Datasheet
R01DS0193EJ0230
Rev.2.30
Jun 19, 2020
RL78/G12
RENESAS MCU
True low-power platform (63 μA/MHz) for the general-purpose applications, with 1.8-V to 5.5-V operation,
2- to 16-Kbyte code flash memory, and 31 DMIPS at 24 MHz
1. OUTLINE
1.1 Features
Ultra-low power consumption technology
VDD = single power supply voltage of 1.8 to 5.5 V which
can operate at a low voltage
HALT mode
STOP mode
SNOOZE mode
RL78 CPU core
CISC architecture with 3-stage pipeline
Minimum instruction execution time: Can be changed
from high speed (0.04167 s: @ 24 MHz operation with
high-speed on-chip oscillator) to ultra-low speed (1 s:
@ 1 MHz operation)
Address space: 1 MB
General-purpose registers: (8-bit register x 8) x 4 banks
On-chip RAM: 256 B to 2 KB
Code flash memory
Code flash memory: 2 to 16 KB
Block size: 1 KB
Prohibition of block erase and rewriting (security
function)
On-chip debug function
DMA (Direct Memory Access) controller Note
2 channels
Number of clocks during transfer between 8/16-bit SFR
and internal RAM: 2 clocks
Multiplier and divider/multiply-accumulator
16 bits x 16 bits = 32 bits (Unsigned or signed)
32 bits x 32 bits = 32 bits (Unsigned)
16 bits x 16 bits + 32 bits = 32 bits (Unsigned or
signed)
Serial interface
CSI
UART
Simplified I2C communication
I2C communication
: 1 to 3 channels
: 1 to 3 channels
: 0 to 3 channels
: 1 channel
Timer
16-bit timer
: 4 to 8 channels
12-bit interval timer : 1 channel
Watchdog timer
: 1 channel (operable with the
dedicated low-speed on-chip
oscillator)
Self-programming (with flash shield window function)
Data flash memory Note
Data flash memory: 2 KB
Back ground operation (BGO): Instructions are
executed from the program memory while rewriting the
data flash memory.
Number of rewrites: 1,000,000 times (TYP.)
Voltage of rewrites: VDD = 1.8 to 5.5 V
High-speed on-chip oscillator
Select from 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz,
4 MHz, 3 MHz, 2 MHz, and 1 MHz
High accuracy: +/- 1.0 % (VDD = 1.8 to 5.5 V, TA = -20
to +85 °C)
Operating ambient temperature
TA = -40 to +85 °C (A: Consumer applications, D:
Industrial applications)
TA = -40 to +105 °C (G: Industrial applications) Note
Power management and reset function
On-chip power-on-reset (POR) circuit
On-chip voltage detector (LVD) (Select interrupt and
reset from 12 levels)
A/D converter
8/10-bit resolution A/D converter (VDD = 1.8 to 5.5 V)
8 to 11 channels, internal reference voltage (1.45 V),
and temperature sensor Note
I/O port
I/O port: 18 to 26
(N-ch open drain I/O [withstand voltage of 6 V]: 2,
N-ch open drain I/O [VDD withstand voltage]: 4 to 9)
Can be set to N-ch open drain, TTL input buffer, and
on-chip pull-up resistor
Different potential interface: Can connect to a 1.8/2.5/3
V device
On-chip key interrupt function
On-chip clock output/buzzer output controller
Others
On-chip BCD (binary-coded decimal) correction circuit
Note Can be selected only in HS (high-speed main)
mode.
Remark The functions mounted depend on the product.
See 1.7 Outline of Functions.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 1 of 108
RL78/G12
1. OUTLINE
Օ ROM, RAM capacities
Code flash
Data flash
RAM
20 pins
24 pins
30 pins
16 KB
2 KB
2 KB
–
–
R5F102AA
–
2 KB
–
1.5 KB
–
12 KB
2KB
1 KB
–
8 KB
2 KB
768 B
–
4 KB
2KB
512 B
–
2 KB
2 KB
–
Notes 1.
256 B
–
R5F1026A
Note 1
R5F1036A
Note 1
R5F10269
Note 1
R5F10369
Note 1
R5F10268
Note 1
R5F10368
Note 1
R5F103AA
R5F1027A
Note 1
–
R5F1037A
Note 1
–
R5F10279
Note 1
R5F102A9
R5F10379
Note 1
R5F103A9
R5F10278
Note 1
R5F102A8
R5F10378
Note 1
R5F103A8
R5F10267
R5F10277
R5F102A7
R5F10367
R5F10377
R5F103A7
R5F10266 Note 2
–
–
R5F10366 Note 2
–
–
This is 640 bytes when the self-programming function or data flash function is used. (For details, see
CHAPTER 3 CPU ARCHITECTURE in the RL78/G12 User’s Manual.)
2.
The self-programming function cannot be used for R5F10266 and R5F10366.
Caution When the flash memory is rewritten via a user program, the code flash area and RAM area are used
because each library is used. When using the library, refer to RL78 Family Flash Self Programming
Library Type01 User's Manual and RL78 Family Data Flash Library Type04 User's Manual.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 2 of 108
RL78/G12
1. OUTLINE
1.2 List of Part Numbers
Figure 1-1. Part Number, Memory Size, and Package of RL78/G12
Product name
Ordering part number R 5 F 1 0 2 A A A x x x S P #V0
Packaging specifications:
#U5, #05, #25: Tray (HWQFN)
#V0, #10, #30: Tray (LSSOP30)
#V5: Tube (LSSOP20)
#15: Tray (TSSOP20)
#35: Tray (TSSOP20), Tube (LSSOP20)
#W5, #45: Embossed Tape (HWQFN)
#X0, #50: Embossed Tape (LSSOP30)
#X5: Embossed Tape (LSSOP20)
#55: Embossed Tape (LSSOP20, TSSOP20)
Package type:
SM : TSSOP, 0.65-mm pitch
SP : LSSOP, 0.65-mm pitch
NA : HWQFN, 0.50-mm pitch
ROM number (Omitted with blank products)
Fields of application:
A : Consumer applications, TA = -40°C to +85°C
D : Industrial applications, TA = -40°C to +85°C
G : Industrial applications, TA = -40°C to +105°C
ROM capacity:
6 :
7:
8:
9 :
A :
2 KB
4 KB
8 KB
12 KB
16 KB
Pin count:
6 : 20-pin
7 : 24-pin
A : 30-pin
RL78/G12 group
102Note 1
103Notes 1, 2
Memory type:
F : Flash memory
Renesas MCU
Renesas semiconductor product
Notes 1.
For details about the differences between the R5F102 products and the R5F103 products of RL78/G12,
see 1.3 Differences between the R5F102 Products and the R5F103 Products.
2.
Products only for “A: Consumer applications (TA = -40 to +85°C)” and “D: Industrial applications (TA = -40 to
+85°C)”
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 3 of 108
RL78/G12
1. OUTLINE
Table 1-1. List of Ordering Part Numbers
Pin
count
Package
Data
flash
Fields of
Application
Note
20
pins
24
pins
20-pin
plastic
LSSOP
(4.4 × 6.5
mm, 0.65mm pitch)
Mounted A
R5F1026AASP, R5F10269ASP, R5F10268ASP,
R5F10267ASP, R5F10266ASP
D
R5F1026ADSP, R5F10269DSP, R5F10268DSP,
R5F10267DSP, R5F10266DSP
G
R5F1026AGSP, R5F10269GSP, R5F10268GSP,
R5F10267GSP, R5F10266GSP
Not
A
mounted
R5F1036AASP, R5F10369ASP, R5F10368ASP,
R5F10367ASP, R5F10366ASP
D
R5F1036ADSP, R5F10369DSP, R5F10368DSP,
R5F10367DSP, R5F10366DSP
#V5, #35, #X5,
#55
PLSP0020JB-A
#V5, #35, #X5,
#55
PLSP0020JB-A
#15, #35, #55
PTSP0020JI-A
Mounted A
Not
A
mounted
R5F1036AASM, R5F10369ASM, R5F10368ASM,
R5F10367ASM, R5F10366ASM
24-pin
plastic
HWQFN
(4 × 4 mm,
0.5-mm
pitch)
Mounted A
R5F1027AANA, R5F10279ANA, R5F10278ANA,
R5F10277ANA
#U5, #W5
PWQN0024KE-A
R5F1027AANA, R5F10279ANA, R5F10278ANA,
R5F10277ANA
#05, #25, #45
PWQN0024KF-A
D
R5F1027ADNA, R5F10279DNA, R5F10278DNA,
R5F10277DNA
#U5, #W5
PWQN0024KE-A
G
R5F1027AGNA, R5F10279GNA, R5F10278GNA,
R5F10277GNA
R5F1027AGNA, R5F10279GNA, R5F10278GNA,
R5F10277GNA
#05, #25, #45
PWQN0024KF-A
R5F1037AANA, R5F10379ANA, R5F10378ANA,
R5F10377ANA
#U5, #W5
PWQN0024KE-A
R5F1037AANA, R5F10379ANA, R5F10378ANA,
R5F10377ANA
#05, #25, #45
PWQN0024KF-A
D
R5F1037ADNA, R5F10379DNA, R5F10378DNA,
R5F10377DNA
#U5, #W5
PWQN0024KE-A
Mounted A
R5F102AAASP, R5F102A9ASP, R5F102A8ASP,
R5F102A7ASP
#V0, #10, #30,
#X0, #50
PLSP0030JB-B
D
R5F102AADSP, R5F102A9DSP, R5F102A8DSP,
R5F102A7DSP
G
R5F102AAGSP, R5F102A9GSP, R5F102A8GSP,
R5F102A7GSP
#V0, #10, #30,
#X0, #50
PLSP0030JB-B
G
30-pin
plastic
LSSOP
(7.62 mm
(300), 0.65mm pitch)
R5F1026AASM, R5F10269ASM, R5F10268ASM,
R5F10267ASM, R5F10266ASM
RENESAS Code
Packaging
Specifications
20-pin
plastic
TSSOP
(4.4 x 6.5
mm, 0.65mm pitch)
Not
A
mounted
30
pins
Ordering Part Number
Product Name
R5F1026AGSM, R5F10269GSM, R5F10268GSM,
R5F10267GSM, R5F10266GSM
Not
A
mounted
R5F103AAASP, R5F103A9ASP, R5F103A8ASP,
R5F103A7ASP
D
R5F103AADSP, R5F103A9DSP, R5F103A8DSP,
R5F103A7DSP
Note For fields of application, see Figure 1-1 Part Number, Memory Size, and Package of RL78/G12.
Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering
part numbers, refer to the target product page of the Renesas Electronics website.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 4 of 108
RL78/G12
1. OUTLINE
1.3 Differences between the R5F102 Products and the R5F103 Products
The following are differences between the R5F102 products and the R5F103 products.
Օ Whether the data flash memory is mounted or not
Օ High-speed on-chip oscillator oscillation frequency accuracy
Օ Number of channels in serial interface
Օ Whether the DMA function is mounted or not
Օ Whether a part of the safety functions are mounted or not
1.3.1 Data Flash
The data flash memory of 2 KB is mounted on the R5F102 products, but not on the R5F103 products.
Product
Data Flash
R5F102 products
2 KB
R5F1026A, R5F1027A, R5F102AA,
R5F10269, R5F10279, R5F102A9,
R5F10268, R5F10278, R5F102A8,
R5F10267, R5F10277, R5F102A7,
R5F10266 Note
R5F103 products
Not mounted
R5F1036A, R5F1037A, R5F103AA,
R5F10369, R5F10379, R5F103A9,
R5F10368, R5F10378 R5F103A8,
R5F10367, R5F10377, R5F103A7,
R5F10366
Note The RAM in the R5F10266 has capacity as small as 256 bytes. Depending on the customer's program
specification, the stack area to execute the data flash library may not be kept and data may not be written to or
erased from the data flash memory.
Caution When the flash memory is rewritten via a user program, the code flash area and RAM area are used
because each library is used. When using the library, refer to RL78 Family Flash Self Programming
Library Type01 User's Manual and RL78 Family Data Flash Library Type04 User's Manual.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 5 of 108
RL78/G12
1. OUTLINE
1.3.2 On-chip oscillator characteristics
(1) High-speed on-chip oscillator oscillation frequency of the R5F102 products
Oscillator
Condition
MIN
MAX
Unit
High-speed on-chip
TA = -20 to +85°C
-1.0
+1.0
%
oscillator oscillation
TA = -40 to -20°C
-1.5
+1.5
frequency accuracy
TA = +85 to +105°C
-2.0
+2.0
(2) High-speed on-chip oscillator oscillation frequency of the R5F103 products
Oscillator
Condition
MIN
MAX
Unit
High-speed on-chip
TA = -40 to + 85°C
-5.0
+5.0
%
oscillator oscillation
frequency accuracy
1.3.3 Peripheral Functions
The following are differences in peripheral functions between the R5F102 products and the R5F103 products.
R5F102 product
RL78/G12
20, 24 pin
30 pin product
product
Serial interface
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
30 pin
product
product
UART
1 channel
3 channels
1 channel
CSI
2 channels
3 channels
1 channel
Simplified I2C
2 channels
3 channels
None
DMA function
Safety function
R5F103 product
20, 24 pin
2 channels
None
CRC operation
Yes
None
RAM guard
Yes
None
SFR guard
Yes
None
Page 6 of 108
RL78/G12
1. OUTLINE
1.4 Pin Configuration (Top View)
1.4.1 20-pin products
● 20-pin plastic LSSOP (4.4 × 6.5 mm, 0.65-mm pitch)
● 20-pin plastic TSSOP (4.4 × 6.5 mm, 0.65-mm pitch)
1
2
3
4
5
6
7
8
9
10
RL78/G12
(Top View)
P20/ANI0/AV REFP
P42/ANI21/SCK01Note/SCL01Note /TI03/TO03
P41/ANI22/SO01Note/SDA01Note/TI02/TO02/INTP1
P40/KR0/TOOL0
P125/KR1/SI01Note /RESET
P137/INTP0
P122/KR2/X2/EXCLK/(TI02)/(INTP2)
P121/KR3/X1/(TI03)/(INTP3)
VSS
VDD
20
19
18
17
16
15
14
13
12
11
P21/ANI1/AV REFM
P22/ANI2
P23/ANI3
P10/ANI16/PCLBUZ0/SCK00/SCL00Note
P11/ANI17/SI00/RxD0/SDA00 Note /TOOLRxD
P12/ANI18/SO00/TxD0/TOOLTxD
P13/ANI19/TI00/TO00/INTP2
P14/ANI20/TI01/TO01/INTP3
P61/KR5/SDAA0/(RxD0)
P60/KR4/SCLA0/(TxD0)
Note Provided only in the R5F102 products.
Remarks 1. For pin identification, see 1.5 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the
RL78/G12 User’s Manual.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 7 of 108
RL78/G12
1. OUTLINE
1.4.2 24-pin products
P23/ANI3
Note
P10/ANI16/PCLBUZ0/SCK00/SCL00
Note
P11/ANI17/SI00/RxD0/SDA00 /TOOLRxD
P12/ANI18/SO00/TxD0/TOOLTxD
P13/ANI19/TO00/INTP2
P14/ANI20/TO01/INTP3
● 24-pin plastic HWQFN (4 × 4 mm, 0.5-mm pitch)
exposed die pad
P22/ANI2
P21/ANI1/AVREFM
P20/ANI0/AVREFP
Note
Note
P42/ANI21/SCK01 /SCL01 /TI03/TO03
Note
Note
P41/ANI22/SO01 /SDA01 /TI02/TO02/INTP1
P40/KR0/TOOL0
18 17 16 15 14 13
12
19
20
11
21 RL78/G12
10
22 (Top View)
9
23
8
24
7
1 2 3 4 5 6
P61/KR5/SDAA0/(RxD0)
P60/KR4/SCLA0/(TxD0)
P03/KR9
Note
Note
P02/KR8/(SCK01) /(SCL01)
Note
Note
P01/KR7/(SO01) /(SDA01)
Note
P00/KR6/(SI01)
Note
P125/KR1/SI01 /RESET
P137/INTP0
P122/KR2/X2/EXCLK/(TI02)/(INTP2)
P121/KR3/X1/(TI03)/(INTP3)
VSS
VDD
INDEX MARK
Note Provided only in the R5F102 products.
Remarks 1. For pin identification, see 1.5 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the
RL78/G12 User’s Manual.
3. It is recommended to connect an exposed die pad to Vss.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 8 of 108
RL78/G12
1. OUTLINE
1.4.3 30-pin products
● 30-pin plastic LSSOP (7.62 mm (300), 0.65-mm pitch)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RL78/G12
(Top View)
P20/ANI0/AVREFP
P01/ANI16/TO00/RxD1Note
P00/ANI17/TI00/TxD1Note
P120/ANI19
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P60/SCLA0
P61/SDAA0
P31/TI03/TO03/INTP4/PCLBUZ0
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P21/ANI1/AVREFM
P22/ANI2
P23/ANI3
P147/ANI18
Note
P10/SCK00/SCL00 /(TI07/TO07)
Note
P11/SI00/RxD0/TOOLRxD/SDA00 /(TI06/TO06)
P12/SO00/TxD0/TOOLTxD/(TI05/TO05)
P13/TxD2Note/SO20Note/(SDAA0)Note/(TI04/TO04)
Note
Note
Note
Note
P14/RxD2 /SI20 /SDA20 /(SCLA0) /(TI03/TO03)
Note
Note
P15/PCLBUZ1/SCK20 /SCL20 /(TI02/TO02)
P16/TI01/TO01/INTP5/(RxD0)
P17/TI02/TO02/(TxD0)
P51/INTP2/SO11Note
P50/INTP1/SI11Note/SDA11Note
Note
Note
P30/INTP3/SCK11 /SCL11
Note Provided only in the R5F102 products.
Caution Connect the REGC pin to VSS via capacitor (0.47 to 1 µF).
Remarks 1. For pin identification, see 1.5 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the
RL78/G12 User’s Manual.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 9 of 108
RL78/G12
1. OUTLINE
1.5 Pin Identification
REGC:
Regulator Capacitance
Analog input
RESET:
Reset
AVREFM:
Analog Reference Voltage Minus
RxD0 to RxD2:
Receive Data
AVREFP:
Analog reference voltage plus
SCK00, SCK01, SCK11,
EXCLK:
External Clock Input
SCK20:
(Main System Clock)
SCL00, SCL01,
ANI0 to ANI3,
ANI16 to ANI22:
Serial Clock Input/Output
INTP0 to INTP5
Interrupt Request From Peripheral
SCL11, SCL20, SCLA0:
KR0 to KR9:
Key Return
SDA00, SDA01, SDA11,
Serial Clock Input/Output
P00 to P03:
Port 0
SDA20, SDAA0:
Serial Data Input/Output
P10 to P17:
Port 1
SI00, SI01, SI11, SI20:
Serial Data Input
P20 to P23:
Port 2
SO00, SO01, SO11,
P30 to P31:
Port 3
SO20:
Serial Data Output
P40 to P42:
Port 4
TI00 to TI07:
Timer Input
P50, P51:
Port 5
TO00 to TO07:
Timer Output
P60, P61:
Port 6
TOOL0:
Data Input/Output for Tool
P120 to P122, P125:
Port 12
TOOLRxD, TOOLTxD:
Data Input/Output for External
P137:
Port 13
P147:
Port 14
PCLBUZ0, PCLBUZ1:
Device
TxD0 to TxD2:
Transmit Data
Programmable Clock Output/
VDD:
Power supply
Buzzer Output
VSS:
Ground
X1, X2:
Crystal Oscillator (Main System
Clock)
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 10 of 108
RL78/G12
1. OUTLINE
1.6 Block Diagram
1.6.1 20-pin products
TAU0 (4ch)
TI00/TO00
ch00
TI01/TO01
ch01
TI02/TO02
ch02
TI03/TO03
ch03
PORT 1
5
P10 to P14
PORT 2
4
P20 to P23
PORT 4
3
P40 to P42
PORT 6
2
P60, P61
PORT 12
3
P121, P122, P125
SAU0 (2ch)
RxD0
TxD0
UART0
Code flash: 16 KB
Data flash: 2 KBNote
SCK00
SI00
SO00
CSI00
SCK01
SI01
SO01
CSI01Note
SCL00
SDA00
IIC00Note
SCL01
SDA01
Note
PORT 13
P137
Buzzer/clock
output control
PCLBUZ0
Interrupt control
RL78
CPU
core
Key return
6ch
6
KR0 to KR5
Interrupt control
4ch
4
INTP0 to INTP3
Note
DMA
2ch
IIC01
RAM
1.5 KB
CRCNote
Window watchdog
timer
TOOL0
Multiplier & divider
multiplyaccumulator
SCLA0
SDAA0
12-bit interval timer
On-chip debug
BCD adjustment
IICA0
Low Speed
On-chip
oscillator
15 kHz
RESET
Clock Generator
+
Reset Generator
Main OSC
1 to 20 MHz
X1 X2/EXCLK
Power-on
reset/voltage
detector
VDD
10-bit A/D converter
11ch
9
ANI2, ANI3, ANI16 to ANI22
ANI0/AVREFP
ANI1/AVREFM
High-Speed
on-chip oscillator
1 to 24 MHz
VSS
TOOL TOOL
TxD RxD
Note Provided only in the R5F102 products.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 11 of 108
RL78/G12
1. OUTLINE
1.6.2 24-pin products
TAU0 (4ch)
TI00/TO00
ch00
TI01/TO01
ch01
TI02/TO02
ch02
TI03/TO03
ch03
Port 0
4
P00 to P03
Port 1
5
P10 to P14
Port 2
4
P20 to P23
Port 4
3
P40 to P42
Port 6
2
P60, P61
Port 12
3
P121, P122, 125
SAU0 (2ch)
RxD0
TxD0
UART0
SCK00
SI00
SO00
CSI00
SCK01
SI01
SO01
Code flash: 16 KB
Note
Data flash: 2 KB
P137
Port 13
Buzzer/clock
output control
CSI01
SCL00
SDA00
IIC00
SCL01
SDA01
IIC01
Note
Note
PCLBUZ0
Interrupt control
RL78
CPU
core
Key return
10ch
10
Interrupt control
4ch
4
Note
RAM
1.5 KB
On-chip debug
BCD adjustment
IICA0
SCLA0
SDAA0
Multiplier &
divider/
multiplyaccumulator
RESET
Clock Generator
+
Reset Generator
Main OSC
1to 20 MHz
X1 X2/EXCLK
Low Speed
On-chip
oscillator
15 KHz
12-bit Interval timer
10-bit
A/D converter
11ch
9
ANI2, ANI3, ANI16 to ANI22
ANI0/AVREFP
ANI1/AVREFM
High-Speed
On-chip
oscillator
1 to 24 MHz
Poer-on
reset/voltage
detector
IICA0
VDD
INTP0 to INTP3
CRCNote
Window watchdog
timer
TOOL0
KR0 to KR9
Note
DMA
2ch
VSS
TOOL TOOL
TxD RxD
Note Provided only in the R5F102 products.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 12 of 108
RL78/G12
1. OUTLINE
1.6.3 30-pin products
TAU (8ch)
TI00
TO00
ch0
TI01/TO01
ch1
TI02/TO02
ch2
Port 0
2
P00, P01
TI03/TO03
ch3
Port 1
8
P10 to P17
(TI04/TO04)
ch4
Port 2
4
P20 to P23
(TI05/TO05)
ch5
Port 3
2
P30, P31
(TI06/TO06)
ch6
(TI07/TO07)
ch7
P40
Port 4
SAU0 (4ch)
RxD0
TxD0
RxD1
TxD1
SCK00
SI00
SO00
SCK11
SI11
SO11
Code flash: 16 KB
Data flash: 2 KBNote
Port 5
2
P50, P51
Port 6
2
P60, P61
Port 12
2
UART0
P120
UART1Note
CSI00
RL78
CPU
core
Port 13
P137
Port 14
P147
Note
DMA
2ch
Note
CSI11
SCL00
SDA00
IIC00
SCL11
SDA11
IIC11
RAM
2 KB
Note
Buzzer/clock
output control
Interrupt control
6ch
Note
CRC
SAU0 (2ch)
RxD2
TxD2
UART2
SCK20
SI20
SO20
CSI20
SCL20
SDA20
IIC20
2
6
PCLBUZ0, PCLBUZ1
INTP0 to INTP5
Note
RESET
Note
Clock Generator
+
Reset Generator
Main OSC
1 to 20 MHz
X1 X2/EXCLK
Window watchdog
timer
Low Speed
On-chip
oscillator
15 KHz
12-bit Interval timer
High-Speed
On-chip
oscillator
1 to 24 MHz
Poer-on
reset/voltage
detector
VDD
TOOL0
P121, P122
Interrupt control
VSS
TOOL TOOL
TxD RxD
10-bit
A/D converter
8ch
6
ANI2, ANI3,
ANI16 to ANI19
ANI0/AVREFP
ANI1/AVREFM
On-chip debug
VOLTAGE
REGULATOR
REGC
BCD adjustment
Multiplier &
divider/
multiplyaccumulator
SCLA0
SDAA0
IICA0
Note Provided only in the R5F102 products.
Remark
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G12
User’s Manual.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 13 of 108
RL78/G12
1. OUTLINE
1.7 Outline of Functions
This outline describes the function at the time when Peripheral I/O redirection register (PIOR) is set to 00H.
(1/2)
Item
20-pin
R5F1026x
Code flash memory
Data flash memory
RAM
24-pin
R5F1036x
R5F1027x
2 KB
R5F102Ax
R5F103Ax
4 to 16 KB
–
2 KB
–
2 KB
512 B to 1.5 KB
Address space
High-speed system clock
R5F1037x
2 to 16 KB Note 1
256 B to 1.5 KB
Main
30-pin
–
512 B to 2KB
1 MB
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
system
HS (High-speed main) mode : 1 to 20 MHz (VDD = 2.7 to 5.5 V),
clock
HS (High-speed main) mode : 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (Low-speed main) mode : 1 to 8 MHz (VDD = 1.8 to 5.5 V)
High-speed on-chip
oscillator clock
HS (High-speed main) mode : 1 to 24 MHz (VDD = 2.7 to 5.5 V),
HS (High-speed main) mode : 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (Low-speed main) mode : 1 to 8 MHz (VDD = 1.8 to 5.5 V)
Low-speed on-chip oscillator clock
15 kHz (TYP)
General-purpose register
(8-bit register × 8) × 4 banks
Minimum instruction execution time
0.04167 µs (High-speed on-chip oscillator clock: fIH = 24 MHz operation)
0.05 µs (High-speed system clock: fMX = 20 MHz operation)
Instruction set
● Data transfer (8/16 bits)
● Adder and subtractor/logical operation (8/16 bits)
● Multiplication (8 bits × 8 bits)
● Rotate, barrel shift, and bit manipulation (set, reset, test, and Boolean operation), etc.
I/O port
Total
CMOS I/O
CMOS input
18
22
26
12
16
21
(N-ch O.D. I/O
(N-ch O.D. I/O
(N-ch O.D. I/O
[VDD withstand voltage]: 4)
[VDD withstand voltage]: 5)
[VDD withstand voltage]: 9)
4
4
3
N-ch open-drain I/O
2
(6 V tolerance)
Timer
16-bit timer
8 channels
Watchdog timer
1 channel
12-bit Interval timer
1 channel
Timer output
Notes 1.
4 channels
4 channels
8 channels
(PWM outputs: 3 Note 3)
(PWM outputs: 7 Notes 2, 3)
The self-programming function cannot be used in the R5F10266 and R5F10366.
2.
The maximum number of channels when PIOR0 is set to 1.
3.
The number of PWM outputs varies depending on the setting of channels in use (the number of masters and
slaves). (See 6.9.3 Operation as multiple PWM output function in the RL78/G12 User’s Manual.)
Caution When the flash memory is rewritten via a user program, the code flash area and RAM area are used
because each library is used. When using the library, refer to RL78 Family Flash Self Programming
Library Type01 User's Manual and RL78 Family Data Flash Library Type04 User's Manual.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 14 of 108
RL78/G12
1. OUTLINE
(2/2)
Item
20-pin
R5F1026x
24-pin
R5F1036x
Clock output/buzzer output
R5F1027x
30-pin
R5F1037x
R5F102Ax
1
R5F103Ax
2
2.44 kHz to 10 MHz: (Peripheral hardware clock: fMAIN = 20 MHz operation)
8/10-bit resolution A/D converter
Serial interface
11 channels
8 channels
[R5F1026x (20-pin), R5F1027x (24-pin)]
● CSI: 2 channels/Simplified I2C: 2 channels/UART: 1 channel
[R5F102Ax (30-pin)]
● CSI: 1 channel/Simplified I2C: 1 channel/UART: 1 channel
● CSI: 1 channel/Simplified I2C: 1 channel/UART: 1 channel
● CSI: 1 channel/Simplified I2C: 1 channel/UART: 1 channel
[R5F1036x (20-pin), R5F1037x (24-pin)]
● CSI: 1 channel/Simplified I2C: 0 channel/UART: 1 channel
[R5F103Ax (30-pin)]
● CSI: 1 channel/Simplified I2C: 0 channel/UART: 1 channel
I2C bus
1 channel
Multiplier and divider/multiply-
● 16 bits × 16 bits = 32 bits (unsigned or signed)
accumulator
● 32 bits × 32 bits = 32 bits (unsigned)
● 16 bits × 16 bits + 32 bits = 32 bits (unsigned or signed)
DMA controller
Vectored interrupt
Internal
sources
External
2 channels
–
2 channels
–
2 channels
–
18
16
18
16
26
19
5
Key interrupt
6
6
10
–
● Reset by RESET pin
Reset
● Internal reset by watchdog timer
● Internal reset by power-on-reset
● Internal reset by voltage detector
● Internal reset by illegal instruction execution
Note
● Internal reset by RAM parity error
● Internal reset by illegal-memory access
Power-on-reset circuit
Voltage detector
● Power-on-reset:
1.51 V (TYP)
● Power-down-reset:
1.50 V (TYP)
● Rising edge : 1.88 to 4.06 V (12 stages)
● Falling edge : 1.84 to 3.98 V (12 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 1.8 to 5.5 V
Operating ambient temperature
TA = –40 to +85°C (A: Consumer applications, D: Industrial applications), TA = –40 to +105°C
(G: Industrial applications)
Note
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 15 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
This chapter describes the following electrical specifications.
Target products A: Consumer applications TA = -40 to +85°C
R5F102xxAxx, R5F103xxAxx
D: Industrial applications TA = -40 to +85°C
R5F102xxDxx, R5F103xxDxx
G: Industrial applications when TA = -40 to +105°C products is used in the range of TA = -40 to +85°C
R5F102xxGxx
Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and
evaluation. Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded when this
function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not
liable for problems occurring when the on-chip debug function is used.
2. The pins mounted depend on the product. Refer to 2.1 Port Functions to 2.2.1 Functions for each
product in the RL78/G12 User’s Manual.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 16 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
2.1 Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply Voltage
Symbols
Conditions
VDD
REGC terminal input
voltageNote1
VIREGC
REGC
Ratings
Unit
–0.5 to + 6.5
V
V
–0.3 to +2
and –0.3 to VDD + 0.3
Note 2
Input Voltage
VI1
Other than P60, P61
VI2
P60, P61 (N-ch open drain)
Output Voltage
VO
Analog input voltage
VAI
IOH1
V
–0.3 to 6.5
V
–0.3 to VDD + 0.3
20-, 24-pin products: ANI0 to ANI3, ANI16 to ANI22
30-pin products: ANI0 to ANI3, ANI16 to ANI19
Output current, high
–0.3 to VDD + 0.3Note 3
Note 3
–0.3 to VDD + 0.3
V
V
and –0.3 to
AVREF(+)+0.3 Notes 3, 4
Per pin
Other than P20 to P23
–40
mA
Total of all pins
All the terminals other than P20 to P23
–170
mA
20-, 24-pin products: P40 to P42
–70
mA
20-, 24-pin products: P00 to P03Note 5,
P10 to P14
30-pin products: P10 to P17, P30, P31,
P50, P51, P147
–100
mA
P20 to P23
–0.5
mA
30-pin products: P00, P01, P40, P120
IOH2
Per pin
Total of all pins
Output current, low
IOL1
IOL2
–2
mA
Per pin
Other than P20 to P23
40
mA
Total of all pins
All the terminals other than P20 to P23
170
mA
20-, 24-pin products: P40 to P42
30-pin products: P00, P01, P40, P120
70
mA
20-, 24-pin products: P00 to P03Note 5,
P10 to P14, P60, P61
30-pin products: P10 to P17, P30, P31,
P50, P51, P60, P61, P147
100
mA
1
mA
Per pin
Total of all pins
P20 to P23
5
mA
Operating ambient
temperature
TA
–40 to +85
°C
Storage temperature
Tstg
–65 to +150
°C
Notes 1.
2.
3.
4.
5.
30-pin product only.
Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF). This value determines the absolute maximum
rating of the REGC pin. Do not use it with voltage applied.
Must be 6.5 V or lower.
Do not exceed AVREF (+) + 0.3 V in case of A/D conversion target pin.
24-pin products only.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
2. AVREF(+) : + side reference voltage of the A/D converter.
3. VSS : Reference voltage
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 17 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
2.2 Oscillator Characteristics
2.2.1 X1 oscillator characteristics
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Resonator
Conditions
MIN.
TYP.
MAX.
X1 clock oscillation
Ceramic resonator /
2.7 V ≤ VDD ≤ 5.5 V
1.0
20.0
frequency (fX)Note
crystal oscillator
1.8 V ≤ VDD < 2.7 V
1.0
8.0
Note
Unit
MHz
Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution
time.
Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the
oscillator characteristics.
Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the
X1 clock oscillation stabilization time using the oscillation stabilization time counter status register
(OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the
oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation
stabilization time with the resonator to be used.
Remark
When using the X1 oscillator, refer to 5.4 System Clock Oscillator in the RL78/G12 User’s Manual.
2.2.2 On-chip oscillator characteristics
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Oscillators
High-speed on-chip oscillator
Parameters
Conditions
MIN.
fIH
TYP.
MAX.
Unit
1
24
MHz
-1.0
+1.0
%
-1.5
+1.5
%
+5.0
%
clock frequency Notes 1, 2
High-speed on-chip oscillator
R5F102 products
clock frequency accuracy
TA = –40 to –20°C
R5F103 products
Low-speed on-chip oscillator
TA = –20 to +85°C
-5.0
fIL
15
kHz
clock frequency
Low-speed on-chip oscillator
-15
+15
%
clock frequency accuracy
Notes 1.
High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H) and bits 0 to 2 of
HOCODIV register.
2.
This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 18 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
2.3 DC Characteristics
2.3.1 Pin characteristics
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Output current, highNote 1
IOH1
(1/4)
Conditions
MIN.
20-, 24-pin products:
Per pin for P00 to P03Note 4,
TYP.
MAX.
Unit
–10.0
mA
Note 2
P10 to P14, P40 to P42
30-pin products:
Per pin for P00, P01, P10 to P17, P30,
P31, P40, P50, P51, P120, P147
20-, 24-pin products:
4.0 V ≤ VDD ≤ 5.5 V
–30.0
mA
Total of P40 to P42
2.7 V ≤ VDD < 4.0 V
–6.0
mA
30-pin products:
1.8 V ≤ VDD < 2.7 V
–4.5
mA
20-, 24-pin products:
4.0 V ≤ VDD ≤ 5.5 V
–80.0
mA
Total of P00 to P03Note 4, P10 to P14
2.7 V ≤ VDD < 4.0 V
–18.0
mA
30-pin products:
1.8 V ≤ VDD < 2.7 V
–10.0
mA
Total of all pins (When duty ≤ 70%Note 3)
–100
mA
Per pin for P20 to P23
–0.1
mA
Total of all pins
–0.4
mA
Total of P00, P01, P40, P120
(When duty ≤ 70% Note 3)
Total of P10 to P17, P30, P31,
P50, P51, P147
(When duty ≤ 70% Note 3)
IOH2
Notes 1.
value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an
output pin.
2.
3.
However, do not exceed the total current value.
The output current value under conditions where the duty factor ≤ 70%.
If duty factor > 70%: The output current value can be calculated with the following expression (where n
represents the duty factor as a percentage).
● Total output current of pins = (IOH × 0.7)/(n × 0.01)
Where n = 80% and IOH = –10.0 mA
Total output current of pins = (–10.0 × 0.7)/(80 × 0.01) –8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
4.
24-pin products only.
Caution P10 to P12 and P41 for 20-pin products, P01, P10 to P12, and P41 for 24-pin products, and P00, P10
to P15, P17, and P50 for 30-pin products do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 19 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Output current, lowNote 1
Symbol
IOL1
(2/4)
Conditions
MIN.
TYP.
MAX.
Unit
20-, 24-pin products:
20.0
mA
Per pin for P00 to P03Note 4,
Note 2
P10 to P14, P40 to P42
30-pin products:
Per pin for P00, P01, P10 to P17, P30,
P31, P40, P50, P51, P120, P147
15.0
Per pin for P60, P61
mA
Note 2
20-, 24-pin products:
4.0 V ≤ VDD ≤ 5.5 V
60.0
mA
Total of P40 to P42
2.7 V ≤ VDD < 4.0 V
9.0
mA
30-pin products:
1.8 V ≤ VDD < 2.7 V
1.8
mA
20-, 24-pin products:
4.0 V ≤ VDD ≤ 5.5 V
80.0
mA
Total of P00 to P03Note 4,
2.7 V ≤ VDD < 4.0 V
27.0
mA
1.8 V ≤ VDD < 2.7 V
5.4
mA
Total of all pins (When duty ≤ 70%Note 3)
140
mA
Per pin for P20 to P23
0.4
mA
Total of all pins
1.6
mA
Total of P00, P01, P40, P120
(When duty ≤ 70% Note 3)
P10 to P14, P60, P61
30-pin products:
Total of P10 to P17, P30, P31, P50,
P51, P60, P61, P147
(When duty ≤ 70% Note 3)
IOL2
Notes 1.
Value of current at which the device operation is guaranteed even if the current flows from an output pin to
the VSS pin.
2.
However, do not exceed the total current value.
3.
The output current value under conditions where the duty factor ≤ 70%.
If duty factor > 70%: The output current value can be calculated with the following expression (where n
represents the duty factor as a percentage).
● Total output current of pins = (IOL × 0.7)/(n × 0.01)
Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
4.
Remark
24-pin products only.
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 20 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Input voltage, high
Symbol
VIH1
(3/4)
Conditions
MIN.
Normal input buffer
20-, 24-pin products: P00 to P03
TYP.
MAX.
Unit
0.8VDD
VDD
V
Note 2
, P10 to P14,
P40 to P42
30-pin products: P00, P01, P10 to P17, P30, P31,
P40, P50, P51, P120, P147
VIH2
4.0 V ≤ VDD ≤ 5.5 V
2.2
VDD
V
20-, 24-pin products: P10, P11 3.3 V ≤ VDD < 4.0 V
2.0
VDD
V
30-pin products: P01, P10,
1.5
VDD
V
0.7VDD
VDD
V
0.7VDD
6.0
V
0.8VDD
VDD
V
0
0.2VDD
V
4.0 V ≤ VDD ≤ 5.5 V
0
0.8
V
20-, 24-pin products: P10, P11 3.3 V ≤ VDD < 4.0 V
0
0.5
V
30-pin products: P01, P10,
0
0.32
V
0
0.3VDD
V
0
0.3VDD
V
0
0.2VDD
V
TTL input buffer
1.8 V ≤ VDD < 3.3 V
P11, P13 to P17
Input voltage, low
VIH3
P20 to P23
VIH4
P60, P61
Note 1
VIH5
P121, P122, P125
VIL1
Normal input buffer
, P137, EXCLK, RESET
20-, 24-pin products: P00 to P03
Note 2
, P10 to P14,
P40 to P42
30-pin products: P00, P01, P10 to P17, P30, P31,
P40, P50, P51, P120, P147
VIL2
TTL input buffer
1.8 V ≤ VDD < 3.3 V
P11, P13 to P17
VIL3
P20 to P23
VIL4
P60, P61
VIL5
Output voltage, high
VOH1
P121, P122, P125
Note 1
, P137, EXCLK, RESET
20-, 24-pin products:
4.0 V ≤ VDD ≤ 5.5 V,
P00 to P03Note 2, P10 to P14,
IOH1 = –10.0 mA
P40 to P42
4.0 V ≤ VDD ≤ 5.5 V,
30-pin products:
IOH1 = –3.0 mA
P00, P01, P10 to P17, P30,
2.7 V ≤ VDD ≤ 5.5 V,
P31, P40, P50, P51, P120,
P147
VDD–1.5
V
VDD–0.7
V
VDD–0.6
V
VDD–0.5
V
VDD–0.5
V
IOH1 = –2.0 mA
1.8 V ≤ VDD ≤ 5.5 V,
IOH1 = –1.5 mA
VOH2
Notes 1.
2.
P20 to P23
IOH2 = –100 µA
20, 24-pin products only.
24-pin products only.
Caution The maximum value of VIH of pins P10 to P12 and P41 for 20-pin products, P01, P10 to P12, and P41
for 24-pin products, and P00, P10 to P15, P17, and P50 for 30-pin products is VDD even in N-ch opendrain mode.
High level is not output in the N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 21 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Output voltage, low
Symbol
VOL1
(4/4)
Conditions
MAX.
Unit
1.3
V
0.7
V
0.6
V
0.4
V
0.4
V
IOL2 = 400 µA
0.4
V
4.0 V ≤ VDD ≤ 5.5 V,
2.0
V
0.4
V
0.4
V
0.4
V
VI = VDD
1
µA
VI = VDD Input port or external
clock input
1
µA
10
µA
–1
µA
–1
µA
–10
µA
100
kΩ
20-, 24-pin products:
4.0 V ≤ VDD ≤ 5.5 V,
P00 to P03Note, P10 to P14,
IOL1 = 20.0 mA
P40 to P42
4.0 V ≤ VDD ≤ 5.5 V,
30-pin products: P00, P01,
IOL1 = 8.5 mA
P10 to P17, P30, P31, P40,
2.7 V ≤ VDD ≤ 5.5 V,
P50, P51, P120, P147
MIN.
TYP.
IOL1 = 3.0 mA
2.7 V ≤ VDD ≤ 5.5 V,
IOL1 = 1.5 mA
1.8 V ≤ VDD ≤ 5.5 V,
IOL1 = 0.6 mA
VOL2
P20 to P23
VOL3
P60, P61
IOL1 = 15.0 mA
4.0 V ≤ VDD ≤ 5.5 V,
IOL1 = 5.0 mA
2.7 V ≤ VDD ≤ 5.5 V,
IOL1 = 3.0 mA
1.8 V ≤ VDD ≤ 5.5 V,
IOL1 = 2.0 mA
Input leakage current,
ILIH1
high
Other than P121,
P122
ILIH2
P121, P122
(X1, X2/EXCLK)
When resonator
connected
Input leakage current,
ILIL1
Other than P121,
VI = VSS
P122
low
ILIL2
P121, P122
VI = VSS Input port or external
(X1, X2/EXCLK)
clock input
When resonator
connected
On-chip pull-up
RU
20-, 24-pin products:
VI = VSS, input port
10
20
P00 to P03Note, P10 to P14,
resistance
P40 to P42, P125, RESET
30-pin products: P00, P01,
P10 to P17, P30, P31, P40,
P50, P51, P120, P147
Note
24-pin products only.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 22 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
2.3.2 Supply current characteristics
(1) 20-, 24-pin products
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
IDD1
Supply
currentNote 1
(1/2)
Conditions
MIN.
Note 3
Operating HS(High-speed fIH = 24 MHz
mode
Basic
main) modeNote 4
VDD = 5.0 V
1.5
operation VDD = 3.0 V
1.5
Normal
3.3
5.0
3.3
5.0
fIH = 8 MHzNote 3
VDD = 5.0 V
2.5
3.7
VDD = 3.0 V
2.5
3.7
VDD = 3.0 V
1.2
1.8
main) modeNote 4
VDD = 2.0 V
1.2
1.8
HS(High-speed fMX = 20 MHzNote 2,
Square wave input
2.8
4.4
main) modeNote4 VDD = 5.0 V
Resonator connection
3.0
4.6
Square wave input
2.8
4.4
Resonator connection
3.0
4.6
Square wave input
1.8
2.6
Resonator connection
1.8
2.6
Square wave input
1.8
2.6
Resonator connection
1.8
2.6
Square wave input
1.1
1.7
Resonator connection
1.1
1.7
Square wave input
1.1
1.7
Resonator connection
1.1
1.7
Note 2
fMX = 20 MHz
,
VDD = 3.0 V
Note 2
fMX = 10 MHz
,
VDD = 5.0 V
Note 2
fMX = 10 MHz
,
VDD = 3.0 V
LS(Low-speed
Note 2
fMX = 8 MHz
,
main) modeNote 4 VDD = 3.0 V
Note 2
fMX = 8 MHz
,
VDD = 2.0 V
Unit
mA
VDD = 5.0 V
fIH = 16 MHz
Notes 1.
MAX.
operation VDD = 3.0 V
Note 3
LS(Low-speed
TYP.
mA
mA
mA
mA
mA
mA
mA
mA
mA
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,
not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
2.
When high-speed on-chip oscillator clock is stopped.
3.
When high-speed system clock is stopped
4.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS (High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz
LS (Low speed main) mode: VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz
Remarks 1.
fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH: high-speed on-chip oscillator clock frequency
3. Temperature condition of the TYP. value is TA = 25°C.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 23 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
(1) 20-, 24-pin products
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
Note 2
DD2
Supply
(2/2)
I
current Note 1
HALT
HS (High-speed
mode
main) modeNote 6
LS (Low-speed
MIN.
fIH = 24 MHz
Note 4
fIH = 16 MHz
Note 4
fIH = 8 MHz
Note 4
main) modeNote 6
VDD = 5.0 V
440
1210
µA
VDD = 3.0 V
440
1210
VDD = 5.0 V
400
950
VDD = 3.0 V
400
950
VDD = 3.0 V
270
542
VDD = 2.0 V
270
542
fMX = 20 MHzNote 3,
Square wave input
280
1000
VDD = 5.0 V
Resonator connection
450
1170
fMX = 20 MHzNote 3,
Square wave input
280
1000
VDD = 3.0 V
Resonator connection
450
1170
Square wave input
190
590
Resonator connection
260
660
Square wave input
190
590
Resonator connection
260
660
Square wave input
110
360
Resonator connection
150
416
Square wave input
110
360
Resonator connection
150
416
fMX = 10 MHz
Note 3
,
Note 3
,
VDD = 3.0 V
LS (Low-speed
fMX = 8 MHz
main) modeNote 6
VDD = 3.0 V
fMX = 8 MHz
Note 3
Note 3
,
,
VDD = 2.0 V
Notes 1.
Unit
main) modeNote 6
VDD = 5.0 V
I
MAX.
HS (High-speed
fMX = 10 MHz
Note 5
DD3
TYP.
STOP
TA = –40°C
0.19
0.50
mode
TA = +25°C
0.24
0.50
TA = +50°C
0.32
0.80
TA = +70°C
0.48
1.20
TA = +85°C
0.74
2.20
µA
µA
µA
µA
µA
µA
µA
µA
µA
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,
not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
2.
During HALT instruction execution by flash memory.
3.
When high-speed on-chip oscillator clock is stopped.
4.
When high-speed system clock is stopped.
5.
Not including the current flowing into the 12-bit interval timer and watchdog timer.
6.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS (High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz
LS (Low speed main) mode: VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz
Remarks 1.
fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH: high-speed on-chip oscillator clock frequency
3. Except temperature condition of the TYP. value is TA = 25°C, other than STOP mode
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 24 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
(2) 30-pin products
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Supply
Symbol
(1/2)
Conditions
Operating HS (High-speed
IDD1
currentNote 1
mode
MIN.
Note 3
Basic
fIH = 24 MHz
main) modeNote 4
1.5
Normal
VDD = 5.0 V
operation VDD = 3.0 V
3.7
5.5
3.7
5.5
VDD = 5.0 V
2.7
4.0
VDD = 3.0 V
2.7
4.0
VDD = 3.0 V
1.2
1.8
VDD = 2.0 V
1.2
1.8
fIH = 16 MHz
fIH = 8 MHzNote 3
main) mode Note 4
1.5
fMX = 20 MHzNote 2,
Square wave input
3.0
4.6
main) mode Note 4
VDD = 5.0 V
Resonator connection
3.2
4.8
Square wave input
3.0
4.6
Resonator connection
3.2
4.8
Square wave input
1.9
2.7
Resonator connection
1.9
2.7
Square wave input
1.9
2.7
Resonator connection
1.9
2.7
Square wave input
1.1
1.7
Resonator connection
1.1
1.7
Square wave input
1.1
1.7
Resonator connection
1.1
1.7
fMX = 20 MHz
,
VDD = 3.0 V
Note 2
fMX = 10 MHz
,
VDD = 5.0 V
Note 2
fMX = 10 MHz
,
VDD = 3.0 V
Note 2
LS (Low-speed
fMX = 8 MHz
main) mode Note 4
VDD = 3.0 V
,
Note 2
fMX = 8 MHz
,
VDD = 2.0 V
Unit
mA
HS (High-speed
Note 2
Notes 1.
MAX.
VDD = 5.0 V
operation VDD = 3.0 V
Note 3
LS (Low-speed
TYP.
mA
mA
mA
mA
mA
mA
mA
mA
mA
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,
not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
2.
When high-speed on-chip oscillator clock is stopped.
3.
When high-speed system clock is stopped
4.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS (High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz
LS (Low speed main) mode: VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz
Remarks 1.
fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH: high-speed on-chip oscillator clock frequency
3. Temperature condition of the TYP. value is TA = 25°C.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 25 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
(2) 30-pin products
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
Note 2
DD2
Supply
(2/2)
I
currentNote 1
HALT
HS (High-speed
mode
main) mode Note 6
LS (Low-speed
MIN.
fIH = 24 MHz
Note 4
fIH = 16 MHz
Note 4
fIH = 8 MHz
Note 4
main) modeNote 6
VDD = 5.0 V
440
1280
µA
VDD = 3.0 V
440
1280
VDD = 5.0 V
400
1000
VDD = 3.0 V
400
1000
VDD = 3.0 V
260
530
VDD = 2.0 V
260
530
fMX = 20 MHzNote 3,
Square wave input
280
1000
VDD = 5.0 V
Resonator connection
450
1170
fMX = 20 MHzNote 3,
Square wave input
280
1000
VDD = 3.0 V
Resonator connection
450
1170
Square wave input
190
600
Resonator connection
260
670
Square wave input
190
600
Resonator connection
260
670
Square wave input
95
330
Resonator connection
145
380
Square wave input
95
330
Resonator connection
145
380
fMX = 10 MHz
Note 3
,
Note 3
,
VDD = 3.0 V
LS (Low-speed
fMX = 8 MHz
main) modeNote 6
VDD = 3.0 V
fMX = 8 MHz
Note 3
,
Note 3
,
VDD = 2.0 V
Notes 1.
Unit
main) modeNote 6
VDD = 5.0 V
I
MAX.
HS (High-speed
fMX = 10 MHz
Note 5
DD3
TYP.
STOP
TA = –40°C
0.18
0.50
mode
TA = +25°C
0.23
0.50
TA = +50°C
0.30
1.10
TA = +70°C
0.46
1.90
TA = +85°C
0.75
3.30
µA
µA
µA
µA
µA
µA
µA
µA
µA
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,
not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
2.
During HALT instruction execution by flash memory.
3.
When high-speed on-chip oscillator clock is stopped.
4.
When high-speed system clock is stopped.
5.
Not including the current flowing into the 12-bit interval timer and watchdog timer.
6.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS (High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz
LS (Low speed main) mode: VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz
Remarks 1.
fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH: high-speed on-chip oscillator clock frequency
3. Except STOP mode, temperature condition of the TYP. value is TA = 25°C.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 26 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
(3) Peripheral functions (Common to all products)
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Low-speed
Symbol
IFIL
Conditions
MIN.
Note 1
TYP.
MAX.
Unit
0.20
µA
0.02
µA
0.22
µA
onchip oscillator
operating current
12-bit interval
ITMKA
timer operating
Notes 1, 2, 3
current
Watchdog timer
IWDT
operating current
Notes 1, 2, 4
A/D converter
operating current
IADCNotes 1, 5
fIL = 15 kHz
When conversion at
maximum speed
Normal mode, AVREFP = VDD = 5.0 V
1.30
1.70
mA
Low voltage mode, AVREFP = VDD = 3.0 V
0.50
0.70
mA
A/D converter
IADREF Note 1
reference voltage
operating current
75.0
µA
Temperature
sensor operating
current
ITMPS Note 1
75.0
µA
LVD operating
ILVD Notes 1, 6
0.08
µA
IFSP Notes 1, 8
2.00
12.20
mA
IBGO Notes 1, 7
2.00
12.20
mA
The mode is performed Note 9
0.50
0.60
mA
The A/D conversion operations are
1.20
1.44
mA
0.70
0.84
mA
current
Selfprogramming
operating current
BGO operating
current
ISNOZ Note 1
SNOOZE
ADC operation
operating current
performed, Low voltage mode,
AVREFP = VDD = 3.0 V
CSI/UART operation
Notes 1. Current flowing to the VDD.
2. When high speed on-chip oscillator and high-speed system clock are stopped.
3. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip
oscillator). The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3, and IFIL and ITMKA when
the 12-bit interval timer operates.
4. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator).
The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer
operates.
5. Current flowing only to the A/D converter. The current value of the RL78 microcontrollers is the sum of IDD1 or
IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.
6. Current flowing only to the LVD circuit. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or
IDD3 and ILVD when the LVD circuit operates.
7. Current flowing only during data flash rewrite.
8. Current flowing only during self programming.
9. For shift time to the SNOOZE mode, see 17.3.3 SNOOZE mode in the RL78/G12 User’s Manual.
Remarks 1. fIL:
Low-speed on-chip oscillator clock frequency
2. Temperature condition of the TYP. value is TA = 25°C
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 27 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
2.4 AC Characteristics
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Items
Instruction cycle (minimum
Symbol
TCY
instruction execution time)
Conditions
MIN.
TYP.
MAX.
Unit
Main system
HS (High-
2.7 V ≤ VDD ≤ 5.5 V
0.04167
1
µs
clock (fMAIN)
speed main)
2.4 V ≤ VDD < 2.7 V
0.0625
1
µs
operation
mode
1.8 V ≤ VDD ≤ 5.5 V
0.125
1
µs
LS (Lowspeed main)
mode
During self
HS (High-
2.7 V ≤ VDD ≤ 5.5 V
0.04167
1
µs
programming
speed main)
2.4 V ≤ VDD < 2.7 V
0.0625
1
µs
1.8 V ≤ VDD ≤ 5.5 V
0.125
1
µs
2.7 V ≤ VDD ≤ 5.5 V
1.0
20.0
MHz
2.4 V ≤ VDD < 2.7 V
1.0
16.0
MHz
1.8 V ≤ VDD < 2.4 V
1.0
8.0
MHz
2.7 V ≤ VDD ≤ 5.5 V
24
ns
2.4 V ≤ VDD < 2.7 V
30
ns
1.8 V ≤ VDD < 2.4 V
60
ns
1/fMCK +
ns
mode
LS (Lowspeed main)
mode
External main system clock
fEX
frequency
External main system clock
tEXH, tEXL
input high-level width, lowlevel width
TI00 to TI07 input high-level
tTIH, tTIL
width, low-level width
TO00 to TO07 output
10
fTO
frequency
PCLBUZ0, or PCLBUZ1
fPCL
output frequency
INTP0 to INTP5 input high-
4.0 V ≤ VDD ≤ 5.5 V
12
MHz
2.7 V ≤ VDD < 4.0 V
8
MHz
1.8 V ≤ VDD < 2.7 V
4
MHz
4.0 V ≤ VDD ≤ 5.5 V
16
MHz
2.7 V ≤ VDD < 4.0 V
8
MHz
1.8 V ≤ VDD < 2.7 V
4
MHz
tINTH, tINTL
1
µs
tKR
250
ns
tRSL
10
µs
level width, low-level width
KR0 to KR9 input available
width
RESET low-level width
Remark
fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the timer clock select register 0 (TPS0) and the CKS0n bit of timer mode
register 0n (TMR0n). n: Channel number (n = 0 to 7))
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 28 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
Minimum Instruction Execution Time during Main System Clock Operation
TCY vs VDD (HS (high-speed main) mode)
10
Cycle time TCY [µs]
1.0
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
0.1
0.0625
0.04167
0.01
0
1.0
2.0
3.0
2.4 2.7
4.0
5.0
6.0
5.5
Supply voltage VDD [V]
TCY vs VDD (LS (low-speed main) mode)
Cycle time TCY [µs]
10
1.0
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
0.125
0.1
0.01
0
1.0
2.0
1.8
3.0
4.0
5.0 5.5 6.0
Supply voltage VDD [V]
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 29 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
AC Timing Test Point
VIH/VOH
VIL/VOL
VIH/VOH
Test points
VIL/VOL
External Main System Clock Timing
1/fEX
tEXL
tEXH
EXCLK
TI/TO Timing
tTIH
tTIL
TI00 to TI07
1/fTO
TO00 to TO07
Interrupt Request Input Timing
tINTH
tINTL
INTP0 to INTP5
Key Interrupt Input Timing
tKR
KR0 to KR9
RESET Input Timing
tRSL
RESET
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 30 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
2.5 Peripheral Functions Characteristics
AC Timing Test Point
VIH/VOH
VIH/VOH
Test points
VIL/VOL
VIL/VOL
2.5.1 Serial array unit
(1) During communication at same potential (UART mode)
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
LS (low-speed
main) Mode
main) Mode
MIN.
Transfer rate
Note 1
Theoretical value of the maximum transfer rate
fCLK = fMCK
Notes 1.
2.
MAX.
MIN.
Unit
MAX.
fMCK/6
fMCK/6
bps
4.0
1.3
Mbps
Note 2
Transfer rate in the SNOOZE mode is 4800 bps only.
The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V)
16 MHz (2.4 V ≤ VDD ≤ 5.5 V)
LS (low-speed main) mode: 8 MHz (1.8 V ≤ VDD ≤ 5.5 V)
Caution
Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
UART mode connection diagram (during communication at same potential)
TxDq
Rx
RL78
microcontroller
User's device
RxDq
Tx
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Remarks 1.
2.
q: UART number (q = 0 to 2), g: PIM, POM number (g = 0, 1)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial
mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10, 11))
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 31 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
(2) During communication at same potential (CSI mode) (master mode, SCK00... internal clock output,
corresponding CSI00 only)
(TA = –40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
LS (low-speed main)
Mode
Mode
MIN.
tKCY1
tKCY1 ≥ 2/fCLK
SCK00 high-/low-
tKH1,
level width
tKL1
SI00 setup time
tSIK1
SCK00 cycle time
(to SCK00↑) Note 1
MIN.
MAX.
83.3
250
ns
4.0 V ≤ VDD ≤ 5.5 V
tKCY1/2–7
tKCY1/2–50
ns
2.7 V ≤ VDD ≤ 5.5 V
tKCY1/2–10
tKCY1/2–50
ns
4.0 V ≤ VDD ≤ 5.5 V
23
110
ns
2.7 V ≤ VDD ≤ 5.5 V
33
110
ns
10
10
ns
tKSI1
SI00 hold time
MAX.
Unit
(from SCK00↑) Note 2
tKSO1
Delay time from
C = 20 pF Note 4
10
10
ns
SCK00↓ to SO00
output Note 3
Notes 1.
When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The SI00 setup time becomes “to
SCK00↓” when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0.
2.
When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The SI00 hold time becomes “from
SCK00↓” when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0.
3.
When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The delay time to SO00 output becomes
4.
C is the load capacitance of the SCK00 and SO00 output lines.
“from SCK00↑” when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0.
Caution Select the normal input buffer for the SI00 pin and the normal output mode for the SO00 and SCK00
pins by using port input mode register 1 (PIM1) and port output mode register 1 (POM1).
Remarks 1. This specification is valid only when CSI00’s peripheral I/O redirect function is not used.
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register 0 (SPS0) and the CKS00 bit of serial mode
register 00 (SMR00).)
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 32 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
(3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
LS (low-speed
main) Mode
main) Mode
MIN.
SCKp cycle time
tKCY1
SCKp high-/low-level width
SIp setup time (to SCKp↑)
MIN.
MAX.
2.7 V ≤ VDD ≤ 5.5 V
167
500
ns
2.4 V ≤ VDD ≤ 5.5 V
250
500
ns
1.8 V ≤ VDD ≤ 5.5 V
–
500
ns
tKH1,
4.0 V ≤ VDD ≤ 5.5 V
tKCY1/2–12
tKCY1/2–50
ns
tKL1
2.7 V ≤ VDD ≤ 5.5 V
tKCY1/2–18
tKCY1/2–50
ns
2.4 V ≤ VDD ≤ 5.5 V
tKCY1/2–38
tKCY1/2–50
ns
1.8 V ≤ VDD ≤ 5.5 V
–
tKCY1/2–50
ns
4.0 V ≤ VDD ≤ 5.5 V
44
110
ns
2.7 V ≤ VDD ≤ 5.5 V
44
110
ns
2.4 V ≤ VDD ≤ 5.5 V
75
110
ns
1.8 V ≤ VDD ≤ 5.5 V
–
110
ns
19
19
ns
tSIK1
Note 1
SIp hold time
tKCY1 ≥ 4/fCLK
MAX.
Unit
tKSI1
(from SCKp↑) Note 2
Delay time from SCKp↓ to
SOp output
tKSO1
C = 30 pF Note 4
25
25
ns
Note 3
Notes 1.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
4.
C is the load capacitance of the SCKp and SOp output lines.
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp and SCKp pins
by using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1,
POM4).
Remarks 1. p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3: “1, 3” is
only for the R5F102 products)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3: “1, 3” is only for the
R5F102 products.))
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 33 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
LS (low-speed main)
main) Mode
Mode
MIN.
SCKp cycle time
Note 5
tKCY2
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD ≤ 5.5 V
20 MHz < fMCK
MAX.
MIN.
Unit
MAX.
8/fMCK
–
ns
fMCK ≤ 20 MHz
6/fMCK
6/fMCK
ns
16 MHz < fMCK
8/fMCK
–
ns
fMCK ≤ 16 MHz
6/fMCK
6/fMCK
ns
6/fMCK
6/fMCK
ns
and 500
and 500
–
6/fMCK
2.4 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD ≤ 5.5 V
ns
and 750
SCKp high-/low-level
tKH2,
4.0 V ≤ VDD ≤ 5.5 V
tKCY2/2–7
tKCY2/2–7
ns
width
tKL2
2.7 V ≤ VDD ≤ 5.5 V
tKCY2/2–8
tKCY2/2–8
ns
2.4 V ≤ VDD ≤ 5.5 V
tKCY2/2–18
tKCY2/2–18
ns
1.8 V ≤ VDD ≤ 5.5 V
–
tKCY2/2–18
ns
2.7 V ≤ VDD ≤ 5.5 V
1/fMCK + 20
1/fMCK + 30
ns
2.4 V ≤ VDD ≤ 5.5 V
1/fMCK + 30
1/fMCK + 30
ns
1.8 V ≤ VDD ≤ 5.5 V
–
1/fMCK + 30
ns
1/fMCK + 31
1/fMCK + 31
ns
tSIK2
SIp setup time
(to SCKp↑) Note 1
tKSI2
SIp hold time
(from SCKp↑) Note 2
Delay time from
tKSO2
C = 30 pF Note 4
2.7 V ≤ VDD ≤ 5.5 V
SCKp↓ to
SOp output Note 3
2.4 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD ≤ 5.5 V
2/fMCK +
2/fMCK +
44
110
2/fMCK +
2/fMCK +
75
110
–
2/fMCK +
ns
ns
ns
110
Notes 1.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
4.
C is the load capacitance of the SOp output lines.
5.
Transfer rate in the SNOOZE mode: MAX. 1 Mbps.
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the normal input buffer for the SIp and SCKp pins and the normal output mode for the SOp pin
by using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1,
POM4).
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 34 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
CSI mode connection diagram (during communication at same potential)
SCKp
RL78
microcontroller
SCK
SIp
SO User's device
SOp
SI
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
t KCY1, 2
t KL1, 2
t KH1, 2
SCKp
t SIK1, 2
SIp
t KSI1, 2
Input data
t KSO1, 2
SOp
Output data
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1, 2
tKH1, 2
tKL 1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Output data
(Remarks are listed on the next page.)
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 35 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
Remarks 1.
p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3: “1, 3” is
only for the R5F102 products.)
2.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3: “1, 3” is only for the
R5F102 products.))
(5) During communication at same potential (simplified I2C mode)
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
Unit
LS (low-speed main) Mode
MIN.
SCLr clock frequency
fSCL
1.8 V ≤ VDD ≤ 5.5 V,
MAX.
400 Note 1
kHz
300 Note 1
kHz
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
Hold time when SCLr = “L”
tLOW
1.8 V ≤ VDD ≤ 5.5 V,
1150
ns
1550
ns
1150
ns
1550
ns
1/fMCK + 145 Note 2
ns
1/fMCK + 230 Note 2
ns
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
Hold time when SCLr = “H”
tHIGH
1.8 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
Data setup time (reception)
tSU:DAT
1.8 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
Data hold time (transmission)
tHD:DAT
1.8 V ≤ VDD ≤ 5.5 V,
0
355
ns
0
405
ns
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
Notes 1.
2.
The value must be equal to or less than fMCK/4.
Set tSU:DAT so that it will not exceed the hold time when SCLr = “L” or SCLr = “H”.
Caution Select the N-ch open drain output (VDD tolerance) mode for SDAr by using port output mode register
h (POMh).
(Remarks are listed on the next page.)
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 36 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
Simplified I2C mode connection diagram (during communication at same potential)
VDD
Rb
SDAr
SDA
RL78
microcontroller
User's device
SCLr
SCL
Simplified I2C mode serial transfer timing (during communication at same potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD:DAT
Remarks 1.
tSU:DAT
Rb [Ω]:Communication line (SDAr) pull-up resistance
Cb [F]: Communication line (SCLr, SDAr) load capacitance
2.
r: IIC number (r = 00, 01, 11, 20), h: = POM number (h = 0, 1, 4, 5)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial
mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (0, 1, 3))
4.
Simplified I2C mode is supported only by the R5F102 products.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 37 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode)
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Transfer
rate Note4
Conditions
Reception
HS (high-speed
main) Mode
LS (low-speed
main) Mode
MIN.
MIN.
MAX.
Unit
MAX.
4.0 V ≤ VDD ≤ 5.5 V,
fMCK/6
fMCK/6
2.7 V ≤ Vb ≤ 4.0 V
Note1
Note1
4.0
1.3
Mbps
2.7 V ≤ VDD < 4.0 V,
fMCK/6
fMCK/6
bps
2.3 V ≤ Vb ≤ 2.7 V
Note1
Note1
4.0
1.3
Mbps
bps
Theoretical value of the maximum
transfer rate
fMCK = fCLKNote3
Theoretical value of the maximum
transfer rate
bps
fMCK = fCLKNote3
1.8 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
fMCK/6
fMCK/6
Notes1, 2
Notes1, 2
4.0
1.3
Mbps
Note4
Note4
bps
Mbps
Theoretical value of the maximum
transfer rate
fMCK = fCLKNote3
Transmission
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
Theoretical value of the maximum
transfer rate
Cb = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V
2.7 V ≤ VDD < 4.0 V,
2.8
2.8
Note5
Note5
Note6
Note6
bps
Mbps
2.3 V ≤ Vb ≤ 2.7 V,
Theoretical value of the maximum
transfer rate
Cb = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V
1.8 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
1.2
1.2
Note7
Note7
Notes
2, 8
Notes
2, 8
bps
0.43
0.43
Mbps
Note9
Note9
Theoretical value of the maximum
transfer rate
Cb = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V
Notes 1.
Transfer rate in the SNOOZE mode is 4800 bps only.
2.
Use it with VDD ≥ Vb.
3.
The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V)
16 MHz (2.4 V ≤ VDD ≤ 5.5 V)
LS (low-speed main) mode:
4.
8 MHz (1.8 V ≤ VDD ≤ 5.5 V)
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V ≤ VDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V
1
Maximum transfer rate =
2.2
{–Cb × Rb × ln (1 – Vb )} × 3
[bps]
1
2.2
Transfer rate × 2 – {–Cb × Rb × ln (1 – Vb )}
Baud rate error (theoretical value) =
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 38 of 108
RL78/G12
5.
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer.
6.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ VDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V
1
Maximum transfer rate =
2.0
{–Cb × Rb × ln (1 – Vb )} × 3
[bps]
2.0
1
Transfer rate × 2 – {–Cb × Rb × ln (1 – Vb )}
Baud rate error (theoretical value) =
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
7.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer.
8.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
1
Maximum transfer rate =
1.5
{–Cb × Rb × ln (1 – Vb )} × 3
[bps]
1.5
1
Transfer rate × 2 – {–Cb × Rb × ln (1 – Vb )}
Baud rate error (theoretical value) =
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
9.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 8 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for
the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg).
For VIH and VIL, see the DC characteristics with TTL input buffer selected.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 39 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
UART mode connection diagram (during communication at different potential)
Vb
Rb
TxDq
Rx
RL78
microcontroller
User's device
RxDq
Tx
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Remarks 1. Rb[Ω]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance,
Vb[V]: Communication line voltage
2. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10, 11))
4. UART0 of the 20- and 24-pin products supports communication at different potential only when the
peripheral I/O redirection function is not used.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 40 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
(7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCK00... internal clock output,
corresponding CSI00 only)
(TA = –40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
LS (low-speed
main) Mode
main) Mode
MIN.
SCK00 cycle time
tKCY1
tKCY1 ≥ 2/fCLK
4.0 V ≤ VDD ≤ 5.5 V,
MAX.
MIN.
Unit
MAX.
200
1150
ns
300
1150
ns
tKCY1/2 –
tKCY1/2 –
ns
50
50
tKCY1/2 –
tKCY1/2 –
120
120
tKCY1/2 –
tKCY1/2 –
7
50
tKCY1/2 –
tKCY1/2 –
Cb = 20 pF, Rb = 2.7 kΩ
10
50
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
58
479
ns
121
479
ns
10
10
ns
10
10
ns
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SCK00 high-level width
tKH1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SCK00 low-level width
tKL1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
SI00 setup time
tSIK1
(to SCK00↑) Note 1
ns
ns
ns
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SI00 hold time
tKSI1
(from SCK00↑) Note 1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
Delay time from SCK00↓
tKSO1
to SO00 output Note 1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
60
60
ns
130
130
ns
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SI00 setup time
tSIK1
(to SCK00↓) Note 2
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
23
110
ns
33
110
ns
10
10
ns
10
10
ns
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SI00 hold time
tKSI1
(from SCK00↓) Note 2
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
Delay time from SCK00↑
tKSO1
to SO00 output Note 2
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
10
10
ns
10
10
ns
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
(Notes, Caution, and Remarks are listed on the next page.)
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 41 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
Notes 1.
When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1
2.
When DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0.
Caution Select the TTL input buffer for the SI00 pin and the N-ch open drain output (VDD tolerance) mode for
the SO00 pin and SCK00 pin by using port input mode register 1 (PIM1) and port output mode
register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
Remarks 1. Rb [Ω]:Communication line (SCK00, SO00) pull-up resistance, Cb [F]: Communication line (SCK00, SO00)
load capacitance, Vb [V]: Communication line voltage
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register 0 (SPS0) and the CKS00 bit of serial mode
register 00 (SMR00).)
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 42 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output) (1/3)
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
LS (low-speed main)
Mode
Mode
MIN.
SCKp cycle time
tKCY1
tKCY1 ≥ 4/fCLK
4.0 V ≤ VDD ≤ 5.5 V,
MAX.
MIN.
Unit
MAX.
300
1150
ns
500
1150
ns
1150
1150
ns
tKCY1/2 –75
tKCY1/2–75
ns
tKCY1/2 –170
tKCY1/2–170
ns
tKCY1/2 –458
tKCY1/2–458
ns
tKCY1/2 –12
tKCY1/2–50
ns
tKCY1/2 –18
tKCY1/2–50
ns
tKCY1/2 –50
tKCY1/2–50
ns
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Note
,
Cb = 30 pF, Rb = 5.5 kΩ
SCKp high-level width
tKH1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note,
Cb = 30 pF, Rb = 5.5 kΩ
SCKp low-level width
tKL1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note,
Cb = 30 pF, Rb = 5.5 kΩ
Note Use it with VDD ≥ Vb.
Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for
the SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode
register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
2. CSI01 and CSI11 cannot communicate at different potential.
Remarks 1. Rb [Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SCKp, SOp)
load capacitance, Vb [V]: Communication line voltage
2. p: CSI number (p = 00, 20)
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 43 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output) (2/3)
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
LS (low-speed
main) Mode
main) Mode
MIN.
tSIK1
SIp setup time
(to SCKp↑) Note 1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
MAX.
MIN.
Unit
MAX.
81
479
ns
177
479
ns
479
479
ns
19
19
ns
19
19
ns
19
19
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 kΩ
tKSI1
SIp hold time
(from SCKp↑)
Note 1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 kΩ
tKSO1
Delay time from
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
100
100
ns
195
195
ns
483
483
ns
Cb = 30 pF, Rb = 1.4 kΩ
SCKp↓ to
SOp output Note 1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 kΩ
Notes 1.
2.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
Use it with VDD ≥ Vb.
(Cautions and Remarks are listed on the next page.)
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 44 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output) (3/3)
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
LS (low-speed
main) Mode
main) Mode
MIN.
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
tSIK1
SIp setup time
(to SCKp↓) Note 1
MAX.
MIN.
Unit
MAX.
44
110
ns
44
110
ns
110
110
ns
19
19
ns
19
19
ns
19
19
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 kΩ
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
tKSI1
SIp hold time
(from SCKp↓) Note 1
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 kΩ
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
tKSO1
Delay time from
25
25
ns
25
25
ns
25
25
ns
Cb = 30 pF, Rb = 1.4 kΩ
SCKp↑ to
SOp output Note 1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 kΩ
Notes 1.
2.
When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Use it with VDD ≥ Vb.
Cautions 1.
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode
for the SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode
register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
2.
Remarks 1.
CSI01 and CSI11 cannot communicate at different potential.
Rb [Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SCKp, SOp)
load capacitance, Vb [V]: Communication line voltage
2.
p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0)
CSI mode connection diagram (during communication at different potential)
Vb
Vb
Rb
SCKp
RL78
microcontroller
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Rb
SCK
SIp
SO
SOp
SI
User's device
Page 45 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1)
t KCY1
t KL1
t KH1
SCKp
t SIK1
SIp
t KSI1
Input data
t KSO1
SOp
Output data
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
t KCY1
t KL1
t KH1
SCKp
t SIK1
SIp
t KSI1
Input data
t KSO1
SOp
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Output data
Page 46 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
(9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
LS (low-speed main)
Mode
Mode
MIN.
SCKp cycle time
Note 1
tKCY2
20 MHz < fMCK ≤ 24 MHz
12/fMCK
8 MHz < fMCK ≤ 20 MHz
10/fMCK
–
ns
4 MHz < fMCK ≤ 8 MHz
8/fMCK
16/fMCK
ns
fMCK ≤ 4 MHz
6/fMCK
10/fMCK
ns
2.7 V ≤ VDD < 4.0 V,
20 MHz < fMCK ≤ 24 MHz
16/fMCK
–
ns
2.3 V ≤ Vb ≤ 2.7 V
16 MHz < fMCK ≤ 20 MHz
14/fMCK
–
ns
8 MHz < fMCK ≤ 16 MHz
12/fMCK
–
ns
4 MHz < fMCK ≤ 8 MHz
8/fMCK
16/fMCK
ns
fMCK ≤ 4 MHz
6/fMCK
10/fMCK
ns
1.8 V ≤ VDD < 3.3 V,
20 MHz < fMCK ≤ 24 MHz
36/fMCK
–
ns
1.6 V ≤ Vb ≤ 2.0 V
16 MHz < fMCK ≤ 20 MHz
32/fMCK
–
ns
8 MHz < fMCK ≤ 16 MHz
26/fMCK
–
ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK
16/fMCK
ns
fMCK ≤ 4 MHz
10/fMCK
10/fMCK
ns
tKCY2/2 – 12
tKCY2/2 – 50
ns
tKCY2/2 – 18
tKCY2/2 – 50
ns
tKCY2/2 – 50
tKCY2/2 – 50
ns
tKH2,
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V
width
tKL2
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
tSIK2
SIp hold time
MAX.
4.0 V ≤ VDD ≤ 5.5 V,
SCKp high-/low-level
(to SCKp↑) Note 3
MIN.
2.7 V ≤ Vb ≤ 4.0 V
Note 2
SIp setup time
MAX.
Unit
Note 2
–
ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ VDD ≤ 4.0 V
1/fMCK + 20
1/fMCK + 30
ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V
1/fMCK + 20
1/fMCK + 30
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ VDD ≤ 2.0 V Note 2
1/fMCK + 30
1/fMCK + 30
ns
1/fMCK + 31
1/fMCK + 31
ns
tKSI2
(from SCKp↑) Note 4
Delay time from
tKSO2
SCKp↓ to SOp
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
output Note 5
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 kΩ
Notes 1.
2/fMCK +
2/fMCK +
120
573
2/fMCK +
2/fMCK +
214
573
2/fMCK +
2/fMCK +
573
573
ns
ns
ns
Transfer rate in the SNOOZE mode: MAX. 1 Mbps
2.
Use it with VDD ≥ Vb.
3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Cautions 1. Select the TTL input buffer for the SIp and SCKp pins and the N-ch open drain output (VDD
tolerance) mode for the SOp pin by using port input mode register 1 (PIM1) and port output mode
register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
2. CSI01 and CSI11 cannot communicate at different potential.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 47 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
CSI mode connection diagram (during communication at different potential)
Vb
Rb
SCKp
RL78
microcontroller
SCK
SIp
SO
SOp
SI
User's device
Remarks 1. Rb [Ω]: Communication line (SOp) pull-up resistance, Cb [F]: Communication line (SOp) load capacitance,
Vb [V]: Communication line voltage
2. p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 10))
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
t KCY2
t KL2
t KH2
SCKp
t SIK2
t KSI2
Input data
SIp
t KSO2
SOp
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Output data
Page 48 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
t KCY2
t KL2
t KH2
SCKp
t SIK2
t KSI2
Input data
SIp
t KSO2
SOp
Remark
Output data
p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0)
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 49 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
(10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode)
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
LS (low-speed
main) Mode
main) Mode
MIN.
SCLr clock frequency
fSCL
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
MAX.
MIN.
Unit
MAX.
Note1
300Note1
kHz
400Note1
300Note1
kHz
300Note1
300Note1
kHz
400
Cb = 100 pF, Rb = 2.8 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,Note2
Cb = 100 pF, Rb = 5.5 kΩ
Hold time when SCLr = “L”
tLOW
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
1150
1550
ns
1150
1550
ns
1550
1550
ns
675
610
ns
600
610
ns
610
610
ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
1/fMCK
1/fMCK
ns
Cb = 100 pF, Rb = 2.8 kΩ
+ 190
+ 190
Note3
Note3
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
1/fMCK
1/fMCK
Cb = 100 pF, Rb = 2.7 kΩ
+ 190
+ 190
Note3
Note3
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,Note2
1/fMCK
1/fMCK
Cb = 100 pF, Rb = 5.5 kΩ
+ 190
+ 190
Note3
Note3
Cb = 100 pF, Rb = 2.8 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,Note2
Cb = 100 pF, Rb = 5.5 kΩ
Hold time when SCLr = “H”
tHIGH
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,Note2
Cb = 100 pF, Rb = 5.5 kΩ
Data setup time (reception)
Data hold time
tSU:DAT
tHD:DAT
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
ns
ns
0
355
0
355
ns
0
355
0
355
ns
0
405
0
405
ns
Cb = 100 pF, Rb = 2.8 kΩ
(transmission)
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,Note2
Cb = 100 pF, Rb = 5.5 kΩ
Notes 1.
The value must be equal to or less than fMCK/4.
2.
Use it with VDD ≥ Vb.
3.
Set tSU:DAT so that it will not exceed the hold time when SCLr = “L” or SCLr = “H”.
Cautions 1. Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin
and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode
register 1 (PIM1) and port output mode register 1 (POM1).
For VIH and VIL, see the DC
characteristics with TTL input buffer selected.
2. IIC01 and IIC11 cannot communicate at different potential.
(Remarks are listed on the next page.)
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 50 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
Simplified I2C mode connection diagram (during communication at different potential)
Vb
Vb
Rb
Rb
SDAr
SDA
RL78
microcontroller
User's device
SCLr
SCL
Simplified I2C mode serial transfer timing (during communication at different potential)
1/fSCL
t LOW
t HIGH
SCLr
SDAr
t HD : DAT
Remarks 1.
t SU : DAT
Rb [Ω]: Communication line (SDAr, SCLr) pull-up resistance, Cb [F]: Communication line (SDAr, SCLr)
load capacitance, Vb [V]: Communication line voltage
2.
r: IIC Number (r = 00, 20)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn).
m: Unit number (m = 0,1), n: Channel number (n = 0))
4.
Simplified I2C mode is supported only by the R5F102 products.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 51 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
2.5.2 Serial interface IICA
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) mode
Unit
LS (low-speed main) mode
Standard Mode
MIN.
SCLA0 clock frequency
fSCL
MAX.
Fast mode: fCLK ≥ 3.5 MHz
Normal mode: fCLK ≥ 1 MHz
0
Fast Mode
MIN.
MAX.
0
400
100
kHz
kHz
Setup time of restart condition
tSU:STA
4.7
0.6
µs
Hold timeNote 1
tHD:STA
4.0
0.6
µs
Hold time when SCLA0 = “L”
tLOW
4.7
1.3
µs
Hold time when SCLA0 = “H”
tHIGH
4.0
0.6
µs
tSU:DAT
250
100
ns
tHD:DAT
0
Setup time of stop condition
tSU:STO
4.0
0.6
µs
Bus-free time
tBUF
4.7
1.3
µs
Data setup time (reception)
Data hold time (transmission)
Notes 1.
2.
Note 2
3.45
0
0.9
µs
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Caution
Only in the 30-pin products, the values in the above table are applied even when bit 2 (PIOR2) in the
peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1,
VOL1) must satisfy the values in the redirect destination.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Normal mode:
Fast mode:
Cb = 400 pF, Rb = 2.7 kΩ
Cb = 320 pF, Rb = 1.1 kΩ
IICA serial transfer timing
t LOW
tR
SCLA0
tHD:DAT
tHD:STA
t HIGH
tF
tSU:STA
tHD:STA
tSU:STO
tSU:DAT
SDAA0
t BUF
Stop
condition
Start
condition
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Restart
condition
Stop
condition
Page 52 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
2.6 Analog Characteristics
2.6.1 A/D converter characteristics
Classification of A/D converter characteristics
Input channel
Reference Voltage
Reference voltage (+) = AVREFP
Reference voltage (+) = VDD
Reference voltage (+) = VBGR
Reference voltage (–) = AVREFM
Reference voltage (–) = VSS
Reference voltage (–) = AVREFM
ANI0 to ANI3
Refer to 2.6.1 (1).
Refer to 2.6.1 (3).
Refer to 2.6.1 (4).
ANI16 to ANI22
Refer to 2.6.1 (2).
Internal reference voltage
Refer to 2.6.1 (1).
–
Temperature sensor
output voltage
(1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (–) = AVREFM/ANI1
(ADREFM = 1), target pin: ANI2, ANI3, internal reference voltage, and temperature sensor output voltage
(TA = –40 to +85°C, 1.8 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (–) =
AVREFM = 0 V)
Parameter
Symbol
Resolution
RES
Overall errorNote 1
AINL
Conversion time
tCONV
Conditions
Full-scale errorNotes 1, 2
Integral linearity errorNote 1
Differential linearity error
EZS
EFS
ILE
DLE
Note 1
Analog input voltage
VAIN
TYP.
MAX.
10
bit
1.2
±3.5
LSB
1.2
±7.0 Note 4
LSB
39
µs
8
10-bit resolution
AVREFP = VDD Note 3
10-bit resolution
Target pin: ANI2, ANI3
10-bit resolution
Target pin: Internal
reference voltage, and
temperature sensor
output voltage
(HS (high-speed main)
mode)
Zero-scale errorNotes 1, 2
MIN.
Unit
3.6 V ≤ VDD ≤ 5.5 V
2.125
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
µs
1.8 V ≤ VDD ≤ 5.5 V
17
39
µs
57
95
µs
3.6 V ≤ VDD ≤ 5.5 V
2.375
39
µs
2.7 V ≤ VDD ≤ 5.5 V
3.5625
39
µs
2.4 V ≤ VDD ≤ 5.5 V
17
39
µs
±0.25
%FSR
10-bit resolution
AVREFP = VDD Note 3
±0.50
10-bit resolution
AVREFP = VDD Note 3
±0.25
±2.5
±5.0
10-bit resolution
AVREFP = VDD Note 3
Internal reference voltage
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode)
Temperature sensor output voltage
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode)
%FSR
%FSR
±0.50 Note 4 %FSR
10-bit resolution
AVREFP = VDD Note 3
ANI2, ANI3
Note 4
Note 4
±1.5
±2.0
0
Note 4
AVREFP
VBGR
Note 5
VTMPS25 Note 5
LSB
LSB
LSB
LSB
V
V
V
(Notes are listed on the next page.)
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 53 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD.
4. Values when the conversion time is set to 57 µs (min.) and 95 µs (max.).
5. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.
(2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (–) = AVREFM/ANI1
(ADREFM = 1), target pin: ANI16 to ANI22
(TA = –40 to +85°C, 1.8 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (–) =
AVREFM = 0 V)
Parameter
Resolution
Symbol
Conditions
RES
Overall error
Note 1
AINL
MIN.
TYP.
8
1.2
10-bit resolution
AVREFP = VDD Note 3
Conversion time
tCONV
1.2
Zero-scale error
EZS
Full-scale error
EFS
DLE
error Note 1
VAIN
LSB
±8.5
Note 4
LSB
µs
3.1875
39
µs
17
39
µs
57
95
µs
±0.35
%FSR
10-bit resolution
±0.60
±0.60
10-bit resolution
10-bit resolution
ANI16 to ANI22
Note 4
±0.35
10-bit resolution
AVREFP = VDD Note 3
Analog input voltage
±5.0
Target ANI pin: ANI16 to ANI22 2.7 V ≤ VDD ≤ 5.5 V
AVREFP = VDD Note 3
Differential linearity
bit
39
AVREFP = VDD Note 3
Integral linearity error Note 1 ILE
10
2.125
AVREFP = VDD Note 3
Notes 1, 2
Unit
3.6 V ≤ VDD ≤ 5.5 V
10-bit resolution
1.8 V ≤ VDD ≤ 5.5 V
Notes 1, 2
MAX.
%FSR
%FSR
±3.5
LSB
±6.0 Note 4
LSB
±2.0
LSB
±2.5
0
Note 4
%FSR
Note 4
AVREFP
LSB
V
and VDD
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP ≤ VDD, the MAX. values are as follows.
Overall error: Add ±4.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.20%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±2.0 LSB to the MAX. value when AVREFP = VDD.
4. When the conversion time is set to 57 µs (min.) and 95 µs (max.).
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 54 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
(3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (–) = VSS (ADREFM = 0),
target pin: ANI0 to ANI3, ANI16 to ANI22, internal reference voltage, and temperature sensor output voltage
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage (–) = VSS)
Parameter
Symbol
Resolution
Conditions
RES
Note 1
Overall error
AINL
MIN.
TYP.
8
10-bit resolution
1.2
1.2
Conversion time
tCONV
tCONV
Unit
10
bit
±7.0
LSB
±10.5
Note 3
LSB
10-bit resolution
3.6 V ≤ VDD ≤ 5.5 V
2.125
39
µs
Target pin: ANI0 to ANI3,
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
µs
1.8 V ≤ VDD ≤ 5.5 V
17
39
µs
57
95
µs
3.6 V ≤ VDD ≤ 5.5 V
2.375
39
µs
Target pin: internal reference 2.7 V ≤ VDD ≤ 5.5 V
voltage, and temperature
2.4 V ≤ VDD ≤ 5.5 V
sensor output voltage (HS
3.5625
39
µs
17
39
µs
±0.60
%FSR
±0.85
%FSR
ANI16 to ANI22
Conversion time
MAX.
10-bit resolution
(high-speed main) mode)
Zero-scale errorNotes 1, 2
EZS
10-bit resolution
Note 3
Full-scale errorNotes 1, 2
EFS
10-bit resolution
±0.60
%FSR
±0.85
%FSR
Note 3
Integral linearity errorNote 1
ILE
10-bit resolution
±4.0
±6.5
Differential linearity error
Note 1
DLE
10-bit resolution
±2.0
±2.5
Analog input voltage
VAIN
ANI0 to ANI3, ANI16 to ANI22
Note 3
0
Internal reference voltage
Note 3
VDD
VBGR
Note 4
LSB
LSB
LSB
LSB
V
V
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode)
Temperature sensor output voltage
VTMPS25 Note 4
V
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode)
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When the conversion time is set to 57 µs (min.) and 95 µs (max.).
4. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 55 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
(4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (–) =
AVREFM (ADREFM = 1), target pin: ANI0, ANI2, ANI3, and ANI16 to ANI22
(TA = –40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = VBGR Note 3, Reference voltage (–) = AVREFM
Note 4=
0 V, HS (high-speed main) mode)
Parameter
Resolution
Symbol
Conditions
MIN.
RES
Conversion time
8-bit resolution
Zero-scale error
EZS
Integral linearity errorNote 1
ILE
Differential linearity error Note 1
DLE
Analog input voltage
MAX.
8
tCONV
Notes 1, 2
TYP.
Unit
bit
39
µs
8-bit resolution
±0.60
%FSR
8-bit resolution
±2.0
LSB
8-bit resolution
±1.0
LSB
VAIN
17
0
VBGR
Note 3
V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.
4. When reference voltage (–) = VSS, the MAX. values are as follows.
Zero-scale error: Add ±0.35%FSR to the MAX. value when reference voltage (–) = AVREFM.
Integral linearity error: Add ±0.5 LSB to the MAX. value when reference voltage (–) = AVREFM.
Differential linearity error: Add ±0.2 LSB to the MAX. value when reference voltage (–) = AVREFM.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 56 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
2.6.2 Temperature sensor/internal reference voltage characteristics
(TA = –40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, HS (high-speed main) mode
Parameter
Symbol
Temperature sensor output voltage
VTMPS25
Conditions
MIN.
TYP.
MAX.
1.05
Setting ADS register = 80H,
Unit
V
TA = +25°C
Internal reference voltage
VBGR
Setting ADS register = 81H
Temperature coefficient
FVTMPS
Temperature sensor output
1.38
1.45
1.50
V
–3.6
mV/°C
voltage that depends on the
temperature
Operation stabilization wait time
tAMP
5
µs
2.6.3 POR circuit characteristics
(TA = –40 to +85°C, VSS = 0 V)
Parameter
Symbol
Detection voltage
VPOR
Conditions
The power supply voltage is
MIN.
TYP.
MAX.
Unit
1.47
1.51
1.55
V
1.46
1.50
1.54
V
rising.
VPDR
The power supply voltage is
falling.
Minimum pulse width Note
Note
TPW
300
µs
Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required
for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or
the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation
status control register (CSC).
TPW
Supply voltage (VDD)
VPOR
VPDR or 0.7 V
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 57 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
2.6.4 LVD circuit characteristics
LVD Detection Voltage of Reset Mode and Interrupt Mode
(TA = –40 to +85°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Detection supply voltage
Symbol
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VLVD8
VLVD9
VLVD10
VLVD11
Minimum pulse width
Detection delay time
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
tLW
Conditions
MIN.
TYP.
MAX.
Unit
The power supply voltage is rising.
3.98
4.06
4.14
V
The power supply voltage is falling.
3.90
3.98
4.06
V
The power supply voltage is rising.
3.68
3.75
3.82
V
The power supply voltage is falling.
3.60
3.67
3.74
V
The power supply voltage is rising.
3.07
3.13
3.19
V
The power supply voltage is falling.
3.00
3.06
3.12
V
The power supply voltage is rising.
2.96
3.02
3.08
V
The power supply voltage is falling.
2.90
2.96
3.02
V
The power supply voltage is rising.
2.86
2.92
2.97
V
The power supply voltage is falling.
2.80
2.86
2.91
V
The power supply voltage is rising.
2.76
2.81
2.87
V
The power supply voltage is falling.
2.70
2.75
2.81
V
The power supply voltage is rising.
2.66
2.71
2.76
V
The power supply voltage is falling.
2.60
2.65
2.70
V
The power supply voltage is rising.
2.56
2.61
2.66
V
The power supply voltage is falling.
2.50
2.55
2.60
V
The power supply voltage is rising.
2.45
2.50
2.55
V
The power supply voltage is falling.
2.40
2.45
2.50
V
The power supply voltage is rising.
2.05
2.09
2.13
V
The power supply voltage is falling.
2.00
2.04
2.08
V
The power supply voltage is rising.
1.94
1.98
2.02
V
The power supply voltage is falling.
1.90
1.94
1.98
V
The power supply voltage is rising.
1.84
1.88
1.91
V
The power supply voltage is falling.
1.80
1.84
1.87
V
300
µs
300
µs
Page 58 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
LVD detection voltage of interrupt & reset mode
(TA = –40 to +85°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Interrupt and reset
VLVDB0
mode
VLVDB1
Conditions
MIN.
TYP.
MAX.
Unit
1.80
1.84
1.87
V
Rising reset release voltage
1.94
1.98
2.02
V
Falling interrupt voltage
1.90
1.94
1.98
V
2.05
2.09
2.13
V
VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage
LVIS1, LVIS0 = 1, 0
VLVDB2
LVIS1, LVIS0 = 0, 1
Rising reset release voltage
Falling interrupt voltage
2.00
2.04
2.08
V
VLVDB3
LVIS1, LVIS0 = 0, 0
Rising reset release voltage
3.07
3.13
3.19
V
Falling interrupt voltage
3.00
3.06
3.12
V
2.40
2.45
2.50
V
Rising reset release voltage
2.56
2.61
2.66
V
Falling interrupt voltage
2.50
2.55
2.60
V
Rising reset release voltage
2.66
2.71
2.76
V
Falling interrupt voltage
2.60
2.65
2.70
V
Rising reset release voltage
3.68
3.75
3.82
V
Falling interrupt voltage
3.60
3.67
3.74
V
2.70
2.75
2.81
V
Rising reset release voltage
2.86
2.92
2.97
V
Falling interrupt voltage
2.80
2.86
2.91
V
Rising reset release voltage
2.96
3.02
3.08
V
Falling interrupt voltage
2.90
2.96
3.02
V
Rising reset release voltage
3.98
4.06
4.14
V
Falling interrupt voltage
3.90
3.98
4.06
V
VLVDC0
VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage
LVIS1, LVIS0 = 1, 0
VLVDC1
LVIS1, LVIS0 = 0, 1
VLVDC2
LVIS1, LVIS0 = 0, 0
VLVDC3
VLVDD0
VPOC2, VPOC1, VPOC1 = 0, 1, 1, falling reset voltage
VLVDD1
VLVDD2
VLVDD3
LVIS1, LVIS0 = 1, 0
LVIS1, LVIS0 = 0, 1
LVIS1, LVIS0 = 0, 0
2.6.5 Power supply voltage rising slope characteristics
(TA = –40 to +85°C, VSS = 0 V)
Parameter
Power supply voltage rising slope
Caution
Symbol
Conditions
SVDD
MIN.
TYP.
MAX.
Unit
54
V/ms
Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the
operating voltage range shown in 2.4 AC Characteristics.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 59 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
2.7 RAM Data Retention Characteristics
(TA = –40 to +85°C, VSS = 0 V)
Parameter
Data retention supply voltage
Symbol
Conditions
VDDDR
MIN.
1.46
TYP.
Note
MAX.
Unit
5.5
V
Note This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage
reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated.
Operation mode
STOP mode
RAM data retention
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
2.8 Flash Memory Programming Characteristics
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
System clock frequency
fCLK
Code flash memory rewritable times
Cerwr
Notes 1, 2, 3
Conditions
MIN.
TYP.
1
Retained for 20 years
1,000
MAX.
Unit
24
MHz
Times
TA = 85°C
Data flash memory rewritable times
Notes 1, 2, 3
1,000,000
Retained for 1 year
TA = 25°C
Retained for 5 years
100,000
TA = 85°C
Retained for 20 years
10,000
TA = 85°C
Notes 1.
1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the
rewrite.
2.
When using flash memory programmer and Renesas Electronics self programming library
3.
These are the characteristics of the flash memory and the results obtained from reliability testing by
Renesas Electronics Corporation.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 60 of 108
RL78/G12
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
2.9 Dedicated Flash Memory Programmer Communication (UART)
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Transfer rate
Conditions
MIN.
During serial programming
TYP.
115,200
MAX.
Unit
1,000,000
bps
2.10 Timing of Entry to Flash Memory Programming Modes
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Time to complete the communication for the initial
Conditions
MIN.
TYP.
POR and LVD reset are
tSUINIT
MAX.
Unit
100
ms
released before external
setting after the external reset is released
reset release
Time to release the external reset after the TOOL0 tSU
POR and LVD reset are
pin is set to the low level
released before external
10
µs
1
ms
reset release
Time to hold the TOOL0 pin at the low level after
POR and LVD reset are
tHD
the external reset is released
released before external
(excluding the processing time of the firmware to
reset release
control the flash memory)
RESET
tHD + software
processing
time
1-byte data for
setting mode
TOOL0
tSU
tSUINIT
The low level is input to the TOOL0 pin.
The external reset is released (POR and LVD reset must be released before the external
reset is released.).
The TOOL0 pin is set to the high level.
Setting of the flash memory programming mode by UART reception and complete the baud
rate setting.
Remark tSUINIT: Communication for the initial setting must be completed within 100 ms after the external reset is released
during this period.
tSU:
Time to release the external reset after the TOOL0 pin is set to the low level
tHD:
Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing
time of the firmware to control the flash memory)
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 61 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to
+105°C)
This chapter describes the following electrical specifications.
Target products G: Industrial applications TA = -40 to +105°C
R5F102xxGxx
Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and
evaluation. Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded when this
function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not
liable for problems occurring when the on-chip debug function is used.
2. The pins mounted depend on the product. Refer to 2.1 Port Functions to 2.2.1 Functions for each
product in the RL78/G12 User’s Manual.
3. Please contact Renesas Electronics sales office for derating of operation under TA = +85°C to
+105°C. Derating is the systematic reduction of load for the sake of improved reliability.
Remark
When the RL78 microcontroller is used in the range of TA = -40 to +85°C, see 2. ELECTRICAL
SPECIFICATIONS (TA = -40 to +85°C).
There are following differences between the products “G: Industrial applications (TA = -40 to +105°C)” and the products “A:
Consumer applications, and D: Industrial applications”.
Parameter
Application
A: Consumer applications,
G: Industrial applications
D: Industrial applications
Operating ambient temperature
TA = -40 to +85°C
TA = -40 to +105°C
Operating mode
HS (high-speed main) mode:
HS (high-speed main) mode only:
Operating voltage range
2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz
2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
LS (low-speed main) mode:
1.8 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz
High-speed on-chip oscillator
R5F102 products, 1.8 V ≤ VDD ≤ 5.5 V:
R5F102 products, 2.4 V ≤ VDD ≤ 5.5 V:
clock accuracy
±1.0%@ TA = -20 to +85°C
±2.0%@ TA = +85 to +105°C
±1.5%@ TA = -40 to -20°C
±1.0%@ TA = -20 to +85°C
R5F103 products, 1.8 V ≤ VDD ≤ 5.5 V:
±1.5%@ TA = -40 to -20°C
±5.0%@ TA = -40 to +85°C
Serial array unit
UART
UART
CSI: fCLK/2 (supporting 12 Mbps), fCLK/4
2
Voltage detector
CSI: fCLK/4
Simplified I C communication
Simplified I2C communication
Rise detection voltage: 1.88 V to 4.06 V (12 levels)
Rise detection voltage: 2.61 V to 4.06 V
Fall detection voltage: 1.84 V to 3.98 V (12 levels)
(8 levels)
Fall detection voltage: 2.55 V to 3.98 V (8 levels)
Remark
The electrical characteristics of the products G: Industrial applications (TA = -40 to +105°C) are different from
those of the products “A: Consumer applications, and D: Industrial applications”. For details, refer to 3.1 to
3.10.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 62 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
3.1 Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25°C)
Parameter
Symbols
Supply Voltage
VDD
REGC terminal input
voltageNote1
VIREGC
Conditions
REGC
Ratings
Unit
–0.5 to + 6.5
V
–0.3 to +2.8
V
and –0.3 to VDD + 0.3
Note 2
Input Voltage
VI1
Other than P60, P61
VI2
P60, P61 (N-ch open drain)
Output Voltage
VO
Analog input voltage
VAI
20, 24-pin products: ANI0 to ANI3, ANI16 to ANI22
30-pin products: ANI0 to ANI3, ANI16 to ANI19
Output current, high
IOH1
–0.3 to VDD + 0.3Note 3
V
–0.3 to 6.5
V
–0.3 to VDD + 0.3Note 3
V
–0.3 to VDD + 0.3
V
and –0.3 to
AVREF(+)+0.3 Notes 3, 4
Per pin
Other than P20 to P23
–40
mA
Total of all pins
All the terminals other than P20 to P23
–170
mA
20-, 24-pin products: P40 to P42
–70
mA
20-, 24-pin products: P00 to P03Note 5,
P10 to P14
30-pin products: P10 to P17, P30, P31,
P50, P51, P147
–100
mA
P20 to P23
–0.5
mA
–2
mA
mA
30-pin products: P00, P01, P40, P120
IOH2
Per pin
Total of all pins
Output current, low
IOL1
IOL2
Per pin
Other than P20 to P23
40
Total of all pins
All the terminals other than P20 to P23
170
mA
20-, 24-pin products: P40 to P42
30-pin products: P00, P01, P40, P120
70
mA
20-, 24-pin products: P00 to P03 Note 5,
P10 to P14, P60, P61
30-pin products: P10 to P17, P30, P31,
P50, P51, P60, P61, P147
100
mA
1
mA
5
mA
Per pin
Total of all pins
P20 to P23
Operating ambient
temperature
TA
–40 to +105
°C
Storage temperature
Tstg
–65 to +150
°C
Notes 1.
2.
3.
4.
5.
30-pin product only.
Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF). This value determines the absolute maximum
rating of the REGC pin. Do not use it with voltage applied.
Must be 6.5 V or lower.
Do not exceed AVREF (+) + 0.3 V in case of A/D conversion target pin.
24-pin products only.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
2. AVREF(+) : + side reference voltage of the A/D converter.
3. VSS : Reference voltage
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 63 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
3.2 Oscillator Characteristics
3.2.1 X1 oscillator characteristics
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Resonator
Conditions
MIN.
TYP.
MAX.
X1 clock oscillation
Ceramic resonator /
2.7 V ≤ VDD ≤ 5.5 V
1.0
20.0
frequency (fX)Note
crystal oscillator
2.4 V ≤ VDD < 2.7 V
1.0
8.0
Unit
MHz
Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time.
Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator
characteristics.
Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1
clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC)
by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation
stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time
with the resonator to be used.
Remark
When using the X1 oscillator, refer to 5.4 System Clock Oscillator in the RL78/G12 User’s Manual.
3.2.2 On-chip oscillator characteristics
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Oscillators
High-speed on-chip oscillator
Parameters
Conditions
MAX.
Unit
1
24
MHz
TA = –20 to +85°C
-1.0
+1.0
%
TA = –40 to –20°C
-1.5
+1.5
%
TA = +85 to +105°C
-2.0
+2.0
%
fIH
MIN.
TYP.
clock frequency Notes 1, 2
High-speed on-chip oscillator
R5F102 products
clock frequency accuracy
Low-speed on-chip oscillator
fIL
15
kHz
clock frequency
Low-speed on-chip oscillator
-15
+15
%
clock frequency accuracy
Notes 1.
High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H) and bits 0 to 2 of
HOCODIV register.
2.
This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 64 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
3.3 DC Characteristics
3.3.1 Pin characteristics
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Output current, high
Note 1
IOH1
(1/4)
Conditions
MIN.
TYP.
MAX.
Unit
20-, 24-pin products:
–3.0
mA
Per pin for P00 to P03Note 4,
Note 2
P10 to P14, P40 to P42
30-pin products:
Per pin for P00, P01, P10 to P17, P30,
P31, P40, P50, P51, P120, P147
20-, 24-pin products:
4.0 V ≤ VDD ≤ 5.5 V
Total of P40 to P42
30-pin products:
–9.0
mA
2.7 V ≤ VDD < 4.0 V
–6.0
mA
2.4 V ≤ VDD < 2.7 V
–4.5
mA
20-, 24-pin products:
4.0 V ≤ VDD ≤ 5.5 V
–27.0
mA
Total of P00 to P03Note 4, P10 to P14
2.7 V ≤ VDD < 4.0 V
–18.0
mA
30-pin products:
2.4 V ≤ VDD < 2.7 V
–10.0
mA
Total of all pins (When duty ≤ 70%Note 3)
–36.0
mA
Per pin for P20 to P23
–0.1
mA
Total of all pins
–0.4
mA
Total of P00, P01, P40, P120
(When duty ≤ 70% Note 3)
Total of P10 to P17, P30, P31,
P50, P51, P147
(When duty ≤ 70% Note 3)
IOH2
Notes 1.
value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an
output pin.
2.
3.
However, do not exceed the total current value.
The output current value under conditions where the duty factor ≤ 70%.
If duty factor > 70%: The output current value can be calculated with the following expression (where n
represents the duty factor as a percentage).
● Total output current of pins = (IOH × 0.7)/(n × 0.01)
Where n = 80% and IOH = –10.0 mA
Total output current of pins = (–10.0 × 0.7)/(80 × 0.01) –8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
4.
24-pin products only.
Caution P10 to P12 and P41 for 20-pin products, P01, P10 to P12, and P41 for 24-pin products, and P00, P10
to P15, P17, and P50 for 30-pin products do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 65 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Note 1
Output current, low
IOL1
(2/4)
Conditions
MIN.
20-, 24-pin products:
Per pin for P00 to P03Note 4,
TYP.
MAX.
Unit
8.5
mA
Note 2
P10 to P14, P40 to P42
30-pin products:
Per pin for P00, P01, P10 to P17, P30,
P31, P40, P50, P51, P120, P147
Per pin for P60, P61
15.0
mA
Note 2
20-, 24-pin products:
4.0 V ≤ VDD ≤ 5.5 V
25.5
mA
Total of P40 to P42
2.7 V ≤ VDD < 4.0 V
9.0
mA
30-pin products:
2.4 V ≤ VDD < 2.7 V
1.8
mA
20-, 24-pin products:
4.0 V ≤ VDD ≤ 5.5 V
40.0
mA
Total of P00 to P03Note 4,
2.7 V ≤ VDD < 4.0 V
27.0
mA
2.4 V ≤ VDD < 2.7 V
5.4
mA
Total of all pins (When duty ≤ 70%Note 3)
65.5
mA
Per pin for P20 to P23
0.4
mA
Total of all pins
1.6
mA
Total of P00, P01, P40, P120
(When duty ≤ 70% Note 3)
P10 to P14, P60, P61
30-pin products:
Total of P10 to P17, P30, P31, P50,
P51, P60, P61, P147
(When duty ≤ 70% Note 3)
IOL2
Notes 1.
Value of current at which the device operation is guaranteed even if the current flows from an output pin to
the VSS pin.
2.
However, do not exceed the total current value.
3.
The output current value under conditions where the duty factor ≤ 70%.
If duty factor > 70%: The output current value can be calculated with the following expression (where n
represents the duty factor as a percentage).
● Total output current of pins = (IOL × 0.7)/(n × 0.01)
Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
4.
Remark
24-pin products only.
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 66 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Input voltage, high
Symbol
VIH1
(3/4)
Conditions
MIN.
MAX.
Unit
0.8VDD
VDD
V
4.0 V ≤ VDD ≤ 5.5 V
2.2
VDD
V
20-, 24-pin products: P10, P11 3.3 V ≤ VDD < 4.0 V
2.0
VDD
V
2.4 V ≤ VDD < 3.3 V
1.5
VDD
V
0.7VDD
VDD
V
0.7VDD
6.0
V
0.8VDD
VDD
V
0
0.2VDD
V
4.0 V ≤ VDD ≤ 5.5 V
0
0.8
V
20-, 24-pin products: P10, P11 3.3 V ≤ VDD < 4.0 V
0
0.5
V
2.4 V ≤ VDD < 3.3 V
0
0.32
V
0
0.3VDD
V
0
0.3VDD
V
0
0.2VDD
V
Normal input buffer
20-, 24-pin products: P00 to P03
TYP.
Note 2
, P10 to P14,
P40 to P42
30-pin products: P00, P01, P10 to P17, P30, P31,
P40, P50, P51, P120, P147
VIH2
TTL input buffer
30-pin products: P01, P10,
P11, P13 to P17
VIH3
Normal input buffer
P20 to P23
VIH4
Input voltage, low
P60, P61
Note 1
VIH5
P121, P122, P125
VIL1
Normal input buffer
, P137, EXCLK, RESET
20-, 24-pin products: P00 to P03
Note 2
, P10 to P14,
P40 to P42
30-pin products: P00, P01, P10 to P17, P30, P31,
P40, P50, P51, P120, P147
VIL2
TTL input buffer
30-pin products: P01, P10,
P11, P13 to P17
Output voltage, high
VIL3
P20 to P23
VIL4
P60, P61
Note 1
VIL5
P121, P122, P125
VOH1
20-, 24-pin products:
, P137, EXCLK, RESET
4.0 V ≤ VDD ≤ 5.5 V,
P00 to P03Note 2, P10 to P14,
IOH1 = –3.0 mA
P40 to P42
2.7 V ≤ VDD ≤ 5.5 V,
30-pin products:
IOH1 = –2.0 mA
P00, P01, P10 to P17, P30,
2.4 V ≤ VDD ≤ 5.5 V,
P31, P40, P50, P51, P120,
VDD–0.7
V
VDD–0.6
V
VDD–0.5
V
VDD–0.5
V
IOH1 = –1.5 mA
P147
VOH2
Notes 1.
2.
P20 to P23
IOH2 = –100 µA
20, 24-pin products only.
24-pin products only.
Caution The maximum value of VIH of pins P10 to P12 and P41 for 20-pin products, P01, P10 to P12, and P41
for 24-pin products, and P00, P10 to P15, P17, and P50 for 30-pin products is VDD even in N-ch opendrain mode.
High level is not output in the N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 67 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Output voltage, low
Symbol
VOL1
(4/4)
Conditions
20-, 24-pin products:
4.0 V ≤ VDD ≤ 5.5 V,
P00 to P03Note, P10 to P14,
IOL1 = 8.5 mA
P40 to P42
2.7 V ≤ VDD ≤ 5.5 V,
30-pin products: P00, P01,
IOL1 = 3.0 mA
P10 to P17, P30, P31, P40,
2.7 V ≤ VDD ≤ 5.5 V,
P50, P51, P120, P147
MIN.
TYP.
MAX.
Unit
0.7
V
0.6
V
0.4
V
0.4
V
IOL1 = 1.5 mA
2.4 V ≤ VDD ≤ 5.5 V,
IOL1 = 0.6 mA
VOL2
P20 to P23
IOL2 = 400 µA
0.4
V
VOL3
P60, P61
4.0 V ≤ VDD ≤ 5.5 V,
2.0
V
0.4
V
0.4
V
0.4
V
1
µA
1
µA
10
µA
–1
µA
–1
µA
–10
µA
100
kΩ
IOL1 = 15.0 mA
4.0 V ≤ VDD ≤ 5.5 V,
IOL1 = 5.0 mA
2.7 V ≤ VDD ≤ 5.5 V,
IOL1 = 3.0 mA
2.4 V ≤ VDD ≤ 5.5 V,
IOL1 = 2.0 mA
Input leakage current,
ILIH1
Other than P121,
VI = VDD
P122
high
ILIH2
P121, P122
VI = VDD Input port or external
(X1, X2/EXCLK)
clock input
When resonator
connected
Input leakage current,
ILIL1
Other than P121,
VI = VSS
P122
low
ILIL2
P121, P122
VI = VSS Input port or external
(X1, X2/EXCLK)
clock input
When resonator
connected
On-chip pull-up
RU
20-, 24-pin products:
VI = VSS, input port
10
20
P00 to P03Note, P10 to P14,
resistance
P40 to P42, P125, RESET
30-pin products: P00, P01,
P10 to P17, P30, P31, P40,
P50, P51, P120, P147
Note
24-pin products only.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 68 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
3.3.2 Supply current characteristics
(1) 20-, 24-pin products
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
IDD1
Supply
currentNote 1
(1/2)
Conditions
Operating HS (High-speed
mode
MIN.
fIH = 24 MHzNote 3
main) mode Note 4
Basic
VDD = 5.0 V
1.5
VDD = 3.0 V
1.5
Normal
VDD = 5.0 V
3.3
5.3
operation
VDD = 3.0 V
3.3
5.3
VDD = 5.0 V
2.5
3.9
VDD = 3.0 V
2.5
3.9
Square wave input
2.8
4.7
Resonator connection
3.0
4.8
Square wave input
2.8
4.7
Resonator connection
3.0
4.8
Square wave input
1.8
2.8
Resonator connection
1.8
2.8
Square wave input
1.8
2.8
Resonator connection
1.8
2.8
fIH = 16 MHz
Note 2
,
VDD = 5.0 V
Note 2
fMX = 20 MHz
,
VDD = 3.0 V
Note 2
fMX = 10 MHz
,
VDD = 5.0 V
Note 2
fMX = 10 MHz
,
VDD = 3.0 V
Notes 1.
MAX.
operation
Note 3
fMX = 20 MHz
TYP.
Unit
mA
mA
mA
mA
mA
mA
mA
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,
not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
2.
When high-speed on-chip oscillator clock is stopped.
3.
When high-speed system clock is stopped
4.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS (High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz
Remarks 1.
fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH: high-speed on-chip oscillator clock frequency
3. Temperature condition of the TYP. value is TA = 25°C.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 69 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(1) 20-, 24-pin products
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
IDD2 Note 2 HALT
Supply
currentNote 1
(2/2)
Conditions
mode
HS (High-speed
MIN.
fIH = 24 MHzNote 4
main) mode Note 6
fIH = 16 MHz
Note 4
fMX = 20 MHz
Note 3
,
VDD = 5.0 V
Note 3
VDD = 5.0 V
440
2230
µA
VDD = 3.0 V
440
2230
VDD = 5.0 V
400
1650
VDD = 3.0 V
400
1650
Square wave input
280
1900
Resonator connection
450
2000
280
1900
Square wave input
Resonator connection
450
2000
fMX = 10 MHzNote 3,
Square wave input
190
1010
VDD = 5.0 V
Resonator connection
260
1090
Square wave input
190
1010
Resonator connection
260
1090
Note 3
,
VDD = 3.0 V
Notes 1.
Unit
,
fMX = 10 MHz
IDD3
MAX.
VDD = 3.0 V
fMX = 20 MHz
Note 5
TYP.
STOP
TA = –40°C
0.19
0.50
mode
TA = +25°C
0.24
0.50
TA = +50°C
0.32
0.80
TA = +70°C
0.48
1.20
TA = +85°C
0.74
2.20
TA = +105°C
1.50
10.20
µA
µA
µA
µA
µA
µA
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,
not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
2.
During HALT instruction execution by flash memory.
3.
When high-speed on-chip oscillator clock is stopped.
4.
When high-speed system clock is stopped.
5.
Not including the current flowing into the 12-bit interval timer and watchdog timer.
6.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS (High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz
Remarks 1.
fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH: high-speed on-chip oscillator clock frequency
3. Except temperature condition of the TYP. value is TA = 25°C, other than STOP mode
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 70 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(2) 30-pin products
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
IDD1
Supply
currentNote 1
(1/2)
Conditions
MIN.
Operating
HS (High-speed fIH = 24 MHzNote 3
Basic
VDD = 5.0 V
1.5
mode
main) mode Note 4
operation VDD = 3.0 V
1.5
Normal
3.7
5.8
3.7
5.8
VDD = 5.0 V
2.7
4.2
VDD = 3.0 V
2.7
4.2
Note 2
,
Square wave input
3.0
4.9
VDD = 5.0 V
Resonator connection
3.2
5.0
fMX = 20 MHzNote 2,
Square wave input
3.0
4.9
VDD = 3.0 V
Resonator connection
3.2
5.0
Square wave input
1.9
2.9
Resonator connection
1.9
2.9
Square wave input
1.9
2.9
Resonator connection
1.9
2.9
Note 2
fMX = 10 MHz
,
VDD = 5.0 V
Note 2
fMX = 10 MHz
,
VDD = 3.0 V
Unit
mA
VDD = 5.0 V
fIH = 16 MHz
fMX = 20 MHz
MAX.
operation VDD = 3.0 V
Note 3
Notes 1.
TYP.
mA
mA
mA
mA
mA
mA
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,
not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
2.
When high-speed on-chip oscillator clock is stopped.
3.
When high-speed system clock is stopped
4.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS (High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz
Remarks 1.
fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH: high-speed on-chip oscillator clock frequency
3. Temperature condition of the TYP. value is TA = 25°C.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 71 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(2) 30-pin products
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Supply
Symbol
(2/2)
Conditions
IDD2 Note 2 HALT
HS (High-speed
mode
main) mode Note 6
current Note 1
MIN.
fIH = 24 MHzNote 4
fIH = 16 MHz
Note 4
fMX = 20 MHz
Note 3
,
VDD = 5.0 V
Note 3
VDD = 5.0 V
440
2300
µA
VDD = 3.0 V
440
2300
VDD = 5.0 V
400
1700
VDD = 3.0 V
400
1700
Square wave input
280
1900
Resonator connection
450
2000
280
1900
Square wave input
Resonator connection
450
2000
fMX = 10 MHzNote 3,
Square wave input
190
1020
VDD = 5.0 V
Resonator connection
260
1100
Square wave input
190
1020
Resonator connection
260
1100
Note 3
,
VDD = 3.0 V
Notes 1.
Unit
,
fMX = 10 MHz
IDD3
MAX.
VDD = 3.0 V
fMX = 20 MHz
Note 5
TYP.
STOP
TA = –40°C
0.18
0.50
mode
TA = +25°C
0.23
0.50
TA = +50°C
0.30
1.10
TA = +70°C
0.46
1.90
TA = +85°C
0.75
3.30
TA = +105°C
2.94
15.30
µA
µA
µA
µA
µA
µA
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,
not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
2.
During HALT instruction execution by flash memory.
3.
When high-speed on-chip oscillator clock is stopped.
4.
When high-speed system clock is stopped.
5.
Not including the current flowing into the 12-bit interval timer and watchdog timer.
6.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS (High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz
Remarks 1.
fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH: high-speed on-chip oscillator clock frequency
3. Except STOP mode, temperature condition of the TYP. value is TA = 25°C.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 72 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(3) Peripheral functions (Common to all products)
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Low-speed onchip
Symbol
IFIL
Conditions
MIN.
Note 1
TYP.
MAX.
Unit
0.20
µA
0.02
µA
0.22
µA
oscillator operating
current
12-bit interval timer
ITMKA
operating current
Notes 1, 2, 3
Watchdog timer
IWDT
operating current
Notes 1, 2, 4
A/D converter
operating current
A/D converter
reference voltage
operating current
Temperature sensor
operating current
LVD operating current
IADC
Notes 1, 5
fIL = 15 kHz
When conversion
at maximum speed
Normal mode, AVREFP = VDD = 5.0 V
1.30
1.70
mA
Low voltage mode,
AVREFP = VDD = 3.0 V
0.50
0.70
mA
IADREF
75.0
µA
75.0
µA
0.08
µA
Note 1
ITMPS
Note 1
ILVD
Notes 1, 6
Self-programming
IFSP
operating current
Notes 1, 8
BGO operating
IBGO
current
Notes 1, 7
SNOOZE operating
ISNOZ
current
Note 1
ADC operation
2.00
12.20
mA
2.00
12.20
mA
The mode is performed Note 9
0.50
1.10
mA
The A/D conversion operations are
1.20
2.04
mA
0.70
1.54
mA
performed, Low voltage mode, AVREFP
= VDD = 3.0 V
CSI/UART operation
Notes 1. Current flowing to the VDD.
2. When high speed on-chip oscillator and high-speed system clock are stopped.
3. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip
oscillator). The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3, and IFIL and ITMKA when
the 12-bit interval timer operates.
4. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator).
The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer
operates.
5. Current flowing only to the A/D converter. The current value of the RL78 microcontrollers is the sum of IDD1 or
IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.
6. Current flowing only to the LVD circuit. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or
IDD3 and ILVD when the LVD circuit operates.
7. Current flowing only during data flash rewrite.
8. Current flowing only during self programming.
9. For shift time to the SNOOZE mode, see 17.3.3 SNOOZE mode in the RL78/G12 User’s Manual.
Remarks 1. fIL: Low-speed on-chip oscillator clock frequency
2. Temperature condition of the TYP. value is TA = 25°C
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 73 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
3.4 AC Characteristics
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Items
Instruction cycle (minimum
Symbol
TCY
instruction execution time)
Conditions
MIN.
TYP.
MAX.
Unit
Main system
HS (High-
2.7 V ≤ VDD ≤ 5.5 V
0.04167
1
µs
clock (fMAIN)
speed main)
2.4 V ≤ VDD < 2.7 V
0.0625
1
µs
operation
mode
During self
HS (High-
2.7 V ≤ VDD ≤ 5.5 V
0.04167
1
µs
programming
speed main)
2.4 V ≤ VDD < 2.7 V
0.0625
1
µs
2.7 V ≤ VDD ≤ 5.5 V
1.0
20.0
MHz
2.4 V ≤ VDD < 2.7 V
1.0
16.0
MHz
2.7 V ≤ VDD ≤ 5.5 V
24
ns
2.4 V ≤ VDD < 2.7 V
30
ns
1/fMCK +
ns
mode
External main system clock
fEX
frequency
External main system clock
tEXH, tEXL
input high-level width, lowlevel width
TI00 to TI07 input high-level
tTIH, tTIL
width, low-level width
TO00 to TO07 output
10
fTO
frequency
PCLBUZ0, or PCLBUZ1
fPCL
output frequency
INTP0 to INTP5 input high-
4.0 V ≤ VDD ≤ 5.5 V
12
MHz
2.7 V ≤ VDD < 4.0 V
8
MHz
2.4 V ≤ VDD < 2.7 V
4
MHz
4.0 V ≤ VDD ≤ 5.5 V
16
MHz
2.7 V ≤ VDD < 4.0 V
8
MHz
2.4 V ≤ VDD < 2.7 V
4
MHz
tINTH, tINTL
1
µs
tKR
250
ns
tRSL
10
µs
level width, low-level width
KR0 to KR9 input available
width
RESET low-level width
Remark
fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the timer clock select register 0 (TPS0) and the CKS0n bit of timer mode
register 0n (TMR0n). n: Channel number (n = 0 to 7))
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 74 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
Minimum Instruction Execution Time during Main System Clock Operation
TCY vs VDD (HS (high-speed main) mode)
Cycle time TCY [µs]
10
1.0
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
0.1
0.0625
0.04167
0.01
0
1.0
2.0
3.0
2.4 2.7
4.0
5.0
6.0
5.5
Supply voltage VDD [V]
AC Timing Test Point
VIH/VOH
VIL/VOL
Test points
VIH/VOH
VIL/VOL
External Main System Clock Timing
1/fEX
tEXL
tEXH
EXCLK
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 75 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
TI/TO Timing
tTIH
tTIL
TI00 to TI07
1/fTO
TO00 to TO07
Interrupt Request Input Timing
tINTH
tINTL
INTP0 to INTP5
Key Interrupt Input Timing
tKR
KR0 to KR9
RESET Input Timing
tRSL
RESET
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 76 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
3.5 Peripheral Functions Characteristics
AC Timing Test Point
VIH/VOH
VIH/VOH
Test points
VIL/VOL
VIL/VOL
3.5.1 Serial array unit
(1) During communication at same potential (UART mode)
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
Transfer rate
Note 1
Unit
MAX.
fMCK/12
bps
2.0
Mbps
Theoretical value of the maximum transfer rate
fCLK = fMCKNote 2
Notes 1.
2.
Transfer rate in the SNOOZE mode is 4800 bps only.
The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V)
16 MHz (2.4 V ≤ VDD ≤ 5.5 V)
Caution
Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
UART mode connection diagram (during communication at same potential)
TxDq
Rx
RL78
microcontroller
User's device
RxDq
Tx
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Remarks 1.
2.
q: UART number (q = 0 to 2), g: PIM, POM number (g = 0, 1)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial
mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10, 11))
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 77 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
SCKp cycle time
tKCY1
SCKp high-/low-level width
SIp setup time (to SCKp↑)
Note 1
SIp hold time (from SCKp↑) Note 2
Delay time from SCKp↓ to
tKCY1 ≥ 4/fCLK
Unit
MAX.
2.7 V ≤ VDD ≤ 5.5 V
334
ns
2.4 V ≤ VDD ≤ 5.5 V
500
ns
tKH1,
4.0 V ≤ VDD ≤ 5.5 V
tKCY1/2–24
ns
tKL1
2.7 V ≤ VDD ≤ 5.5 V
tKCY1/2–36
ns
2.4 V ≤ VDD ≤ 5.5 V
tKCY1/2–76
ns
4.0 V ≤ VDD ≤ 5.5 V
66
ns
2.7 V ≤ VDD ≤ 5.5 V
66
ns
2.4 V ≤ VDD ≤ 5.5 V
113
ns
38
ns
tSIK1
tKSI1
tKSO1
C = 30 pF
Note 4
50
ns
SOp output Note 3
Notes 1.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4.
C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp and SCKp pins
by using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1,
POM4).
Remarks 1. p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3))
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 78 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
SCKp cycle time Note 5
tKCY2
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD ≤ 5.5 V
Unit
MAX.
20 MHz < fMCK
16/fMCK
ns
fMCK ≤ 20 MHz
12/fMCK
ns
16 MHz < fMCK
16/fMCK
ns
fMCK ≤ 16 MHz
12/fMCK
ns
12/fMCK
ns
2.4 V ≤ VDD ≤ 5.5 V
and 1000
SCKp high-/low-level width
SIp setup time (to SCKp↑)
tKH2,
4.0 V ≤ VDD ≤ 5.5 V
tKCY2/2–14
ns
tKL2
2.7 V ≤ VDD ≤ 5.5 V
tKCY2/2–16
ns
tSIK2
Note 1
2.4 V ≤ VDD ≤ 5.5 V
tKCY2/2–36
ns
2.7 V ≤ VDD ≤ 5.5 V
1/fMCK + 40
ns
2.4 V ≤ VDD ≤ 5.5 V
1/fMCK + 60
ns
1/fMCK + 62
ns
tKSI2
SIp hold time
(from SCKp↑) Note 2
Delay time from SCKp↓ to
SOp output
tKSO2
C = 30 pF Note 4
Note 3
Notes 1.
2.7 V ≤ VDD ≤ 5.5 V
2/fMCK + 66
ns
2.4 V ≤ VDD ≤ 5.5 V
2/fMCK + 113
ns
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4.
C is the load capacitance of the SOp output lines.
5.
Transfer rate in the SNOOZE mode: MAX. 1 Mbps.
Caution Select the normal input buffer for the SIp and SCKp pins and the normal output mode for the SOp pin
by using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1,
POM4).
CSI mode connection diagram (during communication at same potential)
SCKp
RL78
microcontroller
SIp
SOp
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
SCK
SO User's device
SI
Page 79 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
t KCY1, 2
t KL1, 2
t KH1, 2
SCKp
t SIK1, 2
SIp
t KSI1, 2
Input data
t KSO1, 2
Output data
SOp
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1, 2
tKH1, 2
tKL 1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Remarks 1.
2.
Output data
p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial
mode register mn (SMRmn). m: Unit number (m = 0,1), n: Channel number (n = 0, 1, 3))
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 80 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(4) During communication at same potential (simplified I2C mode)
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
fSCL
Cb = 100 pF, Rb = 3 kΩ
Hold time when SCLr = “L”
tLOW
Cb = 100 pF, Rb = 3 kΩ
4600
Hold time when SCLr = “H”
tHIGH
Cb = 100 pF, Rb = 3 kΩ
4600
tSU:DAT
Cb = 100 pF, Rb = 3 kΩ
Data hold time (transmission)
tHD:DAT
Cb = 100 pF, Rb = 3 kΩ
Notes 1.
2.
MAX.
100 Note 1
SCLr clock frequency
Data setup time (reception)
Unit
1/fMCK + 580
kHz
ns
ns
Note 2
ns
0
1420
ns
The value must be equal to or less than fMCK/4.
Set tSU:DAT so that it will not exceed the hold time when SCLr = “L” or SCLr = “H”.
Caution Select the N-ch open drain output (VDD tolerance) mode for SDAr by using port output mode register
h (POMh).
Simplified I2C mode connection diagram (during communication at same potential)
VDD
Rb
SDAr
SDA
RL78
microcontroller
User's device
SCLr
SCL
Simplified I2C mode serial transfer timing (during communication at same potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD:DAT
Remarks 1.
tSU:DAT
Rb [Ω]:Communication line (SDAr) pull-up resistance
Cb [F]: Communication line (SCLr, SDAr) load capacitance
2.
3.
r: IIC number (r = 00, 01, 11, 20), h: = POM number (h = 0, 1, 4, 5)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn).
m: Unit number (m = 0, 1), n: Channel number (0, 1, 3))
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 81 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode)
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
HS (high-speed main)
Conditions
Unit
Mode
MIN.
Reception
Transfer
rate Note4
4.0 V ≤ VDD ≤ 5.5 V,
MAX.
fMCK/12
bps
Note 1
2.7 V ≤ Vb ≤ 4.0 V
2.0
Mbps
fMCK/12
bps
Theoretical value of the maximum
transfer rate
fMCK = fCLKNote 2
2.7 V ≤ VDD < 4.0 V,
Note 1
2.3 V ≤ Vb ≤ 2.7 V
2.0
Mbps
fMCK/12
bps
Theoretical value of the maximum
transfer rate
fMCK = fCLKNote 2
2.4 V ≤ VDD < 3.3 V,
Note 1
1.6 V ≤ Vb ≤ 2.0 V
2.0
Mbps
Note 3
bps
2.0
Mbps
Theoretical value of the maximum
transfer rate
fMCK = fCLKNote 2
Transmission
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
Theoretical value of the maximum
Note 4
transfer rate
Cb = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V
2.7 V ≤ VDD < 4.0 V,
Note 5
bps
1.2
Mbps
2.3 V ≤ Vb ≤ 2.7 V,
Theoretical value of the maximum
Note 6
transfer rate
Cb = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V
Notes
2.4 V ≤ VDD < 3.3 V,
bps
2, 7
1.6 V ≤ Vb ≤ 2.0 V
Theoretical value of the maximum
0.43
Mbps
Note 8
transfer rate
Cb = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V
Notes 1.
2.
Transfer rate in the SNOOZE mode is 4800 bps only.
The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V)
16 MHz (2.4 V ≤ VDD ≤ 5.5 V)
3.
The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V ≤ VDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V
1
Maximum transfer rate =
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
2.2
{–Cb × Rb × ln (1 – Vb )} × 3
[bps]
Page 82 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
1
2.2
Transfer rate × 2 – {–Cb × Rb × ln (1 – Vb )}
Baud rate error (theoretical value) =
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
4.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
5.
The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid
Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ VDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V
1
Maximum transfer rate =
2.0
{–Cb × Rb × ln (1 – Vb )} × 3
[bps]
2.0
1
Transfer rate × 2 – {–Cb × Rb × ln (1 – Vb )}
Baud rate error (theoretical value) =
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
6.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer.
7.
The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
1
Maximum transfer rate =
1.5
{–Cb × Rb × ln (1 – Vb )} × 3
[bps]
1.5
1
Transfer rate × 2 – {–Cb × Rb × ln (1 – Vb )}
Baud rate error (theoretical value) =
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
8.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 7 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for
the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg).
For VIH and VIL, see the DC characteristics with TTL input buffer selected.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 83 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
UART mode connection diagram (during communication at different potential)
Vb
Rb
TxDq
Rx
RL78
microcontroller
User's device
RxDq
Tx
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Remarks 1. Rb[Ω]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance,
Vb[V]: Communication line voltage
2. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10, 11))
4. UART0 of the 20- and 24-pin products supports communication at different potential only when the
peripheral I/O redirection function is not used.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 84 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output) (1/3)
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
SCKp cycle time
tKCY1
tKCY1 ≥ 4/fCLK
4.0 V ≤ VDD ≤ 5.5 V,
Unit
MAX.
600
ns
1000
ns
2300
ns
tKCY1/2 –150
ns
tKCY1/2 –340
ns
tKCY1/2 –916
ns
tKCY1/2 –24
ns
tKCY1/2 –36
ns
tKCY1/2 –100
ns
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SCKp high-level width
tKH1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SCKp low-level width
tKL1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Cautions 1.
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode
for the SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode
register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
2.
Remarks 1.
CSI01 and CSI11 cannot communicate at different potential.
Rb [Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SCKp, SOp)
load capacitance, Vb [V]: Communication line voltage
2.
p: CSI number (p = 00, 20)
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 85 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output) (2/3)
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
SIp setup time (to SCKp↑)
tSIK1
Note
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Unit
MAX.
162
ns
354
ns
958
ns
38
ns
38
ns
38
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SIp hold time
tKSI1
(from SCKp↑) Note
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Delay time from SCKp↓ to
tKSO1
SOp output Note
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
200
ns
390
ns
966
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Note
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
(Cautions and Remarks are listed on the next page.)
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 86 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output) (3/3)
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
SIp setup time (to SCKp↓)
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
tSIK1
Note
Unit
MAX.
88
ns
88
ns
220
ns
38
ns
38
ns
38
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
tKSI1
SIp hold time
(from SCKp↓) Note
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Delay time from SCKp↑ to
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
tKSO1
SOp output Note
50
ns
50
ns
50
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Note
When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Cautions 1.
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode
for the SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode
register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
2.
Remarks 1.
CSI01 and CSI11 cannot communicate at different potential.
Rb [Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SCKp, SOp)
load capacitance, Vb [V]: Communication line voltage
2.
p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0)
CSI mode connection diagram (during communication at different potential)
Vb
Vb
Rb
SCKp
RL78
microcontroller
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Rb
SCK
SIp
SO
SOp
SI
User's device
Page 87 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1)
t KCY1
t KL1
t KH1
SCKp
t SIK1
SIp
t KSI1
Input data
t KSO1
SOp
Output data
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
t KCY1
t KL1
t KH1
SCKp
t SIK1
SIp
t KSI1
Input data
t KSO1
Output data
SOp
Remark
p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0)
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 88 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Unit
Mode
MIN.
SCKp cycle time Note 1
tKCY2
MAX.
4.0 V ≤ VDD ≤ 5.5 V,
20 MHz < fMCK ≤ 24 MHz
24/fMCK
ns
2.7 V ≤ Vb ≤ 4.0 V
8 MHz < fMCK ≤ 20 MHz
20/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK
ns
fMCK ≤ 4 MHz
12/fMCK
ns
2.7 V ≤ VDD < 4.0 V,
20 MHz < fMCK ≤ 24 MHz
32/fMCK
ns
2.3 V ≤ Vb ≤ 2.7 V
16 MHz < fMCK ≤ 20 MHz
28/fMCK
ns
8 MHz < fMCK ≤ 16 MHz
24/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK
ns
fMCK ≤ 4 MHz
12/fMCK
ns
2.4 V ≤ VDD < 3.3 V,
20 MHz < fMCK ≤ 24 MHz
72/fMCK
ns
1.6 V ≤ Vb ≤ 2.0 V
16 MHz < fMCK ≤ 20 MHz
64/fMCK
ns
8 MHz < fMCK ≤ 16 MHz
52/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
32/fMCK
ns
fMCK ≤ 4 MHz
20/fMCK
ns
SCKp high-/low-level
tKH2,
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V
tKCY2/2 – 24
ns
width
tKL2
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V
tKCY2/2 – 36
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
tKCY2/2 – 100
ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ VDD ≤ 4.0 V
1/fMCK + 40
ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V
1/fMCK + 40
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ VDD ≤ 2.0 V
1/fMCK + 60
ns
1/fMCK + 62
ns
tSIK2
SIp setup time
(to SCKp↑) Note 2
tKSI2
SIp hold time
(from SCKp↑) Note 3
Delay time from SCKp↓ to
tKSO2
SOp output Note 4
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
2/fMCK +
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
2/fMCK +
2/fMCK +
Cb = 30 pF, Rb = 5.5 kΩ
Notes 1.
2.
ns
428
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
ns
240
Cb = 30 pF, Rb = 1.4 kΩ
ns
1146
Transfer rate in the SNOOZE mode: MAX. 1 Mbps
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Cautions
1. Select the TTL input buffer for the SIp and SCKp pins and the N-ch open drain output (VDD
tolerance) mode for the SOp pin by using port input mode register 1 (PIM1) and port output
mode register 1 (POM1).
For VIH and VIL, see the DC characteristics with TTL input buffer
selected.
2. CSI01 and CSI11 cannot communicate at different potential.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 89 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
CSI mode connection diagram (during communication at different potential)
Vb
Rb
SCKp
RL78
microcontroller
SCK
SIp
SO
SOp
SI
User's device
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
t KCY2
t KL2
t KH2
SCKp
t SIK2
t KSI2
Input data
SIp
t KSO2
SOp
Output data
Remarks 1. Rb [Ω]: Communication line (SOp) pull-up resistance, Cb [F]: Communication line (SOp) load capacitance,
Vb [V]: Communication line voltage
2. p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn))
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 90 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
t KCY2
t KL2
t KH2
SCKp
t SIK2
t KSI2
Input data
SIp
t KSO2
SOp
Remark
Output data
p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0)
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 91 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode)
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Unit
Mode
MIN.
SCLr clock frequency
fSCL
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
MAX.
100Note1
kHz
100Note1
kHz
100Note1
kHz
Cb = 100 pF, Rb = 2.8 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
Hold time when SCLr = “L”
tLOW
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
4600
ns
4600
ns
4650
ns
2700
ns
2400
ns
1830
ns
1/fMCK
ns
Cb = 100 pF, Rb = 2.8 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
Hold time when SCLr = “H”
tHIGH
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
Data setup time (reception)
tSU:DAT
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
Data hold time (transmission)
tHD:DAT
+ 760 Note2
1/fMCK
ns
+ 760 Note2
1/fMCK
ns
+ 570 Note2
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
0
1420
ns
0
1420
ns
0
1215
ns
Cb = 100 pF, Rb = 2.8 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
Notes 1.
2.
The value must be equal to or less than fMCK/4.
Set tSU:DAT so that it will not exceed the hold time when SCLr = “L” or SCLr = “H”.
Cautions 1. Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin
and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode
register 1 (PIM1) and port output mode register 1 (POM1).
For VIH and VIL, see the DC
characteristics with TTL input buffer selected.
2. IIC01 and IIC11 cannot communicate at different potential.
(Remarks are listed on the next page.)
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 92 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
Simplified I2C mode connection diagram (during communication at different potential)
Vb
Vb
Rb
Rb
SDAr
SDA
RL78
microcontroller
User's device
SCLr
SCL
Simplified I2C mode serial transfer timing (during communication at different potential)
1/fSCL
t LOW
t HIGH
SCLr
SDAr
t HD : DAT
Remarks 1.
t SU : DAT
Rb [Ω]: Communication line (SDAr, SCLr) pull-up resistance, Cb [F]: Communication line (SDAr, SCLr)
load capacitance, Vb [V]: Communication line voltage
2.
r: IIC Number (r = 00, 20)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn).
m: Unit number (m = 0,1), n: Channel number (n = 0))
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 93 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
3.5.2 Serial interface IICA
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) mode
Standard Mode
MIN.
MAX.
Fast mode: fCLK ≥ 3.5 MHz
Unit
Fast Mode
MIN.
MAX.
0
400
SCLA0 clock frequency
fSCL
Setup time of restart condition
tSU:STA
4.7
0.6
µs
Hold timeNote 1
tHD:STA
4.0
0.6
µs
Hold time when SCLA0 = “L”
tLOW
4.7
1.3
µs
Hold time when SCLA0 = “H”
tHIGH
4.0
0.6
µs
tSU:DAT
250
100
ns
tHD:DAT
0
Setup time of stop condition
tSU:STO
4.0
0.6
µs
Bus-free time
tBUF
4.7
1.3
µs
Normal mode: fCLK ≥ 1 MHz
Data setup time (reception)
Data hold time (transmission)
Notes 1.
2.
Note 2
0
100
3.45
kHz
kHz
0
0.9
µs
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Caution
Only in the 30-pin products, the values in the above table are applied even when bit 2 (PIOR2) in the
peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1,
VOL1) must satisfy the values in the redirect destination.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Normal mode:
Fast mode:
Cb = 400 pF, Rb = 2.7 kΩ
Cb = 320 pF, Rb = 1.1 kΩ
IICA serial transfer timing
t LOW
tR
SCLA0
tHD:DAT
tHD:STA
t HIGH
tF
tSU:STA
tHD:STA
tSU:STO
tSU:DAT
SDAA0
t BUF
Stop
condition
Start
condition
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Restart
condition
Stop
condition
Page 94 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
3.6 Analog Characteristics
3.6.1 A/D converter characteristics
Classification of A/D converter characteristics
Input channel
Reference Voltage
Reference voltage (+) = AVREFP
Reference voltage (+) = VDD
Reference voltage (+) = VBGR
Reference voltage (–) = AVREFM
Reference voltage (–) = VSS
Reference voltage (–) = AVREFM
ANI0 to ANI3
Refer to 3.6.1 (1).
Refer to 3.6.1 (3).
Refer to 3.6.1 (4).
ANI16 to ANI22
Refer to 3.6.1 (2).
Internal reference voltage
Refer to 3.6.1 (1).
–
Temperature sensor
output voltage
(1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (–) = AVREFM/ANI1
(ADREFM = 1), target pin: ANI2, ANI3, internal reference voltage, and temperature sensor output voltage
(TA = –40 to +105°C, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (–) =
AVREFM = 0 V)
Parameter
Resolution
Symbol
Conditions
RES
Note 1
MIN.
TYP.
8
Overall error
AINL
10-bit resolution
AVREFP = VDD Note 3
Conversion time
tCONV
10-bit resolution
Target pin: ANI2, ANI3
10-bit resolution
Target pin: Internal
reference voltage, and
temperature sensor
output voltage
(HS (high-speed main)
mode)
1.2
MAX.
Unit
10
bit
±3.5
LSB
3.6 V ≤ VDD ≤ 5.5 V
2.125
39
µs
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
µs
2.4 V ≤ VDD ≤ 5.5 V
17
39
µs
3.6 V ≤ VDD ≤ 5.5 V
2.375
39
µs
2.7 V ≤ VDD ≤ 5.5 V
3.5625
39
µs
2.4 V ≤ VDD ≤ 5.5 V
17
39
µs
Zero-scale errorNotes 1, 2
EZS
10-bit resolution
AVREFP = VDD Note 3
±0.25
%FSR
Full-scale errorNotes 1, 2
EFS
10-bit resolution
AVREFP = VDD Note 3
±0.25
%FSR
Integral linearity errorNote 1
ILE
10-bit resolution
AVREFP = VDD Note 3
±2.5
LSB
Differential linearity error
DLE
10-bit resolution
AVREFP = VDD Note 3
±1.5
LSB
Note 1
Analog input voltage
VAIN
ANI2, ANI3
Internal reference voltage
(HS (high-speed main) mode)
Temperature sensor output voltage
(HS (high-speed main) mode)
0
AVREFP
V
VBGR Note 4
V
VTMPS25 Note 4
V
(Notes are listed on the next page.)
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 95 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD.
4. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics.
(2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (–) = AVREFM/ANI1
(ADREFM = 1), target pin: ANI16 to ANI22
(TA = –40 to +105°C, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (–) =
AVREFM = 0 V)
Parameter
Resolution
Symbol
Conditions
RES
Overall error
Note 1
AINL
MIN.
TYP.
8
10-bit resolution
1.2
MAX.
Unit
10
bit
±5.0
LSB
AVREFP = VDD Note 3
Conversion time
tCONV
3.6 V ≤ VDD ≤ 5.5 V
2.125
39
µs
Target ANI pin: ANI16 to ANI22 2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
µs
17
39
µs
±0.35
%FSR
±0.35
%FSR
±3.5
LSB
±2.0
LSB
AVREFP
V
10-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
Zero-scale error Notes 1, 2
EZS
10-bit resolution
AVREFP = VDD Note 3
Full-scale error Notes 1, 2
EFS
10-bit resolution
AVREFP = VDD Note 3
Integral linearity error Note 1
ILE
10-bit resolution
AVREFP = VDD Note 3
Differential linearity
DLE
error Note 1
10-bit resolution
AVREFP = VDD Note 3
Analog input voltage
VAIN
ANI16 to ANI22
0
and VDD
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP ≤ VDD, the MAX. values are as follows.
Overall error: Add ±4.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.20%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±2.0 LSB to the MAX. value when AVREFP = VDD.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 96 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (–) = VSS (ADREFM = 0),
target pin: ANI0 to ANI3, ANI16 to ANI22, internal reference voltage, and temperature sensor output voltage
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage (–) = VSS)
Parameter
Symbol
Resolution
Conditions
RES
Note 1
MIN.
TYP.
8
Unit
10
bit
±7.0
LSB
39
µs
Overall error
AINL
10-bit resolution
Conversion time
tCONV
10-bit resolution
3.6 V ≤ VDD ≤ 5.5 V
2.125
Target pin: ANI0 to ANI3,
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
µs
2.4 V ≤ VDD ≤ 5.5 V
17
39
µs
2.375
39
µs
3.5625
39
µs
17
39
µs
ANI16 to ANI22
Conversion time
tCONV
1.2
MAX.
3.6 V ≤ VDD ≤ 5.5 V
Target pin: internal reference 2.7 V ≤ VDD ≤ 5.5 V
voltage, and temperature
2.4 V ≤ VDD ≤ 5.5 V
sensor output voltage (HS
10-bit resolution
(high-speed main) mode)
Notes 1, 2
Zero-scale error
Notes 1, 2
Full-scale error
Integral linearity error
Note 1
Differential linearity error
Analog input voltage
Note 1
EZS
10-bit resolution
±0.60
%FSR
EFS
10-bit resolution
±0.60
%FSR
ILE
10-bit resolution
±4.0
LSB
DLE
10-bit resolution
±2.0
LSB
VAIN
ANI0 to ANI3, ANI16 to ANI22
VDD
V
0
Internal reference voltage
VBGR
Note 3
V
(HS (high-speed main) mode)
Temperature sensor output voltage
VTMPS25 Note 3
V
(HS (high-speed main) mode)
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 97 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (–) =
AVREFM (ADREFM = 1), target pin: ANI0, ANI2, ANI3, and ANI16 to ANI22
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = VBGR Note 3, Reference voltage (–) =
AVREFM Note 4 = 0 V, HS (high-speed main) mode)
Parameter
Symbol
Resolution
Conditions
MIN.
RES
Conversion time
Notes 1, 2
Zero-scale error
Integral linearity error
Note 1
Differential linearity error
Note 1
Analog input voltage
TYP.
MAX.
8
tCONV
8-bit resolution
EZS
Unit
bit
39
µs
8-bit resolution
±0.60
%FSR
ILE
8-bit resolution
±2.0
LSB
DLE
8-bit resolution
±1.0
LSB
VAIN
17
0
VBGR
Note 3
V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics.
4. When reference voltage (–) = VSS, the MAX. values are as follows.
Zero-scale error: Add ±0.35%FSR to the MAX. value when reference voltage (–) = AVREFM.
Integral linearity error: Add ±0.5 LSB to the MAX. value when reference voltage (–) = AVREFM.
Differential linearity error: Add ±0.2 LSB to the MAX. value when reference voltage (–) = AVREFM.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 98 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
3.6.2 Temperature sensor/internal reference voltage characteristics
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, HS (high-speed main) mode
Parameter
Symbol
Temperature sensor output voltage
VTMPS25
Conditions
MIN.
Setting ADS register = 80H,
TYP.
MAX.
1.05
Unit
V
TA = +25°C
Internal reference voltage
VBGR
Temperature coefficient
FVTMPS
Setting ADS register = 81H
1.38
Temperature sensor output
1.45
1.50
–3.6
V
mV/°C
voltage that depends on the
temperature
Operation stabilization wait time
tAMP
5
µs
3.6.3 POR circuit characteristics
(TA = –40 to +105°C, VSS = 0 V)
Parameter
Symbol
Detection voltage
VPOR
Conditions
The power supply voltage is
MIN.
TYP.
MAX.
Unit
1.45
1.51
1.57
V
1.44
1.50
1.56
V
rising.
VPDR
The power supply voltage is
falling.
Minimum pulse width Note
Note
TPW
300
µs
Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required
for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or
the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation
status control register (CSC).
TPW
Supply voltage (VDD)
VPOR
VPDR or 0.7 V
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 99 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
3.6.4 LVD circuit characteristics
LVD Detection Voltage of Reset Mode and Interrupt Mode
(TA = –40 to +105°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Detection supply voltage
Symbol
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Minimum pulse width
Detection delay time
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
tLW
Conditions
MIN.
TYP.
MAX.
Unit
The power supply voltage is rising.
3.90
4.06
4.22
V
The power supply voltage is falling.
3.83
3.98
4.13
V
The power supply voltage is rising.
3.60
3.75
3.90
V
The power supply voltage is falling.
3.53
3.67
3.81
V
The power supply voltage is rising.
3.01
3.13
3.25
V
The power supply voltage is falling.
2.94
3.06
3.18
V
The power supply voltage is rising.
2.90
3.02
3.14
V
The power supply voltage is falling.
2.85
2.96
3.07
V
The power supply voltage is rising.
2.81
2.92
3.03
V
The power supply voltage is falling.
2.75
2.86
2.97
V
The power supply voltage is rising.
2.70
2.81
2.92
V
The power supply voltage is falling.
2.64
2.75
2.86
V
The power supply voltage is rising.
2.61
2.71
2.81
V
The power supply voltage is falling.
2.55
2.65
2.75
V
The power supply voltage is rising.
2.51
2.61
2.71
V
The power supply voltage is falling.
2.45
2.55
2.65
300
V
µs
300
µs
Page 100 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
LVD detection voltage of interrupt & reset mode
(TA = –40 to +105°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Interrupt and reset
VLVDD0
mode
VLVDD1
Conditions
MIN.
TYP.
MAX.
Unit
2.64
2.75
2.86
V
Rising reset release voltage
2.81
2.92
3.03
V
Falling interrupt voltage
2.75
2.86
2.97
V
Rising reset release voltage
2.90
3.02
3.14
V
Falling interrupt voltage
2.85
2.96
3.07
V
Rising reset release voltage
3.90
4.06
4.22
V
Falling interrupt voltage
3.83
3.98
4.13
V
VPOC2, VPOC1, VPOC1 = 0, 1, 1, falling reset voltage
VLVDD2
VLVDD3
LVIS1, LVIS0 = 1, 0
LVIS1, LVIS0 = 0, 1
LVIS1, LVIS0 = 0, 0
3.6.5 Power supply voltage rising slope characteristics
(TA = –40 to +105°C, VSS = 0 V)
Parameter
Power supply voltage rising slope
Caution
Symbol
Conditions
SVDD
MIN.
TYP.
MAX.
Unit
54
V/ms
Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the
operating voltage range shown in 3.4 AC Characteristics.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 101 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
3.7 RAM Data Retention Characteristics
(TA = –40 to +105°C, VSS = 0 V)
Parameter
Data retention supply voltage
Note
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
5.5
V
1.44 Note
VDDDR
This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage
reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated.
Operation mode
STOP mode
RAM data retention
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
3.8 Flash Memory Programming Characteristics
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
System clock frequency
fCLK
Code flash memory rewritable times
Cerwr
Conditions
MIN.
TYP.
1
Retained for 20 years
Notes 1, 2, 3
TA = 85°C
Data flash memory rewritable times
Retained for 1 year
Notes 1, 2, 3
TA = 25°C
Unit
24
MHz
Times
Note 4
Retained for 5 years
TA = 85°C
1,000
MAX.
1,000,000
100,000
Note 4
Retained for 20 years
10,000
TA = 85°C Note 4
Notes 1.
1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the
rewrite.
2.
When using flash memory programmer and Renesas Electronics self programming library
3.
These are the characteristics of the flash memory and the results obtained from reliability testing by
Renesas Electronics Corporation.
4.
This temperature is the average value at which data are retained.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 102 of 108
RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
3.9 Dedicated Flash Memory Programmer Communication (UART)
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Transfer rate
Conditions
MIN.
During serial programming
TYP.
115,200
MAX.
Unit
1,000,000
bps
3.10 Timing of Entry to Flash Memory Programming Modes
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Time to complete the communication for the initial
tSUINIT
setting after the external reset is released
Conditions
MIN.
POR and LVD reset are released
TYP.
MAX.
Unit
100
ms
before external release
Time to release the external reset after the TOOL0
POR and LVD reset are released
tSU
10
µs
1
ms
before external release
pin is set to the low level
Time to hold the TOOL0 pin at the low level after the tHD
POR and LVD reset are released
external reset is released
before external release
(excluding the processing time of the firmware to
control the flash memory)
RESET
tHD + software
processing
time
1-byte data for
setting mode
TOOL0
tSU
tSUINIT
The low level is input to the TOOL0 pin.
The external reset is released (POR and LVD reset must be released before the external
reset is released.).
The TOOL0 pin is set to the high level.
Setting of the flash memory programming mode by UART reception and complete the baud
rate setting.
Remark tSUINIT: Communication for the initial setting must be completed within 100 ms after the external reset is released
during this period.
tSU:
Time to release the external reset after the TOOL0 pin is set to the low level
tHD:
Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing
time of the firmware to control the flash memory)
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 103 of 108
RL78/G12
4. PACKAGE DRAWINGS
4. PACKAGE DRAWINGS
4.1 20-pin package
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LSSOP20-4.4x6.5-0.65
PLSP0020JB-A
P20MA-65-NAA-1
0.1
2
D
detail of lead end
11
20
E
1
c
10
1
L
3
bp
A
A2
A1
HE
e
y
(UNIT:mm)
NOTE
1.Dimensions “
2.Dimension “
1” and “
2”
” does not include tr
ITEM
DIMENSIONS
D
E
6.50 0.10
4.40 0.10
HE
6.40 0.20
A
1.45 MAX.
A1
0.10 0.10
A2
1.15
e
bp
c
L
y
0.65 0.12
0.22 0.10
0.05
0.15 0.05
0.02
0.50 0.20
0.10
0 to 10
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 104 of 108
RL78/G12
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
4. PACKAGE DRAWINGS
Page 105 of 108
RL78/G12
4. PACKAGE DRAWINGS
4.2 24-pin package
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-HWQFN24-4x4-0.50
PWQN0024KE-A
P24K8-50-CAB-1
0.04
D
DETAIL OF A PART
E
S
A
A
S
y
S
(UNIT:mm)
ITEM
D2
A
EXPOSED DIE PAD
1
6
D
4.00 0.05
E
4.00 0.05
A
0.75 0.05
b
0.25 0.05
0.07
e
7
24
Lp
B
DIMENSIONS
0.50
0.40 0.10
x
0.05
y
0.05
E2
ITEM
19
12
18
EXPOSED
DIE PAD
VARIATIONS
13
D2
E2
MIN NOM MAX MIN NOM MAX
A 2.45 2.50 2.55 2.45 2.50 2.55
e
Lp
b
x
M
S AB
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 106 of 108
RL78/G12
4. PACKAGE DRAWINGS
JEITA Package code
RENESAS code
MASS(TYP.)[g]
P-HWQFN024-4x4-0.50
PWQN0024KF-A
0.04
2X
aaa C
18
13
19
12
D
INDEX AREA
(D/2 X E/2)
24
2X
7
aaa C
6
1
A
E
B
ccc C
C
SEATING PLANE
A (A3) A1
b(24X)
e
24X
bbb
ddd
eee C
E2
fff
1
fff
C A B
24
7
EXPOSED DIE PAD
D2
19
12
18
13
L(24X)
Reference
Symbol
Dimension in Millimeters
Min.
Nom.
A
–
–
0.80
A1
0.00
0.02
0.05
A3
6
C A B
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
C A B
C
K(24X)
b
Max.
0.203 REF.
0.18
D
0.25
0.30
4.00 BSC
E
4.00 BSC
e
0.50 BSC
L
0.35
0.40
0.45
K
0.20
–
–
D2
2.55
2.60
2.65
E2
2.55
2.60
2.65
aaa
0.15
bbb
0.10
ccc
0.10
ddd
0.05
eee
0.08
fff
0.10
Page 107 of 108
RL78/G12
4. PACKAGE DRAWINGS
4.3 30-pin package
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LSSOP30-0300-0.65
PLSP0030JB-B
S30MC-65-5A4-3
0.18
30
16
detail of lead end
F
G
T
P
1
L
15
U
E
A
H
I
J
S
C
D
N
M
S
B
M
K
ITEM
A
MILLIMETERS
9.85 0.15
B
0.45 MAX.
C
0.65 (T.P.)
NOTE
D
0.24 0.08
0.07
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
E
0.1 0.05
F
1.3 0.1
G
1.2
H
8.1 0.2
I
6.1 0.2
J
1.0 0.2
K
0.17 0.03
L
0.5
M
0.13
N
0.10
P
3
T
0.25
U
0.6 0.15
5
3
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0193EJ0230 Rev.2.30
Jun 19, 2020
Page 108 of 108
Revision History
Rev.
1.00
2.00
RL78/G12 Datasheet
Date
Dec 10, 2012
Sep 06, 2013
Description
Summary
Page
1
3
4
7 to 9
14
17
First Edition issued
Modification of 1.1 Features
Modification of 1.2 List of Part Numbers
Modification of Table 1-1. List of Ordering Part Numbers, Note, and Caution
Modification of package name in 1.4.1 to 1.4.3
Modification of tables in 1.7 Outline of Functions
Modification of description of table in 2.1 Absolute Maximum Ratings (TA =
25°C)
18
18
19
20
23
Modification of table, Note, and Caution in 2.2.1 X1 oscillator characteristics
Modification of table in 2.2.2 On-chip oscillator characteristics
Modification of Note 3 in 2.3.1 Pin characteristics (1/4)
Modification of Note 3 in 2.3.1 Pin characteristics (2/4)
Modification of Notes 1 and 2 in (1) 20-, 24-pin products (1/2)
Modification of Notes 1 and 3 in (1) 20-, 24-pin products (2/2)
Modification of Notes 1 and 2 in (2) 30-pin products (1/2)
Modification of Notes 1 and 3 in (2) 30-pin products (2/2)
Modification of (3) Peripheral functions (Common to all products)
Modification of table in 2.4 AC Characteristics
Addition of Minimum Instruction Execution Time during Main System Clock
Operation
24
25
26
27
28
29
30
Modification of figures of AC Timing Test Point and External Main System
Clock Timing
31
Modification of figure of AC Timing Test Point
Modification of description and Note 2 in (1) During communication at same
potential (UART mode)
31
32
Modification of description in (2) During communication at same potential (CSI
mode)
33
Modification of description in (3) During communication at same potential (CSI
mode)
34
Modification of description in (4) During communication at same potential (CSI
mode)
36
Modification of table and Note 2 in (5) During communication at same
potential (simplified I2C mode)
38, 39
Modification of table and Notes 1 to 9 in (6) Communication at different
potential
(1.8 V, 2.5 V, 3 V) (UART mode)
40
Modification of Remarks 1 to 3 in (6) Communication at different potential (1.8
V,
2.5 V, 3 V) (UART mode)
41
Modification of table in (7) Communication at different potential (2.5 V, 3 V) (CSI
mode)
42
Modification of Caution in (7) Communication at different potential (2.5 V, 3 V) (CSI
mode)
43
Modification of table in (8) Communication at different potential (1.8 V, 2.5 V, 3
V) (CSI mode) (1/3)
44
Modification of table and Notes 1 and 2 in (8) Communication at different
potential (1.8 V, 2.5 V, 3 V) (CSI mode) (2/3)
45
Modification of table, Note 1, and Caution 1 in (8) Communication at different
potential (1.8 V, 2.5 V, 3 V) (CSI mode) (3/3)
47
Modification of table in (9) Communication at different potential (1.8 V, 2.5 V, 3
V) (CSI mode)
50
Modification of table, Note 1, and Caution 1 in (10) Communication at different
potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode)
C-1
Rev.
2.00
Page
Date
Sep 06, 2013
52
53
53
54
54
55
56
57
57
58
59
59
2.10
Mar 25, 2016
2.20
Oct 31, 2018
2.21
Jan 31, 2020
2.22
Apr 28, 2020
Description
Summary
Modification of Remark in 2.5.2 Serial interface IICA
Addition of table to 2.6.1 A/D converter characteristics
Modification of description in 2.6.1 (1)
Modification of Notes 3 to 5 in 2.6.1 (1)
Modification of description and Notes 2 to 4 in 2.6.1 (2)
Modification of description and Notes 3 and 4 in 2.6.1 (3)
Modification of description and Notes 3 and 4 in 2.6.1 (4)
Modification of table in 2.6.2 Temperature sensor/internal reference voltage
characteristics
Modification of table and Note in 2.6.3 POR circuit characteristics
Modification of table in 2.6.4 LVD circuit characteristics
Modification of table of LVD detection voltage of interrupt & reset mode
Modification of number and title to 2.6.5 Power supply voltage rising slope
characteristics
61
Modification of table, figure, and Remark in 2.10 Timing of Entry to Flash
Memory Programming Modes
62 to 103
104 to
106
Addition of products of industrial applications (G: TA = -40 to +105°C)
Addition of products of industrial applications (G: TA = -40 to +105°C)
6
Modification of Figure 1-1 Part Number, Memory Size, and Package of
RL78/G12
7
8
Modification of Table 1-1 List of Ordering Part Numbers
Addition of product name (RL78/G12) and description (Top View) in 1.4.1 20pin products
9
Addition of product name (RL78/G12) and description (Top View) in 1.4.2 24pin products
10
Addition of product name (RL78/G12) and description (Top View) in 1.4.3 30pin products
15
16
52
60
Modification of description in 1.7 Outline of Functions
Modification of description, and addition of target products
Modification of note 2 in 2.5.2 Serial interface IICA
Modification of title and note, and addition of caution in 2.7 RAM Data
Retention Characteristics
60
62
94
102
Modification of conditions in 2.8 Flash Memory Programming Characteristics
Modification of description, and addition of target products and remark
Modification of note 2 in 3.5.2 Serial interface IICA
Modification of title and note in 3.7 RAM Data Retention Characteristics
102
104 to
106
Modification of conditions in 3.8 Flash Memory Programming Characteristics
Addition of package name
4
7
3
Modification of Table 1-1 List of Ordering Part Numbers
Modification of pin configuration diagram in 1.4.1 20-pin products
Addition of packaging specifications in Figure 1-1 Part Number, Memory Size,
and Package of RL78/G12
4, 5
Addition of part numbers and RENESAS codes in Table 1-1 List of Ordering
Part Numbers
105, 106,
108
Modification of the titles of the subchapters and deletion of product names in
Chapter 4
107
3
Addition of figure in 4.2 24-pin package
Addition of packaging specifications and package type in Figure 1-1 Part
Number, Memory Size, and Package of RL78/G12
4
Addition of packaging specifications in Table 1-1 List of Ordering Part
Numbers
9
107
Addition of packaging specifications in 1.4.1 20-pin products
Addition of figure in 4.1 20-pin package
C-2
Rev.
2.30
Page
Date
Jun 19, 2020
Description
Summary
3
Modification of Figure 1-1 Part Number, Memory Size, and Package of
RL78/G12
4
Modification of Table 1-1 List of Ordering Part Numbers
All trademarks and registered trademarks are the property of their respective owners.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United
States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
C-3
General Precautions in the Handling of Microprocessing Unit and Microcontroller
Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the
products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
1.
Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps
must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be
adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.
Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor
2.
devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.
Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of
register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset
pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins
in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the
3.
level at which resetting is specified.
Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal
4.
elements. Follow the guideline for input signal during power-off state as described in your product documentation.
Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are
generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of
the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
5.
become possible.
Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program
execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator
during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal
6.
produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the
7.
input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.).
Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these
8.
addresses as the correct operation of the LSI is not guaranteed.
Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.
The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms
of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,
operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a systemevaluation test for the given product.
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by
you or third parties arising from the use of these circuits, software, or information.
2.
Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or
arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application
examples.
3.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.
4.
You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by
5.
Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the
you or third parties arising from such alteration, modification, copying or reverse engineering.
product’s quality grade, as indicated below.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; industrial robots; etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc.
Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are
not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause
serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all
liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or
other Renesas Electronics document.
6.
When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for Handling and Using Semiconductor Devices” in the
reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation
characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such specified
ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a
certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas
Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury
or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult
and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. You are responsible for carefully and
sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics
products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable
laws and regulations.
9.
Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws
or regulations. You shall comply with any applicable export control laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or
transactions.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or transfers the product to a third party, to notify such third
party in advance of the contents and conditions set forth in this document.
11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products.
(Note 1)
“Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries.
(Note 2)
“Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
(Rev.4.0-1 November 2017)
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics Corporation
TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan
Renesas Electronics America Inc. Milpitas Campus
1001 Murphy Ranch Road, Milpitas, CA 95035, U.S.A.
Tel: +1-408-432-8888, Fax: +1-408-434-5351
Renesas Electronics America Inc. San Jose Campus
6024 Silver Creek Valley Road, San Jose, CA 95138, USA
Tel: +1-408-284-8200, Fax: +1-408-284-2775
Renesas Electronics Canada Limited
9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3
Tel: +1-905-237-2004
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-6503-0, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
Room 101-T01, Floor 1, Building 7, Yard No. 7, 8th Street, Shangdi, Haidian District, Beijing 100085, China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai 200333, China
Tel: +86-21-2226-0888, Fax: +86-21-2226-0999
Renesas Electronics Hong Kong Limited
Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2265-6688, Fax: +852 2886-9022
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, #06-02 Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit No 3A-1 Level 3A Tower 8 UOA Business Park, No 1 Jalan Pengaturcara U1/51A, Seksyen U1, 40150 Shah Alam, Selangor, Malaysia
Tel: +60-3-5022-1288, Fax: +60-3-5022-1290
Renesas Electronics India Pvt. Ltd.
No.777C, 100 Feet Road, HAL 2nd Stage, Indiranagar, Bangalore 560 038, India
Tel: +91-80-67208700
Renesas Electronics Korea Co., Ltd.
17F, KAMCO Yangjae Tower, 262, Gangnam-daero, Gangnam-gu, Seoul, 06265 Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5338
© 2020 Renesas Electronics Corporation. All rights reserved.
Colophon 9.0
工商网监
湘ICP备2023018690号
