R5F109AAJSP#X0

User’s Manual 16 RL78/F12 User’s Manual: Hardware 16-Bit Single-Chip Microcontrollers All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com). www.renesas.com Rev.1.11 Jan 2014 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product. 5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below. “Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. “High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; and safety equipment etc. Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics. 6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. 7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products. 11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. (2012.4) NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. How to Use This Manual Readers This manual is intended for users who wish to understand the functions of the RL78/F12 and design application systems using the following devices. • 20-pin: R5F1096x (x = 8, A, B, C, D, E) • 30-pin: R5F109Ax (x = A, B, C, D, E) • 32-pin: R5F109Bx (x = A, B, C, D, E) • 48-pin: R5F100Gx (x = A, B, C, D, E) • 64-pin: R5F109Lx (x = A, B, C, D, E) Purpose This manual is intended to give users an understanding of the hardware functions described in the Organization below. Organization The RL78/F12 manual is divided into two parts: this manual (hardware) and the “RL78 Family User’s Manual: Software” (common to the RL78 family). RL78/F12 RL78 Family User’s Manual User’s Manual Hardware Software • Pin functions • CPU functions • Internal block functions • Instruction set • Interrupts • Explanation of each instruction • Other on-chip peripheral functions • Electrical specifications How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. • To gain a general understanding of functions: → Read this manual in the order of the CONTENTS. • How to interpret the register format: → For a bit number enclosed in angle brackets, the bit name is defined as a reserved word in the assembler, and is defined as an sfr (special function register) variable using the #pragma sfr directive in the compiler. • To know details of the RL78 Microcontroller instructions: → Refer to the separate document RL78 Family User’s Manual: Software (R01US0015E).  Conventions Data significance: Higher digits on the left and lower digits on the right Active low representations: ××× (overscore over pin and signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information ...×××× or ××××B Numerical representations: Binary ...×××× Decimal Hexadecimal Related Documents ...××××H The related documents referenced in this manual may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. RL78/F12 User’s Manual R01UH0231E RL78 Family User’s Manual: Software R01US0015E Documents Related to Flash Memory Programming Document Name PG-FP5 Flash Memory Programmer User’s Manual Document No. R20UT0008E Other Documents Document Name Document No. Renesas MPUs & MCUs RL78 Family R01CP0003E Semiconductor Package Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Semiconductor Reliability Handbook R51ZZ0001E Note See the “Semiconductor Package Mount Manual” website (http://www.renesas.com/products/package/manual/index.jsp). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document accordingly. All trademarks and registered trademarks are the property of their respective owners. EEPROM is a trademark of Renesas Electronics Corporation. Windows, Windows NT and Windows XP are registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc. CONTENTS CHAPTER 1 OUTLINE............................................................................................................................... 1 1.1 Features........................................................................................................................................... 1 1.2 Ordering Information...................................................................................................................... 3 1.3 Pin Configuration (Top View) ........................................................................................................ 4 1.3.1 20-pin products................................................................................................................................... 4 1.3.2 30-pin products................................................................................................................................... 5 1.3.3 32-pin products................................................................................................................................... 6 1.3.4 48-pin products................................................................................................................................... 7 1.3.5 64-pin products................................................................................................................................... 9 1.4 Pin Identification........................................................................................................................... 10 1.5 Block Diagram .............................................................................................................................. 11 1.5.1 20-pin products................................................................................................................................. 11 1.5.2 30-pin products................................................................................................................................. 12 1.5.3 32-pin products................................................................................................................................. 13 1.5.4 48-pin products................................................................................................................................. 14 1.5.5 64-pin products................................................................................................................................. 15 1.6 Outline of Functions..................................................................................................................... 16 CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 18 2.1 Pin Function List .......................................................................................................................... 18 2.1.1 20-pin products................................................................................................................................. 18 2.1.2 30-pin products................................................................................................................................. 19 2.1.3 32-pin products................................................................................................................................. 21 2.1.4 48-pin products................................................................................................................................. 23 2.1.5 64-pin products................................................................................................................................. 25 2.1.6 Pins for each product (pins other than port pins).............................................................................. 27 2.2 Description of Pin Functions ...................................................................................................... 30 2.2.1 P00 to P06 (port 0) ........................................................................................................................... 30 2.2.2 P10 to P17 (port 1) ........................................................................................................................... 30 2.2.3 P20 to P27 (port 2) ........................................................................................................................... 32 2.2.4 P30, P31 (port 3) .............................................................................................................................. 32 2.2.5 P40 to P43 (port 4) ........................................................................................................................... 33 2.2.6 P50 to P55 (port 5) ........................................................................................................................... 34 2.2.7 P60 to P63 (port 6) ........................................................................................................................... 35 2.2.8 P70 to P77 (port 7) ........................................................................................................................... 35 2.2.9 P120 to P124 (port 12) ..................................................................................................................... 36 2.2.10 P130, P137 (port 13) ...................................................................................................................... 37 2.2.11 P140, P141, P146, P147 (port 14) ................................................................................................. 37 Index-1 2.2.12 VDD, VSS .......................................................................................................................................... 37 2.2.13 RESET ........................................................................................................................................... 38 2.2.14 REGC ............................................................................................................................................. 38 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ........................................... 39 CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 43 3.1 Memory Space .............................................................................................................................. 43 3.1.1 Internal program memory space....................................................................................................... 52 3.1.2 Mirror area........................................................................................................................................ 55 3.1.3 Internal data memory space ............................................................................................................. 57 3.1.4 Special function register (SFR) area ................................................................................................ 58 3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area ....................... 58 3.1.6 Data memory addressing ................................................................................................................. 59 3.2 Processor Registers..................................................................................................................... 65 3.2.1 Control registers ............................................................................................................................... 65 3.2.2 General-purpose registers................................................................................................................ 67 3.2.3 ES and CS registers ......................................................................................................................... 69 3.2.4 Special function registers (SFRs) ..................................................................................................... 70 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) ........................... 75 3.3 Instruction Address Addressing................................................................................................. 83 3.3.1 Relative addressing.......................................................................................................................... 83 3.3.2 Immediate addressing ...................................................................................................................... 83 3.3.3 Table indirect addressing ................................................................................................................. 84 3.3.4 Register direct addressing................................................................................................................ 85 3.4 Addressing for Processing Data Addresses ............................................................................. 86 3.4.1 Implied addressing ........................................................................................................................... 86 3.4.2 Register addressing ......................................................................................................................... 86 3.4.3 Direct addressing ............................................................................................................................. 87 3.4.4 Short direct addressing .................................................................................................................... 88 3.4.5 SFR addressing................................................................................................................................ 89 3.4.6 Register indirect addressing ............................................................................................................. 90 3.4.7 Based addressing............................................................................................................................. 91 3.4.8 Based indexed addressing ............................................................................................................... 94 3.4.9 Stack addressing.............................................................................................................................. 95 CHAPTER 4 PORT FUNCTIONS ........................................................................................................... 96 4.1 Port Functions .............................................................................................................................. 96 4.2 Port Configuration........................................................................................................................ 96 4.2.1 Port 0................................................................................................................................................ 97 4.2.2 Port 1.............................................................................................................................................. 105 4.2.3 Port 2.............................................................................................................................................. 115 Index-2 4.2.4 Port 3.............................................................................................................................................. 117 4.2.5 Port 4.............................................................................................................................................. 120 4.2.6 Port 5.............................................................................................................................................. 124 4.2.7 Port 6.............................................................................................................................................. 132 4.2.8 Port 7.............................................................................................................................................. 135 4.2.9 Port 12............................................................................................................................................ 140 4.2.10 Port 13.......................................................................................................................................... 144 4.2.11 Port 14.......................................................................................................................................... 146 4.3 Registers Controlling Port Function ........................................................................................ 150 4.4 Port Function Operations .......................................................................................................... 164 4.4.1 Writing to I/O port ........................................................................................................................... 164 4.4.2 Reading from I/O port ..................................................................................................................... 164 4.4.3 Operations on I/O port .................................................................................................................... 164 4.4.4 Connecting to external device with different potential (2.5 V, 3 V) ................................................. 165 4.5 Settings of Port Mode Register, and Output Latch When Using Alternate Function.......... 167 4.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn).................................... 173 CHAPTER 5 CLOCK GENERATOR .................................................................................................... 174 5.1 Functions of Clock Generator................................................................................................... 174 5.2 Configuration of Clock Generator ............................................................................................ 176 5.3 Registers Controlling Clock Generator.................................................................................... 178 5.3.1 Clock operation mode control register (CMC) ................................................................................ 178 5.3.2 System clock control register (CKC)............................................................................................... 181 5.3.3 Clock operation status control register (CSC) ................................................................................ 183 5.3.4 Oscillation stabilization time counter status register (OSTC).......................................................... 184 5.3.5 Oscillation stabilization time select register (OSTS) ....................................................................... 186 5.3.6 Peripheral enable register 0 (PER0)............................................................................................... 188 5.3.7 Peripheral enable register X (PERX) .............................................................................................. 190 5.3.8 High-speed on-chip oscillator frequency select register (HOCODIV) ............................................. 191 5.3.9 Operation speed mode control register (OSMC) ............................................................................ 192 5.3.10 High-speed on-chip oscillator trimming register (HIOTRM) .......................................................... 193 5.4 System Clock Oscillator ............................................................................................................ 194 5.4.1 X1 oscillator.................................................................................................................................... 194 5.4.2 XT1 oscillator.................................................................................................................................. 194 5.4.3 High-speed on-chip oscillator ......................................................................................................... 198 5.4.4 Low-speed on-chip oscillator .......................................................................................................... 198 5.5 Clock Generator Operation ....................................................................................................... 199 5.6 Controlling Clock........................................................................................................................ 201 5.6.1 Example of setting high-speed on-chip oscillator ........................................................................... 201 5.6.2 Example of setting X1 oscillation clock........................................................................................... 202 5.6.3 Example of setting XT1 oscillation clock ........................................................................................ 203 Index-3 5.6.4 CPU clock status transition diagram............................................................................................... 204 5.6.5 Condition before changing CPU clock and processing after changing CPU clock ......................... 211 5.6.6 Time required for switchover of CPU clock and main system clock ............................................... 213 5.6.7 Conditions before clock oscillation is stopped ................................................................................ 214 CHAPTER 6 TIMER ARRAY UNIT...................................................................................................... 215 6.1 Functions of Timer Array Unit................................................................................................... 216 6.1.1 Independent channel operation function ........................................................................................ 216 6.1.2 Simultaneous channel operation function....................................................................................... 217 6.1.3 8-bit timer operation function (channels 1 and 3 only) .................................................................... 218 6.1.4 LIN-bus supporting function (channel 7 only) ................................................................................. 219 6.2 Configuration of Timer Array Unit ............................................................................................ 220 6.3 Registers Controlling Timer Array Unit.................................................................................... 228 6.4 Basic Rules of Simultaneous Channel Operation Function .................................................. 257 6.4.1 Basic Rules of Simultaneous Channel Operation Function ............................................................ 257 6.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only) ............................................. 259 6.5 Operation of Counter ................................................................................................................. 260 6.5.1 Count clock (fTCLK) .......................................................................................................................... 260 6.5.2 Start timing of counter .................................................................................................................... 262 6.5.3 Operation of counter....................................................................................................................... 263 6.6 Channel Output (TO0n pin) Control.......................................................................................... 268 6.6.1 TO0n pin output circuit configuration.............................................................................................. 268 6.6.2 TO0n Pin Output Setting ................................................................................................................ 269 6.6.3 Cautions on Channel Output Operation ......................................................................................... 270 6.6.4 Collective manipulation of TO0.n bit............................................................................................... 276 6.6.5 Timer Interrupt and TO0n Pin Output at Operation Start................................................................ 277 6.7 Independent Channel Operation Function of Timer Array Unit............................................. 278 6.7.1 Operation as interval timer/square wave output ............................................................................. 278 6.7.2 Operation as external event counter .............................................................................................. 284 6.7.3 Operation as frequency divider (channel 0 only) ............................................................................ 289 6.7.4 Operation as input pulse interval measurement ............................................................................. 293 6.7.5 Operation as input signal high-/low-level width measurement........................................................ 298 6.7.6 Operation as delay counter ............................................................................................................ 302 6.8 Simultaneous Channel Operation Function of Timer Array Unit .......................................... 307 6.8.1 Operation as one-shot pulse output function .................................................................................. 307 6.8.2 Operation as PWM function............................................................................................................ 314 6.8.3 Operation as multiple PWM output function ................................................................................... 321 CHAPTER 7 REAL-TIME CLOCK......................................................................................................... 329 7.1 Functions of Real-time Clock.................................................................................................... 329 7.2 Configuration of Real-time Clock ............................................................................................. 329 Index-4 7.3 Registers Controlling Real-time Clock..................................................................................... 331 7.4 Real-time Clock Operation ........................................................................................................ 346 7.4.1 Starting operation of real-time clock ............................................................................................... 346 7.4.2 Shifting to STOP mode after starting operation .............................................................................. 347 7.4.3 Reading/writing real-time clock....................................................................................................... 348 7.4.4 Setting alarm of real-time clock ...................................................................................................... 350 7.4.5 1 Hz output of real-time clock ......................................................................................................... 351 7.4.6 Example of watch error correction of real-time clock ...................................................................... 352 CHAPTER 8 INTERVAL TIMER ............................................................................................................ 355 8.1 Functions of Interval Timer ....................................................................................................... 355 8.2 Configuration of Interval Timer................................................................................................. 355 8.3 Registers Controlling Interval Timer ........................................................................................ 356 8.4 Interval Timer Operation ............................................................................................................ 359 CHAPTER 9 16-BIT WAKEUP TIMER ................................................................................................ 360 9.1 Overview...................................................................................................................................... 360 9.2 Configuration .............................................................................................................................. 361 9.3 Register ....................................................................................................................................... 362 9.4 Operation..................................................................................................................................... 365 9.4.1 Interval timer mode......................................................................................................................... 365 9.4.2 Cautions ......................................................................................................................................... 367 CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER............................................... 368 10.1 Functions of Clock Output/Buzzer Output Controller .......................................................... 368 10.2 Configuration of Clock Output/Buzzer Output Controller.................................................... 370 10.3 Registers Controlling Clock Output/Buzzer Output Controller ........................................... 370 10.4 Operations of Clock Output/Buzzer Output Controller ........................................................ 373 10.4.1 Operation as output pin ................................................................................................................ 373 10.5 Cautions of clock output/buzzer output controller............................................................... 374 CHAPTER 11 WATCHDOG TIMER ..................................................................................................... 375 11.1 Functions of Watchdog Timer................................................................................................. 375 11.2 Configuration of Watchdog Timer .......................................................................................... 376 11.3 Register Controlling Watchdog Timer.................................................................................... 377 11.4 Operation of Watchdog Timer................................................................................................. 378 11.4.1 Controlling operation of watchdog timer ....................................................................................... 378 11.4.2 Setting overflow time of watchdog timer ....................................................................................... 379 11.4.3 Setting window open period of watchdog timer ............................................................................ 380 11.4.4 Setting watchdog timer interval interrupt ...................................................................................... 381 Index-5 CHAPTER 12 A/D CONVERTER ......................................................................................................... 382 12.1 Function of A/D Converter....................................................................................................... 382 12.2 Configuration of A/D Converter .............................................................................................. 384 12.3 Registers Used in A/D Converter............................................................................................ 386 12.4 A/D Converter Conversion Operations .................................................................................. 413 12.5 Input Voltage and Conversion Results .................................................................................. 415 12.6 A/D Converter Operation Modes............................................................................................. 416 12.6.1 Software trigger mode (select mode, sequential conversion mode) ............................................. 416 12.6.2 Software trigger mode (select mode, one-shot conversion mode) ............................................... 417 12.6.3 Software trigger mode (scan mode, sequential conversion mode)............................................... 418 12.6.4 Software trigger mode (scan mode, one-shot conversion mode) ................................................. 419 12.6.5 Hardware trigger no-wait mode (select mode, sequential conversion mode) ............................... 420 12.6.6 Hardware trigger no-wait mode (select mode, one-shot conversion mode).................................. 421 12.6.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode) ................................. 422 12.6.8 Hardware trigger no-wait mode (scan mode, one-shot conversion mode) ................................... 423 12.6.9 Hardware trigger wait mode (select mode, sequential conversion mode) .................................... 424 12.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode)..................................... 425 12.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode) .................................... 426 12.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode) ...................................... 427 12.7 A/D Converter Setup Flowchart .............................................................................................. 428 12.7.1 Setting up software trigger mode.................................................................................................. 429 12.7.2 Setting up hardware trigger no-wait mode.................................................................................... 430 12.7.3 Setting up hardware trigger wait mode ......................................................................................... 431 12.7.4 Setup when using temperature sensor (example for hardware trigger no-wait mode) ................. 432 12.7.5 Setting up test mode .................................................................................................................... 433 12.8 SNOOZE Mode Function.......................................................................................................... 434 12.9 How to Read A/D Converter Characteristics Table............................................................... 437 12.10 Cautions for A/D Converter ................................................................................................... 439 CHAPTER 13 SERIAL ARRAY UNIT.................................................................................................. 443 13.1 Functions of Serial Array Unit................................................................................................. 445 13.1.1 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSIS0, CSIS1)........................... 445 13.1.2 UART (UART0 to UART2, UARTS0)............................................................................................ 446 13.1.3 Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) ............................................................... 447 13.2 Configuration of Serial Array Unit .......................................................................................... 448 13.3 Registers Controlling Serial Array Unit.................................................................................. 456 13.4 Operation stop mode ............................................................................................................... 486 13.4.1 Stopping the operation by units .................................................................................................... 487 13.4.2 Stopping the operation by channels ............................................................................................. 488 Index-6 13.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSIS0, CSIS1) Communication ........................................................................................................................ 489 13.5.1 Master transmission ..................................................................................................................... 492 13.5.2 Master reception........................................................................................................................... 505 13.5.3 Master transmission/reception...................................................................................................... 517 13.5.4 Slave transmission ....................................................................................................................... 530 13.5.5 Slave reception............................................................................................................................. 542 13.5.6 Slave transmission/reception........................................................................................................ 551 13.5.7 SNOOZE mode function (only CSI00) .......................................................................................... 563 13.5.8 Calculating transfer clock frequency............................................................................................. 567 13.5.9 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSIS0, CSIS1) communication ................................................................ 569 13.6 Operation of UART (UART0 to UART2, UARTS0) Communication ..................................... 570 13.6.1 UART transmission ...................................................................................................................... 573 13.6.2 UART reception............................................................................................................................ 585 13.6.3 SNOOZE mode function (only UART0 reception) ........................................................................ 594 13.6.4 Calculating baud rate ................................................................................................................... 601 13.6.5 Procedure for processing errors that occurred during UART (UART0 to UART2, UARTS0) communication............................................................................................................................. 605 13.7 LIN Communication Operation ............................................................................................... 606 13.7.1 LIN transmission........................................................................................................................... 606 13.7.2 LIN reception ................................................................................................................................ 609 13.8 Operation of Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) Communication ........ 615 13.8.1 Address field transmission............................................................................................................ 618 13.8.2 Data transmission......................................................................................................................... 624 13.8.3 Data reception .............................................................................................................................. 628 13.8.4 Stop condition generation............................................................................................................. 633 13.8.5 Calculating transfer rate ............................................................................................................... 634 13.8.6 Procedure for processing errors that occurred during simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) communication ....................................................................................................... 636 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) ............................... 637 14.1 Features..................................................................................................................................... 637 14.2 Configuration ............................................................................................................................ 639 14.3 Control Registers ..................................................................................................................... 641 14.4 Interrupt Request Signals........................................................................................................ 670 14.5 Operation................................................................................................................................... 671 14.5.1 Data format................................................................................................................................... 671 14.5.2 Data transmission......................................................................................................................... 673 14.5.3 Data reception .............................................................................................................................. 676 14.5.4 BF transmission/reception format................................................................................................. 678 Index-7 14.5.5 BF transmission............................................................................................................................ 682 14.5.6 BF reception ................................................................................................................................. 684 14.5.7 Parity types and operations .......................................................................................................... 687 14.5.8 Data consistency check................................................................................................................ 688 14.5.9 BF reception mode select function ............................................................................................... 692 14.5.10 LIN-UART reception status interrupt generation sources ........................................................... 697 14.5.11 Transmission start wait function ................................................................................................. 700 14.6 UART Buffer Mode.................................................................................................................... 701 14.6.1 UART buffer mode transmission .................................................................................................. 702 14.7 LIN Communication Automatic Baud Rate Mode ................................................................. 704 14.7.1 Automatic baud rate setting function ............................................................................................ 710 14.7.2 Response preparation error detection function............................................................................. 713 14.7.3 ID parity check function ................................................................................................................ 714 14.7.4 Automatic checksum function....................................................................................................... 714 14.7.5 Multi-byte response transmission/reception function.................................................................... 716 14.8 Expansion Bit Mode ................................................................................................................. 720 14.8.1 Expansion bit mode transmission................................................................................................. 720 14.8.2 Expansion bit mode reception (no data comparison) ................................................................... 721 14.8.3 Expansion bit mode reception (with data comparison) ................................................................. 722 14.9 Receive Data Noise Filter ........................................................................................................ 723 14.10 Dedicated Baud Rate Generator ........................................................................................... 724 14.11 Cautions for Use..................................................................................................................... 731 CHAPTER 15 SERIAL INTERFACE IICA ........................................................................................... 732 15.1 Functions of Serial Interface IICA........................................................................................... 732 15.2 Configuration of Serial Interface IICA .................................................................................... 735 15.3 Registers Controlling Serial Interface IICA............................................................................ 738 15.4 I2C Bus Mode Functions .......................................................................................................... 752 15.4.1 Pin configuration........................................................................................................................... 752 15.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers...................................................... 753 2 15.5 I C Bus Definitions and Control Methods .............................................................................. 755 15.5.1 Start conditions............................................................................................................................. 755 15.5.2 Addresses .................................................................................................................................... 756 15.5.3 Transfer direction specification..................................................................................................... 756 15.5.4 Acknowledge (ACK) ..................................................................................................................... 757 15.5.5 Stop condition............................................................................................................................... 758 15.5.6 Wait .............................................................................................................................................. 759 15.5.7 Canceling wait .............................................................................................................................. 761 15.5.8 Interrupt request (INTIICA0) generation timing and wait control................................................... 762 15.5.9 Address match detection method ................................................................................................. 763 15.5.10 Error detection............................................................................................................................ 763 Index-8 15.5.11 Extension code........................................................................................................................... 763 15.5.12 Arbitration ................................................................................................................................... 764 15.5.13 Wakeup function......................................................................................................................... 766 15.5.14 Communication reservation........................................................................................................ 769 15.5.15 Cautions ..................................................................................................................................... 773 15.5.16 Communication operations......................................................................................................... 774 15.5.17 Timing of I2C interrupt request (INTIICA0) occurrence ............................................................... 782 15.6 Timing Charts ........................................................................................................................... 803 CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR ......................................... 818 16.1 Functions of Multiplier and Divider/Multiply-Accumulator .................................................. 818 16.2 Configuration of Multiplier and Divider/Multiply-Accumulator............................................ 818 16.3 Register Controlling Multiplier and Divider/Multiply-Accumulator ..................................... 824 16.4 Operations of Multiplier and Divider/Multiply-Accumulator ................................................ 826 16.4.1 Multiplication (unsigned) operation............................................................................................... 826 16.4.2 Multiplication (signed) operation................................................................................................... 827 16.4.3 Multiply-accumulation (unsigned) operation ................................................................................. 828 16.4.4 Multiply-accumulation (signed) operation ..................................................................................... 830 16.4.5 Division operation......................................................................................................................... 832 CHAPTER 17 DMA CONTROLLER ..................................................................................................... 834 17.1 Functions of DMA Controller .................................................................................................. 834 17.2 Configuration of DMA Controller ............................................................................................ 835 17.3 Registers Controlling DMA Controller ................................................................................... 838 17.4 Operation of DMA Controller................................................................................................... 842 17.4.1 Operation procedure .................................................................................................................... 842 17.4.2 Transfer mode .............................................................................................................................. 843 17.4.3 Termination of DMA transfer ........................................................................................................ 843 17.5 Example of Setting of DMA Controller ................................................................................... 844 17.5.1 CSI consecutive transmission ...................................................................................................... 844 17.5.2 Consecutive capturing of A/D conversion results ......................................................................... 846 17.5.3 UART consecutive reception + ACK transmission........................................................................ 848 17.5.4 Holding DMA transfer pending by DWAITn bit ............................................................................. 850 17.5.5 Forced termination by software .................................................................................................... 851 17.6 Cautions on Using DMA Controller ........................................................................................ 853 CHAPTER 18 INTERRUPT FUNCTIONS............................................................................................. 855 18.1 Interrupt Function Types ......................................................................................................... 855 18.2 Interrupt Sources and Configuration ..................................................................................... 855 18.3 Registers Controlling Interrupt Functions............................................................................. 861 Index-9 18.4 Interrupt Servicing Operations ............................................................................................... 874 18.4.1 Maskable interrupt request acknowledgment ............................................................................... 874 18.4.2 Software interrupt request acknowledgment ................................................................................ 877 18.4.3 Multiple interrupt servicing............................................................................................................ 877 18.4.4 Interrupt request hold ................................................................................................................... 881 CHAPTER 19 KEY INTERRUPT FUNCTION ..................................................................................... 882 19.1 Functions of Key Interrupt ...................................................................................................... 882 19.2 Configuration of Key Interrupt ................................................................................................ 882 19.3 Register Controlling Key Interrupt ......................................................................................... 884 CHAPTER 20 STANDBY FUNCTION .................................................................................................. 885 20.1 Standby Function and Configuration ..................................................................................... 885 20.1.1 Standby function........................................................................................................................... 885 20.1.2 Registers controlling standby function.......................................................................................... 886 20.2 Standby Function Operation ................................................................................................... 889 20.2.1 HALT mode .................................................................................................................................. 889 20.2.2 STOP mode.................................................................................................................................. 894 20.2.3 SNOOZE mode ............................................................................................................................ 899 CHAPTER 21 RESET FUNCTION........................................................................................................ 901 21.1 Register for Confirming Reset Source ................................................................................... 912 CHAPTER 22 POWER-ON-RESET CIRCUIT ...................................................................................... 914 22.1 Functions of Power-on-reset Circuit ...................................................................................... 914 22.2 Configuration of Power-on-reset Circuit................................................................................ 915 22.3 Operation of Power-on-reset Circuit ...................................................................................... 915 22.4 Cautions for Power-on-reset Circuit....................................................................................... 918 CHAPTER 23 VOLTAGE DETECTOR .................................................................................................. 920 23.1 Functions of Voltage Detector ................................................................................................ 920 23.2 Configuration of Voltage Detector.......................................................................................... 921 23.3 Registers Controlling Voltage Detector ................................................................................. 921 23.4 Operation of Voltage Detector ................................................................................................ 926 23.4.1 When used as reset mode............................................................................................................ 926 23.4.2 When used as interrupt mode ...................................................................................................... 928 23.4.3 When used as interrupt and reset mode ...................................................................................... 930 23.5 Cautions for Voltage Detector................................................................................................. 936 Index-10 CHAPTER 24 SAFETY FUNCTIONS .................................................................................................... 938 24.1 Overview of Safety Functions ................................................................................................. 938 24.2 Registers Used by Safety Functions ...................................................................................... 939 24.3 Operations of Safety Functions .............................................................................................. 940 24.3.1 Flash Memory CRC Operation Function (High-Speed CRC)........................................................ 940 24.3.2 CRC Operation Function (General-Purpose CRC)....................................................................... 943 24.3.3 RAM Parity Error Detection Function ........................................................................................... 946 24.3.4 RAM Guard Function.................................................................................................................... 947 24.3.5 SFR Guard Function .................................................................................................................... 947 24.3.6 Invalid Memory Access Detection Function.................................................................................. 949 24.3.7 Frequency Detection Function...................................................................................................... 952 24.3.8 A/D Test Function......................................................................................................................... 954 CHAPTER 25 REGULATOR ................................................................................................................. 958 25.1 Regulator Overview.................................................................................................................. 958 CHAPTER 26 OPTION BYTE............................................................................................................... 959 26.1 Functions of Option Bytes ...................................................................................................... 959 26.1.1 User option byte (000C0H to 000C2H/010C0H to 010C2H)......................................................... 959 26.1.2 On-chip debug option byte (000C3H/ 010C3H)............................................................................ 960 26.2 Format of User Option Byte .................................................................................................... 961 26.3 Format of On-chip Debug Option Byte................................................................................... 965 26.4 Setting of Option Byte.............................................................................................................. 966 CHAPTER 27 FLASH MEMORY .......................................................................................................... 967 27.1 Writing to Flash Memory by Using Flash Memory Programmer ......................................... 968 27.1.1 Programming Environment........................................................................................................... 970 27.1.2 Communication Mode .................................................................................................................. 970 27.2 Writing to Flash Memory by Using External Device (that Incorporates UART) ................. 971 27.2.1 Programming Environment........................................................................................................... 971 27.2.2 Communication Mode .................................................................................................................. 972 27.3 Connection of Pins on Board.................................................................................................. 973 27.3.1 P40/TOOL0 pin ............................................................................................................................ 973 27.3.2 RESET pin.................................................................................................................................... 973 27.3.3 Port pins ....................................................................................................................................... 974 27.3.4 REGC pin ..................................................................................................................................... 974 27.3.5 X1 and X2 pins ............................................................................................................................. 974 27.3.6 Power supply................................................................................................................................ 974 27.4 Data Flash ................................................................................................................................. 975 Index-11 27.4.1 Data flash overview ...................................................................................................................... 975 27.4.2 Register controlling data flash memory ........................................................................................ 976 27.4.3 Procedure for accessing data flash memory ................................................................................ 977 27.5 Programming Method .............................................................................................................. 978 27.5.1 Controlling flash memory.............................................................................................................. 978 27.5.2 Flash memory programming mode............................................................................................... 979 27.5.3 Selecting communication mode.................................................................................................... 980 27.5.4 Communication commands .......................................................................................................... 981 27.6 Security Settings ...................................................................................................................... 982 27.7 Flash Memory Programming by Self-Programming ............................................................. 984 27.7.1 Boot swap function ....................................................................................................................... 986 27.7.2 Flash shield window function........................................................................................................ 988 CHAPTER 28 ON-CHIP DEBUG FUNCTION ..................................................................................... 989 28.1 Connecting E1 On-chip Debugging Emulator to RL78/F12.................................................. 989 28.2 On-Chip Debug Security ID ..................................................................................................... 990 28.3 Securing of User Resources ................................................................................................... 990 CHAPTER 29 BCD CORRECTION CIRCUIT ..................................................................................... 992 29.1 BCD Correction Circuit Function............................................................................................ 992 29.2 Registers Used by BCD Correction Circuit ........................................................................... 992 29.3 BCD Correction Circuit Operation .......................................................................................... 993 CHAPTER 30 INSTRUCTION SET........................................................................................................ 995 30.1 Conventions Used in Operation List ...................................................................................... 996 30.1.1 Operand identifiers and specification methods............................................................................. 996 30.1.2 Description of operation column ................................................................................................... 997 30.1.3 Description of flag operation column ............................................................................................ 998 30.1.4 PREFIX instruction ....................................................................................................................... 998 30.2 Operation List ........................................................................................................................... 999 CHAPTER 31 ELECTRICAL SPECIFICATIONS (J GRADE)............................................................ 1016 31.1 Pins Mounted According to Product .................................................................................... 1016 31.1.1 Port functions ............................................................................................................................. 1016 31.1.2 Non-port functions ...................................................................................................................... 1016 31.2 Absolute Maximum Ratings .................................................................................................. 1017 31.3 Oscillator Characteristics...................................................................................................... 1019 31.3.1 Main system clock oscillator characteristics ............................................................................... 1019 31.3.2 On-chip oscillator characteristics................................................................................................ 1020 31.3.3 Subsystem clock oscillator characteristics.................................................................................. 1021 Index-12 31.4 DC Characteristics ................................................................................................................. 1022 31.4.1 Pin characteristics ...................................................................................................................... 1022 31.4.2 Supply current characteristics .................................................................................................... 1027 31.5 AC Characteristics ................................................................................................................. 1030 31.5.1 Basic operation........................................................................................................................... 1030 31.6 Peripheral Functions Characteristics................................................................................... 1031 31.6.1 Serial array unit .......................................................................................................................... 1031 31.6.2 Serial interface IICA ................................................................................................................... 1037 31.6.3 LIN-UART................................................................................................................................... 1038 31.7 Analog Characteristics .......................................................................................................... 1039 31.7.1 A/D converter characteristics...................................................................................................... 1039 31.7.2 Temperature sensor characteristics ........................................................................................... 1043 31.7.3 POR circuit characteristics ......................................................................................................... 1043 31.7.4 LVD circuit characteristics .......................................................................................................... 1044 31.7.5 Power supply rise time ............................................................................................................... 1046 31.8 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics............. 1047 31.9 Flash Memory Programming Characteristics...................................................................... 1047 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) ........................................................... 1048 32.1 Pins Mounted According to Product .................................................................................... 1048 32.1.1 Port functions ............................................................................................................................. 1048 32.1.2 Non-port functions ...................................................................................................................... 1048 32.2 Absolute Maximum Ratings .................................................................................................. 1049 32.3 Oscillator Characteristics...................................................................................................... 1051 32.3.1 Main system clock oscillator characteristics ............................................................................... 1051 32.3.2 On-chip oscillator characteristics................................................................................................ 1052 32.3.3 Subsystem clock oscillator characteristics.................................................................................. 1053 32.4 DC Characteristics ................................................................................................................. 1054 32.4.1 Pin characteristics ...................................................................................................................... 1054 32.4.2 Supply current characteristics .................................................................................................... 1059 32.5 AC Characteristics ................................................................................................................. 1062 32.5.1 Basic operation........................................................................................................................... 1062 32.6 Peripheral Functions Characteristics................................................................................... 1063 32.6.1 Serial array unit .......................................................................................................................... 1063 32.6.2 Serial interface IICA ................................................................................................................... 1069 32.6.3 LIN-UART................................................................................................................................... 1070 32.7 Analog Characteristics .......................................................................................................... 1071 32.7.1 A/D converter characteristics...................................................................................................... 1071 32.7.2 Temperature sensor characteristics ........................................................................................... 1075 32.7.3 POR circuit characteristics ......................................................................................................... 1075 32.7.4 LVD circuit characteristics .......................................................................................................... 1076 Index-13 32.7.5 Power supply rise time ............................................................................................................... 1077 32.8 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics............. 1078 32.9 Flash Memory Programming Characteristics...................................................................... 1078 CHAPTER 33 PACKAGE DRAWING.................................................................................................. 1079 33.1 20-pin products....................................................................................................................... 1079 33.2 30-pin products....................................................................................................................... 1080 33.3 32-pin products....................................................................................................................... 1081 33.4 48-pin products....................................................................................................................... 1082 33.5 64-pin products....................................................................................................................... 1084 APPENDIX A REVISION HISTORY .................................................................................................... 1085 A.1 Major Revisions in This Edition ............................................................................................. 1085 A.2 Revision History of Preceding Edition .................................................................................. 1087 Index-14 R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 RL78/F12 RENESAS MCU CHAPTER 1 OUTLINE 1.1 Features  Minimum instruction execution time can be changed from high speed (0.03125 μs: @ 32 MHz operation with highspeed on-chip oscillator) to ultra low-speed (30.5 μs: @ 32.768 kHz operation with subsystem clock)  General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)  ROM: 8 to 64 KB, RAM: 0.5 to 4 KB, Data flash memory: 4 KB  High-speed on-chip oscillator • Select from 32 MHz (TYP.), 24 MHz (TYP.), 16 MHz (TYP.), 12 MHz (TYP.), 8 MHz (TYP.), 4 MHz (TYP.), and 1 MHz (TYP.)  On-chip single-power-supply flash memory (with prohibition of block erase/writing function)  Self-programming (with boot swap function/flash shield window function)  On-chip debug function  On-chip power-on-reset (POR) circuit and voltage detector (LVD)  On-chip watchdog timer (operable with the dedicated internal low-speed on-chip oscillator)  On-chip multiplier and divider/multiply-accumulator • 16 bits × 16 bits = 32 bits (Unsigned or signed) • 32 bits ÷ 32 bits = 32 bits (Unsigned) • 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)  On-chip key interrupt function  On-chip clock output/buzzer output controller  On-chip BCD adjustment  I/O ports: 16 to 44 (N-ch open drain: 0 to 4)  Timer • 16-bit timer: 8 channels • Watchdog timer: 1 channel • Real-time clock: 1 channel • Interval timer: 1 channel • Wakeup timer: 1 channel  Serial interface • CSI: 0 to 8 channels • UART/UART (LIN-bus supported): 1 to 5 channels • I2C/Simplified I2C communication: 0 to 7 channels  8/10-bit resolution A/D converter (VDD = 1.8 to 5.5 V): 4 to 12 channels  Power supply voltage: VDD = 1.8 to 5.5 V (J version), VDD = 2.7 to 5.5 V (K version)  Operating ambient temperature: TA = −40 to +85°C (J version), TA = −40 to +125°C (K version) Remark The functions mounted depend on the product. See 1.6 Outline of Functions. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1 RL78/F12 CHAPTER 1 OUTLINE  ROM, RAM capacities Flash ROM 64 KB Data flash 4 KB RAM 4 KB Note RL78/F12 20 pins 30 pins 32 pins 48 pins 64 pins R5F1096E R5F109AE R5F109BE R5F109GE R5F109LE 48 KB 3 KB R5F1096D R5F109AD R5F109BD R5F109GD R5F109LD 32 KB 2 KB R5F1096C R5F109AC R5F109BC R5F109GC R5F109LC 24 KB 1.5 KB R5F1096B R5F109AB R5F109BB R5F109GB R5F109LB 16 KB 1 KB R5F1096A R5F109AA R5F109BA R5F109GA R5F109LA 8 KB 0.5 KB R5F10968 − − − − Note This is 3 KB when the self-programming function is used. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 2 RL78/F12 CHAPTER 1 OUTLINE 1.2 Ordering Information • Flash memory version (lead-free product) Pin count 20 pins Package Data flash 20-pin plastic SSOP Mounted (7.62 mm (300)) 30 pins 30-pin plastic SSOP Mounted 32-pin plastic WQFN Mounted R5F109BAJNA, R5F109BBJNA, R5F109BCJNA, 5F109BDJNA, R5F109BEJNA 48-pin plastic LQFP Mounted (fine pitch) (7 × 7) 48-pin plastic WQFN (7 × 7) R5F109AAJSP, R5F109ABJSP, R5F109ACJSP, R5F109ADJSP, R5F109AEJSP fine pitch)(5 × 5) 48 pins R5F10968JSP, R5F1096AJSP, R5F1096BJSP, R5F1096CJSP, R5F1096DJSP, R5F1096EJSP (7.62 mm (300)) 32 pins Part Number R5F109GAJFB, R5F109GBJFB, R5F109GCJFB, R5F109GDJFB, R5F109GEJFB Note Mounted R5F109GAJNA, R5F109GBJNA, R5F109GCJNA, R5F109GDJNA, Mounted R5F109LAJFB, R5F109LBJFB, R5F109LCJFB, R5F109LDJFB, R5F109GEJNA 64 pins 64-pin plastic LQFP (fine pitch) (10 × 10) Note R5F109LEJFB Contact Renesas local sales office or sales representative for further details on this package. Caution The RL78/F12 has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 3 RL78/F12 CHAPTER 1 OUTLINE 1.3 Pin Configuration (Top View) 1.3.1 20-pin products • 20-pin plastic SSOP (7.62 mm (300)) P20/ANI0/AVREFP P01/ANI16/TO00 P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 P21/ANI1/AVREFM P22/ANI2 P10/SCK00/SCKS0//SCL00/(TI07)/(TO07) P11/SI00/RxD0/SIS0/RxDS0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/SOS0/TxDS0/TOOLTxD/(TI05)/(TO05) P16/TI01/TO01/INTP5/(RXD0) P17/TI02/TO02/(TXD0) P51/INTP2/LTxD0 P50/INTP1/LRxD0 P31/TI03/TO03/INTP4/PCLBUZ0 Cautions 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). 2. For the following each port, complete the following software processings before performing the operation that reads the port latch Pm having the target port latch Pm.n within 50ms after releasing reset (after staring CPU operation) • Set P00, P13, P14, P15, P30, P60, P61, and P147 to low level output mode by the software (clear the PMm.n and Pm.n bits for the target ports). • Set P23 to digital port and low level output mode by the software (set P23 to digital mode with the ADPC register and clear the PM2.3 and P2.3 bits). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 4 RL78/F12 CHAPTER 1 OUTLINE 1.3.2 30-pin products • 30-pin plastic SSOP (7.62 mm (300)) P20/ANI0/AVREFP P01/ANI16/TO00/RxD1 P00/ANI17/TI00/TxD1 P120/ANI19 P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P60/SCLA0 P61/SDAA0 P31/TI03/TO03/INTP4/PCLBUZ0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P147/ANI18 P10/SCK00/SCKS0/SCL00/(TI07)/(TO07) P11/SI00/RxD0/SIS0/RxDS0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/SOS0/TxDS0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RXD0) P17/TI02/TO02/(TXD0) P51/INTP2/SO11/LTxD0 P50/INTP1/SI11/SDA11/LRxD0 P30/INTP3/SCK11/SCL11 Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 5 RL78/F12 CHAPTER 1 OUTLINE 1.3.3 32-pin products P120/ANI19 P00/ANI17/TI00/TxD1 P01/ANI16/TO00/RxD1 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P147/ANI18 • 32-pin plastic WQFN (fine pitch) (5 × 5) exposed die pad 32 31 30 29 28 27 26 25 P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 P10/SCK00/SCKS0/SCL00/(TI07)/(TO07) P11/SI00/RxD0/SIS0/RxDS0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/SOS0/TxDS0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RXD0) P17/TI02/TO02/(TXD0) P60/SCLA0 P61/SDAA0 P62 P31/TI03/TO03/INTP4/PCLBUZ0 P70 P30/INTP3/SCK11/SCL11 P50/INTP1/SI11/SDA11/LRxD0 P51/INTP2/SO11/LTxD0 9 10 11 12 13 14 15 16 Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 6 RL78/F12 CHAPTER 1 OUTLINE 1.3.4 48-pin products VDD VSS REGC P121/X1 P122/X2/EXCLK P137/INTP0 P123/XT1 P124/XT2/EXCLKS RESET P40/TOOL0 P41/TI07/TO07 P120/ANI19 • 48-pin plastic LQFP (fine pitch) (7 × 7) 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 P140/PCLBUZ0/INTP6 P00/TI00/TxD1 P01/TO00/RxD1 P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 P50/INTP1/SI11/SDA11/LRxD0 P51/INTP2/SO11/LTxD0 P17/TI02/TO02/(TXD0) P16/TI01/TO01/INTP5/(RXD0) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P12/SO00/TxD0/SOS0/TxDS0/TOOLTxD/(TI05)/(TO05) P11/SI00/RxD0/SIS0/RxDS0/TOOLRxD/SDA00/(TI06)/(TO06) P10/SCK00/SCKS0/SCL00/(TI07)/(TO07) P146 P147/ANI18 P60/SCLA0 P61/SDAA0 P62 P63 P31/TI03/TO03/INTP4/(PCLBUZ0) P75/KR5/INTP9/SCK01/SCL01 P74/KR4/INTP8/SI01/SDA01 P73/KR3/SO01 P72/KR2/SO21 P71/KR1/SI21/SDA21 P70/KR0/SCK21/SCL21 P30/INTP3/SCK11/SCL11/RTC1HZ Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 7 RL78/F12 CHAPTER 1 OUTLINE VDD VSS REGC P121/X1 P122/X2/EXCLK P137/INTP0 P123/XT1 P124/XT2/EXCLKS RESET P40/TOOL0 P41/TI07/TO07 P120/ANI19 • 48-pin plastic WQFN (7 × 7) 48 47 46 45 44 43 42 41 40 39 38 37 1 36 exposed die pad 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 P140/PCLBUZ0/INTP6 P00/TI00/TxD1 P01/TO00/RxD1 P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 P50/INTP1/SI11/SDA11/LRxD0 P51/INTP2/SO11/LTxD0 P17/TI02/TO02/(TXD0) P16/TI01/TO01/INTP5/(RXD0) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P12/SO00/TxD0/SOS0/TxDS0/TOOLTxD/(TI05)/(TO05) P11/SI00/RxD0/SIS0/RxDS0/TOOLRxD/SDA00/(TI06)/(TO06) P10/SCK00/SCKS0/SCL00/(TI07)/(TO07) P146 P147/ANI18 P60/SCLA0 P61/SDAA0 P62 P63 P31/TI03/TO03/INTP4/(PCLBUZ0) P75/KR5/INTP9/SCK01/SCL01 P74/KR4/INTP8/SI01/SDA01 P73/KR3/SO01 P72/KR2/SO21 P71/KR1/SI21/SDA21 P70/KR0/SCK21/SCL21 P30/INTP3/SCK11/SCL11/RTC1HZ Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). 3. Contact Renesas local sales office or sales representative for further details on this package. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 8 RL78/F12 CHAPTER 1 OUTLINE 1.3.5 64-pin products P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P130 P04/SCK10/SCL10 P03/ANI16/SI10/RXD1/SDA10 P02/ANI17/SO10/TXD1 P01/TO00 P00/TI00 P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 64-pin plastic LQFP P120/ANI19 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 P43 2 47 P146 P42/TI04/TO04 3 46 P10/SCK00/SCL00/SCKS0/(TI07)/(TO07) P41/TI07/TO07 4 45 P11/SI00/RXD0/SDA00/TOOLRXD/SIS0/RXDS0/(TI06)/(TO06) P40/TOOL0 5 44 P12/SO00/TXD0/TOOLTXD/SOS0/TXDS0/(INTP5)/(TI05)/(TO05) RESET 6 43 P13/TXD2/SO20/(SDAA0)/(TI04)/(TO04) P124/XT2/EXCLKS 7 42 P14/RXD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P123/XT1 8 41 P15/SCK20/SCL20/(TI02)/(TO02) P137/INTP0 9 40 P16/TI01/TO01/INTP5/(RXD0)/(SI00) P122/X2/EXCLK 10 39 P17/TI02/TO02/(TXD0)/(SO00 P121/X1 11 38 P55/SCKS1/(PCLBUZ1)/(SCK00) REGC 12 37 P54/SIS1 VSS 13 36 P53/SOS1/(INTP11) EVSS0 14 35 P52/(INTP10) VDD 15 34 P51/INTP2/SO11/LTXD P147/ANI18 P50/INTP1/SI11/SDA11/LRXD P30/INTP3/RTC1HZ/SCK11/SCL11 P05/TI05/TO05 P06/TI06/TO06 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3/SO01 P74/KR4/INTP8/SI01/SDA01 P75/KR5/INTP9/SCK01/SCL01 P76/KR6/INTP10/(RXD2) P77/KR7/INTP11/(TXD2) P31/TI03/TO03/NTP4/(PCLBUZ0) P63 P62 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P60/SCLA0 EVDD0 P61/SDAA0 • Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 9 RL78/F12 CHAPTER 1 OUTLINE 1.4 Pin Identification ANI0 to ANI7, PCLBUZ0, PCLBUZ1: Programmable clock output/buzzer Regulator capacitance output ANI16 to ANI19: Analog input AVREFM: A/D converter reference REGC: potential (− side) input RESET: Reset A/D converter reference RTC1HZ: Real-time clock correction clock AVREFP: (1 Hz) output potential (+ side) input EXCLK: EXCLKS: External clock input (main RxD0 to RxD2, RxDS0: system clock) SCK00, SCK01, SCK10, External clock input (sub SCK11, SCK20, SCK21, system clock) SCKS0, SCKS1: Receive data Serial clock input/output INTP0 to INTP11: External interrupt input SCL00, SCL01, SCL10, KR0 to KR7: Key return SCL11, SCL20, SCL21, LRxD0: Receive Data SCLA0: LTxD0: Transmit Data SDA00, SDA01, SDA10, P00, P06: Port 0 SDA11,SDA20, SDA21, P10 to P17: Port 1 SDAA0: P20 to P27: Port 2 SI00, SI01, SI10, SI11, P30, P31: Port 3 SI20, SI21, SIS0, SIS1: P40 to P43: Port 4 SO00, SO01, SO10, P50 to P55: Port 5 SO11, SO20, SO21, P60 to P63: Port 6 SOS0, SOS1: Serial data output P70 to P77: Port 7 TI00 to TI07: Timer input P120 to P124: Port 12 TO00 to TO07: Timer output P130, P137: Port 13 TOOL0: Data input/output for tool TOOLRxD, TOOLTxD: Data input/output for external device P140, P141, P146, P147: Port 14 R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 Serial clock input/output Serial data input/output Serial data input TxD0 to TxD2, TxDS0: Transmit data VDD: Power supply VSS: Ground X1, X2: Crystal oscillator (main system clock) XT1, XT2: Crystal oscillator (subsystem clock) 10 RL78/F12 CHAPTER 1 OUTLINE 1.5 Block Diagram 1.5.1 20-pin products TIMER ARRAY UNIT (8ch) TO00/P01 ch0 TI01/TO01/P16 ch1 TI02/TO02/P17 ch2 TI03/TO03/P13 ch3 PORT 0 P01 PORT 1 5 P10 to P12, P16, P17 PORT 2 3 P20 to P22 PORT 3 P31 PORT 4 P40 ch4 PORT 5 2 P50, P51 ch6 PORT 12 2 P121, P122 ch7 PORT 13 (TI05/TO05/P12) ch5 (TI06/TO06/P11) (TI07/TO07/P10) INTERVAL TIMER RL78 CPU CORE P137 CODE FLASH MEMORY 3 DATA FLASH MEMORY ANI0/P20 to ANI2/P22 ANI16/P01 A/D CONVERTER AVREFP/P20 AVREFM/P21 WINDOW WATCHDOG TIMER POWER ON RESET/ VOLTAGE DETECTOR LOW-SPEED ON-CHIP OSCILLATOR POR/LVD CONTROL RAM RESET CONTROL REAL-TIME CLOCK TOOL0/P40 ON-CHIP DEBUG 16-BIT WAKEUP TIMER RxD0/P11 (RxD0/P16) TxD0/P12 (TxD0/P17) VDD SERIAL ARRAY UNIT 0 (4 ch) UART0 CSI00 SCL00/P10 SDA00/P11 IIC00 SYSTEM CONTROL RESET X1/P121 HIGH-SPEED LIN-UART0 SCK00/P10 SI00/P11 SO00/P12 VSS TOOLRxD/P11, TOOLTxD/P12 MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR DIRECT MEMORY ACCESS CONTROL LRxD0//P50 LTxD0/P51 ON-CHIP X2/EXCLK/P122 OSCILLATOR VOLTAGE REGULATOR REGC CRC INTP0/P137 INTERRUPT CONTROL 2 INTP1/P50, INTP2/P51 INTP4/P31 INTP5/P16 SERIAL ARRAY UNIT S (2 ch) RxDS0/P11 TxDS0/P12 UARTS0 SCKS0/P10 SIS0/P11 SOS0/P12 CSIS0 Remark BCD ADJUSTMENT Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 11 RL78/F12 CHAPTER 1 OUTLINE 1.5.2 30-pin products TIMER ARRAY UNIT (8ch) TI00/P00 TO00/P01 ch0 TI01/TO01/P16 ch1 TI02/TO02/P17 (TI02/TO02/P15) ch2 TI03/TO03/P31 (TI03/TO03/P14) ch3 (TI04/TO04/P13) ch4 (TI05/TO05/P12) ch5 (TI06/TO06/P11) ch6 (TI07/TO07/P10) RxD2/P14 ch7 PORT 0 2 P00, P01 PORT 1 8 P10 to P17 PORT 2 4 P20 to P23 PORT 3 2 P30, P31 PORT 4 P40 PORT 5 2 P50, P51 PORT 6 2 P60, P61 2 P121, P122 PORT 12 P120 PORT 13 P137 PORT 14 P147 INTERVAL TIMER WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR REAL-TIME CLOCK RL78 CPU CORE 4 ANI0/P20 to ANI3/P23 4 ANI16/P01, ANI17/P00, ANI18/P147, ANI19/P120 CODE FLASH MEMORY A/D CONVERTER AVREFP/P20 AVREFM/P21 DATA FLASH MEMORY 16-BIT WAKEUP TIMER RxD0/P11 (RxD0/P16) TxD0/P12 (TxD0/P17) SERIAL ARRAY UNIT 0 (4 ch) POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RAM UART0 RESET CONTROL RxD1/P01 TxD1/P00 UART1 SCK00/P10 SI00/P11 SO00/P12 CSI00 SCK11/P30 SI11/P50 SO11/P51 CSI11 SCL00/P10 SDA00/P11 IIC00 SCL11/P30 SDA11/P50 IIC11 VDD SERIAL INTERFACE IICA LIN-UART0 VSS TOOLRxD/P11, TOOLTxD/P12 SDAA0/P61 (SDAA0/P14) SCLA0/P60 (SCLA0/P13) LRxD0//P50 TOOL0/P40 ON-CHIP DEBUG SYSTEM CONTROL RESET X1/P121 HIGH-SPEED ON-CHIP OSCILLATOR X2/EXCLK/P122 LTxD0/P51 VOLTAGE REGULATOR BUZZER OUTPUT REGC PCLBUZ1/P15 SERIAL ARRAY UNIT 1 (2 ch) RxD2/P14 TxD2/P13 UART2 LINSEL RxD2/P14 (LINSEL) INTP0/P137 CLOCK OUTPUT CONTROL MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR SCK20/P15 SI20/P14 SO20/P13 CSI20 DIRECT MEMORY ACCESS CONTROL SCL20/P15 SDA20/P14 IIC20 BCD ADJUSTMENT CRC INTERRUPT CONTROL 2 INTP1/P50, INTP2/P51 2 INTP3/P30, INTP4/P31 INTP5/P16 SERIAL ARRAY UNIT S (2 ch) RxDS0/P11 TxDS0/P12 UARTS0 SCKS0/P10 SIS0/P11 SOS0/P12 CSIS0 Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 12 RL78/F12 CHAPTER 1 OUTLINE 1.5.3 32-pin products TIMER ARRAY UNIT (8ch) TI00/P00 TO00/P01 ch0 TI01/TO01/P16 ch1 TI02/TO02/P17 (TI02/TO02/P15) ch2 TI03/TO03/P31 (TI03/TO03/P14) ch3 (TI04/TO04/P13) ch4 (TI05/TO05/P12) ch5 (TI06/TO06/P11) ch6 (TI07/TO07/P10) RxD2/P14 ch7 PORT 0 2 P00, P01 PORT 1 8 P10 to P17 PORT 2 4 P20 to P23 PORT 3 2 P30, P31 PORT 4 PORT 5 2 P50, P51 PORT 6 3 P60 to P62 PORT 7 PORT 12 INTERVAL TIMER WINDOW WATCHDOG TIMER RL78 CPU CORE P70 P120 P121, P122 2 PORT 13 P137 PORT 14 P147 LOW-SPEED ON-CHIP OSCILLATOR REAL-TIME CLOCK P40 4 ANI0/P20 to ANI3/P23 4 ANI16/P01, ANI17/P00, ANI18/P147, ANI19/P120 CODE FLASH MEMORY A/D CONVERTER AVREFP/P20 AVREFM/P21 DATA FLASH MEMORY 16-BIT WAKEUP TIMER RxD0/P11 (RxD0/P16) TxD0/P12 (TxD0/P17) POWER ON RESET/ VOLTAGE DETECTOR SERIAL ARRAY UNIT 0 (4 ch) UART0 POR/LVD CONTROL RAM RESET CONTROL RxD1/P01 TxD1/P00 UART1 SCK00/P10 SI00/P11 SO00/P12 CSI00 SCK11/P30 SI11/P50 SO11/P51 CSI11 SCL00/P10 SDA00/P11 IIC00 SCL11/P30 SDA11/P50 IIC11 VDD SERIAL INTERFACE IICA LIN-UART0 VSS TOOLRxD/P11, TOOLTxD/P12 SDAA0/P61 (SDAA0/P14) SCLA0/P60 (SCLA0/P13) LRxD0//P50 TOOL0/P40 ON-CHIP DEBUG SYSTEM CONTROL RESET X1/P121 HIGH-SPEED ON-CHIP OSCILLATOR X2/EXCLK/P122 LTxD0/P51 VOLTAGE REGULATOR BUZZER OUTPUT REGC PCLBUZ1/P15 SERIAL ARRAY UNIT 1 (2 ch) RxD2/P14 TxD2/P13 UART2 LINSEL RxD2/P14 (LINSEL) INTP0/P137 CLOCK OUTPUT CONTROL MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR SCK20/P15 SI20/P14 SO20/P13 CSI20 DIRECT MEMORY ACCESS CONTROL SCL20/P15 SDA20/P14 IIC20 BCD ADJUSTMENT CRC INTERRUPT CONTROL 2 INTP1/P50, INTP2/P51 2 INTP3/P30, INTP4/P31 INTP5/P16 SERIAL ARRAY UNIT S (2 ch) RxDS0/P11 TxDS0/P12 UARTS0 SCKS0/P10 SIS0/P11 SOS0/P12 CSIS0 Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 13 RL78/F12 CHAPTER 1 OUTLINE 1.5.4 48-pin products TIMER ARRAY UNIT (8ch) TI00/P00 TO00/P01 ch0 PORT 0 2 P00, P01 PORT 1 8 P10 to P17 PORT 2 8 P20 to P27 PORT 3 2 P30, P31 PORT 4 2 P40, P41 PORT 5 2 P50, P51 TI01/TO01/P16 ch1 TI02/TO02/P17 (TI02/TO02/P15) ch2 TI03/TO03/P31 (TI03/TO03/P14) ch3 (TI04/TO04/P13) ch4 (TI05/TO05/P12) ch5 (TI06/TO06/P11) ch6 PORT 6 4 P60 to P63 TI07/TO07/P41 (TI07/TO07/P10) RxD2/P14 ch7 PORT 7 6 P70 to P75 4 P121 to P124 PORT 12 INTERVAL TIMER PORT 14 RTC1HZ/P30 SERIAL ARRAY UNIT 0 (4 ch) DATA FLASH MEMORY 8 ANI0/P20 to ANI7/P27 A/D CONVERTER 2 ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 KEY RETURN RAM POWER ON RESET/ VOLTAGE DETECTOR UART0 KR0/P70 to KR5/P75 6 POR/LVD CONTROL UART1 VDD CSI00 SCK01/P75 SI01/P74 SO01/P73 CSI01 VSS TOOLRxD/P11, TOOLTxD/P12 RESET CONTROL TOOL0/P40 ON-CHIP DEBUG SYSTEM CONTROL SCK11/P30 SI11/P50 SO11/P51 CSI11 SCL00/P10 SDA00/P11 IIC00 SCL01/P75 SDA01/P74 IIC01 SCL11/P30 SDA11/P50 IIC11 RESET X1/P121 X2/EXCLK/P122 CRC HIGH-SPEED XT1/P123 ON-CHIP OSCILLATOR SDAA0/P61 (SDAA0/P14) SCLA0/P60 (SCLA0/P13) SERIAL INTERFACE IICA REGC RxD2/P14 (LINSEL) INTP0/P137 2 INTP1/P50, INTP2/P51 2 INTP3/P30, INTP4/P31 LTxD0/P51 SERIAL ARRAY UNIT 1 (2 ch) UART2 XT2/EXCLKS/P124 VOLTAGE REGULATOR LRxD0//P50 LIN-UART0 INTERRUPT CONTROL INTP5/P16 BUZZER OUTPUT 2 LINSEL SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 P140, P146, P147 REAL-TIME CLOCK SCK00/P10 SI00/P11 SO00/P12 RxD2/P14 TxD2/P13 3 CODE FLASH MEMORY RL78 CPU CORE 16-BIT WAKEUP TIMER RxD0/P11 (RxD0/P16) TxD0/P12 (TxD0/P17 RxD1/P01 TxD1/P00 P130 P137 PORT 13 WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR P120 CLOCK OUTPUT CONTROL PCLBUZ0/P140 (PCLBUZ0/P31), PCLBUZ1/P15 INTP6/P140 2 INTP8/P74, INTP9/P75 CSI20 CSI21 MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR SCL20/P15 SDA20/P14 IIC20 DIRECT MEMORY ACCESS CONTROL SCL21/P70 SDA21/P71 IIC21 BCD ADJUSTMENT SERIAL ARRAY UNIT S (2 ch) Remark RxDS0/P11 TxDS0/P12 UARTS0 SCKS0/P10 SIS0/P11 SOS0/P12 CSIS0 Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 14 RL78/F12 CHAPTER 1 OUTLINE 1.5.5 64-pin products TIMER ARRAY UNIT (8ch) TI00/P00 TO00/P01 ch0 TI01/TO01/P16 ch1 TI02/TO02/P17 (TI02/TO02/P15 ch2 TI03/TO03/P31 (TI03/TO03/P14) PORT 0 7 P00 to P06 PORT 1 8 P10 to P17 PORT 2 8 P20 to P27 ch3 PORT 3 2 P30, P31 TI04/TO04/P42 (TI04/TO04/P13) ch4 PORT 4 4 P40 to P43 TI05/TO05/P05 (TI05/TO05/P12) ch5 PORT 5 6 P50 to P55 PORT 6 4 P60 to P63 PORT 7 8 P70 to P77 4 P121 to P124 TI06/TO06/P06 ch6 (TI06/TO06/P11) TI07/TO07/P41 (TI07/TO07/P10) RxD2/P14 (RxD2/P76) ch6 ch7 INTERVAL TIMER PORT 12 WINDOW WATCHDOG TIMER P120 P130 P137 PORT 13 PORT 14 4 P140, P141, P146, P147 8 ANI0/P20 to ANI7/P27 4 ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120 LOW-SPEED ON-CHIP OSCILLATOR REAL-TIME CLOCK RTC1HZ/P30 16-BIT WAKEUP TIMER RxD0/P11 (RxD0/P16) TxD0/P12 (TxD0/P17) RxD1/P03 TxD1/P02 SCK00/P10 (SCK00/P55) SI00/P11 (SI00/P16) SO00/P12 (SO00/P17) AV REFP/P20 AV REFM/P21 CODE FLASH MEMORY RL78 CPU CORE DATA FLASH MEMORY SERIAL ARRAY UNIT0 (4ch) KEY RETURN KR0/P70 to KR7/P77 8 UART0 POWER ON RESET/ VOLTAGE DETECTOR UART1 CSI00 SCK01/P75 SI01/P74 SO01/P73 CSI01 SCK10/P04 SI10/P03 SO10/P02 CSI10 SCK11/P30 SI11/P50 SO11/P51 CSI11 POR/LVD CONTROL RAM RESET CONTROL TOOL0/P40 ON-CHIP DEBUG VDD, VSS, TOOLRxD/P11, EVDD0 EVSS0 TOOLTxD/P12 SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED XT1/P123 ON-CHIP SCL00/P10 SDA00/P11 SDAA0/P61 SCLA0/P60 SERIAL INTERFACE IICA IIC01 SCL10/P04 SDA10/P03 IIC10 SCL11/P30 SDA11/P50 IIC11 OSCILLATOR XT2/EXCLKS/P124 VOLTAGE REGULATOR IIC00 SCL01/P75 SDA01/P74 RxD2/P14 (RxD2/P76) TxD2/P13 (TxD2/P77) A/D CONVERTER REGC LRxD/P50 LIN-UART RxD2/P14 (RXD2/P76) INTP0/P137 LTxD/P51 2 BUZZER OUTPUT 2 CLOCK OUTPUT CONTROL SERIAL ARRAY UNIT1 (2ch) SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 LINSEL CSI20 DIRECT MEMORY ACCESS CONTROL CSI21 BCD ADJUSTMENT SCL20/P15 SDA20/P14 IIC20 SCL21/P70 SDA21/P71 IIC21 INTERRUPT CONTROL 2 INTP5/P16(INTP5/P12) 2 MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR UART2 PCLBUZ0/P140 (PCLBUZ0/P31), PCLBUZ1/P141 (PCLBUZ1/P55) CRC INTP1/P50, INTP2/P51 INTP3/P30, INTP4/P31 2 2 INTP6/P140, INTP7/P141 INTP8/P74, INTP9/P75 INTP10/P76(INTP10/P52) INTP11/P77(INTP11/P53) SERIAL ARRAY UNIT S (2 ch) Remark RxDS0/P11 TxDS0/P12 UARTS0 SCKS0/P10 SIS0/P11 SOS0/P12 CSIS0 SCKS1/P55 SIS1/P54 SOS1/P53 CSIS1 Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 15 RL78/F12 CHAPTER 1 OUTLINE 1.6 Outline of Functions Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set to 00H. (1/2) Item 20-pin 30-pin 32-pin 48-pin 64-pin R5F1096x R5F109Ax R5F109Bx R5F109Gx R5F109Lx Code flash memory (KB) 8 to 64 16 to 64 16 to 64 16 to 64 16 to 64 Data flash memory (KB) 4 4 4 4 4 Note1 Note1 RAM (KB) 0.5 to 4 Memory space Main system clock Note1 1 to 4 Note1 1 to 4 Note1 1 to 4 1 to 4 1 MB High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) 1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V High-speed on-chip oscillator clock LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V) HS (High-speed main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V), − Subsystem clock Low-speed on-chip oscillator clock XT1 (crystal) oscillation 32.768 kHz (TYP.): VDD = 1.8 to 5.5 V 15 kHz (TYP.): VDD = 1.8 to 5.5 V General-purpose register 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution time 0.03125 μs (high-speed on-chip oscillator clock: fIH = 32 MHz operation) 0.05 μs (High-speed system clock: fMX = 20 MHz operation) 30.5 μs (Subsystem clock: fSUB = 32.768 kHz operation) Instruction set I/O port Timer • • • • Note3 Data transfer (8/16 bits) Adder and subtractor/logical operation (8/16 bits) Multiplication (8 bits × 8 bits) Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. Total 16 26 28 44 58 CMOS I/O 13 21 22 34 48 CMOS input 3 3 3 5 5 CMOS output − − − 1 1 N-ch open-drain I/O (6 V tolerance) − 2 3 4 4 5 channels 8 channels 16-bit timer 8 channels Watchdog timer 1 channel Real-time clock (RTC) 1 channel Interval timer 1 channel Wakeup timer Timer output 1 channel Note2 4 channels (PWM outputs: 3 ) (PWM outputs: 4Note2) (PWM outputs: 4Note2) − RTC output Clock output/buzzer output 1 2 1 1 Hz (subsystem clock: fSUB = 32.768 kHz) 2 2 2 • 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Peripheral hardware clock: fMAIN = 20 MHz operation) • 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz Note3 (Subsystem clock: fSUB = 32.768 kHz operation) Notes 1. 2. 3. In the case of the 4 KB, this is 3 KB when the self-programming function is used. The number of outputs varies, depending on the setting. Available only in 48- and 64-pin products. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 16 RL78/F12 CHAPTER 1 OUTLINE (2/2) Item 8/10-bit resolution A/D converter 20-pin 30-pin 32-pin 48-pin R5F1096x R5F109Ax R5F109Bx R5F109Gx 4 channels (VDD: 3 channels) 8 channels (VDD: 4 channels) 8 channels (VDD: 4 channels) 10 channels (VDD: 8 channels) 64-pin Note3 R5F109Lx 12 channels (VDD: 8 channels) (EVDD: 1 channels) (EVDD: 4 channels) (EVDD: 4 channels) (EVDD: 2 channels) (EVDD: 4 channels) Serial interface [20-pin, 24-pin, 25-pin products] 2 • CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel • CSI: 1 channel/UART: 1 channel • LIN-UART: 1 channel [30-pin, 32-pin products] • • • • 2 CSI: 2 channels/UART: 2 channels/simplified I C: 2 channels 2 CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I C: 1 channel CSI (7 to 16 bits): 1 channel/UART (7 to 9, 16 bits): 1 channel LIN-UART: 1 channel [48-pin products] • • • • 2 CSI: 3 channels/UART: 2 channels/simplified I C: 3 channels 2 CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I C: 2 channels CSI (7 to 16 bits): 1 channel/UART (7 to 9, 16 bits): 1 channel LIN-UART: 1 channel [64-pin products] • • • • 2 I C bus 2 CSI: 4 channels/UART: 2 channels/simplified I C: 4 channels 2 CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I C: 2 channels CSI (7 to 16 bits): 2 channels/UART (7 to 9, 16 bits): 1 channel LIN-UART: 1 channel − 1 channel 1 channel 1 channel Multiplier and divider/multiplyaccumulator • 16 bits × 16 bits = 32 bits (Unsigned or signed) • 32 bits ÷ 32 bits = 32 bits (Unsigned) • 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed) DMA controller 2 channels Vectored interrupt Internal sources External 28 34 34 34 Note1 34 Note1 5 6 6 10 Note1 12 Note1 Key interrupt − Reset • • • • • • • Power-on-reset circuit • Power-on-reset: 1.51 ±0.03 V • Power-down-reset: 1.50 ±0.03 V Voltage detector • Rising edge : 1.88 V to 4.06 V (12 stages) • Falling edge : 1.84 V to 3.98 V (12 stages) 6 Reset by RESET pin Internal reset by watchdog timer Internal reset by power-on-reset Internal reset by voltage detector Note2 Internal reset by illegal instruction execution Internal reset by RAM parity error Internal reset by illegal-memory access On-chip debug function Provided Power supply voltage VDD = 1.6 to 5.5 V Operating ambient temperature TA = −40 to +85 °C Notes 1. 2. 3. 8 INTP8, INTLR, INTP9, and INTLS are counted as one interrupt source in both an internal and external interrupt, respectively. The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. Available only in 48- and 64-pin products. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 17 RL78/F12 CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List 2.1.1 20-pin products Function Name P01 I/O I/O Function Port 0. 1-bit I/O port. After Reset Alternate Function Analog input port ANI16/TO00 Input port SCK00/SCKS0/ SCL00/(TI07)/(TO07) Input of P01 can be set to TTL input buffer. P01 can be set to analog input. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P10 I/O P11 P12 Port 1. 5-bit I/O port. Input of P16 and P17 can be set to TTL input buffer. Output of P10 to P12, and P17 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. SI00/RxD0/ SIS0/RxDS0/ TOOLRxD/SDA00/ (TI06)/(TO06) SO00/TxD0/SOS0/ TxDS0/TOOLTxD/ (TI05)/(TO05) P16 TI01/TO01/INTP5/ (RXD0) P17 TI02/TO02/(TXD0) P20 I/O P21 P22 Port 2. 3-bit I/O port. Input/output can be specified in 1-bit units. Analog input port ANI0/AVREFP ANI1/AVREFM ANI2 P31 I/O Port 3. 1-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port TI03/TO03/INTP4 PCLBUZ0 P40 I/O Port 4. 1-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port TOOL0 P50 I/O Port 5. 2-bit I/O port. Output of P50 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port INTP1/LRxD0 Input Port 12. 2-bit input port. Input port Input Port 13. 1-bit input port. Input port P51 P121 P122 P137 Remark INTP2/LTxD0 X1 X2/EXCLK INTP0 Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 18 RL78/F12 CHAPTER 2 PIN FUNCTIONS 2.1.2 30-pin products (1/2) Function Name P00 I/O I/O P01 Function Port 0. 2-bit I/O port. After Reset Alternate Function Analog input port ANI17/TI00/TxD1 Input port SCK00/SCKS0/ SCL00/(TI07)/(TO07) ANI16/TO00/RxD1 Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (VDD tolerance). P00 and P01 can be set to analog input. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P10 I/O P11 P12 Port 1. 8-bit I/O port. Input of P13 to P17 can be set to TTL input buffer. Output of P10 to P15, and P17 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. SI00/RxD0/ SIS0/RxDS0/ TOOLRxD/SDA00/ (TI06)/(TO06) SO00/TxD0/SOS0/ TxDS0/TOOLTxD/ (TI05)/(TO05) P13 TxD2/SO20/(SDAA0)/ (TI04)/(TO04) P14 RxD2/SI20/SDA20/ (SCLA0)/(TI03)/ (TO03) P15 PCLBUZ1/SCK20/ SCL20/(TI02)/(TO02) P16 TI01/TO01/INTP5/ (RXD0) TI02/TO02/(TXD0) P17 P20 I/O P21 P22 Port 2. 4-bit I/O port. Input/output can be specified in 1-bit units. Analog input port ANI1/AVREFM ANI2 P23 P30 ANI0/AVREFP ANI3 I/O P31 Port 3. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port INTP3/ SCK11/SCL11 TI03/TO03/INTP4 P40 I/O Port 4. 1-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port TOOL0 P50 I/O Port 5. 2-bit I/O port. Output of P50 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port INTP1/SI11/SDA11/ LRxD0 P51 INTP2/SO11/LTxD0 Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 19 RL78/F12 CHAPTER 2 PIN FUNCTIONS (2/2) Function Name P60 I/O I/O P61 P120 P121 I/O Input P122 Function After Reset Port 6. 2-bit I/O port. Output of P60 and P61 can be set to N-ch open-drain output (6 V tolerance). Input/output can be specified in 1-bit units. Input port Port 12. Analog input 1-bit I/O port and 2-bit input port. port P120 can be set to analog input. Input port For only P120, input/output can be specified in 1-bit units. Alternate Function SCLA0 SDAA0 ANI19 X1 X2/EXCLK For only P120, use of an on-chip pull-up resistor can be specified by a software setting. P137 Input Port 13. Input port INTP0 Port 14. Analog input ANI18 1-bit I/O port. port 1-bit input port. P147 I/O P147 can be set to analog input. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 20 RL78/F12 CHAPTER 2 PIN FUNCTIONS 2.1.3 32-pin products (1/2) Function Name P00 I/O I/O P01 Function Port 0. 2-bit I/O port. After Reset Alternate Function Analog input port ANI17/TI00/TxD1 Input port SCK00/SCKS0/ SCL00/(TI07)/(TO07) ANI16/TO00/RxD1 Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (VDD tolerance) P00 and P01 can be set to analog input. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P10 I/O P11 P12 Port 1. 8-bit I/O port. Input of P13 to P17 can be set to TTL input buffer. Output of P10 to P15, and P17 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. SI00/RxD0/ SIS0/RxDS0/ TOOLRxD/SDA00/ (TI06)/(TO06) SO00/TxD0/SOS0/ TxDS0/TOOLTxD/ (TI05)/(TO05) P13 TxD2/SO20/(SDAA0)/ (TI04)/(TO04) P14 RxD2/SI20/SDA20/ (SCLA0)/(TI03)/ (TO03) P15 PCLBUZ1/SCK20/ SCL20/(TI02)/(TO02) P16 TI01/TO01/INTP5/ (RXD0) TI02/TO02/(TXD0) P17 P20 I/O P21 P22 Port 2. 4-bit I/O port. Input/output can be specified in 1-bit units. Analog input port ANI1/AVREFM ANI2 P23 P30 ANI0/AVREFP ANI3 I/O P31 Port 3. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port INTP3/SCK11/ SCL11 TI03/TO03/INTP4 P40 I/O Port 4. 1-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port TOOL0 P50 I/O Port 5. 2-bit I/O port. Output of P50 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port INTP1/SI11/SDA11/ LRxD0 P51 Remark INTP2/SO11/LTxD0 Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 21 RL78/F12 CHAPTER 2 PIN FUNCTIONS (2/2) Function Name P60 I/O I/O P61 P62 P70 I/O Function After Reset Port 6. 3-bit I/O port. Output of P60 to P62 can be set to N-ch open-drain output (6 V tolerance). Input/output can be specified in 1-bit units. Input port Port 7. Input port Alternate Function SCLA0 SDAA0 − − 1-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P120 P121 I/O Input P122 Port 12. Analog input 1-bit I/O port and 2-bit input port. port P120 can be set to analog input. Input port For only P120, input/output can be specified in 1-bit units. ANI19 X1 X2/EXCLK For only P120, use of an on-chip pull-up resistor can be specified by a software setting. P137 Input Port 13. Input port INTP0 Port 14. Analog input ANI18 1-bit I/O port. port 1-bit input port. P147 I/O P147 can be set to analog input. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 22 RL78/F12 CHAPTER 2 PIN FUNCTIONS 2.1.4 48-pin products (1/2) Function Name P00 I/O I/O P01 Function Port 0. 2-bit I/O port. After Reset Input port Alternate Function TI00/TxD1 TO00/RxD1 Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (VDD tolerance) Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P10 I/O P11 P12 Port 1. 8-bit I/O port. Input of P13 to P17 can be set to TTL input buffer. Output of P10 to P15, and P17 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port SCK00/SCKS0/ SCL00/(TI07)/(TO07) SI00/RxD0/ SIS0/RxDS0/ TOOLRxD/SDA00/ (TI06)/(TO06) SO00/TxD0/SOS0/ TxDS0/TOOLTxD/ (TI05)/(TO05) P13 TxD2/SO20/(SDAA0)/ (TI04)/(TO04) P14 RxD2/SI20/SDA20/ (SCLA0)/(TI03)/ (TO03) P15 PCLBUZ1/SCK20/ SCL20/(TI02)/ (TO02) P16 TI01/TO01/INTP5/ (RXD0) TI02/TO02/(TXD0) P17 P20 I/O P21 P22 Port 2. 8-bit I/O port. Input/output can be specified in 1-bit units. Analog input port ANI0/AVREFP ANI1/AVREFM ANI2 P23 ANI3 P24 ANI4 P25 ANI5 P26 ANI6 P27 P30 ANI7 I/O P31 P40 P41 Remark I/O Port 3. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port Port 4. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port INTP3/RTC1HZ/ SCK11/SCL11 TI03/TO03/INTP4/ (PCLBUZ0) TOOL0 TI07/TO07 − Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 23 RL78/F12 CHAPTER 2 PIN FUNCTIONS (2/2) Function Name P50 I/O I/O P51 P60 I/O P61 P62 P63 P70 I/O Function After Reset Port 5. 2-bit I/O port. Output of P50 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port Port 6. 4-bit I/O port. Output of P60 to P63 can be set to N-ch open-drain output (6 V tolerance). Input/output can be specified in 1-bit units. Input port Port 7. Input port SCLA0 SDAA0 − − KR0/SCK21/SCL21 KR1/SI21/SDA21 Output of P71 and P74 can be set to N-ch open-drain output P72 INTP1/SI11/SDA11/ LRxD0 INTP2/SO11/LTxD0 6-bit I/O port. P71 Alternate Function KR2/SO21 (VDD tolerance). P73 Input/output can be specified in 1-bit units. KR3/SO01 P74 Use of an on-chip pull-up resistor can be specified by a KR4/INTP8/SI01/ software setting. SDA01 KR5/INTP9/SCK01/ P75 SCL01 P120 P121 I/O Input P122 Port 12. Analog input 1-bit I/O port and 4-bit input port. port P120 can be set to analog input. Input port For only P120, input/output can be specified in 1-bit units. X1 X2/EXCLK For only P120, use of an on-chip pull-up resistor can be P123 ANI19 XT1 specified by a software setting. P124 XT2/EXCLKS − Output Port 13. Output port P137 Input 1-bit output port and 1-bit input port. Input port INTP0 P140 I/O Port 14. Input port PCLBUZ0/INTP6 Analog input ANI18 P130 P146 P147 3-bit I/O port. P147 can be set to analog input. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a − port software setting. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 24 RL78/F12 CHAPTER 2 PIN FUNCTIONS 2.1.5 64-pin products (1/2) Function Name P00 I/O I/O Function P01 Port 0. 7-bit I/O port. P02 Input of P01, P03 and P04 can be set to TTL input buffer. After Reset Input port P04 P05 ANI17/SO10/TXD1 ANI16/SI10/RXD1/ SDA10 SCK10/SCL10 TI05/TO05 TI06/TO06 P06 P10 TI00 TO00 Output of P00, P02, P03 and P04 can be set to N-ch opendrain output (VDD tolerance) Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P03 Alternate Function I/O P11 P12 Port 1. 8-bit I/O port. Input of P13 to P17 can be set to TTL input buffer. Output of P10 to P15, and P17 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port SCK00/SCL00/SCKS0/ (TI07)/(TO07) SI00/RXD0/SDA00/ TOOLRXD/SIS0/ RXDS0/(TI06)/(TO06) SO00/TXD0/ TOOLTXD/SOS0/ TXDS0/(INTP5)/(TI05)/ (TO05) P13 TXD2/SO20/(SDAA0)/ (TI04)/(TO04) P14 RXD2/SI20/SDA20/ (SCLA0)/(TI03)/ (TO03) P15 SCK20/SCL20/(TI02)/ (TO02) P16 TI01/TO01/INTP5/ (RXD0)/(SI00) P17 TI02/TO02/(TXD0)/ (SO00) P20 I/O P21 P22 Port 2. 8-bit I/O port. Input/output can be specified in 1-bit units. Analog input port ANI0/AVREFP ANI1/AVREFM ANI2 P23 ANI3 P24 ANI4 P25 ANI5 P26 ANI6 P27 ANI7 P30 I/O P31 P40 P41 P42 P43 Remark I/O Port 3. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port Port 4. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port INTP3/RTC1HZ/ SCK11/SCL11 TI03/TO03/INTP4/ (PCLBUZ0) TOOL0 TI07/TO07 TI04/TO04 − Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 25 RL78/F12 CHAPTER 2 PIN FUNCTIONS (2/2) Function Name P50 I/O I/O P51 P52 P53 P54 P55 P60 I/O P61 P62 P63 P70 I/O Function After Reset Port 5. 6-bit I/O port. Input of P55 can be set to TTL input buffer. Output of P50 and P55 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input port Port 6. 4-bit I/O port. Output of P60 to P63 can be set to N-ch open-drain output (6 V tolerance). Input/output can be specified in 1-bit units. Input port Port 7. Input port (INTP10) SOS1/(INTP11) SIS1 SCKS1/(PCLBUZ1)/ (SCK00) SCLA0 SDAA0 − − KR0/SCK21/SCL21 KR1/SI21/SDA21 Output of P71 and P74 can be set to N-ch open-drain output P72 INTP1/SI11/SDA11/ LRXD INTP2/SO11/LTXD 8-bit I/O port. P71 Alternate Function KR2/SO21 (VDD tolerance). P73 Input/output can be specified in 1-bit units. KR3/SO01 P74 Use of an on-chip pull-up resistor can be specified by a KR4/INTP8/SI01/ software setting. SDA01 KR5/INTP9/SCK01/ P75 SCL01 P76 KR6/INTP10/(RXD2) P77 KR7/INTP11/(TXD2) P120 P121 I/O Input P122 Port 12. Analog input 1-bit I/O port and 4-bit input port. port P120 can be set to analog input. Input port For only P120, input/output can be specified in 1-bit units. X1 X2/EXCLKS For only P120, use of an on-chip pull-up resistor can be P123 ANI19 XT1 specified by a software setting. P124 XT2/EXCLKS − Output Port 13. Output port P137 Input 1-bit output port and 1-bit input port. Input port INTP0 P140 I/O Port 14. Input port PCLBUZ0/INTP6 P130 P141 P146 P147 Remark 4-bit I/O port. PCLBUZ1/INTP7 P147 can be set to analog input. − Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a Analog input software setting. port ANI18 Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 26 RL78/F12 CHAPTER 2 PIN FUNCTIONS 2.1.6 Pins for each product (pins other than port pins) (1/3) Function Name 64-pin 48-pin 32-pin 30-pin 20-pin √ √ √ √ √ ANI1 √ √ √ √ √ ANI2 √ √ √ √ √ ANI3 √ √ √ √ − ANI4 √ √ − − − ANI5 √ √ − − − ANI6 √ √ − − − ANI7 √ √ − − − ANI16 √ − √ √ √ ANI17 √ − √ √ − ANI18 √ √ √ √ − ANI19 √ √ √ √ − √ √ √ √ √ INTP1 √ √ √ √ √ INTP2 √ √ √ √ √ INTP3 √ √ √ √ − INTP4 √ √ √ √ √ INTP5 √ √ √ √ √ INTP6 √ √ − − − INTP8 √ √ − − − INTP9 √ √ − − − INTP10 √ − − − − INTP11 √ − − − − √ √ − − − KR1 √ √ − − − KR2 √ √ − − − KR3 √ √ − − − KR4 √ √ − − − KR5 √ √ − − − KR6 √ − − − − KR7 √ − − − − ANI0 INTP0 KR0 I/O Input Input Input Function A/D converter analog input External interrupt request input Key interrupt input LRxD0 Input Serial data input to LIN-UART0 √ √ √ √ √ LTxD0 Output Serial data output from LIN-UART0 √ √ √ √ √ PCLBUZ0 Output Clock output/buzzer output √ √ √ √ √ √ √ √ √ − √ √ √ √ √ √ √ √ √ √ PCLBUZ1 REGC − Connecting regulator output stabilization capacitance for internal operation. Connect to VSS via a capacitor (0.47 to 1 μF). RESET Input System reset input R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 27 RL78/F12 CHAPTER 2 PIN FUNCTIONS (2/3) Function Name 64-pin 48-pin 32-pin 30-pin 20-pin Serial data input to UART0 √ √ √ √ √ RxD1 Serial data input to UART1 √ √ √ √ − RxD2 Serial data input to UART2 √ √ √ √ − RxDS0 Serial data input to UARTS0 √ √ √ √ √ Clock input/output for CSI00, CSI01, CSI10, CSI11, √ √ √ √ √ CSI20, CSI21,CSIS0 and CSIS1 √ √ − − − SCK10 √ − − − − SCK11 √ √ √ √ − SCK20 √ √ √ √ − SCK21 √ √ − − − SCKS0 √ √ √ √ √ √ − − − − √ √ √ √ − √ √ √ √ √ SCL01 √ √ − − − SCL10 √ − − − − SCL11 √ √ √ √ − RxD0 SCK00 I/O Input I/O SCK01 Function SCKS1 SCLA0 SCL00 I/O I/O 2 Clock input/output for I C 2 Clock input/output for simplified I C SCL20 √ √ √ √ − SCL21 √ √ − − − √ √ √ √ − √ √ √ √ √ SDA01 √ √ − − − SDA10 √ − − − − SDA11 √ √ √ √ − SDA20 √ √ √ √ − SDAA0 SDA00 I/O I/O 2 Serial data I/O for I C 2 Serial data I/O for simplified I C √ √ − − − Serial data input to CSI00, CSI01, CSI10, CSI11, √ √ √ √ √ CSI20, CSI21, CSIS0, and CSIS1 √ √ − − − SI10 √ − − − − SI11 √ √ √ √ − SI20 √ √ √ √ − SI21 √ √ − − − SIS0 √ √ √ √ √ SDA21 SI00 Input SI01 √ − − − − Serial data output from CSI00, CSI01, CSI10, CSI11, √ √ √ √ √ CSI20, CSI21, CSIS0, and CSIS1 √ √ − − − SO10 √ − − − − SO11 √ √ √ √ − SO20 √ √ √ √ − SO21 √ √ − − − SOS0 √ √ √ √ √ SOS1 √ − − − − SIS1 SO00 SO01 Output R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 28 RL78/F12 CHAPTER 2 PIN FUNCTIONS (3/3) Function Name 64-pin 48-pin 32-pin 30-pin 20-pin External count clock input to 16-bit timer 00 √ √ √ √ − TI01 External count clock input to 16-bit timer 01 √ √ √ √ √ TI02 External count clock input to 16-bit timer 02 √ √ √ √ √ TI03 External count clock input to 16-bit timer 03 √ √ √ √ √ TI04 External count clock input to 16-bit timer 04 √ (√) (√) (√) − TI05 External count clock input to 16-bit timer 05 √ (√) (√) (√) (√) TI06 External count clock input to 16-bit timer 06 √ (√) (√) (√) (√) TI07 External count clock input to 16-bit timer 07 √ √ (√) (√) (√) 16-bit timer 00 output √ √ √ √ √ TO01 16-bit timer 01 output √ √ √ √ √ TO02 16-bit timer 02 output √ √ √ √ √ TO03 16-bit timer 03 output √ √ √ √ √ TO04 16-bit timer 04 output √ (√) (√) (√) − TO05 16-bit timer 05 output √ (√) (√) (√) (√) TO06 16-bit timer 06 output √ (√) (√) (√) (√) TO07 16-bit timer 07 output √ √ (√) (√) (√) Serial data output from UART0 √ √ √ √ √ TxD1 Serial data output from UART1 √ √ √ √ − TxD2 Serial data output from UART2 √ √ √ √ − TxDS0 Serial data output from UARTS0 √ √ √ √ √ Resonator connection for main system clock √ √ √ √ √ √ √ √ √ √ TI00 TO00 TxD0 I/O Input Output Output Function X1 Input X2 Output EXCLK Input External clock input for main system clock √ √ √ √ √ EXCLKS Input External clock input for subsystem clock √ √ − − − XT1 Input Resonator connection for subsystem clock √ √ − − − XT2 Output √ √ − − − VDD − Positive power supply for all pins √ √ √ √ √ EVDD − Positive power supply for pins other than above- √ − − − − mentioned VDD connected pins AVREFP Input A/D converter reference potential (+ side) input √ √ √ √ √ AVREFM Input A/D converter reference potential (− side) input √ √ √ √ √ VSS − Ground potential for all pins √ √ √ √ √ EVSS − Ground potential for pins other than above-mentioned √ − − − − √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ VSS connected pins TOOLRxD Input UART reception pin for the external device connection used during flash memory programming TOOLTxD Output UART transmission pin for the external device connection used during flash memory programming TOOL0 Remark I/O Data I/O for flash memory programmer/debugger The checked function is available only when the bit corresponding to the function in the peripheral I/O redirection register (PIOR) is set to 1. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 29 RL78/F12 CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions Remark The pins mounted depend on the product. See 1.3 Pin Configuration (Top View) and 2.1 Pin Function List. 2.2.1 P00 to P06 (port 0) P00 to P06 function as an I/O port. These pins also function as timer I/O, A/D converter analog input, serial interface data I/O, and clock I/O. Input to the P01, P03, P04 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units, using port input mode register 0 (PIM0). Output from the P00 and P02 to P04 pins can be specified as normal CMOS output or N-ch open-drain output (VDD tolerance) in 1-bit units, using port output mode register 0 (POM0). Input to the P00 to P03 pins can be specified as analog input or digital input in 1-bit units, using port mode control register 0 (PMC0). The following operation modes can be specified in 1-bit units. (1) Port mode P00, P01 function as an I/O port. P00, P01 can be set to input or output port in 1-bit units using port mode register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0). (2) Control mode P00, P01 function as timer I/O, A/D converter analog input, serial interface data I/O, and clock I/O. (a) ANI16, ANI17 These are the analog input pins (ANI16, ANI17) of A/D converter. When using these pins as analog input pins, see 12.10 (5) Analog input (ANIn) pins. (b) TI00 This is the pin for inputting an external count clock/capture trigger to 16-bit timer 00. (c) TO00 This is the timer output pins of 16-bit timer 00. (d) TxD1 This is a serial data output pin of serial interface UART1. (e) RxD1 This is a serial data input pin of serial interface UART1. 2.2.2 P10 to P17 (port 1) P10 to P17 function as an I/O port. These pins also function as serial interface data I/O, clock I/O, programming UART I/O, timer I/O, clock/buzzer output, and external interrupt request input. Input to the P13 to P17 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units, using port input mode register 1 (PIM1). Output from the P10 to P15 and P17 pins can be specified as normal CMOS output or N-ch open-drain output (VDD tolerance) in 1-bit units, using port output mode register 1 (POM1). The following operation modes can be specified in 1-bit units. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 30 RL78/F12 CHAPTER 2 PIN FUNCTIONS (1) Port mode P10 to P17 function as an I/O port. P10 to P17 can be set to input or output port in 1-bit units using port mode register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1). (2) Control mode P10 to P17 function as serial interface data I/O, clock I/O, programming UART I/O, timer I/O, clock/buzzer output, and external interrupt request input. (a) INTP5 This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) TxD0, TxD2, TxDS0 These are the serial data output pins of serial interface UART0, UART2 and UARTS0. (c) RxD0, RxD2, RxDS0 These are the serial data input pins of serial interface UART0, UART2 and UARTS0. (d) SCK00, SCK20, SCKS0 These are the serial clock I/O pins of serial interface CSI00, CSI20 and CSIS0. (e) SI00, SI20, SIS0 These are the serial data input pins of serial interface CSI00, CSI20 and CSIS0. (f) SO00, SO11, SO20 These are the serial data output pins of serial interface CSI00, CSI20 and CSIS0. (g) SDA00, SDA20 2 These are the serial data I/O pins of serial interface for simplified I C. (h) SCL00, SCL20 2 These are the serial clock I/O pins of serial interface for simplified I C. (i) TI01, TI02 These are the pins for inputting an external count clock/capture trigger to 16-bit timers 01 and 02. (j) TO01, TO02 These are the timer output pins of 16-bit timers 01 and 02. (k) TOOLTxD This UART serial data output pin for an external device connection is used during flash memory programming. (l) TOOLRxD This UART serial data input pin for an external device connection is used during flash memory programming. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 31 RL78/F12 CHAPTER 2 PIN FUNCTIONS 2.2.3 P20 to P27 (port 2) P20 to P27 function as an I/O port. These pins also function as A/D converter analog input and reference voltage input. The following operation modes can be specified in 1-bit units. (1) Port mode P20 to P27 function as an I/O port. P20 to P27 can be set to input or output port in 1-bit units using port mode register 2 (PM2). (2) Control mode P20 to P27 function as A/D converter analog input and reference voltage input. (a) ANI0 to ANI7 These are the analog input pins (ANI0 to ANI7) of A/D converter. When using these pins as analog input pins, see 12.10 (5) Analog input (ANIn) pins. (b) AVREFP This is a pin that inputs the A/D converter reference potential (+ side). (c) AVREFM This is a pin that inputs the A/D converter reference potential (−side). 2.2.4 P30, P31 (port 3) P30, P31 function as an I/O port. These pins also function as external interrupt request input, real-time clock correction clock output, serial interface clock I/O, and timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P30, P31 function as an I/O port. P30 and P31 can be set to input or output port in 1-bit units using port mode register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3). (2) Control mode P30, P31 function as external interrupt request input, real-time clock correction clock output, serial interface clock I/O, and timer I/O. (a) INTP3, INTP4 These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) SCK11 This is a serial clock I/O pin of serial interface CSI11. (c) SCL11 This is a serial clock output pin of serial interface for simplified I2C. (e) TI03 This is a pin for inputting an external count clock/capture trigger to 16-bit timer 03. (f) TO03 This is a timer output pin from 16-bit timer 03. (g) RTC1HZ This is a real-time clock correction clock (1 Hz) output pin. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 32 RL78/F12 CHAPTER 2 PIN FUNCTIONS 2.2.5 P40 to P43 (port 4) P40 to P43 function as an I/O port. These pins also function as data I/O for a flash memory programmer/debugger, and timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P40 to P43 function as an I/O port. P40 to P43 can be set to input or output port in 1-bit units using port mode register 4 (PM4). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (PU4). Be sure to connect an external pull-up resistor to P40 when on-chip debugging is enabled (by using an option byte). (2) Control mode P40 to P43 function as data I/O for a flash memory programmer/debugger and timer I/O. (a) TI04, TI07 This is the pin for inputting an external count clock/capture trigger to 16-bit timer 04, 07. (b) TO04, TO07 This is the timer output pin from 16-bit timer 04, 07. (c) TOOL0 This is a data I/O pin for a flash memory programmer/debugger. Be sure to pull up this pin externally when on-chip debugging is enabled (pulling it down is prohibited). Caution After reset release, the relationships between P40/TOOL0 and the operation mode are as follows. Table 2-1. Relationships between P40/TOOL0 and Operation Mode After Reset Release Operation mode P40/TOOL0 VDD Normal operation mode 0V Flash memory programming mode For details, see 27.5, Programming Method. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 33 RL78/F12 CHAPTER 2 PIN FUNCTIONS 2.2.6 P50 to P55 (port 5) P50 to P55 function as an I/O port. These pins also function as external interrupt request input, and serial interface data I/O. Output from the P50 and P55 pins can be specified as normal CMOS output or N-ch open-drain output (VDD tolerance) in 1-bit units, using port output mode register 5 (POM5). Input of the P55 pin can be specified as normal input buffer or TTL input buffer in 1-bit units, using port input mode register (PIM5). The following operation modes can be specified in 1-bit units. (1) Port mode P50 to P55 function as an I/O port. P50 to P55 can be set to input or output port in 1-bit units using port mode register 5 (PM5). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (PU5). (2) Control mode P50 to P55 function as external interrupt request input, and serial interface data I/O. (a) INTP1, INTP2 These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) SI11 This is the serial data input pin of serial interface CSI11. (c) SO11 This is the serial data output pin of serial interface CSI11. (d) SDA11 This is the serial data I/O pin of serial interface for simplified I2C. (e) LRxD0 This is a serial data input pin of serial interface LIN-UART0. (f) LTxD0 This is a serial data output pin of serial interface LIN-UART0. (g) SOS1 This is a serial data output pin of serial interface CSIS1. (h) SIS1 This is a serial data input pin of serial interface CSIS1. (i) SCKS1 This is a clock I/O pin of serial interface CSIS1. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 34 RL78/F12 CHAPTER 2 PIN FUNCTIONS 2.2.7 P60 to P63 (port 6) P60 to P63 function as an I/O port. These pins also function as serial interface data I/O, and clock I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P60 to P63 function as an I/O port. P60 to P63 can be set to input port or output port in 1-bit units using port mode register 6 (PM6). Output of P60 to P63 is N-ch open-drain output (6 V tolerance). (2) Control mode P60 to P63 function as serial interface data I/O, and clock I/O. (a) SCLA0 This is the serial clock I/O pin of serial interface IICA. (b) SDAA0 This is the serial data I/O pin of serial interface IICA. 2.2.8 P70 to P77 (port 7) P70 to P77 function as an I/O port. These pins also function as key interrupt input, serial interface data I/O, clock I/O, and external interrupt request input. Output from the P71 and P74 pins can be specified as normal CMOS output or N-ch open-drain output (VDD tolerance) in 1-bit units, using port output mode register 7 (POM7). The following operation modes can be specified in 1-bit units. (1) Port mode P70 to P77 function as an I/O port. P70 to P77 can be set to input or output port in 1-bit units using port mode register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7). (2) Control mode P70 to P77 function as key interrupt input, serial interface data I/O, clock I/O, and external interrupt request input. (a) INTP8 to INTP11 These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) KR0 to KR7 These are the key interrupt input pins. (c) SI01, SI21 These are the serial data input pins of serial interface CSI01 and CSI21. (d) SO01, SO21 These are the serial data output pins of serial interface CSI01 and CSI21. (e) SCK01, SCK21 These are the serial clock I/O pins of serial interface CSI01 and CSI21. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 35 RL78/F12 (f) CHAPTER 2 PIN FUNCTIONS SCL01, SCL21 2 These are the serial clock output pins of serial interface for simplified I C. (g) SDA01, SDA21 2 These are the serial data I/O pins of serial interface for simplified I C. 2.2.9 P120 to P124 (port 12) P120 function as an I/O port. P121 to P124 functions as 4-bit input port. These pins also function as A/D converter analog input, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input for main system clock, and external clock input for subsystem clock. Input to the P120 pin can be specified as analog input or digital input in 1-bit units, using port mode control register 12 (PMC12). The following operation modes can be specified in 1-bit units. (1) Port mode P120 function as a 1-bit I/O port. P120 can be set to input or output port using port mode register 12 (PM12). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). P121 to P124 functions as a 4-bit input port. (2) Control mode P120 to P124 function as A/D converter analog input, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input for main system clock, and external clock input for subsystem clock. (a) ANI19 This is an analog input pin of A/D converter. When using this pin as analog input pin, see 12.10 (5) Analog input (ANIn) pins. (b) X1, X2 These are the pins for connecting a resonator for main system clock. (c) EXCLK This is an external clock input pin for main system clock. (d) XT1, XT2 These are the pins for connecting a resonator for subsystem clock. (e) EXCLKS This is an external clock input pin for subsystem clock. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 36 RL78/F12 CHAPTER 2 PIN FUNCTIONS 2.2.10 P130, P137 (port 13) P130 functions as a 1-bit output-only port. P137 functions as a 1-bit input-only port. P137 pin also functions as external interrupt request input. (1) Port mode P130 functions as a 1-bit output-only port. P137 functions as a 1-bit input-only port. (2) Control mode P137 functions as external interrupt request input. (a) INTP0 This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.11 P140, P141, P146, P147 (port 14) P140, P141, P146, P147 function as an I/O port. These pins also function as clock/buzzer output, external interrupt request input, and A/D converter analog input. Input to the P147 pin can be specified as analog input or digital input in 1-bit units, using port mode control register 14 (PMC14). The following operation modes can be specified in 1-bit units. (1) Port mode P140, P141, P146, P147 function as an I/O port. P140, P141, P146, P147 can be set to input or output port in 1-bit units using port mode register 14 (PM14). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (PU14). (2) Control mode P140, P141, P146, P147 function as clock/buzzer output, external interrupt request input, and A/D converter analog input. (a) ANI18 This is an analog input pin of A/D converter. When using this pin as analog input pin, see 12.10 (5) Analog input (ANIn) pins. (b) INTP6, INTP7 This is the external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (c) PCLBUZ0, PCLBUZ1 This is the clock/buzzer output pin. 2.2.12 VDD, VSS (1) VDD VDD is the positive power supply pin. (2) VSS VSS is the ground potential pin. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 37 RL78/F12 CHAPTER 2 PIN FUNCTIONS 2.2.13 RESET This is the active-low system reset input pin. When the external reset pin is not used, connect this pin directly or via a resistor to VDD. When the external reset pin is used, design the circuit based on VDD. 2.2.14 REGC This is the pin for connecting regulator output stabilization capacitance for internal operation. Connect this pin to VSS via a capacitor (0.47 to 1 μF: target). Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage. REGC VSS Caution Keep the wiring length as short as possible for the broken-line part in the above figure. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 38 RL78/F12 CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins. Table 2-2. Connection of Unused Pins (64-pin products ) (1/2) Pin Name I/O Circuit Type P00/TI00 8-R-1 P01/TO00 5-AN-1 P02/ANI17/SO10/TXD1 11-U-1 P03/ANI16/SI10/RXD1/ 11-V-1 I/O I/O Recommended Connection of Unused Pins Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. SDA10 P04/SCK10/SCL10 5-AN-1 P05/TI05/TO05 8-R-1 P06/TI06/TO06 P10/SCK00/SCKS0/ 5-AN-1 SCL00/(TI07)/(TO07) P11/SI00/RxD0/SIS0/ RxDS0/TOOLRxD/SDA00/ (TI06)/(TO06) P12/SO00/TxD0/SOS0/ 8-R-1 TxDS0/TOOLTxD/ (INTP5)/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/ 5-AN-1 (TI04)/(TO04) P14/RxD2/SI20/SDA20/ (SCLA0)/(TI03)/(TO03) P15/SCK20/SCL20/(TI02)/ (TO02) P16/TI01/TO01/INTP5/(RXD0)/ (SI00) P17/TI02/TO02/(TXD0)/(SO00) P20/ANI0/AVREFP 11-T Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. P21/ANI1/AVREFM 11-G P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 P30/INTP3/RTC1HZ/SCK11/ 8-R-1 SCL11 Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. P31/TI03/TO03/INTP4/ (PCLBUZ0) Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Caution With products with 48 or less pins, replace EVDD and EVSS described in Recommended Connection of Unused Pins with VDD and VSS, respectively. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 39 RL78/F12 CHAPTER 2 PIN FUNCTIONS Table 2-2. Connection of Unused Pins (64-pin products ) (2/2) Pin Name P40/TOOL0 I/O Circuit Type 8-R-1 I/O Recommended Connection of Unused Pins Input: I/O Independently connect to EVDD or EVSS via a resistor. Output: Leave open. P41/TI07/TO07 P42/TI04/TO04 P43 P50/INTP1/SI11/SDA11/ LRxD0 P51/INTP2/SO11/LTxD0 P52/(INTP10) P53/SOS1/(INTP11) P54/SIS1 P55/SCKS1/(PCLBUZ1)/ 5-AN-1 (SCK00) P60/SCLA0 13-R P61/SDAA0 P62 P63 P70/KR0/SCK21/SCL21 8-R-1 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3/SO01 P74/KR4/INTP8/SI01/ SDA01 P75/KR5/INTP9/SCK01/ SCL01 P76/KR6/INTP10/(RXD2) P77/KR7/INTP11/(TXD2) P120/ANI19 11-U-1 P121/X1 37-C Input Independently connect to VDD or VSS via a resistor. P130 3-C Output Leave open. P137/INTP0 2 Input Independently connect to VDD or VSS via a resistor. P140/PCLBUZ0/INTP6 8-R-1 I/O Input: P122/X2/EXCLK P123/XT1 P124/XT2/EXCLKS Independently connect to EVDD or EVSS via a resistor. Output: Leave open. P141/PCLBUZ1/INTP7 P146 P147/ANI18 11-U-1 RESET 2 − REGC Remark Input − Connect directly or via a resistor to VDD. Connect to VSS via capacitor (0.47 to 1 μF). Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Caution With products with 48 or less pins, replace EVDD and EVSS described in Recommended Connection of Unused Pins with VDD and VSS, respectively. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 40 RL78/F12 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type 2 Type 3-C EVDD P-ch IN data OUT N-ch Schmitt-triggered input with hysteresis characteristics EVSS Type 5-AN-1 Type 8-R-1 EVDD EVDD pull-up enable P-ch pullup enable P-ch EVDD EVDD data P-ch IN/OUT output disable data P-ch N-ch IN/OUT EVSS output disable ITHL N-ch EVSS ITHL CMOS TTL input characteristic input enable Type 13-R Type 37-C XT2 IN/OUT data output disable input enable N-ch amp enable P-ch N-ch EVSS XT1 input enable R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 41 RL78/F12 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) Type 11-G Type 11-T EVDD data P-ch VDD IN/OUT data P-ch output disable N-ch IN/OUT EVSS output disable N-ch P-ch Comparator VSS + _ Comparator N-ch P-ch Series resistor string voltage + _ VSS N-ch Series resistor string voltage VSS input enable input enable P-ch AVREFP N-ch Type 11-U-1 Type 11-V-1 EVDD pull-up enable EVDD P-ch pull-up enable P-ch EVDD data EVDD data P-ch output disable N-ch P-ch IN/OUT output disable N-ch IN/OUT EVSS EVSS ITHL ITHL CMOS TTL input enable input characteristic P-ch Comparator P-ch Comparator + + _ N-ch Series resistor string voltage _ N-ch Series resistor string voltage VSS R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 VSS 42 RL78/F12 CHAPTER 3 CPU ARCHITECTURE CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the RL78/F12 can access a 1 MB memory space. Figures 3-1 to 3-6 show the memory maps. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 43 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Figure 3-1. Memory Map (R5F10968) 01FFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes RAMNotes 1, 2 0.5 KB FFD00H FFCFFH Program area ReservedNote 3 01FFFH F2000H F1FFFH Data flash memory 4 KB F1000H F0FFFH Reserved 010C4H 010C3H F0800H F07FFH Special function register (2nd SFR) 2 KB Data memory space 010CEH 010CDH 010C0H 010BFH 01080H 0107FH F0000H EFFFFH On-chip debug security ID setting areaNote 4 10 bytes Option byte areaNote 4 4 bytes Boot cluster 1 CALLT table area 64 bytes Vector table area 128 bytes 01000H 00FFFH Program area Reserved 000CEH 000CDH 000C4H 000C3H 000C0H 000BFH 00080H 0007FH Program memory space 02000H 01FFFH 00000H On-chip debug security ID setting areaNote 4 10 bytes Option byte areaNote 4 4 bytes Boot cluster 0Note 4 CALLT table area 64 bytes Vector table area 128 bytes Code flash memory 8 KB 00000H Notes 1. Do not allocate RAM addresses which are used as stack area, data buffer used by the libraries, branch destination of vector interrupt processing, and DMA destination/source addresses to the area FFE20H to FFEDFH when performing self-programming or rewriting the data flash memory area. 2. Instructions can be executed from the RAM area excluding the general-purpose register area. 3. The mirror area is not provided in the R5F10968. 4. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH. 5. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.6 Security Settings). Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 44 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map (R5F109xA (x = 6, A, B, G, L)) 03FFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes RAMNotes 1, 2 1 KB FFB00H FFAFFH Program area Reserved F4000H F3FFFH 01FFFH Mirror 8 KB F2000H F1FFFH 010CEH 010CDH Data flash memory 4 KB F1000H F0FFFH Reserved 010C4H 010C3H F0800H F07FFH 010C0H 010BFH Special function register (2nd SFR) 2 KB Data memory space 01080H 0107FH F0000H EFFFFH On-chip debug security ID setting areaNote 3 10 bytes Option byte areaNote 3 4 bytes Boot cluster 1 CALLT table area 64 bytes Vector table area 128 bytes 01000H 00FFFH Program area Reserved 000CEH 000CDH 000C4H 000C3H 000C0H 000BFH 00080H 0007FH Program memory space 04000H 03FFFH 00000H On-chip debug security ID setting areaNote 3 10 bytes Option byte areaNote 3 4 bytes Boot cluster 0Note 4 CALLT table area 64 bytes Vector table area 128 bytes Code flash memory 16 KB 00000H Notes 1. Do not allocate RAM addresses which are used as stack area, data buffer used by the libraries, branch destination of vector interrupt processing, and DMA destination/source addresses to the area FFE20H to FFEDFH when performing self-programming or rewriting the data flash memory area. 2. Instructions can be executed from the RAM area excluding the general-purpose register area. 3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH. 4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.6 Security Settings). Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 45 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map (R5F109xB (x = 6, A, B, G, L)) 05FFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes RAMNotes 1, 2 1.5 KB FF900H FF8FFH Program area Reserved F6000H F5FFFH Mirror 16 KB F2000H F1FFFH 01FFFH 010CEH 010CDH Data flash memory 4 KB F1000H F0FFFH Reserved 010C4H 010C3H F0800H F07FFH 010C0H 010BFH Special function register (2nd SFR) 2 KB Data memory space 01080H 0107FH F0000H EFFFFH On-chip debug security ID setting areaNote 3 10 bytes Option byte areaNote 3 4 bytes Boot cluster 1 CALLT table area 64 bytes Vector table area 128 bytes 01000H 00FFFH Program area Reserved 000CEH 000CDH 000C4H 000C3H 000C0H 000BFH 00080H 0007FH Program memory space 06000H 05FFFH 00000H On-chip debug security ID setting areaNote 3 10 bytes Option byte areaNote 3 4 bytes Boot cluster 0Note 4 CALLT table area 64 bytes Vector table area 128 bytes Code flash memory 24 KB 00000H Notes 1. Do not allocate RAM addresses which are used as stack area, data buffer used by the libraries, branch destination of vector interrupt processing, and DMA destination/source addresses to the area FFE20H to FFEDFH when performing self-programming or rewriting the data flash memory area. 2. Instructions can be executed from the RAM area excluding the general-purpose register area. 3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH. 4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.6 Security Settings). Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 46 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Memory Map (R5F109xC (x = 6, A, B, G, L)) 07FFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes RAMNotes 1, 2 2 KB FF700H FF6FFH Program area Reserved F8000H F7FFFH 01FFFH Mirror 24 KB F2000H F1FFFH F1000H F0FFFH Data flash memory 4 KB 010CEH 010CDH Reserved 010C4H 010C3H F0800H F07FFH 010C0H 010BFH Special function register (2nd SFR) 2 KB Data memory space F0000H EFFFFH 01080H 0107FH On-chip debug security ID setting areaNote 3 10 bytes Option byte areaNote 3 4 bytes Boot cluster 1 CALLT table area 64 bytes Vector table area 128 bytes 01000H 00FFFH Reserved Program area 000CEH 000CDH 000C4H 000C3H 000C0H 000BFH 00080H 0007FH Program memory space 08000H 07FFFH Option byte areaNote 3 4 bytes Boot cluster 0Note 4 CALLT table area 64 bytes Vector table area 128 bytes Code flash memory 32 KB 00000H 00000H On-chip debug security ID setting areaNote 3 10 bytes Notes 1. Do not allocate RAM addresses which are used as stack area, data buffer used by the libraries, branch destination of vector interrupt processing, and DMA destination/source addresses to the area FFE20H to FFEDFH when performing self-programming or rewriting the data flash memory area. 2. Instructions can be executed from the RAM area excluding the general-purpose register area. 3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH. 4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.6 Security Settings). Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 47 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Memory Map (R5F109xD (x = 6, A, B, G, L)) 0BFFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes RAMNotes 1, 2 3 KB Program area FF300H FF2FFH Reserved FC000H FDFFFH F1000H F0FFFH Data flash memory 4 KB 010CEH 010CDH Reserved 010C4H 010C3H F0800H F07FFH Special function register (2nd SFR) 2 KB Data memory space 01FFFH Mirror 40 KB F2000H F1FFFH F0000H EFFFFH 010C0H 010BFH 01080H 0107FH On-chip debug security ID setting areaNote 3 10 bytes Option byte areaNote 3 4 bytes Boot cluster 1 CALLT table area 64 bytes Vector table area 128 bytes Reserved 01000H 00FFFH Program area 000CEH 000CDH 000C4H 000C3H 000C0H 000BFH 00080H 0007FH 0C000H 0BFFFH Program memory space Option byte areaNote 3 4 bytes Boot cluster 0Note 4 CALLT table area 64 bytes Vector table area 128 bytes Code flash memory 48 KB 00000H On-chip debug security ID setting areaNote 3 10 bytes 00000H Notes 1. Do not allocate RAM addresses which are used as stack area, data buffer used by the libraries, branch destination of vector interrupt processing, and DMA destination/source addresses to the area FFE20H to FFEDFH when performing self-programming or rewriting the data flash memory area. 2. Instructions can be executed from the RAM area excluding the general-purpose register area. 3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH. 4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.6 Security Settings). Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 48 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Memory Map (R5F109xE (x = 6, A, B, G, L)) 0FFFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes RAMNotes 1, 2 4 KB Program area FEF00H FEEFFH Mirror 51.75 KB F2000H F1FFFH Data flash memory 4 KB F1000H F0FFFH Reserved F0800H F07FFH Special function register (2nd SFR) 2 KB Data memory space F0000H EFFFFH 01FFFH 010CEH 010CDH 010C4H 010C3H 010C0H 010BFH 01080H 0107FH On-chip debug security ID setting areaNote 3 10 bytes Option byte areaNote 3 4 bytes Boot cluster 1 CALLT table area 64 bytes Vector table area 128 bytes 01000H 00FFFH Reserved Program area 000CEH 000CDH 000C4H 000C3H 000C0H 000BFH 00080H 0007FH 10000H 0FFFFH Program memory space Option byte areaNote 3 4 bytes Boot cluster 0Note 4 CALLT table area 64 bytes Vector table area 128 bytes Code flash memory 64 KB 00000H On-chip debug security ID setting areaNote 3 10 bytes 00000H Notes 1. Do not allocate RAM addresses which are used as stack area, data buffer used by the libraries, branch destination of vector interrupt processing, and DMA destination/source addresses to the area FFE20H to FFEDFH when performing self-programming or rewriting the data flash memory area. In addition, the use of the area FEF00H to FF2FFH is prohibited, because this area might be used by each library. However, the area to which this prohibition applies may vary with the version of the library. For details, please refer to the manual for the individual library. 2. Instructions can be executed from the RAM area excluding the general-purpose register area. 3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH. 4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.6 Security Settings). Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 49 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-1 Correspondence Between Address Values and Block Numbers in Flash Memory. 0FFFFH Block 3FH 0FC00H 0FBFFH 007FFH 00400H 003FFH Block 01H Block 00H 1 KB 00000H (R5F109xE (x = 6, A, B, G, L)) R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 50 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory Address Value Block Number Address Value Block Number 00000H to 003FFH 00H 08000H to 083FFH 20H 00400H to 007FFH 01H 08400H to 087FFH 21H 00800H to 00BFFH 02H 08800H to 08BFFH 22H 00C00H to 00FFFH 03H 08C00H to 08FFFH 23H 01000H to 013FFH 04H 09000H to 093FFH 24H 01400H to 017FFH 05H 09400H to 097FFH 25H 01800H to 01BFFH 06H 09800H to 09BFFH 26H 01C00H to 01FFFH 07H 09C00H to 09FFFH 27H 02000H to 023FFH 08H 0A000H to 0A3FFH 28H 02400H to 027FFH 09H 0A400H to 0A7FFH 29H 02800H to 02BFFH 0AH 0A800H to 0ABFFH 2AH 02C00H to 02FFFH 0BH 0AC00H to 0AFFFH 2BH 03000H to 033FFH 0CH 0B000H to 0B3FFH 2CH 03400H to 037FFH 0DH 0B400H to 0B7FFH 2DH 03800H to 03BFFH 0EH 0B800H to 0BBFFH 2EH 03C00H to 03FFFH 0FH 0BC00H to 0BFFFH 2FH 04000H to 043FFH 10H 0C000H to 0C3FFH 30H 04400H to 047FFH 11H 0C400H to 0C7FFH 31H 04800H to 04BFFH 12H 0C800H to 0CBFFH 32H 04C00H to 04FFFH 13H 0CC00H to 0CFFFH 33H 05000H to 053FFH 14H 0D000H to 0D3FFH 34H 05400H to 057FFH 15H 0D400H to 0D7FFH 35H 05800H to 05BFFH 16H 0D800H to 0DBFFH 36H 05C00H to 05FFFH 17H 0DC00H to 0DFFFH 37H 06000H to 063FFH 18H 0E000H to 0E3FFH 38H 06400H to 067FFH 19H 0E400H to 0E7FFH 39H 06800H to 06BFFH 1AH 0E800H to 0EBFFH 3AH 06C00H to 06FFFH 1BH 0EC00H to 0EFFFH 3BH 07000H to 073FFH 1CH 0F000H to 0F3FFH 3CH 07400H to 077FFH 1DH 0F400H to 0F7FFH 3DH 07800H to 07BFFH 1EH 0F800H to 0FBFFH 3EH 07C00H to 07FFFH 1FH 0FC00H to 0FFFFH 3FH R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 51 RL78/F12 CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. The RL78/F12 products incorporate internal ROM (flash memory), as shown below. Table 3-2. Internal ROM Capacity Part Number Internal ROM Structure R5F10968 Flash memory Capacity 8192 × 8 bits (00000H to 01FFFH) R5F109xA (x = 6, A, B, G, L) 16384 × 8 bits (00000H to 03FFFH) R5F109xB (x = 6, A, B, G, L) 24576 × 8 bits (00000H to 05FFFH) R5F109xC (x = 6, A, B, G, L) 32768 × 8 bits (00000H to 07FFFH) R5F109xD (x = 6, A, B, G, L) 49152 × 8 bits (00000H to 0BFFFH) R5F109xE (x = 6, A, B, G, L) 65536 × 8 bits (00000H to 0FFFFH) The internal program memory space is divided into the following areas. (1) Vector table area The 128-byte area 00000H to 0007FH is reserved as a vector table area. The program start addresses for branch upon reset or generation of each interrupt request are stored in the vector table area. Furthermore, the interrupt jump address is a 64 K address of 00000H to 0FFFFH, because the vector code is assumed to be 2 bytes. Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. To use the boot swap function, set a vector table also at 01000H to 0107FH. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 52 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Vector Table (1/2) Vector Table Address Interrupt Source 64-pin 48-pin 32-pin 30-pin 20-pin 0000H RESET, POR, LVD, WDT, TRAP, IAW, RAMTOP √ √ √ √ √ 0004H INTWDTI √ √ √ √ √ 0006H INTLVI √ √ √ √ √ 0008H INTP0 √ √ √ √ √ 000AH INTP1 √ √ √ √ √ 000CH INTP2 √ √ √ √ √ 000EH INTP3 √ √ √ √ − 0010H INTP4 √ √ √ √ √ 0012H INTP5 √ √ √ √ √ 0014H INTST2/INTCSI20/INTIIC20 √ √ √ √ − 0016H INTSR2/INTCSI21/INTIIC21 √ √ Note 1 Note 1 − 0018H INTSRE2 √ √ √ √ − 001AH INTDMA0 √ √ √ √ √ 001CH INTDMA1 √ √ √ √ √ 001EH INTST0/INTCSI00/INTIIC00 √ √ √ √ √ 0020H INTSR0/INTCSI01/INTIIC01 √ √ Note 2 Note 2 Note 2 0022H INTSRE0 √ √ √ √ √ INTTM01H √ √ √ √ √ 0024H INTST1/INTCSI10/INTIIC10 √ Note 3 Note 3 Note 3 − 0026H INTSR1/INTCSI11/INTIIC11 √ √ √ √ − 0028H INTSRE1/INTTM03H √ √ √ √ Note 4 002AH INTIICA0 √ √ √ √ − 002CH INTTM00 √ √ √ √ √ 002EH INTTM01 √ √ √ √ √ 0030H INTTM02 √ √ √ √ √ 0032H INTTM03 √ √ √ √ √ 0034H INTAD √ √ √ √ √ 0036H INTRTC √ √ − − − 0038H INTIT √ √ √ √ √ 003AH INTKR √ √ − − − 003CH INTCSIS0/INTSTS0 √ √ √ √ √ 003EH INTCSIS1/INTSRS0 √ Note 5 Note 5 Note 5 Note 5 Notes 1. INTSR2 only. 2. INTSR0 only. 3. INTST1 only. 4. INTTM03H only. 5. INTCSIS1 only. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 53 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Vector Table (2/2) Vector Table Address Interrupt Source 64-pin 48-pin 32-pin 30-pin 20-pin 0040H INTWUTM √ √ √ √ √ 0042H INTTM04 √ √ √ √ √ 0044H INTTM05 √ √ √ √ √ 0046H INTTM06 √ √ √ √ √ 0048H INTTM07 √ √ √ √ √ 004AH INTP6 √ √ − − − 004CH INTP7/INTLT √ Note 2 Note 2 Note 2 Note 2 Note 1 √ √ Note 3 Note 3 Note 3 0050H INTP9/INTLS Note 1 √ √ Note 4 Note 4 Note 4 0052H INTP10/INTSRES0 √ Note 5 Note 5 Note 5 Note 5 0054H INTP11 √ − − − − 005EH INTMD √ √ √ √ √ 0062H INTFL √ √ √ √ √ 007EH BRK √ √ √ √ √ 004EH INTP8/INTLR Notes 1. For 48-pin products, when INTP8 and INTLR interrupts occur at the same time, the interrupt source cannot be distinguished from the vector address. The INTP9 and INTLS interrupts (that occur at the sane time) are the same as the condition above. 2. INTLT only. 3. INTLR only. 4. INTLS only. 5. INTSRES0 only. (2) CALLT instruction table area The 64-byte area 00080H to 000BFH can store the subroutine entry address of a 2-byte call instruction (CALLT). Set the subroutine entry address to a value in a range of 00000H to 0FFFFH (because an address code is of 2 bytes). To use the boot swap function, set a CALLT instruction table also at 01080H to 010BFH. (3) Option byte area A 4-byte area of 000C0H to 000C3H can be used as an option byte area. Set the option byte at 010C0H to 010C3H when the boot swap is used. For details, see CHAPTER 26 OPTION BYTE. (4) On-chip debug security ID setting area A 10-byte area of 000C4H to 000CDH and 010C4H to 010CDH can be used as an on-chip debug security ID setting area. Set the on-chip debug security ID of 10 bytes at 000C4H to 000CDH when the boot swap is not used and at 000C4H to 000CDH and 010C4H to 010CDH when the boot swap is used. For details, see CHAPTER 28 ON-CHIP DEBUG FUNCTION. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 54 RL78/F12 CHAPTER 3 CPU ARCHITECTURE 3.1.2 Mirror area The RL78/F12 mirrors the code flash area of 00000H to 0FFFFH, to F0000H to FFFFFH (the code flash area to be mirrored is set by the processor mode control register (PMC)). By reading data from F0000H to FFFFFH, an instruction that does not have the ES register as an operand can be used, and thus the contents of the code flash can be read with the shorter code. However, the code flash area is not mirrored to the SFR, extended SFR, RAM, and use prohibited areas. See 3.1 Memory Space for the mirror area of each product. The mirror area can only be read and no instruction can be fetched from this area. The following show examples. Example R5F109xE (x = 6, A, B, G) (Flash memory: 64 KB, RAM: 4 KB) FFFFFH Special-function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH FEF00H FEEFFH General-purpose register 32 bytes RAM 4 KB Mirror Note (same data as 02000H to 0EEFFH) F2000H F1FFFH Data flash memory F1000H F0FFFH Reserved F0800H F07FFH Special-function register (2nd SFR) 2 KB F0000H EFFFFH Mirror Reserved For example, 0E789H is mirrored to FE789H. Data can therefore be read by MOV A, !E789H, instead of MOV ES, #00H and MOV A, ES:!E789H. 10000H 0FFFFH Code flash memory 0EF00H 0EEFFH Code flash memory 02000H 01FFFH‚ Code flash memory 00000H R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 55 RL78/F12 Note CHAPTER 3 CPU ARCHITECTURE The mirror area is not provided in the R5F10968. The PMC register is described below. • Processor mode control register (PMC) This register sets the flash memory space for mirroring to area from F0000H to FFFFFH. The PMC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 3-7. Format of Configuration of Processor Mode Control Register (PMC) Address: FFFFEH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 PMC 0 0 0 0 0 0 0 MAA MAA Selection of flash memory space for mirroring to area from F0000H to FFFFFH 0 00000H to 0FFFFH is mirrored to F0000H to FFFFFH 1 Setting prohibited Cautions 1. Be sure to clear bit 0 (MAA) of this register to 0 (default value). 2. Set the PMC register only once during the initial settings prior to operating the DMA controller. Rewriting the PMC register other than during the initial settings is prohibited. 3. After setting the PMC register, wait for at least one instruction and access the mirror area. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 56 RL78/F12 CHAPTER 3 CPU ARCHITECTURE 3.1.3 Internal data memory space The RL78/F12 products incorporate the following RAMs. Table 3-4. Internal RAM Capacity Part Number Internal RAM R5F10968 512 × 8 bits (FFD00H-FFEFFH) R5F109xA (x = 6, A, B, G, L) 1024 × 8 bits (FFB00H-FFEFFH) R5F109xB (x = 6, A, B, G, L) 1536 × 8 bits (FF900H-FFEFFH) R5F109xC (x = 6, A, B, G, L) 2048 × 8 bits (FF700H to FFEFFH) R5F109xD (x = 6, A, B, G, L) 3072 × 8 bits (FF300H to FFEFFH) R5F109xE (x = 6, A, B, G, L) 4096 × 8 bits (FEF00H to FFEFFH) The internal RAM can be used as a data area and a program area where instructions are written and executed. Four general-purpose register banks consisting of eight 8-bit registers per bank are assigned to the 32-byte area of FFEE0H to FFEFFH of the internal RAM area. However, instructions cannot be executed by using the general-purpose registers. The internal RAM is used as a stack memory. Cautions 1. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching instructions or as a stack area. 2. While using the self-programming function or data flash function, the area FFE20H to FFEFFH cannot be used as stack memory. Furthermore, the areas of FEF00H to FF309H also cannot be used with the R5F109xE (x = 6, A, B, G), respectively. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 57 RL78/F12 CHAPTER 3 CPU ARCHITECTURE 3.1.4 Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area FFF00H to FFFFFH (see Table 3-5 in 3.2.4 Special function registers (SFRs)). Caution Do not access addresses to which SFRs are not assigned. 3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area On-chip peripheral hardware special function registers (2nd SFRs) are allocated in the area F0000H to F07FFH (see Table 3-6 in 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers)). SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area. An instruction that accesses the extended SFR area, however, is 1 byte longer than an instruction that accesses the SFR area. Caution Do not access addresses to which extended SFRs are not assigned. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 58 RL78/F12 CHAPTER 3 CPU ARCHITECTURE 3.1.6 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the RL78/F12, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of the special function registers (SFR) and general-purpose registers are available for use. Figures 3-8 to 3-13 show correspondence between data memory and addressing. For details of each addressing, see 3.4 Addressing for Processing Data Addresses. Figure 3-8. Correspondence Between Data Memory and Addressing (R5F10968) FFFFFH FFF20H FFF1FH FFF00H FFEFFH FFEE0H FFEDFH FFE20H FFE1FH FFD00H FFCFFH Special function register (SFR) 256 bytes General-purpose register 32 bytes SFR addressing Register addressing Short direct addressing RAMNote1 0.5 KB ReservedNote2 F2000H F1FFFH F1000H F0FFFH Data flash memory 4 KB Reserved F0800H F07FFH Special function register (2nd SFR) 2 KB F0000H EFFFFH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved 02000H 01FFFH Code flash memory 8 KB 00000H R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 59 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Notes 1. Use of the area FFE20H to FFEDFH is prohibited when using the self-programming function or data flash function, because this area is used for self-programming library. 2. The mirror area is not provided in the R5F10968. Figure 3-9. Correspondence Between Data Memory and Addressing (R5F109xA (x = 6, A, B, G, L)) FFFFFH FFF20H FFF1FH FFF00H FFEFFH FFEE0H FFEDFH FFE20H FFE1FH FFB00H FFAFFH Special function register (SFR) 256 bytes General-purpose register 32 bytes SFR addressing Register addressing Short direct addressing RAMNote 1 KB Reserved F4000H F3FFFH F2000H F1FFFH F1000H F0FFFH Mirror 8 KB Data flash memory 4 KB Reserved F0800H F07FFH Special function register (2nd SFR) 2 KB F0000H EFFFFH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved 04000H 03FFFH Code flash memory 16 KB 00000H Note Use of the area FFE20H to FFEDFH is prohibited when using the self-programming function or data flash function, because this area is used for self-programming library. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 60 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Correspondence Between Data Memory and Addressing (R5F109xB (x = 6, A, B, G, L)) FFFFFH FFF20H FFF1FH FFF00H FFEFFH FFEE0H FFEDFH FFE20H FFE1FH FF900H FF8FFH F6000H F5FFFH F2000H F1FFFH F1000H F0FFFH Special function register (SFR) 256 bytes General-purpose register 32 bytes SFR addressing Register addressing Short direct addressing RAMNote 1.5 KB Reserved Mirror 16 KB Data flash memory 4 KB Reserved F0800H F07FFH Special function register (2nd SFR) 2 KB F0000H EFFFFH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved 06000H 05FFFH Code flash memory 24 KB 00000H Note Use of the area FFE20H to FFEDFH is prohibited when using the self-programming function or data flash function, because this area is used for self-programming library. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 61 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Figure 3-11. Correspondence Between Data Memory and Addressing (R5F109xC (x = 6, A, B, G, L)) FFFFFH FFF20H FFF1FH FFF00H FFEFFH FFEE0H FFEDFH FFE20H FFE1FH FF700H FF6FFH F8000H F7FFFH F2000H F1FFFH F1000H F0FFFH Special function register (SFR) 256 bytes General-purpose register 32 bytes SFR addressing Register addressing Short direct addressing RAMNote 2 KB Reserved Mirror 24 KB Data flash memory 4 KB Reserved F0800H F07FFH Special function register (2nd SFR) 2 KB Direct addressing Register indirect addressing F0000H EFFFFH Based addressing Based indexed addressing Reserved 08000H 07FFFH Code flash memory 32 KB 00000H Note Use of the area FFE20H to FFEDFH is prohibited when using the self-programming function or data flash function, because this area is used for self-programming library. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 62 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Figure 3-12. Correspondence Between Data Memory and Addressing (R5F109xD (x = 6, A, B, G, L)) FFFFFH FFF20H FFF1FH FFF00H FFEFFH FFEE0H FFEDFH FFE20H FFE1FH FF300H FF2FFH FC000H FBFFFH F2000H F1FFFH F1000H F0FFFH Special function register (SFR) 256 bytes General-purpose register 32 bytes SFR addressing Register addressing Short direct addressing RAMNote 3 KB Reserved Mirror 40 KB Data flash memory 4 KB Reserved F0800H F07FFH Special function register (2nd SFR) 2 KB Direct addressing Register indirect addressing F0000H EFFFFH Based addressing Based indexed addressing Reserved 0C000H 0BFFFH Code flash memory 48 KB 00000H Note Use of the area FFE20H to FFEDFH is prohibited when using the self-programming function or data flash function, because this area is used for self-programming library. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 63 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Figure 3-13. Correspondence Between Data Memory and Addressing (R5F109xE (x = 6, A, B, G, L)) FFFFFH FFF20H FFF1FH FFF00H FFEFFH FFEE0H FFEDFH FFE20H FFE1FH FEF00H FEEFFH F2000H F1FFFH F1000H F0FFFH Special function register (SFR) 256 bytes General-purpose register 32 bytes SFR addressing Register addressing Short direct addressing RAMNote 4 KB Mirror 51.75 KB Data flash memory 4 KB Reserved F0800H F07FFH Special function register (2nd SFR) 2 KB Direct addressing Register indirect addressing F0000H EFFFFH Based addressing Based indexed addressing Reserved 10000H 0FFFFH Code flash memory 64 KB 00000H Note Use of the area FFE20H to FFEDFH and FEF00H to FF309H are prohibited when using the self-programming function or data flash function, because this area is used for self-programming library. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 64 RL78/F12 CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The RL78/F12 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 20-bit register that holds the address information of the next program to be executed. In normal operation, PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set. Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 3-14. Format of Program Counter 0 19 PC (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags set/reset by instruction execution. Program status word contents are stored in the stack area upon vectored interrupt request is acknowledged or PUSH PSW instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions. Reset signal generation sets the PSW register to 06H. Figure 3-15. Format of Program Status Word 7 PSW IE 0 Z RBS1 AC RBS0 ISP1 ISP0 CY (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled. When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment is controlled with an in-service priority flag (ISP1, ISP0), an interrupt mask flag for various interrupt sources, and a priority specification flag. The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Register bank select flags (RBS0, RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 65 RL78/F12 CHAPTER 3 CPU ARCHITECTURE (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flags (ISP1, ISP0) This flag manages the priority of acknowledgeable maskable vectored interrupts. Vectored interrupt requests specified lower than the value of ISP0 and ISP1 flags by the priority specification flag registers (PRn0L, PRn0H, PRn1L, PRn1H, PRn2L, PRn2H) (see 18.3 (3)) can not be acknowledged. Actual request acknowledgment is controlled by the interrupt enable flag (IE). Remark n = 0, 1 (f) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal RAM area can be set as the stack area. Figure 3-16. Format of Stack Pointer 15 0 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the stack memory. Each stack operation saves data as shown in Figure 3-17. Cautions 1. Since reset signal generation makes the SP contents undefined, be sure to initialize the SP before using the stack. 2. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space as a stack area. 3. While using the self-programming function or data flash function, the area FFE20H to FFEFFH cannot be used as stack memory. Furthermore, the areas of FEF00H to FF309H also cannot be used with the R5F109xE (x = 6, A, B, G), respectively. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 66 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Figure 3-17. Data to Be Saved to Stack Memory PUSH PSW instruction PUSH rp instruction SP←SP−2 ↑ SP−2 ↑ SP−1 ↑ SP → Register pair lower Register pair higher SP←SP−2 ↑ SP−2 ↑ SP−1 ↑ SP → PC7 to PC0 PC15 to PC8 PC19 to PC16 00H PSW Interrupt, BRK instruction (4-byte stack) CALL, CALLT instructions (4-byte stack) SP←SP−4 ↑ SP−4 ↑ SP−3 ↑ SP−2 ↑ SP−1 ↑ SP → 00H SP←SP−4 ↑ SP−4 ↑ SP−3 ↑ SP−2 ↑ SP−1 ↑ SP → PC7 to PC0 PC15 to PC8 PC19 to PC16 PSW 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The generalpurpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL). These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank. Cautions 1. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching instructions or as a stack area. 2. While using the self-programming function or data flash function, the area FFE20H to FFEFFH cannot be used as stack memory. Furthermore, the areas of FEF00H to FF309H also cannot be used with the R5F109xE (x = 6, A, B, G), respectively. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 67 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Figure 3-18. Configuration of General-Purpose Registers (a) Function name 16-bit processing 8-bit processing FFEFFH H Register bank 0 HL L FFEF8H D Register bank 1 DE E FFEF0H B BC Register bank 2 C FFEE8H A AX Register bank 3 X FFEE0H 15 0 7 0 (b) Absolute name 16-bit processing 8-bit processing FFEFFH R7 Register bank 0 RP3 R6 FFEF8H R5 Register bank 1 RP2 R4 FFEF0H R3 RP1 Register bank 2 R2 FFEE8H R1 RP0 Register bank 3 R0 FFEE0H 15 R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 0 7 0 68 RL78/F12 CHAPTER 3 CPU ARCHITECTURE 3.2.3 ES and CS registers The ES register is used for data access and the CS register is used to specify the higher address when a branch instruction is executed. The default value of the ES register after reset is 0FH, and that of the CS register is 00H. Figure 3-19. Configuration of ES and CS Registers ES CS R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 7 6 5 4 3 2 1 0 0 0 0 0 ES3 ES2 ES1 ES0 7 6 5 4 3 2 1 0 0 0 0 0 CS3 CP2 CP1 CP0 69 RL78/F12 CHAPTER 3 CPU ARCHITECTURE 3.2.4 Special function registers (SFRs) Unlike a general-purpose register, each SFR has a special function. SFRs are allocated to the FFF00H to FFFFFH area. SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type. Each manipulation bit unit can be specified as follows. • 1-bit manipulation Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address. • 8-bit manipulation Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. • 16-bit manipulation Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp). When specifying an address, describe an even address. Table 3-5 gives a list of the SFRs. The meanings of items in the table are as follows. • Symbol Symbol indicating the address of a special function register. It is a reserved word in the assembler, and is defined as an sfr variable using the #pragma sfr directive in the compiler. When using the assembler, debugger, and simulator, symbols can be written as an instruction operand. • R/W Indicates whether the corresponding SFR can be read or written. R/W: Read/write enable R: Read only W: Write only • Manipulable bit units “√” indicates the manipulable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible. • After reset Indicates each register status upon reset signal generation. Caution Do not access addresses to which extended SFRs are not assigned. Remark For extended SFRs (2nd SFRs), see 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 70 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (1/4) Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range After Reset 1-bit 8-bit 16-bit FFF00H Port register 0 P0 R/W √ √ − 00H FFF01H Port register 1 P1 R/W √ √ − 00H FFF02H Port register 2 P2 R/W √ √ − 00H FFF03H Port register 3 P3 R/W √ √ − 00H FFF04H Port register 4 P4 R/W √ √ − 00H FFF05H Port register 5 P5 R/W √ √ − 00H FFF06H Port register 6 P6 R/W √ √ − 00H FFF07H Port register 7 P7 R/W √ √ − 00H FFF0CH Port register 12 P12 R/W √ √ − Undefined FFF0DH Port register 13 P13 R/W √ √ − Undefined FFF0EH Port register 14 P14 R/W √ √ − 00H FFF10H Serial data register 00 TXD0/ SDR00 R/W SIO00 − √ √ 0000H − − − √ √ 0000H − − R/W − − √ 0000H FFF1AH Timer data register 01 TDR01L TDR01 R/W − √ √ 00H FFF1BH TDR01H − FFF11H FFF12H Serial data register 01 RXD0 SDR01 R/W − FFF13H FFF18H Timer data register 00 TDR00 FFF19H − √ FFF1EH 10-bit A/D conversion result register ADCR R − − √ 0000H FFF1FH ADCRH R − √ − 00H 8-bit A/D conversion result register 00H FFF20H Port mode register 0 PM0 R/W √ √ − FFH FFF21H Port mode register 1 PM1 R/W √ √ − FFH FFF22H Port mode register 2 PM2 R/W √ √ − FFH FFF23H Port mode register 3 PM3 R/W √ √ − FFH FFF24H Port mode register 4 PM4 R/W √ √ − FFH FFF25H Port mode register 5 PM5 R/W √ √ − FFH FFF26H Port mode register 6 PM6 R/W √ √ − FFH FFF27H Port mode register 7 PM7 R/W √ √ − FFH FFF2CH Port mode register 12 PM12 R/W √ √ − FFH FFF2EH Port mode register 14 PM14 R/W √ √ − FFH FFF30H A/D converter mode register 0 ADM0 R/W √ √ − 00H FFF31H Analog input channel specification register ADS R/W √ √ − FFF32H A/D converter mode register 1 ADM1 R/W √ √ − 00H FFF37H Key return mode register KRM R/W √ √ − 00H FFF38H External interrupt rising edge EGP0 R/W √ √ − 00H EGN0 R/W √ √ − 00H EGP1 R/W √ √ − 00H EGN1 R/W √ √ − 00H 00H enable register 0 FFF39H External interrupt falling edge enable register 0 FFF3AH External interrupt rising edge enable register 1 FFF3BH External interrupt falling edge enable register 1 R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 71 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (2/4) Address Special Function Register (SFR) Name FFF44H Serial data register 02 Symbol TXD1 R/W FFF46H Serial data register 03 After Reset 1-bit 8-bit 16-bit − √ √ 0000H − − − √ √ 0000H − − − √ √ 0000H − − − √ √ 0000H − − R/W − √ − 00H SDR02 R/W − FFF45H Manipulable Bit Range RXD1/ SDR03 R/W SIO11 − FFF47H FFF48H Serial data register 10 TXD2/ SDR10 R/W SIO20 − FFF49H FFF4AH Serial data register 11 RXD2/ SDR11 R/W SIO21 − FFF4BH FFF50H IICA shift register 0 IICA0 FFF51H IICA status register 0 IICS0 R √ √ − 00H FFF52H IICA flag register 0 IICF0 R/W √ √ − 00H FFF64H Timer data register 02 TDR02 R/W − − √ 0000H FFF66H Timer data register 03 TDR03L TDR03 R/W − √ √ 00H FFF67H TDR03H − √ FFF65H 00H TDR04 R/W − − √ 0000H TDR05 R/W − − √ 0000H TDR06 R/W − − √ 0000H TDR07 R/W − − √ 0000H ITMC R/W − − √ 0FFFH FFF92H Second count register SEC R/W − √ − 00H FFF93H Minute count register MIN R/W − √ − 00H FFF94H Hour count register HOUR R/W − √ − FFF68H Timer data register 04 FFF69H FFF6AH Timer data register 05 FFF6BH FFF6CH Timer data register 06 FFF6DH FFF6EH Timer data register 07 FFF6FH FFF90H Interval timer control register FFF91H 12H Note FFF95H Week count register WEEK R/W − √ − 00H FFF96H Day count register DAY R/W − √ − 01H FFF97H Month count register MONTH R/W − √ − 01H FFF98H Year count register YEAR R/W − √ − 00H FFF99H Watch error correction register SUBCUD R/W − √ − 00H FFF9AH Alarm minute register ALARMWM R/W − √ − 00H FFF9BH Alarm hour register ALARMWH R/W − √ − 12H FFF9CH Alarm week register ALARMWW R/W − √ − 00H FFF9DH Real-time clock control register RTCC0 R/W √ √ − 00H RTCC1 R/W √ √ − 00H 0 FFF9EH Real-time clock control register 1 Note The value of this register is 00H if the AMPM bit (bit 3 of real-time clock control register 0 (RTCC0)) is set to 1 after reset. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 72 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (3/4) Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range After Reset 1-bit 8-bit 16-bit CMC R/W − √ − 00H CSC R/W √ √ − C0H OSTC R √ √ − 00H OSTS R/W − √ − 07H FFFA4H System clock control register CKC R/W √ √ − 00H FFFA5H Clock output select register 0 CKS0 R/W √ √ − 00H FFFA6H Clock output select register 1 CKS1 R/W √ √ − 00H FFFA8H Reset control flag register RESF R − √ − Undefined FFFA9H Voltage detection register LVIM R/W √ √ − 00H FFFAAH Voltage detection level register LVIS R/W √ √ − 00H/01H/81H FFFA0H Clock operation mode control register FFFA1H Clock operation status control register FFFA2H Oscillation stabilization time counter status register FFFA3H Oscillation stabilization time select register Note 2 Note 3 Note 4 FFFABH Watchdog timer enable register WDTE R/W − √ − FFFACH CRC input register CRCIN R/W − √ − 00H FFFB0H DMA SFR address register 0 DSA0 R/W − √ − 00H FFFB1H DMA SFR address register 1 DSA1 R/W − √ − 00H FFFB2H DMA RAM address register 0L DRA0L DRA0 R/W − √ √ 00H FFFB3H DMA RAM address register 0H DRA0H R/W − √ FFFB4H DMA RAM address register 1L DRA1L DRA1 R/W − √ FFFB5H DMA RAM address register 1H DRA1H R/W − √ FFFB6H DMA byte count register 0L DBC0L DBC0 R/W − √ FFFB7H DMA byte count register 0H DBC0H R/W − √ FFFB8H DMA byte count register 1L DBC1L DBC1 R/W − √ FFFB9H DMA byte count register 1H DBC1H R/W − √ FFFBAH DMA mode control register 0 DMC0 R/W √ √ − 00H FFFBBH DMA mode control register 1 DMC1 R/W √ √ − 00H FFFBCH DMA operation control register 0 DRC0 R/W √ √ − 00H R/W √ √ − 00H R/W √ √ √ 00H R/W √ √ R/W √ √ R/W √ √ FFFBDH DMA operation control register 1 DRC1 FFFD0H Interrupt request flag register 2L IF2L IF2 FFFD1H Interrupt request flag register 2H IF2H FFFD4H Interrupt mask flag register 2L MK2L FFFD5H Interrupt mask flag register 2H MK2H MK2 Note 1 1A/9A 00H √ 00H 00H √ 00H 00H √ 00H 00H 00H √ FFH FFH Notes 1. The reset value of the RESF register varies depending on the reset source. 2. The reset value of the LVIM register varies depending on the reset source. 3. The reset value of the LVIS register varies depending on the reset source and the setting of the option byte. 4. The reset value of the WDTE register is determined by the setting of the option byte. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 73 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (4/4) Address Special Function Register (SFR) Name Symbol FFFD8H Priority specification flag register PR02L PR02 R/W Manipulable Bit Range 1-bit 8-bit 16-bit R/W √ √ √ R/W √ √ R/W √ √ R/W √ √ R/W √ √ R/W √ √ After Reset FFH 02L FFFD9H Priority specification flag register PR02H FFH 02H FFFDCH Priority specification flag register PR12L PR12 √ FFH 12L FFFDDH Priority specification flag register PR12H FFH 12H FFFE0H Interrupt request flag register 0L IF0L IF0 FFFE1H Interrupt request flag register 0H IF0H FFFE2H Interrupt request flag register 1L IF1L IF1 FFFE3H Interrupt request flag register 1H IF1H FFFE4H Interrupt mask flag register 0L MK0L FFFE5H Interrupt mask flag register 0H MK0H FFFE6H Interrupt mask flag register 1L MK1L FFFE7H Interrupt mask flag register 1H MK1H MK0 MK1 FFFE8H Priority specification flag register PR00L PR00 R/W √ √ R/W √ √ R/W √ √ R/W √ √ R/W √ √ R/W √ √ R/W √ √ R/W √ √ R/W √ √ R/W √ √ R/W √ √ R/W √ √ R/W √ √ R/W √ √ √ 00H 00H √ 00H 00H √ FFH FFH √ FFH FFH √ FFH 00L FFFE9H Priority specification flag register PR00H FFH 00H FFFEAH Priority specification flag register PR01L PR01 √ FFH 01L FFFEBH Priority specification flag register PR01H FFH 01H FFFECH Priority specification flag register PR10L PR10 √ FFH 10L FFFEDH Priority specification flag register PR10H FFH 10H FFFEEH Priority specification flag register PR11L PR11 √ FFH 11L FFFEFH Priority specification flag register PR11H FFH 11H FFFF0H Multiplication/division data register FFFF1H A (L) MDAL/MULA R/W − − √ 0000H FFFF2H Multiplication/division data register FFFF3H A (H) MDAH/MULB R/W − − √ 0000H FFFF4H Multiplication/division data register FFFF5H B (H) MDBH/MULOH R/W − − √ 0000H FFFF6H Multiplication/division data register FFFF7H B (L) MDBL/MULOL R/W − − √ 0000H √ √ − 00H FFFFEH Processor mode control register PMC R/W Remark For extended SFRs (2nd SFRs), see Table 3-6 Extended SFR (2nd SFR) List. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 74 RL78/F12 CHAPTER 3 CPU ARCHITECTURE 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) Unlike a general-purpose register, each extended SFR (2 nd SFR) has a special function. Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area. An instruction that accesses the extended SFR area, however, is 1 byte longer than an instruction that accesses the SFR area. Extended SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type. Each manipulation bit unit can be specified as follows. • 1-bit manipulation Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (!addr16.bit). This manipulation can also be specified with an address. • 8-bit manipulation Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (!addr16). This manipulation can also be specified with an address. • 16-bit manipulation Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (!addr16). When specifying an address, describe an even address. Table 3-6 gives a list of the extended SFRs. The meanings of items in the table are as follows. • Symbol Symbol indicating the address of an extended SFR. It is a reserved word in the assembler, and is defined as an sfr variable using the #pragma sfr directive in the compiler. When using the assembler, debugger, and simulator, symbols can be written as an instruction operand. • R/W Indicates whether the corresponding extended SFR can be read or written. R/W: Read/write enable R: Read only W: Write only • Manipulable bit units “√” indicates the manipulable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible. • After reset Indicates each register status upon reset signal generation. Caution Do not access addresses to which extended SFRs are not assigned. Remark For SFRs in the SFR area, see 3.2.4 Special function registers (SFRs). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 75 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (1/7) Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range After Reset 1-bit 8-bit 16-bit F0010H A/D converter mode register 2 ADM2 R/W √ √ − 00H F0011H Conversion result comparison upper limit setting register ADUL R/W − √ − FFH F0012H Conversion result comparison lower limit setting register ADLL R/W − √ − 00H F0013H A/D test register ADTES R/W − √ − 00H F0030H Pull-up resistor option register 0 PU0 R/W √ √ − 00H F0031H Pull-up resistor option register 1 PU1 R/W √ √ − 00H F0033H Pull-up resistor option register 3 PU3 R/W √ √ − 00H F0034H Pull-up resistor option register 4 PU4 R/W √ √ − 01H F0035H Pull-up resistor option register 5 PU5 R/W √ √ − 00H F0037H Pull-up resistor option register 7 PU7 R/W √ √ − 00H F003CH Pull-up resistor option register 12 PU12 R/W √ √ − 00H F003EH Pull-up resistor option register 14 PU14 R/W √ √ − 00H F0040H Port input mode register 0 PIM0 R/W √ √ − 00H F0041H Port input mode register 1 PIM1 R/W √ √ − 00H F0045H Port input mode register 5 PIM5 R/W √ √ − 00H F0050H Port output mode register 0 POM0 R/W √ √ − 00H F0051H Port output mode register 1 POM1 R/W √ √ − 00H F0055H Port output mode register 5 POM5 R/W √ √ − 00H F0057H Port output mode register 7 POM7 R/W √ √ − 00H F0060H Port mode control register 0 PMC0 R/W √ √ − FFH PMC12 R/W √ √ − FFH F006CH Port mode control register 12 F006EH Port mode control register 14 PMC14 R/W √ √ − FFH F0070H Noise filter enable register 0 NFEN0 R/W √ √ − 00H F0071H Noise filter enable register 1 NFEN1 R/W √ √ − 00H F0073H Input switch control register ISC R/W √ √ − 00H F0074H Timer input select register 0 TIS0 R/W − √ − 00H F0076H A/D port configuration register ADPC R/W − √ − 00H F0077H Peripheral I/O redirection register PIOR R/W − √ − 00H F0078H Invalid memory access detection control register IAWCTL R/W − √ − 00H F0090H Data flash control register DFLCTL R/W √ √ − 00H F00A0H On-chip high-speed oscillator trimming register HIOTRM R/W − √ − Note F00A8H On-chip high-speed oscillator divider setting register HOCODIV R/W − √ − Undefined F00ACH Temperature trimming register 0 TEMPCAL0 R − √ − Note F00ADH Temperature trimming register 1 TEMPCAL1 R − √ − Note F00AEH Temperature trimming register 2 TEMPCAL2 R − √ − Note F00AFH Temperature trimming register 3 TEMPCAL3 R − √ − Note Note This value varies depending on the products. Remark For SFRs in the SFR area, see Table 3-5 SFR List. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 76 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (2/7) Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range After Reset 1-bit 8-bit 16-bit F00E0H Multiplication/division data register C (L) MDCL R − − √ 0000H F00E2H Multiplication/division data register C (H) MDCH R − − √ 0000H F00E8H Multiplication/division control register MDUC R/W √ √ − 00H F00F0H Peripheral enable register 0 PER0 R/W √ √ − 00H F00F3H Operation speed mode control register OSMC R/W − √ − 00H R/W √ √ − 00H F00F5H RAM parity error control register RPECTL F00FEH BCD adjust result register F0100H SSR00L SSR00 Serial status register 01 SSR01L SSR01 Serial status register 02 SSR02L SSR02 Serial status register 03 SSR03L SSR03 √ − Undefined − √ √ 0000H − − − √ √ 0000H − − − √ √ 0000H − − − √ √ 0000H − − − √ √ 0000H − − − √ √ 0000H − − − √ √ 0000H − − − √ √ 0000H − − R R − F0105H F0106H − R − F0103H F0104H R − F0101H F0102H BCDADJ Serial status register 00 R − F0107H Serial flag clear trigger register 00 SIR00L SIR00 R/W F010AH Serial flag clear trigger register F010BH 01 SIR01L SIR01 R/W F010CH Serial flag clear trigger register F010DH 02 SIR02L SIR02 R/W F010EH Serial flag clear trigger register F010FH 03 SIR03L SIR03 R/W F0110H Serial mode register 00 SMR00 R/W − − √ 0020H Serial mode register 01 SMR01 R/W − − √ 0020H Serial mode register 02 SMR02 R/W − − √ 0020H Serial mode register 03 SMR03 R/W − − √ 0020H Serial communication operation setting register 00 SCR00 R/W − − √ 0087H F011AH Serial communication operation F011BH setting register 01 SCR01 R/W − − √ 0087H F011CH Serial communication operation F011DH setting register 02 SCR02 R/W − − √ 0087H F011EH Serial communication operation F011FH setting register 03 SCR03 R/W − − √ 0087H F0108H F0109H − − − − F0111H F0112H F0113H F0114H F0115H F0116H F0117H F0118H F0119H Remark For SFRs in the SFR area, see Table 3-5 SFR List. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 77 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (3/7) Address Special Function Register (SFR) Name Symbol SE0L F0121H Serial channel enable status register 0 F0122H Serial channel start register 0 SS0L F0120H Serial channel stop register 0 Serial clock select register 0 SS0 R/W 8-bit 16-bit √ √ √ 0000H − − √ √ √ 0000H − − √ √ √ 0000H − − − √ √ 0000H − − − ST0L ST0 SPS0L SPS0 Serial output register 0 After Reset 1-bit R/W R/W − F0127H F0128H R − F0125H F0126H SE0 Manipulable Bit Range − F0123H F0124H R/W SO0 R/W − − √ 0303H SOE0L SOE0 R/W √ √ √ 0000H − − − √ √ 0000H − − − √ √ 0000H − − − √ √ 0000H − − − √ √ 0000H − − − √ √ 0000H − − − √ √ 0000H − − F0129H F012AH Serial output enable register 0 − F012BH F0134H Serial output level register 0 SOL0L SOL0 R/W − F0135H F0138H Serial standby control register 0 SSC0L SSC0 F0140H Serial status register 10 SSR10L SSR10 Serial status register 11 SSR11L SSR11 R/W − − F0141H F0142H R R − F0143H Serial flag clear trigger register 10 SIR10L SIR10 R/W F014AH Serial flag clear trigger register F014BH 11 SIR11L SIR11 R/W F0148H F0149H − − Serial mode register 10 SMR10 R/W − − √ 0020H Serial mode register 11 SMR11 R/W − − √ 0020H Serial communication operation setting register 10 SCR10 R/W − − √ 0087H F015AH Serial communication operation F015BH setting register 11 SCR11 R/W − − √ 0087H SE1 R √ √ √ 0000H − − SS1 R/W √ √ √ 0000H − − √ √ √ 0000H − − − √ √ 0000H − − F0150H F0151H F0152H F0153H F0158H F0159H SE1L F0161H Serial channel enable status register 1 F0162H Serial channel start register 1 SS1L F0160H − F0163H F0164H Serial channel stop register 1 Serial clock select register 1 ST1 R/W SPS1L SPS1 R/W − F0167H F0168H ST1L − F0165H F0166H − Serial output register 1 SO1 R/W − − √ 0F0FH SOE1L SOE1 R/W √ √ √ 0000H − − F0169H F016AH Serial output enable register 1 − F016BH Remark For SFRs in the SFR area, see Table 3-5 SFR List. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 78 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (4/7) Address Special Function Register (SFR) Name Symbol R/W Serial output level register 1 SOL1L SOL1 R/W Timer counter register 00 TCR00 R Timer counter register 01 TCR01 Timer counter register 02 Manipulable Bit Range After Reset 1-bit 8-bit 16-bit − √ √ 0000H − − − − √ FFFFH R − − √ FFFFH TCR02 R − − √ FFFFH Timer counter register 03 TCR03 R − − √ FFFFH Timer counter register 04 TCR04 R − − √ FFFFH F018AH Timer counter register 05 TCR05 R − − √ FFFFH TCR06 R − − √ FFFFH TCR07 R − − √ FFFFH Timer mode register 00 TMR00 R/W − − √ 0000H Timer mode register 01 TMR01 R/W − − √ 0000H Timer mode register 02 TMR02 R/W − − √ 0000H Timer mode register 03 TMR03 R/W − − √ 0000H Timer mode register 04 TMR04 R/W − − √ 0000H F019AH Timer mode register 05 TMR05 R/W − − √ 0000H TMR06 R/W − − √ 0000H TMR07 R/W − − √ 0000H R − √ √ 0000H − − − √ √ 0000H − − F0174H − F0175H F0180H F0181H F0182H F0183H F0184H F0185H F0186H F0187H F0188H F0189H F018BH F018CH Timer counter register 06 F018DH F018EH Timer counter register 07 F018FH F0190H F0191H F0192H F0193H F0194H F0195H F0196H F0197H F0198H F0199H F019BH F019CH Timer mode register 06 F019DH F019EH Timer mode register 07 F019FH F01A0H Timer status register 00 F01A2H Timer status register 01 TSR01L TSR01 R − F01A3H Remark TSR00L TSR00 − F01A1H For SFRs in the SFR area, see Table 3-5 SFR List. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 79 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (5/7) Address Special Function Register (SFR) Name F01A4H Timer status register 02 Symbol R/W TSR02L TSR02 R Manipulable Bit Range 1-bit 8-bit 16-bit − √ √ 0000H − − − √ √ 0000H − − − √ √ 0000H − − − √ √ 0000H − − − √ √ 0000H − − − √ √ 0000H − − √ √ √ 0000H − − √ √ √ 0000H − − √ √ √ 0000H − F01A5H F01A6H Timer status register 03 TSR03L TSR03 R − F01A7H F01A8H Timer status register 04 TSR04L TSR04 R − F01A9H F01AAH Timer status register 05 TSR05L TSR05 R − F01ABH F01ACH Timer status register 06 TSR06L TSR06 R − F01ADH F01AEH Timer status register 07 TSR07L TSR07 R − F01AFH F01B0H Timer channel enable status F01B1H register 0 TE0L F01B2H Timer channel start register 0 TS0L TE0 R TS0 R/W TT0 R/W − − F01B3H F01B4H Timer channel stop register 0 TT0L − F01B5H F01B6H Timer clock select register 0 TPS0 After Reset − − R/W − − √ 0000H R/W − √ √ 0000H − − √ √ √ 0000H − − − √ √ 0000H − − − √ √ 0000H 00H F01B7H F01B8H Timer output register 0 TO0L TO0 − F01B9H F01BAH Timer output enable register 0 TOE0L TOE0 R/W − F01BBH F01BCH Timer output level register 0 TOL0L TOL0 R/W − F01BDH F01BEH Timer output mode register 0 TOM0L TOM0 R/W − F01BFH − − R/W √ √ − IICCTL01 R/W √ √ − 00H IICWL0 R/W − √ − FFH IICWH0 R/W − √ − FFH F0230H IICA control register 00 IICCTL00 F0231H IICA control register 01 F0232H IICA low-level width setting register 0 F0233H IICA high-level width setting register 0 F0234H Slave address register 0 SVA0 R/W − √ − 00H F02F0H Flash memory CRC control register CRC0CTL R/W √ √ − 00H F02F2H Flash memory CRC operation result register PGCRCL R/W − − √ 0000H F02FAH CRC data register CRCD R/W − − √ 0000H Remark For SFRs in the SFR area, see Table 3-5 SFR List. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 80 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (6/7) Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range After Reset 1-bit 8-bit 16-bit Peripheral enable register PERX R/W √ √ − 00H F0501H Peripheral clock select register PCKSEL R/W √ √ − 00H F0504H Port mode register X0 PMX0 R/W √ √ − 01H F0505H Port mode register X1 PMX1 R/W √ √ − 01H F0506H Port mode register X2 PMX2 R/W √ √ − 01H F0507H Port mode register X3 PMX3 R/W √ √ − 01H F0508H Port mode register X4 PMX4 R/W √ √ − 01H F0509H Port input enable register X PIEN R/W √ √ − 00H F050AH Noise filter enable register X NFENX R/W √ √ − 00H F0520H LIN-UART0 control register 0 UF0CTL0 R/W √ √ − 10H F0521H LIN-UART0 option register 0 UF0OPT0 R/W √ √ − 14H F0522H LIN-UART0 control register 1 UF0CTL1 R/W − − √ 0FFFH F0524H LIN-UART0 option register 1 UF0OPT1 R/W √ √ − 00H R/W √ √ − 00H R − − √ 0000H R/W − − √ 0000H UF0WTXB W − √ − 00H F052BH LIN-UART0 wait transmit data register UF0WTX W − − √ 0000H F052EH LIN-UART0 ID setting register UF0ID R/W − √ − 00H F0500H F0525H LIN-UART0 option register 2 UF0OPT2 F0526H LIN-UART0 status register UF0STR F0527H F0528H LIN-UART0 status clear register UF0STC F0529H F052AH LIN-UART0 8-bit wait transmit data register F052FH LIN-UART0 buffer register 0 UF0BUF0 R/W − √ − 00H F0530H LIN-UART0 buffer register 1 UF0BUF1 R/W − √ − 00H F0531H LIN-UART0 buffer register 2 UF0BUF2 R/W − √ − 00H F0532H LIN-UART0 buffer register 3 UF0BUF3 R/W − √ − 00H F0533H LIN-UART0 buffer register 4 UF0BUF4 R/W − √ − 00H F0534H LIN-UART0 buffer register 5 UF0BUF5 R/W − √ − 00H F0535H LIN-UART0 buffer register 6 UF0BUF6 R/W − √ − 00H F0536H LIN-UART0 buffer register 7 UF0BUF7 R/W − √ − 00H F0537H LIN-UART0 buffer register 8 UF0BUF8 R/W − √ − 00H F0538H LIN-UART0 buffer control register UF0BUCTL R/W − − √ 0000H F0539H F0540H Serial data register S0 SDRS0L SDRS0 R/W − √ √ 0000H − − − √ √ 0000H − − − √ √ 00H − − − √ − − − F0541H F0542H Serial data register S1 − F0543H F0548H F0549H F054AH LIN-UART0 8-bit transmit UF0TXB UF0TX R/W data register LIN-UART0 transmit data register − LIN-UART0 8-bit receive UF0RXB UF0RX data register F054BH LIN-UART0 receive data register Remark SDRS1L SDRS1 R/W R − 0000H √ 00H 0000H For SFRs in the SFR area, see Table 3-5 SFR List. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 81 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (7/7) Address Special Function Register (SFR) Name F0550H Symbol R/W Serial status register S0 SSRS0L SSRS0 R Serial status register S1 SSRS1L SSRS1 8-bit 16-bit − √ √ 0000H − − − √ √ 0000H − − − √ √ 0000H − − − √ √ 0000H − − R − F0553H After Reset 1-bit − F0551H F0552H Manipulable Bit Range Serial flag clear trigger register S0 SIRS0L SIRS0 R/W Serial flag clear trigger register S1 SIRS1L SIRS1 R/W F0557H F0558H Serial mode register S0 SMRS0 R/W − − √ 0020H F055AH Serial mode register S1 SMRS1 R/W − − √ 0020H F055CH Serial communication operation F055DH setting register S0 SCRS0 R/W − − √ 0087H F055EH Serial communication operation F055FH setting register S1 SCRS0 R/W − − √ 0087H SES R √ √ √ 0000H − − SSS R/W √ 0000H √ 0000H √ 0000H F0554H F0555H F0556H − − F0559H F055BH Serial channel enable status register S SESL F0561H F0562H Serial channel start register S SSSL F0560H − F0563H F0564H Serial channel stop register S Serial clock select register S STS R/W Serial output register S √ √ − − √ √ − − − √ − − R/W − − √ 0303H SOESL SOES R/W √ √ √ 0000H − − − √ √ 0000H SPSSL SPSS R/W − F0567H F0568H STSL − F0565H F0566H − SOS F0569H F056AH Serial output enable register S − F056BH Serial output level register S SOLSL SOLS − − F0580H WUTM control register WUTMCTL R/W √ √ − 00H F0582H WUTM compare register WUTMCMP R/W − − √ 0000H F0570H R/W − F0571H F0583H Remark For SFRs in the SFR area, see Table 3-5 SFR List. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 82 RL78/F12 CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing 3.3.1 Relative addressing [Function] Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the instruction word (signed complement data: −128 to +127 or −32768 to +32767) to the program counter (PC)’s value (the start address of the next instruction), and specifies the program address to be used as the branch destination. Relative addressing is applied only to branch instructions. Figure 3-20. Outline of Relative Addressing PC OP code DISPLACE 8/16 bits 3.3.2 Immediate addressing [Function] Immediate addressing stores immediate data of the instruction word in the program counter, and specifies the program address to be used as the branch destination. For immediate addressing, CALL !!addr20 or BR !!addr20 is used to specify 20-bit addresses and CALL !addr16 or BR !addr16 is used to specify 16-bit addresses. 0000 is set to the higher 4 bits when specifying 16-bit addresses. Figure 3-21. Example of CALL !!addr20/BR !!addr20 PC OP code Low Addr. High Addr. Seg Addr. Figure 3-22. Example of CALL !addr16/BR !addr16 PC PCS PCH PCL OP code 0000 Low Addr. High Addr. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 83 RL78/F12 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit immediate data in the instruction word, stores the contents at that table address and the next address in the program counter (PC) as 16-bit data, and specifies the program address. Table indirect addressing is applied only for CALLT instructions. In the RL78 microcontrollers, branching is enabled only to the 64 KB space from 00000H to 0FFFFH. Figure 3-23. Outline of Table Indirect Addressing OP code Low Addr. 00000000 10 0 High Addr. Table address Memory 0000 PC R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 PCS PCH PCL 84 RL78/F12 CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register direct addressing [Function] Register direct addressing stores in the program counter (PC) the contents of a general-purpose register pair (AX/BC/DE/HL) and CS register of the current register bank specified with the instruction word as 20-bit data, and specifies the program address. Register direct addressing can be applied only to the CALL AX, BC, DE, HL, and BR AX instructions. Figure 3-24. Outline of Register Direct Addressing OP code rp CS PC R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 PCS PCH PCL 85 RL78/F12 CHAPTER 3 CPU ARCHITECTURE 3.4 Addressing for Processing Data Addresses 3.4.1 Implied addressing [Function] Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the instruction word, without using any register specification field in the instruction word. [Operand format] Because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. Implied addressing can be applied only to MULU X. Figure 3-25. Outline of Implied Addressing OP code A register Memory 3.4.2 Register addressing [Function] Register addressing accesses a general-purpose register as an operand. The instruction word of 3-bit long is used to select an 8-bit register and the instruction word of 2-bit long is used to select a 16-bit register. [Operand format] Identifier Description r X, A, C, B, E, D, L, H rp AX, BC, DE, HL Figure 3-26. Outline of Register Addressing OP code Register Memory R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 86 RL78/F12 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target address. [Operand format] Identifier Description ADDR16 Label or 16-bit immediate data (only the space from F0000H to FFFFFH is specifiable) ES: ADDR16 Label or 16-bit immediate data (higher 4-bit addresses are specified by the ES register) Figure 3-27. Example of ADDR16 FFFFFH OP code Low Addr. Target memory High Addr. F0000H Memory Figure 3-28. Example of ES:ADDR16 FFFFFH ES OP code Low Addr. Target memory High Addr. 00000H Memory R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 87 RL78/F12 CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFE20H to FFF1FH. [Operand format] Identifier SADDR Description Label, FFE20H to FFF1FH immediate data, or 0FE20H to 0FF1FH immediate data (only the space from FFE20H to FFF1FH is specifiable) SADDRP Label, FFE20H to FFF1FH immediate data, or 0FE20H to 0FF1FH immediate data (even address only) (only the space from FFE20H to FFF1FH is specifiable) Figure 3-29. Outline of Short Direct Addressing OP code FFF1FH saddr saddr FFE20H Memory Remark SADDR and SADDRP are used to describe the values of addresses FE20H to FF1FH with 16-bit immediate data (higher 4 bits of actual address are omitted), and the values of addresses FFE20H to FFF1FH with 20bit immediate data. Regardless of whether SADDR or SADDRP is used, addresses within the space from FFE20H to FFF1FH are specified for the memory. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 88 RL78/F12 CHAPTER 3 CPU ARCHITECTURE 3.4.5 SFR addressing [Function] SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFF00H to FFFFFH. [Operand format] Identifier SFR SFRP Description SFR name 16-bit-manipulatable SFR name (even address only) Figure 3-30. Outline of SFR Addressing FFFFFH OP code SFR FFF00H SFR Memory R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 89 RL78/F12 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register indirect addressing directly specifies the target addresses using the contents of the register pair specified with the instruction word as an operand address. [Operand format] Identifier Description − [DE], [HL] (only the space from F0000H to FFFFFH is specifiable) − ES:[DE], ES:[HL] (higher 4-bit addresses are specified by the ES register) Figure 3-31. Example of [DE], [HL] FFFFFH OP code rp Target memory F0000H Memory Figure 3-32. Example of ES:[DE], ES:[HL] FFFFFH ES OP code rp Target memory 00000H Memory R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 90 RL78/F12 CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] Based addressing uses the contents of a register pair specified with the instruction word as a base address, and 8bit immediate data or 16-bit immediate data as offset data. The sum of these values is used to specify the target address. [Operand format] Identifier Description − [HL + byte], [DE + byte], [SP + byte] (only the space from F0000H to FFFFFH is specifiable) − word[B], word[C] (only the space from F0000H to FFFFFH is specifiable) − word[BC] (only the space from F0000H to FFFFFH is specifiable) − ES:[HL + byte], ES:[DE + byte] (higher 4-bit addresses are specified by the ES register) − ES:word[B], ES:word[C] (higher 4-bit addresses are specified by the ES register) − ES:word[BC] (higher 4-bit addresses are specified by the ES register) Figure 3-33. Example of [SP+byte] FFFFFH SP Target memory F0000H OP code byte Memory R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 91 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Figure 3-34. Example of [HL + byte], [DE + byte] FFFFFH rp (HL/DE) Target memory F0000H OP code byte Memory Figure 3-35. Example of word[B], word[C] FFFFFH r (B/C) Target memory F0000H OP code Low Addr. High Addr. Memory Figure 3-36. Example of word[BC] FFFFFH rp (BC) Target memory F0000H OP code Low Addr. High Addr. Memory R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 92 RL78/F12 CHAPTER 3 CPU ARCHITECTURE Figure 3-37. Example of ES:[HL + byte], ES:[DE + byte] FFFFFH ES rp (HL/DE) Target memory OP code 00000H byte Memory Figure 3-38. Example of ES:word[B], ES:word[C] FFFFFH ES r (B/C) Target memory OP code 00000H Low Addr. Memory High Addr. Figure 3-39. Example of ES:word[BC] FFFFFH ES rp (BC) Target memory OP code 00000H Low Addr. Memory High Addr. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 93 RL78/F12 CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] Based indexed addressing uses the contents of a register pair specified with the instruction word as the base address, and the content of the B register or C register similarly specified with the instruction word as offset address. The sum of these values is used to specify the target address. [Operand format] Identifier Description − [HL+B], [HL+C] (only the space from F0000H to FFFFFH is specifiable) − ES:[HL+B], ES:[HL+C] (higher 4-bit addresses are specified by the ES register) Figure 3-40. Example of [HL+B], [HL+C] FFFFFH OP code rp (HL) Target memory F0000H r (B/C) Memory Figure 3-41. Example of ES:[HL+B], ES:[HL+C] FFFFFH OP code ES rp (HL) Target memory 00000H r (B/C) R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 Memory 94 RL78/F12 CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request. Stack addressing is applied only to the internal RAM area. [Operand format] Identifier − Description PUSH AX/BC/DE/HL POP AX/BC/DE/HL CALL/CALLT RET BRK RETB (Interrupt request generated) RETI R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 95 RL78/F12 CHAPTER 4 PORT FUNCTIONS CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The RL78/F12 microcontrollers are provided with digital I/O ports, which enable variety of control operations. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, see CHAPTER 2 PIN FUNCTIONS. 4.2 Port Configuration Ports include the following hardware. Table 4-1. Port Configuration Item Control registers Configuration Port mode registers (PM0 to PM7, PM12, PM14, PMX0 to PMX4) Port registers (P0 to P7, P12-P14) Pull-up resistor option registers (PU0, PU1, PU3 to PU5, PU7, PU12, PU14) Port input mode registers (PIM0, PIM1, PIM5) Port output mode registers (POM0, POM1, POM5, POM7) Port mode control registers (PMC0, PMC12, PMC14) A/D port configuration register (ADPC) Peripheral I/O redirection register (PIOR) Port input enable register (PIEN) • 20-pin products Port Total: 16 (CMOS I/O: 13, CMOS input: 3) • 30-pin products Total: 26 (CMOS I/O: 21, CMOS input: 3, N-ch open drain I/O: 2) • 32-pin products Total: 28 (CMOS I/O: 22, CMOS input: 3, N-ch open drain I/O: 3) • 48-pin products Total: 44 (CMOS I/O: 34, CMOS input: 5, CMOS output: 1, N-ch open drain I/O: 4) • 64-pin products Total: 58 (CMOS I/O: 48, CMOS input: 5, CMOS output: 1, N-ch open drain I/O: 4) Pull-up resistor • 20-pin products Total: 10 • 30-pin products Total: 17 • 32-pin products Total: 18 • 48-pin products Total: 26 • 64-pin products Total: 40 Caution Most of the following descriptions in this chapter use the 64-pin products with the peripheral I/O redirection register (PIOR) being set to 00H as an example. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 96 RL78/F12 CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P06 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0). Input to the P01, P03, P04 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using port input mode register 0 (PIM0). Output from the P00, P02, P03 pins can be specified as N-ch open-drain output (VDD tolerance/EVDD tolerance) in 1-bit units using port output mode register 0 (POM0). Input to the P00 to P03 pinsNote can be specified as analog input or digital input in 1-bit units, using port mode control register 0 (PMC0). This port can also be used for timer I/O, A/D converter analog input, serial interface data I/O, clock I/O. In 20- to 32-pin products, reset signal generation sets port 0 to analog input. In 48-pin products, reset signal generation sets port 0 to input mode. In 64-pin products, reset signal generation sets port 0 to P00, P01, P04 to P06 to analog input and P02/ANI17 and P03/ANI16 to analog input. For settings of the registers when using port 0, refer to Table 4-2. Note In 30- and 32-pin products: P00 and P01 In 20-pin products: P00 R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 97 RL78/F12 CHAPTER 4 PORT FUNCTIONS Table 4-2. Register Settings When Using Port 0 Pins Name P00 P03 P06 PMC0.x Note2 Note2 Note2 Note2 0 0 0 × CMOS output 0 1 0 × N-ch O.D. output – 0 × CMOS input 0 × 1 0 1 1 0 × Input 1 – Output Input Note2 × – Output Input Remarks 0 Output Input Alternate Function Setting When Using × 1 0 × 0 0 0 0 0 1 0 1 0 × 0 1 1 × 0 0 × 0 0 0 × 1 0 1 0 × – 1 1 × 0 × 0 0 × 1 Input 1 – – Output 0 Input 1 Output 0 Output P05 POM0.x Pin as Port Input Output P04 PIM0.x I/O Note1 P01 P02 PM0.x TO00 output = 0 – SO10/TxD1 output = 1 – Note4 CMOS output N-ch O.D. output × CMOS input TTL input SDA10 output = 1 Note4 CMOS output N-ch O.D. output × CMOS input TTL input SCK10/SCL10 output = 1 Note4 CMOS output N-ch O.D. output – × TO05 output = 0 – TTL input Note3 – Note3 × TO06 output = 0 Note3 Important: To use the port 0 as a general-purpose port, set the alternate pin function output to the level indicated by the Alternate Function Setting When Using Pin as Port. Notes 1. 30-, 32-, 48-, or 64-pin products only 2. 64-pin products only 3. To use P02/ANI17/SO10/TxD1, P03/ANI16/SI10/RxD1/SDA10, P04/SCK10/SCL10 as a general-purpose port, set serial channel enable status register 0 (SE0), serial output register 0 (SO0) and serial output enable register 0 (SOE0) to the default status. Clear port output mode register 0 (POM0) to 00H. 4. To use P00/TO00, P05/TI05/TO05, P06/TI06/TO06 as a general-purpose port, set bits 0, 5, and 6 (TO0.0, TO0.5, and TO0.6) of timer output register 0 (TO0) and bits 0, 5, and 6 (TOE0.0, TOE0.5, and TOE0.6) of timer output enable register 0 (TOE0) to “0”, which is the same as their default status setting. Remarks x: don’t care PM0×: Port mode register 0 PIM0×: Port input mode register 0 POM0×: Port output mode register 0 PMC0×: Port mode control register 0 R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 98 RL78/F12 CHAPTER 4 PORT FUNCTIONS For example, figures 4-1 to 4-6 show block diagrams of port 0 for 64-pin products. Figure 4-1. Block Diagram of P00 EVDD WRPU PU0 PU0.0 P-ch Alternate function Selector Internal bus RD WRPORT P0 Output latch (P0.0) P00/TI00 WRPOM POM0 POM0.0 WRPM PM0 PM0.0 P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 POM0: Port output mode register 0 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 99 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-2. Block Diagram of P01 WRPIM PIM0 PIM0.1 EVDD WRPU PU0 Internal bus PU0.1 P-ch CMOS Selector RD TTL WRPORT P0 Output latch (P0.1) P01/TO00 WRPM PM0 PM0.1 Alternate function P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 PIM0: Port input mode register 0 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 100 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P02 EVDD WRPU PU0 PU0.2 P-ch WRPMC PMC0 PMC0.2 Selector Internal bus RD WRPORT P0 Output latch (P0.2) P02/SO10/TxD1/ANI17 WRPOM POM0 POM0.2 WRPM PM0 PM0.2 Alternate function A/D converter P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 POM0: Port output mode register 0 PMC0: Port mode control register 0 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 101 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P03 WRPIM PIM0 PIM0.3 EVDD WRPU PU0 PU0.3 P-ch WRPMC PMC0 PMC0.3 CMOS RD Selector Internal bus Alternate function TTL WRPORT P0 Output latch (P0.3) P03/SI10/RxD1/ SDA10/ANI16 WRPOM POM0 POM0.3 WRPM PM0 PM0.3 Alternate function A/D converter P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 PIM0: Port input mode register 0 POM0: Port output mode register 0 PMC0: Port mode control register 0 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 102 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P04 WRPIM PIM0 PIM0.4 EVDD WRPU PU0 PU0.4 P-ch Alternate function CMOS Selector Internal bus RD TTL WRPORT P0 Output latch (P0.4) P04/SCK10/SCL10 WRPOM POM0 POM0.4 WRPM PM0 PM0.4 Alternate function P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 PIM0: Port input mode register 0 POM0: Port output mode register 0 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 103 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P05 and P06 EVDD WRPU PU0 PU0.5, PU0.6 P-ch Alternate function Selector Internal bus RD WRPORT P0 Output latch (P0.5, P0.6) P05/TI05/TO05, P06/TI06/TO06 WRPM PM0 PM0.5, PM0.6 Alternate function P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 104 RL78/F12 CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 Port 1 is an I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1). Input to the P13 to P17 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using port input mode register 1 (PIM1). Output from the P10 to P15 and P17 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using port output mode register 1 (POM1). This port can also be used for serial interface data I/O, clock I/O, programming UART I/O, timer I/O, and external interrupt request input. Reset signal generation sets port 1 to input mode. For settings of the registers when using port 1, refer to Table 4-3. Table 4-3. Register Settings When Using Port 1 PM1.x PIM1.x Input 1 – × × Output 0 0 SCK00/SCL00 output = 1, (TO07 output = 0) 0 1 Pins Name P10 P11 P12 P13 P16 P17 Remarks × 0 0 0 1 SDA00 output = 1 (TO06 output = 0) 1 Output – CMOS output N-ch O.D. output × Input CMOS output N-ch O.D. output Input 1 × × Output 0 0 0 1 SO00/TxD0 output = 1, (TO05 output = 0) N-ch O.D. output – CMOS output 1 0 × × CMOS input 1 1 × × TTL input 0 × 0 CMOS output 0 × 1 TxD2/SO20 output = 1, (TO04 output = 0, SDAA0 output = 0) 1 0 × × CMOS input 1 1 × × TTL input 0 × 0 0 × 1 SDA20 output = 1 (TO03 output = 0, SCLA0 output = 0) N-ch O.D. output Input 1 0 × × CMOS input 1 1 × × TTL input Output 0 × 0 CMOS output 0 × 1 SCK20/SCL20 output = 1 (TO02 output = 0) N-ch O.D. output 1 0 – × CMOS input 1 1 × TTL input Input Input Output P15 Alternate Function Setting When Using Pin as Port I/O Output P14 POM1.x Input N-ch O.D. output CMOS output Output 0 × 0 TO01 output = 0 Input 1 0 × × CMOS input 1 1 × × TTL input 0 × 0 0 × 1 TO02 output = 0 (SO00/TxD0 output = 1) N-ch O.D. output Output CMOS output Important To use the port 1 as a general-purpose port, set the alternate pin function output to the level indicated by the Alternate Function Setting When Using Pin as Port. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 105 RL78/F12 CHAPTER 4 PORT FUNCTIONS Note. To use SCKS0 or SOS0/TxDS0 as serial data output or serial clock output, set a bit in the corresponding port mode register (PMxx) for each port to “1”. And, set PMX0 and PMX1 registers to “0”. Cautions 1. P10/SCK00/SCKS0/SCL00, P11/SI00/RxD0/SIS0/RxDS0/SDA00, P12/SO00/TxD0/SOS0/TxDS0, P13/TxD2/SO20, P14/RxD2/SI20/SDA20, or P15/SCK20/SCL20 as a general-purpose port, set serial channel enable status register m (SEm), serial output register m (SOm) and serial output enable register m (SOEm) to the default status (m = 0, 1). Clear port output mode register 1 (POM1) to 00H. 2. To use P16/TI01/TO01 or P17/TI02/TO02 as a general-purpose port, set bits 1 and 2 (TO0.1, TO0.2) of timer output register 0 (TO0) and bits 1 and 2 (TOE0.1, TOE0.2) of timer output enable register 0 (TOE0) to “0”, which is the same as their default status setting. 3. If P10 to P15 are used as general-purpose ports and PIOR0 is set to 1, use the corresponding bits in bits 2 to 7 (TO02 to TO07) of timer output register 0 (TO0) and bits 2 to 7 (TOE02 to TOE07) of timer output enable register 0 with “0”, which is the same as their initial setting. 4. If P16, P17 are used as general-purpose port and PIOR1 is set to 1, use serial channel enable status register 0 (SE0), serial output register 0 (SO0) and serial output enable register 0 (SOE0) with the same setting as the initial status. Remark The descriptions in parentheses indicate the case where PIORx = 1. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 106 RL78/F12 CHAPTER 4 PORT FUNCTIONS For example, figures 4-7 to 4-14 show block diagrams of port 1 for 64-pin products. Figure 4-7. Block Diagram of P10 EVDD WRPU PU1 PU1.0 P-ch Alternate function Selector RD WRPORT P1 Output latch (P1.0) P10/SCK00/SCKS0/SCL00 Internal bus WRPOM POM1 POM1.0 WRPM PM1 PM1.0 Alternate function SCKS0 SCKS0 WRPMX PMX0 PMX0 P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 PMX0: Port mode register X0 POM1: Port output mode register 1 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 107 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P11 EVDD WRPU PU1 PU1.1 P-ch Alternate function Selector RD Internal bus WRPORT P1 Output latch (P1.1) WRPOM P11/SI00/RxD0/ SIS0/RxDS0/ TOOLRxD/SDA00 POM1 POM1.1 WRPM PM1 PM1.1 Alternate function SIS0/RxDS0 P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 POM1: Port output mode register 1 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 108 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P12 EVDD WRPU PU1 PU1.2 P-ch Selector RD WRPORT P1 Internal bus Output latch (P1.2) WRPOM P12/SO00/TxD0/ SOS0/TxDS0/TOOLTxD POM1 POM1.2 WRPM PM1 PM1.2 Alternate function SOS0/TxDS0 WRPMX PMX1 PMX1 P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 PMX1: Port mode register X1 POM1: Port output mode register 1 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 109 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P13 WRPIM PIM1 PIM1.3 EVDD WRPU PU1 PU1.3 P-ch CMOS Selector Internal bus RD TTL WRPORT P1 Output latch (P1.3) P13/TxD2/SO20 WRPOM POM1 POM1.3 WRPM PM1 PM1.3 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 PIM1: Port input mode register 1 POM1: Port output mode register 1 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 110 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of P14 WRPIM PIM1 PIM1.4 EVDD WRPU PU1 PU1.4 P-ch Alternate function CMOS Selector Internal bus RD TTL WRPORT P1 Output latch (P1.4) P14/SI20/RxD2/SDA20 WRPOM POM1 POM1.4 WRPM PM1 PM1.4 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 PIM1: Port input mode register 1 POM1: Port output mode register 1 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 111 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of P15 WRPIM PIM1 PIM1.5 EVDD WRPU PU1 PU1.5 P-ch Alternate function CMOS Selector Internal bus RD TTL WRPORT P1 Output latch (P1.5) P15/SCK20/SCL20 WRPOM POM1 POM1.5 WRPM PM1 PM1.5 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 PIM1: Port input mode register 1 POM1: Port output mode register 1 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 112 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P16 WRPIM PIM1 PIM1.6 EVDD WRPU PU1 PU1.6 P-ch Alternate function Selector Internal bus CMOS RD TTL WRPORT P1 Output latch (P1.6) P16/TI01/TO01/INTP5 WRPM PM1 PM1.6 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 PIM1: Port input mode register 1 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 113 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of P17 WRPIM PIM1 PIM1.7 EVDD WRPU PU1 PU1.7 P-ch Alternate function CMOS Selector Internal bus RD TTL WRPORT P1 Output latch (P1.7) P17/TI02/TO02 WRPOM POM1 POM1.7 WRPM PM1 PM1.7 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 PIM1: Port input mode register 1 POM1: Port output mode register 1 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 114 RL78/F12 CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 Port 2 is an I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (PM2). This port can also be used for A/D converter analog input and reference voltage input. To use P20/ANI0 to P27/ANI7 as digital input pins, set them in the digital I/O mode by using the A/D port configuration register (ADPC) and in the input mode by using the PM2 register. Use these pins starting from the upper bit. To use P20/ANI0 to P27/ANI7 as digital output pins, set them in the digital I/O mode by using the ADPC register and in the output mode by using the PM2 register. To use P20/ANI0 to P27/ANI7 as analog input pins, set them in the analog input mode by using the A/D port configuration register (ADPC) and in the input mode by using the PM2 register. Use these pins starting from the lower bit. Table 4-4. Setting Functions of P20/ANI0 to P27/ANI7 Pins ADPC Register Digital I/O selection Analog input selection PM2 Register ADS Register P20/ANI0 to P27/ANI7 Pins Input mode − Digital input Output mode − Digital output Input mode Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Output mode Selects ANI. Setting prohibited Does not select ANI. All P20/ANI0 to P27/ANI7 are set in the analog input mode when the reset signal is generated. Figure 4-15 shows a block diagram of port 2. For settings of the registers when using port 2, refer to Table 4-5. Table 4-5. Register Settings When Using Port 2 PM2.× Pins Name ADPC Alternate Function Remarks Setting When Using Pin I/O as Port P2n Input 1 01 to n+1H Output 0 01 to n+1H – Use these pins as a port from the upper bit. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 115 RL78/F12 CHAPTER 4 PORT FUNCTIONS For example, figure 4-15 shows a block diagram of port 2 for 64-pin products. Figure 4-15. Block Diagram of P20 to P27 WRADPC ADPC 0 : Analog input 1 : Digital I/O ADPC.3 to ADPC.0 Selector Internal bus RD WRPORT P2 P20/ANI0/AVREFP, P21/ANI1/AVREFM, P22/ANI2-P27/ANI7 Output latch (P2.0 to P2.7) WRPM PM2 PM2.0 to PM2.7 A/D converter P2: Port register 2 PM2: Port mode register 2 ADPC: A/D port configuration register RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 116 RL78/F12 CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 Port 3 is an I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When the P30, P31 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (PU3). This port can also be used for external interrupt request input, serial interface clock I/O, timer I/O, and real time clock 1 Hz output. Reset signal generation sets port 3 to input mode. Figures 4-16 and 4-17 show block diagrams of port 3. For settings of the registers when using port 3, refer to Table 4-6. Table 4-6. Register Settings When Using Port 3 PM3.x Pins Alternate Function Setting When Using Remarks Pin as Port Name I/O P30 Input 1 Output 0 × SCK11/SCL11 output = 1 Note1 or Note2 RTC1HZ output = 0 P31 Input 1 Output 0 × TO03 output = 0 Note3 (PCLBUZ0 output = 0) Note3, Note4 Important To use the port 3 as a general-purpose port, set the alternate pin function output to the level indicated by the Alternate Function Setting When Using Pin as Port. Cautions 1. P30/RTC1HZ/INTP3/SCK11/SCL11 as a general-purpose port, set serial channel enable status register 0 (SE0), serial output register 0 (SO0) and serial output enable register 0 (SOE0) to the default status. 2. To use P31/TI03/TO03/INTP4 as a general-purpose port, set bit 3 (TO0.3) of timer output register 0 (TO0) and bit 3 (TOE0.3) of timer output enable register 0 (TOE0) to “0”, which is the same as their default status setting. 3. To use P31/TI03/TO03/INTP4/PCLBUZ0 as a general-purpose port in 20- to 32-pin products, set bit 7 of the clock output select register 0 (CKS0) to “0”, which is the same as their default status setting. 4. To use P31 as a general-purpose port, do not set PIOR3 set to 1. Remark The descriptions in parentheses indicate the case where PIORx = 1. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 117 RL78/F12 CHAPTER 4 PORT FUNCTIONS For example, figures 4-16 and 4-17 show block diagrams of port 3 for 64-pin products. Figure 4-16. Block Diagram of P30 EVDD WRPU PU3 PU3.0 P-ch Alternate function Selector Internal bus RD WRPORT P3 Output latch (P3.0) P30/RTC1HZ/INTP3/ SCK11/SCL11 WRPM PM3 PM3.0 Alternate function Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 118 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of P31 EVDD WRPU PU3 PU3.1 P-ch Alternate function Selector Internal bus RD WRPORT P3 Output latch (P3.1) P31/TI03/TO03/INTP4/(PCLBUZ0) WRPM PM3 PM3.1 Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 119 RL78/F12 CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 4 Port 4 is an I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). When the P40 to P43 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 4 (PU4). This port can also be used for data I/O for a flash memory programmer/debugger, and timer I/O. Reset signal generation sets port 4 to input mode. Figures 4-18 to 4-20 show block diagrams of port 4. For settings of the registers when using port 4, refer to Table 4-7. Table 4-7. Register Settings When Using Port 4 PM4.x Pins Alternate Function Setting When Using Name I/O P40 Input 1 × Output 0 × Input 1 × Output 0 TO07 output = 0 Input 1 × Output 0 TO04 output = 0 Input 1 × Output 0 × P41 P42 P43 Remarks Pin as Port Important To use the port 4 as a general-purpose port, set the alternate pin function output to the level indicated by the Alternate Function Setting When Using Pin as Port. Cautions 1. When a tool is connected, the P40 pin cannot be used as a port pin. 2. To use P41/TI07/TO07, P42/TI04/TO04 as a general-purpose port, set bit 4 (TO0.4), bit 7 (TO0.7) of timer output register 0 (TO0) and bit 4 (TOE0.4), bit 7 (TOE0.7) of timer output enable register 0 (TOE0) to “0”, which is the same as their default status setting. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 120 RL78/F12 CHAPTER 4 PORT FUNCTIONS For example, figures 4-18 to 4-20 show block diagrams of port 4 for 64-pin products. Figure 4-18. Block Diagram of P40 EVDD WRPU PU4 PU4.0 P-ch Alternate function Selector WRPORT P4 Output latch (P4.0) WRPM Selector Internal bus RD P40/TOOL0 PM4 PM4.0 Alternate function P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 121 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of P41 and P42 EVDD WRPU PU4 PU4.1, PU4.2 P-ch Alternate function Selector Internal bus RD WRPORT P4 Output latch (P4.1, P4.2) P41/TI07/TO07, P42/TI04/TO04 WRPM PM4 PM4.1, PM4.2 Alternate function P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 122 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of P43 EVDD WRPU PU4 PU4.3 P-ch Selector Internal bus RD WRPORT P4 Output latch (P4.3) P43 WRPM PM4 PM4.3 P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 123 RL78/F12 CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 5 Port 5 is an I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (PM5). When the P50 to P55 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 5 (PU5). Output from the P50 to P55 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using port output mode register 5 (POM5). Input to the P55 pin can be specified as normal input buffer/TTL input buffer in 1-bit units using the port input mode register 5 (PIM5). This port can also be used for clock/buzzer output, serial interface data I/O, and external interrupt request input. Reset signal generation sets port 5 to input mode. For settings of the registers when using port 5, refer to Table 4-8. Table 4-8. Register Settings When Using Port 5 PM5.x Pins PIM5.x POM5.x Remarks Pin as Port Name I/O P50 Input 1 Output 0 – Input 1 Output 0 Input 1 Output 0 Input 1 Output 0 Input 1 × SDA11 output = 1 0 0 P51 Alternate Function Setting When Using CMOS output 1 – – N-ch O.D. output SO output = 1, Note 1 P52 P53 P54 P55 LTxD0 output = 1 – – – – – – – – – 0 Input 1 0 × 0 1 × 1 0 – – Output Output – – × × 0 1 CMOS input TTL input Note 4 (PLLBUZ1 output = 1 SCK00 output = 1 CMOS output Note 5 ) N-ch O.D. output Important To use the port 5 as a general-purpose port, set the alternate pin function output to the level indicated by the Alternate Function Setting When Using Pin as Port. Notes 1. To use LTxD as a serial data output, set a bit in the corresponding port mode register (PMxx) for each port to “1”. And, set the PMX2 register to “0”. 2. To use SOS1 as a serial data output, set a bit in the corresponding port mode register (PMxx) for each port to “1”. And, set the PMX4 register to “0”. 3. To use SCKS1 as a serial data output, set a bit in the corresponding port mode register (PMxx) for each port to “1”. And, set the PMX3 register to “0”. 4. If P55 is used as general-purpose port and PIOR4 is set to 1, set clock output select register 0 (CKS0) to “0”, which is the same as their default status setting. 5. If P55 is used as general-purpose port and PIOR1 is set to 1, use serial channel enable status register 0 (SE0), serial output register 0 (SO0) and serial output enable register 0 (SOE0) with the same setting as the initial status. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 124 RL78/F12 CHAPTER 4 PORT FUNCTIONS Caution P50/INTP1/SI11/SDA11/LRxD0, P51/INTP2/SO11/LTxD, P53/SOS1, P55/SCKS1 as a general-purpose port, set serial channel enable status register 1 (SE1), serial output register 1 (SO1) and serial output enable register 1 (SOE1) to the default status. Stop the operation of serial interface LIN-UART. Clear port output mode register 5 (POM5) to 00H. Remark The descriptions in parentheses indicate the case where PIORx = 1. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 125 RL78/F12 CHAPTER 4 PORT FUNCTIONS For example, figures 4-21 to 4-26 show block diagrams of port 5 for 64-pin products. Figure 4-21. Block Diagram of P50 EVDD WRPU PU5 PU5.0 P-ch Alternate function Selector RD WRPORT Internal bus P5 Output latch (P5.0) P50/INTP1/ SI11/SDA11/LRxD WRPOM POM5 POM5.0 WRPM PM5 PM5.0 Alternate function LRxD P5: Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 POM5: Port output mode register 5 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 126 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-22. Block Diagram of P51 EVDD WRPU PU5 PU5.1 P-ch Alternate function Selector RD WRPORT Internal bus P5 Output latch (P5.1) P51/INTP2/SO11/LTxD WRPM PM5 PM5.1 Alternate function LTxD WRPMX PMX2 PMX2 P5: Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 127 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-23. Block Diagram of P52 EVDD WRPU PU5 PU5.2 P-ch Selector Internal bus RD WRPORT P5 Output latch (P5.2) P52 WRPM PM5 PM5.2 P5: Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 128 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-24. Block Diagram of P53 EVDD WRPU PU5 PU5.3 P-ch Selector RD WRPORT Internal bus P5 Output latch (P5.3) P53/SOS1 WRPM PM5 PM5.3 SOS1 WRPMX PMX4 PMX4 P5: Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 129 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-25. Block Diagram of P54 EVDD WRPU PU5 PU5.4 P-ch Selector Internal bus RD WRPORT P5 Output latch (P5.4) P54/SIS1 WRPM PM5 PM5.4 WRPIEN PIEN PIEN0 SIS1 P5: Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 PIEN: Port input enable register RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 130 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-26. Block Diagram of P55 WRPIM PIM5 PIM5.5 EVDD WRPU PU5 PU5.5 P-ch CMOS Selector RD TTL WRPORT P5 Internal bus Output latch (P5.5) P55/SCKS1 /(PCLBUZ1)/SCK00 WRPOM POM5 POM5.5 WRPM PM5 PM5.5 Alternate function SCKS1 WRPMX PMX3 PMX3 WRPIEN PIEN PIEN0 SIS1 P5: Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 PIEN: Port input enable register PMX3: Port mode register X3 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 131 RL78/F12 CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 6 Port 6 is an I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). The output of the P60 to P63 pins is N-ch open-drain output (6 V tolerance). This port can also be used for serial interface data I/O and clock I/O. Reset signal generation sets port 6 to input mode. Figures 4-27 and 4-28 show block diagrams of port 6. For settings of the registers when using port 6, refer to Table 4-9. Table 4-9. Register Settings When Using Port 6 Pins PM6.x Alternate Function Setting When Using Pin as Port SCLA0 output = 0 Name I/O P60 Input 1 Output 0 Input 1 Output 0 Input 1 Output 0 Input 1 Output 0 P61 P62 P63 Remarks SDAA0 output = 0 – – Important To use the port 6 as a general-purpose port, set the alternate pin function output to the level indicated by the Alternate Function Setting When Using Pin as Port. Caution Stop the operation of serial interface IICA when using P60/SCLA0, P61/SDAA0 as general- purpose ports. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 132 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-27. Block Diagram of P60, P61 Alternate function Selector RD Internal bus WRPORT P6 Output latch (P6.0, P6.1) P60/SCLA0, P61/SDAA0 WRPM PM6 PM6.0, PM6.1 Alternate function P6: Port register 6 PM6: Port mode register 6 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 133 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-28. Block Diagram of P62, P63 Internal bus Selector RD WRPORT P6 Output latch (P6.2, P6.3) P62, P63 WRPM PM6 PM6.2, PM6.3 P6: Port register 6 PM6: Port mode register 6 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 134 RL78/F12 CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 7 Port 7 is an I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 7 (PU7). Output from the P71 and P74 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using port output mode register 7 (POM7). This port can also be used for key interrupt input, serial interface data I/O, clock I/O, and external interrupt request input. Reset signal generation sets port 7 to input mode. For settings of the registers when using port 7, refer to Table 4-10. Table 4-10. Register Settings When Using Port 7 Pins PM7.x POM7.x Alternate Function Setting When Using Pin as Port – × Name I/O P70 Input 1 Output 0 P71 P72 P73 P74 P75 P76 P77 Remarks SCK21/SCL21 output = 1 Input 1 × × Output 0 0 SDA21 output = 1 0 1 Input 1 – Output 0 Input 1 Output 0 Input 1 × × Output 0 0 SDA01 output = 1 0 1 Input 1 – Output 0 Input 1 Output 0 Input 1 Output 0 CMOS output N-ch O.D. output × SO21 output = 1 – × SO01 output = 1 CMOS output N-ch O.D. output × SCK01/SCL01 output = 1 – – – × (TDX2 output = 1 Note ) Important To use the port 7 as a general-purpose port, set the alternate pin function output to the level indicated by the Alternate Function Setting When Using Pin as Port. Note If P77 is used as general-purpose port and PIOR1 is set to 1, use serial channel enable status register 1 (SE1), serial output register 1 (SO1) and serial output enable register 1 (SOE1) with the same setting as the initial status. Caution P70/KR0/SCK21/SCL21, P71/KR1/SI21/SDA21 or P72/KR2/SO21, P73/KR3/SO01, P74/KR4/INTP8/SI01/ SDA01, P75/INTP9/SCK01/SCL01 as a general-purpose port, set serial channel enable status register m (SEm), serial output register m (SOm) and serial output enable register m (SOEm) to the default sta tus (m = 0, 1). Remark The descriptions in parentheses indicate the case where PIORx = 1. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 135 RL78/F12 CHAPTER 4 PORT FUNCTIONS For example, figures 4-29 to 4-32 show block diagrams of port 7 for 64-pin products. Figure 4-29. Block Diagram of P70, P75 EVDD WRPU PU7 PU7.0, PU7.5 P-ch Alternate function Selector Internal bus RD WRPORT P7 Output latch (P7.0, P7.5) P70/KR0/SCK21/SCL21, P75/KR5/INTP9/SCK01/SCL01 WRPM PM7 PM7.0, PM7.5 Alternate function P7: Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 136 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-30. Block Diagram of P71, P74 EVDD WRPU PU7 PU7.1, PU7.4 P-ch Alternate function Internal bus Selector RD WRPORT P7 Output latch (P7.1, P7.4) P71/KR1/SI21/SDA21, P74/KR4/INTP8/SI01/SDA01 WRPOM POM7 POM7.1, POM7.4 WRPM PM7 PM7.1, PM7.4 Alternate function P7: Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 POM7: Port output mode register 7 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 137 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-31. Block Diagram of P72, P73 EVDD WRPU PU7 PU7.2, PU7.3 P-ch Alternate function Selector Internal bus RD WRPORT P7 Output latch (P7.2, P7.3) P72/KR2/SO21, P73/KR3/SO01 WRPM PM7 PM7.2, PM7.3 Alternate function P7: Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 138 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-32. Block Diagram of P76, P77 EVDD WRPU PU7 PU7.6, PU7.7 P-ch Alternate function Selector Internal bus RD WRPORT P7 Output latch (P7.6, P7.7) P76/KR6/INTP10, P77/KR7/INTP11 WRPM PM7 PM7.6, PM7.7 P7: Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 139 RL78/F12 CHAPTER 4 PORT FUNCTIONS 4.2.9 Port 12 P120 is an I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). P121 to P124 are 4-bit input ports. Input to the P120 pin can be specified as analog input or digital input in 1-bit units, using port mode control register 12 (PMC12). This port can also be used for A/D converter analog input, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input for main system clock, and external clock input for subsystem clock. Reset signal generation sets P120 to analog input and P121 to P124 to input mode. Figures 4-33 to 4-35 show block diagrams of port 12. For settings of the registers when using port 12, refer to Table 4-11. Table 4-11. Register Settings When Using Port 12 Pins PM12.x PMC12.x Alternate Function Setting When Using Pin as Port Name I/O P120 Input 1 0 × Output 0 0 × P121 Input – – Bits OSCSEL = 0 or EXCLK = 1 of the CMC register P122 Input – – The OSCSEL bit of the CMC register = 0 P123 Input – – Bits OSCSELS = 0 or EXCLKS = 1 of the CMC register P124 Input – – The OSCSELS bit of the CMC register = 0 Remarks Important To use the port 12 as a general-purpose port, set the alternate pin function output to the level indicated by the Alternate Function Setting When Using Pin as Port. Caution The function setting on P121 to P124 is available only once after the reset release. The port once set for connection to an oscillator cannot be used as an input port unless the reset is performed. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 140 RL78/F12 CHAPTER 4 PORT FUNCTIONS For example, figures 4-33 to 4-35 show block diagrams of port 12 for 64-pin products. Figure 4-33. Block Diagram of P120 EVDD WRPU PU12 PU12.0 P-ch WRPMC PMC12 Internal bus PMC12.0 Selector RD WRPORT P12 Output latch (P12.0) P120/ANI19 WRPM PM12 PM12.0 A/D converter P12: Port register 12 PU12: Pull-up resistor option register 12 PM12: Port mode register 12 PMC12: Port mode control register 12 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 141 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-34. Block Diagram of P121 and P122 Clock generator CMC OSCSEL RD Internal bus P122/X2/EXCLK CMC EXCLK, OSCSEL RD P121/X1 CMC: Clock operation mode control register RD: Read signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 142 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-35. Block Diagram of P123 and P124 Clock generator CMC OSCSELS RD Internal bus P124/XT2/EXCLKS CMC EXCLKS, OSCSELS RD P123/XT1 CMC: Clock operation mode control register RD: Read signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 143 RL78/F12 CHAPTER 4 PORT FUNCTIONS 4.2.10 Port 13 P130 is a 1-bit output-only port with an output latch. P137 is a 1-bit input-only port. When the reset signal is generated, P130 is fixed to output mode and P137 to input mode. This port can also be used for external interrupt request input. Figures 4-36 and 4-37 show block diagrams of port 13. Figure 4-36. Block Diagram of P130 Internal bus RD WRPORT P13 Output latch (P13.0) P13: Port register 13 RD: Read signal P130 WR××: Write signal Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the CPU reset signal. Reset signal P130 Set by software R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 144 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-37. Block Diagram of P137 RD Internal bus Alternate function RD: P137/INTP0 Read signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 145 RL78/F12 CHAPTER 4 PORT FUNCTIONS 4.2.11 Port 14 Port 14 is an I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (PM14). When the P140, P141, P146, P147 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 14 (PU14). Input to the P147 pin can be specified as analog input or digital input in 1-bit units, using port mode control register 14 (PMC14). This port can also be used for clock/buzzer output, external interrupt request input, and A/D converter analog input. Reset signal generation sets P140, P141, and P146 to input mode and P147 to analog input mode. For settings of the registers when using port 14, refer to Table 4-12. Table 4-12. Register Settings When Using Port 14 Pins PM14.x PMC14.x Alternate Function Setting When Using Pin as Port – × Name I/O P140 Input 1 Output 0 P141 P146 P147 Remarks PCLBUZ0 output = 0 – × Input 1 Output 0 Input 1 Output 0 Input 1 0 × Output 0 0 × PCLBUZ1 output = 0 – × × Important To use the port 14 as a general-purpose port, set the alternate pin function output to the level indicated by the Alternate Function Setting When Using Pin as Port. Caution To use P140/PCLBUZ0/INTP6, P141/PCLBUZ1/INTP7 as a general-purpose port, set bit 7 of clock output select register 0, 1 (CKS0, CKS1) to “0”, which is the same as their default status settings. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 146 RL78/F12 CHAPTER 4 PORT FUNCTIONS For example, figures 4-38 to 4-40 show block diagrams of port 14 for 64-pin products. Figure 4-38. Block Diagram of P140 and P141 EVDD WRPU PU14 PU14.0, PU14.1 P-ch Alternate function Selector Internal bus RD WRPORT P14 Output latch (P14.0, P14.1) P140/PCLBUZ0/INTP6 P141/PCLBUZ1/INTP7 WRPM PM14 PM14.0, PM14.1 Alternate function P14: Port register 14 PU14: Pull-up resistor option register 14 PM14: Port mode register 14 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 147 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-39. Block Diagram of P146 EVDD WRPU PU14 PU14.6 P-ch Selector Internal bus RD WRPORT P14 Output latch (P14.6) P146 WRPM PM14 PM14.6 P14: Port register 14 PU14: Pull-up resistor option register 14 PM14: Port mode register 14 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 148 RL78/F12 CHAPTER 4 PORT FUNCTIONS Figure 4-40. Block Diagram of P147 EVDD WRPU PU14 PU14.7 P-ch WRPMC PMC14 Internal bus PMC14.7 Selector RD WRPORT P14 Output latch (P14.7) P147/ANI18 WRPM PM14 PM14.7 A/D converter P14: Port register 14 PU14: Pull-up resistor option register 14 PM14: Port mode register 14 PMC14: Port mode control register 14 RD: Read signal WR××: Write signal R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 149 RL78/F12 CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following registers. • • • • • • • • • • Port mode registers (PMxx) Port registers (Pxx) Pull-up resistor option registers (PUxx) Port input mode registers (PIMxx) Port output mode registers (POMxx) Port mode control registers (PMCxx) A/D port configuration register (ADPC) Port mode registers X (PMXx) Peripheral I/O redirection register (PIOR) Port input enable register (PIEN) R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 150 RL78/F12 CHAPTER 4 PORT FUNCTIONS Table 4-13. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product (1/2) Port Bit name PMxx Port 0 0 Pxx PUxx PIMxx register − register register register PM0.0 P0.0 PU0.0 POMxx 64 48 32 30 20 pin pin pin pin pin − √ √ √ √ − − √ √ √ √ √ PMCxx PMXx register register register POM0.0 PMC0.0 Note 1 PM0.1 P0.1 PU0.1 PIM0.1 − PMC0.1 Note 2 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Note PM0.2 P0.2 PU0.2 − POM0.2 PMC0.2 − √ − − − − PMC0.3 3 PM0.3 P0.3 PU0.3 PIM0.3 POM0.3 − √ − − − − 4 PM0.4 P0.4 PU0.4 PIM0.4 POM0.4 − − √ − − − − 5 PM0.5 P0.5 PU0.5 − − − − √ − − − − 6 PM0.6 P0.6 PU0.6 − − − − √ − − − − 0 PM1.0 P1.0 PU1.0 − POM1.0 − √ √ √ √ √ 1 PM1.1 P1.1 PU1.1 − POM1.1 − √ √ √ √ √ 2 PM1.2 P1.2 PU1.2 − POM1.2 − √ √ √ √ √ 3 PM1.3 P1.3 PU1.3 PIM1.3 POM1.3 − − √ √ √ √ − 4 PM1.4 P1.4 PU1.4 PIM1.4 POM1.4 − − √ √ √ √ − 5 PM1.5 P1.5 PU1.5 PIM1.5 POM1.5 − − √ √ √ √ − √ PMX0 − PMX1 6 PM1.6 P1.6 PU1.6 PIM1.6 − − − √ √ √ √ 7 PM1.7 P1.7 PU1.7 PIM1.7 POM1.7 − − √ √ √ √ √ 0 PM2.0 P2.0 − − − − − √ √ √ √ √ 1 PM2.1 P2.1 − − − − − √ √ √ √ √ 2 PM2.2 P2.2 − − − − − √ √ √ √ √ 3 PM2.3 P2.3 − − − − − √ √ √ √ − 4 PM2.4 P2.4 − − − − − √ √ − − − 5 PM2.5 P2.5 − − − − − √ √ − − − 6 PM2.6 P2.6 − − − − − √ √ − − − 7 PM2.7 P2.7 − − − − − √ √ − − − 0 PM3.0 P3.0 PU3.0 − − − − √ √ √ √ − 1 PM3.1 P3.1 PU3.1 − − − − √ √ √ √ √ 0 PM4.0 P4.0 PU4.0 − − − − √ √ √ √ √ 1 PM4.1 P4.1 PU4.1 − − − − √ √ − − − 2 PM4.2 P4.2 PU4.2 − − − − √ − − − − 3 PM4.3 P4.3 PU4.3 − − − − √ − − − − 0 PM5.0 P5.0 PU5.0 − POM5.0 − − √ √ √ √ √ 1 PM5.1 P5.1 PU5.1 − − − √ √ √ √ √ 2 PM5.2 P5.2 PU5.2 − − − √ − − − − 3 PM5.3 P5.3 PU5.3 − − − √ − − − − 4 PM5.4 P5.4 PU5.4 − − − 5 PM5.5 P5.5 PU5.5 PIM5.5 POM5.5 − 0 PM6.0 P6.0 − − − − 1 PM6.1 P6.1 − − − 2 PM6.2 P6.2 − − − 3 PM6.3 P6.3 − − − PMX2 − PMX4 − √ − − − − √ − − − − − √ √ √ √ − − − √ √ √ √ − − − √ √ √ − − − − √ √ − − − PMX3 20-, 30-, and 32-pin products only. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 151 RL78/F12 CHAPTER 4 PORT FUNCTIONS Table 4-13. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product (2/2) Port Bit name PMxx Port 7 Port 12 Port 13 Port 14 Note Pxx PUxx PIMxx POMxx PMCxx PMXx 64 48 32 30 20 pin pin pin pin pin register register register register register register register 0 PM7.0 P7.0 PU7.0 − − − − √ √ √ − − 1 PM7.1 P7.1 PU7.1 − POM7.1 − − √ √ − − − 2 PM7.2 P7.2 PU7.2 − − − − √ √ − − − 3 PM7.3 P7.3 PU7.3 − − − − √ √ − − − 4 PM7.4 P7.4 PU7.4 − POM7.4 − − √ √ − − − 5 PM7.5 P7.5 PU7.5 − − − − √ √ − − − 6 PM7.6 P7.6 PU7.6 − − − − √ − − − − 7 PM7.7 P7.7 PU7.7 − − − − √ − − − − 0 PM12.0 P12.0 PU12.0 − − PMC12.0 − √ √ √ √ − 1 − PM12.1 − − − − − √ √ √ √ √ 2 − PM12.2 − − − − − √ √ √ √ √ 3 − PM12.3 − − − − − √ √ − − − 4 − PM12.4 − − − − − √ √ − − − 0 − P13.0 − − − − − √ √ − − − 7 − P13.7 − − − − − √ √ √ √ √ 0 PM14.0 P14.0 PU14.0 − − − − √ √ − − − 1 PM14.1 P14.1 PU14.1 − − − − √ − − − − 6 PM14.6 P14.6 PU14.6 − − − − √ √ − − − 7 PM14.7 P14.7 PU14.7 − − PMC14.7 − √ √ √ √ − 20-, 30-, and 32-pin products only. The format of each register is described below. The description here uses the 64-pin products as an example. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 152 RL78/F12 CHAPTER 4 PORT FUNCTIONS (1) Port mode registers (PMxx) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. When port pins are used as alternate-function pins, set the port mode register by referencing 4.5 Settings of Port Mode Register, and Output Latch When Using Alternate Function. Figure 4-41. Format of Port Mode Register (64-pin products) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM0 1 PM0.6 PM0.5 PM0.4 PM0.3 PM0.2 PM0.1 PM0.0 FFF20H FFH R/W PM1 PM1.7 PM1.6 PM1.5 PM1.4 PM1.3 PM1.2 PM1.1 PM1.0 FFF21H FFH R/W PM2 PM2.7 PM2.6 PM2.5 PM2.4 PM2.3 PM2.2 PM2.1 PM2.0 FFF22H FFH R/W PM3 1 1 1 1 1 1 PM3.1 PM3.0 FFF23H FFH R/W PM4 1 1 1 1 PM4.3 PM4.2 PM4.1 PM4.0 FFF24H FFH R/W PM5 1 1 PM5.5 PM5.4 PM5.3 PM5.2 PM5.1 PM5.0 FFF25H FFH R/W PM6 1 1 1 1 PM6.3 PM6.2 PM6.1 PM6.0 FFF26H FFH R/W PM7 PM7.7 PM7.6 PM7.5 PM7.4 PM7.3 PM7.2 PM7.1 PM7.0 FFF27H FFH R/W PM12 1 1 1 1 1 1 1 PM12.0 FFF2CH FFH R/W PM14 PM14.7 PM14.6 1 1 1 1 PM14.1 PM14.0 FFF2EH FFH R/W Pmn pin I/O mode selection PMm.n (m = 0 to 7, 12, 14; n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Cautions 1. Be sure to set bits 7 of the PM0 registers, bits 2 to7 of the PM3 registers, bits 4 to 7 of the PM4 register, bits 6, 7 of the PM5 register, bits 4 to 7 of the PM6 registers, bits 1 to 7 of the PM12 register, and bits 2 to 5 of the PM14 register to “1”. 2. In 20-pin products, complete the following software processing for the following each port before performing the operation that reads the port latch Pm having the target port latch Pm.n within 50 ms after releasing reset (after starting CPU operation). • Set P00, P13, P14, P15, P30, P60, P61, P120, and P147 to low level output mode by the software (clear the PMm.n and Pm.n bits for the target ports). • Set P23 to digital port and low level output mode by the software (set P23 to digital mode with the ADPC register and clear the PM2.3 and P2.3 bits). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 153 RL78/F12 CHAPTER 4 PORT FUNCTIONS (2) Port registers (Pxx) These registers set the output latch value of a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is Note read . These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Note If P00 to P03, P20 to P27, P120, and P147 are set up as analog inputs of the A/D converter, when a port is read while in the input mode, 0 is always returned, not the pin level. Figure 4-42. Format of Port Register (64-pin products) Symbol 7 6 5 4 3 2 1 0 Address P0 0 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 FFF00H 00H (output latch) R/W P1 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 FFF01H 00H (output latch) R/W P2 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 FFF02H 00H (output latch) R/W P3 0 0 0 0 0 0 P3.1 P3.0 FFF03H 00H (output latch) R/W P4 0 0 0 0 P4.3 P4.2 P4.1 P4.0 FFF04H 00H (output latch) R/W P5 0 0 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 FFF05H 00H (output latch) R/W P6 0 0 0 0 P6.3 P6.2 P6.1 P6.0 FFF06H 00H (output latch) R/W P7 P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0 FFF07H 00H (output latch) R/W P12 0 0 0 P12.4 P12.3 P12.2 P12.1 P12.0 FFF0CH Undefined R/W Note P13 P13.7 0 0 0 0 0 0 P13.0 FFF0DH Undefined R/W Note P14 P14.7 P14.6 0 0 0 0 P14.1 P14.0 FFF0EH Pm.n 2. R/W 00H (output latch) R/W m = 0 to 15; n = 0 to 7 Output data control (in output mode) Notes 1. After reset Input data read (in input mode) 0 Output 0 Input low level 1 Output 1 Input high level P121 to P124, and P137 are read-only. P137: Undefined P130: 0 (output latch) Caution For the following each port, complete the following software processing before performing the operation that reads the port latch Pm having the target port latch Pm.n within 50 ms after releasing reset (after staring CPU operation) • Set P00, P13, P14, P15, P30, P60, P61, P120, and P147 to low level output mode by the software (clear the PMm.n and Pm.n bits for the target ports). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 154 RL78/F12 CHAPTER 4 PORT FUNCTIONS • Set P23 to digital port and low level output mode by the software (set P23 to digital mode with the ADPC register and clear the PM2.3 and P2.3 bits). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 155 RL78/F12 CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option registers (PUxx) These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode (PMmn = 1) by setting POMmn = 0 of the pins to which the use of an on-chip pull-up resistor has been specified in these registers. On-chip pull-up resistors cannot be connected to bits set to output mode, bits used as alternate-function output pins, and bits with analog setting (PMC = 1, ADPC =1), regardless of the settings of these registers. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H (Only PU4 is set to 01H). Caution When a port with the PIMn register is input from different potential device to TTL buffer, pull up to the power supply of the different potential device via a external pull-up resistor by setting PUmn = 0. Figure 4-43. Format of Pull-up Resistor Option Register (64-pin products) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PU0 0 PU0.6 PU0.5 PU0.4 PU0.3 PU0.2 PU0.1 PU0.0 F0030H 00H R/W PU1 PU1.7 PU1.6 PU1.5 PU1.4 PU1.3 PU1.2 PU1.1 PU1.0 F0031H 00H R/W PU3 0 0 0 0 0 0 PU3.1 PU3.0 F0033H 00H R/W PU4 0 0 0 0 PU4.3 PU4.2 PU4.1 PU4.0 F0034H 01H R/W PU5 0 0 PU5.5 PU5.4 PU5.3 PU5.2 PU5.1 PU5.0 F0035H 00H R/W PU7 PU7.7 PU7.6 PU7.5 PU7.4 PU7.3 PU7.2 PU7.1 PU7.0 F0037H 00H R/W PU12 0 0 0 0 0 0 0 PU12.0 F003CH 00H R/W PU14 PU14.7 PU14.6 0 0 0 0 PU14.1 PU14.0 F003EH 00H R/W Pmn pin on-chip pull-up resistor selection PUm.n (m = 0, 1, 3 to 5, 7, 12, 14; n = 0 to 7) 0 On-chip pull-up resistor not connected 1 On-chip pull-up resistor connected R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 156 RL78/F12 CHAPTER 4 PORT FUNCTIONS (4) Port input mode registers (PIM0, PIM1, PM5) These registers set the input buffer in 1-bit units. TTL input buffer can be selected for serial communication, etc with an external device of the different potential. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 4-44. Format of Port Input Mode Register (64-pin products) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PIM0 0 0 0 PIM0.4 PIM0.3 0 PIM0.1 0 F0040H 00H R/W PIM1 PIM1.7 PIM1.6 PIM1.5 PIM1.4 PIM1.3 0 0 0 F0041H 00H R/W PIM5 0 0 PIM5.5 0 0 0 0 0 F0045H 00H R/W Pmn pin input buffer selection PIMm.n (m = 0, 1, 5; n = 1, 3 to 7) 0 Normal input buffer 1 TTL input buffer R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 157 RL78/F12 CHAPTER 4 PORT FUNCTIONS (5) Port output mode registers (POM0, POM1, POM5, POM7) These registers set the output mode in 1-bit units. N-ch open drain output (VDD tolerance/EVDD toleranceNote) mode can be selected during serial communication with an external device of the different potential, and for the SDA00, SDA01, SDA10, SDA11, SDA20, and SDA21 pins during 2 simplified I C communication with an external device of the same potential. In addition, these registers are combined with PUxx registers to specify whether to use an on-chip pull-up resistor. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 4-45. Format of Port Input Mode Register (64-pin products) Symbol 7 6 5 POM0 0 0 0 POM1 POM1.7 POM5 POM7 4 3 2 1 0 Address After reset R/W 0 POM0.0 FFF50H 00H R/W 0 POM1.5 POM1.4 POM1.3 POM1.2 POM1.1 POM1.0 FFF51H 00H R/W 0 0 POM5.5 0 0 0 0 POM5.0 FFF55H 00H R/W 0 0 0 POM7.4 0 0 POM7.1 0 F007H 00H R/W POM0.4 POM0.3 POM0.2 Pmn pin output mode selection POMm.n (m = 0, 1, 5, 7; n = 0 to 5, 7) 0 Normal output mode PUmn bit is enabled during input. 1 N-ch open-drain output (VDD tolerance Note1 /EVDD tolerance Note2 ) mode PUmn bit is disabled during input. Notes 1. 2. For 20- to 48-pin products For 64-pin products R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 158 RL78/F12 CHAPTER 4 PORT FUNCTIONS (6) Port mode control registers (PMC0, PMC12, PMC14) These registers set the P00, P01, P120, and P147 digital I/O/analog input in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to FFH. Figure 4-46. Format of Port Mode Control Register Symbol 7 6 5 4 PMC0 1 1 1 1 PMC12 1 1 1 3 2 1 PMC0.3 PMC0.2 PMC0.1 1 0 Address After reset R/W PMC0.0 F0060H FFH R/W F006CH FFH R/W F006EH FFH R/W Note2 Note2 Note1 Note1 1 1 1 PMC12.0 Note3 PMC14 PMC14.7 1 1 1 1 1 1 1 Note3 Pmn pin digital I/O/analog input selection PMCm.n (m = 0, 12, 14; n = 0 to 3, 7) Notes 1. 0 Digital I/O (alternate function other than analog input) 1 Analog input For 20-, 30-, 32-pin products 2. For 64-pin products 3. For 30-, 32-, 48-, 64-pin products Cautions 1. Set the channels to be used for A/D conversion to input mode by the port mode registers 0, 12, 14 (PM0, PM12, PM14) 2. Do not set the pins by the analog input channel specification register (ADS) when the pins are to be specified as digital I/O by the PMC register. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 159 RL78/F12 CHAPTER 4 PORT FUNCTIONS (7) A/D port configuration register (ADPC) This register switches the P20/ANI0 to P27/ANI7, and P150/ANI8 to P156/ANI14 pins to digital I/O of port or analog input of A/D converter. The ADPC register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 4-47. Format of A/D Port Configuration Register (ADPC) (64-pin products) Address: F0076H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADPC 0 0 0 0 ADPC.3 ADPC.2 ADPC.1 ADPC.0 ADPC.3 ADPC.2 ADPC.1 ADPC.0 Analog input (A)/digital I/O (D) switching ANI7/P27 0 0 0 0 A A A A A A A A 0 0 0 1 D D D D D D D D 0 0 1 0 D D D D D D D A 0 0 1 1 D D D D D D A A 0 1 0 0 D D D D D A A A 0 1 0 1 D D D D A A A A 0 1 1 0 D D D A A A A A 0 1 1 1 D D A A A A A A 1 0 0 0 D A A A A A A A Other than above ANI6/P26 ANI5/P25 ANI4/P24 ANI3/P23 ANI2/P22 ANI1/P21 ANI0/P20 Setting prohibited Cautions 1. Set the channel used for A/D conversion to the input mode by using port mode register 2 (PM2). 2. Do not set the pin set by the ADPC register as digital I/O by the analog input channel specification register (ADS). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 160 RL78/F12 CHAPTER 4 PORT FUNCTIONS (8) Port mode registers X (PMX0 to PMX4) These registers switch modes of some serial communication pins. These registers are set when the pin SCKS0 (master mode), SOS0, TxDS0, LTxD, or SCKS1 is used. The PMX0 to PMX4 registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 01H. Figure 4-48. Format of Port Mode Register X (64-pin products) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PMX0 0 0 0 0 0 0 0 PMX0 F0504H 01H R/W PMX0 Selection of alternate function of P10/SCK00/SCKS0/SCL00 pin 0 SCKS0 output (master mode) 1 SCKS0 input (slave mode), or other alternate function (including general-purpose I/O port) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PMX1 0 0 0 0 0 0 0 PMX1 F0505H 01H R/W PMX1 Selection of alternate function of P12/SO00/TxD0/SOS0/TxDS0/TOOLTxD pin 0 SOS0 or TxDS0 output 1 Other alternate function (including general-purpose I/O port) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PMX2 0 0 0 0 0 0 0 PMX2 F0506H 01H R/W PMX2 Selection of alternate function of P51/INTP2/SO11/LTxD pin 0 LTxD0 output 1 Other alternate function (including general-purpose I/O port) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PMX3 0 0 0 0 0 0 0 PMX3 F0507H 01H R/W PMX3 Selection of alternate function of P55/SCKS1 pin 0 SCKS1 output (master mode) 1 SCKS1 input (slave mode) or other alternate function (including general-purpose I/O port) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PMX4 0 0 0 0 0 0 0 PMX4 F0508H 01H R/W PMX4 Selection of alternate function of P53/SOS1 pin 0 SOS1 output (master mode) 1 Other alternate function (including general-purpose I/O port) R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 161 RL78/F12 CHAPTER 4 PORT FUNCTIONS (9) Peripheral I/O redirection register (PIOR) This register is used to specify whether to enable or disable the peripheral I/O redirect function. This function is used to switch ports to which alternate functions are assigned. The PIOR register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 4-49. Format of Peripheral I/O redirection register (PIOR) Address: F0077H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PIOR 0 0 0 PIOR4 PIOR3 PIOR2 PIOR1 PIOR0 bit Function 64-pin 48-pin 32-pin 30-pin 20-pin Setting Value Setting Value Setting Value Setting Value Setting Value 0 PIOR4 PIOR3 PIOR2 PIOR1 PIOR0 1 PCLBUZ1 P141 P55 INTP5 P16 P12 PCLBUZ0 P140 P31 0 1 0 1 0 1 0 1 Setting is unnecessary. This can be used regardless of value. P140 P31 SCLA0 P60 P14 P60 P14 P60 P14 P60 P14 − − SDAA0 P61 P13 P61 P13 P61 P13 P61 P13 − − INTP10 P76 P52 − − − − − − − − INTP11 P77 P53 − − − − − − − − TxD2 P13 P77 P13 − P13 − P13 − − − RxD2 P14 P76 P14 − P14 − P14 − − − SCL20 P15 − P15 − P15 − P15 − − − SDA20 P14 − P14 − P14 − P14 − − − SI20 P14 − P14 − P14 − P14 − − − SO20 P13 − P13 − P13 − P13 − − − SCK20 P15 − P15 − P15 − P15 − − − TxD0 P12 P17 P12 P17 P12 P17 P12 P17 P12 P17 RxD0 P11 P16 P11 P16 P11 P16 P11 P16 P11 P16 SCL00 P10 − P10 − P10 − P10 − P10 − SDA00 P11 − P11 − P11 − P11 − P11 − SI00 P11 P16 P11 − P11 − P11 − P11 − SO00 P12 P17 P12 − P12 − P12 − P12 − SCK00 P10 P55 P10 − P10 − P10 − P10 − TI02/TO02 P17 P15 P17 P15 P17 P15 P17 P15 P17 − TI03/TO03 P31 P14 P31 P14 P31 P14 P31 P14 P31 − TI04/TO04 P42 P13 − P13 − P13 − P13 − − TI05/TO05 P05 P12 − P12 − P12 − P12 − P12 TI06/TO06 P06 P11 − P11 − P11 − P11 − P11 TI07/TO07 P41 P10 P41 P10 − P10 − P10 − P10 R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 162 RL78/F12 CHAPTER 4 PORT FUNCTIONS (10) Port input enable register (PIEN) This register specifies whether to use the input function of some serial communication pins. This register is set when the SIS1 or SCKS1 pin (slave mode) is used. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 4-50. Format of Port Input Enable Register (PIEN) Address: F0509H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PIOR 0 0 0 0 0 0 0 PIEN0 PIEN0 Selection of alternate function of SIS1 or SCKS1 pin 0 Input function of SIS1 or SCKS1 pin (slave mode) is not used. 1 Input function of SIS1 and/or SCKS1 pin (slave mode) is used. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 163 RL78/F12 CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated. (2) Input mode A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. Thus writing in byte units is possible in a port which includes both input and output pins. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated. 4.4.2 Reading from I/O port (1) Output mode The output latch contents are read by a transfer instruction. The output latch contents do not change. (2) Input mode The pin status is read by a transfer instruction. The output latch contents do not change. 4.4.3 Operations on I/O port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated. (2) Input mode The pin level is read and an operation is performed on its contents. The result of the operation is written to the output latch, but since the output buffer is off, the pin status does not change. Thus writing in byte units is possible in a port which includes both input and output pins. The data of the output latch is cleared when a reset signal is generated. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 164 RL78/F12 CHAPTER 4 PORT FUNCTIONS 4.4.4 Connecting to external device with different potential (2.5 V, 3 V) When parts of ports 0, 1, 5 operate with VDD = 4.0 V to 5.5 V, I/O connections with an external device that operates on 2.5 V, 3 V power supply voltage are possible. Regarding inputs, CMOS/TTL switching is possible on a bit-by-bit basis by the port input mode registers (PIM0, PIM1, PIM5). Moreover, regarding outputs, different potentials can be supported by switching the output buffer to the N-ch open drain (VDD tolerance/EVDD toleranceNote) by the port output mode registers (POM0, POM1, POM5, POM7). Note 64-bit products only (1) Setting procedure when using I/O pins of UART0, UART1, UART2, CSI00, CSI10, and CSI20 functions (a) Use as 2.5 V, 3 V input port After reset release, the port mode is the input mode (Hi-Z). If pull-up is needed, externally pull up the pin to be used (on-chip pull-up resistor cannot be used). Remark In case of UART0: (P16) In case of UART1: P03 In case of UART2: P14 In case of CSI00: (P16, P55) In case of CSI10: P03, P04 In case of CSI20: P14, P15 Pins in parentheses can be assigned via settings in the peripheral I/O redirection register (PIOR). Set the corresponding bit of the PIM0, PIM1, PIM5 registers to 1 to switch to the TTL input buffer. VIH/VIL operates on 2.5 V, 3 V operating voltage. (b) Use as 2.5 V, 3 V output port After reset release, the port mode changes to the input mode (Hi-Z). Pull up externally the pin to be used (on-chip pull-up resistor cannot be used). Remark In case of UART0: P12 (P17) In case of UART1: P02 In case of UART2: P13 In case of CSI00: P12, P10 (P17, P55) In case of CSI10: P02, P04 In case of CSI20: P13, P15 Pins in parentheses can be assigned via settings in the peripheral I/O redirection register (PIOR). Set the output latch of the corresponding port to 1. Set the corresponding bit of the POM0, POM1, POM5 registers to 1 to set the N-ch open drain output (VDD tolerance/EVDD tolerance) mode. Set the output mode by manipulating the PM0, PM1, and PM5 registers. At this time, the output data is high level, so the pin is in the Hi-Z state. Communication is started by setting the serial array unit. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 165 RL78/F12 CHAPTER 4 PORT FUNCTIONS (2) Setting procedure when using I/O pins of simplified IIC20 functions After reset release, the port mode is the input mode (Hi-Z). Externally pull up the pin to be used (on-chip pull-up resistor cannot be used). In case of simplified IIC10: P03, P04 In case of simplified IIC20: P14, P15 Set the output latch of the corresponding port to 1. Set the corresponding bit of the POM0 or POM1 register to 1 to set the N-ch open drain output (VDD tolerance/EVDD tolerance) mode. Set the corresponding bit of the POM0 or POM1 register to the output mode (data I/O is possible in the output mode). At this time, the output data is high level, so the pin is in the Hi-Z state. Enable the operation of the serial array unit and set the mode to the simplified IIC mode. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 166 RL78/F12 CHAPTER 4 PORT FUNCTIONS 4.5 Settings of Port Mode Register, and Output Latch When Using Alternate Function To use the alternate function of a port pin, set the port mode register, and output latch as shown in Table 4-14. Table 4-14. Settings of Port Mode Register, and Output Latch When Using Alternate Function (1/5) Pin Name Alternate Function PIOR.× PMC×.× PM×.× P×.× PMX.× Input × − 1 × − Function Name I/O P00 TI00 P01 TO00 Output × − 0 0 − P02 ANI17 Input × 1 1 × − SO10 Output × 0 0 1 − TxD1 Output × 0 0 1 − ANI16 Input × 1 1 × − SI10 Input × 0 1 × − RxD1 Input × 0 1 × − SDA10 I/O × 0 0 1 − P03 P04 Input × − 1 × − Output × − 0 1 − SCL10 Output × − 0 1 − TI05 Input 0 − 1 × − SCK10 P05 P06 P10 TO05 Output 0 − 0 0 − TI06 Input 0 − 1 × − TO06 Output 0 − 0 0 − SCK00 Input 0 − 1 × 1 Output 0 − 0 1 1 Input × − 1 × 1 × − 1 × 0 0 − 0 1 1 SCKS0 Output Remarks 1. Note 2 SCL00 Output (TI07) Input 1 − 1 × 1 (TO07) Output 1 − 0 0 1 ×: don’t care PIOR.×: Peripheral I/O redirection register POM×.×: Port output mode register PMC×.×: Port mode control register PM×.×: Port mode register P×.×: Port output latch PMX.×: PMX register of the port 2. The relationship between pins and their alternate functions shown in this table indicates the relationship when a 64-pin product is used. In other products, alternate functions might be assigned to different pins, but even in this case, the PIOR.×, PMC×.×, PM×.×, P×.×, and PMX.× settings remain the same. 3. Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection register (PIOR). (The notes are described after the last table.) R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 167 RL78/F12 CHAPTER 4 PORT FUNCTIONS Table 4-14. Settings of Port Mode Register, and Output Latch When Using Alternate Function (2/5) Pin Name Alternate Function PIOR.× PMC×.× PM×.× P×.× PMX.× Input 0 − 1 × − RxD0 Input 0 − 1 × − SIS0 Input × − 1 × − Input × − 1 × − I/O 0 − 0 1 − (TI06) Input 1 − 1 × − (TO06) Output 1 − 0 0 − SO00 Output 0 − 0 1 1 Output 0 − 0 1 1 Function Name P11 SI00 RxDS0 SDA00 P12 Note 4 TxD0 Note 2 Output × − 1 × 0 Output × − 1 × 0 (TI05) Input 1 − 1 × 1 (TO05) Output 1 − 0 0 1 SOS0 TxDS0 P13 P14 Note 2 (INTP5) Input 1 − 1 × 1 TxD2 Output 0 − 0 1 − SO20 Output 0 − 0 1 − (SDAA0) I/O 1 − 0 0 − (TI04) Input 1 − 1 × − (TO04) Output 1 − 0 0 − RxD2 Input 0 − 1 × − Input 0 − 1 × − SI20 Note 4 I/O 0 − 0 1 − (SCLA0) I/O 1 − 0 0 − (TI03) Input 1 − 1 × − (TO03) Output 1 − 0 0 − SDA20 Remarks 1. I/O ×: don’t care PIOR.×: Peripheral I/O redirection register POM×.×: Port output mode register PMC.× :Port mode control register PM×.×: Port mode register P×.×: Port output latch PMX.×: PMX register of the port 2. The relationship between pins and their alternate functions shown in this table indicates the relationship when a 64-pin product is used. In other products, alternate functions might be assigned to different pins, but even in this case, the PIOR.×, PMC×.×, PM×.×, and P×.× settings remain the same. 3. Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection register (PIOR). (The notes are described after the last table.) R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 168 RL78/F12 CHAPTER 4 PORT FUNCTIONS Table 4-14. Settings of Port Mode Register, and Output Latch When Using Alternate Function (3/5) Pin Name Alternate Function Function Name P15 P16 P17 P20 P21 Note 3 P30 P31 Remarks 1. PMC×.× PM×.× P×.× 0 − 1 × I/O SCK20 Input Output 0 − 0 1 SCL20 Output 0 − 0 1 (TI02) Input 1 − 1 × (TO02) Output 1 − 0 0 TI01 Input × − 1 × TO01 Output × − 0 0 INTP5 Input 0 − 1 × (RxD0) Input 1 − 1 × (SI00) Input 1 − 1 × TI02 Input 0 − 1 × TO02 Output 0 − 0 0 (TxD0) Output 1 − 0 1 (SO00) Output 1 − 0 1 ANI0 Input × − 1 × AVREFP Input × − 1 × ANI1 Input × − 1 × Input × − 1 × Input × − 1 × INTP3 Input × − 1 × RTC1HZ Output × − 0 0 SCK11 Input × − 1 × Output × − 0 1 SCL11 Output × − 0 1 TI03 Input 0 − 1 × TO03 Output 0 − 0 0 INTP4 Input × − 1 × (PCLBUZ0) Output 1 − 0 0 AVREFM P22 to P27 PIOR.× ANI2 to ANI7 ×: Note 3 don’t care PIOR.×: Peripheral I/O redirection register PMC×.×: Port mode control register PM×.×: Port mode register P×.×: 2. Port output latch The relationship between pins and their alternate functions shown in this table indicates the relationship when a 64-pin product is used. In other products, alternate functions might be assigned to different pins, but even in this case, the PIOR.×, PMC×.×, PM×.×, and P×.× settings remain the same. 3. Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection register (PIOR). (The notes are described after the last table.) R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 169 RL78/F12 CHAPTER 4 PORT FUNCTIONS Table 4-14. Settings of Port Mode Register, and Output Latch When Using Alternate Function (4/5) Pin Name Alternate Function Function Name PIOR.× PMC×.× PM×.× P×.× PMX.× PIEN × − − I/O P40 TOOL0 I/O × − × P41 TI07 Input 0 − 1 × − − TO07 Output 0 − 0 0 − − TI04 Input 0 − 1 × − − TO04 Output 0 − 0 0 − − INTP1 Input × − 1 × − − SI11 Input × − 1 × − − I/O × − 0 1 − − Input × − 1 × − − INTP2 Input × − 1 × 1 − SO11 Output × − 0 1 1 − Output × − 1 × 0 − 1 − 1 × − − P42 P50 Note 4 SDA11 LRxD0 P51 LTxD0 Note 2 P52 (INTP10) Input P53 SOS1 Output × − 1 × 0 − (INTP11) Input 1 − 1 × 1 − P54 SIS1 Input × − 1 × − 1 P55 SCKS1 Input × − 1 × 1 1 Output × − 1 × 0 × (PCLBUZ1) Output 1 − 0 0 1 × (SCK00) Input 1 − 1 × 1 × Output 1 − 0 1 1 × P60 SCLA0 I/O 0 − 0 0 − − P61 SDAA0 I/O 0 − 0 0 − − P70 KR0 Input × − 1 × − − SCK21 Input × − 1 × − − Output × − 0 1 − − SCL21 Output 0 − 0 1 − − Remarks 1. ×: don’t care PIOR.×: Peripheral I/O redirection register POM×.×: Port output mode register PMC×.×: Port mode control register PM×.×: Port mode register P×.×: Port output latch PMX.×: PMX register of the port PIEN: 2. Port input enable register The relationship between pins and their alternate functions shown in this table indicates the relationship when a 64-pin product is used. In other products, alternate functions might be assigned to different pins, but even in this case, the PIOR.×, PMC×.×, PM×.×, and P×.× settings remain the same. 3. Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection register (PIOR). (The notes are described after the last table.) R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 170 RL78/F12 CHAPTER 4 PORT FUNCTIONS Table 4-14. Settings of Port Mode Register, and Output Latch When Using Alternate Function (5/5) Pin Name Alternate Function Function Name PIOR.× PMC×.× PM×.× P×.× I/O KR1 Input × − 1 × SI21 Input × − 1 × I/O × − 0 1 KR2 Input × − 1 × SO21 Output × − 0 1 P73 KR3 Input × − 1 × SO01 Output × − 0 1 P74 KR4 Input × − 1 × INTP8 Input × − 1 × Input × − 1 × I/O × − 0 1 Input × − 1 × INTP9 Input × − 1 × SCK01 Input × − 1 × Output × − 0 1 SCL01 Output × − 0 1 KR6 Input × − 1 × INTP10 Input 0 − 1 × (RxD2) Input 1 − 1 × KR7 Input × − 1 × INTP11 Input 0 − 1 × (TxD2) Output 1 − 0 1 Input × 1 1 × P71 SDA21 P72 Note 4 SI01 SDA01 P75 Note 4 KR5 P76 P77 Note 1 P120 ANI19 P137 INTP0 Input × − − × P140 PCLBUZ0 Output 0 − 0 0 INTP6 Input × − 1 × PCLBUZ1 Output 0 − 0 0 Input × − 1 × Input × 1 1 × P141 INTP7 P147 ANI18 Remarks 1. Note 1 ×: don’t care PIOR.×: Peripheral I/O redirection register POM×.×: Port output mode register PMC×.×: Port mode control register PM×.×: Port mode register P×.×: 2. Port output latch The relationship between pins and their alternate functions shown in this table indicates the relationship when a 64-pin product is used. In other products, alternate functions might be assigned to different pins, but even in this case, the PIOR.×, PMC×.×, PM×.×, and P×.× settings remain the same. 3. Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 171 RL78/F12 CHAPTER 4 PORT FUNCTIONS Notes 1. The functions of the ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120 pins can be selected by using the port mode control registers 0, 12, 14 (PMC0, PMC12, PMC14), analog input channel specification register (ADS), and port mode registers 0, 3, 10, 11, 12, 14 (PM0, PM3, PM10, PM11, PM12, PM14). Table 4-15. Settings of Pins ANI16/P03, ANI17/P02, ANI18/P147, and ANI19/P120 PMC0, PMC12, PMC14 Registers Digital I/O selection Analog input selection PM0, PM12, PM14 Registers ADS Register ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120 Pins Input mode − Digital input Output mode − Digital output Input mode Output mode Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Selects ANI. Setting prohibited Does not select ANI. 2. To use P10/SCK00/SCKS0/SCL00, P12/SO00/TxD0/SOS0/TxDS0/TOOLTxD, P51/INTP2/SO11/LTxD, P53/SOS1, P55/SCKS1 as a SCKS0 output, SOS0 output, TxDS0 output, LTxD output, SOS1 output, or SCKS1 output set the PMX0 to PMX4 registers. See 4.3 (8) Port mode registers X (PMX0 to PMX4) for details. 3. The functions of the ANI0/P20 to ANI7/P27 pins can be selected by using the A/D port configuration register (ADPC), analog input channel specification register (ADS), and port mode register 2 (PM2). Table 4-16. Settings of Pins ANI0/P20 to ANI7/P27 ADPC Register Digital I/O selection PM2 Register ADS Register − Input mode − Output mode Analog input selection ANI0/P20 to ANI7/P27 Pins Digital input Digital output Input mode Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Output mode Selects ANI. Setting prohibited Does not select ANI. 4. To use a particular alternate output function of a pin to which multiple alternate output functions are assigned, outputs of unused alternate functions should be set to the same level as the initial state, in addition to the settings in Table 4-15. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 172 RL78/F12 CHAPTER 4 PORT FUNCTIONS 4.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode. When P10 is an output port, P11 to P17 are input ports (all pin statuses are high level), and the port latch value of port 1 is 00H, if the output of output port P10 is changed from low level to high level via a 1-bit manipulation instruction, the output latch value of port 1 is FFH. Explanation: The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output latch and pin status, respectively. A 1-bit manipulation instruction is executed in the following order in the RL78/F12. The Pn register is read in 8-bit units. The targeted one bit is manipulated. The Pn register is written in 8-bit units. In step , the output latch value (0) of P10, which is an output port, is read, while the pin statuses of P11 to P17, which are input ports, are read. If the pin statuses of P11 to P17 are high level at this time, the read value is FEH. The value is changed to FFH by the manipulation in . FFH is written to the output latch by the manipulation in . Figure 4-51. Bit Manipulation Instruction (P10) 1-bit manipulation instruction (set1 P1.0) is executed for P1.0 bit. P10 Low-level output P11 to P16 P10 High-level output P11 to P16 Pin status: High-level Port 1 output latch 0 0 0 Pin status: High-level Port 1 output latch 0 0 0 0 0 0 1 1 1 1 1 1 1 1-bit manipulation instruction for P1.0 bit Port register 1 (P1) is read in 8-bit units. • In the case of P10, an output port, the value of the port output latch (0) is read. • In the case of P11 to P16, input ports, the pin status (1) is read. Set the P1.0 bit to 1. Write the results of to the output latch of port register 1 (P1) in 8-bit units. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 173 RL78/F12 CHAPTER 5 CLOCK GENERATOR CHAPTER 5 CLOCK GENERATOR The presence or absence of connecting resonator pin for main system clock, connecting resonator pin for subsystem clock, external clock input pin for main system clock, and external clock input pin for subsystem clock, depends on the product. Output pin 20, 30, 32-pin 48, 64-pin X1, X2 pins √ √ EXCLK pin √ √ XT1, XT2 pins − √ EXCLKS pin − √ Caution The 20, 30, and 32-pin products don’t have the subsystem clock. 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three kinds of system clocks and clock oscillators are selectable. (1) Main system clock X1 oscillator This circuit oscillates a clock of fX = 1 to 20 MHz by connecting a resonator to X1 and X2. Oscillation can be stopped by executing the STOP instruction or setting of the MSTOP bit (bit 7 of the clock operation status control register (CSC)). High-speed on-chip oscillator The frequency at which to oscillate can be selected from among fIH = 32, 24, 16, 12, 8, 4, or 1 MHz (typ.) by using the option byte (000C2H). After a reset release, the CPU always starts operating with this high-speed on-chip oscillator clock. Oscillation can be stopped by executing the STOP instruction or setting the HIOSTOP bit (bit 0 of the CSC register). The frequency set by the option byte can be changed by using the high-speed on-chip oscillator frequency select register (HOCODIV). For the frequency, see Figure 5-9 Format of High-Speed On-Chip Oscillator Frequency Select Register (HOCODIV). The table below shows the oscillation frequencies that can be set for the high-speed on-chip oscillator (the variations selectable using the option byte and the high-speed on-chip oscillator frequency select register (HOCODIV). Oscillation frequency (MHz) Power supply voltage 1 2 3 4 6 8 12 16 24 32 2.7V ≤ VDD ≤ 5.5V √ √ √ √ √ √ √ √ √ √ 1.8V ≤ VDD < 2.7V √ √ √ √ √ √ − − − − An external main system clock (fEX = 1 to 20 MHz) can also be supplied from the EXCLK/X2/P122 pin. An external main system clock input can be disabled by executing the STOP instruction or setting of the MSTOP bit. As the main system clock, a high-speed system clock (X1 clock or external main system clock) or high-speed onchip oscillator clock can be selected by setting of the MCM0 bit (bit 4 of the system clock control register (CKC)). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 174 RL78/F12 CHAPTER 5 CLOCK GENERATOR (2) Subsystem clock • XT1 clock oscillator This circuit oscillates a clock of fXT = 32.768 kHz by connecting a 32.768 kHz resonator to XT1 and XT2. Oscillation can be stopped by setting the XTSTOP bit (bit 6 of the clock operation status control register (CSC)). An external subsystem clock (fEXS = 32.768 KHz) can also be supplied from the EXCLKS/XT2/P124 pin. An external subsystem clock input can be disabled by setting the XTSTOP bit. (3) Low-speed on-chip oscillator clock This circuit oscillates a clock of fIL = 15 kHz (TYP.). The low-speed on-chip oscillator clock cannot be used as the CPU clock. Only the following peripheral hardware runs on the low-speed on-chip oscillator clock. • Watchdog timer • Real-time clock • Interval timer This clock operates when bit 4 (WDTON) of the option byte (000C0H), bit 4 (WUTMMCK0) of the operation speed mode control register (OSMC), or both are set to 1. However, when WDTON = 1, WUTMMCK0 = 0, and bit 0 (WDSTBYON) of the option byte (000C0H) is 0, oscillation of the low-speed on-chip oscillator stops if the HALT or STOP instruction is executed. Caution The low-speed on-chip oscillator clock (fIL) can be selected as the real-time clock operation clock only when the fixed-cycle interrupt function is used. Remark fX: X1 clock oscillation frequency fIH: High-speed on-chip oscillator clock frequency fEX: External main system clock frequency fXT: XT1 clock oscillation frequency fEXS: External subsystem clock frequency fIL: Low-speed on-chip oscillator clock frequency R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 175 RL78/F12 CHAPTER 5 CLOCK GENERATOR 5.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 5-1. Configuration of Clock Generator Item Control registers Configuration Clock operation mode control register (CMC) System clock control register (CKC) Clock operation status control register (CSC) Oscillation stabilization time counter status register (OSTC) Oscillation stabilization time select register (OSTS) Peripheral enable register 0 (PER0) Peripheral enable register X (PERX) Operation speed mode control register (OSMC) High-speed on-chip oscillator frequency select register (HOCODIV) High-speed on-chip oscillator trimming register (HIOTRM) Oscillators R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 X1 oscillator XT1 oscillator High-speed on-chip oscillator Low-speed on-chip oscillator 176 External input clock Crystal/ceramic oscillation fSUB fIH fMX STOP mode signal CLS Low-speed on-chip oscillator fIL 15 kHz (TYP.) MSTOP High-speed on-chip oscillator frequency select register (HOCODIV) (Remark is listed on the next page after next.) Clock operation mode control register (CMC) fEXS fXT fEX fX Clock operation status control register (CSC) Clock operation status control register (CSC) EXCLKS OSCSELS HOCODIV.2 HOCODIV.1 HOCODIV.0 XTSTOP HIOSTOP External input clock Crystal oscillation Subsystem clock oscillator 4 MHz (TYP.) 8 MHz (TYP.) AMPHS1 AMPHS0 XT2/EXCLKS /P124 XT1/P123 12 MHz (TYP.) 16 MHz (TYP.) 1 MHz (TYP.) 24MHz (TYP.) 32 MHz (TYP.) High-speed on-chip oscillator Option byte (000C2H) FRQSEL0 to FRQSEL3 X2/EXCLK /P122 X1/P121 High-speed High-speedsystem system clock clockoscillator oscillator AMPH EXCLK OSCSEL Clock operation mode control register (CMC) 6 Controller Internal bus High-speed on-chip oscillator trimming register(HIOTRM) RTC EN Real-time clock, Interval timer HIOTRM.5 HIOTRM.4 HIOTRM.3 HIOTRM.2 HIOTRM.1 HIOTRM.0 Selector HALT/STOP mode signal Option byte (000C0H) WDTON WDSTBYON Main system clock source selector Oscillation stabilization time counter status register (OSTC) MOST MOST MOST MOST MOST MOST MOST MOST 8 9 10 11 13 15 17 18 X1 oscillation stabilization time counter 3 OSTS.2 OSTS.1 OSTS.0 Oscillation stabilization time select register (OSTS) Internal bus IICA1 EN fMAIN ADC EN IICA0 EN SAU0 EN TAU0 EN Clock output/buzzer output Wakeup timer Peripheral enable register 0 (PER0) SAU1 EN CPU clock and peripheral hardware clock source selection Watchdog timer Wakeup timer CSS MCS MCM0 Clock output/ buzzer output Wakeup timer CLS System clock control register (CKC) fCLK UF0 EN CPU Normal operation mode HALT mode STOP mode Standby controller Controller R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 SAUS EN LIN-UART Serial array unit S Wakeup timer Peripheral enable register X (PERX) WUT EN A/D converter Serial array unit 1 Serial interface IICA Serial array unit 0 Timer array unit Controller Figure 5-1. Block Diagram of Clock Generator RL78/F12 CHAPTER 5 CLOCK GENERATOR 177 RL78/F12 Remark CHAPTER 5 CLOCK GENERATOR fX: X1 clock oscillation frequency fIH: High-speed on-chip oscillator clock frequency fEX: External main system clock frequency fMX: High-speed system clock frequency fMAIN: Main system clock frequency fXT: XT1 clock oscillation frequency fEXS: External subsystem clock frequency fSUB: Subsystem clock frequency fCLK: CPU/peripheral hardware clock frequency fIL: Low-speed on-chip oscillator clock frequency 5.3 Registers Controlling Clock Generator The following ten registers are used to control the clock generator. • Clock operation mode control register (CMC) • System clock control register (CKC) • Clock operation status control register (CSC) • Oscillation stabilization time counter status register (OSTC) • Oscillation stabilization time select register (OSTS) • Peripheral enable register 0 (PER0) • Peripheral enable register X (PERX) • Operation speed mode control register (OSMC) • High-speed on-chip oscillator frequency select register (HOCODIV) • High-speed on-chip oscillator trimming register (HIOTRM) 5.3.1 Clock operation mode control register (CMC) This register is used to set the operation mode of the X1/P121, X2/EXCLK/P122, XT1/P123, and XT2/EXCLKS/P124 pins, and to select a gain of the oscillator. The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release. This register can be read by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 178 RL78/F12 CHAPTER 5 CLOCK GENERATOR Figure 5-2. Format of Clock Operation Mode Control Register (CMC) Address: FFFA0H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CMC EXCLK OSCSEL EXCLKS OSCSELS 0 AMPHS1 AMPHS0 AMPH EXCLK OSCSEL High-speed system clock pin operation mode 0 0 Input port mode Input port 0 1 X1 oscillation mode Crystal/ceramic resonator connection 1 0 Input port mode Input port 1 1 External clock input mode Input port EXCLKS OSCSELS Subsystem clock pin operation mode 0 0 XT1/P123 pin Input port mode Input port X2/EXCLK/P122 pin External clock input XT2/EXCLKS/P124 pin 0 1 XT1 oscillation mode Crystal/ceramic resonator connection 1 0 Input port mode Input port 1 1 External clock input mode Input port AMPHS1 AMPHS0 0 0 Low power consumption oscillation (default) 0 1 Normal oscillation 1 0 Ultra-low power consumption oscillation 1 1 Setting prohibited External clock input XT1 oscillator oscillation mode selection AMPH X1/P121 pin Control of X1 clock oscillation frequency 0 1 MHz ≤ fX ≤ 10 MHz 1 1 MHz ≤ fX ≤ 20 MHz Cautions 1. The CMC register can be written only once after reset release, by an 8-bit memory manipulation instruction. 2. After reset release, set the CMC register before X1 or XT1 oscillation is started as set by the clock operation status control register (CSC). 3. Be sure to set the AMPH bit to 1 if the X1 clock oscillation frequency exceeds 10 MHz. Also, if the X1 clock is oscillating at a frequency in the range from 1 to (but not including) 10 MHz, the margin of oscillation can be improved by setting the AMPH bit to 1. 4. When the CMC register is used at the default value (00H), be sure to set 00H to this register after reset release in order to prevent malfunctioning during a program loop. (Cautions and Remark are given on the next page.) R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 179 RL78/F12 CHAPTER 5 CLOCK GENERATOR 5. The XT1 oscillator is a circuit with low amplification in order to achieve low-power consumption. Note the following points when designing the circuit. • Pins and circuit boards include parasitic capacitance. Therefore, perform oscillation evaluation using a circuit board to be actually used and confirm that there are no problems. • When using the ultra-low power consumption oscillation (AMPHS1, AMPHS0 = 1, 0) as the mode of the XT1 oscillator, use the recommended resonators described in CHAPTER 31 ELECTRICAL SPECIFICATIONS (J GRADE) and CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE). • Make the wiring between the XT1 and XT2 pins and the resonators as short as possible, and minimize the parasitic capacitance and wiring resistance. Note this particularly when the ultra-low power consumption oscillation (AMPHS1, AMPHS0 = 1, 0) is selected. • Configure the circuit of the circuit board, using material with little wiring resistance. • Place a ground pattern that has the same potential as VSS as much as possible near the XT1 oscillator. • Be sure that the signal lines between the XT1 and XT2 pins, and the resonators do not cross with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. • The impedance between the XT1 and XT2 pins may drop and oscillation may be disturbed due to moisture absorption of the circuit board in a high-humidity environment or dew condensation on the board. When using the circuit board in such an environment, take measures to damp-proof the circuit board, such as by coating. • When coating the circuit board, use material that does not cause capacitance or leakage between the XT1 and XT2 pins. 6. Set the AMPH, AMPHS1, and AMPHS0 bits while fIH is selected as fCLK (before changing fCLK to FMX) after a reset release. 7. Count the oscillation stabilization time of fXT by software. 8. Though the maximum frequency of the system clock is 32 MHz, the maximum frequency of the X1 oscillation circuit is 20 MHz. Remark fX: X1 clock frequency R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 180 RL78/F12 CHAPTER 5 CLOCK GENERATOR 5.3.2 System clock control register (CKC) This register is used to select a CPU/peripheral hardware clock and a division ratio. The CKC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 5-3. Format of System Clock Control Register (CKC) Address: FFFA4H After reset: 00H R/W Note 1 Symbol 3 2 1 0 CKC CLS CSS MCS MCM0 0 0 0 0 CLS Status of CPU/peripheral hardware clock (fCLK) 0 Main system clock (fMAIN) 1 Subsystem clock (fSUB) CSS Selection of CPU/peripheral hardware clock (fCLK) 0 Main system clock (fMAIN) 1 Subsystem clock (fSUB) MCS Status of Main system clock (fMAIN) 0 High-speed on-chip oscillator clock (fIH) 1 High-speed system clock (fMX) MCM0 Main system clock (fMAIN) operation control 0 Selects the high-speed on-chip oscillator clock (fIH) as the main system clock (fMAIN) 1 Selects the high-speed system clock (fMX) as the main system clock (fMAIN) Notes 1. Bits 7 and 5 are read-only. 2. Changing the value of the MCM0 bit is prohibited while the CSS bit is set to 1. Remarks 1. fIH: High-speed on-chip oscillator clock frequency fMX: High-speed system clock frequency fMAIN: Main system clock frequency fSUB: Subsystem clock frequency (Cautions are listed on the next page.) R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 181 RL78/F12 CHAPTER 5 CLOCK GENERATOR Cautions 1. Be sure to set 0 in bits 3 to 0. 2. The clock set by the CSS bit is supplied to the CPU and peripheral hardware. If the CPU clock is changed, therefore, the clock supplied to peripheral hardware (except the real-time clock, interval timer, clock output/buzzer output, and watchdog timer) is also changed at the same time. Consequently, stop each peripheral function when changing the CPU/peripheral hardware clock. 3. If the subsystem clock is used as the peripheral hardware clock, the operations of the A/D converter and IICA are not guaranteed. For the operating characteristics of the peripheral hardware, refer to the chapters describing the various peripheral hardware as well as CHAPTER 31 ELECTRICAL SPECIFICATIONS (J GRADE) and CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 182 RL78/F12 CHAPTER 5 CLOCK GENERATOR 5.3.3 Clock operation status control register (CSC) This register is used to control the operations of the high-speed system clock, high-speed on-chip oscillator clock, and subsystem clock (except the low-speed on-chip oscillator clock). The CSC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to C0H. Figure 5-4. Format of Clock Operation Status Control Register (CSC) Address: FFFA1H After reset: C0H R/W Symbol 5 4 3 2 1 CSC MSTOP XTSTOP 0 0 0 0 0 HIOSTOP MSTOP High-speed system clock operation control X1 oscillation mode External clock input mode 0 X1 oscillator operating External clock from EXCLK pin is valid 1 X1 oscillator stopped External clock from EXCLK pin is invalid XTSTOP Input port mode Input port Subsystem clock operation control XT1 oscillation mode External clock input mode 0 XT1 oscillator operating External clock from EXCLKS pin is valid 1 XT1 oscillator stopped External clock from EXCLKS pin is invalid HIOSTOP Input port mode Input port High-speed on-chip oscillator clock operation control 0 High-speed on-chip oscillator operating 1 High-speed on-chip oscillator stopped Cautions 1. After reset release, set the clock operation mode control register (CMC) before setting the CSC register. 2. Set the oscillation stabilization time select register (OSTS) before setting the MSTOP bit to 0 after releasing reset. Note that if the OSTS register is being used with its default settings, the OSTS register is not required to be set here. 3. To start X1 oscillation as set by the MSTOP bit, check the oscillation stabilization time of the X1 clock by using the oscillation stabilization time counter status register (OSTC). 4. When starting XT1 oscillation by setting the XSTOP bit, wait for oscillation of the subsystem clock to stabilize by setting a wait time using software. 5. Do not stop the clock selected as clock (fCLK) of the CPU or the peripheral hardware with the CSC register. 6. The setting of the flags of the register to stop clock oscillation (invalidate the external clock input) and the condition before clock oscillation is to be stopped are as Table 5-2. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 183 RL78/F12 CHAPTER 5 CLOCK GENERATOR Table 5-2. Condition Before Stopping Clock Oscillation and Flag Setting Clock X1 clock External main system clock XT1 clock External subsystem clock High-speed on-chip oscillator clock Condition Before Stopping Clock (Invalidating External Clock Input) CPU and peripheral hardware clocks operate with a clock other than the high-speed system clock. Setting of CSC Register Flags MSTOP = 1 (CLS = 0 and MCS = 0, or CLS = 1) CPU and peripheral hardware clocks operate with a clock other than the subsystem clock. XTSTOP = 1 (CLS = 0) CPU and peripheral hardware clocks operate with a clock other than the high-speed on-chip oscillator clock. HIOSTOP = 1 (CLS = 0 and MCS = 1, or CLS = 1) 5.3.4 Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. The X1 clock oscillation stabilization time can be checked in the following case, • If the X1 clock starts oscillation while the high-speed on-chip oscillator clock or subsystem clock is being used as the CPU clock. • If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as the CPU clock with the X1 clock oscillating. The OSTC register can be read by a 1-bit or 8-bit memory manipulation instruction. When reset signal is generated, the STOP instruction and MSTOP (bit 7 of clock operation status control register (CSC)) = 1 clear the OSTC register to 00H. Remark The oscillation stabilization time counter starts counting in the following cases. • When oscillation of the X1 clock starts (EXCLK, OSCSEL = 0, 1 → MSTOP = 0) • When the STOP mode is released R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 184 RL78/F12 CHAPTER 5 CLOCK GENERATOR Figure 5-5. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFFA2H Symbol OSTC After reset: 00H 7 6 5 R 4 3 2 1 0 MOST MOST MOST MOST MOST MOST MOST MOST 8 9 10 11 13 15 17 18 MOST MOST MOST MOST MOST MOST MOST MOST 8 9 10 11 13 15 17 18 Oscillation stabilization time status fX = 10 MHz fX = 20 MHz 0 0 0 0 0 0 0 0 2 /fX max. 25.6 μs max. 12.8 μs max. 1 0 0 0 0 0 0 0 2 /fX min. 8 8 25.6 μs min. 12.8 μs min. 9 51.2 μs min. 25.6 μs min. 1 1 0 0 0 0 0 0 2 /fX min. 1 1 1 0 0 0 0 0 2 /fX min. 102.4 μs min. 51.2 μs min. 1 1 1 1 0 0 0 0 2 /fX min. 204.8 μs min. 102.4 μs min. 1 1 1 1 1 0 0 0 2 /fX min. 819.2 μs min. 409.6 μs min. 1 1 1 1 1 1 0 0 2 /fX min. 3.27 ms min. 1.64 ms min. 1 1 1 1 1 1 1 0 2 /fX min. 13.11 ms min. 6.55 ms min. 1 1 1 1 1 1 1 1 2 /fX min. 26.21 ms min. 13.11 ms min. 10 11 13 15 17 18 Cautions 1. After the above time has elapsed, the bits are set to 1 in order from the MOST8 bit and remain 1. 2. The oscillation stabilization time counter counts up to the oscillation stabilization time set by the oscillation stabilization time select register (OSTS). In the following cases, set the oscillation stabilization time of the OSTS register to the value greater than the count value which is to be checked by the OSTC register after the oscillation starts. • If the X1 clock starts oscillation while the high-speed on-chip oscillator clock or subsystem clock is being used as the CPU clock. • If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as the CPU clock with the X1 clock oscillating. (Note, therefore, that only the status up to the oscillation stabilization time set by the OSTS register is set to the OSTC register after the STOP mode is released.) 3. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts (“a” below). STOP mode release X1 pin voltage waveform a Remark fX: X1 clock oscillation frequency R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 185 RL78/F12 CHAPTER 5 CLOCK GENERATOR 5.3.5 Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation automatically waits for the time set using the OSTS register after the STOP mode is released. When the high-speed on-chip oscillator clock is selected as the CPU clock, confirm with the oscillation stabilization time counter status register (OSTC) that the desired oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can be checked up to the time set using the OSTC register. The OSTS register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets the OSTS register to 07H. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 186 RL78/F12 CHAPTER 5 CLOCK GENERATOR Figure 5-6. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFFA3H After reset: 07H R/W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS.2 OSTS.1 OSTS.0 OSTS.2 OSTS.1 OSTS.0 0 0 0 2 /fX 0 0 1 2 /fX 0 1 0 2 /fX 0 1 1 2 /fX Oscillation stabilization time selection fX = 10 MHz 51.2 μs 25.6 μs 10 102.4 μs 51.2 μs 11 204.8 μs 102.4 μs 13 819.2 μs 409.6 μs 15 3.27 ms 1.64 ms 17 13.11 ms 6.55 ms 18 26.21 ms 13.11 ms 0 0 2 /fX 1 0 1 2 /fX 1 1 0 2 /fX 1 1 fX = 20 MHz Setting prohibited 9 1 1 25.6 μs 8 2 /fX Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set the OSTS register before executing the STOP instruction. 2. Setting the oscillation stabilization time to 20 μs or less is prohibited. 3. Change the setting of the OSTS register before setting the MSTOP bit of the clock operation status control register (CSC) to 0. 4. Do not change the value of the OSTS register during the X1 clock oscillation stabilization time. 5. The oscillation stabilization time counter counts up to the oscillation stabilization time set by the OSTS register. In the following cases, set the oscillation stabilization time of the OSTS register to the value greater than the count value which is to be checked by the OSTC register after the oscillation starts. • If the X1 clock starts oscillation while the high-speed on-chip oscillator clock or subsystem clock is being used as the CPU clock. • If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as the CPU clock with the X1 clock oscillating. (Note, therefore, that only the status up to the oscillation stabilization time set by the OSTS register is set to the OSTC register after the STOP mode is released.) 6. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts (“a” below). STOP mode release X1 pin voltage waveform a Remark fX: X1 clock oscillation frequency R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 187 RL78/F12 CHAPTER 5 CLOCK GENERATOR 5.3.6 Peripheral enable register 0 (PER0) These registers are used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise. To use the peripheral functions below, which are controlled by this register, set (1) the bit corresponding to each function before specifying the initial settings of the peripheral functions. • Real-time clock, Interval timer • A/D converter • Serial interface IICA • Serial array unit 0 • Serial array unit 1 • Timer array unit The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (1/2) Address: F00F0H After reset: 00H R/W Symbol 6 1 PER0 RTCEN 0 ADCEN IICA0EN SAU1EN SAU0EN 0 TAU0EN RTCEN 0 Control of real-time clock (RTC) and interval timer input clock supply Note Stops input clock supply. • SFR used by the real-time clock (RTC) and interval timer cannot be written. • The real-time clock (RTC) and interval timer are in the reset status. 1 Enables input clock supply. • SFR used by the real-time clock (RTC) and interval timer can be read and written. ADCEN 0 Control of A/D converter input clock supply Stops input clock supply. • SFR used by the A/D converter cannot be written. • The A/D converter is in the reset status. 1 Enables input clock supply. • SFR used by the A/D converter can be read and written. IICA0EN 0 Control of serial interface IICA input clock supply Stops input clock supply. • SFR used by the serial interface IICA cannot be written. • The serial interface IICA is in the reset status. 1 Enables input clock supply. • SFR used by the serial interface IICA can be read and written. Note The input clock that can be controlled by the RTCEN bit is used when the register that is used by the real-time clock (RTC) is accessed from the CPU. The RTCEN bit cannot control supply of the operating clock (fSUB) to RTC. Caution Be sure to clear bits 1 and 6 to 0. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 188 RL78/F12 CHAPTER 5 CLOCK GENERATOR Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (2/2) Address: F00F0H After reset: 00H R/W Symbol 6 1 PER0 RTCEN 0 ADCEN IICA0EN SAU1EN SAU0EN 0 TAU0EN SAU1EN 0 Control of serial array unit 1 input clock supply Stops input clock supply. • SFR used by the serial array unit 1 cannot be written. • The serial array unit 1 is in the reset status. 1 Enables input clock supply. • SFR used by the serial array unit 1 can be read and written. SAU0EN 0 Control of serial array unit 0 input clock supply Stops input clock supply. • SFR used by the serial array unit 0 cannot be written. • The serial array unit 0 is in the reset status. 1 Enables input clock supply. • SFR used by the serial array unit 0 can be read and written. TAU0EN 0 Control of timer array unit input clock supply Stops input clock supply. • SFR used by timer array unit cannot be written. • Timer array unit is in the reset status. 1 Enables input clock supply. • SFR used by timer array unit can be read and written. Caution Be sure to clear bits 1 and 6 to 0. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 189 RL78/F12 CHAPTER 5 CLOCK GENERATOR 5.3.7 Peripheral enable register X (PERX) This register is used to enable or disable use of each peripheral hardware macro. Clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise. PERX can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Caution Whether to enable or disable SFR writing only is selected for the 16-bit wakeup timer. Whether to enable or disable supplying the operating clock is selected using the PCKSEL register. Figure 5-8. Format of Peripheral Enable Register X (PERX) Address: F0500H After reset: 00H R/W Symbol 7 6 5 4 3 PERX 0 0 0 0 0 UF0EN SAUSEN WUTEN UF0EN 0 LIN-UART0 input clock control Stops input clock supply. • Writing to SFR to be used with LIN-UART0 is disabled. • LIN-UART0 is in reset state. 1 Supplies input clock. • Reading from and writing to SFR to be used with LIN-UART0 is enabled. SAUmEN 0 Control of serial array unit m input clock supply (m = 0, 1, S) Stops supply of input clock. • SFR used by serial array unit m cannot be written. • Serial array unit m is in the reset status. 1 Enables input clock supply. • SFR used by serial array unit m can be read/written. WUTEN Control of 16-bit wakeup timer input clock 0 Stops input clock supply for SFR writing. 1 Supplies input clock for SFR writing . • SFR used by the 16-bit wakeup timer cannot be written. • SFR used by the 16-bit wakeup timer can be written. Caution R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 Be sure to clear the bits 3 to 7 of the PERX register to 0. 190 RL78/F12 CHAPTER 5 CLOCK GENERATOR 5.3.8 High-speed on-chip oscillator frequency select register (HOCODIV) The frequency of the high-speed on-chip oscillator which is set by an option byte.(000C2H/0102CH) can be changed by using high-speed on-chip oscillator frequency select register (HOCODIV). However, the selectable frequency depends on the FRQSEL3 bit of the option byte (000C2H/0102CH). The HOCODIV register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to default value (undefined). Figure 5-9. Format of High-Speed On-Chip Oscillator Frequency Select Register (HOCODIV) Address: F00A8H After reset: Undefined R/W Symbol 7 6 5 4 3 2 1 0 HOCODIV 0 0 0 0 0 HOCODIV.2 HOCODIV.1 HOCODIV.0 HOCODIV.2 HOCODIV.1 HOCODIV.0 0 0 Selection of High-Speed On-Chip Oscillator Clock Frequency FRQSEL3 Bit is 0 FRQSEL3 Bit of is 1 0 24 MHz 32 MHz 16 MHz 0 0 1 12 MHz 0 1 0 6 MHz 8 MHz 0 1 1 3 MHz 4 MHz 1 0 0 Setting prohibited 2 MHz 1 0 1 Setting prohibited 1 MHz Setting prohibited Other than above Caution 1. Set the HOCODIV register within the operable voltage range both before and after changing the frequency. 2. Use the device within the voltage of the flash operation mode set by the option byte (000C2H/010C2H) even after the frequency has been changed by using the HOCODIV register. Flash Operation Mode Option Byte (000C2H/010C2H) Value CMODE1 CMODE0 1 0 LS (low-speed main) Operating Frequency Operating Voltage Range Range 1 to 8 MHz 1.8 to 5.5 V 1 to 32 MHz 2.7 to 5.5 V mode 1 1 HS (high-speed main) mode 3. The device operates at the old frequency for the duration of 3 clocks after the frequency value has been changed by using the HOCODIV register. Moreover, when the high-speed on-chip oscillator clock is selected as the system clock, the device waits for the oscillation to stabilize for an additional duration of 3 clocks, 4. To change the frequency of the high-speed on-chip oscillator when X1 oscillation, external oscillation input or subclock is set for the system clock, stop the highspeed on-chip oscillator by setting bit 0 (HIOSTOP) of the CSC register to 1 and then change the frequency. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 191 RL78/F12 CHAPTER 5 CLOCK GENERATOR 5.3.9 Operation speed mode control register (OSMC) This register is used to reduce power consumption by stopping as many unnecessary clock functions as possible. If the RTCLPC bit is set to 1, current consumption can be reduced, because the circuit that synchronizes the clock to the peripheral functions, except the real-time clock and interval timer, is stopped in STOP mode or HALT mode while subsystem clock is selected as CPU clock. Before setting the RTCLPC bit to 1, set bit 7 (RTCEN) of the peripheral enable register 0 (PER0) to 1. In addition, the OSMC register can be used to select the operation clock of the real-time clock and interval timer. The OSMC register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 5-10. Format of Operation Speed Mode Control Register (OSMC) Address: F00F3H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 OSMC RTCLPC 0 0 WUTMMCK0 0 0 0 0 RTCLPC 0 Setting in STOP mode or HALT mode while subsystem clock is selected as CPU clock Enables supply of subsystem clock to peripheral functions (See Table 20-1. Operating Statuses in HALT Mode for peripheral functions whose operations are enabled.) Stops supply of subsystem clock to peripheral functions other than real-time clock and 1 interval timer. WUTMMCK0 Selection of operation clock for real-time clock and interval timer. 0 Subsystem clock 1 Low-speed on-chip oscillator clock Caution The STOP mode current or HALT mode current when the subsystem clock is used can be reduced by setting the RTCLPC bit to 1. However, no clock can be supplied to the peripheral functions other than the real-time clock and interval timer during HALT mode while subsystem clock is selected as CPU clock. Set bit 7 (RTCEN) of peripheral enable registers 0 (PER0), to 1, and bits 0 to 6 of the PER0 register to 0 before setting subsystem clock HALT mode. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 192 RL78/F12 CHAPTER 5 CLOCK GENERATOR 5.3.10 High-speed on-chip oscillator trimming register (HIOTRM) This register is used to adjust the accuracy of the high-speed on-chip oscillator. The HIOTRM register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to default value Note. Figure 5-11. Format of High-Speed On-Chip Oscillator Trimming Register (HIOTRM) Address: F00A0H After reset: See Note. R/W Symbol 7 6 5 4 3 2 1 0 HIOTRM 0 0 HIOTRM.5 HIOTRM.4 HIOTRM.3 HIOTRM.2 HIOTRM.1 HIOTRM.0 HIOTRM.5 HIOTRM.4 HIOTRM.3 HIOTRM.2 HIOTRM.1 HIOTRM.0 High-speed on-chip oscillator 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 0 0 Minimum speed • • • 1 1 1 1 1 0 1 1 1 1 1 1 Maximum speed Note The reset value depends on the individual chip. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 193 RL78/F12 CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin. To use the X1 oscillator, set bits 7 and 6 (EXCLK, OSCSEL) of the clock operation mode control register (CMC) as follows. • Crystal or ceramic oscillation: EXCLK, OSCSEL = 0, 1 • External clock input: EXCLK, OSCSEL = 1, 1 When the X1 oscillator is not used, set the input port mode (EXCLK, OSCSEL = 0, 0). When the pins are not used as input port pins, either, see Table 2-2 Connection of Unused Pins. Figure 5-10 shows an example of the external circuit of the X1 oscillator. Figure 5-12. Example of External Circuit of X1 Oscillator (a) Crystal or ceramic oscillation (b) External clock VSS X1 X2 External clock EXCLK Crystal resonator or ceramic resonator Cautions are listed on the next page. 5.4.2 XT1 oscillator The XT1 oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. To use the XT1 oscillator, set bit 4 (OSCSELS) of the clock operation mode control register (CMC) to 1. An external clock can also be input. In this case, input the clock signal to the EXCLKS pin. To use the XT1 oscillator, set bits 5 and 4 (EXCLKS, OSCSELS) of the clock operation mode control register (CMC) as follows. • Crystal or ceramic oscillation: EXCLKS, OSCSELS = 0, 1 • External clock input: EXCLKS, OSCSELS = 1, 1 When the XT1 oscillator is not used, set the input port mode (EXCLKS, OSCSELS = 0, 0). When the pins are not used as input port pins, either, see Table 2-2 Connection of Unused Pins. Figure 5-13 shows an example of the external circuit of the XT1 oscillator. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 194 RL78/F12 CHAPTER 5 CLOCK GENERATOR Figure 5-13. Example of External Circuit of XT1 Oscillator (a) Crystal or ceramic oscillation (b) External clock VSS XT1 32.768 kHz XT2 Caution External clock EXCLKS When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in the Figures 5-10 and 5-11 to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. The XT1 oscillator is a circuit with low amplification in order to achieve low-power consumption. Note the following points when designing the circuit. • Pins and circuit boards include parasitic capacitance. Therefore, perform oscillation evaluation using a circuit board to be actually used and confirm that there are no problems. • When using the ultra-low power consumption oscillation (AMPHS1, AMPHS0 = 1, 0) as the mode of the XT1 oscillator, use the recommended resonators described in CHAPTER 31 ELECTRICAL SPECIFICATIONS (J GRADE) and CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE). • Make the wiring between the XT1 and XT2 pins and the resonators as short as possible, and minimize the parasitic capacitance and wiring resistance. Note this particularly when the ultralow power consumption oscillation (AMPHS1, AMPHS0 = 1, 0) is selected. • Configure the circuit of the circuit board, using material with little wiring resistance. • Place a ground pattern that has the same potential as VSS as much as possible near the XT1 oscillator. • Be sure that the signal lines between the XT1 and XT2 pins, and the resonators do not cross with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. • The impedance between the XT1 and XT2 pins may drop and oscillation may be disturbed due to moisture absorption of the circuit board in a high-humidity environment or dew condensation on the board. When using the circuit board in such an environment, take measures to damp-proof the circuit board, such as by coating. • When coating the circuit board, use material that does not cause capacitance or leakage between the XT1 and XT2 pins. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 195 RL78/F12 CHAPTER 5 CLOCK GENERATOR Figure 5-14 shows examples of incorrect resonator connection. Figure 5-14. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT VSS X1 X2 VSS X1 X2 NG NG NG (c) The X1 and X2 signal line wires cross. (d) A power supply/GND pattern exists under the X1 and X2 wires. VSS VSS X1 X1 X2 X2 Note Power supply/GND pattern Note Do not place a power supply/GND pattern under the wiring section (section indicated by a broken line in the figure) of the X1 and X2 pins and the resonators in a multi-layer board or double-sided board. Do not configure a layout that will cause capacitance elements and affect the oscillation characteristics. Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 196 RL78/F12 CHAPTER 5 CLOCK GENERATOR Figure 5-14. Examples of Incorrect Resonator Connection (2/2) (e) Wiring near high alternating current (f) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) VDD Pmn X1 X2 High current VSS VSS A X1 B X2 C High current (g) Signals are fetched VSS Caution X1 X2 When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in malfunctioning. Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 197 RL78/F12 CHAPTER 5 CLOCK GENERATOR 5.4.3 High-speed on-chip oscillator The high-speed on-chip oscillator is incorporated in the RL78/F12. The frequency can be selected from among 32, 24, 16, 12, 8, 4, or 1 MHz by using the option byte (000C2H). Oscillation can be controlled by bit 0 (HIOSTOP) of the clock operation status control register (CSC). The high-speed on-chip oscillator automatically starts oscillating after reset release. 5.4.4 Low-speed on-chip oscillator The low-speed on-chip oscillator is incorporated in the RL78/F12. The low-speed on-chip oscillator clock is used only as the watchdog timer, real-time clock, and interval timer clock. The low-speed on-chip oscillator clock cannot be used as the CPU clock. This clock operates when bit 4 (WDTON) of the option byte (000C0H), bit 4 (WUTMMCK0) of the operation speed mode control register (OSMC), or both are set to 1. Unless the watchdog timer is stopped and WUTMMCK0 is a value other than zero, oscillation of the low-speed on-chip oscillator continues. While the watchdog timer operates, the low-speed on-chip oscillator clock does not stop even if the program freezes. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 198 RL78/F12 CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (see Figure 5-1). • Main system clock fMAIN • High-speed system clock fMX X1 clock fX External main system clock fEX • High-speed on-chip oscillator clock fIH • Subsystem clock fSUB • XT1 clock fXT • External subsystem clock fEXS • Low-speed on-chip oscillator clock fIL • CPU/peripheral hardware clock fCLK The CPU starts operation when the high-speed on-chip oscillator starts outputting after a reset release in the RL78/F12. When the power supply voltage is turned on, the clock generator operation is shown in Figure 5-15. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 199 RL78/F12 CHAPTER 5 CLOCK GENERATOR Figure 5-15. Clock Generator Operation When Power Supply Voltage Is Turned On Power supply voltage (VDD) 1.8 V 1.51 V (TYP.) 0V Internal reset signal Voltage stabilization wait 0.99 ms(TYP.), 2.30 ms(MAX.) Reset processing timeNote 3 Switched by software High-speed on-chip oscillator clock CPU clock High-speed system clock Subsystem clock High-speed on-chip oscillator clock (fIH) High-speed system clock (fMX) (when X1 oscillation selected) Subsystem clock (fSUB) (when XT1 oscillation selected) Note 1 X1 clock oscillation stabilization timeNote 2 Starting X1 oscillation is specified by software. Starting XT1 oscillation is specified by software. When the power is turned on, an internal reset signal is generated by the power-on-reset (POR) circuit. When the power supply voltage exceeds 1.51 V (TYP.), the reset is released and the high-speed on-chip oscillator automatically starts oscillation. The CPU starts operation on the high-speed on-chip oscillator clock after a reset processing such as waiting for the voltage of the power supply or regulator to stabilize has been performed after reset release. Set the start of oscillation of the X1 or XT1 clock via software (see 5.6.2 Example of setting X1 oscillation clock and 5.6.3 Example of setting XT1 oscillation clock). When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set switching via software (see 5.6.2 Example of setting X1 oscillation clock and 5.6.3 Example of setting XT1 oscillation clock). Notes 1. The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed onchip oscillator clock. 2. When releasing a reset, confirm the oscillation stabilization time for the X1 clock using the oscillation stabilization time counter status register (OSTC). 3. After the power is turned on and the voltage stabilization wait time has elapsed, the following reset processing time is required release from the reset state (POR), i.e. when the power supply voltage reaches 1.51 V (TYP.) and the RESET signal is driven to the high level. Following initial release from the POR state: 0.672 ms (TYP.), 0.832 ms (MAX.) (when the LVD is in use) 0.399 ms (TYP.), 0.519 ms (MAX.) (when the LVD is off) The following reset processing time is required following the second and subsequent releases from the reset state, i.e. when the RESET signal is asserted (low level) and then de-asserted (high level), as in a reset where a POR is not generated Following the second and subsequent releases from the reset state: 0.531 ms (TYP.), 0.675 ms (MAX.) (when the LVD is in use) 0.259 ms (TYP.), 0.362 ms (MAX.) (when the LVD is off) Caution It is not necessary to wait for the oscillation stabilization time when an external clock input from the EXCLK pin is used. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 200 RL78/F12 CHAPTER 5 CLOCK GENERATOR 5.6 Controlling Clock 5.6.1 Example of setting high-speed on-chip oscillator After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip oscillator clock. The frequency of the high-speed on-chip oscillator can be selected from 32, 24, 16, 12, 8, 4, and 1 MHz by using FRQSEL0 to FRQSEL3 of the option byte (000C2H). The frequency can be changed by the high-speed on-chip oscillator frequency select register (HOCODIV). [Option byte setting] Address: 000C2H Option byte (000C2H) 7 6 5 4 3 2 1 0 CMODE1 0/1 CMODE0 0/1 1 0 FRQSEL3 0/1 FRQSEL2 0/1 FRQSEL1 0/1 FRQSEL0 0/1 CMODE1 CMODE0 1 0 LS (low speed main) mode 1 1 HS (high speed main) mode FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 1 0 0 0 32 MHz 0 0 0 0 24 MHz 1 0 0 1 16 MHz 0 0 0 1 12 MHz 1 0 1 0 8 MHz 1 0 1 1 4 MHz 1 1 0 1 1 MHz Setting of flash operation mode Other than above Frequency of the high-speed on-chip oscillator Setting prohibited [Internal high-speed oscillator frequency select register (HOCODIV) setting] Address: F00A8H HOCODIV 7 6 5 4 3 2 1 0 0 0 0 0 0 HOCODIV.2 HOCODIV.1 HOCODIV.0 HOCODIV.2 HOCODIV.1 HOCODIV.0 FRQSEL3 Bit is 0 FRQSEL3 Bit of is 1 0 0 0 24 MHz 32 MHz 0 0 1 12 MHz 16 MHz 0 1 0 6 MHz 8 MHz 0 1 1 3 MHz 4 MHz 1 0 0 Setting prohibited 2 MHz 0 1 Setting prohibited 1 MHz 1 Other than above R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 Selection of High-speed on-chip oscillator clock frequency Setting prohibited 201 RL78/F12 CHAPTER 5 CLOCK GENERATOR 5.6.2 Example of setting X1 oscillation clock After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip oscillator clock. To subsequently change the clock to the X1 oscillation clock, set the oscillator and start oscillation by using the clock operation mode control register (CMC) and clock operation status control register (CSC) and wait for oscillation to stabilize by using the oscillation stabilization time counter status register (OSTC). After the oscillation stabilizes, set the X1 oscillation clock to fCLK by using the system clock control register (CKC). [Register settings] Set the register in the order of to below. Set (1) the OSCSEL bit and the AMPH bit (in the case of fX > 10 MHz) of the CMC register to operate the X1 oscillator. CMC 7 6 5 4 EXCLK OSCSEL EXCLKS OSCSELS 0 1 0 0 3 2 1 0 AMPHS1 AMPHS0 AMPH 0 0 1 1 0 0 AMPH bit: Set this bit to 0 if the X1 oscillation clock is 10 MHz or less. Clear (0) the MSTOP bit of the CSC register to start oscillating the X1 oscillator. CSC 7 6 MSTOP XTSTOP 0 1 5 4 3 2 HIOSTOP 0 0 0 0 0 0 Use the OSTC register to wait for oscillation of the X1 oscillator to stabilize. Example: Wait until the bits reach the following values when a wait of at least 102.4 μs is set based on a 10 MHz resonator. OSTC 7 6 5 4 3 2 1 0 MOST8 MOST9 MOST10 MOST11 MOST13 MOST15 MOST17 MOST18 1 1 1 0 0 0 0 0 Use the MCM0 bit of the CKC register to specify the X1 oscillation clock as the CPU/peripheral hardware clock. CKC 7 6 5 4 CLS CSS MCS MCM0 0 0 0 1 R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 3 2 1 0 0 0 0 0 202 RL78/F12 CHAPTER 5 CLOCK GENERATOR 5.6.3 Example of setting XT1 oscillation clock After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip oscillator clock. To subsequently change the clock to the XT1 oscillation clock, set the oscillator and start oscillation by using the operation speed mode control register (OSMC), clock operation mode control register (CMC), and clock operation status control register (CSC), set the XT1 oscillation clock to fCLK by using the system clock control register (CKC). [Register settings] Set the register in the order of to below. To run only the real-time clock and interval timer on the subsystem clock (ultra-low current consumption) when in the STOP mode or sub-HALT mode, set the RTCLPC bit to 1. 7 6 5 0/1 3 2 1 0 0 0 0 0 2 1 0 AMPHS1 AMPHS0 AMPH 0/1 0/1 0 WUTMMCK0 RTCLPC OSMC 4 0 0 0 Set (1) the OSCSELS bit of the CMC register to operate the XT1 oscillator. CMC 7 6 5 4 EXCLK OSCSEL EXCLKS OSCSELS 0 0 0 1 3 0 AMPHS0 and AMPHS1 bits: These bits are used to specify the oscillation mode of the XT1 oscillator. Clear (0) the XTSTOP bit of the CSC register to start oscillating the XT1 oscillator. CSC 7 6 MSTOP XTSTOP 1 0 5 4 3 2 1 0 0 0 0 0 0 HIOSTOP 0 Use the timer function or another function to wait for oscillation of the subsystem clock to stabilize by using software. Use the CSS bit of the CKC register to specify the XT1 oscillation clock as the CPU/peripheral hardware clock. CKC 7 6 5 4 CLS CSS MCS MCM0 0 1 0 0 R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 3 2 1 0 0 0 0 0 203 RL78/F12 CHAPTER 5 CLOCK GENERATOR 5.6.4 CPU clock status transition diagram Figure 5-16 shows the CPU clock status transition diagram of this product. Figure 5-16. CPU Clock Status Transition Diagram High-speed on-chip oscillator: Woken up X1 oscillation/EXCLK input: Stops (input port mode) XT1 oscillation/EXCLKS input: Stops (input port mode) Power ON VDD < 1.51 V±0.03 VDD  1.51 V±0.03 (A) High-speed on-chip oscillator: Operating X1 oscillation/EXCLK input: Selectable by CPU XT1 oscillation/EXCLKS input: Selectable by CPU High-speed on-chip oscillator: Selectable by CPU X1 oscillation/EXCLK input: Selectable by CPU XT1 oscillation/EXCLKS input: Operating Reset release High-speed on-chip oscillator: Operating X1 oscillation/EXCLK input: Stops (input port mode) XT1 oscillation/EXCLKS input: Stops (input port mode) VDD  1.8 V Note 1 (B) (H) CPU: Operating with high-speed onchip oscillator clock CPU: High-speed on-chip oscillator  STOP (D) CPU: Operating with XT1 oscillation or EXCLKS input (J) (E) CPU: High-speed on-chip oscillator  HALT (C) (G) CPU: XT1 oscillation/EXCLKS input  HALT High-speed on-chip oscillator: Oscillatable X1 oscillation/EXCLK input: Oscillatable XT1 oscillation/EXCLKS input: Operating CPU: Operating with X1 oscillation or EXCLK input High-speed on-chip oscillator: Selectable by CPU X1 oscillation/EXCLK input: Operating XT1 oscillation/EXCLKS input: Selectable by CPU CPU: High-speed on-chip oscillator  SNOOZE High-speed on-chip oscillator: Stops X1 oscillation/EXCLK input: Stops XT1 oscillation/EXCLKS input: Oscillatable High-speed on-chip oscillator: Operating X1 oscillation/EXCLK input: Stops XT1 oscillation/EXCLKS input: Oscillateble High-speed on-chip oscillator: Operating X1 oscillation/EXCLK input: Oscillatable XT1 oscillation/EXCLKS input: Oscillatable (I) (F) CPU: X1 oscillation/EXCLK input  STOP CPU: X1 oscillation/EXCLK input  HALT High-speed on-chip oscillator: Stops X1 oscillation/EXCLK input: Stops XT1 oscillation/EXCLKS input: Oscillatable High-speed on-chip oscillator: Oscillatable X1 oscillation/EXCLK input: Operating XT1 oscillation/EXCLKS input: Oscillatable R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 204 RL78/F12 CHAPTER 5 CLOCK GENERATOR Table 5-3 shows transition of the CPU clock and examples of setting the SFR registers. Table 5-3. CPU Clock Transition and SFR Register Setting Examples (1/5) (1) CPU operating with high-speed on-chip oscillator clock (B) after reset release (A) Status Transition SFR Register Setting (A) → (B) SFR registers do not have to be set (default status after reset release). (2) CPU operating with high-speed system clock (C) after reset release (A) (The CPU operates with the high-speed on-chip oscillator clock immediately after a reset release (B).) (Setting sequence of SFR registers) Setting Flag of SFR Register CMC Register Note CSC OSTS OSTC Register Register Register CKC Register Status Transition EXCLK OSCSEL AMPH 0 1 0 Note 2 0 Must be checked 1 0 1 1 Note 2 0 Must be checked 1 1 1 × Note 2 0 Must not be checked 1 (A) → (B) → (C) MSTOP MCM0 (X1 clock: 1 MHz ≤ fX ≤ 10 MHz) (A) → (B) → (C) (X1 clock: 10 MHz < fX ≤ 20 MHz) (A) → (B) → (C) (external main clock) Notes 1. The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation instruction after reset release. 2. Set the oscillation stabilization time as follows. • Desired oscillation stabilization time counter status register (OSTC) oscillation stabilization time ≤ Oscillation stabilization time set by the oscillation stabilization time select register (OSTS) Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see CHAPTER 31 ELECTRICAL SPECIFICATIONS (J GRADE) and CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE)). (3) CPU operating with subsystem clock (D) after reset release (A) (The CPU operates with the high-speed on-chip oscillator clock immediately after a reset release (B).) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (A) → (B) → (D) CMC Register Note EXCLKS OSCSELS AMPHS1 AMPHS0 CSC Waiting for CKC Register Oscillation Register XTSTOP Stabilization CSS 0 1 0/1 0/1 0 Necessary 1 1 1 × × 0 Necessary 1 (XT1 clock) (A) → (B) → (D) (external sub clock) Note The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation instruction after reset release. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 205 RL78/F12 CHAPTER 5 CLOCK GENERATOR Remarks 1. ×: don’t care 2. (A) to (J) in Table 5-3 correspond to (A) to (J) in Figure 5-16. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 206 RL78/F12 CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (2/5) (4) CPU clock changing from high-speed on-chip oscillator clock (B) to high-speed system clock (C) (Setting sequence of SFR registers) CMC Register Setting Flag of SFR Register Status Transition (B) → (C) Note 1 OSTS CSC Register Register Register CKC MSTOP MCM0 OSTC Register EXCLK OSCSEL AMPH 0 1 0 Note 2 0 Must be checked 1 0 1 1 Note 2 0 Must be checked 1 1 1 × Note 2 0 Must not be checked 1 (X1 clock: 1 MHz ≤ fX ≤ 10 MHz) (B) → (C) (X1 clock: 10 MHz < fX ≤ 20 MHz) (B) → (C) (external main clock) Unnecessary if these registers Unnecessary if the CPU is operating with the high-speed system clock are already set Notes 1. The clock operation mode control register (CMC) can be changed only once after reset release. This setting is not necessary if it has already been set. 2. Set the oscillation stabilization time as follows. • Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time ≤ Oscillation stabilization time set by the oscillation stabilization time select register (OSTS) Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see CHAPTER 31 ELECTRICAL SPECIFICATIONS (J GRADE) and CAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE)). (5) CPU clock changing from high-speed on-chip oscillator clock (B) to subsystem clock (D) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (B) → (D) CMC Register Note CSC Waiting for Register Oscillation CKC Register EXCLKS OSCSELS XTSTOP Stabilization CSS 0 1 0 Necessary 1 1 1 0 Necessary 1 (XT1 clock) (B) → (D) (external sub clock) Unnecessary if the CPU is operating with the subsystem clock Note The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation instruction after reset release. Remarks 1. ×: don’t care 2. (A) to (J) in Table 5-3 correspond to (A) to (J) in Figure 5-16. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 207 RL78/F12 CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (3/5) (6) CPU clock changing from high-speed system clock (C) to high-speed on-chip oscillator clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (C) → (B) CSC Register Oscillation accuracy CKC Register HIOSTOP stabilization time MCM0 0 30 μ s 0 Unnecessary if the CPU is operating with the high-speed on-chip oscillator clock (7) CPU clock changing from high-speed system clock (C) to subsystem clock (D) (Setting sequence of SFR registers) Setting Flag of SFR Register CSC Register Waiting for Oscillation CKC Register XTSTOP Stabilization CSS 0 Necessary 1 Status Transition (C) → (D) Unnecessary if the CPU is operating with the subsystem clock (8) CPU clock changing from subsystem clock (D) to high-speed on-chip oscillator clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (D) → (B) CSC Register CKC Register HIOSTOP MCM0 CSS 0 0 0 Unnecessary if the CPU Unnecessary if this is operating with the register is already set high-speed on-chip oscillator clock Remark (A) to (J) in Table 5-3 correspond to (A) to (J) in Figure 5-16. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 208 RL78/F12 CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (4/5) (9) CPU clock changing from subsystem clock (D) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register OSTS CSC Register Register MSTOP Note 0 Note Note OSTC Register CKC Register MCM0 CSS Must be checked 1 0 0 Must be checked 1 0 0 Must not be checked 1 0 Status Transition (D) → (C) (X1 clock: 1 MHz ≤ fX ≤ 10 MHz) (D) → (C) (X1 clock: 10 MHz < fX ≤ 20 MHz) (D) → (C) (external main clock) Unnecessary if the CPU is operating with the high-speed system clock Note Unnecessary if these registers are already set Set the oscillation stabilization time as follows. • Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time ≤ Oscillation stabilization time set by the oscillation stabilization time select register (OSTS) Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see CHAPTER 31 ELECTRICAL SPECIFICATIONS (J GRADE) and CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE)). (10) • HALT mode (E) set while CPU is operating with high-speed on-chip oscillator clock (B) • HALT mode (F) set while CPU is operating with high-speed system clock (C) • HALT mode (G) set while CPU is operating with subsystem clock (D) Status Transition (B) → (E) Setting Executing HALT instruction (C) → (F) (D) → (G) Remark (A) to (J) in Table 5-3 correspond to (A) to (J) in Figure 5-16. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 209 RL78/F12 CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (5/5) (11) • STOP mode (H) set while CPU is operating with high-speed on-chip oscillator clock (B) • STOP mode (I) set while CPU is operating with high-speed system clock (C) (Setting sequence) Status Transition (B) → (H) Setting − Stopping peripheral functions that cannot (C) → (I) In X1 oscillation operate in STOP mode Executing STOP instruction Sets the OSTS register External main − system clock (12) CPU changing from STOP mode (H) to SNOOZE mode (J) For details about the setting for switching from the STOP mode to the SNOOZE mode, see 12.8 SNOOZE Mode Function, 13.5.7 SNOOZE mode function (only CSI00) and 13.6.3 SNOOZE mode function (only UART0 reception). Remark (A) to (J) in Table 5-3 correspond to (A) to (J) in Figure 5-16. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 210 RL78/F12 CHAPTER 5 CLOCK GENERATOR 5.6.5 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 5-4. Changing CPU Clock (1/2) CPU Clock Before Change Condition Before Change Processing After Change After Change Stabilization of X1 oscillation Operating current can be reduced by chip oscillator • OSCSEL = 1, EXCLK = 0, MSTOP = 0 stopping high-speed on-chip oscillator clock • After elapse of oscillation stabilization time (HIOSTOP = 1). High-speed on- X1 clock External main Enabling input of external clock from the system clock EXCLK pin • OSCSEL = 1, EXCLK = 1, MSTOP = 0 XT1 clock Stabilization of XT1 oscillation • OSCSELS = 1, EXCLKS = 0, XTSTOP = 0 • After elapse of oscillation stabilization time External Enabling input of external clock from the subsystem clock EXCLKS pin • OSCSELS = 1, EXCLKS = 1, XTSTOP = 0 X1 clock High-speed on- Oscillation of high-speed on-chip oscillator chip oscillator • HIOSTOP = 0 X1 oscillation can be stopped (MSTOP = 1). clock External main Transition not possible system clock (To change the clock, set it again after XT1 clock Stabilization of XT1 oscillation − executing reset once.) X1 oscillation can be stopped (MSTOP = 1). • OSCSELS = 1, EXCLKS = 0, XTSTOP = 0 • After elapse of oscillation stabilization time External Enabling input of external clock from the subsystem clock EXCLKS pin X1 oscillation can be stopped (MSTOP = 1). • OSCSELS = 1, EXCLKS = 1, XTSTOP = 0 External main High-speed on- Oscillation of high-speed on-chip oscillator External main system clock input can be system clock chip oscillator • HIOSTOP = 0 disabled (MSTOP = 1). clock X1 clock Transition not possible − (To change the clock, set it again after executing reset once.) XT1 clock Stabilization of XT1 oscillation External main system clock input can be • OSCSELS = 1, EXCLKS = 0, XTSTOP = 0 disabled (MSTOP = 1). • After elapse of oscillation stabilization time External Enabling input of external clock from the External main system clock input can be subsystem clock EXCLKS pin disabled (MSTOP = 1). • OSCSELS = 1, EXCLKS = 1, XTSTOP = 0 R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 211 RL78/F12 CHAPTER 5 CLOCK GENERATOR Table 5-4. Changing CPU Clock (2/2) CPU Clock Before Change XT1 clock Condition Before Change Processing After Change After Change High-speed on- Oscillation of high-speed on-chip oscillator XT1 oscillation can be stopped (XTSTOP = chip oscillator and selection of high-speed on-chip 1) clock oscillator clock as main system clock • HIOSTOP = 0, MCS = 0 X1 clock Stabilization of X1 oscillation and selection of high-speed system clock as main system clock • OSCSEL = 1, EXCLK = 0, MSTOP = 0 • After elapse of oscillation stabilization time • MCS = 1 External main Enabling input of external clock from the system clock EXCLK pin and selection of high-speed system clock as main system clock • OSCSEL = 1, EXCLK = 1, MSTOP = 0 • MCS = 1 External Transition not possible subsystem clock (To change the clock, set it again after − executing reset once.) External High-speed on- Oscillation of high-speed on-chip oscillator External subsystem clock input can be subsystem clock chip oscillator and selection of high-speed on-chip disabled (XTSTOP = 1). clock oscillator clock as main system clock • HIOSTOP = 0, MCS = 0 X1 clock Stabilization of X1 oscillation and selection of high-speed system clock as main system clock • OSCSEL = 1, EXCLK = 0, MSTOP = 0 • After elapse of oscillation stabilization time • MCS = 1 External main Enabling input of external clock from the system clock EXCLK pin and selection of high-speed system clock as main system clock • OSCSEL = 1, EXCLK = 1, MSTOP = 0 • MCS = 1 XT1 clock Transition not possible − (To change the clock, set it again after executing reset once.) R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 212 RL78/F12 CHAPTER 5 CLOCK GENERATOR 5.6.6 Time required for switchover of CPU clock and main system clock By setting bits 4 and 6 (MCM0, CSS) of the system clock control register (CKC), the CPU clock can be switched (between the main system clock and the subsystem clock), and main system clock can be switched (between the highspeed on-chip oscillator clock and the high-speed system clock). The actual switchover operation is not performed immediately after rewriting to the CKC register; operation continues on the pre-switchover clock for several clocks (see Table 5-5 to Table 5-7). Whether the CPU is operating on the main system clock or the subsystem clock can be ascertained using bit 7 (CLS) of the CKC register. Whether the main system clock is operating on the high-speed system clock or high-speed on-chip oscillator clock can be ascertained using bit 5 (MCS) of the CKC register. When the CPU clock is switched, the peripheral hardware clock is also switched. Table 5-5. Maximum Time Required for Main System Clock Switchover Clock A Switching directions Clock B Remark fIH fMX See Table 5-6 fMAIN fSUB See Table 5-7 Table 5-6. Maximum Number of Clocks Required for fIH ↔ fMX Set Value Before Switchover Set Value After Switchover MCM0 MCM0 0 1 (f MAIN = f IH ) (f MAIN = f MX ) 0 f MX ≥f IH 1 + fIH/fMX clock (f MAIN = f IH ) f MX < accumulated result > MDAL (bits 15 to 0) × MDAH (bits 15 to 0) + MDC (bits 31 to 0) = [MDCH (bits 15 to 0), MDCL (bits 15 to 0)] (The multiplication result is stored in the MDBH (bits 15 to 0) and MDBL (bits 15 to 0).) • Register configuration during division [MDAH (bits 15 to 0), MDAL (bits 15 to 0)] ÷ [MDBH (bits 15 to 0), MDBL (bits 15 to 0)] = [MDAH (bits 15 to 0), MDAL (bits 15 to 0)] ⋅⋅⋅ [MDCH (bits 15 to 0), MDCL (bits 15 to 0)] R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 823 RL78/F12 CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 16.3 Register Controlling Multiplier and Divider/Multiply-Accumulator The multiplier and divider/multiply-accumulator is controlled by using the multiplication/division control register (MDUC). (1) Multiplication/division control register (MDUC) The MDUC register is an 8-bit register that controls the operation of the multiplier and divider/multiply-accumulator. The MDUC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 16-5. Format of Multiplication/Division Control Register (MDUC) Address: F00E8H After reset: 00H R/W Symbol 5 4 MDUC DIVMODE MACMODE 0 0 MDSM MACOF MACSF DIVST DIVMODE MACMODE MDSM 0 0 0 Multiplication mode (unsigned) (default) 0 0 1 Multiplication mode (signed) 0 1 0 Multiply-accumulator mode (unsigned) 0 1 1 Multiply-accumulator mode (signed) 1 0 0 Division mode (unsigned), generation of a division completion Operation mode selection interrupt (INTMD occurs/does not occur) 1 1 0 Division mode (unsigned), not generation of a division completion interrupt (INTMD does not occur) Other than above MACOF Note 1 Setting prohibited Overflow flag of multiply-accumulation result (accumulated value) 0 No overflow 1 With over flow • For the multiply-accumulator mode (unsigned) The bit is set when the accumulated value goes outside the range from 00000000h to FFFFFFFFh. • For the multiply-accumulator mode (signed) The bit is set when the result of adding a positive product to a positive accumulated value exceeds 7FFFFFFFh and is negative, or when the result of adding a negative product to a negative accumulated value exceeds 80000000h and is positive. MACSF Sign flag of multiply-accumulation result (accumulated value) 0 The accumulated value is positive. 1 The accumulated value is negative. Multiply-accumulator mode (unsigned): The bit is always 0. Multiply-accumulator mode (signed): The bit indicates the sign bit of the accumulated value. Note 2 DIVST Division operation start/stop 0 Division operation processing complete 1 Starts division operation/division operation processing in progress R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 824 RL78/F12 CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Notes 1. The MACOF bit is read only. 2. The DIVST bit can only be set (1) in the division mode. In the division mode, division operation is started by setting (1) the DIVST bit. The DIVST bit is automatically cleared (0) when the operation ends. In the multiplication mode, operation is automatically started by setting the multiplier and multiplicand to multiplication/division data register A (MDAH, MDAL), respectively. Cautions 1. Do not rewrite the DIVMODE, MDSM bits during operation processing (while the DIVST bit is 1). If it is rewritten, the operation result will be an undefined value. 2. The DIVST bit cannot be cleared (0) by using software during division operation processing (while the DIVST bit is 1). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 825 RL78/F12 CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 16.4 Operations of Multiplier and Divider/Multiply-Accumulator 16.4.1 Multiplication (unsigned) operation • Initial setting Set the multiplication/division control register (MDUC) to 00H. Set the multiplicand to multiplication/division data register A (L) (MDAL). Set the multiplier to multiplication/division data register A (H) (MDAH). (There is no preference in the order of executing steps and . Multiplication operation is automatically started when the multiplier and multiplicand are set to the MDAH and MDAL registers, respectively.) • During operation processing Wait for at least one clock. The operation will end when one clock has been issued. • Operation end Read the product (lower 16 bits) from multiplication/division data register B (L) (MDBL). Read the product (higher 16 bits) from multiplication/division data register B (H) (MDBH). (There is no preference in the order of executing steps and .) • Next operation To execute multiplication, division, or multiply-accumulation next, start with the initial settings of each step. Remark Steps to correspond to to in Figure 16-6. Figure 16-6. Timing Diagram of Multiplication (Unsigned) Operation (2 × 3 = 6) Operation clock MDUC 00H MDSM L MDAL 0000H MDAH 0000H MDBL, MDBH 0000H 0000H 0002H 0003H FFFFH 0002H FFFDH 0000H 0006H R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 FFFFH , FFFEH 0001H 826 RL78/F12 CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 16.4.2 Multiplication (signed) operation • Initial setting Set the multiplication/division control register (MDUC) to 08H. Set the multiplicand to multiplication/division data register A (L) (MDAL). Set the multiplier to multiplication/division data register A (H) (MDAH). (There is no preference in the order of executing steps and . Multiplication operation is automatically started when the multiplier and multiplicand are set to the MDAH and MDAL registers, respectively.) • During operation processing Wait for at least one clock. The operation will end when one clock has been issued. • Operation end Read the product (lower 16 bits) from multiplication/division data register B (L) (MDBL). Read the product (higher 16 bits) from multiplication/division data register B (H) (MDBH). (There is no preference in the order of executing steps and .) • Next operation To execute multiplication (signed) operation next, start from the “Initial setting” for multiplication (signed) operation. The next time multiplication (unsigned), multiply-accumulation (signed or unsigned), or division is performed, start with the initial settings of each step. Caution The data is in the two's complement format in multiplication mode (signed). Remark Steps to correspond to to in Figure 16-7. Figure 16-7. Timing Diagram of Multiplication (Signed) Operation (−2 × 32767 = −65534) Operation clock MDUC 00H 08H MDSM MDAL 0000H MDAH 0000H MDBL, MDBH 0000H 0000H FFFEH 7FFFH FFFFH FFFFH 8001H FFFFH 0002H R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 FFFFH , 0000H 0001H 827 RL78/F12 CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 16.4.3 Multiply-accumulation (unsigned) operation • Initial setting Set the multiplication/division control register (MDUC) to 40H. Set the initial accumulated value of higher 16 bits to multiplication/division data register C (L) (MDCL). Set the initial accumulated value of lower 16 bits to multiplication/division data register C (H) (MDCH). Set the multiplicand to multiplication/division data register A (L) (MDAL). Set the multiplier to multiplication/division data register A (H) (MDAH). (There is no preference in the order of executing steps and , or and . Multiplication operation is automatically started when the multiplier and multiplicand are set to the MDAH and MDAL registers, respectively.) • During operation processing The multiplication operation finishes in one clock cycle. (The multiplication result is stored in multiplication/division data register B (L) (MDBL) and multiplication/division data register B (H) (MDBH).) After , the multiply-accumulation operation finishes in one additional clock cycle. (There is a wait of at least two clock cycles after specifying the initial settings is finished ().) • Operation end Read the accumulated value (lower 16 bits) from the MDCL register. Read the accumulated value (higher 16 bits) from the MDCH register. (There is no preference in the order of executing steps and .) ( If the result of the multiply-accumulation operation causes an overflow, the MACOF bit is set to 1, and 0000H is stored in the MDCH and MDCL registers.) • Next operation To execute multiply-accumulation (unsigned) operation next, start from the “Initial setting” for multiplyaccumulation (unsigned) operation. The next time multiplication (signed or unsigned), multiply-accumulation (signed), or division is performed, start with the initial settings of each step. Remark Steps to correspond to to in Figure 16-8. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 828 RL78/F12 CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 16-8. Timing Diagram of Multiply-Accumulation (Unsigned) Operation (2 × 3 + 3 = 9 → 32767 × 2 + 429401762 = 0 (over flow generated)) Operation clock MDUC 00H 40H 44H MDSM L MDCH 0000H MDCL 0000H MDAL 0000H MDAH 0000H MDBH MDBL 0000H 0000H FFFFH 0003H 0009H 0000H 0002H 0000H , 0002H 7FFFH 0003H 0002H 0000H 0006H 0000H FFFEH INTMD MACOF MACSF L R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 VLVIn: n = 1 to 13 The following relationship is formed under the same temperature conditions: the detection voltage at power supply rise time > the detection voltage at power supply fall time. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1044 RL78/F12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (J GRADE) Caution The pins mounted depend on the product. (b) LVD Detection Voltage of Interrupt & Reset Mode (TA = −40 to +85°C, VPDR ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Interrupt and reset VLVI11 mode VLVI10 Conditions VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage: 1.8 V LVIS1, LVIS0 = 1, 0 Rising release reset voltage Falling interrupt voltage VLVI9 LVIS1, LVIS0 = 0, 1 Rising release reset voltage Falling interrupt voltage VLVI2 LVIS1, LVIS0 = 0, 0 Rising release reset voltage Falling interrupt voltage VLVI8 VLVI7 VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage: 2.4 V LVIS1, LVIS0 = 1, 0 Rising release reset voltage Falling interrupt voltage VLVI6 LVIS1, LVIS0 = 0, 1 Rising release reset voltage Falling interrupt voltage VLVI1 LVIS1, LVIS0 = 0, 0 Rising release reset voltage Falling interrupt voltage VLVI5 VLVI4 VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage: 2.7 V LVIS1, LVIS0 = 1, 0 Rising release reset voltage Falling interrupt voltage VLVI3 LVIS1, LVIS0 = 0, 1 Rising release reset voltage Falling interrupt voltage VLVI0 LVIS1, LVIS0 = 0, 0 Rising release reset voltage Falling interrupt voltage Note MIN. TYP. MAX. Unit 1.84 1.94 V 1.93 1.98 2.09 V 1.89 1.94 2.04 V 2.04 2.09 2.21 V 1.99 2.04 2.14 V 3.06 3.13 3.28 V 2.99 3.06 3.20 V 1.79 Note 2.39 2.45 2.57 V 2.55 2.61 2.74 V 2.49 2.55 2.67 V 2.64 2.71 2.85 V 2.59 2.65 2.77 V 3.66 3.75 3.93 V 3.58 3.67 3.83 V 2.68 2.75 2.88 V 2.85 2.92 3.07 V 2.79 2.86 2.99 V 2.95 3.02 3.17 V 2.89 2.96 3.09 V 3.96 4.06 4.25 V 3.89 3.98 4.15 V The minimum value lowers the minimum guaranteed voltage for operation(1.8V). However, LVD detection performs in the same way as in normal mode (operation according to the same specification when VDD is 1.8V) until it is reset at reset mode. Remark The following relationship is formed under the same temperature conditions: the rising release reset voltage > the falling interrupt voltage > the falling reset voltage Caution The pins mounted depend on the product. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1045 RL78/F12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (J GRADE) 31.7.5 Power supply rise time (TA = −40 to +85°C, VSS = EVSS = 0 V) Parameter Maximum slew rate for the supply Symbol Conditions Note 2 Svrmax 0 V → VDD (MIN.) Svrmin 0V → 1.8 V (CMODE0 = 0) MIN. TYP. (VPOC2 = 0 or 1) MAX. 50 Note 1 Unit V/ms voltage to rise Minimum slew rate for the supply voltage to rise Notes 1. Note 3 0V → 2.7 V (CMODE0 = 1) 3.5 Note 1 V/ms 6.5 Note 1 V/ms In case the supply voltage falls to a level of VPDR or below and a power-on reset is generated, the slew rate must not exceed the value Svrmax even if the supply voltage does not go down to 0 V. 2. VDD (MIN.) varies depending on the setting of the flash operation mode in the option byte (CMODE0 bit). LS (low speed main) mode (CMODE0 = 0): VDD (MIN.) = 1.8 V HS (high speed main) mode (CMODE0 = 1): VDD (MIN.) = 2.7 V 3. The minimum slew rate for the supply voltage (Svrmin) must be met when the voltage detector (LVD) is not used (option byte bit VPOC2 = 1) and an external reset circuit releases before the supply voltage reaches VDD (MIN.) (as specified in Note 2). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1046 RL78/F12 CHAPTER 31 ELECTRICAL SPECIFICATIONS (J GRADE) 31.8 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°C VSS = EVSS = 0 V) Parameter Data retention supply voltage Symbol Conditions VDDDR MIN. 1.45 TYP. Note MAX. Unit 5.5 V Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is effected, but data is not retained when a POR reset is effected. Operation mode STOP mode Data retention mode VDD VDDDR STOP instruction execution Standby release signal (interrupt request) 31.9 Flash Memory Programming Characteristics (TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol System clock frequency fCLK Number of code flash rewrites Cerwr Notes 1, 2, 3 Conditions MIN. TYP. 1 20 years retention (after rewrite) 1000 MAX. Unit 32 MHz Times TA = +85°C Number of data flash rewrites 20 years retention (after rewrite) Notes 1, 2, 3 10000 TA = +85°C 5 years retention (after rewrite) 100000 TA = +85°C Erase time Block erase write time Terasa 5 ms Twrwa 10 μs Notes 1. Retention years indicate a period between time for a rewrite and the next. 2. When using flash memory programmer and Renesas Electronics self programming library. 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1047 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Cautions 1. RL78/F12 has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 2. Pins mounted are as follows according to product. 32.1 Pins Mounted According to Product 32.1.1 Port functions Refer to 2.1.1 20-pin products to 2.1.5 64-pin products. 32.1.2 Non-port functions Refer to 2.1.6 Pins for each product (pins other than port pins). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1048 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. 32.2 Absolute Maximum Ratings Absolute Maximum Ratings (TA = 25°C) (1/2) Parameter Supply voltage Symbols Ratings Unit VDD −0.5 to +6.5 V EVDD −0.5 to +6.5 V VSS −0.5 to +0.3 V EVSS −0.5 to +0.3 V REGC pin input voltage VIREGC Conditions REGC −0.3 to +2.8 V and −0.3 to VDD +0.3 Input voltage VI1 P00 to P06, P10 to P17, P30, P31, P40 to P43, P50 to P55, P70 to P77, P120, P140, P141, P146, P147 VI2 Output voltage P60 to P63 (N-ch open-drain) VI3 P20 to P27, P121 to P124, P137, RESET VO1 P00 to P06, P10 to P17, P30, P31, P40 to P43, P50 to P55, Note 1 −0.3 to EVDD+0.3 and −0.3 to VDD+0.3 −0.3 to +6.5 −0.3 to VDD +0.3 V Note 2 V Note 2 Note 2 −0.3 to EVDD +0.3 V V P60 to P63, P70 to P77, P120, P130, P140, P141, P146, P147 VO2 Analog input voltage VAI1 VAI2 Notes 1. P20 to P27 ANI16 to ANI19 ANI0 to ANI7 −0.3 to VDD +0.3 −0.3 to EVDD +0.3 −0.3 to VDD +0.3 Note 2 Note 2 V V V Connect the REGC pin to Vss via a capacitor (0.47 to 1 μ F). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. 2. Must be 6.5 V or lower. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1049 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. Absolute Maximum Ratings (TA = 25°C) (2/2) Parameter Output current, high Symbols IOH1 Conditions Per pin P00 to P06, P10 to P17, P30, P31, P40 to P43, Ratings Unit −40 mA P50 to P55, P70 to P77, P120, P130, P140, P141, P146, P147 Total of all pins P00 to P04, P40 to P43, P120, P130, P140, P141 −70 mA −170 mA P05, P06, P10 to P17, P30, P31, P50 to P55, P70 −100 mA to P77, P146, P147 IOH2 Per pin P20 to P27 Total of all pins Output current, low IOL1 Per pin P00 to P06, P10 to P17, P30, P31, P40 to P43, −0.5 mA −2 mA 40 mA P50 to P55, P60 to P63, P70 to P77, P120, P130, P140, P141, P146, P147 Total of all pins P00 to P04, P40 to P43, P120, P130, P140, P141 70 mA 170 mA P05, P06, P10 to P17, P30, P31, P50 to P55, P60 100 mA 1 mA 5 mA −40 to +125 °C to P63, P70 to P77, P146, P147 IOL2 Per pin P20 to P27 Total of all pins Operating ambient TA temperature In normal operation mode In flash memory programming mode Storage temperature Data −40 to +125 Code −40 to +105 Tstg −65 to +150 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1050 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. 32.3 Oscillator Characteristics 32.3.1 Main system clock oscillator characteristics (TA = −40 to +125°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Recommended Resonator Parameter Conditions X1 clock oscillation 2.7 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD ≤ 5.5 V MIN. TYP. MAX. Unit 1.0 20.0 MHz 1.0 20.0 MHz Circuit Ceramic resonator VSS X1 C1 X2 Rd Note frequency (fX) C2 X1 clock oscillation Crystal resonator VSS X1 C1 X2 Rd Note frequency (fX) C2 Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. 2. Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1051 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. 32.3.2 On-chip oscillator characteristics (TA = −40 to +125°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Oscillators High-speed on-chip Parameters fIH oscillator clock frequency Note Low-speed on-chip fIL Conditions MIN. TYP. MAX. Unit 24 MHz selected 23.52 24.00 24.48 MHz 16 MHz selected 15.68 16.00 16.32 MHz 8 MHz selected 7.84 8.00 8.16 MHz 4 MHz selected 3.92 4.00 4.08 MHz 1 MHz selected 0.98 1.00 1.02 MHz 12.75 15 17.25 kHz oscillator clock frequency Note This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1052 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. 32.3.3 Subsystem clock oscillator characteristics (TA = −40 to +125°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Resonator Recommended Items Conditions MIN. TYP. MAX. Unit 29.0 32.768 35.0 kHz Circuit Crystal resonator XT1 clock oscillation VSS XT2 XT1 Note frequency (fXT) Rd C4 C3 Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the XT1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. 2. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore required with the wiring method when the XT1 clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1053 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. 32.4 DC Characteristics 32.4.1 Pin characteristics (TA = −40 to +125°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Items Symbol Output current, Note 1 high IOH1 Conditions MIN. Unit −5.0 mA −3.0 mA 4.0 V ≤ EVDD ≤ 5.5 V −20.0 mA 2.7 V ≤ EVDD < 4.0 V −10.0 mA Total of P05, P06, P10 to P17, P30, P31, 4.0 V ≤ EVDD ≤ 5.5 V P50 to P55, P70 to P77, P146, P147 2.7 V ≤ EVDD < 4.0 V Note 2 (When duty = 70% ) −30.0 mA −19.0 mA 4.0 V ≤ EVDD ≤ 5.5 V −42.0 mA 2.7 V ≤ EVDD < 4.0 V −29.0 mA −0.1 mA −0.8 mA Total of all pins Note 2 ) (When duty = 70% Per pin for P20 to P27 Total of all pins (When duty = 70% Notes 1. MAX. Per pin for P00 to P06, P10 to P17, P30, 4.0 V ≤ EVDD ≤ 5.5 V P31, P40 to P43, P50 to P55, P70 to 2.7 V ≤ EVDD < 4.0 V P77, P120, P130, P140, P141, P146, P147 Total of P00 to P04, P40 to P43, P120, P130, P140, P141 Note 2 ) (When duty = 70% IOH2 TYP. Note 2 ) Value of current at which the device operation is guaranteed even if the current flows from the EVDD pin to an output pin. 2. Specification under conditions where the duty factor is 70%. The output current value that has changed the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n% (the duty before change < n)). • Total output current of pins = (IOH × 0.7)/(n × 0.01) Where n = 80% and IOH = −10.0 mA Total output current of pins = (−10.0 × 0.7)/(80 × 0.01) = −8.75 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Caution P00, P10 to P15, P17, P50, P71, P74 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1054 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. (TA = −40 to +125°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Items Symbol Output current, Note 1 low IOL1 Conditions MIN. Per pin for P00 to P06, P10 to P17, P30, 4.0 V ≤ EVDD ≤ 5.5 V P31, P40 to P43, P50 to P55, P70 to 2.7 V ≤ EVDD < 4.0 V P77, P120, P130, P140, P141, P146, P147 4.0 V ≤ EVDD ≤ 5.5 V Per pin for P60 to P63 Unit 8.5 mA 4.0 mA 15.0 mA 4.0 mA 4.0 V ≤ EVDD ≤ 5.5 V 20.0 mA 2.7 V ≤ EVDD < 4.0 V 15.0 mA Total of P05, P06, P10 to P17, P30, P31, 4.0 V ≤ EVDD ≤ 5.5 V P50 to P55, P60 to P63, P70 to P77, 2.7 V ≤ EVDD < 4.0 V P146, P147 Note 2 ) (When duty = 70% 45.0 mA 35.0 mA 4.0 V ≤ EVDD ≤ 5.5 V 65.0 mA 2.7 V ≤ EVDD < 4.0 V 50.0 mA 0.4 mA 3.2 mA Total of all pins Note 2 ) (When duty = 70% Per pin for P20 to P27 Total of all pins (When duty = 70% Notes 1. MAX. 2.7 V ≤ EVDD < 4.0 V Total of P00 to P04, P40 to P43, P120, P130, P140, P141 Note 2 ) (When duty = 70% IOL2 TYP. Note 2 ) Value of current at which the device operation is guaranteed even if the current flows from an output pin to the EVSS and VSS pin. 2. Specification under conditions where the duty factor is 70%. The output current value that has changed the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n% (the duty before change < n)). • Total output current of pins = (IOL × 0.7)/(n × 0.01) Where n = 80% and IOL = 10.0 mA Total output current of pins = (10.0 × 0.7)/(80 × 0.01) = 8.75 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1055 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. (TA = −40 to +125°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Items Input voltage, Symbol VIH1 high Conditions MIN. P00 to P06, P10 to P17, P30, P31, Normal input buffer P40 to P43, P50 to P55, P70 to P77, (ITHL = 1) TYP. MAX. Unit 0.8 EVDD EVDD V 2.2 EVDD V P120, P140, P141, P146, P147 VIH2 P01, P03, P04, P13 to P17, P55 TTL input buffer 4.0 V ≤ EVDD ≤ 5.5 V VIH3 P20 to P27 0.7 VDD VDD V VIH4 P60 to P63 0.7 EVDD 6.0 V VIH5 P121 to P124, P137, RESET 0.8 VDD VDD V VIH6 P00 to P06, P10 to P17, P30, P31, Normal input buffer 0.8 EVDD EVDD V P40 to P43, P50 to P55, P70 to P77, (ITHL = 0) 0 0.2 EVDD V 0 0.8 V P120, P140, P141, P146, P147 Input voltage, VIL1 low P00 to P06, P10 to P17, P30, P31, Normal input buffer P40 to P43, P50 to P55, P70 to P77, (ITHL = 1) P120, P140, P141, P146, P147 VIL2 P01, P03, P04, P13 to P17, P55 TTL input buffer 4.0 V ≤ EVDD ≤ 5.5 V VIL3 P20 to P27 0 0.3 VDD V VIL4 P60 to P63 0 0.3 EVDD V VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2 VDD V VIL6 P00 to P06, P10 to P17, P30, P31, Normal input buffer 0 0.5 EVDD V P40 to P43, P50 to P55, P70 to P77, (ITHL = 0) 0 0.4 EVDD V P120, P140, P141, P146, P147 4.0 V ≤ EVDD ≤ 5.5 V Normal input buffer (ITHL = 0) 2.7 V ≤ EVDD < 4.0 V Cautions The maximum value of VIH of pins P00, P02 to P04, P10 to P15, P17, P50, P55, P71, P74 is VDD, even in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. The input pins of alternate-functions: CSIS0, CSIS1, UARTS, and UARTF, do not support TTL inputs. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1056 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. (TA = −40 to +125°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Items Symbol Output voltage, VOH1 Conditions P00 to P06, P10 to P17, P30, P31, MIN. 4.0 V ≤ EVDD ≤ 5.5 V, TYP. MAX. Unit EVDD − 0.9 V EVDD − 0.7 V EVDD − 0.5 V EVDD − 0.5 V P40 to P43, P50 to P55, P70 to P77, IOH1 = −5.0 mA high P120, P130, P140, P141, P146, P147 2.7 V ≤ EVDD ≤ 5.5 V, IOH1 = −3.0 mA 2.7 V ≤ EVDD ≤ 5.5 V, IOH1 = −1.0 mA VOH2 P20 to P27 2.7 V ≤ VDD ≤ 5.5 V, IOH2 = −100 μ A Output voltage, VOL1 P00 to P06, P10 to P17, P30, P31, 4.0 V ≤ EVDD ≤ 5.5 V, 0.7 V 0.4 V 0.7 V 0.4 V 0.4 V 2.0 V 0.4 V 0.5 V 0.4 V P40 to P43, P50 to P55, P70 to P77, IOL1 = 8.5 mA low P120, P130, P140, P141, P146, P147 4.0 V ≤ EVDD ≤ 5.5 V, IOL1 = 4.0 mA 2.7 V ≤ EVDD ≤ 5.5 V, IOL1 = 4.0 mA 2.7 V ≤ EVDD ≤ 5.5 V, IOL1 = 1.5 mA VOL2 P20 to P27 2.7 V ≤ VDD ≤ 5.5 V, IOL2 = 400 μ A VOL3 P60 to P63 4.0 V ≤ EVDD ≤ 5.5 V, IOL3 = 15.0 mA 4.0 V ≤ EVDD ≤ 5.5 V, IOL3 = 5.0 mA 2.7 V ≤ EVDD ≤ 5.5 V, IOL3 =4.0 mA 2.7 V ≤ EVDD ≤ 5.5 V, IOL3 = 3.0 mA Caution P00, P02 to P04, P10 to P15, P17, P50, P55, P71, P74 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1057 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. (TA = −40 to +125°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Items Input leakage Symbol ILIH1 Conditions P00 to P06, P10 to P17, P30, MIN. TYP. MAX. Unit VI = EVDD 1 μA 1 μA 1 μA 10 μA VI = EVSS −1 μA −1 μA −1 μA −10 μA 100 kΩ P31, P40 to P43, P50 to P55, current, high P60 to P63, P70 to P77, P120, P140, P141, P146, P147 ILIH2 P20 to P27, P137, RESET VI = VDD ILIH3 P121 to P124 VI = VDD (X1, X2, XT1, XT2) In input port or external clock input In resonator connection Input leakage ILIL1 P00 to P06, P10 to P17, P30, P31, P40 to P43, P50 to P55, current, low P60 to P63, P70 to P77, P120, P140, P141, P146, P147 ILIL2 P20 to P27, P137, RESET VI = VSS ILIL3 P121 to P124 VI = VSS (X1, X2, XT1, XT2) In input port or external clock input In resonator connection On-chip pll-up RU P00 to P06, P10 to P17, P30, 10 20 P31, P40 to P43, P50 to P55, resistance P70 to P77, P120, P140, P141, P146, P147 Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1058 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. 32.4.2 Supply current characteristics (TA = −40 to +125°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Supply current Symbol IDD1 Note 1 Conditions Operatin g mode High-speed Note 5 operation Subsystem clock operation (1/2) TYP. MAX. Unit fIH = 24 MHz Note 2 MIN. 4.5 6.9 mA fIH = 16 MHz Note 2 3.3 5.2 mA 4.0 5.9 mA 2.4 3.5 mA 4.9 13.0 μA fMX = 20 MHz Note 3 fMX = 10 MHz Note 3 fSUB = 32.768 kHz Note 4 TA ≤ + 85°C TA ≤ + 105°C 25.0 TA ≤ + 125°C 59.0 Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values in the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors (when high-speed on-chip oscillator or subsystem clock, not including the current flowing into the BGO too). 2. When high-speed system clock and subsystem clock are stopped. 3. When high-speed on-chip oscillator and subsystem clock are stopped. 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When watchdog timer is stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. High speed operation: VDD = 2.7 to 5.5 V@1 MHz to 24 MHz Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Temperature condition of the TYP. value is TA = 25°C R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1059 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. (TA = −40 to +125°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Supply current Symbol IDD2 Note 2 Note 1 (2/2) Conditions HALT mode High-speed operation Note 7 TYP. MAX. Unit fIH = 24 MHz Note 3 0.48 5.58 mA fIH = 16 MHz Note 3 0.40 3.90 mA TBD TBD mA fMX = 20 MHz Note 4 0.43 1.88 mA fMX = 10 MHz Note 4 0.28 1.02 mA TBD TBD mA 0.52 2.15 μA fIH = 8 MHz MIN. Note 3 fMX = 8 MHz Subsystem clock operation Note 4 fSUB = 32.768 kHz Note 5 TA≤ + 50°C 3.05 TA ≤ + 70°C IDD3 Note 6 STOP mode TA ≤ + 85°C 4.24 TA ≤ + 105°C 15.0 TA ≤ + 125°C 35.0 TA ≤ + 50°C 0.22 2.05 TA ≤ + 70°C 3.05 TA ≤ + 85°C 4.24 TA ≤ +105°C 15.0 TA ≤ + 125°C 35.0 μA Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values in the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors. 2. During HALT instruction execution by flash memory. 3. When high-speed system clock and subsystem clock are stopped. 4. When high-speed on-chip oscillator and subsystem clock are stopped. 5. When operating real-time clock (RTC) and setting ultra-low current consumption (AMPHS1 = 1). When highspeed on-chip oscillator and high-speed system clock are stopped. When watchdog timer is stopped. 6. When high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. When watchdog timer is stopped. 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. High speed operation: VDD = 2.7 to 5.5 V@1 MHz to 24 MHz Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Temperature condition of the TYP. value is TA = 25°C R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1060 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. (TA = −40 to +125°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter RTC operating Symbol IRTC Notes 1, 2 Conditions fSUB = 32.768 kHz current WUTM operating IWUTM MIN. TYP. MAX. Unit Real-time clock operation 0.02 0.17 μA Interval timer operation 0.02 0.37 μA fIL = 15 kHz 0.25 0.6 μA 0.22 0.6 μA current Watchdog timer IWDT Notes 2, 3 fIL = 15 kHz IADC Note 4 at maximum Normal mode, AVREFP = VDD = 5.0 V 1.3 1.7 mA conversion speed Low voltage mode, AVREFP = VDD = 3.0 V 0.5 0.7 mA operating current A/D converter operating current Internal reference voltage selected LVD operating ILVI Note 7 Note 5 μA 75 0.08 0.26 μA current Temperature ITMPS μA 75 sensor operating current BGO operating IBGO Note 6 2.5 12.2 mA current Notes 1. Current flowing only to the real-time clock (excluding the operating current of the XT1 oscillator). The TYP. value of the current value of the RL78/F12 is the sum of the TYP. values of either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode. The IDD1 and IDD2 MAX. values also include the realtime clock operating current. When the real-time clock operates during fCLK = fSUB, the TYP. value of IDD2 includes the real-time clock operating current. 2. When high-speed on-chip oscillator and high-speed system clock are stopped. 3. Current flowing only to the watchdog timer (including the operating current of the 15 kHz on-chip oscillator). The current value of the RL78/F12 is the sum of IDD1, IDD2 or IDD3 and IWDT when fCLK = fSUB when the watchdog timer operates in STOP mode. 4. Current flowing only to the A/D converter. The current value of the RL78/F12 is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. 5. Current flowing only to the LVD circuit. The current value of the RL78/F12 is the sum of IDD1, IDD2 or IDD3 and ILVI when the LVD circuit operates in the Operating, HALT or STOP mode. 6. Current flowing only to the BGO. The current value of the RL78/F12 is the sum of IDD1 or IDD2 and IBGO when the BGO operates in an operation mode or the HALT mode. 7. This indicates operating current which increases when the internal reference voltage is selected. The Current flows even if the conversion is stopped. Remarks 1. fIL: Low-speed on-chip oscillator clock frequency 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 3. fCLK: CPU/peripheral hardware clock frequency 4. Temperature condition of the TYP. value is TA = 25°C R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1061 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. 32.5 AC Characteristics 32.5.1 Basic operation (TA = −40 to +125°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Items Instruction cycle (minimum instruction execution time) Symbol TCY Conditions Main system clock (fMAIN) operation MIN. TYP. 0.04 MAX. Unit 1 μs 34.5 μs High-speed main mode Subsystem clock (fSUB) operation 28.5 30.5 External main system clock frequency fEX 1 20 MHz fEXS 29 35 kHz External main system clock input high-level width, low-level width tEXH, tEXL 24 ns tEXHS, tEXLS 13.7 μs TI00 to TI07 input high-level width, low-level width tTIH, tTIL 2/fMCK +10 ns TO00 to TO07 output frequency fTO PCLBUZ0, PCLBUZ1 output frequency fPCL Interrupt input high-level width, low-level width tINTH, tINTL Key interrupt input low-level width tKR RESET low-level width 4.0 V ≤ EVDD ≤ 5.5 V 16 MHz 2.7 V ≤ EVDD < 4.0 V 8 MHz 4.0 V ≤ EVDD ≤ 5.5 V 16 MHz 2.7 V ≤ EVDD < 4.0 V 8 MHz INTP0 to INTP11 KR0 to KR7 tRSL 1 μs 250 ns 10 μs Remark fMCK: Timer array unit operation clock frequency (Operation clock set by the CKS0n bit of Timer mode register 0n (TMR0n). n: Channel number (n = 0 to 7)) R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1062 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. 32.6 Peripheral Functions Characteristics 32.6.1 Serial array unit (1) During communication at same potential (UART mode) (dedicated baud rate generator output) (TA = −40 to +125°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Transfer rate Conditions MIN. Other than SNOOZE mode TYP. fMCK/256 Theoretical value of the maximum transfer rate Receivable baud rate at SNOOZE mode 4800 MAX. Unit fMCK/6 bps 4.0 Mbps 4800 bps UART mode connection diagram (during communication at same potential) Rx TxDq User's device RL78/F12 Tx RxDq UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register h (POMh). Remarks 1. 2. q: UART number (q = 0 to 2, S0), g: PIM number (g = 0, 1, 5, 7), h: POM number (h = 0, 1, 5, 7) fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 11, S0, S1)) R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1063 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. (2) During communication at same potential (CSI mode) (master mode, SCKp: internal clock output) (TA = −40 to +125°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter SCKp cycle time Symbol Note 1 tKCY1 Conditions 2.7 V ≤ EVDD ≤ 5.5 V CSI00 MIN. Note 1 Other than CSI00 SCKp high-/low-level width SIp setup time (to SCKp↑) Note 3 TYP. MAX. Unit 125 ns 166.6 ns Note 2 tKH1, 4.0 V ≤ EVDD ≤ 5.5 V tKCY1/2 − 12 ns tKL1 2.7 V ≤ EVDD ≤ 5.5 V tKCY1/2 − 18 ns tSIK1 44 ns tKSI1 19 ns SIp hold time (from SCKp↑) SOp output delay time Note 3 Note 4 tKSO1 C = 30 pF Note 5 ns 25 ns (from SCKp↓) Notes 1. The value must also be 2/fCLK or more. 2. The value must also be 4/fCLK or more. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 5. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register h (POMh). Remark p: CSI number (p = 00, 01, 10, 11, 20, 21, S0, S1), m: Unit number (m = 0, 1, S), n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 5, 7), h: POM number (h = 0, 1, 5, 7) R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1064 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. (3) During communication at same potential (CSI mode) (slave mode, SCKp: external clock input) (TA = −40 to +125°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter SCKp cycle time Symbol tKCY2 Conditions 4.0 V ≤ EVDD ≤ 5.5 V 2.7 V ≤ EVDD < 4.0 V MIN. TYP. MAX. Unit fMCK > 20 MHz 8/fMCK ns fMCK ≤ 20 MHz 6/fMCK fMCK > 16 MHz 8/fMCK ns fMCK ≤ 16 MHz 6/fMCK ns tKCY2/2 ns SCKp high-/low-level width tKH2, tKL2 SIp setup time Note 1 (to SCKp↑) tSIK2 2.7 V ≤ EVDD ≤ 5.5 V 1/fMCK+20 ns SIp hold time Note 1 (from SCKp↑) tKSI2 2.7 V ≤ EVDD ≤ 5.5 V 1/fMCK+31 ns SOp output Delay time Note 2 (from SCKp↓) tKSO2 C = 30 pF Note 3 2.7 V ≤ EVDD ≤ 5.5 V 2/fMCK+44 ns Notes 1. This applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time is “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. This applies when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output is “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. C is the load capacitance of the SOp output lines. Caution Select the TTL input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register h (POMh). Remarks 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, S0, S1), m: Unit number (m = 0, 1, S), n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 5), h: POM number (h = 0, 1, 5, 7) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10, 11, S0, S1)) R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1065 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. CSI mode connection diagram (during communication at same potential) SCK SCKp RL78/F12 SIp SO SOp SI User's device CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1, 2 tKL1, 2 tKH1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 Output data SOp CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1, 2 tKH1, 2 tKL1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 SOp Remarks 1. 2. Output data p: CSI number (p = 00, 01, 10, 11, 20, 21, S0, S1) m: Unit number, n: Channel number (mn = 00 to 03, 10, 11, S0, S1) R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1066 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. 2 (4) During communication at same potential (simplified I C mode) (TA = −40 to +125°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter SCLr clock frequency Symbol fSCL Conditions MIN. 2.7 V ≤ EVDD ≤ 5.5 V MAX. Unit 400 kHz Cb = 100 pF, Rb = 3 kΩ Hold time when SCLr = “L” tLOW Hold time when SCLr = “H” tHIGH 2.7 V ≤ EVDD ≤ 5.5 V 1150 ns 1150 ns 1/fMCK + 145 ns Cb = 100 pF, Rb = 3 kΩ 2.7 V ≤ EVDD ≤ 5.5 V Cb = 100 pF, Rb = 3 kΩ Data setup time (reception) tSU:DAT 2.7 V ≤ EVDD ≤ 5.5 V Cb = 100 pF, Rb = 3 kΩ Data hold time (transmission) tHD:DAT 2.7 V ≤ EVDD ≤ 5.5 V Note 0 355 ns Cb = 100 pF, Rb = 3 kΩ Note The value of fMCK must be such that this does not exceed the hold time for SCLr = L or the hold time for SCLr = H. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1067 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. 2 Simplified I C mode mode connection diagram (during communication at same potential) VDD Rb SDA SDAr User's device RL78/F12 SCL SCLr 2 Simplified I C mode serial transfer timing (during communication at same potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD:DAT tSU:DAT Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh). Remarks 1. Rb[Ω]:Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance 2. r: IIC number (r = 00, 01, 11, 20, 21), g: PIM number (g = 0, 1, 5), h: POM number (h = 0, 1, 5, 7) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10, 11, S0, S1) R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1068 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. 32.6.2 Serial interface IICA (TA = −40 to +125°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Standard Conditions Fast Mode Fast Mode MIN. SCLA0 clock frequency fSCL MAX. 0 Normal mode:fCLK ≥ 1 MHz Note 1 MIN. MAX. Fast mode plus:fCLK ≥ 10 MHz Fast mode:fCLK ≥ 3.5 MHz 0 Unit Plus Mode MIN. MAX. 0 1000 400 kHz kHz 100 kHz tSU:STA 4.7 0.6 0.26 μs Hold time tHD:STA 4.0 0.6 0.26 μs Hold time when SCLA0 = “L” tLOW 4.7 1.3 0.5 μs Hold time when SCLA0 = “H” tHIGH 4.0 0.6 0.26 μs tSU:DAT 250 100 50 ns tHD:DAT 0 0 μs Setup time of stop condition tSU:STO 4.0 0.6 0.26 μs Bus-free time tBUF 4.7 1.3 0.5 μs Setup time of restart condition Data setup time (reception) Data hold time (transmission) Notes 1. 2. Remark Note 2 3.45 0 0.9 The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 kΩ Fast mode: Cb = 320 pF, Rb = 1.1 kΩ Fast mode plus: Cb = 120 pF, Rb = 1.1 kΩ IICA serial transfer timing tLOW SCL0 tHD:DAT tHD:STA tHIGH tSU:STA tHD:STA tSU:STO tSU:DAT SDA0 tLOW Stop condition Start condition R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 Restart condition Stop condition 1069 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. 32.6.3 LIN-UART (TA = −40 to +125°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Transfer rate Conditions MIN. Note MAX. 1 Unit Mbps Note However, the upper limit is fCLK/8. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1070 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. 32.7 Analog Characteristics 32.7.1 A/D converter characteristics (1) When the setting of AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1) and AVREF (-) = AVREFM/ANI1 (ADREFM = 1), this applies to the following ANI pins: ANI2 to ANI7 (the ANI pins for which VDD is the power-supply voltage). (TA = −40 to +125°C, 2.7 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, reference voltage (+) = AVREFP, reference voltage (-) = AVREFM = 0 V) Parameter Symbol Resolution Overall error Conditions RES Note 1 AINL Conversion time Zero-scale error Full-scale error tCONV Notes 1, 2 Notes 1, 2 Integral linearity error Note 1 Differential linearity error Note 1 MIN. TYP. 8 10-bit resolution 10-bit resolution MAX. Unit 10 bit 4.0 V ≤ VDD ≤ 5.5 V 1.2 ±3.0 LSB 2.7 V ≤ VDD < 4.0 V 1.2 ±3.5 LSB 4.0 V ≤ VDD ≤ 5.5 V 2.125 39 μs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 μs EZS 10-bit resolution 2.7 V ≤ VDD ≤ 5.5 V ±0.25 %FSR EFS 10-bit resolution 2.7 V ≤ VDD ≤ 5.5 V ±0.25 %FSR ILE 10-bit resolution 2.7 V ≤ VDD ≤ 5.5 V ±2.5 LSB DLE 10-bit resolution 2.7 V ≤ VDD ≤ 5.5 V ±1.5 LSB VDD V Reference voltage (+) AVREFP Reference voltage (-) AVREFM Analog input voltage VAIN VBGR 2.7 0 AVREFM 2.7 V ≤ VDD ≤ 5.5 V 1.38 1.45 V AVREFP V 1.5 V Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. Caution The pins mounted depend on the product. Refer to 2.1.1, 20-pin products to 2.1.5, 64-pin products, and 2.1.6, Pins for each product (pins other than port pins). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1071 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) (2) When the setting of AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1) and AVREF (-) = AVREFM/ANI1 (ADREFM = 1), this applies to the following ANI pins: ANI16 to ANI19 (the ANI pins for which EVDD0 is the power-supply voltage). (TA = −40 to +125°C, 2.7 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, reference voltage (+) = AVREFP, reference voltage (-) = AVREFM = 0 V) Parameter Symbol Resolution Overall error Conditions RES Note 1 AINL Conversion time Zero-scale error Full-scale error tCONV Notes 1, 2 Notes 1, 2 Integral linearity error Note 1 Differential linearity error Note 1 MIN. TYP. 8 10-bit resolution 10-bit resolution MAX. Unit 10 bit 4.0 V ≤ VDD ≤ 5.5 V 1.2 ±4.5 LSB 2.7 V ≤ VDD < 4.0 V 1.2 ±5.0 LSB 4.0 V ≤ VDD ≤ 5.5 V 2.125 39 μs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 μs EZS 10-bit resolution 2.7 V ≤ VDD ≤ 5.5 V ±0.35 %FSR EFS 10-bit resolution 2.7 V ≤ VDD ≤ 5.5 V ±0.35 %FSR ILE 10-bit resolution 2.7 V ≤ VDD ≤ 5.5 V ±3.5 LSB DLE 10-bit resolution 2.7 V ≤ VDD ≤ 5.5 V ±2.0 LSB VDD V Reference voltage (+) AVREFP Reference voltage (-) AVREFM Analog input voltage VAIN VBGR 2.7 0 AVREFM 2.7 V ≤ VDD ≤ 5.5 V 1.38 1.45 V AVREFP V 1.5 V Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. Caution The pins mounted depend on the product. Refer to 2.1.1, 20-pin products to 2.1.5, 64-pin products, and 2.1.6, Pins for each product (pins other than port pins). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1072 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) (3) When the setting of AVREF (+) = VDD (ADREFP1 = 0, ADREFP0 = 0) and AVREF (-) = VSS (ADREFM = 0), this applies to the following ANI pins: ANI0 to ANI7. (TA = −40 to +125°C, 2.7 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, reference voltage (+) = VDD, reference voltage (-) = VSS) Parameter Symbol Resolution Overall error Conditions MIN. RES Note 1 AINL Conversion time Zero-scale error Full-scale error tCONV Notes 1, 2 Notes 1, 2 Integral linearity error Note 1 Differential linearity error Note 1 TYP. 8 10-bit resolution 10-bit resolution MAX. Unit 10 bit 4.0 V ≤ VDD ≤ 5.5 V ANI0-ANI7 1.2 ±5.0 LSB 2.7 V ≤ VDD < 5.5 V ANI0-ANI7 1.2 ±5.5 LSB 4.0 V ≤ VDD ≤ 5.5 V 2.125 39 μs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 μs EZS 10-bit resolution 2.7 V ≤ VDD ≤ 5.5 V ±0.5 %FSR EFS 10-bit resolution 2.7 V ≤ VDD ≤ 5.5 V ±0.5 %FSR ILE 10-bit resolution 2.7 V ≤ VDD ≤ 5.5 V ±3.5 LSB DLE 10-bit resolution 2.7 V ≤ VDD ≤ 5.5 V ±2.0 LSB Reference voltage (+) AVREFP VDD V Reference voltage (-) AVREFM VSS V Analog input voltage VAIN ANI0-ANI7 VSS VBGR 2.7 V ≤ VDD ≤ 5.5 V 1.38 1.45 VDD V 1.5 V Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. Caution The pins mounted depend on the product. Refer to 2.1.1, 20-pin products to 2.1.5, 64-pin products, and 2.1.6, Pins for each product (pins other than port pins). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1073 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) (4) When the setting of AVREF (+) = VDD (ADREFP1 = 0, ADREFP0 = 0) and AVREF (-) = VSS (ADREFM = 0), this applies to the following ANI pins: ANI16 to ANI19. (TA = −40 to +125°C, 2.7 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, reference voltage (+) = VDD, reference voltage (-) = VSS) Parameter Symbol Resolution Overall error Conditions MIN. RES Note 1 AINL Conversion time Zero-scale error Full-scale error tCONV Notes 1, 2 Notes 1, 2 Integral linearity error Note 1 Differential linearity error Note 1 TYP. 8 10-bit resolution 10-bit resolution MAX. Unit 10 bit 4.0 V ≤ VDD ≤ 5.5 V ANI16-ANI19 1.2 ±6.5 LSB 2.7 V ≤ VDD < 5.5 V ANI16-ANI19 1.2 ±7.0 LSB 4.0 V ≤ VDD ≤ 5.5 V 2.125 39 μs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 μs EZS 10-bit resolution 2.7 V ≤ VDD ≤ 5.5 V ±0.60 %FSR EFS 10-bit resolution 2.7 V ≤ VDD ≤ 5.5 V ±0.60 %FSR ILE 10-bit resolution 2.7 V ≤ VDD ≤ 5.5 V ±4.0 LSB DLE 10-bit resolution 2.7 V ≤ VDD ≤ 5.5 V ±2.0 LSB Reference voltage (+) AVREFP VDD V Reference voltage (-) AVREFM VSS V Analog input voltage VAIN ANI16-ANI19 VSS VBGR 2.7 V ≤ VDD ≤ 5.5 V 1.38 1.45 VDD V 1.5 V Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. Caution The pins mounted depend on the product. Refer to 2.1.1, 20-pin products to 2.1.5, 64-pin products, and 2.1.6, Pins for each product (pins other than port pins). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1074 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. 32.7.2 Temperature sensor characteristics (TA = −40 to +125°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Conditions Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25°C Reference output voltage VCONST Setting ADS register = 81H Temperature coefficient FVTMPS Temperature sensor that depends on the MIN. TYP. MAX. 1.05 1.38 1.45 Unit V 1.5 −3.6 V mV/C temperature Operation stabilization wait time tAMP 5 μs 32.7.3 POR circuit characteristics (TA = −40 to +125°C, VSS = 0 V) Parameter Detection voltage Symbol MIN. TYP. MAX. Unit VPOR Power supply rise time 1.46 1.51 1.59 V VPDR Power supply fall time 1.45 1.50 1.58 V Minimum pulse width TPW Detection delay time TPD R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 Conditions μs 300 350 μs 1075 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) 32.7.4 LVD circuit characteristics (a) Characteristics for LVD Detection at Reset and Interrupt modes (TA = −40 to +125°C, VPDR ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Detection Supply voltage level Symbol VLVI0 voltage VLVI1 VLVI2 VLVI3 VLVI4 VLVI5 Conditions MIN. TYP. MAX. Unit Power supply rise time 3.96 4.06 4.25 V Power supply fall time 3.89 3.98 4.15 V Power supply rise time 3.66 3.75 3.93 V Power supply fall time 3.58 3.67 3.83 V Power supply rise time 3.06 3.13 3.28 V Power supply fall time 2.99 3.06 3.20 V Power supply rise time 2.95 3.02 3.17 V Power supply fall time 2.89 2.96 3.09 V Power supply rise time 2.85 2.92 3.07 V Power supply fall time 2.79 2.86 2.99 V Power supply rise time 2.74 2.81 2.95 V 2.75 2.88 V Power supply fall time Minimum pulse width tLW Detection delay time tLD Note 2.68 Note μs 300 300 μs The minimum value lowers the minimum guaranteed voltage for operation(2.7V). However, LVD detection performs in the same way as in normal mode (operation according to the same specification when VDD is 2.7V) until it is reset at reset mode. Remark VLVI(n − 1) > VLVIn: n = 1 to 13 The following relationship is formed under the same temperature conditions: the detection voltage at power supply rise time > the detection voltage at power supply fall time. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1076 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. (b) LVD Detection Voltage of Interrupt & Reset Mode (TA = −40 to +125°C, VPDR ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol Interrupt and reset VLVI5 mode VLVI4 Conditions VPOC0, VPOC1, VPOC2 = 0, 1, 1, falling reset voltage: 2.7 V LVIS1, LVIS0 = 1, 0 Rising release reset voltage Falling interrupt voltage VLVI3 LVIS1, LVIS0 = 0, 1 Rising release reset voltage Falling interrupt voltage VLVI0 LVIS1, LVIS0 = 0, 0 Rising release reset voltage Falling interrupt voltage Note MIN. TYP. MAX. Unit 2.75 2.88 V 2.85 2.92 3.07 V 2.79 2.86 2.99 V 2.95 3.02 3.17 V 2.89 2.96 3.09 V 3.96 4.06 4.25 V 3.89 3.98 4.15 V 2.68 Note The minimum value lowers the minimum guaranteed voltage for operation(2.7V). However, LVD detection performs in the same way as in normal mode (operation according to the same specification when VDD is 2.7V) until it is reset at reset mode. Remark The following relationship is formed under the same temperature conditions: the rising release reset voltage > the falling interrupt voltage > the falling reset voltage 32.7.5 Power supply rise time (TA = −40 to +125°C, VSS = EVSS = 0 V) Parameter Maximum slew rate for the supply Symbol Conditions Svrmax 0 V → 2.7 V (CMODE0 = 1) (VPOC2 = 0 or 1) Svrmin 0 V → 2.7 V (CMODE0 = 1) MIN. TYP. MAX. 50 Note 1 Unit V/ms voltage to rise Minimum slew rate for the supply voltage to rise 6.5 Note 1 V/ms Note 2 Notes 1. In case the supply voltage falls to a level of VPDR or below and a power-on reset is generated, the slew rate 2. The minimum slew rate for the supply voltage (Svrmin) must be met when the voltage detector (LVD) is not must not exceed the value Svrmax even if the supply voltage does not go down to 0 V. used (option byte bit VPOC2 = 1) and an external reset circuit releases before the supply voltage reaches VDD (MIN.) (here 2.7 V). R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1077 RL78/F12 CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) Caution The pins mounted depend on the product. 32.8 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +125°C VSS = EVSS = 0 V) Parameter Data retention supply voltage Symbol VDDDR Conditions STOP mode MIN. 1.45 TYP. Note MAX. Unit 5.5 V Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is effected, but data is not retained when a POR reset is effected. Operation mode STOP mode Data retention mode VDD VDDDR STOP instruction execution Standby release signal (interrupt request) 32.9 Flash Memory Programming Characteristics (TA = −40 to +125°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V) Parameter Symbol System clock frequency fCLK Number of code flash rewrites Cerwr Notes 1, 2, 3 Conditions 20 years retention (after rewrite) TA = +85°C Erase time Block erase write time Unit 24 MHz Times 10000 Note 4 5 years retention (after rewrite) TA = +85°C 1000 MAX. Note 4 20 years retention (after rewrite) Notes 1, 2, 3 TYP. 1 TA = +85°C Number of data flash rewrites MIN. 100000 Note 4 Terasa 5 ms Twrwa 10 μs Notes 1. Retention years indicate a period between time for a rewrite and the next. 2. When using flash memory programmer and Renesas Electronics self programming library. 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas. 4. The specified data retention time is given under the condition that the average temperature (TA) is 85°C or below. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1078 RL78/F12 CHAPTER 33 PACKAGE DRAWING CHAPTER 33 PACKAGE DRAWING 33.1 20-pin products 20-PIN PLASTIC SSOP (7.62 mm (300)) 20 11 detail of lead end F G T P L U E 1 10 A H J I S N S K C D M M B NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 6.65±0.15 B 0.475 MAX. C 0.65 (T.P.) D 0.24 +0.08 −0.07 E 0.1±0.05 F 1.3±0.1 G 1.2 H 8.1±0.2 I 6.1±0.2 J 1.0±0.2 K 0.17±0.03 L 0.5 M 0.13 N 0.10 P 3° +5° −3° T 0.25 U 0.6±0.15 S20MC-65-5A4-2 R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1079 RL78/F12 CHAPTER 33 PACKAGE DRAWING 33.2 30-pin products 30-PIN PLASTIC SSOP (7.62 mm (300)) 30 16 detail of lead end F G T P 1 L 15 U E A H I J S C D N M S B M NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. K ITEM A MILLIMETERS 9.85±0.15 B 0.45 MAX. C 0.65 (T.P.) D 0.24 +0.08 −0.07 E 0.1±0.05 F 1.3±0.1 G 1.2 H 8.1±0.2 I 6.1±0.2 J 1.0±0.2 K 0.17±0.03 L 0.5 M 0.13 N 0.10 P 3° +5° −3° T 0.25 U 0.6±0.15 S30MC-65-5A4-2 R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1080 RL78/F12 CHAPTER 33 PACKAGE DRAWING 33.3 32-pin products 32-PIN PLASTIC WQFN(5x5) D DETAIL OF A PART E S A A S y S D2 A EXPOSED DIE PAD 1 (UNIT:mm) 8 ITEM 9 32 B D 5.00 ± 0.05 E 5.00 ± 0.05 A e 0.75 ± 0.05 + 0.25 − 0.05 0.07 0.50 Lp 0.40 ± 0.10 b E2 x 25 y 16 DIMENSIONS 0.05 0.05 P32K8-50-3B4-2 17 24 Lp e b x R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 M S AB ITEM EXPOSED DIE PAD VARIATIONS D2 E2 MIN NOM MAX MIN NOM MAX A 3.45 3.50 3.55 3.45 3.50 3.55 1081 RL78/F12 CHAPTER 33 PACKAGE DRAWING 33.4 48-pin products 48-PIN PLASTIC LQFP (FINE PITCH)(7x7) HD D detail of lead end 36 25 37 A3 24 c θ E L Lp HE L1 13 48 12 1 (UNIT:mm) ZE e ZD b x M S A A2 ITEM D DIMENSIONS 7.00±0.20 E 7.00±0.20 HD 9.00±0.20 HE 9.00±0.20 A 1.60 MAX. A1 0.10±0.05 A2 1.40±0.05 A3 b S c L y S NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. A1 Lp 0.60±0.15 L1 θ 1.00±0.20 3° +5° −3° e 0.50 x 0.08 y 0.08 ZD 0.75 ZE R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 0.25 0.22±0.05 0.145 +0.055 −0.045 0.50 0.75 P48GA-50-8EU 1082 RL78/F12 CHAPTER 33 PACKAGE DRAWING 48-PIN PLASTIC WQFN(7x7) D DETAIL OF E S A PART A A S y S D2 A EXPOSED DIE PAD 1 (UNIT:mm ) 12 ITEM 13 48 B E2 D 7.00 ± 0.05 E 7.00 ± 0.05 A 0.75 ± 0.05 b + 0.25 − 0.05 0.07 e Lp x y 37 24 36 DIMENSIONS 0.50 0.40 ± 0.10 0.05 0.05 P48K8-50-5B4-3 25 Lp e b R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 x M S AB ITEM EXPOSED DIE PAD VARIATIONS D2 E2 MIN NOM MAX MIN NOM MAX A 5.45 5.50 5.55 5.45 5.50 5.55 1083 RL78/F12 CHAPTER 33 PACKAGE DRAWING 33.5 64-pin products 64-PIN PLASTIC LQFP(FINE PITCH)(10x10) HD D detail of lead end 48 33 49 A3 32 c θ E L Lp HE L1 (UNIT:mm) 17 64 1 16 ZE e ZD b x M S A ITEM D DIMENSIONS 10.00±0.20 E 10.00±0.20 HD 12.00±0.20 HE 12.00±0.20 A 1.60 MAX. A1 0.10±0.05 A2 1.40±0.05 A3 b A2 c S y S NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 A1 L 0.25 0.22±0.05 0.145 +0.055 −0.045 0.50 Lp 0.60±0.15 L1 θ 1.00±0.20 3° +5° −3° e 0.50 x 0.08 y 0.08 ZD 1.25 ZE 1.25 P64GB-50-UEU-1 1084 RL78/F12 APPENDIX A REVISION HISTORY APPENDIX A REVISION HISTORY A.1 Major Revisions in This Edition (1/2) Page Description Classification How to Use This Manual d, e The whole descriptions changed. (c), (e) CHAPTER 1 OUTLINE p.3 1.2 Ordering Information: Note added. (c) p.8 48-pin plastic WQFN (7 × 7): Remark 3 added. (c) CHAPTER 2 PIN FUNCTIONS p.27 2.1.6 Pins for each product (pins other than port pins): Descriptions changed. (c) CHAPTER 3 CPU ARCHITECTURE Figure 3-1. Memory Map (R5F10968) to Figure 3-6. Memory Map (R5F109xE (x = 6, A, B, G, L)): p.44 to 49 (c) Description of Note 1 modified. CHAPTER 5 CLOCK GENERATOR Figure 5-2. Format of Clock Operation Mode Control Register (CMC): Descriptions of the AMPH bit and p.179 (b) Caution 3 changed. Figure 5-9. Format of High-Speed On-Chip Oscillator Frequency Select Register (HOCODIV): incorrect p.191 (a) descriptions modified. Figure 5-15. Clock Generator Operation When Power Supply Voltage Is Turned On: Descriptions of p.200 (b), (c) Figure and Note 3 modified. CHAPTER 12 A/D CONVERTER p.392 to 397 Table 12-3. A/D Conversion Time Selection (1/6) to Table 12-3. A/D Conversion Time Selection (6/6): (c) Descriptions added. CHAPTER 13 SERIAL ARRAY UNIT p.459 Figure 13-7. Format of Serial Clock Select Register m (SPSm): Incorrect description of Note modified. (c) p.478 13.3 (14) Serial standby control register 0 (SSC0): Caution modified. (c) p.568 Table 13-2. Selection of Operation Clock For 3-Wire Serial I/O: Incorrect description of Note modified. (c) p.593 Figure 13-102. Flowchart of UART Reception: Incorrect description in flowchart modified. (a) p.594, 595 13.6.3 SNOOZE mode function (only UART0 reception): Descriptions added. (c) p.635 2 Table 13-5. Selection of Operation Clock For Simplified I C: Incorrect description of Note modified. (c) CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) p.682 Figure 14-30. BF Transmission Processing Flow: Incorrect description of Note modified. (a) p.714 14.7.4 Automatic checksum function: Incorrect description of Note modified. (c) p.715 Figure 14-61. Automatic Checksum Error Occurrence Example (Response Reception): Incorrect (a) description modified. CHAPTER 18 INTERRUPT FUNCTIONS p.865 Table 18-2. Flags Corresponding to Interrupt Request Sources (5/5): Incorrect descriptions modified. (a) p.866 Figure 18-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) (64-pin) (a) (1/2): Incorrect descriptions modified. Remark: “Classification” in the above table classifies revisions as follows. (a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d): Addition/change of package, part number, or management division, (e): Addition/change of related documents R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1085 RL78/F12 APPENDIX A REVISION HISTORY (2/2) Page Description Classification Figure 18-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H) (64- (a) CHAPTER 18 INTERRUPT FUNCTIONS p.868 pin): Incorrect descriptions modified. p.870 Figure 18-4. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, (a) PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) (64-pin) (2/2): Incorrect descriptions modified. CHAPTER 20 STANDBY FUNCTION p.896, 897 Figure 20-5. STOP Mode Release by Interrupt Request Generation: Descriptions modified. (c) p.899 20.2.3 SNOOZE mode: Descriptions modified. (b) CHAPTER 22 POWER-ON-RESET CIRCUIT p.916 Figure 22-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage (c) Detector (1/2): Descriptions of Notes in Figure modified. CHAPTER 27 FLASH MEMORY p.977 27.4.3 Procedure for accessing data flash memory: Caution 4 added. (b) CHAPTER 31 ELECTRICAL SPECIFICATIONS (J GRADE) p.1016 Caution 1 deleted. (c) p.1031 31.6.1 (1) During communication at same potential (UART mode) (dedicated baud rate generator (b) output): Incorrect descriptions modified. p.1032 31.6.1 (2) During communication at same potential (CSI mode) (master mode, SCKp: internal clock (a) output): Incorrect descriptions modified. p.1046 31.7.5 Power supply rise time: Descriptions modified. (c) p.1047 31.9 Flash Memory Programming Characteristics: Descriptions modified. (c) CHAPTER 32 ELECTRICAL SPECIFICATIONS (K GRADE) p.1048 Caution 1 deleted. (c) p.1063 32.6.1 (1) During communication at same potential (UART mode) (dedicated baud rate generator (b) output): Incorrect descriptions modified. p.1077 32.7.5 Power supply rise time: Descriptions modified. (c) p.1078 32.9 Flash Memory Programming Characteristics: Descriptions modified. Note 4 added. (c) Remark: “Classification” in the above table classifies revisions as follows. (a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d): Addition/change of package, part number, or management division, (e): Addition/change of related documents R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1086 RL78/F12 APPENDIX A REVISION HISTORY A.2 Revision History of Preceding Edition (1/2) Edition Rev.1.01 Description Chapter 1.6 Outline of Functions (2/2): Description of 8/10-bit resolution A/D converter, number of vectored CHAPTER 1 interrupt sources, power-on-reset circuit and voltage detector modified. OUTLINE 2.1.6 Pins for each product (pins other than port pins) (1/3): PCLBUZ0D and REGC modified. CHAPTER 2 2.2.14 REGC: Description modified. PIN FUNCTIONS 4.2.6 Port 5: Description, Table 4-8. Register Settings When Using Port 5, and Notes 1 and 3 CHAPTER 4 modified and Important added. PORT FUNCTIONS 6.3 (10) Timer output register 0 (TO0): Description modified and Note added. CHAPTER 6 6.3 (15) Port mode registers 0, 1, 3, 4 (PM0, PM1, PM3, PM4): Description modified and Remark TIMER ARRAY UNIT added. Figure 7-17. Procedure for Starting Operation of Real-time Clock: Modified. CHAPTER 7 Figure 7-19. Procedure for Reading Real-time Clock: Note 1 added. REAL-TIME CLOCK 11.1 Functions of Watchdog Timer: Description modified. CHAPTER 11 11.4.3 Setting window open period of watchdog timer: Remark modified. WATCHDOG TIMER 11.4.4 Setting watchdog timer interval interrupt: Description modified. Table 11-5. Setting of Watchdog Timer Interval Interrupt: Description modified. 12.2 Configuration of A/D Converter: Description and Remark modified, and Caution added. CHAPTER 12 A/D CONVERTER Figure 13-11. Serial Data Register mn (SDRmn) (mn = 00-03, 10, 11): Description modified. CHAPTER 13 13.3 (12) Serial output register m (SOm): Description, Figure 13-19. Format of Serial Output SERIAL ARRAY Register m (SOm), and Caution modified. UNIT Figure 13-27. Format of Port Mode Registers X0 to X4 (PMX0 to PMX4) (64-pin products): Description modified. Figure 13-57. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21) (1/2): Description modified. 13.5.5 Slave reception: Interrupt, and Notes 1 and 2 modified. 13.5.6 Slave transmission/reception: Target channel, interrupt, and Notes 1 and 2 modified. Figure 13-77. Procedure for Resuming Slave Transmission/Reception: Supplement modified. 13.5.7 SNOOZE mode function (only CSI00): Description and Caution modified. 13.8.1 Address field transmission: Error detection flag and Note modified. 2 Table 13-4. Selection of Operation Clock for Simplified I C: Description modified. Figure 14-1. Block Diagram of Asynchronous Serial Interface LIN-UART: Description modified. CHAPTER 14 14.5.6 BF reception: Description modified. ASYNCHRONOUS Figure 14-54. Example of BF/SF Reception Failure: Description modified. SERIAL INTERFACE LIN-UART (UARTF) Figure 14-55. Example of Successful BF, SF, and PID reception: Description modified. Figure 14-56. Example of Successful BF Reception During SF Reception (No PID Reception Error): Description modified. Figure 16-5. Format of Multiplication/Division Control Register (MDUC): Description modified. CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLYACCUMULATOR Table 18-1. Interrupt Source List (1/3): Description modified. CHAPTER 18 INTERRUPT FUNCTIONS R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 1087 RL78/F12 APPENDIX A REVISION HISTORY (2/2) Edition Rev.1.01 Description Chapter Figure 23-10. Delay from the Time LVD Reset Source is Generated until the Time LVD Reset Has CHAPTER 23 been Generated or Released: Description modified. VOLTAGE DETECTOR Figure 27-1. Environment for Wiring Program to Flash Memory: Description modified. CHAPTER 27 27.1.2 Communication Mode: Transfer rate changed. FLASH MEMORY Figure 27-2. Communication with Dedicated Flash Memory Programmer: Description modified, Note 1 deleted. Figure 28-2. Memory Spaces Where Debug Monitor Programs Are Allocated: Description and Notes CHAPTER 28 1 to 3 modified, and Note 4 added. ON-CHIP DEBUG FUNCTION 31.7.2 Temperature sensor characteristics: Description modified. CHAPTER 31 31.7.3 POR circuit characteristics: Description modified and Notes 1 and 2 added. ELECTRICAL 31.7.5 Supply Power Rise Time: Description modified. SPECIFICATIONS (J GRADE) 32.7.2 Temperature sensor characteristics: Description modified. CHAPTER 32 32.7.5 LVD circuit characteristics: Remark modified and section number changed to 32.7.4. ELECTRICAL 32.7.4 Supply Power Rise Time: Description modified and chapter number changed to 32.7.5. R01UH0231EJ0111 Rev.1.11 Jan 31, 2014 SPECIFICATIONS (K GRADE) 1088 RL78/F12 User’s Manual: Hardware Publication Date: Rev.1.11 Jan 31, 2014 Published by: Renesas Electronics Corporation http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. California Eastern Laboratories, Inc. 4590 Patrick Henry Drive, Santa Clara, California 95054, U.S.A. Tel: +1-408-919-2500, Fax: +1-408-988-0279 Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K Tel: +44-1628-651-700, Fax: +44-1628-651-804 Renesas Electronics Europe GmbH Arcadiastrasse 10, 40472 D üsseldorf, Germany Tel: +49-211-65030, Fax: +49-211-6503-1327 Renesas Electronics (China) Co., Ltd. 7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China Tel: +86-10-8235-1155, Fax: +86-10-8235-7679 Renesas Electronics (Shanghai) Co., Ltd. Unit 301, Tower A, Central Towers, 555 LanGao Rd., Putuo District, Shanghai, China Tel: +86-21-2226-0888, Fax: +86-21-2226-0999 Renesas Electronics Hong Kong Limited Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong Tel: +852-2886-9318, Fax: +852 2886-9022/9044 Renesas Electronics Taiwan Co., Ltd. 13F, No. 363, Fu Shing North Road, Taipei, Taiwan Tel: +886-2-8175-9600, Fax: +886 2-8175-9670 Renesas Electronics Singapore Pte. Ltd. 80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre Singapore 339949 Tel: +65-6213-0200, Fax: +65-6213-0300 Renesas Electronics Malaysia Sdn.Bhd. Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: +60-3-7955-9390, Fax: +60-3-7955-9510 Renesas Electronics Korea Co., Ltd. 12F., 234 Teheran-ro, Gangnam-Gu, Seoul, 135-080, Korea Tel: +82-2-558-3737, Fax: +82-2-558-5141 © 2014 Renesas Electronics Corporation. All rights reserved. Colophon 2.0 RL78/F12 R01UH0231EJ0111