User’s Manual
16
RL78/D1A
User’s Manual: Hardware
16-Bit Single-Chip Microcontrollers
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
Rev.1.10
Mar 2015
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you
or third parties arising from the use of these circuits, software, or information.
2.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
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Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of
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You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
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damages arising out of the use of Renesas Electronics products beyond such specified ranges.
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(2012.4)
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a wrist
strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken
for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the device.
How to Use This Manual
Readers
This manual is intended for user engineers who wish to understand the functions of the
RL78/D1A and design and develop application systems and programs for these devices.
The target products are as follows.
48-pin:
R5F10CGxJ, R5F10DGxJ, R5F10CGxL, R5F10DGxL (x = B, C, D)
64-pin:
R5F10CLDJ, R5F10DLxJ, R5F10CLDL, R5F10DLxL (x = D, E)
80-pin:
R5F10CMxJ, R5F10CMxL (x = D, E)
100-pin:
R5F10DPxJ, R5F10DPxL (x = E, F, G, J)
R5F10DMxJ, R5F10DMxL (x = D, E, F, G, J)
R5F10TPJJ, R5F10TPJL
Purpose
This manual is intended to give users an understanding of the functions described in the
Organization below.
Organization
The RL78/D1A manual is separated into two parts: this manual and the instructions edition
(common to the RL78 Microcontroller).
RL78/D1A
RL78 Microcontroller
User’s Manual
User’s Manual
(This Manual)
Instructions
Pin functions
CPU functions
Internal block functions
Instruction set
Interrupts
Explanation of each instruction
Other on-chip peripheral functions
Electrical specifications (target)
How to Read This Manual
It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
To gain a general understanding of functions:
Read this manual in the order of the CONTENTS. The mark “” shows major
revised points. The revised points can be easily searched by copying an “” in the
PDF file and specifying it in the “Find what:” field.
How to interpret the register format:
For a bit number enclosed in angle brackets, the bit name is defined as a reserved
word in the assembler, and is defined as an sfr variable using the #pragma sfr
directive in the compiler.
To know details of the RL78 Microcontroller instructions:
Refer to the separate document RL78 Microcontroller Instructions User’s Manual
(R01US0015E).
Conventions
Data significance:
Higher digits on the left and lower digits on the right
Active low representations: (overscore over pin and signal name)
Note:
Footnote for item marked with Note in the text
Caution:
Information requiring particular attention
Remark:
Supplementary information
... or B
Numerical representations: Binary
...
Decimal
Hexadecimal
Related Documents
...H
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
RL78/D1A User’s Manual Hardware
This manual
RL78 Microcontroller Instructions User’s Manual
R01US0015E
Documents Related to Flash Memory Programming
Document Name
PG-FP5 Flash Memory Programmer User’s Manual
Document No.
R20UT0008E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
Other Documents
Document Name
RENESAS MICROCOMPUTER GENERAL CATALOG
Document No.
R01CS0001E
Semiconductor Package Mount Manual
Note
Quality Grades on NEC Semiconductor Devices
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892E
Note See the “Semiconductor Device Mount Manual” website (http://www.renesas.com/products/package/manual/index.jsp).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
All trademarks and registered trademarks are the property of their respective owners.
EEPROM is a trademark of Renesas Electronics Corporation.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States
and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
CONTENTS
CHAPTER 1 OUTLINE............................................................................................................................... 1
1.1 Features ................................................................................................................................................. 1
1.2 Applications .......................................................................................................................................... 2
1.3 Ordering Information ............................................................................................................................ 3
1.4 Pin Configuration (Top View) .............................................................................................................. 4
1.4.1 48-pin products (R5F10CGBxFB, R5F10CGCxFB, R5F10CGDxFB: with no CAN) ........................... 4
1.4.2 48-pin products (R5F10DGCxFB, R5F10DGDxFB, R5F10DGExFB: with CAN)................................ 5
1.4.3 64-pin products (R5F10CLDxFB: with no CAN) ................................................................................. 6
1.4.4 64-pin products (R5F10DLDxFB, R5F10DLExFB: with CAN) ............................................................ 7
1.4.5 80-pin products (R5F10CMDxFB, R5F10CMExFB: with no CAN) ..................................................... 8
1.4.6 80-pin products (R5F10DMDxFB, R5F10DMExFB, R5F10DMFxFB, R5F10DMGxFB,
R5F10DMJxFB: with CAN)................................................................................................................. 9
1.4.7 100-pin products
(R5F10DPExFB, R5F10DPFxFB, R5F10DPGxFB, R5F10TPJxFB: with 1 ch of CAN) ................... 10
1.4.8 100-pin products (R5F10DPJxFB, R5F10DPKxFB, R5F10DPLxFB: with 2 ch of CAN) .................. 11
1.4.9 128-pin products (R5F10DSLxxFB, R5F10DSKxxFB, R5F10DSJxxFB) .......................................... 12
1.5 Pin Identification ................................................................................................................................. 13
1.6 Block Diagram..................................................................................................................................... 14
1.6.1 48-pin products (R5F10CGBxFB, R5F10CGCxFB, R5F10CGDxFB: with no CAN) ......................... 14
1.6.2 48-pin products (R5F10DGCxFB, R5F10DGDxFB, R5F10DGExFB: with CAN).............................. 15
1.6.3 64-pin products (R5F10CLDxFB: with no CAN) ............................................................................... 16
1.6.4 64-pin products (R5F10DLDxFB, R5F10DLExFB: with CAN) .......................................................... 17
1.6.5 80-pin products (R5F10CMDxFB, R5F10CMExFB: with no CAN) ................................................... 18
1.6.6 80-pin products (R5F10DMDxFB, R5F10DMExFB, R5F10DMFxFB, R5F10DMGxFB,
R5F10DMJxFB: with CAN)............................................................................................................... 19
1.6.7 100-pin products (R5F10DPExFB, R5F10DPFxFB, R5F10DPGxFB, R5F10TPJxFB:
with 1 ch of CAN) ............................................................................................................................. 20
1.6.8 100-pin products (R5F10DPJxFB, R5F10DPKxFB, R5F10DPLxFB: with 2 ch of CAN) .................. 21
1.6.9 128-pin products (R5F10DSJxFB, R5F10DSKxFB, R5F10DSLxFB) ................................................ 22
1.7 Outline of Functions ........................................................................................................................... 23
CHAPTER 2 PIN FUNCTIONS ................................................................................................................ 27
2.1 Pin Function List................................................................................................................................. 27
2.1.1 48-pin products.................................................................................................................................. 28
2.1.2 64-pin products.................................................................................................................................. 30
2.1.3 80-pin products products ................................................................................................................... 32
2.1.4 100-pin products................................................................................................................................ 34
2.1.5 128-pin products................................................................................................................................ 37
Index-1
2.1.6 Pins for each product (pins other than port pins) ............................................................................... 41
2.2 Description of Pin Function ............................................................................................................... 47
2.2.1 P00 to P07 (port 0) ........................................................................................................................... 47
2.2.2 P10 to P17 (port1) ............................................................................................................................ 48
2.2.3 P20 to P27 (port2) ............................................................................................................................ 49
2.2.4 P30 to P37 (port3) ............................................................................................................................ 50
2.2.5 P40 (port4) ....................................................................................................................................... 51
2.2.6 P50 to P57 (port5) ............................................................................................................................ 52
2.2.7 P60 to P66 (port6) ............................................................................................................................ 53
2.2.8 P70 to P75 (port7) ............................................................................................................................ 54
2.2.9 P80 to P87 (port8) ............................................................................................................................ 56
2.2.10 P90 to P97 (port9) .......................................................................................................................... 57
2.2.11 P100 to P107 (port10) .................................................................................................................... 58
2.2.12 P110 to P117 (port 11) ................................................................................................................... 59
2.2.13 P121 to P127 (port12) .................................................................................................................... 60
2.2.14 P130 to P137 (port13) .................................................................................................................... 61
2.2.15 P140 (port14) ................................................................................................................................. 63
2.2.16 P150 to P152 (port15) .................................................................................................................... 63
2.2.17 COM0 to COM3 .............................................................................................................................. 63
2.2.18 VDD, EVDD0, EVDD1, SMVDD0, SMVDD1, VSS, EVSS0, EVSS1, SMVSS0, SMVSS1 ............. 64
2.2.19 RESET ........................................................................................................................................... 64
2.2.20 REGC ............................................................................................................................................. 64
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ................................................. 65
CHAPTER 3 CPU ARCHITECTURE ....................................................................................................... 83
3.1 Memory Space .................................................................................................................................... 83
3.1.1 Internal program memory space....................................................................................................... 98
3.1.2 Mirror area ...................................................................................................................................... 102
3.1.3 Internal data memory space ........................................................................................................... 104
3.1.4 Special function register (SFR) area .............................................................................................. 105
3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area ..................... 105
3.1.6 Data memory addressing ............................................................................................................... 106
3.2 Processor Registers ......................................................................................................................... 115
3.2.1 Control registers ............................................................................................................................. 115
3.2.2 General-purpose registers .............................................................................................................. 117
3.2.3 ES and CS registers ....................................................................................................................... 118
3.2.4 Special function registers (SFRs) ................................................................................................... 119
3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) ......................... 125
3.3 Instruction Address Addressing ..................................................................................................... 147
3.3.1 Relative addressing ........................................................................................................................ 147
3.3.2 Immediate addressing .................................................................................................................... 147
Index-2
3.3.3 Table indirect addressing ............................................................................................................... 148
3.3.4 Register direct addressing .............................................................................................................. 149
3.4 Addressing for Processing Data Addresses ................................................................................. 150
3.4.1 Implied addressing ......................................................................................................................... 150
3.4.2 Register addressing ....................................................................................................................... 150
3.4.3 Direct addressing ........................................................................................................................... 151
3.4.4 Short direct addressing .................................................................................................................. 152
3.4.5 SFR addressing .............................................................................................................................. 153
3.4.6 Register indirect addressing ........................................................................................................... 154
3.4.7 Based addressing ........................................................................................................................... 155
3.4.8 Based indexed addressing ............................................................................................................. 159
3.4.9 Stack addressing ............................................................................................................................ 160
CHAPTER 4 PORT FUNCTIONS .......................................................................................................... 164
4.1 Port Functions .................................................................................................................................. 164
4.2 Port Configuration ............................................................................................................................ 165
4.2.1 Port 0 .............................................................................................................................................. 166
4.2.2 Port 1 .............................................................................................................................................. 173
4.2.3 Port 2 .............................................................................................................................................. 179
4.2.4 Port 3 .............................................................................................................................................. 181
4.2.5 Port 4 .............................................................................................................................................. 186
4.2.6 Port 5 .............................................................................................................................................. 191
4.2.7 Port 6 .............................................................................................................................................. 197
4.2.8 Port 7 .............................................................................................................................................. 204
4.2.9 Port 8 .............................................................................................................................................. 210
4.2.10 Port 9 ............................................................................................................................................ 213
4.2.11 Port 10 .......................................................................................................................................... 218
4.2.12 Port 11 .......................................................................................................................................... 220
4.2.13 Port 12 .......................................................................................................................................... 223
4.2.14 Port 13 .......................................................................................................................................... 226
4.2.15 Port 14 .......................................................................................................................................... 235
4.2.16 Port 15 .......................................................................................................................................... 237
4.3 Registers Controlling Port Function............................................................................................... 239
4.4 Port Function Operations ................................................................................................................ 272
4.4.1 Writing to I/O port ........................................................................................................................... 272
4.4.2 Reading from I/O port ..................................................................................................................... 272
4.4.3 Operations on I/O port .................................................................................................................... 272
4.5 Settings of Registers, and Output Latch When Using Alternate Function ................................. 273
4.5.1 The relationship of alternate function and port ............................................................................... 273
4.5.2 Expanded Control Register of Port Function .................................................................................. 278
4.5.3 The setting to use alternate function .............................................................................................. 295
Index-3
4.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) .......................................... 311
CHAPTER 5 CLOCK GENERATOR ..................................................................................................... 312
5.1 Functions of Clock Generator ......................................................................................................... 312
5.2 Configuration of Clock Generator................................................................................................... 314
5.3 Registers Controlling Clock Generator .......................................................................................... 317
5.4 Clock monitor (CLM) ........................................................................................................................ 334
5.5 System Clock Oscillator .................................................................................................................. 335
5.5.1 X1 oscillator .................................................................................................................................... 335
5.5.2 XT1 oscillator .................................................................................................................................. 335
5.5.3 High-speed on-chip oscillator ......................................................................................................... 339
5.5.4 Low-speed on-chip oscillator .......................................................................................................... 339
5.6 Clock Generator Operation.............................................................................................................. 340
5.7 Controlling Clock .............................................................................................................................. 342
5.7.1 Example of controlling high-speed on-chip oscillator ...................................................................... 342
5.7.2 Example of controlling X1 oscillation clock ..................................................................................... 343
5.7.3 Example of controlling XT1 oscillation clock ................................................................................... 344
5.7.4 Example of controlling Peripheral clock .......................................................................................... 345
5.7.5 CPU clock status transition diagram ............................................................................................... 347
5.7.6 Condition before changing CPU clock and processing after changing CPU clock ......................... 353
5.7.7 Time required for switchover of CPU clock and main system clock ............................................... 355
5.7.8 Conditions before clock oscillation is stopped ................................................................................ 356
CHAPTER 6 TIMER ARRAY UNIT ........................................................................................................ 357
6.1 Functions of Timer Array Unit ......................................................................................................... 358
6.1.1 Functions of each channel when it operates independently ........................................................... 358
6.1.2 Functions of each channel when it operates with another channel ................................................ 359
6.1.3 LIN-bus supporting function (Channel 3 of the timer array unit 0, channels 1 and 4 of the timer
array unit 1, and channel 0 of the timer array unit 2 only) .............................................................. 361
6.2 Configuration of Timer Array `Unit ................................................................................................. 362
6.3 Registers Controlling Timer Array Unit .......................................................................................... 372
6.4 Channel Output (TOmn Pin) Control .............................................................................................. 434
6.4.1 TOmn pin output circuit configuration ............................................................................................. 434
6.4.2 TOmn pin output setting ................................................................................................................. 435
6.4.3 Cautions on channel output operation ............................................................................................ 436
6.4.4 Collective manipulation of TOmn bits ............................................................................................. 441
6.4.5 Timer interrupt and TOmn pin output at count operation start ........................................................ 442
6.5 Channel Input (TImn Pin) Control ................................................................................................... 443
6.5.1 TImn edge detection circuit ............................................................................................................ 443
6.6 Basic Function of Timer Array Unit ................................................................................................ 444
6.6.1 Overview of single-operation function and combination operation function .................................... 444
Index-4
6.6.2 Basic rules of combination operation function ................................................................................ 444
6.6.3 Applicable range of basic rules of combination operation function ................................................. 445
6.7 Operation of Timer Array Unit as Independent Channel .............................................................. 446
6.7.1 Operation as interval timer/square wave output ............................................................................. 446
6.7.2 Operation as external event counter .............................................................................................. 451
6.7.3 Operation as frequency divider....................................................................................................... 454
6.7.4 Operation as input pulse interval measurement ............................................................................. 459
6.7.5 Operation as input signal high-/low-level width measurement ........................................................ 463
6.8 Operation of Plural Channels of Timer Array Unit ........................................................................ 467
6.8.1 Operation as PWM function............................................................................................................ 467
6.8.2 Operation as one-shot pulse output function .................................................................................. 474
6.8.3 Operation as multiple PWM output function ................................................................................... 481
CHAPTER 7 REAL-TIME CLOCK ......................................................................................................... 489
7.1 Functions of Real-time Clock .......................................................................................................... 489
7.2 Configuration of Real-time Clock.................................................................................................... 489
7.3 Registers Controlling Real-time Clock ........................................................................................... 491
7.4 Real-time Clock Operation ............................................................................................................... 508
7.4.1 Starting operation of real-time clock ............................................................................................... 508
7.4.2 Shifting to HALT/STOP mode after starting operation .................................................................... 509
7.4.3 Reading/writing real-time clock ....................................................................................................... 510
7.4.4 Setting alarm of real-time clock ...................................................................................................... 512
7.4.5 1 Hz output of real-time clock ......................................................................................................... 513
7.4.6 Example of watch error correction of real-time clock ...................................................................... 514
CHAPTER 8 INTERVAL TIMER ............................................................................................................ 517
8.1 Functions of Interval Timer ............................................................................................................. 517
8.2 Configuration of Interval Timer ....................................................................................................... 517
8.3 Registers Controlling Interval Timer .............................................................................................. 518
8.4 Interval Timer Operation .................................................................................................................. 521
CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER ................................................. 522
9.1 Functions of Clock Output/Buzzer Output Controller .................................................................. 522
9.2 Configuration of Clock Output/Buzzer Output Controller ............................................................ 523
9.3 Registers Controlling Clock Output/Buzzer Output Controller ................................................... 523
9.4 Operations of Clock Output/Buzzer Output Controller................................................................. 527
9.4.1 Operation as output pin .................................................................................................................. 527
9.5 Cautions of clock output/buzzer output controller ....................................................................... 528
CHAPTER 10 WATCHDOG TIMER ...................................................................................................... 529
Index-5
10.1 Functions of Watchdog Timer ....................................................................................................... 529
10.2 Configuration of Watchdog Timer ................................................................................................ 530
10.3 Register Controlling Watchdog Timer .......................................................................................... 531
10.4 Operation of Watchdog Timer ....................................................................................................... 532
10.4.1 Controlling operation of watchdog timer ....................................................................................... 532
10.4.2 Setting overflow time of watchdog timer ....................................................................................... 533
10.4.3 Setting window open period of watchdog timer ............................................................................ 534
10.4.4 Setting watchdog timer interval interrupt ...................................................................................... 535
CHAPTER 11 A/D CONVERTER ......................................................................................................... 536
11.1 Function of A/D Converter ............................................................................................................. 536
11.2 Configuration of A/D Converter .................................................................................................... 538
11.3 Registers Used in A/D Converter .................................................................................................. 540
11.4 A/D Converter Conversion Operations......................................................................................... 565
11.5 Input Voltage and Conversion Results ........................................................................................ 567
11.6 A/D Converter Operation Modes ................................................................................................... 568
11.6.1 Software trigger mode (select mode, sequential conversion mode) ............................................. 568
11.6.2 Software trigger mode (select mode, one-shot conversion mode) ............................................... 569
11.6.3 Software trigger mode (scan mode, sequential conversion mode) ............................................... 570
11.6.4 Software trigger mode (scan mode, one-shot conversion mode) ................................................. 571
11.6.5 Hardware trigger no-wait mode (select mode, sequential conversion mode) ............................... 572
11.6.6 Hardware trigger no-wait mode (select mode, one-shot conversion mode).................................. 573
11.6.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode) ................................. 574
11.6.8 Hardware trigger no-wait mode (scan mode, one-shot conversion mode) ................................... 575
11.6.9 Hardware trigger wait mode (select mode, sequential conversion mode) .................................... 576
11.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode) ..................................... 577
11.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode) .................................... 578
11.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode) ...................................... 579
11.7 A/D Converter Setup Flowchart .................................................................................................... 580
11.7.1 Setting up software trigger mode.................................................................................................. 581
11.7.2 Setting up hardware trigger no-wait mode .................................................................................... 582
11.7.3 Setting up hardware trigger wait mode ......................................................................................... 583
11.7.4 Setting up test mode .................................................................................................................... 584
11.8 SNOOZE Mode Function ................................................................................................................ 585
11.9 How to Read A/D Converter Characteristics Table ..................................................................... 588
11.10 Cautions for A/D Converter ......................................................................................................... 590
CHAPTER 12 SERIAL ARRAY UNIT ....................................................................................................... 594
12.1 Functions of Serial Array Unit ....................................................................................................... 595
12.1.1 3-wire serial I/O (CSI00, CSI01, CSI10) ....................................................................................... 595
12.1.2 UART (UART0) ............................................................................................................................ 595
Index-6
2
12.1.3 Simplified I C (IIC11) .................................................................................................................... 596
12.2 Configuration of Serial Array Unit ................................................................................................ 597
12.3 Registers Controlling Serial Array Unit ........................................................................................ 604
12.4 Operation stop mode ..................................................................................................................... 629
12.4.1 Stopping the operation by units .................................................................................................... 629
12.4.2 Stopping the operation by channels ............................................................................................. 630
12.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10) Communication...................................... 631
12.5.1 Master transmission ..................................................................................................................... 632
12.5.2 Master reception ........................................................................................................................... 643
12.5.3 Master transmission/reception...................................................................................................... 653
12.5.4 Slave transmission ....................................................................................................................... 664
12.5.5 Slave reception ............................................................................................................................. 674
12.5.6 Slave transmission/reception........................................................................................................ 681
12.5.7 Calculating transfer clock frequency ............................................................................................. 691
12.5.8 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10)
communication ............................................................................................................................... 693
12.6 Operation of UART (UART0) Communication ............................................................................. 694
12.6.1 UART transmission ...................................................................................................................... 695
12.6.2 UART reception ............................................................................................................................ 705
12.6.3 Calculating baud rate ................................................................................................................... 712
12.6.4 Procedure for processing errors that occurred during UART (UART0) communication ............... 716
12.7 Operation of Simplified I2C (IIC11) Communication .................................................................... 717
12.7.1 Address field transmission............................................................................................................ 718
12.7.2 Data transmission ......................................................................................................................... 724
12.7.3 Data reception .............................................................................................................................. 728
12.7.4 Stop condition generation ............................................................................................................. 733
12.7.5 Calculating transfer rate ............................................................................................................... 734
12.7.6 Procedure for processing errors that occurred during simplified I2C (IIC11) communication........ 736
12.8 Relationship Between Register Settings and Pins ...................................................................... 737
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) ............................... 749
13.1 Features ........................................................................................................................................... 749
13.2 Configuration .................................................................................................................................. 751
13.3 Control Registers............................................................................................................................ 753
13.4 Interrupt Request Signals .............................................................................................................. 784
13.5 Operation ......................................................................................................................................... 785
13.5.1 Data format................................................................................................................................... 785
13.5.2 Data transmission ......................................................................................................................... 787
13.5.3 Data reception .............................................................................................................................. 790
13.5.4 BF transmission/reception format ................................................................................................. 792
13.5.5 BF transmission ............................................................................................................................ 797
Index-7
13.5.6 BF reception ................................................................................................................................. 799
13.5.7 Parity types and operations .......................................................................................................... 802
13.5.8 Data consistency check ................................................................................................................ 803
13.5.9 BF reception mode select function ............................................................................................... 807
13.5.10 LIN-UART reception status interrupt generation sources ........................................................... 812
13.5.11 Transmission start wait function ................................................................................................. 815
13.6 UART Buffer Mode .......................................................................................................................... 816
13.6.1 UART buffer mode transmission .................................................................................................. 817
13.7 LIN Communication Automatic Baud Rate Mode........................................................................ 819
13.7.1 Automatic baud rate setting function ............................................................................................ 825
13.7.2 Response preparation error detection function............................................................................. 828
13.7.3 ID parity check function ................................................................................................................ 829
13.7.4 Automatic checksum function ....................................................................................................... 829
13.7.5 Multi-byte response transmission/reception function .................................................................... 831
13.8 Expansion Bit Mode ....................................................................................................................... 835
13.8.1 Expansion bit mode transmission ................................................................................................. 835
13.8.2 Expansion bit mode reception (no data comparison) ................................................................... 836
13.8.3 Expansion bit mode reception (with data comparison) ................................................................. 837
13.9 Receive Data Noise Filter ............................................................................................................... 838
13.10 Dedicated Baud Rate Generator ................................................................................................. 839
13.11 Cautions for Use ........................................................................................................................... 846
CHAPTER 14 CAN CONTROLLER ...................................................................................................... 847
14.1 Outline Description......................................................................................................................... 847
14.1.1 Features ....................................................................................................................................... 847
14.1.2 Overview of functions ................................................................................................................... 848
14.1.3 Configuration ................................................................................................................................ 849
14.2 CAN Protocol .................................................................................................................................. 850
14.2.1 Frame format ................................................................................................................................ 850
14.2.2 Frame types ................................................................................................................................. 851
14.2.3 Data frame and remote frame ...................................................................................................... 851
14.2.4 Error frame ................................................................................................................................... 859
14.2.5 Overload frame ............................................................................................................................. 860
14.3 Functions......................................................................................................................................... 861
14.3.1 Determining bus priority................................................................................................................ 861
14.3.2 Bit stuffing..................................................................................................................................... 861
14.3.3 Multi masters ................................................................................................................................ 861
14.3.4 Multi cast ...................................................................................................................................... 861
14.3.5 CAN sleep mode/CAN stop mode function................................................................................... 861
14.3.6 Error control function .................................................................................................................... 862
14.3.7 Baud rate control function............................................................................................................. 868
Index-8
14.4 Connection with Target System .................................................................................................... 872
14.5 Internal Registers of CAN Controller ............................................................................................ 873
14.5.1 CAN controller configuration......................................................................................................... 873
14.5.2 Register access type .................................................................................................................... 875
14.5.3 Register bit configuration .............................................................................................................. 893
14.6 Bit Set/Clear Function .................................................................................................................... 900
14.7 Control Registers............................................................................................................................ 902
14.8 CAN Controller Initialization .......................................................................................................... 941
14.8.1 Initialization of CAN module ......................................................................................................... 941
14.8.2 Initialization of message buffer ..................................................................................................... 941
14.8.3 Redefinition of message buffer ..................................................................................................... 941
14.8.4 Transition from initialization mode to operation mode .................................................................. 942
14.8.5 Resetting error counter C0ERC of CAN module .......................................................................... 943
14.9 Message Reception ........................................................................................................................ 944
14.9.1 Message reception ....................................................................................................................... 944
14.9.2 Receive Data Read ...................................................................................................................... 945
14.9.3 Receive history list function .......................................................................................................... 946
14.9.4 Mask function ............................................................................................................................... 948
14.9.5 Multi buffer receive block function ................................................................................................ 950
14.9.6 Remote frame reception ............................................................................................................... 951
14.10 Message Transmission ................................................................................................................ 952
14.10.1 Message transmission ................................................................................................................ 952
14.10.2 Transmit history list function ....................................................................................................... 954
14.10.3 Automatic block transmission (ABT) ........................................................................................... 956
14.10.4 Transmission abort process ....................................................................................................... 957
14.10.5 Remote frame transmission........................................................................................................ 958
14.11 Power Save Modes ....................................................................................................................... 959
14.11.1 CAN sleep mode ........................................................................................................................ 959
14.11.2 CAN stop mode .......................................................................................................................... 961
14.11.3 Example of using power saving modes ...................................................................................... 962
14.12 Interrupt Function ......................................................................................................................... 963
14.13 Diagnosis Functions and Special Operational Modes ............................................................. 964
14.13.1 Receive-only mode ..................................................................................................................... 964
14.13.2 Single-shot mode ....................................................................................................................... 965
14.13.3 Self-test mode ............................................................................................................................ 966
14.13.4 Receive/Transmit Operation in Each Operation Mode ............................................................... 967
14.14 Time Stamp Function ................................................................................................................... 968
14.14.1 Time stamp function ................................................................................................................... 968
14.15 Baud Rate Settings ....................................................................................................................... 970
14.15.1 Baud rate settings ...................................................................................................................... 970
14.15.2 Representative examples of baud rate settings.......................................................................... 974
Index-9
14.16 Operation of CAN Controller ....................................................................................................... 978
CHAPTER 15 STEPPER MOTOR CONTROLLER/DRIVER .............................................................. 1003
15.1 Overview ........................................................................................................................................ 1003
15.1.1 Driver overview........................................................................................................................... 1003
15.1.2 ZPD introduction ......................................................................................................................... 1003
15.1.3 ZPD input pins ............................................................................................................................ 1004
15.2 Stepper Motor Controller/Driver Registers ................................................................................ 1006
15.3 Operation ....................................................................................................................................... 1017
15.3.1 Stepper motor controller/driver operation ................................................................................... 1017
15.4 Timing ............................................................................................................................................ 1020
15.4.1 Timer counter ............................................................................................................................. 1020
15.4.2 Automatic PWM phase shift ....................................................................................................... 1021
CHAPTER 16 LCD CONTROLLER/DRIVER ...................................................................................... 1022
16.1 Functions of LCD Controller/Driver ............................................................................................ 1022
16.2 Configuration of LCD Controller/Driver ..................................................................................... 1025
16.3 Registers Controlling LCD Controller/Driver ............................................................................. 1027
16.4 Setting LCD Controller/Driver ..................................................................................................... 1035
16.5 LCD Display Data Memory ........................................................................................................... 1036
16.6 Common and Segment Signals................................................................................................... 1039
16.7 Display Modes............................................................................................................................... 1044
16.7.1 Static display example ................................................................................................................ 1044
16.7.2 Three-time-slice display example ............................................................................................... 1047
16.7.3 Four-time-slice display example ................................................................................................. 1050
16.8 Supplying LCD Drive Voltages VLC0, VLC1, and VLC2............................................................ 1053
CHAPTER 17 LCD BUS INTERFACE (128-pin products only)......................................................... 1055
17.1 Functions of LCD Bus Interface .................................................................................................. 1055
17.2 Configuration of LCD Bus Interface ........................................................................................... 1056
17.3 Registers Controlling LCD Bus Interface ................................................................................... 1059
17.4 Operation of Timing...................................................................................................................... 1063
17.4.1 Timing dependencies ................................................................................................................. 1063
17.4.2 LCD Bus I/F states during and after accesses ........................................................................... 1064
17.4.3 Writing to the LCD bus ............................................................................................................... 1064
17.4.4 Reading from the LCD bus ......................................................................................................... 1067
17.4.5 Write-Read-Write sequence on the LCD bus ............................................................................. 1069
17.5 Cautions for LCD Bus Interface .................................................................................................. 1070
17.5.1 Polling of LBCTL.TPF flag may indicate wrong status ................................................................ 1070
17.5.2 Writing to the LBDATA/ LBDATAL register................................................................................. 1070
Index-10
17.6 Example of LCD Bus Interface Transmission............................................................................ 1071
17.6.1 Connection example of external LCD driver ............................................................................... 1071
17.6.2 Operation procedure of LCD BUS transmission ......................................................................... 1073
CHAPTER 18 SOUND GENERATOR ................................................................................................. 1080
18.1 Overview ........................................................................................................................................ 1080
18.1.1 Description ................................................................................................................................. 1081
18.1.2 Principle of operation .................................................................................................................. 1083
18.2 Sound Generator Registers ......................................................................................................... 1084
18.3 Sound Generator Operation ........................................................................................................ 1089
18.3.1 Generating the tone .................................................................................................................... 1089
18.3.2 Generating the volume information ............................................................................................ 1090
18.4 Sound Generator Application Hints............................................................................................ 1092
18.4.1 Initialization................................................................................................................................. 1092
18.4.2 Start and stop sound .................................................................................................................. 1092
18.4.3 Change sound volume................................................................................................................ 1092
18.4.4 Generate special sounds ............................................................................................................ 1092
CHAPTER 19 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR ....................................... 1093
19.1 Functions of Multiplier and Divider/Multiply-Accumulator ...................................................... 1093
19.2 Configuration of Multiplier and Divider/Multiply-Accumulator ................................................ 1093
19.3 Register Controlling Multiplier and Divider/Multiply-Accumulator ......................................... 1099
19.4 Operations of Multiplier and Divider/Multiply-Accumulator .................................................... 1101
19.4.1 Multiplication (unsigned) operation ............................................................................................... 1101
19.4.2 Multiplication (signed) operation................................................................................................... 1102
19.4.3 Multiply-accumulation (unsigned) operation ................................................................................. 1103
19.4.4 Multiply-accumulation (signed) operation ..................................................................................... 1105
19.4.5 Division operation ......................................................................................................................... 1107
CHAPTER 20 DMA CONTROLLER .................................................................................................... 1109
20.1 Functions of DMA Controller....................................................................................................... 1109
20.2 Configuration of DMA Controller ................................................................................................ 1110
20.3 Registers Controlling DMA Controller........................................................................................ 1113
20.4 Operation of DMA Controller ....................................................................................................... 1120
20.4.1 Operation procedure .................................................................................................................. 1120
20.4.2 Transfer mode ............................................................................................................................ 1121
20.4.3 Termination of DMA transfer ...................................................................................................... 1121
20.5 Example of Setting of DMA Controller ....................................................................................... 1122
20.5.1 CSI consecutive transmission .................................................................................................... 1122
20.5.2 Consecutive capturing of A/D conversion results ....................................................................... 1124
Index-11
20.5.3 UART consecutive reception + ACK transmission...................................................................... 1126
20.5.4 Holding DMA transfer pending by DWAITn bit ........................................................................... 1128
20.5.5 Forced termination by software .................................................................................................. 1129
20.6 Cautions on Using DMA Controller ............................................................................................ 1131
CHAPTER 21 INTERRUPT FUNCTIONS............................................................................................ 1134
21.1 Interrupt Function Types ............................................................................................................. 1134
21.2 Interrupt Sources and Configuration.......................................................................................... 1134
21.3 Registers Controlling Interrupt Functions ................................................................................. 1139
21.4 Interrupt Servicing Operations.................................................................................................... 1149
21.4.1 Maskable interrupt request acknowledgment ............................................................................. 1149
21.4.2 Software interrupt request acknowledgment .............................................................................. 1152
21.4.3 Multiple interrupt servicing .......................................................................................................... 1152
21.4.4 Interrupt request hold ................................................................................................................. 1156
CHAPTER 22 STANDBY FUNCTION ................................................................................................ 1157
22.1 Standby Function and Configuration ......................................................................................... 1157
22.1.1 Standby function......................................................................................................................... 1157
22.1.2 Registers controlling standby function ........................................................................................ 1158
22.2 Standby Function Operation ....................................................................................................... 1162
22.2.1 HALT mode ................................................................................................................................ 1162
22.2.2 STOP mode................................................................................................................................ 1168
22.2.3 SNOOZE mode .......................................................................................................................... 1174
CHAPTER 23 RESET FUNCTION....................................................................................................... 1177
23.1 Register for Confirming Reset Source ....................................................................................... 1189
23.2 CLM Reset Control Flag Register ............................................................................................... 1190
23.3 POR Reset Flag Register ............................................................................................................. 1190
CHAPTER 24 POWER-ON-RESET CIRCUIT .................................................................................... 1191
24.1 Functions of Power-on-reset Circuit .......................................................................................... 1191
24.2 Configuration of Power-on-reset Circuit .................................................................................... 1192
24.3 Operation of Power-on-reset Circuit........................................................................................... 1192
24.4 Cautions for Power-on-reset Circuit ........................................................................................... 1195
CHAPTER 25 VOLTAGE DETECTOR ................................................................................................ 1197
25.1 Functions of Voltage Detector .................................................................................................... 1197
25.2 Configuration of Voltage Detector .............................................................................................. 1198
25.3 Registers Controlling Voltage Detector ..................................................................................... 1198
25.4 Operation of Voltage Detector..................................................................................................... 1203
Index-12
25.4.1 When used as reset mode.......................................................................................................... 1203
25.4.2 When used as interrupt mode .................................................................................................... 1205
25.4.3 When used as interrupt and reset mode .................................................................................... 1207
25.5 Cautions for Voltage Detector ..................................................................................................... 1213
CHAPTER 26 SAFETY FUNCTIONS .................................................................................................. 1215
26.1 Overview of Safety Functions ..................................................................................................... 1215
26.2 Registers Used by Safety Functions .......................................................................................... 1216
26.3 Operations of Safety Functions .................................................................................................. 1216
26.3.1 Flash Memory CRC Operation Function (High-Speed CRC)...................................................... 1216
26.3.2 CRC Operation Function (General-Purpose CRC) ..................................................................... 1220
26.3.3 RAM Parity Error Detection Function ......................................................................................... 1222
26.3.4 RAM Guard Function .................................................................................................................. 1223
26.3.5 SFR Guard Function .................................................................................................................. 1224
26.3.6 Invalid Memory Access Detection Function ................................................................................ 1226
26.3.7 Frequency Detection Function.................................................................................................... 1229
26.3.8 A/D Test Function ....................................................................................................................... 1230
CHAPTER 27 REGULATOR ............................................................................................................... 1232
27.1 Regulator Overview ...................................................................................................................... 1232
CHAPTER 28 OPTION BYTE .............................................................................................................. 1233
28.1 Functions of Option Bytes ........................................................................................................... 1233
28.1.1 User option byte (000C0H to 000C2H/020C0H to 020C2H)....................................................... 1233
28.1.2 On-chip debug option byte (000C3H/ 020C3H) .......................................................................... 1234
28.2 Format of User Option Byte......................................................................................................... 1235
28.3 Format of On-chip Debug Option Byte ....................................................................................... 1239
28.4 Setting of Option Byte .................................................................................................................. 1240
CHAPTER 29 FLASH MEMORY ........................................................................................................ 1241
29.1 Writing to Flash Memory by Using Flash Memory Programmer ............................................. 1242
29.1.1 Programming Environment ......................................................................................................... 1244
29.1.2 Communication Mode ................................................................................................................ 1244
29.2 Writing to Flash Memory by Using External Device (that Incorporates UART) ..................... 1245
29.2.1 Programming Environment ......................................................................................................... 1245
29.2.2 Communication Mode ................................................................................................................ 1246
29.3 Connection of Pins on Board ...................................................................................................... 1247
29.3.1 P40/TOOL0 pin .......................................................................................................................... 1247
____________
29.3.2 RESET pin.................................................................................................................................. 1247
29.3.3 Port pins ..................................................................................................................................... 1248
Index-13
29.3.4 REGC pin ................................................................................................................................... 1248
29.3.5 X1 and X2 pins ........................................................................................................................... 1248
29.3.6 Power supply .............................................................................................................................. 1248
29.4 Data Flash...................................................................................................................................... 1249
29.4.1 Data flash overview .................................................................................................................... 1249
29.4.2 Register controlling data flash memory ...................................................................................... 1250
29.4.3 Procedure for accessing data flash memory .............................................................................. 1251
29.5 Programming Method .................................................................................................................. 1252
29.5.1 Controlling flash memory ............................................................................................................ 1252
29.5.2 Flash memory programming mode ............................................................................................. 1253
29.5.3 Selecting communication mode .................................................................................................. 1254
29.5.4 Communication commands ........................................................................................................ 1255
29.5.5 Description of signature data ...................................................................................................... 1256
29.6 Security Settings .......................................................................................................................... 1257
29.7 Flash Memory Programming by Self-Programming ................................................................. 1259
29.7.1 Boot swap function ..................................................................................................................... 1261
29.7.2 Flash shield window function ...................................................................................................... 1263
CHAPTER 30 ON-CHIP DEBUG FUNCTION ................................................................................... 1264
30.1 Connecting E1 On-chip Debugging Emulator to RL78/D1A ..................................................... 1264
30.2 On-Chip Debug Security ID ......................................................................................................... 1265
30.3 Securing of User Resources ....................................................................................................... 1265
CHAPTER 31 BCD CORRECTION CIRCUIT ................................................................................... 1267
31.1 BCD Correction Circuit Function ................................................................................................ 1267
31.2 Registers Used by BCD Correction Circuit ................................................................................ 1267
31.3 BCD Correction Circuit Operation .............................................................................................. 1268
CHAPTER 32 INSTRUCTION SET...................................................................................................... 1270
32.1 Conventions Used in Operation List .......................................................................................... 1271
32.1.1 Operand identifiers and specification methods ........................................................................... 1271
32.1.2 Description of operation column ................................................................................................. 1272
32.1.3 Description of flag operation column .......................................................................................... 1273
32.1.4 PREFIX instruction ..................................................................................................................... 1273
32.2 Operation List ............................................................................................................................... 1274
CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT).......................................... 1291
33.1 Absolute Maximum Ratings ........................................................................................................ 1293
33.2 Power consumption characteristics ........................................................................................... 1295
33.2.1 Product group A .......................................................................................................................... 1295
Index-14
33.3 Oscillator characteristics............................................................................................................. 1301
33.3.1 Main(X1) oscillator characteristics .............................................................................................. 1301
33.3.2 High speed on chip oscillator characteristics .............................................................................. 1301
33.3.3 Low speed on chip oscillator characteristics............................................................................... 1301
33.3.4 Sub(XT1) oscillator characteristics ............................................................................................. 1301
33.4 DC characteristics ........................................................................................................................ 1302
33.4.1 Pin group 1 ................................................................................................................................. 1302
33.4.2 Pin group 2 (ANI pins) ................................................................................................................ 1306
33.4.3 Pin group 3 (SMC pins) .............................................................................................................. 1307
33.4.4 Pin group 4 (OSC, reset and P137 pins) .................................................................................... 1313
33.5 AC characteristics ........................................................................................................................ 1315
33.5.1 Basic operation........................................................................................................................... 1315
33.5.2 Stepper motor controller/driver ................................................................................................... 1317
33.5.3 Sound generator ......................................................................................................................... 1318
33.5.4 Serial interface: CSI operation.................................................................................................... 1319
33.5.5 Serial interface: UART operation (128-pin only) ......................................................................... 1321
33.5.6 Serial interface: simplified I2C operation ..................................................................................... 1322
33.5.7 Serial interface: LIN-UART(UARTF) operation ........................................................................... 1323
33.5.8 Serial interface: CAN operation .................................................................................................. 1323
33.6 LCD Bus Interface characteristics (128-pin products only) ..................................................... 1324
33.6 LCD characteristics ...................................................................................................................... 1326
33.6 LCD characteristics ...................................................................................................................... 1327
33.7 Analog characteristics ................................................................................................................. 1329
33.7.1 A/D converter characteristics...................................................................................................... 1329
33.7.2 ZPD characteristics .................................................................................................................... 1330
33.7.3 POR characteristics .................................................................................................................... 1331
33.7.4 LVD characteristics .................................................................................................................... 1331
33.8 RAM Data Retention Characteristics .......................................................................................... 1331
33.9 Capacitance Connected to REGC ............................................................................................... 1332
33.10 Flash programming characteristics.......................................................................................... 1332
CHAPTER 34 ELECTRICAL SPECIFICATIONS (L GRADE PRODUCT) ......................................... 1333
34.1 Absolute Maximum Ratings ........................................................................................................ 1335
34.2 Power consumption characteristics ........................................................................................... 1337
34.2.1 Product group A .......................................................................................................................... 1337
34.2.2 Product group B .......................................................................................................................... 1340
34.3 Oscillator characteristics............................................................................................................. 1343
34.3.1 Main(X1) oscillator characteristics .............................................................................................. 1343
34.3.2 High speed on chip oscillator characteristics .............................................................................. 1343
34.3.3 Low speed on chip oscillator characteristics............................................................................... 1343
34.3.4 Sub(XT1) oscillator characteristics ............................................................................................. 1343
Index-15
34.4 DC characteristics ........................................................................................................................ 1344
34.4.1 Pin group 1 ................................................................................................................................. 1344
34.4.2 Pin group 2 (ANI pins) ................................................................................................................ 1348
34.4.3 Pin group 3 (SMC pins) .............................................................................................................. 1349
34.4.4 Pin group 4 (OSC, reset and P137 pins) .................................................................................... 1355
34.5 AC characteristics ........................................................................................................................ 1357
34.5.1 Basic operation........................................................................................................................... 1357
34.5.2 Stepper motor controller/driver ................................................................................................... 1359
34.5.3 Sound generator ......................................................................................................................... 1360
34.5.4 Serial interface: CSI operation.................................................................................................... 1361
34.5.5 Serial interface: UART operation (128-pin only) ......................................................................... 1363
34.5.6 Serial interface: simplified I2C operation ..................................................................................... 1364
34.5.7 Serial interface: LIN-UART(UARTF) operation ........................................................................... 1365
34.5.8 Serial interface: CAN operation .................................................................................................. 1365
34.6 LCD Bus Interface characteristics (128-pin products only) ..................................................... 1366
34.6 LCD characteristics ...................................................................................................................... 1368
34.6 LCD characteristics ...................................................................................................................... 1369
34.7 Analog characteristics ................................................................................................................. 1371
34.7.1 A/D converter characteristics...................................................................................................... 1371
34.7.2 ZPD characteristics .................................................................................................................... 1372
34.7.3 POR characteristics .................................................................................................................... 1373
34.7.4 LVD characteristics .................................................................................................................... 1373
34.8 Data Retention Characteristics ................................................................................................... 1373
34.9 Capacitance Connected to REGC ............................................................................................... 1374
34.10 Flash programming characteristics.......................................................................................... 1374
CHAPTER 35 PACKAGE DRAWINGS ............................................................................................... 1375
35.1 48-pin products ............................................................................................................................. 1375
35.2 64-pin products ............................................................................................................................. 1375
35.2 64-pin products ............................................................................................................................. 1376
35.3 80-pin products ............................................................................................................................. 1377
35.4 100-pin products ........................................................................................................................... 1378
35.5 128-pin products ........................................................................................................................... 1379
APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS ..................................... 1380
Index-16
R01UH0317EJ0110
Rev. 1.10
RL78/D1A
RENESAS MCU
Mar 23. 2015
CHAPTER 1 OUTLINE
1.1 Features
Minimum instruction execution time can be changed from high speed (0.03125 s: @ 32 MHz operation with highspeed on-chip oscillator clock) to ultra low-speed (30.5 s: @ 32.768 kHz operation with subsystem clock)
General-purpose register: 8 bits 32 registers (8 bits 8 registers 4 banks)
ROM: 24 to 512 KB, RAM: 2 to 24 KB, Data flash memory: 8 KB
On-chip high-speed on-chip oscillator clocks
Select from 32 MHz (TYP.), 24 MHz (TYP.), 16 MHz (TYP.), 8 MHz (TYP.), and 4 MHz (TYP.)
On-chip single-power-supply flash memory (with prohibition of block erase/writing function)
Self-programming (with boot swap function/flash shield window function)
On-chip debug function
On-chip power-on-reset (POR) circuit and voltage detector (LVD)
On-chip watchdog timer (operable with the dedicated low-speed on-chip oscillator clock)
On-chip multiplier and divider/multiply-accumulator
16 bits 16 bits = 32 bits (Unsigned or signed)
32 bits 32 bits = 32 bits (Unsigned)
16 bits 16 bits + 32 bits = 32 bits (Unsigned or signed)
On-chip clock output/buzzer output controller
On-chip BCD adjustment
I/O ports: 38 to 112
CMOS I/O port: 35 to 107 (LED direct drive port: 9 to 16, N-ch OD selectable port: 4 to 6)
CMOS input port: 5
CMOS output port: 0 to 1
Timer
16-bit timer:
24 channels
Watchdog timer:
1 channel
Real-time clock:
1 channel
Interval timer:
1 channel
Serial interface
CSI
UART (LIN-bus supported)
Simplified I2C communication
aFCAN controller
Stepper motor controller/driver with zero point detection (ZPD): 1, 2, 4-channels
LCD controller/driver (seg com): 27 4, 39 4, 48 4, 53 4 and 54 4
LCD Bus I/F
RESET output
STOP status output
Sound generator
8/10-bit resolution A/D converter (VDD = EVDD =2.7 to 5.5 V): 3+2 to 9+2 channels
Standby function: HALT, STOP, SNOOZE mode
Power supply voltage: VDD = 2.7 to 5.5 V
Operating ambient temperature: J grade products TA = 40 to +85C,
L grade products TA = 40 to +105C
R01UH0317EJ0110 Rev. 1.10
Mar 23. 2015
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RL78/D1A
CHAPTER 1 OUTLINE
Remark The functions mounted depend on the product. See 1.7 Outline of Functions.
Table 1-1. ROM, RAM capacities
Flash
Data
ROM
flash
RAM
48-pin
64-pin
80-pin
512 KB 8 KB
24 KB
384 KB
20 KB
256 KB
16 KB
R5F10DMJxFB
128 KB
8 KB
R5F10DMGxFB
96 KB
6 KB
R5F10DMFxFB
64 KB
4 KB
48 KB
3 KB
R5F10CGDxFB
R5F10DGDxFB
32 KB
2 KB
R5F10CGCxFB
R5F10DGCxFB
24 KB
2 KB
R5F10CGBxFB
CAN (ch)
R5F10DGExFB
0
Stepper Motor (ch)
LCD (seg com)
Flash
Data
ROM
flash
RAM
R5F10CLDxFB
R5F10DLDxFB
R5F10CMDxFB
R5F10DMDxFB
1
0
1
0
1
1
2
4
27 4
39 4
48 4
128-pin
24 KB
R5F10DPLxFB
R5F10DSLxFB
384 KB
20 KB
R5F10DPKxFB
R5F10DSKxFB
256 KB
16 KB
R5F10TPJxFB
R5F10DPJxFB
R5F10DSJxFB
128 KB
8 KB
R5F10DPGxFB
96 KB
6 KB
R5F10DPFxFB
64 KB
4 KB
R5F10DPExFB
48 KB
3 KB
32 KB
2 KB
24 KB
2 KB
1
2
2
LCD (seg com)
R5F10DMExFB
100-pin
Stepper Motor (ch)
R5F10CMExFB
512 KB 8 KB
CAN (ch)
R5F10DLExFB
4
4
53 4
54 4
1.2 Applications
Automotive electrical appliances (instrument cluster)
R01UH0317EJ0110 Rev. 1.10
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RL78/D1A
CHAPTER 1 OUTLINE
1.3 Ordering Information
[List of Part Number]
Pin count
48-pin
64-pin
80-pin
100-pin
Package
Operating ambient temperature
Operating ambient temperature
J grade
L grade
(TA = -40 to +85 C)
(TA = -40 to +105 C)
48-pin plastic LQFP (fine pitch)
R5F10CGBJFB
R5F10CGBLFB
(7 7)
R5F10CGCJFB
R5F10CGCLFB
R5F10CGDJFB
R5F10CGDLFB
R5F10DGCJFB
R5F10DGCLFB
R5F10DGDJFB
R5F10DGDLFB
R5F10DGEJFB
R5F10DGELFB
64-pin plastic LQFP (fine pitch)
R5F10CLDJFB
R5F10CLDLFB
(10 10)
R5F10DLDJFB
R5F10DLDLFB
R5F10DLEJFB
R5F10DLELFB
80-pin plastic LQFP (fine pitch)
R5F10CMDJFB
R5F10CMDLFB
(12 12)
R5F10CMEJFB
R5F10CMELFB
R5F10DMDJFB
R5F10DMDLFB
R5F10DMEJFB
R5F10DMELFB
R5F10DMFJFB
R5F10DMFLFB
R5F10DMGJFB
R5F10DMGLFB
R5F10DMJJFB
R5F10DMJLFB
R5F10DPEJFB
R5F10DPELFB
100-pin plastic LQFP (fine pitch)
(14 14)
128-pin
Part Number
R5F10DPFJFB
R5F10DPFLFB
R5F10DPGJFB
R5F10DPGLFB
R5F10TPJJFB
R5F10TPJLFB
R5F10DPJJFB
R5F10DPJLFB
R5F10DPKJFB
R5F10DPKLFB
R5F10DPLJFB
R5F10DPLLFB
128-pin plastic LQFP (fine pitch)
R5F10DSLJFB
R5F10DSLLFB
(14 20)
R5F10DSKJFB
R5F10DSKLFB
R5F10DSJJFB
R5F10DSJLFB
R01UH0317EJ0110 Rev. 1.10
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RL78/D1A
CHAPTER 1 OUTLINE
1.4 Pin Configuration (Top View)
1.4.1 48-pin products (R5F10CGBxFB, R5F10CGCxFB, R5F10CGDxFB: with no CAN)
P31/TI21/TO21/SDA11/SEG7
P30/TI20/TO20/SCL11/SEG6
P57/TI17/TO17/SEG5
P56/TI16/TO16/SCK01/SEG4
P55/TI15/TO15/SI01/SEG3
P54/TI14/TO14/SO01/SEG2
P72/ADTRG/SGOA/SEG1
P73/SGO/SGOF/SEG0
COM3
COM2
COM1
COM0
48-pin plastic LQFP (fine pitch) (7 7)
36 35 34 33 32 31 30 29 28 27 26 25
P94/RTC1HZ/TI01/TO01/SEG44
37
24 P33/TI23/TO23/SEG9
P93/SGO/SGOF/TI27/TO27/SEG43
38
23 P00/TI00/TO00/SEG14
P92/SGOA/TI25/TO25/SEG42
39
22 P01/TI01/TO01/SEG15
P91/TI23/TO23/SEG41
40
21 P14/TI14/TO14/SEG24
P90/TI21/TO21/SEG40
41
20 P13/SO01/TI13/TO13/SEG25
SMVSS
42
19 P74/SCK01/TI23/TO23/SEG26
SMVDD
43
18 P75/PCL/SI01/TI22/TO22/SEG27
P83/SM14/ZPD14/TI07/TO07/SEG35
44
17 P12/SO00/TI12/TO12/INTP2/SEG29
P82/SM13/TI05/TO05/SEG34
45
16 P11/LRxD1/INTPLR1/SI00/TI11/TO11/SEG30
P81/SM12/TI03/TO03/SEG33
46
15 P10/LTxD1/SCK00/TI10/TO10/INTP4/SEG31
P80/SM11/TI01/TO01/SEG32
47
14 P61/SDA11/TI21/TO21/INTP3
ANI7/P27
48
13 P60/SCL11/TI20/TO20/INTP1
VDD/EVDD
VSS/EVSS
REGC
X1/P121
P137/INTP5
X2/EXCLK/P122
RESET
TOOL0/P40
AVREFP/ANI0/P20
AVREFM/ANI1/P21
ANI2/P22
ANI3/P23
1 2 3 4 5 6 7 8 9 10 11 12
Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 F)
Remark For pin identification, see 1.5 Pin Identification.
R01UH0317EJ0110 Rev. 1.10
Mar 23. 2015
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RL78/D1A
CHAPTER 1 OUTLINE
1.4.2 48-pin products (R5F10DGCxFB, R5F10DGDxFB, R5F10DGExFB: with CAN)
48-pin plastic LQFP (fine pitch) (7 7)
36 35 34 33 32 31 30 29 28 27 26 25
P94/RTC1HZ/TI01/TO01/SEG44
37
24 P33/TI23/TO23/SEG9
P93/SGO/SGOF/TI27/TO27/SEG43
38
23 P00/CTxD0/TI00/TO00/SEG14
P92/SGOA/TI25/TO25/SEG42
39
22 P01/CRxD0/TI01/TO01/SEG15
P91/TI23/TO23/SEG41
40
21 P14/TI14/TO14/SEG24
P90/TI21/TO21/SEG40
41
20 P13/SO01/TI13/TO13/SEG25
SMVSS
42
19 P74/SCK01/TI23/TO23/SEG26
SMVDD
43
18 P75/PCL/SI01/TI22/TO22/SEG27
P83/SM14/ZPD14/TI07/TO07/SEG35
44
17 P12/SO00/TI12/TO12/INTP2/SEG29
P82/SM13/TI05/TO05/SEG34
45
16 P11/LRxD1/INTPLR1/SI00/TI11/TO11/SEG30
P81/SM12/TI03/TO03/SEG33
46
15 P10/LTxD1/SCK00/TI10/TO10/INTP4/SEG31
P80/SM11/TI01/TO01/SEG32
47
14 P61/SDA11/TI21/TO21/INTP3
ANI7/P27
48
13 P60/SCL11/TI20/TO20/INTP1
1 2 3 4 5 6 7 8 9 10 11 12
Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 F)
Remark For pin identification, see 1.5 Pin Identification.
R01UH0317EJ0110 Rev. 1.10
Mar 23. 2015
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RL78/D1A
CHAPTER 1 OUTLINE
1.4.3 64-pin products (R5F10CLDxFB: with no CAN)
COM0
COM1
COM2
COM3
P73/SGO/SGOF/SEG0
P72/ADTRG/SGOA/SEG1
P54/TI14/TO14/SO01/SEG2
P55/TI15/TO15/SI01/SEG3
P56/TI16/TO16/SCK01/SEG4
P57/TI17/TO17/SEG5
P30/TI20/TO20/SCL11/SEG6
P31/TI21/TO21/SDA11/SEG7
P32/TI22/TO22/SEG8
P33/TI23/TO23/SEG9
P00/TI00/TO00/SEG14
P01/TI01/TO01/SEG15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64-pin plastic LQFP (fine pitch) (10 10)
60
21
P12/SO00/TI12/TO12/INTP2/SEG29
P82/SM13/TI05/TO05/SEG34
61
20
P11/LRxD1/INTPLR1/SI00/TI11/TO11/SEG30
P81/SM12/TI03/TO03/SEG33
62
19
P10/LTxD1/SCK00/TI10/TO10/INTP4/SEG31
P80/SM11/TI01/TO01/SEG32
63
18
ANI7/P27
64
17
P61/SDA11/TI21/TO21/INTP3
P60/SCL11/TI20/TO20/INTP1
16
P17/TI17/TO17/INTP0/SEG28
P83/SM14/ZPD14/TI07/TO07/SEG35
VDD/EVDD
22
15
59
VSS/EVSS
P75/PCL/SI01/TI22/TO22/SEG27
SMVDD
14
23
REGC
58
13
P74/SCK01/TI23/TO23/SEG26
SMVSS
X1/P121
24
12
57
X2/EXCLK/P122
P13/SO01/TI13/TO13/SEG25
P84/SM21/TI11/TO11/SEG36
11
25
P137/INTP5
56
10
P14/TI14/TO14/LRxD0/INTPLR0/SEG24
P85/SM22/TI13/TO13/SEG37
XT1/P123
26
9
55
XT2/P124
P15/TI15/TO15/LTxD0/RTC1HZ/SEG23
P86/SM23/TI15/TO15/SEG38
8
27
RESET
54
7
P07/TI07/TO07/TI17/TO17/SEG21
P87/SM24/ZPD24/TI17/TO17/SEG39
P70/LRxD0/INTPLR0/TI03/TO03/TOOLRXD
28
6
53
P71/LTxD0/TOOLTXD
P05/TI05/TO05/TI15/TO15/SEG19
P90/TI21/TO21/SEG40
5
29
TOOL0/P40
52
4
P04/SCK00/TI04/TO04/TI14/TO14/SEG18
P91/TI23/TO23/SEG41
AVREFP/ANI0/P20
30
3
51
AVREFM/ANI1/P21
P03/SI00/TI03/TO03/TI13/TO13/SEG17
P92/TI25/TO25/SGOA/SEG42
2
P02/SO00/TI02/TO02/TI12/TO12/SEG16
31
1
32
50
ANI2/P22
49
ANI3/P23
P94/TI01/TO01/RTC1HZ/SEG44
P93/TI27/TO27/SGO/SGOF/SEG43
Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 F)
Remark For pin identification, see 1.5 Pin Identification.
R01UH0317EJ0110 Rev. 1.10
Mar 23. 2015
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RL78/D1A
CHAPTER 1 OUTLINE
1.4.4 64-pin products (R5F10DLDxFB, R5F10DLExFB: with CAN)
COM0
COM1
COM2
COM3
P73/SGO/SGOF/SEG0
P72/ADTRG/SGOA/SEG1
P54/TI14/TO14/SO01/SEG2
P55/TI15/TO15/SI01/SEG3
P56/TI16/TO16/SCK01/SEG4
P57/TI17/TO17/SEG5
P30/TI20/TO20/SCL11/SEG6
P31/TI21/TO21/SDA11/SEG7
P32/TI22/TO22/SEG8
P33/TI23/TO23/SEG9
P00/TI00/TO00/CTxD0/SEG14
P01/TI01/TO01/CRxD0/SEG15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64-pin plastic LQFP (fine pitch) (10 10)
60
21
P12/SO00/TI12/TO12/INTP2/SEG29
P82/SM13/TI05/TO05/SEG34
61
20
P11/LRxD1/INTPLR1/SI00/TI11/TO11/SEG30
P81/SM12/TI03/TO03/SEG33
62
19
P10/LTxD1/SCK00/TI10/TO10/INTP4/SEG31
P80/SM11/TI01/TO01/SEG32
63
18
ANI7/P27
64
17
P61/SDA11/TI21/TO21/INTP3
P60/SCL11/TI20/TO20/INTP1
16
P17/TI17/TO17/INTP0/SEG28
P83/SM14/ZPD14/TI07/TO07/SEG35
VDD/EVDD
22
15
59
VSS/EVSS
P75/PCL/SI01/TI22/TO22/SEG27
SMVDD
14
23
REGC
58
13
P74/SCK01/TI23/TO23/SEG26
SMVSS
X1/P121
24
12
57
X2/EXCLK/P122
P13/SO01/TI13/TO13/SEG25
P84/SM21/TI11/TO11/SEG36
11
25
P137/INTP5
56
10
P14/TI14/TO14/LRxD0/INTPLR0/SEG24
P85/SM22/TI13/TO13/SEG37
XT1/P123
26
9
55
XT2/P124
P15/TI15/TO15/LTxD0/RTC1HZ/SEG23
P86/SM23/TI15/TO15/SEG38
8
27
RESET
54
7
P07/TI07/TO07/TI17/TO17/SEG21
P87/SM24/ZPD24/TI17/TO17/SEG39
P70/CRxD0/LRxD0/INTPLR0/TI03/TO03/TOOLRXD
28
6
53
P71/CTxD0/LTxD0/TOOLTXD
P05/TI05/TO05/TI15/TO15/SEG19
P90/TI21/TO21/SEG40
5
29
TOOL0/P40
52
4
P04/SCK00/TI04/TO04/TI14/TO14/SEG18
P91/TI23/TO23/SEG41
AVREFP/ANI0/P20
30
3
51
AVREFM/ANI1/P21
P03/SI00/TI03/TO03/TI13/TO13/SEG17
P92/TI25/TO25/SGOA/SEG42
2
P02/SO00/TI02/TO02/TI12/TO12/SEG16
31
1
32
50
ANI2/P22
49
ANI3/P23
P94/TI01/TO01/RTC1HZ/SEG44
P93/TI27/TO27/SGO/SGOF/SEG43
Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 F)
Remark For pin identification, see 1.5 Pin Identification.
R01UH0317EJ0110 Rev. 1.10
Mar 23. 2015
7
RL78/D1A
CHAPTER 1 OUTLINE
1.4.5 80-pin products (R5F10CMDxFB, R5F10CMExFB: with no CAN)
P33/TI23/TO23/SI00/SEG9
P35/TI25/TO25/SEG11
P36/TI26/TO26/SEG12
P37/TI27/TO27/SEG13
P00/TI00/TO00/SEG14
P01/TI01/TO01/SEG15
45
44
43
42
41
P32/TI22/TO22/SO00/SEG8
P34/TI24/TO24/SCK00/SEG10
P31/TI21/TO21/SDA11/SEG7
48
46
P30/TI20/TO20/SCL11/SEG6
49
47
P57/TI17/TO17/SEG5
P54/TI14/TO14/SO01/SEG2
50
P72/ADTRG/SGOA/SEG1
54
51
P73/SGO/SGOF/SEG0
55
P55/TI15/TO15/SI01/SEG3
COM3
56
P56/TI16/TO16/SCK01/SEG4
COM2
57
52
COM1
58
53
COM0
59
14
15
16
17
18
19
20
XT1/P123
P137/INTP5
X2/EXCLK/P122
X1/P121
REGC
VSS/EVSS
VDD/EVDD
9
TOOL0/P40
13
8
AVREFP/ANI0/P20
XT2/P124
7
AVREFM/ANI1/P21
12
6
ANI2/P22
RESET
5
ANI3/P23
11
4
ANI4/P24
10
3
ANI5/P25
P71/LTxD0/TOOLTXD
2
P70/LRxD0/INTPLR0/TI03/TO03/TOOLRXD
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
ANI6/P26
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
ANI7/P27
P97/SM44/ZPD44/TI07/TO07/SEG47
P96/SM43/TI05/TO05/SEG46
P95/SM42/TI03/TO03/SEG45
P94/SM41/TI01/TO01/RTC1HZ/SEG44
SMVSS1
SMVDD1
P93/SM34/ZPD34/TI27/TO27/SGO/SGOF/SEG43
P92/SM33/TI25/TO25/SGOA/SEG42
P91/SM32/TI23/TO23/SEG41
P90/SM31/TI21/TO21/SEG40
P87/SM24/ZPD24/TI17/TO17/SEG39
P86/SM23/TI15/TO15/SEG38
P85/SM22/TI13/TO13/SEG37
P84/SM21/TI11/TO11/SEG36
SMVSS0
SMVDD0
P83/SM14/ZPD14/TI07/TO07/SEG35
P82/SM13/TI05/TO05/SEG34
P81/SM12/TI03/TO03/SEG33
P80/SM11/TI01/TO01/SEG32
60
80-pin plastic LQFP (fine pitch) (12 12)
P02/SO00/TI02/TO02/TI12/TO12/SEG16
P03/SI00/TI03/TO03/TI13/TO13/SEG17
P04/SCK00/TI04/TO04/TI14/TO14/SEG18
P05/TI05/TO05/TI15/TO15/SEG19
P06/TI06/TO06/TI16/TO16/SEG20
P07/TI07/TO07/TI17/TO17/SEG21
P16/TI16/TO16/SEG22
P15/TI15/TO15/LTxD0/RTC1HZ/SEG23
P14/TI14/TO14/LRxD0/INTPLR0/SEG24
P13/SO01/TI13/TO13/SEG25
P74/SCK01/TI23/TO23/SEG26
P75/PCL/SI01/TI22/TO22/SEG27
P17/TI17/TO17/INTP0/SEG28
P12/SO00/TI12/TO12/INTP2/SEG29
P11/LRxD1/INTPLR1/SI00/TI11/TO11/SEG30
P10/LTxD1/SCK00/TI10/TO10/INTP4/SEG31
P66/TI24/TO24/PCL
P65/TI25/TO25
P61/SDA11/TI21/TO21/INTP3
P60/SCL11/TI20/TO20/INTP1
Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 F)
Remark For pin identification, see 1.5 Pin Identification.
R01UH0317EJ0110 Rev. 1.10
Mar 23. 2015
8
RL78/D1A
CHAPTER 1 OUTLINE
1.4.6 80-pin products (R5F10DMDxFB, R5F10DMExFB, R5F10DMFxFB, R5F10DMGxFB, R5F10DMJxFB: with CAN)
80-pin plastic LQFP (fine pitch) (12 12)
Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 F)
Remark For pin identification, see 1.5 Pin Identification.
R01UH0317EJ0110 Rev. 1.10
Mar 23. 2015
9
RL78/D1A
CHAPTER 1 OUTLINE
1.4.7 100-pin products (R5F10DPExFB, R5F10DPFxFB, R5F10DPGxFB, R5F10TPJxFB: with 1 ch of CAN)
P35/TI25/TO25/SEG11
P36/TI26/TO26/SEG12
P37/TI27/TO27/SEG13
P00/TI00/TO00/CTxD0/SEG14
P01/TI01/TO01/CRxD0/SEG15
55
53
52
51
54
P33/TI23/TO23/SI00/SEG9
P34/TI24/TO24/SCK00/SEG10
P32/TI22/TO22/SO00/SEG8
58
56
P31/TI21/TO21/SDA11/SEG7
59
57
P57/TI17/TO17/SEG5
P30/TI20/TO20/SCL11/SEG6
60
P72/ADTRG/SGOA/SEG1
65
61
P73/SGO/SGOF/SEG0
66
62
COM3
67
P54/TI14/TO14/SO01/SEG2
COM2
68
P55/TI15/TO15/SI01/SEG3
P56/TI16/TO16/SCK01/SEG4
COM1
69
63
COM0
70
64
P52/TI06/TO06/SI10/SEG51
P53/TI13/TO13/SO10/SEG52
71
P50/TI02/TO02/SDA11/SEG49
P51/TI04/TO04/SCK10/SEG50
72
P136/TI00/TO00/SCL11/SEG48
74
73
75
100-pin plastic LQFP (fine pitch) (14 14)
P97/SM44/ZPD44/TI07/TO07/SEG47
76
50
P02/SO00/TI02/TO02/TI12/TO12/SEG16
P96/SM43/TI05/TO05/SEG46
77
49
P03/SI00/TI03/TO03/TI13/TO13/SEG17
P95/SM42/TI03/TO03/SEG45
78
48
P04/SCK00/TI04/TO04/TI14/TO14/SEG18
P94/SM41/TI01/TO01/RTC1HZ/SEG44
79
47
P05/TI05/TO05/TI15/TO15/SEG19
SMVSS1
80
46
P06/TI06/TO06/TI16/TO16/SEG20
SMVDD1
81
45
P07/TI07/TO07/TI17/TO17/SEG21
P93/SM34/ZPD34/TI27/TO27/SGO/SGOF/SEG43
82
44
P16/TI16/TO16/SEG22
P92/SM33/TI25/TO25/SGOA/SEG42
83
43
P15/TI15/TO15/LTxD0/RTC1HZ/SEG23
P91/SM32/TI23/TO23/SEG41
84
42
P14/TI14/TO14/LRxD0/INTPLR0/SEG24
P90/SM31/TI21/TO21/SEG40
85
41
P13/SO01/TI13/TO13/SEG25
P87/SM24/ZPD24/TI17/TO17/SEG39
86
40
P74/SCK01/TI23/TO23/SEG26
P86/SM23/TI15/TO15/SEG38
87
39
P75/PCL/SI01/TI22/TO22/SEG27
P85/SM22/TI13/TO13/SEG37
P84/SM21/TI11/TO11/SEG36
88
38
P17/TI17/TO17/INTP0/SEG28
89
37
P12/SO00/TI12/TO12/INTP2/SEG29
13
14
15
16
17
18
19
20
21
22
23
24
25
P140/TI11/TO11
RESET
XT2/P124
XT1/P123
P137/INTP5
X2/EXCLK/P122
X1/P121
REGC
VSS
EVSS0
VDD
EVDD0
P60/SCL11/TI20/TO20/INTP1
P70/CRxD0/LRxD0/INTPLR0/TI03/TO03/TOOLRXD
26
12
P61/SDA11/TI21/TO21/INTP3
P131/SO10/LTxD1/TI21/TO21
P71/CTxD0/LTxD0/TOOLTXD
27
11
99
100
TOOL0/P40
P62/TI27/TO27
P132/SI10/LRxD1/INTPLR1/TI20/TO20
10
28
AVREFP/ANI0/P20
P63/TI26/TO26
98
9
29
AVREFM/ANI1/P21
97
8
P64/RTC1HZ/TI11/TO11
P134/SGOA/TI24/TO24
P133/SCK10/TI22/TO22
ANI2/P22
30
7
P65/TI25/TO25
96
6
31
ANI3/P23
95
ANI4/P24
P66/TI24/TO24/PCL
P80/SM11/TI01/TO01/SEG32
P135/SGO/SGOF/TI26/TO26
5
32
ANI5/P25
EVDD1
94
ANI6/P26
EVSS1
33
4
34
93
ANI7/P27
92
P82/SM13/TI05/TO05/SEG34
P81/SM12/TI03/TO03/SEG33
3
P10/LTxD1/SCK00/TI10/TO10/INTP4/SEG31
2
P11/LRxD1/INTPLR1/SI00/TI11/TO11/SEG30
35
1
36
91
P130
90
ANI8/P150
SMVSS0
SMVDD0
P83/SM14/ZPD14/TI07/TO07/SEG35
Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 F)
Remark For pin identification, see 1.5 Pin Identification.
R01UH0317EJ0110 Rev. 1.10
Mar 23. 2015
10
RL78/D1A
CHAPTER 1 OUTLINE
1.4.8 100-pin products (R5F10DPJxFB, R5F10DPKxFB, R5F10DPLxFB: with 2 ch of CAN)
P35/TI25/TO25/SEG11
P36/TI26/TO26/SEG12
P37/TI27/TO27/SEG13
P00/TI00/TO00/CTxD0/SEG14
P01/TI01/TO01/CRxD0/SEG15
55
53
52
51
54
P33/TI23/TO23/SI00/SEG9
P34/TI24/TO24/SCK00/SEG10
P32/TI22/TO22/SO00/SEG8
58
56
P31/TI21/TO21/SDA11/SEG7
59
57
P57/TI17/TO17/SEG5
P30/TI20/TO20/SCL11/SEG6
60
P72/ADTRG/SGOA/SEG1
65
61
P73/SGO/SGOF/SEG0
66
62
COM3
67
P54/TI14/TO14/SO01/SEG2
COM2
68
P55/TI15/TO15/SI01/SEG3
P56/TI16/TO16/SCK01/SEG4
COM1
69
63
COM0
70
64
P52/TI06/TO06/SI10/SEG51
P53/TI13/TO13/SO10/SEG52
71
P50/TI02/TO02/SDA11/SEG49
P51/TI04/TO04/SCK10/SEG50
72
P136/TI00/TO00/SCL11/SEG48
74
73
75
100-pin plastic LQFP (fine pitch) (14 14)
P97/SM44/ZPD44/TI07/TO07/SEG47
76
50
P02/SO00/TI02/TO02/TI12/TO12/SEG16
P96/SM43/TI05/TO05/SEG46
77
49
P03/SI00/TI03/TO03/TI13/TO13/SEG17
P95/SM42/TI03/TO03/SEG45
78
48
P04/SCK00/TI04/TO04/TI14/TO14/SEG18
P94/SM41/TI01/TO01/RTC1HZ/SEG44
79
47
P05/TI05/TO05/TI15/TO15/SEG19
SMVSS1
80
46
P06/TI06/TO06/TI16/TO16/SEG20
SMVDD1
81
45
P07/TI07/TO07/TI17/TO17/SEG21
P93/SM34/ZPD34/TI27/TO27/SGO/SGOF/SEG43
82
44
P16/TI16/TO16/SEG22
P92/SM33/TI25/TO25/SGOA/SEG42
83
43
P15/TI15/TO15/LTxD0/RTC1HZ/SEG23
P91/SM32/TI23/TO23/SEG41
84
42
P14/TI14/TO14/LRxD0/INTPLR0/SEG24
P90/SM31/TI21/TO21/SEG40
85
41
P13/SO01/TI13/TO13/SEG25
P87/SM24/ZPD24/TI17/TO17/SEG39
86
40
P74/SCK01/TI23/TO23/SEG26
P86/SM23/TI15/TO15/SEG38
87
39
P75/PCL/SI01/TI22/TO22/SEG27
P85/SM22/TI13/TO13/SEG37
P84/SM21/TI11/TO11/SEG36
88
38
P17/TI17/TO17/INTP0/SEG28
89
37
P12/SO00/TI12/TO12/INTP2/SEG29
13
14
15
16
17
18
19
20
21
22
23
24
25
P140/TI11/TO11
RESET
XT2/P124
XT1/P123
P137/INTP5
X2/EXCLK/P122
X1/P121
REGC
VSS
EVSS0
VDD
EVDD0
P60/SCL11/TI20/TO20/INTP1
P70/CRxD0/LRxD0/INTPLR0/TI03/TO03/TOOLRXD
26
12
P61/SDA11/TI21/TO21/INTP3
P131/SO10/LTxD1/TI21/TO21
P71/CTxD0/LTxD0/TOOLTXD
27
11
99
100
TOOL0/P40
P62/CTxD1/TI27/TO27
P132/SI10/LRxD1/INTPLR1/TI20/TO20
10
28
AVREFP/ANI0/P20
P63/CRxD1/TI26/TO26
98
9
29
AVREFM/ANI1/P21
97
8
P64/RTC1HZ/TI11/TO11
P134/SGOA/CTxD1/TI24/TO24
P133/SCK10/TI22/TO22
ANI2/P22
30
7
P65/TI25/TO25
96
6
31
ANI3/P23
95
ANI4/P24
P66/TI24/TO24/PCL
P80/SM11/TI01/TO01/SEG32
P135/SGO/SGOF/CRxD1/TI26/TO26
5
32
ANI5/P25
EVDD1
94
ANI6/P26
EVSS1
33
4
34
93
ANI7/P27
92
P82/SM13/TI05/TO05/SEG34
P81/SM12/TI03/TO03/SEG33
3
P10/LTxD1/SCK00/TI10/TO10/INTP4/SEG31
2
P11/LRxD1/INTPLR1/SI00/TI11/TO11/SEG30
35
1
36
91
P130
90
ANI8/P150
SMVSS0
SMVDD0
P83/SM14/ZPD14/TI07/TO07/SEG35
Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 F)
Remark For pin identification, see 1.5 Pin Identification.
R01UH0317EJ0110 Rev. 1.10
Mar 23. 2015
11
P60/SCL11/TI20/TO20/INTP1
P61/SDA11/TI21/TO21/INTP3
P62/CTxD1/TI27/TO27
P63/CRxD1/TI26/TO26
P64/RTC1HZ/TI11/TO11
P65/TI25/TO25
P66/TI24/TO24/PCL
EVDD1
EVSS1
P110/DBD0/SCK00/TI00/TO00/SEG35
P111/DBD1/SI00/RxD0/TI02/TO02/SEG34
P112/DBD2/SO00/TxD0/TI04/TO04/SEG33
P113/DBD3/TI06/TO06/SEG32
P114/DBD4/TI07/TO07/SEG31
P115/DBD5/TI10/TO10/SEG30
P116/DBD6/TI12/TO12/SEG29
P117/DBD7/TI20/TO20/SEG28
P46/DBWR/SEG27
P47/DBRD/SEG26
P10/LTxD1/SCK00/TI10/TO10/INTP4/SEG31
P11/LRxD1/INTPLR1/SI00/RxD0/TI11/TO11/SEG30
P12/SO00/TxD0/TI12/TO12/INTP2/SEG29
P17/TI17/TO17/INTP0/SEG28
P75/SI01/TI22/TO22/SEG27/PCL
P74/SCK01/TI23/TO23/SEG26
P13/SO01/TI13/TO13/SEG25
P14/LRxD0/INTPLR0/TI14/TO14/SEG24
P15/LTxD0/RTC1HZ/TI15/TO15/SEG23
P16/TI16/TO16/SEG22
P07/TI07/TO07/TI17/TO17/SEG21
P06/TI06/TO06/TI16/TO16/SEG20
P05/TI05/TO05/TI15/TO15/SEG19
P04/SCK00/TI04/TO04/TI14/TO14/SEG18
P03/SI00/RxD0/TI03/TO03/TI13/TO13/SEG17
P02/SO00/TxD0/TI02/TO02/TI12/TO12/SEG16
P125/TI12/TO12/SEG25
P126/TI14/TO14/SEG24
P127/TI16/TO16/SEG23
ANI10/P152
ANI9/P151
ANI8/P150
ANI7/P27
ANI6/P26
ANI5/P25
ANI4/P24
ANI3/P23
ANI2/P22
AVREFM/ANI1/P21
AVREFP/ANI0/P20
TOOL0/P40
P71/CTxD0/LTxD0/TOOLTxD
P70/CRxD0/LRxD0/INTPLR0/TI03/TO03/TOOLRxD
P140/TI11/TO11
RESET
XT2/P124
XT1/P123
P137/INTP5
X2/EXCLK/P122
X1/P121
REGC
VSS
EVSS0
VDD
EVDD0
R01UH0317EJ0110 Rev. 1.10
Mar 23. 2015
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
P130/RESOUT
P41/STOPST/TI04/TO04
P131/SO10/LTxD1/TI21/TO21
P132/SI10/LRxD1/INTPLR1/TI20/TO20
P133/SCK10/TI22/TO22
P134/SGOA/CTxD1/TI24/TO24
P135/SGO/SGOF/CRxD1/TI26/TO26
P42/TI10/TO10/SEG7
P43/TI22/TO22/SEG14
P44/TI23/TO23/SEG15
P100/I24/TO24/SEG36
P101/TI25/TO25/SEG37
P102/TI26/TO26/SEG38
P103/TI27/TO27/SEG39
P80/SM11/TI01/TO01/SEG32
P81/SM12/TI03/TO03/SEG33
P82/SM13/TI05/TO05/SEG34
P83/SM14/ZPD14/TI07/TO07/SEG35
SMVDD0
SMVSS0
P84/SM21/TI11/TO11/SEG36
P85/SM22/TI13/TO13/SEG37
P86/SM23/TI15/TO15/SEG38
P87/SM24/ZPD24/TI17/TO17/SEG39
P90/SM31/TI21/TO21/SEG40
P91/SM32/TI23/TO23/SEG41
P92/SM33/SGOA/TI25/TO25/SEG42
P93/SM34/ZPD34/SGO/SGOF/TI27/TO27/SEG43
SMVDD1
SMVSS1
P94/SM41/RTC1HZ/TI01/TO01/SEG44
P95/SM42/TI03/TO03/SEG45
P96/SM43/TI05/TO05/SEG46
P97/SM44/ZPD44/TI07/TO07/SEG47
P104/TI01/TO01/SEG44
P105/TI02/TO02/SEG45
P106/TI05/TO05/SEG46
P107/TI06/TO06/SEG47
RL78/D1A
CHAPTER 1 OUTLINE
1.4.9 128-pin products (R5F10DSLxxFB, R5F10DSKxxFB, R5F10DSJxxFB)
128-pin plastic LFQFP (fine pitch) (14 20)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
P136/TI00/TO00/SCL11/SEG48
P50/TI02/TO02/SDA11/SEG49
P51/TI04/TO04/SCK10/SEG50
P52/TI06/TO06/SI10/SEG51
P53/TI13/TO13/SO10/SEG52
P45/SEG53
COM0
COM1
COM2
COM3
P73/SGO/SGOF/SEG0
P72/SGOA/ADTRG/SEG1
P54/TI14/TO14/SO01/SEG2
P55/TI15/TO15/SI01/SEG3
P56/TI16/TO16/SCK01/SEG4
P57/TI17/TO17/SEG5
P30/TI20/TO20/SCL11/SEG6
P31/TI21/TO21/SDA11/SEG7
P32/TI22/TO22/SO00/TxD0/SEG8
P33/TI23/TO23/SI00/RxD0/SEG9
P34/TI24/TO24/SCK00/SEG10
P35/TI25/TO25/SEG11
P36/TI26/TO26/SEG12
P37/TI27/TO27/SEG13
P00/CTxD0/TI00/TO00/SEG14
P01/CRxD0/TI01/TO01/SEG15
Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 F)
Remark For pin identification, see 1.5 Pin Identification.
12
RL78/D1A
CHAPTER 1 OUTLINE
1.5 Pin Identification
ANI0 to ANI10:
ADTRG:
AVREFM:
AVREFP:
Analog input
A/D conversion start
trigger external input
A/D converter reference
potential (− side) input
A/D converter reference
potential (+ side) input
COM0 to COM3:
Common output
CRxD0, CRxD1:
Receive data for CAN
CTxD0, CTxD1:
Transmit data for CAN
DBD0 to DBD7:
LCD Bus I/F data lines
___________
DBWR:
__________
DBRD:
LCD Bus I/F write strobe
LCD Bus I/F read strobe
EVDD, EVDD0, EVDD1: Power supply for port
EVSS, EVSS0, EVSS1: Ground for port
EXCLK:
External clock input
(main system clock)
INTP0 to INTP5:
External interrupt input
INTPLR0, INTPLR1: External interrupt input for LIN
LRxD0, LRxD1:
Serial data input to LIN
LTxD0, LTxD1:
Serial data output from LIN
P00 to P07:
Port 0
P10 to P17:
Port 1
P20 to P27:
Port 2
RxD0:
SCK00, SCK01, SCK10:
Receive data for UART
Serial clock input/output
SCL11:
Serial clock input/output
SDA11:
Serial data input/output
SEG0 to SEG53:
Segment output
SGO:
SGOA:
Sound generator output
Sound generator amplitude
PWM output
Sound generator frequency
output
SGOF:
SI00, SI01, SI10:
Serial data input
SM11 to SM14,
SM21 to SM24,
SM31 to SM34,
SM41 to SM44:
Stepper motor outputs
SMVDD, SMVDD0, SMVDD1: Stepper motor controller/driver
supply voltage
SMVSS, SMVSS0, SMVSS1: Stepper motor controller/driver
ground
SO00, SO01, SO10:
Serial data output
STOPST:
TI00 to TI07,
TI10 to TI17,
TI20 to TI27:
TO00 to TO07,
TO10 to TO17,
TO20 to TO27:
STOP status output
TOOL0:
TOOLRxD, TOOLTxD:
Data input/output for tool
Data input/output for external
device
Transmit data for UART
Timer input
P30 to P37:
Port 3
P40:
Port 4
P50 to P57:
Port 5
P60 to P66:
Port 6
P70 to P75:
Port 7
P80 to P87:
Port 8
VDD:
Power supply
P90 to P97:
Port 9
P121 to P124:
Port 12
VSS:
X1, X2:
Ground
Crystal oscillator (Main system
clock)
Crystal oscillator (Sub system
clock)
TxD0:
P130 to P137:
Port 13
P140:
Port 14
XT1, XT2:
P150 to P152:
PCL:
REGC:
Port 15
Programmable clock output
Regulator capacitance
ZPD14, ZPD24,
ZPD34, ZPD44:
____________
RESET:
Reset
RESOUT:
RTC1HZ:
Reset output signal
Real-time clock correction
clock (1 Hz) output
R01UH0317EJ0110 Rev. 1.10
Mar 23. 2015
Timer output
Zero point detection input
13
RL78/D1A
CHAPTER 1 OUTLINE
1.6 Block Diagram
1.6.1 48-pin products (R5F10CGBxFB, R5F10CGCxFB, R5F10CGDxFB: with no CAN)
ch0
TI01
TO01
ch1
TOOL0
TAU0 (8ch)
TO01/TI00
TO00
ch2
TI03
TO03
ch3
OCD
ch4
FSUB/FIL/TI05
TO05
ch5
RTC1HZ
ch6
RTC1HZ/TI07
TO07
ch7
Code
Flash
Data
Flash
Multiplier &
Divider,
Multiply
Accumulator
TAU1 (8ch)
TI10
TO10
ch0
TI11
TO11
ch1
TI12
TO12
ch2
TI13
TO13
ch3
TI14
TO14
TI15
TO15
ch4
RTC1HZ/TI16
TO16
ch6
RTC1HZ/TI17
TO17
ch7
BCD
Adjustment
INT61
RL78
CPU Core
ch5
PORT0
2
P00 to P01
PORT1
5
P10 to P14
PORT2
5
P20 to P23, P27
PORT3
3
P30 to P31, P33
PORT4
P40
PORT5
4
P54 to P57
PORT6
2
P60, P61
PORT7
4
P72 to P75
PORT8
4
P80 to P83
PORT9
5
P90 to P94
PORT12
2
P121 to P122
PORT13
P137
PCL/BUZ
PCL
DMA
2 ch
RAM
TAU2 (8ch)
TO21/TI20
TO20
ch0
TI21
TO21
ch1
TI22
TO22
ch2
TI23
TO23
ch3
RESET
ch4
TI25
TO25
X1 X2/EXCLK
&
PLL
4 MHz: x6, x8
8 MHz: x3, x4
ch5
Reset Control
ch6
TI27
TO27
Main OSC
(2 to 20 MHz)
Clock Control
Interrupt
Control
5
INTP1 to INTP5
1
INTPLR1
Window
Watchdog
Timer
CRC
ch7
RTC
SAU0
SCK00
SI00
SO00
CSI00
SCK01
SI01
SO01
CSI01
POR/LVD
Low Speed
OCO
15 kHz
IIC11
LRxD1
LTxD1
UARTF1
SEG0 to SEG7, SEG9
SEG14, SEG15
SEG24 to SEG27
SEG29 to SEG35
SEG40 to SEG44
COM0 to COM3
VLC0 to VLC2
Note
Note: No PAD
R01UH0317EJ0110 Rev. 1.10
Mar 23. 2015
Voltage
Regulator
Interval
timer
3
ANI2, ANI3, ANI7
ANI0/AVREFP
ANI1/AVREFM
ADTRG
4
SM11 to SM14
1
ZPD14
10bit A/D
Converter
VDD,
EVDD
LCD
Controller/Driver
4/8/16/24/32 MHz
REGC
SAU1
SCL11
SDA11
High Speed
OCO
VSS,
EVSS
Stepper
Motor
Controller/
Driver
Zero Point
Detector
Sound
Generator
SMVDD
SMVSS
SGOA
SGO/SGOF
14
RL78/D1A
CHAPTER 1 OUTLINE
1.6.2 48-pin products (R5F10DGCxFB, R5F10DGDxFB, R5F10DGExFB: with CAN)
ch0
TI01
TO01
ch1
TOOL0
TAU0 (8ch)
TO01/TI00
TO00
ch2
TI03
TO03
ch3
PORT0
2
P00 to P01
PORT1
5
P10 to P14
PORT2
5
P20 to P23, P27
PORT3
3
P30 to P31, P33
ch4
OCD
FSUB/FIL/TI05
TO05
ch5
RTC1HZ
ch6
RTC1HZ/TI07
TO07
ch7
Code
Flash
Data
Flash
Multiplier &
Divider,
Multiply
Accumulator
TAU1 (8ch)
TI10
TO10
ch0
TI11
TO11
ch1
TI12
TO12
ch2
TI13
TO13
ch3
CAN0 TSOUT/TI14
TO14
TI15
TO15
ch4
RTC1HZ/TI16
TO16
ch6
RTC1HZ/TI17
TO17
ch7
BCD
Adjustment
INT61
ch5
RL78
CPU Core
ch0
TI21
TO21
ch1
TI22
TO22
ch2
TI23
TO23
ch3
Main OSC
(2 to 20MHz)
Clock Control
ch5
X1 X2/EXCLK
&
Reset Control
PLL
4 MHz: x6, x8
8 MHz: x3, x4
ch7
CSI00
SCK01
SI01
SO01
CSI01
P54 to P57
PORT6
2
P60, P61
PORT7
4
P72 to P75
PORT8
4
P80 to P83
PORT9
5
P90 to P94
PORT12
2
P121 to P122
PORT13
P137
PCL/BUZ
PCL
Interrupt
Control
Low Speed
OCO
15 kHz
LRxD1
LTxD1
CRxD0
CTxD0
UARTF1
SEG0 to SEG7, SEG9
SEG14, SEG15
SEG24 to SEG27
SEG29 to SEG35
SEG40 to SEG44
COM0 to COM3
VLC0 to VLC2
Note
High Speed
OCO
4/8/16/24/32 MHz
Voltage
Regulator
Interval
timer
VDD,
EVDD
Note: No PAD
R01UH0317EJ0110 Rev. 1.10
Mar 23. 2015
3
ANI2, ANI3, ANI7
ANI0/AVREFP
ANI1/AVREFM
ADTRG
4
SM11 to SM14
1
ZPD14
10bit A/D
Converter
FCAN0
LCD
Controller/Driver
INTPLR1
Window
Watchdog
Timer
REGC
SAU1
IIC11
INTP1 to INTP5
1
RTC
POR/LVD
SCL11
SDA11
5
CRC
SAU0
SCK00
SI00
SO00
4
RESET
ch6
TI27
TO27
PORT5
RAM
ch4
TI25
TO25
P40
DMA
2 ch
TAU2 (8ch)
TO21/TI20
TO20
PORT4
VSS,
EVSS
Stepper
Motor
Controller/
Driver
Zero Point
Detector
Sound
Generator
SMVDD
SMVSS
SGOA
SGO/SGOF
15
RL78/D1A
CHAPTER 1 OUTLINE
1.6.3 64-pin products (R5F10CLDxFB: with no CAN)
ch2
TI03
TO03
ch3
TI04
TO04
ch4
FSUB/FIL/TI05
TO05
ch5
RTC1HZ
ch6
RTC1HZ/TI07
TO07
ch7
TOOLRxD
ch1
TI02
TO02
TOOLTxD
ch0
TI01
TO01
TOOL0
TAU0 (8ch)
TO01/TI00
TO00
OCD
Code
Flash
Data
Flash
7
P00 to P05, P07
PORT1
7
P10 to P15, P17
PORT2
5
P20 to P23, P27
PORT3
4
P30 to P33
PORT4
BCD
Adjustment
Multiplier &
Divider,
Multiply
Accumulator
TAU1 (8ch)
PORT0
P40
PORT5
4
P54 to P57
PORT6
2
P60, P61
PORT7
6
P70 to P75
PORT8
8
P80 to P87
TI10
TO10
ch0
TI11
TO11
ch1
PORT9
5
P90 to P94
TI12
TO12
ch2
PORT12
4
P121 to P124
TI13
TO13
ch3
TI14
TO14
ch4
TI15
TO15
ch5
RTC1HZ/TI16
TO16
ch6
RTC1HZ/TI17
TO17
ch7
INT61
PORT13
P137
PCL/BUZ
PCL
DMA
2 ch
RL78
CPU Core
RAM
TAU2 (8ch)
TO21/TI20
TO20
ch0
TI21
TO21
ch1
TI22
TO22
ch2
TI23
TO23
ch3
RESET
Main OSC
(2 to 20 MHz)
Clock Control
ch4
X1 X2/EXCLK
&
TI25
TO25
ch5
PLL
4 MHz: x6, x8
8 MHz: x3, x4
Reset Control
Interrupt
Control
6
INTP0 to INTP5
2
INTPLR0,1
Window
Watchdog
Timer
ch6
TI27
TO27
SubOSC
32.768 kHz
ch7
CRC
RTC
XT1
SAU0
SCK00
SI00
SO00
CSI00
SCK01
SI01
SO01
CSI01
POR/LVD
Low Speed
OCO
15 kHz
High Speed
OCO
4/8/16/24/32 MHz
XT2
Voltage
Regulator
Interval
timer
REGC
3
ANI2, ANI3, ANI7
ANI0/AVREFP
ANI1/AVREFM
ADTRG
4
SM11 to SM14
10bit A/D
Converter
SAU1
IIC11
SCL11
SDA11
LRxD0
LTxD0
LRxD1
LTxD1
SEG0 to SEG9, SEG14 to SEG19,
SEG21, SEG23 to SEG44
COM0 to COM3
VLC0 to VLC2
Note
UARTF0
UARTF1
LCD
Controller/Driver
Note: No PAD
R01UH0317EJ0110 Rev. 1.10
Mar 23. 2015
VDD,
EVDD
VSS,
EVSS
Stepper
Motor
Controller/
Driver
Zero Point
Detector
Sound
Generator
4
SM21 to SM24
4
ZPD14, 24
SMVDD
SMVSS
SGOA
SGO/SGOF
16
RL78/D1A
CHAPTER 1 OUTLINE
1.6.4 64-pin products (R5F10DLDxFB, R5F10DLExFB: with CAN)
ch1
TI02
TO02
ch2
TI03
TO03
ch3
TI04
TO04
ch4
FSUB/FIL/TI05
TO05
ch5
RTC1HZ
ch6
RTC1HZ/TI07
TO07
ch7
OCD
Code
Flash
Data
Flash
ch0
TI11
TO11
ch1
TI12
TO12
ch2
TI13
TO13
ch3
CAN0 TSOUT/TI14
TO14
ch4
TI15
TO15
ch5
RTC1HZ/TI16
TO16
ch6
RTC1HZ/TI17
TO17
ch7
BCD
Adjustment
INT61
ch0
TI21
TO21
ch1
TI22
TO22
ch2
TI23
TO23
ch3
Main OSC
(2 to 20 MHz)
Clock Control
SubOSC
32.768 kHz
SAU0
7
P10 to P15, P17
PORT2
5
P20 to P23, P27
PORT3
4
P30 to P33
P40
PORT5
4
P54 to P57
PORT6
2
P60,P61
PORT7
6
P70 to P75
PORT8
8
P80 to P87
PORT9
5
P90 to P94
PORT12
4
P121 to P124
PORT13
P137
PCL/BUZ
PCL
Interrupt
Control
6
INTP0 to INTP5
2
INTPLR0,1
Window
Watchdog
Timer
CRC
RTC
CSI00
XT1
POR/LVD
CSI01
Low Speed
OCO
15 kHz
High Speed
OCO
4/8/16/24/32 MHz
XT2
Voltage
Regulator
Interval
timer
REGC
SAU1
IIC11
SCL11
SDA11
SEG0 to SEG9, SEG14 to SEG19,
SEG21, SEG23 to SEG44
COM0 to COM3
VLC0 to VLC2
Note
PLL
4 MHz: x6, x8
8 MHz: x3, x4
Reset Control
ch7
SCK01
SI01
SO01
LRxD0
LTxD0
LRxD1
LTxD1
CRxD0
CTxD0
X1 X2/EXCLK
&
ch6
SCK00
SI00
SO00
PORT1
RESET
ch5
TI27
TO27
P00 to P05, P07
RAM
ch4
TI25
TO25
7
DMA
2 ch
RL78
CPU Core
TAU2 (8ch)
TO21/TI20
TO20
PORT0
PORT4
Multiplier &
Divider,
Multiply
Accumulator
TAU1 (8ch)
TI10
TO10
TOOLRxD
TI01
TO01
TOOLTxD
ch0
TOOL0
TAU0 (8ch)
TO01/TI00
TO00
3
ANI2, ANI3, ANI7
ANI0/AVREFP
ANI1/AVREFM
ADTRG
4
SM11 to SM14
4
SM21 to SM24
4
ZPD14, 24
10bit A/D
Converter
UARTF0
UARTF1
FCAN0
LCD
Controller/Driver
Note: No PAD
R01UH0317EJ0110 Rev. 1.10
Mar 23. 2015
VDD,
EVDD
VSS,
EVSS
Stepper
Motor
Controller/
Driver
Zero Point
Detector
Sound
Generator
SMVDD
SMVSS
SGOA
SGO/SGOF
17
RL78/D1A
CHAPTER 1 OUTLINE
1.6.5 80-pin products (R5F10CMDxFB, R5F10CMExFB: with no CAN)
ch1
TI02
TO02
ch2
TI03
TO03
ch3
TI04
TO04
ch4
FSUB/FIL/TI05
TO05
ch5
RTC1HZ/TI06
TO06
ch6
RTC1HZ/TI07
TO07
ch7
OCD
Code
Flash
Data
Flash
ch0
TI11
TO11
ch1
TI12
TO12
ch2
TI13
TO13
ch3
TI14
TO14
ch4
TI15
TO15
ch5
RTC1HZ/TI16
TO16
ch6
RTC1HZ/TI17
TO17
ch7
BCD
Adjustment
INT61
RL78
CPU Core
ch0
TI21
TO21
ch1
TI22
TO22
ch2
TI23
TO23
ch3
PORT1
8
P10 to P17
PORT2
8
P20 to P27
PORT3
8
P30 to P37
ch4
TI25
TO25
ch5
&
TI26
TO26
ch6
TI27
TO27
ch7
PORT5
4
P54 to P57
PORT6
4
P60, P61, P65 to P66
PORT7
6
P70 to P75
PORT8
8
P80 to P87
PORT9
8
P90 to P97
PORT12
4
P121 to P124
PORT13
P137
PCL/BUZ
PCL
Main OSC
(2 to 20 MHz)
X1 X2/EXCLK
Reset Control
PLL
4 MHz: x6, x8
8 MHz: x3, x4
SubOSC
32.768 kHz
SAU0
Interrupt
Control
LRxD0
LTxD0
LRxD1
LTxD1
POR/LVD
CSI01
Low Speed
OCO
15 kHz
IIC11
SEG0 to SEG47
LCD
COM0 to COM3
Controller/Driver
VLC0 to VLC2
Note Note: No PAD
R01UH0317EJ0110 Rev. 1.10
Mar 23. 2015
INTPLR0,1
CRC
High Speed
OCO
4/8/16/24/32 MHz
XT1
XT2
Voltage
Regulator
Interval
timer
6
10bit A/D
Converter
SAU1
UARTF1
INTP0 to INTP5
RTC
CSI00
UARTF0
6
2
Window
Watchdog
Timer
REGC
SCL11
SDA11
P40
RESET
Clock Control
SCK01
SI01
SO01
P00 to P07
RAM
TI24
TO24
SCK00
SI00
SO00
8
DMA
2 ch
TAU0 (8ch)
TO21/TI20
TO20
PORT0
PORT4
Multiplier &
Divider,
Multiply
Accumulator
TAU1 (8ch)
TI10
TO10
TOOLRxD
TI01
TO01
TOOLTxD
ch0
TOOL0
TAU0 (8ch)
TO01/TI00
TO00
VDD,
EVDD
VSS,
EVSS
Stepper
Motor
Controller/
Driver
Zero Point
Detector
Sound
Generator
ANI2 to ANI7
ANI0/AVREFP
ANI1/AVREFM
ADTRG
4
SM11 to SM14
4
SM21 to SM24
4
SM31 to SM34
4
SM41 to SM44
ZPD14, 24, 34, 44
SMVDD0, SMVDD1
SMVSS0, SMVSS1
4
SGOA
SGO/SGOF
18
RL78/D1A
CHAPTER 1 OUTLINE
1.6.6 80-pin products (R5F10DMDxFB, R5F10DMExFB, R5F10DMFxFB, R5F10DMGxFB, R5F10DMJxFB: with CAN)
ch1
TI02
TO02
ch2
TI03
TO03
ch3
TI04
TO04
ch4
FSUB/FIL/TI05
TO05
ch5
RTC1HZ/TI06
TO06
ch6
RTC1HZ/TI07
TO07
ch7
OCD
Code
Flash
Data
Flash
ch0
TI11
TO11
ch1
TI12
TO12
ch2
TI13
TO13
ch3
CAN0 TSOUT/TI14
TO14
ch4
TI15
TO15
ch5
RTC1HZ/TI16
TO16
ch6
RTC1HZ/TI17
TO17
ch7
BCD
Adjustment
INT61
RL78
CPU Core
ch0
TI21
TO21
ch1
TI22
TO22
ch2
TI23
TO23
ch3
Main OSC
(2 to 20 MHz)
ch4
TI25
TO25
ch5
&
TI26
TO26
ch6
Reset Control
TI27
TO27
ch7
LRxD0
LTxD0
LRxD1
LTxD1
CRxD0
CTxD0
X1 X2/EXCLK
PLL
4 MHz: x6, x8
8 MHz: x3, x4
SubOSC
32.768 kHz
SAU0
8
P10 to P17
PORT2
8
P20 to P27
PORT3
8
P30 to P37
POR/LVD
CSI01
Low Speed
OCO
15 kHz
PORT5
4
P54 to P57
PORT6
4
P60, P61, P65 to P66
PORT7
6
P70 to P75
PORT8
8
P80 to P87
PORT9
8
P90 to P97
PORT12
4
P121 to P124
PORT13
P137
PCL/BUZ
PCL
Interrupt
Control
R01UH0317EJ0110 Rev. 1.10
Mar 23. 2015
INTPLR0,1
High Speed
OCO
4/8/16/24/32 MHz
XT1
XT2
Voltage
Regulator
Interval
timer
6
10bit A/D
Converter
UARTF1
LCD
COM0 to COM3
Controller/Driver
VLC0 to VLC2
Note Note: No PAD
INTP0 to INTP5
CRC
UARTF0
SEG0 to SEG47
6
2
Window
Watchdog
Timer
REGC
IIC11
FCAN0
P40
RTC
CSI00
SAU1
SCL11
SDA11
PORT1
RESET
Clock Control
SCK01
SI01
SO01
P00 to P07
RAM
TI24
TO24
SCK00
SI00
SO00
8
DMA
2 ch
TAU0 (8ch)
TO21/TI20
TO20
PORT0
PORT4
Multiplier &
Divider,
Multiply
Accumulator
TAU1 (8ch)
TI10
TO10
TOOLRxD
TI01
TO01
TOOLTxD
ch0
TOOL0
TAU0 (8ch)
TO01/TI00
TO00
VDD,
EVDD
VSS,
EVSS
Stepper
Motor
Controller/
Driver
Zero Point
Detector
Sound
Generator
ANI2 to ANI7
ANI0/AVREFP
ANI1/AVREFM
ADTRG
4
SM11 to SM14
4
SM21 to SM24
4
SM31 to SM34
4
SM41 to SM44
ZPD14, 24, 34, 44
SMVDD0, SMVDD1
SMVSS0, SMVSS1
4
SGOA
SGO/SGOF
19
RL78/D1A
CHAPTER 1 OUTLINE
1.6.7 100-pin products (R5F10DPExFB, R5F10DPFxFB, R5F10DPGxFB, R5F10TPJxFB: with 1 ch of CAN))
ch1
TI02
TO02
ch2
TI03
TO03
ch3
TI04
TO04
ch4
FSUB/FIL/TI05
TO05
ch5
RTC1HZ/TI06
TO06
ch6
RTC1HZ/TI07
TO07
ch7
OCD
Code
Flash
Data
Flash
ch0
TI11
TO11
ch1
TI12
TO12
ch2
TI13
TO13
ch3
CAN0 TSOUT/TI14
TO14
TI15
TO15
ch4
RTC1HZ/TI16
TO16
ch6
RTC1HZ/TI17
TO17
ch7
BCD
Adjustment
INT61
ch5
RL78
CPU Core
DMA
4ch
ch0
TI21
TO21
ch1
TI22
TO22
ch2
TI23
TO23
ch3
ch4
Clock Control
TI25
TO25
ch5
&
TI26
TO26
ch6
TI27
TO27
ch7
SCK01
SI01
SO01
SCK10
SI10
SO10
SCL11
SDA11
LRxD0
LTxD0
LRxD1
LTxD1
CRxD0
CTxD0
SEG0 to SEG52
COM0 to COM3
VLC0 to VLC2
Note
P00 to P07
PORT1
8
P10 to P17
PORT2
8
P20 to P27
PORT3
8
P30 to P37
P40
PORT5
8
P50 to P57
PORT6
7
P60 to P66
PORT7
6
P70 to P75
PORT8
8
P80 to P87
PORT9
8
P90 to P97
PORT12
4
P121 to P124
PORT13
6
P130
P131 to P136
P137
PORT14
P140
PORT15
P150
PCL/BUZ
PCL
RESET
TI24
TO24
SCK00
SI00
SO00
8
RAM
TAU0 (8ch)
TO21/TI20
TO20
PORT0
PORT4
Multiplier &
Divider,
Multiply
Accumulator
TAU1 (8ch)
TI10
TO10
TOOLRxD
TI01
TO01
TOOLTxD
ch0
TOOL0
TAU0 (8ch)
TO01/TI00
TO00
Main OSC
(2 to 20MHz)
X1 X2/EXCLK
PLL
4MHz: x6, x8
8MHz: x3, x4
Reset Control
SubOSC
32.768 kHz
SAU0
Interrupt
Control
6
INTP0 to INTP5
2
INTPLR0,1
Window
Watchdog
Timer
CRC
RTC
CSI00
POR/LVD
CSI01
Low Speed
OCO
15 kHz
High Speed
OCO
4/8/16/24/32 MHz
XT1
XT2
Voltage
Regulator
Interval
timer
REGC
SAU1
7
ANI2 to ANI8
ANI0/AVREFP
ANI1/AVREFM
ADTRG
4
SM11 to SM14
4
SM21 to SM24
4
SM31 to SM34
4
SM41 to SM44
ZPD14, 24, 34, 44
SMVDD0, SMVDD1
SMVSS0, SMVSS1
10bit A/D
Converter
CSI10
IIC11
UARTF0
UARTF1
FCAN0
LCD
Controller/Driver
VDD,
EVDD0,
EVDD1
VSS,
EVSS0,
EVSS1
Stepper
Motor
Controller/
Driver
Zero Point
Detector
Sound
Generator
4
SGOA
SGO/SGOF
Note: No PAD
R01UH0317EJ0110 Rev. 1.10
Mar 23. 2015
20
RL78/D1A
CHAPTER 1 OUTLINE
1.6.8 100-pin products (R5F10DPJxFB, R5F10DPKxFB, R5F10DPLxFB: with 2 ch of CAN)
ch1
TI02
TO02
ch2
TI03
TO03
ch3
TI04
TO04
ch4
FSUB/FIL/TI05
TO05
ch5
RTC1HZ/TI06
TO06
ch6
RTC1HZ/TI07
TO07
ch7
OCD
Code
Flash
Data
Flash
ch0
TI11
TO11
ch1
TI12
TO12
ch2
TI13
TO13
ch3
CAN0 TSOUT/TI14
TO14
CAN1 TSOUT/TI15
TO15
ch4
RTC1HZ/TI16
TO16
ch6
RTC1HZ/TI17
TO17
ch7
BCD
Adjustment
INT61
ch5
RL78
CPU Core
DMA
4ch
ch0
TI21
TO21
ch1
TI22
TO22
ch2
TI23
TO23
ch3
ch4
Clock Control
TI25
TO25
ch5
&
TI26
TO26
ch6
TI27
TO27
ch7
SCK01
SI01
SO01
SCK10
SI10
SO10
SCL11
SDA11
LRxD0
LTxD0
LRxD1
LTxD1
CRxD0
CTxD0
CRxD1
CTxD1
SEG0 to SEG52
COM0 to COM3
VLC0 to VLC2
Note
P00 to P07
PORT1
8
P10 to P17
PORT2
8
P20 to P27
PORT3
8
P30 to P37
P40
PORT5
8
P50 to P57
PORT6
7
P60 to P66
PORT7
6
P70 to P75
PORT8
8
P80 to P87
PORT9
8
P90 to P97
PORT12
4
P121 to P124
PORT13
6
P130
P131 to P136
P137
PORT14
P140
PORT15
P150
PCL/BUZ
PCL
RESET
TI24
TO24
SCK00
SI00
SO00
8
RAM
TAU0 (8ch)
TO21/TI20
TO20
PORT0
PORT4
Multiplier &
Divider,
Multiply
Accumulator
TAU1 (8ch)
TI10
TO10
TOOLRxD
TI01
TO01
TOOLTxD
ch0
TOOL0
TAU0 (8ch)
TO01/TI00
TO00
Main OSC
(2 to 20MHz)
X1 X2/EXCLK
Reset Control
PLL
4MHz: x6, x8
8MHz: x3, x4
SubOSC
32.768 kHz
SAU0
Interrupt
Control
6
INTP0 to INTP5
2
INTPLR0,1
Window
Watchdog
Timer
CRC
RTC
CSI00
POR/LVD
CSI01
Low Speed
OCO
15 kHz
High Speed
OCO
4/8/16/24/32 MHz
XT1
XT2
Voltage
Regulator
Interval
timer
REGC
SAU1
7
ANI2 to ANI8
ANI0/AVREFP
ANI1/AVREFM
ADTRG
4
SM11 to SM14
4
SM21 to SM24
4
SM31 to SM34
4
SM41 to SM44
ZPD14, 24, 34, 44
SMVDD0, SMVDD1
SMVSS0, SMVSS1
10bit A/D
Converter
CSI10
IIC11
UARTF0
UARTF1
FCAN0
FCAN1
LCD
Controller/Driver
VDD,
EVDD0,
EVDD1
VSS,
EVSS0,
EVSS1
Stepper
Motor
Controller/
Driver
Zero Point
Detector
Sound
Generator
4
SGOA
SGO/SGOF
Note: No PAD
R01UH0317EJ0110 Rev. 1.10
Mar 23. 2015
21
RL78/D1A
CHAPTER 1 OUTLINE
1.6.9 128-pin products (R5F10DSJxFB, R5F10DSKxFB, R5F10DSLxFB)
ch1
TI02
TO02
ch2
TI03
TO03
ch3
TI04
TO04
ch4
TI05
TO05
ch5
TI06
TO06
ch6
TI07
TO07
ch7
OCD
Code
Flash
Data
Flash
BCD
Adjustment
Multiplier &
Divider,
Multiply
Accumulator
TAU1 (8ch)
TI10
TO10
ch0
TI11
TO11
ch1
TI12
TO12
ch2
TI13
TO13
ch3
TI14
TO14
TI15
TO15
ch4
INT61
ch6
TI17
TO17
ch7
RL78
CPU Core
DMA
4ch
TI21
TO21
ch1
TI22
TO22
ch2
RESET
TI23
TO23
ch3
TI24
TO24
Main OSC
(2 to 20MHz)
ch4
ch6
TI27
TO27
ch7
SCK10
SI10
SO10
SCL11
SDA11
LRxD0
LTxD0
LRxD1
LTxD1
CRxD0
CTxD0
CRxD1
CTxD1
SEG0 to SEG53
COM0 to COM3
P10 to P17
PORT2
8
P20 to P27
PORT3
8
P30 to P37
PORT4
8
P40 to P47
PORT5
8
P50 to P57
PORT6
7
P60 to P66
PORT7
6
P70 to P75
PORT8
8
P80 to P87
PORT9
8
P90 to P97
PORT10
8
P100 to P107
PORT11
8
P110 to P117
4
P121 to P124
3
P125 to P127
P130
P131 to P136
P137
6
&
SubOSC
32.768 kHz
Low Speed
OCO
15 kHz
P150 to P152
3
DBWR
DBRD
LCD Bus
I/F
PLL
4MHz: x6, x8
8MHz: x3, x4
Reset Control
POR/LVD
P140
8
DBD0 to DBD7
PCL/BUZ
SAU0
UART0
CSI00
8
PCL
X1 X2/EXCLK
High Speed
OCO
4/8/16/24/32 MHz
XT1
Interrupt
Control
6
INTP0 to INTP5
2
INTPLR0,1
Window
Watchdog
Timer
XT2
Voltage
Regulator
CRC
RTC
CSI01
RTC1HZ
REGC
Interval
timer
SAU1
CSI10
8
10bit A/D
Converter
IIC11
UARTF0
UARTF1
FCAN0
FCAN1
LCD
Controller/Driver
R01UH0317EJ0110 Rev. 1.10
Mar 23. 2015
VDD,
EVDD0,
EVDD1
VSS,
EVSS0,
EVSS1
RESOUT/P130
SCK01
SI01
SO01
Clock Control
STOPST/P41
RxD0
TxD0
SCK00
SI00
SO00
PORT1
PORT15
ch0
TI26
TO26
P00 to P07
PORT14
RAM
TAU0 (8ch)
ch5
8
PORT13
TI20
TO20
TI25
TO25
PORT0
PORT12
ch5
TI16
TO16
TOOLRxD
TI01
TO01
TOOLTxD
ch0
TOOL0
TAU0 (8ch)
TI00
TO00
Stepper
Motor
Controller/
Driver
Zero Point
Detector
Sound
Generator
ANI2 to ANI10
ANI0/AVREFP
ANI1/AVREFM
ADTRG
4
SM11 to SM14
4
SM21 to SM24
4
SM31 to SM34
4
SM41 to SM44
ZPD14, 24, 34, 44
SMVDD0, SMVDD1
SMVSS0, SMVSS1
4
SGOA
SGO/SGOF
22
RL78/D1A
CHAPTER 1 OUTLINE
1.7 Outline of Functions
(1/4)
ROM/
512 KB
24 KB
RAM
384 KB
20 KB
256 KB
16 KB
128 KB
8 KB
96 KB
6 KB
64 KB
4 KB
48 KB
3 KB
32 KB
2 KB
24 KB
2 KB
R5F10DMJxFB
R5F10DMGxFB
R5F10DMFxFB
R5F10DMExFB
8 KB
Memory space
1 MB
General-purpose register
8 bits 32 registers (8 bits 8 registers 4 banks)
Main
System
clock
High-speed system
clock
1 to 20 MHz (VDD = 2.7 V to 5.5 V)
High-speed on-chip
oscillation clock
4/8/16/24/32 MHz (TA = -40 to 85C)
4/8/16/24 MHz (TA = -40 to 105C)
4 MHz 16/2 = 32 MHz, 8 MHz 16/4 = 32 MHz (TA= -40 to 85C)
4 MHz 12/2 = 24 MHz, 8 MHz 12/4 = 24 MHz (TA= -40 to 105C)
PLL
Subsystem clock
32.768kHz
Low-speed on-chip oscillation clock
15 kHz
Minimum instruction execution time
0.03125 s (Main system clock 32 MHz TA = -40 to +85C)
0.04167 s (Main system clock 24 MHz TA = -40 to 105C)
30.5 s (Subsystem clock 32.768 kHz operation)
Instruction set
8-bit operation,16-bit operation
Multiplication (8 bits 8 bits)
Bit manipulation (Set, reset, test, and Boolean operation), etc.
Total number of port
38
54
68
CMOS I/O port
35
49
63
N-ch open-drain
Selectable port
LED direct drive port
CMOS input port
4
9
13
16
3
5
CMOS output port
Timer
R5F10DMDxFB
Data flash memory
I/O port
R5F10CMExFB
R5F10CMDxFB
80-pin
R5F10DLExFB
R5F10DLDxFB
R5F10CLDxFB
R5F10DGExFB
R5F10DGDxFB
R5F10DGCxFB
R5F10CGDxFB
RAM
R5F10CGCxFB
ROM
capacities
64-pin
48-pin
R5F10CGBxFB
Item
0
8 ch 3 units
16-bit timer
Real-time clock (RTC)
1 ch
Interval timer
1 ch
Watchdog timer (WDT)
1 ch
Timer output
19
21
RTC output
Clock output/buzzer output
10-bit resolution A/D converter
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1
1
3+2
6+2
23
RL78/D1A
CHAPTER 1 OUTLINE
(2/4)
Serial
CSI
2 ch
interface
UART
－
Simplified IIC
1 ch
LIN-UART
aFCAN
Multiplier and divider/multiply accumulator
1 ch
0 ch
R5F10DMJxFB
R5F10DMGxFB
R5F10DMFxFB
R5F10DMExFB
R5F10DMDxFB
R5F10CMExFB
R5F10CMDxFB
80-pin
R5F10DLExFB
R5F10CLDxFB
R5F10DGExFB
R5F10DGDxFB
R5F10DGCxFB
R5F10CGDxFB
R5F10CGCxFB
R5F10DLDxFB
64-pin
48-pin
R5F10CGBxFB
Item
2 ch
1 ch
0 ch
1 ch
0 ch
1 ch
16-bits 16 bits = 32 bits (Unsigned or signed)
32-bits 32 bits = 32 bits (Unsigned)
16-bits 16 bits + 32 bits = 32 bits (Unsigned or signed)
DMA controller
Vectored
Internal
interrupt
External
sources
39
43
42
46
Debugger
1
Bias
SEG COM
Static, 1/3 bias, 1/3 or 1/4 duty
27 4
39 4
Sound generator
Stepper motor controller/driver (with ZPD)
Safety
FLASH memory
function
CRC calculation
46
8
1
controller
42
6
Software
LCD
driver
2 ch
48 4
1 channel
1 ch
2 ch
4 ch
Provided
RAM parity bit error
Provided
detection
IIlegal-memory
Provided
access detection
Frequency detection
Provided
Clock monitor
Reset
Provided
____________
Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
Internal reset by illegal instruction execution
Internal reset by RAM parity error
Internal reset by illegal-memory access
Internal reset by clock monitor
Power on reset (POR)
Power on reset: 1.51 V 0.06 V
Power down reset: 1.50 V 0.06 V
Voltage detector
Rising edge detection voltage = 2.81 to 4.06 V (6 step)
Falling edge detection voltage = 2.75 to 3.98 V (6 step)
On-chip debug function
Provided
Power supply voltage
VDD = 2.7 to 5.5 V
Operating ambient temperature
J grade products:TA = -40 to +85 °C, L grade products: TA = -40 to +105 °C
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24
RL78/D1A
CHAPTER 1 OUTLINE
(3/4)
100-pin
ROM/
512 KB
24 KB
RAM
384 KB
20 KB
256 KB
16 KB
128 KB
8 KB
96 KB
6 KB
64 KB
4 KB
48 KB
3 KB
32 KB
2 KB
24 KB
2 KB
capacities
R5F10DSLxFB
R5F10DSKxFB
Data flash memory
8 KB
Memory space
1 MB
General-purpose register
8 bits 32 registers (8 bits 8 registers 4 banks)
Main
System
clock
High-speed system clock
1 to 20 MHz (VDD = 2.7 V to 5.5 V)
High-speed on-chip oscillation
clock
4/8/16/24/32 MHz (TA = -40 to 85C)
4/8/16/24 MHz (TA = -40 to 105C)
4 MHz 16/2 = 32 MHz, 8 MHz 16/4 = 32 MHz (TA= -40 to 85C)
4 MHz 12/2 = 24 MHz, 8 MHz 12/4 = 24 MHz (TA= -40 to 105C)
PLL
Subsystem clock
32.768kHz
Low-speed on-chip oscillation clock
15 kHz
Minimum instruction execution time
0.03125 s (Main system clock 32 MHz TA = -40 to +85C)
0.04167 s (Main system clock 24 MHz TA = -40 to 105C)
30.5 s (Subsystem clock 32.768 kHz operation)
Instruction set
8-bit operation,16-bit operation
Multiplication (8 bits 8 bits)
Bit manipulation (Set, reset, test, and Boolean operation), etc.
I/O port Total number of port
CMOS I/O port
Timer
R5F10DSJxFB
R5F10DPLxFB
R5F10DPKxFB
128-pin
R5F10DPJxFB
R5F10TPJxFB
R5F10DPGxFB
RAM
R5F10DPFxFB
ROM
R5F10DPExFB
Item
84
112
78
107
N-ch open-drain Selectable
port
6
LED direct drive port
16
CMOS input port
5
CMOS output port
1
8 ch 3 units
16-bit timer
Real-time clock (RTC)
1 ch
Interval timer
1 ch
Watchdog timer (WDT)
1 ch
Timer output
24
RTC output
1
Clock output/buzzer output
10-bit resolution A/D converter
1
7+2
9+2
Reset output
Can be output from P130
STOP status output
Can be output from P41
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RL78/D1A
CHAPTER 1 OUTLINE
(4/4)
CSI
interface
UART
R5F10DSLxFB
R5F10DSKxFB
R5F10DSJxFB
3 ch
－
1 ch
Simplified IIC
1 ch
LIN-UART
2 ch
aFCAN
R5F10DPLxFB
R5F10DPKxFB
128-pin
R5F10DPJxFB
R5F10DPGxFB
R5F10DPFxFB
R5F10DPExFB
Serial
R5F10TPJxFB
100-pin
Item
1 ch
2 ch
Multiplier and divider/multiply accumulator 16-bits 16 bits = 32 bits (Unsigned or signed)
32-bits 32 bits = 32 bits (Unsigned)
16-bits 16 bits + 32 bits = 32 bits (Unsigned or signed)
DMA controller
4 ch
Vectored interrupt Internal
sources
External
53
Software
1
Debugger
1
LCD controller
Bias
driver
SEG COM
8
Static, 1/3 bias, 1/3 or 1/4 duty
LCD Bus I/F
53 4
54 4
－
Provided (8 bit, RD, WR)
Sound generator
1 channel
Stepper motor controller/driver (with ZPD)
Safety
FLASH memory
function
CRC calculation
4 ch
Provided
RAM parity bit error
Provided
detection
IIlegal-memory
Provided
access detection
Frequency detection
Provided
Clock monitor
Reset
Provided
____________
Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
Internal reset by illegal instruction execution
Internal reset by RAM parity error
Internal reset by illegal-memory access
Internal reset by clock monitor
Power on reset (POR)
Power on reset: 1.51 V 0.06 V
Power down reset: 1.50 V 0.06 V
Voltage detector
Rising edge detection voltage = 2.81 to 4.06 V (6 step)
Falling edge detection voltage = 2.75 to 3.98 V (6 step)
On-chip debug function
Provided
Power supply voltage
VDD = 2.7 to 5.5 V
Operating ambient temperature
J grade products:TA = -40 to +85 °C, L grade products: TA = -40 to +105 °C
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26
RL78/D1A
CHAPTER 2 PIN FUNCTIONS
CHAPTER 2 PIN FUNCTIONS
2.1 Pin Function List
Pin I/O buffer power supplies depend on the product. The relationship between these power supplies and the pins is
shown below.
Table 2-1. Pin I/O Buffer Power Supplies
(1) 48-pin products
Power Supply
Corresponding Pins
VDD/EVDD
Port pins other than P80 to P83 and P90 to P94
SMVDD
P80 to P83, P90 to P94
(2) 64-pin products
Power Supply
Corresponding Pins
VDD/EVDD
Port pins other than P80 to P87and P90 to P94
SMVDD
P80 to P87, P90 to P94
(3) 80-pin products
Power Supply
Corresponding Pins
VDD/EVDD
Port pins other than P80 to P87 and P90 to P97
SMVDD0, SMVDD1
P80 to P87, P90 to P97
(4) 100-pin products
Power Supply
Corresponding Pins
____________
VDD
P20 to P27, P150, P137, P121 to P124, RESET
EVDD0, EVDD1
P00 to P07, P10 to P17, P30 to P37, P40, P50 to P57,
P60 to P66, P70 to P75, P130 to P136, P140
SMVDD0, SMVDD1
P80 to P87, P90 to P97
(5) 128-pin products
Power Supply
Corresponding Pins
____________
VDD
P20 to P27, P150 to P152, P137, P121 to P124, RESET
EVDD0, EVDD1
P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P66, P70 to P75, P100 to P107,
P110 to P117, P125 to P127, P130 to P136, and P140
SMVDD0, SMVDD1
P80 to P87, P90 to P97
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RL78/D1A
CHAPTER 2 PIN FUNCTIONS
The setting of I/O, buffer and pull-up resistor in each port is also valid for alternate functions.
2.1.1 48-pin products
Table 2-2. Port Pins for
R5F10CGBxFB, R5F10CGCxFB, R5F10CGDxFB, R5F10DGCxFB, R5F10DGDxFB, R5F10DGExFB (1/2)
Pin Name
P00
I/O
I/O
P01
Function
During
Reset
After
Reset
Alternate Function
Note1
Port 0. 2-bit I/O port.
Ext.: PD Input
TI00/TO00/CTxD0/SEG14
Input of P01 can be set to schmitt 1
input buffer.
Int.: HZ
TI01/TO01/CRxD0/SEG15
Note1
Input/output can be specified in 1-bit
units.
Use of an on-chip pull-up resistor can
be specified by a software setting.
P10
I/O
P11
P12
Port 1. 5-bit I/O port.
Ext.: PD Input
LTxD1/SCK00/TI10/TO10/INTP4/SEG31
Input of P10 and P11 can be set to
schmitt 1 input buffer.
Int.: HZ
LRxD1/INTPLR1/SI00/TI11/TO11/SEG30
SO00/TI12/TO12/INTP2/SEG29
Input/output can be specified in 1-bit
units.
P13
P14
SO01/TI13/TO13/SEG25
TI14/TO14/SEG24
Use of an on-chip pull-up resistor can
be specified by a software setting.
P20
I/O
Port 2. 5-bit I/O port.
HZ
Note2
P21
Can be set to analog input
P22
Input/output can be specified in 1-bit
units.
P23
Analog
Input
AVREFP/ANI0
AVREFM/ANI1
ANI2
ANI3
P27
ANI7
P30
I/O
P31
P33
Port 3. 3-bit I/O port.
Ext.: PD Input
TI20/TO20/SCL11/SEG6
Input of P31 can be set to schmitt 1
input buffer.
Int.: HZ
TI21/TO21/SDA11/SEG7
TI23/TO23/SEG9
Output of P30 and P31 can be set to Nch open-drain output.
Input/output can be specified in 1-bit
units.
Use of an on-chip pull-up resistor can
be specified by a software setting.
P40
I/O
Port 4. 1-bit I/O port.
Ext.: HZ Input
Input/output can be specified.
Int.: PU
TOOL0
Use of an on-chip pull-up resistor can
be specified by a software setting.
P54
I/O
P55
P56
Port 5. 4-bit I/O port.
Ext.: PD Input
TI14/TO14/SO01/SEG2
Input of P55 to P57 can be set to
schmitt 1 input buffer.
Int.: HZ
TI15/TO15/SI01/SEG3
Input/output can be specified in 1-bit
units.
P57
TI16/TO16/SCK01/SEG4
TI17/TO17/SEG5
Use of an on-chip pull-up resistor can
be specified by a software setting.
Remark
Ext. (external reset): POR reset or pin reset, Int. (internal reset): WDT reset or LVD reset,
PD: Pull down, PU: Pull up, HZ: High impedance
Notes 1. CTxD0 and CRxD0 are not provided for R5F10CGDxFB, R5F10CGCxFB and R5F10CGBxFB with no CAN
channel.
2. Setting digital or analog to each pin can be done in A/D port configuration register (ADPC).
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RL78/D1A
CHAPTER 2 PIN FUNCTIONS
Table 2-2. Port Pins for
R5F10CGBxFB, R5F10CGCxFB, R5F10CGDxFB, R5F10DGCxFB, R5F10DGDxFB, R5F10DGExFB (2/2)
Pin Name
P60
I/O
I/O
Function
Port 6. 2-bit I/O port.
During
After
Reset
Reset
HZ
Input
Input of P61 can be set to schmitt 1
input buffer.
P61
Alternate Function
SCL11/TI20/TO20/INTP1
SDA11/TI21/TO21/INTP3
Output of P60 and P61 can be set to
N-ch open-drain output.
Input/output can be specified in 1-bit
units.
Use of an on-chip pull-up resistor can
be specified by a software setting.
P72
I/O
P73
Input/output can be specified in 1-bit
Int.: HZ
SGO/SGOF/SEG0
SCK01/TI23/TO23/SEG26
PCL/SI01/TI22/TO22/SEG27
be specified by a software setting.
I/O
P81
Port 8. 4-bit I/O port.
Ext.: PD Input
SM11/TI01/TO01/SEG32
Input/output can be specified in 1-bit
Int.: HZ
SM12/TI03/TO03/SEG33
units.
P82
SM13/TI05/TO05/SEG34
Use of an on-chip pull-up resistor can
P83
SM14/ZPD14/TI07/TO07/SEG35
be specified by a software setting.
I/O
P91
Port 9. 5-bit I/O port.
Ext.: PD Input
TI21/TO21/SEG40
Input/output can be specified in
Int.: HZ
TI23/TO23/SEG41
1-bit units.
P92
TI25/TO25/SGOA/SEG42
Use of an on-chip pull-up resistor can
P93
TI27/TO27/SGO/SGOF/SEG43
be specified by a software setting.
P94
P121
ADTRG/SGOA/SEG1
Use of an on-chip pull-up resistor can
P75
P90
Ext.: PD Input
units.
P74
P80
Port 7. 4-bit I/O port.
I
Port 12. 2-bit Input port.
TI01/TO01/RTC1HZ/SEG44
HZ
Input
P122
P137
X1
X2/EXCLK
I
Port 13. 1-bit Input port.
HZ
Input
INTP5
Remark Ext. (external reset): POR reset or pin reset, Int. (internal reset): WDT reset or LVD reset,
PD: Pull down, HZ: High impedance
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RL78/D1A
CHAPTER 2 PIN FUNCTIONS
2.1.2 64-pin products
Table 2-3. Port Pins for R5F10CLDxFB, R5F10DLDxFB, R5F10DLExFB (1/2)
Pin Name
P00
I/O
I/O
P01
P02
Function
During
Reset
After
Reset
P04
Ext.: PD Input
TI00/TO00/CTxD0/SEG14
Input of P01 can be set to schmitt 1
input buffer.
Int.: HZ
TI01/TO01/CRxD0/SEG15
Note1
SO00/TI02/TO02/TI12/TO12/SEG16
SI00/TI03/TO03/TI13/TO13/SEG17
SCK00/TI04/TO04/TI14/TO14/SEG18
Use of an on-chip pull-up resistor can
be specified by a software setting.
P05
Note1
Port 0. 7-bit I/O port.
Input/output can be specified in 1-bit
units.
P03
Alternate Function
TI05/TO05/TI15/TO15/SEG19
P07
TI07/TO07/TI17/TO17/SEG21
P10
I/O
P11
P12
Port 1. 7-bit I/O port.
Ext.: PD Input
LTxD1/SCK00/TI10/TO10/INTP4/SEG31
Input of P10, P11, and P17 can be set
to schmitt 1 input buffer.
Int.: HZ
LRxD1/INTPLR1/SI00/TI11/TO11/SEG30
SO00/TI12/TO12/INTP2/SEG29
Input/output can be specified in 1-bit
units.
P13
P14
SO01/TI13/TO13/SEG25
TI14/TO14/LRxD0/INTPLR0/SEG24
Use of an on-chip pull-up resistor can
be specified by a software setting.
P15
TI15/TO15/LTxD0/RTC1HZ/SEG23
P17
TI17/TO17/INTP0/SEG28
P20
I/O
HZ
Port 2. 5-bit I/O port.
Note2
P21
Can be set to analog input
P22
Input/output can be specified in 1-bit
units.
P23
Analog
Input
AVREFP/ANI0
AVREFM/ANI1
ANI2
ANI3
P27
ANI7
P30
I/O
P31
P32
Port 3. 4-bit I/O port.
Ext.: PD Input
TI20/TO20/SCL11/SEG6
Input of P31 can be set to schmitt 1
input buffer.
Int.: HZ
TI21/TO21/SDA11/SEG7
TI22/TO22/SEG8
Output of P30 and P31 can be set to Nch open-drain output.
P33
TI23/TO23/SEG9
Input/output can be specified in 1-bit
units.
Use of an on-chip pull-up resistor can
be specified by a software setting.
P40
I/O
Port 4. 1-bit I/O port.
Ext.: HZ Input
Input/output can be specified.
Int.: PU
TOOL0
Use of an on-chip pull-up resistor can
be specified by a software setting.
P54
I/O
P55
P56
Port 5. 4-bit I/O port.
Ext.: PD Input
TI14/TO14/SO01/SEG2
Input of P55 to P57 can be set to
schmitt 1 input buffer.
Int.: HZ
TI15/TO15/SI01/SEG3
Input/output can be specified in 1-bit
units.
P57
TI16/TO16/SCK01/SEG4
TI17/TO17/SEG5
Use of an on-chip pull-up resistor can
be specified by a software setting.
Remark
Ext. (external reset): POR reset or pin reset, Int. (internal reset): WDT reset or LVD reset,
PD: Pull down, PU: Pull up, HZ: High impedance
Notes 1. CTxD0 and CRxD0 are not provided for R5F10CLDxFB with no CAN channel.
2. Setting digital or analog to each pin can be done in A/D port configuration register (ADPC).
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RL78/D1A
CHAPTER 2 PIN FUNCTIONS
Table 2-3. Port Pins for R5F10CLDxFB, R5F10DLDxFB, R5F10DLExFB (2/2)
Pin Name
I/O
P60
Function
During
After
Reset
Reset
HZ
I/O Port 6. 2-bit I/O port.
Input of P61 can be set to schmitt 1
input buffer.
P61
Input
Alternate Function
SCL11/TI20/TO20/INTP1
SDA11/TI21/TO21/INTP3
Output of P60 and P61 can be set
to
N-ch open-drain output.
Input/output can be specified in 1bit units.
Use of an on-chip pull-up resistor
can be specified by a software
setting.
P70
I/O
Port 7. 6-bit I/O port.
HZ
Input
Input of P70 can be set to schmitt 1
P71
input buffer.
P72
Input/output can be specified in 1-
P73
bit units.
P74
CTxD0/LTxD0/TOOLTXD
Ext.: PD
ADTRG/SGOA/SEG1
Int.: HZ
SGO/SGOF/SEG0
Note
Note
SCK01/TI23/TO23/SEG26
Use of an on-chip pull-up resistor
P75
CRxD0/LRxD0/INTPLR0/TI03/TO03/TOOLRXD
PCL/SI01/TI22/TO22/SEG27
can be specified by a software
setting.
P80
I/O
P81
Port 8. 8-bit I/O port.
Ext.: PD Input
SM11/TI01/TO01/SEG32
Input/output can be specified in 1-
Int.: HZ
SM12/TI03/TO03/SEG33
bit units.
P82
SM13/TI05/TO05/SEG34
Use of an on-chip pull-up resistor
P83
SM14/ZPD14/TI07/TO07/SEG35
can be specified by a software
P84
SM21/TI11/TO11/SEG36
setting.
P85
SM22/TI13/TO13/SEG37
P86
SM23/TI15/TO15/SEG38
P87
SM24/ZPD24/TI17/TO17/SEG39
P90
I/O
P91
Ext.: PD Input
TI21/TO21/SEG40
Input/output can be specified in
Int.: HZ
TI23/TO23/SEG41
1-bit units.
P92
TI25/TO25/SGOA/SEG42
Use of an on-chip pull-up resistor
P93
TI27/TO27/SGO/SGOF/SEG43
can be specified by a software
P94
P121
Port 9. 5-bit I/O port.
TI01/TO01/RTC1HZ/SEG44
setting.
I
Port 12. 4-bit Input port.
HZ
Input
X1
P122
X2/EXCLK
P123
XT1
P124
P137
Remark
XT2
I
Port 13. 1-bit Input port.
HZ
Input
INTP5
Ext. (external reset): POR reset or pin reset, Int. (internal reset): WDT reset or LVD reset,
PD: Pull down, HZ: High impedance
Note CTxD0 and CRxD0 are not provided for R5F10CLDxFB with no CAN channel.
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2.1.3 80-pin products products
Table 2-4. Port Pins for R5F10CMDxFB, R5F10CMExFB,
R5F10DMDxFB, R5F10DMExFB, R5F10DMFxFB, R5F10DMGxFB, R5F10DMJxFB (1/2)
Pin Name
P00
I/O
I/O
P01
P02
P03
P04
P05
Function
Port 0. 8-bit I/O port.
Input of P01 can be set to schmitt 1
input buffer.
Input/output can be specified in 1-bit
units.
Use of an on-chip pull-up resistor can
be specified by a software setting.
During
After
Reset
Reset
TI00/TO00/CTxD0/SEG14
Int.: HZ
TI01/TO01/CRxD0/SEG15
SI00/TI03/TO03/TI13/TO13/SEG17
SCK00/TI04/TO04/TI14/TO14/SEG18
TI05/TO05/TI15/TO15/SEG19
TI06/TO06/TI16/TO16/SEG20
TI07/TO07/TI17/TO17/SEG21
P10
I/O
P11
P12
P13
P14
P15
Ext.: PD Input
Port 1. 8-bit I/O port.
Input of P10, P11, and P17 can be set Int.: HZ
to schmitt 1 input buffer.
Input/output can be specified in 1-bit
units.
Use of an on-chip pull-up resistor can
be specified by a software setting.
P16
I/O
Note2
P22 to P27
I/O
P31
P32
P33
P34
P35
P36
P37
P57
Remark
HZ
Port 2. 8-bit I/O port.
Can be set to analog input
Input/output can be specified in 1-bit
units.
P21
P56
SO00/TI12/TO12/INTP2/SEG29
SO01/TI13/TO13/SEG25
TI14/TO14/LRxD0/INTPLR0/SEG24
TI15/TO15/LTxD0/RTC1HZ/SEG23
TI17/TO17/INTP0/SEG28
P20
P55
LTxD1/SCK00/TI10/TO10/INTP4/SEG31
LRxD1/INTPLR1/SI00/TI11/TO11/SEG30
TI16/TO16/SEG22
P17
P54
Note1
SO00/TI02/TO02/TI12/TO12/SEG16
P07
P40
Note1
Ext.: PD Input
P06
P30
Alternate Function
I/O
I/O
Analog
Input
AVREFP/ANI0
AVREFM/ANI1
ANI2 to ANI7
Port 3. 8-bit I/O port.
Input of P31 can be set to schmitt 1
input buffer.
Output of P30 and P31 can be set to
N-ch open-drain output.
Input/output can be specified in 1-bit
units.
Use of an on-chip pull-up resistor can
be specified by a software setting.
Ext.: PD Input
TI20/TO20/SCL11/SEG6
Int.: HZ
TI21/TO21/SDA11/SEG7
Port 4. 1-bit I/O port.
Ext.: HZ Input
Input/output can be specified.
Use of an on-chip pull-up resistor can
be specified by a software setting.
Int.: PU
Port 5. 4-bit I/O port.
Input of P55 to P57 can be set to
schmitt 1 input buffer.
Input/output can be specified in 1-bit
units.
Use of an on-chip pull-up resistor can
be specified by a software setting.
Ext.: PD Input
TI14/TO14/SO01/SEG2
Int.: HZ
TI15/TO15/SI01/SEG3
TI22/TO22/SO00/SEG8
TI23/TO23/SI00/SEG9
TI24/TO24/SCK00/SEG10
TI25/TO25/SEG11
TI26/TO26/SEG12
TI27/TO27/SEG13
TOOL0
TI16/TO16/SCK01/SEG4
TI17/TO17/SEG5
Ext. (external reset): POR reset or pin reset, Int. (internal reset): WDT reset or LVD reset,
PD: Pull down, PU: Pull up, HZ: High impedance
Notes 1. CTxD0 and CRxD0 are not provided for R5F10CMExFB and R5F10CMDxFB with no CAN channel.
2. Setting digital or analog to each pin can be done in A/D port configuration register (ADPC).
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Table 2-4. Port Pins for R5F10CMDxFB, R5F10CMExFB,
R5F10DMDxFB, R5F10DMExFB, R5F10DMFxFB, R5F10DMGxFB, R5F10DMJxFB (2/2)
Pin Name
I/O
P60
Function
During
After
Reset
Reset
HZ
I/O Port 6. 4-bit I/O port.
Input of P61 can be set to schmitt 1
input buffer.
P61
P65
Input
SCL11/TI20/TO20/INTP1
SDA11/TI21/TO21/INTP3
TI25/TO25
Output of P60 and P61 can be set
to N-ch open-drain output.
P66
Alternate Function
TI24/TO24/PCL
Input/output can be specified in 1-bit
units.
Use of an on-chip pull-up resistor
can be specified by a software
setting.
P70
I/O
Port 7. 6-bit I/O port.
HZ
Input
Input of P70 can be set to schmitt 1
P71
input buffer.
P72
Input/output can be specified in 1-bit
P73
units.
P74
CTxD0/LTxD0/TOOLTXD
Ext.: PD
ADTRG/SGOA/SEG1
Int.: HZ
SGO/SGOF/SEG0
Note
Note
SCK01/TI23/TO23/SEG26
Use of an on-chip pull-up resistor
P75
CRxD0/LRxD0/INTPLR0/TI03/TO03/TOOLRXD
PCL/SI01/TI22/TO22/SEG27
can be specified by a software
setting.
P80
I/O
Port 8. 8-bit I/O port.
Ext.: PD
Input
Input/output can be specified in 1-bit Int.: HZ
P81
SM12/TI03/TO03/SEG33
units.
P82
SM13/TI05/TO05/SEG34
Use of an on-chip pull-up resistor
P83
SM14/ZPD14/TI07/TO07/SEG35
can be specified by a software
P84
SM11/TI01/TO01/SEG32
SM21/TI11/TO11/SEG36
setting.
P85
SM22/TI13/TO13/SEG37
P86
SM23/TI15/TO15/SEG38
P87
SM24/ZPD24/TI17/TO17/SEG39
P90
I/O
Port 9. 8-bit I/O port.
Ext.: PD
Input
Input/output can be specified in 1-bit Int.: HZ
P91
SM32/TI23/TO23/SEG41
units.
P92
SM33/TI25/TO25/SGOA/SEG42
Use of an on-chip pull-up resistor
P93
SM34/ZPD34/TI27/TO27/SGO/SGOF/SEG43
can be specified by a software
P94
SM31/TI21/TO21/SEG40
SM41/TI01/TO01/RTC1HZ/SEG44
setting.
P95
SM42/TI03/TO03/SEG45
P96
SM43/TI05/TO05/SEG46
P97
SM44/ZPD44/TI07/TO07/SEG47
P121
I
Port 12. 4-bit Input port.
HZ
Input
X1
P122
X2/EXCLK
P123
XT1
P124
XT2
P137
Remark
I
Port 13. 1-bit Input port.
HZ
Input
INTP5
Ext. (external reset): POR reset or pin reset, Int. (internal reset): WDT reset or LVD reset,
PD: Pull down, HZ: High impedance
Note CTxD0 and CRxD0 are not provided for R5F10CMExFB and R5F10CMDxFB with no CAN channel.
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2.1.4 100-pin products
Table 2-5. Port Pins for R5F10DPExFB, R5F10DPFxFB, R5F10DPGxFB, R5F10TPJxFB, R5F10DPJxFB (1/3)
Pin Name
P00
I/O
I/O
P01
P02
P03
P04
P05
Function
During
After
Reset
Reset
Port 0. 8-bit I/O port.
Ext.: PD
Input of P01 can be set to schmitt 1
input buffer.
Int.: HZ
Input
SO00/TI02/TO02/TI12/TO12/SEG16
Input/output can be specified in 1-bit
units.
SI00/TI03/TO03/TI13/TO13/SEG17
Use of an on-chip pull-up resistor can
be specified by a software setting.
TI05/TO05/TI15/TO15/SEG19
SCK00/TI04/TO04/TI14/TO14/SEG18
TI06/TO06/TI16/TO16/SEG20
P07
TI07/TO07/TI17/TO17/SEG21
I/O
Port 1. 8-bit I/O port.
Ext.: PD
Input
Input of P10, P11, and P17 can be set Int.: HZ
to schmitt 1 input buffer.
P11
P12
P13
P14
P15
SO00/TI12/TO12/INTP2/SEG29
Input/output can be specified in 1-bit
units.
SO01/TI13/TO13/SEG25
Use of an on-chip pull-up resistor can
be specified by a software setting.
TI15/TO15/LTxD0/RTC1HZ/SEG23
TI14/TO14/LRxD0/INTPLR0/SEG24
TI16/TO16/SEG22
P17
TI17/TO17/INTP0/SEG28
I/O
HZ
Port 2. 8-bit I/O port.
Note
P21
Can be set to analog input
P22 to P27
Input/output can be specified in 1-bit
units.
P30
I/O
P31
P32
P33
P34
P35
P36
Analog
Input
I/O
AVREFP/ANI0
AVREFM/ANI1
ANI2 to ANI7
Port 3. 8-bit I/O port.
Ext.: PD
Input of P31 can be set to schmitt 1
input buffer.
Int.: HZ
Input
TI20/TO20/SCL11/SEG6
TI21/TO21/SDA11/SEG7
TI22/TO22/SO00/SEG8
Output of P30 and P31 can be set to
N-ch open-drain output.
TI23/TO23/SI00/SEG9
Input/output can be specified in 1-bit
units.
TI25/TO25/SEG11
TI24/TO24/SCK00/SEG10
TI26/TO26/SEG12
Use of an on-chip pull-up resistor can
be specified by a software setting.
P37
P40
LTxD1/SCK00/TI10/TO10/INTP4/SEG31
LRxD1/INTPLR1/SI00/TI11/TO11/SEG30
P16
P20
TI00/TO00/CTxD0/SEG14
TI01/TO01/CRxD0/SEG15
P06
P10
Alternate Function
TI27/TO27/SEG13
Port 4. 1-bit I/O port.
Ext.: HZ
Input/output can be specified.
Int.: PU
Input
TOOL0
Use of an on-chip pull-up resistor can
be specified by a software setting.
P50
P51
P52
P53
P54
P55
P56
P57
Remark
I/O
Port 5. 8-bit I/O port.
Ext.: PD
Input of P50 to P52 and P55 to P57
can be set to schmitt 1 input buffer.
Int.: HZ
Input
TI02/TO02/SDA11/SEG49
TI04/TO04/SCK10/SEG50
TI06/TO06/SI10/SEG51
Output of P50 can be set to N-ch
open-drain output.
TI13/TO13/SO10/SEG52
Input/output can be specified in 1-bit
units.
TI15/TO15/SI01/SEG3
Use of an on-chip pull-up resistor can
be specified by a software setting.
TI14/TO14/SO01/SEG2
TI16/TO16/SCK01/SEG4
TI17/TO17/SEG5
Ext. (external reset): POR reset or pin reset, Int. (internal reset): WDT reset or LVD reset,
PD: Pull down, PU: Pull up, HZ: High impedance
Note Setting digital or analog to each pin can be done in A/D port configuration register (ADPC).
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Table 2-5. Port Pins for R5F10DPExFB, R5F10DPFxFB, R5F10DPGxFB, R5F10TPJxFB, R5F10DPJxFB (2/3)
Pin Name
P60
I/O
I/O
Function
Port 6. 4-bit I/O port.
During
After
Reset
Reset
HZ
Input
Input of P61, P63 can be set to
P61
CTxD1/TI27/TO27
Output of P60 and P61 can be set
P63
P66
Note
RTC1HZ/TI11/TO11
Input/output can be specified in
P65
Note
CRxD1/TI26/TO26
to N-ch open-drain output.
P64
SCL11/TI20/TO20/INTP1
SDA11/TI21/TO21/INTP3
schmitt 1 input buffer.
P62
Alternate Function
1-bit units.
TI25/TO25
Use of an on-chip pull-up resistor
TI24/TO24/PCL
can be specified by a software
setting.
P70
I/O
Port 7. 6-bit I/O port.
HZ
Input
Input of P70 can be set to
P71
schmitt 1 input buffer.
P72
Input/output can be specified in 1-
P73
bit units.
P74
CTxD0/LTxD0/TOOLTXD
Ext.: PD
ADTRG/SGOA/SEG1
Int.: HZ
SGO/SGOF/SEG0
SCK01/TI23/TO23/SEG26
Use of an on-chip pull-up resistor
P75
CRxD0/LRxD0/INTPLR0/TI03/TO03/TOOLRXD
PCL/SI01/TI22/TO22/SEG27
can be specified by a software
setting.
P80
I/O
Port 8. 8-bit I/O port.
Ext.: PD
Input
Input/output can be specified in 1- Int.: HZ
P81
bit units.
P82
SM13/TI05/TO05/SEG34
Use of an on-chip pull-up resistor
P83
SM14/ZPD14/TI07/TO07/SEG35
can be specified by a software
P84
SM11/TI01/TO01/SEG32
SM12/TI03/TO03/SEG33
SM21/TI11/TO11/SEG36
setting.
P85
SM22/TI13/TO13/SEG37
P86
SM23/TI15/TO15/SEG38
P87
SM24/ZPD24/TI17/TO17/SEG39
P90
I/O
Port 9. 8-bit I/O port.
Ext.: PD
Input
Input/output can be specified in 1- Int.: HZ
bit units.
P91
P92
SM33/TI25/TO25/SGOA/SEG42
Use of an on-chip pull-up resistor
P93
SM34/ZPD34/TI27/TO27/SGO/SGOF/SEG43
can be specified by a software
P94
SM31/TI21/TO21/SEG40
SM32/TI23/TO23/SEG41
SM41/TI01/TO01/RTC1HZ/SEG44
setting.
P95
SM42/TI03/TO03/SEG45
P96
SM43/TI05/TO05/SEG46
P97
SM44/ZPD44/TI07/TO07/SEG47
P121
I
Port 12. 4-bit Input port.
HZ
Input
X1
P122
X2/EXCLK
P123
XT1
P124
XT2
Remark
Ext. (external reset): POR reset or pin reset, Int. (internal reset): WDT reset or LVD reset,
PD: Pull down, HZ: High impedance
Note CTxD1 and CRxD1 are not provided for R5F10TPJxFB, R5F10DPGxFB, R5F10DPFxFB and R5F10DPExFB
with a CAN channel.
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Table 2-5. Port Pins for R5F10DPExFB, R5F10DPFxFB, R5F10DPGxFB, R5F10TPJxFB, R5F10DPJxFB (3/3)
Pin Name
I/O
Function
During
After
Reset
Reset
P130
O
Port 13. 1-bit output port, 1-bit
Output Low Output
P131
I/O
input port and 6-bit I/O port.
HZ
Input
Input of P135 can be set to
P132
SCK10/TI22/TO22
Output of P136 can be set to N-
P134
SO10/LTxD1/TI21/TO21
SI10/LRxD1/INTPLR1/TI20/TO20
schmitt 1 input buffer.
P133
Alternate Function
Note1
ch open-drain output.
SGOA/CTxD1/TI24/TO24
P135
Input/output of P131 to P136 can
SGO/SGOF/CRxD1/TI26/TO26
P136
be specified in 1-bit units.
Note1
Ext.: PD
TI00/TO00/SCL11/SEG48
Use of an on-chip pull-up resistor Int.: HZ
P137
I
of P131 to P136 can be specified HZ
by a software setting
Input
INTP5
P140
I/O
Port 14. 1-bit I/O port.
HZ
Input
TI11/TO11
HZ
Analog
ANI8
Input/output can be specified.
Use of an on-chip pull-up resistor
can be specified by a software
setting
P150
I/O
Port 14. 1-bit I/O port.
Can be set to analog input
Note2
Input
Input/output can be specified.
Remark
Ext. (external reset): POR reset or pin reset, Int. (internal reset): WDT reset or LVD reset,
PD: Pull down, HZ: High impedance
Notes 1. CTxD1 and CRxD1 are not provided for R5F10TPJxFB, R5F10DPGxFB, R5F10DPFxFB and
R5F10DPExFB with a CAN channel.
2. Setting digital or analog to each pin can be done in A/D port configuration register (ADPC).
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2.1.5 128-pin products
Table 2-6. R5F10DSJxFB, R5F10DSKxFB, R5F10DSLxFB (1/4)
Pin Name
P00
I/O
I/O
P01
P02
P03
P04
P05
Function
During
After
Reset
Reset
Port 0. 8-bit I/O port.
Ext.: PD
Input of P01 can be set to schmitt 1
input buffer.
Int.: HZ
Input
Alternate Function
CTxD0/TI00/TO00/SEG14
CRxD0/TI01/TO01/SEG15
SO00/TxD0/TI02/TO02/TI12/TO12/SEG16
Input/output can be specified in 1-bit
units.
SI00/RxD0/TI03/TO03/TI13/TO13/SEG17
Use of an on-chip pull-up resistor can
be specified by a software setting.
TI05/TO05/TI15/TO15/SEG19
SCK00/TI04/TO04/TI14/TO14/SEG18
P06
TI06/TO06/TI16/TO16/SEG20
P07
TI07/TO07/TI17/TO17/SEG21
P10
I/O
Port 1. 8-bit I/O port.
Ext.: PD
Input
LTxD1/SCK00/TI10/TO10/INTP4/SEG31
P11
Input of P10, P11, and P17 can be set Int.: HZ
to schmitt 1 input buffer.
LRxD1/INTPLR1/SI00/RxD0/TI11/TO11/
SEG30
P12
Input/output can be specified in 1-bit
units.
SO00/TxD0/TI12/TO12/INTP2/SEG29
P13
SO01/TI13/TO13/SEG25
Use of an on-chip pull-up resistor can
be specified by a software setting.
P14
P15
LRxD0/INTPLR0/TI14/TO14/SEG24
LTxD0/RTC1HZ/TI15/TO15/SEG23
P16
TI16/TO16/SEG22
P17
P20
TI17/TO17/INTP0/SEG28
I/O
Port 2. 8-bit I/O port.
HZ
Note
P21
Can be set to analog input
P22 to P27
Input/output can be specified in 1-bit
units.
P30
I/O
P31
P32
P33
P34
P35
P36
P41
P42
I/O
AVREFP/ANI0
AVREFM/ANI1
ANI2 to ANI7
Port 3. 8-bit I/O port.
Ext.: PD
Input of P31 can be set to schmitt 1
input buffer.
Int.: HZ
Input
TI20/TO20/SCL11/SEG6
TI21/TO21/SDA11/SEG7
TI22/TO22/SO00/TxD0/SEG8
Output of P30 and P31 can be set to
N-ch open-drain output.
TI23/TO23/SI00/RxD0/SEG9
Input/output can be specified in 1-bit
units.
TI25/TO25/SEG11
TI24/TO24/SCK00/SEG10
TI26/TO26/SEG12
Use of an on-chip pull-up resistor can
be specified by a software setting.
P37
P40
Analog
Input
Port 4. 8-bit I/O port.
TI27/TO27/SEG13
Ext.: HZ
Input
TOOL0
Input/output can be specified.
Int.: PU
Use of an on-chip pull-up resistor can
be specified by a software setting.
HZ
STOPST/TI04/TO04
Ext.: PD
TI10/TO10/SEG7
Int.: HZ
TI22/TO22/SEG14
P43
P44
TI23/TO23/SEG15
P45
SEG53
P46
DBWR/SEG27
P47
DBRD/SEG26
Remark
___________
__________
Ext. (external reset): POR reset or pin reset, Int. (internal reset): WDT reset or LVD reset,
PD: Pull down, PU: Pull up, HZ: High impedance
Note Setting digital or analog to each pin can be done in A/D port configuration register (ADPC).
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Table 2-6. R5F10DSJxFB, R5F10DSKxFB, R5F10DSLxFB (2/4)
Pin Name
P50
I/O
I/O
Port 5. 8-bit I/O port.
During
After
Reset
Reset
Ext.: PD
Input
Input of P50 to P52 and P55 to
Int.: HZ
P57 can be set to schmitt 1 input
buffer.
P51
P52
P53
P55
P56
P57
I/O
TI13/TO13/SO10/SEG52
TI14/TO14/SO01/SEG2
Input/output can be specified in 1bit units.
TI15/TO15/SI01/SEG3
Use of an on-chip pull-up resistor
can be specified by a software
setting.
TI17/TO17/SEG5
Port 6. 7-bit I/O port.
TI16/TO16/SCK01/SEG4
HZ
Input
CTxD1/TI27/TO27
Output of P60 and P61 can be set
P63
CRxD1/TI26/TO26
to N-ch open-drain output.
P64
RTC1HZ/TI11/TO11
Input/output can be specified in
P65
P66
SCL11/TI20/TO20/INTP1
SDA11/TI21/TO21/INTP3
schmitt 1 input buffer.
P62
TI02/TO02/SDA11/SEG49
TI06/TO06/SI10/SEG51
Input of P61, P63 can be set to
P61
Alternate Function
TI04/TO04/SCK10/SEG50
Output of P50 can be set to N-ch
open-drain output.
P54
P60
Function
1-bit units.
TI25/TO25
Use of an on-chip pull-up resistor
TI24/TO24/PCL
can be specified by a software
setting.
P70
I/O
Port 7. 6-bit I/O port.
HZ
Input
Input of P70 can be set to
P71
schmitt 1 input buffer.
P72
Input/output can be specified in 1-
P73
bit units.
P74
CTxD0/LTxD0/TOOLTxD
Ext.: PD
SGOA/ADTRG/SEG1
Int.: HZ
SGO/SGOF/SEG0
SCK01/TI23/TO23/SEG26
Use of an on-chip pull-up resistor
P75
CRxD0/LRxD0/INTPLR0/TI03/TO03/TOOLRxD
SI01/TI22/TO22/SEG27/PCL
can be specified by a software
setting.
P80
P81
P82
P83
P84
I/O
Port 8. 8-bit I/O port.
Ext.: PD
Input/output can be specified in 1- Int.: HZ
bit units.
Use of an on-chip pull-up resistor
can be specified by a software
setting.
Input
SM11/TI01/TO01/SEG32
SM12/TI03/TO03/SEG33
SM13/TI05/TO05/SEG34
SM14/ZPD14/TI07/TO07/SEG35
SM21/TI11/TO11/SEG36
P85
SM22/TI13/TO13/SEG37
P86
SM23/TI15/TO15/SEG38
P87
SM24/ZPD24/TI17/TO17/SEG39
Remark
Ext. (external reset): POR reset or pin reset, Int. (internal reset): WDT reset or LVD reset,
PD: Pull down, HZ: High impedance
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RL78/D1A
CHAPTER 2 PIN FUNCTIONS
Table 2-6. R5F10DSJxFB, R5F10DSKxFB, R5F10DSLxFB (3/4)
Pin Name
P90
I/O
I/O
Function
Port 9. 8-bit I/O port.
During
After
Reset
Reset
Ext.: PD
Input
Input/output can be specified in 1- Int.: HZ
P91
SM33/SGOA/TI25/TO25/SEG42
Use of an on-chip pull-up resistor
P93
SM34/ZPD34/SGO/SGOF/TI27/TO27/SEG43
can be specified by a software
P94
SM31/TI21/TO21/SEG40
SM32/TI23/TO23/SEG41
bit units.
P92
Alternate Function
SM41/RTC1HZ/TI01/TO01/SEG44
setting.
P95
SM42/TI03/TO03/SEG45
P96
SM43/TI05/TO05/SEG46
P97
SM44/ZPD44/TI07/TO07/SEG47
P100
I/O
Port 10. 8-bit I/O port.
Ext.: PD
Input
Input/output can be specified in 1- Int.: HZ
P101
bit units.
P102
TI26/TO26/SEG38
Use of an on-chip pull-up resistor
P103
TI27/TO27/SEG39
can be specified by a software
P104
TI24/TO24/SEG36
TI25/TO25/SEG37
TI01/TO01/SEG44
setting.
P105
TI02/TO02/SEG45
P106
TI05/TO05/SEG46
P107
TI06/TO06/SEG47
P110
I/O
P111
Port 10. 8-bit I/O port.
Ext.: PD
Input can be set to
Int.: HZ
Input
schmitt 1 input buffer.
P112
DBD2/SO00/TxD0/TI04/TO04/SEG33
Input/output can be specified in 1-
P113
DBD3/TI06/TO06/SEG32
bit units.
P114
DBD4/TI07/TO07/SEG31
Use of an on-chip pull-up resistor
P115
P116
can be specified by a software
DBD5/TI10/TO10/SEG30
setting.
DBD6/TI12/TO12/SEG29
P117
P121
DBD7/TI20/TO20/SEG28
I
be specified in 1-bit units.
P124
I/O
Use of an on-chip pull-up resistor
of P125 to P127 can be specified Ext.: PD
Int.: HZ
by a software setting.
P127
Remark
HZ
Input/output of P125 to P127 can
P123
P126
Port 12. 4-bit Input port, 3-bit I/O
port.
P122
P125
DBD0/SCK00/TI00/TO00/SEG35
DBD1/SI00/RxD0/TI02/TO02/SEG34
Input
X1
X2/EXCLK
XT1
XT2
TI12/TO12/SEG25
TI14/TO14/SEG24
TI16/TO16/SEG23
Ext. (external reset): POR reset or pin reset, Int. (internal reset): WDT reset or LVD reset,
PD: Pull down, HZ: High impedance
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Mar 23, 2015
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RL78/D1A
CHAPTER 2 PIN FUNCTIONS
Table 2-6. R5F10DSJxFB, R5F10DSKxFB, R5F10DSLxFB (4/4)
Pin Name
I/O
Function
During
After
Reset
Reset
Alternate Function
P130
O
Port 13. 1-bit output port, 1-bit
Output Low Output
RESOUT
P131
I/O
input port and 6-bit I/O port.
HZ
SO10/LTxD1/TI21/TO21
Input
Input of P135 can be set to
P132
SI10/LRxD1/INTPLR1/TI20/TO20
schmitt 1 input buffer.
P133
SCK10/TI22/TO22
Output of P136 can be set to N-
P134
ch open-drain output.
SGOA/CTxD1/TI24/TO24
P135
Input/output of P131 to P136 can
SGO/SGOF/CRxD1/TI26/TO26
P136
be specified in 1-bit units.
Ext.: PD
TI00/TO00/SCL11/SEG48
Use of an on-chip pull-up resistor Int.: HZ
P137
I
of P131 to P136 can be specified HZ
by a software setting
Input
INTP5
P140
I/O
Port 14. 1-bit I/O port.
HZ
Input
TI11/TO11
HZ
Analog
ANI8
Input
ANI9
Input/output can be specified.
Use of an on-chip pull-up resistor
can be specified by a software
setting
P150
I/O
Port 15. 3-bit I/O port.
Note
P151
Can be set to analog input
P152
Input/output can be specified.
Remark
ANI10
Ext. (external reset): POR reset or pin reset, Int. (internal reset): WDT reset or LVD reset,
PD: Pull down, HZ: High impedance
Note Setting digital or analog to each pin can be done in A/D port configuration register (ADPC).
R01UH0317EJ0110 Rev. 1.10
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RL78/D1A
CHAPTER 2 PIN FUNCTIONS
2.1.6 Pins for each product (pins other than port pins)
(1/6)
Function
Name
I/O
Function
48-pin
64-pin
80-pin
100-pin
128-pin
R5F10CGx/
R5F10CLx/
R5F10DLx
R5F10CMx/
R5F10DMx
R5F10TPx/
R5F10DPx
R5F10DSx
R5F10DGx
ADTRG
ANI0/AVREFP
ANI1/AVREFM
Input
A/D conversion start
trigger external input
31
43
55
65
53
A/D converter analog
input
4
4
8
10
113
3
3
7
9
112
ANI2
2
2
6
8
111
ANI3
1
5
7
110
ANI4
1
4
6
109
ANI5
3
5
108
2
4
107
1
3
106
2
105
ANI6
ANI7
48
64
ANI8
ANI9
104
ANI10
103
COM0
Output LCD common output 0
36
48
60
70
58
COM1
LCD common output 1
35
47
59
69
57
COM2
LCD common output 2
34
46
58
68
56
COM3
LCD common output 3
33
45
57
67
55
SEG0
Output LCD segment output 0
32
44
56
66
54
SEG1
LCD segment output 1
31
43
55
65
53
SEG2
LCD segment output 2
30
42
54
64
52
SEG3
LCD segment output 3
29
41
53
63
51
SEG4
LCD segment output 4
28
40
52
62
50
SEG5
LCD segment output 5
27
39
51
61
49
SEG6
LCD segment output 6
26
38
50
60
48
SEG7
LCD segment output 7
25
37
49
59
47, 95
SEG8
LCD segment output 8
36
48
58
46
SEG9
LCD segment output 9
47
57
45
SEG10
LCD segment output 10
46
56
44
SEG11
LCD segment output 11
45
55
43
SEG12
LCD segment output 12
44
54
42
SEG13
LCD segment output 13
43
53
41
SEG14
LCD segment output 14
23
34
42
52
40, 94
SEG15
LCD segment output 15
22
33
41
51
39, 93
SEG16
LCD segment output 16
32
40
50
35
SEG17
LCD segment output 17
31
39
49
34
SEG18
LCD segment output 18
30
38
48
33
SEG19
LCD segment output 19
29
37
47
32
SEG20
LCD segment output 20
36
46
31
SEG21
LCD segment output 21
35
45
30
SEG22
LCD segment output 22
34
44
29
SEG23
LCD segment output 23
27
33
43
28, 38
SEG24
LCD segment output 24
21
26
32
42
27, 37
SEG25
LCD segment output 25
20
25
31
41
26, 36
SEG26
LCD segment output 26
19
24
30
40
25, 19
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28
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RL78/D1A
CHAPTER 2 PIN FUNCTIONS
(2/6)
Function
Name
I/O
Function
48-pin
64-pin
80-pin
100-pin
128-pin
R5F10CGx/
R5F10DGx
R5F10CLx/
R5F10DLx
R5F10CMx/
R5F10DMx
R5F10TPx/
R5F10DPx
R5F10DSx
SEG27
LCD segment output 27
18
23
29
39
24, 18
SEG28
LCD segment output 28
-
22
28
38
23, 17
SEG29
Output LCD segment output 29
17
21
27
37
22, 16
SEG30
LCD segment output 30
16
20
26
36
21, 15
SEG31
LCD segment output 31
15
19
25
35
20, 14
SEG32
LCD segment output 32
47
63
80
95
88 ,13
SEG33
LCD segment output 33
46
62
79
94
87 ,12
SEG34
LCD segment output 34
45
61
78
93
86 ,11
SEG35
LCD segment output 35
44
60
77
92
85 ,10
SEG36
LCD segment output 36
57
74
89
82 ,92
SEG37
LCD segment output 37
56
73
88
81 ,91
SEG38
LCD segment output 38
55
72
87
80 ,90
SEG39
LCD segment output 39
54
71
86
79 ,89
SEG40
LCD segment output 40
41
53
70
85
78
SEG41
LCD segment output 41
40
52
69
84
77
SEG42
LCD segment output 42
39
51
68
83
76
SEG43
LCD segment output 43
38
50
67
82
75
SEG44
LCD segment output 44
37
64
79
72, 68
SEG45
LCD segment output 45
63
78
71, 67
SEG46
LCD segment output 46
62
77
70, 66
SEG47
LCD segment output 47
61
76
69, 65
SEG48
LCD segment output 48
75
64
SEG49
LCD segment output 49
74
63
SEG50
LCD segment output 50
73
62
SEG51
LCD segment output 51
72
61
SEG52
LCD segment output 52
71
SEG53
LCD segment output 53
TI00
TI01
TI02
Input
External count clock input/ 23
capture trigger to 16-bit
22, 37, 47
timer 00 to 07
TI03
46
TI04
TI05
45
TI07
TO01
34
Output 16-bit timer 00 to 07
output
63,49,33
80,64,41
95,79,51
39, 88, 72, 68
40
74,50
35, 63, 67, 11
62,7,31
79,63,11,39
94,78,49,13
34, 87, 71, 116
30
38
48,73
33, 62, 12, 101
61, 29
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
78,62,37
93,77,47
32, 86, 70, 66
36
46,72
31, 61, 65, 13
77,61,35
92,76,45
30, 85, 69, 14
23
34
42
75,52
40, 64, 10
22, 37, 47
63,49,33
80,64,41
95,79,51
39, 88, 72, 68
32
40
74,50
35, 63, 67, 11
62,7, 31
79,63,11,39
94,78,49,13
34, 87, 71, 116
30
38
48,73
33, 62, 12, 101
46
45
61,29
TO06
TO07
40, 64,10
60,28
TO04
TO05
59
75,52
44
TO02
TO03
42
60
32
TI06
TO00
49
44
60,28
78,62,37
93,77,47
32, 86, 70, 66
36
46,72
31, 61, 65, 13
77,61,35
92,76,45
30, 85, 69, 14
42
RL78/D1A
CHAPTER 2 PIN FUNCTIONS
(3/6)
Function
Name
TI10
I/O
Input
Function
48-pin
64-pin
80-pin
100-pin
128-pin
R5F10CGx/
R5F10DGx
R5F10CLx/
R5F10DLx
R5F10CMx/
R5F10DMx
R5F10TPx/
R5F10DPx
R5F10DSx
TI12
External count clock input/ 15
capture trigger to 16-bit
16
timer 10 to 17
17
TI13
20
56,25,31
73,31,39
88,71,41,49
34, 26, 60, 81
TI14
21, 30
30,26,42
38,32,54
48,42,64
27, 37, 52, 33
TI15
29
55,41,27,29
72,53,33,37
87,63,43,47
28, 32, 51, 80
TI16
28
40
36,34,52
46,44,62
29, 38, 50, 31
27
54,39,22,28
71,51,28,35
86,61,38,45
23, 30, 79, 49
19
25
35
20, 15, 95
74,26
89,14,30,36
21, 82, 117, 5
TI11
TI17
19
25
35
57, 20
74, 26
89,14,30, 36 21, 82, 117, 5
32, 21
40, 27
50, 37
22, 36, 35, 16
20, 15 , 95
TO10
Output 16-bit timer 10 to 17 output 15
TO11
16
57, 20
TO12
17
32,21
40,27
50,37
22, 36, 35, 16
TO13
20
56,25,31
73,31,39
88,71,41,49
34, 26, 60, 81
TO14
21, 30
30,26,42
38,32,54
48,42,64
27, 37, 52, 33
TO15
29
55,41,27,29
72,53,33,37
87,63,43,47
28, 32, 51, 80
TO16
28
40
36,34,52
46,44,62
29, 38, 50, 31
TO17
27
54,39,22,28
71,51,28,35
86,61,38,45
23, 30, 79, 49
13, 26
17,38
21,50
26,60,99
1, 48, 99, 17
14, 25, 41
53,37,18
70,49,22
100,85,59,2
7
2, 47, 100, 78
TI20
Input
TI21
External count clock input
/capture trigger to 16-bit
timer 20 to 27
TI22
18
23,36
29,48
39,58,98
24, 46, 98, 94
TI23
19, 24, 40
52,35,24
69,47,30
84,57,40
25, 45, 77, 93
TI24
24,46
32,56,97
7, 44, 97, 92
68,45,23
83,55,31
6, 76, 43, 91
44
29,54,96
4, 42, 96, 90
50
67,43
82,53,28
75, 3, 41, 89
17,38
21,50
26,60,99
1, 48, 99, 17
53,37,18
70,49,22
100,85,59,2
7
2, 47, 100, 78
TI25
39
TI27
TO20
51
TI26
38
Output 16-bit timer 20 to 27 output 13, 26
TO21
14, 25, 41
TO22
18
23,36
29,48
39,58,98
24, 46, 98, 94
TO23
19, 24, 40
52,35,24
69,47,30
84,57,40
25, 45, 77, 93
24,46
32,56,97
7, 44, 97, 92
68,45,23
83,55,31
6, 76, 43, 91
44
29,54,96
4, 42, 96, 90
TO24
TO25
39
51
TO26
TO27
38
50
67,43
82,53,28
75, 3, 41, 89
SCK00
Input/ Clock input/output for
Output CSI00
15
19,30
46,25,38
56,35,48
20, 33, 44,10
SI00
Input
16
20,31
47,26,39
57,36,49
21, 34, 45, 11
SO00
Output Serial data output from
CSI00
17
21,32
48,27,40
58,37,50
22, 35, 46, 12
SCK01
Input/ Clock input/output for
Output CSI01
19, 28
40,24
52,30
62,40
50, 25
SI01
Input
18, 29
41,23
53,29
63,39
51, 24
SO01
Output Serial data output from
CSI01
20, 30
42,25
54,31
64,41
Serial data input to CSI00
Serial data input to CSI01
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
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RL78/D1A
CHAPTER 2 PIN FUNCTIONS
(4/6)
Function
Name
I/O
48-pin
64-pin
80-pin
100-pin
128-pin
R5F10CGx/
R5F10DGx
R5F10CLx/
R5F10DLx
R5F10CMx/
R5F10DMx
R5F10TPx/
R5F10DPx
R5F10DSx
21, 34, 45, 11
22, 35, 46, 12
Function
RxD0
Input
TxD0
Output Serial data output from
UART0
SCK10
Input/ Clock input/output for CSI10
Output
98,73
98, 62
SI10
Input
99,72
99, 61
SO10
Output Serial data output from CSI10
100,71
100, 60
SCL11
Output Clock output for simplified I C 13, 26
38,17
50,21
75,60,26
64, 48, 1
SDA11
Input/ Serial data I/O for simplified
2
Output I C
14, 25
37,18
49,22
74,59,27
63, 47, 2
LRxD0
Input
Serial data input to LINUART0
26,7
32,11
42,13
27, 116
INTPLR0
Input
External interrupt request
input for which the valid edge
for LIN-UART0
26,7
32,11
42,13
27, 116
LTxD0
Output Serial data output from LINUART0
27,6
33,10
43,12
28, 115
LRxD1
Input
Serial data input to LINUART1
16
20
26
99,36
99, 21
INTPLR1
Input
External interrupt request
16
input for which the valid edge
for LIN-UART1
20
26
99,36
99, 21
LTxD1
Output Serial data output from LINUART1
15
19
25
100,35
100, 20
CRxD0
Input
22
Note1
39, 116
23
Note1
CTxD0
CRxD1
Serial data input to UART0
Serial data input to CSI10
2
CAN receive data input 0
Output CAN transmit data output 0
Input
CAN receive data input 1
33,7
Note1
41,11
Note1
51,13
34,6
Note1
42,10
Note1
52,12
40, 115
96,29
Note2
97,28
Note2
96, 4
CTxD1
Output CAN transmit data output 1
RTC1Hz
Output Realtime clock calibration
output (1Hz)
37
49,27
64,33
79,30,43
72, 28, 5
97, 3
SGOA
Output SG output(Amplitude PWM)
31, 39
51,43
68,55
97,83,65
97, 76, 53
SGO/SGOF
Output SG output (AND with PWM & 32, 38
Frequency) / SG output
(Frequency)
50,44
67, 56
96,82,66
96, 75, 54
SM11
Output Stepper motor output 11
47
63
80
95
88
SM12
Output Stepper motor output 12
46
62
79
94
87
SM13
Output Stepper motor output 13
45
61
78
93
86
SM14
Output Stepper motor output 14
44
60
77
92
85
ZPD14
Input
Zero point detection input 14 44
60
77
92
85
Notes 1. These pins are only for the following products:
R5F10DGE, R5F10DGD, R5F10DGC (48 pin products)
R5F10DLE, R5F10DLD (64 pin products)
R5F10DMJ, R5F10DMG, R5F10DMF, R5F10DME, R5F10DMD (80 pin products)
R5F10TPJ, R5F10DPG. R5F10DPF, R5F10DPE, R5F10DPL, R5F10DPK,R5F10DPJ (100-pin
products)
2. These pins are only for R5F10DPL, R5F10DPK,R5F10DPJ.
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
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RL78/D1A
CHAPTER 2 PIN FUNCTIONS
(5/6)
Function
Name
I/O
Function
48-pin
64-pin
80-pin
100-pin
128-pin
R5F10CGx/
R5F10DGx
R5F10CLx/
R5F10DLx
R5F10CMx/
R5F10DMx
R5F10TPx/
R5F10DPx
R5F10DSx
SM21
Output Stepper motor output 21
57
74
89
82
SM22
Output Stepper motor output 22
56
73
88
81
SM23
Output Stepper motor output 23
55
72
87
80
SM24
Output Stepper motor output 24
54
71
86
79
ZPD24
Input
54
71
86
79
SM31
Output Stepper motor output 31
70
85
78
SM32
Output Stepper motor output 32
69
84
77
SM33
Output Stepper motor output 33
68
83
76
SM34
Output Stepper motor output 34
67
82
75
ZPD34
Input
67
82
75
SM41
Output Stepper motor output 41
64
79
72
SM42
Output Stepper motor output 42
63
78
71
SM43
Output Stepper motor output 43
62
77
70
SM44
Output Stepper motor output 44
61
76
69
ZPD44
Input
Zero point detection input 44
61
76
69
DBD0
Input/
LCD Bus I/F data lines 0
10
DBD1
Input/
LCD Bus I/F data lines 1
11
DBD2
Input/
LCD Bus I/F data lines 2
12
DBD3
Input/
LCD Bus I/F data lines 3
13
LCD Bus I/F data lines 4
14
LCD Bus I/F data lines 5
15
LCD Bus I/F data lines 6
16
LCD Bus I/F data lines 7
17
Output LCD Bus I/F write strobe
18
DBRD
Output LCD Bus I/F read strobe
19
STOPST
Output STOP status output
101
RESOUT
Output Reset output signal
102
PCL
Output Clock output
INTP0
Input
Interrupt from peripheral 0
INTP1
Input
Interrupt from peripheral 1
INTP2
Input
Interrupt from peripheral 2
INTP3
Input
INTP4
Input
INTP5
Input
Zero point detection input 24
Zero point detection input 34
Output
Output
Output
Output
DBD4
Input/
Output
DBD5
Input/
Output
DBD6
Input/
Output
DBD7
Input/
Output
___________
DBWR
__________
23
24,29
32,39
24, 7
22
28
38
23
13
17
21
26
1
17
21
27
37
22
Interrupt from peripheral 3
14
18
22
27
2
Interrupt from peripheral 4
15
19
25
35
20
Interrupt from peripheral 5
7
11
15
18
121
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
18
–
45
RL78/D1A
CHAPTER 2 PIN FUNCTIONS
(6/6)
Function
Name
EXCLK
I/O
Input
X1
External clock input for main
system clock
Resonator connection for
main system clock
X2
XT1
48-pin
64-pin
80-pin
100-pin
128-pin
R5F10CGx/
R5F10DGx
R5F10CLx/
R5F10DLx
R5F10CMx/
R5F10DMx
R5F10TPx/
R5F10DPx
R5F10DSx
8
RESET
Input
External system reset input
TOOLRxD
Input
UART reception pin for the
external device connection
used during flash memory
programming
TOOLTxD
Output UART transmission pin for the
external device connection
used during flash memory
programming
TOOL0
Input/ Data I/O for flash memory
output programmer/debugger
12
16
19
122
123
9
13
17
20
8
12
16
19
122
10
14
17
120
Resonator connection for sub
clock
XT2
____________
Function
–
–
9
13
16
119
8
12
15
118
–
7
11
13
116
–
6
10
12
115
5
5
9
11
114
6
REGC
Connecting regulator output
stabilization capacitance for
internal operation.
Connect to VSS via a
capacitor
(0.47 to 1 μF).
10
14
18
21
124
VDD
Power supply for P20 to P27, 12
P150,
P137, P121 to P124, RESET
16
20
24
127
EVDD,
EVDD0,
EVDD1
Power supply for
12
P00 to P07, P10 to P17, P30
to P37,
P50 to P57, P60 to P66, P70
to P75,
P130 to P136 and P140
16
20
25, 33
8, 128
SMVDD,
SMVDD0,
SMVDD1
Power supply for P80 to P87, 43
P90 to P97
59
66, 76
81, 91
74, 84
VSS
Ground potential for
P20-P27, P150, P137, P121
to P124, RESET
11
15
19
22
125
EVSS,
EVSS0,
EVSS1
Ground potential for
11
P00 to P07, P10 to P17, P30
to P37,
P50 to P57, P60 to P66, P70
to P75,
P130 to P136 and P140
15
19
23, 34
9, 126
SMVSS,
SMVSS0,
SMVSS1
Ground potential for P80 to
P87,
P90 to P97
58
65, 75
80, 90
73, 83
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2.2 Description of Pin Function
Remark
The pins mounted depend on the product. See 1.4 Pin Configuration (Top View) and 2.1 Pin Function
List.
2.2.1 P00 to P07 (port 0)
48-pin products:
P00 to P01 function as a 2-bit I/O port.
64-pin products:
P00 to P05 and P07 function as a 7-bit I/O port.
80-pin products:
P00 to P07 function as an 8-bit I/O port.
100-pin products:
P00 to P07 function as an 8-bit I/O port.
128-pin products:
P00 to P07 function as an 8-bit I/O port.
These pins also function as timer I/O, serial interface data I/O, and segment signal outputs for the LCD controller/driver.
Input to the P01 pin can be specified through a normal Schmitt3 input buffer or a Schmitt1 input buffer in 1-bit units,
using port input mode register 0 (PIM0).
The following operation modes can be specified in 1-bit units.
(1) Port mode
48-pin products:
P00 to P01 function as a 2-bit I/O port.
64-pin products:
P00 to P05 and P07 function as a 7-bit I/O port.
80-pin products:
P00 to P07 function as an 8-bit I/O port.
100-pin products:
P00 to P07 function as an 8-bit I/O port.
128-pin products:
P00 to P07 function as an 8-bit I/O port.
P00 to P07 can be set to input or output port in 1-bit units using port mode register 0 (PM0). Use of an on-chip pull-up
resistor can be specified by pull-up resistor option register 0 (PU0).
(2) Control mode
P00 to P07 function as timer I/O, serial interface data I/O, and segment signal outputs for the LCD controller/driver.
(a) TI00 (P00) to TI07 (P07) and TI12 (P02) to TI17 (P07)
These are the external count clock input /capture trigger to 16-bit timer 00 to 07, and 12 to 17.
(b) TO00 (P00) to TO07 (P07) and TO12 (P02) to TO17 (P07)
These are the timer output pins of 16-bit timers 00 to 07, and 12 to 17.
(c) CTxD0 (P00)
This is a CAN serial transmit data output pin of aFCAN0.
(d) CRxD0 (P01)
This is a CAN serial receive data input pin of aFCAN0.
(e) SO00 (P02)
This is a serial data output pin of serial interface CSI00.
(f) SI00 (P03)
This is a serial data input pin of serial interface CSI00.
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(g) SCK00 (P04)
This is a serial clock I/O pin of serial interface CSI00.
(h) SEG14 (P00) to SEG21 (P07)
These are the segment signal output pins for the LCD controller/driver.
(i)
TxD0 (P02)
This is a serial data output pin of serial interface UART0.
(j)
RxD0 (P03)
This is a serial data input pin of serial interface UART0.
2.2.2 P10 to P17 (port1)
48-pin products:
P10 to P14 function as a 5-bit I/O port.
64-pin products:
P10 to P15 and P17 function as a 7-bit I/O port.
80-pin products:
P10 to P17 function as an 8-bit I/O port.
100-pin products:
P10 to P17 function as an 8-bit I/O port.
128-pin products:
P10 to P17 function as an 8-bit I/O port.
These pins also function as serial interface data I/O, timer I/O, clock I/O, external interrupt request input and segment
signal outputs for the LCD controller/driver.
Input to the P10, P11 and P17 pins can be specified through a normal Schmitt3 input buffer or a Schmitt1 input buffer
in 1-bit units, using port input mode register 1 (PIM1).
The following operation modes can be specified in 1-bit units.
(1) Port mode
48-pin products:
P10 to P14 function as a 5-bit I/O port.
64-pin products:
P10 to P15 and P17 function as a 7-bit I/O port.
80-pin products:
P10 to P17 function as an 8-bit I/O port.
100-pin products:
P10 to P17 function as an 8-bit I/O port.
128-pin products:
P10 to P17 function as an 8-bit I/O port.
P10 to P17 can be set to input or output port in 1-bit units using port mode register 1 (PM1). Use of an on-chip pull-up
resistor can be specified by pull-up resistor option register 1 (PU1).
(2) Control mode
P10 to P17 function as serial interface data I/O, timer I/O, clock I/O, external interrupt request input, and segment
signal outputs for the LCD controller/driver.
(a) LTxD0 (P15), LTxD1 (P10)
These are the Serial data output from LIN-UART.
(b) LRxD0 (P14), LRxD1 (P11)
These are the Serial data input to LIN-UART.
(c) SO00 (P12), SO01 (P13)
These are the serial data output pins of serial interface CSI00 and CSI01.
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(d) SI00 (P11)
This is a serial data input pins of serial interface CSI00.
(e) SCK00 (P10)
This is the serial clock I/O pin of serial interface CSI00.
(f) TI10 (P10) to TI17 (P17)
These are the pins for inputting an external count clock/capture trigger to 16-bit timers 10 to 17.
(g) TO10 (P10) to TO17 (P17)
These are the timer output pins of 16-bit timers 10 to 17.
(h) RTC1HZ (P15)
This is a real-time clock correction clock (1 Hz) output pin.
(i)
INTP0 (P17), INTP2 (P12), INTP4 (P10)
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(j)
INTPLR0 (P14), INTPLR1 (P11)
These are the external interrupt request input for which the valid edge for LIN-UART0 and 1.
(k) SEG22 (P16) to SEG25 (P13), SEG28 (P17) and SEG29 (P12) to SEG31(P10)
These are the segment signal output pins for the LCD controller/driver.
(l)
TxD0 (P12)
This is a serial data output pin of serial interface UART0.
(m) RxD0 (P11)
This is a serial data input pin of serial interface UART0.
2.2.3 P20 to P27 (port2)
48-pin products:
P20 to P23 and P27 function as a 5-bit I/O.
64-pin products:
P20 to P23 and P27 function as a 5-bit I/O.
80-pin products:
P20 to P27 function as an 8-bit I/O port.
100-pin products:
P20 to P27 function as an 8-bit I/O port
128-pin products:
P20 to P27 function as an 8-bit I/O port
These pins also function as A/D converter analog input and reference voltage input.
The following operation modes can be specified in 1-bit units.
(1) Port mode
48-pin products:
P20 to P23 and P27 function as a 5-bit I/O.
64-pin products:
P20 to P23 and P27 function as a 5-bit I/O.
80-pin products:
P20 to P27 function as an 8-bit I/O port.
100-pin products:
P20 to P27 function as an 8-bit I/O port
128-pin products:
P20 to P27 function as an 8-bit I/O port
P20 to P27 can be set to input or output port in 1-bit units using port mode register 2 (PM2).
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(2) Control mode
P20 to P27 function as A/D converter analog input and reference voltage input.
(a) ANI0 (P20) to ANI7 (P27)
These are the analog input pins (ANI0 to ANI7) of A/D converter.
When using these pins as analog input pins, see 11.10 (5) Analog input (ANIn) pins.
(b) AVREFP (P20)
This is a pin that inputs the A/D converter reference potential (+ side).
(c) AVREFM (P21)
This is a pin that inputs the A/D converter reference potential (−side).
2.2.4 P30 to P37 (port3)
48-pin products:
64-pin products:
80-pin products:
100-pin products:
128-pin products:
P30, P31, P33 function as a 3-bit I/O port.
P30 to P33 function as a 4-bit I/O port.
P30 to P37 function as an 8-bit I/O port.
P30 to P37 function as an 8-bit I/O port.
P30 to P37 function as an 8-bit I/O port.
These pins also function as timer I/O, serial interface data I/O, and segment signal outputs for the LCD controller/driver.
Input to the P31 pin can be specified through a normal Schmitt3 input buffer or a Schmitt1 input buffer, using port input
mode register 1 (PIM3).
Output from the P30 and P31 pins can be specified as normal CMOS output or N-ch open-drain output (VDD tolerance)
in 1-bit units, using port output mode register (POM).
The following operation modes can be specified in 1-bit units.
(1) Port mode
48-pin products:
64-pin products:
80-pin products:
100-pin products:
128-pin products:
P30, P31, P33 function as a 3-bit I/O port.
P30 to P33 function as a 4-bit I/O port.
P30 to P37 function as an 8-bit I/O port.
P30 to P37 function as an 8-bit I/O port.
P30 to P37 function as an 8-bit I/O port.
P30 to P37 can be set to input or output port in 1-bit units using port mode register 3 (PM3). Use of an on-chip pull-up
resistor can be specified by pull-up resistor option register 3 (PU3).
(2) Control mode
P30 to P37 function as timer I/O, serial interface data I/O, and segment signal outputs for the LCD controller/driver.
(a) TI20 (P30) to TI27 (P37)
These are the pins for inputting an external count clock/capture trigger to 16-bit timers 20 to 27.
(b) TO20 (P30) to TO27(P37)
These are the timer output pins of 16-bit timers 20 to 27.
(c) SO00 (P32 in 80-pin and 100-pin product)
This is a serial data output pin of serial interface CSI00.
(d) SI00 (P33 in 80-pin and 100-pin product)
This is a serial data input pin of serial interface CSI00.
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(e) SCK00 (P34)
This is the serial clock I/O pin of serial interface CSI00.
(f) SCL11 (P30)
2
This is a serial clock output pin of serial interface for simplified I C.
(g) SDA11 (P31)
2
This is a serial data I/O pin of serial interface for simplified I C.
(h) SEG6 (P30) to SEG13 (P37)
These are the segment signal output pins for the LCD controller/driver.
(i)
TxD0 (P32)
This is a serial data output pin of serial interface UART0.
(j)
RxD0 (P33)
This is a serial data input pin of serial interface UART0.
2.2.5 P40 (port4)
P40 to P47 function as an 8-bit I/O port.
These pins also functions as data I/O for a flash memory programmer / debugger, STOP status output, timer I/O,
segment signal outputs for the LCD controller/driver, LCD Bus I/F write strobe, and LCD Bus I/F read strobe.
When this pin functions as data I/O for a flash memory programmer / debugger, this pin is N-ch open-drain output.
(1) Port mode
P40 to P47 function as an I/O port. These ports can be set to input or output port using port mode register 4 (PM4).
Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (PU4).
(2) Control mode
P40 to P47 function as data I/O for a flash memory programmer / debugger, STOP status output, timer I/O, segment
signal outputs for the LCD controller/driver, LCD Bus I/F write strobe, and LCD Bus I/F read strobe.
(a) TOOL0 (P40)
This is a data I/O pin for a flash memory programmer/debugger.
Be sure to pull up this pin externally when on-chip debugging is enabled (pulling it down is prohibited).
Caution After reset release, the relationships between P40/TOOL0 and the operating mode are as follows.
Table 2-6. Relationships Between P40/TOOL0 and Operation Mode After Reset Release
P40/TOOL0
Operating mode
VDD
Normal operation mode
0V
Flash memory programming mode
For details, see 29.5 Programming Method.
(b) STOPST (P41)
This is an output pin of STOP status.
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(c) TI04 (P41), TI10 (P42) TI22 (P43) TI23 (P44)
These are the pin for inputting an external count clock/capture trigger to 16-bit timers 04, 10, 22, 23.
(d) TO04 (P41), TO10 (P42), TO22 (P43), TO23 (P44)
These are the timer output pins of 16-bit timers 04, 10, 22, 23.
(e) SEG7 (P42), SEG14 (P43), SEG15 (P44), SEG53 (P45), SEG27 (P46), SEG26 (P47)
These are the segment signal output pins for the LCD controller/driver.
___________
(f)
DBWR (P46)
This is an output pins for LCD Bus I/F write strobe.
__________
(g) DBRD (P47)
This is an output pins for LCD Bus I/F read strobe.
2.2.6 P50 to P57 (port5)
48-pin products:
P54 to P57 function as a 4-bit I/O port.
64-pin products:
P54 to P57 function as a 4-bit I/O port.
80-pin products:
P54 to P57 function as a 4-bit I/O port.
100-pin products:
P50 to P57 function as an 8-bit I/O port.
128-pin products:
P50 to P57 function as an 8-bit I/O port.
These pins also function as timer I/O, serial interface data I/O, and segment signal outputs for the LCD controller/driver.
Input to the P50 to P52 and P55 to P57 pins can be specified through a normal Schmitt3 input buffer or a Schmitt1
input buffer, using port input mode register 5 (PIM5).
Output from the P50 pin can be specified as normal CMOS output or N-ch open-drain output (VDD tolerance), using
port output mode register (POM).
The following operation modes can be specified in 1-bit units.
(1) Port mode
48-pin products:
P54 to P57 function as a 4-bit I/O port.
64-pin products:
P54 to P57 function as a 4-bit I/O port.
80-pin products:
P54 to P57 function as a 4-bit I/O port.
100-pin products:
P50 to P57 function as an 8-bit I/O port.
128-pin products:
P50 to P57 function as an 8-bit I/O port.
P50 to P57 can be set to input or output port in 1-bit units using port mode register 5 (PM5). Use of an on-chip pull-up
resistor can be specified by pull-up resistor option register 5 (PU5).
(2) Control mode
P50 to P57 function as timer I/O, serial interface data I/O, and segment signal outputs for the LCD controller / driver.
(a) TI02 (P50), TI04 (P51), TI06 (P52) and TI13 (P53) to TI17 (P57)
These are the pins for inputting an external count clock/capture trigger to 16-bit timers 02, 04, 06, and 13 to 17.
(b) TO02 (P50), TO04 (P51), TO06 (P52) and TO13 (P53) to TO17 (P57)
These are the timer output pins of 16-bit timers 02, 04, 06 and 13 to 17.
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(c) SO01 (P54), SO10 (P53)
These are the serial data output pins of serial interface CSI01 and CSI10.
(d) SI01 (P55), SI10 (P52)
These are the serial data input pins of serial interface CSI01 and CSI10.
(e) SCK01 (P56), SCK10 (P51)
These are the serial clock I/O pins of serial interface CSI01 and CSI10.
(f) SDA11 (P50)
2
This is a serial data I/O pin of serial interface for simplified I C.
(g) SEG2 (P54) to SEG5 (P57), SEG49 (P50) to SEG52 (P53)
These are the segment signal output pins for the LCD controller/driver.
2.2.7 P60 to P66 (port6)
48-pin products:
64-pin products:
80-pin products:
100-pin products:
128-pin products:
P60 and P61 function as a 2-bit I/O port.
P60 and P61 function as a 2-bit I/O port.
P60, P61, P65, and P66 function as a 4-bit I/O port.
P60 to P66 function as a 7-bit I/O port.
P60 to P66 function as a 7-bit I/O port.
These pins also function as serial interface data I/O, timer I/O, real-time clock correction clock output, clock / buzzer
output, and external interrupt request input.
Input to the P61 and P63 pins can be specified through a normal Schmitt3 input buffer or a Schmitt1 input buffer in 1-bit
units, using port input mode register 6 (PIM6).
Output from the P60 and P61 pins can be specified as normal CMOS output or N-ch open-drain output (VDD tolerance)
in 1-bit units, using port output mode register 6 (POM6).
The following operation modes can be specified in 1-bit units.
(1) Port mode
48-pin products:
64-pin products:
80-pin products:
100-pin products:
128-pin products:
P60 and P61 function as a 2-bit I/O port.
P60 and P61 function as a 2-bit I/O port.
P60, P61, P65, and P66 function as a 4-bit I/O port.
P60 to P66 function as a 7-bit I/O port.
P60 to P66 function as a 7-bit I/O port.
P60 to P66 can be set to input or output port in 1-bit units using port mode register 6 (PM6). Use of an on-chip pull-up
resistor can be specified by pull-up resistor option register 6 (PU6).
(2) Control mode
P60 to P66 function as serial interface data I/O, timer I/O, real-time clock correction clock output, clock / buzzer output,
and external interrupt request input.
(a) TI20 (P60), TI21 (P61), TI24 (P66), TI25 (P65), TI26 (P63) and TI27 (P62)
These are the pins for inputting an external count clock/capture trigger to 16-bit timers 20, 21, and 24 to 27.
(b) TO20 (P60), TO21 (P61), TO24 (P66), TO25 (P65), TO26 (P63) and TO27 (P62)
These are the timer output pins of 16-bit timers 20, 21, and 24 to 27.
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(c) SCL11 (P60)
This is a serial clock output pin of serial interface for simplified I2C.
(d) SDA11 (P61)
2
This is a serial data I/O pin of serial interface for simplified I C.
(e) RTC1HZ (P64)
This is a real-time clock correction clock (1 Hz) output pin.
(f)
PCL (P66)
This is a clock/buzzer output pin.
(g) INTP1 (P60) and INTP3 (P61)
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
2.2.8 P70 to P75 (port7)
P70 to P75 function as a 6-bit I/O port.
These pins also function as A/D conversion start trigger input, output pins for the sound generator, serial interface data
I/O, timer I/O, clock / buzzer output, flash memory programming I/O, external interrupt request input, and segment signal
outputs for the LCD controller/driver.
Input to the P70 pin can be specified through a normal Schmitt3 input buffer or a Schmitt1 input buffer, using port input
mode register 7 (PIM7).
The following operation modes can be specified in 1-bit units.
(1) Port mode
P70 to P75 function as a 6-bit I/O port.
P70 to P75 can be set to input or output port in 1-bit units using port mode register 7 (PM7). Use of an on-chip pull-up
resistor can be specified by pull-up resistor option register 7 (PU7).
(2) Control mode
P70 to P75 function as an I/O port. These pins also function as A/D conversion trigger input, output pins for the sound
generator, serial interface data I/O, timer I/O, clock / buzzer output, flash memory programming I/O, external interrupt
request input, and segment signal outputs for the LCD controller/driver.
(a) ADTRG (P72)
This is an external input pin for AD conversion start trigger.
(b) SGO (P73)
This is an output pin for the sound generator.
(c) SGOA (P72)
This is an amplitude PWM output pin for the sound generator.
(d) SGOF (P73)
This is a frequency output pin for the sound generator.
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(e) TI03 (P70), TI22 (P75), and TI23 (P74)
These are the pins for inputting an external count clock/capture trigger to 16-bit timers03, 22, and 23.
(f) TO03 (P70), TO22 (P75), and TO23 (P74)
These are the timer output pins of 16-bit timers 03, 22, and 23.
(g) CTxD0 (P71)
This is a CAN serial transmit data output pin of aFCAN0.
(h) CRxD0 (P70)
This is a CAN serial receive data input pin of aFCAN0.
(i)
SCK01 (P74)
This is a serial clock I/O pin of serial interface CSI01.
(j)
SI01 (P75)
This is a serial data input pin of serial interface CSI01.
(k) LTXD0 (P71)
This is a Serial data output from LIN-UART.
(l)
LRxD0 (P70)
This is a Serial data input to LIN-UART.
(m) PCL (P75)
This is a clock/buzzer output pin.
(n) TOOLTxD (P71)
This UART serial data output pin for an external device connection is used during flash memory programming.
(o) TOOLRxD (P70)
This UART serial data input pin for an external device connection is used during flash memory programming.
(p) INTPLR0 (P70)
This is an external interrupt request input for which the valid edge for LIN-UART0.
(q) SEG0 (P73), SEG1 (P72), SEG26 (P74), and SEG27 (P75)
These are the segment signal output pins for the LCD controller/driver.
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2.2.9 P80 to P87 (port8)
48-pin products:
P80 to P83 function as an 4-bit I/O port.
64-pin products:
P80 to P87 function as an 8-bit I/O port.
80-pin products:
P80 to P87 function as an 8-bit I/O port.
100-pin products:
P80 to P87 function as an 8-bit I/O port.
128-pin products:
P80 to P87 function as an 8-bit I/O port.
These pins also function as timer I/O, stepper motor controller/driver outputs/inputs, and segment signal outputs for the
LCD controller/driver.
The following operation modes can be specified in 1-bit units.
(1) Port mode
48-pin products:
P80 to P83 function as an 4-bit I/O port.
64-pin products:
P80 to P87 function as an 8-bit I/O port.
80-pin products:
P80 to P87 function as an 8-bit I/O port.
100-pin products:
P80 to P87 function as an 8-bit I/O port.
128-pin products:
P80 to P87 function as an 8-bit I/O port.
P80 to P87 can be set to input or output port in 1-bit units using port mode register 8 (PM8). Use of an on-chip pull-up
resistor can be specified by pull-up resistor option register 8 (PU8).
(2) Control mode
P80 to P87 function as timer I/O, stepper motor controller/driver outputs/inputs, and segment signal outputs for the
LCD controller/driver.
(a) TI01 (P80), TI03 (P81), TI05 (P82), TI07 (P83), TI11 (P84), TI13 (P85), TI15 (P86), and TI17 (P87)
These are the pins for inputting an external count clock/capture trigger to 16-bit timers01, 03, 05, 07, 11, 13, 15,
and 17.
(b) TO01 (P80), TO03 (P81), TO05 (P82), TO07 (P83), TO11 (P84), TO13 (P85), TO15 (P86), and TO17 (P87)
These are the timer output pins of 16-bit timers 01, 03, 05, 07, 11, 13, 15, and 17.
(c) SM11 (P80) to SM14 (P83) and SM21 (P84) to SM24 (P87)
These are the output pins for the stepper motor controller/driver.
(d) ZPD14 (P83), ZPD24 (P87)
These are the Zero Point Detection (ZPD) input pins for the stepper motor controller/driver.
(e) SEG32 (P80) to SEG39 (P87)
These are the segment signal output pins for the LCD controller/driver.
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2.2.10 P90 to P97 (port9)
48-pin products:
P90 to P94 function as a 5-bit I/O port.
64-pin products:
P90 to P94 function as a 5-bit I/O port.
80-pin products:
P90 to P97 function as an 8-bit I/O port.
100-pin products:
P90 to P97 function as an 8-bit I/O port.
128-pin products:
P90 to P97 function as an 8-bit I/O port.
These pins also function as timer I/O, output pins for the sound generator, stepper motor controller/driver outputs/inputs,
real-time clock correction clock output, and segment signal outputs for the LCD controller/driver.
The following operation modes can be specified in 1-bit units.
(1) Port mode
48-pin products:
P90 to P94 function as a 5-bit I/O port.
64-pin products:
P90 to P94 function as a 5-bit I/O port.
80-pin products:
P90 to P97 function as an 8-bit I/O port.
100-pin products:
P90 to P97 function as an 8-bit I/O port.
128-pin products:
P90 to P97 function as an 8-bit I/O port.
P90 to P97 can be set to input or output port in 1-bit units using port mode register 9 (PM9). Use of an on-chip pull-up
resistor can be specified by pull-up resistor option register 9 (PU9).
(2) Control mode
P90 to P97 function as timer I/O, output pins for the sound generator, stepper motor controller/driver outputs/inputs,
real-time clock correction clock output, and segment signal outputs for the LCD controller/driver.
(a) TI01 (P94), TI03 (P95), TI05 (P96), TI07 (P97), TI21 (P90), TI23 (P91), TI25 (P92), and TI27 (P93)
These are the pins for inputting an external count clock/capture trigger to 16-bit timers01, 03, 05, 07, 21, 23, 25,
and 27.
(b) TO01 (P94), TO03 (P95), TO05 (P96), TO07 (P97), TO21 (P90), TO23 (P91), TO25 (P92), and TO27 (P93)
These are the timer output pins of 16-bit timers01, 03, 05, 07, 21, 23, 25, and 27.
(c) SGO (P93)
This is the output pin for the sound generator.
(d) SGOA (P92)
This is the amplitude PWM output pin for the sound generator.
(e) SGOF (P93)
This is the frequency output pin for the sound generator.
(f)
SM31 (P90) to SM34 (P93) and SM41 (P94) to SM44 (P97) (80-pin and 100-pin product)
These are the output pins for the stepper motor controller/driver.
(g) ZPD34 (P93), ZPD44 (P97) (80-pin and 100-pin product)
These are the Zero Point Detection (ZPD) input pins for the stepper motor controller/driver.
(h) RTC1HZ (P94)
This is a real-time clock correction clock (1 Hz) output pin.
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SEG40 (P90) to SEG47 (P97)
These are the segment signal output pins for the LCD controller/driver.
2.2.11 P100 to P107 (port10)
48-pin products:
Not provided
64-pin products:
Not provided
80-pin products:
Not provided
100-pin products:
Not provided
128-pin products:
P100 to P107 function as an 8-bit I/O port.
These pins also function as timer I/O, and segment signal outputs for the LCD controller/driver.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P100 to P107 function as an 8-bit I/O port.
P100 to P107 can be set to input or output port in 1-bit units using port mode register 10 (PM10). Use of an on-chip
pull-up resistor can be specified by pull-up resistor option register 9 (PU10).
(2) Control mode
P100 to P107 function as timer I/O, and segment signal outputs for the LCD controller/driver.
(a) TI24 (P100) to TI27 (P103) , and TI01 (P104), TI02 (P105), TI05 (P106), and TI06 (P107)
These are the pins for inputting an external count clock/capture trigger to 16-bit timers 24 to 27, and 01, 02, 05,
06.
(b) TO24 (P100) to TO27 (P103) , and TO01 (P104), TO02 (P105), TO05 (P106), and TO06 (P107)
These are the timer output pins of 16-bit timers 24 to 27, and 01, 02, 05, 06.
(c) SEG36 (P100) to SEG39 (P103), and SEG44 (P104) to SEG47 (P107)
These are the segment signal output pins for the LCD controller/driver.
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2.2.12 P110 to P117 (port 11)
48-pin products:
Not provided
64-pin products:
Not provided
80-pin products:
Not provided
100-pin products:
Not provided
128-pin products:
P110 to P117 function as an 8-bit I/O port.
These pins also function as LCD Bus I/F data lines I/O, timer I/O, serial interface data I/O, and segment signal outputs
for the LCD controller/driver.
Input can be specified through a normal Schmitt3 input buffer or a Schmitt1 input buffer in 1-bit units, using port input
mode register 0 (PIM0).
The following operation modes can be specified in 1-bit units.
(1) Port mode
P110 to P117 function as an 8-bit I/O port.
P110 to P117 can be set to input or output port in 1-bit units using port mode register 0 (PM11). Use of an on-chip
pull-up resistor can be specified by pull-up resistor option register 0 (PU11).
(2) Control mode
P00 to P07 function as LCD Bus I/F data lines I/O, timer I/O, serial interface data I/O, and segment signal outputs for
the LCD controller/driver.
(a) DBD0 (P110) to DBD7 (P117)
These are the I/O pin of LCD Bus I/F data lines 0 to 7.
(b) TI00 (P110), TI02 (P111), TI04 (P112), TI06 (P113), TI07 (P114), TI10 (P115), TI12 (P116), and TI20 (P117)
These are the external count clock input /capture trigger to 16-bit timer 00, 02, 04, 07, 10, 12, 20.
(b) TO00 (P110), TO02 (P111), TO04 (P112), TO06 (P113), TO07 (P114), TO10 (P115), TO12 (P116), and TO20
(P117)
These are the timer output pins of 16-bit timers 00, 02, 04, 07, 10, 12, 20.
(c) SO00 (P112)
This is a serial data output pin of serial interface CSI00.
(d) SI00 (P111)
This is a serial data input pin of serial interface CSI00.
(e) SCK00 (P110)
This is a serial clock I/O pin of serial interface CSI00.
(f) SEG28 (P117) to SEG35 (P110)
These are the segment signal output pins for the LCD controller/driver.
(g) TxD0 (P112)
This is a serial data output pin of serial interface UART0.
(h) RxD0 (P111)
This is a serial data input pin of serial interface UART0.
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2.2.13 P121 to P127 (port12)
48-pin products:
P121 to P122 function as a 2-bit Input port.
64-pin products:
P121 to P124 function as a 4-bit Input port.
80-pin products:
P121 to P124 function as a 4-bit Input port.
100-pin products:
P121 to P124 function as a 4-bit Input port.
128-pin products:
P121 to P124 function as a 4-bit Input port, P125 to P127 function as a 3-bit I/O port.
These pins also function as external clock input for main system clock, external clock input for subsystem clock, timer
I/O, and segment signal outputs for the LCD controller/driver.
The following operation modes can be specified in 1-bit units.
(1) Port mode
48-pin products:
64-pin products:
80-pin products:
100-pin products:
128-pin products:
P121 to P122 function as a 2-bit Input port.
P121 to P124 function as a 4-bit Input port.
P121 to P124 function as a 4-bit Input port.
P121 to P124 function as a 4-bit Input port.
P121 to P124 function as a 4-bit Input port, P125 to P127 function as a 3-bit I/O port.
(2) Control mode
P121 to P127 function as external clock input for main system clock, external clock input for subsystem clock, timer
I/O, and segment signal outputs for the LCD controller/driver.
(a) X1 (P121), X2 (P122)
These are the pins for connecting a resonator for main system clock.
(b) EXCLK (P122)
This is an external clock input pin for main system clock.
(c) XT1 (P123), XT2 (P124)
These are the pins for connecting a resonator for subsystem clock.
(d) TI12 (P125), TI14 (P126), and TI16 (P127)
These are the external count clock input /capture trigger to 16-bit timer 12, 14, 16.
(e) TO12 (P125), TO14 (P126), and TO16 (P127)
These are the timer output pins of 16-bit timers 12, 14, 16.
(f) SEG23 (P127) to SEG25 (P125)
These are the segment signal output pins for the LCD controller/driver.
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2.2.14 P130 to P137 (port13)
48-pin products:
P137 functions as a 1-bit Input port.
64-pin products:
P137 functions as a 1-bit Input port.
80-pin products:
P137 functions as a 1-bit Input port.
100-pin products:
P130 functions as a 1-bit Output port, P131 to P136 function as a 6-bit I/O port, and P137
128-pin products:
P130 functions as a 1-bit Output port, P131 to P136 function as a 6-bit I/O port, and P137
functions as a 1-bit Input port.
functions as a 1-bit Input port.
These pins also function as timer I/O, output pins for the sound generator, serial interface data I/O ,and segment signal
outputs for the LCD controller/driver.
Input to the P135 pin can be specified through a normal Schmitt3 input buffer or a Schmitt1 input buffer, using port
input mode register 13 (PIM13).
Output from the P136 pin can be specified as normal CMOS output or N-ch open-drain output (VDD tolerance), using
port output mode register (POM).
The following operation modes can be specified in 1-bit units.
(1) Port mode
48-pin products:
P137 functions as a 1-bit Input port.
64-pin products:
P137 functions as a 1-bit Input port.
80-pin products:
P137 functions as a 1-bit Input port.
100-pin products:
P130 functions as a 1-bit Output port, P131 to P136 function as a 6-bit I/O port, and P137
functions as a 1-bit Input port.
128-pin products:
P130 functions as a 1-bit Output port, P131 to P136 function as a 6-bit I/O port, and P137
functions as a 1-bit Input port.
P131 to P136 can be set to input or output port, in 1-bit units using port mode register 13 (PM13). Use of an on-chip
pull-up resistor can be specified by pull-up resistor option register 13 (PU13).
(2) Control mode
P131 to P137 function as timer I/O, output pins for the sound generator, serial interface data I/O, external interrupt
request input, and segment signal outputs for the LCD controller/driver.
(a) RESOUT (P130)
This is the reset output signal pin.
(b) TI00 (P136), TI20 (P132), TI21 (P131), TI22 (P133), TI24 (P134), and TI26 (P135)
These are the pins for inputting an external count clock/capture trigger to 16-bit timers00, 20, 21, 22, 24, and 26.
(c) TO00 (P136), TO20 (P132), TO21 (P131), TO22 (P133), TO24 (P134), and TO26 (P135)
These are the timer output pins of 16-bit timers00, 20, 21, 22, 24, and 26.
(d) SGO (P135)
This is the output pin for the sound generator.
(e) SGOA (P134)
This is the amplitude PWM output pin for the sound generator.
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CHAPTER 2 PIN FUNCTIONS
SGOF (P135)
This is the frequency output pin for the sound generator.
(g) SO10 (P131)
This is a serial data output pin of serial interface CSI10.
(h) SI10 (P132)
This is a serial data input pin of serial interface CSI10.
(i)
SCK10 (P133)
This is a serial clock I/O pin of serial interface CSI10.
(j)
LTxD1 (P131)
This is a Serial data output from LIN-UART.
(k) LRxD0 (P132)
This is a Serial data input to LIN-UART.
(l)
SCL11 (P136)
This is a serial clock output pin of serial interface for simplified I2C.
(m) CTxD1 (P134) (R5F10DPJxFB and R5F10DSJxFB only)
This is a CAN serial transmit data output pin of aFCAN1.
(n) CRxD1 (P135) (R5F10DPJxFB and R5F10DSJxFB only)
This is a CAN serial receive data input pin of aFCAN1.
(o) INTP5 (P137)
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and
falling edges) can be specified.
(p) INTPLR1 (P132)
This is an external interrupt request input for which the valid edge for LIN-UART1.
(q) SEG48 (P136)
This is a segment signal output pin for the LCD controller/driver.
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2.2.15 P140 (port14)
48-pin products:
Not provided
64-pin products:
Not provided
80-pin products:
Not provided
100-pin products:
P140 functions as a 1-bit I/O port.
128-pin products:
P140 functions as a 1-bit I/O port.
This pin also functions as timer I/O.
(1) Port mode
P140 functions as a 1-bit I/O port.
P140 can be set to input or output port, using port mode register 14 (PM14). Use of an on-chip pull-up resistor can be
specified by pull-up resistor option register 14 (PU14).
(2) Control mode
P140 functions as a 1-bit I/O port.
(a) TI11 (P140)
This is a pin for inputting an external count clock/capture trigger to 16-bit timers11.
(b) TO11 (P140)
This is a timer output pin of 16-bit timers11.
2.2.16 P150 to P152 (port15)
48-pin products:
Not provided
64-pin products:
Not provided
80-pin products:
Not provided
100-pin products:
P150 functions as a 1-bit I/O port.
128-pin products:
P150 to P152 functions as a 3-bit I/O port.
This pin also functions as A/D converter analog input.
(1) Port mode
100-pin products:
P150 functions as a 1-bit I/O port.
128-pin products:
P150 to P152 functions as a 3-bit I/O port.
P150 to P152 can be set to input or output port, using port mode register 15 (PM15).
(2) Control mode
P150 to P152 function as A/D converter analog inputs.
(a) ANI8 (P150) to ANI10 (P152)
These are the analog input pins of A/D converter.
2.2.17 COM0 to COM3
These are the common signal output pins for the LCD controller/driver.
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2.2.18 VDD, EVDD0, EVDD1, SMVDD0, SMVDD1, VSS, EVSS0, EVSS1, SMVSS0, SMVSS1
(1) VDD, EVDD, EVDD0, EVDD1
When using the 48-pin products, VDD is the positive power supply pin for P20 to P23, P27, P121 to P122, P137,
_____________
RESET. When using the 64-pin products, VDD is the positive power supply pin for P20 to P23, P27, P121 to P124,
_____________
P137, RESET
When using the 80-pin products, VDD is the positive power supply pin for P20 to P27, P121 to P124,
_____________
P137, RESET. When using the 100-pin products, VDD is the positive power supply pin for P20 to P27, P121 to P124,
_____________
P137, P150, RESET.
EVDD, EVDD0, EVDD1 are the positive power supply pins for the other than VDD, SMVDD, SMVDD0, SMVDD1.
(2) SMVDD, SMVDD0, SMVDD1
When using the 48-pin products, SMVDD is the positive power supply pin for P80 to P83, P90 to P94. When using the
64-pin products, SMVDD is the positive power supply pin for P80 to P87, P90 to P94. When using the 80-pin, 100-pin
products, SMVDD0, SMVDD1 are the positive power supply pins for P80 to P87, P90 to P97.
(3) VSS, EVSS, EVSS0, EVSS1
_____________
When using the 48-pin products, VSS is the ground potential pin for P20 to P23, P27, P121 to P122, P137, RESET.
_____________
When using the 64-pin products, VSS is the ground potential pin for P20 to P23, P27, P121 to P124, P137, RESET.
____________
When using the 80-pin products, VSS is the ground potential pin for P20 to P27, P121 to P124, P137, RESET. When
_____________
using the 100-pin products, VSS is the ground potential pin for P20 to P27, P121 to P124, P137, P150, RESET.
EVSS, EVSS0, EMVSS1 are the ground potential pins for the other than VSS, SMVSS, SMVSS0, SMVSS1.
(4) SMVSS, SMVSS0, SMVSS1
When using the 48-pin products, SMVSS is the ground potential pin for P80 to P83, P90 to P94. When using the 64pin products, SMVSS is the ground potential pin for P80 to P87, P90 to P94. When using the 80-pin, 100-pin products,
SMVSS0, SMVSS1 are the ground potential pins for P80 to P87, P90 to P97.
2.2.19 RESET
This is the active-low system reset input pin.
When the external reset pin is not used, connect this pin directly or via a resistor to VDD.
When the external reset pin is used, design the circuit based on VDD.
2.2.20 REGC
This is the pin for connecting regulator output stabilization capacitance for internal operation. Connect this pin to VSS via
a capacitor (0.47 to 1 μF).
Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage.
REGC
VSS
Caution Keep the wiring length as short as possible for the broken-line part in the above figure.
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2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-7 shows the types of pin I/O circuits and the recommended connections of unused pins.
Table 2-7. Connection of Unused Pins (1/15)
(a) R5F10CGBxFB, R5F10CGCxFB, R5F10CGDxFB, R5F10DGCxFB, R5F10DGDxFB, R5F10DGExFB (1/2)
Pin Name
P00/TI00/TO00/CTxD0/SEG14
I/O Circuit Type
17-W
P01/TI01/TO01/CRxD0/SEG15
17-AD
P10/LTxD1/SCK00/TI10/TO10/
INTP4/SEG31
17-AD
I/O
I/O
Recommended Connection of Unused Pins
Input: Independently connect to EVSS via a resistor.
Output: Leave open.
P11/LRxD1/INTPLR1/SI00/TI11/TO11/
SEG30
P12/SO00/TI12/TO12/INTP2/SEG29
17-W
P13/SO01/TI13/TO13/SEG25
P14/TI14/TO14/LRxD0/INTPLR0/SEG24
P20/AVREFP/ANI0
11-AA
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P21/AVREFM/ANI1
P22/ANI2, P23/ANI3, P27/ANI7
11-Z
P30/TI20/TO20/SCL11/SEG6
17-W
Input: Independently connect to EVSS via a resistor.
P31/TI21/TO21/SDA11/SEG7
17-AD
Output: Leave open.
P33/TI23/TO23/SI00/SEG9
17-W
P40/TOOL0
5-AH
Note
Input: Independently connect to EVDD or leave open.
Output: Leave open.
P54/TI14/TO14/SO01/SEG2
17-W
Input: Independently connect to EVSS via a resistor.
P55/TI15/TO15/SI01/SEG3
17-AD
Output: Leave open.
P60/SCL11/TI20/TO20/INTP1
5-AH
P61/SDA11/TI21/TO21/INTP3
5-BA
Input: Independently connect to EVDD or EVSS via a
resistor.
P72/ADTRG/SGOA/SEG1
17-W
P56/TI16/TO16/SCK01/SEG4
P57/TI17/TO17 /SEG5
Output: Leave open.
Input: Independently connect to EVSS via a resistor.
Output: Leave open.
P73/SGO/SGOF/SEG0
P74/SCK01/TI23/TO23/SEG26
P75/PCL/SI01/TI22/TO22/SEG27
P80/SM11/TI01/TO01/SEG32
17-W
Input: Independently connect to SMVSS via a resistor.
Output: Leave open.
P81/SM12/TI03/TO03/SEG33
P82/SM13/TI05/TO05/SEG34
P83/SM14/ZPD14/TI07/TO07/SEG35
17-AE
P90/SM31/TI21/TO21/SEG40
17-W
P91/SM32/TI23/TO23/SEG41
P92/SM33/TI25/TO25/SGOA/SEG42
P93/SM34/ZPD34/TI27/TO27/SGO
/SGOF/SEG43
17-AE
P94/SM41/TI01/TO01/RTC1HZ/SEG44
17-W
P121/X1
37-C
Input
Independently connect to VDD or VSS via a resistor.
P122/X2/EXCLK
P137/INTP5
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Table 2-7. Connection of Unused Pins (2/15)
(a) R5F10CGBxFB, R5F10CGCxFB, R5F10CGDxFB, R5F10DGCxFB, R5F10DGDxFB, R5F10DGExFB (2/2)
Pin Name
COM0 to COM3
I/O Circuit Type
I/O
Recommended Connection of Unused Pins
18-G
Output
Leave open
RESET
2
Input
Connect directly or via a resistor to VDD.
REGC
-
____________
-
Connect to VSS via capacitor (0.47 to 1 μF).
Note Input NAND is Schmitt1. In only OCD mode, NOD can be selected
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Table 2-7. Connection of Unused Pins (3/15)
(b) R5F10CLDxFB, R5F10DLDxFB, R5F10DLExFB (1/2)
Pin Name
I/O Circuit Type
P00/TI00/TO00/CTxD0/SEG14
17-W
P01/TI01/TO01/CRxD0/SEG15
17-AD
P02/SO00/TI02/TO02/TI12/TO12/SEG16
17-W
I/O
I/O
Recommended Connection of Unused Pins
Input: Independently connect to EVSS via a resistor.
Output: Leave open.
P03/SI00/TI03/TO03/TI13/TO13/SEG17
P04/SCK00/TI04/TO04/TI14/TO14/SEG18
P05/TI05/TO05/TI15/TO15/SEG19
P07/TI07/TO07/TI17/TO17/SEG21
P10/LTxD1/SCK00/TI10/TO10/INTP4/
17-AD
SEG31
P11/LRxD1/INTPLR1/SI00/TI11/TO11/
SEG30
P12/SO00/TI12/TO12/INTP2/SEG29
17-W
P13/SO01/TI13/TO13/SEG25
P14/TI14/TO14/LRxD0/INTPLR0/
SEG24
P15/TI15/TO15/LTxD0/RTC1HZ/SEG23
P17/TI17/TO17/INTP0/SEG28
17-AD
P20/AVREFP/ANI0
11-AA
Input: Independently connect to VDD or VSS via a
resistor.
P21/AVREFM/ANI1
Output: Leave open.
P22/ANI2, P23/ANI3, P27/ANI7
11-Z
P30/TI20/TO20/SCL11/SEG6
17-W
Input: Independently connect to EVSS via a resistor.
P31/TI21/TO21/SDA11/SEG7
17-AD
Output: Leave open.
P32/TI22/TO22/SEG8
17-W
P33/TI23/TO23/SEG9
P40/TOOL0
Note
5-AH
Input: Independently connect to EVDD or leave open.
Output: Leave open.
P54/TI14/TO14/SO01/SEG2
17-W
Input: Independently connect to EVSS via a resistor.
P55/TI15/TO15/SI01/SEG3
17-AD
Output: Leave open.
P56/TI16/TO16/SCK01/SEG4
P57/TI17/TO17/ SEG5
P60/SCL11/TI20/TO20/INTP1
5-AH
Input: Independently connect to EVDD or EVSS via a
P61/SDA11/TI21/TO21/INTP3
5-BA
resistor.
Output: Leave open.
Note Input NAND is Schmitt1. In only OCD mode, NOD can be selected
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CHAPTER 2 PIN FUNCTIONS
Table 2-7. Connection of Unused Pins (4/15)
(b) R5F10CLDxFB, R5F10DLDxFB, R5F10DLExFB (2/2)
Pin Name
P70/CRxD0/LRxD0/INTPLR0/TI03/
I/O Circuit Type
5-BA
I/O
Recommended Connection of Unused Pins
Input: Independently connect to EVDD or EVSS via a resistor.
I/O
TO03/TOOLRXD
Output: Leave open.
P71/CTxD0/LTxD0/TOOLTXD
5-AH
P72/ADTRG/SGOA/SEG1
17-W
Input: Independently connect to EVSS via a resistor.
Output: Leave open.
P73/SGO/SGOF/SEG0
P74/SCK01/TI23/TO23/SEG26
P75/PCL/SI01/TI22/TO22/SEG27
P80/SM11/TI01/TO01/SEG32
17-W
Input: Independently connect to SMVSS via a resistor.
Output: Leave open.
P81/SM12/TI03/TO03/SEG33
P82/SM13/TI05/TO05/SEG34
P83/SM14/ZPD14/TI07/TO07/SEG35
17-AE
P84/SM21/TI11/TO11/SEG36
17-W
P85/SM22/TI13/TO13/SEG37
P86/SM23/TI15/TO15/SEG38
P87/SM24/ZPD24/TI17/TO17/SEG39
17-AE
P90/TI21/TO21/SEG40
17-W
P91/TI23/TO23/SEG41
P92/TI25/TO25/SGOA/SEG42
P93/TI27/TO27/SGO/SGOF/SEG43
P94/TI01/TO01/RTC1HZ/SEG44
P121/X1
37-C
Input
Independently connect to VDD or VSS via a resistor.
P122/X2/EXCLK
P123/XT1
P124/XT2
P137/INTP5
2-H
COM0 to COM3
18-G
Output
Leave open
RESET
2
Input
Connect directly or via a resistor to VDD.
REGC
-
____________
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
-
Connect to VSS via capacitor (0.47 to 1 μF).
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CHAPTER 2 PIN FUNCTIONS
Table 2-7. Connection of Unused Pins (5/15)
(c) R5F10CMDxFB, R5F10CMExFB, R5F10DMDxFB, R5F10DMExFB, R5F10DMFxFB, R5F10DMGxFB,
R5F10DMJxFB (1/2)
Pin Name
P00/TI00/TO00/CTxD0/SEG14
I/O Circuit Type
17-W
P01/TI01/TO01/CRxD0/SEG15
17-AD
P02/SO00/TI02/TO02/TI12/TO12/
SEG16
17-W
I/O
I/O
Recommended Connection of Unused Pins
Input: Independently connect to EVSS via a resistor.
Output: Leave open.
P03/SI00/TI03/TO03/TI13/TO13/SEG17
P04/SCK00/TI04/TO04/TI14/TO14/
SEG18
P05 /TI05/TO05/TI15/TO15/
SEG19
P06/TI06/TO06/TI16/TO16/SEG20
P07/TI07/TO07/TI17/TO17/SEG21
P10/LTxD1/SCK00/TI10/TO10/INTP4/
SEG31
17-AD
P11/LRxD1/INTPLR1/SI00/TI11/TO11/
SEG30
P12/SO00/TI12/TO12/INTP2/SEG29
17-W
P13/SO01/TI13/TO13/SEG25
P14/TI14/TO14/LRxD0/INTPLR0/
SEG24
P15/TI15/TO15/LTxD0/RTC1HZ/SEG23
P16/TI16/TO16/SEG22
P17/ TI17/TO17/INTP0/SEG28
17-AD
P20/AVREFP/ANI0
11-AA
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P21/AVREFM/ANI1
P22/ANI2 to P27/ANI7
11-Z
P30/TI20/TO20/SCL11/SEG6
17-W
Input: Independently connect to EVSS via a resistor.
P31/TI21/TO21/SDA11/SEG7
17-AD
Output: Leave open.
P32/TI22/TO22/SO00/SEG8
17-W
P33/TI23/TO23/SI00/SEG9
P34/TI24/TO24/SCK00/SEG10
P35/TI25/TO25/SEG11
P36/TI26/TO26/SEG12
P37/TI27/TO27/SEG13
P40/TOOL0
Note
5-AH
Input: Independently connect to EVDD or leave open.
Output: Leave open.
P54/TI14/TO14/SO01/SEG2
17-W
Input: Independently connect to EVSS via a resistor.
P55/TI15/TO15/SI01/SEG3
17-AD
Output: Leave open.
P60/SCL11/TI20/TO20/INTP1
5-AH
P61/SDA11/TI21/TO21/INTP3
5-BA
Input: Independently connect to EVDD or EVSS via a
resistor.
P65/TI25/TO25
5-AH
Output: Leave open.
P56/TI16/TO16/SCK01/SEG4
P57/TI17/TO17/SEG5
P66/TI24/TO24/PCL
Note Input NAND is Schmitt1. In only OCD mode, NOD can be selected
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
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CHAPTER 2 PIN FUNCTIONS
Table 2-7. Connection of Unused Pins (6/15)
(c) R5F10CMDxFB, R5F10CMExFB, R5F10DMDxFB, R5F10DMExFB, R5F10DMFxFB, R5F10DMGxFB,
R5F10DMJxFB (2/2)
Pin Name
P70/CRxD0/LRxD0/INTPLR0/TI03/
I/O Circuit Type
5-BA
I/O
I/O
Recommended Connection of Unused Pins
Input: Independently connect to EVDD or EVSS via a resistor.
TO03/TOOLRXD
Output: Leave open.
P71/CTxD0/LTxD0/TOOLTXD
5-AH
P72/ADTRG/SGOA/SEG1
17-W
Input: Independently connect to EVSS via a resistor.
Output: Leave open.
P73/SGO/SGOF/SEG0
P74/SCK01/TI23/TO23/SEG26
P75/PCL/SI01/TI22/TO22/SEG27
P80/SM11/TI01/TO01/SEG32
17-W
Input: Independently connect to SMVSS via a resistor.
Output: Leave open.
P81/SM12/TI03/TO03/SEG33
P82/SM13/TI05/TO05/SEG34
P83/SM14/ZPD14/TI07/TO07/SEG35
17-AE
P84/SM21/TI11/TO11/SEG36
17-W
P85/SM22/TI13/TO13/SEG37
P86/SM23/TI15/TO15/SEG38
P87/SM24/ZPD24/TI17/TO17/SEG39
17-AE
P90/SM31/TI21/TO21/SEG40
17-W
Input: Independently connect to SMVSS via a resistor.
Output: Leave open.
P91/SM32/TI23/TO23/SEG41
P92/SM33/TI25/TO25/SGOA/SEG42
P93/SM34/ZPD34/TI27/TO27/
17-AE
SGO/SGOF/SEG43
P94/SM41/TI01/TO01/RTC1HZ/
17-W
SEG44
P95/SM42/TI03/TO03/SEG45
P96/SM43/TI05/TO05/SEG46
P97/SM44/ZPD44/TI07/TO07/SEG47
17- AE
P121/X1
37-C
Input
Independently connect to VDD or VSS via a resistor.
P122/X2/EXCLK
P123/XT1
P124/XT2
P137/INTP5
2-H
COM0 to COM3
18-G
Output
Leave open
2
Input
Connect directly or via a resistor to VDD.
____________
RESET
REGC
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
-
-
Connect to VSS via capacitor (0.47 to 1 μF).
70
RL78/D1A
CHAPTER 2 PIN FUNCTIONS
Table 2-7. Connection of Unused Pins (7/15)
(d) R5F10DPExFB, R5F10DPFxFB, R5F10DPGxFB, R5F10TPJxFB (1/3)
Pin Name
I/O Circuit Type
P00/TI00/TO00/CTxD0/SEG14
17-W
P01/TI01/TO01/CRxD0/SEG15
17-AD
P02/SO00/TI02/TO02/TI12/TO12/
SEG16
17-W
I/O
I/O
Recommended Connection of Unused Pins
Input: Independently connect to EVSS via a resistor.
Output: Leave open.
P03/SI00/TI03/TO03/TI13/TO13/
SEG17
P04/SCK00/TI04/TO04/TI14/TO14/
SEG18
P05/TI05/TO05/TI15/TO15/
SEG19
P06/TI06/TO06/TI16/TO16/SEG20
P07/TI07/TO07/TI17/TO17/SEG21
P10/LTxD1/SCK00/TI10/TO10/
INTP4/SEG31
17-AD
P11/LRxD1/INTPLR1/SI00/TI11/TO11/
SEG30
P12/SO00/TI12/TO12/INTP2/SEG29
17-W
P13/SO01/TI13/TO13/SEG25
P14/TI14/TO14/LRxD0/INTPLR0/
SEG24
P15/TI15/TO15/LTxD0/RTC1HZ/SEG23
P16/TI16/TO16/SEG22
P17/TI17/TO17/INTP0/SEG28
17-AD
P20/AVREFP/ANI0
11-AA
P22/ANI2 to P27/ANI7
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P21/AVREFM/ANI1
11-Z
P30/TI20/TO20/SCL11/SEG6
17-W
Input: Independently connect to EVSS via a resistor.
P31/TI21/TO21/SDA11/SEG7
17-AD
Output: Leave open.
P32/TI22/TO22/SO00/SEG8
17-W
P33/TI23/TO23/SI00/SEG9
P34/TI24/TO24/SCK00/SEG10
P35/TI25/TO25/SEG11
P36/TI26/TO26/SEG12
P37/TI27/TO27/SEG13
P40/TOOL0
Note
5-AH
Input: Independently connect to EVDD or leave open.
Output: Leave open.
P50/TI02/TO02/SDA11/SEG49
17- AD
Input: Independently connect to EVSS via a resistor.
Output: Leave open.
P51/TI04/TO04/SCK10/SEG50
P52/TI06/TO06/SI10/SEG51
P53/TI13/TO13/SO10/SEG52
17-W
P54/TI14/TO14/SO01/SEG2
P55/TI15/TO15/SI01/SEG3
17-AD
P56/TI16/TO16/SCK01/SEG4
P57/TI17/TO17/SEG5
Note Input NAND is Schmitt1. In only OCD mode, NOD can be selected
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
71
RL78/D1A
CHAPTER 2 PIN FUNCTIONS
Table 2-7. Connection of Unused Pins (8/15)
(d) R5F10DPExFB, R5F10DPFxFB, R5F10DPGxFB, R5F10TPJxFB (2/3)
Pin Name
I/O Circuit Type
I/O
I/O
Recommended Connection of Unused Pins
P60/SCL11/TI20/TO20/INTP1
5-AH
P61/SDA11/TI21/TO21/INTP3
5-BA
Input: Independently connect to EVDD or EVSS via a
resistor.
P62/TI27/TO27
5-AH
Output: Leave open.
P63/TI26/TO26
5-BA
P64/RTC1HZ/TI11/TO11
5-AH
P65/TI25/TO25
P66/TI24/TO24/PCL
P70/CRxD0/LRxD0/INTPLR0/TI03/TO03/
TOOLRXD
5-BA
Input: Independently connect to EVDD or EVSS via a
resistor.
P71/CTxD0/LTxD0/TOOLTXD
5-AH
Output: Leave open.
P72/ADTRG/SGOA/SEG1
17-W
Input: Independently connect to EVSS via a resistor.
Output: Leave open.
P73/SGO/SGOF/SEG0
P74/SCK01/TI23/TO23/SEG26
P75/PCL/SI01/TI22/TO22/SEG27
P80/SM11/TI01/TO01/SEG32
17-W(2)
Input: Independently connect to SMVSS via a resistor.
Output: Leave open.
P81/SM12/TI03/TO03/SEG33
P82/SM13/TI05/TO05/SEG34
P83/SM14/ZPD14/TI07/TO07/SEG35
17-AE
P84/SM21/TI11/TO11/SEG36
17-W
P85/SM22/TI13/TO13/SEG37
P86/SM23/TI15/TO15/SEG38
P87/SM24/ZPD24/TI17/TO17/SEG39
17-AE
P90/SM31/TI21/TO21/SEG40
17-W
Input: Independently connect to SMVSS via a resistor.
Output: Leave open.
P91/SM32/TI23/TO23/SEG41
P92/SM33/TI25/TO25/SGOA/SEG42
P93/SM34/ZPD34/TI27/TO27/SGO/SGOF/
SEG43
17-AE
P94/SM41/TI01/TO01/RTC1HZ/SEG44
17-W
P95/SM42/TI03/TO03/SEG45
P96/SM43/TI05/TO05/SEG46
P97/SM44/ZPD44/TI07/TO07/SEG47
17-AE
P121/X1
37-C
Input
Independently connect to VDD or VSS via a resistor.
P130
3-C
Output
Leave open.
P131/SO10/LTxD1/TI21/TO21
5-AH
I/O
Input: Independently connect to EVDD or EVSS via a
resistor.
P122/X2/EXCLK
P123/XT1
P124/XT2
P132/SI10/LRxD1/INTPLR1/TI20/TO20
Output: Leave open.
P133/SCK10/TI22/TO22
P134/SGOA/TI24/TO24
P135/SGO/SGOF/TI26/TO26
5-BA
P136/TI00/TO00/SCL11/SEG48
17-W
Input: Independently connect to EVSS via a resistor.
Output: Leave open.
P137/INTP5
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
2-H
Input
Independently connect to VDD or VSS via a resistor.
72
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CHAPTER 2 PIN FUNCTIONS
Table 2-7. Connection of Unused Pins (9/15)
(d) R5F10DPExFB, R5F10DPFxFB, R5F10DPGxFB, R5F10TPJxFB (3/3)
Pin Name
P140/TI11/TO11
I/O Circuit Type
5-AH
I/O
I/O
Recommended Connection of Unused Pins
Input: Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P150/ANI8
11-Z
COM0 to COM3
18-G
Output
Leave open
RESET
2
Input
Connect directly or via a resistor to VDD.
REGC
-
____________
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
Independently connect to VDD or VSS via a resistor.
-
Connect to VSS via capacitor (0.47 to 1 μF).
73
RL78/D1A
CHAPTER 2 PIN FUNCTIONS
Table 2-7. Connection of Unused Pins (10/15)
(e) R5F10DPJxFB (1/3)
Pin Name
I/O Circuit Type
P00/TI00/TO00/CTxD0/SEG14
17-W
P01/TI01/TO01/CRxD0/SEG15
17-AD
P02/SO00/TI02/TO02/TI12/TO12/SEG16
17-W
I/O
I/O
Recommended Connection of Unused Pins
Input: Independently connect to EVSS via a resistor.
Output: Leave open.
P03/SI00/TI03/TO03/TI13/TO13/SEG17
P04/SCK00/TI04/TO04/TI14/TO14/
SEG18
P05/TI05/TO05/TI15/TO15/
SEG19
P06/TI06/TO06/TI16/TO16/SEG20
P07/TI07/TO07/TI17/TO17/SEG21
P10/LTxD1/SCK00/TI10/TO10/INTP4/
SEG31
17- AD
P11/LRxD1/INTPLR1/SI00/TI11/TO11/
SEG30
P12/SO00/TI12/TO12/INTP2/SEG29
17-W
P13/SO01/TI13/TO13/SEG25
P14/TI14/TO14/LRxD0/INTPLR0/
SEG24
P15/TI15/TO15/LTxD0/RTC1HZ/SEG23
P16/TI16/TO16/SEG22
P17/TI17/TO17/INTP0/SEG28
17-AD
P20/AVREFP/ANI0
11-AA
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P21/AVREFM/ANI1
P22/ANI2 to P27/ANI7
11-Z
P30/TI20/TO20/SCL11/SEG6
17-W
Input: Independently connect to EVSS via a resistor.
P31/TI21/TO21/SDA11/SEG7
17-AD
Output: Leave open.
P32/TI22/TO22/SO00/SEG8
17-W
P33/TI23/TO23/SI00/SEG9
P34/TI24/TO24/SCK00/SEG10
P35/TI25/TO25/SEG11
P36/TI26/TO26/SEG12
P37/TI27/TO27/SEG13
Note
P40/TOOL0
5-AH
P50/TI02/TO02/SDA11/SEG49
17-AD
Input: Independently connect to EVDD or leave open.
Output: Leave open.
Input: Independently connect to EVSS via a resistor.
Output: Leave open.
P51/TI04/TO04/SCK10/SEG50
P52/TI06/TO06/SI10/SEG51
P53/TI13/TO13/SO10/SEG52
17-W (1)
P54/TI14/TO14/SO01/SEG2
P55/TI15/TO15/SI01/SEG3
17-AD
P56/TI16/TO16/SCK01/SEG4
P57/TI17/TO17/SEG5
Note: Input NAND is Schmitt1. In only OCD mode, NOD can be selected
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
74
RL78/D1A
CHAPTER 2 PIN FUNCTIONS
Table 2-7. Connection of Unused Pins (11/15)
(e) R5F10DPJxFB (2/3)
Pin Name
I/O Circuit Type
I/O
I/O
Recommended Connection of Unused Pins
P60/SCL11/TI20/TO20/INTP1
5-AH
P61/SDA11/TI21/TO21/INTP3
5-BA
Input: Independently connect to EVDD or EVSS via a
resistor.
P62/CTxD1/TI27/TO27
5-AH
Output: Leave open.
P63/CRxD1/TI26/TO26
5-BA
P64/RTC1HZ/TI11/TO11
5-AH
P65/TI25/TO25
P66/TI24/TO24/PCL
P70/CRxD0/LRxD0/INTPLR0/TI03/TO03/
TOOLRXD
5-BA
Input: Independently connect to EVDD or EVSS via a
resistor.
P71/CTxD0/LTxD0/TOOLTXD
5-AH
Output: Leave open.
P72/ADTRG/SGOA/SEG1
17-W
Input: Independently connect to EVSS via a resistor.
Output: Leave open.
P73/SGO/SGOF/SEG0
P74/SCK01/TI23/TO23/SEG26
P75/PCL/SI01/TI22/TO22/SEG27
P80/SM11/TI01/TO01/SEG32
17-W
Input: Independently connect to SMVSS via a resistor.
Output: Leave open.
P81/SM12/TI03/TO03/SEG33
P82/SM13/TI05/TO05/SEG34
P83/SM14/ZPD14/TI07/TO07/SEG35
17-AE
P84/SM21/TI11/TO11/SEG36
17-W
P85/SM22/TI13/TO13/SEG37
P86/SM23/TI15/TO15/SEG38
P87/SM24/ZPD24/TI17/TO17/SEG39
17-AE
P90/SM31/TI21/TO21/SEG40
17-W
Input: Independently connect to SMVSS via a resistor.
Output: Leave open.
P91/SM32/TI23/TO23/SEG41
P92/SM33/TI25/TO25/SGOA/SEG42
P93/SM34/ZPD34/TI27/TO27/SGO/SGOF/
SEG43
17-AE
P94/SM41/TI01/TO01/RTC1HZ/SEG44
17-W
P95/SM42/TI03/TO03/SEG45
P96/SM43/TI05/TO05/SEG46
P97/SM44/ZPD44/TI07/TO07/SEG47
17-AE
P121/X1
37-C
Input
Independently connect to VDD or VSS via a resistor.
P130
3-C
Output
Leave open.
P131/SO10/LTxD1/TI21/TO21
5-AH
I/O
Input: Independently connect to EVDD or EVSS via a
resistor.
P122/X2/EXCLK
P123/XT1
P124/XT2
P132/SI10/LRxD1/INTPLR1/TI20/TO20
Output: Leave open.
P133/SCK10/TI22/TO22
P134/SGOA/CTxD1/TI24/TO24
P135/SGO/SGOF/CRxD1/TI26/TO26
5-BA
P136/TI00/TO00/SCL11/SEG48
17-W
Input: Independently connect to EVSS via a resistor.
Output: Leave open.
P137/INTP5
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
2-H
Input
Independently connect to VDD or VSS via a resistor.
75
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CHAPTER 2 PIN FUNCTIONS
Table 2-7. Connection of Unused Pins (12/15)
(e) R5F10DPJxFB (3/3)
Pin Name
P140/TI11/TO11
I/O Circuit Type
5-AH
I/O
I/O
Recommended Connection of Unused Pins
Input: Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P150/ANI8
COM0 to COM3
____________
RESET
REGC
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
11-Z
Independently connect to VDD or VSS via a resistor.
18-G
Output
Leave open
2
Input
Connect directly or via a resistor to VDD.
-
-
Connect to VSS via capacitor (0.47 to 1 μF).
76
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CHAPTER 2 PIN FUNCTIONS
Table 2-7. Connection of Unused Pins (13/15)
(f) R5F10DSJxFB, R5F10DSKxFB, R5F10DSLxFB (1/3)
Pin Name
P00/CTxD0/TI00/TO00/SEG14
I/O Circuit Type
17-W
P01/CRxD0/TI01/TO01/SEG15
17-AD
P02/SO00/TxD0/TI02/TO02/TI12/TO12/SEG16
17-W
I/O
I/O
Recommended Connection of Unused Pins
Input: Independently connect to EVSS via a resistor.
Output: Leave open.
P03/RxD0/TI03/TO03/TI13/TO13/SEG17
P04/SCK00/TI04/TO04/TI14/TO14/SEG18
P05/SI00/TI05/TO05/TI15/TO15/SEG19
P06/TI06/TO06/TI16/TO16/SEG20
P07/TI07/TO07/TI17/TO17/SEG21
P10/LTxD1/SCK00/TI10/TO10/INTP4/SEG31
17- AD
P11/LRxD1/INTPLR1/SI00/RxD0/TI11/TO11/
SEG30
P12/SO00/TxD0/TI12/TO12/INTP2/SEG29
17-W
P13/SO01/TI13/TO13/SEG25
P14/LRxD0/INTPLR0/TI14/TO14/SEG24
P15/LTxD0/RTC1HZ/TI15/TO15/SEG23
P16/TI16/TO16/SEG22
P17/TI17/TO17/INTP0/SEG28
17-AD
P20/AVREFP/ANI0
11-AA
Input: Independently connect to VDD or VSS via a
resistor.
11-Z
Output: Leave open.
P21/AVREFM/ANI1
P22/ANI2 to P27/ANI7
P30/TI20/TO20/SCL11/SEG6
17-W
Input: Independently connect to EVSS via a resistor.
P31/TI21/TO21/SDA11/SEG7
17-AD
Output: Leave open.
P32/TI22/TO22/SO00/TxD0/SEG8
17-W
P33/TI23/TO23/SI00/RxD0/SEG9
P34/TI24/TO24/SCK00/SEG10
P35/TI25/TO25/SEG11
P36/TI26/TO26/SEG12
P37/TI27/TO27/SEG13
P40/TOOL0
Note
5-AH
Input: Independently connect to EVDD or leave open.
Output: Leave open.
P41/STOPST/TI04/TO04
5-AH
P42/TI10/TO10/SEG7
17-W (1)
Input: Independently connect to EVDD or EVSS via a
resistor.
Output: Leave open.
P43/TI22/TO22/SEG14
Input: Independently connect to EVSS via a resistor.
Output: Leave open.
P44/TI23/TO23/SEG15
P45/SEG53
___________
P46/DBWR/SEG27
__________
P47/DBRD/SEG26
P50/TI02/TO02/SDA11/SEG49
P51/TI04/TO04/SCK10/SEG50
17-AD
Input: Independently connect to EVSS via a resistor.
Output: Leave open.
P52/TI06/TO06/SI10/SEG51
Note: Input NAND is Schmitt1. In only OCD mode, NOD can be selected
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Table 2-7. Connection of Unused Pins (14/15)
(f) R5F10DSJxFB, R5F10DSKxFB, R5F10DSLxFB (2/3)
Pin Name
P53/TI13/TO13/SO10/SEG52
I/O Circuit Type
17-W (1)
I/O
I/O
Input: Independently connect to EVSS via a resistor.
Output: Leave open.
P54/TI14/TO14/SO01/SEG2
P55/TI15/TO15/SI01/SEG3
Recommended Connection of Unused Pins
17-AD
P56/TI16/TO16/SCK01/SEG4
P57/TI17/TO17/SEG5
P60/SCL11/TI20/TO20/INTP1
5-AH
P61/SDA11/TI21/TO21/INTP3
5-BA
P62/CTxD1/TI27/TO27
5-AH
P63/CRxD1/TI26/TO26
5-BA
P64/RTC1HZ/TI11/TO11
5-AH
I/O
Input: Independently connect to EVDD or EVSS via a
resistor.
Output: Leave open.
P65/TI25/TO25
P66/TI24/TO24/PCL
P70/CRxD0/LRxD0/INTPLR0/TI03/TO03/TOOLRxD
5-BA
P71/CTxD0/LTxD0/TOOLTxD
5-AH
Input: Independently connect to EVDD or EVSS via a
resistor.
P72/SGOA/ADTRG/SEG1
17-W
Input: Independently connect to EVSS via a resistor.
Output: Leave open.
Output: Leave open.
P73/SGO/SGOF/SEG0
P74/SCK01/TI23/TO23/SEG26
P75/SI01/TI22/TO22/SEG27/PCL
P80/SM11/TI01/TO01/SEG32
17-W
P81/SM12/TI03/TO03/SEG33
Input: Independently connect to SMVSS via a
resistor.
Output: Leave open.
P82/SM13/TI05/TO05/SEG34
P83/SM14/ZPD14/TI07/TO07/SEG35
17-AE
P84/SM21/TI11/TO11/SEG36
17-W
P85/SM22/TI13/TO13/SEG37
P86/SM23/TI15/TO15/SEG38
P87/SM24/ZPD24/TI17/TO17/SEG39
17-AE
P90/SM31/TI21/TO21/SEG40
17-W
P91/SM32/TI23/TO23/SEG41
Input: Independently connect to SMVSS via a
resistor.
Output: Leave open.
P92/SM33/SGOA/TI25/TO25/SEG42
P93/SM34/ZPD34/SGO/SGOF/TI27/TO27/SEG43
17-AE
P94/SM41/RTC1HZ/TI01/TO01/SEG44
17-W
P95/SM42/TI03/TO03/SEG45
P96/SM43/TI05/TO05/SEG46
P97/SM44/ZPD44/TI07/TO07/SEG47
17-AE
P100/TI24/TO24/SEG36
17-W (1)
P101/TI25/TO25/SEG37
Input: Independently connect to EVSS via a resistor.
Output: Leave open.
P102/TI26/TO26/SEG38
P103/TI27/TO27/SEG39
P104/TI01/TO01/SEG44
P105/TI02/TO02/SEG45
P106/TI05/TO05/SEG46
P107/TI06/TO06/SEG47
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Table 2-7. Connection of Unused Pins (15/15)
(f) R5F10DSJxFB, R5F10DSKxFB, R5F10DSLxFB (3/3)
Pin Name
P110/DBD0/SCK00/TI00/TO00/SEG35
I/O Circuit Type
17-AD
I/O
I/O
Recommended Connection of Unused Pins
Input: Independently connect to EVSS via a resistor.
P111/DBD1/SI00/RxD0/TI02/TO02/SEG34
Output: Leave open.
P112/DBD2/SO00/TxD0/TI04/TO04/SEG33
P113/DBD3/TI06/TO06/SEG32
P114/DBD4/TI07/TO07/SEG31
P115/DBD5/TI10/TO10/SEG30
P116/DBD6/TI12/TO12/SEG29
P117/DBD7/TI20/TO20/SEG28
P121/X1
37-C
Input
Independently connect to VDD or VSS via a resistor.
17-W (1)
I/O
Input: Independently connect to EVSS via a resistor.
P122/X2/EXCLK
P123/XT1
P124/XT2
P125/TI12/TO12/SEG25
P126/TI14/TO14/SEG24
Output: Leave open.
P127/TI16/TO16/SEG23
P130/RESOUT
3-C
Output
Leave open.
P131/SO10/LTxD1/TI21/TO21
5-AH
I/O
P132/SI10/LRxD1/INTPLR1/TI20/TO20
Input: Independently connect to EVDD or EVSS via a
resistor.
P133/SCK10/TI22/TO22
Output: Leave open.
P134/SGOA/CTxD1/TI24/TO24
P135/SGO/SGOF/CRxD1/TI26/TO26
5-BA
P136/TI00/TO00/SCL11/SEG48
17-W
Input: Independently connect to EVSS via a resistor.
Output: Leave open.
P137/INTP5
2-H
Input
Independently connect to VDD or VSS via a resistor.
P140/TI11/TO11
5-AH
I/O
Input: Independently connect to EVDD or EVSS via a
resistor.
Output: Leave open.
P150/ANI8
Input: Independently connect to VDD or VSS via a
resistor.
11-Z
P151/ANI9
Output: Leave open.
P152/ANI10
COM0 to COM3
____________
RESET
REGC
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Output
Leave open
2
Input
Connect directly or via a resistor to VDD.
-
-
Connect to VSS via capacitor (0.47 to 1 μF).
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CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuit List (1/3)
Type 2
Type 2H
IN
IN
Input
enable
Schmitt-triggered input with hysteresis characteristics
Type 3-C
Type 5-AH
EVDD
pull-up
enable
EVDD
P-ch
EVDD
P-ch
OUT
Data
Data
P-ch
N-ch
IN/OUT
Output
disable
EVSS
N-ch
EVSS
Schmitt3
Input
enable
Type 5-BA
Type 11-Z
EVDD
pull-up
enable
EVDD
P-ch
Data
P-ch
EVDD
Data
IN/OUT
Output
disable
P-ch
N-ch
IN/OUT
Output
disable
N-ch
EVSS
Schmitt3
EVSS
Comparator
N-ch
VREF
Schmitt1
Input characteristic
Input enable
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+
EVSS
Schmitt3
Input
enable
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RL78/D1A
CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuit List (2/3)
Type11-AA
EVDD/SMVDD
Type17-W
VDD
Data
pull-up
enable
P-ch
IN/OUT
Output
disable
EVDD /SMVDD
Data
P-ch
N-ch
IN/OUT
Output
disable
VSS
Comparator
P-ch
+
-
N-ch
Schmitt3
N-ch
N-ch
Input enable
pull-down enable
VSS
VREF
EVSS /SMVSS
Schmitt3
P-ch
VLC0
Input
enable
P-ch
P-ch
AVREFP/ AVREFM
EVSS /
SMVSS
VLC1
N-ch
N-ch
SEG
P-ch
VLC2
N-ch
N-ch
EVSS /SMVSS
Type17-AD
SMVDD
Type17-AE
EVDD
pull-up
enable
pull-up
enable
EVDD
Data
SMVDD
Data
P-ch
P-ch
IN/OUT
IN/OUT
Output
disable
N-ch
Output
disable
N-ch
ZPD Comparator
+
-
Schmitt3 EVSS
SMVSS
VREF
Schmitt3
Schmitt1
N-ch
Input characteristic
N-ch
Input enable
P-ch
VLC0
pull-down enable
P-ch
P-ch
EVSS
VLC1
N-ch
SEG
N-ch
P-ch
VLC2
SMVSS
P-ch
VLC0
VLC1
Input enable
pull-down enable
SEG
P-ch
VLC2
N-ch
N-ch
N-ch
EVSS
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EVSS
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CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuit List (3/3)
Type37-C
Type18-G
Schmitt2
P-ch
VLC0
X2/XT2
P-ch
VLC1
Input enable
N-ch
P-ch
COM
VLC2
N-ch
Amp. enable
N-ch
EVSS
X1/XT1
Input enable
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CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
Products in the RL78/D1A can access a 1 MB memory space. Figures 3-1 to 3-9 show the memory maps.
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Figure 3-1. Memory Map (R5F10CGBxFB)
05FFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
Notes 1, 2
RAM
2 KB
Program area
FF700H
FF6FFH
Mirror
49.75 KB
F3000H
F2FFFH
03FFFH
Notes 2
Data flash memory
8 KB
F1000H
F0FFFH
Reserved
020C4H
020C3H
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Data memory
space
020CEH
020CDH
F0000H
EFFFFH
020C0H
020BFH
02080H
0207FH
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
02000H
01FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
06000H
05FFFH
Program
memory
space
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 0Note 4
CALLT table area
64 bytes
Vector table area
128 bytes
Code flash memory
24 KB
00000H
00000H
Notes 1. Use of part of this area is prohibited by libraries, when using the self-programming function and data flash
function.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used:
Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 020C0H to 020C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 020C4H to 020CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 29.6 Security Setting).
Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Figure 3-2. Memory Map (R5F10CGCxFB, R5F10DGCxFB)
07FFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
Notes 1, 2
RAM
2 KB
Program area
FF700H
FF6FFH
Mirror
49.75 KB
F3000H
F2FFFH
F1000H
F0FFFH
03FFFH
Notes 2
Data flash memory
8 KB
Reserved
020C4H
020C3H
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Data memory
space
020CEH
020CDH
020C0H
020BFH
F0000H
EFFFFH
02080H
0207FH
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
02000H
01FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
08000H
07FFFH
Program
memory
space
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 0Note 4
CALLT table area
64 bytes
Vector table area
128 bytes
Code flash memory
32 KB
00000H
00000H
Notes 1. Use of part of this area is prohibited by libraries, when using the self-programming function and data flash
function.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used:
Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 020C0H to 020C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 020C4H to 020CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 29.6 Security Setting).
Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Figure 3-3. Memory Map (R5F10CGDxFB, R5F10DGDxFB, R5F10CLDxFB, R5F10DLDxFB, R5F10CMDxFB,
R5F10DMDxFB)
0BFFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
RAMNotes 1, 2
3 KB
Program area
FF300H
FF2FFH
Mirror
48.75 KB
F3000H
F2FFFH
F1000H
F0FFFH
03FFFH
Data flash memory
8 KB
020CEH
020CDH
Reserved
020C4H
020C3H
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Data memory
space
F0000H
EFFFFH
020C0H
020BFH
02080H
0207FH
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
02000H
01FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
0C000H
0BFFFH
Program
memory
space
Option byte areaNote 3
4 bytes
Boot cluster 0Note 4
CALLT table area
64 bytes
Vector table area
128 bytes
Code flash memory
48 KB
00000H
On-chip debug security
ID setting areaNote 3
10 bytes
00000H
Notes 1. Use of part of this area is prohibited by libraries, when using the self-programming function and data flash
function.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used:
Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 020C0H to 020C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 020C4H to 020CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 29.6 Security Setting).
Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Figure 3-4. Memory Map (R5F10DGExFB, R5F10DLExFB, R5F10CMExFB, R5F10DMExFB, R5F10DPExFB)
0FFFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
RAMNotes 1, 2
4 KB
Program area
FEF00H
FEEFFH
Mirror
47.75 KB
F3000H
F2FFFH
03FFFH
Data flash memory
8 KB
F1000H
F0FFFH
Reserved
020C4H
020C3H
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
F0000H
EFFFFH
Data memory
space
020CEH
020CDH
020C0H
020BFH
02080H
0207FH
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
02000H
01FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
10000H
0FFFFH
Program
memory
space
Option byte areaNote 3
4 bytes
Boot cluster 0Note 4
CALLT table area
64 bytes
Vector table area
128 bytes
Code flash memory
64 KB
00000H
On-chip debug security
ID setting areaNote 3
10 bytes
00000H
Notes 1. Use of part of this area is prohibited by libraries, when using the self-programming function and data flash
function.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used:
Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH and 020C4H to 020CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 29.6 Security Setting).
Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Figure 3-5. Memory Map (R5F10DMFxFB, R5F10DPFxFB)
17FFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
Notes 1, 2
RAM
6 KB
Program area
FE700H
FE6FFH
Mirror
45.75 KB
F3000H
F2FFFH
03FFFH
Data flash memory
8 KB
F1000H
F0FFFH
Reserved
020C4H
020C3H
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Data memory
space
020CEH
020CDH
F0000H
EFFFFH
020C0H
020BFH
02080H
0207FH
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
02000H
01FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
18000H
17FFFH
Program
memory
space
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 0Note 4
CALLT table area
64 bytes
Vector table area
128 bytes
Code flash memory
96 KB
00000H
00000H
Notes 1. Use of part of this area is prohibited by libraries, when using the self-programming function and data flash
function.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used:
Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 020C0H to 020C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 020C4H to 020CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 29.6 Security Setting).
Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Figure 3-6. Memory Map (R5F10DMGxFB, R5F10DPGxFB)
1FFFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
Note 1, 2
RAM
8 KB
Program area
FDF00H
FDEFFH
Mirror
43.75 KB
F3000H
F2FFFH
03FFFH
Data flash memory
8 KB
F1000H
F0FFFH
Reserved
F0800H
F07FFH
020C4H
020C3H
Special function register (2nd SFR)
2 KB
F0000H
EFFFFH
Data memory
space
020CEH
020CDH
020C0H
020BFH
02080H
0207FH
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
02000H
01FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
20000H
1FFFFH
Program
memory
space
Option byte areaNote 3
4 bytes
Boot cluster 0Note 4
CALLT table area
64 bytes
Vector table area
128 bytes
Code flash memory
128 KB
00000H
On-chip debug security
ID setting areaNote 3
10 bytes
00000H
Notes 1. Use of part of this area is prohibited by libraries, when using the self-programming function and data flash
function.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used:
Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 020C0H to 020C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 020C4H to 020CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 29.6 Security Setting).
Caution
When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Figure 3-7. Memory Map (R5F10DMJxFB, R5F10TPJxFB, R5F10DPJxFB, R5F10DSJxFB)
3FFFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
Notes 1, 2
RAM
16 KB
Program area
FBF00H
FBEFFH
Mirror
35.75 KB
F3000H
F2FFFH
03FFFH
Data flash memory
8 KB
F1000H
F0FFFH
Reserved
F0800H
F07FFH
020C4H
020C3H
Special function register (2nd SFR)
2 KB
F0000H
EFFFFH
Data memory
space
020CEH
020CDH
020C0H
020BFH
02080H
0207FH
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
02000H
01FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
40000H
3FFFFH
Program
memory
space
00080H
0007FH
Option byte areaNote 3
4 bytes
Boot cluster 0Note 4
CALLT table area
64 bytes
Vector table area
128 bytes
Code flash memory
256 KB
00000H
On-chip debug security
ID setting areaNote 3
10 bytes
00000H
Notes 1. Use of part of this area is prohibited by libraries, when using the self-programming function and data flash
function.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used:
Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 020C0H to 020C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 020C4H to 020CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 29.6 Security Setting).
Caution
When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Figure3-8. Memory Map (R5F10DSKxFB, R5F10DPKxFB)
5FFFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
RAMNotes 1, 2
20 KB
FAF00H
FAEFFH
Program area
Mirror
31.75 KB
F3000H
F2FFFH
03FFFH
Data flash memory
8 KB
F1000H
F0FFFH
Reserved
020C4H
020C3H
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
F0000H
EFFFFH
Data memory
space
020CEH
020CDH
020C0H
020BFH
02080H
0207FH
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
02000H
01FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
60000H
5FFFFH
Program
memory
space
00080H
0007FH
Option byte areaNote 3
4 bytes
Boot cluster 0Note 4
CALLT table area
64 bytes
Vector table area
128 bytes
Code flash memory
384 KB
00000H
On-chip debug security
ID setting areaNote 3
10 bytes
00000H
Notes 1. Use of part of this area is prohibited by libraries, when using the self-programming function and data flash
function.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used:
Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 020C0H to 020C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 020C4H to 020CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 29.6 Security Setting).
Caution
When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Figure 3-9. Memory Map (R5F10DSLxFB, R5F10DPLxFB)
7FFFFH
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
RAMNotes 1, 2
24 KB
F9F00H
F9EFFH
Program area
Mirror
27.75 KB
F3000H
F2FFFH
03FFFH
Data flash memory
8 KB
F1000H
F0FFFH
Reserved
020C4H
020C3H
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
F0000H
EFFFFH
Data memory
space
020CEH
020CDH
020C0H
020BFH
02080H
0207FH
On-chip debug security
ID setting areaNote 3
10 bytes
Option byte areaNote 3
4 bytes
Boot cluster 1
CALLT table area
64 bytes
Vector table area
128 bytes
02000H
01FFFH
Reserved
Program area
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
80000H
7FFFFH
Program
memory
space
00080H
0007FH
Option byte areaNote 3
4 bytes
Boot cluster 0Note 4
CALLT table area
64 bytes
Vector table area
128 bytes
Code flash memory
512 KB
00000H
On-chip debug security
ID setting areaNote 3
10 bytes
00000H
Notes 1. Use of part of this area is prohibited by libraries, when using the self-programming function and data flash
function.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used:
Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 020C0H to 020C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 020C4H to 020CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 29.6 Security Setting).
Caution
When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
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Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see
Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory.
7FFFFH
7FC00H
7FBFFH
007FFH
00400H
003FFH
00000H
Block 1FFH
Block 001H
Block 000H
1 KB
(In case of R5F113TLL)
(In case of that Flash size is 512KB.)
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Correspondence between the address values and block numbers in the flash memory are shown below.
Table 3-1. Correspondence between Address Values and Block Numbers in Flash Memory (1/4)
Address Value
Block
Address Value
Block
Address Value
Block
Address Value
Block
Number
Number
Number
Number
00000H to 003FFH
000H
08000H to 083FFH
020H
10000H to 103FFH
040H
18000H to 183FFH
060H
00400H to 007FFH
001H
08400H to 087FFH
021H
10400H to 107FFH
041H
18400H to 187FFH
061H
00800H to 00BFFH
002H
08800H to 08BFFH
022H
10800H to 10BFFH
042H
18800H to 18BFFH
062H
00C00H to 00FFFH
003H
08C00H to 08FFFH
023H
10C00H to 10FFFH
043H
18C00H to 18FFFH
063H
01000H to 013FFH
004H
09000H to 093FFH
024H
11000H to 113FFH
044H
19000H to 193FFH
064H
01400H to 017FFH
005H
09400H to 097FFH
025H
11400H to 117FFH
045H
19400H to 197FFH
065H
01800H to 01BFFH
006H
09800H to 09BFFH
026H
11800H to 11BFFH
046H
19800H to 19BFFH
066H
01C00H to 01FFFH
007H
09C00H to 09FFFH
027H
11C00H to 11FFFH
047H
19C00H to 19FFFH
067H
02000H to 023FFH
008H
0A000H to 0A3FFH
028H
12000H to 123FFH
048H
1A000H to 1A3FFH
068H
02400H to 027FFH
009H
0A400H to 0A7FFH
029H
12400H to 127FFH
049H
1A400H to 1A7FFH
069H
02800H to 02BFFH
00AH
0A800H to 0ABFFH
02AH
12800H to 12BFFH
04AH
1A800H to 1ABFFH
06AH
02C00H to 02FFFH
00BH
0AC00H to 0AFFFH
02BH
12C00H to 12FFFH
04BH
1AC00H to 1AFFFH
06BH
03000H to 033FFH
00CH
0B000H to 0B3FFH
02CH
13000H to 133FFH
04CH
1B000H to 1B3FFH
06CH
03400H to 037FFH
00DH
0B400H to 0B7FFH
02DH
13400H to 137FFH
04DH
1B400H to 1B7FFH
06DH
03800H to 03BFFH
00EH
0B800H to 0BBFFH
02EH
13800H to 13BFFH
04EH
1B800H to 1BBFFH
06EH
03C00H to 03FFFH
00FH
0BC00H to 0BFFFH
02FH
13C00H to 13FFFH
04FH
1BC00H to 1BFFFH
06FH
04000H to 043FFH
010H
0C000H to 0C3FFH
030H
14000H to 143FFH
050H
1C000H to 1C3FFH
070H
04400H to 047FFH
011H
0C400H to 0C7FFH
031H
14400H to 147FFH
051H
1C400H to 1C7FFH
071H
04800H to 04BFFH
012H
0C800H to 0CBFFH
032H
14800H to 14BFFH
052H
1C800H to 1CBFFH
072H
04C00H to 04FFFH
013H
0CC00H to 0CFFFH
033H
14C00H to 14FFFH
053H
1CC00H to 1CFFFH
073H
05000H to 053FFH
014H
0D000H to 0D3FFH
034H
15000H to 153FFH
054H
1D000H to 1D3FFH
074H
05400H to 057FFH
015H
0D400H to 0D7FFH
035H
15400H to 157FFH
055H
1D400H to 1D7FFH
075H
05800H to 05BFFH
016H
0D800H to 0DBFFH
036H
15800H to 15BFFH
056H
1D800H to 1DBFFH
076H
05C00H to 05FFFH
017H
0DC00H to 0DFFFH
037H
15C00H to 15FFFH
057H
1DC00H to 1DFFFH
077H
06000H to 063FFH
018H
0E000H to 0E3FFH
038H
16000H to 163FFH
058H
1E000H to 1E3FFH
078H
06400H to 067FFH
019H
0E400H to 0E7FFH
039H
16400H to 167FFH
059H
1E400H to 1E7FFH
079H
06800H to 06BFFH
01AH
0E800H to 0EBFFH
03AH
16800H to 16BFFH
05AH
1E800H to 1EBFFH
07AH
06C00H to 06FFFH
01BH
0EC00H to 0EFFFH
03BH
16C00H to 16FFFH
05BH
1EC00H to 1EFFFH
07BH
07000H to 073FFH
01CH
0F000H to 0F3FFH
03CH
17000H to 173FFH
05CH
1F000H to 1F3FFH
07CH
07400H to 077FFH
01DH
0F400H to 0F7FFH
03DH
17400H to 177FFH
05DH
1F400H to 1F7FFH
07DH
07800H to 07BFFH
01EH
0F800H to 0FBFFH
03EH
17800H to 17BFFH
05EH
1F800H to 1FBFFH
07EH
07C00H to 07FFFH
01FH
0FC00H to 0FFFFH
03FH
17C00H to 17FFFH
05FH
1FC00H to 1FFFFH
07FH
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Table 3-1. Correspondence between Address Values and Block Numbers in Flash Memory (2/4)
Address Value
Block
Address Value
Block
Address Value
Block
Address Value
Block
Number
Number
Number
Number
20000H to 203FFH
080H
28000H to 283FFH
0A0H
30000H to 303FFH
0C0H
38000H to 383FFH
0E0H
20400H to 207FFH
081H
28400H to 287FFH
0A1H
30400H to 307FFH
0C1H
38400H to 387FFH
0E1H
20800H to 20BFFH
082H
28800H to 28BFFH
0A2H
30800H to 30BFFH
0C2H
38800H to 38BFFH
0E2H
20C00H to 20FFFH
083H
28C00H to 28FFFH
0A3H
30C00H to 30FFFH
0C3H
38C00H to 38FFFH
0E3H
21000H to 213FFH
084H
29000H to 293FFH
0A4H
31000H to 313FFH
0C4H
39000H to 393FFH
0E4H
21400H to 217FFH
085H
29400H to 297FFH
0A5H
31400H to 317FFH
0C5H
39400H to 397FFH
0E5H
21800H to 21BFFH
086H
29800H to 29BFFH
0A6H
31800H to 31BFFH
0C6H
39800H to 39BFFH
0E6H
21C00H to 21FFFH
087H
29C00H to 29FFFH
0A7H
31C00H to 31FFFH
0C7H
39C00H to 39FFFH
0E7H
22000H to 223FFH
088H
2A000H to 2A3FFH
0A8H
32000H to 323FFH
0C8H
3A000H to 3A3FFH
0E8H
22400H to 227FFH
089H
2A400H to 2A7FFH
0A9H
32400H to 327FFH
0C9H
3A400H to 3A7FFH
0E9H
22800H to 22BFFH
08AH
2A800H to 2ABFFH
0AAH
32800H to 32BFFH
0CAH
3A800H to 3ABFFH
0EAH
22C00H to 22FFFH
08BH
2AC00H to 2AFFFH
0ABH
32C00H to 32FFFH
0CBH
3AC00H to 3AFFFH
0EBH
23000H to 233FFH
08CH
2B000H to 2B3FFH
0ACH
33000H to 333FFH
0CCH
3B000H to 3B3FFH
0ECH
23400H to 237FFH
08DH
2B400H to 2B7FFH
0ADH
33400H to 337FFH
0CDH
3B400H to 3B7FFH
0EDH
23800H to 23BFFH
08EH
2B800H to 2BBFFH
0AEH
33800H to 33BFFH
0CEH
3B800H to 3BBFFH
0EEH
23C00H to 23FFFH
08FH
2BC00H to 2BFFFH
0AFH
33C00H to 33FFFH
0CFH
3BC00H to 3BFFFH
0EFH
24000H to 243FFH
090H
2C000H to 2C3FFH
0B0H
34000H to 343FFH
0D0H
3C000H to 3C3FFH
0F0H
24400H to 247FFH
091H
2C400H to 2C7FFH
0B1H
34400H to 347FFH
0D1H
3C400H to 3C7FFH
0F1H
24800H to 24BFFH
092H
2C800H to 2CBFFH
0B2H
34800H to 34BFFH
0D2H
3C800H to 3CBFFH
0F2H
24C00H to 24FFFH
093H
2CC00H to 2CFFFH
0B3H
34C00H to 34FFFH
0D3H
3CC00H to 3CFFFH
0F3H
25000H to 253FFH
094H
2D000H to 2D3FFH
0B4H
35000H to 353FFH
0D4H
3D000H to 3D3FFH
0F4H
25400H to 257FFH
095H
2D400H to 2D7FFH
0B5H
35400H to 357FFH
0D5H
3D400H to 3D7FFH
0F5H
25800H to 25BFFH
096H
2D800H to 2DBFFH
0B6H
35800H to 35BFFH
0D6H
3D800H to 3DBFFH
0F6H
25C00H to 25FFFH
097H
2DC00H to 2DFFFH
0B7H
35C00H to 35FFFH
0D7H
3DC00H to 3DFFFH
0F7H
26000H to 263FFH
098H
2E000H to 2E3FFH
0B8H
36000H to 363FFH
0D8H
3E000H to 3E3FFH
0F8H
26400H to 267FFH
099H
2E400H to 2E7FFH
0B9H
36400H to 367FFH
0D9H
3E400H to 3E7FFH
0F9H
26800H to 26BFFH
09AH
2E800H to 2EBFFH
0BAH
36800H to 36BFFH
0DAH
3E800H to 3EBFFH
0FAH
26C00H to 26FFFH
09BH
2EC00H to 2EFFFH
0BBH
36C00H to 36FFFH
0DBH
3EC00H to 3EFFFH
0FBH
27000H to 273FFH
09CH
2F000H to 2F3FFH
0BCH
37000H to 373FFH
0DCH
3F000H to 3F3FFH
0FCH
27400H to 277FFH
09DH
2F400H to 2F7FFH
0BDH
37400H to 377FFH
0DDH
3F400H to 3F7FFH
0FDH
27800H to 27BFFH
09EH
2F800H to 2FBFFH
0BEH
37800H to 37BFFH
0DEH
3F800H to 3FBFFH
0FEH
27C00H to 27FFFH
09FH
2FC00H to 2FFFFH
0BFH
37C00H to 37FFFH
0DFH
3FC00H to 3FFFFH
0FFH
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Table 3-1. Correspondence between Address Values and Block Numbers in Flash Memory (3/4)
Address Value
Block
Address Value
Block
Address Value
Block
Address Value
Block
Number
Number
Number
Number
40000H-403FFH
100H
48000H-483FFH
120H
50000H-503FFH
140H
58000H-583FFH
160H
40400H-407FFH
101H
48400H-487FFH
121H
50400H-507FFH
141H
58400H-587FFH
161H
40800H-40BFFH
102H
48800H-48BFFH
122H
50800H-50BFFH
142H
58800H-58BFFH
162H
40C00H-40FFFH
103H
48C00H-48FFFH
123H
50C00H-50FFFH
143H
58C00H-58FFFH
163H
41000H-413FFH
104H
49000H-493FFH
124H
51000H-513FFH
144H
59000H-593FFH
164H
41400H-417FFH
105H
49400H-497FFH
125H
51400H-517FFH
145H
59400H-597FFH
165H
41800H-41BFFH
106H
49800H-49BFFH
126H
51800H-51BFFH
146H
59800H-59BFFH
166H
41C00H-41FFFH
107H
49C00H-49FFFH
127H
51C00H-51FFFH
147H
59C00H-59FFFH
167H
42000H-423FFH
108H
4A000H-4A3FFH
128H
52000H-523FFH
148H
5A000H-5A3FFH
168H
42400H-427FFH
109H
4A400H-4A7FFH
129H
52400H-527FFH
149H
5A400H-5A7FFH
169H
42800H-42BFFH
10AH
4A800H-4ABFFH
12AH
52800H-52BFFH
14AH
5A800H-5ABFFH
16AH
42C00H-42FFFH
10BH
4AC00H-4AFFFH
12BH
52C00H-52FFFH
14BH
5AC00H-5AFFFH
16BH
43000H-433FFH
10CH
4B000H-4B3FFH
12CH
53000H-533FFH
14CH
5B000H-5B3FFH
16CH
43400H-437FFH
10DH
4B400H-4B7FFH
12DH
53400H-537FFH
14DH
5B400H-5B7FFH
16DH
43800H-43BFFH
10EH
4B800H-4BBFFH
12EH
53800H-53BFFH
14EH
5B800H-5BBFFH
16EH
43C00H-43FFFH
10FH
4BC00H-4BFFFH
12FH
53C00H-53FFFH
14FH
5BC00H-5BFFFH
16FH
44000H-443FFH
110H
4C000H-4C3FFH
130H
54000H-543FFH
150H
5C000H-5C3FFH
170H
44400H-447FFH
111H
4C400H-4C7FFH
131H
54400H-547FFH
151H
5C400H-5C7FFH
171H
44800H-44BFFH
112H
4C800H-4CBFFH
132H
54800H-54BFFH
152H
5C800H-5CBFFH
172H
44C00H-44FFFH
113H
4CC00H-4CFFFH
133H
54C00H-54FFFH
153H
5CC00H-5CFFFH
173H
45000H-453FFH
114H
4D000H-4D3FFH
134H
55000H-553FFH
154H
5D000H-5D3FFH
174H
45400H-457FFH
115H
4D400H-4D7FFH
135H
55400H-557FFH
155H
5D400H-5D7FFH
175H
45800H-45BFFH
116H
4D800H-4DBFFH
136H
55800H-55BFFH
156H
5D800H-5DBFFH
176H
45C00H-45FFFH
117H
4DC00H-4DFFFH
137H
55C00H-55FFFH
157H
5DC00H-5DFFFH
177H
46000H-463FFH
118H
4E000H-4E3FFH
138H
56000H-563FFH
158H
5E000H-5E3FFH
178H
46400H-467FFH
119H
4E400H-4E7FFH
139H
56400H-567FFH
159H
5E400H-5E7FFH
179H
46800H-46BFFH
11AH
4E800H-4EBFFH
13AH
56800H-56BFFH
15AH
5E800H-5EBFFH
17AH
46C00H-46FFFH
11BH
4EC00H-4EFFFH
13BH
56C00H-56FFFH
15BH
5EC00H-5EFFFH
17BH
47000H-473FFH
11CH
4F000H-4F3FFH
13CH
57000H-573FFH
15CH
5F000H-5F3FFH
17CH
47400H-477FFH
11DH
4F400H-4F7FFH
13DH
57400H-577FFH
15DH
5F400H-5F7FFH
17DH
47800H-47BFFH
11EH
4F800H-4FBFFH
13EH
57800H-57BFFH
15EH
5F800H-5FBFFH
17EH
47C00H-47FFFH
11FH
4FC00H-4FFFFH
13FH
57C00H-57FFFH
15FH
5FC00H-5FFFFH
17FH
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Table 3-1. Correspondence between Address Values and Block Numbers in Flash Memory (4/4)
Address Value
Block
Address Value
Block
Address Value
Block
Address Value
Block
Number
Number
Number
Number
60000H-603FFH
180H
68000H-683FFH
1A0H
70000H-703FFH
1C0H
78000H-783FFH
1E0H
60400H-607FFH
181H
68400H-687FFH
1A1H
70400H-707FFH
1C1H
78400H-787FFH
1E1H
60800H-60BFFH
182H
68800H-68BFFH
1A2H
70800H-70BFFH
1C2H
78800H-78BFFH
1E2H
60C00H-60FFFH
183H
68C00H-68FFFH
1A3H
70C00H-70FFFH
1C3H
78C00H-78FFFH
1E3H
61000H-613FFH
184H
69000H-693FFH
1A4H
71000H-713FFH
1C4H
79000H-793FFH
1E4H
61400H-617FFH
185H
69400H-697FFH
1A5H
71400H-717FFH
1C5H
79400H-797FFH
1E5H
61800H-61BFFH
186H
69800H-69BFFH
1A6H
71800H-71BFFH
1C6H
79800H-79BFFH
1E6H
61C00H-61FFFH
187H
69C00H-69FFFH
1A7H
71C00H-71FFFH
1C7H
79C00H-79FFFH
1E7H
62000H-623FFH
188H
6A000H-6A3FFH
1A8H
72000H-723FFH
1C8H
7A000H-7A3FFH
1E8H
62400H-627FFH
189H
6A400H-6A7FFH
1A9H
72400H-727FFH
1C9H
7A400H-7A7FFH
1E9H
62800H-62BFFH
18AH
6A800H-6ABFFH
1AAH
72800H-72BFFH
1CAH
7A800H-7ABFFH
1EAH
62C00H-62FFFH
18BH
6AC00H-6AFFFH
1ABH
72C00H-72FFFH
1CBH
7AC00H-7AFFFH
1EBH
63000H-633FFH
18CH
6B000H-6B3FFH
1ACH
73000H-733FFH
1CCH
7B000H-7B3FFH
1ECH
63400H-637FFH
18DH
6B400H-6B7FFH
1ADH
73400H-737FFH
1CDH
7B400H-7B7FFH
1EDH
63800H-63BFFH
18EH
6B800H-6BBFFH
1AEH
73800H-73BFFH
1CEH
7B800H-7BBFFH
1EEH
63C00H-63FFFH
18FH
6BC00H-6BFFFH
1AFH
73C00H-73FFFH
1CFH
7BC00H-7BFFFH
1EFH
64000H-643FFH
190H
6C000H-6C3FFH
1B0H
74000H-743FFH
1D0H
7C000H-7C3FFH
1F0H
64400H-647FFH
191H
6C400H-6C7FFH
1B1H
74400H-747FFH
1D1H
7C400H-7C7FFH
1F1H
64800H-64BFFH
192H
6C800H-6CBFFH
1B2H
74800H-74BFFH
1D2H
7C800H-7CBFFH
1F2H
64C00H-64FFFH
193H
6CC00H-6CFFFH
1B3H
74C00H-74FFFH
1D3H
7CC00H-7CFFFH
1F3H
65000H-653FFH
194H
6D000H-6D3FFH
1B4H
75000H-753FFH
1D4H
7D000H-7D3FFH
1F4H
65400H-657FFH
195H
6D400H-6D7FFH
1B5H
75400H-757FFH
1D5H
7D400H-7D7FFH
1F5H
65800H-65BFFH
196H
6D800H-6DBFFH
1B6H
75800H-75BFFH
1D6H
7D800H-7DBFFH
1F6H
65C00H-65FFFH
197H
6DC00H-6DFFFH
1B7H
75C00H-75FFFH
1D7H
7DC00H-7DFFFH
1F7H
66000H-663FFH
198H
6E000H-6E3FFH
1B8H
76000H-763FFH
1D8H
7E000H-7E3FFH
1F8H
66400H-667FFH
199H
6E400H-6E7FFH
1B9H
76400H-767FFH
1D9H
7E400H-7E7FFH
1F9H
66800H-66BFFH
19AH
6E800H-6EBFFH
1BAH
76800H-76BFFH
1DAH
7E800H-7EBFFH
1FAH
66C00H-66FFFH
19BH
6EC00H-6EFFFH
1BBH
76C00H-76FFFH
1DBH
7EC00H-7EFFFH
1FBH
67000H-673FFH
19CH
6F000H-6F3FFH
1BCH
77000H-773FFH
1DCH
7F000H-7F3FFH
1FCH
67400H-677FFH
19DH
6F400H-6F7FFH
1BDH
77400H-777FFH
1DDH
7F400H-7F7FFH
1FDH
67800H-67BFFH
19EH
6F800H-6FBFFH
1BEH
77800H-77BFFH
1DEH
7F800H-7FBFFH
1FEH
67C00H-67FFFH
19FH
6FC00H-6FFFFH
1BFH
77C00H-77FFFH
1DFH
7FC00H-7FFFFH
1FFH
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3.1.1 Internal program memory space
The internal program memory space stores the program and table data.
The RL78/D1A products incorporate internal ROM (flash memory), as shown below.
Table 3-2. Internal ROM Capacity
Part Number
Internal ROM
Structure
R5F10CGBxFB
Flash memory
Capacity
24576 8 bits (00000H to 05FFFH)
R5F10CGCxFB, R5F10DGCxFB
32768 8 bits (00000H to 07FFFH)
R5F10CGDxFB, R5F10DGDxFB, R5F10CLDxFB,
49152 8 bits (00000H to 0BFFFH)
R5F10DLDxFB, R5F10CMDxFB, R5F10DMDxFB
R5F10DGExFB, R5F10DLExFB, R5F10CMExFB,
65536 8 bits (00000H to 0FFFFH)
R5F10DMExFB, R5F10DPExFB
R5F10DMFxFB, R5F10DPFxFB
98304 8 bits (00000H to 17FFFH)
R5F10DMGxFB, R5F10DPGxFB
131072 8 bits (00000H to 1FFFFH)
R5F10DMJxFB, R5F10TPJxFB, R5F10DPJxFB,
262144 8 bits (00000H to 3FFFFH)
R5F10DSJxFB
R5F10DSKxFB, R5F10DPKxFB
393216 8 bits (00000H to 5FFFFH)
R5F10DSLxFB, R5F10DPLxFB
524288 8 bits (00000H to 7FFFFH)
The internal program memory space is divided into the following areas.
(1) Vector table area
The 128-byte area 00000H to 0007FH is reserved as a vector table area. The program start addresses for branch
upon reset or generation of each interrupt request are stored in the vector table area. Furthermore, the interrupt jump
address is a 64 K address of 00000H to 0FFFFH, because the vector code is assumed to be 2 bytes.
Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses.
To use the boot swap function, set a vector table also at 02000H to 0207FH.
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Table 3-3. Vector Table (1/2)
R5F10DSx
128-pin
R5F10DPJ
R5F10DPx
R5F10TPx/
100-pin
R5F10DMx
80-pin
R5F10CMx
RESET, POR,
64-pin
R5F10DLx
0000H
48-pin
R5F10CLx
Source
R5F10DGx
Interrupt
R5F10CGx
Vector
Table Address
LVD, WDT,
TRAP, IAW,
RPE, CLKM
0004H
INTWDTI
0006H
INTLVI
0008H
INTP0
–
–
000AH
INTP1
000CH
INTP2
000EH
INTP3
0010H
INTP4
0012H
INTP5
0014H
INTCLM
0016H
INTCSI00
INTST0
INTCSI01
INTSR0
INTDMA0
0018H
001AH
001CH
INTDMA1
001EH
INTRTC
0020H
INTIT
0022H
INTLT0
–
–
0024H
INTLR0
–
–
0026H
INTLS0
–
–
0028H
INTPLR0
–
–
002AH
INTSG
002CH
INTTM00
002EH
INTTM01
0030H
INTTM02
0032H
INTTM03
0034H
INTAD
0036H
INTLT1
0038H
INTLR1
003AH
INTLS1
003CH
INTPLR1
003EH
INTCSI10
0040H
INTIIC11
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Table 3-3. Vector Table (2/2)
R5F10DSx
128-pin
R5F10DPJ
100-pin
R5F10DPx
80-pin
R5F10TPx/
R5F10DGx
64-pin
R5F10DMx
48-pin
R5F10DSx
Source
R5F10CLx
Interrupt
R5F10CGx
Vector
Table Address
R5F10DLx
0042H
INTTM04
0044H
INTTM05
0046H
INTTM06
0048H
INTTM07
004AH
INTC1ERR
004CH
INTC1WUP
004EH
INTC0ERR
0050H
INTC0WUP
0052H
INTC0REC
0054H
INTC0TRX
0056H
INTTM10
0058H
INTTM11
005AH
INTTM12
005CH
INTTM13
005EH
INTMD
0060H
INTC1REC
0062H
INTFL
0064H
INTC1TRX
0066H
INTTM14
0068H
INTTM15
006AH
INTTM16
006CH
INTTM17
006EH
INTTM20
00070H
INTTM21
00072H
INTTM22
0074H
INTTM23
0076H
INTTM24
0078H
INTTM26
007AH
INTDMA2
007CH
INTDMA3
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(2) CALLT instruction table area
The 64-byte area 00080H to 000BFH can store the subroutine entry address of a 2-byte call instruction (CALLT). Set
the subroutine entry address to a value in a range of 00000H to 0FFFFH (because an address code is of 2 bytes).
To use the boot swap function, set a CALLT instruction table also at 02080H to 020BFH.
(3) Option byte area
A 4-byte area of 000C0H to 000C3H can be used as an option byte area. Set the option byte at 020C0H to 020C3H
when the boot swap is used. For details, see CHAPTER 28 OPTION BYTE.
(4) On-chip debug security ID setting area
A 10-byte area of 000C4H to 000CDH and 020C4H to 020CDH can be used as an on-chip debug security ID setting
area. Set the on-chip debug security ID of 10 bytes at 000C4H to 000CDH when the boot swap is not used and at
000C4H to 000CDH and 020C4H to 020CDH when the boot swap is used. For details, see CHAPTER 30 ON-CHIP
DEBUG FUNCTION.
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3.1.2 Mirror area
The RL78/D1A mirrors the code flash area of 00000H to 0FFFFH, to F0000H to FFFFFH. The products with 96 KB or
more flash memory mirror the code flash area of 00000H to 0FFFFH or 10000H to 1FFFFH, to F0000H to FFFFFH (the
code flash area to be mirrored is set by the processor mode control register (PMC)).
By reading data from F0000H to FFFFFH, an instruction that does not have the ES register as an operand can be used,
and thus the contents of the code flash can be read with the shorter code. However, the code flash area is not mirrored to
the SFR, extended SFR, RAM, and use prohibited areas.
See 3.1 Memory Space for the mirror area of each product.
The mirror area can only be read and no instruction can be fetched from this area.
The following show examples.
Example R5F10DMExFB (Flash memory: 64 KB, RAM: 4 KB)
FFFFFH
Special-function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
FEF00H
FEEFFH
General-purpose register
32 bytes
RAM
4 KB
For example, 0E789H is mirrored to
FE789H. Data can therefore be read
Mirror
(same data as 03000H to 0EEFFH)
by MOV A, !E789H, instead of MOV
ES, #00H and MOV A, ES:!E789H.
F3000H
F2FFFH
Data flash memory
F1000H
F0FFFH
F0800H
F07FFH
Reserved
Special-function register (2nd SFR)
2 KB
F0000H
EFFFFH
Mirror
Reserved
10000H
0FFFFH
Code flash memory
0EF00H
0EEFFH
Code flash memory
03000H
02FFFH
Code flash memory
00000H
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The PMC register is described below.
Processor mode control register (PMC)
This register sets the flash memory space for mirroring to area from F0000H to FFFFFH.
The PMC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 3-10. Format of Configuration of Processor Mode Control Register (PMC)
Address: FFFFEH After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
PMC
0
0
0
0
0
0
0
MAA
MAA
Cautions 1.
Selection of flash memory space for mirroring to area from F0000H to FFFFFH
0
00000H to 0FFFFH is mirrored to F0000H to FFFFFH
1
10000H to 1FFFFH is mirrored to F0000H to FFFFFH
In products with 64 KB or less flash memory, be sure to clear bit 0 (MAA) of this register to 0
(default value).
2.
After setting the PMC register, wait for at least one instruction and access the mirror area.
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3.1.3 Internal data memory space
The RL78/D1A products incorporate the following RAMs.
Table 3-4. Internal RAM Capacity
Part Number
Internal RAM
R5F10CGBxFB, R5F10CGCxFB, R5F10DGCxFB
2048 8 bits (FF700H to FFEFFH)
R5F10CGDxFB, R5F10DGDxFB, R5F10CLDxFB,
3072 8 bits (FF300H to FFEFFH)
R5F10DLDxFB, R5F10CMDxFB, R5F10DMDxFB
R5F10DGExFB, R5F10DLExFB, R5F10CMExFB,
4096 8 bits (FEF00H to FFEFFH)
R5F10DMExFB, R5F10DPExFB
R5F10DMFxFB, R5F10DPFxFB
6144 8 bits (FE700H to FFEFFH)
R5F10DMGxFB, R5F10DPGxFB
8192 8 bits (FDF00H to FFEFFH)
R5F10DMJxFB, R5F10TPJxFB, R5F10DPJxFB,
16384 8 bits (FBF00H to FFEFFH)
R5F10DSJxFB
R5F10DSKxFB, R5F10DPKxFB
20480 8 bits (FAF00H to FFEFFH)
R5F10DSLxFB, R5F10DPLxFB
24576 8 bits (F9F00H to FFEFFH)
The internal RAM can be used as a data area and a program area where instructions are written and executed. Four
general-purpose register banks consisting of eight 8-bit registers per bank are assigned to the 32-byte area of FFEE0H to
FFEFFH of the internal RAM area. However, instructions cannot be executed by using the general-purpose registers.
The internal RAM is used as stack memory.
Caution 1. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching or as a
stack area.
2. Do not allocate the stack area, data buffers for use by the flash library, arguments of library functions,
branch destinations in the processing of vectored interrupts, or destinations or sources for DMA
transfer to the area from FFE20H to FFEDFH when performing self-programming or rewriting of the
data flash memory.
3. The flash library uses RAM in self-programming and rewriting of the data flash memory.
The target products and start address of the RAM areas used by the flash library are shown below.
R5F10CGDxFB, R5F10DGDxFB, R5F10CLDxFB, R5F10DLDxFB, R5F10CMDxFB, R5F10DMDxFB:
Start address FF300H
R5F10DGExFB, R5F10DLExFB, R5F10CMExFB, R5F10DMExFB, R5F10DPExFB: Start address
FEF00H
R5F10DSKxFB, R5F10DPKxFB: Start address FAF00H
R5F10DSLxFB, R5F10DPLxFB: Start address F9F00H
For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for
RL78 Family (R20UT2944).
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3.1.4 Special function register (SFR) area
On-chip peripheral hardware special function registers (SFRs) are allocated in the area FFF00H to FFFFFH (see Table
3-5 in 3.2.4 Special function registers (SFRs)).
Caution Do not access addresses to which SFRs are not assigned.
3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area
On-chip peripheral hardware special function registers (2nd SFRs) are allocated in the area F0000H to F07FFH (see
Table 3-6 in 3.2.5 Extended Special function registers (2nd SFRs: 2nd Special Function Registers)).
SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area. An instruction that accesses
the extended SFR area, however, is 1 byte longer than an instruction that accesses the SFR area.
Caution Do not access addresses to which extended SFRs are not assigned.
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3.1.6 Data memory addressing
Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the
register or memory relevant to the execution of instructions.
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the
RL78/D1A, based on operability and other considerations.
For areas containing data memory in particular, special
addressing methods designed for the functions of the special function registers (SFR) and general-purpose registers are
available for use. Figures 3-9 to 3-15 show correspondence between data memory and addressing. For details of each
addressing, see 3.4 Addressing for Processing Data Addresses.
Figure 3-11. Correspondence Between Data Memory and Addressing
(R5F10CGD)
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAM
2 KB
FFE20H
FFE1FH
FF700H
FF6FFH
Mirror
49.75 KB
F3000H
F2FFFH
F1000H
F0FFFH
Data flash memory
8 KB
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Direct addressing
Register indirect addressing
F0000H
EFFFFH
Based addressing
Based indexed addressing
Reserved
06000H
05FFFH
Code flash memory
24 KB
00000H
Note Use of part of this area is prohibited by libraries, when using the self-programming function and data flash
function.
Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0),
be sure to initialize the used RAM area + 10 bytes.
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Figure 3-12. Correspondence Between Data Memory and Addressing
(R5F10CGC, R5F10DGC)
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAM
2 KB
FFE20H
FFE1FH
FF700H
FF6FFH
Mirror
49.75 KB
F3000H
F2FFFH
F1000H
F0FFFH
Data flash memory
8 KB
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Direct addressing
Register indirect addressing
F0000H
EFFFFH
Based addressing
Based indexed addressing
Reserved
08000H
07FFFH
Code flash memory
32 KB
00000H
Note Use of part of this area is prohibited by libraries, when using the self-programming function and data flash
function.
Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0),
be sure to initialize the used RAM area + 10 bytes.
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Figure 3-13. Correspondence Between Data Memory and Addressing
(R5F10CGD, R5F10DGD, R5F10CLD, R5F10DLD, R5F10CMD, R5F10DMD)
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAM
3 KB
FFE20H
FFE1FH
FF300H
FF2FFH
Mirror
48.75 KB
F3000H
F2FFFH
F1000H
F0FFFH
Data flash memory
8 KB
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Direct addressing
Register indirect addressing
F0000H
EFFFFH
Based addressing
Based indexed addressing
Reserved
0C000H
0BFFFH
Code flash memory
48 KB
00000H
Note Use of part of this area is prohibited by libraries, when using the self-programming function and data flash
function.
Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0),
be sure to initialize the used RAM area + 10 bytes.
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Figure 3-14. Correspondence Between Data Memory and Addressing
(R5F10DGE, R5F10DLE, R5F10CME, R5F10DME, R5F10DPE)
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAM
4 KB
FFE20H
FFE1FH
FEF00H
FEEFFH
Mirror
47.75 KB
F3000H
F2FFFH
Data flash memory
8 KB
F1000H
F0FFFH
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Direct addressing
Register indirect addressing
F0000H
EFFFFH
Based addressing
Based indexed addressing
Reserved
10000H
0FFFFH
Code flash memory
64 KB
00000H
Note Use of part of this area is prohibited by libraries, when using the self-programming function and data flash
function.
Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0),
be sure to initialize the used RAM area + 10 bytes.
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Figure 3-15. Correspondence Between Data Memory and Addressing
(R5F10DMF, R5F10DPF)
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAM
6 KB
FFE20H
FFE1FH
FE700H
FE6FFH
Mirror
45.75 KB
F3000H
F2FFFH
Data flash memory
8 KB
F1000H
F0FFFH
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Direct addressing
Register indirect addressing
F0000H
EFFFFH
Based addressing
Based indexed addressing
Reserved
18000H
17FFFH
Code flash memory
96 KB
00000H
Note Use of part of this area is prohibited by libraries, when using the self-programming function and data flash
function.
Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0),
be sure to initialize the used RAM area + 10 bytes.
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Figure 3-16. Correspondence Between Data Memory and Addressing
(R5F10DMG, R5F10DPG)
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAM
8 KB
FFE20H
FFE1FH
FDF00H
FDEFFH
Mirror
43.75 KB
F3000H
F2FFFH
Data flash memory
8 KB
F1000H
F0FFFH
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Direct addressing
Register indirect addressing
F0000H
EFFFFH
Based addressing
Based indexed addressing
Reserved
20000H
1FFFFH
Code flash memory
128 KB
00000H
Note Use of part of this area is prohibited by libraries, when using the self-programming function and data flash
function.
Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0),
be sure to initialize the used RAM area + 10 bytes.
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Figure 3-17. Correspondence Between Data Memory and Addressing
(R5F10DMJ, R5F10TPJ, R5F10DPJ, R5F10DSJ)
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAM
16 KB
FFE20H
FFE1FH
FBF00H
FBEFFH
Mirror
35.75 KB
F3000H
F2FFFH
Data flash memory
8 KB
F1000H
F0FFFH
Reserved
F0800H
F07FFH
Special function register (2nd SFR)
2 KB
Direct addressing
Register indirect addressing
F0000H
EFFFFH
Based addressing
Based indexed addressing
Reserved
40000H
3FFFFH
Code flash memory
256 KB
00000H
Note Use of part of this area is prohibited by libraries, when using the self-programming function and data flash
function.
Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0),
be sure to initialize the used RAM area + 10 bytes.
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Figure 3-18. Correspondence Between Data Memory and Addressing
(R5F10DSK, R5F10DPK)
F F F F FH
F F F 2 0H
F F F 1 FH
F F F 0 0H
F F E F FH
F F E E 0H
F F E D FH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAM
20KB
F F E 2 0H
F F E 1 FH
F A F 0 0H
F A E F FH
Mirror
35.75 KB
F 3 0 0 0H
F 2 F F FH
F 1 0 0 0H
F 0 F F FH
Reserved
F 0 8 0 0H
F 0 7 F FH
Special function register (2nd SFR)
2 KB
Direct addressing
Register indirect addressing
F 0 0 0 0H
E F F F FH
Based addressing
Based indexed addressing
Reserved
6 0 0 0 0H
5 F F F FH
0 0 0 0 0H
Note Use of part of this area is prohibited by libraries, when using the self-programming function and data flash
function.
Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0),
be sure to initialize the used RAM area + 10 bytes.
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Figure 3-19. Correspondence Between Data Memory and Addressing
(R5F10DSL, R5F10DP)
F F F F FH
F F F 2 0H
F F F 1 FH
F F F 0 0H
F F E F FH
F F E E 0H
F F E D FH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
SFR addressing
Register addressing
Short direct
addressing
RAM
24 KB
F F E 2 0H
F F E 1 FH
F 9 F 0 0H
F 9 E F FH
Mirror
35.75 KB
F 3 0 0 0H
F 2 F F FH
F 1 0 0 0H
F 0 F F FH
Reserved
F 0 8 0 0H
F 0 7 F FH
Special function register (2nd SFR)
2 KB
Direct addressing
Register indirect addressing
F 0 0 0 0H
E F F F FH
Based addressing
Based indexed addressing
Reserved
8 0 0 0 0H
7 F F F FH
0 0 0 0 0H
Note Use of part of this area is prohibited by libraries, when using the self-programming function and data flash
function.
Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0),
be sure to initialize the used RAM area + 10 bytes.
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3.2 Processor Registers
The RL78/D1A products incorporate the following processor registers.
3.2.1 Control registers
The control registers control the program sequence, statuses and stack memory. The control registers consist of a
program counter (PC), a program status word (PSW) and a stack pointer (SP).
(1) Program counter (PC)
The program counter is a 20-bit register that holds the address information of the next program to be executed.
In normal operation, PC is automatically incremented according to the number of bytes of the instruction to be fetched.
When a branch instruction is executed, immediate data and register contents are set.
Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 3-20. Format of Program Counter
0
19
PC
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags set/reset by instruction execution.
Program status word contents are stored in the stack area upon vectored interrupt request is acknowledged or PUSH
PSW instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions. Reset
signal generation sets the PSW register to 06H.
Figure 3-21. Format of Program Status Word
7
PSW
IE
0
Z
RBS1
AC
RBS0
ISP1
ISP0
CY
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledge operations of the CPU.
When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled.
When 1, the IE flag is set to the interrupt enabled (EI) state and maskable interrupt request acknowledgment is
controlled with an in-service priority flag (ISP1, ISP0), an interrupt mask flag for various interrupt sources, and a
priority specification flag.
The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
(b) Zero flag (Z)
When the operation or comparison result is zero or equal, this flag is set (1). It is reset (0) in all other cases.
(c) Register bank select flags (RBS0, RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is
stored.
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(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases.
(e) In-service priority flags (ISP1, ISP0)
This flag manages the priority of acknowledgeable maskable vectored interrupts. Vectored interrupt requests
specified lower than the value of ISP0 and ISP1 flags by the priority specification flag registers (PRn0L, PRn0H,
PRn1L, PRn1H, PRn2L, PRn2H) (see 21.3 (3)) cannot be acknowledged. Actual request acknowledgment is
controlled by the interrupt enable flag (IE).
Remark n = 0, 1
(f)
Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon
rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal RAM area can be set as
the stack area.
Figure 3-22. Format of Stack Pointer
15
0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the
stack memory.
Each stack operation saves data as shown in Figure 3-18.
Cautions 1. Since reset signal generation makes the SP contents undefined, be sure to initialize the SP
before using the stack.
2. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching
instructions or a stack area.
3. Do not allocate the stack area, data buffers for use by the flash library, arguments of library
functions, branch destinations in the processing of vectored interrupts, or destinations or
sources for DMA transfer to the area from FFE20H to FFEDFH when performing self-programming
or rewriting of the data flash memory.
4. The flash library uses RAM in self-programming and rewriting of the data flash memory.
The target products and start address of the RAM areas used by the flash library are shown
below.
R5F10CGDxFB, R5F10DGDxFB, R5F10CLDxFB, R5F10DLDxFB, R5F10CMDxFB,
R5F10DMDxFB: Start address FF300H
R5F10DGExFB, R5F10DLExFB, R5F10CMExFB, R5F10DMExFB, R5F10DPExFB: Start address
FEF00H
R5F10DSKxFB, R5F10DPKxFB: Start address FAF00H
R5F10DSLxFB, R5F10DPLxFB: Start address F9F00H
For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library
for RL78 Family (R20UT2944).
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3.2.2 General-purpose registers
General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The generalpurpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX,
BC, DE, and HL).
These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute
names (R0 to R7 and RP0 to RP3).
Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4register bank configuration, an efficient program can be created by switching between a register for normal processing and
a register for interrupts for each bank.
Caution
It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching
instructions or as a stack area.
Figure 3-23. Configuration of General-Purpose Registers
(a) Function name
16-bit processing
8-bit processing
FFEFFH
H
Register bank 0
HL
L
FFEF8H
D
Register bank 1
DE
E
FFEF0H
B
BC
Register bank 2
C
FFEE8H
A
AX
Register bank 3
X
FFEE0H
15
0
7
0
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3.2.3 ES and CS registers
The ES register is used for data access and the CS register is used to specify the higher address when a branch
instruction is executed.
The default value of the ES register after reset is 0FH, and that of the CS register is 00H.
Figure 3-24. Configuration of ES and CS Registers
ES
CS
7
6
5
4
3
2
1
0
0
0
0
0
ES3
ES2
ES1
ES0
7
6
5
4
3
2
1
0
0
0
0
0
CS3
CS2
CS1
CS0
Though the data area which can be accessed with 16-bit addresses is the 64 Kbytes from F0000H to FFFFFH, using the
ES register as well extends this to the 1 Mbyte from 00000H to FFFFFH.
Figure 3-25. Extension of Data Area Which Can Be Accessed
!addr16
F 0000H - FFFFH
ES:!addr16
0H - FH
0000H - FFFFH
FFFFFH
Special function register
(SFR) 256 bytes
!addr16
Extended special function register
(2nd SFR) 2 Kbytes
ES:!addr16
Data memory space
F0000H
EFFFFH
Code flash memory
00000H
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3.2.4 Special function registers (SFRs)
Unlike a general-purpose register, each SFR has a special function.
SFRs are allocated to the FFF00H to FFFFFH area.
SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions.
The manipulable bit units, 1, 8, and 16, depend on the SFR type.
Each manipulation bit unit can be specified as follows.
1-bit manipulation
Describe as follows for the 1-bit manipulation instruction operand (sfr.bit).
When the bit name is defined: Bit name
When the bit name is not defined: Register name, Bit number or Address, Bit number
8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).
This
manipulation can also be specified with an address.
16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp).
When
specifying an address, describe an even address.
Table 3-5 gives a list of the SFRs. The meanings of items in the table are as follows.
Symbol
Symbol indicating the address of a special function register. It is a reserved word in the assembler, and is defined
as an sfr variable using the #pragma sfr directive in the compiler. When using the assembler, debugger, and
simulator, symbols can be written as an instruction operand.
R/W
Indicates whether the corresponding SFR can be read or written.
R/W: Read/write enable
R: Read only
W: Write only
Manipulable bit units
“” indicates the manipulable bit unit (1, 8, or 16). “” indicates a bit unit for which manipulation is not possible.
After reset
Indicates each register status upon reset signal generation.
Caution Do not access addresses to which extended SFRs are not assigned.
Remark
For extended SFRs (2nd SFRs), see 3.2.5 Extended special function registers (2nd SFRs: 2nd Special
Function Registers).
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Table 3-5. SFR List (1/5)
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit Range
After Reset
1-bit
8-bit
16-bit
FFF00H
Port register 0
P0
R/W
00H
FFF01H
Port register 1
P1
R/W
00H
FFF02H
Port register 2
P2
R/W
00H
FFF03H
Port register 3
P3
R/W
00H
FFF04H
Port register 4
P4
R/W
00H
FFF05H
Port register 5
P5
R/W
00H
FFF06H
Port register 6
P6
R/W
00H
FFF07H
Port register 7
P7
R/W
00H
FFF08H
Port register 8
P8
R/W
00H
FFF09H
Port register 9
P9
R/W
00H
P10
R/W
00H
P11
R/W
00H
Note
FFF0AH
Port register 10
FFF0BH
Port register 11
FFF0CH
Port register 12
P12
R/W
00H
FFF0DH
Port register 13
P13
R/W
00H
FFF0EH
Port register 14
P14
R/W
00H
FFF0FH
Port register 15
P15
R/W
00H
FFF10H
Serial data register 00
SDR00
R/W
0000H
SDR00L
R/W
Serial data register 01
SDR01
R/W
SDR01L
R/W
Serial data register 10
SDR10
R/W
SDR10L
R/W
Serial data register 11
SDR11
R/W
SDR11L
R/W
Timer data register 00
TDR00
R/W
0000H
Timer data register 01
TDR01
R/W
0000H
10-bit A/D conversion result register
ADCR
R
0000H
ADCRH
R
00H
Note
FFF11H
FFF12H
FFF13H
FFF14H
FFF15H
FFF16H
FFF17H
FFF18H
0000H
0000H
0000H
FFF19H
FFF1AH
FFF1BH
FFF1EH
FFF1FH
8-bit A/D conversion result register
FFF20H
Port mode register 0
PM0
R/W
FFH
FFF21H
Port mode register 1
PM1
R/W
FFH
FFF22H
Port mode register 2
PM2
R/W
FFH
FFF23H
Port mode register 3
PM3
R/W
FFH
FFF24H
Port mode register 4
PM4
R/W
FFH
FFF25H
Port mode register 5
PM5
R/W
FFH
FFF26H
Port mode register 6
PM6
R/W
FFH
FFF27H
Port mode register 7
PM7
R/W
FFH
FFF28H
Port mode register 8
PM8
R/W
FFH
FFF29H
FFF2AH
FFF2BH
FFF2CH
Port mode register 9
Port mode register 10
Port mode register 11
Port mode register 12
Note
Note
Note
PM9
R/W
FFH
PM10
R/W
FFH
PM11
R/W
FFH
PM12
R/W
FFH
Note 128-pin products only.
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Table 3-5. SFR List (2/5)
Address
Special Function Register (SFR) Name
Symbol
R/W
1-bit
8-bit
16-bit
After Reset
FFF2DH
Port mode register 13
PM13
FFF2EH
Port mode register 14
PM14
R/W
FFH
FFF2FH
Port mode register 15
PM15
R/W
FFH
FFF30H
A/D converter mode register 0
ADM0
R/W
00H
FFF31H
Analog input channel specification register
ADS
R/W
00H
FFF32H
A/D converter mode register 1
ADM1
R/W
00H
FFF34H
Watch error correction register
SUBCUDW
R/W
0000H
FFF36H
RTC1Hz pin select register
RTCSEL
R/W
00H
FFF37H
Stepper motor port mode control register
SMPC
R/W
00H
FFF38H
External interrupt rising edge enable register 0
EGP0
R/W
00H
FFF39H
External interrupt falling edge enable register 0
EGN0
R/W
00H
FFF3CH
Serial communication pin select register 0
STSEL0
R/W
00H
FFF3DH
Serial communication pin select register 1
STSEL1
R/W
00H
FFF3EH
Timer input select else register
TISELSE
R/W
00H
FFF3FH
Sound generator pin select register
SGSEL
R/W
00H
FFF40H
LCD mode register
LCDMD
R/W
00H
FFF41H
LCD display mode register
LCDM
R/W
00H
FFF42H
LCD clock control register
LCDC0
R/W
00H
LBDATA
R/W
0000H
LBDATAL
R/W
00H
LBDATAR
R/W
0000H
FFF44H
FFF46H
FFF48H
FFF4AH
FFF4CH
FFF4EH
LCD Bus Interface data register
Note
LCD Bus Interface read data register
Note
R/W
Manipulable Bit Range
FFH
LBDATARL
R/W
00H
LIN-UART0 transmit data register
UF0TX
R/W
0000H
LIN-UART0 8-bit transmit data register
UF0TXB
R/W
00H
LIN-UART0 receive data register
UF0RX
R
0000H
UF0RXB
R
00H
0000H
LIN-UART1 transmit data register
UF1TX
R/W
LIN-UART1 8-bit transmit data register
UF1TXB
R/W
00H
LIN-UART1 receive data register
UF1RX
R
0000H
UF1RXB
R
00H
Note 128-pin products only.
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Table 3-5. SFR List (3/5)
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit Range
1-bit
8-bit
16-bit
After Reset
FFF50H
Interval timer control register
ITMC
R/W
7FFFH
FFF52H
Second count register
SEC
R/W
00H
FFF53H
Minute count register
MIN
R/W
00H
FFF54H
Hour count register
HOUR
R/W
12H
FFF55H
Week count register
WEEK
R/W
00H
FFF56H
Day count register
DAY
R/W
01H
FFF57H
Month count register
MONTH
R/W
01H
FFF58H
Year count register
YEAR
R/W
00H
FFF59H
Watch error correction register
SUBCUD
R/W
00H
FFF5AH
Alarm minute register
ALARMWM
R/W
FFF5BH
Alarm hour register
ALARMWH
R/W
FFF5CH
Alarm week register
ALARMWW
R/W
00H
FFF5DH
Real time counter control register 0
RTCC0
R/W
00H
FFF5EH
Real time counter control register 1
RTCC1
R/W
00H
FFF64H
Timer data register 02
TDR02
R/W
0000H
FFF66H
Timer data register 03
TDR03
R/W
0000H
FFF68H
Timer data register 04
TDR04
R/W
0000H
FFF6AH
Timer data register 05
TDR05
R/W
0000H
FFF6CH
Timer data register 06
TDR06
R/W
0000H
FFF6EH
Timer data register 07
TDR07
R/W
0000H
FFF70H
Timer data register 10
TDR10
R/W
0000H
FFF72H
Timer data register 11
TDR11
R/W
0000H
FFF74H
Timer data register 12
TDR12
R/W
0000H
FFF76H
Timer data register 13
TDR13
R/W
0000H
FFF78H
Timer data register 14
TDR14
R/W
0000H
FFF7AH
Timer data register 15
TDR15
R/W
0000H
FFF7CH
Timer data register 16
TDR16
R/W
0000H
FFF7EH
Timer data register 17
TDR17
R/W
0000H
FFF90H
Timer data register 20
TDR20
R/W
0000H
FFF92H
Timer data register 21
TDR21
R/W
0000H
FFF94H
Timer data register 22
TDR22
R/W
0000H
FFF96H
Timer data register 23
TDR23
R/W
0000H
FFF98H
Timer data register 24
TDR24
R/W
0000H
FFF9AH
Timer data register 25
TDR25
R/W
0000H
FFF9CH
Timer data register 26
TDR26
R/W
0000H
FFF9EH
Timer data register 27
TDR27
R/W
0000H
00H
12H
Note
Note The value of this register is 00H if the AMPM bit (bit 3 of real-time clock control register 0 (RTCC0)) is set to 1 after
reset.
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Table 3-5. SFR List (4/5)
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit Range
1-bit
8-bit
16-bit
After Reset
FFFA0H
Clock operation mode control register
CMC
R/W
00H
FFFA1H
Clock operation status control register
CSC
R/W
C0H
FFFA2H
Oscillation stabilization time counter status register
OSTC
R
00H
FFFA3H
Oscillation stabilization time select register
OSTS
R/W
07H
FFFA4H
System clock control register
CKC
R/W
00H
FFFA5H
Clock output select register 0
CKS0
R/W
00H
FFFA8H
Reset control flag register
RESF
R
Undefined
Note1
FFFA9H
Voltage detection register
LVIM
R/W
00H
FFFAAH
Voltage detection level register
LVIS
R/W
00H/01H/81H
FFFABH
Watchdog timer enable register
WDTE
R/W
1AH/9AH
FFFACH
CRC input register
CRCIN
R/W
00H
FFFB0H
DMA SFR address register 0
DSA0
R/W
00H
FFFB1H
DMA SFR address register 1
DSA1
R/W
00H
FFFB2H
DMA RAM address register 0L
DRA0L
FFFB3H
DMA RAM address register 0H
DRA0H
FFFB4H
DMA RAM address register 1L
DRA1L
FFFB5H
DMA RAM address register 1H
DRA1H
FFFB6H
DMA byte count register 0L
DBC0L
FFFB7H
DMA byte count register 0H
DBC0H
FFFB8H
DMA byte count register 1L
DBC1L
R/W
FFFB9H
DMA byte count register 1H
DBC1H
R/W
FFFBAH
DMA mode control register 0
DMC0
R/W
DRA0
DRA1
DBC0
DBC1
R/W
R/W
R/W
R/W
R/W
R/W
Note2
00H
00H
00H
00H
00H
00H
00H
00H
DMA mode control register 1
DMC1
R/W
00H
FFFBCH
DMA operation control register 0
DRC0
R/W
00H
FFFBDH
DMA operation control register 1
DRC1
R/W
00H
FFFD0H
Interrupt request flag register 2L
IF2L
R/W
00H
FFFD1H
Interrupt request flag register 2H
IF2H
R/W
FFFD2H
Interrupt request flag register 3L
IF3L
R/W
00H
FFFD3H
Interrupt request flag register 3H
IF3H
R/W
00H
FFFD4H
Interrupt mask flag register 2L
MK2L
R/W
FFH
FFFD5H
Interrupt mask flag register 2H
MK2H
R/W
FFFD6H
Interrupt mask flag register 3L
MK3L
MK3
R/W
FFH
FFFD7H
Interrupt mask flag register 3H
MK3H
R/W
FFH
FFFD8H
Priority specification flag register 02L
PR02L
PR02
R/W
FFH
FFFD9H
Priority specification flag register 02H
PR02H
R/W
IF3
MK2
Note4
00H
FFFBBH
IF2
Note3
00H
FFH
FFH
Notes 1. The reset value of the RESF register varies depending on the reset source.
2. The reset value of the LVIM register varies depending on the reset source.
3. The reset value of the LVIS register varies depending on the reset source and the setting of the option byte.
4. The reset value of the WDTE register is determined by the setting of the option byte.
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Table 3-5. SFR List (5/5)
Address
Special Function Register (SFR) Name
Symbol
FFFDAH
Priority specification flag register 02L
PR03L
FFFDBH
Priority specification flag register 03H
PR03H
FFFDCH
Priority specification flag register 12L
PR12L
FFFDDH
Priority specification flag register 12H
PR12H
FFFDEH
Priority specification flag register 13L
PR13L
FFFDFH
Priority specification flag register 13H
PR13H
FFFE0H
Interrupt request flag register 0L
IF0L
FFFE1H
Interrupt request flag register 0H
IF0H
FFFE2H
Interrupt request flag register 1L
IF1L
FFFE3H
Interrupt request flag register 1H
IF1H
FFFE4H
Interrupt mask flag register 0L
MK0L
FFFE5H
Interrupt mask flag register 0H
MK0H
FFFE6H
Interrupt mask flag register 1L
MK1L
FFFE7H
Interrupt mask flag register 1H
MK1H
R/W
PR03
PR13
IF0
IF1
MK0
MK1
After Reset
1-bit
8-bit
16-bit
FFH
R/W
FFH
R/W
R/W
PR12
Manipulable Bit Range
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FFH
FFH
FFH
00H
00H
00H
00H
FFH
FFH
FFH
FFH
R/W
R/W
PR01
R/W
R/W
PR10
R/W
R/W
R/W
R/W
R/W
0000H
MDAH/MULB
R/W
0000H
Multiplication/division data register B (H)
MDBH/MULOH
R/W
0000H
Multiplication/division data register B (L)
MDBL/MULOL
R/W
0000H
Processor mode control register
PMC
R/W
00H
FFFE8H
Priority specification flag register 00L
PR00L
FFFE9H
Priority specification flag register 00H
PR00H
PR00
FFFEAH
Priority specification flag register 01L
PR01L
FFFEBH
Priority specification flag register 01H
PR01H
FFFECH
Priority specification flag register 10L
PR10L
FFFEDH
Priority specification flag register 10H
PR10H
FFFEEH
Priority specification flag register 11L
PR11L
FFFEFH
Priority specification flag register 11H
PR11H
FFFF0H
Multiplication/division data register A (L)
MDAL/MULA
Multiplication/division data register A (H)
PR11
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFFF1H
FFFF2H
FFFF3H
FFFF4H
FFFF5H
FFFF6H
FFFF7H
FFFFEH
nd
Remark For extended SFRs (2
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SFRs), see Table 3-6 Extended SFR (2
SFR) List.
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3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers)
Unlike a general-purpose register, each extended SFR (2
nd
SFR) has a special function.
Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to
FFFFFH) are allocated to this area. An instruction that accesses the extended SFR area, however, is 1 byte longer than
an instruction that accesses the SFR area.
Extended SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation
instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type.
Each manipulation bit unit can be specified as follows.
1-bit manipulation
Describe as follows for the 1-bit manipulation instruction operand (!addr16.bit)
When the bit name is defined: Bit name
When the bit name is not defined: Register name, Bit number or Address, Bit number
8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (!addr16). This
manipulation can also be specified with an address.
16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (!addr16). When
specifying an address, describe an even address.
Table 3-6 gives a list of the extended SFRs. The meanings of items in the table are as follows.
Symbol
Symbol indicating the address of an extended SFR. It is a reserved word in the assembler, and is defined as an sfr
variable using the #pragma sfr directive in the compiler. When using the assembler, debugger, and simulator,
symbols can be written as an instruction operand.
R/W
Indicates whether the corresponding extended SFR can be read or written.
R/W: Read/write enable
R:
Read only
W:
Write only
Manipulable bit units
“” indicates the manipulable bit unit (1, 8, or 16). “” indicates a bit unit for which manipulation is not possible.
After reset
Indicates each register status upon reset signal generation.
Caution Do not access addresses to which extended SFRs are not assigned.
Remark
For SFRs in the SFR area, see 3.2.4 Special function registers (SFRs).
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Table 3-6. Extended SFR (2nd SFR) List (1/21)
Address
Special Function Register (SFR) Name
F0010H A/D converter mode register 2
Symbol
ADM2
R/W
Manipulable Bit Range After Reset
1-bit
8-bit
16-bit
R/W
00H
F0011H Conversion result comparison upper limit setting register
ADUL
R/W
FFH
F0012H Conversion result comparison lower limit setting register
ADLL
R/W
00H
ADTES
R/W
00H
F0014H RESET output control register Note
F0016H STOP status output control register Note
RESOC
R/W
00H
STPSTC
R/W
00H
F0018H LCD Bus Interface mode register Note
LBCTL
R/W
00H
F0019H LCB Bus Interface cycle control register Note
F001AH LCB Bus Interface wait control register Note
F001FH DMA trigger selection register Note
LBCYC
R/W
02H
LBWST
R/W
00H
DMATSEL
R/W
00H
F0030H Pull-up resistor option register 0
PU0
R/W
00H
F0031H Pull-up resistor option register 1
PU1
R/W
00H
F0033H Pull-up resistor option register 3
PU3
R/W
00H
F0034H Pull-up resistor option register 4
PU4
R/W
01H
F0035H Pull-up resistor option register 5
PU5
R/W
00H
F0036H Pull-up resistor option register 6
PU6
R/W
00H
F0037H Pull-up resistor option register 7
PU7
R/W
00H
F0038H Pull-up resistor option register 8
PU8
R/W
00H
F0039H Pull-up resistor option register 9
PU9
R/W
00H
F0013H A/D test register
F003DH Pull-up resistor option register 13
PU13
R/W
00H
F003EH Pull-up resistor option register 14
PU14
R/W
00H
F0040H Port input mode register 0
F003AH Pull-up resistor option register 10 Note
F003BH Pull-up resistor option register 11 Note
F003CH Pull-up resistor option register 12 Note
PIM0
R/W
00H
PU10
R/W
00H
PU11
R/W
00H
PU12
R/W
00H
F0041H Port input mode register 1
PIM1
R/W
00H
F0043H Port input mode register 3
PIM3
R/W
00H
F0045H Port input mode register 5
PIM5
R/W
00H
F0046H Port input mode register 6
PIM6
R/W
00H
F0047H Port input mode register 7
PIM7
R/W
00H
00H
F004BH Port input mode register 11 Note
PIM11
R/W
F004DH Port input mode register 13
PIM13
R/W
00H
F0050H LCD port function register 0
LCDPF0
R/W
00H
F0051H LCD port function register 1
LCDPF1
R/W
00H
F0053H LCD port function register 3
LCDPF3
R/W
00H
LCDPF4
R/W
00H
F0055H LCD port function register 5
LCDPF5
R/W
00H
F0057H LCD port function register 7
LCDPF7
R/W
00H
F0058H LCD port function register 8
LCDPF8
R/W
00H
F0059H LCD port function register 9
LCDPF9
R/W
00H
LCDPF10
R/W
00H
LCDPF11
R/W
00H
F0054H LCD port function register 4 Note
F005AH LCD port function register 10 Note
F005BH LCD port function register 11 Note
F005CH LCD port function register 12 Note
LCDPF12
R/W
00H
F005DH LCD port function register 13
LCDPF13
R/W
00H
F0060H Noise filter enable register for each channel of TAU unit0
TNFEN0
R/W
00H
F0061H Sampling clock select of noise filter for unit0 (2set)
TNFSMP0
R/W
00H
Note 128-pin products only.
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Table 3-6. Extended SFR (2nd SFR) List (2/21)
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit Range
After Reset
1-bit
8-bit
16-bit
F0062H
Noise filter clock select register for each channel of TAU
unit0
TNFCS0
R/W
00H
F0064H
Noise filter enable register for each channel of TAU unit1
TNFEN1
R/W
00H
F0065H
Sampling clock select of noise filter for unit1 (2set)
TNFSMP1
R/W
00H
F0066H
Noise filter clock select register for each channel of TAU
unit1
TNFCS1
R/W
00H
F0068H
Noise filter enable register for each channel of TAU unit2
TNFEN2
R/W
00H
F0069H
Sampling clock select of noise filter for unit2(2set)
TNFSMP2
R/W
00H
F006AH Noise filter clock select register for each channel of TAU
unit2
TNFCS2
R/W
00H
F006EH A/D port configuration register
ADPC
R/W
00H
F006FH
Port output mode register
POM
R/W
00H
F0070H
Timer input select register 00
TIS00
R/W
00H
F0071H
Timer input select register 01
TIS01
R/W
00H
F0072H
Timer input select register 10
TIS10
R/W
00H
F0073H
Timer input select register 11
TIS11
R/W
00H
F0074H
Timer input select register 20
TIS20
R/W
00H
F0075H
Timer input select register 21
TIS21
R/W
00H
F0076H
Timer output select register 00
TOS00
R/W
00H
F0077H
Timer output select register 01
TOS01
R/W
00H
F0078H
Illegal-memory access detection control register
IAWCTL
R/W
00H
F0079H
Timer output select register 10
TOS10
R/W
00H
F007AH Timer output select register 11
TOS11
R/W
00H
F007BH Timer output select register 20
TOS20
R/W
00H
F007CH Timer output select register 21
TOS21
R/W
00H
F0090H
DFLCTL
R/W
F00A0H High-speed on-chip oscillator trimming register
HIOTRM
R/W
Undefined
F00E0H Multiplication/division data register C (L)
MDCL
R/W
0000H
F00E2H Multiplication/division data register C (H)
MDCH
R/W
0000H
F00E8H Multiplication/division control register
MDUC
R/W
00H
F00F0H
Peripheral enable register 0
PER0
R/W
00H
F00F1H
Peripheral enable register 1
PER1
R/W
00H
F00F2H
Peripheral clock select register
PCKSEL
R/W
00H
00H
Data flash control register
00H
Note
F00F3H
Operation speed mode control register
OSMC
R/W
F00F5H
RAM parity error control register
RPECTL
R/W
00H
F00F8H
FMP clock division selction register
MDIV
R/W
00H
F00F9H
RTC clock selection register
RTCCL
R/W
00H
R
Undefined
F00FAH CLM reset control flag register
RESFCLM
F00FBH POC reset confirm register
POCRES
R/W
00H
F00FCH Specific register manipulation protection register
GUARD
R/W
00H
F00FEH BCD adjust result register
BCDADJ
R
Undefined
F0100H
Serial status register 00
SSR00
R
0000H
SSR00L
R
F0102H Serial status register 01
SSR01
R
SSR01L
R
0000H
Note The reset value differs for each chip.
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Table 3-6. Extended SFR (2nd SFR) List (3/21)
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit Range After Reset
1-bit
8-bit
16-bit
F0104H Serial flag clear trigger register 00
SIR00L
SIR00
R/W
0000H
F0106H Serial flag clear trigger register 01
SIR01L
SIR01
R/W
0000H
F0108H Serial mode register 00
SMR00
R/W
0020H
F010AH Serial mode register 01
SMR01
R/W
0020H
F010CH Serial communication operation setting register 00
SCR00
R/W
0087H
F010EH Serial communication operation setting register 01
SCR01
R/W
0087H
F0110H
Serial channel enable status register 0
SE0L
SE0
R
0000H
F0112H
Serial channel start trigger register 0
SS0L
SS0
R/W
0000H
F0114H
Serial channel stop trigger register 0
ST0L
ST0
R/W
0000H
F0116H
Serial clock select register 0
SPS0L
SPS0
R/W
0000H
F0118H
Serial output register 0
R/W
0303H
SOE0L
SOE0
R/W
0000H
SOL0
F011AH Serial output enable register 0
SO0
F0120H
Serial output level register 0
SOL0L
R/W
0000H
F0128H
PLL status register
PLLSTS
R
00H
F0129H
PLL control register
PLLCTL
R/W
00H
F0130H
Serial status register 10
SSR10L SSR10
R
0000H
F0132H
Serial status register 11
SSR11L SSR11
R
0000H
F0134H
Serial flag clear trigger register 10
SIR10L
SIR10
R/W
0000H
F0136H
Serial flag clear trigger register 11
SIR11L
SIR11
R/W
0000H
F0138H
Serial mode register 10
SMR10
R/W
0020H
F013AH Serial mode register 11
SMR11
R/W
0020H
F013CH Serial communication operation setting register 10
SCR10
R/W
0087H
F013EH Serial communication operation setting register 11
SCR11
R/W
0087H
F0140H
SE1L
R
0000H
Serial channel enable status register 1
SE1
F0142H
Serial channel start trigger register 1
SS1L
SS1
R/W
0000H
F0144H
Serial channel stop trigger register 1
ST1L
ST1
R/W
0000H
F0146H
Serial clock select register 1
SPS1L
SPS1
R/W
0000H
F0148H
Serial output register 1
SO1L
SO1
R/W
0303H
F014AH Serial output enabel register 1
SOE1L
SOE1
R/W
0000H
F0150H
Serial output level register 1
SOL1L
SOL1
R/W
0000H
F0158H
Compare control register 4
MCMPC4
R/W
00H
F015CH ZPD detection voltage setting register0/ZPD analog input
control
ZPDS0
R/W
00H
F015DH ZPD detection voltage setting register1/ZPD analog input
control
ZPDS1
R/W
00H
F015EH ZPD flag detection clock setting register
CMPCTL
R/W
00H
F015FH ZPD operation control register
ZPDEN
R/W
00H
F0160H
MCNTC0
R/W
00H
F0162H
Compare control register 0
Compare register 1HW
MCMP1HW
R/W
0000H
Compare register 10
MCMP10
R/W
00H
F0163H
Compare register 11
MCMP11
R/W
00H
F0164H
Compare register 2HW
MCMP2HW
R/W
0000H
Compare register 20
MCMP20
R/W
00H
F0165H
Compare register 21
MCMP21
R/W
00H
F0166H
Compare register 3HW
MCMP3HW
R/W
0000H
Compare register 30
MCMP30
R/W
00H
Compare register 31
MCMP31
R/W
00H
F0167H
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Table 3-6. Extended SFR (2nd SFR) List (4/21)
Address
F0168H
F0169H
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit Range After Reset
1-bit
8-bit
16-bit
Compare register 4HW
MCMP4HW
R/W
0000H
Compare register 40
MCMP40
R/W
00H
MCMP41
R/W
00H
MCMPC1
R/W
00H
Compare register 41
F016AH Compare control register 1
F016CH Compare control register 2
MCMPC2
R/W
00H
F016EH Compare control register 3
MCMPC3
R/W
00H
F0170H
DMA SFR address register 2
DSA2
R/W
00H
F0171H
DMA SFR address register 3
DSA3
R/W
00H
DMA RAM address register 2
DRA2
R/W
0000H
DMA RAM address register 2L
DRA2L
R/W
00H
F0173H
DMA RAM address register 2H
DRA2H
R/W
00H
F0174H
DMA RAM address register 3
DRA3
R/W
0000H
DMA RAM address register 3L
DRA3L
R/W
00H
F0172H
F0175H
DMA RAM address register 3H
DRA3H
R/W
00H
F0176H
DMA byte count register 2
DBC2
R/W
0000H
DMA byte count register 2L
DBC2L
R/W
00H
DMA byte count register 2H
DBC2H
R/W
00H
F0177H
DMA byte count register 3
DBC3
R/W
0000H
DMA byte count register 3L
DBC3L
R/W
00H
DMA byte count register 3H
DBC3H
R/W
00H
F017AH DMA mode control register 2
DMC2
R/W
00H
F017BH DMA mode control register 3
DMC3
R/W
00H
F017CH DMA operation control register 2
DRC2
R/W
00H
F017DH DMA operation control register 3
DRC3
R/W
00H
F017FH DMA all-channel forced wait register
DWAITALL
R/W
00H
F0180H
Timer counter register 00
TCR00
R
FFFFH
F0182H
Timer counter register 01
TCR01
R
FFFFH
F0184H
Timer counter register 02
TCR02
R
FFFFH
F0186H
Timer counter register 03
TCR03
R
FFFFH
F0188H
F0178H
F0179H
Timer counter register 04
TCR04
R
FFFFH
F018AH Timer counter register 05
TCR05
R
FFFFH
F018CH Timer counter register 06
TCR06
R
FFFFH
F018EH Timer counter register 07
TCR07
R
FFFFH
F0190H
Timer mode register 00
TMR00
R/W
0000H
F0192H
Timer mode register 01
TMR01
R/W
0000H
F0194H
Timer mode register 02
TMR02
R/W
0000H
F0196H
Timer mode register 03
TMR03
R/W
0000H
F0198H
Timer mode register 04
TMR04
R/W
0000H
F019AH Timer mode register 05
TMR05
R/W
0000H
F019CH Timer mode register 06
TMR06
R/W
0000H
F019EH Timer mode register 07
TMR07
R/W
0000H
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Table 3-6. Extended SFR (2nd SFR) List (5/21)
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit Range After Reset
1-bit
8-bit
16-bit
F01A0H Timer status register 00
TSR00L
TSR00
R
0000H
F01A2H Timer status register 01
TSR01L
TSR01
R
0000H
F01A4H Timer status register 02
TSR02L
TSR02
R
0000H
F01A6H Timer status register 03
TSR03L
TSR03
R
0000H
F01A8H Timer status register 04
TSR04L
TSR04
R
0000H
F01AAH Timer status register 05
TSR05L
TSR05
R
0000H
F01ACH Timer status register 06
TSR06L
TSR06
R
0000H
F01AEH Timer status register 07
TSR07L
TSR07
R
0000H
F01B0H Timer channel enable status register 0
TE0L
TE0
R
0000H
F01B2H Timer channel start register 0
TS0L
TS0
R/W
0000H
F01B4H Timer channel stop register 0
TT0L
TT0
F01B6H Timer clock select register 0
TPS0
F01B8H Timer output register 0
TO0L
F01BAH Timer output enable register 0
TOE0L
F01BCH Timer output level register 0
F01BEH Timer output mode register 0
F01C0H Timer counter register 10
R/W
0000H
R/W
0000H
TO0
R/W
0000H
TOE0
R/W
0000H
TOL0L
TOL0
R/W
0000H
TOM0L
TOM0
R/W
0000H
TCR10
R
FFFFH
F01C2H Timer counter register 11
TCR11
R
FFFFH
F01C4H Timer counter register 12
TCR12
R
FFFFH
F01C6H Timer counter register 13
TCR13
R
FFFFH
F01C8H Timer counter register 14
TCR14
R
FFFFH
F01CAH Timer counter register 15
TCR15
R
FFFFH
F01CCH Timer counter register 16
TCR16
R
FFFFH
F01CEH Timer counter register 17
TCR17
R
FFFFH
F01D0H Timer mode register 10
TMR10
R/W
0000H
F01D2H Timer mode register 11
TMR11
R/W
0000H
F01D4H Timer mode register 12
TMR12
R/W
0000H
F01D6H Timer mode register 13
TMR13
R/W
0000H
F01D8H Timer mode register 14
TMR14
R/W
0000H
F01DAH Timer mode register 15
TMR15
R/W
0000H
F01DCH Timer mode register 16
TMR16
R/W
0000H
F01DEH Timer mode register 17
TMR17
R/W
0000H
F01E0H Timer status register 10
TSR10L
TSR10
R
0000H
F01E2H Timer status register 11
TSR11L
TSR11
R
0000H
F01E4H Timer status register 12
TSR12L
TSR12
R
0000H
F01E6H Timer status register 13
TSR13L
TSR13
R
0000H
F01E8H Timer status register 14
TSR14L
TSR14
R
0000H
F01EAH Timer status register 15
TSR15L
TSR15
R
0000H
F01ECH Timer status register 16
TSR16L
TSR16
R
0000H
F01EEH Timer status register 17
TSR17L
TSR17
R
0000H
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (6/21)
Address
Special Function Register (SFR) Name
F01F0H Timer channel enable status register 1
Symbol
TE1L
TE1
R/W
Manipulable Bit Range After Reset
1-bit
8-bit
16-bit
R
0000H
F01F2H Timer channel start register 1
TS1L
TS1
R/W
0000H
F01F4H Timer channel stop register 1
TT1L
TT1
R/W
0000H
F01F6H Timer clock select register 1
TPS1
R/W
0000H
F01F8H Timer output register 1
TO1L
TO1
R/W
0000H
F01FAH Timer output enable register 1
TOE1L
TOE1
R/W
0000H
F01FCH Timer output level register 1
TOL1L
TOL1
R/W
0000H
F01FEH Timer output mode register 1
TOM1L
TOM1
R/W
0000H
F0200H
Timer counter register 20
TCR20
R
FFFFH
F0202H
Timer counter register 21
TCR21
R
FFFFH
F0204H
Timer counter register 22
TCR22
R
FFFFH
F0206H
Timer counter register 23
TCR23
R
FFFFH
F0208H
Timer counter register 24
TCR24
R
FFFFH
F020AH Timer counter register 25
TCR25
R
FFFFH
F020CH Timer counter register 26
TCR26
R
FFFFH
F020EH Timer counter register 27
TCR27
R
FFFFH
F0210H
Timer mode register 20
TMR20
R/W
0000H
F0212H
Timer mode register 21
TMR21
R/W
0000H
F0214H
Timer mode register 22
TMR22
R/W
0000H
F0216H
Timer mode register 23
TMR23
R/W
0000H
F0218H
Timer mode register 24
TMR24
R/W
0000H
F021AH Timer mode register 25
TMR25
R/W
0000H
F021CH Timer mode register 26
TMR26
R/W
0000H
F021EH Timer mode register 27
TMR27
R/W
0000H
F0220H
Timer status register 20
TSR20L
TSR20
R
0000H
F0222H
Timer status register 21
TSR21L
TSR21
R
0000H
F0224H
Timer status register 22
TSR22L
TSR22
R
0000H
F0226H
Timer status register 23
TSR23L
TSR23
R
0000H
F0228H
Timer status register 24
TSR24L
TSR24
R
0000H
F022AH Timer status register 25
TSR25L
TSR25
R
0000H
F022CH Timer status register 26
TSR26L
TSR26
R
0000H
F022EH Timer status register 27
TSR27L
TSR27
R
0000H
F0230H
TE2L
TE2
R
0000H
Timer channel enable status register 2
F0232H
Timer channel start trigger register 2
TS2L
TS2
R/W
0000H
F0234H
Timer channel stop trigger register 2
TT2L
TT2
R/W
0000H
F0236H
Timer clock select register 2
TPS2
R/W
0000H
F0238H
Timer output register 2
TO2L
TO2
R/W
0000H
F023AH Timer output enable register 2
TOE2L
TOE2
R/W
0000H
F023CH Timer output level register 2
TOL2L
TOL2
R/W
0000H
F023EH Timer output mode register 2
TOM2L
TOM2
R/W
0000H
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (7/21)
Address
F0240H
Special Function Register (SFR) Name
LIN-UART0 control register 0
Symbol
R/W
Manipulable Bit Range After Reset
1-bit
8-bit
16-bit
UF0CTL0
R/W
10H
14H
F0241H
LIN-UART0 option control register 0
UF0OPT0
R/W
F0242H
LIN-UART0 control register 1
UF0CTL1
R/W
0FFFH
F0244H
LIN-UART0 option control register 1
UF0OPT1
R/W
00H
F0245H
LIN-UART0 option control register 2
UF0OPT2
R/W
00H
F0246H
LIN-UART0 status register
UF0STR
R
0000H
F0248H
LIN-UART0 status clear register
UF0STC
R/W
0000H
F024AH
LIN-UART0 wait transmit data register
UF0WTX
R/W
0000H
UF0WTXB
R/W
00H
00H
LIN-UART0 8-bit wait transmit data register
F024EH
LIN-UART0 ID setting register
UF0ID
R/W
F024FH
LIN-UART0 buffer register 0
UF0BUF0
R/W
00H
F0250H
LIN-UART0 buffer register 1
UF0BUF1
R/W
00H
F0251H
LIN-UART0 buffer register 2
UF0BUF2
R/W
00H
F0252H
LIN-UART0 buffer register 3
UF0BUF3
R/W
00H
F0253H
LIN-UART0 buffer register 4
UF0BUF4
R/W
00H
F0254H
LIN-UART0 buffer register 5
UF0BUF5
R/W
00H
UF0BUF6
R/W
00H
00H
F0255H
LIN-UART0 buffer register 6
F0256H
LIN-UART0 buffer register 7
UF0BUF7
R/W
F0257H
LIN-UART0 buffer register 8
UF0BUF8
R/W
00H
F0258H
LIN-UART0 buffer control register
UF0BUCTL
R/W
0000H
F0260H
LIN-UART1 control register 0
UF1CTL0
R/W
10H
F0261H
LIN-UART1 option control register 0
UF1OPT0
R/W
14H
F0262H
LIN-UART1 control register 1
UF1CTL1
R/W
0FFFH
F0264H
LIN-UART1 option control register 1
UF1OPT1
R/W
00H
UF1OPT2
R/W
00H
F0265H
LIN-UART0 option control register 2
F0266H
LIN-UART1 status register
UF1STR
R
0000H
F0268H
LIN-UART1 status clear register
UF1STC
R/W
0000H
F026AH
LIN-UART1 wait transmit data register
UF1WTX
R/W
0000H
LIN-UART1 8-bit wait transmit data register
UF1WTXB
R/W
00H
F026EH
LIN-UART1 ID setting register
UF1ID
R/W
00H
F026FH
LIN-UART1 buffer register 0
UF1BUF0
R/W
00H
F0270H
LIN-UART1 buffer register 1
UF1BUF1
R/W
00H
UF1BUF2
R/W
00H
00H
F0271H
LIN-UART1 buffer register 2
F0272H
LIN-UART1 buffer register 3
UF1BUF3
R/W
F0273H
LIN-UART1 buffer register 4
UF1BUF4
R/W
00H
F0274H
LIN-UART1 buffer register 5
UF1BUF5
R/W
00H
F0275H
LIN-UART1 buffer register 6
UF1BUF6
R/W
00H
F0276H
LIN-UART1 buffer register 7
UF1BUF7
R/W
00H
F0277H
LIN-UART1 buffer register 8
UF1BUF8
R/W
00H
F0278H
LIN-UART1 buffer control register
UF1BUCTL
R/W
0000H
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (8/21)
Address
F0280H
Special Function Register (SFR) Name
Frequency register SG0FL
Symbol
R/W
Manipulable Bit Range After Reset
1-bit
8-bit
16-bit
SG0FL
R/W
0000H
0000H
F0282H
Frequency register SG0FH
SG0FH
R/W
F0284H
Amplitude register
SG0PWM
R/W
0000H
F0286H
Duration factor register
SG0SDF
R/W
00H
F0287H
Control register
SG0CTL
R/W
0000H
F0288H
Interrupt threshold register
SG0ITH
R/W
0000H
F02F0H
Flash memory CRC control register
CRC0CTL
R/W
00H
F02F2H
Flash memory CRC operation result register
PGCRCL
R/W
0000H
CRCD
R/W
0000H
00H
F02FAH
CRC data register
F0300H
LCD display data memory0
SEG0
R/W
F0301H
LCD display data memory1
SEG1
R/W
00H
F0302H
LCD display data memory2
SEG2
R/W
00H
F0303H
LCD display data memory3
SEG3
R/W
00H
F0304H
LCD display data memory4
SEG4
R/W
00H
F0305H
LCD display data memory5
SEG5
R/W
00H
F0306H
LCD display data memory6
SEG6
R/W
00H
SEG7
R/W
00H
00H
F0307H
LCD display data memory7
F0308H
LCD display data memory8
SEG8
R/W
F0309H
LCD display data memory9
SEG9
R/W
00H
F030AH
LCD display data memory10
SEG10
R/W
00H
F030BH
LCD display data memory11
SEG11
R/W
00H
F030CH
LCD display data memory12
SEG12
R/W
00H
F030DH
LCD display data memory13
SEG13
R/W
00H
F030EH
LCD display data memory14
SEG14
R/W
00H
SEG15
R/W
00H
00H
F030FH
LCD display data memory15
F0310H
LCD display data memory16
SEG16
R/W
F0311H
LCD display data memory17
SEG17
R/W
00H
F0312H
LCD display data memory18
SEG18
R/W
00H
F0313H
LCD display data memory19
SEG19
R/W
00H
F0314H
LCD display data memory20
SEG20
R/W
00H
F0315H
LCD display data memory21
SEG21
R/W
00H
F0316H
LCD display data memory22
SEG22
R/W
00H
SEG23
R/W
00H
00H
F0317H
LCD display data memory23
F0318H
LCD display data memory24
SEG24
R/W
F0319H
LCD display data memory25
SEG25
R/W
00H
F031AH
LCD display data memory26
SEG26
R/W
00H
F031BH
LCD display data memory27
SEG27
R/W
00H
F031CH
LCD display data memory28
SEG28
R/W
00H
F031DH
LCD display data memory29
SEG29
R/W
00H
F031EH
LCD display data memory30
SEG30
R/W
00H
SEG31
R/W
00H
F031FH
LCD display data memory31
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (9/21)
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit Range After Reset
1-bit
8-bit
16-bit
SEG32
R/W
00H
F0321H LCD display data memory33
SEG33
R/W
00H
F0322H LCD display data memory34
SEG34
R/W
00H
F0323H LCD display data memory35
SEG35
R/W
00H
F0324H LCD display data memory36
SEG36
R/W
00H
F0325H LCD display data memory37
SEG37
R/W
00H
F0326H LCD display data memory38
SEG38
R/W
00H
F0327H LCD display data memory39
SEG39
R/W
00H
SEG40
R/W
00H
F0329H LCD display data memory41
SEG41
R/W
00H
F032AH LCD display data memory42
SEG42
R/W
00H
F032BH LCD display data memory43
SEG43
R/W
00H
F032CH LCD display data memory44
SEG44
R/W
00H
F032DH LCD display data memory45
SEG45
R/W
00H
F032EH LCD display data memory46
SEG46
R/W
00H
F032FH LCD display data memory47
SEG47
R/W
00H
SEG48
R/W
00H
F0331H LCD display data memory49
SEG49
R/W
00H
F0332H LCD display data memory50
SEG50
R/W
00H
F0333H LCD display data memory51
SEG51
R/W
00H
F0334H LCD display data memory52
SEG52
R/W
00H
SEG53
R/W
00H
F0340H CAN1 global module control register
C1GMCTRL
R/W
0000H
F0342H CAN1 global module clock select register
C1GMCS
R/W
0FH
C1GMABT
R/W
0000H
F0348H CAN1 global block transmission delay setting register
C1GMABTD
R/W
00H
F0380H CAN1 module mask 1 register L
C1MASK1L
R/W
Undefined
F0382H CAN1 module mask 1 register H
C1MASK1H
R/W
Undefined
F0384H CAN1 module mask 2 register L
C1MASK2L
R/W
Undefined
F0386H CAN1 module mask 2 register H
C1MASK2H
R/W
Undefined
F0388H CAN1 module mask 3 register L)
C1MASK3L
R/W
Undefined
F038AH CAN1 module mask 3 register H
C1MASK3H
R/W
Undefined
C1MASK4L
R/W
Undefined
F038EH CAN1 module mask 4 register H
C1MASK4H
R/W
Undefined
F0390H CAN1 module control register
C1CTRL
R/W
0000H
F0392H CAN1 module last error information register
C1LEC
R/W
00H
F0393H CAN1 module information register
C1INFO
R
00H
F0394H CAN1 module error counter register
C1ERC
R
0000H
F0396H CAN1 module interrupt enable register
C1IE
R/W
0000H
F0398H CAN1 module interrupt status register
C1INTS
R/W
0000H
F0320H LCD display data memory32
F0328H LCD display data memory40
F0330H LCD display data memory48
F0335H LCD display data memory53 Note
F0346H CAN1 global block transmission control register
F038CH CAN1 module mask 4 register L
Note 128-pin products only.
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (10/21)
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit Range After Reset
1-bit
8-bit
16-bit
C1BRP
R/W
FFH
F039CH CAN1 module bit rate register
C1BTR
R/W
370FH
F039EH CAN1 module last in-pointer register
C1LIPT
R
Undefined
F03A0H CAN1 module receive history list register
C1RGPT
R/W
xx02H
F03A2H CAN1 module last out-pointer register
C1LOPT
R
Undefined
F03A4H CAN1 module transmit history list register
C1TGPT
R/W
xx02H
F03A6H CAN1 module time stamp register
C1TS
R/W
0000H
F0400H
C1MDB0100
R/W
Undefined
Undefined
F039AH CAN1 module bit rate prescaler register
CAN1 message data byte 01 register 00
F0400H
CAN1 message data byte 0 register 00
C1MDB000
R/W
F0401H
CAN1 message data byte 1 register 00
C1MDB100
R/W
Undefined
F0402H
CAN1 message data byte 23 register 00
C1MDB2300
R/W
Undefined
F0402H
CAN1 message data byte 2 register 00
C1MDB200
R/W
Undefined
F0403H
CAN1 message data byte 3 register 00
C1MDB300
R/W
Undefined
F0404H
CAN1 message data byte 45 register 00
C1MDB4500
R/W
Undefined
F0404H
CAN1 message data byte 4 register 00
C1MDB400
R/W
Undefined
F0405H
CAN1 message data byte 5 register 00
C1MDB500
R/W
Undefined
Undefined
F0406H
CAN1 message data byte 67 register 00
C1MDB6700
R/W
F0406H
CAN1 message data byte 6 register 00
C1MDB600
R/W
Undefined
F0407H
CAN1 message data byte 7 register 00
C1MDB700
R/W
Undefined
F0408H
CAN1 message data length register 00
C1MDLC00
R/W
0xH
F0409H
CAN1 message Configuration register 00
C1MCONF00
R/W
Undefined
F040AH CAN1 message ID register 00L
C1MIDL00
R/W
Undefined
F040CH CAN1 message ID register 00H
C1MIDH00
R/W
Undefined
F040EH CAN1 message control register 00
C1MCTRL00
R/W
Undefined
Undefined
F0410H
CAN1 message data byte 01 register 01
C1MDB0101
R/W
F0410H
CAN1 message data byte 0 register 01
C1MDB001
R/W
Undefined
F0411H
CAN1 message data byte 1 register 01
C1MDB101
R/W
Undefined
Undefined
F0412H
CAN1 message data byte 23 register 01
C1MDB2301
R/W
F0412H
CAN1 message data byte 2 register 01
C1MDB201
R/W
Undefined
F0413H
CAN1 message data byte 3 register 01
C1MDB301
R/W
Undefined
F0414H
CAN1 message data byte 45 register 01
C1MDB4501
R/W
Undefined
F0414H
CAN1 message data byte 4 register 01
C1MDB401
R/W
Undefined
F0415H
CAN1 message data byte 5 register 01
C1MDB501
R/W
Undefined
F0416H
CAN1 message data byte 67 register 01
C1MDB6701
R/W
Undefined
F0416H
CAN1 message data byte 6 register 01
C1MDB601
R/W
Undefined
Undefined
F0417H
CAN1 message data byte 7 register 01
C1MDB701
R/W
F0418H
CAN1 message data length register 01
C1MDLC01
R/W
0xH
C1MCONF01
R/W
Undefined
F041AH CAN1 message ID register 01L
C1MIDL01
R/W
Undefined
F041CH CAN1 message ID register 01H
C1MIDH01
R/W
Undefined
F041EH CAN1 message control register 01
C1MCTRL01
R/W
Undefined
F0419H
CAN1 message Configuration register 01
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (11/21)
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit Range
After Reset
1-bit
8-bit
16-bit
Undefined
F0420H
CAN1 message data byte 01 register 02
C1MDB0102
R/W
F0420H
CAN1 message data byte 0 register 02
C1MDB002
R/W
Undefined
F0421H
CAN1 message data byte 1 register 02
C1MDB102
R/W
Undefined
F0422H
CAN1 message data byte 23 register 02
C1MDB2302
R/W
Undefined
F0422H
CAN1 message data byte 2 register 02
C1MDB202
R/W
Undefined
F0423H
CAN1 message data byte 3 register 02
C1MDB302
R/W
Undefined
F0424H
CAN1 message data byte 45 register 02
C1MDB4502
R/W
Undefined
F0424H
CAN1 message data byte 4 register 02
C1MDB402
R/W
Undefined
Undefined
F0425H
CAN1 message data byte 5 register 02
C1MDB502
R/W
F0426H
CAN1 message data byte 67 register 02
C1MDB6702
R/W
Undefined
F0426H
CAN1 message data byte 6 register 02
C1MDB602
R/W
Undefined
F0427H
CAN1 message data byte 7 register 02
C1MDB702
R/W
Undefined
F0428H
CAN1 message data length register 02
C1MDLC02
R/W
0xH
F0429H
CAN1 message Configuration register 02
C1MCONF02
R/W
Undefined
F042AH
CAN1 message ID register 02L
C1MIDL02
R/W
Undefined
F042CH
CAN1 message ID register 02H
C1MIDH02
R/W
Undefined
Undefined
F042EH
CAN1 message control register 02
C1MCTRL02
R/W
F0430H
CAN1 message data byte 01 register 03
C1MDB0103
R/W
Undefined
F0430H
CAN1 message data byte 0 register 03
C1MDB003
R/W
Undefined
F0431H
CAN1 message data byte 1 register 03
C1MDB103
R/W
Undefined
F0432H
CAN1 message data byte 23 register 03
C1MDB2303
R/W
Undefined
F0432H
CAN1 message data byte 2 register 03
C1MDB203
R/W
Undefined
F0433H
CAN1 message data byte 3 register 03
C1MDB303
R/W
Undefined
F0434H
CAN1 message data byte 45 register 03
C1MDB4503
R/W
Undefined
Undefined
F0434H
CAN1 message data byte 4 register 03
C1MDB403
R/W
F0435H
CAN1 message data byte 5 register 03
C1MDB503
R/W
Undefined
F0436H
CAN1 message data byte 67 register 03
C1MDB6703
R/W
Undefined
F0436H
CAN1 message data byte 6 register 03
C1MDB603
R/W
Undefined
F0437H
CAN1 message data byte 7 register 03
C1MDB703
R/W
Undefined
F0438H
CAN1 message data length register 03
C1MDLC03
R/W
0xH
F0439H
CAN1 message Configuration register 03
C1MCONF03
R/W
Undefined
F043AH
CAN1 message ID register 03L
C1MIDL03
R/W
Undefined
Undefined
F043CH
CAN1 message ID register 03H
C1MIDH03
R/W
F043EH
CAN1 message control register 03
C1MCTRL03
R/W
Undefined
F0440H
CAN1 message data byte 01 register 04
C1MDB0104
R/W
Undefined
F0440H
CAN1 message data byte 0 register 04
C1MDB004
R/W
Undefined
F0441H
CAN1 message data byte 1 register 04
C1MDB104
R/W
Undefined
F0442H
CAN1 message data byte 23 register 04
C1MDB2304
R/W
Undefined
F0442H
CAN1 message data byte 2 register 04
C1MDB204
R/W
Undefined
F0443H
CAN1 message data byte 3 register 04
C1MDB304
R/W
Undefined
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (12/21)
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit Range
After Reset
1-bit
8-bit
16-bit
Undefined
F0444H
CAN1 message data byte 45 register 04
C1MDB4504
R/W
F0444H
CAN1 message data byte 4 register 04
C1MDB404
R/W
Undefined
F0445H
CAN1 message data byte 5 register 04
C1MDB504
R/W
Undefined
F0446H
CAN1 message data byte 67 register 04
C1MDB6704
R/W
Undefined
F0446H
CAN1 message data byte 6 register 04
C1MDB604
R/W
Undefined
F0447H
CAN1 message data byte 7 register 04
C1MDB704
R/W
Undefined
F0448H
CAN1 message data length register 04
C1MDLC04
R/W
0xH
F0449H
CAN1 message Configuration register 04
C1MCONF04
R/W
Undefined
F044AH CAN1 message ID register 04L
C1MIDL04
R/W
Undefined
F044CH CAN1 message ID register 04H
C1MIDH04
R/W
Undefined
F044EH CAN1 message control register 04
C1MCTRL04
R/W
Undefined
F0450H
CAN1 message data byte 01 register 05
C1MDB0105
R/W
Undefined
F0450H
CAN1 message data byte 0 register 05
C1MDB005
R/W
Undefined
F0451H
CAN1 message data byte 1 register 05
C1MDB105
R/W
Undefined
F0452H
CAN1 message data byte 23 register 05
C1MDB2305
R/W
Undefined
F0452H
CAN1 message data byte 2 register 05
C1MDB205
R/W
Undefined
Undefined
F0453H
CAN1 message data byte 3 register 05
C1MDB305
R/W
F0454H
CAN1 message data byte 45 register 05
C1MDB4505
R/W
Undefined
F0454H
CAN1 message data byte 4 register 05
C1MDB405
R/W
Undefined
F0455H
CAN1 message data byte 5 register 05
C1MDB505
R/W
Undefined
F0456H
CAN1 message data byte 67 register 05
C1MDB6705
R/W
Undefined
F0456H
CAN1 message data byte 6 register 05
C1MDB605
R/W
Undefined
F0457H
CAN1 message data byte 7 register 05
C1MDB705
R/W
Undefined
F0458H
CAN1 message data length register 05
C1MDLC05
R/W
0xH
C1MCONF05
R/W
Undefined
F045AH CAN1 message ID register 05L
C1MIDL05
R/W
Undefined
F045CH CAN1 message ID register 05H
C1MIDH05
R/W
Undefined
F045EH CAN1 message control register 05
C1MCTRL05
R/W
Undefined
F0460H
CAN1 message data byte 01 register 06
C1MDB0106
R/W
Undefined
F0460H
CAN1 message data byte 0 register 06
C1MDB006
R/W
Undefined
F0461H
CAN1 message data byte 1 register 06
C1MDB106
R/W
Undefined
F0462H
CAN1 message data byte 23 register 06
C1MDB2306
R/W
Undefined
Undefined
F0459H
CAN1 message Configuration register 05
F0462H
CAN1 message data byte 2 register 06
C1MDB206
R/W
F0463H
CAN1 message data byte 3 register 06
C1MDB306
R/W
Undefined
F0464H
CAN1 message data byte 45 register 06
C1MDB4506
R/W
Undefined
F0464H
CAN1 message data byte 4 register 06
C1MDB406
R/W
Undefined
F0465H
CAN1 message data byte 5 register 06
C1MDB506
R/W
Undefined
F0466H
CAN1 message data byte 67 register 06
C1MDB6706
R/W
Undefined
F0466H
CAN1 message data byte 6 register 06
C1MDB606
R/W
Undefined
F0467H
CAN1 message data byte 7 register 06
C1MDB706
R/W
Undefined
C1MDLC06
R/W
0xH
C1MCONF06
R/W
Undefined
F0468H
F0469H
CAN1 message data length register 06
CAN1 message Configuration register 06
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (13/21)
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit Range After Reset
1-bit
8-bit
16-bit
Undefined
F046AH CAN1 message ID register 06L
C1MIDL06
R/W
F046CH CAN1 message ID register 06H
C1MIDH06
R/W
Undefined
F046EH CAN1 message control register 06
C1MCTRL06
R/W
Undefined
F0470H CAN1 message data byte 01 register 07
C1MDB0107
R/W
Undefined
F0470H CAN1 message data byte 0 register 07
C1MDB007
R/W
Undefined
F0471H CAN1 message data byte 1 register 07
C1MDB107
R/W
Undefined
F0472H CAN1 message data byte 23 register 07
C1MDB2307
R/W
Undefined
F0472H CAN1 message data byte 2 register 07
C1MDB207
R/W
Undefined
F0473H CAN1 message data byte 3 register 07
C1MDB307
R/W
Undefined
F0474H CAN1 message data byte 45 register 07
C1MDB4507
R/W
Undefined
F0474H CAN1 message data byte 4 register 07
C1MDB407
R/W
Undefined
F0475H CAN1 message data byte 5 register 07
C1MDB507
R/W
Undefined
F0476H CAN1 message data byte 67 register 07
C1MDB6707
R/W
Undefined
F0476H CAN1 message data byte 6 register 07
C1MDB607
R/W
Undefined
F0477H CAN1 message data byte 7 register 07
C1MDB707
R/W
Undefined
F0478H CAN1 message data length register 07
C1MDLC07
R/W
0xH
C1MCONF07
R/W
Undefined
F047AH CAN1 message ID register 07L
C1MIDL07
R/W
Undefined
F047CH CAN1 message ID register 07H
C1MIDH07
R/W
Undefined
F047EH CAN1 message control register 07
C1MCTRL07
R/W
Undefined
F0480H CAN1 message data byte 01 register 08
C1MDB0108
R/W
Undefined
F0480H CAN1 message data byte 0 register 08
C1MDB008
R/W
Undefined
F0481H CAN1 message data byte 1 register 08
C1MDB108
R/W
Undefined
F0482H CAN1 message data byte 23 register 08
C1MDB2308
R/W
Undefined
F0482H CAN1 message data byte 2 register 08
C1MDB208
R/W
Undefined
F0483H CAN1 message data byte 3 register 08
C1MDB308
R/W
Undefined
F0484H CAN1 message data byte 45 register 08
C1MDB4508
R/W
Undefined
F0484H CAN1 message data byte 4 register 08
C1MDB408
R/W
Undefined
F0485H CAN1 message data byte 5 register 08
C1MDB508
R/W
Undefined
F0486H CAN1 message data byte 67 register 08
C1MDB6708
R/W
Undefined
F0486H CAN1 message data byte 6 register 08
C1MDB608
R/W
Undefined
F0487H CAN1 message data byte 7 register 08
C1MDB708
R/W
Undefined
F0488H CAN1 message data length register 08
C1MDLC08
R/W
0xH
F0489H CAN1 message Configuration register 08
C1MCONF08
R/W
Undefined
F048AH CAN1 message ID register 08L
C1MIDL08
R/W
Undefined
F048CH CAN1 message ID register 08H
C1MIDH08
R/W
Undefined
F048EH CAN1 message control register 08
C1MCTRL08
R/W
Undefined
F0490H CAN1 message data byte 01 register 09
C1MDB0109
R/W
Undefined
F0490H CAN1 message data byte 0 register 09
C1MDB009
R/W
Undefined
F0491H CAN1 message data byte 1 register 09
C1MDB109
R/W
Undefined
F0479H CAN1 message Configuration register 07
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (14/21)
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit Range
After Reset
1-bit
8-bit
16-bit
Undefined
F0492H
CAN1 message data byte 23 register 09
C1MDB2309
R/W
F0492H
CAN1 message data byte 2 register 09
C1MDB209
R/W
Undefined
F0493H
CAN1 message data byte 3 register 09
C1MDB309
R/W
Undefined
F0494H
CAN1 message data byte 45 register 09
C1MDB4509
R/W
Undefined
F0494H
CAN1 message data byte 4 register 09
C1MDB409
R/W
Undefined
F0495H
CAN1 message data byte 5 register 09
C1MDB509
R/W
Undefined
F0496H
CAN1 message data byte 67 register 09
C1MDB6709
R/W
Undefined
F0496H
CAN1 message data byte 6 register 09
C1MDB609
R/W
Undefined
Undefined
F0497H
CAN1 message data byte 7 register 09
C1MDB709
R/W
F0498H
CAN1 message data length register 09
C1MDLC09
R/W
0xH
F0499H
CAN1 message Configuration register 09
C1MCONF09
R/W
Undefined
F049AH CAN1 message ID register 09L
C1MIDL09
R/W
Undefined
F049CH CAN1 message ID register 09H
C1MIDH09
R/W
Undefined
F049EH CAN1 message control register 09
C1MCTRL09
R/W
Undefined
F04A0H CAN1 message data byte 01 register 10
C1MDB0110
R/W
Undefined
F04A0H CAN1 message data byte 0 register 10
C1MDB010
R/W
Undefined
F04A1H CAN1 message data byte 1 register 10
C1MDB110
R/W
Undefined
F04A2H CAN1 message data byte 23 register 10
C1MDB2310
R/W
Undefined
F04A2H CAN1 message data byte 2 register 10
C1MDB210
R/W
Undefined
F04A3H CAN1 message data byte 3 register 10
C1MDB310
R/W
Undefined
F04A4H CAN1 message data byte 45 register 10
C1MDB4510
R/W
Undefined
F04A4H CAN1 message data byte 4 register 10
C1MDB410
R/W
Undefined
F04A5H CAN1 message data byte 5 register 10
C1MDB510
R/W
Undefined
F04A6H CAN1 message data byte 67 register 10
C1MDB6710
R/W
Undefined
F04A6H CAN1 message data byte 6 register 10
C1MDB610
R/W
Undefined
F04A7H CAN1 message data byte 7 register 10
C1MDB710
R/W
Undefined
F04A8H CAN1 message data length register 10
C1MDLC10
R/W
0xH
F04A9H CAN1 message Configuration register 10
C1MCONF10
R/W
Undefined
F04AAH CAN1 message ID register 10L
C1MIDL10
R/W
Undefined
F04ACH CAN1 message ID register 10H
C1MIDH10
R/W
Undefined
F04AEH CAN1 message control register 10
C1MCTRL10
R/W
Undefined
F04B0H CAN1 message data byte 01 register 11
C1MDB0111
R/W
Undefined
F04B0H CAN1 message data byte 0 register 11
C1MDB011
R/W
Undefined
F04B1H CAN1 message data byte 1 register 11
C1MDB111
R/W
Undefined
F04B2H CAN1 message data byte 23 register 11
C1MDB2311
R/W
Undefined
F04B2H CAN1 message data byte 2 register 11
C1MDB211
R/W
Undefined
F04B3H CAN1 message data byte 3 register 11
C1MDB311
R/W
Undefined
F04B4H CAN1 message data byte 45 register 11
C1MDB4511
R/W
Undefined
F04B4H CAN1 message data byte 4 register 11
C1MDB411
R/W
Undefined
F04B5H CAN1 message data byte 5 register 11
C1MDB511
R/W
Undefined
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (15/21)
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit Range
After Reset
1-bit
8-bit
16-bit
Undefined
F04B6H CAN1 message data byte 67 register 11
C1MDB6711
R/W
F04B6H
CAN1 message data byte 6 register 11
C1MDB611
R/W
Undefined
F04B7H
CAN1 message data byte 7 register 11
C1MDB711
R/W
Undefined
F04B8H
CAN1 message data length register 11
C1MDLC11
R/W
0xH
F04B9H CAN1 message Configuration register 11
C1MCONF11
R/W
Undefined
F04BAH CAN1 message ID register 11L
C1MIDL11
R/W
Undefined
F04BCH CAN1 message ID register 11H
C1MIDH11
R/W
Undefined
F04BEH CAN1 message control register 11
C1MCTRL11
R/W
Undefined
F04C0H CAN1 message data byte 01 register 12
C1MDB0112
R/W
Undefined
F04C0H CAN1 message data byte 0 register 12
C1MDB012
R/W
Undefined
F04C1H CAN1 message data byte 1 register 12
C1MDB112
R/W
Undefined
F04C2H CAN1 message data byte 23 register 12
C1MDB2312
R/W
Undefined
F04C2H CAN1 message data byte 2 register 12
C1MDB212
R/W
Undefined
F04C3H CAN1 message data byte 3 register 12
C1MDB312
R/W
Undefined
F04C4H CAN1 message data byte 45 register 12
C1MDB4512
R/W
Undefined
F04C4H CAN1 message data byte 4 register 12
C1MDB412
R/W
Undefined
F04C5H CAN1 message data byte 5 register 12
C1MDB512
R/W
Undefined
F04C6H CAN1 message data byte 67 register 12
C1MDB6712
R/W
Undefined
F04C6H CAN1 message data byte 6 register 12
C1MDB612
R/W
Undefined
F04C7H CAN1 message data byte 7 register 12
C1MDB712
R/W
Undefined
F04C8H CAN1 message data length register 12
C1MDLC12
R/W
0xH
F04C9H CAN1 message Configuration register 12
C1MCONF12
R/W
Undefined
F04CAH CAN1 message ID register 12L
C1MIDL12
R/W
Undefined
F04CCH CAN1 message ID register 12H
C1MIDH12
R/W
Undefined
C1MCTRL12
R/W
Undefined
F04D0H CAN1 message data byte 01 register 13
C1MDB0113
R/W
Undefined
F04D0H CAN1 message data byte 0 register 13
C1MDB013
R/W
Undefined
F04D1H CAN1 message data byte 1 register 13
C1MDB113
R/W
Undefined
F04D2H CAN1 message data byte 23 register 13
C1MDB2313
R/W
Undefined
F04D2H CAN1 message data byte 2 register 13
C1MDB213
R/W
Undefined
F04D3H CAN1 message data byte 3 register 13
C1MDB313
R/W
Undefined
F04D4H CAN1 message data byte 45 register 13
C1MDB4513
R/W
Undefined
F04D4H CAN1 message data byte 4 register 13
C1MDB413
R/W
Undefined
F04D5H CAN1 message data byte 5 register 13
C1MDB513
R/W
Undefined
F04D6H CAN1 message data byte 67 register 13
C1MDB6713
R/W
Undefined
F04D6H CAN1 message data byte 6 register 13
C1MDB613
R/W
Undefined
F04D7H CAN1 message data byte 7 register 13
C1MDB713
R/W
Undefined
F04D8H CAN1 message data length register 13
C1MDLC13
R/W
0xH
F04D9H CAN1 message Configuration register 13
C1MCONF13
R/W
Undefined
F04DAH CAN1 message ID register 13L
C1MIDL13
R/W
Undefined
F04DCH CAN1 message ID register 13H
C1MIDH13
R/W
Undefined
F04DEH CAN1 message control register 13
C1MCTRL13
R/W
Undefined
F04CEH CAN1 message control register 12
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (16/21)
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit Range
After Reset
1-bit
8-bit
16-bit
F04E0H CAN1 message data byte 01 register 14
C1MDB0114
R/W
Undefined
F04E0H CAN1 message data byte 0 register 14
C1MDB014
R/W
Undefined
F04E1H CAN1 message data byte 1 register 14
C1MDB114
R/W
Undefined
F04E2H CAN1 message data byte 23 register 14
C1MDB2314
R/W
Undefined
F04E2H CAN1 message data byte 2 register 14
C1MDB214
R/W
Undefined
F04E3H CAN1 message data byte 3 register 14
C1MDB314
R/W
Undefined
F04E4H CAN1 message data byte 45 register 14
C1MDB4514
R/W
Undefined
F04E4H CAN1 message data byte 4 register 14
C1MDB414
R/W
Undefined
F04E5H CAN1 message data byte 5 register 14
C1MDB514
R/W
Undefined
F04E6H CAN1 message data byte 67 register 14
C1MDB6714
R/W
Undefined
F04E6H CAN1 message data byte 6 register 14
C1MDB614
R/W
Undefined
F04E7H CAN1 message data byte 7 register 14
C1MDB714
R/W
Undefined
F04E8H CAN1 message data length register 14
C1MDLC14
R/W
0xH
F04E9H CAN1 message Configuration register 14
C1MCONF14
R/W
Undefined
F04EAH CAN1 message ID register 14L
C1MIDL14
R/W
Undefined
F04ECH CAN1 message ID register 14H
C1MIDH14
R/W
Undefined
F04EEH CAN1 message control register 14
C1MCTRL14
R/W
Undefined
F04F0H CAN1 message data byte 01 register 15
C1MDB0115
R/W
Undefined
F04F0H CAN1 message data byte 0 register 15
C1MDB015
R/W
Undefined
F04F1H CAN1 message data byte 1 register 15
C1MDB115
R/W
Undefined
F04F2H CAN1 message data byte 23 register 15
C1MDB2315
R/W
Undefined
F04F2H CAN1 message data byte 2 register 15
C1MDB215
R/W
Undefined
F04F3H CAN1 message data byte 3 register 15
C1MDB315
R/W
Undefined
F04F4H CAN1 message data byte 45 register 15
C1MDB4515
R/W
Undefined
F04F4H CAN1 message data byte 4 register 15
C1MDB415
R/W
Undefined
F04F5H CAN1 message data byte 5 register 15
C1MDB515
R/W
Undefined
F04F6H CAN1 message data byte 67 register 15
C1MDB6715
R/W
Undefined
F04F6H CAN1 message data byte 6 register 15
C1MDB615
R/W
Undefined
F04F7H CAN1 message data byte 7 register 15
C1MDB715
R/W
Undefined
F04F8H CAN1 message data length register 15
C1MDLC15
R/W
0xH
F04F9H CAN1 message Configuration register 15
C1MCONF15
R/W
Undefined
F04FAH CAN1 message ID register 15L
C1MIDL15
R/W
Undefined
F04FCH CAN1 message ID register 15H
C1MIDH15
R/W
Undefined
F04FEH CAN1 message control register 15
C1MCTRL15
R/W
Undefined
F05C0H CAN0 global module control register
C0GMCTRL
R/W
0000H
F05C6H CAN0 global block transmission control register
C0GMABT
R/W
0000H
F05C8H CAN0 global block transmission delay setting register
C0GMABTD
R/W
00H
F05CEH CAN0 global module clock select register
C0GMCS
R/W
0FH
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (17/21)
Address
Special Function Register (SFR) Name
F05D0H CAN0 module mask 1 register L
Symbol
R/W
R/W
C0MASK1L
Manipulable Bit Range
1-bit
8-bit
16-bit
After Reset
Undefined
F05D2H CAN0 module mask 1 register H
C0MASK1H
R/W
Undefined
F05D4H CAN0 module mask 2 register L
C0MASK2L
R/W
Undefined
F05D6H CAN0 module mask 2 register H
C0MASK2H
R/W
Undefined
F05D8H CAN0 module mask 3 register L
C0MASK3L
R/W
Undefined
F05DAH CAN0 module mask 3 register H
C0MASK3H
R/W
Undefined
F05DCH CAN0 module mask 4 register L
C0MASK4L
R/W
Undefined
F05DEH CAN0 module mask 4 register H
C0MASK4H
R/W
Undefined
F05E0H CAN0 module control register
C0CTRL
R/W
0000H
F05E2H CAN0 module last error information register
C0LEC
R/W
00H
F05E3H CAN0 module information register
C0INFO
R
00H
F05E4H CAN0 module error counter register
C0ERC
R
0000H
F05E6H CAN0 module interrupt enable register
C0IE
R/W
0000H
F05E8H CAN0 module interrupt status register
C0INTS
R/W
0000H
F05EAH CAN0 module bit rate prescaler register
C0BRP
R/W
FFH
F05ECH CAN0 module bit rate register
C0BTR
R/W
370FH
F05EEH CAN0 module last in-pointer register
C0LIPT
R
Undefined
F05F0H CAN0 module receive history list register
C0RGPT
R/W
xx02H
F05F2H CAN0 module last out-pointer register
C0LOPT
R
Undefined
F05F4H CAN0 module transmit history list register
C0TGPT
R/W
xx2H
F05F6H CAN0 module time stamp register
C0TS
F0600H
C0MDB000
CAN0 message data byte 01 register 00
F0601H
F0602H
0000H
Undefined
C0MDB200
C0MDB2300
R/W
Undefined
C0MDB4500
R/W
Undefined
C0MDB6700
R/W
Undefined
C0MDB300
CAN0 message data Byte 45 register 00
F0605H
F0606H
R/W
C0MDB100
CAN0 message data byte 23 register 00
F0603H
F0604H
R/W
C0MDB0100
C0MDB400
C0MDB500
CAN0 message data byte 67 register 00
C0MDB600
F0608H
CAN0 message data length register 00
C0MDLC00
R/W
0xH
F0609H
CAN0 message configuration register 00
C0MCONF00
R/W
Undefined
F060AH CAN0 message ID register 00L
C0MIDL00
R/W
Undefined
F060CH CAN0 message ID register 00H
C0MIDH00
R/W
Undefined
F060EH CAN0 message control register 00
C0MCTRL00
R/W
Undefined
C0MDB001
C0MDB0101
R/W
Undefined
C0MDB2301
R/W
Undefined
C0MDB4501
R/W
Undefined
C0MDB6701
R/W
Undefined
F0607H
F0610H
C0MDB700
CAN0 message data byte 01 register 01
F0611H
F0612H
C0MDB101
CAN0 message data byte 23 register 01
F0613H
F0614H
C0MDB301
CAN0 message data byte 45 register 01
F0615H
F0616H
C0MDB201
C0MDB401
C0MDB501
CAN0 message data byte 67 register 01
F0617H
C0MDB601
C0MDB701
F0618H
CAN0 message data length register 01
C0MDLC01
R/W
0xH
F0619H
CAN0 message configuration register 01
C0MCONF01
R/W
Undefined
F061AH CAN0 message ID register 01L
C0MIDL01
R/W
Undefined
F061CH CAN0 message ID register 01H
C0MIDH01
R/W
Undefined
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (18/21)
Address Special Function Register (SFR) Name
F061EH
F0620H
CAN0 message control register 01
C0MCTRL01
CAN0 message data byte 01 register 02
C0MDB002
F0621H
F0622H
CAN0 message data byte 23 register 02
Manipulable Bit Range
1-bit
8-bit
16-bit
After Reset
R/W
Undefined
C0MDB0102
R/W
Undefined
C0MDB202
C0MDB2302
R/W
Undefined
C0MDB4502
R/W
Undefined
C0MDB6702
R/W
Undefined
C0MDB302
CAN0 message data byte 45 register 02
F0625H
F0626H
R/W
C0MDB102
F0623H
F0624H
Symbol
C0MDB402
C0MDB502
CAN0 message data byte 67 register 02
C0MDB602
CAN0 message data length register 02
C0MDLC02
R/W
0xH
F0629H
CAN0 message configuration register 02
C0MCONF02
R/W
Undefined
F062AH
CAN0 message ID register 02L
C0MIDL02
R/W
Undefined
F062CH
CAN0 message ID register 02H
C0MIDH02
R/W
Undefined
F062EH
CAN0 message control register 02
C0MCTRL02
F0630H
CAN0 message data byte 01 register 03
C0MDB003
F0627H
F0628H
C0MDB702
F0631H
F0632H
Undefined
Undefined
C0MDB203
C0MDB2303
R/W
Undefined
C0MDB4503
R/W
Undefined
C0MDB6703
R/W
Undefined
C0MDB303
CAN0 message data byte 45 register 03
F0635H
F0636H
R/W
C0MDB103
CAN0 message data byte 23 register 03
F0633H
F0634H
R/W
C0MDB0103
C0MDB403
C0MDB503
CAN0 message data byte 67 register 03
C0MDB603
CAN0 message data length register 03
C0MDLC03
R/W
0xH
F0639H
CAN0 message Configuration register 03
C0MCONF03
R/W
Undefined
F063AH
CAN0 message ID register 03L
C0MIDL03
R/W
Undefined
F063CH
CAN0 message ID register 03H
C0MIDH03
R/W
Undefined
F063EH
CAN0 message control register 03
C0MCTRL03
F0640H
CAN0 message data byte 01 register 04
C0MDB004
F0637H
F0638H
C0MDB703
F0641H
F0642H
Undefined
Undefined
C0MDB204
C0MDB2304
R/W
Undefined
C0MDB4504
R/W
Undefined
C0MDB6704
R/W
Undefined
C0MDB304
CAN0 message data byte 45 register 04
F0645H
F0646H
R/W
C0MDB104
CAN0 message data byte 23 register 04
F0643H
F0644H
R/W
C0MDB0104
C0MDB404
C0MDB504
CAN0 message data byte 67 register 04
F0647H
C0MDB604
C0MDB704
F0648H
CAN0 message data length register 04
C0MDLC04
R/W
0xH
F0649H
CAN0 message Configuration register 04
C0MCONF04
R/W
Undefined
F064AH
CAN0 message ID register 04L
C0MIDL04
R/W
Undefined
F064CH
CAN0 message ID register 04H
C0MIDH04
R/W
Undefined
F064EH
CAN0 message control register 04
C0MCTRL04
R/W
Undefined
C0MDB005
C0MDB0105
R/W
Undefined
C0MDB2305
R/W
Undefined
F0650H
CAN0 message data byte 01 register 05
F0651H
F0652H
C0MDB105
CAN0 message data byte 23 register 05
F0653H
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (19/21)
Address
F0654H
Special Function Register (SFR) Name
CAN0 message data byte 45 register 05
F0655H
F0656H
Symbol
C0MDB405
R/W
Manipulable Bit Range After Reset
1-bit
8-bit
16-bit
C0MDB4505
R/W
Undefined
C0MDB6705
R/W
Undefined
C0MDB505
CAN0 message data byte 67 register 05
F0657H
C0MDB605
C0MDB705
F0658H
CAN0 message data length register 05
C0MDLC05
R/W
0xH
F0659H
CAN0 message Configuration register 05
C0MCONF05
R/W
Undefined
F065AH
CAN0 message ID register 05L
C0MIDL05
R/W
Undefined
F065CH CAN0 message ID register 05H
C0MIDH05
R/W
Undefined
F065EH
CAN0 message control register 05
C0MCTRL05
R/W
Undefined
F0660H
CAN0 message data byte 01 register 06
C0MDB006
C0MDB0106
R/W
Undefined
C0MDB2306
R/W
Undefined
C0MDB4506
R/W
Undefined
C0MDB6706
R/W
Undefined
F0661H
F0662H
C0MDB106
CAN0 message data byte 23 register 06
F0663H
F0664H
C0MDB306
CAN0 message data byte 45 register 06
F0665H
F0666H
C0MDB206
C0MDB406
C0MDB506
CAN0 message data byte 67 register 06
F0667H
C0MDB606
C0MDB706
F0668H
CAN0 message data length register 06
C0MDLC06
R/W
0xH
F0669H
CAN0 message Configuration register 06
C0MCONF06
R/W
Undefined
F066AH
CAN0 message ID register 06L
C0MIDL06
R/W
Undefined
F066CH CAN0 message ID register 06H
C0MIDH06
R/W
Undefined
F066EH
CAN0 message control register 06
C0MCTRL06
R/W
Undefined
F0670H
CAN0 message data byte 01 register 07
C0MDB007
C0MDB0107
R/W
Undefined
C0MDB2307
R/W
Undefined
C0MDB4507
R/W
Undefined
C0MDB6707
R/W
Undefined
F0671H
F0672H
C0MDB107
CAN0 message data byte 23 register 07
F0673H
F0674H
C0MDB307
CAN0 message data byte 45 register 07
F0675H
F0676H
C0MDB207
C0MDB407
C0MDB507
CAN0 message data byte 67 register 07
C0MDB607
F0678H
CAN0 message data length register 07
C0MDLC07
R/W
0xH
F0679H
CAN0 message Configuration register 07
C0MCONF07
R/W
Undefined
F067AH
F0677H
C0MDB707
CAN0 message ID register 07L
C0MIDL07
R/W
Undefined
F067CH CAN0 message ID register 07H
C0MIDH07
R/W
Undefined
F067EH
CAN0 message control register 07
C0MCTRL07
R/W
Undefined
F0680H
CAN0 message data byte 01 register 08
C0MDB008
C0MDB0108
R/W
Undefined
C0MDB2308
R/W
Undefined
C0MDB4508
R/W
Undefined
C0MDB6708
R/W
Undefined
F0681H
F0682H
C0MDB108
CAN0 message data byte 23 register 08
F0683H
F0684H
C0MDB308
CAN0 message data byte 45 register 08
F0685H
F0686H
C0MDB208
C0MDB408
C0MDB508
CAN0 message data byte 67 register 08
C0MDB608
F0688H
CAN0 message data length register 08
C0MDLC08
R/W
0xH
F0689H
CAN0 message Configuration register 08
C0MCONF08
R/W
Undefined
F068AH
CAN0 message ID register 08L
C0MIDL08
R/W
Undefined
F068CH CAN0 message ID register 08H
C0MIDH08
R/W
Undefined
F0687H
C0MDB708
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (20/21)
Address
F068EH
F0690H
Special Function Register (SFR) Name
CAN0 message control register 08
CAN0 message data byte 01 register 09
F0691H
F0692H
Manipulable Bit Range After Reset
1-bit
8-bit
16-bit
C0MCTRL08
R/W
Undefined
C0MDB009
C0MDB0109
R/W
Undefined
C0MDB2309
R/W
Undefined
C0MDB4509
R/W
Undefined
C0MDB6709
R/W
Undefined
C0MDB209
C0MDB309
CAN0 message data byte 45 register 09
F0695H
F0696H
R/W
C0MDB109
CAN0 message data byte 23 register 09
F0693H
F0694H
Symbol
C0MDB409
C0MDB509
CAN0 message data byte 67 register 09
F0697H
C0MDB609
C0MDB709
F0698H
CAN0 message data length register 09
C0MDLC09
R/W
0xH
F0699H
CAN0 message Configuration register 09
C0MCONF09
R/W
Undefined
Undefined
F069AH
CAN0 message ID register 09L
C0MIDL09
R/W
F069CH
CAN0 message ID register 09H
C0MIDH09
R/W
Undefined
F069EH
CAN0 message control register 09
C0MCTRL09
R/W
Undefined
F06A0H
CAN0 message data byte 01 register 10
C0MDB010
C0MDB0110
R/W
Undefined
C0MDB2310
R/W
Undefined
C0MDB4510
R/W
Undefined
C0MDB6710
R/W
Undefined
F06A1H
F06A2H
C0MDB110
CAN0 message data byte 23 register 10
F06A3H
F06A4H
C0MDB310
CAN0 message data byte 45 register 10
F06A5H
F06A6H
C0MDB210
C0MDB410
C0MDB510
CAN0 message data byte 67 register 10
C0MDB610
F06A8H
CAN0 message data length register 10
C0MDLC10
R/W
0xH
F06A9H
CAN0 message Configuration register 10
C0MCONF10
R/W
Undefined
F06AAH
CAN0 message ID register 10L
C0MIDL10
R/W
Undefined
F06ACH
CAN0 message ID register 10H
C0MIDH10
R/W
Undefined
F06AEH
CAN0 message control register 10
C0MCTRL10
F06B0H
CAN0 message data byte 01 register 11
C0MDB011
F06A7H
C0MDB710
F06B1H
F06B2H
CAN0 message data byte 45 register 11
Undefined
Undefined
C0MDB211
C0MDB2311
R/W
Undefined
C0MDB411
C0MDB4511
R/W
Undefined
C0MDB6711
R/W
Undefined
R/W
0xH
C0MDB511
CAN0 message data byte 67 register 11
C0MDB611
CAN0 message data length register 11
C0MDLC11
F06B7H
F06B8H
C0MDB311
F06B5H
F06B6H
R/W
C0MDB111
CAN0 message data byte 23 register 11
F06B3H
F06B4H
R/W
C0MDB0111
C0MDB711
F06B9H
CAN0 message Configuration register 11
C0MCONF11
R/W
Undefined
F06BAH
CAN0 message ID register 11L
C0MIDL11
R/W
Undefined
F06BCH
CAN0 message ID register 11H
C0MIDH11
R/W
Undefined
F06BEH
CAN0 message control register 11
C0MCTRL11
F06C0H
CAN0 message data byte 01 register 12
C0MDB012
F06C1H
F06C2H
Undefined
R/W
Undefined
C0MDB2312
R/W
Undefined
C0MDB4512
R/W
Undefined
C0MDB112
CAN0 message data byte 23 register 12
F06C3H
F06C4H
R/W
C0MDB0112
C0MDB212
C0MDB312
CAN0 message data byte 45 register 12
F06C5H
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (21/21)
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit Range After Reset
1-bit
8-bit
16-bit
R/W
C0MDLC12
R/W
0XH
CAN0 message Configuration register 12
C0MCONF12
R/W
Undefined
F06CAH
CAN0 message ID register 12L
C0MIDL12
R/W
Undefined
F06CCH
CAN0 message ID register 12H
C0MIDH12
R/W
Undefined
F06CEH
CAN0 message control register 12
C0MCTRL12
F06D0H
CAN0 message data byte 01 register 13
C0MDB013
F06C6H
CAN0 message data byte 67 register 12
C0MDB612
F06C8H
CAN0 message data length register 12
F06C9H
F06C7H
CAN0 message data byte 23 register 13
Undefined
R/W
Undefined
C0MDB213
C0MDB2313
R/W
Undefined
C0MDB4513
R/W
Undefined
C0MDB6713
R/W
Undefined
C0MDB313
CAN0 message data byte 45 register 13
F06D5H
F06D6H
R/W
C0MDB0113
C0MDB113
F06D3H
F06D4H
Undefined
C0MDB712
F06D1H
F06D2H
C0MDB6712
C0MDB413
C0MDB513
CAN0 message data byte 67 register 13
C0MDB613
F06D8H
CAN0 message data length register 13
C0MDLC13
R/W
0XH
F06D9H
CAN0 message Configuration register 13
C0MCONF13
R/W
Undefined
F06DAH
CAN0 message ID register 13L
C0MIDL13
R/W
Undefined
F06DCH
CAN0 message ID register 13H
C0MIDH13
R/W
Undefined
F06DEH
CAN0 message control register 13
C0MCTRL13
F06E0H
CAN0 message data byte 01 register 14
C0MDB014
F06D7H
C0MDB713
F06E1H
F06E2H
CAN0 message data byte 23 register 14
Undefined
Undefined
C0MDB214
C0MDB2314
R/W
Undefined
C0MDB4514
R/W
Undefined
C0MDB6714
R/W
Undefined
C0MDB314
CAN0 message data byte 45 register 14
F06E5H
F06E6H
R/W
C0MDB114
F06E3H
F06E4H
R/W
C0MDB0114
C0MDB414
C0MDB514
CAN0 message data byte 67 register 14
F06E7H
C0MDB614
C0MDB714
CAN0 message data length register 14
C0MDLC14
R/W
0XH
F06E9H
CAN0 message Configuration register 14
C0MCONF14
R/W
Undefined
F06EAH
CAN0 message ID register 14L
C0MIDL14
R/W
Undefined
F06ECH
CAN0 message ID register 14H
C0MIDH14
R/W
Undefined
F06EEH
CAN0 message control register 14
C0MCTRL14
F06F0H
CAN0 message data byte 01 register 15
C0MDB015
F06E8H
F06F1H
F06F2H
CAN0 message data byte 23 register 15
Undefined
Undefined
C0MDB215
C0MDB2315
R/W
Undefined
C0MDB4515
R/W
Undefined
C0MDB6715
R/W
Undefined
C0MDB315
CAN0 message data byte 45 register 15
F06F5H
F06F6H
R/W
C0MDB115
F06F3H
F06F4H
R/W
C0MDB0115
C0MDB415
C0MDB515
CAN0 message data byte 67 register 15
C0MDB615
F06F8H
CAN0 message data length register 15
C0MDLC15
R/W
0xH
F06F9H
CAN0 message Configuration register 15
C0MCONF15
R/W
Undefined
F06FAH
CAN0 message ID register 15L
C0MIDL15
R/W
Undefined
F06FCH
CAN0 message ID register 15H
C0MIDH15
R/W
Undefined
F06FEH
CAN0 message control register 15
C0MCTRL15
R/W
Undefined
F06F7H
C0MDB715
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CHAPTER 3 CPU ARCHITECTURE
3.3 Instruction Address Addressing
3.3.1 Relative addressing
[Function]
Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the
instruction word (signed complement data: 128 to +127 or 32768 to +32767) to the program counter (PC)’s value
(the start address of the next instruction), and specifies the program address to be used as the branch destination.
Relative addressing is applied only to branch instructions.
Figure 3-26. Outline of Relative Addressing
PC
OP code
DISPLACE
8/16 bits
3.3.2 Immediate addressing
[Function]
Immediate addressing stores immediate data of the instruction word in the program counter, and specifies the
program address to be used as the branch destination.
For immediate addressing, CALL !!addr20 or BR !!addr20 is used to specify 20-bit addresses and CALL !addr16 or
BR !addr16 is used to specify 16-bit addresses. 0000 is set to the higher 4 bits when specifying 16-bit addresses.
Figure 3-27. Example of CALL !!addr20/BR !!addr20
PC
OP code
Low Addr.
High Addr.
Seg Addr.
Figure 3-28. Example of CALL !addr16/BR !addr16
PC
PCS
PCH
PCL
OP code
0000
Low Addr.
High Addr.
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CHAPTER 3 CPU ARCHITECTURE
3.3.3 Table indirect addressing
[Function]
Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit
immediate data in the instruction word, stores the contents at that table address and the next address in the program
counter (PC) as 16-bit data, and specifies the program address. Table indirect addressing is applied only for CALLT
instructions.
In the RL78 microcontrollers, branching is enabled only to the 64 KB space from 00000H to 0FFFFH.
Figure 3-29. Outline of Table Indirect Addressing
OP code
High Addr.
00000000
10
0
Low Addr.
Table address
Memory
0000
PC
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PCH
PCL
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CHAPTER 3 CPU ARCHITECTURE
3.3.4 Register direct addressing
[Function]
Register direct addressing stores in the program counter (PC) the contents of a general-purpose register pair
(AX/BC/DE/HL) and CS register of the current register bank specified with the instruction word as 20-bit data, and
specifies the program address. Register direct addressing can be applied only to the CALL AX, BC, DE, HL, and BR
AX instructions.
Figure 3-30. Outline of Register Direct Addressing
OP code
rp
CS
PC
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PCH
PCL
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CHAPTER 3 CPU ARCHITECTURE
3.4 Addressing for Processing Data Addresses
3.4.1 Implied addressing
[Function]
Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the
instruction word, without using any register specification field in the instruction word.
[Operand format]
Because implied addressing can be automatically employed with an instruction, no particular operand format
is necessary.
Implied addressing can be applied only to MULU X.
Figure 3-31. Outline of Implied Addressing
OP code
A register
Memory
3.4.2 Register addressing
[Function]
Register addressing accesses a general-purpose register as an operand. The instruction word of 3-bit long is used
to select an 8-bit register and the instruction word of 2-bit long is used to select a 16-bit register.
[Operand format]
Identifier
Description
r
X, A, C, B, E, D, L, H
rp
AX, BC, DE, HL
Figure 3-32. Outline of Register Addressing
OP code
Register
Memory
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CHAPTER 3 CPU ARCHITECTURE
3.4.3 Direct addressing
[Function]
Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target
address.
[Operand format]
Identifier
Description
ADDR16
Label or 16-bit immediate data (only the space from F0000H to FFFFFH is specifiable)
ES: ADDR16
Label or 16-bit immediate data (higher 4-bit addresses are specified by the ES register)
Figure 3-33. Example of ADDR16
MOV
!addr16,
A
FFFFFH
Instruction code
Target memory
OP-code
Low Addr.
High Addr.
F0000H
A 16-bit address in the 64-Kbyte area from
F0000H to FFFFFH specifies the target location
(for use in access to the 2nd SFRs etc.).
Memory
Figure 3-34. Example of ES:ADDR16
ES: !addr16
FFFFFH
Instruction code
Target memory
OP-code
Specifies the
address in memory
Low Addr.
High Addr.
ES
X0000H
Specifies a
64-Kbyte area
The ES register specifies a 64-Kbyte area within the
overall 1-Mbyte space as the four higher-order bits, X, of
the address range.
A 16-bit address in the area from X0000H to XFFFFH
and the ES register specify the target location;
this is used for access to fixed data other than
that in mirrored areas.
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00000H
Memory
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CHAPTER 3 CPU ARCHITECTURE
3.4.4 Short direct addressing
[Function]
Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of
addressing is applied only to the space from FFE20H to FFF1FH.
[Operand format]
Identifier
SADDR
Description
Label, FFE20H to FFF1FH immediate data, or 0FE20H to 0FF1FH immediate data
(only the space from FFE20H to FFF1FH is specifiable)
SADDRP
Label, FFE20H to FFF1FH immediate data, or 0FE20H to 0FF1FH immediate data (even address only)
(only the space from FFE20H to FFF1FH is specifiable)
Figure 3-35. Outline of Short Direct Addressing
OP code
FFF1FH
saddr
saddr
FFE20H
Memory
Remark SADDR and SADDRP are used to describe the values of addresses FE20H to FF1FH with 16-bit immediate
data (higher 4 bits of actual address are omitted), and the values of addresses FFE20H to FFF1FH with 20bit immediate data.
Regardless of whether SADDR or SADDRP is used, addresses within the space from FFE20H to FFF1FH
are specified for the memory.
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CHAPTER 3 CPU ARCHITECTURE
3.4.5 SFR addressing
[Function]
SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of
addressing is applied only to the space from FFF00H to FFFFFH.
[Operand format]
Identifier
SFR
SFRP
Description
SFR name
16-bit-manipulatable SFR name (even address only)
Figure 3-36. Outline of SFR Addressing
FFFFFH
OP code
SFR
FFF00H
SFR
Memory
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CHAPTER 3 CPU ARCHITECTURE
3.4.6 Register indirect addressing
[Function]
Register indirect addressing directly specifies the target addresses using the contents of the register pair specified
with the instruction word as an operand address.
[Operand format]
Identifier
Description
[DE], [HL] (only the space from F0000H to FFFFFH is specifiable)
ES:[DE], ES:[HL] (higher 4-bit addresses are specified by the ES register)
Figure 3-37. Example of [DE], [HL]
FFFFFH
[DE],
[HL]
Instruction code
rp(HL/DE)
OP-code
Target memory
Specifies the
address in memory
F0000H
Either pair of registers specifies the target
location as an address in the 64-Kbyte area from
F0000H to FFFFFH.
Memory
Figure 3-38. Example of ES:[DE], ES:[HL]
ES: [DE],
ES: [HL]
Instruction code
OP-code
FFFFFH
Specifies the
rp(HL/DE)
address in memory
Area from
X0000H to
XFFFFH
X0000H
Specifies a
ES
64-Kbyte area
The ES register specifies a 64-Kbyte area within the
overall 1-Mbyte space as the four higher-order bits, X, of
the address range.
Either pair of registers and the ES register specify
the target location in the area from X0000H to XFFFFH.
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00000H
Memory
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CHAPTER 3 CPU ARCHITECTURE
3.4.7 Based addressing
[Function]
Based addressing uses the contents of a register pair specified with the instruction word or 16-bit immediate data as
a base address, and 8-bit immediate data or 16-bit immediate data as offset data. The sum of these values is used
to specify the target address.
[Operand format]
Identifier
Description
[HL + byte], [DE + byte], [SP + byte] (only the space from F0000H to FFFFFH is specifiable)
word[B], word[C] (only the space from F0000H to FFFFFH is specifiable)
word[BC] (only the space from F0000H to FFFFFH is specifiable)
ES:[HL + byte], ES:[DE + byte] (higher 4-bit addresses are specified by the ES register)
ES:word[B], ES:word[C] (higher 4-bit addresses are specified by the ES register)
ES:word[BC] (higher 4-bit addresses are specified by the ES register)
Figure 3-39. Example of [SP+byte]
FFFFFH
Instruction code
byte
Offset
Target memory
Stack area
Specifies a
SP
stack area
SP (stack pointer) indicates the stack as the
target.
By indicating an offset from the address (top of the
stack) currently pointed to by the stack pointer,
“byte” indicates the target memory (SP + byte).
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-40. Example of [HL + byte], [DE + byte]
[HL + byte],
[DE + byte]
FFFFFH
Instruction code
OP-code
byte
Address of
Other data in
the array
an array
rp(HL/DE)
Target
array
of data
Target memory
Offset
Either pair of registers specifies the address
where the target array of data starts in the 64-Kbyte
area from F0000H to FFFFFH.
“byte” specifies an offset within the array to
the target location in memory.
F0000H
Memory
Figure 3-41. Example of word[B], word[C]
word
[B],
word
[C]
Instruction code
OP-code
FFFFFH
r(B/C)
Array of
word-sized
data
Target memory
Offset
Address of a word
Low Addr.
within an array
F0000H
High Addr.
“word” specifies the address where the target
array of word-sized data starts in the 64-Kbyte area
from F0000H to FFFFFH.
Either register specifies an offset within the
array to the target location in memory.
Memory
Figure 3-42. Example of word[BC]
word
[BC]
Instruction code
OP-code
Low Addr.
High Addr.
FFFFFH
Target memory
rp(BC)
Offset
Address of a word
within an array
“word” specifies the address where the target
array of word-sized data starts in the 64-Kbyte area
from F0000H to FFFFFH.
A pair of registers specifies an offset within
the array to the target location in memory.
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Figure 3-43. Example of ES:[HL + byte], ES:[DE + byte]
ES: [HL + byte], ES: [DE + byte]
Instruction code
OP-code
XFFFFH
Target memory
Offset
byte
Address of
an array
rp(HL/DE)
ES
Other data in
the array
X0000H
X0000H
Specifies a
64-Kbyte area
The ES register specifies a 64-Kbyte
area within the overall 1-Mbyte space as
the four higher-order bits, X, of the address range.
Either pair of registers specifies the address
where the target array of data starts in the 64-Kbyte
area specified in the ES register .
“byte” specifies an offset within the array to the
target location in memory.
Target
array
of data
Memory
Figure 3-44. Example of ES:word[B], ES:word[C]
ES: word [B], ES: word [C]
Instruction code
XFFFFH
Offset
OP-code
Low Addr.
Target memory
r(B/C)
Array of
word-sized
data
Address of a word within an array
High Addr.
ES
X0000H
Specifies a
64-Kbyte area
X0000H
The ES register specifies a 64-Kbyte area within the overall
Memory
1-Mbyte space as the four higher-order bits, X, of the address range.
“word” specifies the address where the target array of word-sizeddata
starts in the 64-Kbyte area specified in the ES register .
Either register specifies an offset within the array to the target location
in memory.
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Figure 3-45. Example of ES:word[BC]
ES: word [BC]
Instruction code
OP-code
XFFFFH
Low Addr.
Target memory
Offset
rp(BC)
Address of a word within an array
High Addr.
X0000H
X0000H
Specifies a
ES
64-Kbyte area
The ES register specifies a 64-Kbyte area within the
overall 1-Mbyte space as the four higher-order bits, X, of
the address range.
“word” specifies the address where the target array of
word-sized data starts in the 64-Kbyte area specified in the
ES register .
A pair of registers specifies an offset within the array
to the target location in memory.
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3.4.8 Based indexed addressing
[Function]
Based indexed addressing uses the contents of a register pair specified with the instruction word as the base
address, and the content of the B register or C register similarly specified with the instruction word as offset address.
The sum of these values is used to specify the target address.
[Operand format]
Identifier
Description
[HL+B], [HL+C] (only the space from F0000H to FFFFFH is specifiable)
ES:[HL+B], ES:[HL+C] (higher 4-bit addresses are specified by the ES register)
Figure 3-46. Example of [HL+B], [HL+C]
[HL +B],
[HL+C]
FFFFFH
Target memory
Instruction code
r(B/C)
OP-code
Offset
rp(HL)
Address of
an array
A pair of registers specifies the address where the target
array of data starts in the 64-Kbyte area from F0000H to
FFFFFH.
Either register specifies an offset within the array to the
target location in memory
Other data in
the array
Target
array
of data
F0000H
Memory
Figure 3-47. Example of ES:[HL+B], ES:[HL+C]
ES: [HL +B], ES: [HL +C]
XFFFFH
Instruction code
OP-code
Target memory
r(B/C)
rp(HL)
byte
ES
Offset
Address of
the array
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X0000H
X0000H
Specifies a
64-Kbyte area
The ES register specifies a 64-Kbyte area within the overall
1-Mbyte space as the four higher-order bits, X, of the address range.
A pair of registers specifies the address where the target
array of data starts in the 64-Kbyte area specified in the ES
register .
Either register specifies an offset within the array to the
target location in memory.
Target
array
of data
Memory
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3.4.9 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing is automatically
employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is
saved/restored upon generation of an interrupt request.
Stack addressing is applied only to the internal RAM area.
[Operand format]
Identifier
Description
PUSH AX/BC/DE/HL
POP AX/BC/DE/HL
CALL/CALLT
RET
BRK
RETB
(Interrupt request generated)
RETI
Each stack operation saves or restores data as shown in Figures 3-48 to 3-53.
Figure 3-48. Example of PUSH rp
PUSH
rp
Instruction code
OP-code
SP
SP
SP - 1
SP - 2
Higher-order byte of rp
Lower-order byte of rp
rp
Stack addressing is specified .
The higher-order and lower-order bytes of the pair of registers
indicated by rp are stored in addresses SP - 1 and SP - 2,
respectively.
The value of SP is decreased by two (if rp is the program
status word (PSW), the value of the PSW is stored in SP - 1 and
0 is stored in SP - 2).
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Figure 3-49. Example of POP
POP
rp
Instruction code
OP-code
SP
SP
SP+ 2
SP+ 1
SP
(SP+1)
(SP)
Stack
area
F0000H
rp
Stack addressing is specified .
The contents of addresses SP and SP + 1 are stored in the
lower-order and higher-order bytes of the pair of registers
indicated by rp , respectively.
The value of SP is increased by two (if rp is the program
status word (PSW), the content of address SP + 1 is stored in
the PSW).
Memory
Figure 3-50. Example of CALL, CALLT
CALL
Instruction code
SP
OP-code
SP
SP - 1
SP - 2
SP - 3
SP - 4
PC19 - PC16
PC15 - PC8
PC7 - PC0
F0000H
PC
Stack addressing is specified . The value of the program
counter (PC) changes to indicate the address of the instruction
following the CALL instruction.
The values of PC bits 19 to 16, 15 to 8, and 7 to 0 are stored in
addresses SP - 2, SP - 3, and SP - 4, respectively .
The value of the SP is decreased by 4.
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Figure 3-51. Example of RET
RET
Instruction code
SP
OP-code
SP
SP+4
SP+3
SP+2
SP+1
SP
(SP+3)
(SP+2)
(SP+1)
(SP)
Stack
area
F0000H
PC
Stack addressing is specified .
The contents of addresses SP, SP + 1, and SP + 2 are stored
in PC bits 7 to 0, 15 to 8, and 19 to 16, respectively .
The value of SP is increased by four.
Memory
Figure 3-52. Example of Interrupt, BRK
PSW
Instruction code
SP
OP-code
or
SP
Interrupt
SP - 1
SP - 2
SP - 3
SP - 4
PSW
PC19 - PC16
PC15 - PC8
PC7 - PC0
F0000H
PC
Stack addressing is specified . In response to a BRK
instruction or acceptance of an interrupt, the value of the
program counter (PC) changes to indicate the address of
the next instruction.
The values of the PSW, PC bits 19 to 16, 15 to 8, and 7 to
0 are stored in addresses SP - 1, SP - 2, SP - 3, and
SP - 4, respectively .
The value of the SP is decreased by 4.
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Figure 3-53. Example of RETI, RETB
RETI, RETB
PSW
Instruction code
SP
OP-code
SP
SP+4
SP+3
SP+2
SP+1
SP
(SP+3)
(SP+2)
(SP+1)
(SP)
F0000H
PC
Stack addressing is specified .
The contents of addresses SP, SP + 1, SP + 2, and SP + 3 are
stored in PC bits 7 to 0, 15 to 8, 19 to 16, and the PSW, respectively
.
The value of SP is increased by four.
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CHAPTER 4 PORT FUNCTIONS
4.1 Port Functions
The RL78/D1A microcontrollers are provided with digital I/O ports, which enable variety of control operations.
In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate
functions, see CHAPTER 2 PIN FUNCTIONS.
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4.2 Port Configuration
Ports include the following hardware.
Table 4-1. Port Configuration
Item
Control registers
Configuration
Port mode registers (PM0 to PM15)
Port registers (P0 to P15)
Pull-up resistor option registers (PU0, PU1, PU3 to PU14)
Port input mode registers (PIM0, PIM1, PIM3, PIM5 to PIM7, PIM11, PIM13)
Port output mode registers (POM)
LCD port function register
(LCDPF0, LCDPF1, LCDPF3 to LCDPF5, LCDPF7 to LCDPF13)
A/D port configuration register (ADPC)
Stepper motor port control register (SMPC)
Port
• 48-pin products
Total: 38 (CMOS I/O: 35 (LED direct drive: 9, N-ch open drain selectable: 4), CMOS input: 3)
• 64-pin products
Total: 54 (CMOS I/O: 49(LED direct drive: 13, N-ch open drain selectable: 4), CMOS input: 5)
• 80-pin products
Total: 68 (CMOS I/O: 63(LED direct drive: 16, N-ch open drain selectable: 4), CMOS input: 5)
• 100-pin products
Total: 84 (CMOS I/O: 78(LED direct drive: 16, N-ch open drain selectable:6), CMOS input: 5, CMOS output: 1)
• 128-pin products
Total: 112 (CMOS I/O: 106(LED direct drive: 16, N-ch open drain selectable:6), CMOS input: 5, CMOS output: 1)
Pull-up resistor
• 48-pin products
Total: 30
• 64-pin products
Total: 44
• 80-pin products
Total: 55
• 100-pin products Total: 69
• 128-pin products Total: 95
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4.2.1 Port 0
48-pin products:
P00 to P01 function as a 2-bit I/O port.
64-pin products:
P00 to P05 and P07 function as a 7-bit I/O port.
80-pin products:
P00 to P07 function as an 8-bit I/O port.
100-pin products:
P00 to P07 function as an 8-bit I/O port.
128-pin products:
P00 to P07 function as an 8-bit I/O port.
Port 0 is an 8-bit or a 7-bit, or a 2-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in
1-bit units using port mode register 0 (PM0). When the P00 to P07 pins are used as an input port, use of an on-chip pullup resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0).
Input to the P01 pin can be specified through a normal Schmitt3 input buffer or a Schmitt1 input buffer using port input
mode register 0 (PIM0).
These pins also function as timer I/O, serial interface data I/O, and segment signal outputs for the LCD controller/driver.
To use P00 to P07 as the port function, refer Table 4-2.
Table 4-2. Setting of P00 to P07 Pins to port function
P00 to P07 Pins
port
P00
LCDPF0
Register
function
Input port
Digital I/O selection
Output port
P01
Input port
Alternate function
Timer
Serial
0
Digital I/O selection
-
-
PM0
PIM0
POM
Register
Register
Register
N/A
N/A
0
N/A
Input mode
1
Output mode
N/A
Input mode
Schmitt1 input
1
Output port
P02
Input port
0
Digital I/O selection
Output port
P03
Input port
P04
Input port
0
Digital I/O selection
Output port
Input port
Input port
Digital I/O selection
Input port
-
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Input mode
-
Input mode
1
Output mode
N/A
Input mode
Output mode
-
N/A
Input mode
Output mode
-
N/A
Input mode
0
LCD segment
N/A
N/A
0
Output port
-
Input mode
Output mode
0
Digital I/O selection
-
Output mode
-
Digital I/O selection
Schmitt3 input
Output mode
1
0
Output port
P07
-
0
Output port
P06
-
Digital I/O selection
Output port
P05
-
Remarks
Output mode
-
output selection
-
-
-
-
LCD segment
output
Reset signal generation sets port 0 to input mode.
Figures 4-1 to 4-6 show block diagrams of port 0.
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Figure 4-1. Block Diagram of P00
EVDD
WRPU
PU0
PU00
P-ch
Alternate
function
WRPORT
P0
Output latch
(P00)
WRPM
PM0
PM00
Selector
Internal bus
Selector
RD
P00/TI00/TO00/
CTxD0/SEG14
Alternate
function
(TO00)
Alternate
function
(CTxD0)
LCD controller/driver
WRLCDPF
LCDPF0
PF00
P0:
PU0:
PM0:
LCDPF0:
RD:
WRxx:
Caution
Port register 0
Pull-up resistor option register 0
Port mode register 0
LCD port function registers 0
Read signal
Write signal
When using the alternate function TO00, set the port latch to 0.
When using the alternate function CTxD0, set the port latch to 1.
When using P00 as a general-purpose port, specify the port settings so that the alternate function
outputs are fixed (Timer to 0 and Serial to 1).
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Figure 4-2. Block Diagram of P01
EVDD
WRPU
PU0
PU01
P-ch
WRPIM
PIM0
PIM01
Alternate
function
Schmitt1
Schmitt3
WRPORT
P0
Output latch
(P01)
WRPM
PM0
PM01
Selector
Internal bus
Selector
RD
P01/TI01/TO01/
CRxD0/SEG15
Alternate
function
(TO01)
LCD controller/driver
WRLCDPF
LCDPF0
PF01
P0:
PU0:
PM0:
PIM0:
LCDPF0:
RD:
WRxx:
Caution
Port register 0
Pull-up resistor option register 0
Port mode register 0
Port Input mode register 0
LCD port function registers 0
Read signal
Write signal
When using the alternate function TO01, set the port latch to 0.
When using P01 as a general-purpose port, specify the port settings so that the alternate function
output is fixed to 0.
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Figure 4-3. Block Diagram of P02
EVDD
WRPU
PU0
PU02
P-ch
Alternate
function
Selector
RD
WRPORT
Internal bus
P0
WRPM
PM0
PM02
Selector
Output latch
(P02)
P02/SO00/TI02/
TO02/TI12/TO12/
SEG16
Alternate
function
(TO02)
Alternate
function
(TO12)
Alternate
function
(SO00)
LCD controller/driver
WRLCDPF
LCDPF0
PF02
P0:
PU0:
PM0:
LCDPF0:
RD:
WRxx:
Caution
Port register 0
Pull-up resistor option register 0
Port mode register 0
LCD port function registers 0
Read signal
Write signal
When using the alternate function TO02 or TO12, set the port latch to 0.
When using the alternate function SO00, set the port latch to 1.
When using P02 as a general-purpose port, specify the port settings so that the alternate function
outputs are fixed (Timer to 0 and Serial to 1).
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Figure 4-4. Block Diagram of P03
EVDD
WRPU
PU0
PU03
P-ch
Alternate
function
Selector
RD
WRPORT
Internal bus
P0
WRPM
PM0
PM03
Selector
Output latch
(P03)
P03/SI00/TI03/
TO03/TI13/TO13/
SEG17
Alternate
function
(TO03)
Alternate
function
(TO13)
LCD controller/driver
WRLCDPF
LCDPF0
PF03
P0:
PU0:
PM0:
LCDPF0:
RD:
WRxx:
Caution
Port register 0
Pull-up resistor option register 0
Port mode register 0
LCD port function registers 0
Read signal
Write signal
When using the alternate function TO03 or TO13, set the port latch to 0.
When using P03 as a general-purpose port, specify the port settings so that the alternate function
outputs are fixed 0.
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Figure 4-5. Block Diagram of P04
EVDD
WRPU
PU0
PU04
P-ch
Alternate
function
Selector
RD
WRPORT
Internal bus
P0
WRPM
PM0
PM04
Selector
Output latch
(P04)
P04/SCK00/TI04/
TO04/TI14/TO14/
SEG18
Alternate
function
(TO04)
Alternate
function
(TO14)
Alternate
function
(SCK00)
LCD controller/driver
WRLCDPF
LCDPF0
PF04
P0:
PU0:
PM0:
LCDPF0:
RD:
WRxx:
Caution
Port register 0
Pull-up resistor option register 0
Port mode register 0
LCD port function registers 0
Read signal
Write signal
When using the alternate function TO04 or TO14, set the port latch to 0.
When using the alternate function SCK00, set the port latch to 1.
When using P04 as a general-purpose port, specify the port settings so that the alternate function
outputs are fixed (Timer to 0 and Serial to 1).
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Figure 4-6. Block Diagram of P05 to P07
EVDD
WRPU
PU0
PU05 to PU07
P-ch
Alternate
function
Selector
RD
WRPORT
Internal bus
P0
WRPM
PM0
PM05 to PM07
Alternate
function
(TO05 to TO07)
Selector
Output latch
(P05 to P07)
P05/TI05/
TO05/TI15/TO15/
SEG19,
P06/TI06/TO06/
TI16/TO16/SEG20,
P07/TI07/TO07/
TI17/TO17/SEG21
Alternate
function
(TO15 to TO17)
LCD controller/driver
WRLCDPF
LCDPF0
PF05 to PF07
P0:
PU0:
PM0:
LCDPF0:
RD:
WRxx:
Caution
Port register 0
Pull-up resistor option register 0
Port mode register 0
LCD port function registers 0
Read signal
Write signal
When using the alternate function TO05 to TO07 or TO15 to TO17, set the port latch to 0.
When using P05 to P07 as a general-purpose port, specify the port settings so that the alternate
function outputs are fixed 0.
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4.2.2 Port 1
48-pin products:
P10 to P14 function as a 5-bit I/O port.
64-pin products:
P10 to P15 and P17 function as a 7-bit I/O port.
80-pin products:
P10 to P17 function as an 8-bit I/O port.
100-pin products:
P10 to P17 function as an 8-bit I/O port.
128-pin products:
P10 to P17 function as an 8-bit I/O port.
Port 1 is an 8-bit or a 7-bit, or a 5-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in
1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pullup resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1).
Input to the P10, P11, and P17 pins can be specified through a normal Schmitt3 input buffer or a Schmitt1 input buffer
using port input mode register 1 (PIM1).
These pins also function as serial interface data I/O, timer I/O, clock I/O, external interrupt request input and segment
signal outputs for the LCD controller/driver.
To use P10 to P17 as the port function, refer Table 4-3.
Table 4-3. Setting of P10 to P17 Pins to port function
P10 to P17 Pins
port
P10
LCDPF1
Alternate
PM1
PIM1
POM
Register
function
Register
Register
Register
0
N/A
function
Input port
Timer
Serial
-
-
Digital I/O selection
Input mode
Schmitt1 input
1
Output port
P11
Input port
0
Digital I/O selection
-
1
Output mode
N/A
Input mode
Schmitt3 input
0
N/A
Schmitt1 input
1
Output port
P12
Input port
0
Digital I/O selection
Output port
P13
Input port
Input port
Digital I/O selection
Input port
Input port
Input port
-
Digital I/O selection
-
N/A
N/A
Output mode
N/A
N/A
N/A
Input mode
N/A
N/A
N/A
N/A
N/A
N/A
0
N/A
Output mode
0
-
-
Input mode
1
Output mode
N/A
Input mode
0
Digital I/O selection
Input mode
1
-
Digital I/O selection
Input mode
Schmitt3 input
Output mode
0
Output port
P17
-
Digital I/O selection
Output port
P16
1
0
Output port
P15
0
Output port
P14
Output mode
Output mode
-
N/A
Input mode
Schmitt1 input
1
Output port
-
-
0
LCD segment
Remarks
Output mode
-
output selection
-
-
Schmitt3 input
-
-
LCD segment
output
Reset signal generation sets port 1 to input mode.
Figures 4-7 to 4-11 show block diagrams of port 1.
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Figure 4-7. Block Diagram of P10
EVDD
WRPU
PU1
PU10
P-ch
WRPIM
PIM1
PIM10
Alternate
function
Schmitt1
Schmitt3
WRPORT
P1
Output latch
(P10)
WRPM
PM1
PM10
Selector
Internal bus
Selector
RD
P10/LTxD1/
SCK00/TI10/
TO10/INTP4/
SEG31
Alternate
function
(TO10)
Alternate
function
(LTxD1)
Alternate
function
(SCK00)
LCD controller/driver
WRLCDPF
LCDPF1
PF10
P1:
PU1:
PM1:
PIM1:
LCDPF1:
RD:
WRxx:
Caution
Port register 1
Pull-up resistor option register 1
Port mode register 1
Port Input mode register 1
LCD port function registers 1
Read signal
Write signal
When using the alternate function TO10, set the port latch to 0.
When using the alternate function LTxD1 or SCK00, set the port latch to 1.
When using P10 as a general-purpose port, specify the port settings so that the alternate function
outputs are fixed (Timer to 0 and Serial to 1).
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Figure 4-8. Block Diagram of P11, P17
EVDD
WRPU
PU1
PU11, PU17
P-ch
WRPIM
PIM1
PIM11, PIM17
Alternate
function
Schmitt1
Schmitt3
WRPORT
P1
Output latch
(P11, P17)
WRPM
PM1
PM11, PM17
Selector
Internal bus
Selector
RD
P11/LRxD1/
INTPLR1/SI00/
TI11/TO11/SEG30,
P17/TI17/
TO17/INTP0/SEG28
Alternate
function
(TO11, TO17)
LCD controller/driver
WRLCDPF
LCDPF1
PF11, PF17
P1:
PU1:
PM1:
PIM1:
LCDPF1:
RD:
WRxx:
Caution
Port register 1
Pull-up resistor option register 1
Port mode register 1
Port Input mode register 1
LCD port function registers 1
Read signal
Write signal
When using the alternate function TO11 or TO17, set the port latch to 0.
When using P11 or P17 as a general-purpose port, specify the port settings so that the alternate
function output is fixed to 0.
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Figure 4-9. Block Diagram of P12, P13
EVDD
WRPU
PU1
PU12, PU13
P-ch
Alternate
function
WRPORT
P1
Output latch
(P12, P13)
WRPM
PM1
PM12, PM13
Selector
Internal bus
Selector
RD
P12/SO00/TI12/
TO12/INTP2/SEG29,
P13/SO01/TI13/
TO13/SEG25
Alternate
function
(TO12, TO13)
Alternate
function
(SO00, SO01)
LCD controller/driver
WRLCDPF
LCDPF1
PF12, PF13
P1:
PU1:
PM1:
LCDPF1:
RD:
WRxx:
Caution
Port register 1
Pull-up resistor option register 1
Port mode register 1
LCD port function registers 1
Read signal
Write signal
When using the alternate function TO12 or TO13, set the port latch to 0.
When using the alternate function SO00 or SO01, set the port latch to 1.
When using P12 or P13 as a general-purpose port, specify the port settings so that the alternate
function outputs are fixed (Timer to 0 and Serial to 1).
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Figure 4-10. Block Diagram of P14, P16
EVDD
WRPU
PU1
PU14, PU16
P-ch
Alternate
function
RD
WRPORT
P1
Output latch
(P14, P16)
WRPM
PM1
PM14, PM16
P14/TI14/
TO14/LRxD0/
INTPLR0/SEG24,
P16/TI16/TO16/
SEG22
Alternate
function
(TO14, TO16)
LCD controller/driver
WRLCDPF
LCDPF1
PF14, PF16
P1:
PU1:
PM1:
LCDPF1:
RD:
WRxx:
Caution
Port register 1
Pull-up resistor option register 1
Port mode register 1
LCD port function registers 1
Read signal
Write signal
When using the alternate function TO14 or TO16, set the port latch to 0.
When using P14 or P16 as a general-purpose port, specify the port settings so that the alternate
function output is fixed 0.
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Figure 4-11. Block Diagram of P15
EVDD
WRPU
PU1
PU15
P-ch
Alternate
function
Selector
RD
WRPORT
Internal bus
P1
WRPM
PM1
PM15
Selector
Output latch
(P15)
P15/TI15/TO15/
LTxD0/RTC1HZ/
SEG23
Alternate
function
(TO15)
Alternate
function
(RTC1HZ)
Alternate
function
(LTxD0)
LCD controller/driver
WRLCDPF
LCDPF1
PF15
P1:
PU1:
PM1:
LCDPF1:
RD:
WRxx:
Caution
Port register 1
Pull-up resistor option register 1
Port mode register 1
LCD port function registers 1
Read signal
Write signal
When using the alternate function TO15, set the port latch to 0.
When using the alternate function LTxD0, set the port latch to 1.
When using P15 as a general-purpose port, specify the port settings so that the alternate function
outputs are fixed (Timer to 0 and Serial to 1).
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4.2.3 Port 2
48-pin products:
P20 to P23 and P27 function as a 5-bit I/O.
64-pin products:
P20 to P23 and P27 function as a 5-bit I/O.
80-pin products:
P20 to P27 function as an 8-bit I/O port.
100-pin products:
P20 to P27 function as an 8-bit I/O port
128-pin products:
P20 to P27 function as an 8-bit I/O port
Port 2 is an 8-bit or a 5-bit I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units
using port mode register 2 (PM2).
This port can also be used for A/D converter analog input and reference voltage input.
To use P20/ANI0 to P27/ANI7 as digital input pins, set them in the digital I/O mode by using the A/D port configuration
register (ADPC) and in the input mode by using the PM2 register. Use these pins starting from the upper bit.
To use P20/ANI0 to P27/ANI7 as digital output pins, set them in the digital I/O mode by using the ADPC register and in
the output mode by using the PM2 register. Use these pins starting from the upper bit.
To use P20/ANI0 to P27/ANI7 as analog input pins, set them in the analog input mode by using the A/D port
configuration register (ADPC) and in the input mode by using the PM2 register. Use these pins starting from the lower bit.
Table 4-4. Setting Functions of P20 to P27 Pins
P20 to P27 Pins
port
P20
function
Input port
ADPC
PM2
Register
Register
0001
Output port
P21
Input port
Input port
0001 or 0010
Input port
0001 to 0011
Input port
0001 to 0100
Input port
0001 to 0101
Input port
0001 to 0110
Input port
Output port
Input mode
Output mode
0001 to 0111
Output port
P27
Input mode
Output mode
Output port
P26
Input mode
Output mode
Output port
P25
Input mode
Output mode
Output port
P24
Input mode
Output mode
Output port
P23
Input mode
Output mode
Output port
P22
Remarks
Input mode
Output mode
0001 to 1000
Input mode
Output mode
All P20/ANI0/AVREFP to P27/ANI7 are set in the analog input mode when the reset signal is generated.
Figures 4-12 shows block diagram of port 2.
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Figure 4-12. Block Diagram of P20 to P27
WR ADPC
ADPC
Input enable
ADPC3 to ADPC0
Internal bus
Selector
RD
WRPORT
P2
Output latch
(P20 to P27)
P20/ANI0/AVREFP,
P21/ANI1/AVREFM,
P22/ANI22 to P27/ANI7
WRPM
PM2
PM20 to PM27
A/D converter
P2:
PM2:
ADPC:
RD:
WRxx:
Port register 2
Port mode register 2
A/D port configuration register
Read signal
Write signal
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4.2.4 Port 3
Port 3 is an 8-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using
port mode register 3 (PM3). When the P30 to P37 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 3 (PU3).
Input to the P31 pin can be specified through a normal Schmitt3 input buffer or a Schmitt1 input buffer using port input
mode register 3 (PIM3).
Output from the P30 and P31 pins can be specified as normal CMOS output or N-ch open-drain output (VDD tolerance)
in 1-bit units, using port output mode register (POM).
These pins also function as timer I/O, serial interface data I/O, and segment signal outputs for the LCD controller/driver.
To use P30 to P37 as the port function, refer Table 4-5.
Table 4-5. Setting of P30 to P37 Pins to port function
P30 to P37 Pins
port
P30
P31
function
LCDPF3
Register
Input port
Digital I/O
Output port
selection
Input port
Alternate function
Timer
Serial
-
-
0
Digital I/O
1
-
PM3
PIM3
POM
Register
Register
Register
Input mode
P32
-
Input mode
P33
P34
P35
P36
P37
-
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
-
LCD
0
CMOS output
1
N-ch OD output
0
Schmitt1 input
1
0
Input port
-
Output mode
selection
Output port
N/A
1
0
-
Output mode
-
Input mode
1
Output mode
N/A
Input mode
0
Remarks
Schmitt3 input
-
0
CMOS output
1
N-ch OD output
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Output mode
-
0
-
-
Input mode
1
Output mode
N/A
Input mode
0
Output mode
-
N/A
Input mode
0
Output mode
-
N/A
Input mode
0
Output mode
-
-
Segment
-
-
-
LCD segment
output
output
selection
Reset signal generation sets port 3 to input mode.
Figures 4-13 to 4-16 show block diagrams of port3.
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Figure 4-13. Block Diagram of P30
EVDD
WRPU
PU3
PU30
P-ch
Alternate
function
RD
WRPORT
P3
Output latch
(P30)
WRPM
PM3
PM30
P30/TI20/TO20/
SCL11/SEG6
Alternate
function
(TO20)
WRPOM
POM
POM_2
Alternate
function
(SCL11)
LCD controller/driver
WRLCDPF
LCDPF3
PF30
P3:
PU3:
PM3:
LCDPF3:
POM:
RD:
WRxx:
Caution
Port register 3
Pull-up resistor option register 3
Port mode register 3
LCD port function registers 3
Port Output mode register
Read signal
Write signal
When using the alternate function TO20, set the port latch to 0.
When using the alternate function SCL11, set the port latch to 1.
When using P30 as a general-purpose port, specify the port settings so that the alternate function
outputs are fixed (Timer to 0 and Serial to 1).
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Figure 4-14. Block Diagram of P31
EVDD
WRPU
PU3
PU31
WRPIM
P-ch
PIM3
PIM31
Alternate
function
Schmitt1
Selector
RD
Schmitt3
WRPORT
Output latch
(P31)
WRPM
PM3
PM31
Selector
Internal bus
P3
P31/TI21/TO21/
SDA11/SEG7
Alternate
function
(TO21)
WRPOM
POM
POM_3
Alternate
function
(SDA11)
LCD controller/driver
WRLCDPF
LCDPF3
PF31
P3:
PU3:
PM3:
PIM3:
LCDPF3:
POM:
RD:
WRxx:
Caution
Port register 3
Pull-up resistor option register 3
Port mode register 3
Port Input mode register 3
LCD port function registers 3
Port Output mode register
Read signal
Write signal
When using the alternate function TO21, set the port latch to 0.
When using the alternate function SDA11, set the port latch to 1.
When using P31 as a general-purpose port, specify the port settings so that the alternate function
outputs are fixed (Timer to 0 and Serial to 1).
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Figure 4-15. Block Diagram of P32, P34
EVDD
WRPU
PU3
PU32, PU34
P-ch
Alternate
function
Selector
RD
WRPORT
Internal bus
P3
WRPM
PM3
PM32, PM34
Selector
Output latch
(P32, P34)
P32/TI22/TO22/
SO00/SEG8,
P34/TI24/TO24/
SCK00/SEG10
Alternate
function
(TO22, TO24)
Alternate
function
(SO00, SCK00)
LCD controller/driver
WRLCDPF
LCDPF3
PF32, PF34
P3:
PU3:
PM3:
LCDPF3:
RD:
WRxx:
Caution
Port register 3
Pull-up resistor option register 3
Port mode register 3
LCD port function registers 3
Read signal
Write signal
When using the alternate function TO22 or TO24, set the port latch to 0.
When using the alternate function SO00 or SCK00, set the port latch to 1.
When using P32 or P34 as a general-purpose port, specify the port settings so that the alternate
function outputs are fixed (Timer to 0 and Serial to 1).
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Figure 4-16. Block Diagram of P33, P35 to P37
EVDD
WRPU
PU3
PU33, PU35 to PU37
P-ch
Alternate
function
RD
WRPORT
P3
Output latch
(P33, P35 to P37)
WRPM
PM3
PM33, PM35 to PM37
P33/TI23/TO23/
SI00/SEG9,
P35/TI25/TO25/
SEG11 to
P37/TI27/TO27/
SEG13
Alternate
function
(TO23, TO25 to
TO27)
LCD controller/driver
WRLCDPF
LCDPF3
PF33, PF35 to PF37
P3:
PU3:
PM3:
LCDPF3:
RD:
WRxx:
Caution
Port register 3
Pull-up resistor option register 3
Port mode register 3
LCD port function registers 3
Read signal
Write signal
When using the alternate function TO23 or TO25 to TO27, set the port latch to 0.
When using P33 or P35 to P37 as a general-purpose port, specify the port settings so that the
alternate function output is fixed to 0.
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4.2.5 Port 4
48-pin products:
P40 function as a 1-bit I/O.
64-pin products:
P40 function as a 1-bit I/O.
80-pin products:
P40 function as a 1-bit I/O.
100-pin products:
P40 function as a 1-bit I/O.
128-pin products:
P40 to P47 function as an 8-bit I/O port
Port 4 is a 1-bit or a 8-bit I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units
using port mode register 4 (PM4). When the P40 pin is used as an input port, use of an on-chip pull-up resistor can be
specified by pull-up resistor option register 4 (PU4).
To use P40 to P47 as the port function, refer Table 4-6.
Table 4-6. Setting of P40 to P47 Pins to port function
P40 to P47 Pins
port
P40
P41
P42
P43
P44
P45
P46
P47
-
function
LCDPF4
Alternate function
Register
Timer
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
0
Input port
Digital I/O
N/A
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
-
LCD
N/A
Serial
N/A
PM4
PIM4
POM
Register
Register
Register
Input mode
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Remarks
Output mode
-
N/A
Input mode
0
Output mode
-
N/A
Input mode
0
Output mode
-
N/A
Input mode
0
Output mode
-
N/A
Input mode
Output mode
N/A
Input mode
Output mode
N/A
N/A
Input mode
Output mode
N/A
N/A
Input mode
Output mode
-
-
Segment
-
-
-
LCD segment
output
output
selection
Reset signal generation sets port 0 to input mode.
Figures 4-17 to 4-20 show block diagrams of port 4.
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Figure 4-17. Block Diagram of P40
EVDD
WRPU
PU4
PU40
P-ch
Alternate
function
Selector
WRPORT
P4
Output latch
(P40)
WRPM
PM4
Selector
Internal bus
RD
P40/TOOL0
PM40
Alternate
function
(TOOL0)
P4:
PU4:
PM4:
RD:
WRxx:
Port register 4
Pull-up resistor option register 4
Port mode register 4
Read signal
Write signal
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Figure 4-18. Block Diagram of P41-P44
EVDD
WRPU
PU4
PU41 to PU44
P-ch
Alternate
function
Selector
RD
WRPORT
Internal bus
P4
WRPM
PM4
PM41 to PM44
Selector
Output latch
(P41 to P44)
P41/STOPST/
TI04/TO04,
P42/TI10/TO10/
SEG7,
P43/TI22/TO22/
SEG14,
P44/TI23/TO23/
SEG15
Alternate
function
(STOPST,
TO04, TO10,
TO22, TO23 )
LCD controller/driver
WRLCDPF
LCDPF4
PF42 to PF44
P4:
PU4:
PM4:
LCDPF4:
RD:
WRxx:
Caution
Port register 4
Pull-up resistor option register 4
Port mode register 4
LCD port function registers 4
Read signal
Write signal
When using the alternate function TO04, TO10, TO22, TO23, set the port latch to 0.
When using P41 to P44 as a general-purpose port, specify the port settings so that the alternate
function outputs are fixed to 0.
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Figure 4-19. Block Diagram of P45
EVDD
WRPU
PU4
PU45
P-ch
Alternate
function
Selector
RD
WRPORT
Internal bus
P4
WRPM
PM4
PM45
Selector
Output latch
(P45)
P45/SEG53
LCD controller/driver
WRLCDPF
LCDPF4
PF45
P4:
PU4:
PM4:
LCDPF4:
RD:
WRxx:
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Pull-up resistor option register 4
Port mode register 4
LCD port function registers 4
Read signal
Write signal
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Figure 4-20. Block Diagram of P46, P47
EVDD
WRPU
PU4
PU46, PU47
P-ch
RD
WRPORT
P4
Output latch
(P46, P47)
WRPM
P46/DBWR/SEG27,
P47/DBRD/SEG26
PM4
PM46, PM47
Alternate
function
(DBWR, DBRD)
LCD controller/driver
WRLCDPF
LCDPF4
PF46 PF47
P4:
PU4:
PM4:
LCDPF4:
RD:
WRxx:
Port register 4
Pull-up resistor option register 4
Port mode register 4
LCD port function registers 4
Read signal
Write signal
___________
Caution
__________
When using the alternate function DBWR or DBRD, set the port latch to 1.
When using P46 or P47 as a general-purpose port, specify the port settings so that the alternate
function outputs are fixed to 1.
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4.2.6 Port 5
48-pin products:
P54 to P57 function as a 4-bit I/O port.
64-pin products:
P54 to P57 function as a 4-bit I/O port.
80-pin products:
P54 to P57 function as a 4-bit I/O port.
100-pin products:
P50 to P57 function as an 8-bit I/O port.
128-pin products:
P50 to P57 function as an 8-bit I/O port.
Port 5 is an 8-bit or a 4-bit I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units
using port mode register 5 (PM5). When the P50 to P57 pins are used as an input port, use of an on-chip pull-up resistor
can be specified in 1-bit units by pull-up resistor option register 5 (PU5).
Input to the P50 to P52 and P55 to P57 pins can be specified through a normal Schmitt3 input buffer or a Schmitt1
input buffer using port input mode register 5 (PIM5).
Output from the P50 pin can be specified as normal CMOS output or N-ch open-drain output (VDD tolerance), using
port output mode register (POM).
These pins also function as timer I/O, serial interface data I/O, and segment signal outputs for the LCD controller/driver.
To use P50 to P57 as the port function, refer Table 4-7.
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Table 4-7. Setting of P50 to P57 Pins to port function
P50 to P57 Pins
port
P50
function
Input port
LCDPF5
Alternate function
Register
Digital I/O
Timer
Serial
-
-
PM5
PIM5
POM
Register
Register
Register
Input mode
selection
Output port
P51
Input port
0
Digital I/O
1
-
Output mode
-
Input mode
selection
Output port
P52
Input port
Digital I/O
-
1
Output mode
N/A
Input mode
selection
P53
P54
P55
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
0
1
0
-
Input mode
Output port
Input port
-
Input mode
1
Output mode
N/A
Input mode
0
Input port
-
Input mode
Digital I/O
-
1
Output mode
N/A
Input mode
selection
-
-
N/A
Schmitt1 input
Schmitt3 input
0
N/A
Schmitt1 input
Schmitt3 input
N/A
N/A
N/A
N/A
0
N/A
Schmitt1 input
Schmitt3 input
0
N/A
Schmitt1 input
Schmitt3 input
0
N/A
Schmitt1 input
1
0
LCD
N-ch OD output
1
0
Output port
1
-
Output mode
-
selection
P57
CMOS output
1
Digital I/O
Output port
0
0
Output mode
selection
P56
-
Output mode
-
Output mode
-
Schmitt1 input
Schmitt3 input
1
0
Input port
-
1
0
Output port
0
1
Remarks
-
-
Schmitt3 input
-
-
LCD segment output
Segment
output
selection
Reset signal generation sets port 5 to input mode.
Figures 4-21 to 4-24 show block diagrams of port5.
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Figure 4-21. Block Diagram of P50
EVDD
WRPU
PU5
PU50
WRPIM
P-ch
PIM5
PIM50
Alternate
function
Schmitt1
Selector
RD
Schmitt3
WRPORT
Output latch
(P50)
WRPM
PM5
PM50
Selector
Internal bus
P5
P50/TI02/TO02/
SDA11/SEG49
Alternate
function
(TO02)
WRPOM
POM
POM_5
Alternate
function
(SDA11)
LCD controller/driver
WRLCDPF
LCDPF5
PF50
P5:
PU5:
PM5:
PIM5:
LCDPF5:
POM:
RD:
WRxx:
Caution
Port register 5
Pull-up resistor option register 5
Port mode register 5
Port Input mode register 5
LCD port function registers 5
Port Output mode register
Read signal
Write signal
When using the alternate function TO02, set the port latch to 0.
When using the alternate function SDA11, set the port latch to 1.
When using P50 as a general-purpose port, specify the port settings so that the alternate function
outputs are fixed (Timer to 0 and Serial to 1).
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Figure 4-22. Block Diagram of P51, P56
EVDD
WRPU
PU5
PU51, PU56
P-ch
WRPIM
PIM5
PIM51, PIM56
Alternate
function
Schmitt1
Schmitt3
WRPORT
P5
Output latch
(P51, P56)
WRPM
PM5
PM51, PM56
Selector
Internal bus
Selector
RD
P51/TI04/TO04/
SCK10/SEG50,
P56/TI16/TO16/
SCK01/SEG4
Alternate
function
(TO04, TO16)
Alternate
function
(SCK10, SCK01)
LCD controller/driver
WRLCDPF
LCDPF5
PF51, PF56
P5:
PU5:
PM5:
PIM5:
LCDPF5:
RD:
WRxx:
Caution
Port register 5
Pull-up resistor option register 5
Port mode register 5
Port Input mode register 5
LCD port function registers 5
Read signal
Write signal
When using the alternate function TO04 or TO16 , set the port latch to 0.
When using the alternate function SCK10 or SCK01, set the port latch to 1.
When using P51 or P56 as a general-purpose port, specify the port settings so that the alternate
function outputs are fixed (Timer to 0 and Serial to 1).
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Figure 4-23. Block Diagram of P52, P55, P57
EVDD
WRPU
PU5
PU52, PU55, PU57
P-ch
WRPIM
PIM5
PIM52, PIM55,
PIM57
Alternate
function
Schmitt1
Schmitt3
WRPORT
P5
Output latch
(P52, P55, P57)
WRPM
PM5
PM52, PM55, PM57
Selector
Internal bus
Selector
RD
P52/TI06/TO06/
SI10/SEG51,
P55/TI15/TO15/
SI01/SEG3,
P57/TI17/TO17/
SEG5
Alternate
function
(TO06, TO15,
TO17)
LCD controller/driver
WRLCDPF
LCDPF5
PF52, PF55, PF57
P5:
PU5:
PM5:
PIM5:
LCDPF5:
RD:
WRxx:
Port register 5
Pull-up resistor option register 5
Port mode register 5
Port Input mode register 5
LCD port function registers 5
Read signal
Write signal
Caution
When using the alternate function TO06, TO15, or TO17, set the port latch to 0.
When using P52, P55, or P57 as a general-purpose port, specify the port settings so that the alternate
function output is fixed to 0.
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Figure 4-24. Block Diagram of P53, P54
EVDD
WRPU
PU5
PU53, PU54
P-ch
Alternate
function
Selector
RD
WRPORT
Internal bus
P5
WRPM
PM5
PM53, PM54
Selector
Output latch
(P53, P54)
P53/TI13/TO13/
SO10/SEG52,
P54/TI14/TO14/
SO01/SEG2
Alternate
function
(TO13, TO14)
Alternate
function
(SO10, SO01)
LCD controller/driver
WRLCDPF
LCDPF5
PF53, PF54
P5:
PU5:
PM5:
LCDPF5:
RD:
WRxx:
Caution
Port register 5
Pull-up resistor option register 5
Port mode register 5
LCD port function registers 5
Read signal
Write signal
When using the alternate function TO13 or TO14 , set the port latch to 0.
When using the alternate function SO10 or SO01, set the port latch to 1.
When using P53 or P54 as a general-purpose port, specify the port settings so that the alternate
function outputs are fixed (Timer to 0 and Serial to 1).
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4.2.7 Port 6
48-pin products:
P60 and P61 function as a 2-bit I/O port.
64-pin products:
P60 and P61 function as a 2-bit I/O port.
80-pin products:
P60, 61, 65, and P66 function as a 4-bit I/O port.
100-pin products:
P60 to P66 function as a 7-bit I/O port.
128-pin products:
P60 to P66 function as a 7-bit I/O port.
Port 6 is a 7-bit, a 4-bit, or 2-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit
units using port mode register 6 (PM6). When the P60 to P66 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 6 (PU6).
Input to the P61 and P63 pins can be specified through a normal Schmitt3 input buffer or a Schmitt1 input buffer using
port input mode register 5 (PIM5).
Output from the P60 and P61 pins can be specified as normal CMOS output or N-ch open-drain output (VDD tolerance),
using port output mode register (POM).
These pins also function as serial interface data I/O, timer I/O, real-time clock correction clock output, clock / buzzer
output, and external interrupt request input.
To use P60 to P66 as the port function, refer Table 4-8.
Table 4-8. Setting of P60 to P66 Pins to port function
P60 to P66 Pins
port
P60
function
Input port
Output port
P61
Alternate function
Timer
Serial
-
-
0
Input port
1
-
PM6
PIM6
POM
Register
Register
Register
Input mode
N/A
-
Output mode
-
Input mode
0
CMOS output
1
N-ch OD output
0
-
1
Output port
P62
Input port
Output port
P63
0
1
0
Input port
-
Output mode
-
Input mode
1
Output mode
N/A
Input mode
P64
Input port
Output port
P65
0
CMOS output
1
N-ch OD output
N/A
N/A
0
N/A
-
N/A
Input mode
Schmitt1 input
Schmitt3 input
N/A
N/A
N/A
N/A
N/A
N/A
Output mode
-
N/A
0
Input port
Output port
Output mode
0
Input port
Output port
P66
0
Schmitt1 input
Schmitt3 input
-
1
Output port
Remarks
Input mode
Output mode
-
N/A
0
Input mode
Output mode
Reset signal generation sets port 6 to input mode.
Figures 4-25 to 4-30 show block diagrams of port6.
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Figure 4-25. Block Diagram of P60
EVDD
WRPU
PU6
PU60
P-ch
Alternate
function
Selector
RD
WRPORT
Internal bus
P6
Output latch
(P60)
WRPM
PM6
P60/SCL11/TI20/
TO20/INTP1
PM60
Alternate
function
(TO20)
WRPOM
POM
POM_0
Alternate
function
(SCL11)
P6:
PU6:
PM6:
POM:
RD:
WRxx:
Caution
Port register 6
Pull-up resistor option register 6
Port mode register 6
Port Output mode register
Read signal
Write signal
When using the alternate function TO20, set the port latch to 0.
When using the alternate function SCL11, set the port latch to 1.
When using P60 as a general-purpose port, specify the port settings so that the alternate function
outputs are fixed (Timer to 0 and Serial to 1).
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Figure 4-26. Block Diagram of P61
EVDD
WRPU
PU6
PU61
WRPIM
P-ch
PIM6
PIM61
Alternate
function
Schmitt1
Internal bus
Selector
RD
Schmitt3
WRPORT
P6
Output latch
(P61)
WRPM
PM6
P61/SDA11/TI21/
TO21/INTP3
PM61
Alternate
function
(TO21)
WRPOM
POM
POM_1
Alternate
function
(SDA11)
P6:
PU6:
PM6:
PIM6:
POM:
RD:
WRxx:
Caution
Port register 6
Pull-up resistor option register 6
Port mode register 6
Port Input mode register 6
Port Output mode register
Read signal
Write signal
When using the alternate function T TO21, set the port latch to 0.
When using the alternate function SDA11, set the port latch to 1.
When using P61 as a general-purpose port, specify the port settings so that the alternate function
outputs are fixed (Timer to 0 and Serial to 1).
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Figure 4-27. Block Diagram of P62
EVDD
WRPU
PU6
PU62
P-ch
Alternate
function
Selector
RD
WRPORT
Internal bus
P6
Output latch
(P62)
P62/CTxD1/
TI27/TO27
WRPM
PM6
PM62
Alternate
function
(TO27)
Alternate
function
(CTxD1)
P6:
PU6:
PM6:
RD:
WRxx:
Caution
Port register 6
Pull-up resistor option register 6
Port mode register 6
Read signal
Write signal
When using the alternate function TO27, set the port latch to 0.
When using the alternate function CTxD1, set the port latch to 1.
When using P62 as a general-purpose port, specify the port settings so that the alternate function
outputs are fixed (Timer to 0 and Serial to 1).
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Figure 4-28. Block Diagram of P63
EVDD
WRPU
PU6
PU63
P-ch
WRPIM
PIM6
PIM63
Alternate
function
Schmitt1
Selector
Internal bus
RD
Schmitt3
WRPORT
P6
Output latch
(P63)
P63/CRxD1/
TI26/TO26
WRPM
PM6
PM63
Alternate
function
(TO26)
P6:
PU6:
PM6:
PIM6:
RD:
WRxx:
Caution
Port register 6
Pull-up resistor option register 6
Port mode register 6
Port Input mode register 6
Read signal
Write signal
When using the alternate function TO26, set the port latch to 0.
When using P63 as a general-purpose port, specify the port settings so that the alternate function
output is fixed to 0.
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Figure 4-29. Block Diagram of P64, P66
EVDD
WRPU
PU6
PU64, P66
P-ch
Alternate
function
Internal bus
Selector
RD
WRPORT
P6
Output latch
(P64, P66)
P64/RTC1HZ/
TI11/TO11,
P66/TI24/TO24/
PCL
WRPM
PM6
PM64, PM66
Alternate
function
(RTC1HZ, TO24)
Alternate
function
(TO11, PCL)
P6:
PU6:
PM6:
RD:
WRxx:
Caution
Port register 6
Pull-up resistor option register 6
Port mode register 6
Read signal
Write signal
When using the alternate function RTC1HZ, TO24, TO11, or PCL, set the port latch to 0.
When using P64 or P66 as a general-purpose port, specify the port settings so that the alternate
function output is fixed to 0.
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Figure 4-30. Block Diagram of P65
EVDD
WRPU
PU6
PU65
P-ch
Alternate
function
Internal bus
Selector
RD
WRPORT
P6
Output latch
(P65)
P65/TI25/TO25
WRPM
PM6
PM65
Alternate
function
(TO25)
P6:
PU6:
PM6:
RD:
WRxx:
Caution
Port register 6
Pull-up resistor option register 6
Port mode register 6
Read signal
Write signal
When using the alternate function TO25, set the port latch to 0.
When using P65 as a general-purpose port, specify the port settings so that the alternate function
output is fixed to 0.
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4.2.8 Port 7
Port 7 is a 6-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port
mode register 7 (PM7). When the P70 to P75 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 7 (PU7).
Input to the P70 pin can be specified through a normal Schmitt3 input buffer or a Schmitt1 input buffer using port input
mode register 7 (PIM7).
These pins also function as A/D conversion start trigger input, output pins for the sound generator, serial interface data
I/O, timer I/O, clock / buzzer output, flash memory programming I/O, external interrupt request input, and segment signal
outputs for the LCD controller/driver.
To use P70 to P75 as the port function, refer Table 4-9.
Table 4-9. Setting of P70 to P75 Pins to port function
P70 to P75 Pins
port
function
LCDPF7
Alternate function
Register
Timer/
Serial
PM7
PIM7
POM
Register
Register
Register
Remarks
SGO
P70
Input port
N/A
-
N/A
Input mode
0
N/A
Schmitt1 input
1
Output port
P71
Input port
0
N/A
Output mode
N/A
-
Output port
P72
P73
P74
P75
-
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
-
LCD
-
1
Output mode
N/A
Input mode
0
-
Input mode
N/A
0
Schmitt3 input
-
N/A
N/A
N/A
Output mode
-
Input mode
-
N/A
Output mode
-
0
-
-
Input mode
1
Output mode
N/A
Input mode
0
N/A
N/A
-
N/A
Output mode
-
-
-
-
-
LCD segment output
Segment
output
selection
Reset signal generation sets port 7 to input mode.
Figures 4-31 to 4-35 show block diagrams of port 7.
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Figure 4-31. Block Diagram of P70
EVDD
WRPU
PU7
PU70
P-ch
WRPIM
PIM7
PIM70
Alternate
function
Schmitt1
RD
Schmitt3
WRPORT
P7
Output latch
(P70)
WRPM
P70/CRxD0/
LRxD0/INTPLR0/
TI03/TO03/
TOOLRxD
PM7
PM70
Alternate
function
(TO03)
P7:
PU7:
PM7:
PIM7:
RD:
WRxx:
Caution
Port register 7
Pull-up resistor option register 7
Port mode register 7
Port Input mode register 7
Read signal
Write signal
When using the alternate function TO03, set the port latch to 0.
When using P70 as a general-purpose port, specify the port settings so that the alternate function
output is fixed to 0.
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Figure 4-32. Block Diagram of P71
EVDD
WRPU
PU7
PU71
P-ch
Alternate
function
Internal bus
Selector
RD
WRPORT
P7
Output latch
(P71)
P71/CTxD0/
LTxD0/TOOLTxD
WRPM
PM7
PM71
Alternate
function
(CTxD0, LTxD0,
TOOLTxD)
P7:
PU7:
PM7:
RD:
WRxx:
Caution
Port register 7
Pull-up resistor option register 7
Port mode register 7
Read signal
Write signal
When using the alternate function CTxD0, LTxD0, TOOLTxD, set the port latch to1.
When using P71 as a general-purpose port, specify the port settings so that the alternate function
outputs are fixed to 1.
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Figure 4-33. Block Diagram of P72, P73
EVDD
WRPU
PU7
PU72, PU73
P-ch
Alternate
function
Selector
RD
WRPORT
Internal bus
P7
WRPM
PM7
PM72, PM73
Selector
Output latch
(P72, P73)
P72/ADTRG/
SGOA/SEG1,
P73/SGO/SGOF/
SEG0
Alternate
function
(SGOA, SGO/SGOF)
LCD controller/driver
WRLCDPF
LCDPF7
PF72, PF73
P7:
PU7:
PM7:
LCDPF7:
RD:
WRxx:
Caution
Port register 7
Pull-up resistor option register 7
Port mode register 7
LCD port function registers 7
Read signal
Write signal
When using the alternate function SGOA, SGO/SGOF, or TO22, set the port latch to 0.
When using P72 or P73 as a general-purpose port, specify the port settings so that the alternate
function output is fixed to 0.
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Figure 4-34. Block Diagram of P74
EVDD
WRPU
PU7
PU74
P-ch
Alternate
function
Selector
RD
WRPORT
Internal bus
P7
WRPM
PM7
PM74
Selector
Output latch
(P74)
P74/SCK01/
TI23/TO23/
SEG26
Alternate
function
(TO23)
Alternate
function
(SCK01)
LCD controller/driver
WRLCDPF
LCDPF7
PF74
P7:
PU7:
PM7:
LCDPF7:
RD:
WRxx:
Caution
Port register 7
Pull-up resistor option register 7
Port mode register 7
LCD port function registers 7
Read signal
Write signal
When using the alternate function TO23, set the port latch to 0.
When using the alternate function SCK01, set the port latch to 1.
When using P74 as a general-purpose port, specify the port settings so that the alternate function
outputs are fixed (Timer to 0 and Serial to 1).
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Figure 4-35. Block Diagram of P75
EVDD
WRPU
PU7
PU75
P-ch
Alternate
function
Selector
RD
WRPORT
Internal bus
P7
WRPM
PM7
PM75
Selector
Output latch
(P75)
P75/PCL/SI01/
TI22/TO22/SEG21
Alternate
function
(PCL)
Alternate
function
(TO22)
LCD controller/driver
WRLCDPF
LCDPF7
PF75
P7:
PU7:
PM7:
LCDPF7:
RD:
WRxx:
Caution
Port register 7
Pull-up resistor option register 7
Port mode register 7
LCD port function registers 7
Read signal
Write signal
When using the alternate function PCL or TO22, set the port latch to 0.
When using P75 as a general-purpose port, specify the port settings so that the alternate function
outputs are fixed 0.
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4.2.9 Port 8
Port 8 is an 8-bit I/O port with an output latch and LED direct drive capability. Port 8 can be set to the input mode or
output mode in 1-bit units using port mode register 8 (PM8). When the P80 to P87 pins are used as an input port, use
of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 8(PU8)
These pins also function as timer I/O, stepper motor controller/driver outputs/inputs, and segment signal outputs for
the LCD controller/driver.
To use P80 to P87 as the port function, refer Table 4-10.
Table 4-10. Setting of P80 to P87 Pins to port function
P80 to P87 Pins
port
P80
P81
P82
P83
P84
P85
P86
P87
-
function
LCDPF8
Register
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
-
LCD
Alternate function
Timer
-
Serial
N/A
0
ZPDS0
Register
Register
Port mode
-
N/A
0
N/A
0
-
N/A
-
N/A
0
-
N/A
0
-
N/A
0
-
N/A
0
-
-
Output mode
ZPD1PC=0
Input mode
Output mode
N/A
Input mode
Note1
Output mode
N/A
Input mode
Note2
Output mode
N/A
Input mode
Note3
Port mode
Input mode
Note4
Port mode
Output mode
N/A
Port mode
Input mode
Note3
Port mode
Output mode
N/A
Port mode
Remarks
Register
Input mode
Note2
Port mode
0
N/A
Note1
Port mode
-
PM8
SMPC
Output mode
ZPD2PC=0
Note4
Input mode
Output mode
-
-
LCD
Segment
segment
output
output
selection
Note1. ENk = 0 or (ENk, MODk, DIRk1, DIRk0)=1110 or 1111
2. ENk = 0 or (ENk, MODk, DIRk1, DIRk0)=1100 or 1101
3. ENk = 0 or (ENk, MODk, DIRk1, DIRk0)=1101 or 1110
4. ENk = 0 or (ENk, MODk, DIRk1, DIRk0)=1100 or 1111
(k = 0, 1)
Reset signal generation sets port 8 to input mode.
Figure 4-36 and 4-37 show block diagrams of port 8.
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Figure 4-36. Block Diagram of P80 to P82 and P84 to P86
SMVDD
WRPU
PU8
PU80 to PU82,
PU84 to PU86
P-ch
Alternate
function
Selector
RD
WRPORT
WRPM
PM8
PM80 to PM82,
PM84 to PM86
Alternate
function
(SM11 to SM13,
SM21 to SM23)
Selector
Internal bus
P8
Output latch
(P80 to P82,
P84 to P86)
P80/SM11/TI01/
TO01/SEG32,
P81/SM12/TI03/
TO03/SEG33,
P82/SM13/TI05/
TO05/SEG34,
P84/SM21/TI11/
TO11/SEG36,
P85/SM22/TI13/
TO13/SEG37,
P86/SM23/TI15/
TO15/SEG38
Alternate
function
(TO01, TO03, TO05,
TO11, TO13, TO15)
LCD controller/driver
WRLCDPF
LCDPF8
PF80 to PF82,
PF84 to PF86
P8:
PU8:
PM8:
LCDPF8:
RD:
WRxx:
Caution
Port register 8
Pull-up resistor option register 8
Port mode register 8
LCD port function registers 8
Read signal
Write signal
When using the alternate function SM11 to SM13, SM21 to SM23, TO01, TO03, TO05, TO11, TO13, or
TO15, set the port latch to 0.
When using P80 to P82 or P84 to P86 as a general-purpose port, specify the port settings so that the
alternate function outputs are fixed 0.
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Figure 4-37. Block Diagram of P83, P87
SMVDD
WRPU
PU8
PU83, PU87
P-ch
Alternate
function
Selector
RD
WRPORT
Output latch
(P83, P87)
WRPM
PM8
PM83, PM87
Selector
Internal bus
P8
P83/SM14/ZPD14/
TI07/TO07/SEG35,
P87/SM24/ZPD24/
TI17/TO17/SEG39
Alternate
function
(SM14, SM24)
Alternate
function
(TO07, TO17)
WR ZPDS
ZPDS0
ZPD1PC, ZPD2PC
WRLCDPF
LCD controller/driver
LCDPF8
PF83, PF87
ZPD comparator
P8:
PU8:
PM8:
LCDPF8:
ZPDS0:
RD:
WRxx:
Caution
Port register 8
Pull-up resistor option register 8
Port mode register 8
LCD port function registers 8
ZPD detection voltage setting register0/ZPD analog input control register
Read signal
Write signal
When using the alternate function SM14, SM18, TO07, or TO17 set the port latch to 0.
When using P83 or P87 as a general-purpose port, specify the port settings so that the alternate
function outputs are fixed 0.
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4.2.10 Port 9
48-pin products:
P90 to P94 function as a 5-bit I/O port.
64-pin products:
P90 to P94 function as a 5-bit I/O port.
80-pin products:
P90 to P97 function as an 8-bit I/O port.
100-pin products:
P90 to P97 function as an 8-bit I/O port.
128-pin products:
P90 to P97 function as an 8-bit I/O port.
Port 9 is an 8-bit or a 5-bit I/O port with an output latch and LED direct drive capability. Port 9 can be set to the input
mode or output mode in 1-bit units using port mode register 9 (PM9). When the P90 to P97 pins are used as an input port,
use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 9(PU9)
These pins also function as timer I/O, stepper motor controller/driver outputs/inputs, and segment signal outputs for the
LCD controller/driver.
To use P90 to P97 as the port function, refer Table 4-11.
Table 4-11. Setting of P90 to P97 Pins to port function
P90 to P97 Pins
port
function
LCDPF9
Timer
Serial
/SGO
P90
P91
P92
P93
P94
P95
P96
P97
-
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
-
LCD segment
PM9
Alternate function
Register
-
N/A
0
SMPC
ZPDS1
Register
Register
Port mode
-
N/A
0
N/A
0
-
N/A
0
-
N/A
0
N/A
0
-
N/A
0
-
N/A
0
-
output selection
-
Output mode
ZPD3PC = 0
Input mode
Output mode
N/A
Input mode
Note1
Output mode
N/A
Input mode
Note2
Output mode
N/A
Input mode
Note3
Port mode
Input mode
Note4
Port mode
Output mode
N/A
Port mode
Input mode
Note3
Port mode
-
N/A
Port mode
Output mode
Note2
Port mode
Input mode
Note1
Port mode
-
N/A
Remarks
Register
Output mode
ZPD4PC = 0
Note4
Input mode
Output mode
-
-
LCD
segment
output
Note1. ENk = 0 or (ENk, MODk, DIRk1, DIRk0)=1110 or 1111
2. ENk = 0 or (ENk, MODk, DIRk1, DIRk0)=1100 or 1101
3. ENk = 0 or (ENk, MODk, DIRk1, DIRk0)=1101 or 1110
4. ENk = 0 or (ENk, MODk, DIRk1, DIRk0)=1100 or 1111
(k = 0, 1)
Reset signal generation sets port 9 to input mode.
Figures 4-38 to 4-41show block diagrams of port 9.
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Figure 4-38. Block Diagram of P90, P91, P95, and P96
SMVDD
WRPU
PU9
PU90, PU91,
PU95, PU96
P-ch
Alternate
function
Selector
RD
WRPORT
WRPM
PM9
PM90, PM91,
PM95, PM96
Alternate
function
(SM31, SM32,
SM42, SM43)
Selector
Internal bus
P9
Output latch
(P90, P91,
P95, P96)
P90/SM31/TI21/
TO21/SEG40,
P91/SM32/TI23/
TO23/SEG41,
P95/SM42/TI03/
TO03/SEG45,
P96/SM43/TI05/
TO05/SEG46
Alternate
function
(TO21, TO23,
TO03, TO05)
LCD controller/driver
WRLCDPF
LCDPF9
PF90, PF91,
PF95, PF96
P9:
PU9:
PM9:
LCDPF9:
RD:
WRxx:
Caution
Port register 9
Pull-up resistor option register 9
Port mode register 9
LCD port function registers 9
Read signal
Write signal
When using the alternate function SM31, SM32, SM42, SM43, TO21, TO23, TO03, or TO05, set the port
latch to 0.
When using P90, P91, P95, or P96 as a general-purpose port, specify the port settings so that the
alternate function outputs are fixed 0.
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Figure 4-39. Block Diagram of P92, P94
SMVDD
WRPU
PU9
PU92, PU94
P-ch
Alternate
function
Selector
RD
P9
Output latch
(P92, P94)
WRPM
PM9
PM92, PM94
Alternate
function
(SM33, SM41)
Selector
Internal bus
WRPORT
P92/SM33/TI25/
TO25/SGOA/
SEG42,
P94/SM41/TI01/
TO01/RTC1HZ/
SEG44
Alternate
function
(TO25, TO01)
Alternate
function
(SGOA, RTC1HZ)
LCD controller/driver
WRLCDPF
LCDPF9
PF92, PF94
P9:
PU9:
PM9:
LCDPF9:
RD:
WRxx:
Caution
Port register 9
Pull-up resistor option register 9
Port mode register 9
LCD port function registers 9
Read signal
Write signal
When using the alternate function SM33, SM41, TO25, TO01, SGOA, or RTC1HZ, set the port latch to
0.
When using P92 or P94 as a general-purpose port, specify the port settings so that the alternate
function outputs are fixed 0.
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Figure 4-40. Block Diagram of P93
SMVDD
WRPU
PU9
PU93
P-ch
Alternate
function
Selector
RD
WRPORT
P9
WRPM
PM9
PM93
Selector
Internal bus
Output latch
(P93)
P93/SM34/ZPD34/
TI27/TO27/
SGO/SGOF/
SEG43
Alternate
function
(SM34)
Alternate
function
(TO27)
Alternate
function
(SGO/SGOF)
WR ZPDS
ZPDS1
ZPD3PC
WRLCDPF
LCD controller/driver
LCDPF9
PF93
ZPD comparator
P9:
PU9:
PM9:
LCDPF9:
ZPDS1:
RD:
WRxx:
Caution
Port register 9
Pull-up resistor option register 9
Port mode register 9
LCD port function registers 9
ZPD detection voltage setting register1/ZPD analog input control register
Read signal
Write signal
When using the alternate function SM34, TO27 or SGO/SGOF, set the port latch to 0.
When using P93 as a general-purpose port, specify the port settings so that the alternate function
outputs are fixed 0.
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Figure 4-41. Block Diagram of P97
SMVDD
WRPU
PU9
PU97
P-ch
Alternate
function
Selector
RD
WRPORT
Output latch
(P97)
WRPM
PM9
PM97
Selector
Internal bus
P9
P97/SM44/ZPD44/
TI07/TO07/SEG47
Alternate
function
(SM44)
Alternate
function
(TO07)
WR ZPDS
ZPDS1
ZPD4PC
WRLCDPF
LCD controller/driver
LCDPF9
PF97
ZPD comparator
P9:
PU9:
PM9:
LCDPF9:
ZPDS1:
RD:
WRxx:
Caution
Port register 9
Pull-up resistor option register 9
Port mode register 9
LCD port function registers 9
ZPD detection voltage setting register1/ZPD analog input control register
Read signal
Write signal
When using the alternate function SM44 or TO07 set the port latch to 0.
When using P97 as a general-purpose port, specify the port settings so that the alternate function
outputs are fixed 0.
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4.2.11 Port 10
48-pin products:
Not provided
64-pin products:
Not provided
80-pin products:
Not provided
100-pin products:
Not provided
128-pin products:
P100 to P107 function as an 8-bit I/O port.
Port 10 is an 8-bit I/O port with an output latch. Port 10 can be set to the input mode or output mode in 1-bit units using
port mode register 10 (PM10). When the P100 to P107 pins are used as an input port, use of an on-chip pull-up resistor
can be specified in 1-bit units by pull-up resistor option register 10(PU10)
These pins also function as timer I/O and segment signal outputs for the LCD controller/driver.
To use P100 to P107 as the port function, refer Table 4-12.
Table 4-12. Setting of P100 to P107 Pins to port function
P100 to P107 Pins
port
P100
P101
P102
P103
P104
P105
P106
P107
-
function
LCDPF10
Register
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
-
Alternate function
LCD
Timer
-
Serial
N/A
PM10
PIM10
POM
Register
Register
Register
Input mode
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Remarks
Output mode
-
N/A
Input mode
0
Output mode
-
N/A
Input mode
0
Output mode
-
N/A
Input mode
0
Output mode
-
N/A
Input mode
0
Output mode
-
N/A
Input mode
0
Output mode
-
N/A
Input mode
0
Output mode
-
N/A
Input mode
0
Output mode
-
-
-
-
-
LCD segment output
Segment
output
selection
Reset signal generation sets port 10 to input mode.
Figure 4-42 shows a block diagram of port 10.
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Figure 4-42. Block Diagram of P100 to P107
EVDD
WRPU
PU10
PU100 to PU107
P-ch
Alternate
function
Selector
RD
WRPORT
Internal bus
P10
WRPM
PM10
PM100 to PM107
Selector
Output latch
(P100 to P107)
P100/TI24/TO24/
SEG36 to
P103/TI27/TO27/
SEG39,
P104/TI01/TO01/
SEG44 to
P107/TI06/TO06/
SEG47
Alternate
function
(TO01 to TO06,
TO24 to TO27)
LCD controller/driver
WRLCDPF
LCDPF10
PF100 to PF107
P10:
PU10:
PM10:
LCDPF10:
RD:
WRxx:
Caution
Port register 10
Pull-up resistor option register 10
Port mode register 10
LCD port function registers 10
Read signal
Write signal
When using the alternate function TO01, TO02, TO05, TO06, or TO24 to TO27, set the port latch to 0.
When using P100 to P107 as general-purpose ports, specify the port settings so that the alternate
function output is fixed 0.
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4.2.12 Port 11
48-pin products:
Not provided
64-pin products:
Not provided
80-pin products:
Not provided
100-pin products:
Not provided
128-pin products:
P110 to P117 function as an 8-bit I/O port.
Port 11 is an 8-bit I/O port with an output latch. Port 11 can be set to the input mode or output mode in 1-bit units using
port mode register 11 (PM11). When the P110 to P117 pins are used as an input port, use of an on-chip pull-up resistor
can be specified in 1-bit units by pull-up resistor option register 11(PU11)
Input to the P110 to P117 pins can be specified through a normal Schmitt3 input buffer or a Schmitt1 input buffer, using
port input mode register 11 (PIM11).
These pins also function as timer I/O, serial interface data I/O, clock I/O, LCD bus interface data I/O, and segment
signal outputs for the LCD controller/driver.
To use P110 to P117 as the port function, refer Table 4-13.
Table 4-13. Setting of P110 to P117 Pins to port function
P110 to P117 Pins
port
P110
P111
P112
P113
P114
P115
P116
P117
-
function
LCDPF11
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
-
Alternate function
Register
LCD
Timer
Serial
0
-
-
0
Output mode
1
N/A
Input mode
0
Output mode
1
Input mode
0
1
Output mode
1
N/A
Input mode
0
Output mode
1
Input mode
0
Output mode
1
Input mode
0
Output mode
1
Input mode
0
Output mode
1
Input mode
0
Output mode
1
-
0
-
N/A
0
-
N/A
0
-
N/A
0
-
POM
Register
Input mode
-
-
PIM11
Register
1
0
0
PM11
Register
N/A
0
-
-
-
N/A
Remarks
Schmitt1 input
Schmitt3 input
N/A
Schmitt1 input
Schmitt3 input
N/A
Schmitt1 input
Schmitt3 input
N/A
Schmitt1 input
Schmitt3 input
N/A
Schmitt1 input
Schmitt3 input
N/A
Schmitt1 input
Schmitt3 input
N/A
Schmitt1 input
Schmitt3 input
N/A
Schmitt1 input
Schmitt3 input
-
-
LCD segment output
Segment
output
selection
Reset signal generation sets port 11 to input mode.
Figures 4-43 and 4-44 show block diagrams of port 11.
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Figure 4-43. Block Diagram of P110 and P112
EVDD
WRPU
PU11
PU110, PU112
P-ch
WRPIM
PIM11
PIM110, PIM112
Alternate
function
Schmitt1
Schmitt3
WRPORT
P11
WRPM
PM11
PM110, PM112
Selector
Output latch
(P110, P112)
Selector
Internal bus
Selector
RD
Alternate
function
P110/DBD0/
SCK00/TI00/
TO00/SEG35,
P112/DBD2/SO00/
TxD0/TI04/TO04/
SEG33
(TO00, TO04)
Alternate
function
(SCK00, SO00)
LCD controller/driver
WRLCDPF
LCDPF11
PF110, PF112
LCD bus I/F
LCD bus I/F control signal
P11:
PU11:
PM11:
PIM11:
LCDPF11:
RD:
WRxx:
Caution
Port register 11
Pull-up resistor option register 11
Port mode register 11
Port Input mode register 11
LCD port function registers 11
Read signal
Write signal
When using the alternate function TO00 or TO04, set the port latch to 0.
When using the alternate function SCK00, SO00, or TxD0, set the port latch to 1.
When using the alternate function DBD0 or DBD2, set the port latch to 0 and the port mode register
to 1 (input mode).
When using P110 or P112 as a general-purpose port, specify the port settings so that the alternate
function output is fixed (Timer to 0 and Serial to 1).
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Figure 4-44. Block Diagram of P111, P113 to P117
EVDD
WRPU
PU11
PU111,
PU113 to PU117
P-ch
WRPIM
PIM11
PIM111,
PIM113 to PIM117
Alternate
function
Schmitt1
Schmitt3
WRPORT
WRPM
PM11
PM111,
PM113 to PM117
Alternate
function
(TO02, TO06, TO07,
TO10, TO12, TO20)
Selector
P11
Output latch
(P111,
P113 to P117)
Selector
Internal bus
Selector
RD
P111/DBD1/SI00/
RxD0/TI02/TO02/
SEG34,
P113/DBD3/TI06/
TO06/SEG32,
P114/DBD4/TI07/
TO07/SEG31,
P115/DBD5/TI10/
TO10/SEG30,
P116/DBD6/TI12/
TO12/SEG29,
P117/DBD7/TI20/
TO20/SEG28
LCD controller/driver
WRLCDPF
LCDPF11
PF111,
PF113 to PF117
LCD bus I/F
LCD bus I/F control signal
P11:
PU11:
PM11:
PIM11:
LCDPF11:
RD:
WRxx:
Caution
Port register 11
Pull-up resistor option register 11
Port mode register 11
Port Input mode register 11
LCD port function registers 11
Read signal
Write signal
When using the alternate function TO02, TO06, TO07, TO10, TO12 or TO20, set the port latch to 0.
When using the alternate function DBD1 or DBD3 to DBD7, set the port latch to 0 and the port mode
register to 1 (input mode).
When using P111 or P113 to P117 as a general-purpose port, specify the port settings so that the
alternate function output is fixed 0.
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4.2.13 Port 12
48-pin products:
P121 to P124 function as a 4-bit Input port.
64-pin products:
P121 to P124 function as a 4-bit Input port.
80-pin products:
P121 to P124 function as a 4-bit Input port.
100-pin products:
P121 to P124 function as a 4-bit Input port.
128-pin products:
P121 to P124 function as a 4-bit Input port, P125 to P127 function as a 3-bit I/O port.
P121 to P124 is a 4-bit Input port.
P125 to P127 is a 3-bit I/O port with an output latch. P125 to P127 can be set to the input mode or output mode in 1-bit
units using port mode register 12 (PM12). When the P125 to P127 pins are used as an input port, use of an on-chip pullup resistor can be specified in 1-bit units by pull-up resistor option register 12 (PU12).
P121 to P124 pins also function as external clock input for main system clock, external clock input for subsystem clock.
P125 to P127 pins also function as timer I/O and segment signal outputs for the LCD controller/driver.
To use P121 to P127 as the port function, refer Table 4-14 and 4-15.
Table 4-14. Setting of P121 to P124 Pins to port function
P121 to P124 Pins
port
CMC Register
function
P121
EXCLK
Input port
Remarks
OSCSEL
-
OSCSELS
0
1
-
1
P122
Input port
-
0
-
P123
Input port
-
-
0
P124
Input port
-
-
0
Table 4-15. Setting of P125 to P127 Pins to port function
P125 to P127 Pins
port
P125
P126
P127
-
function
LCDPF12
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
Input port
Digital I/O
Output port
selection
-
Alternate function
Register
LCD
Timer
-
Serial
N/A
PM12
PIM12
POM
Register
Register
Register
Input mode
0
N/A
N/A
N/A
N/A
N/A
N/A
Remarks
Output mode
-
N/A
Input mode
0
Output mode
-
N/A
Input mode
0
Output mode
-
-
-
-
-
LCD segment output
Segment
output
selection
Reset signal generation sets port 12 to input mode.
Figure 4-45 and 4-47 show block diagrams of port 12.
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Figure 4-45. Block Diagram of P121, P122
Clock generator
CMC
OSCSEL
Internal bus
RD
P122/X2/EXCLK
CMC
EXCLK
RD
P121/X1
Figure 4-46. Block Diagram of P123, P124
Clock generator
CMC
OSCSELS
Internal bus
RD
P124/XT2
RD
P123/XT1
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Figure 4-47. Block Diagram of P125 to P127
EVDD
WRPU
PU12
PU125 to PU127
P-ch
Alternate
function
Selector
RD
WRPORT
Internal bus
P12
WRPM
PM12
PM125 to PM127
Selector
Output latch
(P125 to P127)
P125/TI12/TO12/
SEG25,
P126/TI14/TO14/
SEG24,
P127/TI16/TO16/
SEG23
Alternate
function
(TO12, TO14, TO16)
LCD controller/driver
WRLCDPF
LCDPF12
PF125 to PF127
P12:
PU12:
PM12:
LCDPF12:
RD:
WRxx:
Caution
Port register 12
Pull-up resistor option register 12
Port mode register 12
LCD port function registers 12
Read signal
Write signal
When using the alternate function TO12, TO14, or TO16, set the port latch to 0.
When using P125 to P127 as general-purpose ports, specify the port settings so that the alternate
function output is fixed 0.
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4.2.14 Port 13
48-pin products:
P137 functions as a 1-bit Input port.
64-pin products:
P137 functions as a 1-bit Input port.
80-pin products:
P137 functions as a 1-bit Input port.
100-pin products:
P130 functions as a 1-bit Output port, P131 to P136 function as a 6-bit I/O port, and P137
functions as a 1-bit Input port.
128-pin products:
P130 functions as a 1-bit Output port, P131 to P136 function as a 6-bit I/O port, and P137
functions as a 1-bit Input port.
P130 is a 1-bit output-only port with an output latch.
P131 to P136 is a 6-bit I/O port with an output latch. P131 to P136 can be set to the input mode or output mode in 1-bit
units using port mode register 13 (PM13). When the P131 to P136 pins are used as an input port, use of an on-chip pullup resistor can be specified in 1-bit units by pull-up resistor option register 13 (PU13).
P137 is a 1-bit input-only port.
Input to the P135 pin can be specified through a normal Schmitt3 input buffer or a Schmitt1 input buffer, using port
input mode register 13 (PIM13).
Output from the P136 pin can be specified as normal CMOS output or N-ch open-drain output (VDD tolerance), using
port output mode register (POM).
These pins also function as timer I/O, output pins for the sound generator, serial interface data I/O ,and segment signal
outputs for the LCD controller/driver.
To use P131 to P136 as the port function, refer Table 4-16.
Table 4-16. Setting of P131 to P136 Pins to port function
P131 to P136 Pins
port
P131
function
Input port
LCDPF13
Input port
Input port
N/A
Input port
N/A
Input port
P136
-
Digital I/O
Output port
selection
LCD
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Remarks
-
-
Input mode
Output mode
-
Input mode
1
Output mode
N/A
Input mode
0
Output mode
1
Input mode
N/A
0
Input port
-
Input mode
-
N/A
Input mode
N/A
1
0
Output port
POM
Register
Output mode
-
N/A
PIM13
Register
Output mode
0
Output port
P135
-
-
PM13
Register
1
0
Output port
P134
Serial
0
Output port
P133
Timer/SGO
N/A
Output port
P132
Alternate function
Register
N/A
0
Schmitt3 input
Output mode
-
-
-
Schmitt1 input
-
0
CMOS output
1
N-ch OD output
-
LCD
segment
segment
output
output
selection
Reset signal generation sets port 13 to input mode.
Figures 4-48 to 4-55 show block diagrams of port 13.
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Figure 4-48. Block Diagram of P130
Internal bus
RD
WRPORT
P13
Output latch
(P130)
P13:
RD:
WRxx:
Remark
P130
Port register 13
Read signal
Write signal
When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected,
the output signal of P130 can be dummy-output as the CPU reset signal.
RESET signal
P130
Set by software
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Figure 4-49. Block Diagram of P131
EVDD
WRPU
PU13
PU131
P-ch
Alternate
function
Selector
RD
WRPORT
Internal bus
P13
Output latch
(P131)
P131/SO10/
LTxD1/TI21/
TO21
WRPM
PM13
PM131
Alternate
function
(TO21)
Alternate
function
(SO10)
Alternate
function
(LTxD1)
P13:
PU13:
PM13:
RD:
WRxx:
Caution
Port register 13
Pull-up resistor option register 13
Port mode register 13
Read signal
Write signal
When using the alternate function TO21, set the port latch to 0.
When using the alternate function SO10 or LTxD1, set the port latch to 1.
When using P131 as a general-purpose port, specify the port settings so that the alternate function
outputs are fixed (Timer to 0 and Serial to 1).
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Figure 4-50. Block Diagram of P132
EVDD
WRPU
PU13
PU132
P-ch
Alternate
function
Internal bus
Selector
RD
WRPORT
P13
Output latch
(P132)
P132/SI10/LRxD1/
INTPLR1/TI20/
TO20
WRPM
PM13
PM132
Alternate
function
(TO20)
P13:
PU13:
PM13:
RD:
WRxx:
Caution
Port register 13
Pull-up resistor option register 13
Port mode register 13
Read signal
Write signal
When using the alternate function TO20, set the port latch to 0.
When using P132 as a general-purpose port, specify the port settings so that the alternate function
output is fixed to 0.
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Figure 4-51. Block Diagram of P133
EVDD
WRPU
PU13
PU133
P-ch
Alternate
function
Selector
RD
WRPORT
Internal bus
P13
Output latch
(P133)
P133/SCK10/
TI22/TO22
WRPM
PM13
PM133
Alternate
function
(TO22)
Alternate
function
(SCK10)
P13:
PU13:
PM13:
RD:
WRxx:
Caution
Port register 13
Pull-up resistor option register 13
Port mode register 13
Read signal
Write signal
When using the alternate function TO22, set the port latch to 0.
When using the alternate function SCK10, set the port latch to 1.
When using P133 as a general-purpose port, specify the port settings so that the alternate function
outputs are fixed (Timer to 0 and Serial to 1).
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Figure 4-52. Block Diagram of P134
EVDD
WRPU
PU13
PU134
P-ch
Alternate
function
Internal bus
Selector
RD
WRPORT
P13
Output latch
(P134)
P134/SGOA/
CTxD1/TI24/
TO24
WRPM
PM13
PM134
Alternate
function
(SGOA)
Alternate
function
(TO24)
Alternate
function
(CTxD1)
P13:
PU13:
PM13:
RD:
WRxx:
Caution
Port register 13
Pull-up resistor option register 13
Port mode register 13
Read signal
Write signal
When using the alternate function TO24, set the port latch to 0.
When using the alternate function CTxD1, set the port latch to 1.
When using P134 as a general-purpose port, specify the port settings so that the alternate function
outputs are fixed (Timer to 0 and Serial to 1).
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Figure 4-53. Block Diagram of P135
EVDD
WRPU
PU13
PU135
P-ch
WRPIM
PIM13
PIM135
Alternate
function
Schmitt1
RD
Schmitt3
WRPORT
P13
Output latch
(P135)
P135/SGO/SGOF/
CRxD1/TI26/TO26
WRPM
PM13
PM135
Alternate
function
(SGO/SGOF)
Alternate
function
(TO26)
P13:
PU13:
PM13:
RD:
WRxx:
Caution
Port register 13
Pull-up resistor option register 13
Port mode register 13
Read signal
Write signal
When using the alternate function SGO/SGOF or TO26, set the port latch to 0.
When using P135 as a general-purpose port, specify the port settings so that the alternate function
outputs are fixed to 0.
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Figure 4-54. Block Diagram of P136
EVDD
WRPU
PU13
PU136
P-ch
Alternate
function
RD
WRPORT
P13
Output latch
(P136)
WRPM
PM13
PM136
P136/TI00/TO00/
SCL11/SEG48
Alternate
function
(TO00)
WRPOM
POM
POM_4
Alternate
function
(SCL11)
LCD controller/driver
WRLCDPF
LCDPF13
PF136
P13:
PU13:
PM13:
LCDPF13:
POM:
RD:
WRxx:
Caution
Port register 13
Pull-up resistor option register 13
Port mode register 13
LCD port function registers 13
Port Output mode register
Read signal
Write signal
When using the alternate function TO00, set the port latch to 0.
When using the alternate function SCL11, set the port latch to 1.
When using P136 as a general-purpose port, specify the port settings so that the alternate function
outputs are fixed (Timer to 0 and Serial to 1).
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Figure 4-55. Block Diagram of P137
Internal bus
Alternate
function
RD
P137/INTP5
RD:
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4.2.15 Port 14
48-pin products:
Not provided
64-pin products:
Not provided
80-pin products:
Not provided
100-pin products:
P140 functions as a 1-bit I/O port.
128-pin products:
P140 functions as a 1-bit I/O port.
P140 is a 1-bit I/O port with an output latch. P140 can be set to the input mode or output mode using port mode register
14 (PM14). When the P140 pin is used as an input port, use of an on-chip pull-up resistor can be specified by pull-up
resistor option register 14 (PU14).
This pin also functions as timer I/O.
To use P140 as the port function, refer Table 4-17.
Table 4-17. Setting of P140 Pin to port function
P140 Pin
port
P140
function
Input port
LCDPF14
Alternate function
Register
Timer
N/A
Output port
0
Serial
N/A
PM14
PIM
POM
Register
Register
Register
Input mode
N/A
Remarks
N/A
Output mode
Reset signal generation sets port 14 to input mode.
Figure 4-56 shows block diagram of port 14.
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Figure 4-56. Block Diagram of P140
EVDD
WRPU
PU14
PU140
P-ch
Alternate
function
Internal bus
Selector
RD
WRPORT
P14
Output latch
(P140)
P140/TI11/TO11
WRPM
PM14
PM140
Alternate
function
(TO11)
P14:
PU14:
PM14:
RD:
WRxx:
Caution
Port register 14
Pull-up resistor option register 14
Port mode register 14
Read signal
Write signal
When using the alternate function TO11, set the port latch to 0.
When using P140 as a general-purpose port, specify the port settings so that the alternate function
output is fixed to 0.
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4.2.16 Port 15
48-pin products:
Not provided
64-pin products:
Not provided
80-pin products:
Not provided
100-pin products:
P150 functions as a 1-bit I/O port.
128-pin products:
P150 to P152 function as a 3-bit I/O port
Port 15 is a 3-bit port with an output latch. Port 15 can be set to the input mode or output mode in 1-bit units using port
mode register 15 (PM15).
This port can also be used for A/D converter analog input.
To use P150/ANI8 to P152/ANI10 as digital input pins, set them in the digital I/O mode by using the A/D port
configuration register (ADPC) and in the input mode by using the PM15 register. Use these pins starting from the upper bit.
To use P150/ANI8 to P152/ANI10 as digital output pins, set them in the digital I/O mode by using the ADPC register
and in the output mode by using the PM15 register. Use these pins starting from the upper bit.
To use P150/ANI8 to P152/ANI10 as analog input pins, set them in the analog input mode by using the A/D port
configuration register (ADPC) and in the input mode by using the PM15 register. Use these pins starting from the lower bit.
Table 4-18. Setting of P150 to P152 Pins
P150 Pin
port
P150
function
Input port
ADPC
PM2
Register
Register
0001 to 1001
Output port
P151
Input port
Input port
Output port
Input mode
Output mode
0001 to 1010
Output port
P152
Remarks
Input mode
Output mode
0001 to 1011
Input mode
Output mode
All P150/ANI8 to P152/ANI10 are set in the analog input mode when the reset signal is generated.
Figure 4-57 shows block diagram of port 15.
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Figure 4-57. Block Diagram of P150 to P152
WRADPC
ADPC
Input enable
ADPC3 to ADPC0
Internal bus
Selector
RD
WRPORT
P15
Output latch
(P150 to P152)
P150/ANI8
to P152/ANI10
WRPM
PM15
PM150 to PM152
A/D converter
P15:
PM15:
ADPC:
RD:
WRxx:
Port register 15
Port mode register 15
A/D port configuration register
Read signal
Write signal
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4.3 Registers Controlling Port Function
Port functions are controlled by the following registers.
Port mode registers (PMxx)
Port registers (Pxx)
Pull-up resistor option registers (PUxx)
Port input mode registers (PIMxx)
Port output mode registers (POM)
LCD port function register (LCDPFxx)
A/D port configuration register (ADPC)
Stepper motor control register (SMPC)
Caution The undefined bits in each register vary by product and must be used with their initial value.
Table 4-19. Pxx, PMxx, PUxx, PIMxx, POM, LCDPFxx registers and the bits mounted on each products (1/4)
Port
Port 0
Port 1
Port 2
Bit name
128-pin
Pxx
PMxx
PUxx
PIMxx
POM
LCDPFxx
register
register
register
register
register
register
100-pin
80-pin
64-pin
48-pin
0
PM00
PU00
N/A
LCDPF00
1
PM01
PU01
PIM01
LCDPF01
2
PM02
PU02
N/A
LCDPF02
N/A
3
PM03
PU03
LCDPF03
N/A
4
PM04
PU04
LCDPF04
N/A
5
PM05
PU05
LCDPF05
N/A
6
PM06
PU06
LCDPF06
N/A
N/A
7
PM07
PU07
LCDPF07
N/A
N/A
0
PM10
PU10
PIM10
LCDPF10
1
PM11
PU11
PIM11
LCDPF11
2
PM12
PU12
N/A
LCDPF12
3
PM13
PU13
LCDPF13
4
PM14
PU14
LCDPF14
5
PM15
PU15
LCDPF15
N/A
6
PM16
PU16
LCDPF16
N/A
N/A
7
PM17
PU17
PIM17
LCDPF17
N/A
N/A
N/A
N/A
0
PM20
1
PM21
2
PM22
3
PM23
4
PM24
N/A
N/A
5
PM25
N/A
N/A
6
PM26
N/A
N/A
7
PM27
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Table 4-19. Pxx, PMxx, PUxx, PIMxx, POM, LCDPFxx registers and the bits mounted on each products (2/4)
Port
Bit name
Pxx
register
Port 3
Port 4
Port 5
Port 6
Port 7
PMxx
register
PUxx
register
PIMxx
register
128-pin
POM
register
100-pin
80-pin
64-pin
48-pin
LCDPFxx
register
0
P30
PM30
PU30
N/A
POM2
LCDPF30
1
P31
PM31
PU31
PIM31
POM3
LCDPF31
2
P32
PM32
PU32
N/A
N/A
LCDPF32
N/A
3
P33
PM33
PU33
LCDPF33
4
P34
PM34
PU34
LCDPF34
N/A
N/A
5
P35
PM35
PU35
LCDPF35
N/A
N/A
6
P36
PM36
PU36
LCDPF36
N/A
N/A
7
P37
PM37
PU37
LCDPF37
N/A
N/A
0
P40
PM40
PU40
N/A
N/A
N/A
1
P41
PM41
PU41
N/A
N/A
N/A
N/A
N/A
2
P42
PM42
PU42
LCDPF42
N/A
N/A
N/A
N/A
3
P43
PM43
PU43
LCDPF43
N/A
N/A
N/A
N/A
4
P44
PM44
PU44
LCDPF44
N/A
N/A
N/A
N/A
5
P45
PM45
PU45
LCDPF45
N/A
N/A
N/A
N/A
6
P46
PM46
PU46
LCDPF46
N/A
N/A
N/A
N/A
7
P47
PM47
PU47
LCDPF47
N/A
N/A
N/A
N/A
0
P50
PM50
PU50
LCDPF50
N/A
N/A
N/A
LCDPF51
PIM50
POM5
N/A
1
P51
PM51
PU51
PIM51
N/A
N/A
N/A
2
P52
PM52
PU52
PIM52
LCDPF52
N/A
N/A
N/A
3
P53
PM53
PU53
N/A
LCDPF53
N/A
N/A
N/A
4
P54
PM54
PU54
LCDPF54
5
P55
PM55
PU55
PIM55
LCDPF55
6
P56
PM56
PU56
PIM56
LCDPF56
7
P57
PM57
PU57
PIM57
LCDPF57
0
P60
PM60
PU60
N/A
POM0
N/A
1
P61
PM61
PU61
PIM61
POM1
2
P62
PM62
PU62
N/A
N/A
N/A
N/A
N/A
3
P63
PM63
PU63
PIM63
N/A
N/A
N/A
4
P64
PM64
PU64
N/A
N/A
N/A
N/A
5
P65
PM65
PU65
N/A
N/A
6
P66
PM66
PU66
N/A
N/A
0
P70
PM70
PU70
PIM70
N/A
1
P71
PM71
PU71
N/A
N/A
2
P72
PM72
PU72
LCDPF72
3
P73
PM73
PU73
LCDPF73
4
P74
PM74
PU74
LCDPF74
5
P75
PM75
PU75
LCDPF75
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Table 4-19. Pxx, PMxx, PUxx, PIMxx, POM, LCDPFxx registers and the bits mounted on each products (3/4)
Port
Port 8
Port 9
Bit name
128-pin
Pxx
PMxx
PUxx
PIMxx
POM
register
register
register
register
register
100-pin
80-pin
64-pin
48-pin
LCDPFxx
register
LCDPF80
PU81
LCDPF81
PM82
PU82
LCDPF82
P83
PM83
PU83
LCDPF83
4
P84
PM84
PU84
LCDPF84
N/A
5
P85
PM85
PU85
LCDPF85
N/A
6
P86
PM86
PU86
LCDPF86
N/A
7
P87
PM87
PU87
LCDPF87
0
P90
PM90
PU90
1
P91
PM91
2
P92
3
0
P80
PM80
PU80
1
P81
PM81
2
P82
3
N/A
N/A
N/A
LCDPF90
PU91
LCDPF91
PM92
PU92
LCDPF92
P93
PM93
PU93
LCDPF93
4
P94
PM94
PU94
LCDPF94
5
P95
PM95
PU95
LCDPF95
N/A
N/A
6
P96
PM96
PU96
LCDPF96
N/A
N/A
7
LCDPF97
N/A
N/A
LCDPF100
N/A
N/A
P97
PM97
PU97
Port 10 0
P100
PM100
PU100
N/A
N/A
N/A
N/A
1
P101
PM101
PU101
LCDPF101
N/A
N/A
N/A
N/A
2
P102
PM102
PU102
LCDPF102
N/A
N/A
N/A
N/A
3
P103
PM103
PU103
LCDPF103
N/A
N/A
N/A
N/A
4
P104
PM104
PU104
LCDPF104
N/A
N/A
N/A
N/A
5
P105
PM105
PU105
LCDPF105
N/A
N/A
N/A
N/A
6
P106
PM106
PU106
LCDPF106
N/A
N/A
N/A
N/A
LCDPF107
N/A
N/A
N/A
N/A
LCDPF110
N/A
N/A
7
P107
PM107
PU107
Port 11 0
P110
PM110
PU110
N/A
N/A
N/A
N/A
1
P111
PM111
PU111
LCDPF111
N/A
N/A
N/A
N/A
2
P112
PM112
PU112
LCDPF112
N/A
N/A
N/A
N/A
3
P113
PM113
PU113
LCDPF113
N/A
N/A
N/A
N/A
4
P114
PM114
PU114
LCDPF114
N/A
N/A
N/A
N/A
5
P115
PM115
PU115
LCDPF115
N/A
N/A
N/A
N/A
6
P116
PM116
PU116
LCDPF116
N/A
N/A
N/A
N/A
7
P117
PM117
PU117
LCDPF117
N/A
N/A
N/A
N/A
1
P121
N/A
N/A
2
P122
3
P123
N/A
4
P124
N/A
Port 12
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N/A
N/A
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N/A
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Table 4-19. Pxx, PMxx, PUxx, PIMxx, POM, LCDPFxx registers and the bits mounted on each products (4/4)
Port
Port 13
Port 14
Port 15
Bit name
128-pin
Pxx
PMxx
PUxx
PIMxx
POM
LCDPFxx
register
register
register
register
register
register
N/A
N/A
N/A
100-pin
80-pin
64-pin
48-pin
N/A
N/A
N/A
0
P130
N/A
N/A
1
P131
PM131
PU131
N/A
N/A
N/A
2
P132
PM132
PU132
N/A
N/A
N/A
3
P133
PM133
PU133
N/A
N/A
N/A
4
P134
PM134
PU134
N/A
N/A
N/A
5
P135
PM135
PU135
PIM135
N/A
N/A
N/A
6
P136
PM136
PU136
N/A
7
P137
N/A
N/A
0
P140
PM140
PU140
N/A
POM4
LCDPF136
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
P150
PM150
N/A
N/A
N/A
1
P151
PM151
N/A
N/A
N/A
N/A
2
P152
PM152
N/A
N/A
N/A
N/A
The format of each register is described in the following pages.
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(1) Port mode registers (PM0 to PM9, PM13 to PM15)
These registers specify input or output mode for the port in 1-bit units.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
When port pins are used as alternate-function pins, set the port mode register by referencing 4.5 Settings of Port
Mode Register, and Output Latch When Using Alternate Function.
Figure 4-58. Format of Port Mode Register (1/5)
(48-pin products)
Symbol
7
6
5
4
3
2
1
0
PM0
1
1
1
1
1
1
PM01
PM00
FFF20
FFH
R/W
PM1
1
1
1
PM14
PM13
PM12
PM11
PM10
FFF21
FFH
R/W
PM2
PM27
1
1
1
PM23
PM22
PM21
PM20
FFF22
FFH
R/W
PM3
1
1
1
1
PM33
1
PM31
PM30
FFF23
FFH
R/W
PM4
1
1
1
1
1
1
1
PM40
FFF24
FFH
R/W
PM5
PM57
PM56
PM55
PM54
1
1
1
1
FFF25
FFH
R/W
PM6
1
1
1
1
1
1
PM61
PM60
FFF26
FFH
R/W
PM7
1
1
PM75
PM74
PM73
PM72
1
1
FFF27
FFH
R/W
PM8
1
1
1
1
PM83
PM82
PM81
PM80
FFF28
FFH
R/W
PM9
1
1
1
PM94
PM93
PM92
PM91
PM90
FFF29
FFH
R/W
PM13
1
1
1
1
1
1
1
1
FFF2D
FEH
R/W
PMmn
Pmn pin I/O mode selection (m = 0 to 9 and 13 ; n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
Caution
Address After reset R/W
Be sure to set bits 2 to 7 of the PM0 register, bits 5 to 7 of the PM1 register, bits 4 to 6 of the PM2
register, bits 2 and 4 to 7 of the PM3 register, bits 1 to 7 of the PM4 register, bits 0 to 3 of the PM5
register, bits 2 to 7 of the PM6 register, bits 0 to 1 and 6 to 7 of the PM7 register, bits 4 to 7 of the
PM8 register, bits 5 to 7 of the PM9 register and bits 0 to 7 of the PM13 register to “1”.
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Figure 4-58. Format of Port Mode Register (2/5)
(64-pin products)
Symbol
7
6
5
4
3
2
1
0
PM0
PM07
1
PM05
PM04
PM03
PM02
PM01
PM00
FFF20
FFH
R/W
PM1
PM17
1
PM15
PM14
PM13
PM12
PM11
PM10
FFF21
FFH
R/W
PM2
PM27
1
1
1
PM23
PM22
PM21
PM20
FFF22
FFH
R/W
PM3
1
1
1
1
PM33
PM32
PM31
PM30
FFF23
FFH
R/W
PM4
1
1
1
1
1
1
1
PM40
FFF24
FFH
R/W
PM5
PM57
PM56
PM55
PM54
1
1
1
1
FFF25
FFH
R/W
PM6
1
1
1
1
1
1
PM61
PM60
FFF26
FFH
R/W
PM7
1
1
PM75
PM74
PM73
PM72
PM71
PM70
FFF27
FFH
R/W
PM8
PM87
PM86
PM85
PM84
PM83
PM82
PM81
PM80
FFF28
FFH
R/W
PM9
1
1
1
PM94
PM93
PM92
PM91
PM90
FFF29
FFH
R/W
PMmn
Pmn pin I/O mode selection (m = 0 to 9 ; n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
Caution
Address After reset R/W
Be sure to set bits 6 of the PM0 and PM1 register, bits 4 to 6 of the PM2 register, bits 4 to 7 of the
PM3 register, bits 1 to 7 of the PM4 register, bits 0 to 3 of the PM5 register, bits 2 to 7 of the PM6
register, bits 6 and 7 of the PM7 register, and bits 5 to 7 of the PM9 register to “1”.
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Figure 4-58. Format of Port Mode Register (3/5)
(80-pin products)
Symbol
7
6
5
4
3
2
1
0
PM0
PM07
PM06
PM05
PM04
PM03
PM02
PM01
PM00
FFF20
FFH
R/W
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
FFF21
FFH
R/W
PM2
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
FFF22
FFH
R/W
PM3
PM37
PM36
PM35
PM34
PM33
PM32
PM31
PM30
FFF23
FFH
R/W
PM4
1
1
1
1
1
1
1
PM40
FFF24
FFH
R/W
PM5
PM57
PM56
PM55
PM54
1
1
1
1
FFF25
FFH
R/W
PM6
1
PM66
PM65
1
1
1
PM61
PM60
FFF26
FFH
R/W
PM7
1
1
PM75
PM74
PM73
PM72
PM71
PM70
FFF27
FFH
R/W
PM8
PM87
PM86
PM85
PM84
PM83
PM82
PM81
PM80
FFF28
FFH
R/W
PM9
PM97
PM96
PM95
PM94
PM93
PM92
PM91
PM90
FFF29
FFH
R/W
PMmn
Pmn pin I/O mode selection (m = 0 to 9 ; n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
Caution
Address After reset R/W
Be sure to set bits 1 to 7 of the PM4 register, bits 0 to 3 of the PM5, bits 2 to 4 and 7 of the PM6
register, and bits 6 and 7 of the PM7 register to “1”.
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Figure 4-58. Format of Port Mode Register (4/5)
(100-pin products)
Symbol
7
6
5
4
3
2
1
0
PM0
PM07
PM06
PM05
PM04
PM03
PM02
PM01
PM00
FFF20
FFH
R/W
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
FFF21
FFH
R/W
PM2
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
FFF22
FFH
R/W
PM3
PM37
PM36
PM35
PM34
PM33
PM32
PM31
PM30
FFF23
FFH
R/W
PM4
1
1
1
1
1
1
1
PM40
FFF24
FFH
R/W
PM5
PM57
PM56
PM55
PM54
PM53
PM52
PM51
PM50
FFF25
FFH
R/W
PM6
1
PM66
PM65
PM64
PM63
PM62
PM61
PM60
FFF26
FFH
R/W
PM7
1
1
PM75
PM74
PM73
PM72
PM71
PM70
FFF27
FFH
R/W
PM8
PM87
PM86
PM85
PM84
PM83
PM82
PM81
PM80
FFF28
FFH
R/W
PM9
PM97
PM96
PM95
PM94
PM93
PM92
PM91
PM90
FFF29
FFH
R/W
PM13
1
PM136
PM135
PM134
PM133
PM132
PM131
0
FFF2D
FEH
R/W
PM14
1
1
1
1
1
1
1
PM140
FFF2E
FFH
R/W
PM15
1
1
1
1
1
1
1
PM150
FFF2F
FFH
R/W
PMmn
Pmn pin I/O mode selection (m = 0 to 9 and 13 to 15 ; n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
Caution
Address After reset R/W
Be sure to set bits 1 to 7 of the PM4 register, bits 7 of the PM6 register, bits 6 and 7 of the PM7
register, bits 7 of the PM13 register, and bits 1 to 7 of the PM14 and PM15 registers to “1” and bit 0 of
the PM13 register to “0”.
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Figure 4-58. Format of Port Mode Register (5/5)
(128-pin products)
Symbol
7
6
5
4
3
2
1
0
PM0
PM07
PM06
PM05
PM04
PM03
PM02
PM01
PM00
FFF20
FFH
R/W
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
FFF21
FFH
R/W
PM2
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
FFF22
FFH
R/W
PM3
PM37
PM36
PM35
PM34
PM33
PM32
PM31
PM30
FFF23
FFH
R/W
PM4
PM47
PM46
PM45
PM44
PM43
PM42
PM41
PM40
FFF24
FFH
R/W
PM5
PM57
PM56
PM55
PM54
PM53
PM52
PM51
PM50
FFF25
FFH
R/W
PM6
1
PM66
PM65
PM64
PM63
PM62
PM61
PM60
FFF26
FFH
R/W
PM7
1
1
PM75
PM74
PM73
PM72
PM71
PM70
FFF27
FFH
R/W
PM8
PM87
PM86
PM85
PM84
PM83
PM82
PM81
PM80
FFF28
FFH
R/W
PM9
PM97
PM96
PM95
PM94
PM93
PM92
PM91
PM90
FFF29
FFH
R/W
PM10
PM107
PM106
PM105
PM104
PM103
PM102
PM101
PM100
FFF2A
FEH
R/W
PM11
PM117
PM116
PM115
PM114
PM113
PM112
PM111
PM110
FFF2B
FFH
R/W
PM12
PM127
PM126
PM125
1
1
1
1
1
FFF2C
FFH
R/W
PM13
1
PM136P
PM135
PM134
PM133
PM132
PM131
0
FFF2D
FEH
R/W
PM14
1
1
1
1
1
1
1
PM140
FFF2E
FFH
R/W
PM15
1
1
1
1
1
PM152
PM151
PM150
FFF2F
FFH
R/W
PMmn
Pmn pin I/O mode selection (m = 0 to 15 ; n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
Caution
Address After reset R/W
Be sure to set bits 1 to 7 of the PM4 register, bits 7 of the PM6 register, bits 6 and 7 of the PM7
register, bits 0 to 4 of the PM12 register, bits 7 of the PM13 register, bits 1 to 7 of the PM14, and bits 3
to 7 of the PM15 registers to “1” and bit 0 of the PM13 register to “0”.
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CHAPTER 4 PORT FUNCTIONS
(2) Port registers (P0 to P15)
These registers set the output latch value of a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is
Note
read
.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Note If P20 to P27 and P150 to P152 are set up as analog inputs of the A/D converter, when a port is read while in the
input mode, 0 is always returned, not the pin level. And while in output mode, the output latch value is not output
to port.
If P00 to P07, P10 to P17, P30 to P37, P42 to P47, P50 to P57, P72 to P75, P80 to P87, P90 to P97, P100 to
P107, P110 to P117, P125 to P127, and P136 are set up as the segment outputs of LCD controller/driver, when
a port is read while in the input mode, 0 is always returned, not the pin level. And while in output mode, the
output latch value is not output to port.
If P83, P87, P93, and P97 are set up to ZPD input, when a port is read while in the input mode, 0 is always
returned, not the pin level. And while in output mode, the output latch value is not output to port.
Active alternate function
A/D converter input
Port read in input mode
Port output in output mode
0 is read
output latch value is not output
LCD segment output
0 is read
output latch value is not output
ZPD input
0 is read
output latch value is not output
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Figure 4-59. Format of Port Register (1/5)
(48-pin products)
Symbol
7
6
5
4
3
2
1
0
P0
0
0
0
0
0
0
P01
P00
FFF00
00H
R/W
P1
0
0
0
P14
P13
P12
P11
P10
FFF01
00H
R/W
P2
P27
0
0
0
P23
P22
P21
P20
FFF02
00H
R/W
P3
0
0
0
0
P33
0
P31
P30
FFF03
00H
R/W
P4
0
0
0
0
0
0
0
P40
FFF04
00H
R/W
P5
P57
P56
P55
P54
0
0
0
0
FFF05
00H
R/W
P6
0
0
0
0
0
0
P61
P60
FFF06
00H
R/W
P7
0
0
P75
P74
P73
P72
0
0
FFF07
00H
R/W
P8
0
0
0
0
P83
P82
P81
P80
FFF08
00H
R/W
P9
0
0
0
P94
P93
P92
P91
P90
FFF09
00H
R/W
P12
0
0
0
0
0
P122
P121
0
FFF0C
00H
Read only
P13
P137
0
0
0
0
0
0
0
FFF0D
00H
Read only
Pmn
Output data control (in output mode)
Address After reset R/W
(output latch)
Input data read (in input mode)
0
Output 0
Input low level
1
Output 1
Input high level
Remark m = 0 to 9, 12, and 13 ; n = 0 to 7
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Figure 4-59. Format of Port Register (2/5)
(64-pin products)
Symbol
7
6
5
4
3
2
1
0
P0
P07
0
P05
P04
P03
P02
P01
P00
FFF00
00H
R/W
P1
P17
0
P15
P14
P13
P12
P11
P10
FFF01
00H
R/W
P2
P27
0
0
0
P23
P22
P21
P20
FFF02
00H
R/W
P3
0
0
0
0
P33
P32
P31
P30
FFF03
00H
R/W
P4
0
0
0
0
0
0
0
P40
FFF04
00H
R/W
P5
P57
P56
P55
P54
0
0
0
0
FFF05
00H
R/W
P6
0
0
0
0
0
0
P61
P60
FFF06
00H
R/W
P7
0
0
P75
P74
P73
P72
P71
P70
FFF07
00H
R/W
P8
P87
P86
P85
P84
P83
P82
P81
P80
FFF08
00H
R/W
P9
0
0
0
P94
P93
P92
P91
P90
FFF09
00H
R/W
P12
0
0
0
P124
P123
P122
P121
0
FFF0C
00H
Read only
P13
P137
0
0
0
0
0
0
0
FFF0D
00H
Read only
Pmn
Output data control (in output mode)
Address After reset R/W
(output latch)
Input data read (in input mode)
0
Output 0
Input low level
1
Output 1
Input high level
Remark m = 0 to 9, 12, and 13 ; n = 0 to 7
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Figure 4-59. Format of Port Register (3/5)
(80-pin products)
Symbol
7
6
5
4
3
2
1
0
P0
P07
P06
P05
P04
P03
P02
P01
P00
FFF00
00H
R/W
P1
P17
P16
P15
P14
P13
P12
P11
P10
FFF01
00H
R/W
P2
P27
P26
P25
P24
P23
P22
P21
P20
FFF02
00H
R/W
P3
P37
P36
P35
P34
P33
P32
P31
P30
FFF03
00H
R/W
P4
0
0
0
0
0
0
0
P40
FFF04
00H
R/W
P5
P57
P56
P55
P54
0
0
0
0
FFF05
00H
R/W
P6
0
P66
P65
0
0
0
P61
P60
FFF06
00H
R/W
P7
0
0
P75
P74
P73
P72
P71
P70
FFF07
00H
R/W
P8
P87
P86
P85
P84
P83
P82
P81
P80
FFF08
00H
R/W
P9
P97
P96
P95
P94
P93
P92
P91
P90
FFF09
00H
R/W
P12
0
0
0
P124
P123
P122
P121
0
FFF0C
00H
Read only
P13
P137
0
0
0
0
0
0
0
FFF0D
00H
Read only
Pmn
Address After reset R/W
(output latch)
Output data control (in output mode)
Input data read (in input mode)
0
Output 0
Input low level
1
Output 1
Input high level
Remark m = 0 to 9, 12, and 13 ; n = 0 to 7
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CHAPTER 4 PORT FUNCTIONS
Figure 4-59. Format of Port Register (4/5)
(100-pin products)
Symbol
7
6
5
4
3
2
1
0
P0
P07
P06
P05
P04
P03
P02
P01
P00
FFF00
00H
R/W
P1
P17
P16
P15
P14
P13
P12
P11
P10
FFF01
00H
R/W
P2
P27
P26
P25
P24
P23
P22
P21
P20
FFF02
00H
R/W
P3
P37
P36
P35
P34
P33
P32
P31
P30
FFF03
00H
R/W
P4
0
0
0
0
0
0
0
P40
FFF04
00H
R/W
P5
P57
P56
P55
P54
P53
P52
P51
P50
FFF05
00H
R/W
P6
0
P66
P65
P64
P63
P62
P61
P60
FFF06
00H
R/W
P7
0
0
P75
P74
P73
P72
P71
P70
FFF07
00H
R/W
P8
P87
P86
P85
P84
P83
P82
P81
P80
FFF08
00H
R/W
P9
P97
P96
P95
P94
P93
P92
P91
P90
FFF09
00H
R/W
P12
0
0
0
P124
P123
P122
P121
0
FFF0C
00H
Read only
P13
P137
P136
P135
P134
P133
P132
P131
P130
FFF0D
00H
P14
0
0
0
0
0
0
0
P140
FFF0E
00H
R/W
P15
0
0
0
0
0
0
0
P150
FFF0F
00H
R/W
Pmn
Address After reset R/W
(output latch)
R/W
Note
m = 0 to 9 and 12 to 15 ; n = 0 to 7
Output data control (in output mode)
Input data read (in input mode)
0
Output 0
Input low level
1
Output 1
Input high level
Note P137 is read only.
Remark m = 0 to 9 and 12 to 15 ; n = 0 to 7
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CHAPTER 4 PORT FUNCTIONS
Figure 4-59. Format of Port Registers (5/5)
(128-pin products)
Symbol
7
6
5
4
3
2
1
0
P0
P07
P06
P05
P04
P03
P02
P01
P00
FFF00
00H
R/W
P1
P17
P16
P15
P14
P13
P12
P11
P10
FFF01
00H
R/W
P2
P27
P26
P25
P24
P23
P22
P21
P20
FFF02
00H
R/W
P3
P37
P36
P35
P34
P33
P32
P31
P30
FFF03
00H
R/W
P4
P47
P46
P45
P44
P43
P42
P41
P40
FFF04
00H
R/W
P5
P57
P56
P55
P54
P53
P52
P51
P50
FFF05
00H
R/W
P6
0
P66
P65
P64
P63
P62
P61
P60
FFF06
00H
R/W
P7
0
0
P75
P74
P73
P72
P71
P70
FFF07
00H
R/W
P8
P87
P86
P85
P84
P83
P82
P81
P80
FFF08
00H
R/W
P9
P97
P96
P95
P94
P93
P92
P91
P90
FFF09
00H
R/W
P10
P107
P106
P105
P104
P103
P102
P101
P100
FFF0A
00H
R/W
P11
P117
P116
P115
P114
P113
P112
P111
P110
FFF0B
00H
R/W
P12
P127
P126
P125
P124
P123
P122
P121
0
FFF0C
00H
Read only
P13
P137
P136
P135
P134
P133
P132
P131
P130
FFF0D
00H
P14
0
0
0
0
0
0
0
P140
FFF0E
00H
R/W
P15
0
0
0
0
0
P152
P151
P150
FFF0F
00H
R/W
Pmn
Output data control (in output mode)
Address After reset R/W
(output latch)
R/W
Note
Input data read (in input mode)
0
Output 0
Input low level
1
Output 1
Input high level
Note P137 is read only.
Remark m = 0 to 15 ; n = 0 to 7
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(3)
CHAPTER 4 PORT FUNCTIONS
Pull-up resistor option registers (PU0, PU1, PU3 to PU14)
These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be
used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has
been specified in these registers. On-chip pull-up resistors cannot be connected to bits set to output mode, bits used
as alternate-function output pins, bits used as alternate-function ZPD input pins, and POM is set to 1, regardless of
the settings of these registers.
Table 4-20. on-chip pull-up resistor enable condition
operation mode
on-chip pull-up resistor
PM register setting
other setting
output mode
-
Input mode
Can not be connected
alternate-function output mode
ZPD input mode
POM is set to 1
Input mode
other than those above
usable
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H (Only PU4 is set to 01H)
Figure 4-60. Format of Pull-up resistor option Register (1/5)
(48-pin products)
Symbol
7
6
5
4
3
2
1
0
PU0
0
0
0
0
0
0
PU01
PU00
F0030
00H
R/W
PU1
0
0
0
PU14
PU13
PU12
PU11
PU10
F0031
00H
R/W
PU3
0
0
0
0
PU33
0
PU31
PU30
F0033
00H
R/W
PU4
0
0
0
0
0
0
0
PU40
F0034
01H
R/W
PU5
PU57
PU56
PU55
PU54
0
0
0
0
F0035
00H
R/W
PU6
0
0
0
0
0
0
PU61
PU60
F0036
00H
R/W
PU7
0
0
PU75
PU74
PU73
PU72
0
0
F0037
00H
R/W
PU8
0
0
0
0
PU83
PU82
PU81
PU80
F0038
00H
R/W
PU9
0
0
0
PU94
PU93
PU92
PU91
PU90
F0039
00H
R/W
PU13
0
0
0
0
0
0
0
0
F003D
00H
R/W
PUmn
Address After reset R/W
Pmn pin on-chip pull-up resistor selection (m = 0 to 9, and 13 ; n = 0 to 7)
0
On-chip pull-up resistor not connected
1
On-chip pull-up resistor connected
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Figure 4-60. Format of Pull-up resistor option Register (2/5)
(64-pin products)
Symbol
7
6
5
4
3
2
1
0
PU0
PU07
0
PU05
PU04
PU03
PU02
PU01
PU00
F0030
00H
R/W
PU1
PU17
0
PU15
PU14
PU13
PU12
PU11
PU10
F0031
00H
R/W
PU3
0
0
0
0
PU33
PU32
PU31
PU30
F0033
00H
R/W
PU4
0
0
0
0
0
0
0
PU40
F0034
01H
R/W
PU5
PU57
PU56
PU55
PU54
0
0
0
0
F0035
00H
R/W
PU6
0
0
0
0
0
0
PU61
PU60
F0036
00H
R/W
PU7
0
0
PU75
PU74
PU73
PU72
PU71
PU70
F0037
00H
R/W
PU8
PU87
PU86
PU85
PU84
PU83
PU82
PU81
PU80
F0038
00H
R/W
PU9
0
0
0
PU94
PU93
PU92
PU91
PU90
F0039
00H
R/W
PUmn
Address After reset R/W
Pmn pin on-chip pull-up resistor selection (m = 0 to 9 ; n = 0 to 7)
0
On-chip pull-up resistor not connected
1
On-chip pull-up resistor connected
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Figure 4-60. Format of Pull-up resistor option Register (3/5)
(80-pin products)
Symbol
7
6
5
4
3
2
1
0
PU0
PU07
PU06
PU05
PU04
PU03
PU02
PU01
PU00
F0030
00H
R/W
PU1
PU17
PU16
PU15
PU14
PU13
PU12
PU11
PU10
F0031
00H
R/W
PU3
PU37
PU36
PU35
PU34
PU33
PU32
PU31
PU30
F0033
00H
R/W
PU4
0
0
0
0
0
0
0
PU40
F0034
01H
R/W
PU5
PU57
PU56
PU55
PU54
0
0
0
0
F0035
00H
R/W
PU6
0
PU66
PU65
0
0
0
PU61
PU60
F0036
00H
R/W
PU7
0
0
PU75
PU74
PU73
PU72
PU71
PU70
F0037
00H
R/W
PU8
PU87
PU86
PU85
PU84
PU83
PU82
PU81
PU80
F0038
00H
R/W
PU9
PU97
PU96
PU95
PU94
PU93
PU92
PU91
PU90
F0039
00H
R/W
PUmn
Address After reset R/W
Pmn pin on-chip pull-up resistor selection (m = 0 to 9 ; n = 0 to 7)
0
On-chip pull-up resistor not connected
1
On-chip pull-up resistor connected
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Figure 4-60. Format of Pull-up resistor option Register (4/5)
(100-pin products)
Symbol
7
6
5
4
3
2
1
0
PU0
PU07
PU06
PU05
PU04
PU03
PU02
PU01
PU00
F0030
00H
R/W
PU1
PU17
PU16
PU15
PU14
PU13
PU12
PU11
PU10
F0031
00H
R/W
PU3
PU37
PU36
PU35
PU34
PU33
PU32
PU31
PU30
F0033
00H
R/W
PU4
0
0
0
0
0
0
0
PU40
F0034
01H
R/W
PU5
PU57
PU56
PU55
PU54
PU53
PU52
PU51
PU50
F0035
00H
R/W
PU6
0
PU66
PU65
PU64
PU63
PU62
PU61
PU60
F0036
00H
R/W
PU7
0
0
PU75
PU74
PU73
PU72
PU71
PU70
F0037
00H
R/W
PU8
PU87
PU86
PU85
PU84
PU83
PU82
PU81
PU80
F0038
00H
R/W
PU9
PU97
PU96
PU95
PU94
PU93
PU92
PU91
PU90
F0039
00H
R/W
PU13
0
PU136
PU135
PU134
PU133
PU132
PU131
0
F003D
00H
R/W
PU14
0
0
0
0
0
0
0
PU140
F003E
00H
R/W
PUmn
Address After reset R/W
Pmn pin on-chip pull-up resistor selection (m = 0 to 9,13, and 14 ; n = 0 to 7)
0
On-chip pull-up resistor not connected
1
On-chip pull-up resistor connected
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Figure 4-60. Format of Pull-up resistor option Registers (5/5)
(128-pin products)
Symbol
7
6
5
4
3
2
1
0
PU0
PU07
PU06
PU05
PU04
PU03
PU02
PU01
PU00
F0030
00H
R/W
PU1
PU17
PU16
PU15
PU14
PU13
PU12
PU11
PU10
F0031
00H
R/W
PU3
PU37
PU36
PU35
PU34
PU33
PU32
PU31
PU30
F0033
00H
R/W
PU4
PU47
PU46
PU45
PU44
PU43
PU42
PU41
PU40
F0034
01H
R/W
PU5
PU57
PU56
PU55
PU54
PU53
PU52
PU51
PU50
F0035
00H
R/W
PU6
0
PU66
PU65
PU64
PU63
PU62
PU61
PU60
F0036
00H
R/W
PU7
0
0
PU75
PU74
PU73
PU72
PU71
PU70
F0037
00H
R/W
PU8
PU87
PU86
PU85
PU84
PU83
PU82
PU81
PU80
F0038
00H
R/W
PU9
PU97
PU96
PU95
PU94
PU93
PU92
PU91
PU90
F0039
00H
R/W
PU10
PU107
PU106
PU105
PU104
PU103
PU102
PU101
PU100
F003A
00H
R/W
PU11
PU117
PU116
PU115
PU114
PU113
PU112
PU111
PU110
F003B
00H
R/W
PU12
PU127
PU126
PU125
0
0
0
0
0
F003C
00H
R/W
PU13
0
PU136
PU135
PU134
PU133
PU132
PU131
0
F003D
00H
R/W
PU14
0
0
0
0
0
0
0
PU140
F003E
00H
R/W
PUmn
Address After reset R/W
Pmn pin on-chip pull-up resistor selection (m = 0, 1, 3 to 14 ; n = 0 to 7)
0
On-chip pull-up resistor not connected
1
On-chip pull-up resistor connected
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(4) Port input mode registers (PIM0, PIM1, PIM3, PIM5 to PIM7, PIM11, PIM13)
These registers set the input buffer of P01, P10, P11, P17, P31, P50 to P52, P55 to P57, P61, P63, P70, P110 to
P117, and P135 in 1-bit units.
Schmitt1 input buffer can be selected during serial communication with an external device of the different potential.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 4-61. Format of Port input mode Register (1/5)
(48-pin products)
Symbol
7
6
5
4
3
2
1
0
PIM0
0
0
0
0
0
0
PIM01
0
F0040
00H
R/W
PIM1
0
0
0
0
0
0
PIM11
PIM10
F0041
00H
R/W
PIM3
0
0
0
0
0
0
PIM31
0
F0043
00H
R/W
PIM5
PIM57
PIM56
PIM55
0
0
0
0
0
F0045
00H
R/W
PIM6
0
0
0
0
0
0
PIM61
0
F0046
00H
R/W
PIM7
0
0
0
0
0
0
0
0
F0047
00H
R/W
PIM13
0
0
0
0
0
0
0
0
F004D
00H
R/W
PIMmn
Address After reset R/W
PIMmn pin input threshold selection (m = 0, 1, 3, 5 to 7, and 13 ; n = 0 to 7)
0
Schmit1 input mode
1
Schmit3 input mode
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Figure 4-61. Format of Port input mode Register (2/5)
(64-pin products)
Symbol
7
6
5
4
3
2
1
0
PIM0
0
0
0
0
0
0
PIM01
0
F0040
00H
R/W
PIM1
PIM17
0
0
0
0
0
PIM11
PIM10
F0041
00H
R/W
PIM3
0
0
0
0
0
0
PIM31
0
F0043
00H
R/W
PIM5
PIM57
PIM56
PIM55
0
0
0
0
0
F0045
00H
R/W
PIM6
0
0
0
0
0
0
PIM61
0
F0046
00H
R/W
PIM7
0
0
0
0
0
0
0
PIM70
F0047
00H
R/W
PIMmn
Address After reset R/W
PIMmn pin input threshold selection (m = 0, 1, 3, and 5 to 7 ; n = 0 to 7)
0
Schmit1 input mode
1
Schmit3 input mode
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Figure 4-61. Format of Port input mode Register (3/5)
(80-pin products)
Symbol
7
6
5
4
3
2
1
0
PIM0
0
0
0
0
0
0
PIM01
0
F0040
00H
R/W
PIM1
PIM17
0
0
0
0
0
PIM11
PIM10
F0041
00H
R/W
PIM3
0
0
0
0
0
0
PIM31
0
F0043
00H
R/W
PIM5
PIM57
PIM56
PIM55
0
0
0
0
0
F0045
00H
R/W
PIM6
0
0
0
0
0
0
PIM61
0
F0046
00H
R/W
PIM7
0
0
0
0
0
0
0
PIM70
F0047
00H
R/W
PIMmn
Address After reset R/W
PIMmn pin input threshold selection (m = 0, 1, 3, and 5 to 7 ; n = 0 to 7)
0
Schmit1 input mode
1
Schmit3 input mode
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Figure 4-61. Format of Port input mode Register (4/5)
(100-pin products)
Symbol
7
6
5
4
3
2
1
0
PIM0
0
0
0
0
0
0
PIM01
0
F0040
00H
R/W
PIM1
PIM17
0
0
0
0
0
PIM11
PIM10
F0041
00H
R/W
PIM3
0
0
0
0
0
0
PIM31
0
F0043
00H
R/W
PIM5
PIM57
PIM56
PIM55
0
0
PIM52
PIM51
PIM50
F0045
00H
R/W
PIM6
0
0
0
0
PIM63
0
PIM61
0
F0046
00H
R/W
PIM7
0
0
0
0
0
0
0
PIM70
F0047
00H
R/W
PIM13
0
0
PIM135
0
0
0
0
0
F004D
00H
R/W
PIMmn
PIMmn pin input threshold selection (m = 0, 1, 3, 5 to 7, and 13 ; n = 0 to 7)
0
Schmit1 input mode
1
Schmit3 input mode
Bit name
Address After reset R/W
PIM01
Port input
P01/
function
CRxD0
PIM17
P17
PIM11
PIM10
PIM31
P11/
P10/
P31/
LRxD1
SCK00
SDA11
PIM57
P57
PIM56
PIM55
P56/
P55/
SCK01
SI01
SI00
Bit name
PIM52
PIM51
PIM50
PIM63
PIM61
PIM70
PIM135
Port input
P52/
P51/
P50/
P63/
P61/
P70/
P135/
function
SI10
SCK10
SDA11
CRxD1
SDA11
CRxD0
CRxD1
-
LRxD0
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Figure 4-61. Format of Port Input Mode Registers (5/5)
(128-pin products)
Symbol
7
6
5
4
3
2
1
0
PIM0
0
0
0
0
0
0
PIM01
0
F0040
00H
R/W
PIM1
PIM17
0
0
0
0
0
PIM11
PIM10
F0041
00H
R/W
PIM3
0
0
0
0
0
0
PIM31
0
F0043
00H
R/W
PIM5
PIM57
PIM56
PIM55
0
0
PIM52
PIM51
PIM50
F0045
00H
R/W
PIM6
0
0
0
0
PIM63
0
PIM61
0
F0046
00H
R/W
PIM7
0
0
0
0
0
0
0
PIM70
F0047
00H
R/W
PIM11
PIM117
PIM116
PIM115
PIM114
PIM113
PIM112
PIM111
PIM110
F004B
00H
R/W
PIM13
0
0
PIM135
0
0
0
0
0
F004D
00H
R/W
PIMmn
PIMmn pin input threshold selection (m = 0, 1, 3, 5 to 7, 11, and 13 ; n = 0 to 7)
0
Schmit1 input mode
1
Schmit3 input mode
Bit name
Address After reset R/W
PIM01
Port input
P01/
function
CRxD0
PIM17
P17
PIM11
PIM10
PIM31
P11/
P10/
P31/
LRxD1/
SCK00
SDA11
PIM57
P57
PIM56
PIM55
P56/
P55/
SCK01
SI01
SI00
Bit name
PIM52
PIM51
PIM50
PIM63
PIM61
PIM70
PIM135
Port input
P52/
P51/
P50/
P63/
P61/
P70/
P135/
function
SI10
SCK10
SDA11
CRxD1
SDA11
CRxD0/
CRxD1
-
LRxD0
Bit name
PIM117
PIM116
PIM115
PIM114
PIM113
PIM112
PIM111
Port input
P117/
P116/
P115/
P114/
P113/
P112/
P111/
P110/
function
DBD7
DBD6
DBD5
DBD4
DBD3
DBD2
DBD1
DBD0
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CHAPTER 4 PORT FUNCTIONS
(5) Port output mode register (POM)
This register sets the output mode of P30, P31, P50, P60, P61, P136 in 1-bit units.
N-ch open drain output (VDD tolerance) mode can be selected during serial communication with an external device of
the different potential, and for the SDA11 and SCL11 pins during simplified I2C communication with an external device
of the same potential.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 4-62. Format of Port input mode Register
(a) 48-pin products
Symbol
7
6
5
4
3
2
1
0
POM
0
0
0
0
POM3
POM2
POM1
POM0
Address After reset R/W
F006F
00H
R/W
(b) 64-pin products
Symbol
7
6
5
4
3
2
1
0
POM
0
0
0
0
POM3
POM2
POM1
POM0
Address After reset R/W
F006F
00H
R/W
(c) 80-pin products
Symbol
7
6
5
4
3
2
1
0
POM
0
0
0
0
POM3
POM2
POM1
POM0
Address After reset R/W
F006F
00H
R/W
(d) 100-pin products
Symbol
7
6
5
4
3
2
1
0
POM
0
0
POM5
POM4
POM3
POM2
POM1
POM0
Address After reset R/W
F006F
00H
R/W
(e) 128-pin products
Symbol
7
6
5
4
3
2
1
0
POM
0
0
POM5
POM4
POM3
POM2
POM1
POM0
POMn
Address After reset R/W
F006F
00H
R/W
Port output mode selection (n = 0 to 5)
0
Normal output (CMOS) mode
1
Nch-OD output (VDD tolerance) mode
Bit name
POM5
POM4
POM3
POM2
POM1
POM0
Port output
P50/
P136/
P31/
P30/
P61/
P60/
function
TO02/
TO00/
TO21/
TO20/
TO21/
TO20/
SDA11
SCL11
SDA11
SCL11
SDA11
SCL11
Remark
If use the alternate function of IIC, port output need to be set as Nch open-drain (Nch-OD) output. At that
time, POM forces on-chip pull-up resistors should not be active (disabled by circuit).
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(6) LCD port function register (LCDPF0, LCDPF1, LCDPF3, LCDPF5, LCDPF7 to LCDPF13)
These registers specify the LCD segment signal output function for the port in 1-bit units.
Table 4-21. LCDPFmn register function
LCDPFmn
PMmn
Port pin in/output mode
0
0
Output mode
0
1
Input mode (default)
1
0
Segment output mode (on-chip pull-up resistors to disabled, and port output is disabled)
1
1
Segment output mode (on-chip pull-up resistors to disabled, and port read forced to 0)
Figure 4-63. Format of LCD port function Register (1/5)
(48-pin products)
Symbol
7
6
5
4
3
2
LCDPF0
0
0
0
0
0
0
LCDPF1
0
0
0
LCDPF3
0
0
0
LCDPF5
0
0
LCDPF8
0
0
0
LCDPF9
0
0
0
LCDPF13
0
0
0
Address After reset R/W
F0050
00H
R/W
LCDPF14 LCDPF13 LCDPF12 LCDPF11 LCDPF10
F0051
00H
R/W
F0053
00H
R/W
0
LCDPF33
0
0
0
LCDPF31 LCDPF30
0
0
F0055
00H
R/W
0
0
F0057
00H
R/W
LCDPF83 LCDPF82 LCDPF81 LCDPF80
F0058
00H
R/W
LCDPF94 LCDPF93 LCDPF92 LCDPF91 LCDPF90
F0059
00H
R/W
F005D
00H
R/W
LCDPF75 LCDPF74 LCDPF73 LCDPF72
LCDPFmn
0
LCDPF01 LCDPF00
LCDPF57 LCDPF56 LCDPF55 LCDPF54
LCDPF7
1
0
0
0
0
0
0
LCDPFmn register function (m = 0, 1, 3, 5, 7 to 9, 13)
0
Used as port or alternate function other than segment output
1
Used as LCD segment signal output
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Figure 4-63. Format of LCD port function Register (2/5)
(64-pin products)
Symbol
7
6
LCDPF0
LCDPF07
0
LCDPF05 LCDPF04 LCDPF03 LCDPF02 LCDPF01 LCDPF00
F0050
00H
R/W
LCDPF1
LCDPF17
0
LCDPF15 LCDPF14 LCDPF13 LCDPF12 LCDPF11 LCDPF10
F0051
00H
R/W
LCDPF3
0
0
F0053
00H
R/W
LCDPF5
0
4
0
3
0
0
2
1
0
LCDPF33 LCDPF32 LCDPF31 LCDPF30
0
LCDPF57 LCDPF56 LCDPF55 LCDPF54
LCDPF7
LCDPF8
5
0
LCDPF75 LCDPF74 LCDPF73 LCDPF72
0
0
F0055
00H
R/W
0
0
F0057
00H
R/W
F0058
00H
R/W
F0059
00H
R/W
LCDPF87 LCDPF86 LCDPF85 LCDPF84 LCDPF83 LCDPF82 LCDPF81 LCDPF80
0
LCDPF9
0
0
LCDPF94 LCDPF93 LCDPF92 LCDPF91 LCDPF90
LCDPFmn
Address After reset R/W
LCDPFmn register function (m = 0, 1, 3, 5, 7 to 9)
0
Used as port or alternate function other than segment output
1
Used as LCD segment signal output
Figure 4-63. Format of LCD port function Register (3/5)
(80-pin products)
Symbol
7
6
5
4
3
2
1
0
Address After reset R/W
LCDPF0
LCDPF07 LCDPF06 LCDPF05 LCDPF04 LCDPF03 LCDPF02 LCDPF01 LCDPF00
F0050
00H
R/W
LCDPF1
LCDPF17 LCDPF16 LCDPF15 LCDPF14 LCDPF13 LCDPF12 LCDPF11 LCDPF10
F0051
00H
R/W
LCDPF3
LCDPF37 LCDPF36 LCDPF35 LCDPF34 LCDPF33 LCDPF32 LCDPF31 LCDPF30
F0053
00H
R/W
LCDPF5
LCDPF57 LCDPF56 LCDPF55 LCDPF54
0
LCDPF7
0
0
0
LCDPF75 LCDPF74 LCDPF73 LCDPF72
0
0
F0055
00H
R/W
0
0
F0057
00H
R/W
LCDPF8
LCDPF87 LCDPF86 LCDPF85 LCDPF84 LCDPF83 LCDPF82 LCDPF81 LCDPF80
F0058
00H
R/W
LCDPF9
LCDPF97 LCDPF96 LCDPF95 LCDPF94 LCDPF93 LCDPF92 LCDPF91 LCDPF90
F0059
00H
R/W
LCDPFmn
LCDPFmn register function (m = 0, 1, 3, 5, 7 to 9)
0
Used as port or alternate function other than segment output
1
Used as LCD segment signal output
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Figure 4-63. Format of LCD port function Register (4/5)
(100-pin products)
Symbol
7
6
5
4
3
2
1
0
Address After reset R/W
LCDPF0
LCDPF07 LCDPF06 LCDPF05 LCDPF04 LCDPF03 LCDPF02 LCDPF01 LCDPF00
F0050
00H
R/W
LCDPF1
LCDPF17 LCDPF16 LCDPF15 LCDPF14 LCDPF13 LCDPF12 LCDPF11 LCDPF10
F0051
00H
R/W
LCDPF3
LCDPF37 LCDPF36 LCDPF35 LCDPF34 LCDPF33 LCDPF32 LCDPF31 LCDPF30
F0053
00H
R/W
LCDPF5
LCDPF57 LCDPF56 LCDPF55 LCDPF54 LCDPF53 LCDPF52 LCDPF51 LCDPF50
F0055
00H
R/W
F0057
00H
R/W
LCDPF7
0
0
LCDPF75 LCDPF74 LCDPF73 LCDPF72
0
0
LCDPF8
LCDPF87 LCDPF86 LCDPF85 LCDPF84 LCDPF83 LCDPF82 LCDPF81 LCDPF80
F0058
00H
R/W
LCDPF9
LCDPF97 LCDPF96 LCDPF95 LCDPF94 LCDPF93 LCDPF92 LCDPF91 LCDPF90
F0059
00H
R/W
F005D
00H
R/W
LCDPF13
0
LCDPF136
LCDPFmn
0
0
0
0
0
0
LCDPFmn register function (m = 0, 1, 3, 5, 7 to 9, 13)
0
Used as port or alternate function other than segment output
1
Used as LCD segment signal output
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Figure 4-63. Format of LCD port function Register (5/5)
(128-pin products)
Symbol
7
6
5
4
3
2
1
0
Address After reset R/W
LCDPF0
LCDPF07 LCDPF06 LCDPF05 LCDPF04 LCDPF03 LCDPF02 LCDPF01 LCDPF00
F0050
00H
R/W
LCDPF1
LCDPF17 LCDPF16 LCDPF15 LCDPF14 LCDPF13 LCDPF12 LCDPF11 LCDPF10
F0051
00H
R/W
LCDPF3
LCDPF37 LCDPF36 LCDPF35 LCDPF34 LCDPF33 LCDPF32 LCDPF31 LCDPF30
F0053
00H
R/W
LCDPF4
LCDPF47 LCDPF46 LCDPF45 LCDPF44 LCDPF43 LCDPF42 LCDPF41 LCDPF40
F0054
00H
R/W
LCDPF5
LCDPF57 LCDPF56 LCDPF55 LCDPF54 LCDPF53 LCDPF52 LCDPF51 LCDPF50
F0055
00H
R/W
F0057
00H
R/W
LCDPF7
0
0
LCDPF75 LCDPF74 LCDPF73 LCDPF72
0
0
LCDPF8
LCDPF87 LCDPF86 LCDPF85 LCDPF84 LCDPF83 LCDPF82 LCDPF81 LCDPF80
F0058
00H
R/W
LCDPF9
LCDPF97 LCDPF96 LCDPF95 LCDPF94 LCDPF93 LCDPF92 LCDPF91 LCDPF90
F0059
00H
R/W
LCDPF10 LCDPF107 LCDPF106 LCDPF105 LCDPF104 LCDPF103 LCDPF102 LCDPF101 LCDPF100 F005A
00H
R/W
LCDPF11 LCDPF117 LCDPF116 LCDPF115 LCDPF114 LCDPF113 LCDPF112 LCDPF111 LCDPF110 F005B
00H
R/W
LCDPF12 LCDPF127 LCDPF126 LCDPF125
LCDPF13
0
LCDPF136
0
0
0
0
0
0
F005C
00H
R/W
0
0
0
0
0
F005D
00H
R/W
LCDPFmn
LCDPFmn register function (m = 0, 1, 3 to 5, 7 to 13)
0
Used as port or alternate function other than segment output
1
Used as LCD segment signal output
Caution For 128pin production, 24 SEGxx re-direction function by PF registers is supported. For example,
SEG47 can be output from P97 if setting PF97=1 or from P107 if setting PF107=1, but do not set
PF97=1 and PF107=1 at the same time otherwise both P97 and P107 can output same segment signal,
because there is not exlusive-active-control-logic for PF97=1 and PF107=1 at hardware, this case is
setting prohibited. See below:
SEG name
PF97
PF107
Function
SEG47
0
0
Both Port 97 and Port 107 are not used as LCD segment
0
1
Port 107 is used as LCD segment. Port 97 is not.
1
0
Port 97 is used as LCD segment. Port 107 is not.
1
1
Setting prohibited (Both Port 97 and Port 107 can output
segment signal)
About SEGxx that can be re-directed to output from two pins, see Table 4-22.
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Table 4-22. SEGxx re-direction function
SEG name
Ports
SEG name
Ports
SEG name
Ports
SEG7
P31
P42
SEG28
P17
P117
SEG36
P84
P100
SEG14
P00
P43
SEG29
P12
P116
SEG37
P85
P101
SEG15
P01
P44
SEG30
P11
P115
SEG38
P86
P102
SEG23
P15
P127
SEG31
P10
P114
SEG39
P87
P103
SEG24
P14
P126
SEG32
P80
P113
SEG44
P94
P104
SEG25
P13
P125
SEG33
P81
P112
SEG45
P95
P105
SEG26
P74
P47
SEG34
P82
P111
SEG46
P96
P106
SEG27
P75
P46
SEG35
P83
P110
SEG47
P97
P107
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(7) A/D port configuration register (ADPC)
This register switches the P20/ANI0/AVREFP to P27/ANI7, and P150/ANI8 to P152/ANI10 pins to digital I/O of port or
analog input of A/D converter.
The ADPC register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 4-64. Format of A/D port configuration Register
Symbol
7
6
5
4
3
2
ADPC
0
0
0
0
ADPC3
ADPC2
0
1
ADPC1
Address After reset R/W
F006E
ADPC0
00H
R/W
ANI2/P22
ANI1/AVREFM/P21
ANI0/AVREFP/P20
A
A
A
A
A
0
0
0
1
D
D
D
D
D
D
D
D
D
D
D
0
0
1
0
D
D
D
D
D
D
D
D
D
D
A
0
0
1
1
D
D
D
D
D
D
D
D
D
A
A
0
1
0
0
D
D
D
D
D
D
D
D
A
A
A
0
1
0
1
D
D
D
D
D
D
D
A
A
A
A
0
1
1
0
D
D
D
D
D
D
A
A
A
A
A
0
1
1
1
D
D
D
D
D
A
A
A
A
A
A
1
0
0
0
D
D
D
D
A
A
A
A
A
A
A
1
0
0
1
D
D
D
A
A
A
A
A
A
A
A
1
0
1
0
D
D
A
A
A
A
A
A
A
A
A
1
0
1
1
D
A
A
A
A
A
A
A
A
A
A
Other than the above
ANI4/P24
A
ANI5/P25
A
ANI6/P26
A
ANI7/P27
A
ANI8/P150
A
ANI9/P151
A
ANI10/P152
0
ADPC0
0
ADPC1
0
ADPC2
0
ADPC3
ANI3/P23
Analog input (A)/digital I/O (D) switching
Setting prohibited, all the channels ANI10-0 are alalog input on all hardware
sepecification
A(Analog): Digital functions (input/output) are disabled. PMmn setting is invalid.
D(Digital): Digital functions (input/output) are enabled. PMmn setting is valid.
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(8) Stepper motor port control register (SMPC)
This register sets the output mode of stepper motor controller/driver.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 4-65. Format of Stepper motor port control Register
Symbol
7
6
5
4
3
2
SMPC
MOD4
MOD3
MOD2
MOD1
EN4
EN3
ENk
MODk
0
-
0
1
EN2
EN1
Address After reset R/W
FFF3F
00H
R/W
Port mode selection (k = 1 to 4)
Port mode
All SMkm (m = 1 to 4) are set to port function
1
0
PWM full bridge mode
SMkm (m = 1 to 4) set to FULL bridge output control
1
1
2pin Stepper motor mode and 2pin Port Mode
SMkm set to PWM output control, depending on the DIRkn bit
SMkm, (m = 2n - 1) are in PWM output mode and
SMkm, (m = 2n) are in Port mode for DIRkn = 0,
SMkm, (m = 2n) are in PWM output mode and
SMkm, (m = 2n - 1) are in Port mode for DIRkn = 1
An example of settings when m = 1 is as follows:
EN1
MOD1
0
DIR11
-
DIR10
-
-
PWM Output Pin Control
Output Mode
SM11
SM12
SM13
SM14
(sin+)
(sin-)
(cos+)
(cos-)
port
port
port
port
Port mode
1
0
0
0
PWM
0
PWM
0
PWM mode
1
0
0
1
PWM
0
0
PWM
Full bridge
1
0
1
0
0
PWM
0
PWM
1
0
1
1
0
PWM
PWM
0
1
1
0
0
PWM
port
PWM
port
PWM mode
1
1
0
1
PWM
port
port
PWM
Half bridge
1
1
1
0
port
PWM
port
PWM
1
1
1
1
port
PWM
PWM
port
Caution
Set port registers (Pn) and port mode registers (PMn) to 00H, whose pins are in the PWM full bridge
mode.
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4.4 Port Function Operations
Port operations differ depending on whether the input or output mode is set, as shown below.
4.4.1 Writing to I/O port
(1) Output mode
A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
(2) Input mode
A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not
change.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
4.4.2 Reading from I/O port
(1) Output mode
The output latch contents are read by a transfer instruction. The output latch contents do not change.
(2) Input mode
The pin status is read by a transfer instruction. The output latch contents do not change.
4.4.3 Operations on I/O port
(1) Output mode
An operation is performed on the output latch contents, and the result is written to the output latch. The output latch
contents are output from the pins.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
(2) Input mode
The pin level is read and an operation is performed on its contents. The result of the operation is written to the output
latch, but since the output buffer is off, the pin status does not change.
The data of the output latch is cleared when a reset signal is generated.
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4.5 Settings of Registers, and Output Latch When Using Alternate Function
4.5.1 The relationship of alternate function and port
The alternate functions are connected to some port via selector. Figure 4-59 and 60 represent the connection of
alternate function and port.
Note: Noise filters and so on are omitted in these figures.
Figure 4-66. Timer Array unit and RTC I/O connection (128-pin products) (1/3)
TOTICON0
TAU0
TIS000
SEL
P00
P136
P110
TISEL
TIN0
TOUT0
Channel 0
TIS011, TIS010
P01
P80
P94
P104
TIN1
TOUT1
Channel 1
TIN2
TISEL
TOUT2
Channel 2
TOSEL
P01
P80
P94
P104
TOSEL
P02
P50
P105
P111
TOS031, TOS030
TIS031, TIS030
TIN3
TISEL
TOUT3
Channel 3
TIS041, TIS040
P04
P51
P112
P41
P00
P136
P110
TOS021, TOS020
TIS021, TIS020
P03
P81
P95
P70
TOSEL
TOS011, TOS010
TISEL
P02
P50
P105
P111
TOS001, TOS000
P03
P81
P95
P70
TOSEL
TOS041, TOS040
TIN4
TISEL
TOUT4
Channel 4
TOSEL
P04
P51
P112
P41
TIS051, TIS050 TI05SEL1,0
P05
P82
P96
P106
fIL
fSUB
fEX
TISEL
TOS051, TOS050
SEL
TIN5
TOUT5
Channel 5
TOSEL
P05
P82
P96
P106
RTCTIS00
TIS061, TIS060
P06
P52
P107
P113
TOS061, TOS060
SEL
TISEL
TIN6
TOUT6
Channel 6
RTCTIS01
P06
P52
P107
P113
TOS071, TOS070
TIS071, TIS070
P07
P83
P97
P114
TOSEL
SEL
TISEL
TIN7
TOUT7
Channel 7
TOSEL
P07
P83
P97
P114
RTCOSEL1, RTCOSEL0
RTC1HZ
RTC
RTCSEL
P64
P15
P94
RTC1HZ
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Figure 4-66. Timer Array unit and RTC I/O connection (128-pin products) (2/3)
TAU1
TIS101, TIS100
P10
P115
P42
TIN0
TISEL
Channel 0
TOUT0
TIS111, TIS110
P11
P84
P140
P64
TISEL
Channel 1
TOUT1
TIS121, TIS120
P10
P115
P42
TOSEL
P11
P84
P140
P64
TOS121, TOS120
TIN2
TISEL
Channel 2
TOUT2
TOSEL
P12
P02
P125
P116
TOS131, TOS130
TIS131, TIS130
P13
P03
P53
P85
TOSEL
TOS111, TOS110
TIN1
P12
P02
P125
P116
TOS101, TOS100
TIN3
TISEL
Channel 3
TOUT3
Channel 4
TOUT4
P13
P03
P53
P85
TOSEL
TIS141, TIS140 TMCAN0
P14
P04
TISEL
P54
P126
TSOUT
(aFCAN0)
TIS151, TIS150
P15
P05
TISEL
P55
P86
TSOUT
(aFCAN1)
TOS141, TOS140
TIN4
SEL
TOSEL
P14
P04
P54
P126
TMCAN1
TOS151, TOS150
SEL
TIN5
Channel 5
TOUT5
P15
P05
P55
P86
TOSEL
RTCTIS10
RTC1HZ
TIS161, TIS160
P16
P06
P56
P127
TOS161, TOS160
SEL
TISEL
TIN6
Channel 6
TOUT6
RTCTIS11
SEL
TISEL
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P06
P56
P127
TOS171, TOS170
TIS171, TIS170
P17
P07
P87
P57
TOSEL
TIN7
Channel 7
TOUT7
TOSEL
P17
P07
P87
P57
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Figure 4-66. Timer Array unit and RTC I/O connection (128-pin products) (3/3)
TOTICON1
TAU2
TIS201, TIS200
P60
P30
P132
P117
SEL
TISEL
TIN0
Channel 0
TOUT0
TIS211, TIS210
P61
P31
P131
P90
TISEL
TISEL
Channel 1
TOUT1
TISEL
Channel 2
TOUT2
TISEL
TIN3
Channel 3
TOUT3
TISEL
Channel 4
TOUT4
TISEL
TIN5
Channel 5
TOUT5
TISEL
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P32
P133
P43
P74
P33
P91
P44
TOSEL
TOSEL
P66
P34
P134
P100
TOSEL
P65
P92
P35
P101
TOS261, TOS260
TIN6
Channel 6
TOUT6
TOSEL
P36
P63
P135
P102
TOS271, TOS270
TIS271, TIS270
P93
P62
P37
P103
TOSEL
TOS251, TOS250
TIS261, TIS260
P63
P36
P135
P102
P61
P31
P131
P90
TOS241, TOS240
TIN4
TIS251, TIS250
P65
P92
P35
P101
TOSEL
TOS231, TOS230
TIS241, TIS240
P66
P34
P134
P100
P60
P30
P132
P117
TOS221, TOS220
TIN2
TIS231, TIS230
P74
P33
P91
P44
TOSEL
TOS211, TOS210
TIN1
TIS221, TIS220
P75
P32
P133
P43
TOS201, TOS200
TIN7
Channel 7
TOUT7
TOSEL
P93
P37
P62
P103
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Figure 4-67. Serial unit, SG, and PCL connection (128-pin products) (1/2)
SUARTF0
LTxD0
P71/LTxD0
P70/LRxD0/INTPLR
STSEL
LRxD0
LIN-UART0
P15/LTxD0
P14/LRxD0/INTPLR
EGIN6
INTC
EGIN7
SUARTF1
LTxD1
P10/LTxD1
P11/LRxD1/INTPLR
STSEL
LRxD1
LIN-UART1
P131/LTxD1
P132/LRxD1/INTPL
SCAN0
CTxD0
P71/CTxD0
P70/CRxD0
STSEL
CRxD0
aFCAN0
TSOUT
P00/CTxD0
P01/CRxD0
SCAN1
CTxD1
P62/CTxD1
P63/CRxD1
STSEL
CRxD1
aFCAN1
TSOUT
P134/CTxD1
P135/CRxD1
SAU0
SCSI001, SCSI000
P10/SCK00
P11/SI00/RxD0
P12/SO00/TxD0
P04/SCK00
P03/SI00/RxD0
P02/SO00/TxD0
SCK00
SI00
SO00
CSI00
STSEL
RxD0
TxD0
P34/SCK00
P33/SI00/RxD0
P32/SO00/TxD0
UART0
SCSI010
P74/SCK01
P75/SI01
P13/SO01
STSEL
SCK01
SI01
SO01
CSI01
P56/SCK01
P55/SI01
P54/SO01
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Figure 4-67. Serial unit, SG, and PCL connection (128-pin products) (2/2)
SAU1
SCSI100
P133/SCK10
P132/SI10
P131/SO10
STSEL
SCK10
SI10
SO10
CSI10
P51/SCK10
P52/SI10
P53/SO10
SIIC1, SIIC0
P60/SCL11
P61/SDA11
P30/SCL11
P31/SDA11
STSEL
SCL11
SDA11
IIC11
P136/SCL11
P50/SDA11
SGSEL1, SGSEL0
P73/SGO
P72/SGOA
SGO
P93/SGO
P92/SGOA
SGOA
Sound
Generator
PCL
PCLBUZ
SGSEL
P135/SGO
P134/SGOA
PCLSEL
P75/PCL
SGSEL
P66/PCL
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4.5.2 Expanded Control Register of Port Function
(1) Timer input select register (TIS00, TIS01, TIS10, TIS11, TIS20, TIS21)
These registers are used for alternate switch of TAU input pins. TIS00 ~ TIS01 is for TAU unit0, TIS10~ TIS11 for
TAU unit1, TIS20~ TIS21 for TAU unit2.
Figure 4-68. Format of TIS00 and TIS01 Registers (128-pin products) (1/2)
Symbol
7
6
5
4
3
2
1
0
TIS00
TIS031
TIS030
TIS021
TIS020
TIS011
TIS010
TIS001
TIS000
F0070
00H
R/W
TIS01
TIS071
TIS070
TIS061
TIS060
TIS051
TIS050
TIS041
TIS040
F0071
00H
R/W
TIS001
TIS000
TI00 (TAU unit0 CH0) alternate pin selection
0
0
P00
0
1
P136
1
0
P110
Other than the above
Address After reset R/W
Setting prohibited (same as “00” setting)
TIS011
TIS010
TI01 (TAU unit0 CH1) alternate pin selection
0
0
P01
0
1
P80
1
0
P94
1
1
P104
TIS021
TIS020
0
0
0
1
P50
1
0
P105
1
1
P111
TIS031
TIS030
0
0
P03
0
1
P81
1
0
P95
1
1
P70
TIS041
TIS040
0
0
P04
0
1
P51
1
0
P112
1
1
P41
TIS051
TIS050
0
0
P05
0
1
P82
TI02 (TAU unit0 CH2) alternate pin selection
P02
TI03 (TAU unit0 CH3) alternate pin selection
TI04 (TAU unit0 CH4) alternate pin selection
TI05 (TAU unit0 CH5) alternate pin selection
1
0
P96
1
1
P106
TIS061
TIS060
0
0
0
1
P52
1
0
P107
1
1
P113
TI06 (TAU unit0 CH6) alternate pin selection
P06
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Figure 4-68. Format of TIS00 and TIS01 Registers (128-pin products) (2/2)
Symbol
7
6
5
4
3
2
1
0
TIS00
TIS031
TIS030
TIS021
TIS020
TIS011
TIS010
TIS001
TIS000
F0070
00H
R/W
TIS01
TIS071
TIS070
TIS061
TIS060
TIS051
TIS050
TIS041
TIS040
F0071
00H
R/W
TIS071
TIS070
0
0
P07
0
1
P83
1
0
P97
1
1
P114
Address After reset R/W
TI07 (TAU unit0 CH7) alternate pin selection
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Figure 4-69. Format of TIS10 and TIS11 Registers (128-pin products) (1/2)
Symbol
7
6
5
4
3
2
1
0
TIS10
TIS131
TIS130
TIS121
TIS120
TIS111
TIS110
TIS101
TIS100
F0072
00H
R/W
TIS11
TIS171
TIS170
TIS161
TIS160
TIS151
TIS150
TIS141
TIS140
F0073
00H
R/W
TIS111
TIS110
0
0
Address After reset R/W
TI11 (TAU unit1 CH1) alternate pin selection
P11
0
1
P84
1
0
P140
1
1
P64
TIS121
TIS120
0
0
P12
0
1
P02
1
0
P125
1
1
P116
TIS131
TIS130
0
0
P13
0
1
P03
1
0
P53
1
1
P85
TIS141
TIS140
0
0
P14
0
1
P04
1
0
P54
1
1
P126
TIS151
TIS150
0
0
P15
0
1
P05
1
0
P55
1
1
P86
TIS161
TIS160
0
0
P16
0
1
P06
1
0
P56
1
1
P127
TI12 (TAU unit1 CH1) alternate pin selection
TI13 (TAU unit1 CH3) alternate pin selection
TI14 (TAU unit1 CH4) alternate pin selection
TI15 (TAU unit1 CH5) alternate pin selection
TI16 (TAU unit1 CH6) alternate pin selection
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Figure 4-69. Format of TIS10 and TIS11 Registers (128-pin products) (2/2)
Symbol
7
6
5
4
3
2
1
0
TIS10
TIS131
TIS130
TIS121
TIS120
TIS111
TIS110
TIS101
TIS100
F0072
00H
R/W
TIS11
TIS171
TIS170
TIS161
TIS160
TIS151
TIS150
TIS141
TIS140
F0073
00H
R/W
TIS171
TIS170
0
0
P17
0
1
P07
1
0
P87
1
1
P57
Address After reset R/W
TI17 (TAU unit1 CH7) alternate pin selection
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Figure 4-70. Format of TIS20 and TIS21 Registers (128-pin products) (1/2)
Symbol
7
6
5
4
3
2
1
0
TIS20
TIS231
TIS230
TIS221
TIS220
TIS211
TIS210
TIS201
TIS200
F0074
00H
R/W
TIS21
TIS271
TIS270
TIS261
TIS260
TIS251
TIS250
TIS241
TIS240
F0075
00H
R/W
TIS201
TIS200
0
0
Address After reset R/W
TI21 (TAU unit2 CH1) alternate pin selection
P60
0
1
P30
1
0
P132
1
1
P117
TIS211
TIS210
0
0
TI21 (TAU unit2 CH1) alternate pin selection
P61
0
1
P31
1
0
P131
1
1
P90
TIS221
TIS220
0
0
P75
0
1
P32
1
0
P133
1
1
P43
TIS231
TIS230
0
0
P74
0
1
P33
1
0
P91
1
1
P44
TIS241
TIS240
0
0
TI22 (TAU unit2 CH2) alternate pin selection
TI23 (TAU unit2 CH3) alternate pin selection
TI24 (TAU unit2 CH4) alternate pin selection
P66
0
1
P34
1
0
P134
1
1
P100
TIS251
TIS250
0
0
P65
0
1
P92
1
0
P35
1
1
P101
TIS261
TIS260
0
0
P63
0
1
P36
1
0
P135
1
1
P102
TI25 (TAU unit2 CH5) alternate pin selection
TI26 (TAU unit2 CH6) alternate pin selection
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Figure 4-70. Format of TIS20 and TIS21 Registers (128-pin products) (2/2)
Symbol
7
6
5
4
3
2
1
0
TIS20
TIS231
TIS230
TIS221
TIS220
TIS211
TIS210
TIS201
TIS200
F0074
00H
R/W
TIS21
TIS271
TIS270
TIS261
TIS260
TIS251
TIS250
TIS241
TIS240
F0075
00H
R/W
TIS271
TIS270
0
0
P93
0
1
P62
1
0
P37
1
1
P103
Address After reset R/W
TI27 (TAU unit2 CH7) alternate pin selection
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(2) Timer output select register (TOS00, TOS01, TOS10, TOS11, TOS20, TOS21)
These registers are used for alternate switch of TAU output pins. TOS00 to TOS01 is for TAU unit0, TOS10 to TOS11
for TAU unit1, TOS20 to TOS21 for TAU unit2.
Figure 4-71. Format of TOS00 and TOS01 Registers (128-pin products) (1/2)
Symbol
7
6
5
4
3
2
1
0
Address After reset R/W
TOS00 TOS031 TOS030 TOS021 TOS020 TOS011 TOS010 TOS001 TOS000
F0076
00H
R/W
TOS01 TOS071 TOS070 TOS061 TOS060 TOS051 TOS050 TOS041 TOS040
F0077
00H
R/W
TOS001
TIS000
0
0
P00
0
1
P136
1
0
P110
Other than the above
TO00 (TAU unit0 CH0) alternate pin selection
Setting prohibited (same as “00” setting)
TOS011
TOS010
TO01 (TAU unit0 CH1) alternate pin selection
0
0
P01
0
1
P80
1
0
P94
1
1
P104
TOS021
TOS020
0
0
P02
0
1
P50
1
0
P105
1
1
P111
TOS031
TOS030
0
0
P03
0
1
P81
1
0
P95
1
1
P70
TOS041
TOS040
0
0
TO02 (TAU unit0 CH2) alternate pin selection
TO03 (TAU unit0 CH3) alternate pin selection
TO04 (TAU unit0 CH4) alternate pin selection
P04
0
1
P51
1
0
P112
1
1
P41
TOS051
TOS050
0
0
P05
0
1
P82
1
0
P96
1
1
P106
TO05 (TAU unit0 CH5) alternate pin selection
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Figure 4-71. Format of TOS00 and TOS01 Registers (128-pin products) (2/2)
Symbol
7
6
5
4
3
2
1
0
Address After reset R/W
TOS00 TOS031 TOS030 TOS021 TOS020 TOS011 TOS010 TOS001 TOS000
F0076
00H
R/W
TOS01 TOS071 TOS070 TOS061 TOS060 TOS051 TOS050 TOS041 TOS040
F0077
00H
R/W
TOS061
TOS060
0
0
TO06 (TAU unit0 CH6) alternate pin selection
P06
0
1
P52
1
0
P107
1
1
P113
TOS071
TOS070
0
0
P07
0
1
P83
1
0
P97
1
1
P114
TO07 (TAU unit0 CH7) alternate pin selection
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Figure 4-72. Format of TOS10 and TOS11 Registers (128-pin products) (1/2)
Symbol
7
6
5
4
3
2
1
0
Address After reset R/W
TOS10 TOS131 TOS130 TOS121 TOS120 TOS111 TOS110 TOS101 TOS100
F0079
00H
R/W
TOS11 TOS171 TOS170 TOS161 TOS160 TOS151 TOS150 TOS141 TOS140
F007A
00H
R/W
TOS101
TOS100
0
0
P10
0
1
P115
1
0
P42
Other than the above
TO10 (TAU unit1 CH0) alternate pin selection
Setting prohibited (same as “00” setting)
TOS111
TOS110
TO11 (TAU unit1 CH1) alternate pin selection
0
0
P11
0
1
P84
1
0
P140
1
1
P64
TOS121
TOS120
0
0
P12
0
1
P02
1
0
P125
1
1
P116
TOS131
TOS130
0
0
P13
0
1
P03
1
0
P53
1
1
P85
TOS141
TOS140
0
0
P14
0
1
P04
1
0
P54
1
1
P126
TOS151
TOS150
0
0
P15
0
1
P05
1
0
P55
1
1
P86
TOS161
TOS160
0
0
P16
0
1
P06
TO12 (TAU unit1 CH2) alternate pin selection
TO13 (TAU unit1 CH3) alternate pin selection
TO14 (TAU unit1 CH4) alternate pin selection
TO15 (TAU unit1 CH5) alternate pin selection
TO16 (TAU unit1 CH6) alternate pin selection
1
0
P56
1
1
P127
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Figure 4-72. Format of TOS10 and TOS11 Registers (128-pin products) (2/2)
Symbol
7
6
5
4
3
2
1
0
Address After reset R/W
TOS10 TOS131 TOS130 TOS121 TOS120 TOS111 TOS110 TOS101 TOS100
F0079
00H
R/W
TOS11 TOS171 TOS170 TOS161 TOS160 TOS151 TOS150 TOS141 TOS140
F007A
00H
R/W
TOS171
TOS170
TO17 (TAU unit1 CH7) alternate pin selection
0
0
P17
0
1
P07
1
0
P87
1
1
P57
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Figure 4-73. Format of TOS20 and TOS21 Registers (128-pin products) (1/2)
Symbol
7
6
5
4
3
2
1
0
TOS20 TOS231 TOS230 TOS221 TOS220 TOS211 TOS210 TOS201 TOS200
Address After reset R/W
F007B
00H
R/W
TOS21 TOS271 TOS270 TOS261 TOS260 TOS251 TOS250 TOS241 TOS240 F007C
00H
R/W
TOS201
TOS200
0
0
TO20 (TAU unit2 CH0) alternate pin selection
P60
0
1
P30
1
0
P132
1
1
P117
TOS211
TOS210
0
0
TO21 (TAU unit2 CH1) alternate pin selection
P61
0
1
P31
1
0
P131
1
1
P90
TOS221
TOS220
0
0
P75
0
1
P32
1
0
P133
1
1
P43
TOS231
TOS230
0
0
P74
0
1
P33
1
0
P91
1
1
P44
TOS241
TOS240
0
0
TO22 (TAU unit2 CH2) alternate pin selection
TO23 (TAU unit2 CH3) alternate pin selection
TO24 (TAU unit2 CH4) alternate pin selection
P66
0
1
P34
1
0
P134
1
1
P100
TOS251
TOS250
0
0
P65
0
1
P92
1
0
P35
1
1
P101
TOS261
TOS260
0
0
P36
0
1
P63
1
0
P135
1
1
P102
TO25 (TAU unit2 CH5) alternate pin selection
TO26 (TAU unit2 CH6) alternate pin selection
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Figure 4-73. Format of TOS20 and TOS21 Registers (128-pin products) (2/2)
TOS271
TOS270
0
0
P93
TO27 (TAU unit2 CH7) alternate pin selection
0
1
P37
1
0
P62
1
1
P103
Considering direct LED driving, or other large current application, 16-bit resolution PWM outputs are also alternated to
the SM pins. When configure pin function, the policy is that odd TO (ch1,3,5,7) of TAU should be output with higher priority.
In addition, 4 kinds of output with different periods using different master CH’s can be achieved if by this means.
(3) Timer input select else register (TISELSE)
This register provides below selection function.
(a) TAU unit 0 channel5 input selection
The input source can be timer input signal (TI05) from port or internal/external clock.
(b) Timer conjunction function of timer output to timer input just like 78K0/Dx2.
TAU unit0 CH1 output can be connected to TAU unit0 CH0. This function is controlled by bit6.
TAU unit2 CH1 output can be connected to TAU unit2 CH0. This function is controlled by bit7.
This function is used for measuring speed or taco pulse. If only use timer caupture function to measure, there will
be too many interrupts and increase the loading of software when input is higher (about 8kHz, 125us interrupt
interval). So division of interrupt is necessary. At this usage, one timer is used as capture mode, its output is
internally connected to another timer (operated as external event mode) to generate divided interrupt.
(Refer to TMP2 and TMP3 conjunction function of 78K0/Dx2)
Figure 4-74. Format of TISELSE Registers
Address: FFF3E
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
TISELSE
TOTICON1
TOTICON0
0
0
0
0
TI05SEL1
TI05SEL0
TI05SEL1
TI05SEL0
TIS051
TIS050
0
0
0
0
P05
0
0
0
1
P82
0
0
1
0
P96
0
1
x
x
Low-speed on-chip clock (fIL)
1
0
x
x
Sub system clock (fSUB)
1
1
x
x
Main external clock (fEX)
Other than the above
TAU unit0 CH5 input alternate selection
Setting prohibited (same as “0000” setting)
Considering the below purposes, every peripheral clock is connected to TI05 of TAU0
Low-speed on-chip clock: For Frequency Detection of Safefy Function.
Sub system clock:
External main clock: For the ultra accuracy trimming of high-speed on-chip oscillator without sub system clock Note
For the ultra accuracy trimming of high-speed on-chip oscillator Note
Note Count present operation frequency by timer. It is possible to change trimming code by access HIOTRM register.
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TOTICON0
Timer conjunction function control
0
Cut off the connection of TAU unit0 CH1 output to CH0 input
1
Connect TAU unit0 CH1 output to TAU unit0 CH0 input
TOTICON1
Timer conjunction function control
0
Cut off the connection of TAU unit2 CH1 output to CH0 input
1
Connect TAU unit2 CH1 output to TAU unit2 CH0 input
The connection with TOTICONn is used to count external event (pulse) input to TI01/TI21 in long term such as 16-bit
counter is overflowed. Timer array unit 0 channel 1/timer array unit 2 channel 1 is worked as divider of input pulse and
generates slower pulse to TO01/TO21. Timer array unit 0 channel 0/timer array unit 2 channel 0 is worked as external
event counter. Its expected value should be made the calculated value according to timer array unit 0 channel 1/timer
array unit 2 channel 1 divider setting.
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(4) Serial communication pin select register (STSEL0, STSEL1)
These registers are used for alternate switch of serial input/output pins.
Figure 4-75. Format of STSEL0 Register
Address: FFF3C
After reset: 00H
R/W
Symbol
7
5
STSEL0
0
SCSI100
0
SCSI010
SCSI001
SCSI000
SUARTF1
SUARTF0
Communication pin selection of UARTF0
SUARTF0
LTxD0
LRxD0
0
P71
P70
1
P15
P14
Communication pin selection of UARTF1
SUARTF1
LTxD1
LRxD1
0
P10
P11
1
P131
P132
SCSI001
SCSI000
CSI00 communication pin selection
SCK00
SI00
SO00
0
0
P10
P11
P12
0
1
P04
P03
P02
1
0
P34
1
0
P110
P33
Note
P111
P32
Note
P112
Note
Note 128-pin products only (same as "00" setting for other products).
SCSI010
CSI01 communication pin selection
SCK01
SI01
SO01
0
P74
P75
P13
1
P56
P55
P54
SCSI100
CSI10 communication pin selection
SCK10
SI10
SO10
0
P133
P132
P131
1
P51
P52
P53
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Figure 4-76. Format of STSEL1 Register
Address: FFF3D
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
STSEL1
SIIC1
SIIC0
0
0
SCAN1
SCAN0
TMCAN1
TMCAN0
TMCAN0
Input source switch of TAU unit1 CH4
0
Input from TI14 (after selected by TIS141~0 bits)
1
TSOUT of aFCAN0 (CAN0 time stamp function)
TMCAN1
Input source switch of TAU unit1 CH5
0
Input from TI15 (after selected by TIS151~0 bits)
1
TSOUT of aFCAN1 (CAN1 time stamp function)
SCAN0
Communication pin selection of aFCAN0
CTxD0
CRxD0
0
P71
P70
1
P00
P01
SCAN1
Communication pin selection of aFCAN1
CTxD1
CRxD1
0
P62
P63
1
P134
P135
SIIC1
SIIC0
Communication pin selection of IIC11
SCL11
SDA11
0
0
P60
P61
0
1
P30
P31
1
0
P136
P50
Other than the above
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(5) Sound generator and PCL pin select register (SGSEL)
This register is used for alternate switch of sound generator and PCL output pins.
SGOA output can be stopped when it is not used if SGSEL_2 is set to “1”.
Figure 4-77. Format of SGSEL Register
Address: FFF3F
After reset: 00H
R/W
Symbol
7
6
5
4
2
1
0
SGSEL
0
0
0
0
PCLSEL
SGSEL2
SGSEL1
SGSEL0
SGSEL2
SGSEL1
SGSEL0
Pin select of sound generator outputs
SGO/SGOF
SGOA
0
0
0
P73
P72
0
0
1
P93
P92
0
1
0
P135
P134
0
1
1
Setting prohibit
1
0
0
P73
No port is selected
1
0
1
P93
(output disabled)
1
1
0
P135
1
1
1
Setting prohibit
Note: The driving capability of SGO/SGOF alternate pin (P73, P93, P135) is larger than normal buffer.
P93 is also alternated as Stepper-Motor function, so its driving characteristics is the same as SM buffer.
P73 and P135 are the same as SG buffer of 78K0/Dx2.
PCLSEL
PCL output pin selection
0
P75 (default, be available for 48/64/80/100pin)
1
P66 (option for 80/100pin)
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(6) RTC1HZ pin select register (RTCSEL)
This register includes two kinds of control function.
- Control of switching RTC1Hz output to TAU TI input.
- Control of switching RTC1Hz output to different port.
Figure 4-78. Format of RTCSEL Register
Address: FFF36
Symbol
RTCSEL
After reset: 00H
R/W
5
4
RTCOSEL1
RTCOSEL0
0
0
RTCTIS11
RTCTIS10
RTCTIS01
RTCTIS00
RTCTIS00
Switch RTC1Hz output to TAU TI06 input or not
0
Disconnected to TI06
1
Connected to TI06
RTCTIS01
Switch RTC1Hz output to TAU TI07 input or not
0
Disconnected to TI07
1
Connected to TI07
RTCTIS10
Switch RTC1Hz output to TAU TI16 input or not
0
Disconnected to TI16
1
Connected to TI16
RTCTIS11
Switch RTC1Hz output to TAU TI17 input or not
0
Disconnected to TI17
1
Connected to TI17
RTCOSEL1
RTCOSEL0
RTC1Hz output pin selection
0
0
P64
0
1
P15
1
0
P94
1
1
No port is selected (Output disabled)
To measure 1Hz, two channels of TAU should be used because 16-bit counter will be overflowed if FCLK is fast
frequency. A channel is operated in pulse width measurement mode. Low-level or high-level width of 1Hz pulse is typically
500ms. Another channel is operated in interval timer mode (start trigger is set to TIN edge) and number of overflow should
be counted by software at the interrupt timing. The measurement is finished when interrupt by capture channel is occurred.
The interval time can be calculated by software-overflow-counter and TDR register of capture channel.
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4.5.3 The setting to use alternate function
To use the alternate function of a port pin, set the port mode register, output latch, port output mode register, LCD port
function register, A/D port configuration register, and Stepper motor port mode control register as shown in Table 4-23.
Table 4-23. Settings of Register, and Output Latch When Using Alternate Function (1/16)
(a) Alternate function of P0 (1/2)
Alternate function
port
Function
name
P00
TI00
I/O
Input
Expanded control setting (Register.bit)
PMxx
Pxx
LCDPFxx
1
x
0
Enable function
TIS00.0 = 0
Disable other function
-
TISELSE.6 = 0
P01
P02
TO00
Output
0
0
0
TOS00.0 = 0
CTxD0
Output
0
1
0
STSEL1.2 = 1
SEG14
Output
x
x
1
TI01
Input
1
x
0
TIS00.3,2 = 00
-
TO01
Output
0
0
0
TOS00.3,2 = 00
-
CRxD0
Input
1
x
0
STSEL1.2 = 1
-
SEG15
Output
x
x
1
TI02
Input
1
x
0
TIS00.4 = 0
TO02
Output
0
0
0
TOS00.4 = 0
-
-
STSEL1.2 = 0
-
STSEL0.3,2 = 00/10
TOS10.4 = 0
TI12
Input
1
x
0
TIS10.4 = 1
TO12
Output
0
0
0
TOS10.4 = 1
STSEL0.3,2 = 00/10
TOS00.4 = 0
P03
P04
SO00
Output
0
1
0
SEG16
Output
x
x
1
TI03
Input
1
x
0
STSEL0.3,2 = 01
TIS00.7,6 = 00
TO03
Output
0
0
0
TOS00.7,6 = 00
TI13
Input
1
x
0
TIS10.7,6 = 01
TO13
Output
0
0
0
TOS10.7,6 = 01
SI00
Input
1
x
0
STSEL0.3,2 = 01
SEG17
Output
x
x
1
TI04
Input
1
x
0
TIS01.0 = 0
TO04
Output
0
0
0
TOS01.0 = 0
-
TOS10.7,6 = 00/10/11
TOS00.7,6 = 01/10/11
-
STSEL0.3,2 = 00/10
TOS11.1,0 = 00/10
TI14
Input
1
x
0
TIS11.1,0 = 01
-
STSEL1.0 = 0
TO14
Output
0
0
0
TOS11.1,0 = 01
SCK00
Output
0
1
0
STSEL0.3,2 = 01
Input
1
x
STSEL0.3,2 = 00/10
TOS01.0 = 1
P05
SEG18
Output
x
x
1
TI05
Input
1
x
0
TIS01.3,2 = 00
-
TISELSE.1,0 = 00
TO05
Output
0
0
0
TOS01.3,2 = 00
TI15
Input
1
x
0
TIS11.3,2 = 01
TOS11.3,2 = 00/10/11
-
STSEL1.1 = 0
TO15
Output
0
0
0
SEG19
Output
x
x
1
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-
TOS01.3,2 = 01/10
-
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Table 4-23. Settings of Register, and Output Latch When Using Alternate Function (2/16)
(a) Alternate function of P0 (2/2)
Alternate function
port
Function
name
P06
TI06
Expanded control setting (Register.bit)
PMxx
Pxx
LCDPFxx
I/O
Input
Enable function
1
x
0
TIS01.4 = 0
Disable other function
-
RTCSEL.0 = 0
TO06
Output
0
0
0
TI16
Input
1
x
0
TOS01.4 = 0
TIS11.5,4 = 01
TOS11.5,4 = 00/10
-
RTCSEL.2 = 0
P07
TO16
Output
0
0
0
SEG20
Output
x
x
1
TI07
Input
1
x
0
TOS11.5,4 = 01
TIS01.7,6 = 00
TOS01.4 = 1
-
RTCSEL.1 = 0
TO07
Output
0
0
0
TOS01.7,6 = 00
TI17
Input
1
x
0
TIS11.7,6 = 01
TOS11.7,6 = 00/10/11
-
RTCSEL.3 = 0
TO17
Output
0
0
0
SEG21
Output
x
x
1
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-
TOS01.7,6 = 01/10
-
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Table 4-23. Settings of Register, and Output Latch When Using Alternate Function (3/16)
(b) Alternate function of P1 (1/2)
Alternate function
port
P10
Function
name
I/O
Expanded control setting (Register.bit)
PMxx
Pxx
LCDPFxx
Enable function
Disable other function
INTP4
Input
1
x
0
-
-
TI10
Input
1
x
0
-
-
TO10
Output
0
0
0
-
STSEL0.1 = 1
STSEL0.3,2 = 01/10
P11
P12
P13
P14
LTxD1
Output
0
1
0
SCK00
STSEL0.1 = 0
STSEL0.3,2 = 01/10
Output
0
1
0
Input
1
x
SEG31
Output
x
x
INTPLR1
Input
1
x
0
STSEL0.1 = 0
-
TI11
Input
1
x
0
TIS10.3,2 = 00
-
STSEL0.3,2 = 00
1
STSEL0.1 = 1
-
-
-
TO11
Output
0
0
0
TOS10.3,2 = 00
-
LRxD1
Input
1
x
0
STSEL0.1 = 0
-
SI00
Input
1
x
0
STSEL0.3,2 = 00
-
SEG30
Output
x
x
1
-
-
INTP2
Input
1
x
0
-
-
TI12
Input
1
x
0
TIS10.4 = 0
TO12
Output
0
0
0
TOS10.4 = 0
STSEL0.3,2 = 01/10
SO00
Output
0
1
0
STSEL0.3,2 = 00
TOS10.4 = 1
-
SEG29
Output
x
x
1
-
-
TI13
Input
1
x
0
TIS10.7,6 = 00
-
TO13
Output
0
0
0
TOS10.7,6 = 00
STSEL0.4 = 1
SO01
Output
0
1
0
STSEL0.4 = 0
TOS10.7,6 = 01/10/11
SEG25
Output
x
x
1
INTPLR0
Input
1
x
0
STSEL0.0 = 1
-
TI14
Input
1
x
0
TIS11.1,0 = 00
-
TO14
Output
0
0
0
TOS11.1,0 = 00
-
LRxD0
Input
1
x
0
STSEL0.0 = 1
-
SEG24
Output
x
x
1
-
-
TI15
Input
1
x
0
TIS11.3,2 = 00
-
-
-
STSEL1.0 = 0
P15
STSEL1.1 = 0
P16
TO15
Output
0
0
0
RTC1HZ
Output
0
0
0
LTxD0
Output
0
1
0
TOS11.3,2 = 00
RTCSEL.7,6 = 01
RTCSEL.7,6 = 00/10/11
STSEL0.0 = 0
TOS11.3,2 = 01/10/11
STSEL0.0 = 0
TOS11.3,2 = 01/10/11
STSEL0.0 = 1
RTCSEL.7,6 = 00/10/11
SEG23
Output
x
x
1
-
-
TI16
Input
1
x
0
TIS11.5,4 = 00
-
RTCSEL.2 = 0
TO16
Output
0
0
0
SEG22
Output
x
x
1
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Table 4-23. Settings of Register, and Output Latch When Using Alternate Function (4/16)
(b) Alternate function of P1 (2/2)
Alternate function
port
Function
name
P17
Expanded control setting (Register.bit)
PMxx
Pxx
LCDPFxx
I/O
INTP0
Input
1
x
0
TI17
Input
1
x
0
Enable function
Disable other function
-
-
TIS11.7,6 = 00
-
RTCSEL.3 = 0
TO17
Output
0
0
0
TOS11.7,6 = 00
SEG28
Output
x
x
1
-
PMxx
Pxx
STSEL0.3,2 = 01/10
-
(c) Alternate function of P2
Alternate function
port
Function name
P20
ADPC
(bit 3 to 0)
I/O
AVREFP
Input
-
-
ANI0
Input
-
-
P21
AVREFM
Input
-
-
ANI1
Input
-
-
P22
ANI2
Input
-
-
0000/0100 to 1001
P23
ANI3
Input
-
-
0000/0101 to 1001
P24
ANI4
Input
-
-
0000/0110 to 1001
P25
ANI5
Input
-
-
0000/0111 to 1001
P26
ANI6
Input
-
-
0000/1000/1001
P27
ANI7
Input
-
-
0000/1001
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0000/0011 to 1001
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Table 4-23. Settings of Register, and Output Latch When Using Alternate Function (5/16)
(d) Alternate function of P3
Alternate function
port
Function
name
P30
TI20
Expanded control setting (Register.bit)
PMxx
Pxx
LCDPFxx
I/O
Input
Enable function
1
x
0
TIS20.1,0 = 01
Disable other function
-
TISELSE.7 = 0
P31
P32
P33
P34
P35
P36
P37
TO20
Output
0
0
0
TOS20.1,0 = 01
STSEL1.7,6 = 00/10
SCL11
Output
0
SEG6
Output
x
1
0
STSEL1.7,6 = 01
TOS20.1,0 = 00/10
x
1
TI21
Input
1
x
0
TIS20.3,2 = 01
TO21
Output
0
0
0
TOS20.3,2 = 01
STSEL1.7,6 = 00/10
SDA11
I/O
0
1
0
STSEL1.7,6 = 01
TOS20.3,2 = 00/10/11
SEG7
Output
x
x
1
TI22
Input
1
x
0
TIS20.5,4 = 01
TO22
Output
0
0
0
TOS20.5,4 = 01
STSEL0.3,2 = 00/01
SO00
Output
0
1
0
STSEL0.3,2 = 10
TOS20.5,4 = 00/10
TxD0
Output
0
1
0
STSEL0.3,2 = 10
TOS20.5,4 = 00/10
SEG8
Output
x
x
1
TI23
Input
1
x
0
TIS20.7,6 = 01
TO23
Output
0
0
0
TOS20.7,6 = 01
STSEL0.3,2 = 00/01
SI00
Input
1
x
0
STSEL0.3,2 = 10
TOS20.7,6 = 00/10
RxD0
Input
1
x
0
STSEL0.3,2 = 10
TOS20.7,6 = 00/10
SEG9
Output
x
x
1
TI24
Input
1
x
0
TIS21.1,0 = 01
TO24
Output
0
0
0
TOS21.1,0 = 01
STSEL0.3,2 = 00/01
SCK00
Output
0
1
0
STSEL0.3,2 = 10
TOS21.1,0 = 00/10
Input
1
x
SEG10
Output
x
x
1
TI25
Input
1
x
0
TIS21.3,2 = 10
TO25
Output
0
0
0
TOS21.3,2 = 10
SEG11
Output
x
x
1
TI26
Input
1
x
0
TIS21.5,4 = 01
-
TO26
Output
0
0
0
TOS21.5,4 = 00
-
SEG12
Output
x
x
1
TI27
Input
1
x
0
TIS21.7,6 = 10
-
TO27
Output
0
0
0
TOS21.7,6 = 01
-
SEG13
Output
x
x
1
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-
-
-
-
-
-
-
-
-
-
-
STSEL0.3,2 = 00/01
-
-
-
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Table 4-23. Settings of Register, and Output Latch When Using Alternate Function (6/16)
(e) Alternate function of P4
Alternate function
port
Function
name
P41
P42
P43
P44
P45
P46
P47
Expanded control setting (Register.bit)
PMxx
Pxx
LCDPFxx
I/O
Enable function
Disable other function
TI04
Input
1
x
0
TIS01.1,0 = 11
-
TO04
Output
0
0
0
TOS01.1,0 = 11
-
STOPST
Output
0
0
0
TI10
Input
1
x
0
TIS10.1,0 = 10
-
TO10
Output
0
0
0
TOS10.1,0 = 10
-
SEG7
Output
x
x
1
TI22
Input
1
x
0
TIS20.5,4 = 11
-
TO22
Output
0
0
0
TOS20.5,4 = 11
-
SEG14
Output
x
x
1
TI23
Input
1
x
0
TIS20.7,6 = 11
-
TO23
Output
0
0
0
TOS20.7,6 = 11
-
SEG15
Output
x
x
1
-
-
SEG53
Output
x
x
1
-
-
DBWR
Output
0
1
0
-
-
SEG27
Output
x
X
1
-
-
DBRD
Input
0
1
0
-
-
SEG26
Output
x
x
1
-
-
-
-
-
-
-
-
___________
__________
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Table 4-23. Settings of Register, and Output Latch When Using Alternate Function (7/16)
(f) Alternate function of P5
Alternate function
port
Function
P51
Pxx
LCDPFxx
I/O
name
P50
Expanded control setting (Register.bit)
PMxx
Enable function
Disable other function
TI02
Input
1
x
0
TIS00.4 = 1
TO02
Output
0
0
0
TOS00.4 = 1
STSEL1.7,6 = 00/01
SDA11
I/O
0
1
0
STSEL1.7,6 = 10
TOS00.4 = 0
SEG49
Output
x
x
1
-
TI04
Input
1
x
0
TIS01.0 = 1
TOS01.0 = 1
TO04
Output
0
0
0
SCK10
Output
0
1
0
Input
1
x
SEG50
Output
x
x
1
TI06
Input
1
x
0
-
STSEL0.6 = 0
TOS01.0 = 0
STSEL0.6 = 1
P52
-
-
TIS01.4 = 1
-
RTCSEL.0 = 0
P53
P54
TO06
Output
0
0
0
TOS01.4 = 1
-
SI10
Input
1
x
0
STSEL0.6 = 1
-
SEG51
Output
x
x
1
TI13
Input
1
x
0
TIS10.7,6 = 10
TO13
Output
0
0
0
TOS10.7,6 = 10
STSEL0.6 = 0
SO10
Output
0
1
0
STSEL0.6 = 1
TOS10.7,6 = 00/01/11
SEG52
Output
x
x
1
TI14
Input
1
x
0
-
-
-
-
TIS11.1,0 = 10
-
STSEL1.0 = 0
P55
TO14
Output
0
0
0
TOS11.1,0 = 10
SO01
Output
0
1
0
STSEL0.4 = 1
SEG2
Output
x
x
1
TI15
Input
1
x
0
-
-
TIS11.3,2 = 10
-
STSEL1.1 = 0
P56
TO15
Output
0
0
0
TOS11.3,2 = 10
SI01
Input
1
x
0
STSEL0.4 = 1
SEG3
Output
x
x
1
TI16
Input
1
x
0
-
-
TIS11.5,4 = 10
-
RTCSEL.2 = 0
TO16
Output
0
0
0
SCK01
Output
0
1
0
Input
1
x
SEG4
Output
x
x
1
TI17
Input
1
x
0
TOS11.5,4 = 10
STSEL0.4 = 0
TOS11.5,4 = 00/01
STSEL0.4 = 1
P57
TIS11.7,6 = 11
-
RTCSEL.3 = 0
TO17
Output
0
0
0
SEG5
Output
x
x
1
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-
-
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Table 4-23. Settings of Register, and Output Latch When Using Alternate Function (8/16)
(g) Alternate function of P6
Alternate function
port
Function
name
P60
Expanded control setting (Register.bit)
PMxx
Pxx
LCDPFxx
I/O
INTP1
Input
1
x
TI20
Input
1
x
Enable function
Disable other function
-
-
N/A
TIS20.1,0 = 00
-
TISELSE.7 = 0
P61
P62
P63
P64
P65
P66
TO20
Output
0
0
TOS20.1,0 = 00
STSEL1.7,6 = 01/10
SCL11
Output
0
1
STSEL1.7,6 = 00
TOS20.1,0 = 01/10
INTP3
Input
1
x
TI21
Input
1
x
TIS20.3,2 = 00
TO21
Output
0
0
TOS20.3,2 = 00
STSEL1.7,6 = 01/10
SDA11
I/O
0
1
STSEL1.7,6 = 00
TOS20.3,2 = 01/10/11
TI27
Input
1
x
TO27
Output
1
0
TOS21.7,6 = 10
STSEL1.3 = 1
CTxD1
Output
0
1
STSEL1.3 = 0
TOS21.7,6 = 00/01
TI26
Input
1
x
TO26
Output
0
CRxD1
Input
1
TI11
Input
1
x
TO11
Output
0
0
TOS10.3,2 = 11
RTCSEL.7,6 = 01/10/11
RTC1HZ
Output
0
0
RTCSEL.7,6 = 00
TOS10.3,2 = 00/01/10
TI25
Input
1
x
TO25
Output
0
0
TI24
Input
1
x
TO24
Output
0
0
TOS21.1,0 = 00
SGSEL.3 = 0
PCL
Output
0
0
SGSEL.3 = 1
TOS21.1,0 = 01/10
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N/A
N/A
N/A
-
-
TIS21.7,6 = 01
-
TIS21.5,4 = 00
-
0
TOS21.5,4 = 01
-
x
STSEL1.3 = 0
-
N/A
N/A
N/A
TIS10.3,2 = 11
-
TIS21.3,2 = 00
-
TOS21.3,2 = 00
-
TIS21.1,0 = 00
-
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Table 4-23. Settings of Register, and Output Latch When Using Alternate Function (9/16)
(h) Alternate function of P7
Alternate function
port
Function
name
P70
P71
P72
P73
P74
P75
Expanded control setting (Register.bit)
PMxx
Pxx
LCDPFxx
I/O
Enable function
INTPLR0
Input
1
x
TI03
Input
1
TO03
Output
CRxD0
LRxD0
N/A
Disable other function
STSEL0.0 = 0
-
x
TIS00.7,6 = 11
-
0
0
TOS00.7,6 = 11
-
Input
1
x
STSEL1.2 = 0
-
Input
1
x
STSEL0.0 = 0
-
STSEL1.2 = 0
STSEL0.0 = 1
STSEL0.0 = 0
STSEL1.3 = 1
-
-
CTxD0
Output
0
1
LTxD0
Output
0
1
ADTRG
Input
1
x
0
SGOA
Output
0
0
0
SEG1
Output
x
x
1
SGO/SGOF
Output
0
0
0
SEG0
Output
x
x
1
TI23
Input
1
x
0
TIS20.7,6 = 00
TO23
Output
0
0
0
TOS20.7,6 = 00
STSEL0.4 = 1
SCK01
Output
0
1
0
STSEL0.4 = 0
TOS20.7,6 = 01/10
Input
1
x
SEG26
Output
x
x
1
TI22
Input
1
x
0
TIS20.5,4 = 00
TO22
Output
0
0
0
TOS20.5,4 = 00
SGSEL.3 = 1
PCL
Output
0
0
0
SGSEL.3 = 0
TOS20.5,4 = 01/10
SI01
Input
1
x
0
STSEL0.4 = 0
-
SEG27
Output
x
x
1
-
-
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-
-
-
SGSEL.2-0 = 000
-
-
-
-
-
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Table 4-23. Settings of Register, and Output Latch When Using Alternate Function (10/16)
(i) Alternate function of P8
Alternate function
port
Function
name
P80
P81
P82
Expanded control setting (Register.bit)
PMxx
Pxx
LCDPFxx
I/O
Enable function
Disable other function
TI01
Input
1
x
0
TIS00.3,2 = 01
-
TO01
Output
0
0
0
TOS00.3,2 = 01
SMPC.0 = 0
SM11
Output
0
0
0
SMPC.0 = 1
TOS00.3,2 = 00/10
SEG32
Output
x
x
1
-
-
TI03
Input
1
x
0
TIS00.7,6 = 01
-
TO03
Output
0
0
0
TOS00.7,6 = 01
SMPC.0 = 0
SM12
Output
0
0
0
SMPC.0 = 1
TOS00.7,6 = 00/10/11
SEG33
Output
x
x
1
-
-
TI05
Input
1
x
0
TIS01.3,2 = 01
-
TISELSE.1,0 = 00
P83
TO05
Output
0
0
0
TOS01.3,2 = 01
SMPC.0 = 0
SM13
Output
0
0
0
SMPC.0 = 1
TOS01.3,2 = 00/10
SEG34
Output
x
x
1
TI07
Input
1
x
0
-
-
TIS01.7,6 = 01
-
RTCSEL.1 = 0
P84
P85
P86
TO07
Output
0
0
0
TOS01.7,6 = 01
SMPC.0 = 0
SM14
Output
0
0
0
SMPC.0 = 1
TOS01.7,6 = 00/10
ZPD14
Input
x
x
0
ZPDS0.3 = 1
SEG35
Output
x
x
1
-
-
TI11
Input
1
x
0
TIS10.3,2 = 01
-
TO11
Output
0
0
0
TOS10.3,2 = 01
SMPC.1 = 0
SM21
Output
0
0
0
SMPC.1 = 1
TOS10.3,2 = 00/10/11
SEG36
Output
x
x
1
-
TI13
Input
1
x
0
TIS10.7,6 = 11
TO13
Output
0
0
0
TOS10.7,6 = 11
SMPC.1 = 0
SM22
Output
0
0
0
SMPC.1 = 1
TOS10.7,6 = 00/01/10
SEG37
Output
x
x
1
-
-
TI15
Input
1
x
0
TIS11.3,2 = 11
-
-
-
STSEL1.1 = 0
P87
TO15
Output
0
0
0
TOS11.3,2 = 11
SMPC.1 = 0
SM23
Output
0
0
0
SMPC.1 = 1
TOS11.3,2 = 00/01/10
SEG38
Output
x
x
1
TI17
Input
1
x
0
-
-
TIS11.7,6 = 10
-
RTCSEL.3 = 0
TO17
Output
0
0
0
TOS11.7,6 = 10
SMPC.1 = 0
SM24
Output
0
0
0
SMPC.1 = 1
TOS11.7,6 = 00/01/11
ZPD24
Input
x
x
0
ZPDS0.7 = 1
SEG39
Output
x
x
1
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Table 4-23. Settings of Register, and Output Latch When Using Alternate Function (11/16)
(j) Alternate function of P9(1/2)
Alternate function
port
P90
P91
P92
Function
name
TI21
I/O
Input
Expanded control setting (Register.bit)
PMxx
Pxx
LCDPFxx
1
x
0
Enable function
Disable other function
TIS20.3,2 = 11
-
TO21
Output
0
0
0
TOS20.3,2 = 11
SMPC.2 = 0
SM31
Output
0
0
0
SMPC.2 = 1
TOS20.3,2 = 00/01/10
SEG40
Output
x
x
1
TI23
Input
1
x
0
TIS20.7,6 = 10
TO23
Output
0
0
0
TOS20.7,6 = 10
SMPC.2 = 0
SM32
Output
0
0
0
SMPC.2 = 1
TOS20.7,6 = 00/01
SEG41
Output
x
x
1
TI25
Input
1
x
0
TIS21.3,2 = 01
TO25
Output
0
0
0
TOS21.3,2 = 01
-
-
-
SMPC.2 = 0
SGSEL.2-0 = 000/010/100 to 110
SM33
Output
0
0
0
SMPC.2 = 1
TOS21.3,2 = 00/10
SGSEL.2-0 = 000/010/100 to 110
SGOA
Output
0
0
0
SGSEL.2-0 = 001
SEG42
Output
x
x
1
TI27
Input
1
x
0
TIS21.7,6 = 00
TO27
Output
0
0
0
TOS21.7,6 = 00
SMPC.2 = 0
TOS21.3,2 = 00/10
P93
-
SMPC.2 = 0
SGSEL.1,0 = 00/10
SM34
Output
0
0
0
SMPC.2 = 1
TOS21.7,6 = 01/10
SGSEL.1,0 = 00/10
ZPD34
Input
x
x
0
ZPDS1.3 = 1
SGO/SGOF
Output
0
0
0
SGSEL.1,0 = 01
TOS21.7,6 = 01/10
SMPC.2 = 0
P94
SEG43
Output
x
x
1
TI01
Input
1
x
0
TIS00.3,2 = 10
-
TO01
Output
0
0
0
TOS00.3,2 = 10
SMPC.3 = 0
RTCSEL.7,6 = 00/01
RTC1HZ
Output
0
0
0
RTCSEL.7,6 = 10
TOS00.3,2 = 00/01
SM41
Output
0
0
0
SMPC.3 = 1
TOS00.3,2 = 00/01
SEG44
Output
x
x
1
TI03
Input
1
x
0
SMPC.3 = 0
RTCSEL.7,6 = 00/01
P95
P96
-
-
TIS00.7,6 = 10
-
TO03
Output
0
0
0
TOS00.7,6 = 10
SMPC.3 = 0
SM42
Output
0
0
0
SMPC.3 = 1
TOS00.7,6 = 00/01/11
SEG45
Output
x
x
1
TI05
Input
1
x
0
-
-
TIS01.3,2 = 10
-
TISELSE.1,0 = 00
TO05
Output
0
0
0
TOS01.3,2 = 10
SMPC.3 = 0
SM43
Output
0
0
0
SMPC.3 = 1
TOS01.3,2 = 00/01
SEG46
Output
x
x
1
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Table 4-23. Settings of Register, and Output Latch When Using Alternate Function (12/16)
(j) Alternate function of P9 (2/2)
Alternate function
port
Function
name
P97
TI07
Expanded control setting (Register.bit)
PMxx
Pxx
LCDPFxx
I/O
Input
Enable function
1
x
0
Disable other function
TIS01.7,6 = 10
-
RTCSEL.1 = 0
TO07
Output
0
0
0
TOS01.7,6 = 10
SMPC.3 = 0
SM44
Output
0
0
ZPD44
Input
x
x
0
SMPC.3 = 1
TOS01.7,6 = 00/01
0
ZPDS1.7 = 1
SEG47
Output
x
x
1
-
-
(k) Alternate function of P10
Alternate function
port
P100
P101
P102
P103
P104
P105
P106
P107
Function
name
I/O
Expanded control setting (Register.bit)
PMxx
Pxx
LCDPFxx
Enable function
Disable other function
TI24
Input
1
x
0
TIS21.1,0 = 11
-
TO24
Output
0
0
0
TOS21.1,0 = 11
-
SEG36
Output
x
x
1
TI25
Input
1
x
0
TIS21.3,2 = 11
-
TO25
Output
0
0
0
TOS21.3,2 = 11
-
SEG37
Output
x
x
1
TI26
Input
1
x
0
TIS21.5,4 = 11
-
TO26
Output
0
0
0
TOS21.5,4 = 11
-
SEG38
Output
x
x
1
TI27
Input
1
x
0
TIS21.7,6 = 11
-
TO27
Output
0
0
0
TOS21.7,6 = 11
-
SEG39
Output
x
x
1
TI01
Input
1
x
0
TIS00.3,2 = 11
-
TO01
Output
0
0
0
TOS00.3,2 = 11
-
SEG44
Output
x
x
1
TI02
Input
1
x
0
TIS00.5,4 = 11
-
TO02
Output
0
0
0
TOS00.5,4 = 11
-
SEG45
Output
x
x
1
TI05
Input
1
x
0
TIS01.3,2 = 11
-
TO05
Output
0
0
0
TIS01.3,2 = 11
-
SEG46
Output
x
x
1
TI06
Input
1
x
0
TIS01.5,4 = 10
-
TO06
Output
0
0
0
TIS01.5,4 = 10
-
SEG47
Output
x
x
1
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Table 4-23. Settings of Register, and Output Latch When Using Alternate Function (13/16)
(l) Alternate function of P11
Alternate function
port
P110
P111
P112
Function
name
0
TIS00.1,0 = 00
TO00
Output
0
0
0
TOS00.1,0 = 00
STSEL0.3,2 = 00/01/10
SCK00
Output
0
1
0
STSEL0.3,2 = 11
TOS00.1,0 = 01/10
Input
1
x
DBD0
I/O
1
0
0
-
-
SEG35
Output
x
x
1
-
-
TI02
Input
1
x
0
TIS00.5,4 = 11
-
TO02
Output
0
0
0
TOS00.5,4 = 11
-
SI00
Input
1
x
0
STSEL0.3,2 = 11
-
RxD0
Input
1
x
0
STSEL0.3,2 = 11
-
DBD1
I/O
1
0
0
-
-
SEG34
Output
x
x
1
-
-
1
x
0
TI04
Input
-
-
TIS01.1,0 = 10
-
TO04
Output
0
0
0
TOS01.1,0 = 10
STSEL0.3,2 = 00/01/10
SO00
Output
0
1
0
STSEL0.3,2 = 11
TOS01.1,0 = 00/01/11
TxD0
Output
0
1
0
STSEL0.3,2 = 11
TOS01.1,0 = 00/01/11
1
0
0
-
-
SEG33
Output
x
x
1
-
-
TI06
Input
1
x
0
TIS01.5,4 = 11
-
TO06
Output
0
0
0
TOS01.5,4 = 11
-
I/O
1
0
0
-
-
SEG32
Output
x
x
1
-
-
TI07
Input
1
x
0
TIS01.7,6 = 11
-
TO07
Output
0
0
0
TOS01.7,6 = 11
-
I/O
1
0
0
-
-
SEG31
Output
x
x
1
-
-
TI10
Input
1
x
0
TIS10.1,0 = 01
-
TO10
Output
0
0
0
TOS10.1,0 = 01
-
I/O
1
0
0
-
-
SEG30
Output
x
x
1
-
-
TI12
Input
1
x
0
TIS10.5,4 = 11
-
TO12
Output
0
0
0
TOS10.5,4 = 11
-
1
0
0
-
-
x
1
-
-
DBD6
P117
Disable other function
x
DBD5
P116
Enable function
1
DBD4
P115
LCDPFxx
Input
DBD3
P114
Pxx
TI00
DBD2
P113
I/O
Expanded control setting (Register.bit)
PMxx
I/O
I/O
SEG29
Output
x
TI20
Input
1
x
0
TIS20.1,0 = 11
-
TO20
Output
0
0
0
TOS20.1,0 = 11
-
1
0
0
-
-
x
x
1
-
-
DBD7
SEG28
I/O
Output
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Table 4-23. Settings of Register, and Output Latch When Using Alternate Function (14/16)
(m) Alternate function of P12
Alternate function
port
CMC
Function name
I/O
P121
X1
-
P122
X2
-
EXCLK
Input
P123
XT1
-
P124
XT2
-
CMC.7,6 = 01
CMC.7,6 = 11
CMC.4 = 1
(n) Alternate function of P12
Alternate function
Port
P125
P126
P127
Expanded control setting (Register.bit)
PMxx
Pxx
LCDPFxx
Input
1
x
0
TIS10.5,4 = 10
TO12
Output
0
0
0
TOS10.5,4 = 10
SEG25
Output
x
x
1
-
-
TI14
Input
1
x
0
TIS11.1,0 = 11
-
TO14
Output
0
0
0
TOS11.1,0 = 11
SEG24
Output
x
x
1
-
-
TI16
Input
1
x
0
TIS11.5,4 = 11
-
TO16
Output
0
0
0
TOS11.5,4 = 11
SEG23
Output
x
x
1
Function
name
TI12
I/O
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-
Disable other function
-
-
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Table 4-23. Settings of Register, and Output Latch When Using Alternate Function (15/16)
(o) Alternate function of P13
Alternate function
port
Function
name
P131
Expanded control setting (Register.bit)
PMxx
Pxx
LCDPFxx
I/O
Enable function
TI21
Input
1
x
TO21
Output
0
0
N/A
Disable other function
TIS20.3,2 = 10
TOS20.3,2 = 10
STSEL0.6 = 1
STSEL0.1 = 0
SO10
Output
0
1
STSEL0.6 = 0
TOS20.3,2 = 00/01/11
STSEL0.1 = 0
LTxD1
Output
0
1
STSEL0.1 = 1
TOS20.3,2 = 00/01/11
STSEL0.6 = 1
P132
INTPLR1
Input
1
x
N/A
STSEL0.1 = 1
-
TI20
Input
1
x
TIS20.1,0 = 10
-
TO20
Output
0
0
TOS20.1,0 = 10
-
SI10
Input
1
x
STSEL0.6 = 0
-
LRxD1
Input
1
x
STSEL0.1 = 1
-
TI22
Input
1
x
TIS20.5,4 = 10
-
TO22
Output
0
0
TOS20.5,4 = 10
STSEL0.6 = 1
SCK10
Output
0
1
STSEL0.6 = 0
TOS20.5,4 = 00/01
Input
1
x
TI24
Input
1
x
TO24
Output
0
0
TISELSE.7 = 0
P133
P134
N/A
N/A
TIS21.1,0 = 10
TOS21.1,0 = 10
SGSEL.2-0 = 000/001/100 to 110
STSEL1.3 = 0
SGOA
0
0
SGSEL.2-0 = 010
TOS21.1,0 = 00/01
Output
STSEL1.3 = 0
CTxD1
0
1
STSEL1.3 = 1
TOS21.1,0 = 00/01
Output
SGSEL.2-0 = 000/001/100 to 110
P135
P136
TI26
Input
1
x
N/A
TIS21.5,4 = 10
-
TO26
Output
0
0
TOS21.5,4 = 10
SGSEL.1, 0 = 00/01
SGO/SGOF
Output
0
0
SGSEL.1,0 = 10
TOS21.5,4 = 00/01
CRxD1
Input
1
x
STSEL1.3 = 1
-
TI00
Input
1
x
TIS00.0 = 1
-
0
TISELSE.6 = 0
TO00
Output
0
0
0
TOS00.0 = 1
STSEL1.7,6 = 00/01
SCL11
Output
0
1
0
STSEL1.7,6 = 10
TOS00.0 = 0
SEG48
Output
x
x
1
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Table 4-23. Settings of Register, and Output Latch When Using Alternate Function (16/16)
(p) Alternate function of P14
Alternate function
port
Function
name
P14
Expanded control setting (Register.bit)
PMxx
Pxx
LCDPFxx
I/O
Enable function
TI11
Input
1
x
TO11
Output
0
0
PMxx
Pxx
N/A
Disable other function
TIS10.3,2 = 10
-
TOS10.3,2 = 10
-
(q) Alternate function of 15
Alternate function
port
Function
name
ADPC
(bit 3 to 0)
I/O
P150
ANI8
Input
x
x
0000
P151
ANI9
Input
x
x
0000/1011
P152
ANI10
Input
x
x
0000
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4.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn)
When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output
latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit.
Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
When P10 is an output port, P11 to P17 are input ports (all pin statuses are high level), and the port
latch value of port 1 is 00H, if the output of output port P10 is changed from low level to high level via a
1-bit manipulation instruction, the output latch value of port 1 is FFH.
Explanation:
The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output
latch and pin status, respectively.
A 1-bit manipulation instruction is executed in the following order in the RL78/D1A.
The Pn register is read in 8-bit units.
The targeted one bit is manipulated.
The Pn register is written in 8-bit units.
In step , the output latch value (0) of P10, which is an output port, is read, while the pin statuses of
P11 to P17, which are input ports, are read. If the pin statuses of P11 to P17 are high level at this time,
the read value is FEH.
The value is changed to FFH by the manipulation in .
FFH is written to the output latch by the manipulation in .
Figure 4-79. Bit Manipulation Instruction (P10)
1-bit manipulation
instruction
(set1 P1.0)
is executed for P10
bit.
P10
Low-level output
P11 to P17
P10
High-level output
P11 to P17
Pin status: High level
Port 1 output latch
0
0
0
Pin status: High level
Port 1 output latch
0
0
0
0
0
1
1
1
1
1
1
1
1
1-bit manipulation instruction for P10 bit
Port register 1 (P1) is read in 8-bit units.
• In the case of P10, an output port, the value of the port output latch (0) is read.
• In the case of P11 to P17, input ports, the pin status (1) is read.
Set the P10 bit to 1.
Write the results of to the output latch of port register 1 (P1)
in 8-bit units.
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CHAPTER 5 CLOCK GENERATOR
CHAPTER 5 CLOCK GENERATOR
The presence or absence of connecting resonator pin for main system clock, connecting resonator pin for subsystem
clock, external clock input pin for main system clock, and external clock input pin for subsystem clock, depends on the
product.
Output pin
128-pin
100-pin
80-pin
64-pin
48-pin
X1, X2 pins
EXCLK pin
XT1, XT2 pins
N/A
5.1 Functions of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following three kinds of system clocks and clock oscillators are selectable.
(1) Main system clock
X1 oscillator
This circuit oscillates a clock of fX = 1 to 20 MHz by connecting a resonator to X1 and X2.
Oscillation can be stopped by executing the STOP instruction or setting of the MSTOP bit (bit 7 of the clock
operation status control register (CSC)).
High-speed on-chip oscillator
The frequency at which to oscillate can be selected from among fIH = 32, 24, 16, 8, or 4 MHz (typ.) by using
the option byte (000C2H). After a reset release, the CPU always starts operating with this High-speed onchip oscillator clock. Oscillation can be stopped by executing the STOP instruction or setting the HIOSTOP
bit (bit 0 of the CSC register).
An external main system clock (fEX = 1 to 20 MHz) can also be supplied from the EXCLK/X2/P122 pin. An external
main system clock input can be disabled by executing the STOP instruction or setting of the MSTOP bit.
As the main system clock, a high-speed system clock (X1 clock or external main system clock) or high-speed on
chip oscillator clock can be selected by setting of the MCM0 bit (bit 4 of the system clock control register (CKC)).
(2) PLL clock
A clock that is the main system clock multiplied by 1, 6 or 8 can be oscillated. Oscillation can be stopped by
executing a STOP instruction or by setting PLLON (bit 0 of PLLCTL) to 0.
(3) Subsystem clock
XT1 clock oscillator
This circuit oscillates a clock of fXT = 32.768 kHz by connecting a 32.768 kHz resonator to XT1 and XT2.
Oscillation can be stopped by setting the XTSTOP bit (bit 6 of the clock operation status control register (CSC)).
(4) Low-speed on-chip oscillator clock
This circuit oscillates a clock of fIL = 15 kHz (TYP.).
The low-speed on-chip oscillator clock cannot be used as the CPU clock.
Only the following peripheral hardware runs on the low-speed on-chip oscillator clock.
Watchdog timer
Real-time clock
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Interval timer
LCD controller/driver
This clock operates when bit 4 (WDTON) of the option byte (000C0H), bit 4 (WUTMMCK0) of the operation
speed mode control register (OSMC), or both are set to 1.
However, when WDTON = 1, WUTMMCK0 = 0, and bit 0 (WDSTBYON) of the option byte (000C0H) is 0,
oscillation of the low-speed on-chip oscillator stops if the HALT or STOP instruction is executed.
Caution The low-speed on-chip oscillator clock (fIL) can only be selected as the real-time clock
operation clock when the fixed-cycle interrupt function is used.
Remark
fX:
X1 clock oscillation frequency
fIH:
High-speed on-chip oscillator clock frequency
fEX:
External main system clock frequency
fXT:
XT1 clock oscillation frequency
fIL:
Low-speed on-chip oscillator clock frequency
fIL itself is controlled by the combination of WDT option bytes and OSMC register and CPU status as shown
below. It is not controlled by CLKMB option byte. The other clocks are the same situation. Clock operation control
is separated from clock enable settings for peripherals.
fIL can operate continuously and independently of the CPU status and WDT operation. In order to use fIL as
continuous clock source for the peripheral hardware, WUTTMCK0 should be set to 1.
CPU status
WDTON
(option byte)
WDTSTBYON
(option byte)
WUTMMCK0
(OSMC register)
fIL operation
RUN
0
0
0
Stopped
RUN
0
0
1
Operated
RUN
0
1
0
Stopped
RUN
0
1
1
Operated
RUN
1
0
0
Operated
RUN
1
0
1
Operated
RUN
1
1
0
Operated
RUN
1
1
1
Operated
HALT/STOP/SNOOZE
0
0
0
Stopped
HALT/STOP/SNOOZE
0
0
1
Operated
HALT/STOP/SNOOZE
0
1
0
Stopped
HALT/STOP/SNOOZE
0
1
1
Operated
HALT/STOP/SNOOZE
1
0
0
Stopped
HALT/STOP/SNOOZE
1
0
1
Operated
HALT/STOP/SNOOZE
1
1
0
Operated
HALT/STOP/SNOOZE
1
1
1
Operated
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5.2 Configuration of Clock Generator
The clock generator includes the following hardware.
Table 5-1. Configuration of Clock Generator
Item
Control registers
Configuration
Clock operation mode control register (CMC)
System clock control register (CKC)
Clock operation status control register (CSC)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
Peripheral enable registers 0, 1 (PER0, PER1)
Peripheral clock select register(PCKSEL)
Operation speed mode control register (OSMC)
High-speed on-chip oscillator trimming register (HIOTRM)
PLL control register (PLLCTL)
PLL status register (PLLSTS)
FMP clock division selection register (MDIV)
Oscillators
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XT1 oscillator
High-speed on-chip oscillator
Low-speed on-chip oscillator
314
External input
clock
Crystal/ceramic
oscillation
AMPHS1 AMPHS0 OSCSELS
Crystal
oscillation
fSUB
fIH
CLS
Clock operation
status control
register (CSC)
XTSTOP HIOSTOP
oscillation (15 kHz (TYP.))
Internal low-speed
oscillator
fIL
Internal low-speed
STOP mode
signal
(Remark is listed on the next page after next.)
Clock operation mode
control register
(CMC)
XT2/P124
XT1/P123
Subsystem clock
oscillator
fXT
Internal high-speed
oscillation (8 MHz (TYP.))
Internal high-speed
oscillation (16 MHz (TYP.))
fMX
MSTOP
6
Controller
Selector
HALT/STOP mode signal
Option byte (000C0H)
WDTON
WDSTBYON
Internal bus
Internal high-speed oscillator
trimming register(HIOTRM)
Controller
Main system clock
source selector
HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRM0
WUTMMCK0
RTC,
Interval timer
RTC,
Interval timer
Oscillation stabilization
time counter status
register (OSTC)
MOST MOST MOST MOST MOST MOST MOST MOST
8
9
10
11 13 15 17 18
X1 oscillation
stabilization time counter
3
OSTS2 OSTS1 OSTS0
Oscillation stabilization
time select register (OSTS)
Internal bus
fMAIN
CSS MCS MCM0
MD
IV2
Subsystem clock supply
mode control register
(OSMC)
RTC
EN
Clock output/buzzer output
LCD controller/driver
Watchdog timer
LCD controller/driver
RTC
Internal timer
fMP
fMP/2
fMP/22
fMP/23
fMP/24
fMP/25
CAN controller
Clock output/
buzzer output
RTCLPC WUTMMCK0
RTC
Interval timer
fMP
PLL
(see Figure 5-2)
CAN controller
LCD controller/driver
CLS
System clock control
register (CKC)
3
MD
IV1
LIN1
EN
LIN0
EN
MD
IV0
SAU1
EN
TAU2
EN
TAU1
EN
TAU0
EN
Timer array unit 0
Timer array unit 1
Timer array unit 2
Serial array unit 0
Serial array unit 1
LIN-UART0
LIN-UART1
A/D converter
Sound generator
Stepper motor
controller/driver
RTC
LCD bus controller
CPU, DMA
Normal
operation mode
HALT mode
STOP mode
Standby controller
Peripheral enable
register 0 (PER0)
SAU0
EN
CPU clock
and peripheral
hardware
clock source
selection
fCLK
FMP clock division selection
register (MDIV)
Internal high-speed
oscillation (4 MHz (TYP.))
Internal high-speed
oscillation (24MHz (TYP.))
fEX
fX
Internal high-speed
oscillation (32 MHz (TYP.))
Internal high-speed oscillator
Option byte (000C2H)
FRQSEL0 to FRQSEL3
X2/EXCLK
/P122
X1/P121
High-speed
High-speedsystem
system
clock
clockoscillator
oscillator
AMPH EXCLK OSCSEL
Clock operation status
control register
(CSC)
Selector
Clock operation mode
control register
(CMC)
Prescaler
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Figure 5-1. Block Diagram of Clock Generator
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Remark
CHAPTER 5 CLOCK GENERATOR
fX:
X1 clock oscillation frequency
fIH:
High-speed on-chip oscillator clock frequency
fEX:
External main system clock frequency
fMX:
High-speed system clock frequency
fMAIN: Main system clock frequency
fXT:
XT1 clock oscillation frequency
fSUB:
Subsystem clock frequency
fCLK:
CPU/peripheral hardware clock frequency
fIL:
Low-speed on-chip oscillator clock frequency
Figure 5-2. Block Diagram of PLL Circuit
PLL status register
(PLLSTS)
PLL control register
(PLLCTL)
SELPLLS
LCKSEL0 LCKSEL1
Option byte
(000C1H)
PLL control register
(PLLCTL)
GDPLL
fPLLI
PLL circuit
(X12, X16)
GDPLL
SELPLL
PLL control register
(PLLCTL)
OPTPLL
PLLON
PLL control register
(PLLCTL)
GDPLL
fPLLO
PLLDIV0
Divider
(21, 22)
PLL status register
(PLLSTS)
Counter
fMP
fPLL
Selector
Prescaler
Clock output
LOCK
Clock monitor controller
CSS
CLKMB
System clock control
register (CKC)
Remark
fMAIN:
Main system clock
fIL:
Low-speed on-chip oscillator clock
fPLLI:
PLL input clock
fPLLO:
PLL output clock
fPLL:
PLL clock
fMP:
PLL output for main system clock
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5.3 Registers Controlling Clock Generator
The following nine registers are used to control the clock generator.
Clock operation mode control register (CMC)
System clock control register (CKC)
Clock operation status control register (CSC)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
Peripheral enable registers 0, 1 (PER0, PER1)
Operation speed mode control register (OSMC)
High-speed on-chip oscillator trimming register (HIOTRM)
PLL control register (PLLCTL)
PLL status register (PLLSTS)
Peripheral clock select register(PCKSEL)
FMP clock division selection register (MDIV)
(1) Clock operation mode control register (CMC)
This register is used to set the operation mode of the X1/P121, X2/EXCLK/P122, XT1/P123, and XT2/P124 pins, and
to select a gain of the oscillator.
The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release. This
register can be read by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
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Figure 5-3. Format of Clock Operation Mode Control Register (CMC)
Address: FFFA0H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
CMC
EXCLK
OSCSEL
0
OSCSELS
0
AMPHS1
AMPHS0
AMPH
EXCLK
OSCSEL
0
0
Input port mode
Input port
0
1
X1 oscillation mode
Crystal/ceramic resonator connection
1
0
Input port mode
Input port
1
1
External clock input mode
Input port
OSCSELS
Subsystem clock pin
operation mode
High-speed system clock
pin operation mode
X1/P121 pin
External clock input
XT1/P123 pin
XT2/P124 pin
0
Input port mode
Input port
1
XT1 oscillation mode
Crystal/ceramic resonator connection
AMPHS1
AMPHS0
0
0
Low power consumption oscillation (default)
0
1
Normal oscillation
1
0
Ultra-low power consumption oscillation
1
1
Setting prohibited
XT1 oscillator oscillation mode selection
AMPH
Control of X1 clock oscillation frequency
0
1 MHz fX 10 MHz
1
10 MHz < fX 20 MHz
Cautions
X2/EXCLK/P122 pin
1. The CMC register can be written only once after reset release, by an 8-bit
memory manipulation instruction. When using the CMC register with its initial
value (00H), be sure to set the register to 00H after a reset ends in order to
prevent malfunction due to a program loop. Such a malfunction becomes
unrecoverable when a value other than 00H is mistakenly written.
2. After reset release, set the CMC register before X1 or XT1 oscillation is started as
set by the clock operation status control register (CSC).
3. Be sure to set the AMPH bit to 1 if the X1 clock oscillation frequency exceeds 10
MHz.
4. Specify the settings for the AMPH, AMPHS1 and AMPHS0 bits while fIH is
selected as fCLK after a reset ends (before fCLK is switched to fMX).
5. Oscillation stabilization time of fXT, counting on the software.
6. Although the maximum system clock frequency is 32 MHz, the maximum
frequency of the X1 oscillator is 20 MHz.
(Cautions and Remark are given on the next page.)
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7. The XT1 oscillator is a circuit with low amplification in order to achieve lowpower consumption. Note the following points when designing the circuit.
Pins and circuit boards include parasitic capacitance.
Therefore, perform
oscillation evaluation using a circuit board to be actually used and confirm
that there are no problems.
Make the wiring between the XT1 and XT2 pins and the resonators as short as
possible, and minimize the parasitic capacitance and wiring resistance. Note
this particularly when the ultra-low power consumption oscillation (AMPHS1,
AMPHS0 = 1, 0) is selected.
Configure the circuit of the circuit board, using material with little wiring
resistance.
Place a ground pattern that has the same potential as VSS as much as possible
near the XT1 oscillator.
Be sure that the signal lines between the XT1 and XT2 pins, and the resonators
do not cross with the other signal lines. Do not route the wiring near a signal
line through which a high fluctuating current flows.
The impedance between the XT1 and XT2 pins may drop and oscillation may
be disturbed due to moisture absorption of the circuit board in a high-humidity
environment or dew condensation on the board. When using the circuit board
in such an environment, take measures to damp-proof the circuit board, such
as by coating.
When coating the circuit board, use material that does not cause capacitance
or leakage between the XT1 and XT2 pins.
Remark fX: X1 clock frequency
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(2) System clock control register (CKC)
This register is used to select a CPU/peripheral hardware clock and a main system clock.
The CKC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 5-4. Format of System Clock Control Register (CKC)
Address: FFFA4H
After reset: 00H
R/W
Note 1
Symbol
3
2
1
0
CKC
CLS
CSS
MCS
MCM0
0
0
0
0
CLS
Status of CPU/peripheral hardware clock (fCLK)
0
Main system clock (fMAIN)
1
Subsystem clock (fSUB)
CSS
Selection of CPU/peripheral hardware clock (fCLK)
0
Main system clock (fMAIN)
1
Subsystem clock (fSUB)
MCS
Status of Main system clock (fMAIN)
0
High-speed on-chip oscillator clock (fIH)
1
High-speed system clock (fMX)
MCM0
Main system clock (fMAIN) operation control
0
Selects the high-speed on-chip oscillator clock (fIH) as the main system clock (fMAIN)
1
Selects the high-speed system clock (fMX) as the main system clock (fMAIN)
Notes 1. Bits 7 and 5 are read-only.
2. Changing the value of the MCM0 bit is prohibited while the CSS bit is set to 1.
Remark fIH:
fMX:
fMAIN:
fSUB:
High-speed on-chip oscillator clock frequency
High-speed system clock frequency
Main system clock frequency
Subsystem clock frequency
Cautions 1. Be sure to set bits 3 to 0 of CKC to 0.
2. The clock set by the CSS bit is supplied to the CPU and peripheral hardware. If the
CPU clock is changed, therefore, the clock supplied to peripheral hardware (except
the real-time clock, interval timer, clock output/buzzer output, and watchdog timer) is
also changed at the same time. Consequently, stop each peripheral function when
changing the CPU/peripheral hardware clock.
3. If the subsystem clock is used as the peripheral hardware clock, the operations of
the A/D converter and IICA are not guaranteed. For the operating characteristics of
the peripheral hardware, refer to the chapters describing the various peripheral
hardware as well as CHAPTER 32 ELECTRICAL SPECIFICATIONS (J GRADE
PRODUCT) and CHAPTER 33 ELECTRICAL SPECIFICATIONS (L GRADE PRODUCT).
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(3) Clock operation status control register (CSC)
This register is used to control the operations of the high-speed system clock, high-speed on-chip oscillator clock, and
subsystem clock (except the low-speed on-chip oscillator clock).
The CSC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to C0H.
Figure 5-5. Format of Clock Operation Status Control Register (CSC)
Address: FFFA1H
After reset: C0H
R/W
Symbol
5
4
3
2
1
CSC
MSTOP
XTSTOP
0
0
0
0
0
HIOSTOP
MSTOP
High-speed system clock operation control
X1 oscillation mode
External clock input mode
0
X1 oscillator operating
External clock from EXCLK
pin is valid
1
X1 oscillator stopped
External clock from EXCLK
pin is invalid
XTSTOP
Input port mode
Input port
Subsystem clock operation control
XT1 oscillation mode
0
XT1 oscillator operating
1
XT1 oscillator stopped
HIOSTOP
Input port mode
Input port
High-speed on-chip oscillator clock operation control
0
High-speed on-chip oscillator operating
1
High-speed on-chip oscillator stopped
Cautions 1. After reset release, set the clock operation mode control register (CMC) before
setting the CSC register.
2. Set the oscillation stabilization time select register (OSTS) before setting the MSTOP
bit to 0 after releasing reset. Note that if the OSTS register is being used with its
default settings, the OSTS register is not required to be set here.
3. To start X1 oscillation as set by the MSTOP bit, check the oscillation stabilization
time of the X1 clock by using the oscillation stabilization time counter status register
(OSTC).
4. When starting XT1 oscillation by setting the XSTOP bit to 0, wait for oscillation of the
subsystem clock to stabilize by setting a wait time using software.
5. Do not stop the clock selected for the CPU peripheral hardware clock (fCLK) with the
CSC register.
6. The setting of the flags of the register to stop clock oscillation (invalidate the external
clock input) and the condition before clock oscillation is to be stopped are as Table
5-2.
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Table 5-2. Condition Before Stopping Clock Oscillation and Flag Setting
Condition Before Stopping Clock
(Invalidating External Clock Input)
Clock
X1 clock
External main system
clock
XT1 clock
CPU and peripheral hardware clocks operate with a clock
other than the high-speed system clock.
Setting of CSC
Register Flags
MSTOP = 1
(CLS = 0 and MCS = 0, or CLS = 1)
CPU and peripheral hardware clocks operate with a clock
other than the subsystem clock.
XTSTOP = 1
(CLS = 0)
High-speed on-chip
oscillator clock
CPU and peripheral hardware clocks operate with a clock
other than the high-speed on-chip oscillator clock.
HIOSTOP = 1
(CLS = 0 and MCS = 1, or CLS = 1)
(4) Oscillation stabilization time counter status register (OSTC)
This is the register that indicates the count status of the X1 clock oscillation stabilization time counter.
The X1 clock oscillation stabilization time can be checked in the following case,
If the X1 clock starts oscillation while the high-speed on-chip oscillator clock or subsystem clock is being used as
the CPU clock.
If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as the
CPU clock with the X1 clock oscillating.
The OSTC register can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset signal is generated, the STOP instruction and MSTOP (bit 7 of clock operation status control register
(CSC)) = 1 clear the OSTC register to 00H.
Remark The oscillation stabilization time counter starts counting in the following cases.
When oscillation of the X1 clock starts (EXCLK, OSCSEL = 0, 1 MSTOP = 0)
When the STOP mode is released
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Figure 5-6. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFFA2H
Symbol
OSTC
After reset: 00H
7
6
5
R
4
3
2
1
0
MOST MOST MOST MOST MOST MOST MOST MOST
8
9
10
11
13
15
17
18
MOST MOST MOST MOST MOST MOST MOST MOST
8
9
10
11
13
15
17
18
Oscillation stabilization time status
fX = 10 MHz
fX = 20 MHz
8
0
0
0
0
0
0
0
0
2 /fX max. 25.6 s max. 12.8 s max.
1
0
0
0
0
0
0
0
2 /fX min.
1
1
0
0
0
0
0
0
2 /fX min.
8
25.6 s min.
12.8 s min.
9
51.2 s min.
25.6 s min.
10
1
1
1
0
0
0
0
0
2 /fX min. 102.4 s min. 51.2 s min.
1
1
1
1
0
0
0
0
2 /fX min. 204.8 s min. 102.4 s min.
1
1
1
1
1
0
0
0
2 /fX min. 819.2 s min. 409.6 s min.
1
1
1
1
1
1
0
0
2 /fX min. 3.27 ms min. 1.64 ms min.
1
1
1
1
1
1
1
0
2 /fX min. 13.11 ms min. 6.55 ms min.
1
1
1
1
1
1
1
1
2 /fX min. 26.21 ms min. 13.11 ms min.
11
13
15
17
18
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from the MOST8 bit
and remain 1.
2. The oscillation stabilization time counter counts up to the oscillation stabilization
time set by the oscillation stabilization time select register (OSTS).
In the following cases, set the oscillation stabilization time of the OSTS register to
the value greater than the count value which is to be checked by the OSTC register.
If the X1 clock starts oscillation while the high-speed on-chip oscillator clock or
subsystem clock is being used as the CPU clock.
If the STOP mode is entered and then released while the high-speed on-chip
oscillator clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set by
the OSTS register is set to the OSTC register after the STOP mode is released.)
3. The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark
fX: X1 clock oscillation frequency
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(5) Oscillation stabilization time select register (OSTS)
This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released.
When the X1 clock is selected as the CPU clock, the operation automatically waits for the time set using the OSTS
register after the STOP mode is released.
When the high-speed on-chip oscillator clock is selected as the CPU clock, confirm with the oscillation stabilization
time counter status register (OSTC) that the desired oscillation stabilization time has elapsed after the STOP mode is
released. The oscillation stabilization time can be checked up to the time set using the OSTC register.
The OSTS register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets the OSTS register to 07H.
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Figure 5-7. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFFA3H
After reset: 07H
R/W
Symbol
7
6
5
4
3
2
1
0
OSTS
0
0
0
0
0
OSTS2
OSTS1
OSTS0
OSTS2
OSTS1
OSTS0
Oscillation stabilization time selection
fX = 10 MHz
fX = 20 MHz
8
25.6 s
Setting prohibited
9
51.2 s
25.6 s
10
102.4 s
51.2 s
11
204.8 s
102.4 s
13
819.2 s
409.6 s
15
3.27 ms
1.64 ms
17
13.11 ms
6.55 ms
18
26.21 ms
13.11 ms
0
0
0
2 /fX
0
0
1
2 /fX
0
1
0
2 /fX
0
1
1
2 /fX
1
0
0
2 /fX
1
0
1
2 /fX
1
1
0
2 /fX
1
1
1
2 /fX
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set the OSTS
register before executing the STOP instruction.
2. Change the setting of the OSTS register before setting the MSTOP bit of the clock
operation status control register (CSC) to 0.
3. Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
4. The oscillation stabilization time counter counts up to the oscillation stabilization
time set by the OSTS register.
In the following cases, set the oscillation stabilization time of the OSTS register to
the value greater than the count value which is to be checked by the OSTC register
after the oscillation starts.
If the X1 clock starts oscillation while the high-speed on-chip oscillator clock or
subsystem clock is being used as the CPU clock.
If the STOP mode is entered and then released while the high-speed on-chip
oscillator clock is being used as the CPU clock with the X1 clock oscillating. (Note,
therefore, that only the status up to the oscillation stabilization time set by the
OSTS register is set to the OSTC register after the STOP mode is released.)
5. The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark fX: X1 clock oscillation frequency
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(6) Peripheral enable registers 0, 1 (PER0, PER1)
These registers are used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the
hardware that is not used is also stopped so as to decrease the power consumption and noise.
To use the peripheral functions below, which are controlled by this register, set (1) the bit corresponding to each
function before specifying the initial settings of the peripheral functions.
Real-time clock, interval timer
LIN-UART1
LIN-UART0
Serial array unit 1
Serial array unit 0
Timer array unit 2
Timer array unit 1
Timer array unit 0
A/D converter
Sound generator
Stepper motor controller/driver
LCD bus controller (128-pin products only)
The PER0 and PER1 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 5-8. Format of Peripheral Enable Registers 0, 1 (PER0, PER1) (1/3)
Address: F00F0H
After reset: 00H
PER0
RTCEN
LIN1EN
LIN0EN
SAU1EN
SAU0EN
TAU2EN
TAU1EN
TAU0EN
Address: F00F1H
R/W
Symbol
After reset: 00H
R/W: Bits 0 to 3 and 6 (Read Only)
Symbol
2
1
0
PER1
ADCEN
0
MTRCEN
SGEN
LBEN
0
0
0
RTCEN
0
Control of real-time clock (RTC) and interval timer input clock supply
Stops input clock supply.
SFR used by the real-time clock (RTC) and interval timer cannot be written.
The real-time clock (RTC) and interval timer are in the reset status.
1
Enables input clock supply.
SFR used by the real-time clock (RTC) and interval timer can be read and written.
LIN1EN
0
Control of serial interface LIN-UART1 input clock supply
Stops input clock supply.
SFR used by LIN-UART1 cannot be written.
LIN-UART1 is in the reset status.
1
Supplies input clock.
SFR used by LIN-UART1 can be read and written.
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Figure 5-8. Format of Peripheral Enable Registers 0, 1 (PER0, PER1) (2/3)
Address: F00F0H
After reset: 00H
PER0
RTCEN
LIN1EN
LIN0EN
SAU1EN
SAU0EN
TAU2EN
TAU1EN
TAU0EN
Address: F00F1H
R/W
Symbol
After reset: 00H
R/W: Bits 0 to 3 and 6 (Read Only)
Symbol
2
1
0
PER1
ADCEN
0
MTRCEN
SGEN
LBEN
0
0
0
LIN0EN
0
Control of LIN-UART0 converter input clock supply
Stops input clock supply.
SFR used by LIN-UART0 cannot be written.
LIN-UART0 is in the reset status.
1
Supplies input clock.
SFR used by LIN-UART0 can be read and written.
SAU1EN
0
Control of serial array unit 1 input clock supply
Stops input clock supply.
SFR used by the serial array unit 1 cannot be written.
The serial array unit 1 is in the reset status.
1
Enables input clock supply.
SFR used by the serial array unit 1 can be read and written.
SAU0EN
0
Control of serial array unit 0 input clock supply
Stops input clock supply.
SFR used by the serial array unit 0 cannot be written.
The serial array unit 0 is in the reset status.
1
Enables input clock supply.
SFR used by the serial array unit 0 can be read and written.
TAU2EN
0
Control of serial array unit 2 input clock supply
Stops input clock supply.
SFR used by timer array unit 2 cannot be written.
Timer array unit 2 is in the reset status.
1
Enables input clock supply.
SFR used by timer array unit 2 can be read and written.
TAU1EN
0
Control of timer array unit 1 input clock supply
Stops input clock supply.
SFR used by timer array unit 1 cannot be written.
Timer array unit 1 is in the reset status.
1
Enables input clock supply.
SFR used by timer array unit 1 can be read and written.
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Figure 5-8. Format of Peripheral Enable Registers 0, 1 (PER0, PER1) (3/3)
Address: F00F0H
After reset: 00H
Symbol
PER0
RTCEN
LIN1EN
LIN0EN
SAU1EN
SAU0EN
TAU2EN
TAU1EN
TAU0EN
Address: F00F1H
R/W
After reset: 00H
R/W (Note: Bits 0 to 3 and 6 are Read Only)
Symbol
2
1
0
PER1
ADCEN
0
MTRCEN
SGEN
LBEN
0
0
0
TAU0EN
0
Control of timer array unit 0 input clock supply
Stops input clock supply.
SFR used by timer array unit 0 cannot be written.
Timer array unit 0 is in the reset status.
1
Enables input clock supply.
SFR used by timer array unit 0 can be read and written.
ADCEN
0
Control of A/D converter clock supply
Stops input clock supply.
SFR used by the A/D converter cannot be written.
The A/D converter is in the reset status.
1
Supplies input clock.
SFR used by the A/D converter can be read and written.
MTRCEN
0
Control of stepper motor controller/driver clock supply
Stops input clock supply.
SFR used by the stepper motor controller/driver cannot be written.
The stepper motor controller/driver is in the reset status.
1
Supplies input clock.
SFR used by stepper motor controller/driver can be read and written.
SGEN
0
Control of sound generator clock supply
Stops input clock supply.
SFR used by the sound generator cannot be written.
The sound generator is in the reset status.
1
Supplies input clock.
SFR used by sound generator can be read and written.
LBEN
0
Control of LCD bus controller clock supply
Stops input clock supply.
SFR used by the LCD bus controller cannot be written.
The LCD bus controller is in the reset status.
1
Supplies input clock.
SFR used by LCD bus controller can be read and written.
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(7) Operation speed mode control register (OSMC)
This register is used to reduce power consumption by stopping unnecessary clock functions.
If the RTCLPC bit is set to 1, power consumption can be reduced, because clock supply to the peripheral functions,
except the real-time clock and interval timer, is stopped in STOP mode or HALT mode while subsystem clock is
selected as CPU clock. Set bit 7 (RTCEN) of peripheral enable registers 0 (PER0) to 1 before this setting.
In addition, the OSMC register can be used to select the operation clock of the real-time clock and interval timer.
The OSMC register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 5-9. Format of Operation Speed Mode Control Register (OSMC)
Address: F00F3H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
OSMC
RTCLPC
0
0
WUTMMCK0
0
0
0
0
RTCLPC
0
Setting in STOP mode or HALT mode while subsystem clock is selected as CPU clock
Enables supply of subsystem clock to peripheral functions
(See Table 22-1 for peripheral functions whose operations are enabled.)
1
Stops supply of subsystem clock to peripheral functions other than real-time clock and
interval timer.
WUTMMCK0
Selection of operation clock for real-time clock and interval timer.
0
Other than fIL
1
Low-speed on-chip oscillator clock (fIL)
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(8) High-speed on-chip oscillator trimming register (HIOTRM)
This register is used to adjust the accuracy of the high-speed on-chip oscillator.
With self-measurement of the high-speed on-chip oscillator frequency via a timer using high-accuracy external clock
input (timer array unit), and so on, the accuracy can be adjusted.
The HIOTRM register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to default value (undefined).
Cautions 1. The frequency will vary if the temperature and VDD pin voltage change after accuracy adjustment.
When the temperature and VDD voltage change, accuracy adjustment must be executed regularly
or before the frequency accuracy is required.
2. The optimized value is set by each chip, therefore keep this value unchanged.
Figure 5-10. Format of High-speed on-chip oscillator Trimming Register (HIOTRM)
Address: F00A0H
After reset: undefined
R/W
Symbol
7
6
5
4
3
2
1
0
HIOTRM
0
0
HIOTRM5
HIOTRM4
HIOTRM3
HIOTRM2
HIOTRM1
HIOTRM0
HIOTRM5
HIOTRM4
HIOTRM3
HIOTRM2
HIOTRM1
HIOTRM0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
High-speed on-chip
oscillator
Minimum speed
1
1
1
1
1
0
1
1
1
1
1
1
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(9) PLL control register (PLLCTL)
Figure 5-11. Format of PLL Control Register (PLLCTL)
Address: F0129H
After reset: 00H R/W (Note: Bits 1, 3 and 5 are Read Only)
Symbol
7
6
5
4
3
2
1
0
PLLCTL
LCKSEL1
LCKSEL0
0
PLLDIV0
0
SELPLL
0
PLLON
LCKSEL1
LCKSEL0
0
Lockup wait counter setting value
0
0
Note
7
Should be selected 40 s or more
2 / fMAIN
8
(PLL lock time target is 40 s)
2 / fMAIN (recommended selection of 4 MHz
1
input)
1
9
2 / fMAIN (recommended selection of 8 MHz
0
input)
1
1
Setting prohibited
PLLDIV0
PLL output clock (fPLLO) division selection
0
When fMAIN = 4 MHz
1
When fMAIN = 8 MHz
SELPLL
Clock mode selection
0
Clock through mode (fMAIN)
1
PLL Clock select mode (fPLL)
PLLON
0
1
PLL operation control
Stop PLL
Operates PLL (A lockup wait time is required after the PLL starts operating, so that the
frequency stabilizes.)
Note SELPLL setting is only possible when PLLON = 1 and LOCK = 1.
SELPLL is cleared when either PLLON or LOCK is “0”.
When PLLON = 1, changing of PLLDIV0 is prohibited.
When PLLON = 1, changing of fMAIN is prohibited.
Table 5-3. PLL Input/Output Clock Control
Option byte
PLL control register
User input
SELPLLS = 1
(PLLCTL)
frequency
frequency selection
OPTPLL
PLL
Multiplication
PLLDIV0
Generate frequency
ratio(nr/pr)
0
0
4 MHz
32 MHz
8
32 MHz
1
0
4 MHz
24 MHz
6
24 MHz
0
1
8 MHz
32 MHz
4
32 MHz
1
1
8 MHz
24 MHz
3
24 MHz
Setting value of PLLDIV0 must be related with input frequency. See above table.
The PLL multiplication number (x12 or x16) is set by using bit 5 (OPTPLL) of the option byte (000C2H). See CHAPTER 28
OPTION BYTE for details.
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(10) PLL status register (PLLSTS)
Figure 5-12. Format of PLL Status Register (PLLSTS)
Address: F0128H
After reset: 00H R
Symbol
7
6
5
4
3
2
1
0
PLLSTS
LOCK
0
0
0
SELPLLS
0
0
0
LOCK
Note
PLL lock state
0
Unlocked state
1
Locked state
Note This is set (1) when the lockup wait counter overflows.
State of the clock mode
SELPLLS
0
Clock through mode (fMAIN)
1
PLL clock select mode (fPLL)
(11) FMP clock selection division register (MDIV)
Figure 5-13. Format of FMP Clock Selection Division Register (MDIV)
Address: F00F8H
After reset: 00H R/W
Note1
Symbol
7
6
5
4
3
2
1
0
MDIV
0
0
0
0
0
MDIV2
MDIV1
MDIV0
MDIV2
MDIV1
MDIV0
0
0
0
fMP (default)
0
0
1
fMP/2
0
1
0
fMP/2
2
0
1
1
fMP/2
3
1
0
0
fMP/2
4
1
0
1
fMP/2
5 Note 2
Other than the above
Division of PLL clock (fMP)
Setting prohibited
Notes 1. Bits 7 to 3 must be set to 0.
2. Setting prohibited if fPLL < 4 MHz.
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(12) Peripheral Clock select register (PCKSEL)
Figure 5-14. Format of Peripheral Clock select register (PCKSEL)
Address: F00F2H
After reset: 00H @R/W (Note: Bits 1,2 and 7 are Read Only)
Symbol
PCKSEL
0
0
0
SGCLK
CAN
CAN
CAN
CAN
MCKE1
MCK1
MCKE0
MCK0
CANMCKE1
Supply/stop control of clock (bus & operation) of aFCAN unit1
0
Stops supplying clock (bus & operation) of aFCAN unit1
1
Supplies clock (bus & operation) of aFCAN unit1
CANMCK1
Input clock (operation) supply selection of aFCAN unit1
0
fMAIN is supplied
1
fMP is supplied
CANMCKE0
Supplies/stops control of clock (bus & operation) of aFCAN unit0
0
Stops supplying clock (bus & operation) of aFCAN unit0
1
Supplies clock (bus & operation) of aFCAN unit0
CANMCK0
Input clock (operation) supply selection of aFCAN unit0
0
fMAIN is supplied
1
fMP is supplied
SGCLKSEL
Clock (operation) source supply selection of Sound Generator
0
fCLK is supplied
1
fCLK/2 is supplied
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5.4 Clock monitor (CLM)
The clock monitor uses the low-speed on-chip oscillator to sample the main system clock (fMAIN) and PLL clock(fPLL). If
oscillation of the main system clock stops, a reset request signal (RESFCLM) is generated. If the PLL clock stops, an
interrupt request signal (INTCLM) is generated. Up to 4 clocks of fIL is necessary to detect stop of Main OSC/PLL. After
detection, reset/interrupt request will immediately occurs.
When CLM macro monitors PLL clock (fPLL) and PLL clock stops, clock through is selected (original clock to PLL
input), but the FF/flag of SELPLL/SELPLLS itself is not cleared, so it is necessary to reset chip before select PLL clock
again.
Table 5-4. Clock Monitor Operation Conditions
Condition
fCLK=fSUB
fCLK=fMP/2
N
fIL Stop
fIL Operation
Optionbyte
Clock monitor operation
-
Stop
-
Stop
STOP mode
-
Stop
During oscillation stabilization after
MCM0 setting
-
Stop
Other than the above
CLKMB=1
Stop
CLKMB=0
Operation
As described in above table, fIL must be operated to activate CLM.
fIL operation is controled by the combination of below factor.
-
WDSTBYON option byte
-
WDTON option byte
-
WUTMMCK0 bit
-
Chip status (RUN/HALT/STOP/SNOOZE)
Please refer to the description of “Clock tree” for detail.
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5.5 System Clock Oscillator
5.5.1 X1 oscillator
The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2
pins.
An external clock can also be input. In this case, input the clock signal to the EXCLK pin.
To use the X1 oscillator, set bits 7 and 6 (EXCLK, OSCSEL) of the clock operation mode control register (CMC) as
follows.
Crystal or ceramic oscillation: EXCLK, OSCSEL = 0, 1
External clock input:
EXCLK, OSCSEL = 1, 1
When the X1 oscillator is not used, set the input port mode (EXCLK, OSCSEL = 0, 0).
When the pins are not used as input port pins, either, see Chapter 2.3 Pin I/O Circuits and Recommended
Connection of Unused Pins.
Figure 5-16 shows an example of the external circuit of the X1 oscillator.
Figure 5-15. Example of External Circuit of X1 Oscillator
(a) Crystal or ceramic oscillation
(b) External clock
VSS
X1
X2
External clock
EXCLK
Crystal resonator
or
ceramic resonator
Cautions are listed on the next page.
5.5.2 XT1 oscillator
The XT1 oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins.
To use the XT1 oscillator, set bit 4 (OSCSELS) of the clock operation mode control register (CMC) to 1.
Crystal or ceramic oscillation: OSCSELS = 1
When the XT1 oscillator is not used, set the input port mode (OSCSELS = 0).
When the pins are not used as input port pins, either, see Chapter 2.3 Pin I/O Circuits and Recommended
Connection of Unused Pins.
Figure 5-17 shows an example of the external circuit of the XT1 oscillator.
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Figure 5-16. Example of External Circuit of XT1 Oscillator
(a) Crystal or ceramic oscillation
VSS
XT1
32.768
kHz
XT2
Caution 1. When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the
broken lines in the Figures 5-16 and 5-17 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
The XT1 oscillator is a circuit with low amplification in order to achieve low-power consumption.
Note the following points when designing the circuit.
Pins and circuit boards include parasitic capacitance. Therefore, perform oscillation evaluation
using a circuit board to be actually used and confirm that there are no problems.
Make the wiring between the XT1 and XT2 pins and the resonators as short as possible, and
minimize the parasitic capacitance and wiring resistance. Note this particularly when the ultralow power consumption oscillation (AMPHS1, AMPHS0 = 1, 0) is selected.
Configure the circuit of the circuit board, using material with little wiring resistance.
Place a ground pattern that has the same potential as VSS as much as possible near the XT1
oscillator.
Be sure that the signal lines between the XT1 and XT2 pins, and the resonators do not cross
with the other signal lines. Do not route the wiring near a signal line through which a high
fluctuating current flows.
The impedance between the XT1 and XT2 pins may drop and oscillation may be disturbed due
to moisture absorption of the circuit board in a high-humidity environment or dew
condensation on the board. When using the circuit board in such an environment, take
measures to damp-proof the circuit board, such as by coating.
When coating the circuit board, use material that does not cause capacitance or leakage
between the XT1 and XT2 pins.
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Figure 5-17 shows examples of incorrect resonator connection.
Figure 5-17. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring
(b) Crossed signal line
PORT
VSS
X1
X2
VSS
X1
X2
NG
NG
NG
(c) The X1 and X2 signal line wires cross.
(d) A power supply/GND pattern exists
under the X1 and X2 wires.
VSS
VSS
X1
X1
X2
X2
Note
Power supply/GND pattern
Note
Do not place a power supply/GND pattern under the wiring section (section indicated by a broken line in the
figure) of the X1 and X2 pins and the resonators in a multi-layer board or double-sided board.
Do not configure a layout that will cause capacitance elements and affect the oscillation characteristics.
Remark
When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors
in series on the XT2 side.
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Figure 5-17. Examples of Incorrect Resonator Connection (2/2)
(e) Wiring near high alternating current
(f) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
VDD
Pmn
X1
X2
High current
VSS
VSS
A
X1
B
X2
C
High current
(g) Signals are fetched
VSS
Caution
X1
X2
When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in
malfunctioning.
Remark
When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors
in series on the XT2 side.
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5.5.3 High-speed on-chip oscillator
The high-speed on-chip oscillator is incorporated in the RL78/D1A. The frequency can be selected from among 32, 24,
16, 12, 8, 4, or 1 MHz by using the option byte (000C2H). Oscillation can be controlled by bit 0 (HIOSTOP) of the clock
operation status control register (CSC). The high-speed on-chip oscillator automatically starts oscillating after reset
release.
5.5.4 Low-speed on-chip oscillator
The low-speed on-chip oscillator is incorporated in the RL78/D1A.
The low-speed on-chip oscillator clock is used only as the watchdog timer, real-time clock, and interval timer clock. The
low-speed on-chip oscillator clock cannot be used as the CPU clock.
This clock operates when bit 4 (WDTON) of the option byte (000C0H), bit 4 (WUTMMCK0) of the operation speed
mode control register (OSMC), or both are set to 1.
Unless the watchdog timer is stopped and WUTMMCK0 is a value other than zero, oscillation of the low-speed on-chip
oscillator continues. While the watchdog timer operates, the low-speed on-chip oscillator clock does not stop even if the
program freezes.
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5.6 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby
mode (see Figure 5-1).
Main system clock fMAIN
-
High-speed system clock fMX
X1 clock fX
External main system clock fEX
-
High-speed on-chip oscillator clock fIH
Subsystem clock fSUB
-
XT1 clock fXT
Low-speed on-chip oscillator clock fIL
CPU/peripheral hardware clock fCLK
The CPU starts operation when the high-speed on-chip oscillator starts outputting after a reset release in the RL78/D1A.
When the power supply voltage is turned on, the clock generator operation is shown in Figure 5-19.
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Figure 5-18. Clock Generator Operation When Power Supply Voltage Is Turned On
Power supply
voltage (VDD)
2.7 V
1.51 V
(TYP.)
0V
Internal reset signal
Reset processing
Switched by software
Internal highspeed oscillation clock
CPU clock
High-speed
system clock
Subsystem
clock
Internal high-speed
oscillation clock (fIH)
High-speed
system clock (fMX)
(when X1 oscillation
selected)
Note 1
Subsystem clock (fSUB)
(when XT1 oscillation
selected)
X1 clock
oscillation stabilization timeNote 2
Starting X1 oscillation
is specified by software.
Starting XT1 oscillation
is specified by software.
When the power is turned on, an internal reset signal is generated by the power-on-reset (POR) circuit.
When the power supply voltage exceeds 1.51 V (TYP.), the reset is released and the high-speed on-chip
oscillator automatically starts oscillation.
The CPU starts operation on the high-speed on-chip oscillator clock after a reset processing such as waiting for
the voltage of the power supply or regulator to stabilize has been performed after reset release.
Set the start of oscillation of the X1 or XT1 clock via software (see 5.7.2 Example of setting X1 oscillation
clock and 5.7.3 Example of setting XT1 oscillation clock).
When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set
switching via software (see 5.7.2 Example of setting X1 oscillation clock and 5.7.3 Example of setting XT1
oscillation clock).
Notes 1.
The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed onchip oscillator clock.
2.
When releasing a reset, confirm the oscillation stabilization time for the X1 clock using the oscillation
stabilization time counter status register (OSTC).
3.
Reset processing time: 497 to 720 μs (When LVD is used)
Caution It is not necessary to wait for the oscillation stabilization time when an external clock input from the
EXCLK pin is used.
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5.7 Controlling Clock
5.7.1 Example of controlling high-speed on-chip oscillator
After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip
oscillator clock. The frequency of the high-speed on-chip oscillator can be selected from 32, 24, 16, 8, and 4 MHz by
using FRQSEL0 to FRQSEL3 of the option byte (000C2H).
[Option byte setting]
Address: 000C2H
Option
byte
7
6
5
4
CMODE1
CMODE0
(000C2H)
1
1
1
0
FRQSEL3
FRQSEL2
FRQSEL1
FRQSEL0
1
0
0
0
32 MHz
0
0
0
0
24 MHz
1
0
0
1
16 MHz
1
0
1
0
8 MHz
1
0
1
1
4 MHz
Other than the above
3
2
1
0
FRQSEL3
FRQSEL2
FRQSEL1
FRQSEL0
0/1
0/1
0/1
0/1
Frequency of the high-speed on-chip oscillator
Setting prohibited
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5.7.2 Example of controlling X1 oscillation clock
After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip
oscillator clock. To subsequently change the clock to the X1 oscillation clock, set the oscillator and start oscillation by
using the oscillation stabilization time select register (OSTS) and clock operation mode control register (CMC) and clock
operation status control register (CSC) and wait for oscillation to stabilize by using the oscillation stabilization time
counter status register (OSTC). After the oscillation stabilizes, set the X1 oscillation clock to fCLK by using the system
clock control register (CKC).
[Register settings] Set the register in the order of to below.
Set (1) the OSCSEL bit of the CMC register, except for the cases where fx > 10MHz, in such cases set (1) the
AMPH bit, to operate the X1 oscillator.
CMC
7
6
EXCLK
OSCSEL
0
1
5
4
3
OSCSELS
0
0
2
1
0
AMPHS1
AMPHS0
AMPH
0
0
1
0
AMPH bit: Set this bit to 0 if the X1 oscillation clock is 10 MHz or less.
Using the OSTS register, select the oscillation stabilization time of the X1 oscillator at releasing of the STOP mode.
Example: Setting values when a wait of at least 102.4 s is set based on a 10 MHz resonator.
7
OSTS
0
6
0
5
0
4
0
3
2
1
0
OSTS2
OSTS1
OSTS0
0
1
0
0
0
Clear (0) the MSTOP bit of the CSC register to start oscillating the X1 oscillator.
CSC
7
6
MSTOP
XTSTOP
0
1
5
4
3
2
1
0
0
0
0
0
HIOSTOP
0
Use the OSTC register to wait for oscillation of the X1 oscillator to stabilize.
Example: Wait until the bits reach the following values when a wait of at least 102.4 s is set based on a 10 MHz
resonator.
OSTC
7
6
5
4
3
2
1
0
MOST8
MOST9
MOST10
MOST11
MOST13
MOST15
MOST17
MOST18
1
1
1
0
0
0
0
0
Use the MCM0 bit of the CKC register to specify the X1 oscillation clock as the CPU/peripheral hardware clock.
CKC
7
6
5
4
CLS
CSS
MCS
MCM0
0
0
0
1
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5.7.3 Example of controlling XT1 oscillation clock
After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip
oscillator clock. To subsequently change the clock to the XT1 oscillation clock, set the oscillator and start oscillation by
using the operation speed mode control register (OSMC), clock operation mode control register (CMC), and clock
operation status control register (CSC), set the XT1 oscillation clock to fCLK by using the system clock control register
(CKC).
[Register settings] Set the register in the order of to below.
To run only the real-time clock and interval timer on the subsystem clock (ultra-low current consumption) when in
the STOP mode or sub-HALT mode, set the RTCLPC bit to 1.
7
6
5
RTCLPC
OSMC
0/1
4
3
2
1
0
0
0
0
0
2
1
0
AMPHS1
AMPHS0
AMPH
0/1
0/1
0
WUTMMCK0
0
0
0
Set (1) the OSCSELS bit of the CMC register to operate the XT1 oscillator.
CMC
7
6
EXCLK
OSCSEL
0
0
5
4
3
OSCSELS
0
1
0
AMPHS0 and AMPHS1 bits: These bits are used to specify the oscillation mode of the XT1 oscillator.
Clear (0) the XTSTOP bit of the CSC register to start oscillating the XT1 oscillator.
CSC
7
6
MSTOP
XTSTOP
1
0
5
4
3
2
1
0
0
0
0
0
0
HIOSTOP
0
Use the timer function or another function to wait for oscillation of the subsystem clock to stabilize by using
software.
Use the CSS bit of the CKC register to specify the XT1 oscillation clock as the CPU/peripheral hardware clock.
CKC
7
6
5
4
CLS
CSS
MCS
MCM0
0
1
0
0
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5.7.4 Example of controlling Peripheral clock
In this product, the unnecessary macro clock is stopped in the root for low power consumption and noise attenuation.
The special control registers are configured for the purpose.
Moreover, PCKSEL controls the selection and supply of the operation clock for the asynchronous macro CAN, but
the clock selection bit of SG macro is also in this register, bit0 (SGCLKSEL) in order to save address resources.
Peripheral enable register0 (PER0)
Symbol
7
6
5
4
3
2
1
0
PER0
RTCEN
LIN1EN
LIN0EN
SAU1EN
SAU0EN
TAU2EN
TAU1EN
TAU0EN
Reset init value
R/W (hardware)
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
R/W (user)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Peripheral enable register1 (PER1)
Symbol
7
6
5
4
3
2
1
0
PER1
ADCEN
0
MTRCEN
SGEN
LBEN
0
0
0
Reset init value
R/W (hardware)
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
R/W (user)
R/W
R
R/W
R/W
R/W
R/W
R
R
Peripheral clock select register (PCKSEL)
Symbol
7
6
5
4
3
2
1
0
PCKSEL
0
CAN
CAN
CAN
CAN
0
0
SGCLK
MCKE1
MCK1
MCKE0
MCK0
SEL
Reset init value
R/W (hardware)
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R/W
R/W (user)
R
R/W
R/W
R/W
R/W
R
R
R/W
Control contents of PER0, 1
Bit value
0
Control contents
Stops the input clock supply to peripheral macro.
SFR of peripheral macro can’t be written. (read possible)
Peripheral macro is in reset status.
1
Supplies the input clock to peripheral macro.
SFR of peripheral macro can be written.
The LCD macro connects directly with fIL, fSUB, and fMAIN, and becomes an asynchronization macro like CAN macro.
Inside LCD macro, SCOC bit is used to control LCD sub clock, the low power consumption has been taken into account to
LCD source clock division, so the chip peripheral clock control bit PER/PCKSEL is not configured for LCD macro.
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Controlled by PER0, 1 registers
Bit name
TAU0EN
Input clock (bus & operation) supply of TAU unit0 (TM00-07)
TAU1EN
Input clock (bus & operation) supply of TAU unit1 (TM10-17)
TAU2EN
Input clock (bus & operation) supply of TAU unit2 (TM20-27)
SAU0EN
Input clock (bus & operation) supply of SAU unit0 (CSI00,CSI01)
SAU1EN
Input clock (bus & operation) supply of SAU unit1 (CSI10)
LIN0EN
Input clock (bus & operation) supply of LIN-UART0 (UARTF0)
LIN1EN
Input clock (bus & operation) supply of LIN-UART1 (UARTF1)
RTCEN
Input clock (bus) supply of RTC
ADCEN
Input clock (bus & operation) supply of AD converter
SGEN
MTRCEN
Control object
LBEN
Input clock (bus & operation) supply of SG
Input clock (bus & operation) supply of MTRC
Input clock (bus & operation) supply of LCD bus controller
Operation clock controlled by PCKSEL register
Bit name
CANMCK0
CANMCKE0
CANMCK1
Controlled object
Input clock (operation) supply selection of aFCAN unit0
Supplies/stops control of clock (bus & operation) of aFCAN unit0
Input clock (operation) supply selection of aFCAN unit1
CANMCKE1
Supply/stop control of clock (bus & operation) of aFCAN unit1
SGCLKSEL
Clock (operation) source supply selection of Sound Generator
Selection and supply control of aFCAN0, 1 operation clock
Selection and supply of operation clock
Bus clock supply
CANMCKE0/1
CANMCK0/1
0
x
Clock supply stopped
Clock supply stopped
1
0
fMAIN is supplied
fCLK is supplied
1
1
fMP is supplied
(used for SFR access)
(SFR write is impossible)
(SFR R/W is possible)
Note
fCLK is supplied
(SFR R/W is possible)
Note Wake up interrupt can be generated during CAN sleep mode even if CANMCKEn=0.
SG clock source selection
SGEN
SGCLKSEL
0
x
Clock supply stopped
Selection of operation clock
Clock supply stopped
Bus clock supply
1
0
fCLK is supplied
fCLK is supplied
(SFR write is impossible)
(SFR R/W is possible)
1
1
fCLK/2 is supplied
fCLK is supplied
(SFR R/W is possible)
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5.7.5 CPU clock status transition diagram
Figure 5-19 shows the CPU clock status transition diagram of this product.
Figure 5-19. CPU Clock Status Transition Diagram
Power ON
High-speed on-chip oscillator: Woken up
X1 oscillation/EXCLK input: Stops (input port mode)
XT1 oscillation/EXCLKS input: Stops (input port mode)
VDD < 1.56 V (Typ.)
(A)
Reset release
VDD ≥ 1.56 V (Typ.)
High-speed on-chip oscillator: Operating
X1 oscillation/EXCLK input: Stops (input port mode)
XT1 oscillation/EXCLKS input: Stops (input port mode)
(B)
High-speed on-chip oscillator: Operating
X1 oscillation/EXCLK input: Selectable by CPU
XT1 oscillation/EXCLKS input: Selectable by CPU
VDD ≥ 2.7 V
(H)
CPU: Operating
with high-speed
on-chip oscillator
(M)
(N)
CPU: Low-speed
on-chip oscillator
® HALT
(J)
CPU: Operating
with low-speed
on-chip oscillator
(G)
High-speed on-chip oscillator: Oscillatable
X1 oscillation/EXCLK input: Oscillatable
XT1 oscillation/EXCLKS input: Operating
(E)
CPU: High-speed
on-chip oscillator
® HALT
CPU: Operating with
XT1 oscillation/EXCLKS input
XT1 oscillation/EXCLK input
(C)
High-speed on-chip oscillator:
Selectable by CPU
X1 oscillation/EXCLK input:
Selectable by CPU
CPU: Operating
with X1 oscillation or
EXCLK input
(K)
High-speed on-chip oscillator: Oscillatable
X1 oscillation/EXCLK input: Operating
XT1 oscillation/EXCLKS input:
Selectable by CPU
High-speed on-chip oscillator: Oscillatable
X1 oscillation/EXCLK input: Operating
XT1 oscillation/EXCLKS input:
Selectable by CPU
High-speed on-chip oscillator: Operating
X1 oscillation/EXCLK input: Stops
XT1 oscillation/EXCLKS input:
Oscillatable
CPU: High-speed
on-chip oscillator
® SNOOZE
(D)
CPU: XT1
oscillation/EXCLKS
input ® HALT
High-speed on-chip oscillator: Stops
X1 oscillation/EXCLK input: Stops
XT1 oscillation/EXCLKS input:
Oscillatable
CPU: High-speed
on-chip oscillator
® STOP
CPU: Operating
with PLL (CLS,
MCM0 = 0, 1)
High-speed on-chip oscillator: Operating
X1 oscillation/EXCLK input: Oscillatable
XT1 oscillation/EXCLKS input:
Oscillatable
(I)
CPU: X1
oscillation/EXCLK
input ® STOP
High-speed on-chip oscillator: Stops
X1 oscillation/EXCLK input: Stops
XT1 oscillation/EXCLKS input:
Oscillatable
(F)
High-speed on-chip oscillator: Selectable by CPU
X1 oscillation/EXCLK input: Operating
XT1 oscillation/EXCLKS input:
Selectable by CPU
CPU: X1
oscillation/EXCLK
input ® HALT
High-speed on-chip oscillator: Oscillatable
X1 oscillation/EXCLK input: Operating
XT1 oscillation/EXCLKS input:
Oscillatable
(L)
CPU: PLL operating
(CLS, MCM0 = 0, 1)
® HALT
Caution Transitions in the order of (B) → (D) → (C) or (C) → (D) → (B) are prohibited.
Table 5-5 shows transition of the CPU clock and examples of setting the SFR registers.
Table 5-5. CPU Clock Transition and SFR Register Setting Examples (1/6)
(1) CPU operating with high-speed on-chip oscillator clock (B) after reset release (A)
Status Transition
(A) (B)
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Table 5-5. CPU Clock Transition and SFR Register Setting Examples (2/6)
(2) CPU operating with high-speed system clock (C) after reset release (A)
(The CPU operates with the high-speed on-chip oscillator clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
CMC Register
EXCLK
Status Transition
(A) (B) (C)
OSCSEL
Note1
OSTS
CSC
Register
Register
Register
MSTOP
MCM0
AMPH
CKC
OSTC Register
0
1
0
Note 2
0
1
1
Note 2
0
Must be checked
1
1
1
Note 2
0
Must not be checked
1
0
Must be checked
1
(X1 clock: 1 MHz fX 10 MHz)
(A) (B) (C)
(X1 clock: 10 MHz < fX 20 MHz)
(A) (B) (C)
(external main clock)
Note 1.
The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation
instruction after reset release.
2.
Set the oscillation stabilization time as follows.
Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time
Oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT) and CHAPTER 34 ELECTRICAL
SPECIFICATIONS (L GRADE PRODUCT).
(3) CPU operating with subsystem clock (D) after reset release (A)
(The CPU operates with the high-speed on-chip oscillator clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
CMC Register
Note
CSC
Waiting for
CKC
Register
Oscillation
Register
Status Transition
OSCSELS
AMPHS1
AMPHS0
XTSTOP
Stabilization
CSS
(A) (B) (D)
1
0/1
0/1
0
Necessary
1
1
0
Necessary
1
(XT1 clock)
(A) (B) (D)
(external sub clock)
Note The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation
instruction after reset release.
Remarks 1. ×: don’t care
2. (A) to (J) in Table 5-5 correspond to (A) to (J) in Figure 5-20.
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Table 5-5. CPU Clock Transition and SFR Register Setting Examples (3/6)
(4) CPU clock changing from high-speed on-chip oscillator clock (B) to high-speed system clock (C)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
CMC Register
Note 1
OSTS CSC Register
CKC
OSTC Register
Register
Status Transition
Register
EXCLK OSCSEL AMPH
(B) (C)
MSTOP
MCM0
0
1
0
Note 2
0
Must be checked
1
0
1
1
Note 2
0
Must be checked
1
1
1
Note 2
0
Must not be checked
1
(X1 clock: 1 MHz fX 10 MHz)
(B) (C)
(X1 clock: 10 MHz < fX 20 MHz)
(B) (C)
(external main clock)
Unnecessary if these
Unnecessary if the CPU is operating with the
registers
high-speed system clock
are already set
Notes 1. The clock operation mode control register (CMC) can be changed only once after reset release. This
setting is not necessary if it has already been set.
2. Set the oscillation stabilization time as follows.
Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time
Oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT) and CHAPTER 34 ELECTRICAL
SPECIFICATIONS (L GRADE PRODUCT).
(5) CPU clock changing from high-speed on-chip oscillator clock (B) to subsystem clock (D)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
CMC
CSC Register
Note
Status Transition
(B) (D)
Waiting for
CKC Register
Oscillation
Register
OSCSELS
XTSTOP
Stabilization
CSS
1
0
Necessary
1
(XT1 clock)
Unnecessary if the CPU is operating
with the subsystem clock
Note The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation
instruction after reset release.
Remark
(A) to (J) in Table 5-5 correspond to (A) to (J) in Figure 5-20.
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Table 5-5. CPU Clock Transition and SFR Register Setting Examples (4/6)
(6) CPU clock changing from high-speed system clock (C) to high-speed on-chip oscillator clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(C) (B)
CSC Register
Oscillation accuracy
CKC Register
HIOSTOP
stabilization time
MCM0
0
30 s
0
Unnecessary if the CPU is operating with the
high-speed on-chip oscillator clock
(7) CPU clock changing from high-speed system clock (C) to subsystem clock (D)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(C) (D)
CSC Register
Waiting for Oscillation
CKC Register
XTSTOP
Stabilization
CSS
0
Necessary
1
Unnecessary if the CPU is operating with the
subsystem clock
(8) CPU clock changing from subsystem clock (D) to high-speed on-chip oscillator clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(D) (B)
CSC Register
CKC Register
HIOSTOP
CSS
MCM0
0
0
0
Unnecessary if the CPU
is operating with the
Unnecessary if this
register is already set
high-speed on-chip
oscillator clock
Remark (A) to (J) in Table 5-5 correspond to (A) to (J) in Figure 5-20.
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Table 5-5. CPU Clock Transition and SFR Register Setting Examples (5/6)
(9) CPU clock changing from subsystem clock (D) to high-speed system clock (C)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
OSTS
CSC Register
Register
MSTOP
Note
0
Note
Note
OSTC Register
CKC Register
MCM0
CSS
Must be checked
1
0
0
Must be checked
1
0
0
Must not be checked
1
0
Status Transition
(D) (C) (X1 clock: 1 MHz
fX 10 MHz)
(D) (C) (X1 clock: 10 MHz <
fX 20 MHz)
(D) (C) (external main
clock)
Unnecessary if the CPU is operating with the high-speed
system clock
Note
Unnecessary if these
registers are already set
Set the oscillation stabilization time as follows.
Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time
Oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT) and CHAPTER 34 ELECTRICAL
SPECIFICATIONS (L GRADE PRODUCT).
(10) HALT mode (E) set while CPU is operating with high-speed on-chip oscillator clock (B)
HALT mode (F) set while CPU is operating with high-speed system clock (C)
HALT mode (G) set while CPU is operating with subsystem clock (D)
Status Transition
(B) (E)
Setting
Executing HALT instruction
(C) (F)
(D) (G)
Remark (A) to (J) in Table 5-5 correspond to (A) to (J) in Figure 5-20.
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Table 5-5. CPU Clock Transition and SFR Register Setting Examples (6/6)
(11) STOP mode (H) set while CPU is operating with high-speed on-chip oscillator clock (B)
STOP mode (I) set while CPU is operating with high-speed system clock (C)
(Setting sequence)
Status Transition
(B) (H)
Setting
Stopping peripheral
functions that cannot
(C) (I)
In X1 oscillation
operate in STOP mode
Executing STOP
instruction
Sets the OSTS
register
External main
system clock
(12) CPU changing from STOP mode (H) to SNOOZE mode (J)
For details about the setting for switching from the STOP mode to the SNOOZE mode, see 11.8 SNOOZE Mode
Function.
Remark (A) to (J) in Table 5-5 correspond to (A) to (J) in Figure 5-20.
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5.7.6 Condition before changing CPU clock and processing after changing CPU clock
Condition before changing the CPU clock and processing after changing the CPU clock are shown below.
Table 5-6. Changing CPU Clock (1/2)
CPU Clock
Before Change
Condition Before Change
Processing After Change
After Change
Stabilization of X1 oscillation
Operating current can be reduced by
chip oscillator
OSCSEL = 1, EXCLK = 0, MSTOP = 0
stopping high-speed on-chip oscillator
clock
After elapse of oscillation stabilization time
(HIOSTOP = 1).
High-speed on-
X1 clock
External main
Enabling input of external clock from the
system clock
EXCLK pin
OSCSEL = 1, EXCLK = 1, MSTOP = 0
XT1 clock
Stabilization of XT1 oscillation
OSCSELS = 1, XTSTOP = 0
After elapse of oscillation stabilization time
X1 clock
High-speed on-
Oscillation of high-speed on-chip oscillator
chip oscillator
HIOSTOP = 0
clock
After elapse of oscillation stabilization time
External main
Transition not possible
system clock
(To change the clock, set it again after
XT1 clock
Stabilization of XT1 oscillation
X1 oscillation can be stopped (MSTOP = 1).
executing reset once.)
X1 oscillation can be stopped (MSTOP = 1).
OSCSELS = 1, XTSTOP = 0
After elapse of oscillation stabilization time
External main
High-speed on-
Oscillation of high-speed on-chip oscillator
External main system clock input can be
system clock
chip oscillator
HIOSTOP = 0
disabled (MSTOP = 1).
clock
After elapse of oscillation stabilization time
X1 clock
Transition not possible
(To change the clock, set it again after
executing reset once.)
XT1 clock
Stabilization of XT1 oscillation
External main system clock input can be
OSCSELS = 1, XTSTOP = 0
disabled (MSTOP = 1).
After elapse of oscillation stabilization time
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Table 5-6. Changing CPU Clock (2/2)
CPU Clock
Before Change
XT1 clock
Condition Before Change
Processing After Change
After Change
High-speed on-
Oscillation of high-speed on-chip oscillator
XT1 oscillation can be stopped (XTSTOP =
chip oscillator
and selection of high-speed on-chip
1)
clock
oscillator clock as main system clock
X1 clock
Stabilization of X1 oscillation and selection
HIOSTOP = 0, MCS = 0
of high-speed system clock as main system
clock
OSCSEL = 1, EXCLK = 0, MSTOP = 0
After elapse of oscillation stabilization time
MCS = 1
External main
Enabling input of external clock from the
system clock
EXCLK pin and selection of high-speed
system clock as main system clock
OSCSEL = 1, EXCLK = 1, MSTOP = 0
MCS = 1
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5.7.7 Time required for switchover of CPU clock and main system clock
By setting bits 4 and 6 (MCM0, CSS) of the system clock control register (CKC), the CPU clock can be switched
(between the main system clock and the subsystem clock), and main system clock can be switched (between the highspeed on-chip oscillator clock and the high-speed system clock).
The actual switchover operation is not performed immediately after rewriting to the CKC register; operation continues
on the pre-switchover clock for several clocks (see Table 5-7 to Table 5-9).
Whether the CPU is operating on the main system clock or the subsystem clock can be ascertained using bit 7 (CLS) of
the CKC register. Whether the main system clock is operating on the high-speed system clock or high-speed on-chip
oscillator clock can be ascertained using bit 5 (MCS) of the CKC register.
When the CPU clock is switched, the peripheral hardware clock is also switched.
Table 5-7. Maximum Time Required for Main System Clock Switchover
Clock A
Switching directions
Clock B
Remark
fIH
fMX
See Table 5-8
fMAIN
fSUB
See Table 5-9
Table 5-8. Maximum Number of Clocks Required for fIH fMX
Set Value Before Switchover
Set Value After Switchover
MCM0
MCM0
0
( fMAIN =
fMX
fMX
1
(f MAIN = f MX )
)
f MXf I H
0
(f MAIN = f IH )
1
(f MAIN =
fIH
)
2 clock
{set value of TDRmn
(master) + 1} or if the {set value of TDRmq (slave 2)} > {set value of TDRmn (master) + 1}, it is
summarized into 100% output.
TCRmn of the master channel operates in the interval timer mode and counts the periods.
TCRmp of the slave channel 1 operates in one-count mode, counts the duty factor, and outputs a PWM waveform from
the TOmp pin. TCRmp loads the value of TDRmp to TCRmp, using INTTMmn of the master channel as a start trigger,
and start counting down. When TCRmp = 0000H, TCRmp outputs INTTMmp and stops counting until the next start trigger
(INTTMmn of the master channel) has been input. The output level of TOmp becomes active one count clock after
generation of INTTMmn from the master channel, and inactive when TCRmp = 0000H.
In the same way as TCRmp of the slave channel 1, TCRmq of the slave channel 2 operates in one-count mode, counts
the duty factor, and outputs a PWM waveform from the TOmq pin. TCRmq loads the value of TDRmq to TCRmq, using
INTTMmn of the master channel as a start trigger, and starts counting down. When TCRmq = 0000H, TCRmq outputs
INTTMmq and stops counting until the next start trigger (INTTMmn of the master channel) has been input. The output
level of TOmq becomes active one count clock after generation of INTTMmn from the master channel, and inactive when
TCRmq = 0000H.
When channel 0 is used as the master channel as above, up to seven types of PWM signals can be generated for the
timer array units 0 to 2.
Caution
To rewrite both TDRmn of the master channel and TDRmp of the slave channel 1, write access is
necessary at least twice. Since the values of TDRmn and TDRmp are loaded to TCRmn and TCRmp
after INTTMmn is generated from the master channel, if rewriting is performed separately before and
after generation of INTTMmn from the master channel, the TOmp pin cannot output the expected
waveform. To rewrite both TDRmn of the master and TDRmp of the slave, be sure to rewrite both the
registers immediately after INTTMmn is generated from the master channel (This applies also to
TDRmq of the slave channel 2).
(Remark is given on the next page.)
Remark
m: Unit number (m = 0 to 2), n: Channel number, p, q: Slave channel number 1, 2 (n < p < q 7)
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CKm3
CKm2
Operation clock
CKm1
CKm0
TSmn
Trigger selection
Master channel
(interval timer mode)
Clock selection
Figure 6-81. Block Diagram of Operation as Multiple PWM Output Function (Output Two Types of PWMs)
Timer counter
(TCRmn)
Data register
(TDRmn)
Interrupt
controller
Timer counter
(TCRmp)
Output
controller
Data register
(TDRmp)
Interrupt
controller
Timer counter
(TCRmq)
Output
controller
Data register
(TDRmq)
Interrupt
controller
Interrupt signal
(INTTMmn)
CKm3
CKm2
Operation clock
CKm1
Trigger selection
CKm0
Clock selection
Slave channel 1
(one-count mode)
TOmp pin
Interrupt signal
(INTTMmp)
CKm3
Operation clock
CKm2
CKm1
Trigger selection
CKm0
Clock selection
Slave channel 2
(one-count mode)
TOmq pin
Interrupt signal
(INTTMmq)
Remark m: Unit number (m = 0 to 2), n: Channel number, p, q: Slave channel number 1, 2 (n < p < q 7)
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Figure 6-82. Example of Basic Timing of Operation as Multiple PWM Output Function
(Output Two Types of PWMs)
TSmn
TEmn
FFFFH
Master
channel
TCRmn
0000H
TDRmn
a
b
TOmn
INTTMmn
TSmp
TEmp
FFFFH
Slave
channel 1
TCRmp
0000H
TDRmp
c
d
TOmp
INTTMmp
a+1
a+1
c
c
b+1
d
d
TSmq
TEmq
FFFFH
Slave
channel 2
TCRmq
0000H
TDRmq
e
f
TOmq
INTTMmq
a+1
e
a+1
e
b+1
f
f
Remark m: Unit number (m = 0 to 2), n: Channel number, p, q: Slave channel number 1, 2 (n < p < q 7)
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Figure 6-83. Example of Set Contents of Registers
When Multiple PWM Output Function (Master Channel) Is Used
(a) Timer mode register mn (TMRmn)
15
TMRmn
14
13
1/0
11
10
9
8
7
6
5
4
0
0
MAS
CCSmn
STSmn2 STSmn1 STSmn0 CISmn1 CISmn0
TERmn
CKSmn1 CKSmn0
1/0
12
0
0
0
1
0
0
0
3
2
1
0
MDmn3 MDmn2 MDmn1 MDmn0
0
0
0
0
1
Operation mode of channel n
000B: Interval timer
Setting of operation when counting is started
1: Generates INTTMmn when counting is
started.
Selection of TImn pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
000B: Selects only software start.
Slave/master selection
1: Channel 1 is set as master channel.
Count clock selection
0: Selects operation clock.
Operation clock selection
00B: Selects CKm0 as operation clock of channel n.
01B: Selects CKm1 as operation clock of channel n.
10B: Selects CKm2 as operation clock of channel n.
11B: Selects CKm3 as operation clock of channel n.
(b) Timer output register m (TOm)
Bit n
TOm
0: Outputs 0 from TOmn.
TOmn
0
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
0: Stops the TOmn output operation by counting operation.
0
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOLmn
0: Cleared to 0 when TOMmn = 0 (toggle mode).
0
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOMmn
0: Sets toggle mode.
0
Remark
m: Unit number (m = 0 to 2)
n: Channel number (n = 0 to 7)
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Figure 6-84. Example of Set Contents of Registers
When Multiple PWM Output Function (Slave Channel) Is Used (Output Two Types of PWMs) (1/2)
(a) Timer mode register mp, mq (TMRmp, TMRmq)
15
TMRmp
TMRmq
14
13
1/0
1/0
0
15
14
13
CKSmq1 CKSmq0
1/0
11
10
9
8
7
6
5
4
MAS
CCSmp
STSmp2 STSmp1 STSmp0 CISmp1 CISmp0
TERmp
CKSmp1 CKSmp0
1/0
12
0
12
CCSmq
0
0
1
0
0
0
0
0
0
11
10
9
8
7
6
5
4
MAS
STSmq2 STSmq1 STSmq0 CISmq1 CISmq0
TERmq
1
0
0
0
2
1
0
MDmp3 MDmp2 MDmp1 MDmp0
0
0
3
1
0
0
1
3
2
1
0
MDmq3 MDmq2 MDmq1 MDmq0
0
0
0
1
0
0
1
Operation mode of channel p, q
100B: One-count mode
Start trigger during operation
1: Trigger input is valid.
Selection of TImp and TImq pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
100B: Selects INTTMmn of master channel.
Slave/master selection
0: Channel 0 is set as slave channel.
Count clock selection
0: Selects operation clock.
Operation clock selection
00B: Selects CKm0 as operation clock of channel p, q.
01B: Selects CKm1 as operation clock of channel p, q.
10B: Selects CKm2 as operation clock of channel p, q.
11B: Selects CKm3 as operation clock of channel p, q.
* Make the same setting as master channel.
(b) Timer output register m (TOm)
TOm
Bit q
Bit p
TOmq
TOmp
0: Outputs 0 from TOmp or TOmq.
1/0
1/0
1: Outputs 1 from TOmp or TOmq.
(c) Timer output enable register m (TOEm)
Bit q
TOEm
Bit p
TOEmq TOEmp
1/0
1/0
0: Stops the TOmp or TOmq output operation by counting operation.
1: Enables the TOmp or TOmq output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit q
TOLm
TOLmq TOLmp
1/0
Remark
Bit p
1/0
0: Positive logic output (active-high)
1: Inverted output (active-low)
m: Unit number (m = 0 to 2), n: Channel number, p, q: Slave channel number 1, 2 (n < p < q 7)
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Figure 6-84. Example of Set Contents of Registers
When Multiple PWM Output Function (Slave Channel) Is Used (Output Two Types of PWMs) (2/2)
(e) Timer output mode register m (TOMm)
Bit q
TOMm
TOMmq TOMmp
1
Remark
Bit p
1: Sets the combination operation mode.
1
m: Unit number (m = 0 to 2), n: Channel number, p, q: Slave channel number 1, 2 (n < p < q 7)
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Figure 6-85. Operation Procedure When Multiple PWM Output Function Is Used (1/2)
Software Operation
Hardware Status
Power-off status
TAU
default
(Clock supply is stopped and writing to each register is
setting
disabled.)
Sets the TAU0EN bit, TAU1EN bit of the PER0 register
to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets the TPSm register.
Determines clock frequencies of CKm0 to CKm3.
Channel
Sets the TMRmn, TMRmp, and TMRmq registers of
Channel stops operating.
default
each channel to be used (determines operation mode of
(Clock is supplied and some power is consumed.)
setting
channels).
An interval (period) value is set to the TDRmn register of
the master channel, and a duty factor is set to the
TDRmp and TDRmq registers of the slave channel.
Sets slave channel.
The TOmp and TOmq pins go into Hi-Z output state.
The TOMmp and TOMmq bits of the TOMm register
are set to 1 (combination operation mode).
Clears the TOLmp and TOLmq bits to 0.
Sets the TOmp and TOmq bits and determines default
level of the TOmp and TOmq outputs.
The TOmp and TOmq default setting levels are output
when the port mode register is in output mode and the port
register is 0.
Sets TOEmp and TOEmq to 1 and enables operation
of TOmp and TOmq.
TOmp or TOmq does not change because channel stops
operating.
Operation is resumed (on the next page).
Clears the port register and port mode register to 0.
The TOmp and TOmq pins output the TOmp and TOmq
set levels.
Operation
Sets TOEmp and TOEmq (slave) to 1 (only when
start
operation is resumed).
The TSmn bit (master), and TSmp and TSmq (slave) bits
of the TSm register are set to 1 at the same time.
TEmn = 1, TEmp, TEmq = 1
The TSmn, TSmp, and TSmq bits automatically return
When the master channel starts counting, INTTMmn is
to 0 because they are trigger bits.
generated. Triggered by this interrupt, the slave
channel also starts counting.
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Figure 6-85. Operation Procedure When Multiple PWM Output Function Is Used (2/2)
Operation is resumed (on the before page).
Software Operation
Hardware Status
During
Set values of the TMRmn, TMRmp, TMRmq registers,
The counter of the master channel loads the TDRmn
operation
TOMmn, TOMmp, TOMmq, TOLmn, TOLmp, and TOLmq
value to TCRmn and counts down. When the count value
bits cannot be changed.
reaches TCRmn = 0000H, INTTMmn output is generated.
Set values of the TDRmn, TDRmp, and TDRmq registers
At the same time, the value of the TDRmn register is
can be changed after INTTMmn of the master channel is
loaded to TCRmn, and the counter starts counting down
generated.
again.
The TCRmn, TCRmp, and TCRmq registers can always
At the slave channel 1, the values of TDRmp are
be read.
transferred to TCRmp, triggered by INTTMmn of the
The TSRmn, TSRmp, and TSRmq registers are not used.
master channel, and the counter starts counting down.
Set values of the TOMm, TOLm, TOm, and TOEm
The output levels of TOmp become active one count clock
registers can be changed.
after generation of the INTTMmn output from the master
channel. It becomes inactive when TCRmp = 0000H, and
the counting operation is stopped.
At the slave channel 2, the values of TDRmq are
transferred to TCRmq, triggered by INTTMmn of the
master channel, and the counter starts counting down.
The output levels of TOmq become active one count clock
after generation of the INTTMmn output from the master
channel. It becomes inactive when TCRmq = 0000H, and
the counting operation is stopped.
After that, the above operation is repeated.
Operation The TTmn bit (master), TTmp, and TTmq (slave) bits are
set to 1 at the same time.
stop
The TTmn, TTmp, and TTmq bits automatically return
to 0 because they are trigger bits.
TEmn, TEmp, and TEmq = 0, and count operation stops.
TCRmn, TCRmp, and TCRmq hold count value and
stop.
The TOmp and TOmq outputs are not initialized but hold
current status.
TOEmp or TOEmq of slave channel is cleared to 0
and value is set to the TOmp and TOmq bits.
The TOmp and TOmq pins output the TOmp and TOmq
set levels.
TAU stop
To hold the TOmp and TOmq pin output levels
Clears TOmp and TOmq bits to 0 after
the value to be held is set to the port register.
When holding the TOmp and TOmq pin output levels is
The TOmp and TOmq pin output levels are held by port
function.
not necessary
Switches the port mode register to input mode.
The TOmp and TOmq pin output levels go into Hi-Z
output state.
The TAU0EN bit, TAU1EN bit of the PER0 register are
cleared to 0.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TOmp and TOmq bits are cleared to 0 and the
TOmp and TOmq pins are set to port mode.)
Remark
m: Unit number (m = 0 to 2), n: Channel number, p, q: Slave channel number 1, 2 (n < p < q 7)
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CHAPTER 7 REAL-TIME CLOCK
7.1 Functions of Real-time Clock
The real-time clock has the following features.
Having counters of year, month, week, day, hour, minute, and second, and can count up to 99 years.
Constant-period interrupt function (period: 0.5 seconds, 1 second, 1 minute, 1 hour, 1 day, 1 month)
Alarm interrupt function (alarm: week, hour, minute)
Pin output function of 1 Hz
7.2 Configuration of Real-time Clock
The real-time clock includes the following hardware.
Table 7-1. Configuration of Real-time Clock
Item
Configuration
Counter
Sub-count register
Control registers
Peripheral enable register 0 (PER0)
RTC clock selection register (RTCCL)
Real-time clock control register 0 (RTCC0)
Real-time clock control register 1 (RTCC1)
Second count register (SEC)
Minute count register (MIN)
Hour count register (HOUR)
Day count register (DAY)
Week count register (WEEK)
Month count register (MONTH)
Year count register (YEAR)
Watch error correction register (SUBCUD)
Watch error correction register (SUBCUDW)
Alarm minute register (ALARMWM)
Alarm hour register (ALARMWH)
Alarm week register (ALARMWW)
RTC1Hz pin select register (RTCSEL)
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Figure 7-1. Block Diagram of Real-time Clock
Real-time clock control register 1
WALE
WALIE
WAFG
RIFG
Real-time clock control register 0
RTCE RCLOE1 AMPM
RWST RWAIT
Alarm week
register
(ALARMWW)
(7-bit)
Alarm hour
register
(ALARMWH)
(6-bit)
CT2
CT1
CT0
RTCCL7 RTCCL6 RTCCKS1 RTCCSK0
RTC clock selection
register (RTCCL)
RTC1HZ
Alarm minute
register
(ALARMWM)
(7-bit)
INTRTC
CT0 to CT2
Selector
RIFG
Week count
register
(WEEK)
(3-bit)
AMPM
Year count
register
(YEAR)
(8-bit)
1 day
1 month
Day count
register
(DAY)
(6-bit)
Month count
register
(MONTH)
(5-bit)
1 hour
Hour count
register
(HOUR)
(6-bit)
RWAIT
1 minute
Minute count
register
(MIN)
(7-bit)
Second
count
register
(SEC)
(7-bit)
0.5
seconds
Wait control
Count clock
Sub-count = 32.768 kHz
register
fRTC
(16-bit)
Count enable/
disable circuit
Buffer
Buffer
Buffer
Buffer
Buffer
Buffer
Buffer
Internal bus
RTCE
Watch error
corrention
register
(SUBCUD(8-bit)
/SUBCUDW
(16-bit))
Selector
RWST
1 year
fSUB
fIL
fMX/122
fMX/128
fMX/244
fMX/256
fIH/122
fIH/128
fIH/244
fIH/256
RTCCL7, 6, RTCCK1, 0
Caution The count of year, month, week, day, hour, minutes and second can only be performed when a
subsystem clock (fSUB = 32.768 kHz) or the divided clock of fMX and fIH nearly equal to 32.768kHz
is selected as the operation clock of the real-time clock.
When the low-speed oscillation clock (fIL = 15 kHz) is selected, only the constant-period interrupt
function is available. However, the constant-period interrupt interval when fIL is selected will be
calculated with the constant-period (the value selected with RTCC0 register) × fSUB/fIL.
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7.3 Registers Controlling Real-time Clock
The real-time clock is controlled by the following registers.
• Peripheral enable register 0 (PER0)
• RTC clock selection register (RTCCL)
• Real-time clock control register 0 (RTCC0)
• Real-time clock control register 1 (RTCC1)
• Second count register (SEC)
• Minute count register (MIN)
• Hour count register (HOUR)
• Day count register (DAY)
• Week count register (WEEK)
• Month count register (MONTH)
• Year count register (YEAR)
• Watch error correction register (SUBCUD)
• Watch error correction register (SUBCUDW)
• Alarm minute register (ALARMWM)
• Alarm hour register (ALARMWH)
• Alarm week register (ALARMWW)
• RTC1Hz pin select register (RTCSEL)
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(1) Peripheral enable register 0 (PER0)
This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a
hardware macro that is not used is stopped in order to reduce the power consumption and noise.
When the real-time clock is used, be sure to set bit 7 (RTCEN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-2. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H
After reset: 00H
R/W
Symbol
PER0
RTCEN
LIN1EN
LIN0EN
SAU1EN
SAU0EN
TAU2EN
TAU1EN
TAU0EN
RTCEN
Control of real-time clock (RTC) and interval timer input clock supply
Stops input clock supply.
0
SFR used by the real-time clock (RTC) and interval timer cannot be written.
The real-time clock (RTC) and interval timer are in the reset status.
Enables input clock supply.
1
SFR used by the real-time clock (RTC) and interval timer can be read and written.
Cautions 1. When using the real-time clock, first set the RTCEN bit to 1, while oscillation of the
input clock (fRTC) is stable. If RTCEN = 0, writing to a control register of the real-time
clock or interval timer is ignored, and, even if the register is read, only the default
value is read.
2. The subsystem clock supply to peripheral functions other than the real-time clock
and interval timer can be stopped in STOP mode or HALT mode when the subsystem
clock is used, by setting the RTCLPC bit of the operation speed mode control
register (OSMC) to 1. In this case, set the RTCEN bit of the PER0 register to 1 and
the other bits (bits 0 to 6) to 0.
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(2) RTC clock selection register (RTCCL)
Figure 7-3. Format of RTC clock selection register (RTCCL)
Address: F00F9H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
RTCCL
RTCCL7
RTCCL6
0
0
0
0
RTCCKS1
RTCCKS0
RTCCL7
Operation clock source selection for RTC/interval timer
0
RTC/interval timer uses External Main clock (fMX)
1
RTC/interval timer uses High-speed on-chip oscillator clock (fIH)
RTCCKS1
RTCCKS0
RTCCL6
0
0
0/1
0
1
Operation selection of RTC macro and interval timer
Sub clock (fSUB)
Low-speed on-chip oscillator clock (fIL,15K@typ)
(WUTMMCK0 should be “1” to use this selection)
1
0
0
External Main or High-speed on-chip oscillator clock
(after selected by RTCCL7) /27
1
1
0
External Main or High-speed on-chip oscillator clock
(after selected by RTCCL7) /28
1
0
1
1
1
1
External Main or High-speed on-chip oscillator clock
(after selected by RTCCL7) /122
External Main or High-speed on-chip oscillator clock
(after selected by RTCCL7)/244
Caution
WUTMMCK0 should be set to “1” when fIL is used for RTC/interval timer clock.
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(3) Watch error correction register (SUBCUDW)
This register is used to correct the watch with high accuracy when it is slow or fast by changing the value that
overflows from the sub-count register to the second count register (SEC) (reference value: 7FFFH).
The SUBCUDW register can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Figure 7-4. Format of Watch Error Correction Register (SUBCUDW)
Address: FFF34H
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
SUBCUDW
DEV
0
0
F12
F11
F10
F9
F8
7
6
5
4
3
2
1
0
F7
F6
F5
F4
F3
F2
F1
F0
DEV
Setting of watch error correction timing
0
Corrects watch error when the second digits are at 00, 20, or 40 (every 20 seconds).
1
Corrects watch error only when the second digits are at 00 (every 60 seconds).
Writing to the SUBCUD register at the following timing is prohibited.
When DEV = 0 is set: For a period of SEC = 00H, 20H, 40H
When DEV = 1 is set: For a period of SEC = 00H
F12
Setting of watch error correction value
0
Increases by {(F11, F10, F9, F8, F7, F6, F5, F4, F3, F2, F1, F0) – 1} 2.
1
Decreases by {(/F11, /F10, /F9, /F8, /F7, /F6, /F5, /F4, /F3, /F2, /F1, /F0) + 1} 2.
Note
When (F12, F11, F10, F9, F8, F7, F6, F5, F4, F3, F2, F1, F0) = (0,0,0,0,0,0,0,0,0,0,0,0,0), (0,0,0,0,0,0,0,0,0,0,0,0,1),
(1,0,0,0,0,0,0,0,0,0,0,0,0) or (1,0,0,0,0,0,0,0,0,0,0,0,1), the watch error is not corrected.
Range of correction value:
(when F12 = 0) 2, 4, 6, 8, … , 8186, 8188
(when F12 = 1) –2, –4, –6, –8, … , -8186, -8188
Note
"/" means bit-inverted values.
The range of value that can be corrected by using the watch error correction register (SUBCUDW) is shown below.
DEV = 0 (correction every 20 seconds)
DEV = 1 (correction every 60 seconds)
Correctable range
-12496.9 ppm to 12496.9 ppm
-4165.6 ppm to 4165.6 ppm
Maximum excludes
1.53 ppm
0.51 ppm
3.05 ppm
1.02 ppm
quantization error
Minimum resolution
Caution When correcting the RTC, use either this register or the watch error correction register
(SUBCUD) in (13).
Remark If the correctable range is -4165.6 ppm or lower and 4165.6 ppm or higher, set DEV to 0.
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(4) Real-time clock control register 0 (RTCC0)
The RTCC0 register is an 8-bit register that is used to start or stop the real-time clock operation, control the
RTC1HZ pin, and set a 12- or 24-hour system and the constant-period interrupt function.
The RTCC0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-5. Format of Real-time Clock Control Register 0 (RTCC0)
Address: FFF5DH
After reset: 00H
R/W
Symbol
6
4
3
2
1
0
RTCC0
RTCE
0
RCLOE1
0
AMPM
CT2
CT1
CT0
RTCE
Real-time clock operation control
0
Stops counter operation.
1
Starts counter operation.
RCLOE1
RTC1HZ pin output control
0
Disables output of the RTC1HZ pin (1 Hz).
1
Enables output of the RTC1HZ pin (1 Hz).
AMPM
Selection of 12-/24-hour system
0
12-hour system (a.m. and p.m. are displayed.)
1
24-hour system
Rewrite the AMPM bit value after setting the RWAIT bit (bit 0 of real-time clock control register 1 (RTCC1)) to 1. If
the AMPM bit value is changed, the values of the hour count register (HOUR) change according to the specified
time system.
Table 7-2 shows the displayed time digits that are displayed.
CT2
CT1
CT0
Constant-period interrupt (INTRTC) selection
0
0
0
Does not use constant-period interrupt function.
0
0
1
Once per 0.5 s (synchronized with second count up)
0
1
0
Once per 1 s (same time as second count up)
0
1
1
Once per 1 m (second 00 of every minute)
1
0
0
Once per 1 hour (minute 00 and second 00 of every hour)
1
0
1
Once per 1 day (hour 00, minute 00, and second 00 of every day)
1
1
Once per 1 month (Day 1, hour 00 a.m., minute 00, and second 00 of
every month)
When changing the values of the CT2 to CT0 bits while the counter operates (RTCE = 1), rewrite the values of the
CT2 to CT0 bits after disabling interrupt servicing INTRTC by using the interrupt mask flag register. Furthermore,
after rewriting the values of the CT2 to CT0 bits, enable interrupt servicing after clearing the RIFG and RTCIF flags.
Caution Do not change the value of the RTCLOE1 bit when RTCE = 1.
Remark : don’t care
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(5) Real-time clock control register 1 (RTCC1)
The RTCC1 register is an 8-bit register that is used to control the alarm interrupt function and the wait time of the
counter.
The RTCC1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-6. Format of Real-time Clock Control Register 1 (RTCC1) (1/2)
Address: FFF5EH
After reset: 00H
R/W
Symbol
5
2
RTCC1
WALE
WALIE
0
WAFG
RIFG
0
RWST
RWAIT
WALE
Alarm operation control
0
Match operation is invalid.
1
Match operation is valid.
When setting a value to the WALE bit while the counter operates (RTCE = 1) and WALIE = 1, rewrite the WALE bit
after disabling interrupt servicing INTRTC by using the interrupt mask flag register. Furthermore, clear the WAFG
and RTCIF flags after rewriting the WALE bit. When setting each alarm register (WALIE flag of real-time clock
control register 1 (RTCC1), the alarm minute register (ALARMWM), the alarm hour register (ALARMWH), and the
alarm week register (ALARMWW)), set match operation to be invalid (“0”) for the WALE bit.
WALIE
Control of alarm interrupt (INTRTC) function operation
0
Does not generate interrupt on matching of alarm.
1
Generates interrupt on matching of alarm.
WAFG
Alarm detection status flag
0
Alarm mismatch
1
Detection of matching of alarm
This is a status flag that indicates detection of matching with the alarm. It is valid only when WALE = 1 and is set to
“1” one clock (32.768 kHz) after matching of the alarm is detected. This flag is cleared when “0” is written to it.
Writing “1” to it is invalid.
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Figure 7-7. Format of Real-time Clock Control Register 1 (RTCC1) (2/2)
RIFG
Constant-period interrupt status flag
0
Constant-period interrupt is not generated.
1
Constant-period interrupt is generated.
This flag indicates the status of generation of the constant-period interrupt. When the constant-period interrupt is
generated, it is set to “1”.
This flag is cleared when “0” is written to it. Writing “1” to it is invalid.
RWST
Wait status flag of real-time clock
0
Counter is operating.
1
Mode to read or write counter value
This status flag indicates whether the setting of the RWAIT bit is valid.
Before reading or writing the counter value, confirm that the value of this flag is 1.
RWAIT
Wait control of real-time clock
0
Sets counter operation.
1
Stops SEC to YEAR counters. Mode to read or write counter value
This bit controls the operation of the counter.
Be sure to write “1” to it to read or write the counter value.
As the sub-count register is continuing to run, complete reading or writing within one second and turn back to 0.
When RWAIT = 1, it takes up to 1 clock (fRTC) until the counter value can be read or written (RWST = 1).
When the sub-count register overflowed while RWAIT = 1, it keeps the event of overflow until RWAIT = 0, then
counts up.
However, when it wrote a value to second count register, it will not keep the overflow event.
Caution If writing is performed to the RTCC1 register with a 1-bit manipulation instruction, the RIFG flag
and WAFG flag may be cleared. Therefore, to perform writing to the RTCC1 register, be sure to
use an 8-bit manipulation instruction.
To prevent the RIFG flag and WAFG flag from being
cleared during writing, disable writing by setting 1 to the corresponding bit. If the RIFG flag and
WAFG flag are not used and the value may be changed, the RTCC1 register may be written by
using a 1-bit manipulation instruction.
Remark Fixed-cycle interrupts and alarm match interrupts use the same interrupt source (INTRTC). When using
these two types of interrupts at the same time, which interrupt occurred can be judged by checking the
fixed-cycle interrupt status flag (RIFG) and the alarm detection status flag (WAFG) upon INTRTC
occurrence.
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(6) Second count register (SEC)
The SEC register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of
seconds.
It counts up when the sub-counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (fRTC) later. Set a
decimal value of 00 to 59 to this register in BCD code.
The SEC register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-8. Format of Second Count Register (SEC)
Address: FFF52H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
SEC
0
SEC40
SEC20
SEC10
SEC8
SEC4
SEC2
SEC1
Caution When it reads or writes from/to the register while the counter is in operation (RTCE = 1), follow
the procedures described in the section 7.4.3 Reading/writing real-time clock.
(7) Minute count register (MIN)
The MIN register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of minutes.
It counts up when the second counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (fRTC) later. Even
if the second count register overflows while this register is being written, this register ignores the overflow and is set
to the value written. Set a decimal value of 00 to 59 to this register in BCD code.
The MIN register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-9. Format of Minute Count Register (MIN)
Address: FFF53H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
MIN
0
MIN40
MIN20
MIN10
MIN8
MIN4
MIN2
MIN1
Caution When it reads or writes from/to the register while the counter is in operation (RTCE = 1), follow
the procedures described in the section 7.4.3 Reading/writing real-time clock.
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(8) Hour count register (HOUR)
The HOUR register is an 8-bit register that takes a value of 00 to 23 or 01 to 12 and 21 to 32 (decimal) and
indicates the count value of hours.
It counts up when the minute counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (fRTC) later. Even
if the minute count register overflows while this register is being written, this register ignores the overflow and is set
to the value written. Specify a decimal value of 00 to 23, 01 to 12, or 21 to 32 by using BCD code according to the
time system specified using bit 3 (AMPM) of real-time clock control register 0 (RTCC0).
If the AMPM bit value is changed, the values of the HOUR register change according to the specified time system.
The HOUR register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 12H.
However, the value of this register is 00H if the AMPM bit is set to 1 after reset.
Figure 7-10. Format of Hour Count Register (HOUR)
Address: FFF54H
After reset: 12H
R/W
Symbol
7
6
5
4
3
2
1
0
HOUR
0
0
HOUR20
HOUR10
HOUR8
HOUR4
HOUR2
HOUR1
Cautions 1. Bit 5 (HOUR20) of the HOUR register indicates AM(0)/PM(1) if AMPM = 0 (if the 12-hour system
is selected).
2. When it reads or writes from/to the register while the counter is in operation (RTCE = 1),
follow the procedures described in the section 7.4.3 Reading/writing real-time clock.
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Table 7-2 shows the relationship between the setting value of the AMPM bit, the hour count register (HOUR) value, and
time.
Table 7-2. Displayed Time Digits
24-Hour Display (AMPM = 1)
12-Hour Display (AMPM = 1)
Time
HOUR Register
Time
HOUR Register
0
00H
0 a.m.
12H
1
01H
1 a.m.
01H
2
02H
2 a.m.
02H
3
03H
3 a.m.
03H
4
04H
4 a.m.
04H
5
05H
5 a.m.
05H
6
06H
6 a.m.
06H
7
07H
7 a.m.
07H
8
08H
8 a.m.
08H
9
09H
9 a.m.
09H
10
10H
10 a.m.
10H
11
11H
11 a.m.
11H
12
12H
0 p.m.
32H
13
13H
1 p.m.
21H
14
14H
2 p.m.
22H
15
15H
3 p.m.
23H
16
16H
4 p.m.
24H
17
17H
5 p.m.
25H
18
18H
6 p.m.
26H
19
19H
7 p.m.
27H
20
20H
8 p.m.
28H
21
21H
9 p.m.
29H
22
22H
10 p.m.
30H
23
23H
11 p.m.
31H
The HOUR register value is set to 12-hour display when the AMPM bit is “0” and to 24-hour display when the AMPM bit
is “1”.
In 12-hour display, the fifth bit of the HOUR register displays 0 for AM and 1 for PM.
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(9) Day count register (DAY)
The DAY register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days.
It counts up when the hour counter overflows.
This counter counts as follows.
01 to 31 (January, March, May, July, August, October, December)
01 to 30 (April, June, September, November)
01 to 29 (February, leap year)
01 to 28 (February, normal year)
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (fRTC) later. Even
if the hour count register overflows while this register is being written, this register ignores the overflow and is set to
the value written. Set a decimal value of 01 to 31 to this register in BCD code.
The DAY register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 01H.
Figure 7-11. Format of Day Count Register (DAY)
Address: FFF56H
After reset: 01H
R/W
Symbol
7
6
5
4
3
2
1
0
DAY
0
0
DAY20
DAY10
DAY8
DAY4
DAY2
DAY1
Caution When it reads or writes from/to the register while the counter is in operation (RTCE = 1), follow
the procedures described in the section 7.4.3 Reading/writing real-time clock.
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(10) Week count register (WEEK)
The WEEK register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the count value of
weekdays.
It counts up in synchronization with the day counter.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (fRTC) later. Set a
decimal value of 00 to 06 to this register in BCD code.
The WEEK register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-12. Format of Week Count Register (WEEK)
Address: FFF55H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
WEEK
0
0
0
0
0
WEEK4
WEEK2
WEEK1
Cautions 1. The value corresponding to the month count register (MONTH) or the day count register (DAY)
is not stored in the week count register (WEEK) automatically. After reset release, set the
week count register as follow.
Day
WEEK
Sunday
00H
Monday
01H
Tuesday
02H
Wednesday
03H
Thursday
04H
Friday
05H
Saturday
06H
2. When it reads or writes from/to the register while the counter is in operation (RTCE = 1),
follow the procedures described in the section 7.4.3 Reading/writing real-time clock.
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(11) Month count register (MONTH)
The MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value of
months.
It counts up when the day counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (fRTC) later. Even
if the day count register overflows while this register is being written, this register ignores the overflow and is set to
the value written. Set a decimal value of 01 to 12 to this register in BCD code.
The MONTH register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 01H.
Figure 7-13. Format of Month Count Register (MONTH)
Address: FFF57H
After reset: 01H
R/W
Symbol
7
6
5
4
3
2
1
0
MONTH
0
0
0
MONTH10
MONTH8
MONTH4
MONTH2
MONTH1
Caution When it reads or writes from/to the register while the counter is in operation (RTCE = 1), follow
the procedures described in the section 7.4.3 Reading/writing real-time clock.
(12) Year count register (YEAR)
The YEAR register is an 8-bit register that takes a value of 0 to 99 (decimal) and indicates the count value of years.
It counts up when the month count register (MONTH) overflows.
Values 00, 04, 08, …, 92, and 96 indicate a leap year.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (fRTC) later. Even
if the MONTH register overflows while this register is being written, this register ignores the overflow and is set to
the value written. Set a decimal value of 00 to 99 to this register in BCD code.
The YEAR register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-14. Format of Year Count Register (YEAR)
Address: FFF58H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
YEAR
YEAR80
YEAR40
YEAR20
YEAR10
YEAR8
YEAR4
YEAR2
YEAR1
Caution When it reads or writes from/to the register while the counter is in operation (RTCE = 1), follow
the procedures described in the section 7.4.3 Reading/writing real-time clock.
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(13) Watch error correction register (SUBCUD)
This register is used to correct the watch with high accuracy when it is slow or fast by changing the value that
overflows from the sub-count register to the second count register (SEC) (reference value: 7FFFH).
The SUBCUD register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-15. Format of Watch Error Correction Register (SUBCUD)
Address: FFF59H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
SUBCUD
DEV
F6
F5
F4
F3
F2
F1
F0
DEV
Setting of watch error correction timing
0
Corrects watch error when the second digits are at 00, 20, or 40 (every 20 seconds).
1
Corrects watch error only when the second digits are at 00 (every 60 seconds).
Writing to the SUBCUD register at the following timing is prohibited.
When DEV = 0 is set: For a period of SEC = 00H, 20H, 40H
When DEV = 1 is set: For a period of SEC = 00H
F6
Setting of watch error correction value
0
Increases by {(F5, F4, F3, F2, F1, F0) – 1} 2.
1
Decreases by {(/F5, /F4, /F3, /F2, /F1, /F0) + 1} 2.
Note1
When (F6,F5,F4,F3,F2,F1,F0)=(0,0,0,0,0,0,0) or (0,0,0,0,0,0,1), the watch error is not corrected.
Range of correction value: (when F6=0) 2,4,6,7,...,120,122
(when F6=1) -2,-4,-6,-8,...,-120,-122,-124
Note 2
Notes 1. "/" means bit-inverted values.
2. It is not recommended to set (F6,F5,F4,F3,F2,F1,F0)=(1,0,0,0,0,0,0) or (1,0,0,0,0,0,1).
The range of value that can be corrected by using the watch error correction register (SUBCUD) is shown below.
DEV = 0 (correction every 20 seconds)
DEV = 1 (correction every 60 seconds)
Correctable range
-189.2 ppm to 189.2 ppm
-63.1 ppm to 63.1 ppm
Maximum excludes
1.53 ppm
0.51 ppm
3.05 ppm
1.02 ppm
quantization error
Minimum resolution
Caution When correcting the RTC, use either this register or the watch error correction register
(SUBCUDW) in (3). When SUBCUDW is used, however, the correction value cannot be judged
correctly by reading SUBCUD.
Remark If a correctable range is -63.1 ppm or lower and 63.1 ppm or higher, set 0 to DEV.
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(14) Alarm minute register (ALARMWM)
This register is used to set minutes of alarm.
The ALARMWM register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Caution
Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the range is set,
the alarm is not detected.
Figure 7-16. Format of Alarm Minute Register (ALARMWM)
Address: FFF5AH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
ALARMWM
0
WM40
WM20
WM10
WM8
WM4
WM2
WM1
(15) Alarm hour register (ALARMWH)
This register is used to set hours of alarm.
The ALARMWH register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 12H.
However, the value of this register is 00H if the AMPM bit is set to 1 after reset.
Caution
Set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in BCD code. If a value
outside the range is set, the alarm is not detected.
Figure 7-17. Format of Alarm Hour Register (ALARMWH)
Address: FFF5BH
After reset: 12H
R/W
Symbol
7
6
5
4
3
2
1
0
ALARMWH
0
0
WH20
WH10
WH8
WH4
WH2
WH1
Caution Bit 5 (WH20) of the ALARMWH register indicates AM(0)/PM(1) if AMPM = 0 (if the 12-hour system
is selected).
(16) Alarm week register (ALARMWW)
This register is used to set date of alarm.
The ALARMWW register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-18. Format of Alarm Week Register (ALARMWW)
Address: FFF5CH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
ALARMWW
0
WW6
WW5
WW4
WW3
WW2
WW1
WW0
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Here is an example of setting the alarm.
Time of Alarm
Day
12-Hour Display
Sunday Monday Tuesday Wednesday Thursday Friday Saturday Hour
Hour
24-Hour Display
Minute Minute
Hour
Hour
Minute Minute
10
1
10
1
10
1
10
1
W
W
W
W
W
W
W
W
W
W
W
W
W
W
0
1
2
3
4
5
6
Every day, 0:00 a.m.
1
1
1
1
1
1
1
1
2
0
0
0
0
0
0
Every day, 1:30 a.m.
1
1
1
1
1
1
1
0
1
3
0
0
1
3
0
Every day, 11:59 a.m.
1
1
1
1
1
1
1
1
1
5
9
1
1
5
9
Monday through
Friday, 0:00 p.m.
0
1
1
1
1
1
0
3
2
0
0
1
2
0
0
Sunday, 1:30 p.m.
1
0
0
0
0
0
0
2
1
3
0
1
3
3
0
Monday, Wednesday,
Friday, 11:59 p.m.
0
1
0
1
0
1
0
3
1
5
9
2
3
5
9
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(17) RTC1Hz pin select register (RTCSEL)
This register is used to select the pin to output RTC1Hz signal. The RTCSEL register can be selected by 1-bit or
8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Figure 7-19. Format of RTC1Hz pin Select Register (RTCSEL)
Address: FFFF36
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
RTCSEL
RTCOSEL1
RTCOSEL0
0
0
RTCTIS11
RTCTIS10
RTCTIS01
RTCTIS00
RTCTIS00
Switch RTC1Hz output to TAU TI06 input or not
0
Disconnected to TI06
1
Connected to TI06
RTCTIS01
Switch RTC1Hz output to TAU TI07 input or not
0
Disconnected to TI07
1
Connected to TI07
RTCTIS10
Switch RTC1Hz output to TAU TI16 input or not
0
Disconnected to TI16
1
Connected to TI16
RTCTIS11
Switch RTC1Hz output to TAU TI17 input or not
0
Disconnected to TI17
1
Connected to TI17
RTCOSEL1
RTCOSEL0
RTC1Hz output pin selection
0
0
P64
0
1
P15
1
0
P94
1
1
No port is selected (Output disabled)
To measure 1Hz, two channels of TAU should be used because 16-bit counter will be overflowed if fCLK is fast
frequency. A channel is operated in pulse width measurement mode. Low-level or high-level width of 1Hz pulse is typically
500ms. Another channel is operated in interval timer mode (start trigger is set to TIN edge) and number of overflow should
be counted by software at the interrupt timing. The measurement is finished when interrupt by capture channel is occurred.
The interval time can be calculated by software-overflow-counter and TDR register of capture channel.
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7.4 Real-time Clock Operation
7.4.1 Starting operation of real-time clock
Figure 7-20. Procedure for Starting Operation of Real-time Clock
Start
RTCEN = 1Note 1
RTCE = 0
Setting AMPM, CT2 to CT0
Supplies input clock.
Stops counter operation.
Selects 12-/24-hour system and interrupt (INTRTC).
Setting SEC
Sets second count register.
Setting MIN
Sets minute count register.
Setting HOUR
Sets hour count register.
Setting WEEK
Sets week count register.
Setting DAY
Setting MONTH
Setting YEAR
Setting SUBCUDNote 2
Sets day count register.
Sets month count register.
Sets year count register.
Sets watch error correction register.
Clearing IF flags of interrupt
Clears interrupt request flags (RTCIF, RTCIIF).
Clearing MK flags of interrupt
Clears interrupt mask flags (RTCMK, RTCIMK).
RTCE = 1Note 3
Starts counter operation.
Yes
No
INTRTC = 1?
Reading counter
Notes 1. First set the RTCEN bit to 1, while oscillation of the input clock (fRTC) is stable.
2. Set up the SUBCUD register only if the watch error must be corrected. For details about how to
calculate the correction value, see 7.4.6 Example of watch error correction of real-time clock.
3. Confirm the procedure described in 7.4.2 Shifting to STOP mode after starting operation when
shifting to STOP mode without waiting for INTRTC = 1 after RTCE = 1.
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7.4.2 Shifting to HALT/STOP mode after starting operation
Perform one of the following processing when shifting to HALT/STOP mode immediately after setting the RTCE bit to 1.
However, after setting the RTCE bit to 1, this processing is not required when shifting to HALT/STOP mode after the
first INTRTC interrupt has occurred.
Shifting to HALT/STOP mode when at least two input clocks (fRTC) have elapsed after setting the RTCE bit to 1 (see
Figure 7-21, Example 1).
Checking by polling the RWST bit to become 1, after setting the RTCE bit to 1 and then setting the RWAIT bit to 1.
Afterward, setting the RWAIT bit to 0 and shifting to HALT/STOP mode after checking again by polling that the RWST
bit has become 0 (see Figure 7-21, Example 2).
Figure 7-21. Procedure for Shifting to HALT/STOP Mode After Setting RTCE bit to 1
Example 1
Example 2
Sets to counter operation
RTCE = 1
Sets to counter operation
start
RTCE = 1
Waiting at least for 2
fRTC clocks
HALT/STOP instruction
Shifts to HALT/STOP mode
No
start
RWAIT = 1
Sets to stop the SEC to YEAR
counters, reads the counter
value, write mode
RWST = 1 ?
Checks the counter wait status
Yes
execution
RWAIT = 0
No
Sets the counter operation
RWST = 0 ?
Yes
HALT/STOP instruction
execution
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CHAPTER 7 REAL-TIME CLOCK
7.4.3 Reading/writing real-time clock
Read or write the counter after setting 1 to RWAIT first.
Set RWAIT to 0 after completion of reading or writing the counter.
Figure 7-22. Procedure for Reading Real-time Clock
Start
No
RWAIT = 1
Stops SEC to YEAR counters.
Mode to read and write count values
RWST = 1?
Checks wait status of counter.
Yes
Reading SEC
Reads second count register.
Reading MIN
Reads minute count register.
Reading HOUR
Reads hour count register.
Reading WEEK
Reads week count register.
Reading DAY
Reading MONTH
Reading YEAR
RWAIT = 0
No
Reads day count register.
Reads month count register.
Reads year count register.
Sets counter operation.
RWST = 0?Note
Yes
End
Note Be sure to confirm that RWST = 0 before setting STOP mode.
Caution Complete the series of operations of setting the RWAIT bit to 1 to clearing the RWAIT bit to 0 within 1
second.
Remark
The second count register (SEC), minute count register (MIN), hour count register (HOUR), week count
register (WEEK), day count register (DAY), month count register (MONTH), and year count register (YEAR)
may be read in any sequence.
All the registers do not have to be set and only some registers may be read.
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Figure 7-23. Procedure for Writing Real-time Clock
Start
No
RWAIT = 1
Stops SEC to YEAR counters.
Mode to read and write count values
RWST = 1?
Checks wait status of counter.
Yes
Writing SEC
Writes second count register.
Writing MIN
Writes minute count register.
Writing HOUR
Writes hour count register.
Writing WEEK
Writes week count register.
Writing DAY
Writing MONTH
No
Writes day count register.
Writes month count register.
Writing YEAR
Writes year count register.
RWAIT = 0
Sets counter operation.
RWST = 0?Note
Yes
End
Note Be sure to confirm that RWST = 0 before setting STOP mode.
Caution
1. Complete the series of operations of setting the RWAIT bit to 1 to clearing the RWAIT bit to 0
within 1 second.
2. When changing the values of the SEC, MIN, HOUR, WEEK, DAY, MONTH, and YEAR register
while the counter operates (RTCE = 1), rewrite the values of the MIN register after disabling
interrupt servicing INTRTC by using the interrupt mask flag register. Furthermore, clear the
WAFG, RIFG and RTCIF flags after rewriting the MIN register.
Remark
The second count register (SEC), minute count register (MIN), hour count register (HOUR), week count
register (WEEK), day count register (DAY), month count register (MONTH), and year count register (YEAR)
may be written in any sequence.
All the registers do not have to be set and only some registers may be written.
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7.4.4 Setting alarm of real-time clock
Set time of alarm after setting 0 to WALE first.
Figure 7-24. Alarm Setting Procedure
Start
WALE = 0
Match operation of alarm is invalid.
WALIE = 1
Interrupt is generated when alarm matches.
Setting ALARMWM
Sets alarm minute register.
Setting ALARMWH
Sets alarm hour register.
Setting ALARMWW
Sets alarm week register.
WALE = 1
No
Match operation of alarm is valid.
INTRTC = 1?
Yes
WAFG = 1?
No
Match detection of alarm Yes
Alarm processing
Constant-period interrupt servicing
Remarks 1. The alarm week register (ALARMWW), alarm hour register (ALARMWH), and alarm week register
(ALARMWW) may be written in any sequence.
2. Fixed-cycle interrupts and alarm match interrupts use the same interrupt source (INTRTC). When using
these two types of interrupts at the same time, which interrupt occurred can be judged by checking the
fixed-cycle interrupt status flag (RIFG) and the alarm detection status flag (WAFG) upon INTRTC
occurrence.
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7.4.5 1 Hz output of real-time clock
Figure 7-25. 1 Hz Output Setting Procedure
Start
RTCSEL = xx
PMxx = 0
Pxx = 0
RTCE = 0
RCLOE1 = 1
RTCE = 1
Selects output port (P64/P15/P94)
Sets port mode register to output port mode
Sets 0 to output latch of port
Stops counter operation.
Enables output of the RTC1HZ pin (1 Hz).
Starts counter operation.
Output start from RTC1HZ pin
Caution First set the RTCEN bit to 1, while oscillation of the input clock (fSUB) is stable.
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7.4.6 Example of watch error correction of real-time clock
The watch can be corrected with high accuracy when it is slow or fast, by setting a value to the watch error correction
register.
Example of calculating the correction value
The correction value used when correcting the count value of the sub-count register is calculated by using the
following expression.
Set the DEV bit to 0 when the correction range is -4165.6 ppm or less, or 4165.6 ppm or more.
(When DEV = 0)
Correction valueNote = Number of correction counts in 1 minute 3 = (Oscillation frequency Target frequency 1)
32768 60 3
(When DEV = 1)
Correction valueNote = Number of correction counts in 1 minute = (Oscillation frequency Target frequency 1)
32768 60
Note The correction value is the watch error correction value calculated by using bits 12 to 0 of the watch error
correction register (SUBCUDW).
(When F12 = 0) Correction value = {(F11, F10, F9, F8, F7, F6, F5, F4, F3, F2, F1, F0) 1} 2
(When F12 = 1) Correction value = {(/F11, /F10, /F9, /F8, /F7, /F6, /F5, /F4, /F3, /F2, /F1, /F0) + 1} 2
When (F12 to F0) is (*, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, *), watch error correction is not performed. “*” is 0 or 1.
/F11 to /F0 are bit-inverted values (000000000011 when 111111111100).
Remarks 1.
2.
The correction value is 2, 4, 6, 8, … 8186, 8188 or -2, -4, -6, -8, … -8186, -8188.
The oscillation frequency is the input clock (fRTC).
It can be calculated from the output frequency of the RTC1HZ pin 32768 when the watch error
correction register is set to its initial value (00H).
3.
The target frequency is the frequency resulting after correction performed by using the watch error
correction register.
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Correction example
Example of correcting from 32767.4 Hz to 32768 Hz (32767.4 Hz + 18.3 ppm)
[Measuring the oscillation frequency]
The oscillation frequencyNote of each product is measured by outputting about 1 Hz from the RTC1HZ pin when the
watch error correction register (SUBCUDW) is set to its initial value (0000H).
Note See 7.4.5 1 Hz output of real-time clock for the setting procedure of outputting about 1 Hz from the RTC1HZ
pin.
[Calculating the correction value]
(When the output frequency from the RTC1Hz pin is 0.9999817 Hz)
Oscillation frequency = 32768 0.9999817 32767.4 Hz
Assume the target frequency to be 32768 Hz (32767.4 Hz + 18.3 ppm) and DEV to be 1.
The expression for calculating the correction value when DEV is 1 is applied.
Correction value = Number of correction counts in 1 minute
= (Oscillation frequency Target frequency 1) 32768 60
= (32767.4 32768 1) 32768 60
= 36
[Calculating the values to be set to (F12 to F0)]
(When the correction value is 36)
If the correction value is 0 or less (when quickening), assume F12 to be 1.
Calculate (F11 to F0) from the correction value.
{(/F11 to /F0) 1} 2
= 36
(/F11 to /F0)
= 17
(/F11 to /F0)
= (0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1)
(F11 to F0)
= (1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0)
Consequently, when correcting from 32767.4 Hz to 32768 Hz (32767.4 Hz + 18.3 ppm), setting the correction
register such that DEV is 1 and the correction value is 36 (bits 12 to 0 of the SUBCUDW register: 1, 1, 1, 1, 1, 1,
1,1,0,1,1,1,0) results in 32768 Hz (0 ppm).
Figure 7-26 shows the operation when (DEV, F12, F11, F10, F9, F8, F7, F6, F5, F4, F3, F2, F1, F0) is (1, 1, 1, 1, 1,
1, 1, 1, 1, 0, 1, 1, 1, 0).
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Subcount
register (16-bit)
count value
0000H
Count start
00
01
7FDAH 7FDBH 0000H 0001H
7FFFH-24H (36)
7FFFH
19
0000H 0001H
20
7FFFH 0000H 0001H
7FFFH
39
0000H 0001H
40
7FFFH 0000H 0001H
7FFFH
59
0000H 0001H
7FFFH 0000H
Figure 7-26. Operation when (DEV, F12, F11, F10, F9, F8, F7, F6, F5, F4, F3, F2, F1, F0) = (1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0)
00
7FDAH 7FDBH
7FFFH-24H (36)
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CHAPTER 8 INTERVAL TIMER
CHAPTER 8 INTERVAL TIMER
8.1 Functions of Interval Timer
An interrupt (INTIT) is generated at any previously specified time interval. It can be utilized for wakeup from STOP
Mode.
8.2 Configuration of Interval Timer
The interval timer includes the following hardware.
Table 8-1. Configuration of Interval Timer
Item
Configuration
Counter
15-bit counter
Control registers
Peripheral enable register 0 (PER0)
RTC clock selection register (RTCCL)
Interval timer control register (ITMC)
Figure 8-1. Block Diagram of Interval Timer
Clear
Count clock
15-bit counter
Selector
fSUB
fIL
fMX/122
fMX/128
fMX/244
fMX/256
fIH/122
fIH/128
fIH/244
fIH/256
Interrupt signal (INTIT)
Match singnel
RINTE
RTCCL7, 6, RTCCK1, 0
ITMCMP14-ITMCMP0
Interval timer control
register (ITMC)
Internal bus
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8.3 Registers Controlling Interval Timer
The interval timer is controlled by the following registers.
• Peripheral enable register 0 (PER0)
• RTC clock selection register (RTCCL)
• Interval timer control register (ITMC)
(1) Peripheral enable register 0 (PER0)
This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a
hardware macro that is not used is stopped in order to reduce the power consumption and noise.
When the interval timer is used, be sure to set bit 7 (RTCEN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 8-2. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H
After reset: 00H
R/W
Symbol
PER0
RTCEN
LIN1EN
LIN0EN
SAU1EN
SAU0EN
TAU2EN
TAU1EN
TAU0EN
RTCEN
Control of real-time clock (RTC) and interval timer input clock supply
Note 1
Stops input clock supply.
0
SFR used by the real-time clock (RTC) and interval timer cannot be written.
The real-time clock (RTC) and interval timer are in the reset status.
Enables input clock supply.
1
SFR used by the real-time clock (RTC) and interval timer can be read and written.
Note 1. The input clock that can be controlled by the RTCEN bit is used when the register that is
used by the real-time clock (RTC) and interval timer are accessed from the CPU.
The
RTCEN bit cannot control supply of the operating clock (fSUB) to RTC and interval timer.
Cautions 1. When using the interval timer, first set the RTCEN bit to 1, while oscillation of the
input clock (fRTC) is stable. If RTCEN = 0, writing to a control register of the real-time
clock or interval timer is ignored, and, even if the register is read, only the default
value is read.
2. Clock supply to peripheral functions other than the real-time clock and interval timer
can be stopped in STOP mode or HALT mode when the subsystem clock is used, by
setting the RTCLPC bit of the operation speed mode control register (OSMC) to 1. In
this case, set the RTCEN bit of the PER0 register to 1 and the other bits (bits 0 to 6)
to 0.
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(2) RTC clock selection register (RTCCL)
Figure 8-3. Format of RTC Clock Selection Register (RTCCL)
Address: F00F9H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
RTCCL
RTCCL7
RTCCL6
0
0
0
0
RTCCKS1
RTCCKS0
RTCCL7
Operation clock source selection for RTC/interval timer
0
RTC/interval timer uses External Main clock (fMX)
1
RTC/interval timer uses High-speed on-chip oscillator clock (fIH)
RTCCKS1
RTCCKS0
RTCCL6
0
0
0/1
0
1
Operation selection of RTC macro and interval timer
Sub clock (fSUB)
Low-speed on-chip oscillator clock (fIL, 15K@typ)
(WUTMMCK0 should be “1” to use this selection)
1
0
0
External Main or High-speed on-chip oscillator clock
(after selected by RTCCL7)/2
1
1
0
External Main or High-speed on-chip oscillator clock
(after selected by RTCCL7)/2
1
0
1
1
1
7
8
External Main or High-speed on-chip oscillator clock
(after selected by RTCCL7)/122
1
External Main or High-speed on-chip oscillator clock
(after selected by RTCCL7)/244
Caution WUTMMCK0 should be set to “1” when fIL is used for RTC/interval timer clock.
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CHAPTER 8 INTERVAL TIMER
(3) Interval timer control register (ITMC)
This register is used to set up the starting and stopping of the interval timer operation and to specify the timer
compare value.
The ITMC register can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 7FFFH.
Figure 8-4. Format of Interval Timer Control Register (ITMC)
Address: FFF50H
After reset: 7FFFH
R/W
Symbol
15
14 to 0
ITMC
RINTE
ITMCMP14 to ITMCMP0
RINTE
Interval timer operation control
0
Count operation stopped (count clear)
1
Count operation started
ITMCMP14 to ITMCMP0
0001H
•
Specification of the interval timer compare value
These bits generate an interrupt at the fixed cycle (count clock cycles x (ITMCMP
setting + 1)).
•
•
7FFFH
Example interrupt cycles when 0001H or 7FFFH is specified for ITMCMP14 to ITMCMP0
• ITMCMP14 to ITMCMP0 = 0001H, count clock: when fSUB = 32.768 kHz
1/32.768 [kHz] (1 + 1) = 0.06103515625 [ms] 61.03 [s]
• ITMCMP14 to ITMCMP0 = 7FFFH, count clock: when fSUB = 32.768 kHz
1/32.768 [kHz] (32767 + 1) = 1000 [ms]
Cautions 1. Before changing the RINTE bit from 1 to 0, use the interrupt mask flag register to disable the
INTIT interrupt servicing. When the operation starts (from 0 to 1) again, clear the ITIF flag,
and then enable the interrupt servicing.
2. The value read from the RINTE bit is applied one count clock cycle after setting the RINTE bit.
3. When setting the RINTE bit after returned from standby mode and entering standby mode
again, confirm that the written value of the RINTE bit is reflected, or wait that more than one
clock of the count clock has elapsed after returned from standby mode. Then enter standby
mode.
4. Only change the setting of the ITMCMP14 to ITMCMP0 bits when RINTE = 0.
However, it is possible to change the settings of the ITMCMP14 to ITMCMP0 bits at the same
time as when changing RINTE from 0 to 1 or 1 to 0.
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8.4 Interval Timer Operation
」
The count value specified for the ITMCMP14 to ITMCMP0 bits is used as an interval to operate an interval timer that
repeatedly generates interrupt requests (INTIT).
When the RINTE bit is set to 1, the 15-bit counter starts counting.
When the 15-bit counter value matches the value specified for the ITMCMP14 to ITMCMP0 bits, the 15-bit counter
value is cleared to 0, counting continues, and an interrupt request signal (INTIT) is generated at the same time.
The basic operation of the interval timer is as follows.
Figure 8-5. Interval Timer Operation Timing (ITMCMP14 to ITMCMP0 = 0FFH, count clock: fSUB = 32.768 kHz)
Count clock
RINTE
After RINTE is changed from 0 to 1, counting
starts at the next rise of the count clock signal.
0FFH
15-bit counter
000H
When RINTE is changed from 1 to 0,
the 15-bit counter is cleared without
synchronization with the count clock.
ITMCMP14 ITMCMP0
0FFH
INTIT
Period (7.81 ms)
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CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
9.1 Functions of Clock Output/Buzzer Output Controller
The clock output controller is intended for carrier output during remote controlled transmission and clock output for
supply to peripheral ICs.
Buzzer output is a function to output a square wave of buzzer frequency.
One pin can be used to output a clock or buzzer sound.
The PCL pin outputs a clock selected by clock output select register 0 (CKS0).
Figure 9-1 shows the block diagram of clock output/buzzer output controller.
Caution In the low-consumption RTC mode (when the RTCLPC bit of the operation speed mode control
register (OSMC) = 1), it is not possible to output the subsystem clock (fSUB) from the PCL pin.
Figure 9-1. Block Diagram of Clock Output/Buzzer Output Controller
fMP
Prescaler
5
3
fSUB to fSUB/27
Clock/buzzer
controller
Selector
fMP to fMP/24
Selector
fMP/211 to fMP/213
PCL/P75 (default)
PCL/P66 (option)
8
fSUB
PCLOE0
PCLOE0
Prescaler
0
0
PCLSEL
0
CSEL0 CCS02
CCS01 CCS00
Clock output select register 0 (CKS0)
Internal bus
Note
For output frequencies available from PCL, refer to 33.5 AC characteristics and 34.5 AC characteristics.
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9.2 Configuration of Clock Output/Buzzer Output Controller
The clock output/buzzer output controller includes the following hardware.
Table 9-1. Configuration of Clock Output/Buzzer Output Controller
Item
Control registers
Configuration
Clock output select register 0 (CKS0)
Port mode register 7 (PM7)/6 (PM6)
Port register 7 (P7)/6 (P6)
9.3 Registers Controlling Clock Output/Buzzer Output Controller
The following two registers are used to control the clock output/buzzer output controller.
Clock output select registers 0 (CKS0)
Port mode register 7 (PM7)/6 (PM6)
(1) Clock output select registers 0 (CKS0)
This register sets output enable/disable for clock output or for the buzzer frequency output pin (PCL), and set the
output clock.
Select the clock to be output from the PCL pin by using the CKS0 register.
The CKS0 register is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
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Figure 9-2. Format of Clock Output Select Register 0 (CKS0)
Address: FFFA5H
Symbol
CKS0
After reset: 00H
R/W
6
5
4
3
2
1
0
PCLOE0
0
0
0
CSEL0
CCS02
CCS01
CCS00
PCLOE0
PCL pin output enable/disable specification
0
Output disable (default)
1
Output enable
CSEL0
CCS02
0
0
CCS01
0
CCS00
0
PCL pin output clock selection
fMAIN
fMAIN =
fMAIN =
fMAIN =
fMAIN =
5 MHz
10 MHz
20 MHz
32 MHz
5 MHz
10 MHz
Note
Setting
Setting
prohibited
fMAIN/2
0
0
1
0
fMAIN/2
2
1.25 MHz
2.5 MHz
5 MHz
8 MHz
0
0
1
1
fMAIN/2
3
625 kHz
1.25 MHz
2.5 MHz
4 MHz
0
1
0
0
fMAIN/2
4
312.5 kHz
625 kHz
1.25 MHz
2 MHz
fMAIN/2
11
2.44 kHz
4.88 kHz
9.76 kHz
15.63 kHz
fMAIN/2
12
1.22 kHz
2.44 kHz
4.88 kHz
7.81 kHz
13
610 Hz
1.22 kHz
2.44 kHz
3.91 kHz
1
1
1
0
0
1
1
1
fMAIN/2
1
0
0
0
fSUB
1
0
0
1
fSUB/2
32.768 kHz
16.384 kHz
1
0
1
0
fSUB/2
2
1
0
1
1
fSUB/2
3
4.096 kHz
fSUB/2
4
2.048 kHz
fSUB/2
5
1.024 kHz
fSUB/2
6
512 Hz
fSUB/2
7
256 Hz
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
16 MHz
Note
1
0
Note
Note
0
0
10 MHz
Note
0
1
5 MHz
prohibited
0
0
2.5 MHz
Note
8.192 kHz
Use the output clock within a range of 16 MHz. Furthermore, the available output frequency depends on the
grade. For details, refer to 33.5 AC Characteristics or 34.5 AC Characteristics.
Cautions 1. Change the output clock after disabling clock output (PCLOE0 = 0).
2. To shift to STOP mode when the main system clock is selected (CSEL0 = 0), set PCLOE0 = 0
before executing the STOP instruction. When the subsystem clock is selected (CSEL0 = 1),
PCLOE0 = 1 can be set because the clock can be output in STOP mode.
3. In the low-consumption RTC mode (when the RTCLPC bit of the operation speed mode control
register (OSMC) = 1), it is not possible to output the subsystem clock (fSUB) from the PCL pin.
Remark
fMAIN: Main system clock frequency
fSUB: Subsystem clock frequency
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(2) Port mode register 7 (PM7)
This register sets input/output of port 7 in 1-bit units. Port 7 alternate function about a PCL output is shown in
Table 9-2.
When using the P75/PCL pin for clock output and buzzer output, clear the PM75 bit and the output latches of P75
to 0.
The PM7 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Figure 9-3. Format of Port Mode Register 7 (PM7)
Address: FFF27H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM7
1
1
PM75
PM74
PM73
PM72
PM71
PM70
PM7n
PM7n pin I/O mode selection (n = 0 to 5)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
Table 9-2. Settings of Register, and Output Latch When Using Alternate Function
Alternate function
port
Function
name
P75
Expanded control setting (Register.bit)
PMxx
Pxx
LCDPFxx
I/O
Enable function
Disable other function
TI22
Input
1
x
0
TIS20.5,4 = 00
TO22
Output
0
0
0
TOS20.5,4 = 00
SGSEL.3 = 1
PCL
Output
0
0
0
SGSEL.3 = 0
TOS20.5,4 = 01/10
SI01
Input
1
x
0
STSEL0.4 = 0
-
SEG27
Output
x
x
1
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(3) Port mode register 6 (PM6)
This register sets input/output of port 6 in 1-bit units. Port 6 alternate function about a PCL output is shown in
Table 9-3.
When using the P66/PCL pin for clock output and buzzer output, clear the PM66 bit and the output latches of P66
to 0.
The PM6 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Figure 9-4. Format of Port Mode Register 6 (PM6)
Address: FFF26H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM6
1
PM66
PM65
PM64
PM63
PM62
PM61
PM60
PM6n
PM6n pin I/O mode selection (n = 0 to 6)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
Table 9-3. Settings of Register, and Output Latch When Using Alternate Function
Alternate function
port
Function name
P66
Expanded control setting (Register.bit)
PMxx
Pxx
LCDPFxx
I/O
Enable function
TI24
Input
1
x
TO24
Output
0
0
TOS21.1,0 = 00
SGSEL.3 = 0
PCL
Output
0
0
SGSEL.3 = 1
TOS21.1,0 = 01/10
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(4) Sound generator and PCL pin select register (SGSEL)
This register is used for alternate switch of sound generator and PCL output pins.
SGOA output can be stopped when it is not used if SGSEL2 is set to “1”.
Figure 9-5. Format of sound generator and PCL pin select register (SGSEL)
Address: FFF3FH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
SGSEL
0
0
0
0
PCLSEL
SGSEL2
SGSEL2
SGSEL1
SGSEL0
1
0
SGSEL1 SGSEL0
Pin select of sound generator outputs
SGO/SGOF
SGOA
0
0
0
P73
P72
0
0
1
P93
P92
0
1
0
P135
P134
0
1
1
Setting prohibit
1
0
0
P73
No port is selected
1
0
1
P93
(output disabled)
1
1
0
P135
1
1
1
Setting prohibit
Note The driving capability of SGO/SGOF alternate pin (P73, P93, P135) is larger than normal buffer.
P93 is also alternated as Stepper-Motor function, so its driving characteristics is the same as SM buffer.
P73 and P135 are the same as SG buffer of 78K0/Dx2.
PCLSEL
PCL output pin selection
0
P75 (default, be available for 48/64/80/100pin)
1
P66 (option for 80/100pin)
9.4 Operations of Clock Output/Buzzer Output Controller
One pin can be used to output a clock or buzzer sound.
The PCL pin outputs a clock/buzzer selected by the clock output select register 0 (CKS0).
9.4.1 Operation as output pin
The PCL pin is output as the following procedure.
Select the PCL output pin by the PCLSEL bit in the SGSEL register.
Select the output frequency with bits 0 to 3 (CCS00 to CCS02, CSEL0) of the clock output select register 0
(CKS0) of the PCL pin (output in disabled status).
Set bit 7 (PCLOE0) of the CKS0 register to 1 to enable clock/buzzer output.
Remarks
The controller used for outputting the clock starts or stops outputting the clock one clock after enabling or
disabling clock output (PCLOE0 bit) is switched. At this time, pulses with a narrow width are not output.
Figure 9-6 shows enabling or stopping output using the PCLOE0 bit and the timing of outputting the clock.
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Figure 9-6. Remote Control Output Application Example
PCLOE0
1 clock elapsed
Clock output
Narrow pulses are not recognized
9.5 Cautions of clock output/buzzer output controller
When the main system clock is selected for the PCL output, if STOP or HALT mode is entered within 1.5 main system
clock cycles after the output is disabled (PCLOE0 = 0), the PCL output width becomes shorter.
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CHAPTER 10 WATCHDOG TIMER
CHAPTER 10 WATCHDOG TIMER
10.1 Functions of Watchdog Timer
The watchdog timer operates on the low-speed on-chip oscillator clock.
The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset
signal is generated.
Program loop is detected in the following cases.
If the watchdog timer counter overflows
If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE)
If data other than “ACH” is written to the WDTE register
If data is written to the WDTE register during a window close period
When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For
details of the RESF register, see CHAPTER 23 RESET FUNCTION.
When 75% + 1/2 fIL of the overflow time is reached, an interval interrupt can be generated.
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10.2 Configuration of Watchdog Timer
The watchdog timer includes the following hardware.
Table 10-1. Configuration of Watchdog Timer
Item
Configuration
Control register
Watchdog timer enable register (WDTE)
How the counter operation is controlled, overflow time, window open period, and interval interrupt are set by the option
byte.
Table 10-2. Setting of Option Bytes and Watchdog Timer
Setting of Watchdog Timer
Option Byte (000C0H)
Watchdog timer interval interrupt
Bit 7 (WDTINT)
Window open period
Bits 6 and 5 (WINDOW1, WINDOW0)
Controlling counter operation of watchdog timer
Bit 4 (WDTON)
Overflow time of watchdog timer
Bits 3 to 1 (WDCS2 to WDCS0)
Controlling counter operation of watchdog timer
Bit 0 (WDSTBYON)
(in HALT/STOP mode)
Remark For the option byte, see CHAPTER 28 OPTION BYTE.
Figure 10-1. Block Diagram of Watchdog Timer
WDTINT of option
byte (000C0H)
Interval time controller
(Count value overflow time × 3/4)
Interval time interrupt
WDCS2 to WDCS0 of
option byte (000C0H)
fIL
Clock
input
controller
17-bit
counter
fIL/26 to fIL/216
Selector
Reset
output
controller
Count clear
signal
WINDOW1 and
WINDOW0 of option
byte (000C0H)
WDTON of option
byte (000C0H)
Overflow signal
Internal reset signal
Window size
decision signal
Window size check
Watchdog timer enable
register (WDTE)
Write detector to
WDTE except ACH
Internal bus
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10.3 Register Controlling Watchdog Timer
The watchdog timer is controlled by the watchdog timer enable register (WDTE).
(1) Watchdog timer enable register (WDTE)
Writing “ACH” to the WDTE register clears the watchdog timer counter and starts counting again.
This register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 9AH or 1AHNote.
Figure 10-2. Format of Watchdog Timer Enable Register (WDTE)
Address: FFABH
Symbol
After reset: 9AH/1AH Note R/W
7
6
5
4
3
2
1
0
WDTE
Note The WDTE register reset value differs depending on the WDTON bit setting value of the option byte
(000C0H). To operate watchdog timer, set the WDTON bit to 1.
WDTON Bit Setting Value
WDTE Register Reset Value
0 (watchdog timer count operation disabled)
1AH
1 (watchdog timer count operation enabled)
9AH
Cautions 1. If a value other than “ACH” is written to the WDTE register, an internal reset signal is
generated.
2. If a 1-bit memory manipulation instruction is executed for the WDTE register, an internal reset
signal is generated.
3. The value read from the WDTE register is 9AH/1AH (this differs from the written value (ACH)).
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10.4 Operation of Watchdog Timer
10.4.1 Controlling operation of watchdog timer
1.
When the watchdog timer is used, its operation is specified by the option byte (000C0H).
Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the
counter starts operating after a reset release) (for details, see CHAPTER 28).
WDTON
Watchdog Timer Counter
0
Counter operation disabled (counting stopped after reset)
1
Counter operation enabled (counting started after reset)
Set an overflow time by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H) (for details, see 10.4.2
and CHAPTER 28).
Set a window open period by using bits 6 and 5 (WINDOW1 and WINDOW0) of the option byte (000C0H) (for
details, see 10.4.3 and CHAPTER 28).
2.
After a reset release, the watchdog timer starts counting.
3.
By writing “ACH” to the watchdog timer enable register (WDTE) after the watchdog timer starts counting and before
4.
After that, write the WDTE register the second time or later after a reset release during the window open period. If
the overflow time set by the option byte, the watchdog timer is cleared and starts counting again.
the WDTE register is written during a window close period, an internal reset signal is generated.
5.
If the overflow time expires without “ACH” written to the WDTE register, an internal reset signal is generated.
An internal reset signal is generated in the following cases.
If a 1-bit manipulation instruction is executed on the WDTE register
If data other than “ACH” is written to the WDTE register
Cautions 1. When data is written to the watchdog timer enable register (WDTE) for the first time after reset
release, the watchdog timer is cleared in any timing regardless of the window open time, as long
as the register is written before the overflow time, and the watchdog timer starts counting again.
2. If the watchdog timer is cleared by writing “ACH” to the WDTE register, the actual overflow time
may be different from the overflow time set by the option byte by up to 2/fIL seconds.
3. The watchdog timer can be cleared immediately before the count value overflows.
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Cautions 4. The operation of the watchdog timer in the HALT and STOP and SNOOZE modes differs as
follows depending on the set value of bit 0 (WDSTBYON) of the option byte (000C0H).
WDSTBYON = 0
In HALT mode
WDSTBYON = 1
Watchdog timer operation stops.
Watchdog timer operation continues.
In STOP mode
In SNOOZE mode
If WDSTBYON = 0, the watchdog timer resumes counting after the HALT or STOP mode is
released. At this time, the counter is cleared to 0 and counting starts.
When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer overflow is short,
an overflow occurs during the oscillation stabilization time, causing a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization time when
operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the
STOP mode release by an interval interrupt.
5. The watchdog timer continues its operation during self-programming of the flash memory and
EEPROMTM emulation. During processing, the interrupt acknowledge time is delayed. Set the
overflow time and window size taking this delay into consideration.
10.4.2 Setting overflow time of watchdog timer
Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H).
If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer starts
counting again by writing “ACH” to the watchdog timer enable register (WDTE) during the window open period before the
overflow time.
The following overflow times can be set.
Table 10-3. Setting of Overflow Time of Watchdog Timer
WDCS2
WDCS1
WDCS0
Overflow Time of Watchdog Timer
(fIL = 17.25 kHz (MAX.))
6
0
0
0
2 /fIL (3.71 ms)
0
0
1
2 /fIL (7.42 ms)
0
1
0
2 /fIL (14.84 ms)
0
1
1
2 /fIL (29.68 ms)
1
0
0
2 /fIL (118.72 ms)
1
0
1
2 /fIL (474.90 ms)
1
1
0
2 /fIL (949.80 ms)
1
1
1
2 /fIL (3799.19 ms)
7
8
9
11
13
14
16
Caution The watchdog timer continues its operation during self-programming of the flash memory and
EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the overflow
time and window size taking this delay into consideration.
Remark
fIL: Low-speed on-chip oscillator clock frequency
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10.4.3 Setting window open period of watchdog timer
Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte
(000C0H). The outline of the window is as follows.
If “ACH” is written to the watchdog timer enable register (WDTE) during the window open period, the watchdog timer
is cleared and starts counting again.
Even if “ACH” is written to the WDTE register during the window close period, an abnormality is detected and an
internal reset signal is generated.
Example: If the window open period is 50%
Counting
starts
Overflow
time
Window close period (50%)
Window close period (50%)
Internal reset signal is generated
if "ACH" is written to WDTE.
Counting starts again when
"ACH" is written to WDTE.
Caution When data is written to the WDTE register for the first time after reset release, the watchdog timer is
cleared in any timing regardless of the window open time, as long as the register is written before the
overflow time, and the watchdog timer starts counting again.
The window open period can be set is as follows.
Table 10-4. Setting Window Open Period of Watchdog Timer
WINDOW1
WINDOW0
Window Open Period of Watchdog Timer
0
0
Setting prohibited
0
1
50%
1
0
75%
1
1
100%
Cautions 1. The watchdog timer continues its operation during self-programming of the flash memory and
EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the
overflow time and window size taking this delay into consideration.
2. When bit 0 (WDSTBYON) of the option byte (000C0H) = 0, the window open period is 100%
regardless of the values of the WINDOW1 and WINDOW0 bits.
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Remark If the overflow time is set to 29/fIL, the window close time and open time are as follows.
Setting of Window Open Period
50%
75%
100%
Window close time
0 to 20.08 ms
0 to 10.04 ms
None
Window open time
20.08 to 29.68 ms
10.04 to 29.68 ms
0 to 29.68 ms
Overflow time:
29/fIL (MAX.) = 29/17.25 kHz (MAX.) = 29.68 ms
Window close time:
0 to 29/fIL (MIN.) (1 0.5) = 0 to 29/12.75 kHz 0.5 = 0 to 20.08 ms
Window open time:
29/fIL (MIN.) (1 0.5) to 29/fIL (MAX.) = 29/12.75 kHz (MIN.) 0.5 to 29/17.25 kHz (MAX.)
= 20.08 to 29.68 ms
10.4.4 Setting watchdog timer interval interrupt
Depending on the setting of bit 7 (WDTINT) of an option byte (000C0H), an interval interrupt (INTWDTI) can be
generated when 75% + 1/2 fIL of the overflow time is reached.
Table 10-5. Setting of Watchdog Timer Interval Interrupt
WDTINT
Use of Watchdog Timer Interval Interrupt
0
Interval interrupt is not used.
1
Interval interrupt is generated when 75% + 1/2 fIL of overflow time is reached.
Caution When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer overflow is short, an
overflow occurs during the oscillation stabilization time, causing a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization time when
operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the STOP
mode release by an interval interrupt.
Remark
The watchdog timer continues counting even after INTWDTI is generated (until ACH is written to the
watchdog timer enable register (WDTE)). If ACH is not written to the WDTE register before the overflow time,
an internal reset signal is generated.
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CHAPTER 11 A/D CONVERTER
CHAPTER 11 A/D CONVERTER
The number of analog input channels of the A/D converter differs, depending on the product.
Analog input
48-pin
64-pin
80-pin
100-pin
128-pin
3+2 ch
3+2 ch
6+2 ch
7+2 ch
9+2 ch
channels
Caution Most of the following descriptions in this chapter use the 128-pin products as an examples.
11.1 Function of A/D Converter
Note
The A/D converter is a 10-bit resolution
converter that converts analog input signals into digital values, and is
configured to control analog inputs, including up to nine channels of A/D converter analog inputs (ANI0 to ANI8).
The A/D converter has the following function.
10-bit resolution A/D conversionNote
10-bit resolution A/D conversion is carried out repeatedly for one analog input channel selected from ANI0 to ANI8.
Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated (when in the select mode).
Note 8-bit resolution can also be selected by using the ADTYP bit of A/D converter mode register 2 (ADM2).
Various A/D conversion modes can be specified by using the mode combinations below.
Trigger Mode
Software trigger
Channel Selection Mode
Select mode
Conversion Operation Mode
One-shot conversion mode
Conversion is started by specifying a
A/D conversion is performed on
A/D conversion is performed on
software trigger.
the analog input of one channel.
the selected channel once.
Hardware trigger no-wait mode
Scan mode
Sequential conversion mode
Conversion is started by detecting a
A/D conversion is performed on
A/D conversion is sequentially
hardware trigger.
the analog input of four channels
performed on the selected
in order.
channels until it is stopped by
Hardware trigger wait mode
The power is turned on by detecting a
software.
hardware trigger while the system is off and
in the conversion standby state, and
conversion is then started automatically
after the stabilization wait time passes.
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Figure 11-1. Block Diagram of A/D Converter
Internal bus
A/D port configuration
register (ADPC)
A/D test register
(ADTES)
ADPC.3 ADPC.2 ADPC.1 ADPC.0
Conversion result
comparison lower limit
setting register (ADLL)
Selector
ADREFP1 and ADREFP0 bits
3
4
Internal reference voltage (1.45 V)
VDD
AVREFP /ANI0/P20
ADCS bit
Sample & hold circuit
A/D voltage comparator
Selector
Selector
Comparison
voltage
generator
VSS
Selector
Successive
approximation register
(SAR)
4
ADS.2
ADS.1
ADREFP1 ADREFP0 ADREFM ADRCK
ADS.0
Analog input channel
specification register (ADS)
AVREFM /ANI1/P21
VSS
Timer trigger signal (INTTM02)
Timer trigger signal (INTTM04)
ADTRG/P72
Controller
AWC
A/D conversion
result upper
limit/lower limit
comparator
ADTYP
A/D converter mode
register 2 (ADM2)
ADS.3
ADREFM bit
Selector
Analog/digital switcher
ANI0/AV REFP /P20
ANI1/AV REFM /P21
ANI2/P22
ANI3/P23
ANI4/P24
ANI5/P25
ANI6/P26
ANI7/P27
ANI8/P150
Conversion result
comparison upper limit
setting register (ADUL)
ADTES.2 ADTES.1 ADTES.0
INTAD
6
ADTMD1 ADTMD0 ADSCM ADTRS0 ADTRS0
ADCS
A/D converter mode
register 1 (ADM1)
ADMD
FR2
FR1
FR0
LV1
LV0
ADCE
A/D converter mode
register 0 (ADM0)
A/D conversion result
register (ADCR)
Internal bus
Remark
The analog input pins in the figure are provided in the 128-pin products.
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11.2 Configuration of A/D Converter
The A/D converter includes the following hardware.
(1) ANI0 to ANI8 pins
These are the analog input pins of the up to 9 channels of the A/D converter. They input analog signals to be
converted into digital signals. Pins other than the one selected as the analog input pin can be used as I/O port pins.
(2) Sample & hold circuit
The sample & hold circuit samples each of the analog input voltages sequentially sent from the input circuit, and
sends them to the A/D voltage comparator. This circuit also holds the sampled analog input voltage during A/D
conversion.
(3) A/D voltage comparator
This A/D voltage comparator compares the voltage generated from the voltage tap of the comparison voltage
generator with the analog input voltage. If the analog input voltage is found to be greater than the reference voltage
(1/2 AVREF) as a result of the comparison, the most significant bit (MSB) of the successive approximation register
(SAR) is set. If the analog input voltage is less than the reference voltage (1/2 AVREF), the MSB bit of the SAR is
reset.
After that, bit 8 of the SAR register is automatically set, and the next comparison is made. The voltage tap of the
comparison voltage generator is selected by the value of bit 9, to which the result has been already set.
Bit 9 = 0: (1/4 AVREF)
Bit 9 = 1: (3/4 AVREF)
The voltage tap of the comparison voltage generator and the analog input voltage are compared and bit 8 of the SAR
register is manipulated according to the result of the comparison.
Analog input voltage Voltage tap of comparison voltage generator: Bit 8 = 1
Analog input voltage Voltage tap of comparison voltage generator: Bit 8 = 0
Comparison is continued like this to bit 0 of the SAR register.
When performing A/D conversion at a resolution of 8 bits, the comparison continues until bit 2 of the SAR register.
Remark AVREF: The + side reference voltage of the A/D converter. This can be selected from AVREFP, the internal
reference voltage (1.45 V), and VDD.
(4) Comparison voltage generator
The comparison voltage generator generates the comparison voltage input from an analog input pin.
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(5) Successive approximation register (SAR)
The SAR register is a 10-bit register that sets voltage tap data whose values from the comparison voltage generator
match the voltage values of the analog input pins, 1 bit at a time starting from the most significant bit (MSB).
If data is set in the SAR register all the way to the least significant bit (LSB) (end of A/D conversion), the contents of
the SAR register (conversion results) are held in the A/D conversion result register (ADCR). When all the specified
A/D conversion operations have ended, an A/D conversion end interrupt request signal (INTAD) is generated.
(6) 10-bit A/D conversion result register (ADCR)
The A/D conversion result is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCR register holds the A/D conversion result in its higher 10 bits (the lower 6 bits
are fixed to 0).
(7) 8-bit A/D conversion result register (ADCRH)
The A/D conversion result is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCRH register stores the higher 8 bits of the A/D conversion result.
(8) Controller
This circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as well
as starting and stopping of the conversion operation. When A/D conversion has been completed, this controller
generates INTAD.
(9) AVREFP pin
This pin inputs an external reference voltage (AVREFP).
If using AVREFP as the + side reference voltage of the A/D converter, set the ADREFP1 and ADREFP0 bits of A/D
converter mode register 2 (ADM2) to 0 and 1, respectively.
The analog signals input to ANI0 to ANI8 are converted to digital signals based on the voltage applied between
AVREFP and the side reference voltage (AVREFM/VSS).
In addition to AVREFP, it is possible to select VDD or the internal reference voltage (1.45 V) as the + side reference
voltage of the A/D converter.
(10) AVREFM pin
This pin inputs an external reference voltage (AVREFM). If using AVREFM as the side reference voltage of the A/D
converter, set the ADREFM bit of the ADM2 register to 1.
In addition to AVREFM, it is possible to select VSS as the side reference voltage of the A/D converter.
Caution The A/D conversion accuracy differs depending on the used pins or reference voltage setting. For
details, see CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT) and CHAPTER 34
ELECTRICAL SPECIFICATIONS (L GRADE PRODUCT).
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11.3 Registers Used in A/D Converter
The A/D converter uses the following registers.
Peripheral enable register 1 (PER1)
A/D converter mode register 0 (ADM0)
A/D converter mode register 1 (ADM1)
A/D converter mode register 2 (ADM2)
10-bit A/D conversion result register (ADCR)
8-bit A/D conversion result register (ADCRH)
Analog input channel specification register (ADS)
Conversion result comparison upper limit setting register (ADUL)
Conversion result comparison lower limit setting register (ADLL)
A/D test register (ADTES)
A/D port configuration register (ADPC)
Port mode registers 0 to 9, and 13 to 15 (PM0 to PM9, PM13 to PM15)
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(1) Peripheral enable register 1 (PER1)
This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware
macro that is not used is stopped in order to reduce the power consumption and noise.
When the A/D converter is used, be sure to set bit 7 (ADCEN) of this register to 1.
The PER1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 11-2. Format of Peripheral Enable Register 1 (PER1)
Address: F00F1H
After reset: 00H
R/W
Symbol
PER1
ADCEN
0
MTRCEN
SGEN
0
0
0
0
ADCEN
0
Control of A/D converter input clock supply
Stops input clock supply.
SFR used by the A/D converter cannot be written.
The A/D converter is in the reset status.
1
Enables input clock supply.
SFR used by the A/D converter can be read/written.
Cautions
When setting the A/D converter, be sure to set the ADCEN bit to 1 first. If ADCEN = 0, writing
to a control register of the A/D converter is ignored, and, even if the register is read, only the
default value is read (except for port mode registers 2 and 15 (PM2, PM15) and A/D port
configuration register (ADPC)).
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(2) A/D converter mode register 0 (ADM0)
This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion.
The ADM0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 11-3. Format of A/D Converter Mode Register 0 (ADM0)
Address: FFF30H
Symbol
After reset: 00H
ADM0
R/W
6
ADCS
5
ADMD
FR2
4
Note 1
FR1
ADTMD1
0
Note 1
3
FR0
Note 1
2
DV1
1
Note 1
DV0
Note 1
ADCE
A/D conversion operation control
Stops conversion operation
[When read]
Conversion stopped/standby status
1
Enables conversion operation
[When read
Note 2
]
While in the software trigger mode: Conversion operation status
While in the hardware trigger wait mode: Stabilization wait status + conversion operation status
ADMD
Specification of the A/D conversion channel selection mode
0
Select mode
1
Scan mode
ADCE
Notes 1.
A/D voltage comparator operation control
0
Stops A/D voltage comparator operation
1
Enables A/D voltage comparator operation
Note 3
For details of the FR2 to FR0, LV1, LV0 bits, and A/D conversion, see Table 11-3 A/D Conversion Time
Selection.
2.
While in the software trigger mode or hardware trigger no-wait mode, the operation of the A/D voltage
comparator is controlled by the ADCS and ADCE bits, and it takes 1 s from the start of operation for the
operation to stabilize. Therefore, when the ADCS bit is set to 1 after 1 s or more has elapsed from the
time ADCE bit is set to 1, the conversion result at that time has priority over the first conversion result.
Otherwise, ignore data of the first conversion.
Cautions 1. Change the bits ADMD, FR2 to FR0, LV1 and LV0, and ADCE in the conversion stop state or
conversion wait state (ADCS = 0).
2. It is prohibited to change the ADCE and ADCS bits from 0 to 1 by an 8-bit manipulation
instruction. To change these bits, use the procedure described in 11.7, A/D Converter Setup
Flowchart.
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Table 11-1. Settings of ADCS and ADCE Bits
ADCS
ADCE
A/D Conversion Operation
0
0
Stop status (DC power consumption path does not exist)
0
1
Conversion standby mode (only A/D voltage comparator consumes power
1
0
Setting prohibited
1
1
Conversion mode (A/D voltage comparator: enables operation)
Note
)
Note In hardware trigger wait mode, the DC power consumption path is not provided even in conversion wait mode.
Table 11-2. Setting and Clearing Conditions for ADCS Bit
A/D Conversion Mode
Software
Select mode
trigger
Set Conditions
Sequential conversion
When 1 is
mode
written to ADCS
Clear Conditions
When 0 is written to ADCS
One-shot conversion
When 0 is written to ADCS
mode
The bit is automatically cleared to 0 when
Sequential conversion
When 0 is written to ADCS
A/D conversion ends.
Scan mode
mode
One-shot conversion
When 0 is written to ADCS
mode
The bit is automatically cleared to 0 when
conversion ends on the specified four
channels.
Sequential conversion
When a
trigger no-wait
mode
hardware trigger
mode
One-shot conversion
is input
Hardware
Select mode
When 0 is written to ADCS
When 0 is written to ADCS
mode
Scan mode
Sequential conversion
When 0 is written to ADCS
mode
One-shot conversion
When 0 is written to ADCS
mode
Hardware
Select mode
Sequential conversion
When 0 is written to ADCS
trigger wait
mode
mode
One-shot conversion
When 0 is written to ADCS
mode
The bit is automatically cleared to 0 when
A/D conversion ends.
Scan mode
Sequential conversion
When 0 is written to ADCS
mode
One-shot conversion
When 0 is written to ADCS
mode
The bit is automatically cleared to 0 when
conversion ends on the specified four
channels.
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Figure 11-4. Timing Chart When A/D Voltage Comparator Is Used
A/D voltage comparator: enables operation
ADCE
Conversion start Note2
A/D voltage comparator
Conversion
operation
Conversion
standby
Software
trigger mode
ADCS
Conversion
stopped
Conversion
standby
Note1
1 is written
to ADCS.
0 is written
to ADCS.
Conversion start Note2
Conversion
standby
Hardware trigger
no-wait mode
ADCS
Trigger
standby
Conversion
operation
Conversion
stopped
Conversion
standby
Note1
Hardware
trigger detection
1 is written
to ADCS.
0 is written
to ADCS.
Conversion start Note2
A/D power supply stabilization wait time
Conversion
operation
Conversion
standby
Hardware trigger
wait mode
ADCS
0 is written
to ADCS.
Hardware trigger
detection
Notes 1.
Conversion
stopped
Conversion
standby
While in the software trigger mode or hardware trigger no-wait mode, the time from the rising of the ADCE
bit to the falling of the ADCS bit must be 1 s or longer to stabilize the internal circuit.
2.
In starting conversion, the longer will take up to following time.
ADM0
FR2
FR1
Conversion
FR0
clock (fAD)
Conversion Operation Time (fCLK clock)
Software trigger mode / Hardware
Hardware trigger wait
trigger no-wait mode
mode
1
0
0
0
fCLK/64
63
0
0
1
fCLK/32
31
0
1
0
fCLK/16
15
0
1
1
fCLK/8
7
1
0
0
fCLK/6
5
1
0
1
fCLK/5
4
1
1
0
fCLK/4
3
1
1
1
fCLK/2
1
In the conversion after the second conversion in continuous conversion mode or after the scan 1 in scan mode, the
conversion startup time or A/D power supply stabilization wait time is not generated after detection of a hardware trigger.
Cautions 1. If using the hardware trigger wait mode, setting the ADCS bit to 1 is prohibited (but the bit is
automatically switched to 1 when the hardware trigger signal is detected). However, it is possible
to clear the ADCS bit to 0 to specify the A/D conversion standby status.
2. While in the one-shot conversion mode of the hardware trigger no-wait mode, the ADCS flag is
not automatically cleared to 0 when A/D conversion ends. Instead, 1 is retained.
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Cautions 3. Only rewrite the value of the ADCE bit when ADCS = 0 (while in the conversion
stopped/conversion standby status).
4. To complete A/D conversion, the following hardware trigger interval time is required:
In hardware trigger no-wait mode: Two fCLK clock cycles + A/D conversion time
In hardware trigger wait mode: Two fCLK clock cycles + stabilization wait time + A/D conversion
time
Remark
fCLK: CPU/peripheral hardware clock frequency
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Table 11-3. A/D Conversion Time Selection (1/6)
(1) 4.0 V VDD 5.5 V
When there is no stabilization wait time (software trigger mode/hardware trigger no-wait mode)
A/D Converter Mode Register 0
Mode
Conversion
Conversion Time Selection
Clock (fAD)
(ADM0)
FR2
FR1
FR0
LV1
LV0
fCLK = 1 MHz fCLK = 2 MHz fCLK = 4 MHz
0
0
0
0
0
0
0
1
fCLK/32
0
1
0
fCLK/16
0
1
1
fCLK/8
1
0
0
1
0
1
1
Normal 1
fCLK/64
fCLK = 8 MHz fCLK = 16 MHz fCLK = 32 MHz
Setting
Setting
Setting
Setting
Setting
prohibited
prohibited
prohibited
prohibited
prohibited
38 s
38 s
19 s
38 s
19 s
9.5 s
38 s
19 s
9.5 s
4.75 s
fCLK/6
28.5 s
14.25 s
7.125 s
3.5625 s
1
fCLK/5
23.75 s
11.875 s
5.938 s
2.9688 s
1
0
fCLK/4
38 s
19 s
9.5 s
4.75 s
2.375 s
1
1
fCLK/2
19 s
9.5 s
4.75 s
2.375 s
Setting
38 s
prohibited
0
0
0
0
1
Normal 2
fCLK/64
0
0
1
fCLK/32
0
1
0
fCLK/16
0
1
1
fCLK/8
1
0
0
1
0
1
1
Setting
Setting
Setting
Setting
Setting
prohibited
prohibited
prohibited
prohibited
prohibited
34 s
34 s
17 s
34 s
17 s
8.5 s
34 s
17 s
8.5 s
4.25 s
fCLK/6
25.5 s
12.75 s
6.375 s
3.1875 s
1
fCLK/5
21.25 s
10.625 s
5.3125 s
2.6563 s
1
0
fCLK/4
34 s
17 s
8.5 s
4.25 s
2.125 s
1
1
fCLK/2
17 s
8.5 s
4.25 s
2.125 s
Setting
34 s
prohibited
Other than the above
Setting prohibited
Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, stop A/D conversion
once (ADCS = 0) beforehand.
2. The above conversion time does not include the conversion startup time. Add the conversion
startup time for the first conversion. Also, the above conversion time does not include clock
frequency errors. Select conversion time, taking clock frequency errors into consideration.
Remark
fCLK: CPU/peripheral hardware clock frequency
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Table 11-3. A/D Conversion Time Selection (2/6)
(2) 2.7 V VDD < 5.5 V
When there is no stabilization wait time (software trigger mode/hardware trigger no-wait mode)
A/D Converter Mode Register 0
Mode
Conversion
Conversion Time Selection
Clock (fAD)
(ADM0)
FR2
FR1
FR0
LV1
LV0
fCLK = 1 MHz fCLK = 2 MHz fCLK = 4 MHz
0
0
0
0
0
0
0
1
fCLK/32
0
1
0
fCLK/16
0
1
1
fCLK/8
1
0
0
1
0
1
1
Normal 1
fCLK/64
fCLK = 8 MHz fCLK = 16 MHz fCLK = 32 MHz
Setting
Setting
Setting
Setting
Setting
prohibited
prohibited
prohibited
prohibited
prohibited
38 s
38 s
19 s
38 s
19 s
9.5 s
38 s
19 s
9.5 s
4.75 s
fCLK/6
28.5 s
14.25 s
7.125 s
3.5625 s
1
fCLK/5
23.75 s
11.875 s
5.9375 s
Setting
1
0
fCLK/4
38 s
19 s
9.5 s
4.75 s
prohibited
1
1
fCLK/2
19 s
9.5 s
4.75 s
Setting
38 s
prohibited
0
0
0
0
1
Normal 2
fCLK/64
Setting
prohibited
Setting
prohibited
Setting
prohibited
Setting
Setting
prohibited
prohibited
34 s
34 s
17 s
34 s
17 s
8.5 s
17 s
8.5 s
4.25 s
0
0
1
fCLK/32
0
1
0
fCLK/16
0
1
1
fCLK/8
34 s
1
0
0
fCLK/6
25.5 s
12.75 s
6.375 s
3.1875 s
1
0
1
fCLK/5
21.25 s
10.625 s
5.3125 s
2.6563 s
1
1
0
fCLK/4
34 s
17 s
8.5 s
4.25 s
Setting
1
1
1
fCLK/2
17 s
8.5 s
4.25 s
Setting
prohibited
34 s
prohibited
Other than the above
Setting prohibited
Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, stop A/D conversion
once (ADCS = 0) beforehand.
2. The above conversion time does not include the conversion startup time. Add the conversion
startup time for the first conversion. Also, the above conversion time does not include clock
frequency errors. Select conversion time, taking clock frequency errors into consideration.
Remark
fCLK: CPU/peripheral hardware clock frequency
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Table 11-3. A/D Conversion Time Selection (3/6)
(3) 1.8 V VDD < 5.5 V
When there is no stabilization wait time (software trigger mode/hardware trigger no-wait mode)
A/D Converter Mode Register 0
Mode
Conversion
Conversion Time Selection
Clock (fAD)
(ADM0)
FR2
FR1
FR0
LV1
LV0
0
0
0
0
0
fCLK = 1 MHz fCLK = 2 MHz fCLK = 4 MHz
Normal 1
fCLK/64
Setting
prohibited
fCLK = 8 MHz fCLK = 16 MHz fCLK = 32 MHz
Setting
Setting
Setting
Setting
prohibited
prohibited
prohibited
prohibited
38 s
38 s
19 s
38 s
19 s
Setting
38 s
19 s
Setting
prohibited
fCLK/6
28.5 s
Setting
prohibited
1
fCLK/5
23.75 s
prohibited
1
0
fCLK/4
1
1
fCLK/2
0
0
1
fCLK/32
0
1
0
fCLK/16
0
1
1
fCLK/8
1
0
0
1
0
1
1
38 s
38 s
19 s
19 s
Setting
prohibited
0
0
0
0
1
Normal 2
fCLK/64
Setting
Setting
Setting
Setting
Setting
prohibited
prohibited
prohibited
prohibited
prohibited
34 s
34 s
17 s
34 s
17 s
Setting
34 s
17 s
Setting
prohibited
fCLK/6
25.5 s
Setting
prohibited
1
fCLK/5
21.25 s
prohibited
1
0
fCLK/4
1
1
fCLK/2
0
0
1
fCLK/32
0
1
0
fCLK/16
0
1
1
fCLK/8
1
0
0
1
0
1
1
34 s
34 s
17 s
17 s
Setting
prohibited
Other than the above
Setting prohibited
Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, stop A/D conversion
once (ADCS = 0) beforehand.
2. The above conversion time does not include the conversion startup time. Add the conversion
startup time for the first conversion. Also, the above conversion time does not include clock
frequency errors. Select conversion time, taking clock frequency errors into consideration.
Remark
fCLK: CPU/peripheral hardware clock frequency
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Table 11-3. A/D Conversion Time Selection (4/6)
(4) 4.0 V VDD 5.5 V
When there is stabilization wait time (hardware trigger wait mode)
A/D Converter Mode Register 0
Mode
Conversion
Conversion Time Selection
Clock (fAD)
(ADM0)
FR2
FR1
FR0
LV1
LV0
0
0
0
0
0
Normal 1
fCLK/64
0
0
1
fCLK/32
0
1
0
fCLK/16
0
1
1
fCLK/8
1
0
0
fCLK/6
1
0
1
fCLK/5
1
1
0
fCLK/4
1
1
1
fCLK/2
fCLK = 1 MHz fCLK = 2 MHz fCLK = 4 MHz
fCLK = 8 MHz fCLK = 16 MHz fCLK = 32 MHz
Setting
Setting
Setting
Setting
Setting
Setting
prohibited
prohibited
prohibited
prohibited
prohibited
prohibited
27 s
27 s
27 s
13.5 s
27 s
13.5 s
6.75 s
20.25 s
10.125 s
5.0625 s
33.75 s
16.875 s
8.4375 s
4.2188 s
27 s
13.5 s
6.75 s
3.375 s
13.5 s
6.75 s
3.375 s
Setting
prohibited
0
0
0
0
1
Normal 2
fCLK/64
0
0
1
fCLK/32
0
1
0
fCLK/16
0
1
1
fCLK/8
1
0
0
fCLK/6
1
0
1
1
1
1
1
Setting
Setting
Setting
Setting
Setting
Setting
prohibited
prohibited
prohibited
prohibited
prohibited
prohibited
25 s
25 s
12.5 s
25 s
12.5 s
6.25 s
37.5 s
18.75 s
9.375 s
4.6875 s
fCLK/5
31.25 s
15.625 s
7.8125 s
3.9063 s
0
fCLK/4
25 s
12.5 s
6.25 s
3.125 s
1
fCLK/2
12.5 s
6.25 s
3.125 s
Setting
25 s
prohibited
Other than the above
Setting prohibited
Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, stop A/D conversion
once (ADCS = 0) beforehand.
2. The above conversion time does not include the conversion startup time. Add the conversion
startup time for the first conversion. Also, the above conversion time does not include clock
frequency errors. Select conversion time, taking clock frequency errors into consideration.
3. While in the hardware trigger wait mode, the conversion time includes the time spent waiting for
stabilization after the hardware trigger is detected.
Remark
fCLK: CPU/peripheral hardware clock frequency
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Table 11-3. A/D Conversion Time Selection (5/6)
(5) 2.7 V VDD < 5.5 V
When there is stabilization wait time (hardware trigger wait mode)
A/D Converter Mode Register 0
Mode
Conversion
Conversion Time Selection
Clock (fAD)
(ADM0)
FR2
FR1
FR0
LV1
LV0
0
0
0
0
0
Normal 1
fCLK/64
0
0
1
fCLK/32
0
1
0
fCLK/16
0
1
1
fCLK/8
1
0
0
fCLK/6
1
0
1
fCLK/5
1
1
0
fCLK/4
1
1
1
fCLK/2
fCLK = 1 MHz fCLK = 2 MHz fCLK = 4 MHz
fCLK = 8 MHz fCLK = 16 MHz fCLK = 32 MHz
Setting
Setting
Setting
Setting
Setting
Setting
prohibited
prohibited
prohibited
prohibited
prohibited
prohibited
27 s
27 s
27 s
13.5 s
27 s
13.5 s
6.75 s
20.25 s
10.125 s
5.0625 s
33.75 s
16.875 s
8.4375 s
4.2188 s
27 s
13.5 s
6.75 s
3.375 s
13.5 s
6.75 s
3.375 s
Setting
prohibited
0
0
0
0
1
Normal 2
fCLK/64
Setting
Setting
Setting
Setting
Setting
Setting
prohibited
prohibited
prohibited
prohibited
prohibited
prohibited
25 s
12.5 s
25 s
12.5 s
6.25 s
25 s
0
0
1
fCLK/32
0
1
0
fCLK/16
0
1
1
fCLK/8
1
0
0
fCLK/6
37.5 s
18.75 s
9.375 s
4.6875 s
1
0
1
fCLK/5
31.25 s
15.625 s
7.8125 s
3.9063 s
1
1
0
fCLK/4
25 s
12.5 s
6.25 s
Setting
1
1
1
fCLK/2
12.5 s
6.25 s
Setting
prohibited
25 s
prohibited
Other than the above
Setting prohibited
Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, stop A/D conversion
once (ADCS = 0) beforehand.
2. The above conversion time does not include the conversion startup time. Add the conversion
startup time for the first conversion. Also, the above conversion time does not include clock
frequency errors. Select conversion time, taking clock frequency errors into consideration.
3. While in the hardware trigger wait mode, the conversion time includes the time spent waiting for
stabilization after the hardware trigger is detected.
Remark
fCLK: CPU/peripheral hardware clock frequency
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Table 11-3. A/D Conversion Time Selection (6/6)
(6) 1.8 V VDD < 5.5 V
When there is stabilization wait time (hardware trigger wait mode)
A/D Converter Mode Register 0
Mode
Conversion
Conversion Time Selection
Clock (fAD)
(ADM0)
FR2
FR1
FR0
LV1
LV0
0
0
0
0
0
Normal 1
fCLK/64
fCLK = 1 MHz fCLK = 2 MHz fCLK = 4 MHz
fCLK = 8 MHz fCLK = 16 MHz fCLK = 32 MHz
Setting
Setting
Setting
Setting
Setting
Setting
prohibited
prohibited
prohibited
prohibited
prohibited
prohibited
27 s
0
0
1
fCLK/32
0
1
0
fCLK/16
0
1
1
fCLK/8
1
0
0
fCLK/6
1
0
1
fCLK/5
33.75 s
Setting
1
1
0
fCLK/4
27 s
prohibited
1
1
1
fCLK/2
27 s
27 s
Setting
27 s
Setting
prohibited
20.25 s
prohibited
Setting
prohibited
0
0
0
0
1
Normal 2
fCLK/64
0
0
1
fCLK/32
0
1
0
fCLK/16
0
1
1
fCLK/8
1
0
0
fCLK/6
1
0
1
1
1
1
1
Setting
Setting
Setting
Setting
Setting
Setting
prohibited
prohibited
prohibited
prohibited
prohibited
prohibited
25 s
25 s
Setting
25 s
Setting
prohibited
37.5 s
18.75 s
prohibited
fCLK/5
31.25 s
Setting
0
fCLK/4
25 s
prohibited
1
fCLK/2
25 s
Setting
prohibited
Other than the above
Setting prohibited
Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, stop A/D conversion
once (ADCS = 0) beforehand.
2. The above conversion time does not include the conversion startup time. Add the conversion
startup time for the first conversion. Also, the above conversion time does not include clock
frequency errors. Select conversion time, taking clock frequency errors into consideration.
3. While in the hardware trigger wait mode, the conversion time includes the time spent waiting for
stabilization after the hardware trigger is detected.
Remark
fCLK: CPU/peripheral hardware clock frequency
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Figure 11-5. A/D Converter Sampling and A/D Conversion Timing (Example for Software Trigger Mode)
ADCS ← 1 or ADS rewrite
ADCS
Sampling
timing
INTAD
Sampling
Startup
time
Sampling
Successive conversion Transfer
to ADCR,
INTAD
generation
Conversion time
Conversion time
(3) A/D converter mode register 1 (ADM1)
This register is used to specify the A/D conversion trigger, conversion mode, and hardware trigger signal.
Hardware trigger mode with ADTRG is added to be supported. ADTRG is allocated to P72 as alternate function.
The ADM1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 11-6. Format of A/D Converter Mode Register 1 (ADM1)
Address: FFF32H
After reset: 00H
R/W
Symbol
4
3
2
ADM1
ADTMD1
ADTMD0
ADSCM
0
0
0
ADTRS1
ADTRS0
ADTMD1
ADTMD0
0
x
Software trigger mode
1
0
Hardware trigger no-wait mode
1
1
Hardware trigger wait mode
Selection of the A/D conversion trigger mode
ADSCM
Specification of the A/D conversion mode
0
Sequential conversion mode
1
One-shot conversion mode
ADTRS1
ADTRS0
Selection of the hardware trigger signal
0
0
End of TAU 02 count or capture interrupt (INTTM02)
0
1
End of TAU 04 count or capture interrupt (INTTM04)
1
0
Hardware trigger from external pin (ADTRG) without noise filter
1
1
Hardware trigger from external pin (ADTRG) with noise filter
(Cautions and Remarks are listed on the next page.)
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Cautions 1. Only rewrite the value of the ADM1 register while conversion operation is stopped (which is
indicated by the ADCE bit of A/D converter mode register 0 (ADM0) being 0).
2. To complete A/D conversion, the following hardware trigger interval time is required:
In hardware trigger no-wait mode: Two fCLK clock cycles + A/D conversion time
In hardware trigger wait mode: Two fCLK clock cycles + stabilization wait time + A/D conversion
time
Remarks 1. : don’t care
2. fCLK: CPU/peripheral hardware clock frequency
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(4) A/D converter mode register 2 (ADM2)
This register is used to select the A/D converter reference voltage, check the upper limit and lower limit A/D
conversion result values, select the resolution, and specify whether to use SNOOZE mode.
The ADM2 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 11-7. Format of A/D Converter Mode Register 2 (ADM2) (1/2)
Address: F0010H
After reset: 00H
R/W
Symbol
4
1
ADM2
ADREFP1
ADREFP0
ADREFM
0
ADRCK
AWC
0
ADTYP
ADREFP1
ADREFP0
0
0
Supplied from VDD
0
1
Supplied from P20/AVREFP/ANI0 (recommended setting)
1
0
Supplied from the internal reference voltage (1.45 V)
1
1
Setting prohibited
Selection of the + side reference voltage source of the A/D converter
Note
Rewrite the values of the ADREFP1 and ADREFP0 bits in the following procedure:
1. Set ADCE to 0.
2. Change ADREFP1 and ADREFP0.
3. Count the stabilization wait time (A).
4. Set ADCE to 1.
5. Count the stabilization wait time (B).
To set ADREFP1 to 1 and ADREFP0 to 0: A = 5 s, B = 1 s
To set ADREFP1 to 0 and ADREFP0 to 0, or ADREFP1 to 0 and ADREFP0 to 1: A = no wait, B = 1 s
After step 5, start A/D conversion.
Selection of the side reference voltage source of the A/D converter
ADREFM
0
Supplied from VSS
1
Supplied from P21/AVREFM/ANI1 (recommended setting)
Note Can only be selected in HS (high-speed main) mode.
ADRCK
0
Checking the upper limit and lower limit conversion result values
The interrupt signal (INTAD) is output when the ADLL register the ADCR register the ADUL register
().
1
The interrupt signal (INTAD) is output when the ADCR register < the ADLL register () or the ADUL
register < the ADCR register ().
Figure 11-8 shows the generation range of the interrupt signal (INTAD) for to .
Cautions 1. Only rewrite the value of the ADM2 register while conversion operation is stopped (which is
indicated by the ADCE bit of A/D converter mode register 0 (ADM0) being 0).
2. Do not set the ADREFP1 bit to 1 when shifting to STOP mode, or to HALT mode while the CPU is
operating on the subsystem clock.
3. To use AVREFP and AVREFM, set ANI0 and ANI1 to analog inputs and port mode register to input
mode.
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Figure 11-7. Format of A/D Converter Mode Register 2 (ADM2) (2/2)
Address: F0010H
After reset: 00H
R/W
Symbol
4
1
ADM2
ADREFP1
ADREFP0
ADREFM
0
ADRCK
AWC
0
ADTYP
AWC
Specification of SNOOZE mode
0
Do not use the SNOOZE mode function.
1
Use the SNOOZE mode function.
When there is a hardware trigger signal in the STOP mode, the STOP mode is exited, and A/D conversion is performed
without operating the CPU (the SNOOZE mode).
The SNOOZE mode function can only be specified when the high-speed on-chip oscillator clock is selected for the
CPU/peripheral hardware clock (fCLK). If any other clock is selected, specifying this mode is prohibited.
Using the SNOOZE mode function in the software trigger mode or hardware trigger no-wait mode is prohibited.
Using the SNOOZE mode function in the sequential conversion mode is prohibited.
When using the SNOOZE mode function, specify a hardware trigger interval of at least “transition time to SNOOZE
mode
Note
+ A/D power supply stabilization wait time + A/D conversion time + two fCLK clock cycles”.
When using the SNOOZE function in normal operation mode, set AWC to 0, and then change it to 1 immediately
before a transition to STOP mode.
Be sure to change AWC to 0 after returning from STOP mode to normal operation mode.
If AWC remains 1, A/D conversion is not correctly started regardless whether the subsequent mode is SNOOZE
mode or normal operation mode.
ADTYP
Selection of the A/D conversion resolution
0
10-bit resolution
1
8-bit resolution
Note See the descriptions of “From STOP to SNOOZE” in 22.2.3, SNOOZE mode.
Caution Only rewrite the value of the ADM2 register while conversion operation is stopped (which is
indicated by the ADCE bit of A/D converter mode register 0 (ADM0) being 0).
Figure 11-8. ADRCK Bit Interrupt Signal Generation Range
ADCR register value
(A/D conversion result)
1111111111
(ADUL < ADCR)
INTAD is generated
when ADRCK = 1.
ADUL register setting
(ADLL ≤ ADCR ≤ ADUL)
INTAD is generated
when ADRCK = 0.
ADLL register setting
0000000000
(ADCR < ADLL)
INTAD is generated
when ADRCK = 1.
Remark: If INTAD is not generated, the A/D conversion results are not stored in the ADCR or ADCRH register.
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(5) 10-bit A/D conversion result register (ADCR)
This register is a 16-bit register that stores the A/D conversion result in the select mode. The lower 6 bits are fixed to
0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register (SAR).
The higher 8 bits of the conversion result are stored in FFF1FH and the lower 2 bits are stored in the higher 2 bits of
FFF1EH. Note
The ADCR register can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Note If the A/D conversion result value is outside the range of values specified by the A/D conversion result
comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register (see figure 11-8)), the
value is not stored.
Figure 11-9. Format of 10-bit A/D Conversion Result Register (ADCR)
Address: FFF1FH, FFF1EH
After reset: 0000H
R
FFF1FH
Symbol
FFF1EH
ADCR
0
0
0
0
0
0
Cautions 1. When writing to the A/D converter mode register 0 (ADM0), analog input channel specification
register (ADS), and A/D port configuration register (ADPC), the contents of the ADCR register
may become undefined.
Read the conversion result following conversion completion before
writing to the ADM0, ADS, and ADPC registers. Using timing other than the above may cause an
incorrect conversion result to be read.
2. When 8-bit resolution A/D conversion is selected (when the ADTYP bit of A/D converter mode
register 2 (ADM2) is 1) and the ADCR register is read, 0 is read from the lower two bits (ADCR1
and ADCR0).
3. When the ADCR register is accessed in 16-bit units, the higher 10 bits of the conversion result
are read in order starting at bit 15.
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(6) 8-bit A/D conversion result register (ADCRH)
This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are stored.
The ADCRH register can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Note If the A/D conversion result value is outside the range of values specified by the A/D conversion result
comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register (see figure 11-8)), the
value is not stored.
Figure 11-10. Format of 8-bit A/D Conversion Result Register (ADCRH)
Address: FFF1FH
Symbol
7
After reset: 00H
6
5
R
4
3
2
1
0
ADCRH
Caution When writing to the A/D converter mode register 0 (ADM0), analog input channel specification
register (ADS), and A/D port configuration register (ADPC), the contents of the ADCRH register may
become undefined. Read the conversion result following conversion completion before writing to
the ADM0, ADS, and ADPC registers. Using timing other than the above may cause an incorrect
conversion result to be read.
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(7) Analog input channel specification register (ADS)
This register specifies the input channel of the analog voltage to be A/D converted.
The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 11-11. Format of Analog Input Channel Specification Register (ADS)
Address: FFF31H
After reset: 00H
R/W
Symbol
7
6
5
4
ADS
0
0
0
0
ADS.3
ADS.2
ADS.1
ADS.0
Select mode (ADMD = 0)
ADS3
ADS2
ADS1
ADS0
0
0
0
0
ANI0
P20/ANI0/AVREFP pin
0
0
0
1
ANI1
P21/ANI1/AVREFM pin
0
0
1
0
ANI2
P22/ANI2 pin
0
0
1
1
ANI3
P23/ANI3 pin
0
1
0
0
ANI4
P24/ANI4 pin
0
1
0
1
ANI5
P25/ANI5 pin
0
1
1
0
ANI6
P26/ANI6 pin
0
1
1
1
ANI7
P27/ANI7 pin
1
0
0
0
ANI8
P150/ANI8 pin
1
0
0
1
ANI9
P151/ANI9 pin
1
0
1
0
ANI10
P152/ANI10 pin
Other than the above
Analog input channel
Input source
Setting prohibited
Scan mode (ADMD = 1)
ADS3
ADS2
ADS1
ADS0
Analog input channel
Scan 0
Scan 1
Scan 2
Scan 3
0
0
0
0
ANI0
ANI1
ANI2
ANI3
0
0
0
1
ANI1
ANI2
ANI3
ANI4
0
0
1
0
ANI2
ANI3
ANI4
ANI5
0
0
1
1
ANI3
ANI4
ANI5
ANI6
0
1
0
0
ANI4
ANI5
ANI6
ANI7
0
1
0
1
ANI5
ANI6
ANI7
ANI8
0
1
1
0
ANI6
ANI7
ANI8
ANI9
0
1
1
1
ANI7
ANI8
ANI9
ANI10
Other than the above
Setting prohibited
(Cautions are listed on the next page.)
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Cautions 1. Be sure to clear bits 4, 5, 6, and 7 to 0.
2. Set a channel to be used for A/D conversion in the input mode by using port mode registers 2, 15
(PM2, PM15).
3. Do not set the pin that is set by the A/D port configuration register (ADPC) as digital I/O by the
ADS register.
4. If using AVREFP as the + side reference voltage source of the A/D converter, do not select ANI0 as
an A/D conversion channel.
5. If using AVREFM as the side reference voltage source of the A/D converter, do not select ANI1 as
an A/D conversion channel.
6. Do not set the ADREFP1 bit to 1 when shifting to STOP mode, or to HALT mode while the CPU is
operating on the subsystem clock.
7. The corresponding ANI pin does not exist depending on the product. In this case, ignore the
conversion result.
(8) Conversion result comparison upper limit setting register (ADUL)
This register is used to specify the setting for checking the upper limit of the A/D conversion results.
The A/D conversion results and ADUL register value are compared, and interrupt signal (INTAD) generation is
controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 11-8).
The ADUL register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Caution When 10-bit resolution A/D conversion is selected, the higher eight bits of the 10-bit A/D conversion
result register (ADCR) are compared with the ADUL register.
Figure 11-12. Format of Conversion Result Comparison Upper Limit Setting Register (ADUL)
Address: F0011H After reset: FFH R/W
Symbol
7
6
5
4
3
2
1
0
ADUL
ADUL.7
ADUL.6
ADUL.5
ADUL.4
ADUL.3
ADUL.2
ADUL.1
ADUL.0
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(9) Conversion result comparison lower limit setting register (ADLL)
This register is used to specify the setting for checking the lower limit of the A/D conversion results.
The A/D conversion results and ADLL register value are compared, and interrupt signal (INTAD) generation is
controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 11-8).
The ADLL register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 11-13. Format of Conversion Result Comparison Lower Limit Setting Register (ADLL)
Address: F0012H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
ADLL
ADLL.7
ADLL.6
ADLL.5
ADLL.4
ADLL.3
0
ADLL.1
ADLL.0
Caution When 10-bit resolution A/D conversion is selected, the higher eight bits of the 10-bit A/D conversion
result register (ADCR) are compared with the ADLL register.
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(10) A/D test register (ADTES)
This register is used to select the + side reference voltage (AVREFP) or - side reference voltage (AVREFM) of the A/D
converter, or the analog input channel (ANIxx) as the A/D conversion target for the A/D test function.
The ADTES register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 11-14. Format of A/D Test Register (ADTES)
Address: F0013H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
ADTES
0
0
0
0
0
ADTES2
ADTES1
ADTES0
ADTES2
ADTES1
ADTES0
0
0
0
A/D conversion target
ANIxx (This is specified using the analog input channel specification
register (ADS).)
0
1
0
AVREFM
0
1
1
AVREFP
Other than the above
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(11) A/D port configuration register (ADPC)
This register switches the ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI10/P152 pins to analog input of A/D converter
or digital I/O of port.
The ADPC register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 11-15. Format of A/D Port Configuration Register (ADPC)
Address: F0076H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
ADPC
0
0
0
0
ADPC.3
ADPC.2
ADPC.1
ADPC.0
ANI9/P151
ANI8/P150
ANI7/P27
ANI6/P26
ANI5/P25
ANI4/P24
ANI3/P23
ANI2/P22
ANI1/AVREFM/P21
ANI0/AVREFP/P20
0
A
A
A
A
A
A
A
A
A
A
A
0
0
0
1
D
D
D
D
D
D
D
D
D
D
D
0
0
1
0
D
D
D
D
D
D
D
D
D
D
A
0
0
1
1
D
D
D
D
D
D
D
D
D
A
A
0
1
0
0
D
D
D
D
D
D
D
D
A
A
A
0
1
0
1
D
D
D
D
D
D
D
A
A
A
A
0
1
1
0
D
D
D
D
D
D
A
A
A
A
A
0
1
1
1
D
D
D
D
D
A
A
A
A
A
A
1
0
0
0
D
D
D
D
A
A
A
A
A
A
A
1
0
0
1
D
D
D
A
A
A
A
A
A
A
A
1
0
1
0
D
D
A
A
A
A
A
A
A
A
A
1
0
1
1
D
A
A
A
A
A
A
A
A
A
A
Other than the above
ADPC0
0
ADPC1
0
ADPC2
0
ADPC3
ANI10/P152
Analog input (A)/digital I/O (D) switching
Setting prohibited
Cautions 1 Set the port to analog input by ADPC register to the input mode by using port mode registers 2,
15 (PM2, PM15).
2. Do not set the pin set by the ADPC register as digital I/O by the analog input channel
specification register (ADS).
3. To use AVREFP and AVREFM, set ANI0 and ANI1 to analog inputs and port mode register to input
mode.
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(12) Port mode registers (PM0 to PM15)
When using the ANI0 to ANI8 pin for an analog input port, set the PMmn bit to 1. The output latches of Pnm at this
time may be 0 or 1.
If the PMmn bits are set to 0, they cannot be used as analog input port pins.
The PMmn registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Caution If a pin is set as an analog input port, not the pin level but “0” is always read.
m = 0 to 15, n = 0 to 7
Remark
Figure 11-16. Format of Port Mode Register (128-pin products)
Symbol
7
6
5
4
3
2
1
0
PM0
PM07
PM06
PM05
PM04
PM03
PM02
PM01
PM00
FFF20
FFH
R/W
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
FFF21
FFH
R/W
PM2
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
FFF22
FFH
R/W
PM3
PM37
PM36
PM35
PM34
PM33
PM32
PM31
PM30
FFF23
FFH
R/W
PM4
PM47
PM46
PM45
PM44
PM43
PM42
PM41
PM40
FFF24
FFH
R/W
PM5
PM57
PM56
PM55
PM54
PM53
PM52
PM51
PM50
FFF25
FFH
R/W
PM6
1
PM66
PM65
PM64
PM63
PM62
PM61
PM60
FFF26
FFH
R/W
PM7
1
1
PM75
PM74
PM73
PM72
PM71
PM70
FFF27
FFH
R/W
PM8
PM87
PM86
PM85
PM84
PM83
PM82
PM81
PM80
FFF28
FFH
R/W
PM9
PM97
PM96
PM95
PM94
PM93
PM92
PM91
PM90
FFF29
FFH
R/W
PM10
PM107
PM106
PM105
PM104
PM103
PM102
PM101
PM100
FFF2A
FFH
R/W
PM11
PM117
PM116
PM115
PM114
PM113
PM112
PM111
PM110
FFF2B
FFH
R/W
PM12
PM127
PM126
PM125
1
1
1
1
1
FFF2C
FFH
R/W
PM13
1
PM136
PM135
PM134
PM133
PM132
PM131
0
FFF2D
FEH
R/W
PM14
1
1
1
1
1
1
1
PM140
FFF2E
FFH
R/W
PM15
1
1
1
1
1
PM152
PM151
PM150
FFF2F
FFH
R/W
PMmn
Address After reset R/W
Pmn pin I/O mode selection (m = 0 to 15 ; n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
Caution To use AVREFP and AVREFM, set ANI0 and ANI1 to analog inputs and port mode register to input mode.
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Remark
CHAPTER 11 A/D CONVERTER
For details of the port mode register other than 100-pin products, see 4. 3 Registers Controlling Port
Function.
The ANI0/P20 to ANI7/P27 pins are as shown below depending on the settings of the A/D port configuration register
(ADPC), analog input channel specification register (ADS), and PM2 registers.
Table 11-4. Setting Functions of ANI0/P20 to ANI7/P27 Pins
ADPC
Digital I/O selection
Analog input selection
PM2
ADS
ANI0/P20 to ANI7/P27 Pins
Input mode
Digital input
Output mode
Digital output
Input mode
Output mode
Selects ANI.
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
Selects ANI.
Setting prohibited
Does not select ANI.
The ANI8/P150 pin is as shown below depending on the settings of the A/D port configuration register (ADPC),
analog input channel specification register (ADS), and PM15 registers.
Table 11-5. Setting Functions of ANI8/P150 Pins
ADPC
Digital I/O selection
Analog input selection
PM15
ADS
ANI8/P150 to ANI10/P152 Pins
Input mode
Digital input
Output mode
Digital output
Input mode
Output mode
Selects ANI.
Analog input (to be converted)
Does not select ANI.
Analog input (not to be converted)
Selects ANI.
Setting prohibited
Does not select ANI.
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11.4 A/D Converter Conversion Operations
The A/D converter conversion operations are described below.
The voltage input to the selected analog input channel is sampled by the sample & hold circuit.
When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the
sampled voltage is held until the A/D conversion operation has ended.
Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to (1/2)
AVREF by the tap selector.
The voltage difference between the series resistor string voltage tap and sampled voltage is compared by the
voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB bit of the SAR register remains set
to 1. If the analog input is smaller than (1/2) AVREF, the MSB bit is reset to 0.
Next, bit 8 of the SAR register is automatically set to 1, and the operation proceeds to the next comparison. The
series resistor string voltage tap is selected according to the preset value of bit 9, as described below.
Bit 9 = 1: (3/4) AVREF
Bit 9 = 0: (1/4) AVREF
The voltage tap and sampled voltage are compared and bit 8 of the SAR register is manipulated as follows.
Sampled voltage Voltage tap: Bit 8 = 1
Sampled voltage < Voltage tap: Bit 8 = 0
Comparison is continued in this way up to bit 0 of the SAR register.
Upon completion of the comparison of 10 bits, an effective digital result value remains in the SAR register, and
the result value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latchedNote1.
At the same time, the A/D conversion end interrupt request (INTAD) can also be generatedNote1.
Note2
Repeat steps to , until the ADCS bit is cleared to 0
.
To stop the A/D converter, clear the ADCS bit to 0.
Notes 1.
If the A/D conversion result value is outside the range of values specified by the A/D conversion result
comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D
conversion end interrupt request signal (INTAD) is not generated. In this case, the result value is not stored
in the ADCR or ADCRH register.
2.
While in the sequential conversion mode, the ADCS flag is not automatically cleared to 0. This flag is not
automatically cleared to 0 while in the one-shot conversion mode of the hardware trigger no-wait mode,
either. Instead, 1 is retained.
Remarks 1. Two types of the A/D conversion result registers are available.
ADCR register (16 bits):
Store 10-bit A/D conversion value
ADCRH register (8 bits):
Store 8-bit A/D conversion value
2. AVREF: The + side reference voltage of the A/D converter. This can be selected from AVREFP, the internal
reference voltage (1.45 V), and VDD.
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Figure 11-17. Conversion Operation of A/D Converter (Software Trigger Mode)
ADCS ← 1 or ADS rewrite
Conversion time
Sampling time
A/D converter
operation
SAR
SAR clear
Sampling
A/D conversion
Undefined
ADCR
Conversion
result
Conversion
result
INTAD
A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is
reset (0) by software.
If a write operation is performed to the analog input channel specification register (ADS) during an A/D conversion
operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again from the beginning.
Reset signal generation clears the A/D conversion result register (ADCR, ADCRH) to 0000H or 00H.
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11.5 Input Voltage and Conversion Results
The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI8) and the theoretical A/D
conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression.
SAR = INT (
VAIN
AVREF
1024 + 0.5)
ADCR = SAR 64
or
(
ADCR
64
0.5)
where, INT( ):
AVREF
1024
VAIN < (
ADCR
64
+ 0.5)
AVREF
1024
Function which returns integer part of value in parentheses
VAIN:
Analog input voltage
AVREF:
AVREF pin voltage
ADCR: A/D conversion result register (ADCR) value
SAR:
Successive approximation register
Figure 11-18 shows the relationship between the analog input voltage and the A/D conversion result.
Figure 11-18. Relationship Between Analog Input Voltage and A/D Conversion Result
SAR
ADCR
1023
FFC0H
1022
FF80H
1021
FF40H
3
00C0H
2
0080H
1
0040H
A/D conversion result
0
0000H
1
1
3
2
5
3
2048 1024 2048 1024 2048 1024
2043 1022 2045 1023 2047 1
2048 1024 2048 1024 2048
Input voltage/AVREF
Remark AVREF: The + side reference voltage of the A/D converter. This can be selected from AVREFP, the internal
reference voltage (1.45 V), and VDD.
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CHAPTER 11 A/D CONVERTER
11.6 A/D Converter Operation Modes
The operation of each A/D converter mode is described below. In addition, the procedure for specifying each mode is
described in 11.7 A/D Converter Setup Flowchart.
11.6.1 Software trigger mode (select mode, sequential conversion mode)
In the power-down status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system
enters the A/D conversion standby status.
After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to
perform the A/D conversion of the analog input specified by the analog input channel specification register (ADS).
When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH),
and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion ends, the next
A/D conversion immediately starts.
When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register.
The partially converted data is discarded.
Even if a hardware trigger is input during conversion operation, A/D conversion does not start.
When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status.
When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the power-down
status. When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start.
Figure 11-19. Example of Software Trigger Mode (Select Mode, Sequential Conversion Mode) Operation Timing
ADCE is set to 1.
ADCE
ADCS
The trigger
is not
acknowledged.
ADCE is cleared to 0.
ADCS is set to 1 while in the
conversion standby status.
A/D conversion
ends and the next
conversion starts.
Power Conversion
down standby
Data 1
(ANI0)
ADCR,
ADCRH
Data 1
(ANI0)
Data 1
(ANI0)
Data 1
(ANI0)
ADCS is cleared to
0 during A/D
conversion operation.
A hardware trigger
is generated
(and ignored).
ADS is rewritten during
A/D conversion operation
(from ANI0 to ANI1).
Data 2
(ANI1)
Data 1
(ANI0)
ADS
A/D
conversion
status
ADCS is overwritten
with 1 during A/D
conversion operation.
Conversion is
interrupted
and restarts.
Data 1
Data 1
(ANI0)
(ANI0)
Data 1
(ANI0)
Data 2
(ANI1)
Data 1
(ANI0)
Data 2
(ANI1)
Data 2
(ANI1)
The trigger
is not
acknowledged.
Conversion is
interrupted.
Data 2
(ANI1)
Conversion Power
standby
down
Data 2
(ANI1)
INTAD
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CHAPTER 11 A/D CONVERTER
11.6.2 Software trigger mode (select mode, one-shot conversion mode)
In the power-down status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system
enters the A/D conversion standby status.
After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to
perform the A/D conversion of the analog input specified by the analog input channel specification register (ADS).
When A/D conversion ends, the conversion result is stored in the A/D conversion result register ADCR, ADCRH),
and the A/D conversion end interrupt request signal (INTAD) is generated.
After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the system enters the A/D conversion
standby status.
When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register.
The partially converted data is discarded.
When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status.
When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the power-down
status. When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start. In addition, A/D
conversion does not start even if a hardware trigger is input while in the A/D conversion standby status.
Figure 11-20. Example of Software Trigger Mode (Select Mode, One-Shot Conversion Mode) Operation Timing
ADCE is cleared to 0.
ADCE is set to 1.
ADCE
The trigger
is not
acknowledged.
ADCS is
ADCS is set to
1 while in the automatically
cleared to
conversion
0 after
standby status.
conversion
ends.
ADCS
Power Conversion
down standby
Data 1
(ANI0)
A/D
conversion
ends.
Conversion Data 1
standby
(ANI0)
ADCR,
ADCRH
ADS is rewritten during
A/D conversion operation
(from ANI0 to ANI1).
Data 2
(ANI1)
Data 1
(ANI0)
ADS
A/D
conversion
status
ADCS is overwritten
with 1 during A/D
conversion operation.
Data 1
(ANI0)
Conversion is
interrupted
and restarts.
Data 1
(ANI0)
ADCS is
cleared to
0 during A/D
conversion
operation.
Conversion is
interrupted.
Conversion
standby
Data 1
(ANI0)
Data 1
(ANI0)
Data 2
(ANI1)
The trigger
is not
acknowledged.
Conversion Data 2
standby (ANI1)
Conversion
standby
Power
down
Data 2
(ANI1)
INTAD
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CHAPTER 11 A/D CONVERTER
11.6.3 Software trigger mode (scan mode, sequential conversion mode)
In the power-down status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system
enters the A/D conversion standby status.
After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to
perform A/D conversion on the four analog input channels specified by scan 0 to scan 3, which are specified by
the analog input channel specification register (ADS). A/D conversion is performed on the analog input channels
in order, starting with that specified by scan 0.
A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in
the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end
interrupt request signal (INTAD) is generated.
After A/D conversion of the four channels ends, the A/D
conversion of the channel following the specified channel automatically starts (until all four channels are finished).
When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register.
The partially converted data is discarded.
Even if a hardware trigger is input during conversion operation, A/D conversion does not start.
When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status.
When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the power-down
status. When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start.
Figure 11-21. Example of Software Trigger Mode (Scan Mode, Sequential Conversion Mode) Operation Timing
ADCE is set to 1.
ADCE
The trigger
is not
acknowledged.
ADCS
ADCE is cleared to 0.
ADCS is set to 1 while in the
conversion standby status.
ADCS is overwritten
with 1 during A/D
conversion operation.
ADCS is cleared
A hardware trigger is
to 0 during A/D
generated (and ignored).
conversion operation.
The trigger
is not
acknowledged.
ADS is rewritten during
A/D conversion operation.
ADS
ANI0 to ANI3
ANI4 to ANI7
A/D conversion ends and the
next conversion starts.
A/D
conversion
status
Power Conversion Data 1 Data 2
down standby (ANI0) (ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
Data 1
(ANI0)
ADCR,
ADCRH
Data 1
(ANI0)
Data 2
(ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
Conversion is
interrupted and restarts.
Data 2
(ANI1)
Data 1 Data 2 Data 3
(ANI0) (ANI1) (ANI2)
Data 1 (ANI0)
Data 4 Data 1
(ANI3) (ANI0)
Conversion is
interrupted and restarts.
Data 2
(ANI1)
Data 2 Data 3 Data 4
(ANI1) (ANI2) (ANI3)
Data 5
(ANI4)
Data 1
(ANI0)
Conversion is
interrupted.
Data 6
(ANI5)
Data 7
(ANI6)
Data 8
(ANI7)
Data 5
(ANI4)
Data 5
(ANI4)
Data 6
(ANI5)
Data 7
(ANI6)
Data 8
(ANI7)
Data 6
(ANI5)
Conversion Power
standby
down
Data 5
(ANI4)
INTAD
The interrupt is generated four times.
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
The interrupt is generated four times.
The interrupt is generated four times.
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CHAPTER 11 A/D CONVERTER
11.6.4 Software trigger mode (scan mode, one-shot conversion mode)
In the power-down status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system
enters the A/D conversion standby status.
After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to
perform A/D conversion on the four analog input channels specified by scan 0 to scan 3, which are specified by
the analog input channel specification register (ADS). A/D conversion is performed on the analog input channels
in order, starting with that specified by scan 0.
A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in
the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end
interrupt request signal (INTAD) is generated.
After A/D conversion of the four channels ends, the ADCS bit is automatically cleared to 0, and the system enters
the A/D conversion standby status.
When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register.
The partially converted data is discarded.
When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status.
When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the power-down
status. When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start. In addition, A/D
conversion does not start even if a hardware trigger is input while in the A/D conversion standby status.
Figure 11-22. Example of Software Trigger Mode (Scan Mode, One-Shot Conversion Mode) Operation Timing
ADCE is set to 1.
ADCE
ADCS
The trigger
is not
acknowledged.
ADCE is cleared to 0.
ADCS is set to 1 while
in the conversion
standby status.
ADCS is
automatically
cleared to
0 after
conversion
ends.
ADCS is overwritten
with 1 during A/D
conversion operation.
ADCS is cleared
to 0 during A/D
conversion operation.
The trigger
is not
acknowledged.
ADS is rewritten during
A/D conversion operation.
ADS
ANI4 to ANI7
ANI0 to ANI3
A/D conversion
A/D
conversion
status
Power Conversion Data 1 Data 2
down standby (ANI0) (ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
ADCR,
ADCRH
Data 1
(ANI0)
Data 2
(ANI1)
Data 3
(ANI2)
ends.
Conversion Data 1 Data 2 Data 1 Data 2 Data 3 Data 4 Conversion Data 1
standby (ANI0) (ANI1) (ANI0) (ANI1) (ANI2) (ANI3) standby (ANI0)
Data 4
(ANI3)
Conversion is
interrupted and restarts.
Conversion is
interrupted and restarts.
Data 1 (ANI0)
Data 2 Data 3
(ANI1) (ANI2)
Data 4
(ANI3)
Data 2
(ANI1)
Data 5
(ANI4)
Data 1
(ANI0)
Data 6
(ANI5)
Data 5
(ANI4)
Data 7
(ANI6)
Data 6
(ANI5)
Conversion is
interrupted.
Data 8 Conversion Power
standby down
(ANI7)
Data 7
(ANI6)
INTAD
The interrupt is generated four times.
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CHAPTER 11 A/D CONVERTER
11.6.5 Hardware trigger no-wait mode (select mode, sequential conversion mode)
In the power-down status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system
enters the A/D conversion standby status.
After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to
place the system in the hardware trigger standby status (and conversion does not start at this stage). Note that,
while in this status, A/D conversion does not start even if ADCS is set to 1.
If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the analog input specified by the
analog input channel specification register (ADS).
When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH),
and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion ends, the next
A/D conversion immediately starts.
If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register.
The partially converted data is discarded.
When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status. However, the A/D converter does not power down in this
status.
When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the power-down
status. When ADCS = 0, inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 11-23. Example of Hardware Trigger No-Wait Mode (Select Mode, Sequential Conversion Mode) Operation
Timing
ADCE is cleared to 0.
ADCE is set to 1.
ADCE
ADCS is set to 1.
A hardware trigger is
generated during A/D
conversion operation.
A hardware trigger
is generated.
Hardware
trigger
Trigger
The trigger is not standby
acknowledged. status
ADCS
Data 1
(ANI0)
A/D conversion
ends and the next
conversion
starts.
ADS
A/D
conversion
status
Power
down
Conversion
standby
Data 1
(ANI0)
ADCR,
ADCRH
Data 1
(ANI0)
Data 1
(ANI0)
Data 1
(ANI0)
The trigger is not
acknowledged.
ADCS is overwritten ADCS is cleared
with 1 during A/D
to 0 during A/D
conversion operation. conversion operation.
ADS is rewritten during
A/D conversion operation
(from ANI0 to ANI1).
Data 2
(ANI1)
Conversion is
interrupted and
Conversion
Conversion is
Conversion is
is interrupted.
restarts.
interrupted
interrupted
and restarts.
and restarts.
Data 2
Data 2
Data 2
Data 1
Data 2 Conversion
Data 1
(ANI1)
(ANI1)
(ANI1)
(ANI0)
(ANI1) standby
(ANI0)
Data 1
(ANI0)
Data 1
(ANI0)
Data 2
(ANI1)
Power
down
Data 2
(ANI1)
INTAD
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CHAPTER 11 A/D CONVERTER
11.6.6 Hardware trigger no-wait mode (select mode, one-shot conversion mode)
In the power-down status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system
enters the A/D conversion standby status.
After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to
place the system in the hardware trigger standby status (and conversion does not start at this stage). Note that,
while in this status, A/D conversion does not start even if ADCS is set to 1.
If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the analog input specified by the
analog input channel specification register (ADS).
When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH),
and the A/D conversion end interrupt request signal (INTAD) is generated.
After A/D conversion ends, the ADCS bit remains set to 1, and the system enters the A/D conversion standby
status.
If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register.
The partially converted data is discarded.
When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status. However, the A/D converter does not power down in this
status.
When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the power-down
status. When ADCS = 0, inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 11-24. Example of Hardware Trigger No-Wait Mode (Select Mode, One-Shot Conversion Mode) Operation
Timing
ADCE is cleared to 0.
ADCE is set to 1.
ADCS is set to 1.
ADCE
A hardware trigger
is generated.
Hardware
trigger
A hardware trigger is
generated during A/D
conversion operation.
The trigger is not Trigger ADCS retains
acknowledged. standby the value 1.
status
ADCS
ADCS is overwritten with 1 during
A/D conversion
operation.
ADS is rewritten during
A/D conversion operation
(from ANI0 to ANI1).
A/D conversion
ends.
A/D
conversion
status
Power
down
Conversion
standby
ADCS is cleared
to 0 during A/D
conversion
operation.
Data 2
(ANI1)
Data 1
(ANI0)
ADS
Trigger
standby
status
Data 1
(ANI0)
ADCR,
ADCRH
Conversion
standby
Conversion is
interrupted
and restarts.
Data 1
(ANI0)
Data 1
(ANI0)
Data 1
(ANI0)
Conversion
standby
Conversion is
interrupted
and restarts.
Conversion is
interrupted
and restarts.
Data 1
(ANI0)
Data 1
(ANI0)
Data 2
(ANI1)
Conversion Data 2
standby (ANI1)
Data 2
(ANI1)
Data 2
(ANI1)
Conversion
standby
Conversion is
interrupted.
Data 2 Conversion Power
(ANI1) standby down
Data 2
(ANI1)
INTAD
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CHAPTER 11 A/D CONVERTER
11.6.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode)
In the power-down status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system
enters the A/D conversion standby status.
After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to
place the system in the hardware trigger standby status (and conversion does not start at this stage). Note that,
while in this status, A/D conversion does not start even if ADCS is set to 1.
If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the four analog input channels
specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). A/D
conversion is performed on the analog input channels in order, starting with that specified by scan 0.
A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in
the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end
interrupt request signal (INTAD) is generated.
After A/D conversion of the four channels ends, the A/D
conversion of the channel following the specified channel automatically starts.
If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register.
The partially converted data is discarded.
When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status. However, the A/D converter does not power down in this
status.
When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the power-down
status. When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start.
Figure 11-25. Example of Hardware Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode) Operation
Timing
ADCE is set to 1.
ADCE
ADCE is cleared to 0.
ADCS is set to 1.
A hardware trigger is
generated during A/D
conversion operation.
A hardware trigger
is generated.
Hardware
trigger
The trigger is not
acknowledged.
Trigger The trigger
standby is not
status acknowledged.
Trigger
standby
status
ADCS is overwritten
with 1 during A/D
conversion operation.
ADCS is cleared to 0
during A/D conversion
operation.
ADCS
ADS is rewritten during
A/D conversion operation.
ADS
ANI4 to ANI7
ANI0 to ANI3
A/D conversion
ends and the next
conversion starts.
A/D
conversion
status
Power Conversion Data 1 Data 2
standby (ANI0) (ANI1)
down
Data 3
(ANI2)
Data 4
(ANI3)
Data 1
(ANI0)
ADCR,
ADCRH
Data 1
(ANI0)
Data 2
(ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
Data 2
(ANI1)
Conversion is
interrupted
and restarts.
Data 1 Data 2 Data 3
(ANI0) (ANI1) (ANI2)
Data 4 Data 1
(ANI3) (ANI0)
Data 1 (ANI0)
Conversion is
interrupted
and restarts.
Data 2
(ANI1)
Data 2 Data 3 Data 4
(ANI1) (ANI2) (ANI3)
Data 5
(ANI4)
Data 1
(ANI0)
Conversion is
interrupted
and restarts.
Data 6
(ANI5)
Data 7
(ANI6)
Data 8
(ANI7)
Data 5
(ANI4)
Data 6
(ANI5)
Data 5
(ANI4)
Data 6
(ANI5)
Data 7
(ANI6)
Data 8
(ANI7)
Data 5
(ANI4)
Data 7
(ANI6)
Data 5
(ANI4)
Data 6
(ANI5)
Data 6
(ANI5)
Data 7 Data 8
(ANI6) (ANI7)
Data 5 Data 6
(ANI4) (ANI5)
Data 7
(ANI6)
Conversion is
interrupted.
Data 5 Conversion Power
(ANI4)
standby
down
Data 8
(ANI7)
INTAD
The interrupt is generated four times.
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
The interrupt is generated four times.
The interrupt is generated four times.
The interrupt is generated four times.
574
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CHAPTER 11 A/D CONVERTER
11.6.8 Hardware trigger no-wait mode (scan mode, one-shot conversion mode)
In the power-down status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system
enters the A/D conversion standby status.
After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to
place the system in the hardware trigger standby status (and conversion does not start at this stage). Note that,
while in this status, A/D conversion does not start even if ADCS is set to 1.
If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the four analog input channels
specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). A/D
conversion is performed on the analog input channels in order, starting with that specified by scan 0.
A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in
the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end
interrupt request signal (INTAD) is generated.
After A/D conversion of the four channels ends, the ADCS bit remains set to 1, and the system enters the A/D
conversion standby status.
If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register.
The partially converted data is discarded.
When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status. However, the A/D converter does not power down in this
status.
When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the power-down
status. When ADCS = 0, inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 11-26. Example of Hardware Trigger No-Wait Mode (Scan Mode, One-Shot Conversion Mode) Operation
Timing
ADCE is set to 1.
ADCE
Hardware
trigger
ADCE is cleared to 0.
ADCS is set to 1.
A hardware trigger
is generated.
The trigger is not Trigger
acknowledged. standby
status
A hardware trigger is
generated during A/D
conversion operation.
ADCS retains
the value 1.
ADS is rewritten
during A/D
conversion operation.
ANI0 to ANI3
ANI4 to ANI7
A/D
Conversion is
interrupted
and restarts.
conversion
ends.
A/D
conversion
status
ADCR,
ADCRH
Power Conversion
down
standby
Conversion
standby
status
ADCS is overwritten ADCS is cleared
with 1 during A/D
to 0 during A/D
conversion operation.
conversion
operation.
ADCS
ADS
Data 1 Data 2 Data 3 Data 4 Conversion Data 1
(ANI0) (ANI1) (ANI2) (ANI3) standby (ANI0)
Data 1 Data 2 Data 3
(ANI0) (ANI1) (ANI2)
Data 4
(ANI3)
Data 2
(ANI1)
Conversion is
interrupted
and restarts.
Data 1 Data 2 Data 3 Data 4 Conversion Data 1
(ANI0) (ANI1) (ANI2) (ANI3) standby (ANI0)
Data 1 (ANI0)
Data 2 Data 3
(ANI1) (ANI2)
Data 4
(ANI3)
Data 2
(ANI1)
Conversion is Conversion is
interrupted.
interrupted
and restarts.
Data 5 Data 6 Data 7 Data 8 Conversion Data 5
(ANI4) (ANI5) (ANI6) (ANI7) standby (ANI4)
Data 1
(ANI0)
Data 5 Data 6 Data 7
(ANI4) (ANI5) (ANI6)
Data 8
(ANI7)
Data 6
(ANI5)
Data 5 Data 6
(ANI4) (ANI5)
Data 5 (ANI4)
Data 7
(ANI6)
Conversion Power
standby down
Data 6
(ANI5)
INTAD
The interrupt is generated four times.
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The interrupt is generated four times.
The interrupt is generated four times.
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11.6.9 Hardware trigger wait mode (select mode, sequential conversion mode)
In the power-down status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system
enters the hardware trigger standby status.
If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the
analog input specified by the analog input channel specification register (ADS). The ADCS bit of the ADM0
register is automatically set to 1 according to the hardware trigger input.
When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH),
and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion ends, the next
A/D conversion immediately starts. (At this time, no hardware trigger is necessary.)
If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register.
The partially converted data is discarded.
When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system
enters the hardware trigger standby status, and the A/D converter enters the power-down status. When ADCE =
0, inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 11-27. Example of Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode) Operation
Timing
ADCE is set to 1.
ADCE
A hardware trigger
is generated.
Hardware
trigger
The trigger
is not
acknowledged.
ADCS
Trigger
standby
status
Data 1
(ANI0)
ADS
A/D
conversion
status
A hardware trigger is
generated during A/D
conversion operation.
A/D conversion ends
and the next
conversion
starts.
Power down
Data 1
(ANI0)
ADCR,
ADCRH
Data 1
(ANI0)
Data 1
(ANI0)
Data 1
(ANI0)
Trigger The trigger
standby is not
status acknowledged.
ADCS is overwritten ADCS is cleared
to 0 during A/D
with 1 during A/D
conversion operation. conversion operation.
ADS is rewritten during
A/D conversion operation
(from ANI0 to ANI1).
Data 2
(ANI1)
Conversion is
Conversion is
Conversion is
interrupted and
Conversion is
interrupted
interrupted.
restarts.
interrupted
and restarts.
and restarts.
Data 1
Data 2
Data 2
Data 1
Data 2
Data 2
Power down
(ANI0)
(ANI1)
(ANI1)
(ANI0)
(ANI1)
(ANI1)
Data 1
(ANI0)
Data 1
(ANI0)
Data 2
(ANI1)
Data 2
(ANI1)
INTAD
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11.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode)
In the power-down status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system
enters the hardware trigger standby status.
If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the
analog input specified by the analog input channel specification register (ADS). The ADCS bit of the ADM0
register is automatically set to 1 according to the hardware trigger input.
When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH),
and the A/D conversion end interrupt request signal (INTAD) is generated.
After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the A/D converter enters the powerdown status.
If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register.
The partially converted data is discarded.
When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is initialized.
When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system
enters the hardware trigger standby status, and the A/D converter enters the power-down status. When ADCE =
0, inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 11-28. Example of Hardware Trigger Wait Mode (Select Mode, One-Shot Conversion Mode) Operation
Timing
ADCE is set to 1.
ADCE
A hardware trigger
is generated.
Hardware
trigger
A hardware trigger is
generated during A/D
conversion operation.
Trigger ADCS is automatically
The trigger is not standby
acknowledged. status
cleared to 0 after
conversion ends.
ADCS
Trigger
standby
status
ADCS is overwritten
with 1 during A/D
conversion operation.
is rewritten
ADS
during A/D conversion
ADCS is cleared
to 0 during A/D
conversion
operation.
operation (from ANI0
to ANI1).
Data 1
(ANI0)
ADS
A/D conversion
ends.
A/D
conversion
status
Power down
Data 1
(ANI0)
ADCR,
ADCRH
Power
down
Data 1
(ANI0)
Conversion is
interrupted
and restarts.
Power Data 1
Data 1
down (ANI0)
(ANI0)
Data 1
(ANI0)
Data 2
(ANI1)
Conversion is
interrupted
and restarts.
Data 1
(ANI0)
Data 2
(ANI1)
Power
down
Conversion is
interrupted
and restarts.
Data 2
(ANI1)
Data 2
(ANI1)
Data 2
(ANI1)
Conversion is
interrupted.
Power Data 2
down (ANI1)
Power down
Data 2
(ANI1)
INTAD
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11.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode)
In the power-down status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system
enters the A/D conversion standby status.
If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the
four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel
specification register (ADS). The ADCS bit of the ADM0 register is automatically set to 1 according to the
hardware trigger input. A/D conversion is performed on the analog input channels in order, starting with that
specified by scan 0.
A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in
the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end
interrupt request signal (INTAD) is generated.
After A/D conversion of the four channels ends, the A/D
conversion of the channel following the specified channel automatically starts.
If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register.
The partially converted data is discarded.
When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system
enters the hardware trigger standby status, and the A/D converter enters the power-down status. When ADCE =
0, inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 11-29. Example of Hardware Trigger Wait Mode (Scan Mode, Sequential Conversion Mode) Operation
Timing
ADCE is set to 1.
ADCE
A hardware trigger is
generated during A/D
conversion operation.
A hardware trigger
is generated.
Hardware
trigger
The trigger is not
acknowledged.
Trigger The trigger
standby is not
status acknowledged.
Trigger
standby status
ADCS is overwritten
with 1 during A/D
conversion operation.
ADCS is cleared
to 0 during A/D
conversion operation.
ADCS
ADS is rewritten during
A/D conversion operation.
ADS
A/D
conversion
status
ADCR,
ADCRH
ANI4 to ANI7
ANI0 to ANI3
A/D conversion
ends and the next
conversion starts.
Power down
Data 1
(ANI0)
Data 2
(ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
Data 1
(ANI0)
Data 1
(ANI0)
Data 2
(ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
Conversion is
interrupted and restarts.
Data 2
(ANI1)
Data 1 Data 2 Data 3
(ANI0) (ANI1) (ANI2)
Data 1 (ANI0)
Data 4 Data 1
(ANI3) (ANI0)
Conversion is
interrupted and restarts.
Data 2
(ANI1)
Data 2 Data 3 Data 4
(ANI1) (ANI2) (ANI3)
Data 5
(ANI4)
Data 1
(ANI0)
Conversion is
interrupted and restarts.
Data 6
(ANI5)
Data 7
(ANI6)
Data 8
(ANI7)
Data 5
(ANI4)
Data 6
(ANI5)
Data 5
(ANI4)
Data 6
(ANI5)
Data 7
(ANI6)
Data 8
(ANI7)
Data 5
(ANI4)
Data 7
(ANI6)
Data 5
(ANI4)
Data 6
(ANI5)
Data 6
(ANI5)
Data 7 Data 8
(ANI6) (ANI7)
Data 5 Data 6
(ANI4) (ANI5)
Data 7
(ANI6)
Conversion is
interrupted.
Data 5
(ANI4)
Power down
Data 8
(ANI7)
INTAD
The interrupt is generated four times.
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The interrupt is generated four times.
The interrupt is generated four times.
The interrupt is generated four times.
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CHAPTER 11 A/D CONVERTER
11.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode)
In the power-down status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system
enters the A/D conversion standby status.
If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the
four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel
specification register (ADS). The ADCS bit of the ADM0 register is automatically set to 1 according to the
hardware trigger input. A/D conversion is performed on the analog input channels in order, starting with that
specified by scan 0.
A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in
the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end
interrupt request signal (INTAD) is generated.
After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the A/D converter enters the powerdown status.
If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register.
The partially converted data is discarded.
When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system
enters the hardware trigger standby status, and the A/D converter enters the power-down status. When ADCE =
0, inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 11-30. Example of Hardware Trigger Wait Mode (Scan Mode, One-Shot Conversion Mode) Operation
Timing
ADCE is set to 1.
ADCE
A hardware trigger
is generated.
Hardware
trigger
The trigger is not Trigger
acknowledged. standby
ADCS
status
ADS
A hardware trigger is
generated during A/D
conversion operation.
ADCS is automatically
cleared to 0 after
conversion ends.
ANI0 to ANI3
ADCR,
ADCRH
Power down
ADCS is overwritten ADCS is cleared
with 1 during A/D
conversion operation. to 0 during A/D
conversion
operation.
ADS is rewritten
during A/D
conversion operation.
ANI4 to ANI7
Conversion is
interrupted
and restarts.
A/D
conversion
ends.
A/D
conversion
status
Conversion
standby The trigger is not
status
acknowledged.
Data 1 Data 2 Data 3 Data 4
(ANI0) (ANI1) (ANI2) (ANI3)
Data 1 Data 2 Data 3
(ANI0) (ANI1) (ANI2)
Power
down
Data 1
(ANI0)
Data 4
(ANI3)
Data 2
(ANI1)
Data 1 Data 2 Data 3 Data 4
(ANI0) (ANI1) (ANI2) (ANI3)
Data 1 (ANI0)
Conversion is
interrupted
and restarts.
Data 2 Data 3
(ANI1) (ANI2)
Power
down
Data 1
(ANI0)
Data 4
(ANI3)
Data 2
(ANI1)
Data 5 Data 6 Data 7 Data 8
(ANI4) (ANI5) (ANI6) (ANI7)
Data 1
(ANI0)
Conversion is Conversion is
interrupted.
interrupted
and restarts.
Data 5 Data 6 Data 7
(ANI4) (ANI5) (ANI6)
Power
down
Data 5
(ANI4)
Data 8
(ANI7)
Data 6
(ANI5)
Data 5 Data 6
(ANI4) (ANI5)
Data 5 (ANI4)
Data 7
(ANI6)
Power down
Data 6
(ANI5)
INTAD
The interrupt is generated four times.
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The interrupt is generated four times.
The interrupt is generated four times.
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11.7 A/D Converter Setup Flowchart
The A/D converter setup flowchart in each operation mode is described below.
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CHAPTER 11 A/D CONVERTER
11.7.1 Setting up software trigger mode
Figure 11-31. Setting up Software Trigger Mode
Start of setup
PER1 register setting
ADPC register settings
PM register setting
The ADCEN bit of the PER1 register is set (1), and supplying the clock starts.
The ports are set to analog input.
ANI0 to ANI8 pins: Set using the ADPC register
The ports are set to the input mode.
ADM0 register
FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time.
ADMD bit: Select mode/scan mode
ADM1 register
ADTMD1 and ADTMD0 bits: These are used to specify the software trigger mode.
ADSCM bit: Sequential conversion mode/one-shot conversion mode
ADM0 register setting
ADM1 register setting
ADM2 register setting
ADUL/ADLL register setting
ADS register setting
(The order of the settings is
irrelevant.)
ADM2 register
ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference
voltage source.
ADRCK bit: This is used to select the range for the A/D conversion result
comparison value generated by the interrupt signal from AREA1,
AREA3, and AREA2.
ADTYP bit: 8-bit/10-bit resolution
ADUL/ADLL register
These are used to specify the upper limit and lower limit A/D conversion result
comparison values.
ADS register
ADS.3 to ADS.0 bits: These are used to select the analog input channels.
The stabilization wait time A is necessary for changing ADREFP1 and ADREFP0.
Stabilization wait time count (A)
A = 5 s when ADREFP1 and ADREFP0 are set to 1 and 0, respectively.
No wait time is necessary when ADREFP1 and ADREFP0 are set to 0 and 0 or 0 and 1.
ADCE bit setting
Stabilization wait time count (B)
ADCS bit setting
The ADCE bit of the ADM0 register is set (1), and the system enters the A/D
conversion standby status.
The software counts up to the stabilization wait time (1 s).
After counting up to the stabilization wait time ends, the ADCS bit of the ADM0
register is set (1), and A/D conversion starts.
Start of A/D conversion
The A/D conversion operations are performed.
End of A/D conversion
Storage of conversion results in the
ADCR and ADCRH registers
The A/D conversion end interrupt (INTAD) is generated.
Note
The conversion results are stored in the ADCR and ADCRH registers.
Note Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal
being generated. In this case, the results are not stored in the ADCR and ADCRH registers.
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11.7.2 Setting up hardware trigger no-wait mode
Figure 11-32. Setting up Hardware Trigger No-Wait Mode
Start of setup
The ADCEN bit of the PER1 register is set (1), and supplying the clock starts.
PER1 register setting
ADPC register settings
PM register setting
The ports are set to analog input.
ANI0 to ANI8 pins: Set using the ADPC register
The ports are set to the input mode.
ADM0 register
FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time.
ADMD bit: Select mode/scan mode
ADM1 register
ADTMD1 and ADTMD0 bits: These are used to specify the hardware trigger no-wait
ADM0 register setting
ADM1 register setting
ADM2 register setting
mode.
ADSCM bit: Sequential conversion mode/one-shot conversion mode
ADM2 register
ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference
voltage source.
ADUL/ADLL register setting
ADS register setting
ADRCK bit: This is used to select the range for the A/D conversion result comparison
value generated by the interrupt signal from AREA1, AREA3, and
(The order of the settings is
irrelevant.)
AREA2.
ADUL/ADLL register
These are used to specify the upper limit and lower limit A/D conversion result
comparison values.
ADS register
ADS.3 to ADS.0 bits:These are used to select the analog input channels.
Stabilization wait time count A
ADCE bit setting
Stabilization wait time count B
ADCS bit setting
The stabilization wait time A is necessary for changing ADREFP1 and ADREFP0.
A = 5 s when ADREFP1 and ADREFP0 are set to 1 and 0, respectively.
No wait time is necessary when ADREFP1 and ADREFP0 are set to 0 and 0 or 0 and 1.
The ADCE bit of the ADM0 register is set (1), and the system enters the A/D conversion
standby status.
The software counts up to the stabilization wait time (1 s).
After counting up to the stabilization wait time ends, the ADCS bit of the ADM0 register
is set (1), and the system enters the hardware trigger standby status.
Hardware trigger standby status
Start of A/D conversion by
generating a hardware trigger
The A/D conversion operations are performed.
End of A/D conversion
The A/D conversion end interrupt (INTAD) is generated.Note
Storage of conversion results in the
ADCR and ADCRH registers
The conversion results are stored in the ADCR and ADCRH registers.
Note Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal
being generated. In this case, the results are not stored in the ADCR and ADCRH registers.
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11.7.3 Setting up hardware trigger wait mode
Figure 11-33. Setting up Hardware Trigger Wait Mode
Start of setup
PER1 register setting
ADPC register settings
The ADCEN bit of the PER1 register is set (1), and supplying the clock starts.
The ports are set to analog input.
ANI0 to ANI8 pins: Set using the ADPC register
PM register setting
The ports are set to the input mode.
ADM0 register
FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time.
ADMD bit: Select mode/scan mode
ADM1 register
ADTMD1 and ADTMD0 bits: These are used to specify the hardware trigger wait mode.
ADM0 register setting
ADM1 register setting
ADM2 register setting
ADSCM bit: Sequential conversion mode/one-shot conversion mode
ADTRS1 and ADTRS0 bits: These are used to select the hardware trigger signal.
ADM2 register
ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference
ADUL/ADLL register setting
ADS register setting
(The order of the settings is
irrelevant.)
voltage source.
ADRCK bit: This is used to select the range for the A/D conversion result comparison
value generated by the interrupt signal from AREA1, AREA3, and AREA2.
AWC bit:
This is used to set up the SNOOZE mode function.
ADTYP bit: 8-bit/10-bit resolution
ADUL/ADLL register
These are used to specify the upper limit and lower limit A/D conversion result
comparison values.
ADS register
ADS.3 to ADS.0 bits: These are used to select the analog input channels.
The stabilization wait time A is necessary for changing ADREFP1 and ADREFP0.
Stabilization wait time count
A = 5 s when ADREFP1 and ADREFP0 are set to 1 and 0, respectively.
No wait time is necessary when ADREFP1 and ADREFP0 are set to 0 and 0 or 0 and 1.
ADCE bit setting
The ADCE bit of the ADM0 register is set (1), and the system enters the A/D conversion
standby status.
Hardware trigger generation
Stabilization wait time count
Start of A/D conversion
The system automatically counts up to the stabilization wait time.
After counting up to the stabilization wait time ends, A/D conversion starts
The A/D conversion operations are performed.
End of A/D conversion
Storage of conversion results in the
ADCR and ADCRH registers
The A/D conversion end interrupt (INTAD) is generated.
Note
The conversion results are stored in the ADCR and ADCRH registers.
Note Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal
being generated. In this case, the results are not stored in the ADCR and ADCRH registers.
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11.7.4 Setting up test mode
Figure 11-34. Setting up Test Trigger Mode
Start of setup
PER1 register setting
The ADCEN bit of the PER1 register is set (1), and supplying the clock starts.
ADCE bit setting
The ADCE bit of the ADM0 register is set (1), and the system enters the A/D
conversion standby status.
ADPC register settings
The ports are set to analog input.
ANI0 to ANI8 pins: Set using the ADPC register
PM register setting
The ports are set to the input mode.
ADM0 register
FR2 to FR0, LV1, and LV0 bits: 11100B (set to fCLK/2, normal mode)
ADMD bit: This is used to specify the select mode.
ADM1 register
ADTMD1 and ADTMD0 bits: These are used to specify the software trigger mode.
ADSCM bit: This is used to specify the one-shot conversion mode.
ADM0 register setting
ADM1 register setting
ADM2 register
ADREFP1, ADREFP0, and ADREFM bits: These are used to select VDD and VSS for
ADM2 register setting
ADUL/ADLL register setting
ADS register setting
ADTES register setting
(The order of the settings is
irrelevant.)
the reference voltage source.
ADRCK bit: This is used to set the range for the A/D conversion result comparison
value generated by the interrupt signal to a desired value.
ADTYP bit: This is used to specify 10-bit resolution.
ADUL/ADLL register
These set ADUL and ADLL to desired values.
ADS register
ADS.3 to ADS.0 bits: These are used to set to ANI0.
ADTES register
ADTES.2 to ADTES.0 bits: AVREFM/AVREFP
Stabilization wait time count (1 s)
ADCS bit setting
The software counts up to the stabilization wait time (1 s).
After counting up to the stabilization wait time ends, the ADCS bit of the ADM0 register
is set (1), and A/D conversion starts.
Start of A/D conversion
The A/D conversion operations are performed.
End of A/D conversion
The A/D conversion end interrupt (INTAD) is generated.
Note
Storage of conversion results in the
ADCR and ADCRH registers
The conversion results are stored in the ADCR and ADCRH registers.
Note Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal
being generated. In this case, the results are not stored in the ADCR and ADCRH registers.
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11.8 SNOOZE Mode Function
In the SNOOZE mode, A/D conversion is triggered by inputting a hardware trigger in the STOP mode. Normally, A/D
conversion is stopped while in the STOP mode, but, by using the SNOOZE mode, A/D conversion can be performed
without operating the CPU by inputting a hardware trigger. This is effective for reducing the operation current.
By specifying the conversion result range with ADUL and ADLL in SNOOZE mode, A/D conversion results can be
checked at the specified interval, which allows the monitoring of power supply voltage and check of A/D input keys.
In the SNOOZE mode, only the following two conversion modes can be used:
Hardware trigger wait mode (select mode, one-shot conversion mode)
Hardware trigger wait mode (scan mode, one-shot conversion mode)
Note that the SNOOZE mode can only be specified when the high-speed on-chip oscillator clock is selected for fCLK.
Figure 11-35. Block Diagram When Using SNOOZE Mode Function
Clock request signal
(internal signal)
Hardware trigger input
Clock generator
A/D converter
A/D conversion end
interrupt request
signalNote 1 (INTAD)
High-speed
on-chip oscillator clock
When using the SNOOZE mode function, the initial setting of each register is specified before switching to the STOP
mode. (For details about these settings, see 11.7.3 Setting up hardware trigger wait modeNote 2.) At this time, bit 2
(AWC) of A/D converter mode register 2 (ADM2) is set to 1. After the initial settings are specified, bit 0 (ADCE) of A/D
converter mode register 0 (ADM0) is set to 1.
If a hardware trigger is input after switching to the STOP mode, the high-speed on-chip oscillator clock is supplied to
the A/D converter. After supplying this clock, the system automatically counts up to the stabilization wait time, and then
A/D conversion starts.
The SNOOZE mode operation after A/D conversion ends differs depending on whether an interrupt signal is
generatedNote 1.
Notes 1.
Depending on the setting of the A/D conversion result comparison function (ADRCK bit, ADUL/ADLL
register), there is a possibility of no interrupt signal being generated.
2.
Be sure to set the ADM1 register to E2H or E3H.
Remark The hardware trigger is ADTRG.
Specify the hardware trigger by using the A/D Converter Mode Register 1 (ADM1).
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(1) If an interrupt is generated after A/D conversion ends
If the A/D conversion result value is within the range of values specified by the A/D conversion result comparison
function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request
signal (INTAD) is generated.
While in the select mode
After A/D conversion ends and the A/D conversion end interrupt request signal (INTAD) is generated, the A/D
converter switches from the SNOOZE mode to the normal operation mode. At this time, clear bit 2 (AWC) of A/D
converter mode register 2 (ADM2) to 0 to release SNOOZE mode. If AWC remains 1, A/D conversion is not
correctly started regardless whether the subsequent mode is SNOOZE mode or normal operation mode.
While in the scan mode
If even one A/D conversion end interrupt request signal (INTAD) is generated during A/D conversion of the four
channels, the A/D converter switches from the SNOOZE mode to the normal operation mode. At this time, clear bit
2 (AWC) of A/D converter mode register 2 (ADM2) to 0 to release SNOOZE mode. If AWC remains 1, A/D
conversion is not correctly started regardless whether the subsequent mode is SNOOZE mode or normal operation
mode.
Figure 11-36. Operation Example When Interrupt Is Generated After A/D Conversion Ends (While in Scan Mode)
ADTRG
Clock request signal
(internal signal)
The clock request signal
remains at the high level.
ADCS
Conversion
channels
Channel 1
Channel 2
Channel 3
Channel 4
Interrupt signal
(INTAD)
An interrupt is generated
when conversion on one
of the channels ends.
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(2) If no interrupt is generated after A/D conversion ends
If the A/D conversion result value is outside the range of values specified by the A/D conversion result comparison
function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request
signal (INTAD) is not generated.
While in the select mode
If the A/D conversion end interrupt request signal (INTAD) is not generated after A/D conversion ends, the clock
request signal (an internal signal) is automatically set to the low level, and supplying the high-speed on-chip
oscillator clock stops. If a hardware trigger is input later, A/D conversion work is again performed in the SNOOZE
mode.
While in the scan mode
If the A/D conversion end interrupt request signal (INTAD) is not generated even once during A/D conversion of the
four channels, the clock request signal (an internal signal) is automatically set to the low level after A/D conversion
of the four channels ends, and supplying the high-speed on-chip oscillator clock stops. If a hardware trigger is input
later, A/D conversion work is again performed in the SNOOZE mode.
Figure 11-37. Operation Example When No Interrupt Is Generated After A/D Conversion Ends (While in Scan
Mode)
ADTRG
Clock request signal
(internal signal)
The clock request signal
is set to the low level.
ADCS
Conversion
channels
Channel 1
Channel 2
Channel 3
Channel 4
Interrupt signal
(INTAD)
No interrupt is generated when
conversion ends for any channel.
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11.9 How to Read A/D Converter Characteristics Table
Here, special terms unique to the A/D converter are explained.
(1) Resolution
This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage
per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is
expressed by %FSR (Full Scale Range).
1LSB is as follows when the resolution is 10 bits.
10
1LSB = 1/2
= 1/1024
= 0.098%FSR
Accuracy has no relation to resolution, but is determined by overall error.
(2) Overall error
This shows the maximum error value between the actual measured value and the theoretical value.
Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these
express the overall error.
Note that the quantization error is not included in the overall error in the characteristics table.
(3) Quantization error
When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an analog
input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot be avoided.
Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity
error, and differential linearity error in the characteristics table.
Figure 11-38. Overall Error
Figure 11-39. Quantization Error
1......1
1......1
Overall
error
Digital output
Digital output
Ideal line
1/2LSB
Quantization error
1/2LSB
0......0
AVREF
0
Analog input
0......0
0
Analog input
AVREF
(4) Zero-scale error
This shows the difference between the actual measurement value of the analog input voltage and the theoretical
value (1/2LSB) when the digital output changes from 0......000 to 0......001.
If the actual measurement value is greater than the theoretical value, it shows the difference between the actual
measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes
from 0……001 to 0……010.
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(5) Full-scale error
This shows the difference between the actual measurement value of the analog input voltage and the theoretical
value (Full-scale 3/2LSB) when the digital output changes from 1......110 to 1......111.
(6) Integral linearity error
This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses
the maximum value of the difference between the actual measurement value and the ideal straight line when the zeroscale error and full-scale error are 0.
(7) Differential linearity error
While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and
the ideal value.
Figure 11-40. Zero-Scale Error
Figure 11-41. Full-Scale Error
Full-scale error
Ideal line
011
010
001
Zero-scale error
Digital output (Lower 3 bits)
Digital output (Lower 3 bits)
111
000
111
110
101
Ideal line
000
0
1
2
3
AVREF
AVREF−3
0
Analog input (LSB)
AVREF−2
AVREF−1
AVREF
Analog input (LSB)
Figure 11-42. Integral Linearity Error
Figure 11-43. Differential Linearity Error
1......1
1......1
Ideal 1LSB width
Digital output
Digital output
Ideal line
Integral linearity
error
0......0
0
Analog input
Differential
linearity error
0......0
0
AVREF
Analog input
AVREF
(8) Conversion time
This expresses the time from the start of sampling to when the digital output is obtained.
The sampling time is included in the conversion time in the characteristics table.
(9) Sampling time
This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit.
Sampling
time
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11.10 Cautions for A/D Converter
(1) Operating current in STOP mode
Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of A/D converter mode register 0
(ADM0) to 0). The operating current can be reduced by setting bit 0 (ADCE) of the ADM0 register to 0 at the same
time.
To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1H (IF1H) to 0 and start
operation.
(2) Input range of ANI0 to ANI10 pins
Observe the rated range of the ANI0 to ANI8 pins input voltage. If a voltage of VDD and AVREFP or higher and VSS and
AVREFM or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted
value of that channel becomes undefined. In addition, the converted values of the other channels may also be
affected.
If the internal reference voltage (1.45 V) is selected as the reference voltage on the plus side of the A/D converter, do
not apply the voltage of 1.45 V or more to the pin selected by the ADS register. To the other pins, there are no
problems if the applied voltage is 1.45 V or more.
Note The internal reference voltage (1.45 V) can only be selected in HS (high-speed main) mode.
(3) Conflicting operations
Conflict between the A/D conversion result register (ADCR, ADCRH) write and the ADCR or ADCRH register
read by instruction upon the end of conversion
The ADCR or ADCRH register read has priority. After the read operation, the new conversion result is written to
the ADCR or ADCRH registers.
Conflict between the ADCR or ADCRH register write and the A/D converter mode register 0 (ADM0) write, the
analog input channel specification register (ADS), or A/D port configuration register (ADPC) write upon the end
of conversion
The ADM0, ADS, or ADPC registers write has priority. The ADCR or ADCRH register write is not performed,
nor is the conversion end interrupt signal (INTAD) generated.
(4) Noise countermeasures
To maintain the 10-bit resolution, attention must be paid to noise input to the AVREFP, VDD, ANI0 to ANI8 pins.
Connect a capacitor with a low equivalent resistance and a good frequency response to the power supply.
The higher the output impedance of the analog input source, the greater the influence. To reduce the noise,
connecting external C as shown in Figure 11-44 is recommended.
Do not switch these pins with other pins during conversion.
The accuracy is improved if the HALT mode is set immediately after the start of conversion.
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Figure 11-44. Analog Input Pin Connection
If there is a possibility that noise equal to or higher than AVREFP and
VDD or equal to or lower than AVREFM and VSS may enter, clamp with
a diode with a small VF value (0.3 V or lower).
Reference
voltage
input
AVREFP or VDD
ANI0 to ANI8
C = 100 to 1,000 pF
(5) Analog input (ANIn) pins
The analog input pins (ANI0 to ANI8) are also used as input port pins (P20 to P27, P150).
When A/D conversion is performed with any of the ANI0 to ANI8 pins selected, do not change the output value
to P20 to P27 and P150 while conversion is in progress; otherwise the conversion accuracy may be degraded.
If the pins adjacent to the pins currently used for A/D conversion is used as digital I/O ports, the expected value
of the A/D conversion may not be obtained due to coupling noise. Take care not to input or output such a pulse
to these pins.
(6) Input impedance of analog input (ANIn) pins
This A/D converter charges a sampling capacitor for sampling during sampling time.
Therefore, only a leakage current flows when sampling is not in progress, and a current that charges the capacitor
flows during sampling. Consequently, the input impedance fluctuates depending on whether sampling is in progress,
and on the other states.
To make sure that sampling is effective, however, it is recommended to keep the output impedance of the analog
input source to within 1 k, and to connect a capacitor of about 100 pF to the ANI0 to ANI8 pins (see Figure 11-44).
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(7) Interrupt request flag (ADIF)
The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is
changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF flag for the
pre-change analog input may be set just before the ADS register rewrite. Caution is therefore required since, at this
time, when ADIF flag is read immediately after the ADS register rewrite, ADIF flag is set despite the fact A/D
conversion for the post-change analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF flag before the A/D conversion operation is resumed.
Figure 11-45. Timing of A/D Conversion End Interrupt Request Generation
ADS rewrite
(start of ANIn conversion)
A/D conversion
ADCR
ANIn
ADS rewrite
(start of ANIm conversion)
ANIn
ANIn
ADIF is set but ANIm conversion
has not ended.
ANIm
ANIn
ANIm
ANIm
ANIm
ADIF
(8) Conversion results just after A/D conversion start
While in the software trigger mode or hardware trigger no-wait mode, the first A/D conversion value immediately after
A/D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 1 s after the ADCE bit was
set to 1. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first
conversion result.
(9) A/D conversion result register (ADCR, ADCRH) read operation
When a write operation is performed to A/D converter mode register 0 (ADM0), analog input channel specification
register (ADS), A/D port configuration register (ADPC), the contents of the ADCR and ADCRH registers may become
undefined. Read the conversion result following conversion completion before writing to the ADM0, ADS, or ADPC
register. Using a timing other than the above may cause an incorrect conversion result to be read.
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(10) Internal equivalent circuit
The equivalent circuit of the analog input block is shown below.
Figure 11-46. Internal Equivalent Circuit of ANIn Pin
R1
ANIn
C1
C2
Table 11-6. Resistance and Capacitance Values of Equivalent Circuit (Reference Values)
AVREFP, VDD
ANIn pin
R1 [kΩ]
C1 [pF]
C2 [pF]
4.0 VDD 5.5
ANI0 to ANI7
14
8
2.5
ANI8
18
8
7.0
ANI0 to ANI7
39
8
2.5
ANI8
53
8
7.0
ANI0 to ANI7
231
8
2.5
ANI8
321
8
7.0
2.7 VDD 4.0
1.8 VDD 2.7
Remark The resistance and capacitance values shown in Table 11-6 are not guaranteed values.
(11) Starting the A/D converter
Start the A/D converter after the AVREFP and VDD voltages stabilize.
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CHAPTER 12 SERIAL ARRAY UNIT
Serial array unit 0 has two serial channels, serial array unit 1 has two serial channels. Serial array unit 0 channel can
achieve 3-wire serial (CSI) , and UART. Serial array unit 1 channel can achieve 3-wire serial (CSI), and simplified I2C
communication.
Function assignment of each channel supported by the RL78/D1A is as shown below.
48, 64, 80-pin products
0
1
2
Used as CSI
Used as UART
Used as Simplified I C
0
CSI00
1
CSI01
0
1
IIC11
Used as CSI
Used as UART
Used as Simplified I C
Unit
Channel
100 products
Unit
0
1
Channel
0
CSI00
1
CSI01
0
CSI10
1
IIC11
Used as CSI
Used as UART
Used as Simplified I C
0
CSI00
UART0
1
CSI01
0
CSI10
1
IIC11
128-pin products
Unit
0
1
2
Channel
2
When “UART0” is used for channels 0 and 1 of the unit 0, CSI00 and CSI01 cannot be used, but CSI10, or IIC11 can
be used.
Caution Most of the following descriptions in this chapter use the units and channels of the 128-pin products
as an example.
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12.1 Functions of Serial Array Unit
Each serial interface supported by the RL78/D1A has the following features.
12.1.1 3-wire serial I/O (CSI00, CSI01, CSI10)
Data is transmitted or received in synchronization with the serial clock (SCK) output from the master channel.
3-wire serial communication is clocked communication performed by using three communication lines: one for the serial
clock (SCK), one for transmitting serial data (SO), one for receiving serial data (SI).
For details about the settings, see 12.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10) Communication.
[Data transmission/reception]
Data length of 7 to 16 bits
Phase control of transmit/receive data
MSB/LSB first selectable
Level setting of transmit/receive data
[Clock control]
Master/slave selection
Phase control of I/O clock
Setting of transfer period by prescaler and internal counter of each channel
[Interrupt function]
Transfer end interrupt/buffer empty interrupt
[Error detection flag]
Overrun error
12.1.2 UART (UART0)
This is an asynchronous communication function using two lines: serial data transmission (TXD) and serial data
reception (RXD) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity
bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other
communication party. Full-duplex UART communication can be performed by using a channel dedicated to transmission
(even-numbered channel) and a channel dedicated to reception (odd-numbered channel).
For details about the settings, see 12.6 Operation of UART (UART0) Communication.
[Data transmission/reception]
Data length of 7, 8, 9 or 16 bits (UART0)
Select the MSB/LSB first
Level setting of transmit/receive data and select of reverse
Parity bit appending and parity check functions
Stop bit appending
[Interrupt function]
Transfer end interrupt/buffer empty interrupt/reception interrupt
[Error detection flag]
Framing error, parity error, or overrun error
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12.1.3 Simplified I2C (IIC11)
This is a clocked communication function to communicate with two or more devices by using two lines: serial clock
(SCL) and serial data (SDA). This simplified I2C is designed for single communication with a device such as EEPROM,
flash memory, or A/D converter, and therefore, it functions only as a master.
Make sure by using software, as well as operating the control registers, that the AC specifications of the start and stop
conditions are observed.
For details about the settings, see 12.6 Operation of Simplified I2C (IIC11) Communication.
[Data transmission/reception]
Master transmission, master reception (only master function with a single master)
ACK output function Note and ACK detection function
Data length of 8 bits (When an address is transmitted, the address is specified by the higher 7 bits, and the least
significant bit is used for R/W control.)
Manual generation of start condition and stop condition
[Interrupt function]
Transfer end interrupt
[Error detection flag]
Overrun error
Parity error (ACK error)
* [Functions not supported by simplified I2C]
Slave transmission, slave reception
Arbitration loss detection function
Wait detection functions
Note When receiving the last data, ACK will not be output if 0 is written to the SOEm.n bit (serial output enable
register m (SOEm)) and serial communication data output is stopped. See the processing flow in 12.6.3 (2) for
details.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
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12.2 Configuration of Serial Array Unit
The serial array unit includes the following hardware.
Table 12-1. Configuration of Serial Array Unit
Item
Configuration
Shift register
16 bits
Buffer register
Serial data register mn (SDRmn)
Serial clock I/O
SCK00, SCK01, SCK10 pins (for 3-wire serial I/O), SCL11 pins (for simplified I C)
Serial data input
SI00, SI01, SI10 pins (for 3-wire serial I/O) , RXD0 pin (for UART)
Serial data output
SO00, SO01, SO10 pins (for 3-wire serial I/O) , TXD0 pin (for UART)
Serial data I/O
SDA11 pins (for simplified I C)
Control registers
Note
2
2
Peripheral enable registers 0 (PER0)
Serial clock select register m (SPSm)
Serial channel enable status register m (SEm)
Serial channel start register m (SSm)
Serial channel stop register m (STm)
Serial output enable register m (SOEm)
Serial output register m (SOm)
Serial output level register m (SOLm)
Serial data register mn (SDRmn)
Serial mode register mn (SMRmn)
Serial communication operation setting register mn (SCRmn)
Serial status register mn (SSRmn)
Serial flag clear trigger register mn (SIRmn)
Serial communication pin select register (STSEL)
Port input mode registers 0, 1, 3, 5 to 7, 13 (PIM0, PIM1, PIM3, PIM5 to PIM7, PIM13)
Port output mode register (POM)
Port mode registers 0, 1, 3, 5 to 7, 13 (PM0, PM1, PM3, PM5 to PM7, PM13)
Port registers 0, 1, 3, 5 to 7, 13 (P0, P1, P3, P5 to P7, P13)
Note. During operation (SEmn = 1)
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1),
p: CSI number (p = 00, 01, 10), q: UART number (q = 0), r: IIC number (r = 11)
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Figure 12-1 shows the block diagram of the serial array unit 0.
Figure 12-1. Block Diagram of Serial Array Unit 0
Serial output register 0(SO0)
0
Peripheral enable
register 0 (PER0)
SAU0EN
0
0
0
0
0
CKO01 CKO00
0
0
0
0
Serial clock select register 2 (SPS2)
PRS
013
PRS
012
PRS
011
PRS
010
PRS
003
PRS
002
4
PRS
001
0
0
SO0.1
SO0.0
0
0
SE0.1
SE0.0
Serial channel enable
status register 0 (SE0)
0
0
SS0.1
SS0.0
erial channel start
register 0 (SS0)
0
0
ST0.1
ST0.0
Serial channel stop
register 0 (ST0)
0
0
SOE0.1
SOE0.0
Serial output enable
register 0 (SOE0)
0
0
SOL0.1 SOL0.0
PRS
000
4
fCLK
Prescaler
fCLK/20 - fCLK/211
fCLK/20 - fCLK/211
INTTM23
Serial output level
register 0 (SOL0)
Selector
Selector
Serial data register 00 (SDR00)
CK01
Note 1
Selector
CK00
Serial clock I/O pin
(when CSI00: SCK00)
Selector
fSCK
Edge
detection
Note 2
Serial pin selection
(see Figure 12-2)
fMCK
Clock controller
Channel 0
fTCLK
Shift register
Serial pin selection
(see Figure 12-2)
Output
controller
Interrupt
controller
Communication controller
Note 2
CKS
00
CCS
002
STS
000
MD
002
MD
001
Serial mode register 00 (SMR00)
When UART0
PECT
00
OVCT
00
Clear
Communication
status
Serial data input pin
(when CSI00: SI00)
(when UART0: RxD0)
Serial transfer end interrupt
(when CSI00: INTCSI00)
(when UART0: INTST0)
Serial flag clear trigger
register 00 (SIR00)
Mode selection
CSI00 or UART0
(for transmission)
Edge/level
detection
Serial data output pin
(when CSI00: SO00)
(when UART0: TxD0)
Error controller
Error
information
TXE
S0
RXE
S0
DAP
S0
CKP
S0
0
0
0
DIR
00
0
0
DLS
002
DLS
001
DLS
000
TSF
00
Serial clock I/O pin
(when CSI01: SCK01)
Serial data input pin
(when CSI01: SI01)
Notes 1.
PEF
00
OVF
00
Serial status register 00 (SSR00)
Serial communication operation setting register 00 (SCR00)
CK01
BFF
00
CK00
Channel 1
Serial data output pin
(when CSI01: SO01)
Communication controller
Selector
Edge/level
detection
Mode selection
CSI01
or UART0
(for reception)
Serial transfer end interrupt
(when CSI01: INTCSI01)
(when UART0: INTSR0)
Error controller
When operation is stopped (SEmn = 0), the higher 7 bits become the clock division setting section and the
lower bits are fixed to 0.
During operation (SEmn = 1), it becomes a buffer register.
2.
Serial pin selection (see Figure 12-2)
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Figure 12-2. Port Configuration Diagram of Serial Array Unit 0
STSEL0
STSEL0
(SCSI010)
(SCSI001,000)
Serial array unit0
LTxD1
P10/SCK00
P10/SCK00
P04/SCK00
P10
Selector
P34/SCK00
Selector
P04/SCK00
P04
P11/SI00/RxD0
P03/SI00/RxD0
PM10
PM04
Selector
P34/SCK00
Channel0
P33/SI00/RxD0
P34
PM34
P12/SO00/TxD0
P12
Enable
PM12
Selector
P02/SO00/TxD0
P02
Enable
PM02
P32/SO00/TxD0
P32
Enable
PM32
P74/SCK01
Selector
P74/SCK01
Selector
P56/SCK01
P74
PM74
P56/SCK01
P75/SI01
Selector
Channel1
P56
P55/SI01
PM56
P13/SO01
Selector
P13
Enable
PM13
P54/SO01
P54
Enable
PM54
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Figure 12-3 shows the block diagram of the serial array unit 1.
Figure 12-3. Block Diagram of Serial Array Unit 1
Serial output register 1 (SO1)
0
Peripheral enable
register 0 (PER0)
0
0
0
0
0
CKO11 CKO10
0
0
0
0
Serial clock select register 1 (SPS1)
PRS
113
SAU1EN
PRS
112
PRS
111
PRS
110
PRS
103
PRS
102
4
PRS
101
0
0
SO11
SO10
0
0
SE11
SE10
Serial channel enable
status register 1 (SE1)
0
0
SS11
SS10
Serial channel start
register 1 (SS1)
0
0
ST11
ST10
Serial channel stop
register 1 (ST1)
0
0
SOE11 SOE10
Serial output enable
register 1 (SOE1)
0
0
SOL11 SOL10
Serial output level
register 1 (SOL1)
PRS
100
4
fCLK
Prescaler
fCLK/20 - fCLK/211
fCLK/20 - fCLK/211
INTTM23
Selector
Selector
Serial data register 10 (SDR10)
CK11
Selector
fSCK
Edge
detection
Serial clock I/O pin
(SCK10)
Serial data output pin
(SO10)
fTCLK
Shift register
Output
controller
Interrupt
controller
Communication controller
Output latch
(P133/P51)
PM133/PM51
FECT
10
CCS
102
Communication
status
CKS
10
STS
100
Serial transfer end interrupt
(INTCSI10)
Serial flag clear trigger
register 10 (SIR10)
CSI10
Edge/level
detection
Serial data input pin
(SI10)
PM131/PM53
fMCK
Selector
Output latch
(P131/P53)
Note
CK10
Clock controller
Channel 0
PECT
10
OVCT
10
Clear
Error controller
Serial mode register 10 (SMR10)
Error
information
TXE
10
RXE
10
DAP
10
CKP
10
0
PTC
101
PTC
100
DIR
10
SLC
101
SLC
100
DLS
102
DLS
101
Serial communication operation setting register 10 (SCR10)
CK11
Serial clock I/O pin
(SCL11)
DLS
100
TSF
10
CK10
Channel 1
Notes 1.
Selector
FEF
10
PEF
10
OVF
10
Serial status register 10 (SSR10)
Serial data output pin
(SDA11)
Communication controller
Mode selection
IIC11
Serial data input pin
(SDA11)
BFF
10
Edge/level
detection
Serial transfer end interrupt
(INTIIC11)
When operation is stopped (SEmn = 0), the higher 7 bits become the clock division setting section and the
lower bits are fixed to 0.
During operation (SEmn = 1), it becomes a buffer register.
2.
Serial pin selection (see Figure 12-2)
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Figure 12-4. Port Configuration Diagram of Serial Array Unit 1
STSEL0
STSEL1
(SIIC1, SIIC0)
(SCSI100)
Serial array unit1
P133/SCK10
P133/SCK10
P51/SCK10
P133
Selector
PM133
Selector
P51/SCK10
P51
P132/SI10
P52/SI10
PM51
Selector
Channel0
LTxD1
P131/SO10
P131
PM131
Selector
P53/SO10
P53
PM53
P61/SDA11
P61/SDA11
P31/SDA11
P50/SDA11
P61
PM61
Selector
P31/SDA11
Selector
P31
PM31
P50/SDA11
P50
Channel1
PM50
P60/SCL11
Selector
P60
PM60
P30/SCL11
P30
PM30
P136/SCL11
P136
PM136
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(1) Shift register
This is an 16-bit register that converts parallel data into serial data or vice versa.
During reception, it converts data input to the serial pin into parallel data.
When data is transmitted, the value set to this register is output as serial data from the serial output pin.
The shift register cannot be directly manipulated by program.
To read or write the shift register, serial data register mn (SDRmn) is used during operation (SEmn = 1).
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Shift register
(2) Serial data register mn (SDRmn)
SDRmn is the transmit/receive data register (16 bits) of channel n. When operation is stopped (SEm.n = 0), bits 15
to 9 are used as the division setting register of the operating clock (fMCK). During operation (SEm.n = 1), bits 15 to
9 are used as a transmission/reception buffer register.
When data is received, parallel data converted by the shift register is stored. When data is to be transmitted, set
transmit to be transferred to the shift register.
The data stored in this register is as follows, depending on the setting of bits 4 to 0 (DLSmn4 to DLSmn0) of the
SCRmn register, regardless of the output sequence of the data.
7-bit data length (stored in bits 0 to 6 of SDRmn register)
8-bit data length (stored in bits 0 to 7 of SDRmn register)
:
16-bit data length (stored in bits 0 to15 of SDRmn register)
SDRmn can be read or written in 16-bit units.
When SEm.n = 1, the lower 8 bits of SDRmn can be read or writtenNote in 8-bit units as SDRmnL. The SDRmnL
registers that can be used according to the communication methods are shown below.
CSIp communication … SIOpL
UARTq reception … RxDq (UARTq receive data register)
UARTq transmission … TxDq (UARTq transmit data register)
IICr communication … SDRrL (IICr data register)
Reset signal generation clears this register to 0000H.
Note
Writing in 8-bit units is prohibited when the operation is stopped (SEm.n = 0).
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1),
p: CSI number (p = 00, 01, 10), q: UART number (q = 0 to 2), r: IIC number (r = 11)
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Figure 12-5. Format of Serial Data Register mn (SDRmn)
Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01),
After reset: 0000H
R/W
FFF14H, FFF15H (SDR10), FFF16H, FFF17H (SDR11)
FFF10H (SDR00)
FFF11H (SDR00)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SDRmn
Shift
register
Remarks 1. For the function of the higher 7 bits of SDRmn, see 12.3 Registers Controlling Serial Array Unit.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1),
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12.3 Registers Controlling Serial Array Unit
Serial array unit is controlled by the following registers.
Peripheral enable register 0 (PER0)
Serial clock select register m (SPSm)
Serial mode register mn (SMRmn)
Serial communication operation setting register mn (SCRmn)
Serial data register mn (SDRmn)
Serial flag clear trigger register mn (SIRmn)
Serial status register mn (SSRmn)
Serial channel start register m (SSm)
Serial channel stop register m (STm)
Serial channel enable status register m (SEm)
Serial output enable register m (SOEm)
Serial output level register m (SOLm)
Serial output register m (SOm)
Serial communication pin select register (STSEL)
Port input mode registers 0, 1, 3, 5 to 7, 13 (PIM0, PIM1, PIM3, PIM5 to PIM7, PIM13)
Port output mode register (POM)
Port mode registers 0, 1, 3, 5 to 7, 13 (PM0, PM1, PM3, PM5 to PM7, PM13)
Port registers 0, 1, 3, 5 to 7, 13 (P0, P1, P3, P5 to P7, P13)
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
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(1) Peripheral enable registers 0 (PER0)
PER0 are used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware
macro that is not used is stopped in order to reduce the power consumption and noise.
When serial array unit 0 is used, be sure to set bit 3 (SAU0EN) of PER0.
When serial array unit 1 is used, be sure to set bit 4 (SAU1EN) of PER0.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 12-6. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H
After reset: 00H
R/W
Symbol
PER0
RTCEN
LIN1EN
LIN0EN
SAU1EN
SAU0EN
TAU2EN
TAU1EN
TAU0EN
SAUmEN
0
Control of serial array unit m input clock supply (m = 0, 1)
Stops supply of input clock.
SFR used by serial array unit m cannot be written.
Serial array unit m is in the reset status.
1
Enables input clock supply.
SFR used by serial array unit m can be read/written.
Cautions 1. When setting serial array unit m, be sure to set the SAUmEN bit to 1 first. If SAUmEN = 0,
writing to a control register of serial array unit m is ignored, and, even if the register is read,
only the default value is read (except for Serial communication pin select register (STSEL),
port input mode register (PIM0, PIM1, PIM3, PIM5 to PIM7, PIM13), port output mode register
(POM), port mode registers (PM0, PM1, PM3, PM5 to PM7, PM13), and port registers (P0, P1,
P3, P5 to P7, P13)).
2. After setting the SAUmEN bit to 1, be sure to set serial clock select register m (SPSm) after 4
or more fCLK clocks have elapsed.
Remark m: Unit number (m = 0 to 1)
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(2) Serial clock select register m (SPSm)
The SPSm register is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are
commonly supplied to each channel. CKm1 is selected by bits 7 to 4 of the SPSm register, and CKm0 is selected
by bits 3 to 0.
Rewriting the SPSm register is prohibited when the register is in operation (when SEm.n = 1).
The SPSm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SPSm register can be set with an 8-bit memory manipulation instruction with SPSmL.
Reset signal generation clears the SPSm register to 0000H.
Figure 12-7. Format of Serial Clock Select Register m (SPSm)
Address: F0116H, F0117H (SPS0), F0146H, F0147H (SPS1)
Symbol
15
14
13
12
11
10
9
8
SPSm
0
0
0
0
0
0
0
0
PRS
PRS
PRS
PRS
mp3
mp2
mp1
mp0
0
fCLK
0
0
0
1
fCLK/2
0
0
0
0
1
1
1
0
0
0
1
0
1
4
3
2
1
0
Note
0
1
R/W
5
Section of operation clock (CKmp)
0
0
6
PRSm13 PRSm12 PRSm11 PRSm10 PRSm03 PRSm02 PRSm01 PRSm00
0
0
After reset: 0000H
7
fCLK =
fCLK =
fCLK =
fCLK =
fCLK =
4 MHz
8 MHz
16 MHz
24 MHz
32 MHz
4 MHz
8 MHz
16 MHz
24 MHz
32 MHz
2 MHz
4 MHz
8 MHz
12 MHz
16 MHz
fCLK/2
2
1 MHz
2 MHz
4 MHz
6 MHz
8 MHz
fCLK/2
3
500 kHz
1 MHz
2 MHz
3 MHz
4 MHz
fCLK/2
4
250 kHz
500 kHz
1 MHz
1.5 MHz
2 MHz
fCLK/2
5
125 kHz
250 kHz
500 kHz
750 kHz
1 MHz
0
1
1
0
fCLK/2
6
62.5 kHz
125 kHz
250 kHz
375 kHz
500 kHz
0
1
1
1
fCLK/2
7
31.3 kHz
62.5 kHz
125 kHz
187.5 kHz
250 kHz
fCLK/2
8
15.6 kHz
31.3 kHz
62.5 kHz
93.75 kHz
125 kHz
fCLK/2
9
7.81 kHz
15.6 kHz
31.3 kHz
46.88 kHz
62.5 kHz
fCLK/2
10
3.91 kHz
7.81 kHz
15.6 kHz
23.44 kHz
31.3 kHz
11
1.95 kHz
3.91 kHz
7.81 kHz
11.72 kHz
15.6 kHz
1
1
1
0
0
0
0
0
1
0
1
0
1
0
1
1
fCLK/2
1
1
1
1
INTTM23
Other than the above
Setting prohibited
Note When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), do
so after having stopped (STm = 0003H) the operation of the serial array unit m (SAUm).
Cautions 1. Be sure to clear bits 15 to 8 to “0”.
2. After setting bit 3 (SAU0EN) and bit 4 (SAU1EN) of the PER0 register to 1, be sure to set serial
clock select register m (SPSm) after 4 or more fCLK clocks have elapsed.
Remarks 1. fCLK: CPU/peripheral hardware clock frequency
2. m: Unit number (m = 0, 1), p = 0, 1
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(3) Serial mode register mn (SMRmn)
The SMRmn register is a register that sets an operation mode of channel n. It is also used to select an operation
clock (fMCK), specify whether the serial clock (fSCK) may be input or not, set a start trigger, an operation mode (CSI,
UART, or I2C), and an interrupt source.
Rewriting the SMRmn register is prohibited when the register is in operation (when SEm.n = 1). However, the
MDmn0 bit can be rewritten during operation.
The SMRmn register can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets the SMRmn register to 0020H.
Figure 12-8. Format of Serial Mode Register mn (SMRmn) (1/2)
Address: F0108H, F0109H (SMR00), F010AH, F010BH (SMR01),
After reset: 0020H
R/W
F0138H, F0139H (SMR10), F013AH, F013BH (SMR11)
Symbol
15
14
13
12
11
10
9
8
7
SMRmn
CKS
CCS
0
0
0
0
0
STS
0
mn
mn
CKSm
6
5
4
3
SIS
1
0
0
mn
mn0
Note
Note
2
1
0
MD
MD
MD
mn2
mn1
mn0
Selection of operation clock (fMCK) of channel n
n
0
Operation clock CKm0 set by the SPSm register
1
Operation clock CKm1 set by the SPSm register
Operation clock (fMCK) is used by the edge detector. In addition, depending on the setting of the CCSmn bit and the
higher 7 bits of the SDRmn register, a transfer clock (fTCLK) is generated.
CCSm
Selection of transfer clock (fTCLK) of channel n
n
0
Divided operation clock fMCK specified by the CKSmn bit
1
Clock input fSCK from the SCKp pin (slave transfer in CSI mode)
Transfer clock fTCLK is used for the shift register, communication controller, output controller, interrupt controller, and
error controller. When CCSmn = 0, the division ratio of operation clock (fMCK) is set by the higher 7 bits of the
SDRmn register.
STS
Selection of start trigger source
Note
mn
2
0
Only software trigger is valid (selected for CSI, UART transmission, and simplified I C).
1
Valid edge of the RXDq pin (selected for UART reception)
Transfer is started when the above source is satisfied after 1 is set to the SSm register.
Note The SMR01 register only.
Caution
Be sure to clear bits 13 to 9, 7, 6, 4, and 3 to “0”. Be sure to set bit 5 to “1”.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
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Figure 12-8. Format of Serial Mode Register mn (SMRmn) (2/2)
Address: F0108H, F0109H (SMR00), F010AH, F010BH (SMR01),
After reset: 0020H
R/W
F0138H, F0139H (SMR10), F013AH, F013BH (SMR11)
Symbol
15
14
13
12
11
10
9
8
7
SMRmn
CKS
CCS
0
0
0
0
0
STS
0
mn
mn
mn
6
5
4
3
SIS
1
0
0
mn0
2
1
0
MD
MD
MD
mn2
mn1
mn0
Note1
SIS
mn0
Controls inversion of level of receive data of channel n in UART mode
Note1
0
Falling edge is detected as the start bit.
The input communication data is captured as is.
1
Rising edge is detected as the start bit.
The input communication data is inverted and captured.
MD
MD
mn2
mn1
0
0
CSI mode
0
1
UART mode
1
0
Simplified I C mode
1
1
Setting prohibited
Setting of operation mode of channel n
Note
Note2
2
MD
Selection of interrupt source of channel n
mn0
0
Transfer end interrupt
1
Buffer empty interrupt
(Occurs when data is transferred from the SDRmn register to the shift register.)
For successive transmission, the next transmit data is written by setting MDmn0 to 1 when SDRmn data has run
out.
Notes 1. The SMR01 register only.
2. The SMR00 and SMR01 registers.
Remarks 1. See Table 12-1 Serial Function Assignment of Each Product for details of the modes implemented for
each unit and product.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
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(4) Serial communication operation setting register mn (SCRmn)
The SCRmn register is a communication operation setting register of channel n. It is used to set a data
transmission/reception mode, phase of data and clock, whether an error signal is to be masked or not, parity bit,
start bit, stop bit, and data length.
Rewriting the SCRmn register is prohibited when the register is in operation (when SEm.n = 1).
The SCRmn register can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets the SCRmn register to 0087H.
Figure 12-9. Format of Serial Communication Operation Setting Register mn (SCRmn) (1/3)
Address: F010CH, F010DH (SCR00), F010EH, F010FH (SCR01),
After reset: 0087H
R/W
F013CH, F013DH (SCR10), F013EH, F013FH (SCR11)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SCRmn
TXE
RXE
DAP
CKP
0
0
PTC
PTC
DIR
0
SLC
SLC
DLS
DLS
DLS
DLS
mn
mn
mn
mn
mn1
mn0
mn
mn1
mn0
mn3
mn2
mn1
mn0
Note 1
TXE
RXE
mn
mn
0
0
Disable communication.
0
1
Reception only
1
0
Transmission only
1
1
Transmission/reception
DAP
CKP
mn
mn
0
0
Note 2
Setting of operation mode of channel n
Selection of data and clock phase in CSI mode
Type
SCKp
SOp
1
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
SIp input timing
0
1
SCKp
SOp
2
SIp input timing
1
0
SCKp
SOp
3
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
SIp input timing
1
1
SCKp
SOp
4
SIp input timing
2
Be sure to set DAPmn, CKPmn = 0, 0 in the UART mode and simplified I C mode.
Notes 1. The SCR00 register only.
2. The SCR00 and SCR01 registers only. For other registers, the bit is fixed to 1.
Caution Be sure to clear bits 6, 10 and 11 of SCRmn to “0”.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01, 10, 11)
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Figure 12-9. Format of Serial Communication Operation Setting Register mn (SCRmn) (2/3)
Address: F010CH, F010DH (SCR00), F010EH, F010FH (SCR01),
After reset: 0087H R/W
F013CH, F013DH (SCR10), F013EH, F013FH (SCR11)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SCRmn
TXE
RXE
DAP
CKP
0
0
PTC
PTC
DIR
0
SLC
SLC
DLS
DLS
DLS
DLS
mn
mn
mn
mn
mn1
mn0
mn
mn1
mn0
mn3
mn2
mn1
mn0
Note 1
Note 2
PTC
PTC
mn1
mn0
0
0
Does not output the parity bit.
0
1
Outputs 0 parity
1
0
Outputs even parity.
Judged as even parity.
1
1
Outputs odd parity.
Judges as odd parity.
Setting of parity bit in UART mode
Transmission
Reception
Receives without parity
Note 3
No parity judgment
2
Be sure to set PTCmn1, PTCmn0 = 0, 0 in the CSI mode and simplified I C mode.
DIR
Selection of data transfer sequence in CSI and UART modes
mn
0
Inputs/outputs data with MSB first.
1
Inputs/outputs data with LSB first.
2
Be sure to clear DIRmn = 0 in the simplified I C mode.
SLC
SLC
mn1
mn0
Setting of stop bit in UART mode
Note 1
0
0
No stop bit
0
1
Stop bit length = 1 bit
1
0
Stop bit length = 2 bits (mn = 00 only)
1
1
Setting prohibited
When the transfer end interrupt is selected, the interrupt is generated when all stop bits have been completely
transferred.
2
Set 1 bit (SLCmn1, SLCmn0 = 0, 1) during UART reception and in the simplified I C mode.
Set no stop bit (SLCmn1, SLCmn0 = 0, 0) in the CSI mode.
Notes 1. The SCR00 register only.
2. The SCR00 and SCR01 registers only. For other registers, the bit is fixed to 1.
3. 0 is always added regardless of the data contents.
Caution
Be sure to clear bits 6, 10 and 11 to “0”.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01, 10)
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Figure 12-9. Format of Serial Communication Operation Setting Register mn (SCRmn) (3/3)
Address: F010CH, F010DH (SCR00), F010EH, F010FH (SCR01),
After reset: 0087H R/W
F013CH, F013DH (SCR10), F013EH, F013FH (SCR11)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SCRmn
TXE
RXE
DAP
CKP
0
0
PTC
PTC
DIR
0
SLC
SLC
DLS
DLS
DLS
DLS
mn
mn
mn
mn
mn1
mn0
mn
mn1
mn0
mn3
mn2
mn1
mn0
Note 1
DLS
DLS
DLS
DLS
mn3
mn2
mn1
mn0
Note 2
Setting of data length in CSI mode
Serial-function
correspondence
Note 2
CSI
UART
IIC
0
1
1
0
7-bit data length (stored in bits 0 to 6 of SDRmn register)
0
1
1
1
8-bit data length (stored in bits 0 to 7 of SDRmn register)
1
0
0
0
9-bit data length (stored in bits 0 to 8 of SDRmn register)
1
0
0
1
10-bit data length (stored in bits 0 to 9 of SDRmn register)
1
0
1
0
11-bit data length (stored in bits 0 to 10 of SDRmn register)
1
0
1
1
12-bit data length (stored in bits 0 to 11 of SDRmn register)
1
1
0
0
13-bit data length (stored in bits 0 to 12 of SDRmn register)
1
1
0
1
14-bit data length (stored in bits 0 to 13 of SDRmn register)
1
1
1
0
15-bit data length (stored in bits 0 to 14 of SDRmn register)
1
1
1
1
16-bit data length (stored in bits 0 to 15 of SDRmn register)
Other than the above
Setting prohibited
2
Be sure to set DLSmn3 to DLSmn0 = 0111B in the simplified I C mode.
Notes 1. The SCR00 register only.
2. The SCR00 and SCR01 registers only. For other registers, the bit is fixed to 1.
Caution
Be sure to clear bits 6 , 10 and 11 of SCRmn to “0”.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
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(5) Higher 7 bits of the serial data register mn (SDRmn)
SDRmn is the transmit/receive data register (16 bits) of channel n. When operation is stopped (SEm.n = 0), bits 15
to 9 are used as the division setting register of the operating clock (fMCK). During operation (SEm.n = 1), bits 15 to
9 are used as a transmission/reception buffer register.
If the CCSmn bit of serial mode register mn (SMRmn) is cleared to 0, the clock set by dividing the operating clock
by the higher 7 bits of SDRmn is used as the transfer clock.
See 12.2 Configuration of Serial Array Unit for the functions of SDRmn during operation (SEm.n = 1).
SDRmn can be read or written in 16-bit units.
Reset signal generation clears this register to 0000H.
Figure 12-10. Format of Serial Data Register mn (SDRmn)
Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01),
After reset: 0000H
R/W
FFF14H, FFF15H (SDR10), FFF16H, FFF17H (SDR11)
FFF10H (SDR00)
FFF11H (SDR00)
Symbol
15
14
13
12
11
10
9
SDRmn
SDRmn[15:9]
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
Setting of division ratio of operation clock (fMCK)
0
0
0
0
0
0
0
fMCK
0
0
0
0
0
0
1
fMCK/2
0
0
0
0
0
1
0
fMCK/3
0
0
0
0
0
1
1
fMCK/4
1
1
1
1
1
1
0
fMCK/127
1
1
1
1
1
1
1
fMCK/128
Cautions 1. When operation is stopped (SEm.n = 0), be sure to clear bits 8 to 0 to “0”.
2. Setting SDRmn[15:9] = (0000000B, 0000001B) is prohibited when UART is used.
3. Setting SDRmn[15:9] = 0000000B is prohibited when simplified I2C is used. Set SDRmn[15:9]
to 0000001B or greater.
4. Do not write eight bits to the lower eight bits if operation is stopped (SEm.n = 0). (If these bits
are written to, the higher seven bits are cleared to 0.)
Remarks 1. For the function of during operation (SEm.n = 1), see 12.2 Configuration of Serial Array Unit.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
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(6) Serial flag clear trigger register mn (SIRmn)
The SIRmn register is a trigger register that is used to clear each error flag of channel n.
When each bit (PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (PEFmn, OVFmn) of serial
status register mn is cleared to 0. Because the SIRmn register is a trigger register, it is cleared immediately when
the corresponding bit of the SSRmn register is cleared.
The SIRmn register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SIRmn register can be set with an 8-bit memory manipulation instruction with SIRmnL.
Reset signal generation clears the SIRmn register to 0000H.
Figure 12-11. Format of Serial Flag Clear Trigger Register mn (SIRmn)
Address: F0104H, F0105H (SIR00), F0106H, F0107H (SIR01),
After reset: 0000H
R/W
F0134H, F0135H (SIR10), F0136H, F0137H (SIR11)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SIRmn
0
0
0
0
0
0
0
0
0
0
0
0
0
FEC
PEC
OVC
Tmn
Tmn
Tmn
Note
FEC
Clear trigger of framing error of channel n
Tmn
0
Not cleared
1
Clears the FEFmn bit of the SSRmn register to 0.
PEC
Clear trigger of parity error of SCL11
T11
0
No trigger operation
1
Clears PEF11 bit of SSR11 register to 0.
OVC
Clear trigger of overrun error flag of channel n
Tmn
0
Not cleared
1
Clears the OVFmn bit of the SSRmn register to 0.
Cautions 1.
2.
Be sure to clear bits 15 to 2 of SIRmn to “0”.
Only the error flag set to the SSRn register is cleared by using the SIRmn register. When a
clear operation is performed for an error flag that is not set and when a new error is detected
between reading the error flag and the clear operation, the error flag may be erased.
Remarks 1.
2.
When the SIRmn register is read, 0000H is always read.
When writing “1” to a clear trigger and setting (1) the corresponding error flag occur simultaneously,
setting the error flag takes precedence.
3.
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
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(7) Serial status register mn (SSRmn)
The SSRmn register is a register that indicates the communication status and error occurrence status of channel n.
The errors indicated by this register are a framing error, parity error, and overrun error.
The SSRmn register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the SSRmn register can be set with an 8-bit memory manipulation instruction with SSRmnL.
Reset signal generation clears the SSRmn register to 0000H.
Figure 12-12. Format of Serial Status Register mn (SSRmn) (1/2)
Address: F0100H, F0101H (SSR00), F0102H, F0103H (SSR01),
After reset: 0000H
R
F0130H, F0131H (SSR10), F0132H, F0133H (SSR11)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SSRmn
0
0
0
0
0
0
0
0
0
TSF
BFF
0
0
FEF
PEF
OVF
mn
mn
mn
mn
mn
Note
TSF
Communication status indication flag of channel n
mn
0
Communication is stopped or suspended.
1
Communication is in progress.
The STm.n bit of the STm register is set to 1 (communication is stopped) or the SSm.n bit of the SSm register is
set to 1 (communication is suspended).
Communication ends.
Communication starts.
BFF
Buffer register status indication flag of channel n
mn
0
Valid data is not stored in the SDRmn register.
1
Valid data is stored in the SDRmn register.
Transferring transmit data from the SDRmn register to the shift register ends during transmission.
Reading receive data from the SDRmn register ends during reception.
The STm.n bit of the STm register is set to 1 (communication is stopped) or the SSm.n bit of the SSm register is
set to 1 (communication is enabled).
Transmit data is written to the SDRmn register while the TXEmn bit of the SCRmn register is set to 1
(transmission or transmission and reception mode in each communication mode).
Receive data is stored in the SDRmn register while the RXEmn bit of the SCRmn register is set to 1 (reception or
transmission and reception mode in each communication mode).
A reception error occurs.
Note The SSR01 register only.
Caution
If data is written to the SDRmn register when BFFmn = 1, the transmit/receive data stored in the
register is discarded and an overrun error (OVEmn = 1) is detected.
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Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
Figure 12-12. Format of Serial Status Register mn (SSRmn) (2/2)
Address: F0100H, F0101H (SSR00), F0102H, F0103H (SSR01),
After reset: 0000H
R
F0130H, F0131H (SSR10), F0132H, F0133H (SSR11)
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SSRmn
0
0
0
0
0
0
0
0
0
TSF
BFF
0
0
FEF
PEF
OVF
mn
mn
mn
mn
mn
Note
FEFm
n
Framing error detection flag of channel n
Note
0
No error occurs.
1
An error occurs (during UART reception).
1 is written to the FECTmn bit of the SIRmn register.
A stop bit is not detected when UART reception ends.
PEF
Parity error detection flag of channel 11
mn
0
No error occurs.
1
An error occurs (during UART reception) or ACK is not detected (during I C transmission).
2
1 is written to the PECTmn bit of the SIRmn register.
No ACK signal is returned from the slave channel at the ACK reception timing during I C transmission (ACK is
2
not detected).
OVF
Overrun error detection flag of channel n
mn
0
No error occurs.
1
An error occurs
1 is written to the OVCTmn bit of the SIRmn register.
Even though receive data is stored in the SDRmn register, that data is not read and transmit data or the next
receive data is written while the RXEmn bit of the SCRmn register is set to 1 (reception or transmission and
reception mode in each communication mode).
Transmit data is not ready for slave transmission or transmission and reception in CSI mode.
Note The SSR01 register only.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), PEF bit is SSR11 only
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(8) Serial channel start register m (SSm)
The SSm register is a trigger register that is used to enable starting communication/count by each channel.
When 1 is written a bit of this register (SSmn), the corresponding bit (SEm.n) of serial channel enable status
register m (SEm) is set to 1 (Operation is enabled). Because the SSm.n bit is a trigger bit, it is cleared immediately
when SEm.n = 1.
The SSm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SSm register can be set with an 1-bit or 8-bit memory manipulation instruction with SSmL.
Reset signal generation clears the SSm register to 0000H.
Figure 12-13. Format of Serial Channel Start Register m (SSm)
Address: F0112H, F0113H (SS0), F0142H, F0143H (SS1),
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSm
SSm
1
0
SSmn
Operation start trigger of channel n
0
No trigger operation
1
Sets the SEm.n bit to 1 and enters the communication wait status
Note
.
Note If the SSmn bit is set to 1 during communication, the communication stops and the communication wait state
is entered. At this time, the values of the control registers and shift register and the status of the SCKmn and
SOmn pins and the PEFmn, and OVFmn flags are held.
Caution
Be sure to clear bits 15 to 2 of SSm to “0”.
Remarks 1. When the SSm register is read, 0000H is always read.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
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(9) Serial channel stop register m (STm)
The STm register is a trigger register that is used to enable stopping communication/count by each channel.
When 1 is written a bit of this register (STm.n), the corresponding bit (SEm.n) of serial channel enable status
register m (SEm) is cleared to 0 (operation is stopped). Because the STm.n bit is a trigger bit, it is cleared
immediately when SEm.n = 0.
The STm register can set written by a 16-bit memory manipulation instruction.
The lower 8 bits of the STm register can be set with a 1-bit or 8-bit memory manipulation instruction with STmL.
Reset signal generation clears the STm register to 0000H.
Figure 12-14. Format of Serial Channel Stop Register m (STm)
Address: F0114H, F0115H (ST0), F0144H, F0145H (ST1),
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STm
0
0
0
0
0
0
0
0
0
0
0
0
0
0
STm
STm
1
0
STmn
Operation stop trigger of channel n
0
No trigger operation
1
Clears the SEm.n bit to 0 and stops the communication operation
Note
.
Note Communication stops while holding the value of the control register and shift register, and the status of the
serial clock I/O pin, serial data output pin, and each error flag (PEFmn: parity error flag, OVFmn: overrun
error flag).
Caution
Be sure to clear bits 15 to 2 of STm to “0”.
Remarks 1. When the STm register is read, 0000H is always read.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
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(10) Serial channel enable status register m (SEm)
The SEm register indicates whether data transmission/reception operation of each channel is enabled or stopped.
When 1 is written a bit of serial channel start register m (SSm), the corresponding bit of this register is set to 1.
When 1 is written a bit of serial channel stop register m (STm), the corresponding bit is cleared to 0.
Channel n that is enabled to operate cannot rewrite by software the value of the CKOmn bit (serial clock output of
channel n) of serial output register m (SOm) to be described below, and a value reflected by a communication
operation is output from the serial clock pin.
Channel n that stops operation can set the value of the CKOmn bit of the SOm register by software and output its
value from the serial clock pin. In this way, any waveform, such as that of a start condition/stop condition, can be
created by software.
The SEm register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the SEm register can be set with a 1-bit or 8-bit memory manipulation instruction with SEmL.
Reset signal generation clears the SEm register to 0000H.
Figure 12-15. Format of Serial Channel Enable Status Register m (SEm)
Address: F0110H, F0111H (SE0), F0140H, F0141H (SE1)
After reset: 0000H
R
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SEm
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SEm
SEm
1
0
SEmn
Indication of operation enable/stop status of channel n
0
Operation stops
1
Operation is enabled.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
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(11) Serial output enable register m (SOEm)
The SOEm register is a register that is used to enable or stop output of the serial communication operation of each
channel.
Channel n that enables serial output cannot rewrite by software the value of the SOm.n bit of serial output register
m (SOm) to be described below, and a value reflected by a communication operation is output from the serial data
output pin.
For channel n, whose serial output is stopped, the SOm.n bit value of the SOm register can be set by software,
and that value can be output from the serial data output pin. In this way, any waveform of the start condition and
stop condition can be created by software.
The SOEm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SOEm register can be set with a 1-bit or 8-bit memory manipulation instruction with SOEmL.
Reset signal generation clears the SOEm register to 0000H.
Figure 12-16. Format of Serial Output Enable Register m (SOEm)
Address: F011AH, F011BH (SOE0), F014AH, F014BH (SOE1),
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SOE
SOE
m1
m0
SOE
Serial output enable/stop of channel n
mn
0
Stops output by serial communication operation.
1
Enables output by serial communication operation.
Caution
Be sure to clear bits 15 to 2 of SOEm.
Remark
m: Unit number (m = 0, 1), n: Channel number (n =0, 1)
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(12) Serial output register m (SOm)
The SOm register is a buffer register for serial output of each channel.
The value of the SOm.n bit of this register is output from the serial data output pin of channel n.
The value of the CKOmn bit of this register is output from the serial clock output pin of channel n.
The SOm.n bit of this register can be rewritten by software only when serial output is disabled (SOEm.n = 0).
When serial output is enabled (SOEm.n = 1), rewriting by software is ignored, and the value of the register can be
changed only by a serial communication operation.
The CKOmn bit of this register can be rewritten by software only when the channel operation is stopped (SEm.n =
0). While channel operation is enabled (SEm.n = 1), rewriting by software is ignored, and the value of the CKOmn
bit can be changed only by a serial communication operation.
To use the serial interface pin as a port function pin, set the corresponding CKOmn and SOm.n bits to “1”.
The SOm register can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears the SOm register to 0F0FH.
Figure 12-17. Format of Serial Output Register m (SOm)
Address: F0118H, F0119H (SO0), F0148H, F0149H (SO1),
After reset: 0303H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOm
0
0
0
0
0
0
CKO
CKO
0
0
0
0
0
0
SO
SO
m1
m0
m1
m0
CKO
Serial clock output of channel n
mn
0
Serial clock output value is “0”.
1
Serial clock output value is “1”.
SO
Serial data output of channel n
m.n
0
Serial data output value is “0”.
1
Serial data output value is “1”.
Caution
Be sure to set bits 15 to 10, 7 to 2 of SOm to “0”.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
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(13) Serial output level register m (SOLm)
The SOLm register is a register that is used to set inversion of the data output level of each channel.
2
This register can be set only in the UART mode. Be sure to set 0000H in the CSI mode and simplifies I C mode.
Inverting channel n by using this register is reflected on pin output only when serial output is enabled (SOEm.n =
1). When serial output is disabled (SOEm.n = 0), the value of the SOm.n bit is output as is.
Rewriting the SOLm register is prohibited when the register is in operation (when SEm.n = 1).
The SOLm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SOLm register can be set with an 8-bit memory manipulation instruction with SOLmL.
Reset signal generation clears the SOLm register to 0000H.
Figure 12-18. Format of Serial Output Level Register m (SOLm)
Address: F0120H, F0121H (SOL0), F0150H, F0151H (SOL1),
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOLm
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SOL
m.0
SOL
Selects inversion of the level of the transmit data of channel n in UART mode
mn
0
Communication data is output as is.
1
Communication data is inverted and output.
Caution
Be sure to clear bits 15 to 1 to “0”.
Remark m: Unit number (m = 0, 1)
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(14) Serial communication pin select register 0, 1 (STSEL0, STSEL1)
These registers are used for alternate switch of serial input/output pins.
STSEL0 and STSEL1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 12-19. Serial communication pin select register 0 (STSEL0)
Address: FFF3CH
After reset: 00H
R/W (Note: Bits 5 and 7 are read only bit)
Symbol
7
6
5
4
3
2
1
0
STSEL0
0
SCSI100
0
SCSI010
SCSI001
SCSI000
SUARTF1
SUARTF0
SUARTF0
Communication pin selection of UARTF0
LTxD0
LRxD0
0
P71
P70
1
P15
P14
SUARTF1
Communication pin selection of UARTF1
LTxD1
LRxD1
0
P10
P11
1
P131
P132
STSCSI00
SCSI000
CSI00/UART0 communication pin selection
SCK00
SI00
SO00
0
0
P10
P11
P12
0
1
P04
P03
P02
1
0
P34
P33
P32
Other tan above
Setting prohibited (same as “00” setting)
SCSI010
CSI01 communication pin selection
SCK01
SI01
SO01
0
P74
P75
P13
1
P56
P55
P54
SCSI100
CSI10 communication pin selection
SCK10
SI10
SO10
0
P133
P132
P131
1
P51
P52
P53
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Figure 12-20. Serial communication pin select register 1 (STSEL1)
Address: FFF3D
After reset: 00H
R/W (Note: Bits 4, 5 are read only bit)
Symbol
7
6
5
4
3
2
1
0
STSEL1
SIIC1
SIIC0
0
0
SCAN1
SCAN0
TMCAN1
TMCAN0
SIIC1
SIIC0
Communication pin selection of IIC11
SCL11
SDA11
0
0
P60
P61
0
1
P30
P31
1
0
P136
P50
Other than the above
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CHAPTER 12 SERIAL ARRAY UNIT
(15) Port input mode registers 0, 1, 3, 5 to 7, and 13 (PIM0, PIM1, PIM3, PIM5 to PIM7, PIM13)
These registers set the input buffer of ports 0, 1, 3, 5 to 7, and 13 in 1-bit units.
The PIM0, PIM1, PIM3, PIM5 to PIM7, and PIM13 registers can be set by a 1-bit or 8-bit memory manipulation
instruction.
Reset signal generation clears the PIM0, PIM1, PIM3, PIM5 to PIM7, and PIM13 registers to 00H.
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Figure 12-21. Format of Port Input Mode Registers 0, 1, 3, 5 to 7, and 13 (PIM0, PIM1, PIM3, PIM5 to PIM7, PIM13)
Address: F0040H
After reset: 00H
R/W (Note: Bits 0, 2 to 7 are read only bit)
Symbol
7
6
5
4
3
2
1
0
PIM0
0
0
0
0
0
0
PIM0.1
0
Address: F0041H After reset: 00H
R/W (Note: Bits 2 to 6 are read only bit)
Symbol
7
6
5
4
3
2
1
0
PIM1
PIM1.7
0
0
0
0
0
PIM1.1
PIM1.0
Address: F0043H After reset: 00H
R/W (Note: Bits 0, 2 to 7 are read only bit)
Symbol
7
6
5
4
3
2
1
0
PIM3
0
0
0
0
0
0
PIM3.1
0
Address: F0045H After reset: 00H
R/W (Note: Bits 3, 4 are read only bit)
Symbol
7
6
5
4
3
2
1
0
PIM5
PIM5.7
PIM5.6
PIM5.5
0
0
PIM5.2
PIM5.1
PIM5.0
Address: F0046H After reset: 00H
R/W (Note: Bits 0, 2, 4 to 7 are read only bit)
Symbol
7
6
5
4
3
2
1
0
PIM6
0
0
0
0
PIM6.3
0
PIM6.1
0
Address: F0047H After reset: 00H
R/W (Note: Bits 1 to 7 are read only bit)
Symbol
7
6
5
4
3
2
1
0
PIM7
0
0
0
0
0
0
0
PIM7.0
Address: F004DH After reset: 00H
R/W (Note: Bits 0 to 4, 6, 7 are read only bit)
Symbol
7
6
5
4
3
2
1
0
PIM13
0
0
PIM13.5
0
0
0
0
0
PIMmn
Bit name
Port input threshold selection
0
Schmit1 input mode
1
Schmit3 input mode
PIM5.2
PIM5.1
PIM5.0
PIM3.1
PIM1.7
P52/SI10
P51/SCK10
P50/SDA11
P31/SDA11
P17
Bit name
PIM135
PIM70
PIM63
PIM61
PIM57
PIM56
PIM55
Port input
P135/
P61/SDA11
P57
P56/SCK01
P55/SI01
Port input
function
function
CRxD1
P70/
CRxD0/
LRxD0
P63/
CRxD1
PIM1.1
P11/LRxD1/
SI00
PIM1.0
P10/SCK00
PIM0.1
P01/
CRxD0
Remark For details of the Port Input mode registers (PIM), see 4.3 (4) Port Input mode registers.
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(16) Port output mode register (POM)
These registers set the output mode of P30, P31, P50, P60, P61, P136 in 1-bit units.
Port output mode is set by 1-bit unit. N-ch open drain output (VDD tolerance) mode can be selected during serial
communication with an external device of the different potential, and for the SDA11 and SCL11 pins during
simplified I2C communication with an external device of the same potential.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 12-22. Format of Port Output Mode Register (POM)
Address: F006FH After reset: 00H
R/W (Note: Bits 6, 7 are read only bit)
Symbol
7
6
5
4
3
2
1
0
POM
0
0
POM5
POM4
POM3
POM2
POM1
POM0
POMnx
Port input threshold selection
0
Normal output (CMOS) mode
1
Nch-OD output (VDD tolerance) mode
Bit name
Port output function
POM5
POM4
POM3
POM2
POM1
POM0
P50/
P136/
P31/
P30/
P61/
P60/
TO02/
TO00/
TO21/
TO20/
TO21/
TO20/
SDA11
SCL11
SDA11
SCL11
SDA11
SCL11
If use the alternate function of IIC, port output need to be set as Nch open-drain (Nch-OD) output. At that time, output
signal can also enter into port input (ENI=ON) and on -chip pull-up resistors should not be active (disabled by circuit).
Remark For details of the Port output mode register (POM), see 4.3 (5) Port output mode register.
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(17) Port mode registers 0, 1, 3, 5 to 7, 13 (PM0, PM1, PM3, PM5 to PM7, PM13)
These registers set input/output of ports 0, 1, 3, 5 to 7, 13 in 1-bit units.
When using the ports (such as P02/ SO00/TxD0/TI02/TO02/ TI12/TO12) to be shared with the serial data output
pin for serial data output, set the port mode register (PMxx) bit corresponding to each port to 0. And set the port
register (Pxx) bit corresponding to each port to 1.
Example: When using P02/SO00/TxD0/TI02/TO02/TI12/TO12 for serial data output or serial clock output
Set the PM0.2 bit of the port mode register 0 to 0.
Set the P0.2 bit of the port register 0 to 1.
When using the ports (such as P03/SI00/RxD0/TI03/TO03/TI13/TO13) to be shared with the serial data input pin
for serial data input, set the port mode register (PMxx) bit corresponding to each port to 1. At this time, the port
register (Pxx) bit may be 0 or 1.
Example: When using P03/SI00/RxD0/TI03/TO03/TI13/TO13 for serial data input
Set the PM0.3 bit of port mode register 0 to 1.
Set the P0.3 bit of port register 0 to 0 or 1.
The PM0, PM1, PM3, PM5 to PM7, PM13 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets the PM0, PM1, PM3, PM5 to PM7, PM13 registers to FFH.
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Figure 12-23. Format of Port Mode Registers 0, 1, 3, 5 to 7, 13 (PM0, PM1, PM3, PM5 to PM7, PM13)
Address: FFF20H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM0
PM0.7
PM0.6
PM0.5
PM0.4
PM0.3
PM0.2
PM0.1
PM0.0
Address: FFF21H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM1
PM1.7
PM1.6
PM1.5
PM1.4
PM1.3
PM1.2
PM1.1
PM1.0
Address: FFF23H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM3
PM3.7
PM3.6
PM3.5
PM3.4
PM3.3
PM3.2
PM3.1
PM3.0
Address: FFF25H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM5
PM5.7
PM5.6
PM5.5
PM5.4
PM5.3
PM5.2
PM5.1
PM5.0
Address: FFF26H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM6
PM6.7
PM6.6
PM6.5
PM6.4
PM6.3
PM6.2
PM6.1
PM6.0
Address: FFF27H
After reset: FFH
R/W
Symbol
7
6
5
4
3
2
1
0
PM7
PM7.7
PM7.6
PM7.5
PM7.4
PM7.3
PM7.2
PM7.1
PM7.0
Address: FFF2DH
After reset: FEH
R/W
Symbol
7
6
5
4
3
2
1
0
PM13
1
PM13.6
PM13.5
PM13.4
PM13.3
PM13.2
PM13.1
0
PMmn
Pmn pin I/O mode selection (m = 0, 1, 3, 5 to 7, 13 ; n = 0 to 7)
0
Output mode (output buffer ON)
1
Input mode (output buffer OFF)
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12.4 Operation stop mode
Each serial interface of serial array unit has the operation stop mode.
In this mode, serial communication cannot be executed, thus reducing the power consumption.
Caution
The shaded pins are provided at two ports. Select either port by using the corresponding register.
12.4.1 Stopping the operation by units
The stopping of the operation by units is set by using peripheral enable register 0 (PER0).
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro that is
not used is stopped in order to reduce the power consumption and noise.
To stop the operation of serial array unit 0, set bit 3 (SAU0EN) of PER0 to 0.
To stop the operation of serial array unit 1, set bit 4 (SAU1EN) of PER0 to 0.
Figure 12-24. Peripheral Enable Registers 0 (PER0) Setting When Stopping the Operation by Units
(a) Peripheral enable register 0 (PER0) … Set only the bit of SAU0, SAU1 to be stopped to 0.
PER0
7
6
5
4
3
2
1
0
RTCEN
LIN1EN
LIN0EN
SAU1EN
SAU0EN
TAU2EN
TAU1EN
TAU0EN
0/1
0/1
Control of SAUm input clock
0: Stops supply of input clock
1: Supplies input clock
Caution
If SAUmEN = 0, writing to a control register of serial array unit m is ignored, and, even if the
register is read, only the default value is read.
Note that this does not apply to the following registers.
Serial communication pin select register (STSEL)
Port input mode registers 0, 1, 3, 5 to 7, and 13 (PIM0, PIM1, PIM3, PIM5 to PIM7, PIM13)
Port output mode register (POM)
Port mode registers 0, 1, 3, 5 to 7, 13 (PM0, PM1, PM3, PM5 to PM7, PM13)
Port registers 0, 1, 3, 5 to 7, 13 (P0, P1, P3, P5 to P7, P13)
Remark
m: Unit number (m = 0, 1)
×: Bits not used with serial array units (depending on the settings of other peripheral functions)
0/1: Set to 0 or 1 depending on the usage of the user
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12.4.2 Stopping the operation by channels
The stopping of the operation by channels is set using each of the following registers.
Figure 12-25. Each Register Setting When Stopping the Operation by Channels
(a) Serial channel stop register m (STm) … This register is a trigger register that is used to enable
stopping communication/count by each channel.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
STm
1
0
STm.1
STm.0
0/1
0/1
1: Clears the SEm.n bit to 0 and stops the communication operation
* Because the STm.n bit is a trigger bit, it is cleared immediately when SEm.n = 0.
(b) Serial Channel Enable Status Register m (SEm) … This register indicates whether serial
transmission/reception operation of each channel is enabled or stopped.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SEm
1
0
SEm.1
SEm.0
0/1
0/1
0: Operation stops
* The SEm register is a read-only status register, whose operation is stopped by using the STm register.
With a channel whose operation is stopped, the value of the CKOmn bit of the SOm register can be set by
software.
(c) Serial output enable register m (SOEm) … This register is a register that is used to enable or stop
output of the serial communication operation of each channel.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm
1
0
SOEm.1 SOEm.0
0/1
0/1
0: Stops output by serial communication operation
* For channel n, whose serial output is stopped, the SOm.n bit value of the SOm register can be set by software.
(d) Serial output register m (SOm) …This register is a buffer register for serial output of each channel.
15
14
13
12
11
10
0
0
0
0
0
0
SOm
9
8
7
6
5
4
3
2
0
0
0
0
0
0
CKOm1 CKOm0
1: Serial clock output value is “1”
0/1
0/1
1
0
SOm.1 SOm.0
0/1
0/1
1: Serial data output value is “1”
* When using pins corresponding to each channel as port function pins, set the corresponding CKOmn, SOm.n bits to “1”.
Remarks 1.
2.
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
: Setting disabled (set to the initial value), 0/1: Set to 0 or 1 depending on the usage of the
user
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12.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10) Communication
This is a clocked communication function that uses three lines: serial clock (SCK) and serial data (SI and SO) lines.
[Data transmission/reception]
Data length of 7 to 16 bits (CSI00, CSI01, CSI10)
Phase control of transmit/receive data
MSB/LSB first selectable
Level setting of transmit/receive data
[Clock control]
Master/slave selection
Phase control of I/O clock
Setting of transfer period by prescaler and internal counter of each channel
Maximum transfer rate
During master communication: Max. fCLK/4Note
[Interrupt function]
Transfer end interrupt/buffer empty interrupt
[Error detection flag]
Overrun error
Note
Use the clocks within a range satisfying the SCK cycle time (tKCY) characteristics (see CHAPTER 33
ELECTRICAL SPECIFICATIONS (J GRADE) and CHAPTER 34
ELECTRICAL SPECIFICATIONS
(L GRADE)).
The channels supporting 3-wire serial I/O (CSI00, CSI01, CSI10) are channels 0 and 1 of SAU0, and channels 0 of
SAU1.
0
1
2
Used as CSI
Used as Simplified I C
0
CSI00
1
CSI01
0
CSI10
1
IIC11
Unit
Channel
3-wire serial I/O (CSI00, CSI01, CIS10) performs the following six types of communication operations.
Master transmission
(See 12.5.1.)
Master reception
(See 12.5.2.)
Master transmission/reception
(See 12.5.3.)
Slave transmission
(See 12.5.4.)
Slave reception
(See 12.5.5.)
Slave transmission/reception
(See 12.5.6.)
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12.5.1 Master transmission
Master transmission is an operation wherein the RL78/D1A outputs a transfer clock and transmits data to another
device.
3-Wire Serial I/O
CSI00
CSI01
CSI10
Target channel
Channel 0 of SAU0
Channel 1 of SAU0
Channel 0 of SAU1
Pins used
SCK00, SO00
SCK01, SO01
SCK10, SO10
Interrupt
INTCSI00
INTCSI01
INTCSI10
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be
selected.
Error detection flag
None
Transfer data length
7 to 16 bits
Transfer rate
Max. fCLK/4 [Hz],
Min. fCLK/(2 2 128) [Hz]
11
Data phase
Note
Selectable by the DAPmn bit of the SCRmn register
DAPmn = 0: Data output starts from the start of the serial clock operation.
DAPmn = 1: Data output starts half a clock before the start of the serial clock operation.
Clock phase
Selectable by the CKPmn bit of the SCRmn register
CKPmn = 0: Not reversed (Data output at the falling edge of SCK, data input at the rising edge of SCK)
CKPmn = 1: Reversed (Data output at the rising edge of SCK, data input at the falling edge of SCK)
Data direction
Note
MSB or LSB first
Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE) and CHAPTER 34 ELECTRICAL
SPECIFICATIONS (L GRADE)).
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), mn = 00, 01, 10
fCLK: System clock frequency
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(1) Register setting
Figure 12-26. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O
(CSI00, CSI01, CSI10) (1/2)
(a) Serial output register m (SOm) … Sets only the bits of the target channel.
15
14
13
12
11
10
0
0
0
0
0
0
SOm
9
8
7
6
5
4
3
2
0
0
0
0
0
0
CKOm1 CKOm0
0/1
0/1
1
0
SOm.1 SOm.0
0/1
0/1
Communication starts when these bits are 1 if the data
phase is not reversed (CKPmn = 0). If the phase is
reversed (CKPmn = 1), communication starts when these
bits are 0.
(b) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm
1
0
SOEm.1 SOEm.0
0/1
0/1
1
0
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
SSm.1
SSm.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1
0/1
8
7
6
5
4
3
2
1
0
1
0
0
SSm
(d) Serial mode register mn (SMRmn)
15
SMRmn
14
13
12
11
10
9
0
0
0
0
0
CKSmn CCSmn
0/1
0
STSmn
0
SISmn
0
MDmn2 MDmn1 MDmn0
0
0
0
0/1
Interrupt source of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
(e) Serial communication operation setting register mn (SCRmn)
15
SCRmn
14
13
12
11
10
0
0
TXEmn RXEmn DAPmn CKPmn
1
0
0/1
0/1
9
8
7
6
PTCmn1 PTCmn0 DIRmn
0
5
4
3
2
1
0
SLCmn1 SLCmn0 DLSmn3 DLSmn2 DLSmn1 DLSmn0
0
0/1
0
0
0
0/1
0/1
0/1
0/1
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
(f) Serial data register mn (SDRmn)
(i) When operation is stopped (SEm.n = 0)
15
14
13
12
11
10
9
SDRmn
Baud rate setting
Remark
: Setting is fixed in the CSI master transmission mode,
: Setting disabled (set to the initial value)
0/1: Set to 0 or 1 depending on the usage of the user
n : Channel number (n = 0, 1)
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Figure 12-26. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O
(CSI00, CSI01, CSI10) (2/2)
(ii) During operation (SEm.n = 1) (lower 8 bits: SDRmnL)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Transmit data register
SDRmn
SDRmnL
Remark
: Setting is fixed in the CSI master transmission mode,
: Setting disabled (set to the initial value)
0/1: Set to 0 or 1 depending on the usage of the user
n : Channel number (n = 0, 1)
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(2) Operation procedure
Figure 12-27. Initial Setting Procedure for Master Transmission
Starting initial setting
Setting the PER0 register
Release the serial array unit from the
reset status and start clock supply.
Setting the SPSm register
Set the operation clock.
Setting the SMRmn register
Set an operation mode, etc.
Setting the SCRmn register
Set a communication format.
Set a transfer baud rate (setting the
Setting the SDRmn register
transfer clock by dividing the operation
clock (fMCK)).
Setting the SOm register
Set the initial output level of the serial
clock (CKOmn) and serial data (SOm.n).
Changing setting of
the SOEm register
Set the SOEm.n bit to 1 and enable data
output of the target channel.
Enable data output and clock output of
Setting port
the target channel by setting a port
register and a port mode register.
Set input mode with the port mode
register and set PMxx to 0 to use the
SCKp and SOp pins as output,.
Set the SSm.n bit of the target channel to
Writing to the SSm register
1 to set the SEm.n bit to 1 (to enable
operation).
Starting communication
Set transmit data to the SDRmn register to
start communication.
Caution
After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial
clock select register m (SPSm) after 4 or more fCLK clocks have elapsed.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
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Figure 12-28. Procedure for Stopping Master Transmission
Starting setting to stop
Setting the STm register
Write 1 to the STm.n bit of the target channel.
Changing setting of
Set the SOEm.n bit to 0 and stop the output
the SOEm register
of the target channel.
Stopping communication
Stop communication in midway.
Check TSF when stopping communication
after confirming completion of data
transmission.
Remarks 1.
Even after communication is stopped, the pin level is retained. To resume the operation, re-set serial
output register m (SOm) (see Figure 12-29 Procedure for Resuming Master Transmission).
2.
m: Unit number (m = 0, 1) , n: Channel number (n = 0, 1)
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Figure 12-29. Procedure for Resuming Master Transmission
Starting setting for resumption
Enable data output and clock output of the target channel by
(Essential)
Port manipulation
setting a port register and a port mode register.
Set input mode with the port mode register and set PMxx to 0
to use the SCKp and SOp pins as output.
(Selective)
Changing setting of
Re-set the register to change the operation
the SPSm register
clock setting.
Re-set the register to change the
(Selective)
Changing setting of
the SDRmn register
transfer baud rate setting (setting the
transfer clock by dividing the operation
clock (fMCK)).
Re-set the register to change serial
(Selective)
Changing setting of
mode register mn (SMRmn) setting.
the SMRmn register
Re-set the register to change serial
(Selective)
Changing setting of
the SCRmn register
(Selective)
Changing setting of
the SOEm register
(Selective)
Changing setting of
the SOm register
(Selective)
Changing setting of
the SOEm register
communication operation setting register
mn (SCRmn) setting.
Set the SOEm.n bit to 0 to stop output
from the target channel.
Set the initial output level of the serial
clock (CKOmn) and serial data (SOm.n).
Set the SOEm.n bit to 1 and enable output
from the target channel.
Enable data output and clock output of the target channel by
(Essential)
Port manipulation
setting a port register and a port mode register.
Set PM10 to “0” to use the P10 pin as the SCK00 output.
Set PM10 to “1” to use the P10 pin as the SCK00 input.
Set PM12 to “0” to use the P12 pin as the SO00/TxD0 output.
Set the SSm.n bit of the target channel to
(Essential)
Writing to the SSm register
1 and set the SEm.n bit to 1 (to enable
operation).
Sets transmit data to the SIOp or SDRmn
(Essential)
Starting communication
register and start communication.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
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(3) Processing flow (in single-transmission mode)
Figure 12-30. Timing Chart of Master Transmission (in Single-Transmission Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
STmn
SEmn
SDRmn
Transmit data 1
Transmit data 2
Transmit data 3
SCKp pin
SOp pin
Shift
register mn
INTCSIp
Transmit data 1
Transmit data 2
Transmit data 3
Shift operation
Shift operation
Shift operation
Data transmission (8-bit length)
Data transmission (8-bit length)
Data transmission (8-bit length)
TSFmn
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1),
p: CSI number (p = 00, 01, 10), mn = 00, 01, 10
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Figure 12-31. Flowchart of Master Transmission (in Single-Transmission Mode)
Starting CSI communication
Setting the SAUmEN bit of
the PER0 register to 1
Setting operation clock by
the SPSm register
Specify the initial settings while the
SEm.n bit of serial channel enable
status register m (SEm) is 0 (operation
is stopped).
SMRmn, SCRmn: Setting communication
SDRmn[15:9]: Setting transfer rate
SOm, some: Setting output
Port manipulation
Writing 1 to the SSm.n bit
Writing transmit data to
SDRmn
Transfer end interrupt
generated?
No
Yes
Transmission completed?
No
Yes
Writing 1 to the STm.n bit
Clearing the SAUmEN bit of the
PER0 register to 0
End of communication
Caution
After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial
clock select register m (SPSm) after 4 or more fCLK clocks have elapsed.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
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(4) Processing flow (in continuous transmission mode)
Figure 12-32. Timing Chart of Master Transmission (in Continuous Transmission Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
STmn
SEmn
SDRmn
Transmit data 1
Transmit data 2
Transmit data 3
SCKp pin
SOp pin
Transmit data 2
Transmit data 1
Shift
register mn
INTCSIp
Shift operation
Transmit data 3
Shift operation
Data transmission (8-bit length)
Shift operation
Data transmission (8-bit length)
Data transmission (8-bit length)
MDmn0
TSFmn
BFFmn
(Note)
Note
If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is
1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten.
Caution
The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it will be rewritten before the
transfer end interrupt of the last transmit data.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1),
p: CSI number (p = 00, 01, 10), mn = 00, 10, 11
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Figure 12-33. Flowchart of Master Transmission (in Continuous Transmission Mode)
Starting CSI communication
Setting the SAUmEN bit of
the PER0 register to 1
Setting operation clock by
the SPSm register
SMRmn, SCRmn: Setting communication
Select the buffer empty
SDRmn[15:9]: Setting transfer rate
interrupt.
SOm, SOEm: Setting output
Specify the initial settings while the
SEm.n bit of serial channel enable
status register m (SEm) is 0 (operation
is stopped).
Port manipulation
Writing 1 to the SSm.n bit
Writing transmit data to
SDRmn
No
Buffer empty interrupt
generated?
Yes
Yes
Transmitting next data?
No
Clearing 0 to the MDmn0 bit
No
TSFmn = 1?
Yes
No
Transfer end interrupt
generated?
Yes
Yes
Communication
continued?
Writing 1 to the MDmn0 bit
No
Writing 1 to the STm.n bit
Clearing the SAUmEN bit of
the PER0 register to 0
End of communication
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CHAPTER 12 SERIAL ARRAY UNIT
After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial
clock select register m (SPSm) after 4 or more fCLK clocks have elapsed.
Remarks 1. to in the figure correspond to to in Figure 12-32
Timing Chart of Master
Transmission (in Continuous Transmission Mode).
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
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12.5.2 Master reception
Master reception is an operation wherein the RL78/D1A outputs a transfer clock and receives data from other device.
3-Wire Serial I/O
CSI00
CSI01
CSI10
Target channel
Channel 0 of SAU0
Channel 1 of SAU0
Channel 0 of SAU1
Pins used
SCK00, SI00
SCK01, SI01
SCK10, SI10
Interrupt
INTCSI00
INTCSI01
INTCSI10
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be
selected.
Error detection flag
Overrun error detection flag (OVFmn) only
Transfer data length
7 to 16 bits
Transfer rate
Max. fCLK/4 [Hz],
Min. fCLK/(2 2 128) [Hz]
11
Data phase
Note
Selectable by the DAPmn bit of the SCRmn register
DAPmn = 0: Data input starts from the start of the serial clock operation.
DAPmn = 1: Data input starts half a clock before the start of the serial clock operation.
Clock phase
Selectable by the CKPmn bit of the SCRmn register
CKPmn = 0: Not reversed
CKPmn = 1: Reversed
Data direction
MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE) and CHAPTER 34 ELECTRICAL
SPECIFICATIONS (L GRADE)).
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), mn = 00, 01, 10
fCLK: System clock frequency
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(1) Register setting
Figure 12-34. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O
(CSI00, CSI01, CSI10) (1/2)
(a) Serial output register m (SOm) … Sets only the bits of the target channel.
15
14
13
12
11
10
0
0
0
0
0
0
SOm
9
8
7
6
5
4
3
2
0
0
0
0
0
0
CKOm1 CKOm0
0/1
0/1
1
0
SOm.1 SOm.0
Communication starts when these bits are 1 if the data
phase is not reversed (CKPmn = 0). If the phase is
reversed (CKPmn = 1), communication starts when these
bits are 0.
(b) Serial output enable register m (SOEm) …The register that not used in this mode.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm
1
0
SOEm.1 SOEm.0
1
0
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
SSm.1
SSm.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1
0/1
8
7
6
5
4
3
2
1
0
1
0
0
SSm
(d) Serial mode register mn (SMRmn)
15
SMRmn
14
13
12
11
10
9
0
0
0
0
0
CKSmn CCSmn
0/1
0
STSmn
0
SISmn0
0
MDmn2 MDmn1 MDmn0
0
0
0
0/1
Interrupt sources of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
(e) Serial communication operation setting register mn (SCRmn)
15
SCRmn
14
13
12
11
10
0
0
1
0/1
0/1
8
7
6
PTCmn1 PTCmn0 DIRmn
TXEmn RXEmn DAPmn CKPmn
0
9
0
5
4
3
2
1
0
SLCmn1 SLCmn0 DLSmn3 DLSmn2 DLSmn1 DLSmn0
0
0/1
0
0
0
0/1
0/1
0/1
0/1
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
(f) Serial data register mn (SDRmn)
(i) When operation is stopped (SEm.n = 0)
15
14
13
12
11
10
9
SDRmn
Baud rate setting
Remark
: Setting is fixed in the CSI master reception mode,
: Setting disabled (set to the initial value)
: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
n: Channel number (n = 0, 1)
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Figure 12-34. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O
(CSI00, CSI01, CSI10) (2/2)
(ii) During operation (SEm.n = 1) (lower 8 bits: SDRmnL)
15
14
13
12
11
10
SDRmn
9
8
7
6
5
4
3
2
1
0
Receive data register
SDRmnL
Remark
: Setting is fixed in the CSI master reception mode,
: Setting disabled (set to the initial value)
0/1: Set to 0 or 1 depending on the usage of the user
n: Channel number (n = 0, 1)
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(2) Operation procedure
Figure 12-35. Initial Setting Procedure for Master Reception
Starting initial setting
Release the serial array unit from the reset status and start
Setting the PER0 register
Setting the SPSm register
Setting the SMRmn register
clock supply.
Set the operation clock.
Set an operation mode, etc.
Setting the SCRmn register
Set a communication format.
Setting the SDRmn register
Set a transfer baud rate (setting the transfer clock by dividing the
operation clock (fMCK)).
Setting the SOm register
Set the initial output level of the serial clock (CKOmn).
Enable data output and clock output of the target channel by setting a
port register and a port mode register.
Setting port
Writing to the SSm register
Set the SSm.n bit of the target channel to 1 and set the SEm.n bit to 1
(to enable operation).
Starting communication
Caution
Set dummy data to the SDRmn register to start communication.
After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial
clock select register m (SPSm) after 4 or more fCLK clocks have elapsed.
Figure 12-36. Procedure for Stopping Master Reception
Starting setting to stop
Setting the STm register
Stopping communication
Write 1 to the STm.n bit of the target channel.
Stop communication in midway.
Check TSF when stopping communication after confirming completion
of data transmission.
Remark
Even after communication is stopped, the pin level is retained. To resume the operation, re-set serial
output register m (SOm) (see Figure 12-37 Procedure for Resuming Master Reception).
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Figure 12-37. Procedure for Resuming Master Reception
Starting setting for resumption
(Essential)
Port manipulation
Disable clock output of the target channel by setting a port
register and a port mode register.
(Selective)
Changing setting of
Re-set the register to change the operation clock setting.
the SPSm register
Re-set the register to change the transfer baud rate setting
Changing setting of
(Selective)
the SDRmn register
(setting the transfer clock by dividing the operation clock
(fMCK)).
Re-set the register to change serial mode register mn
Changing setting of
(Selective)
(SMRmn) setting.
the SMRmn register
Re-set the register to change serial communication operation
Changing setting of
(Selective)
setting register mn (SCRmn) setting.
the SCRmn register
Changing setting of
(Selective)
Set the initial output level of the serial clock (CKOmn).
the SOm register
If the FEF, PEF, and OVF flags remain set, clear them
(Selective)
Clearing error flag
(Essential)
Port manipulation
using serial flag clear trigger register mn (SIRmn).
Enable data output and clock output of the target channel by
setting a port register and a port mode register.
Set input mode with the port mode register and set PMxx to 0 to
use the SCKp pins as output,.
Set 1 to the PIEN register to use the SIp pin as input.
(Essential)
Writing to the SSm register
Set the SSm.n bit of the target channel to 1 and set the
SEm.n bit to 1 (to enable operation).
Sets dummy data to the SDRmn register to start
(Essential)
Starting communication
communication.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
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(3) Processing flow (in single-reception mode)
Figure 12-38. Timing Chart of Master Reception (in Single-Reception Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
STmn
SEmn
SDRmn
Dummy data for reception
Write
Receive data 1
Dummy data
Write
Read
Receive data 3
Receive data 2
Dummy data
Write
Read
Read
SCKp pin
SIp pin
Shift
register mn
INTCSIp
Receive data 1
Reception & shift operation
Data reception (8-bit length)
Receive data 2
Receive data 3
Reception & shift operation
Reception & shift operation
Data reception (8-bit length)
Data reception (8-bit length)
TSFmn
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1),
p: CSI number (p = 00, 01, 10), mn = 00, 01, 10
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Figure 12-39. Flowchart of Master Reception (in Single-Reception Mode)
Starting CSI
Setting the SAUmEN bit of
the PER0 register to 1
Setting transfer rate by
the SPSm register
Specify the initial settings while the
SEm.n bit of serial channel enable
status register m (SEm) is 0 (operation
is stopped).
SMRmn, SCRmn: Setting communication
SDRmn[15:9]: Setting transfer rate
SOm: Setting SCKp output
Port manipulation
Writing 1 to the SSm.n bit
Writing dummy data to
SDRmn
Starting reception
Transfer end interrupt
generated?
No
Yes
Reading the
SDRmn register
No
Reception completed?
Yes
Writing 1 to the STm.n bit
Clearing the SAUmEN bit of the
PER0 register to 0
End of communication
Caution
After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial
clock select register m (SPSm) after 4 or more fCLK clocks have elapsed.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
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(4) Processing flow (in continuous reception mode)
Figure 12-40. Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
SSmn
STmn
SEmn
Receive data 3
SDRmn
Dummy data
Write
Dummy data
Write
Receive data 2
Receive data 1
Dummy data
Write
Read
Read
Read
SCKp pin
Receive data 1
SIp pin
Shift
register mn
Receive data 3
Receive data 2
Reception & shift operation
Reception & shift operation
Data reception (8-bit length)
Data reception (8-bit length)
Reception & shift operation
INTCSIp
Data reception (8-bit length)
MDmn0
TSFmn
BFFmn
Caution
The MDmn0 bit can be rewritten even during operation.
However, rewrite it before receive of the last bit is started, so that it has been rewritten before the
transfer end interrupt of the last receive data.
Remarks 1. to in the figure correspond to to in Figure 12-41 Flowchart of Master Reception
(in Continuous Reception Mode).
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1),
p: CSI number (p = 00, 01, 10), mn = 00, 10, 11
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Figure 12-41. Flowchart of Master Reception (in Continuous Reception Mode)
Starting CSI communication
Setting the SAUmEN bit of
the PER0 register to 1
Setting transfer rate by
the SPSm register
Perform initial setting when SEm.n = 0.
Select the buffer empty interrupt.
SMRmn, SCRmn: Setting communication
SDRmn[15:9]: Setting transfer rate
SOm: Setting output and SCKp output
Port manipulation
Writing 1 to the SSm.n bit
Writing dummy data to
SDRmn
Buffer empty interrupt
generated?
No
Yes
Reading receive data from
SDRmn
The following is
the last
No
Yes
Clearing 0 to the MDmn0
TSFmn = 1?
No
Yes
Transfer end interrupt
generated?
Yes
Reading receive data from
SDRmn
Yes
Communication
No
Writing 1 to the MDmn0 bit
Writing 1 to the STm.n bit
Clearing the SAUmEN bit
of the PER0 register to 0
End of communication
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Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
Remarks 1. to in the figure correspond to to in Figure 12-40
Timing Chart of Master
Reception (in Continuous Reception Mode).
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
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12.5.3 Master transmission/reception
Master transmission/reception is an operation wherein the RL78/D1A outputs a transfer clock and transmits/receives
data to/from other device.
3-Wire Serial I/O
CSI00
CSI01
CSI10
Target channel
Channel 0 of SAU0
Channel 1 of SAU0
Channel 0 of SAU1
Pins used
SCK00, SI00, SO00
SCK01, SI01, SO01
SCK10, SI10, SO10
Interrupt
INTCSI00
INTCSI01
INTCSI10
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be
selected.
Error detection flag
Overrun error detection flag (OVFmn) only
Transfer data length
7 to 16 bits
Transfer rate
Max. fCLK/4 [Hz],
Min. fCLK/(2 2 128) [Hz]
11
Data phase
Note
Selectable by the DAPmn bit of the SCRmn register
DAPmn = 0: Data I/O starts at the start of the serial clock operation.
DAPmn = 1: Data I/O starts half a clock before the start of the serial clock operation.
Clock phase
Selectable by the CKPmn bit of the SCRmn register
CKPmn = 0: Not reversed
CKPmn = 1: Reversed
Data direction
MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE) and CHAPTER 34 ELECTRICAL
SPECIFICATIONS (L GRADE)).
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), mn = 00, 01, 10
fCLK: System clock frequency
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(1) Register setting
Figure 12-42. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O
(CSI00, CSI01, CSI10) (1/2)
(a) Serial output register m (SOm) … Sets only the bits of the target channel.
15
14
13
12
11
10
0
0
0
0
0
0
SOm
9
8
7
6
5
4
3
2
0
0
0
0
0
0
CKOm1 CKOm0
0/1
0/1
1
0
SOm.1 SOm.0
0/1
0/1
Communication starts when these bits are 1 if the data
phase is not reversed (CKPmn = 0). If the phase is
reversed (CKPmn = 1), communication starts when these
bits are 0.
(b) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
some
1
0
SOES1 SOES0
0/1
0/1
1
0
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
SSS.1
SSS.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1
0/1
8
7
6
5
4
3
2
1
0
1
0
0
SSm
(d) Serial mode register mn (SMRmn)
15
SMRmn
14
13
12
11
10
9
0
0
0
0
0
CKSmn CCSmn
0/1
0
STSmn
0
SISmn0
0
MDmn2 MDmn1 MDmn0
0
0
0
0/1
Interrupt sources of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
(e) Serial communication operation setting register mn (SCRmn)
15
SCRmn
14
13
12
11
10
0
0
TXEmn RXEmn DAPmn CKPmn
1
1
0/1
0/1
9
8
7
6
PTCmn1 PTCmn0 DIRmn
0
5
4
3
2
1
0
SLCmn1 SLCmn0 DLSmn3 DLSmn2 DLSmn1 DLSmn0
0
0/1
0
0
0
0/1
0/1
0/1
0/1
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
(f) Serial data register mn (SDRmn)
(i) When operation is stopped (SEm.n = 0)
15
14
13
12
11
10
9
SDRmn
Baud rate setting
Remark
: Setting is fixed in the CSI master transmission/reception mode,
: Setting disabled (set to the initial
value)
0/1: Set to 0 or 1 depending on the usage of the user
n: Channel number (n = 0, 1)
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Figure 12-42. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O
(CSI00, CSI01, CSI10) (2/2)
(ii) During operation (SEm.n = 1) (lower 8 bits: SDRmnL)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Transmit data register/receive data register
SDRmn
SDRmnL
Remark
: Setting is fixed in the CSI master transmission/reception mode,
: Setting disabled (set to the initial
value)
0/1: Set to 0 or 1 depending on the usage of the user
n: Channel number (n = 0, 1)
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(2) Operation procedure
Figure 12-43. Initial Setting Procedure for Master Transmission/Reception
Starting initial setting
Setting the PER0 register
Setting the SPSm register
Release the serial array unit from the reset status and start
clock supply.
Set the operation clock.
Setting the SMRmn register
Set an operation mode, etc.
Setting the SCRmn register
Set a communication format.
Set a transfer baud rate (setting the transfer clock by dividing
Setting the SDRmn register
the operation clock (fMCK)).
Set the initial output level of the serial clock (CKOmn) and
Setting the SOm register
Changing setting of
the SOEm register
serial data (SOm.n).
Set the SOEm.n bit to 1 and enable data output of the target
channel.
Enable data output and clock output of the target channel by setting
Setting port
a port register and a port mode register.
Set input mode with the port mode register and set PMxx to 0 to
use the SOp and SCKp pins as output.
Set 1 to the PMXx register to use the SCKp and SIp pins as input.
Writing to the SSm register
Starting communication
Caution
Set the SSm.n bit of the target channel to 1 and set the SEm.n
bit to 1 (to enable operation).
Set transmit data to the SDRmn register and start
communication.
After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial
clock select register m (SPSm) after 4 or more fCLK clocks have elapsed.
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Figure 12-44. Procedure for Stopping Master Transmission/Reception
Starting setting to stop
Setting the STm register
Write 1 to the STm.n bit of the target channel.
Set the SOEm.n bit to 0 and stop the output of the target
Changing setting of
channel.
the SOEm register
Stopping communication
Stop communication in midway.
Check TSF when stopping communication after confirming
completion of data transmission.
Remark
Even after communication is stopped, the pin level is retained. To resume the operation, re-set serial
output register m (SOm) (see Figure 12-45
Procedure for Resuming Master Transmission/
Reception).
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Figure 12-45. Procedure for Resuming Master Transmission/Reception
Starting setting for
(Essential)
Port manipulation
Disable data output and clock output of the target channel
by setting a port register and a port mode register.
(Selective)
Changing setting of
Re-set the register to change the operation clock setting.
the SPSm register
Re-set the register to change the transfer baud rate
Changing setting of
(Selective)
the SDRmn register
Changing setting of
(Selective)
the SMRmn register
Changing setting of
(Selective)
the SCRmn register
setting (setting the transfer clock by dividing the
operation clock (fMCK)).
Re-set the register to change serial mode register mn
(SMRmn) setting.
Re-set the register to change serial communication
operation setting register mn (SCRmn) setting.
If the FEF, PEF, and OVF flags remain set, clear them
(Selective)
Clearing error flag
(Selective)
Changing setting of
using serial flag clear trigger register mn (SIRmn).
Set the SOEm.n bit to 0 to stop output from the target
channel.
the SOEm register
Set the initial output level of the serial clock (CKOmn) and
Changing setting of
(Selective)
serial data (SOm.n).
the SOm register
Changing setting of
(Selective)
the SOEm register
(Essential)
Port manipulation
(Essential)
Writing to the SSm register
(Essential)
Starting communication
Set the SOEm.n bit to 1 and enable output from the target
channel.
Enable data output and clock output of the target channel by
setting a port register and a port mode register.
Set input mode with the port mode register and set PMxx to 0
to use the SOp and SCKp pins as output.
Set 1 to the PMxx register to use the SCKp and SIp pins as
input.
Set the SSm.n bit of the target channel to 1 and set the
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SEm.n bit to 1 (to enable operation).
Sets transmit data to the SDRmn register and start
communication.
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Processing flow (in single-transmission/reception mode)
Figure 12-46. Timing Chart of Master Transmission/Reception (in Single-Transmission/Reception Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
STmn
SEmn
SDRmn
Transmit data 1
Write
Receive data 1
Transmit data 2
Write
Read
Receive data 3
Receive data 2
Transmit data 2
Write
Read
Read
SCKp pin
SIp pin
Shift
register mn
SOp pin
Receive data 1
Reception & shift operation
Transmit data 1
Receive data 2
Reception & shift operation
Transmit data 2
Receive data 3
Reception & shift operation
Transmit data 3
INTCSIp
Data transmission/reception (8-bit length)
Data transmission/reception (8-bit length)
Data transmission/reception (8-bit length)
TSFmn
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1),
p: CSI number (p = 00, 01, 10), mn = 00, 01, 10
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Figure 12-47. Flowchart of Master Transmission/Reception (in Single- Transmission/Reception Mode)
Starting CSI
Setting the SAUmEN bit of
the PER0 register to 1
Setting operation clock by
the SPSm register
SMRmn, SCRmn :Setting communication
Specify the initial settings while the SEm.n bit of the
SDRmn[15:9]
:Setting transfer rate
serial channel enable status register m (SEm) is 0
SOm, SOEm
:Setting output and SCKp output
(operation is stopped).
Port manipulation
Writing 1 to the SSm.n bit
Writing transmit data to
SDRmn
Starting transmission/reception
No
Transfer end interrupt
generated?
Yes
Reading the
SDRmn register
Transmission/reception
completed?
No
Yes
Writing 1 to the STm.n bit
Clearing the SAUmEN bit of
the PER0 register to 0
End of communication
Caution
After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial
clock select register m (SPSm) after 4 or more fCLK clocks have elapsed.
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(4) Processing flow (in continuous transmission/reception mode)
Figure 12-48. Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
STmn
SEmn
Receive data 3
SDRmn
Transmit data 1 Transmit data 2
Write
Write
Receive data 1
Transmit data 3
Write
Read
Receive data 2
Read
Read
SCKp pin
SIp pin
Receive data 1
Shift
register mn
SOp pin
Receive data 3
Receive data 2
Reception & shift operation
Reception & shift operation
Reception & shift operation
Transmit data 2
Transmit data 1
Transmit data 3
INTCSIp
Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) Data transmission/reception (8-bit length)
MDmn0
TSFmn
BFFmn
(Note 1)
(Note 2)
(Note 2)
Notes 1. If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn
(SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten.
2. The transmit data can be read by reading the SDRmn register during this period. At this time, the
transfer operation is not affected.
Caution
The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it has been rewritten before
the transfer end interrupt of the last transmit data.
Remarks 1. to in the figure correspond to to in Figure 12-49
Flowchart of Master
Transmission/Reception (in Continuous Transmission/Reception Mode).
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1),
p: CSI number (p = 00, 01, 10), mn = 00, 10, 11
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Figure 12-49. Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode)
Starting CSI
Setting the SAUmEN bit
of the PER0 register to 1
Setting operation clock by
the SPSm register
SMRmn, SCRmn :Setting communication
Specify the initial settings while the
Select the buffer empty
SDRmn[15:9]
:Setting transfer rate
SEm.n bit of serial channel enable
interrupt
SOm, some
:Setting output and SCKp output
status register m (SEm) is 0
(operation is stopped).
Port manipulation
Writing 1 to the SSm.n bit
Writing transmit data to
SDRmn
No
Buffer empty interrupt
generated?
Yes
Reading receive data
from SDRmn
Yes
Communication data
exists?
No
Clearing 0 to the MDmn0
TSFmn = 1?
No
Yes
Transfer end interrupt
generated?
No
Yes
Reading receive data
from SDRmn
Yes
Communication
No
Writing 1 to the MDmn0 bit
Writing 1 to the STm.n bit
Clearing the SAUmEN bit
of the PER0 register to 0
End of communication
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Caution
CHAPTER 12 SERIAL ARRAY UNIT
After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial
clock select register m (SPSm) after 4 or more fCLK clocks have elapsed.
Remark
to in the figure correspond to to in Figure 12-48 Timing Chart of Master
Transmission/Reception (in Continuous Transmission/Reception Mode).
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12.5.4 Slave transmission
Slave transmission is that the RL78/D1A transmits data to another device in the state of a transfer clock being input
from another device.
3-Wire Serial I/O
CSI00
CSI01
CSI10
Target channel
Channel 0 of SAU0
Channel 1 of SAU0
Channel 0 of SAU1
Pins used
SCK00, SO00
SCK01, SO01
SCK10, SO10
Interrupt
INTCSI00
INTCSI01
INTCSI10
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can
be selected.
Error detection flag
Overrun error detection flag (OVFmn) only
Transfer data length
7 to 16 bits
Transfer rate
Max. fMCK/6 [Hz]
Data phase
Selectable by the DAPmn bit of the SCRmn register
Notes 1, 2
.
DAPmn = 0: Data output starts from the start of the serial clock operation.
DAPmn = 1: Data output starts half a clock before the start of the serial clock operation.
Clock phase
Selectable by the CKPmn bit of the SCRmn register
CKPmn = 0: Not reversed
CKPmn = 1: Reversed
Data direction
MSB or LSB first
Notes 1. Because the external serial clock input to the SCK00, SCK01, and SCK10 pins is sampled internally and
used, the fastest transfer rate is fMCK/6 [Hz]. Set the SPSm register so that fMCK/6 [Hz] equals fSCK/2 or more
that is set with the SDRm register.
2. Use this operation within a range that satisfies the conditions above and the AC characteristics in the
electrical specifications (see CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE) and CHAPTER 34
ELECTRICAL SPECIFICATIONS (L GRADE)).
Remarks 1. fMCK: Operation clock frequency of target channel
fSCK: Serial clock frequency
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), mn = 00, 01, 10
fCLK: System clock frequency
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Register setting
Figure 12-50. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O
(CSI00, CSI01, CSI10) (1/2)
(a) Serial output register m (SOm) … Sets only the bits of the target channel.
15
14
13
12
11
10
0
0
0
0
0
0
SOm
9
8
7
6
5
4
3
2
0
0
0
0
0
0
CKOm1 CKOm0
1
0
SOm.1 SOm.0
0/1
0/1
(b) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm
1
0
SOEm.1 SOEm.0
0/1
0/1
1
0
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
SSm.1
SSm.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1
0/1
8
7
6
5
4
3
2
1
0
1
0
0
SSm
(d) Serial mode register mn (SMRmn)
15
SMRmn
14
13
12
11
10
9
0
0
0
0
0
CKSmn CCSmn
0/1
1
STSmn
0
SISmn0
0
MDmn2 MDmn1 MDmn0
0
0
0
0/1
Interrupt sources of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
(e) Serial communication operation setting register mn (SCRmn)
15
SCRmn
14
13
12
11
10
0
0
0
0/1
0/1
8
7
6
PTCmn1 PTCmn0 DIRmn
TXEmn RXEmn DAPmn CKPmn
1
9
0
5
4
3
2
1
0
SLCmn1 SLCmn0 DLSmn3 DLSmn2 DLSmn1 DLSmn0
0
0/1
0
0
0
0/1
0/1
0/1
0/1
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
(f) Serial data register mn (SDRmn)
(i) When operation is stopped (SEm.n = 0)
15
SDRmn
Remark
14
13
12
11
10
0000000
Baud rate setting
9
: Setting is fixed in the CSI slave transmission mode,
: Setting disabled (set to the initial value)
: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
n: Channel number (n = 0, 1)
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Figure 12-50. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O
(CSI00, CSI01, CSI10) (2/2)
(ii) During operation (SEm.n = 1) (lower 8 bits: SDRmnL)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Transmit data register
SDRmn
SDRmnL
Remark
: Setting is fixed in the CSI slave transmission mode,
: Setting disabled (set to the initial value)
: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
n: Channel number (n = 0, 1)
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(2) Operation procedure
Figure 12-51. Initial Setting Procedure for Slave Transmission
Starting initial setting
Setting the PER0 register
Setting the SPSm register
Release the serial array unit from the reset status and start clock
supply.
Set the operation clock.
Setting the SMRmn register
Set an operation mode, etc.
Setting the SCRmn register
Set a communication format.
Setting the SDRmn register
Set bits 15 to 9 to 0000000B for baud rate setting.
Setting the SOm register
Changing setting of
Set the initial output level of the serial data (SOm.n).
Set the SOEm.n bit to 1 and enable data output of the target channel.
the SOEm register
Enable data output of the target channel by setting a port register
Setting port
and a port mode register.
Set input mode with the port mode register and set PMxx to 0 to use
the SOp pins as output.
Set 1 to the PMxx register to use the SCKp pin as input.
Writing to the SSm register
Set the SSm.n bit of the target channel to 1 and set the SEm.n bit to 1
(to enable operation).
Starting communication
Set transmit data to the SDRmn register and wait for a clock from
the master.
Caution
After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial
clock select register m (SPSm) after 4 or more fCLK clocks have elapsed.
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Figure 12-52. Procedure for Stopping Slave Transmission
Starting setting to stop
Setting the STm register
Changing setting of
Write 1 to the STm.n bit of the target
channel.
Set the SOEm.n bit to 0 and stop the
output of the target channel.
the SOEm register
Stopping communication
Stop communication in midway.
Check TSF when stopping communication after
confirming completion of data transmission.
Remark
Even after communication is stopped, the pin level is retained. To resume the operation, re-set the SOm
register (see Figure 12-53. Procedure for Resuming Slave Transmission).
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Figure 12-53. Procedure for Resuming Slave Transmission
Starting setting for resumption
(Essential)
Manipulating target for
communication
(Selective)
Port manipulation
(Selective)
Changing setting of
the SPSm register
(Selective)
Changing setting of
the SMRmn register
(Selective)
Changing setting of
the SCRmn register
Stop the target for communication or wait until the
target completes its operation.
Disable data output of the target channel by setting a
port register and a port mode register.
Re-set the register to change the operation
clock setting.
Re-set the register to change serial mode register mn
(SMRmn) setting.
Re-set the register to change serial communication
operation setting register mn (SCRmn) setting.
If the FEF, PEF, and OVF flags remain set, clear them
(Selective)
Clearing error flag
(Selective)
Changing setting of
Set the SOEm.n bit to 0 to stop output from the target
the SOEm register
channel.
(Selective)
using serial flag clear trigger register mn (SIRmn).
Changing setting of
Set the initial output level of the serial data (SOm.n).
the SOm register
(Selective)
Changing setting of
Set the SOEm.n bit to 1 and enable output from the
the SOEm register
target channel.
Enable data output and clock output of the target
(Essential)
Port manipulation
channel by setting a port register and a port mode
register.
Set input mode with the port mode register and set
PMxx to 0 to use the SOp pin as output.
Set 1 to the PMxx register to use the SCKp pin as
input
(Essential)
Writing to the SSm register
(Essential)
Starting communication
(Essential)
Starting target for communication
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Set the SSm.n bit of the target channel to 1 and set
the SEm.n bit to 1 (to enable operation).
Sets transmit data to the SDRmn register and wait for
a clock from the master.
Starts the target for communication.
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Processing flow (in single-transmission mode)
Figure 12-54. Timing Chart of Slave Transmission (in Single-Transmission Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
STmn
SEmn
SDRmn
Transmit data 1
Transmit data 2
Transmit data 3
SCKp pin
SOp pin
Transmit data 1
Shift
register mn
INTCSIp
Shift operation
Data transmission (8-bit length)
Transmit data 2
Shift operation
Data transmission (8-bit length)
Transmit data 3
Shift operation
Data transmission (8-bit length)
TSFmn
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1),
p: CSI number (p = 00, 01, 10), mn = 00, 01, 10
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Figure 12-55. Flowchart of Slave Transmission (in Single-Transmission Mode)
Starting CSI communication
Setting the SAUmEN bit of
the PER0 register to 1
Setting transfer rate by
the SPSm register
SMRmn, SCRmn: Setting communication
Specify the initial settings while the SEm.n bit of
SDRmn[15:9]: Setting 0000000B
serial channel enable status register m (SEm) is 0
SOm, SOEm: Setting output
(operation is stopped).
Port manipulation
Writing 1 to the SSm.n bit
Writing transmit data to
SDRmn
Transfer end interrupt
generated?
No
Yes
Transmission
completed?
No
Yes
Writing 1 to the STm.n bit
Clearing the SAUmEN bit of
the PER0 register to 0
End of communication
Caution
After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial
clock select register m (SPSm) after 4 or more fCLK clocks have elapsed.
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(4) Processing flow (in continuous transmission mode)
Figure 12-56. Timing Chart of Slave Transmission (in Continuous Transmission Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
STmn
SEmn
SDRmn
Transmit data 1
Transmit data 3
Transmit data 2
SCKp pin
SOp pin
Transmit data 1
Shift
register mn
INTCSIp
Transmit data 3
Transmit data 2
Shift operation
Shift operation
Data transmission (8-bit length)
Shift operation
Data transmission (8-bit length)
Data transmission (8-bit length)
MDmn0
TSFmn
BFFmn
(Note)
Note If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is
1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten.
Caution
The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1),
p: CSI number (p = 00, 01, 10), mn = 00, 10, 11
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Figure 12-57. Flowchart of Slave Transmission (in Continuous Transmission Mode)
Starting CSI
Setting the SAUmEN bit of
the PER0 register to 1
Setting transfer rate by
the SPSm register
SMRmn, SCRmn: Setting communication
Specify the initial settings while the SEm.n bit of
Select the buffer empty
SDRmn[15:9]: Setting 0000000B
serial channel enable status register m (SEm) is 0
interrupt.
SOm, SOEm: Setting output
(operation is stopped).
Port manipulation
Writing 1 to the SSm.n bit
Writing transmit data to
SDRmn
No
Buffer empty interrupt
generated?
Yes
Yes
Transmitting next
No
Clearing 0 to the MDmn0 bit
No
TSFmn = 1?
Yes
Transfer end interrupt
generated?
Yes
Yes
No
Communication
No
Writing 1 to the MDmn0 bit
Writing 1 to the STm.n bit
Clearing the SAUmEN bit
of the PER0 register to 0
End of communication
Caution
After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial
clock select register m (SPSm) after 4 or more fCLK clocks have elapsed.
Remark
to in the figure correspond to to in Figure 12-56
Timing Chart of Slave
Transmission (in Continuous Transmission Mode).
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12.5.5 Slave reception
Slave reception is that the RL78/D1A receives data from another device in the state of a transfer clock being input from
another device.
3-Wire Serial I/O
CSI00
CSI01
CSI10
Target channel
Channel 0 of SAU0
Channel 1 of SAU0
Channel 0 of SAU1
Pins used
SCK00, SI00
SCK01, SI01
SCK10, SI10
Interrupt
INTCSI00
INTCSI01
INTCSI10
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag
Overrun error detection flag (OVFmn) only
Transfer data length
7 to 16 bits
Transfer rate
Max. fMCK/6 [Hz]
Data phase
Selectable by the DAPmn bit of the SCRmn register
Notes 1, 2
DAPmn = 0: Data input starts from the start of the serial clock operation.
DAPmn = 1: Data input starts half a clock before the start of the serial clock operation.
Clock phase
Selectable by the CKPmn bit of the SCRmn register
CKPmn = 0: Not reversed
CKPmn = 1: Reversed
Data direction
MSB or LSB first
Notes 1. Because the external serial clock input to the SCK00, SCK01, and SCK10 pins is sampled internally and
used, the fastest transfer rate is fMCK/6 [Hz]. Set the SPSm register so that fMCK/6 [Hz] equals fSCK or more
that is set with the SDRm register.
2. Use this operation within a range that satisfies the conditions above and the AC characteristics in the
electrical specifications (see CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE) and CHAPTER 34
ELECTRICAL SPECIFICATIONS (L GRADE)).
Remarks 1. fMCK: Operation clock frequency of target channel
fCLK: System clock frequency
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), mn = 00, 01, 10
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(1) Register setting
Figure 12-58. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O
(CSI00, CSI01, CSI10)
(a) Serial output register m (SOm) …The register that not used in this mode.
15
14
13
12
11
10
0
0
0
0
0
0
SOm
9
8
7
6
5
4
3
2
0
0
0
0
0
0
CKOm1 CKOm0
1
0
SOm.1 SOm.0
1
0
(b) Serial output enable register m (SOEm) …The register that not used in this mode.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm
SOEm.1 SOEm.0
1
0
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
SSm.1
SSm.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1
0/1
8
7
6
5
4
3
2
1
0
1
0
0
SSm
(d) Serial mode register mn (SMRmn)
15
SMRmn
14
13
12
11
10
9
0
0
0
0
0
CKSmn CCSmn
0/1
1
STSmn
0
SISmn0
0
MDmn2 MDmn1 MDmn0
0
0
0
0
Interrupt sources of channel n
0: Transfer end interrupt
(e) Serial communication operation setting register mn (SCRmn)
15
SCRmn
14
13
12
11
10
0
0
TXEmn RXEmn DAPmn CKPmn
0
1
0/1
0/1
9
8
7
6
PTCmn1 PTCmn0 DIRmn
0
5
4
3
2
1
0
SLCmn1 SLCmn0 DLSmn3 DLSmn2 DLSmn1 DLSmn0
0
0/1
0
0
0
0/1
0/1
0/1
0/1
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
(f) Serial data register mn (SDRmn)
(i) When operation is stopped (SEm.n = 0)
15
SDRmn
Remark
14
13
12
11
10
0000000
Baud rate setting
9
: Setting is fixed in the CSI slave reception mode,
: Setting disabled (set to the initial value)
: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
n: Channel number (n = 0, 1)
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Figure 12-58. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O
(CSI00, CSI01, CSI10) (2/2)
(ii) During operation (SEm.n = 1) (lower 8 bits: SDRmnL)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Receive data register
SDRmn
SDRmnL
Remark
: Setting is fixed in the CSI slave reception mode,
: Setting disabled (set to the initial value)
: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
n: Channel number (n = 0, 1)
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(2) Operation procedure
Figure 12-59. Initial Setting Procedure for Slave Reception
Starting initial settings
Setting the PER0 register
Setting the SPSm register
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Setting the SMRmn register
Set an operation mode, etc.
Setting the SCRmn register
Set a communication format.
Setting the SDRmn register
Set bits 15 to 9 to 0000000B for baud
rate setting.
Enable data input and clock input of the
Setting port
target channel by setting a port register
and a port mode register.
Set 1 to the PMxx register to use the
SCKp and SIp pins as input.
Set the SSm.n bit of the target channel to 1
Writing to the SSm register
and set the SEm.n bit to 1 (to enable
operation).
Starting communication
Caution
Wait for a clock from the master.
After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial
clock select register m (SPSm) after 4 or more fCLK clocks have elapsed.
Figure 12-60. Procedure for Stopping Slave Reception
Starting setting to stop
Setting the STm register
Write 1 to the STm.n bit of the target
channel.
Stop communication in midway.
Stopping communication
Check TSF when stopping
communication after confirming
completion of data transmission.
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Figure 12-61. Procedure for Resuming Slave Reception
Starting setting for resumption
Stop the target for communication or
Manipulating target for communication
wait until the target completes its
Disable clock output of the target
Port manipulation
(Essential)
channel by setting a port register and a
port mode register.
(Selective)
Changing setting of the SPSm register
(Selective)
Changing setting of the SMRmn register
(Selective)
Changing setting of the SCRmn register
Re-set the register to change the
operation clock setting.
Re-set the register to change serial
mode register mn (SMRmn) setting.
Re-set the register to change serial
communication operation setting register
mn (SCRmn) setting.
If the FEF, PEF, and OVF flags remain
(Selective)
Clearing error flag
set, clear them using serial flag clear
trigger register mn (SIRmn).
Enable data input and clock input of the
(Essential)
Port manipulation
target channel by setting a port register
and a port mode register.
Set 1 to the PMxx register to use the
SCKp and SIp pins as input.
(Essential)
Writing to the SSm register
Set the SSm.n bit of the target channel to
1 and set the SEm.n bit to 1 (to enable
operation).
(Essential)
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Wait for a clock from the master.
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Processing flow (in single-reception mode)
Figure 12-62. Timing Chart of Slave Reception (in Single-Reception Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
STmn
SEmn
SDRmn
Read
Receive data 3
Receive data 2
Receive data 1
Read
Read
SCKp pin
SIp pin
Shift
register mn
INTCSIp
Receive data 1
Reception & shift operation
Data reception (8-bit length)
Receive data 2
Reception & shift operation
Data reception (8-bit length)
Receive data 3
Reception & shift operation
Data reception (8-bit length)
TSFmn
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1),
p: CSI number (p = 00, 01, 10), mn = 00, 01, 10
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Figure 12-63. Flowchart of Slave Reception (in Single-Reception Mode)
Starting CSI
Setting the SAUmEN bit of
the PER0 register to 1
Setting transfer rate by the
SPSm register
Specify the initial settings while the SEm.n bit of
SMRmn, SCRmn: Setting communication
serial channel enable status register m (SEm) is 0
SDRmn[15:9]: Setting 0000000B
(operation is stopped).
Port manipulation
Writing 1 to the SSm.n bit
Starting reception
Transfer end interrupt
generated?
No
Yes
Reading the SDRmn
register
No
Reception completed?
Yes
Writing 1 to the STm.n bit
Clearing the SAUmEN bit of
the PER0 register to 0
End of communication
Caution
After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial
clock select register m (SPSm) after 4 or more fCLK clocks have elapsed.
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12.5.6 Slave transmission/reception
Slave transmission/reception is that the RL78/D1A transmits/receives data to/from another device in the state of a
transfer clock being input from another device.
3-Wire Serial I/O
CSI00
CSI01
CSI10
Target channel
Channel 0 of SAU0
Channel 1 of SAU0
Channel 0 of SAU1
Pins used
SCK00, SI00, SO00
SCK01, SI01, SO01
SCK10, SI10, SO10
Interrupt
INTCSI00
INTCSI01
INTCSI10
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can
be selected.
Error detection flag
Overrun error detection flag (OVFmn) only
Transfer data length
7 to 16 bits
Transfer rate
Max. fMCK/6 [Hz]
Data phase
Selectable by the DAPmn bit of the SCRmn register
Notes 1, 2
.
DAPmn = 0: Data I/O starts from the start of the serial clock operation.
DAPmn = 1: Data I/O starts half a clock before the start of the serial clock operation.
Clock phase
Selectable by the CKPmn bit of the SCRmn register
CKPmn = 0: Not reversed
CKPmn = 1: Reversed
Data direction
MSB or LSB first
Notes 1. Because the external serial clock input to the SCK00, SCK01, and SCK10 pins is sampled internally and
used, the fastest transfer rate is fMCK/6 [Hz]. Set the SPSm register so that fMCK/6 [Hz] equals fSCK or more
that is set with the SDRm register.
2. Use this operation within a range that satisfies the conditions above and the AC characteristics in the
electrical specifications (see CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE) and CHAPTER 34
ELECTRICAL SPECIFICATIONS (L GRADE)).
Remarks 1. fMCK: Operation clock frequency of target channel
fCLK: System clock frequency
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), mn = 00, 01, 10
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(1) Register setting
Figure 12-64. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O
(CSI00, CSI01, CSI10) (1/2)
(a) Serial output register m (SOm) … Sets only the bits of the target channel.
15
14
13
12
11
10
0
0
0
0
0
0
SOm
9
8
7
6
5
4
3
2
0
0
0
0
0
0
CKOm1 CKOm0
1
0
SOm.1 SOm.0
0/1
0/1
(b) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm
1
0
SOEm.1 SOEm.0
0/1
0/1
1
0
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
SSm.1
SSm.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1
0/1
8
7
6
5
4
3
2
1
0
1
0
0
SSm
(d) Serial mode register mn (SMRmn)
15
SMRmn
14
13
12
11
10
9
0
0
0
0
0
CKSmn CCSmn
0/1
1
STSmn
0
SISmn0
0
MDmn2 MDmn1 MDmn0
0
0
0
0/1
Interrupt sources of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
(e) Serial communication operation setting register mn (SCRmn)
15
SCRmn
14
13
12
11
10
0
0
TXEmn RXEmn DAPmn CKPmn
1
1
0/1
0/1
9
8
7
6
PTCmn1 PTCmn0 DIRmn
0
5
4
3
2
1
0
SLCmn1 SLCmn0 DLSmn3 DLSmn2 DLSmn1 DLSmn0
0
0/1
0
0
0
0/1
0/1
0/1
0/1
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
(f) Serial data register mn (SDRmn)
(i) When operation is stopped (SEm.n = 0)
15
14
SDRmn
Remark
13
12
11
10
0000000
Baud rate setting
9
: Setting is fixed in the CSI slave transmission/reception mode,
: Setting disabled (set to the initial
value)
: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
n: Channel number (n = 0, 1)
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Figure 12-64. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O
(CSI00, CSI01, CSI10) (2/2)
(ii) During operation (SEm.n = 1) (lower 8 bits: SDRmnL)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Transmit data register/receive data register
SDRmn
SDRmnL
Caution Be sure to set transmit data to the SDRmnL register before the clock from the master is started.
Remark
: Setting is fixed in the CSI slave transmission/reception mode,
: Setting disabled (set to the initial
value)
: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
n: Channel number (n = 0, 1)
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(2) Operation procedure
Figure 12-65. Initial Setting Procedure for Slave Transmission/Reception
Starting initial setting
Setting the PER0 register
Release the serial array unit from the reset
status and start clock supply.
Setting the SPSm register
Set the operation clock.
Setting the SMRmn register
Set an operation mode, etc.
Setting the SCRmn register
Set a communication format.
Setting the SDRmn register
Set bits 15 to 9 to 0000000B for baud rate setting.
Setting the SOm register
Changing setting of
Set the initial output level of the serial data (SOm.n).
Set the SOEm.n bit to 1 and enable data
output of the target channel.
the SOEm register
Disable data output of the target channel by setting
Setting port
a port register and a port mode register.
Writing to the SSm register
the SEm.n bit to 1 (to enable operation).
Set the SSm.n bit of the target channel to 1 and set
Starting communication
Set transmit data to the SDRmn register and wait
for a clock from the master.
Cautions 1. After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial
clock select register m (SPSm) after 4 or more fCLK clocks have elapsed.
2. Be sure to set transmit data to the SDR register before the clock from the master is started.
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Figure 12-66. Procedure for Stopping Slave Transmission/Reception
Starting setting to stop
Setting the STm register
Write 1 to the STm.n bit of the target
channel.
Changing setting of
Set the SOEm.n bit to 0 and stop the
the SOEm register
output of the target channel.
Stopping communication
Stop communication in midway.
Check TSF when stopping communication
after confirming completion of data
transmission.
Remark
Even after communication is stopped, the pin level is retained. To resume the operation, re-set serial
output register m (SOm) (see Figure 12-67 Procedure for Resuming Slave Transmission/
Reception).
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Figure 12-67. Procedure for Resuming Slave Transmission/Reception
Starting setting for resumption
(Essential)
(Essential)
Manipulating target
Stop the target for communication or wait until the
for communication
target completes its operation.
Port manipulation
Disable data output of the target channel by setting a
port register and a port mode register.
Changing setting of
Re-set the register to change the operation clock
the SPSm register
setting.
(Selective)
(Selective)
(Selective)
(Selective)
Changing setting of
Re-set the register to change serial mode register
the SMRmn register
mn (SMRmn) setting.
Changing setting of
Re-set the register to change serial communication
the SCRmn register
operation setting register mn (SCRmn) setting.
Clearing error flag
If the FEF, PEF, and OVF flags remain set, clear
them using serial flag clear trigger register mn
(SIRmn).
(Selective)
(Selective)
Changing setting of
Set the SOEm.n bit to 0 to stop output from the target
the SOEm register
channel.
Changing setting of
Set the initial output level of the serial data (SOm.n).
the SOm register
(Selective)
Changing setting of
Set the SOEm.n bit to 1 and enable output from the
the SOEm register
target channel.
Enable serial data output of the target channel by setting a
(Essential)
Port manipulation
port register and a port mode register.
Set input mode with the port mode register and set PMXx to
0 to use the SOp pins as output.
Set 1 to the PMXx register to use the SCKp and SIp pins as
input.
(Essential)
Writing to the SSm register
(Essential)
Starting communication
(Essential)
Starting target for communication
Set the SSm.n bit of the target channel to 1 and set the
SEm.n bit to 1 (to enable operation).
Sets transmit data to the SDRmn register and wait for a
clock from the master.
Starts the target for communication.
Caution Be sure to set transmit data to the SDR register before the clock from the master is started.
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(3) Processing flow (in single-transmission/reception mode)
Figure 12-68. Timing Chart of Slave Transmission/Reception (in Single-Transmission/Reception Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
STmn
SEmn
Receive data 1
SDRmn
Transmit data 1
Write
Receive data 2
Receive data 3
Transmit data 3
Transmit data 2
Write
Read
Write
Read
Read
SCKp pin
SIp pin
Shift
register mn
SOp pin
Receive data 1
Reception & shift operation
Transmit data 1
Receive data 2
Reception & shift operation
Transmit data 2
Receive data 3
Reception & shift operation
Transmit data 3
INTCSIp
Data transmission/reception (8-bit length)
Data transmission/reception (8-bit length)
Data transmission/reception (8-bit length)
TSFmn
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1),
p: CSI number (p = 00, 01, 10), mn = 00, 01, 10
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Figure 12-69. Flowchart of Slave Transmission/Reception (in Single- Transmission/Reception Mode)
Starting CSI communication
Setting the SAUmEN bit of
the PER0 register to 1
Setting transfer rate by
the SPSm register
SMRmn, SCRmn: Setting communication
Specify the initial settings while the SEm.n bit of
SDRmn[15:9]: Setting 0000000B
serial channel enable status register m (SEm) is 0
SOm, SOEm: Setting output
(operation is stopped).
Port manipulation
Writing 1 to the SSm.n bit
Writing transmit data to
SDRmn
Starting
Transfer end interrupt
generated?
No
Yes
Reading the SDRmn
register
Transmission/reception
completed?
No
Yes
Writing 1 to the STm.n bit
Clearing the SAUmEN bit of
the PER0 register to 0
End of communication
Cautions 1.
After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial
clock select register m (SPSm) after 4 or more fCLK clocks have elapsed.
2.
Be sure to set transmit data to the SDR register before the clock from the master is started.
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(4) Processing flow (in continuous transmission/reception mode)
Figure 12-70. Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
STmn
SEmn
SDRmn
Transmit data 2
Transmit data 1
Write
Write
Receive data 3
Receive data 2
Transmit data 3
Write
Read
Receive data 1
Read
Read
SCKp pin
SIp pin
Receive data 2
Receive data 1
Shift
register mn
SOp pin
Reception & shift operation
Receive data 3
Reception & shift operation
Reception & shift operation
Transmit data 1
Transmit data 2
Transmit data 3
INTCSIp
Data transmission/reception (8-bit length)
Data transmission/reception (8-bit length)
Data transmission/reception (8-bit length)
MDmn0
TSFmn
BFFmn
(Note 1)
(Note 2)
(Note 2)
Notes 1. If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn
(SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten.
2. The transmit data can be read by reading the SDRmn register during this period. At this time, the
transfer operation is not affected.
Caution
The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it has been rewritten before
the transfer end interrupt of the last transmit data.
Remarks 1. to in the figure correspond to to in Figure 12-71
Flowchart of Slave
Transmission/Reception (in Continuous Transmission/Reception Mode).
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1),
p: CSI number (p = 00, 01, 10), mn = 00, 10, 11
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Figure 12-71. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode)
Starting CSI communication
Setting the SAUmEN bit
of the PER0 register to 1
Setting transfer rate by
the SPSm register
Select the buffer empty
interrupt.
SMRmn, SCRmn: Setting communication
Specify the initial settings while the SEm.n bit of
SDRmn[15:9]: Setting 0000000B
serial channel enable status register m (SEm) is 0
SOm, SOEm: Setting output
(operation is stopped).
Port manipulation
Writing 1 to the SSm.n bit
Writing transmit data to
SDRmn
Buffer empty
interrupt generated?
No
Yes
Reading receive data to
SDRmn
Communication data
exists?
Yes
No
No
Writing 0 to the MDmn0
TSFmn = 1?
Yes
Transfer end
interrupt generated?
No
Yes
Yes
Reading receive data to
SDRmn
Communication
No
Writing 1 to the MDmn0
bit
Writing 1 to the STm.n bit
Clearing the SAUmEN bit
of the PER0 register to 0
End of communication
Cautions 1.
After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial
clock select register m (SPSm) after 4 or more fCLK clocks have elapsed.
2.
Remark
Be sure to set transmit data to the SDR register before the clock from the master is started.
to in the figure correspond to to in Figure 12-70
Timing Chart of Slave
Transmission/Reception (in Continuous Transmission/Reception Mode).
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12.5.7 Calculating transfer clock frequency
The transfer clock frequency for 3-wire serial I/O (CSI00, CSI01, CSI10) communication can be calculated by the
following expressions.
(1) Master
(Transfer clock frequency) = {Operation clock (fMCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) 2 [Hz]
(2) Slave
(Transfer clock frequency) = {Frequency of serial clock (SCK) supplied by master}Note
[Hz]
Note The permissible maximum transfer clock frequency is fMCK/6.
Remark The value of SDRmn[15:9] is the value of bits 15 to 9 of serial data register mn (SDRmn) (0000000B to
1111111B) and therefore is 0 to 127.
The operation clock (fMCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode
register mn (SMRmn).
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Table 12-2. Selection of Operation Clock For 3-Wire Serial I/O
SMRmn
Register
SPSm Register
CKSmn
PRS PRS PRS PRS PRS PRS PRS PRS
m13 m12 m11 m10 m03 m02 m01 m00
0
1
X
X
X
X
0
0
0
0
Note
fCLK = 32 MHz
fCLK
32 MHz
X
X
X
X
0
0
0
1
fCLK/2
X
X
X
X
0
0
1
0
fCLK/2
2
8 MHz
X
X
X
X
0
0
1
1
fCLK/2
3
4 MHz
X
X
X
X
0
1
0
0
fCLK/2
4
2 MHz
X
X
X
X
0
1
0
1
fCLK/2
5
16 MHz
1 MHz
500 kHz
X
X
X
X
0
1
1
0
fCLK/2
6
X
X
X
X
0
1
1
1
fCLK/2
7
250 kHz
125 kHz
62.5 kHz
X
X
X
X
1
0
0
0
fCLK/2
8
X
X
X
X
1
0
0
1
fCLK/2
9
31.25 kHz
15.63 kHz
X
X
X
X
1
0
1
0
fCLK/2
10
X
X
X
X
1
0
1
1
fCLK/2
11
0
0
0
0
X
X
X
X
fCLK
0
0
0
1
X
X
X
X
fCLK/2
32 MHz
16 MHz
0
0
1
0
X
X
X
X
fCLK/2
2
0
0
1
1
X
X
X
X
fCLK/2
3
4 MHz
0
1
0
0
X
X
X
X
fCLK/2
4
2 MHz
1 MHz
8 MHz
0
1
0
1
X
X
X
X
fCLK/2
5
0
1
1
0
X
X
X
X
fCLK/2
6
500 kHz
250 kHz
125 kHz
0
1
1
1
X
X
X
X
fCLK/2
7
1
0
0
0
X
X
X
X
fCLK/2
8
62.5 kHz
1
0
0
1
X
X
X
X
fCLK/2
9
1
0
1
0
X
X
X
X
fCLK/2
10
31.25 kHz
1
0
1
1
X
X
X
X
fCLK/2
11
15.63 kHz
Other than the above
Note
Operation Clock (fMCK)
Setting prohibited
Stop the operation of the serial array unit (SAU) (by setting bits 3 to 0 of ST0 register and bits 1 and 0 of
ST1 and STS register to 1) before changing operation clock (fCLK) selection (by changing the system clock
control register (CKC) value).
Remarks 1. X: Don’t care
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), mn = 00, 10, 11
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12.5.8 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10) communication
The procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10) communication is
described in Figure 12-72.
Figure 12-72. Processing Procedure in Case of Overrun Error
Software Manipulation
Hardware Status
Remark
Reads serial data register mn (SDRmn).
The BFFmn bit of the SSRmn register is
This is to prevent an overrun error if the
set to 0 and channel n is enabled to
receive data.
next reception is completed during error
processing.
Reads serial status register mn
(SSRmn).
Writes 1 to serial flag clear trigger
register mn (SIRmn).
Error type is identified and the read
value is used to clear error flag.
Error flag is cleared.
Error can be cleared only during
reading, by writing the value read from
the SSRmn register to the SIRmn
register without modification.
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), mn = 00, 10, 11
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12.6 Operation of UART (UART0) Communication
This is a start-stop synchronization function using two lines: serial data transmission (TXD) and serial data reception
(RXD) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and
stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other
communication party. Full-duplex UART communication can be performed by using a channel dedicated to transmission
(even-numbered channel) and a channel dedicated to reception (odd-numbered channel).
[Data transmission/reception]
Data length of 7, 8, 9 or 16 bits (UART0)
Select the MSB/LSB first
Level setting of transmit/receive data and select of reverse
Parity bit appending and parity check functions
Stop bit appending
[Interrupt function]
Transfer end interrupt/buffer empty interrupt
[Error detection flag]
Framing error, parity error, or overrun error
UART0 uses channels 0 and 1 of SAU0.
128-pin products
0
1
2
Used as CSI
Used as UART
Used as Simplified I C
0
CSI00
UART0
1
CSI01
0
CSI10
1
Unit
Channel
IIC11
UART performs the following four types of communication operations.
UART transmission
(See 12.6.1.)
UART reception
(See 12.6.2.)
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12.6.1 UART transmission
UART transmission is an operation to transmit data from the RL78/D1A to another device asynchronously (start-stop
synchronization).
Of two channels used for UART, the even channel is used for UART transmission.
UART
UART0
Target channel
Channel 0 of SAU0
Pins used
TxD0
Interrupt
INTST0
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Error detection flag
None
Transfer data length
7, 8, 9 or 16 bits
Transfer rate
Max. fMCK/6 [bps] (SDRmn [15:9] = 3 or more), Min. fCLK/(2 2 128) [bps]
Data phase
Non-reverse output (default: high level)
Reverse output (default: low level)
Parity bit
The following selectable
11
Note
No parity bit
Appending 0 parity
Appending even parity
Appending odd parity
Stop bit
The following selectable
Appending 1 bit
Appending 2 bits
Data direction
MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE) and CHAPTER 34 ELECTRICAL
SPECIFICATIONS (L GRADE)).
Remarks 1. fMCK:
fCLK:
Operation clock frequency of target channel
System clock frequency
2. m: Unit number (m = 0), n: Channel number (n = 0), mn = 00
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(1) Register setting
Figure 12-73. Example of Contents of Registers for UART Transmission of UART
(UART0) (1/2)
(a) Serial mode register mn (SMRmn)
15
SMRmn
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
1
0
0
CKSmn CCSmn
0/1
0
2
1
0
MDmn2 MDmn1 MDmn0
Operation clock (fMCK) of channel n
0: Prescaler output clock CKm0 set by the SPSm register
1: Prescaler output clock CKm1 set by the SPSm register
0
1
0/1
Interrupt source of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
(b) Serial communication operation setting register mn (SCRmn)
15
SCRmn
14
13
12
11
TXEmn RXEmn DAPmn CKPmn
1
0
0
0
10
9
8
7
6
EOCmn PTCmn1 PTCmn0 DIRmn
0
0
0/1
0/1
0/1
5
4
2
1
0
SLCmn1 SLCmn0 DLSmn3 DLSmn2 DLSmn1 DLSmn0
0
0/1
0/1
0/1
0/1
0/1
0/1
Setting of stop bit
01B: Appending 1 bit
10B: Appending 2 bits
Setting of parity bit
00B: No parity
01B: Appending 0 parity
10B: Appending Even parity
11B: Appending Odd parity
3
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first.
(c) Serial data register mn (SDRmn) (lower 8 bits: TXDq)
15
14
13
SDRmn
12
11
10
9
8
Baud rate setting
0
7
6
5
4
3
2
1
0
1
0
Transmit data setting
Note
TXDq
(d) Serial output level register m (SOLm) … Sets only the bits of the target channel.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
0
0
0
SOLm
2
SOLm.2
0/1
SOLm.0
0
0/1
0: Forward (normal) transmission
1: Reverse transmission
Note
When UART0 performs 9-bit communication (by setting the DLS001 and DLS000 bits of the SCR00
register to 0 and 1, respectively), bits 0 to 8 of the SDR00 register are used as the transmission data
specification area. Only UART0 can be used to perform 9-bit communication.
Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0), q: UART number (q = 0),
mn = 00
2.
: Setting is fixed in the UART transmission mode,
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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Figure 12-73. Example of Contents of Registers for UART Transmission of UART
(UART0) (2/2)
(e) Serial output register m (SOm) … Sets only the bits of the target channel.
15
14
13
12
11
10
0
0
0
0
0
0
SOm
9
8
7
6
5
4
3
2
0
0
0
0
0
0
CKOm1 CKOm0
1
0
SOm1
SOm0
0/1Note
0: Serial data output value is “0”
1: Serial data output value is “1”
(f) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm
1
0
SOEm1 SOEm0
0/1
1
0
SSm1
SSm0
0/1
(g) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSm
Note
Before transmission is started, be sure to set to 1 when the SOLmn bit of the target channel is set to 0,
and set to 0 when the SOLmn bit of the target channel is set to 1. The value varies depending on the
communication data during communication operation.
Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0), q: UART number (q = 0)
mn = 00
2.
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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(2) Operation procedure
Figure 12-74. Initial Setting Procedure for UART Transmission
Starting initial setting
Setting the PER0 register
Setting the SPSm register
Release the serial array unit from the reset status and
start clock supply.
Set the operation clock.
Setting the SMRmn register
Set an operation mode, etc.
Setting the SCRmn register
Set a communication format.
Setting the SDRmn register
Changing setting of
Set a transfer baud rate (setting the transfer clock by
dividing the operation clock (fMCK)).
Set an output data level.
the SOLm register
Setting the SOm register
Set the initial output level of the serial data (SOmn).
Changing setting of
Set the SOEmn bit to 1 and enable data output of the
the SOEm register
target channel.
Enable data output of the target channel by setting a port
Setting port
register and a port mode register.
Set PM10 to “1” to use the P10 pin as the SO00/TxD0 output.
Writing to the SSm register
Set the SSmn bit of the target channel to 1 and set the
SEm.n bit to 1 (to enable operation).
Starting communication
Set transmit data to the TxDq or SDRmn register and start
communication.
Caution
After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial
clock select register m (SPSm) after 4 or more fCLK clocks have elapsed.
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Figure 12-75. Procedure for Stopping UART Transmission
Starting setting to stop
Setting the STm register
Write 1 to the STmn bit of the target channel.
Setting the SOEm register
Set the SOEm.n bit to 0 and stop the output.
Stopping communication
Remark
Stop communication in midway.
Even after communication is stopped, the pin level is retained. To resume the operation, re-set serial
output register m (SOm) (see Figure 12-76 Procedure for Resuming UART Transmission).
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Figure 12-76. Procedure for Resuming UART Transmission
Starting setting for
Disable data output of the target channel by
(Essential)
Port manipulation
setting a port register and a port mode
register. To use the P12 pin as the SO00/TxD0
output, set PM12 to “1”.
(Selective)
Changing setting of the SPSm
register
(Selective)
Changing setting of the
Re-set the register to change the operation
clock setting.
Re-set the register to change the transfer
baud rate setting (setting the transfer clock
by dividing the operation clock (fMCK)).
(Selective)
Changing setting of the
Re-set the register to change serial mode
register mn (SMRmn) setting.
SMRmn
Re-set the register to change the serial
(Selective)
Changing setting of the
SCRmn
Changing setting of the SOLm
(Selective)
register
Changing setting of the SOEm
(Essential)
mn (SCRmn) setting.
Re-set the register to change serial output
level register m (SOLm) setting.
Clear the SOEm.n bit to 0 and stop output.
register
Changing setting of the SOm
(Essential)
register
(Essential)
communication operation setting register
Changing setting of the SOEm
Set the initial output level of the serial data
(SOm.n).
Set the SOEm.n bit to 1 and enable output.
register
Enable data output of the target channel by
(Essential)
Port manipulation
setting a port register and a port mode register.
Set PM12 to “1” to use the P12 pin as the
SO00/TxD0 output.
(Essential)
Writing to the SSm register
Set the SSmn bit of the target channel to 1 and
set the SEmn bit to 1 (to enable operation).
(Essential)
Starting communication
Sets transmit data to the TxDq or SDRmn
register and start communication.
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(3) Processing flow (in single-transmission mode)
Figure 12-77. Timing Chart of UART Transmission (in Single-Transmission Mode)
SSm.n
STm.n
SEm.n
SDRmn
TxDq pin
Shift
register mn
Transmit data 1
ST
Transmit data 1
Transmit data 2
P SP
Shift operation
ST
Transmit data 2
Transmit data 3
P SP
Shift operation
ST
Transmit data 3
P SP
Shift operation
INTSTq
Data transmission (7-bit length)
Data transmission (7-bit length)
Data transmission (7-bit length)
TSFmn
Remark
m: Unit number (m = 0), n: Channel number (n = 0), q: UART number (q = 0)
mn = 00
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Figure 12-78. Flowchart of UART Transmission (in Single-Transmission Mode)
Starting UART communication
Setting the SAUmEN bit of
the PER0 register to 1
Setting operation clock by
the SPSm register
SMRmn, SCRmn: Setting communication
Specify the initial settings while the SEmn bit of
serial channel enable status register m (SEm) is 0
(operation is stopped).
SDRmn[15:9]: Setting transfer rate
SOLmn: Setting output data level
SOm, SOEm: Setting output
Port manipulation
Writing 1 to the SSm.n bit
Writing transmit data to
TxDq or SDRmn
Transfer end interrupt
generated?
No
Yes
No
Transmission
Yes
Writing 1 to the STm.n bit
Clearing the SAUmEN bit of
the PER0 register to 0
End of communication
Caution
After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial
clock select register m (SPSm) after 4 or more fCLK clocks have elapsed.
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(4) Processing flow (in continuous transmission mode)
Figure 12-79. Timing Chart of UART Transmission (in Continuous Transmission Mode)
SSm.n
STm.n
SEm.n
SDRmn
Transmit data 1
TxDq pin
ST
Transmit data 1
Shift
register mn
Transmit data 3
Transmit data 2
P SP ST
Shift operation
Transmit data 2
P SP ST
Shift operation
Transmit data 3
P
SP
Shift operation
INTSTq
Data transmission (7-bit length)
Data transmission (7-bit length)
Data transmission (7-bit length)
MDmn0
TSFmn
BFFmn
(Note)
Note If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is
1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten.
Caution
The MDmn0 bit of serial mode register mn (SSRmn) can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it will be rewritten before the
transfer end interrupt of the last transmit data.
Remark
m: Unit number (m = 0), n: Channel number (n = 0), q: UART number (q = 0)
mn = 00
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Figure 12-80. Flowchart of UART Transmission (in Continuous Transmission Mode)
Starting UART
Setting the SAUmEN bit of
the PER0 register to 1
Setting operation clock by
the SPSm register
Select the buffer empty interrupt.
SMRmn, SCRmn: Setting communication
Specify the initial settings while the SEm.n
SDRmn[15:9]: Setting transfer rate
bit of serial channel enable status register
m (SEm) is 0 (operation is stopped).
SOLmn: Setting output data level
SOm, SOEm: Setting output
Port manipulation
Writing 1 to the SSm.n bit
Writing transmit data to
TxDq or SDRmn
No
Buffer empty interrupt
generated?
Yes
Yes
Transmitting next data?
No
Clearing 0 to the MDmn0 bit
No
TSFmn = 1?
Yes
No
Transfer end interrupt
generated?
Yes
Yes
Communication
No
Writing 1 to the MDmn0 bit
Writing 1 to the STm.n bit
Clearing the SAUmEN bit of
the PER0 register to 0
End of communication
Caution After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial
clock select register m (SPSm) after 4 or more fCLK clocks have elapsed.
Remark
to in the figure correspond to to in Figure G-79
Timing Chart of UART
Transmission (in Continuous Transmission Mode).
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12.6.2 UART reception
UART reception is an operation wherein the RL78/D1A asynchronously receives data from another device (start-stop
synchronization).
For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both
the odd- and even-numbered channels must be set.
UART
UART0
Target channel
Channel 1 of SAU0
Pins used
RxD0
Interrupt
INTSR0
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error interrupt
None
Error detection flag
Framing error detection flag (FEFmn)
Parity error detection flag (PEFmn)
Overrun error detection flag (OVFmn)
Transfer data length
7, 8, 9 or 16 bits
Transfer rate
Max. fMCK/6 [bps] (SDRmn [15:9] = 3 or more),
Min. fCLK/(2 2 128) [bps]
11
Data phase
Note
Forward output (default: high level)
Reverse output (default: low level)
Parity bit
The following selectable
No parity bit (no parity check)
Appending 0 parity (no parity check)
Appending even parity
Appending odd parity
Stop bit
Appending 1 bit
Data direction
MSB or LSB first
Note
Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE) and CHAPTER 34 ELECTRICAL
SPECIFICATIONS (L GRADE)).
Remarks 1. fMCK: Operation clock frequency of target channel
fCLK:
System clock frequency
2. m: Unit number (m = 0), n: Channel number (n = 1), mn = 01
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(1) Register setting
Figure 12-81. Example of Contents of Registers for UART Reception of UART
(UART0) (1/2)
(a) Serial mode register mn (SMRmn)
15
SMRmn
14
13
12
11
10
9
0
0
0
0
0
0
7
STSmn
CKSmn CCSmn
0/1
8
Operation clock (fMCK) of
channel n
0: Prescaler output clock
CKm0
set by the SPSm register
1: Prescaler output clock
CKm1
set by the SPSm register
6
5
4
3
1
0
0
2
SISmn0
1
0
1
0
MDmn2 MDmn1 MDmn0
0/1
0: Forward (normal) reception
1: Reverse reception
0
1
0
Operation mode of channel n
0: Transfer end interrupt
(b) Serial mode register mr (SMRmr)
15
SMRmr
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
1
0
0
2
CKSmr CCSmr
0/1
0
1
0
MDmr2 MDmr1 MDmr0
Same setting value as CKSmn
bit
0
1
0/1
Operation mode of channel r
0: Transfer end interrupt
1: Buffer empty interrupt
(c) Serial communication operation setting register mn (SCRmn)
15
SCRmn
14
13
12
11
TXEmn RXEmn DAPmn CKPmn
0
1
0
0
10
9
8
7
6
EOCmn PTCmn1 PTCmn0 DIRmn
0
1
0/1
0/1
0/1
5
4
3
2
1
0
SLCmn1 SLCmn0 DLSmn3 DLSmn2 DLSmn1 DLSmn0
0
0
1
0/1
0/1
0/1
0/1
Setting of parity bit
00B: No parity
01B: No parity judgment
10B: Appending Even parity
11B: Appending Odd parity
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first.
Setting of data length
(d) Serial data register mn (SDRmn) (lower 8 bits: RXDq)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SDRmn
Baud rate setting
Notes
Caution
Receive data register
0 Note
RXDq
When UART0 performs 9-bit communication (by setting the DLS011 and DLS010 bits of the SMR01
register to 1), bits 0 to 8 of the SDR01 register are used as the transmission data specification area.
Only UART0 can be used to perform 9-bit communication.
For the UART reception, be sure to set the SMRmr register of channel r that is to be paired with
channel n.
Remarks 1. m: Unit number (m = 0), n: Channel number (n = 1), mn = 01
r: Channel number (r = n 1), q: UART number (q = 0)
2.
: Setting is fixed in the UART reception mode,
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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Figure 12-81. Example of Contents of Registers for UART Reception of UART
(UART0) (2/2)
(e) Serial output register m (SOm) … The register that not used in this mode.
15
14
13
12
11
10
0
0
0
0
0
0
SOm
9
8
7
6
5
4
3
2
0
0
0
0
0
0
CKOm1 CKOm0
1
0
SOm1
SOm0
1
0
(f) Serial output enable register m (SOEm) …The register that not used in this mode.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm
SOEm1 SOEm0
1
0
SSm1
SSm0
0/1
(g) Serial channel start register m (SSm) … Sets only the bits of the target channel is 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSm
Caution
For the UART reception, be sure to set the SMRmr register of channel r that is to be paired with
channel n.
Remarks 1. m: Unit number (m = 0), n: Channel number (n = 1), mn = 01
r: Channel number (r = n 1), q: UART number (q = 0)
2.
: Setting is fixed in the UART reception mode,
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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(2) Operation procedure
Figure 12-82. Initial Setting Procedure for UART Reception
Starting initial setting
Setting the PER0 register
Setting the SPSm register
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Setting the SMRmn and SMRmr
Set an operation mode, etc.
Setting the SCRmn register
Set a communication format.
Set a transfer baud rate (setting the
Setting the SDRmn register
transfer clock by dividing the operation
clock (fMCK)).
Set the SSmn bit of the target channel to 1 and
Writing to the SSm register
Starting communication
Caution
set the SEmn bit to 1 (to enable operation).
The start bit is detected.
After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial
clock select register m (SPSm) after 4 or more fCLK clocks have elapsed.
Figure 12-83. Procedure for Stopping UART Reception
Starting setting to stop
Setting the STm register
Stopping communication
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Write 1 to the STmn bit of the target
channel.
Stop communication in midway.
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Figure 12-84. Procedure for Resuming UART Reception
Starting setting for resumption
(Essential)
Manipulating target for
communication
Changing setting of the SPSm
(Selective)
register
Changing setting of the
(Selective)
SDRmn register
(Selective)
(Selective)
until the target completes its operation.
Re-set the register to change the operation
clock setting.
Re-set the register to change the transfer
baud rate setting (setting the transfer clock
by dividing the operation clock (fMCK)).
Changing setting of the
Re-set the registers to change serial mode
SMRmn
registers mn, mr (SMRmn, SMRmr) setting.
Changing setting of the SCRmn
(Selective)
Stop the target for communication or wait
register
Re-set the register to change serial
communication operation setting register
mn (SCRmn) setting.
If the FEF, PEF, and OVF flags remain
Clearing error flag
set, clear them using serial flag clear
trigger register mn (SIRmn).
(Essential)
Writing to the SSm register
(Essential)
Starting communication
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Set the SSmn bit of the target channel to 1 and
set the SEmn bit to 1 (to enable operation).
The start bit is detected.
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(3) Processing flow
Figure 12-85. Timing Chart of UART Reception
SSm.n
STm.n
SEm.n
Receive data 3
SDRmn
RxDq pin
Shift
register mn
Receive data 2
Receive data 1
ST
Receive data 1
Shift operation
P SP
ST
Receive data 2
P SP
Shift operation
ST
Receive data 3
P SP
Shift operation
INTSRq
Data reception (7-bit length)
Data reception (7-bit length)
Data reception (7-bit length)
TSFmn
Remark
m: Unit number (m = 0), n: Channel number (n = 1), mn = 01
r: Channel number (r = n 1), q: UART number (q = 0)
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Figure 12-86. Flowchart of UART Reception
StartingUART comm unication
Setting the SAUm EN bit of
the PER0, PERx registers to 1
Setting transfer rate by
the SPSm regis ter
Specify the initial settings while the SEm.n bit
of serial channel enable status regist er
m (SEm) is 0 (operation is stoppe d).
SMRmn,SMRmr,SCRmn: Settingcommunication
SDRmn[15:9]: Settingtransferrate
Port manipulation
Writing 1 to the S S m.n bit
Detecting start bit
Starting reception
Transfer end interrupt
generated?
No
Yes
Error present?
Yes
No
Reading the R x Dq or
SDRmn register
R eception completed?
Error proces s ing
No
Yes
Writing 1 to the STm.n bit
Clearing the SAUmEN bit of
the PER0, PERx registers to 0
End of UART communication
Caution
After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial
clock select register m (SPSm) after 4 or more fCLK clocks have elapsed.
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12.6.3 Calculating baud rate
(1) Baud rate calculation expression
The baud rate for UART (UART0) communication can be calculated by the following expressions.
(Baud rate) = {Operation clock (fMCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [bps]
Caution
Setting serial data register mn (SDRmn) SDRmn[15:9] = (0000000B, 0000001B, 0000010B) is
prohibited in UART0.
Setting serial data register mn (SDRmn) SDRmn[15:9] = (0000000B, 0000001B) is prohibited in
UARTS0.
Remarks 1.
When UART0 is used, the value of SDRmn[15:9] is the value of bits 15 to 9 of the SDRmn
register (0000010B to 1111111B) and therefore is 2 to 127.
When UARTS0 is used, the value of SDRmn[15:9] is the value of bits 15 to 9 of the SDRmn
register (0000010B to 1111111B) and therefore is 2 to 127.
2.
m: Unit number (m = 0), n: Channel number (n = 0), mn = 00
The operation clock (fMCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial
mode register mn (SMRmn).
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Table 12-3. Selection of Operation Clock For UART
SMRmn
Register
SPSm Register
CKSmn
PRS PRS PRS PRS PRS PRS PRS PRS
m13 m12 m11 m10 m03 m02 m01 m00
0
1
Operation Clock (fMCK)
Note
fCLK = 32 MHz
X
X
X
X
0
0
0
0
fCLK
X
X
X
X
0
0
0
1
fCLK/2
32 MHz
16 MHz
X
X
X
X
0
0
1
0
fCLK/2
2
X
X
X
X
0
0
1
1
fCLK/2
3
4 MHz
2 MHz
8 MHz
X
X
X
X
0
1
0
0
fCLK/2
4
X
X
X
X
0
1
0
1
fCLK/2
5
1 MHz
X
X
X
X
0
1
1
0
fCLK/2
6
500 kHz
250 kHz
125 kHz
X
X
X
X
0
1
1
1
fCLK/2
7
X
X
X
X
1
0
0
0
fCLK/2
8
62.5 kHz
31.25 kHz
X
X
X
X
1
0
0
1
fCLK/2
9
X
X
X
X
1
0
1
0
fCLK/2
10
X
X
X
X
1
0
1
1
fCLK/2
11
0
0
0
0
X
X
X
X
fCLK
15.63 kHz
32 MHz
0
0
0
1
X
X
X
X
fCLK/2
0
0
1
0
X
X
X
X
fCLK/2
2
8 MHz
16 MHz
0
0
1
1
X
X
X
X
fCLK/2
3
4 MHz
0
1
0
0
X
X
X
X
fCLK/2
4
2 MHz
0
1
0
1
X
X
X
X
fCLK/2
5
1 MHz
500 kHz
0
1
1
0
X
X
X
X
fCLK/2
6
0
1
1
1
X
X
X
X
fCLK/2
7
250 kHz
125 kHz
62.5 kHz
1
0
0
0
X
X
X
X
fCLK/2
8
1
0
0
1
X
X
X
X
fCLK/2
9
31.25 kHz
15.63 kHz
1
0
1
0
X
X
X
X
fCLK/2
10
1
0
1
1
X
X
X
X
fCLK/2
11
Other than the above
Setting prohibited
Note When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), do
so after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array unit
(SAU).
Remarks 1.
2.
X: Don’t care
m: Unit number (m = 0), n: Channel number (n = 0), mn = 00
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(2) Baud rate error during transmission
The baud rate error of UART (UART0) communication during transmission can be calculated by the following
expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the
reception side.
(Baud rate error) = (Calculated baud rate value) ÷ (Target baud rate) 100 100 [%]
Here is an example of setting a UART baud rate at fCLK = 32 MHz.
UART Baud Rate
(Target Baud Rate)
fCLK = 32 MHz
Operation Clock (fMCK)
Calculated Baud Rate
Error from Target Baud Rate
103
300.48 bps
+0.16 %
103
600.96 bps
+0.16 %
7
103
1201.92 bps
+0.16 %
fCLK/2
6
103
2403.85 bps
+0.16 %
fCLK/2
5
103
4807.69 bps
+0.16 %
fCLK/2
4
103
9615.38 bps
+0.16 %
fCLK/2
3
103
19230.8 bps
+0.16 %
fCLK/2
3
63
31250.0 bps
0.0 %
38400 bps
fCLK/2
2
103
38461.5 bps
+0.16 %
76800 bps
fCLK/2
103
76923.1 bps
+0.16 %
153600 bps
fCLK
103
153846 bps
+0.16 %
312500 bps
fCLK
50
312500 bps
0.39 %
fCLK/2
9
600 bps
fCLK/2
8
1200 bps
fCLK/2
300 bps
2400 bps
4800 bps
9600 bps
19200 bps
31250 bps
Remark
SDRmn[15:9]
m: Unit number (m = 0), n: Channel number (n = 0), mn = 00
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(3) Permissible baud rate range for reception
The permissible baud rate range for reception during UART (UART0) communication can be calculated by the
following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate
range at the reception side.
2 k Nfr
(Maximum receivable baud rate) =
2 k Nfr k + 2
(Minimum receivable baud rate) =
2 k Nfr k 2
2 k (Nfr 1)
Brate
Brate
Brate: Calculated baud rate value at the reception side (See 12.6.3 (1) Baud rate calculation expression.)
k:
SDRmn[15:9] + 1
Nfr:
1 data frame length [bits]
= (Start bit) + (Data length) + (Parity bit) + (Stop bit)
Remark
m: Unit number (m = 0), n: Channel number (n = 1), mn = 01
Figure 12-87. Permissible Baud Rate Range for Reception (1 Data Frame Length = 11 Bits)
Latch
timing
Data frame length
of SAU
Start
bit
Bit 0
Bit 1
Bit 7
Parity
bit
Stop
bit
FL
1 data frame (11 ´ FL)
Permissible minimum
data frame length
Start
bit
Bit 0
Bit 1
Parity
bit
Bit 7
Stop
bit
(11 ´ FL) min.
Permissible maximum
data frame length
Start
bit
Bit 0
Bit 1
Bit 7
Parity
bit
Stop
bit
(11 ´ FL) max.
As shown in Figure 12-87, the timing of latching receive data is determined by the division ratio set by bits 15 to 9
of serial data register mn (SDRmn) after the start bit is detected. If the last data (stop bit) is received before this
latch timing, the data can be correctly received.
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12.6.4 Procedure for processing errors that occurred during UART (UART0) communication
The procedure for processing errors that occurred during UART (UART0) communication is described in Figures 12-88
and 12-89.
Figure 12-88. Processing Procedure in Case of Parity Error or Overrun Error
Software Manipulation
Hardware Status
Remark
Reads serial data register mn
The BFFmn bit of the SSRmn register
This is to prevent an overrun error if the
(SDRmn).
is set to 0 and channel n is enabled to
receive data.
next reception is completed during error
processing.
Reads serial status register mn
(SSRmn).
Writes 1 to serial flag clear trigger
register mn (SIRmn).
Error type is identified and the read
value is used to clear error flag.
Error flag is cleared.
Error can be cleared only during
reading, by writing the value read from
the SSRmn register to the SIRmn
register without modification.
Figure 12-89. Processing Procedure in Case of Framing Error
Software Manipulation
Hardware Status
Remark
Reads serial data register mn
The BFFmn bit of the SSRmn register
This is to prevent an overrun error if the
(SDRmn).
is set to 0 and channel n is enabled to
receive data.
next reception is completed during error
processing.
Reads serial status register mn
Error type is identified and the read
(SSRmn).
value is used to clear error flag.
Writes serial flag clear trigger register mn
Error flag is cleared.
(SIRmn).
Error can be cleared only during
reading, by writing the value read from
the SSRmn register to the SIRmn
register without modification.
Sets the STm.n bit of serial channel stop
The SEm.n bit of serial channel enable
register m (STm) to 1.
status register m (SEm) is set to 0 and
channel n stops operating.
Synchronization with other party of
Synchronization with the other party of
communication
communication is re-established and
communication is resumed because it is
considered that a framing error has
occurred because the start bit has been
shifted.
Sets the SSm.n bit of serial channel start
The SEm.n bit of serial channel enable
register m (SSm) to 1.
status register m (SEm) is set to 1 and
channel n is enabled to operate.
Remark
m: Unit number (m = 0), n: Channel number (n = 0), mn = 00
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12.7 Operation of Simplified I2C (IIC11) Communication
This is a clocked communication function to communicate with two or more devices by using two lines: serial clock
(SCL) and serial data (SDA). This communication function is designed to execute single communication with devices such
as EEPROM, flash memory, and A/D converter, and therefore, can be used only by the master.
To generate the start and stop conditions, manipulate the control registers through software, considering the IIC bus
line characteristics.
[Data transmission/reception]
Master transmission, master reception (only master function with a single master)
ACK output functionNote and ACK detection function
Data length of 8 bits
(When an address is transmitted, the address is specified by the higher 7 bits, and the least significant bit is
used for R/W control.)
Generation of start condition and stop condition by software
[Interrupt function]
Transfer end interrupt
[Error detection flag]
ACK error detection flag
* [Functions not supported by simplified I2C]
Slave transmission, slave reception
Arbitration loss detection function
Wait detection function
Note When receiving the last data, ACK will not be output if 0 is written to the SOEm.n (SOEm register) bit and serial
communication data output is stopped. See the processing flow in 12.6.3 (2) for details.
Remark
m: Unit number (m = 1), n: Channel number (n = 1), mn = 11
The channels supporting simplified I2C (IIC11) are channel 1 of SAU1.
2
Unit
Channel
Used as CSI
Used as Simplified I C
0
0
CSI00
1
CSI01
0
CSI10
1
IIC11
1
Simplified I2C (IIC11) performs the following four types of communication operations.
Address field transmission
(See 12.6.1.)
Data transmission
(See 12.6.2.)
Data reception
(See 12.6.3.)
Stop condition generation
(See 12.6.4.)
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12.7.1 Address field transmission
2
Address field transmission is a transmission operation that first executes in I C communication to identify the target for
transfer (slave). After a start condition is generated, an address (7 bits) and a transfer direction (1 bit) are transmitted in
one frame.
2
Simplified I C
IIC11
Target channel
Channel 1 of SAU1
Pins used
SCL11, SDA11
Interrupt
INTIIC11
Note
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection
flag
ACK error detection flag (PEFmn)
Transfer data
length
8 bits (transmitted with specifying the higher 7 bits as address and the least significant bit as R/W control)
Transfer rate
Max. fMCK/2 [Hz] (SDRmn[15:9] = 1 or more)
fMCK: Operation clock frequency of target channel
2
However, the following condition must be satisfied in each mode of I C.
Max. 400 kHz (fast mode)
Max. 100 kHz (standard mode)
Data level
Non-reverse output (default: high level)
Parity bit
No parity bit
Stop bit
Appending 1 bit (for ACK reception timing)
Data direction
MSB first
Note
To perform communication via simplified I2C, set the N-ch open-drain output (EVDD tolerance) mode (POMxx = 1)
for the port output mode registers (POMx) (see 4.3 Registers Controlling Port Function for details).
Remark
m: Unit number (m = 1), n: Channel number (n = 1), mn = 11
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(1) Register setting
2
Figure 12-90. Example of Contents of Registers for Address Field Transmission of Simplified I C
(IIC11)(1/2)
(a) Serial mode register mn (SMRmn)
15
SMRmn
14
13
12
11
10
9
0
0
0
0
0
CKSmn CCSmn
0/1
0
8
7
STSmn
0
6
5
4
3
1
0
0
SISmn0
0
2
1
0
MDmn2 MDmn1 MDmn0
0
Operation clock (fMCK) of channel n
0: Prescaler output clock CKm0 set by the SPSm register
1: Prescaler output clock CKm1 set by the SPSm register
1
0
0
Operation mode of channel n
0: Transfer end interrupt
(b) Serial communication operation setting register mn (SCRmn)
15
SCRmn
14
13
12
11
TXEmn RXEmn DAPmn CKPmn
1
0
0
0
10
9
8
7
6
EOCmn PTCmn1 PTCmn0 DIRmn
0
0
0
0
0
5
4
3
2
0
1
SLCmn1 SLCmn0
0
0
1
Setting of parity bit
00B: No parity
1
0
DLSmn1 DLSmn0
1
1
Setting of stop bit
01B: Appending 1 bit (ACK)
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOr)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
SDRmn
Baud rate setting
Transmit data setting (address + R/W)
0
SDRmnL
(d) Serial output register m (SOm)
15
14
13
12
11
10
0
0
0
0
0
0
SOm
9
8
7
6
5
4
3
2
0
0
0
0
0
0
CKOm1 CKOm0
0/1
0/1
SOm.1 SOm.0
0/1
0/1
Start condition is generated by manipulating the SOm.n bit.
(e) Serial output enable register m (SOEm)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm
1
0
SOEm.1 SOEm.0
0/1
0/1
SOEm.n = 0 until the start condition is generated, and SOEm.n =
1 after generation.
Note Serial array unit 0 only.
Remarks 1. m: Unit number (m = 1), n: Channel number (n = 1), r: IIC number (r = 11)
mn = 11
2.
: Setting is fixed in the IIC mode,
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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Figure 12-90. Example of Contents of Registers for Address Field Transmission of Simplified I2C
(IIC00, IIC01, IIC11, IIC20, IIC21)(2/2)
(f) Serial channel start register m (SSm) … Sets only the bits of the target channel is 1.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSm
1
0
SSm.1
SSm.0
0/1
0/1
SSEm.n = 0 until the start condition is generated, and SSEm.n =
1 after generation.
Remarks 1. m: Unit number (m = 1), n: Channel number (n = 1), r: IIC number (r = 11)
mn = 11
2.
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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(2) Operation procedure
Figure 12-91. Initial Setting Procedure for Address Field Transmission
Starting initial setting
Setting the PER0 register
Setting the SPSm register
Release the serial array unit from the reset status
and start clock supply.
Set the operation clock.
Setting the SMRmn register
Set an operation mode, etc.
Setting the SCRmn register
Set a communication format.
Setting the SDRmn register
Set a transfer baud rate (setting the transfer clock by
dividing the operation clock (fMCK)).
Setting the SOm register
Set the initial output level of the serial data (SOmn)
and serial clock (CKOmn).
Enable data output, clock output, and N-ch open-drain output
Setting port
(EVDD tolerance2) mode of the target channel by setting the port
register, port mode register, and port output mode register.
Set PM10 to “1” to use the P10 pin as the SCK00/SCL00.
Starting communication
Caution
After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial clock
select register m (SPSm) after 4 or more fCLK clocks have elapsed.
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(3) Processing flow
Figure 12-92. Timing Chart of Address Field Transmission
SSm.n
SEm.n
SOEm.n
Address field transmission
SDRmn
SCLr output
CKOmn
bit manipulation
SDAr output
D7
D6
D5
D4
D3
D2
D1
SOmn bit manipulation
R/W
Address
D7
SDAr input
Shift
register mn
D6
D5
D4
D0
D3
D2
D1
D0
ACK
Shift operation
INTIICr
TSFmn
Remark
m: Unit number (m = 1), n: Channel number (n = 1), r: IIC number (r = 11)
mn = 11
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Figure 12-93. Flowchart of Address Field Transmission
Starting IIC communication
SMRmn, SCRmn: Setting communication
SPSm, SDRmn[15:9]: Setting transfer rate
Specify the initial settings
while the SEm.n bit of
serial channel enable
status register m (SEm) is
0 (operation is stopped).
Writing 0 to the SOm.n bit
Writing 0 to the CKOmn bit
Writing 1 to the SOEm.n bit
Writing 1 to the SSm.n bit
Writing address and R/W
data to SIOr or SDRmn
Transfer end interrupt
generated?
No
Yes
ACK response
received?
Check PEFmn bit for ACK response
from the slave. If ACK is received
(PEFmn = 0), go to the next processing.
If NACK is received (PEFmn = 1), go to
error handling.
No
Yes
Communication error
Address field
transmission completed
handling
To data transmission flow
and data reception flow
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12.7.2 Data transmission
Data transmission is an operation to transmit data to the target for transfer (slave) after transmission of an address field.
After all data are transmitted to the slave, a stop condition is generated and the bus is released.
2
Simplified I C
IIC11
Target channel
Channel 3 of SAU0
Pins used
SCL11, SDA11
Interrupt
INTIIC11
Note
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection
ACK error detection flag (PEFmn)
flag
Transfer data
8 bits
length
Transfer rate
Max. fMCK/2 [Hz] (SDRmn[15:9] = 1 or more)
fMCK: Operation clock frequency of target channel
2
However, the following condition must be satisfied in each mode of I C.
Max. 400 kHz (fast mode)
Max. 100 kHz (standard mode)
Data level
Non-reverse output (default: high level)
Parity bit
No parity bit
Stop bit
Appending 1 bit (for ACK reception timing)
Data direction
MSB first
Note
To perform communication via simplified I2C, set the N-ch open-drain output (EVDD tolerance) mode (POMxx = 1)
for the port output mode registers (POMx) (see 4.3 Registers Controlling Port Function for details).
Remark
m: Unit number (m = 1), n: Channel number (n = 1), mn = 11
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(1) Register setting
Figure 12-94. Example of Contents of Registers for Data Transmission of Simplified I2C
(IIC11) (1/2)
(a) Serial mode register mn (SMRmn) … Do not manipulate this register during data
transmission/reception.
15
SMRmn
14
13
12
11
10
9
0
0
0
0
0
CKSmn CCSmn
0/1
0
8
7
STSmn
0
6
5
4
3
1
0
0
SISmn0
0
0
2
1
0
MDmn2 MDmn1 MDmn0
1
0
0
(b) Serial communication operation setting register mn (SCRmn) … Do not manipulate the bits of this
register, except the TXEmn and
RXEmn bits, during data
transmission/reception.
15
SCRmn
14
13
12
11
TXEmn RXEmn DAPmn CKPmn
1
0
0
0
10
9
8
7
6
EOCmn PTCmn1 PTCmn0 DIRmn
0
0
0
0
0
5
4
3
2
SLCmn1 SLCmn0
1
0
DLSmn1 DLSmn0
0
0
1
0
1
1
1
6
5
4
3
2
1
0
1
0
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOr)
15
14
13
12
11
10
9
8
7
SDRmn
Baud rate setting
Transmit data setting
0
SDRmnL
(d) Serial output register m (SOm) … Do not manipulate this register during data
transmission/reception.
15
14
13
12
11
10
0
0
0
0
0
0
SOm
9
8
7
6
5
4
3
2
0
0
0
0
0
0
CKOm1 CKOm0
0/1Note 0/1Note
SOm.1 SOm.0
0/1Note 0/1Note
(e) Serial output enable register m (SOEm) … Do not manipulate this register during data
transmission/reception.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm
1
0
SOEm.1 SOEm.0
1
1
Note The value varies depending on the communication data during communication operation.
Remarks 1. m: Unit number (m = 1), n: Channel number (n = 1), r: IIC number (r = 11)
mn = 11
2.
: Setting is fixed in the IIC mode,
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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Figure 12-94. Example of Contents of Registers for Data Transmission of Simplified I2C
(IIC11) (2/2)
(f) Serial channel start register m (SSm) … Do not manipulate this register during data
transmission/reception.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSm
1
0
SSm.1
SSm.0
0/1
0/1
Remarks 1. m: Unit number (m = 1), n: Channel number (n = 1), r: IIC number (r = 11)
mn = 11
2.
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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(2) Processing flow
Figure 12-95. Timing Chart of Data Transmission
SSm.n
L
SEm.n
H
SOEm.n
H
SDRmn
Sending Data 1
SCLr output
SDAr output
D7
D6
D5
D4
D3
D2
D1
D0
SDAr input
D7
D6
D5
D4
D3
D2
D1
D0
Shift
register mn
ACK
Shift operation
INTIICr
TSFmn
Figure 12-96. Flowchart of Data Transmission
Address field transmission completed
Starting data transmission
Writing data to SIOr or
SDRmn
Transmission is started by writing.
Transmission end wait state
Transfer end interrupt
generated?
No
(Interrupt request flag is cleared.)
Check ACK response from the slave.
If ACK is received (PEFmn = 0), go to the next processing.
If NACK is received (PEFmn = 1), go to error handling.
No
ACK error response
received?
Yes
Yes
Communication error
handling
No
Data transfer completed?
Yes
Data transmission completed
Stop condition generation
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12.7.3 Data reception
Data reception is an operation to receive data to the target for transfer (slave) after transmission of an address field.
After all data are received to the slave, a stop condition is generated and the bus is released.
2
Simplified I C
IIC11
Target channel
Channel 3 of SAU0
Pins used
SCL11, SDA11
Interrupt
INTIIC11
Note
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag
Overrun error detection flag (OVFmn) only
Transfer data length
8 bits
Transfer rate
Max. fMCK/2 [Hz] (SDRmn[15:9] = 1 or more)
fMCK: Operation clock frequency of target channel
2
However, the following condition must be satisfied in each mode of I C.
Max. 400 kHz (fast mode)
Max. 100 kHz (standard mode)
Data level
Non-reverse output (default: high level)
Parity bit
No parity bit
Stop bit
Appending 1 bit (ACK transmission)
Data direction
MSB first
Note
To perform communication via simplified I2C, set the N-ch open-drain output (EVDD tolerance) mode (POMxx = 1)
for the port output mode registers (POMx) (see 4.3 Registers Controlling Port Function for details).
Remark
m: Unit number (m = 1), n: Channel number (n = 1), mn = 11
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(1) Register setting
2
Figure 12-97. Example of Contents of Registers for Data Reception of Simplified I C
(IIC11) (1/2)
(a) Serial mode register mn (SMRmn) … Do not manipulate this register during data
transmission/reception.
15
SMRmn
14
13
12
11
10
9
0
0
0
0
0
CKSmn CCSmn
0/1
0
8
7
STSmn
0
6
5
4
3
1
0
0
SISmn0
0
0
2
1
0
MDmn2 MDmn1 MDmn0
1
0
0
(b) Serial communication operation setting register mn (SCRmn) … Do not manipulate the bits of this
register, except the TXEmn and
RXEmn bits, during data
transmission/reception.
15
SCRmn
14
13
12
11
TXEmn RXEmn DAPmn CKPmn
0
1
0
0
10
9
8
7
6
EOCmn PTCmn1 PTCmn0 DIRmn
0
0
0
0
0
5
4
3
2
SLCmn1 SLCmn0
1
0
DLSmn1 DLSmn0
0
0
1
0
1
1
1
6
5
4
3
2
1
0
1
0
SOm.1
SOm.0
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOr)
15
14
13
12
11
10
9
8
7
SDRmn
Baud rate setting
Dummy transmit data setting (FFH)
0
SDRmnL
(d) Serial output register m (SOm) … Do not manipulate this register during data
transmission/reception.
15
14
13
12
11
10
0
0
0
0
0
0
SOm
9
8
7
6
5
4
3
2
0
0
0
0
0
0
CKOm1 CKOm0
0/1Note 0/1Note2
0/1Note 0/1Note2
(e) Serial output enable register m (SOEm) … Do not manipulate this register during data
transmission/reception.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm
Notes
1
0
SOEm.1 SOEm.0
0/1
0/1
The value varies depending on the communication data during communication operation.
Remarks 1. m: Unit number (m = 1), n: Channel number (n = 1), r: IIC number (r = 11)
mn = 11
2.
: Setting is fixed in the IIC mode,
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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Figure 12-97. Example of Contents of Registers for Data Reception of Simplified I2C
(IIC11) (2/2)
(f) Serial channel start register m (SSm) … Do not manipulate this register during data
transmission/reception.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSm
1
0
SSm.1
SSm.0
0/1
0/1
Note Serial array unit 0 only.
Remarks 1. m: Unit number (m = 1), n: Channel number (n = 1), r: IIC number (r = 11)
mn = 11
2.
: Setting is fixed in the IIC mode,
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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(2) Processing flow
Figure 12-98. Timing Chart of Data Reception
(a) When starting data reception
SSm.n
STm.n
SEm.n
SOEmn
TXEmn,
RXEmn
H
TXEmn =1/RXEmn =0
TXEmn =0/RXEmn =1
SDRmn
Receive data
Dummy data (FFH)
SCLr output
SDAr output
ACK
D7
SDAr input
D6
D5
D4
Shift
register mn
D3
D2
D1
D0
Shift operation
INTIICr
TSFmn
(b) When receiving last data
STm.n
SEm.n
SOEm.n
Output is enabled by serial
communication operation
TXEmn,
RXEmn
Output is stopped by serial communication operation
TXEmn =0/RXEmn =1
SDRmn
Dummy data (FFH)
Dummy data (FFH)
Receive data
Receive data
SCLr output
SDAr output
SDAr input
ACK
D2
Shift
register mn
D1
D0
Shift operation
NACK
D7
D6
D5
D4
D3
D2
D1
D0
Shift operation
INTIICr
TSFmn
Reception of last byte
SOmn bit
SOmn bit
manipulation manipulation
IIC operation stop CKOmn bit
manipulation
Step condition
Remark
m: Unit number (m = 1), n: Channel number (n = 1), r: IIC number (r = 11)
mn = 11
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Figure 12-99. Flowchart of Data Reception
Address field transmission completed
Starting data reception
Writing 1 to the STm.n bit
Stop operation to modify the
SCRmn register.
Writing 0 to the TXEmn bit, and 1 to the RXEmn bit
Restart operation.
Writing 1 to the SSm.n bit
Last data received?
Set operation mode of the
channel for reception only.
No
Yes
Writing 0 to the SOEm.n bit
Disable output to prevent ACK
response for the last reception
Start reception operation.
Writing dummy data (FFH) to SIOr (SDRmn[7:0])
Transfer end interrupt
generated?
No
Wait for completion of reception.
(Clear the interrupt request flag.)
Yes
Reading SIOr (SDRmn[7:0])
Read received data and process
the data (storing to RAM, etc.)
No
Data transfer completed?
Yes
Data reception completed
Stop condition generation
Caution
ACK is not output when the last data is received (NACK). Communication is then completed by
setting “1” to the STm.n bit of serial channel stop register m (STm) to stop operation and
generating a stop condition.
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12.7.4 Stop condition generation
After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is released.
(1) Processing flow
Figure 12-100. Timing Chart of Stop Condition Generation
STmn.
SEm.n
SOEmn. Note
SCLr output
SDAr output
SOm.n
CKOmn
SOm.n
bit manipulation bit manipulation bit manipulation
Operation
stop
Stop condition
Note During a receive operation, the SOEm.n bit of serial output enable register m (SOEm) is cleared to 0 before
receiving the last data.
Figure 12-101. Flowchart of Stop Condition Generation
Completion of data transmission/data reception
Starting generation of stop condition.
Writing 1 to the STm.n bit to clear
(the SEm.n bit is cleared to 0)
Writing 0 to the SOEm.n bit
Operation is stopped. (CKOmn can be manipulated.)
Output is disabled. (SOmn can be manipulated.)
Writing 0 to the SOm.n bit
The timing must be such that the SCL low-width
Writing 1 to the CKOmn bit
specification for I2C bus is satisfied.
2
Wait
Secure a wait time so that the specifications of I C bus
are satisfied.
Writing 1 to the SOm.n bit
2
End of I C communication
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12.7.5 Calculating transfer rate
2
The transfer rate for simplified I C (IIC11) communication can be calculated by the following expressions.
(Transfer rate) = {Operation clock (fMCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2
Caution Setting SDRmn[15:9] = 0000000B is prohibited. Set SDRmn[15:9] to 0000001B or more.
2
The duty ratio of the SCL signal output from the simplified I C is 50%.
Remarks 1.
The value of SDRmn[15:9] is the value of bits 15 to 9 of the SDRmn register (0000001B to
1111111B) and therefore is 1 to 127.
2.
m: Unit number (m = 1), n: Channel number (n = 1), mn = 11
The operation clock (fMCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode
register mn (SMRmn).
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Table 12-4. Selection of Operation Clock For Simplified I2C
SMRmn
Register
SPSm Register
CKSmn
PRS PRS PRS PRS PRS PRS PRS PRS
m13 m12 m11 m10 m03 m02 m01 m00
0
1
X
X
X
X
0
Operation Clock (fMCK)
0
0
0
Note
fCLK = 32 MHz
fCLK
32 MHz
X
X
X
X
0
0
0
1
fCLK/2
X
X
X
X
0
0
1
0
fCLK/2
2
8 MHz
16 MHz
X
X
X
X
0
0
1
1
fCLK/2
3
4 MHz
X
X
X
X
0
1
0
0
fCLK/2
4
2 MHz
X
X
X
X
0
1
0
1
fCLK/2
5
1 MHz
500 kHz
X
X
X
X
0
1
1
0
fCLK/2
6
X
X
X
X
0
1
1
1
fCLK/2
7
250 kHz
125 kHz
62.5 kHz
X
X
X
X
1
0
0
0
fCLK/2
8
X
X
X
X
1
0
0
1
fCLK/2
9
31.25 kHz
15.63 kHz
X
X
X
X
1
0
1
0
fCLK/2
10
X
X
X
X
1
0
1
1
fCLK/2
11
0
0
0
0
X
X
X
X
fCLK
0
0
0
1
X
X
X
X
fCLK/2
32 MHz
16 MHz
0
0
1
0
X
X
X
X
fCLK/2
2
0
0
1
1
X
X
X
X
fCLK/2
3
4 MHz
0
1
0
0
X
X
X
X
fCLK/2
4
2 MHz
1 MHz
8 MHz
0
1
0
1
X
X
X
X
fCLK/2
5
0
1
1
0
X
X
X
X
fCLK/2
6
500 kHz
250 kHz
125 kHz
0
1
1
1
X
X
X
X
fCLK/2
7
1
0
0
0
X
X
X
X
fCLK/2
8
62.5 kHz
1
0
0
1
X
X
X
X
fCLK/2
9
1
0
1
0
X
X
X
X
fCLK/2
10
31.25 kHz
1
0
1
1
X
X
X
X
fCLK/2
11
15.63 kHz
Other than the above
Setting prohibited
Note Stop the operation of the serial array unit (SAU) (by setting bits 3 to 0 of ST0 register and bits 1 and 0 of ST1
and STS register to 1) before changing operation clock (fCLK) selection (by changing the system clock control
register (CKC) value).
Remarks 1. X: Don’t care
2. m: Unit number (m = 1), n: Channel number (n = 1), mn = 11
Here is an example of setting an IIC transfer rate where fMCK = fCLK = 32 MHz.
IIC Transfer Mode
(Desired Transfer Rate)
fCLK = 32 MHz
Operation Clock (fMCK)
SDRmn[15:9]
Calculated
Transfer Rate
Error from Desired Transfer
Rate
100 kHz
fCLK/2
79
100 kHz
0.0%
400 kHz
fCLK
41
380 kHz
5.0%
Note
Note The error cannot be controlled to about 0%, because the duty ratio of the SCL signal is 50%.
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12.7.6 Procedure for processing errors that occurred during simplified I2C (IIC11) communication
2
The procedure for processing errors that occurred during simplified I C (IIC11) communication is described in Figure
12-102.
Figure 12-102. Processing Procedure in Case of Parity Error (ACK error) in Simplified I2C Mode
Software Manipulation
Hardware Status
Reads serial status register mn (SSRmn).
Writes serial flag clear trigger register mn
(SIRmn).
Remark
Error type is identified and the read value is
used to clear error flag.
Error flag is cleared.
Error can be cleared only during reading,
by writing the value read from the SSRmn
register to the SIRmn register without
modification.
Sets the STm.n bit of serial channel stop
register m (STm) to 1.
The SEm.n bit of serial channel
Slave is not ready for reception because
enable status register m (SEm) is set
to 0 and channel n stops operation.
ACK is not returned. Therefore, a stop
condition is created, the bus is released,
and communication is started again from
the start condition. Or, a restart condition
Creates stop condition.
is generated and transmission can be
redone from address transmission.
Creates start condition.
Sets the SSm.n bit of serial channel start
The SEm.n bit of serial channel
register m (SSm) to 1.
enable status register m (SEm) is set
to 1 and channel n is enabled to
operate.
Remark
m: Unit number (m = 1), n: Channel number (n = 1), r: IIC number (r = 11)
mn = 11
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12.8 Relationship Between Register Settings and Pins
Tables 12-5 to 12-14 show the relationship between register settings and pins for each channel of serial array units 0, 1.
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SE
00
MD
002
MD
001
SOE
00
SO
00
0
0
0
0
1
1
0
0
1
0
0
0
1
1
0
0/1
1
0/1
Note1
1
1
0
1
1
CKO TXE RXE PM10 P10 PM11 P11 PM12 P12
00
00
00
Operation mode
1
1
1
1
0
1
1
1
1
1
1
0/1
0
1
0
0/1
0/1
1
0
0/1
0/1
1
1
Note3
Note3
Note3 Note3
Note3 Note3
Pin Function
P10/LTxD1/
SCK00/TI10/
TO10/INTP4
P11/LRxD1/
INTPLR1/SI0
0/TI11/TO11
P12/SO00/
TI12/TO12/
INTP2
Operation stop
mode
P10/LTxD1/
TI10/TO10/
INTP4
P11/LRxD1/
INTPLR1/
TI11/TO11
P12/TI12/
TO12/
INTP2
Slave CSI00
reception
SCK00 (input)
SI00
P12/TI12/
TO12/
INTP2
0
1
Slave CSI00
transmission
SCK00 (input)
P11/TI11/
TO11
SO00
1
0
1
Slave CSI00
transmission/
reception
SCK00
(input)
SI00
SO00
1
1
Master CSI00
reception
SCK00
(output)
SI00
P12/SO00/
TI12/TO12/
INTP2
0
1
0
1
Master CSI00
transmission
SCK00
(output)
P11/TI11/
TO11
SO00
0
1
1
0
1
Master CSI00
transmission/
reception
SCK00
(output)
SI00
SO00
Note2 Note2 Note2 Note2 Note2 Note2
Note2 Note2
Note2 Note2
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Table 12-5. Relationship between register settings and pins (Channel 0 of unit 0: CSI00, SCSI0001 = 0, SCSI000 = 0)
Notes 1. The SE0 register is a read-only status register which is set using the SS0 and ST0 registers.
3. This is 0 or 1, depending on the communication operation. For details, refer to 12.3 (12) Serial output register m (SOm).
Caution The shaded pins are provided at some ports. Select either port by using the corresponding register.
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CHAPTER 12 SERIAL ARRAY UNIT
2. This pin can be set as a port function pin or other alternate function pin.
SE
00
MD
002
MD
001
SOE
00
SO
00
0
0
0
0
1
1
0
0
1
0
0
0
1
1
0
0/1
1
0/1
Note1
1
1
0
1
1
CKO TXE RXE PM04 P04 PM03 P03 PM02 P02
00
00
00
Operation mode
1
1
1
1
0
1
1
1
1
1
1
0/1
0
1
0
0/1
0/1
1
0
0/1
0/1
1
1
Note3
Note3
Note3 Note3
Note3 Note3
Pin Function
P04/SCK00/ P03/SI00/
TI04/TO04/ TI03/TO03/
TI14/TO14 TI13/TO13
P02/ SO00/
TI02/TO02/
TI12/TO12
Operation stop
mode
P04/TI04/
TO04/
TI14/TO14
P03/TI03/
TO03/
TI13/TO13
P02/TI02/
TO02/
TI12/TO12
Slave CSI00
reception
SCK00
(input)
SI00
P02/TI02/
TO02/
TI12/TO12
0
1
Slave CSI00
transmission
SCK00
(input)
P03/TI03/
TO03/
TI13/TO13
SO00
1
0
1
Slave CSI00
transmission/
reception
SCK00
(input)
SI00
SO00
1
1
Master CSI00
reception
SCK00
(output)
SI00
P02/TI02/
TO02/
TI12/TO12
0
1
0
1
Master CSI00
transmission
SCK00
(output)
P03/TI03/
TO03/
TI13/TO13
SO00
0
1
1
0
1
Master CSI00
transmission/
reception
SCK00
(output)
SI00
SO00
Note2 Note2 Note2 Note2 Note2 Note2
Note2 Note2
Note2 Note2
2. This pin can be set as a port function pin or other alternate function pin.
3. This is 0 or 1, depending on the communication operation. For details, refer to 12.3 (12) Serial output register m (SOm).
Caution The shaded pins are provided at some ports. Select either port by using the corresponding register.
739
CHAPTER 12 SERIAL ARRAY UNIT
Notes 1. The SE0 register is a read-only status register which is set using the SS0 and ST0 registers.
RL78/D1A
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
Table 12-6. Relationship between register settings and pins (Channel 0 of unit 0: CSI00, SCSI0001 = 0, SCSI000 = 1)
SE
00
MD
002
MD
001
SOE
00
SO
00
0
0
0
0
1
1
0
0
1
0
0
0
1
1
0
0/1
1
0/1
Note1
1
1
0
1
1
CKO TXE RXE PM34 P34 PM33 P33 PM32 P32
00
00
00
Operation mode
1
1
1
1
0
1
1
1
1
1
1
0/1
0
1
0
1
0/1
0/1
1
0
0
1
0/1
0/1
1
1
0
1
Note3
Note3
Note3 Note3
Note3 Note3
Pin Function
P34/TI24/
TO24/SCK00
P33/TI23/
TO23/SI00
P32/TI22/
TO22/SO00
Operation stop
mode
P34/TI24/
TO24
P33/TI23/
TO23
P32/TI22/
TO22
Slave CSI00
reception
SCK00 (input)
SI00
P32/TI22/
TO22
0
1
Slave CSI00
transmission
SCK00 (input)
P33/TI23/
TO23
SO00
1
0
1
Slave CSI00
transmission/
reception
SCK00
(input)
SI00
SO00
1
Master CSI00
reception
SCK00
(output)
SI00
P32/TI22/
TO22
0
1
Master CSI00
transmission
SCK00
(output)
P33/TI23/
TO23
SO00
1
0
1
Master CSI00
transmission/
reception
SCK00
(output)
SI00
SO00
Note2 Note2 Note2 Note2 Note2 Note2
Note2 Note2
Note2 Note2
Note2 Note2
Note2 Note2
RL78/D1A
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
Table 12-7. Relationship between register settings and pins (Channel 0 of unit 0: CSI00, SCSI001 = 1, SCSI000 = 0)
Notes 1. The SE0 register is a read-only status register which is set using the SS0 and ST0 registers.
2. This pin can be set as a port function pin or other alternate function pin.
3. This is 0 or 1, depending on the communication operation. For details, refer to 12.3 (12) Serial output register m (SOm).
CHAPTER 12 SERIAL ARRAY UNIT
740
SE
01
MD
012
MD
011
SOE
01
SO
01
0
0
0
0
1
Note1
CKO TXE RXE PM74 P74
01
01
01
1
0
0
PM
75
P75 PM13 P13
0
0
0
1
1
0
1
1
1
0/1
Note3
1
1
0
1
1
1
1
0
1
Operation stop
mode
P74/TI23/
TO123
P75/PCL/
TI22/TO22
P13/TI13/
TO13
Slave CSI01
reception
SCK01
(input)
SI01
P13/TI13/
TO13
0
1
Slave CSI01
transmission
SCK01
(input)
P75/PCL/
TI22/TO22
SO01
0
1
Slave CSI01
transmission/
reception
SCK01
(input)
SI01
SO01
Master CSI01
reception
SCK01
(output)
SI01
P13/TI13/
TO13
1
1
1
1
0/1
0
1
0
1
1
0/1
0/1
0/1
Note3 Note3
1
0
0
1
Note2 Note2
1
0/1
Note2 Note2
0
1
Master CSI01
transmission
SCK01
(output)
P75/PCL/
TI22/TO22
SO01
1
0
1
Master CSI01
transmission/
reception
SCK01
(output)
SI01
SO01
Note2 Note2
1
1
0
1
P13/SO01/
TI13/TO13
1
Note3 Note3
P75/PCL/
SI01/TI22/
TO22
Note2 Note2
0/1
Note3
Pin Function
P74/SCK01/
TI23/TO123
Note2 Note2 Note2 Note2 Note2 Note2
1
Operation mode
RL78/D1A
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
Table 12-8. Relationship between register settings and pins (Channel 1 of unit 0: CSI01, SCSI010 = 0)
Notes 1. The SE0 register is a read-only status register which is set using the SS0 and ST0 registers.
2. This pin can be set as a port function pin or other alternate function pin.
3. This is 0 or 1, depending on the communication operation. For details, refer to 12.3 (12) Serial output register m (SOm).
CHAPTER 12 SERIAL ARRAY UNIT
741
SE
01
MD
012
MD
011
SOE
01
SO
01
0
0
0
0
1
Note1
CKO TXE RXE PM56 P56 PM55 P55 PM54 P54
01
01
01
Operation mode
1
1
1
0
0
0
0
0
1
1
0
1
1
1
0/1
Note3
1
1
0
1
1
0
1
Operation stop
mode
P56/TI16/
TO16/
P55/TI15/
TO15
P54/TI14/
TO14
Slave CSI01
reception
SCK01
(input)
SI01
P54/TI14/
TO14
0
1
Slave CSI01
transmission
SCK01
(input)
P55/TI15/
TO15
SO01
0
1
Slave CSI01
transmission/
reception
SCK01
(input)
SI01
SO01
Master CSI01
reception
SCK01
(output)
SI01
P54/TI14/
TO14
1
1
1
1
1
0/1
0
1
0
1
1
0/1
0/1
0/1
0/1
Note3 Note3
1
0
0
1
Note2 Note2
1
Note3 Note3
Note2 Note2
0
1
Master CSI01
transmission
SCK01
(output)
P55/TI15/
TO15
SO01
1
0
1
Master CSI01
transmission/
reception
SCK01
(output)
SI01
SO01
Note2 Note2
1
1
0
1
P54/TI14/
TO14/SO0
1
Note2 Note2
0/1
Note3
P55/TI15/
TO15/SI01
Note2 Note2 Note2 Note2 Note2 Note2
1
Pin Function
P56/TI16/
TO16/
SCK01
RL78/D1A
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
Table 12-9. Relationship between register settings and pins (Channel 1 of unit 0: CSI01, SCSI010 = 1)
Notes 1. The SE0 register is a read-only status register which is set using the SS0 and ST0 registers.
2. This pin can be set as a port function pin or other alternate function pin.
3. This is 0 or 1, depending on the communication operation. For details, refer to 12.3 (12) Serial output register m (SOm).
CHAPTER 12 SERIAL ARRAY UNIT
742
RL78/D1A
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
Table 12-10. Relationship between register settings and pins (Channel 0 of unit 1: CSI10, SCSI100 = 0)
SE
MD
MD
SOE
SO
CKO
TXE
RXE
PM
10
102
101
10
10
10
10
10
10
P133
PM
P132
PM
P131
Operation mode
131
132
Note1
0
1
0
0
0
0
0
0
1
1
1
0/1
1
1
1
0
0
1
0
1
1
Note2
Note2
Note2
Note2
Note2
Note2
1
1
Note3
1
0/1
1
1
1
1
1
Note2
Note2
1
Note2
Note2
0
1
Pin Function
P133/SCK10/
P132/SI10/
P131/SO10/
TI22/TO22
LRxD1/INTPLR1
LTxD1/TI21/
/TI20/TO20
TO21
Operation stop
P132/INTP4/
P132/INTP5/
P131/TI21/
mode
CTxD/LTxD1/
LRxD1/
TO21
TI00/P133/
INTPLR1/TI20/
TI22/TO22
TO20
SCK10 (input)
SI10
Slave CSI10
Slave CSI10
SCK10 (input)
0
1
Slave CSI10
P132/INTP5/
SO10
TI20/TO20
transmission
Note3
P131/TI21/
TO21
reception
SCK10 (input)
SI10
SO10
SCK10 (output)
SI10
P131/TI21/
transmission/
reception
0
1
1
1
0/1
0/1
0/1
Note3
Note3
0/1
0/1
Note3
Note3
0
1
1
1
0
1
0
0
0
1
1
1
1
Note2
Note2
1
Note2
Note2
0
1
Master CSI10
TO21
reception
Master CSI10
SCK10 (output)
0
1
Master CSI10
P132/INTP5/
SO10
TI20/TO20
transmission
SCK10 (output)
SI10
SO10
transmission/
Notes 1. The SE1 register is a read-only status register which is set using the SS1 and ST1 registers.
2. This pin can be set as a port function pin or other alternate function pin.
3. This is 0 or 1, depending on the communication operation. For details, refer to 12.3 (12) Serial output register m (SOm).
Caution The shaded pins are provided at two ports. Select either port by using the corresponding register.
743
CHAPTER 12 SERIAL ARRAY UNIT
reception
RL78/D1A
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
Table 12-11. Relationship between register settings and pins (Channel 0 of unit 1: CSI10, SCSI100 = 1)
SE
MD
MD
SOE
SO
CKO
TXE
RXE
PM
10
102
101
10
10
10
10
10
10
P51
PM
P52
PM
P53
Operation mode
53
52
P51/TI04/
P52/TI06/
P53/TI13/
TO04/SCK10
TO06/SI10
TO13/SO10
Operation stop
P51/TI04/
P52/TI06/
P53/TI13/
mode
TO04
TO06
TO13
Slave CSI10
SCK10 (input)
SI10
P53/TI13/
Note1
0
1
0
0
0
0
0
0
1
1
1
0/1
1
1
1
0
0
1
0
1
1
Note2
Note2
Note2
Note2
Note2
Note2
1
1
1
Note3
1
0/1
1
1
1
1
Note2
Note2
1
Note2
Note2
0
1
Pin Function
TO13
reception
Slave CSI10
SCK10 (input)
0
1
Note3
Slave CSI10
P52/TI06/
SO10
TO06
transmission
SCK10 (input)
SI10
SO10
SCK10 (output)
SI10
P53/TI13/
transmission/
reception
0
1
1
1
0/1
0/1
0/1
Note3
Note3
0/1
0/1
Note3
Note3
0
1
1
1
0
1
0
0
0
1
1
1
1
Note2
Note2
1
Note2
Note2
0
1
Master CSI10
TO13
reception
Master CSI10
SCK10 (output)
0
1
Master CSI10
P52/TI06/
SO10
TO06
transmission
SCK10 (output)
SI10
SO10
transmission/
reception
Notes 1. The SE1 register is a read-only status register which is set using the SS1 and ST1 registers.
2. This pin can be set as a port function pin or other alternate function pin.
Caution The shaded pins are provided at two ports. Select either port by using the corresponding register.
744
CHAPTER 12 SERIAL ARRAY UNIT
3. This is 0 or 1, depending on the communication operation. For details, refer to 12.3 (12) Serial output register m (SOm).
RL78/D1A
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
Table 12-12. Relationship between register settings and pins (Channel 1 of unit 1: IIC11, SIIC1: 0, SIIC0: 0)
SE11
MD112
MD111
SOE11
SO11
CKO11
TXE11
RXE11
PM60
P60
PM61
P61
POM1
Note1
0
1
Operation
mode
1
0
0
1
0/1
0/1
Note2
Note2
0/1
0/1
Note4
Note4
0
0
1
0
0
1
1
0
Pin Function
P60/TI20/TO20/
P61/TI21/TO21/
SCL11/INTP1
SDA11/INTP3
0
1
0
1
1
IIC11
start condition
SCL11
SDA11
0
1
0
1
1
IIC11 address
SCL11
SDA11
SCL11
SDA11
SCL11
SDA11
SCL11
SDA11
field
transmission
1
1
0
0
0/1
0/1
Note4
Note4
0/1
0/1
Note4
Note4
0/1
0/1
Note5
Note5
1
0
0
1
0
1
1
IIC11 data
transmission
0
1
0
1
0
1
1
IIC11 data
reception
0
1
1
0
0
1
0
1
0
1
1
IIC11
stop condition
Notes 1. The SE1 register is a read-only status register which is set using the SS1 and ST1 registers.
2. Set the CKO11 bit to 1 before a start condition is generated. Clear the SO11 bit from 1 to 0 when the start condition is generated.
3. This pin can be set as a port function pin.
745
CHAPTER 12 SERIAL ARRAY UNIT
4. This is 0 or 1, depending on the communication operation. For details, refer to 12.3 (12) Serial output register m (SOm).
5. Set the CKO11 bit to 1 before a stop condition is generated. Clear the SO11 bit from 0 to 1 when the stop condition is generated.
RL78/D1A
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
Table 12-13. Relationship between register settings and pins (Channel 1 of unit 1: IIC11, SIIC1 = 0, SIIC0 = 1)
SE11
MD112
MD111
SOE11
SO11
CKO11
TXE11
RXE11
PM30
P30
PM31
P31
POM2
Note1
0
1
Operation
mode
1
0
0
1
0/1
0/1
Note2
Note2
0/1
0/1
Note4
Note4
0
0
1
0
0
1
1
0
Pin Function
P30/TI20/TO20/
P31/TI21/TO21/
SCL11
SDA11
0
1
0
1
1
IIC11
start condition
SCL11
SDA11
0
1
0
1
1
IIC11 address
SCL11
SDA11
SCL11
SDA11
SCL11
SDA11
SCL11
SDA11
field
transmission
1
1
0
0
0/1
0/1
Note4
Note4
0/1
0/1
Note4
Note4
0/1
0/1
Note5
Note5
1
0
0
1
0
1
1
IIC11 data
transmission
0
1
0
1
0
1
1
IIC11 data
reception
0
1
1
0
0
1
0
1
0
1
1
IIC11
stop condition
Notes 1. The SE1 register is a read-only status register which is set using the SS1 and ST1 registers.
2. Set the CKO11 bit to 1 before a start condition is generated. Clear the SO11 bit from 1 to 0 when the start condition is generated.
3. This pin can be set as a port function pin.
746
CHAPTER 12 SERIAL ARRAY UNIT
4. This is 0 or 1, depending on the communication operation. For details, refer to 12.3 (12) Serial output register m (SOm).
5. Set the CKO11 bit to 1 before a stop condition is generated. Clear the SO11 bit from 0 to 1 when the stop condition is generated.
RL78/D1A
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
Table 12-14. Relationship between register settings and pins (Channel 1 of unit 1: IIC11, SIIC1 = 1, SIIC0 = 0)
SE11
MD112
MD111
SOE11
SO11
CKO11
TXE11
RXE11
PM136
P136
PM50
P50
POM5
Note1
0
1
Operation
mode
1
0
0
1
0/1
0/1
Note2
Note2
0/1
0/1
Note4
Note4
0
0
1
0
0
1
1
0
Pin Function
P136/TI00/TO00/
P50/TI21/TO21/
SCL11
SDA11
0
1
0
1
1
IIC11
start condition
SCL11
SDA11
0
1
0
1
1
IIC11 address
SCL11
SDA11
SCL11
SDA11
SCL11
SDA11
SCL11
SDA11
field
transmission
1
1
0
0
0/1
0/1
Note4
Note4
0/1
0/1
Note4
Note4
0/1
0/1
Note5
Note5
1
0
0
1
0
1
1
IIC11 data
transmission
0
1
0
1
0
1
1
IIC11 data
reception
0
1
1
0
0
1
0
1
0
1
1
IIC11
stop condition
Notes 1. The SE1 register is a read-only status register which is set using the SS1 and ST1 registers.
2. Set the CKO11 bit to 1 before a start condition is generated. Clear the SO11 bit from 1 to 0 when the start condition is generated.
3. This pin can be set as a port function pin or other alternate function pin.
747
CHAPTER 12 SERIAL ARRAY UNIT
4. This is 0 or 1, depending on the communication operation. For details, refer to 12.3 (12) Serial output register m (SOm).
5. Set the CKO11 bit to 1 before a stop condition is generated. Clear the SO11 bit from 0 to 1 when the stop condition is generated.
Table 12-15. Relationship between register settings and pins (Channel 0 and 1 of unit 0: UART0)
SE
00
SE
01
MD
002
MD
001
MD
012
MD
011
SOE
00
SO
00
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
0
1
1
0/1
1
1
0
1
0
1
1
0/1
Note1 Note1
Note3
Note3
TXE RXE PM11 P11 PM12 P12
00
01
Operation mode
Pin Function
P11/LRxD1/
INTPLR1/
SI00/RxD0/
TI11/TO11
P12/
SO00/TxD0/
TI12/TO12/
INTP2
Operation stop
mode
P11/LRxD1/
INTPLR1/
SI00/RxD0/
TI11/TO11
P12/
SO00/TxD0/
TI12/TO12/
INTP2
UART0 reception
RxD0
P12/
TI12/TO12/
INTP2
0
1
UART0
transmission
P11/LRxD1/
INTPLR1/
TI11/TO11
TxD0
0
1
UART0
transmission/
reception
RxD0
TxD0
1
1
1
0
1
1
1
Note2 Note2 Note2 Note2
Note2 Note2
RL78/D1A
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
Notes 1. The SE0 register is a read-only status register which is set using the SS0 and ST0 registers.
2. This pin can be set as a port function pin or other alternate function pin.
3. This is 0 or 1, depending on the communication operation. For details, refer to 12.3 (12) Serial output register m (SOm).
Caution
The shaded pins are provided at some ports. Select either port by using the corresponding register.
CHAPTER 12 SERIAL ARRAY UNIT
748
RL78/D1A
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
In the RL78/D1A, two asynchronous serial interface LIN-UART (UARTF) are provided.
13.1 Features
Maximum transfer rate: 1 Mbps (using dedicated baud rate generator)
Full-duplex communication: Internal LIN-UART receive data register n (UFnRX)
Internal LIN-UART transmit data register n (UFnTX)
2-pin configuration:
LTxDn: Transmit data output pin
LRxDn: Receive data input pin
Reception data/reception error detection function
Parity error
Framing error
Overrun error
Function to detect consistency errors in LIN communication data
Function to detect successful BF reception
ID parity error
Checksum error
Response preparation error
ID match function
Expansion bit detection function
Interrupt sources: 3
Reception complete interrupt (INTLRn)
Transmission interrupt (INTLTn)
Status interrupt (INTLSn)
Character length: 7, 8 bits
Communication with 9-bit data length possible by expansion bit setting
When an expansion bit is at the expected level, the received data can be compared with 8-bit data set in a
register in advance
Internal 3-bit prescaler
Parity function: Odd, even, 0, none
Transmission stop bit: 1, 2 bits
On-chip dedicated baud rate generator
MSB-/LSB-first transfer selectable
Transmit/receive data inverted input/output possible
Guarantee for stop bit of reception (suspension of transmission start during stop bit of reception when starting
transmission possible)
Remark n = 0, 1
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
749
RL78/D1A
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
Transmission/reception function in the LIN (Local Interconnect Network) communication format
13 to 20 bits selectable for BF transmission
Recognition of 11 bits or more in the LIN communication format possible for BF reception
BF reception flag provided
Detection of new BF reception possible during data communication
Function to check consistency of transmit data provided (function to detect mismatches by comparing transmit
data and receive data)
Automatic slave baud rate setting
Automatic checksum generation function provided (function to automatically calculate the checksum during
response transmission or response reception)
ID parity check function provided (function to automatically check the parity bit of the PID received)
Remark
LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol
intended to aid the cost reduction of an automotive network.
LIN communication is single-master communication, and up to 15 slaves can be connected to one master.
The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the LIN
master via the LIN network.
Normally, the LIN master is connected to a network such as CAN (Controller Area Network).
In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that
complies with ISO9141.
In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and
corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave is
14% or less.
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13.2 Configuration
Figure 13-1. Block Diagram of Asynchronous Serial Interface LIN-UART
Internal bus
INTLT
INTLR
INTLS
Interrupt
control
circuit
Reception unit
Comparison
UFnBUFn to
UFnBUF8
UF0BUFn
UFnID
Receive shift
register
LRxD0 pin
Transmission
unit
UFnBUCTL
UFnRX
UF0BUFn
UF0BUFn
UFnBUF0
UFnBUF0
UFnBUFn
UFnTX
(UFnTXB)
UFnWTX
(UFnWTXB)
Transmit shift
register
Transmit/
receive data
comparison
Filter
Reception
controller
Transmission
controller
Selector
Baud rate
generatorNote
Baud rate
generatorNote
Selector
LTxD0 pin
Prescaler
fCLK
Automatic baud rate
setting circuit
UFnSTR
UFnEN
UFnCTL1
UFnCTL0
UFnSTC
UFnOPT1
UFnOPT0
UFnOPT2
Peripheral enable register X (PERX)
Internal bus
Note For the configuration of the baud rate generator, see Figure 13-72 Configuration of Baud Rate Generator.
Remark n = 0, 1
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LIN-UART consists of the following hardware units.
Table 13-1. Configuration of LIN-UARTn
Item
Registers
Configuration
Peripheral enable register 0 (PER0)
LIN-UARTn control registers 0, 1 (UFnCTL0, UFnCTL1)
LIN-UARTn option registers 0 to 2 (UFnOPT0 to UFnOPT2)
LIN-UARTn status register (UFnSTR)
LIN-UARTn status clear register (UFnSTC)
LIN-UARTn receive shift register
LIN-UARTn receive data register (UFnRX)
LIN-UARTn 8-bit receive data register (UFnRXB)
LIN-UARTn transmit shift register
LIN-UARTn transmit data register (UFnTX)
LIN-UARTn 8-bit transmit data register (UFnTXB)
LIN-UARTn wait transmit data register (UFnWTX)
LIN-UARTn 8-bit wait transmit data register (UFnWTXB)
LIN-UARTn ID setting register (UFnID)
LIN-UARTn buffer registers 0 to 8 (UFnBUF0 to UFnBUF8)
LIN-UARTn buffer control register (UFnBUCTL)
Serial communication pin select register 0, 1 (STSEL0, STSEL1)
Port mode register 1, 7, 13 (PM1, PM7, PM13)
Remark n = 0, 1
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13.3 Control Registers
(1) Peripheral enable register 0 (PER0)
The PER0 register is used to set whether to use each peripheral hardware unit. Power consumption and noise can
be reduced, because clock supply will be stopped for the hardware not to be used.
When using LIN-UART, be sure to set the bits of the LIN-UART to be used (bit 6 (LIN1EN) and bit 5 (LIN0EN)) to 1.
Set PER0 by using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 13-2. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H
PER0
After reset: 00H
R/W
RTCEN
LIN1EN
LIN0EN
SAU1EN
SAU0EN
TAU2EN
TAU1EN
TAU0EN
LIN1EN
0
LIN-UART1 input clock control
Stops input clock supply.
Writing to SFR to be used with LIN-UART1 is disabled.
LIN-UART1 is in reset state.
1
Supplies input clock.
Reading from and writing to SFR to be used with LIN-UART1 is enabled.
LIN0EN
0
LIN-UART0 input clock control
Stops input clock supply.
Writing to SFR to be used with LIN-UART0 is disabled.
LIN-UART0 is in reset state.
1
Supplies input clock.
Reading from and writing to SFR to be used with LIN-UART0 is enabled.
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(2) LIN-UARTn control register 0 (UFnCTL0)
The UFnCTL0 register is an 8-bit register that controls serial communication operation of LIN-UARTn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 10H.
Figure 13-3. Format of LIN-UARTn Control Register 0 (UFnCTL0) (1/2)
Address: F0240H (UF0CTL0), F0260H (UF1CTL0)
UFnCTL0
After reset: 10H
R/W
7
4
3
2
1
0
0
UFnTXE
UFnRXE
UFnDIR
UFnPS1
UFnPS0
UFnCL
UFnSL
(n = 0, 1)
UFnTXE
Transmission operation enable
0
Stops transmission operation.
1
Enables transmission operation.
The setting of the UFnTDL bit in the UFnOPT0 register is reflected in the LTxDn pin level,
irrespective of the value of the UFnTXE bit.
When clearing the transmission enable bit (UFnCTL0.UFnTXE) after transmission completion,
set (UFnOPT2.UFnITS = 1) a transmission interrupt upon transmission completion and confirm
that the transmission interrupt has been generated, or clear the bit after having confirmed that
the transmission status flag (UFnSTR.UFnTSF) has been cleared to “0” and communication has
been completed.
UFnRXE
0
Reception operation enable
Stops reception operation.
An interrupt is not generated and received data is not stored.
1
Enables reception operation.
UFnDIR
Communication direction mode (MSB/LSB) selection
0
MSB first
1
LSB first
Rewriting is possible only when UFnTXE = UFnRXE = 0.
To perform transmission and reception in the LIN communication format, set the UFnDIR bit to
“1”.
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Figure 13-3. Format of LIN-UARTn Control Register 0 (UFnCTL0) (2/2)
UFnPS1
UFnPS0
Parity selection during transmission
Parity selection during reception
0
0
No parity output
Reception with no parity
0
1
0 parity output
No parity check
1
0
Odd parity output
Odd parity check
1
1
Even parity output
Even parity check
Rewriting is possible only when UFnTXE = UFnRXE = 0.
If “Reception with no parity” or “Reception with 0 parity” is selected during reception, a parity
check is not performed.
Consequently, a status interrupt (INTLSn) is not generated with parity error, because the UFnPE
bit of the UFnSTR register is not set.
To perform transmission and reception in the LIN communication format, set the UFnPS1 and
UFnPS0 bits to “00”.
UFnCL
Specification of data character length of 1 frame of transmit/receive data
0
7 bits
1
8 bits
Rewriting is possible only when UFnTXE = UFnRXE = 0.
To perform transmission and reception in the LIN communication format, set the UFnCL bit to “1”.
UFnSL
Specification of length of stop bit for transmit data
0
1 bit
1
2 bits
Rewriting is possible only when UFnTXE = UFnRXE = 0.
Caution
During receive data framing error detection, only the first bit of the stop bits is
checked, regardless of the value of the stop bit length select bit (UFnSL).
Remark
For details of parity, see 13.5.7 Parity types and operations.
(3) LIN-UARTn control register 1 (UFnCTL1)
See 13.10 (2) LIN-UARTn control register 1 (UFnCTL1) for details.
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(4) LIN-UARTn option register 0 (UFnOPT0)
The UFnOPT0 register is an 8-bit register that controls serial communication operation of LIN-UARTn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 13H.
Figure 13-4. Format of LIN-UARTn Option Register 0 (UFnOPT0) (1/3)
Address: F0241H (UF0OPT0), F0261H (UF1OPT0)
UFnOPT0
After reset: 14H
R/W
4
3
2
1
0
UFnBRF
UFnBRT
UFnBTT
UFnBLS2
UFnBLS1
UFnBLS0
UFnTDL
UFnRDL
(n = 0, 1)
UFnBRF
BF reception flag
0
When the UFnCTL0.UFnRXE = 0 is set. Also upon normal end of BF reception.
1
While waiting for successful BF reception (when the UFnBRT bit is set)
BF (Break Field) reception is judged during LIN communication.
The UFnBRF bit retains “1” when a BF reception error occurs, and is cleared to “0” when BF
reception is started again and ends normally. It cannot be cleared by instruction.
The UFnBRF bit is read-only.
Caution
When the UFnBRF bit is 1, whether BF reception has ended normally can be
judged by checking whether the low-level period is at least 11 bits, when a high
level, including noise, is input to the receive input data even for a moment. If the
low-level period is at least 11 bits, BF reception is judged to be performed
successfully.
When in BF reception enable mode during communication (UFnMD1, UFnMD0 =
10B), normal completion of BF reception can be confirmed by checking that the
successful BF reception flag (UFnBSF) is set to 1 when a status interrupt is
detected.
In BF reception enable mode during communication, a reception complete
interrupt is not generated even by setting the BF reception trigger bit. However,
the normal completion of BF reception can be confirmed also by checking that the
UFnBRF flag is 0 when a status interrupt is detected after setting the bit.
UFnBRT
BF reception trigger
0
1
BF reception trigger
This is the BF reception trigger bit during LIN communication, and when read, “0” is always read.
For BF reception, set (1) the UFnBRT bit to enable BF reception.
Set the UFnBRT bit after having set UFnCTL0.UFnRXE to “1”.
The status flag will not be updated, an interrupt request signal will not be generated, and data will
not be stored.
This bit can only be set again when the UFnBRF bit is 0.
When BF reception is enabled during communication, BF reception is detected as the low-level
period between when the UFnBRT bit is set and when the rising edge of the reception input data
is detected. Therefore, a BF will be detected even if the UFnBRT bit is set during BF reception.
Cautions 1. To release a BF reception enable state without receiving a BF, UFnRXE must be
cleared to 0.
2. Transmitting data while UFnDCS and UFnBRF are “1” is prohibited. BF
transmission, however, can be performed.
3. Setting the UFnBRT bit in automatic baud rate mode (UFnMD1, UFnMD0 = 11B)
is prohibited.
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Figure 13-4. Format of LIN-UARTn Option Register 0 (UFnOPT0) (2/3)
UFnBTT
BF transmission trigger
0
1
BF transmission trigger
This is the BF transmission trigger bit during LIN communication, and when read, “0” is always
read.
Set the UFnBTT bit after having set UFnCTL0.UFnTXE to “1”.
Cautions 1. Setting both the next transmit data and the UFnBTT bit during data
transmission is prohibited.
Also, even if the UFnBTT bit is set during a BF transmission, it is invalid (a BF
transmission is performed once and ends).
2. Completion of a BF transmission can be judged by checking that the UFnTSF
bit is “0” after the BF transmission trigger bit has been set. If the next transmit
data has been written to the UFnTX register during the BF transmission,
however, the UFnTSF bit will not be cleared when transmitting the BF has been
completed, but will retain “1”.
When in BF reception enable mode during communication (UFnMD1, UFnMD0 =
10B), completion of a BF transmission can also be judged by checking that the
successful BF reception flag (UFnBSF) is “1” after a status interrupt has been
detected.
3. Setting the UFnBTT bit is prohibited in automatic baud rate mode (UFnMD1,
UFnMD0 = 11B).
Remark Before setting UFnOPT0.UFnBTT to “1” and starting BF communication, check that no
data transfer is being processed (UFnSTR.UFnTSF = 0).
UFnBLS2
UFnBLS1
UFnBLS0
1
0
1
13-bit output (reset value)
BF length selection bit
1
1
0
14-bit output
1
1
1
15-bit output
0
0
0
16-bit output
0
0
1
17-bit output
0
1
0
18-bit output
0
1
1
19-bit output
1
0
0
20-bit output
This bit can be set when UFnCTL0.UFnTXE is “0”.
UFnTDL
Transmit data level bit
0
Normal output of transfer data
1
Inverted output of transfer data
The LTxDn output value can be inverted by using the UFnTDL bit.
This bit can be set when UFnCTL0.UFnTXE is “0”.
Cautions 1. The LTxDn output level is inverted by controlling the UFnTDL bit, regardless of
the value of the UFnTXE bit. Consequently, if the UFnTDL bit is set to “1” even
when operation is disabled, the LTxDn output becomes low level.
2. To perform transmission and reception in the LIN communication format, set
UFnTDL to “0”.
Remark n = 0, 1
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Figure 13-4. Format of LIN-UARTn Option Register 0 (UFnOPT0) (3/3)
UFnRDL
Receive data level bit
0
Normal input of transfer data
1
Inverted input of transfer data
The LRxDn input value can be inverted by using the UFnRDL bit.
This bit can be set when UFnCTL0.UFnRXE is “0”.
Cautions 1. Be sure to enable reception (UFnRXE = 1) after having changed the UFnRDL bit.
When the UFnRDL bit is changed after reception has been enabled, the start bit
will be falsely detected, depending on the pin level at that time.
2. To perform transmission and reception in the LIN communication format, set
UFnRDL to “0”.
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(5) LIN-UARTn option register 1 (UFnOPT1)
The UFnOPT1 register is an 8-bit register that controls serial communication operation of LIN-UARTn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Caution Set the UFnOPT1 register when UFnTXE and UFnRXE are “0”. Only the UFnEBC bit, however,
can be changed even if UFnTXE is “1” or UFnRXE is “1”.
See 13.8.3 Expansion bit mode
reception (with data comparison) for details.
Figure 13-5. Format of LIN-UARTn Option Register 1 (UFnOPT1) (1/3)
Address: F0244H (UF0OPT1), F0264H (UF1OPT1)
UFnOPT1
After reset: 00H
R/W
7
6
4
3
2
1
0
UFnEBE
UFnEBL
UFnEBC
UFnIPCS
UFnACE
UFnMD1
UFnMD0
UFnDCS
(n = 0, 1)
UFnEBE
Expansion bit enable bit
0
Disables expansion bit operation.
(Transmission and reception are performed in the data length (7, 8 bits) set to
UFnCTL0.UFnCL.)
1
Enables expansion bit operation.
(Transmission
and
reception
are
performed
in
data
length
(9
bits)
when
UFnCTL0.UFnCL is “1”.)
Cautions 1. To perform transmission and reception in 9-bit units by setting (1) the UFnEBE
bit, the data length must be set to 8 bits (UFnCL = 1). If the data length is set to
7 bits (UFnCL = 0), the setting of the UFnEBE bit will be invalid.
2. To perform transmission and reception in the LIN communication format, set
UFnEBE to “0”.
3. The expansion bit is included in parity check.
UFnEBL
Expansion bit detection level select bit
0
Selects expansion bit value “0” as expansion bit detection level.
1
Selects expansion bit value “1” as expansion bit detection level.
If the level selected by the UFnEBL bit is detected as the expansion bit when the expansion bit has
been enabled (UFnCL = UFnEBE = 1), a status interrupt request signal (INTLSn) will be generated
and an expansion bit detection flag (UEnEBD) will be set.
If the inversion level is detected as the expansion bit, a reception complete interrupt request signal
(INTLRn) will be generated, but an expansion bit detection flag will not be set.
Remark The UFnEBL bit becomes valid only if UFnCL = UFnEBE = 1. See 13.8.2 Expansion bit
mode reception (no data comparison) and 13.8.3 Expansion bit mode reception (with
data comparison) for details.
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Figure 13-5. Format of LIN-UARTn Option Register 1 (UFnOPT1) (2/3)
UFnEBC
Expansion bit data comparison enable bit
0
No comparison
(INTLRn or INTLSn is always generated upon completion of data reception.)
1
Compares UFnRX register and UFnID register when the level selected for the UFnEBL
bit has been detected as the expansion bit.
(INTLSn is generated only when the UFnRX register and UFnID register have matched.)
The UFnEBC bit is used to enable comparison between the received data and the UFnID register
when the expansion bit has been enabled (UFnCL = UFnEBE = 1).
Remark The UFnEBC bit becomes valid only if UFnCL = UFnEBE = 1. See 13.8.2 Expansion bit
mode reception (no data comparison) and 13.8.3 Expansion bit mode reception (with
data comparison) for details.
UFnIPCS
ID parity check select bit
0
No automatic ID parity check
(Calculating the parity of the PID by using software and checking are required.)
1
Automatic ID parity check
The UFnIPCS bit is used to select how to handle automatic checking of the parity bit of the
received PID, when in automatic baud rate mode (UFnMD1, UFnMD0 = 11B).
If UFnIPCS is “1”, the parity bit is checked when the PID received in LIN communication is stored
into the UFnID register. When an incorrect result has been detected, an ID parity error flag
(UFnIPE) will be set and a status interrupt request signal (INTLSn) will be generated.
Remark The UFnIPCS bit becomes valid only in the automatic baud rate mode (UFnMD1, UFnMD0
= 11B). See 13.7.3 ID parity check function for details.
UFnACE
Automatic checksum enable bit
0
Disables automatic checksum calculation.
Response transmission: Checksum must be calculated by using software and set to a
buffer.
Response reception:
Checksum must be calculated from the data stored into the
buffer by using software, and compared and checked with the
checksum obtained via communication.
1
Enables automatic checksum calculation.
Response transmission: Checksum is automatically calculated from the data set to a
buffer and is automatically appended at the end of response
transmission.
Response reception:
Checksum is automatically calculated from the data stored
into the buffer and is automatically compared and checked
with the checksum obtained via communication.
The UFnACE bit is used to select how to handle automatic checksum calculation during response
transmission and response reception, when in automatic baud rate mode (UFnMD1, UFnMD0 =
11B).
When response reception is performed while UFnACE is “1”, the checksum received in LIN
communication will be checked when it is stored into a receive buffer. When an incorrect result
has been detected, a checksum error flag (UFnCSE) will be set and a status interrupt request
signal (INTLSn) will be generated.
Remark The UFnACE bit becomes valid only in the automatic baud rate mode (UFnMD1, UFnMD0
= 11B). See 13.7.4 Automatic checksum function for details.
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Figure 13-5. Format of LIN-UARTn Option Register 1 (UFnOPT1) (3/3)
UFnMD1
UFnMD0
LIN-UART operation mode select bit
0
0
Normal UART mode
0
1
Setting prohibited
1
0
LIN communication: BF reception enable mode during communication
Detects a new Break Field during data communication.
(When a low level has been detected at the stop bit position, a wait is
performed until the next high level is detected and a new BF reception is
recognized if the low-level period is at least 11 bits.)
1
1
LIN communication: Automatic baud rate mode
Cautions 1. Setting to automatic baud rate mode (UFnMD1, UFnMD0 = 11B) is prohibited for
a LIN communication master.
2. Be sure to also set the UFnDCS bit to “1” when in BF reception enable mode
during communication (UFnMD1, UFnMD0 = 10B) or in automatic baud rate
mode (UFnMD1, UFnMD0 = 11B).
Remark When in BF reception enable mode during communication (UFnMD1, UFnMD0 = 0B)during
LIN communication, set TMLINn to 1 and select the input signal of the serial data input pin
(LRxDn) as a timer input.
UFnDCS
Data consistency check select bit
0
Does not check data consistency.
1
Checks data consistency.
The UFnDCS bit is used to select how to handle a data consistency check when transmitting data
via LIN communication. For details, see 13.5.8 Data consistency check.
When UFnDCS is “1”, transmit data and receive data will be compared when transmitting data via
LIN communication. When a mismatch is detected, a data consistency error flag (UFnDCE) will
be set and a status interrupt request signal (INTLSn) will be generated.
Cautions 1. When using LIN communication, the UFnDCS bit can be set. Otherwise, clear
the UFnDCS bit to “0”.
2. When setting (1) the UFnDCS bit, fix the data bit length to 8 bits. Appending a
parity bit is prohibited.
3. Be sure to also set the UFnDCS bit to “1” when in BF reception enable mode
during communication (UFnMD1, UFnMD0 = 10B) or in automatic baud rate
mode (UFnMD1, UFnMD0 = 11B).
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(6) LIN-UARTn option register 2 (UFnOPT2)
The UFnOPT2 register is an 8-bit register that controls serial communication operation of LIN-UARTn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Figure 13-6. Format of LIN-UARTn Option Register 2 (UFnOPT2)
Address: F0245H (UF0OPT2), F0265H (UF1OPT2)
UFnOPT2
After reset: 00H
R/W
7
6
5
4
3
2
1
0
0
0
0
0
0
UFnRXFL
UFnITS
(n = 0, 1)
UFnRXFL
Bit to select use of receive data noise filter
0
Uses noise filter.
1
Does not use noise filter.
The UFnRXFL bit is used to select use of the noise filter. See 13.9 Receive Data Noise Filter for
details.
Caution
Be sure to set the UFnRXFL bit when UFnCTL0.UFnRXE is “0”.
UFnITS
Transmission interrupt (INTLTn) generation timing select bit
0
Outputs transmission interrupt request upon transmission start.
1
Outputs transmission interrupt request upon transmission completion.
Caution Be sure to set the UFnITS bit when UFnCTL0.UFnTXE is “0”.
The UFnITS bit can be changed to 1 after transmission of the last data is started
only when completion of transmitting the last data must be known during
successive transmission (UFnITS = 0). However, the change must be completed
before the transmission is completed.
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(7) LIN-UARTn status register (UFnSTR)
The UFnSTR register is a 16-bit register that displays the LIN-UARTn communication status and reception error
contents.
This register is read-only, in 16-bit units.
Reset sets this register to 0000H.
Caution Flags other than the UFnTSF and UFnRSF flags are retained until the target bits of the LINUARTn status clear register (UFnSTC) are written (“1”) and then cleared. To clear a status flag,
use a 16-bit manipulation instruction to write (“1”) and clear the target bits of the LIN-UARTn
status clear register (UFnSTC).
Figure 13-7. Format of LIN-UARTn Status Register (UFnSTR) (1/6)
Address: F0246H, F0247H (UF0STR), F0266H, F0267H (UF1STR)
UFnSTR
(n = 0, 1)
After reset: 0000H
R
15
14
13
12
11
10
9
8
0
UFnIPE
UFnCSE
UFnRPE
UFnHDC
UFnBUC
UFnIDM
UFnEBD
7
6
5
4
3
2
1
0
UFnTSF
UFnRSF
0
UFnBSF
UFnDCE
UFnPE
UFnFE
UFnOVE
UFnIPE
ID parity error flag
0
No ID parity error has occurred.
1
An ID parity error has occurred.
Parity of received PID is incorrect
The UFnIPE bit is a flag indicating the check status by the ID parity check function. It becomes
“1”, if the parity of the received PID is incorrect when in automatic baud rate mode (UFnMD1,
UFnMD0 = 11B). See 13.7.3 ID parity check function for details.
The UFnIPE bit will not be cleared until “1” is written to the UFnCLIPE bit of the UFnSTC register,
because the UFnIPE bit is a cumulative flag. It will not be set if the ID parity check function has
been disabled (UFnIPCS = 0).
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Figure 13-7. Format of LIN-UARTn Status Register (UFnSTR) (2/6)
UFnCSE
Checksum error flag
0
No checksum error has occurred.
1
A checksum error has occurred.
Result of comparing checksum automatically calculated from data stored into buffer and
checksum obtained via communication is incorrect during response reception
The UFnCSE bit is a flag indicating the check status by the automatic checksum function. It
becomes “1” if the received checksum is incorrect when in automatic baud rate mode (UFnMD1,
UFnMD0 = 11B) and during response reception. See 13.7.4 Automatic checksum function for
details.
The UFnCSE bit will not be cleared until “1” is written to the UFnCLCSE bit of the UFnSTC
register, because the UFnCSE bit is a cumulative flag. It will not be set if the automatic checksum
function has been disabled (UFnACE = 0).
Cautions 1. The check sum error flag will not be set during response transmission. Perform
a data consistency check to check for errors.
2. Receive data will be stored in the UFnRX register during response transmission.
However, no overrun error will be set, even if the receive data is not read.
Consequently, the received check sum can be checked by reading the UFnRX
register after the reception completion interrupt has occurred.
UFnRPE
Response preparation error flag
0
No response preparation error has occurred.
1
A response preparation error has occurred.
< Response preparation error source>
Response could not be prepared before completion of receiving first byte of receive data
after header reception
The UFnRPE bit is a flag indicating the check status by the response preparation detection
function. It becomes “1”, if a response (setting of UFnNO, UFnRRQ bits) could not be prepared
in automatic baud rate mode (UFnMD1, UFnMD0 = 11B). See 13.7.2 Response preparation
error detection function for details.
The UFnRPE bit will not be cleared until “1” is written to the UFnCLRPE bit of the UFnSTC
register, because the UFnRPE bit is a cumulative flag. It will not be set when not in automatic
baud rate mode (UFnMD1, UFnMD0 = 00B or 10B).
UFnHDC
0
1
Header reception completion flag
Header reception is not completed.
Receiving header has been completed
The UFnHDC bit is a flag indicating completion of receiving a header. It becomes “1” when
receiving the header has been completed when in automatic baud rate mode (UFnMD1, UFnMD0
= 11B). See 13.7.1 Automatic baud rate setting function for details.
The UFnHDC bit will not be cleared until “1” is written to the UFnCLHDC bit of the UFnSTC
register, because the UFnHDC bit is a cumulative flag. It will not be set when not in automatic
baud rate mode (UFnMD1, UFnMD0 = 00B or 10B).
Caution This flag will not be set by an error during PID reception.
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CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
Figure 13-7. Format of LIN-UARTn Status Register (UFnSTR) (3/6)
UFnBUC
Buffer transmission/reception completion flag
0
Buffer transmission/reception is not completed.
1
Buffer transmission/reception is completed
The set number of data is transmitted or received.
(only when transmitted when in normal UART mode)
The UFnBUC bit is a flag indicating the data transmission and reception status of a buffer. It
becomes “1” when the set number of data items have been transmitted or received
without an error occurring. See 13.6.1 UART buffer mode transmission and 13.7 LIN
Communication Automatic Baud Rate Mode for details.
The UFnBUC bit will not be cleared until “1” is written to the UFnCLBUC bit of the UFnSTC
register, because the UFnBUC bit is a cumulative flag. It will be set only when in normal UART
mode (UFnMD1, UFnMD0 = 00B) or automatic baud rate mode (UFnMD1, UFnMD0 = 11B).
UFnIDM
ID match flag
0
The ID does not match.
1
The IDdoes match
When 8 bits of receive data, excluding expansion bit, have matched with UFnID register
value set in advance
The UFnIDM bit is a flag indicating the result of comparing the 8 bits of receive data, excluding
the expansion bit, and the UFnID register value set in advance when expansion bit data
comparison has been enabled (UFnEBC = 1) by enabling the expansion bit (UFnCL = UFnEBE =
1). The comparison will be performed with the data for which the level set by using the expansion
bit detection level select bit (UFnEBL) has been detected. The UFnIDM bit becomes “1” when
the comparison result has matched. See 13.8.3 Expansion bit mode reception (with data
comparison) for details.
The UFnIDM bit will not be cleared until “1” is written to the UFnCLIDM bit of the UFnSTC register,
because the UFnIDM bit is a cumulative flag. It will not be set when the expansion bit has not
been enabled and expansion bit data comparison has not been enabled (UFnCL = UFnEBE =
UFnEBC = 1).
UFnEBD
Expansion bit detection flag
0
An extension bit is not detected
1
An extension bit is detected
When level set by using expansion bit detection level select bit (UFnEBL) has been
detected for expansion bit
The UFnEBD bit is a flag indicating detection of the level set by using the expansion bit detection
level select bit (UFnEBL) when the expansion bit has been enabled (UFnCL = UFnEBE = 1). It
becomes “1” when the setting level has been detected. See 13.8.2 Expansion bit mode
reception (no data comparison) and 13.8.3 Expansion bit mode reception (with data
comparison) for details.
The UFnEBD bit will not be cleared until “1” is written to the UFnCLEBD bit of the UFnSTC
register, because the UFnEBD bit is a cumulative flag. It will not be set when the expansion bit
has been disabled (UFnEBE = 0).
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CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
Figure 13-7. Format of LIN-UARTn Status Register (UFnSTR) (4/6)
UFnTSF
0
Transmission status flag
A transmit operation is not performed.
When UFnCTL0.UFnTXE has been cleared to “0”
1
When there was no next transmit data after transmission completion, and at the
same time, BF transmit trigger bit (UFnBTT) has not been set
When there was no next transmit data in UFnTX, UFnWTX, UFnBUF0 to UFnBUF8
bit after BF transmission has ended
When the transmission after data consistency error detection is completed
A transmit operation is performed.
Writes to UFnTX, UFnWTX register
Note
When BF transmit trigger bit (UFnBTT) has been set
When the transmission request bit (UFnTRQ) is set
The UFnTSF bit is always “1” when successive transmission is performed.
To initialize the transmission unit, check that UFnTSF is “0” before performing initialization. If
initialization is performed while UFnTSF = 1, the transmission will be aborted midway.
If a BF is detected in BF reception enabled mode during communication and when transmitting
data, or if a BF/SF is detected in automatic baud rate mode and when transmitting data, the
UFnDCE flag will be set and the UFnTSF bit will be cleared when a status interrupt (INTLSn) is
issued.
Note Only during BF period
UFnRSF
0
1
Reception status flag
A receive operation is not performed.
When UFnCTL0.UFnRXE has been cleared to “0”
When at sampling point of stop bit (first bit) during reception
When UFnBRT = 1 is set
When a BF is detected in BF reception enabled mode during communication
When a BF/SF is detected in automatic baud rate mode
A receive operation is performed.
When a start bit is detected (when it is detected that the data is 0 at the sampling point
of the bit after the LRxDn falling edge is detected)
To initialize the reception unit, check that UFnRSF is “0” before performing initialization.
initialization is performed while UFnRSF = 1, the reception will be aborted midway.
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CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
Figure 13-7. Format of LIN-UARTn Status Register (UFnSTR) (5/6)
UFnBSF
Successful BF reception flag
0
BF reception is not successfully performed.
1
BF reception is successfully performed.
When successive low levels (BF) of at least 11 bits have been received
The UFnBSF bit is a flag indicating that receiving a BF has been performed successfully. It
becomes “1” when successive low levels (BF) of at least 11 bits have been received when in BF
reception enable mode during communication (UFnMD1, UFnMD0 = 10B) (This occurs at the
same time as the status interrupt (INTLSn) is issued upon the detection of the rising edge of the
LRxDn pin.).
The start of a new frame slot must be checked by reading the UFnBSF bit via status interrupt
servicing, because the BF may also be received during data communication when in BF
reception enable mode during communication.
The UFnBSF bit will not be cleared until “1” is written to the UFnCLBSF bit of the UFnSTC
register, because the UFnBSF bit is a cumulative flag. It will not be set when not in BF reception
enable mode during communication (UFnMD1, UFnMD0 = 10B).
UFnDCE
Data consistency error flag
0
No data consistency error has occurred.
1
A data consistency error has occurred.
When transmit data and receive data do not match in LIN communication
When the data consistency check select bit is set (UFnDCS = 1), the transmit data and receive
data are compared upon data transmission. The UFnDCE bit becomes “1” at the same time as
the status interrupt (INTLSn) is issued when a mismatch has been detected.
The UFnDCE bit will not be cleared until “1” is written to the UFnCLDCE bit of the UFnSTC
register, because the UFnDCE bit is a cumulative flag. When UFnDCS is “0”, the UFnDCE bit will
not be set.
Caution The next transfer will not be performed if a data consistency error is detected. See
13.5.8 Data consistency check for details.
UFnPE
0
1
Parity error flag
No parity error has occurred.
A parity error has occurred.
When parity of data and parity bit do not match during reception
The operation of the UFnPE bit depends on the settings of the UFnPS1 and UFnPS0 bits.
The UFnPE bit will not be cleared until “1” is written to the UFnCLPE bit of the UFnSTC register or
“0” is written to the UFnRXE bit of the UFnCTL0 register, because the UFnPE bit is a cumulative
flag. When UFnPS1 and UFnPS0 are “0xB”, the UFnPE bit will not be set. (x: Don’t care)
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CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
Figure 13-7. Format of LIN-UARTn Status Register (UFnSTR) (6/6)
UFnFE
Framing error flag
0
No framing error has occurred.
1
A framing error has occurred.
< Framing error source>
When no stop bit is detected during reception
Only the first bit of the receive data stop bits is checked, regardless of the setting value of the
UFnSL bit.
The UFnFE bit will not be cleared until “1” is written to the UFnCLFE bit of the UFnSTC register or
“0” is written to the UFnRXE bit of the UFnCTL0 register, because the UFnFE bit is a cumulative
flag.
UFnOVE
Overrun error flag
0
No overrun error has occurred.
1
An overrun error has occurred.
< Overrun error source>
When receive data has been stored into the UFnRX register and the next receive
operation is completed before that receive data has been read
When an overrun error has occurred, the data is discarded without the next receive data being
written to the UFnRX register.
The UFnFE bit will not be cleared until “1” is written to the UFnCLFE bit of the UFnSTC register or
“0” is written to the UFnRXE bit of the UFnCTL0 register, because the UFnFE bit is a cumulative
flag. It will not be set in automatic baud rate mode (UFnMD1, UFnMD0 = 11B).
Caution
If no status interrupt due to an ID mismatch is issued while expansion bit data
comparison is enabled (UFnEBE = 1 and UFnEBC = 1), as receive data will not be
stored in the UFnRX register, the UFnOVE flag will not be set even if the receive
data is not read. Furthermore, when transmitting in automatic baud rate mode, the
receive data will be always stored in the UFnRX register, but the UFnOVE flag will
not be set even if the receive data is not read.
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CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
(8) LIN-UARTn status clear register (UFnSTC)
The UFnSTC register is a 16-bit register that is used to clear an LIN-UARTn status flag.
This register can be read and written, in 16-bit units.
Reset sets this register to 0000H.
Caution An LIN-UART status register (UFnSTR) flag can be cleared by writing “1” to a corresponding bit.
0 will be read if the bit is read.
Figure 13-8. Format of LIN-UARTn Status Clear Register (UFnSTC) (1/2)
Address: F0248H, F0249H (UF0STC), F0268H, F0269H (UF1STC)
15
UFnSTC
(n = 0, 1)
0
14
13
11
6
5
0
0
0
4
3
1
Clears (0) the UFnIPE bit of the UFnSTR register.
Trigger does not operate.
1
Clears (0) the UFnCSE bit of the UFnSTR register.
Trigger does not operate.
1
Clears (0) the UFnRPE bit of the UFnSTR register.
Trigger does not operate.
1
Clears (0) the UFnHDC bit of the UFnSTR register.
0
UFnCLFE UFnCLOVE
Channel n buffer transmission/reception completion flag clear trigger
0
Trigger does not operate.
1
Clears (0) the UFnBUC bit of the UFnSTR register.
UFnCLIDM
Channel n ID match flag clear trigger
0
Trigger does not operate.
1
Clears (0) the UFnIDM bit of the UFnSTR register.
Channel n expansion bit detection flag clear trigger
0
Trigger does not operate.
1
Clears (0) the UFnEBD bit of the UFnSTR register.
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Channel n header reception completion flag clear trigger
0
UFnCLEBD
2
Channel n response preparation error flag clear trigger
0
UFnCLBUC
8
Channel n checksum error flag clear trigger
0
UFnCLHDC
9
Channel n ID parity error flag clear trigger
Trigger does not operate.
UFnCLRPE
10
UFnCLBSF UFnCLDCE UFnCLPE
0
UFnCLCSE
R/W
UFnCLIPE UFnCLCSE UFnCLRPE UFnCLHDC UFnCLBUC UFnCLIDM UFnCLEBD
7
UFnCLIPE
12
After reset: 0000H
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CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
Figure 13-8. Format of LIN-UARTn Status Clear Register (UFnSTC) (2/2)
UFnCLBSF
Channel n successful BF reception flag clear trigger
0
Trigger does not operate.
1
Clears (0) the UFnBSF bit of the UFnSTR register.
UFnCLDCE
Channel n data consistency error flag clear trigger
0
Trigger does not operate.
1
Clears (0) the UFnDCE bit of the UFnSTR register.
UFnCLPE
Channel n parity error flag clear trigger
0
Trigger does not operate.
1
Clears (0) the UFnPE bit of the UFnSTR register.
UFnCLFE
Channel n framing error flag clear trigger
0
Trigger does not operate.
1
Clears (0) the UFnFE bit of the UFnSTR register.
UFnCLOVE
Channel n overrun error flag clear trigger
0
Trigger does not operate.
1
Clears (0) the UFnOVE bit of the UFnSTR register.
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CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
(9) LIN-UARTn transmit data register (UFnTX)
The UFnTX register is a 16-bit register that is used to set transmit data.
This register can be read or written in 16-bit units. When the UFnTX register is read or written in 8-bit units, it can
be accessed as the UFnTXB register.
When no buffer is used and no data consistency error has been detected (UFnDCE = 0) in a transmission enable
state (UFnTXE = 1), transmission is started by writing transmit data to the UFnTX register.
When UFnEBE = 0, transmit data of a character length specified by the UFnCL bit will be transmitted.
When UFnEBE = UFnCL = 1, transmit data of 9-bit length will be transmitted. See 13.5.1 Data format for the
transmit data format.
The last data written to the UFnTX register before it is loaded to the transmit shift register is to be transmitted.
When UFnITS is “0”, successive transmission can be performed by writing the next transmit data to the UFnTX
register after a transmission interrupt request has been generated. When the next transmit data is written before a
transmission interrupt request is generated, the previously written data will be overwritten and only the subsequent
data will be transmitted.
Reset input sets this register to 0000H.
Figure 13-9. Format of LIN-UARTn Transmit Data Register (UFnTX)
Address: FFF48H, FFF49H (UF0TX), FFF4CH, FFF4DH (UF1TX)
After reset: 0000H
R/W
15
14
13
12
11
10
9
8
UFnTX
0
0
0
0
0
0
0
UFnTX.8
(n = 0, 1)
7
6
5
4
3
2
1
0
UFnTX.7
UFnTX.6
UFnTX.5
UFnTX.4
UFnTX.3
UFnTX.2
UFnTX.1
UFnTX.0
When the data length is specified as 7 bits (UFnCL = 0):
During LSB-first transmission, bits 6 to 0 of the UFnTX register will be transferred as transmit data.
During MSB-first transmission, bits 7 to 1 of the UFnTX register will be transferred as transmit data.
Cautions 1.
If the UFnTX register is written while transmission is disabled (UFnTXE = 0), it will not
operate as a transmission start trigger. Consequently, no transmission will be started, even
if transmission is enabled after having written to the UFnTX register while transmission was
disabled.
2.
When the UFnTX register is written in 8-bit units (when the UFnTXB register is written), “0” is
written to the UFnTX.8 bit.
3.
Writing to the UFnTX register is prohibited when using the UFnBUF0 to UFnBUF8 registers.
4.
When using automatic checksum function, set 0000H in the UFnTX register before starting
communication.
Remarks 1.
When UFnOPT2.UFnITS is “0”, successive transmission can be performed by writing the next
transmit data before transmission is completed, after a transmission interrupt request signal
(INTLTn) has been generated.
2.
The UFnTX8 bit is an expansion bit when expansion bits are enabled (UFnEBE = UFnCL = 1).
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CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
(10) LIN-UARTn 8-bit transmit data register (UFnTXB)
The UFnTXB register is an 8-bit register that is used to set transmit data.
This register can be read or written in 8-bit units.
When no buffer is used and no data consistency error has been detected (UFnDCE = 0) in a transmission enable
state (UFnTXE = 1), transmission is started by writing transmit data to the UFnTXB register.
When UFnEBE = 0, transmit data of a character length specified by the UFnCL bit will be transmitted. For detail of
the transmit data format, see 13.5.1 Data format.
The last data written to the UFnTXB register before it is loaded to the transmit shift register is to be transmitted.
When UFnITS is “0”, successive transmission can be performed by writing the next transmit data to the UFnTXB
register after a transmission interrupt request has been generated. When the next transmit data is written before a
transmission interrupt request is generated, the previously written data will be overwritten and only the subsequent
data will be transmitted.
Reset input sets this register to 00H.
Figure 13-10. Format of LIN-UARTn 8-bit Transmit Data Register (UFnTXB)
Address: FFF48H (UF0TXB), FFF4CH (UF1TXB)
UFnTXB
After reset: 00H
R/W
7
6
5
4
3
2
1
0
UFnTX.7
UFnTX.6
UFnTX.5
UFnTX.4
UFnTX.3
UFnTX.2
UFnTX.1
UFnTX.0
(n = 0, 1)
When the data length is specified as 7 bits (UFnCL = 0):
During LSB-first transmission, bits 6 to 0 of the UFnTXB register will be transferred as transmit data.
During MSB-first transmission, bits 7 to 1 of the UFnTXB register will be transferred as transmit data.
Cautions 1.
If the UFnTXB register is written while transmission is disabled (UFnTXE = 0), it will not
operate as a transmission start trigger. Consequently, no transmission will be started, even
if transmission is enabled after having written to the UFnTXB register while transmission
was disabled.
2.
When the UFnTXB register is written, “0” is written to the UFnTX.8 bit of UFnTX register.
3.
Writing to the UFnTXB register is prohibited when using the UFnBUF0 to UFnBUF8 registers.
4.
When using automatic checksum function, set 00H in the UFnTXB register before starting
communication.
Remark
When UFnOPT2.UFnITS is “0”, successive transmission can be performed by writing the next
transmit data before transmission is completed, after a transmission interrupt request signal
(INTLTn) has been generated.
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CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
(11) 8-bit transmit data register for LIN-UARTn wait (UFnWTX)
The UFnWTX register is a 16-bit register dedicated to delaying starting transmission until the stop bit of reception
is completed during a LIN communication.
This register is write-only, in 16-bit units. When the UFnWTX register is write in 8-bit units, it can be accessed as
the UFnWTXB register.
The stop bit length of reception when reception is switched to transmission is guaranteed for the UFnWTX register.
See 13.5.11 Transmission start wait function for details.
The UFnWTX register value will be read when the UFnWTX register has been read.
Reset input sets this register to 0000H.
Figure 13-11. Format of 8-bit transmit data register for LIN-UARTn wait (UFnWTX)
Address: F024AH, F024BH (UF0WTX), F026AH, F026BH (UF1WTX)
UFnWTX
(n = 0, 1)
After reset: 0000H
W
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
UFnWTX.8
7
6
5
4
3
2
1
0
UFnWTX.7 UFnWTX.6 UFnWTX.5 UFnWTX.4 UFnWTX.3 UFnWTX.2 UFnWTX.1 UFnWTX.0
Cautions 1.
Writing to the UFnWTX register is prohibited other than when reception is switched to
2.
When the UFnWTX register is accessed in 8-bit units (when the UFnWTXB register is
transmission (such as during transmission).
accessed), “0” is written to the UFnWTX.8 bit.
3.
Writing to the UFnWTX register is prohibited when using the UFnBUF0 to UFnBUF8 registers.
Remark The UFnWTX.8 bit is an expansion bit when expansion bits are enabled (UFnEBE = UFnCL = 1).
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(12) LIN-UARTn 8-bit wait transmit data register (UFnWTXB)
The UFnWTXB register is an 8-bit register dedicated to delaying starting transmission until the stop bit of reception
is completed during a LIN communication.
This register is write-only, in 8-bit units.
The stop bit length of reception when reception is switched to transmission is guaranteed for the UFnWTXB
register.
See 13.5.11 Transmission start wait function for details.
The UFnTXB register value will be read when the UFnWTXB register has been read.
Reset input sets this register to 00H.
Figure 13-12. Format of LIN-UARTn 8-bit Wait Transmit Data Register (UFnWTXB)
Address: F024AH (UF0WTXB), F026AH (UF1WTXB)
7
6
5
After reset: 00H
4
3
W
2
1
0
UFnWTXB UFnWTX.7 UFnWTX.6 UFnWTX.5 UFnWTX.4 UFnWTX.3 UFnWTX.2 UFnWTX.1 UFnWTX.0
(n = 0, 1)
Cautions 1.
Writing to the UFnWTXB register is prohibited other than when reception is switched to
2.
When the UFnWTXB register is accessed in 8-bit units (when the UFnWTXB register is
transmission (such as during transmission).
accessed), “0” is written to the UFnWTX.8 bit of UFnWTX register.
3.
Writing to the UFnWTXB register is prohibited when using the UFnBUF0 to UFnBUF8
registers.
Remark The UFnWTX8 bit is an expansion bit when expansion bits are enabled (UFnEBE = UFnCL = 1).
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CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
(13) LIN-UARTn receive data register (UFnRX)
The UFnRX register is a 16-bit register that is used to store receive data.
Receive data of a character length specified by the UFnCL bit after reception completion will be stored into the
UFnRX register when not in automatic baud rate mode (UFnMD1, UFnMD0 = 00B/10B) and when UFnEBE is “0”.
When UFnEBE = UFnCL = 1, receive data of 9-bit length will be stored.
This register is read-only, in 16-bit units. When the UFnRX register is read in 8-bit units, it can be accessed as the
UFnRX register.
Reset input sets this register to 0000H.
Figure 13-13. Format of LIN-UARTn Receive Data Register (UFnRX)
Address: FFF4AH, FFF4BH (UF0RX), FFF4EH, FFF4FH (UF1RX)
After reset: 0000H
R
15
14
13
12
11
10
9
8
UFnRX
0
0
0
0
0
0
0
UFnRX.8
(n = 0, 1)
7
6
5
4
3
2
1
0
UFnRX.7
UFnRX.6
UFnRX.5
UFnRX.4
UFnRX.3
UFnRX.2
UFnRX.1
UFnRX.0
When the data length is specified as 7 bits (UFnCL bit = 0):
During LSB-first reception, receive data is transferred to bits 6 to 0 of the UFnRX register and the MSB always
becomes “0”.
During MSB-first reception, receive data is transferred to bits 7 to 1 of the UFnRX register and the LSB always
becomes “0”.
When an overrun error (UFnOVE = 1) has occurred, the receive data at that time will not be transferred to the
UFnRX register.
Caution “0” is written to the UFnRX8 bit of UFnRX register when writing data to the UFnRXB register.
Remark
The UFnRX.8 bit is an expansion bit when expansion bits are enabled (UFnEBE = UFnCL = 1).
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CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
(14) LIN-UARTn 8-bit receive data register (UFnRXB)
The UFnRXB register is an 8-bit register that is used to store receive data.
Receive data of a character length specified by the UFnCL bit after reception completion will be stored into the
UFnRX register when not in automatic baud rate mode (UFnMD1, UFnMD0 = 00B/10B) and when UFnEBE is “0”.
This register is read-only, in 8-bit units.
Reset input sets this register to 00H.
Figure 13-14. Format of LIN-UARTn 8-bit Receive Data Register (UFnRXB)
Address: FFF4AH (UF0RXB), FFF4EH (UF1RXB)
UFnRXB
After reset: 00H
R
7
6
5
4
3
2
1
0
UFnRX.7
UFnRX.6
UFnRX.5
UFnRX.4
UFnRX.3
UFnRX.2
UFnRX.1
UFnRX.0
(n = 0, 1)
When the data length is specified as 7 bits (UFnCL bit = 0):
During LSB-first reception, receive data is transferred to bits 6 to 0 of the UFnRX register and the MSB always
becomes “0”.
During MSB-first reception, receive data is transferred to bits 7 to 1 of the UFnRX register and the LSB always
becomes “0”.
When an overrun error (UFnOVE = 1) has occurred, the receive data at that time will not be transferred to the
UFnRX register.
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(15) LIN-UARTn ID setting register (UFnID)
The UFnID register is an 8-bit register that stored a PID that has been received when in automatic baud rate mode
(UFnMD1, UFnMD0 = 11B) and during a LIN communication. See 13.7 LIN Communication Automatic Baud
Rate Mode for details.
Also, when in normal UART mode (UFnMD1, UFnMD0 = 00B) and expansion bit data comparison is enabled
(UFnCL = UFnEBE = UFnEBC = 1), the 8 bits (UFnRX7 to UFnRX0) of the receive data and the UFnID register are
compared upon a match between the received expansion bit and the expansion bit detection level (UFnEBL). See
13.8.3 Expansion bit mode reception (with data comparison) for details.
Be sure to execute LIN communication by setting the reception enable bit (the UFnRXE bit of the UFnCTL0
register) to 0 when specifying a comparison value, and then setting the bit to 1.
This register can be read or written in 8-bit units.
Reset input sets this register to 00H.
Figure 13-15. Format of LIN-UARTn ID Setting Register (UFnID)
Address: F024EH (UF0ID), F026EH (UF1ID)
UFnID
After reset: 00H
R/W
7
6
5
4
3
2
1
0
UFnID.7
UFnID.6
UFnID.5
UFnID.4
UFnID.3
UFnID.2
UFnID.1
UFnID.0
(n = 0, 1)
Caution
Set to 00H before starting communication when in automatic baud rate mode (UFnMD1, UFnMD0
= 11B). Writing is prohibited during communication operation in automatic baud rate mode.
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(16) LIN-UARTn buffer registers 0 to 8 (UFnBUF0 to UFnBUF8)
The UFnBUF0 to UFnBUF8 registers are 8-bit buffer registers.
These registers can be used when transmitting data in normal UART mode (UFnMD1 and UFnMD0 = 00B) and
when transmitting and receiving data in automatic baud rate mode (UFnMD1 and UFnMD0 = 11B).
When in normal UART mode (UFnMD1, UFnMD0 = 00B), data will be sequentially transmitted from the UFnBUF0
register by setting the UFnTRQ bit.
When in automatic baud rate mode (UFnMD1, UFnMD0 = 11B) and during response transmission (UFnTRQ = 1),
the transmit data in UFnBUF0 will be transmitted sequentially, but the received data will not be stored.
When in automatic baud rate mode (UFnMD1, UFnMD0 = 11B) and during response reception (UFnRRQ = 1), the
received data will be stored sequentially, starting from the UFnBUF0 register.
See 13.6.1 UART buffer mode transmission and 13.7 LIN Communication Automatic Baud Rate Mode for
details.
These registers can be read or written in 8-bit units.
Reset input sets these registers to 00H.
Figure 13-16. Format of LIN-UARTn Buffer Registers 0 to 8 (UFnBUF0 to UFnBUF8)
Address: F024FH (UF0BUF0), F0250H (UF0BUF1), After reset: 00H R/W
F0251H (UF0BUF2), F0252H (UF0BUF3),
F0253H (UF0BUF4), F0254H (UF0BUF5),
F0255H (UF0BUF5), F0256H (UF0BUF7),
F0257H (UF0BUF8)
F026FH (UF1BUF0), F0270H (UF1BUF1),
F0271H (UF1BUF2), F0272H (UF1BUF3),
F0273H (UF1BUF4), F0274H (UF1BUF5),
F0275H (UF1BUF6), F0276H (UF1BUF7),
F0277H (UF1BUF8)
7
6
5
4
3
2
1
0
UFnBUFm
(n = 0, 1, m = 0 to 8)
Caution These registers cannot be used when expansion bits are enabled (UFnEBE = UFnCL = 1).
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(17) LIN-UARTn buffer control register (UFnBUCTL)
The UFnBUCTL register is a 16-bit register that controls a buffer.
This register can be read or written in 16-bit units.
See 13.6.1 UART buffer mode transmission and 13.7 LIN Communication Automatic Baud Rate Mode for
details.
Reset input sets this register to 0000H.
Figure 13-17. Format of LIN-UARTn Buffer Control Register (UFnBUCTL) (1/2)
Address: F0258H, F0259H (UF0BUCTL), F0278H, F0279H (UF1BUCTL)
After reset: 0000H
R/W
15
14
13
12
11
10
9
8
UFnBUCTL
0
0
0
0
0
0
UFnTW
UFnCON
(n = 0, 1)
7
6
5
4
3
2
1
0
UFnECS
UFnNO
UFnRRQ
UFnTRQ
UFnBUL3
UFnBUL2
UFnBUL1
UFnBUL0
UFnTW
Transmission start wait bit
0
Starts transmission immediately when buffer data transmission is requested.
1
Delays starting of transmission until completion of stop bit of reception when buffer data
transmission is requested.
The UFnTW bit is used to delay starting of transmission until completion of the stop bit of reception
when transmitting buffer data in LIN communication. It can be set only in automatic baud rate mode
(UFnMD1, UFnMD0 = 11B).
See 13.5.11 Transmission start wait function and 13.7 LIN
Communication Automatic Baud Rate Mode for details.
Cautions 1. Setting this bit is prohibited except when switching to response transmission
after header reception.
2. The UFnTW bit becomes valid at the same time as the UFnTRQ bit is set (1).
UFnCON
Successive selection bit
0
The data group to be transmitted or received next is the last data group.
1
The data group to be transmitted or received next is not the last data group.
(Data transmission or reception is continued without waiting for the next header to be
received.)
The UFnCON bit indicates that the data group to be transmitted or received next is not the last data
group when the multi-byte response transmission/reception function is used in LIN communication.
It can be set only in automatic baud rate mode (UFnMD1, UFnMD0 = 11B).
See 13.7.5 Multi-byte response transmission/reception function for details.
Cautions 1. Setting this bit is prohibited except when the multi-byte transmission/reception
function is used.
2. Set the UFnCON bit at the same time as setting UFnNO, UFnRRQ, and UFnTRQ
for 16-bit access.
UFnECS
Enhanced checksum selection bit
0
Classic checksum (used only for data byte calculation)
1
Enhanced checksum (used for calculating data byte + PID byte)
The UFnECS bit is used to select how to handle checksum when the automatic checksum function
is used in LIN communication.
It is valid only when in automatic baud rate mode (UFnMD1,
UFnMD0 = 11B) and automatic checksum is enabled (UFnACE = 1).
See 13.7.4 Automatic checksum function for details.
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Figure 13-17. Format of LIN-UARTn Buffer Control Register (UFnBUCTL) (2/2)
UFnNO
No-response request bit
0
Response for received PID is present.
1
Response for received PID is absent.
The UFnNO bit is used when a PID (PID received by a header) stored into the UFnID register is
excluded in automatic baud rate mode (UFnMD1, UFnMD0 = 11B). After setting the UFnNO bit, the
bit will be cleared automatically when the next BF-SF reception is complete. It can be set only in
automatic baud rate mode (UFnMD1, UFnMD0 = 11B).
Caution
Do not set the UFnTRQ and UFnRRQ bits while the UFnNO bit is “1”. Simultaneous
rewriting is prohibited.
UFnRRQ
Reception request bit
0
Storing has been started/no reception request
1
Reception start request/during receive operation in automatic baud rate mode
The UFnRRQ bit is used to request starting of storing data into a buffer. It is cleared when a
reception completion interrupt for the buffer is generated. It can be set only in automatic baud rate
mode (UFnMD1, UFnMD0 = 11B).
See 13.7 LIN Communication Automatic Baud Rate Mode for details.
Caution
Do not set the UFnNO and UFnTRQ bits while the UFnRRQ bit is “1”. Simultaneous
rewriting is prohibited.
UFnTRQ
Transmission request bit
0
Storing has been started/no transmission request
1
Transmission start request/during transmit operation when using buffer
The UFnTRQ bit is used to request starting of transmitting buffer data.
It is cleared when a
transmission interrupt for the data prepared in the buffer is generated. It can be set only in normal
UART mode (UFnMD1, UFnMD0 = 00B) or automatic baud rate mode (UFnMD1, UFnMD0 = 11B).
See 13.6.1 UART buffer mode transmission and 13.7 LIN Communication Automatic Baud
Rate Mode for details.
Caution
Do not set the UFnNO and UFnRRQ bits while the UFnTRQ bit is “1”. Simultaneous
rewriting is prohibited.
UFnBUL3 to UFnBUL0
0
1 to 9
10 to 15
Buffer length bits
Transmits or receives 9 bytes.
Transmits or receives number of bytes set.
Transmits or receives 9 bytes.
The UFnBUL3 to UFnBUL0 bits are used to set the number of transmit or receive data in a buffer.
The read value is the pointer of the current buffer. The bits are valid only in normal UART mode
(UFnMD1, UFnMD0 = 00B) or automatic baud rate mode (UFnMD1, UFnMD0 = 11B). When
automatic checksum function is enabled, the checksum bits (one byte) need not be included in
buffer length.
See 13.6.1 UART buffer mode transmission and 13.7 LIN Communication Automatic Baud
Rate Mode for details.
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(18) Serial communication pin select registers 0, 1 (STSEL0, STSEL1)
The STSEL0, 1 register are used to switch the input source to the serial array unit and the LIN-UARTn
communication pins.
This register can be read or written in 1-bit units or 8-bit units.
Figure 13-18. Format of STSEL0 Register
Address: FFF3C
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
STSEL0
0
SCSI100
0
SCSI010
SCSI001
SCSI000
SUARTF1
SUARTF0
Communication pin selection of UARTF0
SUARTF0
LTxD0
LRxD0
0
P71
P70
1
P15
P14
Communication pin selection of UARTF1
SUARTF1
LTxD1
LRxD1
0
P10
P11
1
P131
P132
SCSI001
SCSI000
CSI00 communication pin selection
SCK00
SI00
SO00
0
0
P10
P11
P12
0
1
P04
P03
P02
1
0
P34
P33
P32
Other than the above
SCSI010
Setting prohibited (same as “00” setting)
CSI01 communication pin selection
SCK01
SI01
SO01
0
P74
P75
P13
1
P56
P55
P54
SCSI100
CSI10 communication pin selection
SCK10
SI10
SO10
0
P133
P132
P131
1
P51
P52
P53
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Figure 13-19. Format of STSEL1 Register
Address: FFF3D
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
STSEL1
SIIC1
SIIC0
0
0
SCAN1
SCAN0
TMCAN1
TMCAN0
TMCAN0
Input source switch of TAU unit1 CH4
0
Input from TI14 (after selected by TIS141~0 bits)
1
TSOUT of aFCAN0 (CAN0 time stamp function)
TMCAN1
Input source switch of TAU unit1 CH5
0
Input from TI15 (after selected by TIS151~0 bits)
1
TSOUT of aFCAN1 (CAN1 time stamp function)
SCAN0
Communication pin selection of aFCAN0
CTxD0
CRxD0
0
P71
P70
1
P00
P01
SCAN1
Communication pin selection of aFCAN1
CTxD1
CRxD1
0
P62
P63
1
P134
P135
SIIC1
SIIC0
Communication pin selection of IIC11
SCL11
SDA11
0
0
P60
P61
0
1
P30
P31
1
0
P136
P50
Other than the above
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(19) Port mode registers 1, 7, 13 (PM1, PM7, PM13)
The PM1, PM7 and PM13 registers are used to set ports 1, 7, and 13 to input or output in 1-bit units.
The PM1, PM7 and PM13 registers can be set by using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH (PM13 is set to FEH).
Caution
The shaded pins are provided at two ports.
Select either port by using the corresponding
register.
Remarks 1.
The pins mounted depend on the product. See 1.3 Ordering Information and 2.1 Pin Function
List.
2.
See CHAPTER 4 PORT FUNCTIONS for port settings.
Figure 13-20. Format of Port Mode Registers 1, 7, 13 (PM1, PM7, PM13)
Address: FFF21H After reset: FFH R/W
Symbol
7
6
5
4
3
2
1
0
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
Address: FFF27H After reset: FFH R/W
Symbol
7
6
5
4
3
2
1
0
PM7
PM77
PM76
PM75
PM74
PM73
PM72
PM71
PM70
Address: FFF2DH After reset: FEH R/W
Symbol
7
6
5
4
3
2
1
0
PM13
1
PM136
PM135
PM134
PM133
PM132
PM131
0
PMmn
PMmn pin I/O mode selection (m = 1, 7; n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
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13.4 Interrupt Request Signals
The following three interrupt request signals are generated from LIN-UARTn.
LIN-UARTn reception status interrupt (INTLSn)
LIN-UARTn reception interrupt (INTLRn)
LIN-UARTn transmission interrupt (INTLTn)
Table 13-2 shows the default priority order of these three interrupt request signals.
Table 13-2. Interrupts and Their Default Priorities
Interrupt
Status
Default Priority
Low
Reception complete
Transmission start/complete
High
(1) LIN-UARTn reception status interrupt (INTLSn)
LIN-UARTn reception status interrupt is generated when an error condition is detected during a reception. A
UFnSTR register flag (UFnPE, UFnFE, UFnOVE, UFnDCE, UFnBSF, UFnIPE, UFnCSE, UFnRPE, UFnIDM,
UFnEBD) corresponding to the detected status is set.
See 13.5.10 LIN-UART reception status interrupt generation sources for details.
(2) LIN-UARTn reception interrupt (INTLRn)
LIN-UARTn reception interrupt is generated when data is shifted into the receive shift register and transferred to
the UFnRX register in the reception enabled status.
When a reception error occurs, LIN-UARTn reception interrupt is not generated, but LIN-UARTn reception status
interrupt is generated.
LIN-UARTn reception interrupt is not generated in the reception disabled status.
If expansion bit operation is enabled (UFnCL = UFnEBE = 1) and expansion bit data comparison is disabled
(UFnEBC = 0), LIN-UART reception interrupt is generated when the level of the inverted value set by using the
expansion bit detection level select bit (UFnEBL) is detected as an expansion bit.
When there is no error when in automatic baud rate mode (UFnMD1, UFnMD0 = 11B) and PID reception has
been completed (stop bit position), LIN-UART reception itnerrupt is generated.
When response reception has ended without an error when in automatic baud rate mode (UFnMD1, UFnMD0 =
11B), a reception complete interrupt request signal is generated.
(3) LIN-UARTn transmission interrupt (INTLTn)
When a transmission interrupt request is set to output upon starting a transmission (UFnITS = 0), a transmission
interrupt request signal is generated when transmission from the UFnTX register to the transmit shift register has
been completed.
When a transmission interrupt request is set to output upon completion of a transmission (UFnITS = 1), a
transmission interrupt request signal is generated when transmitting a stop bit has been completed.
When in automatic baud rate mode (UFnMD1, UFnMD0 = 11B), a transmission complete interrupt request signal
is generated at the start of transmission of the last byte of a response.
Remark n = 0, 1
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13.5 Operation
13.5.1 Data format
Full-duplex serial data reception and transmission is performed.
As shown in Figure 13-21, one data frame of transmit/receive data consists of a start bit, character bits, an expansion
bit, a parity bit, and stop bits.
Specification of the character bit length within 1 data frame, parity selection, specification of the stop bit length, and
specification of MSB/LSB-first transfer are performed using the UFnCTL0 register.
Moreover, the UFnTDL bit and UFnRDL bit of the UFnOPT0 register are used to control UART output/inverted output
for the LTxDn pin and UART input/inverted input for the LRxDn pin, respectively.
Remark n = 0, 1
Start bit ........................................................ 1 bit
Character bits.............................................. 7 bits/8 bits
Expansion bit .............................................. 1 bit
Parity bit ...................................................... Even parity/odd parity/0 parity/no parity
Stop bit ........................................................ 1 bit/2 bits
Transmission/reception level setting ........... Forward/inversion
Transmission/reception direction setting ..... Forward/inversion
Figure 13-21. Format of LIN-UART Transmit/Receive Data (1/2)
(a) 8-bit data length, LSB first, even parity, 1 stop bit, transfer data: 55H
1 data frame
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity Stop
bit
bit
(b) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H
1 data frame
Start
bit
D7
D6
D5
D4
D3
D2
D1
D0
Parity Stop
bit
bit
(c) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H, LTxDn inversion
1 data frame
Start
bit
D7
D6
D5
D4
D3
D2
D1
D0
Parity Stop
bit
bit
(d) 7-bit data length, LSB first, odd parity, 2 stop bits, transfer data: 36H
1 data frame
Start
bit
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D1
D2
D3
D4
D5
D6
Parity Stop
bit
bit
Stop
bit
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Figure 13-21. Format of LIN-UART Transmit/Receive Data (2/2)
(e) 7-bit data length, MSB first, odd parity, 2 stop bits, transfer data: 36H
1 data frame
Start
bit
(f)
D7
D6
D5
D4
D3
D2
D1
Parity Stop Stop
bit
bit
bit
8-bit data length, LSB first, no parity, 1 stop bit, transfer data: 87H
1 data frame
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop
bit
(g) 8-bit data length, LSB first, even parity, expansion bit: enabled, 1 stop bit, transfer data: 155H
1 data frame
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Expansion Parity Stop
bit
bit
bit
(h) 8-bit data length, MSB first, even parity, expansion bit: enabled, 1 stop bit, transfer data: 155H
1 data frame
Start Expansion
D7
bit
bit
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D4
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D1
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Parity Stop
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13.5.2 Data transmission
Figure 13-22 shows the procedure for transmitting data.
Figure 13-22. Transmission Processing Flow
START
Baud rate setting
(UFnCTL1 register)
Transmit data level setting
(UFnOPT0 register)
Various mode settings
(UFnOPT1 register)
INTLT timing setting
(UFnOPT2 register)
Various mode settings,
enabling transmission
(UFnCTL0 register)
Write UFnTX register
No
INTLT signal generated?
Yes
No
All transmit data written?
Yes
END
Cautions 1. When initializing (UFnTXE = 0) the transmission unit, be sure to confirm that the transmission
status flag has been reset (UFnTSF = 0). When initialization is performed while UFnTSF is “1”,
transmission is aborted midway.
2. During LIN communication, confirm that a status interrupt request signal (INTLSn) has been
generated, because reception is performed simultaneously with transmission.
3. When data consistency error detection has been set (UFnDCS = 1) and a data consistency error
has been detected during LIN communication, transmission of the next data frame or BF is
stopped at the same as when a status interrupt request signal (INTLSn) is generated and a data
consistency error flag is set (UFnDCE = 1).
Remarks1. See (2) of 13.11 Cautions on Use for details of starting LIN-UART.
2. n = 0,1
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A transmission operation is started by writing transmit data to the transmit data register (UFnTX).
The data stored into the UFnTX register is transferred to the transmit shift register and a start bit, an expansion bit, a
parity bit, and stop bits are added to the data, and the data are sequentially output from the LTxDn pin.
If a transmission interrupt is set upon starting a transmission (UFnITS = 0), a transmission interrupt request signal
(INTLTn) is generated when transferring the data stored into the UFnTX register to the transmit shift register has been
completed.
If a transmission interrupt is set upon completion of a transmission (UFnITS = 1), a transmission interrupt request signal
(INTLTn) is generated when transmitting a stop bit has been completed.
Figure 13-23. Data Transmission Timing Chart
fCLK
LTxDn pin
START
DT0
Transmission processing
start
STOP1
Transmission processing
end
Prescaler clock
Transmission baud rate
clock
Transmission baud rate
period
Transmission baud rate
period
Transmission baud rate
period
INTLT (UFnITS = 0)
INTLT (UFnITS = 1)
Set by writing UFnTX register
Cleared when next transmit
data does not exist
UFnTSF flag
Caution If the stop bit length is set to 2 bits (UFnSL = 1), the transmit completion interrupt (INTLTn) will be
output after the second stop bit has been transmitted, at which point the transmission status flag
(UFnTSF) will be cleared.
Remark n = 0, 1
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When generation of a transmission interrupt is set upon starting a transmission (UFnITS = 0), successive transmission
can be performed by writing the next data to UFnTX during the transmission after INTLTn has been generated.
Figure 13-24. Diagram of Timing When Starting Successive Transmission (UFnITS = 0)
Start
LTxDn pin
UFnTX register
Data (1)
Parity
Data (1)
Transmit
shift register
Stop
Start
Data (2)
Parity
Data (2)
Stop
Start
Data (3)
Data (2)
Data (1)
INTLT
UFnTSF flag
Figure 13-25. Diagram of Timing When Ending Successive Transmission (UFnITS = 0)
LTxDn pin
Parity
UFnTX register
Transmit
shift register
Stop
Start
Data (n – 1)
Parity
Stop
Start
Data (n)
Parity Stop
Data (n)
Data (n – 1)
Data (n – 1)
Data (n)
FFH
INTLT
UFnTSF flag
UFnTXE bit
Remark n = 0, 1
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13.5.3 Data reception
Figure 13-26 shows the procedure for receiving data.
Figure 13-26. Reception Processing Flow
START
Baud rate setting
(UFnCTL1 register)
Receive data level setting
(UFnOPT0 register)
Various mode settings
(UFnOPT1 register)
Noise filter setting
(UFnOPT2 register)
Various mode settings,
enabling reception
(UFnCTL0 register)
No
INTLS signal generated?
No
Yes
INTLR signal generated?
Read UFnRX register
Yes
Read UFnSTR register
Read UFnRX register
Clear status flag
(UFnSTC register)
Processing corresponding
to status
Cautions 1. When initializing (UFnRXE = 0) the reception unit, be sure to confirm that the reception status flag
has been reset (UFnRSF = 0). When initialization is performed while UFnRSF is “1”, reception is
aborted midway.
2. Be sure to read the receive data register (UFnRX) when a reception error has occurred.
If the UFnRX register is not read, an overrun error occurs upon completion of receiving the next
data.
Remarks1.
2.
See (2) of 13.11 Cautions on Use for details of starting LIN-UART.
n = 0, 1
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When the LRxDn pin is sampled by using the operating clock and a falling edge is detected, data sampling of the
LRxDn pin is started and is recognized as a start bit if it is at low level at a timing of half the reception baud rate clock
period after the falling edge has been detected. When the start bit has been recognized, a reception operation is started
and serial data is sequentially stored into the receive shift register according to the baud rate set. When a stop bit has
been received, the data stored into the receive shift register is transferred to the receive data register (UFnRX) at the
same time a reception complete interrupt request signal (INTLRn) is generated.
When an overrun error has occurred (UFnOVE = 1), however, the receive data is not transferred to the UFnRX register
but discarded. When any other error has occurred, the reception is continued up to the reception position of the stop bit
and the receive data is transferred to the UFnRX register.
After the occurrence of any reception error, INTLSn is generated after completion of the reception and INTLRn is not
generated.
Figure 13-27. Data Reception Timing Chart
fCLK
START
LRxDn pin
DT0
DTn
STOP1
Reception processing start
Reception processing
end
Sampling point
Prescaler clock
Reception baud rate clock
Note
Reception baud rate
clock period
Reception baud rate
clock period
INTLR (error-free)
INTLS (error)
UFnRX register
New data
UFnRSF flag
Cleared upon detection of first stop bit
Note One-half the reception baud rate clock period
Cautions 1. The start bit is not recognized when a high level is detected at a timing of half the reception baud
rate clock period after the falling edge of the LRxDn pin was detected.
2. A reception always operates with the number of stop bits as 1.
At that time, the second stop bit is ignored.
3. When a low level is constantly input to the LRxDn pin before an operation to enable reception is
performed, the receive data is not identified as a start bit.
4. For successive reception, the next start bit can be detected immediately after a stop bit of the
first receive data has been detected (upon generation of a reception complete interrupt).
5. Be sure to enable reception (UFnRXE = 1) after having changed the UFnRDL bit. If the UFnRDL
bit is changed after having enabled reception, the start bit may be detected falsely.
Remark n = 0, 1
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13.5.4 BF transmission/reception format
The RL78/D1A has a BF (Break Field) transmission/reception control function to enable use of the LIN (Local
Interconnect Network) function.
Figure 13-28. LIN Transmission Manipulation Outline
Wake-up
signal
frame
Break
field
Sync
field
Protected
identifier
field
DATA
field
DATA
field
Check
SUM
field
Note 2
13 bits
55H
transmission
Data
transmission
Data
transmission
Data
transmission
Data
transmission
LIN-bus
Note 3
8 bits
Note 1
LTxDn (output)
Note 4
BF transmission
INTLT
interrupt
(UFnITS = 0)
Notes 1. The interval between each field is controlled by software.
2. BF output is performed by hardware. The output width is the bit length set by the UFnBLS2 to UFnBLS0
bits of the UFnOPT0 register. If even finer output width adjustments are required, such adjustments can be
performed using the UFnBRS11 to UFnBRS0 bits of the UFnCTL1 register.
3. 80H transfer in the 8-bit mode or BF transmission is substituted for the wakeup signal.
4. The LIN-UART transmission interrupt (INTLTn) is output at the start of each transmission. The INTLTn
signal is also output at the start of each BF transmission. Be sure to clear UFnOPT2.UFnITS to “0” when
starting a transmission, so that the LIN-UART transmission interrupt is always generated.
Remarks1.
Figure 13-28 shows the LIN transmission manipulation outline when in BF reception enable mode during
communication (UFnMD1, UFnMD0 = 10B). See 13.7 LIN Communication Automatic Baud Rate
Mode for when in automatic baud rate mode (UFnMD1, UFnMD0 = 11B).
2.
n =0, 1
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Figure 13-29. LIN Reception Manipulation Outline
Wake-up
signal
frame
Break
field
Sync
field
Protected
identifier
field
Note 2
13 bits
SF reception
PID reception
DATA
field
DATA
field
Check
SUM
field
Data
reception
Data
reception
Note 5
Data
reception
LIN-bus
LRxDn (input)
Disable
BF
reception
Enable
Note 3
Status interrupt
(INTLS)
Note 1
Edge detection
(INTP1)
Note 4
Capture timer
Notes
Disable
Enable
1. A wakeup signal is detected by detecting the interrupt edge of a pin (INTP1). After having received the
wakeup signal, enable LIN-UARTn, enable reception operation, and set the BF reception trigger bit if
needed.
2. If a BF reception of at least 11 bits is detected, the BF reception is judged to be ended normally.
3. When BF reception has ended normally in normal UART mode (UFnMD1, UFnMD0 = 00B), a reception
complete interrupt request signal (INTLR) is generated. When BF reception has ended normally in BF
reception enable mode during communication (UFnMD1, UFnMD0 = 10B), a status interrupt request
signal (INTLSn) is generated, and a successful BF reception flag (UFnBSF) is set. When the BF
reception flag (UFnBRF) is “1”, detection of overrun, parity, and framing errors (UFnOVE, UFnPE,
UFnFE) is not performed during BF reception. Moreover, data transfer from the receive shift register to
the receive data register (UFnRX) is also not performed. At this time, UFnRX retains the previous value.
4. Connect the LRxDn pin to the TI (capture input) of the timer array unit. Enable the timer by using a BF
reception complete interrupt, measure the baud rate from the SF transfer data, and calculate the baud
rate error. Set a reception state by stopping the LIN-UARTn reception operation after SF reception and
re-setting the value of LIN-UARTn control register 1 (UFnCTL1) obtained by correcting the baud rate
error.
5. Classification of a checksum field is performed by using software. The processing that initializes LINUARTn after CSF reception and sets to a successful BF reception wait state (UFnBRF = 1) again is also
performed by using software. In BF reception enable mode during communication (UFnMD1, UFnMD0 =
10B), however, BF reception can be automatically performed without setting to a successful BF reception
wait state (UFnBRF = 1) again.
(Caution and Remark are given on the next page.)
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Caution
With the sync field, the transfer baud rate is calculated using the capture function of the TAU. At
this point, stop reception operation to stop generation of a reception interrupt in the LIN-UARTn.
Remarks1. See 13.7 LIN Communication Automatic Baud Rate Mode for when in automatic baud rate mode
(UFnMD1, UFnMD0 = 11B).
2.
n = 0, 1
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Figure 13-30 shows the port configurations for LIN reception manipulation.
Wakeup signals transmitted from the LIN master are received via INTP1 edge detection. The baud rate error can be
calculated by measuring the length of a sync field transmitted from the LIN master via an external event capture operation
of the timer array unit (TAU).
(1) LIN-UART0
Figure 13-30. Port Configuration of LIN Reception Manipulation
Selector
Selector
P70/TI03/
LRxD0/INTPLR0
LRxD0 input
Port Mode
PM70
INTPLR0 input
Selector
P14/TI14/
LRxD0/INTPLR0
Port Mode
PM14
SUARTF0
SUARTF0
0: Selects P70
1: Selects P14
Selector
TI03 input
Selector
P03/TI03
P81/TI03
P95/TI03
Port Mode
PM03
PM81
PM95
00: Selects P03
01: Selects P81
10: Selects P95
11: Selects P70
Selector
Selector
Selector
TI14 input
P04/TI14
P54/TI14
Port Mode
PM04
PM54
Remarks 1.
00: Selects P14 TSOUT
01: Selects P04
10: Selects P54
TMCAN0
0: Selects P14 or P04 or P54
1: Selects TSOUT of CAN controller 0
Figure 13-30 shows the port configuration when in BF reception enable mode during communication
(UFnMD1, UFnMD0 = 10B).
2.
TMCAN0: Bit 0 of the serial communication pin select register 1 (STSEL1) (see Figure 13-19)
A summary of the peripheral functions to be used in LIN communication operation is given below.
LIN-UART0 reception pin interrupt (INTPLR0); Wakeup signal detection
Purpose: Detecting wakeup signal edges and detecting the start of communication
Channel 4 (TI14) of the timer array unit 1 (TAU1); Baud rate error detection
Purpose: Detecting the length of a sync field (SF) and detecting the baud rate error by dividing the sync field length
by the number of bits (measuring the intervals of TI14 input edges in capture mode)
Asynchronous serial interface LIN-UART0
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(2) LIN-UART1
Figure 13-31. Port Configuration of LIN Reception Manipulation
Selector
Selector
P11/TI11/
LRxD1/INTPLR1
LRxD1 input
Port Mode
PM11
INTPLR1 input
Selector
P132/TI20/
LRxD1/INTPLR1
Port Mode
PM132
SUARTF1
SUARTF1
0: Selects P11
1: Selects P132
Selector
TI11 input
Selector
P84/TI11
P140/TI11
P64/TI11
Port Mode
PM84
PM140
PM64
00: Selects P11
01: Selects P84
10: Selects P140
11: Selects P64
Selector
Selector
TI20 input
P60/TI20
P30/TI20
Port Mode
PM60
PM30
00: Selects P60
01: Selects P32
10: Selects P132
A summary of the peripheral functions to be used in LIN communication operation is given below.
LIN-UART1 reception pin interrupt (INTPLR1); Wakeup signal detection
Purpose: Detecting wakeup signal edges and detecting the start of communication
Asynchronous serial interface LIN-UART1
Remarks 1.
Figure 13-31 shows the port configuration when in BF reception enable mode during communication
(UFnMD1, UFnMD0 = 10B).
2.
The above is the port configuration of LIN reception manipulation for R5F10DPJXFB.
The port configuration of LIN reception manipulation differs in depending on the product.
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13.5.5 BF transmission
Figure 13-32 describes the processing of BF transmission in LIN communication.
Figure 13-32. BF Transmission Processing Flow
START
Baud rate setting
(UFnCTL1 register)
Transmit data level,
BF length settings
(UFnOPT0 register)
Various mode settings
(UFnOPT1)
Noise filter,
INTLT timing settings
(UFnOPT2)
Various mode settings,
enabling transmission
(UFnCTL0)
Set UFnBTT bit Note
(UFnOPT0)
No
INTLT signal generated?
Yes
END
Note
In normal UART mode (UFnMD1, UFnMD0 = 00B), set the UFnBRT bit at the same time as setting the
UFnBTT bit.
Caution Set the following values when performing BF transmission.
The transmit data level is normal output (UFnTDL = 0).
Communication direction control is LSB first (UFnDIR = 1).
The parity selection bit is no parity bit output (UFnPS1, UFnPS0 = 00B).
The data character length is 8 bits (UFnCL = 1).
The LIN-UART transmission interrupt is generated when starting transmission (UFnITS = 0).
Remarks 1.
2.
See (2) of 13.11 Cautions on Use for details of starting LIN-UART.
n = 0, 1
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A BF transmission operation is started when a BF transmission trigger (UFnBTT) is set. 13 to 20 bits of low level (the
length specified by the BF length selection bits (UFnBLS2 to UFnBLS0)) is output to the LTxDn pin.
LIN-UARTn
transmission interrupt (INTLTn) is generated when the BF transmission is started. After the BF transmission ends, the BF
transmission state is automatically released and operation is returned to normal UART transmission mode.
The transmission operation stays in a wait state until the data to be transmitted is written to the UFnTX register or a BF
transmission trigger (UFnBTT) is set. Start the next transmission operation after having confirmed that the BF has been
received normally according to the LIN-UARTn reception interrupt (INTLRn) during the BF transmission or the LIN-UARTn
reception status interrupt (INTLSn).
Figure 13-33. BF Transmission Timing Example
fCLK
LTxDn pin
First bit
Second bit
Transmission processing
start
STOP1
Transmission processing
end
Prescaler clock
Transmission baud rate clock
Transmission baud rate period Transmission baud rate period
Transmission baud rate period
INTLT (UFnITS = 0)
Reset by writing 1 to UFnBTT
Cleared when next transmit data
does not exist
UFnTSF flag
Caution When the stop bit length is set to 2 bits (UFnSL = 1), the transmission status flag (UFnTSF) is cleared
when transmission of the second stop bit has been completed.
Remark n = 0, 1
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13.5.6 BF reception
Figure 13-34 describes the processing of BF reception in LIN communication.
Figure 13-34. BF Reception Processing Flow
START
Baud rate setting
(UFnCTL1 register)
Receive data level setting
(UFnOPT0 register)
Various mode settings
(UFnOPT1)
Noise filter,
INTLT timing settings
(UFnOPT2)
Various mode settings,
enabling reception (UFnCTL0)
No
INTLS signal generated?
Yes
END
Caution
Set the following values when performing BF transmission.
The input logic level is normal input (UFnRDL = 0).
Communication direction control is LSB first (UFnDIR = 1).
The parity selection bit is no parity bit output (UFnPS1, UFnPS0 = 00B).
The data character length is 8 bits (UFnCL = 1).
Transmission interrupt is generated when starting transmission (UFnITS = 0).
BF reception enable mode during communication (UFnMD1, UFnMD0 = 10B) as the mode.
Remarks 1. Figure 13-34 shows the reception processing flow of LIN communication in BF reception enable mode
during communication (UFnMD1, UFnMD0 = 10B).
See 13.7 LIN Communication Automatic Baud Rate Mode for when in automatic baud rate mode
(UFnMD1, UFnMD0 = 11B).
2. See (2) of 13.11 Cautions on Use for details of starting LIN-UART.
3. n = 0, 1
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When the BF reception trigger bit (UFnBRT) is set, a successful BF reception wait state (UFnBRF = 1) is entered, the
LRxDn input level is monitored, and start bit detection is performed.
When the falling edge of the LRxDn input is detected, the BF length is measured by counting up the internal counter
until a rising edge is detected. If the BF length is 11 bits or more when a rising edge is detected, BF reception is judged as
being normal, and BF reception ends. When ending BF reception, a successful BF reception flag (UFnBSF) is set at the
same time as generation of the LIN-UARTn reception status interrupt (INTLSn).
In automatic baud rate mode, detection of overrun, parity, and framing errors (UFnOVE, UFnPE, UFnFE) is limited.
Moreover, data transfer from the receive shift register to the receive data register (UFnRX) is not performed. BF reception
is judged as being abnormal if the BF width is less than 11 bits. In that case, the error status flag (UFnSTR) is set at the
same time as generation of the status interrupt request signal (INTLSn).
When performing a transmission for which a data consistency check is enabled (UFnDCS = 1), a data consistency error
flag (UFnDCE) is set and LIN-UARTn reception status interrupt (INTLSn) is output when a mismatch between the transmit
data and receive data is detected, regardless of whether BF reception is performed successfully or fails. At that time,
INTLRn is not output.
When in BF reception enable mode during communication (UFnMD1, UFnMD0 = 10B), LIN-UART can detect a new BF
reception even during data communication or in automatic baud rate mode. See 13.5.9 (2) BF reception enable mode
during communication (UFnMD1, UFnMD0 = 10B) for details.
Remark n = 0, 1
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Figure 13-35. BF Reception Timing Example
- Normal BF reception: A high level is detected after the BF length has exceeded 11 bits.
1
2
3
4
5
6
7
8
9
10
11
9
10
11
11 bits
Set the UFnBRT bit.
UFnBRF flag
INTLR signal
“0”
UFnBSF flag
“0”
INTLS signal
“0”
UFnBSF flag
“0”
- BF reception error: A high level is detected when the BF length is less than 11 bits.
1
2
3
4
5
Set the UFnBRT bit.
6
7
8
11 bits
UFnBRF flag
INTLR signal
“0”
UFnBSF flag
“0”
INTLS signal
“0”
UFnBSF flag
“0”
Caution The UFnBRF bit is reset by setting the UFnBRT bit to “1” and cleared upon normal BF reception.
In BF reception enable mode during communication (UFnMD1, UFnMD0 = 10B), the bit is reset or
cleared in the same way as described above.
Remark n = 0, 1
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13.5.7 Parity types and operations
Caution When using the LIN communication, fix the UFnPS1 and UFnPS0 bits of the UFnCTL0 register to 00
(n = 0, 1).
The parity bit is used to detect bit errors in the communication data. Normally the same parity bit is used on the
transmission side and the reception side.
In the case of even parity and odd parity, it is possible to detect 1-bit (odd-count) errors. In the case of 0 parity and no
parity, errors cannot be detected.
(1) Even parity
(a) During transmission
The number of bits whose value is “1” among the transmit data, including the parity bit, is controlled so as to be
an even number. The parity bit values are as follows.
Odd number of bits whose value is “1” among transmit data: 1
Even number of bits whose value is “1” among transmit data: 0
(b) During reception
The number of bits whose value is “1” among the reception data, including the parity bit, is counted, and if it is
an odd number, a parity error is output.
(2) Odd parity
(a) During transmission
Opposite to even parity, the number of bits whose value is “1” among the transmit data, including the parity bit,
is controlled so that it is an odd number. The parity bit values are as follows.
Odd number of bits whose value is “1” among transmit data: 0
Even number of bits whose value is “1” among transmit data:
1
(b) During reception
The number of bits whose value is “1” among the receive data, including the parity bit, is counted, and if it is an
even number, a parity error is output.
(3) 0 parity
During transmission, the parity bit is always made 0, regardless of the transmit data.
During reception, parity bit check is not performed. Therefore, no parity error occurs, regardless of whether the
parity bit is 0 or 1.
(4) No parity
No parity bit is added to the transmit data.
Reception is performed assuming that there is no parity bit. No parity error occurs since there is no parity bit.
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Figure 13-36. Parity Error Occurrence Timing
Start
bit
LRxDn input
D0
D1
D4
D5
D6
D7
Parity
bit
Stop
bit
Data sampling
UFnPE flag
INTLS
13.5.8 Data consistency check
When the data consistency check selection bit (UFnDCS) is set to “1”, transmit data and receive data are compared
during transmission operation, even if the reception enable bit is disabled (UFnRXE = 0).
When reception is enabled (UFnRXE = 1), it is also checked that reception processing is not ended early during
transmission processing.
When either a mismatch between transmission and reception signals or an early end of reception processing is
detected during transmission processing, operation is judged as being abnormal, a status interrupt request signal
(INTLSn) is output, and a data consistency error flag (UFnDCE) is set. Even if the next transmit data has already been
written to the transmit data register (UFnTX), the next transmission is not performed. (The written data within UFnTX is
ignored.) When the BF transmission trigger bit (UFnBTT) has been set, a BF is not transmitted.
To restart transmission, transmit data must be written to the transmit data register (UFnTX) or the BF transmission
trigger bit (UFnBTT) must be set, after the end of transmission has been confirmed (UFnTSF = 0) and the data
consistency error flag (UFnDCE) has been cleared or the UFnEN bit of the PERX register has been cleared and then set.
When a buffer is used, communication is stopped even if data not transferred remains in the buffer.
When reception is disabled (UFnRXE = 0), storing receive data and thereby generating LIN-UARTn reception interrupt
(INTLRn) as well as setting UFnBSF, UFnFE, and UFnOVE and thereby generating LIN-UARTn reception status interrupt
(INTLSn) are not performed since the reception operation itself is not performed. Consequently, receive data is not
required to be read.
Caution
A store operation of receive data is not affected by whether a data consistency error exists. Storing
is performed even if a consistency error occurs.
Remark n = 0, 1
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(1) Mismatch between transmission and reception signals
Serial transmission and reception signals are compared during data (or BF) transmission, a detected mismatch is
judged as being abnormal, and the UFnDCE bit is set (1) at the same time a status interrupt (INTLSn) is generated.
During data transmission, the comparison is performed from the start bit to the first stop bit.
During BF transmission, the comparison is performed from the first bit of the BF to the first stop bit.
A consistency check is not performed for the second stop bit, even if the stop bit length is specified as two bits by
using the stop bit length select bit (UFnSL).
Figure 13-37. Data Consistency Error Occurrence Timing Example 1 (UFnBRF = 0)
Next transmission is not performed.
LTxDn output
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop
bit
LRxDn input
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop
bit
Data sampling
UFnTSF flag
Mismatch detection
Error judgment (internal signal)
UFnDCE flag
INTLS
Remark n = 0, 1
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Figure 13-38. Data Consistency Error Occurrence Timing Example 2 (UFnBRF = 0)
Next transmission is not performed.
LTxDn output
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop
bit
LRxDn input
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop
bit
Data sampling
Mismatch
detection
UFnTSF flag
Error judgment
(internal signal)
UFnDCE flag
INTLS
INTLR
Remark n = 0, 1
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(2) Early end of reception processing
When transmission is performed while reception is enabled (UFnTXE = UFnRXE = 1), a stop bit position detected
in the reception processing, even though during transmission is judged as being abnormal and the UFnDCE bit is
set (1) at the same time a status interrupt (INTLSn) is generated.
Figure 13-39. Timing Example of Consistency Error Occurrence due to Early End of Reception Processing
Next transmission is not performed.
LTxDn output (D5H)
LRxDn input (AAH)
Start
bit
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Stop
bit
Stop
bit
Data sampling
UFnTSF flag
Reception end
Error judgment (internal signal)
UFnDCE flag
INTLS
Remark n = 0, 1
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13.5.9 BF reception mode select function
A mode for BF (break field) reception, which can be selected by using the LIN-UART operation mode selection bits
(UFnMD1, UFnMD0), is provided.
(1) Normal UART mode (UFnMD1 and UFnMD0 = 00B)
In normal UART mode (UFnMD1 and UFnMD0 = 00B), a new BF is only recognized when the system is waiting for
a BF to be successfully received (UFnBRF = 1). When BF reception has been successfully completed, a reception
complete interrupt (INTLRn) is generated.
If the system is not waiting for a BF to be successfully received (UFnBRF = 0), framing or overrun errors are
detected at the data’s stop bit position (bit 10) (see Figure 13-40). If an overrun error has not occurred, the
received data is stored in the UFnRX register. If the system is waiting for a BF to be successfully received
(UFnBRF = 1), framing or overrun errors are not detected and the received data is not stored in the UFnRX register.
If UFnBRF = 0 and reception is stopped when data or the BF stop bit is transmitted, the data consistency error
interrupt is issued and the flag is changed when transmission of the bit following the stop bit starts (see 13.5.8 (2)).
If reception is in progress when the stop bit is transmitted, the data consistency error interrupt is issued and the
flag is changed when transmission of the stop bit starts (see 13.5.8 (1)). On the other hand, if UFnBRF = 1 and
reception is stopped when the stop bit is transmitted, the data consistency error interrupt is issued and the flag is
changed when transmission of the bit following the stop bit starts (see Figure 13-41) and if reception is in progress
when the stop bit is transmitted, the data consistency error interrupt is issued and the flag is changed when the
rising edge of the input data following the stop bit is detected (see Figure 13-42).
Caution The successful BF reception flag (UFnBSF) is not set in normal UART mode.
Figure 13-40. Timing of Judging Framing or Overrun Error in Normal UART Mode
LRxDn input
Start
bit
D0
D1
D4
D5
D6
D7
Stop
bit
Data sampling
UFnFE flag,
UFnOVE flag
INTLS
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Figure 13-41. Timing of Occurrence of Data Consistency Error When BF Is Transmitted When UFnBRF = 1 (When
Reception Is in Progress After Transmission of Stop Bit Has Stopped (Previous Input Data = 1))
LTxDn output
Edge detection
LRxDn input
UFnBRF
“1“
BF
length
Stop
bit
BF
length
Stop
bit
Next transmission
is not performed.
Reception operation
is stopped
UFnTSF
Error judgment
(internal signal)
UFnDCE
INTLS
Figure 13-42. Timing of Occurrence of Data Consistency Error When BF Is Transmitted When UFnBRF = 1 (When
Reception Is in Progress After Transmission of Stop Bit Has Started (Previous Input Data = 0))
LTxDn output
Edge detection
LRxDn input
UFnBRF
“1“
BF
length
Stop
bit
BF
length
Stop
bit
During reception
operation
Next transmission
is not performed.
Edge
detection
UFnTSF
Error judgment
(internal signal)
UFnDCE
INTLS
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(2) BF reception enable mode during communication (UFnMD1, UFnMD0 = 10B)
If BF reception enable mode during communication (UFnMD1, UFnMD0 = 10B) is set, a mode that recognizes a
new BF is entered during data communication in addition to when waiting for successful BF reception (UFnBRF =
1). When not waiting for successful BF reception (UFnBRF = 0) and when a low level has been detected at the
data stop bit position (10th bit), judging a framing error or an overrun error is being waited for until input data
becomes high level, because a new BF may be undergoing reception. If the successive-low-level period is less
than 11 bits, it is judged as error detection (see Figure 13-43). If not an overrun error, the first eight bits of receive
data are stored into the UFnRX register. At this time, a successful BF reception flag (UFnBSF) is not set. When
waiting for successful BF reception (UFnBRF = 1), detecting framing or overrun errors and storing receive data into
the UFnRX register are not performed.
On the other hand, if the successive-low-level period is at least 11 bits, receiving of the new BF is judged
successful and a successful BF reception flag (UFnBSF) is set (see Figure 13-44). Detection of framing or
overrun errors is not performed. At this time, receive data is not stored into the UFnRX register.
If a reception operation is stopped when starting to transmit the stop bit of data or a BF while UFnBRF is “0”, the
data consistency error interrupt and flag are changed when the bit following the stop bit is started (see 13.5.8 (2)).
If a reception operation is being performed when starting to transmit the stop bit, it is performed when input data “1”
is detected at a position following the stop bit (see 13.5.8 (1) and Figure 13-45).
On the other hand, if input data “1” is detected during BF transmission with UFnBRF set to “1”, it is performed after
transmission of the first stop bit has been completed (see Figure 13-46).
After BF transmission has been
completed, it is performed at a bit for which “1” is detected (see Figure 13-47).
Caution To set to BF reception enable mode during communication (UFnMD1, UFnMD0 = 10B), be sure to
set the UFnDCS bit of the UFnOPT1 register also to “1”.
Figure 13-43. Framing Error/Overrun Error Judgment Timing upon BF Reception Failure (When UFnBRF = 0)
Start
bit
LRxDn input
D0
D5
D6
D7
Stop
bit
Data sampling
When low-level period is less than 11 bits
UFnFE flag/
UFnOVE flag
UFnBSF flag
“0“
INTLS
Remark n = 0, 1
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Figure 13-44. Status Interrupt Occurrence Timing upon Successful BF Reception (When UFnBRF = 0)
Start
bit
LRxDn input
D0
D5
D6
Stop
bit
D7
Data sampling
UFnFE flag/
UFnOVE flag
When low-level period is at least 11 bits
“0“
UFnBSF flag
INTLS
Figure 13-45. Example of Data Consistency Error Occurrence Timing When UFnBRF = 0
LTxDn output
LRxDn input
Start
bit
D0
D5
D6
D7
Stop
bit
Start
bit
D0
D5
D6
D7
Stop
bit
Next transmission is
not performed.
Data sampling
UFnBRF flag
“0“
During reception
operation
Mismatch detection
UFnTSF flag
Error judgment
(internal signal)
UFnDCE flag
INTLS
Remark n = 0, 1
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Figure 13-46. Example of Consistency Error Occurrence Timing During BF Transmission When UFnBRF = 1
(If Reception Operation Is Stopped When Input Data “1” Is Detected After Stop Bit (Previous Bit Is “1”))
BF length
LTxDn output
LRxDn input
BF
length
Stop
bit
Stop
bit
Next transmission is
not performed.
Data sampling
UFnBRF flag
“1“
Mismatch
detection
Reception operation
is stopped.
UFnTSF flag
Error judgment
(internal signal)
UFnDCE flag
INTLS
Figure 13-47. Example of Consistency Error Occurrence Timing During BF Transmission When UFnBRF = 1 (If
During Reception Operation When Input Data “1” Is Detected After Stop Bit (Previous Bit Is “0”))
LTxDn output
LRxDn input
BF length
Stop
bit
BF
length
Stop
bit
Next transmission is
not performed.
Data sampling
UFnBRF flag
“1“
Mismatch detection
During reception
operation
UFnTSF flag
Error judgment
(internal signal)
UFnDCE flag
INTLS flag
Remark n = 0, 1
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13.5.10 LIN-UART reception status interrupt generation sources
LIN-UART reception status interrupt generation sources include parity errors, framing errors, overrun errors, data
consistency errors which occur only during LIN communication, successful BF reception, ID parity errors, checksum errors,
and response preparation errors which occur only in automatic baud rate mode, and ID matches and expansion bit
detections which occur only when expansion bits are enabled. When these sources are detected, LIN-UARTn reception
status interrupt (INTLSn) is generated. The type of a generation source can be referenced by using the status register
(UFnSTR). The content of processing is determined by referencing the UFnSTR register in the LIN-UARTn reception
status interrupt servicing routine.
Status flags must be cleared by writing “1” to the corresponding bits (excluding the UFnTSF and UFnRSF bits of the
UFnSTC register) by using software.
The LIN-UART reception status interrupt generation timing and status flag change timing differ, depending on the mode
setting and generation source.
Table 13-3. LIN-UART Reception Status Interrupt Generation Sources
Status Flag
UFnPE
Generation Source
Parity error
Description
The parity calculation result of receive data and the value of the
received parity bit do not match.
UFnFE
Framing error
No stop bit is detected.
(A low level is detected at a stop bit position.)
UFnOVE
Overrun error
The next data reception is completed before the receive data
transferred to the receive data register is read.
UFnDCE
Data consistency error
The data consistency check selection bit (UFnDCS) is set, and the
values of transmit data and receive data do not match during data
transmission. Transmission operation and reception operation are
out of synchronization.
UFnBSF
Successful BF reception
A new BF is successfully received when in BF reception enable
mode during communication (UFnMD1, UFnMD0 = 10B).
(This
occurs also when the master transmits a BF.)
UFnIPE
ID parity error
Either parity bit of the received PID includes an error.
UFnCSE
Checksum error
The result of comparing the checksum received during response
reception and the automatically calculated result is illegal.
UFnRPE
Response
preparation
error
UFnIDM
ID match
Response preparation could not be performed before reception of
the first byte by a response was completed.
When the following conditions are satisfied:
- Comparison of expansion bit data is enabled (UFnEBC = 1).
- The expansion bit is at the level set by using the expansion bit
detection level selection bit (UFnEBL).
- The received data matches the value of the UFnID register.
UFnEBD
Expansion bit detection
The level set by using the expansion bit detection level select bit
(UFnEBL) is detected at a receive data expansion bit.
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The following processing is required depending on the generation source when a status interrupt is generated.
Parity error, data consistency error
False data has been received, so read the received data and then discard it. Then perform communication again. If
the received data is not read, an overrun error might occur when reception ends next time. For a data consistency
error, a data conflict may also be possible.
Framing error
The stop bit could not be detected normally, or a bit offset may have occurred due to false detection of the start bit.
Furthermore, the baud rate may be offset from that of the transmission side or a BF of insufficient length may have
been received in LIN communication.
When framing errors occur frequently, a bit or the baud rate may be offset, so perform initialize processing on both
the transmission side and reception side, and restart communication. Furthermore, to receive the next data after a
framing error has occurred, the reception pin must become high level once.
Overrun error
Data of one frame that was received immediately before is discarded, because the next reception is completed before
receive data is read. Consequently, the data must be retransmitted.
Successful BF reception
Preparation for starting a new frame slot must be performed, because a new BF has been received successfully.
ID parity error
Set a request bit without a response (UFnNO), because the received PID is illegal. Afterward, do not perform
response transmission or reception, wait for the next BF to be received, and ignore that frame.
Checksum error
Discard the received response (data field), because it is illegal.
Response preparation error
Wait for the next BF to be received and ignore that frame, because response processing cannot be performed
normally.
ID match
Receive data of the expansion bit of a level set by using the UFnEBL bit has matched with the UFnID register setting
value. Perform, therefore, corresponding processing such as disabling expansion bit data comparison (UFnEBC = 0)
to receive subsequent data.
Expansion bit detection
Perform corresponding processing such as preparing for starting DMA transfer, because receive data of the
expansion bit of a level set by using the UFnEBL bit has been received.
Caution Status flags are an accumulation of all sources that have been generated after the status flag has
been cleared, and do not reflect the latest state. Consequently, the above-mentioned processing
must be completed before the next reception is completed and the status flag must be cleared.
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The following table shows examples of processing corresponding to statuses when performing LIN communication.
Table 13-4. Examples of Processing Corresponding to Statuses During LIN Communication (When in BF
Reception Enable Mode During Communication (UFnMD1, UFnMD0 = 10B) and When UFnDCS = 1)
UFnBSF UFnDCE UFnFE UFnOVE
1
1
Status
Processing Example
A mismatch is detected between transmit The next data (Sync field) transmission is
and receive data during BF transmission in
not performed and waiting for the next
master operation. Successive low levels of
time schedule is performed, because the
at least 11 bits are received.
other party of communication may not
The
transmission is not performed even if the
next data transmission has been prepared.
have been able to recognize the BF.
The other party of communication may
not have been able to recognize the BF,
but all status flags are cleared and the
next data is written to transmit the next
data (Sync field).
1
0
BF transmission and BF reception are Processing to transmit the next data (Sync
performed successfully in master operation.
field) is performed.
BF reception is performed successfully in Processing to receive the next data (Sync
slave operation.
0
1
field) is performed.
BF transmission or data (including an SF or Subsequent transmit and receive data is
a PID) transmission has failed in master discarded, all status registers are cleared,
operation.
and the system waits for the next time
Even if transmission of the next data or BF schedule.
has been prepared, the transmission will
not be performed.
Data transmission has failed in slave Subsequent transmit and receive data is
operation.
discarded, all status registers are cleared,
Even if transmission of the next data has and the system waits for the next time
been prepared, the transmission will not be schedule.
performed.
0
0
0
0
1
1
A framing error has been detected during Processing when a framing error has been
data reception.
detected is performed.
An overrun error has been detected during
Processing when an overrun error has
data reception.
been detected is performed.
The single data that was received
immediately before has been discarded.
Cautions 1. Clear all status flags that have been set for any processing.
2. When an error is detected in LIN communication (including when BF reception has been
performed successfully when BF reception enable mode during communication (UFnMD1,
UFnMD0 = 10B) has been set), a status interrupt request signal (INTLSn) is generated instead of a
reception complete interrupt request signal (INTLRn) and a status flag is set according to the
communication status.
Remark
: don’t care
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13.5.11 Transmission start wait function
The RL78/D1A is provided with a function to guarantee the stop bit length of reception when reception is switched to
transmission to perform LIN communication.
To delay starting of transmission until completion of the stop bit of reception, write data to the UFnWTX register which is
a wait-dedicated register, instead of writing transmit data to the UFnTX register as a transmission start request.
In this case, starting transmission is being waited for one bit until the stop bit of receive data has ended for sure.
Note that only a wait of one bit is performed, even if the stop bit length has been set to two bits by using the stop bit
length select bit (UFnSL).
Figure 13-48. When Transmit Data Has Been Written During Stop Bit of Receive Data
UFnTX is written
START
LTxDn pin
START
LRxDn pin
BIT0
STOP
BIT0
START
BIT0
STOP is shortened
Sampling
point
Half the
reception
baud rate
clock period
Half the
reception
baud rate
clock period
Reception baud rate
clock period
LTxDn pin
UFnWTX is written
START
LRxDn pin
BIT0
STOP
START
START
STOP length of 1 bit is guaranteed
Sampling
point
Half the
reception
baud rate
clock period
Reception baud rate
clock period
Reception baud rate
clock period
Half the
reception
baud rate
clock period
Cautions 1. When LIN communication is not performed, accessing the UFnWTX register is prohibited.
2. Writing to the UFnWTX register is prohibited except when reception is switched to transmission
(such as during transmission).
Remark n = 0, 1
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13.6 UART Buffer Mode
The RL78/D1A is provided with a 9-byte transmission buffer that can be used for normal UART communication
(UFnMD1, UFnMD0 = 00B).
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13.6.1 UART buffer mode transmission
The following figure shows the procedure for transmitting data in UART buffer mode.
Figure 13-49. UART Buffer Mode Transmission Processing Flow
START
Baud rate setting
(UFnCTL1 register)
Transmit data level setting
(UFnOPT0 register)
Various mode settings
(UFnOPT1 register)
INTLT timing setting
(UFnOPT2 register)
Various mode settings,
enabling transmission
(UFnCTL0 register)
Writing transmit data
(UFnBUF0 to UFnBUF8
registers)
UFnTRQ = 1,
UFnBUL3 to UFnBUL0 = XH
(UFnBUCTL register)
No
INTLT signal generated?
Yes
Read UFnSTR registerNote
Clear UFnBUC flag
(UFnSTC register)
No
All transmit data written?
Yes
END
Note This can be omitted.
Cautions 1. Set the following values when performing data transmission in UART buffer transmission mode.
Expansion bits are disabled (UFnEBE = 0).
Normal UART mode (UFnMD1, UFnMD0 = 00B).
Data consistency checking is disabled (UFnDCS = 0).
Waiting for buffer transmission start is disabled (UFnTW = 0).
Continuation of transfer is disabled (UFnCON = 0).
Request bits without responses are present (UFnNO = 0).
Reception requests are disabled (UFnRRQ = 0).
2. UFnPRQ must not be set to 1 before completion of receive data reading.
Remarks 1.
2.
See (2) of 13.11 Cautions on Use for details of starting LIN-UART.
X: don’t care
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When transferring the number of bytes (1 to 9) set to the buffer length bit (UFnBUL3 to UFnBUL0) has ended, a
transmission interrupt request signal (INTLTn) is output. When the buffer length bit is set to “0” or “10 to 15”, transfer of
nine bytes is performed.
Writing data to the transmit data register (UFnTX) during transmission in buffer mode is prohibited.
To stop transfer midway, write “0” to the transmission enable bit (UFnTXE). Data transmission processing is stopped
and the UFnTRQ bit and UFnTSF flag are cleared.
Figure 13-50. UART Buffer Mode Transmission Example (UFnITS = 0)
Sets UFnTRQ bit to 1
Set
Set
UFnTRQ bit
UFnBUL3 to UFnBUL0 bits
(write)
UFnBUL3 to UFnBUL0 bits
(read)
0
0 1
2
3
m
8
9
0 1
2
3
m
UFnTSF flag
1st data
LTxD0 pin
2nd data
7th data
8th data
9th data
1st data
2nd data
(m−1)th data
(m)th data
INTLT
(UFnITS = 0)
UFnBUC flag
Prepare next TX
Clear
Prepare next TX
Clear
Sets UFnCLBUC bit to 1
Figure 13-51. UART Buffer Mode Transmission Example (UFnITS = 1)
Sets UF0TRQ bit to 1
Set
Set
UF0TRQ bit
UF0BUL3 to UF0BUL0 bits
(write)
UF0BUL3 to UF0BUL0 bits
(read)
0
0
1
m
2
7
8
2nd data
7th data
8th data
9
0
1
2
1st data
2nd data
m
m1
UF0TSF flag
1st data
LTxD0 pin
9th data
(m−1)th data (m)th data
INTLT
(UF0ITS = 1)
UF0BUC flag
Clear
Clear
Sets UF0CLBUC bit to 1
Prepare next TX
Remark
Prepare next TX
m = 1 to 9
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13.7 LIN Communication Automatic Baud Rate Mode
In LIN communication automatic baud rate mode, a BF and an SF are automatically detected and the baud rate is set
according to the measurement result of the SF.
When UFnMD1 and UFnMD0 are set to “11B”, operation is performed in automatic baud rate mode.
Operation can be performed with the baud rate at 2,400 bps to 128 kbps. Set to 8 to 12 MHz the clock (prescaler
clock) that has been divided by using a prescaler. At that time, the setting values of UFnPRS2 to UFnPRS0 must be
calculated from the fCLK frequency and initial settings must be performed.
When using LIN-UART as the master, using automatic baud rate mode (UFnMD1, UFnMD0 = 11B) is prohibited.
Figure 13-52. Basic Processing Flow Example of LIN Communication Automatic Baud Rate Mode (1/2)
Initial settings
INTLS processing
Prescaler setting
(UFnCTL1 register)
Read UFnSTR register
Transmit data level
(UFnOPT0 register)
Clear status flag
(UFnSTC register)
Various mode settings
(UFnOPT1)
Processing corresponding
to status
Noise filter,
INTLT timing settings
(UFnOPT2)
END
Various mode settings,
enabling transmission/reception
(UFnCTL0)
END
Cautions 1. Set the following values when performing LIN communication automatic baud rate mode.
The transmit and receive data levels are normal input (UFnTDL = UFnRDL = 0).
Expansion bits are disabled (UFnEBE = 0).
Automatic baud rate mode (UFnMD1, UFnMD0 = 11B) as the mode.
Consistency check selection (UFnDCS = 1).
Transmission interrupt is transmission start (UFnITS = 0).
Communication direction control is LSB first (UFnDIR = 1).
The parity selection bit is received without parity (UFnPS1, UFnPS0 = 00B).
The data character length is 8 bits (UFnCL = 1).
Transmit data register is default value (UFnTX = 0000H).
2. Set the UFnPRS2 to UFnPRS0 bits so that the clock that has been divided by using a prescaler is
8 to 12 MHz.
3. The checksum field should be included when UFnACE = 0.
Remark See (2) of 13.11 Cautions on Use for details of starting LIN-UART.
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Figure 13-52. Basic Processing Flow Example of LIN Communication Automatic Baud Rate Mode (2/2)
INTLR processing
Read UFnSTR register
UFnHDC = 1?
No
Yes
No
Clear UFnHDC flag
(UFnSTC register)
Read receive dataNote
(UFnBUF0 to UFnBUF8
registers)
Read UFnID register
Clear UFnBUC flag
(UFnSTC register)
Target PID?
Yes
UFnTW = 0, UFnCON = 0,
UFnECS = ´, UFnNO = 1,
UFnRRQ = 0, UFnTRQ = 0,
UFnBUL3 to UFnBUL0 = ´H
(UFnBUCTL register)
Response received?
Yes
UFnTW = 0, UFnCON = 0,
UFnECS = ´, UFnNO = 0,
UFnRRQ = 1, UFnTRQ = 0,
UFnBUL3 to UFnBUL0 = ´H
(UFnBUCTL register)
No
Write transmit data
(UFnBUF0 to UFnBUF7
registers)
No
UFnACE = 0?
Yes
Write transmit data (checksum)
(UFnBUF1 to UFnBUF8 registers)
UFnTW = 1, UFnCON = 0,
UFnECS = ´, UFnNO = 0,
UFnRRQ = 0, UFnTRQ = 1,
UFnBUL3 to UFnBUL0 = ´H
(UFnBUCTL register)
END
Note This can be omitted.
Cautions 1. When the buffer length bits (UFnBUL3 to UFnBUL0) have been set to “0” or “10 to 15”, reception
or transmission of nine bytes is performed. When the buffer length is set to “1 to 8”, buffers of
the number of bytes set are used in ascending order of the buffer numbers.
Example: When UFnBUL3 to UFnBUL0 are set to “1”, data is always stored only into the
UFnBUF0 register.
2. Do not set the UFnRRQ bit before completion of receive data reading, because, when the
UFnRRQ bit is set, storing (overwriting) into a buffer is performed even if reading receive data
has not ended.
3. Setting (1) the UFnTW bit is prohibited, except when operation is switched to response
transmission after header reception.
Remark
: don’t care
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If a PID stored into the UFnID register is not a target when header reception is completed (UFnHDC = 1), the UFnNO
bit is set and subsequent transmission and reception processing are stopped (responses are ignored).
For a response reception PID, the UFnRRQ bit is set at the same time as the response data length (UFnBUL3 to
UFnBUL0), and response reception processing is performed.
For a response transmission PID, the UFnTRQ bit is set at the same time as the response data length (UFnBUL3 to
UFnBUL0), and response transmission processing is performed, after transmit data has been set to a buffer. At that time,
the receive data will be stored in the UFnRX register. However, no overrun error will occur even if the receive data is not
read.
Perform processing (setting the UFnNO, UFnRRQ, or UFnTRQ bit) for the PID before receiving the first byte of the
response is completed. Otherwise, a response preparation error occurs. See 13.7.2 Response preparation error
detection function for details.
During response reception and response transmission also, when a status interrupt request signal (INTLSn) has been
generated due to an error, transmission and reception operations are stopped and waiting for the next BF reception is
performed.
In automatic baud rate mode, no overrun error occurs, because a buffer is used (the UFnRX register is not used).
Figure 13-53. LIN Communication Automatic Baud Rate Mode (Non-Target PID)
LTxDn pin
“H”
LRxDn pin
BF
SF
PID
data
data
UFnID register
INTLS
CSF
Wait for next successful BF
reception
PID
“L”
INTLR
Sets UFnCLHDC bit to 1
UFnHDC flag
UFnBUC flag
“L”
Clear
Transmission/
reception stopped
UFnNO bit
UFnRRQ bit
“L”
UFnTRQ bit
“L”
UFnBUL3 to UFnBUL0 bits
(write)
m
UFnBUL3 to UFnBUL0 bits
(read)
0
Set
Sets UFnNO bit to 1
Remark n = 0, 1, m = 1 to 9
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Figure 13-54. LIN Communication Automatic Baud Rate Mode (Response Reception)
“H”
LTxDn pin
LRxDn pin
BF
SF
PID
data
data
UFnID register
CSF
Wait for next successful BF
reception
PID
INTLS
“L”
INTLR
UFnHDC flag
Sets UFnCLHDC bit to 1
UFnBUC flag
UFnNO bit
Clear
Clear
“L”
Sets UFnCLBUC bit to 1
UFnRRQ bit
UFnTRQ bit
“L”
UFnBUL3 to UFnBUL0 bits
(write)
m
UFnBUL3 to UFnBUL0 bits
(read)
0
1
(m1)
m
Set
Sets UFnRRQ bit to 1
An example of how reception results are stored into a buffer when 8-byte data is received (UFnBUL3 to UFnBUL0 = 9)
and when 3-byte data is received (UFnBUL3 to UFnBUL0 = 3) are shown below.
(1) When 8-byte data is received
(2) When 3-byte data is received
(UFnBUL3 to UFnBUL0 = 9)
(UFnBUL3 to UFnBUL0 = 4)
Reception results
Reception results
UFnBUF8
Checksum
UFnBUF8
UFnBUF7
Data7
UFnBUF7
UFnBUF6
Data6
UFnBUF6
UFnBUF5
Data5
UFnBUF5
UFnBUF4
Data4
UFnBUF4
UFnBUF3
Data3
UFnBUF3
Checksum
UFnBUF2
Data2
UFnBUF2
Data2
UFnBUF1
Data1
UFnBUF1
Data1
UFnBUF0
Data0
UFnBUF0
Data0
Caution When UARTF is being used with the auto checksum feature enabled (UFnACE = 1), the checksum
data is not stored in a buffer.
Remark n = 0, 1
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Figure 13-55. LIN Communication Automatic Baud Rate Mode (Response Transmission)
data
LTxDn pin
LRxDn pin
BF
SF
PID
data
data
data
UFnID register
INTLS
CSF
CSF
Wait for next successful BF
reception
PID
“L”
INTLT
INTLR
UFnHDC flag
Set UFnCLHDC to 1.
UFnBUC flag
UFnNO bit
“L”
UFnRRQ bit
“L”
Clear
Clear
Set UFnCLBUC to 1.
UFnTRQ bit
UFnBUL3 to UFnBUL0 bits
(Write)
m
UFnBUL3 to UFnBUL0 bits
(Read)
0
1
2
m
Set
Set UFnTRQ to 1.
Examples of the buffer settings and the status of the buffer after 8 bytes of data have been transmitted (UFnBUL3 to
UFnBUL0 = 9) and after 3 bytes of data have been transmitted (UFnBUL3 to UFnBUL0 = 3) are shown below.
(1) When 8-byte data is transmitted (UFnBUL3 to UFnBUL0 = 9)
Buffer setting
Buffer status
UFnBUF8
TX Checksum
RX Checksum
UFnBUF7
Data7
Data7
UFnBUF6
Data6
Data6
UFnBUF5
Data5
Data5
UFnBUF4
Data4
Data4
UFnBUF3
Data3
Data3
UFnBUF2
Data2
Data2
UFnBUF1
Data1
Data1
UFnBUF0
Data0
Data0
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(2) When 3-byte data is received (UFnBUL3 to UFnBUL0 = 4)
Buffer setting
Buffer status
UFnBUF8
UFnBUF7
UFnBUF6
UFnBUF5
UFnBUF4
UFnBUF3
Checksum
Checksum
UFnBUF2
Data2
Data2
UFnBUF1
Data1
Data1
UFnBUF0
Data0
Data0
Caution To enable the automatic checksum function (UFnACE = 1), checksum is not required to be set to the
buffer by using software.
Remark n = 0, 1
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13.7.1 Automatic baud rate setting function
Received low-level widths are always measured when in automatic baud rate mode. BF detection is judged as being
performed successfully when the first low-level width is at least 11 times the second low-level width, and it is checked that
the data is 55H. If the data is confirmed to be 55H and the SF is judged to have been successfully received, reception is
paused, the UFnBRS11 to UFnBRS00 bits are set again, and reception resumes after the start bit is detected.
When it has been confirmed that the data is 55H, successful SF detection is judged and baud rate setting results are
automatically set to the UFnBRS11 to UFnBRS00 bits. At that time, the settings of the UFnPRS2 to UFnPRS0 bits are not
changed. Afterward, the next data (PID) is received after transmission or reception processing has been enabled.
A
reception complete interrupt request signal (INTLRn) is generated when there are no errors upon PID reception
completion (stop bit position), and an error flag is set and a status interrupt request signal (INTLSn) is generated when
there is an error. In both cases, a header reception completion flag (UFnHDC) is set. On the other hand, when the data is
not 55H, SF detection is judged to have failed, the next BF (low level) reception is being waited for with the transmission or
reception processing being stopped, and baud rate setting is not performed.
When the stop bit position of reception processing is reached while transmission or reception processing is enabled,
errors such as framing errors and consistency errors are detected and a status interrupt request signal (INTLSn) may be
generated. This is also applicable when a BF has been received during communication.
Figure 13-56. Example of BF/SF Reception Failure
A < B × 11
BF failed
A
B
B ≥C ×11
BF successful
transmission/
reception
disabled
Wait for next successful
BF reception
55H failed
C
LRxDn pin
55H checked, based on C/2
Transmission/reception stopped
Internal successful
BF flag
Internal successful
SF flag
“L”
UFnHDC flag
“L”
INTLS
“L”
INTLR
“L”
UFnBRS11 to
UFnBRS00 bits
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CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
Figure 13-57. Example of Successful BF, SF, and PID Reception
B ≥ C × 11
BF successful
transmission/
reception disabled
55H successful
Baud rate setting
transmission/
reception enabled
C
B
PID
LRxDn pin
55H checked, based on C/2
Transmission/
reception stopped
Sets UFnCLHDC bit to 1
Clear
Internal successful
BF flag
Internal successful
SF flag
UFnHDC flag
INTLS
“L”
INTLR
UFnBRS11 to
UFnBRS00 bits
Old value
New value
Caution When a PID reception error has occurred, a status interrupt request signal (INTLSn) is generated
instead of a reception complete interrupt request signal (INTLRn) and other error flags (such as
UFnFE and UFnIPE) change.
Figure 13-58. Example of Successful BF Reception During SF Reception (No PID Reception Error)
B ≥ C × 11
BF successful
transmission/
55H failed
reception disabled
B
C
D
D ≥ E × 11
BF successful
transmission/
reception disabled
E/2
55H successful
Baud rate setting
transmission/
reception enabled
PID
LRxDn pin
55H checked,
based on C/2
55H checked, based on E
Transmission/reception stopped
Internal successful
BF flag
Sets UFnCLHDC bit to 1
Clear
Internal successful
SF flag
UFnHDC flag
INTLS
“L”
INTLR
UFnBRS11 to
UFnBRS00 bits
Old value
New value
Caution When a PID reception error has occurred, a status interrupt request signal (INTLSn) is generated
instead of a reception complete interrupt request signal (INTLRn) and other error flags (such as
UFnFE and UFnIPE) change.
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Figure 13-59. Example of Successful BF Reception During PID Reception (No PID2 Reception Error)
D ≥ E × 11
BF successful
transmission/
reception disabled
55H successful
Baud rate setting
transmission/
reception enabled
D
LRxDn pin
55H successful
Baud rate setting
transmission/
reception enabled
E
PID1
PID2
55H checked
55H checked, based on E
Sets UFnCLHDC bit to 1
Transmission/reception stopped
Internal successful
BF flag
Internal successful
SF flag
Sets UFnCLHDC bit to 1
Transmission/
reception
stopped
Clear
Clear
Stop bit position
UFnFE = 1
UFnHDC flag
INTLSn
INTLRn
UFnBRS11 to
UFnBRS00 bits
Old value
New value1
New value2
Caution If the PID1 stop bit position comes after the point where the internal successful BF flag has been set,
the UFnHDC flag and error flags (such as UFnFE and UFnIPE) are not set, and INTLSn is also not
generated.
Figure 13-60. Example of Successful BF Reception During Data/CSF Reception (No PID Reception Error)
D ≥ E × 11
BF successful
transmission/
reception disabled
D
E
Data/CSF
LRxDn pin
55H successful
Baud rate setting
transmission/
reception enabled
PID
55H checked, based on E
Sets UFnCLHDC bit to 1
Transmission/
reception
stopped
Internal successful
BF flag
Internal successful
SF flag
UFnHDC flag
Clear
Stop bit position
UFnFE = 1
(UFnDCE = 1)
INTLSn
INTLRn
UFnBRS11 to
UFnBRS00 bits
Old value
New value
Caution If the Data/CSF stop bit position comes after the point where the internal successful BF flag has been
set, the UFnBUC flag and error flags (such as UFnFE, UFnDCE, UFnCSE, and UFnRPE) are not set,
and INTLSn is also not generated.
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13.7.2 Response preparation error detection function
If response preparation (setting of the UFnNO, UFnRRQ, and UFnTRQ bits) is not performed before reception of the
first byte by a response is completed (sampling point of the stop bit (first bit)) when in automatic baud rate mode (UFnMD1,
UFnMD0 = 11B), a response preparation error flag (UFnRPE) is set, a status interrupt request signal (INTLSn) is
generated, and subsequent transmission and reception processing are stopped (responses are ignored) without data
being stored.
When response transmission is started (UFnTRQ = 1) after reception at the LRxDn pin has been started, recognition
can be performed by the occurrence of consistency errors.
Figure 13-61. Response Preparation Error Occurrence Example
LRxDn pin
BF
SF
data
PID
data
CSF
Bit4
Bit5
BF wait successful
INTLRn
UFnHDC flag
Clear
Sets UFnCLHDC bit to 1
Start
LRxDn pin
Bit0
Bit1
Bit2
Bit3
Bit6
Bit7
Stop
Sampling point
UFnNO bit
“L”
UFnRRQ bit
“L”
UFnTRQ bit
“L”
Transmission/
reception stopped
All “L”
INTLSn
UFnRPE flag
Caution If UFnCON = 0, no response preparation error will occur, because a BF reception wait state is entered after
communication of the number of bytes set using the UFnBUL3 to UFnBUL0 bits is completed.
If UFnCON = 1, a response preparation error check state is entered again after communication of the
number of bytes set using the UFnBUL3 to UFnBUL0 bits is completed.
A response preparation error will occur if a receive operation is started before setting UFnTRQ the next time
after response transmission is completed.
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13.7.3 ID parity check function
When the ID parity check select bit is set (UFnIPCS = 1) in automatic baud rate mode (UFnMD1, UFnMD0 = 11B), the
PID parity bits (P0, P1) are checked when the received PID is stored into the UFnID register. At that time, if either parity
bit includes an error, an ID parity error flag (UFnIPE) is set, a status interrupt request signal (INTLSn) is generated instead
of a reception complete interrupt request signal (INTLRn), and the PID is stored into the UFnID register.
Figure 13-62. PID Parity Error Occurrence Example
LRxDn pin
start
ID0
ID1
ID2
ID3
ID4
ID5
P0
P1
stop
Error present
PID
UFnID register
INTLSn
UFnIPE flag
Sets UFnCLIPE bit to 1
Clear
13.7.4 Automatic checksum function
When the automatic checksum enable bit is set (UFnACE = 1) in automatic baud rate mode (UFnMD1, UFnMD0 = 11B),
a checksum is automatically calculated. Enhanced checksum (calculation targets: PID and data) and classic checksum
(calculation target: only data) can be selected for each frame by using the enhanced checksum selection bit (UFnECS).
During response transmission, calculation is performed when data is transferred in 1-byte units from a buffer register to
a transmit shift registerNote, and the calculation result is automatically added to the end of response transmission and
transmitted. A checksum is not required to be set to a buffer by using software.
During response reception, calculation is performed when data is stored into a buffer register in 1-byte units
Note
, and the
stored data and calculation result are automatically compared when the received checksum is stored into a buffer. A
reception complete interrupt request signal (INTLRn) is generated when the comparison result is correct.
If the
comparison result is illegal, however, a status interrupt request signal (INTLSn) is generated instead of a reception
complete interrupt request signal (INTLRn), a checksum error flag (UFnCSE) is set, and the checksum is stored into the
UFnRX register.
Note When the enhanced checksum is selected, the value of the UFnID register is set to its initial value for calculation
at the time transfer starts.
Remark n = 0, 1
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Figure 13-63. Automatic Checksum Error Occurrence Example (Response Reception)
LTxDn pin
“H”
LRxDn pin
BF
SF
PID
data
data
CSF
Wait for next successful BF
reception
INTLS
INTLR
UFnHDC flag
Sets UFnCLHDC bit to 1
UFnBUC flag
UFnNO bit
Clear
Clear
“L”
Sets UFnCLBUC bit to 1
Sets UFnCLCSE bit to 1
UFnRRQ bit
UFnTRQ bit
“L”
UFnBUL3 to UFnBUL0 bits
(write)
m
UFnBUL3 to UFnBUL0 bits
(read)
UFnCSE flag
0
Sets UFnRRQ bit to 1
1
( m- 1)
Set
Remark n = 0, 1, m = 1 to 9
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13.7.5 Multi-byte response transmission/reception function
In normal LIN communication, a response is no more than 9 bytes (including the checksum field); but in automatic baud
rate mode (UFnMD1, UFnMD0 = 11B), responses of at least 10 bytes can be transmitted and received.
The processing flow of initial settings and INTLSn generation is same as the basic processing flow. See 13.7 LIN
Communication Automatic Baud Rate Mode.
The response preparation error detection function, ID parity check function, and automatic checksum function are valid.
Figure 13-64. Multi-Byte Transmission/Reception Processing Flow Example (1/2)
INTLRn processing
Read UFnSTR register
No
UFnHDC = 1?
Yes
No
Clear UFnHDC flag
(UFnSTC register)
Read receive dataNote
(UFnBUF0 to
UFnBUF8 registers)
Read UFnID register
Clear UFnBUC flag
(UFnSTC register)
Target PID?
Last byte?
(UFnCON = 0)
Yes
UFnTW = 0, UFnCON = 0,
UFnECS = ×, UFnNO = 1,
UFnRRQ = 0, UFnTRQ = 0,
UFnBUL3 to UFnBUL0 = ×H
(UFnBUCTL register)
No
Yes
Response received?
Yes
No
No
Response received?
(Data length ≤ 9)
END
Yes
A
B
End upon next response?
UFnTW = 0, UFnCON = 0,
UFnECS = ×, UFnNO = 0,
UFnRRQ = 1, UFnTRQ = 0,
UFnBUL3 to UFnBUL0 = ×H
(UFnBUCTL register)
Response received?
(Data length > 9)
No
No
Yes
Yes
A
B
C
UFnTW = 0, UFnCON = 1,
UFnECS = ×, UFnNO = 0,
UFnRRQ = 1, UFnTRQ = 0,
UFnBUL3 to UFnBUL0 = ×H
(UFnBUCTL register)
END
TX
Note This can be omitted.
Remark
×: don’t care, n = 0, 1
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Figure 13-64. Multi-Byte Transmission/Reception Processing Flow Example (2/2)
TX
Response transmitted?
(Data length ≤ 9)
C
No
Yes
End upon next response?
No
Yes
Write transmit data
(UFnBUF0 to
UFnBUF7 registers)
Write transmit data
(UFnBUF0 to
UFnBUF7 registers)
Write transmit data
(UFnBUF0 to
UFnBUF8 registers)
No
No
UFnACE = 0?
UFnACE = 0?
Yes
Yes
Write transmit data (checksum)
(UFnBUF1 to
UFnBUF8 registers)
Write transmit data (checksum)
(UFnBUF1 to
UFnBUF8 registers)
UFnTW = 1, UFnCON = 0,
UFnECS = ×, UFnNO = 0,
UFnRRQ = 0, UFnTRQ = 1,
UFnBUL3 to UFnBUL0 = ×H
(UFnBUCTL register)
UFnTW = 0, UFnCON = 0,
UFnECS = ×, UFnNO = 0,
UFnRRQ = 0, UFnTRQ = 1,
UFnBUL3 to UFnBUL0 = ×H
(UFnBUCTL register)
UFnTW = 0/1Note, UFnCON = 1,
UFnECS = ×, UFnNO = 0,
UFnRRQ = 0, UFnTRQ = 1,
UFnBUL3 to UFnBUL0 = ×H
(UFnBUCTL register)
END
END
END
Note Set UFnTW to 1 during only the first data transmission after PID reception.
Cautions 1. When the buffer length bits (UFnBUL3 to UFnBULn) have been set to “0” or “10 to 15”, reception
or transmission of nine bytes is performed. When the buffer length is set to “1 to 8”, buffers of
the number of bytes set are used in ascending order of the buffer numbers.
Example: When UFnBUL3 to UFnBUL0 are set to “1”, data is always stored only into the
UFnBUF0 register.
2. Do not set the UFnRRQ bit before completion of receive data acquisition.
3. Setting the UFnTW bit is prohibited, except when operation is switched to response transmission
after header reception.
Remark
×: don’t care, n = 0, 1
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Figure 13-65. Multi-Byte Reception Implementation Example
“H”
LTxDn pin
LRxDn pin
Response preparation
check
BF
INTLSn
SF
PID
data
Response preparation
check
data
data
Response preparation check
data
data
CSF
“L”
INTLRn
UFnHDC flag
Sets UFnCLHDC bit to 1
UFnBUC flag
Clear
Sets
UFnCLBUC
bit to 1
Clear
Sets
UFnCLBUC
bit to 1
Clear
Clear
UFnRRQ bit
UFnCON bit
UFnTRQ bit
“L”
UFnBUL3 to UFnBUL0 bits
(write)
2
UFnBUL3 to UFnBUL0 bits
(read)
0
2
1
Set
Sets UFnRRQ bit to 1
Sets UFnCON bit to 1
2
0
1
Set
Sets UFnRRQ bit to 1
2
2
0
1
2
Set
Sets UFnRRQ bit to 1
Clears UFnCON bit to 0
Caution When UFnBUL3 to UFnBUL0 are “2”, data is always stored into UFnBUF0 and UFnBUF1.
If read processing of the receive data is not performed in time, make adjustments such as setting
UFnBUL3 to UFnBUL0 to “1”.
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Figure 13-66. Multi-Byte Transmission Implementation Example
LTxDn pin
data
LRxDn pin
BF
INTLS
SF
PID
data
data
data
data
data
data
data
data
data
data
data
CSF
data
data
CSF
Clear
Set
UFnCLBUC
to 1
Clear
“L”
INTLR
INTLT
UFnHDC flag
UFnBUC flag
Set UFnCLHDC to 1
Clear
UFnRRQ bit
Set
UFnCLBUC
to 1
Clear
“L”
Clear
UFnCON bit
UFnTRQ bit
UFnTW bit
UFnBUL3 to UFnBUL0 bits
(Write)
2
UFnBUL3 to UFnBUL0 bits
(Read)
0
Set
Set UFnCON to 1
Set UFnTRQ to 1
Set UFnTW to 1
1
2
2
0
Set
Set UFnTRQ to 1
1
2
2
0
1
Set
Set UFnTRQ to 1
2
2
0
1
2
Set
Clear UFnCON to 0
Set UFnTRQ to 1
Caution When UFnBUL3 to UFnBUL0 are “2”, data of the UFnBUF0 and UFnBUF1 bits are always transmitted
and stored.
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13.8 Expansion Bit Mode
When in normal UART mode (UFnMD1, UFnMD0 = 00B), data of 9-bit lengths can be transmitted or received by setting
the expansion bit enable bit (UFnEBE). See 13.5.1 Data format for the communication data format.
13.8.1 Expansion bit mode transmission
When in expansion bit mode (UFnCL = UFnEBE = 1), transmission in 9-bit lengths is started by writing 9-bit data to the
UFnTX register.
Figure 13-67. Expansion Bit Mode Transmission Example (LSB First)
9
LTxDn pin
data0
9
data1
9
data2
9
data3
9
data4
INTLT
(UFnITS = 0)
INTLT
(UFnITS = 1)
Remark n = 0, 1
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13.8.2 Expansion bit mode reception (no data comparison)
When in expansion bit mode (UFnCL = UFnEBE = 1) and expansion bit data comparison is disabled (UFnEBC = 0),
reception in 9-bit lengths can always be performed without data comparison. When a level set by using the expansion bit
detection level select bit (UFnEBL) is detected, a status interrupt request signal (INTLSn) is generated upon completion of
data reception, and an expansion bit detection flag (UFnEBD) is set. When an inverted value of the expansion bit
detection level is detected, a reception complete interrupt request signal (INTLRn) is generated. In either case, the
receive data is stored into the UFnRX register if no overrun error has occurred.
Figure 13-68. Expansion Bit Mode Reception (No Data Comparison) Example (LSB First, UFnEBL = 0)
data0
LRxDn pin
9
1
data1
9
0
data2
9
1
data3
9
0
data4
9
1
INTLR
INTLS
UFnEBD flag
Clear
Sets UFnCLEBD bit to 1
Clear
Sets UFnCLEBD bit to 1
Cautions 1. When a reception error (parity error, framing error, or overrun error) occurs at receive data 0, 2,
or 4, a status interrupt request signal (INTLSn) is generated instead of a reception complete
interrupt request signal (INTLRn), and the error flag is updated.
2. When a reception error (parity error, framing error, or overrun error) occurs at receive data 1 or 3,
the error flag is also updated.
Remark n = 0, 1
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13.8.3 Expansion bit mode reception (with data comparison)
When in expansion bit mode (UFnCL = UFnEBE = 1) and expansion bit data comparison is enabled (UFnEBC = 1), if a
level set by using the expansion bit detection level select bit (UFnEBL) is detected, 8 bits excluding the receive data
expansion bit are compared with the value of the UFnID register set in advance.
If the comparison results have matched, a status interrupt request signal (INTLSn) is generated, an expansion bit ID
match flag (UFnIDM) and an expansion bit detection flag (UFnEBD) are set, and the receive data is stored into UFnRX. If
the comparison results do not match, no interrupt is generated, no flag is updated, and the receive data is not stored.
Interrupts (INTLRn, INTLSn) are generated upon all subsequent completions of data receptions and data can be
received by disabling expansion bit data comparison (UFnEBC = 0) via the status interrupt servicing when the comparison
results have matched. End the processing before completion of the next data reception, because data will be omitted if
the UFnEBC bit is changed after the next data reception has been completed.
Figure 13-69. Expansion Bit Mode Reception (with Data Comparison) Example (LSB First, UFnEBL = 0)
data0
LRxDn pin
9
1
data1
9
0
data2
9
1
9
data3
data1
UFnID register
Masked
INTLR
0
data4
9
1
data5
9
0
data1
Data mismatch
Masked
Masked
Data match
INTLS
UFnEBD flag
UFnIDM flag
Sets UFnCLEBD bit to 1
Sets UFnCLIDM bit to 1
Clear
Sets UFnCLEBD bit to 1
Sets UFnEBC bit to 1
Clear
Sets UFnEBC bit to 1
Clear
UFnEBC bit
With data comparison
No data comparison
Set
With data comparison
Cautions 1. When a reception error (parity error, framing error, or overrun error) occurs at receive data 2, a
status interrupt request signal (INTLSn) is generated instead of a reception complete interrupt
request signal (INTLRn), and the error flag is updated.
2. When a reception error (parity error, framing error, or overrun error) occurs at receive data 1 or 3,
the error flag is also updated. When a reception error occurs at receive data 0, 4, or 5, the error
flag is not updated.
Remark n = 0, 1
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13.9 Receive Data Noise Filter
The probability of malfunctioning due to noise becomes high with UART reception, because no communication clock
exists. The noise filter is used to eliminate noise in a communication bus and reduce false reception of data. The noise
filter becomes valid by clearing the receive data noise filter use selection bit (UFnRXFL) to “0”.
A start bit and receive data input from a serial data input pin (LRxDn) are sampled with a clock (prescaler clock) divided
by using a prescaler.
When the same sampling value is read twice, the match detector output changes and the receive data is sampled as
the input data. Therefore, data not exceeding 2 clock width is judged to be noise and is not delivered to the internal circuit
(see Figure 13-70). See 13.10 (1) (a) Prescaler clock (fUCLK) regarding the base clock.
Figure 13-70. Noise Filter Circuit Example
UFnRXFL bit
FF4
FF1
LRxDn pin
D
R
Prescaler clock
FF2
D
CKE
R
FF3
D
CKE
R
1
LE
Receive data
D
CKE
R
0
fCLK
RESET
Figure 13-71. Noise Filter Timing Chart Example (UFnPRS = 1)
fCLK
Prescaler clock
(fUCLK)
LRxDn pin
FF1
FF2
FF3
FF4
Mismatch
(judged as noise)
Mismatch
(judged as noise)
Remark n = 0, 1
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13.10 Dedicated Baud Rate Generator
The dedicated baud rate generator consists of a 3-bit prescaler block and a 12-bit programmable counter, and
generates a serial clock during transmission and reception with LIN-UARTn. Regarding the serial clock, a dedicated baud
rate generator output can be selected for each channel.
There is a 12-bit counter for transmission and another one for reception.
(1) Configuration of baud rate generator
Figure 13-72. Configuration of Baud Rate Generator
UFnTXE or UFnRXE bit
UFnTXE (or UFnRXE) bit
Prescaler
clockNote
fCLK
Prescaler
12-bit counter
(fUCLK)
Match detector
UFnCTL1:
UFnPRS2 to UFnPRS0
1/2
Baud rate
UFnCTL1:
UFnBRS11 to UFnBRS00
Note Clock that divides fCLK by 1, 2, 4, 8, 16, 32, 64, or 128
In automatic baud rate mode, confirm that the receive pin is high before setting the UFnRXE bit to 1.
(a) Prescaler clock (fUCLK)
When the UFnEN bit of the PER register is “1”, a clock divided by a frequency division value specified by using
the UFnPRS2 to UFnPRS0 bits of the UFnCTL1 register is supplied to the 12-bit counter.
This clock is called the prescaler clock and its frequency is called fUCLK.
(b) Serial clock generation
A serial clock can be generated by setting the UFnCTL1 register.
The frequency division value for the 12-bit counter can be set by using the UFnBRS11 to UFnBRS00 bits of the
UFnCTL1 register.
Remark n = 0, 1
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CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
(2) LIN-UARTn control register 1 (UFnCTL1)
The UFnCTL1 register is a 16-bit register that is used to control the baud rate of LIN-UARTn.
This register can be read or written in 16-bit units.
Reset sets this register to 0FFFH.
Figure 13-73. Format of LIN-UARTn Control Register 1 (UFnCTL1)
Address: F0242H, F0243H (UF0CTL1), F0262H, F0263H (UF1CTL1)
15
After reset: 0FFFH
14
13
12
UFnPRS1
UFnPRS0
0
7
6
5
4
3
2
1
0
UFnBRS7
UFnBRS6
UFnBRS5
UFnBRS4
UFnBRS3
UFnBRS2
UFnBRS1
UFnBRS0
UFnPRS2
UFnPRS1
UFnPRS0
UFnCTL1 UFnPRS2
11
R/W
10
9
UFnBRS11 UFnBRS10 UFnBRS9
0
0
No division (prescaler clock = fCLK)
0
0
1
Division by 2 (prescaler clock = fCLK/2)
0
1
0
Division by 4 (prescaler clock = fCLK/4)
0
1
1
Division by 8 (prescaler clock = fCLK/8)
1
0
0
Division by 16 (prescaler clock = fCLK/16)
1
0
1
Division by 32 (prescaler clock = fCLK/32)
1
1
0
Division by 64 (prescaler clock = fCLK/64)
1
1
1
Division by 128 (prescaler clock = fCLK/128)
UFn
UFn
UFn
UFn
UFnBRS8
Prescaler clock frequency division value
0
UFn
8
UFn
UFn
UFn
UFn
UFn
UFn
UFn
k
Note
BRS1 BRS1 BRS0 BRS0 BRS0 BRS0 BRS0 BRS0 BRS0 BRS0 BRS0 BRS0
Serial
clock
1
0
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
4
fUCLK/4
0
0
0
0
0
0
0
0
0
1
0
0
4
fUCLK/4
0
0
0
0
0
0
0
0
0
1
0
1
5
fUCLK/5
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
1
1
0
4094 fUCLK/4094
1
1
1
1
1
1
1
1
1
1
1
1
4095 fUCLK/4095
:
:
1
0
Note Specified value
Cautions 1. Rewriting can be performed only when the UFnTXE and UFnRXE bits of the UFnCTL0
register are “0”.
2. The baud rate is the value that results by further dividing the serial clock by 2.
3. Writing to UFnBRS11 to UFnBRS00 is invalid when in automatic baud rate mode.
Remarks 1. fUCLK is the frequency division value of the prescaler clock selected by using the UFnPRS2 to
UFnPRS0 bits.
2. In automatic baud rate mode (UFnMD1, UFnMD0 = 11B), the value after the baud rate has been
set can be checked by reading UFnBRS11 to UFnBRS00 after header reception.
3. : don’t care
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(3) Baud rate
The baud rate is obtained by the following equation.
Baud rate =
fUCLK
2k
[bps]
fUCLK = Frequency of prescaler clock selected by the UFnPRS2 to UFnPRS0 bits of the UFnCTL1 register
k = Value set by using the UFnBRS11 to UFnBRS00 bits of the UFnCTL1 register (k = 4, 5, 6, …, 4095)
(4) Baud rate error
The baud rate error is obtained by the following equation.
Error (%) =
Actual baud rate (baud rate with error)
1 100 [%]
Target baud rate (correct baud rate)
Cautions 1. The baud rate error during transmission must be within the error tolerance on the
receiving side.
2. The baud rate error during reception must satisfy the range indicated in (6) Allowable
baud rate range during reception.
Example: CPU/peripheral hardware clock frequency = 24 MHz = 24,000,000 Hz
Setting values
fCLK = 24 MHz
Setting values of the UFnPRS2 to UFnPRS0 bits of the UFnCTL1 register = 001B (fUCLK = fCLK/2 = 12 MHz)
Setting values of the UFnBRS11 to UFnBRS00 bits of the UFnCTL1 register = 000000100111B (k = 39)
Target baud rate = 153,600 bps
Baud rate = 12,000,000/(2 39)
= 153,846 [bps]
Error = (153,846/153,600 1) 100
= 0.160 [%]
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(5) Baud rate setting example
Table 13-5. Baud Rate Generator Setting Data
(Normal Operation, fCLK = 24 MHz, UFnPRS2 to UFnPRS0 = 0 to 3)
Target Baud
Rate (bps)
UFnPRS2 to UFnPRS0
0
1
2
3
UFnBRS11 to
UFnBRS00
ERR
(%)
UFnBRS11 to
UFnBRS00
ERR
(%)
UFnBRS11 to
UFnBRS00
ERR
(%)
UFnBRS11 to
UFnBRS00
ERR
(%)
300
600
2500
0.00
1200
2500
0.00
1250
0.00
2400
2500
0.00
1250
0.00
625
0.00
4800
2500
0.00
1250
0.00
625
0.00
313
0.16
9600
1250
0.00
625
0.00
313
0.16
156
0.16
19200
625
0.00
313
0.16
156
0.16
78
0.16
31250
384
0.00
192
0.00
96
0.00
48
0.00
38400
313
0.16
156
0.16
78
0.16
39
0.16
2.34
76800
156
0.16
78
0.16
39
0.16
20
128000
94
0.27
47
0.27
23
1.90
12
2.34
153600
78
0.16
39
0.16
20
2.34
10
2.34
312500
38
1.05
19
1.05
10
4.00
5
4.00
1000000
12
0.00
6
0.00
Table 13-6. Baud Rate Generator Setting Data
(Normal Operation, fCLK = 24 MHz, UFnPRS2 to UFnPRS0 = 4 to 7)
Target Baud
Rate (bps)
UFnPRS2 to UFnPRS0
4
UFnBRS11 to
UFnBRS00
300
5
ERR
(%)
UFnBRS11 to
UFnBRS00
2500
0.00
600
1250
1200
6
ERR
(%)
UFnBRS11 to
UFnBRS00
1250
0.00
0.00
625
625
0.00
2400
313
4800
7
ERR
(%)
UFnBRS11 to
UFnBRS00
ERR
(%)
625
0.00
313
0.16
0.00
384
0.16
156
0.16
384
0.16
313
0.16
78
0.16
0.16
313
0.16
156
0.16
625
0.16
156
0.16
156
0.16
94
0.16
313
2.34
9600
78
0.16
94
0.16
78
2.34
156
2.34
19200
39
0.16
78
2.34
156
2.34
78
2.34
31250
24
0.00
192
0.00
96
0.00
38400
20
2.34
156
2.34
78
2.34
76800
10
2.34
78
2.34
128000
6
2.34
153600
5
2.34
312500
1000000
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Table 13-7. Baud Rate Generator Setting Data
(Normal Operation, fCLK = 12 MHz, UFnPRS2 to UFnPRS0 = 0 to 3)
Target Baud
Rate (bps)
UFnPRS2 to UFnPRS0
0
1
2
3
UFnBRS11 to
UFnBRS00
ERR
(%)
UFnBRS11 to
UFnBRS00
ERR
(%)
UFnBRS11 to
UFnBRS00
ERR
(%)
UFnBRS11 to
UFnBRS00
ERR
(%)
300
2500
0.00
600
2500
0.00
1250
0.00
1200
2500
0.00
1250
0.00
625
0.00
2400
2500
0.00
1250
0.00
625
0.00
313
0.16
4800
1250
0.00
625
0.00
313
0.16
156
0.16
9600
625
0.00
313
0.16
156
0.16
78
0.16
19200
313
0.16
156
0.16
78
0.16
39
0.16
31250
192
0.00
96
0.00
48
0.00
24
0.00
38400
156
0.16
78
0.16
39
0.16
20
2.34
76800
78
0.16
39
0.16
20
2.34
10
2.34
128000
47
0.27
23
1.90
12
2.34
6
2.34
153600
39
0.16
20
2.34
10
2.34
5
2.34
312500
19
1.05
10
4.00
5
4.00
1000000
6
0.00
Table 13-8. Baud Rate Generator Setting Data
(Normal Operation, fCLK = 12 MHz, UFnPRS2 to UFnPRS0 = 4 to 7)
Target Baud
Rate (bps)
UFnPRS2 to UFnPRS0
4
UFnBRS11 to
UFnBRS00
300
5
ERR
(%)
UFnBRS11 to
UFnBRS00
1250
0.00
600
625
1200
6
ERR
(%)
UFnBRS11 to
UFnBRS00
625
0.00
0.00
313
313
0.16
2400
156
4800
7
ERR
(%)
UFnBRS11 to
UFnBRS00
ERR
(%)
313
0.16
156
0.16
0.16
156
0.16
78
0.16
156
0.16
78
0.16
39
0.16
0.16
78
0.16
39
0.16
20
2.34
78
0.16
39
0.16
20
2.34
10
2.34
9600
39
0.16
20
2.34
10
2.34
5
2.34
19200
20
2.34
10
2.34
5
2.34
31250
12
0.00
6
0.00
38400
10
2.34
5
2.34
76800
5
2.34
128000
153600
312500
1000000
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(6) Allowable baud rate range during reception
The baud rate error range at the destination that is allowable during reception is shown below.
Caution
The baud rate error during reception must be set within the allowable error range using the
following equation.
Figure 13-74. Allowable Baud Rate Range During Reception
Latch timing
LIN-UARTn
transfer rate
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FL
1 data frame (11 ´ FL)
Minimum
allowable
transfer rate
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmin
Maximum
allowable
transfer rate
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmax
In the figure above, the bits from the start bit to the stop bit is 11 bits long.
As shown in Figure 13-74, the receive data latch timing is determined by the counter set using the UFnCTL1
register following start bit detection. The transmit data can be normally received if up to the last data (stop bit) can
be received in time for this latch timing.
When this is applied to 11-bit reception while the data bit length is 8 bits, the following is the theoretical result.
FL = (Brate)1
Brate: LIN-UARTn baud rate
k:
Setting value of UFnCTL1
FL:
1-bit data length
Latch timing margin: 2 clocks
Minimum allowable transfer rate: FLmin = 11 FL
k2
2k
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FL
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CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
Therefore, the maximum baud rate that can be received by the destination is as follows.
22k
BRmax = (FLmin/11)1 =
Brate
21k + 2
Similarly, obtaining the following maximum allowable transfer rate yields the following.
10
k+2
FLmax = 11 FL
2k
11
FLmax =
21k 2
FL =
21k 2
2k
FL
FL 11
20 k
Therefore, the minimum baud rate that can be received by the destination is as follows.
BRmin = (FLmax/11)1 =
20k
21k 2
Brate
Table 13-9 shows the allowable baud rate error between LIN-UARTn and the transmission source calculated from the
above-described equations for obtaining the minimum and maximum baud rate values.
Table 13-9. Maximum/Minimum Allowable Baud Rate Error
Division Ratio (k)
Maximum Allowable Baud Rate Error
Minimum Allowable Baud Rate Error
BN = 9
BN = 11
BN = 12
BN = 9
BN = 11
BN = 12
4
+2.85%
+2.32%
+2.12%
3.03%
2.43%
2.22%
8
+4.34%
+3.52%
+3.22%
4.47%
3.61%
3.29%
16
+5.10%
+4.14%
+3.78%
5.18%
4.19%
3.82%
64
+5.68%
+4.60%
+4.20%
5.70%
4.61%
4.21%
128
+5.78%
+4.68%
+4.27%
5.79%
4.69%
4.28%
256
+5.83%
+4.72%
+4.31%
5.83%
4.72%
4.31%
512
+5.85%
+4.74%
+4.33%
5.86%
4.74%
4.33%
1024
+5.87%
+4.75%
+4.33%
5.87%
4.75%
4.33%
2048
+5.87%
+4.75%
+4.34%
5.87%
4.75%
4.34%
4095
+3.42%
+4.75%
+4.34%
3.59%
4.75%
4.34%
Remarks 1. The reception accuracy depends on the bit count in 1 frame, the input clock frequency, and the division
ratio (k). The higher the input clock frequency and the larger the division ratio (k), the higher the accuracy.
2. BN: Number of bits from the start bit to the stop bit
K:
Setting values of UFnCTL1.UFnBRS[11:0]
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13.11 Cautions for Use
(1) Execute a STOP instruction during a LIN-UART operation after stopping LIN-UART.
(2) Start up the LIN-UARTn in the following sequence.
Set the ports.
Set PER0.LINnEN to 1.
Set UFnCTL0.UFnTXE to 1, and UFnCTL0.UFnRXE to 1.
(3) Stop the LIN-UARTn in the following sequence.
Set UFnCTL0.UFnTXE to 0, and UFnCTL0.UFnRXE to 0.
Set PER1.LINnEN to 0.
Set the ports. (It is not a problem if port setting is not changed.)
(4) In transmit mode (UFnCTL0.UFnTXE = 1), do not overwrite the same value to the UF0TX register by
software because transmission starts by writing to this register. To transmit the same value continuously,
overwrite the same value.
Remark n = 0, 1
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CHAPTER 14 CAN CONTROLLER
CHAPTER 14 CAN CONTROLLER
R5F10CGx
aFCAN
0 channel
R5F10DGx
1 channel
R5F10CLx
0 channel
R5F10DLx
1 channel
R5F10CMx
0 channel
R5F10DMx
1 channel
R5F10TPJ/
R5F10DPJ/K/L
R5F10DPE/F/G
E5F10DSx
1 channel
2 channels
14.1 Outline Description
This product features an on-chip CAN (Controller Area Network) controller that complies with CAN protocol as
standardized in ISO 11898.
14.1.1 Features
- Compliant with ISO 11898 and tested according to ISO/DIS 16845 (CAN conformance test)
- Standard frame and extended frame transmission/reception enabled
- Transfer rate: 1 Mbps max. (CAN input clock 8 MHz)
- 16 message buffers/1 channel
- Receive/transmit history list function
- Automatic block transmission function
- Multi-buffer receive block function
- Mask setting of four patterns is possible for each channel
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CHAPTER 14 CAN CONTROLLER
14.1.2 Overview of functions
Table 14-1 presents an overview of the CAN controller functions.
Table 14-1. Overview of Functions
Function
Details
Protocol
CAN protocol ISO 11898 (standard and extended frame transmission/reception)
Baud rate
Maximum 1 Mbps (CAN clock input 8 MHz)
Data storage
Storing messages in the CAN RAM
Number of messages
- 16 message buffers/1 channel
- Each message buffer can be set to be either a transmit message buffer or a receive
message buffer.
Message reception
- Unique ID can be set to each message buffer.
- Mask setting of four patterns is possible for each channel.
- A receive completion interrupt is generated each time a message is received and stored in
a message buffer.
- Two or more receive message buffers can be used as a FIFO receive buffer (multi-buffer
receive block function).
- Receive history list function
Message transmission
- Unique ID can be set to each message buffer.
- Transmit completion interrupt for each message buffer
- Message buffer number 0 to 7 specified as the transmit message buffer can be used for
automatic block transfer. Message transmission interval is programmable (automatic
block transmission function (hereafter referred to as “ABT”)).
- Transmission history list function
Remote frame processing
Remote frame processing by transmit message buffer
Time stamp function
- The time stamp function can be set for a message reception when a 16-bit timer is used in
combination.
Time stamp capture trigger can be selected (SOF or EOF in a CAN message frame can
be detected.).
Diagnostic function
- Readable error counters
- “Valid protocol operation flag” for verification of bus connections
- Receive-only mode
- Single-shot mode
- CAN protocol error type decoding
- Self-test mode
Release from bus-off state
- Forced release from bus-off (by ignoring timing constraint) possible by software.
- No automatic release from bus-off (software must re-enable).
Power save mode
- CAN sleep mode (can be woken up by CAN bus)
- CAN stop mode (cannot be woken up by CAN bus)
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CHAPTER 14 CAN CONTROLLER
14.1.3 Configuration
The CAN controller is composed of the following four blocks.
(1) Interface
This functional block provides an internal bus interface and means of transmitting and receiving signals between
the CAN module and the host CPU.
(2) MCM (Memory Control Module)
This functional block controls access to the CAN protocol layer and to the CAN RAM within the CAN module.
(3) CAN protocol layer
This functional block is involved in the operation of the CAN protocol and its related settings.
(4) CAN RAM
This is the CAN memory functional block, which is used to store message IDs, message data, etc.
Figure 14-1. Block Diagram of CAN Module n
CPU
Interrupt request
Internal Bus
INTCnTRX
INTCnREC
INTCnERR
INTCnWUP
CAN bus
CAN module n
Interface
MCM
(Memory Control Module)
CAN
Protocol
Layer
CTxDn
CRxDn
CAN
transceiver
CAN_H
CAN_L
CAN RAM
CMASK1
CMASK2
CMASK3
CMASK4
...
Message
buffer 0
Message
buffer 1
Message
buffer 2
Message
buffer 3
Message
buffer 15
(n = 0, 1)
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CHAPTER 14 CAN CONTROLLER
14.2 CAN Protocol
CAN (Controller Area Network) is a high-speed multiplex communication protocol for real-time communication in
automotive applications (class C). CAN is prescribed by ISO 11898. For details, refer to the ISO 11898 specifications.
The CAN specification is generally divided into two layers: a physical layer and a data link layer. In turn, the data link
layer includes logical link and medium access control. The composition of these layers is illustrated below.
Figure 14-2. Composition of Layers
· Logical link control (LLC)
Higher
Data link
layerNote
Lower
· Medium access control (MAC)
Physical layer
· Acceptance filtering
· Overload report
· Recovery management
· Data capsuled/not capsuled
· Frame coding (stuffing/not stuffing)
· Medium access management
· Error detection
· Error report
· Acknowledgement
· Seriated/not seriated
Prescription of signal level and bit description
Note CAN controller specification
14.2.1 Frame format
(1) Standard format frame
- The standard format frame uses 11-bit identifiers, which means that it can handle up to 2048 messages.
(2) Extended format frame
- The extended format frame uses 29-bit (11 bits + 18 bits) identifiers which increase the number of messages
that can be handled to 2048 x 218 messages.
- Extended format frame is set when “recessive level” (CMOS level equals “1”) is set for both the SRR and IDE
bits in the arbitration field.
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CHAPTER 14 CAN CONTROLLER
14.2.2 Frame types
The following four types of frames are used in the CAN protocol.
Table 14-2. Frame Types
Frame Type
Description
Data frame
Frame used to transmit data
Remote frame
Frame used to request a data frame
Error frame
Frame used to report error detection
Overload frame
Frame used to delay the next data frame or remote frame
(1) Bus value
The bus values are divided into dominant and recessive.
- Dominant level is indicated by logical 0.
- Recessive level is indicated by logical 1.
- When a dominant level and a recessive level are transmitted simultaneously, the bus value becomes dominant
level.
14.2.3 Data frame and remote frame
(1) Data frame
A data frame is composed of seven fields.
Figure 14-3. Data Frame
Data frame
R
D
Interframe space
End of frame (EOF)
ACK field
CRC field
Data field
Control field
Arbitration field
Start of frame (SOF)
Remark
D: Dominant = 0
R: Recessive = 1
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(2) Remote frame
A remote frame is composed of six fields.
Figure 14-4. Remote Frame
Remote frame
R
D
Interframe space
End of frame (EOF)
ACK field
CRC field
Control field
Arbitration field
Start of frame (SOF)
Remarks 1. The data field is not transferred even if the control field’s data length code is not “0000B”.
2. D: Dominant = 0
R: Recessive = 1
(3) Description of fields
Start of frame (SOF)
The start of frame field is located at the start of a data frame or remote frame.
Figure 14-5. Start of Frame (SOF)
(Interframe space or bus idle)
Start of frame
(Arbitration field)
R
D
1 bit
Remark
D: Dominant = 0
R: Recessive = 1
If dominant level is detected in the bus idle state, a hard-synchronization is performed (the current TQ is
assigned to be the SYNC segment).
If dominant level is sampled at the sample point following such a hard-synchronization, the bit is assigned
to be a SOF. If recessive level is detected, the protocol layer returns to the bus idle state and regards the
preceding dominant pulse as a disturbance only. No error frame is generated in such case.
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Arbitration field
The arbitration field is used to set the priority, data frame/remote frame, and frame format.
Figure 14-6. Arbitration Field (in Standard Format Mode)
Arbitration field
(Control field)
R
D
Identifier
RTR
ID28 · · · · · · · · · · · · · · · · · · · · ID18
(11 bits)
(1 bit)
IDE
(r1)
r0
(1 bit)
Cautions 1. ID28 to ID18 are identifiers.
2. An identifier is transmitted MSB first.
Remark D: Dominant = 0
R: Recessive = 1
Figure 14-7. Arbitration Field (in Extended Format Mode)
Arbitration field
(Control field)
R
D
Identifier
SRR
IDE
Identifier
RTR
r1
r0
ID28 · · · · · · · · · · · · · · ID18
ID17 · · · · · · · · · · · · · · · · · ID0
(11 bits)
(1 bit) (1 bit)
(18 bits)
(1 bit)
Cautions 1. ID28 to ID18 are identifiers.
2. An identifier is transmitted MSB first.
Remark D: Dominant = 0
R: Recessive = 1
Table 14-3. RTR Frame Settings
Frame Type
RTR Bit
Data frame
0 (D)
Remote frame
1 (R)
Table 14-4. Frame Format Setting (IDE Bit) and Number of Identifier (ID) Bits
Frame Format
SRR Bit
IDE Bit
Number. of Bits
Standard format mode
None
0 (D)
11 bits
Extended format mode
1 (R)
1 (R)
29 bits
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Control field
The control field sets “DLC” as the number of data bytes in the data field (DLC = 0 to 8).
Figure 14-8. Control Field
(Arbitration field)
Control field
(Data field)
R
D
RTR
Remark
r1
(IDE)
r0
DLC3 DLC2
DLC1
DLC0
D: Dominant = 0
R: Recessive = 1
In a standard format frame, the control field’s IDE bit is the same as the r1 bit.
Table 14-5. Data Length Setting
Data Length Code
Data Byte Count
DLC3
DLC2
DLC1
DLC0
0
0
0
0
0 byte
0
0
0
1
1 byte
0
0
1
0
2 bytes
0
0
1
1
3 bytes
0
1
0
0
4 bytes
0
1
0
1
5 bytes
0
1
1
0
6 bytes
0
1
1
1
7 bytes
1
0
0
0
8 bytes
Other than the above
8 bytes regardless of the
value of DLC3 to DLC0
Caution
In the remote frame, there is no data field even if the
data length code is not 0000B.
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Data field
The data field contains the amount of data (byte units) set by the control field. Up to 8 units of data can be
set.
Figure 14-9. Data Field
(Control field)
Data field
(CRC field)
R
D
MSB
Remark
Data0
(8 bits)
→
MSB
LSB
Data7
(8 bits)
→
LSB
D: Dominant = 0
R: Recessive = 1
CRC field
The CRC field is a 16-bit field that is used to check for errors in transmit data.
Figure 14-10. CRC Field
(Data field or control field)
CRC field
(ACK field)
R
D
CRC sequence
(15 bits)
Remark
CRC delimiter
(1 bit)
D: Dominant = 0
R: Recessive = 1
- The polynomial P(X) used to generate the 15-bit CRC sequence is expressed as follows.
P(X) = X15 + X14 + X10 + X8 + X7 + X4 + X3 + 1
- Transmitting node: Transmits the CRC sequence calculated from the data (before bit stuffing) in the start
of frame, arbitration field, control field, and data field.
- Receiving node:
Compares the CRC sequence calculated using data bits that exclude the stuffing bits
in the receive data with the CRC sequence in the CRC field. If the two CRC
sequences do not match, the node issues an error frame.
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ACK field
The ACK field is used to acknowledge normal reception.
Figure 14-11. ACK Field
(CRC field)
ACK field
(End of frame)
R
D
ACK slot
(1 bit)
Remark
ACK delimiter
(1 bit)
D: Dominant = 0
R: Recessive = 1
- If no CRC error is detected, the receiving node sets the ACK slot to the dominant level.
- The transmitting node outputs two recessive-level bits.
End of frame (EOF)
The end of frame field indicates the end of data frame/remote frame.
Figure 14-12. End of Frame (EOF)
(ACK field)
End of frame
(Interframe space or overload frame)
R
D
(7 bits)
Remark
D: Dominant = 0
R: Recessive = 1
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Interframe space
The interframe space is inserted after a data frame, remote frame, error frame, or overload frame to separate
one frame from the next.
- The bus state differs depending on the error status.
(a) Error active node
The interframe space consists of a 3-bit intermission field and a bus idle field.
Figure 14-13. Interframe Space (Error Active Node)
(Frame)
Interframe space
(Frame)
R
D
Intermission
(3 bits)
Bus idle
(0 to ∞ bits)
Remarks 1. Bus idle: State in which the bus is not used by any node.
2. D: Dominant = 0
R: Recessive = 1
(b) Error passive node
The interframe space consists of an intermission field, a suspend transmission field, and a bus idle field.
Figure 14-14. Interframe Space (Error Passive Node)
(Frame)
R
D
(Frame)
Interframe space
Intermission
(3 bits)
Remarks 1. Bus idle:
Suspend transmission
(8 bits)
Bus idle
(0 to ∞ bits)
State in which the bus is not used by any node.
Suspend transmission: Sequence of 8 recessive-level bits transmitted from the node in
the error passive status.
2. D: Dominant = 0
R: Recessive = 1
Usually, the intermission field is 3 bits. If the transmitting node detects a dominant level at the third bit of the
intermission field, however, it executes transmission.
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- Operation in error status
Table 14-6. Operation in Error Status
Error Status
Operation
Error active
A node in this status can transmit immediately after a 3-bit intermission.
Error passive
A node in this status can transmit 8 bits after the intermission.
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14.2.4 Error frame
An error frame is output by a node that has detected an error.
Figure 14-15. Error Frame
Error frame
R
D
()
6 bits
1 to 6 bits
8 bits
()
Interframe space or overload frame
Error delimiter
Error flag2
Error flag1
Error bit
Remark
D: Dominant = 0
R: Recessive = 1
Table 14-7. Definition Error Frame Fields
No.
Name
Error flag1
Bit Count
6
Definition
Error active node: Outputs 6 dominant-level bits consecutively.
Error passive node: Outputs 6 recessive-level bits consecutively.
If another node outputs a dominant level while one node is outputting a
passive error flag, the passive error flag is not cleared until the same level
is detected 6 bits in a row.
Error flag2
0 to 6
Nodes receiving error flag 1 detect bit stuff errors and issues this error
flag.
Error delimiter
8
Outputs 8 recessive-level bits consecutively.
If a dominant level is detected at the 8th bit, an overload frame is
transmitted from the next bit.
Error bit
–
The bit at which the error was detected.
The error flag is output from the bit next to the error bit.
In the case of a CRC error, this bit is output following the ACK delimiter.
Interframe space/overload
–
An interframe space or overload frame starts from here.5
frame
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14.2.5 Overload frame
An overload frame is transmitted under the following conditions.
- When the receiving node has not completed the reception operationNote
- If a dominant level is detected at the first two bits during intermission
- If a dominant level is detected at the last bit (7th bit) of the end of frame or at the last bit (8th bit) of the error
delimiter/overload delimiter
Note The CAN is internally fast enough to process all received frames not generating overload frames.
Figure 14-16. Overload Frame
Overload frame
R
D
()
6 bits
0 to 6 bits
8 bits
()
Interframe space or overload frame
Overload delimiter
Overload flag
Overload flag
Frame
Remark
D: Dominant = 0
R: Recessive = 1
Table 14-8. Definition of Overload Frame Fields
No
Name
Overload flag
Overload flag from other node
Bit Count
6
0 to 6
Definition
Outputs 6 dominant-level bits consecutively.
The node that received an overload flag in the interframe
space outputs an overload flag.
Overload delimiter
8
Outputs 8 recessive-level bits consecutively.
If a dominant level is detected at the 8th bit, an overload frame
is transmitted from the next bit.
Frame
–
Output following an end of frame, error delimiter, or overload
delimiter.
Interframe space/overload
–
An interframe space or overload frame starts from here.
frame
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14.3 Functions
14.3.1 Determining bus priority
(1) When a node starts transmission:
- During bus idle, the node that output data first transmits the data.
(2) When more than one node starts transmission:
- The node that outputs the dominant level for the longest consecutively from the first bit of the arbitration field
acquires the bus priority (if a dominant level and a recessive level are simultaneously transmitted, the dominant
level is taken as the bus value).
- The transmitting node compares its output arbitration field and the data level on the bus.
Table 14-9. Determining Bus Priority
Level match
Continuous transmission
Level mismatch
Stops transmission at the bit where mismatch is detected and starts reception at the following bit
(3) Priority of data frame and remote frame
- When a data frame and a remote frame are on the bus, the data frame has priority because its RTR bit, the last
bit in the arbitration field, carries a dominant level.
Caution If the extended-format data frame and the standard-format remote frame conflict on the bus (if ID28
to ID18 of both of them are the same), the standard-format remote frames takes priority.
14.3.2 Bit stuffing
Bit stuffing is used to establish synchronization by appending 1-bit inverted data if the same level continues for 5 bits, in
order to prevent a burst error.
Table 14-10. Bit Stuffing
Transmission
During the transmission of a data frame or remote frame, when the same level continues for 5 bits in the data
between the start of frame and the ACK field, 1 inverted-level bit of data is inserted before the following bit.
Reception
During the reception of a data frame or remote frame, when the same level continues for 5 bits in the data
between the start of frame and the ACK field, reception is continued after deleting the next bit.
14.3.3 Multi masters
As the bus priority (a node acquiring transmit functions) is determined by the identifier, any node can be the bus master.
14.3.4 Multi cast
Although there is one transmitting node, two or more nodes can receive the same data at the same time because the
same identifier can be set to two or more nodes.
14.3.5 CAN sleep mode/CAN stop mode function
The CAN sleep mode/CAN stop mode function puts the CAN controller in waiting mode to achieve low power
consumption.
The controller is woken up from the CAN sleep mode by bus operation but it is not woken up from the CAN stop mode
by bus operation (the CAN stop mode is controlled by CPU access).
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14.3.6 Error control function
(1) Error types
Table 14-11. Error Types
Type
Description of Error
Detection Method
Bit error
Comparison of output level and
level on the bus
Detection State
Detection
Transmission/
Condition
Reception
Mismatch of levels
Transmitting/
receiving node
Field/Frame
Bit that outputting data on the
bus at the start of frame to end of
frame, error frame and overload
frame.
Stuff error
CRC error
Check the receive data at the
stuff bit
6 consecutive bits
Receiving node
Start of frame to CRC sequence
Comparison of the CRC
Mismatch of CRC
Receiving node
CRC field
Detection of fixed
format violation
Receiving node
CRC delimiter
of the same output
level
sequence generated from the
receive data and the received
CRC sequence
Form error
Field/frame check of the fixed
format
ACK field
End of frame
Error frame
Overload frame
ACK error
Check of the ACK slot by the
transmitting node
Detection of
Transmitting node
ACK slot
recessive level in
ACK slot
(2) Output timing of error frame
Table 14-12. Output Timing of Error Frame
Type
Bit error, stuff error,
Output Timing
Error frame output is started at the timing of the bit following the detected error.
form error, ACK error
CRC error
Error frame output is started at the timing of the bit following the ACK delimiter.
(3) Processing in case of error
The transmission node re-transmits the data frame or remote frame after the error frame (However, it does not retransmit the frame in the single-shot mode.).
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(4) Error state
(a) Types of error states
The following three types of error states are defined by the CAN specification.
- Error active
- Error passive
- Bus-off
These types of error states are classified by the values of the TEC7 to TEC0 bits (transmission error counter
bits) and the REC6 to REC0 bits (reception error counter bits) of the CAN error counter register (C0ERC,
C1ERC) as shown in Table 14-13.
The present error state is indicated by the CAN module information register (C0INFO, C1INFO).
When each error counter value becomes equal to or greater than the error warning level (96), the TECS0 or
RECS0 bit of the C0INFO, C1INFO register is set to 1. In this case, the bus state must be tested because it
is considered that the bus has a serious fault. An error counter value of 128 or more indicates an error
passive state and the TECS1 or RECS1 bit of the C0INFO, C1INFO register is set to 1.
- If the value of the transmission error counter is greater than or equal to 256 (actually, the transmission error
counter does not indicate a value greater than or equal to 256), the bus-off state is reached and the BOFF
bit of the C0INFO, C1INFO register is set to 1.
- If only one node is active on the bus at startup (i.e., a particular case such as when the bus is connected
only to the local station), ACK is not returned even if data is transmitted. Consequently, re-transmission of
the error frame and data is repeated. In the error passive state, however, the transmission error counter is
not incremented and the bus-off state is not reached.
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Table 14-13. Types of Error States
Type
Error active
Error passive
Operation
Value of Error
Counter
Indication of C0INFO,
C1INFO Register
Transmission
0-95
TECS1, TECS0 = 00
Reception
0-95
RECS1, RECS0 = 00
Transmission
96-127
TECS1, TECS0 = 01
Reception
96-127
RECS1, RECS0 = 01
Transmission
128-255
TECS1, TECS0 = 11
Reception
128 or more
RECS1, RECS0 = 11
Operation specific to Given Error State
- Outputs an active error flag (6 consecutive
dominant-level bits) on detection of the
error.
- Outputs a passive error flag (6 consecutive
recessive-level bits) on detection of the
error.
- Transmits 8 recessive-level bits, in
between transmissions, following an
intermission (suspend transmission).
Bus-off
Transmission
256 or more
BOFF = 1,
Note
(not indicated)
TECS1, TECS0 = 11
- Communication is not possible.
Messages are not stored when receiving
frames, however, the following operations
of , , and are done.
TSOUT toggles.
REC is incremented/decremented.
VALID bit is set.
- If the CAN module is entered to the
initialization mode and then transition
request to any operation mode is made,
and when 11 consecutive recessive-level
bits are detected 128 times, the error
counter is reset to 0 and the error active
state can be restored.
Note The value of the transmission error counter (TEC) is invalid when the BOFF bit is set to 1. If an error that
increments the value of the transmission error counter by +8 while the counter value is in a range of 248 to 255, the
counter is not incremented and the bus-off state is assumed.
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(b) Error counter
The error counter counts up when an error has occurred, and counts down upon successful transmission and
reception. The error counter is updated immediately after error detection.
Table 14-14. Error Counter
State
Transmission Error Counter
Reception Error Counter
(TEC7 to TEC0)
(REC6 to REC0)
Receiving node detects an error (except bit error in the active error flag
or overload flag).
No change
+1 (when REPS bit = 0)
Receiving node detects dominant level following error flag of error
frame.
No change
+8 (when REPS bit = 0)
Transmitting node transmits an error flag.
+8
No change
Bit error detection while active error flag or overload flag is being output
(error-active transmitting node)
+8
No change
Bit error detection while active error flag or overload flag is being output
(error-active receiving node)
No change
+8 (when REPS bit = 0)
When the node detects 14 consecutive dominant-level bits from the
+8 (during transmission)
+8 (during reception,
when REPS bit = 0)
When the transmitting node has completed transmission without error
(±0 if error counter = 0)
–1
No change
When the receiving node has completed reception without error
No change
- –1 (1 REC6 to REC0
[As exceptions, the error counter does not change in the following
cases.]
ACK error is detected in error passive state and dominant level is
not detected while the passive error flag is being output.
A stuff error is detected in an arbitration field that transmitted a
recessive level as a stuff bit, but a dominant level is detected.
beginning of the active error flag or overload flag, and then subsequently
detects 8 consecutive dominant-level bits. When the node detects 8
consecutive dominant levels after a passive error flag
127, when REPS bit =
0)
- ±0 (REC6 to REC0 = 0,
when REPS bit = 0)
- Value of 119 to 127 is
set (when REPS bit =
1)
(c) Occurrence of bit error in intermission
An overload frame is generated.
Caution If an error occurs, the error flag output (active or passive) is controlled according to the
contents of the transmission error counter and reception error counter before the error
occurred. The value of the error counter is incremented after the error flag has been output.
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(5) Recovery from bus-off state
When the CAN module is in the bus-off state, the CAN module permanently sets its output signals (CTxD) to
recessive level.
The CAN module recovers from the bus-off state in the following bus-off recovery sequence.
A request to enter the CAN initialization mode
A request to enter a CAN operation mode
(a) Recovery operation through normal recovery sequence
(b) Forced recovery operation that skips recovery sequence
(a) Recovery operation from bus-off state through normal recovery sequence
The CAN module first issues a request to enter the initialization mode (refer to timing in Figure 14-17).
This request will be immediately acknowledged, and the OPMODE bits of the C0CTRL, C1CTRL register are
cleared to 000B. Processing such as analyzing the fault that has caused the bus-off state, re-defining the
CAN module and message buffer using application software, or stopping the operation of the CAN module
can be performed by clearing the GOM bit to 0.
Next, the user requests to change the mode from the initialization mode to an operation mode (refer to timing
in Figure 14-17). This starts an operation to recover the CAN module from the bus-off state. The
conditions under which the module can recover from the bus-off state are defined by the CAN protocol ISO
11898, and it is necessary to detect 11 consecutive recessive-level bits 128 times. At this time, the request to
change the mode to an operation mode is held pending until the recovery conditions are satisfied. When the
recovery conditions are satisfied (refer to timing in Figure 14-17), the CAN module can enter the
operation mode it has requested. Until the CAN module enters this operation mode, it stays in the
initialization mode. Completion to be requested operation mode can be confirmed by reading the OPMODE
bits of the C0CTRL, C1CTRL register.
During the bus-off period and bus-off recovery sequence, the BOFF bit of the C0INFO, C1INFO register stays
set (to 1). In the bus-off recovery sequence, the reception error counter (REC[6:0]) counts the number of
times 11 consecutive recessive-level bits have been detected on the bus. Therefore, the recovery state can
be checked by reading REC[6:0].
Cautions 1. If the Bus-off Recovery Sequence is interrupted by entering Initialization Mode and reentering any Operation Mode, the Bus-off Recovery Sequence will restart from the
beginning, and the waiting phase will be again 128 times 11 recessive-level bits,
counted from this point.
2. In the bus-off recovery sequence, REC [6:0] counts up (+1) each time 11 consecutive
recessive-level bits have been detected. Even during the bus-off period, the CAN
module can enter the CAN sleep mode or CAN stop mode. To start the bus-off recovery
sequence, it is necessary to transit to the initialization mode once.
However, when the CAN module is in either CAN sleep mode or CAN stop mode,
transition request to the initialization mode is not accepted, thus you have to release
the CAN sleep mode first. In this case, as soon as the CAN sleep mode is released, the
bus-off recovery sequence starts and no transition to initialization mode is necessary.
If the CAN module detects a dominant edge on the CAN bus while in sleep mode even
during bus-off, the sleep mode will be left and the bus-off recovery sequence will start
(In the state that the CAN clock is supplied, it is necessary to clear the PSMODE by
software after dominant edge detection).
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Figure 14-17. Recovery Operation from Bus-off State through Normal Recovery Sequence
TEC > FFH
»bus-off«
»error-passive«
»bus-off-recovery-sequence«
»error-active«
BOFF bit
in C0INFO, C1INFO
register
OPMODE[2:0]
in C0CTRL, C1CTRL
register
(user writings)
OPMODE[2:0]
in C0CTRL, C1CTRL
register
(user readings)
≠ 00H
≠ 00H
00H
≠ 00H
TEC[7:0]
in C0ERC, C1ERC 80H ≤ TEC[7:0] ≤ FFH
register
REPS, REC[6:0]
in C0ERC, C1ERC
register
≠ 00H
00H
FFH < TEC [7:0]
80H ≤ REPS, REC[6:0] ≤ FFH
00H
Undefined
00H ≤ TEC[7:0] < 80H
00H ≤ REPS, REC[6:0] < 80H
(b) Forced recovery operation that skips bus-off recovery sequence
The CAN module can be forcibly released from the bus-off state, regardless of the bus state, by skipping the
bus-off recovery sequence. Here is the procedure.
First, the CAN module requests to enter the initialization mode. For the operation and points to be noted at
this time, refer to (a) Recovery operation from bus-off state through normal recovery sequence.
Next, the module requests to enter an operation mode. At the same time, the CCERC bit of the C0CTRL,
C1CTRL register must be set to 1.
As a result, the bus-off recovery sequence defined by the CAN protocol ISO 11898 is skipped, and the
module immediately enters the operation mode. In this case, the module is connected to the CAN bus after it
has monitored 11 consecutive recessive-level bits. For details, refer to the processing in Figure 14-82.
Caution This function is not defined by the CAN protocol ISO 11898. When using this function,
thoroughly evaluate its effect on the network system.
(6) Initializing CAN module error counter register (C0ERC, C1ERC) in initialization mode
If it is necessary to initialize the CAN module error counter register (C0ERC, C1ERC) and CAN module
information register (C0INFO, C1INFO) for debugging or evaluating a program, they can be initialized to the
default value by setting the CCERC bit of the C0CTRL, C1CTRL register in the initialization mode. When
initialization has been completed, the CCERC bit is automatically cleared to 0.
Cautions 1. This function is enabled only in the initialization mode. Even if the CCERC bit is set to 1 in
a CAN operation mode, the C0ERC, C1ERC and C0INFO, C1INFO registers are not
initialized.
2. The CCERC bit can be set at the same time as the request to enter a CAN operation mode.
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14.3.7 Baud rate control function
(1) Prescaler
The CAN controller has a prescaler that divides the clock (fCAN) supplied to CAN. This prescaler generates a CAN
protocol layer basic clock (fTQ) derived from the CAN module system clock (fCANMOD), and divided by 1 to 256
(refer to 14.6 (12) CAN Bit Rate Prescaler Register (C0BRP, C1BRP)).
(2) Data bit time (8-25 time quanta)
One data bit time is defined as shown in Figure 14-18.
The CAN controller sets time segment 1, time segment 2, and reSynchronization Jump Width (SJW) as the
parameter of data bit time, as shown in Figure 14-18. Time segment 1 is equivalent to the total of the
propagation (prop) segment and phase segment 1 that are defined by the CAN protocol specification. Time
segment 2 is equivalent to phase segment 2.
Figure 14-18. Segment Setting
Data bit time(DBT)
Sync segment
Prop segment
Phase segment 1
Time segment 1(TSEG1)
Phase segment 2
Time segment 2
(TSEG2)
Sample point (SPT)
Segment Name
Settable Range
Notes on Setting to Confirm to CAN Specification
Time Segment 1 (TSEG1)
2TQ-16TQ
—
Time Segment 2 (TSEG2)
1TQ-8TQ
IPT of the CAN controller is 0TQ. To conform to the CAN
protocol specification, therefore, a length less or equal to
phase segment 1 must be set here. This means that the
length of time segment 1 minus 1TQ is the settable upper
limit of time segment 2.
Resynchronization jump
1TQ-4TQ
width(SJW)
The length of time segment 1 minus 1TQ or 4 TQ,
whichever is smaller.
Remark IPT : Information Processing Time
TQ : Time Quanta
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Reference: The CAN standard ISO 11898 specification defines the segments constituting the data bit time as shown in
Figure 14-19.
Figure 14-19. Reference: Configuration of Data Bit Time Defined by CAN Specification
Data bit time(DBT)
Sync segment
Prop segment
Phase segment 1
Phase segment 2
SJW
Sample point (SPT)
Segment Name
Sync Segment
Segment Length
1
(Synchronization Segment)
Prop Segment
Description
This segment starts at the edge where the level changes
from recessive to dominant when hard-synchronization is
established.
Programmable to 1 to 8
This segment absorbs the delay of the output buffer, CAN
or more
bus, and input buffer.
The length of this segment is set so that ACK is returned
before the start of phase segment 1.
Time of prop segment (Delay of output buffer) + 2 x
(Delay of CAN bus) + (Delay of input buffer)
Phase Segment 1
Programmable to 1 to 8
Phase Segment 2
Phase Segment 1 or
IPT, whichever greater
SJW
Programmable from
1TQ to length of
This segment compensates for an error of data bit time.
The longer this segment, the wider the permissible range
but the slower the communication speed.
This width sets the upper limit of expansion or contraction
of the phase segment during resynchronization.
segment 1 or 4TQ,
whichever is smaller
Remark IPT : Information Processing Time
TQ : Time Quanta
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(3) Synchronizing data bit
- The receiving node establishes synchronization by a level change on the bus because it does not have a sync
signal.
- The transmitting node transmits data in synchronization with the bit timing of the transmitting node.
(a) Hard-synchronization
This synchronization is established when the receiving node detects the start of frame in the interframe space.
- When a falling edge is detected on the bus, that TQ means the sync segment and the next segment is the
prop segment. In this case, synchronization is established regardless of SJW.
Figure 14-20. Hard-synchronization at Recognition of Dominant Level during Bus Idle
Interframe space
Start of frame
CANbus
Bit timing
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Prop
segment
Phase
segment 1
Phase
segment 2
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CHAPTER 14 CAN CONTROLLER
(b) Resynchronization
Synchronization is established again if a level change is detected on the bus during reception (only if a
recessive level was sampled previously).
- The phase error of the edge is given by the relative position of the detected edge and sync segment.
0: If the edge is within the sync segment
Positive: If the edge is before the sample point (phase error)
Negative: If the edge is after the sample point (phase error)
If phase error is positive: Phase segment 1 is longer by specified SJW.
If phase error is negative: Phase segment 2 is shorter by specified SJW.
- The sample point of the data of the receiving node moves relatively due to the “discrepancy” in baud rate
between the transmitting node and receiving node.
Figure 14-21. Resynchronization
If phase error is positve
CAN bus
Bit timing
Sync
segment
Prop
segment
Phase
segment 2
Phase segment 1
Sample point
If phase error is negative
CAN bus
Bit timing
Sync
segment
Prop
segment
Phase segment 1
Phase
segment 2
Sample point
Data bit time(DBT)
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14.4 Connection with Target System
The microcontroller incorporated a CAN has to be connected to the CAN bus using an external transceiver.
Figure 14-22. Connection to CAN Bus
Microcontroller
incorporated
a CAN
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CRxD
CAN_L
Transceiver
CAN_H
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CHAPTER 14 CAN CONTROLLER
14.5 Internal Registers of CAN Controller
14.5.1 CAN controller configuration
Table 14-15. List of CAN Controller Registers (1/2)
Item
Control registers
Register Name
Peripheral clock select register (PCKSEL)
Serial communication pin select register 1 (STSEL1)
Port register 0, 6, 7, 13 (P0, P6, P7, P13)
Port mode register 0, 6, 7, 13 (PM0, PM6, PM7, PM13)
CAN global registers
CAN global module control register (C0GMCTRL, C1GMCTRL)
CAN global module clock select register (C0GMCS, C1GMCS)
CAN global automatic block transmission control register
(C0GMABT, C1GMABT)
CAN global automatic block transmission delay setting register
(C0GMABTD, C1GMABTD)
CAN module registers
CAN module mask 1 register L (C0MASK1L, C1MASK1L)
CAN module mask 1 register H (C0MASK1H, C1MASK1H)
CAN module mask 2 register L (C0MASK2L, C1MASK2L)
CAN module mask 2 register H (C0MASK2H, C1MASK2H)
CAN module mask 3 register L (C0MASK3L, C1MASK3L)
CAN module mask 3 register H (C0MASK3H, C1MASK3H)
CAN module mask 4 register L (C0MASK4L, C1MASK4L)
CAN module mask 4 register H (C0MASK4H, C1MASK4H)
CAN module control register (C0CTRL, C1CTRL)
CAN module last error code register (C0LEC, C1LEC)
CAN module information register (C0INFO, C1INFO)
CAN module error counter register (C0ERC, C1ERC)
CAN module interrupt enable register (C0IE, C1IE)
CAN module interrupt status register (C0INTS, C1INTS)
CAN module bit rate prescaler register (C0BRP, C1BRP)
CAN module bit rate register (C0BTR, C1BTR)
CAN module last in-pointer register (C0LIPT, C1LIPT)
CAN module receive history list register (C0RGPT, C1RGPT)
CAN module last out-pointer register (C0LOPT, C1LOPT)
CAN module transmit history list register (C0TGPT, C1TGPT)
CAN module time stamp register (C0TS, C1TS)
Remark
CAN global registers are identified by CGM.
CAN module registers are identified by C.
Message buffer registers are identified by CM.
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Table 14-15. List of CAN Controller Registers (2/2)
Item
Register Name
Message buffer registers
CAN message data byte 01 register m (C0MDB01m, C1MDB01m)
CAN message data byte 0 register m (C0MDB0m, C1MDB0m)
CAN message data byte 1 register m (C0MDB1m, C1MDB1m)
CAN message data byte 23 register m (C0MDB23m, C1MDB23m)
CAN message data byte 2 register m (C0MDB2m, C1MDB2m)
CAN message data byte 3 Register m (C0MDB3m, C1MDB3m)
CAN message data byte 45 Register m (C0MDB45m, C1MDB45m)
CAN message data byte 4 Register m (C0MDB4m, C1MDB4m)
CAN message data byte 5 Register m (C0MDB5m, C1MDB5m)
CAN message data byte 67 Register m (C0MDB67m, C1MDB67m)
CAN message data byte 6 register m (C0MDB6m, C1MDB6m)
CAN message data byte 7 register m (C0MDB7m, C1MDB7m)
CAN message data length register m (C0MDLCm, C1MDLCm)
CAN message configuration register m (C0MCONFm, C1MCONFm)
CAN message ID register L m (C0MIDLm, C1MIDLm)
CAN message ID register H m (C0MIDHm, C1MIDHm)
CAN message control register m (C0MCTRLm, C1MCTRLm)
Remarks 1. CAN global registers are identified by CGM.
CAN module registers are identified by C.
Message buffer registers are identified by CM.
2. m = 0 to 15
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14.5.2 Register access type
The peripheral I/O register for the CAN controller is assigned to 000F05C0H to 000F06FFH. For details, refer to 3.2.5
Extended special function registers (2nd SFRs: 2nd Special Function Registers).
Table 14-16. Register Access Types (1/18)
Address
Register Name
Symbol
R/W
Bit Manipulation Units
Default Value
1
8
16
0000H
000F05C0H
CAN0 global module control register
C0GMCTRL
000F05C6H
CAN0 global automatic block transmission
control register
C0GMABT
0000H
000F05C8H
CAN0 global automatic block transmission
delay setting register
C0GMABTD
00H
000F05CEH
CAN0 global module clock select register
C0GMCS
0FH
000F05D0H
CAN0 module mask 1 register
C0MASK1L
Undefined
000F05D2H
000F05D4H
C0MASK1H
CAN0 module mask 2 register
C0MASK2L
CAN0 module mask 3 register
C0MASK3L
000F05D6H
000F05D8H
Undefined
C0MASK2H
000F05DAH
000F05DCH
R/W
Undefined
C0MASK3H
CAN0 module mask 4 register
000F05DEH
Undefined
Undefined
Undefined
C0MASK4L
C0MASK4H
Undefined
Undefined
000F05E0H
CAN0 module control register
C0CTRL
0000H
000F05E2H
CAN0 module last error code register
C0LEC
00H
000F05E3H
CAN0 module information register
C0INFO
00H
000F05E4H
CAN0 module error counter register
C0ERC
0000H
000F05E6H
CAN0 module interrupt enable register
C0IE
0000H
000F05E8H
CAN0 module interrupt status register
C0INTS
0000H
000F05EAH
CAN0 module bit rate prescaler register
C0BRP
FFH
370FH
R
R/W
000F05ECH CAN0 module bit rate register
C0BTR
000F05EEH
CAN0 module last in-pointer register
C0LIPT
R
000F05F0H
CAN0 module receive history list register
C0RGPT
R/W
xx02H
000F05F2H
CAN0 module last out-pointer register
C0LOPT
R
Undefined
000F05F4H
CAN0 module transmit history list register
C0TGPT
R/W
xx02H
000F05F6H
CAN0 module time stamp register
C0TS
0000H
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CHAPTER 14 CAN CONTROLLER
Table 14-16. Register Access Types (2/18)
Address
000F0600H
Register Name
CAN0 message data byte 01 register 00
Symbol
C0MDB0100
R/W
R/W
Bit Manipulation Units
Default Value
1
8
16
–
–
Undefined
000F0600H CAN0 message data byte 0 register 00
C0MDB000
–
–
Undefined
000F0601H CAN0 message data byte 1 register 00
C0MDB100
–
–
Undefined
C0MDB2300
–
–
Undefined
000F0602H CAN0 message data byte 2 register 00
C0MDB200
–
–
Undefined
000F0603H CAN0 message data byte 3 register 00
C0MDB300
–
–
Undefined
C0MDB4500
–
–
Undefined
000F0604H CAN0 message data byte 4 register 00
C0MDB400
–
–
Undefined
000F0605H CAN0 message data byte 5 register 00
C0MDB500
–
–
Undefined
C0MDB6700
–
–
Undefined
C0MDB600
–
–
Undefined
000F0602H
000F0604H
000F0606H
CAN0 message data byte 23 register 00
CAN0 message data byte 45 register 00
CAN0 message data byte 67 register 00
000F0606H CAN0 message data byte 6 register 00
C0MDB700
–
–
Undefined
000F0608H
CAN0 message data length register 00
C0MDLC00
–
–
0000xxxxB
000F0609H
CAN0 message configuration register 00
C0MCONF00
–
–
Undefined
000F060AH
CAN0 message ID register 00
C0MIDL00
–
–
Undefined
C0MIDH00
–
–
Undefined
00x00000
000xx000B
000F0607H CAN0 message data byte 7 register 00
000F060CH
000F060EH
CAN0 message control register 00
C0MCTRL00
–
–
000F0610H
CAN0 message data byte 01 register 01
C0MDB0101
–
–
Undefined
000F0610H
CAN0 message data byte 0 register 01
C0MDB001
–
–
Undefined
000F0611H
CAN0 message data byte 1 register 01
C0MDB101
–
–
Undefined
000F0612H
CAN0 message data byte 23 register 01
C0MDB2301
–
–
Undefined
000F0612H
CAN0 message data byte 2 register 01
C0MDB201
–
–
Undefined
000F0613H
CAN0 message data byte 3 register 01
C0MDB301
–
–
Undefined
000F0614H
CAN0 message data byte 45 register 01
C0MDB4501
–
–
Undefined
000F0614H
CAN0 message data byte 4 register 01
C0MDB401
–
–
Undefined
000F0615H
CAN0 message data byte 5 register 01
C0MDB501
–
–
Undefined
000F0616H
CAN0 message data byte 67 register 01
C0MDB6701
–
–
Undefined
000F0616H
CAN0 message data byte 6 register 01
C0MDB601
–
–
Undefined
000F0617H
CAN0 message data byte 7 register 01
C0MDB701
–
–
Undefined
000F0618H
CAN0 message data length register 01
C0MDLC01
–
–
0000xxxxB
000F0619H
CAN0 message configuration register 01
C0MCONF01
–
–
Undefined
000F061AH
CAN0 message ID register 01
C0MIDL01
–
–
Undefined
C0MIDH01
–
–
Undefined
CAN0 message control register 01
C0MCTRL01
–
–
00x00000
000xx000B
000F061CH
000F061EH
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Table 14-16. Register Access Types (3/18)
Address
000F0620H
Register Name
CAN0 message data byte 01 register 02
Symbol
C0MDB0102
R/W
R/W
Bit Manipulation Units
Default Value
1
8
16
–
–
Undefined
000F0620H CAN0 message data byte 0 register 02
C0MDB002
–
–
Undefined
000F0621H CAN0 message data byte 1 register 02
C0MDB102
–
–
Undefined
C0MDB2302
–
–
Undefined
000F0622H CAN0 message data byte 2 register 02
C0MDB202
–
–
Undefined
000F0623H CAN0 message data byte 3 register 02
C0MDB302
–
–
Undefined
C0MDB4502
–
–
Undefined
000F0624H CAN0 message data byte 4 register 02
C0MDB402
–
–
Undefined
000F625H
CAN0 message data byte 5 register 02
C0MDB502
–
–
Undefined
CAN0 message data byte 67 register 02
C0MDB6702
–
–
Undefined
C0MDB602
–
–
Undefined
000F0622H
000F0624H
000F0626H
CAN0 message data byte 23 register 02
CAN0 message data byte 45 register 02
000F0626H CAN0 message data byte 6 register 02
C0MDB702
–
–
Undefined
000F0628H
CAN0 message data length register 02
C0MDLC02
–
–
0000xxxxB
000F0629H
CAN0 message configuration register 02
C0MCONF02
–
–
Undefined
000F062AH
CAN0 message ID register 02
C0MIDL02
–
–
Undefined
C0MIDH02
–
–
Undefined
000F0627H CAN0 message data byte 7 register 02
000F062CH
000F062EH
CAN0 message control register 02
C0MCTRL02
–
–
00x00000
000xx000B
000F0630H
CAN0 message data byte 01 register 03
C0MDB0103
–
–
Undefined
000F0630H CAN0 message data byte 0 register 03
C0MDB003
–
–
Undefined
000F0631H CAN0 message data byte 1 register 03
C0MDB103
–
–
Undefined
C0MDB2303
–
–
Undefined
000F0632H CAN0 message data byte 2 register 03
C0MDB203
–
–
Undefined
000F0633H CAN0 message data byte 3 register 03
C0MDB303
–
–
Undefined
000F0632H
CAN0 message data byte 23 register 03
C0MDB4503
–
–
Undefined
000F0634H CAN0 message data byte 4 register 03
C0MDB403
–
–
Undefined
000F0635H CAN0 message data byte 5 register 03
C0MDB503
–
–
Undefined
000F0634H
CAN0 message data byte 45 register 03
C0MDB6703
–
–
Undefined
000F0636H CAN0 message data byte 6 register 03
C0MDB603
–
–
Undefined
000F0637H CAN0 message data byte 7 register 03
C0MDB703
–
–
Undefined
000F0636H
CAN0 message data byte 67 register 03
000F0638H
CAN0 message data length register 03
C0MDLC03
–
–
0000xxxxB
000F0639H
CAN0 message configuration register 03
C0MCONF03
–
–
Undefined
000F063AH
CAN0 message ID register 03
C0MIDL03
–
–
Undefined
C0MIDH03
–
–
Undefined
CAN0 message control register 03
C0MCTRL03
–
–
00x00000
000xx000B
000F063CH
000F063EH
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Table 14-16. Register Access Types (4/18)
Address
000F0640H
Register Name
CAN0 message data byte 01 register 04
Symbol
C0MDB0104
R/W
R/W
Bit Manipulation Units
Default Value
1
8
16
–
–
Undefined
000F0640H CAN0 message data byte 0 register 04
C0MDB004
–
–
Undefined
000F0641H CAN0 message data byte 1 register 04
C0MDB104
–
–
Undefined
C0MDB2304
–
–
Undefined
000F0642H CAN0 message data byte 2 register 04
C0MDB204
–
–
Undefined
000F0643H CAN0 message data byte 3 register 04
C0MDB304
–
–
Undefined
C0MDB4504
–
–
Undefined
000F0644H CAN0 message data byte 4 register 04
C0MDB404
–
–
Undefined
000F0645H CAN0 message data byte 5 register 04
C0MDB504
–
–
Undefined
C0MDB6704
–
–
Undefined
C0MDB604
–
–
Undefined
000F0642H
000F0644H
000F0646H
CAN0 message data byte 23 register 04
CAN0 message data byte 45 register 04
CAN0 message data byte 67 register 04
000F0646H CAN0 message data byte 6 register 04
C0MDB704
–
–
Undefined
000F0648H
CAN0 message data length register 04
C0MDLC04
–
–
0000xxxxB
000F0649H
CAN0 message configuration register 04
C0MCONF04
–
–
Undefined
000F064AH
CAN0 message ID register 04
C0MIDL04
–
–
Undefined
C0MIDH04
–
–
Undefined
000F0647H CAN0 message data byte 7 register 04
000F064CH
000F064EH
CAN0 message control register 04
C0MCTRL04
–
–
00x00000
000xx000B
000F0650H
CAN0 message data byte 01 register 05
C0MDB0105
–
–
Undefined
000F0650H CAN0 message data byte 0 register 05
C0MDB005
–
–
Undefined
000F0651H CAN0 message data byte 1 register 05
C0MDB105
–
–
Undefined
C0MDB2305
–
–
Undefined
000F0652H CAN0 message data byte 2 register 05
C0MDB205
–
–
Undefined
000F0653H CAN0 message data byte 3 register 05
C0MDB305
–
–
Undefined
000F0652H
CAN0 message data byte 23 register 05
C0MDB4505
–
–
Undefined
000F0654H CAN0 message data byte 4 register 05
C0MDB405
–
–
Undefined
000F0655H CAN0 message data byte 5 register 05
C0MDB505
–
–
Undefined
000F0654H
CAN0 message data byte 45 register 05
C0MDB6705
–
–
Undefined
000F0656H CAN0 message data byte 6 register 05
C0MDB605
–
–
Undefined
000F0657H CAN0 message data byte 7 register 05
C0MDB705
–
–
Undefined
000F0656H
CAN0 message data byte 67 register 05
000F0658H
CAN0 message data length register 05
C0MDLC05
–
–
0000xxxxB
000F0659H
CAN0 message configuration register 05
C0MCONF05
–
–
Undefined
000F065AH
CAN0 message ID register 05
C0MIDL05
–
–
Undefined
C0MIDH05
–
–
Undefined
CAN0 message configuration register 05
C0MCTRL05
–
–
00x00000
000xx000B
000F065CH
000F065EH
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Table 14-16. Register Access Types (5/18)
Address
000F0660H
Register Name
CAN0 message data byte 01 register 06
Symbol
C0MDB0106
R/W
R/W
Bit Manipulation Units
Default Value
1
8
16
–
–
Undefined
000F0660H CAN0 message data byte 0 register 06
C0MDB006
–
–
Undefined
000F0661H CAN0 message data byte 1 register 06
C0MDB106
–
–
Undefined
C0MDB2306
–
–
Undefined
000F0662H CAN0 message data byte 2 register 06
C0MDB206
–
–
Undefined
000F0663H CAN0 message data byte 3 register 06
C0MDB306
–
–
Undefined
C0MDB4506
–
–
Undefined
000F0664H CAN0 message data byte 4 register 06
C0MDB406
–
–
Undefined
000F0665H CAN0 message data byte 5 register 06
C0MDB506
–
–
Undefined
C0MDB6706
–
–
Undefined
C0MDB606
–
–
Undefined
000F0662H
000F0664H
000F0666H
CAN0 message data byte 23 register 06
CAN0 message data byte 45 register 06
CAN0 message data byte 67 register 06
000F0666H CAN0 message data byte 6 register 06
C0MDB706
–
–
Undefined
000F0668H
CAN0 message data length register 06
C0MDLC06
–
–
0000xxxxB
000F0669H
CAN0 message configuration register 06
C0MCONF06
–
–
Undefined
000F066AH
CAN0 message ID register 06
C0MIDL06
–
–
Undefined
C0MIDH06
–
–
Undefined
000F0667H CAN0 message data byte 7 register 06
000F066CH
000F066EH
CAN0 message control register 06
C0MCTRL06
–
–
00x00000
000xx000B
000F0670H
CAN0 message data byte 01 register 07
C0MDB0107
–
–
Undefined
000F0670H CAN0 message data byte 0 register 07
C0MDB007
–
–
Undefined
000F0671H CAN0 message data byte 1 register 07
C0MDB107
–
–
Undefined
C0MDB2307
–
–
Undefined
000F0672H CAN0 message data byte 2 register 07
C0MDB207
–
–
Undefined
000F0673H CAN0 message data byte 3 register 07
C0MDB307
–
–
Undefined
000F0672H
CAN0 message data byte 23 register 07
C0MDB4507
–
–
Undefined
000F0674H CAN0 message data byte 4 register 07
C0MDB407
–
–
Undefined
000F0675H CAN0 message data byte 5 register 07
C0MDB507
–
–
Undefined
000F0674H
CAN0 message data byte 45 register 07
C0MDB6707
–
–
Undefined
000F0676H CAN0 message data byte 6 register 07
C0MDB607
–
–
Undefined
000F0677H CAN0 message data byte 7 register 07
C0MDB707
–
–
Undefined
000F0676H
CAN0 message data byte 67 register 07
000F0678H
CAN0 message data length register 07
C0MDLC07
–
–
0000xxxxB
000F0679H
CAN0 message configuration register 07
C0MCONF07
–
–
Undefined
000F067AH
CAN0 message ID register 07
C0MIDL07
–
–
Undefined
C0MIDH07
–
–
Undefined
CAN0 message control register 07
C0MCTRL07
–
–
00x00000
000xx000B
000F067CH
000F067EH
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
879
RL78/D1A
CHAPTER 14 CAN CONTROLLER
Table 14-16. Register Access Types (6/18)
Address
000F0680H
Register Name
CAN0 message data byte 01 register 08
Symbol
C0MDB0108
R/W
R/W
Bit Manipulation Units
Default Value
1
8
16
–
–
Undefined
000F0680H CAN0 message data byte 0 register 08
C0MDB008
–
–
Undefined
000F0681H CAN0 message data byte 1 register 08
C0MDB108
–
–
Undefined
C0MDB2308
–
–
Undefined
000F0682H CAN0 message data byte 2 register 08
C0MDB208
–
–
Undefined
000F0683H CAN0 message data byte 3 register 08
C0MDB308
–
–
Undefined
C0MDB4508
–
–
Undefined
000F0684H CAN0 message data byte 4 register 08
C0MDB408
–
–
Undefined
000F0685H CAN0 message data byte 5 register 08
C0MDB508
–
–
Undefined
C0MDB6708
–
–
Undefined
C0MDB608
–
–
Undefined
000F0682H
000F0684H
000F0686H
CAN0 message data byte 23 register 08
CAN0 message data byte 45 register 08
CAN0 message data byte 67 register 08
000F0686H CAN0 message data byte 6 register 08
C0MDB708
–
–
Undefined
000F0688H
CAN0 message data length register 08
C0MDLC08
–
–
0000xxxxB
000F0689H
CAN0 message configuration register 08
C0MCONF08
–
–
Undefined
000F068AH
CAN0 message ID register 08
C0MIDL08
–
–
Undefined
C0MIDH08
–
–
Undefined
000F0687H CAN0 message data byte 7 register 08
000F068CH
000F068EH
CAN0 message control register 08
C0MCTRL08
–
–
00x00000
000xx000B
000F0690H
CAN0 message data byte 01 register 09
C0MDB0109
–
–
Undefined
000F0690H CAN0 message data byte 0 register 09
C0MDB009
–
–
Undefined
000F0691H CAN0 message data byte 1 register 09
C0MDB109
–
–
Undefined
C0MDB2309
–
–
Undefined
000F0692H CAN0 message data byte 2 register 09
C0MDB209
–
–
Undefined
000F0693H CAN0 message data byte 3 register 09
C0MDB309
–
–
Undefined
000F0692H
CAN0 message data byte 23 register 09
C0MDB4509
–
–
Undefined
000F0694H CAN0 message data byte 4 register 09
C0MDB409
–
–
Undefined
000F0695H CAN0 message data byte 5 register 09
C0MDB509
–
–
Undefined
000F0694H
CAN0 message data byte 45 register 09
C0MDB6709
–
–
Undefined
000F0696H CAN0 message data byte 6 register 09
C0MDB609
–
–
Undefined
000F0697H CAN0 message data byte 7 register 09
C0MDB709
–
–
Undefined
000F0696H
CAN0 message data byte 67 register 09
000F0698H
CAN0 message data length register 09
C0MDLC09
–
–
0000xxxxB
000F0699H
CAN0 message configuration register 09
C0MCONF09
–
–
Undefined
000F069AH
CAN0 message ID register 09
C0MIDL09
–
–
Undefined
C0MIDH09
–
–
Undefined
CAN0 message control register 09
C0MCTRL09
–
–
00x00000
000xx000B
000F069CH
000F069EH
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
880
RL78/D1A
CHAPTER 14 CAN CONTROLLER
Table 14-16. Register Access Types (7/18)
Address
000F06A0H
Register Name
CAN0 message data byte 01 register 10
Symbol
C0MDB0110
R/W
R/W
Bit Manipulation Units
Default Value
1
8
16
–
–
Undefined
000F06A0H CAN0 message data byte 0 register 10
C0MDB010
–
–
Undefined
000F06A1H CAN0 message data byte 1 register 10
C0MDB110
–
–
Undefined
C0MDB2310
–
–
Undefined
000F06A2H CAN0 message data byte 2 register 10
C0MDB210
–
–
Undefined
000F06A3H CAN0 message data byte 3 register 10
C0MDB310
–
–
Undefined
C0MDB4510
–
–
Undefined
000F06A4H CAN0 message data byte 4 register 10
C0MDB410
–
–
Undefined
000F06A5H CAN0 message data byte 5 register 10
C0MDB510
–
–
Undefined
C0MDB6710
–
–
Undefined
C0MDB610
–
–
Undefined
000F06A2H
000F06A4H
000F06A6H
CAN0 message data byte 23 register 10
CAN0 message data byte 45 register 10
CAN0 message data byte 67 register 10
000F06A6H CAN0 message data byte 6 register 10
C0MDB710
–
–
Undefined
000F06A8H
CAN0 message data length register 10
C0MDLC10
–
–
0000xxxxB
000F06A9H
CAN0 message configuration register 10
C0MCONF10
–
–
Undefined
000F06AAH
CAN0 message ID register 10
C0MIDL10
–
–
Undefined
C0MIDH10
–
–
Undefined
000F06A7H CAN0 message data byte 7 register 10
000F06ACH
000F06AEH
CAN0 message control register 10
C0MCTRL10
–
–
00x00000
000xx000B
000F06B0H
CAN0 message data byte 01 register 11
C0MDB0111
–
–
Undefined
000F06B0H CAN0 message data byte 0 register 11
C0MDB011
–
–
Undefined
000F06B1H CAN0 message data byte 1 register 11
C0MDB111
–
–
Undefined
C0MDB2311
–
–
Undefined
000F06B2H CAN0 message data byte 2 register 11
C0MDB211
–
–
Undefined
000F06B3H CAN0 message data byte 3 register 11
C0MDB311
–
–
Undefined
000F06B2H
CAN0 message data byte 23 register 11
C0MDB4511
–
–
Undefined
000F06B4H CAN0 message data byte 4 register 11
C0MDB411
–
–
Undefined
000F06B5H CAN0 message data byte 51 register 11
C0MDB511
–
–
Undefined
000F06B4H
CAN0 message data byte 45 register 11
C0MDB6711
–
–
Undefined
000F06B6H CAN0 message data byte 6 register 11
C0MDB611
–
–
Undefined
000F06B7H CAN0 message data byte 71 register 11
C0MDB711
–
–
Undefined
000F06B6H
CAN0 message data byte 67 register 11
000F06B8H
CAN0 message data length register 11
C0MDLC11
–
–
0000xxxxB
000F06B9H
CAN0 message configuration register 11
C0MCONF11
–
–
Undefined
000F06BAH
CAN0 message ID register 11
C0MIDL11
–
–
Undefined
C0MIDH11
–
–
Undefined
CAN0 message control register 11
C0MCTRL11
–
–
00x00000
000xx000B
000F06BCH
000F06BEH
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
881
RL78/D1A
CHAPTER 14 CAN CONTROLLER
Table 14-16. Register Access Types (8/18)
Address
000F06C0H
Register Name
CAN0 message data byte 01 register 12
Symbol
C0MDB0112
R/W
R/W
Bit Manipulation Units
Default Value
1
8
16
–
–
Undefined
000F06C0H CAN0 message data byte 0 register 12
C0MDB012
–
–
Undefined
000F06C1H CAN0 message data byte 1 register 12
C0MDB112
–
–
Undefined
C0MDB2312
–
–
Undefined
000F06C2H CAN0 message data byte 2 register 12
C0MDB212
–
–
Undefined
000F06C3H CAN0 message data byte 3 register 12
C0MDB312
–
–
Undefined
C0MDB4512
–
–
Undefined
000F06C4H CAN0 message data byte 4 register 12
C0MDB412
–
–
Undefined
000F06C5H CAN0 message data byte 5 register 12
C0MDB512
–
–
Undefined
C0MDB6712
–
–
Undefined
C0MDB612
–
–
Undefined
000F06C2H
000F06C4H
000F06C6H
CAN0 message data byte 23 register 12
CAN0 message data byte 45 register 12
CAN0 message data byte 67 register 12
000F06C6H CAN0 message data byte 6 register 12
C0MDB712
–
–
Undefined
000F06C8H
CAN0 message data length register 12
C0MDLC12
–
–
0000xxxxB
000F06C9H
CAN0 message configuration register 12
C0MCONF12
–
–
Undefined
000F06CAH
CAN0 message ID register 12
C0MIDL12
–
–
Undefined
C0MIDH12
–
–
Undefined
000F06C7H CAN0 message data byte 7 register 12
000F06CCH
000F06CEH
CAN0 message control register 12
C0MCTRL12
–
–
00x00000
000xx000B
000F06D0H
CAN0 message data byte 01 register 13
C0MDB0113
–
–
Undefined
000F06D0H CAN0 message data byte 0 register 13
C0MDB013
–
–
Undefined
000F06D1H CAN0 message data byte 1 register 13
C0MDB113
–
–
Undefined
C0MDB2313
–
–
Undefined
000F06D2H CAN0 message data byte 2 register 13
C0MDB213
–
–
Undefined
000F06D3H CAN0 message data byte 3 register 13
C0MDB313
–
–
Undefined
000F06D2H
CAN0 message data byte 23 register 13
C0MDB4513
–
–
Undefined
000F06D4H CAN0 message data byte 4 register 13
C0MDB413
–
–
Undefined
000F06D5H CAN0 message data byte 5 register 13
C0MDB513
–
–
Undefined
000F06D4H
CAN0 message data byte 45 register 13
C0MDB6713
–
–
Undefined
000F06D6H CAN0 message data byte 6 register 13
C0MDB613
–
–
Undefined
000F06D7H CAN0 message data byte 7 register 13
C0MDB713
–
–
Undefined
000F06D6H
CAN0 message data byte 67 register 13
000F06D8H
CAN0 message data length register 13
C0MDLC13
–
–
0000xxxxB
000F06D9H
CAN0 message configuration register 13
C0MCONF13
–
–
Undefined
000F06DAH
CAN0 message ID register 13
C0MIDL13
–
–
Undefined
C0MIDH13
–
–
Undefined
CAN0 message control register 13
C0MCTRL13
–
–
00x00000
000xx000B
000F06DCH
000F06DEH
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
882
RL78/D1A
CHAPTER 14 CAN CONTROLLER
Table 14-16. Register Access Types (9/18)
Address
000F06E0H
Register Name
CAN0 message data byte 01 register 14
Symbol
C0MDB0114
R/W
R/W
Bit Manipulation Units
Default Value
1
8
16
–
–
Undefined
000F06E0H CAN0 message data byte 0 register 14
C0MDB014
–
–
Undefined
000F06E1H CAN0 message data byte 1 register 14
C0MDB114
–
–
Undefined
C0MDB2314
–
–
Undefined
000F06E2H CAN0 message data byte 2 register 14
C0MDB214
–
–
Undefined
000F06E3H CAN0 message data byte 3 register 14
C0MDB314
–
–
Undefined
C0MDB4514
–
–
Undefined
000F06E4H CAN0 message data byte 4 register 14
C0MDB414
–
–
Undefined
000F06E5H CAN0 message data byte 5 register 14
C0MDB514
–
–
Undefined
C0MDB6714
–
–
Undefined
C0MDB614
–
–
Undefined
000F06E2H
000F06E4H
000F06E6H
CAN0 message data byte 23 register 14
CAN0 message data byte 45 register 14
CAN0 message data byte 67 register 14
000F06E6H CAN0 message data byte 6 register 14
C0MDB714
–
–
Undefined
000F06E8H
CAN0 message data length register 14
C0MDLC14
–
–
0000xxxxB
000F06E9H
CAN0 message configuration register 14
C0MCONF14
–
–
Undefined
000F06EAH
CAN0 message ID register 14
C0MIDL14
–
–
Undefined
C0MIDH14
–
–
Undefined
000F06E7H CAN0 message data byte 7 register 14
000F06ECH
000F06EEH
CAN0 message control register 14
C0MCTRL14
–
–
00x00000
000xx000B
000F06F0H
CAN0 message data byte 01 register 15
C0MDB0115
–
–
Undefined
000F06F0H CAN0 message data byte 0 register 15
C0MDB015
–
–
Undefined
000F06F1H CAN0 message data byte 1 register 15
C0MDB115
–
–
Undefined
C0MDB2315
–
–
Undefined
000F06F2H CAN0 message data byte 2 register 15
C0MDB215
–
–
Undefined
000F06F3H CAN0 message data byte 3 register 15
C0MDB315
–
–
Undefined
000F06F2H
CAN0 message data byte 23 register 15
C0MDB4515
–
–
Undefined
000F06F4H CAN0 message data byte 4 register 15
C0MDB415
–
–
Undefined
000F06F5H CAN0 message data byte 5 register 15
C0MDB515
–
–
Undefined
000F06F4H
CAN0 message data byte 45 register 15
C0MDB6715
–
–
Undefined
000F06F6H CAN0 message data byte 6 register 15
C0MDB615
–
–
Undefined
000F06F7H CAN0 message data byte 7 register 15
C0MDB715
–
–
Undefined
000F06F6H
CAN0 message data byte 67 register 15
000F06F8H
CAN0 message data length register 15
C0MDLC15
–
–
0000xxxxB
000F06F9H
CAN0 message configuration register 15
C0MCONF15
–
–
Undefined
000F06FAH
CAN0 message ID register 15
C0MIDL15
–
–
Undefined
C0MIDH15
–
–
Undefined
000F06FCH
000F06FEH
CAN0 message control register 15
C0MCTRL15
–
–
00x00000
000xx000B
000F0340H
CAN1 global module control register
C1GMCTRL
0000H
000F0342H
CAN1 global module clock select register
C1GMCS
0FH
000F0346H
CAN1 global automatic block transmission
control register
C1GMABT
0000H
000F0348H
CAN1 global automatic block transmission
delay setting register
C1GMABTD
00H
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
883
RL78/D1A
CHAPTER 14 CAN CONTROLLER
Table 14-16. Register Access Types (10/18)
Address
000F0380H
Register Name
CAN1 module mask 1 register L
Symbol
C1MASK1L
R/W
Bit Manipulation Units
R/W
1
8
16
Default Value
Undefined
000F0382H
CAN1 module mask 1 register H
C1MASK1H
Undefined
000F0384H
CAN1 module mask 2 register L
C1MASK2L
Undefined
000F0386H
CAN1 module mask 2 register H
C1MASK2H
Undefined
000F0388H
CAN1 module mask 3 register L
C1MASK3L
Undefined
000F038AH
CAN1 module mask 3 register H
C1MASK3H
Undefined
000F038CH
CAN1 module mask 4 register L
C1MASK4L
Undefined
000F038EH
CAN1 module mask 4 register H
C1MASK4H
Undefined
000F0390H
CAN1 module control register
C1CTRL
0000H
000F0392H
CAN1 module last error code register
C1LEC
00H
000F0393H
CAN1 module information register
C1INFO
00H
000F0394H
CAN1 module error counter register
C1ERC
0000H
000F0396H
CAN1 module interrupt enable register
C1IE
0000H
000F0398H
CAN1 module interrupt status register
C1INTS
0000H
000F039AH
CAN1 module bit rate prescaler register
C1BRP
FFH
000F039CH
CAN1 module bit rate register
C1BTR
370FH
000F039EH
CAN1 module last in-pointer register
C1LIPT
R
Undefined
000F03A0H
CAN1 module receive history list register
C1RGPT
R/W
xx02H
000F03A2H
CAN1 module last out-pointer register
C1LOPT
R
Undefined
000F03A4H
CAN1 module transmit history list register
C1TGPT
R/W
xx02H
000F03A6H
CAN1 module time stamp register
C1TS
0000H
000F0400H
CAN1 message data byte 01 register 00
C1MDB0100
R
R/W
–
–
Undefined
000F0400H CAN1 message data byte 0 register 00
C1MDB000
–
–
Undefined
000F0401H CAN1 message data byte 1 register 00
C1MDB100
–
–
Undefined
C1MDB2300
–
–
Undefined
000F0402H CAN1 message data byte 2 register 00
C1MDB200
–
–
Undefined
000F0403H CAN1 message data byte 3 register 00
C1MDB300
–
–
Undefined
000F0402H
CAN1 message data byte 23 register 00
C1MDB4500
–
–
Undefined
000F0404H CAN1 message data byte 4 register 00
C1MDB400
–
–
Undefined
000F0405H CAN1 message data byte 5 register 00
C1MDB500
–
–
Undefined
000F0404H
CAN1 message data byte 45 register 00
C1MDB6700
–
–
Undefined
000F0406H CAN1 message data byte 6 register 00
C1MDB600
–
–
Undefined
000F0407H CAN1 message data byte 7 register 00
C1MDB700
–
–
Undefined
000F0406H
CAN1 message data byte 67 register 00
000F0408H
CAN1 message data length register 00
C1MDLC00
–
–
0000xxxxB
000F0409H
CAN1 message configuration register 00
C1MCONF00
–
–
Undefined
000F040AH
CAN1 message ID register 00 L
C1MIDL00
–
–
Undefined
000F040CH
CAN1 message ID register 00 H
C1MIDH00
–
–
Undefined
000F040EH
CAN1 message control register 00
C1MCTRL00
–
–
00x00000
000xx000B
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
884
RL78/D1A
CHAPTER 14 CAN CONTROLLER
Table 14-16. Register Access Types (11/18)
Address
000F0410H
Register Name
CAN1 message data byte 01 register 01
Symbol
C1MDB0101
R/W
R/W
Bit Manipulation Units
Default Value
1
8
16
–
–
Undefined
000F0410H CAN1 message data byte 0 register 01
C1MDB001
–
–
Undefined
000F0411H CAN1 message data byte 1 register 01
C1MDB101
–
–
Undefined
C1MDB2301
–
–
Undefined
000F0412H CAN1 message data byte 2 register 01
C1MDB201
–
–
Undefined
000F0413H CAN1 message data byte 3 register 01
C1MDB301
–
–
Undefined
C1MDB4501
–
–
Undefined
000F0414H CAN1 message data byte 4 register 01
C1MDB401
–
–
Undefined
000F0415H CAN1 message data byte 5 register 01
C1MDB501
–
–
Undefined
C1MDB6701
–
–
Undefined
C1MDB601
–
–
Undefined
000F0412H
000F0414H
000F0416H
CAN1 message data byte 23 register 01
CAN1 message data byte 45 register 01
CAN1 message data byte 67 register 01
000F0416H CAN1 message data byte 6 register 01
C1MDB701
–
–
Undefined
000F0418H
CAN1 message data length register 01
C1MDLC01
–
–
0000xxxxB
000F0419H
CAN1 message configuration register 01
C1MCONF01
–
–
Undefined
000F041AH
CAN1 message ID register 01 L
C1MIDL01
–
–
Undefined
000F041CH
CAN1 message ID register 01 H
C1MIDH01
–
–
Undefined
000F041EH
CAN1 message control register 01
C1MCTRL01
–
–
00x00000
000xx000B
000F0420H
CAN1 message data byte 01 register 02
C1MDB0102
–
–
Undefined
000F0420H CAN1 message data byte 0 register 02
C1MDB002
–
–
Undefined
000F0421H CAN1 message data byte 1 register 02
C1MDB102
–
–
Undefined
000F0417H CAN1 message data byte 7 register 01
C1MDB2302
–
–
Undefined
000F0422H CAN1 message data byte 2 register 02
C1MDB202
–
–
Undefined
000F0423H CAN1 message data byte 3 register 02
C1MDB302
–
–
Undefined
000F0422H
CAN1 message data byte 23 register 02
C1MDB4502
–
–
Undefined
000F0424H CAN1 message data byte 4 register 02
C1MDB402
–
–
Undefined
000F0425H CAN1 message data byte 5 register 02
C1MDB502
–
–
Undefined
000F0424H
CAN1 message data byte 45 register 02
C1MDB6702
–
–
Undefined
000F0426H CAN1 message data byte 6 register 02
C1MDB602
–
–
Undefined
000F0427H CAN1 message data byte 7 register 02
C1MDB702
–
–
Undefined
000F0426H
CAN1 message data byte 67 register 02
000F0428H
CAN1 message data length register 02
C1MDLC02
–
–
0000xxxxB
000F0429H
CAN1 message configuration register 02
C1MCONF02
–
–
Undefined
000F042AH
CAN1 message ID register 02 L
C1MIDL02
–
–
Undefined
000F042CH
CAN1 message ID register 02 H
C1MIDH02
–
–
Undefined
C1MCTRL02
–
–
00x00000
000xx000B
000F042EH CAN1 message control register 02
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
885
RL78/D1A
CHAPTER 14 CAN CONTROLLER
Table 14-16. Register Access Types (12/18)
Address
000F0430H
Register Name
CAN1 message data byte 01 register 03
Symbol
C1MDB0103
R/W
R/W
Bit Manipulation Units
Default Value
1
8
16
–
–
Undefined
000F0430H CAN1 message data byte 0 register 03
C1MDB003
–
–
Undefined
000F0431H CAN1 message data byte 1 register 03
C1MDB103
–
–
Undefined
C1MDB2303
–
–
Undefined
000F0432H CAN1 message data byte 2 register 03
C1MDB203
–
–
Undefined
000F0433H CAN1 message data byte 3 register 03
C1MDB303
–
–
Undefined
C1MDB4503
–
–
Undefined
000F0434H CAN1 message data byte 4 register 03
C1MDB403
–
–
Undefined
000F0435H CAN1 message data byte 5 register 03
C1MDB503
–
–
Undefined
C1MDB6703
–
–
Undefined
C1MDB603
–
–
Undefined
000F0432H
000F0434H
000F0436H
CAN1 message data byte 23 register 03
CAN1 message data byte 45 register 03
CAN1 message data byte 67 register 03
000F0436H CAN1 message data byte 6 register 03
C1MDB703
–
–
Undefined
000F0438H
CAN1 message data length register 03
C1MDLC03
–
–
0000xxxxB
000F0439H
CAN1 message configuration register 03
C1MCONF03
–
–
Undefined
000F043AH
CAN1 message ID register 03 L
C1MIDL03
–
–
Undefined
000F043CH
CAN1 message ID register 03 H
C1MIDH03
–
–
Undefined
000F043EH
CAN1 message control register 03
C1MCTRL03
–
–
00x00000
000xx000B
000F0440H
CAN1 message data byte 01 register 04
C1MDB0104
–
–
Undefined
000F0440H CAN1 message data byte 0 register 04
C1MDB004
–
–
Undefined
000F0441H CAN1 message data byte 1 register 04
C1MDB104
–
–
Undefined
000F0437H CAN1 message data byte 7 register 03
C1MDB2304
–
–
Undefined
000F0442H CAN1 message data byte 2 register 04
C1MDB204
–
–
Undefined
000F0443H CAN1 message data byte 3 register 04
C1MDB304
–
–
Undefined
000F0442H
CAN1 message data byte 23 register 04
C1MDB4504
–
–
Undefined
000F0444H CAN1 message data byte 4 register 04
C1MDB404
–
–
Undefined
000F0445H CAN1 message data byte 5 register 04
C1MDB504
–
–
Undefined
000F0444H
CAN1 message data byte 45 register 04
C1MDB6704
–
–
Undefined
000F0446H CAN1 message data byte 6 register 04
C1MDB604
–
–
Undefined
000F0447H CAN1 message data byte 7 register 04
C1MDB704
–
–
Undefined
000F0446H
CAN1 message data byte 67 register 04
000F0448H
CAN1 message data length register 04
C1MDLC04
–
–
0000xxxxB
000F0449H
CAN1 message configuration register 04
C1MCONF04
–
–
Undefined
000F044AH
CAN1 message ID register 04 L
C1MIDL04
–
–
Undefined
000F044CH
CAN1 message ID register 04 H
C1MIDH04
–
–
Undefined
000F044EH
CAN1 message control register 04
C1MCTRL04
–
–
00x00000
000xx000B
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
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CHAPTER 14 CAN CONTROLLER
Table 14-16. Register Access Types (13/18)
Address
000F0450H
Register Name
CAN1 message data byte 01 register 05
Symbol
C1MDB0105
R/W
R/W
Bit Manipulation Units
1
8
16
–
–
000F0450H CAN1 message data byte 0 register 05
C1MDB005
–
–
000F0451H CAN1 message data byte 1 register 05
C1MDB105
–
–
C1MDB2305
–
–
000F0452H CAN1 message data byte 2 register 05
C1MDB205
–
–
000F0453H CAN1 message data byte 3 register 05
C1MDB305
–
–
C1MDB4505
–
–
000F0454H CAN1 message data byte 4 register 05
C1MDB405
–
–
000F0455H CAN1 message data byte 5 register 05
C1MDB505
–
–
C1MDB6705
–
–
C1MDB605
–
–
000F0452H
000F0454H
000F0456H
CAN1 message data byte 23 register 05
CAN1 message data byte 45 register 05
CAN1 message data byte 67 register 05
000F0456H CAN1 message data byte 6 register 05
Default Value
Undefined
Undefined
Undefined
Undefined
C1MDB705
–
–
000F0458H
CAN1 message data length register 05
C1MDLC05
–
–
0000xxxxB
000F0459H
CAN1 message configuration register 05
C1MCONF05
–
–
Undefined
000F045AH
CAN1 message ID register 05 L
C1MIDL05
–
–
Undefined
000F045CH
CAN1 message ID register 05 H
C1MIDH05
–
–
Undefined
000F045EH
CAN1 message configuration register 05
C1MCTRL05
–
–
00x00000
000xx000B
000F0460H
CAN1 message data byte 01 register 06
C1MDB0106
–
–
000F0460H CAN1 message data byte 0 register 06
C1MDB006
–
–
Undefined
000F0461H CAN1 message data byte 1 register 06
C1MDB106
–
–
Undefined
000F0457H CAN1 message data byte 7 register 05
Undefined
C1MDB2306
–
–
Undefined
000F0462H CAN1 message data byte 2 register 06
C1MDB206
–
–
Undefined
000F0463H CAN1 message data byte 3 register 06
C1MDB306
–
–
Undefined
000F0462H
CAN1 message data byte 23 register 06
C1MDB4506
–
–
Undefined
000F0464H CAN1 message data byte 4 register 06
C1MDB406
–
–
Undefined
000F0465H CAN1 message data byte 5 register 06
C1MDB506
–
–
Undefined
000F0464H
CAN1 message data byte 45 register 06
C1MDB6706
–
–
Undefined
000F0466H CAN1 message data byte 6 register 06
C1MDB606
–
–
Undefined
000F0467H CAN1 message data byte 7 register 06
C1MDB706
–
–
Undefined
000F0466H
CAN1 message data byte 67 register 06
000F0468H
CAN1 message data length register 06
C1MDLC06
–
–
0000xxxxB
000F0469H
CAN1 message configuration register 06
C1MCONF06
–
–
Undefined
000F046AH
CAN1 message ID register 06 L
C1MIDL06
–
–
Undefined
000F046CH
CAN1 message ID register 06 H
C1MIDH06
–
–
Undefined
000F046EH
CAN1 message control register 06
C1MCTRL06
–
–
00x00000
000xx000B
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
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CHAPTER 14 CAN CONTROLLER
Table 14-16. Register Access Types (14/18)
Address
000F0470H
Register Name
CAN1 message data byte 01 register 07
Symbol
C1MDB0107
R/W
R/W
Bit Manipulation Units
Default Value
1
8
16
–
–
Undefined
000F0470H CAN1 message data byte 0 register 07
C1MDB007
–
–
Undefined
000F0471H CAN1 message data byte 1 register 07
C1MDB107
–
–
Undefined
C1MDB2307
–
–
Undefined
000F0472H CAN1 message data byte 2 register 07
C1MDB207
–
–
Undefined
000F0473H CAN1 message data byte 3 register 07
C1MDB307
–
–
Undefined
C1MDB4507
–
–
Undefined
000F0474H CAN1 message data byte 4 register 07
C1MDB407
–
–
Undefined
000F0475H CAN1 message data byte 5 register 07
C1MDB507
–
–
Undefined
C1MDB6707
–
–
Undefined
C1MDB607
–
–
Undefined
000F0472H
000F0474H
000F0476H
CAN1 message data byte 23 register 07
CAN1 message data byte 45 register 07
CAN1 message data byte 67 register 07
000F0476H CAN1 message data byte 6 register 07
C1MDB707
–
–
Undefined
000F0478H
CAN1 message data length register 07
C1MDLC07
–
–
0000xxxxB
000F0479H
CAN1 message configuration register 07
C1MCONF07
–
–
Undefined
000F047AH
CAN1 message ID register 07 L
C1MIDL07
–
–
Undefined
000F047CH
CAN1 message ID register 07 H
C1MIDH07
–
–
Undefined
000F047EH
CAN1 message control register 07
C1MCTRL07
–
–
00x00000
000xx000B
000F0480H
CAN1 message data byte 01 register 08
C1MDB0108
–
–
Undefined
000F0480H CAN1 message data byte 0 register 08
C1MDB008
–
–
Undefined
000F0481H CAN1 message data byte 1 register 08
C1MDB108
–
–
Undefined
000F0477H CAN1 message data byte 7 register 07
C1MDB2308
–
–
Undefined
000F0482H CAN1 message data byte 2 register 08
C1MDB208
–
–
Undefined
000F0483H CAN1 message data byte 3 register 08
C1MDB308
–
–
Undefined
000F0482H
CAN1 message data byte 23 register 08
C1MDB4508
–
–
Undefined
000F0484H CAN1 message data byte 4 register 08
C1MDB408
–
–
Undefined
000F0485H CAN1 message data byte 5 register 08
C1MDB508
–
–
Undefined
000F0484H
CAN1 message data byte 45 register 08
C1MDB6708
–
–
Undefined
000F0486H CAN1 message data byte 6 register 08
C1MDB608
–
–
Undefined
000F0487H CAN1 message data byte 7 register 08
C1MDB708
–
–
Undefined
000F0486H
CAN1 message data byte 67 register 08
000F0488H
CAN1 message data length register 08
C1MDLC08
–
–
0000xxxxB
000F0489H
CAN1 message configuration register 08
C1MCONF08
–
–
Undefined
000F048AH
CAN1 message ID register 08 H
C1MIDL08
–
–
Undefined
000F048CH
CAN1 message ID register 08 L
C1MIDH08
–
–
Undefined
000F048EH
CAN1 message control register 08
C1MCTRL08
–
–
00x00000
000xx000B
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
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RL78/D1A
CHAPTER 14 CAN CONTROLLER
Table 14-16. Register Access Types (15/18)
Address
000F0490H
Register Name
CAN1 message data byte 01 register 09
Symbol
C1MDB0109
R/W
R/W
Bit Manipulation Units
Default Value
1
8
16
–
–
Undefined
000F0490H CAN1 message data byte 0 register 09
C1MDB009
–
–
Undefined
000F0491H CAN1 message data byte 1 register 09
C1MDB109
–
–
Undefined
C1MDB2309
–
–
Undefined
000F0492H CAN1 message data byte 2 register 09
C1MDB209
–
–
Undefined
000F0493H CAN1 message data byte 3 register 09
C1MDB309
–
–
Undefined
C1MDB4509
–
–
Undefined
000F0494H CAN1 message data byte 4 register 09
C1MDB409
–
–
Undefined
000F0495H CAN1 message data byte 5 register 09
C1MDB509
–
–
Undefined
C1MDB6709
–
–
Undefined
C1MDB609
–
–
Undefined
000F0492H
000F0494H
000F0496H
CAN1 message data byte 23 register 09
CAN1 message data byte 45 register 09
CAN1 message data byte 67 register 09
000F0496H CAN1 message data byte 6 register 09
C1MDB709
–
–
Undefined
000F0498H
CAN1 message data length register 09
C1MDLC09
–
–
0000xxxxB
000F0499H
CAN1 message configuration register 09
C1MCONF09
–
–
Undefined
000F049AH
CAN1 message ID register 09 L
C1MIDL09
–
–
Undefined
000F049CH
CAN1 message ID register 09 H
C1MIDH09
–
–
Undefined
000F049EH
CAN1 message control register 09
C1MCTRL09
–
–
00x00000
000xx000B
000F04A0H
CAN1 message data byte 01 register 10
C1MDB0110
–
–
Undefined
000F04A0H CAN1 message data byte 0 register 10
C1MDB010
–
–
Undefined
000F04A1H CAN1 message data byte 1 register 10
C1MDB110
–
–
Undefined
000F0497H CAN1 message data byte 7 register 09
C1MDB2310
–
–
Undefined
000F04A2H CAN1 message data byte 2 register 10
C1MDB210
–
–
Undefined
000F04A3H CAN1 message data byte 3 register 10
C1MDB310
–
–
Undefined
000F04A2H
CAN1 message data byte 23 register 10
C1MDB4510
–
–
Undefined
000F04A4H CAN1 message data byte 4 register 10
C1MDB410
–
–
Undefined
000F04A5H CAN1 message data byte 5 register 10
C1MDB510
–
–
Undefined
000F04A4H
CAN1 message data byte 45 register 10
C1MDB6710
–
–
Undefined
000F04A6H CAN1 message data byte 6 register 10
C1MDB610
–
–
Undefined
000F04A7H CAN1 message data byte 7 register 10
C1MDB710
–
–
Undefined
000F04A6H
CAN1 message data byte 67 register 10
000F04A8H
CAN1 message data length register 10
C1MDLC10
–
–
0000xxxxB
000F04A9H
CAN1 message configuration register 10
C1MCONF10
–
–
Undefined
000F04AAH
CAN1 message ID register 10 L
C1MIDL10
–
–
Undefined
000F04ACH
CAN1 message ID register 10 H
C1MIDH10
–
–
Undefined
000F04AEH
CAN1 message control register 10
C1MCTRL10
–
–
00x00000
000xx000B
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
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RL78/D1A
CHAPTER 14 CAN CONTROLLER
Table 14-16. Register Access Types (16/18)
Address
000F04B0H
Register Name
CAN1 message data byte 01 register 11
Symbol
C1MDB0111
R/W
R/W
Bit Manipulation Units
Default Value
1
8
16
–
–
Undefined
000F04B0H CAN1 message data byte 0 register 11
C1MDB011
–
–
Undefined
000F04B1H CAN1 message data byte 1 register 11
C1MDB111
–
–
Undefined
C1MDB2311
–
–
Undefined
000F04B2H CAN1 message data byte 2 register 11
C1MDB211
–
–
Undefined
000F04B3H CAN1 message data byte 3 register 11
C1MDB311
–
–
Undefined
C1MDB4511
–
–
Undefined
000F04B2H
000F04B4H
CAN1 message data byte 23 register 11
CAN1 message data byte 45 register 11
000F04B4H CAN1 message data byte 4 register 11
C1MDB411
–
–
Undefined
000F04B5H CAN1 message data byte 51 register 11
C1MDB511
–
–
Undefined
C1MDB6711
–
–
Undefined
000F04B6H CAN1 message data byte 6 register 11
C1MDB611
–
–
Undefined
000F04B7H CAN1 message data byte 71 register 11
000F04B6H
CAN1 message data byte 67 register 11
C1MDB711
–
–
Undefined
000F04B8H
CAN1 message data length register 11
C1MDLC11
–
–
0000xxxxB
000F04B9H
CAN1 message configuration register 11
C1MCONF11
–
–
Undefined
000F04BAH
CAN1 message ID register 11 L
C1MIDL11
–
–
Undefined
000F04BCH
CAN1 message ID register 11 H
C1MIDH11
–
–
Undefined
000F04BEH
CAN1 message control register 11
C1MCTRL11
–
–
00x00000
000xx000B
000F04C0H
CAN1 message data byte 01 register 12
C1MDB0112
–
–
Undefined
000F04C0H CAN1 message data byte 0 register 12
C1MDB012
–
–
Undefined
000F04C1H CAN1 message data byte 1 register 12
C1MDB112
–
–
Undefined
C1MDB2312
–
–
Undefined
000F04C2H CAN1 message data byte 2 register 12
C1MDB212
–
–
Undefined
000F04C3H CAN1 message data byte 3 register 12
C1MDB312
–
–
Undefined
000F04C2H
CAN1 message data byte 23 register 12
C1MDB4512
–
–
Undefined
000F04C4H CAN1 message data byte 4 register 12
C1MDB412
–
–
Undefined
000F04C5H CAN1 message data byte 5 register 12
C1MDB512
–
–
Undefined
000F04C4H
CAN1 message data byte 45 register 12
C1MDB6712
–
–
Undefined
000F04C6H CAN1 message data byte 6 register 12
C1MDB612
–
–
Undefined
000F04C7H CAN1 message data byte 7 register 12
C1MDB712
–
–
Undefined
000F04C6H
CAN1 message data byte 67 register 12
000F04C8H
CAN1 message data length register 12
C1MDLC12
–
–
0000xxxxB
000F04C9H
CAN1 message configuration register 12
C1MCONF12
–
–
Undefined
000F04CAH
CAN1 message ID register 12 L
C1MIDL12
–
–
Undefined
000F04CCH
CAN1 message ID register 12 H
C1MIDH12
–
–
Undefined
000F04CEH
CAN1 message control register 12
C1MCTRL12
–
–
00x00000
000xx000B
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
890
RL78/D1A
CHAPTER 14 CAN CONTROLLER
Table 14-16. Register Access Types (17/18)
Address
000F04D0H
Register Name
CAN1 message data byte 01 register 13
Symbol
C1MDB0113
R/W
R/W
Bit Manipulation Units
Default Value
1
8
16
–
–
Undefined
000F04D0H CAN1 message data byte 0 register 13
C1MDB013
–
–
Undefined
000F04D1H CAN1 message data byte 1 register 13
C1MDB113
–
–
Undefined
C1MDB2313
–
–
Undefined
000F04D2H CAN1 message data byte 2 register 13
C1MDB213
–
–
Undefined
000F04D3H CAN1 message data byte 3 register 13
C1MDB313
–
–
Undefined
C1MDB4513
–
–
Undefined
000F04D4H CAN1 message data byte 4 register 13
C1MDB413
–
–
Undefined
000F04D5H CAN1 message data byte 5 register 13
C1MDB513
–
–
Undefined
C1MDB6713
–
–
Undefined
C1MDB613
–
–
Undefined
000F04D2H
000F04D4H
000F04D6H
CAN1 message data byte 23 register 13
CAN1 message data byte 45 register 13
CAN1 message data byte 67 register 13
000F04D6H CAN1 message data byte 6 register 13
C1MDB713
–
–
Undefined
000F04D8H
CAN1 message data length register 13
C1MDLC13
–
–
0000xxxxB
000F04D9H
CAN1 message configuration register 13
C1MCONF13
–
–
Undefined
000F04DAH
CAN1 message ID register 13 L
C1MIDL13
–
–
Undefined
000F04DCH
CAN1 message ID register 13 H
C1MIDH13
–
–
Undefined
000F04DEH
CAN1 message control register 13
C1MCTRL13
–
–
00x00000
000xx000B
000F04E0H
CAN1 message data byte 01 register 14
C1MDB0114
–
–
Undefined
000F04E0H CAN1 message data byte 0 register 14
C1MDB014
–
–
Undefined
000F04E1H CAN1 message data byte 1 register 14
C1MDB114
–
–
Undefined
000F04D7H CAN1 message data byte 7 register 13
C1MDB2314
–
–
Undefined
000F04E2H CAN1 message data byte 2 register 14
C1MDB214
–
–
Undefined
000F04E3H CAN1 message data byte 3 register 14
C1MDB314
–
–
Undefined
000F04E2H
CAN1 message data byte 23 register 14
C1MDB4514
–
–
Undefined
000F04E4H CAN1 message data byte 4 register 14
C1MDB414
–
–
Undefined
000F04E5H CAN1 message data byte 5 register 14
C1MDB514
–
–
Undefined
000F04E4H
CAN1 message data byte 45 register 14
C1MDB6714
–
–
Undefined
000F04E6H CAN1 message data byte 6 register 14
C1MDB614
–
–
Undefined
000F04E7H CAN1 message data byte 7 register 14
C1MDB714
–
–
Undefined
000F04E6H
CAN1 message data byte 67 register 14
000F04E8H
CAN1 message data length register 14
C1MDLC14
–
–
0000xxxxB
000F04E9H
CAN1 message configuration register 14
C1MCONF14
–
–
Undefined
000F04EAH
CAN1 message ID register 14 L
C1MIDL14
–
–
Undefined
000F04ECH
CAN1 message ID register 14 H
C1MIDH14
–
–
Undefined
000F04EEH
CAN1 message control register 14
C1MCTRL14
–
–
00x00000
000xx000B
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
891
RL78/D1A
CHAPTER 14 CAN CONTROLLER
Table 14-16. Register Access Types (18/18)
Address
000F04F0H
Register Name
CAN1 message data byte 01 register 15
Symbol
C1MDB0115
R/W
R/W
Bit Manipulation Units
Default Value
1
8
16
–
–
Undefined
000F04F0H CAN1 message data byte 0 register 15
C1MDB015
–
–
Undefined
000F04F1H CAN1 message data byte 1 register 15
C1MDB115
–
–
Undefined
C1MDB2315
–
–
Undefined
000F04F2H CAN1 message data byte 2 register 15
C1MDB215
–
–
Undefined
000F04F3H CAN1 message data byte 3 register 15
C1MDB315
–
–
Undefined
C1MDB4515
–
–
Undefined
000F04F2H
000F04F4H
CAN1 message data byte 23 register 15
CAN1 message data byte 45 register 15
000F04F4H CAN1 message data byte 4 register 15
C1MDB415
–
Undefined
000F04F5H CAN1 message data byte 5 register 15
C1MDB515
–
–
Undefined
C1MDB6715
–
–
Undefined
C1MDB615
–
–
Undefined
000F04F6H
CAN1 message data byte 67 register 15
000F04F6H CAN1 message data byte 6 register 15
C1MDB715
–
–
Undefined
000F04F8H
CAN1 message data length register 15
C1MDLC15
–
–
0000xxxxB
000F04F9H
CAN1 message configuration register 15
C1MCONF15
–
–
Undefined
000F04FAH
CAN1 message ID register 15 L
C1MIDL15
–
–
Undefined
000F04FCH
CAN1 message ID register 15 H
C1MIDH15
–
–
Undefined
000F04FEH
CAN1 message control register 15
C1MCTRL15
–
–
00x00000
000xx000B
000F04F7H CAN1 message data byte 7 register 15
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
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RL78/D1A
CHAPTER 14 CAN CONTROLLER
14.5.3 Register bit configuration
Table 14-17. Bit Configuration of CAN Global Registers (1/2)
Address
Symbol
Bit 7/15
Bit 6/14
Bit 5/13
Bit 4/12
Bit 3/11
Bit 2/10
Bit 1/9
Bit 0/8
000F05C0H C0GMCTRL(W)
0
0
0
0
0
0
0
Clear GOM
000F05C1H
0
0
0
0
0
0
Set EFSD
Set GOM
000F05C0H C0GMCTRL(R)
0
0
0
0
0
0
EFSD
GOM
MBON
0
0
0
0
0
0
0
000F05C6H C0GMABT(W)
0
0
0
0
0
0
0
Clear
ABTTRG
000F05C7H
0
0
0
0
0
0
Set
ABTCLR
Set
ABTTRG
000F05C1H
000F05C6H C0GMABT(R)
0
0
0
0
0
0
ABTCLR
ABTTRG
000F05C7H
0
0
0
0
0
0
0
0
000F05C8H C0GMABTD
0
0
0
0
ABTD3
ABTD2
ABTD1
ABTD0
000F05CEH C0GMCS
0
0
0
0
CCP3
CCP2
CCP1
CCP0
Table 14-17. Bit Configuration of CAN Global Registers (2/2)
Address
Symbol
Bit 7/15
Bit 6/14
Bit 5/13
Bit 4/12
Bit 3/11
Bit 2/10
Bit 1/9
Bit 0/8
000F0340H C1GMCTRL(W)
0
0
0
0
0
0
0
Clear GOM
000F0341H
0
0
0
0
0
0
Set EFSD
Set GOM
000F0340H C1GMCTRL(R)
0
0
0
0
0
0
EFSD
GOM
MBON
0
0
0
0
0
0
0
000F0346H C1GMABT(W)
0
0
0
0
0
0
0
Clear
ABTTRG
000F0347H
0
0
0
0
0
0
Set
ABTCLR
Set
ABTTRG
000F0341H
000F0346H C1GMABT(R)
0
0
0
0
0
0
ABTCLR
ABTTRG
000F0347H
0
0
0
0
0
0
0
0
000F0348H
C1GMABTD
0
0
0
0
ABTD3
ABTD2
ABTD1
ABTD0
000F0342H
C1GMCS
0
0
0
0
CCP3
CCP2
CCP1
CCP0
Caution The actual register address is calculated as follows:
Register Address = Global Register Area Offset (CH dependent) + Offset Address as listed in table
above
Remark (R) When read
(W) When write
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CHAPTER 14 CAN CONTROLLER
Table 14-18. Bit Configuration of CAN Module Registers (1/4)
Address
Symbol
Bit 7/15
Bit 6/14
Bit 5/13
Bit 4/12
000F05D0H C0MASK1L
Bit 3/11
CM1ID [15:8]
000F05D2H C0MASK1H
CM1ID [23:16]
0
0
0
CM2ID [7:0]
000F05D5H
CM2ID [15:8]
000F05D6H C0MASK2H
CM2ID [23:16]
0
0
0
CM2ID [28:24]
000F05D8H C0MASK3L
CM3ID [7:0]
000F05D9H
CM3ID [15:8]
000F05DAH C0MASK3H
CM3ID [23:16]
000F05DBH
0
0
0
CM3ID [28:24]
000F05DCH C0MASK4L
CM4ID [7:0]
000F05DDH
CM4ID [15:8]
000F05DEH C0MASK4H
CM4ID [23:16]
000F05DFH
Bit 0/8
CM1ID [28:24]
000F05D4H C0MASK2L
000F05D7H
Bit 1/9
CM1ID [7:0]
000F05D1H
000F05D3H
Bit 2/10
0
0
0
000F05E0H C0CTRL(W)
Clear
CCERC
Clear
AL
Clear
VALID
Clear
PSMODE
1
Clear
PSMODE
0
CM4ID [28:24]
Clear
OPMODE
2
Clear
OPMODE
1
Clear
OPMODE
0
000F05E1H
Set
CCERC
Set
AL
0
Set
PSMODE
1
Set
PSMODE
0
Set
OPMODE
2
Set
OPMODE
1
Set
OPMODE
0
000F05E0H C0CTRL(R)
CCERC
AL
VALID
PSMODE
1
PSMODE
0
OPMODE
2
OPMODE
1
OPMODE
0
000F05E1H
0
0
0
0
0
0
RSTAT
TSTAT
000F05E2H C0LEC(W)
0
0
0
0
0
0
0
0
000F05E2H C0LEC(R)
0
0
0
0
0
LEC2
LEC1
LEC0
000F05E3H C0INFO
0
0
0
BOFF
TECS1
TECS0
RECS1
RECS0
000F05E4H C0ERC
000F05E5H
TEC [7:0]
REPS
REC [7:0]
000F05E6H C0IE(W)
0
0
Clear
CIE5
Clear
CIE4
Clear
CIE3
Clear
CIE2
Clear
CIE1
Clear
CIE0
000F05E7H
0
0
Set CIE5
Set CIE4
Set CIE3
Set CIE2
Set CIE1
Set CIE0
000F05E6H C0IE(R)
0
0
CIE5
CIE4
CIE3
CIE2
CIE1
CIE0
000F05E7H
0
0
0
0
0
0
0
0
000F05E8H C0INTS(W)
0
0
Clear
CINTS5
Clear
CINTS4
Clear
CINTS3
Clear
CINTS2
Clear
CINTS1
Clear
CINTS0
000F05E9H
0
0
0
0
0
0
0
0
Caution The actual register address is calculated as follows:
Register Address = Global Register Area Offset (CH dependent) + Offset Address as listed in table
above
Remark (R) When read
(W) When write
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CHAPTER 14 CAN CONTROLLER
Table 14-18. Bit Configuration of CAN Module Registers (2/4)
Address
Symbol
Bit 7/15
Bit 6/14
Bit 5/13
Bit 4/12
Bit 3/11
Bit 2/10
Bit 1/9
Bit 0/8
000F05E8H C0INTS(R)
0
0
CINTS5
CINTS4
CINTS3
CINTS2
CINTS1
CINTS0
000F05E9H
0
0
0
0
0
0
0
0
000F05EAH C0BRP
TQPRS [7:0]
000F05ECH C0BTR
0
0
000F05EDH
0
0
0
0
TSEG1 [3:0]
SJW [1:0]
0
000F05EEH C0LIPT
TSEG2 [2:0]
LIPT [7:0]
000F05F0H C0RGPT(W)
0
0
0
0
0
0
0
Clear
ROVF
000F05F1H
0
0
0
0
0
0
0
0
000F05F0H C0RGPT(R)
0
0
0
0
0
0
RHPM
ROVF
000F05F1H
RGPT [7:0]
000F05F2H C0LOPT
LOPT [7:0]
000F05F4H C0TGPT(W)
0
0
0
0
0
0
0
Clear
TOVF
000F05F5H
0
0
0
0
0
0
0
0
000F05F4H C0TGPT(R)
0
0
0
0
0
0
THPM
TOVF
000F05F5H
TGPT [7:0]
000F05F6H C0TS(W)
0
0
0
0
0
Clear
TSLOCK
Clear
TSSEL
Clear
TSEN
000F05F7H
0
0
0
0
0
Set
TSLOCK
Set
TSSEL
Set
TSEN
000F05F6H C0TS(R)
0
0
0
0
0
TSLOCK
TSSEL
TSEN
000F05F7H
0
0
0
0
0
0
0
0
Caution The actual register address is calculated as follows:
Register Address = Global Register Area Offset (CH dependent) + Offset Address as listed in table
above
Remark (R) When read
(W) When write
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CHAPTER 14 CAN CONTROLLER
Table 14-18. Bit Configuration of CAN Module Registers (3/4)
Address
Symbol
Bit 7/15
Bit 6/14
Bit 5/13
Bit 4/12
000F0380H C1MASK1L
Bit 3/11
CM1ID [15:8]
000F0382H C1MASK1H
CM1ID [23:16]
0
0
0
CM2ID [7:0]
000F0385H
CM2ID [15:8]
000F0386H C1MASK2H
CM2ID [23:16]
0
0
0
CM2ID [28:24]
000F0388H C1MASK3L
CM3ID [7:0]
000F0389H
000F038AH
CM3ID [15:8]
C1MASK3H
000F038BH
CM3ID [23:16]
0
0
0
CM3ID [28:24]
000F038CH C1MASK4L
CM4ID [7:0]
000F038DH
CM4ID [15:8]
000F038EH
Bit 0/8
CM1ID [28:24]
000F0384H C1MASK2L
000F0387H
Bit 1/9
CM1ID [7:0]
000F0381H
000F0383H
Bit 2/10
C1MASK4H
000F038FH
CM4ID [23:16]
0
0
0
000F0390H C1CTRL(W)
Clear
CCERC
Clear
AL
Clear
VALID
Clear
PSMODE
1
Clear
PSMODE
0
CM4ID [28:24]
Clear
OPMODE
2
Clear
OPMODE
1
Clear
OPMODE
0
000F0391H
Set
CCERC
Set
AL
0
Set
PSMODE
1
Set
PSMODE
0
Set
OPMODE
2
Set
OPMODE
1
Set
OPMODE
0
000F0390H C1CTRL(R)
CCERC
AL
VALID
PSMODE
1
PSMODE
0
OPMODE
2
OPMODE
1
OPMODE
0
000F0391H
0
0
0
0
0
0
RSTAT
TSTAT
000F0392H C1LEC(W)
0
0
0
0
0
0
0
0
000F0392H C1LEC(R)
0
0
0
0
0
LEC2
LEC1
LEC0
000F0393H C1INFO
0
0
0
BOFF
TECS1
TECS0
RECS1
RECS0
000F0394H C1ERC
000F0395H
TEC [7:0]
REPS
REC [7:0]
000F0396H C1IE(W)
0
0
Clear
CIE5
Clear
CIE4
Clear
CIE3
Clear
CIE2
Clear
CIE1
Clear
CIE0
000F0397H
0
0
Set CIE5
Set CIE4
Set CIE3
Set CIE2
Set CIE1
Set CIE0
000F0396H C1IE(R)
0
0
CIE5
CIE4
CIE3
CIE2
CIE1
CIE0
000F0397H
0
0
0
0
0
0
0
0
000F0398H C1INTS(W)
0
0
Clear
CINTS5
Clear
CINTS4
Clear
CINTS3
Clear
CINTS2
Clear
CINTS1
Clear
CINTS0
000F0399H
0
0
0
0
0
0
0
0
000F0398H C1INTS(R)
0
0
CINTS5
CINTS4
CINTS3
CINTS2
CINTS1
CINTS0
000F0399H
0
0
0
0
0
0
0
0
Caution The actual register address is calculated as follows:
Register Address = Global Register Area Offset (CH dependent) + Offset Address as listed in table
above
Remark (R) When read
(W) When write
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CHAPTER 14 CAN CONTROLLER
Table 14-18. Bit Configuration of CAN Module Registers (4/4)
Address
Symbol
Bit 7/15
Bit 6/14
Bit 5/13
Bit 4/12
000F039AH C1BRP
Bit 3/11
Bit 2/10
Bit 1/9
Bit 0/8
TQPRS [7:0]
000F039CH C1BTR
0
0
000F039DH
0
0
0
0
TSEG1 [3:0]
SJW [1:0]
0
000F039EH C1LIPT
TSEG2 [2:0]
LIPT [7:0]
000F03A0H C1RGPT(W)
0
0
0
0
0
0
0
Clear
ROVF
000F03A1H
0
0
0
0
0
0
0
0
000F03A0H C1RGPT(R)
0
0
0
0
0
0
RHPM
ROVF
000F03A1H
RGPT [7:0]
000F03A2H C1LOPT
LOPT [7:0]
000F03A4H C1TGPT(W)
0
0
0
0
0
0
0
Clear
TOVF
000F03A5H
0
0
0
0
0
0
0
0
000F03A4H C1TGPT(R)
0
0
0
0
0
0
THPM
TOVF
000F03A5H
TGPT [7:0]
000F03A6H C1TS(W)
0
0
0
0
0
Clear
TSLOCK
Clear
TSSEL
Clear
TSEN
000F03A7H
0
0
0
0
0
Set
TSLOCK
Set
TSSEL
Set
TSEN
000F03A6H C1TS(R)
0
0
0
0
0
TSLOCK
TSSEL
TSEN
000F03A7H
0
0
0
0
0
0
0
0
Caution The actual register address is calculated as follows:
Register Address = Global Register Area Offset (CH dependent) + Offset Address as listed in table
above
Remark (R) When read
(W) When write
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CHAPTER 14 CAN CONTROLLER
Table 14-19. Bit Configuration of Message Buffer Registers (1/2)
Address
Symbol
000F06x0H
Bit 7/15
Bit 6/14
C0MDB01m
Message data (byte 0)
000F06x0H
C0MDB0m
Message data (byte 0)
000F06x1H
C0MDB1m
Message data (byte 1)
000F06x2H
C0MDB23m
Message data (byte 2)
000F06x1H
Bit 5/13
Bit 4/12
Bit 3/11
Bit 2/10
Bit 1/9
Bit 0/8
Message data (byte 1)
000F06x3H
Message data (byte 3)
000F06x2H
C0MDB2m
Message data (byte 2)
000F06x3H
C0MDB3m
Message data (byte 3)
000F06x4H
C0MDB45m
Message data (byte 4)
000F06x4H
C0MDB4m
Message data (byte 4)
000F06x5H
C0MDB5m
Message data (byte 5)
000F06x6H
C0MDB67m
Message data (byte 6)
000F06x5H
Message data (byte 5)
000F06x7H
Message data (byte 7)
000F06x6H
C0MDB6m
Message data (byte 6)
000F06x7H
C0MDB7m
Message data (byte 7)
000F06x8H
C0MDLCm
000F06x9H
C0MCONFm
0
0
0
0
MDLC3
MDLC2
MDLC1
MDLC0
OWS
RTR
MT2
MT1
MT0
0
0
MA0
000F06xAH C0MIDLm
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
000F06xBH
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
000F06xCH C0MIDHm
ID23
ID22
ID21
ID20
ID19
ID18
ID17
ID16
000F06xDH
IDE
0
0
ID28
ID27
ID26
ID25
ID24
0
0
0
000F06xEH C0MCTRLm (W)
Clear MOW Clear IE
Clear DN Clear TRQ Clear RDY
000F06xFH
0
0
0
0
Set IE
0
Set TRQ
Set RDY
000F06xEH C0MCTRLm (R)
0
0
0
MOW
IE
DN
TRQ
RDY
000F06xFH
0
0
MUC
0
0
0
0
0
Caution The actual register address is calculated as follows:
Register Address = Global Register Area Offset (CH dependent) + Offset Address as listed in table
above
Remarks 1. (R) When read
(W) When write
2.
m = 0 to 15
3.
x = 0 to F
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CHAPTER 14 CAN CONTROLLER
Table 14-19. Bit Configuration of Message Buffer Registers (2/2)
Address
Symbol
000F04x0H
Bit 7/15
Bit 6/14
C1MDB01m
Message data (byte 0)
000F04x0H
C1MDB0m
Message data (byte 0)
000F04x1H
C1MDB1m
Message data (byte 1)
000F04x2H
C1MDB23m
Message data (byte 2)
000F04x1H
Bit 4/12
Bit 3/11
Bit 2/10
Bit 1/9
Bit 0/8
MDLC2
MDLC1
MDLC0
Message data (byte 1)
000F04x3H
Message data (byte 3)
000F04x2H
C1MDB2m
000F04x3H
C1MDB3m
Message data (byte 3)
000F04x4H
C1MDB45m
Message data (byte 4)
000F04x4H
C1MDB4m
Message data (byte 4)
000F04x5H
C1MDB5m
Message data (byte 5)
000F04x6H
C1MDB67m
Message data (byte 6)
000F04x5H
Message data (byte 2)
Message data (byte 5)
000F04x7H
000F04x6H
Bit 5/13
Message data (byte 7)
C1MDB6m
Message data (byte 6)
000F04x7H
C1MDB7m
Message data (byte 7)
000F04x8H
C1MDLCm
000F04x9H
C1MCONFm
0
0
0
0
MDLC3
OWS
RTR
MT2
MT1
MT0
0
0
MA0
000F04xAH C1MIDLm
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
000F04xBH
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
000F04xCH C1MIDHm
ID23
ID22
ID21
ID20
ID19
ID18
ID17
ID16
000F04xDH
IDE
0
0
ID28
ID27
ID26
ID25
ID24
0
0
0
000F04xEH C1MCTRLm (W)
Clear MOW Clear IE
Clear DN Clear TRQ Clear RDY
000F04xFH
0
0
0
0
Set IE
0
Set TRQ
Set RDY
000F04xEH C1MCTRLm (R)
0
0
0
MOW
IE
DN
TRQ
RDY
000F04xFH
0
0
MUC
0
0
0
0
0
Caution The actual register address is calculated as follows:
Register Address = Global Register Area Offset (CH dependent) + Offset Address as listed in table
above
Remarks 1. (R) When read
(W) When write
2. m = 0 to 15
3. x = 0 to F
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CHAPTER 14 CAN CONTROLLER
14.6 Bit Set/Clear Function
The CAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface.
An operation error occurs if the following registers are written directly. Do not write any values directly via bit manipulation,
read/modify/write, or direct writing of target values.
CAN global control register (C0GMCTRL, C1GMCTRL)
CAN global automatic block transmission control register (C0GMABT, C1GMABT)
CAN module control register (C0CTRL, C1CTRL)
CAN module interrupt enable register (C0IE, C1IE)
CAN module interrupt status register (C0INTS, C1INTS)
CAN module receive history list register (C0RGPT, C1RGPT)
CAN module transmit history list register (C0TGPT, C1TGPT)
CAN module time stamp register (C0TS, C1TS)
CAN message control register (C0MCTRLm, C1MCTRLm)
Remark m = 0 to 15
All the 16 bits in the above registers can be read via the usual method. Use the procedure described in figure 14-23
below to set or clear the lower 8 bits in these registers.
Setting or clearing of lower 8 bits in the above registers is performed in combination with the higher 8 bits (refer to the
16-bit data after a write operation in Figure 14-24). Figure 14-23 shows how the values of set bits or clear bits relate to
set/clear/no change operations in the corresponding register.
Figure 14-23. Example of Bit Setting/Clearing Operations
Register’s current values
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
1
Write values
0
0
0
0
1
0
1
1
1
1
0
1
1
0
0
0
set
0
0
0
0
1
0
1
1
clear 1
1
0
1
1
0
0
0
Set
Set
0
No change
0
No change
0
Clear
0
No change
0
Clear
0
Clear
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0
Bit status
Register’s value after
write operations
0
0
0
0
0
0
0
1
1
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RL78/D1A
CHAPTER 14 CAN CONTROLLER
Figure 14-24. 16-Bit Data during Write Operation
15
14
13
12
11
10
9
8
set 7
set 6
set 5
set 4
set 3
set 2
set 1
7
6
5
4
3
2
1
0
set 0 clear 7 clear 6 clear 5 clear 4 clear 3 clear 2 clear 1 clear 0
set n
clear n
Status of bit n after bit set/clear operation
0
0
No change
0
1
0
1
0
1
1
1
No change
Remark n = 0 to 7
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CHAPTER 14 CAN CONTROLLER
14.7 Control Registers
Remark m = 0 to 15
(1) Peripheral clock select register (PCKSEL)
This register is used to select for and supply to each peripheral hardware device the operating clock.
PCKSEL can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Caution Set the PCKSEL register before starting to operate each peripheral hardware device.
Figure 14-25. Format of Peripheral Clock Select Register (PCKSEL)
Address: F00F2H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
PCKSEL
0
CAN
CAN
CAN
CAN
0
0
SGCLK
MCKE1
MCK1
MCKE0
MCK0
CANMCKEn CANMCKn
0
X
SEL
aFCANn input clock control
STOPS input clock supply.
Writing to SFR to be used with aFCANn is disabled
1
0
1
1
fMAIN is supplied
Reading from and writing to SFR to be used with aFCANn is enable
fMP is supplied
Reading from and writing to SFR to be used with aFCANn is enable
n = 0, 1
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CHAPTER 14 CAN CONTROLLER
(2) CAN global module control register (C0GMCTRL, C1GMCTRL)
The C0GMCTRL, C1GMCTRL register is used to control the operation of the CAN module.
Figure 14-26. Format of CAN Global Module Control Register (C0GMCTRL, C1GMCTRL) (1/2)
Address: F05C0H (C0GMCTRL), F0340H (C1GMCTRL)
After reset: 0000H
R/W
(a) Read
C0GMCTRL,
C1GMCTRL
15
14
13
12
11
10
9
8
MBON
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
EFSD
GOM
15
14
13
12
11
10
9
8
0
0
0
0
0
0
(b) Write
C0GMCTRL,
C1GMCTRL
Set
Set
EFSD
GOM
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Clear
GOM
(a) Read
MBON
Bit Enabling Access to Message Buffer Register,
Transmit/Receive History List Registers
0
Write access and read access to the message buffer register and the transmit/receive history list
registers is disabled.
1
Write access and read access to the message buffer register and the transmit/receive history list
registers is enabled.
Cautions 1. While the MBON bit is cleared (to 0), software access to the message buffers
(C0MDB0m, C1MDB0m, C0MDB1m, C1MDB1m, C0MDB01m, C1MDB01m,
C0MDB2m, C1MDB2m, C0MDB3m, C1MDB3m, C0MDB23m, C1MDB23m,
C0MDB4m, C1MDB4m, C0MDB5m, C1MDB5m, C0MDB45m, C1MDB45m,
C0MDB6m, C1MDB6m, C0MDB7m, C1MDB7m, C0MDB67m, C1MDB67m,
C0MDLCm, C1MDLCm, C0MCONFm, C1MCONFm, C0MIDLm, C1MIDLm,
C0MIDHm, C1MIDHm, and C0MCTRLm, C1MCTRLm), or registers related to
transmit history or receive history (C0LOPT, C1LOPT, C0TGPT, C1TGPT,
C0LIPT, C1LIPT, and C0RGPT, C1RGPT) is disabled.
2. This bit is read-only. Even if 1 is written to MBON while it is 0, the value of
MBON does not change, and access to the message buffer registers, or
registers related to transmit history or receive history remains disabled.
Remark MBON bit is cleared (to 0) when the CAN module enters CAN sleep mode/CAN stop
mode or GOM bit is cleared (to 0).
MBON bit is set (to 1) when the CAN sleep mode/the CAN stop mode is released or
GOM bit is set (to 1).
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Figure 14-26. Format of CAN Global Module Control Register (C0GMCTRL, C1GMCTRL) (2/2)
EFSD
Bit Enabling Forced Shut Down
0
Forced shut down by GOM = 0 disabled.
1
Forced shut down by GOM = 0 enabled.
Caution To request forced shutdown, the GOM bit must be cleared to 0 in a subsequent,
immediately following write access after the EFSD bit has been set to 1. If access
to another register (including reading the C0GMCTRL, C1GMCTRL register) is
executed without clearing the GOM bit immediately after the EFSD bit has been
set to 1, the EFSD bit is forcibly cleared to 0, and the forced shutdown request is
invalid.
When DMA is being performed, a request for a forced shut down might be
ignored. Be sure to read the EFSD bit and confirm that forced shut down is
enabled before issuing a forced shut down request. If forced shut down cannot
be enabled because DMA is being performed, it is recommended to temporarily
stop DMA.
GOM
Global Operation Mode Bit
0
CAN module is disabled from operating.
1
CAN module is enabled to operate.
Caution The GOM bit can be cleared only in the initialization mode or immediately after
EFSD bit is set (to 1).
(b) Write
Set EFSD
EFSD Bit Setting
0
No change in EFSD bit.
1
EFSD bit set to 1.
Set GOM
Clear GOM
0
1
GOM bit cleared to 0.
1
0
GOM bit set to 1.
Other than the above
GOM Bit Setting
No change in GOM bit.
Caution Set GOM bit and EFSD bit always separately.
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(3) CAN global module clock select register (C0GMCS, C1GMCS)
The C0GMCS, C1GMCS register is used to select the CAN module system clock.
Figure 14-27. Format of CAN Global Module Clock Select Register (C0GMCS, C1GMCS)
Address: F05CEH (C0GMCS), F0342H (C1GMCS)
C0GMCS,
C1GMCS
After reset: 0FH
R/W
7
6
5
4
3
2
1
0
0
0
0
0
CCP3
CCP2
CCP1
CCP0
CAN Module System Clock (fCANMOD)
CCP3
CCP2
CCP1
CCP1
0
0
0
0
fCAN/1
0
0
0
1
fCAN/2
0
0
1
0
fCAN/3
0
0
1
1
fCAN/4
0
1
0
0
fCAN/5
0
1
0
1
fCAN/6
0
1
1
0
fCAN/7
0
1
1
1
fCAN/8
1
0
0
0
fCAN/9
1
0
0
1
fCAN/10
1
0
1
0
fCAN/11
1
0
1
1
fCAN/12
1
1
0
0
fCAN/13
1
1
0
1
fCAN/14
1
1
1
0
fCAN/15
1
1
1
1
fCAN/16 (Default value)
Remark
fCAN: Clock supplied to CAN (fMAIN)
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(4) CAN global automatic block transmission control register (C0GMABT, C1GMABT)
The C0GMABT, C1GMABT register is used to control the automatic block transmission (ABT) operation.
Figure 14-28. Format of CAN Global Automatic Block Transmission Control Register
(C0GMABT, C1GMABT) (1/2)
Address: F05C6H (C0GMABT), F0346H (C1GMABT)
After reset: 0000H
R/W
(a) Read
C0GMABT,
C1GMABT
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
15
14
13
12
11
10
0
0
0
0
0
0
ABTCLR ABTTRG
(b) Write
C0GMABT,
C1GMABT
9
8
Set
Set
ABTCLR ABTTRG
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Clear
ABTTRG
Caution Before changing the normal operation mode with ABT to the initialization mode,
be sure to set the C0GMABT, C1GMABT register to the default value (0000H)
and confirm the C0GMABT, C1GMABT register is surely initialized to the default
value (0000H).
(a) Read
ABTCLR
Automatic Block Transmission Engine Clear Status Bit
0
Clearing the automatic transmission engine is completed.
1
The automatic transmission engine is being cleared.
Remarks 1.
Set the ABTCLR bit to 1 while the ABTTRG bit is cleared (0).
The operation is not guaranteed if the ABTCLR bit is set to 1 while the ABTTRG
bit is set to 1.
2.
When the automatic block transmission engine is cleared by setting the ABTCLR
bit to 1, the ABTCLR bit is automatically cleared to 0 as soon as the requested
clearing processing is complete.
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Figure 14-28. Format of CAN Global Automatic Block Transmission Control Register
(C0GMABT, C1GMABT) (2/2)
ABTTRG
Automatic Block Transmission Status Bit
0
Automatic block transmission is stopped.
1
Automatic block transmission is under execution.
Caution Do not set the ABTTRG bit (ABTTRG = 1) in the initialization mode. If the
ABTTRG bit is set in the initialization mode, the operation is not guaranteed
after the CAN module has entered the normal operation mode with ABT.
Do not set the ABTTRG bit (1) while the C0CTRL.TSTAT.TSTAT, C1CTRL.TSTAT
bit is set (1). Confirm TSTAT = 0 directly in advance before setting ABTTRG bit.
(b) Write
Set ABTCLR
0
Automatic Block Transmission Engine Clear Request Bit
The automatic block transmission engine is in idle state or under operation.
1
Request to clear the automatic block transmission engine. After the automatic block
transmission engine has been cleared, automatic block transmission is started from
message buffer 0 by setting the ABTTRG bit to 1.
Set ABTTRG
Clear ABTTRG
0
1
Request to stop automatic block transmission.
1
0
Request to start automatic block transmission.
Other than the above
Automatic Block Transmission Start Bit
No change in ABTTRG bit.
Caution While receiving a message from another node or transmitting the messages other
than the ABT messages (message buffer 8 to 15), there is a possibility not to
begin immediately the transmission even if the ABTTRG bit is set to 1.
Transmission is not aborted even if the ABTTRG bit is cleared to 0, until the
transmission of the ABT message, which is currently being transmitted is
completed (successfully or not). After that, the transmission is aborted.
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(5) CAN global automatic block transmission delay setting register (C0GMABTD, C1GMABTD)
The C0GMABTD, C1GMABTD register is used to set the interval at which the data of the message buffer
assigned to ABT is to be transmitted in the normal operation mode with ABT.
Figure 14-29. Format of CAN Global Automatic Block Transmission Delay Setting Register
(C0GMABTD, C1GMABTD)
Address: F05C8H (C0GMABTD), F0348H (C1GMABTD)
C0GMABTD,
C1GMABTD
After reset: 00H
7
6
5
4
3
2
1
0
0
0
0
0
ABTD3
ABTD2
ABTD1
ABTD0
ABTD3
ABTD2
ABTD1
ABTD0
0
0
0
0
0 DBT (default value)
0
0
0
1
2 DBT
0
0
1
0
2 DBT
0
0
1
1
2 DBT
0
1
0
0
2 DBT
0
1
0
1
2 DBT
0
1
1
0
2 DBT
0
1
1
1
2 DBT
1
0
0
0
2 DBT
Other than the above
Cautions 1.
R/W
Data frame interval during automatic block transmission
(unit: Data bit time (DBT))
5
6
7
8
9
10
11
12
Setting prohibited
Do not change the contents of the C0GMABTD, C1GMABTD register while the
ABTTRG bit is set to 1.
2.
The timing at which the ABT message is actually transmitted onto the CAN
bus differs depending on the status of transmission from the other station or
how a request to transmit a message other than an ABT message (message
buffers 8 to 15) is made.
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(6) CAN module mask register (C0MASKaL, C1MASKaL, C0MASKaH, C1MASKaH)
(a = 1, 2, 3, or 4)
The C0MASKaL, C1MASKaL and C0MASKaH, C1MASKaH registers are used to extend the number of
receivable messages into the same message buffer by masking part of the ID comparison of a message and
invalidating the ID of the masked part.
Figure 14-30. Format of CAN Module Mask Register
(C0MASKaL, C1MASKaL, C0MASKaH, C1MASKaH) (a = 1, 2, 3, or 4) (1/2)
- CAN Module Mask 1 Register
(C0MASK1L, C1MASK1L, C0MASK1H, C1MASK1H)
Address: F05D0H (C0MASK1L), F05D2H (C0MASK1H)
Address: F0380H (C1MASK1L), F0382H (C1MASK1H)
15
C0MASK1L,
C1MASK1L
14
13
12
After reset: Undefined
After reset: Undefined
11
R/W
10
CMID15 CMID14 CMID13 CMID12 CMID11 CMID10
R/W
9
8
CMID9
CMID8
7
6
5
4
3
2
1
0
CMID7
CMID6
CMID5
CMID4
CMID3
CMID2
CMID1
CMID0
12
11
10
9
8
15
14
13
C0MASK1H/
0
0
0
MASK1H,
C1MASK1H
7
6
5
CMID28 CMID27 CMID26 CMID25 CMID24
4
3
2
1
0
CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16
- CAN Module Mask 2 Register
(C0MASK2L, C1MASK2L, C0MASK2H, C1MASK2H)
Address: F05D4H (C0MASK2L), F05D6H (C0MASK2H)
Address: F0384H (C1MASK2L), F0386H (C1MASK2H)
15
C0MASK2L,
C1MASK2L
C0MASK2H,
14
13
12
After reset: Undefined
After reset: Undefined
11
10
CMID15 CMID14 CMID13 CMID12 CMID11 CMID10
R/W
R/W
9
8
CMID9
CMID8
7
6
5
4
3
2
1
0
CMID7
CMID6
CMID5
CMID4
CMID3
CMID2
CMID1
CMID0
15
14
13
12
11
10
9
8
0
0
0
7
6
5
CMID28 CMID27 CMID26 CMID25 CMID24
C1MASK2H
4
3
2
1
0
CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16
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Figure 14-30. Format of CAN Module Mask Register
(C0MASKaL, C1MASKaL, C0MASKaH, C1MASKaH) (a = 1, 2, 3, or 4) (2/2)
- CAN Module Mask 3 Register
(C0MASK3L, C1MASK3L, C0MASK3H, C1MASK3H)
Address: F05D8H (C0MASK3L), F05DAH (C0MASK3H)
Address: F0388H (C1MASK3L), F038AH (C1MASK3H)
15
C0MASK3L,
C1MASK3L
C0MASK3H,
14
13
After reset: Undefined
After reset: Undefined
12
11
R/W
10
CMID15 CMID14 CMID13 CMID12 CMID11 CMID10
R/W
9
8
CMID9
CMID8
7
6
5
4
3
2
1
0
CMID7
CMID6
CMID5
CMID4
CMID3
CMID2
CMID1
CMID0
15
14
13
12
11
10
9
8
0
0
0
7
6
5
CMID28 CMID27 CMID26 CMID25 CMID24
C1MASK3H
4
3
2
1
0
CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16
- CAN Module Mask 4 Register
(C0MASK4L, C1MASK4L, C0MASK4H, C1MASK4H)
Address: F05DCH (C0MASK4L), F05DEH (C0MASK4H)
Address: F038CH (C1MASK4L), F038EH (C1MASK4H)
15
C0MASK4L,
C1MASK4L
C0MASK4H,
14
13
12
After reset: Undefined
After reset: Undefined
11
10
CMID15 CMID14 CMID13 CMID12 CMID11 CMID10
R/W
R/W
9
8
CMID9
CMID8
7
6
5
4
3
2
1
0
CMID7
CMID6
CMID5
CMID4
CMID3
CMID2
CMID1
CMID0
15
14
13
12
11
10
9
8
0
0
0
7
6
5
CMID28 CMID27 CMID26 CMID25 CMID24
C1MASK4H
4
3
2
1
0
CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16
CMID28-CMID0
Sets Mask Pattern of ID Bit.
0
The ID bits of the message buffer set by the CMID28 to CMID0 bits are compared with
the ID bits of the received message frame.
1
The ID bits of the message buffer set by the CMID28 to CMID0 bits are not compared
with the ID bits of the received message frame (they are masked).
Remark Masking is always defined by an ID length of 29 bits. If a mask is assigned to a message
with a standard ID, CMID17 to CMID0 are ignored. Therefore, only CMID28 to CMID18
of the received ID are masked. The same mask can be used for both the standard and
extended IDs.
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(7) CAN module control register (C0CTRL, C1CTRL)
The C0CTRL, C1CTRL register is used to control the operation mode of the CAN module.
Figure 14-31. Format of CAN Module Control Register (C0CTRL, C1CTRL) (1/4)
Address: F05E0H (C0CTRL), F0390H (C1CTRL)
After reset: 0000H
R/W
(a) Read
C0CTRL,
C1CTRL
15
14
13
12
11
10
9
8
0
0
0
0
0
0
RSTAT
TSTAT
7
6
5
4
3
2
1
0
CCERC
AL
VALID
15
14
13
Set
CCERC
Set
AL
0
7
6
5
Clear
Clear
Clear
CCERC
AL
VALID
PSMODE1 PSMODE0 OPMODE2 OPMODE1 OPMODE0
(b) Write
C0CTRL,
C1CTRL
12
11
10
9
8
Set
Set
Set
Set
Set
PSMODE1 PSMODE0 OPMODE2 OPMODE1 OPMODE0
4
3
2
1
0
Clear
Clear
Clear
Clear
Clear
PSMODE1 PSMODE0 OPMODE2 OPMODE1 OPMODE0
(a) Read
RSTAT
Reception Status Bit
0
Reception is stopped.
1
Reception is in progress.
Remark - The RSTAT bit is set to 1 under the following conditions (timing).
- The SOF bit of a receive frame is detected
- On occurrence of arbitration loss during a transmit frame
- The RSTAT bit is cleared to 0 under the following conditions (timing)
- When a recessive level is detected at the second bit of the interframe space
- On transition to the initialization mode at the first bit of the interframe space
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Figure 14-31. Format of CAN Module Control Register (C0CTRL, C1CTRL) (2/4)
TSTAT
Transmission Status Bit
0
Transmission is stopped.
1
Transmission is in progress.
Remark - The TSTAT bit is set to 1 under the following conditions (timing).
- The SOF bit of a transmit frame is detected
- The TSTAT bit is cleared to 0 under the following conditions (timing).
- During transition to bus-off state
- On occurrence of arbitration loss in transmit frame
- On detection of recessive level at the second bit of the interframe space
- On transition to the initialization mode at the first bit of the interframe space
CCERC
Error Counter Clear Bit
0
The C0ERC, C1ERC and C0INFO, C1INFO registers are not cleared in the initialization mode.
1
The C0ERC, C1ERC and C0INFO, C1INFO registers are cleared in the initialization mode.
Remarks 1.
The CCERC bit is used to clear the C0ERC, C1ERC and C0INFO, C1INFO registers for
re-initialization or forced recovery from the bus-off state. This bit can be set to 1 only
in the initialization mode.
2.
When the C0ERC, C1ERC and C0INFO, C1INFO registers have been cleared, the
3.
The CCERC bit can be set to 1 at the same time as a request to change the
4.
The receive data may be corrupted in case of setting the CCERC bit to (1)
CCERC bit is also cleared to 0 automatically.
initialization mode to an operation mode is made.
immediately after entering the INIT mode from self-test mode.
AL
Bit to Set Operation in Case of Arbitration Loss
0
Re-transmission is not executed in case of an arbitration loss in the single-shot mode.
1
Re-transmission is executed in case of an arbitration loss in the single-shot mode.
Remark The AL bit is valid only in the single-shot mode.
VALID
Valid Receive Message Frame Detection Bit
0
A valid message frame has not been received since the VALID bit was last cleared to 0.
1
A valid message frame has been received since the VALID bit was last cleared to 0.
Remarks 1.
Detection of a valid receive message frame is not dependent upon storage in the
receive message buffer (data frame) or transmit message buffer (remote frame).
2.
Clear the VALID bit (0) before changing the initialization mode to an operation mode.
3.
If only two CAN nodes are connected to the CAN bus with one transmitting a
message frame in the normal operation mode and the other in the receive-only mode,
the VALID bit is not set to 1 before the transmitting node enters the error passive
state, because in receive-only mode no acknowledge is generated.
4.
In order to clear the VALID bit, set the Clear VALID bit to 1 first and confirm that the
VALID bit is cleared. If it is not cleared, perform clearing processing again.
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Figure 14-31. Format of CAN Module Control Register (C0CTRL, C1CTRL) (3/4)
PSMODE1 PSMODE0
Power Save Mode
0
0
No power save mode is selected.
0
1
CAN sleep mode
1
0
Setting prohibited
1
1
CAN stop mode
Cautions 1. Transition to and from the CAN stop mode must be made via CAN sleep mode.
A request for direct transition to and from the CAN stop mode is ignored.
2. The MBON flag of C0GMCTRL, C1GMCTRL must be checked after releasing a
power save mode, prior to access the message buffers again.
3. CAN Sleep mode requests are kept pending, until cancelled by software or
entered on appropriate bus condition (bus idle). Software can check the actual
status by reading PSMODE.
OPMODE2 OPMODE1 OPMODE0
Operation Mode
0
0
0
No operation mode is selected (CAN module is in the initialization mode).
0
0
1
Normal operation mode
0
1
0
Normal operation mode with automatic block transmission function
(normal operation mode with ABT)
0
1
1
Receive-only mode
1
0
0
Single-shot mode
1
0
1
Self-test mode
Other than the above
Setting prohibited
Caution Transit to initialization mode or power saving modes may take some time. Be sure
to verify the success of mode change by reading the values, before proceeding.
Remark The OPMODE[2:0] bits are read-only in the CAN sleep mode or CAN stop mode.
(b)Write
Set CCERC
Setting of CCERC Bit
1
CCERC bit is set to 1.
0
CCERC bit is not changed.
Set AL
Clear AL
0
1
AL bit is cleared to 0.
1
0
AL bit is set to 1.
Other than the above
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AL bit is not changed.
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Figure 14-31. Format of CAN Module Control Register (C0CTRL, C1CTRL) (4/4)
Clear VALID
Setting of VALID Bit
0
VALID bit is not changed.
1
VALID bit is cleared to 0.
Set
Clear
PSMODE0
PSMODE0
0
1
PSMODE0 bit is cleared to 0.
1
0
PSMODE bit is set to 1.
Other than the above
Setting of PSMODE0 Bit
PSMODE0 bit is not changed.
Set
Clear
PSMODE1
PSMODE1
0
1
PSMODE1 bit is cleared to 0.
1
0
PSMODE1 bit is set to 1.
Other than the above
Setting of PSMODE1 Bit
PSMODE1 bit is not changed.
Set
Clear
OPMODE0
OPMODE0
0
1
OPMODE0 bit is cleared to 0.
1
0
OPMODE0 bit is set to 1.
Other than the above
Setting of OPMODE0 Bit
OPMODE0 bit is not changed.
Set
OPMODE1
Clear
OPMODE1
0
1
OPMODE1 bit is cleared to 0.
1
0
OPMODE1 bit is set to 1.
Other than the above
Setting of OPMODE1 Bit
OPMODE1 bit is not changed.
Set
Clear
OPMODE2
OPMODE2
0
1
OPMODE2 bit is cleared to 0.
1
0
OPMODE2 bit is set to 1.
Other than the above
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OPMODE2 bit is not changed.
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(8) CAN module last error code register (C0LEC, C1LEC)
The C0LEC, C1LEC register provides the error information of the CAN protocol.
Figure 14-32. Format of CAN Module Last Error Code Register (C0LEC, C1LEC)
Address: F05E2H (C0LEC), F0392H (C1LEC)
C0LEC,
C1LEC
Remarks 1.
After reset: 00H
R/W
7
6
5
4
3
2
1
0
0
0
0
0
0
LEC2
LEC1
LEC0
The contents of the C0LEC, C1LEC register are not cleared when the CAN module
changes from an operation mode to the initialization mode.
2.
If an attempt is made to write a value other than 00H to the C0LEC, C1LEC register
by software, the access is ignored.
LEC2
LEC1
LEC0
Last CAN Protocol Error Information
0
0
0
No error
0
0
1
Stuff error
0
1
0
Form error
0
1
1
ACK error
1
0
0
Bit error (The CAN module tried to transmit a recessive-level bit as part of
a transmit message (except the arbitration field), but the value on the CAN
bus is a dominant-level bit.)
1
0
1
Bit error (The CAN module tried to transmit a dominant-level bit as part of
a transmit message, ACK bit, error frame, or overload frame, but the value
on the CAN bus is a recessive-level bit.)
1
1
0
CRC error
1
1
1
Undefined
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(9) CAN module information register (C0INFO, C1INFO)
The C0INFO, C1INFO register indicates the status of the CAN module.
Figure 14-33. Format of CAN Module Information Register (C0INFO, C1INFO)
Address: F05E3H (C0INFO), F0393H (C1INFO)
C0INFO,
C1INFO
After reset: 00H
R
7
6
5
4
3
2
1
0
0
0
0
BOFF
TECS1
TECS0
RECS1
RECS0
BOFF
Bus-off State Bit
0
Not bus-off state (transmit error counter 255) (The value of the transmit counter is less than 256.)
1
Bus-off state (transmit error counter > 255) (The value of the transmit counter is 256 or more.)
TECS1
TECS0
Transmission Error Counter Status Bit
0
0
The value of the transmission error counter is less than that of the warning level ( DMA channel 1 > DMA channel 2 > DMA channel 3.
If a DMA request and an interrupt request are generated at the same time, the DMA transfer takes precedence,
and then interrupt servicing is executed.
(2) DMA response time
The response time of DMA transfer is as follows.
Table 20-2. Response Time of DMA Transfer
Minimum Time
Response time
3 clocks
Maximum Time
10 clocks
Note
Note The maximum time necessary to execute an instruction from internal RAM is 16 clock cycles.
Cautions 1. The above response time does not include the two clock cycles required for a DMA
transfer.
2. When executing a DMA pending instruction (see 20.6 (4)), the maximum response
time is extended by the execution time of that instruction to be held pending.
3. Do not specify successive transfer triggers for a channel within a period equal to the
maximum response time plus one clock cycle, because they might be ignored.
Remark
1 clock: 1/fCLK (fCLK: CPU clock)
(3) Operation in standby mode
The DMA controller operates as follows in the standby mode.
Table 20-3. DMA Operation in Standby Mode
Status
HALT mode
STOP mode
DMA Operation
Normal operation
Stops operation.
If DMA transfer and STOP instruction execution contend, DMA transfer may be
damaged. Therefore, stop DMA before executing the STOP instruction.
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(4) DMA pending instruction
Even if a DMA request is generated, DMA transfer is held pending immediately after the following instructions.
CALL
!addr16
CALL
$!addr20
CALL
!!addr20
CALL
rp
CALLT
[addr5]
BRK
MOV PSW, #byte
MOV PSW, A
MOV1 PSW. bit, CY
SET1 PSW. bit
CLR1 PSW. bit
POP PSW
BTCLR PSW. bit, $addr20
EI
DI
Write instructions for registers IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, MK0L, MK0H, MK1L, MK1H,
MK2L,MK2H, MK3L, PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L,
PR11H,PR12L, PR12H, and PR13L each.
Instruction for accessing the data flash memory
(5) Operation if address in general-purpose register area or other than those of internal RAM area is specified
The address indicated by DMA RAM address register n (DRAn) is incremented during DMA transfer. If the
address is incremented to an address in the general-purpose register area or exceeds the area of the internal
RAM, the following operation is performed.
In mode of transfer from SFR to RAM
The data of that address is lost.
In mode of transfer from RAM to SFR
Undefined data is transferred to SFR.
In either case, malfunctioning may occur or damage may be done to the system. Therefore, make sure that the
address is within the internal RAM area other than the general-purpose register area.
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose registers
Internal RAM
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CHAPTER 20 DMA CONTROLLER
(6) Operation if instructions for accessing the data flash area
Because DMA transfer is suspended to access to the data flash area, be sure to add the DMA pending
instruction.
If the data flash area is accessed after an next instruction execution from start of DMA transfer, a 3-clock wait
will be inserted to the next instruction.
Instruction 1
DMA transfer
Instruction 2
←The wait of three clock cycles occurs.
MOV A, ! DataFlash area
The data flash should be read in either of following ways.
- Use the flash library provided by Renesas (EEL (Pack01) version V1.13 or later).
- Stop the DMA transfer before reading.
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CHAPTER 21 INTERRUPT FUNCTIONS
CHAPTER 21 INTERRUPT FUNCTIONS
The interrupt function switches the program execution to other processing. When the branch processing is finished, the
program returns to the interrupted processing.
The number of interrupt sources differs, depending on the product.
R5F10CGx R5F10DGx R5F10CLx R5F10DLx R5F10CMx R5F10CMx R5F10TPx R5F10DPJ R5F10DSx
R5F10DPx
Maskable External
interrupts Internal
6
39
8
43
53
26
42
26
49
53
53
21.1 Interrupt Function Types
The following two types of interrupt functions are used.
(1) Maskable interrupts
These interrupts undergo mask control. Maskable interrupts can be divided into four priority groups by setting the
priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR03H, PR10L, PR10H,
PR11L, PR11H, PR12L, PR12H, PR13L, PR13H).
Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. If two
or more interrupt requests, each having the same priority, are simultaneously generated, then they are processed
according to the priority of vectored interrupt servicing. For the priority order, see Table 21-1.
A standby release signal is generated and STOP, HALT, and SNOOZE modes are released.
External interrupt requests and internal interrupt requests are provided as maskable interrupts.
(2) Software interrupt
This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even when interrupts are
disabled. The software interrupt does not undergo interrupt priority control.
21.2 Interrupt Sources and Configuration
Interrupt sources include maskable interrupts and software interrupts. In addition, they also have up to eight reset
sources (see Table 21-1). The vector codes that store the program start address when branching due to the generation of
a reset or various interrupt requests are two bytes each, so interrupts jump to a 64 K address of 00000H to 0FFFFH.
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–
–
R5F10DSx
R5F10DPJ
(A)
R5F10DPx, R5F10TPJ
00004H
R5F10DMx
Internal
(75% of overflow time+1/2fIL)
R5F10CMx
Watchdog timer interval Note2
address
R5F10DLx
INTWDTI
Trigger
Vector
table
R5F10CLx
0
Name
Internal/
External
R5F10DGx
Note1
Maskable
Interrupt Source
Default
priority
R5F10CGx
Type
Basic Configuration
type
Table 21-1. Interrupt Source List (1/2)
1
INTLVI
Voltage detection Note 3
Internal
00006H
2
INTP0
External Interrupt 0
External
00008H
3
INTP1
External Interrupt 1
External
0000AH
4
INTP2
External Interrupt 2
External
0000CH
5
INTP3
External Interrupt 3
External
0000EH
6
INTP4
External Interrupt 4
External
00010H
7
INTP5
External Interrupt 5
External
00012H
8
INTCLM
Clock Monitor interrupt
Internal
00014H
9
INTCSI00
End of CSI00 communication
Internal
00016H
INTST0
UART0 of SAU0 transmission interrupt
–
–
–
–
–
–
–
–
INTCSI01
End of CSI01 communication
INTSR0
UART0 of SAU0 reception interrupt
–
–
–
–
–
–
–
–
11
INTDMA0
End of DMA0 transfer
Internal
0001AH
12
INTDMA1
End of DMA1 transfer
Internal
0001CH
13
INTRTC
Fixed cycle signal of RTC /Alarm match
detection
Internal
0001EH
10
Internal
(B)
(A)
00018H
14
INTIT
Interval timer interrupt
Internal
00020H
15
INTLT0
LIN-UART0(UARTF0) transmission interrupt
Internal
00022H
–
–
16
INTLR0
LIN-UART0(UARTF0) reception interrupt
Internal
00024H
–
–
17
INTLS0
LIN-UART0(UARTF0) reception status interrupt
Internal
00026H
–
–
18
INTPLR0
LIN-UART0(UARTF0) reception pin input
External
00028H
(B)
–
–
19
INTSG
Interrupt from SG in ALD mode
Internal
0002AH
(A)
20
INTTM00
End of TAU 00 count or capture interrupt
Internal
0002CH
21
INTTM01
End of TAU 01 count or capture interrupt
Internal
0002EH
22
INTTM02
End of TAU 02 count or capture interrupt
Internal
00030H
23
INTTM03
End of TAU 03 count or capture interrupt
Internal
00032H
24
INTAD
End of A/D conversion
Internal
00034H
25
INTLT1
LIN-UART1(UARTF1) transmission interrupt
Internal
00036H
26
INTLR1
LIN-UART1(UARTF1) reception interrupt
Internal
00038H
27
INTLS1
LIN-UART1(UARTF1) reception status interrupt
Internal
0003AH
28
INTPLR1
LIN-UART1(UARTF1) reception pin input
External
0003CH
(B)
29
INTCSI10
End of CSI10 communication
Internal
0003EH
(A)
–
–
–
–
–
–
30
INTIIC11
End of IIC11 communication
Internal
00040H
31
INTTM04
End of TAU 04 count or capture interrupt
Internal
00042H
32
INTTM05
End of TAU 05 count or capture interrupt
Internal
00044H
33
INTTM06
End of TAU 06 count or capture interrupt
Internal
00046H
34
INTTM07
End of TAU 07 count or capture interrupt
Internal
00048H
Notes 1.
The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. Zero indicates the highest priority and 60 indicates the lowest priority.
2.
When bit 7 (WDTINT) of the option byte (000C0H) is set to 1.
3
When bit 7 (LVIMD) of the voltage detection level register (LVIS) is cleared to 0.
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Table 21-1. Interrupt Source List (2/2)
R5F10CMx
R5F10DMx
R5F10DPx, R5F10TPJ
R5F10DPJ
(A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0004EH
–
–
–
address
Maskable
35
INTC1ERR
CAN1 error interrupt
Internal
0004AH
36
INTC1WUP
CAN1 wakeup
Internal
0004CH
37
INTC0ERR
CAN0 error interrupt
Internal
R5F10DSx
R5F10DLx
Trigger
Vector
table
R5F10CLx
Name
Internal/
External
R5F10DGx
Note1
Interrupt Source
R5F10CGx
Default
priority
Basic Configuration
type
Type
38
INTC0WUP
CAN0 wakeup
Internal
00050H
–
–
–
39
INTC0REC
CAN0 reception completion
Internal
00052H
–
–
–
40
INTC0TRX
CAN0 transmission completion
Internal
00054H
–
–
–
41
INTTM10
End of TAU 10 count or capture interrupt
Internal
00056H
42
INTTM11
End of TAU 11 count or capture interrupt
Internal
00058H
43
INTTM12
End of TAU 12 count or capture interrupt
Internal
0005AH
44
INTTM13
End of TAU 13 count or capture interrupt
Internal
0005CH
45
INTMD
End of division operation/Overflow occur
Internal
0005EH
46
INTC1REC
CAN1 reception completion
Internal
00060H
–
–
–
–
–
–
–
47
INTFL
End of sequencer interrupt(Flash programming)
Internal
00062H
48
INTC1TRX
CAN1 transmission completion
Internal
00064H
–
–
–
–
–
–
–
49
INTTM14
End of TAU 14 count or capture interrupt
Internal
00066H
50
INTTM15
End of TAU 15 count or capture interrupt
Internal
00068H
51
INTTM16
End of TAU 16 count or capture interrupt
Internal
0006AH
52
INTTM17
End of TAU 17 count or capture interrupt
Internal
0006CH
53
INTTM20
End of TAU 20 count or capture interrupt
Internal
0006EH
54
INTTM21
End of TAU 21 count or capture interrupt
Internal
00070H
55
INTTM22
End of TAU 22 count or capture interrupt
Internal
00072H
56
INTTM23
End of TAU 23 count or capture interrupt
Internal
0074H
57
INTTM24
End of TAU 24 count or capture interrupt
Internal
0076H
58
INTTM26
End of TAU 26 count or capture interrupt
Internal
0078H
59
INTDMA2
End of DMA2 transfer
Internal
007AH
–
–
–
–
–
–
60
INTDMA3
End of DMA3 transfer
Internal
007CH
–
–
–
–
–
–
-
007EH
(C)
-
0000H
-
Software
-
BRK
Execution of BRK instruction
Reset
-
RESET
RESET pin input
POR
Power-on-reset
____________
LVD
Voltage detection
WDT
Overflow of watchdog timer
Note
TRAP
Execution of illegal instruction
IAW
Illegal-memory access
RPE
RAM parity error
Note The default priority determines the sequence of interrupts if two or more maskable interrupts occur simultaneously.
Zero indicates the highest priority and 60 indicates the lowest priority.
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CHAPTER 21 INTERRUPT FUNCTIONS
Figure 21-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal maskable interrupt
Internal bus
MK
Interrupt
request
IE
PR1
PR0
ISP1
ISP0
Vector table
address generator
Priority controller
IF
Standby release
signal
(B) External maskable interrupt (INTPn)
Internal bus
External interrupt edge
enable register
(EGP, EGN)
INTPn pin input
Edge
detector
MK
IF
IE
PR1
PR0
Priority controller
ISP1
ISP0
Vector table
address generator
Standby release
signal
IF:
Interrupt request flag
IE:
Interrupt enable flag
ISP0:
In-service priority flag 0
ISP1:
In-service priority flag 1
MK:
Interrupt mask flag
PR0:
Priority specification flag 0
PR1:
Priority specification flag 1
INTPn = INTP0 to INTP5, INTPLR0, INTPLR1
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CHAPTER 21 INTERRUPT FUNCTIONS
Figure 21-1. Basic Configuration of Interrupt Function (2/2)
(C) Software interrupt
Internal bus
Interrupt
request
IF:
Interrupt request flag
IE:
Interrupt enable flag
ISP0:
In-service priority flag 0
ISP1:
In-service priority flag 1
MK:
Interrupt mask flag
PR0:
Priority specification flag 0
PR1:
Priority specification flag 1
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CHAPTER 21 INTERRUPT FUNCTIONS
21.3 Registers Controlling Interrupt Functions
The following 6 types of registers are used to control the interrupt functions.
Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, IF3H)
Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L, MK3H)
Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR03H, PR10L,
PR10H, PR11L, PR11H, PR12L, PR12H, PR13L, PR13H)
External interrupt rising edge enable register 0 (EGP0)
External interrupt falling edge enable register 0 (EGN0)
Program status word (PSW)
Table 21-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to
interrupt request sources.
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CHAPTER 21 INTERRUPT FUNCTIONS
Table 21-2. Flags Corresponding to Interrupt Request Sources
Name
INTWDTI
Interrupt Request Flag
WDTIIF
Register
IF0
Interrupt Mask Flag
IF0L
Bit
0 WDTIMK
Priority Specification Flag0
Register
MK0
MK0L
Bit
0 WDTIPR0
Register
PR00
Priority Specification Flag1
PR00L
Bit
0 WDTIPR1
Register
PR10
PR10L
Bit
0
INTLVI
LVIIF
1
LVIMK
1
LVIPR0
1
LVIPR1
1
INTP0
PIF0
2
PMK0
2
PPR00
2
PPR10
2
INTP1
PIF1
3
PMK1
3
PPR01
3
PPR11
3
INTP2
PIF2
4
PMK2
4
PPR02
4
PPR12
4
INTP3
PIF3
5
PMK3
5
PPR03
5
PPR13
5
INTP4
PIF4
6
PMK4
6
PPR04
6
PPR14
6
INTP5
PIF5
7
PMK5
7
PPR05
7
PPR15
INTCLM
CLMIF
0
CLMMK
0
CLMPR0
0
CLMPR1
INTCSI00
CSIIF00
1
CSIMK00
1
CSIPR000
1
CSIPR100
INTST0
STIF0
INTCSI01
CSIIF01
INTSR0
SRIF0
INTDMA0
DMAIF0
3
DMAMK0
3
DMAPR00
3
DMAPR10
INTDMA1
DMAIF1
4
DMAMK1
4
DMAPR01
4
DMAPR11
4
INTRTC
RTCIF
5
RTCMK
5
RTCPR0
5
RTCPR1
5
INTIT
ITIF
6
ITMK
6
ITPR0
6
ITPR1
6
INTLT0
LTIF0
7
LTMK0
7
LTPR00
7
LTPR10
7
INTLR0
LRIF0
0
LRMK0
0
LRPR00
0
LRPR10
INTLS0
LSIF0
1
LSMK0
1
LSPR00
1
LSPR10
1
INTPLR0
PIFLR0
2
PMKLR0
2
PPR0LR0
2
PPR1LR0
2
INTSG
SGIF
3
SGMK
3
SGPR0
3
SGPR1
3
INTTM00
TMIF00
4
TMMK00
4
TMPR000
4
TMPR100
4
IF0H
MK0H
STMK0
2
STPR00
2
CSIMK01
SRMK0
IF1
IF1L
PR00H
MK1L
0
1
STPR10
2
CSIPR001
SRPR00
MK1
7
PR10H
2
CSIPR101
SRPR10
PR01
PR01L
3
PR11
PR11L
0
INTTM01
TMIF01
5
TMMK01
5
TMPR001
5
TMPR101
5
INTTM02
TMIF02
6
TMMK02
6
TMPR002
6
TMPR102
6
INTTM03
TMIF03
7
TMMK03
7
TMPR003
7
TMPR103
INTAD
ADIF
0
ADMK
0
ADPR0
0
ADPR1
INTLT1
LTIF1
1
LTMK1
1
LTPR01
1
LTPR11
1
INTLR1
LRIF1
2
LRMK1
2
LRPR01
2
LRPR11
2
IF1H
MK1H
PR01H
0
7
PR11H
0
INTLS1
LSIF1
3
LSMK1
3
LSPR01
3
LSPR11
3
INTPLR1
PIFLR1
4
PMKLR1
4
PPR0LR1
4
PPR1LR1
4
INTCSI10
CSIIF10
5
CSIMK10
5
CSIPR010
5
CSIPR110
5
INTIIC11
IICIF11
6
IICMK11
6
IICPR011
6
IICPR111
6
INTTM04
TMIF04
7
TMMK04
7
TMPR004
7
TMPR104
7
INTTM05
TMIF05
0
TMMK05
0
TMPR005
0
TMPR105
INTTM06
TMIF06
1
TMMK06
1
TMPR006
1
TMPR106
1
INTTM07
TMIF07
2
TMMK07
2
TMPR007
2
TMPR107
2
INTC1ERR C1ERRIF
3
C1ERRMK
3
C1ERRPR0
3
C1ERRPR1
3
INTC1WUP C1WUPIF
4
C1WUPMK
4
C1WUPPR0
4
C1WUPPR1
4
INTC0ERR C0ERRIF
5
C0ERRMK
5
C0ERRPR0
5
C0ERRPR1
5
INTC0WUP C0WUPIF
6
C0WUPMK
6
C0WUPPR0
6
C0WUPPR1
6
INTC0REC C0RECIF
7
C0RECMK
7
C0RECPR0
7
C0RECPR1
0
C0TRXMK
0
C0TRXPR0
0
C0TRXPR1
IF2
IF2L
MK2
MK2L
PR02
PR02L
PR12
PR12L
0
7
INTC0TRX
C0TRXIF
INTTM10
TMIF10
1
TMMK10
1
TMPR010
1
TMPR110
1
INTTM11
TMIF11
2
TMMK11
2
TMPR011
2
TMPR111
2
INTTM12
TMIF12
3
TMMK12
3
TMPR012
3
TMPR112
3
INTTM13
TMIF13
4
TMMK13
4
TMPR013
4
TMPR113
4
INTMD
MDIF
5
MDMK
5
MDPR0
5
MDPR1
5
INTC1REC C1RECIF
6
C1RECMK
6
C1RECPR0
6
C1RECPR1
6
INTFL
FLIF
7
FLMK
7
FLPR0
7
FLPR1
INTC1TRX
C1TRXIF
0
C1TRXMK
0
C1TRXPR0
0
C1TRXPR1
INTTM14
TMIF14
1
TMMK14
1
TMPR014
1
TMPR114
1
INTTM15
TMIF15
2
TMMK15
2
TMPR015
2
TMPR115
2
INTTM16
TMIF16
3
TMMK16
3
TMPR016
3
TMPR116
3
INTTM17
TMIF17
4
TMMK17
4
TMPR017
4
TMPR117
4
INTTM20
TMIF20
5
TMMK20
5
TMPR020
5
TMPR120
5
INTTM21
TMIF21
6
TMMK21
6
TMPR021
6
TMPR121
6
INTTM22
TMIF22
7
TMMK22
7
TMPR022
7
TMPR122
INTTM23
TMIF23
0
TMMK23
0
TMPR023
0
TMPR123
INTTM24
TMIF24
1
TMMK24
1
TMPR024
1
TMPR124
1
2
IF2H
IF3
IF3L
IF3H
MK2H
MK3
MK3L
MK3H
PR02H
PR03
PR03L
PR03H
PR12H
0
7
PR13
PR13L
0
7
PR13H
0
INTTM26
TMIF26
2
TMMK26
2
TMPR026
2
TMPR126
INTDMA2
DMAIF2
3
DMAMK2
3
DMAPR02
3
DMAPR12
3
INTDMA3
DMAIF3
4
DMAMK3
4
DMAPR03
4
DMAPR13
4
-
0
5
1
5
1
5
1
5
-
0
6
1
6
1
6
1
6
-
0
7
1
7
1
7
1
7
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(1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, IF3H)
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is
executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or
upon reset signal generation.
When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is
entered.
The IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, and IF3H registers can be set by a 1-bit or 8-bit memory manipulation
instruction. When the IF0L and IF0H registers, the IF1L and IF1H registers, the IF2L and IF2H registers, and the IF3L
and IF3H registers are combined to form 16-bit registers IF0, IF1, IF2, and IF3, they can be set by a 16-bit memory
manipulation instruction.
Reset signal generation clears these registers to 00H.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
Figure 21-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, IF3H)
(R5F10DSx) (1/2)
Address: FFFE0H After reset: 00H R/W
Symbol
IF0L
PIF5
PIF4
PIF3
PIF2
PIF1
PIF0
LVIIF
WDTIIF
Address: FFFE1H
After reset: 00H
R/W
Symbol
IF0H
LTIF0
ITIF
RTCIF
DMAIF1
DMAIF0
CSIIF01
CSIIF00
CLMIF
SRIF0
STIF0
Address: FFFE2H
After reset: 00H
R/W
Symbol
IF1L
TMIF03
TMIF02
TMIF01
TMIF00
SGIF
PIFLR0
LSIF0
LRIF0
Address: FFFE3H
After reset: 00H
R/W
Symbol
IF1H
TMIF04
IICIF11
CSIIF10
PIFLR1
LSIF1
LRIF1
LTIF1
ADIF
Address: FFFD0H
After reset: 00H
R/W
Symbol
IF2L
C0RECIF
C0WUPIF
C0ERRIF
C1WUPIF
C1ERRIF
TMIF07
TMIF06
TMIF05
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Figure 21-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, IF3H)
(R5F10DSx) (2/2)
Address: FFFD1H
After reset: 00H
R/W
Symbol
IF2H
FLIF
C1RECIF
MDIF
TMIF13
TMIF12
TMIF11
TMIF10
C0TRXIF
Address: FFFD2H
After reset: 00H
R/W
Symbol
IF3L
TMIF22
TMIF21
TMIF20
TMIF17
TMIF16
TMIF15
TMIF14
C1TRXIF
Address: FFFD3H
After reset: 00H
R/W
Symbol
7
6
5
IF3H
0
0
0
DMAIF3
DMAIF2
TMIF26
TMIF24
TMIF23
xxIFx
Interrupt request flag
0
No interrupt request signal is generated
1
Interrupt request is generated, interrupt request status
Cautions 1. The above is the bit layout for the R5F10DSx. The available bits differ depending on the product.
For details about the bits available for each product, see Table 21-1 and 21-2. Be sure to clear
bits that are not available to 0.
2. When manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation
instruction (CLR1). When describing in C language, use a bit manipulation instruction such as
“IF0L.0 = 0;” or “_asm(“clr1 IF0L, 0”);” because the compiled assembler must be a 1-bit memory
manipulation instruction (CLR1).
If a program is described in C language using an 8-bit memory manipulation instruction such as
“IF0L &= 0xfe;” and compiled, it becomes the assembler of three instructions.
mov a, IF0L
and a, #0FEH
mov IF0L, a
In this case, even if the request flag of the another bit of the same interrupt request flag register
(IF0L) is set to 1 at the timing between “mov a, IF0L” and “mov IF0L, a”, the flag is cleared to 0
at “mov IF0L, a”. Therefore, care must be exercised when using an 8-bit memory manipulation
instruction in C language.
(2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L, MK3H)
The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing.
The MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L, and MK3H registers can be set by a 1-bit or 8-bit memory
manipulation instruction. When the MK0L and MK0H registers, the MK1L and MK1H registers, the MK2L and MK2H
registers, and the MK3L and MK3H registers are combined to form 16-bit registers MK0, MK1, MK2, and MK3, they
can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
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Figure 21-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L,
MK3H) (R5F10DSx)
Address: FFFE4H
After reset: FFH
R/W
Symbol
MK0L
PMK5
PMK4
PMK3
PMK2
PMK1
PMK0
LVIMK
WDTIMK
Address: FFFE5H
After reset: FFH
R/W
Symbol
MK0H
LTMK0
ITMK
RTCMK
DMAMK1
DMAMK0
CSIMK01
CSIMK00
CLMMK
SRMK0
STMK0
Address: FFFE6H
After reset: FFH
R/W
Symbol
MK1L
TMMK03
TMMK02
TMMK01
TMMK00
SGMK
PMKLR0
LSMK0
LRMK0
Address: FFFE7H
After reset: FFH
R/W
Symbol
MK1H
TMMK04
IICMK11
CSIMK10
PMKLR1
LSMK1
LRMK1
LTMK1
ADMK
C0ERRMK
C1WUPMK
C1ERRMK
TMMK07
TMMK06
TMMK05
Address: FFFD4H
Symbol
MK2L
After reset: FFH
C0RECMK C0WUPMK
Address: FFFD5H
After reset: FFH
R/W
R/W
Symbol
MK2H
FLMK
C1RECMK
MDMK
TMMK13
TMMK12
TMMK11
TMMK10
C0TRXMK
Address: FFFD6H
After reset: FFH
R/W
Symbol
MK3L
TMMK22
TMMK21
TMMK20
TMMK17
TMMK16
TMMK15
TMMK14
C1TRXMK
Address: FFFD7H
After reset: FFH
R/W
Symbol
7
6
5
MK3H
1
1
1
DMAMK3
DMAMK2
TMMK26
TMMK24
TMMK23
xxMKx
Interrupt servicing control
0
Interrupt servicing enabled
1
Interrupt servicing disabled
Caution The above is the bit layout for the R5F10DSx. The available bits differ depending on the product. For
details about the bits available for each product, see Table 21-1 and 21-2. Be sure to set bits that are
not available to 1.
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(3) Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR03H, PR10L,
PR10H, PR11L, PR11H, PR12L, PR12H, PR13L, PR13H)
The priority specification flag registers are used to set the corresponding maskable interrupt priority level.
A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L, 1H, 2L, or 2H).
The PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR03H, PR10L, PR10H, PR11L, PR11H, PR12L,
PR12H, PR13L, and PR13H registers can be set by a 1-bit or 8-bit memory manipulation instruction. If the PR00L
and PR00H registers, the PR01L and PR01H registers, the PR02L and PR02H registers, the PR10L and PR10H
registers, the PR11L and PR11H registers, the PR12L and PR12H registers, and the PR13L and PR13H registers are
combined to form 16-bit registers PR00, PR01, PR02, PR10, PR11, PR12, and PR13, they can be set by a 16-bit
memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
Figure 21-4. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H,
PR03L, PR03H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L, PR13H) (R5F10DSx) (1/3)
Address: FFFE8H
After reset: FFH
R/W
Symbol
PR00L
PPR05
PPR04
PPR03
PPR02
PPR01
PPR00
LVIPR0
WDTIPR0
Address: FFFECH
After reset: FFH
R/W
Symbol
PR10L
PPR15
PPR14
PPR13
PPR12
PPR11
PPR10
LVIPR1
WDTIPR1
Address: FFFE9H
After reset: FFH
R/W
Symbol
PR00H
LTPR00
ITPR0
RTCPR0
DMAPR01
DMAPR00
CSIPR001
CSIPR000
CLMPR0
Address: FFFEDH
After reset: FFH
R/W
Symbol
PR10H
LTPR10
ITPR1
RTCPR1
DMAPR11
DMAPR10
CSIPR101
CSIPR100
CLMPR1
SRPR10
STPR10
Address: FFFEAH
After reset: FFH
R/W
Symbol
PR01L
TMPR003
TMPR002
TMPR001
TMPR000
SGPR0
PPR0LR0
LSPR00
LRPR00
Address: FFFEEH
After reset: FFH
R/W
Symbol
PR11L
TMPR103
TMPR102
TMPR101
TMPR100
SGPR1
PPR1LR0
LSPR10
LRPR10
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Figure 21-4. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H,
PR03L, PR03H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L, PR13H) (R5F10DSx) (2/3)
Address: FFFEBH
After reset: FFH
R/W
Symbol
PR01H
TMPR004
IICPR011
CSIPR010
PPR0LR1
LSPR01
LRPR01
LTPR01
ADPR0
Address: FFFEFH
After reset: FFH
R/W
Symbol
PR11H
TMPR104
IICPR111
CSIPR110
PPR1LR1
LSPR11
LRPR11
LTPR11
ADPR1
TMPR007
TMPR006
TMPR005
TMPR107
TMPR106
TMPR105
Address: FFFD8H
Symbol
PR02L
After reset: FFH
PR12L
C0RECPR0 C0WUPPR0 C0ERRPR0 C1WUPPR0 C1ERRPR0
Address: FFFDCH
Symbol
R/W
After reset: FFH
R/W
C0RECPR1 C0WUPPR1 C0ERRPR1 C1WUPPR1 C1ERRPR1
Address: FFFD9H
After reset: FFH
R/W
Symbol
PR02H
FLPR0
C1RECPR0
MDPR0
TMPR013
TMPR012
TMPR011
TMPR010
C0TRXPR0
Address: FFFDDH
After reset: FFH
R/W
Symbol
PR12H
FLPR1
C1RECPR1
MDPR1
TMPR113
TMPR112
TMPR111
TMPR110
C0TRXPR1
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Figure 21-4. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H,
PR03L, PR03H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L, PR13H) (R5F10DSx) (3/3)
Address: FFFDAH
After reset: FFH
7
6
PR03L
TMPR022
TMPR021
TMPR020
TMPR017
TMPR016
TMPR015
TMPR014
C1TRXPR0
Address: FFFDEH
After reset: FFH
R/W
Symbol
7
6
PR13L
TMPR122
TMPR121
TMPR120
TMPR117
TMPR116
TMPR115
TMPR114
C1TRXPR1
Address: FFFDBH
After reset: FFH
R/W
Symbol
7
6
5
PR03H
1
1
1
DMAPR03
DMAPR02
TMPR026
TMPR024
TMPR023
Address: FFFDFH
R/W
Symbol
After reset: FFH
R/W
Symbol
7
6
5
PR13H
1
1
1
DMAPR13
DMAPR12
TMPR126
TMPR124
TMPR123
xxPR1x
xxPR0x
0
0
Specify level 0 (high priority level)
0
1
Specify level 1
1
0
Specify level 2
1
1
Specify level 3 (low priority level)
Priority level selection
Caution The above is the bit layout for the R5F10DSx. The available bits differ depending on the product. For
details about the bits available for each product, see Table 20-1 and 20-2. Be sure to set bits that are
not available to 1.
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(4) External interrupt rising edge enable register 0 (EGP0) and external interrupt falling edge enable register 0
(EGN0)
These registers specify the valid edge for external interrupt, INTP0 to INTP5, INTPLR0, and INTPLR1.
The registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 21-5. Format of External Interrupt Rising Edge Enable Register 0 (EGP0) and External Interrupt Falling
Edge Enable Register 0 (EGN0)
Address: FFF38H
Symbol
EGP0
After reset: 00H
6
5
4
3
2
1
0
EGP7
EGP6
EGP5
EGP4
EGP3
EGP2
EGP1
EGP0
Address: FFF39H
Symbol
EGN0
R/W
7
After reset: 00H
R/W
7
6
5
4
3
2
1
0
EGN7
EGN6
EGN5
EGN4
EGN3
EGN2
EGN1
EGN0
EGPn
EGNn
0
0
Edge detection disabled
Valid edge selection of external interrupt
0
1
Falling edge
1
0
Rising edge
1
1
Both rising and falling edges
Table 20-3 shows the ports corresponding to the EGPn and EGNn bits.
Table 21-3. Ports Corresponding to EGPn and EGNn bits
Register name
Bit
External interrupt name
Edge detection port
128-pin
100-pin
80-pin
64-pin
48-pin
EGP0, EGN0
0
INTP0
P17
–
1
INTP1
P60
2
INTP2
P12
3
INTP3
P61
4
INTP4
P10
5
INTP5
P137
6
INTPLR0
P70
–
P70 or P14
–
7
INTPLR1
P11
P11 or P132
–
–
–
Caution
Select the port mode by clearing the EGPn and EGNn bits to 0 because an edge may be detected
when the external interrupt function is switched to the port function.
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(5) Program status word (PSW)
The program status word is a register used to hold the instruction execution result and the current status for an
interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that controls
multiple interrupt servicing are mapped to the PSW.
Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated
instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed, the
contents of the PSW are automatically saved into a stack and the IE flag is reset to 0. If a maskable interrupt request
is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the
ISP0 and ISP1 flags. The PSW contents are also saved into the stack with the PUSH PSW instruction. They are
restored from the stack with the RETI, RETB, and POP PSW instructions.
Reset signal generation sets PSW to 06H.
Figure 21-6. Configuration of Program Status Word
PSW
IE
Z
RBS1
AC
0
After reset
RBS0 ISP1
ISP0
CY
06H
Used when normal instruction is executed
ISP1
ISP0
0
0
Priority of interrupt currently being serviced
Enables interrupt of level 0
(while interrupt of level 1 or 0 is being serviced).
0
1
1
0
Enables interrupt of level 0 and 1
(while interrupt of level 2 is being serviced).
Enables interrupt of level 0 to 2
(while interrupt of level 3 is being serviced).
1
1
Enables all interrupts
(waits for acknowledgment of an interrupt).
IE
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0
Disabled
1
Enabled
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21.4 Interrupt Servicing Operations
21.4.1 Maskable interrupt request acknowledgment
A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK)
flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are
in the interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is not acknowledged
during servicing of a higher priority interrupt request.
The times from generation of a maskable interrupt request until vectored interrupt servicing is performed are listed in
Table 20-4 below.
For the interrupt request acknowledgment timing, see Figures 21-8 and 21-9
Table 21-4. Time from Generation of Maskable Interrupt Until Servicing
Minimum Time
Servicing time
9 clocks
Maximum Time
Note
16 clocks
Note Maximum time does not apply when an instruction from the internal RAM area is executed.
Remark
1 clock: 1/fCLK (fCLK: CPU clock)
If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level
specified in the priority specification flag is acknowledged first. If two or more interrupts requests have the same priority
level, the request with the highest default priority is acknowledged first.
An interrupt request that is held pending is acknowledged when it becomes acknowledgeable.
Figure 20-7shows the interrupt request acknowledgment algorithm.
If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC,
the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged interrupt are
transferred to the ISP1 and ISP0 flags. The vector table data determined for each interrupt request is the loaded into the
PC and branched.
Restoring from an interrupt is possible by using the RETI instruction.
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Figure 21-7. Interrupt Request Acknowledgment Processing Algorithm
Start
No
××IF = 1?
Yes (interrupt request generation)
××MK = 0?
No
Yes
Interrupt request held pending
(××PR1, ××PR0)
≥ (ISP1, ISP0)
No (Low priority)
Interrupt request held pending
Higher priority
than other interrupt requests
simultaneously
generated?
No
Interrupt request held pending
Yes
Higher default priorityNote
than other interrupt requests
simultaneously
generated?
No
Interrupt request held pending
Yes
IE = 1?
Yes
No
Interrupt request held pending
Vectored interrupt servicing
IF:
Interrupt request flag
MK:
Interrupt mask flag
PR0:
Priority specification flag 0
PR1:
Priority specification flag 1
IE:
Flag that controls acknowledgment of maskable interrupt request (1 = Enable, 0 = Disable)
ISP0, ISP1: Flag that indicates the priority level of the interrupt currently being serviced (see Figure 21-6)
Note For the default priority, refer to Table 21-1 Interrupt Source List.
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Figure 21-8. Interrupt Request Acknowledgment Timing (Minimum Time)
6 clocks
CPU processing
Instruction
Instruction
PSW and PC saved,
jump to interrupt
servicing
Interrupt servicing
program
××IF
9 clocks
Remark
1 clock: 1/fCLK (fCLK: CPU clock)
Figure 21-9. Interrupt Request Acknowledgment Timing (Maximum Time)
8 clocks
CPU processing
Instruction
6 clocks
Instruction immediately PSW and PC saved,
jump to interrupt
before interrupt
servicing
Interrupt servicing
program
IF
16 clocks
Remark
1 clock: 1/fCLK (fCLK: CPU clock)
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CHAPTER 21 INTERRUPT FUNCTIONS
21.4.2 Software interrupt request acknowledgment
A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled.
If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program
status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (0007EH,
0007FH) are loaded into the PC and branched.
Restoring from a software interrupt is possible by using the RETB instruction.
Caution Can not use the RETI instruction for restoring from the software interrupt.
21.4.3 Multiple interrupt servicing
Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt.
Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE =
1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0). Therefore,
to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to
enable interrupt acknowledgment.
Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to interrupt
priority control. Two types of priority control are available: default priority control and programmable priority control.
Programmable priority control is used for multiple interrupt servicing.
In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt currently
being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority lower than that
of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt
servicing. Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they
have a lower priority are held pending. When servicing of the current interrupt ends, the pending interrupt request is
acknowledged following execution of at least one main processing instruction execution.
Table 20-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 20-10
shows multiple interrupt servicing examples.
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Table 21-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing
During Interrupt Servicing
Multiple Interrupt Request
Maskable Interrupt Request
Priority Level 0
(PR = 00)
Priority Level 2
(PR = 10)
Priority Level 3
(PR = 11)
IE = 1
IE = 0
IE = 1
IE = 0
IE = 1
IE = 0
IE = 1
IE = 0
ISP1 = 0
ISP0 = 0
-
-
-
-
-
-
-
ISP1 = 0
ISP0 = 1
-
-
-
-
-
ISP1 = 1
ISP0 = 0
-
-
-
-
-
-
-
-
-
Interrupt Being Serviced
Maskable interrupt
Priority Level 1
(PR = 01)
Software
Interrupt
Request
Software interrupt
Remarks 1. : Multiple interrupt servicing enabled
2. -: Multiple interrupt servicing disabled
3. ISP0, ISP1, and IE are flags contained in the PSW.
ISP1 = 0, ISP0 = 0: An interrupt of level 1 or level 0 is being serviced.
ISP1 = 0, ISP0 = 1: An interrupt of level 2 is being serviced.
ISP1 = 1, ISP0 = 0: An interrupt of level 3 is being serviced.
ISP1 = 1, ISP0 = 1: Wait for An interrupt acknowledgment.
IE = 0: Interrupt request acknowledgment is disabled.
IE = 1: Interrupt request acknowledgment is enabled.
4. PR is a flag contained in the PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L,
PR11H, PR12L, and PR12H registers.
PR = 00: Specify level 0 with PR1 = 0, PR0 = 0 (higher priority level)
PR = 01: Specify level 1 with PR1 = 0, PR0 = 1
PR = 10: Specify level 2 with PR1 = 1, PR0 = 0
PR = 11: Specify level 3 with PR1 = 1, PR0 = 1 (lower priority level)
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Figure 21-10. Examples of Multiple Interrupt Servicing (1/2)
Example 1. Multiple interrupt servicing occurs twice
Main processing
INTxx servicing
IE = 0
EI
INTyy servicing
IE = 0
IE = 0
EI
INTxx
(PR = 11)
INTzz servicing
EI
INTyy
(PR = 10)
INTzz
(PR = 01)
RETI
IE = 1
IE = 1
RETI
RETI
IE = 1
During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt
servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be issued to enable
interrupt request acknowledgment.
Example 2. Multiple interrupt servicing does not occur due to priority control
Main processing
EI
INTxx servicing
INTyy servicing
IE = 0
EI
INTxx
(PR = 10)
INTyy
(PR = 11)
RETI
IE = 1
1 instruction execution
IE = 0
RETI
IE = 1
Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower than
that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is
acknowledged following execution of one main processing instruction.
PR = 00: Specify level 0 with PR1 = 0, PR0 = 0 (higher priority level)
PR = 01: Specify level 1 with PR1 = 0, PR0 = 1
PR = 10: Specify level 2 with PR1 = 1, PR0 = 0
PR = 11: Specify level 3 with PR1 = 1, PR0 = 1 (lower priority level)
IE = 0:
Interrupt request acknowledgment is disabled
IE = 1:
Interrupt request acknowledgment is enabled.
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Figure 21-10. Examples of Multiple Interrupt Servicing (2/2)
Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled
Main processing
INTxx servicing INTyy servicing
IE = 0
EI
INTxx
(PR = 11)
INTyy
(PR = 00)
RETI
IE = 1
1 instruction execution
IE = 0
RETI
IE = 1
Interrupts are not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt request
INTyy is not acknowledged and multiple interrupt servicing does not take place. The INTyy interrupt request is held
pending, and is acknowledged following execution of one main processing instruction.
PR = 00: Specify level 0 with PR1 = 0, PR0 = 0 (higher priority level)
PR = 01: Specify level 1 with PR1 = 0, PR0 = 1
PR = 10: Specify level 2 with PR1 = 1, PR0 = 0
PR = 11: Specify level 3 with PR1 = 1, PR0 = 1 (lower priority level)
IE = 0:
Interrupt request acknowledgment is disabled
IE = 1:
Interrupt request acknowledgment is enabled.
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21.4.4 Interrupt request hold
There are instructions where, even if an interrupt request is issued while the instructions are being executed, interrupt
request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt
request hold instructions) are listed below.
MOV PSW, #byte
MOV PSW, A
MOV1 PSW. bit, CY
SET1 PSW. bit
CLR1 PSW. bit
RETB
RETI
POP PSW
BTCLR PSW. bit, $addr20
EI
DI
SKC
SKNC
SKZ
SKNZ
SKH
SKNH
Write instructions for the IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, MK0L, MK0H, MK1L, MK1H, MK2L, MK2H,
MK3L, PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H,
and PR13L registers
Figure 20-11 shows the timing at which interrupt requests are held pending.
Figure 21-11. Interrupt Request Hold
CPU processing
Instruction N
Instruction M
PSW and PC saved, jump
to interrupt servicing
Interrupt servicing
program
××IF
Remarks 1. Instruction N: Interrupt request hold instruction
2. Instruction M: Instruction other than interrupt request hold instruction
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CHAPTER 22 STANDBY FUNCTION
22.1 Standby Function and Configuration
22.1.1 Standby function
The standby function reduces the operating current of the system, and the following three modes are available.
(1) HALT mode
HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the highspeed system clock oscillator, high-speed on-chip oscillator, or subsystem clock oscillator is operating before the
HALT mode is set, oscillation of each clock continues. In this mode, the operating current is not decreased as much
as in the STOP mode, but the HALT mode is effective for restarting operation immediately upon interrupt request
generation and carrying out intermittent operations frequently.
(2) STOP mode
STOP instruction execution sets the STOP mode. In the STOP mode, the high-speed system clock oscillator and
high-speed on-chip oscillator stop, stopping the whole system, thereby considerably reducing the CPU operating
current.
Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out.
However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is released
when the X1 clock is selected, select the HALT mode if it is necessary to start processing immediately upon interrupt
request generation.
(3) SNOOZE mode
In the case of an A/D conversion request by the hardware trigger signal from external pin (ADTRG), the STOP mode
is exited, A/D conversion is performed without operating the CPU. This can only be specified when the high-speed onchip oscillator is selected for the CPU/peripheral hardware clock (fCLK).
In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set
are held. The I/O port output latches and output buffer statuses are also held.
Cautions 1. The STOP mode can be used only when the CPU is operating on the main system clock. The
STOP mode cannot be set while the CPU operates with the subsystem clock. The HALT mode
can be used when the CPU is operating on either the main system clock or the subsystem clock.
2. When shifting to the STOP mode, be sure to stop the peripheral hardware operation operating
with main system clock before executing STOP instruction.
When using the A/D converter in the SNOOZE mode, set up A/D converter mode register 2
(ADM2) before switching to the STOP mode.
For details, see 11.3
Registers Used in A/D
Converter.
3. The following sequence is recommended for operating current reduction of the A/D converter
when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of A/D converter
mode register 0 (ADM0) to 0 to stop the A/D conversion operation, and then execute the STOP
instruction.
4. It can be selected by the option byte whether the low-speed on-chip oscillator continues
oscillating or stops in the HALT or STOP mode. For details, see CHAPTER 28 OPTION BYTE.
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22.1.2 Registers controlling standby function
The standby function is controlled by the following two registers.
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
STOP status output control register (STPSTC) Note
Note 128-pin products only.
Remark
For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR.
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(1) Oscillation stabilization time counter status register (OSTC)
This is the register that indicates the count status of the X1 clock oscillation stabilization time counter.
The X1 clock oscillation stabilization time can be checked in the following case.
If the X1 clock starts oscillation while the high-speed on-chip oscillator clock or subsystem clock is being used as
the CPU clock.
If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as
the CPU clock with the X1 clock oscillating.
The OSTC register can be read by a 1-bit or 8-bit memory manipulation instruction.
____________
When reset is released (reset by RESET input, POR, LVD, WDT, and executing an illegal instruction), the STOP
instruction and MSTOP bit (bit 7 of clock operation status control register (CSC)) = 1 clear this register to 00H.
Figure 22-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFFA2H
Symbol
OSTC
7
After reset: 00H
6
5
R
4
3
2
1
0
MOST MOST MOST MOST MOST MOST MOST MOST
8
9
10
11
13
15
17
18
MOST MOST MOST MOST MOST MOST MOST MOST
8
9
10
11
13
15
17
18
Oscillation stabilization time status
fX = 10 MHz
fX = 20 MHz
0
0
0
0
0
0
0
0
2 /fX max. 25.6 s max.
12.8 s max.
1
0
0
0
0
0
0
0
2 /fX min. 25.6 s min.
12.8 s min.
1
1
0
0
0
0
0
0
2 /fX min. 51.2 s min.
25.6 s min.
8
8
9
1
1
1
0
0
0
0
0
2 /fX min. 102.4 s min. 51.2 s min.
1
1
1
1
0
0
0
0
2 /fX min. 204.8 s min. 102.4 s min.
1
1
1
1
1
0
0
0
2 /fX min. 819.2 s min. 409.6 s min.
1
1
1
1
1
1
0
0
2 /fX min. 3.27 ms min.
1
1
1
1
1
1
1
0
2 /fX min. 13.11 ms min. 6.55 ms min.
1
1
1
1
1
1
1
1
2 /fX min. 26.21 ms min. 13.11 ms min.
10
11
13
15
1.64 ms min.
17
18
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from the MOST8
bit and remain 1.
2. The oscillation stabilization time counter counts up to the oscillation
stabilization time set by the oscillation stabilization time select register (OSTS).
If the STOP mode is entered and then released while the high-speed on-chip
oscillator clock is being used as the CPU clock, set the oscillation stabilization
time as follows.
Desired OSTC register oscillation stabilization time Oscillation
stabilization time set by OSTS register
Note, therefore, that only the status up to the oscillation stabilization time set
by the OSTS register is set to the OSTC register after STOP mode is released.
3. The X1 clock oscillation stabilization wait time does not include the time until
clock oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark
fX: X1 clock oscillation frequency
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(2) Oscillation stabilization time select register (OSTS)
This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released.
When the X1 clock is selected as the CPU clock, the operation waits for the time set using the OSTS register after the
STOP mode is released.
When the high-speed on-chip oscillator clock is selected as the CPU clock, confirm with the oscillation stabilization
time counter status register (OSTC) that the desired oscillation stabilization time has elapsed after the STOP mode is
released. The oscillation stabilization time can be checked up to the time set using the OSTC register.
The OSTS register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 07H.
Figure 22-2. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFFA3H
After reset: 07H
R/W
Symbol
7
6
5
4
3
2
1
0
OSTS
0
0
0
0
0
OSTS.2
OSTS.1
OSTS.0
OSTS.2
OSTS.1
OSTS.0
0
0
0
2 /fX
0
0
1
2 /fX
0
1
0
2 /fX
Oscillation stabilization time selection
fX = 10 MHz
fX = 20 MHz
8
25.6 s
Setting prohibited
9
51.2 s
25.6 s
10
102.4 s
51.2 s
11
204.8 s
102.4 s
13
819.2 s
409.6 s
15
3.27 ms
1.64 ms
17
13.11 ms
6.55 ms
18
26.21 ms
13.11 ms
0
1
1
2 /fX
1
0
0
2 /fX
1
0
1
2 /fX
1
1
0
2 /fX
1
1
1
2 /fX
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set the OSTS register before
executing the STOP instruction.
2. Setting the oscillation stabilization time to 20 s or less is prohibited.
3. Before changing the setting of the OSTS register, confirm that the count operation of the OSTC
register is completed.
4. Do not change the value of the OSTS register during the X1 clock oscillation stabilization time.
5. The oscillation stabilization time counter counts up to the oscillation stabilization time set by
the OSTS register. If the STOP mode is entered and then released while the high-speed on-chip
oscillator clock is being used as the CPU clock, set the oscillation stabilization time as follows.
Desired OSTC register oscillation stabilization time Oscillation stabilization time set by
OSTS register
Note, therefore, that only the status up to the oscillation stabilization time set by the OSTS
register is set to the OSTC register after STOP mode is released.
6. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation
starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark fX: X1 clock oscillation frequency
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(3) STOP status output control register (STPSTC) (128-pin products only)
This register controls the output of STOP status.
Once STOP release triggers occurs, or SNOOZE released to normal mode occurs, P41 pin level is inverted. This
function is incorporated to only 128-pin products.
When a STOP released or SNOOZE released to normal mode, this register can enable to output the inverted signal
STOPST from P41.
The STPSTC register can be set by 1- or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Caution
When using STOPST output, P41 should be set to output mode and the port latch of P41 should
be set to “0” in advance.
Figure 22-3. Format of STOP status output control register (STPSTC)
Address: F0016H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
STPSTC
STPOEN
0
0
STPLV
0
0
0
0
STPOEN
Operation when STOP released
0
P41/STOPST performs no operation when STOP released or SNOOZE released to normal
mode
1
STPLV can be output as STOPST from P41 when STOP released or SNOOZE released to
normal mode.
The STPOEN bit controls output of the STPLV from P41.
STPLV
Data control when STOP released or SNOOZE released to normal mode
0
Low output (will invert to high at next STOP released or SNOOZE released to normal mode )
1
High output (will invert to low at next STOP released or SNOOZE released to normal mode )
The STPLV bit is inverted when STOP released or SNOOZE released to normal mode, regardless of the
STPOEN status. See Figure 22-4
Figure 22-4. Timings of STPLV, P41/STOPST
STOP release
CPU status
RUN
STOP
RUN
SNOOZE release
STOP
RUN
STOP
SNOOZE
RUN
P41/STOPST
STPLV
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22.2 Standby Function Operation
22.2.1 HALT mode
(1) HALT mode
The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU
clock before the setting was the high-speed system clock, high-speed on-chip oscillator clock, or subsystem clock.
The operating statuses in the HALT mode are shown below.
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Table 22-1. Operating Statuses in HALT Mode (1/3)
HALT Mode Setting
When HALT Instruction Is Executed While CPU Is Operating on Main System Clock
When CPU Is Operating on
High-speed on-chip oscillator
Clock (fIH) or fIH+PLL
Item
System clock
When CPU Is Operating on
X1 Clock (fX) or fX +PLL
When CPU Is Operating on
External Main System Clock
(fEX) or fEX +PLL
Clock supply to the CPU is stopped
Main system clock
fIH
Operation continues (cannot
be stopped)
Operation disabled
fX
Operation disabled
Operation continues (cannot
be stopped)
Cannot operate
Cannot operate
Operation continues (cannot
be stopped)
fEX
Subsystem clock
fXT
fIL
Status before HALT mode was set is retained
Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of
operation speed mode control register (OSMC)
WUTMMCK0 = 1: Oscillates
WUTMMCK0 = 1 and WDTON = 0: Stops
WUTMMCK0 = 1, WDTON = 1, and WDSTBYON = 1: Oscillates
WUTMMCK0 = 1, WDTON = 1, and WDSTBYON = 0: Stops
PLL
Status before HALT mode was set is retained
CPU
Operation stopped
Code flash memory
Data flash memory
RAM
Operation stopped (however, operable when DMA is executed)
CREG
Status before HALT mode was set is retained
Port (latch)
Status before HALT mode was set is retained
Timer array unit
Operable
Real-time clock (RTC)
Interval timer
Watchdog timer
See CHAPTER 10 WATCHDOG TIMER
CLM
Operable if fIL is not stopped
PCL
Operable
A/D converter
2
SAU (CSI, I C, UART)
Serial interface LIN-UART
(UARTF)
CAN controller
LCD controller/driver
LCD Bus interface
Sound generator
Stepper motor controller/driver
(with ZPD)
Multiplier and divider/multiplyaccumulator
DMA controller
Power-on-reset function
Voltage detection function
External interrupt
Acceptable
Internal interrupt
CRC
operation
function
High-speed CRC
Operable
General-purpose
CRC
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Table 22-1. Operating Statuses in HALT Mode (2/3)
HALT Mode Setting
Item
Illegal access detection
function
When HALT Instruction Is Executed While CPU Is Operating on Main System Clock
When CPU Is Operating on
High-speed on-chip oscillator
Clock (fIH) or fIH+PLL
When CPU Is Operating on
X1 Clock (fX) or fX +PLL
When CPU Is Operating on
External Main System Clock
(fEX) or fEX +PLL
Operation stopped (however, it is possible when DMA is executed)
RAM parity check function
RAM guard function
SFR guard function
BCD
Operation stopped
Remark Operation stopped:
Operation is automatically stopped before switching to the HALT mode.
Operation disabled: Operation must be stopped before switching to the HALT mode.
fIH:
High-speed on-chip oscillator clock
fEX: External main system clock
Low-speed on-chip oscillator clock
fXT: XT1 clock
fIL:
fX:
X1 clock
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Table 22-1. Operating Statuses in HALT Mode (3/3)
HALT Mode Setting
When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock
Item
When CPU Is Operating on XT1 Clock (fXT)
System clock
Clock supply to the CPU is stopped
Main system clock
fIH
Operation disabled
fX
fEX
Subsystem clock
fXT
fIL
Operation continues (cannot be stopped)
Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of
operation speed mode control register (OSMC)
WUTMMCK0 = 1: Oscillates
WUTMMCK0 = 1 and WDTON = 0: Stops
WUTMMCK0 = 1, WDTON = 1, and WDSTBYON = 1: Oscillates
WUTMMCK0 = 1, WDTON = 1, and WDSTBYON = 0: Stops
PLL
Operation disabled
CPU
Operation stopped
Code flash memory
Data flash memory
RAM
Operation stopped (however, operable when DMA is executed)
CREG
Status before HALT mode was set is retained
Port (latch)
Status before HALT mode was set is retained (CPU is stopped, while input/output function is
possible by DMA access during HALT mode)
Timer array unit
Operable (Operation is disabled while in the low consumption RTC mode (when the RTCLPC
Real-time clock (RTC)
Operable
bit of the OSMC register is 1))
Interval timer
Watchdog timer
See CHAPTER 10 WATCHDOG TIMER
CLM
Operation stopped
PCL
Operable (Operation is disabled while in the low consumption RTC mode)
A/D converter
Operation disabled
2
SAU (CSI, I C, UART)
Operable (Operation is disabled while in the low consumption RTC mode (when the RTCLPC
Serial interface LIN-UART
(UARTF)
bit of the OSMC register is 1))
CAN controller
LCD controller/driver
LCD Bus interface
Operation disabled
Sound generator
Operable (Operation is disabled while in the low consumption RTC mode (when the RTCLPC
Stepper motor controller/driver
(with ZPD)
bit of the OSMC register is 1))
Multiplier and divider/multiplyaccumulator
DMA controller
Power-on-reset function
Operable
Voltage detection function
External interrupt
Acceptable
Internal interrupt
CRC
operation
function
High-speed CRC
Operation disabled
General-purpose
CRC
Operable
Illegal access detection function
Operation stopped (however, it is possible when DMA is executed)
RAM parity check function
RAM guard function
SFR guard function
BCD
Operation stopped
Remark Operation stopped:
Operation is automatically stopped before switching to the HALT mode.
Operation disabled: Operation must be stopped before switching to the HALT mode.
High-speed on-chip oscillator clock
fEX: External main system clock
fIH:
fIL:
Low-speed on-chip oscillator clock
fXT: XT1 clock
fX: X1 clock
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(2) HALT mode release
The HALT mode can be released by the following two sources.
(a) Release by unmasked interrupt request
When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is
enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address
instruction is executed.
Figure 22-5. HALT Mode Release by Interrupt Request Generation
HALT
instruction
Interrupt
request
Standby
release signal
Status of CPU
High-speed system clock,
high-speed on-chip oscillator clock,
or subsystem clock
Remark
Operating mode
Wait
HALT mode
Operating mode
Oscillation
The broken lines indicate the case when the interrupt request which has released the standby mode is
acknowledged.
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(b) Release by reset signal generation
When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 22-6 HALT Mode Release by Reset
(1) When high-speed system clock is used as CPU clock
HALT
instruction
Reset signal
Status of CPU
Reset processing
Normal operation
(high-speed
system clock)
High-speed
system clock
(X1 oscillation)
HALT mode
Normal operation
(high-speed on-chip
oscillator clock)
Reset
period
Oscillation Oscillation
stopped stopped
Oscillates
Oscillates
Oscillation stabilization time
(check by using OSTC register)
Starting X1 oscillation is
specified by software.
When high-speed on-chip oscillator clock is used as CPU clock
HALT
instruction
Reset signal
Reset processing
Normal operation
(high-speed on-chip
oscillator clock)
Status of CPU
HALT mode
Oscillation
stopped
Oscillates
High-speed on-chip oscillator clock
Normal operation
(high-speed on-chip
oscillator clock)
Reset
period
Oscillates
Wait for oscillation
accuracy stabilization
(3) When subsystem clock is used as CPU clock
HALT
instruction
Reset signal
Status of CPU
Subsystem clock
(XT1 oscillation)
Reset processing
Normal operation
(subsystem clock)
HALT mode
Oscillates
Reset
period
Normal operation mode
(high-speed on-chip
oscillator clock)
Oscillation Oscillation
stopped
stopped Oscillates
Starting XT1 oscillation is
specified by software.
Remark fX: X1 clock oscillation frequency
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22.2.2 STOP mode
(1) STOP mode setting and operating statuses
The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the
setting was the main system clock.
Cautions 1. Because the interrupt request signal is used to clear the standby mode, if there is an interrupt
source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is
immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after
execution of the STOP instruction and the system returns to the operating mode as soon as the
wait time set using the oscillation stabilization time select register (OSTS) has elapsed.
2. When using the A/D converter in the SNOOZE mode, set up A/D converter mode register 2
(ADM2) before switching to the STOP mode.
For details, see 11.3
Registers Used in A/D
Converter.
The operating statuses in the STOP mode are shown below.
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Table 22-2. Operating Statuses in STOP Mode (1/2)
STOP Mode Setting
When STOP Instruction Is Executed While CPU Is Operating on Main System Clock
When CPU Is Operating on
High-speed on-chip oscillator
Clock (fIH) or fIH+PLL
Item
System clock
Main system clock
When CPU Is Operating on
X1 Clock (fX) or fX+PLL
When CPU Is Operating on
External Main System Clock
(fEX) or fEX+PLL
Clock supply to the CPU is stopped
fIH
Stopped
fX
fEX
Subsystem clock
fXT
fIL
Status before STOP mode was set is retained
Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of
operation speed mode control register (OSMC)
WUTMMCK0 = 1: Oscillates
WUTMMCK0 = 1 and WDTON = 0: Stops
WUTMMCK0 = 1, WDTON = 1, and WDSTBYON = 1: Oscillates
WUTMMCK0 = 1, WDTON = 1, and WDSTBYON = 0: Stops
PLL
Operation disabled
CPU
Operation stopped
Code flash memory
Data flash memory
Operation stopped (Executing the STOP instruction is disabled during data flash programming)
RAM
Operation stopped
CREG
Low power mode
Port (latch)
Status before STOP mode was set is retained
Timer array unit
Operation disabled
Real-time clock (RTC)
Operable by fXT or fIL
Interval timer
Watchdog timer
See CHAPTER 10 WATCHDOG TIMER
CLM
Operation stopped
PCL
Operable only when fXT clock is selected
A/D converter
2
Wakeup operation is enabled (switching to the SNOOZE mode)
SAU (CSI, I C, UART)
Operation stopped
Serial interface LIN-UART
(UARTF)
Operation disabled (STOP release by INTPLRx is possible)
CAN controller
Operation disabled (STOP release by INTCxWUP during CAN sleep mode is possible)
LCD controller/driver
Operable by fXT or fIL
LCD bus interface
Operation stopped
Sound generator
Stepper motor controller/driver
(with ZPD)
Multiplier and divider/multiplyaccumulator
Operation disabled
DMA controller
Power-on-reset function
Operable
Voltage detection function
External interrupt
Acceptable
Internal interrupt
Interrupts from operable peripherals are acceptable
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Table 22-2. Operating Statuses in STOP Mode (2/2)
STOP Mode Setting
When CPU Is Operating on
High-speed on-chip oscillator
Clock (fIH) or fIH+PLL
Item
CRC
operation
function
When STOP Instruction Is Executed While CPU Is Operating on Main System Clock
High-speed CRC
When CPU Is Operating on
X1 Clock (fX) or fX+PLL
When CPU Is Operating on
External Main System Clock
(fEX) or fEX+PLL
Operation stopped
General-purpose
CRC
Illegal access detection
function
RAM parity check function
RAM guard function
SFR guard function
BCD
Remark
Operation stopped:
Operation is automatically stopped before switching to the STOP mode.
Operation disabled: Operation must be stopped before switching to the STOP mode.
fIH: High-speed on-chip oscillator clock
fIL:
Low-speed on-chip oscillator clock
fEX: External main system clock
fX: X1 clock
fXT: XT1 clock
Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral hardware
for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart
the peripheral hardware.
2. To stop the low-speed on-chip oscillator clock in the STOP mode, use an option byte to stop the
watchdog timer operation in the HALT/STOP mode (bit 0 (WDSTBYON) of 000C0H = 0), and then
execute the STOP instruction.
3. To shorten oscillation stabilization time after the STOP mode is released when the CPU operates
with the high-speed system clock (X1 oscillation), temporarily switch the CPU clock to the highspeed on-chip oscillator clock before the execution of the STOP instruction. Before changing the
CPU clock from the high-speed on-chip oscillator clock to the high-speed system clock (X1
oscillation) after the STOP mode is released, check the oscillation stabilization time with the
oscillation stabilization time counter status register (OSTC).
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(2) STOP mode release
The STOP mode can be released by the following two sources.
(a) Release by unmasked interrupt request
When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization
time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt
acknowledgment is disabled, the next address instruction is executed.
Figure 22-7. STOP Mode Release by Interrupt Request Generation (1/2)
(1) When high-speed system clock (X1 oscillation) is used as CPU clock
STOP
instruction
Interrupt
request
Standby release signal Note 1
Status of CPU
STOP mode
Oscillates
Oscillation stopped
High-speed
system clock
(X1 oscillation)
Notes 1.
STOP mode release time Note 2
Normal operation
(high-speed
system clock)
Supply of the
clock is stopped
Wait
Normal operation
(high-speed
system clock)
Oscillates
For details of the standby release signal, see Figure 21-1.
2.
STOP mode release time
Supply of the clock is stopped:
18 s to whichever is longer 65 s and the oscillation stabilization time
(set by OSTS) (additional wait cycles are required when using a PLL.)
Wait
Remarks 1.
2.
When vectored interrupt servicing is carried out:
10 to 11 clocks
When vectored interrupt servicing is not carried out:
4 to 5 clocks
The clock supply stop time varies depending on the temperature conditions and STOP mode period.
The broken lines indicate the case when the interrupt request that has released the standby mode is
acknowledged.
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Figure 22-7. STOP Mode Release by Interrupt Request Generation (2/2)
(2) When high-speed system clock (external clock input) is used as CPU clock
STOP
instruction
Interrupt
request
Standby release signal Note 1
Status of CPU
High-speed
system clock
(external clock input)
STOP mode release time Note 2
Supply of the
Wait
clock is stopped
Normal operation
(high-speed
system clock)
STOP mode
Oscillates
Oscillation stopped
Normal operation
(high-speed
system clock)
Oscillates
(3) When high-speed on-chip oscillator clock is used as CPU clock
STOP
instruction
Interrupt
request
Standby release signal Note 1
Status of CPU
High-speed on-chip
oscillator clock
STOP mode release time Note 2
Normal operation
(high-speed on-chip
oscillator clock)
STOP mode
Oscillates
Oscillation stopped
Supply of the
clock is stopped
Wait
Normal operation
(high-speed on-chip
oscillator clock)
Oscillates
Wait for oscillation
accuracy stabilization
Notes 1.
2.
For details of the standby release signal, see Figure 21-1.
STOP mode release time
Supply of the clock is stopped:
18 s to 65 s
Wait
When vectored interrupt servicing is carried out:
7 clocks
When vectored interrupt servicing is not carried out:
1 clock
Remarks 1. The clock supply stop time varies depending on the temperature conditions and STOP mode period.
2. The broken lines indicate the case when the interrupt request that has released the standby mode is
acknowledged.
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(b) Release by reset signal generation
When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 22-8. STOP Mode Release by Reset
(1) When high-speed system clock is used as CPU clock
STOP
instruction
Reset signal
Status of CPU
Reset processing
Normal operation
(high-speed
system clock)
High-speed
system clock
(X1 oscillation)
STOP mode
Oscillation stopped
Oscillates
Normal operation
(high-speed on-chip
oscillator clock)
Reset
period
Oscillation Oscillation
stopped stopped
Oscillates
Oscillation stabilization time
(Check by using OSTC register)
Starting X1 oscillation is
specified by software.
(2) When high-speed on-chip oscillator clock is used as CPU clock
STOP
instruction
Reset signal
Status of CPU
High-speed on-chip
oscillator clock
Reset processing
Normal operation
(high-speed on-chip
oscillator clock)
Oscillates
STOP mode
Reset
period
Oscillation
Oscillation stopped stopped
Normal operation
(high-speed on-chip
oscillator clock)
Oscillates
Wait for oscillation
accuracy stabilization
Remark fX: X1 clock oscillation frequency
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22.2.3 SNOOZE mode
(1) SNOOZE mode setting and operating statuses
The SNOOZE mode can only be specified for the A/D converter. Note that this mode can only be specified if the CPU
clock is the high-speed on-chip oscillator clock.
When using the A/D converter in the SNOOZE mode, set up A/D converter mode register 2 (ADM2) before switching
to the STOP mode. For details, see 11.3 Registers Used in A/D Converter.
The transition time of going into and getting out from SNOOZE mode is as following.
Transition time from STOP mode to SNOOZE mode
18 to 65 s
Remark
Transition time from STOP mode to SNOOZE mode varies depending on the temperature conditions and
the STOP mode period.
Transition time from SNOOZE mode to normal operation
When vectored interrupt servicing is carried out:
4.99 to 9.44 s + 7 clocks
When vectored interrupt servicing is not carried out:
4.99 to 9.44 s + 1 clock
The operating statuses in the SNOOZE mode are shown below.
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Table 22-3. Operating Statuses in SNOOZE Mode (1/2)
When Inputting A/D Converter Timer Trigger Signal While in SNOOZE Mode
SNOOZE Mode Setting
Item
When CPU Is Operating on High-speed on-chip oscillator Clock (fIH)
System clock
Main system clock
Clock supply to the CPU is stopped
fIH
Operation started
fX
Stopped
fEX
Subsystem clock
fXT
Use of the status while in the STOP mode continues
Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of
fIL
operation speed mode control register (OSMC)
WUTMMCK0 = 1: Oscillates
WUTMMCK0 = 1 and WDTON = 0: Stops
WUTMMCK0 = 1, WDTON = 1, and WDSTBYON = 1: Oscillates
WUTMMCK0 = 1, WDTON = 1, and WDSTBYON = 0: Stops
PLL
Operation stopped
CPU
Code flash memory
Data flash memory
RAM
CREG
Low power mode
Port (latch)
Use of the status while in the STOP mode continues
Timer array unit
Operation disabled
Real-time clock (RTC)
Operable
Interval timer
Watchdog timer
See CHAPTER 10 WATCHDOG TIMER
CLM
Operation stopped
A/D converter
Operable
2
SAU (CSI, I C, UART)
Operation disabled
Serial interface LIN-UART
(UARTF)
CAN controller
LCD controller/driver
LCD bus interface
Sound generator
Stepper motor controller/driver
(with ZPD)
Multiplier and divider/multiplyaccumulator
DMA controller
Power-on-reset function
Operable
Voltage detection function
External interrupt
Internal interrupt
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Table 22-3. Operating Statuses in SNOOZE Mode (2/2)
SNOOZE Mode Setting
Item
When Inputting A/D Converter Timer Trigger Signal While in SNOOZE Mode
When CPU Is Operating on High-speed on-chip oscillator Clock (fIH)
CRC
High-speed CRC
operation
General-purpose
function
CRC
Operation disabled
Illegal access detection
function
RAM parity check function
RAM guard function
SFR guard function
BCD
Remark
Operation stopped:
Operation is automatically stopped before switching to the SNOOZE mode.
Operation disabled: Operation must be stopped before switching to the SNOOZE mode.
fIL:
Low-speed on-chip oscillator clock
fIH: High-speed on-chip oscillator clock
fEX: External main system clock
fX: X1 clock
fXT: XT1 clock
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CHAPTER 23 RESET FUNCTION
The following eight operations are available to generate a reset signal.
____________
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-reset (POR) circuit
(4) Internal reset by comparison of supply voltage of the voltage detector (LVD) and detection voltage
(5) Internal reset by execution of illegal instructionNote
(6) Internal reset by RAM parity error
(7) Internal reset by detection of main clock oscillation stop via clock monitoring
(8) Internal reset by illegal-memory access
External and internal resets start program execution from the address at 0000H and 0001H when the reset signal is
generated.
____________
A reset is effected when a low level is input to the RESET pin, the watchdog timer overflows, or by POR and LVD
circuit voltage detection, execution of illegal instructionNote, RAM parity error, detection of main clock oscillation stop via
clock monitoring, or illegal-memory access, and each item of hardware is set to the status shown in Tables 22-1.
____________
When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high level is
____________
input to the RESET pin and program execution is started with the high-speed on-chip oscillator clock after reset
processing. A reset by the watchdog timer is automatically released, and program execution starts using the high-speed
on-chip oscillator clock (see Figures 23-2 to 23-4) after reset processing. Reset by POR and LVD circuit supply voltage
detection is automatically released when VDD VPOR or VDD VLVD after the reset, and program execution starts using the
high-speed on-chip oscillator clock (see CHAPTER 24 POWER-ON-RESET CIRCUIT and CHAPTER 25 VOLTAGE
DETECTOR) after reset processing.
Note
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
____________
Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin.
(To perform an external reset upon power application, a low level of at least 10 s must be
continued during the period in which the supply voltage is within the operating range (VDD 2.7
V).)
2. During reset input, the X1 clock, XT1 clock, high-speed on-chip oscillator clock, and low-speed
on-chip oscillator clock stop oscillating. External main system clock input becomes invalid.
3. When reset is effected, port pin P130 is set to low-level output and other port pins become highimpedance, because each SFR and 2nd SFR are initialized.
Remark
VPOR: POR power supply rise detection voltage
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Set
Set
Set
WDTRF
2. LVIS: Voltage detection level register
Remarks 1. LVIM: Voltage detection register
Set
Clear
RPERF
Set
IAWRF
Clear
Reset control flag
register (RESF)
Set
LVIRF
POC reset confirm register (POCRES)
POCRES0
Clear Clear
TRAP
Caution An LVD circuit internal reset does not reset the LVD circuit.
Voltage detector reset signal
Power-on reset circuit reset signal
RESET
RESFCLM register read signal
RESF register read signal
Reset signal by illegal-memory access
Reset signal by RAM parity error
Reset signal by execution of illegal instruction
Clock monitor reset signal
Watchdog timer reset signal
CLKRF
CLM reset control
register (RESFCLM)
Internal bus
Figure 23-1. Block Diagram of Reset Function
Clear
Reset signal
Reset signal to LVIM/LVIS register
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____________
Figure 23-2. Timing of Reset by RESET Input
Wait for oscillation
accuracy stabilization
High-speed on-chip
oscillator clock
Starting X1 oscillation is specified by software.
High-speed system clock
(when X1 oscillation is selected)
Reset period
CPU status
Normal operation
(High-speed on-chip oscillator clock)
Normal operation
Reset processing : 388 to 673 μs (When LVD is used)
156 to 360 μs (When LVD off)
RESET
Internal reset signal
Delay
Port pin
(except P130)
Hi-Z
Note 1
Port pin
(P130)
Note 2
Figure 23-3. Timing of Reset Due to Execution of Illegal Instruction or Watchdog Timer Overflow
Wait for oscillation
accuracy stabilization
High-speed on-chip
oscillator clock
Starting X1 oscillation is specified by software.
High-speed system clock
(when X1 oscillation is selected)
CPU status
Normal operation
Reset period
(oscillation stop)
Reset processing
41 to 69 μs
Normal operation
(High-speed on-chip oscillator clock)
Execution of Illegal
Instruction/
Watchdog timer
overflow
Internal reset signal
Port pin
(except P130)
Hi-Z
Note 1
Port pin
(P130)
Note 2
____________
Notes 1.
2.
Segment output pin is pull-downed while POR reset or RESET input is stay active.
When P130 is set to high-level output before reset is effected, the output signal of P130 can be dummyoutput as a reset signal to an external device, because P130 outputs a low level when reset is effected. To
release a reset signal to an external device, set P130 to high-level output by software.
Caution A watchdog timer internal reset resets the watchdog timer.
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____________
Figure 23-4. Timing of Reset in STOP Mode by RESET Input
Wait for oscillation
accuracy stabilization
STOP instruction execution
High-speed on-chip
oscillator clock
Starting X1 oscillation is specified by software.
High-speed system clock
(when X1 oscillation is selected)
CPU status
Normal
operation
Stop Status
(oscillation stop)
Reset period
Normaloperation
(High-speed on-chip oscillator clock)
RESET
Reset processing : 388 to 673 μs (When LVD is used)
156 to 360 μs (When LVD off)
Internal reset signal
Delay
Port pin
(except P130)
Hi-Z
Note 1
Port pin
(P130)
Note 2
____________
Notes 1.
2.
Segment output pin is pull-downed while POR reset or RESET input is stay active.
When P130 is set to high-level output before reset is effected, the output signal of P130 can be dummyoutput as a reset signal to an external device, because P130 outputs a low level when reset is effected. To
release a reset signal to an external device, set P130 to high-level output by software.
Remark
For the reset timing of the power-on-reset circuit and voltage detector, see CHAPTER 24 POWER-ONRESET CIRCUIT and CHAPTER 25 VOLTAGE DETECTOR.
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Table 23-1. Operation Statuses During Reset Period
Item
During Reset Period
System clock
Clock supply to the CPU is stopped.
Main system clock
Subsystem clock
fIH
Operation stopped
fX
Operation stopped
fEX
Operation stopped
fXT
Operation stopped
fIL
Operation stopped
PLL
CPU
Code flash memory
Operation stopped (The system operates in the LV (low voltage main) mode after reading the
option byte)
Data flash memory
Operation stopped
RAM
Operation stopped (The value, however, is retained when the voltage is at least the power-onreset detection voltage.)
Port (latch)
See CHAPTER 2 PIN FUNCTIONS
Timer array unit
Operation stopped
Real-time clock (RTC)
Interval timer
Watchdog timer
Clock output/buzzer output
A/D converter
Serial array unit (SAU)
Serial interface LIN-UART (UARTF)
CAN controller
LCD controller/driver
LCD Bus I/F
Sound generator
Stepper motor controller/driver
(with ZPD)
Multiplier & divider, multiplyaccumulator
DMA controller
Power-on-reset function
Detection operation possible
Voltage detection function
Operation stopped (LVD detection is possible after reading the option byte)
External interrupt
Operation stopped
CRC
operation
function
High-speed CRC
General-purpose CRC
Illegal access detection function
RAM parity check function
RAM guard function
SFR guard function
Remark fIH:
fX:
High-speed on-chip oscillator clock
X1 oscillation clock
fEX: External main system clock
fXT:
XT1 oscillation clock
fIL:
Low-speed on-chip oscillator clock
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Table 23-2. Hardware Statuses After Reset Acknowledgment (1/7)
Hardware
After Reset
Note 1
Acknowledgment
Program counter (PC)
The contents of the
reset vector table
(0000H, 0001H) are
set.
Stack pointer (SP)
Undefined
Program status word (PSW)
06H
RAM
Data memory
Undefined
General-purpose registers
Undefined
Note 2
Note 2
Port registers (P0 to P9, P13 to P15) (output latches)
00H
Port mode registers 0 to 9, 13 to 15 (PM0 to PM9, PM13 to PM15)
FFH
Note3
Port input mode registers 0, 1, 3, 5 to 7, 13 (PIM0, PIM1, PIM3, PIM5 to PIM7, PIM13)
00H
Port output mode registers (POM)
00H
Pull-up resistor option registers 0, 1, 3 to 9, 13, 14 (PU0, PU1, PU3 to PU9, PU13, PU14)
00H (PU4 is 01H)
Clock operation mode control register (CMC)
00H
Clock operation status control register (CSC)
C0H
STOP status output control register (STPSTC)
00H
System clock control register (CKC)
00H
Oscillation stabilization time counter status register (OSTC)
00H
Oscillation stabilization time select register (OSTS)
07H
Peripheral enable registers 0, 1 (PER0, PER1)
00H
High-speed on-chip oscillator trimming register (HIOTRM)
Undefined
PLL control register (PLLCTL)
00H
PLL status register (PLLSTS)
00H
Peripheral clock select register (PCKSEL)
00H
FMP clock division selection register (MDIV)
00H
Timer input select registers 00, 01, 10, 11, 20, 21 (TIS00, TIS01, TIS10, TIS11, TIS20, TIS21)
00H
Timer array unit
Timer data registers 00 to 07, 10 to 17, 20 to 27
(TDR00 to TDR07, TDR10 to TDR17, TDR20 to TDR27)
0000H
Timer mode registers 00 to 07, 10 to 17, 20 to 27
(TMR00 to TMR07, TMR10 to TMR17, TMR20 to TMR27)
0000H
Timer status registers 00 to 07 (TSR00 to TSR07)
0000H
Timer counter registers 00 to 07, 10 to 17, 20 to 27 (TCR00 to TCR07, TCR10 to TCR17,
TCR20 to TCR27)
FFFFH
Timer channel enable status register 0 (TE0)
0000H
Notes 1.
Timer channel start register 0 (TS0)
0000H
Timer channel stop register 0 (TT0)
0000H
Timer clock select register 0 to 2(TPS0 to TPS2)
0000H
Timer output register 0 (TO0)
0000H
Timer output enable register 0 (TOE0)
0000H
Timer output level register 0 (TOL0)
0000H
Timer output mode registers 0 to 2 (TOM0 to TOM2)
0000H
During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
2.
When a reset is executed in the standby mode, the pre-reset status is held even after reset.
3.
Value afte reset is FEH only for PM3.
Remark
The special function register (SFR) mounted depend on the product. See 3.1.4 Special function registers
(SFRs) and 3.1.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers).
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Table 23-2. Hardware Statuses After Reset Acknowledgment (2/7)
Hardware
Timer input select else register (TISELSE)
Status After Reset
Note 1
Acknowledgment
00H
Sound generator pin select register (SGSEL)
00H
Timer output select register 00, 01, 10, 11, 20, 21 (TOS00, TOS01, TOS10, TOS11, TOS20, TOS21)
00H
Timer array unit
Noise filter enable register for each channel of TAU unit0 to 2 BCD correction
result register ( TNFEN0BCDAJ to TNFEN2)
00H
Sampling clock select of noise filter for unit0 to 2 (2 set) (TNFSMP0, TNFSMP1,
TNFSMP2)
00H
Noise filter clock select register for each channel of TAU unit0 to 2 (TNFCS0,
TNFCS1, TNFCS2)
00H
Second count register (SEC)
00H
Minute count register (MIN)
00H
Hour count register (HOUR)
12H
Week count register (WEEK)
00H
Real-time clock
Day count register (DAY)
01H
Month count register (MONTH)
01H
Year count register (YEAR)
00H
Watch error correction register (SUBCUD, SUBCUDW)
00H, 0000H
Alarm minute register (ALARMWM)
00H
Alarm hour register (ALARMWH)
12H
Alarm week register ALARMWW)
00H
Control register 0 (RTCC0)
00H
Control register 1 (RTCC1)
00H
RTC clock selection register (RTCCL)
00H
RTC1Hz pin select register (RTCSEL)
00H
Interval timer
Interval timer control register (ITMC)
7FFFH
Clock output/buzzer
Clock output select register 0 (CKS0)
00H
Watchdog timer enable register (WDTE)
1AH/9AH
output controller
Watchdog timer
A/D converter
Notes 1.
10-bit A/D conversion result register (ADCR)
0000H
8-bit A/D conversion result register (ADCRH)
00H
Mode registers 0 to 2 (ADM0 to ADM2)
00H
Conversion result comparison upper limit setting register (ADUL)
FFH
Conversion result comparison lower limit setting register (ADLL)
00H
A/D test register (ADTES)
00H
Analog input channel specification register (ADS)
00H
A/D port configuration register (ADPC)
00H
Note 2
During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
2.
Remark
The reset value of WDTE is determined by the option byte setting.
The special function register (SFR) mounted depend on the product. See 3.1.4 Special function registers
(SFRs) and 3.1.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers).
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Table 23-2. Hardware Statuses After Reset Acknowledgment (3/7)
Hardware
Serial array unit (SAU)
DMA controller
Interrupt
Note
1.
Status After Reset
Note 1
Acknowledgment
Serial data registers 00, 01, 10, 11 (SDR00, SDR01, SDR10, SDR11)
0000H
Serial status registers 00, 01, 10, 11 (SSR00, SSR01, SSR10, SSR11)
0000H
Serial flag clear trigger registers 00, 01, 10, 11 (SIR00, SIR01, SIR10, SIR11)
0000H
Serial mode registers 00, 01, 10, 11 (SMR00, SMR01, SMR10, SMR11)
0020H
Serial communication operation setting registers 00, 01, 10, 11 (SCR00, SCR01,
SCR10, SCR11)
0087H
Serial channel enable status registers 0, 1 (SE0, SE1)
0000H
Serial channel start registers 0, 1 (SS0, SS1)
0000H
Serial channel stop registers 0, 1 (ST0, ST1)
0000H
Serial clock select registers 0, 1 (SPS0, SPS1)
0000H
Serial output registers 0, 1 (SO0, SO1)
0303H
Serial output enable registers 0, 1 (SOE0, SOE1)
0000H
Serial output level registers 0, 1 (SOL0, SOL1)
0000H
Serial communication pin select register 0, 1(STSEL0, STSEL1)
00H
DMA SFR address registers 0 to 3 (DSA0 to DSA3)
00H
DMA RAM address registers 0 to 3 (DRA0 to DRA3)
00H
DMA byte count registers 0 to 3 (DBC0 to DBC3)
00H
DMA mode control registers 0 to 3 (DMC0 to DMC3)
00H
DMA operation control registers 0 to 3 (DRC0 to DRC3)
00H
Request flag registers 0L, 0H, 1L, 1H, 2L, 2H, 3L, 3H (IF0L, IF0H, IF1L, IF1H,
IF2L, IF2H, IF3L, IF3H)
00H
Mask flag registers 0L, 0H, 1L, 1H, 2L, 2H, 3L, 3H (MK0L, MK0H, MK1L,
MK1H, MK2L, MK2H, MK3L, MK3H)
FFH
Priority specification flag registers 00L, 00H, 01L, 01H, 02L, 02H, 03L, 03H,
10L, 10H, 11L, 11H, 12L, 12H, 13L, 13H (PR00L, PR00H, PR01L, PR01H,
PR02L, PR02H, PR03L, PR03H, PR10L, PR10H, PR11L, PR11H, PR12L,
PR12H, PR13L, PR13H)
FFH
External interrupt rising edge enable register 0 (EGP0)
00H
External interrupt falling edge enable register 0 (EGN0)
00H
During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
Remark
The special function register (SFR) mounted depend on the product. See 3.1.4 Special function registers
(SFRs) and 3.1.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers).
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Table 23-2. Hardware Statuses After Reset Acknowledgment (4/7)
Hardware
Status After Reset
Acknowledgment
UART
Note
1.
LIN-UART0 control register 0, 1 (UF0CTL0, UF0CTL1)
10H, 0FFFH
LIN-UART0 option control registers 0, to 2 (UF0OPT0 to UF0OPT2)
14H, 00H
LIN-UART0 status register (UF0STR)
0000H
LIN-UART0 status clear register (UF0STC)
0000H
LIN-UART0 wait transmit data register (UF0WTX)
0000H
LIN-UART0 8-bit wait transmit data register (UF0WTXB)
00H
LIN-UART0 ID setting register (UF0ID)
00H
LIN-UART0 buffer registers 0 to 8 (UF0BUF0 to UF0BUF8)
00H
LIN-UART0 buffer control register (UF0BUCTL)
0000H
LIN-UART0 transmit data register (UF0TX)
0000H
LIN-UART0 8-bit transmit data register (UF0TXB)
00H
LIN-UART0 receive data register (UF0RX)
0000H
LIN-UART0 receive data register (UF0RXB)
00H
LIN-UART1 control register 0 to 1 (UF1CTL0, UF1CTL1)
10H, 0FFFH
LIN-UART1 option control registers 0 to 2 (UF1OPT0 to UF1OPT2)
14H, 00H
LIN-UART1 status register (UF1STR)
0000H
LIN-UART1 status clear register (UF1WTX)
0000H
LIN-UART1 8-bit wait transmit data register (UF1WTXB)
00H
LIN-UART1 ID setting register (UF1ID)
00H
LIN-UART1 buffer registers 0 to 8 (UF1BUF0 to UF1BUF8)
00H
LIN-UART1 buffer control register (UF1BUCTL)
0000H
LIN-UART1 transmit data register (UF1TX)
0000H
LIN-UART1 8-bit transmit data register (UF1TXB)
00H
LIN-UART1 receive data register (UF1RX)
0000H
LIN-UART1 receive data register (UF1RXB)
00H
Note 1
During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
Remark
The special function register (SFR) mounted depend on the product. See 3.1.4 Special function registers
(SFRs) and 3.1.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers).
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Table 23-2. Hardware Statuses After Reset Acknowledgment (5/7)
Hardware
Status After Reset
Acknowledgment
CAN controller
Note
1.
CAN0 global module control register (C0GMCTRL)
0000H
CAN0 global block transmission control register (C0GMABT)
0000H
CAN0 global block transmission delay setting register (C0GMABTD)
00H
CAN0 global module clock select register (C0GMCS)
0FH
CAN0 module mask 1 to 4 register L (C0MASK1L to C0MASK4L)
Undefined
CAN0 module mask 1 to 4 register H (C0MASK1H to C0MASK4H)
Undefined
CAN0 module control register (C0CTRL)
0000H
CAN0 module last error information register (C0LEC)
00H
CAN0 module information register (C0INFO)
00H
CAN0 module error counter register (C0ERC)
0000H
CAN0 module interrupt enable register (C0IE)
0000H
CAN0 module interrupt status register (C0INTS)
0000H
CAN0 module bit rate prescaler register (C0BRP)
FFH
CAN0 module bit rate register (C0BTR)
370FH
CAN0 module last in-pointer register (C0LIPT)
Undefined
CAN0 module receive history list register (C0RGPT)
xx02H
CAN0 module last out-pointer register (C0LOPT)
Undefined
CAN0 module transmit history list register (C0TGPT)
xx02H
CAN0 module time stamp register (C0TS)
0000H
CAN0 message data byte 01 register 00 to 15 (C0MDB0100 to C0MDB0115)
Undefined
CAN0 message data byte 23 register 00 to 15 (C0MDB2300 to C0MDB2315)
Undefined
CAN0 message data Byte 45 register 00 to 15 (C0MDB4500 to C0MDB4515)
Undefined
CAN0 message data byte 67 register 00 to 15 (C0MDB6700 to C0MDB6715)
Undefined
CAN0 message data length register 00 to 15 (C0MDLC00 to C0MDLC15)
0xH
CAN0 message configuration register 00 to 15 (C0MCONF00 to C0MCONF15)
Undefined
CAN0 message ID register 00L to 15L (C0MIDL00 to C0MIDL15)
Undefined
CAN0 message ID register 00H to 15H (C0MIDH00 to C0MIDH15)
Undefined
CAN0 message control register 00 to 15 (C0MCTRL00 to C0MCTRL15)
Undefined
CAN1 global module control register (C1GMCTRL)
0000H
CAN1 global module clock select register (C1GMCS)
0FH
CAN1 global block transmission control register (C1GMABT)
0000H
CAN1 global block transmission delay setting register (C1GMABTD)
00H
CAN1 module mask 1 to 4 register L (C1MASK1L to C1MASK4L )
Undefined
CAN1 module mask 1 to 4 register H (C1MASK1H to C1MASK4H)
Undefined
CAN1 module control register (C1CTRL)
0000H
CAN1 module last error information register (C1LEC)
00H
CAN1 module information register (C1INFO)
00H
CAN1 module error counter register (C1ERC)
0000H
CAN1 module interrupt enable register (C1IE)
0000H
CAN1 module interrupt status register (C1INTS)
0000H
Note 1
During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
Remark
The special function register (SFR) mounted depend on the product. See 3.1.4 Special function registers
(SFRs) and 3.1.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers).
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Table 23-2. Hardware Statuses After Reset Acknowledgment (6/7)
Hardware
Status After Reset
Acknowledgment
CAN controller
Stepper motor
controller/driver
LCD controller
Sound generator
Note
1.
CAN1 module bit rate prescaler register (C1BRP)
FFH
CAN1 module bit rate register (C1BTR)
370FH
CAN1 module last in-pointer register (C1LIPT)
Undefined
CAN1 module receive history list register (C1RGPT)
xx02H
CAN1 module last out-pointer register (C1LOPT)
Undefined
CAN1 module transmit history list register (C1TGPT)
xx02H
CAN1 module time stamp register (C1TS)
0000H
CAN1 message data byte 01 register 00 to 15 (C1MDB0100 to C1MDB0115)
Undefined
CAN1 message data byte 23 register 00 to 15 (C1MDB2300 to C1MDB2315)
Undefined
CAN1 message data byte 45 register 00 to 15 (C1MDB4500 to C1MDB4515)
Undefined
CAN1 message data byte 67 register 00 to 15 (C1MDB6700 to C1MDB6715)
Undefined
CAN1 message data length register 00 to 15 (C1MDLC00 to C1MDLC15)
0xH
CAN1 message Configuration register 00 to 15 (C1MCONF00 to C1MCONF15)
Undefined
CAN1 message ID register 00L to 15L (C1MIDL00 to C1MIDL15)
Undefined
CAN1 message ID register 00H to 15H (C1MIDH00 to C1MIDH15)
Undefined
CAN1 message control register 00 to 15 (C1MCTRL00 to C1MCTRL15)
Undefined
Timer mode control register 0 (MCNTC0)
00H
Combined compare registers 1HW to 4HW (MCMP1HW to MCMP4HW)
0000H
Compare registers for sine side (MCMP10, MCMP20, MCMP30, MCMP40)
00H
Compare registers for cosine side (MCMP11, MCMP21, MCMP31, MCMP41)
00H
Compare control registers 1 to 4 (MCMPC1 to MCMPC4)
00H
Stepper motor port control register (SMPC)
00H
ZPD detection voltage setting registers 0, 1 (ZPDS0, ZPDS1)
00H
ZPD flag detection clock setting register (CMPCTL)
00H
ZPD operation control register (ZPDEN)
00H
LCD display data memory 0 to 52 (SEG0 to SEG52)
00H
LCD port function registers 0, 1, 3, 5, 7 to 9, 13 (LCDPF0, LCDPF1, LCDPF3,
LCDPF5, LCDPF7 to LCDPF9, LCDPF13)
00H
LCD mode register (LCDMD)
00H
LCD display mode register (LCDM)
00H
LCD clock control register (LCDC0)
00H
Control register (SG0CTL)
0000H
Frequency register SG0FL (SG0FL)
0000H
Frequency register SG0FH (SG0FH)
0000H
Amplitude register (SG0PWM)
0000H
Duration factor register (SG0SDF)
00H
Interrupt threshold register (SG0ITH)
0000H
Note 1
During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
Remark
The special function register (SFR) mounted depend on the product. See 3.1.4 Special function registers
(SFRs) and 3.1.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers).
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Table 23-2. Hardware Statuses After Reset Acknowledgment (7/7)
Status After Reset
Hardware
Acknowledgment
Multiplier & divider,
multiply-accumulator
Reset function
Voltage detector
Safety functions
Multiplication/division data register A (MDAL, MDAH)
0000H
Multiplication/division data register B (MDBL, MDBH)
0000H
Multiplication/division data register C (MDCL, MDCH)
0000H
Multiplication/division control register (MDUC)
00H
Reset control flag register (RESF)
Undefined
CLM reset control flag register (RESFCLM)
00H
POR reset confirm register (POCRES)
00H
Voltage detection register (LVIM)
00H
Voltage detection level register (LVIS)
00H/01H/81H
Flash memory CRC control register (CRC0CTL)
00H
Flash memory CRC operation result register (PGCRCL)
0000H
CRC input register (CRCIN)
00H
CRC data register (CRCD)
0000H
Invalid memory access detection control register (IAWCTL)
00H
Note 2
Note 2
Note 2
RAM parity error control register (RPECTL)
00H
Specific register manipulation protection register (GUARD)
00H
Flash memory
Data flash control register (DFLCTL)
00H
BCD correction circuit
BCD correction result register (BCDADJ)
Undefined
Notes 1.
Note 1
Notes 2, 3
During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
2.
These values vary depending on the reset source.
Reset Source
Register
___________
RESET
Reset by
Reset by
Reset by
Reset by
Reset by
Reset by
Input
POR
Execution
WDT
RAM parity
illegal-
LVD
error
memory
of Illegal
Instruction
RESF
TRAP bit
WDTRF bit
Cleared
Cleared
(0)
(0)
Set (1)
Held
Held
Set (1)
Held
IAWRF bit
Held
LVIM
LVISEN bit
LVIOMSK bit
Held
Held
Held
Held
Held
Set (1)
Held
Set (1)
Held
Cleared (0)
Held
Held
Held
Held
Cleared (0) Cleared (0) Cleared (0) Cleared (0) Cleared (0) Cleared (0)
Held
Held
Set (1)
Held
Held
Held
Set (1)
LVIRF bit
CLKRF bit
clock
monitor
access
RPERF bit
RESFCLM
Reset by
LVIF bit
LVIS
Cleared
Cleared
Cleared
Cleared
Cleared
Cleared
Cleared
(00H/01H/
(00H/01H/
(00H/01H/
(00H/01H/
(00H/01H/
(00H/01H/
(00H/01H/
81H)
81H)
81H)
81H)
81H)
81H)
81H)
3. The generation of reset signal other than an LVD reset sets as follows.
• When option byte LVIMDS1, LVIMDS0 = 1, 0: 00H
• When option byte LVIMDS1, LVIMDS0 = 1, 1: 81H
• When option byte LVIMDS1, LVIMDS0 = 0, 1: 01H
Remark The special function register (SFR) mounted depend on the product. See 3.1.4 Special function registers
(SFRs) and 3.1.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers).
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23.1 Register for Confirming Reset Source
Many internal reset generation sources exist in the RL78/D1A. The reset control flag register (RESF) is used to store
which source has generated the reset request.
The RESF register can be read by an 8-bit memory manipulation instruction.
____________
RESET input, reset by power-on-reset (POR) circuit, and reading the RESF register clear TRAP, WDTRF, RPERF,
IAWRF, and LVIRF flags.
Figure 23-5. Format of Reset Control Flag Register (RESF)
Address: FFFA8H
After reset: 00H
Note 1
R
Symbol
7
6
5
4
3
2
1
0
RESF
TRAP
0
0
WDTRF
0
RPERF
IAWRF
LVIRF
TRAP
Internal reset request by execution of illegal instruction
0
Internal reset request is not generated, or the RESF register is cleared.
1
Internal reset request is generated.
WDTRF
Internal reset request by watchdog timer (WDT)
0
Internal reset request is not generated, or the RESF register is cleared.
1
Internal reset request is generated.
RPERF
Internal reset request by RAM parity
0
Internal reset request is not generated, or the RESF register is cleared.
1
Internal reset request is generated.
IAWRF
Internal reset request by illegal-memory access
0
Internal reset request is not generated, or the RESF register is cleared.
1
Internal reset request is generated.
LVIRF
Notes 1.
2.
Note 2
Internal reset request by voltage detector (LVD)
0
Internal reset request is not generated, or the RESF register is cleared.
1
Internal reset request is generated.
The value after reset varies depending on the reset source.
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
Cautions 1. Do not read data by a 1-bit memory manipulation instruction.
2.
An instruction code fetched from RAM is not subject to parity error detection while it is being
3.
Because the RL78’s CPU executes lookahead due to the pipeline operation, the CPU might read
executed. However, the data read by the instruction is subject to parity error detection.
an uninitialized RAM area that is allocated beyond the RAM used, which causes a RAM parity
error. Therefore, when enabling RAM parity error resets (RPERDIS = 1), be sure to initialize the
used RAM area + 10 bytes.
The status of the RESF register when a reset request is generated is shown in Table 23-3.
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Table 23-3. RESF and RESFCLM Register Status When Reset Request Is Generated
___________
Reset
Source
RESET
Reset by
Reset by
Reset by
Reset by
Reset by
Reset by
Input
POR
Execution
WDT
RAM parity
illegal-
LVD
error
memory
of Illegal
Flag
Instruction
TRAP bit
Cleared (0)
Cleared (0)
Reset by
clock
monitor
access
Set (1)
Held
Held
Held
Held
Held
WDTRF bit
Held
Set (1)
Held
Held
Held
Held
RPERF bit
Held
Held
Set (1)
Held
Held
Held
IAWRF bit
Held
Held
Held
Set (1)
Held
Held
LVIRF bit
Held
Held
Held
Held
Set (1)
Held
CLKRF bit
Held
Held
Held
Held
Held
Set (1)
23.2 CLM Reset Control Flag Register
The CLM Reset Control Flag Register (RESFCLM) checks whether an internal reset generates. The CLKRF bit is
cleared when the RESFCLM is cleared. The register can be accessed in 8-bit unit. The CLKRF bit is cleared by RESET
input, power-on-reset (POR) circuit, and reading the register.
Figure 23-6. Format of CLM Reset Control Flag Register (RESFCLM)
Address: F00FAH
After reset: 00H
Note 1
R
Symbol
7
6
5
4
3
2
1
0
RESFCLM
0
0
0
0
0
0
0
CLKRF
CLKRF
Note
1.
Internal reset request by clock monitor
0
Internal reset request is not generated, or the RESFCLM is cleared.
1
Internal reset request is generated.
The value after reset varies depending on the reset source.
23.3 POR Reset Flag Register
The POC reset register (POCRES) checks the generation of POR reset, For POCRES, only writing ”1” is valid and
writing ”0” is invalid, Only a reset by the Power-on-Reset (POR) circuit can clear this register to 00H. If use the flag, it is
necessary to preset POCRES0 to ”1”.
Figure 23-7. Format of POR reset confirm register (POCRES)
Address: F00FBH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
POCRES
0
0
0
0
0
0
0
POCRES0
POCRES0
Internal reset request by POR reset
0
POR reset is generated or writing is not performed.
1
POR reset is not generated.
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CHAPTER 24 POWER-ON-RESET CIRCUIT
24.1 Functions of Power-on-reset Circuit
The power-on-reset circuit (POR) has the following functions.
Generates internal reset signal at power on.
The reset signal is released when the supply voltage (VDD) exceeds 1.51 V 0.06 V.
Compares supply voltage (VDD) and detection voltage (VPDR = 1.50 V 0.06 V), generates internal reset signal when
VDD < VPDR.
Caution If an internal reset signal is generated in the POR circuit, TRAP, WDTRF, RPERF, IAWRF, and
LVIRF flags of the reset control flag register (RESF) is cleared.
Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag that
indicates the reset source is located in the reset control flag register (RESF) for when an internal reset
signal is generated by the watchdog timer (WDT), voltage-detector (LVD), illegal instruction execution,
RAM parity error, or illegal-memory access. The RESF register is not cleared to 00H and the flag is set to
1 when an internal reset signal is generated by the watchdog timer (WDT), voltage-detector (LVD), illegal
instruction execution, RAM parity error, or illegal-memory access.
For details of the RESF register, see CHAPTER 23 RESET FUNCTION.
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24.2 Configuration of Power-on-reset Circuit
The block diagram of the power-on-reset circuit is shown in Figure 24-1.
Figure 24-1. Block Diagram of Power-on-reset Circuit
VDD
VDD
+
Internal reset signal
−
Reference
voltage
source
24.3 Operation of Power-on-reset Circuit
An internal reset signal is generated on power application. When the supply voltage (VDD) exceeds the detection
voltage (VPDR = 1.51 V 0.06 V), the reset status is released.
The supply voltage (VDD) and detection voltage (VPDR = 1.50 V 0.06 V) are compared. When VDD < VPDR, the
internal reset signal is generated.
The timing of generation of the internal reset signal by the power-on-reset circuit and voltage detector is shown below.
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Figure 24-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit
and Voltage Detector (1/2)
(a) When LVD is interrupt & reset mode (VLVDL = 2.75 V, VLVDH = 2.92 V (option byte 000C1/020C1H = 7AH)
Supply voltage
(VDD)
Note 4
VLVDH
VLVDL
2.7 VNote 1
VPOR = 1.51 V (TYP.)
VPDR = 1.50 V (TYP.)
0V
Wait for oscillation
accuracy stabilizationNote 3
Wait for oscillation
accuracy stabilizationNote 3
High-speed on-chip
oscillator clock (fIH)
Starting oscillation is
specified by software
High-speed
system clock (fMX)
(when X1 oscillation
is selected)
CPU
Starting oscillation is
specified by software
Normal operation
(high-speed on-chip
oscillation clock)Note 2
Operation
stops
Reset processing time Note 5
POR processing time
Reset
period
(oscillation
stop)
Normal operation
(high-speed on-chip
oscillation clock)Note 2
Reset processing timeNote 5
Operation stops
POR processing time
Internal reset signal
INTLVI
Notes 1.
The operation guaranteed range is 2.7 V VDD 5.5 V. To make the state at lower than 2.7 V reset state
when the supply voltage falls, use the reset function of the voltage detector, or input the low level to the
____________
RESET pin.
2.
The high-speed on-chip oscillator clock and a high-speed system clock or subsystem clock can be selected
as the CPU clock. To use the X1 clock, use the oscillation stabilization time counter status register (OSTC)
to confirm the lapse of the oscillation stabilization time. To use the XT1 clock, use the timer function for
confirmation of the lapse of the stabilization time.
3.
The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed onchip oscillator clock.
4.
After the first interrupt request signal (INTLVI) is generated, the LVIL and LVIMD bits of the voltage
detection level register (LVIS) are automatically set to 1. If the operating voltage returns to 2.7 V or higher
without falling below the voltage detection level (VLVDL), after INTLVI is generated, perform the required
backup processing, and then use software to specify the following settings in order (see Figure 25-8.
Initial Setting of Interrupt and Reset Mode).
5.
Remark
Reset processing time: 497 to 720 μ s
VLVDH, VLVDL: LVD detection voltage
VPOR: POR power supply rise detection voltage
VPDR: POR power supply fall detection voltage
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Figure 24-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit
and Voltage Detector (2/2)
(b) When LVD is OFF (option byte 000C1H/020C1H: VPOC2 = 1B)
Supply voltage
(VDD)
2.7 VNote 1
VPOR = 1.51 V (TYP.)
VPDR = 1.50 V (TYP.)
0V
Wait for oscillation
accuracy stabilizationNote 2
Wait for oscillation
accuracy stabilizationNote 2
high-speed
oscillation clock (fIH)
Starting oscillation is
specified by software
High-speed
system clock (fMX)
(when X1 oscillation
is selected)
Reset processingNote 4
Operation
CPU
stops
Starting oscillation is
specified by software
Normal operation
(high-speed on-chip
oscillation clock)Note 3
Reset
period
(oscillation
stop)
Reset processingNote 4
Normal operation
(high-speed on-chip
oscillation clock)Note 3
Operation stops
Internal reset signal
Notes 1.
The operation guaranteed range is 2.7 V VDD 5.5 V. To make the state at lower than 2.7 V reset state
when the supply voltage falls, use the reset function of the voltage detector, or input the low level to the
RESET pin.
2.
The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed onchip oscillator clock.
3.
The high-speed on-chip oscillator clock and a high-speed system clock or subsystem clock can be selected
as the CPU clock. To use the X1 clock, use the oscillation stabilization time counter status register (OSTC)
to confirm the lapse of the oscillation stabilization time. To use the XT1 clock, use the timer function for
confirmation of the lapse of the stabilization time.
4.
Remark
For details about the reset processing time, see Figure 5-18.
VPOR: POR power supply rise detection voltage
VPDR: POR power supply fall detection voltage
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24.4 Cautions for Power-on-reset Circuit
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POR detection voltage
(VPOR, VPDR), the system may be repeatedly reset and released from the reset status. In this case, the time from release
of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software
counter that uses a timer, and then initialize the ports.
Figure 24-3. Example of Software Processing After Reset Release (1/2)
If supply voltage fluctuation is 50 ms or less in vicinity of POR detection voltage
Reset
Initialization
processing
; Check the reset source, etc.Note 2
Power-on-reset
Setting timer array unit
(to measure 50 ms)
; fCLK = high-speed on-chip oscillation clock (32.32 MHz (MAX.))
Source: fMCK (32.32 MHz (MAX.))/211,
where comparison value = 789: ≅ 50 ms
Timer starts (TS0n = 1).
Clearing WDT
Note 1
No
50 ms has passed?
(TMIF0n = 1?)
Yes
Initialization
processing
Notes 1.
2.
Remark
; Initial setting for port.
Setting of division ratio of system clock,
such as setting of timer or A/D converter.
If reset is generated again during this period, initialization processing is not started.
A flowchart is shown on the next page.
n = 0 to 7
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CHAPTER 24 POWER-ON-RESET CIRCUIT
Figure 24-3. Example of Software Processing After Reset Release (2/2)
Checking reset source
Check reset source
TRAP of RESF
register = 1?
Yes
No
Reset processing by
illegal instruction execution Note
WDTRF of RESF
register = 1?
Yes
No
Reset processing by
watchdog timer
RPERF of RESF
register = 1?
Yes
No
Reset processing by
RAM parity error
IAWRF of RESF
register = 1?
Yes
No
Reset processing by
illegal-memory access
LVIRF of RESF
register = 1?
Yes
No
Reset processing by
voltage detector
Power-on-reset/external
reset generated
Note
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
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CHAPTER 25 VOLTAGE DETECTOR
CHAPTER 25 VOLTAGE DETECTOR
25.1 Functions of Voltage Detector
The voltage detector (LVD) has the following functions.
The LVD circuit compares the supply voltage (VDD) with the detection voltage (VLVDH, VLVDL), and generates an
internal reset or internal interrupt signal.
The detection level for the power supply detection voltage (VLVDH, VLVDL) can be selected by using the option byte as
one of 6 levels (For details, see CHAPTER 28 OPTION BYTE).
Operable in STOP mode.
The following three operation modes can be selected by using the option byte.
(a) Interrupt & reset mode (option byte LVIMDS1, LVIMDS0 = 1, 0)
For the two detection voltages selected by the option byte 000C1H/020C1H, the high-voltage detection level
(VLVDH) is used for generating interrupts and ending resets, and the low-voltage detection level (VLVDL) is used for
triggering resets.
(b) Reset mode (option byte LVIMDS1, LVIMDS0 = 1, 1)
The detection voltage (VLVD) selected by the option byte 000C1H/020C1H is used for triggering and ending resets.
(c) Interrupt mode (option byte LVIMDS1, LVIMDS0 = 0, 1)
The detection voltage (VLVD) selected by the option byte 000C1H/020C1H is used for generating interrupts.
Two detection voltages (VLVDH, VLVDL) can be specified in the interrupt & reset mode, and one (VLVD) can be specified in
the reset mode and interrupt mode.
The reset and interrupt signals are generated as follows according to the option byte (LVIMDS0, LVIMDS1) selection.
Interrupt & reset mode
Reset mode
Interrupt mode
(LVIMDS1, LVIMDS0 = 1, 0)
(LVIMDS1, LVIMDS0 = 1, 1)
(LVIMDS1, LVIMDS0 = 0, 1)
Generates an internal interrupt signal
Generates an internal reset signal when
when VDD < VLVDH, and an internal reset
VDD < VLVD and releases the reset signal
when VDD < VLVDL.
when VDD VLVD.
Releases the reset signal when VDD
VLVDH.
The state of an internal reset by LVD is
retained until VDD VLVD immediately after
reset generation. The internal reset is
released when VDD VLVD is detected.
After that, an interrupt request signal
(INTLVI) is generated when VDD < VLVD or
VDD VLVD is detected.
While the voltage detector is operating, whether the supply voltage is more than or less than the detection level can be
checked by reading the voltage detection flag (LVIF: bit 0 of the voltage detection register (LVIM)).
Bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if reset occurs. For details of the RESF register, see
CHAPTER 23 RESET FUNCTION.
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CHAPTER 25 VOLTAGE DETECTOR
25.2 Configuration of Voltage Detector
The block diagram of the voltage detector is shown in Figure 25-1.
Figure 25-1. Block Diagram of Voltage Detector
VDD
VDD
VLVDH
VLVDL
Option byte (000C1H)
LVIS1, LVIS0
Controller
Internal reset signal
+
Selector
Voltage detection
level selector
N-ch
−
INTLVI
Reference
voltage
source
LVIOMSK
Option byte (000C1H)
VPOC2 to VPOC0
Voltage detection
register (LVIM)
LVIMD LVILV
LVIF
Voltage detection
level register (LVIS)
Internal bus
25.3 Registers Controlling Voltage Detector
The voltage detector is controlled by the following registers.
Voltage detection register (LVIM)
Voltage detection level register (LVIS)
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CHAPTER 25 VOLTAGE DETECTOR
(1) Voltage detection register (LVIM)
This register is used to specify whether to enable or disable rewriting the voltage detection level register (LVIS), as
well as to check the LVD output mask status.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Figure 25-2. Format of Voltage Detection Register (LVIM)
Address: FFFA9H
After reset: 00H
Note 1
R/W
Note 2
Symbol
6
5
4
3
2
LVIM
LVISEN
0
0
0
0
0
LVIOMSK
LVIF
Specification of whether to enable or disable rewriting the voltage detection level
register (LVIS)
LVISEN
0
Disabling rewriting
1
Enabling rewriting
Note 3
LVIOMSK
Mask status flag of LVD output
0
Mask is invalid
1
Mask is valid
Note 4
LVIF
Notes 1.
Voltage detection flag
0
Supply voltage (VDD) detection voltage (VLVD), or when LVD operation is disabled
1
Supply voltage (VDD) < detection voltage (VLVD)
The reset value changes depending on the reset source.
If the LVIS register is reset by LVD, it is not reset but holds the current value. Only the bit 7 of this
register is cleared by “0”, if a reset other than by LVD is effective.
2.
Bits 0 and 1 are read-only.
3.
This can only be set when LVIMDS1 and LVIMDS0 are set to 1 and 0 (interrupt and reset mode) by the
option byte.
4. LVIOMSK bit is automatically set to “1” in the following periods and reset or interruption by LVD is masked.
Period during LVISEN = 1
Waiting period from the time when LVD interrupt is generated until LVD detection voltage becomes
stable
Waiting period from the time when the value of LVILV bit changes until LVD detection voltage
becomes stable.
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CHAPTER 25 VOLTAGE DETECTOR
(2) Voltage detection level register (LVIS)
This register selects the voltage detection level.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation input sets this register to 00H/01H/81H
Note1
.
Figure 25-3. Format of Voltage Detection Level Select Register (LVIS)
Address: FFFAAH
After reset: 00H/01H/81H
Note 1
R/W
Symbol
6
5
4
3
2
1
LVIS
LVIMD
0
0
0
0
0
0
LVILV
LVIMD
Operation mode of voltage detection
0
Interrupt mode
1
Reset mode
LVILV
Notes 1.
Note 2
Note 2
LVD detection level
0
High-voltage detection level (VLVDH)
1
Low-voltage detection level (VLVDL or VLVD)
The reset value changes depending on the reset source and the setting of the option byte.
This register is not cleared (00H) by LVD reset.
The generation of reset signal other than an LVD reset sets as follows.
When option byte LVIMDS1, LVIMDS0 = 1, 0: 00H
When option byte LVIMDS1, LVIMDS0 = 1, 1: 81H
When option byte LVIMDS1, LVIMDS0 = 0, 1: 01H
2.
Writing “0” can only be allowed when LVIMDS1 and LVIMDS0 are set to 1 and 0 (interrupt and reset
mode) by the option byte. In other cases, writing is not allowed and the value is switched automatically
when reset or interrupt is generated.
Cautions 1.
Only rewrite the value of the LVIS register after setting the LVISEN bit (bit 7 of the LVIM register)
to 1.
2.
Specify the LVD operation mode and detection voltage (VLVDH, VLVDL) by using the option byte
(000C1H). Table 25-1 shows the option byte (000C1H) settings. For details about the option
byte, see CHAPTER 28 OPTION BYTE.
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CHAPTER 25 VOLTAGE DETECTOR
Table 25-1. LVD Operation Mode and Detection Voltage Settings for User Option Byte (000C1H/020C1H)
LVD setting (interrupt & reset mode)
Detection voltage
VLVDH
Option byte setting value
VLVDL
Mode setting
Rise
Fall
Fall
LVIMDS1
LVIMDS0
VPOC2
VPOC1
VPOC0
LVIS1
LVIS0
2.92 V
2.86 V
2.75 V
1
0
0
1
1
1
0
3.02 V
2.96 V
0
1
4.06 V
3.98 V
0
0
Other than the above
Setting prohibited
LVD setting (reset mode)
Detection voltage
Option byte setting value
VLVD
Rise
Mode setting
Fall
LVIMDS1
LVIMDS0
VPOC2
VPOC1
VPOC0
LVIS1
LVIS0
1
1
0
1
1
1
1
2.81 V
2.75 V
2.92 V
2.86 V
1
1
1
0
3.02 V
2.96 V
1
1
0
1
3.13 V
3.06 V
0
1
0
0
3.75 V
3.67 V
1
0
0
0
4.06 V
3.98 V
1
1
0
0
Other than the above
Remark
Setting prohibited
: Don’t care.
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CHAPTER 25 VOLTAGE DETECTOR
LVD setting (interrupt mode)
Detection voltage
Option byte setting value
VLVD
Rise
Mode setting
Fall
LVIMDS1
LVIMDS0
VPOC2
VPOC1
VPOC0
LVIS1
LVIS0
0
1
0
1
1
1
1
2.81 V
2.75 V
2.92 V
2.86 V
1
1
1
0
3.02 V
2.96 V
1
1
0
1
3.13 V
3.06 V
0
1
0
0
3.75 V
3.67 V
1
0
0
0
4.06 V
3.98 V
1
1
0
0
Other than the above
Setting prohibited
Remark
: Don’t care.
Caution
External RESET must be used during power supply rising up to 2.7 V.
____________
LVD setting (LVD off)
Detection voltage
Option byte setting value
VLVD
Mode setting
Rise
Fall
LVIMDS1
LVIMDS0
VPOC2
VPOC1
VPOC0
LVIS1
LVIS0
0/1
1
1
Other than the above
Setting prohibited
Remark
: Don’t care.
Caution
External RESET must be used during power supply rising up to 2.7 V.
____________
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CHAPTER 25 VOLTAGE DETECTOR
25.4 Operation of Voltage Detector
25.4.1 When used as reset mode
When starting operation
Start in the following initial setting state.
Specify the operation mode (the reset mode (LVIMDS1, LVIMDS0 = 1, 1)) and the detection voltage (VLVD) by
using the option byte 000C1H/020C1H.
Set bit 7 (LVISEN) of the voltage detection register (LVIM) to 0 (disable rewriting of voltage detection level
register (LVIS)).
When the option byte LVIMDS1 and LVIMDS0 are set to 1, the initial value of the LVIS register is set to 81H.
Bit 7 (LVIMD) is 1 (reset mode).
Bit 0 (LVILV) is 1 (low-voltage detection level: VLVD).
Figure 25-4 shows the timing of the internal reset signal generated by the voltage detector.
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CHAPTER 25 VOLTAGE DETECTOR
Figure 25-4. Timing of Voltage Detector Internal Reset Signal Generation
(Option Byte LVIMDS1, LVIMDS0 = 1, 1)
Supply voltage (VDD)
VLVD
VPOR = 1.51 V (TYP.)
VPDR = 1.50 V (TYP.)
Time
Cleared
LVIF flag
LVIMD flag
H
Not
cleared
Not
cleared
LVILV flag
H
Not
cleared
Not
cleared
Cleared
LVIRF flag
RESF regista
LVD reset signal
Cleared by
software
Cleared by
software
POR reset signal
Internal reset signal
Remark
VPOR: POR power supply rise detection voltage
VPDR: POR power supply fall detection voltage
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CHAPTER 25 VOLTAGE DETECTOR
25.4.2 When used as interrupt mode
When starting operation
Specify the operation mode (the interrupt mode (LVIMDS1, LVIMDS0 = 0, 1)) and the detection voltage (VLVD)
by using the option byte 000C1H/020C1H.
Start in the following initial setting state.
Set bit 7 (LVISEN) of the voltage detection register (LVIM) to 0 (disable rewriting of voltage detection level
register (LVIS)).
When the option byte LVIMDS1 is clear to 0 and LVIMDS0 is set to 1, the initial value of the LVIS register is
set to 01H.
Bit 7 (LVIMD) is 0 (interrupt mode).
Bit 0 (LVILV) is 1 (low-voltage detection level: VLVD).
Figure 25-5 shows the timing of the internal interrupt signal generated by the voltage detector.
____________
Caution
External RESET must be used during power supply rising up to 2.7 V.
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CHAPTER 25 VOLTAGE DETECTOR
Figure 25-5. Timing of Voltage Detector Internal Interrupt Signal Generation
(Option Byte LVIMDS1, LVIMDS0 = 0, 1)
Supply voltage (VDD)
VLVD
VPOR = 1.51 V (TYP.)
VPDR = 1.50 V (TYP.)
Time
LVIMK flag
(interrupt mask)
(set by software)
HNote 1
Cleared by
software
Cleared
LVIF flag
LVIMD flag
LVILV flag
H
INTLVI
LVIIF flag
LVD reset signal
POR reset signal
Internal reset signal
Note The LVIMK flag is set to “1” by reset signal generation.
Remark
VPOR: POR power supply rise detection voltage
VPDR: POR power supply fall detection voltage
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CHAPTER 25 VOLTAGE DETECTOR
25.4.3 When used as interrupt and reset mode
When starting operation
Specify the operation mode (the interrupt and reset (LVIMDS1, LVIMDS0 = 1, 0)) and the detection voltage
(VLVDH, VLVDL) by using the option byte 000C1H/020C1H.
Start in the following initial setting state.
Set bit 7 (LVISEN) of the voltage detection register (LVIM) to 0 (disable rewriting of voltage detection level
register (LVIS)).
When the option byte LVIMDS1 is set to 1 and LVIMDS0 is cleared to 0, the initial value of the LVIS register is
set to 00H.
Bit 7 (LVIMD) is 0 (interrupt mode).
Bit 0 (LVILV) is 0 (high-voltage detection level: VLVDH).
Figure 25-6 shows the timing of the internal reset signal and interrupt signal generated by the voltage detector.
Perform the processing according to Figure 25-7 Processing Procedure after an Interrupt is Generated and
Figure 25-8 Initial Setting of Interrupt and Reset Mode.
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CHAPTER 25 VOLTAGE DETECTOR
Figure 25-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation
(Option Byte LVIMDS1, LVIMDS0 = 1, 0) (1/2)
If a reset is not generated after releasing
the mask, clear LVIMD, and the MCU returns
to normal operation.
Supply voltage (V DD)
V LVDH
V LVDL
V POR = 1.51 V ( TYP.)
V PDR = 1.50 V ( TYP.)
Time
LVIMK flag
(set by software)
Note 1
Cleared by
software
Operation status
RESET
Normal
operation
Normal
operation
Save
processing
Cleared by
software
Wait for stabilization by software (400 s or 5 clocks of fIL) Note 3
RESET
Normal
operation
RESET
Save processing
Cleared
LVIF flag
LVISEN flag
(set by software)
LVIOMSK flag
LVIMD flag
Cleared by
softwareNote 3
LVILV flag
LVIRF flag
Cleared by
softwareNote 2
Cleared by
software
Cleared
LVD reset signal
POR reset signal
Internal reset signal
INTLVI
LVIIF flag
(Notes and Remark are listed on the next page.)
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Notes 1.
2.
CHAPTER 25 VOLTAGE DETECTOR
The LVIMK flag is set to “1” by reset signal generation.
After an interrupt is generated, perform the processing according to Figure 25-7 Processing Procedure
after an Interrupt is Generated in interrupt and reset mode.
3.
After a reset is released, perform the processing according to Figure 25-8 Initial Setting of Interrupt and
Reset Mode in interrupt and reset mode.
Remark
VPOR: POR power supply rise detection voltage
VPDR: POR power supply fall detection voltage
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CHAPTER 25 VOLTAGE DETECTOR
Figure 25-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation
(Option Byte LVIMDS1, LVIMDS0 = 1, 0) (2/2)
If VDD < VLVDH after releasing the mask, a reset
is generated because of LVIMD = 1 (reset mode).
Supply voltage (VDD)
VLVDH
VLVDL
VPOR = 1.51 V (TYP.)
VPDR = 1.50 V (TYP.)
Time
LVIMK flag
(set by software)
H Note 1
Cleared by
software
Operation status
RESET
Normal
operation
Cleared by
software
Wait for stabilization by software (400 s or 5 clocks of fIL) Note 3
RESET
Normal
operation
RESET
Save processing
Cleared
LVIF flag
LVISEN flag
(set by software)
LVIOMSK flag
LVIMD flag
Cleared by
software Note 3
LVILV flag
Cleared by
software Note 2
LVIRF flag
Cleared by
software
Cleared
LVD reset signal
POR reset signal
Internal reset signal
INTLVI
LVIIF flag
(Notes and Remark are listed on the next page.)
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Notes 1.
2.
CHAPTER 25 VOLTAGE DETECTOR
The LVIMK flag is set to “1” by reset signal generation.
After an interrupt is generated, perform the processing according to Figure 25-7 Processing Procedure
after an Interrupt is Generated in interrupt and reset mode.
3.
After a reset is released, perform the processing according to Figure 25-8 Initial Setting of Interrupt and
Reset Mode in interrupt and reset mode.
Remark
VPOR: POR power supply rise detection voltage
VPDR: POR power supply fall detection voltage
Figure 25-7. Processing Procedure after an Interrupt is Generated
INTLVI generated
Save processing
LVISEN = 1
No
Perform required save processing.
Set the LVISEN bit to 1 to mask voltage detection
(LVIOMSK = 1).
LVIOMSK = 1
Yes
LVILV = 0
LVISEN = 0
No
Set the LVILV bit to 0 to set the high-voltage
detection level (VLVDH).
Set the LVISEN bit to 0 to enable voltage
detection.
LVIOMSK = 0
Yes
Yes
LVD reset generated
No
LVISEN = 1
The MCU returns to normal operation when
internal reset by voltage detector (LVD) is not
generated, since a condition of VDD becomes
VDD VLVDH.
Set the LVISEN bit to 1 to mask voltage detection
(LVIOMSK = 1)
No
LVIOMSK = 1
Yes
Reset
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LVIMD = 0
Set the LVIMD bit to 0 to set interrupt mode.
LVISEN = 0
Set the LVISEN bit to 0 to enable voltage
detection.
Normal operation
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CHAPTER 25 VOLTAGE DETECTOR
When setting an interrupt and reset mode (LVIMDS1, LVIMDS0 = 1, 0), voltage detection stabilization wait time for 400 s
or 5 clocks of fIL is necessary after LVD reset is released (LVIRF = 1). After waiting until voltage detection stabilizes, clear
the LVIMD bit to 0 for initialization. While voltage detection stabilization wait time is being counted and when the LVIMD bit
is rewritten, set LVISEN to 1 to mask a reset or interrupt generation by LVD.
Figure 24-8 shows the procedure for initial setting of interrupt and reset mode.
Figure 25-8. Initial Setting of Interrupt and Reset Mode
Power application
Reset source determined
Refer to Figure 25-9 Checking reset source.
LVIRF = 1
Check internal reset generation by LVD circuit.
No
Yes
LVISEN = 1
Set the LVISEN bit to 1 to mask voltage detection
(LVIOMSK = 1)
LVIOMSK = 1
No
Yes
Voltage detection stabilization
Count 400 s or 5 clocks of fIL by software.
wait time
LVIMD = 0
Set the LVIMD bit to 0 to set interrupt mode.
LVISEN = 0
Set the LVISEN bit to 0 to enable voltage detection.
Normal operation
Remark
fIL: Low-speed on-chip oscillator clock frequency
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CHAPTER 25 VOLTAGE DETECTOR
25.5 Cautions for Voltage Detector
(1) Checking reset source
When a reset occurs, check the reset source by using the following method.
Figure 25-9. Checking reset source
Check reset source
TRAP of RESF
register = 1?
Yes
No
Reset processing by
illegal instruction execution Note
WDTRF of RESF
register = 1?
Yes
No
Reset processing by
watchdog timer
RPERF of RESF
register = 1?
Yes
No
Reset processing by
RAM parity error
IAWRF of RESF
register = 1?
Yes
No
Reset processing by
illegal-memory access
LVIRF of RESF
register = 1?
No
Yes
Power-on-reset/external
reset generated
Reset processing by
voltage detector
Note
When instruction code FFH is executed.
Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
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CHAPTER 25 VOLTAGE DETECTOR
(2) Delay from the time LVD reset source is generated until the time LVD reset has been generated or released
There is some delay from the time supply voltage (VDD) < LVD detection voltage (VLVD) until the time LVD reset has
been generated.
In the same way, there is also some delay from the time LVD detection voltage (VLVD) supply voltage (VDD) until the
time LVD reset has been released (see Figure 25-10).
Figure 25-10. Delay from the Time LVD Reset Source is Generated until the Time LVD Reset Has been Generated or
Released
Supply voltage (VDD)
VLVD
Time
LVIF flag
LVD reset signal
:
Detection delay (300 s (MAX.))
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CHAPTER 26 SAFETY FUNCTIONS
CHAPTER 26 SAFETY FUNCTIONS
26.1 Overview of Safety Functions
The RL78/D1A is provided with the following safety functions to meet the IEC 60730 and IEC 61508 safety standards.
The functions are intended to detect failures through microcomputer’s self-diagnosis and to stop the system safely.
(1) Flash memory CRC operation function (high-speed CRC and general-purpose CRC)
This detects errors associated to data in the flash memory by performing CRC operations.
Either of the CRC operations below can be used according to the application and conditions of use.
High-speed CRC: Can be used for high-speed check of the entire code flash memory area while the CPU is
stopped in the initialization routine.
General-purpose CRC: Can be used for not only check of code flash memory area but versatile check while
the CPU is running.
(2) RAM parity error detection function
This detects parity errors when the RAM is read as data.
(3) RAM guard function
This prevents RAM data from being rewritten when the CPU freezes.
(4) SFR guard function
This prevents SFRs from being rewritten when the CPU freezes.
(5) Invalid memory access detection function
This detects access to invalid memory areas (non-existent areas or access-restricted areas).
(6) Frequency detection function
This uses TAU to detect the oscillation frequency.
(7) A/D test function
This is used to perform a self-check of A/D conversion by performing A/D conversion on the internal reference
voltage.
(8) Clock monitor function
This detects the stop of oscillation of main system clock (fMAIN) and PLL clock (fPLL).For more details, see 5.4 Clock
monitor (CLM).
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CHAPTER 26 SAFETY FUNCTIONS
26.2 Registers Used by Safety Functions
Each safety function uses the following registers.
Register Name
Flash memory CRC control register (CRC0CTL)
Safety Functions
Flash memory CRC operation function (high-speed CRC)
Flash memory CRC operation result register (PGCRCL)
CRC input register (CRCIN)
CRC operation function (general-purpose CRC)
CRC data register (CRCD)
RAM parity error control register (RPECTL)
RAM parity error detection function
Invalid memory access detection control register (IAWCTL)
RAM guard function
SFR guard function
Invalid memory access detection function
Timer input select register 0 (TIS0)
Frequency detection function
A/D test register (ADTES)
A/D test function
Analog input channel specification register (ADS)
Specification of the analog voltage input channel
For details of the registers, refer to 26.3 Operations of Safety Functions.
26.3 Operations of Safety Functions
26.3.1 Flash Memory CRC Operation Function (High-Speed CRC)
The IEC 60730 standard requires verification of data in flash memory and recommends CRC as the means for
verification. With the high-speed CRC operation function, the entire code flash memory area can be checked in the
initialization routine. This function is available only in HALT mode of the main system clock through the program on RAM.
With the high-speed CRC operation function, the CPU is stopped and a 32-bit data unit is read from the flash memory
in a clock cycle to perform operation on the data. Therefore, check can be completed in a short time (for example, 64Kbyte flash memory checked in 512s at 32 MHz frequency).
The CRC generator polynomial is X16 + X12 + X5 + 1 of CRC-16-CCITT.
Operation is done with the MSB first, i.e., from bit 31 to bit 0.
Caution Since the monitor program is allocated for on-chip debugging, a different operation result is
obtained.
Remark
Since the general-purpose CRC uses the LSB-fist method, a different operation result is obtained.
26.3.1.1 Flash memory CRC control register (CRC0CTL)
This register is used to control the operation of the high-speed CRC ALU, as well as to specify the operation range.
The CRC0CTL register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
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Figure 26-1. Format of Flash Memory CRC Control Register (CRC0CTL)
Address: F02F0H
After reset: 00H
R/W
Symbol
6
5
4
3
2
1
0
CRC0CTL
CRC0EN
0
FEA5
FEA4
FEA3
FEA2
FEA1
FEA0
CRC0EN
Control of high-speed CRC ALU operation
0
Stop the operation.
1
Start the operation according to HALT instruction execution.
FEA5
FEA4
FEA3
FEA2
FEA1
FEA0
0
0
0
0
0
0
0 to 3FFBH (16 K - 4 bytes)
0
0
0
0
0
1
0 to 7FFBH (32 K - 4 bytes)
0
0
0
0
1
0
0 to BFFBH (48 K - 4 bytes)
0
0
0
0
1
1
0 to FFFBH (64 K - 4 bytes)
0
0
0
1
0
0
0 to 13FFBH (80 K to 4 bytes)
0
0
0
1
0
1
0 to 17FFBH (96 K to 4 bytes)
0
0
0
1
1
0
0 to 1BFFBH (112 K to 4 bytes)
0
0
0
1
1
1
0 to 1FFFBH (128 K to 4 bytes)
0
0
1
0
0
0
0 to 23FFBH (144 K to 4 bytes)
0
0
1
0
0
1
0 to 27FFBH (160 K to 4 bytes)
0
0
1
0
1
0
0 to 2BFFBH (176 K to 4 bytes)
0
0
1
0
1
1
0 to 2FFFBH (192 K to 4 bytes)
0
0
1
1
0
0
0 to 33FFBH (208 K to 4 bytes)
0
0
1
1
0
1
0 to 37FFBH (224 K to 4 bytes)
0
0
1
1
1
0
0 to 3BFFBH (240 K to 4 bytes)
0
0
1
1
1
1
0 to 3FFFBH (256 K to 4 bytes)
0
1
0
0
0
0
0 to 43FFBH (272 K to 4 bytes)
0
1
0
0
0
1
0 to 47FFBH (288 K to 4 bytes)
0
1
0
0
1
0
0 to 4BFFBH (304 K to 4 bytes)
0
1
0
0
1
1
0 to 4FFFBH (320 K to 4 bytes)
0
1
0
1
0
0
0 to 53FFBH (336 K to 4 bytes)
0
1
0
1
0
1
0 to 57FFBH (352 K to 4 bytes)
0
1
0
1
1
0
0 to 5BFFBH (368 K to 4 bytes)
0
1
0
1
0 to 5FFFBH (384 K to 4 bytes)
1
1
1
0
1
0
0
0
0 to 63FFBH (400 K to 4 bytes)
0
1
1
0
0
1
0 to 67FFBH (416 K to 4 bytes)
0
1
1
0
1
0
0 to 6BFFBH (432 K to 4 bytes)
0
1
1
0
1
1
0 to 6FFFBH (448 K to 4 bytes)
0
1
1
1
0
0
0 to 73FFBH (464 K to 4 bytes)
0
1
1
1
0
1
0 to 77FFBH (480 K to 4 bytes)
0
1
1
1
1
0
0 to 7BFFBH (496 K to 4 bytes)
0
1
1
1
1
1
0 to 7FFFBH (512 K to 4 bytes)
Other than the above
Remark
High- speed CRC operation range
Setting prohibited
In the last 4 bytes of the flash memory, store in advance the expected value of the CRC operation result for
comparison. The above table thus shows the operation range that is smaller by 4 bytes.
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26.3.1.2 Flash memory CRC operation result register (PGCRCL)
This register is used to store the high-speed CRC operation results.
The PGCRCL register can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Figure 26-2. Format of Flash Memory CRC Operation Result Register (PGCRCL)
Address: F02F2H
After reset: 0000H
R/W
Symbol
15
14
13
12
11
10
9
8
PGCRCL
PGCRC15
PGCRC14
PGCRC13
PGCRC12
PGCRC11
PGCRC10
PGCRC9
PGCRC8
Symbol
7
6
5
4
3
2
1
0
PGCRCL
PGCRC7
PGCRC6
PGCRC5
PGCRC4
PGCRC3
PGCRC2
PGCRC1
PGCRC0
PGCRC15 to 0
0000H to FFFFH
High-speed CRC operation results
Store the high-speed CRC operation results.
Caution The PGCRCL register can only be written to if CRC0EN (bit 7 of the CRC0CTL register) = 1.
Figure 26-3 shows a flowchart of the flash memory CRC operation function (high-speed CRC).
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Figure 26-3. Flowchart of Flash Memory CRC Operation Function (High-Speed CRC)
; Store CRC operation expected value
Start
; in the least significant 4 bytes in advance.
Set FEA5 to FEA0 bits.
Copy HALT and RET instructions to
RAM. Initialize 10 bytes.
Set all xxMKx to 1.
CRC0EN = 1
PGCRCL = 0000H
; Set CRC operation range.
; To execute CRC operation on RAM,
; copy HALT and RET instructions to RAM.
; Initialize 10 bytes following RET instruction.
; Set mask to all interrupts.
; Enable CRC operation.
; Initialize CRC operation result register.
; Call address of HALT instruction copied
Execute CALL instruction.
; to RAM.
; Start CRC operation by HALT instruction
Execute HALT instruction.
HALT mode
Execute RET instruction.
CRC0EN = 0
Read PGCRCL.
; execution.
; Upon operation completion, HALT mode is
; cancelled and control returns from instruction
; execution on RAM upon RET instruction
; execution.
; Disable CRC operation.
; Read CRC operation result.
; Check result against preset expected value
Check result against CRC
expected value.
Not match
Match
Abort
Successful end
Cautions 1. Only code flash memory is subject to CRC operation.
2. Store the CRC operation expected value in the area following the operation range of the code
flash memory.
3. Boot swapping is not performed during CRC operation.
4. Executing the HALT instruction in the RAM area enables CRC operation; be sure to execute the
HALT instruction in the RAM area.
The CRC expected value can be calculated using the development environment CubeSuite+ or the equivalents (refer to
the CubeSuite+ user’s manual.
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26.3.2 CRC Operation Function (General-Purpose CRC)
The IEC 61508 standard requires safety to be guaranteed during operation and thus the means for data verification
during CPU operation is necessary.
With the general-purpose CRC operation function, the CRC operation is possible as a peripheral function during CPU
operation. The general-purpose CRC operation function can be used for not only check of code flash memory area but
versatile check. Data to be checked is specified with the user program. In HALT mode, the CRC operation function is
available only during DMA transfer.
The CRC operation function is available both in main and subsystem clock operation modes.
The CRC generator polynomial is X16 + X12 + X5 + 1 of CRC-16-CCITT. Operation is done after the input data is
reversed in bit sequence to accommodate to the LSB-first communication. For example, when data 12345678H is to be
transmitted with the LSB first, writing 78H, 56H, 34H, and 12H in CRCIN register in this order allows value 08E6H to be
obtained from the CRCD register. This value is obtained as shown below, where data 12345678H is reversed in bit
sequence and then the resulting bit strings are subjected to CRC operation.
Data set in CRCIN
78H
Data represented in bits
56H
34H
12H
0111 1000 0101 0110 0011 0100 0001 0010
Bit sequence reversed
Data after bit sequence reversal
0001 1110 0110 1010 0010 1100 0100 1000
Operation using polynomial
Resulting data
0110 1111 0001 0000
Bit sequence reversed
CRCD data
Obtained data
0000 1000 1111 0110
(08F6H)
Caution During program execution, the debugger replaces the line in which software break is set with the
break instruction; therefore, setting a software break in the area subject to CRC operation causes a
different operation result to be obtained.
26.3.2.1 CRC input register (CRCIN)
This is an 8-bit register used to set the data for general-purpose CRC operation.
The possible setting range is 00H to FFH.
The CRCIN register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 26-4. Format of CRC Input Register (CRCIN)
Address: FFFACH
Symbol
After reset: 00H
7
6
R/W
5
4
3
2
1
0
CRCIN
Bits 7 to 0
00H to FFH
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26.3.2.2 CRC data register (CRCD)
This register is used to store the general-purpose CRC operation result.
The possible setting range is 0000H to FFFFH.
After 1 clock of CPU/peripheral hardware clock (fCLK) has elapsed from the time CRCIN register is written to, the CRC
operation result is stored to the CRCD register.
The CRCD register can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Figure 26-5. Format of CRC Data Register (CRCD)
Address: F02FAH
Symbol
15
After reset: 0000H
14
13
12
R/W
11
10
9
8
7
6
5
4
3
2
1
0
CRCD
Cautions 1. Read the value written to CRCD register before writing to CRCIN register.
2. If writing and storing operation result to CRCD register conflict, the writing is ignored.
Figure 26-6. Flowchart of CRC Operation Function (General-Purpose CRC)
Start
; Store the start and end addresses in general
Set the start and end addresses.
Write 0000H to CRCD register.
; registers.
; Initialize CRCD register.
Read data.
; Read 8-bit data at applicable address.
Store data in CRCIN register.
; Execute CRC operation on 8-bit data.
Address + 1.
Last address?
Yes
No
Wait 1 clock cycle (fCLK).
Read CRCD register.
End
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; Acquire CRC result.
; Compare result with preset
; expected value and confirm
; that they agree.
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CHAPTER 26 SAFETY FUNCTIONS
26.3.3 RAM Parity Error Detection Function
The IEC 60730 standard requires verification of RAM data. To meet the requirement, one parity bit is appended to each
8-bit data in the RL78/D1A RAM. With the RAM parity error detection function, a parity is written when data is written and
the parity is checked when data is read out. A reset can be generated upon occurrence of a parity error.
26.3.3.1 RAM parity error control register (RPECTL)
This register is used to check occurrence of a parity error and control resets due to parity errors.
The RPECTL register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 26-7. Format of RAM Parity Error Control Register (RPECTL)
Address: F00F5H
After reset: 00H
R/W
Symbol
6
5
4
3
2
1
RPECTL
RPERDIS
0
0
0
0
0
0
RPEF
RPERDIS
Parity error reset mask flag
0
Enables parity error resets.
1
Disables parity error resets.
RPEF
Parity error status flag
0
No parity error has occurred.
1
A parity error has occurred.
Caution With the RL78, the CPU performs read-ahead for pipeline operation to read the RAM area not yet
initialized that follows the currently used RAM area, which may cause a RAM parity error. Therefore,
when RAM parity error reset generation is enabled (RPERDIS = 0), be sure to initialize the RAM area
to be used and 10 more bytes. When the self-programming function is used, be sure to initialize the
RAM area to be rewritten to and 10 more bytes before rewrite.
Parity error detection is performed on RAM data read during RAM instruction fetching.
Remarks 1. The RAM parity check function is always on and the check results can be read from the RPEF flag.
2. In the initial state, parity error reset generation is enabled (RPERDIS = 0). Even if parity error reset
generation is disabled (RPERDIS = 1), the RPEF flag is set (1) when a parity error occurs.
3. The RPEF flag is set (1) by RAM parity errors and cleared (0) by writing 0 to it or by any reset source.
When RPEF = 1, the value is retained even if RAM for which no parity error has occurred is read.
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26.3.4 RAM Guard Function
The IEC 61508 standard requires safety to be guaranteed during operation and thus it is necessary to protect
significant data stored in RAM when the CPU freezes.
The RAM guard function protects data in the specified space.
Setting this function disables writing to RAM in the specified space but enables reading normally.
26.3.4.1 Invalid memory access detection control register (IAWCTL)
This register is used to control the detection of invalid memory access and RAM/SFR guard.
The RAM guard function uses the GRAM1 and GRAM0 bits.
The IAWCTL register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 26-8. Format of Invalid Memory Access Detection Control Register (IAWCTL)
Address: F0078H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
IAWCTL
IAWEN
0
GRAM1
GRAM0
0
GPORT
GINT
GCSC
GRAM1
GRAM0
0
0
Disabled. RAM can be written to.
0
1
The 128 bytes starting at the lower RAM address
1
0
The 256 bytes starting at the lower RAM address
1
1
The 512 bytes starting at the lower RAM address
Note
RAM guard space
Note The RAM start address differs depending on the size of the RAM provided with the product.
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26.3.5 SFR Guard Function
The IEC 61508 standard requires safety to be guaranteed during operation and thus it is necessary to prevent
significant SFRs from being erroneously rewritten when the CPU freezes.
The SFR guard function protects data in the registers used to control the port function, interrupt function, clock control
function, voltage detection circuits, and RAM parity error detection function.
Setting this function disables writing to guarded SFRs but enables reading normally.
26.3.5.1 Invalid memory access detection control register (IAWCTL)
This register is used to control the detection of invalid memory access and RAM/SFR guard.
The SFR guard function uses the GPORT, GINT, and GCSC bits.
The IAWCTL register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 26-9. Format of Invalid Memory Access Detection Control Register (IAWCTL)
Address: F0078H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
IAWCTL
IAWEN
0
GRAM1
GRAM0
0
GPORT
GINT
GCSC
GPORT
0
Port function control register guard
Disabled. Port function control registers can be read or written to.
1
Enabled. Writing to port function control registers is disabled. Reading is enabled.
Guarded SFRs: PMxx, PUxx, PIMxx, POMxx, TISxx, TOSxx, TISELSE, STSELx, SGSEL, RTCSEL,
LCDPFxx, SMPC and ADPC
GINT
Note 1
Interrupt function control register guard
0
Disabled. Interrupt function control registers can be read or written to.
1
Enabled. Writing to interrupt function control registers is disabled. Reading is enabled.
Guarded SFRs: IFxx, MKxx, PRxx, EGPx, EGNx
GCSC
Note 2
Clock control function, voltage detection circuit, and RAM parity error detection function control register
guard
0
Disabled. Registers to control port function, interrupt function, clock control function, voltage detection
circuits, and RAM parity error detection function can be read or written to.
1
Enabled. Writing to registers to control port function, interrupt function, clock control function, voltage
detection circuits, and RAM parity error detection function is disabled. Reading is enabled.
Guarded SFRs: CMC, CSC, OSTS, CKC, PERx, OSMC, LVIM, LVIS, PCKSEL, MDIV and RPECTL
Notes 1. Pxx (port registers) are not guarded.
2. Set GCSC to 0 for self-programming.
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26.3.5.2 Specific register manipulation protection register (GUARD)
This register is used to control the guard function.
GDRTC and GDPLL bits are used in SFR guard function.
The GUARD register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 26-10. Format of Specific Register Manipulation Protection Register (GUARD)
Address: F00FCH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
GUARD
0
0
0
0
0
0
GDRTC
GDPLL
GDRTC
Protection against RTC clock selection register (RTCCL)
0
RTCCL register can be accessed.
1
Disables RTCCL register (GUARD is effective).
GDPLL
Protection against manipulation of PLL control register (PLLCTL)
0
Enables manipulation of PLLCTL register.
1
Disables manipulation of PLLCTL register (GUARD is effective).
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26.3.6 Invalid Memory Access Detection Function
The IEC 60730 standard requires verification of correct operations of the CPU and interrupts.
The invalid memory access detection function allows a reset to be generated when the specified invalid memory
access detection space is accessed.
The space in which invalid memory access is to be detected is indicated as NG in figure 26-11.
Figure 26-11. Invalid Memory Access Detection Space
Access OK or NG
Read
Write
Instruction
fetch
(execution)
FFFFFH
Special function registers (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
NG
General-purpose registers
32 bytes
OK
RAMNote
OK
yyyyyH
Mirror
OK
NG
NG
Data flash memory
F1000H
F0FFFH
Reserved
OK
F0800H
F07FFH
OK
Special function register (2nd SFR)
2 Kbytes
NG
F0000H
EFFFFH
OK
EF000H
EEFFFH
Reserved
NG
NG
NG
xxxxxH
Code flash memory Note
OK
OK
00000H
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Note
CHAPTER 26 SAFETY FUNCTIONS
The addresses of the RAM and code flash memory are shown below according to the product type.
Products
Code flash memory
RAM
(00000H to xxxxxH)
(yyyyyH to FFEFFH)
Reserved
Specific area
Other area
Read access: No error is
Read access: Invalid
detected. But value 0FFH
access is detected.
is read always
Fetching instruction:
Fetching instruction:
Invalid access is
Illegal instruction
detected.
execution is detected and
internal reset generated
Write access: Invalid
(RESF.TRAP bit flag set
access is detected.
to 1)
Write access: Invalid
access is detected.
R5F10CGBxFB
24576 × 8 bits
2048 × 8 bits
40960 x 8 bits
All other “Reserved” area
(00000H to 05FFFH)
(FF700H to FFEFFH)
(06000H to 0FFFFH)
than “Specific area”
R5F10CGCxFB,
32768 × 8 bits
2048 × 8 bits
32768 × 8 bits
All other “Reserved” area
R5F10DGCxFB
(00000H to 07FFFH)
(FF700H to FFEFFH)
(08000H to 0FFFFH)
than “Specific area”
R5F10CGDxFB,
49152 × 8 bits
3072 × 8 bits
16384 × 8 bits
All other “Reserved” area
R5F10DGDxFB,
(00000H to 0BFFFH)
(FF300H to FFEFFH)
(0C000H to 0FFFFH)
than “Specific area”
R5F10DGExFB,
65536 × 8 bits
4096 × 8 bits
Not applicable
All “Reserved” area
R5F10DLExFB,
(00000H to 0FFFFH)
(FEF00H to FFEFFH)
R5F10DMFxFB,
98304 × 8 bits
6144 × 8 bits
32768 × 8 bits
All other “Reserved” area
R5F10DPFxFB
(00000H to 17FFFH)
(FE700H to FFEFFH)
(18000H to 1FFFFH)
than “Specific area”
R5F10DMGxFB,
131072 × 8 bits
8192 × 8 bits
Not applicable
All “Reserved” area
R5F10DPGxFB
(00000H to 1FFFFH)
(FDF00H to FFEFFH)
R5F10DMJxFB,
262144 × 8 bits
16384 × 8 bits
Not applicable
All “Reserved” area
R5F10TPJxFB,
(00000H to 3FFFFH)
(FBF00H to FFEFFH)
R5F10DSKxFB,
393216× 8 bits
20480 8 bits
Not applicable
All “Reserved” area
R5F10DPKxFB
(00000H to 5FFFFH)
(FAF00H to FFEFFH)
R5F10DSLxFB,
524288 × 8 bits
24576 8 bits
Not applicable
All “Reserved” area
R5F10DPLxFB
(00000H to 7FFFFH)
(F9F00H to FFEFFH)
R5F10CLDxFB,
R5F10DLDxFB,
R5F10CMDxFB,
R5F10DMDxFB
R5F10CMExFB,
R5F10DMExFB,
R5F10DPExFB
R5F10DPJxFB,
R5F10DSJxFB
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26.3.6.1 Invalid memory access detection control register (IAWCTL)
This register is used to control the detection of invalid memory access and RAM/SFR guard.
The invalid memory access detection function uses the IAWEN bit.
The IAWCTL register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 26-12. Format of Invalid Memory Access Detection Control Register (IAWCTL)
Address: F0078H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
IAWCTL
IAWEN
0
GRAM1
GRAM0
0
GPORT
GINT
GCSC
Note
IAWEN
Note
Control of invalid memory access detection
0
Disables the detection of invalid memory access.
1
Enables the detection of invalid memory access.
Only writing 1 to the IAWEN bit is valid, and writing 0 to it after setting it to 1 is invalid.
Remark
When WDTON = 1 (watchdog timer operation enabled) for the option byte, the invalid memory access
detection function is enabled even if IAWEN = 0.
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26.3.7 Frequency Detection Function
The IEC 60730 standard requires verification of correct oscillation frequency.
With the frequency detection function, the high-speed on-chip oscillator clock or external X1 oscillator clock is
compared with the low-speed on-chip oscillator clock (15 kHz), which allows detection of the clock operating at an
abnormal frequency.
Figure 26-13. Configuration of Frequency Detection Function
X1
X1 oscillator
X2
(fMX)
Selector
High-speed on-chip
oscillator (fIH)
Selector
fCLK
TI05
Low-speed on-chip
oscillator (15 kHz)
fIL
Timer array unit
0 (TAU0)
Watchdog timer
(WDT)
The clock frequency is judged based on the result of pulse interval measurement carried under the following conditions.
The high-speed on-chip oscillator clock (fIH) or external X1 oscillator clock (fMX) is selected as the CPU/peripheral
hardware clock (fCLK).
The low-speed on-chip oscillator clock (fIL: 15 kHz) is selected as the input to channel 5 of timer array unit 0
(TAU0).
If the pulse interval measurement result is abnormal, the clock frequency is determined to be abnormal. For pulse
interval measurement, refer to 6.7.4, Operation as input pulse interval measurement.
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26.3.7.1 Timer input select register 0 (TISELSE)
This register is used to select the timer input of channel 5.
By selecting the internal low-speed oscillation clock for the timer input, its pulse width can be measured to determine
whether the proportional relationship between the internal low-speed oscillation clock and the timer operation clock is
correct.
The TISELSE register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 26-14. Format of Timer Input Select Else Register (TISELSE) for SAFETY FUNCTIONS
Address: FFF3EH
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
TISELSE
TOTICON1
TOTICON0
0
0
0
0
TI05SEL1
TI05SEL0
TI05SEL1
TI05SEL0
0
0
Input after selected by TIS01. bit 2, 3 (TIS051-0)
0
1
Low-speed on-chip oscillator clock (FIL)
1
0
Sub system clock (FSUB)
1
1
Main external clock (FMX)
TAU unit 0 channel 5 input alternate selection
26.3.8 A/D Test Function
The IEC 60730 standard requires an A/D converter to be tested. With the A/D test function, internal 0 V, AVREF, internal
reference voltage (1.45 V) are A/D-converted to verify correct A/D converter operation.
Correct operation of the analog multiplexer can be verified using the following procedure.
(1) Perform A/D conversion of ANIx pin (conversion result 1).
(2) Perform A/D conversion with AVREFM being selected with the ADTES register, and adjust the potential difference at
both ends of A/D converter sampling capacitor to 0 V.
(3) Perform A/D conversion of ANIx pin (conversion result 2).
(4) Perform A/D conversion with AVREFP being selected with the ADTES register, and adjust the potential difference at
both ends of A/D converter sampling capacitor to AVREF.
(5) Perform A/D conversion of ANIx pin (conversion result 3).
(6) Confirm that conversion results 1, 2, and 3 are identical.
With the above procedure, it can be confirmed that the analog multiplexer is selected and that there is no wire
disconnection.
Remarks 1. When the variable analog voltage should be input during conversion in steps 1 through 5, a different
method is necessary to check the analog multiplexer.
2. The conversion results include errors; take appropriate errors into consideration when comparing
conversion results.
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CHAPTER 26 SAFETY FUNCTIONS
Figure 26-15. A/D Test Function Configuration
VDD
ANI0/AVREFP
+ side reference
voltage source
(AVREF+)
ANI1/AVREFM
ANIx
ANIx
A/D convertor
- side reference
voltage source
(AVREF-)
VSS
26.3.8.1 A/D test register (ADTES)
This register is used to select the AVREFP, AVREFM, or analog input channel (ANIxx) as the A/D conversion target, where
AVREFP and AVREFM are reference voltages for the + and – sides, respectively.
When the A/D test function is used, set this register as follows.
Select AVREFM as the A/D conversion target to measure internal 0 V.
Select AVREFP as the A/D conversion target to measure AVREF.
The ADTES register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 26-16. Format of A/D Test Register (ADTES)
Address: F0013H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
ADTES
0
0
0
0
0
ADTES2
ADTES1
ADTES0
ADTES2
ADTES1
0
0
ADTES0
0
A/D conversion target
ANIxx (This is specified using the analog input channel specification
register (ADS).)
0
1
0
AVREFM
0
1
1
AVREFP
Other than the above
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CHAPTER 27 REGULATOR
CHAPTER 27 REGULATOR
27.1 Regulator Overview
The RL78/D1A contains a circuit for operating the device with a constant voltage. At this time, in order to stabilize the
regulator output voltage, connect the REGC pin to VSS via a capacitor (0.47 to 1 F). Also, use a capacitor with good
characteristics, since it is used to stabilize internal voltage.
REGC
VSS
Caution Keep the wiring length as short as possible for the broken-line part in the above figure.
The regulator output voltage, see table 27-1.
Table 27-1. Regulator Output Voltage Conditions
Mode
High-speed main mode
Output Voltage
1.8 V
Condition
In STOP mode
When both the high-speed system clock (fMX) and the high-speed on-chip oscillator
clock (fIH) are stopped during CPU operation with the subsystem clock (fXT)
When both the high-speed system clock (fMX) and the high-speed on-chip oscillator
clock (fIH) are stopped during the HALT mode when the CPU operation with the
subsystem clock (fXT) has been set
2.1 V
Other than the above (include during OCD mode)
Note
Note When it shifts to the subsystem clock operation or STOP mode during the on-chip debugging, the regulator
output voltage is kept at 2.1 V (not decline to 1.8 V).
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CHAPTER 28 OPTION BYTE
CHAPTER 28 OPTION BYTE
28.1 Functions of Option Bytes
Addresses 000C0H to 000C3H of the flash memory of the RL78/D1A form an option byte area.
Option bytes consist of user option byte (000C0H to 000C2H) and on-chip debug option byte (000C3H).
Upon power application or resetting and starting, an option byte is automatically referenced and a specified function is
set. When using the product, be sure to set the following functions by using the option bytes.
To use the boot swap operation during self programming, 000C0H to 000C3H are replaced by 020C0H to 020C3H.
Therefore, set the same values as 000C0H to 000C3H to 020C0H to 020C3H.
28.1.1 User option byte (000C0H to 000C2H/020C0H to 020C2H)
(1) 000C0H/020C0H
Operation of watchdog timer
Operation is stopped or enabled in the HALT or STOP mode.
Setting of interval time of watchdog timer
Operation of watchdog timer
Operation is stopped or enabled.
Setting of window open period of watchdog timer
Setting of interval interrupt of watchdog timer
Used or not used
Caution Set the same value as 000C0H to 020C0H when the boot swap operation is used because
000C0H is replaced by 020C0H.
(2) 000C1H/020C1H
Setting of LVD operation mode
Interrupt & reset mode.
Reset mode.
Interrupt mode.
Setting of LVD detection level (VLVDH, VLVDL, VLVD)
Caution Set the same value as 000C1H to 020C1H when the boot swap operation is used because
000C1H is replaced by 020C1H.
(3) 000C2H/020C2H
Setting of flash operation mode
HS (high speed main) mode
Setting of the frequency of the high-speed on-chip oscillator
Select from 4 MHz, 8 MHz, 16 MHz, 24 MHz, and 32 MHz.
Caution Set the same value as 000C2H to 020C2H when the boot swap operation is used because
000C2H is replaced by 020C2H.
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28.1.2 On-chip debug option byte (000C3H/ 020C3H)
Control of on-chip debug operation
On-chip debug operation is disabled or enabled.
Handling of data of flash memory in case of failure in on-chip debug security ID authentication
Data of flash memory is erased or not erased in case of failure in on-chip debug security ID authentication.
Caution Set the same value as 000C3H to 020C3H when the boot swap operation is used because
000C3H is replaced by 020C3H.
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CHAPTER 28 OPTION BYTE
28.2 Format of User Option Byte
The format of user option byte is shown below.
Figure 28-1. Format of User Option Byte (000C0H/020C0H)
Address: 000C0H/020C0H
Note 1
7
6
5
4
3
2
1
0
WDTINT
WINDOW1
WINDOW0
WDTON
WDCS2
WDCS1
WDCS0
WDSTBYON
WDTINT
Use of interval interrupt of watchdog timer
0
Interval interrupt is not used.
1
Interval interrupt is generated when 75% +1/2fIL of the overflow time is reached.
WINDOW1
WINDOW0
Watchdog timer window open period
0
0
Setting prohibited
0
1
50%
1
0
75%
1
1
100%
WDTON
Operation control of watchdog timer counter
0
Counter operation disabled (counting stopped after reset)
1
Counter operation enabled (counting started after reset)
WDCS2
WDCS1
WDCS0
Watchdog timer overflow time (fIL = 17.25 kHz (MAX.))
6
0
0
0
2 /fIL (3.71 ms)
0
0
1
2 /fIL (7.42 ms)
0
1
0
2 /fIL (14.84 ms)
0
1
1
2 /fIL (29.68 ms)
1
0
0
2 /fIL (118.72 ms)
1
0
1
2 /fIL (474.90 ms)
1
1
0
2 /fIL (949.80 ms)
1
1
1
2 /fIL (3799.19m s)
WDSTBYON
Notes 1.
Note 2
7
8
9
11
13
14
16
Operation control of watchdog timer counter (HALT/STOP mode)
0
Counter operation stopped in HALT/STOP mode
1
Counter operation enabled in HALT/STOP mode
Note 2
Set the same value as 000C0H to 020C0H when the boot swap operation is used because 000C0H is
replaced by 020C0H.
2.
The window open period is 100% when WDSTBYON = 0, regardless the value of the WINDOW1 and
WINDOW0 bits.
Caution The watchdog timer continues its operation during EEPROM emulation.
During processing, the
interrupt acknowledge time is delayed. Set the overflow time and window size taking this delay into
consideration.
Remark
fIL: Low-speed on-chip oscillator clock frequency
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Figure 28-2. Format of User Option Byte (000C1H/020C1H) (1/2)
Address: 000C1H/020C1H
Note
7
6
5
4
3
2
1
0
VPOC2
VPOC1
VPOC0
CLKMB
LVIS1
LVIS0
LVIMDS1
LVIMDS0
CLKMB
Clock monitoring operation control
0
Operates clock monitoring.
1
Stops clock monitoring. (default)
LVD setting (interrupt & reset mode)
Detection voltage
VLVDH
Option byte Setting Value
VLVDL
LVIMDS1
LVIMDS0
VPOC2
VPOC1
VPOC0
LVIS1
LVIS0
1
0
0
1
1
1
0
Rising
Falling
Falling
edge
edge
edge
2.92 V
2.86 V
2.75 V
3.02 V
2.96 V
0
1
4.06 V
3.98 V
0
0
Other than the above
Setting prohibited
LVD setting (reset mode)
Detection voltage
VLVDH
Rising edge
Falling edge
2.81 V
2.75 V
Option byte Setting Value
LVIMDS1
LVIMDS0
VPOC2
VPOC1
VPOC0
LVIS1
LVIS0
1
1
0
1
1
1
1
2.92 V
2.86 V
0
1
1
1
0
3.02 V
2.96 V
0
1
1
0
1
3.13 V
3.06 V
0
0
1
0
0
3.75 V
3.67 V
0
1
0
0
0
4.06 V
3.98 V
0
1
1
0
0
Other than the above
Note
Setting prohibited
Set the same value as 000C1H to 020C1H when the boot swap operation is used because 000C1H is replaced
by 020C1H.
Remark
For LVD setting, see 25.1 Functions of Voltage Detector.
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Figure 28-2. Format of User Option Byte (000C1H/020C1H) (2/2)
Address: 000C1H/020C1H
Note
7
6
5
4
3
2
1
0
VPOC2
VPOC1
VPOC0
CLKMB
LVIS1
LVIS0
LVIMDS1
LVIMDS0
LVD setting (interrupt mode)
Detection voltage
Option byte Setting Value
VLVDH
Rising edge
Falling edge
2.81 V
2.75 V
LVIMDS1
LVIMDS0
VPOC2
VPOC1
VPOC0
LVIS1
LVIS0
0
1
0
1
1
1
1
2.92 V
2.86 V
0
1
1
1
0
3.02 V
2.96 V
0
1
1
0
1
3.13 V
3.06 V
0
0
1
0
0
3.75 V
3.67 V
0
1
0
0
0
4.06 V
3.98 V
0
1
1
0
0
Other than the above
Setting prohibited
LVD setting (LVDOFF)
Detection voltage
Option byte Setting Value
VLVD
Rising edge
Falling edge
-
-
Other than the above
LVIMDS1
LVIMDS0
VPOC2
VPOC1
VPOC0
LVIS1
LVIS0
0/1
1
1
×
×
×
×
Setting prohibited
____________
Caution External RESET must be used during power supply rising up to 2.7 V.
Note
Set the same value as 000C1H to 020C1H when the boot swap operation is used because 000C1H is replaced
by 020C1H.
Remarks 1.
2.
×: don’t care
For LVD setting, see 25.1 Functions of Voltage Detector.
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Figure 28-3. Format of Option Byte (000C2H/020C2H)
Address: 000C2H/020C2H
Note
7
6
5
4
3
2
1
0
CMODE1
CMODE0
OPTPLL
0
FRQSEL3
FRQSEL2
FRQSEL1
FRQSEL0
CMODE1
CMODE0
1
1
Other than the above
Setting of flash operation mode
HS (high speed main) mode
Setting prohibited
OPTPLL
PLL hard macro multiplication selection
0
16 selection ( 8 from user view) (If input clock is 4/8 MHz, fPLL = 32 MHz)
1
12 selection ( 6 from user view) (default) (If input clock is 4/8 MHz, FPLL = 24 MHz)
FRQSEL3
FRQSEL2
FRQSEL1
FRQSEL0
1
0
0
0
32 MHz
0
0
0
0
24 MHz
1
0
0
1
16 MHz
1
0
1
0
8 MHz
1
0
1
1
4 MHz
Other than the above
Frequency of the high-speed on-chip oscillator
Setting prohibited
Note Set the same value as 000C2H to 020C2H when the boot swap operation is used because 000C2H is replaced
by 020C2H.
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CHAPTER 28 OPTION BYTE
28.3 Format of On-chip Debug Option Byte
The format of on-chip debug option byte is shown below.
Figure 28-4. Format of On-chip Debug Option Byte (000C3H/020C3H)
Address: 000C3H/020C3H
Note
7
6
5
4
3
2
1
0
OCDENSET
0
0
0
0
1
0
OCDERSD
OCDENSET
OCDERSD
0
0
0
1
Setting prohibited
1
0
Enables on-chip debugging.
Control of on-chip debug operation
Disables on-chip debug operation.
Erases data of flash memory in case of failures in authenticating on-chip debug
security ID.
1
1
Enables on-chip debugging.
Does not erases data of flash memory in case of failures in authenticating on-chip
debug security ID.
Note Set the same value as 000C3H to 020C3H when the boot swap operation is used because 000C3H is replaced
by 020C3H.
Caution Bits 7 and 0 (OCDENSET and OCDERSD) can only be specified a value.
Be sure to set 000010B to bits 6 to 1.
Remark The value on bits 3 to 1 will be written over when the on-chip debug function is in use and thus it will become
unstable after the setting.
However, be sure to set the default values (0, 1, and 0) to bits 3 to 1 at setting.
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CHAPTER 28 OPTION BYTE
28.4 Setting of Option Byte
The user option byte and on-chip debug option byte can be set using the assembler linker option, in addition to
describing to the source. When doing so, the contents set by using the linker option take precedence, even if descriptions
exist in the source, as mentioned below.
A software description example of the option byte setting is shown below.
OPT
CSEG
OPT_BYTE
DB
36H
; Does not use interval interrupt of watchdog timer,
; Enables watchdog timer operation,
; Window open period of watchdog timer is 50%,
9
; Overflow time of watchdog timer is 2 /fIL,
; Stops watchdog timer operation during HALT/STOP mode
DB
7AH
; Select 2.75 V for VLVDL
; Select rising edge 2.92 V, falling edge 2.86 V for VLVDH
; Select the interrupt & reset mode as the LVD operation mode
DB
0C9H
stops clock monitoring
; Select the HS (high speed main) mode as the flash operation mode
and 16 MHz as the frequency of the high-speed on-chip oscillator
DB
85H
; Enables on-chip debug operation, does not erase flash memory
data when security ID authorization fails
When the boot swap function is used during self programming, 000C0H to 000C3H is switched to 020C0H to 020C3H.
Describe to 020C0H to 020C3H, therefore, the same values as 000C0H to 000C3H as follows.
OPT2
CSEG
AT
DB
020C0H
36H
; Does not use interval interrupt of watchdog timer,
; Enables watchdog timer operation,
; Window open period of watchdog timer is 50%,
9
; Overflow time of watchdog timer is 2 /fIL,
; Stops watchdog timer operation during HALT/STOP mode
DB
7AH
; Select 2.75 V for VLVDL
; Select rising edge 2.92 V, falling edge 2.86 V for VLVDH
; Select the interrupt & reset mode as the LVD operation mode
DB
0C9H
stops clock monitoring
; Select the HS (high speed main) mode as the flash operation mode
DB
85H
; Enables on-chip debug operation, does not erase flash memory
and 16 MHz as the frequency of the high-speed on-chip oscillator
data when security ID authorization fails
Caution To specify the option byte by using assembly language, use OPT_BYTE as the relocation attribute
name of the CSEG pseudo instruction. To specify the option byte to 020C0H to 020C3H in order to
use the boot swap function, use the relocation attribute AT to specify an absolute address.
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CHAPTER 29 FLASH MEMORY
CHAPTER 29 FLASH MEMORY
The RL78/D1A incorporates the flash memory to which a program can be written, erased, and overwritten while
mounted on the board. The flash memory includes the “code flash memory”, in which programs can be executed, and the
“data flash memory”, an area for storing data.
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
RAM
2 to 24 KB
Mirror
F1000H
F0FFFH
F0800H
F07FFH
Data flash memory
8 KB
Reserved
Special function register (2nd SFR)
2 KB
F0000H
EFFFFH
Reserved
Code flash memory
24 to 512 KB
00000H
The following three methods for programming the flash memory are available:
Writing to flash memory by using flash memory programmer (see 29.1)
Writing to flash memory by using external device (that Incorporates UART) (see 29.2)
Self-programming (see 29.7)
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29.1 Writing to Flash Memory by Using Flash Memory Programmer
The following dedicated flash memory programmer can be used to write data to the internal flash memory of the
RL78/D1A.
PG-FP5, FL-PR5
E1 on-chip debugging emulator
Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer.
(1) On-board programming
The contents of the flash memory can be rewritten after the RL78/D1A has been mounted on the target system. The
connectors that connect the dedicated flash memory programmer must be mounted on the target system.
(2) Off-board programming
Data can be written to the flash memory with a dedicated program adapter (FA series) before the RL78/D1A is
mounted on the target system.
Remark
FL-PR5 and FA series are products of Naito Densei Machida Mfg. Co., Ltd.
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Table 29-1. Wiring Between RL78/D1A and Dedicated Flash Memory Programmer
Pin Configuration of Dedicated Flash Memory Programmer
Signal Name
PG-FP5,
FL-PR5
I/O
TOOL0
I/O
Transmit/receive signal
SI/RxD
I/O
Transmit/receive signal
SCK
Output
Output
CLK
Output
Output
Mode signal
I/O
VDD voltage generation/
power monitoring
GND
5
9
6
8
12
Ground
VDD
12
16
20
EVDD
12
16
20
SMVDD
43
59
66, 76
VSS
11
15
19
EVSS
11
15
19
SMVSS
42
58
65, 75
10
14
18
12
16
20
REGC
EMVDD
Driving power for TOOL pin
Pin Configuration of Dedicated Flash Memory Programmer
PG-FP5,
FL-PR5
5
RESET
80-pin
LQFP (14x14)
Reset signal
FLMD0
Signal Name
64-pin
LQFP (12x12)
____________
Output
/RESET
VDD
48-pin
LQFP (10x10)
TOOL0/P40
____________
RESET
Pin No.
Pin Function
E1 on-chip
debugging
emulator
Pin Name
I/O
Note
EVDD
Pin Name
Pin No.
Pin Function
E1 on-chip
debugging
emulator
100-pin
128-pin
LQFP (10x10)
LQFP (14x20)
11
114
TOOL0
I/O
Transmit/receive signal
SI/RxD
I/O
Transmit/receive signal
SCK
Output
CLK
Output
15
118
24
127
EVDD
25, 33
8, 128
SMVDD
81, 91
74, 84
___________
RESET
/RESET
FLMD0
VDD
___________
Output
Reset signal
RESET
Output
Output
Mode signal
I/O
VDD voltage generation/
power monitoring
GND
TOOL0/P40
Ground
VDD
VSS
EVSS
SMVSS
REGC
EMVDD
Note
Driving power for TOOL pin
Note
EVDD
22
125
23, 34
9, 126
80, 90
73, 83
21
124
25, 33
8, 128
Connect REGC pin to ground via a capacitor (default: 0.47 F).
Remark
Pins that are not indicated in the above table can be left open when using the flash memory programmer
for flash programming.
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29.1.1 Programming Environment
The environment required for writing a program to the flash memory of the RL78/D1A is illustrated below.
Figure 29-1. Environment for Writing Program to Flash Memory
PG-FP5, FL-PR5
E1
VDD/EVDD/SMVDD
RS-232C
VSS/EVSS/SMVSS
USB
RESET
Dedicated flash
TOOL0 (dedicated single-line UART)
memory programmer
RL78/D1A
Host machine
A host machine that controls the dedicated flash memory programmer is necessary.
To interface between the dedicated flash memory programmer and the RL78/D1A, the TOOL0 pin is used for
manipulation such as writing and erasing via a dedicated single-line UART. To write the flash memory off-board, a
dedicated program adapter (FA series) is necessary.
29.1.2 Communication Mode
Communication between the dedicated flash memory programmer and the RL78/D1A is established by serial
communication using the TOOL0 pin via a dedicated single-line UART of the RL78/D1A.
Transfer rate: 1 M, 500 k, 250 k, 115.2 kbps
Figure 29-2. Communication with Dedicated Flash Memory Programmer
VDD
PG-FP5, FL-PR5
E1
EMVDD
GND
Dedicated flash
memory programmer
RESETNote 1,
/RESETNote 2
TOOL0Note 1
SI/RxDNote 2
VDD/EVDD/SMVDD
EVDD
VSS/EVSS/SMVSS/REGCNote 3
RESET
TOOL0
RL78/D1A
Notes 1. When using E1 on-chip debugging emulator.
2. When using PG-FP5 or FL-PR5.
3. Connect REGC pin to ground via a capacitor (default: 0.47 F).
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The dedicated flash memory programmer generates the following signals for the RL78/D1A. See the manual of PGFP5, FL-PR5, or E1 on-chip debugging emulator for details.
Table 29-2. Pin Connection
Dedicated Flash Memory Programmer
Signal Name
PG-FP5,
FL-PR5
I/O
VDD
Output
Mode signal
I/O
VDD voltage generation/power monitoring
VDD, EVDD, SMVDD
Ground
VSS, EVSS, SMVSS,
Note
REGC
EMVDD
Driving power for TOOL pin
EVDD
Output
Output
____________
Clock output
___________
Reset signal
RESET
RESET
Output
TOOL0
I/O
Transmit/receive signal
SI/RxD
I/O
Transmit/receive signal
SCK
Output
Transfer clock
Pin Name
GND
/RESET
Pin Function
Connection
E1 on-chip
debugging
emulator
FLMD0
CLK
RL78/D1A
TOOL0
Note Connect REGC pin to ground via a capacitor (default: 0.47 F).
Caution Make EVDD the same potential as VDD.
Remark
: Be sure to connect the pin.
: The pin does not have to be connected.
29.2 Writing to Flash Memory by Using External Device (that Incorporates UART)
On-board data writing to the internal flash memory is possible by using the RL78/D1A and an external device (a
microcontroller or ASIC) connected to a UART.
29.2.1 Programming Environment
The environment required for writing a program to the flash memory of the RL78/D1A is illustrated below.
Figure 29-3. Environment for Writing Program to Flash Memory
VDD/EVDD/SMVDD
VSS/EVSS/SMVSS
RESET
External device
(such as microcontroller
and ASIC)
UART (TOOLTxD, TOOLRxD)
RL78/D1A
TOOL0
Processing to write data to or delete data from the RL78/D1A by using an external device is performed on-board. Offboard writing is not possible.
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29.2.2 Communication Mode
Communication between the external device and the RL78/D1A is established by serial communication using the
TOOLTxD and TOOLRxD pins via UART0 of the serial array unit of the RL78/D1A.
Transfer rate: 1 M, 500 k, 250 k, 115.2 kbps
Figure 29-4. Communication with External Device
VDD
GND
RESET
External device
(such as microcontroller
and ASIC)
VSS/EVSS/SMVSS/REGCNote
RESET
RxD
TOOLTxD
TxD
TOOLRxD
PORT
Note
VDD/EVDD/SMVDD
RL78/D1A
TOOL0
Connect REGC pin to ground via a capacitor (0.47 F).
Caution Make EVDD the same potential as VDD.
The external device generates the following signals for the RL78/D1A.
Table 29-3. Pin Connection
External Device
Signal Name
VDD
I/O
I/O
GND
RL78/D1A
Pin Function
Pin Name
VDD voltage generation/power monitoring
VDD, EVDD, SMVDD
Ground
VSS, EVSS, SMVSS, REGC
CLK
Output
Clock output
RESETOUT
Output
Reset signal output
RxD
Input
Receive signal
TOOL0TxD
TxD
Output
Transmit signal
TOOL0RxD
PORT
Output
Mode signal
TOOL0
SCK
Output
Transfer clock
Note
Connection
Note
___________
RESET
Connect REGC pin to ground via a capacitor (0.47 F).
Caution Make EVDD the same potential as VDD.
Remark
: Be sure to connect the pin.
: The pin does not have to be connected.
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29.3 Connection of Pins on Board
To write the flash memory on-board by using the flash memory programmer, connectors that connect the dedicated
flash memory programmer must be provided on the target system. First provide a function that selects the normal
operation mode or flash memory programming mode on the board.
When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the
same status as immediately after reset. Therefore, if the external device does not recognize the state immediately after
reset, the pins must be handled as described below.
29.3.1 P40/TOOL0 pin
In the flash memory programming mode, connect this pin to the dedicated flash memory programmer via an external 1
k pull-up resistor. When this pin is used as the port pin, use that by the following method. When used as an input pin:
Input of 1 ms or more width low-level is prohibited after pin reset release. Furthermore, when this pin is used via pull-down
resistors, use the 500 k or more resistors.
When used as an output pin: When this pin is used via pull-down resistors, use the 500 k or more resistors.
Remark
The SAU and IICA pins are not used for communication between the RL78/D1A and dedicated flash memory
programmer, because single-line UART (TOOL0 pin) is used.
____________
29.3.2 RESET pin
Signal conflict will occur if the reset signal of the dedicated flash memory programmer and external device are
connected to the RESET pin that is connected to the reset signal generator on the board. To prevent this conflict, isolate
the connection with the reset signal generator.
The flash memory will not be correctly programmed if the reset signal is input from the user system while the flash
memory programming mode is set. Do not input any signal other than the reset signal of the dedicated flash memory
programmer and external device.
____________
Figure 29-5. Signal Conflict (RESET Pin)
RL78/D1A
Signal conflict
Input pin
Dedicated flash memory programmer
connection pin
Another device
Output pin
In the flash memory programming mode, a signal output by another device
will conflict with the signal output by the dedicated flash memory
programmer. Therefore, isolate the signal of another device.
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29.3.3 Port pins
When the flash memory programming mode is set, all the pins not used for flash memory programming enter the same
status as that immediately after reset.
If external devices connected to the ports do not recognize the port status
immediately after reset, the port pin must be connected to either to VDD, or VSS, via a resistor.
29.3.4 REGC pin
Connect the REGC pin to GND via a capacitor (0.47 to 1 F) in the same manner as during normal operation. Also,
use a capacitor with good characteristics, since it is used to stabilize internal voltage.
29.3.5 X1 and X2 pins
Connect X1 and X2 in the same status as in the normal operation mode.
Remark
In the flash memory programming mode, the high-speed on-chip oscillator clock (fIH) is used.
29.3.6 Power supply
To use the supply voltage output of the flash memory programmer, connect the VDD pin to VDD of the flash memory
programmer, and the VSS pin to GND of the flash memory programmer.
To use the on-board supply voltage, connect in compliance with the normal operation mode.
However, when writing to the flash memory by using the flash memory programmer and using the on-board supply
voltage, be sure to connect the VDD and VSS pins to VDD and GND of the flash memory programmer to use the power
monitor function with the flash memory programmer.
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29.4 Data Flash
29.4.1 Data flash overview
In addition to 24 to 256 KB of code flash memory, the RL78/D1A includes 8 KB of data flash memory for storing data.
FFFFFH
Special function register (SFR)
256 bytes
FFF00H
FFEFFH
FFEE0H
FFEDFH
General-purpose register
32 bytes
RAM
2 to 24 KB
Mirror
F1000H
F0FFFH
F0800H
F07FFH
Data flash memory
8 KB
Reserved
Special function register (2nd SFR)
2 KB
F0000H
EFFFFH
Reserved
Code flash memory
24 to 512 KB
00000H
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An overview of the data flash memory is provided below.
The data flash memory can be written to by using the flash memory programmer or an external device
Programming is performed in 8-bit units
Blocks can be deleted in 1 KB units
The only access by CPU instructions is byte reading (reading: four clock cycles)
Because the data flash memory is an area exclusively used for data, it cannot be used to execute instructions (code
fetching)
Instructions can be executed from the code flash memory while rewriting the data flash memory (That is, dual
operation is supported)
Accessing the data flash memory is not possible while rewriting the code flash memory (such as during selfprogramming)
Because the data flash memory is stopped after a reset ends, the data flash control register (DFLCTL) must be set
up in order to use the data flash memory
Manipulating the DFLCTL register is not possible while rewriting the data flash memory
Transition to the HALT/STOP status is not possible while rewriting the data flash memory
Programming of data flash memory is possible while the program is being run by Renesas' library.
29.4.2 Register controlling data flash memory
(1) Data flash control register (DFLCTL)
This register is used to enable or disable accessing to the data flash.
The DFLCTL register is set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets this register to 00H.
Figure 29-6. Format of Data Flash Control Register (DFLCTL)
Address: F0090H
After reset: 00H
R/W
Symbol
7
6
5
4
3
2
1
0
DFLCTL
0
0
0
0
0
0
0
DFLEN
DFLEN
Data flash access control
0
Disables data flash access
1
Enables data flash access
Caution Manipulating the DFLCTL register is not possible while rewriting the data flash memory.
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29.4.3 Procedure for accessing data flash memory
The data flash memory is initially stopped after a reset ends and cannot be accessed (read or programmed). To
access the memory, perform the following procedure:
Write 1 to bit 0 (DFLEN) of the data flash control register (DFLCTL).
Wait for the setup to finish.
The time setup takes differs for each main clock mode.
HS (high-speed main) mode:
5 s
LS (low-speed main) mode:
720 ns
After the wait, the data flash memory can be accessed.
Cautions 1. Accessing the data flash memory is not possible during the setup time.
2. Before executing a STOP instruction during the setup time, temporarily clear DFLEN to 0.
3. Be sure to set the HIOSTOP bit in the CSC register to 0 when the CPU operates with the clock
other than the high-speed on-chip oscillator clock.
4. The data flash should be read in either of following ways.
Use the flash library provided by Renesas (EEL (Pack01) version V1.13 or later).
Stop the DMA transfer before reading.
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29.5 Programming Method
29.5.1 Controlling flash memory
The following figure illustrates the procedure to manipulate the flash memory.
Figure 29-7. Flash Memory Manipulation Procedure
Start
Controlling TOOL0 pin and RESET pin
Flash memory programming
mode is set
Manipulate flash memory
End?
No
Yes
End
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29.5.2 Flash memory programming mode
To rewrite the contents of the flash memory, set the RL78/D1A in the flash memory programming mode. To enter the
mode, set as follows.
Set the TOOL0 pin to the low level, and then cancel the reset. Next, communication from the dedicated flash
memory programmer is performed to automatically switch to the flash memory programming mode.
Set the TOOL0 pin to the low level, and then cancel the reset. Keep the TOOL0 pin at the low level for at least 1 ms
after the reset ends, and then use UART communication to send the data “00H” from the external device. Complete
UART communication within 100 ms after the reset ends.
When performing on-board writing, either switch the mode by using jumpers or perform pin processing in advance so
that it will be okay if the flash memory programming mode is switched to (For details, see 29.3 Connection of Pins on
Board).
Figure 29-8. Setting of Flash Memory Programming Mode
RESET
tHD
TOOL0
tSU
tSUINIT
The low level is input to the TOOL0 pin.
The pins reset ends (POR and LVD reset must end before the pin reset ends).
The TOOL0 pin is set to the high level.
Setting of the flash memory programming mode by UART reception and complete the baud rate setting.
Remark
tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within
100 ms from when the external and internal resets end.
tSU:
How long from when the TOOL0 pin is placed at the low level until a pin reset ends.
tHD:
How long to keep the TOOL0 pin at the low level from when the external and internal resets end.
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Table 29-4. Relationship Between TOOL0 Pin and Operation Mode After Reset Release
TOOL0
VDD
Operation Mode
Normal operation mode
0
Flash memory programming mode
There are two flash memory programming modes for which the voltage range in which to write, erase, or verify data
differs.
Table 29-5. Programming Modes and Voltages at Which Data Can Be Written, Erased, or Verified
Mode
Full speed mode
Voltages at which data can be written, erased, or verified
Writing Clock Frequency
2.7 V to 5.5 V
32 MHz (MAX.)
Note
Note This can only be specified if the CMODE0 bit is 1.
Specify the mode that corresponds to the voltage range in which to write data. When programming by using the
dedicated flash memory programmer, the mode is automatically selected by the voltage setting on GUI.
Remark
For details about communication commands, see 29.5.4 Communication commands..
29.5.3 Selecting communication mode
Communication mode of the RL78/D1A as follows.
Table 29-6. Communication Modes
Communication
Mode
1-line mode
Standard Setting
Port
UART
(when flash
memory
programmer is
used)
UART0
115200 bps,
Note 1
Pins Used
Frequency
Multiply Rate
TOOL0
TOOLTxD,
250000 bps,
500000 bps,
1 Mbps
UART
(when external
device is used)
Speed
Note 2
115200 bps,
250000 bps,
TOOLRxD
500000 bps,
1 Mbps
Notes 1. Selection items for Standard settings on GUI of the flash memory programmer.
2. Because factors other than the baud rate error, such as the signal waveform slew, also affect
UART communication, thoroughly evaluate the slew as well as the baud rate error.
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29.5.4 Communication commands
The RL78/D1A communicates with the dedicated flash memory programmer or external device by using commands.
The signals sent from the flash memory programmer or external device to the RL78/D1A are called commands, and the
signals sent from the RL78/D1A to the dedicated flash memory programmer or external device are called response.
Figure 29-9. Communication Commands
Dedicated flash
memory programmer
E1
PG-FP5, FL-PR5
Command
Response
RL78/D1A
External device
(such as microcontroller
and ASIC)
The flash memory control commands of the RL78/D1A are listed in the table below. All these commands are issued
from the programmer or external device, and the RL78/D1A perform processing corresponding to the respective
commands.
Table 29-7. Flash Memory Control Commands
Classification
Verify
Command Name
Function
Compares the contents of a specified area of the flash memory with
Verify
data transmitted from the programmer.
Erase
Block Erase
Erases a specified area in the flash memory.
Blank check
Block Blank Check
Checks if a specified block in the flash memory has been correctly
erased.
Write
Programming
Writes data to a specified area in the flash memory.
Getting information
Silicon Signature
Gets the RL78/D1A information (such as the part number and flash
memory configuration).
Security
Others
Checksum
Gets the checksum data for a specified area.
Security Set
Sets security information.
Security Get
Gets security information.
Security Release
Release setting of prohibition of writing.
Reset
Used to detect synchronization status of communication.
Baud Rate Set
Sets baud rate when UART communication mode is selected.
The RL78/D1A returns a response for the command issued by the dedicated flash memory programmer or external
device. The response names sent from the RL78/D1A are listed below.
Table 29-8. Response Names
Response Name
Function
ACK
Acknowledges command/data.
NAK
Acknowledges illegal command/data.
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29.5.5 Description of signature data
When the “silicon signature” command is performed, the RL78/D1A information (such as the part number, flash
memory configuration, and programming firmware version) can be obtained.
Table 29-9 and 29-10 show signature data list and example of signature data list.
Table 29-9. Signature Data List
Field name
Description
Number of transmit
data
Device code
The serial number assigned to the device
3 bytes
Device name
Device name (ASCII code)
10 bytes
Last address of code flash memory area
3 bytes
Code flash memory area last address
(Sent from lower address.
Example. 00000H to 0FFFFH (64 KB) → FFH, 1FH, 00H)
Data flash memory area last address
Last address of data flash memory area
3 bytes
(Sent from lower address.
Example. F1000H to F1FFFH (4 KB) → FFH, 1FH, 0FH)
Firmware version
Version information of firmware for programming
3 bytes
(Sent from upper address.
Example. From Ver. 1.23 → 01H, 02H, 03H)
Table 28-10. Example of Signature Data
Field name
Description
Number of transmit
Device code
RL78 protocol A
3 bytes
Data (hexadecimal)
data
10
00
06
Device name
R5F10DPJ
10 bytes
52 = “R”
35 = “5”
46 = “F”
31 = “1”
30 = “0”
44 = “D”
50 = “P”
4A = “J”
20 = “ ”
20 = “ ”
Code flash memory area last address
Code flash memory area
3 bytes
00000H to 3FFFFH (256 KB)
FF
FF
03
Data flash memory area last address
Data flash memory area
3 bytes
FF
2F
F1000H to F2FFFH (8 KB)
0F
Firmware version
Ver.1.23
3 bytes
01
02
03
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29.6 Security Settings
The RL78/D1A supports a security function that prohibits rewriting the user program written to the internal flash
memory, so that the program cannot be changed by an unauthorized person.
The operations shown below can be performed using the Security Set command. The security setting is valid when the
programming mode is set next.
Disabling block erase
Execution of the block erase command for a specific block in the flash memory is prohibited during on-board/offboard programming. However, blocks can be erased by means of self-programming.
Disabling write
Execution of the write command for entire blocks in the flash memory is prohibited during on-board/off-board
programming. However, blocks can be written by means of self-programming.
Disabling rewriting boot cluster 0
Execution of the block erase command and write command on boot cluster 0 (00000H to 00FFFH) in the flash
memory is prohibited by this setting.
The block erase, write commands and rewriting boot cluster 0 are enabled by the default setting when the flash
memory is shipped. Security can be set by on-board/off-board programming and self-programming. Each security setting
can be used in combination.
Table 29-11 shows the relationship between the erase and write commands when the RL78/D1A security function is
enabled.
Remark To prohibit writing and erasing during self-programming, use the flash sealed window function (see 29.7.2 for
detail).
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Table 29-11. Relationship Between Enabling Security Function and Command
(1) During on-board/off-board programming
Valid Security
Executed Command
Block Erase
Write
Note
Prohibition of block erase
Blocks cannot be erased.
Can be performed.
Prohibition of writing
Blocks can be erased.
Cannot be performed.
Prohibition of rewriting boot cluster 0
Boot cluster 0 cannot be erased.
Boot cluster 0 cannot be written.
Note Confirm that no data has been written to the write area. Because data cannot be erased after block erase is
prohibited, do not write data if the data has not been erased.
(2) During self-programming
Valid Security
Executed Command
Block Erase
Prohibition of block erase
Write
Blocks can be erased.
Can be performed.
Boot cluster 0 cannot be erased.
Boot cluster 0 cannot be written.
Prohibition of writing
Prohibition of rewriting boot cluster 0
Remark To prohibit writing and erasing during self-programming, use the flash sealed window function (see 29.7.2 for
detail).
Table 29-12. Setting Security in Each Programming Mode
(1) On-board/off-board programming
Security
Security Setting
How to Disable Security Setting
Prohibition of block erase
Set via GUI of dedicated flash memory
Cannot be disabled after set.
Prohibition of writing
programmer, etc.
Execute security release command
Prohibition of rewriting boot cluster 0
Cannot be disabled after set.
Caution The security release command can be applied only when the security is not set as the block erase
prohibition and the boot cluster 0 rewrite prohibition with code flash memory area and data flash
memory area being blanks.
(2) Self programming
Security
Security Setting
How to Disable Security Setting
Prohibition of block erase
Set by using flash self-programming
Cannot be disabled after set.
Prohibition of writing
library.
Execute security release command during
on-board/off-board programming (cannot
be disabled during self-programming)
Prohibition of rewriting boot cluster 0
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29.7 Flash Memory Programming by Self-Programming
The RL78/D1A supports a self-programming function that can be used to rewrite the flash memory via a user program.
Because this function allows a user application to rewrite the flash memory by using the RL78/D1A self-programming
library, it can be used to upgrade the program in the field.
Cautions 1. The self-programming function cannot be used when the CPU operates with the subsystem clock.
Be sure to set the HIOSTOP bit in the CSC register to 0 when using the self-programming
function if the CPU operates with the main system clock.
2. To prohibit an interrupt during self-programming, in the same way as in the normal operation
mode, execute the self-programming library in the state where the IE flag is cleared (0) by the DI
instruction. To enable an interrupt, clear (0) the interrupt mask flag to accept in the state where
the IE flag is set (1) by the EI instruction, and then execute the self-programming library.
3. Do not transit to standby mode during self-programming.
Remarks 1. For details of the self-programming function and the RL78/D1A self-programming library, refer to RL78
Microcontroller Self Programming Library Type01 User’s Manual.
2. For details of the time required to execute self-programming, see the notes on use that accompany the
flash self-programming library tool.
Similar to when writing data by using the flash memory programmer, there are two flash memory programming modes
for which the voltage range in which to write, erase, or verify data differs.
Table 28-13. Programming Modes and Voltages at Which Data Can Be Written, Erased, or Verified
Mode
Full speed mode
Note
Voltages at which data can be written, erased, or verified
Writing Clock Frequency
2.7 V to 5.5 V
32 MHz (MAX.)
Note This can only be specified if the CMODE0 bits bit is 1.
The argument fsl_flash_voltage_u08 must be set to 00H when the FSL_Init function of the self-programming library
provided by Renesas Electronics.
Remark For details of the self-programming function and the RL78/D1A self-programming library, refer to
RL78 Microcontroller Self Programming Library Type01 User’s Manual.
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The following figure illustrates a flow of rewriting the flash memory by using a self-programming library.
Figure 29-10. Flow of Self Programming (Rewriting Flash Memory)
Flash memory control start
Initialize flash environment
Flash shield window setting
Erase
Inhibit access to flash memory
Write
Inhibit shifting STOP mode
Inhibit clock stop
Verify
Flash information getting
Flash information setting
Close flash environment
End
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29.7.1 Boot swap function
If rewriting the boot area failed by temporary power failure or other reasons, restarting a program by resetting or
overwriting is disabled due to data destruction in the boot area.
The boot swap function is used to avoid this problem.
Before erasing boot cluster 0Note, which is a boot program area, by self-programming, write a new boot program to boot
cluster 1 in advance. When the program has been correctly written to boot cluster 1, swap this boot cluster 1 and boot
cluster 0 by using the set information function of the firmware of the RL78/D1A, so that boot cluster 1 is used as a boot
area. After that, erase or write the original boot program area, boot cluster 0.
As a result, even if a power failure occurs while the boot programming area is being rewritten, the program is executed
correctly because it is booted from boot cluster 1 to be swapped when the program is reset and started next.
Note A boot cluster is a 8 KB area and boot clusters 0 and 1 are swapped by the boot swap function.
Figure 29-11. Boot Swap Function
XXXXXH
User program
Self-programming
to boot cluster 1
Execution of boot
swap by firmware
User program
User program
Self-programming
to boot cluster 0
User program
04000H
User program
New boot program
(boot cluster 1)
Boot program
(boot cluster 0)
New user program
(boot cluster 0)
Boot program
(boot cluster 0)
Boot program
(boot cluster 0)
New boot program
(boot cluster 1)
New boot program
(boot cluster 1)
02000H
00000H
Boot
Boot
Boot
Boot
In an example of above figure, it is as follows.
Boot cluster 0: Boot program area before boot swap
Boot cluster 1: Boot program area after boot swap
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Figure 29-12. Example of Executing Boot Swapping
Block number
Boot
cluster 1
Boot
cluster 0
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Program
Program
Program
Program
Program
Program
Program
Program
02000H
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
00000H
Erasing block 8
Erasing block 9
Erasing block F
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Program
Program
Program
Program
Program
Program
Program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Program
Program
Program
Program
Program
Program
......
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Booted by boot cluster 0
Writing blocks 8 to F
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Boot swap
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
02000H
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program 0 0 0 0 0 H
Erasing block 8
Erasing block 9
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
Booted by boot cluster 1
Erasing block A
Erasing block F
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Boot program
Boot program
Boot program
Boot program
Boot program
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
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New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
Writing blocks 8 to F
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
02000H
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program 0 0 0 0 0 H
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CHAPTER 29 FLASH MEMORY
29.7.2 Flash shield window function
The flash shield window function is provided as one of the security functions for self-programming. It disables writing to
and erasing areas outside the range specified as a window only during self-programming.
The window range can be set by specifying the start and end blocks. The window range can be set or changed during
both on-board/off-board programming and self-programming.
Writing to and erasing areas outside the window range are disabled during self-programming. During on-board/offboard programming, however, areas outside the range specified as a window can be written and erased.
Figure 29-13. Flash Shield Window Setting Example
(Start Block: 04H, End Block: 06H)
0FFFFH
Flash shield
range
Methods by which writing can be performed
Block 3FH
√: On-board/off-board programming
×: Self programming
Block 3EH
01C00H
01BFFH
Window range
Block 06H
(end block)
√: On-board/off-board programming
√: Self programming
Block 05H
Flash memory
area
01000H
00FFFH
Block 04H
(start block)
Block 03H
Block 02H
Flash shield
range
√: On-board/off-board programming
×: Self programming
Block 01H
00000H
Block 00H
Cautions 1. If the rewrite-prohibited area of the boot cluster 0 overlaps with the flash shield window range,
prohibition to rewrite the boot cluster 0 takes priority.
2. The flash shield window can only be used for the code flash memory (and is not supported for
the data flash memory).
Table 29-14. Relationship between Flash Shield Window Function Setting/Change Methods and Commands
Programming conditions
Window Range
Execution Commands
Setting/Change Methods
Block erase
Write
Specify the starting and
Block erasing is enabled
Writing is enabled only
ending blocks by the set
only within the window
within the range of
information library.
range.
window range.
On-board/Off-board
Specify the starting and
Block erasing is enabled
Writing is enabled also
programming
ending blocks on GUI of
also outside the window
outside the window
dedicated flash memory
range.
range.
Self-programming
programmer, etc.
Remark See 29.6 Security Settings to prohibit writing/erasing during on-board/off-board programming.
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CHAPTER 30 ON-CHIP DEBUG FUNCTION
CHAPTER 30 ON-CHIP DEBUG FUNCTION
30.1 Connecting E1 On-chip Debugging Emulator to RL78/D1A
____________
The RL78/D1A uses the VDD, RESET, TOOL0, and VSS pins to communicate with the host machine via an E1 on-chip
debugging emulator. Serial communication is performed by using a single-line UART that uses the TOOL0 pin.
Caution
The RL78/D1A has an on-chip debug function, which is provided for development and evaluation. Do
not use the on-chip debug function in products designated for mass production, because the
guaranteed number of rewritable times of the flash memory may be exceeded when this function is
used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for
problems occurring when the on-chip debug function is used.
Figure 30-1. Connection Example of E1 On-chip Debugging Emulator and RL78/D1A
E1 target connector
VDD
VDD
RL78/D1A
VDD
VDD
EVDD
EVDD
EVDD
EMVDD
SMVDD
GND
SMVDD
GND
GND
EVDD
GND
1 kΩ
TOOL0
TOOL0
RESET
RESET
TRESET
RESET
VDD
10 kΩ
1 kΩ
Note 2
Note 1
Reset circuit
Reset signal
Notes 1. Connecting the dotted line is not necessary during flash programming.
2. If the reset circuit on the target system does not have a buffer and generates a reset signal only with
resistors and capacitors, this pull-up resistor is not necessary.
Caution This circuit diagram is assumed that the reset signal outputs from an N-ch O.D. buffer (output
resistor: 100 or less)
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CHAPTER 30 ON-CHIP DEBUG FUNCTION
30.2 On-Chip Debug Security ID
The RL78/D1A has an on-chip debug operation control bit in the flash memory at 000C3H (see CHAPTER 28 OPTION
BYTE) and an on-chip debug security ID setting area at 000C4H to 000CDH, to prevent third parties from reading memory
content.
When the boot swap function is used, also set a value that is the same as that of 020C3H and 020C4H to 020CDH in
advance, because 000C3H, 000C4H to 000CDH and 020C3H, and 020C4H to 020CDH are switched.
Table 30-1. On-Chip Debug Security ID
Address
000C4H to 000CDH
On-Chip Debug Security ID
Any ID code of 10 bytes
020C4H to 020CDH
30.3 Securing of User Resources
To perform communication between the RL78/D1A and E1 on-chip debugging emulator, as well as each debug
function, the securing of memory space must be done beforehand.
If Renesas Electronics assembler or compiler is used, the items can be set by using linker options.
(1) Securement of memory space
The shaded portions in Figure 30-2 are the areas reserved for placing the debug monitor program, so user
programs or data cannot be allocated in these spaces. When using the on-chip debug function, these spaces must
be secured so as not to be used by the user program. Moreover, this area must not be rewritten by the user
program.
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CHAPTER 30 ON-CHIP DEBUG FUNCTION
Figure 30-2. Memory Spaces Where Debug Monitor Programs Are Allocated
Code flash memory
Internal RAM
Use prohibited
SFR area
Note 1
(512 bytes or
256 bytes Note 2 )
Stack area for debugging Internal RAM
(4 bytes) Note 4
area
04000H
Mirror area
020D8H
020CEH
Debug monitor area
(10 bytes)
020C4H
Security ID area
(10 bytes)
Boot cruster 1
Code flash
area
On-chip debug option byte area
(1 byte)
020C3H
02002H
02000H
Debug monitor area
(2 bytes)
Note 3
: Area used for on-chip debugging
000D8H
000CEH
Debug monitor area
(10 bytes)
000C4H
Security ID area
(10 bytes)
Boot cruster 0
On-chip debug option byte area
(1 byte)
000C3H
00002H
00000H
Debug monitor area
(2 bytes)
Note 3
Notes 1. Address differs depending on products as follows.
Products (code flash memory capacity)
Address of Note 1
R5F10CGB
05C00H to 05FFFH
R5F10CGC, R5F10DGC
07C00H to 07FFFH
R5F10CxD, R5F10DxD (x = G, L, M)
0BC00H to 0BFFFH
R5F10CME, R5F10DxE (x = G, L, M, P)
0FC00H to 0FFFFH
R5F10DxF (x = M, P)
17C00H to 17FFFH
R5F10DxG (x = M, P)
1FC00H to 1FFFFH
R5F10DxJ, R5F10TPJ (x = M, P)
3FC00H to 3FFFFH
R5F10DPK
5FC00H to 5FFFFH
R5F10DPL, R5F10DSx (x = L, K, J)
7FC00H to 7FFFFH
2. When real-time RAM monitor (RRM) function and dynamic memory modification (DMM) function are not
used, it is 256 bytes.
3. In debugging, reset vector is rewritten to address allocated to a monitor program.
4. Since this area is allocated immediately before the stack area, the address of this area varies depending on
the stack increase and decrease. That is, 4 extra bytes are consumed for the stack area used.
When using self-programming, 12 extra bytes are consumed for the stack area used.
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CHAPTER 31 BCD CORRECTION CIRCUIT
CHAPTER 31 BCD CORRECTION CIRCUIT
31.1 BCD Correction Circuit Function
The result of addition/subtraction of the BCD (binary-coded decimal) code and BCD code can be obtained as BCD
code with this circuit.
The decimal correction operation result is obtained by performing addition/subtraction having the A register as the
operand and then adding/ subtracting the BCD correction result register (BCDADJ).
31.2 Registers Used by BCD Correction Circuit
The BCD correction circuit uses the following registers.
BCD correction result register (BCDADJ)
(1) BCD correction result register (BCDADJ)
The BCDADJ register stores correction values for obtaining the add/subtract result as BCD code through
add/subtract instructions using the A register as the operand.
The value read from the BCDADJ register varies depending on the value of the A register when it is read and those
of the CY and AC flags.
The BCDADJ register is read by an 8-bit memory manipulation instruction.
Reset input sets this register to undefined.
Figure 31-1. Format of BCD Correction Result Register (BCDADJ)
Address: F00FEH
Symbol
After reset: undefined
7
6
R
5
4
3
2
1
0
BCDADJ
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CHAPTER 31 BCD CORRECTION CIRCUIT
31.3 BCD Correction Circuit Operation
The basic operation of the BCD correction circuit is as follows.
(1) Addition: Calculating the result of adding a BCD code value and another BCD code value by using a
BCD code value
The BCD code value to which addition is performed is stored in the A register.
By adding the value of the A register and the second operand (value of one more BCD code to be added) as
are in binary, the binary operation result is stored in the A register and the correction value is stored in the
BCD correction result register (BCDADJ).
Decimal correction is performed by adding in binary the value of the A register (addition result in binary) and
the BCDADJ register (correction value), and the correction result is stored in the A register and CY flag.
Caution
The value read from the BCDADJ register varies depending on the value of the A register
when it is read and those of the CY and AC flags. Therefore, execute the instruction
after the instruction instead of executing any other instructions. To perform BCD
correction in the interrupt enabled state, saving and restoring the A register is required
within the interrupt function. PSW (CY flag and AC flag) is restored by the RETI instruction.
Examples are shown below.
Example 1: 99 + 89 = 188
Instruction
A Register
CY Flag
AC Flag
BCDADJ Register
;
99H
ADD A, #89H
;
22H
1
1
66H
ADD A, !BCDADJ
;
88H
1
0
A Register
CY Flag
AC Flag
BCDADJ Register
MOV A, #99H
Example 2: 85 + 15 = 100
Instruction
MOV A, #85H
;
85H
ADD A, #15H
;
9AH
0
0
66H
ADD A, !BCDADJ
;
00H
1
1
A Register
CY Flag
AC Flag
BCDADJ Register
Example 3: 80 + 80 = 160
Instruction
MOV A, #80H
;
80H
ADD A, #80H
;
00H
1
0
60H
ADD A, !BCDADJ
;
60H
1
0
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CHAPTER 31 BCD CORRECTION CIRCUIT
(2) Subtraction: Calculating the result of subtracting a BCD code value from another BCD code value by
using a BCD code value
The BCD code value from which subtraction is performed is stored in the A register.
By subtracting the value of the second operand (value of BCD code to be subtracted) from the A register as is
in binary, the calculation result in binary is stored in the A register, and the correction value is stored in the
BCD correction result register (BCDADJ).
Decimal correction is performed by subtracting the value of the BCDADJ register (correction value) from the A
register (subtraction result in binary) in binary, and the correction result is stored in the A register and CY flag.
Caution
The value read from the BCDADJ register varies depending on the value of the A register
when it is read and those of the CY and AC flags. Therefore, execute the instruction
after the instruction instead of executing any other instructions. To perform BCD
correction in the interrupt enabled state, saving and restoring the A register is required
within the interrupt function. PSW (CY flag and AC flag) is restored by the RETI instruction.
An example is shown below.
Example: 91 52 = 39
Instruction
A Register
CY Flag
AC Flag
BCDADJ Register
;
91H
SUB A, #52H
;
3FH
0
1
06H
SUB A, !BCDADJ
;
39H
0
0
MOV A, #91H
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CHAPTER 32 INSTRUCTION SET
CHAPTER 32 INSTRUCTION SET
This chapter lists the instructions in the RL78 microcontroller instruction set.
For details of each operation and
operation code, refer to the separate document RL78 Family User’s Manual: Software (R01US0015E).
Remark
The shaded parts of the tables in Table 32-5 Operation List indicate the operation or instruction format that
is newly added for the RL78 microcontrollers.
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CHAPTER 32 INSTRUCTION SET
32.1 Conventions Used in Operation List
32.1.1 Operand identifiers and specification methods
Operands are described in the “Operand” column of each instruction in accordance with the description method of the
instruction operand identifier (refer to the assembler specifications for details). When there are two or more description
methods, select one of them. Alphabetic letters in capitals and the symbols, #, !, !!, $, $!, [ ], and ES: are keywords and
are described as they are. Each symbol has the following meaning.
#:
Immediate data specification
!:
16-bit absolute address specification
!!:
20-bit absolute address specification
$:
8-bit relative address specification
$!:
16-bit relative address specification
[ ]:
Indirect address specification
ES:: Extension address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #, !, !!, $, $!, [ ], and ES: symbols.
For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in
parentheses in the table below, R0, R1, R2, etc.) can be used for description.
Table 32-1. Operand Identifiers and Specification Methods
Identifier
Description Method
r
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
rp
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
sfr
Special-function register symbol (SFR symbol) FFF00H to FFFFFH
sfrp
Special-function register symbols (16-bit manipulatable SFR symbol. Even addresses only
Note
) FFF00H to
FFFFFH
saddr
FFE20H to FFF1FH Immediate data or labels
saddrp
FFE20H to FF1FH Immediate data or labels (even addresses only
addr20
00000H to FFFFFH Immediate data or labels
addr16
0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions
addr5
0080H to 00BFH Immediate data or labels (even addresses only)
word
16-bit immediate data or label
byte
8-bit immediate data or label
bit
3-bit immediate data or label
RBn
RB0 to RB3
Note
Note
)
Note
)
Bit 0 = 0 when an odd address is specified.
Remark
The special function registers can be described to operand sfr as symbols. See Table 3-5 SFR List for the
symbols of the special function registers.
The extended special function registers can be described to
operand !addr16 as symbols. See Table 3-6 Extended SFR (2nd SFR) List for the symbols of the extended
special function registers.
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CHAPTER 32 INSTRUCTION SET
32.1.2 Description of operation column
The operation when the instruction is executed is shown in the “Operation” column using the following symbols.
Table 32-2. Symbols in “Operation” Column
Symbol
Function
A
A register; 8-bit accumulator
X
X register
B
B register
C
C register
D
D register
E
E register
H
H register
L
L register
ES
ES register
CS
CS register
AX
AX register pair; 16-bit accumulator
BC
BC register pair
DE
DE register pair
HL
HL register pair
PC
Program counter
SP
Stack pointer
PSW
Program status word
CY
Carry flag
AC
Auxiliary carry flag
Z
Zero flag
RBS
Register bank select flag
IE
Interrupt request enable flag
()
Memory contents indicated by address or register contents in parentheses
X H, X L
16-bit registers: XH = higher 8 bits, XL = lower 8 bits
XS, XH, XL
20-bit registers: XS = (bits 19 to 16), XH = (bits 15 to 8), XL = (bits 7 to 0)
Logical product (AND)
Logical sum (OR)
Exclusive logical sum (exclusive OR)
Inverted data
addr5
16-bit immediate data (even addresses only in 0080H to 00BFH)
addr16
16-bit immediate data
addr20
20-bit immediate data
jdisp8
Signed 8-bit data (displacement value)
jdisp16
Signed 16-bit data (displacement value)
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CHAPTER 32 INSTRUCTION SET
32.1.3 Description of flag operation column
The change of the flag value when the instruction is executed is shown in the “Flag” column using the following symbols.
Table 32-3. Symbols in “Flag” Column
Symbol
Change of Flag Value
(Blank)
Unchanged
0
Cleared to 0
1
Set to 1
R
Set/cleared according to the result
Previously saved value is restored
32.1.4 PREFIX instruction
Instructions with “ES:” have a PREFIX operation code as a prefix to extend the accessible data area to the 1 MB space
(00000H to FFFFFH), by adding the ES register value to the 64 KB space from F0000H to FFFFFH. When a PREFIX
operation code is attached as a prefix to the target instruction, only one instruction immediately after the PREFIX operation
code is executed as the addresses with the ES register value added.
A interrupt and DMA transfer are not acknowledged between a PREFIX instruction code and the instruction
immediately after.
Table 32-4. Use Example of PREFIX Operation Code
Instruction
Opcode
1
MOV !addr16, #byte
2
CFH
3
!addr16
4
5
#byte
MOV ES:!addr16, #byte
11H
CFH
MOV A, [HL]
8BH
!addr16
#byte
MOV A, ES:[HL]
11H
8BH
Caution Set the ES register value with MOV ES, A, etc., before executing the PREFIX instruction.
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CHAPTER 32 INSTRUCTION SET
32.2 Operation List
Table 32-5. Operation List (1/17)
Instruction Mnemonic
Operands
Bytes
Group
8-bit data MOV
transfer
Operation
Flag
Z AC CY
r, #byte
2
1
r byte
saddr, #byte
3
1
(saddr) byte
sfr, #byte
3
1
sfr byte
4
1
(addr16) byte
A, r
Note 3
1
1
Ar
r, A
Note 3
1
1
rA
A, saddr
2
1
A (saddr)
saddr, A
2
1
(saddr) A
A, sfr
2
1
A sfr
sfr, A
2
1
sfr A
A, !addr16
3
1
4
A (addr16)
!addr16, A
3
1
(addr16) A
PSW, #byte
3
3
PSW byte
A, PSW
2
1
A PSW
PSW, A
2
3
PSW A
ES, #byte
2
1
ES byte
ES (saddr)
!addr16, #byte
Notes 1.
Clocks
Note 1 Note 2
ES, saddr
3
1
A, ES
2
1
A ES
ES, A
2
1
ES A
CS, #byte
3
1
CS byte
A, CS
2
1
A CS
CS, A
2
1
CS A
A, [DE]
1
1
4
A (DE)
[DE], A
1
1
(DE) A
[DE + byte], #byte
3
1
(DE + byte) byte
A, [DE + byte]
2
1
4
A (DE + byte)
[DE + byte], A
2
1
(DE + byte) A
A, [HL]
1
1
4
A (HL)
[HL], A
1
1
(HL) A
[HL + byte], #byte
3
1
(HL + byte) byte
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data
access.
2.
When the program memory area is accessed.
3.
Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an
instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum.
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CHAPTER 32 INSTRUCTION SET
Table 32-5. Operation List (2/17)
Instruction Mnemonic
Group
Operands
Bytes
Clocks
Operation
Note 1 Note 2
8-bit data MOV
A, [HL + byte]
2
1
4
A (HL + byte)
transfer
[HL + byte], A
2
1
(HL + byte) A
A, [HL + B]
2
1
4
A (HL + B)
[HL + B], A
2
1
(HL + B) A
A, [HL + C]
2
1
4
A (HL + C)
[HL + C], A
2
1
(HL + C) A
word[B], #byte
4
1
(B + word) byte
A, word[B]
3
1
4
A (B + word)
word[B], A
3
1
(B + word) A
word[C], #byte
4
1
(C + word) byte
A, word[C]
3
1
4
A (C + word)
word[C], A
3
1
(C + word) A
word[BC], #byte
4
1
(BC + word) byte
A, word[BC]
3
1
4
A (BC + word)
word[BC], A
3
1
(BC + word) A
[SP + byte], #byte
3
1
(SP + byte) byte
A, [SP + byte]
2
1
A (SP + byte)
[SP + byte], A
2
1
(SP + byte) A
B, saddr
2
1
B (saddr)
B, !addr16
3
1
4
B (addr16)
C, saddr
2
1
C (saddr)
C, !addr16
3
1
4
C (addr16)
X, saddr
2
1
X (saddr)
X, !addr16
3
1
4
X (addr16)
ES:!addr16, #byte
5
2
(ES, addr16) byte
A, ES:!addr16
4
2
5
A (ES, addr16)
ES:!addr16, A
4
2
(ES, addr16) A
A, ES:[DE]
2
2
5
A (ES, DE)
ES:[DE], A
2
2
(ES, DE) A
ES:[DE + byte],#byte
4
2
((ES, DE) + byte) byte
A, ES:[DE + byte]
3
2
5
A ((ES, DE) + byte)
ES:[DE + byte], A
3
2
((ES, DE) + byte) A
Notes 1.
Flag
Z AC CY
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data
access.
2.
When the program memory area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an
instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum.
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CHAPTER 32 INSTRUCTION SET
Table 32-5. Operation List (3/17)
Instruction Mnemonic
Group
Operands
Bytes
Clocks
Operation
Note 1 Note 2
8-bit data MOV
A, ES:[HL]
2
2
5
A (ES, HL)
transfer
ES:[HL], A
2
2
(ES, HL) A
ES:[HL + byte],#byte
4
2
((ES, HL) + byte) byte
A, ES:[HL + byte]
3
2
5
A ((ES, HL) + byte)
ES:[HL + byte], A
3
2
((ES, HL) + byte) A
A, ES:[HL + B]
3
2
5
A ((ES, HL) + B)
ES:[HL + B], A
3
2
((ES, HL) + B) A
A, ES:[HL + C]
3
2
5
A ((ES, HL) + C)
ES:[HL + C], A
3
2
((ES, HL) + C) A
ES:word[B], #byte
5
2
((ES, B) + word) byte
A, ES:word[B]
4
2
5
A ((ES, B) + word)
ES:word[B], A
4
2
((ES, B) + word) A
ES:word[C], #byte
5
2
((ES, C) + word) byte
A, ES:word[C]
4
2
5
A ((ES, C) + word)
ES:word[C], A
4
2
((ES, C) + word) A
ES:word[BC], #byte
5
2
((ES, BC) + word) byte
A, ES:word[BC]
4
2
5
A ((ES, BC) + word)
ES:word[BC], A
4
2
((ES, BC) + word) A
B, ES:!addr16
4
2
5
B (ES, addr16)
C, ES:!addr16
4
2
5
C (ES, addr16)
4
2
5
X (ES, addr16)
1 (r = X)
2 (other
than r = X)
1
A r
A, saddr
3
2
A (saddr)
A, sfr
3
2
A sfr
A, !addr16
4
2
A (addr16)
A, [DE]
2
2
A (DE)
A, [DE + byte]
3
2
A (DE + byte)
A, [HL]
2
2
A (HL)
A, [HL + byte]
3
2
A (HL + byte)
A, [HL + B]
2
2
A (HL + B)
A, [HL + C]
2
2
A (HL + C)
X, ES:!addr16
XCH
A, r
Note 3
Flag
Z AC CY
Notes 1.
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data
access.
2. When the program memory area is accessed.
3. Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an
instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum.
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Table 32-5. Operation List (4/17)
Instruction Mnemonic
Group
Operands
Bytes
Clocks
Operation
Note 1 Note 2
Flag
Z AC CY
8-bit data XCH
A, ES:!addr16
5
3
A (ES, addr16)
transfer
A, ES:[DE]
3
3
A (ES, DE)
A, ES:[DE + byte]
4
3
A ((ES, DE) + byte)
A, ES:[HL]
3
3
A (ES, HL)
A, ES:[HL + byte]
4
3
A ((ES, HL) + byte)
A, ES:[HL + B]
3
3
A ((ES, HL) + B)
A, ES:[HL + C]
3
3
A ((ES, HL) + C)
A
1
1
A 01H
X
1
1
X 01H
B
1
1
B 01H
C
1
1
C 01H
saddr
2
1
(saddr) 01H
!addr16
3
1
(addr16) 01H
ES:!addr16
4
2
(ES, addr16) 01H
A
1
1
A 00H
X
1
1
X 00H
B
1
1
B 00H
C
1
1
C 00H
saddr
2
1
(saddr) 00H
!addr16
3
1
(addr16) 00H
ES:!addr16
4
2
(ES,addr16) 00H
[HL + byte], X
3
1
(HL + byte) X
ES:[HL + byte], X
4
2
(ES, HL + byte) X
rp, #word
3
1
rp word
saddrp, #word
4
1
(saddrp) word
sfrp, #word
4
1
sfrp word
AX, saddrp
2
1
AX (saddrp)
saddrp, AX
2
1
(saddrp) AX
AX, sfrp
2
1
AX sfrp
ONEB
CLRB
MOVS
16-bit
MOVW
data
transfer
2
1
sfrp AX
AX, rp
Note 3
1
1
AX rp
rp, AX
Note 3
1
1
rp AX
sfrp, AX
Notes 1.
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data
access.
2.
When the program memory area is accessed.
3.
Except rp = AX
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an
instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum.
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Table 32-5. Operation List (5/17)
Instruction Mnemonic
Group
16-bit
MOVW
data
transfer
Notes 1.
Operands
Bytes
Clocks
Operation
Note 1 Note 2
Flag
Z AC CY
AX, !addr16
3
1
4
AX (addr16)
!addr16, AX
3
1
(addr16) AX
AX, [DE]
1
1
4
AX (DE)
[DE], AX
1
1
(DE) AX
AX, [DE + byte]
2
1
4
AX (DE + byte)
[DE + byte], AX
2
1
(DE + byte) AX
AX, [HL]
1
1
4
AX (HL)
[HL], AX
1
1
(HL) AX
AX, [HL + byte]
2
1
4
AX (HL + byte)
[HL + byte], AX
2
1
(HL + byte) AX
AX, word[B]
3
1
4
AX (B + word)
word[B], AX
3
1
(B + word) AX
AX, word[C]
3
1
4
AX (C + word)
word[C], AX
3
1
(C + word) AX
AX, word[BC]
3
1
4
AX (BC + word)
word[BC], AX
3
1
(BC + word) AX
AX, [SP + byte]
2
1
AX (SP + byte)
[SP + byte], AX
2
1
(SP + byte) AX
BC, saddrp
2
1
BC (saddrp)
BC, !addr16
3
1
4
BC (addr16)
DE, saddrp
2
1
DE (saddrp)
DE, !addr16
3
1
4
DE (addr16)
HL, saddrp
2
1
HL (saddrp)
HL, !addr16
3
1
4
HL (addr16)
AX, ES:!addr16
4
2
5
AX (ES, addr16)
ES:!addr16, AX
4
2
(ES, addr16) AX
AX, ES:[DE]
2
2
5
AX (ES, DE)
ES:[DE], AX
2
2
(ES, DE) AX
AX, ES:[DE + byte]
3
2
5
AX ((ES, DE) + byte)
ES:[DE + byte], AX
3
2
((ES, DE) + byte) AX
AX, ES:[HL]
2
2
5
AX (ES, HL)
ES:[HL], AX
2
2
(ES, HL) AX
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data
access.
2.
When the program memory area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an
instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum.
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Table 32-5. Operation List (6/17)
Instruction Mnemonic
Group
16-bit
MOVW
data
transfer
Clocks
Operation
Note 1 Note 2
AX, ES:[HL + byte]
3
2
5
AX ((ES, HL) + byte)
ES:[HL + byte], AX
3
2
((ES, HL) + byte) AX
AX, ES:word[B]
4
2
5
AX ((ES, B) + word)
ES:word[B], AX
4
2
((ES, B) + word) AX
AX, ES:word[C]
4
2
5
AX ((ES, C) + word)
ES:word[C], AX
4
2
((ES, C) + word) AX
AX, ES:word[BC]
4
2
5
AX ((ES, BC) + word)
ES:word[BC], AX
4
2
((ES, BC) + word) AX
BC, ES:!addr16
4
2
5
BC (ES, addr16)
DE, ES:!addr16
4
2
5
DE (ES, addr16)
HL, ES:!addr16
4
2
5
HL (ES, addr16)
1
1
AX rp
Note 3
Flag
Z AC CY
AX, rp
ONEW
AX
1
1
AX 0001H
BC
1
1
BC 0001H
AX
1
1
AX 0000H
BC
1
1
BC 0000H
A, #byte
2
1
A, CY A + byte
saddr, #byte
3
2
(saddr), CY (saddr) + byte
2
1
A, CY A + r
r, A
2
1
r, CY r + A
A, saddr
2
1
A, CY A + (saddr)
A, !addr16
3
1
4
A, CY A + (addr16)
A, [HL]
1
1
4
A, CY A + (HL)
A, [HL + byte]
2
1
4
A, CY A + (HL + byte)
A, [HL + B]
2
1
4
A, CY A + (HL + B)
A, [HL + C]
2
1
4
A, CY A + (HL + C)
A, ES:!addr16
4
2
5
A, CY A + (ES, addr16)
A, ES:[HL]
2
2
5
A,CY A + (ES, HL)
A, ES:[HL + byte]
3
2
5
A,CY A + ((ES, HL) + byte)
A, ES:[HL + B]
3
2
5
A,CY A + ((ES, HL) + B)
A, ES:[HL + C]
3
2
5
A,CY A + ((ES, HL) + C)
ADD
operation
A, r
Notes 1.
Bytes
XCHW
CLRW
8-bit
Operands
Note 4
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data
access.
2.
When the program memory area is accessed.
3.
Except rp = AX
4.
Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an
instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum.
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Table 32-5. Operation List (7/17)
Instruction Mnemonic
Group
8-bit
ADDC
operation
Operands
Operation
Flag
Z AC CY
A, #byte
2
1
A, CY A + byte + CY
saddr, #byte
3
2
(saddr), CY (saddr) + byte + CY
2
1
A, CY A + r + CY
r, A
2
1
r, CY r + A + CY
A, saddr
2
1
A, CY A + (saddr) + CY
A, !addr16
3
1
4
A, CY A + (addr16) + CY
A, [HL]
1
1
4
A, CY A + (HL) + CY
A, [HL + byte]
2
1
4
A, CY A + (HL + byte) + CY
A, [HL + B]
2
1
4
A, CY A + (HL + B) + CY
A, [HL + C]
2
1
4
A, CY A + (HL + C) + CY
A, ES:!addr16
4
2
5
A, CY A + (ES, addr16) + CY
A, ES:[HL]
2
2
5
A, CY A + (ES, HL) + CY
A, ES:[HL + byte]
3
2
5
A, CY A + ((ES, HL) + byte) + CY
A, ES:[HL + B]
3
2
5
A, CY A + ((ES, HL) + B) + CY
A, ES:[HL + C]
3
2
5
A, CY A + ((ES, HL) + C) + CY
A, #byte
2
1
A, CY A byte
Note 3
3
2
(saddr), CY (saddr) byte
2
1
A, CY A r
r, A
2
1
r, CY r A
A, saddr
2
1
A, CY A (saddr)
A, !addr16
3
1
4
A, CY A (addr16)
A, [HL]
1
1
4
A, CY A (HL)
A, [HL + byte]
2
1
4
A, CY A (HL + byte)
A, [HL + B]
2
1
4
A, CY A (HL + B)
saddr, #byte
A, r
Notes 1.
Clocks
Note 1 Note 2
A, r
SUB
Bytes
Note 3
A, [HL + C]
2
1
4
A, CY A (HL + C)
A, ES:!addr16
4
2
5
A, CY A (ES:addr16)
A, ES:[HL]
2
2
5
A, CY A (ES:HL)
A, ES:[HL + byte]
3
2
5
A, CY A ((ES:HL) + byte)
A, ES:[HL + B]
3
2
5
A, CY A ((ES:HL) + B)
A, ES:[HL + C]
3
2
5
A, CY A ((ES:HL) + C)
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data
access.
2.
When the program memory area is accessed.
3.
Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an
instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum.
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Table 32-5. Operation List (8/17)
Instruction Mnemonic
Group
8-bit
SUBC
operation
Operands
Operation
Flag
Z AC CY
A, #byte
2
1
A, CY A byte CY
saddr, #byte
3
2
(saddr), CY (saddr) byte CY
2
1
A, CY A r CY
r, A
2
1
r, CY r A CY
A, saddr
2
1
A, CY A (saddr) CY
A, !addr16
3
1
4
A, CY A (addr16) CY
A, [HL]
1
1
4
A, CY A (HL) CY
A, [HL + byte]
2
1
4
A, CY A (HL + byte) CY
A, [HL + B]
2
1
4
A, CY A (HL + B) CY
A, [HL + C]
2
1
4
A, CY A (HL + C) CY
A, ES:!addr16
4
2
5
A, CY A (ES:addr16) CY
A, ES:[HL]
2
2
5
A, CY A (ES:HL) CY
A, ES:[HL + byte]
3
2
5
A, CY A ((ES:HL) + byte) CY
A, ES:[HL + B]
3
2
5
A, CY A ((ES:HL) + B) CY
A, ES:[HL + C]
3
2
5
A, CY A ((ES:HL) + C) CY
A, #byte
2
1
A A byte
Note 3
3
2
(saddr) (saddr) byte
2
1
AAr
r, A
2
1
rrA
A, saddr
2
1
A A (saddr)
A, !addr16
3
1
4
A A (addr16)
A, [HL]
1
1
4
A A (HL)
A, [HL + byte]
2
1
4
A A (HL + byte)
A, [HL + B]
2
1
4
A A (HL + B)
saddr, #byte
A, r
Notes 1.
Clocks
Note 1 Note 2
A, r
AND
Bytes
Note 3
A, [HL + C]
2
1
4
A A (HL + C)
A, ES:!addr16
4
2
5
A A (ES:addr16)
A, ES:[HL]
2
2
5
A A (ES:HL)
A, ES:[HL + byte]
3
2
5
A A ((ES:HL) + byte)
A, ES:[HL + B]
3
2
5
A A ((ES:HL) + B)
A, ES:[HL + C]
3
2
5
A A ((ES:HL) + C)
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data
access.
2.
When the program memory area is accessed.
3.
Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an
instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum.
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Table 32-5. Operation List (9/17)
Instruction Mnemonic
Group
8-bit
OR
operation
Operands
Operation
Flag
Z AC CY
A, #byte
2
1
A A byte
saddr, #byte
3
2
(saddr) (saddr) byte
2
1
AAr
r, A
2
1
rrA
A, saddr
2
1
A A (saddr)
A, !addr16
3
1
4
A A (addr16)
A, [HL]
1
1
4
A A (HL)
A, [HL + byte]
2
1
4
A A (HL + byte)
A, [HL + B]
2
1
4
A A (HL + B)
A, [HL + C]
2
1
4
A A (HL + C)
A, ES:!addr16
4
2
5
A A (ES:addr16)
A, ES:[HL]
2
2
5
A A (ES:HL)
A, ES:[HL + byte]
3
2
5
A A ((ES:HL) + byte)
A, ES:[HL + B]
3
2
5
A A ((ES:HL) + B)
A, ES:[HL + C]
3
2
5
A A ((ES:HL) + C)
A, #byte
2
1
A A byte
Note 3
3
2
(saddr) (saddr) byte
2
1
AAr
r, A
2
1
rrA
A, saddr
2
1
A A (saddr)
A, !addr16
3
1
4
A A (addr16)
A, [HL]
1
1
4
A A (HL)
A, [HL + byte]
2
1
4
A A (HL + byte)
A, [HL + B]
2
1
4
A A (HL + B)
saddr, #byte
A, r
Notes 1.
Clocks
Note 1 Note 2
A, r
XOR
Bytes
Note 3
A, [HL + C]
2
1
4
A A (HL + C)
A, ES:!addr16
4
2
5
A A (ES:addr16)
A, ES:[HL]
2
2
5
A A (ES:HL)
A, ES:[HL + byte]
3
2
5
A A ((ES:HL) + byte)
A, ES:[HL + B]
3
2
5
A A ((ES:HL) + B)
A, ES:[HL + C]
3
2
5
A A ((ES:HL) + C)
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data
access.
2.
When the program memory area is accessed.
3.
Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an
instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum.
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Table 32-5. Operation List (10/17)
Instruction Mnemonic
Group
8-bit
CMP
operation
Operands
CMPS
Notes 1.
Clocks
Operation
Note 1 Note 2
Flag
Z AC CY
A, #byte
2
1
A byte
saddr, #byte
3
1
(saddr) byte
2
1
Ar
r, A
2
1
rA
A, saddr
2
1
A (saddr)
A, !addr16
3
1
4
A (addr16)
A, [HL]
1
1
4
A (HL)
A, [HL + byte]
2
1
4
A (HL + byte)
A, [HL + B]
2
1
4
A (HL + B)
A, [HL + C]
2
1
4
A (HL + C)
!addr16, #byte
4
1
4
(addr16) byte
A, ES:!addr16
4
2
5
A (ES:addr16)
A, ES:[HL]
2
2
5
A (ES:HL)
A, ES:[HL + byte]
3
2
5
A ((ES:HL) + byte)
A, ES:[HL + B]
3
2
5
A ((ES:HL) + B)
A, ES:[HL + C]
3
2
5
A ((ES:HL) + C)
ES:!addr16, #byte
5
2
5
(ES:addr16) byte
A
1
1
A 00H
X
1
1
X 00H
B
1
1
B 00H
C
1
1
C 00H
saddr
2
1
(saddr) 00H
!addr16
3
1
4
(addr16) 00H
ES:!addr16
4
2
5
(ES:addr16) 00H
X, [HL + byte]
3
1
4
X (HL + byte)
X, ES:[HL + byte]
4
2
5
X ((ES:HL) + byte)
A, r
CMP0
Bytes
Note 3
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data
access.
2.
When the program memory area is accessed.
3.
Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an
instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum.
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Table 32-5. Operation List (11/17)
Instruction Mnemonic
Group
16-bit
ADDW
operation
SUBW
CMPW
Multiply
Notes 1.
MULU
Operands
Bytes
Clocks
Operation
Note 1 Note 2
Flag
Z AC CY
AX, #word
3
1
AX, CY AX + word
AX, AX
1
1
AX, CY AX + AX
AX, BC
1
1
AX, CY AX + BC
AX, DE
1
1
AX, CY AX + DE
AX, HL
1
1
AX, CY AX + HL
AX, saddrp
2
1
AX, CY AX + (saddrp)
AX, !addr16
3
1
4
AX, CY AX + (addr16)
AX, [HL+byte]
3
1
4
AX, CY AX + (HL + byte)
AX, ES:!addr16
4
2
5
AX, CY AX + (ES:addr16)
AX, ES: [HL+byte]
4
2
5
AX, CY AX + ((ES:HL) + byte)
AX, #word
3
1
AX, CY AX word
AX, BC
1
1
AX, CY AX BC
AX, DE
1
1
AX, CY AX DE
AX, HL
1
1
AX, CY AX HL
AX, saddrp
2
1
AX, CY AX (saddrp)
AX, !addr16
3
1
4
AX, CY AX (addr16)
AX, [HL+byte]
3
1
4
AX, CY AX (HL + byte)
AX, ES:!addr16
4
2
5
AX, CY AX (ES:addr16)
AX, ES: [HL+byte]
4
2
5
AX, CY AX ((ES:HL) + byte)
AX, #word
3
1
AX word
AX, BC
1
1
AX BC
AX, DE
1
1
AX DE
AX, HL
1
1
AX HL
AX, saddrp
2
1
AX (saddrp)
AX, !addr16
3
1
4
AX (addr16)
AX, [HL+byte]
3
1
4
AX (HL + byte)
AX, ES:!addr16
4
2
5
AX (ES:addr16)
AX, ES: [HL+byte]
4
2
5
AX ((ES:HL) + byte)
X
1
1
AX A X
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data
access.
2.
When the program memory area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an
instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum.
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CHAPTER 32 INSTRUCTION SET
Table 32-5. Operation List (12/17)
Instruction Mnemonic
Group
Operands
Bytes
Clocks
Operation
Note 1 Note 2
Flag
Z AC CY
Increment/ INC
r
1
1
rr+1
decrement
saddr
2
2
(saddr) (saddr) + 1
!addr16
3
2
(addr16) (addr16) + 1
(HL+byte) (HL+byte) + 1
[HL+byte]
3
2
ES:!addr16
4
3
(ES, addr16) (ES, addr16) + 1
ES: [HL+byte]
4
3
((ES:HL) + byte) ((ES:HL) + byte) + 1
r
1
1
rr1
saddr
2
2
(saddr) (saddr) 1
!addr16
3
2
(addr16) (addr16) 1
[HL+byte]
3
2
(HL+byte) (HL+byte) 1
ES:!addr16
4
3
(ES, addr16) (ES, addr16) 1
ES: [HL+byte]
4
3
((ES:HL) + byte) ((ES:HL) + byte) 1
rp
1
1
rp rp + 1
saddrp
2
2
(saddrp) (saddrp) + 1
!addr16
3
2
(addr16) (addr16) + 1
[HL+byte]
3
2
(HL+byte) (HL+byte) + 1
ES:!addr16
4
3
(ES, addr16) (ES, addr16) + 1
ES: [HL+byte]
4
3
((ES:HL) + byte) ((ES:HL) + byte) + 1
rp
1
1
rp rp 1
saddrp
2
2
(saddrp) (saddrp) 1
!addr16
3
2
(addr16) (addr16) 1
[HL+byte]
3
2
(HL+byte) (HL+byte) 1
ES:!addr16
4
3
(ES, addr16) (ES, addr16) 1
ES: [HL+byte]
4
3
((ES:HL) + byte) ((ES:HL) + byte) 1
SHR
A, cnt
2
1
(CY A0, Am1 Am, A7 0) cnt
SHRW
AX, cnt
2
1
(CY AX0, AXm1 AXm, AX15 0) cnt
SHL
A, cnt
2
1
(CY A7, Am Am1, A0 0) cnt
B, cnt
2
1
(CY B7, Bm Bm1, B0 0) cnt
C, cnt
2
1
(CY C7, Cm Cm1, C0 0) cnt
AX, cnt
2
1
(CY AX15, AXm AXm1, AX0 0) cnt
BC, cnt
2
1
(CY BC15, BCm BCm1, BC0 0) cnt
SAR
A, cnt
2
1
(CY A0, Am1 Am, A7 A7) cnt
SARW
AX, cnt
2
1
(CY AX0, AXm1 AXm, AX15 AX15) cnt
DEC
INCW
DECW
Shift
SHLW
Notes 1.
2.
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data
access.
When the program memory area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an
instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum.
3. cnt indicates the bit shift count.
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Table 32-5. Operation List (13/17)
Instruction Mnemonic
Group
Rotate
Bit
Bytes
Clocks
Operation
Note 1 Note 2
Flag
Z AC CY
ROR
A, 1
2
1
(CY, A7 A0, Am1 Am) 1
ROL
A, 1
2
1
(CY, A0 A7, Am + 1 Am) 1
RORC
A, 1
2
1
(CY A0, A7 CY, Am1 Am) 1
ROLC
A, 1
2
1
(CY A7, A0 CY, Am + 1 Am) 1
ROLWC
AX,1
2
1
(CY AX15, AX0 CY, AXm + 1 AXm) 1
BC,1
2
1
(CY BC15, BC0 CY, BCm + 1 BCm) 1
CY, saddr.bit
3
1
CY (saddr).bit
CY, sfr.bit
3
1
CY sfr.bit
MOV1
manipulate
AND1
OR1
Notes 1.
Operands
CY, A.bit
2
1
CY A.bit
CY, PSW.bit
3
1
CY PSW.bit
CY,[HL].bit
2
1
4
CY (HL).bit
saddr.bit, CY
3
2
(saddr).bit CY
sfr.bit, CY
3
2
sfr.bit CY
A.bit, CY
2
1
A.bit CY
PSW.bit, CY
3
4
PSW.bit CY
[HL].bit, CY
2
2
(HL).bit CY
CY, ES:[HL].bit
3
2
5
CY (ES, HL).bit
ES:[HL].bit, CY
3
3
(ES, HL).bit CY
CY, saddr.bit
3
1
CY CY (saddr).bit
CY, sfr.bit
3
1
CY CY sfr.bit
CY, A.bit
2
1
CY CY A.bit
CY, PSW.bit
3
1
CY CY PSW.bit
CY,[HL].bit
2
1
4
CY CY (HL).bit
CY, ES:[HL].bit
3
2
5
CY CY (ES, HL).bit
CY, saddr.bit
3
1
CY CY (saddr).bit
CY, sfr.bit
3
1
CY CY sfr.bit
CY, A.bit
2
1
CY CY A.bit
CY, PSW.bit
3
1
CY CY PSW.bit
CY, [HL].bit
2
1
4
CY CY (HL).bit
CY, ES:[HL].bit
3
2
5
CY CY (ES, HL).bit
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data
access.
2.
When the program memory area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an
instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum.
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Table 32-5. Operation List (14/17)
Instruction Mnemonic
Group
Bit
Bytes
Clocks
Operation
Note 1 Note 2
Flag
Z AC CY
CY, saddr.bit
3
1
CY CY (saddr).bit
CY, sfr.bit
3
1
CY CY sfr.bit
CY, A.bit
2
1
CY CY A.bit
CY, PSW.bit
3
1
CY CY PSW.bit
CY, [HL].bit
2
1
4
CY CY (HL).bit
CY, ES:[HL].bit
3
2
5
CY CY (ES, HL).bit
saddr.bit
3
2
(saddr).bit 1
sfr.bit
3
2
sfr.bit 1
A.bit
2
1
A.bit 1
!addr16.bit
4
2
(addr16).bit 1
PSW.bit
3
4
PSW.bit 1
[HL].bit
2
2
(HL).bit 1
ES:!addr16.bit
5
3
(ES, addr16).bit 1
ES:[HL].bit
3
3
(ES, HL).bit 1
saddr.bit
3
2
(saddr.bit) 0
sfr.bit
3
2
sfr.bit 0
A.bit
2
1
A.bit 0
!addr16.bit
4
2
(addr16).bit 0
PSW.bit
3
4
PSW.bit 0
[HL].bit
2
2
(HL).bit 0
ES:!addr16.bit
5
3
(ES, addr16).bit 0
ES:[HL].bit
3
3
(ES, HL).bit 0
SET1
CY
2
1
CY 1
1
CLR1
CY
2
1
CY 0
0
NOT1
CY
2
1
CY CY
XOR1
manipulate
SET1
CLR1
Notes 1.
Operands
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data
access.
2.
When the program memory area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an
instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum.
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Table 32-5. Operation List (15/17)
Instruction Mnemonic
Group
Call/
CALL
Operands
Bytes
Clocks
Operation
Note 1 Note 2
rp
2
3
Flag
Z AC CY
(SP 2) (PC + 2)S, (SP 3) (PC + 2)H,
(SP 4) (PC + 2)L, PC CS, rp,
return
SP SP 4
$!addr20
3
3
(SP 2) (PC + 3)S, (SP 3) (PC + 3)H,
(SP 4) (PC + 3)L, PC PC + 3 +
jdisp16,
SP SP 4
!addr16
3
3
(SP 2) (PC + 3)S, (SP 3) (PC + 3)H,
(SP 4) (PC + 3)L, PC 0000, addr16,
SP SP 4
!!addr20
4
3
(SP 2) (PC + 4)S, (SP 3) (PC + 4)H,
(SP 4) (PC + 4)L, PC addr20,
SP SP 4
CALLT
[addr5]
2
5
(SP 2) (PC + 2)S, (SP 3) (PC + 2)H,
(SP 4) (PC + 2)L , PCS 0000,
PCH (0000, addr5 + 1),
PCL (0000, addr5),
SP SP 4
BRK
2
5
(SP 1) PSW, (SP 2) (PC + 2)S,
(SP 3) (PC + 2)H, (SP 4) (PC + 2)L,
PCS 0000,
PCH (0007FH), PCL (0007EH),
SP SP 4, IE 0
RET
1
6
PCL (SP), PCH (SP + 1),
PCS (SP + 2), SP SP + 4
RETI
2
6
PCL (SP), PCH (SP + 1),
R
R
R
R
R
R
PCS (SP + 2), PSW (SP + 3),
SP SP + 4
RETB
2
6
PCL (SP), PCH (SP + 1),
PCS (SP + 2), PSW (SP + 3),
SP SP + 4
Notes 1.
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data
access.
2.
When the program memory area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an
instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum.
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Table 32-5. Operation List (16/17)
Instruction Mnemonic
Group
Stack
PUSH
Operands
Bytes
Clocks
Operation
Note 1 Note 2
PSW
2
1
rp
1
1
Flag
Z AC CY
(SP 1) PSW, (SP 2) 00H,
SP SP 2
manipulate
(SP 1) rpH, (SP 2) rpL,
SP SP 2
PSW
2
3
PSW (SP + 1), SP SP + 2
rp
1
1
rpL (SP), rpH (SP + 1), SP SP + 2
SP, #word
4
1
SP word
SP, AX
2
1
SP AX
AX, SP
2
1
AX SP
HL, SP
3
1
HL SP
BC, SP
3
1
BC SP
DE, SP
3
1
DE SP
ADDW
SP, #byte
2
1
SP SP + byte
SUBW
SP, #byte
2
1
SP SP byte
Unconditional BR
AX
2
3
PC CS, AX
branch
$addr20
2
3
PC PC + 2 + jdisp8
$!addr20
3
3
PC PC + 3 + jdisp16
!addr16
3
3
PC 0000, addr16
!!addr20
4
$addr20
2
POP
MOVW
Conditional BC
branch
BNC
BZ
BNZ
BH
$addr20
$addr20
$addr20
$addr20
2
2
2
3
3
PC addr20
2/4
Note 3
PC PC + 2 + jdisp8 if CY = 1
2/4
Note 3
PC PC + 2 + jdisp8 if CY = 0
2/4
Note 3
PC PC + 2 + jdisp8 if Z = 1
2/4
Note 3
PC PC + 2 + jdisp8 if Z = 0
2/4
Note 3
PC PC+3+jdisp8 if (Z CY)=0
PC PC+3+jdisp8 if (Z CY)=1
BNH
$addr20
3
2/4
Note 3
BT
saddr.bit, $addr20
4
3/5
Note 3
PC PC + 4 + jdisp8 if (saddr).bit = 1
sfr.bit, $addr20
4
3/5
Note 3
PC PC + 4 + jdisp8 if sfr.bit = 1
A.bit, $addr20
3
3/5
Note 3
PC PC + 3 + jdisp8 if A.bit = 1
3/5
Note 3
PC PC + 4 + jdisp8 if PSW.bit = 1
3/5
Note 3
6/7
PC PC + 3 + jdisp8 if (HL).bit = 1
4/6
Note 3
7/8
PC PC + 4 + jdisp8
PSW.bit, $addr20
[HL].bit, $addr20
ES:[HL].bit,
4
3
4
$addr20
Notes 1.
R
R
R
if (ES, HL).bit = 1
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data
access.
2.
When the program memory area is accessed.
3.
This indicates the number of clocks “when condition is not met/when condition is met”.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an
instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum.
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Table 32-5. Operation List (17/17)
Instruction Mnemonic
Group
Operands
Bytes
Clocks
Operation
Note 1 Note 2
Conditional BF
saddr.bit, $addr20
4
3/5
Note 3
PC PC + 4 + jdisp8 if (saddr).bit = 0
branch
sfr.bit, $addr20
4
3/5
Note 3
PC PC + 4 + jdisp8 if sfr.bit = 0
3/5
Note 3
PC PC + 3 + jdisp8 if A.bit = 0
3/5
Note 3
PC PC + 4 + jdisp8 if PSW.bit = 0
3/5
Note 3
6/7
PC PC + 3 + jdisp8 if (HL).bit = 0
4/6
Note 3
7/8
PC PC + 4 + jdisp8 if (ES, HL).bit = 0
3/5
Note 3
3/5
Note 3
A.bit, $addr20
PSW.bit, $addr20
[HL].bit, $addr20
ES:[HL].bit, $addr20
BTCLR
saddr.bit, $addr20
3
4
3
4
4
Flag
Z AC CY
PC PC + 4 + jdisp8 if (saddr).bit = 1
then reset (saddr).bit
sfr.bit, $addr20
4
PC PC + 4 + jdisp8 if sfr.bit = 1
then reset sfr.bit
A.bit, $addr20
3
3/5
Note 3
PSW.bit, $addr20
4
3/5
Note 3
PC PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
PC PC + 4 + jdisp8 if PSW.bit = 1
then reset PSW.bit
[HL].bit, $addr20
3
3/5
Note 3
4/6
Note 3
PC PC + 3 + jdisp8 if (HL).bit = 1
then reset (HL).bit
ES:[HL].bit, $addr20
4
PC PC + 4 + jdisp8 if (ES, HL).bit = 1
then reset (ES, HL).bit
Conditional SKC
2
1
Next instruction skip if CY = 1
skip
SKNC
2
1
Next instruction skip if CY = 0
SKZ
2
1
Next instruction skip if Z = 1
SKNZ
2
1
Next instruction skip if Z = 0
SKH
2
1
Next instruction skip if (Z CY) = 0
SKNH
2
1
Next instruction skip if (Z CY) = 1
2
1
RBS[1:0] n
CPU
SEL
control
NOP
1
1
No Operation
EI
3
4
IE 1(Enable Interrupt)
DI
3
4
IE 0(Disable Interrupt)
HALT
2
3
Set HALT Mode
STOP
2
3
Set STOP Mode
Notes 1.
RBn
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data
access.
2.
When the program memory area is accessed.
3.
This indicates the number of clocks “when condition is not met/when condition is met”.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an
instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum.
3. n indicates the number of register banks (n = 0 to 3)
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CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
Cautions 1. These specifications show target values, which may change after device evaluation.
2. The RL78/D1A has an on-chip debug function, which is provided for development and evaluation.
Do not use the on-chip debug function in products designated for mass production, because the
guaranteed number of rewritable times of the flash memory may be exceeded when this function
is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable
for problems occurring when the on-chip debug function is used.
Definition of Pin Groups
Definition of pin groups described in this chapter is shown in the following table.
Pin groups
Pin names
48-pin products
Pin group 1 Group 1R P40
64-pin products
P40, P70, P71
80-pin products
P40, P70, P71
100-pin products
128-pin products
P40, P70, P71,
P40 to P44,
P130 to P135,
P70, P71,
P140
P100 to P103,
P130 to P135,
P140
Group 1L
P00 to P01,
P00 to P05, P07,
P00 to P07,
P00 to P07,
P00 to P07,
P10 to P14,
P10 to P15, P17,
P10 to P17,
P10 to P17,
P10 to P17,
P30 to P33,
P30 to P33,
P30 to P37,
P30 to P37,
P30 to P37,
P54 to P57, P60, P54 to P57, P60,
P54 to P57,P60,
P50 to P57,
P45 to P47,
P61, P72 to P75 P61, P72 to P75
P61, P65, P66,
P72 to P75, P136
P50 to P57,
P72 to P75,
P72 to P75
P104 to P107,
P110 to P117,
P125 to P127
P136
Group 1C Pin group 2 (ANI pins)
-
P20 to P23, P27 P20 to P23, P27
-
P60 to P66
P60 to P66
P20 to P27
P20 to P27, P150
P20 to P27,
P150 to P152
Pin group 3 Group 3A P80 to P83
P80 to P83
P80 to P83
P80 to P83
P80 to P83
(SMC pins) Group 3B -
P84 to P87
P84 to P87
P84 to P87
P84 to P87
Group 3C P90 to P94
P90 to P94
P90 to P93
P90 to P93
P90 to P93
Group 3D -
-
P94 to P97
P94 to P97
P94 to P97
-
P121 to P124,
Group 3E P90 to P94
P84 to P87, P90 to P94
Pin group 4
(System pins)
P121 to P122,
P121 to P124,
P121 to P124,
P121 to P124,
____________
____________
____________
____________
RESET, P137
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RESET, P137
RESET, P137
____________
RESET, P137
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CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
Definition of Product Groups
Definition of product groups described in this chapter is shown in the following table.
Product groups
Product names
48-pin products
Product Group A
64-pin products
80-pin products
100-pin products
R5F10CGBJFB
R5F10CLDJFB
R5F10CMDJFB
R5F10DPEJFB
R5F10CGCJFB
R5F10DLDJFB
R5F10CMEJFB
R5F10DPFJFB
R5F10CGDJFB
R5F10DLEJFB
R5F10DMDJFB
R5F10DPGJFB
R5F10DGCJFB
R5F10DMEJFB
R5F10DPJJFB
R5F10DGDJFB
R5F10DMFJFB
R5F10TPJJFB
R5F10DGEJFB
R5F10DMGJFB
128-pin products
-
R5F10DMJJFB
Product Group B
-
-
-
R5F10DPKJFB
R5F10DSJJFB
R5F10DPLJFB
R5F10DSKJFB
R5F10DSLJFB
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CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
33.1 Absolute Maximum Ratings
TA = +25 C
Parameter
Supply voltage
Symbols
Conditions
VDD
VDD
EVDD0
EVDD0 = EVDD1
EVDD1
SMVDD0
Ratings
Unit
-0.5 to +6.5
V
-0.5 to +6.5
V
and -0.5 to VDD + 0.3
SMVDD0 = SMVDD1
SMVDD1
-0.5 to +6.5
V
and -0.5 to VDD + 0.3
VSS
VSS
-0.5 to +0.3
V
EVSS0
EVSS0 = EVSS1
-0.5 to +0.3
V
SMVSS0 = SMVSS1
-0.5 to +0.3
V
50
V/ms
EVSS1
SMVSS0
SMVSS1
Supply voltage
VDDRAMP
up/down ramp
REGC pin
VIREGC
REGC
Input voltage
VI1
Pin group 1
VI2
Pin group 2
VI3
Pin group 3
VI4
Pin group 4
V
-0.3 to +2.8
and -0.3 to VDD + 0.3
input voltage
Note1
-0.3 to +6.5
V
and -0.3 to EVDD0(EVDD1) + 0.3
-0.3 to +6.5
V
and -0.3 to VDD + 0.3
-0.3 to +6.5
V
and -0.3 to SMVDD0(SMVDD1) + 0.3
-0.3 to +6.5
V
and -0.3 to VDD + 0.3
(Continue to next page)
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TA = +25 C
Parameter
Output voltage
Output current,
high
Symbols
Conditions
Unit
VO1
Pin group 1
-0.3 to EVDD0 (EVDD1) + 0.3
V
VO2
Pin group 2
-0.3 to VDD + 0.3
V
VO3
Pin group 3
-0.3 to SMVDD0 (SMVDD1) + 0.3
V
VCOM
COM0 to COM3
-0.3 to VDD + 0.3
V
IOH1
Per pin
Pin group 1
-20
mA
Total
Pin group 1
-150
mA
Pin group 1L
-60
mA
Pin group 1R
-55
mA
Pin group 1C
IOH2
Per pin
-40
mA
-0.5
mA
-2.0
mA
-58
mA
48-pin, 64-pin
-270
mA
80-pin, 100-pin,
128-pin
-480
mA
Pin group 3A
-120
mA
Pin group 3B
-120
mA
Pin group 3C
-120
mA
Pin group 3D
-120
mA
Pin group 3E
-150
mA
Pin group 2
Total
IOH3
Per pin
Pin group 3
Total
Pin group 3
IOHCOM
Output current,
low
Ratings
IOL1
Per pin
COM0 to COM3
-0.5
mA
Total
COM0 to COM3
-1.0
mA
Per pin
Pin group 1
20
mA
Total
Pin group 1
150
mA
Pin group 1L
60
mA
Pin group 1R
50
mA
Pin group 1C
40
mA
1.0
mA
5.0
mA
58
mA
48-pin, 64-pin
270
mA
80-pin, 100-pin,
128-pin
480
mA
Pin group 3A
120
mA
Pin group 3B
120
mA
Pin group 3C
120
mA
Pin group 3D
120
mA
Pin group 3E
150
mA
IOL2
Per pin
Pin group 2
IOL3
Per pin
Pin group 3
Total
Pin group 3
Total
IOLCOM
Operating
ambient
temperature
TA
Storage
temperature
Tstg
Per pin
COM0 to COM3
0.5
mA
Total
COM0 to COM3
1.0
mA
for normal operation mode
-40 to +85
C
for code flash programming
-40 to +85
C
for data flash programming
-40 to +85
C
-65 to +150
C
Note Connect the REGC pin to Vss via a capacitor (0.47 to 1 F ).
This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it.
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33.2 Power consumption characteristics
33.2.1 Product group A
TA = -40 to +85 C, 2.7 V VDD 5.5 V, VSS = 0 V
Parameter
Symbols
Supply current,
IDD1
Note 1
run mode
Conditions
High speed
fCLK = 32 MHz
Typ.
Max.
Unit
5.2
22
mA
4.2
18
mA
fX = 20 MHz
3.8
16
mA
fHOCO = 8 MHz
2.1
11
mA
1.6
9
mA
6
300
A
fHOCO = 32 MHz
MAIN RUN
fHOCO = 4 MHz with PLL
Note 2, 3, 4
fX = 4 MHz with PLL
fX = 8 MHz with PLL
fCLK = 24 MHz
fHOCO = 24 MHz
fHOCO = 4 MHz with PLL
fX = 4 MHz with PLL
fX = 8 MHz with PLL
fCLK = 20 MHz
fCLK = 8 MHz
fX = 8 MHz
fCLK = 4 MHz
fHOCO = 4 MHz
fX = 4 MHz
SUB RUN
fCLK = fXT = 32.768 kHz
Note 2, 3, 5
Notes 1.
2.
3.
4.
5.
The common condition for IDD1:
- IDD includes the total current flowing into whole power pins, including the input leakage current
flowing when the level of the input pin is fixed to VDD or VSS.
- The program is running in the code flash.
The typical value is that when Ta=+25deg.C and VDD=5.0 V. Peripheral devices and the data
flash are stopped.
The maximum value is that when all peripheral devices are operating. But the A/D converter,
RTC, LCD circuit and stepper motor circuit are stopped, and the data flash and the code flash
are stated to read mode. The 16-bit wakeup timer operates with fLOCO.
Either fX or fHOCO which is selected for fCLK is operated. The other is stopped.
fX and fHOCO are stopped.
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TA = -40 to +85 C, 2.7 V VDD 5.5 V, VSS = 0 V
Parameter
Supply current,
Symbols
IDD2
Note 1
halt mode
Conditions
High speed
fCLK = 32 MHz
fHOCO = 32 MHz
MAIN HALT
2.7 VVDD
fHOCO = 4 MHz with PLL
Note 3, 4, 5
Typ.
Max.
Unit
1.0
8.1
mA
0.8
6.9
mA
fX = 4 MHz with PLL
fX = 8 MHz with PLL
fCLK = 24 MHz
fHOCO = 24 MHz
fHOCO = 4 MHz with PLL
fX = 4 MHz with PLL
fX = 8 MHz with PLL
fCLK = 20 MHz
fX = 20 MHz
0.7
6.0
mA
fCLK = 8 MHz
fHOCO = 8 MHz
0.4
4.3
mA
0.35
3.6
mA
1.0
130
A
60
A
fX = 8 MHz
fCLK = 4 MHz
fHOCO = 4 MHz
fX = 4 MHz
SUB HALT
fCLK = fXT
Note 3, 4, 6
= 32.768 kHz
RTC is stopped
RTC is operated by fXT
1.2
= 32.768KHz
Supply current,
IDD3 Note 2
stop mode
STOP Note 3, 4
RTC and fXT are stopped
0.4
RTC is operated by fXT = 32.768KHz
0.8
The common condition for IDD2:
- IDD includes the total current flowing into whole power pins, including the input leakage current
flowing when the level of the input pin is fixed to VDD or VSS.
- The HALT instruction is executed by the program in the code flash.
- The specification shows the stable current during HALT mode.
2. The common condition for IDD3:
- IDD includes the total current flowing into whole power pins, including the input leakage current
flowing when the level of the input pin is fixed to VDD or VSS.
- The STOP instruction is executed by the program in the code flash during MAIN RUN
operation.
- The spec shows the stable current during STOP mode.
3. The typical value is that when Ta=+25deg.C and VDD=5.0 V. Peripheral devices and the data
flash are stopped.
4. The maximum value is that when all peripheral devices are operating. But the A/D converter,
LCD circuit, stepper motor circuit, the data flash and the code flash are stopped. The 16-bit
wakeup timer operates with fLOCO.
5. Either fX or fHOCO which is selected for fCLK is operated. The other is stopped.
6. fX and fHOCO are stopped.
Notes 1.
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TA = -40 to +85 C, 2.7 V VDD 5.5 V, VSS = 0 V
Parameter
WDT operating
current
IWDT
IADC
Note 2
LCD operating
Current
ILCD
Note 3
ZPD operating
current
Conditions
Typ.
Max.
Unit
0.25
1.0
A
Note 1
ADC operating
current
Symbols
IZPD
Normal mode
VDD = 5.0 V
1.3
1.7
mA
Low voltage mode
VDD = 3.0 V
0.5
0.7
mA
fLCD = fSUB,
VDD = 5.0 V
100
140
A
LCD clock = 512 Hz
VDD = 3.0 V
90
130
A
One ZPD operated
VDD = 5.0 V
150
600
A
VDD = 3.0 V
100
500
A
VDD = 5.0 V
500
2000
A
VDD = 3.0 V
400
1600
A
Note 4
Four ZPDs operated
Notes
1. Current flowing only to the watchdog timer. The maximum specification of IDD1, IDD2 and IDD3 include IWDT.
2. Current flowing only to the A/D converter.The current value of the RL78/D1A is the sum of IDD and IADC
when the A/D converter operates.
3. Current flowing only to the LCD controller/driver circuit. The current value of the RL78/D1A is the sum of IDD
and ILCD when the LCD controller/driver circuit operates.
4. Current flowing only to the ZPD circuit. The current value of the RL78/D1A is the sum of IDD and IZPD when
the ZPD circuit operates.
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33.2.2 Product group B
TA = -40 to +85 C, 2.7 V VDD 5.5 V, VSS = 0 V
Parameter
Symbols
Supply current,
IDD1
Note 1
run mode
Conditions
High speed
fCLK = 32 MHz
fHOCO = 32 MHz
MAIN RUN
fHOCO = 4 MHz with PLL
Note 2, 3, 4, 5
fX = 4 MHz with PLL
Typ.
Max.
Unit
5.7
24
mA
4.7
20
mA
fX = 8 MHz with PLL
fCLK = 24 MHz
fHOCO = 24 MHz
fHOCO = 4 MHz with PLL
fX = 4 MHz with PLL
fX = 8 MHz with PLL
fCLK = 20 MHz
fX = 20 MHz
4.3
17.5
mA
fCLK = 8 MHz
fHOCO = 8 MHz
2.4
12
mA
1.8
9.5
mA
7
360
A
fX = 8 MHz
fCLK = 4 MHz
fHOCO = 4 MHz
fX = 4 MHz
SUB RUN
fCLK = fXT = 32.768 kHz
Note 2, 3, 6
Notes 1.
2.
3.
4.
5.
6.
The common condition for IDD1:
- IDD includes the total current flowing into whole power pins, including the input leakage current
flowing when the level of the input pin is fixed to VDD or VSS.
- The program is running in the code flash.
The typical value is that when Ta=+25deg.C and VDD=5.0 V. Peripheral devices and the data
flash are stopped.
The maximum value is that when all peripheral devices are operating. But the A/D converter,
RTC, LCD circuit and stepper motor circuit are stopped, and the data flash and the code flash
are stated to read mode. The 16-bit wakeup timer operates with fLOCO.
Either fX or fHOCO which is selected for fCLK is operated. The other is stopped.
At 128-pin products, the value of IDD1 does not include the LCDB (P11x, P46-7) pin toggle
current.
IDD1 condition of LCDB macro is Fclk=32MHz, mod8 mode, data rate=8MHz, 4cycle, 16bit
write/read.
fX and fHOCO are stopped.
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CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
TA = -40 to +85 C, 2.7 V VDD 5.5 V, VSS = 0 V
Parameter
Supply current,
Symbols
IDD2
Note 1
halt mode
Conditions
High speed
fCLK = 32 MHz
fHOCO = 32 MHz
MAIN HALT
2.7 VVDD
fHOCO = 4 MHz with PLL
Note 3, 4, 5
Typ.
Max.
Unit
1.0
8.9
mA
0.8
7.5
mA
fX = 4 MHz with PLL
fX = 8 MHz with PLL
fCLK = 24 MHz
fHOCO = 24 MHz
fHOCO = 4 MHz with PLL
fX = 4 MHz with PLL
fX = 8 MHz with PLL
fCLK = 20 MHz
fX = 20 MHz
0.7
6.5
mA
fCLK = 8 MHz
fHOCO = 8 MHz
0.4
4.5
mA
0.35
3.8
mA
1.0
140
A
70
A
fX = 8 MHz
fCLK = 4 MHz
fHOCO = 4 MHz
fX = 4 MHz
SUB HALT
fCLK = fXT
Note 3, 4, 6
= 32.768 kHz
RTC is stopped
RTC is operated by fXT
1.2
= 32.768KHz
Supply current,
IDD3 Note 2
stop mode
STOP Note 3, 4
RTC and fXT are stopped
0.4
RTC is operated by fXT = 32.768KHz
0.8
The common condition for IDD2:
- IDD includes the total current flowing into whole power pins, including the input leakage current
flowing when the level of the input pin is fixed to VDD or VSS.
- The HALT instruction is executed by the program in the code flash.
- The specification shows the stable current during HALT mode.
2. The common condition for IDD3:
- IDD includes the total current flowing into whole power pins, including the input leakage current
flowing when the level of the input pin is fixed to VDD or VSS.
- The STOP instruction is executed by the program in the code flash during MAIN RUN
operation.
- The spec shows the stable current during STOP mode.
3. The typical value is that when Ta=+25deg.C and VDD=5.0 V. Peripheral devices and the data
flash are stopped.
4. The maximum value is that when all peripheral devices are operating. But the A/D converter,
LCD circuit, stepper motor circuit, the data flash and the code flash are stopped. The 16-bit
wakeup timer operates with fLOCO.
5. Either fX or fHOCO which is selected for fCLK is operated. The other is stopped.
6. fX and fHOCO are stopped.
Notes 1.
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TA = -40 to +85 C, 2.7 V VDD 5.5 V, VSS = 0 V
Parameter
WDT operating
current
IWDT
IADC
Note 2
LCD operating
Current
ILCD
Note 3
ZPD operating
current
Conditions
Typ.
Max.
Unit
0.25
1.0
A
Note 1
ADC operating
current
Symbols
IZPD
Normal mode
VDD = 5.0 V
1.3
1.7
mA
Low voltage mode
VDD = 3.0 V
0.5
0.7
mA
fLCD = fSUB,
VDD = 5.0 V
100
140
A
LCD clock = 512 Hz
VDD = 3.0 V
90
130
A
One ZPD operated
VDD = 5.0 V
150
600
A
VDD = 3.0 V
100
500
A
VDD = 5.0 V
500
2000
A
VDD = 3.0 V
400
1600
A
Note 4
Four ZPDs operated
Notes
1. Current flowing only to the watchdog timer. The maximum specification of IDD1, IDD2 and IDD3 include IWDT.
2. Current flowing only to the A/D converter.The current value of the RL78/D1A is the sum of IDD and IADC
when the A/D converter operates.
3. Current flowing only to the LCD controller/driver circuit. The current value of the RL78/D1A is the sum of IDD
and ILCD when the LCD controller/driver circuit operates.
4. Current flowing only to the ZPD circuit. The current value of the RL78/D1A is the sum of IDD and IZPD when
the ZPD circuit operates.
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CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
33.3 Oscillator characteristics
33.3.1 Main(X1) oscillator characteristics
TA = -40 to +85 C, 2.7 V VDD 5.5 V, VSS = 0 V
Parameter
Main(X1) clock
Symbols
Conditions
fX
oscillation frequency
Min.
Typ.
Max.
Unit
Ceramic resonator
1.0
20.0
MHz
Crystal resonator
1.0
20.0
MHz
Remark Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
33.3.2 High speed on chip oscillator characteristics
TA = -40 to +85 C, 2.7 V VDD 5.5 V, VSS = 0 V
Parameter
HOCO
Symbols
Conditions
fHOCO
4 MHz mode
oscillation frequency
Min.
Typ.
Max.
Unit
3.92
4.00
4.08
MHz
8 MHz mode
7.84
8.00
8.16
MHz
16 MHz mode
15.68
16.00
16.32
MHz
24 MHz mode
23.52
24.00
24.48
MHz
32 MHz mode
31.36
32.00
32.64
MHz
Remark Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
33.3.3 Low speed on chip oscillator characteristics
TA = -40 to +85 C, 2.7 V VDD 5.5 V, VSS = 0 V
Parameter
LOCO
Symbols
Conditions
fLOCO
Min.
Typ.
Max.
Unit
12.75
15.0
17.25
kHz
oscillation frequency
33.3.4 Sub(XT1) oscillator characteristics
TA = -40 to +85 C, 2.7 V VDD 5.5 V, VSS = 0 V
Parameter
Sub(XT1) clock
Symbols
fXT
Conditions
Min.
Typ.
Max.
Unit
Possible to oscillate
29.0
32.768
35.0
kHz
oscillation frequency
Remark Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
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CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
33.4 DC characteristics
33.4.1 Pin group 1
TA = -40 to +85 C, 4.0 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V (1/2)
Parameter
Symbols
Note 1
Output current, high
Conditions
-5.0
mA
Per pin, P73 or P135 (SG port)
-13.0
mA
IOHTOTAL
Total
(for duty factors
≤ 70%Note 2)
Group 1L
-40.0
mA
Group 1R
-40.0
mA
Group 1C (128-pin,
100-pin)
-30.0
mA
for 128-pin, 100-pin
-110.0
mA
for 80-pin, 64-pin, 48-pin
-60.0
mA
IOL1
Per pin
8.5
mA
IOL2
Per pin, P73 or P135 (SG ports)
13.0
mA
IOLTOTAL
Total
(for duty factors
≤ 70%Note 3)
Group 1L
40.0
mA
Group 1R
35.0
mA
Group 1C (128-pin,
100-pin)
40.0
mA
for 128-pin, 100-pin
115.0
mA
for 80-pin, 64-pin, 48-pin
60.0
mA
2.
Unit
Per pin
Notes 1.
Max.
IOH1
Typ.
IOH2
Output current, low
Min.
When P60 or P61 is set to Nch open drain mode, it does not drive high level output.
These output current values are obtained under the condition that the duty factor is no greater than 70%.
The output current values when the duty factor is changed to a value greater than 70% can be calculated
from the following expression (when the duty factor is changed to n%).
Total output current of pins (IOH 0.7)/(n 0.01)
Where n = 80% and IOH = -30.0 mA
Total output current of pins = (-30.0 0.7)/(80 0.01) ≈ -26.2 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
3.
These output current values are obtained under the condition that the duty factor is no greater than 70%.
The output current values when the duty factor is changed to a value greater than 70% can be calculated
from the following expression (when the duty factor is changed to n%).
Total output current of pins (IOL 0.7)/(n 0.01)
Where n = 80% and IOL = 40.0 mA
Total output current of pins = (40.0 0.7)/(80 0.01) = 35.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Caution Different voltage between EVDD and VDD is allowed only when LCDM register is initial value.
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CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
TA = -40 to +85 C, 4.0 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V (2/2)
Parameter
Input voltage, high
Symbols
Note 2
Input voltage, lowNote 2
Input hysteresis width
Schmitt3 mode
Min.
Typ.
0.8EVDD
Note 3
Max.
Unit
EVDD
V
VIH2
Schmitt1 mode
0.65EVDD
EVDD
V
VIL1
Schmitt3 mode
0
0.5EVDD
V
VIL2
Schmitt1 mode Note 3
0
0.35EVDD
V
VIHYS1
Schmitt3 mode
0.29
V
0.1
0.19
0.15
0.59
Note 2, 4
VIHYS2
Schmitt1 mode
0.84
V
Output voltage, high Note 1
VOH1
IOH = -5.0 mA
EVDD-1.0
EVDD
V
IOH = -3.0 mA up to 6 pins
EVDD-0.5
EVDD
V
VOH2
IOH = -13.0 mA, P73 or P135 (SG port)
EVDD-0.7
EVDD
V
VOL1
IOL = 8.5 mA
0
0.7
V
IOL = 3.0 mA up to 6 pins
0
0.5
V
0
Output voltage, low
VIH1
Conditions
Note 3
VOL2
IOL = 13.0 mA, P73 or P135 (SG port)
0.7
V
Input leakage current,
high
ILIH1
VI = EVDD
1
A
Input leakage current,
low
ILIL1
VI = EVSS
-1
A
On chip pull-up
resistance Note 5
RU
VI = EVSS
10
100
k
On chip pull-down
resistance Note 6
RD
VI = EVDD
100
Notes 1.
2.
3.
4.
5.
6.
20
k
When P60 or P61 is set to Nch open drain mode, it does not drive high level output.
Except P130 because it is output only port.
P01, P10, P11, P17, P31, P40, P50 to P52, P55 to P57, P61, P63, P70, P110 to P117, P135 only.
This value is defined by evaluation result.
Except P130 and P137. Pull-up resistance is connected by software when pin is set to input mode.
LCD segment shared pins only. Pull-down resistance is connected during reset.
Caution Different voltage between EVDD and VDD is allowed only when LCDM register is initial value.
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CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
TA = -40 to +85 C, 2.7 V EVDD0 = EVDD1 4.0 V, EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS = 0 V (1/2)
Parameter
Symbols
Note 1
Output current, high
IOH1
IOH2
IOHTOTAL
Conditions
-1.0
-7.5
mA
mA
-15.0
mA
-30.0
mA
-7.0
mA
for 128-pin, 100-pin
-52.0
mA
for 80-pin, 64-pin, 48-pin
-33.0
mA
1.5
mA
IOL2
Per pin, P73 or P135 (SG ports)
7.0
mA
IOLTOTAL
Total
(for duty factors
Note 3
)
≤ 70%
Group 1L
18.0
mA
Group 1R
30.0
mA
Group 1C (128-pin,
100-pin)
10.0
mA
for 128-pin, 100-pin
58.0
mA
for 80-pin, 64-pin, 48-pin
35.0
mA
2.
Unit
Per pin
Max.
IOL1
Notes 1.
Typ.
Per pin
Per pin, P73 or P135 (SG port)
Total
Group 1L
(for duty factors
Group 1R
Note 2
)
≤ 70%
Group 1C (128-pin,
100-pin)
Output current, low
Min.
When P60 or P61 is set to Nch open drain mode, it does not drive high level output.
These output current values are obtained under the condition that the duty factor is no greater than 70%.
The output current values when the duty factor is changed to a value greater than 70% can be calculated
from the following expression (when the duty factor is changed to n%).
Total output current of pins (IOH 0.7)/(n 0.01)
Where n = 80% and IOH = -7.0 mA
Total output current of pins = (-7.0 0.7)/(80 0.01) ≈ -6.1 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
3.
These output current values are obtained under the condition that the duty factor is no greater than 70%.
The output current values when the duty factor is changed to a value greater than 70% can be calculated
from the following expression (when the duty factor is changed to n%).
Total output current of pins (IOL 0.7)/(n 0.01)
Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 0.7)/(80 0.01) ≈ 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Caution Different voltage between EVDD and VDD is allowed only when LCDM register is initial value.
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CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
TA = -40 to +85 C, 2.7 V EVDD0 = EVDD1 4.0 V, EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS = 0 V (2/2)
Parameter
Symbols
Input voltage, high
Input voltage, low
Note 2
Note 2
Conditions
Min.
Typ.
Max.
Unit
VIH1
Schmitt3 mode
0.8EVDD
EVDD
V
VIH2
Schmitt1 modeNote 3
VIL1
Schmitt3 mode
0.7EVDD
0
EVDD
0.4EVDD
V
V
VIL2
Schmitt1 modeNote 3
VIHYS1
Schmitt3 mode
VIHYS2
Schmitt1 mode Note 3
VOH1
0
0.3EVDD
V
0.05
0.21
V
IOH = -1.0 mA
0.08
EVDD-0.5
0.53
EVDD
V
V
VOH2
IOH = -7.5 mA, P73 or P135 (SG port)
EVDD-0.7
EVDD
V
VOL1
IOL = 1.5 mA
0
0.5
V
VOL2
IOL= 7.0 mA, P73 or P135 (SG port)
0
0.7
V
Input leakage current,
high
ILIH1
VI = EVDD
1
A
Input leakage current,
low
ILIL1
VI = EVSS
-1
A
On chip pull-up
resistance Note 5
RU
VI = EVSS
10
100
k
On chip pull-down
resistance Note 6
RD
VI = EVDD
100
Input hysterisis width
Note 2, 4
Output voltage, high
Note 1
Output voltage, low
Notes 1.
20
k
When P60 or P61 is set to Nch open drain mode, it does not drive high level output.
2.
Except P130 because it is output only port.
3.
P01, P10, P11, P17, P31, P40, P50 to P52, P55 to P57, P61, P63, P70, P110 to P117, P135 only.
4.
This value is defined by evaluation result.
5.
Except P130 and P137. Pull-up resistance is connected by software when pin is set to input mode.
6.
LCD segment shared pins only. Pull-down resistance is connected during reset.
Caution Different voltage between EVDD and VDD is allowed only when LCDM register is initial value.
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CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
33.4.2 Pin group 2 (ANI pins)
TA = -40 to +85 C, 4.0 V VDD 5.5 V, VSS = 0 V
Parameter
Output current, high
Output current, low
Input voltage, high
Symbols
Conditions
Typ.
Max.
Unit
IOH1
Per pin
-0.1
mA
IOHTOTAL
Total
-0.8
mA
IOL1
Per pin
0.4
mA
IOLTOTAL
Total
3.2
mA
VDD
V
VIH1
0.8VDD
Input voltage, low
VIL1
Input hysteresis width Note
VIHYS1
Output voltage, high
VOH1
IOH = -0.1 mA
Output voltage, low
VOL1
IOL = 0.4 mA
ILIH1
ILIL1
Input leakage current,
Min.
0
0.5VDD
V
0.29
V
VDD-0.5
VDD
V
0
0.4
V
VI = VDD
1
A
VI = VSS
-1
A
0.1
0.19
high
Input leakage current,
low
Note
This specification is guaranteed by design. It is not tested when shipment.
TA = -40 to +85 C, 2.7 V VDD 4.0 V, VSS = 0 V
Parameter
Output current, high
Output current, low
Symbols
Conditions
Min.
Typ.
Max.
Unit
IOH1
Per pin
-0.1
mA
IOHTOTAL
Total
-0.8
mA
IOL1
Per pin
0.4
mA
IOLTOTAL
Total
3.2
mA
Input voltage, high
VIH1
0.8VDD
VDD
V
Input voltage, low
VIL1
0
0.4VDD
V
Input hysteresis width Note
VIHYS1
0.05
0.21
V
Output voltage, high
VOH1
IOH = -0.1 mA
VDD-0.5
VDD
V
Output voltage, low
VOL1
IOL = 0.4 mA
0
0.4
V
Input leakage current,
high
ILIH1
VI = VDD
1
A
Input leakage current,
ILIL1
VI = VSS
-1
A
low
Note
This specification is guaranteed by design. It is not tested when shipment.
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CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
33.4.3 Pin group 3 (SMC pins)
TA = -40 to +85 C, 4.0 V VDD = SMVDD0 = SMVDD1 5.5 V, VSS = SMVSS0 = SMVSS1 = 0 V (1/3)
Parameter
Output current, high
Symbols
IOH1
IOHTOTAL
Conditions
Per pin
Max.
Unit
TA = -40 C
-52
mA
TA = +25 C
-39
mA
TA = +85 C
-32
mA
-118
mA
(for duty factors
TA = +25 C
-118
mA
≤ 70%Note)
TA = +85 C
-96
mA
TA = -40 C
-118
mA
TA = +25 C
-118
mA
Group 3A
TA = +85 C
-96
mA
Group 128-pin,
TA = -40 C
-118
mA
3C
100-pin
TA = +25 C
-118
mA
80-pin
TA = +85 C
-96
mA
64-pin
TA = -40 C
-118
mA
48-pin
TA = +25 C
-118
mA
TA = +85 C
-96
mA
TA = -40 C
-118
mA
(128-pin, 100-pin, TA = +25 C
80-pin)
TA = +85 C
-118
mA
-96
mA
Group 3E
TA = -40 C
-148
mA
(64-pin, 48-pin)
TA = +25 C
-118
mA
TA = +85 C
-96
mA
Group 3D
Typ.
TA = -40 C
Total
Group 3B
Min.
Note These output current values are obtained under the condition that the duty factor is no greater than 70%.
The output current values when the duty factor is changed to a value greater than 70% can be calculated from
the following expression (when the duty factor is changed to n%).
Total output current of pins (IOH 0.7)/(n 0.01)
Where n = 80% and IOH = -118.0 mA
Total output current of pins = (-118.0 0.7)/(80 0.01) ≈ -103.2 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current
higher than the absolute maximum rating must not flow into one pin.
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CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
TA = -40 to +85 C, 4.0 V VDD = SMVDD0 = SMVDD1 5.5 V, VSS = SMVSS0 = SMVSS1 = 0 V (2/3)
Parameter
Output current, low
Symbols
IOL1
IOLTOTAL
Conditions
TA = -40 C
Per pin
Note
Max.
Unit
52
mA
TA = +25 C
39
mA
TA = +85 C
32
mA
mA
TA = -40 C
118
TA = +25 C
118
mA
≤ 70%Note)
TA = +85 C
96
mA
Group 3A
TA = -40 C
118
mA
TA = +25 C
118
mA
TA = +85 C
96
mA
Group
128-pin,
TA = -40 C
118
mA
3C
100-pin
TA = +25 C
118
mA
80-pin
TA = +85 C
96
mA
64-pin
TA = -40 C
118
mA
48-pin
TA = +25 C
118
mA
TA = +85 C
96
mA
TA = -40 C
118
mA
(128-pin, 100-pin, TA = +25 C
80-pin)
TA = +85 C
118
mA
96
mA
Group 3E
TA = -40 C
148
mA
(64-pin, 48-pin)
TA = +25 C
118
mA
TA = +85 C
96
mA
Group 3D
Typ.
(for duty factors
Total
Group 3B
Min.
These output current values are obtained under the condition that the duty factor is no greater than 70%.
The output current values when the duty factor is changed to a value greater than 70% can be calculated from
the following expression (when the duty factor is changed to n%).
Total output current of pins (IOL 0.7)/(n 0.01)
Where n = 80% and IOL = 118.0 mA
Total output current of pins = (118.0 0.7)/(80 0.01) ≈ 103.2 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current
higher than the absolute maximum rating must not flow into one pin.
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CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
TA = -40 to +85 C, 4.0 V VDD = SMVDD0 = SMVDD1 5.5 V, VSS = SMVSS0 = SMVSS1 = 0 V (3/3)
Parameter
Input voltage, high
Symbols
Conditions
VIH1
Input voltage, low
VIL1
Input hysteresis width
VIHYS1
Min.
Typ.
0.8SMVDD
0
Max.
Unit
SMVDD
V
0.5SMVDD
V
0.29
V
SMVDD
V
0
0.5
V
0
50
mV
0.1
0.19
Note 1
Output voltage, high
Output voltage, low
Output voltage
VOH1
VOL1
TA = -40 C
IOH = -52 mA
SMVDD
TA = +25 C
IOH = -39 mA
- 0.5
TA = +85 C
IOH = -32 mA
TA = -40 C
IOL = 52 mA
TA = +25 C
IOL = 39 mA
TA = +85 C
IOL = 32 mA
VDEV
deviationNote 2
ILIH1
VI = SMVDD
1
A
Input leakage current,
low
ILIL1
VI = SMVSS
-1
A
On chip pull-up
RU
VI = SMVSS
10
100
k
RD
VI = SMVDD
100
Input leakage current,
high
20
resistance Note 3
On chip pull-down
k
resistance Note 4
Notes 1.
2.
This specification is guaranteed by design. It is not tested when shipment.
Output voltage deviation defines the difference of the outputs levels of the same stepper motor.
VDEV = max (|VOHx-VOHy|, |VOLx-VOLy|) @IOHx = IOHy, IOLx = IOLy.
X and y denote any combination of two pins of the following pin groups: (P80-P83, P84-P87, P90-P93,
P94-P97)
3.
Pull-up resistance is connected by software when pin is set to input mode.
4.
LCD segment shared pins only. Pull-down resistance is connected during reset.
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CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
TA = -40 to +85 C, 2.7 V VDD = SMVDD0 = SMVDD1 4.0 V, VSS = SMVSS0 = SMVSS1 = 0 V (1/3)
Parameter
Output current, high
Symbols
IOH1
IOHTOTAL
Conditions
Per pin
Max.
Unit
TA = -40 C
-30
mA
TA = +25 C
-25
mA
TA = +85 C
-23
mA
TA = -40 C
-90
mA
TA = +25 C
-75
mA
≤ 70%Note)
TA = +85 C
-69
mA
TA = -40 C
-90
mA
TA = +25 C
-75
mA
TA = +85 C
-69
mA
Group 3A
Group
128-pin,
TA = -40 C
-90
mA
3C
100-pin
TA = +25 C
-75
mA
80-pin
TA = +85 C
-69
mA
64-pin
TA = -40 C
-90
mA
48-pin
TA = +25 C
-75
mA
TA = +85 C
-69
mA
TA = -40 C
-90
mA
(128-pin, 100-pin, TA = +25 C
80-pin)
TA = +85 C
-75
mA
-69
mA
Group 3E
TA = -40 C
-90
mA
(64-pin, 48-pin)
TA = +25 C
-75
mA
TA = +85 C
-69
mA
Group 3D
Typ.
(for duty factors
Total
Group 3B
Min.
Note These output current values are obtained under the condition that the duty factor is no greater than 70%.
The output current values when the duty factor is changed to a value greater than 70% can be calculated from
the following expression (when the duty factor is changed to n%).
Total output current of pins (IOH 0.7)/(n 0.01)
Where n = 80% and IOH = -75.0 mA
Total output current of pins = (-75.0 0.7)/(80 0.01) ≈ -65.6 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current
higher than the absolute maximum rating must not flow into one pin.
R01UH0317EJ0110 Rev. 1.10
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CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
TA = -40 to +85 C, 2.7 V VDD = SMVDD0 = SMVDD1 4.0 V, VSS = SMVSS0 = SMVSS1 = 0 V (2/3)
Parameter
Output current, low
Symbols
IOL1
IOLTOTAL
Conditions
Per pin
Note
Max.
Unit
TA = -40 C
30
mA
TA = +25 C
23
mA
TA = +85 C
20
mA
TA = -40 C
90
mA
TA = +25 C
69
mA
≤ 70%Note)
TA = +85 C
60
mA
Group 3A
TA = -40 C
90
mA
TA = +25 C
69
mA
TA = +85 C
60
mA
Group
128-pin,
TA = -40 C
90
mA
3C
100-pin
TA = +25 C
69
mA
80-pin
TA = +85 C
60
mA
64-pin
TA = -40 C
90
mA
48-pin
TA = +25 C
69
mA
TA = +85 C
60
mA
TA = -40 C
90
mA
(128-pin, 100-pin, TA = +25 C
80-pin)
TA = +85 C
69
mA
60
mA
Group 3E
TA = -40 C
90
mA
(64-pin, 48-pin)
TA = +25 C
69
mA
TA = +85 C
60
mA
Group 3D
Typ.
(for duty factors
Total
Group 3B
Min.
These output current values are obtained under the condition that the duty factor is no greater than 70%.
The output current values when the duty factor is changed to a value greater than 70% can be calculated from
the following expression (when the duty factor is changed to n%).
Total output current of pins (IOL 0.7)/(n 0.01)
Where n = 80% and IOL = 69.0 mA
Total output current of pins = (69.0 0.7)/(80 0.01) ≈ 60.3 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current
higher than the absolute maximum rating must not flow into one pin.
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CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
TA = -40 to +85 C, 2.7 V VDD = SMVDD0 = SMVDD1 4.0 V, VSS = SMVSS0 = SMVSS1 = 0 V (3/3)
Parameter
Symbols
Input voltage, high
VIH1
Input voltage, low
VIL1
Input hysteresis width
VIHYS1
Conditions
Min.
Typ.
Max.
Unit
0.8SMVDD
SMVDD
V
0
0.4SMVDD
V
0.05
0.21
V
IOH = -30 mA
SMVDD
SMVDD
V
TA = +25 C
IOH = -25 mA
- 0.5
TA = +85 C
IOH = -23 mA
TA = -40 C
IOL = 30 mA
0
0.5
V
TA = +25 C
IOL = 23 mA
TA = +85 C
IOL = 20 mA
0
50
mV
Note 1
Output voltage, high
Output voltage, low
Output voltage deviation
VOH1
VOL1
TA = -40 C
VDEV
Note 2
Input leakage current,
ILIH1
VI = SMVDD
1
A
ILIL1
VI = SMVSS
-1
A
RU
VI = SMVSS
10
100
k
RD
VI = SMVDD
100
high
Input leakage current,
low
On chip pull-up
20
resistance Note 3
On chip pull-down
resistance
k
Note 4
Notes 1.
2.
This speccification is guaranteed by design. It is not tested when shipment.
Output voltage deviation defines the difference of the outputs levels of the same stepper motor.
VDEV = max (|VOHx-VOHy|, |VOLx-VOLy|) @IOHx = IOHy, IOLx = IOLy.
X and y denote any combination of two pins of the following pin groups: (P80-P83, P84-P87, P90-P93,
P94-P97)
3.
Pull-up resistance is connected by software when pin is set to input mode.
4.
LCD segment shared pins only. Pull-down resistance is connected during reset.
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CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
33.4.4 Pin group 4 (OSC, reset and P137 pins)
TA = -40 to +85 C, 4.0 V VDD 5.5 V, VSS = 0 V
Parameter
Input voltage, high
Symbols
Max.
Unit
0.8VDD
VDD
V
RESET
0.65VDD
VDD
V
VIH3
P137
0.8VDD
VDD
V
VIL1
P121, P122, P123, P124
0
0.2VDD
V
VIH1
Conditions
Min.
P121, P122, P123, P124
Typ.
(Port or EXCLK Note 1)
VIH2
Input voltage, low
____________
(Port or EXCLK Note 1)
Input hysteresis width
____________
VIL2
RESET
0
0.35VDD
V
VIL3
P137
0
0.5VDD
V
VIHYS1
Note 2
P121, P122, P123, P124
(Port or EXCLK
Input leakage current,
Note 1
____________
VIHYS2
RESET
ILIH1
P121, P122, P123, P124
high
0.1
0.7
0.15
0.59
VI = VDD
Port
EXCLK
Note 1
OSC
ILIH2
Input leakage current,
2.
____________
RESET, VI = VDD
0.84
V
1
A
1
A
10
A
1
A
ILIH3
P137, VI = VDD
1
A
ILIL1
P121, P122, P123, P124
Port
-1
A
VI = VSS
EXCLK Note 1
-1
A
OSC
-10
A
A
A
low
Notes 1.
V
)
____________
ILIL2
RESET, VI = VSS
-1
ILIL3
P137, VI = VSS
-1
P122(EXCLK) only.
This speccification is guaranteed by design. It is not tested when shipment.
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CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
TA = -40 to +85 C, 2.7 V VDD 4.0 V, VSS = 0 V
Parameter
Input voltage, high
Symbols
VIH1
Conditions
P121,P122,P123,P124
(Port or EXCLK
Input voltage, low
0.8VDD
VDD
V
)
____________
VDD
V
VIH3
P137
0.8VDD
VDD
V
0
0.2VDD
V
0
0.3VDD
V
0
0.4VDD
V
VIL1
P121, P122, P123, P124
Note 1
)
____________
RESET
VIL3
P137
VIHYS1
P121, P122, P123, P124
(Port or EXCLK
VIHYS2
ILIH1
high
ILIH2
ILIH3
Input leakage current,
Unit
0.7VDD
Note 2
Input leakage current,
Max.
RESET
VIL2
Note 1
Typ.
VIH2
(Port or EXCLK
Input hysteresis width
Min.
ILIL1
low
Note 1
0.08
V
0.08
V
)
_____________
RESET
P121, P122, P123, P124
Port
1
A
VI = VDD
EXCLK Note 1
1
A
OSC
10
A
RESET, VI = VDD
1
A
P137, VI = VDD
1
A
-1
A
____________
P121, P122, P123, P124
VI = VSS
Port
EXCLK
Note 1
OSC
Notes 1.
2.
____________
-1
A
-10
A
ILIL2
RESET, VI = VSS
-1
A
ILIL3
P137, VI = VSS
-1
A
P122(EXCLK) only.
This speccification is guaranteed by design. It is not tested when shipment.
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CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
33.5 AC characteristics
33.5.1 Basic operation
TA = -40 to +85 C,
2.7 V = EVDD0 = EVDD1 VDD = SMVDD0 = SMVDD1 5.5 V, VSS = EVSS0 = EVSS1 = SMVSS0 = SMVSS1 = 0 V
Parameter
Instruction cycle
Symbols
TCY
(minimum instruction
Conditions
Main system
High speed main run
Max.
Unit
1
s
0.03125
(Including PLL)
Sub system
SDIV = 0
s
1/fXT
clock operation
External main system
Typ.
Note 1
clock operation
execution time)
Min.
(Typ. 30.5)
fEX
Square wave input to EXCLK
2
20
MHz
External main system
tEXH
Square wave input to EXCLK
24
ns
clock (square wave)
tEXL
1/fMCK+10
ns
clock frequency
input
high/low level width
Timer input
tTIH
high/low level width
tTIL
Port output frequency
fGPO
TI00 to TI07, TI10 to TI17, TI20 to TI27
Note 2
C = 30 pF
4.0 V SMVDD
2
MHz
C = 30 pF
4.0 V VDD
2
MHz
P73,P135
C = 30 pF
4.0 V EVDD
8
MHz
Other than
C = 30 pF
4.0 V EVDD
16
MHz
8
MHz
P80 to P87,
P90 to P97
P20 to P27,
P150 to P152
the above
External interrupt
tINIH
input high/low level
tINIL
2.7 V EVDD < 4.0 V
INTP0 to INTP5, INTPLR0, INTPLR1
1
s
s
width Note 3
____________
RESET input
low level width
____________
tRSL
RESET
10
tWRJ
INTP0 to INTP5, INTPLR0, INTPLR1, ADTRG
30
tATH
Without noise filter
Note 3
Analog noise filter
50
1000
ns
rejection pulse width
Note 4
ADTRG input
high level width
AWC = 0
1/fCLK+10
ns
AWC = 1
10
1/fCLK+10
or tWRJ
ns
With noise filter
AWC = 0
AWC = 1
(Note 5)
tWRJ
ns
ns
(Note 5)
2.
Value is in case of fCLK is 32.0 MHz. It is also allowed to exceed frequency up to +3%.
fMCK shows the frequency value of operation clock for TAU. Usually, fMCK is defined by MHz but
this speccification is defined by ns. It is not defined by s, so please be careful.
Notes 1.
3.
Pulses longer than this value will pass the input filter.
4.
Pulses shorter than this value do not pass the input filters.
5.
If the value of “1/fCLK+10 [ns]” is less than tWRJ, please use tWRJ value instead of “1/fCLK +10 [ns]”.
Caution Different voltage between EVDD and VDD is allowed only when LCDM register is initial value.
R01UH0317EJ0110 Rev. 1.10
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CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
Figure 33-1. AC Timing Test Points
VIH/VOH
Test points
VIL/VOL
VIH/VOH
VIL/VOL
Figure 33-2. External Main System Clock Timing
1/fEX
tEXL
tEXH
VIH
VIL
EXCLK
Figure 33-3. TI Timing
tTIL
tTIH
TI01-TI07
TI10-TI17
TI20-TI27
Figure 33-4. Interrupt Request Input Timing
tINTL
tINTH
INTP0-INTP5
INTPLR0,1
____________
Figure 33-5. RESET Input Timing
tR SL
RESET
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CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
33.5.2 Stepper motor controller/driver
TA = -40 to +85 C,
2.7 V SMVDD0 = SMVDD1 = VDD 5.5 V, VSS = SMVSS0 = SMVSS1 = 0 V
Items
Symbols
Meter Controller/Driver
Conditions
MIN.
TYP.
fMCNote 1
MAX.
Unit
32
MHz
100
ns
500
ns
100
ns
500
ns
50
ns
input frequency
PWM output rise time
tR
10-90
Note 2
PWM output fall time
tF
10-90
Note 2
Peak Cross CurrentNote 3
ICROSS
Output Pulse WidthNote 4
tMO
Output Pulse
tSMDEV
Length Deviation
Note 5
HSPmn
Symmetry
Note 6
performance
HSPmn
Notes 1.
4.0 V SMVDD 5.5 V
15
2.7 V SMVDD 4.0 V
20
4.0 V SMVDD 5.5 V
15
2.7 V SMVDD 4.0 V
20
60
60
4.0 VSMVDD5.5 V
250
ns
2.7 VSMVDD5.5 V
5000
ns
4.0 VSMVDD5.5 V
-65
2.7 VSMVDD5.5 V
-100
IOH = -32 mA
HSPmn =
| VOH[(SMmn)max (SMmn)min] |
IOL = 32 mA
HSPmn =
| VOL[(SMmn)max (SMmn)min] |
+10
ns
+400
ns
2.7 V SMVDD 5.5 V
50
mV
4.0 V SMVDD 5.5 V
50
mV
2.7 V SMVDD 5.5 V
100
mV
-12
Source clock of the free-running counter.
2.
tR,tF is not tested in production, specified by design.
3.
The slew rate control generates a cross current in the output stage to control the energy of the external
inductive load. The cross current flows only during the output transition time tR, tF. It flows in addtion to the
output current. The cross current is not tested,but derived from simulation.
4.
The output buffer can not generate high or low pulses shorter than this time, because of its slew rate
control system. This value is not tested,but derived from simulation.
5.
The slew rate control function causes a deviation of output pulse time compared to the ideal selected
output pulse setting. This value is not tested,but derived from simulation.
6.
Indicates the dispersion of 16 PWM output voltages.( 4 buffers’ output voltage differences in the state of
IOH(IOL) at the same time.) Not tested in production, specified by design.
Remark m = 1 to 4, n = 1 to 4
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
1317
RL78/D1A
CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
33.5.3 Sound generator
TA = -40 to +85 C,
2.7 V EVDD0 = EVDD1 SMVDD0 = SMVDD1 = VDD 5.5 V, VSS = EVSS0 = EVSS1 = SMVSS0 = SMVSS1 = 0 V
Items
Sound generator input
frequency
SGO output rise time
SGO output fall time
Symbols
Conditions
MIN.
MAX.
Unit
32
MHz
P73, P135
200
ns
P93
500
P73, P135
200
P93
500
fSG
fR
C = 100 pF
fF
C = 100 pF
TYP.
ns
Caution Different voltage between EVDD and VDD is allowed only when LCDM register is initial value.
Sound Generator Output Timing
TR
TF
0.9EVDD/SMVDD
SGO
R01UH0317EJ0110 Rev. 1.10
Mar 23, 2015
0.1EVDD/SMVDD
1318
RL78/D1A
CHAPTER 33 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
33.5.4 Serial interface: CSI operation
TA = -40 to +85 C
2.7 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V
Items
Symbols
SCK cycle time
tKCY1
SCK high/low level width
SI set up time
Conditions
Min.
4.0VDD
125
VDD
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