R5F10NLGDFB#55

Datasheet R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 RL78/I1C RENESAS MCU True Low Power Platform, Independent power supply RTC, Hardware AES, 32-bit MAC, 1.9 V to 5.5 V operation, 64 to 256 Kbyte Flash, for Electric AMI Power Meter Application 1. OUTLINE 1.1 Features PLL clockNote 2 Target application ● 32 MHz is selectable (ΔΣ A/D converter is ● Power meters operable even when the PLL clock is selected as a CPU clock.) Ultra-low power consumption technology ● VDD = single power supply voltage of 1.7 to High-speed on-chip oscillator 5.5 VNote 1 ● HALT mode ● Select from 1 to 24 MHz (TYP.). However when it ● STOP mode is used as a clock for the ΔΣ A/D converter, select ● SNOOZE mode from 24 MHz (TYP.), 12 MHz (TYP.), 6 MHz (TYP.), or 3 MHz (TYP.). ● High accuracy: ±1.0% (VDD = 1.9 to 5.5 V, TA = – RL78 CPU core ● CISC architecture with 3-stage pipeline 20 to +85°C) ● Minimum instruction execution time: Can be changed from high speed (0.03125 µs: @ 32 MHz ● On-chip high-speed on-chip oscillator clock frequency correction function selection with PLL clock, 0.04167 µs: @ 24 MHz selection with high-speed on-chip oscillator) to ultra-low speed (66.6 µs: @ 15 kHz operation with low-speed on-chip oscillator) and 32-bit division are supported. Operating ambient temperature ● TA = -40 to +85°C ● Address space: 1 MB ● General-purpose registers: (8-bit register × 8) × 4 banks Power management and reset function ● On-chip power-on-reset (POR) circuit for Internal ● On-chip RAM: 6 KB to 16 KB VDDNote 3 power supply ● On-chip RTC power-on-reset (RTCPOR) circuit for Code flash memory VRTC power supply ● Code flash memory: 64 KB to 256 KB ● On-chip voltage detector (LVD) (Select interrupt ● Block size: 1 KB ● Prohibition of block erase and rewriting (security function) and reset from 13 levels) Voltage detective circuit ● On-chip debug function ● Self-programming (with boot swap function/flash shield window function) ● Detective voltage for VDD pin (Select interrupt from 6 levels) ● Detective voltage for VBAT pin (Select interrupt from 7 levels) Data flash memory ● Detective voltage for VRTC pin (Select interrupt ● Data flash memory: 2 KB ● Back ground operation (BGO): Instructions can be from ● Select from 4 MHz/2 MHz/1 MHz (However ΔΣ A/D converter is disabled.) ● 16-bit multiplication, 16-bit multiply-accumulation, executed Middle-speed on-chip oscillator the program memory rewriting the data flash memory while from 4 levels) ● Detective voltage for EXLVD pin (Select interrupt from 1 level) ● Number of rewrites: 1,000,000 times (TYP.) ● Voltage of rewrites: VDD = 1.9 to 5.5 V R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 1 of 89 RL78/I1C Data transfer controller (DTC) ● Transfer mode: Normal mode, repeat mode, block mode ● Activation source: Start by interrupt sources ● Chain transfer function Event link controller (ELC) ● Event signals of 22 types can be linked to the specified peripheral function. On-chip 32-bit multiplier and multiply-accumulator ● 32 bits × 32 bits = 64 bits (Unsigned or signed) ● 32 bits × 32 bits + 64 bits = 64 bits (Unsigned or signed) Serial interface ● CSI: 2 to 3 channels ● UART/UART (LIN-bus supported): 2 to 3 channels ● UART/IrDA: 1 channel ● Simplified I2C communication: 2 to 3 channels ● I2C communication: 1 channel 1. OUTLINE I/O port ● I/O port: 35 to 68 (N-ch open drain I/O [6 V tolerance]: 3, N-ch open drain I/O [VDD toleranceNote 5/EVDD toleranceNote 6]: 10 to 16) ● Can be set to N-ch open drain, TTL input buffer, and on-chip pull-up resistor ● Different potential interface: Can connect to a 1.8/2.5/3 V device ● On-chip clock output/buzzer output controller ● On-chip key interrupt function AES circuitNote 7 ● Cipher modes of operation: GCM/ECB/CBC ● Encryption key length: 128/192/256 bits Others ● On-chip BCD (binary-coded decimal) correction circuit ● On-chip battery backup function Notes 1. The minimum operating voltage of this product varies according to the VBATEN Timer ● 16-bit timer: 8 channels ● 12-bit interval timer: 1 channel setting value. When VBATEN = 0, the minimum ● 8-bit interval timer: 4 channels operating voltage is 1.7 V. ● Independent power supply RTC: 1 channel When VBATEN = 1, the minimum (calendar for 99 years, alarm function, and clock correction function) ● Watchdog timer: 1 channel ● Oscillation stop detection circuit: 1 channel LCD controller/driver ● Internal voltage boosting method, capacitor split method, and external resistance division method are switchable ● Segment signal output: 19 (15)Note 4 to 42 (38)Note 4 ● Common signal output: 4 (8)Note 4 A/D converter ● 24-Bit ΔΣ A/D converter: 3 or 4 channels ● 8/10-bit resolution A/D converter operating voltage is 1.9 V. As well, the minimum operating voltage of VRTC is 1.6 V. 2. R5F10NPJ, R5F10NMJ, R5F10NPG only. 3. Either VDD or VBAT is selected by the battery backup function. 4. The values in parentheses are the number of signal outputs when 8 com is used. 5. 64 pin products only 6. 80 pin, 100 pin products only 7. Only available in R5F10N products. Remark The functions mounted depend on the product. See 1.6 Outline of Functions. (VDD = 1.9 to 5.5 V): 4 or 6 channels ● Internal reference voltage (1.45 V) and temperature sensor R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 2 of 89 RL78/I1C 1. OUTLINE Օ ROM, RAM capacities Code Flash 256 KB Data Flash 2 KB 128 KB 2 KB 64 KB 2 KB RAM Note 1 16 KB Note 2 8 KB 6 KB AES Function RL78/I1C 64 pins 80 pins 100 pins Mounted - R5F10NMJ R5F10NPJ Mounted R5F10NLG R5F10NMG R5F10NPG Not mounted R5F11TLG - - Mounted R5F10NLE R5F10NME - Not mounted R5F11TLE - - Notes 1. This is about 15 KB when the self-programming function is used. (For details, refer to CHAPTER 3 in the RL78/I1C User's Manual.) 2. This is about 7 KB when the self-programming function is used (excluding in the case of the R5F10NPG). (For details, refer to CHAPTER 3 in the RL78/I1C User's Manual.) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 3 of 89 RL78/I1C 1. OUTLINE 1.2 List of Part Numbers Figure 1-1. Part Number, Memory Size, and Package of RL78/I1C Part No. R 5 F 1 0 N P J D x x x F B #30 Packaging specification #30 : Tray (LFQFP) Ver.1.0 #35 : Tray (LFQFP) Ver.1.1 #50 : Embossed Tape (LFQFP) Ver.1.0 #55 : Embossed Tape (LFQFP) Ver.1.1 Package type: FB : LFQFP, 0.50 mm pitch ROM number (Omitted with blank products) Fields of application: D : Industrial applications, TA = -40°C to +85°C ROM capacity: E : 64 KB G : 128 KB J : 256 KB Pin count: L : 64-pin M : 80-pin P : 100-pin RL78/I1C group 10N : On-chip AES circuit 11T : No on-chip AES circuit Memory type: F : Flash memory Renesas MCU Renesas semiconductor product Table 1-1. List of Ordering Part Numbers Pin Package Count Data AES Function 64 pins 64-pin plastic LFQFP Mounted Fields of Ordering Part Number ApplicationNote Flash Mounted D (10 × 10 mm, 0.5 mm R5F10NLEDFB#30, R5F10NLGDFB#30, R5F10NLEDFB#50, R5F10NLGDFB#50, pitch) R5F10NLEDFB#35, R5F10NLGDFB#35, R5F10NLEDFB#55, R5F10NLGDFB#55 Not mounted D R5F11TLEDFB#30, R5F11TLGDFB#30, R5F11TLEDFB#50, R5F11TLGDFB#50, R5F11TLEDFB#35, R5F11TLGDFB#35, R5F11TLEDFB#55, R5F11TLGDFB#55 80-pin plastic LFQFP 80 pins Mounted Mounted D (12 × 12 mm, 0.5 mm R5F10NMEDFB#30, R5F10NMGDFB#30, R5F10NMJDFB#30, R5F10NMEDFB#35, pitch) R5F10NMGDFB#35, R5F10NMJDFB#35, R5F10NMEDFB#50, R5F10NMGDFB#50, R5F10NMJDFB#50, R5F10NMEDFB#55, R5F10NMGDFB#55, R5F10NMJDFB#55 100 pins 100-pin plastic LFQFP (14 × 14 mm, 0.5 mm pitch) Mounted Mounted D R5F10NPJDFB#30, R5F10NPGDFB#30, R5F10NPJDFB#35, R5F10NPGDFB#35, R5F10NPJDFB#50, R5F10NPGDFB#50, R5F10NPJDFB#55, R5F10NPGDFB#55 Note For the fields of application, see Figure 1-1 Part Number, Memory Size, and Package of RL78/I1C. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 4 of 89 RL78/I1C 1. OUTLINE 1.3 Pin Configuration (Top View) 1.3.1 64-pin products COM0 COM1 COM2 COM3 COM4/SEG0 COM5/SEG1 COM6/SEG2 COM7/SEG3 P10/SEG4 P11/SEG5 P12/SEG6/SCK10/SCL10 P13/SEG7/SI10/RxD1/SDA10/INTP6 P14/SEG8/SO10/TxD1 P15/SEG9/(SCK00)/(SCL00) P16/SEG10/INTP7/(SI00)/(RxD0)/(SDA00) P17/SEG11/(SO00)/(TxD0) ● 64-pin plastic LFQFP (10 × 10 mm, 0.5 mm pitch) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ANIP3 ANIN3 ANIP2 ANIN2 AVRT AVCM AVSS AREGC ANIP1 ANIN1 ANIP0 ANIN0 P23/ANI3 P22/ANI2/EXLVD P21/AVREFM/ANI1 P20/AVREFP /ANI0 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 RL78/I1C (Top View) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P70/SEG16/KR0/(INTP0) P71/SEG17/KR1/(INTP1) P72/SEG18/KR2/TI01/TO01/(INTP2) P73/SEG19/KR3/(INTP3)/(PCLBUZ1) P74/SEG20/KR4/(INTP4)/(PCLBUZ0) P30/SEG24/RxD2/IrRxD/TI07/TO07/INTP5 P31/SEG25/TxD2/IrTxD/TI06/TO06 P125/VL3/INTP1/TI05/TO05/PCLBUZ1 VL4 VL2 VL1 P126/CAPL/(TI04)/(TO04) P127/CAPH/(TI03)/(TO03) P62/(TI02)/(TO02)/(RTCOUT) P61/SDAA0/(TI01)/(TO01) P60/SCLA0/(TI00)/(TO00) P07/SO00/TxD0/TI02/TO02/INTP2/TOOLTxD P06/SI00/RxD0/SDA00/TI03/TO03/INTP4/TOOLRxD P05/SCK00/SCL00/TI04/TO04/INTP3 P43/TI00/TO00/PCLBUZ0/RTCOUT P40/TOOL0 RESET P122/X2/EXCLK P121/X1 P137/INTP0 P124/XT2/EXCLKS P123/XT1 VRTC REGC VSS/EVSS0 VDD/EVDD0 VBAT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR0). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR0) in the RL78/I1C User's Manual. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 5 of 89 RL78/I1C 1. OUTLINE 1.3.2 80-pin products P07/SO00/TxD0/TI02/TO02/INTP2/TOOLTxD/SEG37 COM0 COM1 COM2 COM3 COM4/SEG0 COM5/SEG1 COM6/SEG2 COM7/SEG3 P10/SEG4 P11/SEG5 P12/SEG6 P13/SEG7 P14/SEG8 P15/SEG9/(SCK00)/(SCL00) P16/SEG10/(SI00)/(RxD0)/(SDA00) P17/SEG11/(SO00)/(TxD0) P80/SEG12/(SCK10)/(SCL10) P81/SEG13/(SI10)/(RxD1)/(SDA10) P82/SEG14/(SO10)/(TxD1) ● 80-pin plastic LFQFP (12 × 12 mm, 0.5 mm pitch) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P06/SI00/RxD0/SDA00/TI03/TO03/TOOLRxD/SEG36 P05/SCK00/SCL00/TI04/TO04/INTP3/SEG35 P04/SO10/TxD1/TI05/TO05/INTP4/SEG34 P03/SI10/RxD1/SDA10/TI06/TO06/SEG33 P02/SCK10/SCL10/TI07/TO07/INTP5/SEG32 ANIP2 ANIN2 AVRT AVCM AVSS AREGC ANIP1 ANIN1 ANIP0 ANIN0 P23/ANI3 P22/ANI2/EXLVD P21/AVREFM/ANI1 P20/AVREFP /ANI0 P56/TxD2/IrTxD 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 RL78/I1C (Top View) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P83/SEG15 P70/SEG16/KR0/(INTP0) P71/SEG17/KR1/(INTP1) P72/SEG18/KR2/(INTP2) P73/SEG19/KR3/(INTP3) P74/SEG20/KR4/(INTP4) P75/SEG21/KR5/(INTP5) P76/SEG22/KR6/(INTP6) P77/SEG23/KR7/(INTP7) P30/SEG24/(TI07)/(TO07) P31/SEG25/(TI06)/(TO06) P32/SEG26/(PCLBUZ1) P33/SEG27/(PCLBUZ0) P125/VL3/INTP1/(TI05)/(TO05) VL4 VL2 VL1 P126/CAPL/(TI04)/(TO04) P127/CAPH/(TI03)/(TO03) P62/(TI02)/(TO02)/(RTCOUT) P55/RxD2/IrRxD P41/INTP6/TI01/TO01/PCLBUZ1 P40/TOOL0 P152/RTCIC2 P151/RTCIC1 P150/RTCOUT/RTCIC0 RESET P122/X2/EXCLK P121/X1 P137/INTP0 P124/XT2/EXCLKS P123/XT1 VRTC REGC VSS/EVSS0 VDD EVDD0 VBAT P60/SCLA0/(TI00)/(TO00) P61/SDAA0/(TI01)/(TO01) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR0). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR0) in the RL78/I1C User's Manual. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 6 of 89 RL78/I1C 1. OUTLINE 1.3.3 100-pin products P56/SEG38/TxD2/IrTxD P57/SEG39/SCK30/SCL30 P84/SEG40/SI30/RxD3/SDA30 P85/SEG41/SO30/TxD3 COM0 COM1 COM2 COM3 COM4/SEG0 COM5/SEG1 COM6/SEG2 COM7/SEG3 EVDD1 P10/SEG4 P11/SEG5 P12/SEG6 P13/SEG7 P14/SEG8 P15/SEG9/(SCK00)/(SCL00) P16/SEG10/(SI00)/(RxD0)/(SDA00) P17/SEG11/(SO00)/(TxD0) EVSS1 P80/SEG12/(SCK10)/(SCL10) P81/SEG13/(SI10)/(RxD1)/(SDA10) P82/SEG14/(SO10)/(TxD1) ● 100-pin plastic LFQFP (14 × 14 mm, 0.5 mm pitch) 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 RL78/I1C (Top View) P83/SEG15 P70/SEG16/KR0/(INTP0) P71/SEG17/KR1/(INTP1) P72/SEG18/KR2/(INTP2) P73/SEG19/KR3/(INTP3) P74/SEG20/KR4/(INTP4) P75/SEG21/KR5/(INTP5) P76/SEG22/KR6/(INTP6) P77/SEG23/KR7/(INTP7) P30/SEG24/(TI07)/(TO07) P31/SEG25/(TI06)/(TO06) P32/SEG26/(PCLBUZ1) P33/SEG27/(PCLBUZ0) P34/SEG28 P35/SEG29 P36/SEG30 P37/SEG31 P125/VL3/INTP1/(TI05)/(TO05) VL4 VL2 VL1 P126/CAPL/(TI04)/(TO04) P127/CAPH/(TI03)/(TO03) P62/(TI02)/(TO02)/(RTCOUT) P61/SDAA0/(TI01)/(TO01) P06/SI00/RxD0/SDA00/TI03/TO03/TOOLRxD P05/SCK00/SCL00/TI04/TO04/INTP3 P04/SO10/TxD1/TI05/TO05/INTP4 P03/SI10/RxD1/SDA10/TI06/TO06 P02/SCK10/SCL10/TI07/TO07/INTP5 P43/TI00/TO00/PCLBUZ0 P42/INTP7 P41/TI01/TO01/PCLBUZ1/INTP6 P40/TOOL0 P152/RTCIC2 P151/RTCIC1 P150/RTCOUT/RTCIC0 RESET P122/X2/EXCLK P121/X1 P137/INTP0 P124/XT2/EXCLKS P123/XT1 VRTC REGC VSS/EVSS0 VDD EVDD0 VBAT P60/SCLA0/(TI00)/(TO00) P55/SEG37/RxD2/IrRxD P54/SEG36 P53/SEG35 P52/SEG34 P51/SEG33 P50/SEG32 ANIP3 ANIN3 ANIP2 ANIN2 AVRT AVCM AVSS AREGC ANIP1 ANIN1 ANIP0 ANIN0 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2/EXLVD P21/AVREFM /ANI1 P20/AVREFP /ANI0 P07/SO00/TxD0/TI02/TO02/INTP2/TOOLTxD Cautions 1. Make EVSS1 the same potential as VSS/EVSS0. 2. Make EVDD1 the same potential as EVDD0. 3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD and EVDD1 pins and connect the VSS and EVSS1 pins to separate ground lines. 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR0). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR0) in the RL78/I1C User's Manual. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 7 of 89 RL78/I1C 1. OUTLINE 1.4 Pin Identification ANI0 to ANI5: Analog Input ANIN0 to ANIN3, P137: Port 13 P150 to P152: Port 15 Analog Input for ΔΣ ADC PCLBUZ0, AREGC: Regulator Capacitance for ΔΣ ADC PCLBUZ1: AVCM: Control for ΔΣ ADC AVREFM: A/D Converter Reference Potential REGC: Regulator Capacitance (– side) Input RESET: Reset A/D Converter Reference Potential RTCOUT: ANIP0 to ANIP3: AVREFP: Programmable Clock Output/Buzzer Output Real-time Clock Correction Clock (1 Hz/64 Hz) Output (+ side) Input AVRT: Reference Potential for ΔΣ ADC RTCIC0 to RTCIC2: RTC Time Capture Event Input AVSS: Ground for ΔΣ ADC RxD0 to RxD3: CAPH, CAPL: Capacitor Connection SCL00, SCL10, for LCD Controller/Driver SCL30: Common Signal Output for LCD SDA00, SDA10, Controller/Driver SDA30: Serial Data Input/Output for Simplified IIC EVDD0, EVDD1: Power Supply for Port SCLA0 : Serial Clock Input/Output for IICA0 EVSS0, EVSS1: Ground for Port SDAA0: Serial Data Input/Output for IICA0 COM0 to COM7: EXCLK: EXCLKS: External Clock Input SCK00, SCK10, (Main System Clock) SCK30: External Clock Input SEG0 to SEG41: Receive Data for UART Serial Clock Output for Simplified IIC Serial Clock Input/Output for CSI Segment Signal Output for LCD Controller/Driver (Subsystem clock) External Input for Low Voltage SI00, SI10, SI30: Detector SO00, SO10, SO30: Serial Data Output for CSI INTP0 to INTP7: Interrupt Request From Peripheral TI00 to TI07: Timer Input IrRxD: Receive Data for IrDA TO00 to TO07: Timer Output IrTxD: Transmit Data for IrDA TOOL0: Data Input/Output for Tool KR0 to KR7: Key Return TOOLRxD, P02 to P07: Port 0 TOOLTxD: Data Input/Output for External Device P10 to P17: Port 1 TxD0 to TxD3: Transmit Data for UART P20 to P25: Port 2 VBAT: Battery Backup Power Supply P30 to P37: Port 3 VDD: Power Supply P40 to P43: Port 4 VL1 to VL4: Voltage for Driving LCD P50 to P57: Port 5 VRTC: RTC Power Supply P60 to P62: Port 6 VSS: Ground P70 to P77: Port 7 X1, X2: Crystal Oscillator (Main System EXLVD: P80 to P85: Port 8 P121 to P127: Port 12 R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Serial Data Input for CSI Clock) XT1, XT2: Crystal Oscillator (Subsystem Clock) Page 8 of 89 RL78/I1C 1. OUTLINE 1.5 Block Diagram 1.5.1 64-pin products TIMER ARRAY UNIT (8ch) TI00/TO00/P43 (TI00/TO00/P60) ch0 TI01/TO01/P72 (TI01/TO01/P61) ch1 TI02/TO02/P07 (TI02/TO02/P62) ch2 TI03/TO03/P06 (TI03/TO03/P127) ch3 TI04/TO04/P05 (TI04/TO04/P126) ch4 TI05/TO05/P125 ch5 TI06/TO06/P31 ch6 TI07/TO07/P30 RxD0/P06 (RxD0/P16) 2 10-BIT A/D CONVERTER (4ch) 5 KEY RETURN PORT 1 8 P10 to P17 PORT 2 4 P20 to P23 ANI2/P22, ANI3/P23 PORT 3 2 P30, P31 ANI0/AVREFP/P20 ANI1/AVREFM/P21 PORT 4 2 P40, P43 PORT 6 3 P60 to P62 PORT 7 5 P70 to P74 KR0 to KR4 ch7 AESNote ch01 LCD CONTROLLER/ DRIVER 8- BIT INTERVAL TIMER 1 ch10 RAM SPACE FOR LCD DATA 19 8 PORT 12 COM0 to COM7 VL1 to VL4 PORT 13 P137 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL 4 P121 to P124 3 P125 to P127 SDAA0/P61 SCLA0/P60 VOLTAGE REGULATOR UART0 SEG0 to SEG11, SEG16 to SEG20, SEG24, SEG25 CAPH CAPL SERIAL INTERFACE IICA0 SERIAL ARRAY UNIT0 (2ch) SDA10/P13 P05 to P07 ELC ch11 RxD1/P13 TxD1/P14 SCK00/P05(SCK00/P15) SI00/P06(SI00/P16) SO00/P07(SO00/P17) SCK10/P12 SI10/P13 SO10/P14 SCL00/P05(SCL00/P15) SDA00/P06(SDA00/P16) SCL10/P12 3 32-bit MULTIPLY ACCUMULATOR 8- BIT INTERVAL TIMER 0 ch00 RxD0/P06(RxD0/P16) TxD0/P07(TxD0/P17) PORT 0 REGC LINSEL RL78 CPU CORE UART1 CODE FLASH MEMORY, DATA FLASH MEMORY MUL & DIV RESET CONTROL TOOL0/P40 ON-CHIP DEBUG CSI00 SYSTEM CONTROL CSI10 RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED ON-CHIP OSCILLATOR MIDDLE-SPEED ON-CHIP OSCILLATOR (4 MHz) IIC00 RAM IIC10 SERIAL ARRAY UNIT1 (1ch) RxD2/IrRxD/P30 TxD2/IrTxD/P31 RxD0/P06 (RxD0/P16) INTP0/P137(INTP0/P70) VDD/EVDD0 UART2 VSS/EVSS0 VBAT IrDA 2 CLOCK OUTPUT CONTROL 24-bit ΔΣ A/D CONVERTER (4ch) ΔΣ ADC0 ANIN1 ANIP1 ΔΣ ADC1 ANIN2 ANIP2 ΔΣ ADC2 ANIN3 ANIP3 INTP1/P125 (INTP1/P71) INTERRUPT CONTROL BUZZER OUTPUT ANIN0 ANIP0 TOOLRxD/P06, TOOLTxD/P07 BCD ADJUSTMENT DATA TRANSFER CONTROLLER (DTC) ΔΣ ADC3 BATTERY BACKUP FUNCTION AVCM AREGC AVRT AVSS PCLBUZ0/P43 (PCLBUZ0/P74), PCLBUZ1/P125 (PCLBUZ1/P73) CRC SUB CLOCK FREQUENCY MEASUREMENT HIGH-SPEED ON-CHIP OSCILLATOR CLOCK FREQUENCY CORRECTION FUNCTION OSCILLATION STOP DETECTOR 4 INTP2/P07(INTP2/P72), INTP3/P05(INTP3/P73), INTP4/P06(INTP4/P74), INTP5/P30 2 INTP6/P13, INTP7/P16 WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR 12- BIT INTERVAL TIMER INDEPENDENT POWER SUPPLY RTC Power supply separation SUB CLOCK OSCILLATOR REAL-TIME CLOCK XT1/P123 XT2/EXCLKS/P124 RTCOUT/P43 (RTCOUT/P62) RTC POWER ON RESET VSS VRTC Note Only available in R5F10N products. Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR0). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR0) in the RL78/I1C User's Manual. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 9 of 89 RL78/I1C 1. OUTLINE 1.5.2 80-pin products TIMER ARRAY UNIT (8ch) (TI00/TO00/P60) ch0 TI01/TO01/P41 (TI01/TO01/P61) ch1 TI02/TO02/P07 (TI02/TO02/P62) ch2 TI03/TO03/P06 (TI03/TO03/P127) ch3 TI04/TO04/P05 (TI04/TO04/P126) ch4 TI05/TO05/P04 (TI05/TO05/P125) ch5 TI06/TO06/P03 (TI06/TO06/P31) TI07/TO07/P02 (TI07/TO07/P30) RxD0/P06 (RxD0/P16) 32-bit MULTIPLY ACCUMULATOR 2 10-BIT A/D CONVERTER (4ch) 8 KEY RETURN ch6 P02 to P07 PORT 1 8 P10 to P17 PORT 2 4 P20 to P23 ANI2/P22, ANI3/P23 PORT 3 4 P30 to P33 PORT 4 2 P40, P41 KR0 to KR7 PORT 5 2 P55, P56 PORT 6 3 P60 to P62 PORT 7 8 P70 to P77 PORT 8 4 P80 to P83 ch7 AES ch01 LCD CONTROLLER/ DRIVER 8- BIT INTERVAL TIMER 1 ch10 RAM SPACE FOR LCD DATA 34 8 SCLA0/P60 VOLTAGE REGULATOR UART0 PORT 12 COM0 to COM7 VL1 to VL4 SDAA0/P61 SERIAL INTERFACE IICA0 SERIAL ARRAY UNIT0 (2ch) SEG0 to SEG27, SEG32 to SEG37 CAPH CAPL ch11 RxD1/P03(RxD1/P81) TxD1/P04(TxD1/P82) SCK00/P05(SCK00/P15) SI00/P06(SI00/P16) SO00/P07(SO00/P17) SCK10/P02(SCK10/P80) SI10/P03(SI10/P81) SO10/P04(SO10/P82) SCL00/P05(SCL00/P15) SDA00/P06(SDA00/P16) SCL10/P02(SCL10/P80) SDA10/P03(SDA10/P81) 6 ANI0/AVREFP /P20 ANI1/AVREFM/P21 ELC 8- BIT INTERVAL TIMER 0 ch00 RxD0/P06(RxD0/P16) TxD0/P07(TxD0/P17) PORT 0 REGC 4 P121 to P124 3 P125 to P127 P137 PORT 13 PORT 15 3 POWER ON RESET/ VOLTAGE DETECTOR P150 to P152 POR/LVD CONTROL LINSEL RL78 CPU CORE UART1 CODE FLASH MEMORY, DATA FLASH MEMORY RESET CONTROL MUL & DIV CSI00 ON-CHIP DEBUG CSI10 SYSTEM CONTROL IIC00 HIGH-SPEED ON-CHIP OSCILLATOR RESET X1/P121 X2/EXCLK/P122 MIDDLE-SPEED ON-CHIP OSCILLATOR (4 MHz) RAM IIC10 TOOL0/P40 PLL CLOCK (32MHz) SERIAL ARRAY UNIT1 (1ch) RxD2/IrRxD/P55 TxD2/IrTxD/P56 VDD UART2 EVDD0 VSS/EVSS VBAT IrDA 2 CLOCK OUTPUT CONTROL 24-bit ΔΣ A/D CONVERTER (3ch) ΔΣ ADC0 ANIN1 ANIP1 ΔΣ ADC1 ANIN2 ANIP2 ΔΣ ADC2 INTP1/P125 (INTP1/P71) INTERRUPT CONTROL BUZZER OUTPUT ANIN0 ANIP0 RxD0/P06 (RxD0/P16) INTP0/P137(INTP0/P70) TOOLRxD/P06, TOOLTxD/P07 BCD ADJUSTMENT DATA TRANSFER CONTROLLER (DTC) BATTERY BACKUP FUNCTION AVCM AREGC AVRT (PCLBUZ0/P33), PCLBUZ1/P41 (PCLBUZ1/P32) CRC SUB CLOCK FREQUENCY MEASUREMENT HIGH-SPEED ON-CHIP OSCILLATOR CLOCK FREQUENCY CORRECTION FUNCTION OSCILLATION STOP DETECTOR AVSS INTP2/P07(INTP2/P72), INTP3/P05(INTP3/P73), INTP4/P04(INTP4/P74), INTP5/P02(INTP5/P75) 2 INTP6/P41(INTP6/P76), (INTP7/P77) WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR 12- BIT INTERVAL TIMER INDEPENDENT POWER SUPPLY RTC Power supply separation XT1/P123 SUB CLOCK OSCILLATOR REAL-TIME CLOCK XT2/EXCLKS/P124 3 RTCIC0-RTCIC2 RTCOUT/P150 (RTCOUT/P62) RTC POWER ON RESET VSS Remark 4 VRTC Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR0). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR0) in the RL78/I1C User's Manual. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 10 of 89 RL78/I1C 1. OUTLINE 1.5.3 100-pin products TIMER ARRAY UNIT (8ch) TI00/TO00/P43 (TI00/TO00/P60) ch0 TI01/TO01/P41 (TI01/TO01/P61) ch1 TI02/TO02/P07 (TI02/TO02/P62) ch2 TI03/TO03/P06 (TI03/TO03/P127) ch3 TI04/TO04/P05 (TI04/TO04/P126) ch4 TI05/TO05/P04 (TI05/TO05/P125) ch5 TI06/TO06/P03 (TI06/TO06/P31) TI07/TO07/P02 (TI07/TO07/P30) RxD0/P06 (RxD0/P16) 32-bit MULTIPLY ACCUMULATOR ch6 8 KR0 to KR7 ELC ch7 AES LCD CONTROLLER/ DRIVER ch01 8- BIT INTERVAL TIMER 1 ch10 SERIAL ARRAY UNIT0 (2ch) UART1 SCL10/P02(SCL10/P80) SDA10/P03(SDA10/P81) IIC10 8 COM0 to COM7 VL1 to VL4 RL78 CPU CORE CSI00 RxD3/P84 TxD3/P85 SCK30/P57 SI30/P84 SO30/P85 SCL30/P57 SDA30/P84 PORT 1 8 P10 to P17 PORT 2 6 P20 to P25 PORT 3 8 P30 to P37 PORT 4 4 P40 to P43 PORT 5 8 P50 to P57 PORT 6 3 P60 to P62 PORT 7 8 P70 to P77 PORT 8 6 P80 to P85 PORT 15 SDAA0/P61 SCLA0/P60 REGC CODE FLASH MEMORY, DATA FLASH MEMORY MUL & DIV P121 to P124 3 P125 to P127 P137 3 POWER ON RESET/ VOLTAGE DETECTOR P150-P152 POR/LVD CONTROL RESET CONTROL TOOL0/P40 ON-CHIP DEBUG IIC00 RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED ON-CHIP OSCILLATOR MIDDLE-SPEED ON-CHIP OSCILLATOR (4 MHz) RAM PLL CLOCK (32MHz) RxD0/P06 (RxD0/P16) INTP0/P137(INTP0/P70) UART2 IrDA VDD EVDD0 EVDD1 VSS/EVSS0 EVSS1 VBAT TOOLRxD/P06, TOOLTxD/P07 UART3 CSI30 BUZZER OUTPUT 2 CLOCK OUTPUT CONTROL IIC30 ANIN0 ANIP0 ΔΣ ADC0 ANIN1 ANIP1 ΔΣ ADC1 ANIN2 ANIP2 ΔΣ ADC2 INTP1/P125 (INTP1/P71) INTERRUPT CONTROL BCD ADJUSTMENT DATA TRANSFER CONTROLLER (DTC) BATTERY BACKUP FUNCTION ΔΣ ADC3 AVCM AREGC PCLBUZ0/P43 (PCLBUZ0/P33), PCLBUZ1/P41 (PCLBUZ1/P32) CRC SUB CLOCK FREQUENCY MEASUREMENT HIGH-SPEED ON-CHIP OSCILLATOR CLOCK FREQUENCY CORRECTION FUNCTION OSCILLATION STOP DETECTOR AVRT AVSS 4 INTP2/P07(INTP2/P72), INTP3/P05(INTP3/P73), INTP4/P04(INTP4/P74), INTP5/P02(INTP5/P75) 2 INTP6/P41(INTP6/P76), INTP7/P42(INTP7/P77) WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR 12- BIT INTERVAL TIMER INDEPENDENT POWER SUPPLY RTC Power supply separation XT1/P123 SUB CLOCK OSCILLATOR REAL-TIME CLOCK XT2/EXCLKS/P124 3 RTCIC0-RTCIC2 RTCOUT/P150 (RTCOUT/P62) RTC POWER ON RESET VSS Remark 4 SYSTEM CONTROL 24-bit ΔΣ A/D CONVERTER (4ch) ANIN3 ANIP3 P02 to P07 PORT 13 CAPH CAPL SERIAL ARRAY UNIT1 (2ch) RxD2/IrRxD/P55 TxD2/IrTxD/P56 6 PORT 12 VOLTAGE REGULATOR LINSEL CSI10 SEG0 to SEG41 SERIAL INTERFACE IICA0 UART0 SCK00/P05(SCK00/P15) SI00/P06(SI00/P16) SO00/P07(SO00/P17) SCK10/P02(SCK10/P80) SI10/P03(SI10/P81) SO10/P04(SO10/P82) SCL00/P05(SCL00/P15) SDA00/P06(SDA00/P16) 42 RAM SPACE FOR LCD DATA ch11 RxD1/P03(RxD1/P81) TxD1/P04(TxD1/P82) ANI2/P22 to ANI5/P25 ANI0/AVREFP /P20 ANI1/AVREFM/P21 KEY RETURN 8- BIT INTERVAL TIMER 0 ch00 RxD0/P06(RxD0/P16) TxD0/P07(TxD0/P17) 4 10-BIT A/D CONVERTER (6ch) PORT 0 VRTC Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR0). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR0) in the RL78/I1C User's Manual. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 11 of 89 RL78/I1C 1. OUTLINE 1.6 Outline of Functions (1/3) Item 64-pin 80-pin R5F10NLEDFB/ R5F10NLGDFB/ R5F11TLEDFB R5F11TLGDFB 64 KB 128 KB Code flash memory (KB) R5F10NMEDFB R5F10NMGDFB R5F10NMJDFB R5F10NPGDFB R5F10NPJDFB 64 KB 128 KB 256 KB 128 KB 256 KB 16 KBNote 2 8 KB 16 KBNote 2 2 KB Data flash memory (KB) 100-pin 6 KB RAM (KB) 8 KB Note 1 6 KB 8 KBNote 1 Address space 1 MB Main system High-speed system clock clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) HS (High-speed main) mode: 1 to 20 MHz (VDD = 2.7 to 5.5 V), HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.5 to 5.5 V), HS (High-speed main) mode: 1 to 12 MHz (VDD = 2.4 to 5.5 V), HS (High-speed main) mode: 1 to 6 MHz (VDD = 2.1 to 5.5 V), LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.9 to 5.5 V), LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.7 to 5.5 V), LP (Low-power main) mode: 1 MHz (VDD = 1.9 to 5.5 V) High -speed on-chip oscillator clock (fIH) MAX.: 24 MHz Middle -speed onchip oscillator clock (fIM) HS (High-speed main) mode: HS (High-speed main) mode: HS (High-speed main) mode: HS (High-speed main) mode: LS (Low-speed main) mode: LV (Low-voltage main) mode: LP (Low-power main) mode: 1 to 24 MHz (VDD = 2.7 to 5.5 V), 1 to 16 MHz (VDD = 2.5 to 5.5 V), 1 to 12 MHz (VDD = 2.4 to 5.5 V), 1 to 6 MHz (VDD = 2.1 to 5.5 V), 1 to 8 MHz (VDD = 1.9 to 5.5 V), 1 to 4 MHz (VDD = 1.7 to 5.5 V), 1 MHz (VDD = 1.9 to 5.5 V) MAX.: 4 MHz PLL clock (fPLL) Subsystem clock - HS (High-speed main) mode: 32 MHz (VDD = 2.8 to 5.5 V) Subsystem clock oscillator clock (fSX) XT1 (crystal) oscillation, external subsystem clock input (EXCLKS) Low-speed on-chip oscillator clock (fIL) 15 kHz (TYP.): VDD = 1.7 to 5.5V 32.768 kHz (TYP.): VDD = 1.7 to 5.5 V High-speed on-chip oscillator clock frequency correction function Correct the frequency of the high-speed on-chip oscillator clock by the subsystem clock. General-purpose register 8 bits × 8 registers × 4 banks Minimum instruction execution time 0.03125 µs (PLL clock: fPLL = 32 MHz selection) 0.04167 µs (High-speed on-chip oscillator: fIH = 24 MHz operation) 30.5 µs (Subsystem clock: fSUB = 32.768 kHz operation) 66.6 µs (Low-speed on-chip oscillator: fIL = 15 kHz operation) Instruction set I/O port Notes 1. 2. ● ● ● ● ● Data transfer (8/16 bits) Adder and subtractor/logical operation (8/16 bits) Multiplication (16 bits × 16 bits), division (32 bits ÷ 32 bits) Multiplication and accumulation (16 bits × 16 bits + 32 bits) Rotate, barrel shift, and bit manipulation (set, reset, test, and boolean operation), etc. Total 35 52 68 CMOS I/O 27 44 60 CMOS input 5 5 5 CMOS output - - - N-ch O.D I/O (6 V tolerance) 3 3 3 In the case of the 8 KB, this is about 7 KB when the self-programming function is used. In the case of the 16 KB, this is about 15 KB when the self-programming function is used. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 12 of 89 RL78/I1C 1. OUTLINE (2/3) Item Timer 64-pin R5F10NLEDFB/ R5F10NLGDFB/ R5F11TLEDFB R5F11TLGDFB 80-pin R5F10NMEDFB R5F10NMGDFB 16-bit timer TAU 8 channels Watchdog timer 1 channel 12-bit interval timer 1 channel 8/16-bit interval timer 100-pin R5F10NMJDFB R5F10NPGDFB R5F10NPJDFB 4 channels (8-bit)/2 channels (16-bit) Independent power supply real-time clock (RTC) 1 channel Oscillation stop 1 channel detection circuit Timer output Timer outputs: 8 channels PWM outputs: 7Note 1 RTC output 1 channel ● 1 Hz/64 Hz (sub clock: fSX = 32.768 kHz) RTC time capture input - 3 channels Clock output/buzzer output 2 ● 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) ● 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Sub clock: fSX = 32.768 kHz operation) 10-bit resolution A/D converter 4 channels 4 channels 6 channels 24-Bit ΔΣ A/D Converter 4 channels 3 channels 4 channels 2 channels 3 channels SNDR Typ. 80 dB (gain ×1) Min. 69 dB (gain ×16) Min. 65 dB (gain ×32) Sampling frequency 3.906 kHz/1.953 kHz PGA ×1, ×2, ×4, ×8, ×16, ×32 Serial CSI/UART/simplified I interface UART/IrDA 2C: 2 channels 1 channel 2 I C bus 1 channel 32-bit multiplier and multiply- 32 bits × 32 bits = 64 bits (Unsigned or signed) (5 clock) accumulator 32 bits × 32 bits + 64 bits = 64 bits (Unsigned or signed) (5 clock) Data transfer controller (DTC) 36 sources 38 sources Event link Event input 9 controller (ELC) Event trigger input 13 LCD controller/driver Internal voltage boosting method, capacitor split method, and external resistance division method are switchable. Segment signal output 19 (15)Note 2 Internal interrupt sources External Notes 1. 42 (38)Note 2 4 (8)Note 2 Common signal output Vectored 34 (30)Note 2 41 41 44 9 12 12 The number of outputs varies, depending on the setting of channels in use and the number of the master (see 8.9.3 Operation as multiple PWM output function in the RL78/I1C User's Manual). 2. The values in parentheses are the number of signal outputs when 8 com is used. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 13 of 89 RL78/I1C 1. OUTLINE (3/3) Item 64-pin R5F10NLEDFB/ R5F10NLGDFB/ R5F11TLEDFB R5F11TLGDFB Key interrupt input AES circuit 80-pin R5F10NMEDFB R5F10NMGDFB 5 Note 3 100-pin R5F10NMJDFB R5F10NPGDFB R5F10NPJDFB 8 Cipher modes of operation: GCM/ECB/CBC Encryption key length: 128/192/256-bit Reset MCU ● Reset by RESET pin ● Internal reset by watchdog timer ● Internal reset by power-on-reset of internal VDDNote 1 power supply ● Internal reset by voltage detector of internal VDDNote 1 power supply ● Internal reset by illegal instruction executionNote 2 ● Internal reset by RAM parity error ● Internal reset by illegal-memory access RTC ● RTC circuit reset by RTC Power-on-reset Power-on-reset circuit Internal VDD ● Power-on-reset: Note 1 VRTC Voltage detector 1.51 V (TYP.) ● Power-down-reset: 1.50 V (TYP.) ● RTC Power-on-reset: 1.52 V (TYP.) ● RTC Power-down-reset: 1.50 V (TYP.) Internal VDD ● Rising edge: 1.77 V to 4.06 V (13 stages) Note 1 VDD ● Falling edge: 1.73 V to 3.98 V (13 stages) ● Rising edge: 2.53 V to 3.77 V (6 stages) ● Falling edge: 2.46 V to 3.70 V (6 stages) VBAT ● Rising edge: 2.11 V to 2.73 V (7 stages) ● Falling edge: 2.05 V to 2.67 V (7 stages) VRTC ● Rising edge: 2.22 V to 2.84 V (4 stages) EXLVD ● Rising edge: 1.33 V ● Falling edge: 2.16 V to 2.78 V (4 stages) ● Falling edge: 1.28 V Battery backup CPU VDD/VBAT function ΔΣ A/D VDD/VBAT Converter RTC VRTC (independent power supply) On-chip debug function Provided Power supply voltage VDD = 1.7 to 5.5 V Operating ambient temperature TA = –40 to +85°C Notes 1. Either VDD or VBAT is selected by the battery backup function. 2. This reset occurs when instruction code FFH is executed. 3. Only available in R5F10N products. This reset does not occur during emulation using an in-circuit emulator or an on-chip debugging emulator. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 14 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS 2. ELECTRICAL SPECIFICATIONS Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 2. The pins mounted depend on the product. See 2.1 Port Function to 2.2.1 With functions for each product in the RL78/I1C User's Manual. Remarks 1. In the descriptions in this chapter, read EVDD as EVDD0 and EVDD1, and EVSS as EVSS0 and EVSS1. 2. For 64-pin products, read EVDD as VDD and EVSS as VSS. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 15 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS 2.1 Absolute Maximum Ratings Absolute Maximum Ratings (1/3) Parameter Supply voltage Symbols Ratings Unit VDD –0.5 to +6.5 V EVDD –0.5 to +6.5 V VBAT –0.5 to +6.5 V VRTC –0.5 to +6.5 V –0.3 to +2.8 V REGC pin input voltage VIREGC Conditions REGC and –0.3 to VDDNote 4 +0.3Note 1 Input voltage VI1 P02 to P07, P10 to P17, P30 to P37, P40 to P43, V –0.3 to EVDD +0.3 and –0.3 to VDDNote 4 +0.3Note 2 P50 to P57, P70 to P77, P80 to P85, P125 to P127 VI2 VI3 P60 to P62 (N-ch open-drain) –0.3 to +6.5 P20 to P25, P121 to P122, P137, P150 to 152, –0.3 to VDD Note 4 +0.3 V Note 2 V EXCLK Output voltage VI4 RESET VI5 P123, P124, EXCLKS VO1 –0.3 to +6.5 V –0.3 to VRTC +0.3Note 2 V P02 to P07, P10 to P17, P30 to P37, P40 to P43, –0.3 to EVDD +0.3 V P50 to P57, P60 to P62, P70 to P77, P80 to P85, and –0.3 to VDDNote 4 +0.3Note 2 P125 to P127 VO2 Analog input voltage VAI1 –0.3 to VDDNote 4 +0.3 Note 2 P20 to P25, P150 to P152 –0.3 to VDD ANI0 to ANI5 Note 4 V +0.3 V and –0.3 to AVREF(+) +0.3Notes 2, 3 VAI2 ANIP0 to ANIP3, ANIN0 to ANIN3 V –0.6 to +2.8 and –0.6 to AREGC +0.3Note 5 Reference supply VIDSAD AREGC, AVCM, AVRT V –0.3 to +2.8 and –0.3 to VDDNote 4 +0.3Note 6 voltage Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. 2. Must be 6.5 V or lower. 3. Do not exceed AV REF(+) + 0.3 V in case of A/D conversion target pin. 4. Either V DD or VBAT is selected by the battery backup function. 5. The ΔΣ A/D conversion target pin must not exceed AREGC +0.3 V. 6. Connect AREGC, AVCM, and AVRT terminals to V SS via capacitor (0.47 µF). This value defines the absolute maximum rating of AREGC, AVCM, and AVRT terminal. Do not use with voltage applied. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. 2. AVREF (+): + side reference voltage of the A/D converter. 3. VSS: Reference voltage R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 16 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (2/3) Parameter LCD voltage Symbols VLI1 Conditions VL1 voltage Note 1 Ratings Unit –0.3 to 2.8 V and –0.3 to VL4 +0.3 VLI2 VL2 voltageNote 1 –0.3 to VL4 +0.3Note 2 V VLI3 VL3 voltageNote 1 –0.3 to VL4 +0.3Note 2 V VLI4 VL4 voltageNote 1 –0.3 to +6.5 V VLCAP VOUT CAPL, CAPH voltage Note 1 COM0 to COM7, External resistance division –0.3 to VL4 +0.3 Note 2 V Note 2 V –0.3 to VDDNote 3 +0.3Note 2 V –0.3 to VDD Note 3 +0.3 SEG0 to SEG41, method output voltage Capacitor split method Internal voltage boosting method Notes 1. –0.3 to VL4 +0.3 Note 2 V This value only indicates the absolute maximum ratings when applying voltage to the V L1 , VL2 , V L3 , and V L4 pins; it does not mean that applying voltage to these pins is recommended. When using the internal voltage boosting method or capacitance split method, connect these pins to V SS via a capacitor (0.47 µF ± 30%) and connect a capacitor (0.47 µF ± 30%) between the CAPL and CAPH pins. 2. Must be 6.5 V or lower. 3. Either VDD or VBAT is selected by the battery backup function. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark VSS: Reference voltage R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 17 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (3/3) Parameter Output current, high Symbols IOH1 Conditions Per pin P02 to P07, P10 to P17, P30 to Ratings Unit –40 mA P37, P40 to P43, P50 to P57, P70 to P77, P80 to P85, P125 to P127 Total of all pins P02 to P07, P40 to P43 –70 mA –170 mA P10 to P17, P30 to P37, P50 to –100 mA –0.5 mA –2 mA 40 mA P57, P70 to P77, P80 to P85, P125 to P127 IOH2 Per pin P20 to P25, P150 to P152 Total of all pins Output current, low IOL1 Per pin P02 to P07, P10 to P17, P30 to P37, P40 to P43, P50 to P57, P70 to P77, P80 to P85, P125 to P127 Total of all pins P02 to P07, P40 to P43 70 mA 170 mA P10 to P17, P30 to P37, P50 to 100 mA 1 mA P57, P60 to P62, P70 to P77, P80 to P85, P125 to P127 IOL2 Per pin P20 to P25, P150 to P152 Total of all pins Operating ambient TA temperature Storage temperature In normal operation mode 5 mA –40 to +85 °C –65 to +150 °C In flash memory programming mode Tstg Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 18 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS 2.2 Oscillator Characteristics 2.2.1 X1, XT1 oscillator characteristics (TA = –40 to +85°C, 1.7 V ≤ VDDNote 2 ≤ 5.5 V, VSS = 0 V) Parameter Resonator Conditions MIN. TYP. MAX. Unit X1 clock oscillation Ceramic resonator/ 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz frequency (fX)Notes 1, 2 crystal resonator 2.5 V ≤ VDD < 2.7 V 1.0 16.0 MHz 2.4 V ≤ VDD < 2.5 V 1.0 12.0 MHz 1.9 V ≤ VDD < 2.4 V 1.0 8.0 MHz 1.7 V ≤ VDD < 1.9 V 1.0 4.0 MHz 35 kHz XT1 clock oscillation Crystal resonator 32 32.768 frequency (fXT)Notes 1, 2 Notes 1. Indicates only permissible oscillator frequency ranges. See 2.4 AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. 2. Either V DD or VBAT is selected by the battery backup function. Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark When using the X1 oscillator and XT1 oscillator, see 6.4 System Clock Oscillator in the RL78/I1C User's Manual. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 19 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS 2.2.2 On-chip oscillator characteristics (TA = –40 to +85°C, 1.7 V ≤ VDDNote 3 ≤ 5.5 V, VSS = 0 V) Oscillators High-speed on-chip oscillator Parameters Conditions MIN. fIH TYP. MAX. Unit 1.5 24 MHz –1.0 +1.0 % clock frequencyNotes 1, 2 High-speed on-chip oscillator –20 to +85°C clock frequency accuracy 1.7 V ≤ VDD –40 to –20°C Middle-speed on-chip oscillator 1.9 V ≤ VDDNote 3 ≤ 5.5 V Note 3 ≤ 1.9 V –5.0 +5.0 % 1.9 V ≤ VDDNote 3 ≤ 5.5 V –1.5 +1.5 % 1.7 V ≤ VDDNote 3 ≤ 1.9 V –5.5 +5.5 % 1 4 MHz –12 +12 % fIM clock frequencyNote 2 1.9 V ≤ VDDNote 3 ≤ 5.5 V Middle-speed on-chip oscillator clock frequency accuracy Low-speed on-chip oscillator fIL 15 kHz clock frequency Low-speed on-chip oscillator –15 +15 % clock frequency accuracy Notes 1. The high-speed on-chip oscillator frequency is selected by using bits 0 to 3 of option byte (000C2H/010C2H) and bits 0 to 2 of the HOCODIV register. 2. This indicates the oscillator characteristics only. See 2.4 AC Characteristics for the instruction execution time. 3. Either VDD or VBAT is selected by the battery backup function. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 20 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS 2.2.3 PLL oscillator characteristics (TA = –40 to +85°C, 2.7 V ≤ VDDNote 2 ≤ 5.5 V, VSS = 0 V) Oscillators PLL input frequency Parameters Note 1 PLL output frequency Note 1 Lockup wait time fPLLIN Conditions MIN. fIH fPLL Wait time from PLL output enable to frequency TYP. MAX. Unit 4 MHz 32 MHz 40 µs stabilization Interval wait time Wait time from PLL stop to PLL restart setting 4 µs Setting wait time Wait time from PLL input clock stabilization and 1 µs PLL setting fixedness to start-up setting Notes 1. Indicates only permissible oscillator frequency ranges. 2. Either V DD or VBAT is selected by the battery backup function. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 21 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS 2.3 DC Characteristics 2.3.1 Pin characteristics (TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 4 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Symbol Output current, IOH1 highNote 1 Conditions MIN. MAX. Unit –10.0Note 2 mA 4.0 V ≤ EVDD ≤ 5.5 V –55.0 mA 2.7 V ≤ EVDD < 4.0 V –10.0 mA 1.9 V ≤ EVDD < 2.7 V –5.0 mA 1.7 V ≤ EVDD < 1.9 V –2.5 mA 4.0 V ≤ EVDD ≤ 5.5 V –80.0 mA 2.7 V ≤ EVDD < 4.0 V –19.0 mA 1.9 V ≤ EVDD < 2.7 V –10.0 mA 1.7 V ≤ EVDD < 1.9 V –5.0 mA –100.0 mA –0.1Note 2 mA –0.9 mA Per pin for P02 to P07, P10 to P17, P30 to 1.9 V ≤ EVDD ≤ 5.5 V P37, P40 to P43, P50 to P57, P70 to P77, P80 to P85, P125 to P127 Total of P02 to P07, P40 to P43 (When duty ≤ 70%Note 3) Total of P10 to P17, P30 to P37, P50 to P57, P70 to P77, P80 to P85, P125 to P127 (When duty ≤ 70%Note 3) Total of all pins TYP. (When duty ≤ 70%Note 3) IOH2 Per pin for P20 to P25, P150 to P152 Total of all pins (When duty ≤ 70%Note 3) Notes 1. 1.7 V ≤ VDDNote 4 ≤ 5.5 V 1.7 V ≤ VDD Note 4 ≤ 5.5 V Value of current at which the device operation is guaranteed even if the current flows from the EVDD and VDD pins to an output pin. 2. Do not exceed the total current value. 3. Specification under conditions where the duty factor ≤ 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). ● Total output current of pins = (IOH × 0.7)/(n × 0.01) Where n = 80% and IOH = –10.0 mA Total output current of pins = (–10.0 × 0.7)/(80 × 0.01)  –8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. 4. Either V DD or VBAT is selected by the battery backup function. Caution P02 to P07, P12 to P17, P31, P56, P57, P80 to P82, P84, and P85 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 22 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 4 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Symbol Output current, IOL1 lowNote 1 MAX. Unit Per pin for P02 to P07, P10 to P17, P30 to P37, P40 to P43, P50 to P57, P70 to P77, P80 to P85, P125 to P127 Conditions 20.0Note 2 mA Per pin for P60 to P62 15.0Note 2 mA Total of P02 to P07, P40 to P43 (When duty ≤ 70%Note 3) Total of P10 to P17, P30 to P37, P50 to P57, P60 to P62, P70 to P77, P80 to P85, P125 to P127 (When duty ≤ 70%Note 3) MIN. 4.0 V ≤ EVDD ≤ 5.5 V 70.0 mA 2.7 V ≤ EVDD < 4.0 V 15.0 mA 1.9 V ≤ EVDD < 2.7 V 9.0 mA 1.7 V ≤ EVDD < 1.9 V 4.5 mA 4.0 V ≤ EVDD ≤ 5.5 V 80.0 mA 2.7 V ≤ EVDD < 4.0 V 35.0 mA 1.9 V ≤ EVDD < 2.7 V 20.0 mA 1.7 V ≤ EVDD < 1.9 V 10.0 mA 150.0 mA 0.4Note 2 mA 3.6 mA Total of all pins (When duty ≤ 70%Note 3) IOL2 Per pin for P20 to P25, P150 to P152 1.7 V ≤ VDDNote 4 ≤ 5.5 V Total of all pins (When duty ≤ 70%Note 3) Notes 1. TYP. 1.7 V ≤ VDD Note 4 ≤ 5.5 V Value of current at which the device operation is guaranteed even if the current flows from an output pin to the EVSS and VSS pins. 2. However, do not exceed the total current value. 3. Specification under conditions where the duty factor ≤ 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). ● Total output current of pins = (IOL × 0.7)/(n × 0.01) Where n = 80% and IOL = 10.0 mA Total output current of pins = (10.0 × 0.7)/(80 × 0.01)  8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. 4. Remark Either V DD or VBAT is selected by the battery backup function. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 23 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Input voltage, Symbol VIH1 high Conditions MIN. P02 to P07, P10 to P17, P30 to P37, Normal input buffer TYP. MAX. Unit 0.8EVDD EVDD V 2.2 EVDD V 2.0 EVDD V 1.5 EVDD V P40 to P43, P50 to P57, P70 to P77, P80 to P85, P125 to P127 VIH2 P02, P03, P05, P06, P12, P13, P15, TTL input buffer P16, P30, P55, P57, P80, P81, P84 4.0 V ≤ EVDD ≤ 5.5 V TTL input buffer 3.3 V ≤ EVDD < 4.0 V TTL input buffer 1.7 V ≤ EVDD < 3.3 V VIH3 P20 to P25 0.7VDDNote VDDNote V VIH4 P60 to P62 0.7EVDD 6.0 V VIH5 Input voltage, P121 to P122, P137, P150 to P152, EXCLK VIH6 RESET VIH7 P123, P124, EXCLKS VIL1 P02 to P07, P10 to P17, P30 to P37, Normal input buffer low 0.8VDD Note 0.8VDD Note VDD Note 6.0 V V 0.8VRTC VRTC V 0 0.2EVDD V 0 0.8 V 0 0.5 V 0 0.32 V P40 to P43, P50 to P57, P70 to P77, P80 to P85, P125 to P127 VIL2 P02, P03, P05, P06, P12, P13, P15, TTL input buffer P16, P30, P55, P57, P80, P81, P84 4.0 V ≤ EVDD ≤ 5.5 V TTL input buffer 3.3 V ≤ EVDD < 4.0 V TTL input buffer 1.7 V ≤ EVDD < 3.3 V Note VIL3 P20 to P25 0 0.3VDDNote V VIL4 P60 to P62 0 0.3EVDD V VIL5 P121, P122, P137, P150 to P152, EXCLK, RESET 0 VIL6 P123, P124, EXCLKS 0 0.2VDD Note 0.2VRTC V V Either V DD or VBAT is selected by the battery backup function. Caution The maximum value of VIH of pins P02 to P07, P12 to P17, P31, P56, P57, P80 to P82, P84, and P85 is EVDD, even in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 24 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Symbol Conditions MIN. Output voltage, VOH1 P02 to P07, P10 to P17, P30 to P37, 4.0 V ≤ EVDD ≤ 5.5 V, high P40 to P43, P50 to P57, P70 to P77, IOH1 = –10.0 mA P80 to P85, P125 to P127 4.0 V ≤ EVDD ≤ 5.5 V, TYP. MAX. Unit EVDD – 1.5 V EVDD – 0.7 V EVDD – 0.6 V EVDD – 0.5 V EVDD – 0.5 V VDD – 0.5 V IOH1 = –3.0 mA 2.7 V ≤ EVDD ≤ 5.5 V, IOH1 = –2.0 mA 1.9 V ≤ EVDD ≤ 5.5 V, IOH1 = –1.5 mA 1.7 V ≤ EVDD ≤ 5.5 V, IOH1 = –1.0 mA VOH2 P20 to P25, P150 to P152 1.7 V ≤ VDDNote ≤ 5.5 V, IOH2 = –100 µA Output voltage, VOL1 P02 to P07, P10 to P17, P30 to P37, 4.0 V ≤ EVDD ≤ 5.5 V, low P40 to P43, P50 to P57, P70 to P77, IOL1 = 20 mA P80 to P85, P125 to P127 4.0 V ≤ EVDD ≤ 5.5 V, 1.3 V 0.7 V 0.6 V 0.4 V 0.4 V 0.4 V 0.4 V 2.0 V 0.4 V 0.4 V 0.4 V 0.4 V IOL1 = 8.5 mA 2.7 V ≤ EVDD ≤ 5.5 V, IOL1 = 3.0 mA 2.7 V ≤ EVDD ≤ 5.5 V, IOL1 = 1.5 mA 1.9 V ≤ EVDD ≤ 5.5 V, IOL1 = 0.6 mA 1.7 V ≤ EVDD ≤ 5.5 V, IOL1 = 0.3 mA VOL2 P20 to P25, P150 to P152 1.7 V ≤ VDDNote ≤ 5.5 V, IOL2 = 400 µA VOL3 P60 to P62 4.0 V ≤ EVDD ≤ 5.5 V, IOL3 = 15.0 mA 4.0 V ≤ EVDD ≤ 5.5 V, IOL3 = 5.0 mA 2.7 V ≤ EVDD ≤ 5.5 V, IOL3 = 3.0 mA 1.9 V ≤ EVDD ≤ 5.5 V, IOL3 = 2.0 mA 1.7 V ≤ EVDD ≤ 5.5 V, IOL3 = 1.0 mA Note Either V DD or VBAT is selected by the battery backup function. Caution P02 to P07, P12 to P17, P31, P56, P57, P80 to P82, P84, and P85 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 25 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Symbol Conditions Input leakage ILIH1 P02 to P07, P10 to P17, P30 to P37, current, high P40 to P43, P50 to P57, P60 to P62, MIN. TYP. MAX. Unit VI = EVDD 1 µA VI = VDDNote 1 µA 1 µA In resonator connection 10 µA In input port or external 1 µA 10 µA VI = EVSS –1 µA VI = VSS –1 µA –1 µA In resonator connection –10 µA In input port or external –1 µA –10 µA P70 to P77, P80 to P85, P125 to P127 ILIH2 P20 to P25, P137, P150 to P152, RESET ILIH3 P121, P122 VI = VDDNote In input port or external (X1, X2, EXCLK) ILIH4 P123, P124 clock input VI = VRTC (EXCLKS) clock input In resonator connection Input leakage ILIL1 current, low P02 to P07, P10 to P17, P30 to P37, P40 to P43, P50 to P57, P70 to P77, P80 to P85, P125 to P127 ILIL2 P20 to P25, P137, P150 to P152, RESET ILIL3 P121, P122 VI = VSS (X1, X2, EXCLK) ILIL4 P123, P124 In input port or external clock input VI = VSS (EXCLKS) clock input In resonator connection On-chip pull- RU1 RU2 Note P10 to P17, P30 to P37, P50 to P57, VI = EVSS P70 to P77, P80 to P85, P125 to P127 up resistance 2.4 V ≤ EVDD ≤ 5.5 V 10 20 100 kΩ 1.7 V ≤ EVDD ≤ 5.5 V 10 30 100 kΩ 10 20 100 kΩ P02 to P07, P40 to P43, P150 to P152 VI = EVSS Either V DD or VBAT is selected by the battery backup function. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 26 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS 2.3.2 Supply current characteristics (TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 8 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Supply currentNote 1 Symbol IDD1 Conditions Operating mode HS (highspeed main) modeNote 5 LS (lowspeed main) modeNote 5 Note 3 fCLK = 32 MHz PLL operation fIH = 24 MHz Note 3 MIN. Normal operation TYP. MAX. Unit VDD = 5.0 V 5.2 8.5 mA VDD = 3.0 V 5.2 8.5 mA VDD = 5.0 V 1.7 VDD = 3.0 V 1.7 Normal operation VDD = 5.0 V 3.9 VDD = 3.0 V 3.9 6.6 mA fIH = 12 MHzNote 3 Normal operation VDD = 5.0 V 2.4 3.8 mA VDD = 3.0 V 2.4 3.8 mA fIH = 6 MHzNote 3 Normal operation VDD = 5.0 V 1.7 2.6 mA VDD = 3.0 V 1.7 2.6 mA fIH = 3 MHzNote 3 Normal operation VDD = 5.0 V 1.3 2.0 mA VDD = 3.0 V 1.3 2.0 mA Normal operation VDD = 3.0 V 1.3 2.2 mA VDD = 2.0 V 1.3 2.2 mA Normal operation VDD = 3.0 V 1.1 2.1 mA VDD = 2.0 V 1.1 2.1 mA Normal operation VDD = 3.0 V 0.84 1.40 mA VDD = 2.0 V 0.84 1.40 mA fIH = 8 MHz Note 3 fIH = 6 MHzNote 3 fIH = 4 MHzNote 3 fIM = 4 MHzNote 6 Basic operation (1/6) Normal operation mA mA 6.6 mA VDD = 3.0 V 0.70 1.20 mA VDD = 2.0 V 0.70 1.20 mA fIH = 3 MHzNote 3 Normal operation VDD = 3.0 V 0.7 1.4 mA VDD = 2.0 V 0.7 1.4 mA fIH = 4 MHzNote 3 LV (lowvoltage main) modeNote 5 Normal operation VDD = 3.0 V 1.3 1.9 mA VDD = 2.0 V 1.3 1.9 mA fIH = 1 MHzNote 3 Normal operation VDD = 3.0 V 315 530 µA VDD = 2.0 V 315 530 µA fIM = 1 MHzNote 6 Normal operation VDD = 3.0 V 160 300 µA VDD = 2.0 V 160 300 µA LP (lowpower main) modeNote 5 (Notes and Remarks are listed on the page after the next page.) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 27 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 8 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Supply currentNote 1 IDD1 Conditions Operating mode MIN. Note 2 fMX = 20 MHz HS (high, speed main) VDD = 5.0 V modeNote 5 fMX = 20 MHzNote 2, VDD = 3.0 V fMX = 16 MHz VDD = 5.0 V Note 2 fMX = 16 MHz VDD = 3.0 V Note 2 , , 5.5 mA 3.5 5.7 mA Normal operation Square wave input 3.3 5.5 mA Resonator connection 3.5 5.7 mA Normal operation Square wave input 2.8 4.4 mA Resonator connection 2.9 4.6 mA Normal operation Square wave input 2.8 4.4 mA Resonator connection 2.9 4.6 mA Square wave input 2.3 3.6 mA fMX = 10 MHzNote 2, VDD = 5.0 V Normal operation fMX = 10 MHzNote 2, VDD = 3.0 V Normal operation Normal operation Normal operation Normal operation Normal operation Square wave input fMX = 4 MHz VDD = 2.0 V Note 2 , , fIH = 1 MHzNote 2, LP (lowpower main) VDD = 3.0 V modeNote 5 fIH = 1 MHzNote 2, VDD = 2.0 V Subclock operation 3.3 Normal operation fMX = 4 MHz VDD = 3.0 V Normal operation Normal operation fSUB = 32.768 kHzNote 4, Normal TA = –40°C operation fSUB = 32.768 kHzNote 4, Normal operation TA = +25°C fSUB = 32.768 kHz TA = +50°C Note 4 fSUB = 32.768 kHz TA = +70°C Note 4 fSUB = 32.768 kHz TA = +85°C Note 4 Unit Square wave input fMX = 12 MHzNote 2, VDD = 3.0 V Note 2 MAX. Resonator connection Normal operation LS (low, fMX = 8 MHz speed main) VDD = 3.0 V modeNote 5 fMX = 8 MHzNote 2, VDD = 2.0 V TYP. Normal operation fMX = 12 MHzNote 2, VDD = 5.0 V Note 2 (2/6) , Normal operation , Normal operation , Normal operation Resonator connection 2.4 3.7 mA Square wave input 2.3 3.6 mA Resonator connection 2.4 3.7 mA Square wave input 2.0 3.2 mA Resonator connection 2.1 3.3 mA Square wave input 2.0 3.2 mA Resonator connection 2.1 3.3 mA Square wave input 1.1 2.0 mA Resonator connection 1.2 2.1 mA Square wave input 1.1 2.0 mA Resonator connection 1.2 2.1 mA Square wave input 0.7 1.2 mA Resonator connection 0.7 1.3 mA Square wave input 0.7 1.2 mA Resonator connection 0.7 1.3 mA 140 240 µA Resonator connection 190 300 µA Square wave input 140 240 µA Resonator connection 190 300 µA Square wave input 5.1 6.6 µA Resonator connection 5.2 6.7 µA Square wave input 5.4 7.1 µA Resonator connection 5.5 7.2 µA Square wave input 5.6 8.0 µA Resonator connection 5.7 8.1 µA Square wave input 6.1 9.7 µA Resonator connection 6.2 9.8 µA Square wave input 6.8 13.7 µA Resonator connection 6.9 13.8 µA fIL = 15 kHz, TA = +85°C Note 7 Normal operation 2.5 7.0 µA fIL = 15 kHz, TA = –40°C Note 7 Normal operation 2.8 7.0 µA fIL = 15 kHz, TA =+ 25°C Note 7 Normal operation 4.1 11.0 µA (Notes and Remarks are listed on the next page.) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 28 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS Notes 1. Total current flowing into VDD, EVDD, and VRTC including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the LCD controller/driver, A/D converter, ΔΣ A/D converter, LVD circuit, battery backup circuit, I/O port, and on-chip pull-up/pull-down resistors. When the VBAT pin (pin for battery backup) is selected, current flowing into VBAT. 2. When high-speed on-chip oscillator, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. 3. When high-speed system clock, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. 4. When high-speed on-chip oscillator, middle-speed on-chip oscillator, and high-speed system clock are stopped. When setting ultra-low current consumption (AMPHS1 = 1). However, not including the current flowing into Independent power supply RTC, 12-bit interval timer, and watchdog timer. 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.8 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz 2.5 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 12 MHz 2.1 V ≤ VDD ≤ 5.5 V@1 MHz to 6 MHz LS (low-speed main) mode: 1.9 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz LP (low-power main) mode: 1.9 V ≤ VDD ≤ 5.5 V@1 MHz LV (low-voltage main) mode: 1.7 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz 6. When high-speed on-chip oscillator, low-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. 7. When high-speed on-chip oscillator, middle-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. 8. Either V DD or VBAT is selected by the battery backup function. Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fIM: Middle-speed on-chip oscillator clock frequency 4. fIL: Low-speed on-chip oscillator clock frequency 5. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 6. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 29 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 10 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Note 2 DD2 I Supply currentNote 1 Conditions HALT mode Note 4 fCLK = 32 MHz HS (high, speed main) PLL operation modeNote 7 fIH = 24 MHzNote 4 fIH = 12 MHzNote 4 fIH = 6 MHzNote 4 fIH = 3 MHzNote 4 Note 4 fIH = 8 MHz LS (lowspeed main) modeNote 7 fIH = 6 MHzNote 4 fIH = 4 MHz Note 4 fIM = 4 MHz fIH = 3 MHz LV (lowvoltage main) modeNote 7 Note 9 Note 4 fIH = 4 MHzNote 4 fIH = 1 MHzNote 4 LP (lowpower main) modeNote 7 fIM = 1 MHzNote 9 MIN. (3/6) TYP. MAX. Unit VDD = 5.0 V 0.80 2.0 mA VDD = 3.0 V 0.80 2.0 mA VDD = 5.0 V 0.48 1.45 mA VDD = 3.0 V 0.48 1.45 mA VDD = 5.0 V 0.37 0.91 mA VDD = 3.0 V 0.37 0.91 mA VDD = 5.0 V 0.32 0.63 mA VDD = 3.0 V 0.32 0.63 mA VDD = 5.0 V 0.29 0.49 mA VDD = 3.0 V 0.29 0.49 mA VDD = 3.0 V 280 740 µA VDD = 2.0 V 280 740 µA VDD = 3.0 V 230 620 µA VDD = 2.0 V 230 620 µA VDD = 3.0 V 220 440 µA VDD = 2.0 V 220 440 µA VDD = 3.0 V 55 300 µA VDD = 2.0 V 55 300 µA VDD = 3.0 V 200 534 µA VDD = 2.0 V 200 534 µA VDD = 3.0 V 450 825 µA VDD = 2.0 V 450 825 µA VDD = 3.0 V 195 400 µA VDD = 2.0 V 195 400 µA VDD = 3.0 V 33 100 µA 33 100 µA fMX = 20 MHzNote 3, HS (highspeed main) VDD = 5.0 V modeNote 7 fMX = 20 MHzNote 3, VDD = 3.0 V Square wave input VDD = 2.0 V 0.31 1.08 mA fMX = 16 MHzNote 3, VDD = 5.0 V Resonator connection fMX = 16 MHzNote 3, VDD = 3.0 V Square wave input 0.28 0.86 mA Resonator connection 0.42 1.00 mA fMX = 12 MHzNote 3, VDD = 5.0 V Square wave input 0.23 0.70 mA Resonator connection 0.37 0.79 mA fMX = 12 MHzNote 3, VDD = 3.0 V Square wave input 0.23 0.70 mA Resonator connection 0.36 0.79 mA fMX = 10 MHzNote 3, VDD = 5.0 V Square wave input 0.21 0.63 mA Resonator connection 0.29 0.71 mA fMX = 10 MHzNote 3, VDD = 3.0 V Square wave input 0.21 0.63 mA Resonator connection 0.28 0.71 mA Resonator connection 0.48 1.28 mA Square wave input 0.31 1.08 mA Resonator connection 0.48 1.28 mA Square wave input 0.28 0.86 mA 0.42 1.00 mA (Notes and Remarks are listed on the page after the next page.) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 30 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 10 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Note 2 DD2 I Supply currentNote 1 Conditions HALT mode Note 3 TYP. MAX. Unit fMX = 8 MHz LS (low, speed main) VDD = 3.0 V modeNote 7 fMX = 8 MHzNote 3, VDD = 2.0 V Square wave input 110 360 µA Resonator connection 160 420 µA fMX = 4 MHzNote 3, VDD = 3.0 V Square wave input 39 200 µA Resonator connection 81 250 µA fMX = 4 MHzNote 3, VDD = 2.0 V Square wave input 39 200 µA Resonator connection 81 250 µA fMX = 1 MHzNote 3, LP (lowpower main) VDD = 3.0 V modeNote 7 fMX = 1 MHzNote 3, VDD = 2.0 V Square wave input 14 100 µA Resonator connection 70 200 µA Square wave input 14 100 µA Subsystem clock operation IDD3Note 6 MIN. (4/6) Square wave input 110 360 µA Resonator connection 160 420 µA Resonator connection fSUB = 32.768 kHzNote 5, Square wave input TA = –40°C Resonator connection 70 200 µA 0.80 1.60 µA 1.00 1.80 µA fSUB = 32.768 kHzNote 5, Square wave input TA = +25°C Resonator connection 0.93 1.70 µA 1.13 1.90 µA fSUB = 32.768 kHzNote 5, Square wave input TA = +50°C Resonator connection 1.10 3.00 µA 1.30 3.20 µA fSUB = 32.768 kHzNote 5, Square wave input TA = +70°C Resonator connection 1.50 5.00 µA 1.70 5.20 µA fSUB = 32.768 kHzNote 5, Square wave input TA = +85°C Resonator connection 2.80 9.00 µA 3.00 9.20 µA fIL = 15 kHzNote 9, TA = –40°C 0.78 1.60 fIL = 15 kHzNote 9, TA = +25°C 1.01 1.76 fIL = 15 kHzNote 9, TA = +85°C 2.25 8.45 µA µA µA µA µA µA TA = –40°C STOP modeNote 8 TA = +25°C 0.47 0.90 µA 0.65 1.20 µA TA = +50°C 0.84 2.80 µA TA = +70°C 1.21 4.70 µA TA = +85°C 1.82 9.00 µA (Notes and Remarks are listed on the next page.) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 31 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS Notes 1. Total current flowing into VDD, EVDD, and VRTC including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the LCD controller/driver, A/D converter, ΔΣ A/D converter, LVD circuit, battery backup circuit, I/O port, and on-chip pull-up/pull-down resistors. When the VBAT pin (pin for battery backup) is selected, current flowing into VBAT. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. 4. When high-speed system clock, middle-speed on-chip oscillator, low-speed on-chip oscillator, and subsystem clock are stopped. 5. When operating independent power supply RTC and setting ultra-low current consumption (AMPHS1 = 1). When high-speed on-chip oscillator, middle-speed on-chip oscillator, and high-speed system clock are stopped. However, not including the current flowing into the 12-bit interval timer and watchdog timer. 6. When high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. However, not including the current flowing into independent power supply RTC, 12-bit interval timer, and watchdog timer. 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.8 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz 2.5 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 12 MHz 2.1 V ≤ VDD ≤ 5.5 V@1 MHz to 6 MHz LS (low-speed main) mode: 1.9 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz LP (low-power main) mode: 1.9 V ≤ VDD ≤ 5.5 V@1 MHz LV (low-voltage main) mode: 1.7 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz 8. If operation of the subsystem clock when STOP mode, same as when HALT mode of subsystem clock operation. 9. When high-speed on-chip oscillator, middle-speed on-chip oscillator, and high-speed system clock are stopped. 10. Either VDD or VBAT is selected by the battery backup function. Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fIM: Middle-speed on-chip oscillator clock frequency 4. fIL: Low-speed on-chip oscillator clock frequency 5. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 6. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 32 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 15 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Independent Symbol Notes 3 Conditions MIN. TYP. (5/6) MAX. Unit fSUB = 32.768 kHz 0.70 µA ITMKANotes 1, 2, 4 fSUB = 32.768 kHz, fMAIN is stopped 0.04 µA ITMTNotes 1, 2, 5 fSUB = 32.768 kHz, 8-bit counter mode × 2 ch operation 0.12 µA 16-bit counter mode operation 0.10 µA 0.22 µA 0.10 µA 0.05 µA 0.04 µA IRTC power supply RTC operating current 12-bit interval timer operating current 8-bit interval timer operating fMAIN is stopped, current per unit Watchdog timer IWDTNotes 1, 2, 6 fIL = 15 kHz, fMAIN is stopped operating current LVD operating ILVDNotes 1, 7 current LVDVDD ILVDVDD operating current LVDVBAT Current flowing to VDD or VBAT ILVDVBAT operating current LVDVRTC ILVDVRTC ILVDEXLVD operating current Oscillation stop 0.04 µA Note 1 0.04 µA Current flowing to VRTC 0.04 µA Current flowing to VDD or VBATNote 1 0.04 µA Current flowing to EXLVD 0.16 µA 0.04 µA 0.02 µA 0.05 µA Current flowing to VDD or VBAT IOSDC Note 1 Current flowing to VBAT Current flowing to VDD or VBAT operating current LVDEXLVD Current flowing to VDD Note 1 Note 1 detection circuit operating current Battery backup IBUPNote 1 circuit operating current A/D converter operating current IADCNotes 1, 8 A/D converter reference voltage current IADREFNote 1 75.0 µA Temperature sensor operating current ITMPSNote 1 105 µA BGO operating IBGONotes 1, 9 2.00 12.20 mA IFSPNotes 1, 10 2.00 12.20 mA When conversion at maximum speed Normal mode, AVREFP = VDD = 5.0 V 1.3 2.4 mA Low voltage mode, AVREFP = VDD = 3.0 V 0.5 1.0 mA current Selfprogramming operating current (Notes and Remarks are listed on the next page.) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 33 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 15 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter 24-Bit ΔΣ A/D Symbol IDSAD Notes 1, 11 Converter operating current SNOOZE ISNOZNotes 1, 12 Conditions TYP. MAX. Unit In 4 ch ΔΣ A/D converter operation 1.45 2.30 mA In 3 ch ΔΣ A/D converter operation 1.14 1.85 mA In 1 ch ΔΣA/D converter operation 0.52 0.94 mA ADC operation The mode is performed 0.50 0.80 mA The A/D conversion operations are 1.20 1.80 mA CSI/UART operation 0.70 1.05 mA DTC operation 2.20 mA 0.06 µA 0.85 µA 1.55 µA 0.20 µA operating current MIN. (6/6) performed, low voltage mode, AVREFP = VDD = 3.0 V ILCD1Notes 1, 13, 14 External LCD operating current I Notes 1, 13 LCD2 fLCD = fSUB VDD = 5.0 V, resistance LCD clock = 128 Hz VL4 = 5.0 V division method 1/3 bias, four-time-slices Internal voltage fLCD = fSUB VDD = 3.0 V, boosting method LCD clock = 128 Hz VL4 = 3.0 V 1/3 bias, four-time-slices (VLCD = 04H) VDD = 5.0 V, VL4 = 5.1 V (VLCD = 12H) I Notes 1, 13 LCD3 Capacitor split fLCD = fSUB VDD = 3.0 V, method LCD clock = 128 Hz VL4 = 3.0 V 1/3 bias, four-time-slices Notes 1. Current flowing to VDD. When the VBAT pin (battery backup power supply pin) is selected, current flowing to the VBAT. 2. When high speed on-chip oscillator and high-speed system clock are stopped. 3. Current flowing to VRTC pin, including RTC power supply, subsystem clock oscillator circuit, and RTC. 4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and XT1 oscillator). The value of the current value of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and ITMKA, when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. 5. Current flowing only to the 8-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and XT1 oscillator). The value of the current value of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and ITMT, when the 8-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. 6. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer operates. 7 Current flowing only to the LVD circuit. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVD when the LVD circuit operates. 8. Current flowing only to the A/D converter. The current value of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. 9. Current flowing only during rewrite of 1 KB data flash memory. 10.Current flowing only during self programming. 11.Current flowing only to the 24-bit ΔΣ A/D converter. The current value of the RL78 microcontrollers is the sum of IDD1 or IDD2, and IDSAD when the 24-bit ΔΣ A/D converter operates. 12.For shift time to the SNOOZE mode, see 26.3.3 SNOOZE mode in the RL78/I1C User's Manual. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 34 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS Notes 13. Current flowing only to the LCD controller/driver. The current value of the RL78 microcontrollers is the sum of the LCD operating current (ILCD1, ILCD2 or ILCD3) to the supply current (IDD1, or IDD2) when the LCD controller/driver operates in an operation mode or HALT mode. Not including the current that flows through the LCD panel. Conditions of the TYP. value and MAX. value are as follows. ● Setting 20 pins as the segment function and blinking all ● Selecting fSUB for system clock when LCD clock = 128 Hz (LCDC0 = 07H) ● Setting four time slices and 1/3 bias 14. Not including the current flowing into the external division resistor when using the external resistance division method. 15. Either V DD or VBAT is selected by the battery backup function. Remarks 1. fIL: Low-speed on-chip oscillator clock frequency 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 3. fCLK: CPU/peripheral hardware clock frequency 4. Temperature condition of the TYP. value is TA = 25°C R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 35 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS 2.4 AC Characteristics (TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Instruction cycle (minimum Symbol TCY instruction execution time) Conditions MIN. MAX. Unit 0.03125 1 µs < 2.8 V 0.04167 1 µs < 2.7 V 0.0625 1 µs < 2.5 V 0.08333 1 µs < 2.4 V 0.16667 1 µs ≤ 5.5 V 0.125 1 µs 1.9 V ≤ VDDNote 1 ≤ 5.5 V 0.25 1 µs 1.9 V ≤ VDDNote 1 ≤ 5.5 V 1 2 µs 0.25 1 µs 31.3 µs 0.03125 1 µs Main system HS (high-speed 2.8 V ≤ VDD Note 1 ≤ 5.5 V clock (fMAIN) 2.7 V ≤ VDD Note 1 2.5 V ≤ VDD Note 1 2.4 V ≤ VDD Note 1 2.1 V ≤ VDD Note 1 1.9 V ≤ VDD Note 1 main) mode operation LS (low-speed TYP. (1/2) main) mode LS (low-speed main) mode @4 MHz LP (low-power main) mode LV (low-voltage 1.7 V ≤ VDDNote 1 ≤ 5.5 V main) mode Subsystem clock (fSUB) 1.9 V ≤ VDDNote 1 ≤ 5.5 V 28.5 30.5 operation In the self HS (high-speed 2.8 V ≤ VDDNote 1 ≤ 5.5 V programming main) mode mode 2.7 V ≤ VDD Note 1 < 2.8 V 0.04167 1 µs 2.5 V ≤ VDDNote 1 < 2.7 V 0.0625 1 µs 2.4 V ≤ VDDNote 1 < 2.5 V 0.08333 1 µs 2.1 V ≤ VDD Note 1 < 2.4 V 0.16667 1 µs 1.9 V ≤ VDD Note 1 ≤ 5.5 V 0.125 1 µs LV (low-voltage 1.7 V ≤ VDDNote 1 ≤ 5.5 V 0.25 1 µs 1 20 MHz MHz LS (low-speed main) mode main) mode External system clock fEX frequency 2.7 V ≤ VDDNote 1 ≤ 5.5 V 2.5 V ≤ VDD Note 1 < 2.7 V 1 16 2.4 V ≤ VDD Note 1 < 2.5 V 1 12 MHz 1.9 V ≤ VDDNote 1 < 2.4 V 1 8 MHz 1.7 V ≤ VDDNote 1 < 1.9 V 1 4 MHz 32 35 kHz fEXS External system clock input tEXH, high-level width, low-level tEXL width 2.7 V ≤ VDD Note 1 ≤ 5.5 V 24 ns 2.5 V ≤ VDD Note 1 < 2.7 V 30 ns 2.4 V ≤ VDD Note 1 < 2.5 V 40 ns 1.9 V ≤ VDD Note 1 < 2.4 V 60 ns 1.7 V ≤ VDD Note 1 < 1.9 V tEXHS, 120 ns 13.7 µs 1/fMCK+10 nsNote 2 tEXLS TI00 to TI07 input high-level tTIH, width, low-level width tTIL (Notes and Remark are listed on the next page.) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 36 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items TO00 to TO07 output Symbol fTO frequency Conditions MIN. TYP. (2/2) MAX. Unit HS (high-speed main) 4.0 V ≤ EVDD ≤ 5.5 V 16 MHz mode 2.7 V ≤ EVDD < 4.0 V 8 MHz 2.4 V ≤ EVDD < 2.7 V 4 MHz 2.1 V ≤ EVDD < 2.4 V 4 MHz 1.9 V ≤ EVDD ≤ 5.5 V 4 MHz 1.9 V ≤ EVDD ≤ 5.5 V 0.5 MHz 1.7 V ≤ EVDD ≤ 5.5 V 2 MHz LS (low-speed main) mode LP (low-power main) mode LV (low-voltage main) mode PCLBUZ0, PCLBUZ1 output fPCL HS (high-speed main) 4.0 V ≤ EVDD ≤ 5.5 V 16 MHz frequency mode 2.7 V ≤ EVDD < 4.0 V 8 MHz 2.4 V ≤ EVDD < 2.7 V 4 MHz 2.1 V ≤ EVDD < 2.4 V 4 MHz 1.9 V ≤ EVDD ≤ 5.5 V 4 MHz 1.9 V ≤ EVDD ≤ 5.5 V 1 MHz LV (low-voltage main) 1.9 V ≤ EVDD ≤ 5.5 V 4 MHz mode 1.7 V ≤ EVDD < 1.9 V 2 MHz LS (low-speed main) mode LP (low-power main) mode Interrupt input high-level tINTH, INTP0 1.7 V ≤ VDD width, low-level width tINTL INTP1 to INTP7 Key interrupt input low-level tKR KR0 to KR7 width RESET low-level width Note 1 ≤ 5.5 V 1 µs 1.7 V ≤ EVDD ≤ 5.5 V 1 µs 1.9 V ≤ EVDD ≤ 5.5 V 250 ns 1.7 V ≤ EVDD < 1.9 V 1 µs 10 µs tRSL Notes 1. Either V DD or VBAT is selected by the battery backup function. 2. The following conditions are required for low voltage interface: 1.9 V ≤ VDD < 2.7 V: MIN. 125 ns Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKSmn0, CKSmn1 bits of timer mode register mn (TMRmn) m: Unit number (m = 0), n: Channel number (n = 0 to 7)) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 37 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL External System Clock Timing 1/fEX tEXL tEXH 0.7VDD (MIN.) 0.3VDD (MAX.) EXCLK 1/fEXS tEXLS tEXHS 0.7VRTC (MIN.) 0.3VRTC (MAX.) EXCLKS TI/TO Timing tTIL tTIH TI00 to TI07 1/fTO TO00 to TO07 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP7 R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 38 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS Key interrupt Input Timing tKR KR0 to KR7 RESET Input Timing tRSL RESET R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 39 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS 2.5 Peripheral Functions Characteristics AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL 2.5.1 Serial array unit (1) During communication at same potential (UART mode) (dedicated baud rate generator output) (TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 4 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LP (low-power LV (low-voltage main) Mode main) Mode main) Mode main) Mode MIN. Transfer rate 2.4 V ≤ VDD ≤ 5.5 V MAX. fMCK/6 MIN. Note 2 Note 1 MAX. fMCK/6 Note MIN. MAX. fMCK/6 MIN. Note 2 Unit MAX. fMCK/6Note 2 bps 2 Theoretical value of the 4.0 1.3 0.1 0.6 Mbps fMCK/6Note 2 fMCK/6Note fMCK/6Note 2 fMCK/6Note 2 bps maximum transfer rate fMCK = fCLKNote 3 1.9 V ≤ VDD ≤ 5.5 V 2 Theoretical value of the 1.0 1.3 0.1 0.6 Mbps fMCK/6Note 2 fMCK/6Note fMCK/6Note 2 fMCK/6Note 2 bps 0.1 0.6 Mbps fMCK/6Note 2 bps 0.6 Mbps maximum transfer rate fMCK = fCLKNote 3 1.8 V ≤ VDD ≤ 5.5 V 2 Theoretical value of the 1.0 1.3 maximum transfer rate fMCK = fCLKNote 3 1.7 V ≤ VDD ≤ 5.5 V Theoretical value of the maximum transfer rate fMCK = fCLKNote 3 Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only. 2. The following conditions are required for low voltage interface. 2.4 V ≤ EVDD < 2.7 V: MAX. 2.6 Mbps 1.9 V ≤ EVDD < 2.4 V: MAX. 1.3 Mbps 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 32 MHz (2.8 V ≤ EVDD ≤ 5.5 V), 24 MHz (2.7 V ≤ EVDD ≤ 5.5 V), 16 MHz (2.5 V ≤ EVDD ≤ 5.5 V), 12 MHz (2.4 V ≤ EVDD ≤ 5.5 V), 6 MHz (2.1 V ≤ EVDD ≤ 5.5 V), LS (low-speed main) mode: 8 MHz (1.9 V ≤ EVDD ≤ 5.5 V), 4 MHz (1.9 V ≤ EVDD ≤ 5.5 V) LP (low-power main) mode: 1 MHz (1.9 V ≤ EVDD ≤ 5.5 V) LV (low-voltage main) mode: 4 MHz (1.7 V ≤ EVDD ≤ 5.5 V) 4. Either V DD or VBAT is selected by the battery backup function. Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 40 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS UART mode connection diagram (during communication at same potential) TxDq Rx RL78/I1C microcontrollers User’s device RxDq Tx UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Remarks 1. 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 3, 5, 8) fMCK: Serial array unit operation clock frequency (Operating clock that is set with the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 41 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) (TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 4 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LP (low-power LV (low-voltage main) Mode main) Mode main) Mode main) Mode MIN. SCKp cycle time tKCY1 MAX. tKH1, high-/low-level tKL1 width ns 2.4 V ≤ EVDD ≤ 5.5 V 250 500 4000 1000 ns 1.9 V ≤ EVDD ≤ 5.5 V 500 500 4000 1000 ns 1.8 V ≤ EVDD ≤ 5.5 V 1000 1000 4000 1000 ns 4.0 V ≤ EVDD ≤ 5.5 V 1000 4000 1000 ns tKCY1/ tKCY1/ tKCY1/ tKCY1/ ns 2 – 12 2 – 50 2 – 50 2 – 50 tKCY1/ tKCY1/ tKCY1/ tKCY1/ 2 – 18 2 – 50 2 – 50 2 – 50 tKCY1/ tKCY1/ tKCY1/ tKCY1/ 2 – 38 2 – 50 2 – 50 2 – 50 tKCY1/ tKCY1/ tKCY1/ tKCY1/ 2 – 50 2 – 50 2 – 50 2 – 50 1.7 V ≤ EVDD ≤ 5.5 V SCKp↓ to SOp tKCY1/ tKCY1/ 2 – 100 2 – 100 tKCY1/ tKCY1/ tKCY1/ 2 – 100 2 – 100 2 – 100 ns ns ns ns 44 110 110 110 ns 2.7 V ≤ EVDD ≤ 5.5 V 44 110 110 110 ns 2.4 V ≤ EVDD ≤ 5.5 V 75 110 110 110 ns 1.9 V ≤ EVDD ≤ 5.5 V 110 110 110 110 ns 1.8 V ≤ EVDD ≤ 5.5 V 220 220 220 220 ns 220 220 220 ns 19 19 19 ns 19 19 19 ns 1.8 V ≤ EVDD ≤ 5.5 V 19 1.7 V ≤ EVDD ≤ 5.5 V tKSO1 tKCY1/ 2 – 100 ns 4.0 V ≤ EVDD ≤ 5.5 V 1.7 V ≤ EVDD ≤ 5.5 V Delay time from MAX. 1000 1.8 V ≤ EVDD ≤ 5.5 V tKSI1 MIN. 4000 1.9 V ≤ EVDD ≤ 5.5 V (from SCKp↑)Note 2 MAX. 500 2.4 V ≤ EVDD ≤ 5.5 V SIp hold time MIN. 125 2.7 V ≤ EVDD ≤ 5.5 V SIp setup time (to tSIK1 SCKp↑)Note 1 MAX. 2.7 V ≤ EVDD ≤ 5.5 V 1.7 V ≤ EVDD ≤ 5.5 V SCKp MIN. Unit C = 30 1.8 V ≤ EVDD 25 25 25 25 ns 25 25 25 ns pFNote 3 ≤ 5.5 V outputNote 3 1.7 V ≤ EVDD ≤ 5.5 V Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. C is the load capacitance of the SCKp and SOp output lines. 4. Either V DD or VBAT is selected by the battery backup function. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 10, 30), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 0, 1, 8) 2. fMCK: Serial array unit operation clock frequency (Operating clock that is set with the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 10, 30)) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 42 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 5 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symb Conditions ol HS (high-speed LS (low-speed LP (low-power LV (low-voltage main) Mode main) Mode main) Mode main) Mode MIN. SCKp cycle tKCY2 timeNote 4 MAX. – – ns fMCK ≤ 20 MHz 6/fMCK 6/fMCK 6/fMCK 6/fMCK ns 2.7 V ≤ 16 MHz < fMCK 8/fMCK – – – ns EVDD ≤ fMCK ≤ 16 MHz 6/fMCK 6/fMCK 6/fMCK 6/fMCK ns ns 6/fMCK 6/fMCK 6/fMCK 6/fMCK and 500 and 500 and 500 and 500 6/fMCK 6/fMCK 6/fMCK 6/fMCK and 750 and 750 and 750 and 750 6/fMCK 6/fMCK 6/fMCK 6/fMCK and 1500 and 1500 and 1500 and 1500 6/fMCK 6/fMCK 6/fMCK and 1500 and 1500 and 1500 tKCY2/ tKCY2/ tKCY2/ tKCY2/ 2–7 2–7 2–7 2–7 tKCY2/ tKCY2/ tKCY2/ tKCY2/ 2–8 2–8 2–8 2–8 1.7 V ≤ EVDD ≤ 5.5 V 4.0 V ≤ EVDD ≤ 5.5 V 2.7 V ≤ EVDD ≤ 5.5 V 1.9 V ≤ EVDD ≤ 5.5 V 1.8 V ≤ EVDD ≤ 5.5 V tKCY2/ tKCY2/ tKCY2/ tKCY2/ 2 – 18 2 – 18 2 – 18 2 – 18 tKCY2/ tKCY2/ tKCY2/ tKCY2/ 2 – 66 2 – 66 2 – 66 2 – 66 1.7 V ≤ EVDD ≤ 5.5 V SIp setup tSIK2 time (to SCKp↑)Note 1 tKSI2 time (from Delay time from SCKp↓ to SOp outputNote 2 tKCY2/ tKCY2/ 2 – 66 2 – 66 ns ns ns ns ns ns 1/fMCK+30 1/fMCK+30 1/fMCK+30 ns 1.9 V ≤ EVDD ≤ 5.5 V 1/fMCK+30 1/fMCK+30 1/fMCK+30 1/fMCK+30 ns 1.8 V ≤ EVDD ≤ 5.5 V 1/fMCK+40 1/fMCK+40 1/fMCK+40 1/fMCK+40 ns 1/fMCK+40 1/fMCK+40 1/fMCK+40 ns 1/fMCK+31 1/fMCK+31 1/fMCK+31 ns 1/fMCK+31 1/fMCK+31 1/fMCK+31 ns 1/fMCK+250 ns 2.1 V ≤ EVDD ≤ 5.5 V 1/fMCK+31 1.7 V ≤ EVDD ≤ 5.5 V tKSO2 ns 1/fMCK+20 1.9 V ≤ EVDD ≤ 5.5 V SCKp↑)Note 1 tKCY2/ 2 – 66 ns 2.7 V ≤ EVDD ≤ 5.5 V 1.7 V ≤ EVDD ≤ 5.5 V SIp hold MAX. – 1.8 V ≤ EVDD ≤ 5.5 V level width MIN. 8/fMCK 1.9 V ≤ EVDD ≤ 5.5 V tKH2, MAX. 20 MHz < fMCK 2.4 V ≤ EVDD ≤ 5.5 V tKL2 MIN. EVDD ≤ 5.5 V high-/low- MAX. 4.0 V ≤ 5.5 V SCKp MIN. Unit C = 30 2.7 V ≤ EVDD ≤ pFNote 3 5.5 V 2.4 V ≤ EVDD ≤ 5.5 V 1.9 V ≤ EVDD ≤ 5.5 V 1.8 V ≤ EVDD ≤ 5.5 V 2/fMCK+ 2/fMCK+ 2/fMCK+ 2/fMCK+ 44 110 110 110 2/fMCK+ 2/fMCK+ 2/fMCK+ 2/fMCK+ 75 110 110 110 2/fMCK+ 2/fMCK+ 2/fMCK+ 2/fMCK+ 100 110 110 110 2/fMCK+ 2/fMCK+ 2/fMCK+ 2/fMCK+ 220 220 220 220 2/fMCK+ 2/fMCK+ 2/fMCK+ 220 220 220 1.7 V ≤ EVDD ≤ 5.5 V ns ns ns ns ns (Notes, Caution, and Remarks are listed on the next page.) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 43 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. C is the load capacitance of the SOp output lines. 4. Transfer rate in the SNOOZE mode: MAX. 1 Mbps 5. Either V DD or VBAT is selected by the battery backup function. Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 10, 30), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM number (g = 0, 1, 8) 2. fMCK: Serial array unit operation clock frequency (Operating clock that is set with the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 10, 30)) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 44 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS CSI mode connection diagram (during communication at same potential) SCKp SCK RL78/I1C SIp microcontrollers SO SOp User’s device SI CSI mode serial transfer timing (during communication at same potential) (when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1) tKCY1, 2 tKL1, 2 tKH1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 Output data SOp CSI mode serial transfer timing (during communication at same potential) (when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0) tKCY1, 2 tKH1, 2 tKL1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 SOp Remarks 1. 2. Output data p: CSI number (p = 00, 10, 30) m: Unit number, n: Channel number (mn = 00, 10, 30) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 45 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (4) During communication at same potential (simplified I2C mode) (TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 3 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) LS (low-speed LP (low-power LV (low-voltage Mode main) Mode main) Mode main) Mode MIN. SCLr clock fSCL (1/2) 2.7 V ≤ EVDD ≤ 5.5 V, MAX. MIN. MAX. MIN. Note 1 MAX. MIN. MAX. 400 Note 1 400 400Note 1 kHz 400Note 1 400Note 1 400Note 1 400Note 1 kHz 300Note 1 300Note 1 300Note 1 300Note 1 kHz 250Note 1 250Note 1 250Note 1 250Note 1 kHz 250Note 1 250Note 1 250Note 1 kHz 1000 Note 1 Unit Cb = 50 pF, Rb = 2.7 kΩ frequency 1.9 V ≤ EVDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1.9 V ≤ EVDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1.8 V ≤ EVDD < 1.9 V, Cb = 100 pF, Rb = 5 kΩ 1.7 V ≤ EVDD < 1.9 V, Cb = 100 pF, Rb = 5 kΩ Hold time tLOW 2.7 V ≤ EVDD ≤ 5.5 V, when SCLr = Cb = 50 pF, Rb = 2.7 kΩ “L” 1.9 V ≤ EVDD ≤ 5.5 V, 475 1150 1150 1150 ns 1150 1150 1150 1150 ns 1550 1550 1550 1550 ns 1850 1850 1850 1850 ns 1850 1850 1850 ns 475 1150 1150 1150 ns 1150 1150 1150 1150 ns 1550 1550 1550 1550 ns 1850 1850 1850 1850 ns 1850 1850 1850 ns ns Cb = 100 pF, Rb = 3 kΩ 1.9 V ≤ EVDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1.8 V ≤ EVDD < 1.9 V, Cb = 100 pF, Rb = 5 kΩ 1.7 V ≤ EVDD < 1.9 V, Cb = 100 pF, Rb = 5 kΩ Hold time tHIGH 2.7 V ≤ EVDD ≤ 5.5 V, when SCLr = Cb = 50 pF, Rb = 2.7 kΩ “H” 1.9 V ≤ EVDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1.9 V ≤ EVDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1.8 V ≤ EVDD < 1.9 V, Cb = 100 pF, Rb = 5 kΩ 1.7 V ≤ EVDD < 1.9 V, Cb = 100 pF, Rb = 5 kΩ Data setup time (reception) tSU:DAT 2.7 V ≤ EVDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1.9 V ≤ EVDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1.9 V ≤ EVDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1.8 V ≤ EVDD < 1.9 V, Cb = 100 pF, Rb = 5 kΩ 1/fMCK + 1/fMCK + 1/fMCK + 1/fMCK + 85Notes 1, 2 145Notes 1, 2 145Notes 1, 2 145Notes 1, 2 1/fMCK + 1/fMCK + 1/fMCK + 1/fMCK + 145Notes 1, 2 145Notes 1, 2 145Notes 1, 2 145Notes 1, 2 1/fMCK + 1/fMCK + 1/fMCK + 1/fMCK + 230Notes 1, 2 230Notes 1, 2 230Notes 1, 2 230Notes 1, 2 1/fMCK + 1/fMCK + 1/fMCK + 1/fMCK + 290Notes 1, 2 290Notes 1, 2 290Notes 1, 2 290Notes 1, 2 1.7 V ≤ EVDD < 1.9 V, 1/fMCK + 1/fMCK + 1/fMCK + Cb = 100 pF, Rb = 5 kΩ 290Notes 1, 2 290Notes 1, 2 290Notes 1, 2 ns ns ns ns (Notes, Caution, and Remarks are listed on the next page.) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 46 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 3 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Data hold tHD:DAT Conditions (2/2) HS (high-speed LS (low-speed LP (low-power LV (low-voltage main) Mode main) Mode main) Mode main) Mode Unit MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. 0 305 0 305 0 305 0 305 ns 0 355 0 355 0 355 0 355 ns 0 405 0 405 0 405 0 405 ns 0 405 0 405 0 405 0 405 ns 0 405 0 405 0 405 ns 2.7 V ≤ EVDD ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ time (transmission) 1.9 V ≤ EVDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1.9 V ≤ EVDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1.8 V ≤ EVDD < 1.9 V, Cb = 100 pF, Rb = 5 kΩ 1.7 V ≤ EVDD < 1.9 V, Cb = 100 pF, Rb = 5 kΩ Notes 1. The value must also be equal to or less than fMCK/4. 2. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”. 3. Either V DD or VBAT is selected by the battery backup function. Simplified I2C mode connection diagram (during communication at same potential) VDD Rb SDAr SDA RL78/I1C microcontrollers User’s device SCLr SCL Simplified I2C mode serial transfer timing (during communication at same potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD:DAT Caution tSU:DAT Select the normal input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. Rb[Ω]:Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance 2. r: IIC number (r = 00, 10, 30), g: PIM and POM number (g = 0, 1, 8) 3. fMCK: Serial array unit operation clock frequency (Operating clock that is set with the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 00, 02, 12)) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 47 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (5) Communication at different potential (1.9 V, 2.5 V, 3 V) (UART mode) (1/2) (TA = –40 to +85°C, 1.9 V ≤ EVDD0 = EVDD1 ≤ VDDNote 1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LP (low-power LV (low-voltage main) Mode main) Mode main) Mode main) Mode MIN. Reception Transfer rate 4.0 V ≤ EVDD ≤ 5.5 V, MAX. fMCK/6 Note 1 MIN. MAX. fMCK/6 MIN. Note 1 MAX. fMCK/6 MIN. Note 1 Unit MAX. fMCK/6Note 1 bps 2.7 V ≤ Vb ≤ 4.0 V Theoretical value of 5.3 1.3 0.1 0.6 Mbps fMCK/6Note 1 fMCK/6Note 1 fMCK/6Note 1 fMCK/6Note 1 bps 5.3 1.3 0.1 0.6 Mbps bps the maximum transfer rate fMCK = fCLKNote 4 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V Theoretical value of the maximum transfer rate fMCK = fCLKNote 4 1.9 V ≤ EVDD < 3.3 V, 1.8 V ≤ Vb ≤ 2.0 V Theoretical value of fMCK/6 fMCK/6 fMCK/6 fMCK/6 Notes 1 to 3 Notes 1, 2 Notes 1, 2 Notes 1, 2 5.3 1.3 0.1 0.6 Mbps the maximum transfer rate fMCK = fCLKNote 4 Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only. 2. Use it with EVDD ≥ Vb. 3. The following conditions are required for low voltage interface. 2.4 V ≤ EVDD < 2.7 V: MAX. 2.6 Mbps 1.9 V ≤ EVDD < 2.4 V: MAX. 1.3 Mbps 4. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 32 MHz (2.8 V ≤ EVDD ≤ 5.5 V), 24 MHz (2.7 V ≤ EVDD ≤ 5.5 V), 16 MHz (2.5 V ≤ EVDD ≤ 5.5 V), 12 MHz (2.4 V ≤ EVDD ≤ 5.5 V), 6 MHz (2.1 V ≤ EVDD ≤ 5.5 V), Caution LS (low-speed main) mode: 8 MHz (1.9 V ≤ EVDD ≤ 5.5 V), 4 MHz (1.9 V ≤ EVDD ≤ 5.5 V) LP (low-power main) mode: 1 MHz (1.9 V ≤ EVDD ≤ 5.5 V) LV (low-voltage main) mode: 4 MHz (1.7 V ≤ EVDD ≤ 5.5 V) Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. Vb[V]: Communication line voltage 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 3, 5, 8) 3. fMCK: Serial array unit operation clock frequency (Operating clock that is set with the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 48 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2) (TA = –40 to +85°C, 1.9 V ≤ EVDD0 = EVDD1 ≤ VDDNote 10 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LP (low-power LV (low-voltage main) Mode main) Mode main) Mode main) Mode Transfer rate Transmission MIN. MAX. 4.0 V ≤ EVDD ≤ 5.5 V, MAX. MIN. MAX. MIN. MAX. Notes Notes Notes Notes 1, 2 1, 2 1, 2 1, 2 2.8Note 3 2.8Note 3 2.8Note 3 2.8Note 3 Mbps Notes Notes Notes Notes 2, 4 2, 4 2, 4 2, 4 1.2Note 5 1.2Note 5 1.2Note 5 2.7 V ≤ Vb ≤ 4.0 V Theoretical value of MIN. Unit bps the maximum transfer rateNote 9 Cb = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V Theoretical value of bps 1.2Note 5 Mbps the maximum transfer rateNote 9 Cb = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V 1.9 V ≤ EVDD < 3.3 V, Notes Notes Notes Notes 1.6 V ≤ Vb ≤ 2.0 V 2, 6, 7 2, 6, 7 2, 6, 7 2, 6, 7 0.43Note 8 0.43Note 8 0.43Note 8 Theoretical value of bps 0.43Note 8 Mbps the maximum transfer rateNote 9 Cb = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V Notes 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V ≤ EVDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V 1 Maximum transfer rate = {–Cb × Rb × ln (1 – Baud rate error (theoretical value) = 2.2 Vb )} × 3 [bps] 2.2 1 Transfer rate × 2 – {–Cb × Rb × ln (1 – Vb )} 1 ( Transfer rate ) × Number of transferred bits × 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 2. 3. Transfer rate in the SNOOZE mode is 4800 bps only. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. 4. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V ≤ EVDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V 1 Maximum transfer rate = {–Cb × Rb × ln (1 – Baud rate error (theoretical value) = 2.0 Vb )} × 3 [bps] 2.0 1 Transfer rate × 2 – {–Cb × Rb × ln (1 – Vb )} 1 ( Transfer rate ) × Number of transferred bits × 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 49 of 89 RL78/I1C Notes 5. 2. ELECTRICAL SPECIFICATIONS This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer. 6. Use it with EVDD ≥ Vb. 7. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.9 V ≤ EVDD < 2.7 V and 1.6 V ≤ Vb ≤ 2.0 V 1 Maximum transfer rate = {–Cb × Rb × ln (1 – Baud rate error (theoretical value) = 1.5 Vb )} × 3 [bps] 1.5 1 Transfer rate × 2 – {–Cb × Rb × ln (1 – Vb )} 1 ( Transfer rate ) × Number of transferred bits × 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 8. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 7 above to calculate the maximum transfer rate under conditions of the customer. 9. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 32 MHz (2.8 V ≤ EVDD ≤ 5.5 V), 24 MHz (2.7 V ≤ EVDD ≤ 5.5 V), 16 MHz (2.5 V ≤ EVDD ≤ 5.5 V), 12 MHz (2.4 V ≤ EVDD ≤ 5.5 V), 6 MHz (2.1 V ≤ EVDD ≤ 5.5 V), LS (low-speed main) mode: 8 MHz (1.9 V ≤ EVDD ≤ 5.5 V), 4 MHz (1.9 V ≤ EVDD ≤ 5.5 V) LP (low-power main) mode: 1 MHz (1.9 V ≤ EVDD ≤ 5.5 V) LV (low-voltage main) mode: 4 MHz (1.7 V ≤ EVDD ≤ 5.5 V) 10. Either V DD or VBAT is selected by the battery backup function. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. Rb[Ω]:Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 3, 5, 8) 3. fMCK: Serial array unit operation clock frequency (Operating clock that is set with the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) UART mode connection diagram (during communication at different potential) Vb Rb TxDq Rx RL78/I1C microcontrollers RxDq R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 User’s device Tx Page 50 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. 2. Rb[Ω]:Communication line (TxDq) pull-up resistance, Vb[V]: Communication line voltage q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 3, 5, 8) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 51 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (6) Communication at different potential (2.5 V, 3 V) (fMCK/2) (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (1/2) (TA = –40 to +85°C, 2.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 3 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions SCKp cycle tKCY1 tKCY1 ≥ 4.0 V ≤ EVDD ≤ 5.5 V, time 2/fCLK HS (high-speed LS (low-speed LP (low-power LV (low-voltage main) Mode main) Mode main) Mode main) Mode MIN. MIN. MIN. MIN. MAX. MAX. MAX. Unit MAX. 200 1150 1150 1150 ns 300 1150 1150 1150 ns ns 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ SCKp high- tKH1 level width 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/ tKCY1/ tKCY1/ tKCY1/ 2 – 50 2 – 50 2 – 50 2 – 50 Cb = 20 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/ tKCY1/ tKCY1/ tKCY1/ 2 – 120 2 – 120 2 – 120 2 – 120 ns Cb = 20 pF, Rb = 2.7 kΩ SCKp low- tKL1 level width 4.0 V ≤ EVDD ≤ 5.5 V, tKCY1/ tKCY1/ tKCY1/ tKCY1/ 2.7 V ≤ Vb ≤ 4.0 V, 2–7 2 – 50 2 – 50 2 – 50 ns Cb = 20 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/ tKCY1/ tKCY1/ tKCY1/ 2 – 10 2 – 50 2 – 50 2 – 50 58 479 479 479 ns 121 479 479 479 ns 10 10 10 10 ns 10 10 10 10 ns ns Cb = 20 pF, Rb = 2.7 kΩ SIp setup tSIK1 4.0 V ≤ EVDD ≤ 5.5 V, time (to 2.7 V ≤ Vb ≤ 4.0 V, SCKp↑)Note 1 Cb = 20 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ SIp hold tKSI1 4.0 V ≤ EVDD ≤ 5.5 V, time (from 2.7 V ≤ Vb ≤ 4.0 V, SCKp↑)Note 1 Cb = 20 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ Delay time tKSO1 4.0 V ≤ EVDD ≤ 5.5 V, from SCKp↓ 2.7 V ≤ Vb ≤ 4.0 V, to SOp Cb = 20 pF, Rb = 1.4 kΩ outputNote 1 2.7 V ≤ EVDD < 4.0 V, 60 60 60 60 ns 130 130 130 130 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ SIp setup tSIK1 4.0 V ≤ EVDD ≤ 5.5 V, time (to 2.7 V ≤ Vb ≤ 4.0 V, SCKp↓)Note 2 Cb = 20 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 23 110 110 110 ns 33 110 110 110 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ (Notes, Caution, and Remarks are listed on the next page.) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 52 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (6) Communication at different potential (2.5 V, 3 V) (fMCK/2) (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (2/2) (TA = –40 to +85°C, 2.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 3 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LP (low-power LV (low-voltage main) Mode main) Mode main) Mode main) Mode MIN. tKSI1 SIp hold 4.0 V ≤ EVDD ≤ 5.5 V, time (from 2.7 V ≤ Vb ≤ 4.0 V, SCKp↓)Note 2 Cb = 20 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, MAX. MIN. MAX. MIN. MAX. MIN. Unit MAX. 10 10 10 10 ns 10 10 10 10 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ Delay time tKSO1 4.0 V ≤ EVDD ≤ 5.5 V, from SCKp↑ 2.7 V ≤ Vb ≤ 4.0 V, to SOp Cb = 20 pF, Rb = 1.4 kΩ outputNote 2 2.7 V ≤ EVDD < 4.0 V, 10 10 10 10 ns 10 10 10 10 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. Either V DD or VBAT is selected by the battery backup function. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. CSI mode connection diagram (during communication at different potential) Vb Rb Vb Rb SCKp RL78/I1C SIp microcontrollers SOp SCK SO User’s device SI Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 10, 30), m: Unit number, n: Channel number (mn = 00, 02, 10), g: PIM and POM number (g = 0, 1, 8) 3. fMCK: Serial array unit operation clock frequency (Operating clock that is set with the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 02, 12)) 4. This specification is valid only when CSI00’s peripheral I/O redirect function is not used. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 53 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (7) Communication at different potential (1.8 V, 2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock output) (1/2) (TA = –40 to +85°C, 1.9 V ≤ EVDD0 = EVDD1 ≤ VDDNote 4 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter SCKp cycle Symbol tKCY1 time Conditions tKCY1 ≥ 4.0 V ≤ EVDD ≤ 5.5 V, 4/fCLK 2.7 V ≤ Vb ≤ 4.0 V, HS (high-speed LS (low-speed LP (low-power LV (low-voltage Unit main) Mode main) Mode main) Mode main) Mode MIN. MIN. MIN. MIN. MAX. MAX. MAX. MAX. 300 1150 1150 1150 ns 500 1150 1150 1150 ns 1150 1150 1150 1150 ns ns Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 1.9 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ SCKp high- tKH1 level width 4.0 V ≤ EVDD ≤ 5.5 V, tKCY1/ tKCY1/ tKCY1/ tKCY1/ 2.7 V ≤ Vb ≤ 4.0 V, 2 – 75 2 – 75 2 – 75 2 – 75 Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/ tKCY1/ tKCY1/ tKCY1/ 2 – 170 2 – 170 2 – 170 2 – 170 ns Cb = 30 pF, Rb = 2.7 kΩ 1.9 VNote 4 ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3 , tKCY1/ tKCY1/ tKCY1/ tKCY1/ 2 – 458 2 – 458 2 – 458 2 – 458 ns Cb = 30 pF, Rb = 5.5 kΩ SCKp low- tKL1 level width 4.0 V ≤ EVDD ≤ 5.5 V, tKCY1/ tKCY1/ tKCY1/ tKCY1/ 2.7 V ≤ Vb ≤ 4.0 V, 2 – 12 2 – 50 2 – 50 2 – 50 ns Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, tKCY1/ tKCY1/ tKCY1/ tKCY1/ 2.3 V ≤ Vb ≤ 2.7 V, 2 – 18 2 – 50 2 – 50 2 – 50 ns Cb = 30 pF, Rb = 2.7 kΩ 1.9 VNote 4 ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3 , tKCY1/ tKCY1/ tKCY1/ tKCY1/ 2 – 50 2 – 50 2 – 50 2 – 50 81 479 479 479 ns 177 479 479 479 ns 479 479 479 479 ns ns Cb = 30 pF, Rb = 5.5 kΩ SIp setup tSIK1 4.0 V ≤ EVDD ≤ 5.5 V, time (to 2.7 V ≤ Vb ≤ 4.0 V, SCKp↑)Note 1 Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 1.9 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 3, Cb = 30 pF, Rb = 5.5 kΩ (Notes, Caution and Remarks are listed on the page after the next page.) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 54 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (7) Communication at different potential (1.8 V, 2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock output) (2/2) (TA = –40 to +85°C, 1.9 V ≤ EVDD0 = EVDD1 ≤ VDDNote 4 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LP (low-power main) Mode main) Mode main) Mode MIN. SIp hold tKSI1 4.0 V ≤ EVDD ≤ 5.5 V, time (from 2.7 V ≤ Vb ≤ 4.0 V, SCKp↑)Note 1 Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, MAX. MIN. MAX. MIN. MAX. LV (low-voltage Unit main) Mode MIN. MAX. 19 19 19 19 ns 19 19 19 19 ns 19 19 19 19 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 1.9 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 3, Cb = 30 pF, Rb = 5.5 kΩ Delay time tKSO1 4.0 V ≤ EVDD ≤ 5.5 V, from SCKp↓ 2.7 V ≤ Vb ≤ 4.0 V, to Cb = 30 pF, Rb = 1.4 kΩ SOp 2.7 V ≤ EVDD < 4.0 V, outputNote 1 100 100 100 100 ns 195 195 195 195 ns 483 483 483 483 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 1.9 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 3, Cb = 30 pF, Rb = 5.5 kΩ SIp setup tSIK1 4.0 V ≤ EVDD ≤ 5.5 V, time (to 2.7 V ≤ Vb ≤ 4.0 V, SCKp↓)Note 2 Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 44 110 110 110 ns 44 110 110 110 ns 110 110 110 110 ns 19 19 19 19 ns 19 19 19 19 ns 19 19 19 19 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 1.9 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 3, Cb = 30 pF, Rb = 5.5 kΩ SIp hold tKSI1 4.0 V ≤ EVDD ≤ 5.5 V, time (from 2.7 V ≤ Vb ≤ 4.0 V, SCKp↓)Note 2 Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 1.9 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 3, Cb = 30 pF, Rb = 5.5 kΩ Delay time tKSO1 4.0 V ≤ EVDD ≤ 5.5 V, from SCKp↑ 2.7 V ≤ Vb ≤ 4.0 V, to SOp Cb = 30 pF, Rb = 1.4 kΩ outputNote 2 2.7 V ≤ EVDD < 4.0 V, 25 25 25 25 ns 25 25 25 25 ns 25 25 25 25 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 1.9 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 3, Cb = 30 pF, Rb = 5.5 kΩ (Notes, Caution and Remarks are listed on the next page.) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 55 of 89 RL78/I1C Notes 1. 2. ELECTRICAL SPECIFICATIONS When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. Use it with EVDD ≥ Vb. 4. Either V DD or VBAT is selected by the battery backup function. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 10, 30), m: Unit number , n: Channel number (mn = 00, 02, 10), g: PIM and POM number (g = 0, 1, 8) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 02, 12)) CSI mode connection diagram (during communication at different potential) Vb Vb Rb Rb SCKp SCK RL78/I1C SIp microcontrollers SO SOp User’s device SI CSI mode serial transfer timing (master mode) (during communication at different potential) (when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1) tKCY1 tKL1 tKH1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 SOp R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Output data Page 56 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS CSI mode serial transfer timing (master mode) (during communication at different potential) (when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0) tKCY1 tKL1 tKH1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 SOp Output data Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remark p: CSI number (p = 00, 10, 30), m: Unit number, n: Channel number (mn = 00, 02, 10), g: PIM and POM number (g = 0, 1, 8) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 57 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp ... external clock input) (TA = –40 to +85°C, 1.9 V ≤ EVDD0 = EVDD1 ≤ VDDNote 5 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Parameter Symb Conditions ol HS (high-speed LS (low-speed LP (low-power LV (low-voltage main) Mode main) Mode main) Mode main) Mode MIN. SCKp cycle tKCY2 timeNote 1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V MAX. MIN. MAX. MIN. MAX. MIN. Unit MAX. 24 MHz < fMCK 14/fMCK – – – ns 20 MHz < fMCK ≤ 12/fMCK – – – ns 10/fMCK – – – ns 8/fMCK 16/fMCK – – ns 24 MHz 8 MHz < fMCK ≤ 20 MHz 4 MHz < fMCK ≤ 8 MHz 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V fMCK ≤ 4 MHz 6/fMCK 10/fMCK 10/fMCK 10/fMCK ns 24 MHz < fMCK 20/fMCK – – – ns 20 MHz < fMCK ≤ 16/fMCK – – – ns 14/fMCK – – – ns 12/fMCK – – – ns 8/fMCK 16/fMCK – – ns fMCK ≤ 4 MHz 6/fMCK 10/fMCK 10/fMCK 10/fMCK ns 24 MHz < fMCK 48/fMCK – – – ns 36/fMCK – – – ns 32/fMCK – – – ns 26/fMCK – – – ns 16/fMCK 16/fMCK – – ns 10/fMCK 10/fMCK 10/fMCK 10/fMCK ns ns 24 MHz 16 MHz < fMCK ≤ 20 MHz 8 MHz < fMCK ≤ 16 MHz 4 MHz < fMCK ≤ 8 MHz 1.9 V ≤ EVDD 20 MHz < fMCK ≤ < 3.3 V, 24 MHz 1.6 V ≤ 16 MHz < fMCK ≤ Vb ≤ 2.0 20 MHz VNote 2 8 MHz < fMCK ≤ 16 MHz 4 MHz < fMCK ≤ 8 MHz fMCK ≤ 4 MHz SCKp high- tKH2, 4.0 V ≤ EVDD ≤ 5.5 V, tKCY2/ tKCY2/ tKCY2/ tKCY2/ /low-level tKL2 2.7 V ≤ Vb ≤ 4.0 V 2 – 12 2 – 50 2 – 50 2 – 50 width tSIK2 2.7 V ≤ EVDD < 4.0 V, tKCY2/ tKCY2/ tKCY2/ tKCY2/ 2.3 V ≤ Vb ≤ 2.7 V 2 – 18 2 – 50 2 – 50 2 – 50 1.9 V ≤ EVDD < 3.3 V, tKCY2/ tKCY2/ tKCY2/ tKCY2/ 1.6 V ≤ Vb ≤ 2.0 VNote 2 2 – 50 2 – 50 2 – 50 2 – 50 2.7 V ≤ EVDD ≤ 5.5 V, 1/fMCK 1/fMCK 1/fMCK + 1/fMCK + time (to 2.3 V ≤ Vb ≤ 4.0 VNote 2 + 20 + 30 30 30 SCKp↑)Note 3 1.9 V ≤ EVDD < 3.3 V, 1/fMCK 1/fMCK 1/fMCK + 1/fMCK + 1.6 V ≤ Vb ≤ 2.0 VNote 2 + 30 + 30 30 30 SIp setup tKSI2 2.7 V ≤ EVDD ≤ 5.5 V, 1/fMCK + 1/fMCK + 1/fMCK + 1/fMCK + time (from 2.3 V ≤ Vb ≤ 4.0 VNote 2 31 31 31 31 SCKp↑)Note 3 1.9 V ≤ EVDD < 3.3 V, 1/fMCK + 1/fMCK + 1/fMCK + 1/fMCK + 1.6 V ≤ Vb ≤ 2.0 VNote 2 31 31 31 31 SIp hold ns ns ns ns ns ns (Notes, Caution and Remarks are listed on the next page.) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 58 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp ... external clock input) (TA = –40 to +85°C, 1.9 V ≤ EVDD0 = EVDD1 ≤ VDDNote 5 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Parameter Symbol Conditions HS (high-speed LS (low-speed LP (low-power LV (low-voltage main) Mode main) Mode main) Mode main) Mode MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. 4.0 V ≤ EVDD ≤ 5.5 V, 2/fMCK 2/fMCK 2/fMCK 2/fMCK from 2.7 V ≤ Vb ≤ 4.0 V, + 120 + 573 + 573 + 573 SCKp↓ to Cb = 30 pF, Rb = 1.4 kΩ Delay time SOp outputNote 4 tKSO2 Unit 2.7 V ≤ EVDD < 4.0 V, 2/fMCK 2/fMCK 2/fMCK 2/fMCK 2.3 V ≤ Vb ≤ 2.7 V, + 214 + 573 + 573 + 573 ns ns Cb = 30 pF, Rb = 2.7 kΩ 1.9 V ≤ EVDD < 3.3 V, 2/fMCK 2/fMCK 2/fMCK 2/fMCK 1.6 V ≤ Vb ≤ 2.0 VNote 2, + 573 + 573 + 573 + 573 ns Cb = 30 pF, Rb = 5.5 kΩ Notes 1. Transfer rate in the SNOOZE mode: MAX. 1 Mbps 2. Use it with EVDD ≥ Vb. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 5. Either V DD or VBAT is selected by the battery backup function. Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. CSI mode connection diagram (during communication at different potential) Vb Rb SCKp SIp RL78/I1C microcontrollers SOp SCK SO User’s device SI Remarks 1. Rb[Ω]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 10, 30), m: Unit number, n: Channel number (mn = 00, 02, 10), g: PIM and POM number (g = 0, 1, 8) 3. fMCK: Serial array unit operation clock frequency (Operating clock that is set with the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 02, 12)) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 59 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS CSI mode serial transfer timing (slave mode) (during communication at different potential) (when DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1) tKCY2 tKL2 tKH2 SCKp tSIK2 SIp tKSI2 Input data tKSO2 Output data SOp CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY2 tKL2 tKH2 SCKp tSIK2 SIp tKSI2 Input data tKSO2 SOp Output data Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remark p: CSI number (p = 00, 10, 30), m: Unit number, n: Channel number (mn = 00, 02, 12), g: PIM and POM number (g = 0, 1, 8) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 60 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (9) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (1/2) (TA = –40 to +85°C, 1.9 V ≤ EVDD0 = EVDD1 ≤ VDDNote 4 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LP (low-power LV (low-voltage main) Mode main) Mode main) Mode main) Mode MIN. SCLr clock frequency fSCL MAX. 1000 4.0 V ≤ EVDD ≤ 5.5 V, MIN. Note 1 MAX. 300 MIN. Note 1 MAX. 300 MIN. Unit MAX. Note 1 300Note 1 kHz 2.7 V ≤ Vb ≤ 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 2.7 V ≤ EVDD < 4.0 V, 1000Note 1 300Note 1 300Note 1 300Note 1 kHz 400Note 1 300Note 1 300Note 1 300Note 1 kHz 400Note 1 300Note 1 300Note 1 300Note 1 kHz 300Note 1 300Note 1 300Note 1 300Note 1 kHz 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 1.9 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 100 pF, Rb = 5.5 kΩ Hold time when SCLr = “L” tLOW 4.0 V ≤ EVDD ≤ 5.5 V, 475 1550 1550 1550 ns 475 1550 1550 1550 ns 1150 1150 1150 1150 ns 1150 1150 1150 1150 ns 1150 1150 1150 1150 ns 245 610 610 610 ns 200 610 610 610 ns 675 610 610 610 ns 600 610 610 610 ns 610 610 610 610 ns 2.7 V ≤ Vb ≤ 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 1.9 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2 , Cb = 100 pF, Rb = 5.5 kΩ Hold time when SCLr = “H” tHIGH 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 1.9 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2 , Cb = 100 pF, Rb = 5.5 kΩ (Notes, Caution and Remarks are listed on the next page.) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 61 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (9) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2) (TA = –40 to +85°C, 1.9 V ≤ EVDD0 = EVDD1 ≤ VDDNote 4 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LP (low-power LV (low-voltage main) Mode main) Mode main) Mode main) Mode MIN. Data setup time (reception) tSU:DAT Data hold tHD:DAT time (transmission) MAX. MIN. MAX. MIN. MAX. MIN. Unit MAX. ns 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK + 135Note 3 1/fMCK + 190Note 3 1/fMCK + 1/fMCK + 190Note 3 190Note 3 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK + 135Note 3 1/fMCK + 190Note 3 1/fMCK + 1/fMCK + 190Note 3 190Note 3 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 1/fMCK + 190Note 3 1/fMCK + 190Note 3 1/fMCK + 1/fMCK + 190Note 3 190Note 3 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 1/fMCK + 190Note 3 1/fMCK + 190Note 3 1/fMCK + 1/fMCK + 190Note 3 190Note 3 1.9 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 100 pF, Rb = 5.5 kΩ 1/fMCK + 190Note 3 1/fMCK + 190Note 3 1/fMCK + 1/fMCK + Note 3 Note 3 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 0 305 0 305 0 305 0 305 ns 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 0 305 0 305 0 305 0 305 ns 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 0 355 0 355 0 355 0 355 ns 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 0 355 0 355 0 355 0 355 ns 1.9 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 VNote 2, Cb = 100 pF, Rb = 5.5 kΩ 0 405 0 405 0 405 0 405 ns 190 190 ns ns ns ns Notes 1. The value must also be equal to or less than fMCK/4. 2. Use it with EVDD ≥ Vb. 3. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”. 4. Either V DD or VBAT is selected by the battery backup function. Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 62 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS Simplified I2C mode connection diagram (during communication at different potential) Vb Rb Vb Rb SDAr SDA RL78/I1C microcontrollers User’s device SCLr SCL Simplified I2C mode serial transfer timing (during communication at different potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD:DAT Caution tSU:DAT Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. Rb[Ω]:Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage 2. r: IIC number (r = 00, 10, 30), g: PIM, POM number (g = 0, 1, 8) 3. fMCK: Serial array unit operation clock frequency (Operating clock that is set with the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 02, 12)) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 63 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS 2.5.2 Serial interface IICA (1) I2C standard mode (1/2) (TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 3 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter SCLA0 clock Symbol fSCL frequency Conditions Standard 2.7 V ≤ EVDD mode: ≤ 5.5 V fCLK ≥ 1 1.9 V ≤ EVDD MHz ≤ 5.5 V 1.8 V ≤ EVDD HS (high-speed LS (low-speed LP (low-power LV (low-voltage main) Mode main) Mode main) Mode main) Mode Unit MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. 0 100 0 100 0 100 0 100 kHz 0 100 0 100 0 100 0 100 kHz 0 100 0 100 0 100 0 100 kHz – – 0 100 0 100 0 100 kHz ≤ 5.5 V 1.7 V ≤ EVDD ≤ 5.5 V Setup time of tSU:STA restart condition Hold timeNote 1 tHD:STA 2.7 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 4.7 µs 1.9 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 4.7 µs 1.8 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 4.7 µs 1.7 V ≤ EVDD ≤ 5.5 V – 4.7 4.7 4.7 µs 2.7 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 4.0 µs 1.9 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 4.0 µs 1.8 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 4.0 µs 1.7 V ≤ EVDD ≤ 5.5 V – 4.0 4.0 4.0 µs – – 2.7 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 4.7 µs 1.9 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 4.7 µs 1.8 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 4.7 µs 1.7 V ≤ EVDD ≤ 5.5 V – 4.7 4.7 4.7 µs 2.7 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 4.0 µs 1.9 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 4.0 µs 1.8 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 4.0 µs 1.7 V ≤ EVDD ≤ 5.5 V – 4.0 4.0 4.0 µs 2.7 V ≤ EVDD ≤ 5.5 V 250 250 250 250 µs 1.9 V ≤ EVDD ≤ 5.5 V 250 250 250 250 µs 1.8 V ≤ EVDD ≤ 5.5 V 250 250 250 250 µs 1.7 V ≤ EVDD ≤ 5.5 V – – 250 250 250 µs Data hold time tHD:DAT 2.7 V ≤ EVDD ≤ 5.5 V 0 3.45 0 3.45 0 3.45 0 3.45 µs (transmission) 1.9 V ≤ EVDD ≤ 5.5 V 0 3.45 0 3.45 0 3.45 0 3.45 µs 1.8 V ≤ EVDD ≤ 5.5 V 0 3.45 0 3.45 0 3.45 0 3.45 µs 1.7 V ≤ EVDD ≤ 5.5 V – – 0 3.45 0 3.45 0 3.45 µs Hold time tLOW when SCLA0 = “L” Hold time tHIGH when SCLA0 = “H” Data setup tSU:DAT time (reception) Note 2 – – (Notes and Remark are listed on the next page.) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 64 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (1) I2C standard mode (2/2) (TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 3 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LP (low-power LV (low-voltage main) Mode main) Mode main) Mode main) Mode MIN. Setup time of tSU:STO stop condition Bus-free time Notes 1. 2. 3. Remark tBUF MAX. MIN. MAX. MIN. MAX. MIN. Unit MAX. 2.7 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 4.0 µs 1.9 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 4.0 µs 1.8 V ≤ EVDD ≤ 5.5 V 4.0 4.0 4.0 4.0 µs 4.0 4.0 4.0 µs 1.7 V ≤ EVDD ≤ 5.5 V – 2.7 V ≤ EVDD ≤ 5.5 V – 4.7 4.7 4.7 4.7 µs 1.9 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 4.7 µs 1.8 V ≤ EVDD ≤ 5.5 V 4.7 4.7 4.7 4.7 µs 1.7 V ≤ EVDD ≤ 5.5 V – 4.7 4.7 4.7 µs – The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Either V DD or VBAT is selected by the battery backup function. The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 kΩ R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 65 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (2) I2C fast mode (TA = –40 to +85°C, 1.9 V ≤ EVDD0 = EVDD1 ≤ VDDNote 3 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol SCLA0 clock fSCL frequency Setup time of tSU:STA restart Conditions Fast mode: fCLK ≥ 3.5 MHz Hold time tLOW when SCLA0 LS (low-speed LP (low-power LV (low-voltage main) Mode main) Mode main) Mode main) Mode Unit MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. 2.7 V ≤ EVDD ≤ 5.5 V 0 400 0 400 – – 0 400 kHz 1.9 V ≤ EVDD 0 400 0 400 – – 0 400 kHz ≤ 5.5 V 2.7 V ≤ EVDD ≤ 5.5 V 0.6 0.6 – – 0.6 µs 1.9 V ≤ EVDD ≤ 5.5 V 0.6 0.6 – – 0.6 µs 2.7 V ≤ EVDD ≤ 5.5 V 0.6 0.6 – – 0.6 µs 1.9 V ≤ EVDD ≤ 5.5 V 0.6 0.6 – – 0.6 µs 2.7 V ≤ EVDD ≤ 5.5 V 1.3 1.3 – – 1.3 µs 1.9 V ≤ EVDD ≤ 5.5 V 1.3 1.3 – – 1.3 µs condition Hold timeNote 1 tHD:STA HS (high-speed = “L” 2.7 V ≤ EVDD ≤ 5.5 V 0.6 0.6 – – 0.6 µs 1.9 V ≤ EVDD ≤ 5.5 V 0.6 0.6 – – 0.6 µs 2.7 V ≤ EVDD ≤ 5.5 V 100 100 – – 100 ns 1.9 V ≤ EVDD ≤ 5.5 V 100 100 – – 100 ns Data hold time tHD:DAT 2.7 V ≤ EVDD ≤ 5.5 V 0 0.9 0 0.9 – – 0 0.9 µs (transmission) 1.9 V ≤ EVDD ≤ 5.5 V 0 0.9 0 0.9 – – 0 0.9 µs 2.7 V ≤ EVDD ≤ 5.5 V 0.6 0.6 – – 0.6 µs 1.9 V ≤ EVDD ≤ 5.5 V 0.6 0.6 – – 0.6 µs 2.7 V ≤ EVDD ≤ 5.5 V 1.3 1.3 – – 1.3 µs 1.9 V ≤ EVDD ≤ 5.5 V 1.3 1.3 – – 1.3 µs Hold time tHIGH when SCLA0 = “H” Data setup tSU:DAT time (reception) Note 2 Setup time of tSU:STO stop condition Bus-free time Notes 1. 2. 3. Remark tBUF The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Either V DD or VBAT is selected by the battery backup function. The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Fast mode: Cb = 320 pF, Rb = 1.1 kΩ R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 66 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (3) I2C fast mode plus (TA = –40 to +85°C, 2.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 3 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol SCLA0 clock Conditions Fast mode plus: fCLK ≥ 10 MHz fSCL frequency Setup time of restart tSU:STA 2.7 V ≤ EVDD HS (high-speed LS (low-speed LP (low-power LV (low-voltage main) Mode main) Mode main) Mode main) Mode Unit MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. 0 1000 – – – – – – kHz ≤ 5.5 V 2.7 V ≤ EVDD ≤ 5.5 V 0.26 – – – – – – µs condition Hold timeNote 1 tHD:STA 2.7 V ≤ EVDD ≤ 5.5 V 0.26 – – – – – – µs Hold time when tLOW 2.7 V ≤ EVDD ≤ 5.5 V 0.5 – – – – – – µs tHIGH 2.7 V ≤ EVDD ≤ 5.5 V 0.26 – – – – – – µs tSU:DAT 2.7 V ≤ EVDD ≤ 5.5 V 50 – – – – – – ns tHD:DAT 2.7 V ≤ EVDD ≤ 5.5 V 0 – – – – – – µs tSU:STO 2.7 V ≤ EVDD ≤ 5.5 V 0.26 – – – – – – µs tBUF 2.7 V ≤ EVDD ≤ 5.5 V 0.5 – – – – – – µs SCLA0 = “L” Hold time when SCLA0 = “H” Data setup time (reception) Data hold time 0.5 Note 2 (transmission) Setup time of stop condition Bus-free time Notes 1. 2. 3. Remark The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Either V DD or VBAT is selected by the battery backup function. The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Fast mode plus: Cb = 120 pF, Rb = 1.1 kΩ IICA serial transfer timing tLOW tR SCL0 tHD:DAT tHD:STA tHIGH tF tSU:STA tHD:STA tSU:STO tSU:DAT SDA0 tBUF Stop condition Start condition R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Restart condition Stop condition Page 67 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS 2.6 Analog Characteristics 2.6.1 A/D converter characteristics (1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (–) = AVREFM/ANI1 (ADREFM = 1), target pins: ANI2 to ANI5 and internal reference voltage (TA = –40 to +85°C, 1.9 V ≤ VDDNote 3 ≤ 5.5 V, VSS = 0 V, reference voltage (+) = AVREFP, reference voltage (–) = AVREFM = 0 V) Parameter Resolution Overall error Symbol Conditions RES Note 1 AINL MIN. TYP. 8 10-bit resolution 1.9 V ≤ AVREFP ≤ 5.5 V 1.2 MAX. Unit 10 bit ±5.0 LSB AVREFP = VDD Conversion time tCONV 10-bit resolution 3.6 V ≤ VDD ≤ 5.5 V 2.125 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 µs 1.9 V ≤ VDD ≤ 5.5 V 17 39 µs Zero-scale error EZS 10-bit resolution AVREFP = VDD 1.9 V ≤ AVREFP ≤ 5.5 V ±0.35 %FSR Full-scale errorNotes 1, 2 EFS 10-bit resolution AVREFP = VDD 1.9 V ≤ AVREFP ≤ 5.5 V ±0.35 %FSR Integral linearity errorNote 1 ILE 10-bit resolution 1.9 V ≤ AVREFP ≤ 5.5 V ±3.5 LSB 1.9 V ≤ AVREFP ≤ 5.5 V ±2.0 LSB VDD V AVREFP V 1.5 V Notes 1, 2 AVREFP = VDD Differential linearity errorNote 1 DLE 10-bit resolution AVREFP = VDD Reference voltage (+) AVREFP Analog input voltage VAIN VBGR 1.9 0 Select internal reference voltage output 1.38 1.45 2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. Either V DD or VBAT is selected by the battery backup function. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 68 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (2) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (–) = VSS (ADREFM = 0), target pins: ANI0 to ANI5 and internal reference voltage (TA = –40 to +85°C, 1.9 V ≤ VDDNote 3 ≤ 5.5 V, VSS = 0 V, reference voltage (+) = VDDNote 3, reference voltage (–) = VSS) Parameter Symbol Resolution Conditions RES Overall error Note 1 Conversion time MIN. TYP. 8 1.2 MAX. Unit 10 bit ±10.5 LSB AINL 10-bit resolution 1.9 V ≤ VDD ≤ 5.5 V tCONV 10-bit resolution 3.6 V ≤ VDD ≤ 5.5 V 2.125 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 µs 1.9 V ≤ VDD ≤ 5.5 V 17 39 µs Zero-scale error EZS 10-bit resolution 1.9 V ≤ VDD ≤ 5.5 V ±0.85 %FSR Full-scale errorNotes 1, 2 EFS 10-bit resolution 1.9 V ≤ VDD ≤ 5.5 V ±0.85 %FSR ILE 10-bit resolution 1.9 V ≤ VDD ≤ 5.5 V ±4.0 LSB DLE 10-bit resolution 1.9 V ≤ VDD ≤ 5.5 V ±2.0 LSB VDD V 1.5 V Notes 1, 2 Integral linearity errorNote 1 Differential linearity error Note 1 Analog input voltage VAIN VBGR 0 Select internal reference voltage output, 1.38 1.45 2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. Either V DD or VBAT is selected by the battery backup function. Caution When using reference voltage (+) = VDD, taking into account the voltage drop due to the effect of the power switching circuit of the battery backup function and use the A/D conversion result. In addition, enter HALT mode during A/D conversion and set VDD port to input. (3) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (–) = AVREFM/ANI1 (ADREFM = 1), target pins: ANI0, ANI2 to ANI5 (TA = –40 to +85°C, 2.4 V ≤ VDDNote 3 ≤ 5.5 V, VSS = 0 V, reference voltage (+) = VBGR, reference voltage (–) = AVREFM = 0 V, HS (high-speed main) mode) Parameter Symbol Resolution Conditions MIN. RES Conversion time Notes 1, 2 Zero-scale error Integral linearity error Note 1 TYP. MAX. 8 tCONV 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V EZS 8-bit resolution 17 Unit bit 39 µs 2.4 V ≤ VDD ≤ 5.5 V ±0.60 %FSR ILE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±2.0 LSB Differential linearity errorNote 1 DLE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±1.0 LSB Reference voltage (+) VBGR 1.38 1.5 V Analog input voltage VAIN 0 VBGR V 1.45 Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. Either V DD or VBAT is selected by the battery backup function. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 69 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS 2.6.2 24-bit ΔΣ A/D converter characteristics (1) Reference voltage (TA = –40 to +85°C, 2.4 V ≤ VDDNote 1 ≤ 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Internal reference voltage VAVRTO Temperature coefficient for TCBOX Conditions MIN. 0.47 µF capacitor connected to AREGC, AVRT, TYP. MAX. Unit 0.8 V 10 ppm/°C and AVCM pins internal reference voltage Note 2 Notes 1. Either VDD or VBAT is selected by the battery backup function. 2. This is as stipulated by the BOX method. TCBOX = 1 Vmax – Vmin Vmin Ta VBGR Vmax Vmin Box Ta -40°C R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 85°C T Page 70 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (2) Analog input (TA = –40 to +85°C, 2.4 V ≤ VDDNote ≤ 5.5 V, VSS = AVSS = 0 V) Parameter Input voltage range Symbol VAIN (differential voltage) Input gain Input impedance Note Conditions MIN. TYP. Unit mV x1 gain –500 500 x2 gain –250 250 x4 gain –125 125 x8 gain –62.5 62.5 x16 gain –31.25 31.25 x32 gain –15.625 15.625 ainGAIN x1 gain 1 x2 gain 2 x4 gain 4 ainRIN MAX. x8 gain 8 x16 gain 16 x32 gain 32 Differential voltage 150 360 Single-ended voltage 100 240 Times kΩ Either VDD or VBAT is selected by the battery backup function. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 71 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (3) 4 kHz sampling mode (TA = –40 to +85°C, 2.4 V ≤ VDDNote ≤ 5.5 V, VSS = AVSS = 0 V) Parameter Operation clock Symbol fDSAD Conditions MIN. fX oscillation clock, input external clock or high- TYP. MAX. 12 Unit MHz speed on-chip oscillator clock is used Sampling frequency fS 3906.25 Hz Oversampling frequency fOS 1.5 MHz Output data rate TDATA 256 µs Data width RES 24 bit SNDR SNDR 80 dB x1 gain High-speed system clock is selected as operating clock of 24-bit ΔΣ A/D converter (bit 0 of PCKC register (DSADCK) = 1) x16 gain 69 74 65 69 High-speed system clock is selected as operating clock of 24-bit ΔΣ A/D converter (bit 0 of PCKC register (DSADCK) = 1) x32 gain High-speed system clock is selected as operating clock of 24-bit ΔΣ A/D converter (bit 0 of PCKC register (DSADCK) = 1) Passband (low pass band) fChpf At –3 dB (phase in high pass filter not adjusted) 0.607 Hz 1.214 Hz 2.429 Hz 4.857 Hz Bits 7 and 6 of DSADHPFCR register (DSADCOF1, DSADCOF0) = 00 At –3 dB (phase in high pass filter not adjusted) Bits 7 and 6 of DSADHPFCR register (DSADCOF1, DSADCOF0) = 01 At –3 dB (phase in high pass filter not adjusted) Bits 7 and 6 of DSADHPFCR register (DSADCOF1, DSADCOF0) = 10 At –3 dB (phase in high pass filter not adjusted) Bits 7 and 6 of DSADHPFCR register (DSADCOF1, DSADCOF0) = 11 In-band ripple 1 In-band ripple 2 In-band ripple 3 rp1 rp2 rp3 45 Hz to 55 Hz @50 Hz 54 Hz to 66 Hz @60 Hz 45 Hz to 275 Hz @50 Hz 54 Hz to 330 Hz @60 Hz 45 Hz to 1100 Hz @50 Hz 54 Hz to 1320 Hz @60 Hz –0.01 0.01 –0.1 0.1 –0.1 0.1 dB Passband (high pass band) fClpf –3 dB 1672 Hz Stopband (high pass band) fatt –80 dB 2545 Hz Out-band attenuation ATT1 fS –80 dB ATT2 2 fS –80 dB Note Either VDD or VBAT is selected by the battery backup function. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 72 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (4) 2 kHz sampling mode (TA = –40 to +85°C, 2.4 V ≤ VDDNote ≤ 5.5 V, VSS = AVSS = 0 V) Parameter Operation clock Symbol fDSAD Conditions MIN. fX oscillation clock, input external clock or high- TYP. MAX. 12 Unit MHz speed on-chip oscillator clock is used Sampling frequency fS 1953.125 Hz Oversampling frequency fOS 0.75 MHz Output data rate TDATA 512 µs Data width RES 24 bit SNDR SNDR 80 dB x1 gain High-speed system clock is selected as operating clock of 24-bit ΔΣ A/D converter (bit 0 of PCKC register (DSADCK) = 1) x16 gain 69 74 65 69 High-speed system clock is selected as operating clock of 24-bit ΔΣ A/D converter (bit 0 of PCKC register (DSADCK) = 1) x32 gain High-speed system clock is selected as operating clock of 24-bit ΔΣ A/D converter (bit 0 of PCKC register (DSADCK) = 1) Passband (low pass band) fChpf At –3 dB (phase in high pass filter not adjusted) In-band ripple 1 rp1 45 Hz to 55 Hz @50 Hz 54 Hz to 66 Hz @60 Hz In-band ripple 2 In-band ripple 3 rp2 rp3 45 Hz to 275 Hz @50 Hz 54 Hz to 330 Hz @60 Hz 45 Hz to 660 Hz @50 Hz 54 Hz to 550 Hz @60 Hz 0.303 Hz –0.01 0.01 –0.1 0.1 –0.1 0.1 dB Passband (high pass band) fClpf –3 dB 836 Hz Stopband (high pass band) fatt –80 dB 1273 Hz Out-band attenuation ATT1 fS –80 dB ATT2 2 fS –80 dB Note Either VDD or VBAT is selected by the battery backup function. 2.6.3 Temperature sensor 2 characteristics (TA = –40 to +85°C, 2.4 V ≤ VDDNote 2 ≤ 5.5 V, VSS = 0 V, HS (high-speed main) mode) Parameter Symbol Temperature sensor 2 output voltage VOUT Temperature coefficient FVTMPS2 Conditions MIN. TYP. MAX. 0.67 Temperature sensor that depends on –11.7 Unit V –10.7 –9.7 mV/°C the temperature Operation stabilization wait timeNote 1 tTMPON Operable 15 50 µs tTMPCHG Switching mode 5 15 µs Notes 1. Time to drop to output stable value ±5LSB (±7 mV) or less. 2. Either V DD or VBAT is selected by the battery backup function. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 73 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS 2.6.4 POR circuit characteristics (TA = –40 to +85°C, VSS = 0 V) Parameter Detection voltage Symbol VPOR VPDR Conditions When power supply rises When power supply falls Note 1 Note 2 MIN. TYP. MAX. Unit 1.47 1.51 1.55 V 1.46 1.50 1.54 V Notes 1. Be sure to maintain the reset state until the power supply voltage rises over the minimum VDD value in the operating voltage range specified in 2.4 AC Characteristics, by using the voltage detector or external reset pin. 2. If the power supply voltage falls while the voltage detector is off, be sure to either shift to STOP mode or execute a reset by using the voltage detector or external reset pin before the power supply voltage falls below the minimum operating voltage specified in 2.4 AC Characteristics. 2.6.5 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = –40 to +85°C, VPDR ≤ VDDNote ≤ 5.5 V, VSS = 0 V) Parameter Detection voltage Symbol VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VLVD8 VLVD9 VLVD10 VLVD11 VLVD12 Minimum pulse width Conditions MIN. TYP. MAX. Unit When power supply rises 3.98 4.06 4.24 V When power supply falls 3.90 3.98 4.16 V When power supply rises 3.68 3.75 3.92 V When power supply falls 3.60 3.67 3.84 V When power supply rises 3.07 3.13 3.29 V When power supply falls 3.00 3.06 3.22 V When power supply rises 2.96 3.02 3.18 V When power supply falls 2.90 2.96 3.12 V When power supply rises 2.86 2.92 3.07 V When power supply falls 2.80 2.86 3.01 V When power supply rises 2.76 2.81 2.97 V When power supply falls 2.70 2.75 2.91 V When power supply rises 2.66 2.71 2.86 V When power supply falls 2.60 2.65 2.80 V When power supply rises 2.56 2.61 2.76 V When power supply falls 2.50 2.55 2.70 V When power supply rises 2.45 2.50 2.65 V When power supply falls 2.40 2.45 2.60 V When power supply rises 2.05 2.09 2.23 V When power supply falls 2.00 2.04 2.18 V When power supply rises 1.94 1.98 2.12 V When power supply falls 1.90 1.94 2.08 V When power supply rises 1.84 1.88 2.01 V When power supply falls 1.80 1.84 1.97 V When power supply rises 1.74 1.77 1.81 V When power supply falls 1.70 1.73 1.77 V 300 µs tLW Detection delay time Note 300 µs Either VDD or VBAT is selected by the battery backup function. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 74 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS LVD Detection Voltage of Interrupt & Reset Mode (TA = –40 to +85°C, VPDR ≤ VDDNote ≤ 5.5 V, VSS = 0 V) Parameter Symbol Detection voltage VLVD8 Conditions MIN. TYP. MAX. Unit 1.80 1.84 1.97 V LVIS1, LVIS0 = 1, 0 Rising release reset voltage 1.94 1.98 2.12 V (+0.1 V) 1.90 1.94 2.08 V LVIS1, LVIS0 = 0, 1 Rising release reset voltage (+0.2 V) Falling interrupt voltage 2.05 2.09 2.23 V 2.00 2.04 2.18 V LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.07 3.13 3.29 V (+1.2 V) Falling interrupt voltage 3.00 3.06 3.22 V VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage 2.40 2.45 2.60 V 2.56 2.61 2.76 V 2.50 2.55 2.70 V VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage: 1.8 V VLVD7 VLVD6 VLVD1 VLVD8 VLVD7 Falling interrupt voltage LVIS1, LVIS0 = 1, 0 Rising release reset voltage Falling interrupt voltage 2.66 2.71 2.86 V 2.60 2.65 2.80 V 3.68 3.75 3.92 V Falling interrupt voltage 3.60 3.67 3.84 V VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage 2.70 2.75 2.91 V 2.86 2.92 3.07 V 2.80 2.86 3.01 V 2.96 3.02 3.18 V 2.90 2.96 3.12 V 3.98 4.06 4.24 V 3.90 3.98 4.16 V VLVD6 LVIS1, LVIS0 = 0, 1 Rising release reset voltage Falling interrupt voltage VLVD1 VLVD5 LVIS1, LVIS0 = 0, 0 Rising release reset voltage VLVD4 LVIS1, LVIS0 = 1, 0 Rising release reset voltage Falling interrupt voltage VLVD3 LVIS1, LVIS0 = 0, 1 Rising release reset voltage Falling interrupt voltage VLVD0 LVIS1, LVIS0 = 0, 0 Rising release reset voltage Falling interrupt voltage Note Either VDD or VBAT is selected by the battery backup function. 2.6.6 Power supply voltage rising slope characteristics (TA = –40 to +85°C, VSS = 0 V) Parameter Power supply voltage rising slope Symbol Conditions SVDDR MIN. TYP. MAX. Unit 54 V/ms SVRTCR Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating voltage range shown in 2.4 AC Characteristics. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 75 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS 2.7 Battery Backup Function 2.7.1 Power supply switching characteristics (TA = –40 to +85°C, VSS = 0 V) Parameter Power switching detection voltage Symbol VDETBAT1 Conditions VDD → VBAT MIN. TYP. MAX. Unit 2.09 2.18 2.26 V 2.19 2.28 2.36 V VBAT ≤ 3.6 V VDETBAT2 VBAT → VDD VBAT ≤ 3.6 V VDD fall slope SVDDF Response time of power switch detector tcmp V/ms -0.06 VBAT ≤ 3.6 V 500 µs Min -0.06 V/ms VBAT Internal voltage VDETBAT2 VDETBAT1 VDD Power switching signal tcmp R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 tcmp Page 76 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS 2.7.2 VDD pin voltage detection characteristics (TA = –40 to +85°C, 1.9 V ≤ VDDNote ≤ 5.5 V, VSS = 0 V) Parameter Symbol Detection voltage LVDVDD[2:0] VLVDVDD0 000 VLVDVDD1 001 VLVDVDD2 VLVDVDD3 010 011 VLVDVDD4 100 VLVDVDD5 101 Conditions Rising TYP. MAX. Unit 2.40 2.53 2.65 V Falling 2.33 2.46 2.58 V Rising 2.60 2.74 2.86 V Falling 2.53 2.67 2.79 V Rising 2.79 2.94 3.07 V Falling 2.73 2.87 2.99 V Rising 3.00 3.15 3.28 V Falling 2.93 3.08 3.21 V Rising 3.30 3.46 3.60 V Falling 3.23 3.39 3.52 V Rising 3.59 3.77 3.91 V Falling 3.53 3.70 3.84 V Minimum pulse width tpw_lvdvdd – – Detection delay time tdly_lvdvdd – – Note MIN. 300 µs 300 µs Either VDD or VBAT is selected by the battery backup function. tpw_lvdvdd Detected voltage VDD→__ Detection voltage VLVDVDD* VDD tdly_lvdvdd R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 tdly_lvdvdd Page 77 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS 2.7.3 VBAT pin voltage detection characteristics (TA = –40 to +85°C, 1.9 V ≤ VDDNote ≤ 5.5 V, VSS = 0 V) Parameter Detection voltage Symbol LVDVBAT[2:0] VLVDVBAT0 000 VLVDVBAT1 001 VLVDVBAT2 VLVDVBAT3 010 011 VLVDVBAT4 100 VLVDVBAT5 101 VLVDVBAT6 110 Conditions Rising TYP. MAX. Unit 1.99 2.11 2.22 V Falling 1.94 2.05 2.16 V Rising 2.09 2.21 2.32 V Falling 2.03 2.15 2.26 V Rising 2.20 2.32 2.43 V Falling 2.14 2.26 2.37 V Rising 2.29 2.42 2.53 V Falling 2.23 2.36 2.47 V Rising 2.38 2.52 2.64 V Falling 2.33 2.46 2.58 V Rising 2.48 2.62 2.74 V Falling 2.42 2.56 2.68 V Rising 2.59 2.73 2.86 V Falling 2.53 2.67 2.79 V Minimum pulse width tpw_lvdvbat – – Detection delay time tdly_lvdvbat – – Note MIN. 300 µs 300 µs Either VDD or VBAT is selected by the battery backup function. tpw_lvdvbat Detected voltage VBAT →__ Detection voltage VLVDVBAT* VBAT tdly_lvdvbat R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 tdly_lvdvbat Page 78 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS 2.7.4 VRTC pin voltage detection characteristics (TA = –40 to +85°C, 1.9 V ≤ VDDNote ≤ 5.5 V, VSS = 0 V) Parameter Detection voltage Symbol LVDVRTC[1:0] VLVDVRTC0 00 VLVDVRTC1 01 VLVDVRTC2 VLVDVRTC3 10 11 Conditions MIN. TYP. MAX. Unit Rising 2.16 2.22 2.28 V Falling 2.10 2.16 2.22 V Rising 2.36 2.43 2.50 V Falling 2.30 2.37 2.44 V Rising 2.56 2.63 2.70 V Falling 2.50 2.57 2.64 V Rising 2.76 2.84 2.92 V Falling 2.70 2.78 2.86 V Minimum pulse width tpw_lvdvrtc – – Detection delay time tdly_lvdvrtc – – Note 300 µs 300 µs Either VDD or VBAT is selected by the battery backup function. tpw_lvdvrtc Detected voltage VRTC →__ Detection voltage VLVDVRTC* VRTC tdly_lvdvrtc R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 tdly_lvdvrtc Page 79 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS 2.7.5 EXLVD pin voltage detection (TA = –40 to +85°C, 1.9 V ≤ VDDNote ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions Detection voltage VLVDEXLVD Rising Minimum pulse width tpw_lvdexlvd – Detection delay time tdly_lvdexlvd – Pin resistor rin_exlvd Falling Note MIN. TYP. MAX. Unit 1.25 1.33 1.41 V 1.20 1.28 1.36 300 300 LVDEXLVDEN = 1 V µs 34 µs MΩ Either VDD or VBAT is selected by the battery backup function. tpw_lvdexlvd __ Detected voltage EXLVD → Detection voltage VLVDEXLVD EXLVD tdly_lvdexlvd R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 tdly_lvdexlvd Page 80 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS 2.8 LCD Characteristics 2.8.1 Resistance division method (1) Static display mode (TA = –40 to +85°C, VL4 (MIN.) ≤ EVDD0 = EVDD1 ≤ VDDNote ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter LCD drive voltage Note Symbol Conditions VL4 MIN. TYP. 2.0 MAX. VDD Note Unit V Either VDD or VBAT is selected by the battery backup function. (2) 1/2 bias method, 1/4 bias method (TA = –40 to +85°C, VL4 (MIN.) ≤ EVDD0 = EVDD1 ≤ VDDNote ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter LCD drive voltage Note Symbol Conditions VL4 MIN. TYP. 2.7 MAX. VDD Note Unit V Either VDD or VBAT is selected by the battery backup function. (3) 1/3 bias method (TA = –40 to +85°C, VL4 (MIN.) ≤ EVDD0 = EVDD1 ≤ VDDNote ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter LCD drive voltage Note Symbol Conditions VL4 MIN. 2.5 TYP. MAX. VDD Note Unit V Either VDD or VBAT is selected by the battery backup function. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 81 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS 2.8.2 Internal voltage boosting method (1) 1/3 bias method (TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 4 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol LCD output voltage variation range Doubler output voltage VL2 Tripler output voltage VL4 Reference voltage setup time Voltage boost wait time VL1 Note 2 Note 3 Conditions Note 1 TYP. MAX. Unit C1 to C4 VLCD = 04H 0.90 1.00 1.08 V = 0.47 µF VLCD = 05H 0.95 1.05 1.13 V VLCD = 06H 1.00 1.10 1.18 V VLCD = 07H 1.05 1.15 1.23 V VLCD = 08H 1.10 1.20 1.28 V VLCD = 09H 1.15 1.25 1.33 V VLCD = 0AH 1.20 1.30 1.38 V VLCD = 0BH 1.25 1.35 1.43 V VLCD = 0CH 1.30 1.40 1.48 V VLCD = 0DH 1.35 1.45 1.53 V VLCD = 0EH 1.40 1.50 1.58 V VLCD = 0FH 1.45 1.55 1.63 V VLCD = 10H 1.50 1.60 1.68 V VLCD = 11H 1.55 1.65 1.73 V VLCD = 12H 1.60 1.70 1.78 V VLCD = 13H 1.65 1.75 1.83 V Note 1 = 0.47 µF 2 VL1–0.10 2 VL1 2 VL1 V Note 1 = 0.47 µF 3 VL1–0.15 3 VL1 3 VL1 V C1 to C4 C1 to C4 tVWAIT1 tVWAIT2 MIN. Note 1 C1 to C4 = 0.47 µF 5 ms 500 ms Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = 0.47 µF±30% 2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the internal voltage boosting method is selected (by setting the MDSET1 and MDSET0 bits of the LCDM0 register to 01B) if the default value reference voltage is used) until voltage boosting starts (VLCON = 1). 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). 4. Either VDD or VBAT is selected by the battery backup function. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 82 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS (2) 1/4 bias method (TA = –40 to +85°C, 1.7 V ≤ EVDD0 = EVDD1 ≤ VDDNote 4 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol LCD output voltage variation range Doubler output voltage VL2 Tripler output voltage VL3 Quadruply output voltage Reference voltage setup time Voltage boost wait time VL1 VL4 Note 2 Note 3 Conditions Note 1 TYP. MAX. Unit C1 to C5 VLCD = 04H 0.90 1.00 1.08 V = 0.47 µF VLCD = 05H 0.95 1.05 1.13 V VLCD = 06H 1.00 1.10 1.18 V VLCD = 07H 1.05 1.15 1.23 V VLCD = 08H 1.10 1.20 1.28 V VLCD = 09H 1.15 1.25 1.33 V VLCD = 0AH 1.20 1.30 1.38 V 2 VL1–0.08 2 VL1 2 VL1 V C1 to C5Note 1 = 0.47 µF Note 1 = 0.47 µF 3 VL1–0.12 3 VL1 3 VL1 V Note 1 = 0.47 µF 4 VL1–0.16 4 VL1 4 VL1 V C1 to C5 C1 to C5 tVWAIT1 tVWAIT2 MIN. Note 1 C1 to C5 = 0.47 µF 5 ms 500 ms Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL3 and GND C5: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = C5 = 0.47 µF±30% 2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the internal voltage boosting method is selected (by setting the MDSET1 and MDSET0 bits of the LCDM0 register to 01B) if the default value reference voltage is used) until voltage boosting starts (VLCON = 1). 3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). 4. Either VDD or VBAT is selected by the battery backup function. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 83 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS 2.8.3 Capacitor split method (1) 1/3 bias method (TA = –40 to +85°C, 2.2 V ≤ EVDD0 = EVDD1 ≤ VDDNote 3 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter VL4 voltage Symbol VL4 VL2 voltage VL2 Conditions MIN. Note 2 C1 to C4 = 0.47 µF Note 2 C1 to C4 = 0.47 µF TYP. VDD 2/3 VL4– 2/3 VL4 0.1 VL1 voltage VL1 C1 to C4 = 0.47 µFNote 2 1/3 VL4– Notes 1. 2. tVWAIT Unit V 2/3 VL4 + V 0.1 1/3 VL4 0.1 Capacitor split wait timeNote 1 MAX. Note 3 100 1/3 VL4 + V 0.1 ms This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1). This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = 0.47 µF±30% 3. Either VDD or VBAT is selected by the battery backup function. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 84 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS 2.9 RAM Data Retention Characteristics (TA = –40 to +85°C) Parameter Symbol Data retention supply voltage Conditions MIN. TYP. 1.46Note VDDDR MAX. Unit 5.5 V Note The value depends on the POR detection voltage. When the voltage drops, the data in RAM are retained until a POR is applied, but are not retained following a POR. Operation mode STOP mode RAM data retention VDD VDDDR STOP instruction execution Standby release signal (interrupt request) 2.10 Flash Memory Programming Characteristics (TA = –40 to +85°C, 1.9 V ≤ VDDNote 4 ≤ 5.5 V, VSS = 0 V) Parameter Symbol System clock frequency Number of code flash rewrites fCLK Notes 1, 2, 3 Cerwr Conditions 1.9 V ≤ VDD Note 4 ≤ 5.5 V Retained for 20 years MIN. TYP. 1 MAX. Unit 24 MHz 1,000 Times TA = 85°C Number of data flash rewritesNotes 1, 2, 3 Retained for 1 year 1,000,000 TA = 25°C Retained for 5 years 100,000 TA = 85°C Retained for 20 years 10,000 TA = 85°C Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. 2. When using flash memory programmer and Renesas Electronics self programming library 3. This characteristic indicates the flash memory characteristic and based on Renesas Electronics reliability test. 4. Either VDD or VBAT is selected by the battery backup function. 2.11 Dedicated Flash Memory Programmer Communication (UART) (TA = –40 to +85°C, 1.9 V ≤ EVDD0 = EVDD1 ≤ VDDNote ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Transfer rate Note Symbol Conditions During serial programming MIN. 115,200 TYP. MAX. Unit 1,000,000 bps Either VDD or VBAT is selected by the battery backup function. R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 85 of 89 RL78/I1C 2. ELECTRICAL SPECIFICATIONS 2.12 Timing Specs for Switching Flash Memory Programming Modes (TA = –40 to +85°C, 1.9 V ≤ EVDD0 = EVDD1 ≤ VDDNote ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Time to complete the tSUINIT Conditions MIN. TYP. POR and LVD reset must be released before MAX. Unit 100 ms the external reset is released. communication for the initial setting after the external reset is released Time to release the external reset tSU after the TOOL0 pin is set to the POR and LVD reset must be released before 10 µs 1 ms the external reset is released. low level Time to hold the TOOL0 pin at the tHD low level after the external reset is POR and LVD reset must be released before the external reset is released. released (excluding the processing time of the firmware to control the flash memory) Note Either VDD or VBAT is selected by the battery backup function. RESET 723 µs + tHD processing time 1-byte data for setting mode TOOL0 tSU tSUINIT The low level is input to the TOOL0 pin. The external reset is released (POR and LVD reset must be released before the external reset is released.). The TOOL0 pin is set to the high level. Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the resets end. tSU: Time to release the external reset after the TOOL0 pin is set to the low level. tHD: Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory) R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 86 of 89 S 64 49 ZD 1 48 D HD e y S 1 Index mark *1 6 33 *3 bp 17 32 x ZE F Previous Code 64P6Q-A / FP-64K / FP-64KV E *2 RENESAS Code PLQP0064KB-A b1 bp c1 Detail F Terminal cross section MASS[Typ.] 0.3g A HE JEITA Package Code P-LFQFP64-10x10-0.50 A2 R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 A1 c L1 L e x y ZD ZE L L1 D E A2 HD HE A A1 bp b1 c c1 Reference Symbol Min Nom Max 9.9 10.0 10.1 9.9 10.0 10.1 1.4 11.8 12.0 12.2 11.8 12.0 12.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 8° 0° 0.5 0.08 0.08 1.25 1.25 0.35 0.5 0.65 1.0 Dimension in Millimeters NOTE) 1. DIMENSIONS " *1" AND " *2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION " *3" DOES NOT INCLUDE TRIM OFFSET. RL78/I1C 3. PACKAGE DRAWINGS 3. PACKAGE DRAWINGS 3.1 64-pin Products R5F10NLEDFB, R5F10NLGDFB, R5F11TLEDFB, R5F11TLGDFB Page 87 of 89 c RL78/I1C 3. PACKAGE DRAWINGS 3.2 80-pin Products R5F10NMEDFB, R5F10NMGDFB, R5F10NMJDFB R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 Page 88 of 89 S 100 76 ZD 1 75 *1 e D HD y S *3 bp 5 51 x 26 50 Previous Code 100P6Q-A / FP-100U / FP-100UV F b1 bp c1 Detail F Terminal cross section MASS[Typ.] 0.6g A2 A HE RENESAS Code PLQP0100KB-A 2 Index mark JEITA Package Code P-LFQFP100-14x14-0.50 E *2 ZE R01DS0281EJ0210 Rev.2.10 Aug 23, 2019 A1 c L1 L e x y ZD ZE L L1 D E A2 HD HE A A1 bp b1 c c1 Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0° 8° 0.5 0.08 0.08 1.0 1.0 0.35 0.5 0.65 1.0 Reference Dimension in Millimeters Symbol NOTE) 1. DIMENSIONS " *1" AND " *2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION " *3" DOES NOT INCLUDE TRIM OFFSET. RL78/I1C 3. PACKAGE DRAWINGS 3.3 100-pin Products R5F10NPJDFB, R5F10NPGDFB Page 89 of 89 c Revision History RL78/I1C Datasheet Rev. Date Page 1.00 2.00 May 31, 2016 Aug 31, 2018  p.12 p.21, 22 p.67 p.68 Description Summary First Edition issued Modification of table in 1.6 Outline of Functions Modification of description in 2.3.1 Pin characteristics Modification of table in 2.6.1 (1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (–) = AVREFM/ANI1 (ADREFM = 1), target pins: ANI2 to ANI5 and internal reference voltage Modification of table in 2.6.1 (2) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (–) = VSS (ADREFM = 0), target pins: ANI0 to ANI5 and internal reference voltage p.69 2.10 Aug 23, 2019 Modification of parameter and symbol, and addition of note 2 in 2.6.2 (1) Reference voltage p.70 Modification of condition and unit in 2.6.2 (2) Analog input p.72 Modification of typical value in 2.6.2 (4) 2 kHz sampling mode Throughout Addition of products in which AES function is not available (R5F11TLG and R5F11TLE) p.1 Addition of description in 1.1 Features p.3 Modification of note 2 in 1.1 Features p.4 Modification of Figure 1-1 Part Number, Memory Size, and Package of RL78/I1C p.4 Modification of Table 1-1 List of Ordering Part Numbers p.12 Deletion of note 1 in the “100-pin” column in 1.6 Outline of Functions p.13, 14 Modification of 1.6 Outline of Functions p.78 Modification of 2.7.3 VBAT pin voltage detection characteristics p.79 Modification of 2.7.4 VRTC pin voltage detection characteristics p.82 Deletion of note 2 for VL1 in 2.8.2 Internal voltage boosting method, (1) 1/3 bias method p.83 Deletion of note 2 for VL1 in 2.8.2 Internal voltage boosting method, (2) 1/4 bias method The mark “” shows major revised points. The revised points can be easily searched by copying an “” in the PDF file and specifying it in the “Find what:” field. All trademarks and registered trademarks are the property of their respective owners. EEPROM is a trademark of Renesas Electronics Corporation. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc. C-1 General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor 2. devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the 3. level at which resetting is specified. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal 4. elements. Follow the guideline for input signal during power-off state as described in your product documentation. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal 5. become possible. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal 6. produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the 7. input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.). Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these 8. addresses as the correct operation of the LSI is not guaranteed. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a systemevaluation test for the given product. Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits, software, or information. 2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application examples. 3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 4. You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by 5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the you or third parties arising from such alteration, modification, copying or reverse engineering. product’s quality grade, as indicated below. "Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; industrial robots; etc. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc. Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or other Renesas Electronics document. 6. When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for Handling and Using Semiconductor Devices” in the reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such specified ranges. 7. Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you. 8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. You are responsible for carefully and sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You shall comply with any applicable export control laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or transactions. 10. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or transfers the product to a third party, to notify such third party in advance of the contents and conditions set forth in this document. 11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. (Rev.4.0-1 November 2017) http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics Corporation TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan Renesas Electronics America Inc. 1001 Murphy Ranch Road, Milpitas, CA 95035, U.S.A. Tel: +1-408-432-8888, Fax: +1-408-434-5351 Renesas Electronics Canada Limited 9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3 Tel: +1-905-237-2004 Renesas Electronics Europe GmbH Arcadiastrasse 10, 40472 Düsseldorf, Germany Tel: +49-211-6503-0, Fax: +49-211-6503-1327 Renesas Electronics (China) Co., Ltd. Room 101-T01, Floor 1, Building 7, Yard No. 7, 8th Street, Shangdi, Haidian District, Beijing 100085, China Tel: +86-10-8235-1155, Fax: +86-10-8235-7679 Renesas Electronics (Shanghai) Co., Ltd. Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai 200333, China Tel: +86-21-2226-0888, Fax: +86-21-2226-0999 Renesas Electronics Hong Kong Limited Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong Tel: +852-2265-6688, Fax: +852 2886-9022 Renesas Electronics Taiwan Co., Ltd. 13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan Tel: +886-2-8175-9600, Fax: +886 2-8175-9670 Renesas Electronics Singapore Pte. Ltd. 80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949 Tel: +65-6213-0200, Fax: +65-6213-0300 Renesas Electronics Malaysia Sdn.Bhd. Unit No 3A-1 Level 3A Tower 8 UOA Business Park, No 1 Jalan Pengaturcara U1/51A, Seksyen U1, 40150 Shah Alam, Selangor, Malaysia Tel: +60-3-5022-1288, Fax: +60-3-5022-1290 Renesas Electronics India Pvt. Ltd. No.777C, 100 Feet Road, HAL 2nd Stage, Indiranagar, Bangalore 560 038, India Tel: +91-80-67208700 Renesas Electronics Korea Co., Ltd. 17F, KAMCO Yangjae Tower, 262, Gangnam-daero, Gangnam-gu, Seoul, 06265 Korea Tel: +82-2-558-3737, Fax: +82-2-558-5338 © 2019 Renesas Electronics Corporation. All rights reserved. Colophon 8.0