Datasheet
RL78/L12
R01DS0157EJ0210
Rev.2.10
Sep 30, 2016
RENESAS MCU
Integrated LCD controller/driver, True Low Power Platform (as low as 62.5 µA/MHz, and 0.64 µA for RTC + LVD),
1.6 V to 5.5 V operation, 8 to 32 Kbyte Flash, 31 DMIPS at 24 MHz, for All LCD Based Applications
1. OUTLINE
1.1 Features
Ultra-Low Power Technology
• 1.6 V to 5.5 V operation from a single supply
• Stop (RAM retained): 0.23 µA, (LVD enabled): 0.31 µA
• Halt (RTC + LVD): 0.64 µA
• Supports snooze
• Operating: 62.5 µA/MHz
• LCD operating current (Capacitor split method): 0.12 µA
• LCD operating current (Internal voltage boost method):
0.63 µA (VDD = 3.0 V)
16-bit RL78 CPU Core
• Delivers 31 DMIPS at maximum operating frequency of
24 MHz
• Instruction Execution: 86% of instructions can be
executed in 1 to 2 clock cycles
• CISC Architecture (Harvard) with 3-stage pipeline
• Multiply Signed & Unsigned: 16 x 16 to 32-bit result in 1
clock cycle
• MAC: 16 x 16 to 32-bit result in 2 clock cycles
• 16-bit barrel shifter for shift & rotate in 1 clock cycle
• 1-wire on-chip debug function
Code Flash Memory
• Density: 8 KB to 32 KB
• Block size: 1 KB
• On-chip single voltage flash memory with protection
from block erase/writing
• Self-programming with flash shield window function
Data Flash Memory
• Data flash with background operation
• Data flash size: 2 KB size
• Erase cycles: 1 Million (typ.)
• Erase/programming voltage: 1.8 V to 5.5 V
RAM
• 1 KB and 1.5 KB size options
• Supports operands or instructions
• Back-up retention in all modes
High-speed On-chip Oscillator
• 24 MHz with +/− 1% accuracy over voltage (1.8 V to 5.5
V) and temperature (−20°C to 85°C)
• Pre-configured settings: 24 MHz, 16 MHz, 12 MHz, 8
MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz & 1 MHz
Reset and Supply Management
• Power-on reset (POR) monitor/generator
• Low voltage detection (LVD) with 14 setting options
(Interrupt and/or reset function)
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
LCD Controller/Driver
• Up to 35 seg x 8 com or 39 seg x 4 com
• Supports capacitor split method, internal voltage boost
method and resistance division method
• Supports waveform types A and B
• Supports LCD contrast adjustment (16 steps)
• Supports LCD blinking
Direct Memory Access (DMA) Controller
• Up to 2 fully programmable channels
• Transfer unit: 8- or 16-bit
Multiple Communication Interfaces
2
• Up to 1 × I C multi-master
• Up to 2 × CSI/SPI (7-, 8-bit)
• Up to 1 × UART (7-, 8-, 9-bit)
• Up to 1 × LIN
Extended-Function Timers
• Multi-function 16-bit timers: Up to 8 channels
• Real-time clock (RTC): 1 channel (full calendar and
alarm function with watch correction function)
• Interval Timer: 12-bit, 1 channel
• 15 kHz watchdog timer: 1 channel (window function)
Rich Analog
• ADC: Up to 10 channels, 10-bit resolution, 2.1 µs
conversion time
• Supports 1.6 V
• Internal reference voltage (1.45 V)
• On-chip temperature sensor
Safety Features (IEC or UL 60730 compliance)
• Flash memory CRC calculation
• RAM parity error check
• RAM write protection
• SFR write protection
• Illegal memory access detection
• Clock frequency detection
• ADC self-test
General Purpose I/O
• 5V tolerant, high-current (up to 20 mA per pin)
• Open-Drain, Internal Pull-up support
Operating Ambient Temperature
• TA: −40 °C to +85 °C (A: Consumer applications)
• TA: −40 °C to +105 °C (G: Industrial applications)
Package Type and Pin Count
From 7mm x 7mm to 12mm x 12mm
QFP: 32, 44, 48, 52, 64
Page 1 of 131
RL78/L12
1. OUTLINE
ROM, RAM capacities
Flash ROM Data flash
32 KB
16 KB
8KB
2 KB
2 KB
2 KB
RAM
Note
1.5 KB
1 KB
1 KB
Note
Note
RL78/L12
32 pins
44 pins
48 pins
52 pins
64 pins
R5F10RBC
R5F10RFC
R5F10RGC
R5F10RJC
R5F10RLC
R5F10RBA
R5F10RFA
R5F10RGA
R5F10RJA
R5F10RLA
R5F10RB8
R5F10RF8
R5F10RG8
R5F10RJ8
−
Note In the case of the 1 KB, and 1.5 KB, this is 630 bytes when the self-programming function and data flash
function is used.
Remark The functions mounted depend on the product. See 1.6 Outline of Functions.
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RL78/L12
1. OUTLINE
1.2 List of Part Numbers
Figure 1-1 Part Number, Memory Size, and Package of RL78/L12
Part No. R 5 F 1 0 R L C A x x x F B
Package type:
FP
FA
FB
NB
:
:
:
:
LQFP, 0.80 mm pitch
LQFP, 0.65 mm pitch
LQFP, 0.50 mm pitch
WQFN, 0.40 mm pitch
ROM number (Omitted with blank products)
Classification:
A : Consumer applications, TA = -40˚C to 85˚C
G : Industrial applications, TA = -40˚C to 105˚C
ROM capacity:
8 : 8 KB
A : 16 KB
C : 32 KB
Pin count:
B :
F :
G:
J :
L :
32-pin
44-pin
48-pin
52-pin
64-pin
RL78/L12 group
Memory type:
F : Flash memory
Renesas MCU
Renesas semiconductor product
R01DS0157EJ0210 Rev.2.10
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RL78/L12
1. OUTLINE
Pin count
Package
Application
32 pins
32-pin plastic LQFP (7 × 7)
Part Number
Fields of
Note
A
R5F10RB8AFP, R5F10RBAAFP, R5F10RBCAFP
G
R5F10RB8GFP, R5F10RBAGFP, R5F10RBCGFP
A
R5F10RF8AFP, R5F10RFAAFP, R5F10RFCAFP
44 pins
44-pin plastic LQFP (10 × 10)
G
R5F10RF8GFP, R5F10RFAGFP, R5F10RFCGFP
48 pins
48-pin plastic LQFP (fine pitch)
A
R5F10RG8AFB, R5F10RGAAFB, R5F10RGCAFB
(7 × 7)
G
R5F10RG8GFB, R5F10RGAGFB, R5F10RGCGFB
52-pin plastic LQFP (10 × 10)
A
R5F10RJ8AFA, R5F10RJAAFA, R5F10RJCAFA
G
R5F10RJ8GFA, R5F10RJAGFA, R5F10RJCGFA
A
R5F10RLAANB, R5F10RLCANB
G
R5F10RLAGNB, R5F10RLCGNB
64-pin plastic LQFP (fine pitch)
A
R5F10RLAAFB, R5F10RLCAFB
(10 × 10)
G
R5F10RLAGFB, R5F10RLCGFB
64-pin plastic LQFP (12 × 12)
A
R5F10RLAAFA, R5F10RLCAFA
G
R5F10RLAGFA, R5F10RLCGFA
52 pins
64 pins
64-pin plastic WQFN (8 × 8)
Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/L12.
Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering
part numbers, refer to the target product page of the Renesas Electronics website.
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Sep 30, 2016
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RL78/L12
1. OUTLINE
1.3 Pin Configuration (Top View)
1.3.1 32-pin products
• 32-pin plastic LQFP (7 × 7)
COM0
COM1
COM2
COM3
SEG0
P15/SCK01/INTP1/SEG4
P16/SI01/INTP2/SEG5
P17/SO01/TI02/TO02/SEG6
24 23 22 21 20 19 18 17
16
25
15
26
14
27
RL78/L12
13
28
29
(Top View) 12
11
30
10
31
9
32
1 2 3 4 5 6 7 8
P30/TI01/TO01/SEG19
VL4
VL2
VL1
P126/CAPL
P127/CAPH
P61/SDAA0/SEG20
P60/SCLA0/SEG21
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P14/ANI19/SEG32
P13/ANI18/TI00/SEG31
P12/SO00/TXD0/TOOLTxD/KR0/SEG30/(TI02)/(TO02)
P11/SI00/RXD0/TOOLRxD/KR1/SEG29/(INTP2)
P10/SCK00/TI07/TO07/KR2/SEG28/(INTP1)
P140/TO00/PCLBUZ0/KR3/SEG27
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
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Sep 30, 2016
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RL78/L12
1. OUTLINE
1.3.2 44-pin products
• 44-pin plastic LQFP (10 × 10)
COM0
COM1
COM2
COM3
COM4/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P15/SCK01/INTP1/SEG4
P16/SI01/INTP2/SEG5
P17/SO01/TI02/TO02/SEG6
33 32 31 30 29 28 27 26 25 24 23
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
RL78/L12
17
(Top View)
16
15
14
13
12
1 2 3 4 5 6 7 8 9 10 11
P32/TI03/TO03/INTP4/SEG17
P31/INTP3/RTC1HZ/SEG18
P30/TI01/TO01/SEG19
P125/VL3
VL4
VL2
VL1
P126/CAPL
P127/CAPH
P61/SDAA0/SEG20
P60/SCLA0/SEG21
P120/ANI17/SEG25
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P143/ANI21/SEG34
P142/ANI20/SEG33
P14/ANI19/SEG32
P13/ANI18/SEG31
P12/SO00/TxD0/TOOLTxD/KR0/SEG30/(TI02)/(TO02)
P11/SI00/RxD0/TOOLRxD/KR1/SEG29/(INTP2)
P10/SCK00/TI07/TO07/KR2/SEG28/(INTP1)
P140/TO00/PCLBUZ0/KR3/SEG27
P141/TI00/PCLBUZ1/SEG26
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
R01DS0157EJ0210 Rev.2.10
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RL78/L12
1. OUTLINE
1.3.3 48-pin products
• 48-pin plastic LQFP (fine pitch) (7 × 7)
COM0
COM1
COM2
COM3
COM4/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P15/SCK01/INTP1/SEG4
P16/SI01/INTP2/SEG5
P17/SO01/TI02/TO02/SEG6
P50/INTP5/SEG7/(PCLBUZ0)
36 35 34 33 32 31 30 29 28 27 26 25
24
37
23
38
22
39
21
40
20
41
19
42
RL78/L12
18
43
(Top View)
17
44
16
45
15
46
14
47
13
48
1 2 3 4 5 6 7 8 9 10 11 12
P70/KR0/SEG16
P32/TI03/TO03/INTP4/KR1/SEG17
P31/INTP3/RTC1HZ/KR2/SEG18
P30/TI01/TO01/KR3/SEG19
P125/VL3
VL4
VL2
VL1
P126/CAPL
P127/CAPH
P61/SDAA0/SEG20
P60/SCLA0/SEG21
P120/ANI17/SEG25
P41/ANI16/TI04/TO04/SEG24
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P144/ANI22/SEG35
P143/ANI21/SEG34
P142/ANI20/SEG33
P14/ANI19/SEG32
P13/ANI18/SEG31
P12/SO00/TxD0/TOOLTxD/SEG30/(TI02)/(TO02)
P11/SI00/RxD0/TOOLRxD/SEG29/(INTP2)
P10/SCK00/TI07/TO07/SEG28/(INTP1)
P140/TO00/PCLBUZ0/SEG27
P141/TI00/PCLBUZ1/SEG26
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
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RL78/L12
1. OUTLINE
1.3.4 52-pin products
• 52-pin plastic LQFP (10 × 10)
P51/TI06/TO06/SEG8
P50/INTP5/SEG7/(PCLBUZ0)
P17/SO01/TI02/TO02/SEG6
P16/SI01/INTP2/SEG5
P15/SCK01/INTP1/SEG4
COM7/SEG3
COM6/SEG2
COM5/SEG1
COM4/SEG0
COM3
COM2
COM1
COM0
39 38 37 36 35 34 33 32 31 30 29 28 27
P21/ANI1/AVREFM
40
26
P71/KR1/SEG15
P20/ANI0/AVREFP
41
25
P70/KR0/SEG16
P145/ANI23/SEG36
42
24
P32/TI03/TO03/INTP4/SEG17
P144/ANI22/SEG35
43
23
P31/INTP3/RTC1HZ/KR2/SEG18
P143/ANI21/SEG34
44
22
P30/TI01/TO01/KR3/SEG19
P142/ANI20/SEG33
45
21
P125/VL3
P14/ANI19/SEG32
46
20
VL4
P13/ANI18/SEG31
47
19
VL2
P12/SO00/TxD0/TOOLTxD/SEG30/(TI02)/(TO02)
48
18
VL1
P11/SI00/RxD0/TOOLRxD/SEG29/(INTP2)
49
17
P126/CAPL
P10/SCK00/TI07/TO07/SEG28/(INTP1)
50
16
P127/CAPH
P140/TO00/PCLBUZ0/SEG27
51
15
P61/SDAA0/SEG20
P141/TI00/PCLBUZ1/SEG26
52
14
P60/SCLA0/SEG21
VDD
VSS
REGC
P121/X1
P122/X2/EXCLK
8 9 10 11 12 13
P137/INTP0
P123/XT1
6 7
P124/XT2/EXCLKS
5
RESET
P120/ANI17/SEG25
3 4
P40/TOOL0
2
P42/TI05/TO05/SEG23
1
P41/ANI16/TI04/TO04/SEG24
RL78/L12
(Top View)
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
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Sep 30, 2016
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RL78/L12
1. OUTLINE
1.3.5 64-pin products
• 64-pin plastic WQFN (8 × 8)
COM0
COM1
COM2
COM3
COM4/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P15/SCK01/INTP1/SEG4
P16/SI01/INTP2/SEG5
P17/SO01/TI02/TO02/SEG6
P50/INTP5/SEG7/(PCLBUZ0)
P51/TI06/TO06/SEG8
P52/INTP6/SEG9
P53/TI07/TO07/SEG10/(INTP1)
P54/SEG11/(TI02)/(TO02)/(INTP2)
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P147/SEG38
P146/SEG37
P145/ANI23/SEG36
P144/ANI22/SEG35
P143/ANI21/SEG34
P142/ANI20/SEG33
P14/ANI19/SEG32
P13/ANI18/SEG31
P12/SO00/TxD0/TOOLTxD/SEG30
P11/SI00/RxD0/TOOLRxD/SEG29
P10/SCK00/SEG28
P140/TO00/PCLBUZ0/SEG27/(INTP6)
P141/TI00/PCLBUZ1/SEG26/(INTP7)
RL78/L12
(Top View)
P74/SEG12
P73/KR3/SEG13
P72/KR2/SEG14
P71/KR1/SEG15
P70/KR0/SEG16
P32/TI03/TO03/INTP4/SEG17
P31/INTP3/RTC1HZ/SEG18
P30/TI01/TO01/SEG19
P125/VL3
VL4
VL2
VL1
P126/CAPL
P127/CAPH
P61/SDAA0/SEG20
P60/SCLA0/SEG21
6 7 8 9 10 11 12 13 14 15 16
P120/ANI17/SEG25
P41/ANI16/TI04/TO04/SEG24
P42/TI05/TO05/SEG23
P43/INTP7/SEG22
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS
VDD
EVDD
1 2 3 4 5
exposed die pad
Cautions 1. Make EVSS pin the same potential as VSS pin.
2. Make VDD pin the same potential as EVDD pin.
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the microcontroller
must be reduced, it is recommended to supply separate powers to the VDD and EVDD pins and connect
the VSS and EVSS pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
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RL78/L12
1. OUTLINE
• 64-pin plastic LQFP (fine pitch) (10 × 10)
• 64-pin plastic LQFP (12 × 12)
COM0
COM1
COM2
COM3
COM4/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P15/SCK01/INTP1/SEG4
P16/SI01/INTP2/SEG5
P17/SO01/TI02/TO02/SEG6
P50/INTP5/SEG7/(PCLBUZ0)
P51/TI06/TO06/SEG8
P52/INTP6/SEG9
P53/TI07/TO07/SEG10/(INTP1)
P54/SEG11/(TI02)/(TO02)/(INTP2)
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P147/SEG38
P146/SEG37
P145/ANI23/SEG36
P144/ANI22/SEG35
P143/ANI21/SEG34
P142/ANI20/SEG33
P14/ANI19/SEG32
P13/ANI18/SEG31
P12/SO00/TxD0/TOOLTxD/SEG30
P11/SI00/RxD0/TOOLRxD/SEG29
P10/SCK00/SEG28
P140/TO00/PCLBUZ0/SEG27/(INTP6)
P141/TI00/PCLBUZ1/SEG26/(INTP7)
RL78/L12
(Top View)
6 7 8 9 10 11 12 13 14 15 16
P120/ANI17/SEG25
P41/ANI16/TI04/TO04/SEG24
P42/TI05/TO05/SEG23
P43/INTP7/SEG22
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS
VDD
EVDD
1 2 3 4 5
P74/SEG12
P73/KR3/SEG13
P72/KR2/SEG14
P71/KR1/SEG15
P70/KR0/SEG16
P32/TI03/TO03/INTP4/SEG17
P31/INTP3/RTC1HZ/SEG18
P30/TI01/TO01/SEG19
P125/VL3
VL4
VL2
VL1
P126/CAPL
P127/CAPH
P61/SDAA0/SEG20
P60/SCLA0/SEG21
Cautions 1. Make EVSS pin the same potential as VSS pin.
2. Make VDD pin the same potential as EVDD pin.
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the microcontroller
must be reduced, it is recommended to supply separate powers to the VDD and EVDD pins and connect
the VSS and EVSS pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
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Sep 30, 2016
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RL78/L12
1. OUTLINE
1.4 Pin Identification
P130, P137:
ANI0, ANI1,
Port 13
ANI16 to ANI23:
Analog Input
P140 to P147:
Port 14
AVREFM:
Analog Reference
PCLBUZ0, PCLBUZ1:
Programmable Clock
Output/Buzzer Output
Voltage Minus
Analog Reference
REGC:
Regulator Capacitance
Voltage Plus
RESET:
Reset
Capacitor for LCD
RTC1HZ:
Real-time Clock Correction Clock
EVDD:
Power Supply for Port
RxD0:
Receive Data
EVSS:
Ground for Port
SCK00, SCK01:
Serial Clock Input/Output
EXCLK:
External Clock Input
SCLA0:
Serial Clock Input/Output
(Main System Clock)
SDAA0:
Serial Data Input/Output
External Clock Input
SEG0 to SEG38:
LCD Segment Output
(Subsystem Clock)
SI00, SI01:
Serial Data Input
Interrupt Request From
SO00, SO01:
Serial Data Output
Peripheral
TI00 to TI07:
Timer Input
Key Return
TO00 to TO07:
Timer Output
P10 to P17:
Port 1
TOOL0:
Data Input/Output for Tool
P20, P21:
Port 2
TOOLRxD, TOOLTxD:
Data Input/Output for External Device
P30 to P32:
Port 3
TxD0:
Transmit Data
P40 to P43:
Port 4
VDD:
Power Supply
AVREFP:
CAPH, CAPL:
(1 Hz) Output
COM0 to COM7,
EXCLKS:
INTP0 to INTP7:
KR0 to KR3:
P50 to P54:
Port 5
VL1 to VL4:
LCD Power Supply
P60, P61:
Port 6
VSS:
Ground
P70 to P74:
Port 7
X1, X2:
Crystal Oscillator (Main System Clock)
P120 to P127:
Port 12
XT1, XT2:
Crystal Oscillator (Subsystem Clock)
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RL78/L12
1. OUTLINE
1.5 Block Diagram
1.5.1 32-pin products
TIMER ARRAY
UNIT0 (8ch)
TI00/P13
TO00/P140
ch0
TI01/TO01/P30
ch1
TI02/TO02/P17
(TI02/TO02/P12)
ch2
ch3
ch4
2
ANI0/P20, ANI1/P21
2
ANI18/P13, ANI19/P14
PORT 1
8
P10 to P17
PORT 2
2
P20, P21
PORT 3
P30
PORT 4
P40
A/D CONVERTER
ch5
AVREFP/P20
AVREFM/P21
ch6
PORT 6
2
P60, P61
ch7
TI07/TO07/P10
REAL-TIME
CLOCK
LOW-SPEED
ON-CHIP
OSCILLATOR
12- BIT INTERVAL
TIMER
PORT 12
RL78
CPU
CORE
2
P126, P127
2
P121, P122
CODE FLASH MEMORY
PORT 13
P137
PORT 14
P140
DATA FLASH MEMORY
WINDOW
WATCHDOG
TIMER
BUZZER OUTPUT
PCLBUZ0/P140
SEG0, SEG4 to SEG6,
SEG19 to SEG21,
SEG27 to SEG32
COM0 to COM3
VL1, VL2, VL4
CAPH
CAPL
13
4
LCD
CONTROLLER/
DRIVER
CLOCK OUTPUT
CONTROL
RAM
KEY RETURN
3
KR0/P12 to KR2/P10
KR3/P140
RAM SPACE
FOR LCD DATA
POWER ON RESET/
VOLTAGE
DETECTOR
SERIAL ARRAY
UNIT0 (2ch)
VDD
RxD0/P11
TxD0/P12
UART0
SCK00/P10
SI00/P11
SO00/P12
CSI00
VSS
POR/LVD
CONTROL
TOOLRxD/P11,
TOOLTxD/P12
RESET CONTROL
SCK01/P15
SI01/P16
SO01/P17
CSI01
TOOL0/P40
ON-CHIP DEBUG
DIRECT MEMORY
ACCESS CONTROL
SYSTEM
CONTROL
SDAA0/P61
SCLA0/P60
HIGH-SPEED
SERIAL
INTERFACE IICA0
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
RESET
X1/P121
X2/EXCLK/P122
ON-CHIP
OSCILLATOR
CRC
VOLTAGE
REGULATOR
REGC
INTP0/P137
2
BCD
ADJUSTMENT
Remark
INTP1/P15(INTP1/P10),
INTP2/P16(INTP2/P11)
INTERRUPT
CONTROL
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR)
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 12 of 131
RL78/L12
1. OUTLINE
1.5.2 44-pin products
TIMER ARRAY
UNIT0 (8ch)
TI00/P141
TO00/P140
ch0
TI01/TO01/P30
ch1
TI02/TO02/P17
(TI02/TO02/P12)
ch2
TI03/TO03/P32
ch3
2
ch4
ANI0/P20, ANI1/P21
ANI17/P120, ANI18/P13,
ANI19/P14
ANI20/P142, ANI21/P143
3
A/D CONVERTER
ch5
2
PORT 1
8
P10 to P17
PORT 2
2
P20, P21
PORT 3
3
P30 to P32
PORT 4
AVREFP/P20
AVREFM/P21
ch6
PORT 6
REAL-TIME
CLOCK
RTC1HZ/P31
LOW-SPEED
ON-CHIP
OSCILLATOR
12- BIT INTERVAL
TIMER
PORT 12
RL78
CPU
CORE
22
8
LCD
CONTROLLER/
DRIVER
P120, P125 to P127
4
P121 to P124
PORT 13
P137
PORT 14
4
P140 to P143
2
PCLBUZ0/P140,
PCLBUZ1/P141
3
KR0/P12 to KR2/P10
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
RAM
KEY RETURN
KR3/P140
RAM SPACE
FOR LCD DATA
POWER ON RESET/
VOLTAGE
DETECTOR
VDD
RxD0/P11
TxD0/P12
UART0
SCK00/P10
SI00/P11
SO00/P12
CSI00
SCK01/P15
SI01/P16
SO01/P17
CSI01
SCLA0/P60
4
DATA FLASH MEMORY
SERIAL ARRAY
UNIT0 (2ch)
SDAA0/P61
P60, P61
CODE FLASH MEMORY
WINDOW
WATCHDOG
TIMER
COM0 to COM7
VL1 to VL4
CAPH
CAPL
2
ch7
TI07/TO07/P10
SEG0 to SEG6,
SEG17 to SEG21,
SEG25 to SEG34
P40
VSS
POR/LVD
CONTROL
TOOLRxD/P11,
TOOLTxD/P12
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
DIRECT MEMORY
ACCESS CONTROL
SYSTEM
CONTROL
HIGH-SPEED
SERIAL
INTERFACE IICA0
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
RESET
X1/P121
X2/EXCLK/P122
XT1/P123
ON-CHIP
CRC
OSCILLATOR
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
INTP0/P137
BCD
ADJUSTMENT
Remark
INTERRUPT
CONTROL
2
INTP1/P15(INTP1/P10),
INTP2/P16(INTP2/P11)
2
INTP3/P31,
INTP4/P32
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR)
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Sep 30, 2016
Page 13 of 131
RL78/L12
1. OUTLINE
1.5.3 48-pin products
TIMER ARRAY
UNIT0 (8ch)
TI00/P141
TO00/P140
ch0
TI01/TO01/P30
ch1
TI02/TO02/P17
(TI02/TO02/P12)
ch2
TI03/TO03/P32
ch3
2
ch4
TI04/TO04/P41
ANI0/P20, ANI1/P21
ANI16/P41, ANI17/P120,
ANI18/P13, ANI19/P14
ANI20/P142 to ANI22/P144
4
A/D CONVERTER
ch5
3
PORT 1
8
P10 to P17
PORT 2
2
P20, P21
PORT 3
3
P30 to P32
PORT 4
2
P40, P41
PORT 5
P50
AVREFP/P20
AVREFM/P21
ch6
PORT 6
2
P60, P61
ch7
TI07/TO07/P10
PORT 7
RTC1HZ/P31
REAL-TIME
CLOCK
LOW-SPEED
ON-CHIP
OSCILLATOR
12- BIT INTERVAL
TIMER
PORT 12
RL78
CPU
CORE
COM0 to COM7
VL1 to VL4
CAPH
CAPL
26
8
LCD
CONTROLLER/
DRIVER
P120, P125 to P127
4
P121 to P124
PORT 13
P137
DATA FLASH MEMORY
PORT 14
5
P140 to P144
2
PCLBUZ0/P140
(PCLBUZ0/P50),
PCLBUZ1/P141
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
RAM
KEY RETURN
KR0/P70
3
KR1/P32 to KR3/P30
RAM SPACE
FOR LCD DATA
SERIAL ARRAY
UNIT0 (2ch)
RxD0/P11
TxD0/P12
4
CODE FLASH MEMORY
WINDOW
WATCHDOG
TIMER
SEG0 to SEG7,
SEG16 to SEG21,
SEG24 to SEG35
P70
POWER ON RESET/
VOLTAGE
DETECTOR
VDD
UART0
VSS
POR/LVD
CONTROL
TOOLRxD/P11,
TOOLTxD/P12
RESET CONTROL
SCK00/P10
SI00/P11
SO00/P12
CSI00
SCK01/P15
SI01/P16
SO01/P17
CSI01
SDAA0/P61
SCLA0/P60
TOOL0/P40
ON-CHIP DEBUG
DIRECT MEMORY
ACCESS CONTROL
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
SERIAL
INTERFACE IICA0
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
XT1/P123
ON-CHIP
OSCILLATOR
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
CRC
INTP0/P137
BCD
ADJUSTMENT
INTERRUPT
CONTROL
2
INTP1/P15(INTP1/P10),
INTP2/P16(INTP2/P11)
2
INTP3/P31,
INTP4/P32
INTP5/P50
Remark
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR)
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Page 14 of 131
RL78/L12
1. OUTLINE
1.5.4 52-pin products
TIMER ARRAY
UNIT0 (8ch)
TI00/P141
TO00/P140
ch0
TI01/TO01/P30
ch1
TI02/TO02/P17
(TI02/TO02/P12)
ch2
TI03/TO03/P32
ch3
2
ch4
TI04/TO04/P41
4
A/D CONVERTER
ch5
TI05/TO05/P42
TI06/TO06/P51
ch6
TI07/TO07/P10
ch7
RTC1HZ/P31
ANI0/P20, ANI1/P21
ANI16/P41, ANI17/P120,
ANI18/P13, ANI19/P14
ANI20/P142 to ANI23/P145
4
12- BIT INTERVAL
TIMER
COM0 to COM7
VL1 to VL4
CAPH
CAPL
30
8
LCD
CONTROLLER/
DRIVER
RL78
CPU
CORE
PORT 2
2
P20, P21
PORT 3
3
P30 to P32
PORT 4
3
P40 to P42
PORT 5
2
P50, P51
PORT 6
2
P60, P61
PORT 7
2
P70, P71
4
P120, P125 to P127
4
P121 to P124
CODE FLASH MEMORY
PORT 13
P137
DATA FLASH MEMORY
PORT 14
6
P140 to P145
2
PCLBUZ0/P140
(PCLBUZ0/P50),
PCLBUZ1/P141
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
RAM
KEY RETURN
2
KR0/P70, KR1/P71
2
KR2/P31, KR3/P30
RAM SPACE
FOR LCD DATA
POWER ON RESET/
VOLTAGE
DETECTOR
SERIAL ARRAY
UNIT0 (2ch)
VDD
RxD0/P11
TxD0/P12
UART0
SCK00/P10
SO10/P17
SI00/P11
SO00/P12
CSI00
SCK01/P15
SI01/P16
P10 to P17
PORT 12
WINDOW
WATCHDOG
TIMER
SEG0 to SEG8,
SEG15 to SEG21,
SEG23 to SEG36
8
AVREFP/P20
AVREFM/P21
REAL-TIME
CLOCK
LOW-SPEED
ON-CHIP
OSCILLATOR
PORT 1
VSS
POR/LVD
CONTROL
TOOLRxD/P11,
TOOLTxD/P12
RESET CONTROL
CSI01
DIRECT MEMORY
ACCESS CONTROL
TOOL0/P40
ON-CHIP DEBUG
CRC
SYSTEM
CONTROL
SDAA0/P61
SCLA0/P60
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
SERIAL
INTERFACE IICA0
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
XT1/P123
ON-CHIP
OSCILLATOR
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
INTP0/P137
BCD
ADJUSTMENT
INTERRUPT
CONTROL
2
INTP1/P15(INTP1/P10),
INTP2/P16(INTP2/P11)
2
INTP3/P31,
INTP4/P32
INTP5/P50
Remark
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR)
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Page 15 of 131
RL78/L12
1. OUTLINE
1.5.5 64-pin products
TIMER ARRAY
UNIT0 (8ch)
TI00/P141
TO00/P140
ch0
TI01/TO01/P30
ch1
TI02/TO02/P17
(TI02/TO02/P54)
ch2
TI03/TO03/P32
ch3
2
ch4
TI04/TO04/P41
4
A/D CONVERTER
ch5
TI05/TO05/P42
TI06/TO06/P51
ch6
TI07/TO07/P53
ch7
RTC1HZ/P31
4
ANI0/P20, ANI1/P21
ANI16/P41, ANI17/P120,
ANI18/P13, ANI19/P14
ANI20/P142 to ANI23/P145
12- BIT INTERVAL
TIMER
39
COM0 to COM7
VL1 to VL4
CAPH
CAPL
8
LCD
CONTROLLER/
DRIVER
RL78
CPU
CORE
SCK00/P10
SI00/P11
SO00/P12
CSI00
SCK01/P15
SI01/P16
SO01/P17
CSI01
SDAA0/P61
SCLA0/P60
2
P20, P21
PORT 3
3
P30 to P32
PORT 4
4
P40 to P43
PORT 5
5
P50 to P54
PORT 6
2
P60, P61
PORT 7
5
P70 to P74
4
P120, P125 to P127
4
P121 to P124
P130
P137
PORT 13
DATA FLASH MEMORY
PORT 14
8
P140 to P147
2
PCLBUZ0/P140
(PCLBUZ0/P50),
PCLBUZ1/P141
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
RAM
KEY RETURN
POWER ON RESET/
VOLTAGE
DETECTOR
SERIAL ARRAY
UNIT0 (2ch)
UART0
PORT 2
CODE FLASH MEMORY
RAM SPACE
FOR LCD DATA
RxD0/P11
TxD0/P12
P10 to P17
PORT 12
WINDOW
WATCHDOG
TIMER
SEG0 to SEG38
8
AVREFP/P20
AVREFM/P21
REAL-TIME
CLOCK
LOW-SPEED
ON-CHIP
OSCILLATOR
PORT 1
VDD,
EVDD
KR0/P70 to
KR3/P73
4
POR/LVD
CONTROL
VSS, TOOLRxD/P11,
EVSS TOOLTxD/P12
RESET CONTROL
DIRECT MEMORY
ACCESS CONTROL
TOOL0/P40
ON-CHIP DEBUG
CRC
SYSTEM
CONTROL
SERIAL
INTERFACE IICA0
MULTIPLIER&
DIVIDER,
MULITIPLYACCUMULATOR
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
XT1/P123
ON-CHIP
OSCILLATOR
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
INTP0/P137
2
BCD
ADJUSTMENT
INTERRUPT
CONTROL
2
INTP1/P15(INTP1/P53),
INTP2/P16(INTP2/P54)
INTP3/P31,
INTP4/P32
INTP5/P50
INTP6/P52(INTP6/P140)
INTP7/P43(INTP7/P141)
Remark
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR)
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Page 16 of 131
RL78/L12
1. OUTLINE
1.6 Outline of Functions
Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set
to 00H.
(1/2)
Item
Code flash memory (KB)
32-pin
44-pin
48-pin
52-pin
64-pin
R5F10RBx
R5F10RFx
R5F10RGx
R5F10RJx
R5F10RLx
8 to 32
8 to 32
8 to 32
8 to 32
16, 32
Data flash memory (KB)
RAM (KB)
Memory space
Main
system
clock
2
1, 1.5
Note 1
2
1, 1.5
Note 1
2
1, 1.5
2
Note 1
1, 1.5
Note 1
2
Note 1
1, 1.5
1 MB
High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
HS (high-speed main) operation: 1 to 20 MHz (VDD = 2.7 to 5.5 V),
HS (high-speed main) operation: 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (low-speed main) operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V),
LV (low-voltage main) operation: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
High-speed on-chip
oscillator clock
Subsystem clock
HS (high-speed main) operation: 1 to 24 MHz (VDD = 2.7 to 5.5 V),
HS (high-speed main) operation: 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (low-speed main) operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V),
LV (low-voltage main) operation: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
−
XT1 (crystal) oscillation , external subsystem clock input (EXCLKS)
32.768 kHz (TYP.): VDD = 1.6 to 5.5 V
Low-speed on-chip oscillator clock
Internal oscillation
15 kHz (TYP.): VDD = 1.6 to 5.5 V
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
0.04167 μs (High-speed on-chip oscillator clock: fIH = 24 MHz operation)
0.05 μs (High-speed system clock: fMX = 20 MHz operation)
30.5 μs (Subsystem clock: fSUB = 32.768 kHz operation)
Instruction set
• Data transfer (8/16 bits)
• Adder and subtractor/logical operation (8/16 bits)
• Multiplication (8 bits × 8 bits)
• Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean
operation), etc.
Total number of I/O port pins and
pins dedicated to drive an LCD
I/O
port
28
40
44
48
58
Total
20
29
33
37
47
CMOS I/O
15
22
26
30
39
CMOS input
3
5
5
5
5
CMOS output
−
−
−
−
1
N-ch open-drain I/O
(EVDD tolerance)
2
2
2
2
2
8
11
11
11
11
Pins dedicated to drive an LCD
LCD controller/driver
Notes 1.
Internal voltage boosting method, capacitor split method, and external resistance
division method are switchable.
Segment signal output
13
Common signal output
4
22 (18)
Note 2
26 (22)
Note 2
4 (8)
30 (26)
Note 2
39 (35)
Note 2
Note 2
In the case of the 1 KB, and 1.5 KB, this is 630 bytes when the self-programming function and data
flash function is used.
2.
The values in parentheses are the number of signal outputs when 8 com is used.
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Page 17 of 131
RL78/L12
1. OUTLINE
(2/2)
Item
Timer
16-bit timer
32-pin
44-pin
48-pin
52-pin
64-pin
R5F10RBx
R5F10RFx
R5F10RGx
R5F10RJx
R5F10RLx
8 channels
8 channels (with 1 channel remote control output function)
Watchdog timer
1 channel
Real-time clock (RTC)
1 channel
12-bit interval timer (IT)
1 channel
Timer output
RTC output
Clock output/buzzer output
4 channels
5 channels
6 channels
8 channels (PWM outputs: 7
(PWM outputs: (PWM outputs: (PWM outputs:
Note 1
Note 1
Note 1
3
)
4
)
5
)
−
Note 1
)
1
• 1 Hz (subsystem clock: fSUB = 32.768 kHz or )
1
2
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz,
32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter
Serial interface
2
I C bus
4 channels
7 channels
9 channels
10 channels
10 channels
• CSI: 2 channel/UART (LIN-bus supported): 1 channel
1 channel
1 channel
1 channel
1 channel
Multiplier and divider/multiply-
• 16 bits × 16 bits = 32 bits (Unsigned or signed)
accumulator
• 32 bits ÷ 32 bits = 32 bits (Unsigned)
1 channel
• 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)
DMA controller
Vectored interrupt Internal
sources
External
2 channels
23
23
23
23
23
4
6
7
7
9
Key interrupt
4
• Reset by RESET pin
Reset
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution
Note 2
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit
• Power-on-reset:
1.51 ±0.04 V
• Power-down-reset: 1.50 ±0.04 V
Voltage detector
• Rising edge : 1.67 V to 4.06 V (14 stages)
• Falling edge : 1.63 V to 3.98 V (14 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 1.6 to 5.5 V
Operating ambient temperature
TA = −40 to +85 °C
Notes 1. The number of PWM outputs varies depending on the setting of channels in use (the number of masters
and slaves).
2. The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
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RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
This chapter describes the electrical specifications for the products "A: Consumer applications (TA = -40 to +85°C)" and
"G: Industrial applications (with TA = -40 to +85°C)".
Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and
evaluation. Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded when
this function is used, and product reliability therefore cannot be guaranteed.
Renesas
Electronics is not liable for problems occurring when the on-chip debug function is used.
2. With products not provided with an EVDD, or EVSS pin, replace EVDD with VDD, or replace EVSS with
VSS.
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RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
2.1 Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25°C)
Parameter
Symbols
Supply voltage
(1/3)
Conditions
Ratings
Unit
VDD
VDD = EVDD
−0.5 to +6.5
V
EVDD
VDD = EVDD
−0.5 to +6.5
V
−0.5 to +0.3
V
EVSS
REGC pin input voltage VIREGC
−0.3 to +2.8
REGC
V
Note 1
and −0.3 to VDD + 0.3
Input voltage
VI1
P70 to P74, P120, P125 to P127,P140 to P147
VI2
−0.3 to EVDD +0.3
P10 to P17, P30 to P32, P40 to P43, P50 to P54,
V
Note 2
and −0.3 to VDD + 0.3
−0.3 to EVDD +0.3
P60, P61 (N-ch open-drain)
V
Note 2
and −0.3 to VDD + 0.3
VI3
P20, P21, P121 to P124, P137, EXCLK,
−0.3 to VDD + 0.3
Note 2
V
EXCLKS, RESET
Output voltage
VO1
−0.3 to EVDD + 0.3
P10 to P17, P30 to P32, P40 to P43,
P50 to P54, P60, P61, P70 to P74, P120,
V
Note 2
and −0.3 to VDD + 0.3
P125 to P127, P130, P140 to P147
Analog input voltage
Note 2
VO2
P20, P21
−0.3 to VDD + 0.3
VAI1
ANI16 to ANI23
−0.3 to EVDD + 0.3 and
V
V
−0.3 to AVREF(+) + 0.3
Notes 2, 3
VAI2
ANI0, ANI1
−0.3 to VDD + 0.3 and
V
−0.3 to AVREF(+) + 0.3
Notes 2, 3
Notes 1.
Connect the REGC pin to Vss via a capacitor (0.47 to 1 μ F). This value regulates the absolute
maximum rating of the REGC pin. Do not use this pin with voltage applied to it.
2.
Must be 6.5 V or lower.
3.
Do not exceed AV REF(+) + 0.3 V in case of A/D conversion target pin.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remarks 1.
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
2.
AVREF(+) : + side reference voltage of the A/D converter.
3.
VSS : Reference voltage
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RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
Absolute Maximum Ratings (TA = 25°C)
Parameter
LCD voltage
(2/3)
Symbols
VL1
Conditions
VL1 voltage
Note 1
Ratings
Unit
−0.3 to +2.8
V
and −0.3 to VL4 + 0.3
VL2
VL3
VL4
VLCAP
VLOUT
VL2 voltage
Note 1
−0.3 to VL4 + 0.3
Note 2
V
VL3 voltage
Note 1
−0.3 to VL4 + 0.3
Note 2
V
VL4 voltage
Note 1
CAPL, CAPH voltage
COM0 to COM7, External resistance division
V
−0.3 to VL4 + 0.3
Note 2
V
−0.3 to VDD + 0.3
Note 2
V
SEG0 to
method
SEG38,
Capacitor split method
−0.3 to VDD + 0.3
Note 2
Internal voltage boosting method
−0.3 to VL4 + 0.3
Note 2
output voltage
Notes 1.
−0.3 to +6.5
Note 1
This value only indicates the absolute maximum ratings when applying voltage to the V L1 , VL2 , V L3 ,
and V L4 pins; it does not mean that applying voltage to these pins is recommended. When using
the internal voltage boosting method or capacitance split method, connect these pins to V SS via a
capacitor (0.47 μ F ± 30%) and connect a capacitor (0.47 μ F ± 30%) between the CAPL and CAPH
pins.
2.
Must be 6.5 V or lower.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure that
the absolute maximum ratings are not exceeded.
Remark VSS : Reference voltage
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 21 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
Absolute Maximum Ratings (TA = 25°C)
Parameter
Output current, high
Symbols
IOH1
(3/3)
Conditions
Per pin
P10 to P17, P30 to P32,
Ratings
Unit
−40
mA
−70
mA
−100
mA
−0.5
mA
−1
mA
40
mA
70
mA
100
mA
1
mA
P40 to P43, P50 to P54,
P70 to P74, P120, P125 to P127,
P130, P140 to P147
Total of all pins
P10 to P14, P40 to P43, P120,
−170 mA
P130, P140 to P147
P15 to P17, P30 to P32,
P50 to P54, P70 to P74,
P125 to P127
IOH2
Per pin
P20, P21
Total of all pins
Output current, low
IOL1
Per pin
P10 to P17, P30 to P32,
P40 to P43, P50 to P54, P60,
P61, P70 to P74, P120,
P125 to P127, P130,
P140 to P147
Total of all pins
P10 to P14, P40 to P43, P120,
170 mA
P130, P140 to P147
P15 to P17, P30 to P32,
P50 to P54, P60, P61,
P70 to P74, P125 to P127
IOL2
Per pin
P20, P21
Total of all pins
Operating ambient
TA
temperature
In normal operation mode
2
mA
−40 to +85
°C
−65 to +150
°C
In flash memory programming mode
Storage temperature
Tstg
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 22 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
2.2 Oscillator Characteristics
2.2.1 X1, XT1 oscillator characteristics
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Resonator
X1 clock oscillation frequency Ceramic resonator/
Note
(fX)
Conditions
MIN.
TYP.
MAX.
Unit
2.7 V ≤ VDD ≤ 5.5 V
1.0
20.0
MHz
2.4 V ≤ VDD ≤ 2.7 V
1.0
16.0
MHz
1.8 V ≤ VDD < 2.7 V
1.0
8.0
MHz
1.6 V ≤ VDD 70% the duty ratio can be calculated with the
following expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOH × 0.7)/(n × 0.01)
Where n = 80% and IOH = −40.0 mA
Total output current of pins = (−40.0 × 0.7)/(80 × 0.01) ≅ −35.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Caution P10, P12, P15, and P17 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 24 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Symbol
Output current,
Note 1
low
IOL1
Conditions
(2/5)
MIN.
TYP.
Per pin for P10 to P17, P30 to P32, P40 to P43,
P50 to P54, P70 to P74, P120, P125 to P127, P130,
P140 to P147
Per pin for P60, P61
Total of P10 to P14, P40 to P43,
P120, P130, P140 to P147
Note 3
)
(When duty = 70%
Total of P15 to P17, P30 to P32,
P50 to P54, P60, P61, P70 to P74,
P125 to P127
Note 3
)
(When duty = 70%
P20, P21
Notes 1.
mA
Note 2
Note 2
mA
4.0 V ≤ EVDD ≤ 5.5 V
70.0
2.7 V ≤ EVDD < 4.0 V
15.0
mA
1.8 V ≤ EVDD < 2.7 V
9.0
mA
1.6 V ≤ EVDD < 1.8 V
4.5
mA
4.0 V ≤ EVDD ≤ 5.5 V
80.0
mA
2.7 V ≤ EVDD < 4.0 V
35.0
mA
1.8 V ≤ EVDD < 2.7 V
20.0
mA
1.6 V ≤ EVDD < 1.8 V
10.0
mA
150.0
mA
0.4
mA
0.8
mA
Per pin
Total of all pins
Unit
20.0
15.0
Total of all pins
Note 3
)
(When duty = 70%
IOL2
MAX.
1.6 V ≤ VDD ≤ 5.5 V
mA
Value of current at which the device operation is guaranteed even if the current flows from the VDD and
EVDD pins to an output pin.
2.
Do not exceed the total current value.
3.
Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the
following expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOH × 0.7)/(n × 0.01)
Where n = 80% and IOL = 70.0 mA
Total output current of pins = (70.0 × 0.7)/(80 × 0.01) ≅ 61.25 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 25 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Input voltage,
Symbol
VIH1
Conditions
(3/5)
MIN.
P10 to P17, P30 to P32, P40 to P43, Normal input buffer
TYP.
MAX.
Unit
0.8EVDD
EVDD
V
2.2
EVDD
V
2.0
EVDD
V
1.50
EVDD
V
P50 to P54, P70 to P74, P120,
high
P125 to P127, P140 to P147
VIH2
P10, P11, P15, P16
TTL input buffer
4.0 V ≤ EVDD ≤ 5.5 V
TTL input buffer
3.3 V ≤ EVDD < 4.0 V
TTL input buffer
1.6 V ≤ EVDD < 3.3 V
Input voltage,
VIH3
P20, P21
0.7VDD
VDD
V
VIH4
P60, P61
0.7EVDD
EVDD
V
VIH5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0.8VDD
VDD
V
VIL1
P10 to P17, P30 to P32, P40 to P43, Normal input buffer
0
0.2EVDD
V
0
0.8
V
0
0.5
V
0
0.32
V
P50 to P54, P70 to P74, P120,
low
P125 to P127, P140 to P147
VIL2
P10, P11, P15, P16
TTL input buffer
4.0 V ≤ EVDD ≤ 5.5 V
TTL input buffer
3.3 V ≤ EVDD < 4.0 V
TTL input buffer
1.6 V ≤ EVDD < 3.3 V
VIL3
P20, P21
0
0.3VDD
V
VIL4
P60, P61
0
0.3EVDD
V
VIL5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0
0.2VDD
V
Caution The maximum value of VIH of P10, P12, P15, P17 is EVDD, even in the N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 26 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Symbol
Output voltage,
VOH1
high
Conditions
(4/5)
MIN.
P10 to P17, P30 to P32, P40 to P43,
4.0 V ≤ EVDD ≤ 5.5 V, EVDD−1.5
P50 to P54, P70 to P74, P120,
IOH1 = −10 mA
P125 to P127, P130, P140 to P147
TYP.
MAX.
Unit
V
4.0 V ≤ EVDD ≤ 5.5 V, EVDD−0.7
V
IOH1 = −3.0 mA
2.7 V ≤ EVDD ≤ 5.5 V, EVDD−0.6
V
IOH1 = −2.0 mA
1.8 V ≤ EVDD ≤ 5.5 V, EVDD−0.5
V
IOH1 = −1.5 mA
1.6 V ≤ EVDD ≤ 5.5 V, EVDD−0.5
V
IOH1 = −1.0 mA
VOH2
P20, P21
1.6 V ≤ VDD ≤ 5.5 V,
VDD−0.5
V
IOH2 = −100 μ A
Output voltage,
VOL1
low
P10 to P17, P30 to P32, P40 to P43,
4.0 V ≤ EVDD ≤ 5.5 V,
P50 to P54, P70 to P74, P120,
IOL1 = 20 mA
P125 to P127, P130, P140 to P147
4.0 V ≤ EVDD ≤ 5.5 V,
1.3
V
0.7
V
0.6
V
0.4
V
0.4
V
0.4
V
0.4
V
2.0
V
0.4
V
0.4
V
0.4
V
0.4
V
IOL1 = 8.5 mA
2.7 V ≤ EVDD ≤ 5.5 V,
IOL1 = 3.0 mA
2.7 V ≤ EVDD ≤ 5.5 V,
IOL1 = 1.5 mA
1.8 V ≤ EVDD ≤ 5.5 V,
IOL1 = 0.6 mA
1.6 V ≤ EVDD < 5.5 V,
IOL1 = 0.3 mA
VOL2
P20, P21
1.6 V ≤ VDD ≤ 5.5 V,
IOL2 = 400 μ A
VOL3
P60, P61
4.0 V ≤ EVDD ≤ 5.5 V,
IOL3 = 15.0 mA
4.0 V ≤ EVDD ≤ 5.5 V,
IOL3 = 5.0 mA
2.7 V ≤ EVDD ≤ 5.5 V,
IOL3 = 3.0 mA
1.8 V ≤ EVDD ≤ 5.5 V,
IOL3 = 2.0 mA
1.6 V ≤ EVDD < 5.5 V,
IOL3 = 1.0 mA
Caution P10, P12, P15, P17 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 27 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Input leakage
Symbol
ILIH1
Conditions
P10 to P17, P30 to P32,
(5/5)
MIN.
TYP.
MAX.
Unit
VI = EVDD
1
μA
1
μA
1
μA
10
μA
VI = EVSS
−1
μA
−1
μA
−1
μA
−10
μA
P40 to P43, P50 to P54, P60,
current, high
P61, P70 to P74, P120,
P125 to P127, P140 to P147
ILIH2
P20, P21, P137, RESET
VI = VDD
ILIH3
P121 to P124
VI = VDD
In input port or
(X1, X2, XT1, XT2, EXCLK,
external clock
EXCLKS)
input
In resonator
connection
Input leakage
ILIL1
P10 to P17, P30 to P32,
P40 to P43, P50 to P54, P60,
current, low
P61, P70 to P74, P120,
P125 to P127, P140 to P147
ILIL2
P20, P21, P137, RESET
VI = VSS
ILIL3
P121 to P124
VI = VSS
In input port or
(X1, X2, XT1, XT2, EXCLK,
external clock
EXCLKS)
input
In resonator
connection
On-chip pll-up
RU1
VI = EVSS
resistance
RU2
SEGxx port
2.4 V ≤ EVDD = VDD ≤ 5.5 V
10
20
100
kΩ
1.6 V ≤ EVDD = VDD < 2.4 V
10
30
100
kΩ
10
20
100
kΩ
Ports other than above
(Except for P60, P61, and
P130)
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 28 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
2.3.2 Supply current characteristics
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter Symbol
Supply
current
Note 1
IDD1
Conditions
Operating HS (highspeed main)
mode
Note 5
mode
fIH = 24 MHz
fIH = 16 MHz
Note 3
Note 3
LS (low-speed fIH = 8 MHz
Note
main) mode
Note 3
LV (lowvoltage main)
Note 5
mode
fIH = 4 MHz
Note 3
HS (highspeed main)
Note 5
mode
fMX = 20 MHz
5
Note 2
,
VDD = 5.0 V
fMX = 20 MHz
Note 2
,
VDD = 3.0 V
fMX = 10 MHz
MAX.
Basic
VDD = 5.0 V
operation VDD = 3.0 V
1.5
mA
1.5
mA
Normal
VDD = 5.0 V
operation VDD = 3.0 V
3.3
5.0
3.3
5.0
mA
Normal
VDD = 5.0 V
operation VDD = 3.0 V
2.5
3.7
mA
2.5
3.7
mA
Normal
VDD = 3.0 V
operation VDD = 2.0 V
1.2
1.8
mA
1.2
1.8
mA
Normal
VDD = 3.0 V
operation VDD = 2.0 V
1.2
1.7
mA
1.2
1.7
mA
Normal
Square wave input
operation Resonator connection
2.8
4.4
mA
3.0
4.6
mA
Normal
Square wave input
operation Resonator connection
2.8
4.4
mA
3.0
4.6
mA
1.8
2.6
mA
1.8
2.6
mA
Normal
Square wave input
operation Resonator connection
1.8
2.6
mA
1.8
2.6
mA
Normal
Square wave input
operation Resonator connection
1.1
1.7
mA
1.1
1.7
mA
Normal
Square wave input
operation Resonator connection
1.1
1.7
mA
1.1
1.7
mA
3.5
4.9
μA
3.6
5.0
μA
,
Note 2
fMX = 8 MHz
Note 2
,
,
VDD = 2.0 V
Note
fSUB = 32.768 kHz
4
Normal
Square wave input
operation Resonator connection
TA = −40°C
f
Note
= 32.768 kHz
Normal
Square wave input
operation Resonator connection
3.6
4.9
μA
3.7
5.0
μA
Normal
Square wave input
operation Resonator connection
3.7
5.5
μA
3.8
5.6
μA
Normal
Square wave input
operation Resonator connection
3.8
6.3
μA
3.9
6.4
μA
Normal
Square wave input
operation Resonator connection
4.1
7.7
μA
4.2
7.8
μA
TA = +25°C
f
SUB
4
Note
= 32.768 kHz
TA = +50°C
f
SUB
4
Note
= 32.768 kHz
TA = +70°C
f
SUB
4
Note
= 32.768 kHz
TA = +85°C
mA
Note 2
LS (low-speed fMX = 8 MHz
Note
main) mode
VDD = 3.0 V
5
SUB
4
Unit
Normal
Square wave input
operation Resonator connection
,
VDD = 3.0 V
Subsystem
clock
operation
TYP.
Note 2
VDD = 5.0 V
fMX = 10 MHz
(1/3)
MIN.
(Notes and Remarks are listed on the next page.)
R01DS0157EJ0210 Rev.2.10
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Page 29 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
Notes 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input
pin is fixed to VDD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral operation
current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip
pull-up/pull-down resistors and the current flowing during data flash rewrite.
2. When high-speed on-chip oscillator and subsystem clock are stopped.
3. When high-speed system clock and subsystem clock are stopped.
4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low
power consumption oscillation). However, not including the current flowing into the RTC, 12-bit interval timer,
watchdog timer, and LCD controller/driver.
5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
LS (low-speed main) mode:
1.8 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 30 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Supply
current
Symbol
I
DD2
Note 2
Note 1
Conditions
HALT
mode
HS (highspeed main)
Note 7
mode
fIH = 24 MHz
fIH = 16 MHz
MIN.
Note 4
LV (lowvoltage
main) mode
fIH = 4 MHz
HS (highspeed main)
Note 7
mode
fMX = 20 MHz
MAX.
Unit
mA
VDD = 5.0 V
0.44
1.28
0.44
1.28
mA
VDD = 5.0 V
0.40
1.00
mA
VDD = 3.0 V
0.40
1.00
mA
VDD = 3.0 V
260
530
μA
VDD = 2.0 V
260
530
μA
VDD = 3.0 V
420
640
μA
VDD = 2.0 V
420
640
μA
Note 3
Square wave input
0.28
1.00
mA
Resonator connection
0.45
1.17
mA
Note 3
Square wave input
0.28
1.00
mA
Resonator connection
0.45
1.17
mA
Square wave input
0.19
0.60
mA
Resonator connection
0.26
0.67
mA
Square wave input
0.19
0.60
mA
Resonator connection
0.26
0.67
mA
Note 4
fIH = 8 MHz
TYP.
VDD = 3.0 V
Note 4
LS (lowspeed main)
Note 7
mode
(2/3)
Note 4
Note 7
,
VDD = 5.0 V
fMX = 20 MHz
,
VDD = 3.0 V
fMX = 10 MHz
Note 3
,
VDD = 5.0 V
fMX = 10 MHz
Note 3
,
VDD = 3.0 V
LS (lowspeed main)
Note 7
mode
fMX = 8 MHz
Note 3
,
Square wave input
95
330
μA
Resonator connection
145
380
μA
Note 3
,
Square wave input
95
330
μA
Resonator connection
145
380
μA
VDD = 3.0 V
fMX = 8 MHz
VDD = 2.0 V
Subsystem
clock
operation
Note 5
fSUB = 32.768 kHz
Square wave input
0.31
0.57
μA
TA = −40°C
Resonator connection
0.50
0.76
μA
Note 5
fSUB = 32.768 kHz
Square wave input
0.37
0.57
μA
TA = +25°C
Resonator connection
0.56
0.76
μA
Note 5
Square wave input
0.46
1.17
μA
Resonator connection
0.65
1.36
μA
fSUB = 32.768 kHz
Note 5
Square wave input
0.57
1.97
μA
TA = +70°C
Resonator connection
0.76
2.16
μA
fSUB = 32.768 kHz
TA = +50°C
Note 5
I
Note 6
DD3
fSUB = 32.768 kHz
Square wave input
0.85
3.37
μA
TA = +85°C
Resonator connection
1.04
3.56
μA
STOP
TA = −40°C
Note 8
mode
TA = +25°C
0.17
0.50
μA
0.23
0.50
μA
TA = +50°C
0.32
1.10
μA
TA = +70°C
0.43
1.90
μA
TA = +85°C
0.71
3.30
μA
(Notes and Remarks are listed on the next page.)
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 31 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
Notes 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input
pin is fixed to VDD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral operation
current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip
pull-up/pull-down resistors and the current flowing during data flash rewrite.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator and subsystem clock are stopped.
4. When high-speed system clock and subsystem clock are stopped.
5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting
ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not
including the current flowing into the 12-bit interval timer, watchdog timer, and LCD controller/driver.
6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer.
7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
LS (low-speed main) mode:
1.8 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz
8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode.
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Low-speed on-
Symbol
IFIL
Conditions
(3/3)
MIN.
Note 1
TYP.
MAX.
Unit
0.20
μA
0.08
μA
0.08
μA
0.24
μA
chip oscillator
operating
current
RTC operating
IRTC
current
Notes 1, 2, 3
12-bit interval
IIT
timer current
Notes 1, 2, 4
fMAIN is stopped
Watchdog timer
IWDT
operating
Notes 1, 2, 5
fIL = 15 kHz
current
A/D converter
operating
current
IADC
Notes 1, 6
A/D converter
reference
voltage current
IADREF
Temperature
sensor
operating
current
ITMPS
When conversion
at maximum speed
Normal mode, AVREFP = VDD = 5.0 V
1.3
1.7
mA
Low voltage mode, AVREFP = VDD = 3.0 V
0.5
0.7
mA
Note 1
Note 1
LVD operating
ILVD
current
Notes 1, 7
Self-
IFSP
programming
Notes 1, 9
75.0
μA
75.0
μA
0.08
μA
2.50
12.20
mA
2.00
12.20
mA
0.04
0.20
μA
1.12
3.70
μA
0.63
2.20
μA
0.12
0.50
μA
0.50
0.60
mA
1.20
1.44
mA
0.70
0.84
mA
operating
current
BGO operating
IBGO
current
Notes 1, 8
LCD operating
ILCD1
current
Notes 11, 12
ILCD2
External resistance division method
Note 11
VDD = EVDD = 5.0 V
VL4 = 5.0 V
Internal voltage boosting method
VDD = EVDD = 5.0 V
VL4 = 5.1 V (VLCD = 12H)
VDD = EVDD = 3.0 V
VL4 = 3.0 V (VLCD = 04H)
ILCD3
Note 11
Capacitor split method
ISNOZ
Note 1
ADC operation
VDD = EVDD = 3.0 V
VL4 = 3.0 V
SNOOZE
operating
The mode is performed
Note 10
The A/D conversion operations are
current
performed, Low voltage mode, AVREFP = VDD
= 3.0 V
CSI/UART operation
(Notes and Remarks are listed on the next page.)
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
Notes 1. Current flowing to VDD.
2. When high speed on-chip oscillator and high-speed system clock are stopped.
3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed on-chip
oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of
either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode. When the
low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the
operational current of the real-time clock.
4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip
oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of
either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT mode. When the
low-speed on-chip oscillator is selected, IFIL should be added.
5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator).
The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog
timer is in operation.
6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or
IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.
7. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2
or IDD3 and ILVD when the LVD circuit is in operation.
8. Current flowing only during data flash rewrite.
9. Current flowing only during self programming.
10. For shift time to the SNOOZE mod.
11. Current flowing only to the LCD controller/driver. The supply current value of the RL78 microcontrollers is the
sum of the LCD operating current (ILCD1, ILCD2 or ILCD3) to the supply current (IDD1 or IDD2) when the LCD
controller/driver operates in an operation mode or HALT mode. Not including the current that flows through the
LCD panel.
The TYP. value and MAX. value are following conditions.
• When fSUB is selected for system clock, LCD clock = 128 Hz (LCDC0 = 07H)
• 4-Time-Slice, 1/3 Bias Method
12. Not including the current that flows through the external divider resistor when the external resistance division
method is used.
Remarks 1. fIL:
Low-speed on-chip oscillator clock frequency
2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
3. fCLK: CPU/peripheral hardware clock frequency
4. Temperature condition of the TYP. value is TA = 25°C
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
2.4 AC Characteristics
2.4.1 Basic operation
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Instruction cycle (minimum
instruction execution time)
Symbol
TCY
Conditions
MIN.
LS (low-speed 1.8 V ≤ VDD ≤ 5.5 V
main) mode
0.125
1.8 V ≤ VDD ≤ 5.5 V
28.5
Subsystem clock (fSUB)
operation
In the self
HS (high-speed 2.7 V ≤ VDD ≤ 5.5 V 0.04167
programmin main) mode
2.4 V ≤ VDD < 2.7 V 0.0625
g mode
LV (low voltage 1.8 V ≤ VDD ≤ 5.5 V 0.25
main) mode
LS (low-speed 1.8 V ≤ VDD ≤ 5.5 V
main) mode
External main system clock
frequency
fEX
tEXH, tEXL
TO00 to TO07 output frequency
fTO
PCLBUZ0, PCLBUZ1 output
frequency
Interrupt input high-level width,
low-level width
fPCL
tINTH,
tINTL
Key interrupt input low-level width tKR
RESET low-level width
Remark
μs
1
μs
1
μs
1
μs
31.3
μs
1
1
μs
μs
μs
1
μs
MHz
1
1.0
20.0
1.0
16.0
MHz
1.8 V ≤ VDD < 2.4 V
1.0
8.0
MHz
1.6 V ≤ VDD < 1.8 V
1.0
4.0
MHz
32
35
kHz
2.7 V ≤ VDD ≤ 5.5 V
24
ns
2.4 V ≤ VDD < 2.7 V
30
ns
1.8 V ≤ VDD < 2.4 V
60
ns
1.6 V ≤ VDD < 1.8 V
tTIH,
tTIL
Unit
1
2.7 V ≤ VDD ≤ 5.5 V
tEXHS,
tEXLS
TI00 to TI07 input high-level
width, low-level width
0.125
30.5
MAX.
2.4 V ≤ VDD < 2.7 V
fEXS
External main system clock input
high-level width, low-level width
TYP.
Main
HS (high-speed 2.7 V ≤ VDD ≤ 5.5 V 0.04167
system
main) mode
2.4 V ≤ VDD < 2.7 V 0.0625
clock (fMAIN)
LV (low voltage 1.6 V ≤ VDD ≤ 5.5 V 0.25
operation
main) mode
120
ns
13.7
μs
1/fMCK+10
ns
4.0 V ≤ EVDD ≤ 5.5 V
16
MHz
2.7 V ≤ EVDD < 4.0 V
8
MHz
2.4 V ≤ EVDD < 2.7 V
4
MHz
LS (low-speed
main) mode
1.8 V ≤ EVDD ≤ 5.5 V
4
MHz
LV (low voltage
main) mode
1.6 V ≤ EVDD ≤ 5.5 V
2
MHz
HS (high-speed
main) mode
4.0 V ≤ EVDD ≤ 5.5 V
16
MHz
2.7 V ≤ EVDD < 4.0 V
8
MHz
2.4 V ≤ EVDD < 2.7 V
4
MHz
LS (low-speed
main) mode
1.8 V ≤ EVDD ≤ 5.5 V
4
MHz
LV (low-voltage
main) mode
1.8 V ≤ EVDD ≤ 5.5 V
4
MHz
1.6 V ≤ EVDD < 1.8 V
2
MHz
INTP0
1.6 V ≤ VDD ≤ 5.5 V
HS (high-speed
main) mode
1
μs
μs
INTP1 to INTP7
1.6 V ≤ EVDD ≤ 5.5 V
1
KR0 to KR3
1.8 V ≤ EVDD ≤ 5.5 V
250
ns
1.6 V ≤ EVDD < 1.8 V
1
μs
μs
tRSL
10
fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKS0n bit of timer mode register 0n (TMR0n). n: Channel number (n = 0 to 7))
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
Minimum Instruction Execution Time during Main System Clock Operation
TCY vs VDD (HS (high-speed main) mode)
10
Cycle time TCY [µs]
1.0
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
0.1
0.0625
0.04167
0.01
0
1.0
2.0
3.0
2.4 2.7
4.0
5.0
6.0
5.5
Supply voltage VDD [V]
TCY vs VDD (LS (low-speed main) mode)
Cycle time TCY [µs]
10
1.0
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
0.125
0.1
0.01
0
1.0
2.0
1.8
3.0
4.0
5.0 5.5 6.0
Supply voltage VDD [V]
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
TCY vs VDD (LV (low-voltage main) mode)
Cycle time TCY [µs]
10
1.0
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
0.25
0.1
0.01
0
1.0
2.0
1.6 1.8
3.0
4.0
5.0 5.5 6.0
Supply voltage VDD [V]
AC Timing Test Points
VIH/VOH
VIL/VOL
VIH/VOH
Test points
VIL/VOL
External System Clock Timing
1/fEX/
1/fEXS
t EXL/
t EXLS
t EXH/
t EXHS
EXCLK/EXCLKS
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
TI/TO Timing
t TIH
t TIL
TI00 to TI07
1/fTO
TO00 to TO07
Interrupt Request Input Timing
t INTH
t INTL
INTP0 to INTP7
Key Interrupt Input Timing
t KR
KR0 to KR3
RESET Input Timing
t RSL
RESET
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
2.5 Peripheral Functions Characteristics
AC Timing Test Points
VIH/VOH
VIH/VOH
Test points
VIL/VOL
VIL/VOL
2.5.1 Serial array unit
(1) During communication at same potential (UART mode)
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Transfer rate
Symbol
Note 1
Conditions
2.4 V ≤ EVDD = VDD ≤ 5.5 V
Theoretical value of the
HS (high-speed LS (low-speed LV (low-voltage
main) Mode
main) Mode
main) Mode
MIN.
MIN.
MIN.
MAX.
MAX.
Unit
MAX.
fMCK/6
fMCK/6
fMCK/6
bps
4.0
1.3
0.6
Mbps
fMCK/6
fMCK/6
bps
1.3
0.6
Mbps
fMCK/6
bps
0.6
Mbps
maximum transfer rate
fMCK = fCLK
Note 2
1.8 V ≤ EVDD = VDD ≤ 5.5 V
Theoretical value of the
maximum transfer rate
fMCK = fCLK
Note 2
1.6 V ≤ EVDD = VDD ≤ 5.5 V
Theoretical value of the
maximum transfer rate
fMCK = fCLK
Note 2
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode:
24 MHz (2.7 V ≤ VDD ≤ 5.5 V)
16 MHz (2.4 V ≤ VDD ≤ 5.5 V)
LS (low-speed main) mode:
8 MHz (1.8 V ≤ VDD ≤ 5.5 V)
LV (low-voltage main) mode:
4 MHz (1.6 V ≤ VDD ≤ 5.5 V)
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
UART mode connection diagram (during communication at same potential)
Rx
TxDq
User's device
RL78 microcontroller
RxDq
Tx
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Remarks 1.
2.
q: UART number (q = 0), g: PIM and POM number (g = 1)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01))
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
SCKp cycle time
Symbol
tKCY1
Conditions
2.7 V ≤ EVDD ≤ 5.5 V
2.4 V ≤ EVDD ≤ 5.5 V
HS (high-speed LS (low-speed LV (low-voltage
main) Mode
main) Mode
main) Mode
MIN.
MIN.
MIN.
MAX.
MAX.
167
500
1000
Note 1
Note 1
Note 1
250
500
1000
Note 1
Note 1
Note 1
500
1000
Note 1
Note 1
1.8 V ≤ EVDD ≤ 5.5 V
1.6 V ≤ EVDD ≤ 5.5 V
Unit
MAX.
ns
ns
ns
ns
1000
Note 1
SCKp high-/low-level width
tKH1,
4.0 V ≤ EVDD ≤ 5.5 V
tKL1
2.7 V ≤ EVDD ≤ 5.5 V
2.4 V ≤ EVDD ≤ 5.5 V
tKCY1/2
tKCY1/2
tKCY1/2
− 12
− 50
− 50
tKCY1/2
tKCY1/2
tKCY1/2
− 18
− 50
− 50
tKCY1/2
tKCY1/2
tKCY1/2
− 38
− 50
− 50
tKCY1/2
tKCY1/2
− 50
− 50
1.8 V ≤ EVDD ≤ 5.5 V
1.6 V ≤ EVDD ≤ 5.5 V
ns
ns
ns
ns
tKCY1/2
ns
− 100
SIp setup time (to SCKp↑)
tSIK1
Note 2
2.7 V ≤ EVDD ≤ 5.5 V
44
110
110
ns
2.4 V ≤ EVDD ≤ 5.5 V
75
110
110
ns
110
110
ns
1.8 V ≤ EVDD ≤ 5.5 V
1.6 V ≤ EVDD ≤ 5.5 V
SIp hold time (from SCKp↑) tKSI1
Note 3
2.4 V ≤ EVDD ≤ 5.5 V
19
1.8 V ≤ EVDD ≤ 5.5 V
220
ns
19
19
ns
19
19
1.6 V ≤ EVDD ≤ 5.5 V
Delay time from SCKp↓ to
SOp output
tKSO1
Note 4
C = 30 pF 2.4 V ≤ EVDD ≤ 5.5 V
Note 5
19
25
1.8 V ≤ EVDD ≤ 5.5 V
25
25
25
25
1.6 V ≤ EVDD ≤ 5.5 V
ns
25
Notes 1. For CSI00, set a cycle of 2/fMCK or longer. For CSI01, set a cycle of 4/fMCK or longer.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin
by using port input mode register g (PIMg) and port output mode register g (POMg).
(Remarks are listed on the next page.)
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
Remarks 1.
p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM numbers (g = 1)
fMCK: Serial array unit operation clock frequency
2.
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00, 01))
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(1/2)
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
SCKp cycle time
Symbol
Note
tKCY2
Conditions
4.0 V ≤ EVDD ≤ 5.5 V
5
2.7 V ≤ EVDD < 4.0 V
HS (high-speed LS (low-speed LV (low-voltage
main) Mode
main) Mode
main) Mode
MIN.
MIN.
MIN.
MAX.
MAX.
Unit
MAX.
20 MHz < fMCK
8/fMCK
fMCK ≤ 20 MHz
6/fMCK
16 MHz < fMCK
8/fMCK
fMCK ≤ 16 MHz
6/fMCK
6/fMCK
6/fMCK
ns
6/fMCK
6/fMCK
6/fMCK
ns
6/fMCK
6/fMCK
ns
6/fMCK
ns
ns
2.4 V ≤ EVDD ≤ 5.5 V
ns
6/fMCK
6/fMCK
ns
ns
and
500
1.8 V ≤ EVDD < 2.4 V
1.6 V ≤ EVDD < 1.8 V
SCKp high-/low-
tKH2,
level width
tKL2
4.0 V ≤ EVDD ≤ 5.5 V
2.7 V ≤ EVDD < 4.0 V
2.4 V ≤ EVDD < 2.7 V
tKCY2/2
tKCY2/2
tKCY2/2
−7
−7
−7
tKCY2/2
tKCY2/2
tKCY2/2
−8
−8
−8
tKCY2/2
tKCY2/2
tKCY2/2
− 18
− 18
− 18
tKCY2/2
tKCY2/2
− 18
− 18
1.8 V ≤ EVDD < 2.4 V
1.6 V ≤ EVDD < 1.8 V
tKCY2/2
ns
ns
ns
ns
− 66
SIp setup time
tSIK2
2.7 V ≤ EVDD ≤ 5.5 V
Note 1
(to SCKp↑)
2.4 V ≤ EVDD < 2.7 V
1/fMCK
1/fMCK
1/fMCK
+ 20
+ 30
+ 30
1/fMCK
1/fMCK
1/fMCK
+ 30
+ 30
+ 30
1/fMCK
1/fMCK
+ 30
+ 30
1.8 V ≤ EVDD < 2.4 V
1.6 V ≤ EVDD < 1.8 V
1/fMCK
ns
ns
ns
+ 40
SIp hold time
tKSI2
2.4 V ≤ EVDD ≤ 5.5 V
Note 2
(from SCKp↑)
1.8 V ≤ EVDD < 2.4 V
1.6 V ≤ EVDD < 1.8 V
1/fMCK
1/fMCK
1/fMCK
+ 31
+ 31
+ 31
1/fMCK
1/fMCK
+ 31
+ 31
1/fMCK
ns
ns
ns
+
250
(Notes, Caution, and Remarks are listed on the next page.)
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(2/2)
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
HS
Conditions
LS (low- LV (low-
(high-
speed
voltage
speed
main)
main)
main)
Mode
Mode
Unit
Para
Symbol Conditions
meter
Mode
Delay time from
tKSO2
C = 30 pF
Note 4
4.0 V ≤ EVDD ≤ 5.5 V
SCKp↓ to SOp
output
Note 3
2.7 V ≤ EVDD < 4.0 V
2.4 V ≤ EVDD < 2.7 V
2/fMCK
2/fMCK
2/fMCK
+ 44
+ 110
+ 110
2/fMCK
2/fMCK
2/fMCK
+ 44
+ 110
+ 110
2/fMCK
2/fMCK
2/fMCK
+ 75
+ 110
+ 110
1.8 V ≤ EVDD < 2.4 V
2/fMCK
2/fMCK
+ 110
+ 110
1.6 V ≤ EVDD < 1.8 V
2/fMCK
ns
ns
ns
ns
ns
+ 220
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SCKp and SOp output lines.
5. Transfer rate in the SNOOZE mode: MAX. 1 Mbps
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin
by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0),
n: Channel number (n = 0, 1), g: PIM number (g = 1)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01))
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
CSI mode connection diagram (during communication at same potential)
SCK
SCKp
RL78
SIp
microcontroller
SO User's device
SOp
SI
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
t KCY1, 2
t KL1, 2
t KH1, 2
SCKp
t SIK1, 2
SIp
t KSI1, 2
Input data
t KSO1, 2
Output data
SOp
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
t KCY1, 2
t KH1, 2
t KL1, 2
SCKp
t SIK1, 2
SIp
t KSI1, 2
Input data
t KSO1, 2
SOp
Remarks 1.
2.
Output data
p: CSI number (p = 00, 01)
m: Unit number, n: Channel number (mn = 00, 01)
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
(4) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode)
(1/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
LS (low-speed
LV (low-voltage
main) Mode
main) Mode
main) Mode
MIN.
Transfer rate
Reception
4.0 V ≤ EVDD ≤ 5.5 V,
MAX.
MIN.
MAX.
fMCK/6
Note 1
Note 1
4.0
1.3
0.6
Mbps
fMCK/6
fMCK/6
fMCK/6
bps
Note 1
Note 1
4.0
1.3
0.6
Mbps
fMCK/6
fMCK/6
fMCK/6
bps
Note 1
Note 1
1.3
0.6
Mbps
bps
Note 1
Theoretical value of the
MIN.
fMCK/6
fMCK/6
2.7 V ≤ Vb ≤ 4.0 V
MAX.
Unit
bps
maximum transfer rate
fMCK = fCLK
Note 3
2.7 V ≤ EVDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
Note 1
Theoretical value of the
maximum transfer rate
fMCK = fCLK
Note 3
2.4 V ≤ EVDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Note 1
Theoretical value of the
4.0
maximum transfer rate
fMCK = fCLK
Note 3
1.8 V ≤ EVDD < 3.3 V,
fMCK/6
fMCK/6
1.6 V ≤ Vb ≤ 2.0 V
Notes 1, 2
Notes 1, 2
1.3
0.6
Theoretical value of the
Mbps
maximum transfer rate
fMCK = fCLK
Note 3
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
2. Use it with EVDD ≥ Vb.
3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode:
24 MHz (2.7 V ≤ VDD ≤ 5.5 V)
16 MHz (2.4 V ≤ VDD ≤ 5.5 V)
Caution
LS (low-speed main) mode:
8 MHz (1.8 V ≤ VDD ≤ 5.5 V)
LV (low-voltage main) mode:
4 MHz (1.6 V ≤ VDD ≤ 5.5 V)
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (32-pin to 52pin products)/EVDD tolerance (64-pin products)) mode for the TxDq pin by using port input mode
register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics
with TTL input buffer selected.
Remarks 1.
2.
3.
Vb[V]: Communication line voltage
q: UART number (q = 0), g: PIM and POM number (g = 1)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
(4) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode)
(2/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
LS (low-speed
LV (low-voltage
main) Mode
main) Mode
main) Mode
MIN.
Transfer rate
Transmissio
4.0 V ≤ EVDD ≤ 5.5 V,
n
2.7 V ≤ Vb ≤ 4.0 V
MAX.
Note 1
Theoretical value of the
2.8
Note 2
MIN.
MAX.
MIN.
Note 1
2.8
MAX.
Note 1
Note 2
Unit
2.8
Note 2
bps
Mbps
maximum transfer rate
Cb = 50 pF, Rb = 1.4 kΩ,
Vb = 2.7 V
2.7 V ≤ EVDD < 4.0 V,
Note 3
Note 3
Note 3
bps
2.3 V ≤ Vb ≤ 2.7 V
Theoretical value of the
1.2
Note 4
1.2
Note 4
1.2
Note 4
Mbps
maximum transfer rate
Cb = 50 pF, Rb = 2.7 kΩ
Vb = 2.3 V
2.4 V ≤ EVDD < 3.3 V,
Note 6
Note 6
Note 6
bps
1.6 V ≤ Vb ≤ 2.0 V
Theoretical value of the
0.43
Note 7
0.43
Note 7
0.43
Note 7
Mbps
maximum transfer rate
Cb = 50 pF, Rb = 5.5 kΩ
Vb = 1.6 V
1.8 V ≤ EVDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Notes
Notes
5, 6
5, 6
Note 7
Theoretical value of the
0.43
0.43
Note 7
bps
Mbps
maximum transfer rate
Cb = 50 pF, Rb = 5.5 kΩ,
Vb = 1.6 V
Notes 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 4.0 V ≤ EVDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V
1
Maximum transfer rate =
{−Cb × Rb × ln (1 −
Baud rate error (theoretical value) =
2.2
Vb )} × 3
[bps]
2.2
1
− {−Cb × Rb × ln (1 − Vb )}
Transfer rate × 2
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
3. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ EVDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V
1
Maximum transfer rate =
{−Cb × Rb × ln (1 −
Baud rate error (theoretical value) =
2.0
Vb )} × 3
[bps]
2.0
1
− {−Cb × Rb × ln (1 − Vb )}
Transfer rate × 2
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
4.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
5.
6.
Use it with EVDD ≥ Vb.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 1.8 V ≤ EVDD < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V
1
Maximum transfer rate =
{−Cb × Rb × ln (1 −
Baud rate error (theoretical value) =
1.5
Vb )} × 3
[bps]
1.5
1
− {−Cb × Rb × ln (1 − Vb )}
Transfer rate × 2
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
7.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (32-pin to 52pin products)/EVDD tolerance (64-pin products)) mode for the TxDq pin by using port input mode
register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics
with TTL input buffer selected.
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Sep 30, 2016
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
UART mode connection diagram (during communication at different potential)
Vb
Rb
Rx
TxDq
RL78 microcontroller
User's device
RxDq
Tx
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Remarks 1.
Rb[Ω]:Communication line (TxDq) pull-up resistance,
Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
2.
q: UART number (q = 0, 1), g: PIM and POM number (g = 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01))
R01DS0157EJ0210 Rev.2.10
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
(5) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only)
(TA = −40 to +85°C, 2.7 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
HS (high-
LS (low-speed
LV (low-
speed main)
main) Mode
voltage main)
Mode
MIN.
SCKp cycle time
tKCY1
tKCY1 ≥ 2/fCLK 4.0 V ≤ EVDD ≤ 5.5 V,
MAX.
Mode
MIN.
MAX.
MIN.
200
1150
1150
Note 1
Note 1
Note 1
2.7 V ≤ EVDD < 4.0 V,
300
1150
1150
2.3 V ≤ Vb ≤ 2.7 V,
Note 1
Note 1
Note 1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2
− 50
Cb = 20 pF, Rb = 1.4 kΩ
tKCY1/2
tKCY1/2
− 50
− 50
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2
tKCY1/2
tKCY1/2
− 120
− 120
− 120
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2
tKCY1/2
tKCY1/2
− 50
− 50
2.7 V ≤ Vb ≤ 4.0 V,
Unit
MAX.
ns
Cb = 20 pF, Rb = 1.4 kΩ
ns
Cb = 20 pF, Rb = 2.7 kΩ
SCKp high-level width
tKH1
Cb = 20 pF, Rb = 2.7 kΩ
SCKp low-level width
tKL1
Cb = 20 pF, Rb = 1.4 kΩ
−7
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2
Cb = 20 pF, Rb = 2.7 kΩ
SIp setup time
(to SCKp↑)
tSIK1
Note 2
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
ns
ns
ns
tKCY1/2
tKCY1/2
− 10
− 50
− 50
58
479
479
ns
121
479
479
ns
10
10
10
ns
10
10
10
ns
ns
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SIp hold time
(from SCKp↑)
tKSI1
Note 2
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
Delay time from SCKp↓ to
SOp output
tKSO1
Note 2
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
60
60
60
ns
130
130
130
ns
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SIp setup time
(to SCKp↓)
tSIK1
Note 3
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
23
110
110
ns
33
110
110
ns
10
10
10
ns
10
10
10
ns
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SIp hold time
(from SCKp↓)
tKSI1
Note 3
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
Delay time from SCKp↑ to
SOp output
tKSO1
Note 3
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
10
10
10
ns
10
10
10
ns
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
(Notes, Caution and Remarks are listed on the next page.)
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
Notes 1. For CSI00, set a cycle of 2/fMCK or longer. For CSI01, set a cycle of 4/fMCK or longer.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
3. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (32-pin to 52pin products)/EVDD tolerance (64-pin products)) mode for the SOp pin and SCKp pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
For VIH and VIL, see the DC
characteristics with TTL input buffer selected.
Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load
capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM number (g = 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)
R01DS0157EJ0210 Rev.2.10
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (1/3)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
HS (high-
LS (low-speed
LV (low-
speed main)
main) Mode
voltage main)
Mode
MIN.
SCKp cycle time
tKCY1
tKCY1 ≥ 4/fCLK
4.0 V ≤ EVDD ≤ 5.5 V,
MAX.
Unit
Mode
MIN.
MAX.
MIN.
MAX.
300
1150
1150
ns
500
1150
1150
ns
1150
1150
1150
ns
1150
1150
ns
tKCY1/2
tKCY1/2
tKCY1/2
ns
− 75
− 75
− 75
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
1.8 V ≤ EVDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Note
,
Cb = 30 pF, Rb = 5.5 kΩ
SCKp high-level width
tKH1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
tKCY1/2
tKCY1/2
tKCY1/2
Cb = 30 pF, Rb = 2.7 kΩ
− 170
− 170
− 170
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
tKCY1/2
tKCY1/2
tKCY1/2
Cb = 30 pF, Rb = 5.5 kΩ
− 458
− 458
− 458
tKCY1/2
tKCY1/2
− 458
− 458
tKCY1/2
tKCY1/2
tKCY1/2
− 12
− 50
− 50
tKCY1/2
tKCY1/2
tKCY1/2
− 18
− 50
− 50
tKCY1/2
tKCY1/2
tKCY1/2
− 50
− 50
− 50
tKCY1/2
tKCY1/2
− 50
− 50
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Note
,
Cb = 30 pF, Rb = 5.5 kΩ
SCKp low-level width
tKL1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Cb = 30 pF, Rb = 5.5 kΩ
Note
Caution
Note
,
ns
ns
ns
ns
ns
ns
ns
Use it with EVDD ≥ Vb.
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (32-pin to 52pin products)/EVDD tolerance (64-pin products)) mode for the SOp pin and SCKp pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
For VIH and VIL, see the DC
characteristics with TTL input buffer selected.
R01DS0157EJ0210 Rev.2.10
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (2/3)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
HS (high-
LS (low-
LV (low-
Unit
speed main) speed main) voltage main)
Mode
Mode
Mode
MIN. MAX. MIN. MAX. MIN. MAX.
SIp setup time
Note 1
(to SCKp↑)
tSIK1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
81
479
479
ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
177
479
479
ns
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
479
479
479
ns
479
479
ns
1.8 V ≤ EVDD < 3.3 V,
Note 3
,
1.6 V ≤ Vb ≤ 2.0 V
Cb = 30 pF, Rb = 5.5 kΩ
SIp hold time
Note 1
(from SCKp↑)
tKSI1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
19
19
19
ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
19
19
19
ns
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
19
19
19
ns
19
19
ns
1.8 V ≤ EVDD < 3.3 V,
Note 3
,
1.6 V ≤ Vb ≤ 2.0 V
Cb = 30 pF, Rb = 5.5 kΩ
Delay time from SCKp↓ to
Note 1
SOp output
tKSO1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
100
100
100
ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
195
195
195
ns
2.4 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
483
483
483
ns
483
483
ns
1.8 V ≤ EVDD < 3.3 V,
Note 3
,
1.6 V ≤ Vb ≤ 2.0 V
Cb = 30 pF, Rb = 5.5 kΩ
SIp setup time
Note 2
(to SCKp↓)
tSIK1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
44
110
110
ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
44
110
110
ns
2.4 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
110
110
110
ns
110
110
ns
1.8 V ≤ EVDD < 3.3 V,
Note 3
,
1.6 V ≤ Vb ≤ 2.0 V
Cb = 30 pF, Rb = 5.5 kΩ
Notes
1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. Use it with EVDD ≥ Vb.
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (32-pin to 52pin products)/EVDD tolerance (64-pin products)) mode for the SOp pin and SCKp pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
For VIH and VIL, see the DC
characteristics with TTL input buffer selected.
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 52 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (3/3)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
HS (high-
LS (low-
LV (low-
Unit
speed main) speed main) voltage main)
Mode
Mode
Mode
MIN. MAX. MIN. MAX. MIN. MAX.
SIp hold time
Note 2
(from SCKp↓)
tKSI1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
19
19
19
ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
19
19
19
ns
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
19
19
19
ns
19
19
ns
1.8 V ≤ EVDD < 3.3 V,
Note 3
,
1.6 V ≤ Vb ≤ 2.0 V
Cb = 30 pF, Rb = 5.5 kΩ
Delay time from SCKp↑ to
Note 2
SOp output
tKSO1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
25
25
25
ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
25
25
25
ns
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
25
25
25
ns
25
25
ns
1.8 V ≤ EVDD < 3.3 V,
Note 3
,
1.6 V ≤ Vb ≤ 2.0 V
Cb = 30 pF, Rb = 5.5 kΩ
Notes
1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. Use it with EVDD ≥ Vb.
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (32-pin to 52pin products)/EVDD tolerance (64-pin products)) mode for the SOp pin and SCKp pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
For VIH and VIL, see the DC
characteristics with TTL input buffer selected.
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 53 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
CSI mode connection diagram (during communication at different potential)
Vb
Rb
SCKp
SIp
RL78
microcontroller
SOp
Vb
Rb
SCK
SO
User's device
SI
Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load
capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM
number (g = 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 54 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
t KCY1
t KL1
t KH1
SCKp
t SIK1
SIp
t KSI1
Input data
t KSO1
SOp
Output data
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
t KCY1
t KL1
t KH1
SCKp
t SIK1
SIp
t KSI1
Input data
t KSO1
SOp
Remark
Output data
p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM number (g = 1)
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 55 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
(1/2)
HS (high-
LS (low-speed
LV (low-
speed main)
main) mode
voltage main)
mode
MIN.
SCKp cycle time
Note 1
tKCY2
4.0 V ≤ EVDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
2.7 V ≤ EVDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
2.4 V ≤ EVDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
1.8 V ≤ EVDD < 3.3 V,
Note 2
1.6 V ≤ Vb ≤ 2.0 V
SCKp high-/low-level
width
tKH2,
tKL2
tSIK2
tKSI2
MIN.
MAX.
MIN.
MAX.
12/fMCK
ns
8 MHz < fMCK ≤ 20 MHz
10/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
8/fMCK
16/fMCK
fMCK ≤ 4 MHz
6/fMCK
10/fMCK
20 MHz < fMCK ≤ 24 MHz
16/fMCK
ns
16 MHz < fMCK ≤ 20 MHz
14/fMCK
ns
8 MHz < fMCK ≤ 16 MHz
12/fMCK
4 MHz < fMCK ≤ 8 MHz
8/fMCK
16/fMCK
fMCK ≤ 4 MHz
6/fMCK
10/fMCK
20 MHz < fMCK ≤ 24 MHz
36/fMCK
ns
16 MHz < fMCK ≤ 20 MHz
32/fMCK
ns
8 MHz < fMCK ≤ 16 MHz
26/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK
16/fMCK
fMCK ≤ 4 MHz
10/fMCK
10/fMCK
ns
10/fMCK
ns
ns
ns
10/fMCK
ns
ns
10/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK
fMCK ≤ 4 MHz
10/fMCK
10/fMCK
ns
ns
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V
tKCY2/2
− 12
tKCY2/2
− 50
tKCY2/2
− 50
ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V
tKCY2/2
− 18
tKCY2/2
− 50
tKCY2/2
− 50
ns
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
tKCY2/2
− 50
tKCY2/2
− 50
tKCY2/2
− 50
ns
tKCY2/2
− 50
tKCY2/2
− 50
ns
4.0 V ≤ EVDD < 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V
1/fMCK +
20
1/fMCK +
30
1/fMCK +
30
ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V
1/fMCK +
20
1/fMCK +
30
1/fMCK +
30
ns
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
1/fMCK +
30
1/fMCK +
30
1/fMCK +
30
ns
1/fMCK +
30
1/fMCK +
30
ns
1.8 V ≤ EVDD < 3.3 V,
Note 2
1.6 V ≤ Vb ≤ 2.0 V
SIp hold time
Note 4
(from SCKp↑)
mode
20 MHz < fMCK ≤ 24 MHz
1.8 V ≤ EVDD < 3.3 V,
Note 2
1.6 V ≤ Vb ≤ 2.0 V
SIp setup time
Note 3
(to SCKp↑)
MAX.
Unit
4.0 V ≤ EVDD < 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V
1/fMCK +
31
1/fMCK +
31
1/fMCK +
31
ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V
1/fMCK +
31
1/fMCK +
31
1/fMCK +
31
ns
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
1/fMCK +
31
1/fMCK +
31
1/fMCK +
31
ns
1/fMCK +
31
1/fMCK +
31
ns
1.8 V ≤ EVDD < 3.3 V,
Note 2
1.6 V ≤ Vb ≤ 2.0 V
(Notes, Caution and Remarks are listed on the next page.)
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 56 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
(2/2)
HS (high-
LS (low-speed
LV (low-
speed main)
main) mode
voltage main)
mode
MIN.
Delay time from SCKp↓
Note 5
to SOp output
tKSO2
MAX.
Unit
mode
MIN.
MAX.
MIN.
MAX.
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2/fMCK
+ 120
2/fMCK
+ 573
2/fMCK
+ 573
ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2/fMCK
+ 214
2/fMCK
+ 573
2/fMCK
+ 573
ns
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
2/fMCK
+ 573
2/fMCK
+ 573
2/fMCK
+ 573
ns
2/fMCK
+ 573
2/fMCK
+ 573
ns
1.8 V ≤ EVDD < 3.3 V,
Note 2
,
1.6 V ≤ Vb ≤ 2.0 V
Cb = 30 pF, Rb = 5.5 kΩ
Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
2. Use it with EVDD ≥ Vb.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance
(32-pin to 52-pin products)/EVDD tolerance (64-pin products)) mode for the SOp pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
For VIH and VIL, see the DC
characteristics with TTL input buffer selected.
CSI mode connection diagram (during communication at different potential)
Vb
Rb
SCKp
RL78
microcontroller
SCK
SIp
SO
SOp
SI
User's device
Remarks 1. Rb[Ω]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance,
Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM number (g = 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01))
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 57 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
t KCY2
t KL 2
t KH 2
SCKp
t SIK2
SIp
t KSI2
Input data
t KSO 2
Output data
SOp
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
t KCY2
t KL 2
t KH 2
SCKp
t SI K2
SIp
t KSI 2
Input data
t KSO 2
SOp
Remark
Output data
p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM number (g = 1)
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 58 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
2.5.2 Serial interface IICA
2
(1) I C standard mode
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
HS (high-
LS (low-speed
LV (low-
speed main)
main) Mode
voltage main)
Mode
SCLA0 clock frequency
fSCL
Standard
mode:
fCLK ≥ 1 MHz
Mode
MIN.
MAX.
MIN.
MIN.
MAX.
MIN.
2.7 V ≤ EVDD ≤ 5.5 V
0
100
0
100
0
100
2.4 V ≤ EVDD ≤ 5.5 V
0
100
0
100
0
100
0
100
0
100
0
100
1.8 V ≤ EVDD ≤ 5.5 V
1.6 V ≤ EVDD ≤ 5.5 V
Setup time of restart condition
tSU:STA
2.7 V ≤ EVDD ≤ 5.5 V
4.7
4.7
4.7
2.4 V ≤ EVDD ≤ 5.5 V
4.7
4.7
4.7
4.7
4.7
1.8 V ≤ EVDD ≤ 5.5 V
1.6 V ≤ EVDD ≤ 5.5 V
Hold time
Note 1
tHD:STA
2.7 V ≤ EVDD ≤ 5.5 V
4.0
4.0
4.0
2.4 V ≤ EVDD ≤ 5.5 V
4.0
4.0
4.0
4.0
4.0
1.6 V ≤ EVDD ≤ 5.5 V
tLOW
2.7 V ≤ EVDD ≤ 5.5 V
4.7
4.7
4.7
2.4 V ≤ EVDD ≤ 5.5 V
4.7
4.7
4.7
4.7
4.7
1.6 V ≤ EVDD ≤ 5.5 V
tHIGH
2.7 V ≤ EVDD ≤ 5.5 V
4.0
4.0
4.0
2.4 V ≤ EVDD ≤ 5.5 V
4.0
4.0
4.0
4.0
4.0
1.6 V ≤ EVDD ≤ 5.5 V
tSU:DAT
2.7 V ≤ EVDD ≤ 5.5 V
250
250
250
2.4 V ≤ EVDD ≤ 5.5 V
250
250
250
250
250
1.6 V ≤ EVDD ≤ 5.5 V
Data hold time (transmission)
tHD:DAT
0
3.45
0
3.45
0
3.45
2.4 V ≤ EVDD ≤ 5.5 V
0
3.45
0
3.45
0
3.45
0
3.45
0
3.45
0
3.45
2.7 V ≤ EVDD ≤ 5.5 V
4.0
4.0
4.0
2.4 V ≤ EVDD ≤ 5.5 V
4.0
4.0
4.0
4.0
4.0
1.8 V ≤ EVDD ≤ 5.5 V
1.6 V ≤ EVDD ≤ 5.5 V
Bus-free time
tBUF
ns
2.7 V ≤ EVDD ≤ 5.5 V
1.6 V ≤ EVDD ≤ 5.5 V
tSU:STO
μs
250
1.8 V ≤ EVDD ≤ 5.5 V
Setup time of stop condition
μs
4.0
1.8 V ≤ EVDD ≤ 5.5 V
Note 2
μs
4.7
1.8 V ≤ EVDD ≤ 5.5 V
Data setup time (reception)
μs
4.0
1.8 V ≤ EVDD ≤ 5.5 V
Hold time when SCLA0 = “H”
4.7
4.7
4.7
2.4 V ≤ EVDD ≤ 5.5 V
4.7
4.7
4.7
4.7
4.7
1.6 V ≤ EVDD ≤ 5.5 V
μs
μs
4.0
2.7 V ≤ EVDD ≤ 5.5 V
1.8 V ≤ EVDD ≤ 5.5 V
kHz
4.7
1.8 V ≤ EVDD ≤ 5.5 V
Hold time when SCLA0 = “L”
Unit
μs
4.7
(Notes and Remark are listed on the next page.)
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 59 of 131
RL78/L12
Notes 1.
2.
Remark
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 kΩ
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 60 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
2
(2) I C fast mode
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
HS (high-
LS (low-speed
LV (low-
speed main)
main) Mode
voltage main)
Mode
SCLA0 clock frequency
fSCL
Fast mode:
fCLK ≥ 3.5
MHz
Setup time of restart condition
tSU:STA
MAX.
MIN.
MIN.
MAX.
MIN.
2.7 V ≤ EVDD ≤ 5.5 V
0
400
0
400
0
400
2.4 V ≤ EVDD ≤ 5.5 V
0
400
0
400
0
400
0
400
0
400
2.7 V ≤ EVDD ≤ 5.5 V
0.6
2.4 V ≤ EVDD ≤ 5.5 V
0.6
0.6
1.8 V ≤ EVDD ≤ 5.5 V
Hold time
Note 1
tHD:STA
tLOW
tHIGH
0.6
0.6
2.4 V ≤ EVDD ≤ 5.5 V
0.6
0.6
0.6
0.6
0.6
2.7 V ≤ EVDD ≤ 5.5 V
1.3
1.3
1.3
2.4 V ≤ EVDD ≤ 5.5 V
1.3
1.3
1.3
1.3
1.3
2.7 V ≤ EVDD ≤ 5.5 V
0.6
0.6
0.6
2.4 V ≤ EVDD ≤ 5.5 V
0.6
0.6
0.6
0.6
0.6
1.8 V ≤ EVDD ≤ 5.5 V
Data setup time (reception)
tSU:DAT
2.7 V ≤ EVDD ≤ 5.5 V
100
100
100
2.4 V ≤ EVDD ≤ 5.5 V
100
100
100
100
100
1.8 V ≤ EVDD ≤ 5.5 V
Data hold time (transmission)
Note 2
tHD:DAT
tSU:STO
tBUF
2.
μs
ns
0.9
0
0.9
0
0.9
2.4 V ≤ EVDD ≤ 5.5 V
0
0.9
0
0.9
0
0.9
0
0.9
0
0.9
2.7 V ≤ EVDD ≤ 5.5 V
0.6
0.6
0.6
2.4 V ≤ EVDD ≤ 5.5 V
0.6
0.6
0.6
0.6
0.6
2.7 V ≤ EVDD ≤ 5.5 V
1.3
1.3
1.3
2.4 V ≤ EVDD ≤ 5.5 V
1.3
1.3
1.3
1.3
1.3
1.8 V ≤ EVDD ≤ 5.5 V
Notes 1.
μs
0
1.8 V ≤ EVDD ≤ 5.5 V
Bus-free time
μs
2.7 V ≤ EVDD ≤ 5.5 V
1.8 V ≤ EVDD ≤ 5.5 V
Setup time of stop condition
0.6
0.6
0.6
1.8 V ≤ EVDD ≤ 5.5 V
Hold time when SCLA0 = “H”
0.6
0.6
kHz
μs
0.6
2.7 V ≤ EVDD ≤ 5.5 V
1.8 V ≤ EVDD ≤ 5.5 V
Hold time when SCLA0 = “L”
Mode
MIN.
1.8 V ≤ EVDD ≤ 5.5 V
Unit
μs
μs
μs
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Fast mode:
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Cb = 320 pF, Rb = 1.1 kΩ
Page 61 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
2
(3) I C fast mode plus
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
Fast mode plus: 2.7 V ≤ EVDD ≤ 5.5 V
fCLK ≥ 10 MHz
SCLA0 clock frequency
fSCL
Setup time of restart
tSU:STA
2.7 V ≤ EVDD ≤ 5.5 V
HS (high-speed
LS (low-speed
LV (low-voltage
main) Mode
main) Mode
main) Mode
MIN.
MAX.
0
1000
MIN.
MAX.
MIN.
Unit
MAX.
⎯
⎯
kHz
0.26
⎯
⎯
μs
condition
Hold time
Note 1
Hold time when SCLA0 =
tHD:STA
2.7 V ≤ EVDD ≤ 5.5 V
0.26
⎯
⎯
μs
tLOW
2.7 V ≤ EVDD ≤ 5.5 V
0.5
⎯
⎯
μs
tHIGH
2.7 V ≤ EVDD ≤ 5.5 V
0.26
⎯
⎯
μs
tSU:DAT
2.7 V ≤ EVDD ≤ 5.5 V
50
⎯
⎯
μs
tHD:DAT
2.7 V ≤ EVDD ≤ 5.5 V
0
⎯
⎯
μs
tSU:STO
2.7 V ≤ EVDD ≤ 5.5 V
0.26
⎯
⎯
μs
tBUF
2.7 V ≤ EVDD ≤ 5.5 V
0.5
⎯
⎯
μs
“L”
Hold time when SCLA0 =
“H”
Data setup time
(reception)
Data hold time
0.45
Note 2
(transmission)
Setup time of stop
condition
Bus-free time
Notes 1.
2.
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection
register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in
the redirect destination.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Fast mode plus: Cb = 120 pF, Rb = 1.1 kΩ
IICA serial transfer timing
tLOW
SCLA0
tHD:DAT
tHD:STA
tHIGH
tSU:STA
tHD:STA
tSU:STO
tSU:DAT
SDAA0
tLOW
Stop
condition
Start
condition
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Restart
condition
Stop
condition
Page 62 of 131
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
2.6 Analog Characteristics
2.6.1 A/D converter characteristics
Classification of A/D converter characteristics
Reference Voltage
Reference voltage (+) = AVREFP
Reference voltage (+) = VDD
Reference voltage (+) = VBGR
Input channel
Reference voltage (−) = AVREFM
Reference voltage (−) = VSS
Reference voltage (−) = AVREFM
ANI0, ANI1
−
Refer to 2.6.1 (3).
Refer to 2.6.1 (4).
ANI16 to ANI23
Refer to 2.6.1 (2).
Internal reference voltage
Refer to 2.6.1 (1).
−
Temperature sensor output voltage
(1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1
(ADREFM = 1), target pin : internal reference voltage, and temperature sensor output voltage
(TA = −40 to +85°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, 1.6 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) =
AVREFP, Reference voltage (−) = AVREFM = 0 V)
Parameter
Resolution
Symbol
Conditions
MIN.
RES
Note 1
Overall error
AINL
tCONV
MAX.
Unit
10
bit
1.2
±3.5
LSB
1.2
8
10-bit resolution
AVREFP = VDD
Conversion time
TYP.
Note 3
1.8 V ≤ VDD ≤ 5.5 V
±7.0
LSB
10-bit resolution
3.6 V ≤ VDD ≤ 5.5 V
2.375
39
μs
Target pin: Internal reference
2.7 V ≤ VDD ≤ 5.5 V
3.5625
39
μs
2.4 V ≤ VDD ≤ 5.5 V
17
39
μs
±0.25
%FSR
±0.50
%FSR
±0.25
%FSR
±0.50
%FSR
voltage, and temperature
sensor output voltage (HS
1.6 V ≤ VDD ≤ 5.5 V
Note 4
(high-speed main) mode)
Notes 1, 2
Zero-scale error
Notes 1, 2
Full-scale error
Integral linearity
error
EFS
ILE
Note 1
10-bit resolution
Note 3
AVREFP = VDD
10-bit resolution
Note 3
AVREFP = VDD
10-bit resolution
AVREFP = VDD
Differential linearity
error
EZS
DLE
Note 1
10-bit resolution
AVREFP = VDD
Analog input voltage
VAIN
Note 3
Note 3
1.8 V ≤ AVREFP ≤ 5.5 V
1.6 V ≤ AVREFP ≤ 5.5 V
Note 4
1.8 V ≤ AVREFP ≤ 5.5 V
1.6 V ≤ AVREFP ≤ 5.5 V
Note 4
1.8 V ≤ VDD ≤ 5.5 V
1.6 V ≤ VDD ≤ 5.5 V
±2.5
LSB
Note 4
±5.0
LSB
±1.5
LSB
Note 4
±2.0
LSB
1.8 V ≤ VDD ≤ 5.5 V
1.6 V ≤ VDD ≤ 5.5 V
Internal reference voltage
VBGR
Note 5
V
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode)
VBGR
Temperature sensor output voltage
VTMPS25
Note 5
V
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode)
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD.
4. Values when the conversion time is set to 57 μs (min.) and 95 μs (max.).
5. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.
R01DS0157EJ0210 Rev.2.10
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Page 63 of 131
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
(2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1
(ADREFM = 1), target pin : ANI16 to ANI23
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, 1.6 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) =
AVREFP, Reference voltage (−) = AVREFM = 0 V)
Parameter
Symbol
Resolution
Conditions
RES
Note 1
Overall error
AINL
Conversion time
tCONV
Zero-scale error
EZS
TYP.
8
MAX.
Unit
10
bit
10-bit resolution
1.8 V ≤ AVREFP ≤ 5.5 V
1.2
±5.0
LSB
AVREFP = EVDD = VDD
1.6 V ≤ AVREFP ≤ 5.5 V
1.2
±8.5
LSB
Note 3
Note 4
10-bit resolution
3.6 V ≤ VDD ≤ 5.5 V
2.125
39
μs
AVREFP = EVDD = VDD
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
μs
1.8 V ≤ VDD ≤ 5.5 V
17
39
μs
1.6 V ≤ VDD ≤ 5.5 V
57
95
μs
±0.35
%FSR
±0.60
%FSR
±0.35
%FSR
±0.60
%FSR
1.8 V ≤ AVREFP ≤ 5.5 V
±3.5
LSB
1.6 V ≤ AVREFP ≤ 5.5 V
±6.0
LSB
Note 3
Notes 1, 2
MIN.
10-bit resolution
1.8 V ≤ AVREFP ≤ 5.5 V
Note
AVREFP = EVDD = VDD
1.6 V ≤ AVREFP ≤ 5.5 V
3
Note 4
Notes 1, 2
Full-scale error
EFS
10-bit resolution
1.8 V ≤ AVREFP ≤ 5.5 V
Note
AVREFP = EVDD = VDD
1.6 V ≤ AVREFP ≤ 5.5 V
3
Note 4
Integral linearity error
Note 1
ILE
10-bit resolution
AVREFP = EVDD = VDD
Differential linearity error
DLE
Note 3
Note 4
10-bit resolution
1.8 V ≤ AVREFP ≤ 5.5 V
±2.0
LSB
1.6 V ≤ AVREFP ≤ 5.5 V
±2.5
LSB
AVREFP
V
AVREFP = EVDD = VDD
Note 1
Note 3
Analog input voltage
Note 4
VAIN
0
and
EVDD
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < EVDD = VDD, the MAX. values are as follows.
Overall error: Add ±4.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.20%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/Differential linearity error: Add ±2.0 LSB to the MAX. value when AVREFP = VDD.
4. When the conversion time is set to 57 μs (min.) and 95 μs (max.).
R01DS0157EJ0210 Rev.2.10
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Page 64 of 131
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
(3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (−) = VSS (ADREFM = 0),
target pin : ANI0, ANI1, ANI16 to ANI23, internal reference voltage, and temperature sensor output voltage
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = VDD, Reference voltage (−)
= VSS)
Parameter
Symbol
Resolution
Conditions
RES
Note 1
Overall error
AINL
MIN.
TYP.
8
10-bit resolution
MAX.
Unit
10
bit
1.8 V ≤ VDD ≤ 5.5 V
1.2
±7.0
LSB
1.6 V ≤ VDD ≤ 5.5 V
1.2
±10.5
LSB
Note 3
Conversion time
tCONV
3.6 V ≤ VDD ≤ 5.5 V
2.125
39
μs
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
μs
1.8 V ≤ VDD ≤ 5.5 V
17
39
μs
1.6 V ≤ VDD ≤ 5.5 V
57
95
μs
10-bit resolution
3.6 V ≤ VDD ≤ 5.5 V
2.375
39
μs
Target pin: Internal
2.7 V ≤ VDD ≤ 5.5 V
3.5625
39
μs
2.4 V ≤ VDD ≤ 5.5 V
17
39
μs
10-bit resolution
reference voltage, and
temperature sensor output
voltage (HS (high-speed
main) mode)
Notes 1, 2
Zero-scale error
EZS
10-bit resolution
1.8 V ≤ VDD ≤ 5.5 V
±0.60 %FSR
1.6 V ≤ VDD ≤ 5.5 V
±0.85 %FSR
Note 3
Notes 1, 2
Full-scale error
EFS
10-bit resolution
1.8 V ≤ VDD ≤ 5.5 V
±0.60 %FSR
1.6 V ≤ VDD ≤ 5.5 V
±0.85 %FSR
Note 3
Integral linearity error
Note 1
ILE
10-bit resolution
1.8 V ≤ VDD ≤ 5.5 V
±4.0
LSB
1.6 V ≤ VDD ≤ 5.5 V
±6.5
LSB
1.8 V ≤ VDD ≤ 5.5 V
±2.0
LSB
1.6 V ≤ VDD ≤ 5.5 V
±2.5
LSB
VDD
V
EVDD
V
Note 3
Differential linearity error
Note 1
DLE
10-bit resolution
Note 3
Analog input voltage
VAIN
ANI0, ANI1
0
ANI16 to ANI23
0
Internal reference voltage
VBGR
Note 4
V
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode)
Temperature sensor output voltage
VTMPS25
Note 4
V
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode)
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When the conversion time is set to 57 μs (min.) and 95 μs (max.).
4. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 65 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
(4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (−) =
AVREFM/ANI1 (ADREFM = 1), target pin : ANI0, ANI16 to ANI23
(TA = −40 to +85°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = VBGR Note 3, Reference
voltage (−) = AVREFM Note 4 = 0 V, HS (high-speed main) mode)
Parameter
Symbol
Resolution
Conditions
MIN.
TYP.
RES
Conversion time
Notes 1, 2
Zero-scale error
Integral linearity error
Note 1
Differential linearity error
Note 1
Analog input voltage
MAX.
Unit
8
bit
tCONV
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
39
μs
EZS
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
ILE
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±2.0
LSB
DLE
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±1.0
LSB
17
VAIN
0
VBGR
Note 3
V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.
4. When reference voltage (−) = VSS, the MAX. values are as follows.
Zero-scale error: Add ±0.35%FSR to the MAX. value when reference voltage (−) = AVREFM.
Integral linearity error: Add ±0.5 LSB to the MAX. value when reference voltage (−) = AVREFM.
Differential linearity error: Add ±0.2 LSB to the MAX. value when reference voltage (−) = AVREFM.
2.6.2 Temperature sensor/internal reference voltage characteristics
(TA = −40 to +85°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) (HS (high-speed main) mode)
Parameter
Symbol
Conditions
Temperature sensor output voltage VTMPS25
Setting ADS register = 80H, TA = +25°C
Internal reference voltage
VBGR
Setting ADS register = 81H
Temperature coefficient
FVTMPS
Temperature sensor that depends on the
MIN.
TYP.
MAX.
1.05
1.38
1.45
−3.6
Unit
V
1.5
V
mV/°C
temperature
Operation stabilization wait time
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
tAMP
5
μs
Page 66 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
2.6.3 POR circuit characteristics
(TA = −40 to +85°C, VSS = 0 V)
Parameter
Symbol
Detection voltage
Minimum pulse width
Note
Conditions
MIN.
TYP.
MAX.
Unit
VPOR
Power supply rise time
1.47
1.51
1.55
V
VPDR
Power supply fall time
1.46
1.50
1.54
V
TPW
μs
300
Note Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a
POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main
system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control
register (CSC).
TPW
Supply voltage (VDD)
VPOR
VPDR or 0.7 V
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 67 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
2.6.4 LVD circuit characteristics
(TA = −40 to +85°C, VPDR ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Detection
Supply voltage level
Symbol
VLVD0
voltage
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VLVD8
VLVD9
VLVD10
VLVD11
VLVD12
VLVD13
Minimum pulse width
tLW
Detection delay time
tLD
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Conditions
MIN.
TYP.
MAX.
Unit
Power supply rise time
3.98
4.06
4.14
V
Power supply fall time
3.90
3.98
4.06
V
Power supply rise time
3.68
3.75
3.82
V
Power supply fall time
3.60
3.67
3.74
V
Power supply rise time
3.07
3.13
3.19
V
Power supply fall time
3.00
3.06
3.12
V
Power supply rise time
2.96
3.02
3.08
V
Power supply fall time
2.90
2.96
3.02
V
Power supply rise time
2.86
2.92
2.97
V
Power supply fall time
2.80
2.86
2.91
V
Power supply rise time
2.76
2.81
2.87
V
Power supply fall time
2.70
2.75
2.81
V
Power supply rise time
2.66
2.71
2.76
V
Power supply fall time
2.60
2.65
2.70
V
Power supply rise time
2.56
2.61
2.66
V
Power supply fall time
2.50
2.55
2.60
V
Power supply rise time
2.45
2.50
2.55
V
Power supply fall time
2.40
2.45
2.50
V
Power supply rise time
2.05
2.09
2.13
V
Power supply fall time
2.00
2.04
2.08
V
Power supply rise time
1.94
1.98
2.02
V
Power supply fall time
1.90
1.94
1.98
V
Power supply rise time
1.84
1.88
1.91
V
Power supply fall time
1.80
1.84
1.87
V
Power supply rise time
1.74
1.77
1.81
V
Power supply fall time
1.70
1.73
1.77
V
Power supply rise time
1.64
1.67
1.70
V
Power supply fall time
1.60
1.63
1.66
V
μs
300
300
μs
Page 68 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
LVD Detection Voltage of Interrupt & Reset Mode
(TA = −40 to +85°C, VPDR ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Interrupt and reset VLVDA0
mode
VLVDA1
Conditions
VPOC2, VPOC1, VPOC0 = 0, 0, 0, falling reset voltage
LVIS1, LVIS0 = 1, 0 Rising release reset voltage
Falling interrupt voltage
VLVDA2
LVIS1, LVIS0 = 0, 1 Rising release reset voltage
Falling interrupt voltage
VLVDA3
LVIS1, LVIS0 = 0, 0 Rising release reset voltage
Falling interrupt voltage
VLVDB1
VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage
VLVDB2
LVIS1, LVIS0 = 1, 0 Rising release reset voltage
Falling interrupt voltage
VLVDB3
LVIS1, LVIS0 = 0, 1 Rising release reset voltage
Falling interrupt voltage
VLVDB4
LVIS1, LVIS0 = 0, 0 Rising release reset voltage
Falling interrupt voltage
VLVDC0
VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage
VLVDC1
LVIS1, LVIS0 = 1, 0 Rising release reset voltage
Falling interrupt voltage
VLVDC2
LVIS1, LVIS0 = 0, 1 Rising release reset voltage
Falling interrupt voltage
VLVDC3
LVIS1, LVIS0 = 0, 0 Rising release reset voltage
Falling interrupt voltage
VLVDD0
VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage
VLVDD1
LVIS1, LVIS0 = 1, 0 Rising release reset voltage
Falling interrupt voltage
VLVDD2
LVIS1, LVIS0 = 0, 1 Rising release reset voltage
Falling interrupt voltage
VLVDD3
LVIS1, LVIS0 = 0, 0 Rising release reset voltage
Falling interrupt voltage
MIN.
TYP.
MAX.
Unit
1.60
1.63
1.66
V
1.74
1.77
1.81
V
1.70
1.73
1.77
V
1.84
1.88
1.91
V
1.80
1.84
1.87
V
2.86
2.92
2.97
V
2.80
2.86
2.91
V
1.80
1.84
1.87
V
1.94
1.98
2.02
V
1.90
1.94
1.98
V
2.05
2.09
2.13
V
2.00
2.04
2.08
V
3.07
3.13
3.19
V
3.00
3.06
3.12
V
2.40
2.45
2.50
V
2.56
2.61
2.66
V
2.50
2.55
2.60
V
2.66
2.71
2.76
V
2.60
2.65
2.70
V
3.68
3.75
3.82
V
3.60
3.67
3.74
V
2.70
2.75
2.81
V
2.86
2.92
2.97
V
2.80
2.86
2.91
V
2.96
3.02
3.08
V
2.90
2.96
3.02
V
3.98
4.06
4.14
V
3.90
3.98
4.06
V
MIN.
TYP.
MAX.
Unit
54
V/ms
2.6.5 Supply voltage rise time
(TA = −40 to +85°C, VSS = 0 V)
Parameter
Power supply voltage rising slope
Caution
Symbol
Conditions
SVDD
Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the
operating voltage range shown in 30.4 AC Characteristics.
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 69 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
2.7 LCD Characteristics
2.7.1 Resistance division method
(1) Static display mode
(TA = −40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
LCD drive voltage
Symbol
Conditions
VL4
MIN.
TYP.
2.0
MAX.
Unit
VDD
V
MAX.
Unit
VDD
V
MAX.
Unit
VDD
V
(2) 1/2 bias method, 1/4 bias method
(TA = −40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
LCD drive voltage
Symbol
Conditions
VL4
MIN.
TYP.
2.7
(3) 1/3 bias method
(TA = −40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
LCD drive voltage
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Symbol
VL4
Conditions
MIN.
2.5
TYP.
Page 70 of 131
RL78/L12
2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
2.7.2 Internal voltage boosting method
(1) 1/3 bias method
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
LCD output voltage variation range
VL1
Conditions
Note 1
C1 to C4
= 0.47 μF
MIN.
TYP.
MAX.
Unit
VLCD = 04H
0.90
1.00
1.08
V
VLCD = 05H
0.95
1.05
1.13
V
VLCD = 06H
1.00
1.10
1.18
V
VLCD = 07H
1.05
1.15
1.23
V
VLCD = 08H
1.10
1.20
1.28
V
VLCD = 09H
1.15
1.25
1.33
V
VLCD = 0AH
1.20
1.30
1.38
V
VLCD = 0BH
1.25
1.35
1.43
V
VLCD = 0CH
1.30
1.40
1.48
V
VLCD = 0DH
1.35
1.45
1.53
V
VLCD = 0EH
1.40
1.50
1.58
V
VLCD = 0FH
1.45
1.55
1.63
V
VLCD = 10H
1.50
1.60
1.68
V
VLCD = 11H
1.55
1.65
1.73
V
VLCD = 12H
1.60
1.70
1.78
V
1.65
1.75
1.83
V
Note 1
= 0.47 μF
VLCD = 13H
2 VL1
− 0.1
2 VL1
2 VL1
V
Note 1
= 0.47 μF
3 VL1
− 0.15
3 VL1
3 VL1
V
5
ms
Note 1
= 0.47 μF
500
ms
Doubler output voltage
VL2
C1 to C4
Tripler output voltage
VL4
C1 to C4
Reference voltage setup time
Voltage boost wait time
Note 2
Note 3
tVWAIT1
tVWAIT2
C1 to C4
Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = 0.47 μF±30%
2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or
when the internal voltage boosting method is selected [by setting the MDSET1 and MDSET0 bits of the
LCDM0 register to 01B] if the default value reference voltage is used) until voltage boosting starts (VLCON = 1).
3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
(2) 1/4 bias method
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
LCD output voltage variation range
VL1
Note 4
Conditions
Note 1
C1 to C5
= 0.47 μF
MIN.
TYP.
MAX.
Unit
VLCD = 04H
0.90
1.00
1.08
V
VLCD = 05H
0.95
1.05
1.13
V
VLCD = 06H
1.00
1.10
1.18
V
VLCD = 07H
1.05
1.15
1.23
V
VLCD = 08H
1.10
1.20
1.28
V
VLCD = 09H
1.15
1.25
1.33
V
VLCD = 0AH
1.20
1.30
1.38
V
VLCD = 0BH
1.25
1.35
1.43
V
VLCD = 0CH
1.30
1.40
1.48
V
VLCD = 0DH
1.35
1.45
1.53
V
VLCD = 0EH
1.40
1.50
1.58
V
VLCD = 0FH
1.45
1.55
1.63
V
VLCD = 10H
1.50
1.60
1.68
V
VLCD = 11H
1.55
1.65
1.73
V
VLCD = 12H
1.60
1.70
1.78
V
VLCD = 13H
Doubler output voltage
VL2
Tripler output voltage
VL3
Quadruply output voltage
Reference voltage setup time
Voltage boost wait time
Notes 1.
2.
3.
4.
VL4
Note 2
Note 3
1.65
1.75
1.83
V
Note 1
= 0.47 μF
2 VL1 − 0.08
2 VL1
2 VL1
V
Note 1
= 0.47 μF
3 VL1 − 0.12
3 VL1
3 VL1
V
Note 1
= 0.47 μF
4 VL1 − 0.16
4 VL1
4 VL1
C1 to C5
C1 to C5
Note 4
C1 to C5
tVWAIT1
tVWAIT2
Note 1
C1 to C5
= 0.47 μF
V
5
ms
500
ms
This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL3 and GND
C5: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = C5 = 0.47 μF±30%
This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when
the internal voltage boosting method is selected [by setting the MDSET1 and MDSET0 bits of the LCDM0
register to 01B] if the default value reference voltage is used) until voltage boosting starts (VLCON = 1).
This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).
VL4 must be 5.5 V or lower.
2.7.3 Capacitor split method
1/3 bias method
(TA = −40 to +85°C, 2.2 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
VL4 voltage
VL4
Conditions
C1 to C4 = 0.47 μ F
V
2/3 VL4
+ 0.1
V
Note 2
1/3 VL4
− 0.1
1/3 VL4
1/3 VL4
+ 0.1
V
VL1 voltage
VL1
C1 to C4 = 0.47 μ F
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
VDD
Unit
2/3 VL4
C1 to C4 = 0.47 μ F
tVWAIT
MAX.
2/3 VL4
− 0.1
VL2
Note 1
TYP.
Note 2
VL2 voltage
Capacitor split wait time
MIN.
Note 2
100
ms
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
Notes 1. This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1).
2. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = 0.47 μF±30%
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
2.8 RAM Data Retention Characteristics
(TA = −40 to +85°C, VSS = 0 V)
Parameter
Data retention supply voltage
Symbol
Conditions
VDDDR
MIN.
1.46
TYP.
Note
MAX.
Unit
5.5
V
Note This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage
reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated.
Operation mode
STOP mode
RAM Data retention mode
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
2.9 Flash Memory Programming Characteristics
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
System clock frequency
fCLK
1.8 V ≤ VDD ≤ 5.5 V
Number of code flash rewrites
Cerwr
Retained for 20 years
Note 1, 2, 3
MIN.
TYP.
1
1,000
MAX.
Unit
24
MHz
Times
TA = 85°C
Number of data flash rewrites
Note 1, 2, 3
Retained for 1 year
1,000,000
TA = 25°C
Retained for 5 years
100,000
TA = 85°C
Retained for 20 years
10,000
TA = 85°C
Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite.
The retaining years are until next rewrite after the rewrite.
2. When using flash memory programmer and Renesas Electronics self programming library
3. This characteristic indicates the flash memory characteristic and based on Renesas Electronics reliability test.
Remark
When updating data multiple times, use the flash memory as one for updating data.
2.10 Dedicated Flash Memory Programmer Communication (UART)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Transfer rate
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Symbol
Conditions
During flash memory programming
MIN.
115,200
TYP.
MAX.
Unit
1,000,000
bps
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2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85°C)
2.11 Timing Specifications for Switching Flash Memory Programming Modes
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Time to complete the
tSUINIT
Conditions
MIN.
TYP.
POR and LVD reset must be released before
MAX.
Unit
100
ms
the external reset is released.
communication for the initial setting
after the external reset is released
Time to release the external reset
tSU
POR and LVD reset must be released before
10
μs
1
ms
the external reset is released.
after the TOOL0 pin is set to the
low level
Time to hold the TOOL0 pin at the
tHD
POR and LVD reset must be released before
the external reset is released.
low level after the external reset is
released
(excluding the processing time of
the firmware to control the flash
memory)
RESET
tH D +
soft processing
time
1-byte data for mode setting
TOOL0
t SU
t SUINIT
The low level is input to the TOOL0 pin.
The external reset is released (POR and LVD reset must be released before the external
reset is released.).
The TOOL0 pin is set to the high level.
Setting of the flash memory programming mode by UART reception and complete the baud
rate setting.
Remark tSUINIT: Communication for the initial setting must be completed within 100 ms after a reset is released during this
period.
tSU:
Time to release the external reset after the TOOL0 pin is set to the low level
tHD:
Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing
time of the firmware to control the flash memory)
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
This chapter describes the electrical specifications for the products "G: Industrial applications (TA = -40 to
+105°C)".
Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development
and evaluation.
Do not use the on-chip debug function in products designated for mass
production, because the guaranteed number of rewritable times of the flash memory may be
exceeded when this function is used, and product reliability therefore cannot be guaranteed.
Renesas Electronics is not liable for problems occurring when the on-chip debug function is
used.
2. With products not provided with an EVDD or EVSS pin, replace EVDD with VDD, or replace EVSS with
VSS.
3. For derating with TA = +85 to +105°C, contact our Sales Division or the vender's sales division.
Derating means the specified reduction in an operating parameter to improve reliability.
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
There are following differences between the products "G: Industrial applications (TA = -40 to +105°C)" and the products “A:
Consumer applications, and G: Industrial applications (TA = -40 to +85°C)”.
Parameter
Application
A: Consumer applications,
G: Industrial applications
G: Industrial applications
(with TA = -40 to +85°C)
Operating ambient temperature
TA = -40 to +85°C
TA = -40 to +105°C
Operating mode
HS (high-speed main) mode:
HS (high-speed main) mode only:
Operating voltage range
2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz
2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
LS (low-speed main) mode:
1.8 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz
LV (low-voltage main) mode:
1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz
High-speed on-chip oscillator clock
accuracy
1.8 V ≤ VDD ≤ 5.5 V:
2.4 V ≤ VDD ≤ 5.5 V:
±1.0%@ TA = -20 to +85°C
±2.0%@ TA = +85 to +105°C
±1.5%@ TA = -40 to -20°C
±1.0%@ TA = -20 to +85°C
1.6 V ≤ VDD < 1.8 V:
±1.5%@ TA = -40 to -20°C
±5.0%@ TA = -20 to +85°C
±5.5%@ TA = -40 to -20°C
Serial array unit
UART
UART
CSI00: fCLK/2 (supporting 16 Mbps), fCLK/4
CSI00: fCLK/4
CSI01
CSI01
2
IICA
2
Simplified I C communication
Simplified I C communication
Normal mode
Normal mode
Fast mode
Fast mode
Fast mode plus
Voltage detector
Rise detection voltage: 1.67 V to 4.06 V
Rise detection voltage: 2.61 V to 4.06 V
(14 levels)
(8 levels)
Fall detection voltage: 1.63 V to 3.98 V
Fall detection voltage: 2.55 V to 3.98 V
(14 levels)
(8 levels)
Remark The electrical characteristics of the products G: Industrial applications (TA = -40 to +105°C) are different from
those of the products “A: Consumer applications, and G: Industrial applications (only with TA = -40 to +85°C)”.
For details, refer to 3.1 to 3.10.
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
3.1 Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbols
(1/3)
Conditions
VDD
VDD = EVDD
EVDD
VDD = EVDD
EVSS
REGC pin input voltage
VIREGC
Ratings
Unit
−0.5 to +6.5
V
−0.5 to +6.5
V
−0.5 to +0.3
V
−0.3 to +2.8
REGC
V
Note 1
and −0.3 to VDD + 0.3
Input voltage
VI1
−0.3 to EVDD + 0.3
P10 to P17, P30 to P32, P40 to P43,
P50 to P54, P70 to P74, P120, P125 to P127, P140
and −0.3 to VDD + 0.3
to P147
VI2
V
Note 2
−0.3 to EVDD + 0.3
P60, P61 (N-ch open-drain)
V
Note 2
and −0.3 to VDD + 0.3
VI3
−0.3 to VDD + 0.3
P20, P21, P121 to P124, P137, EXCLK, EXCLKS,
Note 2
V
RESET
Output voltage
VO1
−0.3 to EVDD + 0.3
P10 to P17, P30 to P32, P40 to P43, P50 to P54,
P60, P61, P70 to P74, P120, P125 to P127, P130,
and −0.3 to VDD + 0.3
P140 to P147
Analog input voltage
VO2
P20, P21
VAI1
ANI16 to ANI23
−0.3 to VDD + 0.3
V
Note 2
Note 2
−0.3 to EVDD + 0.3
V
V
Notes 2, 3
and −0.3 to AVREF(+) + 0.3
VAI2
−0.3 to VDD + 0.3
ANI0, ANI1
V
Notes 2, 3
and −0.3 to AVREF(+) + 0.3
Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μ F).
This value regulates the absolute
maximum rating of the REGC pin. Do not use this pin with voltage applied to it.
2.
Must be 6.5 V or lower.
3.
Do not exceed AV REF (+) + 0.3 V in case of A/D conversion target pin.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure that
the absolute maximum ratings are not exceeded.
Remarks 1.
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
2.
AVREF (+) : + side reference voltage of the A/D converter.
3.
VSS : Reference voltage
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Absolute Maximum Ratings (TA = 25°C)
Parameter
LCD voltage
(2/3)
Symbols
VL1
Conditions
VL1 voltage
Note 1
Ratings
Unit
−0.3 to +2.8
V
and −0.3 to VL4 + 0.3
VL2
VL3
VL4
VLCAP
VLOUT
VL2 voltage
Note 1
−0.3 to VL4 + 0.3
Note 2
V
VL3 voltage
Note 1
−0.3 to VL4 + 0.3
Note 2
V
VL4 voltage
Note 1
CAPL, CAPH voltage
COM0 to COM7, External resistance division
V
−0.3 to VL4 + 0.3
Note 2
V
−0.3 to VDD + 0.3
Note 2
V
SEG0 to
method
SEG38,
Capacitor split method
−0.3 to VDD + 0.3
Note 2
Internal voltage boosting method
−0.3 to VL4 + 0.3
Note 2
output voltage
Notes 1.
−0.3 to +6.5
Note 1
This value only indicates the absolute maximum ratings when applying voltage to the V L1 , VL2 , V L3 ,
and V L4 pins; it does not mean that applying voltage to these pins is recommended. When using
the internal voltage boosting method or capacitance split method, connect these pins to V SS via a
capacitor (0.47 μ F ± 30%) and connect a capacitor (0.47 μ F ± 30%) between the CAPL and CAPH
pins.
2.
Must be 6.5 V or lower.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure that
the absolute maximum ratings are not exceeded.
Remark VSS : Reference voltage
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Absolute Maximum Ratings (TA = 25°C)
Parameter
Output current, high
Symbols
IOH1
(3/3)
Conditions
Per pin
P10 to P17, P30 to P32, P40 to P43,
Ratings
Unit
−40
mA
−70
mA
−100
mA
−0.5
mA
−1
mA
40
mA
70
mA
100
mA
1
mA
P50 to P54, P70 to P74, P120,
P125 to P127, P130, P140 to P147
Total of all pins
P10 to P14, P40 to P43, P120,
−170 mA
P130, P140 to P147
P15 to P17, P30 to P32,
P50 to P54, P70 to P74,
P125 to P127
IOH2
Per pin
P20, P21
Total of all pins
Output current, low
IOL1
Per pin
P10 to P17, P30 to P32, P40 to P43,
P50 to P54, P60, P61, P70 to P74,
P120, P125 to P127, P130,
P140 to P147
Total of all pins
P10 to P14, P40 to P43, P120,
170 mA
P130, P140 to P147
P15 to P17, P30 to P32, P50 to P54,
P60, P61, P70 to P74, P125 to P127
IOL2
Per pin
P20, P21
Total of all pins
Operating ambient
TA
temperature
Storage temperature
In normal operation mode
2
mA
−40 to +105
°C
−65 to +150
°C
In flash memory programming mode
Tstg
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure that
the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
3.2 Oscillator Characteristics
3.2.1 X1, XT1 oscillator characteristics
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
X1 clock oscillation
Note
frequency (fX)
XT1 clock oscillation
Resonator
Conditions
MIN.
TYP.
MAX.
Unit
Ceramic resonator/
2.7 V ≤ VDD ≤ 5.5 V
1.0
20.0
MHz
crystal resonator
2.4 V ≤ VDD < 2.7 V
1.0
16.0
MHz
35
kHz
Crystal resonator
32
32.768
Note
frequency (fXT)
Note Indicates only permissible oscillator frequency ranges. Refer to 3.4 AC Characteristics for instruction execution
time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator
characteristics.
Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1
clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC)
by the user.
Determine the oscillation stabilization time of the OSTC register and the oscillation
stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time
with the resonator to be used.
3.2.2 On-chip oscillator characteristics
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Oscillators
High-speed on-chip oscillator
clock frequency
Parameters
Conditions
fIH
MIN.
TYP.
1
MAX.
Unit
24
MHz
Notes 1, 2
High-speed on-chip oscillator
−20 to +85°C
2.4 V ≤ VDD ≤ 5.5 V
−1
+1
%
clock frequency accuracy
−40 to −20°C
2.4 V ≤ VDD ≤ 5.5 V
−1.5
+1.5
%
+85 to +105°C
2.4 V ≤ VDD ≤ 5.5 V
−2.0
+2.0
%
Low-speed on-chip oscillator
fIL
15
kHz
clock frequency
Low-speed on-chip oscillator
−15
+15
%
clock frequency accuracy
Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H) and bits 0 to 2 of
HOCODIV register.
2. This indicates the oscillator characteristics only. Refer to 3.4 AC Characteristics for instruction execution
time.
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
3.3 DC Characteristics
3.3.1 Pin characteristics
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Symbol
IOH1
Output current,
Note 1
high
IOH2
Conditions
MIN.
Per pin for P10 to P17, P30 to P32, P40 to P43, P50 to P54,
P70 to P74, P120, P125 to P127, P130, P140 to P147
TYP.
MAX.
-3.0
Note 2
Unit
mA
Total of P10 to P14, P40 to P43, P120,
P130, P140 to P147
Note 3
(When duty = 70%
)
4.0 V ≤ EVDD ≤ 5.5 V
-30.0
mA
2.7 V ≤ EVDD < 4.0 V
−8.0
mA
2.4 V ≤ EVDD < 2.7 V
−4.0
mA
Total of P15 to P17, P30 to P32,
P50 to P54, P70 to P74, P125 to P127
Note 3
)
(When duty = 70%
4.0 V ≤ EVDD ≤ 5.5 V
-30.0
mA
2.7 V ≤ EVDD < 4.0 V
−15.0
mA
−8.0
mA
Total of all pins
Note 3
)
(When duty = 70%
-60.0
mA
P20, P21
2.4 V ≤ EVDD < 2.7 V
−0.1
mA
−0.2
mA
Per pin
Total of all pins
Notes 1.
(1/5)
2.4 V ≤ VDD ≤ 5.5 V
Value of current at which the device operation is guaranteed even if the current flows from the VDD and
EVDD pins to an output pin.
2.
Do not exceed the total current value.
3.
Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the
following expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOH × 0.7)/(n × 0.01)
Where n = 80% and IOH = −30.0 mA
Total output current of pins = (−30.0 × 0.7)/(80 × 0.01) ≅ −26.25 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Caution P10, P12, P15, and P17 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Symbol
Output current,
Note 1
low
IOL1
Conditions
TYP.
MAX.
Note 2
8.5
Per pin for P60, P61
15.0
Note 2
Unit
mA
mA
Total of P10 to P14, P40 to P43, P120, 4.0 V ≤ EVDD ≤ 5.5 V
P130, P140 to P147
2.7 V ≤ EVDD < 4.0 V
Note 3
(When duty = 70%
)
2.4 V ≤ EVDD < 2.7 V
40.0
mA
15.0
mA
9.0
mA
4.0 V ≤ EVDD ≤ 5.5 V
40.0
mA
2.7 V ≤ EVDD < 4.0 V
35.0
mA
2,4 V ≤ EVDD < 2.7 V
20.0
mA
Total of all pins
Note 3
(When duty = 70%
)
80.0
mA
P20, P21
0.4
mA
0.8
mA
Per pin
Total of all pins
Notes 1.
MIN.
Per pin for P10 to P17, P30 to P32, P40 to P43, P50 to P54,
P70 to P74, P120, P125 to P127, P130, P140 to P147
Total of P15 to P17, P30 to P32, P50
to P54, P60, P61, P70 to P74,
P125 to P127
Note 3
)
(When duty = 70%
IOL2
(2/5)
2.4 V ≤ VDD ≤ 5.5 V
Value of current at which the device operation is guaranteed even if the current flows from the VDD and
EVDD pins to an output pin.
2.
3.
Do not exceed the total current value.
Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the
following expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOL × 0.7)/(n × 0.01)
Where n = 80% and IOL = 40.0 mA
Total output current of pins = (40.0 × 0.7)/(80 × 0.01) ≅ 35.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 83 of 131
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Input voltage,
Symbol
VIH1
Conditions
P10 to P17, P30 to P32, P40 to P43,
(3/5)
MIN.
Normal input buffer
TYP.
MAX.
Unit
0.8EVDD
EVDD
V
2.2
EVDD
V
2.0
EVDD
V
1.50
EVDD
V
P50 to P54, P70 to P74, P120,
high
P125 to P127, P140 to P147
VIH2
P10, P11, P15, P16
TTL input buffer
4.0 V ≤ EVDD ≤ 5.5 V
TTL input buffer
3.3 V ≤ EVDD < 4.0 V
TTL input buffer
2.4 V ≤ EVDD < 3.3 V
VIH3
P20, P21
0.7VDD
VDD
V
VIH4
P60, P61
0.7EVDD
EVDD
V
VIH5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0.8VDD
VDD
V
Normal input buffer
0
0.2EVDD
V
TTL input buffer
0
0.8
V
0
0.5
V
0
0.32
V
Input voltage, low VIL1
P10 to P17, P30 to P32, P40 to P43,
P50 to P54, P70 to P74, P120,
P125 to P127, P140 to P147
VIL2
P10, P11, P15, P16
4.0 V ≤ EVDD ≤ 5.5 V
TTL input buffer
3.3 V ≤ EVDD < 4.0 V
TTL input buffer
2.4 V ≤ EVDD < 3.3 V
VIL3
P20, P21
0
0.3VDD
V
VIL4
P60, P61
0
0.3EVDD
V
VIL5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0
0.2VDD
V
Caution The maximum value of VIH of pins P10, P12, P15, and P17 is EVDD, even in the N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0157EJ0210 Rev.2.10
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Page 84 of 131
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Symbol
Output voltage,
VOH1
high
Conditions
MIN.
P10 to P17, P30 to P32, P40 to P43,
4.0 V ≤ EVDD ≤ 5.5 V,
P50 to P54, P70 to P74, P120,
IOH1 = −3.0 mA
P125 to P127, P130, P140 to P147
2.7 V ≤ EVDD ≤ 5.5 V,
IOH1 = −2.0 mA
2.4 V ≤ EVDD ≤ 5.5 V,
IOH1 = −1.5 mA
VOH2
P20, P21
(4/5)
2.4 V ≤ VDD ≤ 5.5 V,
TYP.
MAX.
EVDD −
Unit
V
0.7
EVDD −
V
0.6
EVDD −
V
0.5
VDD − 0.5
V
IOH2 = −100 μ A
Output voltage,
VOL1
low
P10 to P17, P30 to P32, P40 to P43,
4.0 V ≤ EVDD ≤ 5.5 V,
P50 to P54, P70 to P74, P120,
IOL1 = 8.5 mA
P125 to P127, P130, P140 to P147
2.7 V ≤ EVDD ≤ 5.5 V,
0.7
V
0.6
V
0.4
V
0.4
V
0.4
V
2.0
V
0.4
V
0.4
V
0.4
V
IOL1 = 3.0 mA
2.7 V ≤ EVDD ≤ 5.5 V,
IOL1 = 1.5 mA
2.4 V ≤ EVDD ≤ 5.5 V,
IOL1 = 0.6 mA
VOL2
P20, P21
2.4 V ≤ VDD ≤ 5.5 V,
IOL2 = 400 μ A
VOL3
P60, P61
4.0 V ≤ EVDD ≤ 5.5 V,
IOL3 = 15.0 mA
4.0 V ≤ EVDD ≤ 5.5 V,
IOL3 = 5.0 mA
2.7 V ≤ EVDD ≤ 5.5 V,
IOL3 = 3.0 mA
2.4 V ≤ EVDD ≤ 5.5 V,
IOL3 = 2.0 mA
Caution P10, P12, P15, and P17 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 85 of 131
RL78/L12
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Input leakage
Symbol
ILIH1
Conditions
P10 to P17, P30 to P32,
(5/5)
MIN.
TYP.
MAX.
Unit
VI = EVDD
1
μA
1
μA
1
μA
10
μA
VI = EVSS
−1
μA
−1
μA
−1
μA
−10
μA
P40 to P43, P50 to P54, P60,
current, high
P61, P70 to P74, P120,
P125 to P127, P140 to P147
ILIH2
P20, P21, P137, RESET
VI = VDD
ILIH3
P121 to P124
VI = VDD
In input port or
(X1, X2, XT1, XT2, EXCLK,
external clock
EXCLKS)
input
In resonator
connection
Input leakage
ILIL1
P10 to P17, P30 to P32,
P40 to P43, P50 to P54, P60,
current, low
P61, P70 to P74, P120,
P125 to P127, P140 to P147
ILIL2
P20, P21, P137, RESET
VI = VSS
ILIL3
P121 to P124
VI = VSS
In input port or
(X1, X2, XT1, XT2, EXCLK,
external clock
EXCLKS)
input
In resonator
connection
On-chip pll-up
RU1
VI = EVSS
resistance
SEGxx port
2.4 V ≤ EVDD = VDD ≤ 5.5 V
RU2
Ports other than above
10
20
100
kΩ
10
20
100
kΩ
(Except for P60, P61, and
P130)
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
3.3.2 Supply current characteristics
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Supply
current
Symbol
IDD1
Conditions
Operating
mode
Note 1
HS (highspeed main)
Note 5
mode
fIH = 24 MHz
fIH = 16 MHz
HS (highspeed main)
Note 5
mode
Note 3
Note 3
fMX = 20 MHz
Note 2
,
VDD = 5.0 V
fMX = 20 MHz
Note 2
,
VDD = 3.0 V
fMX = 10 MHz
Note 2
,
VDD = 5.0 V
fMX = 10 MHz
Note 2
VDD = 3.0 V
Subsystem
clock
operation
fSUB = 32.768 kHz
Note 4
(1/3)
MIN.
,
TYP.
MAX.
Basic
operation
VDD = 5.0 V
1.5
mA
VDD = 3.0 V
1.5
mA
Normal
operation
VDD = 5.0 V
3.3
5.3
VDD = 3.0 V
3.3
5.3
mA
Normal
operation
VDD = 5.0 V
2.5
3.9
mA
VDD = 3.0 V
2.5
3.9
mA
Normal
operation
Square wave input
2.8
4.7
mA
Resonator connection
3.0
4.8
mA
Normal
operation
Square wave input
2.8
4.7
mA
Resonator connection
3.0
4.8
mA
Normal
operation
Square wave input
1.8
2.8
mA
Resonator connection
1.8
2.8
mA
Normal
operation
Square wave input
1.8
2.8
mA
Resonator connection
1.8
2.8
mA
Normal
operation
Square wave input
3.5
4.9
μA
Resonator connection
3.6
5.0
μA
Normal
operation
Square wave input
3.6
4.9
μA
Resonator connection
3.7
5.0
μA
Normal
operation
Square wave input
3.7
5.5
μA
Resonator connection
3.8
5.6
μA
Normal
operation
Square wave input
3.8
6.3
μA
Resonator connection
3.9
6.4
μA
Normal
operation
Square wave input
4.1
7.7
μA
Resonator connection
4.2
7.8
μA
Normal
operation
Square wave input
6.4
19.7
μA
Resonator connection
6.5
19.8
μA
TA = −40°C
f
= 32.768 kHz
SUB
Note 4
TA = +25°C
fSUB = 32.768 kHz
Note 4
TA = +50°C
fSUB = 32.768 kHz
Note 4
TA = +70°C
fSUB = 32.768 kHz
Note 4
TA = +85°C
fSUB = 32.768 kHz
Note 4
TA = +105°C
Unit
mA
(Notes and Remarks are listed on the next page.)
R01DS0157EJ0210 Rev.2.10
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Page 87 of 131
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Notes 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input
pin is fixed to VDD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral operation
current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip
pull-up/pull-down resistors and the current flowing during data flash rewrite.
2. When high-speed on-chip oscillator and subsystem clock are stopped.
3. When high-speed system clock and subsystem clock are stopped.
4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low
power consumption oscillation). However, not including the current flowing into the RTC, 12-bit interval timer,
watchdog timer, and LCD controller/driver.
5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 88 of 131
RL78/L12
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
Supply
IDD2
HALT
current
Note 2
mode
Note 1
HS (highspeed main)
Note 7
mode
HS (highspeed main)
Note 7
mode
fIH = 24 MHz
Note 4
fIH = 16 MHz
Note 4
fMX = 20 MHz
MIN.
Note 3
,
VDD = 5.0 V
fMX = 20 MHz
Note 3
,
VDD = 3.0 V
fMX = 10 MHz
Note 3
,
VDD = 5.0 V
fMX = 10 MHz
Note 3
,
VDD = 3.0 V
Subsystem
fSUB = 32.768 kHz
clock
TA = −40°C
operation
fSUB = 32.768 kHz
Note 5
Note 5
TA = +25°C
fSUB = 32.768 kHz
Note 5
TA = +50°C
fSUB = 32.768 kHz
Note 5
TA = +70°C
fSUB = 32.768 kHz
Note 5
mode
Note 8
Unit
VDD = 5.0 V
0.44
2.3
mA
VDD = 3.0 V
0.44
2.3
mA
VDD = 5.0 V
0.40
1.7
mA
VDD = 3.0 V
0.40
1.7
mA
Square wave input
0.28
1.9
mA
Resonator connection
0.45
2.0
mA
Square wave input
0.28
1.9
mA
Resonator connection
0.45
2.0
mA
Square wave input
0.19
1.02
mA
Resonator connection
0.26
1.10
mA
Square wave input
0.19
1.02
mA
Resonator connection
0.26
1.10
mA
Square wave input
0.31
0.57
μA
Resonator connection
0.50
0.76
μA
Square wave input
0.37
0.57
μA
Resonator connection
0.56
0.76
μA
Square wave input
0.46
1.17
μA
Resonator connection
0.65
1.36
μA
Square wave input
0.57
1.97
μA
Resonator connection
0.76
2.16
μA
Square wave input
0.85
3.37
μA
1.04
3.56
μA
3.04
15.37
μA
Resonator connection
3.23
15.56
μA
TA = −40°C
0.17
0.50
μA
TA = +25°C
0.23
0.50
μA
TA = +50°C
0.32
1.10
μA
TA = +70°C
0.43
1.90
μA
TA = +85°C
0.71
3.30
μA
TA = +105°C
2.90
15.30
μA
TA = +105°C
STOP
MAX.
Square wave input
fSUB = 32.768 kHz
I
TYP.
Resonator connection
TA = +85°C
Note 6
DD3
(2/3)
Note 5
(Notes and Remarks are listed on the next page.)
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 89 of 131
RL78/L12
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Notes 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input
pin is fixed to VDD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral operation
current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip
pull-up/pull-down resistors and the current flowing during data flash rewrite.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator and subsystem clock are stopped.
4. When high-speed system clock and subsystem clock are stopped.
5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting
ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not
including the current flowing into the 12-bit interval timer, watchdog timer, and LCD controller/driver.
6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer.
7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
8. Regarding the value for current operate the subsystem clock in STOP mode, refer to that in HALT mode.
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 90 of 131
RL78/L12
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Low-speed on-
Symbol
IFIL
Conditions
(3/3)
MIN.
Note 1
TYP.
MAX.
Unit
0.20
μA
0.08
μA
0.08
μA
0.24
μA
chip oscillator
operating
current
RTC operating
IRTC
current
Notes 1, 2, 3
12-bit interval
IIT
timer current
Notes 1, 2, 4
fMAIN is stopped
Watchdog timer
IWDT
operating
Notes 1, 2, 5
fIL = 15 kHz
current
A/D converter
operating
current
A/D converter
reference
voltage current
Temperature
sensor
operating
current
IADC
Notes 1, 6
When conversion
at maximum speed
Normal mode, AVREFP = VDD = 5.0 V
1.3
1.7
mA
Low voltage mode, AVREFP = VDD = 3.0 V
0.5
0.7
mA
IADREF
75.0
μA
75.0
μA
0.08
μA
Note 1
ITMPS
Note 1
LVD operating
ILVD
current
Notes 1, 7
Self-
IFSP
programming
Notes 1, 9
2.50
12.20
mA
2.50
12.20
mA
0.04
0.20
μA
1.12
3.70
μA
0.63
2.20
μA
0.12
0.50
μA
0.50
1.10
mA
1.20
2.04
mA
0.70
1.54
mA
operating
current
BGO operating
IBGO
current
Notes 1, 8
LCD operating
ILCD1
current
Notes 11, 12
External resistance division method
ILCD2
VDD = EVDD = 5.0 V
VL4 = 5.0 V
Internal voltage boosting method
Note 11
VDD = EVDD = 5.0 V
VL4 = 5.1 V (VLCD = 12H)
VDD = EVDD = 3.0 V
VL4 = 3.0 V (VLCD = 04H)
ILCD3
Note 11
Capacitor split method
ISNOZ
Note 1
ADC operation
VDD = EVDD = 3.0 V
VL4 = 3.0 V
SNOOZE
operating
The mode is performed
Note 10
The A/D conversion operations are
current
performed, Low voltage mode, AVREFP = VDD
= 3.0 V
CSI/UART operation
(Notes and Remarks are listed on the next page.)
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 91 of 131
RL78/L12
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Notes 1. Current flowing to VDD.
2. When high speed on-chip oscillator and high-speed system clock are stopped.
3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed on-chip
oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of
either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode. When the
low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the
operational current of the real-time clock.
4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip
oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of
either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT mode. When the
low-speed on-chip oscillator is selected, IFIL should be added.
5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator).
The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog
timer is in operation.
6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or
IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.
7. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2
or IDD3 and ILVD when the LVD circuit is in operation.
8. Current flowing only during data flash rewrite.
9. Current flowing only during self programming.
10. For shift time to the SNOOZE mode.
11. Current flowing only to the LCD controller/driver. The supply current value of the RL78 microcontrollers is the
sum of the LCD operating current (ILCD1, ILCD2 or ILCD3) to the supply current (IDD1 or IDD2) when the LCD
controller/driver operates in an operation mode or HALT mode. Not including the current that flows through the
LCD panel.
The TYP. value and MAX. value are following conditions.
• When fSUB is selected for system clock, LCD clock = 128 Hz (LCDC0 = 07H)
• 4-Time-Slice, 1/3 Bias Method
12. Not including the current that flows through the external divider resistor when the external resistance division
method is used.
Remarks 1. fIL:
Low-speed on-chip oscillator clock frequency
2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
3. fCLK: CPU/peripheral hardware clock frequency
4. Temperature condition of the TYP. value is TA = 25°C
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 92 of 131
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
3.4 AC Characteristics
3.4.1 Basic operation
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Instruction cycle (minimum
instruction execution time)
Symbol
TCY
Conditions
Main
system
clock (fMAIN)
operation
MIN.
TYP.
HS (high-speed 2.7 V ≤ VDD ≤ 5.5 V 0.04167
main) mode
2.4 V ≤ VDD < 2.7 V 0.0625
Subsystem clock (fSUB)
2.4 V ≤ VDD ≤ 5.5 V
28.5
30.5
MAX.
Unit
1
μs
1
μs
31.3
μs
1
μs
1
μs
operation
In the self
HS (high-speed 2.7 V ≤ VDD ≤ 5.5 V 0.04167
programming main) mode
2.4 V ≤ VDD < 2.7 V 0.0625
mode
External system clock frequency
fEX
2.7 V ≤ VDD ≤ 5.5 V
1.0
20.0
MHz
2.4 V ≤ VDD < 2.7 V
1.0
16.0
MHz
32
35
kHz
fEXS
External system clock input highlevel width, low-level width
tEXH, tEXL
2.7 V ≤ VDD ≤ 5.5 V
24
2.4 V ≤ VDD < 2.7 V
30
ns
13.7
μs
1/fMCK+10
ns
tEXHS,
tEXLS
TI00 to TI07 input high-level width, tTIH,
low-level width
tTIL
TO00 to TO07 output frequency
fTO
HS (high-speed
main) mode
HS (high-speed
main) mode
ns
4.0 V ≤ EVDD ≤ 5.5 V
16
MHz
2.7 V ≤ EVDD < 4.0 V
8
MHz
2.4 V ≤ EVDD < 2.7 V
4
MHz
4.0 V ≤ EVDD ≤ 5.5 V
16
MHz
2.7 V ≤ EVDD < 4.0 V
8
MHz
4
MHz
PCLBUZ0, PCLBUZ1 output
frequency
fPCL
Interrupt input high-level width,
low-level width
tINTH,
tINTL
INTP0
2.4 V ≤ VDD ≤ 5.5 V
1
μs
INTP1 to INTP7
2.4 V ≤ EVDD ≤ 5.5 V
1
μs
Key interrupt input low-level width
tKR
KR0 to KR3
2.4 V ≤ EVDD ≤ 5.5 V
250
ns
RESET low-level width
tRSL
10
μs
2.4 V ≤ EVDD < 2.7 V
Remark fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKS0n bit of timer mode register 0n (TMR0n).
n: Channel number (n = 0 to 7))
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Minimum Instruction Execution Time during Main System Clock Operation
TCY vs VDD (HS (high-speed main) mode)
Cycle time TCY [µs]
10
1.0
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
0.1
0.0625
0.05
0.0417
0.01
0
1.0
2.0
3.0
2.4 2.7
4.0
5.0 5.5 6.0
Supply voltage VDD [V]
AC Timing Test Points
VIH/VOH
VIL/VOL
VIH/VOH
Test points
VIL/VOL
External System Clock Timing
1/fEX/
1/fEXS
t EXL/
t EXLS
t EXH/
t EXHS
EXCLK/EXCLKS
R01DS0157EJ0210 Rev.2.10
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
TI/TO Timing
t TIL
t TIH
TI00 to TI07
1/fTO
TO00 to TO07
Interrupt Request Input Timing
t INTL
t INTH
INTP0 to INTP7
Key Interrupt Input Timing
t KR
KR0 to KR3
RESET Input Timing
t RSL
RESET
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
3.5 Peripheral Functions Characteristics
AC Timing Test Points
VIH/VOH
VIH/VOH
Test points
VIL/VOL
VIL/VOL
3.5.1 Serial array unit
(1) During communication at same potential (UART mode)
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
Transfer rate
Note 1
Unit
MAX.
fMCK/12
bps
2.0
Mbps
Theoretical value of the
maximum transfer rate
fMCK = fCLK
Note 2
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode:
24 MHz (2.7 V ≤ VDD ≤ 5.5 V)
16 MHz (2.4 V ≤ VDD ≤ 5.5 V)
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
UART mode connection diagram (during communication at same potential)
Rx
TxDq
User's device
RL78 microcontroller
RxDq
Tx
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Remarks 1.
2.
q: UART number (q = 0), g: PIM and POM number (g = 1)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01))
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
SCKp cycle time
tKCY1
2.7 V ≤ EVDD ≤ 5.5 V
2.4 V ≤ EVDD ≤ 5.5 V
SCKp high-/low-level width
SIp setup time (to SCKp↑)
Note 2
SIp hold time (from SCKp↑)
Note 3
Delay time from SCKp↓ to
SOp output
Unit
MAX.
334
Note 1
ns
500
Note 1
ns
tKH1,
4.0 V ≤ EVDD ≤ 5.5 V
tKCY1/2 − 24
ns
tKL1
2.7 V ≤ EVDD ≤ 5.5 V
tKCY1/2 − 36
ns
2.4 V ≤ EVDD ≤ 5.5 V
tKCY1/2 − 76
ns
2.7 V ≤ EVDD ≤ 5.5 V
66
ns
2.4 V ≤ EVDD ≤ 5.5 V
113
ns
2.4 V ≤ EVDD ≤ 5.5 V
38
ns
tSIK1
tKSI1
tKSO1
C = 30 pF
Note 5
2.4 V ≤ EVDD ≤ 5.5 V
50
ns
Note 4
Notes 1. Set a cycle of 4/fMCK or longer.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin
by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM numbers (g = 1)
2.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01))
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
SCKp cycle time
Note 5
tKCY2
4.0 V ≤ EVDD ≤ 5.5 V
2.7 V ≤ EVDD < 4.0 V
Unit
MAX.
20 MHz < fMCK
16/fMCK
ns
fMCK ≤ 20 MHz
12/fMCK
ns
16 MHz < fMCK
16/fMCK
ns
fMCK ≤ 16 MHz
12/fMCK
ns
12/fMCK and 1000
ns
2.4 V ≤ EVDD ≤ 5.5 V
SCKp high-/low-level
tKH2,
4.0 V ≤ EVDD ≤ 5.5 V
tKCY2/2 − 14
ns
width
tKL2
2.7 V ≤ EVDD < 4.0 V
tKCY2/2 − 16
ns
2.4 V ≤ EVDD < 2.7 V
tKCY2/2 − 36
ns
2.7 V ≤ EVDD ≤ 5.5 V
1/fMCK + 40
ns
2.4 V ≤ EVDD < 2.7 V
1/fMCK + 60
ns
tKSI2
2.4 V ≤ EVDD ≤ 5.5 V
1/fMCK + 62
ns
tKSO2
C = 30 pF
SIp setup time
(to SCKp↑)
tSIK2
Note 1
SIp hold time
(from SCKp↑)
Note 2
Delay time from SCKp↓
to SOp output
Note 4
Note 3
4.0 V ≤ EVDD ≤ 5.5 V
2/fMCK + 66
ns
2.7 V ≤ EVDD < 4.0 V
2/fMCK + 66
ns
2.4 V ≤ EVDD < 2.7 V
2/fMCK + 113
Ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SOp output lines.
5. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin
by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM number (g = 1)
2.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01))
CSI mode connection diagram (during communication at same potential)
SCKp
RL78
SIp
microcontroller
SOp
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
SCK
SO User's device
SI
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
t KCY1, 2
t KL1, 2
t KH1, 2
SCKp
t SIK1, 2
SIp
t KSI1, 2
Input data
t KSO1, 2
Output data
SOp
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
t KCY1, 2
t KH1, 2
t KL1, 2
SCKp
t SIK1, 2
SIp
t KSI1, 2
Input data
t KSO1, 2
SOp
Remarks 1.
2.
Output data
p: CSI number (p = 00, 01)
m: Unit number, n: Channel number (mn = 00, 01)
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(4) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode)
(1/2)
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
Transfer rate
Reception
4.0 V ≤ EVDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
MAX.
Note 1
fMCK/12
Theoretical value of the
Unit
2.0
bps
Mbps
maximum transfer rate
fMCK = fCLK
Note 2
2.7 V ≤ EVDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
Note 1
fMCK/12
Theoretical value of the
bps
2.0
Mbps
fMCK/12
bps
maximum transfer rate
fMCK = fCLK
Note 2
2.4 V ≤ EVDD < 3.3 V,
Note 1
1.6 V ≤ Vb ≤ 2.0 V
Theoretical value of the
2.0
Mbps
maximum transfer rate
fMCK = fCLK
Note 2
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode:
24 MHz (2.7 V ≤ VDD ≤ 5.5 V)
16 MHz (2.4 V ≤ VDD ≤ 5.5 V)
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (32- to 52-pin
products)/EVDD tolerance (64-pin products)) mode for the TxDq pin by using port input mode register g
(PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL
input buffer selected.
Remarks 1.
Vb[V]: Communication line voltage
2.
q: UART number (q = 0), g: PIM and POM number (g = 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(4) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode)
(2/2)
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
MAX.
Transmission 4.0 V ≤ EVDD ≤ 5.5 V,
Transfer rate
2.7 V ≤ Vb ≤ 4.0 V
Unit
Note 1
Theoretical value of the
2.0
Note 2
bps
Mbps
maximum transfer rate
Cb = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V
2.7 V ≤ EVDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
Note 3
Theoretical value of the
1.2
Note 4
bps
Mbps
maximum transfer rate
Cb = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V
2.4 V ≤ EVDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Note 5
bps
Theoretical value of the
0.43
Mbps
maximum transfer rate
Note 6
Cb = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V
Notes 1.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 4.0 V ≤ EVDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V
1
Maximum transfer rate =
{−Cb × Rb × ln (1 −
Baud rate error (theoretical value) =
2.2
Vb )} × 3
[bps]
2.2
1
− {−Cb × Rb × ln (1 − Vb )}
Transfer rate × 2
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
3.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ EVDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V
1
Maximum transfer rate =
{−Cb × Rb × ln (1 −
Baud rate error (theoretical value) =
2.0
Vb )} × 3
[bps]
2.0
1
− {−Cb × Rb × ln (1 − Vb )}
Transfer rate × 2
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
4.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
R01DS0157EJ0210 Rev.2.10
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5.
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 1.8 V ≤ EVDD < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V
1
Maximum transfer rate =
{−Cb × Rb × ln (1 −
Baud rate error (theoretical value) =
1.5
Vb )} × 3
[bps]
1.5
1
− {−Cb × Rb × ln (1 − Vb )}
Transfer rate × 2
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
6.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (32- to 52-pin
products)/EVDD tolerance (64-pin products)) mode for the TxDq pin by using port input mode register g
(PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL
input buffer selected.
UART mode connection diagram (during communication at different potential)
Vb
Rb
TxDq
Rx
RL78 microcontroller
RxDq
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
User's device
Tx
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Remarks 1.
Rb[Ω]:Communication line (TxDq) pull-up resistance,
Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
2.
q: UART number (q = 0, 1), g: PIM and POM number (g = 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01))
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(5) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output)
(1/2)
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
SCKp cycle time
tKCY1
tKCY1 ≥ 4/fCLK
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Unit
MAX.
600
ns
600
ns
2300
ns
tKCY1/2 − 150
ns
tKCY1/2 − 340
ns
tKCY1/2 − 916
ns
tKCY1/2 − 24
ns
tKCY1/2 − 36
ns
tKCY1/2 − 100
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SCKp high-level width
tKH1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SCKp low-level width
tKL1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (32- to 52-pin
products)/EVDD tolerance (64-pin products)) mode for the SOp pin and SCKp pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
For VIH and VIL, see the DC
characteristics with TTL input buffer selected.
R01DS0157EJ0210 Rev.2.10
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(5) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output)
(2/2)
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
SIp setup time
Note 1
(to SCKp↑)
tSIK1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Unit
MAX.
162
ns
354
ns
958
ns
38
ns
38
ns
38
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SIp hold time
Note 1
(from SCKp↑)
tKSI1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Delay time from SCKp↓ to
Note 1
SOp output
tKSO1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
200
ns
390
ns
966
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 2.7 kΩ
SIp setup time
Note
(to SCKp↓)
tSIK1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
88
ns
88
ns
220
ns
38
ns
38
ns
38
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SIp hold time
Note 2
(from SCKp↓)
tKSI1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Delay time from SCKp↑ to
Note 2
SOp output
tKSO1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
50
ns
50
ns
50
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
(Notes, Caution and Remarks are listed on the page after the next page.)
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (32- to 52-pin
products)/EVDD tolerance (64-pin products)) mode for the SOp pin and SCKp pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
For VIH and VIL, see the DC
characteristics with TTL input buffer selected.
CSI mode connection diagram (during communication at different potential)
Vb
Rb
SCKp
SIp
RL78
microcontroller
SOp
Vb
Rb
SCK
SO
User's device
SI
Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance,
Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM number (g = 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number, n: Channel number (mn = 00))
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
t KCY1
t KL1
t KH1
SCKp
t SIK1
SIp
t KSI1
Input data
t KSO1
SOp
Output data
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
t KCY1
t KL1
t KH1
SCKp
t SIK1
SIp
t KSI1
Input data
t KSO1
SOp
Remark
Output data
p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM number (g = 1)
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
SCKp cycle time
Note 1
SCKp high-/low-level width
tKCY2
Unit
MAX.
4.0 V ≤ EVDD ≤ 5.5 V,
20 MHz < fMCK ≤ 24 MHz
24/fMCK
ns
2.7 V ≤ Vb ≤ 4.0 V
8 MHz < fMCK ≤ 20 MHz
20/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK
ns
fMCK ≤ 4 MHz
12/fMCK
ns
2.7 V ≤ EVDD < 4.0 V,
20 MHz < fMCK ≤ 24 MHz
32/fMCK
ns
2.3 V ≤ Vb ≤ 2.7 V
16 MHz < fMCK ≤ 20 MHz
28/fMCK
ns
8 MHz < fMCK ≤ 16 MHz
24/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK
ns
fMCK ≤ 4 MHz
12/fMCK
ns
2.4 V ≤ EVDD < 3.3 V,
20 MHz < fMCK ≤ 24 MHz
72/fMCK
ns
1.6 V ≤ Vb ≤ 2.0 V
16 MHz < fMCK ≤ 20 MHz
64/fMCK
ns
8 MHz < fMCK ≤ 16 MHz
52/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
32/fMCK
ns
fMCK ≤ 4 MHz
20/fMCK
ns
tKCY2/2 − 24
ns
tKCY2/2 − 36
ns
tKCY2/2 − 100
ns
1/fMCK + 40
ns
1/fMCK + 40
ns
1/fMCK + 60
ns
1/fMCK + 62
ns
1/fMCK + 62
ns
1/fMCK + 62
ns
tKH2,
4.0 V ≤ EVDD ≤ 5.5 V,
tKL2
2.7 V ≤ Vb ≤ 4.0 V
2.7 V ≤ EVDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
2.4 V ≤ EVDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
SIp setup time
(to SCKp↑)
tSIK2
Note2
4.0 V ≤ EVDD < 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
2.7 V ≤ EVDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
2.4 V ≤ EVDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
SIp hold time
(from SCKp↑)
tKSI2
Note 3
4.0 V ≤ EVDD < 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
2.7 V ≤ EVDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
2.4 V ≤ EVDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Delay time from SCKp↓ to
SOp output
tKSO2
Note 4
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
2/fMCK + 240
ns
2/fMCK + 428
ns
2/fMCK + 1146
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Cb = 30 pF, Rb = 5.5 kΩ
(Notes, Caution and Remarks are listed on the page after the next page.)
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution
Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance
(32- to 52-pin products)/EVDD tolerance (64-pin products)) mode for the SOp pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
For VIH and VIL, see the DC
characteristics with TTL input buffer selected.
CSI mode connection diagram (during communication at different potential)
Vb
Rb
SCKp
RL78
microcontroller
SCK
SIp
SO
SOp
SI
User's device
Remarks 1. Rb[Ω]:Communication line (SOp) pull-up resistance,
Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM number (g = 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01))
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Page 109 of 131
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
t KCY2
t KL 2
t KH 2
SCKp
t SIK2
SIp
t KSI2
Input data
t KSO 2
Output data
SOp
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
t KCY2
t KL 2
t KH 2
SCKp
t SI K2
SIp
t KSI 2
Input data
t KSO 2
SOp
Remark
Output data
p: CSI number (p = 00, 01), m: Unit number (m = 0),
n: Channel number (n = 0, 1), g: PIM and POM number (g = 1)
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
3.5.2 Serial interface IICA
2
(1) I C standard mode
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
SCLA0 clock frequency
fSCL
Setup time of restart condition
Hold time
Note 1
tHD:STA
Hold time when SCLA0 = “L”
tLOW
Hold time when SCLA0 = “H”
tHIGH
Data setup time (reception)
Data hold time (transmission)
tSU:DAT
Note 2
Setup time of stop condition
Bus-free time
Notes 1.
2.
Remark
tSU:STA
tHD:DAT
tSU:STO
tBUF
Conditions
HS (high-speed main) Mode
MIN.
MAX.
Unit
Standard mode:
2.7 V ≤ EVDD ≤ 5.5 V
0
100
kHz
fCLK ≥ 1 MHz
2.4 V ≤ EVDD ≤ 5.5 V
0
100
kHz
2.7 V ≤ EVDD ≤ 5.5 V
4.7
μs
2.4 V ≤ EVDD ≤ 5.5 V
4.7
μs
2.7 V ≤ EVDD ≤ 5.5 V
4.0
μs
2.4 V ≤ EVDD ≤ 5.5 V
4.0
μs
2.7 V ≤ EVDD ≤ 5.5 V
4.7
μs
2.4 V ≤ EVDD ≤ 5.5 V
4.7
μs
2.7 V ≤ EVDD ≤ 5.5 V
4.0
μs
2.4 V ≤ EVDD ≤ 5.5 V
4.0
μs
2.7 V ≤ EVDD ≤ 5.5 V
250
ns
2.4 V ≤ EVDD ≤ 5.5 V
250
ns
2.7 V ≤ EVDD ≤ 5.5 V
0
3.45
μs
2.4 V ≤ EVDD ≤ 5.5 V
0
3.45
μs
2.7 V ≤ EVDD ≤ 5.5 V
4.0
μs
2.4 V ≤ EVDD ≤ 5.5 V
4.0
μs
2.7 V ≤ EVDD ≤ 5.5 V
4.7
μs
2.4 V ≤ EVDD ≤ 5.5 V
4.7
μs
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 kΩ
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
2
(2) I C fast mode
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
SCLA0 clock frequency
fSCL
Setup time of restart condition
Hold time
Note 1
tHD:STA
Hold time when SCLA0 = “L”
tLOW
Hold time when SCLA0 = “H”
tHIGH
Data setup time (reception)
Data hold time (transmission)
tSU:DAT
Note 2
Setup time of stop condition
Bus-free time
Notes 1.
2.
tSU:STA
tHD:DAT
tSU:STO
tBUF
Conditions
Fast mode:
fCLK ≥ 3.5 MHz
HS (high-speed main) Mode
MIN.
MAX.
2.7 V ≤ EVDD ≤ 5.5 V
0
400
2.4 V ≤ EVDD ≤ 5.5 V
0
400
2.7 V ≤ EVDD ≤ 5.5 V
0.6
2.4 V ≤ EVDD ≤ 5.5 V
0.6
2.7 V ≤ EVDD ≤ 5.5 V
0.6
2.4 V ≤ EVDD ≤ 5.5 V
0.6
2.7 V ≤ EVDD ≤ 5.5 V
1.3
2.4 V ≤ EVDD ≤ 5.5 V
1.3
2.7 V ≤ EVDD ≤ 5.5 V
0.6
2.4 V ≤ EVDD ≤ 5.5 V
0.6
2.7 V ≤ EVDD ≤ 5.5 V
100
2.4 V ≤ EVDD ≤ 5.5 V
100
Unit
kHz
μs
μs
μs
μs
ns
2.7 V ≤ EVDD ≤ 5.5 V
0
0.9
2.4 V ≤ EVDD ≤ 5.5 V
0
0.9
2.7 V ≤ EVDD ≤ 5.5 V
0.6
2.4 V ≤ EVDD ≤ 5.5 V
0.6
2.7 V ≤ EVDD ≤ 5.5 V
1.3
2.4 V ≤ EVDD ≤ 5.5 V
1.3
μs
μs
μs
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Fast mode:
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Cb = 320 pF, Rb = 1.1 kΩ
Page 112 of 131
RL78/L12
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
3.6 Analog Characteristics
3.6.1 A/D converter characteristics
Classification of A/D converter characteristics
Reference Voltage
Input channel
Reference voltage (+) = AVREFP
Reference voltage (+) = VDD
Reference voltage (+) = VBGR
Reference voltage (−) = AVREFM
Reference voltage (−) = VSS
Reference voltage (−) = AVREFM
ANI0, ANI1
−
ANI16 to ANI23
Refer to 3.6.1 (2).
Internal reference voltage
Refer to 3.6.1 (1).
Refer to 3.6.1 (3).
Refer to 3.6.1 (4).
−
Temperature sensor output
voltage
(1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1
(ADREFM = 1), target pin : internal reference voltage, and temperature sensor output voltage
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+)
= AVREFP, Reference voltage (−) = AVREFM = 0 V)
Parameter
Resolution
Symbol
Conditions
RES
Note 1
Overall error
AINL
tCONV
TYP.
8
10-bit resolution
AVREFP = VDD
Conversion time
MIN.
2.4 V ≤ AVREFP ≤ 5.5 V
1.2
MAX.
Unit
10
bit
±3.5
LSB
Note 3
10-bit resolution
3.6 V ≤ VDD ≤ 5.5 V
2.375
39
μs
Target pin: Internal reference
2.7 V ≤ VDD ≤ 5.5 V
3.5625
39
μs
2.4 V ≤ VDD ≤ 5.5 V
17
39
μs
voltage, and temperature
sensor output voltage (HS
(high-speed main) mode)
EZS
10-bit resolution
Note 3
AVREFP = VDD
1.8 V ≤ AVREFP ≤ 5.5 V
±0.25
%FSR
Full-scale error
Notes 1, 2
EFS
10-bit resolution
Note 3
AVREFP = VDD
1.8 V ≤ AVREFP ≤ 5.5 V
±0.25
%FSR
Integral linearity error
ILE
10-bit resolution
1.8 V ≤ AVREFP ≤ 5.5 V
±2.5
LSB
1.8 V ≤ AVREFP ≤ 5.5 V
±1.5
LSB
Notes 1, 2
Zero-scale error
Note 1
AVREFP = VDD
Differential linearity error
DLE
Note 1
10-bit resolution
AVREFP = VDD
Analog input voltage
VAIN
Note 3
Note 3
Internal reference voltage
VBGR
Note 4
V
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode)
Temperature sensor output voltage
VTMPS25
Note 4
V
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode)
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD.
4. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics.
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1
(ADREFM = 1), target pin : ANI16 to ANI23
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+)
= AVREFP, Reference voltage (−) = AVREFM = 0 V)
Parameter
Symbol
Resolution
Conditions
RES
Note 1
Overall error
AINL
tCONV
Zero-scale error
Notes 1, 2
Full-scale error
Integral linearity error
Note 1
Unit
10
bit
±5.0
LSB
Note 3
3.6 V ≤ VDD ≤ 5.5 V
2.125
39
μs
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
μs
2.4 V ≤ VDD ≤ 5.5 V
17
39
μs
EZS
10-bit resolution
Note 3
AVREFP = EVDD = VDD
2.4 V ≤ AVREFP ≤ 5.5 V
±0.35
%FSR
EFS
10-bit resolution
Note 3
AVREFP = EVDD = VDD
2.4 V ≤ AVREFP ≤ 5.5 V
±0.35
%FSR
ILE
10-bit resolution
2.4 V ≤ AVREFP ≤ 5.5 V
±3.5
LSB
2.4 V ≤ AVREFP ≤ 5.5 V
±2.0
LSB
AVREFP
V
DLE
Note 1
VAIN
Note 3
10-bit resolution
AVREFP = EVDD = VDD
Analog input voltage
1.2
MAX.
Note 3
10-bit resolution
AVREFP = EVDD = VDD
Differential linearity error
2.4 V ≤ AVREFP ≤ 5.5 V
10-bit resolution
AVREFP = EVDD = VDD
Notes 1, 2
TYP.
8
AVREFP = EVDD = VDD
Conversion time
MIN.
Note 3
ANI16 to ANI23
0
and EVDD
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < EVDD = VDD, the MAX. values are as follows.
Overall error: Add ±4.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.20%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±2.0 LSB to the MAX. value when AVREFP = VDD.
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (−) = VSS (ADREFM = 0),
target pin : ANI0, ANI1, ANI16 to ANI23, internal reference voltage, and temperature sensor output voltage
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = VDD, Reference voltage (−)
= VSS)
Parameter
Symbol
Resolution
Conditions
MIN.
RES
Note 1
TYP.
8
MAX.
Unit
10
bit
Overall error
AINL
10-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±7.0
LSB
Conversion time
tCONV
10-bit resolution
3.6 V ≤ VDD ≤ 5.5 V
2.125
39
μs
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
μs
2.4 V ≤ VDD ≤ 5.5 V
17
39
μs
10-bit resolution
3.6 V ≤ VDD ≤ 5.5 V
2.375
39
μs
Target pin: Internal reference
2.7 V ≤ VDD ≤ 5.5 V
3.5625
39
μs
2.4 V ≤ VDD ≤ 5.5 V
17
39
μs
voltage, and temperature
sensor output voltage (HS
1.2
(high-speed main) mode)
Notes 1, 2
Zero-scale error
Notes 1, 2
Full-scale error
Integral linearity error
Note 1
Differential linearity error
EZS
10-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
EFS
10-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
ILE
10-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±4.0
LSB
DLE
10-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±2.0
LSB
VAIN
ANI0, ANI1
0
VDD
V
ANI16 to ANI23
0
EVDD
V
Note 1
Analog input voltage
Internal reference voltage output
VBGR
Note 3
V
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode)
Temperature sensor output voltage
VTMPS25
Note 3
V
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode)
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics.
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (−) =
AVREFM/ANI1 (ADREFM = 1), target pin : ANI0, ANI16 to ANI23
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = VBGR Note 3, Reference
voltage (−) = AVREFM Note 4 = 0 V, HS (high-speed main) mode)
Parameter
Symbol
Resolution
Conditions
MIN.
RES
Conversion time
Notes 1, 2
Zero-scale error
Integral linearity error
Note 1
Differential linearity error
Note 1
Analog input voltage
TYP.
MAX.
8
Unit
bit
tCONV
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
39
μs
EZS
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
ILE
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±2.0
LSB
DLE
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±1.0
LSB
VAIN
17
0
VBGR
Note 3
V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics.
4. When reference voltage (−) = VSS, the MAX. values are as follows.
Zero-scale error: Add ±0.35%FSR to the MAX. value when reference voltage (−) = AVREFM.
Integral linearity error: Add ±0.5 LSB to the MAX. value when reference voltage (−) = AVREFM.
Differential linearity error: Add ±0.2 LSB to the MAX. value when reference voltage (−) = AVREFM.
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 116 of 131
RL78/L12
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
3.6.2 Temperature sensor/internal reference voltage characteristics
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, HS (high-speed main) mode)
Parameter
Symbol
Conditions
MIN.
Temperature sensor output voltage
VTMPS25
Setting ADS register = 80H, TA = +25°C
Internal reference voltage
VBGR
Setting ADS register = 81H
Temperature coefficient
FVTMPS
Temperature sensor that depends on the
TYP.
MAX.
1.05
1.38
1.45
Unit
V
1.5
−3.6
V
mV/°C
temperature
Operation stabilization wait time
tAMP
μs
5
3.6.3 POR circuit characteristics
(TA = −40 to +105°C, VSS = 0 V)
Parameter
Symbol
Detection voltage
Minimum pulse width
Conditions
MIN.
TYP.
MAX.
Unit
VPOR
Power supply rise time
1.45
1.51
1.57
V
VPDR
Power supply fall time
1.44
1.50
1.56
V
TPW
μs
300
Note Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a
POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main
system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control
register (CSC).
TPW
Supply voltage (VDD)
VPOR
VPDR or 0.7 V
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 117 of 131
RL78/L12
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
3.6.4 LVD circuit characteristics
(TA = −40 to +105°C, VPDR ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Detection
Symbol
Supply voltage level
VLVD0
voltage
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Minimum pulse width
Conditions
MIN.
TYP.
MAX.
Unit
Power supply rise time
3.90
4.06
4.22
V
Power supply fall time
3.83
3.98
4.13
V
Power supply rise time
3.60
3.75
3.90
V
Power supply fall time
3.53
3.67
3.81
V
Power supply rise time
3.01
3.13
3.25
V
Power supply fall time
2.94
3.06
3.18
V
Power supply rise time
2.90
3.02
3.14
V
Power supply fall time
2.85
2.96
3.07
V
Power supply rise time
2.81
2.92
3.03
V
Power supply fall time
2.75
2.86
2.97
V
Power supply rise time
2.70
2.81
2.92
V
Power supply fall time
2.64
2.75
2.86
V
Power supply rise time
2.61
2.71
2.81
V
Power supply fall time
2.55
2.65
2.75
V
Power supply rise time
2.51
2.61
2.71
V
Power supply fall time
2.45
2.55
2.65
V
tLW
μs
300
Detection delay time
300
μs
LVD Detection Voltage of Interrupt & Reset Mode
(TA = −40 to +105°C, VPDR ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Interrupt and reset
VLVDD0
mode
VLVDD1
Conditions
MIN.
TYP.
MAX.
Unit
2.64
2.75
2.86
V
Rising release reset voltage
2.81
2.92
3.03
V
Falling interrupt voltage
2.75
2.86
2.97
V
Rising release reset voltage
2.90
3.02
3.14
V
Falling interrupt voltage
2.85
2.96
3.07
V
Rising release reset voltage
3.90
4.06
4.22
V
VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage
VLVDD2
VLVDD3
LVIS1, LVIS0 = 1, 0
LVIS1, LVIS0 = 0, 1
LVIS1, LVIS0 = 0, 0
Falling interrupt voltage
3.83
3.98
4.13
V
MIN.
TYP.
MAX.
Unit
54
V/ms
3.6.5 Power supply voltage rising slope characteristics
(TA = −40 to +105°C, VSS = 0 V)
Parameter
Power supply voltage rising slope
Caution
Symbol
Conditions
SVDD
Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the
operating voltage range shown in 31.4 AC Characteristics.
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 118 of 131
RL78/L12
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
3.7 LCD Characteristics
3.7.1 Resistance division method
(1) Static display mode
(TA = −40 to +105°C, VL4 (MIN.) ≤ VDDNote ≤ 5.5 V, VSS = 0 V)
Parameter
LCD drive voltage
Symbol
Conditions
VL4
MIN.
TYP.
2.0
MAX.
Unit
VDD
V
MAX.
Unit
VDD
V
MAX.
Unit
VDD
V
Note Must be 2.4 V or higher.
(2) 1/2 bias method, 1/4 bias method
(TA = −40 to +105°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
LCD drive voltage
Symbol
Conditions
VL4
MIN.
TYP.
2.7
(3) 1/3 bias method
(TA = −40 to +105°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
LCD drive voltage
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Symbol
VL4
Conditions
MIN.
2.5
TYP.
Page 119 of 131
RL78/L12
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
3.7.2 Internal voltage boosting method
(1) 1/3 bias method
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
LCD output voltage variation range
VL1
Conditions
Note 1
MAX.
Unit
C1 to C4
VLCD = 04H
0.90
1.00
1.08
V
VLCD = 05H
0.95
1.05
1.13
V
VLCD = 06H
1.00
1.10
1.18
V
VLCD = 07H
1.05
1.15
1.23
V
VLCD = 08H
1.10
1.20
1.28
V
VLCD = 09H
1.15
1.25
1.33
V
1.30
1.38
V
V
VLCD = 0BH
1.25
1.35
VLCD = 0CH
1.30
1.40
1.48
V
VLCD = 0DH
1.35
1.45
1.53
V
VLCD = 0EH
1.40
1.50
1.58
V
VLCD = 0FH
1.45
1.55
1.63
V
VLCD = 10H
1.50
1.60
1.68
V
VLCD = 11H
1.55
1.65
1.73
V
1.70
1.78
V
1.65
1.75
1.83
V
2 VL1
2 VL1
2 VL1
V
3 VL1
3 VL1
V
VLCD = 13H
Note 1
C1 to C4
1.20
1.43
VLCD = 12H
VL2
TYP.
= 0.47 μF
VLCD = 0AH
Doubler output voltage
MIN.
= 0.47 μF
1.60
−0.1
Tripler output voltage
VL4
Note 1
C1 to C4
= 0.47 μF
3 VL1
−0.15
Reference voltage setup time
Voltage boost wait time
Note 2
Note 3
tVWAIT1
tVWAIT2
Note 1
C1 to C4
= 0.47 μF
5
ms
500
ms
Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = 0.47 μF±30%
2. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or
when the internal voltage boosting method is selected [by setting the MDSET1 and MDSET0 bits of the
LCDM0 register to 01B] if the default value reference voltage is used) until voltage boosting starts (VLCON = 1).
3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 120 of 131
RL78/L12
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
(2) 1/4 bias method
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
LCD output voltage variation range
VL1
Note 4
Conditions
C1 to C5
Note 1
= 0.47 μF
Doubler output voltage
VL2
Tripler output voltage
Quadruply output voltage
Reference voltage setup time
Voltage boost wait time
Notes 1.
VL4
Note 2
Note 3
MAX.
Unit
VLCD = 04H
0.90
1.00
1.08
V
VLCD = 05H
0.95
1.05
1.13
V
VLCD = 06H
1.00
1.10
1.18
V
VLCD = 07H
1.05
1.15
1.23
V
VLCD = 08H
1.10
1.20
1.28
V
VLCD = 09H
1.15
1.25
1.33
V
VLCD = 0AH
1.20
1.30
1.38
V
VLCD = 0BH
1.25
1.35
1.43
V
VLCD = 0CH
1.30
1.40
1.48
V
VLCD = 0DH
1.35
1.45
1.53
V
VLCD = 0EH
1.40
1.50
1.58
V
VLCD = 0FH
1.45
1.55
1.63
V
VLCD = 10H
1.50
1.60
1.68
V
VLCD = 11H
1.55
1.65
1.73
V
VLCD = 12H
1.60
1.70
1.78
V
VLCD = 13H
1.65
1.75
1.83
V
= 0.47 μF
2 VL1 − 0.08
2 VL1
2 VL1
V
Note 1
= 0.47 μF
3 VL1 − 0.12
3 VL1
3 VL1
V
Note 1
= 0.47 μF
4 VL1 − 0.16
4 VL1
4 VL1
V
C1 to C5
Note 4
TYP.
Note 1
C1 to C5
VL3
MIN.
C1 to C5
tVWAIT1
tVWAIT2
Note 1
C1 to C5
= 0.47 μF
5
ms
500
ms
This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL3 and GND
C5: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = C5 = 0.47 μF±30%
2.
This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when
the internal voltage boosting method is selected [by setting the MDSET1 and MDSET0 bits of the LCDM0
register to 01B] if the default value reference voltage is used) until voltage boosting starts (VLCON = 1).
3.
This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).
4.
VL4 must be 5.5 V or lower.
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 121 of 131
RL78/L12
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
3.7.3 Capacitor split method
1/3 bias method
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
VL4 voltage
VL4
Conditions
MAX.
VDD
Unit
V
Note 2
2/3 VL4
− 0.1
2/3 VL4
2/3 VL4
+ 0.1
V
Note 2
1/3 VL4
− 0.1
1/3 VL4
1/3 VL4
+ 0.1
V
VL2
C1 to C4 = 0.47 μ F
VL1 voltage
VL1
C1 to C4 = 0.47 μ F
Note 1
TYP.
C1 to C4 = 0.47 μ F
VL2 voltage
Capacitor split wait time
MIN.
Note 2
tVWAIT
100
ms
Notes 1. This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1).
2. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = 0.47 μF±30%
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 122 of 131
RL78/L12
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
3.8 RAM Data Retention Characteristics
(TA = −40 to +105°C, VSS = 0 V)
Parameter
Symbol
Data retention supply voltage
Conditions
MIN.
VDDDR
1.44
TYP.
MAX.
Unit
5.5
V
Note
Note This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage
reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated.
Operation mode
STOP mode
RAM Data retention mode
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
3.9 Flash Memory Programming Characteristics
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
System clock frequency
fCLK
1.8 V ≤ VDD ≤ 5.5 V
Number of code flash rewrites
Cerwr
Retained for 20 years
Notes 1, 2, 3
MIN.
TYP.
1
MAX.
Unit
24
1,000
MHz
Times
Note 4
TA = 85°C
Number of data flash rewrites
Notes 1, 2, 3
Retained for 1 year
1,000,000
Note 4
TA = 25°C
Retained for 5 years
100,000
Note 4
TA = 85°C
Retained for 20 years
10,000
Note 4
TA = 85°C
Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite.
The retaining years are until next rewrite after the rewrite.
2. When using flash memory programmer and Renesas Electronics self programming library
3. This characteristic indicates the flash memory characteristic and based on Renesas Electronics reliability test.
4. This temperature is the average value at which data are retained.
3.10 Dedicated Flash Memory Programmer Communication (UART)
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Transfer rate
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Symbol
Conditions
During flash memory programming
MIN.
115,200
TYP.
MAX.
Unit
1,000,000
bps
Page 123 of 131
RL78/L12
3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
3.11 Timing Specifications for Switching Flash Memory Programming Modes
(TA = −40 to +105°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Time to complete the communication
tSUINIT
Conditions
MIN.
POR and LVD reset must be released before
TYP.
MAX.
Unit
100
ms
the external reset is released.
for the initial setting after the external
reset is released
Time to release the external reset
tSU
POR and LVD reset must be released before
10
μs
1
ms
the external reset is released.
after the TOOL0 pin is set to the low
level
Time to hold the TOOL0 pin at the
tHD
low level after the external reset is
POR and LVD reset must be released before
the external reset is released.
released
(excluding the processing time of the
firmware to control the flash memory)
RESET
tH D +
soft processing
time
1-byte data for mode setting
TOOL0
t SU
t SUINIT
The low level is input to the TOOL0 pin.
The external reset is released (POR and LVD reset must be released before the external
reset is released.).
The TOOL0 pin is set to the high level.
Setting of the flash memory programming mode by UART reception and complete the baud
rate setting.
Remark tSUINIT: Communication for the initial setting must be completed within 100 ms after the external reset is released
during this period.
tSU:
Time to release the external reset after the TOOL0 pin is set to the low level
tHD:
Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing
time of the firmware to control the flash memory)
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 124 of 131
RL78/L12
4. PACKAGE DRAWINGS
4. PACKAGE DRAWINGS
4.1 32-pin Products
R5F10RB8AFP, R5F10RBAAFP, R5F10RBCAFP
R5F10RB8GFP, R5F10RBAGFP, R5F10RBCGFP
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LQFP32-7x7-0.80
PLQP0032GB-A
P32GA-80-GBT-1
0.2
HD
2
D
17
16
24
25
detail of lead end
1
E
c
HE
θ
32
8
1
L
9
e
(UNIT:mm)
3
b
x
M
A
A2
ITEM
D
DIMENSIONS
7.00±0.10
E
7.00±0.10
HD
9.00±0.20
HE
9.00±0.20
A
1.70 MAX.
A1
0.10±0.10
A2
y
A1
1.40
b
0.37±0.05
c
0.145 ±0.055
L
0.50±0.20
θ
0° to 8°
e
0.80
1.Dimensions “ 1” and “ 2” do not include mold flash.
x
0.20
2.Dimension “ 3” does not include trim offset.
y
0.10
NOTE
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 125 of 131
RL78/L12
4. PACKAGE DRAWINGS
4.2 44-pin Products
R5F10RF8AFP, R5F10RFAAFP, R5F10RFCAFP
R5F10RF8GFP, R5F10RFAGFP, R5F10RFCGFP
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LQFP44-10x10-0.80
PLQP0044GC-A
P44GB-80-UES-2
0.36
HD
D
detail of lead end
A3
23
22
33
34
c
L
E
Lp
HE
L1
(UNIT:mm)
12
11
44
1
ZE
e
ZD
b
x
M
S
A
S
S
NOTE
Each lead centerline is located within 0.20 mm of
its true position at maximum material condition.
A1
DIMENSIONS
10.00±0.20
E
10.00±0.20
HD
12.00±0.20
HE
12.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
A2
y
ITEM
D
0.25
b
0.37 +0.08
0.07
c
0.145 +0.055
0.045
L
0.50
Lp
0.60±0.15
L1
1.00±0.20
3° +5°
3°
e
0.80
x
0.20
y
0.10
ZD
1.00
ZE
1.00
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 126 of 131
RL78/L12
4. PACKAGE DRAWINGS
4.3 48-pin Products
R5F10RG8AFB, R5F10RGAAFB, R5F10RGCAFB
R5F10RG8GFB, R5F10RGAGFB, R5F10RGCGFB
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LFQFP48-7x7-0.50
PLQP0048KF-A
P48GA-50-8EU-1
0.16
HD
D
detail of lead end
36
25
37
A3
24
c
L
E
Lp
HE
L1
(UNIT:mm)
13
48
12
1
ZE
e
ZD
b
x
M
S
A
ITEM
D
DIMENSIONS
7.00±0.20
E
7.00±0.20
HD
9.00±0.20
HE
9.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
b
A2
c
L
S
y
S
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
A1
0.25
0.22±0.05
0.145 +0.055
0.045
0.50
Lp
0.60±0.15
L1
1.00±0.20
3° +5°
3°
e
0.50
x
0.08
y
0.08
ZD
0.75
ZE
0.75
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 127 of 131
RL78/L12
4. PACKAGE DRAWINGS
4.4 52-pin Products
R5F10RJ8AFA, R5F10RJAAFA, R5F10RJCAFA
R5F10RJ8GFA, R5F10RJAGFA, R5F10RJCGFA
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LQFP52-10x10-0.65
PLQP0052JA-A
P52GB-65-GBS-1
0.3
HD
D
2
27
39
40
detail of lead end
26
c
1
E
HE
L
52
14
1
13
e
(UNIT:mm)
3
b
x
M
A
A2
y
A1
ITEM
D
10.00±0.10
E
10.00±0.10
HD
12.00±0.20
HE
12.00±0.20
A
1.70 MAX.
A1
0.10±0.05
A2
1.40
b
0.32±0.05
c
0.145±0.055
L
0.50±0.15
NOTE1.Dimensions “ 1” and “ 2” do not include mold flash.
2.Dimension “ 3” does not include trim offset.
DIMENSIONS
0° to 8°
e
0.65
x
0.13
y
0.10
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 128 of 131
RL78/L12
4. PACKAGE DRAWINGS
4.5 64-pin Products
R5F10RLAAFA, R5F10RLCAFA
R5F10RLAGFA, R5F10RLCGFA
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LQFP64-12x12-0.65
PLQP0064JA-A
P64GK-65-UET-2
0.51
HD
D
detail of lead end
48
33
49
32
A3
c
L
E
Lp
HE
L1
(UNIT:mm)
17
64
1
16
ZE
e
ZD
b
x
M
S
A2
S
S
NOTE
Each lead centerline is located within 0.13 mm of
its true position at maximum material condition.
DIMENSIONS
12.00±0.20
E
12.00±0.20
HD
14.00±0.20
HE
14.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
A
y
ITEM
D
A1
0.25
b
0.32 +0.08
0.07
c
0.145 +0.055
0.045
L
0.50
Lp
0.60±0.15
L1
1.00±0.20
3° +5°
3°
e
0.65
x
0.13
y
0.10
ZD
1.125
ZE
1.125
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 129 of 131
RL78/L12
4. PACKAGE DRAWINGS
R5F10RLAAFB, R5F10RLCAFB
R5F10RLAGFB, R5F10RLCGFB
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LFQFP64-10x10-0.50
PLQP0064KF-A
P64GB-50-UEU-2
0.35
HD
D
detail of lead end
48
33
49
A3
32
c
L
E
Lp
HE
L1
(UNIT:mm)
17
64
1
16
ZE
e
ZD
b
x
M
S
ITEM
D
DIMENSIONS
10.00±0.20
E
10.00±0.20
HD
12.00±0.20
HE
12.00±0.20
A
1.60 MAX.
A1
0.10±0.05
A2
1.40±0.05
A3
b
A
A2
c
L
S
y
S
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
A1
0.25
0.22±0.05
0.145 +0.055
0.045
0.50
Lp
0.60±0.15
L1
1.00±0.20
3° +5°
3°
e
0.50
x
0.08
y
0.08
ZD
1.25
ZE
1.25
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 130 of 131
RL78/L12
4. PACKAGE DRAWINGS
R5F10RLAANB, R5F10RLCANB
R5F10RLAGNB, R5F10RLCGNB
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-HWQFN64-8x8-0.40
PWQN0064LA-A
P64K8-40-9B5-4
0.16
Unit: mm
D
33
48
DETAIL OF A PART
32
49
E
A
A1
17
64
c2
16
1
INDEX AREA
A
S
y
S
D2
A
Lp
EXPOSED DIE PAD
Reference Dimensions in millimeters
Symbol
Min
Nom
Max
D
7.95
8.00
8.05
E
7.95
8.00
8.05
A
—
—
0.80
A1
0.00
—
—
b
0.17
0.20
0.23
e
—
0.40
—
Lp
0.40
—
0.50
x
0.30
—
y
—
—
ZD
—
1.00
0.05
—
ZE
—
1.00
—
c2
0.20
D2
0.15
—
6.50
0.25
—
E2
—
6.50
—
16
1
64
17
B
E2
ZE
32
49
48
33
ZD
e
b
M
S AB x
0.05
© 2015 Renesas Electronics Corporation. All rights reserved.
R01DS0157EJ0210 Rev.2.10
Sep 30, 2016
Page 131 of 131
Revision History
RL78/L12 Datasheet
Description
Rev.
Date
0.01
0.02
Feb 20, 2012
Sep 26, 2012
1.00
Jan 31, 2013
Page
7, 8
15
11 to 15
16
17
18
19
20
22, 23
30
32
34
36
38, 40 to
42, 44 to
46, 48 to
52, 54, 55
57, 58
62
64
69
2.00
Jan 10, 2014
Summary
First Edition issued
Modification of caution 2 in 1.3.5 64-pin products
Modification of I/O port in 1.6 Outline of Functions
Modification of 2. ELECTRICAL SPECIFICATIONS (TARGET)
Update of package drawings in 3. PACKAGE DRAWINGS
Modification of 1.5 Block Diagram
Modification of Note 2 in 1.6 Outline of Functions
Modification of 1.6 Outline of Functions
Deletion of target in 2. ELECTRICAL SPECIFICATIONS
Addition of caution 2 to 2. ELECTRICAL SPECIFICATIONS
Addition of description, note 3, and remark 2 to 2.1 Absolute Maximum Ratings
Modification of description and addition of note to 2.1 Absolute Maximum
Ratings
Modification of 2.2 Oscillator Characteristics
Modification of notes 1 to 4 in 2.3.2 Supply current characteristics
Modification of notes 1, 3 to 6, 8 in 2.3.2 Supply current characteristics
Modification of notes 7, 9, 11, and addition of notes 8, 12 to 2.3.2 Supply current
characteristics
Addition of description to 2.4 AC Characteristics
Modification of 2.5.1 Serial array unit
Modification of 2.5.2 Serial interface IICA
Modification of 2.6.2 Temperature sensor/internal reference voltage
characteristics
Addition of note and caution in 2.6.5 Supply voltage rise time
Modification of 2.8 Data Memory STOP Mode Low Supply Voltage Data Retention
Characteristics
69
Modification of conditions in 2.9 Timing Specs for Switching Flash Memory
Programming Modes
70
Modification of 2.10 Timing Specifications for Switching Flash Memory
Programming Modes
1
3
4
5 to 10
11
12 to 16
17
20
21
23
23
24
25
30
31, 32
33, 34
Modification of 1.1 Features
Modification of Figure 1-1
Modification of part number, note, and caution
Deletion of COMEXP pin in 1.3.1 to 1.3.5.
Modification of description in 1.4 Pin Identification
Deletion of COMEXP pin in 1.5.1 to 1.5.5
Modification of table and note 2 in 1.6 Outline of Functions
Modification of description in Absolute Maximum Ratings (TA = 25°C) (1/3)
Modification of description and note 2 in Absolute Maximum Ratings (TA = 25°C)
(2/3)
Modification of table, note, caution, and remark in 2.2.1 X1, XT1 oscillator
characteristics
Modification of table in 2.2.2 On-chip oscillator characteristics
Modification of table, notes 2 and 3 in 2.3.1 Pin characteristics (1/5)
Modification of notes 1 and 3 in 2.3.1 Pin characteristics (2/5)
Modification of notes 1 and 4 in 2.3.2 Supply current characteristics (1/3)
Modification of table, notes 1, 5, and 6 in 2.3.2 Supply current characteristics
(2/3)
Modification of table, notes 1, 3, 4, and 5 to 10 in 2.3.2 Supply current
characteristics (3/3)
C-1
Rev.
Date
Page
2.00
Jan 10, 2014
35
36
37
39
39
41, 42
42, 43
45
46, 48
49, 50
51
52
53, 54
56
57
59, 60
61
62
63
63, 64
65
66
67
67
68
70
70
75
76
2.10
Sep 30, 2016
77 to 126
127 to 133
5
6
7
8
9, 10
17
74
74
123
123
131
Description
Summary
Modification of table in 2.4 AC Characteristics
Addition of Minimum Instruction Execution Time during Main System Clock
Operation
Modification of AC Timing Test Points and External System Clock Timing
Modification of AC Timing Test Points
Modification of description, notes 1 and 2 in (1) During communication at same
potential (UART mode)
Modification of description, remark 2 in (2) During communication at same
potential (CSI mode)
Modification of description in (3) During communication at same potential (CSI
mode)
Modification of description, notes 1 and 3, and remark 3 in (4) Communication at
different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2)
Modification of description, and remark 3 in (4) Communication at different
potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2)
Modification of table, and note 1, caution, and remark 3 in (5) Communication at
different potential (2.5 V, 3 V) (CSI mode)
Modification of table and note in (6) Communication at different potential (1.8 V,
2.5 V, 3 V) (1/3)
Modification of table and notes 1 to 3 in (6) Communication at different potential
(1.8 V, 2.5 V, 3 V) (2/3)
Modification of table, note 3, and remark 3 in (6) Communication at different
potential (1.8 V, 2.5 V, 3 V) (3/3)
Modification of table in (7) Communication at different potential (1.8 V, 2.5 V, 3 V)
(CSI mode) (1/2)
Modification of table in (7) Communication at different potential (1.8 V, 2.5 V, 3 V)
(CSI mode) (2/2)
Addition of (1) I2C standard mode
Addition of (2) I2C fast mode
Addition of (3) I2C fast mode plus
Addition of table in 2.6.1 A/D converter characteristics
Modification of description and notes 3 to 5 in 2.6.1 (1)
Modification of description, notes 3 and 4 in 2.6.1 (2)
Modification of description, notes 3 and 4 in 2.6.1 (3)
Modification of description, notes 3 and 4 in 2.6.1 (4)
Modification of the table in 2.6.2 Temperature sensor/internal reference voltage
characteristics
Modification of the table and note in 2.6.3 POR circuit characteristics
Modification of the table of LVD Detection Voltage of Interrupt & Reset Mode
Modification from VDD rise slope to Power supply voltage rising slope in 2.6.5
Supply voltage rise time
Modification of description in 2.10 Dedicated Flash Memory Programmer
Communication (UART)
Modification of the figure in 2.11 Timing Specifications for Switching Flash
Memory Programming Modes
Addition of products for industrial applications (G: TA = -40 to +105°C)
Addition of product names for industrial applications (G: TA = -40 to +105°C)
Modification of pin configuration in 1.3.1 32-pin products
Modification of pin configuration in 1.3.2 44-pin products
Modification of pin configuration in 1.3.3 48-pin products
Modification of pin configuration in 1.3.4 52-pin products
Modification of pin configuration in 1.3.5 64-pin products
Modification of description of main system clock in 1.6 Outline of Functions
Modification of title of 2.8 RAM Data Retention Characteristics, Note, and figure
Modification of table of 2.9 Flash Memory Programming Characteristics
Modification of title of 3.8 RAM Data Retention Characteristics, Note, and figure
Modification of table of 3.9 Flash Memory Programming Characteristics and
addition of Note 4
Modification of 4.5 64-pin Products
C-2
The mark “” shows major revised points. The revised points can be easily searched by copying an “” in the
PDF file and specifying it in the “Find what:” field.
All trademarks and registered trademarks are the property of their respective owners.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United
States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
C-3
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a wrist
strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken
for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the device.
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
2.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
3.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
4.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or
5.
Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on
third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.
the product's quality grade, as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; and industrial robots etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical
implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it
in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses
incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
6.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or systems manufactured by you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
9.
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regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the
development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the
contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics
products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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