Datasheet
RL78/L1C
R01DS0192EJ0220
Rev.2.20
Dec 28, 2017
RENESAS MCU
Integrated LCD controller/driver, 12-bit resolution A/D Converter, USB 2.0 controller (function), True Low Power Platform (as low as 112.5
μA/MHz, and 0.68 μA for RTC2 + LVD), 1.6 V to 3.6 V operation, 64 to 256 Kbyte Flash, 33 DMIPS at 24 MHz, for All LCD Based Applications
1. OUTLINE
1.1
Features
Ultra-low power consumption technology
• VDD = single power supply voltage of 1.6 to 3.6 V
• HALT mode
• STOP mode
• SNOOZE mode
RL78 CPU core
• CISC architecture with 3-stage pipeline
• Minimum instruction execution time: Can be changed from high
speed (0.04167 μs: @ 24 MHz operation with high-speed on-chip
oscillator clock or PLL clock) to ultra-low speed (30.5 μs: @ 32.768
kHz operation with subsystem clock)
• Multiply/divide and multiply/accumulate instructions are supported.
• Address space: 1 Mbyte
• General-purpose registers: (8-bit register × 8) × 4 banks
• On-chip RAM: 8 to 16 KB
Code flash memory
• Code flash memory: 64 to 256 KB
• Block size: 1 KB
• Prohibition of block erase and rewriting (security function)
• On-chip debug function
• Self-programming (with boot swap function/flash shield window
function)
Data flash memory
• Data flash memory: 8 KB
• Background operation (BGO): Instructions can be executed from the
program memory while rewriting the data flash memory.
• Number of rewrites: 1,000,000 times (TYP.)
• Voltage of rewrites: VDD = 1.8 to 3.6 V
High-speed on-chip oscillator
• Select from 48 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4
MHz, 3 MHz, 2 MHz, and 1 MHz
• High accuracy: ±1.0% (VDD = 1.8 to 3.6 V, TA = -20 to +85°C)
Operating ambient temperature
• TA = -40 to +85°C (A: Consumer applications)
• TA = -40 to +105°C (G: Industrial applications)
Power management and reset function
• On-chip power-on-reset (POR) circuit
• On-chip voltage detector (LVD) (Select interrupt and reset from 12
levels)
Data transfer controller (DTC)
• Transfer modes: Normal transfer mode, repeat transfer mode, block
transfer mode
• Activation sources: Activated by interrupt sources (30 to 33 sources).
• Chain transfer function
Event link controller (ELC)
• Event signals of 30 or 31 types can be linked to the specified
peripheral function.
Timers
• 16-bit timer: 11 channels
• 12-bit interval timer: 1 channel
• Real-time clock 2: 1 channel (calendar for 99 years, alarm function,
and clock correction function)
• Watchdog timer: 1 channel (operable with the dedicated low-speed
on-chip oscillator)
LCD controller/driver
• Internal voltage boosting method, capacitor split method, and
external resistance division method are switchable.
• Segment signal output: 44 (40) Note 1 to 56 (52) Note 1
• Common signal output: 4 (8) Note 1
USB Note 2
• USB version 2.0 (function controller)
• Full-speed transfer (12 Mbps) and low-speed transfer (1.5 Mbps) are
supported
• Compliant to Battery Charging Specification Revision 1.2
A/D converter
• 8/10-bit resolution A/D converter (VDD = 1.6 to 3.6 V)
• 12-bit resolution A/D converter (VDD = 2.4 to 3.6 V)
• Analog input: 9 to 13 channels
• Internal reference voltage (TYP. 1.45 V) and temperature sensor Note 2
D/A converter
• 8-bit resolution D/A converter (VDD = 1.6 to 3.6 V)
• Analog output: 2 channels
• Output voltage: 0 V to VDD
• Real-time output function
Comparator
• 2 channels
• Operating modes: Comparator high-speed mode, comparator lowspeed mode, window mode
• The external reference voltage or internal reference voltage can be
selected as the reference voltage.
I/O ports
• I/O ports: 59 to 77 (N-ch open drain I/O [withstand voltage of 6 V]: 2)
• Can be set to N-ch open drain, TTL input buffer, and on-chip pull-up
resistor
• On-chip key interrupt function
• On-chip clock output/buzzer output controller
Others
• On-chip BCD (binary-coded decimal) correction circuit
Note 1.
Note 2.
Remark
The number in parentheses indicates the number of
signal outputs when 8 coms are used.
Selectable only in HS (high-speed main) mode.
The functions mounted depend on the product. See
1.6 Outline of Functions.
Serial interfaces
• CSI: 4 channels
• UART/UART (LIN-bus supported): 4 channels
• I2C/simplified I2C: 5 channels
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 1 of 147
RL78/L1C
1. OUTLINE
ROM, RAM capacities
Products with USB
Flash ROM
Data Flash
RAM
256 KB
8 KB
192 KB
RL78/L1C
80 pins
85 pins
100 pins
16 KB Note
R5F110MJ
R5F110NJ
R5F110PJ
8 KB
16 KB Note
R5F110MH
R5F110NH
R5F110PH
128 KB
8 KB
12 KB
R5F110MG
R5F110NG
R5F110PG
96 KB
8 KB
10 KB
R5F110MF
R5F110NF
R5F110PF
64 KB
8 KB
8 KB
R5F110ME
R5F110NE
R5F110PE
Flash ROM
Data Flash
RAM
256 KB
8 KB
192 KB
Products without USB
Note
RL78/L1C
80 pins
85 pins
100 pins
16 KB Note
R5F111MJ
R5F111NJ
R5F111PJ
8 KB
16 KB Note
R5F111MH
R5F111NH
R5F111PH
128 KB
8 KB
12 KB
R5F111MG
R5F111NG
R5F111PG
96 KB
8 KB
10 KB
R5F111MF
R5F111NF
R5F111PF
64 KB
8 KB
8 KB
R5F111ME
R5F111NE
R5F111PE
This is about 15 KB when the self-programming function and data flash function are used (For details, see CHAPTER 3
in the RL78/L1C User’s Manual).
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 2 of 147
RL78/L1C
1.2
1. OUTLINE
Ordering Information
Products with USB
Pin
Count
80 pins
Package
80-pin plastic
Fields of
Application
A
LFQFP
(12 × 12 mm,
0.5 mm pitch)
85 pins
85-pin plastic
0.65 mm pitch)
100 pins
100-pin plastic
G
0.5 mm pitch)
R5F110MEGFB#30, R5F110MFGFB#30, R5F110MGGFB#30, R5F110MHGFB#30, R5F110MJGFB#30
R5F110MEGFB#50, R5F110MFGFB#50, R5F110MGGFB#50, R5F110MHGFB#50, R5F110MJGFB#50
A
R5F110NEALA#U0, R5F110NFALA#U0, R5F110NGALA#U0, R5F110NHALA#U0, R5F110NJALA#U0
R5F110NEALA#W0, R5F110NFALA#W0, R5F110NGALA#W0, R5F110NHALA#W0, R5F110NJALA#W0
G
R5F110NEGLA#U0, R5F110NFGLA#U0, R5F110NGGLA#U0, R5F110NHGLA#U0, R5F110NJGLA#U0
R5F110NEGLA#W0, R5F110NFGLA#W0, R5F110NGGLA#W0, R5F110NHGLA#W0, R5F110NJGLA#W0
A
LFQFP
(14 × 14 mm,
R5F110MEAFB#30, R5F110MFAFB#30, R5F110MGAFB#30, R5F110MHAFB#30, R5F110MJAFB#30
R5F110MEAFB#50, R5F110MFAFB#50, R5F110MGAFB#50, R5F110MHAFB#50, R5F110MJAFB#50
VFLGA
(7 × 7 mm,
Orderable Part Number
R5F110PEAFB#30, R5F110PFAFB#30, R5F110PGAFB#30, R5F110PHAFB#30, R5F110PJAFB#30
R5F110PEAFB#50, R5F110PFAFB#50, R5F110PGAFB#50, R5F110PHAFB#50, R5F110PJAFB#50
G
R5F110PEGFB#30, R5F110PFGFB#30, R5F110PGGFB#30, R5F110PHGFB#30, R5F110PJGFB#30
R5F110PEGFB#50, R5F110PFGFB#50, R5F110PGGFB#50, R5F110PHGFB#50, R5F110PJGFB#50
Products without USB
Pin
Count
80 pins
Package
80-pin plastic
Fields of
Application
A
LFQFP
(12 × 12 mm,
0.5 mm pitch)
85 pins
85-pin plastic
0.65 mm pitch)
100 pins
100-pin plastic
G
0.5 mm pitch)
R5F111MEGFB#30, R5F111MFGFB#30, R5F111MGGFB#30, R5F111MHGFB#30, R5F111MJGFB#30
R5F111MEGFB#50, R5F111MFGFB#50, R5F111MGGFB#50, R5F111MHGFB#50, R5F111MJGFB#50
A
R5F111NEALA#U0, R5F111NFALA#U0, R5F111NGALA#U0, R5F111NHALA#U0, R5F111NJALA#U0
R5F111NEALA#W0, R5F111NFALA#W0, R5F111NGALA#W0, R5F111NHALA#W0, R5F111NJALA#W0
G
R5F111NEGLA#U0, R5F111NFGLA#U0, R5F111NGGLA#U0, R5F111NHGLA#U0, R5F111NJGLA#U0
R5F111NEGLA#W0, R5F111NFGLA#W0, R5F111NGGLA#W0, R5F111NHGLA#W0, R5F111NJGLA#W0
A
LFQFP
(14 × 14 mm,
R5F111MEAFB#30, R5F111MFAFB#30, R5F111MGAFB#30, R5F111MHAFB#30, R5F111MJAFB#30
R5F111MEAFB#50, R5F111MFAFB#50, R5F111MGAFB#50, R5F111MHAFB#50, R5F111MJAFB#50
VFLGA
(7 × 7 mm,
Orderable Part Number
R5F111PEAFB#30, R5F111PFAFB#30, R5F111PGAFB#30, R5F111PHAFB#30, R5F111PJAFB#30
R5F111PEAFB#50, R5F111PFAFB#50, R5F111PGAFB#50, R5F111PHAFB#50, R5F111PJAFB#50
G
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
R5F111PEGFB#30, R5F111PFGFB#30, R5F111PGGFB#30, R5F111PHGFB#30, R5F111PJGFB#30
R5F111PEGFB#50, R5F111PFGFB#50, R5F111PGGFB#50, R5F111PHGFB#50, R5F111PJGFB#50
Page 3 of 147
RL78/L1C
1. OUTLINE
Figure 1 - 1 Part Number, Memory Size, and Package of RL78/L1C
Part No. R 5 F 1 1 0 P E A x x x F B # 3 0
Packaging specification:
#30: Tray (LFQFP)
#U0: Tray (VFLGA)
#50: Embossed Tape (LFQFP)
#W0: Embossed Tape (VFLGA)
Package type:
FB: LFQFP, 0.50 mm pitch
LA: VFLGA, 0.65 mm pitch
ROM number (Omitted with blank products)
Fields of application:
A: Consumer applications, TA = -40 to +85°C
G: Industrial applications, TA = -40 to +105°C
ROM capacity:
E: 64 KB
F: 96 KB
G: 128 KB
H: 192 KB
J: 256 KB
Pin count:
M: 80-pin
N: 85-pin
P: 100-pin
RL78/L1C Group
110: Products with USB
111: Products without USB
Memory type:
F: Flash memory
Renesas MCU
Renesas semiconductor product
Caution
Orderable part numbers are current as of when this manual was published.
Please make sure to refer to the relevant product page on the Renesas website for the latest part numbers.
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 4 of 147
RL78/L1C
1.3
1. OUTLINE
Pin Configuration (Top View)
1.3.1
80-pin products (with USB)
COM4/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P50/SEG4/INTP6
P51/SEG5
P52/SEG6
P07/TI06/TO06/SEG55
COM0
COM1
COM2
COM3
P12/TxD2/SO20/SEG42
P00/SCK10/SCL10/SEG48
P01/SI10/RxD1/SDA10/SEG49
P02/SO10/TxD1/(PCLBUZ0)/SEG50
P03/TI00/TO00/INTP1/SEG51
P04/INTP2/SEG52
P05/TI02/TO02/SEG53
P06/INTP5/SEG54
• 80-pin plastic LFQFP (12 × 12 mm, 0.5 mm pitch)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P11/RxD2/SI20/SDA20/SEG41/VCOUT0
P10/INTP7/PCLBUZ0/SCK20/SCL20/SEG40
P27/TI05/TO05/(INTP5)/PCLBUZ1/SEG39
P26/SO00/TxD0/TOOLTxD/SEG38
P25/SI00/RxD0/TOOLRxD/SDA00/SEG37
P24/SCK00/SCL00/SEG36
P23/TI07/TO07/SEG35
P22/TI04/TO04/SEG34
P21/ANI21/SEG33
P20/ANI20/SEG32
P143/ANI19/SEG31
P142/ANI18/SEG30
P141/ANI17/SEG29
P140/ANI16/SEG28
UREGC
UVBUS
UDM
UDP
AVDD
AVSS
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
RL78/L1C
(Top View)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P70/KR7/SEG12
P71/KR6/SEG13
P72/KR5/TKBO20/SEG14
P73/KR4/TKBO21/SEG15
P74/KR3/TKBO10/SEG16
P75/KR2/TKBO11/SEG17
P76/KR1/TKBO00/SEG18
P77/KR0/TKBO01/SEG19
P30/TI03/TO03/REMOOUT/SEG20
P31/INTP3/RTC1HZ/SEG21
P32/TI01/TO01/SEG22
P33/INTP4/SCK30/SCL30/SEG23
P34/SI30/RxD3/SDA30/SEG24
P35/SO30/TxD3/SEG25
P125/VL3/(TI06)/(TO06)
VL4
VL2
VL1
P126/CAPL/(TI04)/(TO04)
P127/CAPH/(TI03)/(TO03)/(REMOOUT)
P152/ANI2
P151/ANI1/AVREFM
P150/ANI0/AVREFP
P130
P46/ANO1
P45/ANO0
P44/IVREF0
P43/(INTP7)/IVCMP0
P40/TOOL0/(TI00)/(TO00)
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS0
VDD0
P60/SCLA0/(TI01)/(TO01)
P61/SDAA0/(TI02)/(TO02)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Caution 1. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 μF).
Caution 2. Connect the UREGC pin to VSS pin via a capacitor (0.33 μF).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register
(PIOR).
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 5 of 147
RL78/L1C
1.3.2
1. OUTLINE
80-pin products (without USB)
COM4/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P50/SEG4/INTP6
P51/SEG5
P52/SEG6
P07/TI06/TO06/SEG55
COM0
COM1
COM2
COM3
P12/TxD2/SO20/SEG42
P00/SCK10/SCL10/SEG48
P01/SI10/RxD1/SDA10/SEG49
P02/SO10/TxD1/(PCLBUZ0)/SEG50
P03/TI00/TO00/INTP1/SEG51
P04/INTP2/SEG52
P05/TI02/TO02/SEG53
P06/INTP5/SEG54
• 80-pin plastic LFQFP (fine pitch) (12 × 12 mm, 0.5 mm pitch)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P11/RxD2/SI20/SDA20/SEG41/VCOUT0
P10/INTP7/PCLBUZ0/SCK20/SCL20/SEG40
P27/TI05/TO05/(INTP5)/PCLBUZ1/SEG39
P26/SO00/TxD0/TOOLTxD/SEG38
P25/SI00/RxD0/TOOLRxD/SDA00/SEG37
P24/SCK00/SCL00/SEG36
P23/TI07/TO07/SEG35
P22/TI04/TO04/SEG34
P21/ANI21/SEG33
P20/ANI20/SEG32
P143/ANI19/SEG31
P142/ANI18/SEG30
P141/ANI17/SEG29
P140/ANI16/SEG28
P82
P83
P156/ANI6
P155/ANI5
AVDD
AVSS
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
RL78/L1C
(Top View)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P70/KR7/SEG12
P71/KR6/SEG13
P72/KR5/TKBO20/SEG14
P73/KR4/TKBO21/SEG15
P74/KR3/TKBO10/SEG16
P75/KR2/TKBO11/SEG17
P76/KR1/TKBO00/SEG18
P77/KR0/TKBO01/SEG19
P30/TI03/TO03/REMOOUT/SEG20
P31/INTP3/RTC1HZ/SEG21
P32/TI01/TO01/SEG22
P33/INTP4/SCK30/SCL30/SEG23
P34/SI30/RxD3/SDA30/SEG24
P35/SO30/TxD3/SEG25
P125/VL3/(TI06)/(TO06)
VL4
VL2
VL1
P126/CAPL/(TI04)/(TO04)
P127/CAPH/(TI03)/(TO03)/(REMOOUT)
P152/ANI2
P151/ANI1/AVREFM
P150/ANI0/AVREFP
P130
P46/ANO1
P45/ANO0
P44/IVREF0
P43/(INTP7)/IVCMP0
P40/TOOL0/(TI00)/(TO00)
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS0
VDD0
P60/SCLA0/(TI01)/(TO01)
P61/SDAA0/(TI02)/(TO02)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Caution
Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 μF).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register
(PIOR).
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 6 of 147
RL78/L1C
1.3.3
Pin
1. OUTLINE
85-pin products (with USB)
Name
A10
B10
C10
D10
E10
F10
G10
H10
J10
K10
A9
B9
C9
D9
E9
F9
G9
H9
J9
K9
A8
B8
C8
D8
E8
F8
G8
H8
J8
K8
A7
B7
C7
H7
J7
K7
A6
B6
C6
H6
J6
K6
A5
B5
C5
H5
J5
K5
A4
B4
C4
D4
H4
J4
K4
A3
B3
C3
D3
E3
F3
G3
H3
J3
K3
A2
B2
C2
D2
E2
F2
G2
H2
J2
K2
A1
B1
C1
D1
E1
F1
G1
H1
J1
K1
Pin
Name
Pin
Name
Pin
Name
Pin
Name
A1
COM7/SEG3
C1
COM2
E1
P04/INTP2/SEG52
G1
P00/SCK10/SCL10/
SEG48
J1
VSS0
A2
P51/SEG5
C2
COM5/SEG1
E2
P05/TI02/TO02/SEG53
G2
VSS0
J2
P11/RxD2/SI20/SDA20/
SEG41/VCOUT0
A3
P70/KR7/SEG12
C3
COM6/SEG2
E3
P06/INTP5/SEG54
G3
P12/TxD2/SO20/SEG42/
VCOUT1
J3
P26/SO00/TxD0/
TOOLTxD/SEG38
A4
P73/KR4/TKBO21/SEG15
C4
P71/KR6/SEG13
E4
—
G4
—
J4
P23/TI07/TO07/SEG35
A5
P74/KR3/TKBO10/SEG16
C5
P76/KR1/TKBO00/SEG18
E5
—
G5
—
J5
P20/ANI20/SEG32
A6
P31/INTP3/RTC1HZ/
SEG21
C6
P77/KR0/TKBO01/SEG19
E6
—
G6
—
J6
P141/ANI17/SEG29
A7
P33/INTP4/SCK30/SCL30/
SEG23
C7
P34/SI30/RxD3/SDA30/
SEG24
E7
—
G7
—
J7
UREGC
A8
P35/SO30/TxD3/SEG25
C8
VL1
E8
P40/TOOL0/(TI00)/(TO00)
G8
J8
UVBUS
AVDD
P44/(SCK10)/(SCL10)/
IVREF0
A9
VL4
C9
P61/SDAA0/(TI02)/(TO02)
E9
P137/INTP0
G9
P45/ANO0
J9
A10
P126/CAPL/(TI04)/(TO04)
C10
VDD0
E10
P122/X2/EXCLK
G10
P123/XT1
J10
P150/ANI0/AVREFP
B1
COM4/SEG0
D1
COM0
F1
P03/TI00/TO00/INTP1/
SEG51
H1
VSS0
K1
VSS0
B2
P50/SEG4/INTP6
D2
COM1
F2
P02/SO10/TxD1/
(PCLBUZ0)/SEG50
H2
VSS0
K2
P27/TI05/TO05/(INTP5)/
PCLBUZ1/SEG39
B3
P52/SEG6
D3
P07/TI06/TO06/SEG55
F3
P01/SI10/RxD1/SDA10/
SEG49
H3
P10/INTP7/PCLBUZ0/
SCK20/SCL20/SEG40
K3
P25/SI00/RxD0/
TOOLRxD/SDA00/SEG37
B4
P72/KR5/TKBO20/SEG14
D4
COM3
F4
—
H4
P24/SCK00/SCL00/
SEG36
K4
P22/TI04/TO04/SEG34
B5
P75/KR2/TKBO11/SEG17
D5
—
F5
—
H5
P21/ANI21/SEG33
K5
P143/ANI19/SEG31
B6
P30/TI03/TO03/
REMOOUT/SEG20
D6
—
F6
—
H6
P140/ANI16/SEG28
K6
P142/ANI18/SEG30
B7
P32/TI01/TO01/SEG22
D7
—
F7
—
H7
P152/ANI2
K7
UDM
B8
P125/VL3/(TI06)/(TO06)
D8
P60/SCLA0/(TI01)/(TO01)
F8
P43/(INTP7)/(SI10)/
(RxD1)/(SDA10)/IVCMP0
H8
P46/ANO1
K8
UDP
P130
K9
AVSS
K10
P151/ANI1/AVREFM
B9
VL2
D9
REGC
F9
RESET
H9
B10
P127/CAPH/(TI03)/
(TO03)/(REMOOUT)
D10
P121/X1
F10
VSS0
H10 P124/XT2/EXCLKS
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 7 of 147
RL78/L1C
1.3.4
Pin
1. OUTLINE
85-pin products (without USB)
Name
A10
B10
C10
D10
E10
F10
G10
H10
J10
K10
A9
B9
C9
D9
E9
F9
G9
H9
J9
K9
A8
B8
C8
D8
E8
F8
G8
H8
J8
K8
A7
B7
C7
H7
J7
K7
A6
B6
C6
H6
J6
K6
A5
B5
C5
H5
J5
K5
A4
B4
C4
D4
H4
J4
K4
A3
B3
C3
D3
E3
F3
G3
H3
J3
K3
A2
B2
C2
D2
E2
F2
G2
H2
J2
K2
A1
B1
C1
D1
E1
F1
G1
H1
J1
K1
Pin
Name
Pin
Name
Pin
Name
Pin
Name
A1
COM7/SEG3
C1
COM2
E1
P04/INTP2/SEG52
G1
P00/SCK10/SCL10/
SEG48
J1
VSS0
A2
P51/SEG5
C2
COM5/SEG1
E2
P05/TI02/TO02/SEG53
G2
VSS0
J2
P11/RxD2/SI20/SDA20/
SEG41/VCOUT0
A3
P70/KR7/SEG12
C3
COM6/SEG2
E3
P06/INTP5/SEG54
G3
P12/TxD2/SO20/SEG42/
VCOUT1
J3
P26/SO00/TxD0/
TOOLTxD/SEG38
A4
P73/KR4/TKBO21/SEG15
C4
P71/KR6/SEG13
E4
—
G4
—
J4
P23/TI07/TO07/SEG35
A5
P74/KR3/TKBO10/SEG16
C5
P76/KR1/TKBO00/SEG18
E5
—
G5
—
J5
P20/ANI20/SEG32
A6
P31/INTP3/RTC1HZ/
SEG21
C6
P77/KR0/TKBO01/
SEG19
E6
—
G6
—
J6
P141/ANI17/SEG29
A7
P33/INTP4/SCK30/
SCL30/SEG23
C7
P34/SI30/RxD3/SDA30/
SEG24
E7
—
G7
—
J7
P82
A8
P35/SO30/TxD3/SEG25
C8
VL1
E8
P40/TOOL0/(TI00)/(TO00)
G8
J8
P83
AVDD
P44/(SCK10)/(SCL10)/
IVREF0
A9
VL4
C9
P61/SDAA0/(TI02)/(TO02)
E9
P137/INTP0
G9
P45/ANO0
J9
A10
P126/CAPL/(TI04)/(TO04)
C10
VDD0
E10
P122/X2/EXCLK
G10
P123/XT1
J10
P150/ANI0/AVREFP
B1
COM4/SEG0
D1
COM0
F1
P03/TI00/TO00/INTP1/
SEG51
H1
VSS0
K1
VSS0
B2
P50/SEG4/INTP6
D2
COM1
F2
P02/SO10/TxD1/
(PCLBUZ0)/SEG50
H2
VSS0
K2
P27/TI05/TO05/(INTP5)/
PCLBUZ1/SEG39
B3
P52/SEG6
D3
P07/TI06/TO06/SEG55
F3
P01/SI10/RxD1/SDA10/
SEG49
H3
P10/INTP7/PCLBUZ0/
SCK20/SCL20/SEG40
K3
P25/SI00/RxD0/
TOOLRxD/SDA00/SEG37
B4
P72/KR5/TKBO20/SEG14
D4
COM3
F4
—
H4
P24/SCK00/SCL00/
SEG36
K4
P22/TI04/TO04/SEG34
B5
P75/KR2/TKBO11/SEG17
D5
—
F5
—
H5
P21/ANI21/SEG33
K5
P143/ANI19/SEG31
B6
P30/TI03/TO03/
REMOOUT/SEG20
D6
—
F6
—
H6
P140/ANI16/SEG28
K6
P142/ANI18/SEG30
B7
P32/TI01/TO01/SEG22
D7
—
F7
B8
P125/VL3/(TI06)/(TO06)
D8
P60/SCLA0/(TI01)/(TO01)
F8
—
P43/(INTP7)/(SI10)/
H7
P152/ANI2
K7
P156/ANI6
H8
P46/ANO1
K8
P155/ANI5
P130
K9
AVSS
K10
P151/ANI1/AVREFM
(RxD1)/(SDA10)/IVCMP0
B9
VL2
D9
REGC
F9
RESET
H9
B10
P127/CAPH/(TI03)/
(TO03)/(REMOOUT)
D10
P121/X1
F10
VSS0
H10 P124/XT2/EXCLKS
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 8 of 147
RL78/L1C
1.3.5
1. OUTLINE
100-pin products (with USB)
P51/SEG5
P52/SEG6
P12/TxD2/SO20/SEG42/VCOUT1
P13/SEG43
P14/SEG44
P15/SEG45
P16/SEG46
P17/SEG47
P00/SCK10/SCL10/SEG48
P01/SI10/RxD1/SDA10/SEG49
P02/SO10/TxD1/(PCLBUZ0)/SEG50
P03/TI00/TO00/INTP1/SEG51
P04/INTP2/SEG52
P05/TI02/TO02/SEG53
P06/INTP5/SEG54
P07/TI06/TO06/SEG55
COM0
COM1
COM2
COM3
COM4/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P50/SEG4/INTP6
• 100-pin plastic LFQFP (fine pitch) (14 × 14 mm, 0.5 mm pitch)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
RL78/L1C
(Top View)
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P53/SEG7
P54/SEG8
P55/SEG9
P56/SEG10
P57/SEG11
P70/KR7/SEG12
P71/KR6/SEG13
P72/KR5/TKBO20/SEG14
P73/KR4/TKBO21/SEG15
P74/KR3/TKBO10/SEG16
P75/KR2/TKBO11/SEG17
P76/KR1/TKBO00/SEG18
P30/TI03/TO03/REMOOUT/SEG20
P31/INTP3/RTC1HZ/SEG21
P32/TI01/TO01/SEG22
P33/INTP4/SCK30/SCL30/SEG23
P34/SI30/RxD3/SDA30/SEG24
P35/SO30/TxD3/SEG25
P36/SEG26
P37/SEG27
P125/VL3/(TI06)/(TO06)
VL4
VL2
VL1
P153/ANI3
P152/ANI2
P151/ANI1/AVREFM
P150/ANI0/AVREFP
P130
P46/ANO1
P45/ANO0
P44/(SCK10)/(SCL10)/IVREF0
P43/(INTP7)/(SI10)/(RxD1)/(SDA10)/IVCMP0
P42/TI05/TO05/(SO10)/(TxD1)/IVCMP1
P41/(TI07)/(TO07)/IVREF1
P40/TOOL0/(TI00)/(TO00)
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS0
VDD0
P60/SCLA0/(TI01)/(TO01)
P61/SDAA0/(TI02)/(TO02)
P127/CAPH/(TI03)/(TO03)/(REMOOUT)
P126/CAPL/(TI04)/(TO04)
P11/RxD2/SI20/SDA20/SEG41/VCOUT0
P10/INTP7/PCLBUZ0/SCK20/SCL20/SEG40
P27/(TI05)/(TO05)/(INTP5)/PCLBUZ1/SEG39
P26/SO00/TxD0/TOOLTxD/SEG38
P25/SI00/RxD0/TOOLRxD/SDA00/SEG37
P24/SCK00/SCL00/SEG36
P23/TI07/TO07/SEG35
P22/TI04/TO04/SEG34
P21/ANI21/SEG33
P20/ANI20/SEG32
P143/ANI19/SEG31
P142/ANI18/SEG30
P141/ANI17/SEG29
P140/ANI16/SEG28
VDD1
VSS1
UREGC
UVBUS
UDM
UDP
P156/ANI6
P155/ANI5
AVDD
AVSS
P154/ANI4
Caution 1. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 μF).
Caution 2. Connect the UREGC pin to VSS pin via a capacitor (0.33 μF).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register
(PIOR).
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 9 of 147
RL78/L1C
1.3.6
1. OUTLINE
100-pin products (without USB)
P51/SEG5
P52/SEG6
P12/TxD2/SO20/SEG42/VCOUT1
P13/SEG43
P14/SEG44
P15/SEG45
P16/SEG46
P17/SEG47
P00/SCK10/SCL10/SEG48
P01/SI10/RxD1/SDA10/SEG49
P02/SO10/TxD1/(PCLBUZ0)/SEG50
P03/TI00/TO00/INTP1/SEG51
P04/INTP2/SEG52
P05/TI02/TO02/SEG53
P06/INTP5/SEG54
P07/TI06/TO06/SEG55
COM0
COM1
COM2
COM3
COM4/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
P50/SEG4/INTP6
• 100-pin plastic LFQFP (fine pitch) (14 × 14 mm, 0.5 mm pitch)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
RL78/L1C
(Top View)
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P53/SEG7
P54/SEG8
P55/SEG9
P56/SEG10
P57/SEG11
P70/KR7/SEG12
P71/KR6/SEG13
P72/KR5/TKBO20/SEG14
P73/KR4/TKBO21/SEG15
P74/KR3/TKBO10/SEG16
P75/KR2/TKBO11/SEG17
P76/KR1/TKBO00/SEG18
P77/KR0/TKBO01/SEG19
P30/TI03/TO03/REMOOUT/SEG20
P31/INTP3/RTC1HZ/SEG21
P32/TI01/TO01/SEG22
P33/INTP4/SCK30/SCL30/SEG23
P34/SI30/RxD3/SDA30/SEG24
P35/SO30/TxD3/SEG25
P36/SEG26
P37/SEG27
P125/VL3/(TI06)/(TO06)
VL4
VL2
VL1
P153/ANI3
P152/ANI2
P151/ANI1/AVREFM
P150/ANI0/AVREFP
P130
P46/ANO1
P45/ANO0
P44/(SCK10)/(SCL10)/IVREF0
P43/(INTP7)/(SI10)/(RxD1)/(SDA10)/IVCMP0
P42/TI05/TO05/(SO10)/(TxD1)/IVCMP1
P41/(TI07)/(TO07)/IVREF1
P40/TOOL0/(TI00)/(TO00)
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS0
VDD0
P60/SCLA0/(TI01)/(TO01)
P61/SDAA0/(TI02)/(TO02)
P127/CAPH/(TI03)/(TO03)/(REMOOUT)
P126/CAPL/(TI04)/(TO04)
P11/RxD2/SI20/SDA20/SEG41/VCOUT0
P10/INTP7/PCLBUZ0/SCK20/SCL20/SEG40
P27/(TI05)/(TO05)/(INTP5)/PCLBUZ1/SEG39
P26/SO00/TxD0/TOOLTxD/SEG38
P25/SI00/RxD0/TOOLRxD/SDA00/SEG37
P24/SCK00/SCL00/SEG36
P23/TI07/TO07/SEG35
P22/TI04/TO04/SEG34
P21/ANI21/SEG33
P20/ANI20/SEG32
P143/ANI19/SEG31
P142/ANI18/SEG30
P141/ANI17/SEG29
P140/ANI16/SEG28
VDD1
VSS1
P80
P81
P82
P83
P156/ANI6
P155/ANI5
AVDD
AVSS
P154/ANI4
Caution
Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 μF).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register
(PIOR).
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 10 of 147
RL78/L1C
1.4
1. OUTLINE
Pin Identification
ANI0 to ANI6,
: Analog Input
ANI16 to ANI21
SCL00, SCL10, SCL20, SCL30 : Serial Clock Output
SDAA0, SDA00, SDA10,
: Serial Data Input/Output
ANO0, ANO1
: Analog Output
SDA20, SDA30
AVDD
: Analog Power Supply
SEG0 to SEG55
: LCD Segment Output
AVREFM
: Analog Reference Voltage
SI00, SI10, SI20, SI30
: Serial Data Input
SO00, SO10, SO20, SO30
: Serial Data Output
TI00 to TI07
: Timer Input
TO00 to TO07
: Timer Output
Minus
AVREFP
: Analog Reference Voltage
Plus
AVSS
: Analog Ground
TKBO00, TKBO01, TKBO10,
CAPH, CAPL
: Capacitor for LCD
TKBO11, TKBO20, TKBO21
COM0 to COM7
: LCD Common Output
TOOL0
: Data Input/Output for Tool
EXCLK
: External Clock Input
TOOLRxD, TOOLTxD
: Data Input/Output for
(Main System Clock)
EXCLKS
: External Clock Input
INTP0 to INTP7
: External Interrupt Input
IVCMP0, IVCMP1
External Device
UDM, UDP
: USB Input/Output
UREGC
: USB Regulator Capacitance
UVBUS
: USB Input/USB Power Supply
: Comparator Input
TxD0 to TxD3
: Transmit Data
IVREF0, IVREF1
: Comparator Reference Input
VCOUT0, VCOUT1
: Comparator Output
KR0 to KR7
: Key Return
VDD0, VDD1
: Power Supply
P00 to P07
: Port 0
VL1 to VL4
: LCD Power Supply
P10 to P17
: Port 1
VSS0, VSS1
: Ground
P20 to P27
: Port 2
X1, X2
: Crystal Oscillator
XT1, XT2
: Crystal Oscillator
(Subsystem Clock)
P30 to P37
: Port 3
P40 to P46
: Port 4
P50 to P57
: Port 5
P60 to P62
: Port 6
P70 to P77
: Port 7
P80 to P83
: Port 8
P121 to P127
: Port 12
P130, P137
: Port 13
P140 to P143
: Port 14
P150 to P156
: Port 15
PCLBUZ0, PCLBUZ1
: Programmable Clock Output/
Buzzer Output
REGC
: Regulator Capacitance
REMOOUT
: Remote Control Output
RESET
: Reset
RTC1HZ
: Real-time Clock Correction
Clock (1 Hz) Output
RxD0 to RxD3
: Receive Data
SCK00, SCK10,
SCK20, SCK30
: Serial Clock Input/Output
SCLA0
: Serial Clock Input/Output
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
(Main System Clock)
(Subsystem Clock)
Page 11 of 147
RL78/L1C
1.5
1.5.1
1. OUTLINE
Block Diagram
80/85-pin products (with USB)
TIMER ARRAY
UNIT0 (8 ch)
TI00/TO00
ch 0
TI01/TO01
ch 1
TI02/TO02
ch 2
TI03/TO03
ch 3
TI04/TO04
ch 4
TI05/TO05
ch 5
TI06/TO06
ch 6
TI07/TO07
ch 7
ANI2
A/D CONVERTER
REMOOUT
REMOTE CARRIER
TKBO00
TKBO01
TIMER KB2_0
TKBO10
TKBO11
TIMER KB2_1
TKBO20
TKBO21
TIMER KB2_2
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
ANI16 to ANI21
AVREFM/ANI1
RL78 CPU CORE
CODE FLASH MEMORY
MULTIPLIER &
DIVIDER,
MULITIPLYACCUMULATOR
PORT 2
8
P20 to P27
PORT 3
6
P30 to P35
PORT 4
5
P40, P43 to P46
PORT 5
3
P50 to P52
PORT 6
2
P60, P61
PORT 7
8
P70 to P77
3
P125 to P127
4
P121 to P124
PORT 12
4
P140 to P143
PORT 15
3
P150 to P152
KEY RETURN
8
KR0 to KR7
AVDD, AVSS, TOOLRxD,
VDD0
VSS0 TOOLTxD
SYSTEM
CONTROL
SDAA0
SERIAL
INTERFACE IICA0
SERIAL ARRAY
UNIT1 (4 ch)
RxD2
TxD2
UART2
RxD3
TxD3
UART3
TOOL0
RESET
X1
X2/EXCLK
HIGH-SPEED
ON-CHIP
OSCILLATOR
XT1
XT2/EXCLKS
SCLA0
PLL
BUZZER OUTPUT
IIC10
POR/LVD
CONTROL
RESET CONTROL
UART0
IIC00
P130
P137
PORT 14
ON-CHIP DEBUG
CSI10
SCK20
SI20
SO20
SCK30
SI30
SO30
SCL20
SDA20
P10 to P12
POWER ON RESET/
VOLTAGE
DETECTOR
CSI00
SCL10
SDA10
3
SERIAL ARRAY
UNIT0 (4 ch)
UART1
SCK10
SI10
SO10
SCL00
SDA00
PORT 1
PORT 13
LINSEL
RxD1
TxD1
SCK00
SI00
SO00
P00 to P07
DATA FLASH MEMORY
RAM
REAL-TIME
CLOCK
RxD0
TxD0
8
AVREFP/ANI0
12- BIT INTERVAL
TIMER
RTC1HZ
CLOCK OUTPUT
CONTROL
2
PCLBUZ0,
PCLBUZ1
VOLTAGE
REGULATOR
INTERRUPT
CONTROL
DATA TRANSFER
CONTROL
D/A CONVERTER
EVENT LINK
CONTROLLER
REGC
8
INTP0 to INTP7
ANO0
ANO1
COMPARATOR
(1 ch)
BCD
ADJUSTMENT
COMPARATOR0
USB VOLTAGE
REGULATOR
VCOUT0
IVCMP0
IVREF0
CRC
CSI20
UREGC
CSI30
UDP
USB
IIC20
SCL30
SDA30
SEG0 to SEG6, SEG12 to SEG25,
SEG27 to SEG42, SEG48 to SEG55
COM0 to COM7
6
PORT 0
UDM
UVBUS
IIC30
44
8
VL1 to VL4
CAPH
CAPL
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
LCD
CONTROLLER/
DRIVER
RAM SPACE
FOR LCD DATA
Page 12 of 147
RL78/L1C
1.5.2
1. OUTLINE
80/85-pin products (without USB)
TIMER ARRAY
UNIT0 (8 ch)
TI00/TO00
ch 0
TI01/TO01
ch 1
TI02/TO02
ch 2
TI03/TO03
ch 3
TI04/TO04
ch 4
TI05/TO05
ch 5
TI06/TO06
ch 6
TI07/TO07
ch 7
REMOOUT
REMOTE CARRIER
A/D CONVERTER
TKBO00
TKBO01
TIMER KB2_0
TKBO10
TKBO11
TIMER KB2_1
TKBO20
TKBO21
TIMER KB2_2
ANI2, ANI5, ANI6
6
ANI16 to ANI21
8
P00 to P07
PORT 1
3
P10 to P12
PORT 2
8
P20 to P27
PORT 3
6
P30 to P35
PORT 4
5
P40, P43 to P46
PORT 5
3
P50 to P52
PORT 6
2
P60, P61
PORT 7
8
P70 to P77
PORT 8
2
P82, P83
AVREFP/ANI0
AVREFM/ANI1
RL78 CPU CORE
CODE FLASH MEMORY
MULTIPLIER &
DIVIDER,
MULITIPLYACCUMULATOR
PORT 12
DATA FLASH MEMORY
3
P125 to P127
4
P121 to P124
P130
PORT 13
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
RAM
12- BIT INTERVAL
TIMER
REAL-TIME
CLOCK
RTC1HZ
RxD0
TxD0
P137
PORT 14
4
P140 to P143
PORT 15
5
P150 to P152,
P155, P156
KEY RETURN
8
KR0 to KR7
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
AVDD, AVSS, TOOLRxD,
VDD0
VSS0 TOOLTxD
SERIAL ARRAY
UNIT0 (4 ch)
RESET CONTROL
UART0
ON-CHIP DEBUG
TOOL0
LINSEL
RxD1
TxD1
SCK00
SI00
SO00
UART1
SDAA0
SERIAL
INTERFACE IICA0
SCLA0
CSI00
BUZZER OUTPUT
SCK10
SI10
SO10
SCL00
SDA00
CSI10
IIC00
SCL10
SDA10
IIC10
SERIAL ARRAY
UNIT1 (4 ch)
RxD2
TxD2
UART2
RxD3
TxD3
UART3
SCK20
SI20
SO20
SCK30
SI30
SO30
SCL20
SDA20
CSI20
CLOCK OUTPUT
CONTROL
2
PCLBUZ0,
PCLBUZ1
SYSTEM
CONTROL
RESET
X1
X2/EXCLK
HIGH-SPEED
ON-CHIP
OSCILLATOR
XT1
XT2/EXCLKS
VOLTAGE
REGULATOR
DATA TRANSFER
CONTROL
INTERRUPT
CONTROL
EVENT LINK
CONTROLLER
D/A CONVERTER
REGC
8
INTP0 to INTP7
ANO0
ANO1
COMPARATOR
(1 ch)
BCD
ADJUSTMENT
COMPARATOR0
VCOUT0
IVCMP0
IVREF0
CRC
CSI30
IIC20
SCL30
SDA30
SEG0 to SEG6, SEG12 to SEG25,
SEG27 to SEG42, SEG48 to SEG55
COM0 to COM7
3
PORT 0
IIC30
44
8
VL1 to VL4
CAPH
CAPL
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
LCD
CONTROLLER/
DRIVER
RAM SPACE
FOR LCD DATA
Page 13 of 147
RL78/L1C
1.5.3
1. OUTLINE
100-pin products (with USB)
TIMER ARRAY
UNIT0 (8 ch)
TI00/TO00
ch 0
TI01/TO01
ch 1
TI02/TO02
ch 2
TI03/TO03
ch 3
TI04/TO04
ch 4
TI05/TO05
ch 5
TI06/TO06
ch 6
TI07/TO07
ch 7
REMOOUT
REMOTE CARRIER
A/D CONVERTER
TKBO00
TKBO01
TIMER KB2_0
TKBO10
TKBO11
TIMER KB2_1
TKBO20
TKBO21
TIMER KB2_2
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
ANI2 to ANI6
6
ANI16 to ANI21
AVREFM/ANI1
RL78 CPU CORE
CODE FLASH MEMORY
MULTIPLIER &
DIVIDER,
MULITIPLYACCUMULATOR
PORT 2
8
P20 to P27
PORT 3
8
P30 to P37
PORT 4
7
P40 to P46
PORT 5
8
P50 to P57
PORT 6
2
P60, P61
PORT 7
8
P70 to P77
PORT 12
AVDD, AVSS, TOOLRxD,
VDD0, VSS0, TOOLTxD
VDD1
VSS1
SDAA0
SERIAL
INTERFACE IICA0
PORT 15
7
P150 to P156
KEY RETURN
8
KR0 to KR7
SERIAL ARRAY
UNIT1 (4 ch)
UART2
RxD3
TxD3
UART3
POR/LVD
CONTROL
RESET CONTROL
TOOL0
RESET
X1
X2/EXCLK
HIGH-SPEED
ON-CHIP
OSCILLATOR
XT1
XT2/EXCLKS
SCLA0
PLL
BUZZER OUTPUT
RxD2
TxD2
P130
P137
P140 to P143
SYSTEM
CONTROL
IIC10
P125 to P127
P121 to P124
4
UART0
IIC00
3
4
PORT 14
ON-CHIP DEBUG
CSI10
SCK20
SI20
SO20
SCK30
SI30
SO30
SCL20
SDA20
P10 to P17
POWER ON RESET/
VOLTAGE
DETECTOR
CSI00
SCL10
SDA10
8
SERIAL ARRAY
UNIT0 (4 ch)
UART1
SCK10
SI10
SO10
SCL00
SDA00
PORT 1
DATA FLASH MEMORY
LINSEL
RxD1
TxD1
SCK00
SI00
SO00
P00 to P07
PORT 13
RAM
REAL-TIME
CLOCK
RxD0
TxD0
8
AVREFP/ANI0
12- BIT INTERVAL
TIMER
RTC1HZ
CLOCK OUTPUT
CONTROL
2
PCLBUZ0,
PCLBUZ1
VOLTAGE
REGULATOR
INTERRUPT
CONTROL
DATA TRANSFER
CONTROL
D/A CONVERTER
EVENT LINK
CONTROLLER
REGC
8
INTP0 to INTP7
ANO0
ANO1
COMPARATOR
(2 ch)
BCD
ADJUSTMENT
USB VOLTAGE
REGULATOR
CRC
CSI20
COMPARATOR0
VCOUT0
IVCMP0
IVREF0
COMPARATOR1
VCOUT1
IVCMP1
IVREF1
UREGC
CSI30
UDP
USB
IIC20
SCL30
SDA30
UDM
UVBUS
IIC30
SEG0 to SEG55
56
COM0 to COM7
8
VL1 to VL4
CAPH
CAPL
5
PORT 0
LCD
CONTROLLER/
DRIVER
RAM SPACE
FOR LCD DATA
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 14 of 147
RL78/L1C
1.5.4
1. OUTLINE
100-pin products (without USB)
TIMER ARRAY
UNIT0 (8 ch)
TI00/TO00
ch 0
TI01/TO01
ch 1
TI02/TO02
ch 2
TI03/TO03
ch 3
TI04/TO04
ch 4
TI05/TO05
ch 5
TI06/TO06
ch 6
TI07/TO07
ch 7
REMOOUT
REMOTE CARRIER
A/D CONVERTER
TKBO00
TKBO01
TIMER KB2_0
TKBO10
TKBO11
TIMER KB2_1
TKBO20
TKBO21
TIMER KB2_2
ANI2 to ANI6
6
ANI16 to ANI21
8
P00 to P07
PORT 1
8
P10 to P17
PORT 2
8
P20 to P27
PORT 3
8
P30 to P37
PORT 4
7
P40 to P46
PORT 5
8
P50 to P57
PORT 6
2
P60, P61
PORT 7
8
P70 to P77
PORT 8
4
P80 to P83
AVREFP/ANI0
AVREFM/ANI1
RL78 CPU CORE
CODE FLASH MEMORY
MULTIPLIER &
DIVIDER,
MULITIPLYACCUMULATOR
PORT 12
DATA FLASH MEMORY
3
P125 to P127
4
P121 to P124
P130
PORT 13
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
RAM
12- BIT INTERVAL
TIMER
REAL-TIME
CLOCK
RTC1HZ
RxD0
TxD0
P137
PORT 14
4
P140 to P143
PORT 15
7
P150 to P156
KEY RETURN
8
KR0 to KR7
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
AVDD, AVSS, TOOLRxD,
VDD0, VSS0, TOOLTxD
VDD1
VSS1
SERIAL ARRAY
UNIT0 (4 ch)
RESET CONTROL
UART0
ON-CHIP DEBUG
TOOL0
LINSEL
RxD1
TxD1
SCK00
SI00
SO00
UART1
SDAA0
SERIAL
INTERFACE IICA0
SCLA0
CSI00
BUZZER OUTPUT
SCK10
SI10
SO10
SCL00
SDA00
CSI10
IIC00
SCL10
SDA10
IIC10
SERIAL ARRAY
UNIT1 (4 ch)
RxD2
TxD2
UART2
RxD3
TxD3
UART3
SCK20
SI20
SO20
SCK30
SI30
SO30
SCL20
SDA20
CSI20
CLOCK OUTPUT
CONTROL
2
PCLBUZ0,
PCLBUZ1
SYSTEM
CONTROL
RESET
X1
X2/EXCLK
HIGH-SPEED
ON-CHIP
OSCILLATOR
XT1
XT2/EXCLKS
VOLTAGE
REGULATOR
DATA TRANSFER
CONTROL
INTERRUPT
CONTROL
EVENT LINK
CONTROLLER
D/A CONVERTER
REGC
8
INTP0 to INTP7
ANO0
ANO1
COMPARATOR
(2 ch)
BCD
ADJUSTMENT
CRC
COMPARATOR0
VCOUT0
IVCMP0
IVREF0
COMPARATOR1
VCOUT1
IVCMP1
IVREF1
CSI30
IIC20
SCL30
SDA30
IIC30
SEG0 to SEG55
56
COM0 to COM7
8
VL1 to VL4
CAPH
CAPL
5
PORT 0
LCD
CONTROLLER/
DRIVER
RAM SPACE
FOR LCD DATA
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 15 of 147
RL78/L1C
1.6
1. OUTLINE
Outline of Functions
[80/85-pin, 100-pin products (with USB)]
(1/2)
80/85-pin
100-pin
R5F110Mx/R5F110Nx (x = E to H, J)
R5F110Px (x = E to H, J)
Code flash memory (KB)
64 to 256
64 to 256
Data flash memory (KB)
8
8
8 to 16 Note 1
8 to 16 Note 1
Item
RAM (KB)
Memory space
Main system clock
1 MB
High-speed system clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
High-speed on-chip
HS (high-speed main) operation mode: 1 to 24 MHz (VDD = 2.7 to 3.6 V),
oscillator clock
HS (high-speed main) operation mode: 1 to 16 MHz (VDD = 2.4 to 3.6 V),
1 to 20 MHz: VDD = 2.7 to 3.6 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V
LS (low-speed main) operation mode: 1 to 8 MHz (VDD = 1.8 to 3.6 V),
LV (low-voltage main) operation mode: 1 to 4 MHz (VDD = 1.6 to 3.6 V)
PLL clock
6, 12, 24 MHz Note 2: VDD = 2.4 to 3.6 V
Subsystem clock
XT1 (crystal) oscillation, external subsystem clock input (EXCLKS)
Low-speed on-chip oscillator clock
15 kHz (TYP.): VDD = 1.6 to 3.6 V
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
0.04167 μs (High-speed on-chip oscillator clock: fHOCO = fIH = 24 MHz operation)
32.768 kHz (TYP.): VDD = 1.6 to 3.6 V
0.04167 μs (PLL clock: fPLL = 48 MHz/fIH = 24 MHz Note 2 operation)
0.05 μs (High-speed system clock: fMX = 20 MHz operation)
30.5 μs (Subsystem clock: fSUB = 32.768 kHz operation)
Instruction set
I/O port
•
•
•
•
•
Data transfer (8/16 bits)
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and Accumulation (16 bits × 16 bits + 32 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
Total
59
77
CMOS I/O
51
69
CMOS input
5
5
CMOS output
1
1
2
2
N-ch open-drain I/O
(6 V tolerance)
Timer
16-bit timer TAU
8 channels (with 1 channel remote control output function) (Timer outputs: 8, PWM outputs: 7 Note 3)
16-bit timer KB2
3 channels (PWM outputs: 6)
Watchdog timer
1 channel
12-bit interval timer
1 channel
Real-time clock 2
1 channel
RTC output
1
1 Hz (subsystem clock: fSUB = 32.768 kHz)
Note 1.
Note 2.
Note 3.
In the case of the 16 KB, this is about 15 KB when the self-programming function and data flash function are used (For
details, see CHAPTER 3 in the RL78/L1C User’s Manual).
In the PLL clock 48 MHz operation, the system clock is 2/4/8 dividing ratio.
The number of outputs varies, depending on the setting of channels in use and the number of the master.
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 16 of 147
RL78/L1C
1. OUTLINE
(2/2)
Item
80/85-pin
100-pin
R5F110Mx/R5F110Nx (x = E to H, J)
R5F110Px (x = E to H, J)
2
2
Clock output/buzzer output
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/12-bit resolution A/D converter
9 channels
D/A converter
2 channels
2 channels
Comparator
1 channel
2 channels
Serial interface
13 channels
• CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
I2C bus
USB
1 channel
1 channel
Function
LCD controller/driver
1 channel
Internal voltage boosting method, capacitor split method, and external resistance division method
are switchable.
Segment signal output
44 (40) Note 1
Common signal output
56 (52) Note 1
4 (8) Note 1
Data transfer controller (DTC)
Event link controller (ELC)
32 sources
33 sources
Event input: 30, Event trigger output: 22
Event input: 31, Event trigger output: 22
Vectored interrupt
Internal
36
37
sources
External
9
9
8
8
Key interrupt
Reset
•
•
•
•
Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
• Internal reset by illegal instruction execution Note 2
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit
• Power-on-reset: 1.51 ± 0.03 V
• Power-down-reset: 1.50 ± 0.03 V
Voltage detector
• Rising edge: 1.67 V to 3.13 V (12 stages)
• Falling edge: 1.63 V to 3.06 V (12 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 1.6 to 3.6 V (TA = -40 to +85°C)
VDD = 2.4 to 3.6 V (TA = -40 to +105°C)
Operating ambient temperature
Note 1.
Note 2.
TA = -40 to +85°C (A: Consumer applications), TA = -40 to +105°C (G: Industrial applications)
The number in parentheses indicates the number of signal outputs when 8 coms are used.
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not is issued by emulation with the in-circuit emulator or on-chip debug
emulator.
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 17 of 147
RL78/L1C
1. OUTLINE
[80/85-pin, 100-pin products (without USB)]
(1/2)
80/85-pin
100-pin
R5F111Mx/R5F111Nx (x = E to H, J)
R5F111Px (x = E to H, J)
Code flash memory (KB)
64 to 256
64 to 256
Data flash memory (KB)
8
8
8 to 16 Note 1
8 to 16 Note 1
Item
RAM (KB)
Memory space
Main system clock
1 MB
High-speed system clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
High-speed on-chip
HS (high-speed main) operation mode: 1 to 24 MHz (VDD = 2.7 to 3.6 V),
oscillator clock
HS (high-speed main) operation mode: 1 to 16 MHz (VDD = 2.4 to 3.6 V,
1 to 20 MHz: VDD = 2.7 to 3.6 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V
LS (low-speed main) operation mode: 1 to 8 MHz (VDD = 1.8 to 3.6 V),
LV (low-voltage main) operation mode: 1 to 4 MHz (VDD = 1.6 to 3.6 V)
Subsystem clock
XT1 (crystal) oscillation, external subsystem clock input (EXCLKS)
Low-speed on-chip oscillator clock
15 kHz (TYP.): VDD = 1.6 to 3.6 V
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
0.04167 μs (High-speed on-chip oscillator clock: fHOCO = fIH = 24 MHz operation)
32.768 kHz (TYP.): VDD = 1.6 to 3.6 V
0.05 μs (High-speed system clock: fMX = 20 MHz operation)
30.5 μs (Subsystem clock: fSUB = 32.768 kHz operation)
Instruction set
I/O port
•
•
•
•
•
Data transfer (8/16 bits)
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and Accumulation (16 bits × 16 bits + 32 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
Total
63
81
CMOS I/O
55
73
CMOS input
5
5
CMOS output
1
1
2
2
N-ch open-drain I/O
(6 V tolerance)
Timer
16-bit timer TAU
8 channels (with 1 channel remote control output function) (Timer outputs: 8, PWM outputs: 7 Note 2)
16-bit timer KB2
3 channels (PWM outputs: 6)
Watchdog timer
1 channel
12-bit interval timer
1 channel
Real-time clock 2
1 channel
RTC output
1
1 Hz (subsystem clock: fSUB = 32.768 kHz)
Note 1.
Note 2.
In the case of the 16 KB, this is about 15 KB when the self-programming function and data flash function are used (For
details, see CHAPTER 3 in the RL78/L1C User’s Manual).
The number of outputs varies, depending on the setting of channels in use and the number of the master.
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 18 of 147
RL78/L1C
1. OUTLINE
(2/2)
Item
80/85-pin
100-pin
R5F111Mx/R5F111Nx (x = E to H, J)
R5F111Px (x = E to H, J)
2
2
Clock output/buzzer output
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/12-bit resolution A/D converter
11 channels
D/A converter
2 channels
2 channels
Comparator
1 channel
2 channels
Serial interface
13 channels
• CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
I2C bus
LCD controller/driver
1 channel
1 channel
Internal voltage boosting method, capacitor split method, and external resistance division method
are switchable.
Segment signal output
44 (40) Note 1
Common signal output
4 (8) Note 1
Data transfer controller (DTC)
Event link controller (ELC)
Vectored interrupt
Internal
sources
External
30 sources
31 sources
Event input: 30, Event trigger output: 22
Event input: 31, Event trigger output: 22
32
33
Key interrupt
Reset
56 (52) Note 1
•
•
•
•
9
9
8
8
Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
• Internal reset by illegal instruction execution Note 2
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit
• Power-on-reset: 1.51 ± 0.03 V
• Power-down-reset: 1.50 ± 0.03 V
Voltage detector
• Rising edge: 1.67 V to 3.13 V (12 stages)
• Falling edge: 1.63 V to 3.06 V (12 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 1.6 to 3.6 V (TA = -40 to +85°C)
VDD = 2.4 to 3.6 V (TA = -40 to +105°C)
Operating ambient temperature
Note 1.
Note 2.
TA = -40 to +85°C (A: Consumer applications), TA = -40 to +105°C (G: Industrial applications)
The number in parentheses indicates the number of signal outputs when 8 coms are used.
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not is issued by emulation with the in-circuit emulator or on-chip debug
emulator.
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 19 of 147
RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
This chapter describes the electrical specifications for the products A: Consumer applications (TA = -40 to +85°C) and
G: Industrial applications (when used in the range of TA = -40 to +85°C).
Caution 1. The RL78 microcontroller has an on-chip debug function, which is provided for development and
evaluation. Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded when this
function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not
liable for problems occurring when the on-chip debug function is used.
Caution 2. The pins mounted depend on the product. Refer to 2.1 Port Function to 2.2.1 With functions for each
product in the RL78/L1C User’s Manual.
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 20 of 147
RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
2.1
Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbols
(1/3)
Conditions
VDD
UVBUS
AVDD
REGC pin input voltage
VIREGC
AVDD ≤ VDD
REGC
Ratings
Unit
-0.5 to + 6.5
V
-0.5 to + 6.5
V
-0.5 to + 4.6
V
-0.3 to + 2.8
V
and -0.3 to VDD + 0.3 Note 1
UREGC pin input voltage
Input voltage
Output voltage
Analog input voltage
VIUREGC
UREGC
-0.3 to UVBUS + 0.3 Note 2
V
-0.3 to VDD + 0.3 Note 3
V
V
VI1
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
P40 to P46, P50 to P57, P70 to P77, P80 to P83,
P125 to P127, P137, P140 to P143, EXCLK,
EXCLKS, RESET
VI2
P60, P61 (N-ch open-drain)
-0.3 to + 6.5
VI3
UDP, UDM
-0.3 to + 6.5
VI4
P150 to P156
-0.3 to AVDD + 0.3
VO1
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
P40 to P46, P50 to P57, P60, P61, P70 to P77,
P80 to P83, P125 to P127, P130, P140 to P143
-0.3 to VDD + 0.3 Note 3
V
VO2
P150 to P156
-0.3 to AVDD + 0.3 Note 3
V
VO3
UDP, UDM
-0.3 to + 3.8
V
VAI1
ANI16 to ANI21
-0.3 to VDD + 0.3
V
V
Note 4
V
and AVREF(+) + 0.3 Notes 3, 5
VAI2
ANI0 to ANI6
-0.3 to AVDD + 0.3
V
and AVREF(+) + 0.3 Notes 3, 5
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Caution
Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF). This value regulates the absolute maximum rating of the
REGC pin. Do not use this pin with voltage applied to it.
Connect the UREGC pin to Vss via a capacitor (0.33 μF). This value regulates the absolute maximum rating of the UREGC
pin. Do not use this pin with voltage applied to it.
Must be 6.5 V or lower.
Must be 4.6 V or lower.
Do not exceed AVREF(+) + 0.3 V in case of A/D conversion target pin.
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the product must be used under conditions that ensure that the absolute maximum
ratings are not exceeded.
Remark 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
Remark 2. AVREF (+): + side reference voltage of the A/D converter.
Remark 3. VSS: Reference voltage
R01DS0192EJ0220 Rev.2.20
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Page 21 of 147
RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Absolute Maximum Ratings (TA = 25°C)
Parameter
LCD voltage
Note 1.
Note 2.
Caution
(2/3)
Symbols
Conditions
Ratings
Unit
VLI1
VL1 input voltage Note 1
-0.3 to +2.8
V
VLI2
VL2 input voltage Note 1
-0.3 to +6.5
V
VLI3
VL3 input voltage Note 1
-0.3 to +6.5
V
VLI4
VL4 input voltage Note 1
-0.3 to +6.5
V
VLI5
CAPL, CAPH input voltage Note 1
-0.3 to +6.5
V
VLO1
VL1 output voltage
-0.3 to +2.8
V
VLO2
VL2 output voltage
-0.3 to +6.5
V
VLO3
VL3 output voltage
-0.3 to +6.5
V
VLO4
VL4 output voltage
-0.3 to +6.5
V
VLO5
CAPL, CAPH output voltage
-0.3 to +6.5
VLO6
COM0 to COM7
SEG0 to SEG55
output voltage
External resistance division method
Capacitor split method
Internal voltage boosting method
V
-0.3 to VDD + 0.3
Note 2
V
-0.3 to VDD + 0.3
Note 2
V
-0.3 to VLI4 + 0.3
Note 2
V
This value only indicates the absolute maximum ratings when applying voltage to the VL1, VL2, VL3, and VL4 pins; it does
not mean that applying voltage to these pins is recommended. When using the internal voltage boosting method or
capacitance split method, connect these pins to VSS via a capacitor (0.47 ± 30%) and connect a capacitor (0.47 ± 30%)
between the CAPL and CAPH pins.
Must be 6.5 V or lower.
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the product must be used under conditions that ensure that the absolute maximum
ratings are not exceeded.
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Absolute Maximum Ratings (TA = 25°C)
Parameter
Output current, high
(3/3)
Symbols
IOH1
Conditions
Per pin
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
P40 to P46, P50 to P57, P70 to P77, P80 to P83,
P125 to P127, P130, P140 to P143
Total of all P40 to P46
pins
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
-170 mA
P50 to P57, P70 to P77, P80 to P83,
P125 to P127, P130, P140 to P143
IOH2
Per pin
P150 to P156
Total of all
pins
Output current, low
Unit
-40
mA
-70
mA
-100
mA
-0.1
mA
-0.7
mA
IOH3
Per pin
UDP, UDM
-3
mA
IOL1
Per pin
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
P40 to P46, P50 to P57, P60, P61, P70 to P77,
P80 to P83, P125 to P127, P130, P140 to P143
40
mA
Total of all P40 to P46
pins
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
170 mA
P50 to P57, P70 to P77, P80 to P83,
P125 to P127, P130, P140 to P143
70
mA
100
mA
0.4
mA
2.8
mA
3
mA
-40 to +85
°C
-65 to +150
°C
IOL2
Per pin
P150 to P156
Total of all
pins
IOL3
Per pin
Operating ambient
temperature
TA
In normal operation mode
Storage temperature
Tstg
Caution
Ratings
UDP, UDM
In flash memory programming mode
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the product must be used under conditions that ensure that the absolute maximum
ratings are not exceeded.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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RL78/L1C
2.2
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Oscillator Characteristics
2.2.1
X1 and XT1 oscillator characteristics
(TA = -40 to +85°C, 1.6 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Resonator
Conditions
MIN.
MAX.
Unit
X1 clock oscillation frequency (fX)
Ceramic resonator/crystal resonator
2.7 V ≤ VDD ≤ 3.6 V
1.0
20.0
MHz
2.4 V ≤ VDD < 2.7 V
1.0
16.0
1.8 V ≤ VDD < 2.4 V
1.0
8.0
1.6 V ≤ VDD < 1.8 V
1.0
Note
XT1 clock oscillation frequency
Crystal resonator
32
TYP.
4.0
32.768
35
kHz
(fXT) Note
Note
Caution
Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time.
Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator
characteristics.
Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock
oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user.
Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select
register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used.
Remark
When using the X1 and XT1 oscillator, refer to 5.4 System Clock Oscillator in the RL78/L1C User’s Manual.
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RL78/L1C
2.2.2
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
On-chip oscillator characteristics
(TA = -40 to +85°C, 1.6 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Oscillators
High-speed on-chip oscillator
Parameters
Conditions
MAX.
Unit
1
48
MHz
-1.0
+1.0
%
1.6 V ≤ VDD ≤ 1.8 V
-5.0
+5.0
%
1.8 V ≤ VDD < 3.6 V
-1.5
+1.5
%
1.6 V ≤ VDD ≤ 1.8 V
-5.5
+5.5
%
fHOCO
MIN.
TYP.
clock frequency Notes 1, 2
High-speed on-chip oscillator
-20 to +85°C
clock frequency accuracy
-40 to -20°C
Low-speed on-chip oscillator
clock frequency
1.8 V ≤ VDD ≤ 3.6 V
15
fIL
Low-speed on-chip oscillator
clock frequency accuracy
Note 1.
Note 2.
2.2.3
-15
kHz
+15
%
High-speed on-chip oscillator frequency is selected with bits 0 to 4 of the option byte (000C2H) and bits 0 to 2 of the
HOCODIV register.
This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time.
PLL oscillator characteristics
(TA = -40 to +85°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Oscillators
PLL input frequency
Note
PLL output frequency Note
Note
Parameters
fPLLIN
fPLL
Conditions
High-speed system clock
MIN.
TYP.
6.00
48.00
MAX.
Unit
16.00
MHz
MHz
Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
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RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
2.3
DC Characteristics
2.3.1
Pin characteristics
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V)
Items
Symbol
Output current,
high
IOH1
Note 1
Conditions
Total of P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P46, P50 to P57,
P70 to P77, P80 to P83, P125 to P127, P130,
P140 to P143
MIN.
Per pin for P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P46, P50 to P57,
P70 to P77, P80 to P83, P125 to P127, P130,
P140 to P143
TYP.
MAX.
Unit
-10.0
mA
Note 2
2.7 V ≤ VDD ≤ 3.6 V
-15.0
mA
1.8 V ≤ VDD < 2.7 V
-7.0
mA
1.6 V ≤ VDD < 1.8 V
-3.0
mA
-0.1
mA
(When duty ≤ 70% Note 3)
IOH2
Per pin for P150 to P156
1.6 V ≤ VDD ≤ 3.6 V
Note 2
Total of all pins
Note 1.
Note 2.
Note 3.
1.6 V ≤ VDD ≤ 3.6 V
-0.7
mA
Value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an output pin.
However, do not exceed the total current value.
Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOH × 0.7)/(n × 0.01)
Where n = 80% and IOH = -10.0 mA
Total output current of pins = (-10.0 × 0.7)/(80 × 0.01) ≈ -8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher
than the absolute maximum rating must not flow into one pin.
Caution
P00 to P02, P10 to P12, P24 to P26, P33 to P35, and P42 to P44 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V)
Items
Symbol
Output current,
IOL1
low Note 1
Conditions
MIN.
TYP.
Per pin for P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P46, P50 to P57,
P70 to P77, P80 to P83,
P125 to P127, P130, P140 to P143
MAX.
Unit
20.0
mA
Note 2
Per pin for P60 and P61
15.0
mA
Note 2
Total of P40 to P46, P130
2.7 V ≤ VDD ≤ 3.6 V
15.0
mA
(When duty ≤ 70% Note 3)
1.8 V ≤ VDD < 2.7 V
9.0
mA
1.6 V ≤ VDD < 1.8 V
4.5
mA
2.7 V ≤ VDD ≤ 3.6 V
35.0
mA
1.8 V ≤ VDD < 2.7 V
20.0
mA
1.6 V ≤ VDD < 1.8 V
10.0
mA
50.0
mA
0.4
mA
Total of P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P50 to P57, P60, P61,
P70 to P77, P80 to P83, P125 to P127,
P140 to P143
(When duty ≤ 70% Note 3)
Total of all pins
(When duty ≤ 70% Note 3)
IOL2
Per pin for P150 to P156
Note 2
Total of all pins
Note 1.
Note 2.
Note 3.
1.6 V ≤ VDD ≤ 3.6 V
2.8
mA
Value of current at which the device operation is guaranteed even if the current flows from an output pin to the VSS pin.
However, do not exceed the total current value.
Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following
expression
(when changing the duty factor from 70% to n%).
• Total output current of pins = (IOL × 0.7)/(n × 0.01)
Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) ≈ 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V)
Items
Input voltage, high
Input voltage, low
Caution
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VIH1
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P46, P50 to P57,
P70 to P77, P80 to P83, P125 to P127,
P140 to P143
Normal input buffer
0.8 VDD
VDD
V
VIH2
P00, P01, P10, P11, P24, P25,
P33, P34, P43, P44
TTL input buffer
3.3 V ≤ VDD ≤ 3.6 V
2.0
VDD
V
TTL input buffer
1.6 V ≤ VDD < 3.3 V
1.50
VDD
V
VIH3
P150 to P156
0.7 AVDD
AVDD
V
VIH4
P60, P61
0.7 VDD
6.0
V
VIH5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0.8 VDD
VDD
V
VIL1
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P46, P50 to P57,
P70 to P77, P80 to P83, P125 to P127,
P140 to P143
Normal input buffer
0
0.2 VDD
V
VIL2
P00, P01, P10, P11, P24, P25,
P33, P34, P43, P44
TTL input buffer
3.3 V ≤ VDD ≤ 3.6 V
0
0.5
V
TTL input buffer
1.6 V ≤ VDD < 3.3 V
0
0.32
V
VIL3
P150 to P156
0
0.3 AVDD
V
VIL4
P60, P61
0
0.3 VDD
V
VIL5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0
0.2 VDD
V
The maximum value of VIH of pins P00 to P02, P10 to P12, P24 to P26, P33 to P35, and P42 to P44 is VDD, even in
the N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V)
Items
Output voltage, high
Output voltage, low
Symbol
VOH1
Conditions
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P46, P50 to P57,
P70 to P77, P80 to P83, P125 to P127,
P130, P140 to P143
MIN.
TYP.
MAX.
Unit
2.7 V ≤ VDD ≤ 3.6 V,
IOH1 = -2.0 mA
VDD - 0.6
V
1.8 V ≤ VDD ≤ 3.6 V,
IOH1 = -1.5 mA
VDD - 0.5
V
1.6 V ≤ VDD < 3.6 V,
IOH1 = -1.0 mA
VDD - 0.5
V
1.6 V ≤ VDD ≤ 3.6 V,
IOH2 = -100 μA
AVDD - 0.5
V
VOH2
P150 to P156
VOL1
P00 to P07, P10 to P17, P20 to P27,
2.7 V ≤ VDD ≤ 3.6 V,
P30 to P37, P40 to P46, P50 to P57,
IOL1 = 3.0 mA
P70 to P77, P80 to P83, P125 to P127, 2.7 V ≤ VDD ≤ 3.6 V,
P130, P140 to P143
IOL1 = 1.5 mA
0.6
V
0.4
V
1.8 V ≤ VDD ≤ 3.6 V,
IOL1 = 0.6 mA
0.4
V
1.6 V ≤ VDD < 1.8 V,
IOL1 = 0.3 mA
0.4
V
VOL2
P150 to P156
1.6 V ≤ VDD ≤ 3.6 V,
IOL2 = 400 μA
0.4
V
VOL3
P60, P61
2.7 V ≤ VDD ≤ 3.6 V,
IOL3 = 3.0 mA
0.4
V
1.8 V ≤ VDD ≤ 3.6 V,
IOL3 = 2.0 mA
0.4
V
1.6 V ≤ VDD ≤ 1.8 V,
IOL3 = 1.0 mA
0.4
V
Caution
P00 to P02, P10 to P12, P24 to P26, P33 to P35, and P42 to P44 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V)
Items
Symbol
Input leakage
current, high
Conditions
MIN.
TYP.
μA
VI = VDD
ILIH2
P20, P21, P140 to P143
VI = VDD
1
μA
ILIH3
P121 to P124 (X1, X2, EXCLK, XT1,
XT2, EXCLKS)
VI = VDD In input port or
external clock input
1
μA
10
μA
ILIH4
P150 to P156
VI = AVDD
1
μA
ILIL1
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P46, P50 to P57,
P60, P61, P70 to P77, P80 to P83,
P125 to P127, P137,
P140 to P143, RESET
VI = VSS
-1
μA
ILIL2
P20, P21, P140 to P143
VI = VSS
-1
μA
ILIL3
P121 to P124 (X1, X2, EXCLK, XT1,
XT2, EXCLKS)
VI = VSS In input port or
external clock input
-1
μA
-10
μA
ILIL4
P150 to P156
VI = AVSS
-1
μA
RU1
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P50 to P57, P70 to P77,
P140 to P143, P125 to P127
VI = VSS 2.4 V ≤ VDD ≤ 3.6 V
10
20
100
kΩ
1.6 V ≤ VDD ≤ 2.4 V
10
30
100
P40 to P46, P80 to P83
VI = VSS
10
20
100
RU2
Remark
1
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P46, P50 to P57,
P60, P61, P70 to P77, P80 to P83,
P125 to P127, P137,
P140 to P143, RESET
In resonator
connection
On-chip pull-up
resistance
Unit
ILIH1
In resonator
connection
Input leakage
current, low
MAX.
kΩ
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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RL78/L1C
2.3.2
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Supply current characteristics
(TA = -40 to +85°C, 1.6 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Supply
current Note 1
Symbol
IDD1
(1/2)
Conditions
Operating HS
fHOCO = 48 MHz Note 3,
mode
(high-speed main) fIH = 24 MHz Note 3
mode Note 5
fHOCO = 24 MHz Note 3,
fIH = 24 MHz Note 3
fHOCO = 16 MHz Note 3,
fIH = 16 MHz Note 3
LS
(low-speed main)
TYP.
MAX.
Unit
VDD = 3.6 V
MIN.
2.2
2.8
mA
VDD = 3.0 V
2.2
2.8
Normal
operation
VDD = 3.6 V
4.4
8.5
VDD = 3.0 V
4.4
8.5
Basic
operation
VDD = 3.6 V
2.0
2.6
VDD = 3.0 V
2.0
2.6
Normal
operation
VDD = 3.6 V
4.2
6.8
VDD = 3.0 V
4.2
6.8
Normal
operation
VDD = 3.6 V
3.1
4.9
VDD = 3.0 V
3.1
4.9
Basic
operation
Normal
operation
VDD = 3.0 V
1.4
2.2
VDD = 2.0 V
1.4
2.2
LV
fHOCO = 4 MHz Note 3,
(low-voltage main) fIH = 4 MHz Note 3
mode Note 5
Normal
operation
VDD = 3.0 V
1.3
1.8
VDD = 2.0 V
1.3
1.8
HS
fMX = 20 MHz Note 2,
(high-speed main) VDD = 3.6 V
mode Note 5
fMX = 20 MHz Note 2,
VDD = 3.0 V
Normal
operation
Square wave input
3.5
5.5
Resonator connection
3.6
5.7
Normal
operation
Square wave input
3.5
5.5
Resonator connection
3.6
5.7
fMX = 16 MHz Note 2,
VDD = 3.6 V
Normal
operation
Square wave input
2.9
4.5
Resonator connection
3.1
4.6
Note 2,
Normal
operation
Square wave input
2.9
4.5
Resonator connection
3.1
4.6
fMX = 10 MHz Note 2,
VDD = 3.6 V
Normal
operation
Square wave input
2.1
3.2
Resonator connection
2.2
3.2
Note 2,
Normal
operation
Square wave input
2.1
3.2
Resonator connection
2.2
3.2
fMX = 8 MHz Note 2,
VDD = 3.6 V
Normal
operation
Square wave input
1.2
2.0
Resonator connection
1.3
2.0
fMX = 8 MHz Note 2,
VDD = 3.0 V
Normal
operation
Square wave input
1.2
2.1
Resonator connection
1.3
2.2
Normal
operation
VDD = 3.6 V
4.7
7.5
VDD = 3.0 V
4.7
7.5
Normal
operation
VDD = 3.6 V
3.1
5.1
VDD = 3.0 V
3.1
5.1
fHOCO = 8 MHz
Note 3,
fIH = 8 MHz Note 3
mode Note 5
fMX = 16 MHz
VDD = 3.0 V
fMX = 10 MHz
VDD = 3.0 V
LS
(low-speed main)
mode Note 5
HS
fPLL = 48 MHz,
(High-speed main) fCLK = 24 MHz Note 2
mode
fPLL = 48 MHz,
(PLL operation)
fCLK = 12 MHz Note 2
fPLL = 48 MHz,
Normal
operation
VDD = 3.6 V
2.3
3.9
VDD = 3.0 V
2.3
3.9
Normal
operation
Square wave input
4.6
6.9
Resonator connection
4.7
6.9
fSUB = 32.768 kHzNote 4 Normal
operation
TA = +25°C
Square wave input
4.9
7.0
Resonator connection
5.0
7.2
Normal
operation
Square wave input
5.2
7.6
Resonator connection
5.2
7.7
fSUB = 32.768 kHzNote 4 Normal
operation
TA = +70°C
Square wave input
5.5
9.3
Resonator connection
5.6
9.4
Normal
operation
Square wave input
6.2
13.3
Resonator connection
6.2
13.4
fCLK = 6 MHz Note 2
Subsystem clock
operation
fSUB = 32.768 kHz
TA = -40°C
fSUB = 32.768
TA = +50°C
fSUB = 32.768
TA = +85°C
Note 4
kHzNote 4
kHzNote 4
mA
mA
mA
mA
mA
μA
(Notes and Remarks are listed on the next page.)
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RL78/L1C
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD, or
VSS. The values below the MAX. column include the peripheral operation current. However, not including the current
flowing into the LCD controller/driver, A/D converter, D/A converter, comparator, LVD circuit, USB 2.0 function module,
I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite.
When high-speed on-chip oscillator and subsystem clock are stopped.
When high-speed system clock and subsystem clock are stopped.
When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power
consumption oscillation). However, not including the current flowing into the real-time clock 2, 12-bit interval timer, and
watchdog timer.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 3.6 V@1 MHz to 24 MHz
2.4 V ≤ VDD ≤ 3.6 V@1 MHz to 16 MHz
LS (low-speed main) mode:
1.8 V ≤ VDD ≤ 3.6 V@1 MHz to 8 MHz
LV (low-voltage main) mode
1.6 V ≤ VDD ≤ 3.6 V@1 MHz to 4 MHz
Remark 1. fMX:
High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (48 MHz max.)
Remark 3. fIH:
Main system clock source frequency when the high-speed on-chip oscillator clock divided 1, 2, 4, or 8, or the PLL
clock divided by 2, 4, or 8 is selected (24 MHz max.)
Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 5. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
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RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(TA = -40 to +85°C, 1.6 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
Supply
current
IDD2
HALT mode
Note 2
(2/2)
TYP.
MAX.
Unit
VDD = 3.6 V
MIN.
0.77
2.70
mA
VDD = 3.0 V
0.77
2.70
fHOCO = 24 MHz Note 4,
VDD = 3.6 V
0.55
1.91
fIH = 24 MHz Note 4
VDD = 3.0 V
0.55
1.90
fHOCO = 16 MHz Note 4,
VDD = 3.6 V
0.48
1.41
fIH = 16 MHz Note 4
VDD = 3.0 V
0.47
1.41
HS (high-speed main) fHOCO = 48 MHz Note 4,
mode Note 7
fIH = 24 MHz Note 4
Note 1
LS (low-speed main)
fHOCO = 8 MHz
mode Note 7
fIH = 8 MHz Note 4
Note 4,
440
770
440
770
HS (high-speed main) fMX = 20 MHz Note 3,
mode Note 7
VDD = 3.6 V
Square wave input
0.35
1.63
Resonator connection
0.51
1.68
fMX = 20 MHz Note 3,
VDD = 3.0 V
Square wave input
0.34
1.63
Resonator connection
0.51
1.68
Note 3,
Square wave input
0.30
1.22
Resonator connection
0.45
1.39
fMX = 16 MHz Note 3,
VDD = 3.0 V
Square wave input
0.29
1.20
Resonator connection
0.45
1.38
Note 3,
Square wave input
0.23
0.82
Resonator connection
0.30
0.90
Square wave input
0.22
0.81
Resonator connection
0.30
0.89
Square wave input
120
510
Resonator connection
170
560
fMX = 8 MHz Note 3,
VDD = 2.0 V
Square wave input
130
520
Resonator connection
170
570
fMX = 48 MHz,
VDD = 3.6 V
0.99
2.89
fCLK = 24 MHz Note 3
VDD = 3.0 V
0.99
2.88
fMX = 48 MHz,
VDD = 3.6 V
0.89
2.48
fCLK = 12 MHz Note 3
VDD = 3.0 V
0.89
2.47
fMX = 48 MHz,
VDD = 3.6 V
0.84
2.27
fCLK = 6 MHz Note 3
VDD = 3.0 V
0.84
2.27
fSUB = 32.768 kHz Note 5 Square wave input
TA = -40°C
Resonator connection
0.32
0.61
0.51
0.80
fSUB = 32.768 kHz Note 5 Square wave input
TA = +25°C
Resonator connection
0.41
0.74
0.62
0.91
fSUB = 32.768 kHz Note 5 Square wave input
TA = +50°C
Resonator connection
0.52
2.30
0.75
2.49
Square wave input
0.82
4.03
Resonator connection
1.08
4.22
fSUB = 32.768 kHz Note 5 Square wave input
TA = +85°C
Resonator connection
1.38
8.04
1.62
8.23
TA = -40°C
0.18
0.52
TA = +25°C
0.25
0.52
TA = +50°C
0.34
2.21
TA = +70°C
0.64
3.94
TA = +85°C
1.18
7.95
fMX = 10 MHz
VDD = 3.6 V
fMX = 10 MHz Note 3,
VDD = 3.0 V
LS (low-speed main)
mode Note 7
HS
(High-speed main)
mode
(PLL operation)
Subsystem clock
operation
fMX = 8 MHz
VDD = 3.0 V
Note 3,
fSUB = 32.768 kHz
TA = +70°C
STOP mode
Note 8
770
770
VDD = 3.0 V
fMX = 16 MHz
VDD = 3.6 V
Note 6
300
300
VDD = 2.0 V
LV (low-voltage main) fHOCO = 4 MHz Note 4,
mode Note 7
fIH = 4 MHz Note 4
IDD3
VDD = 3.0 V
VDD = 2.0 V
Note 5
μA
μA
mA
μA
mA
μA
μA
(Notes and Remarks are listed on the next page.)
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RL78/L1C
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Note 7.
Note 8.
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or
VSS. The values below the MAX. column include the peripheral operation current. However, not including the current
flowing into the LCD controller/driver, A/D converter, D/A converter, comparator, LVD circuit, USB 2.0 function module,
I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite.
During HALT instruction execution by flash memory.
When high-speed on-chip oscillator and subsystem clock are stopped.
When high-speed system clock and subsystem clock are stopped.
When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low
current consumption (AMPHS1 = 1). The current flowing into the real-time clock 2 is included. However, not including the
current flowing into the 12-bit interval timer and watchdog timer.
Not including the current flowing into the real-time clock 2, 12-bit interval timer, and watchdog timer.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 3.6 V@1 MHz to 24 MHz
2.4 V ≤ VDD ≤ 3.6 V@1 MHz to 16 MHz
LS (low-speed main) mode:
1.8 V ≤ VDD ≤ 3.6 V@1 MHz to 8 MHz
LV (low-voltage main) mode
1.6 V ≤ VDD ≤ 3.6 V@1 MHz to 4 MHz
Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode.
Remark 1. fMX:
High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (48 MHz max.)
Remark 3. fIH:
Main system clock source frequency when the high-speed on-chip oscillator clock divided 1, 2, 4, or 8, or the PLL
clock divided by 2, 4, or 8 is selected (24 MHz max.)
Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 5. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
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RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(TA = -40 to +85°C, 1.6 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Low-speed
on-chip oscillator
operating current
RTC2 operating
current
12-bit interval
timer operating
current
Watchdog timer
operating current
A/D converter
operating current
AVREF (+) current
Symbol
Conditions
Unit
IRTC
0.02
μA
0.02
μA
fIL = 15 kHz
0.22
μA
AVDD = 3.0 V, when conversion at maximum speed
422
720
μA
AVDD = 3.0 V, ADREFP1 = 0, ADREFP0 = 0 Note 7
14.0
25.0
μA
AVREFP = 3.0 V, ADREFP1 = 0, ADREFP0 = 1 Note 10
14.0
25.0
14.0
25.0
Notes 1, 3
ITMKA
Notes 1, 2, 4
IWDT
Notes 1, 2, 5
IADC
Notes 6, 7
IAVREF
IADREF
Note 1
VDD = 3.0 V
75.0
μA
78
μA
Notes 1, 9
ITMPS Note 1
D/A converter
operating current
Notes 1, 11
Comparator
operating current
Notes 1, 12
IDAC
ICMP
Per D/A converter channel
0.53
VDD = 3.6 V,
Regulator output
voltage = 2.1 V
Window mode
12.5
μA
Comparator high-speed mode
4.5
μA
VDD = 3.6 V,
Regulator output
voltage = 1.8 V
LVD operating
current
MAX.
μA
ADREFP1 = 1, ADREFP0 = 0
Temperature
sensor operating
current
TYP.
0.20
Note 8
A/D converter
reference voltage
current
MIN.
IFIL Note 1
1.5
mA
Comparator low-speed mode
1.2
μA
Window mode
7.05
μA
Comparator high-speed mode
2.2
μA
Comparator low-speed mode
0.9
μA
0.06
μA
ILVI
Notes 1, 13
Self-programming IFSP
operating current Notes 1, 14
2.50
12.20
mA
BGO operating
current
1.68
12.20
mA
The mode is performed Note 16
0.34
1.10
mA
The A/D conversion operations are performed, Low
voltage mode, AVREFP = VDD = 3.0 V
0.53
2.04
0.70
1.54
SNOOZE
operating current
IBGO
Notes 1, 15
ISNOZ Note 1
ADC operation
CSI/UART operation
LCD operating
current
External
resistance
division method
fLCD = fSUB
LCD clock = 128 Hz
1/3 bias
VDD = 3.6 V,
4-time slice LV4 = 3.6 V
Internal voltage
boosting method
fLCD = fSUB
LCD clock = 128 Hz
1/3 bias
4-time slice
Note 17
Capacitor split
method
fLCD = fSUB
LCD clock = 128 Hz
1/3 bias
4-time slice
IUSB Note 20
IUSB Note 21
ILCD1
Notes 17, 18
ILCD2
Note 17
ILCD3
USB current
Note 19
mA
0.14
μA
VDD = 3.0 V,
LV4 = 3.0 V
(VLCD = 04H)
0.61
μA
VDD = 3.0 V,
LV4 = 3.0 V
0.12
μA
Operating current during USB communication
4.88
mA
Operating current in the USB suspended state
0.04
mA
(Notes and Remarks are listed on the next page.)
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RL78/L1C
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Note 7.
Note 8.
Note 9.
Note 10.
Note 11.
Note 12.
Note 13.
Note 14.
Note 15.
Note 16.
Note 17.
Note 18.
Note 19.
Note 20.
Note 21.
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Current flowing to VDD.
When high speed on-chip oscillator and high-speed system clock are stopped.
Current flowing only to the real-time clock 2 (excluding the operating current of the low-speed on-chip oscillator and the
XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IRTC,
when the real-time clock 2 operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected,
IFIL should be added. IDD2 subsystem clock operation includes the operational current of the real-time clock 2.
Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and
the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and
ITMKA, when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is
selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of the 12-bit interval
timer.
Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The
current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer operates in
STOP mode.
Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and
IADC, IAVREF, IADREF when the A/D converter operates in an operation mode or the HALT mode.
Current flowing to the AVDD.
Current flowing from the reference voltage source of A/D converter.
Operation current flowing to the internal reference voltage.
Current flowing to the AVREFP.
Current flowing only to the D/A converter. The current value of the RL78 microcontrollers is the sum of IDD1 or IDD2 and
IDA when the D/A converter operates in an operation mode or the HALT mode.
Current flowing only to the comparator circuit. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or
IDD3 and ICMP when the comparator circuit operates in the Operating, HALT or STOP mode.
Current flowing only to the LVD circuit. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and
ILVI when the LVD circuit operates in the Operating, HALT or STOP mode.
Current flowing only during self-programming.
Current flowing only during data flash rewrite.
For shift time to the SNOOZE mode, see 23.3.3 SNOOZE mode in the RL78/L1C User’s Manual.
Current flowing only to the LCD controller/driver (VDD pin). The current value of the RL78 microcontrollers is the sum of
the LCD operating current (ILCD1, ILCD2 or ILCD3) to the supply current (IDD1, or IDD2) when the LCD controller/driver
operates in an operation mode or HALT mode. Not including the current that flows through the LCD panel.
Not including the current that flows through the external divider resistor divider resistor.
Current flowing to the UVBUS.
Including the operating current when fPLL = 48 MHz.
Including the current supplied from the pull-up resistor of the UDP pin to the pull-down resistor of the host device, in
addition to the current consumed by this MCU during the suspended state.
Remark 1. fIL: Low-speed on-chip oscillator clock frequency
Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 3. fCLK: CPU/peripheral hardware clock frequency
Remark 4. Temperature condition of the TYP. value is TA = 25°C
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RL78/L1C
2.4
2.4.1
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
AC Characteristics
Basic operation
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V)
Items
Instruction cycle
(minimum instruction
execution time)
Symbol
TCY
Conditions
MAX.
Unit
2.7 V ≤ VDD ≤ 3.6 V
0.0417
1
μs
2.4 V ≤ VDD < 2.7 V
0.0625
1
μs
LS (low-speed main)
mode
1.8 V ≤ VDD ≤ 3.6 V
0.125
1
μs
LV (low-voltage main)
mode
1.6 V ≤ VDD ≤ 3.6 V
0.25
1
μs
Subsystem clock (fSUB) operation
1.8 V ≤ VDD ≤ 3.6 V
28.5
31.3
μs
In the selfHS (high-speed main)
programming mode
mode
LS (low-speed main)
mode
2.7 V ≤ VDD ≤ 3.6 V
0.0417
1
μs
2.4 V ≤ VDD < 2.7 V
0.0625
1
μs
1.8 V ≤ VDD ≤ 3.6 V
0.125
1
μs
1.8 V ≤ VDD ≤ 3.6 V
0.25
1
μs
2.7 V ≤ VDD ≤ 3.6 V
1.0
20.0
MHz
2.4 V ≤ VDD < 2.7 V
1.0
16.0
MHz
1.8 V ≤ VDD < 2.4 V
1.0
8.0
MHz
1.6 V ≤ VDD < 1.8 V
1.0
4.0
MHz
32
35
kHz
Main system
clock (fMAIN)
operation
HS (high-speed main)
mode
LV (low-voltage main)
mode
External main system
clock frequency
fEX
fEXT
External main system
clock input high-level
width, low-level width
tEXH,
tEXL
tEXHS,
tEXLS
TI00 to TI07 input
high-level width,
low-level width
Remark
tTIH,
tTIL
(1/2)
MIN.
TYP.
30.5
2.7 V ≤ VDD ≤ 3.6 V
24
ns
2.4 V ≤ VDD < 2.7 V
30
ns
1.8 V ≤ VDD < 2.4 V
60
ns
1.6 V ≤ VDD < 1.8 V
120
ns
13.7
μs
1/fMCK +
10
ns
fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of timer mode register mn (TMRmn). m: Unit number (m = 0),
n: Channel number (n = 0 to 7))
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RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V)
Items
TO00 to TO07, TKBO00,
TKBO01, TKBO10, TKBO11,
TKBO20, TKBO21
output frequency
PCLBUZ0, PCLBUZ1 output
frequency
Symbol
fTO
fPCL
(2/2)
Conditions
HS (high-speed main) mode
MIN.
TYP.
MAX.
Unit
2.7 V ≤ VDD ≤ 3.6 V
8
MHz
2.4 V ≤ VDD < 2.7 V
8
MHz
LS (low-speed main) mode
1.8 V ≤ VDD ≤ 3.6 V
4
MHz
LV (low-voltage main) mode
1.6 V ≤ VDD ≤ 3.6 V
2
MHz
HS (high-speed main) mode
2.7 V ≤ VDD ≤ 3.6 V
8
MHz
2.4 V ≤ VDD < 2.7 V
8
MHz
LS (low-speed main) mode
1.8 V ≤ VDD ≤ 3.6 V
4
MHz
LV (low-voltage main) mode
1.8 V ≤ VDD ≤ 3.6 V
2
MHz
1.6 V ≤ VDD ≤ 3.6 V
Interrupt input high-level width,
low-level width
tINTH,
tINTL
INTP0 to INTP7
Key interrupt input low-level
width
tKR
1.8 V ≤ VDD ≤ 3.6 V
250
ns
1.6 V ≤ VDD < 1.8 V
1
μs
fCLK > 16 MHz
125
ns
fCLK ≤ 16 MHz
2
fCLK
10
μs
TMKB2 forced output stop input tIHR
high-level width
RESET low-level width
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Dec 28, 2017
tRSL
INTP0 to INTP7
1
μs
Page 38 of 147
RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Minimum Instruction Execution Time during Main System Clock Operation
TCY vs VDD (HS (high-speed main) mode)
10
1.0
Cycle time TCY [µs]
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
0.1
0.0625
0.05
0.0417
0.01
0
1.0
2.0
3.0
4.0
2.4 2.7 3.6
5.0
6.0
Supply voltage VDD [V]
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RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
TCY vs VDD (LS (low-speed main) mode)
10
When the high-speed on-chip oscillator clock is selected
Cycle time TCY [µs]
1.0
During self programming
When high-speed system clock is selected
0.125
0.1
0.01
0
1.0
2.0
1.8
4.0
3.0
5.0
6.0
3.6
Supply voltage VDD [V]
TCY vs VDD (LV (low-voltage main) mode)
10
Cycle time TCY [µs]
1.0
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
0.25
0.1
0.01
0
1.0
2.0
1.6 1.8
4.0
3.0
5.0
6.0
3.6
Supply voltage VDD [V]
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RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
AC Timing Test Points
VIH/VOH
VIH/VOH
Test points
VIL/VOL
VIL/VOL
External System Clock Timing
1/fEX
1/fEXS
tEXL
tEXLS
tEXH
tEXHS
EXCLK/EXCLKS
TI/TO Timing
tTIL
tTIH
TI00 to TI07, TI10 to TI17
1/fTO
TO00 to TO07, TO10 to TO17,
TKBO00, TKBO01,
TKBO10, TKBO11,
TKBO20, TKBO21
Interrupt Request Input Timing
tINTL
tINTH
INTP0 to INTP7
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RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Key Interrupt Input Timing
tKR
KR0 to KR7
Timer KB2 Input Timing
tIHR
INTP0 to INTP7
RESET Input Timing
tRSL
RESET
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RL78/L1C
2.5
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Peripheral Functions Characteristics
AC Timing Test Points
VIH/VOH
VIH/VOH
Test points
VIL/VOL
VIL/VOL
2.5.1
Serial array unit
(1) During communication at same potential (UART mode)
(TA = -40 to +85°C, 1.6 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Mode
MIN.
Transfer
rate Note 1
2.7 V ≤ VDD ≤ 3.6 V
MAX.
LS (low-speed main)
Mode
MIN.
MAX.
LV (low-voltage main)
Mode
MIN.
Unit
MAX.
fMCK/6
fMCK/6
bps
4.0
1.3
0.6
Mbps
fMCK/6 Note 2
fMCK/6
fMCK/6
bps
2.6
1.3
0.6
Mbps
—
fMCK/6 Note 2
fMCK/6
bps
—
1.3
0.6
Mbps
fMCK/6
Theoretical value of the
maximum transfer rate
Note 2
fMCK = fCLK Note 3
2.4 V ≤ VDD ≤ 3.6 V
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 3
1.8 V ≤ VDD ≤ 3.6 V
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 3
1.6 V ≤ VDD ≤ 3.6 V
Theoretical value of the
maximum transfer rate
—
—
fMCK/6
bps
—
—
0.6
Mbps
fMCK = fCLK Note 3
Note 1.
Note 2.
Note 3.
Caution
Transfer rate in the SNOOZE mode is 4800 bps only.
The following conditions are required for low voltage interface.
2.4 V ≤ VDD < 2.7 V: MAX. 2.6 Mbps
1.8 V ≤ VDD < 2.4 V: MAX. 1.3 Mbps
1.6 V ≤ VDD < 1.8 V: MAX. 0.6 Mbps
The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 3.6 V)
16 MHz (2.4 V ≤ VDD ≤ 3.6 V)
LS (low-speed main) mode:
8 MHz (1.8 V ≤ VDD ≤ 3.6 V)
LV (low-voltage main) mode:
4 MHz (1.6 V ≤ VDD ≤ 3.6 V)
Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
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RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
UART mode connection diagram (during communication at same potential)
TxDq
Rx
RL78 microcontroller
User’s device
RxDq
Tx
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Remark 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0 to 3)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
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RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only)
(TA = -40 to +85°C, 2.7 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Mode
MIN.
2.7 V ≤ VDD ≤ 3.6 V
MAX.
LS (low-speed main)
Mode
MIN.
MAX.
LV (low-voltage main)
Mode
MIN.
Unit
MAX.
167
250
500
ns
2.7 V ≤ VDD ≤ 3.6 V
tKCY1/2 - 10
tKCY1/2 - 50
tKCY1/2 - 50
ns
tSIK1
2.7 V ≤ VDD ≤ 3.6 V
33
110
110
ns
tKSI1
2.7 V ≤ VDD ≤ 3.6 V
10
10
10
ns
tKSO1
C = 20 pF Note 4
SCKp cycle time
tKCY1
tKCY1 ≥ fCLK/2
SCKp high-/
low-level width
tKL1
SIp setup time
(to SCKp↑) Note 1
SIp hold time
(from SCKp↑) Note 2
Delay time from
SCKp↓ to SOp
10
10
10
ns
output Note 3
Note 1.
Note 2.
Note 3.
Note 4.
Caution
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
C is the load capacitance of the SCKp and SOp output lines.
Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM number (g = 2)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = -40 to +85°C, 1.6 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
SCKp cycle time
SCKp high-/
low-level width
SIp setup time
Sym
bol
(from SCKp↑) Note 2
Delay time from
SCKp↓ to SOp output
MIN.
Note 2.
Note 3.
Note 4.
Caution
MAX.
LS (low-speed main)
Mode
MIN.
LV (low-voltage main)
Mode
MAX.
MIN.
Unit
MAX.
167
500
1000
ns
2.4 V ≤ VDD ≤ 3.6 V
250
500
1000
ns
1.8 V ≤ VDD ≤ 3.6 V
—
500
1000
ns
1.6 V ≤ VDD ≤ 3.6 V
—
—
1000
ns
tKH1,
tKL1
tSIK1
tKSI1
2.7 V ≤ VDD ≤ 3.6 V
tKCY1/2 - 18
tKCY1/2 - 50
tKCY1/2 - 50
ns
2.4 V ≤ VDD ≤ 3.6 V
tKCY1/2 - 38
tKCY1/2 - 50
tKCY1/2 - 50
ns
1.8 V ≤ VDD ≤ 3.6 V
—
tKCY1/2 - 50
tKCY1/2 - 50
ns
1.6 V ≤ VDD ≤ 3.6 V
—
—
tKCY1/2 - 100
ns
2.7 V ≤ VDD ≤ 3.6 V
44
110
110
ns
2.4 V ≤ VDD ≤ 3.6 V
75
110
110
ns
1.8 V ≤ VDD ≤ 3.6 V
—
110
110
ns
1.6 V ≤ VDD ≤ 3.6 V
—
—
220
ns
2.4 V ≤ VDD ≤ 3.6 V
19
19
19
ns
1.8 V ≤ VDD ≤ 3.6 V
—
19
19
ns
1.6 V ≤ VDD ≤ 3.6 V
—
tKSO1 C = 30 pF
Note 4
Note 3
Note 1.
HS (high-speed main)
Mode
tKCY1 tKCY1 ≥ fCLK/4 2.7 V ≤ VDD ≤ 3.6 V
(to SCKp↑) Note 1
SIp hold time
Conditions
—
19
ns
2.7 V ≤ VDD ≤ 3.6 V
25
50
50
ns
2.4 V ≤ VDD ≤ 3.6 V
25
50
50
ns
1.8 V ≤ VDD ≤ 3.6 V
—
50
50
ns
1.6 V ≤ VDD ≤ 3.6 V
—
—
50
ns
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
C is the load capacitance of the SCKp and SOp output lines.
Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 10, 20, 30), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM number (g = 0 to 3)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = -40 to +85°C, 1.6 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) Mode
MIN.
tKCY2
SCKp cycle
2.7 V ≤ VDD < 3.6 V
tKH2, tKL2
SIp setup time
(to SCKp↑)
tSIK2
Note 1
SIp hold time
(from SCKp↑)
tKSI2
Note 2
Delay time
from SCKp↓ to
SOp output
tKSO2
MIN.
LV (low-voltage main)
Mode
MAX.
MIN.
Unit
MAX.
fMCK > 16 MHz
8/fMCK
—
—
ns
fMCK ≤ 16 MHz
6/fMCK
6/fMCK
6/fMCK
ns
2.4 V ≤ VDD < 3.6 V
6/fMCK
and 500
6/fMCK
and 500
6/fMCK
and 500
ns
1.8 V ≤ VDD < 3.6 V
—
6/fMCK
and 750
6/fMCK
and 750
ns
1.6 V ≤ VDD < 3.6 V
—
—
6/fMCK
and 1500
ns
2.7 V ≤ VDD ≤ 3.6 V
tKCY2/2 - 8
tKCY2/2 - 8
tKCY2/2 - 8
ns
1.8 V ≤ VDD ≤ 3.6 V
—
tKCY2/2 - 18
tKCY2/2 - 18
ns
time Note 5
SCKp high-/
low-level width
MAX.
LS (low-speed main)
Mode
1.6 V ≤ VDD ≤ 3.6 V
—
—
tKCY1/2 - 66
ns
2.7 V ≤ VDD ≤ 3.6 V
1/fMCK + 20
1/fMCK + 30
1/fMCK + 30
ns
2.4 V ≤ VDD ≤ 3.6 V
1/fMCK + 30
1/fMCK + 30
1/fMCK + 30
ns
1.8 V ≤ VDD < 3.6 V
—
1/fMCK + 30
1/fMCK + 30
ns
1.6 V ≤ VDD < 3.6 V
—
—
1/fMCK + 40
ns
2.4 V ≤ VDD < 3.6 V
1/fMCK + 31
1/fMCK + 31
1/fMCK + 31
ns
1.8 V ≤ VDD < 3.6 V
—
1/fMCK + 31
1/fMCK + 31
ns
1.6 V ≤ VDD < 3.6 V
—
—
1/fMCK + 250
ns
C = 30 pF Note 4
Note 3
2.7 V ≤ VDD ≤ 3.6 V
2/fMCK
+ 44
2/fMCK
+ 110
2/fMCK
+ 110
ns
2.4 V ≤ VDD < 3.6 V
2/fMCK
+ 75
2/fMCK
+ 110
2/fMCK
+ 110
ns
1.8 V ≤ VDD < 3.6 V
—
2/fMCK
+ 110
2/fMCK
+ 110
ns
1.6 V ≤ VDD < 3.6 V
—
—
2/fMCK
+ 220
ns
Note 5.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
C is the load capacitance of the SOp output lines.
The maximum transfer rate when using the SNOOZE mode is 1 Mbps.
Caution
Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin by using port input
Note 1.
Note 2.
Note 3.
Note 4.
mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 10, 20, 30), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM number (g = 0 to 3)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
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RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
CSI mode connection diagram (during communication at same potential)
SCKp
RL78 microcontroller
SIp
SOp
SCK
SO
User's device
SI
Remark 1. p: CSI number (p = 00, 10, 20, 30)
Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)
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RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1, 2
tKH1, 2
tKL1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Output data
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1, 2
tKL1, 2
tKH1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Output data
Remark 1. p: CSI number (p = 00, 10, 20, 30)
Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(5) During communication at same potential (simplified I2C mode)
(TA = -40 to +85°C, 1.6 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Mode
MIN.
SCLr clock
frequency
fSCL
MAX.
Hold time
when SCLr = “H”
Data setup time
(reception)
Data hold time
(transmission)
tLOW
tHIGH
tSU: DAT
tHD: DAT
Note 2.
Caution
MAX.
MIN.
Unit
MAX.
1000
400
400
Note 1
Note 1
Note 1
1.8 V ≤ VDD ≤ 3.6 V,
Cb = 100 pF, Rb = 3 kΩ
400
400
400
Note 1
Note 1
Note 1
1.8 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
300
300
300
Note 1
Note 1
Note 1
—
—
250
kHz
kHz
kHz
kHz
2.7 V ≤ VDD ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
475
1150
1150
ns
1.8 V ≤ VDD ≤ 3.6 V,
Cb = 100 pF, Rb = 3 kΩ
1150
1150
1150
ns
1.8 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1550
1550
1550
ns
1.6 V ≤ VDD < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
—
—
1850
ns
2.7 V ≤ VDD ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
475
1150
1150
ns
1.8 V ≤ VDD ≤ 3.6 V,
Cb = 100 pF, Rb = 3 kΩ
1150
1150
1150
ns
1.8 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1550
1550
1550
ns
1.6 V ≤ VDD < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
—
—
1850
ns
2.7 V ≤ VDD ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK + 85
1/fMCK + 145
1/fMCK + 145
ns
Note 2
Note 2
Note 2
1.8 V ≤ VDD ≤ 3.6 V,
Cb = 100 pF, Rb = 3 kΩ
1/fMCK + 145
1/fMCK + 145
1/fMCK + 145
Note 2
Note 2
Note 2
1.8 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1/fMCK + 230
1/fMCK + 230
1/fMCK + 230
Note 2
Note 2
Note 2
1.6 V ≤ VDD < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
—
—
1/fMCK + 290
2.7 V ≤ VDD ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
0
305
0
305
0
305
ns
1.8 V ≤ VDD ≤ 3.6 V,
Cb = 100 pF, Rb = 3 kΩ
0
355
0
355
0
355
ns
1.8 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
0
405
0
405
0
405
ns
0
405
ns
1.6 V ≤ VDD < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
Note 1.
MIN.
LV (low-voltage main)
Mode
2.7 V ≤ VDD ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
1.6 V ≤ VDD < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
Hold time
when SCLr = “L”
LS (low-speed main)
Mode
ns
ns
ns
Note 2
—
—
The value must be equal to or less than fMCK/4.
Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Select the normal input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the
normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h
(POMh).
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RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Simplified I2C mode connection diagram (during communication at same potential)
VDD
Rb
SDAr
SDA
RL78 microcontroller
User’s device
SCLr
SCL
Simplified I2C mode serial transfer timing (during communication at same potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD: DAT
tSU: DAT
Remark 1. Rb[Ω]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance
Remark 2. r: IIC number (r = 00, 10, 20, 30), g: PIM number (g = 0 to 3),
h: POM number (h = 0 to 3)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13)
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RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(6) Communication at different potential (1.8 V, 2.5 V) (UART mode)
(TA = -40 to +85°C, 1.8 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
(1/2)
HS (high-speed main)
Mode
MIN.
Transfer rate
reception
Notes 1, 2
2.7 V ≤ VDD ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V
Theoretical value of the
maximum transfer rate
MAX.
LS (low-speed main)
Mode
LV (low-voltage main)
Mode
MIN.
MIN.
MAX.
Unit
MAX.
fMCK/6 Note 1
fMCK/6 Note 1
fMCK/6 Note 1
bps
4.0
1.3
0.6
Mbps
bps
fMCK = fCLK Note 4
1.8 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Theoretical value of the
maximum transfer rate
fMCK/6
fMCK/6
fMCK/6
Notes 1, 2, 3
Notes 1, 2, 3
Notes 1, 2, 3
4.0
1.3
0.6
Mbps
fMCK = fCLK Note 4
Note 1.
Note 2.
Note 3.
Note 4.
Caution
Transfer rate in the SNOOZE mode is 4,800 bps only.
Use it with VDD ≥ Vb.
The following conditions are required for low voltage interface.
MAX. 2.6 Mbps
2.4 V ≤ VDD < 2.7 V:
MAX. 1.3 Mbps
1.8 V ≤ VDD < 2.4 V:
MAX. 0.6 Mbps
1.6 V ≤ VDD < 1.8 V:
The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 3.6 V)
16 MHz (2.4 V ≤ VDD ≤ 3.6 V)
LS (low-speed main) mode:
8 MHz (1.8 V ≤ VDD ≤ 3.6 V)
LV (low-voltage main) mode:
4 MHz (1.6 V ≤ VDD ≤ 3.6 V)
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq
pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the
DC characteristics with TTL input buffer selected.
Remark 1. Vb[V]: Communication line voltage
Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0 to 3)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
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RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(6) Communication at different potential (1.8 V, 2.5V) (UART mode)
(TA = -40 to +85°C, 1.8 ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
(2/2)
HS (high-speed main)
Mode
Conditions
MIN.
Transfer
MAX.
transmission 2.7 V ≤ VDD ≤ 3.6 V,
rate Note 2
LS (low-speed main)
Mode
MIN.
LV (low-voltage main)
Mode
MAX.
MIN.
Unit
MAX.
Note 1
Note 1
Note 1
bps
1.2 Note 2
1.2 Note 2
1.2 Note 2
Mbps
Notes 3, 4
Notes 3, 4
Notes 3, 4
bps
0.43 Note 5
0.43 Note 5
0.43 Note 5
Mbps
2.3 V ≤ Vb ≤ 2.7 V
Theoretical value of the
maximum transfer rate
Cb = 50 pF, Rb = 2.7 kΩ,
Vb = 2.3 V
1.8 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Theoretical value of the
maximum transfer rate
Cb = 50 pF, Rb = 5.5 kΩ,
Vb = 1.6 V
Note 1.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ VDD < 3.6 V and 2.3 V ≤ Vb ≤ 2.7 V
1
Maximum transfer rate =
2.0
{-Cb × Rb × In (1 Vb
[bps]
)} × 3
1
Transfer rate × 2
- {-Cb × Rb × In (1 -
2.0
Vb
)}
× 100 [%]
Baud rate error (theoretical value) =
(
1
Transfer rate
) × Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
Note 2.
Note 3.
Note 4.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
Use it with VDD ≥ Vb.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate.
Expression for calculating the transfer rate when 1.8 V ≤ VDD < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V
1
Maximum transfer rate =
1.5
{-Cb × Rb × In (1 Vb
[bps]
)} × 3
1
Transfer rate × 2
- {-Cb × Rb × In (1 -
1.5
Vb
Baud rate error (theoretical value) =
)}
× 100 [%]
(
1
Transfer rate
) × Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
Note 5.
Caution
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer.
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq
pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the
DC characteristics with TTL input buffer selected.
R01DS0192EJ0220 Rev.2.20
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
UART mode connection diagram (during communication at different potential)
Vb
Rb
TxDq
Rx
RL78 microcontroller
User’s device
RxDq
Tx
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Remark 1. Rb[Ω]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance,
Vb[V]: Communication line voltage
Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0 to 3)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
R01DS0192EJ0220 Rev.2.20
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RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(7) Communication at different potential (2.5 V) (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only)
(TA = -40 to +85°C, 2.7 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Mode
MIN.
SCKp cycle time
tKCY1
tKCY1 ≥ fCLK/2 2.7V ≤ VDD < 3.6 V,
MAX.
LS (low-speed main)
Mode
MIN.
LV (low-voltage main)
Mode
MAX.
MIN.
Unit
MAX.
300
1150
1150
ns
tKCY1/2 - 120
tKCY1/2 - 120
tKCY1/2 - 120
ns
tKCY1/2 - 10
tKCY1/2 - 50
tKCY1/2 - 50
ns
121
479
479
ns
10
10
10
ns
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SCKp high-level
width
tKH1
SCKp low-level
width
tKL1
SIp setup time
tSIK1
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
tKSI1
tKSO1
output Note 2
Note 1.
Note 2.
Caution
130
130
130
ns
tSIK1
2.7 V ≤ VDD < 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
33
110
110
ns
tKSI1
2.7 V ≤ VDD < 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
10
10
10
ns
tKSO1
2.7 V ≤ VDD < 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
(from SCKp↓) Note 2
Delay time from
SCKp↑ to SOp
2.7 V ≤ VDD < 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 1.4 kΩ
(to SCKp↓) Note 2
SIp hold time
2.7 V ≤ VDD < 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 1.4 kΩ
output Note 1
SIp setup time
2.7 V ≤ VDD < 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
(from SCKp↑) Note 1
Delay time from
SCKp↓ to SOp
2.7 V ≤ VDD < 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 1.4 kΩ
(to SCKp↑) Note 1
SIp hold time
2.7 V ≤ VDD < 3.6 V,
10
10
10
ns
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin
and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and
VIL, see the DC characteristics with TTL input buffer selected.
Remark 1. Rb[Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00), m: Unit number (m = 0),
n: Channel number (n = 0), g: PIM and POM number (g = 2)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 55 of 147
RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(8) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = -40 to +85°C, 1.8 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
(1/2)
HS (high-speed
main) Mode
MIN.
SCKp cycle
time
tKCY1
SCKp high- tKH1
level width
SCKp lowlevel width
Note
Caution
tKL1
MAX.
LS (low-speed
main) Mode
MIN.
MAX.
LV (low-voltage
main) Mode
MIN.
Unit
MAX.
2.7V ≤ VDD < 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
500 Note
1150
1150
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 1.8 V,
Cb = 30 pF, Rb = 5.5 kΩ
1150 Note
1150
1150
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
tKCY1/2 170
tKCY1/2 170
tKCY1/2 170
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
tKCY1/2 458
tKCY1/2 458
tKCY1/2 458
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
tKCY1/2 18
tKCY1/2 50
tKCY1/2 50
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
tKCY1/2 50
tKCY1/2 50
tKCY1/2 50
ns
tKCY1 ≥
fCLK/4
Use it with VDD ≥ Vb.
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin
and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and
VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the page after the next page.)
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 56 of 147
RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(8) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = -40 to +85°C, 1.8 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
SIp setup time
Symbol
tSIK1
(to SCKp↑) Note 1
SIp hold time
tKSI1
(from SCKp↑) Note 1
Delay time from
SCKp↓ to SOp
tKSO1
output Note 1
SIp setup time
tSIK1
(to SCKp↓) Note 2
SIp hold time
tKSI1
(from SCKp↓) Note 2
Delay time from
SCKp↑ to SOp
output Note 2
Note 1.
Note 2.
Note 3.
Caution
tKSO1
Conditions
(2/2)
HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
MIN.
MIN.
MIN.
MAX.
MAX.
Unit
MAX.
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
177
479
479
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
479
479
479
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
19
19
19
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
19
19
19
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
195
195
195
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
483
483
483
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
44
110
110
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
110
110
110
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
19
19
19
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
19
19
19
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
25
25
25
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
25
25
25
ns
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Use it with VDD ≥ Vb.
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin
and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and
VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 57 of 147
RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
CSI mode connection diagram (during communication at different potential)
Vb
Vb
Rb
SCKp
RL78 microcontroller
Rb
SCK
SIp
SO
SOp
SI
User’s device
Remark 1. Rb[Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 10, 20, 30), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0 to 3)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 58 of 147
RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
tKSI1
Input data
SIp
tKSO1
Output data
SOp
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1
tKH1
tKL1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
Remark
Output data
p: CSI number (p = 00, 10, 20, 30), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0 to 3)
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 59 of 147
RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(9) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (slave mode, SCKp... external clock input)
(TA = -40 to +85°C, 1.8 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) Mode
MIN.
tKCY2
SCKp cycle
time Note 1
SCKp high-/
low-level width
SIp setup time
(to SCKp↑)
tKH2,
tKL2
tSIK2
Note 3
SIp hold time
(from SCKp↑)
2.7 V ≤ VDD ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V
MAX.
LS (low-speed
main) Mode
MIN.
MAX.
LV (low-voltage
main) Mode
MIN.
Unit
MAX.
20 MHz < fMCK ≤ 24 MHz
16/fMCK
—
—
ns
16 MHz < fMCK ≤ 20 MHz
14/fMCK
—
—
ns
8 MHz < fMCK ≤ 16 MHz
12/fMCK
—
—
ns
4 MHz < fMCK ≤ 8 MHz
8/fMCK
16/fMCK
—
ns
fMCK ≤ 4 MHz
6/fMCK
10/fMCK
10/fMCK
ns
1.8 V ≤ VDD < 3.3 V,
20 MHz < fMCK ≤ 24 MHz
36/fMCK
—
—
ns
1.6 V ≤ Vb ≤ 2.0 V Note 2
16 MHz < fMCK ≤ 20 MHz
32/fMCK
—
—
ns
8 MHz < fMCK ≤ 16 MHz
26/fMCK
—
—
ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK
16/fMCK
—
ns
fMCK ≤ 4 MHz
10/fMCK
10/fMCK
10/fMCK
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V
tKCY2/2
- 18
tKCY2/2
- 50
tKCY2/2
- 50
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2
tKCY2/2
- 50
tKCY2/2
- 50
tKCY2/2
- 50
ns
2.7 V ≤ VDD ≤ 3.6 V
1/fMCK
+ 20
1/fMCK
+ 30
1/fMCK
+ 30
ns
1.8 V ≤ VDD < 3.3 V
1/fMCK
+ 30
1/fMCK
+ 30
1/fMCK
+ 30
ns
1/fMCK
+ 31
1/fMCK
+ 31
1/fMCK
+ 31
ns
tKSI2
Note 4
Delay time from
SCKp↓ to SOp
output Note 5
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Caution
tKSO2
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V
Cb = 30 pF, Rb = 2.7 kΩ
2/fMCK
+ 214
2/fMCK
+ 573
2/fMCK
+ 573
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2
Cb = 30 pF, Rb = 5.5 kΩ
2/fMCK
+ 573
2/fMCK
+ 573
2/fMCK
+ 573
ns
Transfer rate in the SNOOZE mode: MAX. 1 Mbps
Use it with VDD ≥ Vb.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance) mode for
the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL,
see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 60 of 147
RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
CSI mode connection diagram (during communication at different potential)
Vb
Rb
SCKp
RL78 microcontroller
SCK
SIp
SO
SOp
SI
User’s device
Remark 1. Rb[Ω]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 10, 20, 30), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0 to 3)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 02, 10, 12))
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 61 of 147
RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY2
tKL2
tKH2
SCKp
tSIK2
tKSI2
Input data
SIp
tKSO2
SOp
Output data
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY2
tKH2
tKL2
SCKp
tSIK2
SIp
tKSI2
Input data
tKSO2
SOp
Remark
Output data
p: CSI number (p = 00, 10, 20, 30), m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3), g: PIM and POM number (g = 0 to 3)
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 62 of 147
RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(10) Communication at different potential (1.8 V, 2.5 V) (simplified I2C mode)
(TA = -40 to +85°C, 1.8 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Mode
MIN.
SCLr clock
frequency
Hold time
when SCLr
= “L”
Hold time
when SCLr
= “H”
Data setup
time
(reception)
Data hold
time
(transmission)
fSCL
tLOW
tHIGH
tSU:DAT
tHD:DAT
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
MAX.
LS (low-speed main)
Mode
MIN.
1000
MAX.
LV (low-voltage main)
Mode
MIN.
Unit
MAX.
300 Note 1
300 Note 1
kHz
Note 1
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
400 Note 1
300 Note 1
300 Note 1
kHz
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
400 Note 1
300 Note 1
300 Note 1
kHz
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
475
1550
1550
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb 50 mV/μs standard mode
1.2
μs
High-speed comparator mode,
window mode
2.0
μs
5.0
μs
Ivcmp
Output delay
TYP.
Low-speed comparator mode,
standard mode
3
High-electric-potential VTW+
judgment voltage
High-speed comparator mode, window mode
0.76 VDD
V
Low-electric-potential
judgment voltage
High-speed comparator mode, window mode
0.24 VDD
V
VTW-
100
Operation stabilization tCMP
wait time
Internal reference
VBGR
1.38
μs
1.45
1.50
V
voltage Note
Note
2.6.5
Not usable in LS (low-speed main) mode, LV (low-voltage main) mode, sub-clock operation, or STOP mode.
POR circuit characteristics
(TA = -40 to +85°C, VSS = 0 V)
Parameter
Detection voltage
Symbol
VPOR
VPDR
Minimum pulse width
Note
Conditions
Power supply rise time
Power supply fall time
Note
MIN.
TYP.
MAX.
Unit
1.47
1.51
1.55
V
1.46
1.50
1.54
V
300
TPW
μs
Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a
POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main
system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register
(CSC).
TPW
Supply voltage (VDD)
VPOR
VPDR or 0.7 V
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 77 of 147
RL78/L1C
2.6.6
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
LVD circuit characteristics
(TA = -40 to +85°C, VPDR ≤ VDD ≤ 3.6 V ≤ VSS = 0 V)
Parameter
Detection
voltage
Supply voltage level
Symbol
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VLVD8
VLVD9
VLVD10
VLVD11
VLVD12
VLVD13
Minimum pulse width
Conditions
MIN.
TYP.
MAX.
Unit
Power supply rise time
3.07
3.13
3.19
V
Power supply fall time
3.00
3.06
3.12
V
Power supply rise time
2.96
3.02
3.08
V
Power supply fall time
2.90
2.96
3.02
V
Power supply rise time
2.86
2.92
2.97
V
Power supply fall time
2.80
2.86
2.91
V
Power supply rise time
2.76
2.81
2.87
V
Power supply fall time
2.70
2.75
2.81
V
Power supply rise time
2.66
2.71
2.76
V
Power supply fall time
2.60
2.65
2.70
V
Power supply rise time
2.56
2.61
2.66
V
Power supply fall time
2.50
2.55
2.60
V
Power supply rise time
2.45
2.50
2.55
V
Power supply fall time
2.40
2.45
2.50
V
Power supply rise time
2.05
2.09
2.13
V
Power supply fall time
2.00
2.04
2.08
V
Power supply rise time
1.94
1.98
2.02
V
Power supply fall time
1.90
1.94
1.98
V
Power supply rise time
1.84
1.88
1.91
V
Power supply fall time
1.80
1.84
1.87
V
Power supply rise time
1.74
1.77
1.81
V
Power supply fall time
1.70
1.73
1.77
V
Power supply rise time
1.64
1.67
1.70
V
Power supply fall time
1.60
1.63
1.66
V
tLW
Detection delay time
Caution
300
μs
300
μs
Set the detection voltage (VLVD) to be within the operating voltage range. The operating voltage range depends
on the setting of the user option byte (000C2H/010C2H). The following shows the operating voltage range.
HS (high-speed main) mode: VDD = 2.7 to 3.6 V at 1 MHz to 24 MHz
VDD = 2.4 to 3.6 V at 1 MHz to 16 MHz
LS (low-speed main) mode:
VDD = 1.8 to 3.6 V at 1 MHz to 8 MHz
LV (low-voltage main) mode: VDD = 1.6 to 3.6 V at 1 MHz to 4 MHz
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 78 of 147
RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
LVD Detection Voltage of Interrupt & Reset Mode
(TA = -40 to +85°C, VPDR ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Interrupt and reset
mode
Symbol
VLVDA0
Conditions
LVIS0, LVIS1 = 1, 0
VLVDA1
LVIS0, LVIS1 = 0, 1
VLVDA2
LVIS0, LVIS1 = 0, 0
VLVDA3
VLVDB0
TYP.
MAX.
Unit
1.60
1.63
1.66
V
Rising release reset voltage
1.74
1.77
1.81
V
Falling interrupt voltage
1.70
1.73
1.77
V
Rising release reset voltage
1.84
1.88
1.91
V
Falling interrupt voltage
1.80
1.84
1.87
V
Rising release reset voltage
2.86
2.92
2.97
V
Falling interrupt voltage
2.80
2.86
2.91
V
VPOC0, VPOC1, VPOC2 = 0, 0, 1, falling reset voltage: 1.8 V
LVIS0, LVIS1 = 1, 0
VLVDB1
1.80
1.84
1.87
V
Rising release reset voltage
1.94
1.98
2.02
V
Falling interrupt voltage
1.90
1.94
1.98
V
2.05
2.09
2.13
V
VLVDB2
LVIS0, LVIS1 = 0, 1
Rising release reset voltage
Falling interrupt voltage
2.00
2.04
2.08
V
VLVDB3
LVIS0, LVIS1 = 0, 0
Rising release reset voltage
3.07
3.13
3.19
V
Falling interrupt voltage
3.00
3.06
3.12
V
2.40
2.45
2.50
V
VLVDC0
VPOC0, VPOC1, VPOC2 = 0, 1, 0, falling reset voltage: 2.4 V
LVIS0, LVIS1 = 1, 0
VLVDC1
LVIS0, LVIS1 = 0, 1
VLVDC2
VLVDD0
Rising release reset voltage
2.56
2.61
2.66
V
Falling interrupt voltage
2.50
2.55
2.60
V
Rising release reset voltage
2.66
2.71
2.76
V
Falling interrupt voltage
2.60
2.65
2.70
V
VPOC0, VPOC1, VPOC2 = 0, 1, 1, falling reset voltage: 2.7 V
VLVDD1
VLVDD2
2.7
MIN.
VPOC0, VPOC1, VPOC2 = 0, 0, 0, falling reset voltage: 1.6 V
LVIS0, LVIS1 = 1, 0
LVIS0, LVIS1 = 0, 1
2.70
2.75
2.81
V
Rising release reset voltage
2.86
2.92
2.97
V
Falling interrupt voltage
2.80
2.86
2.91
V
Rising release reset voltage
2.96
3.02
3.08
V
Falling interrupt voltage
2.90
2.96
3.02
V
Power supply voltage rising slope characteristics
(TA = -40 to +85°C, VSS = 0 V)
Parameter
Power supply voltage rising slope
Caution
Conditions
SVDD
MIN.
TYP.
MAX.
Unit
54
V/ms
Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating
voltage range shown in 2.4 AC Characteristics.
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RL78/L1C
2.8
2.8.1
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
LCD Characteristics
Resistance division method
(1) Static display mode
(TA = -40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
LCD drive voltage
Symbol
Conditions
MIN.
TYP.
2.0
VL4
MAX.
Unit
VDD
V
MAX.
Unit
VDD
V
MAX.
Unit
VDD
V
(2) 1/2 bias method, 1/4 bias method
(TA = -40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
LCD drive voltage
Symbol
Conditions
MIN.
TYP.
2.7
VL4
(3) 1/3 bias method
(TA = -40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
LCD drive voltage
Symbol
VL4
R01DS0192EJ0220 Rev.2.20
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Conditions
MIN.
2.5
TYP.
Page 80 of 147
RL78/L1C
2.8.2
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Internal voltage boosting method
(1) 1/3 bias method
(TA = -40 to +85°C, 1.8 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
LCD output voltage variation range
Symbol
VL1
Conditions
C1 to C4
Note 1
= 0.47 μF
Note 2
MIN.
TYP.
MAX.
Unit
VLCD = 04H
0.90
1.00
1.08
V
VLCD = 05H
0.95
1.05
1.13
V
VLCD = 06H
1.00
1.10
1.18
V
VLCD = 07H
1.05
1.15
1.23
V
VLCD = 08H
1.10
1.20
1.28
V
VLCD = 09H
1.15
1.25
1.33
V
VLCD = 0AH
1.20
1.30
1.38
V
VLCD = 0BH
1.25
1.35
1.43
V
VLCD = 0CH
1.30
1.40
1.48
V
VLCD = 0DH
1.35
1.45
1.53
V
VLCD = 0EH
1.40
1.50
1.58
V
VLCD = 0FH
1.45
1.55
1.63
V
VLCD = 10H
1.50
1.60
1.68
V
VLCD = 11H
1.55
1.65
1.73
V
VLCD = 12H
1.60
1.70
1.78
V
VLCD = 13H
1.65
1.75
1.83
V
= 0.47 μF
2 VL1 - 0.1
2 VL1
2 VL1
V
C1 to C4Note 1 = 0.47 μF
3 VL1 - 0.15
3 VL1
3 VL1
V
Doubler output voltage
VL2
C1 to
Tripler output voltage
VL3
Reference voltage setup time Note 2
tVWAIT1
Voltage boost wait time Note 3
tVWAIT2
Note 1.
Note 2.
Note 3.
C4Note 1
C1 to C4Note 1 = 0.47μF
5
ms
500
ms
This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = 0.47 μF±30%
This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the
internal voltage boosting method is selected (by setting the MDSET1 and MDSET0 bits of the LCDM0 register to 01B) if
the default value reference voltage is used) until voltage boosting starts (VLCON = 1).
This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).
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Page 81 of 147
RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
(2) 1/4 bias method
(TA = -40 to +85°C, 1.8 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
LCD output voltage variation range
VL1
Conditions
C1 to C4
Note 1
= 0.47 μF
Doubler output voltage
VL2
Tripler output voltage
VL3
Quadruply output voltage
VL4
Reference voltage setup time
Voltage boost wait time
Note 1.
Note 2.
Note 3.
Note 2
Note 3
Note 2
MIN.
TYP.
MAX.
Unit
VLCD = 04H
0.90
1.00
1.08
V
VLCD = 05H
0.95
1.05
1.13
V
VLCD = 06H
1.00
1.10
1.18
V
VLCD = 07H
1.05
1.15
1.23
V
VLCD = 08H
1.10
1.20
1.28
V
VLCD = 09H
1.15
1.25
1.33
V
VLCD = 0AH
1.20
1.30
1.38
V
C1 to C4
Note 1
= 0.47 μF
2 VL1 - 0.08
2 VL1
2 VL1
V
C1 to C4
Note 1
= 0.47 μF
3 VL1 - 0.12
3 VL1
3 VL1
V
C1 to C5
Note 1
= 0.47 μF
4 VL1 - 0.16
4 VL1
4 VL1
V
C1 to C5
Note 1
tVWAIT1
tVWAIT2
= 0.47μF
5
ms
500
ms
This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL3 and GND
C5: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = 0.47 μF±30%
This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the
internal voltage boosting method is selected (by setting the MDSET1 and MDSET0 bits of the LCDM0 register to 01B) if
the default value reference voltage is used) until voltage boosting starts (VLCON = 1).
This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).
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Page 82 of 147
RL78/L1C
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
2.8.3
Capacitor split method
(1) 1/3 bias method
(TA = -40 to +85°C, 2.2 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
VL4
C1 to C4 = 0.47 μF
VL2 voltage
VL2
C1 to C4 = 0.47 μF Note 2
2/3 VL4 - 0.1
2/3 VL4
2/3 VL4 + 0.1
V
VL1 voltage
VL1
C1 to C4 = 0.47 μF Note 2
1/3 VL4 - 0.1
1/3 VL4
1/3 VL4 + 0.1
V
Capacitor split wait time Note 1
tVWAIT
Note 1.
Note 2.
VDD
Unit
VL4 voltage
Note 2
V
100
ms
This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1).
This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = 0.47 μF±30%
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RL78/L1C
2.9
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
RAM Data Retention Characteristics
(TA = -40 to +85°C, VSS = 0 V)
Parameter
Symbol
Data retention supply
voltage
Conditions
MIN.
TYP.
MAX.
Unit
3.6
V
1.46 Note
VDDDR
This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage reaches the
Note
level that triggers a POR reset but not once it reaches the level at which a POR reset is generated.
Operation mode
STOP mode
RAM data retention mode
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
2.10
Flash Memory Programming Characteristics
(TA = -40 to +85°C, 1.8 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
CPU/peripheral hardware clock
frequency
fCLK
2.4 V ≤ VDD ≤ 3.6 V
Number of code flash rewrites
Cerwr
Retained for 20 years
TA = 85°C
Notes 1, 2, 3
Retained for 5 years
TA = 85°C
Retained for 20 years
TA = 85°C
Note 2.
Note 3.
2.11
TYP.
1
MAX.
Unit
24
MHz
Times
1,000
Retained for 1 year
TA = 25°C
Number of data flash rewrites
Notes 1, 2, 3
Note 1.
MIN.
1,000,000
100,000
10,000
1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite.
When using flash memory programmer and Renesas Electronics self programming library
These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics
Corporation.
Dedicated Flash Memory Programmer Communication (UART)
(TA = -40 to +85°C, 1.8 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Transfer rate
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Symbol
Conditions
During serial programming
MIN.
115,200
TYP.
MAX.
Unit
1,000,000
bps
Page 84 of 147
RL78/L1C
2.12
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
Timing of Entry to Flash Memory Programming Modes
(TA = -40 to +85°C, 1.8 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
How long from when an external reset ends until the
initial communication settings are specified
tSUINIT
POR and LVD reset must end
before the external reset ends.
How long from when the TOOL0 pin is placed at the
low level until an external reset ends
tSU
POR and LVD reset must end
before the external reset ends.
10
μs
Time to hold the TOOL0 pin at the low level after an
external reset is released (excluding the processing
time of the firmware to control the flash memory)
tHD
POR and LVD reset must end
before the external reset ends.
1
ms
Conditions
MIN.
TYP.
MAX.
Unit
100
ms
RESET
723 µs + tHD
processing
time
1-byte data for setting mode
TOOL0
tSU
tSUINIT
The low level is input to the TOOL0 pin.
The external reset ends (POR and LVD reset must end before the external reset ends.).
The TOOL0 pin is set to the high level.
Setting of the flash memory programming mode by UART reception and complete the baud rate setting.
Remark
tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from
when the resets end.
tSU:
How long from when the TOOL0 pin is placed at the low level until a external reset ends
tHD:
How long to keep the TOOL0 pin at the low level from when the external and internal resets end (except soft
processing time)
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RL78/L1C
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = 40 to +105°C)
This chapter describes the following electrical specifications.
Target products G: Industrial applications TA = -40 to +105°C
R5F110xxGxx, R5F111xxGxx
Caution 1. The RL78 microcontroller has an on-chip debug function, which is provided for development and
evaluation. Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded when this
function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not
liable for problems occurring when the on-chip debug function is used.
Caution 2. The pins mounted depend on the product. Refer to 2.1 Port Function to 2.2.1 With functions for each
product in the RL78/L1C User’s Manual.
Caution 3. Please contact Renesas Electronics sales office for derating of operation under TA = +85°C to
+105°C. Derating is the systematic reduction of load for the sake of improved reliability.
Remark
When the RL78 microcontroller is used in the range of TA = -40 to +85°C, see 2. ELECTRICAL
SPECIFICATIONS (TA = -40 to +85°C).
The following functions differ between the products “G: Industrial applications (TA = -40 to +105°C)” and the products “A:
Consumer applications and G: Industrial applications (when used in the range of TA = -40 to +85°C)”.
Parameter
A: Consumer applications
G: Industrial applications
Operating ambient temperature
TA = -40 to +85°C
TA = -40 to +105°C
Operating mode
Operating voltage range
HS (high-speed main) mode:
2.7 V ≤ VDD ≤ 3.6 V@1 MHz to 24 MHz
2.4 V ≤ VDD ≤ 3.6 V@1 MHz to 16 MHz
LS (low-speed main) mode:
1.8 V ≤ VDD ≤ 3.6 V@1 MHz to 8 MHz
LV (low-voltage main) mode:
1.6 V ≤ VDD ≤ 3.6 V@1 MHz to 4 MHz
HS (high-speed main) mode only:
2.7 V ≤ VDD ≤ 3.6 V@1 MHz to 24 MHz
2.4 V ≤ VDD ≤ 3.6 V@1 MHz to 16 MHz
High-speed on-chip oscillator
clock accuracy
1.8 V ≤ VDD ≤ 3.6 V:
±1.0% @ TA = -20 to +85°C
±1.5% @ TA = -40 to -20°C
1.6 V ≤ VDD ≤ 1.8 V:
±5.0% @ TA = -20 to +85°C
±5.5% @ TA = -40 to -20°C
2.4 V ≤ VDD ≤ 3.6 V:
±2.0% @ TA = +85 to +105°C
±1.0% @ TA = -20 to +85°C
±1.5% @ TA = -40 to -20°C
Serial array unit
UART
CSI: fCLK/4
UART
CSI: fCLK/4
Simplified I2C communication
Simplified I2C communication
IICA
Normal mode
Fast mode
Fast mode plus
Normal mode
Fast mode
Voltage detector
• Rise detection: 1.67 V to 3.13 V (12 levels)
• Fall detection: 1.63 V to 3.06 V (12 levels)
• Rise detection: 2.61 V to 3.13 V (6 levels)
• Fall detection: 2.55 V to 3.06 V (6 levels)
Remark
The electrical characteristics of the products G: Industrial applications (TA = -40 to +105°C) are different from those of the
products “A: Consumer applications”. For details, refer to 3.1 to 3.12.
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RL78/L1C
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
3.1
Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbols
(1/3)
Conditions
VDD
UVBUS
AVDD
REGC pin input voltage
VIREGC
AVDD ≤ VDD
REGC
Ratings
Unit
-0.5 to + 6.5
V
-0.5 to + 6.5
V
-0.5 to + 4.6
V
-0.3 to + 2.8
V
and -0.3 to VDD + 0.3 Note 1
UREGC pin input voltage
Input voltage
Output voltage
Analog input voltage
VIUREGC
UREGC
-0.3 to UVBUS + 0.3 Note 2
V
-0.3 to VDD + 0.3 Note 3
V
V
VI1
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
P40 to P46, P50 to P57, P70 to P77, P80 to P83,
P125 to P127, P137, P140 to P143, EXCLK,
EXCLKS, RESET
VI2
P60, P61 (N-ch open-drain)
-0.3 to + 6.5
VI3
UDP, UDM
-0.3 to + 6.5
VI4
P150 to P156
-0.3 to AVDD + 0.3
VO1
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
P40 to P46, P50 to P57, P60, P61, P70 to P77,
P80 to P83, P125 to P127, P130, P140 to P143
-0.3 to VDD + 0.3 Note 3
V
VO2
P150 to P156
-0.3 to AVDD + 0.3 Note 3
V
VO3
UDP, UDM
-0.3 to + 3.8
V
VAI1
ANI16 to ANI21
-0.3 to VDD + 0.3
V
V
Note 4
V
and AVREF(+) + 0.3 Notes 3, 5
VAI2
ANI0 to ANI6
-0.3 to AVDD + 0.3
V
and AVREF(+) + 0.3 Notes 3, 5
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Caution
Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF). This value regulates the absolute maximum rating of the
REGC pin. Do not use this pin with voltage applied to it.
Connect the UREGC pin to Vss via a capacitor (0.33 μF). This value regulates the absolute maximum rating of the UREGC
pin. Do not use this pin with voltage applied to it.
Must be 6.5 V or lower.
Must be 4.6 V or lower.
Do not exceed AVREF(+) + 0.3 V in case of A/D conversion target pin.
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the product must be used under conditions that ensure that the absolute maximum
ratings are not exceeded.
Remark 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
Remark 2. AVREF (+): + side reference voltage of the A/D converter.
Remark 3. VSS: Reference voltage
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RL78/L1C
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
Absolute Maximum Ratings (TA = 25°C)
Parameter
LCD voltage
Note 1.
Note 2.
Caution
(2/3)
Symbols
Conditions
Ratings
Unit
VLI1
VL1 input voltage Note 1
-0.3 to +2.8
V
VLI2
VL2 input voltage Note 1
-0.3 to +6.5
V
VLI3
VL3 input voltage Note 1
-0.3 to +6.5
V
VLI4
VL4 input voltage Note 1
-0.3 to +6.5
V
VLI5
CAPL, CAPH input voltage Note 1
-0.3 to +6.5
V
VLO1
VL1 output voltage
-0.3 to +2.8
V
VLO2
VL2 output voltage
-0.3 to +6.5
V
VLO3
VL3 output voltage
-0.3 to +6.5
V
VLO4
VL4 output voltage
-0.3 to +6.5
V
VLO5
CAPL, CAPH output voltage
-0.3 to +6.5
VLO6
COM0 to COM7
SEG0 to SEG55
output voltage
External resistance division method
Capacitor split method
Internal voltage boosting method
V
-0.3 to VDD + 0.3
Note 2
V
-0.3 to VDD + 0.3
Note 2
V
-0.3 to VLI4 + 0.3
Note 2
V
This value only indicates the absolute maximum ratings when applying voltage to the VL1, VL2, VL3, and VL4 pins; it does
not mean that applying voltage to these pins is recommended. When using the internal voltage boosting method or
capacitance split method, connect these pins to VSS via a capacitor (0.47 ± 30%) and connect a capacitor (0.47 ± 30%)
between the CAPL and CAPH pins.
Must be 6.5 V or lower.
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the product must be used under conditions that ensure that the absolute maximum
ratings are not exceeded.
R01DS0192EJ0220 Rev.2.20
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RL78/L1C
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
Absolute Maximum Ratings (TA = 25°C)
Parameter
Output current, high
(3/3)
Symbols
IOH1
Conditions
Per pin
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
P40 to P46, P50 to P57, P70 to P77, P80 to P83,
P125 to P127, P130, P140 to P143
Total of all P40 to P46
pins
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
-170 mA
P50 to P57, P70 to P77, P80 to P83,
P125 to P127, P130, P140 to P143
IOH2
Per pin
P150 to P156
Total of all
pins
Output current, low
-40
mA
-70
mA
-100
mA
-0.1
mA
-0.7
mA
Per pin
UDP, UDM
-3
mA
IOL1
Per pin
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
P40 to P46, P50 to P57, P60, P61, P70 to P77,
P80 to P83, P125 to P127, P130, P140 to P143
40
mA
Total of all P40 to P46
pins
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
170 mA
P50 to P57, P70 to P77, P80 to P83,
P125 to P127, P130, P140 to P143
70
mA
100
mA
0.4
mA
2.8
mA
3
mA
-40 to +105
°C
Per pin
P150 to P156
Total of all
pins
IOL3
Per pin
Operating ambient
temperature
TA
In normal operation mode
Storage temperature
Tstg
Caution
Unit
IOH3
IOL2
Ratings
UDP, UDM
In flash memory programming mode
-40 to +105
-65 to +150
°C
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the product must be used under conditions that ensure that the absolute maximum
ratings are not exceeded.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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RL78/L1C
3.2
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
Oscillator Characteristics
3.2.1
X1 and XT1 oscillator characteristics
(TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Resonator
Conditions
MIN.
MAX.
Unit
X1 clock oscillation frequency (fX)
Ceramic resonator/crystal resonator
2.7 V ≤ VDD ≤ 3.6 V
1.0
20.0
MHz
2.4 V ≤ VDD < 2.7 V
1.0
16.0
Note
XT1 clock oscillation frequency
Crystal resonator
32
TYP.
32.768
35
kHz
(fXT) Note
Note
Caution
Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time.
Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator
characteristics.
Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock
oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user.
Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select
register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used.
Remark
When using the X1 and XT1 oscillator, refer to 5.4 System Clock Oscillator in the RL78/L1C User’s Manual.
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3.2.2
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
On-chip oscillator characteristics
(TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Oscillators
High-speed on-chip oscillator
Parameters
Conditions
fHOCO
MIN.
TYP.
MAX.
Unit
1
24
MHz
-1.0
+1.0
%
clock frequency Notes 1, 2
High-speed on-chip oscillator
-20 to +85°C
clock frequency accuracy
-40 to -20°C
-1.5
+1.5
%
+85 to +105°C
-2.0
+2.0
%
Low-speed on-chip oscillator
clock frequency
fIL
15
Low-speed on-chip oscillator
clock frequency accuracy
Note 1.
Note 2.
3.2.3
-15
kHz
+15
%
High-speed on-chip oscillator frequency is selected with bits 0 to 4 of the option byte (000C2H) and bits 0 to 2 of the
HOCODIV register.
This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time.
PLL oscillator characteristics
(TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Oscillators
PLL input frequency
Note
PLL output frequency Note
Note
Parameters
fPLLIN
fPLL
Conditions
High-speed system clock
MIN.
TYP.
6.00
48.00
MAX.
Unit
16.00
MHz
MHz
Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
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3.3
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
DC Characteristics
3.3.1
Pin characteristics
(TA = -40 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V)
Items
Symbol
Output current,
IOH1
high
Note 1
Conditions
MIN.
Per pin for P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P46, P50 to P57,
P70 to P77, P80 to P83, P125 to P127, P130,
P140 to P143
Total of P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P46, P50 to P57,
P70 to P77, P80 to P83, P125 to P127, P130,
P140 to P143
TYP.
MAX.
-3.0
2.7 V ≤ VDD ≤ 3.6 V
Note 2
Unit
mA
-15.0
mA
-7.0
mA
-0.1 Note 2
mA
-0.7
mA
2.4 V ≤ VDD < 2.7 V
(When duty ≤ 70% Note 3)
IOH2
Per pin for P150 to P156
Total of all pins
Note 1.
Note 2.
Note 3.
2.4 V ≤ VDD ≤ 3.6 V
Value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an output pin.
However, do not exceed the total current value.
Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOH × 0.7)/(n × 0.01)
Where n = 80% and IOH = -10.0 mA
Total output current of pins = (-10.0 × 0.7)/(80 × 0.01) ≈ -8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher
than the absolute maximum rating must not flow into one pin.
Caution
P00 to P02, P10 to P12, P24 to P26, P33 to P35, and P42 to P44 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
(TA = -40 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V)
Items
Symbol
Output current,
IOL1
low Note 1
Conditions
MIN.
TYP.
Per pin for P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P46, P50 to P57,
P70 to P77, P80 to P83,
P125 to P127, P130, P140 to P143
MAX.
Unit
8.5
mA
Note 2
Per pin for P60 and P61
15.0
mA
Note 2
Total of P40 to P46, P130
2.7 V ≤ VDD ≤ 3.6 V
15.0
mA
(When duty ≤ 70% Note 3)
2.4 V ≤ VDD < 2.7 V
9.0
mA
Total of P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P50 to P57, P60, P61,
P70 to P77, P80 to P83, P125 to P127,
P140 to P143
2.7 V ≤ VDD ≤ 3.6 V
35.0
mA
2.4 V ≤ VDD < 2.7 V
20.0
mA
50.0
mA
0.4
mA
(When duty ≤ 70% Note 3)
Total of all pins
(When duty ≤ 70% Note 3)
IOL2
Per pin for P150 to P156
Note 2
Total of all pins
Note 1.
Note 2.
Note 3.
2.4 V ≤ VDD ≤ 3.6 V
2.8
mA
Value of current at which the device operation is guaranteed even if the current flows from an output pin to the VSS pin.
However, do not exceed the total current value.
Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following
expression
(when changing the duty factor from 70% to n%).
• Total output current of pins = (IOL × 0.7)/(n × 0.01)
Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) ≈ 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
(TA = -40 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V)
Items
Input voltage, high
Input voltage, low
Caution
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VIH1
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P46, P50 to P57,
P70 to P77, P80 to P83, P125 to P127,
P140 to P143
Normal input buffer
0.8 VDD
VDD
V
VIH2
P00, P01, P10, P11, P24, P25,
P33, P34, P43, P44
TTL input buffer
3.3 V ≤ VDD ≤ 3.6 V
2.0
VDD
V
TTL input buffer
2.4 V ≤ VDD < 3.3 V
1.50
VDD
V
VIH3
P150 to P156
0.7 AVDD
AVDD
V
VIH4
P60, P61
0.7 VDD
6.0
V
VIH5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0.8 VDD
VDD
V
VIL1
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P46, P50 to P57,
P70 to P77, P80 to P83, P125 to P127,
P140 to P143
Normal input buffer
0
0.2 VDD
V
VIL2
P00, P01, P10, P11, P24, P25,
P33, P34, P43, P44
TTL input buffer
3.3 V ≤ VDD ≤ 3.6 V
0
0.5
V
TTL input buffer
2.4 V ≤ VDD < 3.3 V
0
0.32
V
VIL3
P150 to P156
0
0.3 AVDD
V
VIL4
P60, P61
0
0.3 VDD
V
VIL5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0
0.2 VDD
V
The maximum value of VIH of pins P00 to P02, P10 to P12, P24 to P26, P33 to P35, and P42 to P44 is VDD, even in
the N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
(TA = -40 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V)
Items
Output voltage, high
Output voltage, low
Symbol
VOH1
Conditions
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P46, P50 to P57,
P70 to P77, P80 to P83, P125 to P127,
P130, P140 to P143
MIN.
TYP.
MAX.
Unit
2.7 V ≤ VDD ≤ 3.6 V,
IOH1 = -2.0 mA
VDD - 0.6
V
2.4 V ≤ VDD ≤ 3.6 V,
IOH1 = -1.5 mA
VDD - 0.5
V
AVDD - 0.5
V
VOH2
P150 to P156
2.4 V ≤ VDD ≤ 3.6 V,
IOH2 = -100 μA
VOL1
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P46, P50 to P57,
2.7 V ≤ VDD ≤ 3.6 V,
IOL1 = 3.0 mA
0.6
V
P70 to P77, P80 to P83, P125 to P127,
P130, P140 to P143
2.4 V ≤ VDD ≤ 3.6 V,
IOL1 = 1.5 mA
0.4
V
2.4 V ≤ VDD ≤ 3.6 V,
IOL1 = 0.6 mA
0.4
V
VOL2
P150 to P156
2.4 V ≤ VDD ≤ 3.6 V,
IOL2 = 400 μA
0.4
V
VOL3
P60, P61
2.7 V ≤ VDD ≤ 3.6 V,
IOL3 = 3.0 mA
0.4
V
2.4 V ≤ VDD ≤ 3.6 V,
IOL3 = 2.0 mA
0.4
V
Caution
P00 to P02, P10 to P12, P24 to P26, P33 to P35, and P42 to P44 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
(TA = -40 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V)
Items
Symbol
Input leakage
current, high
Conditions
MIN.
TYP.
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P46, P50 to P57,
P60, P61, P70 to P77, P80 to P83,
P125 to P127, P137,
P140 to P143, RESET
VI = VDD
1
μA
ILIH2
P20, P21, P140 to P143
VI = VDD
1
μA
ILIH3
P121 to P124 (X1, X2, EXCLK, XT1,
XT2, EXCLKS)
VI = VDD In input port or
external clock input
1
μA
10
μA
ILIH4
P150 to P156
VI = AVDD
1
μA
ILIL1
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P46, P50 to P57,
P60, P61, P70 to P77, P80 to P83,
P125 to P127, P137,
P140 to P143, RESET
VI = VSS
-1
μA
ILIL2
P20, P21, P140 to P143
VI = VSS
-1
μA
ILIL3
P121 to P124 (X1, X2, EXCLK, XT1,
XT2, EXCLKS)
VI = VSS In input port or
external clock input
-1
μA
-10
μA
In resonator
connection
On-chip pull-up
resistance
Remark
Unit
ILIH1
In resonator
connection
Input leakage
current, low
MAX.
ILIL4
P150 to P156
VI = AVSS
-1
μA
RU1
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P50 to P57, P70 to P77,
P140 to P143, P125 to P127
VI = VSS 2.4 V ≤ VDD ≤ 3.6 V
10
20
100
kΩ
RU2
P40 to P46, P80 to P83
VI = VSS
10
20
100
kΩ
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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3.3.2
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
Supply current characteristics
(TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Supply
current Note 1
Symbol
IDD1
(1/2)
Conditions
Operating HS
fHOCO = 48 MHz Note 3,
mode
(high-speed main) fIH = 24 MHz Note 3
mode Note 5
fHOCO = 24 MHz Note 3,
fIH = 24 MHz Note 3
fHOCO = 16 MHz Note 3,
fIH = 16 MHz Note 3
TYP.
MAX.
Unit
VDD = 3.6 V
MIN.
2.2
2.9
mA
VDD = 3.0 V
2.2
2.9
Normal
operation
VDD = 3.6 V
4.4
9.2
VDD = 3.0 V
4.4
9.2
Basic
operation
VDD = 3.6 V
2.0
2.6
VDD = 3.0 V
2.0
2.6
Normal
operation
VDD = 3.6 V
4.2
7.0
VDD = 3.0 V
4.2
7.0
Normal
operation
VDD = 3.6 V
3.1
5.0
VDD = 3.0 V
3.1
5.0
3.5
5.9
Basic
operation
HS
fMX = 20 MHz Note 2,
(high-speed main) VDD = 3.6 V
mode Note 5
fMX = 20 MHz Note 2,
VDD = 3.0 V
Normal
operation
Square wave input
Resonator connection
3.6
6.0
Normal
operation
Square wave input
3.5
5.9
Resonator connection
3.6
6.0
Note 2,
Normal
operation
Square wave input
2.9
4.5
Resonator connection
3.1
4.6
fMX = 16 MHz Note 2,
VDD = 3.0 V
Normal
operation
Square wave input
2.9
4.5
Resonator connection
3.1
4.6
Note 2,
Normal
operation
Square wave input
2.1
3.5
Resonator connection
2.2
3.5
fMX = 10 MHz Note 2,
VDD = 3.0 V
Normal
operation
Square wave input
2.1
3.5
Resonator connection
2.2
3.5
HS
fPLL = 48 MHz,
(High-speed main) fCLK = 24 MHz Note 2
mode
fPLL = 48 MHz,
(PLL operation)
fCLK = 12 MHz Note 2
Normal
operation
VDD = 3.6 V
4.7
7.6
VDD = 3.0 V
4.7
7.6
VDD = 3.6 V
3.1
5.2
VDD = 3.0 V
3.1
5.1
VDD = 3.6 V
2.3
3.9
fMX = 16 MHz
VDD = 3.6 V
fMX = 10 MHz
VDD = 3.6 V
fPLL = 48 MHz,
Subsystem clock
operation
Normal
operation
fCLK = 6 MHz Note 2
Normal
operation
fSUB = 32.768 kHz Note 4
TA = -40°C
Normal
operation
VDD = 3.0 V
2.3
3.9
Square wave input
4.6
6.9
Resonator connection
4.7
6.9
fSUB = 32.768 kHz Note 4 Normal
operation
TA = +25°C
Square wave input
4.9
7.0
Resonator connection
5.0
7.2
fSUB = 32.768 kHz Note 4 Normal
operation
TA = +50°C
Square wave input
5.2
7.6
Resonator connection
5.2
7.7
Normal
operation
Square wave input
5.5
9.3
Resonator connection
5.6
9.4
fSUB = 32.768 kHz Note 4 Normal
operation
TA = +85°C
Square wave input
6.2
13.3
Resonator connection
6.2
13.4
Normal
operation
Square wave input
8.3
46.0
Resonator connection
8.4
46.0
fSUB = 32.768 kHz
TA = +70°C
fSUB = 32.768 kHz
TA = +105°C
Note 4
Note 4
mA
mA
μA
(Notes and Remarks are listed on the next page.)
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Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD, or
VSS. The values below the MAX. column include the peripheral operation current. However, not including the current
flowing into the LCD controller/driver, A/D converter, D/A converter, comparator, LVD circuit, USB 2.0 function module,
I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite.
When high-speed on-chip oscillator and subsystem clock are stopped.
When high-speed system clock and subsystem clock are stopped.
When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power
consumption oscillation). However, not including the current flowing into the real-time clock 2, 12-bit interval timer, and
watchdog timer.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 3.6 V@1 MHz to 24 MHz
2.4 V ≤ VDD ≤ 3.6 V@1 MHz to 16 MHz
Remark 1. fMX:
High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (48 MHz max.)
Remark 3. fIH:
Main system clock source frequency when the high-speed on-chip oscillator clock divided 1, 2, 4, or 8, or the PLL
clock divided by 2, 4, or 8 is selected (24 MHz max.)
Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 5. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
(TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
Supply
current
IDD2
HALT mode
Note 2
(2/2)
TYP.
MAX.
Unit
VDD = 3.6 V
MIN.
0.77
3.4
mA
VDD = 3.0 V
0.77
3.4
fHOCO = 24 MHz Note 4,
VDD = 3.6 V
0.55
2.7
fIH = 24 MHz Note 4
VDD = 3.0 V
0.55
2.7
fHOCO = 16 MHz Note 4,
VDD = 3.6 V
0.48
1.9
fIH = 16 MHz Note 4
VDD = 3.0 V
0.47
1.9
Square wave input
0.35
2.10
Resonator connection
0.51
2.20
fMX = 20 MHz Note 3,
VDD = 3.0 V
Square wave input
0.34
2.10
Resonator connection
0.51
2.20
Note 3,
Square wave input
0.30
1.25
Resonator connection
0.45
1.41
fMX = 16 MHz Note 3,
VDD = 3.0 V
Square wave input
0.29
1.23
Resonator connection
0.45
1.41
Note 3,
Square wave input
0.23
1.10
Resonator connection
0.30
1.20
fMX = 10 MHz Note 3,
VDD = 3.0 V
Square wave input
0.22
1.10
Resonator connection
0.30
1.20
fMX = 48 MHz,
VDD = 3.6 V
0.99
2.93
fCLK = 24 MHz Note 3
VDD = 3.0 V
0.99
2.92
fMX = 48 MHz,
VDD = 3.6 V
0.89
2.51
fCLK = 12 MHz Note 3
VDD = 3.0 V
0.89
2.50
fMX = 48 MHz,
VDD = 3.6 V
0.84
2.30
fCLK = 6 MHz Note 3
VDD = 3.0 V
0.84
2.29
fSUB = 32.768 kHz Note 5 Square wave input
TA = -40°C
Resonator connection
0.32
0.61
0.51
0.80
fSUB = 32.768 kHz Note 5 Square wave input
TA = +25°C
Resonator connection
0.41
0.74
0.62
0.91
fSUB = 32.768 kHz Note 5 Square wave input
TA = +50°C
Resonator connection
0.52
2.30
0.75
2.49
Square wave input
0.82
4.03
Resonator connection
1.08
4.22
fSUB = 32.768 kHz Note 5 Square wave input
TA = +85°C
Resonator connection
1.38
8.04
1.62
8.23
Square wave input
3.29
41.00
Resonator connection
3.63
41.00
TA = -40°C
0.18
0.52
TA = +25°C
0.25
0.52
TA = +50°C
0.34
2.21
TA = +70°C
0.64
3.94
TA = +85°C
1.18
7.95
TA = +105°C
2.92
40.00
HS (high-speed main) fHOCO = 48 MHz Note 4,
mode Note 7
fIH = 24 MHz Note 4
Note 1
HS (high-speed main) fMX = 20 MHz
VDD = 3.6 V
mode Note 7
fMX = 16 MHz
VDD = 3.6 V
fMX = 10 MHz
VDD = 3.6 V
HS
(High-speed main)
mode
(PLL operation)
Subsystem clock
operation
Note 3,
fSUB = 32.768 kHz
TA = +70°C
fSUB = 32.768 kHz
TA = +105°C
IDD3
STOP mode
Note 6
Note 8
Note 5
Note 5
mA
mA
μA
μA
(Notes and Remarks are listed on the next page.)
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RL78/L1C
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Note 7.
Note 8.
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or
VSS. The values below the MAX. column include the peripheral operation current. However, not including the current
flowing into the LCD controller/driver, A/D converter, D/A converter, comparator, LVD circuit, USB 2.0 function module,
I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite.
During HALT instruction execution by flash memory.
When high-speed on-chip oscillator and subsystem clock are stopped.
When high-speed system clock and subsystem clock are stopped.
When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low
current consumption (AMPHS1 = 1). The current flowing into the real-time clock 2 is included. However, not including the
current flowing into the 12-bit interval timer and watchdog timer.
Not including the current flowing into the real-time clock 2, 12-bit interval timer, and watchdog timer.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 3.6 V@1 MHz to 24 MHz
2.4 V ≤ VDD ≤ 3.6 V@1 MHz to 16 MHz
Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode.
Remark 1. fMX:
High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (48 MHz max.)
Remark 3. fIH:
Main system clock source frequency when the high-speed on-chip oscillator clock divided 1, 2, 4, or 8, or the PLL
clock divided by 2, 4, or 8 is selected (24 MHz max.)
Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 5. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
(TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Low-speed
on-chip oscillator
operating current
RTC2 operating
current
12-bit interval
timer operating
current
Watchdog timer
operating current
A/D converter
operating current
AVREF (+) current
Symbol
Conditions
MIN.
IRTC
0.02
μA
0.02
μA
fIL = 15 kHz
0.22
μA
AVDD = 3.0 V, when conversion at maximum speed
422
720
μA
14.0
25.0
μA
14.0
25.0
14.0
25.0
Notes 1, 3
ITMKA
Notes 1, 2, 4
IWDT
Notes 1, 2, 5
IADC
Notes 6, 7
IAVREF Note 8 AVDD = 3.0 V, ADREFP1 = 0, ADREFP0 = 0 Note 7
IADREF
Note 1
VDD = 3.0 V
75.0
μA
78
μA
Notes 1, 9
Temperature
sensor operating
current
ITMPS Note 1
D/A converter
operating current
IDAC
Per D/A converter channel
0.53
1.5
mA
VDD = 3.6 V,
Regulator output
voltage = 2.1 V
Window mode
12.5
μA
Comparator high-speed mode
4.5
μA
Notes 1, 11
ICMP
Notes 1, 12
Comparator low-speed mode
LVD operating
current
Unit
μA
ADREFP1 = 1, ADREFP0 = 0
Comparator
operating current
MAX.
0.20
AVREFP = 3.0 V, ADREFP1 = 0, ADREFP0 = 1 Note 10
A/D converter
reference voltage
current
TYP.
IFIL Note 1
ILVD
1.2
μA
0.06
μA
Notes 1, 13
Self-programming IFSP
operating current Notes 1, 14
2.50
12.20
mA
BGO operating
current
1.68
12.20
mA
The mode is performed Note 16
0.34
1.10
mA
The A/D conversion operations are performed, Low voltage
mode, AVREFP = VDD = 3.0 V
0.53
2.04
0.70
1.54
IBGO
Notes 1, 15
SNOOZE
operating current
ISNOZ Note 1
LCD operating
current
ILCD1
ADC operation
CSI/UART operation
fLCD = fSUB
LCD clock = 128 Hz
1/3 bias
4-time slice
VDD = 3.6 V,
LV4 = 3.6 V
0.14
μA
Internal voltage
boosting method
fLCD = fSUB
LCD clock = 128 Hz
1/3 bias
4-time slice
VDD = 3.0 V,
LV4 = 3.0 V
(VLCD = 04H)
0.61
μA
Capacitor split
method
fLCD = fSUB
LCD clock = 128 Hz
1/3 bias
4-time slice
VDD = 3.0 V,
LV4 = 3.0 V
0.12
μA
Note 17
IUSB Note 20
Operating current during USB communication
4.88
mA
IUSB Note 21
Operating current in the USB suspended state
0.04
mA
Notes 17, 18
ILCD2
Note 17
ILCD3
USB current
Note 19
mA
External
resistance
division method
(Notes and Remarks are listed on the next page.)
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RL78/L1C
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Note 7.
Note 8.
Note 9.
Note 10.
Note 11.
Note 12.
Note 13.
Note 14.
Note 15.
Note 16.
Note 17.
Note 18.
Note 19.
Note 20.
Note 21.
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
Current flowing to VDD.
When high speed on-chip oscillator and high-speed system clock are stopped.
Current flowing only to the real-time clock 2 (excluding the operating current of the low-speed on-chip oscillator and the
XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IRTC,
when the real-time clock 2 operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected,
IFIL should be added. IDD2 subsystem clock operation includes the operational current of the real-time clock 2.
Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and
the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and
ITMKA, when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is
selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of the 12-bit interval
timer.
Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The
current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer operates in
STOP mode.
Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and
IADC, IAVREF, IADREF when the A/D converter operates in an operation mode or the HALT mode.
Current flowing to the AVDD.
Current flowing from the reference voltage source of A/D converter.
Operation current flowing to the internal reference voltage.
Current flowing to the AVREFP.
Current flowing only to the D/A converter. The current value of the RL78 microcontrollers is the sum of IDD1 or IDD2 and
IDA when the D/A converter operates in an operation mode or the HALT mode.
Current flowing only to the comparator circuit. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or
IDD3 and ICMP when the comparator circuit operates in the Operating, HALT or STOP mode.
Current flowing only to the LVD circuit. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and
ILVI when the LVD circuit operates in the Operating, HALT or STOP mode.
Current flowing only during self-programming.
Current flowing only during data flash rewrite.
For shift time to the SNOOZE mode, see 23.3.3 SNOOZE mode in the RL78/L1C User’s Manual..
Current flowing only to the LCD controller/driver (VDD pin). The current value of the RL78 microcontrollers is the sum of
the LCD operating current (ILCD1, ILCD2 or ILCD3) to the supply current (IDD1, or IDD2) when the LCD controller/driver
operates in an operation mode or HALT mode. Not including the current that flows through the LCD panel.
Not including the current that flows through the external divider resistor divider resistor.
Current flowing to the UVBUS.
Including the operating current when fPLL = 48 MHz.
Including the current supplied from the pull-up resistor of the UDP pin to the pull-down resistor of the host device, in
addition to the current consumed by this MCU during the suspended state.
Remark 1. fIL: Low-speed on-chip oscillator clock frequency
Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 3. fCLK: CPU/peripheral hardware clock frequency
Remark 4. Temperature condition of the TYP. value is TA = 25°C
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3.4
3.4.1
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
AC Characteristics
Basic operation
(TA = -40 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V)
Items
Instruction cycle
(minimum instruction
execution time)
External main system
clock frequency
Symbol
TCY
fEX
Conditions
MAX.
Unit
2.7 V ≤ VDD ≤ 3.6 V
0.0417
1
μs
2.4 V ≤ VDD < 2.7 V
0.0625
1
Subsystem clock (fSUB) operation
2.4 V ≤ VDD ≤ 3.6 V
28.5
In the selfHS (high-speed main)
programming mode
mode
2.7 V ≤ VDD ≤ 3.6 V
2.4 V ≤ VDD < 2.7 V
Main system
clock (fMAIN)
operation
HS (high-speed main)
mode
TI00 to TI07 input
high-level width,
low-level width
Remark
tEXH,
tEXL
tEXHS,
tEXLS
tTIH,
tTIL
MIN.
TYP.
30.5
μs
31.3
μs
0.0417
1
μs
0.0625
1
μs
2.7 V ≤ VDD ≤ 3.6 V
1.0
20.0
MHz
2.4 V ≤ VDD < 2.7 V
1.0
16.0
MHz
32
35
kHz
fEXT
External main system
clock input high-level
width, low-level width
(1/2)
2.7 V ≤ VDD ≤ 3.6 V
2.4 V ≤ VDD < 2.7 V
24
ns
30
ns
13.7
μs
1/fMCK +
10
ns
fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of timer mode register mn (TMRmn). m: Unit number (m = 0),
n: Channel number (n = 0 to 7))
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
(TA = -40 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V)
Items
Symbol
Conditions
TO00 to TO07, TKBO00,
TKBO01, TKBO10, TKBO11,
TKBO20, TKBO21
output frequency
fTO
PCLBUZ0, PCLBUZ1 output
frequency
fPCL
Interrupt input high-level width,
low-level width
tINTH,
tINTL
INTP0 to INTP7
Key interrupt input low-level
width
tKR
2.4 V ≤ VDD ≤ 3.6 V
TMKB2 forced output stop input tIHR
high-level width
RESET low-level width
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tRSL
(2/2)
HS (high-speed main) mode
HS (high-speed main) mode
INTP0 to INTP7
MIN.
TYP.
MAX.
Unit
2.7 V ≤ VDD ≤ 3.6 V
8
MHz
2.4 V ≤ VDD < 2.7 V
8
MHz
2.7 V ≤ VDD ≤ 3.6 V
8
MHz
2.4 V ≤ VDD < 2.7 V
8
MHz
2.4 V ≤ VDD ≤ 3.6 V
1
μs
250
ns
fCLK > 16 MHz
125
ns
fCLK ≤ 16 MHz
2
fCLK
10
μs
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
Minimum Instruction Execution Time during Main System Clock Operation
TCY vs VDD (HS (high-speed main) mode)
10
1.0
Cycle time TCY [µs]
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
0.1
0.0625
0.05
0.0417
0.01
0
1.0
4.0
2.0
3.0
2.4 2.7 3.6
5.0
6.0
Supply voltage VDD [V]
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
AC Timing Test Points
VIH/VOH
VIH/VOH
Test points
VIL/VOL
VIL/VOL
External System Clock Timing
1/fEX
1/fEXS
tEXL
tEXLS
tEXH
tEXHS
EXCLK/EXCLKS
TI/TO Timing
tTIL
tTIH
TI00 to TI07, TI10 to TI17
1/fTO
TO00 to TO07, TO10 to TO17,
TKBO00, TKBO01,
TKBO10, TKBO11,
TKBO20, TKBO21
Interrupt Request Input Timing
tINTL
tINTH
INTP0 to INTP7
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
Key Interrupt Input Timing
tKR
KR0 to KR7
Timer KB2 Input Timing
tIHR
INTP0 to INTP7
RESET Input Timing
tRSL
RESET
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3.5
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
Peripheral Functions Characteristics
VIH/VOH
VIH/VOH
Test points
VIL/VOL
VIL/VOL
3.5.1
Serial array unit
(1) During communication at same potential (UART mode)
(TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
Transfer rate Note 1
HS (high-speed main) Mode
Conditions
MIN.
2.4 V ≤ VDD ≤ 3.6 V
Theoretical value of the maximum transfer rate
Unit
MAX.
fMCK/12 Note 2
bps
2.0
Mbps
fMCK = fCLK Note 3
Note 1.
Note 2.
Note 3.
Caution
Transfer rate in the SNOOZE mode is 4800 bps only.
The following conditions are required for low voltage interface.
2.4 V ≤ VDD < 2.7 V: MAX. 1.3 Mbps
The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 3.6 V)
16 MHz (2.4 V ≤ VDD ≤ 3.6 V)
Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
UART mode connection diagram (during communication at same potential)
TxDq
Rx
RL78 microcontroller
User’s device
RxDq
Tx
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Remark 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0 to 3)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
2.7 V ≤ VDD ≤ 3.6 V
HS (high-speed main) Mode
MIN.
MAX.
Unit
SCKp cycle time
tKCY1
tKCY1 ≥ fCLK/4
SCKp high-/low-level width
tKH1, tKL1
2.7 V ≤ VDD ≤ 3.6 V
2.4 V ≤ VDD ≤ 3.6 V
tKCY1/2 - 76
ns
SIp setup time (to SCKp↑) Note 1
tSIK1
2.7 V ≤ VDD ≤ 3.6 V
66
ns
2.4 V ≤ VDD ≤ 3.6 V
133
ns
38
ns
2.4 V ≤ VDD ≤ 3.6 V
SIp hold time (from SCKp↑)
Note 2
Delay time from SCKp↓ to SOp output Note 3
Note 1.
Note 2.
Note 3.
Note 4.
Caution
tKSI1
tKSO1
250
ns
500
ns
tKCY1/2 - 36
ns
C = 30 pF Note 4
50
ns
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
C is the load capacitance of the SCKp and SOp output lines.
Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 10, 20, 30), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM number (g = 0 to 3)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
tKCY2
SCKp cycle time Note 5
Conditions
2.7 V ≤ VDD < 3.6 V
fMCK > 16 MHz
fMCK ≤ 16 MHz
tKH2, tKL2
SCKp high-/low-level width
tSIK2
SIp setup time (to SCKp↑) Note 1
Delay time from SCKp↓ to SOp output
Note 3
tKSO2
MIN.
MAX.
16/fMCK
Unit
ns
12/fMCK
ns
2.4 V ≤ VDD < 3.6 V
12/fMCK and 1000
ns
2.7 V ≤ VDD ≤ 3.6 V
tKCY2/2 - 16
ns
2.4 V ≤ VDD ≤ 3.6 V
tKCY2/2 - 36
ns
2.7 V ≤ VDD ≤ 3.6 V
1/fMCK + 40
ns
2.4 V ≤ VDD ≤ 3.6 V
1/fMCK + 60
ns
1/fMCK + 62
ns
tKSI2
SIp hold time (from SCKp↑) Note 2
HS (high-speed main) Mode
C = 30 pF
Note 4
2.7 V ≤ VDD ≤ 3.6 V
2/fMCK + 66
ns
2.4 V ≤ VDD < 3.6 V
2/fMCK + 113
ns
Note 5.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
C is the load capacitance of the SOp output lines.
The maximum transfer rate when using the SNOOZE mode is 1 Mbps.
Caution
Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin by using port input
Note 1.
Note 2.
Note 3.
Note 4.
mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 10, 20, 30), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM number (g = 0 to 3)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
CSI mode connection diagram (during communication at same potential)
SCKp
RL78 microcontroller
SIp
SOp
SCK
SO
User's device
SI
Remark 1. p: CSI number (p = 00, 10, 20, 30)
Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1, 2
tKH1, 2
tKL1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Output data
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1, 2
tKL1, 2
tKH1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Output data
Remark 1. p: CSI number (p = 00, 10, 20, 30)
Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
(4) During communication at same potential (simplified I2C mode)
(TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
SCLr clock frequency
fSCL
Hold time when SCLr = “L”
tLOW
Hold time when SCLr = “H”
tHIGH
Data setup time (reception)
tSU: DAT
Data hold time (transmission)
Note 1.
Note 2.
Caution
HS (high-speed main) Mode
Conditions
tHD: DAT
MIN.
MAX.
Unit
2.7 V ≤ VDD ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
400 Note 1
kHz
2.4 V ≤ VDD ≤ 3.6 V,
Cb = 100 pF, Rb = 3 kΩ
100 Note 1
kHz
2.7 V ≤ VDD ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
1200
ns
2.4 V ≤ VDD ≤ 3.6 V,
Cb = 100 pF, Rb = 3 kΩ
4600
ns
2.7 V ≤ VDD ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
1200
ns
2.4 V ≤ VDD ≤ 3.6 V,
Cb = 100 pF, Rb = 3 kΩ
4600
ns
2.7 V ≤ VDD ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK + 200 Note 2
ns
2.4 V ≤ VDD ≤ 3.6 V,
Cb = 100 pF, Rb = 3 kΩ
1/fMCK + 580 Note 2
ns
2.7 V ≤ VDD ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
0
770
ns
2.4 V ≤ VDD ≤ 3.6 V,
Cb = 100 pF, Rb = 3 kΩ
0
1420
ns
The value must be equal to or less than fMCK/4.
Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Select the normal input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the
normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h
(POMh).
Simplified I2C mode connection diagram (during communication at same potential)
VDD
Rb
SDAr
SDA
RL78 microcontroller
SCLr
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SCL
Page 113 of 147
RL78/L1C
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
Simplified I2C mode serial transfer timing (during communication at same potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD: DAT
tSU: DAT
Remark 1. Rb[Ω]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance
Remark 2. r: IIC number (r = 00, 10, 20, 30), g: PIM number (g = 0 to 3),
h: POM number (h = 0 to 3)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13)
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(5) Communication at different potential (1.8 V, 2.5 V) (UART mode)
(TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
Transfer rate Notes 1, 2
Conditions
Reception
(1/2)
HS (high-speed main) Mode
MIN.
2.7 V ≤ VDD ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V
MAX.
Unit
fMCK/12 Note 1
bps
2.0
Mbps
fMCK/12 Notes 1, 2, 3
bps
1.3
Mbps
Theoretical value of the maximum transfer rate
fMCK = fCLK Note 4
1.8 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Theoretical value of the maximum transfer rate
fMCK = fCLK Note 4
Note 1.
Note 2.
Note 3.
Note 4.
Caution
Transfer rate in the SNOOZE mode is 4,800 bps only.
Use it with VDD ≥ Vb.
The following conditions are required for low voltage interface.
2.4 V ≤ VDD < 2.7 V:
MAX. 2.6 Mbps
The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 3.6 V)
16 MHz (2.4 V ≤ VDD ≤ 3.6 V)
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq
pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the
DC characteristics with TTL input buffer selected.
Remark 1. Vb[V]: Communication line voltage
Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0 to 3)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
(5) Communication at different potential (1.8 V, 2.5V) (UART mode)
(TA = -40 to +105°C, 2.4 ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Transfer rate Note 2
Symbol
(2/2)
HS (high-speed main) Mode
Conditions
MIN.
MAX.
Transmission 2.7 V ≤ VDD ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V
Theoretical value of the maximum transfer rate
Cb = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V
1.8 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Theoretical value of the maximum transfer rate
Cb = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V
Note 1.
Unit
Note 1
bps
1.2 Note 2
Mbps
Notes 3, 4
bps
0.43 Note 5
Mbps
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ VDD < 3.6 V and 2.3 V ≤ Vb ≤ 2.7 V
1
Maximum transfer rate =
2.0
{-Cb × Rb × In (1 Vb
[bps]
)} × 3
1
Transfer rate × 2
- {-Cb × Rb × In (1 -
2.0
Vb
)}
× 100 [%]
Baud rate error (theoretical value) =
(
1
Transfer rate
) × Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
Note 2.
Note 3.
Note 4.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
Use it with VDD ≥ Vb.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate.
Expression for calculating the transfer rate when 2.4 V ≤ VDD < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V
1
Maximum transfer rate =
1.5
{-Cb × Rb × In (1 Vb
[bps]
)} × 3
1
Transfer rate × 2
- {-Cb × Rb × In (1 -
1.5
Vb
)}
× 100 [%]
Baud rate error (theoretical value) =
(
1
Transfer rate
) × Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
Note 5.
Caution
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer.
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq
pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the
DC characteristics with TTL input buffer selected.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
UART mode connection diagram (during communication at different potential)
Vb
Rb
TxDq
Rx
RL78 microcontroller
User’s device
RxDq
Tx
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Remark 1. Rb[Ω]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance,
Vb[V]: Communication line voltage
Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0 to 3)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
(6) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
SCKp cycle time
SCKp high-level width
SCKp low-level width
Note
Caution
Symbol
tKCY1
tKH1
tKL1
Conditions
tKCY1 ≥ fCLK/4
(1/2)
HS (high-speed main) Mode
MIN.
MAX.
Unit
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1000 Note
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 1.8 V,
Cb = 30 pF, Rb = 5.5 kΩ
2300 Note
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
tKCY1/2 - 340
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
tKCY1/2 - 916
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
tKCY1/2 - 36
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
tKCY1/2 - 100
ns
Use it with VDD ≥ Vb.
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin
and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and
VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the page after the next page.)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
(6) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
(2/2)
Conditions
HS (high-speed main)
Mode
MIN.
SIp setup time (to SCKp↑) Note 1
SIp hold time (from SCKp↑) Note 1
Delay time from SCKp↓ to SOp output Note 1
SIp setup time (to SCKp↓) Note 2
SIp hold time (from SCKp↓) Note 2
Delay time from SCKp↑ to SOp output Note 2
Note 1.
Note 2.
Note 3.
Caution
tSIK1
tKSI1
tKSO1
tSIK1
tKSI1
tKSO1
Unit
MAX.
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
354
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
958
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
38
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
38
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
390
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
966
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
88
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
220
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
38
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
38
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
50
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
50
ns
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Use it with VDD ≥ Vb.
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin
and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and
VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
CSI mode connection diagram (during communication at different potential)
Vb
Vb
Rb
SCKp
RL78 microcontroller
Rb
SCK
SIp
SO
SOp
SI
User’s device
Remark 1. Rb[Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 10, 20, 30), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0 to 3)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
tKSI1
Input data
SIp
tKSO1
Output data
SOp
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1
tKH1
tKL1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
Remark
Output data
p: CSI number (p = 00, 10, 20, 30), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0 to 3)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
(7) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (slave mode, SCKp... external clock input)
(TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
SCKp cycle time Note 1
SCKp high-/low-level width
Symbol
tKCY2
tKH2, tKL2
2.7 V ≤ VDD ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V
tSIK2
SIp hold time (from SCKp↑) Note 4
tKSI2
Delay time from SCKp↓ to SOp output Note 5
tKSO2
MIN.
Note 2.
Note 3.
Note 4.
Note 5.
Caution
Unit
32/fMCK
ns
16 MHz < fMCK ≤ 20 MHz
28/fMCK
ns
8 MHz < fMCK ≤ 16 MHz
24/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK
ns
fMCK ≤ 4 MHz
12/fMCK
ns
2.4 V ≤ VDD < 3.3 V,
20 MHz < fMCK ≤ 24 MHz
72/fMCK
ns
1.6 V ≤ Vb ≤ 2.0 V Note 2
16 MHz < fMCK ≤ 20 MHz
64/fMCK
ns
8 MHz < fMCK ≤ 16 MHz
52/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
32/fMCK
ns
fMCK ≤ 4 MHz
20/fMCK
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V
Note 2
2.7 V ≤ VDD ≤ 3.6 V
2.4 V ≤ VDD < 3.3 V
Note 1.
MAX.
20 MHz < fMCK ≤ 24 MHz
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
SIp setup time (to SCKp↑) Note 3
HS (high-speed main) Mode
Conditions
tKCY2/2 - 36
ns
tKCY2/2 - 100
ns
1/fMCK + 40
ns
1/fMCK + 60
ns
1/fMCK + 62
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V
Cb = 30 pF, Rb = 2.7 kΩ
2/fMCK + 428
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2
Cb = 30 pF, Rb = 5.5 kΩ
2/fMCK + 1146
ns
Transfer rate in the SNOOZE mode: MAX. 1 Mbps
Use it with VDD ≥ Vb.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance) mode for
the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL,
see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
CSI mode connection diagram (during communication at different potential)
Vb
Rb
SCKp
RL78 microcontroller
SCK
SIp
SO
SOp
SI
User’s device
Remark 1. Rb[Ω]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 10, 20, 30), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0 to 3)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 02, 10, 12))
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY2
tKL2
tKH2
SCKp
tSIK2
tKSI2
Input data
SIp
tKSO2
SOp
Output data
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY2
tKH2
tKL2
SCKp
tSIK2
SIp
tKSI2
Input data
tKSO2
SOp
Remark
Output data
p: CSI number (p = 00, 10, 20, 30), m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3), g: PIM and POM number (g = 0 to 3)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
(8) Communication at different potential (1.8 V, 2.5 V) (simplified I2C mode)
(TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
SCLr clock frequency
Hold time when SCLr = “L”
Hold time when SCLr = “H”
Data setup time (reception)
Data hold time (transmission)
Symbol
fSCL
tLOW
tHIGH
tSU:DAT
tHD:DAT
HS (high-speed main) Mode
Conditions
MIN.
MAX.
Unit
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
400 Note 1
kHz
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
100 Note 1
kHz
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
100 Note 1
kHz
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
1200
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb 50 mV/μs mode, standard mode
1.2
μs
High-speed comparator
mode, window mode
2.0
μs
5.0
μs
Low-speed comparator mode,
standard mode
3
High-electric-potential VTW+
judgment voltage
High-speed comparator mode, window mode
0.76 VDD
V
Low-electric-potential
judgment voltage
High-speed comparator mode, window mode
0.24 VDD
V
VTW-
100
Operation stabilization tCMP
wait time
Internal reference
VBGR
2.4 V ≤ VDD ≤ 3.6 V, HS (high-speed main) mode
1.38
μs
1.45
1.50
V
voltage Note
Note
3.6.5
Not usable in sub-clock operation or STOP mode.
POR circuit characteristics
(TA = -40 to +105°C, VSS = 0 V)
Parameter
Detection voltage
Symbol
VPOR
VPDR
Minimum pulse width
Note
Conditions
Power supply rise time
Power supply fall time
Note
TPW
MIN.
TYP.
MAX.
Unit
1.45
1.51
1.57
V
1.44
1.50
1.56
V
300
μs
Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a
POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main
system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register
(CSC).
TPW
Supply voltage (VDD)
VPOR
VPDR or 0.7 V
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3.6.6
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
LVD circuit characteristics
(TA = -40 to +105°C, VPDR ≤ VDD ≤ 3.6 V ≤ VSS = 0 V)
Parameter
Detection voltage
Supply voltage level
Symbol
TYP.
MAX.
Unit
Power supply rise time
3.01
3.13
3.25
V
Power supply fall time
2.94
3.06
3.18
V
VLVD3
Power supply rise time
2.90
3.02
3.14
V
Power supply fall time
2.85
2.96
3.07
V
Power supply rise time
2.81
2.92
3.03
V
Power supply fall time
2.75
2.86
2.97
V
Power supply rise time
2.71
2.81
2.92
V
Power supply fall time
2.64
2.75
2.86
V
Power supply rise time
2.61
2.71
2.81
V
Power supply fall time
2.55
2.65
2.75
V
Power supply rise time
2.51
2.61
2.71
V
Power supply fall time
2.45
2.55
2.65
V
VLVD5
VLVD6
VLVD7
tLW
Detection delay time
Caution
MIN.
VLVD2
VLVD4
Minimum pulse width
Conditions
300
μs
300
μs
Set the detection voltage (VLVD) to be within the operating voltage range. The operating voltage range depends
on the setting of the user option byte (000C2H/010C2H). The following shows the operating voltage range.
HS (high-speed main) mode: VDD = 2.7 to 3.6 V at 1 MHz to 24 MHz
VDD = 2.4 to 3.6 V at 1 MHz to 16 MHz
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
LVD Detection Voltage of Interrupt & Reset Mode
(TA = -40 to +105°C, VPDR ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Interrupt and reset mode
Symbol
VLVDD0
Conditions
MIN.
TYP.
MAX.
Unit
2.64
2.75
2.86
V
Rising release reset voltage
2.81
2.92
3.03
V
Falling interrupt voltage
2.75
2.86
2.97
V
VPOC0, VPOC1, VPOC2 = 0, 1, 1, falling reset voltage: 2.7 V
VLVDD1
LVIS0, LVIS1 = 1, 0
VLVDD2
LVIS0, LVIS1 = 0, 1 Rising release reset voltage
Falling interrupt voltage
3.7
2.90
3.02
3.14
V
2.85
2.96
3.07
V
Power supply voltage rising slope characteristics
(TA = -40 to +105°C, VSS = 0 V)
Parameter
Power supply voltage rising slope
Caution
Conditions
SVDD
MIN.
TYP.
MAX.
Unit
54
V/ms
Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating
voltage range shown in 3.4 AC Characteristics.
R01DS0192EJ0220 Rev.2.20
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Page 138 of 147
RL78/L1C
3.8
3.8.1
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
LCD Characteristics
Resistance division method
(1) Static display mode
(TA = -40 to +105°C, VL4 (MIN.) ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
LCD drive voltage
Symbol
Conditions
VL4
MIN.
TYP.
2.0
MAX.
Unit
VDD
V
MAX.
Unit
VDD
V
MAX.
Unit
VDD
V
(2) 1/2 bias method, 1/4 bias method
(TA = -40 to +105°C, VL4 (MIN.) ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
LCD drive voltage
Symbol
Conditions
VL4
MIN.
TYP.
2.7
(3) 1/3 bias method
(TA = -40 to +105°C, VL4 (MIN.) ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
LCD drive voltage
Symbol
VL4
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Conditions
MIN.
2.5
TYP.
Page 139 of 147
RL78/L1C
3.8.2
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
Internal voltage boosting method
(1) 1/3 bias method
(TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
LCD output voltage variation range
Symbol
VL1
Conditions
C1 to C4
Note 1
= 0.47 μF
Note 2
MIN.
TYP.
MAX.
Unit
VLCD = 04H
0.90
1.00
1.08
V
VLCD = 05H
0.95
1.05
1.13
V
VLCD = 06H
1.00
1.10
1.18
V
VLCD = 07H
1.05
1.15
1.23
V
VLCD = 08H
1.10
1.20
1.28
V
VLCD = 09H
1.15
1.25
1.33
V
VLCD = 0AH
1.20
1.30
1.38
V
VLCD = 0BH
1.25
1.35
1.43
V
VLCD = 0CH
1.30
1.40
1.48
V
VLCD = 0DH
1.35
1.45
1.53
V
VLCD = 0EH
1.40
1.50
1.58
V
VLCD = 0FH
1.45
1.55
1.63
V
VLCD = 10H
1.50
1.60
1.68
V
VLCD = 11H
1.55
1.65
1.73
V
VLCD = 12H
1.60
1.70
1.78
V
VLCD = 13H
1.65
1.75
1.83
V
= 0.47 μF
2 VL1 - 0.1
2 VL1
2 VL1
V
C1 to C4Note 1 = 0.47 μF
3 VL1 - 0.15
3 VL1
3 VL1
V
Doubler output voltage
VL2
C1 to
Tripler output voltage
VL3
Reference voltage setup time Note 2
tVWAIT1
Voltage boost wait time Note 3
tVWAIT2
Note 1.
Note 2.
Note 3.
C4Note 1
C1 to C4Note 1 = 0.47μF
5
ms
500
ms
This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = 0.47 μF±30%
This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the
internal voltage boosting method is selected (by setting the MDSET1 and MDSET0 bits of the LCDM0 register to 01B) if
the default value reference voltage is used) until voltage boosting starts (VLCON = 1).
This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 140 of 147
RL78/L1C
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
(2) 1/4 bias method
(TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
LCD output voltage variation range
VL1
Conditions
C1 to C4
Note 1
= 0.47 μF
Doubler output voltage
VL2
Tripler output voltage
VL3
Quadruply output voltage
VL4
Reference voltage setup time
Voltage boost wait time
Note 1.
Note 2.
Note 3.
Note 2
Note 3
Note 2
MIN.
TYP.
MAX.
Unit
VLCD = 04H
0.90
1.00
1.08
V
VLCD = 05H
0.95
1.05
1.13
V
VLCD = 06H
1.00
1.10
1.18
V
VLCD = 07H
1.05
1.15
1.23
V
VLCD = 08H
1.10
1.20
1.28
V
VLCD = 09H
1.15
1.25
1.33
V
VLCD = 0AH
1.20
1.30
1.38
V
C1 to C4
Note 1
= 0.47 μF
2 VL1 - 0.08
2 VL1
2 VL1
V
C1 to C4
Note 1
= 0.47 μF
3 VL1 - 0.12
3 VL1
3 VL1
V
C1 to C5
Note 1
= 0.47 μF
4 VL1 - 0.16
4 VL1
4 VL1
V
C1 to C5
Note 1
tVWAIT1
tVWAIT2
= 0.47μF
5
ms
500
ms
This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL3 and GND
C5: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = 0.47 μF±30%
This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the
internal voltage boosting method is selected (by setting the MDSET1 and MDSET0 bits of the LCDM0 register to 01B) if
the default value reference voltage is used) until voltage boosting starts (VLCON = 1).
This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 141 of 147
RL78/L1C
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
3.8.3
Capacitor split method
(1) 1/3 bias method
(TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VL4 voltage
VL4
C1 to C4 = 0.47 μF
VL2 voltage
VL2
C1 to C4 = 0.47 μF Note 2
2/3 VL4 - 0.07
2/3 VL4
2/3 VL4 + 0.07
V
VL1 voltage
VL1
C1 to C4 = 0.47 μF Note 2
1/3 VL4 - 0.08
1/3 VL4
1/3 VL4 + 0.08
V
Capacitor split wait time Note 1
tVWAIT
Note 1.
Note 2.
3.9
VDD
Note 2
V
100
ms
This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1).
This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = 0.47 μF±30%
RAM Data Retention Characteristics
(TA = -40 to +105°C, VSS = 0 V)
Parameter
Data retention supply
voltage
Note
Symbol
Conditions
MIN.
TYP.
1.44 Note
VDDDR
MAX.
Unit
3.6
V
This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage reaches the
level that triggers a POR reset but not once it reaches the level at which a POR reset is generated.
STOP mode
Operation mode
RAM data retention mode
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 142 of 147
RL78/L1C
3.10
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
Flash Memory Programming Characteristics
(TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
CPU/peripheral hardware clock
frequency
fCLK
2.4 V ≤ VDD ≤ 3.6 V
Number of code flash rewrites
Cerwr
Retained for 20 years
Notes 1, 2, 3
TA = 85°CNote 4
Number of data flash rewrites
Retained for 1 year
TA = 25°C
Notes 1, 2, 3
Retained for 5 years
TA = 85°CNote 4
Retained for 20 years
TA =
Note 1.
Note 2.
Note 3.
Note 4.
3.11
MIN.
TYP.
1
MAX.
Unit
24
MHz
Times
1,000
1,000,000
100,000
10,000
85°CNote 4
1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite.
When using flash memory programmer and Renesas Electronics self programming library
These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics
Corporation.
This temperature is the average value at which data are retained.
Dedicated Flash Memory Programmer Communication (UART)
(TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Transfer rate
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Symbol
Conditions
During serial programming
MIN.
115,200
TYP.
MAX.
Unit
1,000,000
bps
Page 143 of 147
RL78/L1C
3.12
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105°C)
Timing of Entry to Flash Memory Programming Modes
(TA = -40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
How long from when an external reset ends until the
initial communication settings are specified
tSUINIT
POR and LVD reset must end
before the external reset ends.
How long from when the TOOL0 pin is placed at the
low level until an external reset ends
tSU
POR and LVD reset must end
before the external reset ends.
10
μs
Time to hold the TOOL0 pin at the low level after an
external reset is released (excluding the processing
time of the firmware to control the flash memory)
tHD
POR and LVD reset must end
before the external reset ends.
1
ms
Conditions
MIN.
TYP.
MAX.
Unit
100
ms
RESET
723 µs + tHD
processing
time
1-byte data for setting mode
TOOL0
tSU
tSUINIT
The low level is input to the TOOL0 pin.
The external reset ends (POR and LVD reset must end before the external reset ends.).
The TOOL0 pin is set to the high level.
Setting of the flash memory programming mode by UART reception and complete the baud rate setting.
Remark
tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from
when the resets end.
tSU:
How long from when the TOOL0 pin is placed at the low level until a external reset ends
tHD:
How long to keep the TOOL0 pin at the low level from when the external and internal resets end (except soft
processing time)
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
Page 144 of 147
RL78/L1C
4. PACKAGE DRAWINGS
4. PACKAGE DRAWINGS
4.1
80-pin products
R5F110MEAFB, R5F110MFAFB, R5F110MGAFB, R5F110MHAFB, R5F110MJAFB
R5F111MEAFB, R5F111MFAFB, R5F111MGAFB, R5F111MHAFB, R5F111MJAFB
R5F110MEGFB, R5F110MFGFB, R5F110MGGFB, R5F110MHGFB, R5F110MJGFB
R5F111MEGFB, R5F111MFGFB, R5F111MGGFB, R5F111MHGFB, R5F111MJGFB
JEITA Package Code
P-LFQFP80-12x12-0.50
RENESAS Code
PLQP0080KB-A
Previous Code
80P6Q-A
MASS[Typ.]
0.5g
HD
*1
D
60
41
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
40
61
bp
E
c
*2
HE
c1
b1
Reference Dimension in Millimeters
Symbol
ZE
Terminal cross section
80
21
1
20
ZD
Index mark
F
bp
c
A
*3
A1
y S
e
A2
S
L
x
L1
Detail F
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
e
x
y
ZD
ZE
L
L1
Min Nom Max
11.9 12.0 12.1
11.9 12.0 12.1
1.4
13.8 14.0 14.2
13.8 14.0 14.2
1.7
0.1 0.2
0
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
10°
0.5
0.08
0.08
1.25
1.25
0.3 0.5 0.7
1.0
Page 145 of 147
RL78/L1C
4.2
4. PACKAGE DRAWINGS
85-pin products
R5F110NEALA, R5F110NFALA, R5F110NGALA, R5F110NHALA, R5F110NJALA
R5F111NEALA, R5F111NFALA, R5F111NGALA, R5F111NHALA, R5F111NJALA
R5F110NEGLA, R5F110NFGLA, R5F110NGGLA, R5F110NHGLA, R5F110NJGLA
R5F111NEGLA, R5F111NFGLA, R5F111NGGLA, R5F111NHGLA, R5F111NJGLA
JEITA Package code
RENESAS code
Previous code
MASS(TYP.)[g]
P-VFLGA85-7x7-0.65
PVLG0085JA-A
P85FC-65-BN4
0.1
E
w S B
DETAIL A
D
b
(LAND SIZE)
0.45±0.05
(SR OPENING SIZE)
INDEX AREA
w S
y1 S
A
A
S
y
Referance
Symbol
S
A
B
ZE
Dimension in Millimeters
Min
Nom
Max
D
6.90
7.00
7.10
E
6.90
7.00
7.10
A
A
1.00
e
K
J
H
G
ZD
F
E
D
C
b
0.65
0.30
0.35
0.40
x
0.08
y
0.10
y1
0.20
ZD
0.575
ZE
0.575
w
0.20
e
B
A
1 2 3 4 5 6 7 8 9 10
b
x
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
M
S AB
2013 Renesas Electronics Corporation. All rights reserved.
Page 146 of 147
RL78/L1C
4. PACKAGE DRAWINGS
4.3
100-pin products
R5F110PEAFB, R5F110PFAFB, R5F110PGAFB, R5F110PHAFB, R5F110PJAFB
R5F111PEAFB, R5F111PFAFB, R5F111PGAFB, R5F111PHAFB, R5F111PJAFB
R5F110PEGFB, R5F110PFGFB, R5F110PGGFB, R5F110PHGFB, R5F110PJGFB
R5F111PEGFB, R5F111PFGFB, R5F111PGGFB, R5F111PHGFB, R5F111PJGFB
JEITA Package Code
P-LFQFP100-14x14-0.50
RENESAS Code
PLQP0100KB-A
Previous Code
100P6Q-A / FP-100U / FP-100UV
MASS[Typ.]
0.6g
HD
*1
D
51
75
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
50
76
bp
c1
Reference
Symbol
c
E
*2
HE
b1
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
100
26
1
ZE
Terminal cross section
25
Index mark
ZD
F
y S
e
*3
bp
A1
c
A
A2
S
L
x
L1
Detail F
R01DS0192EJ0220 Rev.2.20
Dec 28, 2017
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.08
1.0
1.0
0.35 0.5 0.65
1.0
Page 147 of 147
REVISION HISTORY
Rev.
Date
RL78/L1C Datasheet
Description
Page
Summary
0.01
Oct 15, 2012
—
1.00
Nov 18, 2013
1, 2
Modification of 1.1 Features
3, 4
Modification of 1.2 Ordering Information
5 to 8
14 to 17
Modification of vectored interrupt sources in 1.6 Outline of Functions
Modification of operating ambient temperature in 1.6 Outline of Functions
19 to 21
Modification of description in tables in 2.1 Absolute Maximum Ratings
Modification of description in 2.2 Oscillator Characteristics
25
Modification of low-level output current in 2.3.1 Pin characteristics
26
Modification of error of high-level input voltage conditions in 2.3.1 Pin
characteristics
26
Modification of error of low-level input voltage conditions in 2.3.1 Pin
characteristics
27
Modification of low-level output voltage in 2.3.1 Pin characteristics
28
Modification of error of internal pull-up resistor conditions in 2.3.1 Pin
characteristics
29 to 34
Modification of 2.3.2 Supply current characteristics
35, 36
Modification of 2.4 AC Characteristics
37, 38
Addition of minimum instruction execution time during main system clock
operation
41 to 63
Addition of LS mode and LV mode characteristics in 2.5.1 Serial array unit
64 to 66
Addition of LS mode and LV mode characteristics in 2.5.2 Serial interface IICA
67, 68
69
70 to 75
Modification of conditions in 2.5.3 USB
Addition of (3) BC option standard in 2.5.3 USB
Addition of characteristics about conversion of internal reference voltage and
temperature sensor in 2.6.1 A/D converter characteristics
76
Addition of characteristic in 2.6.4 Comparator
76
Deletion of detection delay in 2.6.5 POR circuit characteristics
78
79 to 82
83
Modification of 2.7 Power supply voltage rising slope characteristics
Modification of 2.8 LCD Characteristics
Modification of 2.9 Data Memory STOP Mode Low Supply Voltage Data
Retention Characteristics
83
Modification of 2.10 Flash Memory Programming Characteristics
84
Addition of 2.12 Timing Specs for Switching Modes
85 to 144
Feb 21, 2014
Modification of package type in 1.3 Pin Configuration (Top View)
14 to 17
22, 23
2.00
First Edition issued
Addition of 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
All
Addition of 85-pin product information
All
Modification from 80-pin to 80/85-pin
All
Modification from x = M, P to x = M, N, P
All
Modification from high-accuracy real-time clock to real-time clock 2
All
Modification from RTC to RTC2
1
Modification of 1.1 Features
3
Modification of 1.2 Ordering Information
C-1
REVISION HISTORY
Rev.
Date
2.00
Feb 21, 2014
2.10
Aug 12, 2016
Description
Page
4
Modification of Figure 1 - 1 Part Number, Memory Size, and Package of
RL78/L1C
Modification of (1) Electrical specifications in 2.5.3 USB
82
Modification of note 1 in (1) 1/3 bias method in 2.8.2 Internal voltage boosting
method
130
Modification of (1) Electrical specifications in 3.5.3 USB
142
Modification of note 1 in (1) 1/3 bias method in 3.8.2 Internal voltage boosting
method
5
Addition of product name (RL78/L1C) and description (Top View) in 1.3.1 80-pin
products (with USB)
6
Addition of product name (RL78/L1C) and description (Top View) in 1.3.2 80-pin
products (without USB)
9
Addition of product name (RL78/L1C) and description (Top View) in 1.3.5 100-pin
products (with USB)
10
Addition of product name (RL78/L1C) and description (Top View) in 1.3.6 100-pin
products (without USB)
23
Modification of 1.6 Outline of Functions
Modification of description in Absolute Maximum Ratings (TA = 25°C)
26, 27
Modification of description in 2.3.1 Pin characteristics
39, 40
Modification of the graph for Minimum Instruction Execution Time during Main
System Clock Operation
72
Modification of conditions in (1) of 2.6.1 A/D converter characteristics
85
Modification of the title and note in 2.9 RAM Data Retention Characteristics
85
Modification of conditions in 2.10 Flash Memory Programming Characteristics
87
Modification of description in 3. ELECTRICAL SPECIFICATIONS (G:
INDUSTRIAL APPLICATIONS TA = -40 to +105 °C)
88, 90
Modification of description in Absolute Maximum Ratings (TA = 25°C)
93, 94, 96
Dec 28, 2017
Summary
69
17, 19
2.20
RL78/L1C Datasheet
Modification of description in 3.3.1 Pin characteristics
106
Modification of the graph for Minimum Instruction Execution Time during Main
System Clock Operation
144
Modification of the title and note in 3.9 RAM Data Retention Characteristics
145
Modification of conditions and addition of note 4 in 3.10 Flash Memory
Programming Characteristics
13
Modification of figure in 1.5.2 80/85-pin products (without USB)
17, 19
Modification of tables in 1.6 Outline of Functions
26, 27
Modification of table and note 3 in 2.3.1 Pin characteristics
85
Modification of figure in 2.12 Timing of Entry to Flash Memory Programming
Modes
89
Modification of table in 3.1 Absolute Maximum Ratings
92, 93
144
Modification of table and note 3 in 3.3.1 Pin characteristics
Modification of figure in 3.12 Timing of Entry to Flash Memory Programming
Modes
C-2
REVISION HISTORY
RL78/L1C Datasheet
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries
including the United States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
All trademarks and registered trademarks are the property of their respective owners.
C-3
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a wrist
strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken
for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the device.
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by
you or third parties arising from the use of these circuits, software, or information.
2.
Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other disputes involving patents, copyrights, or other intellectual property rights of third parties, by or
arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawing, chart, program, algorithm, application
examples.
3.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.
4.
You shall not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages
5.
Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The intended applications for each Renesas Electronics product depends on the
incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics products.
product’s quality grade, as indicated below.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; and industrial robots etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical
implantations etc.), or may cause serious property damages (space and undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas
Electronics disclaims any and all liability for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas
Electronics.
6.
When using the Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, "General Notes for Handling and Using Semiconductor Devices" in the
reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat radiation
characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions or failure or accident arising out of the use of Renesas Electronics products beyond such specified
ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics such as the occurrence of failure at a
certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please ensure to implement safety measures to guard them
against the possibility of bodily injury, injury or damage caused by fire, and social damage in the event of failure or malfunction of Renesas Electronics products, such as safety design for hardware and
software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures by your own responsibility as warranty
for your products/system. Because the evaluation of microcomputer software alone is very difficult and not practical, please evaluate the safety of the final products or systems manufactured by you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please investigate applicable laws and
regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive carefully and sufficiently and use Renesas Electronics products in compliance with all
these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
9.
Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws
or regulations. You shall not use Renesas Electronics products or technologies for (1) any purpose relating to the development, design, manufacture, use, stockpiling, etc., of weapons of mass destruction,
such as nuclear weapons, chemical weapons, or biological weapons, or missiles (including unmanned aerial vehicles (UAVs)) for delivering such weapons, (2) any purpose relating to the development,
design, manufacture, or use of conventional weapons, or (3) any other purpose of disturbing international peace and security, and you shall not sell, export, lease, transfer, or release Renesas Electronics
products or technologies to any third party whether directly or indirectly with knowledge or reason to know that the third party or any other party will engage in the activities described above. When exporting,
selling, transferring, etc., Renesas Electronics products or technologies, you shall comply with any applicable export control laws and regulations promulgated and administered by the governments of the
countries asserting jurisdiction over the parties or transactions.
10. Please acknowledge and agree that you shall bear all the losses and damages which are incurred from the misuse or violation of the terms and conditions described in this document, including this notice,
and hold Renesas Electronics harmless, if such misuse or violation results from your resale or making Renesas Electronics products available any third party.
11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
(Rev.3.0-1 November 2016)
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