Datasheet
RL78/I1A
R01DS0171EJ0320
Rev.3.20
Sep 29, 2017
RENESAS MCU
True Low Power Platform, High Resolution PWM and Rich Analog, 2.7 V to 5.5 V operation, 32 to 64 Kbyte Flash,
for Inverter Control, Digital Power Control and Lighting Control Applications
1. OUTLINE
1.1 Features
Ultra-Low Power Technology
2.7 V to 5.5 V operation from a single supply
Stop (RAM retained): 0.23 µA, (LVD enabled): 0.31 µA
Halt (RTC + LVD): 0.60 µA
Operating: 156.25 µA/MHz
16-bit RL78 CPU Core
Delivers 41 DMIPS at maximum operating frequency of
32 MHz
Instruction execution: 86% of instructions can be
executed in 1 to 2 clock cycles
CISC architecture (Harvard) with 3-stage pipeline
Multiply signed & unsigned: 16 x 16 to 32-bit result in 1
clock cycle
MAC: 16 x 16 to 32-bit result in 2 clock cycles
16-bit barrel shifter for shift & rotate in 1 clock cycle
1-wire on-chip debug function
Main Flash Memory
Density: 32 KB to 64 KB
Block size: 1 KB
On-chip single voltage flash memory with protection from
block erase/writing
Self-programming with secure boot swap function and
flash shield window function
Data Flash Memory
Data flash with background operation
Data flash size: 4 KB
Erase cycles: 1 million (typ.)
Erase/programming voltage: 2.7 V to 5.5 V
RAM
2 KB to 4 KB size options
Supports operands or instructions
Back-up retention in all modes
High-speed On-chip Oscillator
32 MHz with +/ 1% accuracy over voltage (2.7 V to 5.5
V) and temperature (20°C to 85°C)
Pre-configured settings: 32 MHz, 24 MHz, 16 MHz, 12
MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz & 1 MHz
Reset and Supply Management
Power-on reset (POR) monitor/generator
Low voltage detection (LVD) with 6 setting options
(Interrupt and/or reset function)
Data Memory Access (DMA) Controller
Up to 2 fully programmable channels
Transfer unit: 8- or 16-bit
16-bit timers KB0 to KB2, and KC0 for PWM output
16-bit timers KB0 to KB2: maximum 6 outputs (3 channels 2)
Smooth start function, dithering function, forced output
stop function (unsynchronized with comparator or external
interrupt) enables over-voltage protection, over-current
protection and peak current control, and single/interleave
PFC function
Average resolution < 0.98 nsec output, 64 MHz (when
using PLL) + dithering option
16-bit timer KC0 (1 channel × 6 (output))
PWM output gating function by interlocking with 16-bit
timers KB0, KB1, and KB2
Extended-Function Timers
Multi-function 16-bit timers: Up to 8 channels
Real-time clock (RTC): 1 channel (full calendar and
alarm function with watch correction function)
Interval timer: 12-bit, 1 channel
15 kHz watchdog timer: 1 channel (window function)
Multiple Communication Interfaces
Up to 1 channel x I2C multi-master (SMBus/PMBus
support)
Up to 1 channel x CSI/SPI (7-, 8-bit)
Up to 3 channels x UART (7-, 8-, 9-bit),
DALI support 1 channel (8-, 16-, 17-, 24-bit, master and
slave)
Up to 1 channel x LIN
Rich Analog
ADC: Up to 11 channels, 8/10-bit resolution, 2.125 µs
conversion time
Supports 2.7 V
Internal voltage reference (1.45 V)
Comparator: High response time 70 ns (typ.), up to 6
channels, internal DAC 3 channels 8-bit resolution,
window comparator mode
PGA (x4 to x32): 6 input channels
On-chip temperature sensor
Safety Features (IEC or UL 60730 compliance)
Flash memory CRC calculation
RAM parity error check
RAM/SFR write protection
Illegal memory access detection
Clock stop/frequency detection
ADC self-test
General Purpose I/O
5-V tolerant, high-current (up to 8.5 mA per pin)
Open-drain, internal pull-up support
Operating Ambient Temperature
Standard: 40°C to +105°C
Extend: 40°C to +125°C
Package Type and Pin Count
SSOP: 20, 30, 38
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RL78/I1A
1. OUTLINE
○ ROM, RAM capacities
Flash ROM Data flash
64 KB
4 KB
32 KB
4 KB
Note
RAM
4 KB
Note
2 KB
RL78/I1A
20 pins
30 pins
38 pins
R5F107AE
R5F107DE
R5F1076C
R5F107AC
This is about 3 KB when the self-programming function and data flash function are used.
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RL78/I1A
1. OUTLINE
1.2 List of Part Numbers
Figure 1-1. Part Number, Memory Size, and Package of RL78/I1A
Part No. R 5 F 1 0 7 D E G x x x S P # V 0
Package specification:
#V0: Tray (LSSOP30, SSOP38), Tube (LSSOP20)
#X0: Embossed tape (LSSOP, SSOP)
Package type:
SP: LSSOP, 0.65 mm pitch
SSOP, 0.65 mm pitch
ROM number (Omitted with blank products)
Classification:
G: Operating ambient temperature: −40°C to 105°C
M: Operating ambient temperature: −40°C to 125°C
ROM capacity:
C: 32 KB
E: 64 KB
Pin count:
6: 20-pin
A: 30-pin
D: 38-pin
RL78/I1A group
Memory type:
F: Flash memory
Renesas MCU
Renesas semiconductor product
Pin count
Package
Operating Ambient
Part Number
Temperature
20 pins
30 pins
20-pin plastic LSSOP
(4.4 6.5)
TA = 40 to +105C
R5F1076CGSP#V0, R5F1076CGSP#X0
TA = 40 to +125C
R5F1076CMSP#V0, R5F1076CMSP#X0
30-pin plastic LSSOP
TA = 40 to +105C
R5F107ACGSP#V0, R5F107AEGSP#V0,
(7.62 mm (300))
R5F107ACGSP#X0, R5F107AEGSP#X0
TA = 40 to +125C
R5F107ACMSP#V0, R5F107AEMSP#V0,
R5F107ACMSP#X0, R5F107AEMSP#X0
38 pins
38-pin plastic SSOP
TA = 40 to +105C
R5F107DEGSP#V0, R5F107DEGSP#X0
(7.62 mm (300))
TA = 40 to +125C
R5F107DEMSP#V0, R5F107DEMSP#X0
Caution The ordering part numbers represent the numbers at the time of publication. For the latest
ordering part numbers, refer to the target product page of the Renesas Electronics website.
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RL78/I1A
1. OUTLINE
1.3 Pin Configuration (Top View)
1.3.1 20-pin products
20-pin plastic LSSOP (4.4 x 6.5)
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
P22/ANI2/CMP0P
P24/ANI4/CMP1P
P25/ANI5/CMP2P
P147/CMPCOM/ANI18/(CMP3P)
P10/TxD0/TKCO00/INTP20/SCLA0/(DALITxD4)
P11/RxD0/TKCO01/INTP21/SDAA0/(TI07)/(DALIRxD4)/(TxRx4)/(INTP0)
P200/TKBO00/INTP22
P201/TKBO01
P202/TKBO10/(INTP21)
P203/TKBO11/TKCO02/(INTP20)
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR1) or the input switch control register (ISC). See Figure 4-8 Format of
Peripheral I/O Redirection Register (PIOR1) and Figure 15-20
Format of Input Switch
Control Register (ISC) in the RL78/I1A User's Manual.
3. The shared function CMP3P can be assigned to P147 by setting the CMPSEL0 bit in the
comparator input switch control register (CMPSEL).
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RL78/I1A
1. OUTLINE
1.3.2 30-pin products
30-pin plastic LSSOP (7.62 mm (300))
P20/ANI0/AVREFP
P03/RxD1/CMP5P/ANI16
P02/TxD1/ANI17
P120/ANI19
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P31/TI03/TO03/INTP4
P77/INTP11
P206/TKCO05/DALIRxD4/TxRx4/INTP23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P21/ANI1/AVREFM
P22/ANI2/CMP0P
P24/ANI4/CMP1P
P25/ANI5/CMP2P
P26/ANI6/CMP3P
P27/ANI7/CMP4P
P147/CMPCOM/ANI18
P10/TxD0/TKCO00/INTP20/SCLA0/(DALITxD4)
P11/RxD0/TKCO01/INTP21/SDAA0/(TI07)/(DALIRxD4)/(TxRx4)/(INTP0)
P200/TKBO00/INTP22
P201/TKBO01
P202/TKBO10/(INTP21)
P203/TKBO11/TKCO02/(INTP20)
P204/TKBO20/TKCO03
P205/TKBO21/TKCO04/DALITxD4
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR1) or the input switch control register (ISC). See Figure 4-8 Format of
Peripheral I/O Redirection Register (PIOR1) and Figure 15-20
Format of Input Switch
Control Register (ISC) in the RL78/I1A User's Manual.
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RL78/I1A
1. OUTLINE
1.3.3 38-pin products
38-pin plastic SSOP (7.62 mm (300))
P20/ANI0/AVREFP
P03/RxD1/CMP5P/ANI16
P02/TxD1/ANI17
P120/ANI19
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P31/TI03/TO03/INTP4
P77/INTP11
P76/INTP10
P75/INTP9
P06/TI06/TO06
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
P21/ANI1/AVREFM
P22/ANI2/CMP0P
P24/ANI4/CMP1P
P25/ANI5/CMP2P
P26/ANI6/CMP3P
P27/ANI7/CMP4P
P147/CMPCOM/ANI18
P10/SO00/TxD0/TKCO00/INTP20/SCLA0/(DALITxD4)
P11/SI00/RxD0/TKCO01/INTP21/SDAA0/(TI07)/(DALIRxD4)/(TxRx4)/(INTP0)
P12/SCK00/(TKCO03)
P200/TKBO00/INTP22
P201/TKBO01
P202/TKBO10/(INTP21)
P203/TKBO11/TKCO02/(INTP20)
P204/TKBO20/TKCO03
P205/TKBO21/TKCO04/DALITxD4
P206/TKCO05/DALIRxD4/TXRx4/INTP23
P30/INTP3/RTC1HZ
P05/TI05/TO05
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR1) or the input switch control register (ISC). See Figure 4-8 Format of
Peripheral I/O Redirection Register (PIOR1) and Figure 15-20
Format of Input Switch
Control Register (ISC) in the RL78/I1A User's Manual.
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RL78/I1A
1. OUTLINE
1.4 Pin Identification
ANI0 to ANI2,
REGC:
Regulator Capacitance
ANI4 to ANI7,
RESET:
Reset
RTC1HZ:
Real-time Clock Correction Clock
ANI16 to ANI19:
Analog Input
AVREFM:
Analog Reference Voltage Minus
AVREFP:
Analog Reference Voltage Plus
RxD0, RxD1,
CMP0P to CMP5P:
Comparator Analog Input
DALIRxD4:
Receive Data
CMPCOM:
Comparator External Reference
SCK00:
Serial Clock Input/Output
Voltage
SCLA0:
Serial Clock Input/Output
External Clock Input (Main System
SDAA0:
Serial Data Input/Output
Clock)
SI00:
Serial Data Input
External Clock Input (Subsystem
SO00:
Serial Data Output
Clock)
TI03, TI05, TI06,
EXCLK:
EXCLKS:
(1 Hz) Output
INTP0, INTP3,
TI07:
INTP4, INTP9,
TO03, TO05, TO06,
INTP10, INTP11,
TKBO00, TKBO01 to
INTP20 to INTP23:
Interrupt Request from Peripheral
P02, P03,
Timer Input
TKBO20, TKBO21,
TKCO00 to TKCO05: Timer Output
P05, P06:
Port 0
TOOL0:
Data Input/Output for Tool
P10 to P12:
Port 1
TxRx4:
Serial Data Input/Output for Single
P20 to P22,
Wired UART
P24 to P27:
Port 2
TxD0, TxD1
P30, P31:
Port 3
DALITxD4:
Transmit Data
P40:
Port 4
VDD:
Power Supply
P75 to P77:
Port 7
VSS:
Ground
P120 to P124:
Port 12
X1, X2:
Crystal Oscillator (Main System Clock)
P137:
Port 13
XT1, XT2:
Crystal Oscillator (Subsystem Clock)
P147:
Port 14
P200 to P206:
Port 20
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RL78/I1A
1. OUTLINE
1.5 Block Diagram
1.5.1 20-pin products
TIMER ARRAY
UNIT (8ch)
ch0
PORT 1
2
P10, P11
PORT 2
5
P20 to P22,
P24, P25
ch1
ch2
PORT 4
P40
ch3
(TI07)/RxD0/P11(LIN-bus, DMX512)
TKBO00/P200, TKBO01/P201,
TKBO10/P202, TKBO11/P203
4
2
PORT 12
ch5
PORT 13
P137
ch6
PORT 14
P147
ch7
PORT 20
4
P200 to P203
5
ANI0/P20 to ANI2/P22,
ANI4/P24, ANI5/P25
16-bit TIMER KB0, KB1
ANI18/P147
A/D CONVERTER
TKCO00/P10, TKCO01/P11,
TKCO02/P203
AVREFP/P20
AVREFM/P21
16-bit TIMER KC0
3
PROGRAMMABLE
GAIN AMPLIFIER
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
12- BIT INTERVAL
TIMER
REAL-TIME
CLOCK
COMPARATOR
CODE FLASH MEMORY
RL78
CPU
CORE
DATA FLASH MEMORY
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P11
TxD0/P10
3
CMP0P/P22, CMP1P/P24,
CMP2P/P25, (CMP3P/P147)
3
CMP0P/P22, CMP1P/P24,
CMP2P/P25, (CMP3P/P147)
CMPCOM/P147
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
UART0
RESET CONTROL
LIN-bus, DMX512
DATA
FLASH
MEMORY
RAM
SERIAL ARRAY
UNIT4 (2ch)
(DALIRxD4/P11)
(DALITxD4/P10)
HIGH-SPEED
SINGLE-WIRE UART
SERIAL
INTERFACE IICA
MULTIPLIER&
DIVIDER,
MULTIPLYACCUMULATOR
TOOL0/P40
RESET
X1/P121
X2/EXCLK/P122
ON-CHIP
VDD
SDAA0/P11
SCLA0/P10
ON-CHIP DEBUG
SYSTEM
CONTROL
UART4
DALI, DMX512
(TxRx4/P11)
P121, P122
ch4
OSCILLATOR
VSS
DIRECT MEMORY
ACCESS CONTROL
CRC
BCD
ADJUSTMENT
VOLTAGE
REGULATOR
INTERRUPT
CONTROL
REGC
RxD0/P11
INTP0/P137
INTP20/P10(INTP20/P203)
INTP21/P11(INTP21/P202)
INTP22/P200
Remarks 1. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR1) or the input switch control register (ISC). See Figure 4-8 Format of
Peripheral I/O Redirection Register (PIOR1) and Figure 15-20
Format of Input Switch
Control Register (ISC) in the RL78/I1A User's Manual.
2. The shared function CMP3P can be assigned to P147 by setting the CMPSEL0 bit in the
comparator input switch control register (CMPSEL).
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RL78/I1A
1. OUTLINE
1.5.2 30-pin products
TIMER ARRAY
UNIT (8ch)
ch0
PORT 0
2
P02, P03
PORT 1
2
P10, P11
PORT 2
7
P20 to P22,
P24 to P27
ch1
ch2
PORT 3
P31
PORT 4
P40
ch5
PORT 7
P77
ch6
PORT 12
ch3
TI03/TO03/P31
ch4
(TI07)/RxD0/P11(LIN-bus, DMX512)
TKBO00/P200, TKBO01/P201,
TKBO10/P202, TKBO11/P203,
TKBO20/P204, TKBO21/P205
ch7
6
P121, P122
PORT 13
P137
PORT 14
P147
16-bit TIMER KB0 to KB2
PORT 20
TKCO00/P10, TKCO01/P11,
TKCO02/P203,TKCO03/P204,
TKCO04/P205,TKCO05/P206
P120
2
16-bit TIMER KC0
6
A/D CONVERTER
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
CODE FLASH MEMORY
RL78
CPU
CORE
PROGRAMMABLE
GAIN AMPLIFIER
DATA FLASH MEMORY
SERIAL ARRAY
UNIT0 (4ch)
UART0
LIN-bus, DMX512
RxD1/P03
TxD1/P02
UART1
7
ANI0/P20 to ANI2/P22,
ANI4/P24 to ANI7/P27
4
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120
DATA
FLASH
MEMORY
RAM
6
6
COMPARATOR
RxD0/P11
TxD0/P10
P200 to P206
AVREFP/P20
AVREFM/P21
12- BIT INTERVAL
TIMER
REAL-TIME
CLOCK
7
POWER ON RESET/
VOLTAGE
DETECTOR
CMP0P/P22,
CMP1P/P24 to CMP4P/P27,
CMP5P/P03
CMP0P/P22,
CMP1P/P24 to CMP4P/P27,
CMP5P/P03
CMPCOM/P147
POR/LVD
CONTROL
RESET CONTROL
SERIAL ARRAY
UNIT4 (2ch)
DALIRxD4/P206(DALIRxD4/P11)
DALITxD4/P205(DALITxD4/P10)
TxRx4/P206(TXRX4/P11)
ON-CHIP DEBUG
UART4
DALI, DMX512
VDD
VSS
SYSTEM
CONTROL
SINGLE-WIRE UART
SDAA0/P11
SCLA0/P10
DIRECT MEMORY
ACCESS CONTROL
SERIAL
INTERFACE IICA
MULTIPLIER&
DIVIDER,
MULTIPLYACCUMULATOR
CRC
HIGH-SPEED
RESET
X1/P121
X2/EXCLK/P122
ON-CHIP
OSCILLATOR
BCD
ADJUSTMENT
VOLTAGE
REGULATOR
REGC
RxD0/P11
INTP0/P137
INTERRUPT
CONTROL
Remark
TOOL0/P40
INTP4/P31
INTP11/P77
INTP20/P10(INTP20/P203)
INTP21/P11(INTP21/P202)
INTP22/P200
INTP23/P206
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR1) or the input switch control register (ISC). See Figure 4-8 Format of
Peripheral I/O Redirection Register (PIOR1) and Figure 15-20 Format of Input Switch Control
Register (ISC) in the RL78/I1A User's Manual.
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RL78/I1A
1. OUTLINE
1.5.3 38-pin products
TIMER ARRAY
UNIT (8ch)
ch0
PORT 0
4
P02, P03, P05, P06
PORT 1
3
P10 to P12
PORT 2
7
P20 to P22,
P24 to P27
PORT 3
2
P30, P31
ch1
ch2
ch3
TI03/TO03/P31
PORT 4
ch4
ch6
TI06/TO06/P06
(TI07)/RxD0/P11(LIN-bus, DMX512)
TKBO00/P200, TKBO01/P201,
TKBO10/P202, TKBO11/P203,
TKBO20/P204, TKBO21/P205
PORT 7
ch5
TI05/TO05/P05
PORT 12
ch7
6
6
P75 to P77
P120
4
P121 to P124
P137
PORT 14
P147
16-bit TIMER KB0 to KB2
16-bit TIMER KC0
A/D CONVERTER
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
3
PORT 13
PORT 20
TKCO00/P10, TKCO01/P11,
TKCO02/P203,TKCO03/P204(TKCO03/P12),
TKCO04/P205,TKCO05/P206
P40
P200 to P206
7
ANI0/P20 to ANI2/P22,
ANI4/P24 to ANI7/P27
4
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
12- BIT INTERVAL
TIMER
REAL-TIME
CLOCK
7
CODE FLASH MEMORY
RL78
CPU
CORE
PROGRAMMABLE
GAIN AMPLIFIER
DATA FLASH MEMORY
CMP0P/P22,
CMP1P/P24 to CMP4P/P27,
CMP5P/P03
6
CMP0P/P22,
CMP1P/P24 to CMP4P/P27,
CMP5P/P03
CMPCOM/P147
6
COMPARATOR
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P11
TxD0/P10
UART0
LIN-bus, DMX512
RxD1/P03
TxD1/P02
UART1
SCK00/P12
SI00/P11
SO00/P10
CSI00
DATA
FLASH
MEMORY
RAM
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
SERIAL ARRAY
UNIT4 (2ch)
DALIRxD4/P206(DALIRxD4/P11)
DALITxD4/P205(DALITxD4/P10)
DALI, DMX512
TxRx4/P206(TxRx4/P11)
SDAA0/P11
SCLA0/P10
VDD
SYSTEM
CONTROL
DIRECT MEMORY
ACCESS CONTROL
SINGLE-WIRE UART
SERIAL
INTERFACE IICA
CRC
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
XT1/P123
ON-CHIP
OSCILLATOR
BCD
ADJUSTMENT
MULTIPLIER&
DIVIDER,
MULTIPLYACCUMULATOR
Remark
VSS
UART4
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
2
INTERRUPT
CONTROL
3
RxD0/P11
INTP0/P137
INTP3/P30,
INTP4/P31
INTP9/P75 to
INTP11/P77
INTP20/P10(INTP20/P203)
INTP21/P11(INTP21/P202)
INTP22/P200
INTP23/P206
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR1) or the input switch control register (ISC). See Figure 4-8 Format of
Peripheral I/O Redirection Register (PIOR1) and Figure 15-20 Format of Input Switch Control
Register (ISC) in the RL78/I1A User's Manual.
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RL78/I1A
1. OUTLINE
1.6 Outline of Functions
Caution This outline describes the functions at the time when Peripheral I/O redirection register
(PIOR1) is set to 00H.
(1/3)
Item
20-pin
30-pin
38-pin
R5F1076C
R5F107AC
R5F107AE
R5F107DE
Code flash memory (KB)
32
32
64
64
Data flash memory (KB)
4
4
RAM (KB)
2
Address space
Main system
clock
4
2
4
4
Note 1
4
Note 1
1 MB
High-speed system
clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
HS (High-speed main) mode: 1 to 20 MHz (VDD = 2.7 to 5.5 V),
LS (Low-speed main) mode: 1 to 8 MHz (VDD = 2.7 to 5.5 V)
High-speed on-chip
oscillator
HS (High-speed main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V),
LS (Low-speed main) mode: 1 to 8 MHz (VDD = 2.7 to 5.5 V)
Clock for 16-bit timers KB0 to KB2,
and KC0
64 MHz (TYP.)
Subsystem clock (38-pin products
only)
XT1 (crystal) oscillation, external subsystem clock input (EXCLKS)
32.768 kHz
Low-speed on-chip oscillator
15 kHz (TYP.)
General-purpose register
(8-bit register 8) 4 banks
Minimum instruction execution time
0.03125 s (High-speed on-chip oscillator: fIH = 32 MHz operation)
0.05 s (High-speed system clock: fMX = 20 MHz operation)
30.5 s (Subsystem clock: fSUB = 32.768 kHz operation) (38-pin products only)
8-bit operation, 16-bit operation
Multiplication (8 bits 8 bits)
Bit manipulation (Set, reset, test, and Boolean operation), etc.
Instruction set
I/O port
Timer
Notes 1.
Total
16
26
34
CMOS I/O
13
23
29
CMOS input
3
3
5
CMOS output
8 channels (timer output: 1, PWM output: 1
Note 2
16-bit timer TAU
8 channels (no timer
output)
)
16-bit timer KB
2 channels (PWM
outputs: 4)
3 channels (PWM outputs: 6)
16-bit timer KC
1 channel (PWM
outputs: 3)
1 channel (PWM outputs: 6)
8 channels (timer
outputs: 3, PWM
outputs: 3Note 2)
This is about 3 KB when the self-programming function and data flash function are used. (For details,
see CHAPTER 3 in the RL78/I1A User's Manual.)
2.
The number of PWM outputs varies depending on the setting of channels in use (the number of
masters and slaves) (see 6.9.3 Operation as multiple PWM output function in the RL78/I1A
User's Manual).
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RL78/I1A
1. OUTLINE
(2/3)
Item
Timer
20-pin
30-pin
38-pin
R5F1076C
R5F107AC, R5F107AE
R5F107DE
Watchdog timer
1 channel
Real-time clock
(RTC)
1 channelNotes 1, 2
12-bit interval timer
(IT)
1 channel
RTC output
1
1 Hz (subsystem clock:
fSUB = 32.768 kHz)
8/10-bit resolution A/D converter
6 channels
11 channels
11 channels
Comparator
4 channels
6 channels
6 channels
Programmable gain amplifier
Input
Serial interface
1 channel
Note 3
4 channels
[20-pin]
6 channels
6 channels
Note 5
UART (Supporting LIN-bus and DMX512): 1 channel
UART (Supporting DALI communication): 1 channel
[30-pin products]
UART (Supporting LIN-bus and DMX512): 1 channel
UART: 1 channel
UART (Supporting DALI communication): 1 channel
[38-pin products]
CSI: 1 channel/UART (Supporting LIN-bus and DMX512): 1 channel
UART: 1 channel
UART (Supporting DALI communication): 1 channel
2
I C bus
1 channel
1 channel
Multiplier and divider/multiply-
16 bits 16 bits = 32 bits (Unsigned or signed)
accumulator
32 bits 32 bits = 32 bits (Unsigned)
1 channel
16 bits 16 bits + 32 bits = 32 bits (Unsigned or signed)
DMA controller
2 channels
Vectored interrupt Internal
sources
External
27
30
30
7
10
11
Reset by RESET pin
Reset
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
Internal reset by illegal instruction executionNote 4
Internal reset by RAM parity error
Internal reset by illegal-memory access
Notes 1.
2.
The subsystem clock (fSUB) can be selected as the operating clock only for 38-pin products.
The 20- and 30-pin products can only be used as the constant-period interrupt function.
3.
The comparator input is alternatively used with analog input pin (ANI pin).
4.
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or onchip debug emulator.
5.
The 20 pin products can only be used 1 UART simultaneously due to sharing of the same I/O pins.
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RL78/I1A
1. OUTLINE
(3/3)
Item
Power-on-reset circuit
20-pin
30-pin
38-pin
R5F1076C
R5F107AC, R5F107AE
R5F107DE
• Power-on-reset:
1.51 V (TYP.)
• Power-down-reset: 1.50 V (TYP.)
Voltage detector
Rising edge:
2.81 V to 4.06 V (6 stages)
Falling edge:
2.75 V to 3.98 V (6 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 2.7 to 5.5 V
Operating ambient temperature
TA = 40 to +105C (G: Industrial applications), TA = 40 to +125C (M: Industrial applications)
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RL78/I1A
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
2. ELECTRICAL SPECIFICATIONS
(G: Industrial applications, TA = 40 to +105C)
In this chapter, shows the electrical specifications of the target products.
Target products (G: Industrial applications): TA = 40 to + 105C
R5F107xxGxx
Cautions 1. The RL78/I1A has an on-chip debug function, which is provided for development and evaluation.
Do not use the on-chip debug function in products designated for mass production, because
the guaranteed number of rewritable times of the flash memory may be exceeded when this
function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics
is not liable for problems occurring when the on-chip debug function is used.
2. The pins mounted depend on the product. See 2.1 Port Function to 2.2.1 Functions for each
product in the RL78/I1A User's Manual.
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2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
2.1 Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25C) (1/2)
Parameter
Symbols
Supply voltage
VDD
REGC pin input voltage
VIREGC
Conditions
REGC
Ratings
Unit
0.5 to +6.5
V
0.3 to +2.8
V
and 0.3 to VDD +0.3Note 1
Input voltage
VI1
P02, P03, P05, P06, P10 to P12, P20 to P22,
0.3 to VDD +0.3Note 2
V
0.3 to VDD +0.3Note 2
V
0.3 to VDD +0.3
V
P24 to P27, P30, P31, P40, P75 to P77,
P120 to P124, P137, P147, P200 to P206,
EXCLK, EXCLKS, RESET
Output voltage
VO1
P02, P03, P05, P06, P10 to P12, P20 to P22,
P24 to P27, P30, P31, P40, P75 to P77, P120,
P147, P200 to P206
Analog input voltage
VAI1
ANI0 to ANI2, ANI4 to ANI7, ANI16 to ANI19
and 0.3 to AVREF(+)
+0.3Notes 2, 3
Notes 1.
Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
This value regulates the
absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it.
2.
Must be 6.5 V or lower.
3.
Do not exceed AV REF(+) + 0.3 V in case of A/D conversion target pin.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remarks 1.
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of
the port pins.
2. AVREF (+): + side reference voltage of the A/D converter.
3. VSS: Reference voltage
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2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
Absolute Maximum Ratings (TA = 25C) (2/2)
Parameter
Output current, high
Symbols
IOH1
Conditions
Per pin
P02, P03, P05, P06, P10 to P12,
Ratings
Unit
40
mA
P30, P31, P40, P75 to P77, P120,
P147, P200 to P206
Total of all pins
170 mA
P02, P03, P40, P120
70
mA
P05, P06, P10 to P12, P30, P31,
100
mA
0.5
mA
2
mA
40
mA
P75 to P77, P147, P200 to P206
IOH2
Per pin
P20 to P22, P24 to P27
Total of all pins
Output current, low
IOL1
Per pin
P02, P03, P05, P06, P10 to P12,
P30, P31, P40, P75 to P77, P120,
P147, P200 to P206
Total of all pins
P02, P03, P40, P120
70
mA
170 mA
P05, P06, P10 to P12, P30, P31,
100
mA
1
mA
P75 to P77, P147, P200 to P206
IOL2
Per pin
P20 to P22, P24 to P27
Total of all pins
Operating ambient
TA
temperature
In normal operation mode
5
mA
40 to +105
C
65 to +150
C
In flash memory programming mode
Storage temperature
Tstg
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
2.2 Oscillator Characteristics
2.2.1 X1, XT1 oscillator characteristics
(TA = 40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
X1 clock oscillation
Resonator
Conditions
MIN.
Ceramic resonator/crystal resonator
1.0
Crystal resonator
32
TYP.
MAX.
Unit
20.0
MHz
35
kHz
frequency (fX)Note
XT1 clock oscillation
32.768
frequency (fXT)Note
Note Indicates only permissible oscillator frequency ranges. See AC Characteristics for instruction execution
time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the
oscillator characteristics.
Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check
the X1 clock oscillation stabilization time using the oscillation stabilization time counter status
register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and
the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation
stabilization time with the resonator to be used.
Remark
When using the X1 oscillator and XT1 oscillator, see 5.4 System Clock Oscillator in the RL78/I1A
User's Manual.
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2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
2.2.2 On-chip oscillator characteristics
(TA = 40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V)
Oscillators
Parameters
High-speed on-chip oscillator
Conditions
fIH
MIN.
TYP.
MAX.
Unit
1
32
MHz
clock frequencyNote 1
High-speed on-chip oscillator
TA = 20 to 85C
1
+1
%
clock frequency accuracyNote 2
TA = 40 to 105C
1.5
+1.5
%
Low-speed on-chip oscillator
fIL
15
kHz
clock frequency
15
Low-speed on-chip oscillator
+15
%
clock frequency accuracy
Notes 1. Frequency can be selected in a high-speed on-chip oscillator. Selected by bits 0 to 3 of option byte
(000C2H/010C2H).
2. This indicates the oscillator characteristics only. See AC Characteristics for instruction execution
time.
2.2.3 PLL characteristics
(TA = 40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
PLL input clock
Symbol
fPLLIN
frequencyNote
PLL output clock
fPLL
MIN.
TYP.
MAX.
Unit
High-speed system clock is selected (fMX = 4 MHz)
Conditions
3.94
4.00
4.06
MHz
High-speed on-chip oscillator clock is selected (fIH = 4 MHz)
3.94
4.00
4.06
MHz
fPLLIN 16
MHz
frequencyNote
Note This only indicates the oscillator characteristics. See AC Characteristics for instruction execution time.
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2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
2.3 DC Characteristics
2.3.1 Pin characteristics
(TA = 40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V)
Items
Symbol
Output current,
highNote 1
IOH1
Conditions
Per pin for P02, P03, P05, P06, P10 to P12,
P30, P31, P40, P75 to P77, P120, P147,
P200 to P206
Total of P02, P03, P40, P120
(When duty 70%Note 3)
Total of P05, P06, P10 to P12, P30, P31,
P75 to P77, P147, P200 to P206
(When duty 70%Note 3)
IOH2
Notes 1.
MIN.
4.0 V VDD 5.5 V
TYP.
MAX.
3.0
Note 2
Unit
mA
2.7 V VDD < 4.0 V
1.0
mA
4.0 V VDD 5.5 V
12.0
mA
2.7 V VDD < 4.0 V
4.0
mA
4.0 V VDD 5.5 V
30.0
mA
2.7 V VDD < 4.0 V
10.0
mA
4.0 V VDD 5.5 V
30.0
mA
Total of all pins
(When duty 70%Note 3)
2.7 V VDD < 4.0 V
14.0
mA
Per pin for P20 to P22, P24 to P27
2.7 V VDD 5.5 V
0.1Note 2
mA
Total of all pins
(When duty 70%Note 3)
2.7 V VDD 5.5 V
0.7
mA
Value of current at which the device operation is guaranteed even if the current flows from the VDD
pin to an output pin.
2.
However, do not exceed the total current value.
3.
Specification under conditions where the duty factor 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated
with the following expression (when changing the duty factor from 70% to n%).
Total output current of pins = (IOH × 0.7)/(n × 0.01)
Where n = 80% and IOH = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Caution P02, P10 to P12 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
(TA = 40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V)
Items
Symbol
Output current,
lowNote 1
IOL1
Conditions
Per pin for P02, P03, P05, P06,
P10 to P12, P30, P31, P40,
P75 to P77, P120, P147, P200 to P206
Total of P02, P03, P40, P120
(When duty 70%Note 3)
Total of P05, P06, P10 to P12, P30,
P31, P75 to P77, P147, P200 to P206
(When duty 70%Note 3)
IOL2
Notes 1.
MAX.
Unit
4.0 V VDD 5.5 V
MIN.
TYP.
8.5Note 2
mA
2.7 V VDD < 4.0 V
1.5Note 2
mA
4.0 V VDD 5.5 V
40.0
mA
2.7 V VDD < 4.0 V
7.5
mA
4.0 V VDD 5.5 V
40.0
mA
2.7 V VDD < 4.0 V
17.5
mA
Total of all pins
(When duty 70%Note 3)
4.0 V VDD 5.5 V
80.0
mA
2.7 V VDD < 4.0 V
25.0
mA
Per pin for P20 to P22, P24 to P27
2.7 V VDD 5.5 V
Total of all pins
(When duty 70%Note 3)
2.7 V VDD 5.5 V
Note 2
0.4
2.8
mA
mA
Value of current at which the device operation is guaranteed even if the current flows from an output
pin to the VSS pin.
2.
However, do not exceed the total current value.
3.
Specification under conditions where the duty factor 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated
with the following expression (when changing the duty factor from 70% to n%).
Total output current of pins = (IOL × 0.7)/(n × 0.01)
Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
(TA = 40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V)
Items
Input voltage,
Symbol
VIH1
high
Conditions
P02, P03, P05, P06, P10 to P12,
MIN.
TYP.
MAX.
Unit
Normal input buffer
0.8VDD
VDD
V
TTL input buffer
4.0 V VDD 5.5 V
2.1
VDD
V
TTL input buffer
3.3 V VDD 4.0 V
2.0
VDD
V
TTL input buffer
2.7 V VDD 3.3 V
1.5
VDD
V
Normal input buffer
0
0.2VDD
V
TTL input buffer
4.0 V VDD 5.5 V
0
0.8
V
TTL input buffer
3.3 V VDD 4.0 V
0
0.5
V
TTL input buffer
2.7 V VDD 3.3 V
0
0.32
V
P20 to P22, P24 to P27, P30, P31,
P40, P75 to P77, P120 to P124, P137,
P147, P200 to P206, EXCLK,
EXCLKS, RESET
VIH2
Input voltage, low VIL1
P03, P10, P11
P02, P03, P05, P06, P10 to P12,
P20 to P22, P24 to P27, P30, P31,
P40, P75 to P77, P120 to P124, P137,
P147, P200 to P206, EXCLK,
EXCLKS, RESET
VIL2
P03, P10, P11
Caution The maximum value of VIH of pins P02, P10 to P12 is VDD, even in the N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
(TA = 40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V)
Items
Symbol
Output voltage,
VOH1
high
Conditions
MIN.
P02, P03, P05, P06, P10 to P12, P30,
4.0 V VDD 5.5 V,
P31, P40, P75 to P77, P120, P147,
IOH1 = 3.0 mA
P200 to P206
2.7 V VDD 5.5 V,
TYP.
MAX.
Unit
VDD 0.7
V
VDD 0.5
V
VDD 0.5
V
IOH1 = 1.0 mA
VOH2
P20 to P22, P24 to P27
2.7 V VDD 5.5 V,
IOH2 = 100 A
Output voltage,
VOL1
low
P02, P03, P05, P06, P10 to P12, P30,
4.0 V VDD 5.5 V,
P31, P40, P75 to P77, P120, P147,
IOL1 = 8.5 mA
P200 to P206
4.0 V VDD 5.5 V,
0.7
V
0.4
V
0.4
V
0.4
V
IOL1 = 4.0 mA
2.7 V VDD 5.5 V,
IOL1 = 1.5 mA
VOL2
P20 to P22, P24 to P27
2.7 V VDD 5.5 V,
IOL2 = 400 A
Caution P02, P10 to P12 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
(TA = 40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V)
Items
Symbol
Input leakage
ILIH1
current, high
Conditions
P02, P03, P05, P06, P10 to P12,
MIN.
TYP.
VI = VDD
MAX.
Unit
1
A
1
A
10
A
1
A
1
A
10
A
100
k
P20 to P22, P24 to P27, P30,
P31, P40, P75 to P77, P120,
P137, P147, P200 to P206,
RESET
ILIH2
P121 to P124
VI = VDD
In input port or
(X1, X2, XT1, XT2, EXCLK,
external clock
EXCLKS)
input
In resonator
connection
Input leakage
ILIL1
current, low
P02, P03, P05, P06, P10 to P12,
VI = VSS
P20 to P22, P24 to P27, P30,
P31, P40, P75 to P77, P120,
P137, P147, P200 to P206,
RESET
ILIL2
P121 to P124
VI = VSS
In input port or
(X1, X2, XT1, XT2, EXCLK,
external clock
EXCLKS)
input
In resonator
connection
On-chip pull-up
RU
resistance
P02, P03, P05, P06, P10 to P12,
VI = VSS, In input port
10
20
P30, P31, P40, P75 to P77,
P120, P147, P200 to P206
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
2.3.2 Supply current characteristics
(TA = 40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V) (1/2)
Parameter
Supply
current
Symbol
IDD1
Conditions
Operating
mode
Note 1
HS (highspeed main)
modeNote 5
fIH = 32 MHz
fIH = 24 MHz
MIN.
Note 3
Note 3
fIH = 16 MHzNote 3
LS (lowspeed main)
modeNote 5
fIH = 8 MHzNote 3,
TA = 40 to + 85C
HS (highspeed main)
modeNote 5
fMX = 20 MHzNote 2,
VDD = 5.0 V
fMX = 20 MHzNote 2,
VDD = 3.0 V
fMX = 10 MHzNote 2,
VDD = 5.0 V
fMX = 10 MHz
VDD = 3.0 V
Note 2
,
Note 2
TYP.
MAX.
Unit
VDD = 5.0 V
5.0
7.5
mA
VDD = 3.0 V
5.0
7.5
mA
VDD = 5.0 V
3.9
5.8
mA
VDD = 3.0 V
3.9
5.8
mA
VDD = 5.0 V
2.9
4.2
mA
VDD = 3.0 V
2.9
4.2
mA
VDD = 3.0 V
1.3
2.0
mA
mA
Square wave input
3.2
4.9
Resonator connection
3.3
5.0
mA
Square wave input
3.2
4.9
mA
Resonator connection
3.3
5.0
mA
Square wave input
2.0
2.9
mA
Resonator connection
2.0
2.9
mA
Square wave input
2.0
2.9
mA
Resonator connection
2.0
2.9
mA
Square wave input
1.2
1.8
mA
Resonator connection
1.2
1.8
mA
LS (lowspeed main)
modeNote 5
,
fMX = 8 MHz
VDD = 3.0 V,
TA = 40 to + 85C
HS (highspeed main)
modeNote 5
fIH = 4 MHzNote 3
VDD = 5.0 V
fPLL = 64 MHz, fCLK = 32 MHz VDD = 3.0 V
5.4
8.5
mA
5.4
8.5
mA
fIH = 4 MHzNote 3
VDD = 5.0 V
fPLL = 64 MHz, fCLK = 16 MHz VDD = 3.0 V
3.3
5.7
mA
3.3
5.7
mA
Subsystem
clock
operation
fSUB = 32.768 kHzNote 4
TA = 40C
Square wave input
4.2
6.0
A
Resonator connection
4.4
6.2
A
fSUB = 32.768 kHzNote 4
TA = +25C
Square wave input
4.2
6.0
A
Resonator connection
4.4
6.2
A
Square wave input
4.3
7.2
A
Resonator connection
4.5
7.4
A
fSUB = 32.768 kHzNote 4
TA = +50C
Square wave input
4.4
8.1
A
Resonator connection
4.6
8.3
A
fSUB = 32.768 kHzNote 4
TA = +85C
Square wave input
5.2
11.4
A
Resonator connection
5.4
11.6
A
fSUB = 32.768 kHzNote 4
TA = +105C
Square wave input
6.9
20.8
A
Resonator connection
7.1
21.0
A
Note 4
fSUB = 32.768 kHz
TA = +70C
(Notes and Remarks are listed on the next page.)
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 24 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS.
The values below the MAX. column include the peripheral operation current.
However, not including the current flowing into the A/D converter, comparator, programmable gain
amplifier, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data
flash rewrite.
2. When high-speed on-chip oscillator and subsystem clock are stopped.
3. When high-speed system clock and subsystem clock are stopped.
4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1
(Ultra-low power consumption oscillation). However, not including the current flowing into the RTC, 12bit interval timer, and watchdog timer.
5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz
LS (low-speed main) mode:
2.7 V VDD 5.5 V@1 MHz to 8 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 25 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
(TA = 40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V) (2/2)
Parameter
Symbol
Supply
Note 2
DD2
I
current
Conditions
TYP.
MAX.
Unit
VDD = 5.0 V
0.72
2.9
mA
VDD = 3.0 V
0.72
2.9
mA
VDD = 5.0 V
0.57
2.3
mA
VDD = 3.0 V
0.57
2.3
mA
VDD = 5.0 V
0.50
1.7
mA
VDD = 3.0 V
0.50
1.7
mA
fIH = 8 MHz
,
TA = 40 to +85C
VDD = 3.0 V
320
910
A
HS (high-
fMX = 20 MHzNote 3,
Square wave input
0.40
1.9
mA
speed main)
VDD = 5.0 V
Resonator connection
0.50
2.0
mA
HALT
HS (high-
mode
speed main)
Note 1
modeNote 7
fIH = 32 MHz
fIH = 24 MHzNote 4
fIH = 16 MHz
LS (lowspeed main)
MIN.
Note 4
Note 4
Note 4
modeNote 7
modeNote 7
Square wave input
0.40
1.9
mA
VDD = 3.0 V
Resonator connection
0.50
2.0
mA
fMX = 10 MHzNote 3,
Square wave input
0.24
1.02
mA
VDD = 5.0 V
Resonator connection
0.30
1.08
mA
Square wave input
0.24
1.02
mA
Resonator connection
0.30
1.08
mA
fMX = 20 MHz
fMX = 10 MHz
Note 3
,
Note 3
,
VDD = 3.0 V
LS (low-
fMX = 8 MHz
Square wave input
130
720
A
speed main)
modeNote 7
VDD = 3.0 V,
TA = 40 to +85C
Resonator connection
170
760
A
HS (high-
fIH = 4 MHzNote 4
VDD = 5.0 V
1.15
4.0
mA
speed main)
fPLL = 64 MHz, fCLK = 32 MHz
VDD = 3.0 V
1.15
4.0
mA
fIH = 4 MHzNote 4
VDD = 5.0 V
0.95
3.2
mA
VDD = 3.0 V
0.95
3.2
mA
Square wave input
0.28
0.70
A
Resonator connection
0.47
0.89
A
Square wave input
0.33
0.70
A
Resonator connection
0.52
0.89
A
fSUB = 32.768 kHz
TA = +50C
Square wave input
0.41
1.90
A
Resonator connection
0.60
2.09
A
fSUB = 32.768 kHzNote 5
TA = +70C
Square wave input
0.54
2.80
A
Resonator connection
0.73
2.99
A
Note 5
Square wave input
1.27
6.10
A
Resonator connection
1.46
6.29
A
Square wave input
3.04
15.5
A
Resonator connection
3.23
15.7
A
modeNote 7
Note 3
,
fPLL = 64 MHz, fCLK = 16 MHz
Subsystem
clock
operation
Note 5
fSUB = 32.768 kHz
TA = 40C
Note 5
fSUB = 32.768 kHz
TA = +25C
Note 5
fSUB = 32.768 kHz
TA = +85C
Note 5
fSUB = 32.768 kHz
TA = +105C
I
Note 6
DD3
STOP
TA = 40C
0.18
0.50
A
mode
TA = +25C
0.23
0.50
A
TA = +50C
0.27
1.70
A
TA = +70C
0.44
2.60
A
TA = +85C
1.17
5.90
A
TA = +105C
2.94
15.3
A
Note 8
(Notes and Remarks are listed on the next page.)
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 26 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS.
The values below the MAX. column include the peripheral operation current.
However, not including the current flowing into the A/D converter, comparator, programmable gain
amplifier, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data
flash rewrite.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator and subsystem clock are stopped.
4. When high-speed system clock and subsystem clock are stopped.
5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and
setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included.
However, not including the current flowing into the 12-bit interval timer and watchdog timer.
6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer.
7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz
LS (low-speed main) mode:
2.7 V VDD 5.5 V@1 MHz to 8 MHz
8. Regarding the value for current operate the subsystem clock in STOP mode, refer to that in HALT mode.
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA =
25C
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 27 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
(TA = 40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Low-speed on-
Symbol
I
Conditions
MIN.
Note 1
FIL
TYP.
MAX.
Unit
0.20
A
0.02
A
0.02
A
0.22
A
chip oscillator
operating current
RTC operating
IRTC
current
Notes 1, 2, 3
12-bit interval
IIT
timer operating
Notes 1, 2, 4
current
fIL = 15 kHz
Watchdog timer
IWDT
operating current
Notes 1, 2, 5
A/D converter
operating current
IADC
A/D converter
reference voltage
current
IADREFNote 1
75.0
A
Temperature
sensor operating
current
ITMPSNote 1
75.0
A
LVD operating
ILVDNotes 1, 7
0.08
A
IFSPNotes 1, 8
2.50
12.2
mA
AVREFP = VDD = 5.0 V
0.21
0.31
mA
AVREFP = VDD = 3.0 V
0.18
0.29
mA
When one comparator channel is
AVREFP = VDD = 5.0 V
41.4
62
A
operating
AVREFP = VDD = 3.0 V
37.2
59
A
When one internal reference voltage
AVREFP = VDD = 5.0 V
14.8
26
A
circuit is operating
AVREFP = VDD = 3.0 V
8.9
20
A
AVREFP = VDD = 5.0 V
3.2
5.1
A
AVREFP = VDD = 3.0 V
2.9
4.9
A
2.50
12.2
mA
Notes 1, 6
When conversion at
maximum speed
Normal mode, AVREFP = VDD = 5.0 V
Low voltage mode, AVREFP = VDD = 3.0 V
1.3
1.7
mA
0.5
0.7
mA
current
Selfprogramming
operating current
Programmable
IPGANote 9
gain amplifier
operating current
Comparator
ICMPNote 10
operating current
IVREF
Programmable
IIREF
Note 11
gain amplifier/
comparator
reference current
source
BGO operating
IBGONote 12
current
SNOOZE
ISNOZNote 1
operating current
ADC operation
The mode is performedNote 13
0.50
1.1
mA
The A/D conversion operations are performed,
2.0
3.04
mA
0.70
1.54
mA
Standard mode, AVREFP = VDD = 5.0 V
CSI/UART operation
(Notes and Remarks are listed on the next page.)
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Sep 29, 2017
Page 28 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
Notes 1. Current flowing to the VDD.
2. When the high-speed on-chip oscillator and high-speed system clock are stopped.
3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed onchip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the
values of either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode.
When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation
includes the operational current of the real-time clock.
4. Current flowing only to the 12-bit interval timer (excluding the operating current of the XT1 oscillator and
fIL operating current). The current of the RL78 microcontrollers is the sum of the values of either IDD1 or
IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT mode.
5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip
oscillator). The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when
the watchdog timer is in operation.
6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of
IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.
7. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1,
IDD2 or IDD3 and ILVD when the LVD circuit is in operation.
8. Current flowing during self-programming operation.
9. Current flowing only to the programmable gain amplifier.
The supply current value of the RL78
microcontrollers is the sum of IDD1, IDD2 or IDD3, and IPGA, when the programmable gain amplifier is
operating in operating mode or in HALT mode.
10. Current flowing only to the comparator. The supply current value of the RL78 microcontrollers is the sum
of IDD1, IDD2 or IDD3, and ICMP, when the comparator is operating.
11. This is the current required to flow to VDD pin of the current circuit that is used as the programmable gain
amplifier and the comparator.
12. Current flowing only during data flash rewrite.
13. See 21.3.3 SNOOZE mode in the RL78/I1A User's Manual for shift time to the SNOOZE mode .
Remarks 1. fIL:
Low-speed on-chip oscillator clock frequency
2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
3. fCLK: CPU/peripheral hardware clock frequency
4. Temperature condition of the TYP. value is TA = 25C
5. Example of calculating current value when using programmable gain amplifier and comparator.
Examples 1) TYP. operating current value when three comparator channels, one internal reference
voltage generator, and PGA are operating (when AVREFP = VDD = 5.0 V)
ICMP × 3 + IVREF + IPGA + IIREF
= 41.4 [A] × 3 + 14.8 [A] × 1 + 210 [A] + 3.2 [A]
= 352.2 [A]
Examples 2) TYP. operating current value when using two comparator channels, without using
internal reference voltage generator (when AVREFP = VDD = 5.0 V)
ICMP × 2 + IIREF
= 41.4 [A] × 2 + 3.2 [A]
= 86.0 [A]
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Sep 29, 2017
Page 29 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
2.4 AC Characteristics
(TA = 40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V)
Items
Instruction cycle (minimum
instruction execution time)
Symbol
TCY
Conditions
Main system
clock (fMAIN)
operation
MIN.
HS (high-speed main) mode
LS (low-speed
main) mode
TA = 40 to +85C
TYP.
Unit
1
s
0.125
1
s
31.3
s
0.03125
1
s
0.125
1
s
fEX
1.0
20.0
MHz
fEXS
32
35
kHz
Subsystem clock (fSUB) operation
In the self
programming
mode
External system clock frequency
MAX.
0.03125
HS (high-speed main) mode
LS (low-speed
main) mode
TA = 40 to +85C
External system clock input high- tEXH, tEXL
level width, low-level width
tEXHS, tEXLS
TI03, TI05, TI06, TI07 input high- tTIH,
level width, low-level width
tTIL
TO03, TO05, TO06, TKBO00,
TKBO01, TKBO10, TKBO11,
TKBO20, TKBO21, TKCO00 to
TKCO05 output frequency
(When duty = 50%)
fTO
Interrupt input high-level width,
low-level width
tINTH,
tINTL
RESET low-level width
tRSL
28.5
30.5
24
ns
13.7
s
2/fMCK+10
ns
4.0 V VDD 5.5 V
8
MHz
2.7 V VDD < 4.0 V
4
MHz
LS (low-speed main)
4.0 V VDD 5.5 V
mode, TA = 40 to +85C
2.7 V VDD < 4.0 V
4
MHz
2
MHz
HS (high-speed main)
mode
INTP0, INTP3, INTP4, INTP9 to INTP11,
INTP20 to INTP23
1
s
10
s
Remark fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKS0n bit of timer mode register 0n (TMR0n). n: Channel number (n = 0
to 7))
R01DS0171EJ0320 Rev.3.20
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2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
Minimum Instruction Execution Time during Main System Clock Operation
TCY vs VDD (HS (high-speed main) mode)
Cycle time TCY [µs]
10
1.0
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
0.1
0.05
0.03125
0.01
0
1.0
2.0
3.0
2.7
4.0
5.0 5.5 6.0
Supply voltage VDD [V]
TCY vs VDD (LS (low-speed main) mode)
Cycle time TCY [µs]
10
1.0
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
0.125
0.1
0.05
0.01
0
1.0
2.0
3.0
2.7
4.0
5.0 5.5 6.0
Supply voltage VDD [V]
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2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
AC Timing Test Points
VIH/VOH
VIL/VOL
VIH/VOH
Test points
VIL/VOL
External System Clock Timing
1/fEX/
1/fEXS
tEXL/
tEXLS
tEXH/
tEXHS
EXCLK/EXCLKS
TI/TO Timing
tTIH
tTIL
TI03, TI05, TI06, TI07
1/fTO
TO03, TO05, TO06, TKBO00, TKBO01, TKBO10,
TKBO11, TKBO20, TKBO21, TKCO00 to TKCO05
Interrupt Request Input Timing
tINTL
tINTH
INTP0, INTP3, INTP4, INTP9 to INTP11,
INTP20 to INTP23
RESET Input Timing
tRSL
RESET
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 32 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
2.5 Peripheral Functions Characteristics
AC Timing Test Points
VIH/VOH
VIH/VOH
Test points
VIL/VOL
VIL/VOL
2.5.1 Serial array unit 0, 4 (UART0, UART1, CSI00, DALI/UART4)
(1) During communication at same potential (UART mode)
(TA = 40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) LS (low-speed main)
Mode
Mode
MIN.
Transfer rate
MAX.
2.7 V VDD 5.5 V
Note 1
Theoretical value of the
maximum transfer rate
fMCK = fCLKNote 2
MIN.
Unit
MAX.
fMCK/6
fMCK/6
bps
5.3
1.3
Mbps
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 32 MHz (2.7 V VDD 5.5 V)
LS (low-speed main) mode:
8 MHz (2.7 V VDD 5.5 V), TA = 40 to +85C
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
UART mode connection diagram (during communication at same potential)
Rx
TxDq
User's device
RL78 microcontroller
Tx
RxDq
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
2.
q: UART number (q = 0, 1), g: PIM and POM number (g = 0, 1)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03))
R01DS0171EJ0320 Rev.3.20
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2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = 40 to +105CNote 5, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
LS (low-speed main)
Mode
Mode
MIN.
tKCY1
tKCY1 4/fCLK
SCKp high-/low-level
tKH1,
width
tKL1
SIp setup time (to SCKp) tSIK1
SCKp cycle time
Note 1
MAX.
500
ns
4.0 V VDD 5.5 V
tKCY1/2 12
tKCY1/2 50
ns
2.7 V VDD 5.5 V
tKCY1/2 18
tKCY1/2 50
ns
4.0 V VDD 5.5 V
44
110
ns
44
110
ns
19
19
ns
tKSI1
Delay time from SCKp to tKSO1
SOp outputNote 3
MIN.
125
2.7 V VDD 5.5 V
SIp hold time (from
SCKp) Note 2
MAX.
Unit
C = 30 pFNote 4
25
25
ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SCKp and SOp output lines.
5. Operating conditions of LS (low-speed main) mode is TA = 40 to +85°C.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM number (g = 1)
2.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
R01DS0171EJ0320 Rev.3.20
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2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = 40 to +105CNote 6, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
HS (high-speed main)
Conditions
LS (low-speed main) Mode Unit
Mode
MIN.
SCKp cycle time
tKCY2
4.0 V VDD 5.5 V
Note 5
2.7 V VDD 5.5 V
MAX.
MIN.
MAX.
20 MHz < fMCK
8/fMCK
ns
fMCK 20 MHz
6/fMCK
6/fMCK
ns
16 MHz < fMCK
8/fMCK
ns
fMCK 16 MHz
6/fMCK
6/fMCK
ns
tKCY2/2
tKCY2/2
ns
SCKp high-/low-
tKH2,
level width
tKL2
SIp setup time
(to SCKp)Note 1
tSIK2
1/fMCK+20
1/fMCK+30
ns
SIp hold time
(from SCKp)Note 2
tKSI2
1/fMCK+31
1/fMCK+31
ns
Delay time from
SCKp to SOp
tKSO2
C = 30 pFNote 4
2/fMCK+
2/fMCK+
44
110
ns
outputNote 3
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SOp output lines.
5. Transfer rate in the SNOOZE mode: MAX. 1 Mbps
6. Operating conditions of LS (low-speed main) mode is TA = 40 to +85C.
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the
SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks
1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM number (g = 1)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 35 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
CSI mode connection diagram (during communication at same potential)
SCK
SCKp
RL78
microcontroller
SIp
SO
SOp
SI
User's device
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1, 2
tKL1, 2
tKH1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
Output data
SOp
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1, 2
tKH1, 2
tKL1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Remarks 1.
2.
Output data
p: CSI number (p = 00)
m: Unit number, n: Channel number (mn = 00)
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Sep 29, 2017
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2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
(4) Communication at different potential (2.5 V, 3 V) (UART mode) (1/2)
(TA = 40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) LS (low-speed main)
Mode
MIN.
Transfer
Reception
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V
rate
Theoretical value of the
Unit
Mode
MAX.
MIN.
MAX.
fMCK/6Note 1
fMCK/6Note 1
bps
5.3
1.3
Mbps
fMCK/6Note 1
fMCK/6Note 1
bps
5.3
1.3
Mbps
maximum transfer rate
fMCK = fCLKNote 2
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V
Theoretical value of the
maximum transfer rate
fMCK = fCLKNote 2
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode:
32 MHz (2.7 V VDD 5.5 V)
LS (low-speed main) mode:
8 MHz (2.7 V VDD 5.5 V), TA = 40 to +85C.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode
for the TxDq pin by using port input mode register g (PIMg) and port output mode register g
(POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
Remarks 1.
Vb[V]: Communication line voltage
2.
q: UART number (q = 0, 1), g: PIM and POM number (g = 0, 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03)
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Sep 29, 2017
Page 37 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
(4) Communication at different potential (2.5 V, 3 V) (UART mode) (2/2)
(TA = 40 to +105C Note 5, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) Mode
MIN.
Transfer rate
Transmission 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V
Theoretical value of the
maximum transfer rate
Cb = 50 pF, Rb = 1.4 k, Vb = 2.7 V
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V
Theoretical value of the
maximum transfer rate
Cb = 50 pF, Rb = 2.7 k, Vb = 2.3 V
Notes 1.
MAX.
LS (low-speed main) Unit
Mode
MIN.
MAX.
Note 1
Note 1
bps
2.8Note 2
2.8Note 2
Mbps
Note 3
Note 3
bps
1.2Note 4
1.2Note 4
Mbps
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V VDD 5.5 V and 2.7 V Vb 4.0 V
1
Maximum transfer rate =
{Cb × Rb × ln (1
Baud rate error (theoretical value) =
2.2
Vb )} × 3
[bps]
2.2
1
{Cb × Rb × ln (1 Vb )}
Transfer rate 2
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2.
This value as an example is calculated when the conditions described in the “Conditions” column are
3.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
met. See Note 1 above to calculate the maximum transfer rate under conditions of the customer.
maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V VDD < 4.0 V and 2.3 V Vb 2.7 V
1
Maximum transfer rate =
{Cb × Rb × ln (1
Baud rate error (theoretical value) =
2.0
Vb )} × 3
[bps]
2.0
1
{Cb × Rb × ln (1 Vb )}
Transfer rate 2
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
4.
This value as an example is calculated when the conditions described in the “Conditions” column are
5.
Operating conditions of LS (low-speed main) mode is TA = 40 to +85C.
met. See Note 3 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode
for the TxDq pin by using port input mode register g (PIMg) and port output mode register g
(POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
Remarks 1.
Rb[]: Communication line (TxDq) pull-up resistance,
Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
2.
q: UART number (q = 0, 1), g: PIM and POM number (g = 0, 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03))
R01DS0171EJ0320 Rev.3.20
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Page 38 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
UART mode connection diagram (during communication at different potential)
Vb
Rb
TxDq
Rx
User's device
RL78 microcontroller
RxDq
Tx
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance)
mode for the TxDq pin by using port input mode register g (PIMg) and port output mode
register g (POMg).
Remarks 1. Rb[]: Communication line (TxDq) pull-up resistance, Vb[V]: Communication line voltage
2.
q: UART number (q = 0, 1), g: PIM and POM number (g = 0, 1)
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 39 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
(5) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output)
(TA = 40 to +105C Note 3, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) Mode
MIN.
SCKp cycle time
SCKp high-level
width
SCKp low-level
width
SIp setup time
(to SCKp)Note 1
tKCY1
tKH1
tKL1
MAX.
LS (low-speed
main) Mode
MIN.
Unit
MAX.
tKCY1 2/fCLK 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
200
1150
ns
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
300
1150
ns
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
tKCY1/2 50
tKCY1/2 75
ns
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
tKCY1/2
120
tKCY1/2
170
ns
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
tKCY1/2 7
tKCY1/2 50
ns
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
tKCY1/2 10
tKCY1/2 50
ns
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
81
479
ns
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
177
479
ns
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
10
19
ns
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
10
19
ns
Cb = 30 pF, Rb = 1.4 k
tSIK1
Cb = 30 pF, Rb = 2.7 k
tKSI1
SIp hold time
(from SCKp)
Note 1
Cb = 30 pF, Rb = 2.7 k
Delay time from
SCKp to SOp
outputNote 1
tKSO1
SIp setup time
(to SCKp)Note 2
tSIK1
tKSI1
SIp hold time
(from SCKp)
Note 2
Delay time from
SCKp to
SOp outputNote 2
tKSO1
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
60
100
ns
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
130
195
ns
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
44
110
ns
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
44
110
ns
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
10
19
ns
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
10
19
ns
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
10
25
ns
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
10
25
ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. Operating conditions of LS (low-speed main) mode is TA = 40 to +85C.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for
the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode
register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
Remarks 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM number (g = 1)
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Sep 29, 2017
Page 40 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
(6) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output)
(TA = 40 to +105C Note 3, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode LS (low-speed main) Mode Unit
MIN.
SCKp cycle
tKCY1
time
tKCY1 4/fCLK 4.0 V VDD 5.5 V,
2.7 V Vb 4.0 V,
MAX.
MIN.
MAX.
300
1150
ns
500
1150
ns
tKCY1/2 75
tKCY1/2 75
ns
tKCY1/2 170
tKCY1/2 170
ns
tKCY1/2 12
tKCY1/2 50
ns
tKCY1/2 18
tKCY1/2 50
ns
81
479
ns
177
479
ns
19
19
ns
19
19
ns
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
SCKp high-level tKH1
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
width
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
SCKp low-level
tKL1
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
width
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
SIp setup time
(to SCKp)
tSIK1
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
Note 1
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
SIp hold time
(from SCKp)
tKSI1
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
Note 1
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
Delay time from tKSO1
SCKp to
SOp outputNote 1
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
100
100
ns
195
195
ns
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
SIp setup time tSIK1
(to SCKp)Note 2
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
44
110
ns
44
110
ns
19
19
ns
19
19
ns
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
SIp hold time
(from SCKp)
tKSI1
Note 2
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
Delay time from tKSO1
SCKp to
SOp outputNote 2
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
25
25
ns
25
25
ns
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
Notes
1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. Operating conditions of LS (low-speed main) mode is TA = 40 to +85C.
(Caution and Remarks are listed on the next page.)
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
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2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for
the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode
register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
CSI mode connection diagram (during communication at different potential)
Vb
Rb
Vb
Rb
SCKp
RL78
microcontroller
SCK
SIp
SO
SOp
SI
User's device
Remarks 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number
(g = 1)
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 42 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
Output data
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
Output data
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for
the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode
register g (POMg).
Remark
p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g
= 1)
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 43 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
(7) DALI/UART4 mode
(TA = 40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) LS (low-speed main)
Mode
MIN.
Transfer rate
Unit
Mode
MAX.
MIN.
MAX.
fMCK/12
fMCK/12
bps
2.6
0.6
Mbps
Maximum transfer rate theoretical value
HS: fCLK = 32 MHz, fMCK = fCLK
LS: fCLK = 8 MHz, fMCK = fCLK
Remark
fMCK: Operation clock frequency of DALI/UART.
(Operation clock to be set by the serial clock select register mn (SPS4).)
Caution Operating conditions of LS (low-speed main) mode is TA = 40 to +85C.
R01DS0171EJ0320 Rev.3.20
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Page 44 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
2.5.2 Serial interface IICA
(1) I2C standard mode
(TA = 40 to +105C Note 3, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
Standard mode: fCLK 1 MHz
HS (high-speed LS (low-speed
main) Mode
main) Mode
MIN.
MAX.
MIN.
MAX.
0
100
0
100
Unit
SCLA0 clock frequency
fSCL
Setup time of restart condition
tSU:STA
4.7
4.7
s
tHD:STA
4.0
4.0
s
tLOW
4.7
4.7
s
Hold time
Note 1
Hold time when SCLA0 = “L”
kHz
Hold time when SCLA0 = “H”
tHIGH
4.0
4.0
s
Data setup time (reception)
tSU:DAT
250
250
ns
Data hold time (transmission)Note 2
tHD:DAT
0
Setup time of stop condition
tSU:STO
4.0
4.0
s
Bus-free time
tBUF
4.7
4.7
s
Notes 1.
3.45
0
3.45
s
The first clock pulse is generated after this period when the start/restart condition is detected.
2.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
3.
Operating conditions of LS (low-speed main) mode is TA = 40 to +85C.
(acknowledge) timing.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line
pull-up resistor) at that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 k
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 45 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
(2) I2C fast mode
(TA = 40 to +105C Note 3, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
HS (high-speed LS (low-speed
Conditions
fast mode: fCLK 3.5 MHz
main) Mode
main) Mode
MIN.
MAX.
MIN.
MAX.
0
400
0
400
Unit
SCLA0 clock frequency
fSCL
Setup time of restart condition
tSU:STA
0.6
0.6
s
tHD:STA
0.6
0.6
s
tLOW
1.3
1.3
s
Hold time
Note 1
Hold time when SCLA0 = “L”
kHz
Hold time when SCLA0 = “H”
tHIGH
0.6
0.6
s
Data setup time (reception)
tSU:DAT
100
100
ns
Data hold time (transmission)Note 2
tHD:DAT
0
Setup time of stop condition
tSU:STO
0.6
0.6
s
Bus-free time
tBUF
1.3
1.3
s
Notes 1.
0.9
0
0.9
s
The first clock pulse is generated after this period when the start/restart condition is detected.
2.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
3.
Operating conditions of LS (low-speed main) mode is TA = 40 to +85C.
(acknowledge) timing.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line
pull-up resistor) at that time in each mode are as follows.
Cb = 320 pF, Rb = 1.1 k
Fast mode:
IICA serial transfer timing
tLOW
SCLA0
tHD:DAT
tHD:STA
tHIGH
tSU:STA
tHD:STA
tSU:STO
tSU:DAT
SDAA0
tLOW
Stop
condition
Start
condition
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Restart
condition
Stop
condition
Page 46 of 105
RL78/I1A
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
2.6 Analog Characteristics
2.6.1 A/D converter characteristics
Classification of A/D converter characteristics
Reference Voltage
Reference voltage (+) =
AVREFP
Reference voltage () =
Input channel
AVREFM
Reference voltage (+) = VDD
Reference voltage () = VSS
ANI0 to ANI2, ANI4 to ANI7
See 2.6.1 (1).
See 2.6.1 (3).
ANI16 to ANI19
See 2.6.1 (2).
Internal reference voltage
See 2.6.1 (1).
Reference voltage (+) = VBGR
Reference voltage () =
AVREFM
See 2.6.1 (4).
Temperature sensor output
voltage
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2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
(1) When reference voltage (+)= AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage () =
AVREFM/ANI1 (ADREFM = 1), target pin: ANI2, ANI4 to ANI7, internal reference voltage, and temperature
sensor output voltage
(TA = 40 to +105C, 2.7 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference
voltage () = AVREFM = 0 V)
Parameter
Symbol
Conditions
Resolution
RES
Overall errorNote 1
AINL
10-bit resolution
AVREFP = VDDNote 3
Conversion time
tCONV
10-bit resolution
Target pin: ANI2, ANI4 to
ANI7
MIN.
TYP.
MAX.
10
bit
1.2
3.5
LSB
8
Unit
3.6 V VDD 5.5 V
2.125
39
s
2.7 V VDD 5.5 V
3.1875
39
s
10-bit resolution
3.6 V VDD 5.5 V
Target pin: Internal reference 2.7 V VDD 5.5 V
voltage, and temperature
sensor output voltage
(HS (high-speed main)
mode)
2.375
39
s
3.5625
39
s
Zero-scale errorNotes 1, 2
EZS
10-bit resolution
AVREFP = VDDNote 3
0.25
%FSR
Full-scale errorNotes 1, 2
EFS
10-bit resolution
AVREFP = VDDNote 3
0.25
%FSR
Integral linearity errorNote 1
ILE
10-bit resolution
AVREFP = VDDNote 3
2.5
LSB
Differential linearity error
DLE
10-bit resolution
AVREFP = VDDNote 3
1.5
LSB
VAIN
ANI2, ANI4 to ANI7
AVREFP
V
Note 1
Analog input voltage
0
Internal reference voltage
(HS (high-speed main) mode)
Temperature sensor output voltage
(HS (high-speed main) mode)
VBGR
Note 4
VTMPS25Note 4
V
V
Notes 1. Excludes quantization error (1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add 1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add 0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/Differential linearity error: Add 0.5 LSB to the MAX. value when AVREFP = VDD.
4. See 2.6.2 Temperature sensor/internal reference voltage characteristics.
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2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
(2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage () =
AVREFM/ANI1 (ADREFM = 1), target pin: ANI16 to ANI19
(TA = 40 to +105C, 2.7 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference
voltage () = AVREFM = 0 V)
Parameter
Resolution
Symbol
Conditions
MIN.
RES
Overall error
Note 1
AINL
TYP.
8
10-bit resolution
1.2
MAX.
Unit
10
bit
5.0
LSB
AVREFP = VDDNotes 3
Conversion time
tCONV
3.6 V VDD 5.5 V
2.125
39
s
Target ANI pin : ANI16 to ANI19 2.7 V VDD 5.5 V
3.1875
10-bit resolution
39
s
EZS
10-bit resolution
AVREFP = VDDNotes 3
0.35
%FSR
EFS
10-bit resolution
AVREFP = VDDNotes 3
0.35
%FSR
Integral linearity errorNote ILE
10-bit resolution
3.5
LSB
1
AVREFP = VDDNotes 3
2.0
LSB
AVREFP
V
Zero-scale error
Notes 1, 2
Full-scale errorNotes 1, 2
Differential linearity
DLE
errorNote 1
10-bit resolution
AVREFP = VDDNotes 3
Analog input voltage
VAIN
ANI16 to ANI19
0
and VDD
Notes 1. Excludes quantization error (1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add 1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add 0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/Differential linearity error: Add 0.5 LSB to the MAX. value when AVREFP = VDD.
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2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
(3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage () = VSS (ADREFM =
0), target pin: ANI0 to ANI2, ANI4 to ANI7, ANI16 to ANI19, internal reference voltage, and temperature
sensor output voltage
(TA = 40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage () = VSS)
Parameter
Resolution
Overall error
Symbol
Conditions
RES
Note 1
MIN.
TYP.
8
Unit
10
bit
7.0
LSB
AINL
10-bit resolution
tCONV
10-bit resolution
3.6 V VDD 5.5 V
2.125
39
s
Target pin: ANI0 to ANI2,
2.7 V VDD 5.5 V
3.1875
39
s
10-bit resolution
3.6 V VDD 5.5 V
2.375
39
s
Target pin: Internal
2.7 V VDD 5.5 V
3.5625
39
s
EZS
10-bit resolution
0.60
%FSR
Full-scale error
EFS
10-bit resolution
0.60
%FSR
Integral linearity errorNote 1
ILE
10-bit resolution
4.0
LSB
Differential linearity errorNote 1 DLE
10-bit resolution
2.0
LSB
Analog input voltage
ANI0 to ANI2, ANI4 to ANI7
0
VDD
V
ANI16 to ANI19
0
VDD
V
Conversion time
ANI4 to ANI7, ANI16 to
1.2
MAX.
ANI19
Conversion time
tCONV
reference voltage, and
temperature sensor output
voltage (HS (high-speed
main) mode)
Zero-scale error
Notes 1, 2
Notes 1, 2
VAIN
Internal reference voltage
VBGR
Note 3
V
(HS (high-speed main) mode)
Temperature sensor output voltage
VTMPS25Note 3
V
(HS (high-speed main) mode)
Notes 1. Excludes quantization error (1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. See 2.6.2 Temperature sensor/internal reference voltage characteristics.
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2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
(4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage
() = AVREFM/ANI1 (ADREFM = 1), target pin: ANI0, ANI2, ANI4 to ANI7, ANI16 to ANI19
(TA = 40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VBGRNote 3, Reference voltage () =
AVREFM = 0 VNote 4, HS (high-speed main) mode)
Parameter
Symbol
Resolution
Conditions
MIN.
RES
Conversion time
Zero-scale error
Notes 1, 2
Integral linearity error
Note 1
Differential linearity error
Note 1
Analog input voltage
TYP.
MAX.
8
Unit
bit
39
s
8-bit resolution
0.60
%FSR
ILE
8-bit resolution
2.0
LSB
DLE
8-bit resolution
1.0
LSB
tCONV
8-bit resolution
EZS
VAIN
17
0
VBGR
Note 3
V
Notes 1. Excludes quantization error (1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. See 2.6.2 Temperature sensor/internal reference voltage characteristics.
4. When reference voltage () = VSS, the MAX. values are as follows.
Zero-scale error: Add 0.35%FSR to the MAX. value when reference voltage () = AVREFM.
Integral linearity error: Add 0.5 LSB to the MAX. value when reference voltage () = AVREFM.
Differential linearity error: Add 0.2 LSB to the MAX. value when reference voltage () = AVREFM.
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Page 51 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
2.6.2 Temperature sensor/internal reference voltage characteristics
(TA = 40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V, HS (high-speed main) mode)
Parameter
Symbol
Conditions
VTMPS25
Setting ADS register = 80H, TA = +25C
Internal reference voltage
VBGRT
Setting ADS register = 81H
Temperature coefficient
FVTMPS
Temperature sensor that depends on the
Temperature sensor output voltage
MIN.
TYP.
MAX.
1.05
1.38
1.45
3.6
Unit
V
1.5
V
mV/C
temperature
Operation stabilization wait time
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tAMP
5
s
Page 52 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
2.6.3 Programmable gain amplifier
(TA = 40 to +105C, 2.7 V AVREFP = VDD 5.5 V, VSS = AVREFM = 0 V)
Parameter
Symbol
Input offset voltage
VIOPGA
Input voltage range
VIPGA
Gain errorNote 1
Conditions
MIN.
TYP.
MAX.
Unit
5
10
mV
0.9VDD/
gain
V
4, 8 times
1
%
16 times
1.5
%
0
2
32 times
Slew rateNote 1
SRRPGA
SRFPGA
Operation stabilization wait timeNote 2
tPGA
%
V/s
4.0 V VDD 5.5 V
4, 8 times
16, 32 times
1.4
V/s
2.7 V VDD < 4.0 V
4, 8 times
1.8
V/s
16, 32 times
0.5
V/s
4.0 V VDD 5.5 V
4, 8 times
3.2
V/s
16, 32 times
1.4
V/s
2.7 V VDD < 4.0 V
4, 8 times
1.2
V/s
16, 32 times
0.5
V/s
4, 8 times
5
s
16, 32 times
10
s
Rising
edge
Falling
edge
4
Notes 1. When VIPGA = 0.1VDD/gain to 0.9VDD/gain.
2. Time required until a state is entered where the DC and AC specifications of the PGA are satisfied after
the PGA operation has been enabled (PGAEN = 1).
Remark These characteristics apply when AVREFM is selected as GND of the PGA by using the CVRVS1 bit.
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Page 53 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
2.6.4 Comparator
(TA = 40 to +105C, 2.7 V AVREFP = VDD 5.5 V, VSS = AVREFM = 0 V)
Parameter
Symbol
Input offset voltage
VIOCMP
Input voltage range
VICMP
Conditions
MIN.
CMP0P to CMP5P
CMPCOM
VIREF
Internal reference voltage deviation
TYP.
MAX.
Unit
5
40
mV
0
VDD
V
0.045
0.9VDD
V
2
LSB
1
LSB
150
ns
CmRVM register values: 7FH to 80H
(m = 0 to 2)
Other than above
Response time
Operation stabilization wait time
Note 1
Reference voltage stabilization wait
tCR, tCF
Input amplitude = 100 mV
tCMP
3.3 V VDD 5.5 V
1
s
2.7 V VDD < 3.3 V
3
s
10
s
tVR
CVRE: 0 to 1
70
Note 2
time
Notes 1. Time required until a state is entered where the DC and AC specifications of the comparator are
satisfied after the operation of the comparator has been enabled (CMPnEN bit = 1: n = 0 to 5)
2. Enable comparator output (CnOE bit = 1; n = 0 to 5) after enabling operation of the internal reference
voltage generator (by setting the CVREm bit to 1; m = 0 to 2) and waiting for the operation stabilization
time to elapse.
Remark These characteristics apply when AVREFP is selected as the power supply source of the internal reference
voltage by using the CVRVS0 bit, and when AVREFM is selected as GND of the internal reference voltage
by using the CVRVS1 bit.
Output voltage VO
tCR
tCF
+100 mV
Input voltage VIN
Comparator
ref. voltage
-100 mV
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Page 54 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
2.6.5 POR circuit characteristics
(TA = 40 to +105C, VSS = 0 V)
Parameter
Detection voltage
Minimum pulse widthNote
Symbol
MIN.
TYP.
MAX.
Unit
VPOR
Power supply rise time
Conditions
1.45
1.51
1.57
V
VPDR
Power supply fall time
1.44
1.50
1.56
TPW
V
s
300
Note Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time
required for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode
is entered or the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the
clock operation status control register (CSC).
TPW
Supply voltage (VDD)
VPOR
VPDR or 0.7 V
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Page 55 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
2.6.6 LVD circuit characteristics
LVD Detection Voltage of Reset Mode and Interrupt Mode
(TA = 40 to +105C, VPDR VDD 5.5 V, VSS = 0 V)
Parameter
Detection
Symbol
Supply voltage level
VLVD0
voltage
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
Minimum pulse width
Conditions
MIN.
TYP.
MAX.
Unit
Power supply rise time
3.97
4.06
4.14
V
Power supply fall time
3.89
3.98
4.06
V
Power supply rise time
3.67
3.75
3.82
V
Power supply fall time
3.59
3.67
3.74
V
Power supply rise time
3.06
3.13
3.19
V
Power supply fall time
2.99
3.06
3.12
V
Power supply rise time
2.95
3.02
3.08
V
Power supply fall time
2.89
2.96
3.02
V
Power supply rise time
2.85
2.92
2.97
V
Power supply fall time
2.79
2.86
2.91
V
Power supply rise time
2.75
2.81
2.87
V
Power supply fall time
2.70
2.75
2.81
V
tLW
s
300
Detection delay time
300
s
LVD Detection Voltage of Interrupt & Reset Mode
(TA = 40 to +105C, VPDR VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Interrupt and reset
VLVD0
mode
VLVD1
Conditions
MIN.
TYP.
MAX.
Unit
2.70
2.75
2.81
V
Rising release reset voltage
2.85
2.92
2.97
V
Falling interrupt voltage
2.79
2.86
2.91
V
Rising release reset voltage
2.95
3.02
3.08
V
Falling interrupt voltage
2.89
2.96
3.02
V
Rising release reset voltage
3.97
4.06
4.14
V
Falling interrupt voltage
3.89
3.98
4.06
V
MIN.
TYP.
MAX.
Unit
54
V/ms
VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage: 2.7 V
VLVD2
VLVD3
LVIS1, LVIS0 = 1, 0
LVIS1, LVIS0 = 0, 1
LVIS1, LVIS0 = 0, 0
2.6.7 Supply voltage rise inclination characteristics
(TA = 40 to +105C, VSS = 0 V)
Parameter
Supply voltage rise
Symbol
Conditions
SVDD
Caution Keep the internal reset status by using the LVD circuit or an external reset signal until VDD rises to
within the operating voltage range shown in 32.4 AC Characteristics.
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Page 56 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
2.7 RAM Data Retention Characteristics
(TA = 40 to +105C, VSS = 0 V)
Parameter
Data retention supply voltage
Symbol
Note 2
Conditions
MIN.
Note 1
VDDDR
1.44
TYP.
MAX.
Unit
5.5
V
Note The value depends on the POR detection voltage. When the voltage drops, the RAM data is retained before
a POR reset is effected, but RAM data is not retained when a POR reset is effected.
Caution When CPU is operated at the voltage of out of the operation voltage range, RAM data is not
retained. Therefore, set STOP mode before the supplied voltage is below the operation voltage
range.
STOP mode
Operation mode
RAM Data retention
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
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Page 57 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
2.8 Flash Memory Programming Characteristics
(TA = 40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
CPU/peripheral hardware clock
Symbol
Conditions
MIN.
fCLK
2.7 V VDD 5.5 V
Cerwr
Retained for 20 years, TA = 85CNote 3
TYP.
MAX.
Unit
32
MHz
1
frequency
Number of code flash
rewrites
Retained for 1 year, TA = 25CNote 3
Number of data flash
rewrites
1,000
Times
Notes 1, 2, 3
Notes 1, 2, 3
1,000,000
Note 3
Retained for 5 years, TA = 85C
100,000
Retained for 20 years, TA = 85CNote 3
10,000
Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after
the rewrite.
2. When using flash memory programmer and Renesas Electronics self programming library
3. These are the characteristics of the flash memory and the results obtained from reliability testing by
Renesas Electronics Corporation.
2.9 Dedicated Flash Memory Programmer Communication (UART)
(TA = 40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Transfer rate
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Symbol
Conditions
During serial programming
MIN.
115.2 k
TYP.
MAX.
Unit
1M
bps
Page 58 of 105
2. ELECTRICAL SPECIFICATIONS (G: Industrial applications, TA = 40 to +105C)
RL78/I1A
2.10 Timing of Entry to Flash Memory Programming Modes
(TA = 40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
How long from when an external
tSUINIT
Conditions
MIN.
TYP.
POR and LVD reset must end before the
MAX.
Unit
100
ms
external reset ends.
reset ends until the initial
communication settings are
specified
How long from when the TOOL0 pin tSU
POR and LVD reset must end before the
is placed at the low level until an
external reset ends.
10
s
1
ms
external reset ends
How long the TOOL0 pin must be
kept at the low level after a reset
tHD
POR and LVD reset must end before the
external reset ends.
ends
(except soft processing time)
RESET
723 µs + tHD
processing
time
1-byte data for setting mode
TOOL0
tSU
tSUINIT
The low level is input to the TOOL0 pin.
The external reset ends (POR and LVD reset must end before the pin reset ends.).
The TOOL0 pin is set to the high level.
Complete the baud rate setting by UART reception.
Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within
100 ms from when the resets end.
tSU:
How long from when the TOOL0 pin is placed at the low level until an external reset ends
tHD:
How long to keep the TOOL0 pin at the low level from when the external and internal resets end
(except soft processing time)
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Page 59 of 105
RL78/I1A
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
3. ELECTRICAL SPECIFICATIONS
(M: Industrial applications, TA = 40 to +125C)
In this chapter, shows the electrical specifications of the target products.
Target products (M: Industrial applications): TA = 40 to +125C
R5F107xxMxx
Cautions 1. The RL78/I1A has an on-chip debug function, which is provided for development and
evaluation. Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded
when this function is used, and product reliability therefore cannot be guaranteed. Renesas
Electronics is not liable for problems occurring when the on-chip debug function is used.
2. The pins mounted depend on the product. See 2.1 Port Function to 2.2.1 Functions for each
product in the RL78/I1A User's Manual.
3. When any of these products are used at 105°C or lower, see 2. ELECTRICAL SPECIFICATIONS
(TA = 40 to +105°C).
R01DS0171EJ0320 Rev.3.20
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Page 60 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
3.1 Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25C) (1/2)
Parameter
Symbols
Supply voltage
VDD
REGC pin input voltage
VIREGC
Conditions
REGC
Ratings
Unit
0.5 to +6.5
V
0.3 to +2.8
V
and 0.3 to VDD +0.3Note 1
Input voltage
VI1
P02, P03, P05, P06, P10 to P12, P20 to P22,
0.3 to VDD +0.3Note 2
V
0.3 to VDD +0.3Note 2
V
0.3 to VDD +0.3
V
P24 to P27, P30, P31, P40, P75 to P77,
P120 to P124, P137, P147, P200 to P206,
EXCLK, EXCLKS, RESET
Output voltage
VO1
P02, P03, P05, P06, P10 to P12, P20 to P22,
P24 to P27, P30, P31, P40, P75 to P77, P120,
P147, P200 to P206
Analog input voltage
VAI1
ANI0 to ANI2, ANI4 to ANI7, ANI16 to ANI19
and 0.3 to AVREF(+)
+0.3Notes 2, 3
Notes 1.
Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
This value regulates the
absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it.
2.
Must be 6.5 V or lower.
3.
Do not exceed AV REF(+) + 0.3 V in case of A/D conversion target pin.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remarks 1.
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of
the port pins.
2. AVREF (+): + side reference voltage of the A/D converter.
3. VSS : Reference voltage
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Page 61 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
Absolute Maximum Ratings (TA = 25C) (2/2)
Parameter
Output current, high
Symbols
IOH1
Conditions
Per pin
Ratings
Unit
40
mA
P02, P03, P40, P120
70
mA
P05, P06, P10 to P12, P30, P31,
100
mA
0.5
mA
2
mA
40
mA
P02, P03, P05, P06, P10 to P12,
P30, P31, P40, P75 to P77, P120,
P147, P200 to P206
Total of all pins
170 mA
P75 to P77, P147, P200 to P206
IOH2
Per pin
P20 to P22, P24 to P27
Total of all pins
Output current, low
IOL1
Per pin
P02, P03, P05, P06, P10 to P12,
P30, P31, P40, P75 to P77, P120,
P147, P200 to P206
Total of all pins
P02, P03, P40, P120
70
mA
170 mA
P05, P06, P10 to P12, P30, P31,
100
mA
1
mA
5
mA
In normal operation mode
40 to +125
C
In flash memory programming mode
40 to +105
P75 to P77, P147, P200 to P206
IOL2
Per pin
P20 to P22, P24 to P27
Total of all pins
Operating ambient
TA
temperature
Storage temperature
Tstg
65 to +150
C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 62 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
3.2 Oscillator Characteristics
3.2.1 X1, XT1 oscillator characteristics
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Resonator
X1 clock
Ceramic resonator/
frequency (fX)Note
crystal resonator
XT1 clock frequency
Crystal resonator
Conditions
MIN.
TYP.
1.0
32
32.768
MAX.
Unit
20.0
MHz
35
kHz
(fXT)Note
Note Indicates only permissible oscillator frequency ranges. See AC Characteristics for instruction execution
time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the
oscillator characteristics.
Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check
the X1 clock oscillation stabilization time using the oscillation stabilization time counter status
register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register
and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the
oscillation stabilization time with the resonator to be used.
Remark
When using the X1 oscillator and XT1 oscillator, see 5.4 System Clock Oscillator in the RL78/I1A
User's Manual.
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 63 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
3.2.2 On-chip oscillator characteristics
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V)
Oscillators
Parameters
High-speed on-chip oscillator
Conditions
fIH
MIN.
TYP.
MAX.
Unit
1
32
MHz
clock frequencyNote 1
High-speed on-chip oscillator
TA = 20 to 85C
1
+1
%
clock frequency accuracyNote 2
TA = 40 to 105C
1.5
+1.5
%
TA = 40 to 125C
2
+2
%
When 16 MHz selected
Low-speed on-chip oscillator
fIL
15
kHz
clock frequency
15
Low-speed on-chip oscillator
+15
%
clock frequency accuracy
Notes 1. Frequency can be selected in a high-speed on-chip oscillator. Selected by bits 0 to 3 of option byte
(000C2H/010C2H).
2. This indicates the oscillator characteristics only. See AC Characteristics for instruction execution
time.
Remark
When using the device at an ambient temperature that exceeds TA = 105C, the selectable oscillation
frequency is 16 MHz max.
3.2.3 PLL characteristics
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
PLL input clock
Symbol
fPLLIN
frequencyNote
PLL output clock
Conditions
MIN.
TYP.
MAX.
High-speed system clock is selected (fMX = 4 MHz)
3.92
4.00
4.08
MHz
High-speed on-chip oscillator clock is selected (fIH = 4 MHz)
3.92
4.00
4.08
MHz
fPLL
fPLLIN 16
Unit
MHz
frequencyNote
Note This only indicates the oscillator characteristics. See AC Characteristics for instruction execution time.
Remark
When using the device at an ambient temperature that exceeds TA = 105C, only 16 MHz (fPLL 1/4)
can be selected as the CPU operating frequency.
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 64 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
3.3 DC Characteristics
3.3.1 Pin characteristics
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V)
Items
Symbol
Output current,
highNote 1
IOH1
IOH2
Notes 1.
Conditions
MIN.
TYP.
MAX.
Unit
Per pin for P02, P03, P05, P06, P10 to P12,
P30, P31, P40, P75 to P77, P120, P147,
P200 to P206
4.0 V VDD 5.5 V
3.0Note 2
mA
2.7 V VDD < 4.0 V
1.0
mA
Total of P02, P03, P40, P120
(When duty 70%Note 3)
4.0 V VDD 5.5 V
9.0
mA
2.7 V VDD < 4.0 V
3.0
mA
Total of P05, P06, P10 to P12, P30, P31,
P75 to P77, P147, P200 to P206
(When duty 70%Note 3)
4.0 V VDD 5.5 V
21.0
mA
2.7 V VDD < 4.0 V
6.0
mA
Total of all pins
(When duty 70%Note 3)
4.0 V VDD 5.5 V
21.0
mA
2.7 V VDD < 4.0 V
9.0
mA
Per pin for P20 to P22, P24 to P27
2.7 V VDD 5.5 V
Total of all pins
(When duty 70%Note 3)
2.7 V VDD 5.5 V
0.1
Note 2
0.4
mA
mA
Value of current at which the device operation is guaranteed even if the current flows from the VDD
pin to an output pin.
2.
However, do not exceed the total current value.
3.
Specification under conditions where the duty factor 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated
with the following expression (when changing the duty factor from 70% to n%).
Total output current of pins = (IOH × 0.7)/(n × 0.01)
Where n = 80% and IOH = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Caution P02, P10 to P12 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 65 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V)
Items
Symbol
Output current,
lowNote 1
IOL1
Conditions
Per pin for P02, P03, P05, P06,
P10 to P12, P30, P31, P40,
P75 to P77, P120, P147, P200 to P206
Notes 1.
4.0 V VDD 5.5 V
2.7 V VDD < 4.0 V
TYP.
MAX.
Unit
Note 2
mA
Note 2
mA
8.5
1.5
4.0 V VDD 5.5 V
20.0
mA
2.7 V VDD < 4.0 V
5.0
mA
Total of P05, P06, P10 to P12, P30, P31, 4.0 V VDD 5.5 V
P75 to P77, P147, P200 to P206
2.7 V VDD < 4.0 V
(When duty 70%Note 3)
20.0
mA
10.0
mA
Total of all pins
(When duty 70%Note 3)
4.0 V VDD 5.5 V
40.0
mA
2.7 V VDD < 4.0 V
15.0
mA
Per pin for P20 to P22, P24 to P27
2.7 V VDD 5.5 V
Total of all pins
(When duty 70%Note 3)
2.7 V VDD 5.5 V
Total of P02, P03, P40, P120
(When duty 70%Note 3)
IOL2
MIN.
Note 2
0.4
1.6
mA
mA
Value of current at which the device operation is guaranteed even if the current flows from an output
pin to the VSS pin.
2.
However, do not exceed the total current value.
3.
Specification under conditions where the duty factor 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated
with the following expression (when changing the duty factor from 70% to n%).
Total output current of pins = (IOL × 0.7)/(n × 0.01)
Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 66 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V)
Items
Input voltage,
Symbol
VIH1
Conditions
P02, P03, P05, P06, P10 to P12,
MIN.
TYP.
MAX.
Unit
Normal input buffer
0.8VDD
VDD
V
TTL input buffer
4.0 V VDD 5.5 V
2.1
VDD
V
TTL input buffer
3.3 V VDD 4.0 V
2.0
VDD
V
TTL input buffer
2.7 V VDD 3.3 V
1.5
VDD
V
Normal input buffer
0
0.2VDD
V
TTL input buffer
4.0 V VDD 5.5 V
0
0.8
V
TTL input buffer
3.3 V VDD 4.0 V
0
0.5
V
TTL input buffer
2.7 V VDD 3.3 V
0
0.32
V
P20 to P22, P24 to P27, P30, P31, P40,
high
P75 to P77, P120 to P124, P137, P147,
P200 to P206, EXCLK, EXCLKS,
RESET
VIH2
Input voltage, low VIL1
P03, P10, P11
P02, P03, P05, P06, P10 to P12,
P20 to P22, P24 to P27, P30, P31, P40,
P75 to P77, P120 to P124, P137, P147,
P200 to P206, EXCLK, EXCLKS,
RESET
VIL2
P03, P10, P11
Caution The maximum value of VIH of pins P02, P10 to P12 is VDD, even in the N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 67 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V)
Items
Symbol
Output voltage,
VOH1
high
Conditions
MIN.
P02, P03, P05, P06, P10 to P12, P30,
4.0 V VDD 5.5 V,
P31, P40, P75 to P77, P120, P147,
IOH1 = 3.0 mA
P200 to P206
2.7 V VDD 5.5 V,
TYP.
MAX.
Unit
VDD 0.7
V
VDD 0.5
V
VDD 0.5
V
IOH1 = 1.0 mA
VOH2
P20 to P22, P24 to P27
2.7 V VDD 5.5 V,
IOH2 = 100 A
Output voltage,
VOL1
low
P02, P03, P05, P06, P10 to P12, P30,
4.0 V VDD 5.5 V,
P31, P40, P75 to P77, P120, P147,
IOL1 = 8.5 mA
P200 to P206
4.0 V VDD 5.5 V,
0.7
V
0.4
V
0.4
V
0.4
V
IOL1 = 4.0 mA
2.7 V VDD 5.5 V,
IOL1 = 1.5 mA
VOL2
P20 to P22, P24 to P27
2.7 V VDD 5.5 V,
IOL2 = 400 A
Caution P02, P10 to P12 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 68 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V)
Items
Symbol
Input leakage
ILIH1
Conditions
P02, P03, P05, P06, P10 to P12,
MIN.
TYP.
VI = VDD
MAX.
Unit
1
A
1
A
10
A
1
A
1
A
10
A
100
k
P20 to P22, P24 to P27, P30,
current, high
P31, P40, P75 to P77, P120,
P137, P147, P200 to P206,
RESET
ILIH2
P121 to P124
VI = VDD
In input port or
(X1, X2, XT1, XT2, EXCLK,
external clock
EXCLKS)
input
In resonator
connection
Input leakage
ILIL1
current, low
P02, P03, P05, P06, P10 to P12,
VI = VSS
P20 to P22, P24 to P27, P30,
P31, P40, P75 to P77, P120,
P137, P147, P200 to P206,
RESET
ILIL2
P121 to P124
VI = VSS
In input port or
(X1, X2, XT1, XT2, EXCLK,
external clock
EXCLKS)
input
In resonator
connection
On-chip pull-up
RU
P02, P03, P05, P06, P10 to P12,
VI = VSS, In input port
10
20
P30, P31, P40, P75 to P77, P120,
resistance
P147, P200 to P206
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 69 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
3.3.2 Supply current characteristics
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V) (1/2)
Parameter
Symbol
Supply
current
IDD1
Conditions
Operating
mode
Note 1
MIN.
HS (highspeed main)
modeNote 5
fIH = 16 MHzNote 3
HS (highspeed main)
modeNote 5
fMX = 20 MHzNote 2,
VDD = 5.0 V
fMX = 20 MHzNote 2,
VDD = 3.0 V
fMX = 10 MHzNote 2,
VDD = 5.0 V
fMX = 10 MHz
VDD = 3.0 V
Note 2
,
TYP.
MAX.
Unit
VDD = 5.0 V
2.9
4.8
mA
VDD = 3.0 V
2.9
4.8
mA
mA
Square wave input
3.2
5.6
Resonator connection
3.3
5.7
mA
Square wave input
3.2
5.6
mA
Resonator connection
3.3
5.7
mA
Square wave input
2.0
3.3
mA
Resonator connection
2.0
3.3
mA
Square wave input
2.0
3.3
mA
Resonator connection
2.0
3.3
mA
3.3
6.5
mA
3.3
6.5
mA
Square wave input
4.2
6.0
A
Resonator connection
4.4
6.2
A
Note 3
HS (highspeed main)
modeNote 5
fIH = 4 MHz
VDD = 5.0 V
fPLL = 64 MHz, fCLK = 16 MHz VDD = 3.0 V
Subsystem
clock
operation
fSUB = 32.768 kHzNote 4
TA = 40C
Note 4
fSUB = 32.768 kHz
TA = +25C
fSUB = 32.768 kHzNote 4
TA = +50C
fSUB = 32.768 kHzNote 4
TA = +70C
Square wave input
4.2
6.0
A
Resonator connection
4.4
6.2
A
Square wave input
4.3
7.2
A
Resonator connection
4.5
7.4
A
Square wave input
4.4
8.1
A
Resonator connection
4.6
8.3
A
fSUB = 32.768 kHzNote 4
TA = +85C
Square wave input
5.2
11.4
A
Resonator connection
5.4
11.6
A
Note 4
fSUB = 32.768 kHz
TA = +105C
Square wave input
6.9
20.8
A
Resonator connection
7.1
21.0
A
fSUB = 32.768 kHzNote 4
TA = +125C
Square wave input
11.1
51.2
A
Resonator connection
11.3
51.4
A
(Notes and Remarks are listed on the next page.)
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 70 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin
is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current.
However, not including the current flowing into the A/D converter, comparator, programmable gain
amplifier, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during
data flash rewrite.
2. When high-speed on-chip oscillator and subsystem clock are stopped.
3. When high-speed system clock and subsystem clock are stopped.
4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1
(Ultra-low power consumption oscillation). However, not including the current flowing into the RTC, 12bit interval timer, and watchdog timer.
5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 20 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 71 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V) (2/2)
Parameter
Symbol
Supply
Note 2
DD2
I
current
Conditions
HALT
HS (high-
mode
speed main)
Note 1
fIH = 16 MHz
MIN.
Note 4
modeNote 7
Unit
VDD = 5.0 V
0.50
2.0
mA
VDD = 3.0 V
0.50
2.0
mA
fMX = 20 MHzNote 3,
Square wave input
0.40
2.2
mA
speed main)
VDD = 5.0 V
Resonator connection
0.50
2.3
mA
Square wave input
0.40
2.2
mA
fMX = 20 MHz
Note 3
,
VDD = 3.0 V
Resonator connection
0.50
2.3
mA
fMX = 10 MHzNote 3,
Square wave input
0.24
1.22
mA
VDD = 5.0 V
Resonator connection
0.30
1.28
mA
Square wave input
0.24
1.22
mA
Resonator connection
0.30
1.28
mA
fMX = 10 MHz
Note 3
,
VDD = 3.0 V
HS (high-
fIH = 4 MHz
VDD = 5.0 V
0.95
3.7
mA
speed main)
fPLL = 64 MHz, fCLK = 16 MHz
VDD = 3.0 V
0.95
3.7
mA
fSUB = 32.768 kHzNote 5
TA = 40C
Square wave input
0.28
0.70
A
Resonator connection
0.47
0.89
A
fSUB = 32.768 kHzNote 5
TA = +25C
Square wave input
0.33
0.70
A
Resonator connection
0.52
0.89
A
fSUB = 32.768 kHzNote 5
TA = +50C
Square wave input
0.41
1.90
A
Resonator connection
0.60
2.09
A
Note 5
Square wave input
0.54
2.80
A
Resonator connection
0.73
2.99
A
Square wave input
1.27
6.10
A
Resonator connection
1.46
6.29
A
Square wave input
3.04
15.5
A
Resonator connection
3.23
15.7
A
Square wave input
7.20
45.2
A
Resonator connection
7.53
45.5
A
Note 4
modeNote 7
Subsystem
clock
operation
fSUB = 32.768 kHz
TA = +70C
Note 5
fSUB = 32.768 kHz
TA = +85C
Note 5
fSUB = 32.768 kHz
TA = +105C
fSUB = 32.768 kHzNote 5
TA = +125C
I
MAX.
HS (highmodeNote 7
Note 6
DD3
TYP.
STOP
TA = 40C
0.18
0.50
A
mode
TA = +25C
0.23
0.50
A
TA = +50C
0.27
1.70
A
TA = +70C
0.44
2.60
A
TA = +85C
1.17
5.90
A
TA = +105C
2.94
15.3
A
TA = +125C
7.14
45.1
A
Note 8
(Notes and Remarks are listed on the next page.)
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 72 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS.
The values below the MAX. column include the peripheral operation current.
However, not including the current flowing into the A/D converter, comparator, programmable gain
amplifier, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data
flash rewrite.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator and subsystem clock are stopped.
4. When high-speed system clock and subsystem clock are stopped.
5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and
setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included.
However, not including the current flowing into the 12-bit interval timer and watchdog timer.
6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer.
7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 20 MHz
8. Regarding the value for current operate the subsystem clock in STOP mode, refer to that in HALT mode.
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA =
25C
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 73 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Low-speed on-
Symbol
I
Conditions
MIN.
Note 1
FIL
TYP.
MAX.
Unit
0.20
A
0.02
A
0.02
A
0.22
A
chip oscillator
operating current
RTC operating
IRTC
current
Notes 1, 2, 3
12-bit interval timer
IIT
operating current
Notes 1, 2, 4
Watchdog timer
IWDT
operating current
Notes 1, 2, 5
A/D converter
operating current
IADC
A/D converter
reference voltage
current
IADREFNote 1
75.0
A
Temperature
sensor operating
current
ITMPSNote 1
75.0
A
LVD operating
ILVDNotes 1, 7
0.08
A
IFSP Notes 1, 8
2.5
12.2
mA
AVREFP = VDD = 5.0 V
0.21
0.37
mA
AVREFP = VDD = 3.0 V
0.18
0.35
mA
AVREFP = VDD = 5.0 V
41.4
74
A
AVREFP = VDD = 3.0 V
37.2
71
A
When one internal reference voltage
AVREFP = VDD = 5.0 V
14.8
31
A
circuit is operating
AVREFP = VDD = 3.0 V
8.9
24
A
AVREFP = VDD = 5.0 V
3.2
6.1
A
AVREFP = VDD = 3.0 V
2.9
4.9
A
2.50
12.2
mA
Notes 1, 6
fIL = 15 kHz
When conversion at
maximum speed
Normal mode, AVREFP = VDD = 5.0 V
1.3
1.7
mA
current
Self-programming
operating current
Programmable
IPGANote 9
gain amplifier
operating current
Comparator
ICMPNote 10
IVREF
Programmable
When one comparator channel is
operating
operating current
IIREFNote 11
gain amplifier/
comparator
reference current
source
BGO operating
IBGONote 12
current
SNOOZE
ISNOZNote 1
operating current
A/D converter
The mode is performedNote 13
0.50
1.10
mA
operation
The A/D conversion operations are performed,
1.20
2.17
mA
0.70
1.27
mA
Normal mode, AVREFP = VDD = 5.0 V
CSI/UART operation
(Notes and Remarks are listed on the next page.)
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3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
Notes 1. Current flowing to the VDD.
2. When the high-speed on-chip oscillator and high-speed system clock are stopped.
3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed onchip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the
values of either IDD1 or IDD2, and IRTC, when the real-time clock is operating in operating mode or in HALT
mode. When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock
operation includes the operational current of the real-time clock.
4. Current flowing only to the 12-bit interval timer (excluding the operating current of the XT1 oscillator and
fIL operating current). The current of the RL78 microcontrollers is the sum of the values of either IDD1 or
IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT mode. When the lowspeed on-chip oscillator is selected, IFIL should be added.
5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip
oscillator). The supply current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3, and IWDT,
when the watchdog timer is operating.
6. Current flowing only to the A/D converter. The supply current value of the RL78 microcontrollers is the
sum of IDD1 or IDD2 and IADC, when the A/D converter is operating in operating mode or in HALT mode.
7. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1,
IDD2 or IDD3 and ILVD when the LVD circuit is in operation.
8. Current flowing during self-programming operation.
9. Current flowing only to the programmable gain amplifier.
The supply current value of the RL78
microcontrollers is the sum of IDD1, IDD2 or IDD3, and IPGA, when the programmable gain amplifier is
operating in operating mode or in HALT mode.
10. Current flowing only to the comparator. The supply current value of the RL78 microcontrollers is the sum
of IDD1, IDD2 or IDD3, and ICMP, when the comparator is operating.
11. This is the current required to flow to VDD pin of the current circuit that is used as the programmable gain
amplifier and the comparator.
12. Current flowing only during data flash rewrite.
13. See 21.3.3 SNOOZE mode in the RL78/I1A User's Manual for shift time to the SNOOZE mode.
Remarks 1. fIL:
Low-speed on-chip oscillator clock frequency
2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
3. fCLK: CPU/peripheral hardware clock frequency
4. Temperature condition of the TYP. value is TA = 25C
5. Example of calculating current value when using programmable gain amplifier and comparator.
Examples 1) TYP. operating current value when three comparator channels, one internal reference
voltage generator, and PGA are operating (when AVREFP = VDD = 5.0 V)
ICMP × 3 + IVREF + IPGA + IIREF
= 41.4 [A] × 3 + 14.8 [A] × 1 + 210 [A] + 3.2 [A]
= 352.2 [ A]
Examples 2) TYP. operating current value when using two comparator channels, without using
internal reference voltage generator (when AVREFP = VDD = 5.0 V)
ICMP × 2 + IIREF
= 41.4 [A] × 2 + 3.2 [A]
= 86.0 [A]
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3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
3.4 AC Characteristics
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V)
Items
Instruction cycle (minimum
instruction execution time)
Symbol
TCY
Conditions
MIN.
Main system HS (high-speed main) mode
clock (fMAIN)
operation
Subsystem clock (fSUB) operation
In the self
HS (high-speed
programming main) mode
mode
TA = 40 to +105C
TYP.
0.05
MAX.
Unit
1
s
31.3
s
0.05
1
s
28.5
30.5
External system clock frequency
fEX
1.0
20.0
MHz
fEXS
32
35
kHz
External system clock input highlevel width, low-level width
tEXH, tEXL
24
ns
13.7
s
TI03, TI05, TI06, TI07 input highlevel width, low-level width
tTIH,
tTIL
2/fMCK+10
ns
TO03, TO05, TO06, TKBO00,
TKBO01, TKBO10, TKBO11,
TKBO20, TKBO21, TKCO00 to
TKCO05 output frequency (When
duty = 50%)
fTO
Interrupt input high-level width,
low-level width
tINTH,
tINTL
RESET low-level width
tRSL
tEXHS, tEXLS
HS (high-speed main) 4.0 V VDD 5.5 V
mode
2.7 V VDD < 4.0 V
INTP0, INTP3, INTP4, 2.7 V VDD 5.5 V
INTP9 to INTP11,
INTP20 to INTP23
5
MHz
4
MHz
1
s
10
s
Remark fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKS0n bit of timer mode register 0n (TMR0n). n: Channel number (n = 0
to 7))
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3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
Minimum Instruction Execution Time during Main System Clock Operation
TCY vs VDD (HS (high-speed main) mode)
10
1.0
Cycle time TCY [µs]
When the high-speed on-chip
oscillator clock is selected
During self programming
When high-speed system clock
is selected
0.1
0.05
0.01
0
1.0
2.0
3.0
2.7
4.0
5.0
5.5
6.0
Supply voltage VDD [V]
AC Timing Test Points
VIH/VOH
VIL/VOL
VIH/VOH
Test points
VIL/VOL
External System Clock Timing
1/fEX/
1/fEXS
tEXL/
tEXLS
tEXH/
tEXHS
EXCLK/EXCLKS
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RL78/I1A
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
TI/TO Timing
tTIH
tTIL
TI03, TI05, TI06, TI07
1/fTO
TO03, TO05, TO06, TKBO00, TKBO01, TKBO10,
TKBO11, TKBO20, TKBO21, TKCO00 to TKCO05
Interrupt Request Input Timing
tINTL
tINTH
INTP0, INTP3, INTP4, INTP9 to INTP11,
INTP20 to INTP23
RESET Input Timing
tRSL
RESET
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3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
3.5 Peripheral Functions Characteristics
AC Timing Test Points
VIH/VOH
VIH/VOH
Test points
VIL/VOL
VIL/VOL
3.5.1 Serial array unit 0, 4 (UART0, UART1, CSI00, DALI/UART4)
(1) During communication at same potential (UART mode)
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Unit
Mode
MIN.
Transfer rateNote 1
Theoretical value of the maximum
MAX.
fMCK/6
bps
3.3
Mbps
transfer rate
fMCK = fCLKNote 2
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
2. The operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode:
20 MHz (2.7 V VDD 5.5 V)
UART mode connection diagram (during communication at same potential)
Rx
TxDq
User's device
RL78 microcontroller
Tx
RxDq
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Caution
Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
2.
q: UART number (q = 0, 1), g: PIM and POM number (g = 0, 1)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03))
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3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Unit
Mode
MIN.
SCKp cycle time
tKCY1
SCKp high-/low-level width
Note 1
SIp setup time (to SCKp)
Note 2
SIp hold time (from SCKp)
Delay time from SCKp to
tKCY1 4/fCLK
MAX.
4.0 V VDD 5.5 V
250
ns
2.7 V VDD 5.5 V
500
ns
tKH1,
4.0 V VDD 5.5 V
tKCY1/2 20
ns
tKL1
2.7 V VDD 5.5 V
tKCY1/2 40
ns
tSIK1
4.0 V VDD 5.5 V
80
ns
2.7 V VDD 5.5 V
80
ns
40
ns
tKSI1
tKSO1
Note 4
C = 30 pF
80
ns
SOp outputNote 3
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM number (g = 1)
2.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
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3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Unit
Mode
MIN.
SCKp cycle timeNote 5
SCKp high-/low-level width
tKCY2
MAX.
4.0 V VDD 5.5 V
fMCK 20 MHz
6/fMCK
ns
2.7 V VDD 5.5 V
16 MHz < fMCK
8/fMCK
ns
fMCK 16 MHz
6/fMCK
ns
tKCY2/2
ns
tKH2,
tKL2
SIp setup time
(to SCKp)Note 1
tSIK2
1/fMCK+40
ns
SIp hold time
(from SCKp)Note 2
tKSI2
1/fMCK+60
ns
Delay time from SCKp to SOp
tKSO2
C = 30 pFNote 4
2/fMCK+80
ns
outputNote 3
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SOp output lines.
5. Transfer rate in the SNOOZE mode: MAX. 1 Mbps
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the
SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks
1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM number (g = 1)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
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3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
CSI mode connection diagram (during communication at same potential)
SCK
SCKp
RL78
microcontroller
SIp
SO
SOp
SI
User's device
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1, 2
tKL1, 2
tKH1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
Output data
SOp
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1, 2
tKH1, 2
tKL1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Remarks 1.
2.
Output data
p: CSI number (p = 00)
m: Unit number, n: Channel number (mn = 00)
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3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
(4) Communication at different potential (2.5 V, 3 V) (UART mode) (1/2)
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
Unit
main) Mode
MIN.
Transfer rate
Reception
4.0 V VDD 5.5 V,
MAX.
bps
fMCK/6
2.7 V Vb 4.0 V
Note 1
Theoretical value of the maximum
3.3
Mbps
fMCK/6
bps
transfer rate
fMCK = fCLKNote 2
2.7 V VDD < 4.0 V,
2.3 V Vb 2.7 V
Note 1
Theoretical value of the maximum
3.3
Mbps
transfer rate
fMCK = fCLKNote 2
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
2. The operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode:
Caution
20 MHz (2.7 V VDD 5.5 V)
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode
for the TxDq pin by using port input mode register g (PIMg) and port output mode register g
(POMg).
Remarks 1.
Vb[V]: Communication line voltage
2.
q: UART number (q = 0, 1), g: PIM and POM number (g = 0, 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03)
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3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
(4) Communication at different potential (2.5 V, 3 V) (UART mode) (2/2)
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
Unit
main) Mode
MIN.
Transfer rate
Transmission
4.0 V VDD 5.5 V,
2.7 V Vb 4.0 V
Note 1
Notes 1.
bps
2.8Note 2 Mbps
Theoretical value of the maximum transfer rate
Cb = 50 pF, Rb = 1.4 k, Vb = 2.7 V
2.7 V VDD < 4.0 V,
2.3 V Vb 2.7 V
MAX.
Note 3
Theoretical value of the maximum transfer rate
Cb = 50 pF, Rb = 2.7 k, Vb = 2.3 V
1.2
Note 4
bps
Mbps
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V VDD 5.5 V and 2.7 V Vb 4.0 V
1
Maximum transfer rate =
{Cb × Rb × ln (1
Baud rate error (theoretical value) =
2.2
Vb )} × 3
[bps]
2.2
1
{Cb × Rb × ln (1 Vb )}
Transfer rate 2
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2.
This value as an example is calculated when the conditions described in the “Conditions” column are
3.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
met. See Note 1 above to calculate the maximum transfer rate under conditions of the customer.
maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V VDD < 4.0 V and 2.3 V Vb 2.7 V
1
Maximum transfer rate =
{Cb × Rb × ln (1
Baud rate error (theoretical value) =
2.0
Vb )} × 3
[bps]
2.0
1
{Cb × Rb × ln (1 Vb )}
Transfer rate 2
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
4.
This value as an example is calculated when the conditions described in the “Conditions” column are
met. See Note 3 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode
for the TxDq pin by using port input mode register g (PIMg) and port output mode register g
(POMg).
Remarks 1.
Rb[]: Communication line (TxDq) pull-up resistance,
Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
2.
q: UART number (q = 0, 1), g: PIM and POM number (g = 0, 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03))
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3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
UART mode connection diagram (during communication at different potential)
Vb
Rb
TxDq
Rx
User's device
RL78 microcontroller
RxDq
Tx
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode
for the TxDq pin by using port input mode register g (PIMg) and port output mode register g
(POMg).
Remarks 1.
2.
Rb[]: Communication line (TxDq) pull-up resistance, Vb[V]: Communication line voltage
q: UART number (q = 0, 1), g: PIM and POM number (g = 0, 1)
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3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
(5) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output)
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Unit
Mode
MIN.
SCKp cycle time
tKCY1
tKCY1 4/fCLK
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
MAX.
600
ns
1000
ns
tKCY1/2 80
ns
tKCY1/2 170
ns
tKCY1/2 28
ns
tKCY1/2 40
ns
160
ns
250
ns
40
ns
40
ns
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
SCKp high-level width
tKH1
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
SCKp low-level width
tKL1
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
SIp setup time
(to SCKp)Note 1
tSIK1
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
SIp hold time
(from SCKp)Note 1
tKSI1
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
Delay time from SCKp to
tKSO1
SOp outputNote 1
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
160
ns
250
ns
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
SIp setup time
(to SCKp)Note 2
tSIK1
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
80
ns
80
ns
40
ns
40
ns
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
SIp hold time
(from SCKp)Note 2
tKSI1
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
Delay time from SCKp to
SOp outputNote 2
tKSO1
4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V,
80
ns
80
ns
Cb = 30 pF, Rb = 1.4 k
2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
(Caution and Remarks are listed on the next page.)
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Page 86 of 105
RL78/I1A
Caution
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode
for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode
register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
CSI mode connection diagram (during communication at different potential)
Vb
Rb
Vb
Rb
SCKp
RL78
microcontroller
SCK
SIp
SO
SOp
SI
User's device
Remarks 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM number (g = 1)
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Page 87 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
Output data
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
Output data
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for
the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode
register g (POMg).
Remark
p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g
= 1)
R01DS0171EJ0320 Rev.3.20
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Page 88 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
(6) DALI/UART4 mode
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
Transfer rate
Maximum transfer rate theoretical value
Unit
MAX.
fMCK/12
bps
1.6
Mbps
fCLK = 20 MHz, fMCK = fCLK
Remark
fMCK: Operation clock frequency of DALI/UART.
(Operation clock to be set by the serial clock select register 4 (SPS4).)
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Page 89 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
3.5.2 Serial interface IICA
(1) I2C standard mode
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Unit
Mode
Standard mode: fCLK 1 MHz
MIN.
MAX.
0
100
SCLA0 clock frequency
fSCL
Setup time of restart condition
tSU:STA
4.7
s
tHD:STA
4.0
s
Hold time when SCLA0 = “L”
tLOW
4.7
s
Hold time when SCLA0 = “H”
tHIGH
4.0
s
Data setup time (reception)
tSU:DAT
250
Data hold time (transmission)Note 2
tHD:DAT
0
Setup time of stop condition
tSU:STO
4.0
s
Bus-free time
tBUF
4.7
s
Hold time
Note 1
Notes 1.
2.
kHz
ns
3.45
s
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line
pull-up resistor) at that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 k
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Page 90 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
(2) I2C fast mode
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Unit
Mode
fast mode: fCLK 3.5 MHz
MIN.
MAX.
0
400
SCLA0 clock frequency
fSCL
Setup time of restart condition
tSU:STA
0.6
s
tHD:STA
0.6
s
Hold time when SCLA0 = “L”
tLOW
1.3
s
Hold time when SCLA0 = “H”
tHIGH
0.6
s
tSU:DAT
100
ns
tHD:DAT
0
Setup time of stop condition
tSU:STO
0.6
s
Bus-free time
tBUF
1.3
s
Hold time
Note 1
Data setup time (reception)
Data hold time (transmission)
Notes 1.
2.
Note 2
kHz
0.9
s
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line
pull-up resistor) at that time in each mode are as follows.
Cb = 320 pF, Rb = 1.1 k
fast mode:
IICA serial transfer timing
tLOW
SCLA0
tHD:DAT
tHD:STA
tHIGH
tSU:STA
tHD:STA
tSU:STO
tSU:DAT
SDAA0
tLOW
Stop
condition
Start
condition
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Sep 29, 2017
Restart
condition
Stop
condition
Page 91 of 105
RL78/I1A
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
3.6 Analog Characteristics
3.6.1 A/D converter characteristics
Classification of A/D converter characteristics
Reference Voltage
Reference voltage (+) =
AVREFP
Reference voltage () =
Input channel
AVREFM
Reference voltage (+) = VDD
Reference voltage () = VSS
ANI0 to ANI2, ANI4 to ANI7
See 3.6.1 (1).
See 3.6.1 (3).
ANI16 to ANI19
See 3.6.1 (2).
Internal reference voltage
See 3.6.1 (1).
Reference voltage (+) = VBGR
Reference voltage () =
AVREFM
See 3.6.1 (4).
Temperature sensor output
voltage
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Page 92 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
(1) When reference voltage
(+)
= AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage
()
=
AVREFM/ANI1 (ADREFM = 1), target ANI pin: ANI2, ANI4 to ANI7, internal reference voltage, and
temperature sensor output voltage
(TA = 40 to +125C, 2.7 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference
voltage () = AVREFM = 0 V)
Parameter
Resolution
Symbol
Conditions
RES
Overall error
Note 1
Conversion time
MIN.
TYP.
8
AINL
10-bit resolution
AVREFP = VDDNote 3
tCONV
10-bit resolution
Target pin: ANI2, ANI4 to
ANI7
1.2
MAX.
Unit
10
bit
3.5
LSB
3.6 V VDD 5.5 V
2.125
39
s
2.7 V VDD 5.5 V
3.4
39
s
2.375
39
s
3.8
39
s
10-bit resolution
3.6 V VDD 5.5 V
Target pin: Internal reference 2.7 V VDD 5.5 V
voltage, and temperature
sensor output voltage
(HS (high-speed main)
mode)
Zero-scale errorNotes 1, 2
EZS
10-bit resolution
AVREFP = VDDNote 3
0.25
%FSR
Full-scale errorNotes 1, 2
EFS
10-bit resolution
AVREFP = VDDNote 3
0.25
%FSR
Integral linearity errorNote 1
ILE
10-bit resolution
AVREFP = VDDNote 3
2.5
LSB
Differential linearity error
DLE
10-bit resolution
AVREFP = VDDNote 3
1.5
LSB
AVREFP
V
Note 1
Analog input voltage
VAIN
ANI2, ANI4 to ANI7
0
Internal reference voltage
(HS (high-speed main) mode)
Temperature sensor output voltage
(HS (high-speed main) mode)
VBGR
Note 4
VTMPS25Note 4
V
V
Notes 1. Excludes quantization error (1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add 1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add 0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/Differential linearity error: Add 0.5 LSB to the MAX. value when AVREFP = VDD.
4. See 3.6.2 Temperature sensor/internal reference voltage characteristics.
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3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
(2) When reference voltage
(+)
= AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage
()
=
AVREFM/ANI1 (ADREFM = 1), target pin: ANI16 to ANI19
(TA = 40 to +125C, 2.7 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference
voltage () = AVREFM = 0 V)
Parameter
Resolution
Symbol
Conditions
RES
Overall error
Note 1
AINL
MIN.
TYP.
8
1.2
10-bit resolution
MAX.
Unit
10
bit
5.0
LSB
AVREFP = VDDNote 3
Conversion time
tCONV
10-bit resolution
3.6 V VDD 5.5 V
2.125
39
s
Target ANI pin : ANI16 to
2.7 V VDD < 5.5 V
3.4
39
s
0.35
%FSR
0.35
%FSR
3.5
LSB
2.0
LSB
AVREFP
V
ANI19
Zero-scale errorNotes 1, 2
EZS
10-bit resolution
AVREFP = VDDNote 3
Full-scale errorNotes 1, 2
EFS
10-bit resolution
AVREFP = VDD
Integral linearity errorNote 1
ILE
Note 3
10-bit resolution
AVREFP = VDDNote 3
Differential linearity errorNote 1
DLE
10-bit resolution
AVREFP = VDDNote 3
Analog input voltage
VAIN
ANI16 to ANI19
0
and VDD
Notes 1. Excludes quantization error (1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add 4.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add 0.2%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/Differential linearity error: Add 2.0 LSB to the MAX. value when AVREFP = VDD.
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 94 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
(3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage () = VSS (ADREFM = 0),
target pin: ANI0 to ANI2, ANI4 to ANI7, ANI16 to ANI19, internal reference voltage, and temperature
sensor output voltage
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage () = VSS)
Parameter
Resolution
Overall error
Symbol
Conditions
RES
Note 1
MIN.
TYP.
8
Unit
10
bit
7.0
LSB
AINL
10-bit resolution
tCONV
10-bit resolution
3.6 V VDD 5.5 V
2.125
39
s
Target pin: ANI0 to ANI2,
2.7 V VDD 5.5 V
3.4
39
s
10-bit resolution
3.6 V VDD 5.5 V
2.375
39
s
Target pin: Internal
2.7 V VDD 5.5 V
3.8
39
s
EZS
10-bit resolution
0.60
%FSR
Full-scale errorNotes 1, 2
EFS
10-bit resolution
0.60
%FSR
Integral linearity errorNote 1
ILE
10-bit resolution
4.0
LSB
Differential linearity error
DLE
10-bit resolution
2.0
LSB
VAIN
ANI0 to ANI2, ANI4 to ANI7
0
VDD
V
ANI16 to ANI19
0
VDD
V
Conversion time
ANI4 to ANI7, ANI16 to
1.2
MAX.
ANI19
Conversion time
tCONV
reference voltage, and
temperature sensor output
voltage (HS (high-speed
main) mode)
Zero-scale error
Notes 1, 2
Note 1
Analog input voltage
Internal reference voltage
VBGR
Note 3
V
(HS (high-speed main) mode)
Temperature sensor output voltage
VTMPS25 Note 3
V
(HS (high-speed main) mode)
Notes 1. Excludes quantization error (1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. See 3.6.2 Temperature sensor/internal reference voltage characteristics.
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Page 95 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
(4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage
()
= AVREFM/ANI1 (ADREFM = 1), target pin: ANI0, ANI2, ANI4 to ANI7, ANI16 to ANI19
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VBGRNote 3, Reference voltage () =
AVREFM Note 4 = 0 V, HS (high-speed main) mode)
Parameter
Resolution
Symbol
Conditions
MIN.
RES
Conversion time
tCONV
TYP.
MAX.
8
8-bit resolution
Unit
bit
17
39
s
%FSR
EZS
8-bit resolution
0.60
Integral linearity errorNote 1
ILE
8-bit resolution
2.0
LSB
Differential linearity errorNote 1
DLE
8-bit resolution
1.0
LSB
Zero-scale error
Notes 1, 2
Analog input voltage
VAIN
0
VBGR
Note 3
V
Notes 1. Excludes quantization error (1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. See 3.6.2 Temperature sensor/internal reference voltage characteristics.
4. When reference voltage () = VSS, the MAX. values are as follows.
Zero-scale error: Add 0.35%FSR to the MAX. value when reference voltage () = AVREFM.
Integral linearity error: Add 0.5 LSB to the MAX. value when reference voltage () = AVREFM.
Differential linearity error: Add 0.2 LSB to the MAX. value when reference voltage () = AVREFM.
3.6.2 Temperature sensor/internal reference voltage characteristics
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V, HS (high-speed main) mode)
Parameter
Symbol
Conditions
Temperature sensor output voltage
VTMPS25
Setting ADS register = 80H, TA = +25C
Internal reference voltage
VBGR
Setting ADS register = 81H
Temperature coefficient
FVTMPS
MIN.
TYP.
MAX.
1.05
1.38
1.45
3.6
Temperature sensor that depends on the
Unit
V
1.5
V
mV/C
temperature
Operation stabilization wait time
R01DS0171EJ0320 Rev.3.20
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tAMP
5
s
Page 96 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
3.6.3 Programmable gain amplifier
(TA = 40 to +125C, 2.7 V AVREFP = VDD 5.5 V, VSS = AVREFM = 0 V)
Parameter
Symbol
Input offset voltage
VIOPGA
Input voltage range
VIPGA
Gain errorNote 1
Conditions
MIN.
TYP.
MAX.
Unit
5
10
mV
0.9VDD/
gain
V
4, 8 times
1
%
16 times
1.5
%
0
2
32 times
Slew rateNote 1
SRRPGA
SRFPGA
Rising
edge
Falling
edge
4, 8 times
16, 32 times
1.4
V/s
2.7 V VDD < 4.0 V
4, 8 times
1.8
V/s
16, 32 times
0.5
V/s
4, 8 times
3.2
V/s
16, 32 times
1.4
V/s
4, 8 times
1.2
V/s
16, 32 times
4.0 V VDD 5.5 V
2.7 V VDD < 4.0 V
Operation stabilization wait timeNote 2
tPGA
%
V/s
4.0 V VDD 5.5 V
4
0.5
V/s
4, 8 times
5
s
16, 32 times
10
s
Notes 1. When VIPGA = 0.1VDD/gain to 0.9VDD/gain.
2. Time required until a state is entered where the DC and AC specifications of the PGA are satisfied after
the PGA operation has been enabled (PGAEN = 1).
Remark These characteristics apply when AVREFM is selected as GND of the PGA by using the CVRVS1 bit.
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 97 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
3.6.4 Comparator
(TA = 40 to +125C, 2.7 V AVREFP = VDD 5.5 V, VSS = AVREFM = 0 V)
Parameter
Symbol
Input offset voltage
VIOCMP
Input voltage range
VICMP
Conditions
MIN.
CMP0P to CMP5P
CMPCOM
VIREF
Internal reference voltage deviation
TYP.
MAX.
Unit
5
40
mV
0
VDD
V
0.045
0.9VDD
V
2
LSB
1
LSB
150
ns
CmRVM register values: 7FH to 80H
(m = 0 to 2)
Other than above
Response time
tCR, tCF
Input amplitude = 100 mV
Operation stabilization wait timeNote 1
tCMP
3.3 V VDD 5.5 V
1
s
2.7 V VDD < 3.3 V
3
s
10
s
Reference voltage stabilization wait
tVR
CVRE: 0 to 1
70
Note 2
time
Notes 1. Time required until a state is entered where the DC and AC specifications of the comparator are
satisfied after the operation of the comparator has been enabled (CMPnEN bit = 1: n = 0 to 5)
2. Enable comparator output (CnOE bit = 1; n = 0 to 5) after enabling operation of the internal reference
voltage generator (by setting the CVREm bit to 1; m = 0 to 2) and waiting for the operation stabilization
time to elapse.
Remark These characteristics apply when AVREFP is selected as the power supply source of the internal reference
voltage by using the CVRVS0 bit, and when AVREFM is selected as GND of the internal reference voltage
by using the CVRVS1 bit.
Output voltage VO
tCR
tCF
+100 mV
Input voltage VIN
Comparator
ref. voltage
-100 mV
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 98 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
3.6.5 POR circuit characteristics
(TA = 40 to +125C, VSS = 0 V)
Parameter
Detection voltage
Minimum pulse width
Note
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VPOR
Power supply rise time
1.45
1.51
1.62
V
VPDR
Power supply fall time
1.44
1.50
1.61
V
TPW
s
300
Note Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time
required for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode
is entered or the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the
clock operation status control register (CSC).
TPW
Supply voltage (VDD)
VPOR
VPDR or 0.7 V
3.6.6 LVD circuit characteristics
LVD Detection Voltage of Reset Mode and Interrupt Mode
(TA = 40 to +125C, VPDR VDD 5.5 V, VSS = 0 V)
Parameter
Detection
Supply voltage level
Symbol
VLVD0
voltage
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
Minimum pulse width
Detection delay time
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
tLW
Conditions
MIN.
TYP.
MAX.
Unit
Power supply rise time
3.97
4.06
4.25
V
Power supply fall time
3.89
3.98
4.15
V
Power supply rise time
3.67
3.75
3.93
V
Power supply fall time
3.59
3.67
3.83
V
Power supply rise time
3.06
3.13
3.28
V
Power supply fall time
2.99
3.06
3.20
V
Power supply rise time
2.95
3.02
3.17
V
Power supply fall time
2.89
2.96
3.09
V
Power supply rise time
2.85
2.92
3.07
V
Power supply fall time
2.79
2.86
2.99
V
Power supply rise time
2.75
2.81
2.95
V
Power supply fall time
2.70
2.75
2.88
V
s
300
300
s
Page 99 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
LVD Detection Voltage of Interrupt & Reset Mode
(TA = 40 to +125C, VPDR VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Interrupt and reset
VLVD0
mode
VLVD1
Conditions
MIN.
TYP.
MAX.
Unit
2.70
2.75
2.88
V
Rising release reset voltage
2.85
2.92
3.07
V
Falling interrupt voltage
2.79
2.86
2.99
V
Rising release reset voltage
2.95
3.02
3.17
V
VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage: 2.7 V
LVIS1, LVIS0 = 1, 0
VLVD2
LVIS1, LVIS0 = 0, 1
VLVD3
LVIS1, LVIS0 = 0, 0
Falling interrupt voltage
2.89
2.96
3.09
V
Rising release reset voltage
3.97
4.06
4.25
V
Falling interrupt voltage
3.89
3.98
4.15
V
MIN.
TYP.
MAX.
Unit
54
V/ms
3.6.7 Supply voltage rise inclination characteristics
(TA = 40 to +125C, VSS = 0 V)
Parameter
Supply voltage rise
Symbol
Conditions
SVDD
Caution Keep the internal reset status by using the LVD circuit or an external reset signal until VDD rises to
within the operating voltage range shown in 33.4 AC Characteristics.
3.7 RAM Data Retention Characteristics
(TA = 40 to +125C, VSS = 0 V)
Parameter
Data retention supply voltageNote 2
Symbol
Conditions
MIN.
1.47Note 1
VDDDR
TYP.
MAX.
Unit
5.5
V
Note The value depends on the POR detection voltage. When the voltage drops, the RAM data is retained before
a POR reset is effected, but RAM data is not retained when a POR reset is effected.
Caution When CPU is operated at the voltage of out of the operation voltage range, RAM data is not
retained. Therefore, set STOP mode before the supplied voltage is below the operation voltage
range.
STOP mode
Operation mode
RAM Data retention
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
R01DS0171EJ0320 Rev.3.20
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Page 100 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
3.8 Flash Memory Programming Characteristics
(TA = 40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
CPU/peripheral hardware clock
Symbol
Conditions
MIN.
fCLK
2.7 V VDD 5.5 V
Cerwr
Retained for 20 years, TA = 85CNote 3, 4
TYP.
MAX.
Unit
32
MHz
1
frequency
Number of code flash
rewrites
Retained for 1 year, TA = 25CNote 3, 4
Number of data flash
rewrites
1,000
Times
Notes 1, 2, 3
Notes 1, 2, 3
1,000,000
Note 3, 4
Retained for 5 years, TA = 85C
100,000
Note 3, 4
Retained for 20 years, TA = 85C
10,000
Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite
after the rewrite.
2. When using flash memory programmer and Renesas Electronics self programming library
3. These are the characteristics of the flash memory and the results obtained from reliability testing by
Renesas Electronics Corporation.
4. These are the average temperature of during the retainment.
3.9 Dedicated Flash Memory Programmer Communication (UART)
(TA = 40 to +105C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Transfer rate
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Symbol
Conditions
During serial programming
MIN.
115.2 k
TYP.
MAX.
Unit
1M
bps
Page 101 of 105
3. ELECTRICAL SPECIFICATIONS (M: Industrial applications, TA = 40 to +125C)
RL78/I1A
3.10 Timing of Entry to Flash Memory Programming Modes
(TA = 40 to +125C, 2.7 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
How long from when an external
tSUINIT
reset ends until the initial
Conditions
MIN.
TYP.
POR and LVD reset must end before the
MAX.
Unit
100
ms
external reset ends.
communication settings are
specified
How long from when the TOOL0 pin tSU
is placed at the low level until an
POR and LVD reset must end before the
10
s
1
ms
external reset ends.
external reset ends
How long the TOOL0 pin must be
kept at the low level after a reset
tHD
POR and LVD reset must end before the
external reset ends.
ends
(except soft processing time)
RESET
723 µs + tHD
processing
time
1-byte data for setting mode
TOOL0
tSU
tSUINIT
The low level is input to the TOOL0 pin.
The external reset ends (POR and LVD reset must end before the pin reset ends.).
The TOOL0 pin is set to the high level.
Complete the baud rate setting by UART reception.
Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within
100 ms from when the resets end.
tSU:
How long from when the TOOL0 pin is placed at the low level until an external reset ends
tHD:
How long to keep the TOOL0 pin at the low level from when the external and internal resets end
(except soft processing time)
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 102 of 105
RL78/I1A
4. PACKAGE DRAWINGS
4. PACKAGE DRAWINGS
4.1 20-pin Products
R5F1076CGSP#V0, R5F1076CGSP#X0, R5F1076CMSP#V0, R5F1076CMSP#X0
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LSSOP20-4.4x6.5-0.65
PLSP0020JB-A
P20MA-65-NAA-1
0.1
D
2
detail of lead end
11
20
E
1
c
10
1
L
3
bp
A
A2
A1
HE
e
y
(UNIT:mm)
ITEM
DIMENSIONS
D
E
6.50 0.10
4.40 0.10
NOTE
HE
6.40 0.20
1.Dimensions “
1” and “
A
1.45 MAX.
A1
0.10 0.10
2.Dimension “
” does not include tr
A2
1.15
2”
e
bp
c
L
y
0.65 0.12
0.22 0.10
0.05
0.15 0.05
0.02
0.50 0.20
0.10
0 to 10
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 103 of 105
RL78/I1A
4. PACKAGE DRAWINGS
4.2 30-pin Products
R5F107ACGSP#V0, R5F107AEGSP#V0, R5F107ACGSP#X0, R5F107AEGSP#X0, R5F107ACMSP#V0,
R5F107AEMSP#V0, R5F107ACMSP#X0, R5F107AEMSP#X0
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LSSOP30-0300-0.65
PLSP0030JB-B
S30MC-65-5A4-3
0.18
30
16
detail of lead end
F
G
T
P
1
L
15
U
E
A
H
I
J
S
C
D
N
M
S
B
M
K
ITEM
A
MILLIMETERS
9.85±0.15
B
0.45 MAX.
C
0.65 (T.P.)
NOTE
D
0.24 +0.08
−0.07
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
E
0.1±0.05
F
1.3±0.1
G
1.2
H
8.1±0.2
I
6.1±0.2
J
1.0±0.2
K
0.17±0.03
L
0.5
M
0.13
N
0.10
P
3° +5°
−3°
T
0.25
U
0.6±0.15
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 104 of 105
RL78/I1A
4. PACKAGE DRAWINGS
4.3 38-pin Products
R5F107DEGSP#V0, R5F107DEGSP#X0, R5F107DEMSP#V0, R5F107DEMSP#X0
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-SSOP38-0300-0.65
PRSP0038JA-A
P38MC-65-2A4-2
0.3
38
detail of lead end
V
20
T
I
P
W
U
V
19
1
L
W
A
F
H
G
J
S
C
E
D
N
S
B
M M
NOTE
Each lead centerline is located within 0.10 mm
of its true position (T.P.) at maximum material
condition.
K
(UNIT:mm)
ITEM
A
DIMENSIONS
B
12.30±0.10
0.30
C
0.65 (T.P.)
D
0.32 +0.08
−0.07
E
0.125±0.075
F
2.00 MAX.
G
1.70±0.10
H
8.10±0.20
I
6.10±0.10
J
1.00±0.20
K
0.17 +0.08
−0.07
L
0.50
M
0.10
N
0.10
P
3° +7°
−3°
T
0.25(T.P.)
U
0.60±0.15
V
0.25 MAX.
W
0.15 MAX.
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0171EJ0320 Rev.3.20
Sep 29, 2017
Page 105 of 105
Revision History
RL78/I1A Datasheet
Rev.
Date
Page
3.20
Sep 29, 2017
p.1
Description
Summary
Modification of description in 1.1 Features
p.59
Modification of figure in 2.10 Timing of Entry to Flash Memory Programming Modes
p.102
Modification of figure in 3.10 Timing of Entry to Flash Memory Programming Modes
p.103
Modification of figure in 4.1 20-pin Products
All trademarks and registered trademarks are the property of their respective owners.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United
States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
C-1
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a wrist
strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken
for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the device.
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by
you or third parties arising from the use of these circuits, software, or information.
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Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other disputes involving patents, copyrights, or other intellectual property rights of third parties, by or
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(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
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(Rev.3.0-1 November 2016)
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Refer to "http://www.renesas.com/" for the latest and detailed information.
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