Datasheet
R01DS0244EJ0230
Rev. 2.30
Jun 30, 2020
RL78/I1D
RENESAS MCU
True low-power platform (58.3 μA/MHz, and 0.64 μA for operation with only RTC2 and LVD) for the generalpurpose applications, with 1.6-V to 3.6-V operation, 8- to 32-Kbyte code flash memory, and 33 DMIPS at 24 MHz
1. OUTLINE
1.1
Features
Ultra-low power consumption technology
Data transfer controller (DTC)
•
•
•
•
• Transfer modes: Normal transfer mode, repeat transfer
mode, block transfer mode
• Activation sources: Activated by interrupt sources.
• Chain transfer function
VDD = 1.6 V to 3.6 V
HALT mode
STOP mode
SNOOZE mode
RL78 CPU core
Event link controller (ELC)
• CISC architecture with 3-stage pipeline
• Minimum instruction execution time: Can be changed
from high speed (0.04167 s: @ 24 MHz operation with
high-speed on-chip oscillator) to ultra-low speed (66.6
s: @ 15 kHz operation with low-speed on-chip
oscillator clock)
• Multiply/divide/multiply & accumulate instructions are
supported.
• Address space: 1 MB
• General-purpose registers: (8-bit register 8) 4 banks
• On-chip RAM: 0.7 to 3 KB
• Event signals of 20 types can be linked to the specified
peripheral function.
Code flash memory
• Code flash memory: 8 to 32 KB
• Block size: 1 KB
• Prohibition of block erase and rewriting (security
function)
• On-chip debug function
• Self-programming (with boot swap function/flash shield
window function)
Data flash memory
• Data flash memory: 2 KB
• Back ground operation (BGO): Instructions can be
executed from the program memory while rewriting the
data flash memory.
• Number of rewrites: 1,000,000 times (TYP.)
• Voltage of rewrites: VDD = 1.8 to 3.6 V
Serial interfaces
• CSI: 1 or 2 channels
• UART: 1 channel
• I2C/simplified I2C: 1 or 2 channels
Timers
•
•
•
•
16-bit timer: 4 channels
12-bit interval timer: 1 channel
8-bit interval timer: 4 channels
Real-time clock: 1 channel (calendar for 99 years, alarm
function, and clock correction function)
• Watchdog timer: 1 channel
A/D converter
• 8/12-bit resolution A/D converter (VDD = 1.6 to 3.6 V)
• Analog input: 6 to 17 channels
• Internal reference voltage (1.45 V) and temperature
sensor
Comparator
• 2 channels
• Operating modes: Comparator high-speed mode,
comparator low-speed mode, window mode
Operational amplifier
High-speed on-chip oscillator
• Select from 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4
MHz, 3 MHz, 2 MHz, and 1 MHz
• High accuracy: ±1.0% (VDD = 1.8 to 3.6 V, TA = -20 to
+85°C)
Middle-speed on-chip oscillator
• Selectable from 4 MHz, 2 MHz, and 1 MHz.
Operating ambient temperature
• TA = -40 to +105°C (G: Industrial applications)
• 4 channels
I/O ports
• I/O port: 14 to 42 (N-ch open drain I/O [withstand
voltage of 6 V]: 4, N-ch open drain I/O [VDD withstand
voltage]: 3 to 7)
• Can be set to N-ch open drain, TTL input buffer, and onchip pull-up resistor
• Different potential interface: Can connect to a 1.8/2.5 V
device
• On-chip key interrupt function
• On-chip clock output/buzzer output controller
Others
Power management and reset function
• On-chip power-on-reset (POR) circuit
• On-chip voltage detector (LVD) (Select interrupt and
reset from 12 levels)
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
• On-chip BCD (binary-coded decimal) correction circuit
• On-chip data operation circuit
Remark
The functions mounted depend on the
product. See 1.6 Outline of Functions.
Page 1 of 101
RL78/I1D
1. OUTLINE
ROM, RAM capacities
Flash
ROM
RL78/I1D
Data flash
RAM
20 pins
24 pins
30 pins
32 pins
48 pins
32 KB
2 KB
3 KB Note
—
—
R5F117AC
R5F117BC
R5F117GC
16 KB
2 KB
2 KB
R5F1176A
R5F1177A
R5F117AA
R5F117BA
R5F117GA
8 KB
2 KB
0.7 KB
R5F11768
R5F11778
R5F117A8
—
—
Note
The flash library uses RAM in self-programming and rewriting of the data flash memory.
The target products and start address of the RAM areas used by the flash library are shown below.
R5F117xC (x = A, B, G): Start address FF300H
For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for RL78 Family
(R20UT2944).
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 2 of 101
RL78/I1D
1.2
1. OUTLINE
Ordering Information
Figure 1 - 1 Part Number, Memory Size, and Package of RL78/I1D
Part No.
R 5 F 1 1 7 GC G x x x F B # U 0
Packaging specification
#10: Tray (LFQFP, LQFP, LSSOP, TSSOP)
#30: Tray (LFQFP, LQFP, LSSOP, TSSOP), Tube (LSSOP) Note 1
#U0, #00, #20: Tray (HWQFN, HVQFN)
#50: Embossed Tape (LFQFP, LQFP, LSSOP, TSSOP)
#W0, #40: Embossed Tape (HWQFN, HVQFN)
Package type:
SM: TSSOP, 0.65 mm pitch
SP: LSSOP, 0.65 mm pitch
FP: LQFP, 0.80 mm pitch
FB: LFQFP, 0.50 mm pitch
NA: HWQFN, 0.50 mm pitch Note 2
NA: HVQFN, 0.50 mm pitch Note 3
ROM number (Omitted for blank products)
Fields of application:
G: Industrial applications, TA = -40 to +105 °C
ROM capacity:
8: 8 KB
A: 16 KB
C: 32 KB
Pin count:
6: 20-pin
7: 24-pin
A: 30-pin
B: 32-pin
G: 48-pin
RL78/I1D
Memory type:
F : Flash memory
Renesas MCU
Renesas semiconductor product
Note 1.
The packaging specification is only “Tube” for products in the 20-pin LSSOP.
Note 2.
24-pin products
Note 3.
32-pin products
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 3 of 101
RL78/I1D
Pin
count
1. OUTLINE
Package
20 pins 20-pin plastic LSSOP
Ordering Part Number
R5F11768GSP#30, R5F1176AGSP#30,
(4.4 × 6.5 mm, 0.65 mm pitch)
R5F11768GSP#50, R5F1176AGSP#50
20-pin plastic TSSOP
R5F11768GSM#10, R5F1176AGSM#10,
(4.4 × 6.5 mm, 0.65 mm pitch)
R5F11768GSM#30, R5F1176AGSM#30,
RENESAS Code
PLSP0020JB-A
PTSP0020JI-A
R5F11768GSM#50, R5F1176AGSM#50
24 pins 24-pin plastic HWQFN
(4 × 4 mm, 0.5 mm pitch)
R5F11778GNA#U0, R5F1177AGNA#U0,
PWQN0024KE-A
R5F11778GNA#W0, R5F1177AGNA#W0
R5F11778GNA#00, R5F1177AGNA#00,
PWQN0024KF-A
R5F11778GNA#20, R5F1177AGNA#20,
R5F11778GNA#40, R5F1177AGNA#40
30 pins 30-pin plastic LSSOP
(7.62 mm (300), 0.65 mm pitch)
R5F117A8GSP#10, R5F117AAGSP#10, R5F117ACGSP#10,
PLSP0030JB-B
R5F117A8GSP#30, R5F117AAGSP#30, R5F117ACGSP#30,
R5F117A8GSP#50, R5F117AAGSP#50, R5F117ACGSP#50
32 pins 32-pin plastic HVQFN
(5 × 5 mm, 0.5 mm pitch)
R5F117BAGNA#00, R5F117BCGNA#00,
PVQN0032KE-A
R5F117BAGNA#20, R5F117BCGNA#20,
R5F117BAGNA#40, R5F117BCGNA#40
32-pin plastic LQFP
R5F117BAGFP#10, R5F117BCGFP#10,
(7 × 7 mm, 0.8 mm pitch)
R5F117BAGFP#30, R5F117BCGFP#30,
PLQP0032GB-A
R5F117BAGFP#50, R5F117BCGFP#50
48 pins 48-pin plastic LFQFP
(7 × 7 mm, 0.5 mm pitch)
R5F117GAGFB#10, R5F117GCGFB#10,
PLQP0048KB-A
R5F117GAGFB#30, R5F117GCGFB#30,
R5F117GAGFB#50, R5F117GCGFB#50
Caution
The ordering part numbers represent the numbers at the time of publication. For the latest ordering part
numbers, refer to the target product page of the Renesas Electronics website.
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 4 of 101
RL78/I1D
1. OUTLINE
1.3
Pin Configuration (Top View)
1.3.1
20-pin products
• 20-pin plastic LSSOP (4.4 6.5 mm, 0.65 mm pitch)
• 20-pin plastic TSSOP (4.4 6.5 mm, 0.65 mm pitch)
1
2
3
4
5
6
7
8
9
10
RL78/I1D
(Top View)
P12/ANI2/AMP0+
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P55/SI00/RxD0/SDA00/INTP2/TOOLRxD
20
19
18
17
16
15
14
13
12
11
P13/ANI3/AMP0P14/ANI4/IVCMP0/AMP0O
AVSS
AVDD
P22/ANI11/AMP3+
P21/ANI12/AMP3P20/ANI13/IVCMP1/AMP3O
P31/TI01/TO00/PCLBUZ0/IVREF1
P30/SCK00/SCL00/TI00/TO01/IVREF0
P54/SO00/TxD0/INTP1/TOOLTxD
Caution 1. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Caution 2. Make AVSS pin the same potential as VSS pin.
Caution 3. Make AVDD pin the same potential as VDD pin.
Remark
For pin identification, see 1.4 Pin Identification.
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Page 5 of 101
RL78/I1D
1.3.2
1. OUTLINE
24-pin products
AVDD
P22/ANI11/AMP3+
P21/ANI12/AMP3P20/ANI13/IVCMP1/AMP3O
P31/TI01/TO00/PCLBUZ0/IVREF1
P30/(SCK00)/(SCL00)/TI00/TO01/IVREF0
• 24-pin plastic HWQFN (4 4 mm, 0.5 mm pitch)
exposed die pad
AVSS
P14/ANI4/IVCMP0/AMP0O
P13/ANI3/AMP0P12/ANI2/AMP0+
P40/TOOL0
RESET
18 17 16 15 14 13
19
12
20
11
21 RL78/I1D 10
22 (Top View)
9
23
8
24
7
1 2 3 4 5 6
P51/KR0/SCK01/SCL01/TI02/TO02
P52/KR1/SI01/SDA01/TI03/TO03
P53/KR2/SO01/VCOUT0
P54/SO00/TxD0/INTP1/TOOLTxD
P55/SI00/RxD0/SDA00/INTP2/TOOLRxD
P56/SCK00/SCL00/INTP3
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
V DD
INDEX MARK
Caution 1. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Caution 2. Make AVSS pin the same potential as VSS pin.
Caution 3. Make AVDD pin the same potential as VDD pin.
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. It is recommended to connect an exposed die pad to VSS.
Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0
(PIOR0).
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 6 of 101
RL78/I1D
1. OUTLINE
1.3.3
30-pin products
• 30-pin plastic LSSOP (7.62 mm (300), 0.65 mm pitch)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RL78/I1D
(Top View)
P14/ANI4/IVCMP0/AMP0O
P13/ANI3/AMP0P12/ANI2/AMP0+
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
V SS
V DD
P56/SCK00/SCL00/INTP3
P55/SI00/RxD0/SDA00/INTP2/TOOLRxD
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P15/ANI5/AMP1+
P16/ANI6/AMP1P17/ANI7/AMP1O
AVSS
AVDD
P25/ANI8/AMP2+
P24/ANI9/AMP2P23/ANI10/AMP2O
P22/ANI11/AMP3+
P21/ANI12/AMP3P20/ANI13/IVCMP1/AMP3O
P33/TI02/TO02/INTP5
P31/TI01/TO00/PCLBUZ0/IVREF1
P30/(SCK00)/(SCL00)/TI00/TO01/IVREF0
P54/SO00/TxD0/INTP1/TOOLTxD
Caution 1. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Caution 2. Make AVSS pin the same potential as VSS pin.
Caution 3. Make AVDD pin the same potential as VDD pin.
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0
(PIOR0).
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 7 of 101
RL78/I1D
1. OUTLINE
1.3.4
32-pin products
AV SS
AV DD
P25/ANI8/AMP2+
P24/ANI9/AMP2P23/ANI10/AMP2O
P22/ANI11/AMP3+
P21/ANI12/AMP3P20/ANI13/IVCMP1/AMP3O
• 32-pin plastic HVQFN (5 5 mm, 0.5 mm pitch)
exposed die pad
P17/ANI7/AMP1O
P16/ANI6/AMP1P15/ANI5/AMP1+
P14/ANI4/IVCMP0/AMP0O
P13/ANI3/AMP0P12/ANI2/AMP0+
P40/TOOL0
RESET
25
26
27
28
29
30
31
32
24 23 22 21 20 19 18 17
16
15
14
13
RL78/I1D
12
(Top View)
11
10
9
1 2 3 4 5 6 7 8
P31/TI01/TO00/PCLBUZ0/IVREF1
P30/(SCK00)/(SCL00)/TI00/TO01/IVREF0
P51/KR0/SCK01/SCL01/TI02/TO02
P52/KR1/SI01/SDA01/TI03/TO03
P53/KR2/SO01/VCOUT0
P54/SO00/TxD0/INTP1/TOOLTxD
P55/SI00/RxD0/SDA00/INTP2/TOOLRxD
P56/SCK00/SCL00/INTP3
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
V SS
V DD
INDEX MARK
Caution 1. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Caution 2. Make AVSS pin the same potential as VSS pin.
Caution 3. Make AVDD pin the same potential as VDD pin.
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0
(PIOR0).
Remark 3. It is recommended to connect an exposed die pad to VSS.
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Jun 30, 2020
Page 8 of 101
RL78/I1D
1. OUTLINE
AV SS
AV DD
P25/ANI8/AMP2+
P24/ANI9/AMP2P23/ANI10/AMP2O
P22/ANI11/AMP3+
P21/ANI12/AMP3P20/ANI13/IVCMP1/AMP3O
• 32-pin plastic LQFP (7 7 mm, 0.8 mm pitch)
25
26
27
28
29
30
31
32
24 23 22 21 20 19 18 17
16
15
14
RL78/I1D
13
(Top View)
12
11
10
9
1 2 3 4 5 6 7 8
P31/TI01/TO00/PCLBUZ0/IVREF1
P30/(SCK00)/(SCL00)/TI00/TO01/IVREF0
P51/KR0/SCK01/SCL01/TI02/TO02
P52/KR1/SI01/SDA01/TI03/TO03
P53/KR2/SO01/VCOUT0
P54/SO00/TxD0/INTP1/TOOLTxD
P55/SI00/RxD0/SDA00/INTP2/TOOLRxD
P56/SCK00/SCL00/INTP3
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
V DD
P17/ANI7/AMP1O
P16/ANI6/AMP1P15/ANI5/AMP1+
P14/ANI4/IVCMP0/AMP0O
P13/ANI3/AMP0P12/ANI2/AMP0+
P40/TOOL0
RESET
Caution 1. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Caution 2. Make AVSS pin the same potential as VSS pin.
Caution 3. Make AVDD pin the same potential as VDD pin.
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0
(PIOR0).
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 9 of 101
RL78/I1D
1. OUTLINE
1.3.5
48-pin products
P32/KR3/(TI01/TO00)/INTP6
P31/TI01/TO00/PCLBUZ0/IVREF1
P20/ANI13/IVCMP1/AMP3O
P33/(TI02/TO02)/INTP5
36 35 34 33 32 31 30 29 28 27 26 25
24
37
23
38
22
39
21
40
20
41
19
42
18
43
17
44
16
45
46
15
14
47
13
48
1 2 3 4 5 6 7 8 9 10 11 12
P30/(SCK00)/(SCL00)/TI00/TO01/IVREF0
P50/(TI00/TO01)/RTC1HZ
P51/KR0/SCK01/SCL01/TI02/TO02
P52/KR1/SI01/SDA01/TI03/TO03
P53/KR2/SO01/VCOUT0
P54/SO00/TxD0/INTP1/TOOLTxD
P55/SI00/RxD0/SDA00/INTP2/TOOLRxD
P56/SCK00/SCL00/INTP3
P57/(TI03/TO03)/INTP4/VCOUT1
P63/SSI00
P62
P61
P00
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P60
RL78/I1D
(Top View)
P01/PCLBUZ1
P16/ANI6/AMP1P15/ANI5/AMP1+
P14/ANI4/IVCMP0/AMP0O
P13/ANI3/AMP0P12/ANI2/AMP0+
P11/ANI1/AVREFM
P10/ANI0/AVREFP
P130
P40/TOOL0
P04/ANI18
P03/ANI17
P02/ANI16
P24/ANI9/AMP2P23/ANI10/AMP2O
P22/ANI11/AMP3+
P21/ANI12/AMP3-
P17/ANI7/AMP1O
AVSS
AVDD
P25/ANI8/AMP2+
• 48-pin plastic LFQFP (7 7 mm, 0.5 mm pitch)
Caution 1. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Caution 2. Make AVSS pin the same potential as VSS pin.
Caution 3. Make AVDD pin the same potential as VDD pin.
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0
(PIOR0).
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 10 of 101
RL78/I1D
1.4
1. OUTLINE
Pin Identification
ANI0 to ANI13,
PCLBUZ0, PCLBUZ1
: Programmable clock output/buzzer
ANI16 to ANI18
: Analog input
output
AVDD
: Analog power supply
REGC
: Regulator capacitance
AVREFM
: A/D converter reference
RESET
: Reset
potential (- side) input
RTC1HZ
: Real-time clock correction clock (1 Hz)
AVREFP
: A/D converter reference
RxD0
: Receive data
AVSS
: Analog ground
SCK00, SCK01
: Serial clock input/output
EXCLK
: External clock input
SCL00, SCL01
: Serial clock input/output
(main system clock)
SDA00, SDA01
: Serial data input/output
potential (+ side) input
EXCLKS
: External clock input
(subsystem clock)
output
SI00, SI01
: Serial data input
SO00, SO01
: Serial data output
INTP0 to INTP6
: External interrupt input
SSI00
: Serial interface chip select input
IVCMP0, IVCMP1
: Comparator input
TI00 to TI03
: Timer input
IVREF0, IVREF1
: Comparator reference input
TO00 to TO03
: Timer output
KR0 to KR3
: Key return
TOOL0
: Data input/output for tool
P00 to P04
: Port 0
TOOLRxD, TOOLTxD
: Data input/output for external device
P10 to P17
: Port 1
TxD0
: Transmit data
: Comparator output
P20 to P25
: Port 2
VCOUT0, VCOUT1
P30 to P33
: Port 3
AMP0+, AMP1+,
P40
: Port 4
AMP2+, AMP3+
P50 to P57
: Port 5
AMP0-, AMP1-,
: Operational amplifier (+side) input
P60 to P63
: Port 6
AMP2-, AMP3-
P121 to P124
: Port 12
AMP0O, AMP1O,
P130, P137
: Port 13
AMP2O, AMP3O
: Operational amplifier output
VDD
: Power supply
VSS
: Ground
X1, X2
: Crystal oscillator (main system clock)
XT1, XT2
: Crystal oscillator (subsystem clock)
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Jun 30, 2020
: Operational amplifier (-side) input
Page 11 of 101
RL78/I1D
1.5
1. OUTLINE
Block Diagram
1.5.1
48-pin products
Port 0
5
P00 to P 04
Port 1
8
P10 to P 17
Port 2
6
P20 to P 25
4
P30 to P 33
T IMER ARRAY UNIT 0
( 4ch)
T I00
TO00
EVENT LINK CONT ROLLER
( ELC)
ch00
T I01
TO01
ch01
T I02
TO02
ch02
Port 3
T I03
TO03
ch03
Port 4
P40
Port 5
8
P50 to P 57
Port 6
4
P60 to P 63
Port 12
4
P121 to P124
8-BIT INTERVAL T IMER 0
ch00
BCD CORRECTION
CIRCUIT
CODE F LASH :
32 KB
DATA F LASH:
2 KB
ch01
DAT A OPERATION
CIRCUIT (DOC )
P130
Port 13
P137
8-BIT INTERVAL T IMER 1
ch10
INT
ch11
ON -CHIP DEBUG
T OOL0 /P40
CLOCK OUT PUT /
BUZZ ER OUTPUT
CONT ROLLER
PCLBUZ 0
RL 78 CPU CORE
DAT A T RANSF ER
CONT ROLLER (DT C )
MULDIV
RAM 3 KB
SERIAL ARRAY UNIT 0
(2 ch)
RxD 0
TxD0
SI00
CSI00
CLOCK GENERATOR
+
RESET CIRCUIT
X1
CSI01
IIC 00
EXTERNAL INT ERRUPT
7ch
7
INT P0 to INTP 6
RTC1 HZ
XT 1
IIC 01
SDA 01
HIGH -SPEED
POR/
LVD
V DD
15
A/D CONVERT ER
(16 ch)
ON -CHIP
OSCIL L AT OR
24 MHz
V SS
M IDDL E- SPEED
ON- CHIP
L OW -SPEED
ON - CHIP
OSCIL L AT OR
OSCIL L AT OR
4 MHz
15 kHz
XT 2/EXCLK
ANI2 to ANI 13,
ANI16 to ANI 18
ANI0 /AV REF P
ANI1 /AV REF M
COMPARATOR 0
VCOUT0
IVCMP 0
IVREF 0
REGULATOR
COMPARATOR 1
VCOUT1
IVCMP 1
IVREF 1
REGC
OPERAT IONAL
AMPLIFIER (4ch)
OPERATIONAL
AMPLIF IER 0
TOOLRxD/P55 ,
TOOLTxD/P54
WATCHDOG T IMER
(WDT)
CRC
F REQUENCY
MEASUREMENT CIRCUIT
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
12 -BIT INT ERVAL
T IMER
COMPARATOR (2 ch)
SDA 00
SCL 01
KR0 to KR3
X2/ EXCLK
SUBSYST EM CLOCK
GENERAT OR
32.768 kHz
SO01
SCL 00
4
REAL TIME CLOCK 2
MAIN SYSTEM CLOCK
GENERAT OR
1 to 20 MHz
SCK 01
SI01
KEY INTERRUPT
4ch
RESET
UART0
SCK 00
SO00
SSI00
PCLBUZ 1
OPERATIONAL
AMPLIF IER 1
OPERATIONAL
AMPLIF IER 2
OPERATIONAL
AMPLIF IER 3
AMP0+
AMP0AMP0O
AMP1+
AMP1AMP1O
AMP2+
AMP2AMP2O
AMP3+
AMP3AMP3O
Page 12 of 101
RL78/I1D
1.6
1. OUTLINE
Outline of Functions
Remark
This outline describes the functions at the time when Peripheral I/O redirection register 0 (PIOR0) are set
to 00H.
(1/2)
Item
Code flash memory (KB)
20-pin
24-pin
30-pin
32-pin
48-pin
R5F1176x
(x = 8, A)
R5F1177x
(x = 8, A)
R5F117Ax
(x = 8, A, C)
R5F117Bx
(x = A, C)
R5F117Gx
(x = A, C)
8 to 16 KB
8 to 16 KB
8 to 32 KB
16 to 32 KB
16 to 32 KB
Data flash memory (KB)
RAM
Address space
Main system
clock
2 KB
2 KB
2 KB
2 KB
0.7 to 2.0 KB
0.7 to 3.0 KB Note
2.0 to 3.0 KB Note
2.0 to 3.0 KB Note
1 MB
High-speed system clock (fMX)
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
HS (High-speed main) mode:1 to 20 MHz (VDD = 2.7 to 3.6 V),
HS (High-speed main) mode:1 to 16 MHz (VDD = 2.4 to 3.6 V),
LS (Low-speed main) mode:1 to 8 MHz (VDD = 1.8 to 3.6 V),
LV (Low-voltage main) mode:1 to 4 MHz (VDD = 1.6 to 3.6 V),
LP (Low-power main) mode:1 MHz (VDD = 1.8 to 3.6 V)
High-speed on-chip oscillator
clock (fIH) Max: 24 MHz
HS (High-speed main) mode:
HS (High-speed main) mode:
LS (Low-speed main) mode:
LV (Low-voltage main) mode:
LP (Low-power main) mode:
Middle-speed on-chip oscillator
clock (fIM) Max: 4 MHz
Subsystem
clock
2 KB
0.7 to 2.0 KB
Subsystem clock oscillator
(fSX, fSXR)
Low-speed on-chip oscillator
clock (fIL)
General-purpose register
Minimum instruction execution time
1 to 24 MHz (VDD = 2.7 to 3.6 V),
1 to 16 MHz (VDD = 2.4 to 3.6 V),
1 to 8 MHz (VDD = 1.8 to 3.6 V),
1 to 4 MHz (VDD = 1.6 to 3.6 V),
1 MHz (VDD = 1.8 to 3.6 V)
—
XT1 (crystal) oscillation
32.768 kHz (TYP.): VDD = 1.6 to 3.6 V
15 kHz (TYP.): VDD = 1.6 to 3.6 V
8 bits 32 registers (8 bits 8 registers 4 banks)
0.04167 s (High-speed on-chip oscillator clock: fIH = 24 MHz operation)
0.05 s (High-speed system clock: fMX = 20 MHz operation)
30.5s
(Subsystem clock oscillator clock: fSX = 32.768 kHz
operation)
—
Instruction set
I/O port
Timer
•
•
•
•
•
Data transfer (8/16 bits)
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits 8 bits, 16 bits 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and Accumulation (16 bits 16 bits + 32 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
Total
14
18
24
26
42
CMOS I/O
11
15
19
21
33
CMOS input
3
3
5
5
5
N-ch open-drain I/O
(6 V tolerance)
—
—
—
—
4
3
4
4
16-bit timer
4 channels
Watchdog timer
1 channel
Real-time clock
1 channel
12-bit interval timer
1 channel
8/16-bit interval timer
4 channels (8 bit) / 2 channels (16 bit)
Timer output
2
RTC output
Note
4
—
1 channel
• 1 Hz
(subsystem clock generator and RTC2/other clock:
fSX = 32.768 kHz)
The flash library uses RAM in self-programming and rewriting of the data flash memory.
The target products and start address of the RAM areas used by the flash library are shown below.
R5F117xC (x = A, B, G): Start address FF300H
For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for RL78 Family
(R20UT2944).
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Page 13 of 101
RL78/I1D
1. OUTLINE
(2/2)
Item
20-pin
24-pin
30-pin
32-pin
48-pin
R5F1176x
(x = 8, A)
R5F1177x
(x = 8, A)
R5F117Ax
(x = 8, A, C)
R5F117Bx
(x = A, C)
R5F117Gx
(x = A, C)
1
1
1
1
2
Clock output/buzzer output
[20-pin, 24-pin products]
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
[30-pin, 32-pin, 48-pin products]
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(subsystem clock generator and RTC/other clock: fSXR = 32.768 kHz operation)
12-bit resolution A/D converter
6 channels
6 channels
12 channels
Comparator (Window Comparator)
2 channels
Operational amplifier
2 channels
Data Operation Circuit (DOC)
Comparison, addition, and subtraction of 16-bit data
Serial interface
12 channels
17 channels
4 channels
[20-pin, 30-pin products]
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
[24-pin, 32-pin, 48-pin products]
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
Data transfer controller (DTC)
Event link controller (ELC)
Vectored interrupt
Internal
sources
External
16 sources
20 sources
19 sources
20 sources
22 sources
Event input: 15
Event input: 17
Event input: 17
Event input: 17
Event input: 20
Event trigger
Event trigger
Event trigger
Event trigger
Event trigger
output: 5
output: 5
output: 7
output: 7
output: 7
22
Key interrupt
Reset
•
•
•
•
22
24
24
24
3
5
5
5
8
—
3
—
3
4
Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
• Internal reset by illegal instruction execution Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit
Voltage detector
• Power-on-reset: 1.51 ± 0.04V (TA = -40 to +85°C)
• Power-down-reset: 1.50 ± 0.04 V (TA = -40 to +85°C)
Power on
1.67 V to 3.13 V (12 stages)
Power down
1.63 V to 3.06 V (12 stages)
On-chip debug function
Provided (Enable to tracing)
Power supply voltage
VDD = 1.6 to 3.6 V
Operating ambient temperature
TA = -40 to +105°C
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
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Page 14 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
2. ELECTRICAL SPECIFICATIONS
Caution 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and
evaluation. Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded when this
function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not
liable for problems occurring when the on-chip debug function is used.
Caution 2. The pins mounted depend on the product. Refer to 2.1 Port Functions to 2.2.1 Functions for each
product in the RL78/I1D User’s Manual.
Caution 3. Please contact Renesas Electronics sales office for derating of operation under TA = +85 to +105°C.
Derating is the systematic reduction of load for the sake of improved reliability.
Caution 4. When operating temperature exceeds 85°C, only HS (high-speed main) mode can be used as the
flash operation mode. Regulator mode should be used with the normal setting (MCSEL = 0).
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Page 15 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
2.1
Absolute Maximum Ratings
Absolute Maximum Ratings
Parameter
Supply voltage
(1/2)
Symbols
VDD, AVDD
Conditions
VDD = AVDD
AVREFP
Ratings
-0.3 to + 4.6
0.3 to AVDD + 0.3
AVSS
Unit
V
Note 2
V
Note 2
V
-0.5 to + 0.3
AVREFM
-0.3 to AVDD + 0.3
V
and AVREFM ≤ AVREFP
REGC pin input voltage
VIREGC
REGC
-0.3 to + 2.8
and -0.3 to VDD + 0.3
Input voltage
VI1
P00 to P04, P30 to P33, P40, P50 to P57,
V
Note 1
-0.3 to VDD + 0.3 Note 2
V
-0.3 to + 6.5
V
-0.3 to AVDD + 0.3 Note 2
V
-0.3 to VDD + 0.3 Note 2
V
-0.3 to AVDD + 0.3 Note 2
V
-0.3 to VDD + 0.3
V
P121 to P124, P130, P137,
EXCLK, EXCLKS, RESET
Output voltage
VI2
P60 to P63 (N-ch open-drain)
VI3
P10 to P17, P20 to P25
VO1
P00 to P04, P30 to P33, P40, P50 to P57,
P60 to P63, P130
Analog input voltage
VO2
P10 to P17, P20 to P25
VAI1
ANI16 to ANI18
and -0.3 to AVREF(+) + 0.3 Notes 2, 3
VAI2
ANI0 to ANI13
-0.3 to AVDD + 0.3
and -0.3 to AVREF(+) + 0.3
VAI3
Note 1.
Operational amplifier input pin
V
Notes 2, 3
V
-0.3 to AVDD + 0.3 Note 2
Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). This value regulates the absolute maximum rating of the
REGC pin. Do not use this pin with voltage applied to it.
Note 2.
Must be 4.6 V or lower.
Note 3.
Do not exceed AVREF (+) + 0.3 V in case of A/D conversion target pin.
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the product must be used under conditions that ensure that the absolute maximum
ratings are not exceeded.
Remark 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
Remark 2. AVREF (+): + side reference voltage of the A/D converter.
Remark 3. VSS: Reference voltage
R01DS0244EJ0230 Rev. 2.30
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Page 16 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter
Output current, high
(2/2)
Symbols
IOH1
IOH2
Conditions
IOL1
Unit
-40
mA
Per pin
P00 to P04, P30 to P33, P40, P50 to P57, P130
Total of all pins
P00 to P04, P40, P130
-70
mA
-170 mA
P30 to P33, P50 to P57
-100
mA
Per pin
P10 to P17, P20 to P25
-0.1
mA
-1.4
mA
40
mA
Total of all pins
Output current, low
Ratings
Per pin
P00 to P04, P30 to P33, P40, P50 to P57, P60 to P63,
P130
IOL2
Total of all pins
P00 to P04, P40, P130
70
mA
170 mA
P30 to P33, P50 to P57, P60 to P63
100
mA
Per pin
P10 to P17, P20 to P25
0.4
mA
Total of all pins
Operating ambient
TA
temperature
Storage temperature
Caution
In normal operation mode
5.6
mA
-40 to +105
°C
-65 to +150
°C
In flash memory programming mode
Tstg
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the product must be used under conditions that ensure that the absolute maximum
ratings are not exceeded.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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Page 17 of 101
RL78/I1D
2.2
2.2.1
2. ELECTRICAL SPECIFICATIONS
Oscillator Characteristics
X1, XT1 characteristics
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Resonator
Resonator
X1 clock oscillation frequency (fX) Note
XT1 clock oscillation frequency (fXT) Note
Note
Conditions
MIN.
TYP.
MAX.
Unit
MHz
Ceramic resonator/
2.7 V ≤ VDD ≤ 3.6 V
1.0
20.0
crystal resonator
2.4 V ≤ VDD < 2.7 V
1.0
16.0
1.8 V ≤ VDD < 2.4 V
1.0
8.0
1.6 V ≤ VDD < 1.8 V
1.0
4.0
Crystal resonator
32
32.768
35
kHz
Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time.
Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator
characteristics.
Caution
Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock
oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user.
Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select
register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used.
Remark
2.2.2
When using the X1 oscillator and XT1 oscillator, refer to 6.4 System Clock Oscillator in the RL78/I1D User’s Manual.
On-chip oscillator characteristics
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Oscillators
High-speed on-chip oscillator clock frequency
Parameters
Notes 1, 2
Conditions
fIH
High-speed on-chip oscillator clock frequency accuracy
-20 to +85°C
-40 to -20°C
+85 to +105°C
Middle-speed on-chip oscillator oscillation frequency Note 2
Low-speed on-chip oscillator clock frequency accuracy
Note 1.
TYP.
MAX.
Unit
1
24
MHz
1.8 V ≤ VDD ≤ 3.6 V
-1.0
+1.0
%
1.6 V ≤ VDD < 1.8 V
-5.0
+5.0
1.8 V ≤ VDD ≤ 3.6 V
-1.5
+1.5
1.6 V ≤ VDD < 1.8 V
-5.5
+5.5
2.4 V ≤ VDD ≤ 3.6 V
-2.0
+2.0
%
1
4
MHz
fIM
1.8V ≤ VDD ≤ 3.6V
Middle-speed on-chip oscillator oscillation frequency accuracy
Low-speed on-chip oscillator clock frequency Note 2
MIN.
-12
fIL
+12
15
%
%
kHz
-15
+15
%
High-speed on-chip oscillator frequency is selected with bits 0 to 3 of the option byte (000C2H) and bits 0 to 2 of the
HOCODIV register.
Note 2.
This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time.
R01DS0244EJ0230 Rev. 2.30
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Page 18 of 101
RL78/I1D
2.3
2.3.1
2. ELECTRICAL SPECIFICATIONS
DC Characteristics
Pin characteristics
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(1/5)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Items
Output current, high
Symbol
IOH1
Conditions
Per pin for P00 to P04, P30 to P33, P40,
MIN.
TYP.
TA = -40 to +85°C
P50 to P57, P130
Note 1
MAX.
Unit
-10.0
mA
Note 2
TA = +85 to +105°C
-3.0
mA
Note 2
Total of P00 to P04, P40, P130
2.7 V ≤ VDD ≤ 3.6 V
-10.0
mA
(When duty ≤ 70% Note 3)
1.8 V ≤ VDD < 2.7 V
-5.0
mA
1.6 V ≤ VDD < 1.8 V
-2.5
mA
Total of P30 to P33, P50 to P57
2.7 V ≤ VDD ≤ 3.6 V
-19.0
mA
(When duty ≤ 70% Note 3)
1.8 V ≤ VDD < 2.7 V
-10.0
mA
1.6 V ≤ VDD < 1.8 V
Total of all pins
-5.0
mA
-29.0
mA
-0.1
mA
(When duty ≤ 70% Note 3)
IOH2
Per pin for P10 to P17, P20 to P25
Note 2
1.6 V ≤ VDD ≤ 3.6 V
Total of all pins
(When duty ≤ 70%
-1.4
mA
Note 3)
Note 1.
Value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an output pin.
Note 2.
Do not exceed the total current value.
Note 3.
Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOH × 0.7)/(n × 0.01)
Where n = 80% and IOH = -10.0 mA
Total output current of pins = (-10.0 × 0.7)/(80 × 0.01) ≈ -8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Caution
P30 and P51 to P56 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
R01DS0244EJ0230 Rev. 2.30
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Page 19 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Items
Output current, low
Symbol
IOL1
(2/5)
Conditions
Per pin for P00 to P04, P30 to P33, P40,
MIN.
TYP.
TA = -40 to +85°C
P50 to P57, P130
Note 1
MAX.
Unit
20.0
mA
Note 2
TA = +85 to +105°C
8.5
mA
Note 2
Per pin for P60 to P63
15.0
mA
Note 2
Total of P00 to P04, P40, P130
2.7 V ≤ VDD ≤ 3.6 V
15.0
mA
(When duty ≤ 70%
1.8 V ≤ VDD < 2.7 V
9.0
mA
1.6 V ≤ VDD < 1.8 V
4.5
mA
Total of P30 to P33, P50 to P57, P60 to P63 2.7 V ≤ VDD ≤ 3.6 V
35.0
mA
(When duty ≤ 70% Note 3)
1.8 V ≤ VDD < 2.7 V
20.0
mA
1.6 V ≤ VDD < 1.8 V
10.0
mA
50.0
mA
0.4
mA
Note 3)
Total of all pins
(When duty ≤ 70% Note 3)
Per pin for P10 to P17, P20 to P25
IOL2
Note 2
Total of all pins
1.6 V ≤ VDD ≤ 3.6 V
5.6
mA
(When duty ≤ 70% Note 3)
Note 1.
Value of current at which the device operation is guaranteed even if the current flows from an output pin to the VSS pin.
Note 2.
Do not exceed the total current value.
Note 3.
Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOL × 0.7)/(n × 0.01)
Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) ≈ 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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Page 20 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Items
Input voltage, high
Symbol
VIH1
Conditions
P00 to P04, P30 to P33, P40,
(3/5)
MIN.
Normal input buffer
MAX.
Unit
0.8 VDD
TYP.
VDD
V
2.0
VDD
V
1.5
VDD
V
P50 to P57, P130
VIH2
P30, P32, P33, P51, P52,
TTL input buffer
P54 to P57
3.3 V ≤ VDD ≤ 3.6 V
TTL input buffer
1.6 V ≤ VDD < 3.3 V
Input voltage, low
VIH3
P10 to P17, P20 to P25
0.7 AVDD
AVDD
V
VIH4
P60 to P63
0.7 VDD
6.0
V
VIH5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0.8 VDD
VDD
V
VIL1
P00 to P04, P30 to P33, P40,
Normal input buffer
0
0.2 VDD
V
P30, P32, P33, P51, P52,
TTL input buffer
0
0.5
V
P54 to P57
3.3 V ≤ VDD ≤ 3.6 V
0
0.32
V
P50 to P57, P130
VIL2
TTL input buffer
1.6 V ≤ VDD < 3.3 V
VIL3
P10 to P17, P20 to P25
0
0.3 AVDD
V
VIL4
P60 to P63
0
0.3 VDD
V
VIL5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0
0.2 VDD
V
Caution
The maximum value of VIH of pins P30 and P51 to P56 is VDD, even in the N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Items
Output voltage, high
Symbol
VOH1
Conditions
(4/5)
MIN.
P00 to P04, P30 to P33, P40,
2.7 V ≤ VDD ≤ 3.6 V,
P50 to P57, P130
IOH = -2.0 mA
1.8 V ≤ VDD ≤ 3.6 V Note 3,
TYP.
MAX.
Unit
VDD - 0.6
V
VDD - 0.5
V
VDD - 0.5
V
AVDD - 0.5
V
IOH = -1.5 mA
1.6 V ≤ VDD ≤ 3.6 V Note 1,
IOH = -1.0 mA
VOH2
P10 to P17, P20 to P25
1.6 V ≤ AVDD ≤ 3.6 V Note 2,
IOH = -100 A
Output voltage, low
VOL1
P00 to P04, P30 to P33, P40,
2.7 V ≤ VDD ≤ 3.6 V,
P50 to P57, P130
IOL = 3.0 mA
2.7 V ≤ VDD ≤ 3.6 V,
0.6
V
0.4
V
0.4
V
0.4
V
0.4
V
0.4
V
0.4
V
0.4
V
IOL = 1.5 mA
1.8 V ≤ VDD ≤ 3.6 V Note 3,
IOL = 0.6 mA
1.6 V ≤ AVDD ≤ 3.6 V Note 1,
IOL = 0.3 mA
VOL2
P10 to P17, P20 to P25
1.6 V ≤ AVDD ≤ 3.6 V Note 2,
IOL = 400 A
VOL3
P60 to P63
2.7 V ≤ VDD ≤ 3.6 V,
IOL
= 3.0 mA
1.8 V ≤ VDD ≤ 3.6 V Note 3,
IOL = 2.0 mA
1.6 V ≤ AVDD ≤ 3.6 V Note 1,
IOL = 1.0 mA
Note 1.
Only TA = -40 to +85°C is guaranteed.
Note 2.
The condition that 2.4 V ≤ AVDD ≤ 3.6 V is guaranteed when +85°C < TA ≤ +105°C.
Note 3.
The condition that 2.4 V ≤ VDD ≤ 3.6 V is guaranteed when +85°C < TA ≤ +105°C.
Caution
P30 and P51 to P56 do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 22 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Items
Symbol
Input leakage
ILIH1
(5/5)
Conditions
P00 to P04, P30 to P33, P40,
MAX.
Unit
VI = VDD
MIN.
TYP.
1
A
1
A
1
A
10
A
P50 to P57, P60 to P63, P130,
current, high
P137
ILIH2
RESET
VI = VDD
ILIH3
P121 to P124 (X1, X2, EXCLK,
VI = VDD
XT1, XT2, EXCLKS)
In input port or
external clock input
In resonator
connection
Input leakage
ILIH4
P10 to P17, P20 to P25
VI = AVDD
1
A
ILIL1
P00 to P04, P30 to P33, P40,
VI = VSS
-1
A
-1
A
-1
A
-10
A
-1
A
100
k
P50 to P57, P60 to P63, P130,
current, low
P137
ILIL2
RESET
VI = VSS
ILIL3
P121 to P124 (X1, X2, EXCLK,
VI = VSS
XT1, XT2, EXCLKS)
In input port or
external clock input
In resonator
connection
On-chip pull-up
resistance
Remark
ILIL4
P10 to P17, P20 to P25
VI = AVSS
RU
P00 to P04, P30 to P33, P40,
VI = VSS, In input port
10
20
P50 to P57, P130
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 23 of 101
RL78/I1D
2.3.2
2. ELECTRICAL SPECIFICATIONS
Supply current characteristics
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(1/4)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Supply current
Note 1
Symbol
IDD1
Conditions
Operating
mode
MIN.
TYP.
MAX.
HS (high-speed main)
mode
Note 3,
fIH = 24 MHz
TA = -40 to +105°C
Basic
operation
VDD = 3.0 V
1.4
HS (high-speed main)
mode
fIH = 24 MHz Note 3,
TA = -40 to +85°C
Normal
operation
VDD = 3.0 V
3.2
fIH = 24 MHz Note 3,
TA = +85 to +105°C
Normal
operation
VDD = 3.0 V
fIH = 16 MHz Note 3,
TA = -40 to +85°C
Normal
operation
VDD = 3.0 V
fIH = 16 MHz Note 3,
TA = +85 to +105°C
Normal
operation
VDD = 3.0 V
LS (low-speed main)
mode
(MCSEL = 0)
fIH = 8 MHz Note 3,
TA = -40 to +85°C
Normal
operation
VDD = 3.0 V
1.1
2.0
VDD = 2.0 V
1.1
2.0
LS (low-speed main)
mode
(MCSEL = 1)
fIH = 4 MHz Note 3,
TA = -40 to +85°C
Normal
operation
VDD = 3.0 V
0.72
1.30
VDD = 2.0 V
0.72
1.30
fIM = 4 MHz Note 7,
TA = -40 to +85°C
Normal
operation
VDD = 3.0 V
0.58
1.10
VDD = 2.0 V
0.58
1.10
Note 3,
mA
6.3
2.4
4.6
4.9
fIH = 3 MHz
TA = -40 to +85°C
Normal
operation
VDD = 3.0 V
1.2
1.8
VDD = 2.0 V
1.2
1.8
LP (low-power main)
fIH = 1 MHz Note 3,
TA = -40 to +85°C
Normal
operation
VDD = 3.0 V
290
480
VDD = 2.0 V
290
480
fIM = 1 MHz Note 5,
TA = -40 to +85°C
Normal
operation
VDD = 3.0 V
124
230
VDD = 2.0 V
124
230
fMX = 20 MHz Note 2,
TA = -40 to +85°C
Normal
operation
VDD = 3.0 V
fMX = 20 MHz Note 2,
TA = +85 to +105°C
Normal
operation
VDD = 3.0 V
fMX = 10 MHz Note 2,
TA = -40 to +85°C
Normal
operation
VDD = 3.0 V
fMX = 10 MHz Note 2,
TA = +85 to +105°C
Normal
operation
VDD = 3.0 V
fMX = 8 MHz Note 2,
TA = -40 to +85°C
Normal
operation
VDD = 3.0 V
fMX = 8 MHz Note 2,
TA = -40 to +85°C
Normal
operation
VDD = 2.0 V
fMX = 4 MHz Note 2,
TA = -40 to +85°C
Normal
operation
VDD = 3.0 V
fMX = 4 MHz Note 2,
TA = -40 to +85°C
Normal
operation
VDD = 2.0 V
fMX = 1 MHz Note 2,
TA = -40 to +85°C
Normal
operation
VDD = 3.0 V
fMX = 1 MHz Note 2,
TA = -40 to +85°C
Normal
operation
VDD = 2.0 V
HS (high-speed main)
mode
LS (low-speed main)
mode
(MCSEL = 0)
LS (low-speed main)
mode
(MCSEL = 1)
LP (low-power main)
mode
(MCSEL = 1)
mA
6.7
LV (low-voltage main)
mode
mode Note 5
(MCSEL = 1)
Unit
Square wave input
2.7
5.3
Resonator connection
2.8
5.5
Square wave input
5.7
Resonator connection
5.8
Square wave input
1.8
3.1
Resonator connection
1.9
3.2
Square wave input
3.4
Resonator connection
3.5
Square wave input
0.9
1.9
Resonator connection
1.0
2.0
Square wave input
0.9
1.9
Resonator connection
1.0
2.0
Square wave input
0.6
1.1
Resonator connection
0.6
1.2
Square wave input
0.6
1.1
Resonator connection
0.6
1.2
Square wave input
100
190
Resonator connection
136
250
Square wave input
100
190
Resonator connection
136
250
mA
mA
mA
A
mA
mA
mA
A
(Notes and Remarks are listed on the next page.)
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 24 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Supply current
Symbol
IDD1
Note 1
Operating
mode
Subsystem clock
operation
fSX = 32.768 kHz,
MIN.
Normal operation
TA = -40°C Note 4
fSX = 32.768 kHz,
Normal operation
TA = +25°C Note 4
fSX = 32.768 kHz,
Normal operation
TA = +50°C Note 4
fSX = 32.768 kHz,
Normal operation
TA = +70°C Note 4
fSX = 32.768 kHz,
Normal operation
TA = +85°C Note 4
fSX = 32.768 kHz,
Normal operation
TA = +105°C Note 4
TYP.
MAX.
Unit
Square wave input
3.2
6.1
A
Resonator connection
3.3
6.1
Square wave input
3.4
6.1
Resonator connection
3.6
6.1
Square wave input
3.5
6.7
Resonator connection
3.7
6.7
Square wave input
3.7
7.5
Resonator connection
3.9
7.5
Square wave input
4.0
8.9
Resonator connection
4.2
8.9
Square wave input
4.5
21.0
Resonator connection
4.7
21.1
Normal operation
1.8
5.9
fIL = 15 kHz, TA = +25°C Note 6
Normal operation
1.9
5.9
Note 6
Normal operation
2.3
8.7
Normal operation
3.0
20.9
fIL = 15 kHz, TA = -40°C
fIL = 15 kHz, TA = +85°C
Note 6
fIL = 15 kHz, TA = +105°C Note 6
Note 1.
(2/4)
Conditions
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or
VSS. The MAX values include the peripheral operating current. However, these values do not include the current flowing
into the A/D converter, operational amplifier, comparator, LVD circuit, I/O ports, and on-chip pull-up/pull-down resistors,
and the current flowing during data flash rewrite.
Note 2.
When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, low-speed on-chip oscillator clock,
and sub clock are stopped.
Note 3.
When the high-speed system clock, middle-speed on-chip oscillator clock, low-speed on-chip oscillator clock, and sub
clock are stopped.
Note 4.
When the high-speed system clock, high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, low-speed
on-chip oscillator clock, and sub clock are stopped. When ultra-low-power consumption oscillation is set (AMPHS1,
AMPHS0) = (1, 0). The values do not include the current flowing into the real-time clock 2, 12-bit interval timer, and
watchdog timer.
Note 5.
When the high-speed system clock, high-speed on-chip oscillator clock, sub clock, and low-speed on-chip oscillator clock
are stopped. The MAX values include the current of peripheral operation except BGO operation, and the STOP leakage
current. However, the real-time clock 2, watchdog timer, LVD circuit, and A/D converter are stopped.
Note 6.
When the high-speed system clock, high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, and sub
clock are stopped.
Note 7.
When the high-speed system clock, high-speed on-chip oscillator clock, low-speed on-chip oscillator clock, and sub clock
are stopped.
Remark 1. fMX:
Remark 2. fIH:
High-speed on-chip oscillator clock frequency (24 MHz max.)
High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 3. fIM:
Middle-speed on-chip oscillator clock frequency (4 MHz max.)
Remark 4. fIL:
Low-speed on-chip oscillator clock frequency
Remark 5. fSX:
Sub clock frequency (XT1 clock oscillation frequency)
Remark 6. fSUB:
Subsystem clock frequency (XT1 clock oscillation frequency or low-speed on-chip oscillator clock frequency)
Remark 7. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 25 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Symbol
Supply current
IDD2
Note 1
Note 2
(3/4)
Conditions
HALT
mode
HS (high-speed main) mode
MIN.
fIH = 24 MHz Note 4,
TA = -40 to +85°C
VDD = 3.0 V
fIH = 24 MHz Note 4,
TA = +85 to +105°C
VDD = 3.0 V
fIH = 16 MHz Note 4,
VDD = 3.0 V
TYP.
MAX.
Unit
0.37
1.83
mA
2.85
0.36
1.38
TA = -40 to +85°C
fIH = 16 MHz Note 4,
TA = +85 to +105°C
VDD = 3.0 V
2.08
LS (low-speed main) mode
(MCSEL = 0)
fIH = 8 MHz Note 4,
TA = -40 to +85°C
VDD = 3.0 V
250
710
VDD = 2.0 V
250
710
LS (low-speed main) mode
fIH = 4 MHz Note 4,
TA = -40 to +85°C
VDD = 3.0 V
204
400
VDD = 2.0 V
204
400
fIM = 4 MHz Note 7,
VDD = 3.0 V
40
250
TA = -40 to +85°C
VDD = 2.0 V
40
250
fIH = 3 MHz Note 4,
VDD = 3.0 V
425
800
TA = -40 to +85°C
VDD = 2.0 V
425
800
fIH = 1 MHz Note 4,
TA = -40 to +85°C
VDD = 3.0 V
192
400
VDD = 2.0 V
192
400
fIM = 1 MHz Note 7,
VDD = 3.0 V
27
100
TA = -40 to +85°C
VDD = 2.0 V
27
100
fMX = 20 MHz Note 3,
VDD = 3.0 V Square wave input
0.20
1.55
0.40
1.74
(MCSEL = 1)
LV (low-voltage main) mode
LP (low-power main) mode
(MCSEL = 1)
HS (high-speed main) mode
TA = -40 to +85°C
fMX = 20 MHz Note 3,
Resonator connection
VDD = 3.0 V Square wave input
TA = +85 to +105°C
fMX = 10 MHz Note 3,
TA = -40 to +85°C
fMX = 10 MHz Note 3,
Resonator connection
LS (low-speed main) mode
(MCSEL = 0)
fMX = 8 MHz Note 3,
TA = -40 to +85°C
fMX = 8 MHz Note 3,
Resonator connection
VDD = 2.0 V Square wave input
TA = -40 to +85°C
LS (low-speed main) mode
fMX = 4 MHz Note 3,
(MCSEL = 1)
TA = -40 to +85°C
fMX = 1 MHz Note 3,
Resonator connection
VDD = 3.0 V Square wave input
Resonator connection
VDD = 2.0 V Square wave input
TA = -40 to +85°C
LP (low-power main) mode
(MCSEL = 1)
fMX = 4 MHz Note 3,
Subsystem clock operation
Resonator connection
VDD = 3.0 V Square wave input
TA = -40 to +85°C
fMX = 1 MHz Note 3,
0.86
0.30
0.93
Resonator connection
VDD = 2.0 V Square wave input
TA = -40 to +85°C
Resonator connection
A
mA
1.28
Resonator connection
VDD = 3.0 V Square wave input
A
2.57
0.15
VDD = 3.0 V Square wave input
TA = +85 to +105°C
A
2.45
Resonator connection
VDD = 3.0 V Square wave input
A
1.36
68
550
120
590
68
550
120
590
23
128
65
200
23
128
65
200
10
64
48
150
10
64
48
150
fSX = 32.768 kHz,
Square wave input
0.24
0.57
TA = -40°C Note 5
Resonator connection
0.42
0.76
fSX = 32.768 kHz,
Square wave input
0.30
0.57
TA = +25°C Note 5
Resonator connection
0.54
0.76
fSX = 32.768 kHz,
Square wave input
0.35
1.17
TA = +50°C Note 5
Resonator connection
0.60
1.36
fSX = 32.768 kHz,
Square wave input
0.42
1.97
TA = +70°C Note 5
Resonator connection
0.70
2.16
fSX = 32.768 kHz,
Square wave input
0.80
3.37
TA = +85°C Note 5
Resonator connection
0.95
3.56
fSX = 32.768 kHz,
Square wave input
1.80
17.10
TA = +105°C Note 5
Resonator connection
2.20
17.50
fIL = 15 kHz, TA = -40°C Note 6
0.40
1.22
fIL = 15 kHz, TA = +25°C Note 6
0.47
1.22
fIL = 15 kHz, TA = +85°C Note 6
0.80
3.30
fIL = 15 kHz, TA = +105°C Note 6
2.00
17.30
A
A
A
A
A
(Notes and Remarks are listed on the next page.)
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 26 of 101
RL78/I1D
Note 1.
2. ELECTRICAL SPECIFICATIONS
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or
VSS. The MAX values include the peripheral operating current. However, these values do not include the current flowing
into the A/D converter, operational amplifier, comparator, LVD circuit, I/O ports, and on-chip pull-up/pull-down resistors,
and the current flowing during data flash rewrite.
Note 2.
When the HALT instruction is executed in the flash memory.
Note 3.
When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, low-speed on-chip oscillator clock,
and sub clock are stopped.
Note 4.
When the high-speed system clock, middle-speed on-chip oscillator clock, low-speed on-chip oscillator clock, and sub
clock are stopped.
Note 5.
When the high-speed system clock, middle-speed on-chip oscillator clock, low-speed on-chip oscillator clock, and highspeed on-chip oscillator clock are stopped. When RTCLPC = 1 and ultra-low-power consumption oscillation is set
(AMPHS1, AMPHS0) = (1, 0). The values include the current flowing into the real-time clock 2. However, the values do
not include the current flowing into the 12-bit interval timer and watchdog timer.
Note 6.
When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, high-speed system clock, and sub
clock are stopped.
Note 7.
When the high-speed system clock, high-speed on-chip oscillator clock, low-speed on-chip oscillator clock, and sub clock
are stopped.
Remark 1. fMX:
Remark 2. fIH:
High-speed on-chip oscillator clock frequency (24 MHz max.)
High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 3. fIM:
Middle-speed on-chip oscillator clock frequency (4 MHz max.)
Remark 4. fIL:
Low-speed on-chip oscillator clock frequency
Remark 5. fSX:
Sub clock frequency (XT1 clock oscillation frequency)
Remark 6. fSUB:
Subsystem clock frequency (XT1 clock oscillation frequency or low-speed on-chip oscillator clock frequency)
Remark 7. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 27 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
TYP.
MAX.
Unit
Supply current
IDD3
STOP mode
TA = -40°C
0.16
0.51
A
Note 1
Note 2
Note 3
TA = +25°C
0.22
0.51
TA = +50°C
0.27
1.10
TA = +70°C
0.37
1.90
TA = +85°C
0.60
3.30
TA = +105°C
1.50
17.00
Note 1.
Symbol
Conditions
(4/4)
MIN.
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or
VSS. The MAX values include the peripheral operating current. However, these values do not include the current flowing
into the A/D converter, operational amplifier, comparator, LVD circuit, I/O ports, and on-chip pull-up/pull-down resistors,
and the current flowing during data flash rewrite.
Note 2.
The values do not include the current flowing into the real-time clock 2, 12-bit interval timer, and watchdog timer.
Note 3.
For the setting of the current values when operating the subsystem clock in STOP mode, see the current values when
operating the subsystem clock in HALT mode.
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 28 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
Peripheral Functions (Common to all products)
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
Unit
0.02
A
fSX = 32.768 kHz
0.04
A
8-bit counter mode 2-channel operation
0.12
A
16-bit counter mode operation
0.10
A
IRTC Notes 1, 2, 3
12-bit interval timer operating current
ITMKA Notes 1, 2, 4
8-bit interval timer operating current
ITMT Notes 1, 9
fSX = 32.768 kHz
fMAIN stopped (per unit)
Watchdog timer operating current
IWDT Notes 1, 2, 5
fIL = 15 kHz
A/D converter operating current
IADC Notes 6, 10
During maximum-speed
conversion
AVREF(+) current
IAVREF Note 11
AVREFP = 3.0 V, ADREFP1 = 0, ADREFP0 = 1
Internal reference voltage (1.45 V)
current
IADREF Notes 1, 12
Temperature sensor operating current
ITMPS Note 1
Comparator operating current
ICMP
AVDD = 3.6 V,
Regulator output voltage
= 2.1 V
AVDD = 3.6 V,
Regulator output voltage
= 1.8 V
Low-power consumption
mode
High-speed mode
AVDD = 3.0 V
420
720
A
14.0
25.0
A
85.0
A
85.0
A
Comparator high-speed mode
Window mode
12.5
A
Comparator low-speed mode
Window mode
3.0
Comparator high-speed mode
Standard mode
6.5
Comparator low-speed mode
Standard mode
1.7
Comparator high-speed mode
Window mode
8.0
Comparator low-speed mode
Window mode
2.2
Comparator high-speed mode
Standard mode
4.0
Comparator low-speed mode
Standard mode
1.3
One operational amplifier unit operates Note 14
2.5
Note 14
4.0
4.5
8.0
Three operational amplifier units operate Note 14
6.5
11.0
Four operational amplifier units operate Note 14
8.5
14.0
One operational amplifier unit operates Note 14
140
220
Two operational amplifier units operate Note 14
280
410
420
600
560
780
Two operational amplifier units operate
Note 14
Four operational amplifier units operate Note 14
ILVD Notes 1, 7
A
0.22
Three operational amplifier units operate
LVD operating current
MAX.
fSX = 32.768 kHz
RTC2 operating current
IAMP Notes 10, 13
TYP.
A
IFIL Note 1
Operational amplifier operating current
MIN.
0.20
Low-speed on-chip oscillator operating
current
Notes 8, 10
(1/2)
0.10
A
A
(Notes and Remarks are listed on the next page.)
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 29 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
Note 1.
Current flowing to VDD.
Note 2.
When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, and high-speed system clock are
stopped.
Note 3.
Current flowing only to the real-time clock 2 (RTC2) (excluding the operating current of the low-speed on-chip oscillator
and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2,
and IRTC, when the real-time clock 2 operates in operation mode or HALT mode. When the low-speed on-chip oscillator is
selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of the real-time clock 2.
Note 4.
Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and
the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT,
when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is
selected, IFIL should be added.
Note 5.
Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator).
The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer is in
operation.
Note 6.
Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and
IADC when the A/D converter operates in an operation mode or the HALT mode.
Note 7.
Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and
ILVD when the LVD circuit is in operation.
Note 8.
Current flowing only to the comparator circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2, or
IDD3 and ICMP when the comparator circuit is in operation.
Note 9.
Current flowing only to the 8-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the
XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT,
when the 8-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is
selected, IFIL should be added.
Note 10.
Current flowing to AVDD.
Note 11.
Current flowing into AVREFP.
Note 12.
Current consumed by generating the internal reference voltage (1.45 V).
Note 13.
Current flowing only to the operational amplifier. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2,
or IDD3 and IAMP when the operational amplifier is operating in operating mode, HALT mode, or STOP mode.
Note 14.
The values include the operating current of the operational amplifier reference current circuit.
Remark 1. fIL:
Low-speed on-chip oscillator clock frequency
Remark 2. fSUB:
Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 3. fCLK:
CPU/peripheral hardware clock frequency
Remark 4. Temperature condition of the TYP. value is TA = 25°C
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RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
(2/2)
TYP.
MAX.
Unit
Self-programming operating current IFSP Notes 1, 3
2.0
12.20
mA
BGO current
IBGO Notes 1, 2
2.0
12.20
mA
SNOOZE operating current
ISNOZ Note 1
0.50
0.60
mA
0.60
0.75
mA
420
720
A
0.50
1.10
mA
0.60
1.34
mA
420
720
A
TA = -40 to +85°C
0.70
0.84
mA
TA = +85 to +105°C
0.70
1.54
mA
ADC operation
The mode is performed
AVREFP = VDD = 3.0 V
Note 5
TA = -40 to +85°C
MIN.
The A/D conversion
operations are performed
Note 1
The A/D conversion
operations are performed
Note 4
ADC operation
The mode is performed
AVREFP = VDD = 3.0 V
Note 5
TA = +85 to +105°C
The A/D conversion
operations are performed
Note 1
The A/D conversion
operations are performed
Note 4
CSI/UART operation
Note 1.
Current flowing to VDD.
Note 2.
Current flowing during programming of the data flash.
Note 3.
Current flowing during self-programming.
Note 4.
Current flowing to AVDD.
Note 5.
For shift time to the SNOOZE mode, see 23.3.3 SNOOZE mode in the RL78/I1D User’s Manual.
Remark 1. fIL:
Low-speed on-chip oscillator clock frequency
Remark 2. fSUB:
Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 3. fCLK:
CPU/peripheral hardware clock frequency
Remark 4. Temperature condition of the TYP. value is TA = 25°C
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RL78/I1D
2.4
2. ELECTRICAL SPECIFICATIONS
AC Characteristics
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Items
Instruction cycle
Symbol
TCY
(minimum instruction
(1/2)
MAX.
Unit
Main system clock HS (high-speed main)
Conditions
2.7 V ≤ VDD ≤ 3.6 V
0.04167
1
s
(fMAIN) operation
2.4 V ≤ VDD < 2.7 V
0.0625
1
s
LS (low-speed main)
1.8 V ≤ VDD ≤ 3.6 V
0.125
1
s
mode
PMMC. MCSEL = 0
0.25
1
execution time)
mode
MIN.
1.8 V ≤ VDD ≤ 3.6 V
TYP.
PMMC. MCSEL = 1
LP (low-power main)
1.8 V ≤ VDD ≤ 3.6 V
s
1
mode
LV (low-voltage main)
1.8 V ≤ VDD ≤ 3.6 V
0.25
1
mode
1.6 V ≤ VDD < 1.8 V
0.34
1
Subsystem clock
fSX
1.8 V ≤ VDD ≤ 3.6 V
28.5
(fSUB) operation
fIL
1.8 V ≤ VDD ≤ 3.6 V
In the self-
HS (high-speed main)
2.7 V ≤ VDD ≤ 3.6 V
programming
mode
LS (low-speed main)
s
31.3
s
0.04167
1
s
2.4 V ≤ VDD < 2.7 V
0.0625
1
s
1.8 V ≤ VDD ≤ 3.6 V
0.125
1
s
1.8 V ≤ VDD ≤ 3.6 V
0.25
1
s
2.7 V ≤ VDD ≤ 3.6 V
1.0
20.0
MHz
2.4 V ≤ VDD < 2.7 V
1.0
16.0
MHz
1.8 V ≤ VDD < 2.4 V
1
8
MHz
1.6 V ≤ VDD < 1.8 V
1
4
MHz
32
35
kHz
mode
30.5
66.7
mode
LV (low-voltage main)
mode
External system
fEX
clock frequency
fEXS
External system
tEXH,
2.7 V ≤ VDD ≤ 3.6 V
24
ns
clock input high-level
tEXL
2.4 V ≤ VDD < 2.7 V
30
ns
1.8 V ≤ VDD < 2.4 V
60
ns
1.6 V ≤ VDD < 1.8 V
120
ns
13.7
s
1/fMCK +
ns
width, low-level width
tEXHS,
tEXLS
TI00 to TI03 input
tTIH, tTIL
high-level width,
10
low-level width
Remark
fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of timer mode register mn (TMRmn). m: Unit number (m = 0), n: Channel
number (n = 0 to 3))
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RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Items
TO00 to TO03 output frequency
Symbol
fTO
Conditions
HS (high-speed main) mode
LS (low-speed main) mode
PCLBUZ0, PCLBUZ1 output
fPCL
tINTH,
low-level width
tINTL
Key interrupt input low-level width
tKR
RESET low-level width
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
tRSL
MAX.
Unit
2.7 V ≤ VDD ≤ 3.6 V
MIN.
TYP.
8
MHz
2.4 V ≤ VDD < 2.7 V
4
1.8 V ≤ VDD ≤ 3.6 V
4
LP (low-power main) mode
1.8 V ≤ VDD ≤ 3.6 V
0.5
LV (low-voltage main) mode
1.6 V ≤ VDD ≤ 3.6 V
2
HS (high-speed main) mode
2.7 V ≤ VDD ≤ 3.6 V
8
2.4 V ≤ VDD < 2.7 V
4
frequency
Interrupt input high-level width,
(2/2)
LS (low-speed main) mode
1.8 V ≤ VDD ≤ 3.6 V
4
LP (low-power main) mode
1.8 V ≤ VDD ≤ 3.6 V
1
LV (low-voltage main) mode
1.8 V ≤ VDD ≤ 3.6 V
4
1.6 V ≤ VDD < 1.8 V
2
MHz
INTP0 to INTP6
1.6 V ≤ VDD ≤ 3.6 V
1
s
KR0 to KR3
1.8 V ≤ VDD ≤ 3.6 V
250
ns
1.6 V ≤ VDD < 1.8 V
1
s
10
s
Page 33 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
AC Timing Test Points
VIH/VOH
VIH/VOH
Test points
VIL/VOL
VIL/VOL
External System Clock Timing
1/fEX
1/fEXS
tEXL
tEXLS
tEXH
tEXHS
EXCLK/EXCLKS
TI/TO Timing
tTIL
tTIH
TI00 to TI03
1/fTO
TO00 to TO03
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RL78/I1D
2. ELECTRICAL SPECIFICATIONS
Interrupt Request Input Timing
tINTL
tINTH
INTP0 to INTP6
Key Interrupt Input Timing
tKR
KR0 to KR3
RESET Input Timing
tRSL
RESET
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RL78/I1D
2.5
2. ELECTRICAL SPECIFICATIONS
Peripheral Functions Characteristics
AC Timing Test Points
VIH/VOH
VIL/VOL
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Test points
VIH/VOH
VIL/VOL
Page 36 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
2.5.1
Serial array unit
(1) During communication at same potential (UART mode)
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Mode
MIN.
Transfer rate
Note 1
MAX.
2.4 V ≤ VDD ≤ 3.6 V
LS (low-speed main)
Mode
MIN.
MAX.
LP (Low-power main)
mode
MIN.
MAX.
Unit
LV (low-voltage main)
Mode
MIN.
MAX.
fMCK/6
fMCK/6
fMCK/6
fMCK/6
bps
4.0
1.3
0.1
0.6
Mbps
—
fMCK/6
fMCK/6
fMCK/6
bps
—
1.3
0.1
0.6
Mbps
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 2
1.8 V ≤ VDD ≤ 3.6 V
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 2
1.7 V ≤ VDD ≤ 3.6 V
Theoretical value of the
maximum transfer rate
—
—
—
fMCK/6
bps
—
—
—
0.6
Mbps
—
—
—
fMCK/6
bps
—
—
—
0.6
Mbps
fMCK = fCLK Note 2
1.6 V ≤ VDD ≤ 3.6 V
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 2
Note 1.
Note 2.
Transfer rate in the SNOOZE mode is 4800 bps only.
The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode:
24 MHz (2.7 V ≤ VDD ≤ 3.6 V)
LS (low-speed main) mode:
8 MHz (1.8 V ≤ VDD ≤ 3.6 V)
LP (low-power main) mode:
1 MHz (1.8 V ≤ VDD ≤ 3.6 V)
LV (low-voltage main) mode:
4 MHz (1.6 V ≤ VDD ≤ 3.6 V)
16 MHz (2.4 V ≤ VDD ≤ 3.6 V)
Caution
Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
HS (high-speed main) Mode
Parameter
Symbol
Conditions
Unit
MIN.
Transfer rate Note 1
2.4 V ≤ VDD ≤ 3.6 V
Theoretical value of the maximum
MAX.
fMCK/12
bps
2.0
Mbps
transfer rate
fMCK = fCLK Note 2
Note 1.
Note 2.
Transfer rate in the SNOOZE mode is 4800 bps only.
The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode:
24 MHz (2.7 V ≤ VDD ≤ 3.6 V)
16 MHz (2.4 V ≤ VDD ≤ 3.6 V)
Caution
Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
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RL78/I1D
2. ELECTRICAL SPECIFICATIONS
UART mode connection diagram (during communication at same potential)
TxDq
Rx
RL78 microcontroller
User’s device
RxDq
Tx
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Remark 1. q: UART number (q = 0), g: PIM and POM number (g = 5)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01))
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RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only)
(TA = -40 to +85°C, 2.7 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Mode
MIN.
tKCY1 ≥fCLK/2
MAX.
LS (low-speed main)
Mode
MIN.
MAX.
LP (Low-power main)
mode
MIN.
MAX.
LV (low-voltage main)
Mode
MIN.
Unit
MAX.
SCKp cycle time
tKCY1
83.3
250
2000
500
ns
SCKp high-/low-level width
tKL1
tKCY1/2
- 10
tKCY1/2
- 50
tKCY1/2
- 50
tKCY1/2
- 50
ns
SIp setup time (to SCKp↑)
tSIK1
33
110
110
110
ns
tKSI1
10
10
10
10
ns
Note 1
SIp hold time (from SCKp↑)
Note 2
Delay time from SCKp↓ to
tKSO1
SOp output Note 3
C = 20 pF
10
20
20
20
ns
Note 4
Note 4.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
C is the load capacitance of the SCKp and SOp output lines.
Caution
Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using
Note 1.
Note 2.
Note 3.
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 5)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
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RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
SCKp cycle
time
SCKp high-/
low-level
width
SIp setup
time
(to SCKp↑)
Symbol
tKCY1
tKH1,
tKL1
tSIK1
Note 1
SIp hold
time (from
SCKp↑)
tKSI1
Note 2
Delay time
from SCKp↓
to SOp
output
tKSO1
Conditions
tKCY1 ≥ fCLK/4
HS (high-speed
main) Mode
LS (low-speed
main) Mode
MIN.
MIN.
2.7 V ≤ VDD ≤ 3.6 V
167
MAX.
LP (Low-power
main) mode
MAX.
MIN.
500
4000
LV (low-voltage
main) Mode
MAX.
MIN.
ns
ns
2.4 V ≤ VDD ≤ 3.6 V
250
—
1.7 V ≤ VDD ≤ 3.6 V
—
—
—
1.6 V ≤ VDD ≤ 3.6 V
—
—
—
2.7 V ≤ VDD ≤ 3.6 V
tKCY1/2 18
tKCY1/2 50
tKCY1/2 50
tKCY1/2 50
2.4 V ≤ VDD ≤ 3.6 V
tKCY1/2 38
1.8 V ≤ VDD ≤ 3.6 V
—
1.7 V ≤ VDD ≤ 3.6 V
—
—
—
tKCY1/2 100
1.6 V ≤ VDD ≤ 3.6 V
—
—
—
2.7 V ≤ VDD ≤ 3.6 V
58
110
110
110
2.4 V ≤ VDD ≤ 3.6 V
75
1.8 V ≤ VDD ≤ 3.6 V
—
220
1.7 V ≤ VDD ≤ 3.6 V
—
—
—
—
—
—
19
19
—
—
2.4 V ≤ VDD ≤ 3.6 V
19
1.8 V ≤ VDD ≤ 3.6 V
—
1.6 V ≤ VDD ≤ 3.6 V
—
C = 30 pF
2.4 V ≤ VDD ≤ 3.6 V
33.4
Note 4
1.8 V ≤ VDD ≤ 3.6 V
—
1.6 V ≤ VDD ≤ 3.6 V
—
Note 3
MAX.
1000
1.8 V ≤ VDD ≤ 3.6 V
1.6 V ≤ VDD ≤ 3.6 V
ns
19
33.4
33.4
—
—
Unit
ns
33.4
ns
Note 4.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
C is the load capacitance of the SCKp and SOp output lines.
Caution
Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using
Note 1.
Note 2.
Note 3.
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 5)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01))
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RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = +85 to +105°C, 2.7 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
HS (high-speed main) Mode
Parameter
Symbol
Conditions
Unit
MIN.
SCKp cycle time
tKCY1
SCKp high-/low-level width
tKH1, tKL1
tSIK1
SIp setup time (to SCKp↑) Note 1
2.7 V ≤ VDD ≤ 3.6 V
250
ns
2.4 V ≤ VDD ≤ 3.6 V
500
ns
2.7 V ≤ VDD ≤ 3.6 V
tKCY1/2 - 36
ns
2.4 V ≤ VDD ≤ 3.6 V
tKCY1/2 - 76
ns
2.7 V ≤ VDD ≤ 3.6 V
66
ns
2.4 V ≤ VDD ≤ 3.6 V
133
ns
tKSI1
SIp hold time (from SCKp↑) Note 2
Delay time from SCKp↓ to SOp output
tKCY1 ≥ fCLK/4
Note 3
tKSO1
MAX.
38
C = 30 pF
Note 4
ns
50
ns
Note 4.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
C is the load capacitance of the SCKp and SOp output lines.
Caution
Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using
Note 1.
Note 2.
Note 3.
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 5)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01))
R01DS0244EJ0230 Rev. 2.30
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RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Mode
MIN.
SCKp cycle time
tKCY2
2.7 V ≤ VDD ≤ 3.6 V
MAX.
(1/2)
LS (low-speed main)
Mode
MIN.
MAX.
—
LP (Low-power
main) mode
LV (low-voltage
main) Mode
MIN.
MAX.
MIN.
MAX.
—
—
—
—
fMCK > 16 MHz
8/fMCK
—
fMCK ≤ 16 MHz
6/fMCK
6/fMCK
6/fMCK
6/fMCK
2.4 V ≤ VDD ≤ 3.6 V
6/fMCK
and 500
6/fMCK
6/fMCK
6/fMCK
1.8 V ≤ VDD ≤ 3.6 V
—
6/fMCK
6/fMCK
6/fMCK
1.7 V ≤ VDD ≤ 3.6 V
—
—
—
Unit
ns
Note 5
SCKp high-/
low-level width
tKH2,
tKL2
SIp setup time
(to SCKp↑)
tSIK2
Note 1
SIp hold time
(from SCKp↑)
tKSI2
Note 2
Delay time from
SCKp↓ to SOp
tKSO2
1.6 V ≤ VDD ≤ 3.6 V
—
—
—
2.7 V ≤ VDD ≤ 3.6 V
tKCY2/2 8
tKCY2/2 8
tKCY2/2 8
tKCY2/2 8
2.4 V ≤ VDD ≤ 3.6 V
tKCY2/2
- 18
tKCY2/2
- 18
tKCY2/2
- 18
tKCY2/2
- 18
1.8 V ≤ VDD ≤ 3.6 V
—
1.7 V ≤ VDD ≤ 3.6 V
—
—
—
1.6 V ≤ VDD ≤ 3.6 V
—
—
—
tKCY2/2
- 66
2.7 V ≤ VDD ≤ 3.6 V
1/fMCK
+ 20
1/fMCK
+ 30
1/fMCK
+ 30
1/fMCK
+ 30
2.4 V ≤ VDD ≤ 3.6 V
1/fMCK
+ 30
1.8 V ≤ VDD ≤ 3.6 V
—
1.7 V ≤ VDD ≤ 3.6 V
—
—
—
1.6 V ≤ VDD ≤ 3.6 V
—
—
—
1/fMCK
+ 40
2.4 V ≤ VDD ≤ 3.6 V
1/fMCK
+ 31
1/fMCK
+ 31
1/fMCK
+ 31
1/fMCK
+ 31
1.8 V ≤ VDD ≤ 3.6 V
—
1.7 V ≤ VDD ≤ 3.6 V
—
—
—
1.6 V ≤ VDD ≤ 3.6 V
—
—
—
1/fMCK
+ 250
C = 30 pF Note 4
output Note 3
2.7 V ≤ VDD ≤ 3.6 V
2/fMCK
+ 44
2.4 V ≤ VDD ≤ 3.6 V
2/fMCK
+ 75
1.8 V ≤ VDD ≤ 3.6 V
—
1.7 V ≤ VDD ≤ 3.6 V
1.6 V ≤ VDD ≤ 3.6 V
ns
ns
ns
2/fMCK
+ 110
2/fMCK
+ 110
2/fMCK
+ 110
—
—
—
—
—
—
2/fMCK
+ 220
ns
Note 5.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
C is the load capacitance of the SOp output lines.
The maximum transfer rate when using the SNOOZE mode is 1 Mbps.
Caution
Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin by using port input
Note 1.
Note 2.
Note 3.
Note 4.
mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 5)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01))
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2. ELECTRICAL SPECIFICATIONS
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Symbol
HS (high-speed main)
Mode
Conditions
MIN.
SSI00 setup time
tSSIK
DAPmn = 0
DAPmn = 1
SSI00 hold time
tKSSI
DAPmn = 0
DAPmn = 1
Caution
MAX.
(2/2)
LS (low-speed main)
Mode
MIN.
MAX.
LP (Low-power main)
mode
MIN.
MAX.
LV (low-voltage main)
Mode
MIN.
2.7 V ≤ VDD ≤ 3.6 V
120
120
120
120
2.4 V ≤ VDD < 2.7 V
200
200
200
200
1.8 V ≤ VDD < 2.4 V
—
1.6 V ≤ VDD < 1.8 V
—
—
—
400
2.7 V ≤ VDD ≤ 3.6 V
1/fMCK
+ 120
1/fMCK
+ 120
1/fMCK
+ 120
1/fMCK
+ 120
2.4 V ≤ VDD < 2.7 V
1/fMCK
+ 200
1/fMCK
+ 200
1/fMCK
+ 200
1/fMCK
+ 200
1.8 V ≤ VDD < 2.4 V
—
1.6 V ≤ VDD < 1.8 V
—
—
—
1/fMCK
+ 400
2.7 V ≤ VDD ≤ 3.6 V
1/fMCK
+ 120
1/fMCK
+ 120
1/fMCK
+ 120
1/fMCK
+ 120
2.4 V ≤ VDD < 2.7 V
1/fMCK
+ 200
1/fMCK
+ 200
1/fMCK
+ 200
1/fMCK
+ 200
—
—
1/fMCK
+ 400
1.8 V ≤ VDD < 2.4 V
—
1.6 V ≤ VDD < 1.8 V
—
2.7 V ≤ VDD ≤ 3.6 V
120
120
120
120
2.4 V ≤ VDD < 2.7 V
200
200
200
200
1.8 V ≤ VDD < 2.4 V
—
1.6 V ≤ VDD < 1.8 V
—
—
—
400
Unit
MAX.
ns
ns
ns
ns
Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark
p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 5)
CSI mode connection diagram (during communication at same potential)
SCKp
RL78 microcontroller
SIp
SOp
SCK
SO
User's device
SI
CSI mode connection diagram (during communication at same potential)
(Slave Transmission of slave select input function (CSI00))
SCK00
SI00
RL78 microcontroller
SCK
SO
User's device
SO00
SI
SSI00
SSO
Remark 1. p: CSI number (p = 00, 01)
Remark 2. m: Unit number, n: Channel number (mn = 00, 01)
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2. ELECTRICAL SPECIFICATIONS
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(1/2)
HS (high-speed main) Mode
Parameter
Symbol
Conditions
Unit
MIN.
SCKp cycle time Note 5
tKCY2
2.7 V ≤ VDD < 3.6 V
MAX.
fMCK > 16 MHz
16/fMCK
ns
fMCK ≤ 16 MHz
12/fMCK
ns
2.4 V ≤ VDD < 2.7 V
12/fMCK and 1000
ns
SCKp high-/low-level width
tKH2, tKL2
2.7 V ≤ VDD ≤ 3.6 V
tKCY2/2 - 16
ns
2.4 V ≤ VDD < 2.7 V
tKCY2/2 - 36
ns
SIp setup time (to SCKp↑) Note 1
tSIK2
2.7 V ≤ VDD ≤ 3.6 V
1/fMCK + 40
ns
1/fMCK + 60
ns
SIp hold time (from SCKp↑) Note 2
tKSI2
1/fMCK + 62
ns
2.4 V ≤ VDD < 2.7 V
Delay time from SCKp↓ to SOp output Note 3 tKSO2
C = 30 pF Note 4
2.7 V ≤ VDD ≤ 3.6 V
2/fMCK + 66
ns
2.4 V ≤ VDD < 2.7 V
2/fMCK + 113
ns
Note 5.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
C is the load capacitance of the SOp output lines.
The maximum transfer rate when using the SNOOZE mode is 1 Mbps.
Caution
Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin by using port input
Note 1.
Note 2.
Note 3.
Note 4.
mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 5)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01))
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RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(2/2)
HS (high-speed main) Mode
Parameter
Symbol
Conditions
Unit
MIN.
tSSIK
SSI00 setup time
DAPmn = 0
DAPmn = 1
tKSSI
SSI00 hold time
DAPmn = 0
DAPmn = 1
Caution
MAX.
2.7 V ≤ VDD ≤ 3.6 V
240
ns
2.4 V ≤ VDD < 2.7 V
400
ns
2.7 V ≤ VDD ≤ 3.6 V
1/fMCK + 240
ns
2.4 V ≤ VDD < 2.7 V
1/fMCK + 400
ns
2.7 V ≤ VDD ≤ 3.6 V
1/fMCK + 240
ns
2.4 V ≤ VDD < 2.7 V
1/fMCK + 400
ns
2.7 V ≤ VDD ≤ 3.6 V
240
ns
2.4 V ≤ VDD < 2.7 V
400
ns
Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark
p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 5)
CSI mode connection diagram (during communication at same potential)
SCKp
RL78 microcontroller
SIp
SOp
SCK
SO
User's device
SI
CSI mode connection diagram (during communication at same potential)
(Slave Transmission of slave select input function (CSI00))
SCK00
SI00
RL78 microcontroller
SCK
SO
User's device
SO00
SI
SSI00
SSO
Remark 1. p: CSI number (p = 00, 01)
Remark 2. m: Unit number, n: Channel number (mn = 00, 01)
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RL78/I1D
2. ELECTRICAL SPECIFICATIONS
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1, 2
tKH1, 2
tKL1, 2
SCKp
tKSI1, 2
tSIK1, 2
SIp
Input data
tKSO1, 2
Output data
SOp
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1, 2
tKL1, 2
tKH1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Output data
Remark 1. p: CSI number (p = 00, 01)
Remark 2. m: Unit number, n: Channel number (mn = 00, 01)
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RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(5) During communication at same potential (simplified I2C mode)
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Mode
MIN.
SCLr clock frequency
fSCL
2.7 V ≤ VDD ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
MAX.
LS (low-speed main)
Mode
MIN.
tLOW
when SCLr = “L”
MIN.
MAX.
400
250
400
Note 1
Note 1
1.8 V ≤ VDD < 2.7 V,
—
1.7 V ≤ VDD < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
—
1.6 V ≤ VDD < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
—
Unit
MAX.
Note 1
—
1.8 V ≤ VDD ≤ 3.6 V,
MIN.
1000
1.8 V ≤ VDD ≤ 3.6 V,
Cb = 100 pF, Rb = 3 kΩ
2.7 V ≤ VDD ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
LV (low-voltage
main) Mode
Note 1
Cb = 100 pF, Rb = 5 kΩ
Hold time
MAX.
LP (Low-power
main) mode
300
250
300
Note 1
Note 1
Note 1
—
—
kHz
250
Note 1
475
—
—
1150
1150
1150
—
1550
1550
1550
—
—
—
1850
—
—
—
475
1150
1150
1150
—
1550
1550
1550
—
—
—
1850
—
—
—
1/fMCK
1/fMCK
1/fMCK
1/fMCK
+ 85
+ 145
+ 145
+ 145
Note 2
Note 2
Note 2
Note 2
1/fMCK
+ 230
1/fMCK
+ 230
1/fMCK
+ 230
ns
—
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1.7 V ≤ VDD < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
1.6 V ≤ VDD < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
Hold time
when SCLr = “H”
tHIGH
2.7 V ≤ VDD ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD ≤ 3.6 V,
ns
—
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1.7 V ≤ VDD < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
1.6 V ≤ VDD < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
Data setup time
tSU: DAT
(reception)
2.7 V ≤ VDD ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD ≤ 3.6 V,
ns
—
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ VDD < 2.7 V,
—
Cb = 100 pF, Rb = 5 kΩ
Data hold time
(transmission)
tHD: DAT
Note 2
Note 2
Note 2
1.7 V ≤ VDD < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
—
—
—
1/fMCK
1.6 V ≤ VDD < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
—
—
—
2.7 V ≤ VDD ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
0
305
1.8 V ≤ VDD ≤ 3.6 V,
—
—
—
—
—
—
—
—
—
—
—
—
+ 290
0
305
0
355
Note 2
305
0
305
355
355
—
—
405
—
—
ns
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1.7 V ≤ VDD < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
1.6 V ≤ VDD < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
(Notes and Caution are listed on the next page.)
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RL78/I1D
Note 1.
Note 2.
Caution
2. ELECTRICAL SPECIFICATIONS
The value must also be equal to or less than fMCK/4.
Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Select the normal input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the
normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h
(POMh).
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RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(5) During communication at same potential (simplified I2C mode)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
HS (high-speed main) Mode
Parameter
Symbol
Unit
Conditions
MIN.
SCLr clock frequency
Hold time when SCLr = “L”
Hold time when SCLr = “H”
Data setup time (reception)
Data hold time (transmission)
Note 1.
Note 2.
Caution
fSCL
tLOW
tHIGH
tSU: DAT
tHD: DAT
MAX.
2.7 V ≤ VDD ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
400 Note 1
kHz
2.4 V ≤ VDD ≤ 3.6 V,
Cb = 100 pF, Rb = 3 kΩ
100 Note 1
kHz
2.7 V ≤ VDD ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
1200
ns
2.4 V ≤ VDD ≤ 3.6 V,
Cb = 100 pF, Rb = 3 kΩ
4600
ns
2.7 V ≤ VDD ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
1200
ns
2.4 V ≤ VDD ≤ 3.6 V,
Cb = 100 pF, Rb = 3 kΩ
4600
ns
2.7 V ≤ VDD ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK + 220 Note 2
ns
2.4 V ≤ VDD ≤ 3.6 V,
Cb = 100 pF, Rb = 3 kΩ
1/fMCK + 580 Note 2
ns
2.7 V ≤ VDD ≤ 3.6 V,
Cb = 50 pF, Rb = 2.7 kΩ
0
770
ns
2.4 V ≤ VDD ≤ 3.6 V,
Cb = 100 pF, Rb = 3 kΩ
0
1420
ns
The value must also be equal to or less than fMCK/4.
Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Select the normal input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the
normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h
(POMh).
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RL78/I1D
2. ELECTRICAL SPECIFICATIONS
Simplified I2C mode connection diagram (during communication at same potential)
VDD
Rb
SDAr
SDA
RL78 microcontroller
User’s device
SCLr
SCL
Simplified I2C mode serial transfer timing (during communication at same potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD: DAT
tSU: DAT
Remark 1. Rb[Ω]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance
Remark 2. r: IIC number (r = 00, 01), g: PIM number (g = 5), h: POM number (h = 5)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0),
n: Channel number (n = 0, 1), mn = 00, 01)
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RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(6) Communication at different potential (1.8 V, 2.5 V) (UART mode) (dedicated baud rate generator output)
(TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) Mode
MIN.
Transfer
rate
reception
2.7 V ≤ VDD ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V
Notes 1, 2
MAX.
(1/2)
LS (low-speed
main) Mode
LP (Low-power
main) mode
LV (low-voltage
main) Mode
MIN.
MIN.
MIN.
MAX.
MAX.
Unit
MAX.
fMCK/6
fMCK/6
fMCK/6
fMCK/6
Note 1
Note 1
Note 1
Note 1
4.0
1.3
0.1
0.6
Mbps
bps
Theoretical value of
the maximum transfer
rate
bps
fMCK = fCLK Note 3
1.8 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
fMCK/6
fMCK/6
fMCK/6
fMCK/6
Notes 1, 2
Notes 1, 2
Notes 1, 2
Notes 1, 2
4.0
1.3
0.1
0.6
Theoretical value of
the maximum transfer
rate
Mbps
fMCK = fCLK Note 3
Note 1.
Note 2.
Note 3.
Caution
Transfer rate in the SNOOZE mode is 4,800 bps only.
Use it with VDD ≥ Vb.
The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 3.6 V)
16 MHz (2.4 V ≤ VDD ≤ 3.6 V)
LS (low-speed main) mode:
8 MHz (1.8 V ≤ VDD ≤ 3.6 V)
LP (low-power main) mode:
1 MHz (1.8 V ≤ VDD ≤ 3.6 V)
LV (low-voltage main) mode:
4 MHz (1.6 V ≤ VDD ≤ 3.6 V)
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq
pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the
DC characteristics with TTL input buffer selected.
Remark 1. Vb[V]: Communication line voltage
Remark 2. q: UART number (q = 0), g: PIM and POM number (g = 5)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01)
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2. ELECTRICAL SPECIFICATIONS
(6) Communication at different potential (1.8 V, 2.5 V) (UART mode) (dedicated baud rate generator output)
(TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Transfer
Symbol
Conditions
Transmission
rate Note 2
HS (high-speed
main) Mode
LS (low-speed
main) Mode
LP (Low-power
main) mode
LV (low-voltage
main) Mode
MIN.
MIN.
MIN.
MIN.
2.7 V ≤ VDD ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V
MAX.
Note 1
Theoretical value of the
maximum transfer rate
Cb = 50 pF, Rb = 2.7 kΩ,
Vb = 2.3 V
1.8 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Theoretical value of the
maximum transfer rate
Cb = 50 pF, Rb = 5.5 kΩ,
Vb = 1.6 V
Note 1.
(2/2)
MAX.
MAX.
Note 1
Unit
MAX.
Note 1
Note 1
bps
Mbps
1.2
1.2
1.2
1.2
Note 2
Note 2
Note 2
Note 2
Notes 3, 4
Notes 3, 4
Notes 3, 4
Notes 3, 4
bps
Mbps
0.43
0.43
0.43
0.43
Note 5
Note 5
Note 5
Note 5
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ VDD ≤ 3.6 V and 2.3 V ≤ Vb ≤ 2.7 V
1
[bps]
Maximum transfer rate =
{-Cb Rb In (1 -
2.0
)} 3
Vb
1
Transfer rate 2
- {-Cb Rb In (1 -
2.0
)}
Vb
100 [%]
Baud rate error (theoretical value) =
(
1
Transfer rate
) Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
Note 2.
Note 3.
Note 4.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
Use it with VDD ≥ Vb.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate.
Expression for calculating the transfer rate when 1.8 V ≤ VDD < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V
1
[bps]
Maximum transfer rate =
1.5
{-Cb Rb In (1 )} 3
Vb
1
Transfer rate 2
- {-Cb Rb In (1 -
1.5
)}
Vb
100 [%]
Baud rate error (theoretical value) =
(
1
Transfer rate
) Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
Note 5.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer.
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq
pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the
DC characteristics with TTL input buffer selected.
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2. ELECTRICAL SPECIFICATIONS
(6) Communication at different potential (1.8 V, 2.5 V) (UART mode) (dedicated baud rate generator output)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(1/2)
HS (high-speed main) Mode
Parameter
Symbol
Conditions
Unit
MIN.
Transfer rate Notes 1, 2
Reception
2.7 V ≤ VDD ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V
MAX.
fMCK/12 Note 1
bps
2.0
Mbps
fMCK/12 Notes 1, 2
bps
0.66
Mbps
Theoretical value of the maximum transfer rate
fMCK = fCLK Note 3
2.4 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Theoretical value of the maximum transfer rate
fMCK = fCLK Note 3
Note 3.
Transfer rate in the SNOOZE mode is 4,800 bps only.
Use it with VDD ≥ Vb.
The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 3.6 V)
16 MHz (2.4 V ≤ VDD ≤ 3.6 V)
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq
Note 1.
Note 2.
pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the
DC characteristics with TTL input buffer selected.
Remark 1. Vb[V]: Communication line voltage
Remark 2. q: UART number (q = 0), g: PIM and POM numbers (g = 5)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01)
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RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(6) Communication at different potential (1.8 V, 2.5 V) (UART mode) (dedicated baud rate generator output)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(2/2)
HS (high-speed main) Mode
Parameter
Symbol
Conditions
Unit
MIN.
Transfer rate Note 2
Transmission 2.7 V ≤ VDD ≤ 3.6 V,
MAX.
Note 1
bps
1.2 Note 2
Mbps
Notes 3, 4
bps
2.3 V ≤ Vb ≤ 2.7 V
Theoretical value of the maximum transfer rate
Cb = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V
2.4 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Theoretical value of the maximum transfer rate
Cb = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V
Note 1.
0.43
Note 5
Mbps
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ VDD ≤ 3.6 V and 2.3 V ≤ Vb ≤ 2.7 V
1
[bps]
Maximum transfer rate =
2.0
{-Cb Rb In (1 )} 3
Vb
1
Transfer rate 2
- {-Cb Rb In (1 -
2.0
)}
Vb
100 [%]
Baud rate error (theoretical value) =
(
1
Transfer rate
) Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
Note 2.
Note 3.
Note 4.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
Use it with VDD ≥ Vb.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate.
Expression for calculating the transfer rate when 2.4 V ≤ VDD < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V
1
Maximum transfer rate =
[bps]
1.5
)} 3
{-Cb Rb In (1 Vb
1
Transfer rate 2
- {-Cb Rb In (1 -
1.5
)}
Vb
100 [%]
Baud rate error (theoretical value) =
(
1
Transfer rate
) Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
Note 5.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer.
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq
pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the
DC characteristics with TTL input buffer selected.
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2. ELECTRICAL SPECIFICATIONS
UART mode connection diagram (during communication at different potential)
Vb
Rb
TxDq
Rx
RL78 microcontroller
User’s device
RxDq
Tx
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Remark 1. Rb[Ω]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance,
Vb[V]: Communication line voltage
Remark 2. q: UART number (q = 0), g: PIM and POM number (g = 5)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01))
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2. ELECTRICAL SPECIFICATIONS
(7) Communication at different potential (2.5 V) (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only)
(TA = -40 to +85°C, 2.7 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
SCKp cycle time
Sym
bol
tKCY1
Conditions
tKCY1 ≥ fCLK/2
2.7 V ≤ VDD ≤ 3.6 V,
HS (high-speed
main) Mode
LS (low-speed
main) Mode
LP (Low-power
main) mode
MIN.
MIN.
MIN.
MAX.
MAX.
MAX.
LV (low-voltage
main) Mode
MIN.
Unit
MAX.
300
1500
1500
1500
ns
tKCY1/2
- 120
tKCY1/2
- 120
tKCY1/2
- 120
tKCY1/2
- 120
ns
tKCY1/2
- 10
tKCY1/2
- 50
tKCY1/2
- 50
tKCY1/2
- 50
ns
121
479
479
479
ns
10
10
10
10
ns
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SCKp high-level
width
tKH1
SCKp low-level
width
tKL1
SIp setup time (to
tSIK1
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
tKSI1
tKSO1
output Note 2
130
130
130
130
ns
tSIK1
2.7 V ≤ VDD ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
33
110
110
110
ns
tKSI1
2.7 V ≤ VDD ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
10
10
10
10
ns
tKSO1
2.7 V ≤ VDD ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SCKp↓) Note 2
Delay time from
SCKp↑ to SOp
2.7 V ≤ VDD ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SCKp↓) Note 2
SIp hold time (from
2.7 V ≤ VDD ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
output Note 1
SIp setup time (to
2.7 V ≤ VDD ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SCKp↑) Note 1
Delay time from
SCKp↓ to SOp
2.7 V ≤ VDD ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 1.4 kΩ
SCKp↑) Note 1
SIp hold time (from
2.7 V ≤ VDD ≤ 3.6 V,
10
10
10
10
ns
Note 2.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin
Note 1.
and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and
VIL, see the DC characteristics with TTL input buffer selected.
Remark 1. Rb[ι]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g = 5)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
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2. ELECTRICAL SPECIFICATIONS
(8) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
SCKp cycle
time
Sym
bol
tKCY1
Conditions
tKCY1 ≥ fCLK/4
2.7V ≤ VDD ≤ 3.6 V,
(1/2)
HS (high-speed
main) Mode
LS (low-speed
main) Mode
LP (Low-power
main) mode
MIN.
MIN.
MIN.
MAX.
MAX.
MAX.
LV (low-voltage
main) Mode
MIN.
Unit
MAX.
500
1150
1150
1150
ns
1150
1150
1150
1150
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
tKCY1/2
- 170
tKCY1/2
- 170
tKCY1/2
- 170
tKCY1/2
- 170
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note,
Cb = 30 pF, Rb = 5.5 kΩ
tKCY1/2
- 458
tKCY1/2
- 458
tKCY1/2
- 458
tKCY1/2
- 458
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
tKCY1/2
- 18
tKCY1/2
- 50
tKCY1/2
- 50
tKCY1/2
- 50
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note, tKCY1/2
- 50
Cb = 30 pF, Rb = 5.5 kΩ
tKCY1/2
- 50
tKCY1/2
- 50
tKCY1/2
- 50
ns
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note,
Cb = 30 pF, Rb = 5.5 kΩ
SCKp highlevel width
tKH1
SCKp low-level
width
tKL1
Note
Use it with VDD ≥ Vb.
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin
and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and
VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the page after the next page.)
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
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RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(8) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Sym
bol
Conditions
(2/2)
HS (high-speed
main) Mode
LS (low-speed
main) Mode
LP (Low-power
main) mode
MIN.
MIN.
MIN.
MAX.
MAX.
MAX.
LV (low-voltage
main) Mode
MIN.
Unit
MAX.
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
177
479
479
479
ns
Note 1
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
479
479
479
479
ns
SIp hold time tKSI1
(from SCKp↑)
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
19
19
19
19
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
19
19
19
19
ns
SIp setup
time
(to SCKp↑)
tSIK1
Note 1
Delay time
from SCKp↓
to SOp
tKSO1
output Note 1
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
195
195
195
195
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
483
483
483
483
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
44
110
110
110
ns
Note 2
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
110
110
110
110
ns
SIp hold time tKSI1
(from SCKp↓)
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
19
19
19
19
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
19
19
19
19
ns
SIp setup
time
(to SCKp↓)
tSIK1
Note 2
Delay time
from SCKp↑
to SOp
output Note 2
tKSO1
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
25
25
25
25
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
25
25
25
25
ns
Note 3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Use it with VDD ≥ Vb.
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin
Note 1.
Note 2.
and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and
VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
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RL78/I1D
2. ELECTRICAL SPECIFICATIONS
CSI mode connection diagram (during communication at different potential)
Vb
Vb
Rb
SCKp
RL78 microcontroller
Rb
SCK
SIp
SO
SOp
SI
User’s device
Remark 1. Rb[Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM numbers (g = 5)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01))
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2. ELECTRICAL SPECIFICATIONS
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
tKSI1
Input data
SIp
tKSO1
SOp
Output data
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1
tKH1
tKL1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
Remark
Output data
p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM numbers (g = 5)
R01DS0244EJ0230 Rev. 2.30
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2. ELECTRICAL SPECIFICATIONS
(8) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = +85 to 105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(1/2)
HS (high-speed main) Mode
Parameter
Symbol
Conditions
Unit
MIN.
SCKp cycle time
SCKp high-level width
SCKp low-level width
Caution
tKCY1
tKH1
tKL1
tKCY1 ≥ fCLK/4
MAX.
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1000
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
2300
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
tKCY1/2 - 340
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
tKCY1/2 - 916
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
tKCY1/2 - 36
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
tKCY1/2 - 100
ns
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin
and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and
VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the page after the next page.)
R01DS0244EJ0230 Rev. 2.30
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RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(8) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = +85 to 105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
(2/2)
HS (high-speed main)
Mode
MIN.
SIp setup time (to SCKp↑) Note 1
SIp hold time (from SCKp↑) Note 1
Delay time from SCKp↓ to SOp output Note 1
SIp setup time (to SCKp↓) Note 2
SIp hold time (from SCKp↓) Note 2
Delay time from SCKp↑ to SOp output Note 2
tSIK1
tKSI1
tKSO1
tSIK1
tKSI1
tKSO1
Unit
MAX.
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
354
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
958
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
38
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
38
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
390
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
966
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
88
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
220
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
38
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
38
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
50
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 kΩ
50
ns
Note 3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Use it with VDD ≥ Vb.
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin
Note 1.
Note 2.
and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and
VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 62 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
CSI mode connection diagram (during communication at different potential)
SCKp
RL78 microcontroller
SCK
SIp
SO
SOp
SI
User’s device
Remark 1. Rb[Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM numbers (g = 5)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01))
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 63 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
tKSI1
Input data
SIp
tKSO1
SOp
Output data
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1
tKH1
tKL1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
Remark
Output data
p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM numbers (g = 5)
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 64 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(9) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (slave mode, SCKp... external clock input)
(TA = -40 to 85°C, 1.8 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
SCKp cycle
Symb
ol
tKCY2
time Note 1
Conditions
2.7 V ≤ VDD ≤ 3.6 V, 2.3
V ≤ Vb ≤ 2.7 V
1.8 V ≤ VDD < 3.3 V, 1.6
V ≤ Vb ≤ 2.0 V
Note 2
SCKp high-/
low-level
width
tKH2,
tKL2
SIp setup
time (to
SCKp↑)
tSIK2
Note 3
SIp hold
time (from
SCKp↑)
20 MHz < fMCK ≤ 24 MHz
HS (high-speed
main) Mode
LS (low-speed
main) Mode
LP (Low-power
main) mode
LV (low-voltage
main) Mode
MIN.
MIN.
MIN.
MIN.
MAX.
MAX.
MAX.
Unit
MAX.
16/fMCK
—
—
—
ns
16 MHz < fMCK ≤ 20 MHz
14/fMCK
—
—
—
ns
8 MHz < fMCK ≤ 16 MHz
12/fMCK
—
—
—
ns
4 MHz < fMCK ≤ 8 MHz
8/fMCK
16/fMCK
—
—
ns
fMCK ≤ 4 MHz
6/fMCK
10/fMCK
10/fMCK
10/fMCK
ns
20 MHz < fMCK ≤ 24 MHz
36/fMCK
—
—
—
ns
16 MHz < fMCK ≤ 20 MHz
32/fMCK
—
—
—
ns
8 MHz < fMCK ≤ 16 MHz
26/fMCK
—
—
—
ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK
16/fMCK
—
—
ns
fMCK ≤ 4 MHz
10/fMCK
10/fMCK
10/fMCK
10/fMCK
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V
tKCY2/2
- 18
tKCY2/2
- 50
tKCY2/2
- 50
tKCY2/2 50
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2
tKCY2/2
- 50
tKCY2/2
- 50
tKCY2/2
- 50
tKCY2/2 50
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V
1/fMCK
+ 20
1/fMCK
+ 30
1/fMCK
+ 30
1/fMCK +
30
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2
1/fMCK
+ 30
1/fMCK
+ 30
1/fMCK
+ 30
1/fMCK +
30
ns
1/fMCK
+ 31
1/fMCK
+ 31
1/fMCK
+ 31
1/fMCK +
31
ns
tKSI2
Note 4
Delay time
from SCKp↓
to SOp
output Note 5
tKSO2
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2/fMCK
2/fMCK
+ 573
2/fMCK
+ 573
2/fMCK
+ 573
ns
+ 214
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 kΩ
2/fMCK
+ 573
2/fMCK
+ 573
2/fMCK
+ 573
2/fMCK
+ 573
ns
(Notes and Caution are listed on the next page. Remarks are listed on the page after the next page.)
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 65 of 101
RL78/I1D
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Caution
2. ELECTRICAL SPECIFICATIONS
Transfer rate in the SNOOZE mode: MAX. 1 Mbps
Use it with VDD ≥ Vb.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance) mode for
the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL,
see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 66 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
CSI mode connection diagram (during communication at different potential)
Vb
Rb
SCKp
RL78 microcontroller
SCK
SIp
SO
SOp
SI
User’s device
Remark 1. Rb[Ω]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM numbers (g = 5)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01))
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 67 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY2
tKL2
tKH2
SCKp
tSIK2
tKSI2
Input data
SIp
tKSO2
SOp
Output data
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY2
tKH2
tKL2
SCKp
tSIK2
SIp
tKSI2
Input data
tKSO2
SOp
Remark
Output data
p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM numbers (g = 5)
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 68 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(9) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (slave mode, SCKp... external clock input)
(TA = +85 to 105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
HS (high-speed main) Mode
Parameter
Symbol
Conditions
Unit
MIN.
tKCY2
SCKp cycle time Note 1
SCKp high-/low-level width
tKH2, tKL2
2.7 V ≤ VDD ≤ 3.6 V,
2.3 V ≤ Vb ≤ 2.7 V
20 MHz < fMCK ≤ 24 MHz
32/fMCK
ns
16 MHz < fMCK ≤ 20 MHz
28/fMCK
ns
8 MHz < fMCK ≤ 16 MHz
24/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK
ns
fMCK ≤ 4 MHz
12/fMCK
ns
2.4 V ≤ VDD < 3.3 V,
20 MHz < fMCK ≤ 24 MHz
72/fMCK
ns
1.6 V ≤ Vb ≤ 2.0 V Note 2
16 MHz < fMCK ≤ 20 MHz
64/fMCK
ns
8 MHz < fMCK ≤ 16 MHz
52/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
32/fMCK
ns
fMCK ≤ 4 MHz
20/fMCK
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
SIp setup time (to SCKp↑) Note 3
tSIK2
SIp hold time (from SCKp↑)
Delay time from SCKp↓ to SOp output Note 5
Note 2
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Note 4
Note 2
tKSI2
tKSO2
MAX.
tKCY2/2 - 36
ns
tKCY2/2 - 100
ns
1/fMCK + 40
ns
1/fMCK + 60
ns
1/fMCK + 62
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V
Cb = 30 pF, Rb = 2.7 kΩ
2/fMCK + 428
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2
Cb = 30 pF, Rb = 5.5 kΩ
2/fMCK + 1146
ns
(Notes and Caution are listed on the next page. Remarks are listed on the page after the next page.)
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 69 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
Note 1.
Transfer rate in the SNOOZE mode: MAX. 1 Mbps
Note 2.
Use it with VDD ≥ Vb.
Note 3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 5.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution
Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance) mode for
the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL,
see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 70 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
CSI mode connection diagram (during communication at different potential)
Vb
Rb
SCKp
RL78 microcontroller
SCK
SIp
SO
SOp
SI
User’s device
Remark 1. Rb[Ω]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM numbers (g = 5)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01))
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 71 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY2
tKL2
tKH2
SCKp
tSIK2
tKSI2
Input data
SIp
tKSO2
SOp
Output data
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY2
tKH2
tKL2
SCKp
tSIK2
SIp
tKSI2
Input data
tKSO2
SOp
Remark
Output data
p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM numbers (g = 5)
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 72 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(10) Communication at different potential (1.8 V, 2.5 V) (simplified I2C mode)
(TA = -40 to 85°C, 1.8 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
SCLr clock
frequency
Sym
bol
fSCL
Hold time
when SCLr
= “L”
tLOW
Hold time
tHIGH
Conditions
HS (high-speed
main) Mode
LS (low-speed
main) Mode
LP (Low-power
main) mode
LV (low-voltage
main) Mode
MIN.
MIN.
MIN.
MIN.
MAX.
MAX.
MAX.
Unit
MAX.
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
1000
300
250
300
Note 1
Note 1
Note 1
Note 1
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
400
300
250
300
Note 1
Note 1
Note 1
Note 1
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
300
300
250
300
Note 1
Note 1
Note 1
Note 1
kHz
kHz
kHz
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
475
1550
1550
1550
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1150
1550
1550
1550
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
1550
1550
1550
1550
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
200
610
610
610
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
600
610
610
610
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
610
610
610
610
ns
1/fMCK
1/fMCK
+ 190
1/fMCK
+ 190
1/fMCK
+ 190
ns
+ 135
Note 3
Note 2
Note 3
Note 3
1/fMCK
+ 190
1/fMCK
+ 190
1/fMCK
+ 190
1/fMCK
+ 190
Note 3
Note 3
Note 3
Note 3
1/fMCK
+ 190
1/fMCK
+ 190
1/fMCK
+ 190
1/fMCK
+ 190
Note 3
Note 3
Note 3
Note 3
Cb = 50 pF, Rb = 2.7 kΩ
when SCLr
= “H”
Data setup
time
(reception)
tSU:
DAT
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
Data hold
time (transmission)
tHD:
DAT
ns
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
0
305
0
305
0
305
0
305
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
0
355
0
355
0
355
0
355
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
0
405
0
405
0
405
0
405
ns
Note 1.
The value must also be equal to or less than fMCK/4.
Note 2.
Use it with VDD ≥ Vb.
Note 3.
Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution
Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the N-ch
open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port
output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 73 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
Simplified I2C mode connection diagram (during communication at different potential)
Vb
Vb
Rb
Rb
SDAr
SDA
RL78 microcontroller
User’s device
SCLr
SCL
Simplified I2C mode serial transfer timing (during communication at different potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD: DAT
tSU: DAT
Remark 1. Rb[Ω]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance,
Vb[V]: Communication line voltage
Remark 2. r: IIC number (r = 00, 01), g: PIM, POM number (g = 5)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0),
n: Channel number (n = 0, 1), mn = 00, 01)
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 74 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(10) Communication at different potential (1.8 V, 2.5 V) (simplified I2C mode)
(TA = +85 to 105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
HS (high-speed main) Mode
Parameter
Symbol
Conditions
Unit
MIN.
SCLr clock frequency
Hold time when SCLr = “L”
Hold time when SCLr = “H”
Data setup time (reception)
Data hold time (transmission)
fSCL
tLOW
tHIGH
tSU:DAT
tHD:DAT
MAX.
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
400 Note 1
kHz
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
100 Note 1
kHz
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
100 Note 1
kHz
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
1200
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
4600
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
4650
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
500
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
2400
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
1830
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK + 340 Note 3
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1/fMCK + 760 Note 3
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
1/fMCK + 570 Note 3
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
0
770
ns
2.7 V ≤ VDD ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
0
1420
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
0
1215
ns
Note 1.
The value must also be equal to or less than fMCK/4.
Note 2.
Use it with VDD ≥ Vb.
Note 3.
Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution
Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the N-ch
open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port
output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 75 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
Simplified I2C mode connection diagram (during communication at different potential)
Vb
Vb
Rb
Rb
SDAr
SDA
RL78 microcontroller
User’s device
SCLr
SCL
Simplified I2C mode serial transfer timing (during communication at different potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD: DAT
tSU: DAT
Remark 1. Rb[Ω]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance,
Vb[V]: Communication line voltage
Remark 2. r: IIC number (r = 00, 01), g: PIM and POM numbers (g = 5)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0),
n: Channel number (n = 0, 1), mn = 00, 01)
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 76 of 101
RL78/I1D
2.6
2. ELECTRICAL SPECIFICATIONS
Analog Characteristics
2.6.1
A/D converter characteristics
Classification of A/D converter characteristics
Reference Voltage
Input Channel
Reference voltage (+) = AVREFP Reference voltage (+) = AVDD
Reference voltage (-) = AVREFM Reference voltage (-) = AVSS
High-accuracy channel; ANI0 to ANI13
(input buffer power supply: AVDD)
Refer to 2.6.1 (1).
Refer to 2.6.1 (7).
Refer to 2.6.1 (2).
Refer to 2.6.1 (7).
Standard channel; ANI16 to ANI18
(input buffer power supply: VDD)
Refer to 2.6.1 (3).
Refer to 2.6.1 (8).
Refer to 2.6.1 (4).
Refer to 2.6.1 (9).
Internal reference voltage,
Temperature sensor output voltage
Refer to 2.6.1 (3).
Refer to 2.6.1 (8).
Refer to 2.6.1 (4).
Refer to 2.6.1 (9).
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Reference voltage (+) = Internal reference
voltage
Reference voltage (-) = AVSS
Refer to 2.6.1 (5).
Refer to 2.6.1 (10).
—
Page 77 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) =
AVREFM/ANI1 (ADREFM = 1), conversion target: ANI2 to ANI13
(TA = -40 to +85°C, 1.6 V ≤ AVREFP ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVREFP,
Reference voltage (-) = AVREFM = 0 V)
Parameter
Resolution
Symbol
Conditions
RES
MIN.
Overall error
Conversion time
AINL
tCONV
MAX.
Unit
bit
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
8
12
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
8
Note 1
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
Note 3
TYP.
10
8
Note 2
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±6.0
10-bit resolution
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±5.0
8-bit resolution
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±2.5
ADTYP = 0,
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
3.375
ADTYP = 0,
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
6.75
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
13.5
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
2.5625
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
5.125
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
10.25
LSB
s
10-bit resolution Note 1
ADTYP = 0,
8-bit resolution Note 2
ADTYP = 1,
8-bit resolution
Zero-scale error Note 3
Full-scale error Note 3
EZS
EFS
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±4.5
10-bit resolution
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±4.5
8-bit resolution
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±2.0
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±4.5
10-bit resolution
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±4.5
8-bit resolution
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±2.0
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±2.0
10-bit resolution
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±1.5
8-bit resolution
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±1.0
Differential linearity error DLE
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±1.5
Note 3
10-bit resolution
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±1.5
8-bit resolution
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±1.0
Integral linearity error
ILE
Note 3
Analog input voltage
VAIN
Note 1.
Cannot be used for lower 2 bit of ADCR register
Note 2.
Cannot be used for lower 4 bit of ADCR register
Note 3.
Excludes quantization error (±1/2 LSB).
Caution
Always use AVDD pin with the same potential as the VDD pin.
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
0
AVREFP
LSB
LSB
LSB
LSB
V
Page 78 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(2) When reference voltage (+) = AVDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (-) = AVSS (ADREFM =
0), conversion target: ANI0 to ANI13
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVDD,
Reference voltage (-) = AVSS = 0 V)
Parameter
Resolution
Symbol
Conditions
2.4 V ≤ AVDD ≤ 3.6 V
RES
1.8 V ≤ AVDD ≤ 3.6 V
MIN.
MAX.
Unit
8
12
bit
8
Note 1
1.6 V ≤ AVDD ≤ 3.6 V
Overall error
Note 3
Conversion time
AINL
tCONV
2.4 V ≤ AVDD ≤ 3.6 V
±7.5
1.8 V ≤ AVDD ≤ 3.6 V
±5.5
8-bit resolution
1.6 V ≤ AVDD ≤ 3.6 V
±3.0
ADTYP = 0,
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
ADTYP = 0,
1.8 V ≤ AVDD ≤ 3.6 V
1.6 V ≤ AVDD ≤ 3.6 V
8-bit resolution Note 2
ADTYP = 1,
8-bit resolution
Full-scale error Note 3
Integral linearity error
EFS
ILE
Note 3
8
10-bit resolution
ADTYP = 0,
EZS
10
Note 2
12-bit resolution
10-bit resolution Note 1
Zero-scale error Note 3
TYP.
s
3.375
6.75
13.5
2.4 V ≤ AVDD ≤ 3.6 V
2.5625
1.8 V ≤ AVDD ≤ 3.6 V
5.125
1.6 V ≤ AVDD ≤ 3.6 V
10.25
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±6.0
10-bit resolution
1.8 V ≤ AVDD ≤ 3.6 V
±5.0
8-bit resolution
1.6 V ≤ AVDD ≤ 3.6 V
±2.5
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±6.0
10-bit resolution
1.8 V ≤ AVDD ≤ 3.6 V
±5.0
8-bit resolution
1.6 V ≤ AVDD ≤ 3.6 V
±2.5
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±3.0
10-bit resolution
1.8 V ≤ AVDD ≤ 3.6 V
±2.0
8-bit resolution
1.6 V ≤ AVDD ≤ 3.6 V
±1.5
Differential linearity error DLE
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±2.0
Note 3
10-bit resolution
1.8 V ≤ AVDD ≤ 3.6 V
±2.0
8-bit resolution
1.6 V ≤ AVDD ≤ 3.6 V
±1.5
Analog input voltage
VAIN
ANI0 to ANI6
Note 1.
Cannot be used for lower 2 bit of ADCR register
Note 2.
Cannot be used for lower 4 bit of ADCR register
Note 3.
Excludes quantization error (±1/2 LSB).
Caution
Always use AVDD pin with the same potential as the VDD pin.
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
LSB
0
AVDD
LSB
LSB
LSB
LSB
V
Page 79 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(3) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) =
AVREFM/ANI1 (ADREFM = 1), conversion target: ANI16 to ANI18, internal reference voltage, temperature
sensor output voltage
(TA = -40 to +85°C, 1.6 V ≤ VDD ≤ 3.6 V, 1.6 V ≤ AVREFP ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V, AVSS = 0 V,
Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V)
Parameter
Resolution
Symbol
Conditions
RES
MAX.
Unit
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
MIN.
8
TYP.
12
bit
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
8
10 Note 1
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
Overall error Note 3
Conversion time
AINL
tCONV
8 Note 2
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±7.0
10-bit resolution
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±5.5
8-bit resolution
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
ADTYP = 0,
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
4.125
ADTYP = 0,
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
9.5
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
57.5
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
3.3125
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
7.875
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
54.25
LSB
±3.0
s
10-bit resolution Note 1
ADTYP = 0,
8-bit resolution Note 2
ADTYP = 1,
8-bit resolution
Zero-scale error
Note 3
EZS
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±5.0
10-bit resolution
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±5.0
8-bit resolution
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±2.5
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±5.0
10-bit resolution
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±5.0
8-bit resolution
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±2.5
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±3.0
10-bit resolution
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±2.0
8-bit resolution
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±1.5
Differential linearity error DLE
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±2.0
Note 3
10-bit resolution
1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±2.0
8-bit resolution
1.6 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
Full-scale error
Note 3
Integral linearity error
EFS
ILE
Note 3
Analog input voltage
VAIN
LSB
LSB
LSB
±1.5
0
Internal reference voltage (1.8 V ≤ VDD ≤ 3.6 V)
Temperature sensor output voltage (1.8 V ≤ VDD ≤ 3.6 V)
Note 1.
Cannot be used for lower 2 bits of ADCR register
Note 2.
Cannot be used for lower 4 bits of ADCR register
Note 3.
Excludes quantization error (±1/2 LSB).
Note 4.
Refer to 2.6.2 Temperature sensor, internal reference voltage output characteristics.
Caution
Always use AVDD pin with the same potential as the VDD pin.
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
LSB
AVREFP
V
VBGR Note 4
VTMP25 Note 4
Page 80 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(4) When reference voltage (+) = AVDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (-) = AVSS (ADREFM =
0), conversion target: ANI16 to ANI18, internal reference voltage, temperature sensor output voltage
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVDD, Reference
voltage (-) = AVSS = 0 V)
Parameter
Resolution
Symbol
Conditions
RES
MIN.
TYP.
Overall error
Conversion time
AINL
tCONV
Unit
bit
2.4 V ≤ AVDD ≤ 3.6 V
8
12
1.8 V ≤ AVDD ≤ 3.6 V
8
Note 1
10
1.6 V ≤ AVDD ≤ 3.6 V
Note 3
MAX.
8
Note 2
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±8.5
10-bit resolution
1.8 V ≤ AVDD ≤ 3.6 V
±6.0
8-bit resolution
1.6 V ≤ AVDD ≤ 3.6 V
±3.5
ADTYP = 0,
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
4.125
ADTYP = 0,
1.8 V ≤ AVDD ≤ 3.6 V
9.5
1.6 V ≤ AVDD ≤ 3.6 V
57.5
LSB
A
10-bit resolution Note 1
ADTYP = 0,
8-bit resolution Note 2
ADTYP = 1,
8-bit resolution
Zero-scale error Note 3
Full-scale error Note 3
Integral linearity error
EZS
EFS
ILE
Note 3
2.4 V ≤ AVDD ≤ 3.6 V
3.3125
1.8 V ≤ AVDD ≤ 3.6 V
7.875
1.6 V ≤ AVDD ≤ 3.6 V
54.25
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±8.0
10-bit resolution
1.8 V ≤ AVDD ≤ 3.6 V
±5.5
8-bit resolution
1.6 V ≤ AVDD ≤ 3.6 V
±3.0
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±8.0
10-bit resolution
1.8 V ≤ AVDD ≤ 3.6 V
±5.5
8-bit resolution
1.6 V ≤ AVDD ≤ 3.6 V
±3.0
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±3.5
10-bit resolution
1.8 V ≤ AVDD ≤ 3.6 V
±2.5
8-bit resolution
1.6 V ≤ AVDD ≤ 3.6 V
±1.5
Differential linearity error DLE
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±2.5
Note 3
10-bit resolution
1.8 V ≤ AVDD ≤ 3.6 V
±2.5
8-bit resolution
1.6 V ≤ AVDD ≤ 3.6 V
±2.0
Analog input voltage
VAIN
0
Internal reference voltage (1.8 V ≤ VDD ≤ 3.6 V)
Temperature sensor output voltage
(1.8 V ≤ VDD ≤ 3.6 V)
AVDD
LSB
LSB
LSB
V
VBGR Note 4
VTMP25 Note 4
Note 1.
Cannot be used for lower 2 bits of ADCR register
Note 2.
Cannot be used for lower 4 bits of ADCR register
Note 3.
Excludes quantization error (±1/2 LSB).
Note 4.
Refer to 2.6.2 Temperature sensor, internal reference voltage output characteristics.
Caution
Always use AVDD pin with the same potential as the VDD pin.
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
LSB
Page 81 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(5) When reference voltage (+) = Internal reference voltage (1.45 V) (ADREFP1 = 1, ADREFP0 = 0), reference
voltage (-) = AVSS (ADREFM = 0), conversion target: ANI0 to ANI13, ANI16 to ANI18
(TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = internal reference
voltage, Reference voltage (-) = AVSS = 0 V)
Parameter
Symbol
Resolution
Conditions
MIN.
TYP.
RES
Conversion time
MAX.
Unit
8
bit
s
tCONV
8-bit resolution
EZS
8-bit resolution
±4.0
LSB
Integral linearity error Note
ILE
8-bit resolution
±2.0
LSB
Differential linearity error Note
DLE
8-bit resolution
±2.5
LSB
Analog input voltage
VAIN
VBGR
V
Zero-scale error
Note
16
0
Note
Excludes quantization error (±1/2 LSB).
Caution
Always use AVDD pin with the same potential as the VDD pin.
(6) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1),
reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), conversion target: ANI2 to ANI13
(TA = +85 to +105°C, 2.4 V ≤ AVREFP ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVREFP,
Reference voltage (-) = AVREFM = 0 V)
Symbol
Conditions
Resolution
Parameter
RES
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
Overall error Note
AINL
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
Conversion time
tCONV
ADTYP = 0,
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
Zero-scale error Note
EZS
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±4.5
LSB
EFS
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±4.5
LSB
ILE
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±2.0
LSB
DLE
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±1.5
LSB
AVREFP
V
Full-scale error Note
Integral linearity error
Note
Differential linearity error
Note
Analog input voltage
VAIN
Note
Excludes quantization error (±1/2 LSB).
Caution
Always use AVDD pin with the same potential as the VDD pin.
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
MIN.
8
TYP.
MAX.
Unit
12
bit
±6.0
LSB
s
3.375
0
Page 82 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(7) When reference voltage (+) = AVDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (-) = AVSS (ADREFM =
0), conversion target: ANI0 to ANI13
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVDD,
Reference voltage (-) = AVSS = 0 V)
Parameter
Resolution
Symbol
Conditions
2.4 V ≤ AVDD ≤ 3.6 V
RES
MIN.
8
TYP.
MAX.
Unit
12
bit
±7.5
LSB
AINL
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
Conversion time
tCONV
ADTYP = 0,
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
Zero-scale error Note
EZS
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±6.0
LSB
Full-scale error Note
EFS
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±6.0
LSB
Integral linearity error Note
ILE
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±3.0
LSB
Differential linearity error Note
DLE
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±2.0
LSB
Analog input voltage
VAIN
AVDD
V
Overall error
Note
Note
Excludes quantization error (±1/2 LSB).
Caution
Always use AVDD pin with the same potential as the VDD pin.
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
s
3.375
0
Page 83 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(8) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) =
AVREFM/ANI1 (ADREFM = 1), conversion target ANI16 to ANI18, internal reference voltage, temperature
sensor output voltage
(TA = +85 to +105°C, 2.4 V ≤ AVREFP ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVREFP,
Reference voltage (-) = AVREFM = 0 V)
Parameter
Symbol
Conditions
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
MIN.
TYP.
MAX.
Unit
12
bit
±7.0
LSB
Resolution
RES
Overall error Note 1
AINL
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
Conversion time
tCONV
ADTYP = 0,
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
Zero-scale error Note 1
EZS
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±5.0
LSB
Full-scale error Note 1
EFS
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±5.0
LSB
Integral linearity error Note 1
ILE
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±3.0
LSB
Differential linearity error
DLE
12-bit resolution
2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V
±2.0
LSB
AVREFP
V
8
s
4.125
Note 1
Analog input voltage
0
VAIN
Internal reference voltage (2.4 V ≤ VDD ≤ 3.6 V)
Temperature sensor output voltage
(2.4 V ≤ VDD ≤ 3.6 V)
Note 1.
Excludes quantization error (±1/2 LSB).
Note 2.
Refer to 2.6.2 Temperature sensor, internal reference voltage output characteristics.
Caution
Always use AVDD pin with the same potential as the VDD pin.
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
VBGR Note 2
VTMP25 Note 2
Page 84 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(9) When reference voltage (+) = AVDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (-) = AVSS (ADREFM =
0), conversion target: ANI16 to ANI18, internal reference voltage, temperature sensor output voltage
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVDD, Reference
voltage (-) = AVSS = 0)
Parameter
Resolution
Symbol
Conditions
2.4 V ≤ AVDD ≤ 3.6 V
RES
MIN.
TYP.
8
MAX.
Unit
12
bit
±8.5
LSB
AINL
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
Conversion time
tCONV
ADTYP = 0,
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
Zero-scale error Note 1
EZS
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±8.0
LSB
Full-scale error Note 1
EFS
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±8.0
LSB
Integral linearity error Note 1
ILE
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±3.5
LSB
Differential linearity error
DLE
12-bit resolution
2.4 V ≤ AVDD ≤ 3.6 V
±2.5
LSB
AVDD
V
Overall error
Note 1
s
4.125
Note 1
Analog input voltage
0
VAIN
Internal reference voltage (2.4 V ≤ VDD ≤ 3.6 V)
Temperature sensor output voltage
(2.4 V ≤ VDD ≤ 3.6 V)
Note 1.
Excludes quantization error (±1/2 LSB).
Note 2.
Refer to 2.6.2 Temperature sensor, internal reference voltage output characteristics.
Caution
Always use AVDD pin with the same potential as the VDD pin.
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
VBGR Note 2
VTMP25 Note 2
Page 85 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(10) When reference voltage (+) = Internal reference voltage (1.45 V) (ADREFP1 = 1, ADREFP0 = 0), reference
voltage (-) = AVSS (ADREFM = 0), conversion target: ANI0 to ANI13, ANI16 to ANI18
(TA = +85 to +105°C, 2.4 V ≤ VDD, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = internal
reference voltage, Reference voltage (-) = AVSS = 0 V)
Parameter
Resolution
Symbol
Conditions
MIN.
TYP.
RES
Conversion time
MAX.
Unit
8
bit
s
tCONV
8-bit resolution
EZS
8-bit resolution
±4.0
LSB
Integral linearity error Note
ILE
8-bit resolution
±2.0
LSB
Differential linearity error Note
DLE
8-bit resolution
±2.5
LSB
Analog input voltage
VAIN
VBGR
V
Zero-scale error
Note
16.0
0
Note
Excludes quantization error (±1/2 LSB).
Caution
Always use AVDD pin with the same potential as the VDD pin.
2.6.2
Temperature sensor, internal reference voltage output characteristics
(TA = -40 to 85°C, 1.8 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(TA = +85 to 105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
1.38
1.45
Temperature sensor output voltage VTMPS25
Setting ADS register = 80H, TA = +25°C
Internal reference voltage
VBGR
Setting ADS register = 81H
Temperature coefficient
FVTMPS
Temperature sensor output voltage that
depends on the temperature
Operation stabilization wait time
tAMP
2.4 V ≤ VDD ≤ 3.6 V
5
1.8 V ≤ VDD < 2.4 V
10
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
MAX.
Unit
1.50
V
1.05
-3.6
V
mV/°C
s
Page 86 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
2.6.3
Comparator
(TA = -40 to +85°C, 1.6 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Input voltage range
Output delay
Operation stabilization
wait time
Note
Symbol
Conditions
Ivref0
IVREF0 pin
Ivref1
IVREF1 pin
Ivcmp
IVCMP0, IVCMP1 pins
td
AVDD = 3.0 V
Input slew rate > 50 mV/s
MIN.
TYP.
0
MAX.
Unit
VDD - 1.4 Note
V
VDD
V
VDD + 0.3
V
Comparator high-speed mode,
standard mode
1.2
s
Comparator high-speed mode,
window mode
2.0
s
1.4
Note
-0.3
Comparator low-speed mode,
standard mode
3.0
s
Comparator low-speed mode,
window mode
4
s
tCMP
100
s
In window mode, make sure that Vref1 - Vref0 ≥ 0.2 V.
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 87 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
2.6.4
Operational amplifier characteristics
(TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
MAX.
Unit
Vicm1
Low-power consumption mode
0.2
AVDD - 0.5
V
Vicm2
High-speed mode
0.3
AVDD - 0.6
V
Output voltage range
Vo1
Low-power consumption mode
0.1
AVDD - 0.1
V
Vo2
High-speed mode
0.1
AVDD - 0.1
V
Input offset voltage
Vioff
-10
10
mV
Open gain
Av
60
Common mode input range
Symbol
Gain-bandwidth (GB) product GBW1
Conditions
MIN.
Low-power consumption mode
TYP.
120
dB
0.04
MHz
1.7
MHz
GBW2
High-speed mode
Phase margin
PM
CL = 20 pF
50
deg
Gain margin
GM
CL = 20 pF
10
dB
Equivalent input noise
Vnoise1 f = 1 kHz
230
nV/√Hz
Vnoise2 f = 10 kHz
Low-power
consumption mode
200
nV/√Hz
Vnoise3 f = 1 kHz
High-speed mode
90
nV/√Hz
Vnoise4 f = 2 kHz
70
nV/√Hz
Power supply reduction ratio
PSRR
90
dB
Common mode signal
reduction ratio
CMRR
90
dB
Operation stabilization wait
time
Tstd1
CL = 20 pF
Only operational amplifier is
Low-power
consumption mode
650
s
Tstd2
activated Note
High-speed mode
13
s
Tstd3
CL = 20 pF
Operational amplifier and
reference current circuit are
activated simultaneously
Low-power
consumption mode
650
s
High-speed mode
13
s
Tstd4
Settling time
Tset1
CL = 20 pF
Tset2
Slew rate
Tslew1
CL = 20 pF
Tslew2
Load current
Load capacitance
Note
Low-power
consumption mode
750
s
High-speed mode
13
s
Low-power
consumption mode
0.02
V/s
High-speed mode
1.1
V/s
Iload1
Low-power consumption mode
-100
100
A
Iload2
High-speed mode
-100
100
A
20
pF
CL
When the operational amplifier reference current circuit is activated in advance.
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 88 of 101
RL78/I1D
2.6.5
2. ELECTRICAL SPECIFICATIONS
POR circuit characteristics
(TA = -40 to +105°C, VSS = AVSS = 0 V)
Parameter
Detection voltage
Minimum pulse width Note 2
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VPOR
The power supply voltage is rising.
TA = -40 to +85°C
1.47
1.51
1.55
V
TA = +85 to +105°C
1.45
1.51
1.57
V
VPDR
The power supply voltage is falling.
TA = -40 to +85°C
1.46
1.50
1.54
V
Note 1
TA = +85 to +105°C
1.44
1.50
1.56
V
TPW1
Other than
STOP/SUB HALT/SUB RUN
TA = +40 to +105°C
300
s
TPW2
STOP/SUB HALT/SUB RUN
TA = +40 to +105°C
300
s
Note 1.
However, when the operating voltage falls while the LVD is off, enter STOP mode, or enable the reset status using the
external reset pin before the voltage falls below the operating voltage range shown in 2.4 AC Characteristics.
Note 2.
Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a
POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main
system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register
(CSC).
TPW1
TPW2
VDD
VPOR
VPDR
0.7 V
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 89 of 101
RL78/I1D
2.6.6
2. ELECTRICAL SPECIFICATIONS
LVD circuit characteristics
(1) LVD Detection Voltage of Reset Mode and Interrupt Mode
(TA = -40 to +85°C, VPDR ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Detection voltage
Supply voltage level
Symbol
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VLVD8
VLVD9
VLVD10
VLVD11
VLVD12
VLVD13
Minimum pulse width
Conditions
The power supply voltage is rising.
MIN.
TYP.
MAX.
Unit
3.07
3.13
3.19
V
The power supply voltage is falling.
3.00
3.06
3.12
V
The power supply voltage is rising.
2.96
3.02
3.08
V
The power supply voltage is falling.
2.90
2.96
3.02
V
The power supply voltage is rising.
2.86
2.92
2.97
V
The power supply voltage is falling.
2.80
2.86
2.91
V
The power supply voltage is rising.
2.76
2.81
2.87
V
The power supply voltage is falling.
2.70
2.75
2.81
V
The power supply voltage is rising.
2.66
2.71
2.76
V
The power supply voltage is falling.
2.60
2.65
2.70
V
The power supply voltage is rising.
2.56
2.61
2.66
V
The power supply voltage is falling.
2.50
2.55
2.60
V
The power supply voltage is rising.
2.45
2.50
2.55
V
The power supply voltage is falling.
2.40
2.45
2.50
V
The power supply voltage is rising.
2.05
2.09
2.13
V
The power supply voltage is falling.
2.00
2.04
2.08
V
The power supply voltage is rising.
1.94
1.98
2.02
V
The power supply voltage is falling.
1.90
1.94
1.98
V
The power supply voltage is rising.
1.84
1.88
1.91
V
The power supply voltage is falling.
1.80
1.84
1.87
V
The power supply voltage is rising.
1.74
1.77
1.81
V
The power supply voltage is falling.
1.70
1.73
1.77
V
The power supply voltage is rising.
1.64
1.67
1.70
V
The power supply voltage is falling.
1.60
1.63
1.66
tLW
V
s
300
Detection delay time
300
s
MAX.
Unit
(TA = +85 to +105°C, VPDR ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Detection voltage
Supply voltage level
Symbol
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Minimum pulse width
Detection delay time
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
tLW
Conditions
MIN.
TYP.
The power supply voltage is rising.
3.01
3.13
3.25
V
The power supply voltage is falling.
2.94
3.06
3.18
V
The power supply voltage is rising.
2.90
3.02
3.14
V
The power supply voltage is falling.
2.85
2.96
3.07
V
The power supply voltage is rising.
2.81
2.92
3.03
V
The power supply voltage is falling.
2.75
2.86
2.97
V
The power supply voltage is rising.
2.71
2.81
2.92
V
The power supply voltage is falling.
2.64
2.75
2.86
V
The power supply voltage is rising.
2.61
2.71
2.81
V
The power supply voltage is falling.
2.55
2.65
2.75
V
The power supply voltage is rising.
2.51
2.61
2.71
V
The power supply voltage is falling.
2.45
2.55
2.65
V
s
300
300
s
Page 90 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
(2) LVD Detection Voltage of Interrupt & Reset Mode
(TA = -40 to +85°C, VPDR ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Symbol
Interrupt and
VLVDA0
reset mode
VLVDA1
Conditions
TYP.
MAX.
Unit
1.60
1.63
1.66
V
Rising release reset voltage
1.74
1.77
1.81
V
Falling interrupt voltage
1.70
1.73
1.77
V
Rising release reset voltage
1.84
1.88
1.91
V
Falling interrupt voltage
1.80
1.84
1.87
V
Rising release reset voltage
2.86
2.92
2.97
V
Falling interrupt voltage
2.80
2.86
2.91
V
1.80
1.84
1.87
V
1.94
1.98
2.02
V
VPOC0, VPOC1, VPOC2 = 0, 0, 0, falling reset voltage
LVIS0, LVIS1 = 1, 0
VLVDA2
LVIS0, LVIS1 = 0, 1
VLVDA3
VLVDB0
MIN.
LVIS0, LVIS1 = 0, 0
VPOC0, VPOC1, VPOC2 = 0, 0, 1, falling reset voltage
VLVDB1
LVIS0, LVIS1 = 1, 0
Rising release reset voltage
Falling interrupt voltage
1.90
1.94
1.98
V
VLVDB2
LVIS0, LVIS1 = 0, 1
Rising release reset voltage
2.05
2.09
2.13
V
Falling interrupt voltage
2.00
2.04
2.08
V
Rising release reset voltage
3.07
3.13
3.19
V
Falling interrupt voltage
3.00
3.06
3.12
V
2.40
2.45
2.50
V
Rising release reset voltage
2.56
2.61
2.66
V
Falling interrupt voltage
2.50
2.55
2.60
V
Rising release reset voltage
2.66
2.71
2.76
V
Falling interrupt voltage
2.60
2.65
2.70
V
2.70
2.75
2.81
V
2.86
2.92
2.97
V
VLVDB3
VLVDC0
LVIS0, LVIS1 = 0, 0
VPOC0, VPOC1, VPOC2 = 0, 1, 0, falling reset voltage
VLVDC1
LVIS0, LVIS1 = 1, 0
VLVDC2
VLVDD0
LVIS0, LVIS1 = 0, 1
VPOC0, VPOC1, VPOC2 = 0, 1, 1, falling reset voltage
VLVDD1
LVIS0, LVIS1 = 1, 0
Rising release reset voltage
Falling interrupt voltage
2.80
2.86
2.91
V
VLVDD2
LVIS0, LVIS1 = 0, 1
Rising release reset voltage
2.96
3.02
3.08
V
Falling interrupt voltage
2.90
2.96
3.02
V
MIN.
TYP.
MAX.
Unit
(TA = +85 to +105°C, VPDR ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Interrupt and
reset mode
Symbol
VLVDD0
Conditions
VPOC0, VPOC1, VPOC2 = 0, 1, 1, falling reset voltage
VLVDD1
VLVDD2
2.6.7
LVIS0, LVIS1 = 1, 0
LVIS0, LVIS1 = 0, 1
2.64
2.75
2.86
V
Rising release reset voltage
2.81
2.92
3.03
V
Falling interrupt voltage
2.75
2.86
2.97
V
Rising release reset voltage
2.90
3.02
3.14
V
Falling interrupt voltage
2.85
2.96
3.07
V
Power supply voltage rising slope characteristics
(TA = -40 to +105°C, VSS = AVSS = 0 V)
Parameter
Power supply voltage rising slope
Caution
Symbol
SVDD
Conditions
MIN.
TYP.
MAX.
Unit
54
V/ms
Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating
voltage range shown in 2.4 AC Characteristics.
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 91 of 101
RL78/I1D
2. ELECTRICAL SPECIFICATIONS
2.7
RAM Data Retention Characteristics
(TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Data retention supply voltage
Symbol
VDDDR
MAX.
Unit
TA = -40 to +85°C
Conditions
MIN.
1.46
Note
TYP.
3.6
V
TA = +85 to +105°C
1.44 Note
3.6
V
The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is
Note
effected, but data is not retained when a POR reset is effected.
Operation mode
STOP mode
RAM data retention
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
2.8
Flash Memory Programming Characteristics
(TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Symbol
System clock frequency
fCLK
Number of code flash rewrites
Cerwr
Conditions
TYP.
1
Retained for 20 years
Notes 1, 2, 3
TA = 85°C Note 4
Number of data flash rewrites
Retained for 1 year
Notes 1, 2, 3
MIN.
TA = 25°C
MAX.
24
1,000
Unit
MHz
Times
1,000,000
Note 4
Retained for 5 years
100,000
TA = 85°C Note 4
Retained for 20 years
10,000
TA = 85°C Note 4
Note 1.
1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite.
Note 2.
When using flash memory programmer and Renesas Electronics self-programming library
Note 3.
These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics
Corporation.
Note 4.
This temperature is the average value at which data are retained.
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 92 of 101
RL78/I1D
2.9
2. ELECTRICAL SPECIFICATIONS
Dedicated Flash Memory Programmer Communication (UART)
(TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Symbol
Transfer rate
2.10
Conditions
MIN.
During serial programming
TYP.
115,200
MAX.
Unit
1,000,000 bps
Timing of Entry to Flash Memory Programming Modes
(TA = -40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
(TA = +85 to +105°C, 2.4 V ≤ AVDD = VDD ≤ 3.6 V, VSS = AVSS = 0 V)
Parameter
Symbol
How long from when an external reset ends until the
tSUINIT
tSU
POR and LVD reset must end
POR and LVD reset must end
TYP.
MAX.
Unit
100
ms
10
s
1
ms
before the external reset ends.
low level until an external reset ends Note 1
How long the TOOL0 pin must be kept at the low
MIN.
before the external reset ends.
initial communication settings are specified Note 1
How long from when the TOOL0 pin is placed at the
Conditions
tHD
POR and LVD reset must end
level after an external reset ends
before the external reset ends.
(excluding the processing time of the firmware to
control the flash memory) Notes 1, 2
Note 1.
Deassertion of the POR and LVD reset signals must precede deassertion of the pin reset signal.
Note 2.
This excludes the flash firmware processing time (723 s).
RESET
723 μs + tH D
processing
time
1-byte data for setting mode
TOOL0
tSU
tSU IN IT
The low level is input to the TOOL0 pin.
The external reset ends (POR and LVD reset must end before the external reset ends).
The TOOL0 pin is set to the high level.
Setting of the flash memory programming mode by UART reception and complete the baud rate setting.
Remark
tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from
when the external resets end.
tSU:
How long from when the TOOL0 pin is placed at the low level until a pin reset ends
tHD:
How long to keep the TOOL0 pin at the low level from when the external resets end
(excluding the processing time of the firmware to control the flash memory)
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 93 of 101
RL78/I1D
3. PACKAGE DRAWINGS
3. PACKAGE DRAWINGS
3.1
20-pin package
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LSSOP20-4.4x6.5-0.65
PLSP0020JB-A
P20MA-65-NAA-1
0.1
2
D
detail of lead end
11
20
E
1
c
10
1
L
3
bp
A
A2
A1
HE
e
y
(UNIT:mm)
NOTE
1.Dimensions “
2.Dimension “
1” and “
2”
” does not include tr
ITEM
DIMENSIONS
D
E
6.50 0.10
4.40 0.10
HE
6.40 0.20
A
1.45 MAX.
A1
0.10 0.10
A2
1.15
e
bp
c
L
y
0.65 0.12
0.22 0.10
0.05
0.15 0.05
0.02
0.50 0.20
0.10
0 to 10
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 94 of 101
RL78/I1D
3. PACKAGE DRAWINGS
JEITA Package code
RENESAS code
MASS(TYP.)[g]
P-TSSOP20-4.40x6.50-0.65
PTSP0020JI-A
0.08
2X
20
ddd C B A
11
E1
E
B
10
1
e
20X b
bbb
C
C B A
ccc
A
D
aaa C
SEATING
PLANE
A1
C
A2
A
Detail of Lead End
S
H
0.25
GAUGE PLANE
L
θ
L1
NOTES:
1.DIMENSION 'D' AND 'E1' DOES NOT INCLUDE MOLD FLASH.
2.DIMENSION 'b' DOES NOT INCLUDE TRIM OFFSET.
3.DIMENSION 'D' AND 'E1' TO BE DETERMINED AT DATUM PLANE H .
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Reference
Symbol
Dimension in Millimeters
Min.
Nom.
Max.
A
-
-
1.20
A1
0.05
-
0.15
A2
0.80
1.00
1.05
b
0.19
-
0.30
C
0.09
0.127
0.20
D
6.40
6.50
6.60
E1
4.30
4.40
4.50
E
6.40 BSC
e
0.65 BSC
L1
1.00 REF
L
0.50
0.60
S
0.20
-
-
θ
0°
-
8°
aaa
0.10
bbb
0.10
ccc
0.05
ddd
0.20
0.75
Page 95 of 101
RL78/I1D
3. PACKAGE DRAWINGS
3.2
24-pin package
JEITA Package code
P-HWQFN24-4x4-0.50
RENESAS code
Previous code
MASS(TYP.)[g]
PWQN0024KE-A
P24K8-50-CAB-3
0.04
D
18
13
DETAIL OF A PART
12
19
E
24
A
7
A1
c2
6
1
INDEX AREA
A
S
y
S
Referance
Symbol
D2
A
Lp
EXPOSED DIE PAD
1
6
7
24
Dimension in Millimeters
Min
Nom
Max
D
3.95
4.00
4.05
E
3.95
4.00
4.05
A
0.80
A1
0.00
b
0.18
e
Lp
B
E2
0.25
0.30
0.40
x
0.05
ZD
19
12
13
18
e
ZD
b
x
M
0.75
ZE
c2
0.50
0.05
y
ZE
0.30
0.50
0.75
0.15
0.20
D2
2.50
E2
2.50
0.25
S AB
2013 Renesas Electronics Corporation. All rights reserved.
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 96 of 101
RL78/I1D
3. PACKAGE DRAWINGS
JEITA Package code
RENESAS code
MASS(TYP.)[g]
P-HWQFN024-4x4-0.50
PWQN0024KF-A
0.04
2X
aaa C
18
13
19
12
D
INDEX AREA
(D/2 X E/2)
24
2X
7
aaa C
6
1
A
E
B
ccc C
C
SEATING PLANE
A (A3) A1
b(24X)
e
24X
eee C
E2
fff
1
fff
C A B
CA B
C
C A B
7
EXPOSED DIE PAD
D2
19
12
18
13
L(24X)
Reference
Symbol
Dimension in Millimeters
Min.
A
-
A1
0.00
A3
6
24
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
bbb
ddd
K(24X)
b
Nom.
Max.
0.80
0.02
0.05
0.203 REF.
0.18
D
0.25
0.30
4.00 BSC
E
4.00 BSC
e
0.50 BSC
L
0.35
0.40
0.45
K
0.20
-
-
D2
2.55
2.60
2.65
E2
2.55
2.60
2.65
aaa
0.15
bbb
0.10
ccc
0.10
ddd
0.05
eee
0.08
fff
0.10
Page 97 of 101
RL78/I1D
3.3
3. PACKAGE DRAWINGS
30-pin package
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LSSOP30-0300-0.65
PLSP0030JB-B
S30MC-65-5A4-3
0.18
30
16
detail of lead end
F
G
T
P
1
L
15
U
E
A
H
I
J
S
C
D
N
M
S
B
M
K
ITEM
A
MILLIMETERS
9.85 0.15
B
0.45 MAX.
C
0.65 (T.P.)
NOTE
D
0.24 0.08
0.07
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
E
0.1 0.05
F
1.3 0.1
G
1.2
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
H
8.1 0.2
I
6.1 0.2
J
1.0 0.2
K
0.17 0.03
L
0.5
M
0.13
N
0.10
P
3
T
0.25
U
0.6 0.15
5
3
Page 98 of 101
RL78/I1D
3. PACKAGE DRAWINGS
3.4
32-pin package
JEITA Package code
RENESAS code
Previous code
MASS(TYP.)[g]
P-HVQFN32-5x5-0.50
PVQN0032KE-A
P32K9-50B-BAH
0.058
HD
D
DETAIL OF
24
A
PART
17
16
25
A
E HE
c2
A1
9
32
8
1
ZE
ZD
INDEX MARK
A
S
y
Referance
Symbol
Dimension in Millimeters
D
4.75
E
4.75
Nom
A
S
D2
EXPOSED DIE PAD
A
Max
0.90
A1
0.00
b
0.20
e
Lp
1
Min
0.25
0.30
0.50
0.30
0.40
0.50
8
9
32
B
E2
x
0.10
y
0.05
HD
4.95
5.00
5.05
HE
4.95
5.00
5.05
ZD
0.75
ZE
0.75
c2
25
16
24
17
Lp
0.19
0.20
D2
3.30
E2
3.30
0.21
e
b
x
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
M
S
AB
Page 99 of 101
RL78/I1D
3. PACKAGE DRAWINGS
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LQFP32-7x7-0.80
PLQP0032GB-A
P32GA-80-GBT-1
0.2
HD
2
D
17
16
24
25
detail of lead end
1
E
c
HE
θ
32
8
1
L
9
e
(UNIT:mm)
3
b
x
M
A
A2
ITEM
D
DIMENSIONS
7.00±0.10
E
7.00±0.10
HD
9.00±0.20
HE
9.00±0.20
A
1.70 MAX.
A1
0.10±0.10
A2
y
A1
1.40
b
0.37±0.05
c
0.145 ±0.055
L
0.50±0.20
θ
0° to 8°
e
0.80
1.Dimensions “ 1” and “ 2” do not include mold flash.
x
0.20
2.Dimension “ 3” does not include trim offset.
y
0.10
NOTE
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
Page 100 of 101
RL78/I1D
3.5
3. PACKAGE DRAWINGS
48-pin package
JEITA Package Code
P-LFQFP48-7x7-0.50
RENESAS Code
PLQP0048KB-A
Previous Code
48P6Q-A
MASS[Typ.]
0.2g
HD
*1
D
36
25
37
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
24
bp
c
c1
*2
E
HE
b1
Reference Dimension in Millimeters
Symbol
48
13
1
ZE
Terminal cross section
12
c
A
F
A2
Index mark
ZD
S
A1
L
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
e
R01DS0244EJ0230 Rev. 2.30
Jun 30, 2020
*3
bp
Detail F
x
8.8
8.8
0
0.17
0.09
0°
L1
y S
Min
6.9
6.9
e
x
y
ZD
ZE
L
L1
0.35
Nom Max
7.0 7.1
7.0 7.1
1.4
9.0 9.2
9.0 9.2
1.7
0.1 0.2
0.22 0.27
0.20
0.145 0.20
0.125
8°
0.5
0.08
0.10
0.75
0.75
0.5 0.65
1.0
Page 101 of 101
REVISION HISTORY
Description
Rev.
Date
1.00
Aug 29, 2014
—
2.00
Jan 16, 2015
24, 25, 27
2.20
Feb 20, 2017
Page
Jun 30, 2020
Summary
First Edition issued
Addition of note 7 in 2.3.2 Supply current characteristics
24, 26
Addition of description in 2.3.2 Supply current characteristics
26, 28
Modification of description in 2.3.2 Supply current characteristics
28
Correction of error in 2.3.2 Supply current characteristics
95
Modification of package drawing in 3.2 24-pin products
ALL
The function name changed from real-time clock to real-time clock 2
5
Addition of product name in 1.3.1 20-pin products
6
Addition of product name in 1.3.2 24-pin products
7
Addition of product name in 1.3.3 30-pin products
8
Addition of product name in 1.3.4 32-pin products
9
Change of description and addition of product name in 1.3.4 32-pin products
10
Addition of product name in 1.3.5 48-pin products
13, 14
Change of description in 1.6 Outline of Functions
16
Change of 2.1 Absolute Maximum Ratings
22
Change of 2.3.1 Pin characteristics
24
Change of conditions in 2.3.2 Supply current characteristics
25, 27, 28
2.30
RL78/I1D Datasheet
Change of note 1 in 2.3.2 Supply current characteristics
26
Change of conditions and unit in 2.3.2 Supply current characteristics
30
Change of note 3 in 2.3.2 Supply current characteristics
31
Addition of note 5 in 2.3.2 Supply current characteristics
92
Change of table in 2.8 Flash Memory Programming Characteristics
92
Addition of note 4 in 2.8 Flash Memory Programming Characteristics
99
Change of package drawing in 3.5 48-pin products
1
Change of description in 1.1 Features
3
Change of Figure 1 - 1 Part Number, Memory Size, and Package of RL78/I1D
and addition of note 1
4
Change of table in 1.2 Ordering Information
5
Change of description in 1.3.1 20-pin products
93
Change of the figure in 2.10 Timing of Entry to Flash Memory Programming
Modes
95
Addition of package drawing in 3.1 20-pin package
97
Addition of package drawing in 3.2 24-pin package
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries
including the United States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
All trademarks and registered trademarks are the property of their respective owners.
C-1
General Precautions in the Handling of Microprocessing Unit and Microcontroller
Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the
products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
1.
Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps
must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be
adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.
Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor
2.
devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.
Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of
register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset
pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins
in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the
3.
level at which resetting is specified.
Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal
4.
elements. Follow the guideline for input signal during power-off state as described in your product documentation.
Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are
generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of
the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
5.
become possible.
Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program
execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator
during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal
6.
produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the
7.
input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.).
Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these
8.
addresses as the correct operation of the LSI is not guaranteed.
Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.
The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms
of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,
operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a systemevaluation test for the given product.
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by
you or third parties arising from the use of these circuits, software, or information.
2.
Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or
arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application
examples.
3.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.
4.
You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by
5.
Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the
you or third parties arising from such alteration, modification, copying or reverse engineering.
product’s quality grade, as indicated below.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; industrial robots; etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc.
Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are
not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause
serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all
liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or
other Renesas Electronics document.
6.
When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for Handling and Using Semiconductor Devices” in the
reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation
characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such specified
ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a
certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas
Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury
or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult
and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. You are responsible for carefully and
sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics
products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable
laws and regulations.
9.
Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws
or regulations. You shall comply with any applicable export control laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or
transactions.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or transfers the product to a third party, to notify such third
party in advance of the contents and conditions set forth in this document.
11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products.
(Note 1)
“Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries.
(Note 2)
“Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
(Rev.4.0-1 November 2017)
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics Corporation
TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan
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Tel: +86-21-2226-0888, Fax: +86-21-2226-0999
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Tel: +852-2265-6688, Fax: +852 2886-9022
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Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, #06-02 Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
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Unit No 3A-1 Level 3A Tower 8 UOA Business Park, No 1 Jalan Pengaturcara U1/51A, Seksyen U1, 40150 Shah Alam, Selangor, Malaysia
Tel: +60-3-5022-1288, Fax: +60-3-5022-1290
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No.777C, 100 Feet Road, HAL 2nd Stage, Indiranagar, Bangalore 560 038, India
Tel: +91-80-67208700
Renesas Electronics Korea Co., Ltd.
17F, KAMCO Yangjae Tower, 262, Gangnam-daero, Gangnam-gu, Seoul, 06265 Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5338
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