R5F11B7EGNA#20

Datasheet RL78/G1F R01DS0246EJ0112 Rev.1.12 Apr 28, 2021 RENESAS MCU True Low Power Platform (as low as 66 μA/MHz, and 0.57 μA for RTC + LVD), 1.6 V to 5.5 V operation, 32/64 Kbyte Flash, Max.32 MHz CPU operation, Enhanced analog functions, for General Purpose Applications 1. OUTLINE 1.1 Features Ultra-low power consumption technology Serial interfaces • VDD = single power supply voltage of 1.6 to 5.5 V which can operate a 1.8 V device at a low voltage • HALT mode • STOP mode • SNOOZE mode Timer RL78 CPU core • CISC architecture with 3-stage pipeline • Minimum instruction execution time: Can be changed from high speed (0.03125 s: @ 32 MHz operation with high-speed on-chip oscillator) to ultra-low speed (30.5 s: @ 32.768 kHz operation with subsystem clock) • Multiply/divide/multiply & accumulate instructions are supported. • Address space: 1 MB • General-purpose registers: (8-bit register  8)  4 banks • On-chip RAM: 5.5 KB Code flash memory • Code flash memory: 32/64 KB • Block size: 1 KB • Prohibition of block erase and rewriting (security function) • On-chip debug function • Self-programming (with boot swap function/flash shield window function) Data flash memory • Data flash memory: 4 KB • Back ground operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory. • Number of rewrites: 1,000,000 times (TYP.) • Voltage of rewrites: VDD = 1.8 to 5.5 V High-speed on-chip oscillator • Select from 64 MHz, 48 MHz, 32 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz • High accuracy: ±1.0% (VDD = 1.8 to 5.5 V, TA = -20 to +85°C) Operating ambient temperature • TA = 40 to +85°C (A: Consumer applications) • TA = 40 to +105°C (G: Industrial applications) Power management and reset function • On-chip power-on-reset (POR) circuit • On-chip voltage detector (LVD) (Select interrupt and reset from 14 levels) Data transfer controller (DTC) • Transfer modes: Normal transfer mode, repeat transfer mode, block transfer mode • Activation sources: Activated by interrupt sources. • Chain transfer function • • • • CSI: 3 to 6 channels UART/UART (LIN-bus supported): 3 channels I2C/simplified I2C: 3 to 6 channels IrDA: 1 channel • 16-bit timer: 9 channels (Timer Array Unit (TAU): 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels (with PWMOPA), Timer RG: 1 channel, Timer RX: 1 channel) • 12-bit interval timer: 1 channel • Real-time clock: 1 channel (calendar for 99 years, alarm function, and clock correction function) • Watchdog timer: 1 channel (operable with the dedicated low-speed on-chip oscillator) A/D converter • 8/10-bit resolution A/D converter (VDD = 1.6 to 5.5 V) • Analog input: 8 to 17 channels • Internal reference voltage (1.45 V) and temperature sensor D/A converter • • • • 8-bit resolution D/A converter (VDD = 1.6 to 5.5 V) Analog output: 1 or 2 channels Output voltage: 0 V to VDD Real-time output function Comparator • 2 channels (pin selector is provided for 1 channel) • Incorporates a function for the output of a timer window in combination with the timer array unit. • The external reference voltage or internal reference voltage can be selected as the reference voltage. Programmable gain amplifier (PGA) • 1 channel I/O port • I/O port: 20 to 58 (N-ch open drain I/O [withstand voltage of 6 V]: 2 to 4, N-ch open drain I/O [VDD withstand voltage/EVDD withstand voltage]: 10 to 16) • Can be set to N-ch open drain, TTL input buffer, and onchip pull-up resistor • Different potential interface: Can connect to a 1.8/2.5/3 V device • On-chip key interrupt function • On-chip clock output/buzzer output controller Others • On-chip BCD (binary-coded decimal) correction circuit Remark The functions mounted depend on the product. See 1.6 Outline of Functions. Event link controller (ELC) • Event signals of 22 types can be linked to the specified peripheral function. R01DS0246EJ0112 Rev.1.12 Apr 28, 2021 Page 1 of 143 RL78/G1F 1. OUTLINE ROM, RAM capacities Flash ROM Data flash RAM 64 KB 4 KB 32 KB 4 KB Note RL78/G1F 24 pins 32 pins 36 pins 48 pins 64 pins 5.5 KB Note R5F11B7E R5F11BBE R5F11BCE R5F11BGE R5F11BLE 5.5 KB Note R5F11B7C R5F11BBC R5F11BCC R5F11BGC R5F11BLC This is about 4.5 KB when performing self-programming and rewriting the data flash memory (For details, see CHAPTER 3 CPU ARCHITECTURE in the RL78/G1F User’s Manual). R01DS0246EJ0112 Rev.1.12 Apr 28, 2021 Page 2 of 143 RL78/G1F 1.2 1. OUTLINE Ordering Information Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G1F Product name Ordering Part Number R 5 F 1 1 B L E A x x x F B # 1 0 Packaging specification #U0: Tray (HWQFN, WFLGA) #00, #20: Tray (HWQFN) #10, #30: Tray (LFQFP, LQFP) #W0: Embossed Tape (HWQFN, WFLGA) #40: Embossed Tape (HWQFN) #50: Embossed Tape (LFQFP, LQFP) Package type: FP: LQFP, 0.80-mm pitch FB: LFQFP, 0.50-mm pitch NA:HWQFN, 0.50-mm pitch LA: WFLGA, 0.50-mm pitch ROM number (Omitted with blank products) Fields of application : A: Consumer applications, TA = -40 to +85C G: Industrial applications , TA = -40 to +105C ROM capacity: C: 32 KB E: 64 KB Pin count: 7: 24-pin B: 32-pin C: 36-pin G: 48-pin L: 64-pin RL78/G1F Memory type: F : Flash memory Renesas MCU Renesas semiconductor product R01DS0246EJ0112 Rev.1.12 Apr 28, 2021 Page 3 of 143 RL78/G1F 1. OUTLINE Table 1 - 1 List of Ordering Part Numbers Pin count Package Fields of Application Note 24 pins 24-pin plastic HWQFN Ordering Part Number Product name A R5F11B7CANA, R5F11B7EANA G R5F11B7CGNA, R5F11B7EGNA 32-pin plastic HWQFN A R5F11BBCANA, R5F11BBEANA (5 × 5 mm, 0.5-mm pitch) G R5F11BBCGNA, R5F11BBEGNA 32-pin plastic LQFP A R5F11BBCAFP, R5F11BBEAFP (4 × 4 mm, 0.5-mm pitch) 32 pins 36 pins 48 pins 64 pins (7 × 7 mm, 0.8-mm pitch) G R5F11BBCGFP, R5F11BBEGFP 36-pin plastic WFLGA A R5F11BCCALA, R5F11BCEALA (4 × 4 mm, 0.5-mm pitch) G R5F11BCCGLA, R5F11BCEGLA 48-pin plastic LFQFP A R5F11BGCAFB, R5F11BGEAFB (7 × 7 mm, 0.5-mm pitch) G R5F11BGCGFB, R5F11BGEGFB 64-pin plastic LFQFP A R5F11BLCAFB, R5F11BLEAFB G R5F11BLCGFB, R5F11BLEGFB (10 × 10 mm, 0.5-mm pitch) Note Caution Packaging specification RENESAS Code #U0, #W0 PWQN0024KE-A #00, #20, #40 PWQN0024KF-A #U0, #W0 PWQN0024KE-A #00, #20, #40 PWQN0024KF-A #00, #20, #40 PWQN0032KE-A #10, #30, #50 PLQP0032GB-A #U0, #W0 PWLG0036KA-A #10, #30, #50 PLQP0048KB-B #10, #30, #50 PLQP0064KB-C For the fields of application, refer to Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G1F. The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0246EJ0112 Rev.1.12 Apr 28, 2021 Page 4 of 143 RL78/G1F 1.3 1. OUTLINE Pin Configuration (Top View) 1.3.1 24-pin products P1 47/ANI18/VCOUT1/IVREF0 P1 0/A NI20/SCK11/SCL11 /TRDIOD1/(TxD2) P11 /ANI21/SI11/S DA 11/TRDIO C1 P1 2/S O11/TRDIOB1/INTP5/VCOUT0 P1 3/TxD2 /SO 20/TRDIO A1/(TRDIOC0)/IrTxD/TI03 /TO03 P1 4/RxD2 /SI20/SDA20 /TRDIOD0/(SCLA0) /IrRxD • 24-pin plastic HWQFN (4  4 mm, 0.5-mm pitch) exposed die pad 18 17 16 15 14 13 P 22/ANI2/ANO0/PGAI/IVCMP0 P21 /ANI1/AVREFM/IVCMP13 P20/ANI0/AVREFP /INTP11/IVCMP12 P01/ANI16 /TO00 /RxD1 /TRGCLKB/TRJIO0/(IrRxD)/INTP10 /SCLA 0/IVCMP11 P00/ANI17/TI00/TxD1/TRGCLKA/(TRJO0)/(IrTxD)/INTP8/SDAA 0/IVCMP10 P40/TOOL0 19 20 21 22 23 24 RL78/G1F (Top View) 12 11 10 9 8 7 P15/PCLBUZ1/SCK 20/SCL20/TRDIOB0/(SDAA0) P51/INTP2/SO00 /TxD0 /TOOLTxD/TRGIOB/(TRDIOD1) P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)/(TRDIOC1) P72/PCLBUZ0/INTP4/SCK 00/SCL00/TRJO0/(TxD1)/(VCOUT1) P73/INTP3/SSI00/(TRJIO0)/(RxD1)/(VCOUT0) VDD RESE T P137/INTP0 P 122/X2/EXCLK P121/X1 REG C VSS 1 2 3 4 5 6 Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection registers 0 to 3 (PIOR0 to PIOR3). R01DS0246EJ0112 Rev.1.12 Apr 28, 2021 Page 5 of 143 RL78/G1F 1.3.2 32-pin products P10/ANI20/SCK11/SCL11/TRDIOD1/(TxD2) P11/ANI21/SI11/SDA11/TRDIOC1 P12/ANI22/SO11/TRDIOB1 P13/ANI23/TxD2/SO20/TRDIOA1/IrTxD P14/ANI24/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)/IrRxD P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/(RxD0)/(TRDIOA1) P17/TI02/TO02/TRDIOA0/TRDCLK/(TxD0)/(TRDIOD0) • 32-pin plastic HWQFN (5  5 mm, 0.5-mm pitch) exposed die pad P147/ANI18/IVREF0 P23/ANI3/ANO1/PGAGND P22/ANI2/ANO0/PGAI/IVCMP0 P21/ANI1/AVREFM/IVCMP13 P20/ANI0/AVREFP/INTP11/IVCMP12 P01/ANI16/TO00/RxD1/TRGCLKB/TRJIO0/INTP10/IVCMP11 P00/ANI17/TI00/TxD1/TRGCLKA/(TRJO0)/INTP8/IVCMP10 P120/ANI19/VCOUT0 24 23 22 21 20 19 18 17 25 16 26 15 27 14 28 13 29 12 30 11 31 10 32 9 1 2 3 4 5 6 7 8 P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB/(TRDIOD1) P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)/(TRDIOC1) P30/INTP3/SCK00/SCL00/TRJO0/(TRDIOB1) P70/INTP6/(VCOUT1) P72/INTP7/(TxD1) P73/(RxD1)/(VCOUT0) P74/SDAA0 P31/TI03/TO03/INTP4/PCLBUZ0/SSI00/(TRJIO0)/VCOUT1/SCLA0 P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD 1. OUTLINE Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection registers 0 to 3 (PIOR0 to PIOR3). Remark 2. It is recommended to connect an exposed die pad to VSS. R01DS0246EJ0112 Rev.1.12 Apr 28, 2021 Page 6 of 143 RL78/G1F 1. OUTLINE P1 0/A NI20/SCK11/SCL11 /TRDIOD1/(TxD2) P1 1/A NI21/SI11/SDA11/TRDIOC1 P1 2/A NI22/SO11 /TRDIOB 1 P1 3/A NI23/TxD2/SO20 /TRDIOA1 /IrTxD P1 4/A NI24/RxD2/SI20/SDA20/TRDIO D0 /(S CL A0)/IrRxD P1 5/P CLB UZ1/SCK20/SCL20 /TRDIOB0 /(S DA A0) P1 6/TI01/TO 01/INTP5/TRDIO C0 /(RxD0 )/(TRDIOA 1) P1 7/TI02/TO 02/TRDIO A0/TRDCL K/( TxD0)/(TRDIO D0 ) • 32-pin plastic LQFP (7  7 mm, 0.8-mm pitch) 24 23 22 21 20 19 18 17 16 15 14 RL78/G1F 13 (Top View) 12 11 10 9 1 2 3 4 5 6 7 8 Caution P51/INTP2/SO 00/TxD0/TOOLTxD/TRGIOB/(TRDIOD1) P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/( TRJO0)/(TRDIOC1) P30/INTP3/SCK00 /SCL00 /TRJO0/(TRDIOB1) P70/INTP6/(VCOUT1) P72/INTP7/(TxD1) P73/(RxD1)/(VCOUT0) P74/SDAA0 P31/TI03 /TO03 /INTP4 /PCLBUZ0/SSI00/(TRJIO0)/VCOUT1 /SCLA 0 VSS V DD 25 26 27 28 29 30 31 32 P40/TO OL0 RESE T P 137/INTP0 P 122/X2/EXCLK P121/X1 REG C P147 /ANI18/IVREF0 P23/ANI3 /ANO1 /PGAGND P 22/ANI2/ANO0/PGAI/IVCMP0 P 21/ANI1/AVREFM/IVCMP13 P20 /ANI0/AVREFP /INTP11/IVCMP12 P01/ANI16 /TO00 /RxD1 /TRGCLKB/TRJIO0/INTP10/IVCMP11 P00/ANI17/TI00/TxD1/TRGCLKA/(TRJO0)/INTP8/IVCMP10 P120 /ANI19/VCOUT0 Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection registers 0 to 3 (PIOR0 to PIOR3). R01DS0246EJ0112 Rev.1.12 Apr 28, 2021 Page 7 of 143 RL78/G1F 1. OUTLINE 1.3.3 36-pin products • 36-pin plastic WFLGA (4 × 4 mm, 0.5-mm pitch) Top View Bottom View 6 5 4 3 2 1 A B C D E F F E D C B A INDEX MARK A 6 5 3 C D E EVDD0 VDD P121/X1 P122/X2/EXCLK P137/INTP0 P61/SDAA0 P60/SCLA0 VSS REGC RESET F P40/TOOL0 P124/XT2/ P14/ANI24/RxD2/ P20/ANI0/ P21/ANI1/ P01/ANI16/TO00/ P123/XT1 INTP4/PCLBUZ0/ SI20/SDA20/ AVREFP/IVCMP12/ AVREFM/IVCMP13 RxD1/TRGCLKB/ SSI00/(TRJIO0)/ TRDIOD0/ INTP11 VCOUT1 (SCLA0)/IrRxD P50/INTP1/SI00/ P70/INTP6/ P15/PCLBUZ1/ P23/ANI3/ANO1/ P00/ANI17/TI00/ P120/ANI19/ RxD0/TOOLRxD/ (VCOUT0)/ SCK20/SCL20/ PGAGND TxD1/TRGCLKA/ VCOUT0 SDA00/TRGIOA/ (VCOUT1) TRDIOB0/ (TRJO0)/INTP8/ (SDAA0) IVCMP10 (TRJO0)/ 6 5 EXCLKS P31/TI03/TO03/ 4 B 4 TRJIO0/INTP10/ IVCMP11 3 (TRDIOC1) 2 1 P30/INTP3/ P16/TI01/TO01/ P12/ANI22/SO11/ P11/ANI21/SI11/ RTC1HZ/SCK00/ INTP5/TRDIOC0/ TRDIOB1 SDA11/TRDIOC1 SCL00/TRJO0/ (RxD0)/ (TRDIOB1) (TRDIOA1) P51/INTP2/SO00/ P17/TI02/TO02/ P13/ANI23/TxD2/ P10/ANI20/ P147/ANI18/ TxD0/TOOLTxD/ TRDIOA0/ SO20/TRDIOA1/ SCK11/SCL11/ IVREF0 TRGIOB/ TRDCLK0/(TxD0)/ IrTxD (TRDIOD1) (TRDIOD0) A B P24/ANI4 P22/ANI2/ANO0/ PGAI/IVCMP0 P25/ANI5 1 TRDIOD1/(TxD2) C D 2 E F Caution 1. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Caution 2. Make VDD pin the potential that is higher than EVDD0 pin. Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection registers 0 to 3 (PIOR0 to PIOR3). Remark 3. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD and EVDD0 pins. R01DS0246EJ0112 Rev.1.12 Apr 28, 2021 Page 8 of 143 RL78/G1F 1. OUTLINE 1.3.4 48-pin products P121 /X1 REGC Caution P 26/ANI6 P 27/ANI7 P 24/ANI4 P 25/ANI5 P 22/ANI2/ANO0/PGA I/IV CMP0 P 23/ANI3/ANO1/PGA GND P 20/ANI0/AVREFP/IVCMP12 /INTP1 1 P 21/ANI1/AVREFM/IV CMP1 3 P 130 P 11/ANI21 /SI11/SDA11 /TRDIOC1 P 12/ANI22 /SO 11/TRDIOB1 19 P 13/ANI23 /TxD2 /SO 20/TRDIOA1/IrTxD P 14/ANI24 /RxD2 /SI20/SDA20 /TRDIOD0/(SCLA0)/IrRxD RL78/G1F (Top View) 42 43 44 45 48 18 17 16 15 46 47 1 2 3 4 5 6 P60 /SCLA 0 V SS VDD 21 20 14 13 7 8 9 10 11 12 P 15/PCLBUZ1/SCK20 /SCL 20/TRDIOB0/(SDAA0) P 16/TI01/TO01/INTP5/TRDIOC0/( RxD0)/(TRDIOA1) P 17/TI02/TO02/TRDIOA0/TRDCLK/(TxD0)/(TRDIOD0) P 51/INTP2/SO00 /TxD0/TOOLTxD/TRGIOB/(TRDIOD1 ) P 50/INTP1/SI00 /RxD0/TOOLRxD/SDA 00/TRGIOA/(TRJO0 )/(TRDIOC1) P72 /KR2/SO2 1/(TxD1) P71/KR1/SI21/SDA21/(VCOUT0) P70/KR0/S CK 21/SCL21/(VCOUT1) P30 /INTP 3/RTC1HZ/SCK00/SCL00/TRJO0 /(TRDIOB 1) P137 /INTP0 P122 /X 2/EXCLK 40 41 P7 5/K R5 /INTP9 /SCK0 1/S CL0 1 P74/KR4/S I01 /SDA0 1 P73/KR3/SO0 1/(RxD1) P124 /XT2 /EXCLKS P123/XT1 22 P 147/ANI18 /IVREF0 P 146 P 10/ANI20 /SCK11 /SCL 11/TRDIOD1/(TxD2) P31/TI03 /TO03 /INTP4 /(P CLB UZ0)/(TRJIO0)/VCOUT1 P40 /TOOL 0 RESET 36 35 34 33 32 31 30 29 28 27 26 25 24 23 37 38 39 P61 /SDAA 0 P6 2/S SI0 0 P6 3 P120/ANI19 /VCOUT0 P 41/(TRJIO0) P 00/ANI17/TI0 0/TxD1 /TRGCLKA/(TRJO0 )/INTP 8/IVCMP10 P 01/ANI16/TO00/RxD1/TRGCL KB/TRJIO 0/INTP 10/IVCMP11 P 140/PCLBUZ0/INTP 6 • 48-pin plastic LFQFP (7  7 mm, 0.5-mm pitch) Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection registers 0 to 3 (PIOR0 to PIOR3). R01DS0246EJ0112 Rev.1.12 Apr 28, 2021 Page 9 of 143 RL78/G1F 1.3.5 1. OUTLINE 64-pin products P 147/ANI18 /IVREF0 P 146 P 10/A NI20/SCK11 /SCL1 1/TRDIOD1 P 11/A NI21/SI11/SDA11/TRDIOC1 P 12/A NI22/SO 11/TRDIO B1/(INTP5) P 13/A NI23/TxD2/SO2 0/TRDIOA 1/IrTxD P 14/A NI24/RxD2/SI20/SDA20/TRDIOD0/( SCLA0)/Ir RxD P 15/S CK 20/SCL20/TRDIOB0/(SDAA0 ) P 16/TI01/TO 01/INTP5/TRDIOC0/(S I00 )/(RxD0)/( TRDIO A1) P 17/TI02/TO 02/TRDIO A0/TRDCLK/(SO00 )/(TxD0)/( TRDIO D0 ) P 55/( PCLBUZ1 )/(S CK 00)/(INTP4) P 54/( INTP3) P 53/( INTP2) P 52/( INTP1) P 51/INTP2/SO00/TxD0/TOOLTxD/TRG IO B/(TRDIO D1) P 50/INTP1/SI0 0/RxD0 /TOOL RxD/S DA 00/TRGIOA/(TRJO0 )/(TRDIOC1) • 64-pin plastic LFQFP (10  10 mm, 0.5-mm pitch) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 31 51 30 52 29 53 28 54 27 55 26 56 25 57 RL78/G1F 24 58 (Top View) 23 59 60 61 62 63 64 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P 30/INTP3/RTC1HZ/SCK00 /SCL00 /TRJO0/(TRDIOB1) P 05/(INTP10) P 06/(INTP11)/(TRJIO0) P 70/KR0/SCK 21/SCL21/(VCOUT1) P 71/KR1/SI21 /SDA21 /(VCOUT0) P 72/KR2/SO 21 P 73/KR3/SO 01 P 74/KR4/INTP8/SI01 /SDA01 P 75/KR5/INTP9/SCK 01/SCL01 P 76/KR6/INTP10/(RxD2) P 77/KR7/INTP11/(TxD2) P 31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)/VCOUT1 P 63 P 62/SSI00 P 61/SDAA0 P 60/SCLA0 P1 20/ANI19 /VCOUT0 P4 3/(INTP9) P4 2/(INTP8) P 41/(TRJIO 0) P4 0/TOO L0 RESET P1 24/X T2 /EX CL KS P123/XT1 P1 37/INTP0 P12 2/X 2/E XCLK P1 21/X1 REGC VSS EVSS0 VDD EV DD0 P27 /ANI7 P26 /ANI6 P25 /ANI5 P24 /ANI4 P23 /ANI3/ANO1/PGAGND P22/ANI2 /ANO0 /PGAI/IVCMP0 P21/ANI1 /AV REFM/IVCMP13 P20/ANI0 /AV REFP/IVCMP12/(INTP11) P130 P04 /SCK 10/SCL10 P03/ANI16 /SI10/RxD1/SDA10 /IVCMP11 P02 /ANI17/SO10 /TxD1 /IVCMP10 P01/TO00/TRGCLKB/TRJIO0 /(INTP10) P00/TI00 /TRGCLKA/(TRJO0)/(INTP8) P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 Caution 1. Make EVSS0 pin the same potential as VSS pin. Caution 2. Make VDD pin the potential that is higher than EVDD0 pin. Caution 3. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD and EVDD0 pins and connect the V SS and EV SS0 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection registers 0 to 3 (PIOR0 to PIOR3). R01DS0246EJ0112 Rev.1.12 Apr 28, 2021 Page 10 of 143 RL78/G1F 1.4 1. OUTLINE Pin Identification ANI0 to ANI7: Analog input ANI16 to ANI24: Analog input PGAGND: PGA input ANO0, ANO1: Analog output RTC1HZ: Real-time clock correction AVREFM: Analog reference voltage AVREFP: PGAI: PGA input clock (1 Hz) output minus RxD0 to RxD2: Receive data Analog reference voltage SCK00, SCK01, SCK10: Serial clock input/output plus SCK11, SCK20, SCK21: Serial clock input/output EVDD0: Power supply for port SCLA0: Serial clock input/output EVSS0: Ground for port SCL00, SCL01, SCL10, SCL11: Serial clock output EXCLK: External clock input SCL20,SCL21: Serial clock output (main system clock) SDAA0: Serial data input/output External clock input SDA00, SDA01, SDA10: Serial data input/output (subsystem clock) SDA11, SDA20, SDA21: Serial data input/output INTP0 to INTP11: External interrupt input SI00, SI01, SI10, SI11: Serial data input IrRxD: Receive Data for IrDA SI20, SI21: Serial data input IrTxD: Transmit Data for IrDA SO00, SO01, SO10: Serial data output IVCMP0: Comparator 0 input SO11, SO20, SO21: Serial data output EXCLKS: SSI00: Serial interface chip select input reference input TI00 to TI03: Timer input Comparator 0 reference TO00 to TO03: Timer output input TRJO0: Timer output IVCMP10 to IVCMP13: Comparator 1 input / IVREF0: KR0 to KR7: Key return TOOL0: Data input/output for tool P00 to P06: Port 0 TOOLRxD, TOOLTxD: Data input/output for external device P10 to P17: Port 1 TRDCLK, TRGCLKA: Timer external input clock P20 to P27: Port 2 TRGCLKB: Timer external Input clock P30, P31: Port 3 TRDIOA0, TRDIOB0: Timer input/output P40 to P43: Port 4 TRDIOC0, TRDIOD0: Timer input/output P50 to P55: Port 5 TRDIOA1, TRDIOB1: Timer input/output P60 to P63: Port 6 TRDIOC1, TRDIOD1: Timer input/output P70 to P77: Port 7 TRGIOA, TRGIOB, TRJIO0: Timer input/output P120 to P124: Port 12 TxD0 to TxD2: Transmit data P130, P137 Port 13 VCOUT0, VCOUT1: Comparator output P140, P141, P146, Port 14 VDD: Power supply VSS: Ground Programmable clock output/ X1, X2: Crystal oscillator (main system clock) buzzer output XT1, XT2: Crystal oscillator (subsystem clock) P147: PCLBUZ0, PCLBUZ1: REGC: Regulator capacitance RESET: Reset R01DS0246EJ0112 Rev.1.12 Apr 28, 2021 Page 11 of 143 RL78/G1F 1.5 1. OUTLINE Block Diagram TIMER ARRAY UNIT (4ch) TI00 TO00 ch0 TI01/TO01 ch1 TI02/TO02 ch2 TI03/TO03 RxD0 (LINSEL) ch3 2 TRGIOA, TRGIOB 2 TRGCLKA, TRGCLKB TIMER RG TRDIOA0/TRDCLK TRDIOB0, TRDIOC0, TRDIOD0 3 PORT 0 7 P00 to P06 PORT 1 8 P10 to P17 PORT 2 8 P20 to P27 PORT 3 2 P30, P31 PORT 4 4 P40 to P43 PORT 5 6 P50 to P55 PORT 6 4 P60 to P63 PORT 7 8 P70 to P77 4 P120 P121 to P124 PWMOPA TRDIOA1 to TRDIOD1 1 4 TRJIO0 TIMER RJ TRJO00 TIMER RD (2ch) WINDOW WATCHDOG TIMER ch0 PORT 12 P130 PORT 13 ch1 LOW-SPEED ON-CHIP OSCILLATOR 12- BIT INTERVAL TIMER PORT 14 P137 4 TIMER RX SERIAL ARRAY UNIT0 (4ch) RxD0 TxD0 UART 0 LINSEL RxD1 TxD1 UART 1 SCK00 SI00 SO00 SSI00 CSI00 SCK01 SI01 SO01 CSI01 SCK10 SI10 SO10 CSI10 SCK11 SI11 SO11 CSI11 SCL00 SDA00 IIC00 SCL01 SDA01 IIC01 SCL10 SDA10 IIC10 REAL-TIME CLOCK RTC1HZ INTCMP1 RL78 CPU CORE POR/LVD CONTROL CODE FLASH MEMORY MULTIPLIER & DIVIDER, MULTIPLYACCUMULATOR RESET CONTROL DATA FLASH MEMORY TOOL0 ON-CHIP DEBUG SYSTEM CONTROL RESET X1 X2/EXCLK XT 1 XT 2/EXCLKS HIGH-SPEED ON-CHIP OSCILLATOR SCL11 SDA11 IIC11 RAM VOLTAGE REGULATOR KEY RETURN V DD, V SS, TOOLRxD, EV DD0 EV SS0 TOOLTxD RxD2/IrRxD TxD2/IrTxD SCK20 SI 20 SO20 UART2 (IrDA) CSI20 CLOCK OUTPUT CONTROL SCLA0 2 CSI21 SCL20 SDA20 IIC20 SCL21 SDA21 IIC21 REGC 8 KR0 to KR7 RxD0 (LINSEL) INTP0 11 INTP1 to INTP11 8 ANI0 to ANI7 9 ANI16 to ANI24 AV REFP AV REFM PROGRAMMABLE GAIN AMPLIFIER DATA TRANSFER CONTROL PGAI PGAGND COMPARATOR (2ch) BCD ADJUSTMENT D/A CONVERTER A/D CONVERTER PCLBUZ0, PCLBUZ1 EVENT LINK CONTROLLER SCK21 SI21 SO21 INTERRUPT CONTROL SDAA0 SERIAL INTERFACE IICA0 BUZZER OUTPUT SERIAL ARRAY UNIT1 (2ch ) Remark POWER ON RESET / VOLTAGE DETECTOR P140, P141, P146, P147 ANO0 COMP A RA TOR0 VCOUT0 IVCMP0 IVREF 0 COMP A RA TOR1 VCOUT1 IVCMP10 IVCMP11 IVCMP12 IVCMP13 ANO1 Block diagram of 64-pin products is shown as an example. For difference of the block diagram other than 64-pin products, refer to 1.6 Outline of Functions. R01DS0246EJ0112 Rev.1.12 Apr 28, 2021 Page 12 of 143 RL78/G1F 1.6 1. OUTLINE Outline of Functions Caution This outline describes the functions at the time when Peripheral I/O redirection register 0, 1 (PIOR0, 1) are set to 00H. (1/2) 24-pin 32-pin 36-pin 48-pin 64-pin R5F11B7x (x = C, E) R5F11BBx (x = C, E) R5F11BCx (x = C, E) R5F11BGx (x = C, E) R5F11BLx (x = C, E) Code flash memory (KB) 32, 64 32, 64 32, 64 32, 64 32, 64 Data flash memory (KB) 4 4 4 4 4 Item RAM (KB) 5.5 Address space Main system clock Note 5.5 Note 5.5 Note 5.5 Note 5.5 Note 1 MB High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) HS (high-speed main) mode: 1 to 20 MHz (VDD = 2.7 to 5.5 V), HS (high-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V), LS (low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 2.7 V), LV (low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 1.8 V) High-speed on-chip oscillator clock (fIH) HS (high-speed main) mode: HS (high-speed main) mode: LS (low-speed main) mode: LV (low-voltage main) mode: Subsystem clock 1 to 32 MHz (VDD = 2.7 to 5.5 V), 1 to 16 MHz (VDD = 2.4 to 5.5 V), 1 to 8 MHz (VDD = 1.8 to 5.5 V), 1 to 4 MHz (VDD = 1.6 to 5.5 V) — XT1 (crystal) oscillation, external subsystem clock input (EXCLKS) 32.768 kHz Low-speed on-chip oscillator clock 15 kHz (TYP.): VDD = 1.6 to 5.5 V General-purpose register 8 bits  32 registers (8 bits  8 registers  4 banks) Minimum instruction execution time 0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) 30.5 s (Subsystem clock: fSUB = 32.768 kHz operation) — Instruction set I/O port • • • • • Total CMOS I/O Timer Data transfer (8/16 bits) Adder and subtractor/logical operation (8/16 bits) Multiplication (8 bits  8 bits, 16 bits  16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits) Multiplication and Accumulation (16 bits  16 bits + 32 bits) Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. 20 28 31 44 58 17 (N-ch O.D. output [VDD withstand voltage]: 10) 25 (N-ch O.D. output [VDD withstand voltage]: 12) 24 (N-ch O.D. output [VDD withstand voltage]: 10) 34 (N-ch O.D. output [VDD withstand voltage]: 12) 48 (N-ch O.D. output [VDD withstand voltage]: 12) CMOS input 3 3 5 5 5 CMOS output — — — 1 1 N-ch open-drain I/O (6 V tolerance) — — 2 4 4 16-bit timer 9 channels (TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels (with PWMOPA), Timer RX: 1 channel, Timer RG: 1 channel) Watchdog timer 1 channel Real-time clock (RTC) 1 channel 12-bit interval timer 1 channel Timer output Timer outputs: 13 channels PWM outputs: 8 channels RTC output Timer outputs: 16 channels PWM outputs: 9 channels — 1 • 1 Hz (subsystem clock: fSUB = 32.768 kHz) Note This is about 4.5 KB when the self-programming function and data flash function are used (For details, see CHAPTER 3 in the RL78/G1F User’s Manual). R01DS0246EJ0112 Rev.1.12 Apr 28, 2021 Page 13 of 143 RL78/G1F 1. OUTLINE (2/2) Item 24-pin 32-pin 36-pin 48-pin 64-pin R5F11B7x (x = C, E) R5F11BBx (x = C, E) R5F11BCx (x = C, E) R5F11BGx (x = C, E) R5F11BLx (x = C, E) 2 2 2 2 2 17 channels 17 channels Clock output/buzzer output • 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) 8/10-bit resolution A/D converter 8 channels 8-bit D/A converter 1 channel 13 channels 15 channels 2 channels Comparator 2 channels Programmable gain amplifier (PGA) 1 channel Serial interface [24-pin, 32-pin, 36-pin products] • CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel • CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel • CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel [48-pin products] • CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C:2 channels • CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel • CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels [64-pin products] • CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels • CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels • CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels I2C bus 1 channel 1 channel 1 channel 1 channel 1 channel Data transfer controller (DTC) 30 sources 32 sources 31 sources 32 sources 33 sources 21 21 21 22 22 Event link controller (ELC) Vectored interrupt sources Event input 9 10 10 10 10 Internal 25 25 25 25 25 External 9 11 10 12 13 — — — 6 8 Event trigger output Key interrupt Reset • • • • Reset by RESET pin Internal reset by watchdog timer Internal reset by power-on-reset Internal reset by voltage detector • Internal reset by illegal instruction execution Note • Internal reset by RAM parity error • Internal reset by illegal-memory access Power-on-reset circuit Voltage detector 1.51 ±0.04 V (TA = 40 to +85°C) 1.51 ±0.06 V (TA = 40 to +105°C) • Power-down-reset: 1.50 ±0.04 V (TA = 40 to +85°C) 1.50 ±0.06 V (TA = 40 to +105°C) • Power-on-reset: [TA = 40 to +85°C] • Rising edge: 1.67 ±0.03 V to 4.00 ±0.08 V (14 stages) • Falling edge: 1.63 ±0.03 V to 3.98 ±0.08 V (14 stages) [TA = 40 to +105°C (G: Industrial applications)] • Rising edge: 2.61 ±0.1 V to 4.06 ±0.16 V (8 stages) • Falling edge: 2.55 ±0.1 V to 3.98 ±0.15 V (8 stages) On-chip debug function Power supply voltage Provided VDD = 1.6 to 5.5 V (TA = 40 to +85°C) VDD = 2.4 to 5.5 V (TA = 40 to +105°C) Operating ambient temperature TA = 40 to +85°C (A: Consumer applications), TA = 40 to +105°C (Industrial applications), The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not is issued by emulation with the in-circuit emulator or on-chip debug emulator. R01DS0246EJ0112 Rev.1.12 Apr 28, 2021 Page 14 of 143 RL78/G1F 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C) 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C) This chapter describes the following electrical specifications. Target products A: Consumer applications TA = −40 to +85°C R5F11BxxAxx G: Industrial applications when TA = −40 to +105°C products is used in the range of TA = −40 to +85°C R5F11BxxGxx Caution 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. Caution 2. With products not provided with an EVDD0, EVSS0 pin, replace EVDD0 with VDD, or replace EVSS0 with VSS. Caution 3. The pins mounted depend on the product. Refer to 2.1 Port Functions to 2.2.1 Functions for each product in the RL78/G1F User’s Manual. R01DS0246EJ0112 Rev.1.12 Apr 28, 2021 Page 15 of 143 RL78/G1F 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C) 2.1 Absolute Maximum Ratings Absolute Maximum Ratings Parameter (1/2) Symbols Supply voltage VDD REGC pin input voltage VIREGC Conditions EVDD0 REGC Ratings Unit -0.5 to +6.5 V -0.5 to +6.5 V -0.3 to +2.8 V and -0.3 to VDD +0.3 Note 1 Input voltage VI1 P00 to P06, P10 to P17, P30, P31, P40 to P43, P50 to P55, P70 to P77, P120, -0.3 to EVDD0 +0.3 and -0.3 to VDD +0.3 V Note 2 P140, P141, P146, P147 VI2 P60 to P63 (N-ch open-drain) VI3 P20 to P27, P121 to P124, P137, -0.3 to +6.5 V -0.3 to VDD +0.3 Note 2 V -0.3 to EVDD0 +0.3 V EXCLK, EXCLKS, RESET Output voltage VO1 P00 to P06, P10 to P17, P30, P31, P40 to P43, P50 to P55, P60 to P63, and -0.3 to VDD +0.3 Note 2 P70 to P77, P120, P130, P140, P141, P146, P147 Analog input voltage VO2 P20 to P27 VAI1 ANI16 to ANI24 -0.3 to VDD +0.3 Note 2 -0.3 to EVDD0 +0.3 and -0.3 to AVREF(+) +0.3 Notes 2, 3 VAI2 ANI0 to ANI7 -0.3 to VDD +0.3 and -0.3 to AVREF(+) +0.3 Notes 2, 3 Note 1. V V V Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. Note 2. Must be 6.5 V or lower. Note 3. Do not exceed AVREF (+) + 0.3 V in case of A/D conversion target pin. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. Remark 2. AVREF (+): + side reference voltage of the A/D converter. Remark 3. VSS: Reference voltage R01DS0246EJ0112 Rev.1.12 Apr 28, 2021 Page 16 of 143 RL78/G1F 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C) Absolute Maximum Ratings Parameter Output current, high (2/2) Symbols IOH1 Conditions Ratings Unit -40 mA Total of all P00 to P04, P40 to P43,P120, P130, P140, P141 -70 mA pins P05, P06, P10 to P17, P30, P31, P50 to P55, P70 -100 mA -170 mA to P77, P146, P147 Per pin P20 to P27 -0.5 mA -2 mA 40 mA Total of all P00 to P04, P40 to P47, P120, P130, P140, P141 70 mA pins P05, P06, P10 to P17, P30, P31, P50 to P55, 100 mA 170 mA P70 to P77, P146, P147 Per pin P20 to P27 1 mA 5 mA -40 to +85 C -65 to +150 C Per pin P00 to P06, P10 to P17, P30, P31, P40 to P43, P50 to P55, P70 to P77, P120, P130, P140, P141, P146, P147 IOH2 Total of all pins Output current, low IOL1 Per pin P00 to P06, P10 to P17, P30, P31, P40-P43, P50 to P55, P60 to P63, P70 to P77, P120, P130, P140, P141, P146, P147 IOL2 Total of all pins Operating ambient tem- TA perature In flash memory programming mode Storage temperature Caution In normal operation mode Tstg Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0246EJ0112 Rev.1.12 Apr 28, 2021 Page 17 of 143 RL78/G1F 2.2 2.2.1 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C) Oscillator Characteristics X1, XT1 characteristics (TA = -40 to +85°C, 1.6 V  EVDD0 = VDD  5.5 V, VSS = 0 V) Resonator X1 clock oscillation frequency Resonator (fX) Note XT1 clock oscillation frequency (fXT) Note Note Conditions MIN. MAX. Unit Ceramic resonator/ 2.7 V VDD 5.5 V 1.0 20.0 MHz crystal resonator 2.4 V VDD