R5F11BLEAFB#30

Datasheet RL78/G1G R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 RENESAS MCU 1. OUTLINE 1.1 Features Ultra-low power consumption technology • VDD = single power supply voltage of 2.7 to 5.5 V • HALT mode • STOP mode • SNOOZE mode RL78 CPU core • CISC architecture with 3-stage pipeline • Minimum instruction execution time: Can be changed from high-speed (0.04167 s: @ 24 MHz operation with high-speed on-chip oscillator) to low-speed (1.0 s: @1 MHz operation with high-speed on-chip oscillator) • Multiply/divide/multiply & accumulate instructions are supported. • Address space: 1 MB • General-purpose registers: (8-bit register  8)  4 banks • On-chip RAM: 1.5 KB Code flash memory • Code flash memory: 8 to 16 KB • Block size: 1 KB • Prohibition of block erase and rewriting (security function) • On-chip debug function • Self-programming (flash shield window function) High-speed on-chip oscillator • Select from 48 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz, 4 MHz, and 1 MHz • High accuracy: ±2.0% Operating ambient temperature • TA = -40 to +85C Power management and reset function • On-chip power-on-reset (POR) circuit • On-chip voltage detector (LVD) (Select interrupt and reset from 6 levels) Timer • 16-bit timer: 7 channels (Timer Array Unit (TAU): 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels) • 12-bit interval timer: 1 channel • Watchdog timer: 1 channel (operable with the dedicated low-speed on-chip oscillator) A/D converter • 8/10-bit resolution A/D converter (VDD = 2.7 to 5.5 V) • Analog input: 8 to 12 channels • Internal reference voltage (1.45 V) and temperature sensorNote Note: Selectable only in HS (high-speed main) mode. Comparator • 2 channels • The voltage from a dedicated 8-bit DAC (resolution of 256 with VDD/AVREFP or VSS/AVREFM as the internally generated reference voltage) can be selected as the reference voltage. Programmable gain amplifier I/O port • I/O port: 26 to 40 • Can be set to N-ch open drain, TTL input buffer, and onchip pull-up resistor • Different potential interface: Can connect to a 2.5/3 V device • On-chip key interrupt function • On-chip clock output/buzzer output controller Others • On-chip BCD (binary-coded decimal) correction circuit Remark: The function mounted depend on the product. See 1.6 Outline of Functions. Event link controller (ELC) • Event signals of 18 to 19 types can be linked to the specified peripheral function. Serial interfaces • CSI: 1 channel • UART: 2 channels • Simplified I2C: 1 channel R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 1 of 67 RL78/G1G 1. OUTLINE ROM, RAM capacities Flash ROM 16 KB 8 KB Note RAM 1.5 KB Note 30 pins 32 pins 44 pins R5F11EAAASP R5F11EBAAFP R5F11EFAAFP R5F11EA8ASP R5F11EB8AFP R5F11EF8AFP This is 630 bytes when the self-programming function is used. R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 2 of 67 RL78/G1G 1.2 1. OUTLINE List of Part Numbers Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G1G P a rt N o . R 5 F 1 1 E A A A X X X S P # 3 0 T y p e o f p a c k in g # 3 0 : T ra y (L S S O P , L Q F P ) # 5 0 : E m b o s s e d ta p e (L S S O P , L Q F P ) P a c k a g e ty p e S P : 0 .6 5 -m m p itc h L S S O P F P : 0 .8 0 -m m p itc h L Q F P R O M c o d e n u m b e r if th e p ro d u c t h a s b e e n p re -p ro g ra m m e d b e fo re s h ip m e n t (O m itte d fo r b la n k p ro d u c ts) F ie ld o f a p p lic a tio n A : C o n s u m e r a p p lic a tio n s, o p e ra tin g a m b ie n t te m p e ra tu re: -4 0 °C to + 8 5 ° C R O M c a p a c ity 8: 8 KB A: 16 KB N u m b e r o f p in s : A : 3 0 -p in B : 3 2 -p in F : 4 4 -p in R L 7 8 /G 1 G g ro u p M e m o ry ty p e : F : F la s h m e m o ry R enesas M C U R e n e s a s s e m ic o n d u c to r p ro d u c t Table 1 - 1 Orderable Part Numbers Pin Count 44 pins Package 44-pin plastic LQFP (10  10 mm) Part Number R5F11EFAAFP#30, R5F11EFAAFP#50 R5F11EF8AFP#30, R5F11EF8AFP#50 32 pins 32-pin plastic LQFP (7  7 mm) R5F11EBAAFP#30, R5F11EBAAFP#50 R5F11EB8AFP#30, R5F11EB8AFP#50 30 pins 30-pin plastic LSSOP (7.62 mm (300)) R5F11EAAASP#30, R5F11EAAASP#50 R5F11EA8ASP#30, R5F11EA8ASP#50 R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 3 of 67 RL78/G1G 1.3 Pin Configuration (Top View) 1.3.1 1. OUTLINE 30-pin products • 30-pin plastic LSSOP (7.62 mm (300), 0.65 mm pitch) P20/ANI0/AV REFP P01/ANI16/TO00 /RxD1/PGAI /(TRJIO0) P00 /ANI17/TI00 /TxD1/CMP0P/(TRJO0) P120/ANI19 /CMP1P Caution RL78/G1G (Top View) P40/TOOL0 RESET P137 /INTP0 P122/X2/EXCLK P121 /X1 REGC V SS VDD P60 P61 P31 /TI03/TO03/INTP4/PCLBUZ0 /SSI00 /(TRJIO0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P21 /ANI1/AVREFM P22 /ANI2 P23 /ANI3 P147 /ANI18 P10 /TRDIOD1 P11 /TRDIOC1 P12 /TRDIOB1 P13 /TRDIOA1 P14 /TRDIOD0 P15 /PCLBUZ1/TRDIOB0 P16 /TI01/TO01/INTP5/TRDIOC0 P17 /TI02/TO02/TRDIOA0/TRDCLK P51 /INTP2/SO00/TxD0/TOOLTxD P50 /INTP1/SI00 /RxD0 /TOOLRxD/SDA 00/(TRJO0) P30 /INTP3/SCK00/SCL00/TRJO0 Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. The functions in parentheses shown in the above figure can be assigned by setting peripheral I/O redirection register 1 (PIOR1). R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 4 of 67 RL78/G1G 1.3.2 32-pin products P10 /TRDIOD1 P11 /TRDIOC1 P12 /TRDIOB 1 P13 /TRDIOA 1 P14 /TRDIOD0 P15 /PCLB UZ1/TRDIOB0 P16 /TI01/TO0 1/INTP 5/TRDIO C0 P17 /TI02/TO0 2/TRDIOA 0/TRDCL K • 32-pin plastic LQFP (7 × 7 mm, 0.8 mm pitch) 25 26 27 28 29 30 31 32 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 RL78/G1G (Top View) Caution P51/INTP2/SO00 /TxD0 /TOOLTxD P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/(TRJO0 ) P30/INTP3/SCK00/SCL00 /TRJO0 P70 P31/TI03 /TO03/INTP4 /PCLBUZ0/(TRJIO0) P62/SSI00 P61 P60 VSS V DD P147 /ANI18 P23/ANI3 P22/ANI2 P21/ANI1 /AV REFM P20/ANI0/AV REFP P01 /ANI16/TO00/RxD1/PGAI/TRJIO0 P00 /ANI17/TI00 /TxD1/CMP0P/(TRJO0) P120/ANI19 /CMP1P P 40/TO OL0 RESE T P 137/INTP0 P 122/X2/EXCLK P 121/X1 REG C 1. OUTLINE Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. The functions in parentheses shown in the above figure can be assigned by setting peripheral I/O redirection register 1 (PIOR1). R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 5 of 67 RL78/G1G 1.3.3 44-pin products P147/ANI18 P146 P10/TRDIOD1 P11/TRDIOC1 P12/TRDIOB1 P13/TRDIOA1 P14/TRDIOD0 P15/PCLBUZ1/TRDIOB0 P16/TI01/TO01/INTP5/TRDIOC0 P17/TI02/TO02/TRDIOA0/TRDCLK P51/INTP2/SO00/TxD0/TOOLTxD • 44-pin plastic LQFP (10 × 10 mm, 0.8 mm pitch) P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AV REFM P20/ANI0/AV REFP P01/TO00/RxD1/PGA I/ANI16/TRJIO0 P00/TI00/TxD1/CMP0P/ANI17/(TRJO0) P120/ANI19/CMP1P 34 35 36 37 38 39 40 41 42 43 44 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11 RL78/G1G (Top View) P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/(TRJO0) P30/INTP3/SCK00/SCL00/TRJO0 P70/KR0 P71/KR1 P72/KR2 P73/KR3 P31/TI03/TO03/INTP4/PCLBUZ0/(TRJIO0) P63 P62/SSI00 P61 P60 P41/(TRJIO0) P40/TOOL0 RESET P124 P123 P137/INTP0 P122/X2/EXCLK P121/X1 REGC V SS VDD 1. OUTLINE Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. The functions in parentheses shown in the above figure can be assigned by setting peripheral I/O redirection register 1 (PIOR1). R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 6 of 67 RL78/G1G 1.4 1. OUTLINE Pin Identification ANI0 to ANI7, ANI16 to ANI19:Analog input AVREFM: A/D converter reference potential (- side) input AVREFP: A/D converter reference potential (+ side) input EXCLK: External clock input (main system clock) INTP0 to INTP5: External interrupt input KR0 to KR3: Key Return P00, P01: Port 0 P10 to P17: Port 1 P20 to P27: Port 2 P30, P31: Port 3 P40, P41: Port 4 P50, P51: Port 5 P60 to P63: Port 6 P70 to P73: Port 7 P120 to P124: Port 12 P137: Port 13 P146, P147: Port 14 PCLBUZ0, PCLBUZ1: Programmable clock output/buzzer output REGC: Regulator capacitance RESET: Reset RxD0, RxD1: Receive data SCK00: Serial clock input/output SCL00: Serial clock output SDA00: Serial data input/output SI00: Serial data input SO00: Serial data output SSI00: Serial interface chip select input TI00 to TI03: Timer input TO00 to TO03, TRJO0: Timer output TOOL0: Data input/output for tool TOOLRxD, TOOLTxD: Data input/output for external device TRDCLK: Timer external input clock TRDIOA0, TRDIOB0, TRDIOC0, TRDIOD0,:Timer input/output TRDIOA1, TRDIOB1, TRDIOC1, TRDIOD1, TRJIO0 TxD0, TxD1: Transmit data CMP0P, CMP1P: Comparator input PGAI: PGA input VDD: Power supply VSS: Ground X1, X2: Crystal oscillator (main system clock) R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 7 of 67 RL78/G1G 1.5 1.5.1 1. OUTLINE Block Diagram 30-pin products TIMER ARRAY UNIT (4ch) TI00/P00 TO00/P01 ch0 TI01/TO01/P16 ch1 TI02/TO02/P17 ch2 TI03/TO03/P31 RxD0/P50 ch3 2 P00, P01 PORT 1 8 P10 to P17 PORT 2 4 P20 to P23 PORT 3 2 P30, P31 PORT 4 TIMER RD (2ch) TRDIOA0/TRDCLK/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 3 ch0 TRDIOA1/P13 toTRDIOD1/P10 4 ch1 WINDOW WATCHDOG TIMER PORT 5 2 P50, P51 PORT 6 2 P60, P61 2 P120 P121, P122 PORT 12 PORT 13 10-bit A/D CONVERTER SERIAL ARRAY UNIT0 (4ch) UART0 RxD1/P01 TxD1/P00 UART1 SCK00/P30 SI00/P50 SO00/P51 SSI00/P31 CSI00 SCL00/P30 SDA00/P50 IIC00 P137 PORT 14 12- BIT INTERVAL TIMER RxD0/P50 TxD0/P51 P40 TRJIO0/P01 TIMER RJ TRJO0/P30 LOW-SPEED ON-CHIP OSCILLATOR PORT 0 P147 4 ANI0/P20 to ANI3/P23 4 ANI16/P01, ANI17/P00, ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 RL78 CPU CORE MULTIPLIER & DIVIDER, MULTIPLYACCUMULATOR CODE FLASH MEMORY POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RAM RESET CONTROL ON-CHIP DEBUG VDD VSS BUZZER OUTPUT CLOCK OUTPUT CONTROL 2 TOOLRxD/P50, TOOLTxD/P51 PCLBUZ0/P31, PCLBUZ1/P15 TOOL0/P40 SYSTEM CONTROL RESET HIGH-SPEED ON-CHIP OSCILLATOR X1/P121 X2/EXCLK/P122 VOLTAGE REGULATOR REGC INTP0/P137 EVENT LINK CONTROLLER BCD ADJUSTMENT INTERRUPT CONTROL 2 2 INTP1/P50, INTP2/P51 INTP3/P30, INTP4/P31 INTP5/P16 CMP (2ch) CMP0 CMP0P/P00 CMP1 CMP1P/P120 PGA PGAI/P01 PWM OPTION UNIT R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 8 of 67 RL78/G1G 1.5.2 1. OUTLINE 32-pin products TIMER ARRAY UNIT (4ch) TI00/P00 TO00/P01 ch0 TI01/TO01/P16 ch1 TI02/TO02/P17 ch2 TI03/TO03/P31 RxD0/P50 ch3 2 P00, P01 PORT 1 8 P10 to P17 PORT 2 4 P20 to P23 PORT 3 2 P30, P31 PORT 4 TIMER RD (2ch) TRDIOA0/TRDCLK/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 3 ch0 TRDIOA1/P13 toTRDIOD1/P10 4 ch1 P40 PORT 5 2 P50, P51 PORT 6 3 P60 to P62 2 P120 P121, P122 TRJIO0/P01 TIMER RJ TRJO0/P30 LOW-SPEED ON-CHIP OSCILLATOR PORT 0 WINDOW WATCHDOG TIMER PORT 7 PORT 12 P70 PORT 13 12- BIT INTERVAL TIMER P137 PORT 14 SERIAL ARRAY UNIT0 (4ch) RxD0/P50 TxD0/P51 UART0 RxD1/P01 TxD1/P00 UART1 SCK00/P30 SI00/P50 SO00/P51 SSI00/P62 CSI00 SCL00/P30 SDA00/P50 IIC00 10-bit A/D CONVERTER P147 4 ANI0/P20 to ANI3/P23 4 ANI16/P01, ANI17/P00, ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 RL78 CPU CORE MULTIPLIER & DIVIDER, MULTIPLYACCUMULATOR CODE FLASH MEMORY POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RAM RESET CONTROL ON-CHIP DEBUG VDD VSS BUZZER OUTPUT CLOCK OUTPUT CONTROL 2 TOOLRxD/P50, TOOLTxD/P51 PCLBUZ0/P31, PCLBUZ1/P15 TOOL0/P40 SYSTEM CONTROL RESET HIGH-SPEED ON-CHIP OSCILLATOR X1/P121 X2/EXCLK/P122 VOLTAGE REGULATOR REGC INTP0/P137 EVENT LINK CONTROLLER BCD ADJUSTMENT INTERRUPT CONTROL 2 2 INTP1/P50, INTP2/P51 INTP3/P30, INTP4/P31 INTP5/P16 CMP (2ch) CMP0 CMP0P/P00 CMP1 CMP1P/P120 PGA PGAI/P01 PWM OPTION UNIT R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 9 of 67 RL78/G1G 1.5.3 1. OUTLINE 44-pin products TIMER ARRAY UNIT (4ch) TI00/P00 TO00/P01 ch0 TI01/TO01/P16 ch1 TI02/TO02/P17 ch2 TI03/TO03/P31 RxD0/P50 ch3 TIMER RD (2ch) TRDIOA0/TRDCLK/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 3 ch0 TRDIOA1/P13 toTRDIOD1/P10 4 ch1 2 P00, P01 PORT 1 8 P10 to P17 PORT 2 8 P20 to P27 PORT 3 2 P30, P31 PORT 4 2 P40, P41 PORT 5 2 P50, P51 PORT 6 4 P60 to P63 PORT 7 4 P70 to P73 4 P120 P121 to P124 TRJIO0/P01 TIMER RJ TRJO0/P30 LOW-SPEED ON-CHIP OSCILLATOR PORT 0 WINDOW WATCHDOG TIMER PORT 12 PORT 13 12- BIT INTERVAL TIMER PORT 14 SERIAL ARRAY UNIT0 (4ch) RxD0/P50 TxD0/P51 UART0 RxD1/P01 TxD1/P00 UART1 SCK00/P30 SI00/P50 SO00/P51 SSI00/P62 CSI00 SCL00/P30 SDA00/P50 IIC00 10-bit A/D CONVERTER P137 2 P146, P147 8 ANI0/P20 to ANI7/P27 4 ANI16/P01, ANI17/P00, ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 RL78 CPU CORE MULTIPLIER & DIVIDER, MULTIPLYACCUMULATOR CODE FLASH MEMORY KEY RETURN 4 POWER ON RESET/ VOLTAGE DETECTOR KR0/P70 to KR3/P73 POR/LVD CONTROL RAM RESET CONTROL ON-CHIP DEBUG VDD VSS BUZZER OUTPUT CLOCK OUTPUT CONTROL 2 TOOLRxD/P50, TOOLTxD/P51 PCLBUZ0/P31, PCLBUZ1/P15 TOOL0/P40 SYSTEM CONTROL RESET HIGH-SPEED ON-CHIP OSCILLATOR X1/P121 X2/EXCLK/P122 VOLTAGE REGULATOR REGC INTP0/P137 EVENT LINK CONTROLLER BCD ADJUSTMENT INTERRUPT CONTROL 2 2 INTP1/P50, INTP2/P51 INTP3/P30, INTP4/P31 INTP5/P16 CMP (2ch) CMP0 CMP0P/P00 CMP1 CMP1P/P120 PGA PGAI/P01 PWM OPTION UNIT R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 10 of 67 RL78/G1G 1.6 1. OUTLINE Outline of Functions [30-pin, 32-pin, 44-pin products (code flash memory 8 KB to 16 KB)] Caution The above outline of the functions applies when peripheral I/O redirection register 1 (PIOR1) is set to 00H. (1/2) Item 30-pin 32-pin 44-pin R5F11EA8ASP, R5F11EB8AFP, R5F11EF8AFP, R5F11EAAASP R5F11EBAAFP R5F11EFAAFP Code flash memory (KB) 8 to 16 RAM (KB) 1.5 Address space 1 MB Main system High-speed system X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) clock clock LS (low-speed main) mode: 1 to 8 MHz (VDD = 2.7 to 5.5 V), HS (high-speed main) mode: 1 to 20 MHz (VDD = 2.7 to 5.5 V) High-speed on-chip LS (low-speed main) mode: 1 to 8 MHz (VDD = 2.7 to 5.5 V) oscillator clock (fIH) HS (high-speed main) mode: 1 to 24 MHz (VDD = 2.7 to 5.5 V) Low-speed on-chip oscillator clock 15 kHz (TYP.): VDD = 2.7 to 5.5 V General-purpose register 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution 0.04167 s (High-speed on-chip oscillator clock: fIH = 24 MHz operation) time 0.05 s (High-speed system clock: fMX = 20 MHz operation) Instruction set • Data transfer (8/16 bits) • Adder and subtractor/logical operation (8/16 bits) • Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits) • Multiplication and Accumulation (16 bits × 16 bits + 32 bits) • Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. I/O port Total 26 28 40 CMOS I/O 23 25 35 CMOS input 3 3 5 CMOS output — N-ch open-drain I/O — (6 V tolerance) Timer 16-bit timer 7 channels (TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels) Watchdog timer 1 channel 12-bit interval timer 1 channel Timer output Timer outputs: 14 channels PWM outputs: 9 channels Caution Since a library is used when rewriting the flash memory using the user program, flash ROM and RAM areas are used. Refer to the RL78 Family Flash Self-Programming Library Type01 User’s Manual before using these products. R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 11 of 67 RL78/G1G 1. OUTLINE (2/2) Item 30-pin 32-pin 44-pin R5F11EA8ASP, R5F11EB8AFP, R5F11EF8AFP, R5F11EAAASP R5F11EBAAFP R5F11EFAAFP Clock output/buzzer output 2 • 2.44 kHz, 4.88 kHz, 9.77 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) 8/10-bit resolution A/D converter 8 channels 12 channels Comparator 2 channels PGA 1 channel Serial interface • CSI: 1 channel/UART0: 1 channel/simplified I2C: 1 channel • UART1: 1 channel Event link controller (ELC) Event input: 18 Event input: 19 Event trigger output: 6 Vectored Internal interrupt External Event trigger output: 6 20 sources Key interrupt Reset 6 7 — 4 • Reset by RESET pin • Internal reset by watchdog timer • Internal reset by power-on-reset • Internal reset by voltage detector • Internal reset by illegal instruction execution Note • Internal reset by RAM parity error • Internal reset by illegal-memory access Power-on-reset circuit • Power-on-reset: 1.51 ±0.03 V • Power-down-reset: 1.50 ±0.03 V Voltage detector 2.75 V to 4.06 V (6 stages) On-chip debug function Provided Power supply voltage VDD = 2.7 to 5.5 V Operating ambient temperature TA = -40 to +85°C Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip debug emulator. R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 12 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS 2. ELECTRICAL SPECIFICATIONS Caution 1. The RL78 microcontroller has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. Caution 2. The pins mounted are as follows according to product. 2.1 Pins Mounted According to Product 2.1.1 Port functions Refer to 2.1.1 30-pin products, 2.1.2 32-pin products, and 2.1.3 44-pin products in the RL78/G1G User’s Manual. 2.1.2 Non-port functions Refer to 2.2.1 With functions for each product in the RL78/G1G User’s Manual. R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 13 of 67 RL78/G1G 2.2 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Absolute Maximum Ratings Parameter (1/2) Symbol Supply voltage VDD REGC pin input voltage VIREGC Conditions REGC Ratings Unit -0.5 to +6.5 V -0.3 to +2.8 V and -0.3 to VDD +0.3 Note 1 Input voltage VI1 P00, P01, P10 to P17, P20 to P27, P30, -0.3 to VDD +0.3 Note 2 V -0.3 to VDD +0.3 Note 2 V P31, P40, P41, P50, P51, P60 to P63, P70 to P73, P120, P121 to P124, P137, P146, P147, EXCLK, RESET Output voltage VO1 P00, P01, P10 to P17, P20 to P27, P30, P31, P40, P41, P50, P51, P60 to P63, P70 to P73, P120, P146, P147 Analog input voltage VAI1 ANI0 to ANI7, ANI16 to ANI19 -0.3 to VDD +0.3 Notes 2, 3 and -0.3 to AVREF (+) +0.3 Note 1. V Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. Note 2. Must be 6.5 V or lower. Note 3. Do not exceed AVREF (+) + 0.3 V in case of A/D conversion target pin. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. Remark 2. AVREF (+): + side reference voltage of the A/D converter. Remark 3. VSS: Reference voltage R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 14 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Parameter Output current, high (2/2) Symbol IOH1 Conditions Ratings Unit -40 mA Total of all P00, P01, P40, P41, P120 -70 mA pins P10 to P17, P30, P31, P50, P51, P60 to P63, P70 -100 mA -170 mA to P73, P146, P147 Per pin P20 to P27 -0.5 mA -2 mA 40 mA Total of all P00, P01, P40, P41, P120 70 mA pins P10 to P17, P30, P31, P50, P51, P60 to P63, P70 100 mA 170 mA to P73, P146, P147 Per pin P20 to P27 1 mA 5 mA -40 to +85 C -65 to +150 C Per pin P00, P01, P10 to P17, P30, P31, P40, P41, P50, P51, P60 to P63, P70 to P73, P120, P146, P147 IOH2 Total of all pins Output current, low IOL1 Per pin P00, P01, P10 to P17, P30, P31, P40, P41, P50, P51, P60 to P63, P70 to P73, P120, P146, P147 IOL2 Total of all pins Operating ambient TA temperature Storage temperature Caution In normal operation mode In flash memory programming mode Tstg Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 15 of 67 RL78/G1G 2.3 2.3.1 2. ELECTRICAL SPECIFICATIONS Oscillator Characteristics X1 oscillator characteristics (TA = -40 to +85°C, 2.7 V  VDD  5.5 V, VSS = 0 V) Parameter X1 clock oscillation frequency Resonator (fX) Note Ceramic resonator/ Conditions MIN. 2.7 V VDD 5.5 V 1.0 TYP. MAX. Unit 20.0 MHz crystal resonator Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark 2.3.2 When using the X1 oscillator, refer to 5.4 System Clock Oscillator in the RL78/G1G User’s Manual. On-chip oscillator characteristics (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V) Oscillators Parameters Conditions MIN. TYP. MAX. Unit MHz High-speed on-chip oscillator fIH 1 24 clock frequency Notes 1, 2 fHOCO 1 48 -2 +2 High-speed on-chip oscillator % clock frequency accuracy Low-speed on-chip oscillator 15 fIL kHz clock frequency Low-speed on-chip oscillator -15 +15 % clock frequency accuracy Note 1. High-speed on-chip oscillator frequency is selected with bits 0 to 4 of the option byte (000C2H) and bits 0 to 2 of the HOCODIV register. Note 2. This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time. R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 16 of 67 RL78/G1G 2.4 2.4.1 2. ELECTRICAL SPECIFICATIONS DC Characteristics Pin characteristics (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V) Items Output current, high Symbol Note 1 IOH1 Conditions Per pin for P00, P01, P10 to P17, MIN. TYP. 2.7 V  VDD  5.5 V P30, P31, P40, P41, P50, P51, MAX. Unit -10.0 mA Note 2 P60 to P63, P70 to P73, P120, P146, P147 Total of P00, P01, P40, P41, P120 4.0 V  VDD  5.5 V -55.0 mA (When duty  70% Note 3) 2.7 V  VDD < 4.0 V -10.0 mA Total of P10 to P17, P30, P31, 4.0 V  VDD  5.5 V -80.0 mA 2.7 V  VDD < 4.0 V -19.0 mA 2.7 V  VDD  5.5 V -135.0 mA -0.1 mA P50, P51, P60 to P63, P70 to P73, P146, P147 (When duty  70% Note 3) Total of all pins (When duty  70% Note 3) IOH2 Per pin for P20 to P27 2.7 V  VDD  5.5 V Note 2 Total of all pins 2.7 V  VDD  5.5 V -1.5 mA (When duty  70% Note 3) Note 1. Value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an output pin. Note 2. Do not exceed the total current value. Note 3. Specification under conditions where the duty factor  70%. The output current value that has changed to the duty factor  70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). • Total output current of pins = (IOH × 0.7)/(n × 0.01) Where n = 80% and IOH = -10.0 mA Total output current of pins = (-10.0 × 0.7)/(80 × 0.01)  -8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Caution P00, P10, P15, P17, P30, P50, P51 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 17 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V) Items Output current, low Note 1 Symbol IOL1 Conditions MIN. TYP. MAX. Unit Per pin for P00, P01, P10 to P17, 20.0 mA P30, P31, P40, P41, P50, P51, Note 2 P60 to P63, P70 to P73, P120, P146, P147 Total of P00, P01, P40, P41, P120 4.0 V  VDD  5.5 V 70.0 mA (When duty  70% Note 3) 2.7 V  VDD < 4.0 V 15.0 mA Total of P10 to P17, P30, P31, 4.0 V  VDD  5.5 V 80.0 mA P50, P51, P60 to P63, P70 to 2.7 V  VDD < 4.0 V 35.0 mA 150.0 mA 0.4 mA P73, P146, P147 (When duty  70% Note 3) Total of all pins (When duty  70% Note 3) IOL2 Per pin for P20 to P27 Note 2 Total of all pins 2.7 V  VDD  5.5 V 5.0 mA (When duty  70% Note 3) Note 1. Value of current at which the device operation is guaranteed even if the current flows from an output pin to the VSS pin. Note 2. However, do not exceed the total current value. Note 3. Specification under conditions where the duty factor  70%. The output current value that has changed to the duty factor  70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). • Total output current of pins = (IOL × 0.7)/(n × 0.01) Where n = 80% and IOL = 10.0 mA Total output current of pins = (10.0 × 0.7)/(80 × 0.01)  8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 18 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V) Items Input voltage, high Symbol VIH1 Conditions MIN. P00, P01, P10 to P17, P30, P31, Normal input buffer TYP. MAX. Unit 0.8 VDD VDD V 2.2 VDD V 2.0 VDD V 1.50 VDD V P40, P41, P50, P51, P60 to P63, P70 to P73, P120 to P124, P146, P147 VIH2 P01, P10, P15 to P17, P30, P31, TTL input buffer P50 4.0 V  VDD  5.5 V TTL input buffer 3.3 V  VDD < 4.0 V TTL input buffer 2.7 V  VDD < 3.3 V Input voltage, low VIH3 P20 to P27 0.7 VDD VDD V VIH4 EXCLK, RESET 0.8 VDD VDD V VIL1 P00, P01, P10 to P17, P30, P31, Normal input buffer 0 0.2 VDD V 0 0.8 V 0 0.5 V 0 0.32 V P40, P41, P50, P51, P60 to P63, P70 to P73, P120 to P124, P146, P147 VIL2 P01, P10, P15 to P17, P30, P31, TTL input buffer P50 4.0 V  VDD  5.5 V TTL input buffer 3.3 V  VDD < 4.0 V TTL input buffer 2.7 V  VDD < 3.3 V Caution VIL3 P20 to P27 0 0.3 VDD V VIL4 EXCLK, RESET 0 0.2 VDD V The maximum value of VIH of pins P00, P10, P15, P17, P30, P50, and P51 is VDD, even in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 19 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V) Items Output voltage, high Symbol VOH1 Conditions P00, P01, P10 to P17, P30, P31, 4.0 V  VDD  5.5 V, MIN. TYP. MAX. Unit VDD - 1.5 V VDD - 0.7 V VDD - 0.6 V VDD - 0.5 V VDD - 0.5 V P40, P41, P50, P51, P60 to P63, IOH1 = -10.0 mA P70 to P73, P120, P146, P147 4.0 V  VDD  5.5 V, IOH1 = -3.0 mA 2.7 V  VDD  5.5 V, IOH1 = -2.0 mA 2.7 V  VDD  5.5 V, IOH1 = -1.0 mA VOH2 P20 to P27 2.7 V  VDD  5.5 V, IOH2 = -100 A Output voltage, low VOL1 P00, P01, P10 to P17, P30, P31, 4.0 V  VDD  5.5 V, 1.3 V 0.7 V 0.6 V 0.4 V 0.4 V 0.4 V P40, P41, P50, P51, P60 to P63, IOL1 = 20.0 mA P70 to P73, P120, P146, P147 4.0 V  VDD  5.5 V, IOL1 = 8.5 mA 2.7 V  VDD  5.5 V, IOL1 = 3.0 mA 2.7 V  VDD  5.5 V, IOL1 = 1.5 mA 2.7 V  VDD  5.5 V, IOL1 = 0.3 mA VOL2 P20 to P27 2.7 V  VDD  5.5 V, IOL2 = 400 A Caution P00, P10, P15, P17, P30, P50, and P51 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 20 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V) Items Input leakage Symbol ILIH1 Conditions P00, P01, P10 to P17, P20 to MIN. TYP. VI = VDD MAX. Unit 1 A 1 A 10 A -1 A -1 A -10 A 100 k P27, P30, P31, P40, P41, P50, current, high P51, P60 to P63, P70 to P73, P120, P123, P124, P137, P146, P147, RESET ILIH2 P121, P122 (X1, X2, EXCLK) VI = VDD In input port or external clock input In resonator connection Input leakage ILIL1 P00, P01, P10 to P17, P20 to VI = VSS P27, P30, P31, P40, P41, P50, current, low P51, P60 to P63, P70 to P73, P120, P123, P124, P137, P146, P147, RESET ILIL2 P121, P122 (X1, X2, EXCLK) VI = VSS In input port or external clock input In resonator connection On-chip pull-up RU P00, P01, P10 to P17, P30, P31, VI = VSS, in input port 10 20 P40, P41, P50, P51, P60 to P63, resistance P70 to P73, P120, P146, P147 Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 21 of 67 RL78/G1G 2.4.2 2. ELECTRICAL SPECIFICATIONS Supply current characteristics (1) Flash ROM: 16 KB of 30- pin to 44-pin products (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V) Parameter Symbol Supply current IDD1 (1/2) Conditions Operating HS (high-speed mode Note 1 fHOCO = 48 MHz, Basic main) mode Notes 3, 4 fIH = 24 MHz HS (high-speed MIN. VDD = 5.0 V 1.8 operation VDD = 3.0 V 1.8 fHOCO = 48 MHz, Normal main) mode Notes 3, 4 fIH = 24 MHz LS (low-speed main) fIH = 8 MHz mode 3.9 6.9 3.9 6.9 VDD = 5.0 V 3.7 6.3 operation VDD = 3.0 V 3.7 6.3 VDD = 5.0 V 2.8 4.6 operation VDD = 3.0 V 2.8 4.6 Normal VDD = 3.0 V 1.2 2.0 mA Square wave input mA HS (high-speed fMX = 20 MHz, Normal 3.1 5.3 main) mode Notes 2, 4 VDD = 5.0 V operation Resonator connection 3.3 5.5 fMX = 20 MHz, Normal 3.1 5.3 VDD = 3.0 V operation Resonator connection 3.3 5.5 fMX = 10 MHz, Normal 2.0 3.1 VDD = 5.0 V operation Resonator connection 2.0 3.2 fMX = 10 MHz, Normal 2.0 3.1 VDD = 3.0 V operation Resonator connection 2.0 3.2 1.2 1.9 1.2 2.0 mode Notes 2, 4 mA operation Notes 3, 4 LS (low-speed main) fMX = 8 MHz, Note 1. mA VDD = 5.0 V fHOCO = 16 MHz, Normal fIH = 16 MHz MAX. Unit operation VDD = 3.0 V fHOCO = 24 MHz, Normal fIH = 24 MHz TYP. VDD = 3.0 V Normal Square wave input Square wave input Square wave input Square wave input operation Resonator connection mA Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, comparator, programmable gain amplifier, watchdog timer, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors. Note 2. When high-speed on-chip oscillator is stopped. Note 3. When high-speed system clock is stopped. Note 4. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high speed main) mode: VDD = 2.7 V to 5.5 V@1 MHz to 24 MHz LS (low speed main) mode: VDD = 2.7 V to 5.5 V@1 MHz to 8 MHz Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (48 MHz max.) Remark 3. fIH: High-speed on-chip oscillator clock frequency (24 MHz max.) Remark 4. Temperature condition of the TYP. value is TA = 25°C R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 22 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS (1) Flash ROM: 16 KB of 30-pin to 44-pin products (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V) Parameter Symbol Supply IDD2 current Note 2 (2/2) Conditions HALT mode HS (high-speed fHOCO = 48 MHz, main) mode Notes 4, 6 fIH = 24 MHz Note 1 main) mode Unit 2.40 mA VDD = 3.0 V 0.60 2.40 VDD = 5.0 V 0.40 1.83 fIH = 24 MHz VDD = 3.0 V 0.40 1.83 fHOCO = 16 MHz, VDD = 5.0 V 0.38 1.38 fIH = 16 MHz VDD = 3.0 V 0.38 1.38 VDD = 3.0 V 260 710 A Notes 3, 6 fMX = 20 MHz, Square wave input 0.28 1.55 mA VDD = 5.0 V Resonator connection 0.42 1.74 fMX = 20 MHz, Square wave input 0.28 1.55 VDD = 3.0 V Resonator connection 0.42 1.74 fMX = 10 MHz, Square wave input 0.19 0.86 VDD = 5.0 V Resonator connection 0.27 0.93 fMX = 10 MHz, Square wave input 0.19 0.86 VDD = 3.0 V Resonator connection 0.27 0.93 LS (low-speed main) fMX = 8 MHz, Square wave input 95 550 Resonator connection 145 590 TA = -40C 0.18 0.51 mode Note 5 TA = +25C 0.24 0.51 TA = +50C 0.29 1.10 TA = +70C 0.41 1.90 TA = +85C 0.90 3.30 mode Note 1. MAX. 0.60 Notes 4, 6 HS (high-speed IDD3 MIN. fHOCO = 24 MHz, LS (low-speed main) fIH = 8 MHz mode TYP. VDD = 5.0 V STOP Notes 3, 6 VDD = 3.0 V A A Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, comparator, programmable gain amplifier, watchdog timer, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors. Note 2. During HALT instruction execution by flash memory. Note 3. When high-speed on-chip oscillator is stopped. Note 4. When high-speed system clock is stopped. Note 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When watchdog timer is stopped. The values below the MAX. column include the leakage current. Note 6. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high speed main) mode: VDD = 2.7 V to 5.5 V@1 MHz to 24 MHz LS (low speed main) mode: VDD = 2.7 V to 5.5 V@1 MHz to 8 MHz Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (48 MHz max.) Remark 3. fIH: High-speed on-chip oscillator clock frequency (24 MHz max.) Remark 4. Temperature condition of the TYP. value is TA = 25°C R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 23 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS (2) Peripheral Functions (Common to all products) (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V) Parameter 12-bit interval timer Symbol Conditions MIN. TYP. MAX. Unit 0.02 A fIL = 15 kHz 0.22 A When conversion Normal mode, AVREFP = VDD = 5.0 V 1.3 1.7 mA at maximum 0.5 0.7 mA IIT Notes 1, 8 operating current Watchdog timer IWDT operating current Notes 1, 2 A/D converter IADC Note 3 operating current Low voltage mode, AVREFP = VDD = 3.0 V speed A/D converter IADREF 75 A ITMPS 75 A reference voltage current Temperature sensor operating current Comparator operating ICMP Note 4 current Per channel of When the comparator is operating 45.0 65.0 comparator 1 When the comparator is stopped 0.0 0.1 Programmable gain When the programmable gain amplifier is operating 240.0 340.0 0.0 0.1 IPGA Note 5 amplifier operating When the programmable gain amplifier is stopped A A current LVD operating current ILVI Note 6 SNOOZE operating ISNOZ current A 0.08 ADC operation The mode is performed Note 7 The A/D conversion Low voltage mode operations are 0.50 0.60 mA 1.20 1.44 mA 0.70 0.84 mA AVREFP = VDD = 3.0 V performed CSI/UART operation Note 1. When high speed on-chip oscillator and high-speed system clock are stopped. Note 2. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The current value of the RL78 microcontroller is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer operates in STOP mode. Note 3. Current flowing only to the A/D converter. The current value of the RL78 microcontroller is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. Note 4. Current flowing only to the comparator. The current value of the RL78 microcontroller is the sum of IDD1 or IDD2 and ICMP when the comparator operates in operating mode or HALT mode. Note 5. Current flowing only to the programmable gain amplifier. The current value of the RL78 microcontroller is the sum of IDD1 or IDD2 and IPGA when the programmable gain amplifier operates in operating mode or HALT mode. Note 6. Current flowing only to the LVD circuit. The current value of the RL78 microcontroller is the sum of IDD1, IDD2 or IDD3 and ILVI when the LVD circuit operates in the Operating, HALT or STOP mode. Note 7. For details on the transition time to SNOOZE mode, refer to 18.3.3 SNOOZE mode in the RL78/G1G User’s Manual. Note 8. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator). The supply current of the RL78 microcontroller is the sum of the values of either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fCLK: CPU/peripheral hardware clock frequency Remark 3. Temperature condition of the TYP. value is TA = 25°C R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 24 of 67 RL78/G1G 2.5 2. ELECTRICAL SPECIFICATIONS AC Characteristics 2.5.1 Basic operation (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V) Items Instruction cycle (minimum Symbol TCY instruction execution time) Conditions Main system HS (high-speed 2.7 V  VDD  5.5 V clock (fMAIN) main) mode operation LS (low-speed 2.7 V  VDD  5.5 V MIN. TYP. MAX. Unit 0.04167 1 s 0.125 1 s 0.04167 1 s 0.125 1 s 20.0 MHz main) mode In the self HS (high-speed 2.7 V  VDD  5.5 V programming main) mode mode LS (low-speed 2.7 V  VDD  5.5 V main) mode fEX 2.7 V  VDD  5.5 V 1.0 External main system clock tEXH, 2.7 V  VDD  5.5 V 24 ns input high-level width, tEXL 1/fMCK + ns External main system clock frequency low-level width TI00 to TI03 input high-level tTIH, tTIL width, low-level width 10 Timer RJ input cycle fC TRJIO 2.7 V  VDD  5.5 V 100 ns Timer RJ input high-level fWH, fWL TRJIO 2.7 V  VDD  5.5 V 40 ns fTO HS (high-speed main) mode 4.0 V  VDD  5.5 V 12 MHz 2.7 V  VDD < 4.0 V 8 MHz LS (low-speed main) mode 2.7 V  VDD  5.5 V 4 MHz HS (high-speed main) mode 4.0 V  VDD  5.5 V 16 MHz 2.7 V  VDD < 4.0 V 8 MHz 4 MHz width, low-level width TO00 to TO03, TRJIO0,TRJO, TRDIOA0/1, TRDIOB0/1, TRDIOC0/1,TRDIOD0/1 output frequency PCLBUZ0, PCLBUZ1 fPCL output frequency Interrupt input high-level tINTH, width, low-level width tINTL Key interrupt input tKR LS (low-speed main) mode 2.7 V  VDD  5.5 V INTP0 to INTP5 2.7 V  VDD  5.5 V 1 s KR0-KR3 2.7 V  VDD  5.5 V 250 ns 10 s low-level width RESET low-level width Remark tRSL fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKSmn bit of timer mode register mn (TMRmn). m: Unit number (m = 0), n: Channel number (n = 0 to 3)) R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 25 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) 10 1.0 Cycle time TCY [µs] When the high-speed on-chip oscillator clock is selected During self-programming When high-speed system clock is selected 0.1 0.05 0.04167 0.01 0 1.0 2.0 3.0 2.7 4.0 5.0 5.5 6.0 Supply voltage VDD [V] R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 26 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS TCY vs VDD (LS (low-speed main) mode) 10 When the high-speed on-chip oscillator clock is selected Cycle time TCY [µs] 1.0 During self-programming When high-speed system clock is selected 0.125 0.1 0.01 0 1.0 2.0 3.0 4.0 5.0 5.5 6.0 2.7 Supply voltage VDD [V] R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 27 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL External System Clock Timing 1/fEX tEXL tEXH EXCLK TI/TO Timing tTIL tTIH TI00 to TI03 1/fTO TO00 to TO03 TRJIO0, TRJO0, TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 28 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS tTJIH tTJIL TRJIO tTDIL tTDIH TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 tTDSIL INTP0 R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 29 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS Interrupt Request Input Timing tINTL tINTH INTP0 to INTP5 Key Interrupt Input Timing tKR KR0 to KR3 RESET Input Timing tRSL RESET R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 30 of 67 RL78/G1G 2.6 2. ELECTRICAL SPECIFICATIONS Peripheral Functions Characteristics AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL 2.6.1 Serial array unit (1) During communication at same potential (UART mode) (TA = -40 to +85C, 2.7 V  5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) LS (low-speed main) Mode Mode MIN. Transfer rate Note 1 2.7 V  VDD  5.5 V Theoretical value of the maximum MAX. MIN. Unit MAX. fMCK/6 fMCK/6 bps 4.0 1.3 Mbps transfer rate fMCK = fCLK Note 2 UART mode connection diagram (during communication at same potential) TxDq Rx RL78 microcontroller User’s device RxDq Tx UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Note 1. Transfer rate in the SNOOZE mode is 4800 bps only. However, the SNOOZE mode cannot be used when FRQSEL4 = 1. Note 2. Caution The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V  VDD  5.5 V) LS (low-speed main) mode: 8 MHz (2.7 V  VDD  5.5 V) Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. q: UART number (q = 0, 1), g: PIM and POM number (g = 0, 5) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03)) R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 31 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. SCKp cycle time tKCY1 tKCY1  2/fCLK SCKp high-/low-level width tKH1, tKL1 SIp setup time (to SCKp↑) Note 1 tSIK1 2.7 V  VDD  5.5 V MAX. LS (low-speed main) mode MIN. Unit MAX. 83.3 250 ns 4.0 V  VDD  5.5 V tKCY1/2 - 7 tKCY1/2 - 50 ns 2.7 V  VDD  5.5 V tKCY1/2 - 10 tKCY1/2 - 50 ns 4.0 V  VDD  5.5 V 23 110 ns 2.7 V  VDD  5.5 V 33 110 ns 10 10 ns SIp hold time (from SCKp↑) Note 2 tKSI1 2.7 V  VDD  5.5 V Delay time from SCKp↓ to SOp output tKSO1 C = 20 pF Note 4 10 10 ns Note 3 Note 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using Note 1. Note 2. Note 3. port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. This value is valid only when CSI00’s peripheral I/O redirect function is not used. Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 1) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 32 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS (3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. SCKp cycle time tKCY1 tKCY1  4/fCLK SCKp high-/low-level width tKH1, tKL1 SIp setup time (to SCKp↑) Note 1 SIp hold time (from SCKp↑) Note 2 Delay time from SCKp↓ to SOp output Note 3 2.7 V  VDD  5.5 V MAX. LS (low-speed main) mode MIN. Unit MAX. 167 500 ns 4.0 V  VDD  5.5 V tKCY1/2 - 12 tKCY1/2 - 50 ns 2.7 V  VDD  5.5 V tKCY1/2 - 18 tKCY1/2 - 50 ns 4.0 V  VDD  5.5 V 44 110 ns 2.7 V  VDD  5.5 V 44 110 ns tKSI1 2.7 V  VDD  5.5 V 19 tKSO1 2.7 V  VDD  5.5 V tSIK1 19 25 ns 25 ns C = 30 pF Note 4 Note 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using Note 1. Note 2. Note 3. port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM number (g = 3, 5) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 33 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. tKCY2 SCKp cycle time Note 5 SIp setup time (to SCKp↑) Note 1 SIp hold time (from SCKp↑) Note 2 Delay time from SCKp↓ to SOp SSI00 hold time Note 1. Note 2. Note 3. Note 4. Note 5. Caution MAX. 8/fMCK — ns fMCK  20 MHz 6/fMCK 6/fMCK ns 2.7 V  VDD  5.5 V 16 MHz < fMCK 8/fMCK — ns 6/fMCK 6/fMCK ns 4.0 V  VDD  5.5 V tKCY2/2 - 7 tKCY2/2 - 7 ns 2.7 V  VDD  5.5 V tKCY2/2 - 8 tKCY2/2 - 8 ns tSIK2 2.7 V  VDD  5.5 V 1/fMCK + 20 1/fMCK + 30 ns tKSI2 2.7 V  VDD  5.5 V 1/fMCK + 31 tKSO2 C = 30 pF tSSIK DAPmn = 0 Note 4 2.7 V  VDD  5.5 V tKSSI 2.7 V  VDD  5.5 V 1/fMCK + 31 2/fMCK + 44 output Note 3 SSI00 setup time MIN. Unit 4.0 V  VDD  5.5 V 20 MHz < fMCK fMCK  16 MHz tKH2, tKL2 SCKp high-/low-level width MAX. LS (low-speed main) mode 120 ns 2/fMCK + 110 ns 120 ns DAPmn = 1 2.7 V  VDD  5.5 V 1/fMCK + 120 1/fMCK + 120 ns DAPmn = 0 2.7 V  VDD  5.5 V 1/fMCK + 120 1/fMCK + 120 ns DAPmn = 1 2.7 V  VDD  5.5 V 120 ns 120 When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. C is the load capacitance of the SOp output lines. The maximum transfer rate when using the SNOOZE mode is 1 Mbps. Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM number (g = 3, 5) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 34 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS CSI mode connection diagram (during communication at same potential) SCKp RL78 microcontroller SCK SIp SO SOp SI User's device CSI mode connection diagram (during communication at same potential) (Slave Transmission of slave select input function (CSI00)) SCK00 RL78 microcontroller SCK SI00 SO SO00 SI SSI00 SS0 User's device Remark 1. p: CSI number (p = 00) Remark 2. m: Unit number, n: Channel number (mn = 00) R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 35 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1, 2 tKH1, 2 tKL1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 SOp Output data tKSSI tSSIK SSI00 (CSI00 only) CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1, 2 tKL1, 2 tKH1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 SOp Output data tSSIK tKSSI SSI00 (CSI00 only) Remark 1. p: CSI number (p = 00) Remark 2. m: Unit number, n: Channel number (mn = 00) R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 36 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS (5) During communication at same potential (simplified I2C mode) (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. SCLr clock frequency Hold time when SCLr = “L” Hold time when SCLr = “H” Data setup time (reception) Data hold time (transmission) fSCL tLOW tHIGH tSU: DAT tHD: DAT MAX. LS (low-speed main) mode MIN. Unit MAX. 2.7 V  VDD  5.5 V, Cb = 50 pF, Rb = 2.7 k 1000 Note 1 400 Note 1 kHz 2.7 V  VDD  5.5 V, Cb = 100 pF, Rb = 3 k 400 Note 1 400 Note 1 kHz 2.7 V  VDD  5.5 V, Cb = 50 pF, Rb = 2.7 k 475 1150 ns 2.7 V  VDD  5.5 V, Cb = 100 pF, Rb = 3 k 1150 1150 ns 2.7 V  VDD  5.5 V, Cb = 50 pF, Rb = 2.7 k 475 1150 ns 2.7 V  VDD  5.5 V, Cb = 100 pF, Rb = 3 k 1150 1150 ns 2.7 V  VDD  5.5 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 85 1/fMCK + 145 ns Note 2 Note 2 2.7 V  VDD  5.5 V, Cb = 100 pF, Rb = 3 k 1/fMCK + 145 1/fMCK + 145 Note 2 Note 2 2.7 V  VDD  5.5 V, Cb = 50 pF, Rb = 2.7 k 0 305 0 305 ns 2.7 V  VDD  5.5 V, Cb = 100 pF, Rb = 3 k 0 355 0 355 ns Note 1. The value must also be equal to or less than fMCK/4. Note 2. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”. ns (Remaks are listed on the next page.) R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 37 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS Simplified I2C mode connection diagram (during communication at same potential) VDD Rb SDAr SDA RL78 microcontroller User’s device SCLr SCL Simplified I2C mode serial transfer timing (during communication at same potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD: DAT Caution tSU: DAT Select the normal input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh). Remark 1. Rb[]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance Remark 2. r: IIC number (r = 00), g: PIM number (g = 3, 5), h: POM number (h = 3, 5) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0), n: Channel number (n = 0), mn = 00) R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 38 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS (6) Communication at different potential (2.5 V, 3 V) (UART mode) (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V) Parameter Symbol Conditions (1/2) HS (high-speed main) mode MIN. Transfer rate Reception 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V Theoretical value of the maximum transfer rate MAX. LS (low-speed main) mode MIN. Unit MAX. fMCK/6 Note 1 fMCK/6 Note 1 bps 4.0 1.3 Mbps fMCK/6 Note 1 fMCK/6 Note 1 bps 4.0 1.3 Mbps bps fMCK = fCLK Note 3 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 2.7 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Theoretical value of the maximum transfer rate fMCK/6 fMCK/6 Notes 1, 2 Notes 1, 2 4.0 1.3 Mbps fMCK = fCLK Note 3 Note 1. Transfer rate in the SNOOZE mode is 4800 bps only. However, the SNOOZE mode cannot be used when FRQSEL4 = 1. Note 2. Use it with VDD  Vb. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V  VDD  5.5 V) LS (low-speed main) mode: 8 MHz (2.7 V  VDD  5.5 V) Note 3. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remark 1. Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0, 1), g: PIM and POM number (g = 0, 5) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03) Remark 4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at different potentials in UART mode. 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V: VIH = 2.2 V, VIL = 0.8 V 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V: VIH = 2.0 V, VIL = 0.5 V 2.7 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V: VIH = 1.50 V, VIL = 0.32 V R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 39 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS (6) Communication at different potential (2.5 V, 3 V) (UART mode) (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V) Parameter Symbol (2/2) Conditions HS (high-speed main) mode MIN. Transfer rate transmission 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 1.4 k, Vb = 2.7 V 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 2.7 k, Vb = 2.3 V 2.7 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 5.5 k, Vb = 1.6 V Note 1. MAX. LS (low-speed main) mode MIN. Unit MAX. Note 1 Note 1 bps 2.8 Note 2 2.8 Note 2 Mbps Note 3 Note 3 bps 1.2 Note 4 1.2 Note 4 Mbps Note 5, 6 Note 5, 6 bps 0.43 Note 7 0.43 Note 7 Mbps The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V  VDD  5.5 V and 2.7 V  Vb  4.0 V 1 Maximum transfer rate = 2.2 )}  3 {-Cb  Rb  In (1 Vb 1 Transfer rate  2 [bps] - {-Cb  Rb  In (1 - 2.2 )} Vb  100 [%] Baud rate error (theoretical value) = ( 1 Transfer rate )  Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. Note 2. Note 3. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V  VDD < 4.0 V and 2.3 V  Vb  2.7 V 1 Maximum transfer rate = {-Cb  Rb  In (1 - 2.0 )}  3 Vb 1 Transfer rate  2 [bps] - {-Cb  Rb  In (1 - 2.0 )} Vb  100 [%] Baud rate error (theoretical value) = ( 1 Transfer rate )  Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. Note 4. Note 5. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer. Use it with VDD  Vb. R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 40 of 67 RL78/G1G Note 6. 2. ELECTRICAL SPECIFICATIONS The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V  VDD < 3.3 V and 1.6 V  Vb  2.0 V 1 Maximum transfer rate = {-Cb  Rb  In (1 - 1.5 Vb [bps] )}  3 1 Transfer rate  2 - {-Cb  Rb  In (1 - 1.5 Vb )}  100 [%] Baud rate error (theoretical value) = ( 1 Transfer rate )  Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. Note 7. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remark 1. Rb[]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0, 1), g: PIM and POM number (g = 0, 5) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03)) Remark 4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at different potentials in UART mode. 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V: VIH = 2.2 V, VIL = 0.8 V 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V: VIH = 2.0 V, VIL = 0.5 V 2.7 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V: VIH = 1.50 V, VIL = 0.32 V UART mode connection diagram (during communication at different potential) Vb Rb TxDq Rx RL78 microcontroller User’s device RxDq R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Tx Page 41 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Remark 1. Rb[]: Communication line (TxDq) pull-up resistance, Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0, 1), g: PIM and POM number (g = 0, 5) R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 42 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS (7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) mode MIN. SCKp cycle time SCKp high-level width SCKp low-level width SIp setup time tKCY1 tKH1 tKL1 tSIK1 (to SCKp↑) Note 1 SIp hold time tKSI1 (from SCKp↑) Note 1 Delay time from SCKp↓ to SOp tKSO1 output Note 1 SIp setup time tSIK1 (to SCKp↓) Note 2 SIp hold time tKSI1 (from SCKp↓) Note 2 Delay time from SCKp↑ to SOp output Note 2 tKSO1 tKCY1  2/fCLK MAX. LS (low-speed main) mode MIN. Unit MAX. 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 20 pF, Rb = 1.4 k 200 1150 ns 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 20 pF, Rb = 2.7 k 300 1150 ns 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 20 pF, Rb = 1.4 k tKCY1/2 - 50 tKCY1/2 - 50 ns 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 20 pF, Rb = 2.7 k tKCY1/2 - 120 tKCY1/2 - 120 ns 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 20 pF, Rb = 1.4 k tKCY1/2 - 7 tKCY1/2 - 50 ns 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 20 pF, Rb = 2.7 k tKCY1/2 - 10 tKCY1/2 - 50 ns 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 20 pF, Rb = 1.4 k 58 479 ns 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 20 pF, Rb = 2.7 k 121 479 ns 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 20 pF, Rb = 1.4 k 10 10 ns 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 20 pF, Rb = 2.7 k 10 10 ns 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 20 pF, Rb = 1.4 k 60 60 ns 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 20 pF, Rb = 2.7 k 130 130 ns 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 20 pF, Rb = 1.4 k 23 110 ns 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 20 pF, Rb = 2.7 k 33 110 ns 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 20 pF, Rb = 1.4 k 10 10 ns 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 20 pF, Rb = 2.7 k 10 10 ns 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 20 pF, Rb = 1.4 k 10 10 ns 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 20 pF, Rb = 2.7 k 10 10 ns (Notes, Caution and Remarks are listed on the next page.) R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 43 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS CSI mode connection diagram (during communication at different potential) Vb Vb Rb Rb SCKp RL78 microcontroller SCK SIp SO SOp SI User’s device Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. Note 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g = 3, 5) Remark 3. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at different potentials in CSI mode. 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V: VIH = 2.2 V, VIL = 0.8 V 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V: VIH = 2.0 V, VIL = 0.5 V Remark 4. This value is valid only when CSI00’s peripheral I/O redirect function is not used. R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 44 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS (8) Communication at different potential (2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V)(1/2) Parameter Symbol Conditions HS (high-speed main) mode MIN. SCKp cycle time SCKp high-level width SCKp low-level width tKCY1 tKH1 tKL1 tKCY1 4/fCLK MAX. LS (low-speed main) mode MIN. Unit MAX. 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 30 pF, Rb = 1.4 k 300 1150 ns 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 500 1150 ns 2.7 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V, Cb = 30 pF, Rb = 5.5 k 1150 1150 ns 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 30 pF, Rb = 1.4 k tKCY1/2 - 75 tKCY1/2 - 75 ns 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k tKCY1/2 - 170 tKCY1/2 - 170 ns 2.7 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V, Cb = 30 pF, Rb = 5.5 k tKCY1/2 - 458 tKCY1/2 - 458 ns 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 30 pF, Rb = 1.4 k tKCY1/2 - 12 tKCY1/2 - 50 ns 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k tKCY1/2 - 18 tKCY1/2 - 50 ns 2.7 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V, Cb = 30 pF, Rb = 5.5 k tKCY1/2 - 50 tKCY1/2 - 50 ns Caution 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Caution 2. Use it with VDD  Vb. Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g = 3, 5) Remark 3. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at different potentials in CSI mode. 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V: VIH = 2.2 V, VIL = 0.8 V 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V: VIH = 2.0 V, VIL = 0.5 V R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 45 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS (8) Communication at different potential (2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V) Parameter Symbol Conditions (2/2) HS (high-speed main) mode MIN. SIp setup time (to SCKp↑) Note 1 SIp hold time (from SCKp↑) Note 1 Delay time from SCKp↓ to SOp tSIK1 tKSI1 tKSO1 output Note 1 SIp setup time (to SCKp↓) Note 2 SIp hold time (from SCKp↓) Note 2 Delay time from SCKp↑ to SOp output Note 2 tSIK1 tKSI1 tKSO1 MAX. LS (low-speed main) mode MIN. Unit MAX. 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 30 pF, Rb = 1.4 k 81 479 ns 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 177 479 ns 2.7 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V, Cb = 30 pF, Rb = 5.5 k 479 479 ns 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 30 pF, Rb = 1.4 k 19 19 ns 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 19 19 ns 2.7 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V, Cb = 30 pF, Rb = 5.5 k 19 19 ns 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 30 pF, Rb = 1.4 k 100 100 ns 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 195 195 ns 2.7 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V, Cb = 30 pF, Rb = 5.5 k 483 483 ns 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 30 pF, Rb = 1.4 k 44 110 ns 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 44 110 ns 2.7 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V, Cb = 30 pF, Rb = 5.5 k 110 110 ns 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 30 pF, Rb = 1.4 k 19 19 ns 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 19 19 ns 2.7 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V, Cb = 30 pF, Rb = 5.5 k 19 19 ns 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 30 pF, Rb = 1.4 k 25 25 ns 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 25 25 ns 2.7 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V, Cb = 30 pF, Rb = 5.5 k 25 25 ns (Notes, Caution and Remarks are listed on the next page.) R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 46 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS CSI mode connection diagram (during communication at different potential Vb Vb Rb Rb SCKp RL78 microcontroller Note 1. Note 2. SCK SIp SO SOp SI User’s device When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Caution 2. Use it with VDD  Vb. Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g = 3, 5) Remark 3. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at different potentials in CSI mode. 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V: VIH = 2.2 V, VIL = 0.8 V 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V: VIH = 2.0 V, VIL = 0.5 V R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 47 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1 tKL1 tKH1 SCKp tSIK1 tKSI1 Input data SIp tKSO1 SOp Output data CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1 tKH1 tKL1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 SOp Remark Output data p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g = 3, 5) R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 48 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS (9) Communication at different potential (2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V) Parameter Sym bol Conditions HS (high-speed main) mode MIN. SCKp cycle time Note 1 tKCY2 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V 2.7 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V SCKp high-/low-level width tKH2, tKL2 SIp setup time tSIK2 MAX. LS (low-speed main) mode MIN. Unit MAX. 20 MHz < fMCK  24 MHz 12/fMCK — ns 8 MHz < fMCK  20 MHz 10/fMCK — ns 4 MHz < fMCK  8 MHz 8/fMCK 16/fMCK ns fMCK  4 MHz 6/fMCK 10/fMCK ns 20 MHz < fMCK  24 MHz 16/fMCK — ns 16 MHz < fMCK  20 MHz 14/fMCK — ns 8 MHz < fMCK  16 MHz 12/fMCK — ns 4 MHz < fMCK  8 MHz 8/fMCK 16/fMCK ns fMCK  4 MHz 6/fMCK 10/fMCK ns 20 MHz < fMCK  24 MHz 36/fMCK — ns 16 MHz < fMCK  20 MHz 32/fMCK — ns 8 MHz < fMCK  16 MHz 26/fMCK — ns 4 MHz < fMCK  8 MHz 16/fMCK 16/fMCK ns fMCK  4 MHz 10/fMCK 10/fMCK ns 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V tKCY2/2 - 12 tKCY2/2 - 50 ns 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V tKCY2/2 - 18 tKCY2/2 - 50 ns 2.7 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V tKCY2/2 - 50 tKCY2/2 - 50 ns 2.7 V  VDD  5.5 V 1/fMCK + 20 1/fMCK + 30 ns 1/fMCK + 31 1/fMCK + 31 ns (to SCKp↑) Note 2 SIp hold time tKSI2 (from SCKp↑) Note 3 Delay time from SCKp↓ to SOp output Note 4 tKSO2 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 30 pF, Rb = 1.4 k 2/fMCK + 120 2/fMCK + 573 ns 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 2/fMCK + 214 2/fMCK + 573 ns 2.7 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V, Cb = 30 pF, Rv = 5.5 k 2/fMCK + 573 2/fMCK + 573 ns (Notes, Caution and Remarks are listed on the next page.) R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 49 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS CSI mode connection diagram (during communication at different potential) Vb Rb SCKp RL78 microcontroller Note 1. Note 2. Note 3. Note 4. Caution SCK SIp SO SOp SI User’s device Transfer rate in the SNOOZE mode: MAX. 1 Mbps When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Select the TTL input buffer for the SIp pin and SCKp pin, and the N-ch open drain output (VDD tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remark 1. Rb[]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g = 3, 5) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) Remark 4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at different potentials in CSI mode. 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V: VIH = 2.2 V, VIL = 0.8 V 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V: VIH = 2.0 V, VIL = 0.5 V Remark 5. Communication at different potential cannot be performed during clock synchronous serial communication with the slave select function. R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 50 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY2 tKL2 tKH2 SCKp tSIK2 tKSI2 Input data SIp tKSO2 SOp Output data CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY2 tKH2 tKL2 SCKp tSIK2 SIp tKSI2 Input data tKSO2 SOp Output data Remark 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g = 3, 5) Remark 2. Communication at different potential cannot be performed during clock synchronous serial communication with the slave select function. R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 51 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS (10) Communication at different potential (2.5 V, 3 V) (simplified I2C mode) (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V) Parameter Symbol (1/2) HS (high-speed main) LS (low-speed main) mode mode Conditions MIN. SCLr clock fSCL 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, MAX. MIN. Unit MAX. 1000 Note 1 300 Note 1 kHz 1000 Note 1 300 Note 1 kHz 400 Note 1 300 Note 1 kHz 400 Note 1 300 Note 1 kHz 300 Note 1 300 Note 1 kHz Cb = 50 pF, Rb = 2.7 k frequency 2.7 V  VDD < 4.0 V, 2.3 V  Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V  VDD < 4.0 V, 2.3 V  Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 2.7 V  VDD < 3.3 V, 1.6 V  Vb < 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k Hold time when tLOW 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, 475 1550 ns 475 1550 ns 1150 1550 ns 1150 1550 ns 1550 1550 ns 245 610 ns 200 610 ns 675 610 ns 600 610 ns 610 610 ns Cb = 50 pF, Rb = 2.7 k SCLr = “L” 2.7 V  VDD < 4.0 V, 2.3 V  Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V  VDD < 4.0 V, 2.3 V  Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 2.7 V  VDD < 3.3 V, 1.6 V  Vb < 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k Hold time when SCLr = “H” tHIGH 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 50 pF, Rb = 2.7 k 2.7 V  VDD < 4.0 V, 2.3 V  Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V  VDD < 4.0 V, 2.3 V  Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 2.7 V  VDD < 3.3 V, 1.6 V  Vb < 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k (Notes, Caution and Remarks are listed on the next page.) R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 52 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS (10) Communication at different potential (2.5 V, 3 V) (simplified I2C mode) (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V) Parameter Symbol Conditions (2/2) HS (high-speed main) LS (low-speed main) mode mode MIN. Data setup time tSU:DAT 4.0 V  VDD  5.5 V, MAX. MIN. Unit MAX. Note 3 ns 1/fMCK + 135 Note 3 1/fMCK + 190 Note 3 ns 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 ns 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 ns 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 ns 1/fMCK + 135 Note 3 1/fMCK + 190 2.7 V  Vb  4.0 V, (reception) Cb = 50 pF, Rb = 2.7 k 2.7 V  VDD < 4.0 V, 2.3 V  Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V  VDD < 4.0 V, 2.3 V  Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 2.7 V  VDD < 3.3 V, 1.6 V  Vb < 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k Data hold time tHD:DAT (transmission) 4.0 V  VDD  5.5 V, 0 305 0 305 ns 0 305 0 305 ns 0 355 0 355 ns 0 355 0 355 ns 0 405 0 405 ns 2.7 V  Vb  4.0 V, Cb = 50 pF, Rb = 2.7 k 2.7 V  VDD < 4.0 V, 2.3 V  Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V  VDD < 4.0 V, 2.3 V  Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 2.7 V  VDD < 3.3 V, 1.6 V  Vb < 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k Note 1. The value must also be equal to or less than fMCK/4. Note 2. Use it with VDD  Vb. Note 3. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”. Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 53 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS Simplified I2C mode connection diagram (during communication at different potential) Vb Vb Rb Rb SDAr SDA RL78 microcontroller User’s device SCLr SCL Simplified I2C mode serial transfer timing (during communication at different potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD: DAT tSU: DAT Remark 1. Rb[]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage Remark 2. r: IIC number (r = 00), g: PIM, POM number (g = 3, 5) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0), n: Channel number (n = 0), mn = 00) Remark 4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at different potentials in simplified I2C mode. 4.0 V  VDD  5.5 V, 2.7 V  Vb  4.0 V: VIH = 2.2 V, VIL = 0.8 V 2.7 V  VDD < 4.0 V, 2.3 V  Vb  2.7 V: VIH = 2.0 V, VIL = 0.5 V R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 54 of 67 RL78/G1G 2.7 2. ELECTRICAL SPECIFICATIONS Analog Characteristics 2.7.1 A/D converter characteristics Classification of A/D converter characteristics Reference Voltage Reference voltage (+) = AVREFP Reference voltage (-) = AVREFM Input channel ANI0 to ANI7 Refer to 2.7.1 (1). ANI16 to ANI19 Refer to 2.7.1 (2). Internal reference voltage Temperature sensor output voltage Refer to 2.7.1 (1). Reference voltage (+) = VDD Reference voltage (-) = VSS Refer to 2.7.1 (3). Reference voltage (+) = VBGR Reference voltage (-) = AVREFM Refer to 2.7.1 (4). — (1) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF (-) = AVREFM/ANI1 (ADREFM = 1), target ANI pin: ANI2 to ANI7 (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V) Parameter Resolution Symbol Conditions RES Overall error Note 1 AINL MIN. 8 10-bit resolution 2.7 V  VDD  5.5 V 1.2 AVREFP = VDD Conversion time Zero-scale error Notes 1, 2 tCONV EZS TYP. EFS ILE Differential linearity error DLE AVREFP Analog input voltage VAIN VBGR 3.5 LSB 2.125 39 s 2.7 V  VDD  5.5 V 3.1875 39 s 10-bit resolution 2.7 V  VDD  5.5 V 0.25 % FSR 0.25 % FSR 2.5 LSB 1.5 LSB 2.7 VDD V 0 AVREFP V 1.5 V 10-bit resolution 2.7 V  VDD  5.5 V 10-bit resolution 2.7 V  VDD  5.5 V 10-bit resolution 2.7 V  VDD  5.5 V AVREFP = VDD Reference voltage (+) bit 3.6 V  VDD  5.5 V AVREFP = VDD Note 1 10 AVREFP = VDD AVREFP = VDD Integral linearity error Note 1 Unit 10-bit resolution AVREFP = VDD Full-scale error Notes 1, 2 MAX. Select internal reference voltage output, 1.38 1.45 2.7 V  VDD  5.5 V, HS (high-speed main) mode Note 1. Excludes quantization error (±1/2 LSB). Note 2. This value is indicated as a ratio (% FSR) to the full-scale value. R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 55 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS (2) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF (-) = AVREFM/ANI1 (ADREFM = 1), target ANI pin: ANI16 to ANI19 (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V) Parameter Resolution Symbol Conditions RES Overall error Note 1 AINL MIN. TYP. 8 10-bit resolution 2.7 V  VDD  5.5 V 1.2 MAX. Unit 10 bit 5.0 LSB AVREFP = VDD Conversion time Zero-scale error Notes 1, 2 tCONV EZS 10-bit resolution 3.6 V  VDD  5.5 V 2.125 39 s AVREFP = VDD 2.7 V  VDD  5.5 V 3.1875 39 s 10-bit resolution 2.7 V  VDD  5.5 V 0.35 % FSR 2.7 V  VDD  5.5 V 0.35 % FSR 2.7 V  VDD  5.5 V 3.5 LSB 2.7 V  VDD  5.5 V 2.0 LSB 2.7 VDD V 0 AVREFP V 1.5 V AVREFP = VDD Full-scale error Notes 1, 2 EFS 10-bit resolution AVREFP = VDD Integral linearity error Note 1 ILE 10-bit resolution AVREFP = VDD Differential linearity error DLE 10-bit resolution AVREFP = VDD Note 1 Reference voltage (+) AVREFP Analog input voltage VAIN VBGR Select internal reference voltage output, 1.38 1.45 2.7 V  VDD  5.5 V, HS (high-speed main) mode Note 1. Excludes quantization error (±1/2 LSB). Note 2. This value is indicated as a ratio (% FSR) to the full-scale value. R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 56 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS (3) When AVREF (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), AVREF (-) = VSS (ADREFM = 0), target ANI pin: ANI0 to ANI7, ANI16 to ANI19 (TA = -40 to +85°C, 2.7 V  VDD  5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage (-) = VSS) Parameter Symbol Conditions Resolution RES Overall error Note 1 AINL 10-bit resolution 2.7 V  VDD  5.5 V Conversion time tCONV 10-bit resolution 3.6 V  VDD  5.5 V 2.7 V  VDD  5.5 V Zero-scale error Full-scale error Notes 1, 2 Notes 1, 2 Integral linearity error Note 1 Differential linearity error MIN. TYP. MAX. Unit 10 bit 7.0 LSB 2.125 39 s 3.1875 39 s 8 1.2 EZS 10-bit resolution 2.7 V  VDD  5.5 V 0.60 % FSR EFS 10-bit resolution 2.7 V  VDD  5.5 V 0.60 % FSR ILE 10-bit resolution 2.7 V  VDD  5.5 V 4.0 LSB DLE 10-bit resolution 2.7 V  VDD  5.5 V 2.0 LSB VAIN ANI0 to ANI7 0 VDD V ANI16 to ANI19 0 VDD V 1.5 V Note 1 Analog input voltage VBGR Select internal reference voltage output, 1.38 1.45 2.7 V  VDD  5.5 V, HS (high-speed main) mode Note 1. Excludes quantization error (±1/2 LSB). Note 2. This value is indicated as a ratio (% FSR) to the full-scale value. R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 57 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS (4) When AVREF (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), AVREF (-) = AVREFM/ANI1 (ADREFM = 1), target ANI pin: ANI0 to ANI7, ANI16 to ANI19 (TA = -40 to +85°C, 2.7 V  VDD  5.5 V, VSS = 0 V, Reference voltage (+) = VBGR, Reference voltage (-) = AVREFM = 0 V, HS (high-speed main) mode) Parameter Resolution Symbol Conditions MIN. RES Conversion time Zero-scale error Notes 1, 2 Integral linearity error Note 1 MAX. 8 Unit bit tCONV 8-bit resolution 2.7 V  VDD  5.5 V 39 s EZS 8-bit resolution 2.7 V  VDD  5.5 V 0.60 % FSR ILE 8-bit resolution 2.7 V  VDD  5.5 V 2.0 LSB 8-bit resolution 2.7 V  VDD  5.5 V 1.0 LSB 1.5 V VBGR V Differential linearity error Note 1 DLE 17 Reference voltage (+) VBGR 1.38 Analog input voltage VAIN 0 Note 1. Excludes quantization error (±1/2 LSB). Note 2. This value is indicated as a ratio (% FSR) to the full-scale value. R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 TYP. 1.45 Page 58 of 67 RL78/G1G 2.7.2 2. ELECTRICAL SPECIFICATIONS Temperature sensor characteristics (TA = -40 to +85°C, 2.7 V  VDD  5.5 V, VSS = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25C Reference output voltage VCONST Setting ADS register = 81H Temperature coefficient FVTMPS Temperature sensor that depends on the MIN. TYP. MAX. 1.05 1.38 Unit V 1.45 1.5 V mV/°C -3.6 temperature Operation stabilization wait time 2.7.3 tAMP s 5 Comparator (TA = -40 to +85°C, 2.7 V  VDD  5.5 V, VSS = 0 V) Parameter Symbol Input offset voltage VIOCMP Input voltage range VICMP Internal reference voltage deviation ∆VIREF Conditions MIN. TYP. MAX. Unit ±5 ±40 mV VDD V 0 CmRVM register value: 7FH to 80H (m = 0, 1) ±2 LSB Other than above ±1 LSB 150 ns 1 s Response time tCR, tCF Input amplitude = 100 mV Operation stabilization time Note 1 tCMP CMPnEN = 0→1 Reference voltage stabilization tVR 70 VDD = 3.3 to 5.5 V VDD = 2.7 to 3.3 V CVRE: 0→1 3 20 Note 2 s wait time Note 1. Time required after the operation enable signal of the comparator has been changed (CMPnEN = 0 → 1) until a state satisfying the DC and AC characteristics of the comparator is entered. Note 2. Enable operation of internal reference voltage generation (CVREm bit = 1; m = 0, 1) and wait for the operation stabilization wait time before enabling the comparator output (CnOE bit = 1; n = 0, 1). Output voltage VO tCR tCF +100 mV Input voltage VIN Comparator reference voltage -100 mV R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 59 of 67 RL78/G1G 2.7.4 2. ELECTRICAL SPECIFICATIONS Programmable gain amplifier (TA = -40 to +85°C, 2.7 V  VDD  5.5 V, VSS = 0 V) Parameter Symbol Input offset voltage VIOPGA Input voltage range VIPGA Response time VOHPGA Conditions MIN. TYP. MAX. Unit ±5 ±10 mV 0.9 × VDD/gain V 0 0.9 × VDD V 0.1 × VDD VOLPGA Gain error — Slew rate SRRPGA SRFPGA 4, 8 times ±1 16 times ±1.5 32 times ±2 4.0 V  VDD  5.5 V 1.4 2.7 V  VDD  4.0 V 0.5 Falling edge 4.0 V  VDD  5.5 V 1.4 2.7 V  VDD  4.0 V 0.5 Rising edge V/s Operation stabilization wait time tPGA 4, 8 times 5 Note 16, 32 times 10 Note 2.7.5 % s Time required after the PGA operation has been enabled (PGAEN = 1) until a state satisfying the DC and AC specifications of the PGA is entered. POR circuit characteristics (TA = -40 to +85C, VSS = 0 V) Parameter Symbol Detection voltage Minimum pulse width Note Note Conditions MIN. TYP. MAX. Unit VPOR Power supply rise time 1.47 1.51 1.55 V VPDR Power supply fall time 1.46 1.50 1.54 V tPW s 300 Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC). TPW Supply voltage (VDD) VPOR VPDR or 0.7 V R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 60 of 67 RL78/G1G 2.7.6 2. ELECTRICAL SPECIFICATIONS LVD circuit characteristics (TA = -40 to +85C, VPDR  VDD  5.5 V, VSS = 0 V) Parameter Detection voltage Supply voltage level Symbol VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 Minimum pulse width tLW Detection delay time tLD Remark Conditions Power supply rise time MIN. TYP. MAX. Unit 3.98 4.06 4.14 V Power supply fall time 3.90 3.98 4.06 V Power supply rise time 3.68 3.75 3.82 V Power supply fall time 3.60 3.67 3.74 V Power supply rise time 3.07 3.13 3.19 V Power supply fall time 3.00 3.06 3.12 V Power supply rise time 2.96 3.02 3.08 V Power supply fall time 2.90 2.96 3.02 V Power supply rise time 2.86 2.92 2.97 V Power supply fall time 2.80 2.86 2.91 V Power supply rise time 2.76 2.81 2.87 V Power supply fall time 2.70 2.75 2.81 V s 300 300 s VLVD (n - 1) > VLVDn: n = 1 to 5 R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 61 of 67 RL78/G1G 2. ELECTRICAL SPECIFICATIONS LVD Detection Voltage of Interrupt & Reset Mode (TA = -40 to +85C, VPDR  VDD  5.5 V, VSS = 0 V) Parameter Symbol Interrupt and reset mode VLVD5 Conditions VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage: 2.7 V VLVD4 VLVD3 VLVD0 2.7.7 MIN. TYP. MAX. Unit 2.70 2.75 2.81 V LVIS1, LVIS0 = 1, 0 (+0.1 V) Rising release reset voltage 2.86 2.92 2.97 V Falling interrupt voltage 2.80 2.86 2.91 V LVIS1, LVIS0 = 0, 1 (+0.2 V) Rising release reset voltage 2.96 3.02 3.08 V Falling interrupt voltage 2.90 2.96 3.02 V LVIS1, LVIS0 = 0, 0 (+1.2 V) Rising release reset voltage 3.98 4.06 4.14 V Falling interrupt voltage 3.90 3.98 4.06 V Power supply voltage rising slope characteristics (TA = -40 to +85C, VSS = 0 V) Parameter Power supply voltage rising slope Caution Symbol SVDD Conditions MIN. TYP. MAX. Unit 54 V/ms Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating voltage range shown in 2.5 AC Characteristics. R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 62 of 67 RL78/G1G 2.8 2. ELECTRICAL SPECIFICATIONS RAM Data Retention Characteristics (TA = -40 to +85°C) Parameter Symbol Data retention supply voltage VDDDR Conditions MIN. TYP. 1.46 Note MAX. Unit 5.5 V The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is Note effected, but data is not retained when a POR reset is effected. Operation mode STOP mode RAM date retention mode VDD VDDDR STOP instruction execution Standby release signal (interrupt request) 2.9 Flash Memory Programming Characteristics (TA = -40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions CPU/peripheral hardware clock frequency fCLK 2.7 V ≤ VDD ≤ 5.5 V Number of code flash rewrites Notes 1, 2, 3 Cerwr Retained for 20 years Note 1. Note 2. Note 3. Remark 2.10 MIN. TYP. 1 TA = 85°C Note 3 MAX. 24 1,000 Unit MHz Times 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. When using flash memory programmer and Renesas Electronics self programming library. These specifications show the characteristics of the flash memory and the results obtained from Renesas Electronics reliability testing. When updating data multiple times, use the flash memory as one for updating data. Dedicated Flash Memory Programmer Communication (UART) (TA = -40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Transfer rate R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Symbol Conditions During serial programming MIN. 115.2 k TYP. MAX. Unit 1M bps Page 63 of 67 RL78/G1G 2.11 2. ELECTRICAL SPECIFICATIONS Timing for Switching Flash Memory Programming Modes (TA = -40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V Parameter Symbol How long from when an external reset ends until the tSUINIT Conditions MIN. POR and LVD reset must end TYP. MAX. Unit 100 ms before the external reset ends. initial communication settings are specified How long from when the TOOL0 pin is placed at the tSU low level until an external reset ends POR and LVD reset must end 10 s 1 ms before the external reset ends. tHD How long the TOOL0 pin must be kept at the low level after an external reset ends POR and LVD reset must end before the external reset ends. (excluding the processing time of the firmware to control the flash memory) RESET 723 µs + tHD 00H reception processing (TOOLRxD, TOOLTxD mode) time TOOL0 tSU tSUINIT The low level is input to the TOOL0 pin. The external reset ends (POR and LVD reset must end before the external reset ends.). The TOOL0 pin is set to the high level. Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the external resets end. tSU: How long from when the TOOL0 pin is placed at the low level until a pin reset ends tHD: How long to keep the TOOL0 pin at the low level from when the external resets end (the flash firmware processing time is excluded) R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 64 of 67 RL78/G1G 3. PACKAGE DRAWINGS 3. PACKAGE DRAWINGS 3.1 30-pin Products R5F11EA8ASP, R5F11EAAASP JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LSSOP30-0300-0.65 PLSP0030JB-B S30MC-65-5A4-3 0.18 30 16 detail of lead end F G T P 1 L 15 U E A H I J S C D N M S B M K ITEM A MILLIMETERS 9.85p0.15 B 0.45 MAX. C 0.65 (T.P.) NOTE D 0.24 0.08 0.07 Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. E 0.1p0.05 F 1.3p0.1 G 1.2 R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 H 8.1p0.2 I 6.1p0.2 J 1.0p0.2 K 0.17p0.03 L 0.5 M 0.13 N 0.10 P 3o 5o 3o T 0.25 U 0.6p0.15 Page 65 of 67 RL78/G1G 3.2 3. PACKAGE DRAWINGS 32-pin Products R5F11EB8AFP, R5F11EBAAFP JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP32-7x7-0.80 PLQP0032GB-A P32GA-80-GBT-1 0.2 HD 2 D 17 16 24 25 detail of lead end 1 E c HE θ 32 8 1 L 9 e (UNIT:mm) 3 b x M A A2 ITEM D DIMENSIONS 7.00±0.10 E 7.00±0.10 HD 9.00±0.20 HE 9.00±0.20 A 1.70 MAX. A1 0.10±0.10 A2 y A1 1.40 b 0.37±0.05 c 0.145 ±0.055 L 0.50±0.20 θ 0° to 8° e 0.80 1.Dimensions “ 1” and “ 2” do not include mold flash. x 0.20 2.Dimension “ 3” does not include trim offset. y 0.10 NOTE R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 Page 66 of 67 RL78/G1G 3.3 3. PACKAGE DRAWINGS 44-pin Products R5F11EF8AFP, R5F11EFAAFP JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP44-10x10-0.80 PLQP0044GC-A P44GB-80-UES-2 0.36 HD D detail of lead end A3 23 22 33 34 c Q E L Lp HE L1 (UNIT:mm) 12 11 44 1 ZE e ZD b x M S A S S NOTE Each lead centerline is located within 0.20 mm of its true position at maximum material condition. R01DS0241EJ0130 Rev. 1.30 Sep 30, 2016 A1 DIMENSIONS 10.00p0.20 E 10.00p0.20 HD 12.00p0.20 HE 12.00p0.20 A 1.60 MAX. A1 0.10p0.05 A2 1.40p0.05 A3 A2 y ITEM D 0.25 b 0.37 0.08 0.07 c 0.145 0.055 0.045 L 0.50 Lp 0.60p0.15 L1 Q 1.00p0.20 3o 5o 3o e 0.80 x 0.20 y 0.10 ZD 1.00 ZE 1.00 Page 67 of 67 REVISION HISTORY Rev. Date RL78/G1G Datasheet Description Page Summary 1.00 Jul 31, 2014 — First Edition issued 1.20 Mar 25, 2015 1 Change of description in 1.1 Features 3 Change of Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G1G 3 Change of Table 1 - 1 Orderable Part Numbers 1.30 Sep 30, 2016 11 Change of 1.6 Outline of Functions 1 Addition of Note to 1.1 Features 4 Modification of Pin configuration in 1.3.1 30-pin products 5 Modification of Pin configuration in 1.3.2 32-pin products 6 Modification of Pin configuration in 1.3.3 44-pin products 63 Change of Note in 2.8 RAM Data Retention Characteristics All trademarks and registered trademarks are the property of their respective owners. EEPROM is a trademark of Renesas Electronics Corporation. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash technology licensed from Silicon Storage Technology, Inc. C-1 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Notice 1. 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