Datasheet
RL78/I1E
R01DS0274EJ0110
Rev. 1.10
Jun 30, 2016
RENESAS MCU
1. OUTLINE
1.1
Features
Ultra-low power consumption technology
High-speed on-chip oscillator
VDD= 2.4 to 5.5 V
Select from 32 MHz, 24 MHz, 16 MHz, 12 MHz, 8
HALT mode
MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz
STOP mode
High accuracy:
SNOOZE mode
±2.0% (VDD = 2.4 to 5.5 V, TA = 40 to +105C)
±3.0% (VDD = 2.4 to 5.5 V, TA = 40 to +125C)
RL78 CPU core
CISC architecture with 3-stage pipeline
Minimum instruction execution time: Can be changed
from high speed (0.03125 s: @ 32 MHz operation
with high-speed on-chip oscillator or PLL clock)Note to
ultra-low speed (1 s: @ 1 MHz operation with high-
Operating ambient temperature
TA = 40 to +105C (G: Industrial applications)
TA = 40 to +125C (M: Industrial applications)
Power management and reset function
speed on-chip oscillator or PLL clock)
On-chip power-on-reset (POR) circuit
Multiply/divide/multiply & accumulate instructions are
On-chip voltage detector (LVD) (Select interrupt and
supported.
reset from 7 levels)
Address space: 1 MB
General-purpose registers: (8-bit register 8) 4
banks
Transfer modes: Normal transfer mode, repeat transfer
mode, block transfer mode
On-chip RAM: 8 KB
Note
Data transfer controller (DTC)
For industrial applications (M; TA = 40 to
Activation sources: Activated by interrupt sources.
Chain transfer function
+125C): 0.04167 s @ 24 MHz operation
with high-speed on-chip oscillator or PLL
clock
Event link controller (ELC)
Event signals of 16 types can be linked to the specified
peripheral function.
Code flash memory
Code flash memory: 32 KB
Serial interfaces
Block size: 1 KB
CSI: 2 channels
Prohibition of block erase and rewriting (security
UART: 2 channels (UART with LIN-bus supported: 1
function)
channel)
On-chip debug function
I2C/simplified I2C: 2 channels
Self-programming (with boot swap function/flash shield
window function)
Timer
16-bit timer: 8 channels
Data flash memory
Data flash memory: 4 KB
Back ground operation (BGO): Instructions can be
(Timer Array Unit (TAU): 6 channels, timer RJ: 1
channel, timer RG: 1 channel)
Interval timer: 1 channel
executed from the program memory while rewriting the
Real-time clock: 1 channel (calendar for 99 years,
data flash memory.
alarm function, and clock correction function)
Number of rewrites: 1,000,000 times (TYP.)
Watchdog timer: 1 channel (operable with the
Voltage of rewrites: VDD = 2.4 to 5.5 V
dedicated low-speed on-chip oscillator)
Analog front-end (AFE) power supply
Sensor power supply (SBIAS) output: 0.5 V to 2.2 V
R01DS0274EJ0110 Rev. 1.10
Jun 30, 2016
Page 1 of 108
RL78/I1E
1. OUTLINE
24-bit ∆Σ A/D converter with programmable gain
D/A converter
instrumentation amplifier
12-bit R-2R resistor ladder type D/A converter (AVDD =
24-bit second-order ∆Σ A/D converter (AVDD = 2.7 to
2.7 to 5.5 V)
5.5 V)
Analog output: 1 channel (via configurable amplifier)
SNDR: 85 dB (TYP.)
I/O port
Output data rate:
488 sps to 15.625 ksps in normal mode
CMOS I/O: 10 to 14 (N-ch open drain I/O [withstanding
61 sps to 1.953 ksps in low power mode
voltage of VDD]: 6, CMOS I/O: 7 to 11, CMOS input: 3)
Programmable gain instrumentation amplifier input: 3
Can be set to TTL input buffer and on-chip pull-up
or 4 channels
resistor
(differential input mode or single-ended input mode
Different potential interface: Can connect to a 2.5/3 V
can be specified for each input channel)
device
DAC for offset adjustment
On-chip clock output/buzzer output controller
Variable gain: x1 to x64
Others
On-chip temperature sensor
On-chip BCD (binary-coded decimal) correction circuit
10-bit A/D converter
8-bit/10-bit successive approximation A/D converter
(AVDD = 2.7 to 5.5 V)
Analog input: 8 or 10 channels, sensor power supply
(SBIAS), and internal reference voltage
Internal reference voltage (1.45 V)
Configurable amplifier
Matrix configuration that consists of 3 operational
amplifier channels and a configurable switch (AVDD =
2.7 to 5.5 V)
Can be used as a 2- or 3-channel general operational
amplifier
Operational amplifier output: 3 channels
General-purpose Analog I/O ports: 5 or 6 channels
Offset voltage calibration
ROM, RAM capacities
RL78/I1E
Flash ROM
32 KB
R01DS0274EJ0110 Rev. 1.10
Jun 30, 2016
Data flash
4 KB
RAM
8 KB
32 pins
36 pins
R5F11CBC
R5F11CCC
Page 2 of 108
RL78/I1E
1.2
1. OUTLINE
Ordering Information
Figure 1 - 1 Part Number, Memory Size, and Package of RL78/I1E
Part No. R 5 F 1 1 C B C G x x x N A # 4 0
Packaging specification
#20: Tray (HVQFN)
#U0: Tray (HVQFN, TFBGA)
#40: Embossed Tape (HVQFN)
#W0: Embossed Tape (HVQFN, TFBGA)
Package type:
BG:TFBGA, 0.50 mm pitch
NA:HVQFN, 0.50 mm pitch
ROM number (Omitted with blank products)
Fields of application:
G: Industrial applications, TA = -40 to +105C
M: Industrial applications, TA = -40 to +125C
ROM capacity:
C: 32 KB
Pin count:
B: 32-pin
C: 36-pin
RL78/I1E
Memory type:
F : Flash memory
Renesas MCU
Renesas semiconductor product
Pin
count
32 pins
Package
Fields of
Application
Ordering Part Number
Note
32-pin plastic HVQFN
G
(5 5 mm, 0.5 mm pitch)
R5F11CBCGNA#20
R5F11CBCGNA#40
M
R5F11CBCMNA#U0
R5F11CBCMNA#W0
36 pins
36-pin plastic TFBGA
G
R5F11CCCGBG#U0
M
R5F11CCCMBG#U0
(4 4 mm, 0.5 mm pitch)
R5F11CCCGBG#W0
R5F11CCCMBG#W0
Note
Caution
For the fields of application, refer to Figure 1 - 1 Part Number, Memory Size, and Package of RL78/I1E.
The ordering part numbers represent the numbers at the time of publication. For the latest ordering part
numbers, refer to the target product page of the Renesas Electronics website.
R01DS0274EJ0110 Rev. 1.10
Jun 30, 2016
Page 3 of 108
RL78/I1E
1. OUTLINE
1.3
Pin Configuration (Top View)
1.3.1
REGA
AVDD
ANI1/AMP0O
ANI2/AMP0N/ANX0
ANI3/AMP0P/ANX1
ANI4/AMP1O
ANI5/AMP1N/ANX2
ANI6/AMP1P/ANX3
• 32-pin plastic HVQFN (5 5 mm, 0.5 mm pitch)
exposed die pad
SBIAS
AVSS
PGA0P
PGA0N
PGA1P
PGA1N
PGA2P
PGA2N
25
26
27
28
29
30
31
32
24 23 22 21 20 19 18 17
16
15
14
13
RL78/I1E
12
(Top View)
11
10
9
1 2 3 4 5 6 7 8
ANI7/AMP2O
ANI9/AMP2P/ANX5
P15/SCK00/SCL00/TI10/TO10/INTP6/TRGCLKB
P14/SI00/RXD0/SDA00/TI02/TO02/INTP5/TOOLRXD
P13/SO00/TXD0/TI00/TO00/INTP4/TOOLTXD/RTC1HZ
P12/SCK01/SCL01/TI11/TO11/INTP3/PCLBUZ0/TRGIOB/TRJO0
P11/SI01/RXD1/SDA01/TI03/TO03/INTP2/TRGCLKA/TRJIO0
P10/SO01/TXD1/TI01/TO01/INTP1/TRGIOA
INDEX MARK
P40/TOOL0
RESET
P137/SSI00/INTP0
P122/EXCLK/X2
P121/X1
REGC
VSS
VDD
32-pin products
Caution 1. Connect the REGC pin to the VSS pin via a capacitor (0.47 to 1 F).
Caution 2. Connect the REGA pin to the AVSS pin via a capacitor (0.22 F).
Caution 3. Make the AVSS pin the same potential as the VSS pin.
Caution 4. Make the AVDD pin the same potential as the VDD pin.
Caution 5. Connect the SBIAS pin to the AVSS pin via a capacitor (0.22 F).
Remark 1. It is recommended to connect an exposed die pad to VSS.
R01DS0274EJ0110 Rev. 1.10
Jun 30, 2016
Page 4 of 108
RL78/I1E
1. OUTLINE
1.3.2
36-pin products
• 36-pin plastic TFBGA (4 × 4 mm, 0.5 mm pitch)
Top View
Bottom View
6
5
RL78/I1E
(Top View)
4
3
2
1
A
B
C
D
E
F
F
E
D
C
B
A
INDEX MARK
A
PGA2P
B
PGA1N
C
PGA1P
D
PGA0P
E
PGA3P
F
AVSS
6
6
PGA2N
P40/TOOL0
PGA0N
PGA3N
REGA
SBIAS
5
5
RESET
P137/SSI00/
P11/SI01/RXD1/
P12/SCK01/
INTP0
SDA01/TI03/
SCL01/TI11/
TO03/INTP2/
TO11/INTP3/
TRGCLKA/
PCLBUZ0/
TRJIO0
TRGIOB/TRJO0
P15/SCK00/
P10/SO01/TXD1/
ANI3/AMP0P/
ANI2/AMP0N/
SCL00/TI10/
TI01/TO01/
ANX1
ANX0
TO10/INTP6/
INTP1/TRGIOA
4
P122/EXCLK/X2
3
ANI0
AVDD
4
ANI1/AMP0O
3
TRGCLKB
P121/X1
REGC
P14/SI00/RXD0/
P41/ANI6/
P42/ANI5/
SDA00/TI02/
AMP1P/ANX3
AMP1N/ANX2
ANI4/AMP1O
2
2
TO02/INTP5/
TOOLRXD
VSS
VDD
P13/SO00/TXD0/
P16/INTP7/ANI9/
P17/ANI8/
TI00/TO00/INTP4/
AMP2P/ANX5
AMP2N/ANX4
ANI7/AMP2O
1
1
TOOLTXD/
RTC1HZ
A
B
C
D
E
F
Caution 1. Connect the REGC pin to the VSS pin via a capacitor (0.47 to 1 F).
Caution 2. Connect the REGA pin to the AVSS pin via a capacitor (0.22 F).
Caution 3. Make the AVSS pin the same potential as the VSS pin.
Caution 4. Make the AVDD pin the same potential as the VDD pin.
Caution 5. Connect the SBIAS pin to the AVSS pin via a capacitor (0.22 F).
R01DS0274EJ0110 Rev. 1.10
Jun 30, 2016
Page 5 of 108
RL78/I1E
1.4
1. OUTLINE
Pin Identification
ANI0 to ANI9:
Analog input
RESET:
Reset
AMP0P to AMP2P:
Operational amplifier
REGA:
Regulator capacitance for analog
positive input
REGC:
Regulator capacitance
Operational amplifier
RTC1HZ:
Real-time clock correction
negative input
RxD0, RxD1:
Receive data
AMP0O to AMP2O:
Operational amplifier output
SBIAS:
Bias output for MEMS sensor
ANX0 to ANX5:
General-purpose analog
SCK00, SCK01:
Serial clock input/output
AMP0N to AMP2N:
ports for operational amplifier SCL00, SCL01:
Serial clock output
AVDD:
Power supply for analog
SI00, SI01:
Serial data input
AVSS:
Ground for analog
SO00, SO01:
Serial data output
EXCLK:
External clock input
TI00 to TI03, TI10, TI11:
Timer input
(main system clock)
TO00 to TO03, TO10, TO11,
Timer output
INTP0 to INTP7:
External interrupt input
TRJO0:
P10 to P17:
Port 1
TOOL0:
Data input/output for tools
P40 to P42:
Port 4
TOOLRxD, TOOLTxD:
Data input/output for external devices
P121, P122:
Port 12
TRGCLKA, TRGCLKB:
Timer external clock input
P137:
Port 13
TRGIOA, TRGIOB, TRJIO0:
Timer input/output
PCLBUZ0:
Programmable clock output/
TxD0, TxD1:
Transmit data
buzzer output
VDD:
Power supply
PGA0N to PGA3N:
PGA negative analog input
VSS:
Ground
PGA0P to PGA3P:
PGA positive analog input
X1, X2:
Crystal oscillator (main system clock)
R01DS0274EJ0110 Rev. 1.10
Jun 30, 2016
Page 6 of 108
RL78/I1E
1. OUTLINE
1.5
Block Diagram
1.5.1
32-pin products
TAU0 (4ch)
TI00
TO00
TI01
TO01
TI02
TO02
TI03
TO03
ch00
ch02
TOOL
TXD
TOOL0
TO10
TI11
TO11
P10-P15
TOOL
RXD
P40
PORT4
ch03
TAU1 (4ch)
TI10
6
PORT1
ELC
ch01
2
OCD
PORT12
BCD
PORT13
P137
PCLBUZ
PCLBUZ0
P121, P122
ch10
ch11
CODE FLASH: 32KB
DATA FLASH: 4KB
TRJIO0
TRJO0
TRGCLKA
TRGCLKB
TRGIOA
TRGIOB
TRJ0
TRG
Interval Timer
External INT
8ch
INTERRUPT
CONTROL
RL78 CPU CORE
MULTIPLIER &
DIVIDER,
MULTIPLYACCUMULATOR
DTC
TXD0
RAM 8KB
CRC
UART0
(LIN)
RXD1
TXD1
UART1
SCK00
SI00
SO00
SSI00
CSI00
SCK01
SI01
CSI01
INTP0-INTP6
WWDT
SAU0 (4ch)
RXD0
7
RTC1HZ
RTC
RESET
VOLTAGE
REGULATOR
PLL
CSC
Clock Generator
+
Reset Generator
SO01
Main OSC
1-20MHz
REGC
X1
SCL00
SDA00
IIC00
SCL01
SDA01
IIC01
POR/
LVD
Low Speed
Internal OSC
15kHz
X2/EXCLK
High Speed
Internal OSC
32MHz/24MHz
VDD
VSS
PGA0N
PGA0P
24-bitΔΣA/D
Converter
PGA
PGA1N
PGA1P
PGA2N
Input
Mux
PGA2P
Temperature Sensor
12-bitD/A
Converter
AMP0O/ANI1
AMP1O/ANI4
AMP2O/ANI7
AFE
VOLTAGE
REGULATOR
10-bitA/D
Converter
Input
Mux
REGA
OpAmp
3ch
sel
AMP0N/ANX0/ANI2
AMP0P/ANX1/ANI3
AMP1N/ANX2/ANI5
AMP1P/ANX3/ANI6
AMP2P/ANX5/ANI9
SW
SBIAS
SBIAS
AVDD
R01DS0274EJ0110 Rev. 1.10
Jun 30, 2016
AVSS
Page 7 of 108
RL78/I1E
1. OUTLINE
1.5.2
36-pin products
TAU0 (4ch)
TI00
TO00
TI01
TO01
TI02
TO02
TI03
TO03
ch00
ch02
TO10
TI11
TO11
8
P10-P17
PORT4
3
P40-P42
OCD
PORT12
4
P121, P122
BCD
PORT13
P137
PCLBUZ
PCLBUZ0
TOOL
TXD
TOOL0
TOOL
RXD
ch03
TAU1 (4ch)
TI10
PORT1
ELC
ch01
ch10
ch11
CODE FLASH: 32KB
DATA FLASH: 4KB
TRJIO0
TRJO0
TRGCLKA
TRGCLKB
TRGIOA
TRGIOB
TRJ0
TRG
Interval Timer
External INT
8ch
INTERRUPT
CONTROL
RL78 CPU CORE
MULTIPLIER &
DIVIDER,
MULTIPLYACCUMULATOR
DTC
8
INTP0-INTP7
WWDT
RAM 8KB
CRC
SAU0 (4ch)
RXD0
TXD0
UART0
(LIN)
RXD1
TXD1
UART1
SCK00
SI00
SO00
SSI00
CSI00
SCK01
SI01
CSI01
RTC
RTC1HZ
RESET
VOLTAGE
REGULATOR
PLL
CSC
Clock Generator
+
Reset Generator
SO01
Main OSC
1-20MHz
REGC
X1
SCL00
SDA00
IIC00
SCL01
SDA01
IIC01
POR/
LVD
Low Speed
Internal OSC
15kHz
X2/EXCLK
VDD
High Speed
Internal OSC
32MHz/24MHz
VSS
PGA0N
PGA0P
24-bit ΔΣA/D
Converter
PGA
PGA1N
PGA1P
PGA2N
Input
Mux
PGA2P
PGA3N
PGA3P
Temperature Sensor
12-bit D/A
Converter
AMP0O/ANI1
AMP1O/ANI4
AMP2O/ANI7
ANI0
AFE
VOLTAGE
REGULATOR
REGA
SBIAS
10-bit A/D
Converter
Input
Mux
OpAmp
3ch
sel
AMP0N/ANX0/ANI2
AMP0P/ANX1/ANI3
AMP1N/ANX2/ANI5
AMP1P/ANX3/ANI6
AMP2N/ANX4/ANI8
AMP2P/ANX5/ANI9
SW
SBIAS
AVDD
R01DS0274EJ0110 Rev. 1.10
Jun 30, 2016
AVSS
Page 8 of 108
RL78/I1E
1.6
1. OUTLINE
Outline of Functions
[32-pin, 36-pin products]
(1/2)
32-pin
36-pin
R5F11CBC
R5F11CCC
Item
Code flash memory
32 KB
Data flash memory
4 KB
RAM
8 KB
Address space
1 MB
Main system
High-speed system
clock
clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 16 MHz: VDD = 2.4 to 2.7 V
High-speed on-chip
1 to 32 MHz (VDD = 2.7 to 5.5 V)Note 1
oscillator clock (fIH)
1 to 16 MHz (VDD = 2.4 to 5.5 V)
PLL clock (fPLL divided
by 2, 4, or 8)
3 to 16 MHz (VDD = 2.4 to 5.5 V)
3 to 32 MHz (VDD = 2.7 to 5.5 V)Note 2
General-purpose register
8 bits 32 registers (8 bits 8 registers 4 banks)
Minimum instruction execution time
0.03125 s (high-speed on-chip oscillator clock: fIH = 32 MHz operation)Note 3
0.03125 s (PLL clock: fPLL = 64 MHz, fIH = 32 MHz operation)Note 4
0.05 s (high-speed system clock: fMX = 20 MHz operation)
Instruction set
I/O port
•
•
•
•
•
Data transfer (8/16 bits)
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits 8 bits, 16 bits 16 bits), division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and Accumulation (16 bits 16 bits + 32 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
Total
10
14
CMOS I/O
7
11
3
3
CMOS input
Timer
16-bit timer
8 channels (TAU: 6 channels, Timer RJ: 1 channel, Timer RG: 1 channel)
Watchdog timer
1 channel
Real-time clock (RTC)
1 channel
Interval timer
1 channel
Timer output
Timer outputs: 10 channels
RTC output
1
PWM outputs: 9 channels
Clock output/buzzer output
1
2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
8/10-bit A/D converter
8 channels
Serial interface
CSI: 2 channels/UART: 2 channels (UART supporting LIN-bus: 1 channel)/simplified I2C: 2 channels
10 channels
Note 1.
1 to 24 MHz (VDD = 2.7 to 5.5 V) for M products (industrial applications, TA = 40 to +125C)
Note 2.
3 to 24 MHz (VDD = 2.7 to 5.5 V) for M products (industrial applications, TA = 40 to +125C)
Note 3.
0.04167 μs (high-speed on-chip oscillator clock: fIH = 24 MHz operation) for M products (industrial applications, TA = 40
to +125C)
Note 4.
0.04167 μs (PLL clock: fPLL = 64 MHz, fIH = 24 MHz operation) for M products (industrial applications, TA = 40 to +125C
R01DS0274EJ0110 Rev. 1.10
Jun 30, 2016
Page 9 of 108
RL78/I1E
1. OUTLINE
(2/2)
32-pin
36-pin
R5F11CBC
R5F11CCC
Item
Data transfer controller (DTC)
Event link controller (ELC)
22 sources
Event input: 16
Event trigger output: 7
Vectored interrupt
Internal
23
23
sources
External
7
8
∆Σ A/D converter
24-bit
3 channels
AFE temperature
1 channel
4 channels
sensor
Operational
amplifier
3-pin
3 channels Note 1
3 channels
General-purpose
5 channels
6 channels
port
D/A converter
12-bit
Reset
1 channel
•
•
•
•
Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
• Internal reset by illegal instruction execution Note 2
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit
• Power-on-reset:
1.56 ±0.03 V
• Power-down-reset: 1.55 ±0.03 V
Voltage detector
• At rise: 2.55 V to 4.64 V (7 steps)
• At fall: 2.61 V to 4.74 V (7 steps)
On-chip debug function
Provided
Power supply voltage
VDD = 2.4 to 5.5 V
Operating ambient temperature
TA = 40 to +105C (G: Industrial applications), TA = 40 to +125C (M: Industrial applications)
Note 1.
When each of the 3 channels is in use as an independent amplifier, at least one channel must be in a voltage follower
configuration.
Note 2.
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not is issued by emulation with the in-circuit emulator or on-chip debug
emulator.
R01DS0274EJ0110 Rev. 1.10
Jun 30, 2016
Page 10 of 108
RL78/I1E
2. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
2. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
This chapter describes the electrical specifications for the products “G: Industrial applications (TA = -40 to +105C)”.
Caution 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and
evaluation. Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded when this
function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not
liable for problems occurring when the on-chip debug function is used.
Caution 2. The pins mounted depend on the product.
Caution 3. Please contact Renesas Electronics sales office for derating of operation under TA = +85 to +105°C.
Derating is the systematic reduction of load for the sake of improved reliability.
Remark
The electrical characteristics of the products G: Industrial applications (TA = -40 to +105°C) are different from
those of the products “M: Industrial applications”. For details, refer to 2.1 to 2.10.
R01DS0274EJ0110 Rev. 1.10
Jun 30, 2016
Page 11 of 108
RL78/I1E
2. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
2.1
Absolute Maximum Ratings
Absolute Maximum Ratings
Parameter
Supply voltage
REGC pin input voltage
(1/2)
Symbol
Conditions
VDD
Ratings
Unit
-0.5 to +6.5
V
AVDD
AVDD = VDD
-0.5 to +6.5
V
AVSS
AVSS = VSS
-0.5 to +0.3
V
VIREGC
REGC
-0.3 to +2.8
V
and -0.3 to VDD + 0.3 Note 1
REGA pin input voltage
VIREGA
REGA
-0.3 to +2.8
V
and -0.3 to AVDD + 0.3 Note 2
Input voltage
VI1
P10 to P15, P40, P121, P122, P137, EXCLK,
-0.3 to VDD +0.3 Note 3
V
-0.3 to VDD + 0.3 Note 3
V
-0.3 to AVDD + 0.3 Note 3
V
-0.3 to AVDD + 0.3 Note 3
V
-0.3 to VDD + 0.3 Note 3
V
Note 3
V
RESET
Alternate-function pin
VI2
Digital input voltage
(36-pin products only) Analog input voltage
input voltage
Analog input voltage
P16, P17, P41, P42
VIA
PGA0P to PGA3P, PGA0N to PGA3N,
ANI0 to ANI9, ANX0 to ANX5
Output voltage
VO1
P10 to P15, P40
Alternate-function pin
VO2
P16, P17, P41, P42
output voltage
Analog output voltage
Note 1.
VOA
Digital output voltage
-0.3 to VDD + 0.3
(36-pin products only) Analog output voltage
-0.3 to AVDD + 0.3
Note 3
V
SBIAS, AMP0O to AMP2O, ANX0 to ANX5
-0.3 to AVDD + 0.3 Note 3
V
Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). This value regulates the absolute maximum rating of the
REGC pin. Do not use this pin with voltage applied to it.
Note 2.
Connect the REGA pin to AVSS via a capacitor (0.22 F). This value regulates the absolute maximum rating of the REGA
pin. Do not use this pin with voltage applied to it.
Note 3.
Caution
Must be 6.5 V or lower.
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the product must be used under conditions that ensure that the absolute maximum
ratings are not exceeded.
Remark 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
Remark 2. VSS is used as the reference voltage.
R01DS0274EJ0110 Rev. 1.10
Jun 30, 2016
Page 12 of 108
RL78/I1E
2. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Absolute Maximum Ratings
Parameter
Output current, high
Analog output current,
(2/2)
Symbol
IOH1
IOHA
Conditions
Per pin
Unit
-40
mA
-100
mA
P10 to P17, P40 to P42
Total of all pins
P10 to P17, P41, P42
Per pin
AMP0O to AMP2O
high
Ratings
Note
ANX0 to ANX5
Output current, low
IOL1
Analog output current, low IOLA
TA
Storage temperature
Note
Caution
mA
AMP0O to AMP2O, ANX0 to ANX5
-18
mA
Per pin
P10 to P17, P40 to P42
40
mA
100
mA
Total of all pins
P10 to P17, P41, P42
Per pin
AMP0O to AMP2O
Total of all pins
temperature
mA
Total of all pins
Note
12
mA
0.12
mA
18
mA
-40 to +105
C
-65 to +150
C
ANX0 to ANX5
Operating ambient
-12
-0.12
AMP0O to AMP2O, ANX0 to ANX5
In normal operation mode
In flash memory programming mode
Tstg
This indicates the total current value when P16, P17, P41, and P42 are used as digital input pins.
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the product must be used under conditions that ensure that the absolute maximum
ratings are not exceeded.
Remark 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
Remark 2. VSS is used as the reference voltage.
R01DS0274EJ0110 Rev. 1.10
Jun 30, 2016
Page 13 of 108
RL78/I1E
2.2
2. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C)
Oscillator Characteristics
2.2.1
X1 characteristics
(TA = -40 to +105°C, 2.4 V AVDD = VDD 5.5 V, AVSS = VSS = 0 V)
Parameter
X1 clock oscillation frequency
Note
Resonator
(fX) Note
Conditions
MIN.
MAX.
Unit
Ceramic resonator/
2.7 V VDD 5.5 V
1.0
TYP.
20.0
MHz
crystal resonator
2.4 V VDD
