Datasheet
R01DS0371EJ0100
Rev.1.00
Nov 29, 2019
RL78/G1P
RENESAS MCU
True low-power platform (66 μA/MHz, and 0.31 μA for LVD) for the general-purpose and sensor control applications, with 2.7-V to 3.6-V operation,
low pin counts (24 or 32 pins), small ROM capacity (16 Kbytes), and highly-functional analog circuits (12-bit A/D and 10-bit D/A converters)
1. OUTLINE
1.1 Features
Minimum instruction execution time can be
changed from high speed (0.03125 s: @ 32 MHz
8/12-bit resolution A/D converter (VDD = 2.7 to 3.6
V): 6 or 8 channels
operation with high-speed on-chip oscillator) to
Standby function: HALT, STOP, SNOOZE mode
low-speed (1 s: @ 1 MHz operation with high-
On-chip 10-bit D/A converter
speed on-chip oscillator)
DMA controller: 2 channels
General-purpose registers: 8 bits 32 registers (8
bits 8 registers 4 banks)
ROM: 16 KB, RAM: 1.5 KB, Data flash: 2 KB
High-speed on-chip oscillator
Select from 32 MHz (TYP.), 24 MHz (TYP.), 16
On-chip event link controller (ELC)
Power supply voltage: VDD = 2.7 to 3.6 V
Operating ambient temperature: TA = -40 to +85C
(A: Consumer applications, D: Industrial
applications)
MHz (TYP.), 12 MHz (TYP.), 8 MHz (TYP.), 6
MHz (TYP.), 4 MHz (TYP.), 3 MHz (TYP.), 2
MHz (TYP.), and 1 MHz (TYP.)
Remark The functions mounted depend on the
product. See 1.6 Outline of Functions.
On-chip single-power supply flash memory (with
prohibition of block erase/writing function)
Self-programming
On-chip debug function
On-chip power-on-reset (POR) circuit and voltage
detector (LVD)
On-chip watchdog timer (operable with the
dedicated low-speed on-chip oscillator)
On-chip clock output/buzzer output controller
On-chip BCD adjustment
I/O ports: 26 or 28 (N-ch open drain: 2)
Timer
16-bit timer TAU:
4 channels
Watchdog timer:
1 channel
Serial interface
CSI:
1 channel
UART:
1 channel
I2C
1 channel (2 slave addresses)
R01DS0371EJ0100 Rev.1.00
Nov 29, 2019
Page 1 of 39
RL78/G1P
1. OUTLINE
ROM, RAM capacities
Flash ROM
Data Flash
RAM Note
24-pin
32-pin
16 KB
2 KB
1.5 KB
R5F11Z7AANA, R5F11Z7ADNA
R5F11ZBAAFP, R5F11ZBADFP
Note The flash libraries use the on-chip RAM area from FFE20H to FFEFFH and the parts of the RAM area referred to
as self RAM (RAM for use in self-programming), which are listed in the table below, for self-programming or
rewriting of the data flash memory.
See below for the RAM areas used by the flash library.
RAM
R5F11Z7AANA
1.5 KB
FSL Type01
FDL Type04
Self RAM size
Self RAM size
896 bytes Note
136 bytes
FF900H to FFC7FH
FF900H to FF987H
EEL Pack01, EEL Pack02
Not available
R5F11Z7ADNA
R5F11ZBAAFP
R5F11ZBADFP
Note Functions supported in FSL Type01 are only basic functions. Other functions are not supported.
Basic functions: FSL_Init, FSL_Open, FSL_Close, FSL_PrepareFunctions, FSL_BlankCheck, FSL_Erase,
FSL_IVerify, FSL_Write, and FSL_StatusCheck
R01DS0371EJ0100 Rev.1.00
Nov 29, 2019
Page 2 of 39
RL78/G1P
1. OUTLINE
1.2 List of Part Numbers
Figure 1-1. Part Number, Memory Size, and Package
Part No.
R5F11ZxAxxx#x0
Packaging specification
#00, #20: Tray (HWQFN)
#40:
Embossed Tape (HWQFN)
#10, #30: Tray (LQFP)
#50:
Embossed Tape (LQFP)
Package type:
NA: HWQFN, 4 × 4 mm, 0.50 mm pitch
FP: LQFP, 7 × 7 mm, 0.80 mm pitch
Fields of application:
A: Consumer applications, TA = -40 to +85°C
D: Industrial applications, TA = -40 to +85°C
ROM capacity:
A: 16 KB
Pin count:
7: 24-pin
B: 32-pin
RL78/G1P group
Memory type:
F: Flash memory
Renesas MCU
Renesas semiconductor product
Pin Count
24 pins
Package
24-pin plastic HWQFN
Data Flash
2 KB
A
Fields of
Packaging
Application
Specification
Tray
(4 × 4 mm, 0.5 mm pitch)
Part Number
R5F11Z7AANA#00,
R5F11Z7AANA#20
D
Embossed Tape
R5F11Z7AANA#40
Tray
R5F11Z7ADNA#00,
R5F11Z7ADNA#20
Embossed Tape
32 pins
32-pin plastic LQFP
A
Tray
(7 × 7 mm, 0.8 mm pitch)
R5F11Z7ADNA#40
R5F11ZBAAFP#10,
R5F11ZBAAFP#30
Embossed Tape
D
Tray
R5F11ZBAAFP#50
R5F11ZBADFP#10,
R5F11ZBADFP#30
Embossed Tape
R01DS0371EJ0100 Rev.1.00
Nov 29, 2019
R5F11ZBADFP#50
Page 3 of 39
RL78/G1P
1. OUTLINE
1.3 Pin Configuration (Top View)
1.3.1 24-pin products
P27/ANI7
P10/ANI16
P12/TI03/TO03/INTP4/PCLBUZ0
P13/TI00/TO00
P15/PCLBUZ1
P16/TI01/TO01/INTP5
24-pin plastic HWQFN (4 × 4 mm, 0.5 mm pitch)
exposed die pad
INDEX MARK
18 17 16 15 14 13
12
19
11
20
10
21
9
22
8
23
7
24
1 2 3 4 5 6
P30/INTP2/TxD0/TOOLTxD/SO00
P31/INTP1/RxD0/TOOLRxD/SI00
P32/INTP3/SCK00
P33/TI02/TO02/SSI00
P61/SDAA0/SDAA1
P60/SCLA0/SCLA1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P22/ANI2/ANO0
P23/ANI3/ANO1
P40/TOOL0
RESET
Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. It is recommended to connect an exposed die pad to VSS.
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Nov 29, 2019
Page 4 of 39
RL78/G1P
1. OUTLINE
1.3.2 32-pin products
P10
P11
P12/TI03/TO03/INTP4/PCLBUZ0
P13/TI00/TO00
P14
P15/PCLBUZ1
P16/TI01/TO01/INTP5
P17
32-pin plastic LQFP (7 × 7 mm, 0.8 mm pitch)
24 23 22 21 20 19 18 17
25
16
26
15
27
14
28
13
29
12
30
11
31
10
32
9
1 2 3 4 5 6 7 8
P30/INTP2/TxD0/TOOLTxD/SO00
P31/INTP1/RxD0/TOOLRxD/SI00
P32/INTP3/SCK00
P33/TI02/TO02/SSI00
P34
P35
P61/SDAA0/SDAA1
P60/SCLA0/SCLA1
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P27/ANI7
P26/ANI6
P25/ANI5
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P22/ANI2/ANO0
P23/ANI3/ANO1
P24/ANI4
Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 F).
Remark
For pin identification, see 1.4 Pin Identification.
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Nov 29, 2019
Page 5 of 39
RL78/G1P
1. OUTLINE
1.4 Pin Identification
ANI0 to ANI7, ANI16: Analog input
RxD0:
Receive data
ANO0, ANO1:
Analog output
SCK00:
Serial clock input/output
AVREFM:
Analog reference voltage
SCLA0, SCLA1:
Serial clock input/output
minus
SDAA0, SDAA1:
Serial data input/output
AVREFP:
Analog reference voltage
SI00:
Serial data input
plus
SO00:
Serial data output
EXCLK:
External clock input
SSI00:
Serial interface chip select input
(main system clock)
TI00 to TI03:
Timer input
INTP0 to INTP5:
External Interrupt Input
TO00 to TO03:
Timer output
P10 to P17:
Port 1
TOOL0:
Data input/output for tool
P20 to P27:
Port 2
TOOLRxD, TOOLTxD:
Data input/output for external device
P30 to P35:
Port 3
TxD0:
Transmit data
P40:
Port 4
VDD:
Power supply
P60, P61:
Port 6
VSS:
Ground
P121, P122:
Port 12
X1, X2:
Crystal oscillator (main system clock)
P137:
Port 13
PCLBUZ0, PCLBUZ1: Programmable clock
output/buzzer output
REGC:
Regulator capacitance
RESET:
Reset
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Nov 29, 2019
Page 6 of 39
RL78/G1P
1. OUTLINE
1.5 Block Diagram
1.5.1 24-pin products
TIMER ARRAY
UNIT (4ch)
TI00/TO00/P13
ch0
PORT 1
5
P10, P12, P13,
P15, P16
TI01/TO01/P16
ch1
PORT 2
5
P20 to P23,
P27
TI02/TO02/P33
ch2
PORT 3
4
P30 to P33
TI03/TO03/P12
ch3
PORT 4
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHI P
OSCILLATOR
PORT 6
2
P60, P61
PORT 12
2
P121, P122
PORT 13
SERIAL ARRAY
UNIT0 (2ch)
RxD0/P31
TxD0/P30
P40
P137
ANI0/P20 to
ANI3/P23,
ANI7/P27,
ANI16/P10
6
CODE FLASH MEMORY
RL78 CPU CORE
A/D CONVERTER
UART0
AV REFP/P20
AV REFM /P21
DATA FLASH MEMORY
SCK00/P32
SI00/P31
SO00/P30
SSI00/P33
SDAA0/SDAA1/P61
SCLA0/SCLA1/P60
CSI00
POWER ON RESET/
VOLTAGE
DETECTOR
SERIAL
INTERFACE
IICA0/IICA1
POR/LVD
CONTROL
RAM
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
VDD
VSS
TOOLRxD/P31,
TOOLTxD/P30
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
ON-CHIP
BUZZER OUTPUT
2
CLOCK OUTPUT
CONTROL
PCLBUZ0/P12,
PCLBUZ1/P15
OSCILLATOR
VOLTAGE
REGULATOR
REGC
DIRECT MEMORY
ACCESS CONTROL
EVENT LINK
CONTROLLER
BCD
ADJUSTMENT
R01DS0371EJ0100 Rev.1.00
Nov 29, 2019
INTERRUPT
CONTROL
D/A CONVERTER
6
2
INTP0/P137,
INTP1/P31,
INTP2/P30,
INTP3/P32,
INTP4/P12,
INTP5/P16
ANO0/P22,
ANO1/P23
Page 7 of 39
RL78/G1P
1. OUTLINE
1.5.2 32-pin products
TIMER ARRAY
UNIT (4ch)
TI00/TO00/P13
ch0
PORT 1
8
P10 to P17
TI01/TO01/P16
ch1
PORT 2
8
P20 to P27
TI02/TO02/P33
ch2
PORT 3
6
P30 to P35
TI03/TO03/P12
ch3
PORT 4
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHI P
OSCILLATOR
SCK00/P32
SI00/P31
SO00/P30
2
P60, P61
PORT 12
2
P121, P122
P137
ANI0/P20 to
ANI7/P27
8
CODE FLASH MEMORY
RL78 CPU CORE
A/D CONVERTER
UART0
AV REFP/P20
AV REFM /P21
DATA FLASH MEMORY
CSI00
POWER ON RESET/
VOLTAGE
DETECTOR
SSI00/P33
SDAA0/SDAA1/P61
SCLA0/SCLA1/P60
PORT 6
PORT 13
SERIAL ARRAY
UNIT0 (2ch)
RxD0/P31
TxD0/P30
P40
SERIAL
INTERFACE
IICA0/IICA1
POR/LVD
CONTROL
RAM
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
VDD
VSS
TOOLRxD/P31,
TOOLTxD/P30
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
ON-CHIP
BUZZER OUTPUT
2
CLOCK OUTPUT
CONTROL
PCLBUZ0/P12,
PCLBUZ1/P15
OSCILLATOR
VOLTAGE
REGULATOR
REGC
DIRECT MEMORY
ACCESS CONTROL
EVENT LINK
CONTROLLER
BCD
ADJUSTMENT
R01DS0371EJ0100 Rev.1.00
Nov 29, 2019
INTERRUPT
CONTROL
D/A CONVERTER
6
2
INTP0/P137,
INTP1/P31,
INTP2/P30,
INTP3/P32,
INTP4/P12,
INTP5/P16
ANO0/P22,
ANO1/P23
Page 8 of 39
RL78/G1P
1. OUTLINE
1.6 Outline of Functions
(1/2)
Item
24-pin
32-pin
R5F11Z7AANA, R5F11Z7ADNA
R5F11ZBAAFP, R5F11ZBADFP
Code flash memory
16 KB
Data flash memory
2 KB
RAM
1.5 KBNote
Memory space
1 MB
Main system
High-speed
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
clock
system clock
1 to 20 MHz: VDD = 2.7 to 3.6 V
High-speed on-
High-speed operation: 32 MHz (VDD = 2.7 to 3.6 V)
chip oscillator
clock (fIH)
Low-speed on-chip oscillator clock
15 kHz (TYP.): VDD = 2.7 to 3.6 V
General-purpose registers
8 bits 32 registers (8 bits 8 registers 4 banks)
Minimum instruction execution time
0.03125 s (High-speed on-chip oscillator: fIH = 32 MHz operation)
0.05 s (High-speed system clock: fMX = 20 MHz operation)
Data transfer (8/16 bits)
Instruction set
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits 8 bits)
Rotate, barrel shift, and bit manipulation (set, reset, test, and boolean operation), etc.
I/O port
Total
20
28
CMOS I/O
15
23
CMOS input
3
3
N-ch O.D I/O
2
2
(6 V tolerance)
Timer
16-bit timer
4 channels (TAU)
Watchdog timer
1 channel
Timer output
4
PWM outputs: 3
Clock output/buzzer output
2
2.44 kHz, 4.88 kHz, 9.77 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
8/12-bit resolution A/D converter
6 channels
10-bit D/A converter
2 channels
8 channels
CSI: 1 channel/UART: 1 channel
Serial interface
2
I C bus
1 channel (2 slave addresses)
DMA controller
2 channels
Event link controller (ELC)
Event input: 10, Event trigger output: 3
Vectored
Internal
12
interrupt sources
External
6
Note This is about 0.5 KB when the self-programming function and data flash function are used. For details, see
CHAPTER 3 in the RL78/G1P User’s Manual.
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Page 9 of 39
RL78/G1P
1. OUTLINE
(2/2)
Item
24-pin
32-pin
R5F11Z7AANA, R5F11Z7ADNA
R5F11ZBAAFP, R5F11ZBADFP
Reset by RESET pin
Reset
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
Internal reset by illegal instruction executionNote
Internal reset by RAM parity error
Internal reset by illegal-memory access
Power-on-reset circuit
Power-on-reset:
1.51 0.03 V
Power-down-reset: 1.50 0.03 V
Voltage detector
2.75 V to 3.13 V (4 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 2.7 to 3.6 V
Operating ambient temperature
TA = 40 to +85C
Note
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
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Page 10 of 39
RL78/G1P
2. ELECTRICAL SPECIFICATIONS
2. ELECTRICAL SPECIFICATIONS
Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development
and evaluation.
Do not use the on-chip debug function in products designated for mass
production, because the guaranteed number of rewritable times of the flash memory may be
exceeded when this function is used, and product reliability therefore cannot be guaranteed.
Renesas Electronics is not liable for problems occurring when the on-chip debug function is
used.
2. The pins mounted depend on the product. See 2.1 Pin Function List to 2.2.1 With functions for
each product in the RL78/G1P User’s Manual.
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Page 11 of 39
RL78/G1P
2. ELECTRICAL SPECIFICATIONS
2.1 Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25C) (1/2)
Parameter
Supply voltage
REGC pin input voltage
Symbols
Ratings
Unit
VDD
0.5 to +4.6
V
VSS
0.5 to +0.3
V
0.3 to +2.8
V
VIREGC
Conditions
REGC
and 0.3 to VDD +0.3Note 1
Input voltage
VI1
P10 to P17, P20 to P27, P30 to P35, P40, P121,
0.3 to VDD +0.3Note 2
V
0.3 to +6.5
V
P122, P137
VI2
Output voltage
VO1
P60, P61 (N-ch open-drain)
P10 to P17, P20 to P27, P30 to P35, P40, P60,
0.3 to VDD +0.3
Note 2
V
P61, P121, P122, P137
Analog input voltage
VAI1
ANI0 to ANI7, ANI16
0.3 to VDD +0.3
V
and 0.3 to AVREF(+) +0.3Notes 2, 3
Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
This value regulates the absolute
maximum rating of the REGC pin. Do not use this pin with voltage applied to it.
2.
Must be 4.6 V or lower.
3.
Do not exceed AVREF(+) + 0.3 V in case of A/D conversion target pin.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure that
the absolute maximum ratings are not exceeded.
Remarks 1.
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
2.
AVREF(+): + side reference voltage of the A/D converter.
3.
VSS: Reference voltage
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Page 12 of 39
RL78/G1P
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C) (2/2)
Parameter
Output current, high
Symbols
IOH1
IOH2
Conditions
IOL1
Unit
40
mA
Per pin
P10 to P17, P30 to P35, P40
Total of all pins
140 mA
P40
40
mA
P10 to P17, P30, P35
100
mA
Per pin
P20 to P27
0.5
mA
2
mA
40
mA
Total of all pins
Output current, low
Ratings
Per pin
P10 to P17, P30 to P35, P40, P60,
P61
IOL2
Total of all pins
P40
40
mA
140 mA
P10 to P17, P30 to P35, P60, P61
100
mA
Per pin
P20 to P27
1
mA
5
mA
40 to +85
C
Total of all pins
Operating ambient
TA
temperature
Storage temperature
In normal operation mode
In flash memory programming mode
Tstg
0 to +40
65 to +150
C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure that
the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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Page 13 of 39
RL78/G1P
2. ELECTRICAL SPECIFICATIONS
2.2 Oscillator Characteristics
2.2.1 X1 oscillator characteristics
(TA = 40 to +85C, 2.7 V VDD 3.6 V, VSS = 0 V)
Parameter
Resonator
X1 clock oscillation
Ceramic resonator/
frequency (fX)Note
crystal resonator
Conditions
2.7 V VDD 3.6 V
MIN.
TYP.
1.0
MAX.
Unit
20.0
MHz
Note Indicates only oscillator characteristics. See 2.4 AC Characteristics for instruction execution time.
Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator
characteristics.
Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1
clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC)
by the user.
Determine the oscillation stabilization time of the OSTC register and the oscillation
stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time
with the resonator to be used.
Remark
When using the X1 oscillator, refer to 5.4 System Clock Oscillator in the RL78/G1P User’s Manual.
2.2.2 On-chip oscillator characteristics
(TA = 40 to +85C, 2.7 V VDD 3.6 V, VSS = 0 V)
Oscillators
High-speed on-chip oscillator
Parameters
fIH
Conditions
MIN.
TYP.
MAX.
Unit
32 MHz selected
1
32
MHz
clock frequencyNotes 1, 2
24 MHz selected
1
24
MHz
High-speed on-chip oscillator
-20 to +85°C
2.7 V ≤ VDD ≤ 3.6 V
-1.0
+1.0
%
clock frequency accuracy
-40 to -20°C
2.7 V ≤ VDD ≤ 3.6 V
-1.5
+1.5
%
Low-speed on-chip oscillator
15
fIL
kHz
clock frequencyNote 2
Low-speed on-chip oscillator
-15
+15
%
clock frequency accuracy
Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H) and bits 0 to 2 of
HOCODIV register.
2. This indicates the oscillator characteristics only. See 2.4 AC Characteristics for instruction execution time.
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Page 14 of 39
RL78/G1P
2. ELECTRICAL SPECIFICATIONS
2.3 DC Characteristics
2.3.1 Pin characteristics
(TA = 40 to +85C, 2.7 V VDD 3.6 V, VSS = 0 V) (1/3)
Items
Symbol
Output current, highNote 1
IOH1
IOH2
Notes 1.
Conditions
MIN.
TYP.
MAX.
Unit
2.0Note 2
mA
Total of P10 to P17, P30 to P35
(When duty ≤ 70%Note 3)
19.0
mA
Total of all pins
(When duty ≤ 70%Note 3)
21.0
mA
Per pin for P20 to P27
0.1
mA
Total of all pins
(When duty ≤ 70%Note 3)
0.8
mA
Per pin for P10 to P17, P30 to P35, P40
Value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an
output pin.
2.
Do not exceed the total current value.
3.
Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the
following expression (when changing the duty factor from 70% to n%).
Total output current of pins = (IOH × 0.7)/(n × 0.01)
Where n = 80% and IOH = 19.0 mA
Total output current of pins = (19.0 × 0.7)/(80 × 0.01) = 16.625 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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Page 15 of 39
RL78/G1P
2. ELECTRICAL SPECIFICATIONS
(TA = 40 to +85C, 2.7 V VDD 3.6 V, VSS = 0 V) (2/3)
Items
Symbol
Output current, lowNote 1
IOL1
IOL2
Notes 1.
MAX.
Unit
Per pin for P10 to P17, P30 to P35, P40
Conditions
MIN.
TYP.
3.0Note 2
mA
Per pin for P60, P61
3.0Note 2
mA
Total of P10 to P17, P30 to P35, P60, P61
(When duty ≤ 70%Note 3)
35.0
mA
Total of all pins
(When duty ≤ 70%Note 3)
38.0
mA
Per pin for P20 to P27
0.4
mA
Total of all pins
(When duty ≤ 70%Note 3)
3.2
mA
Value of current at which the device operation is guaranteed even if the current flows from an output pin to
the VSS pin.
2.
However, do not exceed the total current value.
3.
Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the
following expression (when changing the duty factor from 70% to n%).
Total output current of pins = (IOL × 0.7)/(n × 0.01)
Where n = 80% and IOL = 35.0 mA
Total output current of pins = (35.0 × 0.7)/(80 × 0.01) = 30.625 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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Page 16 of 39
RL78/G1P
2. ELECTRICAL SPECIFICATIONS
(TA = 40 to +85C, 2.7 V VDD 3.6 V, VSS = 0 V) (3/3)
Items
Input voltage, high
Symbol
VIH1
Conditions
MIN.
P10 to P17, P30 to P35, P40, P121, P122, P137,
TYP.
MAX.
Unit
0.8VDD
VDD
V
EXCLK, RESET
Input voltage, low
VIH2
P20 to P27
0.7VDD
VDD
V
VIH3
P60, P61
0.7VDD
6.0
V
VIL1
P10 to P17, P30 to P35, P40, P121, P122, P137,
0
0.2VDD
V
0
0.3VDD
V
EXCLK, RESET
Output voltage, high
VIL2
P20 to P27, P60, P61
VOH1
P10 to P17, P30 to
IOH1 = 2.0 mA
VDD 0.6
V
P20 to P27
IOH1 = 100 A
VDD 0.5
V
P10 to P17, P30 to
IOL1 = 3.0 mA
0.6
V
P35, P40
IOL1 = 1.5 mA
0.4
V
P35, P40
VOH2
Output voltage, low
Input leakage current,
VOL1
VOL2
P20 to P27
IOL2 = 400 A
0.4
V
VOL3
P60, P61
IOL3 = 3.0 mA
0.4
V
ILIH1
P10 to P17, P20 to
VI = VDD
1
A
1
A
10
A
1
A
1
A
10
A
100
k
P27, P30 to P35,
high
P40, P137, RESET
ILIH2
P121, P122
VI = VDD
(X1, X2, EXCLK)
In input port or
external clock input
In resonator
connection
Input leakage current,
ILIL1
P10 to P17, P20 to
VI = VSS
P27, P30 to P35,
low
P40, P137, RESET
ILIL2
P121, P122
(X1, X2, EXCLK)
VI = VSS
In input port or
external clock input
In resonator
connection
On-chip pull-up
RU
Remark
P10 to P17, P30 to
VI = VSS, In input port
10
20
P35, P40
resistance
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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Page 17 of 39
RL78/G1P
2. ELECTRICAL SPECIFICATIONS
2.3.2 Supply current characteristics
(TA = 40 to +85C, 2.7 V VDD 3.6 V, VSS = 0 V) (1/3)
Parameter
Supply
Symbol
I
Note 1
DD1
current
Conditions
Operating
HS (high-
mode
speed main)
fIH = 32 MHz
Note 3
MIN.
Basic
TYP.
MAX.
Unit
VDD = 3.0 V
2.1
mA
VDD = 3.0 V
4.8
7.0
mA
VDD = 3.0 V
3.8
5.5
mA
VDD = 3.0 V
2.8
4.0
mA
VDD = 3.0 V
1.3
2.0
mA
Normal
Square wave input
3.3
4.6
mA
operation
Resonator
3.5
4.8
operation
modeNote 4
Normal
operation
fIH = 24 MHzNote 3
Normal
operation
fIH = 16 MHz Note 3
Normal
operation
fIH = 8 MHzNote 3
LS (lowspeed main)
Normal
operation
modeNote 4
HS (high-
fMX = 20 MHzNote 2,
speed main) VDD = 3.0 V
modeNote 4
connection
fMX = 10 MHzNote 2,
Normal
Square wave input
2.0
2.7
VDD = 3.0 V
operation
Resonator
2.1
2.7
mA
connection
LS (low-
fMX = 8 MHzNote 2,
speed main) VDD = 3.0 V
Normal
Square wave input
1.2
2.0
operation
Resonator
1.2
2.0
modeNote 4
mA
connection
Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed
to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not
including the current flowing into the A/D converter, D/A converter, LVD circuit, I/O port, and on-chip pullup/pull-down resistors and the current flowing during data flash rewrite.
2. When high-speed on-chip oscillator is stopped.
3. When high-speed system clock is stopped.
4. Relationship between operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: @1 MHz to 32 MHz
LS (low-speed main) mode:
@1 MHz to 8 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. Temperature condition of the TYP. value is TA = 25C
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Page 18 of 39
RL78/G1P
2. ELECTRICAL SPECIFICATIONS
(TA = 40 to +85C, 2.7 V VDD 3.6 V, VSS = 0 V) (2/3)
Parameter
Symbol
Supply
Note 2
DD2
I
currentNote 1
Conditions
HALT
mode
MIN.
MAX.
Unit
VDD = 3.0 V
0.60
1.63
mA
VDD = 3.0 V
0.49
1.28
mA
Note 4
VDD = 3.0 V
0.45
1.00
mA
VDD = 3.0 V
320
530
A
0.28
1.00
mA
0.49
1.17
mA
0.19
0.60
mA
0.30
0.67
mA
95
330
A
145
380
fIH = 16 MHz
LS (low-speed
fIH = 8 MHz
main) modeNote 6
Note 4
HS (high-speed fMX = 20 MHzNote 3, Square wave input
main) modeNote 6
VDD = 3.0 V
Resonator connection
fMX = 10 MHz
Note 3
, Square wave input
VDD = 3.0 V
LS (low-speed
fMX = 8 MHz
Resonator connection
Note 3
,
main) modeNote 6 VDD = 3.0 V
IDD3Note 5
TYP.
HS (high-speed fIH = 32 MHz
main) modeNote 6
fIH = 24 MHzNote 4
Note 4
Square wave input
Resonator connection
A
STOP
TA = 40C
0.18
mode
TA = +25C
0.23
0.50
TA = +50C
0.26
1.10
TA = +70C
0.29
1.90
TA = +85C
0.90
3.30
Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed
to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not
including the current flowing into the A/D converter, D/A converter, LVD circuit, I/O port, and on-chip pull-up/pulldown resistors and the current flowing during data flash rewrite.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator is stopped.
4. When high-speed system clock is stopped.
5. When high-speed on-chip oscillator and high-speed system clock are stopped.
When watchdog timer is
stopped. The values below the MAX. column include the leakage current.
6. Relationship between operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: @1 MHz to 32 MHz
LS (low-speed main) mode:
@1 MHz to 8 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. Except STOP mode, temperature condition of the TYP. value is TA = 25C
R01DS0371EJ0100 Rev.1.00
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Page 19 of 39
RL78/G1P
2. ELECTRICAL SPECIFICATIONS
(TA = 40 to +85C, 2.7 V VDD 3.6 V, VSS = 0 V) (3/3)
Parameter
Watchdog timer
Symbol
IWDT
Notes 1, 2, 3
Conditions
MIN.
TYP.
fIL = 15 kHz
0.22
VDD = 3.0 V, When conversion at maximum speed
0.58
MAX.
Unit
A
operating current
A/D converter
operating current
IADCNotes 1, 4
A/D converter
reference voltage
current
IADREFNote 1
75.0
A
Temperature sensor
operating current
ITMPSNote 1
75.0
A
D/A converter
operating current
IDACNotes 1, 5
LVD operating
ILVINotes 1, 6
0.08
IFSPNotes 1, 8
2.50
12.20
mA
IBGONotes 1, 7
2.50
12.20
mA
0.82
2
mA
mA
A
current
Self-programming
operating current
BGO operating
current
Notes 1. Current flowing to VDD.
2. When high speed on-chip oscillator and high-speed system clock are stopped.
3. Current flowing only to the watchdog timer (including the operating current of the 15 kHz low-speed on-chip
oscillator). The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the
watchdog timer is in operation.
4. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or
IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.
5. Current flowing only to the D/A converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or
IDD2 and IDAC when the D/A converter operates in an operation mode or the HALT mode.
6. Current flowing only to the LVD circuit. The supply current value of the RL78 microcontrollers is the sum of IDD1,
IDD2 or IDD3 and ILVD when the LVD circuit is in operation.
7. Current flowing during programming of the data flash.
8. Current flowing during self-programming.
Remarks 1. fIL:
Low-speed on-chip oscillator clock frequency
2. fCLK: CPU/peripheral hardware clock frequency
3. Temperature condition of the TYP. value is TA = 25C
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Nov 29, 2019
Page 20 of 39
RL78/G1P
2. ELECTRICAL SPECIFICATIONS
2.4 AC Characteristics
(TA = 40 to +85C, 2.7 V VDD 3.6 V, VSS = 0 V)
Items
Instruction cycle (minimum
Symbol
MIN.
TYP.
MAX.
Unit
HS (high-speed main) mode
0.03125
1
s
LS (low-speed main) mode
0.125
1
s
In the self-
HS (high-speed main) mode
0.03125
1
s
programming mode
LS (low-speed main) mode
0.125
1
s
fEX
1.0
20.0
MHz
tEXH,
24
ns
1/fMCK+10
ns
TCY
Main system clock
(fMAIN) operation
instruction execution time)
External system clock
Conditions
frequency
External system clock input
high-level width, low-level width tEXL
TI00 to TI03 input high-level
tTIH,
width, low-level width
tTIL
TO00 to TO03 output frequency fTO
PCLBUZ0, PCLBUZ1 output
fPCL
frequency
Interrupt input high-level width,
tINTH,
low-level width
tINTL
RESET low-level width
tRSL
HS (high-speed main) mode
8
MHz
LS (low-speed main) mode
4
MHz
HS (high-speed main) mode
8
MHz
LS (low-speed main) mode
4
MHz
INTP0 to INTP5
1
s
10
s
Remark fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKSmn0 and CKSmn1 bits of timer mode register mn (TMRmn).
m: Unit number (m = 0), n: Channel number (n = 0 to 3))
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RL78/G1P
2. ELECTRICAL SPECIFICATIONS
Minimum Instruction Execution Time during Main System Clock Operation
TCY vs VDD (HS (high-speed main) mode)
10
1.0
Cycle time TCY [μs]
When the high-speed on-chip oscillator clock is selected
During self-programming
When high-speed system clock is selected
0.1
0.05
0.03125
0.01
0
1.0
2.0
3.0
4.0
2.7
3.6
Supply voltage VDD [V]
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Page 22 of 39
RL78/G1P
2. ELECTRICAL SPECIFICATIONS
TCY vs VDD (LS (low-speed main) mode)
10
When the high-speed on-chip oscillator clock is selected
Cycle time TCY [μs]
1.0
During self-programming
When high-speed system clock is selected
0.125
0.1
0.01
0
1.0
2.0
3.0
2.7
4.0
3.6
Supply voltage VDD [V]
AC Timing Test Points
VIH/VOH
VIH/VOH
Test points
VIL/VOL
VIL/VOL
External System Clock Timing
1/f EX
t EXL
t EXH
EXCLK
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RL78/G1P
2. ELECTRICAL SPECIFICATIONS
TI/TO Timing
t TIL
t TIH
TI00 to T03
1/f TO
TO00 to TO03
Interrupt Request Input Timing
tINTH
tINTL
INTP0 to INTP5
RESET Input Timing
tRSL
RESET
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RL78/G1P
2. ELECTRICAL SPECIFICATIONS
2.5 Peripheral Functions Characteristics
AC Timing Test Points
VIH/VOH
VIH/VOH
Test points
VIL/VOL
VIL/VOL
2.5.1 Serial array unit
(1) During communication at same potential (UART mode)
(TA = 40 to +85C, 2.7 V VDD 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
LS (low-speed main)
main) Mode
Mode
MIN.
Note 1
Transfer rate
2.7 V ≤ VDD ≤ 3.6 V
Theoretical value of the maximum transfer rate
TYP.
MIN.
Unit
MAX.
fMCK/6
fMCK/6
bps
5.3
1.3
Mbps
fMCK = fCLK Note 2
UART mode connection diagram (during communication at same potential)
TxDq
Rx
User's device
RL78 microcontroller
RxDq
Tx
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 32 MHz (2.7 V ≤ VDD ≤ 3.6 V)
LS (low-speed main) mode: 8 MHz (2.7 V ≤ VDD ≤ 3.6 V).
Remarks 1.
2.
q: UART number (q = 0)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01))
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RL78/G1P
2. ELECTRICAL SPECIFICATIONS
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = -40 to +85C, 2.7 V ≤ VDD ≤ 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode LS (low-speed main) Mode Unit
MIN.
SCKp cycle time
tKCY1
SCKp high-/low-level width
SIp setup time (to SCKp↑)
tKH1, tKL1
Note 1
SIp hold time (from SCKp↑)
Delay time from SCKp↓ to SOp output
tKSO1
C = 20 pF
MAX.
250
ns
tKCY1/2 - 10
tKCY1/2 - 50
ns
33
110
ns
10
10
ns
tKSI1
Note 2
MIN.
83.3
tSIK1
Note 1
MAX.
Note 3
10
10
ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” and
the SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. C is the load capacitance of the SCKp and SOp output lines.
Remarks 1.
2.
p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
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RL78/G1P
2. ELECTRICAL SPECIFICATIONS
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = 40 to +85C, 2.7 V VDD 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Mode
MIN.
Note 4
SCKp cycle time
tKCY2
SCKp high-/low-level width
SIp setup time (to SCKp)Note 1
SIp hold time (from SCKp)
Note 1
MAX.
LS (low-speed main)
Mode
MIN.
Unit
MAX.
16 MHz < fMCK
8/fMCK
-
ns
fMCK 16 MHz
6/fMCK
6/fMCK
ns
tKH2,
tKL2
tKCY2/2-8
tKCY2/2-8
ns
tSIK2
1/fMCK+20
1/fMCK+30
ns
1/fMCK+31
1/fMCK+31
ns
tKSI2
Delay time from SCKp to SOp output
tKSO2
C = 30 pF
SSI00 setup time
tSSIK
DAPmn = 0
120
120
ns
DAPmn = 1
1/fMCK+120
1/fMCK+120
ns
DAPmn = 0
1/fMCK+120
1/fMCK+120
ns
DAPmn = 1
120
120
ns
Note 2
SSI00 hold time
tKSSI
Note 3
2/fMCK+44
2/fMCK+110
ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp” and
the SIp hold time becomes “from SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. C is the load capacitance of the SOp output lines.
4. Transfer rate in the SNOOZE mode: MAX. 1 Mbps
Remarks 1.
2.
p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
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RL78/G1P
2. ELECTRICAL SPECIFICATIONS
CSI mode connection diagram (during communication at same potential)
SCKp
RL78
microcontroller
SCK
SIp
SO
SOp
SI
User's device
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1, 2
tKL1, 2
tKH1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
Output data
SOp
tKSSI
tSSIK
SSI00
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1, 2
tKH1, 2
tKL1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
Output data
SOp
tSSIK
tKSSI
SSI00
Remarks 1.
2.
p: CSI number (p = 00)
m: Unit number, n: Channel number (mn = 00)
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RL78/G1P
2. ELECTRICAL SPECIFICATIONS
2.5.2 Serial interface IICA
(TA = 40 to +85C, 2.7 V VDD 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
Standard
Mode
MIN.
SCLAn clock frequency
MAX.
Fast Mode
MIN.
MAX.
Fast mode plus:
fCLK 10 MHz
fSCL
Fast mode:
fCLK 3.5 MHz
0
Normal mode:
fCLK 1 MHz
0
Fast Mode
Plus
MIN.
MAX.
0
1000
400
Unit
kHz
kHz
100
kHz
tSU:STA
4.7
0.6
0.26
s
Hold time
tHD:STA
4.0
0.6
0.26
s
Hold time when SCLAn = “L”
tLOW
4.7
1.3
0.5
s
Hold time when SCLAn = “H”
tHIGH
4.0
0.6
0.26
s
tSU:DAT
250
100
50
ns
Setup time of restart condition
Note 1
Data setup time (reception)
Data hold time (transmission)
Note 2
0
tSU:STO
4.0
0.6
0.26
s
Bus-free time
tBUF
4.7
1.3
0.5
s
Notes 1.
2.
3.45
0
0.9
0
0.45
s
tHD:DAT
Setup time of stop condition
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Remarks 1. The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Standard mode:
Cb = 400 pF, Rb = 2.7 k
Fast mode:
Cb = 320 pF, Rb = 1.1 k
Fast mode plus:
Cb = 120 pF, Rb = 1.1 k
2. n = 0, 1
IICA serial transfer timing
tLOW
tR
SCLA0/SCLA1
tHD;DAT
tHD;STA
tHIGH
tF
tSU;STA
tHD;STA
tSU;STO
tSU;DAT
SDAA0/SDAA1
tBUF
Stop
condition
Start
condition
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Restart
condition
Stop
condition
Page 29 of 39
RL78/G1P
2. ELECTRICAL SPECIFICATIONS
2.5.3 Dedicated Flash Memory Programmer Communication (UART)
(TA = 40 to +85C, 2.7 V VDD 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
Transfer rate
TYP.
115.2 k
MAX.
Unit
1M
bps
2.6 Analog Characteristics
2.6.1 A/D converter characteristics
Classification of A/D converter characteristics
Reference Voltage Reference voltage (+) = AVREFP
Reference voltage (+) = VDD
Reference voltage (+) = VBGR
Input channel
Reference voltage (-) = AVREFM
Reference voltage (-) = VSS
Reference voltage (-) = AVREFM.
ANI0 to ANI7
Refer to 2.6.1 (1)
Refer to 2.6.1 (2)
ANI16
Refer to 2.6.1 (3)
Refer to 2.6.1 (4)
Internal reference voltage
Refer to 2.6.1 (3)
Refer to 2.6.1 (4)
Refer to 2.6.1 (5)
Temperature sensor output voltage
(1) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF () = AVREFM/ANI1 (ADREFM = 1), target ANI
pin: ANI0 to ANI7
(TA = 40 to +85C, 2.7 V VDD 3.6 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage () = AVREFM = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
Unit
12
bit
6.0
LSB
108
s
Resolution
RES
Overall errorNote 1
AINL
12-bit resolution
AVREFP = VDD
Conversion time
tCONV
12-bit resolution
AVREFP = VDD
Zero-scale errorNotes 1, 2
EZS
12-bit resolution
AVREFP = VDD
0.10
%FSR
Full-scale errorNotes 1, 2
EFS
12-bit resolution
AVREFP = VDD
0.10
%FSR
Integral linearity errorNote 1
ILE
12-bit resolution
AVREFP = VDD
2.5
LSB
Differential linearity errorNote 1
DLE
12-bit resolution
AVREFP = VDD
1.5
LSB
Reference voltage (+)
AVREFP
2.7
VDD
V
Reference voltage ()
AVREFM
0.5
0.3
V
Analog input voltage
VAIN
0
AVREFP
V
1.5
V
VBGR
8
MAX.
Select internal reference voltage output
2.7 V VDD 3.6 V, HS (high-speed main) mode
3.375
1.38
1.45
Notes 1. Excludes quantization error (1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
R01DS0371EJ0100 Rev.1.00
Nov 29, 2019
Page 30 of 39
RL78/G1P
2. ELECTRICAL SPECIFICATIONS
(2) When AVREF (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), AVREF () = VSS (ADREFM = 0), target ANI pin: ANI0 to ANI7
(TA = 40 to +85C, 2.7 V VDD 3.6 V, VSS = 0 V, Reference voltage (+) = VSS, Reference voltage () = VSS)
Parameter
Symbol
Resolution
Conditions
RES
Note 1
MIN.
TYP.
8
MAX.
Unit
12
bit
7.0
LSB
108
s
Overall error
AINL
10-bit resolution
Conversion time
tCONV
10-bit resolution
Zero-scale errorNotes 1, 2
EZS
10-bit resolution
0.60
%FSR
EFS
10-bit resolution
0.60
%FSR
ILE
10-bit resolution
4.0
LSB
Differential linearity error
DLE
10-bit resolution
2.0
LSB
Analog input voltage
VAIN
AVREFP
V
1.5
V
Notes 1, 2
Full-scale error
Integral linearity error
Note 1
Note 1
VBGR
3.375
0
Select internal reference voltage output
2.7 V VDD 3.6 V, HS (high-speed main) mode
1.38
1.45
Notes 1. Excludes quantization error (1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
(3) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF () = AVREFM/ANI1 (ADREFM = 1), target ANI
pin: ANI16, internal reference voltage, and temperature sensor output voltage
(TA = 40 to +85C, 2.7 V VDD 3.6 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage () = AVREFM= 0
V)
Parameter
Resolution
Symbol
Conditions
RES
Note 1
MIN.
TYP.
8
MAX.
Unit
12
bit
7.0
LSB
132
s
Overall error
AINL
12-bit resolution
AVREFP = VDD
Conversion time
tCONV
12-bit resolution
AVREFP = VDD
Zero-scale errorNotes 1, 2
EZS
12-bit resolution
AVREFP = VDD
0.10
%FSR
Full-scale errorNotes 1, 2
EFS
12-bit resolution
AVREFP = VDD
0.10
%FSR
Integral linearity errorNote 1
ILE
12-bit resolution
AVREFP = VDD
3.0
LSB
12-bit resolution
AVREFP = VDD
2.0
LSB
Differential linearity errorNote 1 DLE
4.125
Reference voltage (+)
AVREFP
2.7
VDD
V
Reference voltage ()
AVREFM
0.5
0.3
V
Analog input voltage
VAIN
0
AVREFP
V
1.5
V
VBGR
Select internal reference voltage output
2.7 V VDD 3.6 V, HS (high-speed main) mode
1.38
1.45
Notes 1. Excludes quantization error (1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
R01DS0371EJ0100 Rev.1.00
Nov 29, 2019
Page 31 of 39
RL78/G1P
2. ELECTRICAL SPECIFICATIONS
(4) When AVREF
(+)
= VDD (ADREFP1 = 0, ADREFP0 = 0), AVREF
()
= VSS (ADREFM = 0), target ANI pin: ANI16,
internal reference voltage, and temperature sensor output voltage
(TA = 40 to +85C, 2.7 V VDD 3.6 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage () = VSS)
Parameter
Symbol
Resolution
Conditions
RES
Note 1
Overall error
Conversion time
Notes 1, 2
Zero-scale error
Notes 1, 2
Full-scale error
Integral linearity error
Note 1
TYP.
8
MAX.
Unit
12
bit
7.0
LSB
132
s
AINL
10-bit resolution
tCONV
10-bit resolution
EZS
10-bit resolution
0.60
%FSR
EFS
10-bit resolution
0.60
%FSR
ILE
10-bit resolution
4.0
LSB
10-bit resolution
2.5
LSB
VDD
V
1.5
V
Differential linearity error Note 1 DLE
Analog input voltage
MIN.
4.125
VAIN
0
Select internal reference voltage output
2.7 V VDD 3.6 V, HS (high-speed main) mode
VBGR
1.38
1.45
Notes 1. Excludes quantization error (1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
(5) When AVREF (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), AVREF () = AVREFM/ANI1 (ADREFM =
1), target ANI pin: ANI0 to ANI7, ANI16
(TA = 40 to +85C, 2.7 V VDD 3.6 V, VSS = 0 V, Reference voltage (+) = VBGR, Reference voltage () = AVREFM = 0 V,
HS (high-speed main) mode)
Parameter
Symbol
Resolution
Conditions
MIN.
RES
Conversion time
Notes 1, 2
Zero-scale error
Integral linearity error
Note 1
Differential linearity error
Note 1
Analog input voltage
TYP.
MAX.
8
Unit
bit
108
s
8-bit resolution
1.60
%FSR
ILE
8-bit resolution
2.5
LSB
DLE
8-bit resolution
2.5
LSB
VBGR
V
tCONV
8-bit resolution
EZS
VAIN
16
0
Notes 1. Excludes quantization error (1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
R01DS0371EJ0100 Rev.1.00
Nov 29, 2019
Page 32 of 39
RL78/G1P
2. ELECTRICAL SPECIFICATIONS
2.6.2 Temperature sensor/internal reference voltage characteristics
(TA = 40 to +85C, 2.7 V VDD 3.6 V, VSS = 0 V, HS (high-speed main) mode)
Parameter
Symbol
Temperature sensor output
voltage
VTMPS25
Conditions
MIN.
Setting ADS register = 80H, TA = +25C
Internal reference voltage
VBGR
Setting ADS register = 81H
Temperature coefficient
FVTMPS
Temperature sensor that depends on the
temperature
Operation stabilization wait
time
tAMP
TYP.
MAX.
1.05
1.38
1.45
Unit
V
1.5
V
mV/C
-3.6
s
5
2.6.3 D/A converter
(TA = 40 to +85C, 2.7 V VDD 3.6 V, VSS = 0 V)
Parameter
Symbol
Resolution
RES
Overall error
AINL
Conditions
MIN.
TYP.
MAX.
Unit
10
bit
Load current = 0 mA,
0.2 V ≤ output voltage ≤ VDD 0.2 V
2.0
4.0
LSB
Load = 2.5 kΩ,
0.2 V ≤ output voltage ≤ VDD 0.2 V
5.0
10.0
LSB
10
s
Settling time
tSET
Rload = 47 k, Cload = 20 pF
D/A output resistance
RO
Per channel
Output voltage = 0 V to 0.2 V or
Output voltage = VDD 0.2 V to VDD
40
60
Per channel
Output voltage = 0.2 V to VDD 0.2 V
8
12
R01DS0371EJ0100 Rev.1.00
Nov 29, 2019
Page 33 of 39
RL78/G1P
2. ELECTRICAL SPECIFICATIONS
2.6.4 POR circuit characteristics
(TA = 40 to +85C, VSS = 0 V)
Parameter
Detection voltage
Minimum pulse width Note
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V
VPOR
Power supply rise time
1.47
1.51
1.55
VPDR
Power supply fall time
1.46
1.50
1.54
TPW
V
s
300
Note Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for
a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the
main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status
control register (CSC).
TPW
Supply voltage (VDD)
VPOR
VPDR or 0.7 V
R01DS0371EJ0100 Rev.1.00
Nov 29, 2019
Page 34 of 39
RL78/G1P
2. ELECTRICAL SPECIFICATIONS
2.6.5 LVD circuit characteristics
LVD Detection Voltage of Reset Mode and Interrupt Mode
(TA = 40 to +85C, VPDR VDD 3.6 V, VSS = 0 V)
Parameter
Symbol
Detection voltage
VLVD2
VLVD3
VLVD4
VLVD5
Minimum pulse width
Conditions
MIN.
TYP.
MAX.
Unit
Power supply rise time
3.07
3.13
3.19
V
Power supply fall time
3.00
3.06
3.12
V
Power supply rise time
2.96
3.02
3.08
V
Power supply fall time
2.90
2.96
3.02
V
Power supply rise time
2.86
2.92
2.97
V
Power supply fall time
2.80
2.86
2.91
V
Power supply rise time
2.76
2.81
2.87
V
Power supply fall time
2.70
2.75
2.81
V
tLW
s
300
Detection delay time
300
s
LVD Detection Voltage of Interrupt & Reset Mode
(TA = 40 to +85C, VPDR VDD 3.6 V, VSS = 0 V)
Parameter
Detection voltage
Symbol
VLVD5
Conditions
MIN.
TYP.
MAX.
Unit
2.70
2.75
2.81
V
Rising release reset voltage
2.86
2.92
2.97
V
Falling interrupt voltage
2.80
2.86
2.91
V
Rising release reset voltage
2.96
3.02
3.08
V
Falling interrupt voltage
2.90
2.96
3.02
V
MIN.
TYP.
MAX.
Unit
54
V/ms
VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage
VLVD4
VLVD3
LVIS1, LVIS0 = 1, 0
LVIS1, LVIS0 = 0, 1
2.6.6 Power supply voltage rising slope characteristics
(TA = 40 to +85C, VSS = 0 V)
Parameter
Power supply voltage rising slope
Symbol
Conditions
SVDD
Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the
operating voltage range shown in 2.4 AC Characteristics.
R01DS0371EJ0100 Rev.1.00
Nov 29, 2019
Page 35 of 39
RL78/G1P
2. ELECTRICAL SPECIFICATIONS
2.7 RAM data retention characteristics
(TA = 40 to +85C, VSS = 0 V)
Parameter
Data retention supply voltage
Symbol
Conditions
MIN.
TYP.
Note
VDDDR
1.46
MAX.
Unit
3.6
V
Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR
reset is effected, but data is not retained when a POR reset is effected.
Operation mode
STOP mode
Data retention mode
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
2.8 Flash Memory Programming Characteristics
(TA = 40 to +85C, 2.7 V VDD 3.6 V, VSS = 0 V)
Parameter
Symbol
Conditions
System clock frequency
fCLK
2.7 V VDD 3.6 V
Number of code flash rewrites
Cerwr
Retained for 20 years
TA = 85C
Note 1, 2, 3
Number of data flash rewrites
Note 1, 2, 3
In flash memory programming mode
In the self-programming mode
TYP.
1
1,000
MAX.
Unit
32
MHz
Times
1,000,000
Retained for 1 years
TA = 25C
Retained for 5 years
TA = 85C
Operating ambient temperature
MIN.
100,000
0 to +40
C
40 to +85
C
Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite.
The retaining years are until next rewrite after the rewrite.
2. When using flash memory programmer and Renesas Electronics self programming library
3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas
Electronics Corporation.
R01DS0371EJ0100 Rev.1.00
Nov 29, 2019
Page 36 of 39
RL78/G1P
2. ELECTRICAL SPECIFICATIONS
2.9 Timing of Entry to Flash Memory Programming Modes
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
100
ms
How long from when an external
reset ends until the initial
communication settings are
specified
tSUINIT
POR and LVD reset must end before the
external reset ends.
How long from when the TOOL0
pin is placed at the low level until
an external reset ends
tSU
POR and LVD reset must end before the
external reset ends.
10
s
How long the TOOL0 pin must be
kept at the low level after an
external reset ends
(excluding the processing time of
the firmware to control the flash
memory)
tHD
POR and LVD reset must end before the
external reset ends.
1
ms
RESET
723 μs + tHD
processing
time
00H reception
(TOOLRxD, TOOLTxD mode)
TOOL0
tSU
tSUINIT
The low level is input to the TOOL0 pin.
The external reset ends (POR and LVD reset must end before the external reset ends.).
The TOOL0 pin is set to the high level.
Setting of the flash memory programming mode by UART reception and complete the baud
rate setting.
Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within
100 ms from when the resets end.
tSU:
How long from when the TOOL0 pin is placed at the low level until an external reset ends (MIN. 10 s)
tHD:
How long to keep the TOOL0 pin at the low level from when the external and internal resets end
(except software processing time)
R01DS0371EJ0100 Rev.1.00
Nov 29, 2019
Page 37 of 39
RL78/G1P
3. PACKAGE DRAWINGS
3. PACKAGE DRAWINGS
3.1 24-pin Products
R5F11Z7AANA, R5F11Z7ADNA
JEITA Package code
RENESAS code
MASS(TYP.)[g]
P-HWQFN024-4x4-0.50
PWQN0024KF-A
0.04
2X
aaa C
18
13
19
12
D
INDEX AREA
(D/2 X E/2)
24
2X
7
aaa C
6
1
A
E
B
ccc C
C
SEATING PLANE
A (A3) A1
b(24X)
e
24X
bbb
ddd
eee C
E2
fff
1
fff
C A B
24
7
EXPOSED DIE PAD
D2
19
12
18
13
L(24X)
Reference
Symbol
Dimension in Millimeters
Min.
K(24X)
Nom.
Max.
A
–
–
0.80
A1
0.00
0.02
0.05
A3
6
C A B
R01DS0371EJ0100 Rev.1.00
Nov 29, 2019
C A B
C
b
0.203 REF.
0.18
D
0.25
0.30
4.00 BSC
E
4.00 BSC
e
0.50 BSC
L
0.35
0.40
0.45
K
0.20
–
–
D2
2.55
2.60
2.65
E2
2.55
2.60
2.65
aaa
0.15
bbb
0.10
ccc
0.10
ddd
0.05
eee
0.08
fff
0.10
Page 38 of 39
S
32
25
ZD
1
24
e
D
Index mark
*1
y S
8
17
*3
bp
9
16
x
E
F
*2
HD
Previous Code
32P6U-A
ZE
RENESAS Code
PLQP0032GB-A
MASS[Typ.]
0.2g
b1
bp
c1
Detail F
Terminal cross section
A2
R01DS0371EJ0100 Rev.1.00
Nov 29, 2019
A1
JEITA Package Code
P-LQFP32-7x7-0.80
L1
L
e
x
y
ZD
ZE
L
L1
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
Min Nom Max
6.9 7.0 7.1
6.9 7.0 7.1
1.4
8.8 9.0 9.2
8.8 9.0 9.2
1.7
0.1 0.2
0
0.32 0.37 0.42
0.35
0.09 0.145 0.20
0.125
0°
8°
0.8
0.20
0.10
0.7
0.7
0.3 0.5 0.7
1.0
Reference Dimension in Millimeters
Symbol
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
RL78/G1P
3. PACKAGE DRAWINGS
3.2 32-pin Products
R5F11ZBAAFP, R5F11ZBADFP
Page 39 of 39
c
c
A
HE
Revision History
RL78/G1P Datasheet
Description
Rev.
Date
Page
1.00
Nov 29, 2019
—
Summary
First edition issued
All trademarks and registered trademarks are the property of their respective owners.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States
and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
C-1
General Precautions in the Handling of Microprocessing Unit and Microcontroller
Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the
products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
1.
Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps
must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be
adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.
Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor
2.
devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.
Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of
register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset
pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins
in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the
3.
level at which resetting is specified.
Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal
4.
elements. Follow the guideline for input signal during power-off state as described in your product documentation.
Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are
generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of
the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
5.
become possible.
Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program
execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator
during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal
6.
produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the
7.
input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.).
Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these
8.
addresses as the correct operation of the LSI is not guaranteed.
Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.
The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms
of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,
operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a systemevaluation test for the given product.
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by
you or third parties arising from the use of these circuits, software, or information.
2.
Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or
arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application
examples.
3.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.
4.
You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by
5.
Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the
you or third parties arising from such alteration, modification, copying or reverse engineering.
product’s quality grade, as indicated below.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; industrial robots; etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc.
Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are
not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause
serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all
liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or
other Renesas Electronics document.
6.
When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for Handling and Using Semiconductor Devices” in the
reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation
characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such specified
ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a
certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas
Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury
or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult
and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. You are responsible for carefully and
sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics
products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable
laws and regulations.
9.
Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws
or regulations. You shall comply with any applicable export control laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or
transactions.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or transfers the product to a third party, to notify such third
party in advance of the contents and conditions set forth in this document.
11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products.
(Note 1)
“Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries.
(Note 2)
“Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
(Rev.4.0-1 November 2017)
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics Corporation
TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan
Renesas Electronics America Inc.
1001 Murphy Ranch Road, Milpitas, CA 95035, U.S.A.
Tel: +1-408-432-8888, Fax: +1-408-434-5351
Renesas Electronics Canada Limited
9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3
Tel: +1-905-237-2004
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-6503-0, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
Room 101-T01, Floor 1, Building 7, Yard No. 7, 8th Street, Shangdi, Haidian District, Beijing 100085, China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai 200333, China
Tel: +86-21-2226-0888, Fax: +86-21-2226-0999
Renesas Electronics Hong Kong Limited
Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2265-6688, Fax: +852 2886-9022
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit No 3A-1 Level 3A Tower 8 UOA Business Park, No 1 Jalan Pengaturcara U1/51A, Seksyen U1, 40150 Shah Alam, Selangor, Malaysia
Tel: +60-3-5022-1288, Fax: +60-3-5022-1290
Renesas Electronics India Pvt. Ltd.
No.777C, 100 Feet Road, HAL 2nd Stage, Indiranagar, Bangalore 560 038, India
Tel: +91-80-67208700
Renesas Electronics Korea Co., Ltd.
17F, KAMCO Yangjae Tower, 262, Gangnam-daero, Gangnam-gu, Seoul, 06265 Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5338
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