Datasheet
R01DS0376EJ0110
Rev.1.10
Sep 18, 2020
RL78/G13A
RENESAS MCU
RL78/G13A microcontrollers share the functionality of RL78/G13 products but have a much (over 40%) lower operating current of 47 µA/MHz (typ.).
Operation is guaranteed at ambient temperatures up to 105°C while this is not the case for RL78/G13 products with 384 or 512 Kbytes of code flash memory.
RL78/G13A microcontrollers can be used in a wide variety of applications, from home and consumer appliances to industrial equipment.
1. OUTLINE
1.1 Features
Ultra-low power consumption technology
Operating ambient temperature
● VDD = single power supply voltage of 1.6 to 5.5 V
● TA = -40 to +85°C (A: Consumer applications)
● HALT mode
● TA = -40 to +105°C (G: Industrial applications)
● STOP mode
● SNOOZE mode
Power management and reset function
● On-chip power-on-reset (POR) circuit
RL78 CPU core
● On-chip voltage detector (LVD) (Select interrupt
● CISC architecture with 3-stage pipeline
and reset from 14 levels)
● Minimum instruction execution time: Can be
changed from high speed (0.03125 μs: @ 32 MHz
DMA (Direct Memory Access) controller
operation with high-speed on-chip oscillator) to
● 2/4 channels
ultra-low speed (30.5 μs: @ 32.768 kHz operation
● Number of clocks during transfer between 8/16-bit
with subsystem clock)
SFR and internal RAM: 2 clocks
● Address space: 1 MB
● General-purpose registers: (8-bit register × 8) × 4
banks
● On-chip RAM: 24 or 32 KB
Multiplier and divider/multiply-accumulator
● 16 bits × 16 bits = 32 bits (Unsigned or signed)
● 32 bits ÷ 32 bits = 32 bits (Unsigned)
● 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or
Code flash memory
signed)
● Code flash memory: 384 or 512 KB
● Block size: 1 KB
● Prohibition of block erase and rewriting (security
function)
● On-chip debug function
Serial interface
● CSI: 4 to 8 channels
● UART/UART (LIN-bus supported): 3 or 4 channels
● I2C/Simplified I2C communication: 5 to 10
● Self-programming (with boot swap function/flash
channels
shield window function)
Timer
Data flash memory
● 16-bit timer: 8 or 12 channels
● Data flash memory: 8 KB
● 12-bit interval timer: 1 channel
● Back ground operation (BGO): Instructions can be
● Real-time clock:
executed from the program memory while
rewriting the data flash memory.
● Number of rewrites: 1,000,000 times (typ.)
● Voltage of rewrites: VDD = 1.8 to 5.5 V
High-speed on-chip oscillator
● Select from 32 MHz, 24 MHz, 16 MHz, 12 MHz, 8
MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz
● High accuracy: ±1.0% (VDD = 1.6 to 5.5 V, TA = -40
to +85°C)
1 channel (calendar for 99
years, alarm function, and clock correction
function)
● Watchdog timer: 1 channel (operable with the
dedicated low-speed on-chip oscillator)
A/D converter
● 8/10-bit resolution A/D converter (VDD = 1.6 to 5.5
V)
● Analog input: 10 to 20 channels
● Internal reference voltage (1.45 V) and
temperature sensor Note 1
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1
RL78/G13A
1. OUTLINE
Others
I/O port
● I/O port: 40 to 92 (N-ch open drain I/O [withstand
withstand voltage
Note 3]:
Note 2/EVDD
● On-chip BCD (binary-coded decimal) correction
circuit
voltage of 6 V]: 4, N-ch open drain I/O [VDD
withstand voltage
10 to 24)
● Can be set to N-ch open drain, TTL input buffer,
Notes 1. Can be selected only in HS (high-speed main)
mode
and on-chip pull-up resistor
● Different potential interface: Can connect to a
2. 44- and 48-pin products
3. 64- and 100-pin products
1.8/2.5/3 V device
● On-chip key interrupt function
● On-chip clock output/buzzer output controller
Remark The functions mounted depend on the
product. See 1.6 Outline of Functions.
Ο ROM, RAM capacities
Flash ROM
Data flash
512 KB
8 KB
384 KB
8 KB
Note
RAM
32 KB
Note
24 KB
RL78/G13A
44 pins
48 pins
64 pins
100 pins
R5F140FL
R5F140GL
R5F140LL
R5F140PL
R5F140FK
R5F140GK
R5F140LK
R5F140PK
The flash library uses RAM in self-programming and rewriting of the data flash memory.
The target products and start address of the RAM areas used by the flash library are shown below.
R5F140xL (x = F, G, L, P): Start address F7F00H
For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for RL78
Family (R20UT2944).
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RL78/G13A
1. OUTLINE
1.2 List of Part Numbers
Figure 1-1. Part Number, Memory Size, and Package of RL78/G13A
Part No.
R 5 F 1 4 0 L L A x x x F B #50
Packaging specification
#10, #30: Tray (LFQFP, LQFP)
#50: Embossed Tape (LFQFP, LQFP)
Package type:
FP: LQFP, 0.80-mm pitch
FB: LFQFP, 0.50-mm pitch
ROM number (Omitted with blank products)
Fields of application:
A: Consumer applications, TA = -40 to +85C
G: Industrial applications, TA = -40 to +105C
ROM capacity:
K: 384 KB
L: 512 KB
Pin count:
F: 44-pin
G: 48-pin
L: 64-pin
P: 100-pin
RL78/G13A group
140: Data flash is provided
Memory type:
F: Flash memory
Renesas MCU
Renesas semiconductor product
R01DS0376EJ0110 Rev.1.10
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RL78/G13A
1. OUTLINE
Table 1-1. List of Ordering Part Numbers
Pin count
44 pins
Package
44-pin plastic LQFP
Data
Fields of
flash
Application Note
Mounted
A
(10 x 10 mm, 0.8-mm pitch)
Ordering Part Number
R5F140FKAFP#10, R5F140FLAFP#10
R5F140FKAFP#30, R5F140FLAFP#30
R5F140FKAFP#50, R5F140FLAFP#50
G
R5F140FKGFP#10, R5F140FLGFP#10
R5F140FKGFP#30, R5F140FLGFP#30
R5F140FKGFP#50, R5F140FLGFP#50
48 pins
48-pin plastic LFQFP
Mounted
A
(7 x 7 mm, 0.5-mm pitch)
R5F140GKAFB#10, R5F140GLAFB#10
R5F140GKAFB#30, R5F140GLAFB#30
R5F140GKAFB#50, R5F140GLAFB#50
G
R5F140GKGFB#10, R5F140GLGFB#10
R5F140GKGFB#30, R5F140GLGFB#30
R5F140GKGFB#50, R5F140GLGFB#50
64 pins
64-pin plastic LFQFP
Mounted
A
(10 x 10 mm, 0.5-mm pitch)
R5F140LKAFB#10, R5F140LLAFB#10
R5F140LKAFB#30, R5F140LLAFB#30
R5F140LKAFB#50, R5F140LLAFB#50
G
R5F140LKGFB#10, R5F140LLGFB#10
R5F140LKGFB#30, R5F140LLGFB#30
R5F140LKGFB#50, R5F140LLGFB#50
100 pins
100-pin plastic LFQFP
Mounted
A
(14 x 14 mm, 0.5-mm pitch)
R5F140PKAFB#10, R5F140PLAFB#10
R5F140PKAFB#30, R5F140PLAFB#30
R5F140PKAFB#50, R5F140PLAFB#50
G
R5F140PKGFB#10, R5F140PLGFB#10
R5F140PKGFB#30, R5F140PLGFB#30
R5F140PKGFB#50, R5F140PLGFB#50
Note
For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13A.
Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part
numbers, refer to the target product page of the Renesas Electronics website.
R01DS0376EJ0110 Rev.1.10
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RL78/G13A
1. OUTLINE
1.3 Pin Configuration (Top View)
1.3.1 44-pin products
P147/ANI18
P146
P10/SCK00/SCL00/(TI07)/(TO07)
P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06)
P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05)
P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)
P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)
P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02)
P16/TI01/TO01/INTP5/(RxD0)
P17/TI02/TO02/(TxD0)
P51/INTP2/SO11
● 44-pin plastic LQFP (10 × 10 mm, 0.8-mm pitch)
33 32 31 30 29 28 27 26 25 24 23
22
34
21
35
20
36
19
37
RL78/G13A
18
38
17
39
(Top
View)
16
40
15
41
14
42
13
43
12
44
1 2 3 4 5 6 7 8 9 10 11
P50/INTP1/SI11/SDA11
P30/INTP3/RTC1HZ/SCK11/SCL11
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P31/TI03/TO03/INTP4/PCLBUZ0
P63
P62
P61/SDAA0
P60/SCLA0
P41/TI07/TO07
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3
P22/ANI2
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P01/TO00/RxD1
P00/TI00/TxD1
P120/ANI19
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the
RL78/G13A User’s Manual.
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RL78/G13A
1. OUTLINE
1.3.2 48-pin products
P140/PCLBUZ0/INTP6
P00/TI00/TxD1
P01/TO00/RxD1
P130
P20/ANI0/AVREFP
P21/ANI1/AVREFM
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
● 48-pin plastic LFQFP (7 × 7 mm, 0.5-mm pitch)
36 35 34 33 32 31 30 29 28 27 26 25
24
37
23
38
22
39
21
40
20
41
RL78/G13A
19
42
18
43
(Top View)
17
44
16
45
15
46
14
47
13
48
1 2 3 4 5 6 7 8 9 10 11 12
P147/ANI18
P146
P10/SCK00/SCL00/(TI07)/(TO07)
P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06)
P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05)
P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)
P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)
P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02)
P16/TI01/TO01/INTP5/(RxD0)
P17/TI02/TO02/(TxD0)
P51/INTP2/SO11
P50/INTP1/SI11/SDA11
P60/SCLA0
P61/SDAA0
P62
P63
P31/TI03/TO03/INTP4/(PCLBUZ0)
P75/KR5/INTP9/SCK01/SCL01
P74/KR4/INTP8/SI01/SDA01
P73/KR3/SO01
P72/KR2/SO21
P71/KR1/SI21/SDA21
P70/KR0/SCK21/SCL21
P30/INTP3/RTC1HZ/SCK11/SCL11
P120/ANI19
P41/TI07/TO07
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the
RL78/G13A User’s Manual.
R01DS0376EJ0110 Rev.1.10
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RL78/G13A
1. OUTLINE
1.3.3 64-pin products
P50/INTP1/SI11/SDA11
P51/INTP2/SO11
P52/(INTP10)
P53/(INTP11)
P54
P55/(PCLBUZ1)/(SCK00)
P17/TI02/TO02/(SO00)/(TxD0)
P16/TI01/TO01/INTP5/(SI00)/(RxD0)
P15/SCK20/SCL20/(TI02)/(TO02)
P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)
P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)
P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05)
P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06)
P10/SCK00/SCL00/(TI07)/(TO07)
P146
P147/ANI18
● 64-pin plastic LFQFP (10 × 10 mm, 0.5-mm pitch)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3
P22/ANI2
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P04/SCK10/SCL10
P03/ANI16/SI10/RxD1/SDA10
P02/ANI17/SO10/TxD1
P01/TO00
P00/TI00
P141/PCLBUZ1/INTP7
P140/PCLBUZ0/INTP6
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RL78/G13A
(Top View)
P30/INTP3/RTC1HZ/SCK11/SCL11
P05/TI05/TO05
P06/TI06/TO06
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3/SO01
P74/KR4/INTP8/SI01/SDA01
P75/KR5/INTP9/SCK01/SCL01
P76/KR6/INTP10/(RxD2)
P77/KR7/INTP11/(TxD2)
P31/TI03/TO03/INTP4/(PCLBUZ0)
P63
P62
P61/SDAA0
P60/SCLA0
EVDD0
VDD
EVSS0
VSS
REGC
P121/X1
P122/X2/EXCLK
P137/INTP0
P123/XT1
P124/XT2/EXCLKS
RESET
P40/TOOL0
P41/TI07/TO07
P42/TI04/TO04
P43
P120/ANI19
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Cautions 1. Make EVSS0 pin the same potential as VSS pin.
2. Make VDD pin the potential that is no less than EVDD0 pin.
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the microcontroller
must be reduced, it is recommended to supply separate powers to the VDD and EVDD0 pins and connect
the VSS and EVSS0 pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the
RL78/G13A User’s Manual.
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RL78/G13A
1. OUTLINE
1.3.4 100-pin products
P100/ANI20
P147/ANI18
P146/(INTP4)
P111/(INTP11)
P110/(INTP10)
P101
P10/SCK00/SCL00/(TI07)/(TO07)
P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06)
P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05)
P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)
P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)
P15/SCK20/SCL20/(TI02)/(TO02)
P16/TI01/TO01/INTP5/(SI00)/(RxD0)
P17/TI02/TO02/(SO00)/(TxD0)
P57/(INTP3)
P56/(INTP1)
P55/(PCLBUZ1)/(SCK00)
P54/SCK31/SCL31
P53/SI31/SDA31
P52/SO31
P51/SO11
P50/SI11/SDA11
EVDD1
P30/INTP3/RTC1HZ/SCK11/SCL11
P87/(INTP9)
● 100-pin plastic LFQFP (14 × 14 mm, 0.5-mm pitch)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
76
49
77
48
78
47
79
46
80
45
81
44
82
43
83
42
84
41
85
40
86
39
87
38
88
37
89
36
90
35
91
34
92
33
93
32
94
31
95
30
96
29
97
28
98
27
99
26
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
RL78/G13A
(Top View)
P86/(INTP8)
P85/(INTP7)
P84/(INTP6)
P83
P82/(SO10)/(TxD1)
P81/(SI10)/(RxD1)/(SDA10)
P80/(SCK10)/(SCL10)
EVSS1
P05
P06
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P74/KR4/INTP8
P75/KR5/INTP9
P76/KR6/INTP10/(RxD2)
P77/KR7/INTP11/(TxD2)
P67/TI13/TO13
P66/TI12/TO12
P65/TI11/TO11
P64/TI10/TO10
P31/TI03/TO03/INTP4/(PCLBUZ0)
P63/SDAA1
P62/SCLA1
P142/SCK30/SCL30
P141/PCLBUZ1/INTP7
P140/PCLBUZ0/INTP6
P120/ANI19
P47/INTP2
P46/INTP1/TI05/TO05
P45/SO01
P44/SI01/SDA01
P43/SCK01/SCL01
P42/TI04/TO04
P41
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS0
VDD
EVDD0
P60/SCLA0
P61/SDAA0
P156/ANI14
P155/ANI13
P154/ANI12
P153/ANI11
P152/ANI10
P151/ANI9
P150/ANI8
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3
P22/ANI2
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P102/TI06/TO06
P04/SCK10/SCL10
P03/ANI16/SI10/RxD1/SDA10
P02/ANI17/SO10/TxD1
P01/TO00
P00/TI00
P145/TI07/TO07
P144/SO30/TxD3
P143/SI30/RxD3/SDA30
Cautions 1. Make EVSS0 and EVSS1 pins the same potential as VSS pin.
2. Make VDD pin the potential that is no less than EVDD0 and EVDD1 pins (EVDD0 = EVDD1).
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the microcontroller
must be reduced, it is recommended to supply separate powers to the VDD, EVDD0 and EVDD1 pins and
connect the VSS, EVSS0 and EVSS1 pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the
RL78/G13A User’s Manual.
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RL78/G13A
1. OUTLINE
1.4 Pin Identification
ANI0 to ANI14,
REGC:
Regulator capacitance
ANI16 to ANI20:
Analog input
RESET:
Reset
AVREFM:
A/D converter negative
RTC1HZ:
Real-time clock correction clock
reference voltage input
(1 Hz) output
AVREFP:
A/D converter positive
RxD0 to RxD3:
reference voltage input
SCLA0, SCLA1,
EVDD0, EVDD1:
Power supply for port
SCK00, SCK01, SCK10,
EVSS0, EVSS1:
Ground for port
SCK11, SCK20, SCK21,
EXCLK:
External clock input (Main SCK30, SCK31:
EXCLKS:
INTP0 to INTP11:
system clock)
SCL00, SCL01, SCL10,
External clock input
SCL11, SCL20, SCL21,
(Subsystem clock)
SCL30, SCL31:
Interrupt request from
SDAA0, SDAA1, SDA00,
Receive data
Serial clock input/output
Serial clock output
peripheral
SDA01, SDA10, SDA11,
KR0 to KR7:
Key return
SDA20, SDA21, SDA30,
P00 to P06:
Port 0
SDA31:
P10 to P17:
Port 1
SI00, SI01, SI10, SI11,
P20 to P27:
Port 2
SI20, SI21, SI30, SI31:
P30, P31:
Port 3
SO00, SO01, SO10,
P40 to P47:
Port 4
SO11, SO20, SO21,
P50 to P57:
Port 5
SO30, SO31:
P60 to P67:
Port 6
TI00 to TI07,
P70 to P77:
Port 7
TI10 to TI13:
P80 to P87:
Port 8
TO00 to TO07,
P100 to P102:
Port 10
TO10 to TO13:
P110, P111:
Port 11
TOOL0:
Data input/output for tool
P120 to P124:
Port 12
TOOLRxD, TOOLTxD:
Data input/output for external device
P130, P137:
Port 13
TxD0 to TxD3:
Transmit data
P140 to P147:
Port 14
VDD:
Power supply
P150 to P156:
Port 15
PCLBUZ0, PCLBUZ1: Programmable clock
output/buzzer output
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Serial data input/output
Serial data input
Serial data output
Timer input
Timer output
VSS:
Ground
X1, X2:
Crystal oscillator (main system clock)
XT1, XT2:
Crystal oscillator (subsystem clock)
9
RL78/G13A
1. OUTLINE
1.5 Block Diagram
1.5.1 44-pin products
TIMER ARRAY
UNIT (8ch)
PORT 0
2
P00, P01
TI00/P00
TO00/P01
ch0
PORT 1
8
P10 to P17
PORT 2
8
P20 to P27
PORT 3
2
P30, P31
PORT 4
2
P40, P41
PORT 5
2
P50, P51
TI01/TO01/P16
ch1
TI02/TO02/P17
(TI02/TO02/P15)
ch2
TI03/TO03/P31
(TI03/TO03/P14)
ch3
(TI04/TO04/P13)
ch4
(TI05/TO05/P12)
ch5
(TI06/TO06/P11)
TI07/TO07/P41
(TI07/TO07/P10)
RxD2/P14
ch6
PORT 6
4
P60 to P63
ch7
PORT 7
4
P70 to P73
4
P121 to P124
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
PORT 12
PORT 13
TxD0/P12(TxD0/P17)
RxD1/P01
TxD1/P00
REAL-TIME
CLOCK
CODE FLASH MEMORY
RL78
CPU
CORE
DATA FLASH MEMORY
A/D CONVERTER
P146, P147
8
ANI0/P20 to
ANI7/P27
2
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
KEY RETURN
SCK11/P30
SI11/P50
SO11/P51
CSI11
SCL00/P10
SDA00/P11
IIC00
SCL11/P30
SDA11/P50
IIC11
KR0/P70 to
KR3/P73
4
RAM
POWER ON RESET/
VOLTAGE
DETECTOR
VDD
RESET CONTROL
SCLA0/P60(SCLA0/P14)
TOOL0/P40
SYSTEM
CONTROL
BUZZER OUTPUT
UART2
CSI20
ON-CHIP DEBUG
SDAA0/P61(SDAA0/P13)
SERIAL ARRAY
UNIT1 (2ch)
LINSEL
POR/LVD
CONTROL
VSS TOOLRxD/P11,
TOOLTxD/P12
SERIAL
INTERFACE IICA0
2
CLOCK OUTPUT
CONTROL
MULTIPLIER&
DIVIDER,
MULTIPLYACCUMULATOR
PCLBUZ0/P31,
PCLBUZ1/P15
CRC
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
ON-CHIP
OSCILLATOR
XT1/P123
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
RxD2/P14
INTP0/P137
CSI21
SCL20/P15
SDA20/P14
IIC20
SCL21/P70
SDA21/P71
IIC21
Remark
2
UART1
CSI00
SCK20/P15
SI20/P14
SO20/P13
SCK21/P70
SI21/P71
SO21/P72
PORT 14
UART0
SCK00/P10
SI00/P11
SO00/P12
RxD2/P14
TxD2/P13
P137
12- BIT INTERVAL
TIMER
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P11(RxD0/P16)
P120
DIRECT MEMORY
ACCESS CONTROL
BCD
ADJUSTMENT
INTERRUPT
CONTROL
2
INTP1/P50,
INTP2/P51
2
INTP3/P30,
INTP4/P31
INTP5/P16
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the
RL78/G13A User’s Manual.
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RL78/G13A
1. OUTLINE
1.5.2 48-pin products
TIMER ARRAY
UNIT (8ch)
PORT 0
2
P00, P01
TI00/P00
TO00/P01
ch0
PORT 1
8
P10 to P17
TI01/TO01/P16
ch1
PORT 2
8
P20 to P27
PORT 3
2
P30, P31
PORT 4
2
P40, P41
PORT 5
2
P50, P51
PORT 6
4
P60 to P63
PORT 7
6
P70 to P75
PORT 12
4
P121 to P124
TI02/TO02/P17
(TI02/TO02/P15)
ch2
TI03/TO03/P31
(TI03/TO03/P14)
ch3
(TI04/TO04/P13)
ch4
(TI05/TO05/P12)
ch5
(TI06/TO06/P11)
ch6
TI07/TO07/P41
(TI07/TO07/P10)
RxD2/P14
ch7
P120
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
PORT 14
REAL-TIME
CLOCK
SERIAL ARRAY
UNIT0 (4ch)
RxD0/P11(RxD0/P16)
TxD0/P12(TxD0/P17)
UART0
RxD1/P01
TxD1/P00
UART1
SCK00/P10
SI00/P11
SO00/P12
SCK01/P75
SI01/P74
SO01/P73
SCL01/P75
SDA01/P74
IIC01
SCL11/P30
SDA11/P50
IIC11
A/D CONVERTER
POWER ON RESET/
VOLTAGE
DETECTOR
VDD
SERIAL ARRAY
UNIT1 (2ch)
UART2
LINSEL
Remark
8
ANI0/P20 to
ANI7/P27
2
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
CSI01
IIC00
SCL21/P70
SDA21/P71
DATA FLASH MEMORY
RAM
SCL00/P10
SDA00/P11
SCL20/P15
SDA20/P14
P140,
P146, P147
KR0/P70 to
KR5/P75
6
CSI00
CSI11
SCK20/P15
SI20/P14
SO20/P13
SCK21/P70
SI21/P71
SO21/P72
3
CODE FLASH MEMORY
RL78
CPU
CORE
KEY RETURN
SCK11/P30
SI11/P50
SO11/P51
RxD2/P14
TxD2/P13
P130
P137
PORT 13
12- BIT INTERVAL
TIMER
CSI20
CSI21
VSS TOOLRxD/P11,
TOOLTxD/P12
POR/LVD
CONTROL
RESET CONTROL
ON-CHIP DEBUG
TOOL0/P40
SYSTEM
CONTROL
SERIAL
INTERFACE IICA0
SDAA0/P61(SDAA0/P13)
BUZZER OUTPUT
2
CLOCK OUTPUT
CONTROL
MULTIPLIER&
DIVIDER,
MULTIPLYACCUMULATOR
DIRECT MEMORY
ACCESS CONTROL
RESET
X1/P121
X2/EXCLK/P122
SCLA0/P60(SCLA0/P14)
PCLBUZ0/P140
(PCLBUZ0/P31),
PCLBUZ1/P15
HIGH-SPEED
ON-CHIP
OSCILLATOR
XT1/P123
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
RxD2/P14
INTP0/P137
CRC
2
INTERRUPT
CONTROL
2
INTP5/P16
INTP6/P140
IIC20
IIC21
INTP1/P50,
INTP2/P51
INTP3/P30,
INTP4/P31
BCD
ADJUSTMENT
2
INTP8/P74,
INTP9/P75
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR). Refer to Figure 4-8
Format of Peripheral I/O Redirection Register (PIOR) in the
RL78/G13A User’s Manual.
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RL78/G13A
1. OUTLINE
1.5.3 64-pin products
TIMER ARRAY
UNIT (8ch)
PORT 0
7
P00 to P06
TI00/P00
TO00/P01
ch0
PORT 1
8
P10 to P17
TI01/TO01/P16
ch1
PORT 2
8
P20 to P27
TI02/TO02/P17
(TI02/TO02/P15)
ch2
PORT 3
2
P30, P31
TI03/TO03/P31
(TI03/TO03/P14)
ch3
TI04/TO04/P42
(TI04/TO04/P13)
PORT 4
4
P40 to P43
ch4
TI05/TO05/P05
(TI05/TO05/P12)
ch5
PORT 5
6
P50 to P55
ch6
PORT 6
4
P60 to P63
ch7
PORT 7
8
P70 to P77
4
P121 to P124
TI06/TO06/P06
(TI06/TO06/P11)
TI07/TO07/P41
(TI07/TO07/P10)
RxD2/P14
(RxD2/P76)
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
PORT 12
PORT 14
UART0
RxD1/P03
TxD1/P02
UART1
A/D CONVERTER
DATA FLASH MEMORY
ANI0/P20 to
ANI7/P27
4
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
KEY RETURN
POWER ON RESET/
VOLTAGE
DETECTOR
KR0/P70 to
KR7/P77
8
SCK11/P30
SI11/P50
SO11/P51
CSI11
SCL00/P10
SDA00/P11
IIC00
SCL01/P75
SDA01/P74
IIC01
SCL10/P04
SDA10/P03
IIC10
SCL11/P30
SDA11/P50
IIC11
RESET CONTROL
ON-CHIP DEBUG
VDD,
VSS, TOOLRxD/P11,
EVDD0 EVSS0 TOOLTxD/P12
SCLA0/P60(SCLA0/P14)
SERIAL
INTERFACE IICA0
TOOL0/P40
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
ON-CHIP
OSCILLATOR
XT1/P123
XT2/EXCLKS/P124
SDAA0/P61(SDAA0/P13)
VOLTAGE
REGULATOR
2
SERIAL ARRAY
UNIT1 (2ch)
POR/LVD
CONTROL
RAM
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
REGC
PCLBUZ0/P140
(PCLBUZ0/P31),
PCLBUZ1/P141
(PCLBUZ1/P55)
RxD2/P14 (RxD2/P76)
INTP0/P137
2
UART2
LINSEL
MULTIPLIER&
DIVIDER,
MULTIPLYACCUMULATOR
CSI20
CRC
2
INTERRUPT
CONTROL
2
CSI21
IIC20
SCL21/P70
SDA21/P71
IIC21
BCD
ADJUSTMENT
INTP1/P50,
INTP2/P51
INTP3/P30,
INTP4/P31
INTP5/P16(INTP5/P12)
2
DIRECT MEMORY
ACCESS CONTROL
SCL20/P15
SDA20/P14
Remark
8
CODE FLASH MEMORY
RL78
CPU
CORE
CSI01
CSI10
SCK20/P15
SI20/P14
SO20/P13
SCK21/P70
SI21/P71
SO21/P72
P140, P141,
P146, P147
CSI00
SCK10/P04
SI10/P03
SO10/P02
TxD2/P13(TxD2/P77)
4
REAL-TIME
CLOCK
RxD0/P11(RxD0/P16)
TxD0/P12(TxD0/P17)
RxD2/P14(RxD2/P76)
P130
P137
PORT 13
12- BIT INTERVAL
TIMER
SERIAL ARRAY
UNIT0 (4ch)
SCK00/P10(SCK00/P55)
SI00/P11(SI00/P16)
SO00/P12(SO00/P17)
SCK01/P75
SI01/P74
SO01/P73
P120
2
INTP6/P140,
INTP7/P141
INTP8/P74,
INTP9/P75
INTP10/P76(INTP10/P52),
INTP11/P77(INTP11/P53)
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR). Refer to Figure 4-8
Format of Peripheral I/O Redirection Register (PIOR) in the
RL78/G13A User’s Manual.
R01DS0376EJ0110 Rev.1.10
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RL78/G13A
1. OUTLINE
1.5.4 100-pin products
TIMER ARRAY
UNIT0 (8ch)
TIMER ARRAY
UNIT1 (4ch)
TI00/P00
TO00/P01
ch0
ch0
TI10/TO10/P64
TI01/TO01/P16
ch1
ch1
TI02/TO02/P17
(TI02/TO02/P15)
ch2
TI03/TO03/P31
(TI03/TO03/P14)
ch3
TI04/TO04/P42
(TI04/TO04/P13)
ch4
TI05/TO05/P46
(TI05/TO05/P12)
ch5
TI06/TO06/P102
(TI06/TO06/P11)
TI07/TO07/P145
(TI07/TO07/P10)
RxD2/P14
(RxD2/P76)
PORT 0
7
P00 to P06
TI11/TO11/P65
PORT 1
8
P10 to P17
ch2
TI12/TO12/P66
PORT 2
8
P20 to P27
ch3
TI13/TO13/P67
PORT 3
2
P30, P31
PORT 4
8
P40 to P47
PORT 5
8
P50 to P57
PORT 6
8
P60 to P67
PORT 7
8
P70 to P77
PORT 8
8
P80 to P87
PORT 10
3
P100 to P102
PORT 11
2
P110, P111
ch6
ch7
SERIAL ARRAY
UNIT0 (4ch)
8
RxD0/P11(RxD0/P16)
TxD0/P12(TxD0/P17)
UART0
7
RxD1/P03(RxD1/P81)
TxD1/P02(TxD1/P82)
UART1
SCK00/P10(SCK00/P55)
SI00/P11(SI00/P16)
SO00/P12(SO00/P17)
SCK01/P43
SI01/P44
SO01/P45
5
A/D CONVERTER
CSI00
AVREFP/P20
AVREFM/P21
CSI01
PORT 12
SCK10/P04(SCK10/P80)
SI10/P03(SI10/P81)
SO10/P02(SO10/P82)
CSI10
SCK11/P30
SI11/P50
SO11/P51
CSI11
SCL00/P10
SDA00/P11
IIC00
SCL01/P43
SDA01/P44
IIC01
SCL10/P04(SCL10/P80)
SDA10/P03(SDA10/P81)
IIC10
SCL11/P30
ANI0/P20 to ANI7/P27
ANI8/P150 to ANI14/P156
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120,
ANI20/P100
DATA FLASH MEMORY
VSS,
VDD,
EVDD0, EVSS0,
EVDD1 EVSS1
UART2
SCK20/P15
SI20/P14
SO20/P13
SCK21/P70
SI21/P71
SO21/P72
SCLA0/P60(SCLA0/P14)
SDAA0/P61(SDAA0/P13)
SERIAL
INTERFACE IICA1
SDAA1/P63
SCLA1/P62
BUZZER OUTPUT
2
CSI21
CLOCK OUTPUT
CONTROL
CSI30
MULTIPLIER&
DIVIDER,
MULTIPLYACCUMULATOR
SCK31/P54
SI31/P53
SO31/P52
CSI31
DIRECT MEMORY
ACCESS CONTROL
SCL20/P15
SDA20/P14
IIC20
SCL21/P70
SDA21/P71
IIC21
SCL30/P142
SDA30/P143
IIC30
SCL31/P54
SDA31/P53
IIC31
SI30/P143
SO30/P144
PCLBUZ0/P140
(PCLBUZ0/P31),
PCLBUZ1/P141
(PCLBUZ1/P55)
CRC
P140 to P147
PORT 15
7
P150 to P156
KEY RETURN
8
KR0/P70 to
KR7/P77
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
ON-CHIP
OSCILLATOR
XT1/P123
XT2/EXCLKS/P124
VOLTAGE
REGULATOR
REGC
2
2
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
POR/LVD
CONTROL
RxD2/P14 (RxD2/P76)
INTP0/P137
BCD
ADJUSTMENT
RTC1HZ/P30
Remark
TOOLRxD/P11,
TOOLTxD/P12
SERIAL
INTERFACE IICA0
CSI20
SCK30/P142
8
POWER ON RESET/
VOLTAGE
DETECTOR
SERIAL ARRAY
UNIT1 (4ch)
UART3
PORT 14
RAM
IIC11
RxD3/P143
TxD3/P144
P130
P137
PORT 13
SDA11/P50
LINSEL
P121 to P124
CODE FLASH MEMORY
RL78
CPU
CORE
RxD2/P14(RxD2/P76)
TxD2/P13(TxD2/P77)
P120
4
12- BIT INTERVAL
TIMER
INTERRUPT
CONTROL
INTP1/P46(INTP1/P56),
INTP2/P47
INTP3/P30(INTP3/P57),
INTP4/P31(INTP4/P146)
INTP5/P16(INTP5/P12)
2
INTP6/P140(INTP6/P84),
INTP7/P141(INTP7/P85)
2
INTP8/P74(INTP8/P86),
INTP9/P75(INTP9/P87)
2
INTP10/P76(INTP10/P110),
INTP11/P77(INTP11/P111)
REAL-TIME
CLOCK
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR). Refer to Figure 4-8
Format of Peripheral I/O Redirection Register (PIOR) in the
RL78/G13A User’s Manual.
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Sep 18, 2020
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RL78/G13A
1. OUTLINE
1.6 Outline of Functions
[44-pin, 48-pin, 64-pin products]
Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set
to 00H.
(1/2)
Item
44-pin
R5F140Fx
48-pin
R5F140Gx
64-pin
R5F140Lx
Code flash memory (KB)
384, 512
384, 512
384, 512
Data flash memory (KB)
8
8
8
Note 1
RAM (KB)
24, 32
Address space
Main system
clock
24, 32
Note 1
24, 32Note 1
1 MB
High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
HS (High-speed main) mode: 1 to 20 MHz (VDD = 2.7 to 5.5 V),
HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V),
LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
High-speed on-chip
oscillator
Subsystem clock
HS (High-speed main) mode:
HS (High-speed main) mode:
LS (Low-speed main) mode:
LV (Low-voltage main) mode:
1 to 32 MHz (VDD = 2.7 to 5.5 V),
1 to 16 MHz (VDD = 2.4 to 5.5 V),
1 to 8 MHz (VDD = 1.8 to 5.5 V),
1 to 4 MHz (VDD = 1.6 to 5.5 V)
XT1 (crystal) oscillation, external subsystem clock input (EXCLKS)
32.768 kHz
Low-speed on-chip oscillator
15 kHz (typ.)
General-purpose registers
(8-bit register × 8) × 4 banks
Minimum instruction execution time
0.03125 µs (High-speed on-chip oscillator: fIH = 32 MHz operation)
0.05 µs (High-speed system clock: fMX = 20 MHz operation)
30.5 µs (Subsystem clock: fSUB = 32.768 kHz operation)
●
●
●
●
Instruction set
I/O port
Data transfer (8/16 bits)
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
Total
CMOS I/O
40
44
58
31
(N-ch O.D. I/O [VDD withstand
voltage]: 10)
34
(N-ch O.D. I/O [VDD withstand
voltage]: 11)
48
(N-ch O.D. I/O [VDD withstand
voltage]: 15)
5
5
5
CMOS input
Timer
CMOS output
–
1
1
N-ch O.D. I/O (withstand
voltage: 6 V)
4
4
4
16-bit timer
8 channels
Watchdog timer
1 channel
Real-time clock (RTC)
1 channel
12-bit interval timer (IT)
1 channel
Timer output
5 channels (PWM outputs: 4 Note 2),
8 channels (PWM outputs: 7 Note 2) Note 3
RTC output
Notes 1.
2.
3.
8 channels (PWM outputs: 7
)
Note 2
1 channel
● 1 Hz (subsystem clock: fSUB = 32.768 kHz)
The flash library uses RAM in self-programming and rewriting of the data flash memory.
The target products and start address of the RAM areas used by the flash library are shown below.
R5F140xL (x = F, G, L): Start address F7F00H
For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for
RL78 Family (R20UT2944).
The number of PWM outputs varies depending on the setting of channels in use (the number of masters and
slaves) (see 6.9.3 Operation as multiple PWM output function in the RL78/G13A User’s Manual).
When setting to PIOR = 1
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RL78/G13A
1. OUTLINE
(2/2)
Item
44-pin
48-pin
64-pin
R5F140Fx
R5F140Gx
R5F140Lx
2
2
2
Clock output/buzzer output
● 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
● 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter
Serial interface
10 channels
10 channels
12 channels
[44-pin products]
● CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel
● CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel
● CSI: 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel
[48-pin products]
● CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel
● CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel
● CSI: 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel
[64-pin products]
● CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel
● CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel
● CSI: 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel
I2C bus
1 channel
1 channel
1 channel
Multiplier and divider/multiply-accumulator ● 16 bits × 16 bits = 32 bits (Unsigned or signed)
● 32 bits ÷ 32 bits = 32 bits (Unsigned)
● 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)
DMA controller
Vectored
interrupt sources
2 channels
Internal
27
27
27
External
7
10
13
4
6
8
Key interrupt
Reset
●
●
●
●
●
●
●
Power-on-reset circuit
● Power-on-reset: 1.51 V (typ.)
● Power-down-reset: 1.50 V (typ.)
Voltage detector
● Rising edge :
● Falling edge :
On-chip debug function
Provided
Power supply voltage
VDD = 1.6 to 5.5 V (TA = -40 to +85°C)
Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
Internal reset by illegal instruction execution Note
Internal reset by RAM parity error
Internal reset by illegal-memory access
1.67 V to 4.06 V (14 stages)
1.63 V to 3.98 V (14 stages)
VDD = 2.4 to 5.5 V (TA = -40 to +105°C)
Operating ambient temperature
Note
TA = -40 to +85°C (A: Consumer applications)
TA = -40 to +105°C (G: Industrial applications)
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
R01DS0376EJ0110 Rev.1.10
Sep 18, 2020
15
RL78/G13A
1. OUTLINE
[100-pin products]
Caution
This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set
to 00H.
(1/2)
Item
100-pin
R5F140Px
Code flash memory (KB)
384, 512
Data flash memory (KB)
8
24, 32Note 1
RAM (KB)
Address space
1 MB
Main system High-speed system
clock
clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
HS (High-speed main) mode: 1 to 20 MHz (VDD = 2.7 to 5.5 V),
HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V),
LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
High-speed on-chip
oscillator
HS (High-speed main) mode:
HS (High-speed main) mode:
LS (Low-speed main) mode:
LV (Low-voltage main) mode:
1 to 32 MHz (VDD = 2.7 to 5.5 V),
1 to 16 MHz (VDD = 2.4 to 5.5 V),
1 to 8 MHz (VDD = 1.8 to 5.5 V),
1 to 4 MHz (VDD = 1.6 to 5.5 V)
Subsystem clock
XT1 (crystal) oscillation, external subsystem clock input (EXCLKS)
32.768 kHz
Low-speed on-chip oscillator
15 kHz (typ.)
General-purpose register
(8-bit register × 8) × 4 banks
Minimum instruction execution time
0.03125 µs (High-speed on-chip oscillator: fIH = 32 MHz operation)
0.05 µs (High-speed system clock: fMX = 20 MHz operation)
30.5 µs (Subsystem clock: fSUB = 32.768 kHz operation)
●
●
●
●
Instruction set
I/O port
Data transfer (8/16 bits)
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
Total
92
CMOS I/O
Timer
82 (N-ch O.D. I/O [EVDD withstand voltage]: 24)
CMOS input
5
CMOS output
1
N-ch O.D. I/O
(withstand voltage: 6 V)
4
16-bit timer
12 channels
Watchdog timer
1 channel
Real-time clock (RTC)
1 channel
12-bit interval timer (IT)
1 channel
12 channels (PWM outputs: 10 Note 2)
Timer output
RTC output
Notes 1.
1 channel
● 1 Hz (subsystem clock: fSUB = 32.768 kHz)
The flash library uses RAM in self-programming and rewriting of the data flash memory.
The target products and start address of the RAM areas used by the flash library are shown below.
R5F140xL (x = P): Start address F7F00H
For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for
RL78 Family (R20UT2944).
2.
The number of PWM outputs varies depending on the setting of channels in use (the number of masters and
slaves) (see 6.9.3 Operation as multiple PWM output function in the RL78/G13A User’s Manual).
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RL78/G13A
1. OUTLINE
(2/2)
Item
100-pin
R5F140Px
Clock output/buzzer output
2
● 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
● 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter
Serial interface
20 channels
[100-pin products]
● CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel
● CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel
● CSI: 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel
● CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel
I2C bus
2 channels
Multiplier and divider/multiply-
● 16 bits × 16 bits = 32 bits (Unsigned or signed)
accumulator
● 32 bits ÷ 32 bits = 32 bits (Unsigned)
● 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)
DMA controller
4 channels
Vectored
Internal
37
interrupt sources
External
13
Key interrupt
8
● Reset by RESET pin
Reset
● Internal reset by watchdog timer
● Internal reset by power-on-reset
● Internal reset by voltage detector
● Internal reset by illegal instruction execution Note
● Internal reset by RAM parity error
● Internal reset by illegal-memory access
Power-on-reset circuit
● Power-on-reset:
1.51 V (typ.)
● Power-down-reset: 1.50 V (typ.)
Voltage detector
● Rising edge :
1.67 V to 4.06 V (14 stages)
● Falling edge :
1.63 V to 3.98 V (14 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 1.6 to 5.5 V (TA = -40 to +85°C)
VDD = 2.4 to 5.5 V (TA = -40 to +105°C)
Operating ambient temperature
TA = -40 to +85°C (A: Consumer applications)
TA = -40 to +105°C (G: Industrial applications)
Note
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
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RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
This chapter describes the following electrical specifications.
Target products A: Consumer applications TA = −40 to +85°C
R5F140xxAxx
G: Industrial applications when TA = −40 to +105°C products is used in the range of TA = −40 to +85°C
R5F140xxGxx
Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development
and evaluation. Do not use the on-chip debug function in products designated for mass
production, because the guaranteed number of rewritable times of the flash memory may be
exceeded when this function is used, and product reliability therefore cannot be guaranteed.
Renesas Electronics is not liable for problems occurring when the on-chip debug function is
used.
2. With products not provided with an EVDD0, EVDD1, EVSS0, or EVSS1 pin, replace EVDD0 and EVDD1 with
VDD, or replace EVSS0 and EVSS1 with VSS.
3. The pins mounted depend on the product. Refer to 2.1 Port Function to 2.2.1 Functions for each
product in the RL78/G13A User’s Manual.
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RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
2.1 Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25°C) (1/2)
Parameter
Supply voltage
Symbols
Conditions
VDD
REGC pin input voltage
Ratings
Unit
–0.5 to +6.5
V
EVDD0, EVDD1
EVDD0 = EVDD1
–0.5 to +6.5
V
EVSS0, EVSS1
EVSS0 = EVSS1
–0.5 to +0.3
V
VIREGC
REGC
–0.3 to +2.1
V
and –0.3 to VDD +0.3Note 1
Input voltage
VI1
P00 to P06, P10 to P17, P30, P31, P40 to P47,
P50 to P57, P64 to P67, P70 to P77, P80 to P87,
–0.3 to EVDD0 +0.3
and –0.3 to VDD +0.3
V
Note 2
P100 to P102, P110, P111, P120, P140 to P147
VI2
P60 to P63 (N-ch open-drain)
VI3
P20 to P27, P121 to P124, P137, P150 to P156,
–0.3 to +6.5
V
–0.3 to VDD +0.3
V
Note 2
EXCLK, EXCLKS, RESET
Output voltage
VO1
P00 to P06, P10 to P17, P30, P31, P40 to P47,
P50 to P57, P60 to P67, P70 to P77, P80 to P87,
–0.3 to EVDD0 +0.3
V
and –0.3 to VDD +0.3 Note 2
P100 to P102, P110, P111, P120, P130,
P140 to P147
Analog input voltage
VO2
P20 to P27, P150 to P156
VAI1
ANI16 to ANI20
–0.3 to VDD +0.3 Note 2
V
–0.3 to EVDD0 +0.3
V
and –0.3 to AVREF(+) +0.3Notes 2, 3
VAI2
ANI0 to ANI14
–0.3 to VDD +0.3
V
and –0.3 to AVREF(+) +0.3Notes 2, 3
Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). This value regulates the absolute
maximum rating of the REGC pin. Do not use this pin with voltage applied to it.
2.
Must be 6.5 V or lower.
3.
Do not exceed AVREF (+) + 0.3 V in case of A/D conversion target pin.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure that
the absolute maximum ratings are not exceeded.
Remarks 1.
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
2.
AVREF (+) : Positive reference voltage of the A/D converter.
3.
VSS : Reference voltage
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RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
Absolute Maximum Ratings (TA = 25°C) (2/2)
Parameter
Output current, high
Symbols
IOH1
Conditions
Per pin
P00 to P06, P10 to P17,
Ratings
Unit
–40
mA
–70
mA
–100
mA
–0.5
mA
–2
mA
40
mA
70
mA
100
mA
1
mA
5
mA
–40 to +85
°C
–65 to +150
°C
P30, P31, P40 to P47,
P50 to P57, P64 to P67,
P70 to P77, P80 to P87,
P100 to P102, P110, P111,
P120, P130, P140 to P147
Total of all pins
P00 to P04, P40 to P47, P102,
–170 mA
P120, P130, P140 to P145
P05, P06, P10 to P17, P30, P31,
P50 to P57, P64 to P67,
P70 to P77, P80 to P87,
P100, P101, P110, P111,
P146, P147
IOH2
Per pin
P20 to P27, P150 to P156
Total of all pins
Output current, low
IOL1
Per pin
P00 to P06, P10 to P17,
P30, P31, P40 to P47,
P50 to P57, P60 to P67,
P70 to P77, P80 to P87,
P100 to P102, P110, P111,
P120, P130, P140 to P147
Total of all pins
P00 to P04, P40 to P47, P102,
170 mA
P120, P130, P140 to P145
P05, P06, P10 to P17, P30, P31,
P50 to P57, P60 to P67,
P70 to P77, P80 to P87,
P100, P101, P110, P111,
P146, P147
IOL2
Per pin
P20 to P27, P150 to P156
Total of all pins
Operating ambient
TA
temperature
Storage temperature
In normal operation mode
In flash memory programming mode
Tstg
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure that
the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
2.2 Oscillator Characteristics
2.2.1 X1, XT1 oscillator characteristics
(TA = –40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Resonator
Conditions
MIN.
TYP.
MAX.
Unit
MHz
X1 clock oscillation
Ceramic resonator/
2.7 V ≤ VDD ≤ 5.5 V
1.0
20.0
frequency (fX)Note
crystal resonator
2.4 V ≤ VDD < 2.7 V
1.0
16.0
MHz
1.8 V ≤ VDD < 2.4 V
1.0
8.0
MHz
1.6 V ≤ VDD < 1.8 V
1.0
4.0
MHz
35
kHz
XT1 clock oscillation
Crystal resonator
32
32.768
frequency (fX)Note
Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time.
Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator
characteristics.
Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1
clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC)
by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation
stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time
with the resonator to be used.
Remark When using the X1 oscillator and XT1 oscillator, refer to 5.4 System Clock Oscillator in the RL78/G13A User’s
Manual.
2.2.2 On-chip oscillator characteristics
(TA = –40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Oscillators
High-speed on-chip oscillator
Parameters
fIH
Conditions
MIN.
TYP.
MAX.
Unit
1
32
MHz
–1.0
+1.0
%
clock frequency Notes 1, 2
High-speed on-chip oscillator
clock frequency accuracy
Low-speed on-chip oscillator
fIL
15
kHz
clock frequency
Low-speed on-chip oscillator
–15
+15
%
clock frequency accuracy
Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H/010C2H) and bits 0
to 2 of HOCODIV register.
2. This indicates the oscillator characteristics only. Refer to AC Characteristics for instruction execution time.
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2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
2.3 DC Characteristics
2.3.1 Pin characteristics
(TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/5)
Items
Symbol
Output current,
highNote 1
IOH1
Conditions
Notes 1.
TYP.
MAX.
Unit
–10.0
mA
Per pin for P00 to P06, P10 to P17,
P30, P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77, P80 to P87,
P100 to P102, P110, P111, P120, P130,
P140 to P147
1.6 V ≤ EVDD0 ≤ 5.5 V
Total of P00 to P04, P40 to P47, P102,
P120, P130, P140 to P145
(When duty ≤ 70% Note 3)
4.0 V ≤ EVDD0 ≤ 5.5 V
–55.0
mA
2.7 V ≤ EVDD0 < 4.0 V
–10.0
mA
1.8 V ≤ EVDD0 < 2.7 V
–5.0
mA
1.6 V ≤ EVDD0 < 1.8 V
–2.5
mA
4.0 V ≤ EVDD0 ≤ 5.5 V
–80.0
mA
2.7 V ≤ EVDD0 < 4.0 V
–19.0
mA
1.8 V ≤ EVDD0 < 2.7 V
–10.0
mA
1.6 V ≤ EVDD0 < 1.8 V
–5.0
mA
Total of all pins
(When duty ≤ 70% Note 3)
1.6 V ≤ EVDD0 ≤ 5.5 V
–135.0
mA
Per pin for P20 to P27, P150 to P156
1.6 V ≤ VDD ≤ 5.5 V
–0.1Note 2
mA
Total of all pins
(When duty ≤ 70% Note 3)
1.6 V ≤ VDD ≤ 5.5 V
–1.5
mA
Total of P05, P06, P10 to P17, P30, P31,
P50 to P57, P64 to P67, P70 to P77,
P80 to P87, P100, P101, P110, P111,
P146, P147
(When duty ≤ 70% Note 3)
IOH2
MIN.
Note 2
Note 4
Value of current at which the device operation is guaranteed even if the current flows from the EVDD0,
EVDD1, VDD pins to an output pin.
2.
However, do not exceed the total current value.
3.
Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the
following expression (when changing the duty factor from 70% to n%).
● Total output current of pins = (IOH × 0.7)/(n × 0.01)
Where n = 80% and IOH = –10.0 mA
Total output current of pins = (–10.0 × 0.7)/(80 × 0.01) –8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
4.
The applied current for the products for industrial application (R5F140xxGxx) is –100 mA.
Caution P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, and P142 to P144
do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/5)
Items
Symbol
Output current,
lowNote 1
IOL1
MAX.
Unit
Per pin for P00 to P06, P10 to P17,
P30, P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77, P80 to P87,
P100 to P102, P110, P111, P120,
P130, P140 to P147
Conditions
20.0 Note 2
mA
Per pin for P60 to P63
15.0 Note 2
mA
Total of P00 to P04, P40 to P47,
P102, P120, P130, P140 to P145
(When duty ≤ 70% Note 3)
Total of P05, P06, P10 to P17, P30,
P31, P50 to P57, P60 to P67,
P70 to P77, P80 to P87, P100, P101,
P110, P111, P146, P147
(When duty ≤ 70% Note 3)
MIN.
4.0 V ≤ EVDD0 ≤ 5.5 V
70.0
mA
2.7 V ≤ EVDD0 < 4.0 V
15.0
mA
1.8 V ≤ EVDD0 < 2.7 V
9.0
mA
1.6 V ≤ EVDD0 < 1.8 V
4.5
mA
4.0 V ≤ EVDD0 ≤ 5.5 V
80.0
mA
2.7 V ≤ EVDD0 < 4.0 V
35.0
mA
1.8 V ≤ EVDD0 < 2.7 V
20.0
mA
1.6 V ≤ EVDD0 < 1.8 V
10.0
mA
150.0
mA
0.4 Note 2
mA
5.0
mA
Total of all pins
(When duty ≤ 70% Note 3)
IOL2
Per pin for P20 to P27, P150 to P156
Total of all pins
(When duty ≤ 70%Note 3)
Notes 1.
TYP.
1.6 V ≤ VDD ≤ 5.5 V
Value of current at which the device operation is guaranteed even if the current flows from an output pin to
the EVSS0, EVSS1 and VSS pin.
2.
3.
However, do not exceed the total current value.
Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the
following expression (when changing the duty factor from 70% to n%).
● Total output current of pins = (IOL × 0.7)/(n × 0.01)
Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (3/5)
Items
Input voltage,
Symbol
VIH1
high
Conditions
MAX.
Unit
0.8EVDD0
EVDD0
V
2.2
EVDD0
V
2.0
EVDD0
V
1.5
EVDD0
V
0.7VDD
VDD
V
0.7EVDD0
6.0
V
0.8VDD
VDD
V
Normal input buffer
0
0.2EVDD0
V
P01, P03, P04, P10, P11,
TTL input buffer
0
0.8
V
P13 to P17, P43, P44, P53 to P55,
4.0 V ≤ EVDD0 ≤ 5.5 V
P80, P81, P142, P143
TTL input buffer
0
0.5
V
0
0.32
V
P00 to P06, P10 to P17, P30, P31,
MIN.
Normal input buffer
TYP.
P40 to P47, P50 to P57, P64 to P67,
P70 to P77, P80 to P87,
P100 to P102, P110, P111, P120,
P140 to P147
VIH2
P01, P03, P04, P10, P11,
TTL input buffer
P13 to P17, P43, P44, P53 to P55,
4.0 V ≤ EVDD0 ≤ 5.5 V
P80, P81, P142, P143
TTL input buffer
3.3 V ≤ EVDD0 < 4.0 V
TTL input buffer
1.6 V ≤ EVDD0 < 3.3 V
VIH3
P20 to P27, P150 to P156
VIH4
P60 to P63
VIH5
P121 to P124, P137, EXCLK, EXCLKS, RESET
Input voltage, low VIL1
P00 to P06, P10 to P17, P30, P31,
P40 to P47, P50 to P57, P64 to P67,
P70 to P77, P80 to P87,
P100 to P102, P110, P111, P120,
P140 to P147
VIL2
3.3 V ≤ EVDD0 < 4.0 V
TTL input buffer
1.6 V ≤ EVDD0 < 3.3 V
VIL3
P20 to P27, P150 to P156
0
0.3VDD
V
VIL4
P60 to P63
0
0.3EVDD0
V
VIL5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0
0.2VDD
V
Caution The maximum value of VIH of pins P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71,
P74, P80 to P82, and P142 to P144 is EVDD0, even in the N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (4/5)
Items
Symbol
Output voltage,
VOH1
high
Conditions
MIN.
P00 to P06, P10 to P17, P30, P31,
4.0 V ≤ EVDD0 ≤ 5.5 V,
P40 to P47, P50 to P57, P64 to P67,
IOH1 = –10.0 mA
P70 to P77, P80 to P87,
4.0 V ≤ EVDD0 ≤ 5.5 V,
P100 to P102, P110, P111, P120,
P130, P140 to P147
IOH1 = –3.0 mA
2.7 V ≤ EVDD0 ≤ 5.5 V,
IOH1 = –2.0 mA
1.8 V ≤ EVDD0 ≤ 5.5 V,
IOH1 = –1.5 mA
1.6 V ≤ EVDD0 < 5.5 V,
IOH1 = –1.0 mA
VOH2
P20 to P27, P150 to P156
1.6 V ≤ VDD ≤ 5.5 V,
TYP.
MAX.
EVDD0 –
Unit
V
1.5
EVDD0 –
V
0.7
EVDD0 –
V
0.6
EVDD0 –
V
0.5
EVDD0 –
V
0.5
VDD – 0.5
V
IOH2 = –100 µA
Output voltage,
VOL1
low
P00 to P06, P10 to P17, P30, P31,
4.0 V ≤ EVDD0 ≤ 5.5 V,
P40 to P47, P50 to P57, P64 to P67,
IOL1 = 20 mA
P70 to P77, P80 to P87,
4.0 V ≤ EVDD0 ≤ 5.5 V,
P100 to P102, P110, P111, P120,
P130, P140 to P147
1.3
V
0.7
V
0.6
V
0.4
V
0.4
V
0.4
V
0.4
V
2.0
V
0.4
V
0.4
V
0.4
V
0.4
V
IOL1 = 8.5 mA
2.7 V ≤ EVDD0 ≤ 5.5 V,
IOL1 = 3.0 mA
2.7 V ≤ EVDD0 ≤ 5.5 V,
IOL1 = 1.5 mA
1.8 V ≤ EVDD0 ≤ 5.5 V,
IOL1 = 0.6 mA
1.6 V ≤ EVDD0 < 5.5 V,
IOL1 = 0.3 mA
VOL2
P20 to P27, P150 to P156
1.6 V ≤ VDD ≤ 5.5 V,
IOL2 = 400 µA
VOL3
P60 to P63
4.0 V ≤ EVDD0 ≤ 5.5 V,
IOL3 = 15.0 mA
4.0 V ≤ EVDD0 ≤ 5.5 V,
IOL3 = 5.0 mA
2.7 V ≤ EVDD0 ≤ 5.5 V,
IOL3 = 3.0 mA
1.8 V ≤ EVDD0 ≤ 5.5 V,
IOL3 = 2.0 mA
1.6 V ≤ EVDD0 < 5.5 V,
IOL3 = 1.0 mA
Caution P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, and P142 to P144
do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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Sep 18, 2020
25
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (5/5)
Items
Input leakage
Symbol
ILIH1
current, high
Conditions
P00 to P06, P10 to P17,
MIN.
TYP.
MAX.
Unit
VI = EVDD0
1
µA
VI = VDD
1
µA
1
µA
10
µA
VI = EVSS0
–1
µA
VI = VSS
–1
µA
–1
µA
–10
µA
100
kΩ
P30, P31, P40 to P47,
P50 to P57, P60 to P67,
P70 to P77, P80 to P87,
P100 to P102, P110, P111,
P120, P140 to P147
ILIH2
P20 to P27, P137,
P150 to P156, RESET
ILIH3
P121 to P124
VI = VDD
In input port or
(X1, X2, XT1, XT2, EXCLK,
external clock
EXCLKS)
input
In resonator
connection
Input leakage
ILIL1
current, low
P00 to P06, P10 to P17,
P30, P31, P40 to P47,
P50 to P57, P60 to P67,
P70 to P77, P80 to P87,
P100 to P102, P110, P111,
P120, P140 to P147
ILIL2
P20 to P27, P137,
P150 to P156, RESET
ILIL3
P121 to P124
VI = VSS
In input port or
(X1, X2, XT1, XT2, EXCLK,
external clock
EXCLKS)
input
In resonator
connection
On-chip pll-up
RU
resistance
P00 to P06, P10 to P17,
VI = EVSS0, In input port
10
20
P30, P31, P40 to P47,
P50 to P57, P64 to P67,
P70 to P77, P80 to P87,
P100 to P102, P110, P111,
P120, P140 to P147
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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26
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
2.3.2 Supply current characteristics
(TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2)
Parameter
Symbol
Supply
IDD1
current Note 1
Conditions
Operating
mode
HS (highspeed main)
mode Note 5
MIN.
TYP.
MAX.
Unit
Basic
operation
VDD = 5.0 V
1.5
mA
VDD = 3.0 V
1.5
mA
Normal
operation
VDD = 5.0 V
3.4
6.8
mA
VDD = 3.0 V
3.4
6.8
mA
Normal
operation
VDD = 5.0 V
2.7
5.3
mA
VDD = 3.0 V
2.7
5.3
mA
Normal
operation
VDD = 5.0 V
2
3.8
mA
VDD = 3.0 V
2
3.8
mA
Normal
operation
VDD = 3.0 V
1.1
1.9
mA
VDD = 2.0 V
1.1
1.9
mA
LV (lowfIH = 4 MHz Note 3
voltage main)
mode Note 5
Normal
operation
VDD = 3.0 V
0.7
1.2
mA
VDD = 2.0 V
0.7
1.2
mA
HS (highspeed main)
mode Note 5
Normal
operation
Square wave input
2.2
4.4
mA
Resonator connection
2.3
4.5
mA
Normal
operation
Square wave input
2.2
4.4
mA
Resonator connection
2.3
4.5
mA
Normal
operation
Square wave input
1.2
2.4
mA
Resonator connection
1.4
2.6
mA
Normal
operation
Square wave input
1.2
2.4
mA
Resonator connection
1.4
2.6
mA
Normal
operation
Square wave input
0.9
1.7
mA
1
1.8
mA
Normal
operation
Square wave input
0.9
1.7
mA
Resonator connection
1
1.8
mA
Normal
operation
Square wave input
4
5.5
µA
Resonator connection
4
5.7
µA
Normal
operation
Square wave input
4.2
6.7
µA
Resonator connection
4.3
6.9
µA
Normal
operation
Square wave input
4.5
9.3
µA
Resonator connection
4.7
9.5
µA
Normal
operation
Square wave input
5.3
15.8
µA
Resonator connection
5.6
16
µA
Normal
operation
Square wave input
6.6
25.8
µA
Resonator connection
7.1
26
µA
fIH = 32 MHz
fIH = 24 MHz
fIH = 16 MHz
LS (lowspeed main)
mode Note 5
fIH = 8 MHz
Note 3
Note 3
Note 3
Note 3
fMX = 20 MHzNote 2,
VDD = 5.0 V
fMX = 20 MHzNote 2,
VDD = 3.0 V
fMX = 10 MHzNote 2,
VDD = 5.0 V
fMX = 10 MHz
,
Note 2
VDD = 3.0 V
LS (lowspeed main)
mode Note 5
fMX = 8 MHz
Note 2
,
VDD = 3.0 V
fMX = 8 MHzNote 2,
VDD = 2.0 V
Subsystem
clock
operation
fSUB = 32.768 kHz
Note 4
TA = –40°C
f
= 32.768 kHz
SUB
Note 4
TA = +25°C
fSUB = 32.768 kHz
Note 4
TA = +50°C
fSUB = 32.768 kHz
Note 4
TA = +70°C
fSUB = 32.768 kHz
Note 4
TA = +85°C
Resonator connection
(Notes and Remarks are listed on the next page.)
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Sep 18, 2020
27
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of
the input pin is fixed to VDD, EVDD0, EVDD1 or VSS, EVSS0, EVSS1. The values below the MAX. column include the
peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O
port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite.
2. When high-speed on-chip oscillator and subsystem clock are stopped.
3. When high-speed system clock and subsystem clock are stopped.
4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low
power consumption oscillation). However, not including the current flowing into the RTC, 12-bit interval timer,
and watchdog timer.
5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
LS (low-speed main) mode:
1.8 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
R01DS0376EJ0110 Rev.1.10
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28
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
Parameter
Symbol
Conditions
Supply
IDD2
HALT
current
Note 2
mode
Note 1
HS (highspeed main)
mode Note 7
LS (lowspeed main)
mode Note 7
MIN.
fIH = 32 MHz
Note 4
fIH = 24 MHz
Note 4
fIH = 16 MHz
Note 4
fIH = 8 MHz
Note 4
LV (lowfIH = 4 MHz Note 4
voltage main)
mode Note 7
HS (highspeed main)
mode Note 7
fMX = 20 MHz
,
Note 3
VDD = 5.0 V
fMX = 20 MHz
,
Note 3
VDD = 3.0 V
fMX = 10 MHz
MAX.
Unit
VDD = 5.0 V
0.41
1.71
mA
VDD = 3.0 V
0.41
1.71
mA
VDD = 5.0 V
0.34
1.35
mA
VDD = 3.0 V
0.34
1.35
mA
VDD = 5.0 V
0.33
1.04
mA
VDD = 3.0 V
0.33
1.04
mA
VDD = 3.0 V
290
650
µA
VDD = 2.0 V
290
650
µA
VDD = 3.0 V
270
540
µA
VDD = 2.0 V
270
540
µA
Square wave input
0.19
1.05
mA
Resonator connection
0.37
1.26
mA
Square wave input
0.19
1.05
mA
Resonator connection
0.37
1.26
mA
Square wave input
0.12
0.62
mA
VDD = 5.0 V
Resonator connection
0.22
0.73
mA
fMX = 10 MHzNote 3,
Square wave input
0.12
0.62
mA
VDD = 3.0 V
Resonator connection
0.22
0.73
mA
Square wave input
100
410
µA
Resonator connection
200
520
µA
Square wave input
100
410
µA
LS (low-speed fMX = 8 MHz
main) mode
VDD = 3.0 V
,
TYP.
Note 3
Note 3
,
Note 7
fMX = 8 MHz
Note 3
,
VDD = 2.0 V
Resonator connection
200
520
µA
Note 5
Square wave input
0.39
1
µA
Subsystem
fSUB = 32.768 kHz
clock
TA = –40°C
Resonator connection
0.48
1.3
µA
fSUB = 32.768 kHzNote 5
Square wave input
0.55
2.2
µA
TA = +25°C
Resonator connection
0.64
2.5
µA
Square wave input
0.98
4.8
µA
Resonator connection
1.07
5.1
µA
Square wave input
1.73
11.3
µA
Resonator connection
1.82
11.6
µA
Square wave input
2.73
21.3
µA
Resonator connection
operation
fSUB = 32.768 kHz
Note 5
TA = +50°C
fSUB = 32.768 kHz
Note 5
TA = +70°C
fSUB = 32.768 kHz
TA = +85°C
IDD3Note 6
Note 5
2.82
21.6
µA
STOP
TA = –40°C
0.26
0.7
µA
modeNote 8
TA = +25°C
0.42
1.9
µA
TA = +50°C
0.85
4.5
µA
TA = +70°C
1.60
11
µA
TA = +85°C
2.60
21
µA
(Notes and Remarks are listed on the next page.)
R01DS0376EJ0110 Rev.1.10
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29
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of
the input pin is fixed to VDD, EVDD0, EVDD1 or VSS, EVSS0, EVSS1. The values below the MAX. column include the
peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O
port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator and subsystem clock are stopped.
4. When high-speed system clock and subsystem clock are stopped.
5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting
ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not
including the current flowing into the 12-bit interval timer and watchdog timer.
6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer.
7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
LS (low-speed main) mode:
1.8 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz
8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode.
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C
R01DS0376EJ0110 Rev.1.10
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30
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
Peripheral Functions (Common to all products)
(TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Low-speed on-
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
I
0.2
µA
RTC operating
IRTC
0.02
µA
current
Notes 1, 2, 3
12-bit interval
IIT Notes 1, 2, 4
0.02
µA
0.22
µA
Note 1
FIL
chip oscillator
operating current
timer operating
current
Watchdog timer
IWDT
operating current
Notes 1, 2, 5
A/D converter
operating current
IADC Notes 1, 6
fIL = 15 kHz
When
conversion at
maximum speed
Normal mode, AVREFP = VDD = 5.0 V
1.3
1.7
mA
Low voltage mode, AVREFP = VDD = 3.0 V
0.5
0.7
mA
A/D converter
reference
voltage current
IADREF Note 1
100
µA
Temperature
sensor operating
current
ITMPS Note 1
100
µA
LVD operating
ILVI Notes 1, 7
0.02
µA
IFSP Notes 1, 9
2.5
12.2
mA
IBGO Notes 1, 8
2.5
12.2
mA
The mode is performed Note 10
0.5
0.6
mA
The A/D conversion operations are
0.9
1.1
mA
0.5.
0.62
mA
current
Selfprogramming
operating current
BGO operating
current
SNOOZE
ISNOZ Note 1
ADC operation
operating current
performed, Low voltage mode, AVREFP =
VDD = 3.0 V
CSI/UART operation
Notes 1. Current flowing to VDD.
2. When high speed on-chip oscillator and high-speed system clock are stopped.
3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed on-chip
oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of
either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode. When the
low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the
operational current of the real-time clock.
4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip
oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of
either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT mode. When the
low-speed on-chip oscillator is selected, IFIL should be added.
5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator).
The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog
timer is in operation.
6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or
IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.
R01DS0376EJ0110 Rev.1.10
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RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
Notes 7. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2
or IDD3 and ILVD when the LVD circuit is in operation.
8. Current flowing only during data flash rewrite.
9. Current flowing only during self programming.
10. For shift time to the SNOOZE mode, see 18.3.3 SNOOZE mode in the RL78/G13A User’s Manual.
Remarks 1. fIL:
Low-speed on-chip oscillator clock frequency
2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
3. fCLK: CPU/peripheral hardware clock frequency
4. Temperature condition of the TYP. value is TA = 25°C
R01DS0376EJ0110 Rev.1.10
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32
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
2.4 AC Characteristics
(TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items
Instruction cycle (minimum
instruction execution time)
Symbol
TCY
Conditions
MIN.
Main system HS (high-speed 2.7 V ≤ VDD ≤ 5.5 V
clock (fMAIN) main) mode
2.4 V ≤ VDD < 2.7 V
operation
LS (low-speed 1.8 V ≤ VDD ≤ 5.5 V
TYP.
MAX.
Unit
0.03125
1
µs
0.0625
1
µs
0.125
1
µs
0.25
1
µs
31.3
µs
0.03125
1
µs
0.0625
1
µs
0.125
1
µs
0.25
1
µs
MHz
main) mode
LV (low-voltage 1.6 V ≤ VDD ≤ 5.5 V
main) mode
Subsystem clock (fSUB)
1.8 V ≤ VDD ≤ 5.5 V
28.5
30.5
operation
In the self
HS (high-speed 2.7 V ≤ VDD ≤ 5.5 V
programming main) mode
2.4 V ≤ VDD < 2.7 V
mode
LS (low-speed 1.8 V ≤ VDD ≤ 5.5 V
main) mode
LV (low-voltage 1.8 V ≤ VDD ≤ 5.5 V
main) mode
External system clock frequency
fEX
2.7 V ≤ VDD ≤ 5.5 V
1.0
20.0
2.4 V ≤ VDD < 2.7 V
1.0
16.0
MHz
1.8 V ≤ VDD < 2.4 V
1.0
8.0
MHz
1.6 V ≤ VDD < 1.8 V
1.0
4.0
MHz
32
35
kHz
fEXS
External system clock input highlevel width, low-level width
tEXH, tEXL
2.7 V ≤ VDD ≤ 5.5 V
24
ns
2.4 V ≤ VDD < 2.7 V
30
ns
1.8 V ≤ VDD < 2.4 V
60
ns
1.6 V ≤ VDD < 1.8 V
120
ns
tEXHS, tEXLS
TI00 to TI07, TI10 to TI13 input
high-level width, low-level width
tTIH,
tTIL
TO00 to TO07, TO10 to TO13
output frequency
fTO
PCLBUZ0, PCLBUZ1 output
frequency
Interrupt input high-level width,
low-level width
fPCL
tINTH,
tINTL
Key interrupt input low-level width tKR
RESET low-level width
13.7
µs
1/fMCK+10
nsNote
4.0 V ≤ EVDD0 ≤ 5.5 V
16
MHz
2.7 V ≤ EVDD0 < 4.0 V
8
MHz
1.8 V ≤ EVDD0 < 2.7 V
4
MHz
1.6 V ≤ EVDD0 < 1.8 V
2
MHz
LS (low-speed
main) mode
1.8 V ≤ EVDD0 ≤ 5.5 V
4
MHz
1.6 V ≤ EVDD0 < 1.8 V
2
MHz
LV (low-voltage
main) mode
1.6 V ≤ EVDD0 ≤ 5.5 V
2
MHz
HS (high-speed
main) mode
4.0 V ≤ EVDD0 ≤ 5.5 V
16
MHz
2.7 V ≤ EVDD0 < 4.0 V
8
MHz
1.8 V ≤ EVDD0 < 2.7 V
4
MHz
1.6 V ≤ EVDD0 < 1.8 V
2
MHz
LS (low-speed
main) mode
1.8 V ≤ EVDD0 ≤ 5.5 V
4
MHz
1.6 V ≤ EVDD0 < 1.8 V
2
MHz
LV (low-voltage
main) mode
1.8 V ≤ EVDD0 ≤ 5.5 V
4
MHz
1.6 V ≤ EVDD0 < 1.8 V
2
MHz
INTP0
1.6 V ≤ VDD ≤ 5.5 V
1
µs
INTP1 to INTP11
1.6 V ≤ EVDD0 ≤ 5.5 V
1
µs
1.8 V ≤ EVDD0 ≤ 5.5 V
250
ns
1.6 V ≤ EVDD0 < 1.8 V
1
µs
10
µs
HS (high-speed
main) mode
KR0 to KR7
tRSL
(Note and Remark are listed on the next page.)
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RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
Note The following conditions are required for low voltage interface when EVDD0 < VDD
1.8 V ≤ EVDD0 < 2.7 V : MIN. 125 ns
1.6 V ≤ EVDD0 < 1.8 V : MIN. 250 ns
Remark fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKSmn0, CKSmn1 bits of timer mode register mn (TMRmn).
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7))
Minimum Instruction Execution Time during Main System Clock Operation
TCY vs VDD (HS (high-speed main) mode)
10
Cycle time TCY [µs]
1.0
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
0.1
0.0625
0.05
0.03125
0.01
0
1.0
2.0
3.0
2.4 2.7
4.0
5.0 5.5 6.0
Supply voltage VDD [V]
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RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
TCY vs VDD (LS (low-speed main) mode)
10
Cycle time TCY [µs]
1.0
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
0.125
0.1
0.01
0
1.0
2.0
1.8
3.0
5.0 5.5 6.0
4.0
Supply voltage VDD [V]
TCY vs VDD (LV (low-voltage main) mode)
10
Cycle time TCY [µs]
1.0
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
0.25
0.1
0.01
0
1.0
2.0
1.6 1.8
3.0
4.0
5.0 5.5 6.0
Supply voltage VDD [V]
R01DS0376EJ0110 Rev.1.10
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35
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
AC Timing Test Points
VIH/VOH
VIL/VOL
VIH/VOH
VIL/VOL
Test points
External System Clock Timing
1/fEX/
1/fEXS
tEXL/
tEXLS
tEXH/
tEXHS
EXCLK/EXCLKS
TI/TO Timing
tTIL
tTIH
TI00 to TI07, TI10 to TI13
1/fTO
TO00 to TO07, TO10 to TO13
Interrupt Request Input Timing
tINTL
tINTH
INTP0 to INTP11
Key Interrupt Input Timing
tKR
KR0 to KR7
RESET Input Timing
tRSL
RESET
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2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
2.5 Peripheral Functions Characteristics
AC Timing Test Points
VIH/VOH
VIL/VOL
VIH/VOH
VIL/VOL
Test points
2.5.1 Serial array unit
(1) During communication at same potential (UART mode)
(TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) Mode
MIN.
Transfer rate Note 1
MAX.
2.4 V≤ EVDD0 ≤ 5.5 V
LS (low-speed
main) Mode
MIN.
fMCK/6
MAX.
LV (low-voltage
main) Mode
MIN.
Unit
MAX.
fMCK/6
fMCK/6
bps
5.3
1.3
0.6
Mbps
fMCK/6
fMCK/6
fMCK/6
bps
5.3
1.3
0.6
Mbps
fMCK/6
fMCK/6
fMCK/6
bps
Note 2
Note 2
5.3
1.3
0.6
Mbps
fMCK/6
fMCK/6
bps
0.6
Mbps
Note 2
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 3
1.8 V ≤ EVDD0 ≤ 5.5 V
Note 2
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 3
1.7 V ≤ EVDD0 ≤ 5.5 V
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 3
1.6 V ≤ EVDD0 ≤ 5.5 V
–
Note 2
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 3
–
1.3
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
2. The following conditions are required for low voltage interface when EVDD0 < VDD.
2.4 V ≤ EVDD0 < 2.7 V : MAX. 2.6 Mbps
1.8 V ≤ EVDD0 < 2.4 V : MAX. 1.3 Mbps
1.6 V ≤ EVDD0 < 1.8 V : MAX. 0.6 Mbps
3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode:
32 MHz (2.7 V ≤ VDD ≤ 5.5 V)
16 MHz (2.4 V ≤ VDD ≤ 5.5 V)
LS (low-speed main) mode:
8 MHz (1.8 V ≤ VDD ≤ 5.5 V)
LV (low-voltage main) mode:
4 MHz (1.6 V ≤ VDD ≤ 5.5 V)
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
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RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
UART mode connection diagram (during communication at same potential)
TxDq
Rx
User device
RL78 microcontroller
RxDq
Tx
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Remarks 1.
2.
q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
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RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only)
(TA = –40 to +85°C, 2.7 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) Mode
MIN.
SCKp cycle time
SCKp high-/low-level
width
SIp setup time (to SCKp↑)
tKCY1
tKH1,
tKL1
tSIK1
Note 1
SIp hold time (from SCKp↑) tKSI1
MAX.
LS (low-speed
main) Mode
MIN.
MAX.
LV (low-voltage
main) Mode
MIN.
Unit
MAX.
tKCY1 ≥ 2/fCLK 4.0 V ≤ EVDD0 ≤ 5.5 V
62.5
250
500
ns
2.7 V ≤ EVDD0 ≤ 5.5 V
83.3
250
500
ns
4.0 V ≤ EVDD0 ≤ 5.5 V
tKCY1/2 –
7
tKCY1/2 –
50
tKCY1/2 –
50
ns
2.7 V ≤ EVDD0 ≤ 5.5 V
tKCY1/2 –
10
tKCY1/2 –
50
tKCY1/2 –
50
ns
4.0 V ≤ EVDD0 ≤ 5.5 V
23
110
110
ns
2.7 V ≤ EVDD0 ≤ 5.5 V
33
110
110
ns
2.7 V ≤ EVDD0 ≤ 5.5 V
10
10
10
ns
Note 2
Delay time from SCKp↓ to
SOp output Note 3
tKSO1
C = 20 pF Note 4
10
10
10
ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin
by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
2.
This value is valid only when CSI00’s peripheral I/O redirect function is not used.
p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM numbers (g = 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
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RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) Mode
MIN.
SCKp cycle time
SCKp high-/low-level
width
SIp setup time
(to SCKp↑)
tKCY1
tKH1,
tKL1
tSIK1
MAX.
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
MIN.
MIN.
MAX.
Unit
MAX.
tKCY1 ≥ 4/fCLK 2.7 V ≤ EVDD0 ≤ 5.5 V
125
500
1000
ns
2.4 V ≤ EVDD0 ≤ 5.5 V
250
500
1000
ns
1.8 V ≤ EVDD0 ≤ 5.5 V
500
500
1000
ns
1.7 V ≤ EVDD0 ≤ 5.5 V
1000
1000
1000
ns
1.6 V ≤ EVDD0 ≤ 5.5 V
–
1000
1000
ns
4.0 V ≤ EVDD0 ≤ 5.5 V
tKCY1/2 –
12
tKCY1/2 –
50
tKCY1/2 –
50
ns
2.7 V ≤ EVDD0 ≤ 5.5 V
tKCY1/2 –
18
tKCY1/2 –
50
tKCY1/2 –
50
ns
2.4 V ≤ EVDD0 ≤ 5.5 V
tKCY1/2 –
38
tKCY1/2 –
50
tKCY1/2 –
50
ns
1.8 V ≤ EVDD0 ≤ 5.5 V
tKCY1/2 –
50
tKCY1/2 –
50
tKCY1/2 –
50
ns
1.7 V ≤ EVDD0 ≤ 5.5 V
tKCY1/2 –
100
tKCY1/2 –
100
tKCY1/2 –
100
ns
1.6 V ≤ EVDD0 ≤ 5.5 V
–
tKCY1/2 –
100
tKCY1/2 –
100
ns
4.0 V ≤ EVDD0 ≤ 5.5 V
44
110
110
ns
2.7 V ≤ EVDD0 ≤ 5.5 V
44
110
110
ns
2.4 V ≤ EVDD0 ≤ 5.5 V
75
110
110
ns
1.8 V ≤ EVDD0 ≤ 5.5 V
110
110
110
ns
1.7 V ≤ EVDD0 ≤ 5.5 V
220
220
220
ns
1.6 V ≤ EVDD0 ≤ 5.5 V
–
220
220
ns
1.7 V ≤ EVDD0 ≤ 5.5 V
19
19
19
ns
1.6 V ≤ EVDD0 ≤ 5.5 V
–
19
19
ns
Note 1
SIp hold time
(from SCKp↑) Note 2
tKSI1
Delay time from
SCKp↓ to SOp
output Note 3
tKSO1
1.7 V ≤ EVDD0 ≤ 5.5 V
C = 30 pFNote 4
25
25
25
ns
1.6 V ≤ EVDD0 ≤ 5.5 V
C = 30 pFNote 4
–
25
25
ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin
by using port input mode register g (PIMg) and port output mode register g (POMg).
R01DS0376EJ0110 Rev.1.10
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40
RL78/G13A
Remarks 1.
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM numbers (g = 0, 1, 4, 5, 8, 14)
2.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (1/2)
(TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Mode
MIN.
SCKp cycle time
tKCY2
4.0 V ≤ EVDD0 ≤ 5.5 V
MAX.
MIN.
MAX.
8/fMCK
–
–
ns
fMCK ≤ 20 MHz
6/fMCK
6/fMCK
6/fMCK
ns
16 MHz < fMCK
8/fMCK
–
–
ns
fMCK ≤ 16 MHz
6/fMCK
6/fMCK
6/fMCK
ns
2.4 V ≤ EVDD0 ≤ 5.5 V
6/fMCK
and 500
6/fMCK
and
500
6/fMCK
and
500
ns
1.8 V ≤ EVDD0 ≤ 5.5 V
6/fMCK
and 750
6/fMCK
and
750
6/fMCK
and
750
ns
1.7 V ≤ EVDD0 ≤ 5.5 V
6/fMCK
and 1500
6/fMCK
and
1500
6/fMCK
and
1500
ns
–
6/fMCK
and
1500
6/fMCK
and
1500
ns
4.0 V ≤ EVDD0 ≤ 5.5 V
tKCY2/2 – 7
tKCY2/2
–7
tKCY2/2
–7
ns
2.7 V ≤ EVDD0 ≤ 5.5 V
tKCY2/2 – 8
tKCY2/2
–8
tKCY2/2
–8
ns
1.8 V ≤ EVDD0 ≤ 5.5 V
tKCY2/2 –
18
tKCY2/2
– 18
tKCY2/2
– 18
ns
1.7 V ≤ EVDD0 ≤ 5.5 V
tKCY2/2 –
66
tKCY2/2
– 66
tKCY2/2
– 66
ns
–
tKCY2/2
– 66
tKCY2/2
– 66
ns
2.7 V ≤ EVDD0 ≤ 5.5 V
1.6 V ≤ EVDD0 ≤ 5.5 V
tKH2,
tKL2
MIN.
LV (low-voltage Unit
main) Mode
20 MHz < fMCK
Note 5
SCKp high-/lowlevel width
MAX.
LS (low-speed
main) Mode
1.6 V ≤ EVDD0 ≤ 5.5 V
(Notes, Caution, and Remarks are listed on the next page.)
R01DS0376EJ0110 Rev.1.10
Sep 18, 2020
41
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (2/2)
(TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Mode
MIN.
SIp setup time
(to SCKp↑) Note 1
tSIK2
tKSI2
MIN.
MAX.
1/fMCK+30
1/fMCK+30
ns
1.8 V ≤ EVDD0 ≤ 5.5 V
1/fMCK+30
1/fMCK+30
1/fMCK+30
ns
1.7 V ≤ EVDD0 ≤ 5.5 V
1/fMCK+40
1/fMCK+40
1/fMCK+40
ns
–
1/fMCK+40
1/fMCK+40
ns
1.8 V ≤ EVDD0 ≤ 5.5 V
1/fMCK+31
1/fMCK+31
1/fMCK+31
ns
1.7 V ≤ EVDD0 ≤ 5.5 V
1/fMCK+
250
1/fMCK+
250
1/fMCK+
250
ns
–
1/fMCK+
250
1/fMCK+
250
ns
1.6 V ≤ EVDD0 ≤ 5.5 V
tKSO2
MAX.
1/fMCK+20
Note 2
Delay time from
SCKp↓ to SOp
output Note 3
MIN.
LV (low-voltage main) Unit
Mode
2.7 V ≤ EVDD0 ≤ 5.5 V
1.6 V ≤ EVDD0 ≤ 5.5 V
SIp hold time
(from SCKp↑)
MAX.
LS (low-speed main)
Mode
C = 30 2.7 V ≤ EVDD0 ≤ 5.5 V
pF Note 4
2/fMCK+
44
2/fMCK+
110
2/fMCK+
110
ns
2.4 V ≤ EVDD0 ≤ 5.5 V
2/fMCK+
75
2/fMCK+
110
2/fMCK+
110
ns
1.8 V ≤ EVDD0 ≤ 5.5 V
2/fMCK+
110
2/fMCK+
110
2/fMCK+
110
ns
1.7 V ≤ EVDD0 ≤ 5.5 V
2/fMCK+
220
2/fMCK+
220
2/fMCK+
220
ns
1.6 V ≤ EVDD0 ≤ 5.5 V
–
2/fMCK+
220
2/fMCK+
220
ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SOp output lines.
5. Transfer rate in the SNOOZE mode: MAX. 1 Mbps
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin
by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 4, 5, 8, 14)
2.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
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2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
CSI mode connection diagram (during communication at same potential)
SCKp
SCK
RL78
microcontroller SIp
SO User device
SOp
SI
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1, 2
tKL1, 2
tKH1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
Output data
SOp
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1, 2
tKH1, 2
tKL1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Remarks 1.
2.
Output data
p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31)
m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)
R01DS0376EJ0110 Rev.1.10
Sep 18, 2020
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RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(5) During communication at same potential (simplified I2C mode) (1/2)
(TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) Mode
MIN.
SCLr clock frequency
fSCL
2.7 V ≤ EVDD0 ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
Hold time when SCLr = “H”
tLOW
tHIGH
MIN.
MAX.
LV (low-voltage
main) Mode
MIN.
1000
400
400
Note 1
Note 1
Note 1
400
400
400
Note 1
Note 1
Note 1
1.8 V ≤ EVDD0 < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
300
300
300
Note 1
Note 1
Note 1
1.7 V ≤ EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
250
250
250
Note 1
Note 1
Note 1
–
Unit
MAX.
1.8 V ≤ EVDD0 ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1.6 V ≤ EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
Hold time when SCLr = “L”
MAX.
LS (low-speed
main) Mode
250
250
Note 1
Note 1
kHz
kHz
kHz
kHz
kHz
2.7 V ≤ EVDD0 ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
475
1150
1150
ns
1.8 V ≤ EVDD0 ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1150
1150
1150
ns
1.8 V ≤ EVDD0 < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1550
1550
1550
ns
1.7 V ≤ EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
1850
1850
1850
ns
1.6 V ≤ EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
–
1850
1850
ns
2.7 V ≤ EVDD0 ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
475
1150
1150
ns
1.8 V ≤ EVDD0 ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1150
1150
1150
ns
1.8 V ≤ EVDD0 < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1550
1550
1550
ns
1.7 V ≤ EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
1850
1850
1850
ns
1.6 V ≤ EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
–
1850
1850
ns
(Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.)
R01DS0376EJ0110 Rev.1.10
Sep 18, 2020
44
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(5) During communication at same potential (simplified I2C mode) (2/2)
(TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) Mode
MIN.
Data setup time (reception)
tSU:DAT
Data hold time (transmission) tHD:DAT
MAX.
LS (low-speed
main) Mode
MIN.
MAX.
LV (low-voltage
main) Mode
MIN.
Unit
MAX.
1/fMCK
+ 145
1/fMCK
+ 145
Note2
Note2
1/fMCK
+ 145
1/fMCK
+ 145
1/fMCK
+ 145
Note2
Note2
Note2
1.8 V ≤ EVDD0 < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1/fMCK
+ 230
1/fMCK
+ 230
1/fMCK
+ 230
Note2
Note2
Note2
1.7 V ≤ EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
1/fMCK
+ 290
1/fMCK
+ 290
1/fMCK
+ 290
Note2
Note2
Note2
1.6 V ≤ EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
–
1/fMCK
+ 290
1/fMCK
+ 290
Note2
Note2
2.7 V ≤ EVDD0 ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
0
305
0
305
0
305
ns
1.8 V ≤ EVDD0 ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
0
355
0
355
0
355
ns
1.8 V ≤ EVDD0 < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
0
405
0
405
0
405
ns
1.7 V ≤ EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
0
405
0
405
0
405
ns
0
405
0
405
ns
2.7 V ≤ EVDD0 ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK +
85 Note2
1.8 V ≤ EVDD0 ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1.6 V ≤ EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 kΩ
–
ns
ns
ns
ns
ns
Notes 1. The value must also be equal to or less than fMCK/4.
2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H".
Caution
Select the normal input buffer and the N-ch open drain output (VDD tolerance (When 44- and 48-pin
products)/EVDD tolerance (When 64- and 100-pin products)) mode for the SDAr pin and the normal
output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register
h (POMh).
(Remarks are listed on the next page.)
R01DS0376EJ0110 Rev.1.10
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45
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
Simplified I2C mode mode connection diagram (during communication at same potential)
VDD
Rb
SDAr
SDA
User device
RL78 microcontroller
SCLr
SCL
Simplified I2C mode serial transfer timing (during communication at same potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD:DAT
tSU:DAT
Remarks 1. Rb[Ω]:Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load
capacitance
2. r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM number (g = 0, 1, 4, 5, 8, 14),
h: POM number (g = 0, 1, 4, 5, 7 to 9, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13)
R01DS0376EJ0110 Rev.1.10
Sep 18, 2020
46
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2)
(TA = –40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
HS (high-speed LS (low-speed LV (low-voltage Unit
main) Mode
main) Mode
main) Mode
Conditions
MIN.
Transfer rate
Reception
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
Theoretical value
of the maximum
transfer rate
fMCK = fCLK Note 4
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
Theoretical value
of the maximum
transfer rate
fMCK = fCLK Note 4
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Theoretical value
of the maximum
transfer rate
fMCK = fCLK Note 4
MAX.
MIN.
MAX.
MIN.
MAX.
fMCK/6
fMCK/6
fMCK/6
Note 1
Note 1
Note 1
5.3
1.3
0.6
Mbps
fMCK/6
fMCK/6
fMCK/6
bps
Note 1
Note 1
Note 1
5.3
1.3
0.6
Mbps
bps
fMCK/6
fMCK/6
fMCK/6
Notes 1 to 3
Notes 1, 2
Notes 1, 2
5.3
1.3
0.6
bps
Mbps
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
2. Use it with EVDD0 ≥ Vb.
3. The following conditions are required for low voltage interface when EVDD0 < VDD.
2.4 V ≤ EVDD0 < 2.7 V : MAX. 2.6 Mbps
1.8 V ≤ EVDD0 < 2.4 V : MAX. 1.3 Mbps
4. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode:
32 MHz (2.7 V ≤ VDD ≤ 5.5 V)
16 MHz (2.4 V ≤ VDD ≤ 5.5 V)
Caution
LS (low-speed main) mode:
8 MHz (1.8 V ≤ VDD ≤ 5.5 V)
LV (low-voltage main) mode:
4 MHz (1.6 V ≤ VDD ≤ 5.5 V)
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When 44and 48-pin products)/EVDD tolerance (When 64- and 100-pin products)) mode for the TxDq pin by using
port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC
characteristics with TTL input buffer selected.
Remarks 1.
Vb[V]: Communication line voltage
2.
q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13)
4.
UART2 cannot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redirection register
(PIOR) is 1.
R01DS0376EJ0110 Rev.1.10
Sep 18, 2020
47
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2)
(TA = –40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
HS (high- LS (low-speed LV (lowspeed main) main) Mode voltage main)
Mode
Mode
Conditions
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Transfer rate
Transmission 4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
Note 1
Theoretical
value of the
maximum
transfer rate
Note 1
Note 1
bps
Mbps
2.8
2.8
2.8
Note 2
Note 2
Note 2
Note 3
Note 3
Note 3
bps
Mbps
Cb = 50 pF, Rb =
1.4 kΩ, Vb = 2.7 V
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
Theoretical
value of the
maximum
transfer rate
1.2
1.2
1.2
Note 4
Note 4
Note 4
Notes
Notes
Notes
5, 6
5, 6
5, 6
0.43
0.43
0.43
Note 7
Note 7
Note 7
Cb = 50 pF, Rb =
2.7 kΩ, Vb = 2.3 V
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Theoretical
value of the
maximum
transfer rate
bps
Mbps
Cb = 50 pF, Rb =
5.5 kΩ, Vb = 1.6 V
Notes 1.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 4.0 V ≤ EVDD0 ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V
1
Maximum transfer rate =
{–Cb × Rb × ln (1 –
Baud rate error (theoretical value) =
2.2
Vb )} × 3
[bps]
2.2
1
Transfer rate × 2 – {–Cb × Rb × ln (1 – Vb )}
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
R01DS0376EJ0110 Rev.1.10
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48
RL78/G13A
Notes 3.
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ EVDD0 < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V
1
Maximum transfer rate =
{–Cb × Rb × ln (1 –
Baud rate error (theoretical value) =
2.0
Vb )} × 3
[bps]
2.0
1
Transfer rate × 2 – {–Cb × Rb × ln (1 – Vb )}
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
4.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
5.
Use it with EVDD0 ≥ Vb.
Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
6.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 1.8 V ≤ EVDD0 < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V
1
Maximum transfer rate =
{–Cb × Rb × ln (1 –
Baud rate error (theoretical value) =
1.5
Vb )} × 3
[bps]
1.5
1
Transfer rate × 2 – {–Cb × Rb × ln (1 – Vb )}
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
7.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When 44and 48-pin products)/EVDD tolerance (When 64- and 100-pin products)) mode for the TxDq pin by using
port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC
characteristics with TTL input buffer selected.
UART mode connection diagram (during communication at different potential)
Vb
Rb
TxDq
Rx
User device
RL78 microcontroller
RxDq
R01DS0376EJ0110 Rev.1.10
Sep 18, 2020
Tx
49
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Remarks 1.
Rb[Ω]:Communication line (TxDq) pull-up resistance,
Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
2.
q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13))
4. UART2 cannot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redirection register
(PIOR) is 1.
R01DS0376EJ0110 Rev.1.10
Sep 18, 2020
50
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only) (1/2)
(TA = –40 to +85°C, 2.7 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
SCKp cycle time
Symbol
tKCY1
Conditions
tKCY1 ≥ 2/fCLK
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
MIN.
MIN.
MIN.
MAX.
MAX.
Unit
MAX.
200
1150
1150
ns
300
1150
1150
ns
tKCY1/2 –
50
tKCY1/2 –
50
tKCY1/2 –
50
ns
tKCY1/2 –
120
tKCY1/2 –
120
tKCY1/2 –
120
ns
tKCY1/2 –
7
tKCY1/2 –
50
tKCY1/2 –
50
ns
tKCY1/2 –
10
tKCY1/2 –
50
tKCY1/2 –
50
ns
58
479
479
ns
121
479
479
ns
10
10
10
ns
10
10
10
ns
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SCKp high-level
width
tKH1
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SCKp low-level
width
tKL1
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SIp setup time
(to SCKp↑) Note 1
tSIK1
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SIp hold time
tKSI1
(from SCKp↑) Note 1
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
Delay time from
SCKp↓ to SOp
output Note 1
tKSO1
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
60
60
60
ns
130
130
130
ns
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
(Notes, Caution, and Remarks are listed on the next page.)
R01DS0376EJ0110 Rev.1.10
Sep 18, 2020
51
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only) (2/2)
(TA = –40 to +85°C, 2.7 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
SIp setup time
(to SCKp↓) Note 2
Symbol
tSIK1
Conditions
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
MIN.
MIN.
MIN.
MAX.
MAX.
Unit
MAX.
23
110
110
ns
33
110
110
ns
10
10
10
ns
10
10
10
ns
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SIp hold time
(from SCKp↓) Note 2
tKSI1
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
Delay time from SCKp↑
to
SOp output Note 2
tKSO1
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
10
10
10
ns
10
10
10
ns
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 44- and
48-pin products)/EVDD tolerance (When 64- and 100-pin products)) mode for the SOp pin and SCKp pin
by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see
the DC characteristics with TTL input buffer selected.
Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load
capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM number (g = 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
4. This value is valid only when CSI00’s peripheral I/O redirect function is not used.
R01DS0376EJ0110 Rev.1.10
Sep 18, 2020
52
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (1/3)
(TA = –40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
SCKp cycle time tKCY1
Conditions
tKCY1 ≥ 4/fCLK 4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
MIN.
MIN.
MIN.
MAX.
MAX.
Unit
MAX.
300
1150
1150
ns
500
1150
1150
ns
1150
1150
1150
ns
tKCY1/2 –
75
tKCY1/2 –
75
tKCY1/2 –
75
ns
tKCY1/2 –
170
tKCY1/2 –
170
tKCY1/2 –
170
ns
tKCY1/2 –
458
tKCY1/2 –
458
tKCY1/2 –
458
ns
tKCY1/2 –
12
tKCY1/2 –
50
tKCY1/2 –
50
ns
tKCY1/2 –
18
tKCY1/2 –
50
tKCY1/2 –
50
ns
tKCY1/2 –
50
tKCY1/2 –
50
tKCY1/2 –
50
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note,
Cb = 30 pF, Rb = 5.5 kΩ
SCKp high-level
width
tKH1
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note,
Cb = 30 pF, Rb = 5.5 kΩ
SCKp low-level
width
tKL1
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note,
Cb = 30 pF, Rb = 5.5 kΩ
Note
Use it with EVDD0 ≥ Vb.
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 44- and
48-pin products)/EVDD tolerance (When 64- and 100-pin products)) mode for the SOp pin and SCKp pin
by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see
the DC characteristics with TTL input buffer selected.
(Remarks are listed two pages after the next page.)
R01DS0376EJ0110 Rev.1.10
Sep 18, 2020
53
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (2/3)
(TA = –40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) Mode
MIN.
SIp setup time
(to SCKp↑) Note 1
tSIK1
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
MAX.
LS (low-speed main)
Mode
MIN.
MAX.
LV (low-voltage
main) Mode
MIN.
Unit
MAX.
81
479
479
ns
177
479
479
ns
479
479
479
ns
19
19
19
ns
19
19
19
ns
19
19
19
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 kΩ
SIp hold time
(from SCKp↑) Note 1
tKSI1
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 kΩ
Delay time from SCKp↓
to
SOp output Note 1
tKSO1
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
100
100
100
ns
195
195
195
ns
483
483
483
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 kΩ
Notes
1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
2. Use it with EVDD0 ≥ Vb.
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 44- and
48-pin products)/EVDD tolerance (When 64- and 100-pin products)) mode for the SOp pin and SCKp pin
by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see
the DC characteristics with TTL input buffer selected.
(Remarks are listed on the page after the next page.)
R01DS0376EJ0110 Rev.1.10
Sep 18, 2020
54
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (3/3)
(TA = –40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) Mode
MIN.
SIp setup time
(to SCKp↓) Note 1
tSIK1
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
MAX.
LS (low-speed main)
Mode
MIN.
MAX.
LV (low-voltage
main) Mode
MIN.
Unit
MAX.
44
110
110
ns
44
110
110
ns
110
110
110
ns
19
19
19
ns
19
19
19
ns
19
19
19
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 kΩ
SIp hold time
(from SCKp↓) Note 1
tKSI1
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 kΩ
Delay time from SCKp↑
to
SOp output Note 1
tKSO1
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
25
25
25
ns
25
25
25
ns
25
25
25
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 kΩ
Notes
1. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. Use it with EVDD0 ≥ Vb.
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 44- and
48-pin products)/EVDD tolerance (When 64- and 100-pin products)) mode for the SOp pin and SCKp pin
by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see
the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
R01DS0376EJ0110 Rev.1.10
Sep 18, 2020
55
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
CSI mode connection diagram (during communication at different potential)
Vb
Vb
Rb
Rb
SCKp
SIp
RL78
microcontroller
SOp
SCK
SO
User device
SI
Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load
capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number , n: Channel number (mn = 00, 01, 02, 10, 12,
13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00))
4. CSI01 of 48- and 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use
other CSI for communication at different potential.
R01DS0376EJ0110 Rev.1.10
Sep 18, 2020
56
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
Output data
SOp
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
Output data
Remarks 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13),
g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
2. CSI01 of 48- and 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use
other CSI for communication at different potential.
R01DS0376EJ0110 Rev.1.10
Sep 18, 2020
57
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)
(TA = –40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2)
Parameter
Symbol
Conditions
HS (high-speed LS (low-speed LV (low-voltage Unit
main) Mode
main) Mode
main) Mode
MIN.
SCKp cycle time Note 1
tKCY2
4.0 V ≤ EVDD0 ≤ 5.5 V, 24 MHz < fMCK
MIN.
MAX.
MIN.
MAX.
14/
fMCK
–
–
ns
20 MHz < fMCK ≤ 24 MHz
12/
fMCK
–
–
ns
8 MHz < fMCK ≤ 20 MHz
10/
fMCK
–
–
ns
4 MHz < fMCK ≤ 8 MHz
8/fMCK
16/
fMCK
–
ns
fMCK ≤ 4 MHz
6/fMCK
10/
fMCK
10/
fMCK
ns
20/
fMCK
–
–
ns
20 MHz < fMCK ≤ 24 MHz
16/
fMCK
–
–
ns
16 MHz < fMCK ≤ 20 MHz
14/
fMCK
–
–
ns
8 MHz < fMCK ≤ 16 MHz
12/
fMCK
–
–
ns
4 MHz < fMCK ≤ 8 MHz
8/fMCK
16/
fMCK
–
ns
fMCK ≤ 4 MHz
6/fMCK
10/
fMCK
10/
fMCK
ns
48/
fMCK
–
–
ns
20 MHz < fMCK ≤ 24 MHz
36/
fMCK
–
–
ns
16 MHz < fMCK ≤ 20 MHz
32/
fMCK
–
–
ns
8 MHz < fMCK ≤ 16 MHz
26/
fMCK
–
–
ns
4 MHz < fMCK ≤ 8 MHz
16/
fMCK
16/
fMCK
–
ns
fMCK ≤ 4 MHz
10/
fMCK
10/
fMCK
10/
fMCK
ns
2.7 V ≤ Vb ≤ 4.0 V
2.7 V ≤ EVDD0 < 4.0 V, 24 MHz < fMCK
2.3 V ≤ Vb ≤ 2.7 V
1.8 V ≤ EVDD0 < 3.3 V, 24 MHz < fMCK
1.6 V ≤ Vb ≤ 2.0 V
MAX.
Note 2
(Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.)
R01DS0376EJ0110 Rev.1.10
Sep 18, 2020
58
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)
(TA = –40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
Parameter
Symbol
Conditions
HS (high-speed LS (low-speed LV (low-voltage Unit
main) Mode
main) Mode
main) Mode
MIN.
SCKp high-/low-level
width
SIp setup time
(to SCKp↑) Note 3
tKH2,
tKL2
tSIK2
Delay time from
SCKp↓ to SOp output
tKSO2
Note 5
MAX.
MIN.
MAX.
tKCY2/2 –
tKCY2/2
tKCY2/2
12
– 50
– 50
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
tKCY2/2 –
tKCY2/2
tKCY2/2
18
– 50
– 50
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note 2
tKCY2/2 –
tKCY2/2
tKCY2/2
50
– 50
– 50
4.0 V ≤ EVDD0 ≤ 5.5 V,
1/fMCK
+ 20
1/fMCK
+ 30
1/fMCK
+ 30
ns
1/fMCK
+ 30
1/fMCK
+ 30
ns
2.3 V ≤ Vb ≤ 2.7 V
1/fMCK
+ 20
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note 2
1/fMCK
+ 30
1/fMCK
+ 30
1/fMCK
+ 30
ns
1/fMCK +
31
1/fMCK
+ 31
1/fMCK
+ 31
ns
2.7 V ≤ EVDD0 < 4.0 V,
tKSI2
MIN.
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
2.7 V ≤ Vb ≤ 4.0 V
SIp hold time
(from SCKp↑) Note 4
MAX.
ns
ns
ns
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2/fMCK
+ 120
2/fMCK
+ 573
2/fMCK
+ 573
ns
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2/fMCK
+ 214
2/fMCK +
573
2/fMCK +
573
ns
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 kΩ
2/fMCK
+ 573
2/fMCK +
573
2/fMCK +
573
ns
Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
2. Use it with EVDD0 ≥ Vb.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (for the 44- and
48-pin products)/EVDD tolerance (for the 64- and 100-pin products)) mode for the SOp pin and SCKp pin
by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see
the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
R01DS0376EJ0110 Rev.1.10
Sep 18, 2020
59
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
CSI mode connection diagram (during communication at different potential)
Vb
Rb
SCKp
RL78
microcontroller SIp
SOp
SCK
SO
User device
SI
Remarks 1. Rb[Ω]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance,
Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13),
g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13))
4. CSI01 of 48- and 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use
other CSI for communication at different potential.
R01DS0376EJ0110 Rev.1.10
Sep 18, 2020
60
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY2
tKL2
tKH2
SCKp
tSIK2
SIp
tKSI2
Input data
tKSO2
Output data
SOp
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY2
tKL2
tKH2
SCKp
tSIK2
SIp
tKSI2
Input data
tKSO2
SOp
Output data
Remarks 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number,
n: Channel number (mn = 00, 01, 02, 10, 12. 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
2. CSI01 of 48- and 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use
other CSI for communication at different potential.
R01DS0376EJ0110 Rev.1.10
Sep 18, 2020
61
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (1/2)
(TA = –40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
SCLr clock frequency
Symbol
fSCL
Conditions
HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
MIN.
MIN.
MIN.
300
300
Note 1
Note 1
Note 1
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
1000
300
300
Note 1
Note 1
Note 1
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
R01DS0376EJ0110 Rev.1.10
Sep 18, 2020
MAX.
1000
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
Hold time when SCLr = tHIGH
“H”
MAX.
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
Hold time when SCLr = tLOW
“L”
MAX.
Unit
400
300
300
Note 1
Note 1
Note 1
400
300
300
Note 1
Note 1
ote 1
300
300
300
Note 1
Note 1
Note 1
kHz
kHz
kHz
kHz
kHz
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
475
1550
1550
ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
475
1550
1550
ns
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
1150
1550
1550
ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1150
1550
1550
ns
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
1550
1550
1550
ns
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
245
610
610
ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
200
610
610
ns
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
675
610
610
ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
600
610
610
ns
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
610
610
610
ns
62
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2)
(TA = –40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Data setup time
(reception)
Data hold time
(transmission)
Symbol
tSU:DAT
tHD:DAT
Conditions
HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
MIN.
MIN.
MIN.
MAX.
MAX.
1/fMCK
+ 190
1/fMCK
+ 190
Note 3
Note 3
1/fMCK
+ 190
1/fMCK
+ 190
Note 3
Note 3
1/fMCK
+ 190
1/fMCK
+ 190
Note 3
Note 3
1/fMCK
+ 190
1/fMCK
+ 190
Note 3
Note 3
1/fMCK
+ 190
1/fMCK
+ 190
Note 3
Note 3
Unit
MAX.
kHz
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK +
135 Note 3
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK +
135 Note 3
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
1/fMCK +
190 Note 3
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1/fMCK +
190 Note 3
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
1/fMCK +
190 Note 3
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
0
305
0
305
0
305
ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
0
305
0
305
0
305
ns
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
0
355
0
355
0
355
ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
0
355
0
355
0
355
ns
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 kΩ
0
405
0
405
0
405
ns
kHz
kHz
kHz
kHz
Notes 1. The value must also be equal to or less than fMCK/4.
2. Use it with EVDD0 ≥ Vb.
3. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H".
Caution
Select the TTL input buffer and the N-ch open drain output (VDD tolerance (for the 44- and 48-pin
products)/EVDD tolerance (for the 64- and 100-pin products)) mode for the SDAr pin and the N-ch open
drain output (VDD tolerance (for the 44- and 48-pin products)/EVDD tolerance (for the 64- and 100-pin
products)) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode
register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
R01DS0376EJ0110 Rev.1.10
Sep 18, 2020
63
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
Simplified I2C mode connection diagram (during communication at different potential)
Vb
Vb
Rb
Rb
SDAr
SDA
RL78
microcontroller
User device
SCLr
SCL
Simplified I2C mode serial transfer timing (during communication at different potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD:DAT
tSU:DAT
Remarks 1. Rb[Ω]:Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load
capacitance, Vb[V]: Communication line voltage
2. r: IIC number (r = 00, 01, 10, 20, 30, 31), g: PIM, POM number (g = 0, 1, 4, 5, 8, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01, 02, 10, 12, 13)
R01DS0376EJ0110 Rev.1.10
Sep 18, 2020
64
RL78/G13A
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
2.5.2 Serial interface IICA
(1) I2C standard mode
(TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
SCLA0 clock frequency
Symbol
fSCL
Conditions
HS (high-speed
main) Mode
tSU:STA
tHD:STA
MIN.
MAX.
MIN.
MAX.
Standard mode: 2.7 V ≤ EVDD0 ≤ 5.5 V
fCLK ≥ 1 MHz
1.8 V ≤ EVDD0 ≤ 5.5 V
0
100
0
100
0
100
kHz
0
100
0
100
0
100
kHz
1.7 V ≤ EVDD0 ≤ 5.5 V
0
100
0
100
0
100
kHz
0
100
0
100
kHz
–
2.7 V ≤ EVDD0 ≤ 5.5 V
4.7
4.7
4.7
µs
1.8 V ≤ EVDD0 ≤ 5.5 V
4.7
4.7
4.7
µs
1.7 V ≤ EVDD0 ≤ 5.5 V
4.7
4.7
4.7
µs
4.7
4.7
µs
2.7 V ≤ EVDD0 ≤ 5.5 V
4.0
–
4.0
4.0
µs
1.8 V ≤ EVDD0 ≤ 5.5 V
4.0
4.0
4.0
µs
1.7 V ≤ EVDD0 ≤ 5.5 V
4.0
4.0
4.0
µs
4.0
4.0
µs
1.6 V ≤ EVDD0 ≤ 5.5 V
Hold time when SCLA0 =
“L”
tLOW
–
2.7 V ≤ EVDD0 ≤ 5.5 V
4.7
4.7
4.7
µs
1.8 V ≤ EVDD0 ≤ 5.5 V
4.7
4.7
4.7
µs
1.7 V ≤ EVDD0 ≤ 5.5 V
4.7
4.7
4.7
µs
1.6 V ≤ EVDD0 ≤ 5.5 V
Hold time when SCLA0 =
“H”
tHIGH
4.7
4.7
µs
2.7 V ≤ EVDD0 ≤ 5.5 V
4.0
–
4.0
4.0
µs
1.8 V ≤ EVDD0 ≤ 5.5 V
4.0
4.0
4.0
µs
1.7 V ≤ EVDD0 ≤ 5.5 V
4.0
4.0
4.0
µs
4.0
4.0
µs
1.6 V ≤ EVDD0 ≤ 5.5 V
Data setup time
(reception)
tSU:DAT
–
2.7 V ≤ EVDD0 ≤ 5.5 V
250
250
250
ns
1.8 V ≤ EVDD0 ≤ 5.5 V
250
250
250
ns
1.7 V ≤ EVDD0 ≤ 5.5 V
250
250
250
ns
1.6 V ≤ EVDD0 ≤ 5.5 V
Data hold time
(transmission)Note 2
tHD:DAT
–
tSU:STO
tBUF
250
ns
0
3.45
0
3.45
0
3.45
µs
1.8 V ≤ EVDD0 ≤ 5.5 V
0
3.45
0
3.45
0
3.45
µs
1.7 V ≤ EVDD0 ≤ 5.5 V
0
3.45
0
3.45
0
3.45
µs
0
3.45
0
3.45
µs
–
2.7 V ≤ EVDD0 ≤ 5.5 V
4.0
4.0
4.0
µs
1.8 V ≤ EVDD0 ≤ 5.5 V
4.0
4.0
4.0
µs
1.7 V ≤ EVDD0 ≤ 5.5 V
4.0
4.0
4.0
µs
1.6 V ≤ EVDD0 ≤ 5.5 V
Bus-free time
250
2.7 V ≤ EVDD0 ≤ 5.5 V
1.6 V ≤ EVDD0 ≤ 5.5 V
Setup time of stop
condition
Unit
MAX.
1.6 V ≤ EVDD0 ≤ 5.5 V
Hold timeNote 1
LV (low-voltage
main) Mode
MIN.
1.6 V ≤ EVDD0 ≤ 5.5 V
Setup time of restart
condition
LS (low-speed
main) Mode
4.0
4.0
µs
2.7 V ≤ EVDD0 ≤ 5.5 V
4.7
4.7
4.7
µs
1.8 V ≤ EVDD0 ≤ 5.5 V
4.7
4.7
4.7
µs
1.7 V ≤ EVDD0 ≤ 5.5 V
4.7
4.7
4.7
µs
4.7
4.7
µs
1.6 V ≤ EVDD0 ≤ 5.5 V
–
–
(Notes, Caution and Remark are listed on the next page.)
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Notes 1.
2.
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection
register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in
the redirect destination.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 kΩ
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2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(2) I2C fast mode
(TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
SCLA0 clock frequency
Symbol
fSCL
Conditions
Fast mode:
fCLK ≥ 3.5 MHz
Setup time of restart
condition
tSU:STA
Hold time
tHD:STA
Note 1
Hold time when SCLA0 =
“L”
tLOW
Hold time when SCLA0 =
“H”
tHIGH
Data setup time
(reception)
tSU:DAT
Data hold time
(transmission)Note 2
tHD:DAT
Setup time of stop
condition
tSU:STO
Bus-free time
tBUF
Notes 1.
2.
HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
2.7 V ≤ EVDD0 ≤ 5.5 V
0
400
0
400
0
400
kHz
1.8 V ≤ EVDD0 ≤ 5.5 V
0
400
0
400
0
400
kHz
2.7 V ≤ EVDD0 ≤ 5.5 V
0.6
0.6
0.6
µs
1.8 V ≤ EVDD0 ≤ 5.5 V
0.6
0.6
0.6
µs
2.7 V ≤ EVDD0 ≤ 5.5 V
0.6
0.6
0.6
µs
1.8 V ≤ EVDD0 ≤ 5.5 V
0.6
0.6
0.6
µs
2.7 V ≤ EVDD0 ≤ 5.5 V
1.3
1.3
1.3
µs
1.8 V ≤ EVDD0 ≤ 5.5 V
1.3
1.3
1.3
µs
2.7 V ≤ EVDD0 ≤ 5.5 V
0.6
0.6
0.6
µs
1.8 V ≤ EVDD0 ≤ 5.5 V
0.6
0.6
0.6
µs
2.7 V ≤ EVDD0 ≤ 5.5 V
100
100
100
µs
1.8 V ≤ EVDD0 ≤ 5.5 V
100
100
100
µs
2.7 V ≤ EVDD0 ≤ 5.5 V
0
0.9
0
0.9
0
0.9
µs
1.8 V ≤ EVDD0 ≤ 5.5 V
0
0.9
0
0.9
0
0.9
µs
2.7 V ≤ EVDD0 ≤ 5.5 V
0.6
0.6
0.6
µs
1.8 V ≤ EVDD0 ≤ 5.5 V
0.6
0.6
0.6
µs
2.7 V ≤ EVDD0 ≤ 5.5 V
1.3
1.3
1.3
µs
1.8 V ≤ EVDD0 ≤ 5.5 V
1.3
1.3
1.3
µs
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection
register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in
the redirect destination.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Fast mode:
Cb = 320 pF, Rb = 1.1 kΩ
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2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(3) I2C fast mode plus
(TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
HS (high-speed
main) Mode
Conditions
Fast mode plus: 2.7 V ≤ EVDD0 ≤ 5.5 V
fCLK ≥ 10 MHz
SCLA0 clock frequency
fSCL
Setup time of restart
condition
tSU:STA
2.7 V ≤ EVDD0 ≤ 5.5 V
Hold timeNote 1
tHD:STA
Hold time when SCLA0 =
“L”
MIN.
MAX.
0
1000
LS (low-speed
main) Mode
MIN.
MAX.
LV (low-voltage
main) Mode
MIN.
Unit
MAX.
–
–
kHz
0.26
–
–
µs
2.7 V ≤ EVDD0 ≤ 5.5 V
0.26
–
–
µs
tLOW
2.7 V ≤ EVDD0 ≤ 5.5 V
0.5
–
–
µs
Hold time when SCLA0 =
“H”
tHIGH
2.7 V ≤ EVDD0 ≤ 5.5 V
0.26
–
–
µs
Data setup time
(reception)
tSU:DAT
2.7 V ≤ EVDD0 ≤ 5.5 V
50
–
–
µs
Data hold time
(transmission)Note 2
tHD:DAT
2.7 V ≤ EVDD0 ≤ 5.5 V
0
–
–
µs
Setup time of stop
condition
tSU:STO
2.7 V ≤ EVDD0 ≤ 5.5 V
0.26
–
–
µs
Bus-free time
tBUF
2.7 V ≤ EVDD0 ≤ 5.5 V
0.5
–
–
µs
Notes 1.
2.
0.45
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection
register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in
the redirect destination.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Fast mode plus: Cb = 120 pF, Rb = 1.1 kΩ
IICA serial transfer timing
tLOW
tR
SCLAn
tHD:DAT
tHD:STA
tHIGH
tF
tSU:STA
tHD:STA
tSU:STO
tSU:DAT
SDAAn
tBUF
Stop
condition
Start
condition
Restart
condition
Stop
condition
Remark n = 0, 1
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2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
2.6 Analog Characteristics
2.6.1 A/D converter characteristics
Classification of A/D converter characteristics
Reference Voltage
Reference voltage (+) = AVREFP
Reference voltage (+) = VDD
Reference voltage (+) = VBGR
Input channel
Reference voltage (–) = AVREFM
Reference voltage (–) = VSS
Reference voltage (–) = AVREFM
ANI0 to ANI14
Refer to 2.6.1 (1).
Refer to 2.6.1 (3).
Refer to 2.6.1 (4).
ANI16 to ANI20
Refer to 2.6.1 (2).
Internal reference voltage
Refer to 2.6.1 (1).
–
Temperature sensor output
voltage
(1) When reference voltage (+)= AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (–) = AVREFM/ANI1
(ADREFM = 1), target pin : ANI2 to ANI14, internal reference voltage, and temperature sensor output voltage
(TA = –40 to +85°C, 1.6 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (–) =
AVREFM = 0 V)
Parameter
Symbol
Resolution
RES
Overall errorNote 1
AINL
Conversion time
tCONV
Conditions
MIN.
Full-scale errorNotes 1, 2
Integral linearity error
Note 1
EZS
EFS
ILE
Differential linearity error Note 1 DLE
Analog input voltage
VAIN
MAX.
8
Unit
10
bit
10-bit resolution
AVREFP = VDD Note 3
1.8 V ≤ AVREFP ≤ 5.5 V
1.2
±3.5
LSB
1.6 V ≤ AVREFP ≤ 5.5 V Note 4
1.2
±7.0
LSB
10-bit resolution
Target pin: ANI2 to ANI14
3.6 V ≤ VDD ≤ 5.5 V
2.125
39
µs
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
µs
1.8 V ≤ VDD ≤ 5.5 V
17
39
µs
1.6 V ≤ VDD ≤ 5.5 V
57
95
µs
2.375
39
µs
3.5625
39
µs
17
39
µs
±0.25
%FSR
10-bit resolution
3.6 V ≤ VDD ≤ 5.5 V
Target pin: Internal
2.7 V ≤ VDD ≤ 5.5 V
reference voltage, and
2.4 V ≤ VDD ≤ 5.5 V
temperature sensor output
voltage
(HS (high-speed main)
mode)
Zero-scale errorNotes 1, 2
TYP.
10-bit resolution
AVREFP = VDD Note 3
1.8 V ≤ AVREFP ≤ 5.5 V
±0.50
%FSR
10-bit resolution
AVREFP = VDD Note 3
1.8 V ≤ AVREFP ≤ 5.5 V
±0.25
%FSR
1.6 V ≤ AVREFP ≤ 5.5 V Note 4
±0.50
%FSR
10-bit resolution
AVREFP = VDD Note 3
1.8 V ≤ AVREFP ≤ 5.5 V
±2.5
LSB
±5.0
LSB
10-bit resolution
AVREFP = VDD Note 3
1.8 V ≤ AVREFP ≤ 5.5 V
±1.5
LSB
1.6 V ≤ AVREFP ≤ 5.5 V Note 4
±2.0
LSB
AVREFP
V
1.6 V ≤ AVREFP ≤ 5.5 V
1.6 V ≤ AVREFP ≤ 5.5 V
ANI2 to ANI14
Internal reference voltage
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode)
Temperature sensor output voltage
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode)
Note 4
Note 4
0
VBGR
Note 5
VTMPS25 Note 5
V
V
(Notes are listed on the next page.)
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2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD.
4. Values when the conversion time is set to 57 µs (min.) and 95 µs (max.).
5. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.
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2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (–) = AVREFM/ANI1
(ADREFM = 1), target pin : ANI16 to ANI20
(TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, 1.6 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V,
Reference voltage (+) = AVREFP, Reference voltage (–) = AVREFM = 0 V)
Parameter
Symbol
Resolution
RES
Overall errorNote 1
AINL
Conversion time
tCONV
Zero-scale error
Notes 1, 2
Full-scale errorNotes 1, 2
Integral linearity error
Note 1
EZS
EFS
ILE
Differential linearity
error Note 1
DLE
Analog input voltage
VAIN
Conditions
MIN.
TYP.
MAX.
Unit
10
bit
1.2
±5.0
LSB
1.2
±8.5
LSB
8
10-bit resolution
EVDD0 = AVREFP = VDD Notes 3, 4
1.8 V ≤ AVREFP ≤ 5.5 V
10-bit resolution
Target ANI pin : ANI16 to
ANI20
3.6 V ≤ VDD ≤ 5.5 V
2.125
39
µs
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
µs
1.8 V ≤ VDD ≤ 5.5 V
17
39
µs
1.6 V ≤ VDD ≤ 5.5 V
57
95
µs
1.6 V ≤ AVREFP ≤ 5.5 V
Note 5
10-bit resolution
EVDD0 = AVREFP = VDD Notes 3, 4
1.8 V ≤ AVREFP ≤ 5.5 V
±0.35
%FSR
1.6 V ≤ AVREFP ≤ 5.5 V Note 5
±0.60
%FSR
10-bit resolution
EVDD0 = AVREFP = VDD Notes 3, 4
1.8 V ≤ AVREFP ≤ 5.5 V
±0.35
%FSR
±0.60
%FSR
10-bit resolution
EVDD0 = AVREFP = VDD Notes 3, 4
1.8 V ≤ AVREFP ≤ 5.5 V
±3.5
LSB
±6.0
LSB
10-bit resolution
EVDD0 = AVREFP = VDD Notes 3, 4
1.8 V ≤ AVREFP ≤ 5.5 V
±2.0
LSB
±2.5
LSB
AVREFP
and EVDD0
V
1.6 V ≤ AVREFP ≤ 5.5 V
1.6 V ≤ AVREFP ≤ 5.5 V
1.6 V ≤ AVREFP ≤ 5.5 V
ANI16 to ANI20
Note 5
Note 5
Note 5
0
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD.
4. When AVREFP < EVDD0 ≤ VDD, the MAX. values are as follows.
Overall error: Add ±4.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.20%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±2.0 LSB to the MAX. value when AVREFP = VDD.
5. When the conversion time is set to 57 µs (min.) and 95 µs (max.).
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2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (–) = VSS (ADREFM = 0),
target pin : ANI0 to ANI14, ANI16 to ANI20, internal reference voltage, and temperature sensor output voltage
(TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VDD,
Reference voltage (–) = VSS)
Parameter
Symbol
Resolution
RES
Overall errorNote 1
AINL
Conditions
MIN.
TYP.
8
10-bit resolution
MAX.
Unit
10
bit
1.8 V ≤ VDD ≤ 5.5 V
1.2
±7.0
LSB
1.6 V ≤ VDD ≤ 5.5 V
1.2
±10.5
LSB
Note 3
Conversion time
Conversion time
Zero-scale errorNotes 1, 2
tCONV
tCONV
EZS
10-bit resolution
Target pin: ANI0 to ANI14,
ANI16 to ANI20
10-bit resolution
Target pin: Internal
reference voltage, and
temperature sensor output
voltage (HS (high-speed
main) mode)
10-bit resolution
3.6 V ≤ VDD ≤ 5.5 V
2.125
39
µs
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
µs
1.8 V ≤ VDD ≤ 5.5 V
17
39
µs
1.6 V ≤ VDD ≤ 5.5 V
57
95
µs
3.6 V ≤ VDD ≤ 5.5 V
2.375
39
µs
2.7 V ≤ VDD ≤ 5.5 V
3.5625
39
µs
2.4 V ≤ VDD ≤ 5.5 V
17
39
µs
1.8 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
1.6 V ≤ VDD ≤ 5.5 V
±0.85
%FSR
1.8 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
1.6 V ≤ VDD ≤ 5.5 V
±0.85
%FSR
1.8 V ≤ VDD ≤ 5.5 V
±4.0
LSB
1.6 V ≤ VDD ≤ 5.5 V
±6.5
LSB
1.8 V ≤ VDD ≤ 5.5 V
±2.0
LSB
1.6 V ≤ VDD ≤ 5.5 V
±2.5
LSB
VDD
V
EVDD0
V
Note 3
Full-scale errorNotes 1, 2
EFS
10-bit resolution
Note 3
Integral linearity errorNote 1
ILE
10-bit resolution
Note 3
Differential linearity error Note 1
DLE
10-bit resolution
Note 3
Analog input voltage
VAIN
ANI0 to ANI14
0
ANI16 to ANI20
0
Internal reference voltage
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode)
Temperature sensor output voltage
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode)
VBGR
Note 4
VTMPS25 Note 4
V
V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When the conversion time is set to 57 µs (min.) and 95 µs (max.).
4. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.
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2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
(4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (–) =
AVREFM/ANI1 (ADREFM = 1), target pin : ANI0, ANI2 to ANI14, ANI16 to ANI20
(TA = –40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+)
= VBGR Note 3, Reference voltage (–) = AVREFM = 0 V Note 4, HS (high-speed main) mode)
Parameter
Symbol
Resolution
Conditions
MIN.
RES
Conversion time
Zero-scale error
Notes 1, 2
Integral linearity error
Note 1
Differential linearity error
Note 1
Analog input voltage
TYP.
MAX.
8
tCONV
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
EZS
8-bit resolution
ILE
DLE
Unit
bit
39
µs
2.4 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±2.0
LSB
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±1.0
LSB
VAIN
17
0
VBGR
Note 3
V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.
4. When reference voltage (–) = VSS, the MAX. values are as follows.
Zero-scale error: Add ±0.35%FSR to the MAX. value when reference voltage (–) = AVREFM.
Integral linearity error: Add ±0.5 LSB to the MAX. value when reference voltage (–) = AVREFM.
Differential linearity error: Add ±0.2 LSB to the MAX. value when reference voltage (–) = AVREFM.
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2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
2.6.2 Temperature sensor/internal reference voltage characteristics
(TA = –40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, HS (high-speed main) mode)
Parameter
Symbol
Conditions
Temperature sensor output voltage
VTMPS25
Setting ADS register = 80H, TA = +25°C
Internal reference voltage
VBGR
Setting ADS register = 81H
Temperature coefficient
FVTMPS
Temperature dependence of the temperature
sensor
Operation stabilization wait time
tAMP
MIN.
TYP.
MAX.
1.14
1.38
1.45
Unit
V
1.5
–3.6
V
mV/°C
5
µs
2.6.3 POR circuit characteristics
(TA = –40 to +85°C, VSS = 0 V)
Parameter
Detection voltage
Minimum pulse width
Note
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VPOR
The power supply voltage is rising.
1.47
1.51
1.55
V
VPDR
The power supply voltage is falling.
1.46
1.50
1.54
V
TPW
300
µs
Note Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a
POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main
system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control
register (CSC).
TPW
Supply voltage (VDD)
VPOR
VPDR or 0.7 V
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2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
2.6.4 LVD circuit characteristics
LVD Detection Voltage of Reset Mode and Interrupt Mode
(TA = –40 to +85°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Detection voltage
Symbol
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VLVD8
VLVD9
VLVD10
VLVD11
VLVD12
VLVD13
Minimum pulse width
Detection delay time
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tLW
Conditions
MIN.
TYP.
MAX.
Unit
The power supply voltage is rising.
3.98
4.06
4.14
V
The power supply voltage is falling.
3.90
3.98
4.06
V
The power supply voltage is rising.
3.68
3.75
3.82
V
The power supply voltage is falling.
3.60
3.67
3.74
V
The power supply voltage is rising.
3.07
3.13
3.19
V
The power supply voltage is falling.
3.00
3.06
3.12
V
The power supply voltage is rising.
2.96
3.02
3.08
V
The power supply voltage is falling.
2.90
2.96
3.02
V
The power supply voltage is rising.
2.86
2.92
2.97
V
The power supply voltage is falling.
2.80
2.86
2.91
V
The power supply voltage is rising.
2.76
2.81
2.87
V
The power supply voltage is falling.
2.70
2.75
2.81
V
The power supply voltage is rising.
2.66
2.71
2.76
V
The power supply voltage is falling.
2.60
2.65
2.70
V
The power supply voltage is rising.
2.56
2.61
2.66
V
The power supply voltage is falling.
2.50
2.55
2.60
V
The power supply voltage is rising.
2.45
2.50
2.55
V
The power supply voltage is falling.
2.40
2.45
2.50
V
The power supply voltage is rising.
2.05
2.09
2.13
V
The power supply voltage is falling.
2.00
2.04
2.08
V
The power supply voltage is rising.
1.94
1.98
2.02
V
The power supply voltage is falling.
1.90
1.94
1.98
V
The power supply voltage is rising.
1.84
1.88
1.91
V
The power supply voltage is falling.
1.80
1.84
1.87
V
The power supply voltage is rising.
1.74
1.77
1.81
V
The power supply voltage is falling.
1.70
1.73
1.77
V
The power supply voltage is rising.
1.64
1.67
1.70
V
The power supply voltage is falling.
1.60
1.63
1.66
V
300
µs
300
µs
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2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
LVD Detection Voltage of Interrupt & Reset Mode
(TA = –40 to +85°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Detection voltage
VLVDA0
VLVDA1
VLVDA2
VLVDA3
VLVDB0
VLVDB1
VLVDB2
VLVDB3
VLVDC0
VLVDC1
VLVDC2
VLVDC3
VLVDD0
VLVDD1
VLVDD2
VLVDD3
Conditions
MIN.
TYP.
MAX.
Unit
1.60
1.63
1.66
V
Rising release reset voltage
1.74
1.77
1.81
V
Falling interrupt voltage
1.70
1.73
1.77
V
Rising release reset voltage
1.84
1.88
1.91
V
Falling interrupt voltage
1.80
1.84
1.87
V
Rising release reset voltage
2.86
2.92
2.97
V
Falling interrupt voltage
2.80
2.86
2.91
V
1.80
1.84
1.87
V
Rising release reset voltage
1.94
1.98
2.02
V
Falling interrupt voltage
1.90
1.94
1.98
V
Rising release reset voltage
2.05
2.09
2.13
V
Falling interrupt voltage
2.00
2.04
2.08
V
Rising release reset voltage
3.07
3.13
3.19
V
Falling interrupt voltage
3.00
3.06
3.12
V
2.40
2.45
2.50
V
2.56
2.61
2.66
V
VPOC2, VPOC1, VPOC0 = 0, 0, 0, falling reset voltage
LVIS1, LVIS0 = 1, 0
LVIS1, LVIS0 = 0, 1
LVIS1, LVIS0 = 0, 0
VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage
LVIS1, LVIS0 = 1, 0
LVIS1, LVIS0 = 0, 1
LVIS1, LVIS0 = 0, 0
VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage
LVIS1, LVIS0 = 1, 0
LVIS1, LVIS0 = 0, 1
LVIS1, LVIS0 = 0, 0
Rising release reset voltage
Falling interrupt voltage
2.50
2.55
2.60
V
Rising release reset voltage
2.66
2.71
2.76
V
Falling interrupt voltage
2.60
2.65
2.70
V
Rising release reset voltage
3.68
3.75
3.82
V
Falling interrupt voltage
3.60
3.67
3.74
V
2.70
2.75
2.81
V
Rising release reset voltage
2.86
2.92
2.97
V
Falling interrupt voltage
2.80
2.86
2.91
V
Rising release reset voltage
2.96
3.02
3.08
V
Falling interrupt voltage
2.90
2.96
3.02
V
Rising release reset voltage
3.98
4.06
4.14
V
Falling interrupt voltage
3.90
3.98
4.06
V
MIN.
TYP.
MAX.
Unit
54
V/ms
VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage
LVIS1, LVIS0 = 1, 0
LVIS1, LVIS0 = 0, 1
LVIS1, LVIS0 = 0, 0
2.6.5 Power supply voltage rising slope characteristics
(TA = –40 to +85°C, VSS = 0 V)
Parameter
Power supply voltage rising slope
Caution
Symbol
Conditions
SVDD
Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the
operating voltage range shown in 2.4 AC Characteristics.
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2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
2.7 RAM Data Retention Characteristics
(TA = –40 to +85°C, VSS = 0 V)
Parameter
Symbol
Data retention supply voltage
Conditions
VDDDR
MIN.
TYP.
1.46
Note
MAX.
Unit
5.5
V
Note This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage
reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated.
Operation mode
STOP mode
RAM data retention
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
2.8 Flash Memory Programming Characteristics
(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
CPU/peripheral hardware clock
frequency
fCLK
1.8 V ≤ VDD ≤ 5.5 V
Number of code flash rewrites
Cerwr
Retained for 20 years
TA = 85°C
Notes 1, 2, 3
Number of data flash rewrites
Notes 1, 2, 3
MIN.
TYP.
1
1,000
Retained for 1 years
TA = 25°C
MAX.
Unit
32
MHz
Times
1,000,000
Retained for 5 years
TA = 85°C
100,000
Retained for 20 years
TA = 85°C
10,000
Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite.
The retaining years are until next rewrite after the rewrite.
2. When using flash memory programmer and Renesas Electronics self programming library
3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas
Electronics Corporation.
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2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85C)
2.9 Dedicated Flash Memory Programmer Communication (UART)
(TA = –40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Transfer rate
Conditions
MIN.
During serial programming
TYP.
115,200
MAX.
Unit
1,000,000
bps
2.10 Timing of Entry to Flash Memory Programming Modes
(TA = –40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
100
ms
Time to complete the communication tSUINIT
for the initial setting after the
external reset is released
POR and LVD reset must be released before
the external reset is released.
tSU
Time to release the external reset
after the TOOL0 pin is set to the low
level
POR and LVD reset must be released before
the external reset is released.
10
µs
tHD
POR and LVD reset must be released before
the external reset is released.
1
ms
Time to hold the TOOL0 pin at the
low level after the external reset is
released
(excluding the processing time of
the firmware to control the flash
memory)
RESET
723 µs + tHD
processing
time
1-byte data for setting mode
TOOL0
tSU
tSUINIT
The low level is input to the TOOL0 pin.
The external reset is released (POR and LVD reset must be released before the external
reset is released.).
The TOOL0 pin is set to the high level.
Setting of the flash memory programming mode by UART reception and complete the baud
rate setting.
Remark tSUINIT: Communication for the initial setting must be completed within 100 ms after the external reset is released
during this period.
tSU:
Time to release the external reset after the TOOL0 pin is set to the low level
tHD:
Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing
time of the firmware to control the flash memory)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
3. ELECTRICAL SPECIFICATIONS
(G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
This chapter describes the following electrical specifications.
Target products G:
Industrial applications TA = –40 to +105°C
R5F140xxGxx
Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development
and evaluation. Do not use the on-chip debug function in products designated for mass
production, because the guaranteed number of rewritable times of the flash memory may be
exceeded when this function is used, and product reliability therefore cannot be guaranteed.
Renesas Electronics is not liable for problems occurring when the on-chip debug function is
used.
2. With products not provided with an EVDD0, EVDD1, EVSS0, or EVSS1 pin, replace EVDD0 and EVDD1
with VDD, or replace EVSS0 and EVSS1 with VSS.
3. The pins mounted depend on the product. Refer to 2.1 Port Function to 2.2.1 Functions for each
product in the RL78/G13A User’s Manual.
4. Please contact Renesas Electronics sales office for derating of operation under TA = +85°C to
+105°C. Derating is the systematic reduction of load for the sake of improved reliability.
Remark When RL78/G13A is used in the range of TA = –40 to +85°C, see 2. ELECTRICAL SPECIFICATIONS (TA =
–40 to +85°C).
There are following differences between the products "G: Industrial applications (TA = –40 to +105°C)" and the products
“A: Consumer applications”.
Parameter
Application
A: Consumer applications
Operating ambient temperature
Operating mode
Operating voltage range
TA = -40 to +85°C
HS (high-speed main) mode:
G: Industrial applications
TA = -40 to +105°C
HS (high-speed main) mode only:
2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz
2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
LS (low-speed main) mode:
1.8 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz
LV (low-voltage main) mode:
1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz
Serial array unit
IICA
UART
UART
CSI: fCLK/2 (supporting 16 Mbps), fCLK/4
CSI: fCLK/4
Simplified I2C communication
Simplified I2C communication
Normal mode
Normal mode
Fast mode
Fast mode
Fast mode plus
Voltage detector
Rise detection voltage: 1.67 V to 4.06 V
Rise detection voltage: 2.61 V to 4.06 V
(14 levels)
(8 levels)
Fall detection voltage: 1.63 V to 3.98 V
Fall detection voltage: 2.55 V to 3.98 V
(14 levels)
(8 levels)
(Remark is listed on the next page.)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
Remark The electrical characteristics of the products G: Industrial applications (TA = -40 to +105°C) are different from
those of the products “A: Consumer applications”. For details, refer to 3.1 to 3.10.
3.1 Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25°C) (1/2)
Parameter
Supply voltage
Symbols
Conditions
VDD
REGC pin input voltage
Ratings
Unit
–0.5 to +6.5
V
EVDD0, EVDD1
EVDD0 = EVDD1
–0.5 to +6.5
V
EVSS0, EVSS1
EVSS0 = EVSS1
–0.5 to +0.3
V
VIREGC
REGC
–0.3 to +2.1
V
and –0.3 to VDD +0.3Note 1
Input voltage
VI1
P00 to P06, P10 to P17, P30, P31, P40 to P47,
P50 to P57, P64 to P67, P70 to P77, P80 to P87,
–0.3 to EVDD0 +0.3
and –0.3 to VDD +0.3
V
Note 2
P100 to P102, P110, P111, P120, P140 to P147
VI2
P60 to P63 (N-ch open-drain)
VI3
P20 to P27, P121 to P124, P137, P150 to P156,
–0.3 to +6.5
V
–0.3 to VDD +0.3
V
Note 2
EXCLK, EXCLKS, RESET
Output voltage
VO1
P00 to P06, P10 to P17, P30, P31, P40 to P47,
P50 to P57, P60 to P67, P70 to P77, P80 to P87,
–0.3 to EVDD0 +0.3
and –0.3 to VDD +0.3
V
Note 2
P100 to P102, P110, P111, P120, P130,
P140 to P147
Analog input voltage
VO2
P20 to P27, P150 to P156
VAI1
ANI16 to ANI20
–0.3 to VDD +0.3 Note 2
V
–0.3 to EVDD0 +0.3
V
and –0.3 to AVREF(+) +0.3Notes 2, 3
VAI2
ANI0 to ANI14
–0.3 to VDD +0.3
V
and –0.3 to AVREF(+) +0.3Notes 2, 3
Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). This value regulates the absolute
maximum rating of the REGC pin. Do not use this pin with voltage applied to it.
2.
Must be 6.5 V or lower.
3.
Do not exceed AVREF (+) + 0.3 V in case of A/D conversion target pin.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure that
the absolute maximum ratings are not exceeded.
Remarks 1.
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
2.
AVREF (+) : Positive reference voltage of the A/D converter.
3.
VSS : Reference voltage
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
Absolute Maximum Ratings (TA = 25°C) (2/2)
Parameter
Output current, high
Symbols
IOH1
Conditions
Per pin
P00 to P06, P10 to P17, P30,
Ratings
Unit
–40
mA
–70
mA
–100
mA
–0.5
mA
–2
mA
40
mA
70
mA
100
mA
1
mA
5
mA
–40 to +105
°C
–65 to +150
°C
P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100 to P102,
P110, P111, P120, P130,
P140 to P147
Total of all pins
P00 to P04, P40 to P47, P102,
–170 mA
P120, P130, P140 to P145
P05, P06, P10 to P17, P30, P31,
P50 to P57, P64 to P67,
P70 to P77, P80 to P87,
P100, P101, P110, P111,
P146, P147
IOH2
Per pin
P20 to P27, P150 to P156
Total of all pins
Output current, low
IOL1
Per pin
P00 to P06, P10 to P17,
P30, P31, P40 to P47,
P50 to P57, P60 to P67,
P70 to P77, P80 to P87,
P100 to P102, P110, P111,
P120, P130, P140 to P147
Total of all pins
P00 to P04, P40 to P47, P102,
170 mA
P120, P130, P140 to P145
P05, P06, P10 to P17, P30, P31,
P50 to P57, P60 to P67,
P70 to P77, P80 to P87,
P100, P101, P110, P111,
P146, P147
IOL2
Per pin
P20 to P27, P150 to P156
Total of all pins
Operating ambient
TA
temperature
Storage temperature
In normal operation mode
In flash memory programming mode
Tstg
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure that
the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
3.2 Oscillator Characteristics
3.2.1 X1, XT1 oscillator characteristics
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Resonator
Conditions
MIN.
X1 clock oscillation
Ceramic resonator/
2.7 V ≤ VDD ≤ 5.5 V
1.0
frequency (fX)Note
crystal resonator
2.4 V ≤ VDD < 2.7 V
1.0
XT1 clock oscillation
Crystal resonator
32
TYP.
MAX.
Unit
20.0
MHz
16.0
MHz
35
kHz
32.768
frequency (fX)Note
Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time.
Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator
characteristics.
Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1
clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC)
by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation
stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time
with the resonator to be used.
Remark When using the X1 oscillator and XT1 oscillator, refer to 5.4 System Clock Oscillator in the RL78/G13A User’s
Manual.
3.2.2 On-chip oscillator characteristics
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Oscillators
High-speed on-chip oscillator
Parameters
fIH
Conditions
MIN.
TYP.
MAX.
Unit
1
32
MHz
–1.0
+1.0
%
clock frequency Notes 1, 2
High-speed on-chip oscillator
clock frequency accuracy
Low-speed on-chip oscillator
fIL
15
kHz
clock frequency
Low-speed on-chip oscillator
–15
+15
%
clock frequency accuracy
Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H/010C2H) and bits 0
to 2 of HOCODIV register.
2. This indicates the oscillator characteristics only. Refer to AC Characteristics for instruction execution time.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
3.3 DC Characteristics
3.3.1 Pin characteristics
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/5)
Items
Symbol
Output current,
highNote 1
IOH1
IOH2
Notes 1.
Conditions
MIN.
TYP.
MAX.
Unit
Per pin for P00 to P06, P10 to P17,
P30, P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77, P80 to P87,
P100 to P102, P110, P111, P120, P130,
P140 to P147
2.4 V ≤ EVDD0 ≤ 5.5 V
Total of P00 to P04, P40 to P47, P102,
P120, P130, P140 to P145
(When duty ≤ 70% Note 3)
4.0 V ≤ EVDD0 ≤ 5.5 V
–30.0
mA
2.7 V ≤ EVDD0 < 4.0 V
–10.0
mA
2.4 V ≤ EVDD0 < 2.7 V
–5.0
mA
Total of P05, P06, P10 to P17, P30, P31,
P50 to P57, P64 to P67, P70 to P77,
P80 to P87, P100, P101, P110, P111,
P146, P147
(When duty ≤ 70% Note 3)
4.0 V ≤ EVDD0 ≤ 5.5 V
–30.0
mA
2.7 V ≤ EVDD0 < 4.0 V
–19.0
mA
2.4 V ≤ EVDD0 < 2.7 V
–10.0
mA
Total of all pins
(When duty ≤ 70%Note 3)
2.4 V ≤ EVDD0 ≤ 5.5 V
–60.0
mA
Per pin for P20 to P27, P150 to P156
2.4 V ≤ VDD ≤ 5.5 V
–0.1Note 2
mA
Total of all pins
(When duty ≤ 70%Note 3)
2.4 V ≤ VDD ≤ 5.5 V
–1.5
mA
–3.0
Note 2
mA
Value of current at which the device operation is guaranteed even if the current flows from the EVDD0,
EVDD1, VDD pins to an output pin.
2.
Do not exceed the total current value.
3.
Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the
following expression (when changing the duty factor from 70% to n%).
● Total output current of pins = (IOH × 0.7)/(n × 0.01)
Where n = 80% and IOH = –10.0 mA
Total output current of pins = (–10.0 × 0.7)/(80 × 0.01) –8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Caution P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, and P142 to P144
do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/5)
Items
Symbol
Output current,
lowNote 1
IOL1
Conditions
MIN.
Unit
8.5
Per pin for P60 to P63
15.0 Note 2
mA
4.0 V ≤ EVDD0 ≤ 5.5 V
40.0
mA
2.7 V ≤ EVDD0 < 4.0 V
15.0
mA
2.4 V ≤ EVDD0 < 2.7 V
9.0
mA
4.0 V ≤ EVDD0 ≤ 5.5 V
40.0
mA
2.7 V ≤ EVDD0 < 4.0 V
35.0
mA
2.4 V ≤ EVDD0 < 2.7 V
20.0
mA
80.0
mA
0.4 Note 2
mA
5.0
mA
Total of P05, P06, P10 to P17, P30,
P31, P50 to P57, P60 to P67,
P70 to P77, P80 to P87, P100, P101,
P110, P111, P146, P147
(When duty ≤ 70% Note 3)
Total of all pins
(When duty ≤ 70% Note 3)
Per pin for P20 to P27, P150 to P156
Total of all pins
(When duty ≤ 70%Note 3)
Notes 1.
MAX.
Per pin for P00 to P06, P10 to P17,
P30, P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77, P80 to P87,
P100 to P102, P110, P111, P120,
P130, P140 to P147
Total of P00 to P04, P40 to P47,
P102, P120, P130, P140 to P145
(When duty ≤ 70% Note 3)
IOL2
TYP.
2.4 V ≤ VDD ≤ 5.5 V
Note 2
mA
Value of current at which the device operation is guaranteed even if the current flows from an output pin to
the EVSS0, EVSS1 and VSS pin.
2.
Do not exceed the total current value.
3.
Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the
following expression (when changing the duty factor from 70% to n%).
● Total output current of pins = (IOL × 0.7)/(n × 0.01)
Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (3/5)
Items
Input voltage,
Symbol
VIH1
high
Conditions
MAX.
Unit
0.8EVDD0
EVDD0
V
2.2
EVDD0
V
2.0
EVDD0
V
1.5
EVDD0
V
0.7VDD
VDD
V
0.7EVDD0
6.0
V
0.8VDD
VDD
V
Normal input buffer
0
0.2EVDD0
V
P01, P03, P04, P10, P11,
TTL input buffer
0
0.8
V
P13 to P17, P43, P44, P53 to P55,
4.0 V ≤ EVDD0 ≤ 5.5 V
P80, P81, P142, P143
TTL input buffer
0
0.5
V
0
0.32
V
P00 to P06, P10 to P17, P30, P31,
MIN.
Normal input buffer
TYP.
P40 to P47, P50 to P57, P64 to P67,
P70 to P77, P80 to P87,
P100 to P102, P110, P111, P120,
P140 to P147
VIH2
P01, P03, P04, P10, P11,
TTL input buffer
P13 to P17, P43, P44, P53 to P55,
4.0 V ≤ EVDD0 ≤ 5.5 V
P80, P81, P142, P143
TTL input buffer
3.3 V ≤ EVDD0 < 4.0 V
TTL input buffer
2.4 V ≤ EVDD0 < 3.3 V
VIH3
P20 to P27, P150 to P156
VIH4
P60 to P63
VIH5
P121 to P124, P137, EXCLK, EXCLKS, RESET
Input voltage, low VIL1
P00 to P06, P10 to P17, P30, P31,
P40 to P47, P50 to P57, P64 to P67,
P70 to P77, P80 to P87,
P100 to P102, P110, P111, P120,
P140 to P147
VIL2
3.3 V ≤ EVDD0 < 4.0 V
TTL input buffer
2.4 V ≤ EVDD0 < 3.3 V
VIL3
P20 to P27, P150 to P156
0
0.3VDD
V
VIL4
P60 to P63
0
0.3EVDD0
V
VIL5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0
0.2VDD
V
Caution The maximum value of VIH of pins P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71,
P74, P80 to P82, and P142 to P144 is EVDD0, even in the N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (4/5)
Items
Symbol
Output voltage,
VOH1
high
Conditions
MIN.
P00 to P06, P10 to P17, P30, P31,
4.0 V ≤ EVDD0 ≤ 5.5 V,
P40 to P47, P50 to P57, P64 to P67,
IOH1 = –3.0 mA
P70 to P77, P80 to P87,
2.7 V ≤ EVDD0 ≤ 5.5 V,
P100 to P102, P110, P111, P120,
P130, P140 to P147
IOH1 = –2.0 mA
2.4 V ≤ EVDD0 ≤ 5.5 V,
IOH1 = –1.5 mA
VOH2
P20 to P27, P150 to P156
2.4 V ≤ VDD ≤ 5.5 V,
TYP.
MAX.
EVDD0 –
Unit
V
0.7
EVDD0 –
V
0.6
EVDD0 –
V
0.5
VDD – 0.5
V
IOH2 = –100 µA
Output voltage,
VOL1
low
P00 to P06, P10 to P17, P30, P31,
4.0 V ≤ EVDD0 ≤ 5.5 V,
P40 to P47, P50 to P57, P64 to P67,
IOL1 = 8.5 mA
P70 to P77, P80 to P87,
4.0 V ≤ EVDD0 ≤ 5.5 V,
P100 to P102, P110, P111, P120,
P130, P140 to P147
0.7
V
0.6
V
0.4
V
0.4
V
0.4
V
2.0
V
0.4
V
0.4
V
0.4
V
IOL1 = 3.0 mA
2.7 V ≤ EVDD0 ≤ 5.5 V,
IOL1 = 1.5 mA
2.4 V ≤ EVDD0 ≤ 5.5 V,
IOL1 = 0.6 mA
VOL2
P20 to P27, P150 to P156
2.4 V ≤ VDD ≤ 5.5 V,
IOL2 = 400 µA
VOL3
P60 to P63
4.0 V ≤ EVDD0 ≤ 5.5 V,
IOL3 = 15.0 mA
4.0 V ≤ EVDD0 ≤ 5.5 V,
IOL3 = 5.0 mA
2.7 V ≤ EVDD0 ≤ 5.5 V,
IOL3 = 3.0 mA
2.4 V ≤ EVDD0 ≤ 5.5 V,
IOL3 = 2.0 mA
Caution P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, and P142 to P144
do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (5/5)
Items
Input leakage
Symbol
ILIH1
current, high
Conditions
P00 to P06, P10 to P17,
MIN.
TYP.
MAX.
Unit
VI = EVDD0
1
µA
VI = VDD
1
µA
1
µA
10
µA
VI = EVSS0
–1
µA
VI = VSS
–1
µA
–1
µA
–10
µA
100
kΩ
P30, P31, P40 to P47,
P50 to P57, P60 to P67,
P70 to P77, P80 to P87,
P100 to P102, P110, P111,
P120, P140 to P147
ILIH2
P20 to P27, P137,
P150 to P156, RESET
ILIH3
P121 to P124
VI = VDD
In input port or
(X1, X2, XT1, XT2, EXCLK,
external clock
EXCLKS)
input
In resonator
connection
Input leakage
ILIL1
current, low
P00 to P06, P10 to P17,
P30, P31, P40 to P47,
P50 to P57, P60 to P67,
P70 to P77, P80 to P87,
P100 to P102, P110, P111,
P120, P140 to P147
ILIL2
P20 to P27, P137,
P150 to P156, RESET
ILIL3
P121 to P124
VI = VSS
In input port or
(X1, X2, XT1, XT2, EXCLK,
external clock
EXCLKS)
input
In resonator
connection
On-chip pll-up
RU
resistance
P00 to P06, P10 to P17,
VI = EVSS0, In input port
10
20
P30, P31, P40 to P47,
P50 to P57, P64 to P67,
P70 to P77, P80 to P87,
P100 to P102, P110, P111,
P120, P140 to P147
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
3.3.2 Supply current characteristics
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2)
Parameter Symbol
Supply
current
IDD1
Conditions
Operating
mode
Note 1
HS (highfIH = 32 MHz
speed main)
mode Note 5
Note 3
fIH = 24 MHz Note 3
fIH = 16 MHz
Note 3
HS (high,
fMX = 20 MHz
speed main) VDD = 5.0 V
mode Note 5
fMX = 20 MHzNote 2,
Note 2
VDD = 3.0 V
fMX = 10 MHzNote 2,
VDD = 5.0 V
fMX = 10 MHzNote 2,
VDD = 3.0 V
Subsystem
clock
operation
fSUB = 32.768 kHz
Note 4
TA = –40°C
fSUB = 32.768 kHz
Note 4
TA = +25°C
fSUB = 32.768 kHz
Note 4
TA = +50°C
fSUB = 32.768 kHz
Note 4
TA = +70°C
fSUB = 32.768 kHz
Note 4
TA = +85°C
fSUB = 32.768 kHz
Note 4
TA = +105°C
MIN.
TYP.
MAX.
Unit
Basic
VDD = 5.0 V
operation VDD = 3.0 V
1.5
Normal
VDD = 5.0 V
operation VDD = 3.0 V
3.4
3.4
6.8
mA
Normal
VDD = 5.0 V
operation VDD = 3.0 V
2.7
5.3
mA
2.7
5.3
mA
Normal
VDD = 5.0 V
operation VDD = 3.0 V
2
3.8
mA
2
3.8
mA
Normal
Square wave input
operation Resonator connection
Normal
Square wave input
operation Resonator connection
mA
1.5
mA
6.8
mA
2.2
4.4
mA
2.3
4.5
mA
2.2
4.4
mA
2.3
4.5
mA
Normal
Square wave input
operation Resonator connection
1.2
2.4
mA
1.4
2.6
mA
Normal
Square wave input
operation Resonator connection
1.2
2.4
mA
1.4
2.6
mA
4
5.5
µA
4
5.7
µA
4.2
6.7
µA
4.3
6.9
µA
4.5
9.3
µA
4.7
9.5
µA
5.3
15.8
µA
5.6
16
µA
6.6
25.8
µA
7.1
26
µA
10.6
54.8
µA
11.4
55
µA
Normal
Square wave input
operation
Resonator connection
Normal
Square wave input
operation
Resonator connection
Normal
Square wave input
operation
Resonator connection
Normal
Square wave input
operation
Resonator connection
Normal
Square wave input
operation
Resonator connection
Normal
Square wave input
operation
Resonator connection
(Notes and Remarks are listed on the next page.)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of
the input pin is fixed to VDD, EVDD0, EVDD1 or VSS, EVSS0, EVSS1. The values below the MAX. column include the
peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O
port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite.
2. When high-speed on-chip oscillator and subsystem clock are stopped.
3. When high-speed system clock and subsystem clock are stopped.
4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low
power consumption oscillation). However, not including the current flowing into the RTC, 12-bit interval timer,
and watchdog timer.
5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
Parameter
Symbol
Conditions
Supply
IDD2
HALT
current
Note 2
mode
Note 1
HS (highspeed main)
mode Note 7
HS (highspeed main)
mode Note 7
fIH = 32 MHz Note 4
fIH = 24 MHz
Note 4
fIH = 16 MHz
Note 4
fMX = 20 MHz
VDD = 5.0 V
0.41
1.71
mA
VDD = 3.0 V
0.41
1.71
mA
VDD = 5.0 V
0.34
1.35
mA
VDD = 3.0 V
0.34
1.35
mA
VDD = 5.0 V
0.33
1.04
mA
VDD = 3.0 V
0.33
1.04
mA
0.19
1.05
mA
Resonator connection
0.37
1.26
mA
fMX = 20 MHzNote 3,
Square wave input
0.19
1.05
mA
VDD = 3.0 V
Resonator connection
0.37
1.26
mA
Square wave input
0.12
0.62
mA
Resonator connection
0.22
0.73
mA
Square wave input
0.12
0.62
mA
Resonator connection
0.22
0.73
mA
fMX = 10 MHz
,
Note 3
,
Note 3
VDD = 3.0 V
Subsystem
fSUB = 32.768 kHz
Square wave input
0.39
1
µA
clock
TA = –40°C
Resonator connection
0.48
1.3
µA
fSUB = 32.768 kHzNote 5
Square wave input
0.55
2.2
µA
TA = +25°C
Resonator connection
0.64
2.5
µA
Square wave input
0.98
4.8
µA
Resonator connection
1.07
5.1
µA
Square wave input
1.73
11.3
µA
Resonator connection
1.82
11.6
µA
operation
fSUB = 32.768 kHz
Note 5
Note 5
TA = +50°C
fSUB = 32.768 kHz
Note 5
TA = +70°C
Square wave input
2.73
21.3
µA
TA = +85°C
Resonator connection
2.82
21.6
µA
fSUB = 32.768 kHzNote 5
Square wave input
5.33
50.3
µA
TA = +105°C
Resonator connection
5.42
50.6
µA
fSUB = 32.768 kHz
I
MAX. Unit
Square wave input
Note 3
VDD = 5.0 V
Note 6
DD3
TYP.
VDD = 5.0 V
fMX = 10 MHz
,
MIN.
Note 5
STOP
TA = –40°C
0.26
0.7
µA
modeNote 8
TA = +25°C
0.42
1.9
µA
TA = +50°C
0.85
4.5
µA
TA = +70°C
1.6
11
µA
TA = +85°C
2.6
21
µA
TA = +105°C
5.2
50
µA
(Notes and Remarks are listed on the next page.)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of
the input pin is fixed to VDD, EVDD0, EVDD1 or VSS, EVSS0, EVSS1. The values below the MAX. column include the
peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O
port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator and subsystem clock are stopped.
4. When high-speed system clock and subsystem clock are stopped.
5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting
ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not
including the current flowing into the 12-bit interval timer and watchdog timer.
6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer.
7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
8. Regarding the value for current operate the subsystem clock in STOP mode, refer to that in HALT mode.
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH:
High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
Peripheral Functions (Common to all products)
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Low-speed on-
IFIL
chip oscillator
Note 1
Conditions
MIN.
TYP.
MAX.
Unit
0.2
µA
0.02
µA
0.02
µA
fIL = 15 kHz
0.22
µA
When conversion
Normal mode, AVREFP = VDD = 5.0 V
at maximum speed
Low voltage mode, AVREFP = VDD = 3.0 V
1.3
1.7
mA
0.5
0.7
mA
operating current
RTC operating
IRTC
current
Notes 1, 2, 3
12-bit interval
IIT
timer operating
Notes 1, 2, 4
current
Watchdog timer
IWDT
operating current
Notes 1, 2, 5
A/D converter
operating current
A/D converter
reference
voltage current
Temperature
sensor operating
current
IADC
Notes 1, 6
IADREF
100
µA
100
µA
0.02
µA
Note 1
ITMPS
Note 1
LVD operating
ILVD
current
Notes 1, 7
Self
IFSP
programming
Notes 1, 9
2.5
12.2
mA
2.5
12.2
mA
The mode is performed Note 10
0.5
0.6
mA
The A/D conversion operations are
0.9
1.1
mA
0.5
0.62
mA
operating current
BGO operating
IBGO
current
Notes 1, 8
SNOOZE
ISNOZ
operating
Note 1
ADC operation
current
performed, low-voltage mode, AVREFP = VDD
= 3.0 V
CSI/UART operation
Notes 1. Current flowing to the VDD.
2. When high speed on-chip oscillator and high-speed system clock are stopped.
3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed on-chip
oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of
either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode. When the
low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the
operational current of the real-time clock.
4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip
oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of
either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT mode. When the
low-speed on-chip oscillator is selected, IFIL should be added.
5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator).
The supply current of the RL78 is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer operates.
6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or
IDD2 and IADC when the A/D converter is in operation.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
Notes 7. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2
or IDD3 and ILVD when the LVD circuit is in operation.
8. Current flowing only during data flash rewrite.
9. Current flowing only during self programming.
10. For shift time to the SNOOZE mode, see 18.3.3 SNOOZE mode in the RL78/G13A User’s Manual.
Remarks 1. fIL:
Low-speed on-chip oscillator clock frequency
2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
3. fCLK: CPU/peripheral hardware clock frequency
4. Temperature condition of the TYP. value is TA = 25°C
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3.4 AC Characteristics
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items
Instruction cycle (minimum
instruction execution time)
Symbol
TCY
Conditions
Main
system
clock (fMAIN)
operation
MIN.
TYP.
HS (high-speed 2.7 V ≤ VDD ≤ 5.5 V 0.03125
main) mode
2.4 V ≤ VDD < 2.7 V 0.0625
Subsystem clock (fSUB)
2.4 V ≤ VDD ≤ 5.5 V
28.5
30.5
MAX.
Unit
1
µs
1
µs
31.3
µs
1
µs
1
µs
operation
In the self
HS (high-speed 2.7 V ≤ VDD ≤ 5.5 V 0.03125
programming main) mode
2.4 V ≤ VDD < 2.7 V 0.0625
mode
External system clock frequency
fEX
2.7 V ≤ VDD ≤ 5.5 V
1.0
20.0
MHz
2.4 V ≤ VDD < 2.7 V
1.0
16.0
MHz
32
35
kHz
fEXS
External system clock input highlevel width, low-level width
tEXH, tEXL
2.7 V ≤ VDD ≤ 5.5 V
24
ns
2.4 V ≤ VDD < 2.7 V
30
ns
13.7
µs
1/fMCK+10
nsNote
tEXHS,
tEXLS
TI00 to TI07, TI10 to TI13 input
high-level width, low-level width
tTIH,
tTIL
TO00 to TO07, TO10 to TO13
output frequency
fTO
HS (high-speed
main) mode
HS (high-speed
main) mode
PCLBUZ0, PCLBUZ1 output
frequency
fPCL
Interrupt input high-level width,
low-level width
tINTH,
tINTL
INTP1 to INTP11
Key interrupt input low-level width
tKR
KR0 to KR7
RESET low-level width
tRSL
4.0 V ≤ EVDD0 ≤ 5.5 V
16
MHz
2.7 V ≤ EVDD0 < 4.0 V
8
MHz
2.4 V ≤ EVDD0 < 2.7 V
4
MHz
4.0 V ≤ EVDD0 ≤ 5.5 V
16
MHz
2.7 V ≤ EVDD0 < 4.0 V
8
MHz
4
MHz
2.4 V ≤ EVDD0 < 2.7 V
INTP0
2.4 V ≤ VDD ≤ 5.5 V
1
µs
2.4 V ≤ EVDD0 ≤ 5.5 V
1
µs
2.4 V ≤ EVDD0 ≤ 5.5 V
250
ns
10
µs
Note The following conditions are required for low voltage interface when EVDD0 < VDD
2.4V ≤ EVDD0 < 2.7 V : MIN. 125 ns
Remark fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKSmn0, CKSmn1 bits of timer mode register mn (TMRmn).
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7))
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Minimum Instruction Execution Time during Main System Clock Operation
TCY vs VDD (HS (high-speed main) mode)
10
Cycle time TCY [µs]
1.0
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
0.1
0.0625
0.05
0.03125
0.01
0
1.0
2.0
3.0
4.0
2.4 2.7
Supply voltage V DD [V]
5.0 5.5 6.0
AC Timing Test Points
VIH/VOH
VIL/VOL
Test points
VIH/VOH
VIL/VOL
External System Clock Timing
1/fEX/
1/fEXS
tEXL/
tEXLS
tEXH/
tEXHS
EXCLK/EXCLKS
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
TI/TO Timing
tTIL
tTIH
TI00 to TI07, TI10 to TI13
1/fTO
TO00 to TO07, TO10 to TO13
Interrupt Request Input Timing
tINTL
tINTH
INTP0 to INTP11
Key Interrupt Input Timing
tKR
KR0 to KR7
RESET Input Timing
tRSL
RESET
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
3.5 Peripheral Functions Characteristics
AC Timing Test Points
VIH/VOH
VIH/VOH
Test points
VIL/VOL
VIL/VOL
3.5.1 Serial array unit
(1) During communication at same potential (UART mode)
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
Transfer rate Note 1
Unit
MAX.
fMCK/12 Note 2
bps
2.6
Mbps
Theoretical value of the
maximum transfer rate
fCLK = 32 MHz, fMCK = fCLK
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
2. The following conditions are required for low voltage interface when EVDD0 < VDD.
2.4 V ≤ EVDD0 < 2.7 V : MAX. 1.3 Mbps
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
UART mode connection diagram (during communication at same potential)
TxDq
Rx
User device
RL78 microcontroller
RxDq
Tx
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Remarks 1.
2.
q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
SCKp cycle time
tKCY1
SCKp high-/low-level width
SIp setup time (to SCKp↑)
Note 1
tKCY1 ≥ 4/fCLK
Unit
MAX.
2.7 V ≤ EVDD0 ≤ 5.5 V
250
ns
2.4 V ≤ EVDD0 ≤ 5.5 V
500
ns
tKH1,
4.0 V ≤ EVDD0 ≤ 5.5 V
tKCY1/2 – 24
ns
tKL1
2.7 V ≤ EVDD0 ≤ 5.5 V
tKCY1/2 – 36
ns
2.4 V ≤ EVDD0 ≤ 5.5 V
tKCY1/2 – 76
ns
4.0 V ≤ EVDD0 ≤ 5.5 V
66
ns
2.7 V ≤ EVDD0 ≤ 5.5 V
66
ns
2.4 V ≤ EVDD0 ≤ 5.5 V
113
ns
38
ns
tSIK1
SIp hold time (from SCKp↑) Note 2
tKSI1
Delay time from SCKp↓ to
tKSO1
C = 30 pF Note 4
50
ns
SOp output Note 3
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin
by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM numbers (g = 0, 1, 4, 5, 8, 14)
2.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
SCKp cycle time Note 5
tKCY2
4.0 V ≤ EVDD0 ≤ 5.5 V
2.7 V ≤ EVDD0 ≤ 5.5 V
Unit
MAX.
20 MHz < fMCK
16/fMCK
ns
fMCK ≤ 20 MHz
12/fMCK
ns
16 MHz < fMCK
16/fMCK
ns
fMCK ≤ 16 MHz
12/fMCK
ns
16/fMCK
ns
12/fMCK and 1000
ns
2.4 V ≤ EVDD0 ≤ 5.5 V
SCKp high-/low-level
tKH2,
4.0 V ≤ EVDD0 ≤ 5.5 V
tKCY2/2 – 14
ns
width
tKL2
2.7 V ≤ EVDD0 ≤ 5.5 V
tKCY2/2 – 16
ns
2.4 V ≤ EVDD0 ≤ 5.5 V
tKCY2/2 – 36
ns
SIp setup time
2.7 V ≤ EVDD0 ≤ 5.5 V
1/fMCK+40
ns
2.4 V ≤ EVDD0 ≤ 5.5 V
1/fMCK+60
ns
tKSI2
2.4 V ≤ EVDD0 ≤ 5.5 V
1/fMCK+62
ns
tKSO2
C = 30 pF Note 4
tSIK2
(to SCKp↑) Note 1
SIp hold time
(from SCKp↑) Note 2
Delay time from SCKp↓
to SOp output
Note 3
2.7 V ≤ EVDD0 ≤ 5.5 V
2/fMCK+66
ns
2.4 V ≤ EVDD0 ≤ 5.5 V
2/fMCK+113
ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SOp output lines.
5. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin
by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 4, 5, 8, 14)
2.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
CSI mode connection diagram (during communication at same potential)
SCKp
RL78
microcontroller SIp
SOp
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SO User device
SI
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1, 2
tKL1, 2
tKH1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
Output data
SOp
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1, 2
tKH1, 2
tKL1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Remarks 1.
2.
Output data
p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31)
m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)
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(4) During communication at same potential (simplified I2C mode)
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Unit
Mode
MIN.
SCLr clock frequency
fSCL
2.7 V ≤ EVDD0 ≤ 5.5 V,
MAX.
400 Note1
kHz
100 Note1
kHz
Cb = 50 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
Hold time when SCLr = “L”
tLOW
2.7 V ≤ EVDD0 ≤ 5.5 V,
1200
ns
4600
ns
1200
ns
4600
ns
1/fMCK + 220
ns
Cb = 50 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
Hold time when SCLr = “H”
tHIGH
2.7 V ≤ EVDD0 ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
Data setup time (reception)
tSU:DAT
2.7 V ≤ EVDD0 ≤ 5.5 V,
Cb = 50 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
Data hold time (transmission)
tHD:DAT
2.7 V ≤ EVDD0 ≤ 5.5 V,
Note2
1/fMCK + 580
ns
Note2
0
770
ns
0
1420
ns
Cb = 50 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
Notes 1. The value must also be equal to or less than fMCK/4.
2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H".
Caution
Select the normal input buffer and the N-ch open drain output (VDD tolerance (for the 44- and 48-pin
products)/EVDD tolerance (for the 64- and 100-pin products)) mode for the SDAr pin and the normal
output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register
h (POMh).
(Remarks are listed on the next page.)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
Simplified I2C mode mode connection diagram (during communication at same potential)
VDD
Rb
SDAr
SDA
User device
RL78 microcontroller
SCLr
SCL
Simplified I2C mode serial transfer timing (during communication at same potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD:DAT
tSU:DAT
Remarks 1. Rb[Ω]:Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load
capacitance
2. r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM number (g = 0, 1, 4, 5, 8, 14),
h: POM number (g = 0, 1, 4, 5, 7 to 9, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2)
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
Transfer rate
Reception
Unit
MAX.
fMCK/12 Note 1
bps
2.6
Mbps
fMCK/12 Note 1
bps
2.6
Mbps
2.4 V ≤ EVDD0 < 3.3 V,
fMCK/12
bps
1.6 V ≤ Vb ≤ 2.0 V
Notes 1,2
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
Theoretical value of the
maximum transfer rate
fCLK = 32 MHz, fMCK = fCLK
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
Theoretical value of the
maximum transfer rate
fCLK = 32 MHz, fMCK = fCLK
Theoretical value of the
2.6
Mbps
maximum transfer rate
fCLK = 32 MHz, fMCK = fCLK
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
2. The following conditions are required for low voltage interface when EVDD0 < VDD.
2.4 V ≤ EVDD0 < 2.7 V : MAX. 1.3 Mbps
Caution
Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (for the 44
and 48-pin products)/EVDD tolerance (for the 64- and 100-pin products)) mode for the TxDq pin by using
port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC
characteristics with TTL input buffer selected.
Remarks 1.
2.
3.
Vb[V]: Communication line voltage
q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13)
4.
UART2 cannot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redirection register
(PIOR) is 1.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2)
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
Transfer rate
MAX.
Note 1
bps
2.6 Note 2
Mbps
Note 3
bps
1.2 Note 4
Mbps
Note 5
bps
Theoretical value of the
0.43
Mbps
maximum transfer rate
Note 6
Transmission 4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
Unit
Theoretical value of the
maximum transfer rate
Cb = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
Theoretical value of the
maximum transfer rate
Cb = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V
2.4 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Cb = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V
Notes 1.
The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 4.0 V ≤ EVDD0 ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V
1
Maximum transfer rate =
{–Cb × Rb × ln (1 –
Baud rate error (theoretical value) =
2.2
Vb )} × 3
[bps]
2.2
1
Transfer rate × 2 – {–Cb × Rb × ln (1 – Vb )}
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
3.
The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ EVDD0 < 4.0 V and 2.4 V ≤ Vb ≤ 2.7 V
1
Maximum transfer rate =
{–Cb × Rb × ln (1 –
Baud rate error (theoretical value) =
2.0
Vb )} × 3
[bps]
2.0
1
Transfer rate × 2 – {–Cb × Rb × ln (1 – Vb )}
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
4.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
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Notes 5.
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 2.4 V ≤ EVDD0 < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V
1
Maximum transfer rate =
{–Cb × Rb × ln (1 –
Baud rate error (theoretical value) =
1.5
Vb )} × 3
[bps]
1.5
1
Transfer rate × 2 – {–Cb × Rb × ln (1 – Vb )}
1
( Transfer rate ) × Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
6.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (for the 44and 48-pin products)/EVDD tolerance (for the 64- and 100-pin products)) mode for the TxDq pin by using
port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC
characteristics with TTL input buffer selected.
UART mode connection diagram (during communication at different potential)
Vb
Rb
TxDq
Rx
User device
RL78 microcontroller
RxDq
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Tx
105
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Remarks 1.
Rb[Ω]:Communication line (TxDq) pull-up resistance,
Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
2.
q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13))
4. UART2 cannot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redirection register
(PIOR) is 1.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output) (1/3)
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
SCKp cycle time
tKCY1
tKCY1 ≥ 4/fCLK
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Unit
MAX.
600
ns
1000
ns
2300
ns
tKCY1/2 – 150
ns
tKCY1/2 – 340
ns
tKCY1/2 – 916
ns
tKCY1/2 – 24
ns
tKCY1/2 – 36
ns
tKCY1/2 – 100
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SCKp high-level width
tKH1
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SCKp low-level width
tKL1
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (for the 44- and
48-pin products)/EVDD tolerance (for the 64- and 100-pin products)) mode for the SOp pin and SCKp pin
by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see
the DC characteristics with TTL input buffer selected.
(Remarks are listed two pages after the next page.)
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(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output) (2/3)
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
SIp setup time
(to SCKp↑) Note
tSIK1
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Unit
MAX.
162
ns
354
ns
958
ns
38
ns
38
ns
38
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SIp hold time
(from SCKp↑) Note
tKSI1
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 2.7 kΩ
Delay time from SCKp↓ to
SOp output Note
tKSO1
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
200
ns
390
ns
966
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Note
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (for the 44- and
48-pin products)/EVDD tolerance (for the 64- and 100-pin products)) mode for the SOp pin and SCKp pin
by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see
the DC characteristics with TTL input buffer selected.
(Remarks are listed on the page after the next page.)
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(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output) (3/3)
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
SIp setup time
(to SCKp↓) Note
tSIK1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Unit
MAX.
88
ns
88
ns
220
ns
38
ns
38
ns
38
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SIp hold time
(from SCKp↓) Note
tKSI1
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Delay time from SCKp↑ to
SOp output Note
tKSO1
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
50
ns
50
ns
50
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Note
When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (for the 44- and
48-pin products)/EVDD tolerance (for the 64- and 100-pin products)) mode for the SOp pin and SCKp pin
by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see
the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
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CSI mode connection diagram (during communication at different potential)
Vb
Vb
Rb
SCKp
RL78
SIp
microcontroller
SOp
Rb
SCK
SO
User device
SI
Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load
capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number , n: Channel number (mn = 00, 01, 02, 10, 12,
13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00))
4. CSI01 of 48- and 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use
other CSI for communication at different potential.
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CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
Output data
SOp
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1
tKH1
tKL1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
Output data
Remarks 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 00, 01, 02, 10, 12, 13), n: Channel number
(n = 0, 2), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
2. CSI01 of 48- and 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use
other CSI for communication at different potential.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
MIN.
SCKp cycle time Note 1
SCKp high-/low-level width
tKCY2
Unit
MAX.
4.0 V ≤ EVDD0 ≤ 5.5 V, 24 MHz < fMCK
28/fMCK
ns
2.7 V ≤ Vb ≤ 4.0 V
20 MHz < fMCK ≤ 24 MHz
24/fMCK
ns
8 MHz < fMCK ≤ 20 MHz
20/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK
ns
fMCK ≤ 4 MHz
12/fMCK
ns
2.7 V ≤ EVDD0 < 4.0 V, 24 MHz < fMCK
40/fMCK
ns
2.3 V ≤ Vb ≤ 2.7 V
32/fMCK
ns
16 MHz < fMCK ≤ 20 MHz
28/fMCK
ns
8 MHz < fMCK ≤ 16 MHz
24/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK
ns
fMCK ≤ 4 MHz
12/fMCK
ns
2.4 V ≤ EVDD0 < 3.3 V, 24 MHz < fMCK
96/fMCK
ns
1.6 V ≤ Vb ≤ 2.0 V
20 MHz < fMCK ≤ 24 MHz
72/fMCK
ns
16 MHz < fMCK ≤ 20 MHz
64/fMCK
ns
8 MHz < fMCK ≤ 16 MHz
52/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
32/fMCK
ns
fMCK ≤ 4 MHz
20/fMCK
ns
tKCY2/2 – 24
ns
tKCY2/2 – 36
ns
tKCY2/2 – 100
ns
1/fMCK + 40
ns
1/fMCK + 40
ns
1/fMCK + 60
ns
1/fMCK + 62
ns
20 MHz < fMCK ≤ 24 MHz
tKH2,
4.0 V ≤ EVDD0 ≤ 5.5 V,
tKL2
2.7 V ≤ Vb ≤ 4.0 V
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
2.4 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Note 2
SIp setup time
tSIK2
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
(to SCKp↑) Note2
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
2.4 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
SIp hold time
tKSI2
(from SCKp↑) Note 3
Delay time from SCKp↓ to
tKSO2
SOp output Note 4
4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
2/fMCK + 240
ns
2/fMCK + 428
ns
2/fMCK + 1146
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Cb = 30 pF, Rb = 5.5 kΩ
(Notes, Caution and Remarks are listed on the next page.)
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Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution
Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance
(for the 44- and 48-pin products)/EVDD tolerance (for the 64- and 100-pin products)) mode for the SOp
pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL,
see the DC characteristics with TTL input buffer selected.
CSI mode connection diagram (during communication at different potential)
Vb
Rb
SCKp
RL78
microcontroller SIp
SOp
SCK
SO
User device
SI
Remarks 1. Rb[Ω]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance,
Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 00, 01, 02,
10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13))
4. CSI01 of 48- and 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use
other CSI for communication at different potential.
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CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY2
tKL2
tKH2
SCKp
tSIK2
SIp
tKSI2
Input data
tKSO2
Output data
SOp
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY2
tKH2
tKL2
SCKp
tSIK2
SIp
tKSI2
Input data
tKSO2
SOp
Output data
Remarks 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number,
n: Channel number (mn = 00, 01, 02, 10, 12. 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
2. CSI01 of 48- and 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use
other CSI for communication at different potential.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (1/2)
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Unit
Mode
MIN.
SCLr clock frequency
fSCL
4.0 V ≤ EVDD0 ≤ 5.5 V,
MAX.
400 Note 1
kHz
400 Note 1
kHz
100 Note 1
kHz
100 Note 1
kHz
100 Note 1
kHz
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
Hold time when SCLr = “L”
tLOW
4.0 V ≤ EVDD0 ≤ 5.5 V,
1200
ns
1200
ns
4600
ns
4600
ns
4650
ns
620
ns
500
ns
2700
ns
2400
ns
1830
ns
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
Hold time when SCLr = “H”
tHIGH
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
2.4 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
(Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.)
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(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2)
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Mode
MIN.
Data setup time (reception)
Data hold time (transmission)
tSU:DAT
tHD:DAT
Unit
MAX.
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK + 340
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
1/fMCK + 340
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
1/fMCK + 760
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1/fMCK + 760
2.4 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
1/fMCK + 570
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 50 pF, Rb = 2.7 kΩ
0
770
ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 50 pF, Rb = 2.7 kΩ
0
770
ns
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
0
1420
ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
0
1420
ns
2.4 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
0
1215
ns
ns
Note 2
ns
Note 2
ns
Note 2
ns
Note 2
ns
Note 2
Notes 1. The value must also be equal to or less than fMCK/4.
2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H".
Caution
Select the TTL input buffer and the N-ch open drain output (VDD tolerance (for the 44- and 48-pin
products)/EVDD tolerance (for the 64- and 100-pin products)) mode for the SDAr pin and the N-ch open
drain output (VDD tolerance (for the 44- and 48-pin products)/EVDD tolerance (for the 64- and 100-pin
products)) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode
register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
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Simplified I2C mode connection diagram (during communication at different potential)
Vb
Vb
Rb
Rb
SDAr
SDA
RL78
microcontroller
User device
SCLr
SCL
Simplified I2C mode serial transfer timing (during communication at different potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD:DAT
tSU:DAT
Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance (for the 44- and 48-pin
products)/EVDD tolerance (for the 64- and 100-pin products)) mode for the SDAr pin and the N-ch open
drain output (VDD tolerance (for the 44- and 48-pin products)/EVDD tolerance (for the 64- and 100-pin
products)) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode
register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
Remarks 1. Rb[Ω]:Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load
capacitance, Vb[V]: Communication line voltage
2. r: IIC number (r = 00, 01, 10, 20, 30, 31), g: PIM, POM number (g = 0, 1, 4, 5, 8, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01, 02, 10, 12, 13)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
3.5.2 Serial interface IICA
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
Standard Mode
SCLA0 clock frequency
fSCL
Setup time of restart condition
Hold time
Unit
Fast Mode
MIN.
MAX.
MIN.
MAX.
Fast mode: fCLK ≥ 3.5 MHz
–
–
0
400
kHz
Standard mode: fCLK ≥ 1 MHz
0
100
–
–
kHz
tSU:STA
4.7
0.6
µs
tHD:STA
4.0
0.6
µs
Hold time when SCLA0 = “L”
tLOW
4.7
1.3
µs
Hold time when SCLA0 = “H”
tHIGH
4.0
0.6
µs
tSU:DAT
250
100
ns
tHD:DAT
0
Setup time of stop condition
tSU:STO
4.0
0.6
µs
Bus-free time
tBUF
4.7
1.3
µs
Note 1
Data setup time (reception)
Data hold time (transmission)
Notes 1.
2.
Note 2
3.45
0
0.9
µs
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection
register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in
the redirect destination.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 kΩ
Fast mode:
Cb = 320 pF, Rb = 1.1 kΩ
IICA serial transfer timing
tLOW
tR
SCLAn
tHD:DAT
tHD:STA
tHIGH
tF
tSU:STA
tHD:STA
tSU:STO
tSU:DAT
SDAAn
tBUF
Stop
condition
Start
condition
Restart
condition
Stop
condition
Remark n = 0, 1
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3.6 Analog Characteristics
3.6.1 A/D converter characteristics
Classification of A/D converter characteristics
Reference Voltage
Reference voltage (+) = AVREFP
Reference voltage (+) = VDD
Reference voltage (+) = VBGR
Input channel
Reference voltage (–) = AVREFM
Reference voltage (–) = VSS
Reference voltage (–) = AVREFM
ANI0 to ANI14
Refer to 3.6.1 (1).
Refer to 3.6.1 (3).
Refer to 3.6.1 (4).
ANI16 to ANI20
Refer to 3.6.1 (2).
Internal reference voltage
Refer to 3.6.1 (1).
–
Temperature sensor output
voltage
(1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (–) = AVREFM/ANI1
(ADREFM = 1), target pin : ANI2 to ANI14, internal reference voltage, and temperature sensor output voltage
(TA = –40 to +105°C, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (–) =
AVREFM = 0 V)
Parameter
Resolution
Symbol
Conditions
RES
Overall error
Note 1
AINL
MIN.
TYP.
8
10-bit resolution
2.4 V ≤ AVREFP ≤ 5.5 V
1.2
MAX.
Unit
10
bit
±3.5
LSB
AVREFP = VDD Note 3
Conversion time
tCONV
10-bit resolution
3.6 V ≤ VDD ≤ 5.5 V
2.125
39
µs
Target pin: ANI2 to ANI14
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
µs
2.4 V ≤ VDD ≤ 5.5 V
17
39
µs
10-bit resolution
3.6 V ≤ VDD ≤ 5.5 V
2.375
39
µs
Target pin: Internal reference
2.7 V ≤ VDD ≤ 5.5 V
3.5625
39
µs
2.4 V ≤ VDD ≤ 5.5 V
17
39
µs
voltage, and temperature
sensor output voltage (HS
(high-speed main) mode)
Zero-scale errorNotes 1, 2
EZS
10-bit resolution
AVREFP = VDD Note 3
2.4 V ≤ AVREFP ≤ 5.5 V
±0.25
%FSR
Full-scale errorNotes 1, 2
EFS
10-bit resolution
AVREFP = VDD Note 3
2.4 V ≤ AVREFP ≤ 5.5 V
±0.25
%FSR
Integral linearity error
ILE
10-bit resolution
2.4 V ≤ AVREFP ≤ 5.5 V
±2.5
LSB
2.4 V ≤ AVREFP ≤ 5.5 V
±1.5
LSB
AVREFP
V
AVREFP = VDD Note 3
Note 1
Differential linearity error
DLE
Analog input voltage
10-bit resolution
AVREFP = VDD Note 3
Note 1
VAIN
ANI2 to ANI14
Internal reference voltage output
0
VBGR
Note 4
V
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode)
Temperature sensor output voltage
VTMPS25 Note 4
V
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode)
(Notes are listed on the next page.)
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Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD.
4. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics.
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(2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (–) = AVREFM/ANI1
(ADREFM = 1), target pin : ANI16 to ANI20
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V,
Reference voltage (+) = AVREFP, Reference voltage (–) = AVREFM = 0 V)
Parameter
Symbol
Resolution
RES
Overall errorNote 1
AINL
Conditions
MIN.
TYP.
8
10-bit resolution
2.4 V ≤ AVREFP ≤ 5.5 V
1.2
MAX.
Unit
10
bit
±5.0
LSB
EVDD0 ≤ AVREFP = VDD Notes 3, 4
Conversion time
tCONV
10-bit resolution
3.6 V ≤ VDD ≤ 5.5 V
2.125
39
µs
Target pin : ANI16 to ANI20
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
µs
2.4 V ≤ VDD ≤ 5.5 V
17
39
µs
Zero-scale error
EZS
10-bit resolution
EVDD0 ≤ AVREFP = VDD Notes 3, 4
Full-scale errorNotes 1, 2
EFS
10-bit resolution
EVDD0 ≤ AVREFP = VDD Notes 3, 4
2.4 V ≤ AVREFP ≤ 5.5 V
±0.35
%FSR
Integral linearity errorNote 1
ILE
10-bit resolution
2.4 V ≤ AVREFP ≤ 5.5 V
±3.5
LSB
2.4 V ≤ AVREFP ≤ 5.5 V
±2.0
LSB
AVREFP
V
Notes 1, 2
2.4 V ≤ AVREFP ≤ 5.5 V
±0.35
%FSR
EVDD0 ≤ AVREFP = VDD Notes 3, 4
Differential linearity error
DLE
10-bit resolution
EVDD0 ≤ AVREFP = VDD Notes 3, 4
Note 1
Analog input voltage
VAIN
ANI16 to ANI20
0
and EVDD0
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD.
4. When AVREFP < EVDD0 ≤ VDD, the MAX. values are as follows.
Overall error: Add ±4.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.20%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±2.0 LSB to the MAX. value when AVREFP = VDD.
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(3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (–) = VSS (ADREFM = 0),
target pin : ANI0 to ANI14, ANI16 to ANI20, internal reference voltage, and temperature sensor output voltage
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VDD,
Reference voltage (–) = VSS)
Parameter
Symbol
Resolution
RES
Overall errorNote 1
AINL
Conversion time
tCONV
Conditions
MIN.
TYP.
8
Unit
10
bit
±7.0
LSB
10-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
10-bit resolution
3.6 V ≤ VDD ≤ 5.5 V
2.125
39
µs
Target pin: ANI0 to ANI14,
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
µs
2.4 V ≤ VDD ≤ 5.5 V
17
39
µs
10-bit resolution
3.6 V ≤ VDD ≤ 5.5 V
2.375
39
µs
Target pin: Internal reference
2.7 V ≤ VDD ≤ 5.5 V
3.5625
39
µs
2.4 V ≤ VDD ≤ 5.5 V
17
39
µs
ANI16 to ANI20
voltage, and temperature
sensor output voltage (HS
1.2
MAX.
(high-speed main) mode)
EZS
10-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
Full-scale error
EFS
10-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
Integral linearity errorNote 1
ILE
10-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±4.0
LSB
Differential linearity error
DLE
10-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±2.0
LSB
VAIN
ANI0 to ANI14
0
VDD
V
ANI16 to ANI20
0
EVDD0
V
Zero-scale error
Notes 1, 2
Notes 1, 2
Note 1
Analog input voltage
Internal reference voltage output
VBGR
Note 3
V
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode)
Temperature sensor output voltage
VTMPS25 Note 3
V
(2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode)
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics.
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(4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (–) =
AVREFM/ANI1 (ADREFM = 1), target pin : ANI0, ANI2 to ANI14, ANI16 to ANI20
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VBGR Note 3,
Reference voltage (–) = AVREFM Note 4 = 0 V, HS (high-speed main) mode)
Parameter
Symbol
Resolution
Conditions
MIN.
RES
Conversion time
Zero-scale error
Notes 1, 2
Integral linearity error
Note 1
Differential linearity error
Note 1
Analog input voltage
TYP.
MAX.
8
tCONV
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
EZS
8-bit resolution
ILE
DLE
Unit
bit
39
µs
2.4 V ≤ VDD ≤ 5.5 V
±0.60
%FSR
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±2.0
LSB
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
±1.0
LSB
VAIN
17
0
VBGR
Note 3
V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics.
4. When reference voltage (–) = VSS, the MAX. values are as follows.
Zero-scale error: Add ±0.35%FSR to the MAX. value when reference voltage (–) = AVREFM.
Integral linearity error: Add ±0.5 LSB to the MAX. value when reference voltage (–) = AVREFM.
Differential linearity error: Add ±0.2 LSB to the MAX. value when reference voltage (–) = AVREFM.
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3.6.2 Temperature sensor/internal reference voltage characteristics
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, HS (high-speed main) mode)
Parameter
Symbol
Conditions
MIN.
Temperature sensor output voltage
VTMPS25
Setting ADS register = 80H, TA = +25°C
Internal reference voltage
VBGR
Setting ADS register = 81H
Temperature coefficient
FVTMPS
TYP.
MAX.
1.14
1.38
Temperature dependence of the temperature
1.45
Unit
V
1.5
–3.6
V
mV/°C
sensor
Operation stabilization wait time
tAMP
5
µs
3.6.3 POR circuit characteristics
(TA = –40 to +105°C, VSS = 0 V)
Parameter
Detection voltage
Minimum pulse width
Note
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VPOR
The power supply voltage is rising.
1.45
1.51
1.57
V
VPDR
The power supply voltage is falling.
1.44
1.50
1.56
V
TPW
300
µs
Note Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a
POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main
system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control
register (CSC).
TPW
Supply voltage (VDD)
VPOR
VPDR or 0.7 V
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3.6.4 LVD circuit characteristics
LVD Detection Voltage of Reset Mode and Interrupt Mode
(TA = –40 to +105°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Detection voltage
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Minimum pulse width
Conditions
MIN.
TYP.
MAX.
Unit
The power supply voltage is rising.
3.90
4.06
4.22
V
The power supply voltage is falling.
3.83
3.98
4.13
V
The power supply voltage is rising.
3.60
3.75
3.90
V
The power supply voltage is falling.
3.53
3.67
3.81
V
The power supply voltage is rising.
3.01
3.13
3.25
V
The power supply voltage is falling.
2.94
3.06
3.18
V
The power supply voltage is rising.
2.90
3.02
3.14
V
The power supply voltage is falling.
2.85
2.96
3.07
V
The power supply voltage is rising.
2.81
2.92
3.03
V
The power supply voltage is falling.
2.75
2.86
2.97
V
The power supply voltage is rising.
2.70
2.81
2.92
V
The power supply voltage is falling.
2.64
2.75
2.86
V
The power supply voltage is rising.
2.61
2.71
2.81
V
The power supply voltage is falling.
2.55
2.65
2.75
V
The power supply voltage is rising.
2.51
2.61
2.71
V
The power supply voltage is falling.
2.45
2.55
2.65
tLW
300
V
µs
Detection delay time
300
µs
LVD Detection Voltage of Interrupt & Reset Mode
(TA = –40 to +105°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Detection voltage
Symbol
VLVDD0
Conditions
MIN.
TYP.
MAX.
Unit
2.64
2.75
2.86
V
Rising release reset voltage
2.81
2.92
3.03
V
Falling interrupt voltage
2.75
2.86
2.97
V
Rising release reset voltage
2.90
3.02
3.14
V
Falling interrupt voltage
2.85
2.96
3.07
V
Rising release reset voltage
3.90
4.06
4.22
V
Falling interrupt voltage
3.83
3.98
4.13
V
MIN.
TYP.
MAX.
Unit
54
V/ms
VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage
VLVDD1
VLVDD2
VLVDD3
LVIS1, LVIS0 = 1, 0
LVIS1, LVIS0 = 0, 1
LVIS1, LVIS0 = 0, 0
3.6.5 Power supply voltage rising slope characteristics
(TA = –40 to +105°C, VSS = 0 V)
Parameter
Power supply voltage rising slope
Caution
Symbol
Conditions
SVDD
Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the
operating voltage range shown in 3.4 AC Characteristics.
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3.7 RAM Data Retention Characteristics
(TA = –40 to +105°C, VSS = 0 V)
Parameter
Data retention supply voltage
Symbol
Conditions
VDDDR
MIN.
1.44
TYP.
Note
MAX.
Unit
5.5
V
Note This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage
reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated.
Operation mode
STOP mode
RAM data retention
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
3.8 Flash Memory Programming Characteristics
(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
CPU/peripheral hardware clock
Symbol
Conditions
fCLK
2.4 V ≤ VDD ≤ 5.5 V
Cerwr
Retained for 20 years
MIN.
TYP.
1
MAX.
Unit
32
MHz
frequency
Number of code flash rewrites
Notes 1, 2, 3
TA = 85°C Note 4
Number of data flash rewrites
Retained for 1 years
Notes 1, 2, 3
TA = 25°C
Retained for 5 years
1,000
Times
1,000,000
100,000
TA = 85°C Note 4
Retained for 20 years
10,000
TA = 85°C Note 4
Notes 1.
2.
3.
4.
1 erase + 1 write after the erase is regarded as 1 rewrite.The retaining years are until next rewrite after the
rewrite.
When using flash memory programmer and Renesas Electronics self programming library.
These are the characteristics of the flash memory and the results obtained from reliability testing by
Renesas Electronics Corporation.
This temperature is the average value at which data are retained.
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3.9 Dedicated Flash Memory Programmer Communication (UART)
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Transfer rate
Conditions
MIN.
During serial programming
TYP.
115,200
MAX.
Unit
1,000,000
bps
3.10 Timing of Entry to Flash Memory Programming Modes
(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
MIN.
Time to complete the communication tSUINIT
POR and LVD reset must be released before
for the initial setting after the
the external reset is released.
TYP.
MAX.
Unit
100
ms
external reset is released
Time to release the external reset
tSU
after the TOOL0 pin is set to the low
POR and LVD reset must be released before
10
µs
1
ms
the external reset is released.
level
Time to hold the TOOL0 pin at the
tHD
low level after the external reset is
POR and LVD reset must be released before
the external reset is released.
released
(excluding the processing time of the
firmware to control the flash
memory)
RESET
723 µs + tHD
processing
time
1-byte data for setting mode
TOOL0
tSU
tSUINIT
The low level is input to the TOOL0 pin.
The external reset is released (POR and LVD reset must be released before the external
reset is released.).
The TOOL0 pin is set to the high level.
Setting of the flash memory programming mode by UART reception and complete the baud
rate setting.
Remark tSUINIT: Communication for the initial setting must be completed within 100 ms after the external reset is released
during this period.
tSU:
Time to release the external reset after the TOOL0 pin is set to the low level
tHD:
Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing
time of the firmware to control the flash memory)
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4. PACKAGE DRAWINGS
4. PACKAGE DRAWINGS
4.1 44-pin Products
R5F140FKAFP, R5F140FLAFP
R5F140FKGFP, R5F140FLGFP
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4. PACKAGE DRAWINGS
4.2 48-pin Products
R5F140GKAFB, R5F140GLAFB
R5F140GKGFB, R5F140GLGFB
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4. PACKAGE DRAWINGS
4.3 64-pin Products
R5F140LKAFB, R5F140LLAFB
R5F140LKGFB, R5F140LLGFB
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4. PACKAGE DRAWINGS
4.4 100-pin Products
R5F140PKAFB, R5F140PLAFB
R5F140PKGFB, R5F140PLGFB
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Revision History
RL78/G13A Datasheet
Rev.
Date
Page
1.00
1.10
Mar 06, 2020
Sep 18, 2020
18
79
Description
Summary
First edition issued
Deletion of “(TARGET)” from the title of chapter 2 ELECTRICAL
SPECIFICATIONS (TA = –40 to +85°C)
Deletion of “(TARGET)” from the title of chapter 3 ELECTRICAL
SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C)
All trademarks and registered trademarks are the property of their respective owners.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United
States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
C-1
General Precautions in the Handling of Microprocessing Unit and Microcontroller
Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the
products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
1.
Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps
must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be
adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.
Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor
2.
devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.
Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of
register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset
pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins
in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the
3.
level at which resetting is specified.
Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal
4.
elements. Follow the guideline for input signal during power-off state as described in your product documentation.
Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are
generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of
the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
5.
become possible.
Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program
execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator
during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal
6.
produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the
7.
input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.).
Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these
8.
addresses as the correct operation of the LSI is not guaranteed.
Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.
The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms
of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,
operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a systemevaluation test for the given product.
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by
you or third parties arising from the use of these circuits, software, or information.
2.
Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or
arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application
examples.
3.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.
4.
You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by
5.
Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the
you or third parties arising from such alteration, modification, copying or reverse engineering.
product’s quality grade, as indicated below.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; industrial robots; etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc.
Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are
not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause
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liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or
other Renesas Electronics document.
6.
When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for Handling and Using Semiconductor Devices” in the
reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation
characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such specified
ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a
certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas
Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury
or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult
and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. You are responsible for carefully and
sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics
products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable
laws and regulations.
9.
Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws
or regulations. You shall comply with any applicable export control laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or
transactions.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or transfers the product to a third party, to notify such third
party in advance of the contents and conditions set forth in this document.
11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products.
(Note 1)
“Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries.
(Note 2)
“Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
(Rev.4.0-1 November 2017)
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