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Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
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Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1.
2.
3.
4.
5.
6.
7.
All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
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“Standard”:
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9.
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12.
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
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R8C/11 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0034-0160
Rev.1.60
Jan 27, 2006
1. Overview
This MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU
core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions
featuring a high level of instruction efficiency. With 1M bytes of address space, it is capable of executing
instructions at high speed.
1.1 Applications
Electric household appliance, office equipment, housing equipment (sensor, security), general industrial
equipment, audio, etc.
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
page 1 of 26
R8C/11 Group
1. Overview
1.2 Performance Overview
Table 1.1. lists the performance outline of this MCU.
Table 1.1 Performance outline
Item
Performance
CPU
Number of basic instructions 89 instructions
Minimum instruction execution time 50 ns (f(XIN) = 20 MHZ, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHZ, VCC = 2.7 to 5.5 V)
Operating mode
Single-chip
Address space
1M bytes
Memory capacity
See Table 1.2.
Peripheral
Port
Input/Output: 22 (including LED drive port), Input: 2
function
LED drive port
I/O port: 8
Timer
Timer X: 8 bits x 1 channel, Timer Y: 8 bits x 1 channel,
Timer Z: 8 bits x 1 channel
(Each timer equipped with 8-bit prescaler)
Timer C: 16 bits x 1 channel
(Circuits of input capture and output compare)
Serial Interface
•1 channel
Clock synchronous, UART
•1 channel
UART
A/D converter
10-bit A/D converter: 1 circuit, 12 channels
Watchdog timer
15 bits x 1 (with prescaler)
Interrupt
Internal: 11 factors, External: 5 factors,
Software: 4 factors, Priority level: 7 levels
Clock generation circuit
2 circuits
•Main clock generation circuit (Equipped with a built-in
feedback resistor)
•On-chip oscillator (high speed, low speed)
On High-speed on-chip oscillator the frequency adjustment function is usable.
Oscillation stop detection function Main clock oscillation stop detection function
Voltage detection circuit
Included
Power on reset circuit
Included
Electrical
Supply voltage
VCC = 3.0 to 5.5 V (f(XIN) = 20 MHZ)
characteristics
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHZ)
Power consumption
Typ. 9 mA (VCC = 5.0 V, (f(XIN) = 20 MHZ)
Typ. 5 mA (VCC = 3.0 V, (f(XIN) = 10 MHZ)
Typ. 35 µA (VCC = 3.0 V, Wait mode, Peripheral clock off)
Typ. 0.7 µA (VCC = 3.0 V, Stop mode)
Flash memory Program/erase supply voltage VCC = 2.7 to 5.5 V
Program/erase endurance
100 times
Operating ambient temperature
-20 to 85 °C
-40 to 85 °C (D-version)
Package
32-pin plastic mold LQFP
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
page 2 of 26
R8C/11 Group
1. Overview
1.3 Block Diagram
Figure 1.1 shows this MCU block diagram.
8
8
I/O port
Port P0
1
5
Port P3
Port P1
2
Port P4
Peripheral functions
Timer
Timer X (8 bits)
Timer Y (8 bits)
Timer Z (8 bits)
Timer C (16 bits)
A/D converter
(10 bits ✕ 12 channels)
System clock generator
UART or Clock synchronous
serial I/O
(8 bits ✕ 1 channel)
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
UART
(8 bits ✕ 1 channel)
Memory
R8C/Tiny Series CPU core
Watchdog timer
(15 bits)
R0H
R1H
R0L
R1L
R2
R3
SB
(1)
RAM
(2)
ISP
INTB
A0
A1
FB
ROM
USP
PC
FLG
Multiplier
NOTES:
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.
Figure 1.1 Block Diagram
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
page 3 of 26
R8C/11 Group
1. Overview
1.4 Product Information
Table 1.2 lists the product information.
Table 1.2 Product Information
As of January 2006
ROM capacity
RAM capacity
R5F21112FP
8K bytes
512 bytes
PLQP0032GB-A
R5F21113FP
12K bytes
768 bytes
PLQP0032GB-A
R5F21114FP
16K bytes
1K bytes
PLQP0032GB-A
R5F21112DFP
8K bytes
512 bytes
PLQP0032GB-A
R5F21113DFP
12K bytes
768 bytes
PLQP0032GB-A
R5F21114DFP
16K bytes
1K bytes
PLQP0032GB-A
Type No.
Type No. R 5 F
Remarks
Package type
Flash memory version
D version
21 11 4 D FP
Package type:
FP : PLQP0032GB-A
Classification:
D: Operating ambient temperature –40 °C to 85 °C
No symbol: Operating ambient temperature –20 °C to 85 °C
ROM capacity:
2 : 8 KBytes.
3 : 12 KBytes.
4 : 16 KBytes.
R8C/11 group
R8C/Tiny series
Memory type:
F: Flash memory version
Renesas MCU
Renesas semiconductors
Figure 1.2 Type No., Memory Size, and Package
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
page 4 of 26
R8C/11 Group
1. Overview
1.5 Pin Assignments
Figure 1.3 shows the pin configuration (top view).
P30/CNTR0/CMP10
AVSS
P31/TZOUT/CMP11
AVCC/VREF
P32/INT2/CNTR1/CMP12
P33/INT3/ TCIN
P07/AN0
IVCC
PIN CONFIGURATION (top view)
24 23 22 21 20 19 18 17
P06/AN1
P05/AN2
P04/AN3
MODE
P03/AN4
P02/AN5
P01/AN6
P00/AN7/TxD11
25
26
27
28
29
30
31
32
R8C/11 Group
16
15
14
13
12
11
10
9
P45/INT0
P10/KI0/AN8/CMP00
P11/KI1/AN9/CMP01
P12/KI2/AN10/CMP02
P13/KI3/AN11
P14/TxD0
P15/RxD0
P16/CLK0
RESET
XOUT/P47 (1)
VSS
XIN/P46
VC C
P17/INT1/CNTR0
P37/TxD10/RxD1
CNVSS
1 2 3 4 5 6 7 8
NOTES:
1. P47 functions only as an input port.
2. When using On-chip debugger, do not use pins P00/AN7/TxD11
and P37/TxD10/RxD1.
3. Do not connect IVcc to Vcc.
Package: PLQP0032GB-A (32P6U-A)
Figure 1.3 Pin Assignments (Top View)
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
page 5 of 26
R8C/11 Group
1. Overview
1.6 Pin Description
Table 1.3 shows the pin description
Table 1.3 Pin description
Signal name
Power supply
input
IVcc
Pin name
Vcc,
Vss
IVcc
I/O type
O
Analog power
supply input
AVcc, AVss
I
Power supply input pins for A/D converter. Connect the
AVcc pin to Vcc. Connect the AVss pin to Vss. Connect a
capacitor between pins AVcc and AVss.
Reset input
CNVss
MODE
Main clock input
RESET
CNVss
MODE
XIN
I
I
I
I
I
I
I/O
O
I/O
O
I
O
Input “L” on this pin resets the MCU.
Connect this pin to Vss via a resistor.
Connect this pin to Vcc via a resistor.
These pins are provided for the main clock generating circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins. To use
an externally derived clock, input it to the XIN pin and
leave the XOUT pin open.
______
INT interrupt input pins.
Key input interrupt pins.
Timer X I/O pin
Timer X output pin
Timer Y I/O pin
Timer Z output pin
Timer C input pin
Timer C output pins
I/O
I
O
Transfer clock I/O pin.
Serial data input pins.
Serial data output pins.
I
Reference voltage input pin for A/D converter. Connect the VREF pin to Vcc.
Analog input pins for A/D converter
These are 8-bit CMOS I/O ports. Each port has an I/O
select direction register, allowing each pin in that port
to be directed for input or output individually.
Any port set to input can select whether to use a pullup resistor or not by program.
P10 to P17 also function as LED drive ports.
Port for input-only
I
___________
Main clock output XOUT
_____
_______
O
_______
INT interrupt input INT
0 to_____
INT3
_____
Key input interrupt KI0 to KI3
Timer X
CNTR0
____________
CNTR0
Timer Y
CNTR1
Timer Z
TZOUT
Timer C
TCIN
CMP00 to CMP02,
CMP10 to CMP12
Serial interface
CLK0
RxD0, RxD1
TxD0, TxD10,
TxD11
Reference voltage VREF
input
A/D converter
AN0 to AN11
I/O port
P00 to P07,
P10 to P17,
P30 to P33, P37,
P45
Input port
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
P46, P47
page 6 of 26
I
I/O
I
Function
Apply 2.7 V to 5.5 V to the Vcc pin. Apply 0 V to the
Vss pin.
This pin is to stabilize internal power supply.
Connect this pin to Vss via a capacitor (0.1 µF).
Do not connect to Vcc.
R8C/11 Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. Two sets of register banks are provided.
b31
b15
b8 b7
b0
R2
R0H (high-order of R0) R0L (low-order of R0)
R3
R1H (high-order of R1) R1L (low-order of R1)
R2
Data registers(1)
R3
A0
b19
A1
Address registers(1)
FB
Frame base registers(1)
b15
b0
INTBH
INTBL
Interrupt table register
The 4-high order bits of INTB are INTBH and
the 16-low bits of INTB are INTBL.
b19
b0
PC
Program counter
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
b8
IPL
b7
U I
Flag register
b0
O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
NOTES:
1. A regist er bank co mpr ises t hese regist ers. Two set s of r eg ist er banks are prov ided
Figure 2.1 CPU Register
2.1 Data Registers (R0, R1, R2 and R3)
R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The R0
can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers.
The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit
data register (R2R0). The same applies to R3R1 as R2R0.
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
page 7 of 26
R8C/11 Group
2. Central Processing Unit (CPU)
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing.
They also are used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A0 can be
combined with A0 to be used as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register indicates the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC, 20 bits wide, indicates the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP and ISP, are 16 bits wide each.
The U flag of FLG is used to switch between USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is a 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)
The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic logic unit.
2.8.2 Debug Flag (D)
The D flag is for debug only. Set to “0”.
2.8.3 Zero Flag (Z)
The Z flag is set to “1” when an arithmetic operation resulted in 0; otherwise, “0”.
2.8.4 Sign Flag (S)
The S flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, “0”.
2.8.5 Register Bank Select Flag (B)
The register bank 0 is selected when the B flag is “0”. The register bank 1 is selected when this flag is
set to “1”.
2.8.6 Overflow Flag (O)
The O flag is set to “1” when the operation resulted in an overflow; otherwise, “0”.
2.8.7 Interrupt Enable Flag (I)
The I flag enables a maskable interrupt.
An interrupt is disabled when the I flag is set to “0”, and are enabled when the I flag is set to “1”. The
I flag is set to “0” when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to “0”, USP is selected when the U flag is set to “1”.
The U flag is set to “0” when a hardware interrupt request is acknowledged or the INT instruction of
software interrupt numbers 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has greater priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
When write to this bit, set to “0”. When read, its content is indeterminate.
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
page 8 of 26
R8C/11 Group
3. Memory
3. Memory
Figure 3.1 is a memory map of this MCU. This MCU provides 1-Mbyte address space from addresses
0000016 to FFFFF16.
The internal ROM is allocated lower addresses beginning with address 0FFFF16. For example, a 16-Kbyte
internal ROM is allocated addresses from 0C00016 to 0FFFF16.
The fixed interrupt vector table is allocated addresses 0FFDC16 to 0FFFF16. They store the starting
address of each interrupt routine.
The internal RAM is allocated higher addresses beginning with address 0040016. For example, a 1-Kbyte
internal RAM is allocated addresses 0040016 to 007FF16. The internal RAM is used not only for storing
data, but for calling subroutines and stacks when interrupt request is acknowledged.
Special function registers (SFR) are allocated addresses 0000016 to 002FF16. The peripheral function
control registers are located them. All addresses, which have nothing allocated within the SFR, are reserved area and cannot be accessed by users.
0000016
SFR
(See Chapter 4 for details.)
002FF16
0040016
Internal RAM
0XXXX16
0FFDC16
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer,Oscillation stop detection,Voltage detection
0YYYY16
(Reserved)
(Reserved)
Reset
Internal ROM
0FFFF16
0FFFF16
Expansion area
FFFFF16
NOTES :
1. Blank spaces are reserved. No access is allowed.
Type name
Internal ROM
Address 0YYYY16
Size
Internal RAM
Address 0XXXX16
Size
R5F21114FP, R5F21114DFP
16K bytes
0C00016
1K bytes
R5F21113FP, R5F21113DFP
12K bytes
0D00016
768 bytes
006FF16
R5F21112FP, R5F21112DFP
8K bytes
0E00016
512 bytes
005FF16
Figure 3.1 Memory Map
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
page 9 of 26
007FF16
R8C/11 Group
4. Special Function Register (SFR)
4. Special Function Register (SFR)
SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.4 list the SFR
information
Table 4.1 SFR Information(1)(1)
Register
Address
Symbol
After reset
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
Processor mode register 0
Processor mode register 1
System clock control register 0
System clock control register 1
High-speed on-chip oscillator control register 0
Address match interrupt enable register
Protect register
High-speed on-chip oscillator control register 1
Oscillation stop detection register
Watchdog timer reset register
Watchdog timer start register
Watchdog timer control register
Address match interrupt register 0
PM0
PM1
CM0
CM1
HR0
AIER
PRCR
HR1
OCD
WDTR
WDTS
WDC
RMAD0
0016
0016
011010002
001000002
0016
XXXXXX002
00XXX0002
4016
000001002
XX16
XX16
000111112
0016
0016
X016
Address match interrupt register 1
RMAD1
0016
0016
X016
Voltage detection register 1(2)
Voltage detection register 2(2)
VCR1
VCR2
000010002
0016 (3)
100000002(4)
INT0 input filter select register
Voltage detection interrupt register (2)
INT0F
D4INT
XXXXX0002
0016 (3)
010000012 (4)
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
X : Undefined
NOTES:
1. Blank spaces are reserved. No access is allowed.
2. Software reset or the watchdog timer reset does not affect this register.
3. Owing to Reset input.
4. In the case of RESET pin = H retaining.
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
page 10 of 26
R8C/11 Group
4. Special Function Register (SFR)
Table 4.2 SFR Information(2)(1)
Register
Symbol
After reset
Key input interrupt control register
AD conversion interrupt control register
KUPIC
ADIC
XXXXX0002
XXXXX0002
Compare 1 interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
CMP1IC
S0TIC
S0RIC
S1TIC
S1RIC
INT2IC
TXIC
TYIC
TZIC
INT1IC
INT3IC
TCIC
CMP0IC
INT0IC
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XX00X0002
Address
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005B16
INT2 interrupt control register
Timer X interrupt control register
Timer Y interrupt control register
Timer Z interrupt control register
INT1 interrupt control register
INT3 interrupt control register
Timer C interrupt control register
005C16
Compare 0 interrupt control register
005D16
INT0 interrupt control register
005516
005616
005716
005816
005916
005A16
005E16
005F16
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
X : Undefined
NOTES:
1. Blank spaces are reserved. No access is allowed.
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
page 11 of 26
R8C/11 Group
4. Special Function Register (SFR)
Table 4.3 SFR Information(3)(1)
Register
Timer Y, Z mode register
Prescaler Y register
Timer Y secondary register
Timer Y primary register
Timer Y, Z waveform output control register
Prescaler Z register
Timer Z secondary register
Timer Z primary register
Symbol
TYZMR
PREY
TYSC
TYPR
PUM
PREZ
TZSC
TZPR
After reset
0016
FF16
FF16
FF16
0016
FF16
FF16
FF16
Timer Y, Z output control register
Timer X mode register
Prescaler X register
Timer X register
Timer count source set register
TYZOC
TXMR
PREX
TX
TCSS
0016
0016
FF16
FF16
0016
Timer C register
TC
0016
0016
External input enable register
INTEN
0016
Key input enable register
KIEN
0016
Timer C control register 0
Timer C control register 1
Capture, compare 0 register
TCC0
TCC1
TM0
009E16
Compare 1 register
TM1
009F16
00A016
UART0 transmit/receive mode register
U0MR
U0BRG
U0TB
0016
0016
0016
0016 (2)
FF16
FF16
0016
XX16
XX16
XX16
000010002
000000102
XX16
X X1 6
0016
XX16
XX16
X X1 6
000010002
000000102
XX16
X X1 6
0016
Address
008016
008116
008216
008316
008416
008516
008616
008716
008816
008916
008A16
008B16
008C16
008D16
008E16
008F16
009016
009116
009216
009316
009416
009516
009616
009716
009816
009916
009A16
009B16
009C16
009D16
00A116
00A216
UART0 bit rate register
UART0 transmit buffer register
00A316
00A516
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
00A616
UART0 receive buffer register
00A416
U0C0
U0C1
U0RB
00A716
00A816
UART1 transmit/receive mode register
00A916
UART1 bit rate register
UART1 transmit buffer register
00AA16
U1MR
U1BRG
U1TB
00AB16
00AD16
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
00AE16
UART1 receive buffer register
U1C0
U1C1
U1RB
UART transmit/receive control register 2
UCON
00AC16
00AF16
00B016
00B116
00B216
00B316
00B416
00B516
00B616
00B716
00B816
00B916
00BA16
00BB16
00BC16
00BD16
00BE16
00BF16
X : Undefined
NOTES:
1. Blank spaces are reserved. No access is allowed.
2. When output compare mode (the TCC13 bit in the TCC1 register = 1) is selected, the value after reset is set to “FFFF16”.
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
page 12 of 26
R8C/11 Group
4. Special Function Register (SFR)
Table 4.4 SFR Information(4)(1)
Register
Address
AD register
Symbol
AD
AD control register 2
ADCON2
0016
AD control register 0
AD control register 1
ADCON0
ADCON1
00000XXX2
0016
Port P0 register
Port P1 register
Port P0 direction register
Port P1 direction register
P0
P1
PD0
PD1
XX16
X X1 6
0016
0016
Port P3 register
P3
X X1 6
Port P3 direction register
Port P4 register
PD3
P4
0016
X X1 6
Port P4 direction register
PD4
0016
00FF16
Pull-up control register 0
Pull-up control register 1
Port P1 drive capacity control register
Timer C output control register
PUR0
PUR1
DRR
TCOUT
00XX00002
XXXXXX0X2
0016
0016
01B316
Flash memory control register 4
FMR4
010000002
Flash memory control register 1
FMR1
0100XX0X2
Flash memory control register 0
FMR0
000000012
00C016
00C116
After reset
X X1 6
XX16
00C216
00C316
00C416
00C516
00C616
00C716
00C816
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
00D216
00D316
00D416
00D516
00D616
00D716
00D816
00D916
00DA16
00DB16
00DC16
00DD16
00DE16
00DF16
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
00EF16
00F016
00F116
00F216
00F316
00F416
00F516
00F616
00F716
00F816
00F916
03FA16
00FB16
00FC16
00FD16
00FE16
01B416
01B516
01B616
01B716
X : Undefined
NOTES:
1. Blank columns, 010016 to 01B216 and 01B816 to 02FF16 are all reserved. No access is allowed.
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
page 13 of 26
R8C/11 Group
5. Electrical Characteristics
5. Electrical Characteristics
Table 5.1 Absolute Maximum Ratings
Condition
Rated value
Unit
VCC
Symbol
Supply voltage
Parameter
VCC=AVCC
-0.3 to 6.5
V
AVCC
Analog supply voltage
VCC=AVCC
-0.3 to 6.5
V
VI
Input voltage
-0.3 to VCC+0.3
V
VO
Output voltage
-0.3 to VCC+0.3
V
Pd
Power dissipation
300
mW
Topr
Operating ambient temperature
-20 to 85 / -40 to 85 (D version)
C
Tstg
Storage temperature
Topr=25 C
C
-65 to 150
Table 5.2 Recommended Operating Conditions
Symbol
Parameter
VC C
AVcc
Supply voltage
Analog supply voltage
Vss
Supply voltage
Conditions
Min.
Standard
Typ.
2.7
Max.
5.5
VCC(3)
0
Unit
V
V
V
V
AVss
Analog supply voltage
VIH
"H" input voltage
0.8VCC
VCC
V
VIL
"L" input voltage
0
0.2VCC
V
-60.0
mA
-10.0
mA
-5.0
mA
60
mA
I OH (peak)
Sum of all pins' IOH
"H" peak all
output currents (peak)
"H" peak output current
I OH (avg)
"H" average output current
I OL (sum)
Sum of all pins' IOL
"L" peak all
output currents (peak)
"L" peak output Except P10 to P17
current
P10 to P17
I OH (sum)
I OL (peak)
I OL (avg)
f (XIN)
"L" average
output current
Except P10 to P17
P10 to P17
0
Drive capacity HIGH
Drive capacity LOW
Drive capacity HIGH
Drive capacity LOW
Main clock input oscillation frequency 3.0V ≤ Vcc ≤ 5.5V
2.7V ≤ Vcc < 3.0V
0
0
NOTES:
1. VCC = AVCC = 2.7 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C, unless otherwise specified.
2. The typical values when average output current is 100ms.
3. Hold Vcc=AVcc.
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
page 14 of 26
10
mA
30
mA
10
mA
5
15
5
20
10
mA
mA
mA
MHz
MHz
R8C/11 Group
5. Electrical Characteristics
Table 5.3 A/D Conversion Characteristics
Symbol
Parameter
–
Resolution
–
Absolute
accuracy
RLADDER Ladder resistance
Conversion time
tCONV
VREF
VIA
Measuring condition
Standard
Unit
Min. Typ. Max.
Vref =VCC
10
Bit
10 bit mode
øAD=10 MHz, Vref=Vcc=5.0V
±3
LSB
8 bit mode
øAD=10 MHz, Vref=Vcc=5.0V
±2
LSB
10 bit mode
øAD=10 MHz, Vref=Vcc=3.3V(3)
±5
LSB
8 bit mode
øAD=10 MHz, Vref=Vcc=3.3V(3)
±2
LSB
kΩ
VREF=VCC
10 bit mode øAD=10 MHz, Vref=Vcc=5.0V
8 bit mode øAD=10 MHz, Vref=Vcc=5.0V
Reference voltage
Analog input voltage
10
40
µs
µs
3.3
2.8
V
VCC(4)
Vref
V
10
MHz
10
NOTES:
1. VCC=AVCC=2.7 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C, unless otherwise specified.
2. If fAD exceeds 10 MHz more, divide the fAD and hold A/D operating clock frequency (ØAD) 10 MHz or below.
3. If the AVcc is less than 4.2V, divide the fAD and hold A/D operating clock frequency (ØAD) fAD/2 or below.
4. Hold Vcc=Vref.
MHz
–
0
A/D operating
Without sample & hold
clock frequency(2) With sample & hold
0.25
1.0
P0
P1
P2
P3
P4
Figure 5.1 Port P0 to P4 measurement circuit
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
page 15 of 26
30pF
R8C/11 Group
5. Electrical Characteristics
Table 5.4 Flash Memory Version Electrical Characteristics
Symbol
Parameter
–
Program/erase endurance
–
Byte program time
–
Block erase time
Measuring condition
Standard
Typ.
Unit
Max
times
100
50
0.4
Time delay from suspend request until erase
td(SR-ES)
suspend
Erase Suspend Request Interval
–
–
Min.
400
µs
9
s
8
ms
ms
10
Program, Erase voltage
2.7
5.5
Read voltage
2.7
5.5
V
0
60
°C
–
–
Program, Erase temperature
–
Data hold time(2)
Ambient
temperature=55 °C
V
20
year
NOTES:
1. Referenced to VCC1=AVcc=2.7 to 5.5V at Topr = 0 to 60 °C unless otherwise specified.
2. The data hold time includes time that the power supply is off or the clock is not supplied.
Table 5.5 Voltage Detection Circuit Electrical Characteristics
Symbol
Vdet
Parameter
Measuring condition
Voltage detection level
Min.
Standard
Typ.
3 .3
3 .8
Voltage detection circuit self consumption current
Waiting time till voltage detection circuit operation starts(3)
Vccmin
Minimum value of microcomputer operation voltage
4 .3
40
Voltage detection interrupt request generating time(2)
td(E-A)
Max.
VC27=1, VCC=5.0V
V
µs
nA
600
20
2.7
Unit
µs
V
NOTES:
1. The measuring condition is Vcc=AVcc=2.7V to 5.5V and Topr= -40°C to 85 °C.
2. This shows the time until the voltage detection interrupt request is generated since the voltage passes Vdet.
3. This shows the required time until the voltage detection circuit operates when setting to "1" again after setting the VC27 bit in
the VCR2 register to “0”.
Erase-suspend request
(interrupt request)
FMR46
td(SR-ES)
Figure 5.2 Time delay from Suspend Request until Erase Suspend
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
page 16 of 26
R8C/11 Group
5. Electrical Characteristics
Table 5.6 Reset Circuit Electrical Characteristics (When Using Hardware Reset 2(1, 3))
Symbol
Vpor2
Measuring condition
Parameter
Power-on reset valid voltage
tW(Vpor2- Supply voltage rising time when power-on reset is canceled(2)
Vdet)
Min.
Standard
Typ.
Max.
Unit
–20°C ≤ Topr < 85°C
Vdet
V
–20°C ≤ Topr < 85°C, tW(por2) ≥ 0s(4)
100
ms
NOTES:
1. The voltage detection circuit which is embedded in a microcomputer is a factor to generate the hardware reset 2. Refer to 5.1.2 Hardware
Reset 2 of Hardware Manual for details.
2. This condition is not applicable when using with Vcc ≥ 1.0V.
3. When turning power on after the external power has been held below the valid voltage (Vpor1) for greater than 10 seconds, refer to Table 5.7
Reset Circuit Electrical Characteristics (When Not Using Hardware Reset 2).
4. tw(por2) is time to hold the external power below effective voltage (Vpor2).
Table 5.7 Reset Circuit Electrical Characteristics (When Not Using Hardware Reset 2)
Symbol
Measuring condition
Parameter
Min.
Standard
Typ.
Max.
Unit
–20°C ≤ Topr < 85°C
0.1
V
tW(Vpor1- Supply voltage rising time when power-on reset is canceled
Vdet)
0°C ≤ Topr ≤ 85°C, tW(por1) ≥ 10s(2)
100
ms
tW(Vpor1Supply voltage rising time when power-on reset is canceled
Vdet)
–20°C ≤ Topr < 0°C, tW(por1) ≥ 30s(2)
100
ms
tW(Vpor1Vdet) Supply voltage rising time when power-on reset is canceled
tW(Vpor1Supply voltage rising time when power-on reset is canceled
Vdet)
–20°C ≤ Topr < 0°C, tW(por1) ≥ 10s(2)
1
ms
0°C ≤ Topr ≤ 85°C, tW(por1) ≥
0.5
ms
Vpor1
Power-on reset valid voltage
1s(2)
NOTES:
1. When not using hardware reset 2, use with Vcc ≥ 2.7V.
2. tw(por1) is time to hold the external power below effective voltage (Vpor1).
Vdet(3)
Vdet(3)
Vcc min
Vpor2
Vpor1
Sampling time(1, 2)
tw(por2) tw(Vpor2 –Vdet)
tw(por1) tw(Vpor1–Vdet)
Internal reset signal
(“L” effective)
1
X 32
fRING-S
1
X 32
fRING-S
NOTES:
1. Hold the voltage of the microcomputer operation voltage range (Vccmin or above) within sampling time.
2. A sampling clock is selectable. Refer to “5.4 Voltage Detection Circuit” of Hardware Manual for details.
3. Vdet shows the voltage detection level of the voltage detection circuit. Refer to “5.4 Voltage Detection Circuit” for details.
4. Refer to “Table 16.6 Reset Circuit Electrical Characteristics” for electrical characteristics.
Figure 5.3 Reset Circuit Electrical Characteristics
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
page 17 of 26
R8C/11 Group
5. Electrical Characteristics
Table 5.8 High-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol
Measuring condition
Parameter
High-speed on-chip oscillator frequency 1 / {td(HRoffset)+td(HR)} when the
reset is released
Standard
Typ.
Max.
6
8
10
VCC=5.0V, Topr=25 °C
Set "0016" in the HR1 register
Differences when setting "0116" and "0016"
in the HR register
td(HRoffset) Settable high-speed on-chip oscillator minimum period
td(HR)
VCC=5.0V, Topr=25 °C
Set "4016" in the HR1 register
Min.
High-speed on-chip oscillator period adjusted unit
Unit
MHz
61
ns
1
ns
High-speed on-chip oscillator frequency temperature dependence(1)
Frequency fluctuation in temperature range
of -10 °C to 50 °C
±5
%
High-speed on-chip oscillator frequency temperature dependence(2)
Frequency fluctuation in temperature range
of -40 °C to 85 °C
±10
%
NOTES:
1. The measuring condition is Vcc=AVcc=5.0 V and Topr=25 °C.
Table 5.9 Power Circuit Timing Characteristics
Symbol
Measuring condition
Parameter
td(P-R)
Time for internal power supply stabilization during powering-on(2)
td(R-S)
STOP release time(3)
Min.
Standard
Typ.
Max.
Unit
2000
µs
150
µs
Standard
Max.
Typ.
Unit
1
NOTES:
1. The measuring condition is Vcc=AVcc=2.7 to 5.5 V and Topr=25 °C.
2. This shows the wait time until the internal power supply generating circuit is stabilized during power-on.
3. This shows the time until BCLK starts from the interrupt acknowledgement to cancel stop mode.
Table 5.10 Electrical Characteristics (1)
Symbol
[Vcc=5V]
Measuring condition
Parameter
Except XOUT
"H" output voltage
VOH
XOUT
IOH=-5mA
IOH=-200µA
Drive ability HIGH
Except P10 to P17, XOUT
"L" output voltage
P10 to P17
XOUT
V
V
V
V
IOL= 5 mA
2.0
V
IOL= 200 µA
0.45
V
2.0
V
V
Drive capacity HIGH
Hysteresis
II H
"H" input current
IOH=-1 mA
IOH=-500µA
IOL= 15 mA
Drive capacity LOW
IOL= 5 mA
2.0
Drive capacity LOW
IOL= 200 µA
0.45
V
Drive capacity HIGH
IOL= 1 mA
IOL=500 µA
2.0
V
Drive capacity LOW
VT+-VT-
VCC-2.0
VCC-0.3
VCC-2.0
VCC-2.0
VCC
VCC
VCC
VCC
Drive ability LOW
VOL
Min.
INTo, INT1, INT2, INT3, KI0, KI1,
KI2, KI3, CNTR0, CNTR1, TCIN,
RxD0, RxD1, P45
RESET
II L
"L" input current
VI=5V
VI=0V
RPULLUP
Pull-up resistance
VI=0V
RfXIN
Feedback resistance
fRING-S
Low-speed on-chip oscillator frequency
VRAM
RAM retention voltage
2.0
V
0.2
1.0
V
0.2
2.2
V
5.0
µA
µA
kΩ
-5.0
30
50
167
40
1.0
125
250
XIN
At stop mode
2.0
NOTES:
1. Referenced to VCC = AVCC = 4.2 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C, f(XIN)=20MHz unless otherwise specified.
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
page 18 of 26
MΩ
kHz
V
R8C/11 Group
5. Electrical Characteristics
Table 5.11 Electrical Characteristics (2)
Symbol
[Vcc=5V]
Measuring condition
Parameter
High-speed
mode
Medium-speed
mode
ICC
Power supply current
(VCC=3.3 to 5.5V)
In single-chip mode, the output
pins are open and other pins
are VSS
XIN=20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
No division
XIN=16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
No division
XIN=10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
No division
XIN=20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
Division by 8
XIN=16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
Division by 8
XIN=10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
Division by 8
Main clock off
High-speed
High-speed on-chip oscillator on=8 MHz
on-chip oscillator Low-speed on-chip oscillator on=125 kHz
mode
No division
Max.
Unit
9
15
mA
8
14
mA
5
mA
4
mA
3
mA
2
mA
4
8
mA
1.5
Main clock off
Low-speed
High-speed on-chip oscillator off
on-chip oscillator Low-speed on-chip oscillator on=125 kHz
mode
Division by 8
470
900
µA
40
80
µA
38
76
µA
0 .8
3 .0
µA
Wait mode
Stop mode
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
When a WAIT instruction is executed(1)
Peripheral clock operation
VC27=“0”
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
When a WAIT instruction is executed(1)
Peripheral clock off
VC27=“0”
Main clock off, Topr = 25 °C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10="1"
Peripheral clock off
VC27="0"
NOTES:
1. Timer Y is operated with timer mode.
2. Referenced to VCC = AVCC = 4.2 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C, f(XIN)=20MHz unless otherwise specified.
page 19 of 26
Standard
Typ.
Main clock off
High-speed on-chip oscillator on=8 MHz
Low-speed on-chip oscillator on=125 kHz
Division by 8
Wait mode
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
Min.
mA
R8C/11 Group
5. Electrical Characteristics
Timing requirements (Unless otherwise noted: VCC = 5V, VSS = 0V at Topr = 25 °C) [VCC=5V]
Table 5.12 XIN input
Symbol
tC(XIN)
tWH(XIN)
tWL(XIN)
Parameter
XIN input cycle time
XIN input HIGH pulse width
XIN input LOW pulse width
Standard
Min.
Max.
50
–
25
–
25
–
Unit
Standard
Min.
Max.
100
–
40
–
40
–
Unit
Standard
Min.
Max.
400(1)
–
200(2)
–
200(2)
–
Unit
ns
ns
ns
________
Table 5.13 CNTR0 input, CNTR1 input, INT2 input
Symbol
Parameter
tC(CNTR0)
tWH(CNTR0)
tWL(CNTR0)
CNTR0 input cycle time
CNTR0 input HIGH pulse width
CNTR0 input LOW pulse width
ns
ns
ns
________
Table 5.14 TCIN input, INT3 input
Symbol
tC(TCIN)
tWH(TCIN)
tWL(TCIN)
Parameter
TCIN input cycle time
TCIN input HIGH pulse width
TCIN input LOW pulse width
ns
ns
ns
NOTES:
1. When using the Timer C input capture mode, adjust the cycle time above ( 1/ Timer C count source
frequency x 3).
2. When using the Timer C input capture mode, adjust the pulse width above ( 1/ Timer C count source
frequency x 1.5).
Table 5.15 Serial Interface
Symbol
tC(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Parameter
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
RxDi input setup time
RxDi input hold time
Standard
Min.
Max.
200
–
100
–
100
–
80
–
–
0
–
35
–
90
Unit
Standard
Min.
Max.
250(1)
–
250(2)
–
Unit
ns
ns
ns
ns
ns
ns
ns
________
Table 5.16 External interrupt INT0 input
Symbol
Parameter
________
tW(INH)
tW(INL)
INT0
input HIGH pulse width
________
INT0 input LOW pulse width
ns
ns
NOTES:
________
________
1. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input HIGH pulse width
to the greater value,either ( 1/ digital filter
clock frequency x 3) or the minimum
value of standard.
________
________
2. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input LOW pusle width
to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard.
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
page 20 of 26
R8C/11 Group
5. Electrical Characteristics
VCC = 5V
tc(CNTR0)
tWH(CNTR0)
CNTR0 input
tWL(CNTR0)
tc(TCIN)
tWH(TCIN)
TCIN input
tWL(TCIN)
tc(XIN)
tWH(XIN)
XIN input
tWL(XIN)
tc(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TxDi
td(C-Q)
tsu(D-C)
RxDi
tW(INL)
INTi
tW(INH)
Figure 5.4 Vcc=5V timing diagram
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
page 21 of 26
th(C-D)
R8C/11 Group
5. Electrical Characteristics
Table 5.17 Electrical Characteristics (3)
Symbol
[Vcc=3V]
Measuring condition
Parameter
"H" output voltage
VOH
"L" output voltage
VOL
Except XOUT
IOH=-1mA
XOUT
Drive capacity HIGH
Drive capacity LOW
Except P10 to P17, XOUT
IOL= 1 mA
P10 to P17
Drive capacity HIGH
XOUT
VT+-VT-
Hysteresis
II H
"H" input current
IOH=-0.1 mA
IOH=-50 µA
Min.
VC C
V
VCC-0.5
VCC-0.5
VCC
VC C
V
V
0 .5
V
IOL= 2 mA
IOL= 1 mA
0.5
V
Drive capacity LOW
0.5
V
Drive capacity HIGH
Drive capacity LOW
IOL= 0.1 mA
IOL=50 µ A
0 .5
0 .5
V
V
0 .2
0 .8
V
0 .2
1 .8
V
4.0
µA
-4.0
µA
INTo, INT1, INT2, INT3, KI0, KI1,
KI2, KI3, CNTR0, CNTR1, TCIN,
RxD0, RxD1, P45
VI=3V
VI=0V
II L
"L" input current
RPULLUP
RfXIN
Pull-up resistance
Feedback resistance
fRING-S
Low-speed on-chip oscillator frequency
VRAM
RAM retention voltage
VI=0V
66
160
40
3.0
125
XIN
At stop mode
NOTES:
1. Referenced to VCC = AVCC = 2.7 to 3.3V at Topr = -20 to 85 °C / -40 to 85 °C, f(XIN)=10MHz unless otherwise specified.
page 22 of 26
Unit
VCC-0.5
RESET
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
Standard
Typ.
Max.
2 .0
500
kΩ
250
MΩ
kHz
V
R8C/11 Group
5. Electrical Characteristics
Table 5.18 Electrical Characteristics (4)
Symbol
[Vcc=3V]
Measuring condition
Parameter
High-speed
mode
Medium-speed
mode
ICC
Power supply current
(VCC=2.7 to 3.3V)
In single-chip mode, the output
pins are open and other pins
are VSS
XIN=20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
No division
XIN=16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
No division
XIN=10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
No division
XIN=20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
Division by 8
XIN=16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
Division by 8
XIN=10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
Division by 8
Max.
Unit
8
13
mA
7
12
mA
5
mA
3
mA
2 .5
mA
1 .6
mA
3 .5
Main clock off
High-speed on-chip oscillator on=8 MHz
Low-speed on-chip oscillator on=125 kHz
Division by 8
1 .5
Main clock off
Low-speed
High-speed on-chip oscillator off
on-chip oscillator Low-speed on-chip oscillator on=125 kHz
mode
Division by 8
420
800
µA
37
74
µA
35
70
µA
0 .7
3 .0
Wait mode
Stop mode
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
When a WAIT instruction is executed(1)
Peripheral clock operation
VC27=“0”
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on=125 kHz
When a WAIT instruction is executed(1)
Peripheral clock off
VC27=“0”
Main clock off, Topr = 25 °C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10="1"
Peripheral clock off
VC27="0"
NOTES:
1. Timer Y is operated with timer mode.
2. Referenced to VCC = AVCC = 2.7 to 3.3V at Topr = -20 to 85 °C / -40 to 85 °C, f(XIN)=10MHz unless otherwise specified.
page 23 of 26
Standard
Typ.
Main clock off
High-speed
High-speed on-chip oscillator on=8 MHz
on-chip oscillator Low-speed on-chip oscillator on=125 kHz
mode
No division
Wait mode
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
Min.
7 .5
mA
mA
µA
R8C/11 Group
5. Electrical Characteristics
Timing requirements (Unless otherwise noted: VCC = 3V, VSS = 0V at Topr = 25 °C) [VCC=3V]
Table 5.19 XIN input
Symbol
tC(XIN)
tWH(XIN)
tWL(XIN)
Parameter
XIN input cycle time
XIN input HIGH pulse width
XIN input LOW pulse width
Standard
Min.
Max.
100
–
40
–
40
–
Unit
Standard
Min.
Max.
300
–
120
–
120
–
Unit
Standard
Min.
Max.
1200(1)
–
600(2)
–
600(2)
–
Unit
ns
ns
ns
________
Table 5.20 CNTR0 input, CNTR1 input, INT2 input
Symbol
Parameter
tC(CNTR0)
tWH(CNTR0)
tWL(CNTR0)
CNTR0 input cycle time
CNTR0 input HIGH pulse width
CNTR0 input LOW pulse width
ns
ns
ns
________
Table 5.21 TCIN input, INT3 input
Symbol
Parameter
tC(TCIN)
tWH(TCIN)
tWL(TCIN)
TCIN input cycle time
TCIN input HIGH pulse width
TCIN input LOW pulse width
ns
ns
ns
NOTES:
1. When using the Timer C input capture mode, adjust the cycle time above ( 1/ Timer C count source
frequency x 3).
2. When using the Timer C input capture mode, adjust the pulse width above ( 1/ Timer C count source
frequency x 1.5).
Table 5.22 Serial Interface
Symbol
tC(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Parameter
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
RxDi input setup time
RxDi input hold time
Standard
Min.
Max.
300
–
150
–
150
–
160
–
0
–
55
–
90
–
Unit
Standard
Min.
Max.
380(1)
–
380(2)
–
Unit
ns
ns
ns
ns
ns
ns
ns
________
Table 5.23 External interrupt INT0 input
Symbol
tW(INH)
tW(INL)
Parameter
________
INT0
input HIGH pulse width
________
INT0 input LOW pulse width
ns
ns
NOTES:
________
________
1. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input HIGH pulse width
to the greater value,either ( 1/ digital filter
clock frequency x 3) or the minimum
value of standard.
________
________
2. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input LOW pusle width
to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard.
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
page 24 of 26
R8C/11 Group
5. Electrical Characteristics
VCC = 3V
tc(CNTR0)
tWH(CNTR0)
CNTR0 input
tWL(CNTR0)
tc(TCIN)
tWH(TCIN)
TCIN input
tWL(TCIN)
tc(XIN)
tWH(XIN)
XIN input
tWL(XIN)
tc(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TxDi
td(C-Q)
tsu(D-C)
RxDi
tW(INL)
INTi
tW(INH)
Figure 5.5 Vcc=3V timing diagram
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
page 25 of 26
th(C-D)
R8C/11 Group
Package Dimensions
Package Dimensions
JEITA Package Code
P-LQFP32-7x7-0.80
RENESAS Code
PLQP0032GB-A
Previous Code
32P6U-A
MASS[Typ.]
0.2g
HD
*1
D
24
17
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
16
25
bp
c
c1
HE
*2
E
b1
Reference
Symbol
9
1
ZE
Terminal cross section
32
8
ZD
c
A
A1
F
A2
Index mark
L
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
L1
y
e
Rev.1.60 Jan 27, 2006
REJ03B0034-0160
page 26 of 26
*3
Detail F
bp
x
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
6.9 7.0 7.1
6.9 7.0 7.1
1.4
8.8 9.0 9.2
8.8 9.0 9.2
1.7
0.1 0.2
0
0.32 0.37 0.42
0.35
0.09 0.145 0.20
0.125
0°
8°
0.8
0.20
0.10
0.7
0.7
0.3 0.5 0.7
1.0
REVISION HISTORY
Rev.
R8C/11 Group Datasheet
Date
Description
Summary
Page
1.00 Jun. 19, 2003
First edition issued
1.10 Sep. 08, 2003
2
5
6
10
12
14
Table 1.1: Shortest instruction execution time ____________
and f(XIN) changed
Figure 1.3: Pin name changed from TXOUT to____________
CNTR0
Table 1.3: Pin name changed from TXOUT to CNTR0
The value of HR1 register after reset changed
The value of TC register after reset changed
Chapter “5. Electrical Characteristics” added
1.20 Oct. 31, 2003
2
6
11
24
25
Table 1.1: Power consumption values added
Table 1.3: Resistor value for CNVss and MODE deleted
Register name of address 005016 modified from CMP2IC to CMP1IC, register name
of address 005C16 modified from CMP1IC to CMP0IC
Table 5.2: Note 3 and Note 4 deleted
tsamp in Table 5.3 deleted
Figure 5.1 added
Table 5.10: Vcc changed from “4.2 to 5.5V” to “3.3V to 5.5V”, low-power on-chip
oscillator changed from “on 100kHz” to “125kHz”, X IN =5MHz deleted and
XIN=10MHz added in high-speed mode and medium-speed mode, VC27=”0” added
in stop mode measuring condition, data added and modified
Table 11 to Table 15 added
Figure 5.2 added
Table 5.16: Note 1, f(BCLK)=5 MHz changed to 10 MHz
Table 5.17: low-power ring oscillator changed from “on 100kHz” to “125kHz”,
XIN=5MHz deleted and XIN=10MHz added in high-speed mode and medium-speed
mode, VC27=”0” added in stop mode measuring condition, data added and modified
Table 5.18 to Table 5.22 added
Figure 5.3 added
4
15
Table 1.2 : ** deleted
Table 5.4 revised
14
15
17
19
20
21
22
23
1.30 Dec 05, 2003
1.40 Sep 30, 2004 all pages
2
5
6
9
10-13
12
14
15
16
17
18
Words standardized (on-chip oscillator, serial interface, A/D)
Table 1.1 revised
Figure 1.3, NOTES 3 added
Table 1.3 revised
Figure 3.1, NOTES added
One body sentence in chapter 4 added ; Title of Table 4.1 to 4.4 added
Table 4.3 revised ; Table 4.4 revised
Table 5.2 revised
Table 5.3 revised
Table 5.4 revised ; Table 16.5 revised
Table 5.6, 5.7 adn 5.8 revised ; Figure 5.3 revised
Table 5.9 revised ; Table 5.10 revised
A-1
REVISION HISTORY
Rev.
R8C/11 Group Datasheet
Date
Description
Summary
Page
1.40 Sep 30, 2004
20
22
24
Table 5.12 revised ; Table 5.16 revised
Table 16.17 revised
Table 16.19 revised
1.50 Apr.27.2005
4
5
10
12
15
16
17
18
22
26
Table 1.2, Figure 1.2 package name revised
Figure 1.3 package name revised
Table 4.1 revised
Table 4.3 revised
Table 5.3 partly revised
Table 5.4 partly added
Table 5.6, Table 5.7 revised
Table 5.9, Table 10 partly revised
Table 5.17 partly revised
Package Dimensions revised
1.60 Jan.27.2006
2
3
4
Table 1.1 Performance outline revised
Figure 1.1 Block diagram partly revised
1.4 Product Information, title of Table 1.2 “Product List” →
“Product Informaton” revised
Figure 1.2 Type No., Memory Size, and Package partly revised
Table 1.3 Pin description revised
2 Central Processing Unit (CPU) revised
Figure 2.1 CPU register revised
Table 4.1 SFR Information(1) NOTES:1 revised
Table 4.2 SFR Information(2) NOTES:1 revised
Table 4.3 SFR Information(3);
008116: “Prescaler Y” → “Prescaler Y Register”
008216: “Timer Y Secondary” → “Timer Y Secondary Register”
008316: “Timer Y Primary” → “Timer Y Primary Register”
008516: “Prescaler Z” → “Prescaler Z Register”
008616: “Timer Z Secondary” → “Timer Z Secondary Register”
008716: “Timer Z Primary” → “Timer Z Primary Register”
008C16: “Prescaler X” → “Prescaler X Register” revised
NOTES:1, 2 revised
Table 4.4 SFR Information(4) NOTES:1 revised
Table 5.2 Recommended Operating Conditions; NOTES: 1, 2, 3 revised
Table 5.3 A/D Conversion Characteristics;
“A/D operation clock frequency” → “A/D operating clock frequency” revised
NOTES: 1, 2, 3, 4 revised
Table 5.4 Flash Memory (Program ROM) Electrical Characteristics;
“Topr” → “Ambient temperature” revised
Measuring condition of byte program time and block erase time deleted
Table 5.6 Reset Circuit Electrical Characteristics (When Using Hardware Reset 2)
NOTES: 3 revised
Table 5.8 High-speed On-Chip Oscillator Circuit Electrical Characteristics;
“High-speed on-chip oscillator temperature dependence” →
“High-speed on-chip oscillator frequency temperature dependence” revised
Table 5.10 Electrical Characteristics (1) [VCC=5V];
“P10 to P17 Except XOUT” → “Except P10 to P17, XOUT” revised
6
7-8
10
11
12
13
14
15
16
17
18
A-2
REVISION HISTORY
Rev.
R8C/11 Group Datasheet
Date
Description
Summary
Page
1.60 Jan.27.2006
19
22
23
Table 5.11 Electrical Characteristics (2) [VCC=5V]
NOTES: 1, 2 revised
Measuring condition Stop mode: “Topr = 25 °C”
Table 5.17 Electrical Characteristics (3) [VCC=3V]
“P10 to P17 Except XOUT” → “Except P10 to P17, XOUT” revised
Table 5.18 Electrical Characteristics (4) [VCC=3V]
NOTES: 1, 2 revised
Measuring condition Stop mode: “Topr = 25 °C”
A-3
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