To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1.
2.
3.
4.
5.
6.
7.
All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights
of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.
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of Renesas Electronics or others.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by
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When exporting the products or technology described in this document, you should comply with the applicable export control
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expressly specified in a Renesas Electronics data sheets or data books, etc.
“Standard”:
8.
9.
10.
11.
12.
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support.
“Specific”:
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or
systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare
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You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
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(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
R8C/18 Group, R8C/19 Group
SINGLE-CHIP 16-BIT CMOS MCU
1.
REJ03B0124-0140
Rev.1.40
Apr 14, 2006
Overview
These MCUs are fabricated using a high-performance silicon gate CMOS process, embedding the
R8C/Tiny Series CPU core, and is packaged in a 20-pin molded-plastic LSSOP, SDIP or a 28-pin plastic
molded-HWQFN. It implements sophisticated instructions for a high level of instruction efficiency. With 1
Mbyte of address space, they are capable of executing instructions at high speed.
Furthermore, the R8C/19 Group has on-chip data flash ROM (1 KB × 2 blocks).
The difference between the R8C/18 Group and R8C/19 Group is only the presence or absence of data
flash ROM. Their peripheral functions are the same.
1.1
Applications
Electric household appliances, office equipment, housing equipment (sensors, security systems), general
industrial equipment, audio equipment, etc.
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 1 of 38
R8C/18 Group, R8C/19 Group
1.2
1. Overview
Performance Overview
Table 1.1 outlines the Functions and Specifications for R8C/18 Group and Table 1.2 outlines the
Functions and Specifications for R8C/19 Group.
Table 1.1
Functions and Specifications for R8C/18 Group
Item
Specification
CPU
Number of fundamental
89 instructions
instructions
Minimum instruction execution 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
time
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
Operation mode
Single-chip
Address space
1 Mbyte
Memory capacity
Refer to Table 1.3 Product Information for R8C/18
Group
Peripheral
Ports
I/O ports: 13 pins (including LED drive port)
Functions
Input port: 3 pins
LED drive ports
I/O ports: 4 pins
Timers
Timer X: 8 bits × 1 channel, timer Z: 8 bits × 1 channel
(Each timer equipped with 8-bit prescaler)
Timer C: 16 bits × 1 channel
(Input capture and output compare circuits)
Serial interfaces
1 channel
Clock synchronous serial I/O, UART
1 channel
UART
Comparator
1-bit comparator: 1 circuit, 4 channels
Watchdog timer
15 bits × 1 channel (with prescaler)
Reset start selectable, count source protection mode
Interrupts
Internal: 10 sources, External: 4 sources, Software: 4
sources,
Priority levels: 7 levels
Clock generation circuits
2 circuits
• Main clock oscillation circuit (with on-chip feedback
resistor)
• On-chip oscillator (high speed, low speed)
High-speed on-chip oscillator has frequency
adjustment function
Oscillation stop detection
Main clock oscillation stop detection function
function
Voltage detection circuit
On-chip
Power-on reset circuit
On-chip
Electric
Supply voltage
VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)
Characteristics
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
Current consumption
Typ. 9 mA (VCC = 5.0 V, f(XIN) = 20 MHz, comparator stopped)
Typ. 5 mA (VCC = 3.0V, f(XIN) = 10 MHz, comparator stopped)
Typ. 35 µA (VCC = 3.0 V, wait mode, peripheral clock off)
Typ. 0.7 µA (VCC = 3.0 V, stop mode)
Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V
Programming and erasure
100 times
endurance
Operating Ambient Temperature
-20 to 85°C
-40 to 85°C (D version)
Package
20-pin molded-plastic LSSOP
20-pin molded-plastic SDIP
28-pin molded-plastic HWQFN
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 2 of 38
R8C/18 Group, R8C/19 Group
Table 1.2
1. Overview
Functions and Specifications for R8C/19 Group
Item
Specification
CPU
Number of fundamental
89 instructions
instructions
Minimum instruction
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
execution time
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
Operation mode
Single-chip
Address space
1 Mbyte
Memory capacity
Refer to Table 1.4 Product Information for R8C/19
Group
Peripheral
Ports
I/O ports: 13 pins (including LED drive port)
Functions
Input port: 3 pins
LED drive ports
I/O ports: 4 pins
Timers
Timer X: 8 bits × 1 channel, timer Z: 8 bits × 1 channel
(Each timer equipped with 8-bit prescaler)
Timer C: 16 bits × 1 channel
(Input capture and output compare circuits)
Serial interfaces
1 channel
Clock synchronous serial I/O, UART
1 channel
UART
Comparator
1-bit comparator: 1 circuit, 4 channels
Watchdog timer
15 bits × 1 channel (with prescaler)
Reset start selectable, count source protection mode
Interrupts
Internal: 10 sources, External: 4 sources, Software: 4
sources,
Priority levels: 7 levels
Clock generation circuits
2 circuits
• Main clock generation circuit (with on-chip feedback
resistor)
• On-chip oscillator (high speed, low speed)
High-speed on-chip oscillator has frequency
adjustment function
Oscillation stop detection
Main clock oscillation stop detection function
function
Voltage detection circuit
On-chip
Power-on reset circuit
On-chip
Electric
Supply voltage
VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)
Characteristics
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
Current consumption
Typ. 9 mA (VCC = 5.0 V, f(XIN) = 20 MHz, comparator stopped)
Typ. 5 mA (VCC = 3.0 V, f(XIN) = 10MHz, comparator stopped)
Typ. 35 µA (VCC = 3.0 V, wait mode, peripheral clock off)
Typ. 0.7 µA (VCC = 3.0 V, stop mode)
Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V
Programming and erasure
10,000 times (data flash)
1,000 times (program ROM)
endurance
Operating Ambient Temperature
-20 to 85°C
-40 to 85°C (D version)
Package
20-pin molded-plastic LSSOP
20-pin molded-plastic SDIP
28-pin molded-plastic HWQFN
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 3 of 38
R8C/18 Group, R8C/19 Group
1.3
1. Overview
Block Diagram
Figure 1.1 shows a Block Diagram.
I/O ports
8
4
Port P1
Port P3
1
3
Port P4
Peripheral Functions
Timers
Comparator
(1 bit × 4 channels)
Timer X (8 bits)
Timer Z (8 bits)
Timer C (16 bits)
UART or
clock synchronous serial I/O
(8 bits × 1 channel)
System clock generator
XIN-XOUT
High-speed on-chip
oscillator
Low-speed on-chip
oscillator
UART
(8 bits × 1 channel)
Watchdog timer
(15 bits)
R8C/Tiny Series CPU core
R0H
R1H
R0L
R1L
R2
R3
SB
ROM(1)
USP
ISP
INTB
A0
A1
FB
Memory
RAM(2)
PC
FLG
Multiplier
NOTES:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
Figure 1.1
Block Diagram
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 4 of 38
R8C/18 Group, R8C/19 Group
1.4
1. Overview
Product Information
Table 1.3 lists Product Information for R8C/18 Group and Table 1.4 lists Product Information for R8C/19
Group.
Table 1.3
Product Information for R8C/18 Group
Type No.
R5F21181SP
R5F21182SP
R5F21183SP
R5F21184SP
R5F21181DSP (D)
R5F21182DSP (D)
R5F21183DSP (D)
R5F21184DSP (D)
R5F21181DD
R5F21182DD
R5F21183DD
R5F21184DD
R5F21182NP
R5F21183NP
R5F21184NP
ROM Capacity
4 Kbytes
8 Kbytes
12 Kbytes
16 Kbytes
4 Kbytes
8 Kbytes
12 Kbytes
16 Kbytes
4 Kbytes
8 Kbytes
12 Kbytes
16 Kbytes
8 Kbytes
12 Kbytes
16 Kbytes
RAM Capacity
384 bytes
512 bytes
768 bytes
1 Kbyte
384 bytes
512 bytes
768 bytes
1 Kbyte
384 bytes
512 bytes
768 bytes
1 Kbyte
512 bytes
768 bytes
1 Kbyte
Current of Apr. 2006
Package Type
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PRDP0020BA-A
PRDP0020BA-A
PRDP0020BA-A
PRDP0020BA-A
PWQN0028KA-B
PWQN0028KA-B
PWQN0028KA-B
Remarks
Flash memory version
D version
Flash memory version
Flash memory version
(D): Under Development
Type No.
R 5 F 21 18 4 D SP
Package type:
SP: PLSP0020JB-A
DD: PRDP0020BA-A
NP: PWQN0028KA-B
Classification
D: Operating ambient temperature -40°C to 85°C
No Symbol: Operating ambient temperature -20°C to 85°C
ROM capacity
2: 8 KB
3: 12 KB
4: 16 KB
R8C/18 Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductors
Figure 1.2
Type Number, Memory Size, and Package of R8C/18 Group
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 5 of 38
R8C/18 Group, R8C/19 Group
Table 1.4
1. Overview
Product Information for R8C/19 Group
Type No.
R5F21191SP
R5F21192SP
R5F21193SP
R5F21194SP
R5F21191DSP (D)
R5F21192DSP (D)
R5F21193DSP (D)
R5F21194DSP (D)
R5F21191DD
R5F21192DD
R5F21193DD
R5F21194DD
R5F21192NP
R5F21193NP
R5F21194NP
ROM Capacity
Program ROM Data flash
4 Kbytes
1 Kbyte × 2
8 Kbytes
1 Kbyte × 2
12 Kbytes
1 Kbyte × 2
16 Kbytes
1 Kbyte × 2
4 Kbytes
1 Kbyte × 2
8 Kbytes
1 Kbyte × 2
12 Kbytes
1 Kbyte × 2
16 Kbytes
1 Kbyte × 2
4 Kbytes
1 Kbyte × 2
8 Kbytes
1 Kbyte × 2
12 Kbytes
1 Kbyte × 2
16 Kbytes
1 Kbyte × 2
8 Kbytes
1 Kbyte × 2
12 Kbytes
1 Kbyte × 2
16 Kbytes
1 Kbyte × 2
RAM
Capacity
384 bytes
512 bytes
768 bytes
1 Kbyte
384 bytes
512 bytes
768 bytes
1 Kbyte
384 bytes
512 bytes
768 bytes
1 Kbyte
512 bytes
768 bytes
1 Kbyte
Current of Apr. 2006
Package Type
Remarks
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PRDP0020BA-A
PRDP0020BA-A
PRDP0020BA-A
PRDP0020BA-A
PWQN0028KA-B
PWQN0028KA-B
PWQN0028KA-B
Flash memory version
D version
Flash memory version
Flash memory version
(D): Under Development
Type No.
R 5 F 21 19 4 D SP
Package type:
SP: PLSP0020JB-A
DD: PRDP0020BA-A
NP: PWQN0028KA-B
Classification
D: Operating ambient temperature -40°C to 85°C
No Symbol: Operating ambient temperature -20°C to 85°C
ROM capacity
2: 8 KB
3: 12 KB
4: 16 KB
R8C/19 Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductors
Figure 1.3
Type Number, Memory Size, and Package of R8C/19 Group
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 6 of 38
R8C/18 Group, R8C/19 Group
1.5
1. Overview
Pin Assignments
Figure 1.4 shows Pin Assignments for PLSP0020JB-A Package (Top View), Figure 1.5 shows Pin
Assignments for PRDP0020BA-A Package (Top View) and Figure 1.6 shows Pin Assignments for
PWQN0028KA-B Package (Top View).
PIN assignments (top view)
1
20
P3_4/CMP1_1
P3_7/CNTR0/TXD1
2
19
P3_3/TCIN/INT3/CMP1_0
RESET
3
18
P1_0/KI0/AN8/CMP0_0
XOUT/P4_7(1)
4
17
P1_1/KI1/AN9/CMP0_1
VSS/AVSS
5
16
P4_2/VREF
XIN/P4_6
6
15
P1_2/KI2/AN10/CMP0_2
VCC/AVCC
7
14
P1_3/KI3/AN11/TZOUT
MODE
8
13
P1_4/TXD0
P4_5/INT0/RXD1
9
12
P1_5/RXD0/CNTR01/INT11
10
11
P1_6/CLK0
P1_7/CNTR00/INT10
R8C/18 Group
R8C/19 Group
P3_5/CMP1_2
NOTE:
1. P4_7 is an input-only port.
Package: PLSP0020JB-A(20P2F-A)
Figure 1.4
Pin Assignments for PLSP0020JB-A Package (Top View)
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 7 of 38
R8C/18 Group, R8C/19 Group
1. Overview
PIN assignments (top view)
1
20
P3_4/CMP1_1
P3_7/CNTR0/TXD1
2
19
P3_3/TCIN/INT3/CMP1_0
RESET
3
18
P1_0/KI0/AN8/CMP0_0
XOUT/P4_7(1)
4
17
P1_1/KI1/AN9/CMP0_1
VSS/AVSS
5
16
P4_2/VREF
XIN/P4_6
6
15
P1_2/KI2/AN10/CMP0_2
VCC/AVCC
7
14
P1_3/KI3/AN11/TZOUT
MODE
8
13
P1_4/TXD0
P4_5/INT0/RXD1
9
12
P1_5/RXD0/CNTR01/INT11
10
11
P1_6/CLK0
P1_7/CNTR00/INT10
R8C/18 Group
R8C/19 Group
P3_5/CMP1_2
NOTE:
1. P4_7 is an input-only port.
Package: PRDP0020BA-A(20P4B)
Figure 1.5
Pin Assignments for PRDP0020BA-A Package (Top View)
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 8 of 38
NC
NC
NC
P4_2/VREF
NC
PIN Assignment (top view)
P1_3/AN11/KI3/TZOUT
1. Overview
P1_2/AN10/KI2/CMP0_2
R8C/18 Group, R8C/19 Group
21 20 19 18 17 16 15
P1_1/AN9/KI1/CMP0_1
22
14
P1_4/TXD0
P1_0/AN8/KI0/CMP0_0
23
13
P1_5/RXD0/CNTR01/INT11
P3_3/TCIN/INT3/CMP1_0
24
12
P1_6/CLK0
P3_4/CMP1_1
25
11
P1_7/CNTR00/INT10
P3_5/CMP1_2
26
10
P4_5/INT0/RXD1
P3_7/CNTR0/TXD1
27
9
MODE
RESET
28
8
VCC/AVCC
2
3
4
5
6
7
VSS/AVSS
NC
NC
XIN/P4_6
NC
XOUT/P4_7
NC
1
(1)
R8C/18 Group
R8C/19 Group
NOTES:
1. P4_7 is a port for the input.
Package: PWQN0028KA-B(28PJW-B)
Figure 1.6
Pin Assignments for PWQN0028KA-B Package (Top View)
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 9 of 38
R8C/18 Group, R8C/19 Group
1.6
1. Overview
Pin Functions
Table 1.5 lists Pin Functions, Table 1.6 lists Pin Name Information by Pin Number of PLSP0020JB-A,
PRDP0020BA-A packages, and Table 1.7 lists Pin Name Information by Pin Number of PWQN0028KAB package.
Table 1.5
Pin Functions
I/O Type
Description
Power supply input VCC
VSS
Type
I
Apply 2.7 V to 5.5 V to the VCC pin. Apply 0 V to
the VSS pin.
Analog power
supply input
AVCC, AVSS
I
Power supply for the comparator
Connect a capacitor between AVCC and AVSS.
Reset input
RESET
I
Input “L” on this pin resets the MCU.
MODE
MODE
I
Connect this pin to VCC via a resistor.
Main clock input
XIN
I
Main clock output
XOUT
O
These pins are provided for main clock generation
circuit I/O. Connect a ceramic resonator or a
crystal oscillator between the XIN and XOUT pins.
To use an external clock, input it to the XIN pin
and leave the XOUT pin open.
INT interrupt
INT0, INT1, INT3
I
INT interrupt input pins
Key input interrupt
KI0 to KI3
I
Key input interrupt input pins
Timer X
CNTR0
I/O
Timer X I/O pin
CNTR0
O
Timer X output pin
Timer Z
TZOUT
O
Timer Z output pin
Timer C
TCIN
I
Timer C input pin
CMP0_0 to CMP0_2,
CMP1_0 to CMP1_2
O
Timer C output pins
CLK0
I/O
Transfer clock I/O pin
RXD0, RXD1
I
Serial data input pins
Serial interface
Symbol
TXD0, TXD1
O
Serial data output pins
Reference voltage
input
VREF
I
Reference voltage input pin to comparator
Comparator
AN8 to AN11
I/O port
P1_0 to P1_7, P3_3
to P3_5, P3_7, P4_5
Input port
P4_2, P4_6, P4_7
I: Input
O: Output
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
I
I/O
I
I/O: Input and output
Page 10 of 38
Analog input pins to comparator
CMOS I/O ports. Each port has an I/O select
direction register, allowing each pin in the port to
be directed for input or output individually.
Any port set to input can be set to use a pull-up
resistor or not by a program.
P1_0 to P1_3 also function as LED drive ports.
Input-only ports
R8C/18 Group, R8C/19 Group
Table 1.6
Pin
Number
1
2
3
4
5
6
7
8
9
1. Overview
Pin Name Information by Pin Number of PLSP0020JB-A, PRDP0020BA-A packages
Control
Pin
Port
Interrupt
P3_5
P3_7
RESET
XOUT
VSS/AVSS
XIN
VCC/AVCC
MODE
I/O Pin Functions for Peripheral Modules
Timer
Serial Interface
Comparator
CMP1_2
TXD1
CNTR0
P4_7
P4_6
P4_5
INT0
10
P1_7
INT10
CNTR00
11
12
P1_6
P1_5
INT11
CNTR01
13
14
P1_4
P1_3
KI3
TZOUT
AN11
15
P1_2
KI2
CMP0_2
AN10
P4_2
P1_1
KI1
CMP0_1
AN9
18
P1_0
KI0
CMP0_0
AN8
19
P3_3
INT3
TCIN/CMP1_0
20
P3_4
16
17
VREF
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 11 of 38
RXD1
CLK0
RXD0
TXD0
CMP1_1
R8C/18 Group, R8C/19 Group
Table 1.7
1. Overview
Pin Name Information by Pin Number of PWQN0028KA-B package
Pin
Number
1
Control
Pin
NC
2
XOUT
3
4
5
6
7
8
VSS/AVSS
NC
NC
XIN
NC
VCC/AVCC
9
MODE
Port
Interrupt
Comparator
P4_7
P4_6
10
P4_5
INT0
11
P1_7
INT10
12
P1_6
13
P1_5
14
P1_4
15
I/O Pin of Peripheral Function
Timer
Serial Interface
RXD1
CNTR00
CLK0
INT11
CNTR01
RXD0
TXD0
NC
16
P1_3
KI3
TZOUT
AN11
17
P1_2
KI2
CMP0_2
AN10
18
NC
19
NC
20
21
VREF
NC
P4_2
22
P1_1
KI1
CMP0_1
AN9
23
P1_0
KI0
CMP0_0
AN8
24
P3_3
INT3
TCIN/CMP1_0
25
26
P3_4
P3_5
CMP1_1
CMP1_2
27
P3_7
CNTR0
28
RESET
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 12 of 38
TXD1
R8C/18 Group, R8C/19 Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB
configure a register bank. There are two sets of register bank.
b31
b15
R2
R3
b8b7
b0
R0H (high-order of R0)
R0L (low-order of R0)
R1H (high-order of R1)
R1L (low-order of R1)
Data registers (1)
R2
R3
A0
A1
FB
b19
b15
Address registers (1)
Frame base register (1)
b0
Interrupt table register
INTBL
INTBH
The 4-high order bits of INTB are INTBH and
the 16-low bits of INTB are INTBL.
b19
b0
Program counter
PC
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
b8
IPL
b7
Flag register
b0
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
NOTE:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Registers
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 13 of 38
R8C/18 Group, R8C/19 Group
2.1
2. Central Processing Unit (CPU)
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0
can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data
registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a
32-bit data register (R2R0). R3R1 is analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing.
It is also used for transfer, arithmetic and logic operations. A1 is analogous to A0. A1 can be combined
with A0 and used as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide, indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch
between USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains a carry, borrow, or shift-out bits that have been generated by the arithmetic and logic
unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when the operation results in an overflow; otherwise to 0.
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 14 of 38
R8C/18 Group, R8C/19 Group
2.8.7
2. Central Processing Unit (CPU)
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is
set to 0 when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of
software interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
Rev.1.40 Apr 14, 2006
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Page 15 of 38
R8C/18 Group, R8C/19 Group
3.
3. Memory
Memory
3.1
R8C/18 Group
Figure 3.1 is a Memory Map of R8C/18 Group. The R8C/18 Group has 1 Mbyte of address space from
addresses 00000h to FFFFFh.
The internal ROM area is allocated lower addresses, beginning with address 0FFFFh. For example, a
16-Kbyte internal ROM is allocated addresses 0C000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting
address of each interrupt routine.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 1Kbyte internal RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only
for storing data but also for calling subroutines and as stacks when interrupt requests are
acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function
control registers are allocated here. All addresses within the SFR, which have nothing allocated are
reserved for future use and cannot be accessed by users.
00000h
SFR
(See 4. Special Function
Registers (SFRs))
002FFh
00400h
Internal RAM
0XXXXh
0FFDCh
0YYYYh
Internal ROM
0FFFFh
0FFFFh
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer • oscillation stop detection • voltage monitor 2
Address break
(Reserved)
Reset
Expanded area
FFFFFh
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Internal ROM
Part Number
Internal RAM
Size
Address 0YYYYh
Size
Address 0XXXXh
R5F21184SP, R5F21184DSP, R5F21184DD, R5F21184NP
R5F21183SP, R5F21183DSP, R5F21183DD, R5F21183NP
16 Kbytes
12 Kbytes
0C000h
0D000h
1 Kbyte
768 bytes
007FFh
006FFh
R5F21182SP, R5F21182DSP, R5F21182DD, R5F21182NP
8 Kbytes
0E000h
512 bytes
005FFh
R5F21181SP, R5F21181DSP, R5F21181DD
4 Kbytes
0F000h
384 bytes
0057Fh
Figure 3.1
Memory Map of R8C/18 Group
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 16 of 38
R8C/18 Group, R8C/19 Group
3.2
3. Memory
R8C/19 Group
Figure 3.2 is a Memory Map of R8C/19 Group. The R8C/19 group has 1 Mbyte of address space from
addresses 00000h to FFFFFh.
The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For
example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting
address of each interrupt routine.
The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 1Kbyte internal RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only
for storing data but also for calling subroutines and as stacks when interrupt requests are
acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function
control registers are allocated here. All addresses within the SFR, which have nothing allocated are
reserved for future use and cannot be accessed by users.
00000h
SFR
(See 4. Special Function
Registers (SFRs))
002FFh
00400h
Internal RAM
0XXXXh
02400h
Internal ROM
(data flash)(1)
02BFFh
0FFDCh
0YYYYh
Internal ROM
(program ROM)
0FFFFh
0FFFFh
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer • oscillation stop detection • voltage monitor 2
Address break
(Reserved)
Reset
Expanded area
FFFFFh
NOTES:
1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown.
2. The blank regions are reserved. Do not access locations in these regions.
Internal ROM
Part Number
Internal RAM
Size
Address 0YYYYh
Size
Address 0XXXXh
R5F21193SP, R5F21193DSP, R5F21193DD, R5F21193NP
16 Kbytes
12 Kbytes
0C000h
0D000h
1 Kbyte
768 bytes
007FFh
006FFh
R5F21192SP, R5F21192DSP, R5F21192DD, R5F21192NP
8 Kbytes
0E000h
512 bytes
005FFh
R5F21191SP, R5F21191DSP, R5F21191DD
4 Kbytes
0F000h
384 bytes
0057Fh
R5F21194SP, R5F21194DSP, R5F21194DD, R5F21194NP
Figure 3.2
Memory Map of R8C/19 Group
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 17 of 38
R8C/18 Group, R8C/19 Group
4.
4. Special Function Registers (SFRs)
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.4 list the
special function registers.
Table 4.1
SFR Information (1)(1)
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
Register
Symbol
After reset
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
PM0
PM1
CM0
CM1
00h
00h
01101000b
00100000b
Address Match Interrupt Enable Register
Protect Register
AIER
PRCR
00h
00h
Oscillation Stop Detection Register
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
Address Match Interrupt Register 0
OCD
WDTR
WDTS
WDC
RMAD0
00000100b
XXh
XXh
00011111b
00h
00h
X0h
Address Match Interrupt Register 1
RMAD1
00h
00h
X0h
Count Source Protection Mode Register
CSPR
00h
INT0 Input Filter Select Register
INT0F
00h
High-Speed On-Chip Oscillator Control Register 0
High-Speed On-Chip Oscillator Control Register 1
High-Speed On-Chip Oscillator Control Register 2
HRA0
HRA1
HRA2
00h
When shipping
00h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
Voltage Detection Register 1(2)
Voltage Detection Register 2(2)
VCA1
VCA2
00001000b
0033h
0034h
0035h
0036h
Voltage Monitor 1 Circuit Control Register (2)
VW1C
Voltage Monitor 2 Circuit Control Register (5)
VW2C
0000X000b(3)
0100X001b(4)
00h
001Fh
0020h
0021h
0022h
0023h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect this register.
3. After hardware reset.
4. After power-on reset or voltage monitor 1 reset.
5. Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect b2 and b3.
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 18 of 38
00h(3)
01000000b(4)
R8C/18 Group, R8C/19 Group
Table 4.2
Address
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
4. Special Function Registers (SFRs)
SFR Information (2)(1)
Register
Symbol
After reset
Key Input Interrupt Control Register
Comparator Conversion Interrupt Control Register
KUPIC
ADIC
XXXXX000b
XXXXX000b
Compare 1 Interrupt Control Register
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
CMP1IC
S0TIC
S0RIC
S1TIC
S1RIC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
Timer X Interrupt Control Register
TXIC
XXXXX000b
Timer Z Interrupt Control Register
TZIC
INT1IC
XXXXX000b
XXXXX000b
INT3IC
XXXXX000b
TCIC
CMP0IC
INT0IC
XXXXX000b
XXXXX000b
XX00X000b
INT1 Interrupt Control Register
INT3 Interrupt Control Register
Timer C Interrupt Control Register
Compare 0 Interrupt Control Register
INT0 Interrupt Control Register
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 19 of 38
R8C/18 Group, R8C/19 Group
Table 4.3
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
4. Special Function Registers (SFRs)
SFR Information (3)(1)
Register
Symbol
After reset
Timer Z Mode Register
TZMR
00h
Timer Z Waveform Output Control Register
Prescaler Z Register
Timer Z Secondary Register
Timer Z Primary Register
PUM
PREZ
TZSC
TZPR
00h
FFh
FFh
FFh
Timer Z Output Control Register
Timer X Mode Register
Prescaler X Register
Timer X Register
Timer Count Source Setting Register
TZOC
TXMR
PREX
TX
TCSS
00h
00h
FFh
FFh
00h
Timer C Register
TC
00h
00h
External Input Enable Register
INTEN
00h
Key Input Enable Register
KIEN
00h
Timer C Control Register 0
Timer C Control Register 1
Capture, Compare 0 Register
TCC0
TCC1
TM0
Compare 1 Register
TM1
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
UART0 Transmit Buffer Register
U0MR
U0BRG
U0TB
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Register
UART1 Transmit Buffer Register
U1MR
U1BRG
U1TB
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
UART1 Receive Buffer Register
U1C0
U1C1
U1RB
UART Transmit/Receive Control Register 2
UCON
00h
00h
00h
00h(2)
FFh
FFh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. When the output compare mode is selected (the TCC13 bit in the TCC1 register = 1), the value is set to FFFF16.
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 20 of 38
R8C/18 Group, R8C/19 Group
Table 4.4
Address
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
4. Special Function Registers (SFRs)
SFR Information (4)(1)
Register
Symbol
After reset
A/D Register
AD
XXh
A/D Control Register 2
ADCON2
00h
A/D Control Register 0
A/D Control Register 1
ADCON0
ADCON1
00000XXXb
00h
Port P1 Register
P1
XXh
Port P1 Direction Register
PD1
00h
Port P3 Register
P3
XXh
Port P3 Direction Register
Port P4 Register
PD3
P4
00h
XXh
Port P4 Direction Register
PD4
00h
Pull-Up Control Register 0
Pull-Up Control Register 1
Port P1 Drive Capacity Control Register
Timer C Output Control Register
PUR0
PUR1
DRR
TCOUT
00XX0000b
XXXXXX0Xb
00h
00h
01B3h
01B4h
01B5h
01B6h
01B7h
Flash Memory Control Register 4
FMR4
01000000b
Flash Memory Control Register 1
FMR1
1000000Xb
Flash Memory Control Register 0
FMR0
00000001b
0FFFFh
Optional Function Select Register
OFS
(Note 2)
X: Undefined
NOTES:
1. The blank regions, 0100h to 01B2h and 01B8h to 02FFh are all reserved. Do not access locations in these regions.
2. The OFS register cannot be changed by a program. Use a flash programmer to write to it.
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 21 of 38
R8C/18 Group, R8C/19 Group
5.
5. Electrical Characteristics
Electrical Characteristics
Table 5.1
Absolute Maximum Ratings
Rated Value
Unit
VCC
Symbol
Supply voltage
Parameter
VCC = AVCC
Condition
-0.3 to 6.5
V
AVCC
Analog supply voltage
VCC = AVCC
-0.3 to 6.5
V
V
VI
Input voltage
-0.3 to VCC+0.3
VO
Output voltage
-0.3 to VCC+0.3
V
Pd
Power dissipation
300
mW
Topr
Operating ambient temperature
-20 to 85 / -40 to 85 (D version)
°C
Tstg
Storage temperature
-65 to 150
°C
Table 5.2
Topr = 25°C
Recommended Operating Conditions
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
VCC
Supply voltage
2.7
−
5.5
AVCC
Analog supply voltage
−
VCC
−
V
VSS
Supply voltage
−
0
−
V
AVSS
Analog supply voltage
−
0
−
V
VIH
Input “H” voltage
0.8VCC
−
VCC
V
VIL
Input “L” voltage
0
−
0.2VCC
V
IOH(sum)
Peak sum output
“H” current
−
−
-60
mA
IOH(peak)
Peak output “H” current
−
−
-10
mA
IOH(avg)
Average output “H” current
−
−
-5
mA
IOL(sum)
Peak sum output
“L” currents
Sum of all
pins IOL (peak)
−
−
60
mA
IOL(peak)
Peak output “L”
currents
Except P1_0 to P1_3
IOL(avg)
f(XIN)
Average output
“L” current
Sum of all
pins IOH (peak)
P1_0 to P1_3
−
−
10
mA
Drive capacity HIGH
−
−
30
mA
Drive capacity LOW
−
−
10
mA
−
−
5
mA
Drive capacity HIGH
−
−
15
mA
Drive capacity LOW
−
−
5
mA
Except P1_0 to P1_3
P1_0 to P1_3
Main clock input oscillation frequency
3.0 V ≤ VCC ≤ 5.5 V
0
−
20
MHz
2.7 V ≤ VCC < 3.0 V
0
−
10
MHz
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -20 to 85 °C / -40 to 85 °C, unless otherwise specified.
2. Typical values when average output current is 100 ms.
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 22 of 38
V
R8C/18 Group, R8C/19 Group
Table 5.3
5. Electrical Characteristics
Comparator Characteristics
Symbol
Parameter
Conditions
−
Resolution
−
Absolute accuracy
φAD = 10 MHz(3)
tconv
Conversion time
φAD = 10 MHz(3)
Vref
Reference voltage
VIA
Analog input voltage
−
Comparator conversion operating clock
frequency(2)
Standard
Min.
Typ.
Max.
Unit
−
−
1
Bit
−
−
±20
mV
1
−
−
µs
0
−
AVCC
V
0
−
AVCC
V
1
−
10
MHz
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -20 to 85 °C / -40 to 85 °C, unless otherwise specified.
2. If f1 exceeds 10 MHz, divided f1 and ensure the comparator conversion operating clock frequency (φAD) is 10 MHz or below.
3. If AVcc is less than 4.2 V, divided f1 and ensure the comparator conversion operating clock frequency (φAD) is f1/2 or below.
P1
P3
P4
Figure 5.1
Port P1, P3, and P4 Measurement Circuit
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 23 of 38
30pF
R8C/18 Group, R8C/19 Group
Table 5.4
Flash Memory (Program ROM) Electrical Characteristics
Symbol
−
5. Electrical Characteristics
Parameter
Program/erase endurance(2)
Conditions
Standard
Unit
Min.
Typ.
Max.
R8C/18 Group
100(3)
−
−
times
R8C/19 Group
1,000(3)
−
−
times
µs
−
Byte program time
−
50
400
−
Block erase time
−
0.4
9
s
td(SR-SUS)
Time delay from suspend request until
suspend
−
−
97+CPU clock
× 6 cycles
µs
−
Interval from erase start/restart until
following suspend request
650
−
−
µs
−
Interval from program start/restart until
following suspend request
0
−
−
ns
−
Time from suspend until program/erase
restart
−
−
3+CPU clock
× 4 cycles
µs
−
Program, erase voltage
2.7
−
5.5
V
−
Read voltage
2.7
−
5.5
V
−
Program, erase temperature
0
−
60
°C
−
Data hold time(8)
20
−
−
year
Ambient temperature = 55 °C
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60 °C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting
prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. If emergency processing is required, a suspend request can be generated independent of this characteristic. In that case the
normal time delay to Suspend can be applied to the request.However, we recommend that a suspend request with an interval
of less than 650 µs is only used once because, if the suspend state continues, erasure cannot operate and the incidence of
erasure error rises.
5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. In addition, averaging the number of erase operations between block A and block B
can further reduce the effective number of rewrites. It is also advisable to retain data on the erase count of each block and
limit the number of erase operations to a certain number.
6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
7. Customers desiring programming/erasure failure rate information should contact their Renesas technical support
representative.
8. The data hold time includes time that the power supply is off or the clock is not supplied.
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 24 of 38
R8C/18 Group, R8C/19 Group
Table 5.5
5. Electrical Characteristics
Flash Memory (Data flash Block A, Block B) Electrical Characteristics
Symbol
Parameter
Standard
Conditions
Min.
Typ.
Unit
Max.
10,000(3)
−
−
times
Byte program time
(Program/erase endurance ≤ 1,000 times)
−
50
400
µs
−
Byte program time
(Program/erase endurance > 1,000 times)
−
65
−
µs
−
Block erase time
(Program/erase endurance ≤ 1,000 times)
−
0.2
9
s
−
Block erase time
(Program/erase endurance > 1,000 times)
−
0.3
−
s
td(SR-SUS)
Time delay from suspend request until
suspend
−
−
97+CPU clock
× 6 cycles
µs
−
Interval from erase start/restart until
following suspend request
650
−
−
µs
−
Interval from program start/restart until
following suspend request
0
−
−
ns
−
Time from suspend until program/erase
restart
−
−
3+CPU clock
× 4 cycles
µs
−
Program, erase voltage
2.7
−
5.5
V
−
Read voltage
2.7
−
5.5
V
−
Program, erase temperature
-20(8)
−
85
°C
−
Data hold time(9)
20
−
−
year
−
Program/erase endurance(2)
−
Ambient temperature = 55 °C
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -20 to 85 °C / -40 to 85 °C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting
prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. If emergency processing is required, a suspend request can be generated independent of this characteristic. In that case the
normal time delay to suspend can be applied to the request. However, we recommend that a suspend request with an interval
of less than 650 µs is only used once because, if the suspend state continues, erasure cannot operate and the incidence of
erasure error rises.
5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
7. Customers desiring programming/erasure failure rate information should contact their Renesas technical support
representative.
8. -40 °C for D version.
9. The data hold time includes time that the power supply is off or the clock is not supplied.
Suspend request
(Maskable interrupt request)
FMR46
Fixed time (97 µs)
Clock-dependent
time
td(SR-SUS)
Figure 5.2
Transition Time to Suspend
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 25 of 38
Access restart
R8C/18 Group, R8C/19 Group
Table 5.6
5. Electrical Characteristics
Voltage Detection 1 Circuit Electrical Characteristics
Symbol
Parameter
Vdet1
Voltage detection level(3)
−
Voltage detection circuit self power consumption
td(E-A)
Waiting time until voltage detection circuit operation
starts(2)
Vccmin
MCU operating voltage minimum value
Condition
VCA26 = 1, VCC = 5.0 V
Standard
Unit
Min.
Typ.
Max.
2.70
2.85
3.00
V
−
600
−
nA
−
−
100
µs
2.7
−
−
V
NOTES:
1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = -40°C to 85 °C.
2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
3. Ensure that Vdet2 > Vdet1.
Table 5.7
Voltage Detection 2 Circuit Electrical Characteristics
Symbol
Parameter
Vdet2
Voltage detection level(4)
−
Voltage monitor 2 interrupt request generation time(2)
−
Voltage detection circuit self power consumption
td(E-A)
Waiting time until voltage detection circuit operation
starts(3)
Condition
VCA27 = 1, VCC = 5.0 V
Standard
Unit
Min.
Typ.
Max.
3.00
3.30
3.60
V
−
40
−
µs
−
600
−
nA
−
−
100
µs
NOTES:
1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = -40°C to 85 °C.
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet1.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
4. Ensure that Vdet2 > Vdet1.
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 26 of 38
R8C/18 Group, R8C/19 Group
Table 5.8
5. Electrical Characteristics
Reset Circuit Electrical Characteristics (When Using Voltage Monitor 1 Reset)
Symbol
Parameter
Condition
Standard
Min.
Power-on reset valid voltage
Vpor2
tw(Vpor2-Vdet1) Supply voltage rising time when power-on reset is
deasserted(1)
Unit
Typ.
Max.
-20°C ≤ Topr ≤ 85°C
−
−
Vdet1
V
-20°C ≤ Topr ≤ 85°C,
tw(por2) ≥ 0s(3)
−
−
100
ms
NOTES:
1. This condition is not applicable when using with Vcc ≥ 1.0 V.
2. When turning power on after the time to hold the external power below effective voltage (Vpor1) exceeds10 s, refer to Table
5.9 Reset Circuit Electrical Characteristics (When Not Using Voltage Monitor 1 Reset).
3. tw(por2) is the time to hold the external power below effective voltage (Vpor2).
Table 5.9
Reset Circuit Electrical Characteristics (When Not Using Voltage Monitor 1 Reset)
Symbol
Parameter
Condition
Standard
Min.
Typ.
Unit
Max.
Vpor1
Power-on reset valid voltage
-20°C ≤ Topr ≤ 85°C
−
−
0.1
V
tw(Vpor1-Vdet1)
Supply voltage rising time when power-on reset is
deasserted
0°C ≤ Topr ≤ 85°C,
tw(por1) ≥ 10 s(2)
−
−
100
ms
tw(Vpor1-Vdet1)
Supply voltage rising time when power-on reset is
deasserted
-20°C ≤ Topr < 0°C,
tw(por1) ≥ 30 s(2)
−
−
100
ms
tw(Vpor1-Vdet1)
Supply voltage rising time when power-on reset is
deasserted
-20°C ≤ Topr < 0°C,
tw(por1) ≥ 10 s(2)
−
−
1
ms
tw(Vpor1-Vdet1)
Supply voltage rising time when power-on reset is
deasserted
0°C ≤ Topr ≤ 85°C,
tw(por1) ≥ 1 s(2)
−
−
0.5
ms
NOTES:
1. When not using voltage monitor 1, use with Vcc ≥ 2.7 V.
2. tw(por1) is the time to hold the external power below effective voltage (Vpor1).
Vdet1(3)
Vdet1(3)
Vccmin
Vpor2
Vpor1
tw(por1)
Sampling time(1, 2)
tw(Vpor1–Vdet1)
tw(por2) tw(Vpor2–Vdet1)
Internal
reset signal
(“L” valid)
1
× 32
fRING-S
1
× 32
fRING-S
NOTES:
1. Hold the voltage inside the MCU operation voltage range (Vccmin or above) within the sampling time.
2. The sampling clock can be selected. Refer to 7. Voltage Detection Circuit for details.
3. Vdet1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 7. Voltage Detection Circuit for details.
Figure 5.3
Reset Circuit Electrical Characteristics
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 27 of 38
R8C/18 Group, R8C/19 Group
Table 5.10
5. Electrical Characteristics
High-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
−
High-speed on-chip oscillator frequency when the
reset is deasserted
VCC = 5.0 V, Topr = 25 °C
−
8
−
MHz
−
High-speed on-chip oscillator frequency temperature
supply voltage dependence(2)
0 to +60 °C/5 V ± 5 %(3)
7.76
−
8.24
MHz
-20 to +85 °C/2.7 to 5.5 V(3)
7.68
−
8.32
MHz
-40 to +85 °C/2.7 to 5.5 V(3)
7.44
−
8.32
MHz
NOTES:
1. The measurement condition is VCC = 5.0 V and Topr = 25 °C.
2. Refer to 10.6.4 High-Speed On-Chip Oscillator Clock for notes on high-speed on-chip oscillator clock.
3. The standard value shows when the HRA1 register is assumed as the value in shipping and the HRA2 register value is set to
00h.
Table 5.11
Power Supply Circuit Timing Characteristics
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
td(P-R)
Time for internal power supply stabilization during
power-on(2)
1
−
2000
µs
td(R-S)
STOP exit time(3)
−
−
150
µs
NOTES:
1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = 25 °C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
3. Time until CPU clock supply starts after the interrupt is acknowledged to exit stop mode.
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 28 of 38
R8C/18 Group, R8C/19 Group
Table 5.12
Electrical Characteristics (1) [VCC = 5 V]
Symbol
VOH
5. Electrical Characteristics
Parameter
Output “H” voltage
Except XOUT
XOUT
VOL
Output “L” voltage
Condition
Standard
Unit
Min.
Typ.
Max.
IOH = -5 mA
VCC − 2.0
−
VCC
V
IOH = -200 µA
VCC − 0.3
−
VCC
V
Drive capacity
HIGH
IOH = -1 mA
VCC − 2.0
−
VCC
V
Drive capacity
LOW
IOH = -500 µA
VCC − 2.0
−
VCC
V
Except P1_0 to
P1_3, XOUT
IOL = 5 mA
−
−
2.0
V
IOL = 200 µA
−
−
0.45
V
P1_0 to P1_3
Drive capacity
HIGH
IOL = 15 mA
−
−
2.0
V
Drive capacity
LOW
IOL = 5 mA
−
−
2.0
V
Drive capacity
LOW
IOL = 200 µA
−
−
0.45
V
Drive capacity
HIGH
IOL = 1 mA
−
−
2.0
V
Drive capacity
LOW
IOL = 500 µA
−
−
2.0
V
0.2
−
1.0
V
0.2
−
2.2
V
−
−
5.0
µA
XOUT
VT+-VT-
Hysteresis
IIH
Input “H” current
VI = 5 V
IIL
Input “L” current
VI = 0 V
−
−
-5.0
µA
VI = 0 V
30
50
167
kΩ
INT0, INT1, INT2,
INT3, KI0, KI1, KI2,
KI3, CNTR0,
CNTR1, TCIN,
RXD0
RESET
RPULLUP Pull-up resistance
RfXIN
Feedback resistance
fRING-S
Low-speed on-chip oscillator frequency
XIN
VRAM
RAM hold voltage
During stop mode
−
1.0
−
MΩ
40
125
250
kHz
2.0
−
−
V
NOTE:
1. VCC = 4.2 to 5.5 V at Topr = -20 to 85 °C / -40 to 85 °C, f(XIN) = 20 MHz, unless otherwise specified.
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 29 of 38
R8C/18 Group, R8C/19 Group
Table 5.13
Symbol
ICC
5. Electrical Characteristics
Electrical Characteristics (2) [Vcc = 5 V] (Topr = -40 to 85 °C, unless otherwise specified.)
Parameter
Condition
Unit
Typ.
Max.
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−
9
15
mA
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−
8
14
mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−
5
−
mA
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−
4
−
mA
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−
3
−
mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−
2
−
mA
Main clock off
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
−
4
8
mA
Main clock off
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−
1.5
−
mA
Low-speed
on-chip
oscillator
mode
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
FMR47 = 1
−
110
300
µA
Wait mode
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = 0
−
40
80
µA
Wait mode
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = 0
−
38
76
µA
Stop mode
Main clock off, Topr = 25 °C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = 0
−
0.8
3.0
µA
Power supply current High-speed
mode
(VCC = 3.3 to 5.5 V)
Single-chip mode,
output pins are open,
other pins are VSS,
comparator is
stopped
Mediumspeed mode
High-speed
on-chip
oscillator
mode
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Standard
Min.
Page 30 of 38
R8C/18 Group, R8C/19 Group
5. Electrical Characteristics
Timing Requirements
(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Ta = 25 °C) [VCC = 5 V]
Table 5.14
XIN Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(XIN)
XIN input cycle time
50
−
ns
tWH(XIN)
XIN input “H” width
25
−
ns
tWL(XIN)
XIN input “L” width
25
−
ns
VCC = 5 V
tc(XIN)
tWH(XIN)
XIN input
tWL(XIN)
Figure 5.4
Table 5.15
XIN Input Timing Diagram when VCC = 5 V
CNTR0 Input, CNTR1 Input, INT1 Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(CNTR0)
CNTR0 input cycle time
100
−
ns
tWH(CNTR0)
CNTR0 input “H” width
40
−
ns
tWL(CNTR0)
CNTR0 input “L” width
40
−
ns
VCC = 5 V
tc(CNTR0)
tWH(CNTR0)
CNTR0 input
tWL(CNTR0)
Figure 5.5
Table 5.16
CNTR0 Input, CNTR1 Input, INT1 Input Timing Diagram when VCC = 5 V
TCIN Input, INT3 Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TCIN)
TCIN input cycle time
400(1)
−
ns
tWH(TCIN)
TCIN input “H” width
200(2)
−
ns
tWL(TCIN)
TCIN input “L” width
200(2)
−
ns
NOTES:
1. When using timer C input capture mode, adjust the cycle time to (1/timer C count source frequency x 3) or above.
2. When using timer C input capture mode, adjust the pulse width to (1/timer C count source frequency x 1.5) or above.
VCC = 5 V
tc(TCIN)
tWH(TCIN)
TCIN input
tWL(TCIN)
Figure 5.6
TCIN Input, INT3 Input Timing Diagram when VCC = 5 V
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 31 of 38
R8C/18 Group, R8C/19 Group
Table 5.17
5. Electrical Characteristics
Serial Interface
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
200
−
ns
tW(CKH)
CLKi input “H” width
100
−
ns
tW(CKL)
CLKi input “L” width
100
−
ns
td(C-Q)
TXDi output delay time
−
50
ns
th(C-Q)
TXDi hold time
0
−
ns
tsu(D-C)
RXDi input setup time
50
−
ns
th(C-D)
RXDi input hold time
90
−
ns
i = 0 or 1
VCC = 5 V
tc(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TxDi
td(C-Q)
tsu(D-C)
th(C-D)
RxDi
Figure 5.7
Table 5.18
Serial Interface Timing Diagram when VCC = 5 V
External Interrupt INT0 Input
Symbol
tW(INH)
tW(INL)
Standard
Parameter
Unit
Min.
Max.
INT0 input “H” width
250(1)
−
ns
INT0 input “L” width
250(2)
−
ns
NOTES:
1. When selecting the digital filter by the INT0 input filter select bit, use an INT0 input HIGH width of either (1/digital filter clock
frequency x 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INT0 input filter select bit, use an INT0 input LOW width of either (1/digital filter clock
frequency x 3) or the minimum value of standard, whichever is greater.
VCC = 5 V
tW(INL)
INT0 input
tW(INH)
Figure 5.8
External Interrupt INT0 Input Timing Diagram when VCC = 5 V
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 32 of 38
R8C/18 Group, R8C/19 Group
Table 5.19
Electrical Characteristics (3) [VCC = 3V]
Symbol
VOH
VOL
5. Electrical Characteristics
Parameter
Output “H” voltage
Output “L” voltage
Hysteresis
Standard
Min.
Typ.
Max.
Unit
Except XOUT
IOH = -1 mA
VCC − 0.5
−
VCC
V
XOUT
Drive capacity
HIGH
IOH = -0.1 mA
VCC − 0.5
−
VCC
V
Drive capacity
LOW
IOH = -50 µA
VCC − 0.5
−
VCC
V
−
−
0.5
V
Except P1_0 to
P1_3, XOUT
IOL = 1mA
P1_0 to P1_3
Drive capacity
HIGH
IOL = 2 mA
−
−
0.5
V
Drive capacity
LOW
IOL = 1 mA
−
−
0.5
V
Drive capacity
HIGH
IOL = 0.1 mA
−
−
0.5
V
Drive capacity
LOW
IOL = 50 µA
−
−
0.5
V
INT0, INT1, INT2,
INT3, KI0, KI1, KI2,
KI3, CNTR0,
CNTR1, TCIN,
RXD0
0.2
−
0.8
V
RESET
0.2
−
1.8
V
µA
XOUT
VT+-VT-
Condition
IIH
Input “H” current
VI = 3 V
−
−
4.0
IIL
Input “L” current
VI = 0 V
−
−
-4.0
µA
VI = 0 V
66
160
500
kΩ
RPULLUP Pull-up resistance
RfXIN
Feedback resistance
fRING-S
Low-speed on-chip oscillator frequency
XIN
VRAM
RAM hold voltage
During stop mode
−
3.0
−
MΩ
40
125
250
kHz
2.0
−
−
V
NOTE:
1. VCC = 2.7 to 3.3 V at Topr = -20 to 85 °C / -40 to 85 °C, f(XIN) = 10 MHz, unless otherwise specified.
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 33 of 38
R8C/18 Group, R8C/19 Group
Table 5.20
Symbol
ICC
5. Electrical Characteristics
Electrical Characteristics (4) [Vcc = 3V] (Topr = -40 to 85 °C, unless otherwise specified.)
Parameter
Condition
Unit
Typ.
Max.
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−
8
13
mA
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−
7
12
mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−
5
−
mA
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−
3
−
mA
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−
2.5
−
mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−
1.6
−
mA
Main clock off
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
−
3.5
7.5
mA
Main clock off
High-speed on-chip oscillator on = 8 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−
1.5
−
mA
Low-speed
on-chip
oscillator
mode
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
FMR47 = 1
−
100
280
µA
Wait mode
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = 0
−
37
74
µA
Wait mode
Main clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = 0
−
35
70
µA
Stop mode
Main clock off, Topr = 25 °C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = 0
−
0.7
3.0
µA
Power supply current High-speed
mode
(VCC = 2.7 to 3.3 V)
Single-chip mode,
output pins are open,
other pins are VSS,
comparator is
stopped
Mediumspeed mode
High-speed
on-chip
oscillator
mode
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Standard
Min.
Page 34 of 38
R8C/18 Group, R8C/19 Group
5. Electrical Characteristics
Timing requirements
(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Ta = 25 °C) [VCC = 3 V]
Table 5.21
XIN Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(XIN)
XIN input cycle time
100
−
ns
tWH(XIN)
XIN input “H” width
40
−
ns
tWL(XIN)
XIN input “L” width
40
−
ns
VCC = 3 V
tc(XIN)
tWH(XIN)
XIN input
tWL(XIN)
Figure 5.9
Table 5.22
XIN Input Timing Diagram when VCC = 3 V
CNTR0 Input, CNTR1 Input, INT1 Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(CNTR0)
CNTR0 input cycle time
300
−
ns
tWH(CNTR0)
CNTR0 input “H” width
120
−
ns
tWL(CNTR0)
CNTR0 input “L” width
120
−
ns
VCC = 3 V
tc(CNTR0)
tWH(CNTR0)
CNTR0 input
tWL(CNTR0)
Figure 5.10
Table 5.23
CNTR0 Input, CNTR1 Input, INT1 Input Timing Diagram when VCC = 3 V
TCIN Input, INT3 Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TCIN)
TCIN input cycle time
1,200(1)
−
ns
tWH(TCIN)
TCIN input “H” width
600(2)
−
ns
tWL(TCIN)
TCIN input “L” width
600(2)
−
ns
NOTES:
1. When using the timer C input capture mode, adjust the cycle time to (1/timer C count source frequency × 3) or above.
2. When using the timer C input capture mode, adjust the width to (1/timer C count source frequency × 1.5) or above.
VCC = 3 V
tc(TCIN)
tWH(TCIN)
TCIN input
tWL(TCIN)
Figure 5.11
TCIN Input, INT3 Input Timing Diagram when VCC = 3 V
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 35 of 38
R8C/18 Group, R8C/19 Group
Table 5.24
5. Electrical Characteristics
Serial Interface
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
300
−
ns
tW(CKH)
CLKi input “H” width
150
−
ns
tW(CKL)
CLKi input “L” width
150
−
ns
td(C-Q)
TXDi output delay time
−
80
ns
th(C-Q)
TXDi hold time
0
−
ns
tsu(D-C)
RXDi input setup time
70
−
ns
th(C-D)
RXDi input hold time
90
−
ns
i = 0 or 1
VCC = 3 V
tc(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TxDi
td(C-Q)
tsu(D-C)
th(C-D)
RxDi
Figure 5.12
Table 5.25
Serial Interface Timing Diagram when VCC = 3 V
External Interrupt INT0 Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tW(INH)
INT0 input “H” width
380(1)
−
ns
tW(INL)
INT0 input “L” width
380(2)
−
ns
NOTES:
1. When selecting the digital filter by the INT0 input filter select bit, use an INT0 input HIGH width of either (1/digital filter clock
frequency x 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INT0 input filter select bit, use an INT0 input LOW width of either (1/digital filter clock
frequency x 3) or the minimum value of standard, whichever is greater.
VCC = 3 V
tW(INL)
INTi input
tW(INH)
Figure 5.13
External Interrupt INT0 Input Timing Diagram when VCC = 3 V
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 36 of 38
R8C/18 Group, R8C/19 Group
Package Dimensions
Package Dimensions
JEITA Package Code
P-LSSOP20-4.4x6.5-0.65
RENESAS Code
PLSP0020JB-A
Previous Code
20P2F-A
11
*1
E
20
HE
MASS[Typ.]
0.1g
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
F
1
10
Index mark
c
A1
Reference
Symbol
D
D
E
A2
A
A1
bp
c
A
L
*2
A2
*3
e
bp
Detail F
y
HE
e
y
L
RENESAS Code
PRDP0020BA-A
Previous Code
20P4B
Min
6.4
4.3
Nom Max
6.5 6.6
4.4 4.5
1.15
1.45
0.1 0.2
0
0.17 0.22 0.32
0.13 0.15 0.2
0°
10°
6.2 6.4 6.6
0.53 0.65 0.77
0.10
0.3 0.5 0.7
MASS[Typ.]
1.0g
11
1
10
c
*1
E
20
e1
JEITA Package Code
P-SDIP20-6.3x19-1.78
Dimension in Millimeters
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
D
A
A2
*2
L
A1
Reference
Symbol
*3 b
3
e
SEATING PLANE
bp
e1
D
E
A
A1
A2
bp
b3
c
e
L
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 37 of 38
Dimension in Millimeters
Min Nom Max
7.32 7.62 7.92
18.8 19.0 19.2
6.15 6.3 6.45
4.5
0.51
3.3
0.38 0.48 0.58
0.9 1.0 1.3
0.22 0.27 0.34
0°
15°
1.528 1.778 2.028
3.0
R8C/18 Group, R8C/19 Group
Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS[Typ.]
P-HWQFN28-5x5-0.50
PWQN0028KA-B
28PJW-B
0.05g
D
15
21
22
21
15
14
14
22
E1
E
D2
Lp
7
7
1
28
8
8
28
1
e
bp
x
Reference
Symbol
F
Dimension in Millimeters
Min
Nom
Max
D
4.9
5.0
5.1
E
4.9
5.0
5.1
A2
0.75
A
A2
A
y
0.8
A1
0
bp
0.15
A1
e
Detail F
Rev.1.40 Apr 14, 2006
REJ03B0124-0140
Page 38 of 38
Lp
0
0.05
0.2
0.25
0.5
0.5
0.6
0.7
x
0.05
y
0.05
D2
2.0
E1
2.0
REVISION HISTORY
R8C/18 Group, R8C/19 Group Datasheet
Description
Rev.
Date
0.10
Nov 15, 2004
−
0.20
Jan 11, 2005
5, 6
Tables 1.3 and 1.4: The date updated
0.21
Apr 04, 2005
2, 3
Tables 1.1 and 1.2: Partly revised
Page
4
1.00
May 27, 2005
Summary
First Edition issued
Figure 1.1: Partly revised
5, 6
Tables 1.3 and 1.4: Partly revised
5, 6
Figure 1.2 and 1.3: Partly revised
7, 8
Figure 1.4 and 1.5: Partly revised
10
Table 1.6: Partly revised
16
Table 4.1: Partly revised
17
Table 4.2: Partly revised
18
Table 4.3: Partly revised
20
Package Dimensions are revised
5, 6
Tables 1.3 and 1.4: Partly revised
9
Table 1.5: Partly revised
25
Table 5.9: Revised
26
Table 5.10: Partly revised
28
Table 5.13: Partly revised
32
Table 5.20: Partly revised
1.10
Jun 09, 2005
26
Table 5.10: Partly revised
1.20
Nov 01, 2005
3
Table 1.2 Performance Outline of the R8C/19 Group;
Flash Memory: (Data area) → (Data flash)
(Program area) → (Program ROM) revised
4
Figure 1.1 Block Diagram;
“Peripheral Function” added,
“System Clock Generation” → “System Clock Generator” revised
6
Table 1.4 Product Information of R8C/19 Group;
ROM capacity: “Program area” → “Program ROM”,
“Data area” → “Data flash” revised
9
Table 1.5 Pin Description;
Power Supply Input: “VCC/AVCC” → “VCC”,
“VSS/AVSS” → “VSS” revised
Analog Power Supply Input: added
11
Figure 2.1 CPU Register;
“Reserved Area” → “Reserved Bit” revised
13
2.8.10 Reserved Area;
“Reserved Area” → “Reserved Bit” revised
15
3.2 R8C/19 Group, Figure 3.2 Memory Map of R8C/19 Group;
“Data area” → “Data flash”,
“Program area” → “Program ROM” revised
A-1
REVISION HISTORY
Rev.
Date
1.20
Nov 01, 2005
1.30
Dec 16, 2005
R8C/18 Group, R8C/19 Group Datasheet
Description
Page
Summary
16
Table 4.1 SFR Information(1);
0009h: “XXXXXX00b” → “00h”
000Ah: “00XXX000b” → “00h”
001Eh: “XXXXX000b” → “00h” revised
18
Table 4.3 SFR Information(3);
0085h:
“Prescaler Z” → “Prescaler Z Register”
0086h:
“Timer Z Secondary” → “Timer Z Secondary Register”
0087h:
“Timer Z Primary” → “Timer Z Primary Register”
008Ch:
“Prescaler X” → “Prescaler X Register”
008Dh:
“Timer X” → “Timer X Register”
0090h, 0091h: “Timer C” → “Timer C Register” revised
22
Table 5.4 Flash Memory (Program ROM) Electrical Characteristics;
NOTES 3 and 5 revised, NOTE8 deleted
23
Table 5.5 Flash Memory (Data flash Block A, Block B) Electrical
Characteristics; NOTES 1 and 3 revised
25
Table 5.8 Reset Circuit Electrical Characteristics (When Using Voltage
Monitor 1 Reset); NOTE 2 revised
26
Table 5.10 High-speed On-Chip Oscillator Circuit Electrical
Characteristics;
“High-Speed On-Chip Oscillator ...” →
“High-Speed On-Chip Oscillator Frequency ...” revised
NOTE 2, 3 added
28
Table 5.13 Electrical Characteristics (2) [Vcc = 5V];
NOTE 1 deleted
32
Table 5.20 Electrical Characteristics (4) [Vcc = 3V];
NOTE 1 deleted
−
Products of PWQN0028KA-B package included
5, 6
Table 1.3, Table 1.4 revised
24
Table 5.4 Flash Memory (Program ROM) Electrical Characteristics;
Ta → Ambient temperature
25
Table 5.5 Flash Memory (Data flash Block A, Block B) Electrical
Characteristics; Ta → Ambient temperature
30, 34 Table 5.13, Table 5.20; The title revised, Condition of Stop Mode added
32, 36 Table 5.17, Table 5.24; td(C-Q) and tsu(D-C) revised
37, 38 Package Dimensions revised
1.40
Apr 14, 2006
2, 3
Table 1.1, Table 1.2;
Interrupts: Internal 8 → 10 sources,
5, 6
Table 1.3, Table 1.4; Type No. added, deleted
16, 17 Figure 3.1, Figure 3.2; Part Number added, deleted
24, 25 Table 5.4, Table 5.5;
Conditions: VCC = 5.0 V at Topr = 25 °C deleted
A-2
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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