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REJ09B0349-0100 16 R8C/2E Group, R8C/2F Group Hardware Manual RENESAS MCU R8C FAMILY / R8C/2x SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com). Rev.1.00 Revision Date: Dec 14, 2007 w ww.renesas.com Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.  The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.  The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.  The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.  When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems.  The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products. How to Use This Manual 1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual. The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral functions, and electrical characteristics; and usage notes. Particular attention should be paid to the precautionary notes when using the manual. These notes occur within the body of the text, at the end of each section, and in the Usage Notes section. The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer to the text of the manual for details. The following documents apply to the R8C/2E Group, R8C/2F Group. Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site. Description Document Title Document No. Hardware overview and electrical characteristics R8C/2E, R8C/2F REJ03B0222 Group Datasheet This hardware R8C/2E Group, Hardware manual Hardware specifications (pin assignments, manual R8C/2F Group memory maps, peripheral function Hardware Manual specifications, electrical characteristics, timing charts) and operation description Note: Refer to the application notes for details on using peripheral functions. Software manual Description of CPU instruction set R8C/Tiny Series REJ09B0001 Software Manual Available from Renesas Application note Information on using peripheral functions and Technology Web site. application examples Sample programs Information on writing programs in assembly language and C Renesas Product specifications, updates on documents, technical update etc. Document Type Datasheet 2. Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word “register,” “bit,” or “pin” to distinguish the three categories. Examples the PM03 bit in the PM0 register P3_5 pin, VCC pin Notation of Numbers The indication “b” is appended to numeric values given in binary format. However, nothing is appended to the values of single bits. The indication “h” is appended to numeric values given in hexadecimal format. Nothing is appended to numeric values given in decimal format. Examples Binary: 11b Hexadecimal: EFA0h Decimal: 1234 (2) 3. Register Notation The symbols and terms used in register diagrams are described below. XXX Register b7 b6 b5 b4 b3 b2 b1 b0 *1 Symbol XXX Address XXX After Reset 00h 0 Bit Symbol XXX0 Bit Name XXX bits b1 b0 Function 1 0: XXX 0 1: XXX 1 0: Do not set. 1 1: XXX RW RW *2 XXX1 RW (b2) Nothing is assigned. If necessary, set to 0. When read, the content is undefined. *3 RW (b3) Reserved bits Set to 0. *4 XXX4 XXX bits Function varies according to the operating mode. RW XXX5 WO XXX6 0: XXX 1: XXX RW XXX7 XXX bit RO *1 Blank: Set to 0 or 1 according to the application. 0: Set to 0. 1: Set to 1. X: Nothing is assigned. *2 RW: Read and write. RO: Read only. WO: Write only. −: Nothing is assigned. *3 • Reserved bit Reserved bit. Set to specified value. *4 • Nothing is assigned Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0. • Do not set to a value Operation is not guaranteed when a value is set. • Function varies according to the operating mode. The function of the bit varies with the peripheral function mode. Refer to the register diagram for information on the individual modes. 4. List of Abbreviations and Acronyms Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SFR SIM UART VCO Full Form Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access Direct Memory Access Controller Global System for Mobile Communications High Impedance Inter Equipment Bus Input / Output Infrared Data Association Least Significant Bit Most Significant Bit Non-Connect Phase Locked Loop Pulse Width Modulation Special Function Registers Subscriber Identity Module Universal Asynchronous Receiver / Transmitter Voltage Controlled Oscillator All trademarks and registered trademarks are the property of their respective owners. Table of Contents SFR Page Reference ........................................................................................................................... B - 1 1. Overview ......................................................................................................................................... 1 1.1 1.1.1 1.1.2 1.2 1.3 1.4 1.5 2. Features ..................................................................................................................................................... 1 Applications .......................................................................................................................................... 1 Specifications ........................................................................................................................................ 2 Product List ............................................................................................................................................... 6 Block Diagram ......................................................................................................................................... 8 Pin Assignment .......................................................................................................................................... 9 Pin Functions ........................................................................................................................................... 11 Central Processing Unit (CPU) ..................................................................................................... 12 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.8.1 2.8.2 2.8.3 2.8.4 2.8.5 2.8.6 2.8.7 2.8.8 2.8.9 2.8.10 Data Registers (R0, R1, R2, and R3) ...................................................................................................... Address Registers (A0 and A1) ............................................................................................................... Frame Base Register (FB) ....................................................................................................................... Interrupt Table Register (INTB) .............................................................................................................. Program Counter (PC) ............................................................................................................................. User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) .................................................................. Static Base Register (SB) ........................................................................................................................ Flag Register (FLG) ................................................................................................................................ Carry Flag (C) ..................................................................................................................................... Debug Flag (D) ................................................................................................................................... Zero Flag (Z) ....................................................................................................................................... Sign Flag (S) ....................................................................................................................................... Register Bank Select Flag (B) ............................................................................................................ Overflow Flag (O) .............................................................................................................................. Interrupt Enable Flag (I) ..................................................................................................................... Stack Pointer Select Flag (U) .............................................................................................................. Processor Interrupt Priority Level (IPL) ............................................................................................. Reserved Bit ........................................................................................................................................ 13 13 13 13 13 13 13 13 13 13 13 13 13 13 14 14 14 14 3. 3.1 3.2 4. 5. Memory ......................................................................................................................................... 15 R8C/2E Group ......................................................................................................................................... 15 R8C/2F Group ......................................................................................................................................... 16 Special Function Registers (SFRs) ............................................................................................... 17 Resets ........................................................................................................................................... 24 5.1 5.1.1 5.1.2 5.2 5.3 5.4 5.5 5.6 Hardware Reset ....................................................................................................................................... When Power Supply is Stable ............................................................................................................. Power On ............................................................................................................................................ Power-On Reset Function ....................................................................................................................... Voltage Monitor 1 Reset ......................................................................................................................... Voltage Monitor 2 Reset ......................................................................................................................... Watchdog Timer Reset ............................................................................................................................ Software Reset ......................................................................................................................................... 27 27 27 29 30 30 30 30 6. 6.1 Voltage Detection Circuit .............................................................................................................. 31 VCC Input Voltage .................................................................................................................................. 36 A-1 6.1.1 Monitoring Vdet1 ............................................................................................................................... 6.1.2 Monitoring Vdet2 ............................................................................................................................... 6.2 Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset ..................................................................... 6.3 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset ..................................................................... 7. 7.1 7.2 7.3 7.4 7.5 8. 8.1 9. 10. 36 36 37 39 Programmable I/O Ports ............................................................................................................... 41 Functions of Programmable I/O Ports ..................................................................................................... Effect on Peripheral Functions ................................................................................................................ Pins Other than Programmable I/O Ports ................................................................................................ Port Setting .............................................................................................................................................. Unassigned Pin Handling ........................................................................................................................ 41 42 42 52 62 Processor Mode ............................................................................................................................ 63 Processor Modes ...................................................................................................................................... 63 Bus ................................................................................................................................................ 64 Clock Generation Circuit ............................................................................................................... 65 XIN Clock ............................................................................................................................................... On-Chip Oscillator Clocks ...................................................................................................................... Low-Speed On-Chip Oscillator Clock ................................................................................................ High-Speed On-Chip Oscillator Clock ............................................................................................... CPU Clock and Peripheral Function Clock ............................................................................................. System Clock ...................................................................................................................................... CPU Clock .......................................................................................................................................... Peripheral Function Clock (f1, f2, f4, f8, and f32) ............................................................................. fOCO ................................................................................................................................................... fOCO40M ........................................................................................................................................... fOCO-F ............................................................................................................................................... fOCO-S ............................................................................................................................................... fOCO128 ............................................................................................................................................. Power Control .......................................................................................................................................... Standard Operating Mode ................................................................................................................... Wait Mode .......................................................................................................................................... Stop Mode ........................................................................................................................................... Oscillation Stop Detection Function ....................................................................................................... How to Use Oscillation Stop Detection Function ............................................................................... Notes on Clock Generation Circuit ......................................................................................................... Stop Mode ........................................................................................................................................... Wait Mode .......................................................................................................................................... Oscillation Stop Detection Function ................................................................................................... Oscillation Circuit Constants .............................................................................................................. 73 74 74 74 75 75 75 75 75 75 75 75 75 76 76 78 82 85 85 88 88 88 88 88 10.1 10.2 10.2.1 10.2.2 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.3.6 10.3.7 10.3.8 10.4 10.4.1 10.4.2 10.4.3 10.5 10.5.1 10.6 10.6.1 10.6.2 10.6.3 10.6.4 11. 12. Protection ...................................................................................................................................... 89 Interrupts ....................................................................................................................................... 90 12.1 Interrupt Overview .................................................................................................................................. 90 12.1.1 Types of Interrupts .............................................................................................................................. 90 12.1.2 Software Interrupts ............................................................................................................................. 91 A-2 12.1.3 12.1.4 12.1.5 12.1.6 12.2 12.2.1 12.2.2 12.3 12.4 12.5 12.6 12.6.1 12.6.2 12.6.3 12.6.4 12.6.5 13. 13.1 13.2 14. Special Interrupts ................................................................................................................................ 92 Peripheral Function Interrupt .............................................................................................................. 92 Interrupts and Interrupt Vectors .......................................................................................................... 93 Interrupt Control ................................................................................................................................. 95 INT Interrupt ......................................................................................................................................... 104 INTi Interrupt (i = 0, 1, 3) ................................................................................................................. 104 INTi Input Filter (i = 0, 1, 3) ............................................................................................................. 106 Key Input Interrupt ................................................................................................................................ 107 Address Match Interrupt ........................................................................................................................ 109 Timer RC Interrupt, Comparator 0 Interrupt, and Comparator 1 Interrupt ........................................... 111 Notes on Interrupts ................................................................................................................................ 112 Reading Address 00000h .................................................................................................................. 112 SP Setting .......................................................................................................................................... 112 External Interrupt and Key Input Interrupt ....................................................................................... 112 Changing Interrupt Sources .............................................................................................................. 113 Changing Interrupt Control Register Contents ................................................................................. 114 Watchdog Timer ........................................................................................................................... 115 Count Source Protection Mode Disabled .............................................................................................. 118 Count Source Protection Mode Enabled ............................................................................................... 119 Timers ......................................................................................................................................... 120 Timer RA ............................................................................................................................................... Timer Mode ...................................................................................................................................... Pulse Output Mode ........................................................................................................................... Event Counter Mode ......................................................................................................................... Pulse Width Measurement Mode ...................................................................................................... Pulse Period Measurement Mode ..................................................................................................... Notes on Timer RA ........................................................................................................................... Timer RB ............................................................................................................................................... Timer Mode ...................................................................................................................................... Programmable Waveform Generation Mode .................................................................................... Programmable One-shot Generation Mode ...................................................................................... Programmable Wait One-Shot Generation Mode ............................................................................. Notes on Timer RB ........................................................................................................................... Timer RC ............................................................................................................................................... Overview ........................................................................................................................................... Registers Associated with Timer RC ................................................................................................ Common Items for Multiple Modes ................................................................................................. Timer Mode (Input Capture Function) ............................................................................................. Timer Mode (Output Compare Function) ......................................................................................... PWM Mode ....................................................................................................................................... PWM2 Mode ..................................................................................................................................... Timer RC Interrupt ........................................................................................................................... Notes on Timer RC ........................................................................................................................... Timer RE ............................................................................................................................................... Output Compare Mode ..................................................................................................................... Notes on Timer RE ........................................................................................................................... 122 125 127 129 131 134 137 138 142 145 148 152 155 159 159 161 171 177 182 188 193 199 200 201 202 206 14.1 14.1.1 14.1.2 14.1.3 14.1.4 14.1.5 14.1.6 14.2 14.2.1 14.2.2 14.2.3 14.2.4 14.2.5 14.3 14.3.1 14.3.2 14.3.3 14.3.4 14.3.5 14.3.6 14.3.7 14.3.8 14.3.9 14.4 14.4.1 14.4.2 A-3 15. Serial Interface ............................................................................................................................ 207 213 216 216 217 218 222 223 15.1 Clock Synchronous Serial I/O Mode ..................................................................................................... 15.1.1 Polarity Select Function .................................................................................................................... 15.1.2 LSB First/MSB First Select Function ............................................................................................... 15.1.3 Continuous Receive Mode ................................................................................................................ 15.2 Clock Asynchronous Serial I/O (UART) Mode .................................................................................... 15.2.1 Bit Rate ............................................................................................................................................. 15.3 Notes on Serial Interface ....................................................................................................................... 16. Hardware LIN .............................................................................................................................. 224 Features ................................................................................................................................................. Input/Output Pins .................................................................................................................................. Register Configuration .......................................................................................................................... Functional Description .......................................................................................................................... Master Mode ..................................................................................................................................... Slave Mode ....................................................................................................................................... Bus Collision Detection Function ..................................................................................................... Hardware LIN End Processing ......................................................................................................... Interrupt Requests .................................................................................................................................. Notes on Hardware LIN ........................................................................................................................ 224 225 226 228 228 231 235 236 237 238 16.1 16.2 16.3 16.4 16.4.1 16.4.2 16.4.3 16.4.4 16.5 16.6 17. 17.1 17.2 17.3 17.4 17.5 17.6 17.7 18. 19. A/D Converter ............................................................................................................................. 239 One-Shot Mode ..................................................................................................................................... Repeat Mode .......................................................................................................................................... Sample and Hold ................................................................................................................................... A/D Conversion Cycles ......................................................................................................................... Internal Equivalent Circuit of Analog Input .......................................................................................... Output Impedance of Sensor under A/D Conversion ............................................................................ Notes on A/D Converter ........................................................................................................................ 243 246 249 249 250 251 252 D/A Converter ............................................................................................................................. 253 Comparator ................................................................................................................................. 256 Overview ............................................................................................................................................... Register Functions ................................................................................................................................. Functional Description .......................................................................................................................... Comparison Result Output ................................................................................................................ Digital Filter ...................................................................................................................................... Comparator 0 Interrupt and Comparator 1 Interrupt ............................................................................. 256 258 260 261 262 263 19.1 19.2 19.3 19.3.1 19.3.2 19.4 20. Flash Memory Version ................................................................................................................ 264 Overview ............................................................................................................................................... Memory Map ......................................................................................................................................... Functions to Prevent Rewriting of Flash Memory ................................................................................ ID Code Check Function .................................................................................................................. ROM Code Protect Function ............................................................................................................ CPU Rewrite Mode ............................................................................................................................... EW0 Mode ........................................................................................................................................ EW1 Mode ........................................................................................................................................ A-4 264 265 267 267 268 269 270 270 20.1 20.2 20.3 20.3.1 20.3.2 20.4 20.4.1 20.4.2 20.4.3 Software Commands ......................................................................................................................... 20.4.4 Status Registers ................................................................................................................................. 20.4.5 Full Status Check .............................................................................................................................. 20.5 Standard Serial I/O Mode ...................................................................................................................... 20.5.1 ID Code Check Function .................................................................................................................. 20.6 Parallel I/O Mode .................................................................................................................................. 20.6.1 ROM Code Protect Function ............................................................................................................ 20.7 Notes on Flash Memory Version ........................................................................................................... 20.7.1 CPU Rewrite Mode ........................................................................................................................... 21. 22. 279 284 285 287 287 290 290 291 291 Electrical Characteristics ............................................................................................................ 294 Usage Notes ............................................................................................................................... 309 Notes on Clock Generation Circuit ....................................................................................................... 309 Stop Mode ......................................................................................................................................... 309 Wait Mode ........................................................................................................................................ 309 Oscillation Stop Detection Function ................................................................................................. 309 Oscillation Circuit Constants ............................................................................................................ 309 Notes on Interrupts ................................................................................................................................ 310 Reading Address 00000h .................................................................................................................. 310 SP Setting .......................................................................................................................................... 310 External Interrupt and Key Input Interrupt ....................................................................................... 310 Changing Interrupt Sources .............................................................................................................. 311 Changing Interrupt Control Register Contents ................................................................................. 312 Notes on Timers .................................................................................................................................... 313 Notes on Timer RA ........................................................................................................................... 313 Notes on Timer RB ........................................................................................................................... 314 Notes on Timer RC ........................................................................................................................... 318 Notes on Timer RE ........................................................................................................................... 319 Notes on Serial Interface ....................................................................................................................... 320 Notes on Hardware LIN ........................................................................................................................ 321 Notes on A/D Converter ........................................................................................................................ 322 Notes on Flash Memory Version ........................................................................................................... 323 CPU Rewrite Mode ........................................................................................................................... 323 Notes on Noise ...................................................................................................................................... 326 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and Latch-up ............................................................................................................................................ 326 22.8.2 Countermeasures against Noise Error of Port Control Registers ..................................................... 326 Notes for On-Chip Debugger ...................................................................................................... 327 22.1 22.1.1 22.1.2 22.1.3 22.1.4 22.2 22.2.1 22.2.2 22.2.3 22.2.4 22.2.5 22.3 22.3.1 22.3.2 22.3.3 22.3.4 22.4 22.5 22.6 22.7 22.7.1 22.8 22.8.1 23. Appendix 1. Package Dimensions ........................................................................................................ 328 Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator ............ 329 Appendix 3. Example of Oscillation Evaluation Circuit ......................................................................... 330 Index ..................................................................................................................................................... 331 A-5 SFR Page Reference Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch Register Symbol Page Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh Register Symbol Page Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 PM0 PM1 CM0 CM1 63 63 67 68 Timer RC Interrupt Control Register TRCIC 96 Protect Register Oscillation Stop Detection Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0 PRCR OCD WDTR WDTS WDC RMAD0 89 69 116 116 116 110 Timer RE Interrupt Control Register TREIC 95 Key Input Interrupt Control Register A/D Conversion Interrupt Control Register KUPIC ADIC 95 95 UART0 Transmit Interrupt Control Register S0TIC UART0 Receive Interrupt Control Register S0RIC 95 95 Address Match Interrupt Enable Register Address Match Interrupt Register 1 AIER RMAD1 110 110 Timer RA Interrupt Control Register Timer RB Interrupt Control Register INT1 Interrupt Control Register INT3 Interrupt Control Register Comparator 0 Interrupt Control Register Comparator 1 Interrupt Control Register INT0 Interrupt Control Register TRAIC TRBIC INT1IC INT3IC CM0IC CM1IC INT0IC 95 95 97 97 96 96 97 Count Source Protection Mode Register CSPR 117 High-Speed On-Chip Oscillator Control Register 0 High-Speed On-Chip Oscillator Control Register 1 High-Speed On-Chip Oscillator Control Register 2 FRA0 FRA1 FRA2 70 70 70 High-Speed On-Chip Oscillator Control Register 7 FRA7 71 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Voltage Detection Register 1 Voltage Detection Register 2 VCA1 VCA2 33 33, 71 Voltage Monitor 1 Circuit Control Register Voltage Monitor 2 Circuit Control Register VW1C VW2C 34 35 NOTE: 1. The blank regions are reserved. Do not access locations in these regions. B-1 Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh Register Symbol Page UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register U0MR U0BRG U0TB 210 210 209 211 212 209 UART0 Transmit / Receive Control Register 0 U0C0 UART0 Transmit / Receive Control Register 1 U0C1 UART0 Receive Buffer Register U0RB Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh Register A/D Register Symbol AD Page 242 A/D Control Register 2 A/D Control Register 0 A/D Control Register 1 D/A Register 0 D/A Register 1 D/A Control Register ADCON2 ADCON0 ADCON1 DA0 DA1 DACON 242 241 242 254 254 254 Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P3 Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register P0 P1 PD0 PD1 P3 PD3 P4 P5 PD4 PD5 49 49 48 48 49 48 49 49 48 48 Pin Select Register 2 Pin Select Register 3 Port Mode Register External Input Enable Register INT Input Filter Select Register Key Input Enable Register Pull-Up Control Register 0 Pull-Up Control Register 1 Port P1 Drive Capacity Control Register PINSR2 PINSR3 PMR INTEN INTF KIEN PUR0 PUR1 P1DRR 50 50 50, 212 104 105 108 51 51 51 NOTE: 1. The blank regions are reserved. Do not access locations in these regions. B-2 Address Register 0100h Timer RA Control Register 0101h Timer RA I/O Control Register 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh Timer RA Mode Register Timer RA Prescaler Register Timer RA Register LIN Control Register LIN Status Register Timer RB Control Register Timer RB One-Shot Control Register Timer RB I/O Control Register Timer RB Mode Register Timer RB Prescaler Register Timer RB Secondary Register Timer RB Primary Register Symbol TRACR TRAIOC TRAMR TRAPRE TRA LINCR LINST TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBSC TRBPR Page 123 123, 125, 128, 130, 132, 135 124 124 124 226 227 139 139 140, 142, 146, 149, 153 140 141 141 141 Timer RE Counter Data Register Timer RE Compare Data Register TRESEC TREMIN 203 203 Timer RE Control Register 1 Timer RE Control Register 2 Timer RE Clock Source Select Register Timer RC Mode Register Timer RC Control Register 1 Timer RC Interrupt Enable Register Timer RC Status Register Timer RC I/O Control Register 0 Timer RC I/O Control Register 1 Timer RC Counter Timer RC General Register A Timer RC General Register B Timer RC General Register C Timer RC General Register D TRECR1 TRECR2 TRECSR TRCMR TRCCR1 TRCIER TRCSR TRCIOR0 TRCIOR1 TRC TRCGRA TRCGRB TRCGRC TRCGRD 203 204 204 162 163, 186, 190, 195 164 165 170, 179, 184 170, 180, 185 166 166 166 166 166 NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Address Register 0130h Timer RC Control Register 2 0131h Timer RC Digital Filter Function Select Register 0132h Timer RC Output Master Enable Register 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh Symbol TRCCR2 TRCDF TRCOER Page 167 168 169 B-3 Address Register 0170h 0171h 0172h 0173h 0174h Comparator 0 Control Register 0175h Comparator 1 Control Register 0176h 0177h Comparator Mode Register 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh Symbol Page ACCR0 ACCR1 ACMR 255, 258 255, 258 259 Address Register 01B0h 01B1h 01B2h 01B3h Flash Memory Control Register 4 01B4h 01B5h Flash Memory Control Register 1 01B6h 01B7h Flash Memory Control Register 0 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh FFFFh Option Function Select Register Symbol Page FMR4 FMR1 FMR0 275 274 273 OFS 26, 117, 268 NOTE: 1. The blank regions are reserved. Do not access locations in these regions. B-4 R8C/2E Group, R8C/2F Group RENESAS MCU REJ09B0349-0100 Rev.1.00 Dec 14, 2007 1. 1.1 Overview Features The R8C/2E Group and R8C/2F Group of single-chip MCUs incorporates the R8C/Tiny Series CPU core, employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high speed. In addition, the CPU core boasts a multiplier for high-speed operation processing. Power consumption is low, and the supported operating modes allow additional power control. These MCUs also use an anti-noise configuration to reduce emissions of electromagnetic noise and are designed to withstand EMI. Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of system components. Furthermore, the R8C/2F Group has on-chip data flash (1 KB × 2 blocks). The difference between the R8C/2E Group and R8C/2F Group is only the presence or absence of data flash. Their peripheral functions are the same. 1.1.1 Applications Electronic household appliances, office equipment, audio equipment, consumer equipment, etc. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 1 of 332 R8C/2E Group, R8C/2F Group 1. Overview 1.1.2 Specifications Tables 1.1 and 1.2 outlines the Specifications for R8C/2E Group and Tables 1.3 and 1.4 outlines the Specifications for R8C/2F Group. Table 1.1 Item CPU Specifications for R8C/2E Group (1) Function Specification Central R8C/Tiny series core processing unit • Number of fundamental instructions: 89 • Minimum instruction execution time: 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) • Multiplier: 16 bits × 16 bits → 32 bits • Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits • Operation mode: Single-chip mode (address space: 1 Mbyte) Memory ROM, RAM Refer to Table 1.5 Product List for R8C/2E Group. Power Supply Voltage • Power-on reset detection circuit • Voltage detection 2 Voltage Detection I/O Ports Programmable • Input-only: 3 pins I/O ports • CMOS I/O ports: 25, selectable pull-up resistor • High current drive ports: 8 Clock Clock generation 2 circuits: XIN clock oscillation circuit (with on-chip feedback resistor), circuits On-chip oscillator (high-speed, low-speed) (high-speed on-chip oscillator has a frequency adjustment function) • Oscillation stop detection: XIN clock oscillation stop detection function • Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16 • Low power consumption modes: Standard operating mode (high-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode Interrupts • External: 4 sources, Internal: 13 sources, Software: 4 sources • Priority levels: 7 levels Watchdog Timer 15 bits × 1 (with prescaler), reset start selectable Timer Timer RA 8 bits × 1 (with 8-bit prescaler) Timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode Timer RB 8 bits × 1 (with 8-bit prescaler) Timer mode (period timer), programmable waveform generation mode (PWM output), programmable one-shot generation mode, programmable wait one-shot generation mode Timer RC 16 bits × 1 (with 4 capture/compare registers) Timer mode (input capture function, output compare function), PWM mode (output 3 pins), PWM2 mode (PWM output pin) Timer RE 8 bits × 1 Output compare mode Serial UART0 Clock synchronous serial I/O/UART × 1 Interface LIN Module Hardware LIN: 1 (timer RA, UART0) A/D Converter 10-bit resolution × 12 channels, includes sample and hold function D/A Converter 8-bit resolution × 2 circuits Comparator 2 circuits Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 2 of 332 R8C/2E Group, R8C/2F Group 1. Overview Table 1.2 Specifications for R8C/2E Group (2) Item Specification Flash Memory • Programming and erasure voltage: VCC = 2.7 to 5.5 V • Programming and erasure endurance: 100 times • Program security: ROM code protect, ID code check • Debug functions: On-chip debug, on-board flash rewrite function Operating Frequency/Supply f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V), f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V) Voltage Current consumption Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz) Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz) Typ. 23 µA (VCC = 3.0 V, wait mode (peripheral clock off)) Typ. 0.7 µA (VCC = 3.0 V, stop mode) Operating Ambient Temperature -20 to 85°C (N version) -40 to 85°C (D version)(1) Package 32-pin LQFP Package code: PLQP0032GB-A (previous code: 32P6U-A) NOTE: 1. Specify the D version if D version functions are to be used. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 3 of 332 R8C/2E Group, R8C/2F Group 1. Overview Table 1.3 Item CPU Specifications for R8C/2F Group (1) Function Specification Central R8C/Tiny series core processing unit • Number of fundamental instructions: 89 • Minimum instruction execution time: 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) • Multiplier: 16 bits × 16 bits → 32 bits • Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits • Operation mode: Single-chip mode (address space: 1 Mbyte) Memory ROM, RAM Refer to Table 1.6 Product List for R8C/2F Group. Power Supply Voltage detection • Power-on reset Voltage circuit • Voltage detection 2 Detection I/O Ports Programmable • Input-only: 3 pins I/O ports • CMOS I/O ports: 25, selectable pull-up resistor • High current drive ports: 8 Clock Clock generation 2 circuits: XIN clock oscillation circuit (with on-chip feedback resistor), circuits On-chip oscillator (high-speed, low-speed) (high-speed on-chip oscillator has a frequency adjustment function) • Oscillation stop detection: XIN clock oscillation stop detection function • Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16 • Low power consumption modes: Standard operating mode (high-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode Interrupts • External: 4 sources, Internal: 13 sources, Software: 4 sources • Priority levels: 7 levels Watchdog Timer 15 bits × 1 (with prescaler), reset start selectable Timer Timer RA 8 bits × 1 (with 8-bit prescaler) Timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode Timer RB 8 bits × 1 (with 8-bit prescaler) Timer mode (period timer), programmable waveform generation mode (PWM output), programmable one-shot generation mode, programmable wait one-shot generation mode Timer RC 16 bits × 1 (with 4 capture/compare registers) Timer mode (input capture function, output compare function), PWM mode (output 3 pins), PWM2 mode (PWM output pin) Timer RE 8 bits × 1 Output compare mode Serial UART0 Clock synchronous serial I/O/UART × 1 Interface LIN Module Hardware LIN: 1 (timer RA, UART0) A/D Converter 10-bit resolution × 12 channels, includes sample and hold function D/A Converter 8-bit resolution × 2 circuits Comparator 2 circuits Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 4 of 332 R8C/2E Group, R8C/2F Group 1. Overview Table 1.4 Specifications for R8C/2F Group (2) Item Specification Flash Memory • Programming and erasure voltage: VCC = 2.7 to 5.5 V • Programming and erasure endurance: 10,000 times (data flash) 1,000 times (program ROM) • Program security: ROM code protect, ID code check • Debug functions: On-chip debug, on-board flash rewrite function Operating Frequency/Supply f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V), f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V) Voltage Current consumption Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz) Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz) Typ. 23 µA (VCC = 3.0 V, wait mode (peripheral clock off)) Typ. 0.7 µA (VCC = 3.0 V, stop mode) Operating Ambient Temperature -20 to 85°C (N version) -40 to 85°C (D version)(1) Package 32-pin LQFP Package code: PLQP0032GB-A (previous code: 32P6U-A) NOTE: 1. Specify the D version if D version functions are to be used. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 5 of 332 R8C/2E Group, R8C/2F Group 1. Overview 1.2 Product List Table 1.5 lists Product List for R8C/2E Group, Figure 1.1 shows a Part Number, Memory Size, and Package of R8C/2E Group, Table 1.6 lists Product List for R8C/2F Group, and Figure 1.2 shows a Part Number, Memory Size, and Package of R8C/2F Group. Table 1.5 Product List for R8C/2E Group ROM Capacity 8 Kbytes 16 Kbytes 8 Kbytes 16 Kbytes 8 Kbytes 16 Kbytes 8 Kbytes 16 Kbytes RAM Capacity 512 bytes 1 Kbyte 512 bytes 1 Kbyte 512 bytes 1 Kbyte 512 bytes 1 Kbyte Package Type PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A Current of Dec. 2007 Remarks N version D version N version Factory programming product(1) D version Factory programming product(1) Part No. R5F212E2NFP R5F212E4NFP R5F212E2DFP R5F212E4DFP R5F212E2NXXXFP R5F212E4NXXXFP R5F212E2DXXXFP R5F212E4DXXXFP NOTE: 1. The user ROM is programmed before shipment. Part No. R 5 F 21 2E 2 N XXX FP Package type: FP: PLQP0032GB-A ROM number (only factory programming product) Classification N: Operating ambient temperature -20°C to 85°C D: Operating ambient temperature -40°C to 85°C ROM capacity 2: 8 KB 4: 16 KB R8C/2E Group R8C/Tiny Series Memory type F: Flash memory version Renesas MCU Renesas semiconductor Figure 1.1 Part Number, Memory Size, and Package of R8C/2E Group Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 6 of 332 R8C/2E Group, R8C/2F Group 1. Overview Table 1.6 Product List for R8C/2F Group ROM Capacity Program ROM Data flash 8 Kbytes 1 Kbyte × 2 16 Kbytes 1 Kbyte × 2 8 Kbytes 1 Kbyte × 2 16 Kbytes 1 Kbyte × 2 8 Kbytes 1 Kbyte × 2 16 Kbytes 1 Kbyte × 2 8 Kbytes 16 Kbytes RAM Capacity 512 bytes 1 Kbyte 512 bytes 1 Kbyte 512 bytes 1 Kbyte Package Type PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A Current of Dec. 2007 Remarks N version D version Part No. R5F212F2NFP R5F212F4NFP R5F212F2DFP R5F212F4DFP R5F212F2NXXXFP R5F212F4NXXXFP R5F212F2DXXXFP R5F212F4DXXXFP N version Factory programming product(1) 1 Kbyte × 2 512 bytes PLQP0032GB-A D version 1 Kbyte × 2 1 Kbyte PLQP0032GB-A Factory programming product(1) NOTE: 1. The user ROM is programmed before shipment. Part No. R 5 F 21 2F 2 N XXX FP Package type: FP: PLQP0032GB-A ROM number (only factory programming product) Classification N: Operating ambient temperature -20°C to 85°C D: Operating ambient temperature -40°C to 85°C ROM capacity 2: 8 KB 4: 16 KB R8C/2F Group R8C/Tiny Series Memory type F: Flash memory version Renesas MCU Renesas semiconductor Figure 1.2 Part Number, Memory Size, and Package of R8C/2F Group Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 7 of 332 R8C/2E Group, R8C/2F Group 1. Overview 1.3 Block Diagram Figure 1.3 shows a Block Diagram. 8 8 6 1 3 2 I/O ports Port P0 Port P1 Port P3 Port P4 Port P5 Peripheral functions Timers Timer RA (8 bits × 1) Timer RB (8 bits × 1) Timer RC (16 bits × 1) Timer RE (8 bits × 1) A/D converter (10 bits × 12 channels) D/A converter (8 bits × 2) Comparator (× 2) System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-Speed on-chip oscillator UART or clock synchronous serial I/O (8 bits × 1) LIN module Watchdog timer (15 bits) R8C/Tiny Series CPU core R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG Memory ROM(1) RAM(2) Multiplier NOTES: 1. ROM size varies with MCU type. 2. RAM size varies with MCU type. Figure 1.3 Block Diagram Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 8 of 332 R8C/2E Group, R8C/2F Group 1. Overview 1.4 Pin Assignment Figure 1.4 shows Pin Assignments (Top View). Table 1.7 outlines the Pin Name Information by Pin Number. P1_1/KI1/AN9/TRCIOA/TRCTRG VREF/P4_2 P1_2/KI2/AN10/TRCIOB P1_3/KI3/AN11/(TRBO)(2) P3_4/(TRCIOC)(2) P3_3/INT3/TRCCLK P1_0/KI0/AN8 24 23 22 21 20 19 18 17 P1_4/TXD0 P0_7/AN0/DA1 P0_6/AN1/DA0 P0_5/AN2/AVREF0 P0_4/AN3/TREO/ACMP0 P0_3/AN4/AVREF1 P0_2/AN5/ACMP1 P0_1/AN6 P0_0/AN7 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 16 R8C/2E Group, R8C/2F Group PLQP0032GB-A (32P6U-A) (top view) 15 14 13 12 11 10 9 P1_5/RXD0/(TRAIO)/(INT1)(2) P1_6/CLK0 P5_3/TRCIOC/ACOUT0 P5_4/TRCIOD/ACOUT1 P3_1/TRBO P3_6/(INT1)(2) P1_7/TRAIO/INT1 P4_5/INT0 P3_5/(TRCIOD)(2) P3_7/TRAO RESET XOUT/P4_7 (1) VSS/AVSS XIN/P4_6 NOTES: 1. P4_7 is an input-only port. 2. Can be assigned to the pin in parentheses by a program. 3. Confirm the pin 1 position on the package by referring to the package dimensions. Figure 1.4 Pin Assignments (Top View) Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 9 of 332 VCC/AVCC MODE R8C/2E Group, R8C/2F Group 1. Overview Table 1.7 Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name Information by Pin Number Control Pin Port P3_5 P3_7 RESET XOUT VSS/AVSS XIN VCC/AVCC MODE P4_7 P4_6 I/O Pin Functions for of Peripheral Modules Serial A/D D/A Timer Interface Converter Converter (TRCIOD)(1) TRAO Interrupt Comparator P4_5 P1_7 P3_6 P3_1 P5_4 P5_3 P1_6 P1_5 P1_4 P1_3 P1_2 VREF P4_2 P1_1 P1_0 P3_3 P3_4 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 INT0 INT1 (INT1)(1) TRBO TRCIOD TRCIOC CLK0 (INT1)(1) KI3 KI2 KI1 KI0 INT3 TRCCLK (TRCIOC)(1) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 DA1 DA0 AVREF0 ACMP0 AVREF1 ACMP1 (TRAIO)(1) (TRBO)(1) TRCIOB TRCIOA/ TRCTRG RXD0 TXD0 AN11 AN10 AN9 AN8 ACOUT1 ACOUT0 TRAIO TREO NOTE: 1. Can be assigned to the pin in parentheses by a program. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 10 of 332 R8C/2E Group, R8C/2F Group 1. Overview 1.5 Pin Functions Table 1.8 list Pin Functions. Table 1.8 Type Analog power supply input Reset input MODE XIN clock input XIN clock output INT interrupt input Key input interrupt Timer RA Timer RB Timer RC Pin Functions Symbol AVCC, AVSS RESET MODE XIN XOUT INT0, INT1, INT3 KI0 to KI3 TRAO TRAIO TRBO TRCCLK TRCTRG TRCIOA, TRCIOB, TRCIOC, TRCIOD I/O Type I I I I I O I I O I/O O I I I/O O I/O I O I I O I I O I/O Description Apply 2.7 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin. Power supply for the A/D converter. Connect a capacitor between AVCC and AVSS. Input “L” on this pin resets the MCU. Connect this pin to VCC via a resistor. These pins are provided for XIN clock generation circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins.(1) To use an external clock, input it to the XIN pin and leave the XOUT pin open. INT interrupt input pins Key input interrupt input pins Timer RA output pin Timer RA I/O pin Timer RB output pin External clock input pin External trigger input pin Sharing output-compare output / input-capture input / PWM / PWM2 output pins Timer RE output pin Clock I/O pin Receive data input pin Transmit data output pin Reference voltage input pin to A/D converter Analog input pins to A/D converter Output pins from D/A converter Reference voltage input pins to comparator Analog voltage input pins to comparator Comparison result output pins of comparator CMOS I/O ports. Each port has an I/O select direction register, allowing each pin in the port to be directed for input or output individually. Any port set to input can be set to use a pull-up resistor or not by a program. P1_0 to P1_7 also function as LED drive ports. Input-only ports Power supply input VCC, VSS Timer RE Serial interface TREO CLK0 RXD0 TXD0 Reference voltage input A/D converter D/A converter Comparator VREF AN0 to AN11 DA0 to DA1 AVREF0 to AVREF1 ACMP0 to ACMP1 ACOUT0 to ACOUT1 I/O port P0_0 to P0_7, P1_0 to P1_7, P3_1, P3_3 to P3_7, P4_5, P5_3, P5_4 P4_2, P4_6, P4_7 Input port I I: Input O: Output I/O: Input and output NOTE: 1. Refer to the oscillator manufacturer for oscillation characteristics. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 11 of 332 R8C/2E Group, R8C/2F Group 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank. b31 b15 b8b7 b0 R2 R3 R0H (high-order of R0) R0L (low-order of R0) R1H (high-order of R1) R1L (low-order of R1) Data registers(1) R2 R3 A0 A1 FB b19 b15 b0 Address registers(1) Frame base register(1) INTBH INTBL Interrupt table register The 4 high order bits of INTB are INTBH and the 16 low order bits of INTB are INTBL. b19 b0 PC Program counter b15 b0 USP ISP SB b15 b0 User stack pointer Interrupt stack pointer Static base register FLG b15 b8 b7 b0 Flag register IPL U I OBSZDC Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bit Processor interrupt priority level Reserved bit NOTE: 1. These registers comprise a register bank. There are two register banks. Figure 2.1 CPU Registers Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 12 of 332 R8C/2E Group, R8C/2F Group 2. Central Processing Unit (CPU) 2.1 Data Registers (R0, R1, R2, and R3) R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is analogous to R2R0. 2.2 Address Registers (A0 and A1) A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 to be used as a 32-bit address register (A1A0). 2.3 Frame Base Register (FB) FB is a 16-bit register for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is a 20-bit register that indicates the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is 20 bits wide and indicates the address of the next instruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between USP and ISP. 2.7 Static Base Register (SB) SB is a 16-bit register for SB relative addressing. 2.8 Flag Register (FLG) FLG is an 11-bit register indicating the CPU state. 2.8.1 Carry Flag (C) The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 Debug Flag (D) The D flag is for debugging only. Set it to 0. 2.8.3 Zero Flag (Z) The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 Sign Flag (S) The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 Register Bank Select Flag (B) Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1. 2.8.6 Overflow Flag (O) The O flag is set to 1 when an operation results in an overflow; otherwise to 0. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 13 of 332 R8C/2E Group, R8C/2F Group 2. Central Processing Unit (CPU) 2.8.7 Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged. 2.8.8 Stack Pointer Select Flag (U) ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1. The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled. 2.8.10 Reserved Bit If necessary, set to 0. When read, the content is undefined. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 14 of 332 R8C/2E Group, R8C/2F Group 3. Memory 3. 3.1 Memory R8C/2E Group Figure 3.1 is a Memory Map of R8C/2E Group. The R8C/2E group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1-Kbyte internal RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users. 00000h SFR (Refer to 4. Special Function Registers (SFRs)) 002FFh 00400h Internal RAM 0XXXh 0FFDCh Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer/oscillation stop detection/voltage monitor 2 0YYYYh Internal ROM (program ROM) 0FFFFh 0FFFFh (Reserved) (Reserved) Reset FFFFFh NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Internal ROM Part Number R5F212E2NFP, R5F212E2DFP, R5F212E2NXXXFP, R5F212E2DXXXFP R5F212E4NFP, R5F212E4DFP, R5F212E4NXXXFP, R5F212E4DXXXFP 16 Kbytes 0C000h 1 Kbyte 007FFh Size 8 Kbytes Address 0YYYYh 0E000h Size 512 bytes Internal RAM Address 0XXXXh 005FFh Figure 3.1 Memory Map of R8C/2E Group Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 15 of 332 R8C/2E Group, R8C/2F Group 3. Memory 3.2 R8C/2F Group Figure 3.2 is a Memory Map of R8C/2F Group. The R8C/2F group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal ROM (data flash) is allocated addresses 02400h to 02BFFh. The internal RAM area is allocated higher addresses, beginning with address 00400h. For example, a 1-Kbyte internal RAM is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users. 00000h SFR (Refer to 4. Special Function Registers (SFRs)) 002FFh 00400h Internal RAM 0XXXXh 02400h Internal ROM (data flash)(1) 02BFFh 0FFDCh Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer/oscillation stop detection/voltage monitor 2 0YYYYh Internal ROM (program ROM) 0FFFFh 0FFFFh (Reserved) (Reserved) Reset FFFFFh NOTES: 1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown. 2. The blank regions are reserved. Do not access locations in these regions. Internal ROM Part Number R5F212F2NFP, R5F212F2DFP, R5F212F2NXXXFP, R5F212F2DXXXFP R5F212F4NFP, R5F212F4DFP, R5F212F4NXXXFP, R5F212F4DXXXFP 16 Kbytes 0C000h 1 Kbyte 007FFh Size 8 Kbytes Address 0YYYYh 0E000h Size 512 bytes Internal RAM Address 0XXXXh 005FFh Figure 3.2 Memory Map of R8C/2F Group Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 16 of 332 R8C/2E Group, R8C/2F Group 4. Special Function Registers (SFRs) 4. Special Function Registers (SFRs) An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.7 list the special function registers. Table 4.1 Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch SFR Information (1)(1) Register Symbol After reset Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 PM0 PM1 CM0 CM1 00h 00h 01101000b 00100000b Protect Register Oscillation Stop Detection Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0 PRCR OCD WDTR WDTS WDC RMAD0 00h 00000100b XXh XXh 00X11111b 00h 00h 00h 00h 00h 00h 00h Address Match Interrupt Enable Register Address Match Interrupt Register 1 AIER RMAD1 Count Source Protection Mode Register CSPR 00h 10000000b(4) High-Speed On-Chip Oscillator Control Register 0 High-Speed On-Chip Oscillator Control Register 1 High-Speed On-Chip Oscillator Control Register 2 FRA0 FRA1 FRA2 00h When shipping 00h High-Speed On-Chip Oscillator Control Register 7 FRA7 When Shipping 0030h VCA1 00001000b 0031h Voltage Detection Register 1 (2) VCA2 00100000b 0032h Voltage Detection Register 2 (2) 0033h 0034h 0035h VW1C 00001000b 0036h Voltage Monitor 1 Circuit Control Register(3) VW2C 00h 0037h Voltage Monitor 2 Circuit Control Register(3) 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Software reset, watchdog timer reset, and voltage monitor 1 reset or voltage monitor 2 reset do not affect this register. 3. Software reset, watchdog timer reset, and voltage monitor 1 reset or voltage monitor 2 reset do not affect b2 and b3. 4. The CSPROINI bit in the OFS register is set to 0. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 17 of 332 R8C/2E Group, R8C/2F Group Table 4.2 SFR Information (2)(1) 4. Special Function Registers (SFRs) Address Register 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h Timer RC Interrupt Control Register 0048h 0049h 004Ah Timer RE Interrupt Control Register 004Bh 004Ch 004Dh Key Input Interrupt Control Register 004Eh A/D Conversion Interrupt Control Register 004Fh 0050h 0051h UART0 Transmit Interrupt Control Register 0052h UART0 Receive Interrupt Control Register 0053h 0054h 0055h 0056h Timer RA Interrupt Control Register 0057h 0058h Timer RB Interrupt Control Register 0059h INT1 Interrupt Control Register 005Ah INT3 Interrupt Control Register 005Bh Comparator 0 Interrupt Control Register 005Ch Comparator 1 Interrupt Control Register 005Dh INT0 Interrupt Control Register 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Symbol After reset TRCIC XXXXX000b TREIC XXXXX000b KUPIC ADIC XXXXX000b XXXXX000b S0TIC S0RIC XXXXX000b XXXXX000b TRAIC TRBIC INT1IC INT3IC CM0IC CM1IC INT0IC XXXXX000b XXXXX000b XX00X000b XX00X000b XXXXX000b XXXXX000b XX00X000b Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 18 of 332 R8C/2E Group, R8C/2F Group 4. Special Function Registers (SFRs) Table 4.3 SFR Information (3)(1) Symbol After reset Address Register 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h UART0 Transmit/Receive Mode Register 00A1h UART0 Bit Rate Register 00A2h UART0 Transmit Buffer Register 00A3h 00A4h UART0 Transmit/Receive Control Register 0 00A5h UART0 Transmit/Receive Control Register 1 00A6h UART0 Receive Buffer Register 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. U0MR U0BRG U0TB U0C0 U0C1 U0RB 00h XXh XXh XXh 00001000b 00000010b XXh XXh Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 19 of 332 R8C/2E Group, R8C/2F Group 4. Special Function Registers (SFRs) Table 4.4 SFR Information (4)(1) Symbol AD XXh XXh After reset Address Register 00C0h A/D Register 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h A/D Control Register 2 00D5h 00D6h A/D Control Register 0 00D7h A/D Control Register 1 00D8h D/A Register 0 00D9h 00DAh D/A Register 1 00DBh 00DCh D/A Control Register 00DDh 00DEh 00DFh 00E0h Port P0 Register 00E1h Port P1 Register 00E2h Port P0 Direction Register 00E3h Port P1 Direction Register 00E4h 00E5h Port P3 Register 00E6h 00E7h Port P3 Direction Register 00E8h Port P4 Register 00E9h Port P5 Register 00EAh Port P4 Direction Register 00EBh Port P5 Direction Register 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h Pin Select Register 2 00F7h Pin Select Register 3 00F8h Port Mode Register 00F9h External Input Enable Register 00FAh INT Input Filter Select Register 00FBh Key Input Enable Register 00FCh Pull-Up Control Register 0 00FDh Pull-Up Control Register 1 00FEh Port P1 Drive Capacity Control Register 00FFh X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. ADCON2 ADCON0 ADCON1 DA0 DA1 DACON 00h 00h 00h 00h 00h 00h P0 P1 PD0 PD1 P3 PD3 P4 P5 PD4 PD5 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h PINSR2 PINSR3 PMR INTEN INTF KIEN PUR0 PUR1 P1DRR 00h 00h 00h 00h 00h 00h 00h 00h 00h Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 20 of 332 R8C/2E Group, R8C/2F Group 4. Special Function Registers (SFRs) Table 4.5 SFR Information (5)(1) Symbol TRACR TRAIOC TRAMR TRAPRE TRA LINCR LINST TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBSC TRBPR After reset 00h 00h 00h FFh FFh 00h 00h 00h 00h 00h 00h FFh FFh FFh Address Register 0100h Timer RA Control Register 0101h Timer RA I/O Control Register 0102h Timer RA Mode Register 0103h Timer RA Prescaler Register 0104h Timer RA Register 0105h 0106h LIN Control Register 0107h LIN Status Register 0108h Timer RB Control Register 0109h Timer RB One-Shot Control Register 010Ah Timer RB I/O Control Register 010Bh Timer RB Mode Register 010Ch Timer RB Prescaler Register 010Dh Timer RB Secondary Register 010Eh Timer RB Primary Register 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h Timer RE Counter Data Register 0119h Timer RE Compare Data Register 011Ah 011Bh 011Ch Timer RE Control Register 1 011Dh Timer RE Control Register 2 011Eh Timer RE Clock Source Select Register 011Fh 0120h Timer RC Mode Register 0121h Timer RC Control Register 1 0122h Timer RC Interrupt Enable Register 0123h Timer RC Status Register 0124h Timer RC I/O Control Register 0 0125h Timer RC I/O Control Register 1 0126h Timer RC Counter 0127h 0128h Timer RC General Register A 0129h 012Ah Timer RC General Register B 012Bh 012Ch Timer RC General Register C 012Dh 012Eh Timer RC General Register D 012Fh 0130h Timer RC Control Register 2 0131h Timer RC Digital Filter Function Select Register 0132h Timer RC Output Master Enable Register 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. TRESEC TREMIN 00h 00h TRECR1 TRECR2 TRECSR TRCMR TRCCR1 TRCIER TRCSR TRCIOR0 TRCIOR1 TRC TRCGRA TRCGRB TRCGRC TRCGRD TRCCR2 TRCDF TRCOER 00h 00h 00001000b 01001000b 00h 01110000b 01110000b 10001000b 10001000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00011111b 00h 01111111b Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 21 of 332 R8C/2E Group, R8C/2F Group 4. Special Function Registers (SFRs) Table 4.6 SFR Information (6)(1) Symbol After reset Address Register 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h Comparator 0 Control Register 0175h Comparator 1 Control Register 0176h 0177h Comparator Mode Register 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. ACCR0 ACCR1 ACMR 00001000b 00001000b 00h Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 22 of 332 R8C/2E Group, R8C/2F Group 4. Special Function Registers (SFRs) Table 4.7 Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh SFR Information (7)(1) Register Symbol After reset Flash Memory Control Register 4 Flash Memory Control Register1 Flash Memory Control Register 0 FMR4 FMR1 FMR0 01000000b 1000000Xb 00000001b FFFFh Option Function Select Register X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. The OFS register cannot be changed by a program. Use a flash programmer to write to it. OFS (Note 2) Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 23 of 332 R8C/2E Group, R8C/2F Group 5. Resets 5. Resets The following resets are implemented: hardware reset, power-on reset, voltage monitor 1 reset, voltage monitor 2 reset, watchdog timer reset, and software reset. Table 5.1 lists the Reset Names and Sources. Figure 5.1 shows the Block Diagram of Reset Circuit. Table 5.1 Reset Names and Sources Reset Name Hardware reset Power-on reset Voltage monitor 1 reset Voltage monitor 2 reset Watchdog timer reset Software reset Source Input voltage of RESET pin is held “L” VCC rises VCC falls (monitor voltage: Vdet1) VCC falls (monitor voltage: Vdet2) Underflow of watchdog timer Write 1 to PM03 bit in PM0 register RESET Hardware reset SFRs VCC Power-on reset circuit b5 bit in VCA2 register Power-on reset Voltage monitor 1 reset Voltage detection circuit SFRs Bits VCA13, VCA26, VCA27, VW1C2, VW1C3, VW2C2, VW2C3 Voltage monitor 2 reset Watchdog timer Watchdog timer reset CPU Pin, CPU, and SFR bits other than those listed above Software reset VCA13: Bit in VCA1 register VCA26, VCA27: Bits in VCA2 register VW1C2, VW1C3: Bits in VW1C register VW2C2, VW2C3: Bits in VW2C register Figure 5.1 Block Diagram of Reset Circuit Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 24 of 332 R8C/2E Group, R8C/2F Group 5. Resets Table 5.2 shows the Pin Functions while RESET Pin Level is “L”, Figure 5.2 shows the CPU Register Status after Reset, Figure 5.3 shows the Reset Sequence, and Figure 5.4 shows the OFS Register. Table 5.2 Pin Functions while RESET Pin Level is “L” Pin Functions Input port Input port Input port Input port Pin Name P0, P1 P3_1, P3_3 to P3_7 P4_2, P4_5 to P4_7 P5_3, P5_4 b15 b0 0000h 0000h 0000h 0000h 0000h 0000h 0000h b19 b0 Data register(R0) Data register(R1) Data register(R2) Data register(R3) Address register(A0) Address register(A1) Frame base register(FB) 00000h Content of addresses 0FFFEh to 0FFFCh b15 b0 Interrupt table register(INTB) Program counter(PC) 0000h 0000h 0000h b15 b0 User stack pointer(USP) Interrupt stack pointer(ISP) Static base register(SB) 0000h b15 b8 b7 b0 Flag register(FLG) IPL U I OBSZDC Figure 5.2 CPU Register Status after Reset fOCO-S RESET pin 10 cycles or more are needed(1) fOCO-S clock × 32 cycles(2) Internal reset signal Start time of flash memory (CPU clock × 14 cycles) CPU clock × 28 cycles CPU clock 0FFFCh Address (internal address signal) 0FFFDh Content of reset vector 0FFFEh NOTES: 1. Hardware reset. 2. When the “L” input width to the RESET pin is set to fOCO-S clock × 32 cycles or more, setting the RESET pin to “H” also sets the internal reset signal to “H” at the same. Figure 5.3 Reset Sequence Page 25 of 332 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 R8C/2E Group, R8C/2F Group 5. Resets Option Function Select Register(1) b7 b6 b5 b4 b3 b2 b1 b0 101 1 Symbol OFS Bit Symbol WDTON — (b1) ROMCR ROMCP1 — (b4) — (b5) — (b6) Address 0FFFFh Bit Name Watchdog timer start select bit Reserved bit ROM code protect disabled bit ROM code protect bit Reserved bit Reserved bit Reserved bit When Shipping FFh(2) Function 0 : Starts w atchdog timer automatically after reset 1 : Watchdog timer is inactive after reset Set to 1. 0 : ROM code protect disabled 1 : ROMCP1 enabled 0 : ROM code protect enabled 1 : ROM code protect disabled Set to 1. Set to 0. Set to 1. 0 : Count source protect mode enabled after reset 1 : Count source protect mode disabled after reset RW RW RW RW RW RW RW RW Count source protect CSPROINI mode after reset select bit RW NOTES: 1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not w rite additions to the OFS register. 2. If the block including the OFS register is erased, FFh is set to the OFS register. Figure 5.4 OFS Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 26 of 332 R8C/2E Group, R8C/2F Group 5. Resets 5.1 Hardware Reset A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the supply voltage meets the recommended operating conditions, pins, CPU, and SFRs are all reset (refer to Table 5.2 Pin Functions while RESET Pin Level is “L”). When the input level applied to the RESET pin changes from “L” to “H”, a program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected as the CPU clock. Refer to 4. Special Function Registers (SFRs) for the state of the SFRs after reset. The internal RAM is not reset. If the RESET pin is pulled “L” while writing to the internal RAM is in progress, the contents of internal RAM will be undefined. Figure 5.5 shows an Example of Hardware Reset Circuit and Operation and Figure 5.6 shows an Example of Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation. 5.1.1 When Power Supply is Stable (1) Apply “L” to the RESET pin. (2) Wait for 10 µs or more. (3) Apply “H” to the RESET pin. 5.1.2 Power On (1) Apply “L” to the RESET pin. (2) Let the supply voltage increase until it meets the recommended operating conditions. (3) Wait for td(P-R) or more to allow the internal power supply to stabilize (refer to 21. Electrical Characteristics). (4) Wait for 10 µs or more. (5) Apply “H” to the RESET pin. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 27 of 332 R8C/2E Group, R8C/2F Group 5. Resets VCC VCC 0V RESET RESET 2.2 V 0.2 VCC or below 0V td(P-R) + 10 µs or more NOTE: 1. Refer to 21. Electrical Characteristics. Figure 5.5 Example of Hardware Reset Circuit and Operation Supply voltage detection circuit 5V VCC 2.2 V RESET VCC 0V 5V RESET 0V td(P-R) + 10 µs or more Example when VCC = 5 V NOTE: 1. Refer to 21. Electrical Characteristics. Figure 5.6 Example of Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 28 of 332 R8C/2E Group, R8C/2F Group 5. Resets 5.2 Power-On Reset Function When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises while the rise gradient is trth or more, the power-on reset function is enabled and the MCU resets its pins, CPU, and SFR. When a capacitor is connected to the RESET pin, too, always keep the voltage to the RESET pin 0.8VCC or more. When the input voltage to the VCC pin reaches the maximum 2.6 V or above, the low-speed on-chip oscillator clock starts counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H” and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock divided by 8 is automatically selected as the CPU clock after reset. Refer to 4. Special Function Registers (SFRs) for the states of the SFR after power-on reset. Figure 5.7 shows an Example of Power-On Reset Circuit and Operation. VCC 4.7 kΩ (reference) RESET max. 2.6 V 2.2 V External Power VCC Vpor1 tw(por1) Sampling time(1, 2) trth Vpor2 trth max. 2.6 V Internal reset signal (“L” valid) 1 × 32 fOCO-S NOTES: 1. Ensure that the voltage is 2.2 V or above during the sampling time. 2. The sampling time is fOCO-S divided by 1 × 4 cycles. 3. Refer to 21. Electrical Characteristics. 1 × 32 fOCO-S Figure 5.7 Example of Power-On Reset Circuit and Operation Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 29 of 332 R8C/2E Group, R8C/2F Group 5. Resets 5.3 Voltage Monitor 1 Reset A reset is applied using the on-chip voltage detection 1 circuit. The voltage detection 1 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet1. When the input voltage to the VCC pin drops the Vdet1 level or below, the pins, CPU, and SFR are reset and a program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected as the CPU clock. The voltage monitor 1 does not reset some portions of the SFR. Refer to 4. Special Function Registers (SFRs) for details. The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet1 level or below while writing to the internal RAM is in progress, the contents of internal RAM are undefined. Refer to 6. Voltage Detection Circuit for details of voltage monitor 1 reset. 5.4 Voltage Monitor 2 Reset A reset is applied using the on-chip voltage detection 2 circuit. The voltage detection 2 circuit monitors the input voltage to the VCC pin. The voltage monitored is Vdet2. When the input voltage to the VCC pin drops the Vdet2 level or below, the pins, CPU, and SFR are reset and the program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected as the CPU clock. The voltage monitor 2 does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details. The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet2 level or below while writing to the internal RAM is in progress, the contents of internal RAM are undefined. Refer to 6. Voltage Detection Circuit for details of voltage monitor 2 reset. 5.5 Watchdog Timer Reset When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins, CPU, and SFR if the watchdog timer underflows. Then the program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected as the CPU clock. The watchdog timer reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details. The internal RAM is not reset. When the watchdog timer underflows, the contents of internal RAM are undefined. Refer to 13. Watchdog Timer for details of the watchdog timer. 5.6 Software Reset When the PM03 bit in the PM0 register is set to 1 (MCU reset), the MCU resets its pins, CPU, and SFR. The program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected for the CPU clock. The software reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details. The internal RAM is not reset. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 30 of 332 R8C/2E Group, R8C/2F Group 6. Voltage Detection Circuit 6. Voltage Detection Circuit The voltage detection circuit monitors the input voltage to the VCC pin. This circuit can be used to monitor the VCC input voltage by a program. Alternately, voltage monitor 1 interrupt, voltage monitor 1 reset, voltage monitor 2 interrupt, and voltage monitor 2 reset can also be used. Table 6.1 lists the Specifications of Voltage Detection Circuit and Figures 6.1 to 6.3 show the Block Diagrams. Figures 6.4 to 6.6 show the Associated Registers. Table 6.1 VCC Monitor Specifications of Voltage Detection Circuit Item Voltage to monitor Detection target Monitor Voltage Detection 1 Vdet1 Passing through Vdet1 by rising or falling VW1C3 bit in VW1C register Whether VCC is higher or lower than Vdet1 Voltage monitor 1 reset Reset at Vdet1 > VCC; restart CPU operation after a specified time Voltage monitor 1 interrupt Interrupt request at Vdet1 > VCC and VCC > Vdet1 when digital filter is enabled; interrupt request at Vdet1 > VCC or VCC > Vdet1 when digital filter is disabled Available (Divide-by-n of fOCO-S) × 4 n: 1, 2, 4, and 8 Voltage Detection 2 Vdet2 Passing through Vdet2 by rising or falling VCA13 bit in VCA1 register Whether VCC is higher or lower than Vdet2 Voltage monitor 2 reset Reset at Vdet2 > VCC; restart CPU operation after a specified time Voltage monitor 2 interrupt Interrupt request at Vdet2 > VCC and VCC > Vdet2 when digital filter is enabled; interrupt request at Vdet2 > VCC or VCC > Vdet2 when digital filter is disabled Available (Divide-by-n of fOCO-S) × 4 n: 1, 2, 4, and 8 Process Reset When Voltage is Detected Interrupt Digital Filter Switch enabled/disabled Sampling time VCC VCA27 + Internal reference voltage Noise filter ≥ Vdet2 Voltage detection 2 signal - VCA1 register b3 VCA26 VCA13 bit + - Noise filter ≥ Vdet1 Voltage detection 1 signal VW1C register b3 VW1C3 bit Figure 6.1 Block Diagram of Voltage Detection Circuit Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 31 of 332 R8C/2E Group, R8C/2F Group 6. Voltage Detection Circuit Voltage monitor 1 interrupt/reset generation circuit VW1F1 to VW1F0 = 00b = 01b Voltage detection 1 circuit fOCO-S VCA26 VW1C3 VCC Internal reference voltage + Noise filter (Filter width: 200 ns) Voltage detection 1 signal = 10b 1/2 1/2 1/2 = 11b VW1C2 bit is set to 0 (not detected) by writing 0 by a program. When VCA26 bit is set to 0 (voltage detection 1 circuit disabled), VW1C2 bit is set to 0 VW1C1 Watchdog timer interrupt signal VW1C2 Digital filter Voltage detection 1 signal is held “H” when VCA26 bit is set to 0 (disabled) VW1C1 Voltage monitor 1 interrupt signal Non-maskable interrupt signal Oscillation stop detection interrupt signal VW1C7 VW1C0 VW1C6 Voltage monitor 1 reset signal VW1C0 to VW1C3, VW1F0, VW1F1, VW1C6, VW1C7: Bits in VW1C register VCA26: Bit in VCA2 register Figure 6.2 Block Diagram of Voltage Monitor 1 Interrupt/Reset Generation Circuit Voltage monitor 2 interrupt/reset generation circuit VW2F1 to VW2F0 = 00b = 01b Voltage detection 2 circuit fOCO-S VCA27 VCA13 VCC Internal reference voltage + Noise filter (Filter width: 200 ns) Voltage detection 2 signal = 10b 1/2 1/2 1/2 = 11b VW2C2 bit is set to 0 (not detected) by writing 0 by a program. When VCA27 bit is set to 0 (voltage detection 2 circuit disabled), VW2C2 bit is set to 0 VW2C1 Digital filter Watchdog timer interrupt signal VW2C2 Voltage detection 2 signal is held “H” when VCA27 bit is set to 0 (disabled) VW2C1 Voltage monitor 2 interrupt signal Non-maskable interrupt signal Watchdog timer block VW2C3 VW2C7 Watchdog timer underflow signal VW2C0 VW2C6 Oscillation stop detection interrupt signal This bit is set to 0 (not detected) by writing 0 by a program. Voltage monitor 2 reset signal VW2C0 to VW2C3, VW2F0, VW2F1, VW2C6, VW2C7: Bits in VW2C register VCA13: Bit in VCA1 register VCA27: Bit in VCA2 register Figure 6.3 Block Diagram of Voltage Monitor 2 Interrupt/Reset Generation Circuit Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 32 of 332 R8C/2E Group, R8C/2F Group 6. Voltage Detection Circuit Voltage Detection Register 1 b7 b6 b5 b4 b3 b2 b1 b0 0000 000 Symbol Address 0031h VCA1 Bit Symbol Bit Name Reserved bits — (b2-b0) VCA13 — (b7-b4) Voltage detection 2 signal monitor flag(1) Reserved bits After Reset(2) 00001000b Function Set to 0. 0 : VCC < Vdet2 1 : VCC ≥ V det2 or voltage detection 2 circuit disabled Set to 0. RW RW RO RW NOTES: 1. The VCA13 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled). The VCA13 bit is set to 1 (VCC ≥ V det 2) w hen the VCA27 bit in the VCA2 register is set to 0 (voltage detection 2 circuit disabled). 2. The softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this register. Voltage Detection Register 2(1) b7 b6 b5 b4 b3 b2 b1 b0 10000 Symbol VCA2 Bit Symbol VCA20 — (b4-b1) — (b5) VCA26 VCA27 Address 0032h Bit Name Internal pow er low consumption enable bit(5) Reserved bits Reserved bit Voltage detection 1 enable bit(2) Voltage detection 2 enable bit(3) After Reset(4) Pow er-on reset or hardw are reset : 00100000b Function 0 : Disables low consumption 1 : Enables low consumption Set to 0. Set to 1. 0 : Voltage detection 1 circuit disabled 1 : Voltage detection 1 circuit enabled 0 : Voltage detection 2 circuit disabled 1 : Voltage detection 2 circuit enabled RW RW RW RW RW RW NOTES: 1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VCA2 register. 2. To use the voltage monitor 1 interrupt/reset or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1. After the VCA26 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting operation. 3. To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1. After the VCA27 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting operation. 4. Softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this register. 5. Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in Figure 10.8 Procedure for Enabling Reduced Internal Pow er Consum ption Using VCA20 bit. Figure 6.4 Registers VCA1 and VCA2 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 33 of 332 R8C/2E Group, R8C/2F Group 6. Voltage Detection Circuit Voltage Monitor 1 Circuit Control Register (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol VW1C Bit Symbol VW1C0 Address 0036h Bit Name Voltage monitor 1 interrupt/reset 0 : Disable enable bit(6) 1 : Enable Voltage monitor 1 digital filter disable mode select bit(2) After Reset(8) 00001000b Function RW RW VW1C1 0 : Digital filter enabled mode (digital filter circuit enabled) 1 : Digital filter disabled mode (digital filter circuit disabled) 0 : Not detected 1 : Vdet1 pass detected 0 : VCC < Vdet1 1 : VCC ≥ V det1 or voltage detection 1 circuit disabled b5 b4 RW VW1C2 Voltage change detection flag(3, 4, 8) Voltage detection 1 signal monitor flag(3, 8) Sampling clock select bits RW VW1C3 RO VW1F0 VW1F1 VW1C6 Voltage monitor 1 circuit mode select bit(5) 0 0 : fOCO-S divided by 0 1 : fOCO-S divided by 1 0 : fOCO-S divided by 1 1 : fOCO-S divided by 1 2 4 8 RW RW RW 0 : Voltage monitor 1 interrupt mode 1 : Voltage monitor 1 reset mode VW1C7 Voltage monitor 1 interrupt/reset 0 : When VCC reaches Vdet1 or above generation condition select 1 : When VCC reaches Vdet1 or below bit(7,9) RW NOTES: 1. Set the PRC3 bit in the PRCR register to 1 (rew rite enable) before w riting to the VW1C register. 2. To use the voltage monitor 1 interrupt to exit stop mode and to return again, w rite 0 to the VW1C1 bit before w riting 1. 3. Bits VW1C2 and VW1C3 are enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled). 4. Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is w ritten to it). 5. The VW1C6 bit is enabled w hen the VW1C0 bit is set to 1 (voltage monitor 1 interrupt/enabled reset). 6. The VW1C0 bit is enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled). Set the VW1C0 bit to 0 (disable) w hen the VCA26 bit is set to 0 (voltage detection 1 circuit disabled). 7. The VW1C7 bit is enabled w hen the VW1C1 bit is set to 1 (digital filter disabled mode). 8. Bits VW1C2 and VW1C3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset. 9. When the VW1C6 bit is set to 1 (voltage monitor 1 reset mode), set the VW1C7 bit to 1 (w hen VCC reaches Vdet1 or below ). (Do not set to 0.) Figure 6.5 VW1C Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 34 of 332 R8C/2E Group, R8C/2F Group 6. Voltage Detection Circuit Voltage Monitor 2 Circuit Control Register (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol VW2C Bit Symbol VW2C0 Address 0037h Bit Name Voltage monitor 2 interrupt/reset 0 : Disable enable bit(6) 1 : Enable Voltage monitor 2 digital filter disable mode select bit(2) After Reset(8) 00h Function RW RW VW2C1 0 : Digital filter enabled mode (digital filter circuit enabled) 1 : Digital filter disabled mode (digital filter circuit disabled) 0 : Not detected 1 : VCC has crossed Vdet2 0 : Not detected 1 : Detected b5 b4 RW VW2C2 VW2C3 VW2F0 Voltage change detection flag(3,4,8) WDT detection flag(4,8) Sampling clock select bits RW RW RW VW2F1 VW2C6 Voltage monitor 2 circuit mode select bit(5) 0 0 : fOCO-S divided by 0 1 : fOCO-S divided by 1 0 : fOCO-S divided by 1 1 : fOCO-S divided by 1 2 4 8 RW RW 0 : Voltage monitor 2 interrupt mode 1 : Voltage monitor 2 reset mode VW2C7 Voltage monitor 2 interrupt/reset 0 : When VCC reaches Vdet2 or above 1 : When VCC reaches Vdet2 or below generation condition select bit(7,9) RW NOTES: 1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VW2C register. 2. To use the voltage monitor 2 interrupt to exit stop mode and to return again, w rite 0 to the VW2C1 bit before w riting 1. 3. The VW2C2 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled). 4. Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is w ritten to it). 5. The VW2C6 bit is enabled w hen the VW2C0 bit is set to 1 (voltage monitor 2 interrupt/enables reset). 6. The VW2C0 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled). Set the VW2C0 bit to 0 (disable) w hen the VCA27 bit is set to 0 (voltage detection 2 circuit disabled). 7. The VW2C7 bit is enabled w hen the VW2C1 bit is set to 1 (digital filter disabled mode). 8. Bits VW2C2 and VW2C3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset. 9. When the VW2C6 bit is set to 1 (voltage monitor 2 reset mode), set the VW2C7 bit to 1 (w hen VCC reaches Vdet2 or below ). (Do not set to 0.) Figure 6.6 VW2C Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 35 of 332 R8C/2E Group, R8C/2F Group 6. Voltage Detection Circuit 6.1 6.1.1 VCC Input Voltage Monitoring Vdet1 Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled). After td(E-A) has elapsed (refer to 21. Electrical Characteristics), Vdet1 can be monitored by the VW1C3 bit in the VW1C register. 6.1.2 Monitoring Vdet2 Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled). After td(E-A) has elapsed (refer to 21. Electrical Characteristics), Vdet2 can be monitored by the VCA13 bit in the VCA1 register. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 36 of 332 R8C/2E Group, R8C/2F Group 6. Voltage Detection Circuit 6.2 Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Table 6.2 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset. Figure 6.7 shows an Example of Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Operation. To use the voltage monitor 1 interrupt or voltage monitor 1 reset to exit stop mode, set the VW1C1 bit in the VW1C register to 1 (digital filter disabled). Table 6.2 Step 1 2 3 4(2) 5(2) Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset When Using Digital Filter When Not Using Digital Filter Voltage Monitor 1 Voltage Monitor 1 Voltage Monitor 1 Voltage Monitor 1 Interrupt Reset Interrupt Reset Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled) Wait for td(E-A) Select the sampling clock of the digital filter Select the timing of the interrupt and reset request by the VW1C7 bit in the VW1C by the VW1F0 to VW1F1 bits in the VW1C register register(1) Set the VW1C1 bit in the VW1C register to 0 Set the VW1C1 bit in the VW1C register to 1 (digital filter enabled) (digital filter disabled) Set the VW1C6 bit in Set the VW1C6 bit in Set the VW1C6 bit in Set the VW1C6 bit in the VW1C register to the VW1C register to the VW1C register to the VW1C register to 0 (voltage monitor 1 1 (voltage monitor 1 0 (voltage monitor 1 1 (voltage monitor 1 reset mode) interrupt mode) reset mode) interrupt mode) Set the VW1C2 bit in the VW1C register to 0 (passing of Vdet1 is not detected) Set the CM14 bit in the CM1 register to 0 − (low-speed on-chip oscillator on) Wait for 4 cycles of the sampling clock of the − (No wait time required) digital filter Set the VW1C0 bit in the VW1C register to 1 (voltage monitor 1 interrupt/reset enabled) 6 7 8 9 NOTES: 1. Set the VW1C7 bit to 1 (when VCC reaches Vdet1 or below) for the voltage monitor 1 reset. 2. When the VW1C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1 instruction). Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 37 of 332 R8C/2E Group, R8C/2F Group 6. Voltage Detection Circuit VCC Vdet1 1 VW1C3 bit 0 4 cycles of sampling clock of digital filter 1 VW1C2 bit 0 Set to 0 by a program When VW1C1 bit is set to 0 (digital filter enabled) Voltage monitor 1 interrupt request (VW1C6 = 0) Internal reset signal (VW1C6 = 1) Set to 0 by a program 1 When VW1C1 bit is set to 1 (digital filter disabled) and VW1C7 bit is set to 0 (Vdet1 or above) VW1C2 bit 0 Voltage monitor 1 interrupt request (VW1C6 = 0) Set to 0 by interrupt request acknowledgement Set to 0 by interrupt request acknowledgement 4 cycles of sampling clock of digital filter Set to 0 by a program 1 VW1C2 bit 0 When VW1C1 bit is set to 1 (digital filter disabled) and VW1C7 bit is set to 1 (Vdet1 or below) Voltage monitor 1 interrupt request (VW1C6 = 0) Internal reset signal (VW1C6 = 1) Set to 0 by interrupt request acknowledgement VW1C1, VW1C2, VW1C3, VW1C6, VW1C7: Bit in VW1C Register The above applies under the following conditions. • VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled) • VW1C0 bit in VW1C register = 1 (voltage monitor 1 interrupt and voltage monitor 1 reset enabled) Figure 6.7 Example of Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Operation Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 38 of 332 R8C/2E Group, R8C/2F Group 6. Voltage Detection Circuit 6.3 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset. Figure 6.8 shows an Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation. To use the voltage monitor 2 interrupt or voltage monitor 2 reset to exit stop mode, set the VW2C1 bit in the VW2C register to 1 (digital filter disabled). Table 6.3 Step 1 2 3 4 5(2) Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset When Using Digital Filter When Not Using Digital Filter Voltage Monitor 2 Voltage Monitor 2 Voltage Monitor 2 Voltage Monitor 2 Interrupt Reset Interrupt Reset Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled) Wait for td(E-A) Select the sampling clock of the digital filter Select the timing of the interrupt and reset request by the VW2C7 bit in the VW2C by the VW2F0 to VW2F1 bits in the VW2C register register(1) Set the VW2C1 bit in the VW2C register to 0 Set the VW2C1 bit in the VW2C register to 1 (digital filter enabled) (digital filter disabled) Set the VW2C6 bit in Set the VW2C6 bit in Set the VW2C6 bit in Set the VW2C6 bit in the VW2C register to the VW2C register to the VW2C register to the VW2C register to 0 (voltage monitor 2 1 (voltage monitor 2 0 (voltage monitor 2 1 (voltage monitor 2 reset mode) interrupt mode) reset mode) interrupt mode) Set the VW2C2 bit in the VW2C register to 0 (passing of Vdet2 is not detected) Set the CM14 bit in the CM1 register to 0 − (low-speed on-chip oscillator on) Wait for 4 cycles of the sampling clock of the − (No wait time required) digital filter Set the VW2C0 bit in the VW2C register to 1 (voltage monitor 2 interrupt/reset enabled) 6 7 8 9 NOTES: 1. Set the VW2C7 bit to 1 (when VCC reaches Vdet2 or below) for the voltage monitor 2 reset. 2. When the VW2C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1 instruction). Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 39 of 332 R8C/2E Group, R8C/2F Group 6. Voltage Detection Circuit VCC Vdet2 1 VCA13 bit 0 4 cycles of sampling clock of digital filter 1 VW2C2 bit 0 Set to 0 by a program When VW2C1 bit is set to 0 (digital filter enabled) Set to 0 by interrupt request acknowledgement 4 cycles of sampling clock of digital filter Voltage monitor 2 interrupt request (VW2C6 = 0) Internal reset signal (VW2C6 = 1) Set to 0 by a program 1 When VW2C1 bit is set to 1 (digital filter disabled) and VW2C7 bit is set to 0 (Vdet2 or above) VW2C2 bit 0 Voltage monitor 2 interrupt request (VW2C6 = 0) Set to 0 by interrupt request acknowledgement Set to 0 by a program 1 VW2C2 bit 0 When VW2C1 bit is set to 1 (digital filter disabled) and VW2C7 bit is set to 1 (Vdet2 or below) Voltage monitor 2 interrupt request (VW2C6 = 0) Internal reset signal (VW2C6 = 1) Set to 0 by interrupt request acknowledgement VCA13: Bit in VCA1 register VW2C1, VW2C2, VW2C6, VW2C7: Bits in VW2C register The above applies under the following conditions. • VCA27 bit in VCA2 register = 1 (voltage detection 2 circuit enabled) • VW2C0 bit in VW2C register = 1 (voltage monitor 2 interrupt and voltage monitor 2 reset enabled) Figure 6.8 Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 40 of 332 R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports 7. Programmable I/O Ports There are 25 programmable Input/Output ports (I/O ports) P0, P1, P3_1, P3_3 to P3_7, P4_5, P5_3, and P5_4. Also, P4_6 and P4_7 can be used as input-only ports if the XIN clock oscillation circuit is not used, and the P4_2 can be used as an input-only port if the A/D converter is not used. Table 7.1 lists an Overview of Programmable I/O Ports. Table 7.1 Ports P0, P1 P3_1, P3_3 to P3_7 P4_5 P5_3, P5_4 P4_2(2) P4_6, P4_7(3) Overview of Programmable I/O Ports I/O I/O I/O I/O I/O I Type of Output CMOS3 State CMOS3 State CMOS3 State CMOS3 State (No output function) I/O Setting Set per bit Set per bit Set per bit Set per bit None Internal Pull-Up Resister Set every 4 bits(1) Set every 2 bits, 4 bits(1) Set every bit(1) Set every bit(1) None NOTES: 1. In input mode, whether an internal pull-up resistor is connected or not can be selected by registers PUR0 and PUR1. 2. When the A/D converter is not used, this port can be used as the input-only port. 3. When the XIN clock oscillation circuit is not used, these ports can be used as the input-only ports. 7.1 Functions of Programmable I/O Ports The PDi_j (j = 0 to 7) bit in the PDi (i = 0, 1, 3 to 5) register controls I/O of the ports P0, P1, P3_1, P3_3 to P3_7, P4_5, P5_3, and P5_4. The Pi register consists of a port latch to hold output data and a circuit to read pin states. Figures 7.1 to 7.5 show the Configurations of Programmable I/O Ports. Table 7.2 lists the Functions of Programmable I/O Ports. Also, Figure 7.7 shows the PDi (i = 0, 1, and 3 to 5) Register. Figure 7.8 shows the Pi (i = 0, 1, and 3 to 5) Register, Figure 7.9 shows Registers PINSR2 and PINSR3, Figure 7.10 shows the PMR Register, Figure 7.11 shows Registers PUR0 and PUR1, and Figure 7.12 shows the P1DRR Register. Table 7.2 Functions of Programmable I/O Ports Operation When Value of PDi_j Bit in PDi Register(1) Accessing When PDi_j Bit is Set to 0 (Input Mode) When PDi_j Bit is Set to 1 (Output Mode) Pi Register Reading Read pin input level Read the port latch Write to the port latch. The value written to Writing Write to the port latch the port latch is output from the pin. i = 0, 1, 3 to 5 j = 0 to 7 NOTE: 1. Nothing is assigned to bits PD3_0, PD3_2, PD4_0 to PD4_4, PD4_6, and PD4_7. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 41 of 332 R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports 7.2 Effect on Peripheral Functions Programmable I/O ports function as I/O ports for peripheral functions (Refer to Table 1.7 Pin Name Information by Pin Number). Table 7.3 lists the Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 0, 1, 3 to 5 j = 0 to 7). Refer to the description of each function for information on how to set peripheral functions. Table 7.3 Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 0, 1, 3 to 5 j = 0 to 7) I/O of Peripheral Functions PDi_j Bit Settings for Shared Pin Functions Input Set this bit to 0 (input mode). Output This bit can be set to either 0 or 1 (output regardless of the port setting) 7.3 Pins Other than Programmable I/O Ports Figure 7.6 shows the Configuration of I/O Pins. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 42 of 332 R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports P0 Direction register Pull-up selection (Note 1) Data bus Port latch (Note 1) Analog input Drive capacity select P1_0 to P1_3 Direction register Pull-up selection 1 (Note 1) Output from individual peripheral function Data bus Port latch (Note 1) Input to individual peripheral function Analog input Drive capacity select Drive capacity select Pull-up selection Direction register 1 (Note 1) Output from individual peripheral function P1_4 Data bus Port latch (Note 1) Drive capacity select NOTE: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. Figure 7.1 Configuration of Programmable I/O Ports (1) Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 43 of 332 R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports Drive capacity select P1_5 and P1_7 Pull-up selection Direction register 1 (Note 1) Output from individual peripheral function Data bus Port latch (Note 1) Input to external interrupt Digital filter Input to individual peripheral function Drive capacity select P1_6 Pull-up selection Direction register 1 Drive capacity select (Note 1) Output from individual peripheral function Data bus Port latch (Note 1) Input to individual peripheral function Drive capacity select NOTE: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. Figure 7.2 Configuration of Programmable I/O Ports (2) Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 44 of 332 R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports P3_1 Direction register Pull-up selection 1 (Note 1) Output from individual peripheral function Data bus Port latch (Note 1) P3_3 and P3_6 Direction register Pull-up selection 1 (Note 1) Output from individual peripheral function Data bus Port latch (Note 1) Input to individual peripheral function Input to external interrupt Digital filter P3_4, P3_5, and P3_7 Direction register Pull-up selection 1 (Note 1) Output from individual peripheral function Data bus Port latch (Note 1) Input to individual peripheral function NOTE: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. Figure 7.3 Configuration of Programmable I/O Ports (3) Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 45 of 332 R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports P4_2/VREF Data bus (Note 1) (Note 1) P4_5 Direction register Pull-up selection 1 (Note 1) Output from individual peripheral function Data bus Port latch (Note 1) Input to individual peripheral function Input to external interrupt Digital filter P4_6/XIN (Note 1) Data bus (Note 1) CM13 XIN oscillation circuit CM05 CM11 P4_7/XOUT RfXIN (Note 2) Data bus (Note 1) (Note 1) NOTES: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. 2. This pin is pulled up in one of the following conditions: • CM05 = CM13 = 1 • CM10 = CM13 = 1 • CM10 = 1 CM05: Bit in CM0 register CM10, CM13: Bits in CM1 register Figure 7.4 Configuration of Programmable I/O Ports (4) Page 46 of 332 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports P5_3 and P5_4 Direction register Pull-up selection 1 (Note 1) Output from individual peripheral function Data bus Port latch (Note 1) Input to individual peripheral function NOTE: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. Figure 7.5 Configuration of Programmable I/O Ports (5) MODE MODE signal input (Note 1) RESET RESET signal input (Note 1) NOTE: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. Figure 7.6 Configuration of I/O Pins Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 47 of 332 R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports Port Pi Direction Register (i = 0, 1, 3 to 5)(1, 2, 3, 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PD0 PD1 PD3 PD4 PD5 Bit Symbol PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7 Address 00E2h 00E3h 00E7h 00EAh 00EBh Bit Name Port Pi_0 direction bit Port Pi_1 direction bit Port Pi_2 direction bit Port Pi_3 direction bit Port Pi_4 direction bit Port Pi_5 direction bit Port Pi_6 direction bit Port Pi_7 direction bit After Reset 00h 00h 00h 00h 00h Function 0 : Input mode (functions as an input port) 1 : Output mode (functions as an output port) RW RW RW RW RW RW RW RW RW NOTES: 1. Set the PD0 register by using the next instruction after setting the PRC2 bit in the PRCR register to 1 (w rite enable). 2. Bits PD3_0 and PD3_2 in the PD3 register are unavailable on this MCU. If it is necessary to set bits PD3_0 and PD3_2, set to 0 (input mode). When read, the content is 0. 3. Bits PD4_0, PD4_1, PD4_3, PD4_4, PD4_6, and PD4_7 in the PD4 register are unavailable on this MCU. If it is necessary to set bits D4_0, PD4_1, PD4_3, PD4_4, PD4_6, and PD4_7, set to 0 (input mode). When read, the content is 0. 4. Bits PD5_0 to PD5_2 and PD5_5 to PD5_7 in the PD5 register are unavailable on this MCU. If it is necessary to set bits PD5_0 to PD5_2 and PD5_5 to PD5_7, set to 0 (input mode). When read, the content is 0. Figure 7.7 PDi (i = 0, 1, and 3 to 5) Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 48 of 332 R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports Port Pi Register (i = 0, 1, 3 to 5)(1, 2, 3) b7 b6 b5 b4 b3 b2 b1 b0 Symbol P0 P1 P3 P4 P5 Bit Symbol Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 Pi_5 Pi_6 Pi_7 Address 00E0h 00E1h 00E5h 00E8h 00E9h Bit Name Port Pi_0 bit Port Pi_1 bit Port Pi_2 bit Port Pi_3 bit Port Pi_4 bit Port Pi_5 bit Port Pi_6 bit Port Pi_7 bit After Reset 00h 00h 00h 00h 00h Function The pin level of any I/O port w hich is set to input mode can be read by reading the corresponding bit in this register. The pin level of any I/O port w hich is set to output mode can be controlled by w riting to the corresponding bit in this register. 0 : “L” level 1 : “H” level RW RW RW RW RW RW RW RW RW NOTES: 1. Bits P3_0 and P3_2 in the P3 register are unavailable on this MCU. If it is necessary to set bits P3_0 and P3_2, set to 0 (“L” level). When read, the content is 0. 2. Bits P4_0 to P4_4, P4_6, and P4_7 in the P4 register are unavailable on this MCU. If it is necessary to set bits P4_0 to P4_4, P4_6, and P4_7, set to 0 (“L” level). When read, the content is 0. 3. Bits P5_0 to P5_2, P5_5 to P5_7 in the P5 register are unavailable on this MCU. If it is necessary to set bits P5_0 to P5_2, P5_5 to P5_7, set to 0 (“L” level). When read, the content is 0. Figure 7.8 Pi (i = 0, 1, and 3 to 5) Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 49 of 332 R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports Pin Select Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 000000 Symbol PINSR2 Bit Symbol — (b5-b0) TRBOSEL — (b7) Address 00F6h Bit Name Reserved bits TRBO pin select bit Reserved bit After Reset 00h Function Set to 0. When read, the content is 0. 0 : P3_1 1 : P1_3 Set to 0. When read, the content is 0. RW RW RW RW Pin Select Register 3 b7 b6 b5 b4 b3 b2 b1 b0 1 111 Symbol PINSR3 Bit Symbol — (b2-b0) TRCIOCSEL TRCIODSEL — (b5) — (b7-b6) Address 00F7h Bit Name Reserved bits TRCIOC pin select bit TRCIOD pin select bit Reserved bit After Reset 00h Function Set to 1. When read, the content is 0. 0 : P5_3 1 : P3_4 0 : P5_4 1 : P3_5 Set to 1. When read, the content is 0. RW RW RW RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. Figure 7.9 Registers PINSR2 and PINSR3 Port Mode Register b7 b6 b5 b4 b3 b2 b1 b0 000 Symbol PMR Bit Symbol INT1SEL — (b3-b1) — (b6-b4) — (b7) Address 00F8h Bit Name ____ INT1 pin select bit After Reset 00h Function 0 : P1_5, P1_7 1 : P3_6 RW RW — RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. Reserved bits Set to 0. Nothing is assigned. If necessary, set to 0. When read, the content is 0. Figure 7.10 PMR Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 50 of 332 R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports Pull-Up Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol PUR0 Bit Symbol PU00 PU01 PU02 PU03 — (b5-b4) PU06 PU07 Address 00FCh Bit Name P0_0 to P0_3 pull-up(1) P0_4 to P0_7 pull-up(1) P1_0 to P1_3 pull-up(1) P1_4 to P1_7 pull-up(1) Reserved bits P3_1 and P3_3 pull-up(1) P3_4 to P3_7 pull-up(1) After Reset 00h Function 0 : Not pulled up 1 : Pulled up RW RW RW RW RW RW RW RW Set to 0. When read, the content is 0. 0 : Not pulled up 1 : Pulled up NOTE: 1. When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up. Pull-Up Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 00 0 Symbol Address 00FDh PUR1 Bit Symbol Bit Name — Reserved bit (b0) PU11 PU12 PU13 — (b5-b4) — (b7-b6) P4_5 pull-up(1) P5_3 pull-up(1) P5_4 pull-up(1) Reserved bits After Reset 00h Function Set to 0. When read, the content is 0. 0 : Not pulled up 1 : Pulled up Set to 0. When read, the content is 0. RW RW RW RW RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. NOTE: 1. When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up. Figure 7.11 Registers PUR0 and PUR1 Port P1 Drive Capacity Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol P1DRR Bit Symbol P1DRR0 P1DRR1 P1DRR2 P1DRR3 P1DRR4 P1DRR5 P1DRR6 P1DRR7 Address 00FEh Bit Name P1_0 drive capacity P1_1 drive capacity P1_2 drive capacity P1_3 drive capacity P1_4 drive capacity P1_5 drive capacity P1_6 drive capacity P1_7 drive capacity After Reset 00h Function Set P1 output transistor drive capacity 0 : Low 1 : High(1) RW RW RW RW RW RW RW RW RW NOTE: 1. Both “H” and “L” output are set to high drive capacity. Figure 7.12 P1DRR Register Page 51 of 332 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports 7.4 Port Setting Table 7.4 to Table 7.39 list the port setting. Table 7.4 Register Bit Setting value Port P0_0/AN7 PD0 PD0_0 0 1 0 1 CH2 ADCON0 CH1 CH0 ADGSEL0 Input port(1) Output port 0 A/D converter input (AN7) Other than 1110b Other than 1110b 1 1 Function NOTE: 1. Pulled up by setting the PU00 bit in the PUR0 register to 1. Table 7.5 Register Bit Setting value Port P0_1/AN6 PD0 PD0_1 0 1 0 CH2 X X 1 X X 1 ADCON0 CH1 CH0 X X 0 ADGSEL0 X X 0 Input port(1) Output port A/D converter input (AN6) Function X: 0 or 1 NOTE: 1. Pulled up by setting the PU00 bit in the PUR0 register to 1. Table 7.6 Register Bit Setting value Port P0_2/AN5/ACMP1 PD0 PD0_2 0 1 0 0 CH2 X X 1 X X X 0 X ADCON0 CH1 CH0 X X 1 X ADGSEL0 X X 0 X ACCR1 CM1E 0 0 0 1 Input port(1) Output port A/D converter input (AN5) ACMP1 input Function X: 0 or 1 NOTE: 1. Pulled up by setting the PU00 bit in the PUR0 register to 1. Table 7.7 Register Bit Port P0_3/AN4/AVREF1 PD0 PD0_3 0 1 0 0 CH2 X X 1 X X X 0 X ADCON0 CH1 CH0 X X 0 X ADGSEL0 X X 0 X 0 0 0 1 1 ACCR1 CM1E VR1SEL X X X 1 0 Function Input port(1) Output port A/D converter input (AN4) AVREF1 input Setting value X: 0 or 1 NOTE: 1. Pulled up by setting the PU00 bit in the PUR0 register to 1. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 52 of 332 R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports Table 7.8 Register Bit Port P0_4/AN3/TREO/ACMP0 PD0 PD0_4 0 1 0 X 0 TRECR1 TOENA 0 0 0 1 0 CH2 X X 0 X X X X 1 X X ADCON0 CH1 CH0 X X 1 X X ADGSEL0 X X 0 X X ACCR0 CM0E 0 0 0 0 1 Function Input port(1) Output port A/D converter input (AN3) TREO output ACMP0 input Setting value X: 0 or 1 NOTE: 1. Pulled up by setting the PU01 bit in the PUR0 register to 1. Table 7.9 Register Bit Port P0_5/AN2/AVREF0 PD0 PD0_5 0 CH2 X X X 0 X X X X 1 X ADCON0 CH1 CH0 X X X 0 X ADGSEL0 X X X 0 X 0 0 0 0 1 1 ACCR0 CM0E VR0SEL X X X X 1 0 Function Input port(1) Output port A/D converter input (AN2) AVREF0 input Setting value 1 0 0 X: 0 or 1 NOTE: 1. Pulled up by setting the PU01 bit in the PUR0 register to 1. Table 7.10 Register Bit Port P0_6/AN1/DA0 PD0 PD0_6 0 CH2 X X 0 X ADCON0 CH1 X X 0 X CH0 X X 1 X ADGSEL0 X X 0 X DACON DA0E 0 1 0 1 0 1 1 ACCR0 VR0SEL X 1 X 1 X 1 0 Function Input port(1) Output port A/D converter input (AN1) DA0 output Setting value 1 0 0 X: 0 or 1 NOTE: 1. Pulled up by setting the PU01 bit in the PUR0 register to 1. Table 7.11 Register Bit Port P0_7/AN0/DA1 PD0 PD0_7 0 CH2 X X 0 X ADCON0 CH1 X X 0 X CH0 X X 0 X ADGSEL0 X X 0 X DACON DA1E 0 1 0 1 0 1 1 ACCR1 VR1SEL X 1 X 1 X 1 0 Function Input port(1) Output port A/D converter input (AN0) DA1 output Setting value 1 0 0 X: 0 or 1 NOTE: 1. Pulled up by setting the PU01 bit in the PUR0 register to 1. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 53 of 332 R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports Table 7.12 Register Bit Setting value Port P1_0/KI0/AN8 PD1 PD1_0 0 1 0 0 KIEN KI0EN 0 0 1 0 CH2 X X X 1 X X X 0 ADCON0 CH1 CH0 X X X 0 ADGSEL0 X X X 1 Input port(1) Output port KI0 input(1) A/D converter input (AN8) Function X: 0 or 1 NOTE: 1. Pulled up by setting the PU02 bit in the PUR0 register to 1. Table 7.13 Register Bit Port P1_1/KI1/AN9/TRCIOA/TRCTRG PD1 0 1 0 KIEN 0 0 0 1 0 0 Timer RC Setting − Other than TRCIOA usage conditions Other than TRCIOA usage conditions Other than TRCIOA usage conditions Other than TRCIOA usage conditions Refer to Table 7.14 TRCIOA Pin Setting Refer to Table 7.14 TRCIOA Pin Setting CH2 X X 1 X X X X X 0 X X X ADCON0 CH1 CH0 ADGSEL0 X X 1 X X X X X 1 X X X PD1_1 KI1EN Function Input port(1) Output port A/D converter input (AN9) KI1 input(1) TRCIOA output TRCIOA input(1) Setting value 0 X 0 X: 0 or 1 NOTE: 1. Pulled up by setting the PU02 bit in the PUR0 register to 1. Table 7.14 Register Bit TRCIOA Pin Setting TRCOER EA 0 TRCMR PWM2 1 1 0 IOA2 0 0 1 X TRCIOR0 IOA1 0 1 X X Other than above IOA0 1 X X X X X X X 0 1 TRCCR2 TCEG1 TCEG2 X X X X 1 X Function Timer waveform output (output compare function) Timer mode (input capture function) PWM2 mode TRCTRG input Other than TRCIOA usage conditions Setting value 0 1 0 1 X: 0 or 1 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 54 of 332 R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports Table 7.15 Register Bit Port P1_2/KI2/AN10/TRCIOB PD1 0 1 0 KIEN 0 0 0 1 0 0 Timer RC Setting − Other than TRCIOB usage conditions Other than TRCIOB usage conditions Other than TRCIOB usage conditions Other than TRCIOB usage conditions Refer to Table 7.16 TRCIOB Pin Setting Refer to Table 7.16 TRCIOB Pin Setting CH2 X X 1 X X X X X 1 X X X ADCON0 CH1 CH0 ADGSEL0 X X 0 X X X X X 1 X X X PD1_2 KI2EN Function Input port(1) Output port A/D converter input (AN10) KI2 input(1) TRCIOB output TRCIOB input(1) Setting value 0 X 0 X: 0 or 1 NOTE: 1. Pulled up by setting the PU02 bit in the PUR0 register to 1. Table 7.16 Register Bit TRCIOB Pin Setting TRCOER EB 0 0 0 1 1 1 TRCMR PWM2 PWMB X 1 0 0 IOB2 X X 0 0 1 TRCIOR0 IOB1 X X 0 1 X IOB0 X X 1 X X Function PWM2 mode waveform output PWM mode waveform output Timer waveform output (output compare function) Timer mode (input capture function) Other than TRCIOB usage conditions Setting value 0 0 1 Other than above X: 0 or 1 Table 7.17 Register Bit Port P1_3/KI3/AN11/(TRBO) PD1 PD1_3 0 1 KIEN KI3EN 0 0 0 1 0 Timer RB Setting − Other than TRBO usage conditions Other than TRBO usage conditions Other than TRBO usage conditions Other than TRBO usage conditions Refer to Table 7.18 TRBO Pin Setting CH2 X X 1 X X X X 1 X X ADCON0 CH1 CH0 X X 1 X X ADGSEL0 X X 1 X X Function Input port(1) Output port A/D converter input (AN11) KI3 input TRBO output Setting value 0 0 X X: 0 or 1 NOTE: 1. Pulled up by setting the PU02 bit in the PUR0 register to 1. Table 7.18 Register Bit TRBO Pin Setting PINSR2 TRBOSEL 1 1 TRBIOC TOCNT(1) 0 0 0 1 TMOD1 0 1 1 0 TRBMR TMOD0 1 0 1 1 Function Programmable waveform generation mode Programmable one-shot generation mode Programmable wait one-shot generation mode P1_3 output port Other than TRBO usage conditions Setting value 1 1 Other than above NOTE: 1. Set the TOCNT bit in the TRBIOC register to 0 in modes except for programmable waveform generation mode. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 55 of 332 R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports Table 7.19 Register Bit Port P1_4/TXD0 PD1 PD1_4 0 1 SMD2 0 0 0 X 1 1 1 U0MR SMD1 0 0 0 0 0 1 SMD0 0 0 1 0 1 0 TXD0 output(2) Input port(1) Output port Function Setting value X: 0 or 1 NOTES: 1. Pulled up by setting the PU03 bit in the PUR0 register to 1. 2. N-channel open drain output by setting the NCH bit in the U0C0 register to 1. Table 7.20 Register Bit Port P1_5/RXD0/(TRAIO)/(INT1) PD1 PD1_5 0 0 1 1 1 0 1 0 1 1 0 1 1 1 X 1 TRAIOC TIOSEL TOPCR(3) X 1 0 X 0 X 0 0 0 1 0 0 0 0 0 TMOD2 X 0 0 X 0 X TRAMR TMOD1 X 0 0 X 0 X Other than 001b Other than 000b, 001b 0 0 0 0 1 1 TMOD0 X 1 0 X 0 X INTEN INT1EN X 0 0 X X X 0 0 1 1 1 X Output port RXD0 input(1) TRAIO input(1) INT1(2) TRAIO input/INT1(1, 2) TRAIO pulse output Input port(1) Function Setting value Other than 000b, 001b X: 0 or 1 NOTES: 1. Pulled up by setting the PU03 bit in the PUR0 register to 1. 2. Set the INT1SEL bit in the PMR register to 0 (P1_5, P1_7). 3. Set the TOPCR bit in the TRAIOC register to 0 in modes except for pulse output mode. Table 7.21 Register Bit Setting value Port P1_6/CLK0 PD1 PD1_6 0 1 X 0 CKDIR X X 0 1 0 X SMD2 X U0MR SMD1 X Other than 001b 0 X 1 X SMD0 X Input port(1) Output port CLK0 output CLK0 input(1) Function X: 0 or 1 NOTE: 1. Pulled up by setting the PU03 bit in the PUR0 register to 1. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 56 of 332 R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports Table 7.22 Register Bit Port P1_7/TRAIO/INT1 PD1 PD1_7 0 1 0 0 1 1 0 0 0 0 0 0 X 0 TRAIOC TIOSEL TOPCR(3) X 1 0 X 0 0 0 1 0 0 TMOD2 X 0 0 X 0 0 0 0 TRAMR TMOD1 X 0 0 X 0 0 0 0 TMOD0 X 1 0 X 0 0 1 1 INTEN INT1EN X 0 0 X X 0 1 1 1 X Output port TRAIO input(1) INT1(2) TRAIO input/INT1(1, 2) TRAIO pulse output Input port(1) Function Setting value Other than 000b, 001b Other than 000b, 001b X: 0 or 1 NOTES: 1. Pulled up by setting the PU03 bit in the PUR0 register to 1. 2. Set the INT1SEL bit in the PMR register to 0 (P1_5, P1_7). 3. Set the TOPCR bit in the TRAIOC register to 0 in modes except for pulse output mode. Table 7.23 Register Bit Setting value Port P3_1/TRBO PD3 PD3_1 0 1 X Timer RB Setting − Other than TRBO usage conditions Other than TRBO usage conditions Refer to Table 7.24 TRBO Pin Setting Input port(1) Output port TRBO output Function X: 0 or 1 NOTE: 1. Pulled up by setting the PU06 bit in the PUR0 register to 1. Table 7.24 Register Bit TRBO Pin Setting PINSR2 TRBOSEL 0 0 TRBIOC TOCNT(1) 0 0 0 1 TMOD1 0 1 1 1 TRBMR TMOD0 1 0 1 0 Function Programmable waveform generation mode Programmable one-shot generation mode Programmable wait one-shot generation mode P3_1 output port Other than TRBO usage conditions Setting value 0 0 Other than above NOTE: 1. Set the TOCNT bit in the TRBIOC register to 0 in modes except for programmable waveform generation mode. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 57 of 332 R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports Table 7.25 Register Bit Port P3_3/INT3/TRCCLK PD3 PD3_3 0 1 0 0 1 TCK2 TRCCR1 TCK1 Other than 101b Other than 101b Other than 101b 0 1 TCK0 INTEN INT3EN 0 0 1 0 Input port(1) Output port INT3 input(1) TRCCLK input(1) Function Setting value NOTE: 1. Pulled up by setting the PU06 bit in the PUR0 register to 1. Table 7.26 Register Bit Port P3_4/(TRCIOC) PD3 PD3_4 0 Timer RC setting − Other than TRCIOC usage conditions Other than TRCIOC usage conditions Other than TRCIOC usage conditions Other than TRCIOC usage conditions Refer to Table 7.27 TRCIOC Pin Setting Refer to Table 7.27 TRCIOC Pin Setting Input port(1) Output port TRCIOC output TRCIOC input(1) Function Setting value 1 X 0 X: 0 or 1 NOTE: 1. Pulled up by setting the PU07 bit in the PUR0 register to 1. Table 7.27 Register Bit TRCIOC Pin Setting PINSR3 TRCOER EC 0 0 0 1 1 1 1 TRCMR PWM2 PWMC 1 0 0 IOC2 X 0 0 1 TRCIOR1 IOC1 X 0 1 X IOC0 X 1 X X Function PWM mode waveform output Timer waveform output (output compare function) Timer mode (input capture function) Other than TRCIOC usage conditions TRCIOCSEL 1 1 Setting value 1 1 1 Other than above X: 0 or 1 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 58 of 332 R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports Table 7.28 Register Bit Setting value Port P3_5/(TRCIOD) PD3 PD3_5 0 1 X 0 Timer RC setting − Other than TRCIOD usage conditions Other than TRCIOD usage conditions Refer to Table 7.29 TRCIOD Pin Setting Refer to Table 7.29 TRCIOD Pin Setting Input port(1) Output port TRCIOD output TRCIOD input(1) Function X: 0 or 1 NOTE: 1. Pulled up by setting the PU07 bit in the PUR0 register to 1. Table 7.29 Register Bit TRCIOD Pin Setting PINSR3 TRCOER EC 0 0 0 1 1 1 1 TRCMR PWM2 PWMD 1 0 0 IOD2 X 0 0 1 TRCIOR1 IOD1 X 0 1 X IOD0 X 1 X X Function PWM mode waveform output Timer waveform output (output compare function) Timer mode (input capture function) Other than TRCIOD usage conditions TRCIODSEL 1 1 Setting value 1 1 1 Other than above X: 0 or 1 Table 7.30 Register Bit Setting value Port P3_6/(INT1) PD3 PD3_6 0 1 0 INTEN INT1EN 0 0 1 Input port(1) Output port INT1 input(1, 2) Function NOTES: 1. Pulled up by setting the PU07 bit in the PUR0 register to 1. 2. Set the INT1SEL bit in the PMR register to 1 (P3_6). Table 7.31 Register Bit Setting value Port P3_7/TRAO PD3 PD3_7 0 1 X TRAMR TOENA 0 0 1 Input port(1) Output port TRAO output Function X: 0 or 1 NOTE: 1. Pulled up by setting the PU07 bit in the PUR0 register to 1. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 59 of 332 R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports Table 7.32 Register Bit Setting value Port P4_2/VREF ADCON1 VCUT 0 1 Input port Input port/VREF input Function Table 7.33 Register Bit Setting value Port P4_5/INT0 PD4 PD4_5 0 1 0 INTEN INT0EN 0 0 1 Input port(1) Output port INT0 input(1) Function NOTE: 1. Pulled up by setting the PU11 bit in the PUR1 register to 1. Table 7.34 Register Bit Port P4_6/XIN CM0 CM05 1 CM13 0 CM1 CM11 X 0 0 1 ON 0 OFF OFF OFF 1 OFF OFF ON ON OFF OFF CM10 0 Circuit specifications Oscillation buffer OFF ON Feedback resistor − ON Input port XIN clock oscillation (on-chip feedback resistor enabled) XIN clock oscillation (on-chip feedback resistor disabled) External clock input XIN clock oscillation stop (on-chip feedback resistor enabled) XIN clock oscillation stop (on-chip feedback resistor disabled) XIN clock oscillation stop (stop mode) Function Setting value 1 0 1 0 1 1 X: 0 or 1 Table 7.35 Register Bit Port P4_7/XOUT CM0 CM05 1 CM13 0 CM1 CM11 X 0 0 1 ON 0 OFF OFF OFF 1 OFF OFF ON ON OFF OFF CM10 0 Circuit specifications Oscillation buffer OFF ON Feedback resistor − ON Input port XIN clock oscillation (on-chip feedback resistor enabled) XIN clock oscillation (on-chip feedback resistor disabled) External clock input XIN clock oscillation stop (on-chip feedback resistor enabled) XIN clock oscillation stop (on-chip feedback resistor disabled) XOUT pulled up Function Setting value 1 1 0 0 1 1 X: 0 or 1 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 60 of 332 R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports Table 7.36 Register Bit Port P5_3/TRCIOC/ACOUT0 PD5 PD5_3 0 1 X 0 X Timer RC setting − Other than TRCIOC usage conditions Other than TRCIOC usage conditions Refer to Table 7.37 TRCIOC Pin Setting Refer to Table 7.37 TRCIOC Pin Setting Other than TRCIOC usage conditions ACCR0 CM0OE 0 0 0 0 1 Input port(1) Output port TRCIOC output TRCIOC input(1) ACOUT0 output Function Setting value X: 0 or 1 NOTE: 1. Pulled up by setting the PU12 bit in the PUR1 register to 1. Table 7.37 Register Bit TRCIOC Pin Setting PINSR3 TRCOER EC 0 0 0 1 1 1 1 TRCMR PWM2 PWMC 1 0 0 IOC2 X 0 0 1 TRCIOR1 IOC1 X 0 1 X IOC0 X 1 X X Function PWM mode waveform output Timer waveform output (output compare function) Timer mode (input capture function) Other than TRCIOC usage conditions TRCIOCSEL 0 0 Setting value 0 0 0 Other than above X: 0 or 1 Table 7.38 Register Bit Port P5_4/TRCIOD/ACOUT1 PD5 PD5_4 0 1 X 0 X Timer RC setting − Other than TRCIOD usage conditions Other than TRCIOD usage conditions Refer to Table 7.39 TRCIOD Pin Setting Refer to Table 7.39 TRCIOD Pin Setting Other than TRCIOD usage conditions ACCR1 CM1OE 0 0 0 0 1 Input port(1) Output port TRCIOD output TRCIOD input(1) ACOUT1 output Function Setting value X: 0 or 1 NOTE: 1. Pulled up by setting the PU13 bit in the PUR1 register to 1. Table 7.39 Register Bit TRCIOD Pin Setting PINSR3 TRCOER ED 0 0 0 1 1 1 1 TRCMR PWM2 PWMD 1 0 0 IOD2 X 0 0 1 TRCIOR1 IOD1 X 0 1 X IOD0 X 1 X X Function PWM mode waveform output Timer waveform output (output compare function) Timer mode (input capture function) Other than TRCIOD usage conditions TRCIODSEL 0 0 Setting value 0 0 0 Other than above X: 0 or 1 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 61 of 332 R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports 7.5 Unassigned Pin Handling Table 7.40 lists Unassigned Pin Handling. Table 7.40 Unassigned Pin Handling Pin Name Connection Ports P0, P1, P3_1, P3_3 to P3_7, • After setting to input mode, connect each pin to VSS via a resistor P4_3 to P4_5, P5_3, P5_4 (pull-down) or connect each pin to VCC via a resistor (pull-up).(2) • After setting to output mode, leave these pins open.(1, 2) Ports P4_6, P4_7 Connect to VCC via a pull-up resistor(2) Port P4_2, VREF Connect to VCC RESET (3) Connect to VCC via a pull-up resistor(2) NOTES: 1. If these ports are set to output mode and left open, they remain in input mode until they are switched to output mode by a program. The voltage level of these pins may be undefined and the power current may increase while the ports remain in input mode. The content of the direction registers may change due to noise or program runaway caused by noise. In order to enhance program reliability, the program should periodically repeat the setting of the direction registers. 2. Connect these unassigned pins to the MCU using the shortest wire length (2 cm or less) possible. 3. When the power-on reset function is in use. MCU Port P0, P1, (Input mode ) : P3_1, P3_3 to P3_7, : P4_3 to P4_5, (Input mode) P5_3, P5_4 (Output mode) : : Open Port P4_6, P4_7 RESET(1) Port P4_2/VREF NOTE: 1. When the power-on reset function is in use. Figure 7.13 Unassigned Pin Handling Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 62 of 332 R8C/2E Group, R8C/2F Group 8. Processor Mode 8. 8.1 Processor Mode Processor Modes Single-chip mode can be selected as the processor mode. Table 8.1 lists Features of Processor Mode. Figure 8.1 shows the PM0 Register and Figure 8.2 shows the PM1 Register. Table 8.1 Features of Processor Mode Accessible Areas Pins Assignable as I/O Port Pins SFR, internal RAM, internal ROM All pins are I/O ports or peripheral function I/O pins Processor Mode Single-chip mode Processor Mode Register 0(1) b7 b6 b5 b4 b3 b2 b1 b0 000 Symbol Address PM0 0004h Bit Symbol Bit Name Reserved bits — (b2-b0) PM03 — (b7-b4) Softw are reset bit After Reset 00h Function Set to 0. The MCU is reset w hen this bit is set to 1. When read, the content is 0. RW RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. NOTE: 1. Set the PRC1 bit in the PRCR register to 1 (w rite enable) before rew riting the PM0 register. Figure 8.1 PM0 Register Processor Mode Register 1(1) b7 b6 b5 b4 b3 b2 b1 b0 0 00 Symbol Address PM1 0005h Bit Symbol Bit Name — Reserved bits (b1-b0) PM12 — (b6-b3) — (b7) WDT interrupt/reset sw itch bit After Reset 00h Function Set to 0. 0 : Watchdog timer interrupt 1 : Watchdog timer reset(2) RW RW RW — RW Nothing is assigned. If necessary, set to 0. When read, the content is 0. Reserved bit Set to 0. NOTES: 1. Set the PRC1 bit in the PRCR register to 1 (w rite enable) before rew riting the PM1 register. 2. The PM12 bit is set to 1 by a program (It remains unchanged even if 0 is w ritten to it). When the CSPRO bit in the CSPR register is set to 1 (count source protect mode enabled), the PM12 bit is automatically s et to 1. Figure 8.2 PM1 Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 63 of 332 R8C/2E Group, R8C/2F Group 9. Bus 9. Bus The bus cycles differ when accessing ROM/RAM, and when accessing SFR. Table 9.1 lists Bus Cycles by Access Space of the R8C/2E Group and Table 9.2 lists Bus Cycles by Access Space of the R8C/2F Group. ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units, these areas are accessed twice in 8-bit units. Table 9.3 lists Access Units and Bus Operations. Table 9.1 Bus Cycles by Access Space of the R8C/2E Group Bus Cycle 2 cycles of CPU clock 1 cycle of CPU clock Access Area SFR ROM/RAM Table 9.2 Bus Cycles by Access Space of the R8C/2F Group Bus Cycle 2 cycles of CPU clock 1 cycle of CPU clock Access Area SFR/Data flash Program ROM/RAM Table 9.3 Area Even address Byte access Access Units and Bus Operations SFR, data flash CPU clock Address Data Even Data ROM (program ROM), RAM CPU clock Address Data CPU clock Odd Data Address Data CPU clock Even Data Even+1 Data Address Data CPU clock Odd Data Odd+1 Data Address Data Odd Data Odd+1 Data Even Data Even+1 Data Odd Data Even Data Odd address Byte access CPU clock Address Data Even address Word access CPU clock Address Data Odd address Word access CPU clock Address Data However, only following SFRs are connected with the 16-bit bus: Timer RC: registers TRC, TRCGRA, TRCGRB, TRCGRC, and TRCGRD Therefore, when accessing in word (16-bit) unit, 16-bit data is accessed at a time. The bus operation is the same as “Area: SFR, data flash, even address byte access” in Table 9.3 Access Units and Bus Operations, and 16-bit data is accessed at a time. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 64 of 332 R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit 10. Clock Generation Circuit The clock generation circuit has: • XIN clock oscillation circuit • Low-speed on-chip oscillator • High-speed on-chip oscillator Table 10.1 lists Specifications of Clock Generation Circuit. Figure 10.1 shows a Clock Generation Circuit. Figures 10.2 to 10.7 show clock associated registers. Table 10.1 Item Applications Specifications of Clock Generation Circuit XIN Clock Oscillation Circuit • CPU clock source • Peripheral function clock source On-Chip Oscillator High-Speed On-Chip Oscillator Low-Speed On-Chip Oscillator • CPU clock source • CPU clock source • Peripheral function clock • Peripheral function clock source source • CPU and peripheral function • CPU and peripheral function clock sources when XIN clock clock sources when XIN clock stops oscillating stops oscillating (3) Approx. 125 kHz Approx. 40 MHz − −(1) Usable Stop − − −(1) Usable Oscillate − Clock frequency Connectable oscillator Oscillator connect pins Oscillation stop, restart function Oscillator status after reset Others 0 to 20 MHz • Ceramic resonator • Crystal oscillator XIN, XOUT(1) Usable Stop • Externally generated clock can be input(2) • On-chip feedback resistor RfXIN (connected/ not connected, selectable) NOTES: 1. These pins can be used as P4_6 or P4_7 when using the on-chip oscillator clock as the CPU clock while the XIN clock oscillation circuit is not used. 2. Set the CM05 bit in the CM0 register to 1 (XIN clock stopped) and the CM13 bit in the CM1 register to 1 (XINXOUT pin) when an external clock is input. 3. The clock frequency is automatically set to up to 20 MHz by a divider when using the high-speed on-chip oscillator as the CPU clock source. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 65 of 332 R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit FRA1 register Frequency adjustable FRA00 High-speed on-chip oscillator fOCO40M FRA2 register Divider fOCO-F FRA01 = 1 FRA01 = 0 On-chip oscillator clock fOCO INT0 Divider (1/128) fOCO128 Watchdog timer Timer RA A/D Timer RB Timer RC Timer RE converter UART0 Stop signal CM14 Low-speed on-chip oscillator fOCO-S Power-on reset circuit Voltage detection circuit b f1 c f2 d e f4 f8 g f32 XIN XOUT CM13 CM05 Oscillation stop detection OCD2 = 1 XIN clock a OCD2 = 0 Divider CPU clock D/A converter Comparator System clock CM02 CM10 = 1 (stop mode) RESET Power-on reset Software reset Interrupt request WAIT instruction SQ R b SQ R CM06 = 0 CM17 to CM16 = 11b CM06 = 1 c 1/2 1/2 d 1/2 e 1/2 1/2 g a CM06 = 0 CM17 to CM16 = 10b h CM02, CM05, CM06: Bits in CM0 register CM10, CM13, CM14, CM16, CM17: Bits in CM1 register OCD0, OCD1, OCD2: Bits in OCD register FRA00, FRA01: Bits in FRA0 register CM06 = 0 CM17 to CM16 = 01b CM06 = 0 CM17 to CM16 = 00b Detail of divider Oscillation Stop Detection Circuit Forcible discharge when OCD0 = 0 XIN clock Pulse generation circuit for clock edge detection and charge, discharge control circuit Charge, discharge circuit OCD1 Oscillation stop detection interrupt generation circuit detection Watchdog timer interrupt Voltage monitor 1 interrupt Voltage monitor 2 interrupt OCD2 bit switch signal CM14 bit switch signal Oscillation stop detection, Watchdog timer, Voltage monitor 1 interrupt, Voltage monitor 2 interrupt Figure 10.1 Clock Generation Circuit Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 66 of 332 R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit System Clock Control Register 0(1) b7 b6 b5 b4 b3 b2 b1 b0 0 01 00 Symbol Address 0006h CM0 Bit Symbol Bit Name — Reserved bits (b1-b0) WAIT peripheral function clock stop bit After Reset 01101000b Function Set to 0. 0 : Peripheral function clock does not stop in w ait mode 1 : Peripheral function clock stops in w ait mode Set to 1. Set to 0. 0 : XIN clock oscillates 1 : XIN clock stops (4) 0 : CM16, CM17 enabled 1 : Divide-by-8 mode Set to 0. RW RW CM02 RW — (b3) — (b4) CM05 CM06 — (b7) Reserved bit Reserved bit XIN clock (XIN-XOUT) stop bit(2, 3) System clock division select bit 0(5) Reserved bit RW RW RW RW RW NOTES: 1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM0 register. 2. P4_6 and P4_7 can be used as input ports w hen the CM05 bit is set to 1 (XIN clock stops) and the CM13 bit in the CM1 register is set to 0 (P4_6, P4_7). 3. The CM05 bit stops the XIN clock w hen the high-speed on-chip oscillator mode or low -speed on-chip oscillator mode is selected. Do not use this bit to detect w hether the XIN clock is stopped. To stop the XIN clock, set the bits in the follow ing order: (a) Set bits OCD1 to OCD0 in the OCD register to 00b. (b) Set the OCD2 bit to 1 (selects on-chip oscillator clock). 4. During external clock input, only the clock oscillation buffer is turned off and clock input is acknow ledged. 5. When entering stop mode, the CM06 bit is set to 1 (divide-by-8 mode). Figure 10.2 CM0 Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 67 of 332 R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit System Clock Control Register 1(1) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol CM1 Bit Symbol CM10 CM11 — (b2) CM13 CM14 CM15 Address 0007h Bit Name All clock stop control bit(2, 3, 4) After Reset 00100000b Function 0 : Clock operates 1 : Stops all clocks (stop mode) RW RW RW RW RW RW RW XIN-XOUT on-chip feedback resistor 0 : On-chip feedback resistor enabled select bit 1 : On-chip feedback resistor disabled Reserved bit Port XIN-XOUT sw itch bit(3, 5) Low -speed on-chip oscillation stop bit(4, 6, 7) XIN-XOUT drive capacity select bit(8) System clock division select bits 1(9) Set to 0. 0 : Input ports P4_6, P4_7 1 : XIN-XOUT pin 0 : Low -speed on-chip oscillator on 1 : Low -speed on-chip oscillator off 0 : Low 1 : High b7 b6 CM16 CM17 0 0 : No division mode 0 1 : Divide-by-2 mode 1 0 : Divide-by-4 mode 1 1 : Divide-by-16 mode RW RW NOTES: 1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM1 register. 2. If the CM10 bit is set to 1 (stop mode), the on-chip feedback resistor is disabled. 3. When the CM10 bit is set to 1 (stop mode) and the CM13 bit is set to 1 (XIN-XOUT pin), the XOUT (P4_7) pin goes “H”. When the CM13 bit is set to 0 (input ports, P4_6, P4_7), P4_7 (XOUT) enters input mode. 4. In count source protect mode (Refer to 13.2 Count Source Protect Mode Enabled), the value remains unchanged even if bits CM10 and CM14 are set. 5. Once the CM13 bit is set to 1 by a program, it cannot be set to 0. 6. When the OCD2 bit is set to 0 (XIN clock selected), the CM14 bit is set to 1 (low -speed on-chip oscillator stopped). When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low -speed on-chip oscillator on). It remains unchanged even if 1 is w ritten to it. 7. When using the voltage monitor 1 interrupt or voltage monitor 2 interrupt (w hen using the digital filter), set the CM14 bit to 0 (low -speed on-chip oscillator on). 8. When entering stop mode, the CM15 bit is set to 1 (drive capacity high). 9. When the CM06 bit is set to 0 (bits CM16, CM17 enabled), bits CM16 to CM17 are enabled. Figure 10.3 CM1 Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 68 of 332 R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit Oscillation Stop Detection Register(1) b7 b6 b5 b4 b3 b2 b1 b0 0000 Symbol OCD Bit Symbol OCD0 Address After Reset 000Ch 00000100b Bit Name Function Oscillation stop detection enable 0 : Oscillation stop detection function bit(7) disabled(2) 1 : Oscillation stop detection function enabled Oscillation stop detection interrupt enable bit System clock select bit(4) Clock monitor bit(5, 6) Reserved bits 0 : Disabled(2) 1 : Enabled 0 : Selects XIN clock(7) 1 : Selects on-chip oscillator clock(3) 0 : XIN clock oscillates 1 : XIN clock stops Set to 0. RW RW OCD1 OCD2 OCD3 — (b7-b4) RW RW RO RW NOTES: 1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting to the OCD register. 2. Set bits OCD1 to OCD0 to 00b before entering stop mode, high-speed on-chip oscillator mode, or low -speed on-chip oscillator mode (XIN clock stops). 3. The CM14 bit is set to 0 (low -speed on-chip oscillator on) if the OCD2 bit is set to 1 (on-chip oscillator clock selected). 4. The OCD2 bit is automatically set to 1 (on-chip oscillator clock selected) if a XIN clock oscillation stop is detected w hile bits OCD1 to OCD0 are set to 11b. If the OCD3 bit is set to 1 (XIN clock stopped), the OCD2 bit remains unchanged even w hen set to 0 (XIN clock selected). 5. The OCD3 bit is enabled w hen the OCD0 bit is set to 1 (oscillation stop detection function enabled). 6. The OCD3 bit remains 0 (XIN clock oscillates) if bits OCD1 to OCD0 are set to 00b. 7. Refer to Figure 10.14 Procedure for Sw itching Clock Source from Low -speed On-Chip Oscillator to XIN Clock f or the sw itching procedure w hen the XIN clock re-oscillates after detecting an oscillation stop. Figure 10.4 OCD Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 69 of 332 R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit High-Speed On-Chip Oscillator Control Register 0(1) b7 b6 b5 b4 b3 b2 b1 b0 000000 Symbol FRA0 Bit Symbol FRA00 FRA01 — (b7-b2) Address 0023h Bit Name High-speed on-chip oscillator enable bit High-speed on-chip oscillator select bit(2) Reserved bits After Reset 00h Function 0 : High-speed on-chip oscillator off 1 : High-speed on-chip oscillator on 0 : Selects low -speed on-chip oscillator (3) 1 : Selects high-speed on-chip oscillator Set to 0. RW RW RW RW NOTES: 1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the FRA0 register. 2. Change the FRA01 bit under the follow ing conditions. • FRA00 = 1 (high-speed on-chip oscillation) • The CM14 bit in the CM1 register = 0 (low -speed on-chip oscillator on) 3. When setting the FRA01 bit to 0 (low -speed on-chip oscillator selected), do not set the FRA00 bit to 0 (high-speed on-chip oscillator off) at the same time. Set the FRA00 bit to 0 after setting the FRA01 bit to 0. High-Speed On-Chip Oscillator Control Register 1(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol FRA1 Address 0024h After Reset When Shipping RW Function The frequency of the high-speed on-chip oscillator is adjusted w ith bits 0 to 7. High-speed on-chip oscillator frequency = 40 MHz (FRA1 register = value w hen shipping) Setting the FRA1 register to a low er value results in a higher frequency. Setting the FRA1 register to a higher value results in a low er frequency.(2) RW NOTES: 1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the FRA1 register. 2. When changing the values of the FRA1 register, adjust the FRA1 register so that the frequency of the high-speed on-chip oscillator clock w ill be 40 MHz or less. High-Speed On-Chip Oscillator Control Register 2(1) b7 b6 b5 b4 b3 b2 b1 b0 00000 Symbol FRA2 Bit Symbol FRA20 Address 0025h Bit Name High-speed on-chip oscillator frequency sw itching bits After Reset 00h Function Selects the dividing ratio for the highspeed on-chip oscillator clock. b2 b1 b0 RW RW FRA21 FRA22 0 0 0: Divide-by-2 mode 0 0 1: Divide-by-3 mode 0 1 0: Divide-by-4 mode 0 1 1: Divide-by-5 mode 1 0 0: Divide-by-6 mode 1 0 1: Divide-by-7 mode 1 1 0: Divide-by-8 mode 1 1 1: Divide-by-9 mode RW RW — (b7-b3) Reserved bits Set to 0. RW NOTE: 1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the FRA2 register. Figure 10.5 Registers FRA0 and FRA1, FRA2 Page 70 of 332 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit High-Speed On-Chip Oscillator Control Register 7 b7 b6 b5 b4 b3 b2 b1 b0 Symbol FRA7 Address 002Ch After Reset When Shipping RW RO Function 36.864 MHz frequency correction data is stored. The oscillation frequency of the high-speed on-chip oscillator can be adjusted to 36.864 MHz by transferring this value to the FRA1 register. Figure 10.6 FRA7 Register Voltage Detection Register 2(1) b7 b6 b5 b4 b3 b2 b1 b0 10000 Symbol VCA2 Bit Symbol VCA20 — (b4-b1) — (b5) VCA26 VCA27 Address 0032h Bit Name Internal pow er low consumption enable bit(5) Reserved bits Reserved bit Voltage detection 1 enable bit(2) Voltage detection 2 enable bit(3) After Reset(4) Pow er-on reset or hardw are reset : 00100000b Function 0 : Disables low consumption 1 : Enables low consumption Set to 0. Set to 1. 0 : Voltage detection 1 circuit disabled 1 : Voltage detection 1 circuit enabled 0 : Voltage detection 2 circuit disabled 1 : Voltage detection 2 circuit enabled RW RW RW RW RW RW NOTES: 1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VCA2 register. 2. To use the voltage monitor 1 interrupt/reset or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1. After the VCA26 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting operation. 3. To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1. After the VCA27 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting operation. 4. Softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this register. 5. Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in Figure 10.8 Procedure for Enabling Reduced Internal Pow er Consum ption Using VCA20 bit. Figure 10.7 VCA2 Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 71 of 332 R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit Exit wait mode by interrupt Handling procedure of internal power low consumption enabled by VCA20 bit (Note 1) In interrupt routine Step (1) Enter low-speed on-chip oscillator mode Step (5) VCA20 ← 0 (internal power low consumption disabled)(2) Step (2) Stop XIN clock and high-speed on-chip oscillator clock Step (6) Start XIN clock or high-speed on-chip oscillator clock Step (3) VCA20 ← 1 (internal power low consumption enabled)(2, 3) Step (7) (Wait until XIN clock oscillation stabilizes) If it is necessary to start the high-speed clock or the high-speed on-chip oscillator in the interrupt routine, execute steps (5) to (7) in the interrupt routine. Step (4) Enter wait mode(4) Step (8) Enter high-speed clock mode or high-speed on-chip oscillator mode Step (5) VCA20 ← 0 (internal power low consumption disabled)(2) Interrupt handling Step (6) Start XIN clock or high-speed on-chip oscillator clock Step (1) Enter low-speed on-chip oscillator mode If the high-speed clock or high-speed on-chip oscillator is started in the interrupt routine, execute steps (1) to (3) at the last of the interrupt routine. Step (2) Step (7) (Wait until XIN clock oscillation stabilizes) Stop XIN clock and high-speed on-chip oscillator clock Step (8) Enter high-speed clock mode or high-speed on-chip oscillator mode Step (3) VCA20 ← 1 (internal power low consumption enabled)(2, 3) Interrupt handling completed NOTES: 1. Execute this routine to handle all interrupts generated in wait mode. However, this does not apply if it is not necessary to start the high-speed clock or high-speed on-chip oscillator during the interrupt routine. 2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite. 3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode). 4. When entering wait mode, follow 10.6.2 Wait Mode. VCA20: Bit in VCA2 register Figure 10.8 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 72 of 332 R8C/2E Group, R8C/2F Group The clocks generated by the clock generation circuits are described below. 10. Clock Generation Circuit 10.1 XIN Clock This clock is supplied by the XIN clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks. The XIN clock oscillation circuit is configured by connecting a resonator between the XIN and XOUT pins. The XIN clock oscillation circuit includes an on-chip feedback resistor, which is disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed by the chip. The XIN clock oscillation circuit may also be configured by feeding an externally generated clock to the XIN pin. Figure 10.9 shows Examples of XIN Clock Connection Circuit. In reset and after reset, the XIN clock stops. The XIN clock starts oscillating when the CM05 bit in the CM0 register is set to 0 (XIN clock oscillates) after setting the CM13 bit in the CM1 register to 1 (XIN- XOUT pin). To use the XIN clock for the CPU clock source, set the OCD2 bit in the OCD register to 0 (select XIN clock) after the XIN clock is oscillating stably. The power consumption can be reduced by setting the CM05 bit in the CM0 register to 1 (XIN clock stops) if the OCD2 bit is set to 1 (select on-chip oscillator clock). When an external clock is input to the XIN pin are input, the XIN clock does not stop if the CM05 bit is set to 1. If necessary, use an external circuit to stop the clock. This MCU has an on-chip feedback resistor and on-chip resistor disable/enable switching is possible by the CM11 bit in the CM1 register. In stop mode, all clocks including the XIN clock stop. Refer to 10.4 Power Control for details. MCU (on-chip feedback resistor) XIN Rf(1) XOUT MCU (on-chip feedback resistor) XIN XOUT Open Rd(1) Externally derived clock CIN COUT VCC VSS Ceramic resonator external circuit External clock input circuit NOTE: 1. Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the manufacturer of the oscillator. Use high drive when oscillation starts and, if it is necessary to switch the oscillation drive capacity, do so after oscillation stabilizes. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added to the chip externally, insert a feedback resistor between XIN and XOUT following the instructions. To use this MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1 register to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and connect the feedback resistor to the chip externally. Figure 10.9 Examples of XIN Clock Connection Circuit Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 73 of 332 R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit 10.2 On-Chip Oscillator Clocks These clocks are supplied by the on-chip oscillators (high-speed on-chip oscillator and a low-speed on-chip oscillator). The on-chip oscillator clock is selected by the FRA01 bit in the FRA0 register. 10.2.1 Low-Speed On-Chip Oscillator Clock The clock generated by the low-speed on-chip oscillator is used as the clock source for the CPU clock, peripheral function clock, fOCO, and fOCO-S. After reset, the on-chip oscillator clock generated by the low-speed on-chip oscillator divided by 8 is selected as the CPU clock. If the XIN clock stops oscillating when bits OCD1 to OCD0 in the OCD register are set to 11b, the low-speed on-chip oscillator automatically starts operating, supplying the necessary clock for the MCU. The frequency of the low-speed on-chip oscillator varies depending on the supply voltage and the operating ambient temperature. Application products must be designed with sufficient margin to allow for frequency changes. 10.2.2 High-Speed On-Chip Oscillator Clock The clock generated by the high-speed on-chip oscillator is used as the clock source for the CPU clock, peripheral function clock, fOCO, fOCO-F, and fOCO40M. After reset, the on-chip oscillator clock generated by the high-speed on-chip oscillator stops. Oscillation is started by setting the FRA00 bit in the FRA0 register to 1 (high-speed on-chip oscillator on). The frequency can be adjusted by registers FRA1 and FRA2. The frequency correction data of 36.864 MHz is stored in the FRA7 register. To set the frequency of the highspeed on-chip oscillator to 36.864 MHz, transfer the correction value in the FRA7 register to the FRA1 register before use. Since there are differences in the amount of frequency adjustment among the bits in the FRA1 register, make adjustments by changing the settings of individual bits. Adjust the FRA1 register so that the frequency of the high-speed on-chip oscillator clock will be 40 MHz or less. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 74 of 332 R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit 10.3 CPU Clock and Peripheral Function Clock There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer to Figure 10.1 Clock Generation Circuit. 10.3.1 System Clock The system clock is the clock source for the CPU and peripheral function clocks. Either the XIN clock or the on-chip oscillator clock can be selected. 10.3.2 CPU Clock The CPU clock is an operating clock for the CPU and watchdog timer. The system clock can be divided by 1 (no division), 2, 4, 8, or 16 to produce the CPU clock. Use the CM06 bit in the CM0 register and bits CM16 to CM17 in the CM1 register to select the value of the division. After reset, the low-speed on-chip oscillator clock divided by 8 provides the CPU clock. When entering stop mode from high-speed clock mode, the CM06 bit is set to 1 (divide-by-8 mode). 10.3.3 Peripheral Function Clock (f1, f2, f4, f8, and f32) The peripheral function clock is the operating clock for the peripheral functions. The clock fi (i = 1, 2, 4, 8, and 32) is generated by the system clock divided by i. The clock fi is used for timers RA, RB, RC, and RE, the serial interface and the A/D converter. When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to 1 (peripheral function clock stops in wait mode), the clock fi stop. 10.3.4 fOCO fOCO is an operating clock for the peripheral functions. fOCO runs at the same frequency as the on-chip oscillator clock and can be used as the source for timer RA. When the WAIT instruction is executed, the clocks fOCO does not stop. 10.3.5 fOCO40M fOCO40M is used as the count source for timer RC. fOCO40M is generated by the high-speed on-chip oscillator and supplied by setting the FRA00 bit to 1. When the WAIT instruction is executed, the clock fOCO40M does not stop. fOCO40M can be used with supply voltage VCC = 3.0 to 5.5 V. 10.3.6 fOCO-F fOCO-F is used as the count source for the A/D converter. fOCO-F is generated by the high-speed on-chip oscillator and supplied by setting the FRA00 bit to 1. When the WAIT instruction is executed, the clock fOCO-F does not stop. 10.3.7 fOCO-S fOCO-S is an operating clock for the watchdog timer and voltage detection circuit. fOCO-S is supplied by setting the CM14 bit to 0 (low-speed on-chip oscillator on) and uses the clock generated by the low-speed onchip oscillator. When the WAIT instruction is executed or in count source protect mode of the watchdog timer, fOCO-S does not stop. 10.3.8 fOCO128 fOCO128 is generated by fOCO divided by 128. The clock fOCO128 is used for capture signal of the timer RC’s TRCGRA register. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 75 of 332 R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit 10.4 Power Control There are three power control modes. All modes other than wait mode and stop mode are referred to as standard operating mode. 10.4.1 Standard Operating Mode Standard operating mode is further separated into four modes. In standard operating mode, the CPU clock and the peripheral function clock are supplied to operate the CPU and the peripheral function clocks. Power consumption control is enabled by controlling the CPU clock frequency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU clock frequency, the more power consumption decreases. When unnecessary oscillator circuits stop, power consumption is further reduced. Before the clock sources for the CPU clock can be switched over, the new clock source needs to be oscillating and stable. If the new clock source is the XIN clock, allow sufficient wait time in a program until oscillation is stabilized before exiting. Table 10.2 Settings and Modes of Clock Associated Bits OCD Register OCD2 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 CM1 Register CM17, CM16 CM14 00b − 01b − 10b − − − 11b − 00b − 01b − 10b − − − 11b − 00b 0 01b 0 10b 0 − 0 11b 0 CM13 1 1 1 1 1 − − − − − − − − − − CM0 Register CM06 CM05 0 0 0 0 0 0 1 0 0 0 0 − 0 − 0 − 1 − 0 − 0 − 0 − 0 − 1 − 0 − FRA0 Register FRA01 FRA00 − − − − − − − − − − 1 1 1 1 1 1 1 1 1 1 0 − 0 − 0 − 0 − 0 − Modes High-speed clock mode No division Divide-by-2 Divide-by-4 Divide-by-8 Divide-by-16 No division Divide-by-2 Divide-by-4 Divide-by-8 Divide-by-16 No division Divide-by-2 Divide-by-4 Divide-by-8 Divide-by-16 High-speed on-chip oscillator mode Low-speed on-chip oscillator mode −: can be 0 or 1, no change in outcome Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 76 of 332 R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit 10.4.1.1 High-Speed Clock Mode The XIN clock divided by 1 (no division), 2, 4, 8, or 16 provides the CPU clock. Set the CM06 bit to 1 (divideby-8 mode) when transiting to high-speed on-chip oscillator mode, low-speed on-chip oscillator mode. If the CM14 bit is set to 0 (low-speed on-chip oscillator on) or the FRA00 bit in the FRA0 register is set to 1 (highspeed on-chip oscillator on), fOCO can be used as timer RA. When the FRA00 bit is set to 1, fOCO40M can be used as timer RC. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used as the watchdog timer and voltage detection circuit. 10.4.1.2 High-Speed On-Chip Oscillator Mode The high-speed on-chip oscillator is used as the on-chip oscillator clock when the FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator on) and the FRA01 bit in the FRA0 register is set to 1. The onchip oscillator divided by 1 (no division), 2, 4, 8, or 16 provides the CPU clock. Set the CM06 bit to 1 (divideby-8 mode) when transiting to high-speed clock mode. If the FRA00 bit is set to 1, fOCO40M can be used as timer RC. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used as the watchdog timer and voltage detection circuit. 10.4.1.3 Low-Speed On-Chip Oscillator Mode If the CM14 bit in the CM1 register is set to 0 (low-speed on-chip oscillator on) or the FRA01bit in the FRA0 register is set to 0, the low-speed on-chip oscillator provides the on-chip oscillator clock. The on-chip oscillator clock divided by 1 (no division), 2, 4, 8 or 16 provides the CPU clock. The on-chip oscillator clock is also the clock source for the peripheral function clocks. Set the CM06 bit to 1 (divide-by-8 mode) when transiting to high-speed clock mode. When the FRA00 bit is set to 1, fOCO40M can be used as timer RC. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used as the watchdog timer and voltage detection circuit. In this mode, stopping the XIN clock and high-speed on-chip oscillator, and setting the FMR47 bit in the FMR4 register to 1 (flash memory low consumption current read mode enabled) enables low consumption operation. To enter wait mode from low-speed on-chip oscillator mode, setting the VCA20 bit in the VCA2 register to 1 (internal power low consumption enabled) enables lower consumption current in wait mode. When enabling reduced internal power consumption using the VCA20 bit, follow Figure 10.11 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 77 of 332 R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit 10.4.2 Wait Mode Since the CPU clock stops in wait mode, the CPU, which operates using the CPU clock, and the watchdog timer, when count source protection mode is disabled, stop. The XIN clock and on-chip oscillator clock do not stop and the peripheral functions using these clocks continue operating. 10.4.2.1 Peripheral Function Clock Stop Function If the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the f1, f2, f4, f8, and f32 clocks stop in wait mode. This reduces power consumption. 10.4.2.2 Entering Wait Mode The MCU enters wait mode when the WAIT instruction is executed. When the OCD2 bit in the OCD register is set to 1 (on-chip oscillator selected as system clock), set the OCD1 bit in the OCD register to 0 (oscillation stop detection interrupt disabled) before executing the WAIT instruction. If the MCU enters wait mode while the OCD1 bit is set to 1 (oscillation stop detection interrupt enabled), current consumption is not reduced because the CPU clock does not stop. 10.4.2.3 Pin Status in Wait Mode The I/O port is the status before wait mode was entered is maintained. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 78 of 332 R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit 10.4.2.4 Exiting Wait Mode The MCU exits wait mode by a reset or a peripheral function interrupt. The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is set to 0 (peripheral function clock does not stop in wait mode), all peripheral function interrupts can be used to exit wait mode. When the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the peripheral functions using the peripheral function clock stop operating and the peripheral functions operated by external signals or on-chip oscillator clock can be used to exit wait mode. Table 10.3 lists Interrupts to Exit Wait Mode and Usage Conditions. Table 10.3 Interrupts to Exit Wait Mode and Usage Conditions CM02 = 0 Usable when operating with internal or external clock Usable Usable in one-shot mode Usable Usable Usable in all modes CM02 = 1 Usable when operating with external clock Usable (Do not use) Can be used if there is no filter Can be used if there is no filter Can be used if there is no filter in event counter mode. Usable by selecting fOCO as count source. (Do not use) (Do not use) (Do not use) Usable (INT0, INT1, INT3 can be used if there is no filter.) Usable Usable (Do not use) Interrupt Serial interface interrupt Key input interrupt A/D conversion interrupt Comparator 0 interrupt Comparator 1 interrupt Timer RA interrupt Timer RB interrupt Timer RC interrupt Timer RE interrupt INT interrupt Voltage monitor 1 interrupt Voltage monitor 2 interrupt Oscillation stop detection interrupt Usable in all modes Usable in all modes Usable in all modes Usable Usable Usable Usable Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 79 of 332 R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit Figure 10.10 shows Time from Wait Mode to Interrupt Routine Execution. When using a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT instruction. (1) Set the interrupt priority level in bits ILVL2 to ILVL0 in the interrupt control registers of the peripheral function interrupts to be used for exiting wait mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used for exiting wait mode to 000b (interrupt disabled). (2) Set the I flag to 1. (3) Operate the peripheral function to be used for exiting wait mode. When exiting by a peripheral function interrupt, the time (number of cycles) between interrupt request generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 register, as described in Figure 10.10. The CPU clock, when exiting wait mode by a peripheral function interrupt, is the same clock as the CPU clock when the WAIT instruction is executed. FMR0 Register FMSTP Bit 0 (flash memory operates) 1 (flash memory stops) Time until Flash Memory is Activated (T1) Period of XIN clock × 12 cycles + 30 µs (max.) Period of XIN clock × 12 cycles Time until CPU Clock is Supplied (T2) Period of CPU clock × 6 cycles Same as above Time for Interrupt Sequence (T3) Remarks Period of CPU clock Following total time is × 20 cycles the time from wait mode until an interrupt Same as above routine is executed. T1 Wait mode Flash memory activation sequence Interrupt request generated T2 CPU clock restart sequence T3 Interrupt sequence Figure 10.10 Time from Wait Mode to Interrupt Routine Execution Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 80 of 332 R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit 10.4.2.5 Reducing Internal Power Consumption Internal power consumption can be reduced by using low-speed on-chip oscillator mode. Figure 10.11 shows the Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit. When enabling reduced internal power consumption using the VCA20 bit, follow Figure 10.11 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit. Exit wait mode by interrupt Handling procedure of internal power low consumption enabled by VCA20 bit (Note 1) In interrupt routine Step (1) Enter low-speed on-chip oscillator mode Step (5) VCA20 ← 0 (internal power low consumption disabled)(2) Step (2) Stop XIN clock and high-speed on-chip oscillator clock Step (6) Start XIN clock or high-speed on-chip oscillator clock Step (3) VCA20 ← 1 (internal power low consumption enabled)(2, 3) Step (7) (Wait until XIN clock oscillation stabilizes) If it is necessary to start the high-speed clock or the high-speed on-chip oscillator in the interrupt routine, execute steps (5) to (7) in the interrupt routine. Step (4) Enter wait mode(4) Step (8) Enter high-speed clock mode or high-speed on-chip oscillator mode Step (5) VCA20 ← 0 (internal power low consumption disabled)(2) Interrupt handling Step (6) Start XIN clock or high-speed on-chip oscillator clock Step (1) Enter low-speed on-chip oscillator mode If the high-speed clock or high-speed on-chip oscillator is started in the interrupt routine, execute steps (1) to (3) at the last of the interrupt routine. Step (2) Step (7) (Wait until XIN clock oscillation stabilizes) Stop XIN clock and high-speed on-chip oscillator clock Step (8) Enter high-speed clock mode or high-speed on-chip oscillator mode Step (3) VCA20 ← 1 (internal power low consumption enabled)(2, 3) Interrupt handling completed NOTES: 1. Execute this routine to handle all interrupts generated in wait mode. However, this does not apply if it is not necessary to start the high-speed clock or high-speed on-chip oscillator during the interrupt routine. 2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite. 3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode). 4. When entering wait mode, follow 10.6.2 Wait Mode. VCA20: Bit in VCA2 register Figure 10.11 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 81 of 332 R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit 10.4.3 Stop Mode Since the oscillator circuits stop in stop mode, the CPU clock and peripheral function clock stop and the CPU and peripheral functions that use these clocks stop operating. The least power required to operate the MCU is in stop mode. If the voltage applied to the VCC pin is VRAM or more, the contents of internal RAM is maintained. The peripheral functions clocked by external signals continue operating. Table 10.4 lists Interrupts to Exit Stop Mode and Usage Conditions. Table 10.4 Interrupts to Exit Stop Mode and Usage Conditions Usage Conditions − Can be used if there is no filter When there is no filter and external pulse is counted in event counter mode When external clock is selected Usable in digital filter disabled mode (VW1C1 bit in VW1C register is set to 1) Usable in digital filter disabled mode (VW2C1 bit in VW2C register is set to 1) Can be used if there is no filter Interrupt Key input interrupt INT0, INT1, INT3 interrupt Timer RA interrupt Serial interface interrupt Voltage monitor 1 interrupt Voltage monitor 2 interrupt Comparator 0 interrupt, Comparator 1 interrupt 10.4.3.1 Entering Stop Mode The MCU enters stop mode when the CM10 bit in the CM1 register is set to 1 (all clocks stop). At the same time, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode) and the CM15 bit in the CM1 register is set to 1 (XIN clock oscillator circuit drive capacity high). When using stop mode, set bits OCD1 to OCD0 to 00b before entering stop mode. 10.4.3.2 Pin Status in Stop Mode The status before wait mode was entered is maintained. However, when the CM13 bit in the CM1 register is set to 1 (XIN-XOUT pins), the XOUT(P4_7) pin is held “H”. When the CM13 bit is set to 0 (input ports P4_6 and P4_7), the P4_7(XOUT pin) is held in input status. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 82 of 332 R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit 10.4.3.3 Exiting Stop Mode The MCU exits stop mode by a reset or peripheral function interrupt. Figure 10.12 shows the Time from Stop Mode to Interrupt Routine Execution. When using a peripheral function interrupt to exit stop mode, set up the following before setting the CM10 bit to 1. (1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peripheral function interrupts to be used for exiting stop mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used for exiting stop mode to 000b (interrupt disabled). (2) Set the I flag to 1. (3) Operates the peripheral function to be used for exiting stop mode. When exiting by a peripheral function interrupt, the interrupt sequence is executed when an interrupt request is generated and the CPU clock supply is started. If the clock used immediately before stop mode is a system clock and stop mode is exited by a peripheral function interrupt, the CPU clock becomes the previous system clock divided by 8. FMR0 Register FMSTP Bit 0 (flash memory operates) 1 (flash memory stops) Time until Flash Memory is Activated (T2) Period of XIN clock × 12 cycles + 30 µs (max.) Period of XIN clock × 12 cycles Time until CPU Clock is Supplied (T3) Period of CPU clock × 6 cycles Same as above Time for Interrupt Sequence (T4) Remarks Period of CPU clock Following total time of T0 to T4 × 20 cycles is the time from stop mode until an interrupt Same as above handling is executed. T0 Stop mode Internal power stability time T1 Oscillation time of CPU clock source used immediately before stop mode T2 Flash memory activation sequence T3 CPU clock restart sequence T4 Interrupt sequence 150 µs Interrupt (max.) request generated Figure 10.12 Time from Stop Mode to Interrupt Routine Execution Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 83 of 332 R8C/2E Group, R8C/2F Group Figure 10.13 shows the State Transitions in Power Control Mode. 10. Clock Generation Circuit State Transitions in Power Control Mode Reset Standard operating mode Low-speed on-chip oscillator mode CM14 = 0 OCD2 = 1 FRA01 = 0 CM14 = 0 OCD2 = 1 FRA01 = 0 CM05 = 0 CM13 = 1 OCD2 = 0 High-speed clock mode CM05 = 0 CM13 = 1 OCD2 = 0 CM14 = 0 FRA01 = 0 FRA00 = 1 FRA01 = 1 OCD2 = 1 FRA00 = 1 FRA01 = 1 CM05 = 0 CM13 = 1 OCD2 = 0 High-speed on-chip oscillator mode OCD2 = 1 FRA00 = 1 FRA01 = 1 Interrupt WAIT instruction Interrupt CM10 = 1 Wait mode CPU operation stops CM05: Bit in CM0 register CM13, CM14: Bits in CM1 register OCD2: Bit in OCD register FRA00, FRA01: Bits in FRA0 register Stop mode All oscillators stop Figure 10.13 State Transitions in Power Control Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 84 of 332 R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit 10.5 Oscillation Stop Detection Function The oscillation stop detection function detects the stop of the XIN clock oscillating circuit. The oscillation stop detection function can be enabled and disabled by the OCD0 bit in the OCD register. Table 10.5 lists the Specifications of Oscillation Stop Detection Function. When the XIN clock is the CPU clock source and bits OCD1 to OCD0 are set to 11b, the system is placed in the following state if the XIN clock stops. • OCD2 bit in OCD register = 1 (on-chip oscillator clock selected) • OCD3 bit in OCD register = 1 (XIN clock stops) • CM14 bit in CM1 register = 0 (low-speed on-chip oscillator oscillates) • Oscillation stop detection interrupt request is generated. Table 10.5 Specifications of Oscillation Stop Detection Function Specification f(XIN) ≥ 2 MHz Set bits OCD1 to OCD0 to 11b Oscillation stop detection interrupt is generated Item Oscillation stop detection clock and frequency bandwidth Enabled condition for oscillation stop detection function Operation at oscillation stop detection 10.5.1 How to Use Oscillation Stop Detection Function • The oscillation stop detection interrupt shares a vector with the voltage monitor 1 interrupt, the voltage monitor 2 interrupt, and the watchdog timer interrupt. When using the oscillation stop detection interrupt and watchdog timer interrupt, the interrupt source needs to be determined. Table 10.6 lists Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, and Voltage Monitor 2 Interrupts. Figure 10.15 shows the Example of Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt. When the XIN clock restarts after oscillation stop, switch the XIN clock to the clock source of the CPU clock and peripheral functions by a program. Figure 10.14 shows the Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to XIN Clock. To enter wait mode while using the oscillation stop detection function, set the CM02 bit to 0 (peripheral function clock does not stop in wait mode). Since the oscillation stop detection function is a function for cases where the XIN clock is stopped by an external cause, set bits OCD1 to OCD0 to 00b when the XIN clock stops or is started by a program, (stop mode is selected or the CM05 bit is changed). This function cannot be used when the XIN clock frequency is 2 MHz or below. In this case, set bits OCD1 to OCD0 to 00b. To use the low-speed on-chip oscillator clock for the CPU clock and clock sources of peripheral functions after detecting the oscillation stop, set the FRA01 bit in the FRA0 register to 0 (low-speed on-chip oscillator selected) and bits OCD1 to OCD0 to 11b. To use the high-speed on-chip oscillator clock for the CPU clock and clock sources of peripheral functions after detecting the oscillation stop, set the FRA00 bit to 1 (high-speed on-chip oscillator on) and the FRA01 bit to 1 (high-speed on-chip oscillator selected) and then set bits OCD1 to OCD0 to 11b. • • • • • Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 85 of 332 R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit Table 10.6 Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, and Voltage Monitor 2 Interrupts Generated Interrupt Source Bit Showing Interrupt Cause Oscillation stop detection (a) OCD3 bit in OCD register = 1 ((a) or (b)) (b) OCD1 to OCD0 bits in OCD register = 11b and OCD2 bit = 1 Watchdog timer VW2C3 bit in VW2C register = 1 Voltage monitor 1 VW1C2 bit in VW1C register = 1 Voltage monitor 2 VW2C2 bit in VW2C register = 1 Switch to XIN clock NO Multiple confirmations that OCD3 bit is set to 0 (XIN clock oscillates) ? YES Set OCD1 to OCD0 bits to 00b Set OCD2 bit to 0 (select XIN clock) End OCD3 to OCD0: Bits in OCD register Figure 10.14 Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to XIN Clock Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 86 of 332 R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit Interrupt sources judgment OCD3 = 1 ? (XIN clock stopped) NO YES OCD1 = 1 (oscillation stop detection interrupt enabled) and OCD2 = 1 (on-chip oscillator clock selected as system clock) ? NO YES VW2C3 = 1 ? (Watchdog timer underflow) NO YES VW2C2 = 1 ? (passing Vdet2) NO YES Set OCD1 bit to 0 (oscillation stop detection interrupt disabled). (1) To oscillation stop detection interrupt routine To watchdog timer interrupt routine To voltage monitor 2 interrupt routine To voltage monitor 1 interrupt routine NOTE: 1. This disables multiple oscillation stop detection interrupts. OCD1 to OCD3: Bits in OCD register VW2C2, VW2C3: Bits in VW2C register Figure 10.15 Example of Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 87 of 332 R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit 10.6 10.6.1 Notes on Clock Generation Circuit Stop Mode When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit to 1 (stop mode) and the program stops. Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets the CM10 bit to 1. • Program example to enter stop mode BCLR BSET FSET BSET JMP.B LABEL_001 : NOP NOP NOP NOP 1,FMR0 0,PRCR I 0,CM1 LABEL_001 ; CPU rewrite mode disabled ; Protect disabled ; Enable interrupt ; Stop mode 10.6.2 Wait Mode When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the program stops. Insert at least 4 NOP instructions after the WAIT instruction. • Program example to execute the WAIT instruction BCLR 1,FMR0 FSET I WAIT NOP NOP NOP NOP ; CPU rewrite mode disabled ; Enable interrupt ; Wait mode 10.6.3 Oscillation Stop Detection Function Since the oscillation stop detection function cannot be used if the XIN clock frequency is 2 MHz or below, set bits OCD1 to OCD0 to 00b. 10.6.4 Oscillation Circuit Constants Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system. To use this MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1 register to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and connect the feedback resistor to the chip externally. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 88 of 332 R8C/2E Group, R8C/2F Group 11. Protection 11. Protection The protection function protects important registers from being easily overwritten when a program runs out of control. Figure 11.1 shows the PRCR Register. The registers protected by the PRCR register are listed below. • Registers protected by PRC0 bit: Registers CM0, CM1, OCD, FRA0, FRA1, and FRA2 • Registers protected by PRC1 bit: Registers PM0 and PM1 • Registers protected by PRC2 bit: PD0 register • Registers protected by PRC3 bit: Registers VCA2, VW1C, and VW2C Protect Register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol PRCR Bit Symbol Address 000Ah Bit Name Protect bit 0 PRC0 After Reset 00h Function Writing to registers CM0, CM1, OCD, FRA0, FRA1, and FRA2 is enabled. 0 : Disables w riting 1 : Enables w riting Writing to registers PM0 and PM1 is enabled. 0 : Disables w riting 1 : Enables w riting Writing to the PD0 register is enabled. 0 : Disables w riting 1 : Enables w riting(1) Writing to registers VCA2, VW1C, and VW2C is enabled. 0 : Disables w riting 1 : Enables w riting Set to 0. When read, the content is 0. RW RW Protect bit 1 PRC1 Protect bit 2 PRC2 Protect bit 3 PRC3 RW RW RW — (b5-b4) — (b7-b6) Reserved bits Reserved bits RW RO NOTE: 1. This bit is set to 0 after w riting 1 to the PRC2 bit and executing a w rite to any address. Since the other bits are not set to 0, set them to 0 by a program. Figure 11.1 PRCR Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 89 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts 12. Interrupts 12.1 12.1.1 Interrupt Overview Types of Interrupts Figure 12.1 shows the types of Interrupts. Software (non-maskable interrupts) Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Watchdog timer Oscillation stop detection Voltage monitor 1 Voltage monitor 2 Single step(2) Address break(2) Address match Interrupts Special (non-maskable interrupts) Hardware Peripheral functions(1) (maskable interrupts) NOTES: 1. Peripheral function interrupts in the MCU are used to generate peripheral interrupts. 2. Do not use this interrupt. This is for use with development tools only. Figure 12.1 Interrupts • Maskable Interrupts: • Non-Maskable Interrupts: The interrupt enable flag (I flag) enables or disables these interrupts. The interrupt priority order can be changed based on the interrupt priority level. The interrupt enable flag (I flag) does not enable or disable these interrupts. The interrupt priority order cannot be changed based on interrupt priority level. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 90 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts 12.1.2 Software Interrupts A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable. 12.1.2.1 Undefined Instruction Interrupt The undefined instruction interrupt is generated when the UND instruction is executed. 12.1.2.2 Overflow Interrupt The overflow interrupt is generated when the O flag is set to 1 (arithmetic operation overflow) and the INTO instruction is executed. Instructions that set the O flag are: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, and SUB. 12.1.2.3 BRK Interrupt A BRK interrupt is generated when the BRK instruction is executed. 12.1.2.4 INT Instruction Interrupt An INT instruction interrupt is generated when the INT instruction is executed. The INT instruction can select software interrupt numbers 0 to 63. Software interrupt numbers 3 to 31 are assigned to the peripheral function interrupt. Therefore, the MCU executes the same interrupt routine when the INT instruction is executed as when a peripheral function interrupt is generated. For software interrupt numbers 0 to 31, the U flag is saved to the stack during instruction execution and the U flag is set to 0 (ISP selected) before the interrupt sequence is executed. The U flag is restored from the stack when returning from the interrupt routine. For software interrupt numbers 32 to 63, the U flag does not change state during instruction execution, and the selected SP is used. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 91 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts 12.1.3 Special Interrupts Special interrupts are non-maskable. 12.1.3.1 Watchdog Timer Interrupt The watchdog timer interrupt is generated by the watchdog timer. For details, refer to 13. Watchdog Timer. 12.1.3.2 Oscillation Stop Detection Interrupt The oscillation stop detection interrupt is generated by the oscillation stop detection function. For details of the oscillation stop detection function, refer to 10. Clock Generation Circuit. 12.1.3.3 Voltage Monitor 1 Interrupt The voltage monitor 1 interrupt is generated by the voltage detection circuit. For details of the voltage detection circuit, refer to 6. Voltage Detection Circuit. 12.1.3.4 Voltage Monitor 2 Interrupt The voltage monitor 2 interrupt is generated by the voltage detection circuit. For details of the voltage detection circuit, refer to 6. Voltage Detection Circuit. 12.1.3.5 Single-Step Interrupt, and Address Break Interrupt Do not use these interrupts. They are for use by development tools only. 12.1.3.6 Address Match Interrupt The address match interrupt is generated immediately before executing an instruction that is stored at an address indicated by registers RMAD0 to RMAD1 when the AIER0 or AIER1 bit in the AIER register is set to 1 (address match interrupt enable). For details of the address match interrupt, refer to 12.4 Address Match Interrupt. 12.1.4 Peripheral Function Interrupt The peripheral function interrupt is generated by the internal peripheral function of the MCU and is a maskable interrupt. Refer to Table 12.2 Relocatable Vector Tables for sources of the peripheral function interrupt. For details of peripheral functions, refer to the descriptions of individual peripheral functions. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 92 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts 12.1.5 Interrupts and Interrupt Vectors There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector. Figure 12.2 shows an Interrupt Vector. MSB LSB Vector address (L) Low address Mid address 0000 High address 0000 Vector address (H) Figure 12.2 Interrupt Vector 0000 12.1.5.1 Fixed Vector Tables The fixed vector tables are allocated addresses 0FFDCh to 0FFFFh. Table 12.1 lists the Fixed Vector Tables. The vector addresses (H) of fixed vectors are used by the ID code check function. For details, refer to 20.3 Functions to Prevent Rewriting of Flash Memory. • Table 12.1 Fixed Vector Tables Vector Addresses Remarks Reference Address (L) to (H) 0FFDCh to 0FFDFh Interrupt on UND R8C/Tiny Series Software instruction Manual 0FFE0h to 0FFE3h Interrupt on INTO instruction 0FFE4h to 0FFE7h If the content of address 0FFE7h is FFh, program execution starts from the address shown by the vector in the relocatable vector table. 0FFE8h to 0FFEBh 12.4 Address Match Interrupt 0FFECh to 0FFEFh 0FFF0h to 0FFF3h 13. Watchdog Timer 10. Clock Generation Circuit 6. Voltage Detection Circuit Interrupt Source Undefined instruction Overflow BRK instruction Address match Single step(1) Watchdog timer, Oscillation stop detection, Voltage monitor 1, Voltage monitor 2 Address break(1) (Reserved) Reset 0FFF4h to 0FFF7h 0FFF8h to 0FFFBh 0FFFCh to 0FFFFh 5. Resets NOTE: 1. Do not use these interrupts. They are for use by development tools only. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 93 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts 12.1.5.2 Relocatable Vector Tables The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register. Table 12.2 lists the Relocatable Vector Tables. Table 12.2 Relocatable Vector Tables Vector Addresses(1) Address (L) to Address (H) +0 to +3 (0000h to 0003h) Software Interrupt Control Interrupt Reference Register Number 0 − R8C/Tiny Series Software Manual 1 to 2 − − 3 to 6 − − 7 TRCIC 14.3 Timer RC − − 8 to 9 10 TREIC 14.4 Timer RE 11 to 12 − − 13 KUPIC 12.3 Key Input Interrupt 14 ADIC 17. A/D Converter − 15 to 16 − 17 18 19 to 21 22 23 24 25 26 27 28 29 S0TIC S0RIC − TRAIC − TRBIC INT1IC INT3IC CM0IC CM1IC INT0IC − − − Interrupt Source BRK instruction(2) (Reserved) (Reserved) Timer RC (Reserved) Timer RE (Reserved) Key input A/D (Reserved) UART0 transmit UART0 receive (Reserved) Timer RA (Reserved) Timer RB INT1 INT3 Comparator 0 Comparator 1 INT0 (Reserved) (Reserved) Software interrupt(2) +28 to +31 (001Ch to 001Fh) +40 to +43 (0028h to 002Bh) +52 to +55 (0034h to 0037h) +56 to +59 (0038h to 003Bh) +68 to +71 (0044h to 0047h) +72 to +75 (0048h to 004Bh) +88 to +91 (0058h to 005Bh) +96 to +99 (0060h to 0063h) +100 to +103 (0064h to 0067h) +104 to +107 (0068h to 006Bh) +108 to +111 (006Ch to 006Fh) +112 to +115 (0070h to 0073h) +116 to +119 (0074h to 0077h) 15. Serial Interface − 14.1 Timer RA − 14.2 Timer RB 12.2 INT Interrupt 19. Comparator 12.2 INT Interrupt − − R8C/Tiny Series Software Manual 30 31 +128 to +131 (0080h to 0083h) to 32 to 63 +252 to +255 (00FCh to 00FFh) NOTES: 1. These addresses are relative to those in the INTB register. 2. The I flag does not disable these interrupts. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 94 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts 12.1.6 Interrupt Control The following describes enabling and disabling the maskable interrupts and setting the priority for acknowledgement. The explanation does not apply to nonmaskable interrupts. Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in each interrupt control register to enable or disable maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control register. Figure 12.3 shows the Interrupt Control Register, Figure 12.4 shows Registers TRCIC, CM0IC, and CM1IC and Figure 12.5 shows the INTiIC Register (i=0, 1, 3). Interrupt Control Register(2) Symbol TREIC KUPIC ADIC S0TIC S0RIC TRAIC TRBIC Bit Symbol ILVL0 Address 004Ah 004Dh 004Eh 0051h 0052h 0056h 0058h Bit Name Interrupt priority level select bits After Reset XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b Function b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 RW RW ILVL1 ILVL2 Interrupt request bit 0 0 0 : Level 0 (interrupt disable) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : Requests no interrupt 1 : Requests interrupt RW RW IR — (b7-b4) RW(1) — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. NOTES: 1. Only 0 can be w ritten to the IR bit. Do not w rite 1. 2. Rew rite the interrupt control register w hen the interrupt request w hich is applicable for its register is not generated. Refer to 12.6.5 Changing Interrupt Control Register Contents . Figure 12.3 Interrupt Control Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 95 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts Interrupt Control Register(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRCIC CM0IC CM1IC Bit Symbol ILVL0 Address 0047h 005Bh 005Ch Bit Name Interrupt priority level select bits b2 b1 b0 After Reset XXXXX000b XXXXX000b XXXXX000b Function 0 0 0 : Level 0 (interrupt disable) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 RW RW ILVL1 RW ILVL2 Interrupt request bit RW IR — (b7-b4) 0 : Requests no interrupt 1 : Requests interrupt RO — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. NOTE: 1. Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated. Refer to 12.6.5 Changing Interrupt Control Register Contents . Figure 12.4 Registers TRCIC, CM0IC, and CM1IC Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 96 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts INTi Interrupt Control Register (i=0, 1, 3)(2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol INT1IC INT3IC INT0IC Bit Symbol ILVL0 Address 0059h 005Ah 005Dh Bit Name Interrupt priority level select bits After Reset XX00X000b XX00X000b XX00X000b Function b2 b1 b0 0 RW RW ILVL1 ILVL2 Interrupt request bit Polarity sw itch bit(4) Reserved bit 0 0 0 : Level 0 (interrupt disable) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : Requests no interrupt 1 : Requests interrupt 0 : Selects falling edge 1 : Selects rising edge(3) Set to 0. RW RW IR POL — (b5) — (b7-b6) RW(1) RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. NOTES: 1. Only 0 can be w ritten to the IR bit. (Do not w rite 1.) 2. Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated. Refer to 12.6.5 Changing Interrupt Control Register Contents . 3. If the INTiPL bit in the INTEN register is set to 1 (both edges), set the POL bit to 0 (selects falling edge). 4. The IR bit may be set to 1 (requests interrupt) w hen the POL bit is rew ritten. Refer to 12.6.4 Changing Interrupt Sources. Figure 12.5 INTiIC Register (i=0, 1, 3) Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 97 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts 12.1.6.1 I Flag The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable interrupts. Setting the I flag to 0 (disabled) disables all maskable interrupts. 12.1.6.2 IR Bit The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. Then, when the interrupt request is acknowledged and the CPU branches to the corresponding interrupt vector, the IR bit is set to 0 (= interrupt not requested). The IR bit can be set to 0 by a program. Do not write 1 to this bit. However, the IR bit operations of the timer RC interrupt, comparator 0 interrupt, and comparator 1 interrupt are different. Refer to 12.5 Timer RC Interrupt, Comparator 0 Interrupt, and Comparator 1 Interrupt. 12.1.6.3 ILVL2 to ILVL0 Bits and IPL Interrupt priority levels can be set using bits ILVL2 to ILVL0. Table 12.3 lists the Settings of Interrupt Priority Levels and Table 12.4 lists the Interrupt Priority Levels Enabled by IPL. The following are conditions under which an interrupt is acknowledged: • I flag = 1 • IR bit = 1 • Interrupt priority level > IPL The I flag, IR bit, bits ILVL2 to ILVL0, and IPL are independent of each other. They do not affect one another. Table 12.3 ILVL2 to ILVL0 Bits 000b 001b 010b 011b 100b 101b 110b 111b Settings of Interrupt Priority Levels Interrupt Priority Level Priority Order − Level 0 (interrupt disabled) Level 1 Low Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High Table 12.4 IPL 000b 001b 010b 011b 100b 101b 110b 111b Interrupt Priority Levels Enabled by IPL Enabled Interrupt Priority Levels Interrupt level 1 and above Interrupt level 2 and above Interrupt level 3 and above Interrupt level 4 and above Interrupt level 5 and above Interrupt level 6 and above Interrupt level 7 and above All maskable interrupts are disabled Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 98 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts 12.1.6.4 Interrupt Sequence An interrupt sequence is performed between an interrupt request acknowledgement and interrupt routine execution. When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle. However, for the SMOVB, SMOVF, SSTR, or RMPA instructions, if an interrupt request is generated while the instruction is being executed, the MCU suspends the instruction to start the interrupt sequence. The interrupt sequence is performed as indicated below. Figure 12.6 shows the Time Required for Executing Interrupt Sequence. (1) The CPU gets interrupt information (interrupt number and interrupt request level) by reading address 00000h. The IR bit for the corresponding interrupt is set to 0 (interrupt not requested).(2) (2) The FLG register is saved to a temporary register(1) in the CPU immediately before entering the interrupt sequence. (3) The I, D and U flags in the FLG register are set as follows: The I flag is set to 0 (interrupts disabled). The D flag is set to 0 (single-step interrupt disabled). The U flag is set to 0 (ISP selected). However, the U flag does not change state if an INT instruction for software interrupt number 32 to 63 is executed. (4) The CPU’s internal temporary register(1) is saved to the stack. (5) The PC is saved to the stack. (6) The interrupt priority level of the acknowledged interrupt is set in the IPL. (7) The starting address of the interrupt routine set in the interrupt vector is stored in the PC. After the interrupt sequence is completed, instructions are executed from the starting address of the interrupt routine. 1 CPU Clock Address Bus Data Bus RD WR 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Address 0000h Interrupt information Undefined Undefined Undefined SP-2 SP-1 SP-4 SP-3 SP-3 contents VEC VEC contents VEC+1 VEC+1 contents VEC+2 VEC+2 contents PC SP-2 SP-1 SP-4 contents contents contents The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is ready to acknowledge instructions. Figure 12.6 Time Required for Executing Interrupt Sequence NOTES: 1. This register cannot be used by user. 2. Refer to 12.5 Timer RC Interrupt, Comparator 0 Interrupt, and Comparator 1 Interrupt for the IR bit operations of the timer RC interrupt, comparator 0 interrupt, and comparator 1 interrupt. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 99 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts 12.1.6.5 Interrupt Response Time Figure 12.7 shows the Interrupt Response Time. The interrupt response time is the period between an interrupt request generation and the execution of the first instruction in the interrupt routine. The interrupt response time includes the period between interrupt request generation and the completion of execution of the instruction (refer to (a) in Figure 12.7) and the period required to perform the interrupt sequence (20 cycles, refer to (b) in Figure 12.7). Interrupt request is generated. Interrupt request is acknowledged. Time Instruction (a) Interrupt sequence 20 cycles (b) Instruction in interrupt routine Interrupt response time (a) Period between interrupt request generation and the completion of execution of an instruction. The length of time varies depending on the instruction being executed. The DIVX instruction requires the longest time, 30 cycles (no wait and when the register is set as the divisor) (b) 21 cycles for address match and single-step interrupts. Figure 12.7 Interrupt Response Time 12.1.6.6 IPL Change when Interrupt Request is Acknowledged When an interrupt request of a maskable interrupt is acknowledged, the interrupt priority level of the acknowledged interrupt is set in the IPL. When a software interrupt or special interrupt request is acknowledged, the level listed in Table 12.5 is set in the IPL. Table 12.5 lists the IPL Value When Software or Special Interrupt Is Acknowledged. Table 12.5 IPL Value When Software or Special Interrupt Is Acknowledged Value Set in IPL 7 Not changed Interrupt Source Watchdog timer, oscillation stop detection, voltage monitor 1, voltage monitor 2, address break Software, address match, single-step Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 100 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts 12.1.6.7 Saving a Register In the interrupt sequence, the FLG register and PC are saved to the stack. After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG register, are saved to the stack, the 16 low-order bits in the PC are saved. Figure 12.8 shows the Stack State Before and After Acknowledgement of Interrupt Request. The other necessary registers are saved by a program at the beginning of the interrupt routine. The PUSHM instruction can save several registers in the register bank being currently used(1) with a single instruction. NOTE: 1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB. Address MSB Stack LSB Address MSB Stack LSB m−4 m−3 m−2 m−1 m m−4 m−3 m−2 m−1 PCL PCM FLGL FLGH PCH [SP] New SP value Previous stack contents Previous stack contents [SP] SP value before interrupt is generated m Previous stack contents Previous stack contents m+1 m+1 PCH PCM PCL FLGH FLGL : 4 High-order bits of PC : 8 Middle-order bits of PC : 8 Low-order bits of PC : 4 High-order bits of FLG : 8 Low-order bits of FLG Stack state before interrupt request is acknowledged Stack state after interrupt request is acknowledged NOTE: 1.When executing software number 32 to 63 INT instructions, this SP is specified by the U flag. Otherwise it is ISP. Figure 12.8 Stack State Before and After Acknowledgement of Interrupt Request The register saving operation, which is performed as part of the interrupt sequence, saved in 8 bits at a time in four steps. Figure 12.9 shows the Register Saving Operation. Stack Sequence in which order registers are saved [SP]−5 [SP]−4 [SP]−3 [SP]−2 [SP]−1 Address PCL PCM FLGL FLGH PCH (3) (4) Saved, 8 bits at a time (1) (2) [SP] Completed saving registers in four operations. PCH PCM PCL FLGH FLGL : 4 High-order bits of PC : 8 Middle-order bits of PC : 8 Low-order bits of PC : 4 High-order bits of FLG : 8 Low-order bits of FLG NOTE: 1. [SP] indicates the initial value of the SP when an interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. When executing software number 32 to 63 INT instructions, this SP is specified by the U flag. Otherwise it is ISP. Figure 12.9 Register Saving Operation Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 101 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts 12.1.6.8 Returning from an Interrupt Routine When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have been saved to the stack, are automatically restored. The program, that was running before the interrupt request was acknowledged, starts running again. Restore registers saved by a program in an interrupt routine using the POPM instruction or others before executing the REIT instruction. 12.1.6.9 Interrupt Priority If two or more interrupt requests are generated while a single instruction is being executed, the interrupt with the higher priority is acknowledged. Set bits ILVL2 to ILVL0 to select the desired priority level for maskable interrupts (peripheral functions). However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware, and the higher priority interrupts acknowledged. The priority levels of special interrupts, such as reset (reset has the highest priority) and watchdog timer, are set by hardware. Figure 12.10 shows the Priority Levels of Hardware Interrupts. The interrupt priority does not affect software interrupts. The MCU jumps to the interrupt routine when the instruction is executed. Reset Address break Watchdog timer Oscillation stop detection Voltage monitor 1 Voltage monitor 2 Peripheral function Single step Address match High Low Figure 12.10 Priority Levels of Hardware Interrupts Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 102 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts 12.1.6.10 Interrupt Priority Judgement Circuit The interrupt priority judgement circuit selects the highest priority interrupt, as shown in Figure 12.11. Priority level of interrupt Level 0 (default value) Highest Comparator 0 INT3 Timer RB Timer RA INT0 Comparator 1 INT1 Timer RC UART0 receive A/D conversion Timer RE UART0 transmit Key input IPL Lowest Interrupt request level judgment output signal I flag Address match Watchdog timer Oscillation stop detection Voltage monitor 1 Voltage monitor 2 Interrupt request acknowledged Priority of peripheral function interrupts (if priority levels are same) Figure 12.11 Interrupt Priority Level Judgement Circuit Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 103 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts 12.2 12.2.1 INT Interrupt INTi Interrupt (i = 0, 1, 3) The INTi interrupt is generated by an INTi input. When using the INTi interrupt, the INTiEN bit in the INTEN register is set to 1 (enable). The edge polarity is selected using the INTiPL bit in the INTEN register and the POL bit in the INTiIC register. Inputs can be passed through a digital filter with three different sampling clocks. The INT0 pin is shared with the pulse output forced cutoff of timer RC and is shared with the external trigger input of timer RB. Figure 12.12 shows the INTEN Register. Figure 12.13 shows the INTF Register. External Input Enable Register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol INTEN Bit Symbol INT0EN INT0PL INT1EN INT1PL — (b5-b4) INT3EN INT3PL Address 00F9h Bit Name _____ INT0 input enable bit INT0 input polarity select bit(1,2) _____ _____ After Reset 00h Function 0 : Disable 1 : Enable 0 : One edge 1 : Both edges 0 : Disable 1 : Enable 0 : One edge 1 : Both edges Set to 0. 0 : Disable 1 : Enable 0 : One edge 1 : Both edges RW RW RW RW RW RW RW RW INT1 input enable bit INT1 input polarity select bit(1,2) Reserved bits _____ _____ INT3 input enable bit INT3 input polarity select bit(1,2) _____ NOTES: 1. When setting the INTiPL bit (i = 0 to 3) to 1 (both edges), set the POL bit in the INTiIC register to 0 (selects falling edge). 2. The IR bit in the INTiIC register may be set to 1 (requests interrupt) w hen the INTiPL bit is rew ritten. Refer to 12.6.4 Changing Interrupt Sources. Figure 12.12 INTEN Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 104 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts _______ INT0 Input Filter Select Register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol INTF Bit Symbol _____ Address 00FAh Bit Name INT0 input filter select bits b1 b0 After Reset 00h Function 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling RW RW INT0F0 INT0F1 _____ RW INT1F0 INT1 input filter select bits b3 b2 INT1F1 — (b5-b4) INT3F0 Reserved bits _____ 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling Set to 0. b7 b6 RW RW RW INT3 input filter select bits INT3F1 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling RW RW Figure 12.13 INTF Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 105 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts 12.2.2 INTi Input Filter (i = 0, 1, 3) The INTi input contains a digital filter. The sampling clock is selected by bits INTiF1 to INTiF0 in the INTF register. The IR bit in the INTiIC register is set to 1 (interrupt requested) when the INTi level is sampled for every sampling clock and the sampled input level matches three times. Figure 12.14 shows the Configuration of INTi Input Filter. Figure 12.15 shows an Operating Example of INTi Input Filter. INTiF1 to INTiF0 f1 f8 f32 = 01b = 10b = 11b Sampling clock INTiEN Other than INTiF1 to INTiF0 = 00b INTi Port direction register(1) Digital filter (input level matches 3x) INTi interrupt INTiPL = 0 = 00b INTiF0, INTiF1: Bits in INTF register INTiEN, INTiPL: Bits in INTEN register i = 0, 1, 3 NOTE: 1. INT0: Port P4_5 direction register INT1: Port P1_5 direction register when using the P1_5 pin Port P1_7 direction register when using the P1_7 pin INT3: Port P3_3 direction register Both edges detection INTiPL = 1 circuit Figure 12.14 Configuration of INTi Input Filter INTi input Sampling timing IR bit in INTiIC register Set to 0 in program This is an operation example when bits INTiF1 to INTiF0 in the INTiF register are set to 01b, 10b, or 11b (passing digital filter). i = 0, 1, 3 Figure 12.15 Operating Example of INTi Input Filter Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 106 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts 12.3 Key Input Interrupt A key input interrupt request is generated by one of the input edges of the K10 to K13 pins. The key input interrupt can be used as a key-on wake-up function to exit wait or stop mode. The KIiEN (i = 0 to 3) bit in the KIEN register can select whether the pins are used as KIi input. The KIiPL bit in the KIEN register can select the input polarity. When inputting “L” to the KIi pin which sets the KIiPL bit to 0 (falling edge), the input of the other pins K10 to K13 is not detected as interrupts. Also, when inputting “H” to the KIi pin, which sets the KIiPL bit to 1 (rising edge), the input of the other pins K10 to K13 is not detected as interrupts. Figure 12.16 shows a Block Diagram of Key Input Interrupt. PU02 bit in PUR0 register Pull-up transistor KUPIC register PD1_3 bit in PD1 register KI3EN bit PD1_3 bit KI3PL = 0 KI3 KI3PL = 1 Pull-up transistor KI2 KI2PL = 1 Pull-up transistor KI1 KI1PL = 1 Pull-up transistor KI0 KI0PL = 1 KI0EN bit PD1_0 bit KI0PL = 0 KI0EN, KI1EN, KI2EN, KI3EN, KI0PL, KI1PL, KI2PL, KI3PL: Bits in KIEN register PD1_0, PD1_1, PD1_2, PD1_3: Bits in PD1 register KI1EN bit PD1_1 bit KI1PL = 0 KI2EN bit PD1_2 bit KI2PL = 0 Interrupt control circuit Key input interrupt request Figure 12.16 Block Diagram of Key Input Interrupt Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 107 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts Key Input Enable Register(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol KIEN Bit Symbol KI0EN KI0PL KI1EN KI1PL KI2EN KI2PL KI3EN KI3PL Address 00FBh Bit Name KI0 input enable bit KI0 input polarity select bit KI1 input enable bit KI1 input polarity select bit KI2 input enable bit KI2 input polarity select bit KI3 input enable bit KI3 input polarity select bit After Reset 00h Function 0 : Disable 1 : Enable 0 : Falling edge 1 : Rising edge 0 : Disable 1 : Enable 0 : Falling edge 1 : Rising edge 0 : Disable 1 : Enable 0 : Falling edge 1 : Rising edge 0 : Disable 1 : Enable 0 : Falling edge 1 : Rising edge RW RW RW RW RW RW RW RW RW NOTE: 1. The IR bit in the KUPIC register may be set to 1 (requests interrupt) w hen the KIEN register is rew ritten. Refer to 12.6.4 Changing Interrupt Sources. Figure 12.17 KIEN Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 108 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts 12.4 Address Match Interrupt An address match interrupt request is generated immediately before execution of the instruction at the address indicated by the RMADi register (i = 0 or 1). This interrupt is used as a break function by the debugger. When using the on-chip debugger, do not set an address match interrupt (registers of AIER, RMAD0, and RMAD1 and fixed vector tables) in a user system. Set the starting address of any instruction in the RMADi register. Bits AIER0 and AIER1 in the AIER0 register can be used to select enable or disable of the interrupt. The I flag and IPL do not affect the address match interrupt. The value of the PC (Refer to 12.1.6.7 Saving a Register for the value of the PC) which is saved to the stack when an address match interrupt is acknowledged varies depending on the instruction at the address indicated by the RMADi register. (The appropriate return address is not saved on the stack.) When returning from the address match interrupt, return by one of the following means: • Change the content of the stack and use the REIT instruction. • Use an instruction such as POP to restore the stack as it was before the interrupt request was acknowledged. Then use a jump instruction. Table 12.6 lists the Values of PC Saved to Stack when Address Match Interrupt is Acknowledged, Table 12.7 lists the Correspondence Between Address Match Interrupt Sources and Associated Registers. Figure 12.18 shows Registers AIER and RMAD0 to RMAD1. Table 12.6 Values of PC Saved to Stack when Address Match Interrupt is Acknowledged Address Indicated by RMADi Register (i = 0 or 1) • Instruction with 2-byte operation • Instruction with 1-byte operation code(2) ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ STNZ #IMM8,dest STZX #IMM81,#IMM82,dest CMP.B:S #IMM8,dest PUSHM src POPM JMPS #IMM8 JSRS #IMM8 MOV.B:S #IMM,dest (however, dest = A0 or A1) • Instructions other than the above code(2) PC Value Saved(1) Address indicated by RMADi register + 2 #IMM8,dest #IMM8,dest dest Address indicated by RMADi register + 1 NOTES: 1. Refer to the 12.1.6.7 Saving a Register for the PC value saved. 2. Operation code: Refer to the R8C/Tiny Series Software Manual (REJ09B0001). Chapter 4. Instruction Code/Number of Cycles contains diagrams showing operation code below each syntax. Operation code is shown in the bold frame in the diagrams. Table 12.7 Correspondence Between Address Match Interrupt Sources and Associated Registers Address Match Interrupt Source Address Match Interrupt Enable Bit Address Match Interrupt Register Address match interrupt 0 AIER0 RMAD0 Address match interrupt 1 AIER1 RMAD1 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 109 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts A ddress Match Interrupt Enable Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER Bit Symbol AIER0 AIER1 — (b7-b2) Address 0013h Bit Name Address match interrupt 0 enable bit 0 : Disable 1 : Enable Address match interrupt 1 enable bit 0 : Disable 1 : Enable Nothing is assigned. If necessary, set to 0. When read, the content is 0. After Reset 00h Function RW RW RW — Address Match Interrupt Register i(i = 0 or 1) (b23) b7 (b19) b3 (b16) (b15) b0 b7 (b8) b0 b7 b0 Symbol RMAD0 RMAD1 Function Address 0012h-0010h 0016h-0014h After Reset 000000h 000000h Setting Range 00000h to FFFFFh RW RW — Address setting register for address match interrupt — Nothing is assigned. If necessary, set to 0. (b7-b4) When read, the content is 0. Figure 12.18 Registers AIER and RMAD0 to RMAD1 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 110 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts 12.5 Timer RC Interrupt, Comparator 0 Interrupt, and Comparator 1 Interrupt As with other maskable interrupts, the timer RC interrupt, comparator 0 interrupt, and comparator 1 interrupt are controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, some differences from other maskable interrupts apply. Refer to chapters of the individual peripheral functions (14.3 Timer RC and 19.4 Comparator 0 Interrupt and Comparator 1 Interrupt) for the status register and enable register. Refer to 12.1.6 Interrupt Control for the interrupt control register. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 111 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts 12.6 12.6.1 Notes on Interrupts Reading Address 00000h Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At this time, the acknowledged interrupt IR bit is set to 0. If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be generated. 12.6.2 SP Setting Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset. Therefore, if an interrupt is acknowledged before setting a value in the SP, the program may run out of control. 12.6.3 External Interrupt and Key Input Interrupt Either “L” level or an “H” level of width shown in the Electrical Characteristics is necessary for the signal input to pins INT0, INT1, INT3 and pins KI0 to KI3, regardless of the CPU clock. For details, refer to Table 21.19 (VCC = 5V), Table 21.25 (VCC = 3V) External Interrupt INTi (i = 0, 1, 3) Input. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 112 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts 12.6.4 Changing Interrupt Sources The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source. In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to individual software interrupt numbers, polarities, and timing. Therefore, if a mode change of a peripheral function involves interrupt sources, edge polarities, and timing, set the IR bit to 0 (no interrupt requested) after the change. Refer to the individual peripheral function for its related interrupts. Figure 12.19 shows an Example of Procedure for Changing Interrupt Sources. Interrupt source change Disable interrupts(2, 3) Change interrupt source (including mode of peripheral function) Set the IR bit to 0 (interrupt not requested) using the MOV instruction(3) Enable interrupts (2, 3) Change completed IR bit: The interrupt control register bit of an interrupt whose source is changed. NOTES: 1. Execute the above settings individually. Do not execute two or more settings at once (by one instruction). 2. To prevent interrupt requests from being generated, disable the peripheral function before changing the interrupt source. In this case, use the I flag if all maskable interrupts can be disabled. If all maskable interrupts cannot be disabled, use bits ILVL0 to ILVL2 of the interrupt whose source is changed. 3. Refer to 12.6.5 Changing Interrupt Control Register Contents for the instructions to be used and usage notes. Figure 12.19 Example of Procedure for Changing Interrupt Sources Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 113 of 332 R8C/2E Group, R8C/2F Group 12. Interrupts 12.6.5 Changing Interrupt Control Register Contents (a) The contents of an interrupt control register can only be changed while no interrupt requests corresponding to that register are generated. If interrupt requests may be generated, disable interrupts before changing the interrupt control register contents. (b) When changing the contents of an interrupt control register after disabling interrupts, be careful to choose appropriate instructions. Changing any bit other than IR bit If an interrupt request corresponding to a register is generated while executing the instruction, the IR bit may not be set to 1 (interrupt requested), and the interrupt request may be ignored. If this causes a problem, use the following instructions to change the register: AND, OR, BCLR, BSET Changing IR bit If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used. Therefore, use the MOV instruction to set the IR bit to 0. (c) When disabling interrupts using the I flag, set the I flag as shown in the sample programs below. Refer to (b) regarding changing the contents of interrupt control registers by the sample programs. Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before the interrupt control register is changed for reasons of the internal bus or the instruction queue buffer. Example 1: Use NOP instructions to prevent I flag from being set to 1 before interrupt control register is changed INT_SWITCH1: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h NOP ; NOP FSET I ; Enable interrupts Example 2: Use dummy read to delay FSET instruction INT_SWITCH2: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h MOV.W MEM,R0 ; Dummy read FSET I ; Enable interrupts Example 3: Use POPC instruction to change I flag INT_SWITCH3: PUSHC FLG FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h POPC FLG ; Enable interrupts Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 114 of 332 R8C/2E Group, R8C/2F Group 13. Watchdog Timer 13. Watchdog Timer The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is recommended to improve the reliability of the system. The watchdog timer contains a 15-bit counter and allows selection of count source protection mode enable or disable. Table 13.1 lists the Specifications for Watchdog Timer. Refer to 5.5 Watchdog Timer Reset for details on the watchdog timer. Figure 13.1 shows the Block Diagram of Watchdog Timer, Figure 13.2 shows the Registers WDTR, WDTS, and WDC and Figure 13.3 shows the Registers CSPR and OFS. Table 13.1 Specifications for Watchdog Timer Count Source Protection Mode Disabled Count Source Protection Mode Enabled CPU clock Low-speed on-chip oscillator clock Decrement Either of the following can be selected • After reset, count starts automatically • Count starts by writing to WDTS register Count stop condition Stop mode, wait mode None Reset condition of • Reset • Write 00h to the WDTR register before writing FFh watchdog timer • Underflow Operation at the time Watchdog timer interrupt or watchdog Watchdog timer reset of underflow timer reset Select functions • Division ratio of prescaler Selected by the WDC7 bit in the WDC register • Count source protection mode Whether count source protection mode is enabled or disabled after a reset can be selected by the CSPROINI bit in the OFS register (flash memory). If count source protection mode is disabled after a reset, it can be enabled or disabled by the CSPRO bit in the CSPR register (program). • Starts or stops of the watchdog timer after a reset Selected by the WDTON bit in the OFS register (flash memory). Item Count source Count operation Count start condition Prescaler 1/16 CPU clock 1/128 WDC7 = 0 CSPRO = 0 PM12 = 0 Watchdog timer interrupt request WDC7 = 1 Watchdog timer PM12 = 1 Watchdog timer reset fOCO-S CSPRO = 1 Set to 7FFFh(1) Write to WDTR register Internal reset signal CSPRO: Bit in CSPR register WDC7: Bit in WDC register PM12: Bit in PM1 register NOTE: 1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set. Figure 13.1 Block Diagram of Watchdog Timer Page 115 of 332 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 R8C/2E Group, R8C/2F Group 13. Watchdog Timer Watchdog Timer Reset Register b7 b0 Symbol WDTR Address 000Dh After Reset Undefined RW Function When 00h is w ritten before w riting FFh, the w atchdog timer is reset.(1) The default value of the w atchdog timer is 7FFFh w hen count source protection mode is disabled and 0FFFh w hen count source protection mode is enabled.(2) NOTES: 1. Do not generate an interrupt betw een w hen 00h and FFh are w ritten. 2. When the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled), 0FFFh is set in the w atchdog timer. WO Watchdog Timer Start Register b7 b0 Symbol WDTS Address 000Eh After Reset Undefined RW WO Function The w atchdog timer starts counting after a w rite instruction to this register. Watchdog Timer Control Register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol Address 000Fh WDC Bit Symbol Bit Name — High-order bits of w atchdog timer (b4-b0) — (b5) — (b6) WDC7 Reserved bit Reserved bit Prescaler select bit After Reset 00X11111b Function RW RO RW RW RW Set to 0. When read, the content is undefined. Set to 0. 0 : Divide-by-16 1 : Divide-by-128 Figure 13.2 Registers WDTR, WDTS, and WDC Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 116 of 332 R8C/2E Group, R8C/2F Group 13. Watchdog Timer Count Source Protection Mode Register b7 b6 b5 b4 b3 b2 b1 b0 0000000 Symbol Address 001Ch CSPR Bit Symbol Bit Name — Reserved Bits (b6-b0) CSPRO After Reset(1) 00h Function Set to 0. RW RW RW Count Source Protection Mode 0 : Count source protection mode disabled 1 : Count source protection mode enabled Select Bit(2) NOTES: 1. When 0 is w ritten to the CSPROINI bit in the OFS register, the value after reset is 10000000b. 2. Write 0 before w riting 1 to set the CSPRO bit to 1. 0 cannot be set by a program. Option Function Select Register(1) b7 b6 b5 b4 b3 b2 b1 b0 101 1 Symbol OFS Bit Symbol WDTON — (b1) ROMCR ROMCP1 — (b4) — (b5) — (b6) Address 0FFFFh Bit Name Watchdog timer start select bit Reserved bit ROM code protect disabled bit ROM code protect bit Reserved bit Reserved bit Reserved bit When Shipping FFh(2) Function 0 : Starts w atchdog timer automatically after reset 1 : Watchdog timer is inactive after reset Set to 1. 0 : ROM code protect disabled 1 : ROMCP1 enabled 0 : ROM code protect enabled 1 : ROM code protect disabled Set to 1. Set to 0. Set to 1. 0 : Count source protect mode enabled after reset 1 : Count source protect mode disabled after reset RW RW RW RW RW RW RW RW Count source protect CSPROINI mode after reset select bit RW NOTES: 1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not w rite additions to the OFS register. 2. If the block including the OFS register is erased, FFh is set to the OFS register. Figure 13.3 Registers CSPR and OFS Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 117 of 332 R8C/2E Group, R8C/2F Group 13. Watchdog Timer 13.1 Count Source Protection Mode Disabled The count source of the watchdog timer is the CPU clock when count source protection mode is disabled. Table 13.2 lists the Watchdog Timer Specifications (with Count Source Protection Mode Disabled). Table 13.2 Watchdog Timer Specifications (with Count Source Protection Mode Disabled) Item Count source Count operation Period CPU clock Decrement Division ratio of prescaler (n) × count value of watchdog timer (32768)(1) CPU clock n: 16 or 128 (selected by WDC7 bit in WDC register) Example: When the CPU clock frequency is 16 MHz and prescaler divides by 16, the period is approximately 32.8 ms • Reset • Write 00h to the WDTR register before writing FFh • Underflow The WDTON bit(2) in the OFS register (0FFFFh) selects the operation of the watchdog timer after a reset • When the WDTON bit is set to 1 (watchdog timer is in stop state after reset) The watchdog timer and prescaler stop after a reset and the count starts when the WDTS register is written to • When the WDTON bit is set to 0 (watchdog timer starts automatically after exiting) • The watchdog timer and prescaler start counting automatically after a reset Stop and wait modes (inherit the count from the held value after exiting modes) • When the PM12 bit in the PM1 register is set to 0 Watchdog timer interrupt • When the PM12 bit in the PM1 register is set to 1 Watchdog timer reset (refer to 5.5 Watchdog Timer Reset) Specification Reset condition of watchdog timer Count start condition Count stop condition Operation at time of underflow NOTES: 1. The watchdog timer is reset when 00h is written to the WDTR register before FFh. The prescaler is reset after the MCU is reset. Some errors in the period of the watchdog timer may be caused by the prescaler. 2. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address 0FFFFh with a flash programmer. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 118 of 332 R8C/2E Group, R8C/2F Group 13. Watchdog Timer 13.2 Count Source Protection Mode Enabled The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection mode is enabled. If the CPU clock stops when a program is out of control, the clock can still be supplied to the watchdog timer. Table 13.3 lists the Watchdog Timer Specifications (with Count Source Protection Mode Enabled). Table 13.3 Watchdog Timer Specifications (with Count Source Protection Mode Enabled) Item Count source Count operation Period Specification Low-speed on-chip oscillator clock Decrement Count value of watchdog timer (4096) Low-speed on-chip oscillator clock Example: Period is approximately 32.8 ms when the low-speed onchip oscillator clock frequency is 125 kHz • Reset • Write 00h to the WDTR register before writing FFh • Underflow The WDTON bit(1) in the OFS register (0FFFFh) selects the operation of the watchdog timer after a reset. • When the WDTON bit is set to 1 (watchdog timer is in stop state after reset) The watchdog timer and prescaler stop after a reset and the count starts when the WDTS register is written to • When the WDTON bit is set to 0 (watchdog timer starts automatically after reset) The watchdog timer and prescaler start counting automatically after a reset None (The count does not stop in wait mode after the count starts. The MCU does not enter stop mode.) Watchdog timer reset (Refer to 5.5 Watchdog Timer Reset.) • When setting the CSPPRO bit in the CSPR register to 1 (count source protection mode is enabled)(2), the following are set automatically - Set 0FFFh to the watchdog timer - Set the CM14 bit in the CM1 register to 0 (low-speed on-chip oscillator on) - Set the PM12 bit in the PM1 register to 1 (The watchdog timer is reset when watchdog timer underflows) • The following conditions apply in count source protection mode - Writing to the CM10 bit in the CM1 register is disabled (It remains unchanged even if it is set to 1. The MCU does not enter stop mode.) - Writing to the CM14 bit in the CM1 register is disabled (It remains unchanged even if it is set to 1. The low-speed on-chip oscillator does not stop.) Reset condition of watchdog timer Count start condition Count stop condition Operation at time of underflow Registers, bits NOTES: 1. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address 0FFFFh with a flash programmer. 2. Even if 0 is written to the CSPROINI bit in the OFS register, the CSPRO bit is set to 1. The CSPROINI bit cannot be changed by a program. To set the CSPROINI bit, write 0 to bit 7 of address 0FFFFh with a flash programmer. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 119 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14. Timers The MCU has two 8-bit timers with 8-bit prescalers, a 16-bit timer, and a timer with a 4-bit counter and an 8-bit counter. The two 8-bit timers with 8-bit prescalers are timer RA and timer RB. These timers contain a reload register to store the default value of the counter. The 16-bit timer is timer RC, and has input capture and output compare functions. The 4-bit and 8-bit counters are timer RE, and has an output compare function. All the timers operate independently. Table 14.1 lists Functional Comparison of Timers. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 120 of 332 R8C/2E Group, R8C/2F Group 14. Timers Table 14.1 Functional Comparison of Timers Timer RA 8-bit timer with 8bit prescaler (with reload register) Decrement • f1 • f2 • f8 • fOCO Timer RB 8-bit timer with 8bit prescaler (with reload register) Decrement • f1 • f2 • f8 • Timer RA underflow Timer RC 16-bit free-run timer (with input capture and output compare) Increment • f1 • f2 • f4 • f8 • f32 • fOCO40M • TRCCLK provided (input capture function, output compare function) not provided not provided not provided not provided not provided Timer RE 4-bit counter 8-bit counter Increment • f4 • f8 • f32 Item Configuration Count Count source Function Timer Mode provided provided not provided Pulse Output Mode Event Counter Mode Pulse Width Measurement Mode Pulse Period Measurement Mode Programmable Waveform Generation Mode Programmable One-Shot generation Mode Programmable Wait One-Shot Generation Mode Input Capture Mode Output Compare Mode PWM Mode PWM2 Mode Input Pin provided provided provided provided not provided not provided not provided not provided not provided provided not provided not provided not provided not provided not provided not provided provided not provided not provided not provided provided not provided not provided not provided not provided not provided not provided TRAIO not provided not provided not provided not provided provided provided provided provided not provided provided Output Pin Related Interrupt Timer Stop not provided not provided INT0, TRCCLK, TRCTRG − INT0 TRCIOA, TRCIOB, TRCIOC, TRCIOD TRAO TRBO TRCIOA, TRCIOB, TREO TRAIO TRCIOC, TRCIOD Timer RE Timer RA interrupt Timer RB interrupt Compare Match / Input interrupt INT0 interrupt Capture A to D interrupt INT1 interrupt Overflow interrupt INT0 interrupt provided provided provided provided Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 121 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.1 Timer RA Timer RA is an 8-bit timer with an 8-bit prescaler. The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated at the same address, and can be accessed when accessing registers TRAPRE and TRA (refer to Tables 14.2 to 14.6 the Specification of Each Modes). The count source for timer RA is the operating clock that regulates the timing of timer operations such as counting and reloading. Figure 14.1 shows a Block Diagram of Timer RA. Figures 14.2 and 14.3 show the registers associated with Timer RA. Timer RA contains the following five operating modes: • Timer mode: The timer counts the internal count source. • Pulse output mode: The timer counts the internal count source and outputs pulses which invert the polarity by underflow of the timer. • Event counter mode: The timer counts external pulses. • Pulse width measurement mode: The timer measures the pulse width of an external pulse. • Pulse period measurement mode: The timer measures the pulse period of an external pulse. Data bus TCK2 to TCK0 bit f1 = 001b f8 = 010b fOCO = 011b f2 = 000b TCKCUT bit TMOD2 to TMOD0 = other than 010b Reload register TCSTF bit Counter TRAPRE register (prescaler) Reload register Underflow signal Timer RA interrupt TIPF1 to TIPF0 bits f1 = 10b f8 = 11b f32 TIPF1 to TIPF0 bits TIOSEL = 0 = other than Digital 000b INT1/TRAIO (P1_7) pin = 01b TMOD2 to TMOD0 = 010b Counter TRA register (timer) TMOD2 to TMOD0 = 011b or 100b Polarity switching Count control circle filter INT1/TRAIO (P1_5) pin TIOSEL = 1 = 00b Measurement completion signal Toggle flip-flop CLR TMOD2 to TMOD0 = 001b TEDGSEL = 1 TOPCR bit Q TOENA bit TRAO pin Q TEDGSEL = 0 CK Write to TRAMR register Write 1 to TSTOP bit TCSTF, TSTOP: TRACR register TEDGSEL, TOPCR, TOENA, TIOSEL, TIPF1, TIPF0: TRAIOC register TMOD2 to TMOD0, TCK2 to TCK0, TCKCUT: TRAMR register Figure 14.1 Block Diagram of Timer RA Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 122 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RA Control Register(4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRACR Bit Symbol TSTART TCSTF TSTOP — (b3) TEDGF Address 0100h Bit Name Timer RA count start bit(1) After Reset 00h Function 0 : Count stops 1 : Count starts RW RW RO RW — Timer RA count status flag(1) 0 : Count stops 1 : During count Timer RA count forcible stop When this bit is set to 1, the count is forcibly bit(2) stopped. When read, its content is 0. Nothing is assigned. If necessary, set to 0. When read, the content is 0. Active edge judgment flag(3, 5) 0 : Active edge not received 1 : Active edge received (end of measurement period) RW TUNDF — (b7-b6) Timer RA underflow flag(3, 5) 0 : No underflow 1 : Underflow Nothing is assigned. If necessary, set to 0. When read, the content is 0. RW — NOTES: 1. Refer to 14.1.6 Notes on Tim er RA f or precautions regarding bits TSTART and TCSTF. 2. When the TSTOP bit is set to 1, bits TSTART and TCSTF and registers TPRAPRE and TRA are set to the values after a reset. 3. Bits TEDGF and TUNDF can be set to 0 by w riting 0 to these bits by a program. How ever, their value remains unchanged w hen 1 is w ritten. 4. In pulse w idth measurement mode and pulse period measurement mode, use the MOV instruction to set the TRACR register. If it is necessary to avoid changing the values of bits TEDGF and TUNDF, w rite 1 to them. 5. Set to 0 in timer mode, pulse output mode, and event counter mode. Timer RA I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 — (b7-b6) Address 0101h Bit Name TRAIO polarity sw itch bit TRAIO output control bit TRAO output enable bit _____ After Reset 00h Function Function varies depending on operating mode. RW RW RW RW RW RW — INT1/TRAIO select bit TRAIO input filter select bits Nothing is assigned. If necessary, set to 0. When read, the content is 0. Figure 14.2 Registers TRACR and TRAIOC Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 123 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RA Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRAMR Bit Symbol TMOD0 Address 0102h Bit Name Timer RA operating mode select bits (1) After Reset 00h Function b2 b1 b0 RW RW TMOD1 TMOD2 — (b3) TCK0 0 0 0 : Timer mode 0 0 1 : Pulse output mode 0 1 0 : Event counter mode 0 1 1 : Pulse w idth measurement mode 1 0 0 : Pulse period measurement mode 101: 1 1 0 : Do not set. 111: RW RW Nothing is assigned. If necessary, set to 0. When read, the content is 0. Timer RA count source select bits b6 b5 b4 — TCK1 TCK2 Timer RA count source cutoff bit 0 0 0 : f1 0 0 1 : f8 0 1 0 : fOCO 0 1 1 : f2 100: 1 0 1 : Do not set. 110: 111: 0 : Provides count source 1 : Cuts off count source RW RW RW TCKCUT RW NOTE: 1. When both the TSTART and TCSTF bits in the TRACR register are set to 0 (count stops), rew rite this register. Timer RA Prescaler Register b7 b0 Symbol TRAPRE Mode Timer mode Pulse output mode Event counter mode Pulse w idth measurement mode Pulse period measurement mode Address 0103h Function Counts an internal count source Counts an external count source Measure pulse w idth of input pulses from external (counts internal count source) Measure pulse period of input pulses from external (counts internal count source) After Reset FFh(1) Setting Range 00h to FFh 00h to FFh 00h to FFh 00h to FFh 00h to FFh RW RW RW RW RW RW NOTE: 1. When the TSTOP bit in the TRACR register is set to 1, the TRAPRE register is set to FFh. Timer RA Register b7 b0 Symbol TRA Mode All modes Address 0104h Function Counts on underflow of timer RA prescaler register After Reset FFh(1) Setting Range 00h to FFh RW RW NOTE: 1. When the TSTOP bit in the TRACR register is set to 1, the TRA register is set to FFh. Figure 14.3 Registers TRAMR, TRAPRE, and TRA Page 124 of 332 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 R8C/2E Group, R8C/2F Group 14. Timers 14.1.1 Timer Mode In this mode, the timer counts an internally generated count source (refer to Table 14.2 Timer Mode Specifications). Figure 14.4 shows TRAIOC Register in Timer Mode. Table 14.2 Timer Mode Specifications Specification f1, f2, f8, fOCO • Decrement • When the timer underflows, the contents of the reload register are reloaded and the count is continued. 1/(n+1)(m+1) n: Value set in TRAPRE register, m: Value set in TRA register 1 (count starts) is written to the TSTART bit in the TRACR register. • 0 (count stops) is written to the TSTART bit in the TRACR register. • 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. When timer RA underflows [timer RA interrupt]. Programmable I/O port, or INT1 interrupt input Programmable I/O port The count value can be read by reading registers TRA and TRAPRE. • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter. • When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 Timer Write Control during Count Operation). Item Count sources Count operations Divide ratio Count start condition Count stop conditions Interrupt request generation timing INT1/TRAIO pin function TRAO pin function Read from timer Write to timer Timer RA I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 00 000 Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 — (b7-b6) Address 0101h Bit Name TRAIO polarity sw itch bit TRAIO output control bit TRAO output enable bit _____ After Reset 00h Function Set to 0 in timer mode. RW RW RW RW _____ 0 : INT1/TRAIO pin (P1_7) _____ 1 : INT1/TRAIO pin (P1_5) TRAIO input filter select bits Set to 0 in timer mode. Nothing is assigned. If necessary, set to 0. When read, the content is 0. INT1/TRAIO select bit RW RW — Figure 14.4 TRAIOC Register in Timer Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 125 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.1.1.1 Timer Write Control during Count Operation Timer RA has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each consist of a reload register and a counter. When writing to the prescaler or timer, values are written to both the reload register and counter. However, values are transferred from the reload register to the counter of the prescaler in synchronization with the count source. In addition, values are transferred from the reload register to the counter of the timer in synchronization with prescaler underflows. Therefore, if the prescaler or timer is written to when count operation is in progress, the counter value is not updated immediately after the WRITE instruction is executed. Figure 14.5 shows an Operating Example of Timer RA when Counter Value is Rewritten during Count Operation. Set 01h to the TRAPRE register and 25h to the TRA register by a program. Count source After writing, the reload register is written to at the first count source. Reloads register of timer RA prescaler Previous value Reload at second count source Counter of timer RA prescaler 06h 05h 04h 01h 00h New value (01h) Reload at underflow 01h 00h 01h 00h 01h 00h After writing, the reload register is written to at the first underflow. Reloads register of timer RA Previous value New value (25h) Reload at the second underflow Counter of timer RA 03h 02h 25h 24h IR bit in TRAIC register 0 The IR bit remains unchanged until underflow is generated by a new value. The above applies under the following conditions. Both bits TSTART and TCSTF in the TRACR register are set to 1 (During count). Figure 14.5 Operating Example of Timer RA when Counter Value is Rewritten during Count Operation Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 126 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.1.2 Pulse Output Mode In pulse output mode, the internally generated count source is counted, and a pulse with inverted polarity is output from the TRAIO pin each time the timer underflows (refer to Table 14.3 Pulse Output Mode Specifications). Figure 14.6 shows TRAIOC Register in Pulse Output Mode. Table 14.3 Pulse Output Mode Specifications Specification f1, f2, f8, fOCO • Decrement • When the timer underflows, the contents in the reload register is reloaded and the count is continued. Divide ratio 1/(n+1)(m+1) n: Value set in TRAPRE register, m: Value set in TRA register Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register. Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register. • 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. Interrupt request When timer RA underflows [timer RA interrupt]. generation timing INT1/TRAIO pin function TRAO pin function Read from timer Write to timer Pulse output, programmable output port, or INT1 interrupt(1) Programmable I/O port or inverted output of TRAIO(1) The count value can be read by reading registers TRA and TRAPRE. • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter. • When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 Timer Write Control during Count Operation). • TRAIO signal polarity switch function The TEDGSEL bit in the TRAIOC register selects the level at the start of pulse output.(1) • TRAO output function Pulses inverted from the TRAIO output polarity can be output from the TRAO pin (selectable by the TOENA bit in the TRAIOC register). • Pulse output stop function Output from the TRAIO pin is stopped by the TOPCR bit in the TRAIOC register. • INT1/TRAIO pin select function P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register. Item Count sources Count operations Select functions NOTE: 1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR register is written to. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 127 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RA I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 — (b7-b6) Address 0101h Bit Name TRAIO polarity sw itch bit TRAIO output control bit TRAO output enable bit _____ After Reset 00h Function 0 : TRAIO output starts at “H” 1 : TRAIO output starts at “L” 0 : TRAIO output 1 : Port P1_7 or P1_5 0 : Port P3_7 1 : TRAO output (inverted TRAIO output from P3_7) _____ RW RW RW RW RW RW RW — INT1/TRAIO select bit 0 : INT1/TRAIO pin (P1_7) _____ 1 : INT1/TRAIO pin (P1_5) TRAIO input filter select bits Set to 0 in pulse output mode. Nothing is assigned. If necessary, set to 0. When read, the content is 0. Figure 14.6 TRAIOC Register in Pulse Output Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 128 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.1.3 Event Counter Mode In event counter mode, external signal inputs to the INT1/TRAIO pin are counted (refer to Table 14.4 Event Counter Mode Specifications). Figure 14.7 shows TRAIOC Register in Event Counter Mode. Table 14.4 Event Counter Mode Specifications Specification External signal which is input to TRAIO pin (active edge selectable by a program) • Decrement • When the timer underflows, the contents of the reload register are reloaded and the count is continued. Divide ratio 1/(n+1)(m+1) n: setting value of TRAPRE register, m: setting value of TRA register Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register. Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register. • 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. • When timer RA underflows [timer RA interrupt]. Interrupt request generation timing INT1/TRAIO pin function TRAO pin function Read from timer Write to timer Count source input (INT1 interrupt input) Programmable I/O port or pulse output(1) The count value can be read by reading registers TRA and TRAPRE. • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter. • When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 Timer Write Control during Count Operation). • INT1 input polarity switch function The TEDGSEL bit in the TRAIOC register selects the active edge of the count source. • Count source input pin select function P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register. • Pulse output function Pulses of inverted polarity can be output from the TRAO pin each time the timer underflows (selectable by the TOENA bit in the TRAIOC register).(1) • Digital filter function Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital filter and select the sampling frequency. Item Count source Count operations Select functions NOTE: 1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR register is written to. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 129 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RA I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol TRAIOC Bit Symbol Address 0101h Bit Name TRAIO polarity sw itch bit TEDGSEL After Reset 00h Function 0 : Starts counting at rising edge of the TRAIO input or TRAIO starts output at “L” 1 : Starts counting at falling edge of the TRAIO input or TRAIO starts output at “H” Set to 0 in event counter mode. 0 : Port P3_0 1 : TRAO output _____ RW RW TOPCR TOENA TIOSEL TRAIO output control bit TRAO output enable bit _____ RW RW RW INT1/TRAIO select bit TRAIO input filter select bits (1) 0 : INT1/TRAIO pin (P1_7) _____ 1 : INT1/TRAIO pin (P1_5) b5 b4 TIPF0 TIPF1 — (b7-b6) 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling RW Nothing is assigned. If necessary, set to 0. When read, the content is 0. — NOTE: 1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined. Figure 14.7 TRAIOC Register in Event Counter Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 130 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.1.4 Pulse Width Measurement Mode In pulse width measurement mode, the pulse width of an external signal input to the INT1/TRAIO pin is measured (refer to Table 14.5 Pulse Width Measurement Mode Specifications). Figure 14.8 shows TRAIOC Register in Pulse Width Measurement Mode and Figure 14.9 shows an Operating Example of Pulse Width Measurement Mode. Table 14.5 Pulse Width Measurement Mode Specifications Specification f1, f2, f8, fOCO • Decrement • Continuously counts the selected signal only when measurement pulse is “H” level, or conversely only “L” level. • When the timer underflows, the contents of the reload register are reloaded and the count is continued. 1 (count starts) is written to the TSTART bit in the TRACR register. • 0 (count stops) is written to the TSTART bit in the TRACR register. • 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. • When timer RA underflows [timer RA interrupt]. • Rising or falling of the TRAIO input (end of measurement period) [timer RA interrupt] Programmable I/O port The count value can be read by reading registers TRA and TRAPRE. • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter. • When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 Timer Write Control during Count Operation). • Measurement level select The TEDGSEL bit in the TRAIOC register selects the “H” or “L” level period. • Measured pulse input pin select function P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register. • Digital filter function Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital filter and select the sampling frequency. Item Count sources Count operations Count start condition Count stop conditions Interrupt request generation timing INT1/TRAIO pin function Measured pulse input (INT1 interrupt input) TRAO pin function Read from timer Write to timer Select functions Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 131 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RA I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL Address 0101h Bit Name TRAIO polarity sw itch bit TRAIO output control bit TRAO output enable bit _____ After Reset 00h Function 0 : TRAIO input starts at “L” 1 : TRAIO input starts at “H” Set to 0 in pulse w idth measurement mode. RW RW RW RW _____ INT1/TRAIO select bit TRAIO input filter select bits (1) 0 : INT1/TRAIO pin (P1_7) _____ 1 : INT1/TRAIO pin (P1_5) b5 b4 RW TIPF0 TIPF1 — (b7-b6) 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling RW Nothing is assigned. If necessary, set to 0. When read, the content is 0. — NOTE: 1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined. Figure 14.8 TRAIOC Register in Pulse Width Measurement Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 132 of 332 R8C/2E Group, R8C/2F Group 14. Timers n = high level: the contents of TRA register, low level: the contents of TRAPRE register FFFFh n Content of counter (hex) Count start Underflow Count stop Count stop 0000h Set to 1 by a program TSTART bit in TRACR register 1 0 Count start Count start Period Measured pulse (TRAIO pin input) 1 0 Set to 0 when interrupt request is acknowledged, or set by a program IR bit in TRAIC register 1 0 Set to 0 by a program TEDGF bit in TRACR register 1 0 Set to 0 by a program TUNDF bit in TRACR register 1 0 The above applies under the following conditions. • “H” level width of measured pulse is measured. (TEDGSEL = 1) • TRAPRE = FFh Figure 14.9 Operating Example of Pulse Width Measurement Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 133 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.1.5 Pulse Period Measurement Mode In pulse period measurement mode, the pulse period of an external signal input to the INT1 /TRAIO pin is measured (refer to Table 14.6 Pulse Period Measurement Mode Specifications). Figure 14.10 shows TRAIOC Register in Pulse Period Measurement Mode and Figure 14.11 shows an Operating Example of Pulse Period Measurement Mode. Table 14.6 Pulse Period Measurement Mode Specifications Specification f1, f2, f8, fOCO • Decrement • After the active edge of the measured pulse is input, the contents of the readout buffer are retained at the first underflow of timer RA prescaler. Then timer RA reloads the contents in the reload register at the second underflow of timer RA prescaler and continues counting. 1 (count start) is written to the TSTART bit in the TRACR register. • 0 (count stop) is written to TSTART bit in the TRACR register. • 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. • When timer RA underflows or reloads [timer RA interrupt]. • Rising or falling of the TRAIO input (end of measurement period) [timer RA interrupt] Item Count sources Count operations Count start condition Count stop conditions Interrupt request generation timing INT1/TRAIO pin function Measured pulse input(1) (INT1 interrupt input) Programmable I/O port TRAO pin function Read from timer Write to timer The count value can be read by reading registers TRA and TRAPRE. • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter. • When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 Timer Write Control during Count Operation). • Measurement period select The TEDGSEL bit in the TRAIOC register selects the measurement period of the input pulse. • Measured pulse input pin select function P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register. • Digital filter function Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital filter and select the sampling frequency. Select functions NOTE: 1. Input a pulse with a period longer than twice the timer RA prescaler period. Input a pulse with a longer “H” and “L” width than the timer RA prescaler period. If a pulse with a shorter period is input to the TRAIO pin, the input may be ignored. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 134 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RA I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol TRAIOC Bit Symbol Address 0101h Bit Name TRAIO polarity sw itch bit TEDGSEL After Reset 00h Function 0 : Measures measurement pulse from one rising edge to next rising edge 1 : Measures measurement pulse from one falling edge to next falling edge Set to 0 in pulse period measurement mode. RW RW TOPCR TOENA TIOSEL TRAIO output control bit TRAO output enable bit _____ RW RW _____ INT1/TRAIO select bit TRAIO input filter select bits (1) 0 : INT1/TRAIO pin (P1_7) _____ 1 : INT1/TRAIO pin (P1_5) b5 b4 RW TIPF0 TIPF1 — (b7-b6) 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling RW Nothing is assigned. If necessary, set to 0. When read, the content is 0. — NOTE: 1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined. Figure 14.10 TRAIOC Register in Pulse Period Measurement Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 135 of 332 R8C/2E Group, R8C/2F Group 14. Timers Underflow signal of timer RA prescaler Set to 1 by a program TSTART bit in TRACR register 1 0 Starts counting Measurement pulse (TRAIO pin input) 1 0 TRA reloads TRA reloads Contents of TRA 0Fh 0Eh 0Dh 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 0Fh 0Eh 0Dh 01h 00h 0Fh 0Eh Underflow Retained Retained Contents of read-out buffer(1) 0Fh 0Eh 0Dh 0Bh 0Ah 09h 0Dh 01h 00h 0Fh 0Eh TRA read(3) (Note 2) (Note 2) TEDGF bit in TRACR register 1 0 Set to 0 by a program (Note 4) (Note 6) TUNDF bit in TRACR register 1 0 Set to 0 by a program (Note 5) IR bit in TRAIC register 1 0 Set to 0 when interrupt request is acknowledged, or set by a program Conditions: The period from one rising edge to the next rising edge of the measured pulse is measured (TEDGSEL = 0) with the default value of the TRA register as 0Fh. NOTES: 1. The contents of the read-out buffer can be read by reading the TRA register in pulse period measurement mode. 2. After an active edge of the measured pulse is input, the TEDGF bit in the TRACR register is set to 1 (active edge found) when the timer RA prescaler underflows for the second time. 3. The TRA register should be read before the next active edge is input after the TEDGF bit is set to 1 (active edge found). The contents in the read-out buffer are retained until the TRA register is read. If the TRA register is not read before the next active edge is input, the measured result of the previous period is retained. 4. To set to 0 by a program, use a MOV instruction to write 0 to the TEDGF bit in the TRACR register. At the same time, write 1 to the TUNDF bit in the TRACR register. 5. To set to 0 by a program, use a MOV instruction to write 0 to the TUNDF bit. At the same time, write 1 to the TEDGF bit. 6. Bits TUNDF and TEDGF are both set to 1 if timer RA underflows and reloads on an active edge simultaneously. Figure 14.11 Operating Example of Pulse Period Measurement Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 136 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.1.6 Notes on Timer RA • Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the count starts. • Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by the MCU. Consequently, the timer value may be updated during the period when these two registers are being read. • In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by writing 0 to these bits by a program. However, these bits remain unchanged if 1 is written. When using the READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0 although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or TUNDF bit which is not supposed to be set to 0 with the MOV instruction. • When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts. • The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts. • When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler immediately after the count starts, then set the TEDGF bit to 0. • The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1 (count starts) while the count is stopped. During this time, do not access registers associated with timer RA(1) other than the TCSTF bit. Timer RA starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count). The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RA(1) other than the TCSTF bit. NOTE: 1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA. • When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the count source clock for each write interval. • When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 137 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.2 Timer RB Timer RB is an 8-bit timer with an 8-bit prescaler. The prescaler and timer each consist of a reload register and counter (refer to Tables 1 4.7 to 14.10 the Specifications of Each Mode). Timer RB has timer RB primary and timer RB secondary as reload registers. The count source for timer RB is the operating clock that regulates the timing of timer operations such as counting and reloading. Figure 14.12 shows a Block Diagram of Timer RB. Figures 14.13 and 14.15 show the registers associated with timer RB. Timer RB has four operation modes listed as follows: • Timer mode: • Programmable waveform generation mode: • Programmable one-shot generation mode: • Programmable wait one-shot generation mode: The timer counts an internal count source (peripheral function clock or timer RA underflows). The timer outputs pulses of a given width successively. The timer outputs a one-shot pulse. The timer outputs a delayed one-shot pulse. Reload register TCK1 to TCK0 bits f1 f8 Timer RA underflow = 00b = 01b = 10b = 11b Data bus TRBSC register Reload register TRBPR register Reload register Timer RB interrupt TCKCUT bit Counter TRBPRE register (prescaler) TSTRAT bit TOSSTF bit INT0 interrupt Input polarity selected to be one edge or both edges Counter (timer RB) (Timer) TMOD1 to TMOD0 bits = 10b or 11b f2 INT0 pin Digital filter Polarity select INOSEG bit TOPL = 1 Q Q INT0PL bit TMOD1 to TMOD0 bits = 01b, 10b, 11b TOCNT = 0 TRBO pin P3_1 bit in P3 register TOCNT = 1 TSTART, TCSTF: Bits in TRBCR register TOSSTF: Bit in TRBOCR register TOPL, TOCNT, INOSTG, INOSEG: Bits in TRBIOC register TMOD1 to TMOD0, TCK1 to TCK0, TCKCUT: Bits in TRBMR register INT0EN bit INOSTG bit Toggle flip-flop CLR CK TOPL = 0 TCSTF bit TMOD1 to TMOD0 bits = 01b, 10b, 11b Figure 14.12 Block Diagram of Timer RB Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 138 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RB Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRBCR Bit Symbol TSTART TCSTF TSTOP — (b7-b3) Address 0108h Bit Name Timer RB count start bit(1) After Reset 00h Function 0 : Count stops 1 : Count starts RW RW RO RW — Timer RB count status flag(1) 0 : Count stops 1 : During count(3) Timer RB count forcible stop When this bit is set to 1, the count is forcibly bit(1, 2) stopped. When read, its content is 0. Nothing is assigned. If necessary, set to 0. When read, the content is 0. NOTES: 1. Refer to 14.2.5 Notes on Tim er RB f or precautions regarding bits TSTART, TCSTF and TSTOP. 2. When the TSTOP bit is set to 1, registers TRBPRE, TRBSC, TRBPR, and bits TSTART and TCSTF, and the TOSSTF bit in the TRBOCR register are set to values after a reset. 3. Indicates that count operation is in progress in timer mode or programmable w aveform mode. In programmable oneshot generation mode or programmable w ait one-shot generation mode, indicates that a one-shot pulse trigger has been acknow ledged. Timer RB One-Shot Control Register(2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRBOCR Bit Symbol TOSST Address 0109h Bit Name Timer RB one-shot start bit Timer RB one-shot stop bit After Reset 00h Function When this bit is set to 1, one-shot trigger generated. When read, its content is 0. When this bit is set to 1, counting of one-shot pulses (including programmable w ait one-shot pulses) stops. When read, its content is 0. 0 : One-shot stopped 1 : One-shot operating (Including w ait period) RW RW TOSSP Timer RB one-shot status flag(1) RW TOSSTF — (b7-b3) RO — Nothing is assigned. If necessary, set to 0. When read, the content is 0. NOTES: 1. When 1 is set to the TSTOP bit in the TRBCR register, the TOSSTF bit is set to 0. 2. This register is enabled w hen bits TMOD1 to TMOD0 in the TRBMR register is set to 10b (programmable one-shot generation mode) or 11b (programmable w ait one-shot generation mode). Figure 14.13 Registers TRBCR and TRBOCR Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 139 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RB I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRBIOC Bit Symbol TOPL TOCNT INOSTG INOSEG — (b7-b4) Address After Reset 010Ah 00h Bit Name Function Timer RB output level select Function varies depending on operating mode. bit Timer RB output sw itch bit One-shot trigger control bit One-shot trigger polarity select bit Nothing is assigned. If necessary, set to 0. When read, the content is 0. RW RW RW RW RW — Timer RB Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRBMR Bit Symbol TMOD0 Address 010Bh Bit Name Timer RB operating mode select bits (1) After Reset 00h Function b1 b0 RW RW TMOD1 — (b2) TWRC 0 0 : Timer mode 0 1 : Programmable w aveform generation mode 1 0 : Programmable one-shot generation mode 1 1 : Programmable w ait one-shot generation mode RW Nothing is assigned. If necessary, set to 0. When read, the content is 0. Timer RB w rite control bit(2) Timer RB count source select bits (1) 0 : Write to reload register and counter 1 : Write to reload register only b5 b4 — RW TCK0 TCK1 — (b6) TCKCUT 0 0 : f1 0 1 : f8 1 0 : Timer RA underflow 1 1 : f2 RW RW Nothing is assigned. If necessary, set to 0. When read, the content is 0. Timer RB count source cutoff bit(1) 0 : Provides count source 1 : Cuts off count source — RW NOTES: 1. Change bits TMOD1 and TMOD0; TCK1 and TCK0; and TCKCUT w hen both the TSTART and TCSTF bits in the TRBCR register set to 0 (count stops). 2. The TWRC bit can be set to either 0 or 1 in timer mode. In programmable w aveform generation mode, programmable one-shot generation mode, or programmable w ait one-shot generation mode, the TWRC bit must be set to 1 (w rite to reload register only). Figure 14.14 Registers TRBIOC and TRBMR Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 140 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RB Prescaler Register(1) b7 b0 Symbol TRBPRE Mode Timer mode Programmable w aveform generation mode Programmable one-shot generation mode Programmable w ait one-shot generation mode Address 010Ch Function Counts an internal count source or timer RA underflow s After Reset FFh Setting Range 00h to FFh 00h to FFh 00h to FFh 00h to FFh RW RW RW RW RW NOTE: 1. When the TSTOP bit in the TRBCR register is set to 1, the TRBPRE register is set to FFh. Timer RB Secondary Register(3, 4) b7 b0 Symbol TRBSC Mode Timer mode Programmable w aveform generation mode Programmable one-shot generation mode Disabled Address 010Dh Function After Reset FFh Setting Range 00h to FFh 00h to FFh 00h to FFh 00h to FFh RW — WO(2) — WO(2) Counts timer RB prescaler underflow s (1) Disabled Programmable w ait one-shot Counts timer RB prescaler underflow s generation mode (one-shot w idth is counted) NOTES: 1. The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted. 2. The count value can be read out by reading the TRBPR register even w hen the secondary period is being counted. 3. When the TSTOP bit in the TRBCR register is set to 1, the TRBSC register is set to FFh. 4. To w rite to the TRBSC register, perform the follow ing steps. (1) Write the value to the TRBSC register. (2) Write the value to the TRBPR register. (If the value does not change, w rite the same value second time.) Timer RB Primary Register(2) b7 b0 Symbol TRBPR Mode Timer mode Programmable w aveform generation mode Programmable one-shot generation mode Address 010Eh Function Counts timer RB prescaler underflow s Counts timer RB prescaler underflow s (1) Counts timer RB prescaler underflow s (one-shot w idth is counted) After Reset FFh Setting Range 00h to FFh 00h to FFh 00h to FFh 00h to FFh RW RW RW RW RW Programmable w ait one-shot Counts timer RB prescaler underflow s generation mode (w ait period w idth is counted) NOTES: 1. The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted. 2. When the TSTOP bit in the TRBCR register is set to 1, the TRBPR register is set to FFh. Figure 14.15 Registers TRBPRE, TRBSC, and TRBPR Page 141 of 332 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 R8C/2E Group, R8C/2F Group 14. Timers 14.2.1 Timer Mode In timer mode, a count source which is internally generated or timer RA underflows are counted (refer to Table 14.7 Timer Mode Specifications). Registers TRBOCR and TRBSC are not used in timer mode. Figure 14.16 shows TRBIOC Register in Timer Mode. Table 14.7 Timer Mode Specifications Specification f1, f2, f8, timer RA underflow • Decrement • When the timer underflows, it reloads the reload register contents before the count continues (when timer RB underflows, the contents of timer RB primary reload register is reloaded). 1/(n+1)(m+1) n: setting value in TRBPRE register, m: setting value in TRBPR register 1 (count starts) is written to the TSTART bit in the TRBCR register. • 0 (count stops) is written to the TSTART bit in the TRBCR register. • 1 (count forcibly stop) is written to the TSTOP bit in the TRBCR register. When timer RB underflows [timer RB interrupt]. Programmable I/O port Programmable I/O port or INT0 interrupt input The count value can be read out by reading registers TRBPR and TRBPRE. • When registers TRBPRE and TRBPR are written while the count is stopped, values are written to both the reload register and counter. • When registers TRBPRE and TRBPR are written to while count operation is in progress: If the TWRC bit in the TRBMR register is set to 0, the value is written to both the reload register and the counter. If the TWRC bit is set to 1, the value is written to the reload register only. (Refer to 14.2.1.1 Timer Write Control during Count Operation.) Item Count sources Count operations Divide ratio Count start condition Count stop conditions Interrupt request generation timing TRBO pin function INT0 pin function Read from timer Write to timer Timer RB I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 0000 Symbol TRBIOC Bit Symbol TOPL TOCNT INOSTG INOSEG — (b7-b4) Address After Reset 010Ah 00h Bit Name Function Timer RB output level select Set to 0 in timer mode. bit Timer RB output sw itch bit One-shot trigger control bit One-shot trigger polarity select bit Nothing is assigned. If necessary, set to 0. When read, the content is 0. RW RW RW RW RW — Figure 14.16 TRBIOC Register in Timer Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 142 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.2.1.1 Timer Write Control during Count Operation Timer RB has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each consist of a reload register and a counter. In timer mode, the TWRC bit in the TRBMR register can be used to select whether writing to the prescaler or timer during count operation is performed to both the reload register and counter or only to the reload register. However, values are transferred from the reload register to the counter of the prescaler in synchronization with the count source. In addition, values are transferred from the reload register to the counter of the timer in synchronization with prescaler underflows. Therefore, even if the TWRC bit is set for writing to both the reload register and counter, the counter value is not updated immediately after the WRITE instruction is executed. In addition, if the TWRC bit is set for writing to the reload register only, the synchronization of the writing will be shifted if the prescaler value changes. Figure 14.17 shows an Operating Example of Timer RB when Counter Value is Rewritten during Count Operation. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 143 of 332 R8C/2E Group, R8C/2F Group 14. Timers When the TWRC bit is set to 0 (write to reload register and counter) Set 01h to the TRBPRE register and 25h to the TRBPR register by a program. Count source After writing, the reload register is written with the first count source. Reloads register of timer RB prescaler Previous value Reload with the second count source Reload on underflow New value (01h) Counter of timer RB prescaler 06h 05h 04h 01h 00h 01h 00h 01h 00h 01h 00h After writing, the reload register is written on the first underflow. Reloads register of timer RB Previous value New value (25h) Reload on the second underflow Counter of timer RB 03h 02h 25h 24h IR bit in TRBIC register 0 The IR bit remains unchanged until underflow is generated by a new value. When the TWRC bit is set to 1 (write to reload register only) Set 01h to the TRBPRE register and 25h to the TRBPR register by a program. Count source After writing, the reload register is written with the first count source. Reloads register of timer RB prescaler Previous value New value (01h) Reload on underflow Counter of timer RB prescaler 06h 05h 04h 03h 02h 01h 00h 01h 00h 01h 00h 01h 00h 01h After writing, the reload register is written on the first underflow. Reloads register of timer RB Previous value New value (25h) Reload on underflow Counter of timer RB 03h 02h 01h 00h 25h IR bit in TRBIC register 0 Only the prescaler values are updated, extending the duration until timer RB underflow. The above applies under the following conditions. Both bits TSTART and TCSTF in the TRBCR register are set to 1 (During count). Figure 14.17 Operating Example of Timer RB when Counter Value is Rewritten during Count Operation Page 144 of 332 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 R8C/2E Group, R8C/2F Group 14. Timers 14.2.2 Programmable Waveform Generation Mode In programmable waveform generation mode, the signal output from the TRBO pin is inverted each time the counter underflows, while the values in registers TRBPR and TRBSC are counted alternately (refer to Table 14.8 Programmable Waveform Generation Mode Specifications). Counting starts by counting the setting value in the TRBPR register. The TRBOCR register is unused in this mode. Figure 14.18 shows TRBIOC Register in Programmable Waveform Generation Mode. Figure 14.19 shows an Operating Example of Timer RB in Programmable Waveform Generation Mode. Table 14.8 Programmable Waveform Generation Mode Specifications Specification f1, f2, f8, timer RA underflow • Decrement • When the timer underflows, it reloads the contents of the primary reload and secondary reload registers alternately before the count continues. Width and period of Primary period: (n+1)(m+1)/fi output waveform Secondary period: (n+1)(p+1)/fi Period: (n+1){(m+1)+(p+1)}/fi fi: Count source frequency n: Value set in TRBPRE register m: Value set in TRBPR register p: Value set in TRBSC register Count start condition 1 (count start) is written to the TSTART bit in the TRBCR register. Count stop conditions • 0 (count stop) is written to the TSTART bit in the TRBCR register. • 1 (count forcibly stop) is written to the TSTOP bit in the TRBCR register. Interrupt request In half a cycle of the count source, after timer RB underflows during the generation timing secondary period (at the same time as the TRBO output change) [timer RB interrupt] TRBO pin function Programmable output port or pulse output INT0 pin function Read from timer Write to timer Programmable I/O port or INT0 interrupt input The count value can be read out by reading registers TRBPR and TRBPRE(1). • When registers TRBPRE, TRBSC, and TRBPR are written while the count is stopped, values are written to both the reload register and counter. • When registers TRBPRE, TRBSC, and TRBPR are written to during count operation, values are written to the reload registers only.(2) • Output level select function The TOPL bit in the TRBIOC register selects the output level during primary and secondary periods. • TRBO pin output switch function Timer RB pulse output or P3_1 latch output is selected by the TOCNT bit in the TRBIOC register.(3) Item Count sources Count operations Select functions NOTES: 1. Even when counting the secondary period, the TRBPR register may be read. 2. The set values are reflected in the waveform output beginning with the following primary period after writing to the TRBPR register. 3. The value written to the TOCNT bit is enabled by the following. • When counting starts. • When a timer RB interrupt request is generated. The contents after the TOCNT bit is changed are reflected from the output of the following primary period. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 145 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RB I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol TRBIOC Bit Symbol TOPL Address 010Ah Bit Name Timer RB output level select 0 : Outputs bit Outputs Outputs 1 : Outputs Outputs Outputs Timer RB output sw itch bit One-shot trigger control bit One-shot trigger polarity select bit After Reset 00h Function “H” for primary period “L” for secondary period “L” w hen the timer is stopped “L” for primary period “H” for secondary period “H” w hen the timer is stopped RW RW TOCNT INOSTG INOSEG — (b7-b4) 0 : Outputs timer RB w aveform 1 : Outputs value in P3_1 (P1_3) port register Set to 0 in programmable w aveform generation mode. RW RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. Figure 14.18 TRBIOC Register in Programmable Waveform Generation Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 146 of 332 R8C/2E Group, R8C/2F Group 14. Timers Set to 1 by a program TSTART bit in TRBCR register 1 0 Count source Timer RB prescaler underflow signal Timer RB secondary reloads Timer RB primary reloads Counter of timer RB 01h 00h 02h 01h 00h 01h 00h 02h Set to 0 when interrupt request is acknowledged, or set by a program. IR bit in TRBIC register 1 0 Set to 0 by a program TOPL bit in TRBIO register 1 0 Waveform output starts Waveform output inverted Waveform output starts 1 TRBO pin output 0 Primary period Secondary period Primary period Initial output is the same level as during secondary period. The above applies under the following conditions. TRBPRE = 01h, TRBPR = 01h, TRBSC = 02h TRBIOC register TOCNT = 0 (timer RB waveform is output from the TRBO pin) Figure 14.19 Operating Example of Timer RB in Programmable Waveform Generation Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 147 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.2.3 Programmable One-shot Generation Mode In programmable one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (refer to Table 14.9 Programmable One-Shot Generation Mode Specifications). When a trigger is generated, the timer starts operating from the point only once for a given period equal to the set value in the TRBPR register. The TRBSC register is not used in this mode. Figure 14.20 shows TRBIOC Register in Programmable One-Shot Generation Mode. Figure 14.21 shows an Operating Example of Programmable One-Shot Generation Mode. Table 14.9 Programmable One-Shot Generation Mode Specifications Specification f1, f2, f8, timer RA underflow • Decrement the setting value in the TRBPR register • When the timer underflows, it reloads the contents of the reload register before the count completes and the TOSSTF bit is set to 0 (one-shot stops). • When the count stops, the timer reloads the contents of the reload register before it stops. One-shot pulse (n+1)(m+1)/fi output time fi: Count source frequency, n: Setting value in TRBPRE register, m: Setting value in TRBPR register(2) Count start conditions • The TSTART bit in the TRBCR register is set to 1 (count starts) and the next trigger is generated • Set the TOSST bit in the TRBOCR register to 1 (one-shot starts) • Input trigger to the INT0 pin Count stop conditions • When reloading completes after timer RB underflows during primary period • When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops) • When the TSTART bit in the TRBCR register is set to 0 (stops counting) • When the TSTOP bit in the TRBCR register is set to 1 (forcibly stops counting) Interrupt request In half a cycle of the count source, after the timer underflows (at the same time as generation timing the TRBO output ends) [timer RB interrupt] TRBP pin function Pulse output INT0 pin functions • When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger disabled): programmable I/O port or INT0 interrupt input • When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger enabled): external trigger (INT0 interrupt input) The count value can be read out by reading registers TRBPR and TRBPRE. • When registers TRBPRE and TRBPR are written while the count is stopped, values are written to both the reload register and counter. • When registers TRBPRE and TRBPR are written during the count, values are written to the reload register only (the data is transferred to the counter at the following reload)(1). • Output level select function The TOPL bit in the TRBIOC register selects the output level of the one-shot pulse waveform. • One-shot trigger select function Refer to 14.2.3.1 One-Shot Trigger Selection. Item Count sources Count operations Read from timer Write to timer Select functions NOTES: 1. The set value is reflected at the following one-shot pulse after writing to the TRBPR register. 2. Do not set both the TRBPRE and TRBPR registers to 00h. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 148 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RB I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol TRBIOC Bit Symbol TOPL Address 010Ah Bit Name Timer RB Output Level Select Bit 0 : Outputs Outputs 1 : Outputs Outputs After Reset 00h Function one-shot pulse “H” “L” w hen the timer is stopped one-shot pulse “L” “H” w hen the timer is stopped RW RW TOCNT INOSTG INOSEG — (b7-b4) Timer RB Output Sw itch Bit One-Shot Trigger Control Bit(1) One-Shot Trigger Polarity Select Bit(1) Set to 0 in programmable one-shot generation mode. _____ RW RW RW — 0 : INT0 pin one-shot trigger disabled _____ 1 : INT0 pin one-shot trigger enabled 0 : Falling edge trigger 1 : Rising edge trigger Nothing is assigned. If necessary, set to 0. When read, its content is 0. NOTE: 1. Refer to 14.2.3.1 One-Shot Trigger Selection. Figure 14.20 TRBIOC Register in Programmable One-Shot Generation Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 149 of 332 R8C/2E Group, R8C/2F Group 14. Timers Set to 1 by a program TSTART bit in TRBCR register 1 0 Set to 1 by a program Set to 0 when counting ends Set to 1 by INT0 pin input trigger TOSSTF bit in TRBOCR register 1 0 INT0 pin input Count source Timer RB prescaler underflow signal Count starts Timer RB primary reloads Count starts Timer RB primary reloads Counter of timer RB 01h 00h 01h 00h 01h Set to 0 when interrupt request is acknowledged, or set by a program IR bit in TRBIC register 1 0 Set to 0 by a program TOPL bit in TRBIOC register 1 0 Waveform output starts Waveform output ends Waveform output starts Waveform output ends 1 TRBIO pin output 0 The above applies under the following conditions. TRBPRE = 01h, TRBPR = 01h TRBIOC register TOPL = 0, TOCNT = 0 INOSTG = 1 (INT0 one-shot trigger enabled) INOSEG = 1 (edge trigger at rising edge) Figure 14.21 Operating Example of Programmable One-Shot Generation Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 150 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.2.3.1 One-Shot Trigger Selection In programmable one-shot generation mode and programmable wait one-shot generation mode, operation starts when a one-shot trigger is generated while the TCSTF bit in the TRBCR register is set to 1 (count starts). A one-shot trigger can be generated by either of the following causes: • 1 is written to the TOSST bit in the TRBOCR register by a program. • Trigger input from the INT0 pin. When a one-shot trigger occurs, the TOSSTF bit in the TRBOCR register is set to 1 (one-shot operation in progress) after one or two cycles of the count source have elapsed. Then, in programmable one-shot generation mode, count operation begins and one-shot waveform output starts. (In programmable wait one-shot generation mode, count operation starts for the wait period.) If a one-shot trigger occurs while the TOSSTF bit is set to 1, no retriggering occurs. To use trigger input from the INT0 pin, input the trigger after making the following settings: • Set the PD4_5 bit in the PD4 register to 0 (input port). • Select the INT0 digital filter with bits INT0F1 and INT0F0 in the INTF register. • Select both edges or one edge with the INT0PL bit in INTEN register. If one edge is selected, further select falling or rising edge with the INOSEG bit in TRBIOC register. • Set the INT0EN bit in the INTEN register to 0 (enabled). • After completing the above, set the INOSTG bit in the TRBIOC register to 1 (INT pin one-shot trigger enabled). Note the following points with regard to generating interrupt requests by trigger input from the INT0 pin. • Processing to handle the interrupts is required. Refer to 12. Interrupts, for details. • If one edge is selected, use the POL bit in the INT0IC register to select falling or rising edge. (The INOSEG bit in the TRBIOC register does not affect INT0 interrupts). • If a one-shot trigger occurs while the TOSSTF bit is set to 1, timer RB operation is not affected, but the value of the IR bit in the INT0IC register changes. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 151 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.2.4 Programmable Wait One-Shot Generation Mode In programmable wait one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (refer to Table 14.10 Programmable Wait One-Shot Generation Mode Specifications). When a trigger is generated from that point, the timer outputs a pulse only once for a given length of time equal to the setting value in the TRBSC register after waiting for a given length of time equal to the setting value in the TRBPR register. Figure 14.22 shows TRBIOC Register in Programmable Wait One-Shot Generation Mode. Figure 14.23 shows an Operating Example of Programmable Wait One-Shot Generation Mode. Table 14.10 Programmable Wait One-Shot Generation Mode Specifications Specification f1, f2, f8, timer RA underflow • Decrement the timer RB primary setting value. • When a count of the timer RB primary underflows, the timer reloads the contents of timer RB secondary before the count continues. • When a count of the timer RB secondary underflows, the timer reloads the contents of timer RB primary before the count completes and the TOSSTF bit is set to 0 (one-shot stops). • When the count stops, the timer reloads the contents of the reload register before it stops. (n+1)(m+1)/fi fi: Count source frequency n: Value set in the TRBPRE register, m Value set in the TRBPR register(2) (n+1)(p+1)/fi fi: Count source frequency n: Value set in the TRBPRE register, p: Value set in the TRBSC register • The TSTART bit in the TRBCR register is set to 1 (count starts) and the next trigger is generated. • Set the TOSST bit in the TRBOCR register to 1 (one-shot starts). • Input trigger to the INT0 pin • When reloading completes after timer RB underflows during secondary period. • When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops). • When the TSTART bit in the TRBCR register is set to 0 (starts counting). • When the TSTOP bit in the TRBCR register is set to 1 (forcibly stops counting). In half a cycle of the count source after timer RB underflows during secondary period (complete at the same time as waveform output from the TRBO pin) [timer RB interrupt]. Pulse output • When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger disabled): programmable I/O port or INT0 interrupt input • When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger enabled): external trigger (INT0 interrupt input) The count value can be read out by reading registers TRBPR and TRBPRE. • When registers TRBPRE, TRBSC, and TRBPR are written while the count stops, values are written to both the reload register and counter. • When registers TRBPRE, TRBSC, and TRBPR are written to during count operation, values are written to the reload registers only.(1) • Output level select function The TOPL bit in the TRBIOC register selects the output level of the one-shot pulse waveform. • One-shot trigger select function Refer to 14.2.3.1 One-Shot Trigger Selection. Item Count sources Count operations Wait time One-shot pulse output time Count start conditions Count stop conditions Interrupt request generation timing TRBO pin function INT0 pin functions Read from timer Write to timer Select functions NOTES: 1. The set value is reflected at the following one-shot pulse after writing to registers TRBSC and TRBPR. 2. Do not set both the TRBPRE and TRBPR registers to 00h. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 152 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RB I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol TRBIOC Bit Symbol TOPL Address 010Ah Bit Name Timer RB output level select 0 : Outputs bit Outputs w ait. 1 : Outputs Outputs w ait. Timer RB output sw itch bit After Reset 00h Function one-shot pulse “H”. “L” w hen the timer stops or during one-shot pulse “L”. “H” w hen the timer stops or during RW RW TOCNT INOSTG INOSEG — (b7-b4) Set to 0 in programmable w ait one-shot generation mode. _____ RW RW RW — One-shot trigger control bit(1) 0 : INT0 pin one-shot trigger disabled _____ 1 : INT0 pin one-shot trigger enabled 0 : Falling edge trigger One-shot trigger polarity 1 : Rising edge trigger select bit(1) Nothing is assigned. If necessary, set to 0. When read, the content is 0. NOTE: 1. Refer to 14.2.3.1 One-Shot Trigger Selection. Figure 14.22 TRBIOC Register in Programmable Wait One-Shot Generation Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 153 of 332 R8C/2E Group, R8C/2F Group 14. Timers Set to 1 by a program TSTART bit in TRBCR register 1 0 Set to 1 by setting 1 to TOSST bit in TRBOCR register, or INT0 pin input trigger. Set to 0 when counting ends TOSSTF bit in TRBOCR register 1 0 INT0 pin input Count source Timer RB prescaler underflow signal Count starts Timer RB secondary reloads Timer RB primary reloads Counter of timer RB 01h 00h 04h 03h 02h 01h 00h 01h Set to 0 when interrupt request is acknowledged, or set by a program. IR bit in TRBIC register 1 0 Set to 0 by a program TOPL bit in TRBIOC register 1 0 Wait starts Waveform output starts Waveform output ends 1 TRBIO pin output 0 Wait (primary period) One-shot pulse (secondary period) The above applies under the following conditions. TRBPRE = 01h, TRBPR = 01h, TRBSC = 04h INOSTG = 1 (INT0 one-shot trigger enabled) INOSEG = 1 (edge trigger at rising edge) Figure 14.23 Operating Example of Programmable Wait One-Shot Generation Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 154 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.2.5 Notes on Timer RB • Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the count starts. • Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the MCU. Consequently, the timer value may be updated during the period when these two registers are being read. • In programmable one-shot generation mode and programmable wait one-shot generation mode, when setting the TSTART bit in the TRBCR register to 0, 0 (stops counting) or setting the TOSSP bit in the TRBOCR register to 1 (stops one-shot), the timer reloads the value of reload register and stops. Therefore, in programmable one-shot generation mode and programmable wait one-shot generation mode, read the timer count value before the timer stops. • The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to 1 (count starts) while the count is stopped. During this time, do not access registers associated with timer RB(1)other than the TCSTF bit. Timer RB starts counting at the first valid edge of the count source after the TCSTF bit is set to 1 (during count). The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RB(1) other than the TCSTF bit. NOTE: 1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and TRBPR. • If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately. • If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes after one or two cycles of the count source have elapsed. If the TOSSP bit is written to 1 during the period between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit may be set to either 0 or 1. 14.2.5.1 Timer mode The following workaround should be performed in timer mode. To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: • When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 155 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.2.5.2 Programmable waveform generation mode The following three workarounds should be performed in programmable waveform generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: • When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval. (2) To change registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), synchronize the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period A shown in Figures 14.24 and 14.25. The following shows the detailed workaround examples. • Workaround example (a): As shown in Figure 14.24, write to registers TRBSC and TRBPR in the timer RB interrupt routine. These write operations must be completed by the beginning of period A. Period A Count source/ prescaler underflow signal TRBO pin output Primary period Secondary period IR bit in TRBIC register (a) Interrupt request is acknowledged (b) Ensure sufficient time Interrupt request is generated Instruction in Interrupt sequence interrupt routine Set the secondary and then the primary register immediately (a) Period between interrupt request generation and the completion of execution of an instruction. The length of time varies depending on the instruction being executed. The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as the divisor). (b) 20 cycles. 21 cycles for address match and single-step interrupts. Figure 14.24 Workaround Example (a) When Timer RB interrupt is Used Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 156 of 332 R8C/2E Group, R8C/2F Group 14. Timers • Workaround example (b): As shown in Figure 14.25 detect the start of the primary period by the TRBO pin output level and write to registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A. If the port register’s bit value is read after the port direction register’s bit corresponding to the TRBO pin is set to 0 (input mode), the read value indicates the TRBO pin output value. Period A Count source/ prescaler underflow signal TRBO pin output Read value of the port register’s bit corresponding to the TRBO pin (when the bit in the port direction register is set to 0) Primary period Secondary period (i) (ii) (iii) Ensure sufficient time The TRBO output inversion is detected at the end of the secondary period. Upon detecting (i), set the secondary and then the primary register immediately. Figure 14.25 Workaround Example (b) When TRBO Pin Output Value is Read (3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case, registers TRBPRE and TRBPR are initialized and their values are set to the values after reset. 14.2.5.3 Programmable one-shot generation mode The following two workarounds should be performed in programmable one-shot generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: • When the TRBPRE register is written continuously during count operation (TCSTF bit is set to 1), allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval. (2) Do not set both the TRBPRE and TRBPR registers to 00h. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 157 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.2.5.4 Programmable wait one-shot generation mode The following three workarounds should be performed in programmable wait one-shot generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: • When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval. (2) Do not set both the TRBPRE and TRBPR registers to 00h. (3) Set registers TRBSC and TRBPR using the following procedure. (a) To use “INT0 pin one-shot trigger enabled” as the count start condition Set the TRBSC register and then the TRBPR register. At this time, after writing to the TRBPR register, allow an interval of 0.5 or more cycles of the count source before trigger input from the INT0 pin. (b) To use “writing 1 to TOSST bit” as the start condition Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the TRBPR register, allow an interval of 0.5 or more cycles of the count source before writing to the TOSST bit. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 158 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.3 14.3.1 Timer RC Overview Timer RC is a 16-bit timer with four I/O pins. Timer RC uses either f1 or fOCO40M as its operation clock. Table 14.11 lists the Timer RC Operation Clock. Table 14.11 Timer RC Operation Clock Condition Timer RC Operation Clock Count source is f1, f2, f4, f8, f32, or TRCCLK input (bits TCK2 to TCK0 in f1 TRCCR1 register are set to a value from 000b to 101b) Count source is fOCO40M (bits TCK2 to TCK0 in TRCCR1 register are set fOCO40M to 110b) Table 14.12 lists the Timer RC I/O Pins, and Figure 14.26 shows a Block Diagram of Timer RC. Timer RC has three modes. • Timer mode - Input capture function The counter value is captured to a register, using an external signal as the trigger. - Output compare function Matches between the counter and register values are detected. (Pin output state changes when a match is detected.) The following two modes use the output compare function. • PWM mode Pulses of a given width are output continuously. • PWM2 mode A one-shot waveform or PWM waveform is output following the trigger after the wait time has elapsed. Input capture function, output compare function, and PWM mode settings may be specified independently for each pin. In PWM2 mode waveforms are output based on a combination of the counter or the register. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 159 of 332 R8C/2E Group, R8C/2F Group 14. Timers f1, f2, f4, f8, f32, fOCO40M TRCMR register TRCCR1 register TRCIER register TRCSR register TRCIOR0 register TRCIOR1 register Data bus INT0 Count source select circuit TRCCLK TRCIOA/TRCTRG TRCIOB TRC register TRCGRA register TRCGRB register TRCGRC register TRCGRD register TRCCR2 register Timer RC control circuit TRCIOC TRCIOD TRCDF register TRCOER register Timer RC interrupt request Figure 14.26 Block Diagram of Timer RC Table 14.12 Timer RC I/O Pins I/O I/O Function Function differs according to the mode. Refer to descriptions of individual modes for details Pin Name TRCIOA(P1_1) TRCIOB(P1_2) TRCIOC(P5_3 or P3_4)(1) TRCIOD(P5_4 or P3_5)(1) TRCCLK(P3_3) TRCTRG(P1_1) Input Input External clock input PWM2 mode external trigger input NOTE: 1. The pins used for TRCIOC and TRCIOD are selectable. Refer to the description of the bits TRCIOCSEL and TRCIODSEL in the PINSR3 register in Figure 7.9 Registers PINSR2 and PINSR3 for details. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 160 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.3.2 Registers Associated with Timer RC Table 14.13 lists the Registers Associated with Timer RC. Figures 14.27 to 14.36 show details of the registers associated with timer RC. Table 14.13 Registers Associated with Timer RC Mode Timer Input Output PWM Capture Compare Function Function Valid Valid Valid Valid Valid Valid Address Symbol PWM2 Valid Valid Related Information 0120h 0121h TRCMR TRCCR1 0122h 0123h 0124h TRCIER TRCSR Valid Valid Valid Valid Valid Valid Valid − Valid Valid − TRCIOR0 Valid 0125h TRCIOR1 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh 0130h 0131h 0132h − : Invalid TRC TRCGRA TRCGRB TRCGRC TRCGRD TRCCR2 TRCDF TRCOER Valid Valid Valid Valid Valid Valid Valid Valid Timer RC mode register Figure 14.27 TRCMR Register Timer RC control register 1 Figure 14.28 TRCCR1 Register Figure 14.49 TRCCR1 Register in Output Compare Function Figure 14.52 TRCCR1 Register in PWM Mode Figure 14.56 TRCCR1 Register in PWM2 Mode Timer RC interrupt enable register Figure 14.29 TRCIER Register Timer RC status register Figure 14.30 TRCSR Register Timer RC I/O control register 0, timer RC I/O control register 1 Figure 14.36 Registers TRCIOR0 and TRCIOR1 Figure 14.43 TRCIOR0 Register in Input Capture Function Figure 14.44 TRCIOR1 Register in Input Capture Function Figure 14.47 TRCIOR0 Register in Output Compare Function Figure 14.48 TRCIOR1 Register in Output Compare Function Timer RC counter Figure 14.31 TRC Register Timer RC general registers A, B, C, and D Figure 14.32 Registers TRCGRA, TRCGRB, TRCGRC, and TRCGRD − − − − − Valid Valid Valid Valid − Valid Valid Timer RC control register 2 Figure 14.33 TRCCR2 Register Timer RC digital filter function select register Figure 14.34 TRCDF Register Timer RC output mask enable register Figure 14.35 TRCOER Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 161 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RC Mode Register(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRCMR Bit Symbol PWMB PWMC PWMD PWM2 BFC BFD — (b6) TSTART Address 0120h Bit Name PWM mode of TRCIOB select bit(2) PWM mode of TRCIOC select bit(2) PWM mode of TRCIOD select bit(2) PWM2 mode select bit TRCGRC register function select bit(3) TRCGRD register function select bit After Reset 01001000b Function 0 : Timer mode 1 : PWM mode 0 : Timer mode 1 : PWM mode 0 : Timer mode 1 : PWM mode 0 : PWM 2 mode 1 : Timer mode or PWM mode 0 : General register 1 : Buffer register of TRCGRA register 0 : General register 1 : Buffer register of TRCGRB register RW RW RW RW RW RW RW — RW Nothing is assigned. If necessary, set to 0. When read, the content is 1. TRC count start bit 0 : Count stops 1 : Count starts NOTES: 1. For notes on PWM2 mode, refer to 14.3.9.5 TRCMR Register in PWM2 Mode . 2. These bits are enabled w hen the PWM2 bit is set to 1 (timer mode or PWM mode). 3. Set the BFC bit to 0 (general register) in PWM2 mode. Figure 14.27 TRCMR Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 162 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RC Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRCCR1 Bit Symbol TOA TOB TOC TOD Address 0121h Bit Name TRCIOA output level select bit(1) TRCIOB output level select bit TRCIOC output level select bit (1) After Reset 00h Function Function varies according to the operating mode (function).(2) RW RW RW RW RW (1) TRCIOD output level select bit Count source select bits (1) (1) b6 b5 b4 TCK0 TCK1 TCK2 TRC counter clear select bit(2, 3) CCLR 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : f1 1 : f2 0 : f4 1 : f8 0 : f32 1 : TRCCLK input rising edge 0 : fOCO40M 1 : Do not set. RW RW RW 0 : Disable clear (free-running operation) 1 : Clear by compare match in the TRCGRA register RW NOTES: 1. Set to these bits w hen the TSTART bit in the TRCMR register is set to 0 (count stops). 2. Bits CCLR, TOA, TOB, TOC and TOD are disabled for the input capture function of the timer mode. 3. The TRC counter performs free-running operation for the input capture function of the timer mode independent of the CCLR bit setting. Figure 14.28 TRCCR1 Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 163 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RC Interrupt Enable Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRCIER Bit Symbol IMIEA Address 0122h Bit Name Input capture / compare match interrupt enable bit A After Reset 01110000b Function 0 : Disable interrupt (IMIA) by the IMFA bit 1 : Enable interrupt (IMIA) by the IMFA bit 0 : Disable interrupt (IMIB) by the IMFB bit 1 : Enable interrupt (IMIB) by the IMFB bit 0 : Disable interrupt (IMIC) by the IMFC bit 1 : Enable interrupt (IMIC) by the IMFC bit 0 : Disable interrupt (IMID) by the IMFD bit 1 : Enable interrupt (IMID) by the IMFD bit RW RW IMIEB Input capture / compare match interrupt enable bit B RW IMIEC Input capture / compare match interrupt enable bit C RW IMIED Input capture / compare match interrupt enable bit D RW — (b6-b4) Nothing is assigned. If necessary, set to 0. When read, the content is 1. Overflow interrupt enable bit 0 : Disable interrupt (OVI) by the OVF bit 1 : Enable interrupt (OVI) by the OVF bit — OVIE RW Figure 14.29 TRCIER Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 164 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RC Status Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRCSR Bit Symbol IMFA IMFB IMFC IMFD — (b6-b4) Address 0123h Bit Name Input capture / compare match flag A Input capture / compare match flag B Input capture / compare match flag C Input capture / compare match flag D After Reset 01110000b Function [Source for setting this bit to 0] Write 0 after read(1). [Source for setting this bit to 1] Refer to the table below . RW RW RW RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is 1. Overflow flag [Source for setting this bit to 0] Write 0 after read(1). [Source for setting this bit to 1] Refer to the table below . OVF RW NOTE: 1. The w riting results are as follow s: • This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit. • This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains 1 even if it is set to 1 from 0 after reading, and w riting 0.) • This bit remains unchanged if 1 is w ritten to it. Bit Symbol Timer Mode PWM Mode PWM2 Mode Input capture Function Output Compare Function TRCIOA pin input edge(1) When the values of the registers TRC and TRCGRA match. TRCIOB pin input edge(1) When the values of the registers TRC and TRCGRB match. When the values of the registers TRC and TRCGRC match.(2) TRCIOC pin input edge(1) TRCIOD pin input edge(1) When the values of the registers TRC and TRCGRD match.(2) When the TRC register overflow s. IMFA IMFB IMFC IMFD OVF NOTES: 1. Edge selected by bits IOj1 to IOj0 (j = A, B, C, or D). 2. Includes the condition that bits BFC and BFD are set to 1 (buffer registers of registers TRCGRA and TRCGRB). Figure 14.30 TRCSR Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 165 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RC Counter(1) (b15) b7 (b8) b0 b7 b0 Symbol TRC Address 0127h-0126h Function Count a count source. Count operation is incremented. When an overflow occurs, the OVF bit in the TRCSR register is set to 1. NOTE: 1. Access the TRC register in 16-bit units. Do not access it in 8-bit units. After Reset 0000h Setting Range 0000h to FFFFh RW RW Figure 14.31 TRC Register Timer RC General Register A, B, C and D(1) (b15) b7 (b8) b0 b7 b0 Symbol TRCGRA TRCGRB TRCGRC TRCGRD Address 0129h-0128h 012Bh-012Ah 012Dh-012Ch 012Fh-012Eh After Reset FFFFh FFFFh FFFFh FFFFh RW RW Function Function varies according to the operating mode. NOTE: 1. Access registers TRCGRA to TRCGRD in 16-bit units. Do not access them in 8-bit units. Figure 14.32 Registers TRCGRA, TRCGRB, TRCGRC, and TRCGRD Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 166 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RC Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address TRCCR2 0130h Bit Symbol Bit Name — Nothing is assigned. If necessary, set to 0. (b4-b0) When read, the content is 1. TRC count operation select bit(1, 2) After Reset 00011111b Function RW — CSEL 0 : Count continues at compare match w ith the TRCGRA register 1 : Count stops at compare match w ith the TRCGRA register b7 b6 RW TRCTRG input edge select bits (3) TCEG0 TCEG1 0 0 : Disable the trigger input from the TRCTRG pin 0 1 : Rising edge selected 1 0 : Falling edge selected 1 1 : Both edges selected RW RW NOTES: 1. For notes on PWM2 mode, refer to 14.3.9.5 TRCMR Register in PWM2 Mode . 2. In timer mode and PWM mode this bit is disabled (the count operation continues independent of the CSEL bit setting). 3. In timer mode and PWM mode these bits are disabled. Figure 14.33 TRCCR2 Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 167 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RC Digital Filter Function Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRCDF Bit Symbol DFA DFB DFC DFD DFTRG — (b5) Address 0131h Bit Name TRCIOA pin digital filter function select bit(1) TRCIOB pin digital filter function select bit(1) TRCIOC pin digital filter function select bit(1) TRCIOD pin digital filter function select bit(1) TRCTRG pin digital filter function select bit(2) After Reset 00h Function 0 : Function is not used 1 : Function is used RW RW RW RW RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. Clock select bits for digital filter function(1, 2) b7 b6 DFCK0 0 0 1 1 DFCK1 0 : f32 1 : f8 0 : f1 1 : Count source (clock selected by bits TCK2 to TCK0 in the TRCCR1 register) RW RW NOTES: 1. These bits are enabled for the input capture function. 2. These bits are enabled w hen in PWM2 mode and bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or 11b (TRCTRG trigger input enabled). Figure 14.34 TRCDF Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 168 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RC Output Master Enable Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRCOER Bit Symbol EA Address 0132h Bit Name TRCIOA output disable bit(1) After Reset 01111111b Function 0 : Enable output 1 : Disable output (The TRCIOA pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRCIOB pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRCIOC pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRCIOD pin is used as a programmable I/O port.) RW RW TRCIOB output disable bit(1) EB TRCIOC output disable bit(1) EC TRCIOD output disable bit(1) ED — (b6-b4) RW RW RW Nothing is assigned. If necessary, set to 0. When read, the content is 1. _____ — PTO INT0 of pulse output forced cutoff signal input enabled bit 0 : Pulse output forced cutoff input disabled 1 : Pulse output forced cutoff input enabled (Bits EA, EB, EC, and ED are set to 1 _____ RW (disable output) w hen “L” is applied to the INT0 pin) NOTE: 1. These bits are disabled for input pins set to the input capture function. Figure 14.35 TRCOER Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 169 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RC I/O Control Register 0(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address TRCIOR0 0124h Bit Symbol Bit Name IOA0 TRCGRA control bits IOA1 TRCGRA mode select bit(2) IOA2 IOA3 IOB0 IOB1 IOB2 — (b7) TRCGRA input capture input sw itch bit(4) TRCGRB control bits TRCGRB mode select bit(3) After Reset 10001000b Function Function varies according to the operating mode (function). 0 : Output compare function 1 : Input capture function 0 : fOCO128 signal 1 : TRCIOA pin input Function varies according to the operating mode (function). 0 : Output compare function 1 : Input capture function RW RW RW RW RW RW RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is 1. NOTES: 1. The TRCIOR0 register is enabled in timer mode. It is disabled in modes PWM and PWM2. 2. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 3. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. 4. The IOA3 bit is enabled w hen the IOA2 bit is set to 1 (input capture function). Timer RC I/O Control Register 1(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address TRCIOR1 0125h Bit Symbol Bit Name IOC0 TRCGRC control bits IOC1 TRCGRC mode select bit(2) IOC2 — (b3) IOD0 IOD1 IOD2 — (b7) After Reset 10001000b Function Function varies according to the operating mode (function). 0 : Output compare function 1 : Input capture function RW RW RW RW — RW RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is 1. TRCGRD control bits TRCGRD mode select bit(3) Function varies according to the operating mode (function). 0 : Output compare function 1 : Input capture function Nothing is assigned. If necessary, set to 0. When read, the content is 1. NOTES: 1. The TRCIOR1 register is enabled in timer mode. It is disabled in modes PWM and PWM2. 2. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 3. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. Figure 14.36 Registers TRCIOR0 and TRCIOR1 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 170 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.3.3 Common Items for Multiple Modes Count Source 14.3.3.1 The method of selecting the count source is common to all modes. Table 14.14 lists the Count Source Selection, and Figure 14.37 shows a Count Source Block Diagram. Table 14.14 Count Source Selection Count Source f1, f2, f4, f8, f32 fOCO40M Selection Method Count source selected using bits TCK2 to TCK0 in TRCCR1 register FRA00 bit in FRA0 register set to 1 (high-speed on-chip oscillator on) and bits TCK2 to TCK0 in TRCCR1 register are set to 110b (fOCO40M) External signal input Bits TCK2 to TCK0 in TRCCR1 register are set to 101b (count source is rising edge to TRCCLK pin of external clock) and PD3_3 bit in PD3 register is set to 0 (input mode) f1 f2 f4 f8 f32 TRCCLK fOCO40M TCK2 to TCK0 = 000b = 001b = 010b = 011b = 100b = 101b = 110b Count source TRC register TCK2 to TCK0: Bits in TRCCR1 register Figure 14.37 Count Source Block Diagram The pulse width of the external clock input to the TRCCLK pin should be three cycles or more of the timer RC operation clock (see Table 14.11 Timer RC Operation Clock). To select fOCO40M as the count source, set the FRA00 bit in the FRA0 register set to 1 (high-speed on-chip oscillator on), and then set bits TCK2 to TCK0 in the TRCCR1 register to 110b (fOCO40M). Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 171 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.3.3.2 Buffer Operation Bits BFC and BFD in the TRCMR register are used to select the TRCGRC or TRCGRD register as the buffer register for the TRCGRA or TRCGRB register. • Buffer register for TRCGRA register: TRCGRC register • Buffer register for TRCGRB register: TRCGRD register Buffer operation differs depending on the mode. Table 14.15 lists the Buffer Operation in Each Mode, Figure 14.38 shows the Buffer Operation for Input Capture Function, and Figure 14.39 shows the Buffer Operation for Output Compare Function. Table 14.15 Buffer Operation in Each Mode Transfer Timing Input capture signal input Transfer Destination Register Contents of TRCGRA (TRCGRB) register are transferred to buffer register Contents of buffer register are transferred to TRCGRA (TRCGRB) register Contents of buffer register (TRCGRD) are transferred to TRCGRB register Function, Mode Input capture function Output compare function Compare match between TRC register and TRCGRA (TRCGRB) PWM mode register PWM2 mode • Compare match between TRC register and TRCGRA register • TRCTRG pin trigger input TRCIOA input (input capture signal) TRCGRC register TRCGRA register TRC TRCIOA input TRC register n-1 n Transfer n+1 TRCGRA register m Transfer n TRCGRC register (buffer) m The above applies under the following conditions: • The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register). • Bits IOA2 to IOA0 in the TRCIOR0 register are set to 100b (input capture at the rising edge). Figure 14.38 Buffer Operation for Input Capture Function Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 172 of 332 R8C/2E Group, R8C/2F Group 14. Timers Compare match signal TRCGRC register TRCGRA register Comparator TRC TRC register m-1 m m+1 TRCGRA register m Transfer n TRCGRC register (buffer) n TRCIOA output The above applies under the following conditions: • The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register). • Bits IOA2 to IOA0 in the TRCIOR0 register are set to 001b (“L” output at compare match). Figure 14.39 Buffer Operation for Output Compare Function Make the following settings in timer mode. • To use the TRCGRC register as the buffer register for the TRCGRA register: Set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. • To use the TRCGRD register as the buffer register for the TRCGRB register: Set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. The output compare function, PWM mode, or PWM2 mode, and the TRCGRC or TRCGRD register is functioning as a buffer register, the IMFC bit or IMFD bit in the TRCSR register is set to 1 when a compare match with the TRC register occurs. The input capture function and the TRCGRC register or TRCGRD register is functioning as a buffer register, the IMFC bit or IMFD bit in the TRCSR register is set to 1 at the input edge of a signal input to the TRCIOC pin or TRCIOD pin. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 173 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.3.3.3 Digital Filter The input to TRCTRG or TRCIOj (j = A, B, C, or D) is sampled, and the level is considered to be determined when three matches occur. The digital filter function and sampling clock are selected using the TRCDF register. Figure 14.40 shows a Block Diagram of Digital Filter. TCK2 to TCK0 f1 f2 f4 f8 f32 TRCCLK fOCO40M = 001b = 010b = 011b Count source = 100b = 101b = 110b = 000b f32 f8 f1 DFCK1 to DFCK0 = 00b = 01b = 10b = 11b IOA2 to IOA0 IOB2 to IOB0 IOC2 to IOC0 IOD2 to IOD0 (or TCEG1 to TCEG0) Sampling clock DFj (or DFTRG) C TRCIOj input signal (or TRCTRG input signal) D Latch Timer RC operation clock f1 or fOCO40M C D Latch Q Q D C Q Latch D C Q Latch D C Q Latch Match detect circuit 1 Edge detect circuit 0 Clock cycle selected by TCK2 to TCK0 (or DFCK1 to DFCK0) Sampling clock TRCIOj input signal (or TRCTRG input signal) Three matches occur and a signal change is confirmed. Input signal after passing through digital filter Maximum signal transmission delay is five sampling clock pulses. If fewer than three matches occur, the matches are treated as noise and no transmission is performed. j = A, B, C, or D TCK0 to TCK2: Bits in TRCCR1 register DFTRG, DFCK0 to DFCK1, DFj: Bits in TRCDF register IOA0 to IOA2, IOB0 to IOB2: Bits in TRCIOR0 register IOC0 to IOC2, IOD0 to IOD2: Bits in TRCIOR1 register TCEG1 to TCEG0: Bits in TRCCR2 register Figure 14.40 Block Diagram of Digital Filter Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 174 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.3.3.4 Forced Cutoff of Pulse Output When using the timer mode’s output compare function, the PWM mode, or the PWM2 mode, pulse output from the TRCIOj (j = A, B, C, or D) output pin can be forcibly cut off and the TRCIOj pin set to function as a programmable I/O port by means of input to the INT0 pin. A pin used for output by the timer mode’s output compare function, the PWM mode, or the PWM2 mode can be set to function as the timer RC output pin by setting the Ej bit in the TRCOER register to 0 (timer RC output enabled). If “L” is input to the INT0 pin while the PTO bit in the TRCOER register is set to 1 (pulse output forced cutoff signal input INT0 enabled), bits EA, EB, EC, and ED in the TRCOER register are all set to 1 (timer RC output disabled, TRCIOj output pin functions as the programmable I/O port). When one or two cycles of the timer RC operation clock after “L” input to the INT0 p in (refer to Table 14.11 Timer RC Operation Clock) has elapsed, the TRCIOj output pin becomes a programmable I/O port. Make the following settings to use this function. • Set the pin state following forced cutoff of pulse output (high impedance (input), “L” output, or “H” output). (Refer to 7. Programmable I/O Ports.) • Set the INT0EN bit to 1 (INT0 input enabled) and the INT0PL bit to 0 (one edge) in the INTEN register. • Set the PD4_5 bit in the PD4 register to 0 (input mode). • Select the INT0 digital filter by means of bits INT0F1 to INT0F0 in the INTF register. • Set the PTO bit in the TRCOER register to 1 (pulse output forced cutoff signal input INT0 enabled). The IR bit in the INT0IC register is set to 1 (interrupt request) in accordance with the setting of the POL bit and a change in the INT0 pin input (refer to 12.6 Notes on Interrupts). For details on interrupts, refer to 12. Interrupts. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 175 of 332 R8C/2E Group, R8C/2F Group 14. Timers EA bit write value EA bit DQ S Timer RC output data Port P1_1 output data Port P1_1 input data INT0 input PTO bit TRCIOA EB bit write value EB bit DQ S Timer RC output data Port P1_2 output data Port P1_2 input data TRCIOB EC bit write value EC bit DQ S Timer RC output data TRCIOC Port P5_3 (P3_4)(1) output data Port P5_3 (P3_4)(1) input data ED bit DQ S Timer RC output data ED bit write value TRCIOD Port P5_4 (P3_5)(1) output data Port P5_4 (P3_5)(1) input data EA, EB, EC, ED, PTO: Bits in TRCOER register NOTE: 1. The pin in parentheses ( ) can be assigned by a program. Figure 14.41 Forced Cutoff of Pulse Output Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 176 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.3.4 Timer Mode (Input Capture Function) This function measures the width or period of an external signal. An external signal input to the TRCIOj (j = A, B, C, or D) pin acts as a trigger for transferring the contents of the TRC register (counter) to the TRCGRj register (input capture). The input capture function, or any other mode or function, can be selected for each individual pin. The TRCGRA register can also select fOCO128 signal as input-capture trigger input. Table 14.16 lists the Specifications of Input Capture Function, Figure 14.42 shows a Block Diagram of Input Capture Function, Figures 14.43 and 14.44 show registers associated with the input capture function, Table 14.17 lists the Functions of TRCGRj Register when Using Input Capture Function, and Figure 14.45 shows an Operating Example of Input Capture Function. Table 14.16 Specifications of Input Capture Function Specification f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to TRCCLK pin Increment 1/fk × 65,536 fk: Count source frequency 1 (count starts) is written to the TSTART bit in the TRCMR register. 0 (count stops) is written to the TSTART bit in the TRCMR register. The TRC register retains a value before count stops. • Input capture (valid edge of TRCIOj input or fOCO128 signal edge) • The TRC register overflows. Programmable I/O port or input capture input (selectable individually by pin) Programmable I/O port or INT0 interrupt input The count value can be read by reading TRC register. The TRC register can be written to. • Input capture input pin select One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD • Input capture input valid edge selected Rising edge, falling edge, or both rising and falling edges • Buffer operation (Refer to 14.3.3.2 Buffer Operation.) • Digital filter (Refer to 14.3.3.3 Digital Filter.) • Input-capture trigger selected fOCO128 can be selected for input-capture trigger input of the TRCGRA register. Item Count source Count operation Count period Count start condition Count stop condition Interrupt request generation timing TRCIOA, TRCIOB, TRCIOC, and TRCIOD pin functions INT0 pin function Read from timer Write to timer Select functions j = A, B, C, or D Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 177 of 332 R8C/2E Group, R8C/2F Group 14. Timers fOCO Divided by 128 fOCO128 IOA3 = 0 Input capture signal(3) TRCIOA IOA3 = 1 (Note 1) TRCGRA register TRC register TRCGRC register TRCIOC Input capture signal Input capture signal TRCIOB TRCGRB register (Note 2) TRCGRD register TRCIOD Input capture signal IOA3: Bit in TRCIOR0 register NOTES: 1. The BFC bit in the TRCMR register is set to 1 (TRCGRC register functions as the buffer register for the TRCGRA register) 2. The BFD bit in the TRCMR register is set to 1 (TRCGRD register functions as the buffer register for the TRCGRB register) 3. The trigger input of the TRCGRA register can select the TRCIOA pin input or fOCO128 signal. Figure 14.42 Block Diagram of Input Capture Function Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 178 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RC I/O Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol TRCIOR0 Bit Symbol Address 0124h Bit Name TRCGRA control bits After Reset 10001000b Function b1 b0 RW IOA0 IOA1 0 0 : Input capture to the TRCGRA register at the rising edge 0 1 : Input capture to the TRCGRA register at the falling edge 1 0 : Input capture to the TRCGRA register at both edges 1 1 : Do not set. TRCGRA mode select bit(1) TRCGRA input capture input sw itch bit(3) TRCGRB control bits Set to 1 (input capture) in the input capture function. 0 : fOCO128 signal 1 : TRCIOA pin input b5 b4 RW RW IOA2 IOA3 RW RW IOB0 IOB1 0 0 : Input capture to the TRCGRB register at the rising edge 0 1 : Input capture to the TRCGRB register at the falling edge 1 0 : Input capture to the TRCGRB register at both edges 1 1 : Do not set. TRCGRB mode select bit(2) Set to 1 (input capture) in the input capture function. RW RW IOB2 — (b7) RW — Nothing is assigned. If necessary, set to 0. When read, the content is 1. NOTES: 1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. 3. The IOA3 bit is enabled w hen the IOA2 bit is set to 1 (input capture function). Figure 14.43 TRCIOR0 Register in Input Capture Function Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 179 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RC I/O Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol TRCIOR1 Bit Symbol Address 0125h Bit Name TRCGRC control bits After Reset 10001000b Function b1 b0 RW IOC0 IOC1 0 0 : Input capture to the TRCGRC register at the rising edge 0 1 : Input capture to the TRCGRC register at the falling edge 1 0 : Input capture to the TRCGRC register at both edges 1 1 : Do not set. TRCGRC mode select bit(1) Set to 1 (input capture) in the input capture function. RW RW IOC2 — (b3) RW — Nothing is assigned. If necessary, set to 0. When read, the content is 1. TRCGRD control bits b5 b4 IOD0 IOD1 0 0 : Input capture to the TRCGRD register at the rising edge 0 1 : Input capture to the TRCGRD register at the falling edge 1 0 : Input capture to the TRCGRD register at both edges 1 1 : Do not set. TRCGRD mode select bit(2) Set to 1 (input capture) in the input capture function. RW RW IOD2 — (b7) RW — Nothing is assigned. If necessary, set to 0. When read, the content is 1. NOTES: 1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. Figure 14.44 TRCIOR1 Register in Input Capture Function Table 14.17 Register TRCGRA TRCGRB TRCGRC TRCGRD TRCGRC TRCGRD Functions of TRCGRj Register when Using Input Capture Function Setting − BFC = 0 BFD = 0 BFC = 1 BFD = 1 Input Capture Input Pin General register. Can be used to read the TRC register value TRCIOA at input capture. TRCIOB General register. Can be used to read the TRC register value TRCIOC at input capture. TRCIOD Buffer registers. Can be used to hold transferred value from TRCIOA the general register. (Refer to 14.3.3.2 Buffer Operation.) TRCIOB Register Function j = A, B, C, or D BFC, BFD: Bits in TRCMR register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 180 of 332 R8C/2E Group, R8C/2F Group 14. Timers TRCCLK input count source TRC register count value FFFFh 0006h 0003h 0000h TSTART bit in TRCMR register 1 0 65536 TRCIOA input TRCGRA register Transfer TRCGRC register 0006h 0003h Transfer 0006h IMFA bit in TRCSR register OVF bit in TRCSR register 1 0 1 0 Set to 0 by a program The above applies under the following conditions: • Bits TCK2 to TCK0 in the TRCCR1 register are set to 101b (the count source is TRCCLK input). • Bits IOA2 to IOA0 in the TRCIORA register are set to 101b (input capture at the falling edge of the TRCIOA input). • The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register). Figure 14.45 Operating Example of Input Capture Function Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 181 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.3.5 Timer Mode (Output Compare Function) This function detects when the contents of the TRC register (counter) and the TRCGRj register (j = A, B, C, or D) match (compare match). When a match occurs a signal is output from the TRCIOj pin at a given level. The output compare function, or other mode or function, can be selected for each individual pin. Table 14.18 lists the Specifications of Output Compare Function, Figure 14.46 shows a Block Diagram of Output Compare Function, Figures 14.47 to 14.49 show registers associated with the output compare function, Table 14.19 lists the Functions of TRCGRj Register when Using Output Compare Function, and Figure 14.50 shows an Operating Example of Output Compare Function. Table 14.18 Specifications of Output Compare Function Specification f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to TRCCLK pin Increment • The CCLR bit in the TRCCR1 register is set to 0 (free running operation): 1/fk × 65,536 fk: Count source frequency • The CCLR bit in the TRCCR1 register is set to 1 (TRC register set to 0000h at TRCGRA compare match): 1/fk × (n + 1) n: TRCGRA register setting value Compare match 1 (count starts) is written to the TSTART bit in the TRCMR register. 0 (count stops) is written to the TSTART bit in the TRCMR register. The output compare output pin retains output level before count stops, the TRC register retains a value before count stops. • Compare match (contents of registers TRC and TRCGRj match) • The TRC register overflows. Programmable I/O port or output compare output (selectable individually by pin) Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input The count value can be read by reading the TRC register. The TRC register can be written to. • Output compare output pin selected One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD • Compare match output level select “L” output, “H” output, or output level inverted • Initial output level select Sets output level for period from count start to compare match • Timing for clearing the TRC register to 0000h Overflow or compare match with the TRCGRA register • Buffer operation (Refer to 14.3.3.2 Buffer Operation.) • Pulse output forced cutoff signal input (Refer to 14.3.3.4 Forced Cutoff of Pulse Output.) • Can be used as an internal timer by disabling timer RC output Item Count source Count operation Count period Waveform output timing Count start condition Count stop condition Interrupt request generation timing TRCIOA, TRCIOB, TRCIOC, and TRCIOD pin functions INT0 pin function Read from timer Write to timer Select functions j = A, B, C, or D Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 182 of 332 R8C/2E Group, R8C/2F Group 14. Timers TRC Output control Compare match signal Comparator TRCGRA TRCIOA TRCIOC Output control Compare match signal Comparator TRCGRC TRCIOB Output control Compare match signal Comparator TRCGRB TRCIOD Output control Compare match signal Comparator TRCGRD Figure 14.46 Block Diagram of Output Compare Function Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 183 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RC I/O Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 0 10 Symbol TRCIOR0 Bit Symbol Address 0124h Bit Name TRCGRA control bits After Reset 10001000b Function b1 b0 RW IOA0 IOA1 0 0 : Disable pin output by compare match (TRCIOA pin functions as the programmable I/O port) 0 1 : “L” output by compare match in the TRCGRA register 1 0 : “H” output by compare match in the TRCGRA register 1 1 : Toggle output by compare match in the TRCGRA register TRCGRA mode select bit(1) TRCGRA input capture input sw itch bit TRCGRB control bits Set to 0 (output compare) in the output compare function. Set to 1. b5 b4 RW RW IOA2 IOA3 RW RW IOB0 IOB1 0 0 : Disable pin output by compare match (TRCIOB pin functions as the programmable I/O port) 0 1 : “L” output by compare match in the TRCGRB register 1 0 : “H” output by compare match in the TRCGRB register 1 1 : Toggle output by compare match in the TRCGRB register TRCGRB mode select bit(2) Set to 0 (output compare) in the output compare function. RW RW IOB2 — (b7) RW — Nothing is assigned. If necessary, set to 0. When read, the content is 1. NOTES: 1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. Figure 14.47 TRCIOR0 Register in Output Compare Function Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 184 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RC I/O Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol TRCIOR1 Bit Symbol Address 0125h Bit Name TRCGRC control bits After Reset 10001000b Function b1 b0 RW IOC0 IOC1 0 0 : Disable pin output by compare match 0 1 : “L” output by compare match in the TRCGRC register 1 0 : “H” output by compare match in the TRCGRC register 1 1 : Toggle output by compare match in the TRCGRC register RW RW IOC2 — (b3) TRCGRC mode select bit(1) Set to 0 (output compare) in the output compare function. RW — Nothing is assigned. If necessary, set to 0. When read, the content is 1. TRCGRD control bits b5 b4 IOD0 IOD1 0 0 : Disable pin output by compare match 0 1 : “L” output by compare match in the TRCGRD register 1 0 : “H” output by compare match in the TRCGRD register 1 1 : Toggle output by compare match in the TRCGRD register RW RW IOD2 — (b7) TRCGRD mode select bit(2) Set to 0 (output compare) in the output compare function. RW — Nothing is assigned. If necessary, set to 0. When read, the content is 1. NOTES: 1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. Figure 14.48 TRCIOR1 Register in Output Compare Function Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 185 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RC Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRCCR1 Bit Symbol TOA TOB TOC TOD Address 0121h Bit Name TRCIOA output level select bit(1, 2) TRCIOB output level select bit TRCIOC output level select bit (1, 2) After Reset 00h Function 0 : Initial output “L” 1 : Initial output “H” RW RW RW RW RW (1, 2) TRCIOD output level select bit Count source select bits (1) (1, 2) b6 b5 b4 TCK0 TCK1 TCK2 TRC counter clear select bit CCLR 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : f1 1 : f2 0 : f4 1 : f8 0 : f32 1 : TRCCLK input rising edge 0 : fOCO40M 1 : Do not set. RW RW RW 0 : Disable clear (free-running operation) 1 : Clear by compare match in the TRCGRA register RW NOTES: 1. Set to these bits w hen the TSTART bit in the TRCMR register is set to 0 (count stops). 2. If the pin function is set for w aveform output (refer to Tables 7.13 to 7.16, Tables 7.26 to 7.29, and Tables 7.36 to 7.39), the initial output level is output w hen the TRCCR1 register is set. Figure 14.49 TRCCR1 Register in Output Compare Function Table 14.19 Register TRCGRA TRCGRB TRCGRC TRCGRD TRCGRC TRCGRD Functions of TRCGRj Register when Using Output Compare Function Setting − BFC = 0 BFD = 0 BFC = 1 BFD = 1 Register Function General register. Write a compare value to one of these registers. General register. Write a compare value to one of these registers. Buffer register. Write the next compare value to one of these registers. (Refer to 14.3.3.2 Buffer Operation.) Output Compare Output Pin TRCIOA TRCIOB TRCIOC TRCIOD TRCIOA TRCIOB j = A, B, C, or D BFC, BFD: Bits in TRCMR register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 186 of 332 R8C/2E Group, R8C/2F Group 14. Timers Count source TRC register value m n p Count restarts Count stops TSTART bit in TRCMR register 1 0 m+1 m+1 Output level held TRCIOA output Output inverted at compare match Initial output “L” IMFA bit in TRCSR register 1 0 Set to 0 by a program n+1 TRCIOB output Output level held “H” output at compare match Initial output “L” 1 0 Set to 0 by a program P+1 “L” output at compare match Output level held IMFB bit in TRCSR register TRCIOC output Initial output “H” IMFC bit in TRCSR register 1 0 Set to 0 by a program m: TRCGRA register setting value n: TRCGRB register setting value p: TRCGRC register setting value The above applies under the following conditions: • Bits BFC and BFD in the TRCMR register are set to 0 (TRCGRC and TRCGRD do not operate as buffers). • Bits EA, EB, and EC in the TRCOER register are set to 0 (output from TRCIOA, TRCIOB, and TRCIOC enabled). • The CCLR bit in the TRCCR1 register is set to 1 (set the TRC register to 0000h by TRCGRA compare match). • In the TRCCR1 register, bits TOA and TOB are set to 0 (“L” initial output until compare match) and the TOC bit is set to 1 (“H” initial output until compare match). • Bits IOA2 to IOA0 in the TRCIOR0 register are set to 011b (TRCIOA output inverted at TRCGRA compare match). • Bits IOB2 to IOB0 in the TRCIOR0 register are set to 010b (“H” TRCIOB output at TRCGRB compare match). • Bits IOC2 to IOC2 in the TRCIOR1 register are set to 001b (“L” TRCIOC output at TRCGRC compare match). Figure 14.50 Operating Example of Output Compare Function Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 187 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.3.6 PWM Mode This mode outputs PWM waveforms. A maximum of three PWM waveforms with the same period are output. The PWM mode, or the timer mode, can be selected for each individual pin. (However, since the TRCGRA register is used when using any pin for the PWM mode, the TRCGRA register cannot be used for the timer mode.) Table 14.20 lists the Specifications of PWM Mode, Figure 14.51 shows a Block Diagram of PWM Mode, Figure 14.52 shows the registers associated with the PWM mode, Table 14.21 lists the Functions of TRCGRj Register in PWM Mode, and Figures 14.53 and 14.54 show Operating Examples of PWM Mode. Table 14.20 Count source Count operation PWM waveform Specifications of PWM Mode Item Specification f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to TRCCLK pin Increment PWM period: 1/fk × (m + 1) Active level width: 1/fk × (m - n) Inactive width: 1/fk × (n + 1) fk: Count source frequency m: TRCGRA register setting value n: TRCGRj register setting value m+1 n+1 m-n (“L” is active level) Count start condition Count stop condition Interrupt request generation timing TRCIOA pin function TRCIOB, TRCIOC, and TRCIOD pin functions INT0 pin function Read from timer Write to timer Select functions 1 (count starts) is written to the TSTART bit in the TRCMR register. 0 (count stops) is written to the TSTART bit in the TRCMR register. PWM output pin retains output level before count stops, TRC register retains value before count stops. • Compare match (contents of registers TRC and TRCGRj match) • The TRC register overflows. Programmable I/O port Programmable I/O port or PWM output (selectable individually by pin) Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input The count value can be read by reading the TRC register. The TRC register can be written to. • One to three pins selectable as PWM output pins per channel One or more of pins TRCIOB, TRCIOC, and TRCIOD • Active level selectable by individual pin • Buffer operation (Refer to 14.3.3.2 Buffer Operation.) • Pulse output forced cutoff signal input (Refer to 14.3.3.4 Forced Cutoff of Pulse Output.) j = B, C, or D Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 188 of 332 R8C/2E Group, R8C/2F Group 14. Timers TRC Compare match signal TRCIOB Compare match signal Comparator TRCGRA (Note 1) TRCIOC Output control Comparator Compare match signal TRCGRB TRCIOD Compare match signal Comparator TRCGRC (Note 2) Comparator TRCGRD NOTES: 1. The BFC bit in the TRCMR register is set to 1 (TRCGRC register functions as the buffer register for the TRCGRA register) 2. The BFD bit in the TRCMR register is set to 1 (TRCGRD register functions as the buffer register for the TRCGRB register) Figure 14.51 Block Diagram of PWM Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 189 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RC Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRCCR1 Bit Symbol TOA Address 0121h Bit Name TRCIOA output level select bit(1) TRCIOB output level select bit(1, 2) After Reset 00h Function Disabled in PWM mode 0 : Active level “H” (Initial output “L” “H” output by compare match in the TRCGRj register “L” output by compare match in the TRCGRA register 1 : Active level “L” (Initial output “H” “L” output by compare match in the TRCGRj register “H” output by compare match in the TRCGRA register b6 b5 b4 RW RW TOB RW TRCIOC output level select bit(1, 2) TOC RW TRCIOD output level select bit(1, 2) TOD RW Count source select bits (1) TCK0 TCK1 TCK2 TRC counter clear select bit CCLR 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : f1 1 : f2 0 : f4 1 : f8 0 : f32 1 : TRCCLK input rising edge 0 : fOCO40M 1 : Do not set. RW RW RW 0 : Disable clear (free-running operation) 1 : Clear by compare match in the TRCGRA register RW j = B, C or D NOTES: 1. Set to these bits w hen the TSTART bit in the TRCMR register is set to 0 (count stops). 2. If the pin function is set for w aveform output (refer to Table 7.15, Table 7.16, Tables 7.26 to 7.29, and Tables 7.36 to 7.39), the initial output level is output w hen the TRCCR1 register is set. Figure 14.52 TRCCR1 Register in PWM Mode Table 14.21 Register TRCGRA TRCGRB TRCGRC TRCGRD TRCGRC TRCGRD Functions of TRCGRj Register in PWM Mode Setting − − BFC = 0 BFD = 0 BFC = 1 Register Function General register. Set the PWM period. General register. Set the PWM output change point. General register. Set the PWM output change point. Buffer register. Set the next PWM period. (Refer to 14.3.3.2 Buffer Operation.) Buffer register. Set the next PWM output change point. (Refer to 14.3.3.2 Buffer Operation.) PWM Output Pin − TRCIOB TRCIOC TRCIOD − TRCIOB BFD = 1 j = A, B, C, or D BFC, BFD: Bits in TRCMR register NOTE: 1. The output level does not change even when a compare match occurs if the TRCGRA register value (PWM period) is the same as the TRCGRB, TRCGRC, or TRCGRD register value. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 190 of 332 R8C/2E Group, R8C/2F Group 14. Timers Count source TRC register value m n p q m+1 n+1 m-n TRCIOB output Active level is “H” Inactive level is “L” p+1 m-p “L” initial output until compare match TRCIOC output q+1 m-q TRCIOD output Active level is “L” “H” initial output until compare match IMFA bit in TRCSR register 1 0 Set to 0 by a program Set to 0 by a program IMFB bit in TRCSR register 1 0 IMFC bit in TRCSR register 1 0 Set to 0 by a program Set to 0 by a program IMFD bit in TRCSR register 1 0 m: TRCGRA register setting value n: TRCGRB register setting value p: TRCGRC register setting value q: TRCGRD register setting value The above applies under the following conditions: • Bits BFC and BFD in the TRCMR register are set to 0 (registers TRCGRC and TRCGRD do not operate as buffers). • Bits EB, EC, and ED in the TRCOER register are set to 0 (output from TRCIOB, TRCIOC, and TRCIOD enabled). • In the TRCCR1 register, bits TOB and TOC are set to 0 (active level is “H”) and the TOD bit is set to 1 (active level is “L”). Figure 14.53 Operating Example of PWM Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 191 of 332 R8C/2E Group, R8C/2F Group 14. Timers TRC register value p m q n 0000h TSTART bit in TRCMR register 1 0 Duty 0% TRCIOB output does not switch to “L” because no compare match with the TRCGRB register has occurred TRCIOB output TRCGRB register n p (p>m) Rewritten by a program q IMFA bit in TRCSR register 1 0 Set to 0 by a program Set to 0 by a program IMFB bit in TRCSR register 1 0 TRC register value m p n 0000h TSTART bit in TRCMR register 1 0 If compare matches occur simultaneously with registers TRCGRA and TRCGRB, the compare match with the TRCGRB register has priority. TRCIOB output switches to “L”. (In other words, no change). Duty 100% TRCIOB output switches to “L” at compare match with the TRCGRB register. (In other words, no change). TRCIOB output TRCGRB register n m Rewritten by a program p IMFA bit in TRCSR register 1 0 Set to 0 by a program IMFB bit in TRCSR register 1 0 Set to 0 by a program m: TRCGRA register setting value The above applies under the following conditions: • The EB bit in the TRCOER register is set to 0 (output from TRCIOB enabled). • The TOB bit in the TRCCR1 register is set to 1 (active level is “L”). Figure 14.54 Operating Example of PWM Mode (Duty 0% and Duty 100%) Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 192 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.3.7 PWM2 Mode This mode outputs a single PWM waveform. After a given wait duration has elapsed following the trigger, the pin output switches to active level. Then, after a given duration, the output switches back to inactive level. Furthermore, the counter stops at the same time the output returns to inactive level, making it possible to use PWM2 mode to output a programmable wait one-shot waveform. Since timer RC uses multiple general registers in PWM2 mode, other modes cannot be used in conjunction with it. Figure 14.55 shows a Block Diagram of PWM2 Mode, Table 14.22 lists the Specifications of PWM2 Mode, Figure 14.56 shows the register associated with PWM2 mode, Table 14.23 lists the Functions of TRCGRj Register in PWM2 Mode, and Figures 14.57 to 14.59 show Operating Examples of PWM2 Mode. Trigger signal Compare match signal TRCTRG Input control Count clear signal (Note 1) TRC Comparator TRCGRA Comparator TRCGRB TRCGRD register TRCIOB Output control Comparator TRCGRC NOTE: 1. The BFD bit in the TRCMR register is set to 1 (the TRCGRD register functions as the buffer register for the TRCGRB register). Figure 14.55 Block Diagram of PWM2 Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 193 of 332 R8C/2E Group, R8C/2F Group 14. Timers Table 14.22 Specifications of PWM2 Mode Specification f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to TRCCLK pin Increment TRC register PWM period: 1/fk × (m + 1) (no TRCTRG input) Active level width: 1/fk × (n - p) Wait time from count start or trigger: 1/fk × (p + 1) fk: Count source frequency m: TRCGRA register setting value n: TRCGRB register setting value p: TRCGRC register setting value TRCTRG input m+1 n+1 p+1 TRCIOB output n-p n-p (TRCTRG: Rising edge, active level is “H”) n+1 p+1 Item Count source Count operation PWM waveform Count start conditions Count stop conditions Interrupt request generation timing TRCIOA/TRCTRG pin function TRCIOB pin function PWM output TRCIOC and TRCIOD pin Programmable I/O port functions INT0 pin function Read from timer Write to timer Select functions • Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger disabled) or the CSEL bit in the TRCCR2 register is set to 0 (count continues). 1 (count starts) is written to the TSTART bit in the TRCMR register. • Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or 11b (TRCTRG trigger enabled) and the TSTART bit in the TRCMR register is set to 1 (count starts). A trigger is input to the TRCTRG pin • 0 (count stops) is written to the TSTART bit in the TRCMR register while the CSEL bit in the TRCCR2 register is set to 0 or 1. The TRCIOB pin outputs the initial level in accordance with the value of the TOB bit in the TRCCR1 register. The TRC register retains the value before count stops. • The count stops due to a compare match with TRCGRA while the CSEL bit in the TRCCR2 register is set to 1 The TRCIOB pin outputs the initial level. The TRC register retains the value before count stops if the CCLR bit in the TRCCR1 register is set to 0. The TRC register is set to 0000h if the CCLR bit in the TRCCR1 register is set to 1. • Compare match (contents of TRC and TRCGRj registers match) • The TRC register overflows Programmable I/O port or TRCTRG input Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input The count value can be read by reading the TRC register. The TRC register can be written to. • External trigger and valid edge selected The edge or edges of the signal input to the TRCTRG pin can be used as the PWM output trigger: rising edge, falling edge, or both rising and falling edges • Buffer operation (Refer to 14.3.3.2 Buffer Operation.) • Pulse output forced cutoff signal input (Refer to 14.3.3.4 Forced Cutoff of Pulse Output.) • Digital filter (Refer to 14.3.3.3 Digital Filter.) j = A, B, C, or D Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 194 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RC Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRCCR1 Bit Symbol TOA Address 0121h Bit Name TRCIOA output level select bit(1) TRCIOB output level select bit(1, 2) After Reset 00h Function Disabled in the PWM2 mode 0 : Active level “H” (Initial output “L” “H” output by compare match in the TRCGRC register “L” output by compare match in the TRCGRB register) 1 : Active level “L” (Initial output “H” “L” output by compare match in the TRCGRC register “H” output by compare match in the TRCGRB register) Disabled in the PWM2 mode RW RW TOB RW TOC TOD TRCIOC output level select bit(1) TRCIOD output level select bit(1) Count source select bits (1) RW RW b6 b5 b4 TCK0 TCK1 TCK2 TRC counter clear select bit CCLR 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : f1 1 : f2 0 : f4 1 : f8 0 : f32 1 : TRCCLK input rising edge 0 : fOCO40M 1 : Do not set. RW RW RW 0 : Disable clear (free-running operation) 1 : Clear by compare match in the TRCGRA register RW NOTES: 1. Set to these bits w hen the TSTART bit in the TRCMR register is set to 0 (count stops). 2. If the pin function is set for w aveform output (refer to Table 7.15 and Table 7.16), the initial output level is output w hen the TRCCR1 register is set. Figure 14.56 TRCCR1 Register in PWM2 Mode Table 14.23 Register TRCGRA TRCGRB TRCGRC TRCGRD TRCGRD Functions of TRCGRj Register in PWM2 Mode Setting − − BFC = 0 BFD = 0 BFD = 1 Register Function PWM2 Output Pin General register. Set the PWM period. TRCIOB pin General register. Set the PWM output change point. General register. Set the PWM output change point (wait time after trigger). (Not used in PWM2 mode) − Buffer register. Set the next PWM output change point. (Refer to TRCIOB pin 14.3.3.2 Buffer Operation.) j = A, B, C, or D BFC, BFD: Bits in TRCMR register NOTE: 1. Do not set the TRCGRB and TRCGRC registers to the same value. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 195 of 332 R8C/2E Group, R8C/2F Group 14. Timers Count source TRC register value FFFFh m TRC register cleared at TRCGRA register compare match n Previous value held if the TSTRAT bit is set to 0 Set to 0000h by a program p 0000h TSTART bit in TRCMR register 1 0 Set to 1 by a program Count stops because the CSEL bit is set to 1 TSTART bit is set to 0 CSEL bit in TRCCR2 register 1 0 m+1 n+1 p+1 “H” output at TRCGRC register compare match “L” initial output Return to initial output if the TSTART bit is set to 0 No change “H” output at TRCGRC register compare match p+1 “L” output at TRCGRB register compare match No change TRCIOB output IMFA bit in TRCSR register 1 0 IMFB bit in TRCSR register 1 0 Set to 0 by a program IMFC bit in TRCSR register 1 0 Set to 0 by a program Set to 0 by a program TRCGRB register Transfer TRCGRD register n n Transfer Next data Transfer from buffer register to general register m: TRCGRA register setting value n: TRCGRB register setting value p: TRCGRC register setting value The above applies under the following conditions: • The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare match with the TRCGRB register). • Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled). Figure 14.57 Operating Example of PWM2 Mode (TRCTRG Trigger Input Disabled) Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 196 of 332 R8C/2E Group, R8C/2F Group 14. Timers Count source TRC register value FFFFh m TRC register (counter) cleared at TRCTRG pin trigger input TRC register cleared at TRCGRA register compare match n Previous value held if the TSTART bit is set to 0 Set to 0000h by a program p 0000h Count starts at TRCTRG pin trigger input Changed by a program The TSTART bit is set to 0 Count stops because the CSEL bit is set to 1 TRCTRG input Count starts TSTART bit is set to 1 1 0 TSTART bit in TRCMR register CSEL bit in TRCCR2 register 1 0 Set to 1 by a program m+1 n+1 p+1 “H” output at TRCGRC register compare match “L” output at TRCGRB register compare match p+1 n+1 p+1 TRCIOB output “L” initial output Active level so TRCTRG input is disabled IMFA bit in TRCSR register 1 0 Inactive level so TRCTRG input is enabled Return to initial value if the TSTART bit is set to 0 IMFB bit in TRCSR register 1 0 Set to 0 by a program Set to 0 by a program Set to 0 by a program Set to 0 by a program IMFC bit in TRCSR register 1 0 TRCGRB register n Transfer n n Transfer n Transfer n Transfer Next data TRCGRD register Transfer from buffer register to general register Transfer from buffer register to general register m: TRCGRA register setting value n: TRCGRB register setting value p: TRCGRC register setting value The above applies under the following conditions: • The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare match with the TRCGRB register). • Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 11b (trigger at both rising and falling edges of TRCTRG input). Figure 14.58 Operating Example of PWM2 Mode (TRCTRG Trigger Input Enabled) Page 197 of 332 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 R8C/2E Group, R8C/2F Group 14. Timers • TRCGRB register setting value greater than TRCGRA register setting value TRC register value n m • TRCGRC register setting value greater than TRCGRA register setting value TRC register value p m n p 0000h TSTART bit in TRCMR register 1 0 p+1 m+1 No compare match with TRCGRB register, so “H” output continues TRCIOB output TRCIOB output “L” initial output TSTART bit in TRCMR register 0000h 1 0 n+1 m+1 No compare match with TRCGRC register, so “L” output continues “L” output at TRCGRB register compare match with no change. “H” output at TRCGRC register compare match 1 0 “L” initial output IMFA bit in TRCSR register IMFA bit in TRCSR register 1 0 IMFB bit in TRCSR register 1 0 Set to 0 by a program IMFB bit in TRCSR register 1 0 IMFC bit in TRCSR register 1 0 IMFC bit in TRCSR register 1 0 m: TRCGRA register setting value n: TRCGRB register setting value p: TRCGRC register setting value The above applies under the following conditions: • The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare match with the TRCGRB register). • Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled). Figure 14.59 Operating Example of PWM2 Mode (Duty 0% and Duty 100%) Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 198 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.3.8 Timer RC Interrupt Timer RC generates a timer RC interrupt request from five sources. The timer RC interrupt uses the single TRCIC register (bits IR and ILVL0 to ILVL2) and a single vector. Table 14.24 lists the Registers Associated with Timer RC Interrupt, and Figure 14.60 is a Timer RC Interrupt Block Diagram. Table 14.24 Registers Associated with Timer RC Interrupt Timer RC Interrupt Enable Register TRCIER Timer RC Interrupt Control Register TRCIC Timer RC Status Register TRCSR IMFA bit IMIEA bit IMFB bit IMIEB bit IMFC bit IMIEC bit IMFD bit IMIED bit OVF bit OVIE bit Timer RC interrupt request (IR bit in TRCIC register) IMFA, IMFB, IMFC, IMFD, OVF: Bits in TRCSR register IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRCIER register Figure 14.60 Timer RC Interrupt Block Diagram Like other maskable interrupts, the timer RC interrupt is controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, it differs from other maskable interrupts in the following respects because a single interrupt source (timer RC interrupt) is generated from multiple interrupt request sources. • The IR bit in the TRCIC register is set to 1 (interrupt requested) when a bit in the TRCSR register is set to 1 and the corresponding bit in the TRCIER register is also set to 1 (interrupt enabled). • The IR bit is set to 0 (no interrupt request) when the bit in the TRCSR register or the corresponding bit in the TRCIER register is set to 0, or both are set to 0. In other words, the interrupt request is not maintained if the IR bit is once set to 1 but the interrupt is not acknowledged. • If after the IR bit is set to 1 another interrupt source is triggered, the IR bit remains set to 1 and does not change. • If multiple bits in the TRCIER register are set to 1, use the TRCSR register to determine the source of the interrupt request. • The bits in the TRCSR register are not automatically set to 0 when an interrupt is acknowledged. Set them to 0 within the interrupt routine. Refer to Figure 14.30 TRCSR Register, for the procedure for setting these bits to 0. Refer to Figure 14.29 TRCIER Register, for details of the TRCIER register. Refer to 12.1.6 Interrupt Control, for details of the TRCIC register and 12.1.5.2 Relocatable Vector Tables, for information on interrupt vectors. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 199 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.3.9 Notes on Timer RC TRC Register 14.3.9.1 • The following note applies when the CCLR bit in the TRCCR1 register is set to 1 (clear TRC register at compare match with TRCGRA register). When using a program to write a value to the TRC register while the TSTART bit in the TRCMR register is set to 1 (count starts), ensure that the write does not overlap with the timing with which the TRC register is set to 0000h. If the timing of the write to the TRC register and the setting of the TRC register to 0000h coincide, the write value will not be written to the TRC register and the TRC register will be set to 0000h. • Reading from the TRC register immediately after writing to it can result in the value previous to the write being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions. Program Example MOV.W #XXXXh, TRC ;Write JMP.B L1 ;JMP.B instruction L1: MOV.W TRC,DATA ;Read 14.3.9.2 TRCSR Register Reading from the TRCSR register immediately after writing to it can result in the value previous to the write being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions. Program Example MOV.B #XXh, TRCSR ;Write JMP.B L1 ;JMP.B instruction L1: MOV.B TRCSR,DATA ;Read 14.3.9.3 Count Source Switching • Stop the count before switching the count source. Switching procedure (1) Set the TSTART bit in the TRCMR register to 0 (count stops). (2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register. • After switching the count source from fOCO40M to another clock, allow a minimum of two cycles of f1 to elapse after changing the clock setting before stopping fOCO40M. Switching procedure (1) Set the TSTART bit in the TRCMR register to 0 (count stops). (2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register. (3) Wait for a minimum of two cycles of f1. (4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off). 14.3.9.4 Input Capture Function • The pulse width of the input capture signal should be three cycles or more of the timer RC operation clock (refer to Table 14.11 Timer RC Operation Clock). • The value of the TRC register is transferred to the TRCGRj register one or two cycles of the timer RC operation clock after the input capture signal is input to the TRCIOj (j = A, B, C, or D) pin (when the digital filter function is not used). 14.3.9.5 TRCMR Register in PWM2 Mode When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA register), do not set the TRCMR register at compare match timing of registers TRC and TRCGRA. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 200 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.4 Timer RE Timer RE has the 4-bit counter and 8-bit counter. Timer RE has the following modes: • Output compare mode Count a count source and detect compare matches. The count source for timer RE is the operating clock that regulates the timing of timer operations. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 201 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.4.1 Output Compare Mode In output compare mode, the internal count source divided by 2 is counted using the 4-bit or 8-bit counter and compare value match is detected with the 8-bit counter. Figure 14.61 shows a Block Diagram of Output Compare Mode and Table 14.25 lists the Output Compare Mode Specifications. Figures 14.62 to 14.66 show the Registers Associated with Output Compare Mode, and Figure 14.67 shows the Operating Example in Output Compare Mode. f4 f8 RCS1 to RCS0 = 00b = 01b f32 = 10b 1/2 4-bit counter RCS2 = 1 RCS6 to RCS5 = 00b f2 = 01b = 10b 8-bit counter RCS2 = 0 TOENA TREO pin TQ R = 11b Reset TRERST Comparison circuit Match signal COMIE Timer RE interrupt TRERST, TOENA: Bits in TRECR1 register COMIE: Bit in TRECR2 register RCS0 to RCS2, RCS5 to RCS6: Bits in TRECSR register TRESEC TREMIN Data bus Figure 14.61 Block Diagram of Output Compare Mode Table 14.25 Output Compare Mode Specifications Specification f4, f8, f32 • Increment • When the 8-bit counter content matches with the TREMIN register content, the value returns to 00h and count continues. The count value is held while count stops. Count period • When RCS2 = 0 (4-bit counter is not used) 1/fi x 2 x (n+1) • When RCS2 = 1 (4-bit counter is used) 1/fi x 32 x (n+1) fi: Frequency of count source n: Setting value of TREMIN register Count start condition 1 (count starts) is written to the TSTART bit in the TRECR1 register Count stop condition 0 (count stops) is written to the TSTART bit in the TRECR1 register Interrupt request generation timing When the 8-bit counter content matches with the TREMIN register content TREO pin function Select any one of the following: • Programmable I/O ports • Output f2, f4, or f8 • Compare output Read from timer When reading the TRESEC register, the 8-bit counter value can be read. When reading the TREMIN register, the compare value can be read. Write to timer Writing to the TRESEC register is disabled. When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer stops), writing to the TREMIN register is enabled. Select functions • Select use of 4-bit counter • Compare output function Every time the 8-bit counter value matches the TREMIN register value, TREO output polarity is reversed. The TREO pin outputs “L” after reset is deasserted and the timer RE is reset by the TRERST bit in the TRECR1 register. Output level is held by setting the TSTART bit to 0 (count stops). Item Count sources Count operations Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 202 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RE Counter Data Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRESEC Address 0118h Function After Reset 00h RW RO 8-bit counter data can be read. Although Timer RE stops counting, the count value is held. The TRESEC register is set to 00h at the compare match. Figure 14.62 TRESEC Register in Output Compare Mode Timer RE Compare Data Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TREMIN 8-bit compare data is stored. Address 0119h Function After Reset 00h RW RW Figure 14.63 TREMIN Register in Output Compare Mode Timer RE Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 00 0 Symbol Address 011Ch TRECR1 Bit Symbol Bit Name Nothing is assigned. If necessary, set to 0. — When read, the content is 0. (b0) TCSTF TOENA INT Timer RE count status flag TREO pin output enable bit Interrupt request timing bit Timer RE reset bit 0 : Count stopped 1 : Counting After Reset 00h Function RW — RO RW RW 0 : Disable clock output 1 : Enable clock output Set to 0 in output compare mode. When setting this bit to 0, after setting it to 1, the follow ing w ill occur. • Registers TRESEC, TREMIN, and TRECR2 are set to 00h. • Bits TCSTF, INT, and TSTART in the TRECR1 register are set to 0. • The 8-bit counter is set to 00h and the 4-bit counter is set to 0h. Set to 0. 0 : Count stops 1 : Count starts TRERST RW — (b6-b5) TSTART Reserved bits Timer RE count start bit RW RW Figure 14.64 TRECR1 Register in Output Compare Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 203 of 332 R8C/2E Group, R8C/2F Group 14. Timers Timer RE Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 00000 Symbol Address 011Dh TRECR2 Bit Symbol Bit Name — Reserved bits (b4-b0) COMIE — (b7-b6) Compare match interrupt enable bit After Reset 00h Function Set to 0. 0 : Disable compare match interrupt 1 : Enable compare match interrupt RW RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. Figure 14.65 TRECR2 Register in Output Compare Mode Timer RE Count Source Select Register b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol TRECSR Bit Symbol RCS0 Address 011Eh Bit Name Count source select bits After Reset 00001000b Function b1 b0 RW RW RCS1 4-bit counter select bit Reserved bit 0 0 : f4 0 1 : f8 1 0 : f32 1 1 : Do not set. RW RCS2 — (b3) — (b4) RCS5 0 : Not used 1 : Used Set to 0. RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. Clock output select bits (1) b6 b5 RCS6 — (b7) 0 0 : f2 0 1 : f4 1 0 : f8 1 1 : Compare output RW RW Nothing is assigned. If necessary, set to 0. When read, the content is 0. — NOTE: 1. Write to bits RCS5 to RCS6 w hen the TOENA bit in the TRECR1 register is set to 0 (disable clock output). Figure 14.66 TRECSR Register in Output Compare Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 204 of 332 R8C/2E Group, R8C/2F Group 14. Timers Count starts 8-bit counter content (hexadecimal number) TREMIN register setting value Matched Matched Matched 00h Set to 1 by a program Time TSTART bit in TRECR1 register 1 0 2 cycles of maximum count source TCSTF bit in TRECR1 register 1 0 Set to 0 by acknowledgement of interrupt request or a program IR bit in TREIC register 1 0 TREO output 1 0 Output polarity is inverted when the compare matches The above applies under the following conditions. TOENA bit in TRECR1 register = 1 (enable clock output) COMIE bit in TRECR2 register = 1 (enable compare match interrupt) RCS6 to RCS5 bits in TRECSR register = 11b (compare output) Figure 14.67 Operating Example in Output Compare Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 205 of 332 R8C/2E Group, R8C/2F Group 14. Timers 14.4.2 Notes on Timer RE Starting and Stopping Count 14.4.2.1 Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates count start or stop. Bits TSTART and TCSTF are in the TRECR1 register. Timer RE starts counting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to 1. During this time, do not access registers associated with timer RE(1) other than the TCSTF bit. Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0 (count stops). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF bit. NOTE: 1. Registers associated with timer RE: TRESEC, TREMIN, TRECR1, TRECR2, and TRECSR. 14.4.2.2 Register Setting Write to the following registers or bits when timer RE is stopped. • Registers TRESEC, TREMIN, and TRECR2 • INT bit in TRECR1 register • Bits RCS0 to RCS2 and b3 in TRECSR register Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped). Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the TRECR2 register. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 206 of 332 R8C/2E Group, R8C/2F Group 15. Serial Interface 15. Serial Interface The serial interface consists of one channel (UART0). UART0 has an exclusive timer to generate the transfer clock and operates. Figure 15.1 shows a UART0 Block Diagram. Figure 15.2 shows a UART0 Transmit/Receive Unit. UARTi has two modes: clock synchronous serial I/O mode and clock asynchronous serial I/O mode (UART mode). Figures 15.3 to 15.7 show the Registers Associated with UART0. (UART0) RXD0 CLK1 to CLK0 = 00b f1 f8 f32 = 01b = 10b TXD0 1/16 CKDIR = 0 Internal U0BRG register UART reception Clock synchronous type Reception control circuit Receive clock 1/(n0+1) External CKDIR = 1 1/16 UART transmission Clock synchronous type Transmission control circuit Transmit clock Transmit/ receive unit Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) Clock synchronous type (when internal clock is selected) 1/2 CKDIR = 0 CKDIR = 1 CLK0 CLK polarity switch circuit CLK1 to CLK0: Bits in U0C0 register CKDIR: Bit in U0MR register Figure 15.1 UART0 Block Diagram Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 207 of 332 R8C/2E Group, R8C/2F Group 15. Serial Interface 1SP PRYE = 0 Clock PAR disabled synchronous type Clock synchronous type UART (7 bits) UART (8 bits) UART (7 bits) UART0 receive register RXD0 SP 2SP SP PAR PAR UART enabled PRYE = 1 UART (9 bits) Clock synchronous type UART (8 bits) UART (9 bits) 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 U0RB register MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits MSB/LSB conversion circuit D8 D7 UART (8 bits) UART (9 bits) Clock synchronous type D6 D5 D4 D3 D2 D1 D0 U0TB register 2SP PRYE = 1 PAR enabled UART (9 bits) UART SP SP 1SP PAR Clock PAR disabled synchronous PRYE = 0 type 0 UART (7 bits) UART (8 bits) Clock synchronous type UART (7 bits) UART0 transmit register SP: Stop bit PAR: Parity bit PRYE: Bit in U0MR register TXD0 Figure 15.2 UART0 Transmit/Receive Unit Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 208 of 332 R8C/2E Group, R8C/2F Group 15. Serial Interface UART0 Transmit Buffer Register(1, 2) (b15) b7 (b8) b0 b7 b0 Symbol U0TB — (b8-b0) — (b15-b9) Transmit data Address 00A3h-00A2h Function After Reset Undefined RW WO — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. NOTES: 1. When the transfer data length is 9 bits, w rite data to high byte first, then low byte. 2. Use the MOV instruction to w rite to this register. UART0 Receive Buffer Register(1) (b15) b7 (b8) b0 b7 b0 Symbol U0RB Bit Symbol — (b7-b0) — (b8) — (b11-b9) OER FER PER SUM Address 00A7h-00A6h Bit Name — — After Reset Undefined Function Receive data (D7 to D0) Receive data (D8) RW RO RO — RO RO RO RO Nothing is assigned. If necessary, set to 0. When read, the content is undefined. Overrun error flag(2) Framing error flag(2) Parity error flag(2) Error sum flag(2) 0 : No overrun error 1 : Overrun error 0 : No framing error 1 : Framing error 0 : No parity error 1 : Parity error 0 : No error 1 : Error NOTES: 1. Read out the U0RB register in 16-bit units. 2. Bits SUM, PER, FER, and OER are set to 0 (no error) w hen bits SMD2 to SMD0 in the U0MR register are set to 000b (serial interface disabled) or the RE bit in the U0C1 register is set to 0 (receive disabled). The SUM bit is set to 0 (no error) w hen bits PER, FER, and OER are set to 0 (no error). Bits PER and FER are set to 0 even w hen the higher byte of the U0RB register is read out. Also, bits PER and FER are set to 0 w hen reading the high-order byte of the U0RB register. Figure 15.3 Registers U0TB and U0RB Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 209 of 332 R8C/2E Group, R8C/2F Group 15. Serial Interface UART0 Bit Rate Register(1, 2, 3) b7 b0 Address 00A1h Function Assuming the set value is n, U0BRG divides the count source by n+1 NOTES: 1. Write to this register w hile the serial I/O is neither transmitting nor receiving. 2. Use the MOV instruction to w rite to this register. 3. After setting the CLK0 to CLK1 bits of the U0C0 register, w rite to the U0BRG register. Symbol U0BRG After Reset Undefined Setting Range 00h to FFh RW WO UART0 Transmit/Receive Mode Register b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol U0MR Bit Symbol SMD0 Address 00A0h Bit Name Serial I/O mode select bits After Reset 00h Function b2 b1 b0 RW RW SMD1 SMD2 CKDIR STPS 0 0 0 : Serial interface disabled 0 0 1 : Clock synchronous serial I/O mode 1 0 0 : UART mode transfer data 7 bits long 1 0 1 : UART mode transfer data 8 bits long 1 1 0 : UART mode transfer data 9 bits long Other than above : Do not set Internal/external clock select bit 0 : Internal clock 1 : External clock(1) Stop bit length select bit Odd/even parity select bit 0 : 1 stop bit 1 : 2 stop bits Enable w hen PRYE = 1 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled Set to 0. RW RW RW RW PRY Parity enable bit Reserved bit RW PRYE — (b7) RW RW NOTE: 1. When the CLK0 pin is used, set the PD1_6 bit in the PD1 register to 0 (input). Figure 15.4 Registers U0BRG and U0MR Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 210 of 332 R8C/2E Group, R8C/2F Group 15. Serial Interface UART0 Transmit/Receive Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol U0C0 Bit Symbol CLK0 CLK1 — (b2) TXEPT — (b4) NCH Address 00A4h Bit Name BRG count source select b1 b0 bits (1) 0 0 : Selects f1 0 1 : Selects f8 1 0 : Selects f32 1 1 : Do not set. Reserved bit Transmit register empty flag Set to 0. After Reset 00001000b Function RW RW RW RW 0 : Data in transmit register (during transmit) 1 : No data in transmit register (transmit completed) RO Nothing is assigned. If necessary, set to 0. When read, the content is 0. Data output select bit CLK polarity select bit 0 : TXDi pin is for CMOS output 1 : TXDi pin is for N-channel open drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge — RW CKPOL RW UFORM Transfer format select bit 0 : LSB first 1 : MSB first RW NOTE: 1. If the BRG count source is sw itched, set the U0BRG register again. Figure 15.5 U0C0 Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 211 of 332 R8C/2E Group, R8C/2F Group 15. Serial Interface UART0 Transmit/Receive Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0C1 Bit Symbol TE TI RE RI U0IRS U0RRM — (b7-b6) Address 00A5h Bit Name Transmit enable bit(1) Transmit buffer empty flag Receive enable bit Receive complete flag(1) UART0 transmit interrupt cause select bit UART0 continuous receive mode enable bit(2) After Reset 00000010b Function 0 : Disables transmission 1 : Enables transmission 0 : Data in U0TB register 1 : No data in U0TB register 0 : Disables reception 1 : Enables reception 0 : No data in U0RB register 1 : Data in U0RB register 0 : Transmission buffer empty (TI=1) 1 : Transmission completed (TXEPT=1) 0 : Disables continuous receive mode 1 : Enables continuous receive mode RW RW RO RW RO RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. NOTES: 1. The RI bit is set to 0 w hen the higher byte of the U0RB register is read out. 2. Set the U0RRM bit to 0 (disables continuous receive mode) in UART mode. Figure 15.6 U0C1 Register Port Mode Register b7 b6 b5 b4 b3 b2 b1 b0 000 Symbol PMR Bit Symbol INT1SEL — (b3-b1) — (b6-b4) — (b7) Address 00F8h Bit Name ____ INT1 pin select bit After Reset 00h Function 0 : P1_5, P1_7 1 : P3_6 RW RW — RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. Reserved bits Set to 0. Nothing is assigned. If necessary, set to 0. When read, the content is 0. Figure 15.7 PMR Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 212 of 332 R8C/2E Group, R8C/2F Group 15. Serial Interface 15.1 Clock Synchronous Serial I/O Mode In the clock synchronous serial I/O mode, data is transmitted and received using a transfer clock. Table 15.1 lists the Specifications of Clock Synchronous Serial I/O Mode. Table 15.2 lists the Registers Used and Settings in Clock Synchronous Serial I/O Mode. Table 15.1 Specifications of Clock Synchronous Serial I/O Mode Specification • Transfer data length: 8 bits • CKDIR bit in U0MR register is set to 0 (internal clock): fi/(2(n+1)) fi = f1, f8, f32 n = value set in U0BRG register: 00h to FFh • The CKDIR bit is set to 1 (external clock): input from CLK0 pin • Before transmit starts, the following requirements must be met(1) - The TE bit in the U0C1 register is set to 1 (transmission enabled) - The TI bit in the U0C1 register is set to 0 (data in the U0TB register) • Before receive starts, the following requirements must be met(1) - The RE bit in the U0C1 register is set to 1 (reception enabled) - The TE bit in the U0C1 register is set to 1 (transmission enabled) - The TI bit in the U0C1 register is set to 0 (data in the U0TB register) • When transmitting, one of the following conditions can be selected - The U0IRS bit is set to 0 (transmit buffer empty): When transferring data from the U0TB register to UART0 transmit register (when transmission starts). - The U0IRS bit is set to 1 (transmission completes): When completing data transmission from UART0 transmit register. • When receiving When data transfer from the UART0 receive register to the U0RB register (when reception completes). • Overrun error(2) This error occurs if the serial interface starts receiving the next data item before reading the U0RB register and receives the 7th bit of the next data. • CLK polarity selection Transfer data input/output can be selected to occur synchronously with the rising or the falling edge of the transfer clock. • LSB first, MSB first selection Whether transmitting or receiving data begins with bit 0 or begins with bit 7 can be selected. • Continuous receive mode selection Receive is enabled immediately by reading the U0RB register. Item Transfer data format Transfer clocks Transmit start conditions Receive start conditions Interrupt request generation timing Error detection Select functions NOTES: 1. If an external clock is selected, ensure that the external clock is “H” when the CKPOL bit in the U0C0 register is set to 0 (transmit data output at falling edge and receive data input at rising edge of transfer clock), and that the external clock is “L” when the CKPOL bit is set to 1 (transmit data output at rising edge and receive data input at falling edge of transfer clock). 2. If an overrun error occurs, the receive data (b0 to b8) of the U0RB register will be undefined. The IR bit in the S0RIC register remains unchanged. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 213 of 332 R8C/2E Group, R8C/2F Group 15. Serial Interface Table 15.2 Register U0TB U0RB U0BRG U0MR U0C0 Registers Used and Settings in Clock Synchronous Serial I/O Mode(1) Bit 0 to 7 0 to 7 OER 0 to 7 SMD2 to SMD0 CKDIR CLK1 to CLK0 TXEPT NCH CKPOL UFORM TE TI RE RI U0IRS U0RRM Function Set data transmission Data reception can be read Overrun error flag Set bit rate Set to 001b U0C1 Select the internal clock or external clock Select the count source in the U0BRG register Transmit register empty flag Select TXD0 pin output mode Select the transfer clock polarity Select the LSB first or MSB first Set this bit to 1 to enable transmission/reception Transmit buffer empty flag Set this bit to 1 to enable reception Reception complete flag Select the UART0 transmit interrupt source Set this bit to 1 to use continuous receive mode NOTE: 1. Set bits which are not in this table to 0 when writing to the above registers in clock synchronous serial I/O mode. Table 15.3 lists the I/O Pin Functions in Clock Synchronous Serial I/O Mode. The TXD0 pin outputs “H” level between the operating mode selection of UART0 and transfer start. (If the NCH bit is set to 1 (N-channel opendrain output), this pin is in a high-impedance state.) Table 15.3 I/O Pin Functions in Clock Synchronous Serial I/O Mode Function Output serial data Input serial data Selection Method (Outputs dummy data when performing reception only) PD1_5 bit in PD1 register = 0 (P1_5 can be used as an input port when performing transmission only) CKDIR bit in U0MR register = 0 CKDIR bit in U0MR register = 1 PD1_6 bit in PD1 register = 0 Pin Name TXD0 (P1_4) RXD0 (P1_5) CLK0 (P1_6) Output transfer clock Input transfer clock Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 214 of 332 R8C/2E Group, R8C/2F Group 15. Serial Interface • Example of transmit timing (when internal clock is selected) TC Transfer clock TE bit in U0C1 register TI bit in U0C1 register 1 0 1 0 Set data in U0TB register Transfer from U0TB register to UART0 transmit register TCLK Stop pulsing because the TE bit is set to 0 CLK0 TXD0 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 TXEPT bit in U0C0 register 1 0 IR bit in S0TIC register 1 0 Set to 0 when interrupt request is acknowledged, or set by a program The above applies under the following settings: • CKDIR bit in U0MR register = 0 (internal clock) • CKPOL bit in U0C0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock) • U0IRS bit in U0C1 register = 0 (an interrupt request is generated when the transmit buffer is empty) TC = TCLK = 2(n+1)/fi fi: Frequency of U0BRG count source (f1, f8, f32) n: Setting value to U0BRG register • Example of receive timing (when external clock is selected) RE bit in U0C1 register TE bit in U0C1 register TI bit in U0C1 register 1 0 1 0 1 0 Transfer from U0TB register to UART0 transmit register 1/fEXT Write dummy data to U0TB register CLK0 Receive data is taken in RXD0 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 RI bit in U0C1 register 1 0 1 0 Transfer from UART0 receive register to U0RB register Read out from U0RB register IR bit in S0RIC register Set to 0 when interrupt request is acknowledged, or set by a program The above applies under the following settings: • CKDIR bit in U0MR register = 1 (external clock) • CKPOL bit in U0C0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock) The following conditions are met when “H” is applied to the CLK0 pin before receiving data: • TE bit in U0C1 register = 1 (enables transmit) • RE bit in U0C1 register = 1 (enables receive) • Write dummy data to the U0TB register fEXT: Frequency of external clock Figure 15.8 Transmit and Receive Timing Example in Clock Synchronous Serial I/O Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 215 of 332 R8C/2E Group, R8C/2F Group 15. Serial Interface 15.1.1 Polarity Select Function Figure 15.9 shows the Transfer Clock Polarity. Use the CKPOL bit in the U0C0 register to select the transfer clock polarity. • When the CKPOL bit in the U0C0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock) CLK0(1) TXD0 D0 D1 D2 D3 D4 D5 D6 D7 RXD0 D0 D1 D2 D3 D4 D5 D6 D7 • When the CKPOL bit in the U0C0 register = 1 (output transmit data at the rising edge and input receive data at the falling edge of the transfer clock) CLK0(2) TXD0 D0 D1 D2 D3 D4 D5 D6 D7 RXD0 D0 D1 D2 D3 D4 D5 D6 D7 NOTES: 1. When not transferring, the CLK0 pin level is “H”. 2. When not transferring, the CLK0 pin level is “L”. Figure 15.9 Transfer Clock Polarity 15.1.2 LSB First/MSB First Select Function Figure 15.10 shows the Transfer Format. Use the UFORM bit in the U0C0 register to select the transfer format. • When UFORM bit in U0C0 register = 0 (LSB first)(1) CLK0 TXD0 D0 D1 D2 D3 D4 D5 D6 D7 RXD0 D0 D1 D2 D3 D4 D5 D6 D7 • When UFORM bit in U0C0 register = 1 (MSB first)(1) CLK0 TXD0 D7 D6 D5 D4 D3 D2 D1 D0 RXD0 D7 D6 D5 D4 D3 D2 D1 D0 NOTE: 1. The above applies when the CKPOL bit in the U0C0 register is set to 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock). Figure 15.10 Transfer Format Page 216 of 332 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 R8C/2E Group, R8C/2F Group 15. Serial Interface 15.1.3 Continuous Receive Mode Continuous receive mode is selected by setting the U0RRM bit in the U0C1 register to 1 (enables continuous receive mode). In this mode, reading the U0RB register sets the TI bit in the U0C1 register to 0 (data in the U0TB register). When the U0RRM bit is set to 1, do not write dummy data to the U0TB register by a program. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 217 of 332 R8C/2E Group, R8C/2F Group 15. Serial Interface 15.2 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows data transmission and reception after setting the desired bit rate and transfer data format. Table 15.4 lists the Specifications of UART Mode. Table 15.5 lists the Registers Used and Settings for UART Mode. Table 15.4 Specifications of UART Mode Specification • Character bit (transfer data): Selectable among 7, 8 or 9 bits • Start bit: 1 bit • Parity bit: Selectable among odd, even, or none • Stop bit: Selectable among 1 or 2 bits • CKDIR bit in U0MR register is set to 0 (internal clock): fj/(16(n+1)) fj = f1, f8, f32 n = value set in U0BRG register: 00h to FFh • CKDIR bit is set to 1 (external clock): fEXT/(16(n+1)) fEXT: Input from CLK0 pin, n = value set in U0BRG register: 00h to FFh • Before transmission starts, the following are required - TE bit in U0C1 register is set to 1 (transmission enabled) - TI bit in U0C1 register is set to 0 (data in U0TB register) • Before reception starts, the following are required - RE bit in U0C1 register is set to 1 (reception enabled) - Start bit detected • When transmitting, one of the following conditions can be selected - U0IRS bit is set to 0 (transmit buffer empty): When transferring data from the U0TB register to UART0 transmit register (when transmit starts). - U0IRS bit is set to 1 (transfer ends): When serial interfac.e completes transmitting data from the UART0 transmit register • When receiving When transferring data from the UART0 receive register to U0RB register (when receive ends). • Overrun error(1) This error occurs if the serial interface starts receiving the next data item before reading the U0RB register and receive the bit preceding the final stop bit of the next data item. • Framing error This error occurs when the set number of stop bits is not detected. • Parity error This error occurs when parity is enabled, and the number of 1’s in parity and character bits do not match the number of 1’s set. • Error sum flag This flag is set is set to 1 when an overrun, framing, or parity error is generated. Item Transfer data formats Transfer clocks Transmit start conditions Receive start conditions Interrupt request generation timing Error detection NOTE: 1. If an overrun error occurs, the receive data (b0 to b8) of the U0RB register will be undefined. The IR bit in the S0RIC register remains unchanged. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 218 of 332 R8C/2E Group, R8C/2F Group 15. Serial Interface Table 15.5 Register U0TB U0RB U0BRG U0MR Registers Used and Settings for UART Mode Bit 0 to 8 0 to 8 OER,FER,PER,SUM 0 to 7 SMD2 to SMD0 Set transmit data(1) Function Receive data can be read(1, 2) Error flag Set a bit rate Set to 100b when transfer data is 7 bits long. Set to 101b when transfer data is 8 bits long. Set to 110b when transfer data is 9 bits long. Select the internal clock or external clock Select the stop bit Select whether parity is included and whether odd or even Select the count source for the U0BRG register Transmit register empty flag Select TXD0 pin output mode Set to 0 LSB first or MSB first can be selected when transfer data is 8 bits long. Set to 0 when transfer data is 7 or 9 bits long. Set to 1 to enable transmit Transmit buffer empty flag Set to 1 to enable receive Receive complete flag Select the factor of UART0 transmit interrupt Set to 0 U0C0 CKDIR STPS PRY, PRYE CLK0, CLK1 TXEPT NCH CKPOL UFORM TE TI RE RI U0IRS U0RRM U0C1 NOTES: 1. The bits used for transmit/receive data are as follows: Bits 0 to 6 when transfer data is 7 bits long; bits 0 to 7 when transfer data is 8 bits long; bits 0 to 8 when transfer data is 9 bits long. 2. The following bits are undefined: Bits 7 and 8 when transfer data is 7 bits long; bit 8 when transfer data is 8 bits long. Table 15.6 lists the I/O Pin Functions in UART Mode. After the UART0 operating mode is selected, the TXD0 pin outputs “H” level (If the NCH bit is set to 1 (N-channel open-drain output), this pin is in a high-impedance state) until transfer starts. Table 15.6 I/O Pin Functions in UART Mode Pin name Function TXD0 (P1_4) Output serial data RXD0 (P1_5) Input serial data Selection Method (Cannot be used as a port when performing reception only) PD1_5 bit in PD1 register = 0 (P1_5 can be used as an input port when performing transmission only) CLK0 (P1_6) Programmable I/O Port CKDIR bit in U0MR register = 0 Input transfer clock CKDIR bit in U0MR register = 1 PD1_6 bit in PD1 register = 0 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 219 of 332 R8C/2E Group, R8C/2F Group 15. Serial Interface • Transmit timing when transfer data is 8 bits long (parity enabled, 1 stop bit) TC Transfer clock TE bit in U0C1 register TI bit in U0C1 register 1 0 Write data to U0TB register 1 0 Transfer from U0TB register to UART0 transmit register Start bit Parity Stop bit bit Stop pulsing because the TE bit is set to 0 TXD0 ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 TXEPT bit U0C0 register 1 0 IR bit in S0TIC register 1 0 Set to 0 when interrupt request is acknowledged, or set by a program TC=16 (n + 1) / fj or 16 (n + 1) / fEXT The above timing diagram applies under the following conditions: • PRYE bit in U0MR register = 1 (parity enabled) fj: Frequency of U0BRG count source (f1, f8, f32) • STPS bit in U0MR register = 0 (1 stop bit) fEXT: Frequency of U0BRG count source (external clock) • U0IRS bit in U0C1 register = 1 (an interrupt request is generated when transmit completes) n: Setting value to U0BRG register • Transmit timing when transfer data is 9 bits long (parity disabled, 2 stop bits) TC Transfer clock TE bit in U0C1 register TI bit in U0C1 register 1 0 Write data to U0TB register 1 0 Transfer from U0TB register to UART0 transmit register Start bit Stop Stop bit bit TXD0 ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 TXEPT bit in U0C0 register 1 0 IR bit in S0TIC register 1 0 Set to 0 when interrupt request is acknowledged, or set by a program The above timing diagram applies under the following conditions: TC=16 (n + 1) / fj or 16 (n + 1) / fEXT • PRYE bit in U0MR register = 0 (parity disabled) fj: Frequency of U0BRG count source (f1, f8, f32) • STPS bit in U0MR register = 1 (2 stop bits) fEXT: Frequency of U0BRG count source (external clock) • U0IRS bit in U0C1 register = 0 (an interrupt request is generated when transmit buffer is empty) n: Setting value to U0BRG register Figure 15.11 Transmit Timing in UART Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 220 of 332 R8C/2E Group, R8C/2F Group 15. Serial Interface • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) U0BRG output RE bit in U0C1 register RXD0 1 0 Stop bit Start bit D0 D1 D7 Determined to be “L” Receive data taken in Transfer clock Reception triggered when transfer clock is generated by falling edge of start bit RI bit in U0C1 register IR bit in S0RIC register 1 0 1 0 Transferred from UART0 receive register to U0RB register Set to 0 when interrupt request is accepted, or set by a program The above timing diagram applies when the register bits are set as follows: • PRYE bit in U0MR register = 0 (parity disabled) • STPS bit in U0MR register = 0 (1 stop bit) Figure 15.12 Receive Timing Example in UART Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 221 of 332 R8C/2E Group, R8C/2F Group 15. Serial Interface 15.2.1 Bit Rate In UART mode, the bit rate is the frequency divided by the U0BRG register. Figure 15.13 shows a Calculation Formula of U0BRG Register Setting Value. Table 15.7 lists the Bit Rate Setting Example in UART Mode (Internal Clock Selected). UART mode • Internal clock selected U0BRG register setting value = fj Bit Rate × 6 1 -1 fj: Count source frequency of the U0BRG register (f1, f8, or f32) • External clock selected U0BRG register setting value = fEXT Bit Rate × 6 1 -1 fEXT: Count source frequency of the U0BRG register (external clock) Figure 15.13 Calculation Formula of U0BRG Register Setting Value Table 15.7 Bit Rate (bps) 1200 2400 4800 9600 14400 19200 28800 31250 38400 51200 Bit Rate Setting Example in UART Mode (Internal Clock Selected) BRG Count Source f8 f8 f8 f1 f1 f1 f1 f1 f1 f1 System Clock = 20 MHz System Clock = 8 MHz U0BRG Actual Time U0BRG Actual Error (%) Error (%) Setting Value (bps) Setting Value Time (bps) 129 (81h) 1201.92 0.16 51 (33h) 1201.92 0.16 64 (40h) 2403.85 0.16 25 (19h) 2403.85 0.16 32 (20h) 4734.85 -1.36 12 (0Ch) 4807.69 0.16 129 (81h) 9615.38 0.16 51 (33h) 9615.38 0.16 86 (56h) 14367.82 -0.22 34 (22h) 14285.71 -0.79 64 (40h) 19230.77 0.16 25 (19h) 19230.77 0.16 42 (2Ah) 29069.77 0.94 16 (10h) 29411.76 2.12 39 (27h) 31250.00 0.00 15 (0Fh) 31250.00 0.00 32 (20h) 37878.79 -1.36 12 (0Ch) 38461.54 0.16 23 (17h) 52083.33 1.73 9 (09h) 50000.00 -2.34 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 222 of 332 R8C/2E Group, R8C/2F Group 15. Serial Interface 15.3 Notes on Serial Interface • When reading data from the U0RB register either in the clock synchronous serial I/O mode or in the clock asynchronous serial I/O mode, ensure the data is read in 16-bit units. When the high-order byte of the U0RB register is read, bits PER and FER in the U0RB register and the RI bit in the U0C1 register are set to 0. The check receive errors, read the U0RB register and then use the read data. Example (when reading receive buffer register): MOV.W 00A6H,R0 ; Read the U0RB register • When writing data to the U0TB register in the clock asynchronous serial I/O mode with 9-bit transfer data length, write data to the high-order byte first then the low-order byte, in 8-bit units. Example (when reading transmit buffer register): MOV.B #XXH,00A3H ; Write the high-order byte of U0TB register MOV.B #XXH,00A2H ; Write the low-order byte of U0TB register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 223 of 332 R8C/2E Group, R8C/2F Group 16. Hardware LIN 16. Hardware LIN The hardware LIN performs LIN communication in cooperation with timer RA and UART0. 16.1 Features The hardware LIN has the features listed below. Figure 16.1 shows a Block Diagram of Hardware LIN. Master mode • Generates Synch Break • Detects bus collision Slave mode • Detects Synch Break • Measures Synch Field • Controls Synch Break and Synch Field signal inputs to UART0 • Detects bus collision NOTE: 1. The WakeUp function is detected by INT1. Hardware LIN RXD0 pin Synch Field control circuit TIOSEL = 0 RXD data LSTART bit SBE bit LINE bit RXD0 input control circuit TIOSEL = 1 Interrupt control circuit UART0 Bits BCIE, SBIE, and SFIE UART0 transfer clock UART0 TE bit Timer RA output pulse MST bit TXD0 pin LINE, MST, SBE, LSTART, BCIE, SBIE, SFIE: Bits in LINCR register TIOSEL: Bit in TRAIOC register TE: Bit in U0C1 register UART0 TXD data Timer RA underflow signal Timer RA interrupt Timer RA Bus collision detection circuit Figure 16.1 Block Diagram of Hardware LIN Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 224 of 332 R8C/2E Group, R8C/2F Group 16. Hardware LIN 16.2 Input/Output Pins The pin configuration of the hardware LIN is listed in Table 16.1. Table 16.1 Pin Configuration Abbreviation Input/Output Function RXD0 Input Receive data input pin of the hardware LIN TXD0 Output Transmit data output pin of the hardware LIN Name Receive data input Transmit data output Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 225 of 332 R8C/2E Group, R8C/2F Group 16. Hardware LIN 16.3 Register Configuration The hardware LIN contains the registers listed below. These registers are detailed in Figures 16.2 and 16.3. • LIN Control Register (LINCR) • LIN Status Register (LINST) LIN Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol LINCR Bit Symbol SFIE Address 0106h Bit Name Synch Field measurementcompleted interrupt enable bit After Reset 00h Function 0 : Disables Synch Field measurementcompleted interrupt 1 : Enables Synch Field measurementcompleted interrupt RW RW SBIE BCIE RXDSF Synch Break detection interrupt 0 : Disables Synch Break detection interrupt 1 : Enables Synch Break detection interrupt enable bit Bus collision detection interrupt 0 : Disables bus collision detection interrupt 1 : Enables bus collision detection interrupt enable bit RXD0 input status flag 0 : RXD0 input enabled 1 : RXD0 input disabled RW RW RO LSTART Synch Break detection start bit(1) When this bit is set to 1, timer RA input is enabled and RXD0 input is disabled. When read, the content is 0. 0 : Unmasked after Synch Break is detected RXD0 input unmasking timing select bit (effective only in slave 1 : Unmasked after Synch Field measurement is completed mode) LIN operation mode setting bit(2) 0 : Slave mode (Synch Break detection circuit actuated) 1 : Master mode (timer RA output OR’ed w ith TXD0) 0 : Causes LIN to stop 1 : Causes LIN to start operating(3) RW SBE RW MST RW LINE LIN operation start bit RW NOTES: 1. After setting the LSTART bit, confirm that the RXDSF flag is set to 1 before Synch Break input starts. 2. Before changing LIN operation modes, temporarily stop the LIN operation (LINE bit = 0). 3. Inputs to timer RA and UART0 are prohibited immediately after this bit is set to 1. (Refer to Figure 16.5 Exam ple of Header Field Transm ission Flow chart (1) and Figure 16.9 Exam ple of Header Field Reception Flow chart (2) .) Figure 16.2 LINCR Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 226 of 332 R8C/2E Group, R8C/2F Group 16. Hardware LIN LIN Status Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol LINST Bit Symbol SFDCT SBDCT BCDCT B0CLR B1CLR B2CLR — (b7-b6) Address 0107h Bit Name Synch Field measurementcompleted flag Synch Break detection flag Bus collision detection flag SFDCT bit clear bit SBDCT bit clear bit BCDCT bit clear bit After Reset 00h Function 1 show s Synch Field measurement completed. 1 show s Synch Break detected or Synch Break generation completed. 1 show s Bus collision detected. When this bit is set to 1, the SFDCT bit is set to 0. When read, the content is 0. When this bit is set to 1, the SBDCT bit is set to 0. When read, the content is 0. When this bit is set to 1, the BCDCT bit is set to 0. When read, the content is 0. RW RO RO RO RW RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. Figure 16.3 LINST Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 227 of 332 R8C/2E Group, R8C/2F Group 16. Hardware LIN 16.4 16.4.1 Functional Description Master Mode Figure 16.4 shows typical operation of the hardware LIN when transmitting a header field in master mode. Figures 16.5 and 16.6 show an Example of Header Field Transmission Flowchart. When transmitting a header field, the hardware LIN operates as described below. (1) When the TSTART bit in the TRACR register for timer RA is set by writing 1 in software, the hardware LIN outputs “L” level from the TXD0 pin for the period that is set in registers TRAPRE and TRA for timer RA. (2) When timer RA underflows upon reaching the terminal count, the hardware LIN reverses the output of the TXD0 pin and sets the SBDCT flag in the LINST register to 1. Furthermore, if the SBIE bit in the LINCR register is set to 1, it generates a timer RA interrupt. (3) The hardware LIN transmits 55h via UART0. (4) The hardware LIN transmits an ID field via UART0 after it finishes sending 55h. (5) The hardware LIN performs communication for a response field after it finishes sending the ID field. Synch Break Synch Field IDENTIFIER TXD0 pin 1 0 1 0 1 0 (1) (2) (3) Set by writing 1 to the B1CLR bit in the LINST register Cleared to 0 upon acceptance of interrupt request or by a program SBDCT flag in LINST register IR bit in TRAIC register (4) (5) The above applies under the following conditions. LINE = 1, MST = 1, SBIE = 1 LINE, MST, SBIE: Bits in LINCR register Figure 16.4 Typical Operation when Sending a Header Field Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 228 of 332 R8C/2E Group, R8C/2F Group 16. Hardware LIN Timer RA Set to timer mode Bits TMOD0 to TMOD2 in TRAMR register ← 000b Timer RA Set the pulse output level from low to start TEDGSEL bit in TRAIOC register ← 1 Timer RA Set the INT1/TRAIO pin to P1_5 TIOSEL bit in TRAIOC register ← 1 Timer RA Set the count source (f1, f2, f8, fOCO) Bits TCK0 to TCK2 in TRAMR register Timer RA Set the Synch Break width TRAPRE register TRA register UART0 Set to transmit/receive mode (Transfer data length: 8 bits, Internal clock, 1 stop bit, Parity disabled) U0MR register Set the BRG count source (f1, f8, f32) Bits CLK0 to CLK2 in U0C0 register Set the bit rate U0BRG register For the hardware LIN function, set the TIOSEL bit in the TRAIOC register to 1. Set the count source and registers TRA and TRAPRE as suitable for the Synch Break period. UART0 UART0 Set the BRG count source and U0BRG register as appropriate for the bit rate. Hardware LIN Set the LIN operation to stop LINCR register LINE bit ← 0 Hardware LIN Set to master mode MST bit in LINCR register ← 1 Hardware LIN Set the LIN operation to start LINE bit in LINCR register ← 1 Hardware LIN Set the register to enable interrupts (Bus collision detection, Synch Break detection, Synch Field measurement) Bits BCIE, SBIE, SFIE in LINCR register Hardware LIN Clear the status flags (Bus collision detection, Synch Break detection, Synch Field measurement) Bits B2CLR, B1CLR, B0CLR in LINST register ← 1 During master mode, the Synch Field measurementcompleted interrupt cannot be used. A Figure 16.5 Example of Header Field Transmission Flowchart (1) Page 229 of 332 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 R8C/2E Group, R8C/2F Group 16. Hardware LIN A Timer RA Set the timer to start counting TSTART bit in TRACR register ← 1 Timer RA Read the count status flag TCSTF flag in TRACR register NO Timer RA generates Synch Break. If registers TRAPRE and TRA for timer RA do not need to be read or the register settings do not need to be changed after writing 1 to the TSTART bit, the procedure for reading TCSTF flag = 1 can be omitted. Zero to one cycle of the timer RA count source is required after timer RA starts counting before the TCSTF flag is set to 1. The timer RA interrupt may be used to terminate generation of Synch Break. Three to five cycles of the CPU clock are required after Synch Break generation completes before the SBDCT flag is set to 1. After timer RA Synch Break is generated, the timer should be made to stop counting. If registers TRAPRE and TRA for timer RA do not need to be read or the register settings do not need to be changed after writing 0 to the TSTART bit, the procedure for reading TCSTF flag = 0 can be omitted. Zero to one cycle of the timer RA count source is required after timer RA stops counting before the TCSTF flag is set to 0. Transmit the Synch Field. TCSTF = 1 ? YES Hardware LIN Read the Synch Break detection flag SBDCT flag in LINST register NO SBDCT = 1 ? YES Timer RA Set the timer to stop counting TSTART bit in TRACR register ← 0 Timer RA Read the count status flag TCSTF flag in TRACR register NO TCSTF = 0 ? YES UART0 Communication via UART0 TE bit in U0C1 register ← 1 U0TB register ← 0055h UART0 Communication via UART0 U0TB register ← ID field Transmit the ID field. Figure 16.6 Example of Header Field Transmission Flowchart (2) Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 230 of 332 R8C/2E Group, R8C/2F Group 16. Hardware LIN 16.4.2 Slave Mode Figure 16.7 shows typical operation of the hardware LIN when receiving a header field in slave mode. Figure 16.8 through Figure 16.10 show an Example of Header Field Transmission Flowchart. When receiving a header field, the hardware LIN operates as described below. (1) Synch Break detection is enabled by writing 1 to the LSTART bit in the LINCR register of the hardware LIN. (2) When “L” level is input for a duration equal to or greater than the period set in timer RA, the hardware LIN detects it as Synch Break. At this time, the SBDCT flag in the LINST register is set to 1. Furthermore, if the SBIE bit in the LINCR register is set to 1, the hardware LIN generates a timer RA interrupt. Then it goes to Synch Field measurement. (3) The hardware LIN receives a Synch Field (55h). At this time, it measures the period of the start bit and bits 0 to 6 by using timer RA. In this case, it is possible to select whether to input the Synch Field signal to RXD0 of UART0 by setting the SBE bit in the LINCR register accordingly. (4) The hardware LIN sets the SFDCT flag in the LINST register to 1 when it finishes measuring the Synch Field. Furthermore, if the SFIE bit in the LINCR register is set to 1, it generates a timer RA interrupt. (5) After it finishes measuring the Synch Field, calculate a transfer rate from the count value of timer RA and set to UART0 and registers TRAPRE and TRA of timer RA again. Then it receives an ID field via UART0. (6) The hardware LIN performs communication for a response field after it finishes receiving the ID field. Synch Break Synch Field IDENTIFIER RXD0 pin 1 0 1 0 1 0 1 0 1 0 1 0 (1) (2) (3) RXD0 input for UART0 RXDSF flag in LINCR register SBDCT flag in LINST register SFDCT flag in LINST register IR bit in TRAIC register Set by writing 1 to the LSTART bit in the LINCR register Set by writing 1 to the B1CLR bit in the LINST register Measure this period Cleared to 0 when Synch Field measurement finishes Set by writing 1 to the B0CLR bit in the LINST register Cleared to 0 upon acceptance of interrupt request or by a program (4) (5) (6) The above applies under the following conditions. LINE = 1, MST = 0, SBE = 1, SBIE = 1, SFIE = 1 LINE, MST, SBE, SBIE, SFIE: Bits in LINCR register Figure 16.7 Typical Operation when Receiving a Header Field Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 231 of 332 R8C/2E Group, R8C/2F Group 16. Hardware LIN Timer RA Set to pulse width measurement mode Bits TMOD0 to TMOD2 in the TRAMR register ← 011b Timer RA Set the pulse width measurement level low TEDGSEL bit in the TRAIOC register ← 0 Timer RA Set the INT1/TRAIO pin to P1_5 TIOSEL bit in the TRAIOC register ← 1 Timer RA Set the count source (f1, f2, f8, fOCO) Bits TCK0 to TCK2 in the TRAMR register Timer RA Set the Synch Break width TRAPRE register TRA register Hardware LIN Set the LIN operation to stop LINE bit in the LINCR register ← 0 Hardware LIN Set to slave mode MST bit in the LINCR register ← 0 Hardware LIN Set the LIN operation to start LINE bit in the LINCR register ← 1 Hardware LIN Set the RXD0 input unmasking timing (After Synch Break detection, or after Synch Field measurement) SBE bit in the LINCR register Select the timing at which to unmask the RXD0 input for UART0. If the RXD0 input is chosen to be unmasked after detection of Synch Break, the Synch Field signal is also input to UART0. Set the count source and registers TRA and TRAPRE as appropriate for the Synch Break period. For the hardware LIN function, set the TIOSEL bit in the TRAIOC register to 1. Hardware LIN Set the register to enable interrupts (Bus collision detection, Synch Break detection, Synch Field measurement) Bits BCIE, SBIE, SFIE in the LINCR register A Figure 16.8 Example of Header Field Reception Flowchart (1) Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 232 of 332 R8C/2E Group, R8C/2F Group 16. Hardware LIN A Hardware LIN Clear the status flags (Bus collision detection, Synch Break detection, Synch Field measurement) Bits B2CLR, B1CLR, B0CLR in the LINST register ← 1 Timer RA Set to start a pulse width measurement TSTART bit in the TRACR register ← 1 Timer RA Read the count status flag TCSTF flag in the TRACR register NO Zero to one cycle of the timer RA count source is required after timer RA starts counting before the TCSTF flag is set to 1. Hardware LIN waits until the RXD0 input for UART0 is masked. Do not apply “L” level to the RXD pin until the RXDSF flag reads 1 after writing 1 to the LSTART bit. This is because the signal applied during this time is input directly to UART0. Three to five cycles of the CPU clock are required after the LSTART bit is set to 1 before the RXDSF flag is set to 1. After this, input to timer RA and UART0 is enabled. Hardware LIN detects a Synch Break. The interrupt of the timer RA may be used. When Synch Break is detected, timer RA is reloaded with the initially set count value. Even if the duration of the input “L” level is shorter than the set period, timer RA is reloaded with the initially set count value and waits until the next “L” level is input. Three to five cycles of the CPU clock are required after Synch Break detection before the SBDCT flag is set to 1. When the SBE bit in the LINCR register is set to 0 (unmasked after Synch Break is detected), timer RA can be used in timer mode after the SBDCT flag in the LINST register is set to 1 and the RXDSF flag is set to 0. Timer RA waits until the timer starts counting. TCSTF = 1 ? YES Hardware LIN Set to start Synch Break detection LSTART bit in the LINCR register ← 1 Hardware LIN Read the RXD0 input status flag RXDSF flag in the LINCR register NO RXDSF = 1 ? YES Hardware LIN Read the Synch Break detection flag SBDCT flag in the LINST register NO SBDCT = 1 ? YES B Figure 16.9 Example of Header Field Reception Flowchart (2) Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 233 of 332 R8C/2E Group, R8C/2F Group 16. Hardware LIN B YES Hardware LIN Read the Synch Field measurementcompleted flag SFDCT flag in the LINST register NO SFDCT = 1 ? YES Hardware LIN measures the Synch Field. The interrupt of timer RA may be used (the SBDCT flag is set when the timer RA counter underflows upon reaching the terminal count). When the SBE bit in the LINCR register is set to 1 (unmasked after Synch Field measurement is completed), timer RA may be used in timer mode after the SFDCT bit in the LINST register is set to 1. UART0 Set the UART0 communication rate U0BRG register Timer RA Set the Synch Break width again TRAPRE register TRA register UART0 Communication via UART0 Clock asynchronous serial interface (UART) mode Transmit ID field Set a communication rate based on the Synch Field measurement result. Communication via UART0 (The SBDCT flag is set when the timer RA counter underflows upon reaching the terminal count.) Figure 16.10 Example of Header Field Reception Flowchart (3) Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 234 of 332 R8C/2E Group, R8C/2F Group 16. Hardware LIN 16.4.3 Bus Collision Detection Function The bus collision detection function can be used when UART0 is enabled for transmission (TE bit in the U0C1 register = 1). Figure 16.11 shows Typical Operation when a Bus Collision is Detected. TXD0 pin 1 0 1 0 1 0 Set to 1 by a program RXD0 pin Transfer clock LINE bit in the LINCR register TE bit in the U0C1 register BCDCT flag in the LINST register 1 0 Set to 1 by a program 1 0 1 0 Set by writing 1 to the B2CLR bit in the LINST register Cleared to 0 upon acceptance of interrupt request or by a program IR bit in the TRAIC register 1 0 Figure 16.11 Typical Operation when a Bus Collision is Detected Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 235 of 332 R8C/2E Group, R8C/2F Group 16. Hardware LIN 16.4.4 Hardware LIN End Processing Figure 16.12 shows an Example of Hardware LIN Communication Completion Flowchart. Use the following timing for hardware LIN end processing: • If the hardware bus collision detection function is used Perform hardware LIN end processing after checksum transmission completes. • If the bus collision detection function is not used Perform hardware LIN end processing after header field transmission and reception complete. Timer RA Set the timer to stop counting TSTART bit in TRACR register ← 0 Read the count status flag TCSTF flag in TRACR register NO Set the timer to stop counting. Zero to one cycle of the timer RA count source is required after timer RA starts counting before the TCSTF flag is set to 1. Timer RA TCSTF = 0 ? YES UART0 Complete transmission via UART0 When the bus collision detection function is not used, end processing for the UART0 transmission is not required. Hardware LIN Clear the status flags (Bus collision detection, Synch Break detection, Synch Field measurement) Bits B2CLR, B1CLR, B0CLR in the LINST register ← 1 Hardware LIN Set the LIN operation to stop LINE bit in the LINCR register ← 0 After clearing hardware LIN status flag, stop the hardware LIN operation. Figure 16.12 Example of Hardware LIN Communication Completion Flowchart Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 236 of 332 R8C/2E Group, R8C/2F Group 16. Hardware LIN 16.5 Interrupt Requests There are four interrupt requests that are generated by the hardware LIN: Synch Break detection, Synch Break generation completed, Synch Field measurement completed, and bus collision detection. These interrupts are shared with timer RA. Table 16.2 lists the Interrupt Requests of Hardware LIN. Table 16.2 Interrupt Requests of Hardware LIN Status Flag Cause of Interrupt Generated when timer RA has underflowed after measuring the “L” level duration of RXD0 input, or when a “L” level is input for a duration longer than the Synch Break period during communication. Generated when “L” level output to TXD0 for the duration set by timer RA completes. Generated when measurement for 6 bits of the Synch Field by timer RA is completed. Generated when the RXD0 input and TXD0 output values differed at data latch timing while UART0 is enabled for transmission. Interrupt Request Synch Break detection SBDCT Synch Break generation completed Synch Field measurement completed Bus collision detection SFDCT BCDCT Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 237 of 332 R8C/2E Group, R8C/2F Group 16. Hardware LIN 16.6 Notes on Hardware LIN For the time-out processing of the header and response fields, use another timer to measure the duration of time with a Synch Break detection interrupt as the starting point. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 238 of 332 R8C/2E Group, R8C/2F Group 17. A/D Converter 17. A/D Converter The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling amplifier. The analog input shares pins P0_0 to P0_7, and P1_0 to P1_3. Therefore, when using these pins, ensure that the corresponding port direction bits are set to 0 (input mode). When not using the A/D converter, set the VCUT bit in the ADCON1 register to 0 (Vref unconnected) so that no current will flow from the VREF pin into the resistor ladder. This helps to reduce the power consumption of the chip. The result of A/D conversion is stored in the AD register. Table 17.1 lists the Performance of A/D converter. Figure 17.1 shows a Block Diagram of A/D Converter. Figures 17.2 and 17.3 show the A/D converter-related registers. Table 17.1 Performance of A/D converter Performance Successive approximation (with capacitive coupling amplifier) 0 V to AVCC 4.2 V ≤ AVCC ≤ 5.5 V f1, f2, f4, fOCO-F 2.7 V ≤ AVCC < 4.2 V f2, f4, fOCO-F 8 bits or 10 bits selectable AVCC = Vref = 5 V, φAD = 10 MHz • 8-bit resolution ±2 LSB • 10-bit resolution ±3 LSB AVCC = Vref = 3.3 V, φAD = 10 MHz • 8-bit resolution ±2 LSB • 10-bit resolution ±5 LSB One-shot and repeat(3) 12 pins (AN0 to AN11) Software trigger Set the ADST bit in the ADCON0 register to 1 (A/D conversion starts) • Without sample and hold function 8-bit resolution: 49φAD cycles, 10-bit resolution: 59φAD cycles • With sample and hold function 8-bit resolution: 28φAD cycles, 10-bit resolution: 33φAD cycles Item A/D conversion method Analog input voltage(1) Operating clock φAD(2) Resolution Absolute accuracy Operating mode Analog input pin A/D conversion start condition Conversion rate per pin NOTES: 1. The analog input voltage does not depend on use of a sample and hold function. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in 8-bit mode. 2. When 2.7 V ≤ AVCC ≤ 5.5 V, the frequency of φAD must be 10 MHz or below. Without a sample and hold function, the φAD frequency should be 250 kHz or above. With a sample and hold function, the φAD frequency should be 1 MHz or above. 3. In repeat mode, only 8-bit mode can be used. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 239 of 332 R8C/2E Group, R8C/2F Group 17. A/D Converter fOCO-F f1 CKS0 = 1 A/D conversion rate selection CKS1 = 1 CKS0 = 0 CKS0 = 1 f2 f4 CKS0 = 0 VCUT = 0 CKS1 = 0 φAD AVSS VREF VCUT = 1 Resistor ladder Successive conversion register ADCON0 Vcom AD register Decoder Comparator Data bus VIN P0_7/AN0 P0_6/AN1 P0_5/AN2 P0_4/AN3 P0_3/AN4 P0_2/AN5 P0_1/AN6 P0_0/AN7 CH2 to CH0 = 000b CH2 to CH0 = 001b CH2 to CH0 = 010b CH2 to CH0 = 011b CH2 to CH0 = 100b CH2 to CH0 = 101b CH2 to CH0 = 110b CH2 to CH0 = 111b ADGSEL0 = 0 ADGSEL0 = 1 P1_0/AN8 P1_1/AN9 P1_2/AN10 P1_3/AN11 CH2 to CH0 = 100b CH2 to CH0 = 101b CH2 to CH0 = 110b CH2 to CH0 = 111b CH0 to CH2, ADGSEL0, CKS0: Bits in ADCON0 register CKS1, VCUT: Bits in ADCON1 register Figure 17.1 Block Diagram of A/D Converter Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 240 of 332 R8C/2E Group, R8C/2F Group 17. A/D Converter A/D Control Register 0(1) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol ADCON0 Bit Symbol CH0 CH1 CH2 MD ADGSEL0 — (b5) ADST Address 00D6h Bit Name Analog input pin select bits (Note 4) After Reset 00h Function RW RW RW RW A/D operating mode select 0 : One-shot mode bit(2) 1 : Repeat mode A/D input group select bit(4) 0 : Selects port P0 group (AN0 to AN7) 1 : Selects port P1 group (AN8 to AN11) Reserved bit A/D conversion start flag Frequency select bit 0 Set to 0. 0 : Stops A/D conversion 1 : Starts A/D conversion [When CKS1 in ADCON1 register = 0] 0 : Select f4 1 : Select f2 [When CKS1 in ADCON1 register = 1] 0 : Select f1(3) 1 : Select fOCO-F RW RW RW RW CKS0 RW NOTES: 1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result is undefined. 2. When changing A/D operation mode, set the analog input pin again. 3. Set øAD frequency to 10 MHz or below . 4. The analog input pin can be selected according to a combination of bits CH0 to CH2 and the ADGSEL0 bit. CH2 to CH0 ADGSEL0 = 0 ADGSEL0 = 1 000b Do not set. AN0 001b AN1 010b AN2 011b AN3 100b AN4 AN8 101b AN5 AN9 110b AN6 AN10 111b AN7 AN11 Figure 17.2 ADCON0 Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 241 of 332 R8C/2E Group, R8C/2F Group 17. A/D Converter A/D Control Register 1(1) b7 b6 b5 b4 b3 b2 b1 b0 00 000 Symbol Address 00D7h ADCON1 Bit Symbol Bit Name Reserved bits — (b2-b0) BITS CKS1 VCUT — (b6-b7) 8/10-bit mode select bit(2) Frequency select bit 1 VREF connect bit(3) Reserved bits After Reset 00h Function Set to 0. 0 : 8-bit mode 1 : 10-bit mode Refer to the description of the CKS0 bit in the ADCON0 register function. 0 : VREF not connected 1 : VREF connected Set to 0. RW RW RW RW RW RW NOTES: 1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result is undefined. 2. Set the BITS bit to 0 (8-bit mode) in repeat mode. 3. When the VCUT bit is set to 1 (connected) from 0 (not connected), w ait for 1 µs or more before starting A/D conversion. A/D Control Register 2(1) b7 b6 b5 b4 b3 b2 b1 b0 000 Symbol ADCON2 Bit Symbol SMP — (b3-b1) — (b7-b4) Address 00D4h Bit Name A/D conversion method select bit Reserved bits After Reset 00h Function 0 : Without sample and hold 1 : With sample and hold Set to 0. RW RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. NOTE: 1. If the ADCON2 register is rew ritten during A/D conversion, the conversion result is undefined. A /D Register (b15) b7 (b8) b0 b7 b0 Symbol AD Function When BITS bit in ADCON1 register is set to 1 (10-bit mode). 8 low -order bits in A/D conversion result 2 high-order bits in A/D conversion result Nothing is assigned. If necessary, set to 0. When read, the content is 0. Address 00C1h-00C0h After Reset Undefined When BITS bit in ADCON1 register is set to 0 (8-bit mode). A/D conversion result When read, the content is undefined. RW RO RO — Figure 17.3 Registers ADCON1, ADCON2, and AD Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 242 of 332 R8C/2E Group, R8C/2F Group 17. A/D Converter 17.1 One-Shot Mode In one-shot mode, the input voltage of one selected pin is A/D converted once. Table 17.2 lists the Specification of One-Shot Mode. Figure 17.4 shows the ADCON0 Register in One-Shot Mode and Figure 17.5 shows the ADCON1 Register in One-Shot Mode. Table 17.2 Specification of One-Shot Mode Item Specification Function The input voltage of one pin selected by bits CH2 to CH0 and ADGSEL0 is A/D converted once Start condition Set the ADST bit to 1 (A/D conversion starts) Stop condition • A/D conversion completes (ADST bit is set to 0) • Set the ADST bit to 0 Interrupt request generation A/D conversion completes timing Input pin Select one of AN0 to AN11 Reading of A/D conversion Read AD register result Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 243 of 332 R8C/2E Group, R8C/2F Group 17. A/D Converter A/D Control Register 0(1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol ADCON0 Bit Symbol CH0 CH1 CH2 MD ADGSEL0 — (b5) ADST Address 00D6h Bit Name Analog input pin select bits (Note 4) After Reset 00h Function RW RW RW RW A/D operating mode select 0 : One-shot mode bit(2) A/D input group select bit(4) 0 : Selects port P0 group (AN0 to AN7) 1 : Selects port P1 group (AN8 to AN11) Reserved bit A/D conversion start flag Frequency select bit 0 Set to 0. 0 : Stops A/D conversion 1 : Starts A/D conversion [When CKS1 in ADCON1 register = 0] 0 : Select f4 1 : Select f2 [When CKS1 in ADCON1 register = 1] 0 : Select f1(3) 1 : Select fOCO-F RW RW RW RW CKS0 RW NOTES: 1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result is undefined. 2. After changing the A/D operating mode, select the analog input pin again. 3. Set øAD frequency to 10 MHz or below . 4. The analog input pin can be selected according to a combination of bits CH0 to CH2 and the ADGSEL0 bit. CH2 to CH0 ADGSEL0 = 0 ADGSEL0 = 1 000b Do not set. AN0 001b AN1 010b AN2 011b AN3 100b AN4 AN8 101b AN5 AN9 110b AN6 AN10 111b AN7 AN11 Figure 17.4 ADCON0 Register in One-Shot Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 244 of 332 R8C/2E Group, R8C/2F Group 17. A/D Converter A/D Control Register 1(1) b7 b6 b5 b4 b3 b2 b1 b0 001 000 Symbol Address 00D7h ADCON1 Bit Symbol Bit Name Reserved bits — (b2-b0) BITS CKS1 VCUT — (b6-b7) 8/10-bit mode select bit Frequency select bit 1 VREF connect bit(2) Reserved bits After Reset 00h Function Set to 0. 0 : 8-bit mode 1 : 10-bit mode Refer to the description of the CKS0 bit in the ADCON0 register function. 1 : VREF connected Set to 0. RW RW RW RW RW RW NOTES: 1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result is undefined. 2. When the VCUT bit is set to 1 (connected) from 0 (not connected), w ait for 1 µs or more before starting A/D conversion. Figure 17.5 ADCON1 Register in One-Shot Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 245 of 332 R8C/2E Group, R8C/2F Group 17. A/D Converter 17.2 Repeat Mode In repeat mode, the input voltage of one selected pin is A/D converted repeatedly. Table 17.3 lists the Repeat Mode Specifications. Figure 17.6 shows the ADCON0 Register in Repeat Mode and Figure 17.7 shows ADCON1 Register in Repeat Mode. Table 17.3 Repeat Mode Specifications Item Specification Function The Input voltage of one pin selected by bits CH2 to CH0 and ADGSEL0 is A/D converted repeatedly Start conditions Set the ADST bit to 1 (A/D conversion starts) Stop condition Set the ADST bit to 0 Interrupt request generation Not generated timing Input pin Select one of AN0 to AN11 Reading of result of A/D Read AD register converter Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 246 of 332 R8C/2E Group, R8C/2F Group 17. A/D Converter A/D Control Register 0(1) b7 b6 b5 b4 b3 b2 b1 b0 0 1 Symbol ADCON0 Bit Symbol CH0 CH1 CH2 MD ADGSEL0 — (b5) ADST Address 00D6h Bit Name Analog input pin select bits (Note 4) After Reset 00h Function RW RW RW RW A/D operating mode select 1 : Repeat mode bit(2) A/D input group select bit(4) 0 : Selects port P0 group (AN0 to AN7) 1 : Selects port P1 group (AN8 to AN11) Reserved bit A/D conversion start flag Frequency select bit 0 Set to 0. 0 : Stops A/D conversion 1 : Starts A/D conversion [When CKS1 in ADCON1 register = 0] 0 : Select f4 1 : Select f2 [When CKS1 in ADCON1 register = 1] 0 : Select f1(3) 1 : Do not set. RW RW RW RW CKS0 RW NOTES: 1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result is undefined. 2. After changing A/D operation mode, select the analog input pin again. 3. Set øAD frequency to 10 MHz or below . 4. The analog input pin can be selected according to a combination of bits CH0 to CH2 and the ADGSEL0 bit. CH2 to CH0 ADGSEL0 = 0 ADGSEL0 = 1 000b Do not set. AN0 001b AN1 010b AN2 011b AN3 100b AN4 AN8 101b AN5 AN9 110b AN6 AN10 111b AN7 AN11 Figure 17.6 ADCON0 Register in Repeat Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 247 of 332 R8C/2E Group, R8C/2F Group 17. A/D Converter A/D Control Register 1(1) b7 b6 b5 b4 b3 b2 b1 b0 001 0000 Symbol Address 00D7h ADCON1 Bit Symbol Bit Name Reserved bits — (b2-b0) BITS CKS1 VCUT — (b6-b7) 8/10-bit mode select bit(2) Frequency select bit 1 VREF connect bit(3) Reserved bits After Reset 00h Function Set to 0. 0 : 8-bit mode Refer to the description of the CKS0 bit in the ADCON0 register function. 1 : VREF connected Set to 0. RW RW RW RW RW RW NOTES: 1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result is undefined. 2. Set the BITS bit to 0 (8-bit mode) in repeat mode. 3. When the VCUT bit is set to 1 (connected) from 0 (not connected), w ait for 1 µs or more before starting A/D conversion. Figure 17.7 ADCON1 Register in Repeat Mode Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 248 of 332 R8C/2E Group, R8C/2F Group 17. A/D Converter 17.3 Sample and Hold When the SMP bit in the ADCON2 register is set to 1 (sample and hold function enabled), the A/D conversion rate per pin increases. The sample and hold function is available in all operating modes. Start A/D conversion after selecting whether the sample and hold circuit is to be used or not. Figure 17.8 shows a Timing Diagram of A/D Conversion. Sample and hold disabled Conversion time of 1st bit Sampling time 4ø AD cycles 2nd bit Comparison Sampling time Comparison Sampling time Comparison 2.5ø AD cycles 2.5ø AD cycles time time time * Repeat until conversion ends Sample and hold enabled Conversion time of 1st bit Sampling time 4ø AD cycles Comparison time 2nd bit Comparison Comparison Comparison time time time * Repeat until conversion ends Figure 17.8 Timing Diagram of A/D Conversion 17.4 A/D Conversion Cycles Figure 17.9 shows the A/D Conversion Cycles. Conversion time at the 1st bit Conversion time at the 2nd bit and the follows End process A/D Conversion Mode Without Sample & Hold Without Sample & Hold With Sample & Hold With Sample & Hold 8 bits 10 bits 8 bits 10 bits Conversion Time 49φAD 59φAD 28φAD 33φAD Sampling Time 4φAD 4φAD 4φAD 4φAD Comparison Time 2.0φAD 2.0φAD 2.5φAD 2.5φAD Sampling Time 2.5φAD 2.5φAD 0.0φAD 0.0φAD Comparison End process Time 2.5φAD 2.5φAD 2.5φAD 2.5φAD 8.0φAD 8.0φAD 4.0φAD 4.0φAD Figure 17.9 A/D Conversion Cycles Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 249 of 332 R8C/2E Group, R8C/2F Group 17. A/D Converter 17.5 Internal Equivalent Circuit of Analog Input Figure 17.10 shows the Internal Equivalent Circuit of Analog Input. VCC VCC VSS AVCC Parasitic Diode AN0 ON Resistor Approx. 2kΩ Wiring Resistor Approx. 0.2kΩ SW1 Parasitic Diode ON Resistor Approx. 0.6kΩ Analog Input Voltage SW2 VIN ON Resistor Approx. 5kΩ SW3 C = Approx.1.5pF AMP Sampling Control Signal VSS SW4 i=12 i Ladder-type Switches i Ladder-type Wiring Resistors AVSS Chopper-type Amplifier ON Resistor Approx. 2kΩ Wiring Resistor Approx. 0.2kΩ AN11 SW1 b4 b2 b1 b0 A/D Control Register 0 VREF Reference Control Signal A/D Successive Conversion Register Vref Resistor ladder AVSS SW5 ON Resistor Approx. 0.6k f Comparison voltage A/D Conversion Interrupt Request Comparison reference voltage (Vref) generator Sampling C parison om C onnect to SW1 conducts only on the ports selected for analog input. SW2 and SW3 are open when A/D conversion is not in progress; their status varies as shown by the waveforms in the diagrams on the left. SW4 conducts only when A/D conversion is not in progress. C onnect to Control signal for SW2 C onnect to C onnect to Control signal for SW3 SW5 conducts when compare operation is in progress. NOTE: 1. Use only as a standard for designing this data. Mass production may cause some changes in device characteristics. Figure 17.10 Internal Equivalent Circuit of Analog Input Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 250 of 332 R8C/2E Group, R8C/2F Group 17. A/D Converter 17.6 Output Impedance of Sensor under A/D Conversion To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 17.11 has to be completed within a specified period of time. T (sampling time) as the specified time. Let output impedance of sensor equivalent circuit be R0, internal resistance of microcomputer be R, precision (error) of the A/D converter be X, and the resolution of A/D converter be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode). 1 – -------------------------C ( R0 + R )  VC = VIN  1 – e  t    VC is generally And when t = T, X X VC = VIN – --- VIN = VIN  1 – ---   Y Y 1 – --------------------------T C ( R0 + R ) = X --e Y 1 – -------------------------- T = ln X --C ( R0 + R ) Y Hence, T R0 = – ------------------- – R X C • ln --Y Figure 17.11 shows Analog Input Pin and External Sensor Equivalent Circuit. When the difference between VIN and VC becomes 0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN(0.1/1024) VIN in time T. (0.1/1024) means that A/D precision drop due to insufficient capacitor charge is held to 0.1LSB at time of A/D conversion in the 10-bit mode. Actual error however is the value of absolute precision added to 0.1LSB. When f(XIN) = 10 MHz, T = 0.25 µs in the A/D conversion mode without sample and hold. Output impedance R0 for sufficiently charging capacitor C within time T is determined as follows. T = 0.25 µs, R = 2.8 kΩ, C = 6.0 pF, X = 0.1, and Y = 1024. Hence, 3 3 0.25 × 10 – 6 R0 = – -------------------------------------------------- – 2.8 ×10 ≈ 1.7 ×10 0.1 6.0 × 10 – 12 • ln ----------1024 Thus, the allowable output impedance of the sensor equivalent circuit, making the precision (error) 0.1LSB or less, is approximately 1.7 kΩ. maximum. MCU Sensor equivalent circuit R0 VIN C (6.0 pF) VC R (2.8 kΩ) NOTE: 1. The capacity of the terminal is assumed to be 4.5 pF. Figure 17.11 Analog Input Pin and External Sensor Equivalent Circuit Page 251 of 332 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 R8C/2E Group, R8C/2F Group 17. A/D Converter 17.7 Notes on A/D Converter • Write to each bit (other than bit 6) in the ADCON0 register, each bit in the ADCON1 register, or the SMP bit in the ADCON2 register when A/D conversion is stopped (before a trigger occurs). When the VCUT bit in the ADCON1 register is changed from 0 (VREF not connected) to 1 (VREF connected), wait for at least 1 µs before starting the A/D conversion. After changing the A/D operating mode, select an analog input pin again. When using the one-shot mode, ensure that A/D conversion is completed before reading the AD register. The IR bit in the ADIC register or the ADST bit in the ADCON0 register can be used to determine whether A/D conversion is completed. When using the repeat mode, select the frequency of the A/D converter operating clock φAD or more for the CPU clock during A/D conversion. Do not select the fOCO-F for the φAD. If the ADST bit in the ADCON0 register is set to 0 (A/D conversion stops) by a program and A/D conversion is forcibly terminated during an A/D conversion operation, the conversion result of the A/D converter will be undefined. If the ADST bit is set to 0 by a program, do not use the value of the AD register. Connect 0.1 µF capacitor between the P4_2/VREF pin and AVSS pin. Do not enter stop mode during A/D conversion. Do not enter wait mode when the CM02 bit in the CM0 register is set to 1 (peripheral function clock stops in wait mode) during A/D conversion. • • • • • • • Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 252 of 332 R8C/2E Group, R8C/2F Group 18. D/A Converter 18. D/A Converter The D/A converters are 8-bit R-2R type units. The D/A converter 0 and D/A converter 1 are two independent D/A converters. D/A conversion is performed by writing to the DAi register (i = 0 or 1). To output the conversion result, set the DAiE bit in the DACON register to 1 (output enabled) and set the VRiSEL bit in the ACCRi register to 0 (AVREFi pin input). Before using D/A conversion, the corresponding port direction bit must be set to 0 (input mode). Setting the DAiE bit to 1 removes the pull-up from the corresponding port. The output analog voltage (V) is determined by the setting value n (n: decimal) of the DAi register. V = Vref × n/256 (n = 0 to 255) Vref: Reference voltage Table 18.1 lists the D/A Converter Specifications. Figure 18.1 shows the Block Diagram of D/A Converter. Figures 18.2 and 18.3 show the D/A converter related registers. Figure 18.4 shows the D/A Converter Equivalent Circuit. Table 18.1 D/A Converter Specifications Performance R-2R method 8 bits 2 (DA0 and DA1) Item D/A conversion method Resolution Analog output pins DA0 register 0 1 Data bus R-2R resistor ladder 1 0 DA0 DA0E bit VR0SEL bit DA1 register 0 1 R-2R resistor ladder 1 0 DA1 DA1E bit VR1SEL bit DA0E, DA1E: Bits in DACON register VR0SEL: Bit in ACCR0 register VR1SEL: Bit in ACCR1 register Figure 18.1 Block Diagram of D/A Converter Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 253 of 332 R8C/2E Group, R8C/2F Group 18. D/A Converter D/Ai Register (i = 0 or 1)(1) b7 b0 Symbol DA0 DA1 Address 00D8h 00DAh Function After Reset 00h 00h Setting Range 00h to FFh RW RW Output value of D/A conversion NOTE: 1. When not using the D/A converter, set the DAiE bit (i = 0 or 1) to 0 (output disabled) and set the DAi register to 00h to prevent current from flow ing into the R-2R resistor ladder to reduce unnecessary current consumption. D/A Control Register(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol DACON Bit Symbol DA0E DA1E — (b7-b2) Address 00DCh Bit Name D/A0 output enable bit D/A1 output enable bit 0 : Output disabled 1 : Output enabled 0 : Output disabled 1 : Output enabled After Reset 00h Function RW RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. NOTE: 1. When not using the D/A converter, set the DAiE bit (i = 0 or 1) to 0 (output disabled) and set the DAi register to 00h to prevent current from flow ing into the R-2R resistor ladder to reduce unnecessary current consumption. Figure 18.2 Registers DA0 to DA1 and DACON Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 254 of 332 R8C/2E Group, R8C/2F Group 18. D/A Converter Comparator i Control Register (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ACCR0 ACCR1 Bit Symbol CMiE CMiOE VRiSEL CMiLV Address After Reset 0174h 00001000b 0175h 00001000b Bit Name Function Comparator i enable operation bit 0 : Disable operation 1 : Enable operation ACOUTi output enable bit Comparator i reference input select bit Comparison result monitor flag Comparator i digital filter select bits 0 : Disable output 1 : Enable output 0 : AVREFi pin input 1 : D/A converter i output(1) 0 : ACMPi input < reference input 1 : ACMPi input > reference input b5 b4 RW RW RW RW RO FLTi0 FLTi1 Comparator i interrupt enable bit Comparator i interrupt flag CMiF 0 0 : No filter 0 1 : Filter w ith f2 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling 0 : Disable interrupt by CMiF bit 1 : Enable interrupt by CMiF bit [Source for setting this bit to 0] Write 0 after read(2) [Source for setting this bit to 1] When the comparison result is changed RW RW CMiIE RW RW NOTES: 1. When setting the VRiSEL bit to 1 (D/A converter i output), set the DAiE bit in the DACON register to 1 (output enabled). How ever, at this time, the D/A conversion result is not output from DAi pin. 2. The w riting results are as follow s: • This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit. • This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains 1 even if it is set to 1 from 0 after reading, and w riting 0.) • This bit remains unchanged if 1 is w ritten to it. Figure 18.3 Registers ACCR0 to ACCR1 DAiE bit r DAi 1 2R MSB DAi register 2R 2R 2R 2R 2R 2R 2R LSB 0 R R R R R R R 2R 0 1 AVSS VREF(2) i = 0 to 1 NOTES: 1. The above diagram applies when the value of the DAi register is 2Ah. 2. VREF is not affected by the setting of the VCUT bit in the ADCON1 register. Figure 18.4 D/A Converter Equivalent Circuit Page 255 of 332 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 R8C/2E Group, R8C/2F Group 19. Comparator 19. Comparator The comparators compare a reference input voltage and an analog input voltage. Comparator 0 and comparator 1 are two independent comparators. 19.1 Overview The comparison result of the reference input voltage and analog input voltage can be read by software. The result also can be output from the ACOUTi (i = 0 or 1) pin. An input to the AVREFi pin or output from D/A converter i can be selected as the reference input voltage. Table 19.1 lists the Specifications for Comparator, Figure 19.1 shows the Block Diagram of Comparator, and Table 19.2 lists the I/O Pins. Table 19.1 Specifications for Comparator Item Analog input voltage Reference input voltage Comparison result Interrupt request generation timing Select functions Specification Input voltage to ACMPi pin Input voltage to AVREFi pin or output voltage of D/A converter i Read the CMiLV bit in the ACCRi register When the comparison result changes • The comparison result can be output from the ACOUTi pin. • ACOUTi pin output polarity Whether the comparison result output is inverted or not inverted can be selected. • Digital filter function For the CMACOUTi signal (comparison result), whether the digital filter is applied or not and the sampling frequency can be selected. i = 0 or 1 FLT01 to FLT00 f2 = 01b Sampling clock f8 = 10b CM0E CM0POR CM0LV Pin output select circuit CM0OE ACMP0 AVREF0 0 1 0 1 f32 = 11b + - = other than 00b CMACOUT0 signal = 00b Digital filter 0 1 ACOUT0 VR0SEL FLT11 to FLT10 f2 = 01b Sampling clock f8 = 10b CM1E CM1POR ACMP1 AVREF1 0 1 0 1 f32 = 11b + - CM1OE Digital filter 0 1 = other than 00b CMACOUT1 signal = 00b ACOUT1 VR1SEL CM1LV VR0SEL 1 DA0E 0 1 0 1 DA0 DA1 D/A Converter 0 D/A Converter 1 DA1E 0 1 0 Interrupt control circuit Comparator 0 interrupt request Comparator 1 interrupt request VR1SEL CM0E, CM0OE, VR0SEL, CM0LV, FLT00 to FLT01: Bits in ACCR0 register CM1E, CM1OE, VR1SEL, CM1LV, FLT10 to FLT11: Bits in ACCR1 register CM0POR, CM1POR: Bits in ACMR register DA0E, DA1E: Bits in DACON register CMACOUT0 signal, CMACOUT1 signal: Internal signal Figure 19.1 Block Diagram of Comparator Page 256 of 332 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 R8C/2E Group, R8C/2F Group 19. Comparator Table 19.2 I/O Pins I/O Input Input Output Input Input Output Function Comparator 0 analog pin Comparator 0 reference voltage pin Comparator 0 comparison result output pin Comparator 1 analog pin Comparator 1 reference voltage pin Comparator 1 comparison result output pin Pin Name ACMP0 AVREF0 ACOUT0 ACMP1 AVREF1 ACOUT1 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 257 of 332 R8C/2E Group, R8C/2F Group 19. Comparator 19.2 Register Functions Figure 19.2 shows the Registers ACCR0 to ACCR1 and Figure 19.3 shows the ACMR Register. Comparator i Control Register (i = 0 or 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ACCR0 ACCR1 Bit Symbol CMiE CMiOE VRiSEL CMiLV Address After Reset 0174h 00001000b 0175h 00001000b Bit Name Function Comparator i enable operation bit 0 : Disable operation 1 : Enable operation ACOUTi output enable bit Comparator i reference input select bit Comparison result monitor flag Comparator i digital filter select bits 0 : Disable output 1 : Enable output 0 : AVREFi pin input 1 : D/A converter i output(1) 0 : ACMPi input < reference input 1 : ACMPi input > reference input b5 b4 RW RW RW RW RO FLTi0 FLTi1 Comparator i interrupt enable bit Comparator i interrupt flag CMiF 0 0 : No filter 0 1 : Filter w ith f2 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling 0 : Disable interrupt by CMiF bit 1 : Enable interrupt by CMiF bit [Source for setting this bit to 0] Write 0 after read(2) [Source for setting this bit to 1] When the comparison result is changed RW RW CMiIE RW RW NOTES: 1. When setting the VRiSEL bit to 1 (D/A converter i output), set the DAiE bit in the DACON register to 1 (output enabled). How ever, at this time, the D/A conversion result is not output from DAi pin. 2. The w riting results are as follow s: • This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit. • This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains 1 even if it is set to 1 from 0 after reading, and w riting 0.) • This bit remains unchanged if 1 is w ritten to it. Figure 19.2 Registers ACCR0 to ACCR1 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 258 of 332 R8C/2E Group, R8C/2F Group 19. Comparator Comparator Mode Register b7 b6 b5 b4 b3 b2 b1 b0 000 0 Symbol ACMR Bit Symbol CM0POR Address After Reset 0177h 00h Bit Name Function ACOUT0 output polarity select bit 0 : Output the non-inverted comparator 0 comparison result to ACOUT0 1 : Output the inverted comparator 0 comparison result to ACOUT0 ACOUT1 output polarity select bit 0 : Output the non-inverted comparator 1 comparison result to ACOUT1 1 : Output the inverted comparator 1 comparison result to ACOUT1 Reserved bit Set to 0. RW RW CM1POR RW (b2) (b3) (b6-b4) (b7) RW — RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. Reserved bits Set to 0. Nothing is assigned. If necessary, set to 0. When read, the content is 0. Figure 19.3 ACMR Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 259 of 332 R8C/2E Group, R8C/2F Group 19. Comparator 19.3 Functional Description Comparator 0 and comparator 1 operate independently. Their operations are the same. Table 19.3 lists the Procedure for Setting Registers Associated with Comparator Table 19.3 Procedure for Setting Registers Associated with Comparator Step Register Bit Setting Value 1 Function selection of ACMPi, AVREFi, and ACOUTi pin. Refer to 7.4 Port Setting. Set registers and bits other than listed in step 2 and the following steps. 2 ACMR CMiPOR When using the ACOUTi output: Select the ACOUTi output polarity. 3 ACCRi FLTi1 to FLTi0 Select to enable or disable the filter, and select the sampling clock frequency. VRiSEL Select the reference input. 4 DACON DAiE When setting the D/A converter i output voltage to reference voltage: 1 (D/A output enabled) 5 ACCRi CMiE 1 (operation enabled) 6 Wait until comparator stability time (max. 10 µs) 7 ACCRi CMiF Read (dummy read to initialize the interrupt flag) 8 ACCRi CMiOE When using the ACOUTi output: 1 (ACOUTi output enabled) CMiIE When using interrupts: 1 (interrupt enabled) CMiF When using interrupts: 0 (no interrupt requested: Initialization) 9 CMiIC ILVL2 to ILVL0 When using interrupts: Select the interrupt priority level. IR When using interrupts: 0 (no interrupt requested: Initialization) i = 0 or 1 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 260 of 332 R8C/2E Group, R8C/2F Group 19. Comparator Figure 19.4 shows an Operating Example of Comparator i (i = 0 or 1). If the analog input voltage is higher than the reference input voltage, the CMiLV bit in the ACCRi register is set to 1. If the analog input voltage is lower than the reference input voltage, the CMiLV bit is set to 0. When the comparison result changes, the CMiF bit in the ACCRi register is set to 1. If the value of the CMiIE bit in the ACCRi register is 1 (interrupt by CMiF bit enabled) at this time, a comparator i interrupt request is generated. Refer to 19.4 Comparator 0 Interrupt and Comparator 1 Interrupt for information of interrupts. Analog input voltage (V) Reference input voltage 0 CMiLV bit in ACCRi register 1 0 Set to 0 by a program CMiF bit in ACCRi register 1 0 ACOUTi output (when CMiPOR bit in ACMR register is set to 0) ACOUTi output (when CMiPOR bit in ACMR register is set to 1) 1 0 1 0 The above applies under the following conditions: CMiOE bit in the ACCRi register = 1 (output enabled) Bits FLTi1 to FLTi0 in the ACCRi register = 00b (no filter) CMiPOR bit in the ACMR register = 0 (non-inverted comparator i compare result output to ACOUTi) CMiPOR bit in the ACMR register = 1 (inverted comparator i compare result output to ACOUTi) i = 0 or 1 Figure 19.4 Operating Example of Comparator i (i = 0 or 1) 19.3.1 Comparison Result Output When the CMiOE bit in the ACCRi register is set to 1 (output enabled), the comparison result can be output from the ACOUTi pin. Also, the CMiPOR bit in the ACMR register can be used to select whether the ACOUTi pin output polarity is inverted or not inverted. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 261 of 332 R8C/2E Group, R8C/2F Group 19. Comparator 19.3.2 Digital Filter The digital filter can be applied to the CMACOUTi (i = 0 or1) signal. The CMACOUTi signal is sampled, and the level is considered to be determined when two matches occur. The digital filter function and sampling frequency are selected using bits FLTi0 to FLTi1 in the ACCRi register. Figure 19.5 shows a Block Diagram of Digital Filter. f2 f8 = 10b f32 = 11b FLTi1 to FLTi0 = 01b Sampling clock C C Q D Latch Q CMACOUTi signal D Latch Match detect circuit C D Latch Q FLTi1 to FLTi0 = 01b, 10b, 11b = 00b Clock cycle selected by FLTi1 to FLTi0 Sampling clock CMACOUTi signal Input signal after passing through digital filter Two matches occur and a signal change is confirmed. Maximum signal transmission delay is 2.5 sampling clock pulses. If fewer than two matches occur, the matches are treated as noise and no transmission is performed. FLTi0 to FLTi1: Bits in ACCRi register i = 0 or 1 Figure 19.5 Block Diagram of Digital Filter Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 262 of 332 R8C/2E Group, R8C/2F Group 19. Comparator 19.4 Comparator 0 Interrupt and Comparator 1 Interrupt Comparator 0 and Comparator 1 generate interrupt request from two sources. The comparator i (i = 0 or 1) interrupt uses the corresponding CMiIC register (bits IR and ILVL0 to ILVL2) and vector. When the comparison result changes, the CMiF bit in the ACCRi register is set to 1. If the value of the CMiIE bit in the ACCRi register is 1 (interrupt by CMiF bit enabled) at this time, a comparator i interrupt request is generated. Table 19.4 lists the Registers and Bits Associated with Comparator Interrupt, and Figure 19.6 is a Block Diagram of Comparator Interrupt. Table 19.4 Registers and Bits Associated with Comparator Interrupt Comparator i Interrupt Control Register, Comparator i Interrupt Enable Bit CMiE bit in ACCRi register Comparator i Interrupt Control Register CMiIC Comparator i Control Register, Comparator i Interrupt Flag CMiF bit in ACCRi register i = 0 or 1 CM0F bit CM0IE bit CM1F bit CM1IE bit Comparator 0 interrupt request (IR bit in CM0IC register) Comparator 1 interrupt request (IR bit in CM1IC register) CM0F, CM0IE: Bits in ACCR0 register CM1F, CM1IE: Bits in ACCR1 register Figure 19.6 Block Diagram of Comparator Interrupt Like other maskable interrupts, the comparator i interrupt is controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, the existence of the bits CMiF and CMiIE results in the following differences from other maskable interrupts. • The IR bit in the CMiIC register is set to 1 (interrupt requested) when the CMiF bit in the ACCRi register is set to 1 and the CMiIE bit in the ACCRi register is set to 1 (interrupt enabled). • The IR bit is set to 0 (no interrupt requested) when the CMiF bit or CMiIE bit is set to 0, or both are set to 0. In other words, the interrupt request is not maintained if the IR bit is once set to 1 but the interrupt is not acknowledged. • The CMiF bit is not automatically set to 0 when an interrupt is acknowledged. Set it to 0 within the interrupt routine. Refer to Figure 19.2 Registers ACCR0 to ACCR1, for the procedure for setting these bits to 0. Refer to 12.1.6 Interrupt Control, for details of the CMiIC register and 12.1.5.2 Relocatable Vector Tables, for information on interrupt vectors. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 263 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version 20. Flash Memory Version 20.1 Overview In the flash memory, rewrite operations to the flash memory can be performed in three modes: CPU rewrite, standard serial I/O, and parallel I/O. Table 20.1 lists the Flash Memory Performance (refer to Table 1.1 , Table 1.2, Table 1.3 , and Table 1.4 Specifications for items not listed in Table 20.1). Table 20.1 Flash Memory Performance Specification 3 modes (CPU rewrite, standard serial I/O, and parallel I/O) Refer to Figure 20.1 and Figure 20.2 Byte unit Block erase Program and erase control by software command Rewrite control for blocks 0 and 1 by FMR02 bit in FMR0 register Rewrite control for block 0 by FMR15 bit and block 1 by FMR16 bit in FMR1 register 5 commands R8C/2E Group: 100 times; R8C/2F Group: 1,000 times Item Flash memory operating mode Division of erase block Programming method Erase method Programming and erasure control method(3) Rewrite control method Number of commands Programming Blocks 0 and 1 (program and erasure ROM) endurance(1) Blocks A and B (data flash)(2) 10,000 times ID code check function ROM code protect Standard serial I/O mode supported Parallel I/O mode supported NOTES: 1. Definition of programming and erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1-Kbyte block, and then the block is erased, the erase count stands at one. When performing 100 or more rewrites, the actual erase count can be reduced by executing programming operations in such a way that all blank areas are used before performing an erase operation. Avoid rewriting only particular blocks and try to average out the programming and erasure endurance of the blocks. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 2. Blocks A and B are implemented only in the R8C/2F group. 3. To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform programming and erasure at less than 2.7 V. Table 20.2 Flash Memory Rewrite Modes Standard Serial I/O Mode User ROM area is rewritten by executing User ROM area is rewritten by a software commands from the CPU. dedicated serial EW0 mode: Rewritable in the RAM EW1 mode: Rewritable in flash memory programmer. User ROM area User ROM area CPU Rewrite Mode Boot mode Serial programmer Parallel I/O Mode User ROM area is rewritten by a dedicated parallel programmer. User ROM area Parallel I/O mode Parallel programmer Flash memory Rewrite mode Function Areas which can be rewritten Operating mode Single chip mode ROM Programmer None Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 264 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version 20.2 Memory Map The flash memory contains a user ROM area and a boot ROM area (reserved area). Figure 20.1 shows the Flash Memory Block Diagram for R8C/2E Group. Figure 20.2 shows a Flash Memory Block Diagram for R8C/2F Group. The user ROM area of the R8C/2F Group contains an area (program ROM) which stores MCU operating programs and blocks A and B (data flash) each 1 Kbyte in size. The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite mode and standard serial I/O and parallel I/O modes. When rewriting blocks 0 and 1 in CPU rewrite mode, set the FMR02 bit in the FMR0 register to 1 (rewrite enabled). When the FMR15 bit in the FMR1 register is set to 0 (rewrite enabled), block 0 is rewritable. When the FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable. The rewrite control program for standard serial I/O mode is stored in the boot ROM area before shipment. The boot ROM area and the user ROM area share the same address, but have separate memory areas. 16 Kbyte ROM product 0C000h 0DFFFh 0E000h 0FFFFh User ROM area Block 1: 8 Kbytes(1) Block 0: 8 Kbytes(1) 0E000h 0FFFFh User ROM area 8 Kbyte ROM product Block 0: 8 Kbytes(1) Program ROM 0E000h 0FFFFh Boot ROM area (reserved area)(2) 8 Kbytes NOTES: 1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1 register is set to 0 (rewrite enabled), block 0 is rewritable. When the FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable (only for CPU rewrite mode). 2. This area is for storing the boot program provided by Renesas Technology. Figure 20.1 Flash Memory Block Diagram for R8C/2E Group Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 265 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version 16 Kbytes ROM product 02400h Block A: 1 Kbyte Block B: 1 Kbyte 02400h 8 Kbytes ROM product Block A: 1 Kbyte Data flash Block B: 1 Kbyte 02BFFh 02BFFh Block 0: 16 Kbytes(1) 0C000h 0DFFFh 0E000h 0FFFFh Block 1: 8 Kbytes(1) Block 0: 8 Kbytes(1) User ROM area 0E000h 0FFFFh User ROM area Block 0: 8 Kbytes(1) Program ROM 0E000h 0FFFFh Boot ROM area (reserved area)(2) 8 Kbytes NOTES: 1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1 register is set to 0 (rewrite enabled), block 0 is rewritable. When the FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable (only for CPU rewrite mode). 2. This area is for storing the boot program provided by Renesas Technology. Figure 20.2 Flash Memory Block Diagram for R8C/2F Group Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 266 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version 20.3 Functions to Prevent Rewriting of Flash Memory Standard serial I/O mode has an ID code check function, and parallel I/O mode has a ROM code protect function to prevent the flash memory from being read or rewritten easily. 20.3.1 ID Code Check Function This function is used in standard serial I/O mode. Unless the flash memory is blank, the ID codes sent from the programmer and the ID codes written in the flash memory are checked to see if they match. If the ID codes do not match, the commands sent from the programmer are not acknowledged. The ID codes consist of 8 bits of data each, the areas of which, beginning with the first byte, are 00FFDFh, 00FFE3h, 00FFEBh, 00FFEFh, 00FFF3h, 00FFF7h, and 00FFFBh. Write programs in which the ID codes are set at these addresses and write them to the flash memory. Address 00FFDFh to 00FFDCh 00FFE3h to 00FFE0h 00FFE7h to 00FFE4h 00FFEBh to 00FFE8h 00FFEFh to 00FFECh 00FFF3h to 00FFF0h 00FFF7h to 00FFF4h 00FFFBh to 00FFF8h 00FFFFh to 00FFFCh ID1 ID2 Undefined instruction vector Overflow vector BRK instruction vector ID3 ID4 ID5 ID6 ID7 (Note 1) Address match vector Single step vector Oscillation stop detection/watchdog timer/voltage monitor 1 and voltage monitor 2 vector Address break (Reserved) Reset vector 4 bytes NOTE: 1. The OFS register is assigned to 00FFFFh. Refer to Figure 20.4 OFS Register for OFS register details. Figure 20.3 Address for Stored ID Code Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 267 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version 20.3.2 ROM Code Protect Function The ROM code protect function disables reading or changing the contents of the on-chip flash memory by the OFS register in parallel I/O mode. Figure 20.4 shows the OFS Register. The ROM code protect function is enabled by writing 0 to the ROMCP1 bit and 1 to the ROMCR bit. It disables reading or changing the contents of the on-chip flash memory. Once ROM code protect is enabled, the content in the internal flash memory cannot be rewritten in parallel I/O mode. To disable ROM code protect, erase the block including the OFS register with CPU rewrite mode or standard serial I/O mode. Option Function Select Register(1) b7 b6 b5 b4 b3 b2 b1 b0 101 1 Symbol OFS Bit Symbol WDTON — (b1) ROMCR ROMCP1 — (b4) — (b5) — (b6) Address 0FFFFh Bit Name Watchdog timer start select bit Reserved bit ROM code protect disabled bit ROM code protect bit Reserved bit Reserved bit Reserved bit When Shipping FFh(2) Function 0 : Starts w atchdog timer automatically after reset 1 : Watchdog timer is inactive after reset Set to 1. 0 : ROM code protect disabled 1 : ROMCP1 enabled 0 : ROM code protect enabled 1 : ROM code protect disabled Set to 1. Set to 0. Set to 1. 0 : Count source protect mode enabled after reset 1 : Count source protect mode disabled after reset RW RW RW RW RW RW RW RW Count source protect CSPROINI mode after reset select bit RW NOTES: 1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not w rite additions to the OFS register. 2. If the block including the OFS register is erased, FFh is set to the OFS register. Figure 20.4 OFS Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 268 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version 20.4 CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU. Therefore, the user ROM area can be rewritten directly while the MCU is mounted on a board without using a ROM programmer. Execute the program and block erase commands only to blocks in the user ROM area. The flash module has an erase-suspend function when an interrupt request is generated during an erase operation in CPU rewrite mode. It performs an interrupt process after the erase operation is halted temporarily. During erasesuspend, the user ROM area can be read by a program. In case an interrupt request is generated during an auto-program operation in CPU rewrite mode, the flash module contains a program-suspend function which performs the interrupt process after the auto-program operation is suspended. During program-suspend, the user ROM area can be read by a program. CPU rewrite mode has an erase write 0 mode (EW0 mode) and an erase write 1 mode (EW1 mode). Table 20.3 lists the Differences between EW0 Mode and EW1 Mode. Table 20.3 Differences between EW0 Mode and EW1 Mode EW0 Mode Single-chip mode User ROM area EW1 Mode Single-chip mode User ROM area Item Operating mode Areas in which a rewrite control program can be located Areas in which a rewrite control program can be executed Areas which can be rewritten Software command restrictions Modes after program or erase Modes after read status register CPU status during autowrite and auto-erase Flash memory status detection Necessary to transfer to any area other Executing directly in user ROM or RAM than the flash memory (e.g., RAM) before area possible executing User ROM area User ROM area However, blocks which contain a rewrite control program are excluded(1) None • Program and block erase commands Cannot be run on any block which contains a rewrite control program • Read status register command Cannot be executed Read status register mode Read array mode Read status register mode Operating Do not execute this command Conditions for transition to erase-suspend Conditions for transitions to program-suspend CPU clock NOTE: Hold state (I/O ports hold state before the command is executed) • Read bits FMR00, FMR06, and FMR07 Read bits FMR00, FMR06, and FMR07 in in the FMR0 register by a program the FMR0 register by a program • Execute the read status register command and read bits SR7, SR5, and SR4 in the status register. Set bits FMR40 and FMR41 in the FMR4 The FMR40 bit in the FMR4 register is set register to 1 by a program. to 1 and the interrupt request of the enabled maskable interrupt is generated Set bits FMR40 and FMR42 in the FMR4 The FMR40 bit in the FMR4 register is set register to 1 by a program. to 1 and the interrupt request of the enabled maskable interrupt is generated 5 MHz or below No restriction (on clock frequency to be used) 1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled), rewriting block 0 is enabled by setting the FMR15 bit in the FMR1 register to 0 (rewrite enabled), and rewriting block 1 is enabled by setting the FMR16 bit to 0 (rewrite enabled). Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 269 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version 20.4.1 EW0 Mode The MCU enters CPU rewrite mode and software commands can be acknowledged by setting the FMR01 bit in the FMR0 register to 1 (CPU rewrite mode enabled). In this case, since the FMR11 bit in the FMR1 register is set to 0, EW0 mode is selected. Use software commands to control program and erase operations. The FMR0 register or the status register can be used to determine when program and erase operations complete. During auto-erasure, set the FMR40 bit to 1 (erase-suspend enabled) and the FMR41 bit to 1 (request erasesuspend). Wait for td(SR-SUS) and ensure that the FMR46 bit is set to 1 (read enabled) before accessing the user ROM area. The auto-erase operation can be restarted by setting the FMR41 bit to 0 (erase restarts). To enter program-suspend during the auto-program operation, set the FMR40 bit to 1 (suspend enabled) and the FMR42 bit to 1 (request program-suspend). Wait for td(SR-SUS) and ensure that the FMR46 bit is set to 1 (read enabled) before accessing the user ROM area. The auto-program operation can be restarted by setting the FMR42 bit to 0 (program restarts). 20.4.2 EW1 Mode The MCU is switched to EW1 mode by setting the FMR11 bit to 1 (EW1 mode) after setting the FMR01 bit to 1 (CPU rewrite mode enabled). The FMR0 register can be used to determine when program and erase operations complete. Do not execute commands that use the read status register in EW1 mode. To enable the erase-suspend function during auto-erasure, execute the block erase command after setting the FMR40 bit to 1 (erase-suspend enabled). The interrupt to enter erase-suspend should be in interrupt enabled status. After waiting for td(SR-SUS) after the block erase command is executed, the interrupt request is acknowledged. When an interrupt request is generated, the FMR41 bit is automatically set to 1 (requests erase-suspend) and the auto-erase operation suspends. If an auto-erase operation does not complete (FMR00 bit is 0) after an interrupt process completes, the auto-erase operation restarts by setting the FMR41 bit to 0 (erasure restarts) To enable the program-suspend function during auto-programming, execute the program command after setting the FMR40 bit to 1 (suspend enabled). The interrupt to enter program-suspend should be in interrupt enabled status. After waiting for td(SR-SUS) after the program command is executed, an interrupt request is acknowledged. When an interrupt request is generated, the FMR42 bit is automatically set to 1 (request program-suspend) and the auto-program operation suspends. When the auto-program operation does not complete (FMR00 bit is 0) after the interrupt process completes, the auto-program operation can be restarted by setting the FMR42 bit to 0 (programming restarts). Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 270 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version Figure 20.5 shows the FMR0 Register. Figure 20.6 shows the FMR1 Register. Figure 20.7 shows the FMR4 Register. 20.4.2.1 FMR00 Bit This bit indicates the operating status of the flash memory. The bits value is 0 during programming, erasure (including suspend periods), or erase-suspend mode; otherwise, it is 1. 20.4.2.2 FMR01 Bit The MCU is made ready to accept commands by setting the FMR01 bit to 1 (CPU rewrite mode). 20.4.2.3 FMR02 Bit Rewriting of blocks 0 and 1 does not accept program or block erase commands if the FMR02 bit is set to 0 (rewrite disabled). Rewriting of blocks 0 and 1 are controlled by bits FMR15 and FMR16 if the FMR02 bit is set to 1 (rewrite enabled). 20.4.2.4 FMSTP Bit This bit is used to initialize the flash memory control circuits, and also to reduce the amount of current consumed by the flash memory. Access to the flash memory is disabled by setting the FMSTP bit to 1. Therefore, the FMSTP bit must be written to by a program transferred to the RAM. In the following cases, set the FMSTP bit to 1: • When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00 bit not reset to 1 (ready)) • To provide lower consumption in high-speed on-chip oscillator mode and low-speed on-chip oscillator mode (XIN clock stops). Figure 20.11 shows the handling to provide lower consumption in high-speed on-chip oscillator mode and lowspeed on-chip oscillator mode (XIN clock stops). Handle according to this flowchart. Note that when going to stop or wait mode while the CPU rewrite mode is disabled, the FMR0 register does not need to be set because the power for the flash memory is automatically turned off and is turned back on again after returning from stop or wait mode. 20.4.2.5 FMR06 Bit This is a read-only bit indicating the status of an auto-program operation. The bit is set to 1 when a program error occurs; otherwise, it is cleared to 0. For details, refer to the description in 20.4.5 Full Status Check. 20.4.2.6 FMR07 Bit This is a read-only bit indicating the status of an auto-erase operation. The bit is set to 1 when an erase error occurs; otherwise, it is set to 0. Refer to 20.4.5 Full Status Check for details. 20.4.2.7 FMR11 Bit Setting this bit to 1 (EW1 mode) places the MCU in EW1 mode. 20.4.2.8 FMR15 Bit When the FMR02 bit is set to 1 (rewrite enabled) and the FMR15 bit is set to 0 (rewrite enabled), block 0 accepts program and block erase commands. 20.4.2.9 FMR16 Bit When the FMR02 bit is set to 1 (rewrite enabled) and the FMR16 bit is set to 0 (rewrite enabled), block 1 accepts program and block erase commands. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 271 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version 20.4.2.10 FMR40 Bit The suspend function is enabled by setting the FMR40 bit to 1 (enable). 20.4.2.11 FMR41 Bit In EW0 mode, the MCU enters erase-suspend mode when the FMR41 bit is set to 1 by a program. The FMR41 bit is automatically set to 1 (request erase-suspend) when an interrupt request of an enabled interrupt is generated in EW1 mode, and then the MCU enters erase-suspend mode. Set the FMR41 bit to 0 (erase restarts) when the auto-erase operation restarts. 20.4.2.12 FMR42 Bit In EW0 mode, the MCU enters program-suspend mode when the FMR42 bit is set to 1 by a program. The FMR42 bit is automatically set to 1 (request program-suspend) when an interrupt request of an enabled interrupt is generated in EW1 mode, and then the MCU enters program-suspend mode. Set the FMR42 bit to 0 (program restart) when the auto-program operation restarts. 20.4.2.13 FMR43 Bit When the auto-erase operation starts, the FMR43 bit is set to 1 (erase execution in progress). The FMR43 bit remains set to 1 (erase execution in progress) during erase-suspend operation. When the auto-erase operation ends, the FMR43 bit is set to 0 (erase not executed). 20.4.2.14 FMR44 Bit When the auto-program operation starts, the FMR44 bit is set to 1 (program execution in progress). The FMR44 bit remains set to 1 (program execution in progress) during program-suspend operation. When the auto-program operation ends, the FMR44 bit is set to 0 (program not executed). 20.4.2.15 FMR46 Bit The FMR46 bit is set to 0 (reading disabled) during auto-program or auto-erase execution and set to 1 (reading enabled) in suspend mode. Do not access the flash memory while this bit is set to 0. 20.4.2.16 FMR47 Bit Power consumption when reading the flash memory can be reduced by setting the FMR47 bit to 1 (enabled) in low-speed on-chip oscillator mode (XIN clock stops). Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 272 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version Flash Memory Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol FMR0 Bit Symbol FMR00 FMR01 FMR02 Address 01B7h ____ After Reset 00000001b Function 0 : Busy (w riting or erasing in progress) 1 : Ready 0 : CPU rew rite mode disabled 1 : CPU rew rite mode enabled 0 : Disables rew rite 1 : Enables rew rite 0 : Enables flash memory operation 1 : Stops flash memory (enters low -pow er consumption state and flash memory is reset) Set to 0. 0 : Completed successfully 1 : Terminated by error 0 : Completed successfully 1 : Terminated by error RW RO RW RW Bit Name RY/BY s tatus flag CPU rew rite mode select bit(1) Blocks 0, 1 rew rite enable bit(2, 6) Flash memory stop bit(3, 5) FMSTP RW — (b5-b4) FMR06 FMR07 Reserved bits Program status flag(4) Erase status flag(4) RW RO RO NOTES: 1. To set this bit to 1, set it to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit to 0 and setting it to 1. Enter read array mode and set this bit to 0. 2. Set this bit to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1. Do not generate an interrupt betw een setting the bit to 0 and setting it to 1. 3. Set this bit by a program transferred to the RAM. 4. This bit is set to 0 by executing the clear status command. 5. This bit is enabled w hen the FMR01 bit is set to 1 (CPU rew rite mode enabled). When the FMR01 bit is set to 0, w riting 1 to the FMSTP bit causes the FMSTP bit to be set to 1. The flash memory does not enter low -pow er consumption state nor is it reset. 6. When setting the FMR01 bit to 0 (CPU rew rite mode disabled), the FMR02 bit is set to 0 (disables rew rite). Figure 20.5 FMR0 Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 273 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version Flash Memory Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 1 000 Symbol Address 01B5h FMR1 Bit Symbol Bit Name — Reserved bit (b0) FMR11 — (b4-b2) FMR15 FMR16 — (b7) EW1 mode select bit Reserved bits Block 0 rew rite disable bit Block 1 rew rite disable bit Reserved bit (2,3) (1, 2) After Reset 1000000Xb Function When read, the content is undefined. 0 : EW0 mode 1 : EW1 mode Set to 0. 0 : Enables rew rite 1 : Disables rew rite 0 : Enables rew rite 1 : Disables rew rite Set to 1. RW RO RW RW RW RW RW (2,3) NOTES: 1. To set this bit to 1, set it to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1 (CPU rew rite mode enable) . Do not generate an interrupt betw een setting the bit to 0 and setting it to 1. 2. This bit is set to 0 by setting the FMR01 bit in the FMR0 register to 0 (CPU rew rite mode disabled). 3. When the FMR01 bit is set to 1 (CPU rew rite mode enabled), bits FMR15 and FMR16 can be w ritten to. To set this bit to 0, set it to 0 immediately after setting it first to 1. To set this bit to 1, set it to 1. Figure 20.6 FMR1 Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 274 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version Flash Memory Control Register 4 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol FMR4 Bit Symbol FMR40 FMR41 FMR42 FMR43 FMR44 — (b5) FMR46 FMR47 Address 01B3h Bit Name Erase-suspend function enable bit(1) Erase-suspend request bit(2) After Reset 01000000b Function 0 : Disable 1 : Enable 0 : Erase restart 1 : Erase-suspend request RW RW RW RW RO RO RO RO RW Program-suspend request bit(3) 0 : Program restart 1 : Program-suspend request Erase command flag Program command flag Reserved bit Read status flag 0 : Erase not executed 1 : Erase execution in progress 0 : Program not executed 1 : Program execution in progress Set to 0. 0 : Disables reading 1 : Enables reading Low -pow er consumption read 0 : Disable 1 : Enable mode enable bit (1, 4, 5) NOTES: 1. To set this bit to 1, set it to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit to 0 and setting it to 1. 2. This bit is enabled w hen the FMR40 bit is set to 1 (enable) and it can be w ritten to during the period betw een issuing an erase command and completing the erase. (This bit is set to 0 during periods other than the above.) In EW0 mode, it can be set to 0 or 1 by a program. In EW1 mode, it is automatically set to 1 if a maskable interrupt is generated during an erase operation w hile the FMR40 bit is set to 1. Do not set this bit to 1 by a program (0 can be w ritten). 3. The FMR42 bit is enabled only w hen the FMR40 bit is set to 1 (enable) and programming to the FMR42 bit is enabled until auto-programming ends after a program command is generated. (This bit is set to 0 during periods other than the above.) In EW0 mode, 0 or 1 can be programmed to the FMR42 bit by a program. In EW1 mode, the FMR42 bit is automatically set to 1 by generating a maskable interrupt during auto-programming w hen the FMR40 bit is set to 1. 1 cannot be w ritten to the FMR42 bit by a program. 4. In high-speed clock mode and high-speed on-chip oscillator mode, set the FMR47 bit to 0 (disabled). 5. Set the FMR01 bit in the FMR0 register to 0 (CPU rew rite mode disabled) in low -pow er consumption read mode. Figure 20.7 FMR4 Register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 275 of 332 R8C/2E Group, R8C/2F Group Figure 20.8 shows the Timing of Suspend Operation. 20. Flash Memory Version Erasure starts Erasure suspends Programming Programming Programming Programming Erasure starts suspends restarts ends restarts Erasure ends During erasure FMR00 bit in FMR0 register 1 0 During programming During programming During erasure Remains 0 during suspend FMR46 bit in FMR4 register 1 0 FMR44 bit in FMR4 register 1 0 FMR43 bit in FMR4 register 1 0 Remains 1 during suspend Check that the FMR43 bit is set to 1 (during erase execution), and that the erase-operation has not ended. Check that the FMR44 bit is set to 1 (during program execution), and that the program has not ended. Check the status, and that the programming ends normally. Check the status, and that the erasure ends normally. The above figure shows an example of the use of program-suspend during programming following erase-suspend. NOTE: 1. If program-suspend is entered during erase-suspend, always restart programming. Figure 20.8 Timing of Suspend Operation Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 276 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version Figure 20.9 shows How to Set and Exit EW0 Mode. Figure 20.10 shows How to Set and Exit EW1 Mode. EW0 Mode Operating Procedure Rewrite control program Write 0 to the FMR01 bit before writing 1 (CPU rewrite mode enabled)(2) Set registers(1) CM0 and CM1 Execute software commands Transfer a rewrite control program which uses CPU rewrite mode to the RAM. Execute the read array command(3) Jump to the rewrite control program which has been transferred to the RAM. (The subsequent process is executed by the rewrite control program in the RAM.) Write 0 to the FMR01 bit (CPU rewrite mode disabled) Jump to a specified address in the flash memory NOTES: 1. Select 5 MHz or below for the CPU clock by the CM06 bit in the CM0 register and bits CM16 to CM17 in the CM1 register. 2. To set the FMR01 bit to 1, write 0 to the FMR01 bit before writing 1. Do not generate an interrupt between writing 0 and 1. Write to the FMR01 bit in the RAM. 3. Disable the CPU rewrite mode after executing the read array command. Figure 20.9 How to Set and Exit EW0 Mode EW1 Mode Operating Procedure Program in ROM Write 0 to the FMR01 bit before writing 1 (CPU rewrite mode enabled)(1) Write 0 to the FMR11 bit before writing 1 (EW1 mode) Execute software commands Write 0 to the FMR01 bit (CPU rewrite mode disabled) NOTE: 1. To set the FMR01 bit to 1, write 0 to the FMR01 bit before writing 1. Do not generate an interrupt between writing 0 and 1. Figure 20.10 How to Set and Exit EW1 Mode Page 277 of 332 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 R8C/2E Group, R8C/2F Group 20. Flash Memory Version High-speed on-chip oscillator mode and low-speed on-chip oscillator mode (XIN clock stops) program Transfer a high-speed on-chip oscillator mode and low-speed on-chip oscillator mode (XIN clock stops) program to the RAM. Write 0 to the FMR01 bit before writing 1 (CPU rewrite mode enabled) Jump to the high-speed on-chip oscillator mode and low-speed on-chip oscillator mode (XIN clock stops) program which has been transferred to the RAM. (The subsequent processing is executed by the program in the RAM.) Write 1 to the FMSTP bit (flash memory stops. Low power consumption mode)(1) Switch the clock source for the CPU clock. Turn XIN off Process in high-speed on-chip oscillator mode and low-speed on-chip oscillator mode (XIN clock stops) Turn XIN clock on → w ait until oscillation stabilizes → switch the clock source for CPU clock(2) Write 0 to the FMSTP bit (flash memory operation) Write 0 to the FMR01 bit (CPU rewrite mode disabled) NOTES: 1. Set the FMR01 bit to 1 (CPU rewrite mode enabled) before setting the FMSTP bit to 1. 2. Before switching to a different clock source for the CPU, make sure the designated clock is stable. 3. Insert a 30 µs wait time in a program. Do not access to the flash memory during this wait time. Wait until the flash memory circuit stabilizes (30 µs)(3) Jump to a specified address in the flash memory Figure 20.11 Process to Reduce Power Consumption in High-Speed On-Chip Oscillator Mode and Low-Speed On-Chip Oscillator Mode (XIN Clock Stops) Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 278 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version 20.4.3 Software Commands The software commands are described below. Read or write commands and data in 8-bit units. Table 20.4 Software Commands First Bus Cycle Command Read array Read status register Clear status register Program Block erase Mode Write Write Write Write Write Address × × × WA × Data Mode (D7 to D0) FFh 70h Read 50h 40h Write 20h Write Second Bus Cycle Address Data (D7 to D0) × WA BA SRD WD D0h SRD: Status register data (D7 to D0) WA: Write address (Ensure the address specified in the first bus cycle is the same address as the write address specified in the second bus cycle.) WD: Write data (8 bits) BA: Given block address ×: Any specified address in the user ROM area 20.4.3.1 Read Array Command The read array command reads the flash memory. The MCU enters read array mode when FFh is written in the first bus cycle. When the read address is entered in the following bus cycles, the content of the specified address can be read in 8-bit units. Since the MCU remains in read array mode until another command is written, the contents of multiple addresses can be read continuously. In addition, the MCU enters read array mode after a reset. 20.4.3.2 Read Status Register Command The read status register command is used to read the status register. When 70h is written in the first bus cycle, the status register can be read in the second bus cycle (refer to 20.4.4 Status Registers). When reading the status register, specify an address in the user ROM area. Do not execute this command in EW1 mode. The MCU remains in read status register mode until the next read array command is written. 20.4.3.3 Clear Status Register Command The clear status register command sets the status register to 0. When 50h is written in the first bus cycle, bits FMR06 to FMR07 in the FMR0 register and SR4 to SR5 in the status register are set to 0. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 279 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version 20.4.3.4 Program Command The program command writes data to the flash memory in 1-byte units. By writing 40h in the first bus cycle and data in the second bus cycle to the write address, an auto-program operation (data program and verify) will start. Make sure the address value specified in the first bus cycle is the same address as the write address specified in the second bus cycle. The FMR00 bit in the FMR0 register can be used to determine whether auto-programming has completed. When suspend function disabled, the FMR00 bit is set to 0 during auto-programming and set to 1 when autoprogramming completes. When suspend function enabled, the FMR44 bit is set to 1 during auto-programming and set to 0 when autoprogramming completes. The FMR06 bit in the FMR0 register can be used to determine the result of auto-programming after it has been finished (refer to 20.4.5 Full Status Check). Do not write additions to the already programmed addresses. When the FMR02 bit in the FMR0 register is set to 0 (rewriting disabled), or the FMR02 bit is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1 register is set to 1 (rewriting disabled), program commands targeting block 0 are not acknowledged. When the FMR16 bit is set to 1 (rewriting disabled), program commands targeting block 1 are not acknowledged. Figure 20.12 shows Program Command (When Suspend Function Disabled). Figure 20.13 shows Program Command (When Suspend Function Enabled). In EW1 mode, do not execute this command for any address which a rewrite control program is allocated. In EW0 mode, the MCU enters read status register mode at the same time auto-programming starts and the status register can be read. The status register bit 7 (SR7) is set to 0 at the same time auto-programming starts and set back to 1 when auto-programming completes. In this case, the MCU remains in read status register mode until the next read array command is written. The status register can be read to determine the result of auto-programming after auto-programming has completed. Start Write the command code 40h to the write address Write data to the write address FMR00 = 1? No Yes Full status check Program completed Figure 20.12 Program Command (When Suspend Function Disabled) Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 280 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version EW0 Mode Start Maskable interrupt(1) I = 1 (enable interrupt)(3) FMR44 = 1 ? Yes FMR42 = 1(4) No FMR40 = 1 Write the command code 40h to the write address FMR46 = 1 ? Write data to the write address Yes Access flash memory FMR44 = 0 ? Yes Full status check REIT No FMR42 = 0 No Access flash memory Program completed EW1 Mode Start Maskable interrupt (2) I = 1 (enable interrupt) Access flash memory FMR40 = 1 REIT Write the command code 40h Write data to the write address FMR42 = 0 FMR44 = 0 ? Yes Full status check No Program completed NOTES: 1. In EW0 mode, the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the RAM area. 2. td(SR-SUS) is needed until the interrupt request is acknowledged after it is generated. The interrupt to enter suspend should be in interrupt enabled status. 3. When no interrupt is used, the instruction to enable interrupts is not needed. 4. td(SR-SUS) is needed until program is suspended after the FMR42 bit in the FMR4 register is set to 1. Figure 20.13 Program Command (When Suspend Function Enabled) Page 281 of 332 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 R8C/2E Group, R8C/2F Group 20. Flash Memory Version 20.4.3.5 Block Erase When 20h is written in the first bus cycle and D0h is written to a given address of a block in the second bus cycle, an auto-erase operation (erase and verify) of the specified block starts. The FMR00 bit in the FMR0 register can determine whether auto-erasure has completed. The FMR00 bit is set to 0 during auto-erasure and set to 1 when auto-erasure completes. The FMR07 bit in the FMR0 register can be used to determine the result of auto-erasure after auto-erasure has completed (refer to 20.4.5 Full Status Check). When the FMR02 bit in the FMR0 register is set to 0 (rewriting disabled) or the FMR02 bit is set to 1 (rewriting enabled) and the FMR15 bit in the FMR1 register is set to 1 (rewriting disabled), the block erase commands targeting block 0 are not acknowledged. When the FMR16 bit is set to 1 (rewriting disabled), block erase commands targeting block 1 are not acknowledged. Do not use the block erase command during program-suspend. Figure 20.14 shows the Block Erase Command (When Erase-Suspend Function Disabled). Figure 20.15 shows the Block Erase Command (When Erase-Suspend Function Enabled). In EW1 mode, do not execute this command for any address to which a rewrite control program is allocated. In EW0 mode, the MCU enters read status register mode at the same time auto-erasure starts and the status register can be read. The status register bit 7 (SR7) is set to 0 at the same time auto-erasure starts and set back to 1 when auto-erasure completes. In this case, the MCU remains in read status register mode until the next read array command is written. Start Write the command code 20h Write D0h to a given block address FMR00 = 1? No Yes Full status check Block erase completed Figure 20.14 Block Erase Command (When Erase-Suspend Function Disabled) Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 282 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version EW0 Mode Start Maskable interrupt(1) I = 1 (enable interrupt)(3) FMR43 = 1 ? Yes FMR41 = 1(4) No FMR40 = 1 Write the command code 20h FMR46 = 1 ? Write D0h to any block address Yes Access flash memory FMR00 = 1 ? Yes Full status check REIT No FMR41 = 0 No Access flash memory Block erase completed EW1 Mode Start Maskable interrupt(2) I = 1 (enable interrupt) Access flash memory FMR40 = 1 REIT Write the command code 20h Write D0h to any block address FMR41 = 0 FMR00 = 1 ? Yes Full status check No Block erase completed NOTES: 1. In EW0 mode, the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the RAM area. 2. td(SR-SUS) is needed until the interrupt request is acknowledged after it is generated. The interrupt to enter suspend should be in interrupt enabled status. 3. When no interrupt is used, the instruction to enable interrupts is not needed. 4. td(SR-SUS) is needed until erase is suspended after the FMR41 bit in the FMR4 register is set to 1. Figure 20.15 Block Erase Command (When Erase-Suspend Function Enabled) Page 283 of 332 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 R8C/2E Group, R8C/2F Group 20. Flash Memory Version 20.4.4 Status Registers The status register indicates the operating status of the flash memory and whether an erase or program operation has completed normally or in error. Status of the status register can be read by bits FMR00, FMR06, and FMR07 in the FMR0 register. Table 20.5 lists the Status Register Bits. In EW0 mode, the status register can be read in the following cases: • When a given address in the user ROM area is read after writing the read status register command • When a given address in the user ROM area is read after executing the program or block erase command but before executing the read array command. 20.4.4.1 Sequencer Status (SR7 and FMR00 Bits) The sequencer status bits indicate the operating status of the flash memory. SR7 is set to 0 (busy) during autoprogramming and auto-erasure, and is set to 1 (ready) at the same time the operation completes. 20.4.4.2 Erase Status (SR5 and FMR07 Bits) Refer to 20.4.5 Full Status Check. 20.4.4.3 Program Status (SR4 and FMR06 Bits) Refer to 20.4.5 Full Status Check. Table 20.5 Status Register Bits FMR0 Register Bit − − − − FMR06 FMR07 − FMR00 Status Name Reserved Reserved Reserved Reserved Program status Erase status Reserved Sequencer status Description 0 − − − − Completed normally Completed normally − Busy − − − − Error Error − Ready 1 − − − − 0 0 − 1 Value after Reset Status Register Bit SR0 (D0) SR1 (D1) SR2 (D2) SR3 (D3) SR4 (D4) SR5 (D5) SR6 (D6) SR7 (D7) D0 to D7:Indicate the data bus which is read when the read status register command is executed. Bits FMR07 (SR5) to FMR06 (SR4) are set to 0 by executing the clear status register command. When the FMR07 bit (SR5) or FMR06 bit (SR4) is set to 1, the program and block erase commands cannot be accepted. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 284 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version 20.4.5 Full Status Check When an error occurs, bits FMR06 to FMR07 in the FMR0 register are set to 1, indicating the occurrence of an error. Therefore, checking these status bits (full status check) can be used to determine the execution result. Table 20.6 lists the Errors and FMR0 Register Status. Figure 20.16 shows the Full Status Check and Handling Procedure for Individual Errors. Table 20.6 Errors and FMR0 Register Status Error Occurrence Condition • When a command is not written correctly • When invalid data other than that which can be written in the second bus cycle of the block erase command is written (i.e., other than D0h or FFh)(1) • When the program command or block erase command is executed while rewriting is disabled by the FMR02 bit in the FMR0 register, or the FMR15 or FMR16 bit in the FMR1 register. • When an address not allocated in flash memory is input during erase command input • When attempting to erase the block for which rewriting is disabled during erase command input. • When an address not allocated in flash memory is input during write command input. • When attempting to write to a block for which rewriting is disabled during the write command input. • When the block erase command is executed but autoerasure does not complete correctly • When the program command is executed but not autoprogramming does not complete. FRM0 Register (Status Register) Status Error FMR07(SR5) FMR06(SR4) 1 1 Command sequence error 1 0 0 1 Erase error Program error NOTE: 1. The MCU enters read array mode when FFh is written in the second bus cycle of these commands. At the same time, the command code written in the first bus cycle is disabled. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 285 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version Command sequence error Full status check Execute the clear status register command (set these status flags to 0) FMR06 = 1 and FMR07 = 1? No Re-execute the command Yes Command sequence error Check if command is properly input FMR07 = 1? No Yes Erase error Erase error Execute the clear status register command (set these status flags to 0) Erase command re-execution times ≤ 3 times? Yes Yes Re-execute block erase command No Block targeting for erasure cannot be used FMR06 = 1? No Program error Program error Execute the clear status register command (set these status flags to 0) Full status check completed Specify the other address besides the write address where the error occurs for the program address(1) NOTE: 1. To rewrite to the address where the program error occurs, check if the full status check is complete normally and write to the address after the block erase command is executed. Re-execute program command Figure 20.16 Full Status Check and Handling Procedure for Individual Errors Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 286 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version 20.5 Standard Serial I/O Mode In standard serial I/O mode, the user ROM area can be rewritten while the MCU is mounted on-board by using a serial programmer which is suitable for the MCU. There are three types of Standard serial I/O modes: • Standard serial I/O mode 1 ............Clock synchronous serial I/O used to connect with a serial programmer • Standard serial I/O mode 2 ............Clock asynchronous serial I/O used to connect with a serial programmer • Standard serial I/O mode 3 ............Special clock asynchronous serial I/O used to connect with a serial programmer This MCU uses Standard serial I/O mode 2 and Standard serial I/O mode 3. Refer to Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator. Contact the manufacturer of your serial programmer for details. Refer to the user’s manual of your serial programmer for instructions on how to use it. Table 20.7 lists the Pin Functions (Flash Memory Standard Serial I/O Mode 2), Table 20.8 lists the Pin Functions (Flash Memory Standard Serial I/O Mode 3). Figure 20.17 shows Pin Connections for Standard Serial I/O Mode 3. After processing the pins shown in Table 20.8 and rewriting the flash memory using the programmer, apply “H” to the MODE pin and reset the hardware to run a program in the flash memory in single-chip mode. 20.5.1 ID Code Check Function The ID code check function determines whether the ID codes sent from the serial programmer and those written in the flash memory match (refer to 20.3 Functions to Prevent Rewriting of Flash Memory). Table 20.7 Pin VCC,VSS RESET P4_6/XIN P4_7/XOUT P0_0 to P0_7 P1_0 to P1_7 P3_0, P3_1, P3_3 to P3_6 P4_2/VREF P5_3, P5_4 MODE P3_7 P4_5 Pin Functions (Flash Memory Standard Serial I/O Mode 2) Name Power input Reset input P4_6 input/clock input P4_7 input/clock output Input port P0 Input port P1 Input port P3 Input port P4 Input port P5 MODE TXD output RXD input I I I/O I I I I I I/O O I I/O Description Apply the voltage guaranteed for programming and erasure to the VCC pin and 0 V to the VSS pin. Reset input pin. Connect a ceramic resonator or crystal oscillator between the XIN and XOUT pins. Input “H” or “L” level signal or leave the pin open. Input “L”. Serial data output pin. Serial data input pin. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 287 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version Table 20.8 Pin VCC,VSS RESET P4_6/XIN P4_7/XOUT Pin Functions (Flash Memory Standard Serial I/O Mode 3) Name Power input Reset input P4_6 input/clock input I/O Description Apply the voltage guaranteed for programming and erasure to the VCC pin and 0 V to the VSS pin. Reset input pin. I I Connect a ceramic resonator or crystal oscillator between the XIN and XOUT pins when connecting P4_7 input/clock output I/O external oscillator. Apply “H” and “L” or leave the pin open when using as input port. Input port P0 Input port P1 Input port P3 Input port P4 Input port P5 MODE I I I Input “H” or “L” level signal or leave the pin open. P0_0 to P0_7 P1_0 to P1_7 P3_0, P3_1, P3_3 to P3_7 P4_2/VREF, P4_5 P5_3, P5_4 MODE I I I/O Serial data I/O pin. Connect to the flash programmer. 24 23 22 21 20 19 18 17 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 16 15 14 13 R8C/2E Group, R8C/2F Group 12 11 10 9 VSS MODE VCC Connect oscillator circuit(1) Mode setting Signal MODE RESET Value Voltage from programmer Package: PLQP0032GB-A NOTE: 1. It is not necessary to connect an oscillating circuit when operating with the on-chip oscillator clock. VSS → VCC Figure 20.17 Pin Connections for Standard Serial I/O Mode 3 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 288 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version 20.5.1.1 Example of Circuit Application in the Standard Serial I/O Mode Figure 20.18 shows an example of Pin Processing in Standard Serial I/O Mode 2, Figure 20.19 shows an example of Pin Processing in Standard Serial I/O Mode 3. Since the controlled pins vary depending on the programmer, refer to the manual of your serial programmer for details. MCU Data Output TXD Data Input RXD MODE NOTES: 1. In this example, modes are switched between single-chip mode and standard serial I/O mode by controlling the MODE input with a switch. 2. Connecting the oscillation is necessary. Set the main clock frequency 1 MHz to 20 MHz. Refer to Appendix Figure 2.1 Connecting examples with M16C Flash Starter (M3A-0806). Figure 20.18 Pin Processing in Standard Serial I/O Mode 2 MCU MODE I/O MODE Reset input RESET User reset signal NOTES: 1. Controlled pins and external circuits vary depending on the programmer. Refer to the programmer manual for details. 2. In this example, modes are switched between single-chip mode and standard serial I/O mode by connecting a programmer. 3. When operating with the on-chip oscillator clock, it is not necessary to connect an oscillating circuit. Figure 20.19 Pin Processing in Standard Serial I/O Mode 3 Page 289 of 332 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 R8C/2E Group, R8C/2F Group 20. Flash Memory Version 20.6 Parallel I/O Mode Parallel I/O mode is used to input and output software commands, addresses and data necessary to control (read, program, and erase) the on-chip flash memory. Use a parallel programmer which supports this MCU. Contact the manufacturer of the parallel programmer for more information, and refer to the user’s manual of the parallel programmer for details on how to use it. ROM areas shown in Figures 20.1 and 20.2 can be rewritten in parallel I/O mode. 20.6.1 ROM Code Protect Function The ROM code protect function disables the reading and rewriting of the flash memory. (Refer to the 20.3 Functions to Prevent Rewriting of Flash Memory.) Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 290 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version 20.7 20.7.1 Notes on Flash Memory Version CPU Rewrite Mode Operating Speed 20.7.1.1 Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit in the CM0 register and bits CM16 to CM17 in the CM1 register. This does not apply to EW1 mode. 20.7.1.2 Prohibited Instructions The following instructions cannot be used in EW0 mode because they reference internal data in flash memory: UND, INTO, and BRK. 20.7.1.3 Interrupts Table 20.9 lists the EW0 Mode Interrupts and Table 20.10 lists the EW1 Mode Interrupt. Table 20.9 Mode EW0 Mode Interrupts Status When Maskable Interrupt Request is Acknowledged Any interrupt can be used by allocating a vector in RAM When Watchdog Timer, Oscillation Stop Detection, Voltage Monitor 1, or Voltage Monitor 2 Interrupt Request is Acknowledged Once an interrupt request is acknowledged, the auto-programming or auto-erasure is forcibly stopped immediately and the flash memory is reset. Interrupt handling starts after the fixed period and the flash memory restarts. Since the block during auto-erasure or the address during auto-programming is forcibly stopped, the normal value may not be read. Execute autoerasure again and ensure it completes normally. Since the watchdog timer does not stop during the command operation, interrupt requests may be generated. Reset the watchdog timer regularly. EW0 During auto-erasure Auto-programming NOTES: 1. Do not use the address match interrupt while a command is being executed because the vector of the address match interrupt is allocated in ROM. 2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is allocated in block 0. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 291 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version Table 20.10 EW1 Mode Interrupt When Watchdog Timer, Oscillation Stop Detection, Voltage Monitor 1, or Voltage Monitor 2 Interrupt Request is Acknowledged Auto-erasure is suspended after Once an interrupt request is acknowledged, auto-programming or td(SR-SUS) and interrupt auto-erasure is forcibly stopped handling is executed. Autoimmediately and the flash memory is erasure can be restarted by reset. Interrupt handling starts after the setting the FMR41 bit in the FMR4 register to 0 (erase restart) fixed period and the flash memory restarts. Since the block during autoafter interrupt handling erasure or the address during autocompletes. Auto-erasure has priority and the programming is forcibly stopped, the normal value may not be read. Execute interrupt request auto-erasure again and ensure it acknowledgement is put on completes normally. standby. Interrupt handling is Since the watchdog timer does not stop executed after auto-erasure during the command operation, completes. Auto-programming is suspended interrupt requests may be generated. Reset the watchdog timer regularly after td(SR-SUS) and interrupt using the erase-suspend function. handling is executed. Auto-programming can be restarted by setting the FMR42 bit in the FMR4 register to 0 (program restart) after interrupt handling completes. Auto-programming has priority and the interrupt request acknowledgement is put on standby. Interrupt handling is executed after auto-programming completes. When Maskable Interrupt Request is Acknowledged Mode Status EW1 During auto-erasure (erase-suspend function enabled) During auto-erasure (erase-suspend function disabled) During autoprogramming (program suspend function enabled) During autoprogramming (program suspend function disabled) NOTES: 1. Do not use the address match interrupt while a command is executing because the vector of the address match interrupt is allocated in ROM. 2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is allocated in block 0. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 292 of 332 R8C/2E Group, R8C/2F Group 20. Flash Memory Version 20.7.1.4 How to Access Write 0 before writing 1 when setting the FMR01, FMR02, or FMR11 bit to 1. Do not generate an interrupt between writing 0 and 1. 20.7.1.5 Rewriting User ROM Area In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be rewritten correctly. In this case, use standard serial I/O mode. 20.7.1.6 Program Do not write additions to the already programmed address. 20.7.1.7 Entering Stop Mode or Wait Mode Do not enter stop mode or wait mode during erase-suspend. 20.7.1.8 Program and Erase Voltage for Flash Memory To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform programming and erasure at less than 2.7 V. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 293 of 332 R8C/2E Group, R8C/2F Group 21. Electrical Characteristics 21. Electrical Characteristics Table 21.1 Symbol VCC/AVCC VI VO Pd Topr Tstg Absolute Maximum Ratings Parameter Supply voltage Input voltage Output voltage Power dissipation Operating ambient temperature Storage temperature Condition Rated Value −0.3 to 6.5 −0.3 to VCC + 0.3 −0.3 to VCC + 0.3 500 −20 to 85 (N version) / −40 to 85 (D version) −65 to 150 Unit V V V mW °C °C Topr = 25°C Table 21.2 Symbol VCC/AVCC VSS/AVSS VIH VIL IOH(sum) IOH(sum) IOH(peak) IOH(avg) IOL(sum) IOL(sum) IOL(peak) IOL(avg) f(XIN) − Recommended Operating Conditions Parameter Supply voltage Supply voltage Input “H” voltage Input “L” voltage Peak sum output “H” current Average sum output “H” current Peak output “H” current Average output “H” current Conditions Min. 2.7 − 0.8 VCC 0 − − − − − − − − − − − − Sum of all pins IOH(peak) Sum of all pins IOH(avg) Except P1_0 to P1_7 P1_0 to P1_7 Except P1_0 to P1_7 P1_0 to P1_7 Sum of all pins IOL(peak) Standard Typ. − 0 − − − − − − − − − − − − − − − − − − 125 − Max. 5.5 − VCC 0.2 VCC −160 −80 −10 −20 −5 −10 Unit V V V V mA mA mA mA mA mA mA mA mA mA mA mA MHz MHz MHz MHz kHz Peak sum output “L” currents Average sum Sum of all pins IOL(avg) output “L” currents Peak output “L” Except P1_0 to P1_7 currents P1_0 to P1_7 Average output Except P1_0 to P1_7 “L” current P1_0 to P1_7 XIN clock input oscillation frequency System clock OCD2 = 0 XlN clock selected 160 80 10 20 5 10 20 10 20 10 − OCD2 = 1 On-chip oscillator clock selected 3.0 V ≤ VCC ≤ 5.5 V 2.7 V ≤ VCC < 3.0 V 3.0 V ≤ VCC ≤ 5.5 V 2.7 V ≤ VCC < 3.0 V FRA01 = 0 Low-speed on-chip oscillator clock selected FRA01 = 1 High-speed on-chip oscillator clock selected 3.0 V ≤ VCC ≤ 5.5 V FRA01 = 1 High-speed on-chip oscillator clock selected 2.7 V ≤ VCC ≤ 5.5 V 0 0 0 0 − − 20 MHz − − 10 MHz NOTES: 1. VCC = 2.7 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. 2. The average output current indicates the average value of current measured during 100 ms. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 294 of 332 R8C/2E Group, R8C/2F Group 21. Electrical Characteristics P0 P1 P3 P4 P5 30pF Figure 21.1 Ports P0, P1, and P3 to P5 Timing Measurement Circuit Table 21.3 Symbol − − A/D Converter Characteristics Parameter Resolution Absolute accuracy 10-bit mode 8-bit mode 10-bit mode 8-bit mode Vref = AVCC φAD = 10 MHz, Vref = AVCC = 5.0 V φAD = 10 MHz, Vref = AVCC = 5.0 V φAD = 10 MHz, Vref = AVCC = 3.3 V φAD = 10 MHz, Vref = AVCC = 3.3 V Vref = AVCC φAD = 10 MHz, Vref = AVCC = 5.0 V φAD = 10 MHz, Vref = AVCC = 5.0 V 8-bit mode Conditions Standard Min. − − − − − 10 3.3 2.8 2.7 0 Vref = AVCC = 2.7 to 5.5 V Vref = AVCC = 2.7 to 5.5 V 0.25 1 Without sample and hold With sample and hold Typ. − − − − − − − − − − − − Max. 10 ±3 ±2 ±5 ±2 40 − − AVCC AVCC 10 10 Unit Bits LSB LSB LSB LSB kΩ µs µs V V MHz MHz Rladder tconv Vref VIA − Resistor ladder Conversion time 10-bit mode Reference voltage Analog input voltage(2) A/D operating clock frequency NOTES: 1. AVCC = 2.7 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. 2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in 8-bit mode. Table 21.4 Symbol − − tsu RO IVref D/A Converter Characteristics Parameter Resolution Absolute accuracy Setup time Output resistor Reference power input current (NOTE 2) Conditions Standard Min. − − − 4 − Typ. − − − 10 − Max. 8 1.0 3 20 1.5 Unit Bit % µs kΩ mA NOTES: 1. AVCC = 2.7 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. 2. This applies when one D/A converter is used and the value of the DAi register (i = 0 or 1) for the unused D/A converter is 00h. The resistor ladder of the A/D converter is not included. Also, even if the VCUT bit in the ADCON1 register is set to 0 (VREF not connected), IVref flows into the D/A converters. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 295 of 332 R8C/2E Group, R8C/2F Group 21. Electrical Characteristics Table 21.5 Symbol Vcref Vcin Vofs Tcrsp Comparator Characteristics(1) Parameter Comparator reference voltage Comparator input voltage Input offset voltage Response time Conditions Standard Min. 0 −0.3 − − Typ. − − − − Max. VCC−1.2 VCC+0.3 ±100 200 Unit V V mV ns NOTE: 1. VCC = 2.7 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. Table 21.6 Symbol − − − td(SR-SUS) − − − − − − − Flash Memory (Program ROM) Electrical Characteristics Parameter Program/erase endurance(2) Byte program time Block erase time Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Interval from program start/restart until following suspend request Time from suspend until program/erase restart Program, erase voltage Read voltage Program, erase temperature Data hold time(7) Ambient temperature = 55°C Conditions R8C/2E Group R8C/2F Group Standard Min. 100(3) 1,000(3) − − − 650 0 − 2.7 2.7 0 20 Typ. − − 50 0.4 − − − − − − − − Max. − − 400 9 97+CPU clock × 6 cycles − − 3+CPU clock × 4 cycles 5.5 5.5 60 − Unit times times µs s µs µs ns µs V V °C year NOTES: 1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 296 of 332 R8C/2E Group, R8C/2F Group 21. Electrical Characteristics Table 21.7 Symbol − − − − − Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4) Parameter Program/erase endurance(2) Byte program time (program/erase endurance ≤ 1,000 times) Byte program time (program/erase endurance > 1,000 times) Block erase time (program/erase endurance ≤ 1,000 times) Block erase time (program/erase endurance > 1,000 times) Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Interval from program start/restart until following suspend request Time from suspend until program/erase restart Program, erase voltage Read voltage Program, erase temperature Data hold time(9) Ambient temperature = 55 °C Conditions Min. 10,000(3) − − − − − Standard Typ. − 50 65 0.2 0.3 − − − − − − − − Max. − 400 − Unit times µs µs 9 − s s µs µs td(SR-SUS) − − − − − − − 650 0 − 97+CPU clock × 6 cycles − − ns µs 2.7 2.7 −20(8) 3+CPU clock × 4 cycles 5.5 5.5 85 − V V °C year 20 NOTES: 1. VCC = 2.7 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times is the same as that in program ROM. 5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 8. −40°C for D version. 9. The data hold time includes time that the power supply is off or the clock is not supplied. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 297 of 332 R8C/2E Group, R8C/2F Group 21. Electrical Characteristics Suspend request (maskable interrupt request) FMR46 Fixed time Clock-dependent time Access restart td(SR-SUS) Figure 21.2 Time delay until Suspend Table 21.8 Symbol Vdet1 − − Voltage Detection 1 Circuit Electrical Characteristics Parameter Voltage detection level(4) Voltage monitor 1 interrupt request generation time(2) Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(3) MCU operating voltage minimum value VCA26 = 1, VCC = 5.0 V Condition Min. 2.7 − − − Standard Typ. Max. 2.85 3.00 40 0.6 − − − − 100 − Unit V µs µA µs td(E-A) Vccmin 2.7 V NOTES: 1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version). 2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1. 3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0. 4. This parameter shows the voltage detection level when the power supply drops. The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply drops by approximately 0.1 V. Table 21.9 Symbol Vdet2 − − Voltage Detection 2 Circuit Electrical Characteristics Parameter Voltage detection level Voltage monitor 2 interrupt request generation Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(3) time(2) VCA27 = 1, VCC = 5.0 V Condition Min. 3.3 − − − Standard Typ. Max. 3.6 3.9 40 0.6 − − − Unit V µs µA µs td(E-A) 100 NOTES: 1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version). 2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2. 3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2 register to 0. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 298 of 332 R8C/2E Group, R8C/2F Group 21. Electrical Characteristics Table 21.10 Symbol Vpor1 Vpor2 trth Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics Parameter Power-on reset valid voltage(3) Power-on reset valid voltage External power VCC rise gradient(2) Condition Min. − 0 20 Standard Typ. − − − Max. 0.1 2.6 − Unit V V mV/msec NOTES: 1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. 2. This condition (external power VCC rise gradient) does not apply if VCC ≥ 1.0 V. 3. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if −20°C ≤ Topr ≤ 85°C, maintain tw(por1) for 3,000 s or more if −40°C ≤ Topr < −20°C. max. 2.6 V 2.2 V External Power VCC Vpor1 tw(por1) Sampling time(1, 2) trth Vpor2 trth max. 2.6 V Internal reset signal (“L” valid) 1 × 32 fOCO-S NOTES: 1. Ensure that the voltage is 2.2 V or above during the sampling time. 2. The sampling time is fOCO-S divided by 1 × 4 cycles. 1 × 32 fOCO-S Figure 21.3 Reset Circuit Electrical Characteristics Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 299 of 332 R8C/2E Group, R8C/2F Group 21. Electrical Characteristics Table 21.11 Symbol fOCO40M High-speed On-Chip Oscillator Circuit Electrical Characteristics Parameter High-speed on-chip oscillator frequency temperature • supply voltage dependence Condition VCC = 4.75 V to 5.25 V 0°C ≤ Topr ≤ 60°C(2) VCC = 3.0 V to 5.5 V −20°C ≤ Topr ≤ 85°C(2) VCC = 3.0 V to 5.5 V −40°C ≤ Topr ≤ 85°C(2) VCC = 2.7 V to 5.5 V −20°C ≤ Topr ≤ 85°C(2) VCC = 2.7 V to 5.5 V −40°C ≤ Topr ≤ 85°C(2) VCC = 5.0 V ±10% −20°C ≤ Topr ≤ 85°C(2) VCC = 5.0 V ±10% −40°C ≤ Topr ≤ 85°C(2) VCC = 5.0 V, Topr = 25°C VCC = 2.7 V to 5.5 V −20°C ≤ Topr ≤ 85°C Adjust FRA1 register (value after reset) to −1 VCC = 5.0 V, Topr = 25°C Min. 39.2 38.8 38.4 38 37.6 38.8 38.4 − −3% Standard Typ. 40 40 40 40 40 40 40 36.864 − − +0.3 Max. 40.8 41.2 41.6 42 42.4 40.8 40.8 − 3% Unit MHz MHz MHz MHz MHz MHz MHz MHz % − MHz µs µA High-speed on-chip oscillator frequency when correction value in FRA7 register is written to FRA1 register − − − − Value in FRA1 register after reset Oscillation frequency adjustment unit of highspeed on-chip oscillator Oscillation stability time Self power consumption at oscillation 08h − − − F7h − 100 − 10 400 NOTES: 1. VCC = 2.7 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. 2. These standard values show when the FRA1 register value after reset is assumed. Table 21.12 Symbol fOCO-S − − Low-speed On-Chip Oscillator Circuit Electrical Characteristics Parameter Low-speed on-chip oscillator frequency Oscillation stability time Self power consumption at oscillation Condition Min. 30 − − Standard Typ. 125 10 15 Max. 250 100 − Unit kHz µs µA VCC = 5.0 V, Topr = 25°C NOTE: 1. VCC = 2.7 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. Table 21.13 Symbol td(P-R) td(R-S) Power Supply Circuit Timing Characteristics Parameter Condition Min. 1 − Time for internal power supply stabilization during power-on(2) STOP exit time(3) Standard Typ. Max. − 2000 − Unit µs µs 150 NOTES: 1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = 25°C. 2. Waiting time until the internal power supply generation circuit stabilizes during power-on. 3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 300 of 332 R8C/2E Group, R8C/2F Group 21. Electrical Characteristics Table 21.14 Symbol VOH Electrical Characteristics (1) [VCC = 5 V] Parameter Condition IOH = −5 mA IOH = −200 µA Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW IOL = 5 mA IOL = 200 µA Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW Standard Min. Typ. VCC − 2.0 − VCC − 0.5 − VCC − 2.0 − VCC − 2.0 − VCC − 2.0 − VCC − 2.0 − − − − − − − − − − − − − 0.1 0.5 Max. VCC VCC VCC VCC VCC VCC 2.0 0.45 2.0 2.0 2.0 2.0 − Unit V V V V V V V V V V V V V Output “H” voltage Except P1_0 to P1_7, XOUT P1_0 to P1_7 XOUT IOH = −10 mA IOH = −5 mA IOH = −1 mA IOH = −500 µA VOL Output “L” voltage Except P1_0 to P1_7, XOUT P1_0 to P1_7 XOUT IOL = 10 mA IOL = 5 mA IOL = 1 mA IOL = 500 µA VT+-VT- Hysteresis INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, CLK0 RESET VI = 5 V, VCC = 5 V VI = 0 V, VCC = 5 V VI = 0 V, VCC = 5 V 0.1 − − 1.0 − − − V µA µA kΩ MΩ IIH IIL RPULLUP RfXIN VRAM Input “H” current Input “L” current Pull-up resistance Feedback XIN resistance RAM hold voltage 5.0 −5.0 30 − 1.8 50 1.0 − 167 − − During stop mode V NOTE: 1. VCC = 4.2 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 20 MHz, unless otherwise specified. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 301 of 332 R8C/2E Group, R8C/2F Group 21. Electrical Characteristics Table 21.15 Electrical Characteristics (2) [Vcc = 5 V] (Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.) Condition XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 Symbol ICC Parameter Power supply High-speed clock mode current (VCC = 3.3 to 5.5 V) Single-chip mode, output pins are open, other pins are VSS Min. − Standard Typ. Max. 10 17 Unit mA − 9 15 mA − 6 − mA − 5 − mA − 4 − mA − 2.5 − mA High-speed on-chip oscillator mode XIN clock off High-speed on-chip oscillator on fOCO = 20 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 20 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 − 10 15 mA − 4 − mA − 5.5 10 mA − 2.5 − mA Low-speed on-chip oscillator mode Wait mode XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = 0 VCA20 = 1 − 130 300 µA − 25 75 µA − 23 60 µA Stop mode XIN clock off, Topr = 25°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = 0 XIN clock off, Topr = 85°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = 0 − 0.8 3.0 µA − 1.2 − µA Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 302 of 332 R8C/2E Group, R8C/2F Group Timing Requirements (Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V] Table 21.16 Symbol tc(XIN) tWH(XIN) tWL(XIN) XIN input cycle time XIN input “H” width XIN input “L” width 21. Electrical Characteristics XIN Input Parameter Standard Min. Max. 50 − 25 − 25 − Unit ns ns ns tC(XIN) tWH(XIN) VCC = 5 V XIN input tWL(XIN) Figure 21.4 XIN Input Timing Diagram when VCC = 5 V Table 21.17 Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO) TRAIO Input Parameter TRAIO input cycle time TRAIO input “H” width TRAIO input “L” width Standard Min. Max. 100 − 40 − 40 − Unit ns ns ns tC(TRAIO) tWH(TRAIO) VCC = 5 V TRAIO input tWL(TRAIO) Figure 21.5 TRAIO Input Timing Diagram when VCC = 5 V Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 303 of 332 R8C/2E Group, R8C/2F Group 21. Electrical Characteristics Table 21.18 Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Serial Interface Parameter CLK0 input cycle time CLK0 input “H” width CLK0 input “L” width TXD0 output delay time TXD0 hold time RXD0 input setup time RXD0 input hold time Standard Min. Max. 200 − 100 − 100 − − 50 0 − 50 − 90 − Unit ns ns ns ns ns ns ns tC(CK) tW(CKH) VCC = 5 V CLK0 tW(CKL) th(C-Q) TXD0 td(C-Q) tsu(D-C) th(C-D) RXD0 Figure 21.6 Serial Interface Timing Diagram when VCC = 5 V Table 21.19 Symbol tW(INH) tW(INL) External Interrupt INTi (i = 0, 1, 3) Input Parameter INTi input “H” width INTi input “L” width Standard Min. Max. (1) − 250 250(2) − Unit ns ns NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. VCC = 5 V tW(INL) INTi input tW(INH) i = 0, 1, 3 Figure 21.7 External Interrupt INTi Input Timing Diagram when VCC = 5 V Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 304 of 332 R8C/2E Group, R8C/2F Group 21. Electrical Characteristics Table 21.20 Symbol VOH Electrical Characteristics (3) [VCC = 3 V] Parameter Condition IOH = −1 mA Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW IOL = 1 mA Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW IOH = −2 mA IOH = −1 mA Standard Min. Typ. VCC − 0.5 − VCC − 0.5 VCC − 0.5 − − − − − − − − − Output “H” voltage Except P1_0 to P1_7, XOUT P1_0 to P1_7 Max. VCC VCC VCC VCC VCC 0.5 0.5 0.5 0.5 0.5 − Unit V V V V V V V V V V V XOUT IOH = −0.1 mA VCC − 0.5 IOH = −50 µA VCC − 0.5 − VOL Output “L” voltage Except P1_0 to P1_7, XOUT P1_0 to P1_7 IOL = 2 mA IOL = 1 mA IOL = 0.1 mA IOL = 50 µA − − − − XOUT VT+-VT- Hysteresis INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, CLK0 RESET VI = 3 V, VCC = 3 V VI = 0 V, VCC = 3 V VI = 0 V, VCC = 3 V XIN During stop mode 0.1 0.3 0.1 − − 0.4 − − − V µA µA kΩ MΩ V IIH IIL RPULLUP RfXIN VRAM Input “H” current Input “L” current Pull-up resistance Feedback resistance RAM hold voltage 4.0 −4.0 66 − 1.8 160 3.0 − 500 − − NOTE: 1. VCC =2.7 to 3.3 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 10 MHz, unless otherwise specified. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 305 of 332 R8C/2E Group, R8C/2F Group 21. Electrical Characteristics Table 21.21 Electrical Characteristics (4) [Vcc = 3 V] (Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.) Parameter Condition XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = 0 VCA20 = 1 XIN clock off, Topr = 25°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = 0 XIN clock off, Topr = 85°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = 0 Min. − Standard Typ. Max. 6 − Unit mA Symbol ICC Power supply current High-speed (VCC = 2.7 to 3.3 V) clock mode Single-chip mode, output pins are open, other pins are VSS − 2 − mA High-speed on-chip oscillator mode − 5 9 mA − 2 − mA Low-speed on-chip oscillator mode Wait mode − 130 300 µA − 25 70 µA − 23 55 µA Stop mode − 0.7 3.0 µA − 1.1 − µA Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 306 of 332 R8C/2E Group, R8C/2F Group Timing requirements (Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C) [VCC = 3 V] Table 21.22 Symbol tc(XIN) tWH(XIN) tWL(XIN) XIN input cycle time XIN input “H” width XIN input “L” width 21. Electrical Characteristics XIN Input Parameter Standard Min. Max. 100 − 40 − 40 − Unit ns ns ns tC(XIN) tWH(XIN) VCC = 3 V XIN input tWL(XIN) Figure 21.8 XIN Input Timing Diagram when VCC = 3 V Table 21.23 Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO) TRAIO Input Parameter TRAIO input cycle time TRAIO input “H” width TRAIO input “L” width Standard Min. Max. 300 − 120 − 120 − Unit ns ns ns tC(TRAIO) tWH(TRAIO) VCC = 3 V TRAIO input tWL(TRAIO) Figure 21.9 TRAIO Input Timing Diagram when VCC = 3 V Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 307 of 332 R8C/2E Group, R8C/2F Group 21. Electrical Characteristics Table 21.24 Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Serial Interface Parameter CLK0 input cycle time CLK0 input “H” width CLK0 Input “L” width TXD0 output delay time TXD0 hold time RXD0 input setup time RXD0 input hold time Standard Min. Max. 300 − 150 − 150 − − 80 0 − 70 − 90 − Unit ns ns ns ns ns ns ns tC(CK) tW(CKH) VCC = 3 V CLK0 tW(CKL) th(C-Q) TXD0 td(C-Q) tsu(D-C) th(C-D) RXD0 Figure 21.10 Serial Interface Timing Diagram when VCC = 3 V Table 21.25 Symbol tW(INH) tW(INL) External Interrupt INTi (i = 0, 1, 3) Input Parameter INTi input “H” width INTi input “L” width Standard Min. Max. − 380(1) 380(2) − Unit ns ns NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. VCC = 3 V tW(INL) INTi input tW(INH) i = 0, 1, 3 Figure 21.11 External Interrupt INTi Input Timing Diagram when VCC = 3 V Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 308 of 332 R8C/2E Group, R8C/2F Group 22. Usage Notes 22. Usage Notes 22.1 22.1.1 Notes on Clock Generation Circuit Stop Mode When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit to 1 (stop mode) and the program stops. Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets the CM10 bit to 1. • Program example to enter stop mode BCLR BSET FSET BSET JMP.B LABEL_001 : NOP NOP NOP NOP 1,FMR0 0,PRCR I 0,CM1 LABEL_001 ; CPU rewrite mode disabled ; Protect disabled ; Enable interrupt ; Stop mode 22.1.2 Wait Mode When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the program stops. Insert at least 4 NOP instructions after the WAIT instruction. • Program example to execute the WAIT instruction BCLR 1,FMR0 FSET I WAIT NOP NOP NOP NOP ; CPU rewrite mode disabled ; Enable interrupt ; Wait mode 22.1.3 Oscillation Stop Detection Function Since the oscillation stop detection function cannot be used if the XIN clock frequency is 2 MHz or below, set bits OCD1 to OCD0 to 00b. 22.1.4 Oscillation Circuit Constants Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system. To use this MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1 register to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and connect the feedback resistor to the chip externally. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 309 of 332 R8C/2E Group, R8C/2F Group 22. Usage Notes 22.2 22.2.1 Notes on Interrupts Reading Address 00000h Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At this time, the acknowledged interrupt IR bit is set to 0. If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be generated. 22.2.2 SP Setting Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset. Therefore, if an interrupt is acknowledged before setting a value in the SP, the program may run out of control. 22.2.3 External Interrupt and Key Input Interrupt Either “L” level or an “H” level of width shown in the Electrical Characteristics is necessary for the signal input to pins INT0, INT1, INT3 and pins KI0 to KI3, regardless of the CPU clock. For details, refer to Table 21.19 (VCC = 5V), Table 21.25 (VCC = 3V) External Interrupt INTi (i = 0, 1, 3) Input. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 310 of 332 R8C/2E Group, R8C/2F Group 22. Usage Notes 22.2.4 Changing Interrupt Sources The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source. In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to individual software interrupt numbers, polarities, and timing. Therefore, if a mode change of a peripheral function involves interrupt sources, edge polarities, and timing, set the IR bit to 0 (no interrupt requested) after the change. Refer to the individual peripheral function for its related interrupts. Figure 22.1 shows an Example of Procedure for Changing Interrupt Sources. Interrupt source change Disable interrupts(2, 3) Change interrupt source (including mode of peripheral function) Set the IR bit to 0 (interrupt not requested) using the MOV instruction(3) Enable interrupts (2, 3) Change completed IR bit: The interrupt control register bit of an interrupt whose source is changed. NOTES: 1. Execute the above settings individually. Do not execute two or more settings at once (by one instruction). 2. To prevent interrupt requests from being generated, disable the peripheral function before changing the interrupt source. In this case, use the I flag if all maskable interrupts can be disabled. If all maskable interrupts cannot be disabled, use bits ILVL0 to ILVL2 of the interrupt whose source is changed. 3. Refer to 12.6.5 Changing Interrupt Control Register for the instructions to be used and usage notes. Figure 22.1 Example of Procedure for Changing Interrupt Sources Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 311 of 332 R8C/2E Group, R8C/2F Group 22. Usage Notes 22.2.5 Changing Interrupt Control Register Contents (a) The contents of an interrupt control register can only be changed while no interrupt requests corresponding to that register are generated. If interrupt requests may be generated, disable interrupts before changing the interrupt control register contents. (b) When changing the contents of an interrupt control register after disabling interrupts, be careful to choose appropriate instructions. Changing any bit other than IR bit If an interrupt request corresponding to a register is generated while executing the instruction, the IR bit may not be set to 1 (interrupt requested), and the interrupt request may be ignored. If this causes a problem, use the following instructions to change the register: AND, OR, BCLR, BSET Changing IR bit If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used. Therefore, use the MOV instruction to set the IR bit to 0. (c) When disabling interrupts using the I flag, set the I flag as shown in the sample programs below. Refer to (b) regarding changing the contents of interrupt control registers by the sample programs. Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before the interrupt control register is changed for reasons of the internal bus or the instruction queue buffer. Example 1: Use NOP instructions to prevent I flag from being set to 1 before interrupt control register is changed INT_SWITCH1: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h NOP ; NOP FSET I ; Enable interrupts Example 2: Use dummy read to delay FSET instruction INT_SWITCH2: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h MOV.W MEM,R0 ; Dummy read FSET I ; Enable interrupts Example 3: Use POPC instruction to change I flag INT_SWITCH3: PUSHC FLG FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h POPC FLG ; Enable interrupts Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 312 of 332 R8C/2E Group, R8C/2F Group 22. Usage Notes 22.3 22.3.1 Notes on Timers Notes on Timer RA • Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the • count starts. Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by the MCU. Consequently, the timer value may be updated during the period when these two registers are being read. In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by writing 0 to these bits by a program. However, these bits remain unchanged if 1 is written. When using the READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0 although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or TUNDF bit which is not supposed to be set to 0 with the MOV instruction. When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts. The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts. When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler immediately after the count starts, then set the TEDGF bit to 0. The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1 (count starts) while the count is stopped. During this time, do not access registers associated with timer RA(1) other than the TCSTF bit. Timer RA starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count). The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RA(1) other than the TCSTF bit. NOTE: 1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA. • • • • • • When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the count source clock for each write interval. • When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 313 of 332 R8C/2E Group, R8C/2F Group 22. Usage Notes 22.3.2 Notes on Timer RB • Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the count starts. • Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the MCU. Consequently, the timer value may be updated during the period when these two registers are being read. • In programmable one-shot generation mode and programmable wait one-shot generation mode, when setting the TSTART bit in the TRBCR register to 0, 0 (stops counting) or setting the TOSSP bit in the TRBOCR register to 1 (stops one-shot), the timer reloads the value of reload register and stops. Therefore, in programmable one-shot generation mode and programmable wait one-shot generation mode, read the timer count value before the timer stops. • The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to 1 (count starts) while the count is stopped. During this time, do not access registers associated with timer RB(1)other than the TCSTF bit. Timer RB starts counting at the first valid edge of the count source after the TCSTF bit is set to 1 (during count). The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RB(1) other than the TCSTF bit. NOTE: 1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and TRBPR. • If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately. • If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes after one or two cycles of the count source have elapsed. If the TOSSP bit is written to 1 during the period between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit may be set to either 0 or 1. 22.3.2.1 Timer mode The following workaround should be performed in timer mode. To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: • When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 314 of 332 R8C/2E Group, R8C/2F Group 22. Usage Notes 22.3.2.2 Programmable waveform generation mode The following three workarounds should be performed in programmable waveform generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: • When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval. (2) To change registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), synchronize the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period A shown in Figures 22.2 and 22.3. The following shows the detailed workaround examples. • Workaround example (a): As shown in Figure 22.2, write to registers TRBSC and TRBPR in the timer RB interrupt routine. These write operations must be completed by the beginning of period A. Period A Count source/ prescaler underflow signal TRBO pin output Primary period Secondary period IR bit in TRBIC register (a) Interrupt request is acknowledged (b) Ensure sufficient time Interrupt request is generated Instruction in Interrupt sequence interrupt routine Set the secondary and then the primary register immediately (a) Period between interrupt request generation and the completion of execution of an instruction. The length of time varies depending on the instruction being executed. The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as the divisor). (b) 20 cycles. 21 cycles for address match and single-step interrupts. Figure 22.2 Workaround Example (a) When Timer RB interrupt is Used Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 315 of 332 R8C/2E Group, R8C/2F Group 22. Usage Notes • Workaround example (b): As shown in Figure 22.3 detect the start of the primary period by the TRBO pin output level and write to registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A. If the port register’s bit value is read after the port direction register’s bit corresponding to the TRBO pin is set to 0 (input mode), the read value indicates the TRBO pin output value. Period A Count source/ prescaler underflow signal TRBO pin output Read value of the port register’s bit corresponding to the TRBO pin (when the bit in the port direction register is set to 0) Primary period Secondary period (i) (ii) (iii) Ensure sufficient time The TRBO output inversion is detected at the end of the secondary period. Upon detecting (i), set the secondary and then the primary register immediately. Figure 22.3 Workaround Example (b) When TRBO Pin Output Value is Read (3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case, registers TRBPRE and TRBPR are initialized and their values are set to the values after reset. 22.3.2.3 Programmable one-shot generation mode The following two workarounds should be performed in programmable one-shot generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: • When the TRBPRE register is written continuously during count operation (TCSTF bit is set to 1), allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval. (2) Do not set both the TRBPRE and TRBPR registers to 00h. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 316 of 332 R8C/2E Group, R8C/2F Group 22. Usage Notes 22.3.2.4 Programmable wait one-shot generation mode The following three workarounds should be performed in programmable wait one-shot generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: • When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval. (2) Do not set both the TRBPRE and TRBPR registers to 00h. (3) Set registers TRBSC and TRBPR using the following procedure. (a) To use “INT0 pin one-shot trigger enabled” as the count start condition Set the TRBSC register and then the TRBPR register. At this time, after writing to the TRBPR register, allow an interval of 0.5 or more cycles of the count source before trigger input from the INT0 pin. (b) To use “writing 1 to TOSST bit” as the start condition Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the TRBPR register, allow an interval of 0.5 or more cycles of the count source before writing to the TOSST bit. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 317 of 332 R8C/2E Group, R8C/2F Group 22. Usage Notes 22.3.3 Notes on Timer RC TRC Register 22.3.3.1 • The following note applies when the CCLR bit in the TRCCR1 register is set to 1 (clear TRC register at compare match with TRCGRA register). When using a program to write a value to the TRC register while the TSTART bit in the TRCMR register is set to 1 (count starts), ensure that the write does not overlap with the timing with which the TRC register is set to 0000h. If the timing of the write to the TRC register and the setting of the TRC register to 0000h coincide, the write value will not be written to the TRC register and the TRC register will be set to 0000h. • Reading from the TRC register immediately after writing to it can result in the value previous to the write being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions. Program Example MOV.W #XXXXh, TRC ;Write JMP.B L1 ;JMP.B instruction L1: MOV.W TRC,DATA ;Read 22.3.3.2 TRCSR Register Reading from the TRCSR register immediately after writing to it can result in the value previous to the write being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions. Program Example MOV.B #XXh, TRCSR ;Write JMP.B L1 ;JMP.B instruction L1: MOV.B TRCSR,DATA ;Read 22.3.3.3 Count Source Switching • Stop the count before switching the count source. Switching procedure (1) Set the TSTART bit in the TRCMR register to 0 (count stops). (2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register. • After switching the count source from fOCO40M to another clock, allow a minimum of two cycles of f1 to elapse after changing the clock setting before stopping fOCO40M. Switching procedure (1) Set the TSTART bit in the TRCMR register to 0 (count stops). (2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register. (3) Wait for a minimum of two cycles of f1. (4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off). 22.3.3.4 Input Capture Function • The pulse width of the input capture signal should be three cycles or more of the timer RC operation clock (refer to Table 14.11 Timer RC Operation Clock). • The value of the TRC register is transferred to the TRCGRj register one or two cycles of the timer RC operation clock after the input capture signal is input to the TRCIOj (j = A, B, C, or D) pin (when the digital filter function is not used). 22.3.3.5 TRCMR Register in PWM2 Mode When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA register), do not set the TRCMR register at compare match timing of registers TRC and TRCGRA. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 318 of 332 R8C/2E Group, R8C/2F Group 22. Usage Notes 22.3.4 Notes on Timer RE Starting and Stopping Count 22.3.4.1 Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates count start or stop. Bits TSTART and TCSTF are in the TRECR1 register. Timer RE starts counting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to 1. During this time, do not access registers associated with timer RE(1) other than the TCSTF bit. Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0 (count stops). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF bit. NOTE: 1. Registers associated with timer RE: TRESEC, TREMIN, TRECR1, TRECR2, and TRECSR. 22.3.4.2 Register Setting Write to the following registers or bits when timer RE is stopped. • Registers TRESEC, TREMIN, and TRECR2 • INT bit in TRECR1 register • Bits RCS0 to RCS2 and b3 in TRECSR register Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped). Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the TRECR2 register. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 319 of 332 R8C/2E Group, R8C/2F Group 22. Usage Notes 22.4 Notes on Serial Interface • When reading data from the U0RB register either in the clock synchronous serial I/O mode or in the clock asynchronous serial I/O mode, ensure the data is read in 16-bit units. When the high-order byte of the U0RB register is read, bits PER and FER in the U0RB register and the RI bit in the U0C1 register are set to 0. The check receive errors, read the U0RB register and then use the read data. Example (when reading receive buffer register): MOV.W 00A6H,R0 ; Read the U0RB register • When writing data to the U0TB register in the clock asynchronous serial I/O mode with 9-bit transfer data length, write data to the high-order byte first then the low-order byte, in 8-bit units. Example (when reading transmit buffer register): MOV.B #XXH,00A3H ; Write the high-order byte of U0TB register MOV.B #XXH,00A2H ; Write the low-order byte of U0TB register Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 320 of 332 R8C/2E Group, R8C/2F Group 22. Usage Notes 22.5 Notes on Hardware LIN For the time-out processing of the header and response fields, use another timer to measure the duration of time with a Synch Break detection interrupt as the starting point. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 321 of 332 R8C/2E Group, R8C/2F Group 22. Usage Notes 22.6 Notes on A/D Converter • Write to each bit (other than bit 6) in the ADCON0 register, each bit in the ADCON1 register, or the SMP bit in the ADCON2 register when A/D conversion is stopped (before a trigger occurs). When the VCUT bit in the ADCON1 register is changed from 0 (VREF not connected) to 1 (VREF connected), wait for at least 1 µs before starting the A/D conversion. After changing the A/D operating mode, select an analog input pin again. When using the one-shot mode, ensure that A/D conversion is completed before reading the AD register. The IR bit in the ADIC register or the ADST bit in the ADCON0 register can be used to determine whether A/D conversion is completed. When using the repeat mode, select the frequency of the A/D converter operating clock φAD or more for the CPU clock during A/D conversion. Do not select the fOCO-F for the φAD. If the ADST bit in the ADCON0 register is set to 0 (A/D conversion stops) by a program and A/D conversion is forcibly terminated during an A/D conversion operation, the conversion result of the A/D converter will be undefined. If the ADST bit is set to 0 by a program, do not use the value of the AD register. Connect 0.1 µF capacitor between the P4_2/VREF pin and AVSS pin. Do not enter stop mode during A/D conversion. Do not enter wait mode when the CM02 bit in the CM0 register is set to 1 (peripheral function clock stops in wait mode) during A/D conversion. • • • • • • • Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 322 of 332 R8C/2E Group, R8C/2F Group 22. Usage Notes 22.7 22.7.1 Notes on Flash Memory Version CPU Rewrite Mode Operating Speed 22.7.1.1 Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit in the CM0 register and bits CM16 to CM17 in the CM1 register. This does not apply to EW1 mode. 22.7.1.2 Prohibited Instructions The following instructions cannot be used in EW0 mode because they reference internal data in flash memory: UND, INTO, and BRK. 22.7.1.3 Interrupts Table 22.1 lists the EW0 Mode Interrupts and Table 22.2 lists the EW1 Mode Interrupt. Table 22.1 EW0 Mode Interrupts Mode Status EW0 During auto-erasure When Maskable Interrupt Request is Acknowledged Any interrupt can be used by allocating a vector in RAM Auto-programming When Watchdog Timer, Oscillation Stop Detection, Voltage Monitor 1, or Voltage Monitor 2 Interrupt Request is Acknowledged Once an interrupt request is acknowledged, the auto-programming or auto-erasure is forcibly stopped immediately and the flash memory is reset. Interrupt handling starts after the fixed period and the flash memory restarts. Since the block during auto-erasure or the address during auto-programming is forcibly stopped, the normal value may not be read. Execute autoerasure again and ensure it completes normally. Since the watchdog timer does not stop during the command operation, interrupt requests may be generated. Reset the watchdog timer regularly. NOTES: 1. Do not use the address match interrupt while a command is being executed because the vector of the address match interrupt is allocated in ROM. 2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is allocated in block 0. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 323 of 332 R8C/2E Group, R8C/2F Group 22. Usage Notes Table 22.2 EW1 Mode Interrupt Mode Status EW1 During auto-erasure (erase-suspend function enabled) During auto-erasure (erase-suspend function disabled) During autoprogramming (program suspend function enabled) During autoprogramming (program suspend function disabled) When Watchdog Timer, Oscillation Stop Detection, Voltage Monitor 1, or Voltage Monitor 2 Interrupt Request is Acknowledged Auto-erasure is suspended after Once an interrupt request is acknowledged, auto-programming or td(SR-SUS) and interrupt auto-erasure is forcibly stopped handling is executed. Autoimmediately and the flash memory is erasure can be restarted by reset. Interrupt handling starts after the setting the FMR41 bit in the FMR4 register to 0 (erase restart) fixed period and the flash memory restarts. Since the block during autoafter interrupt handling erasure or the address during autocompletes. Auto-erasure has priority and the programming is forcibly stopped, the normal value may not be read. Execute interrupt request auto-erasure again and ensure it acknowledgement is put on completes normally. standby. Interrupt handling is Since the watchdog timer does not stop executed after auto-erasure during the command operation, completes. Auto-programming is suspended interrupt requests may be generated. Reset the watchdog timer regularly after td(SR-SUS) and interrupt using the erase-suspend function. handling is executed. Auto-programming can be restarted by setting the FMR42 bit in the FMR4 register to 0 (program restart) after interrupt handling completes. Auto-programming has priority and the interrupt request acknowledgement is put on standby. Interrupt handling is executed after auto-programming completes. When Maskable Interrupt Request is Acknowledged NOTES: 1. Do not use the address match interrupt while a command is executing because the vector of the address match interrupt is allocated in ROM. 2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is allocated in block 0. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 324 of 332 R8C/2E Group, R8C/2F Group 22. Usage Notes 22.7.1.4 How to Access Write 0 before writing 1 when setting the FMR01, FMR02, or FMR11 bit to 1. Do not generate an interrupt between writing 0 and 1. 22.7.1.5 Rewriting User ROM Area In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be rewritten correctly. In this case, use standard serial I/O mode. 22.7.1.6 Program Do not write additions to the already programmed address. 22.7.1.7 Entering Stop Mode or Wait Mode Do not enter stop mode or wait mode during erase-suspend. 22.7.1.8 Program and Erase Voltage for Flash Memory To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform programming and erasure at less than 2.7 V. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 325 of 332 R8C/2E Group, R8C/2F Group 22. Usage Notes 22.8 22.8.1 Notes on Noise Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and Latch-up Connect a bypass capacitor (at least 0.1 µF) using the shortest and thickest write possible. 22.8.2 Countermeasures against Noise Error of Port Control Registers During rigorous noise testing or the like, external noise (mainly power supply system noise) can exceed the capacity of the MCU's internal noise control circuitry. In such cases the contents of the port related registers may be changed. As a firmware countermeasure, it is recommended that the port registers, port direction registers, and pull-up control registers be reset periodically. However, examine the control processing fully before introducing the reset routine as conflicts may be created between the reset routine and interrupt routines. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 326 of 332 R8C/2E Group, R8C/2F Group 23. Notes for On-Chip Debugger 23. Notes for On-Chip Debugger When using the on-chip debugger to develop and debug programs for the R8C/2E Group and R8C/2F Group take note of the following. (1) Some of the user flash memory and RAM areas are used by the on-ship debugger. These areas cannot be accessed by the user. Refer to the on-chip debugger manual for which areas are used. Do not set the address match interrupt (registers AIER, RMAD0, and RMAD1 and fixed vector tables) in a user system. Do not use the BRK instruction in a user system. Debugging is available under the condition of supply voltage VCC = 2.7 to 5.5 V. Debugging with the on-chip debugger under less than 2.7 V is not allowed. (2) (3) (4) Connecting and using the on-chip debugger has some special restrictions. Refer to the on-chip debugger manual for details. Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 327 of 332 R8C/2E Group, R8C/2F Group Appendix 1. Package Dimensions Appendix 1. Package Dimensions Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas Technology website. JEITA Package Code P-LQFP32-7x7-0.80 RENESAS Code PLQP0032GB-A Previous Code 32P6U-A MASS[Typ.] 0.2g HD *1 D 24 17 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1 25 16 HE E c1 *2 c Reference Dimension in Millimeters Symbol Terminal cross section 32 1 ZD Index mark 8 ZE 9 A2 A F A1 L L1 D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 y e *3 Detail F bp x Min Nom Max 6.9 7.0 7.1 6.9 7.0 7.1 1.4 8.8 9.0 9.2 8.8 9.0 9.2 1.7 0.1 0.2 0 0.32 0.37 0.42 0.35 0.09 0.145 0.20 0.125 0° 8° 0.8 0.20 0.10 0.7 0.7 0.3 0.5 0.7 1.0 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 328 of 332 c R8C/2E Group, R8C/2F Group Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator Appendix Figure 2.1 shows a Connection Example with M16C Flash Starter (M3A-0806) and Appendix Figure 2.2 shows a Connection Example with E8 Emulator (R0E000080KCE00). VCC 29 28 25 30 31 26 32 27 1 (2) 24 23 22 21 20 19 18 17 12 13 16 14 15 11 10 9 TXD RESET Connect oscillation circuit (1) VSS 2 3 4 5 6 7 R8C/2E Group, R8C/2F Group MODE 8 10 TXD 7 VSS RXD 4 1 VCC (2) M16C Flash Starter (M3A-0806) RXD NOTES: 1. An oscillation circuit must be connected, even when operating with the on-chip oscillator clock. 2. For development tools only. Appendix Figure 2.1 Connection Example with M16C Flash Starter (M3A-0806) VCC Open collector buffer 4.7kΩ or more User logic 1 2 3 29 28 25 30 31 26 32 27 24 23 22 21 20 19 18 17 12 13 16 14 15 11 10 9 R8C/2E Group, R8C/2F Group Connect oscillation circuit (1) VSS 4 5 6 14 12 10 8 VCC 6 4 2 VSS 13 RESET 4.7kΩ ±10% MODE 7 8 7 MODE E8 emulator (R0E000080KCE00) NOTE: 1. It is not necessary to connect an oscillation circuit when operating with the on-chip oscillator clock. Appendix Figure 2.2 Connection Example with E8 Emulator (R0E000080KCE00) Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 329 of 332 R8C/2E Group, R8C/2F Group Appendix 3. Example of Oscillation Evaluation Circuit Appendix 3. Example of Oscillation Evaluation Circuit Appendix Figure 3.1 shows an Example of Oscillation Evaluation Circuit. VCC 29 28 30 25 26 31 32 27 1 2 24 23 R8C/2E Group, R8C/2F Group RESET Connect oscillation circuit 3 4 22 21 20 19 18 17 VSS 5 6 7 8 12 13 16 14 15 11 10 NOTE: 1. After reset, the XIN clock stops. Write a program to oscillate the XIN clock. 9 Appendix Figure 3.1 Example of Oscillation Evaluation Circuit Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 330 of 332 R8C/2E Group, R8C/2F Group Index Index [A] ACCR0 to ACCR1 ....................................................... 255, 258 ACMR .................................................................................. 259 AD ....................................................................................... 242 ADCON0 ............................................................................. 241 ADCON1 ............................................................................. 242 ADCON2 ............................................................................. 242 ADIC ...................................................................................... 95 AIER .................................................................................... 110 [C] CM0 ....................................................................................... 67 CM0IC ................................................................................... 96 CM1 ....................................................................................... 68 CM1IC ................................................................................... 96 CSPR .................................................................................. 117 [D] DA0 to DA1 ......................................................................... 254 DACON ............................................................................... 254 [F] FMR0 .................................................................................. 273 FMR1 .................................................................................. 274 FMR4 .................................................................................. 275 FRA0 ..................................................................................... 70 FRA1 ..................................................................................... 70 FRA2 ..................................................................................... 70 FRA7 ..................................................................................... 71 [I] INT0IC ................................................................................... 97 INT1IC ................................................................................... 97 INT3IC ................................................................................... 97 INTEN ................................................................................. 104 INTF .................................................................................... 105 [K] KIEN .................................................................................... 108 KUPIC ................................................................................... 95 [L] LINCR ................................................................................. 226 LINST .................................................................................. 227 [O] OCD ...................................................................................... 69 OFS ....................................................................... 26, 117, 268 [P] P1DRR .................................................................................. 51 PDi (i = 0, 1, and 3 to 5) ........................................................ 48 Pi (i = 0, 1, and 3 to 5) ........................................................... 49 PINSR2 ................................................................................. 50 PINSR3 ................................................................................. 50 PM0 ....................................................................................... 63 PM1 ....................................................................................... 63 PMR .............................................................................. 50, 212 PRCR .................................................................................... 89 PUR0 ..................................................................................... 51 PUR1 ..................................................................................... 51 [R] RMAD0 ................................................................................ 110 RMAD1 ................................................................................ 110 [S] S0RIC .................................................................................... 95 S0TIC .................................................................................... 95 [T] TRA ..................................................................................... 124 TRACR ................................................................................ 123 TRAIC .................................................................................... 95 TRAIOC ....................................... 123, 125, 128, 130, 132, 135 TRAMR ................................................................................ 124 TRAPRE .............................................................................. 124 TRBCR ................................................................................ 139 TRBIC .................................................................................... 95 TRBIOC ............................................... 140, 142, 146, 149, 153 TRBMR ................................................................................ 140 TRBOCR ............................................................................. 139 TRBPR ................................................................................ 141 TRBPRE .............................................................................. 141 TRBSC ................................................................................ 141 TRC ..................................................................................... 166 TRCCR1 ...................................................... 163, 186, 190, 195 TRCCR2 .............................................................................. 167 TRCDF ................................................................................ 168 TRCGRA ............................................................................. 166 TRCGRB ............................................................................. 166 TRCGRC ............................................................................. 166 TRCGRD ............................................................................. 166 TRCIC .................................................................................... 96 TRCIER ............................................................................... 164 TRCIOR0 ............................................................. 170, 179, 184 TRCIOR1 ............................................................. 170, 180, 185 TRCMR ................................................................................ 162 TRCOER ............................................................................. 169 TRCSR ................................................................................ 165 TRECR1 .............................................................................. 203 TRECR2 .............................................................................. 204 TRECSR .............................................................................. 204 TREIC .................................................................................... 95 TREMIN ............................................................................... 203 TRESEC .............................................................................. 203 [U] U0BRG ................................................................................ 210 U0C0 ................................................................................... 211 U0C1 ................................................................................... 212 U0MR .................................................................................. 210 U0RB ................................................................................... 209 U0TB ................................................................................... 209 [V] VCA1 ..................................................................................... 33 VCA2 ............................................................................... 33, 71 VW1C .................................................................................... 34 VW2C .................................................................................... 35 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 331 of 332 R8C/2E Group, R8C/2F Group Index [W] WDC .................................................................................... 116 WDTR ................................................................................. 116 WDTS .................................................................................. 116 Rev.1.00 Dec 14, 2007 REJ09B0349-0100 Page 332 of 332 REVISION HISTORY REVISION HISTORY Rev. 0.01 0.03a Date Nov 17, 2006 May 31, 2007 R8C/2E Group, R8C/2F Group Hardware Manual R8C/2E Group, R8C/2F Group Hardware Manual Description Page − − Summary First Edition issued “RENESAS TECHNICAL UPDATE” reflected: TN-16C-A164A/E, TN-16C-A167A/E Figure 5.3 revised Figure 5.4 NOTE1 revised 5.2 and Figure 5.7 revised Figure 6.4; VCA2 register NOTE5 revised Table 7.18 revised 10 revised Figure 10.1 revised Figure 10.5 FRA1 register revised Figure 10.6 NOTE5 revised Figure 10.7 added 10.4.1.3 revised 10.4.2.5 and Figure 10.10 revised Figure 10.11 revised 10.5.1 revised 12.1.3.1 revised 12.2.1 revised Table 12.6 revised 12.6.4 deleted Figure 12.19 NOTE2 revised Figure 13.3 OFS register NOTE1 revised Figure 14.5; “Following conditions” revised 14.1.6 revised Figure 14.14 TRBMR register revised Figure 14.15 TRBPR register; NOTE2 revised Figure 14.17; “Following conditions” revised Table 14.10 revised Figure 15.4 U0MR to U1MR Register NOTE2 deleted Table 15.5 NOTE2 added Figure 16.6 revised Figure 16.7; “B0CLR“bit name revised Figure 16.9 revised Figure 16.11; “BCDCT” flag name revised. 17.7 revised Table 20.2 revised C-1 25 26 29 33 56 67 68 72 73 74 79 83 85 87 94 106 111 114 115 119 128 139 142 143 146 154 212 222 233 234 236 238 255 267 157 to 160 14.2.5.1 to 14.2.5.4 added REVISION HISTORY R8C/2E Group, R8C/2F Group Hardware Manual Description Rev. 0.03a Date May 31, 2007 Page 271 272 274 275 276 278 280 281 283 284 286 288 303 313 314 316 325 332 333 Figure 20.4 NOTE1 revised Table 20.3 revised 20.4.2.4 revised 20.4.2.15 revised Figure 20.5 revised Figure 20.7 NOTE5 revised Figure 20.9 revised Figure 20.11 revised 20.4.3.4 revised Figure 20.13 revised Figure 20.15 revised Summary Table 20.6; “FRM00 Register” → “FRM0 Register” revised Table 21.11 revised 22.2.4 deleted Figure 22.1 NOTE2 revised 22.3.1 revised 22.6 revised Appendix Figure 2.1 NOTE2 deleted Appendix Figure 3.1 NOTE1 revised Table 1.1 and Table 1.3; “Serial Interface” revised Table 1.2 and Table 1.4; revised specifications of “Operating Frequency/ Supply Voltage” and “Current consumption” Table 1.5 and Figure 1.1; “factory programming product” added Table 1.6 and Figure 1.2; “factory programming product” added Figure 1.3 “UART or clock synchronous serial I/O (8 bits × 1)” revised Figure 1.4 revised Table 1.7 revised Table 1.8 revised Figure 3.1 revised Figure 3.2 revised Table 4.2; - 0053h “S1TIC register” deleted, - 0054h “S1RIC register” deleted Table 4.3; - 00A8h “U1MR register” deleted, - 00A9h “U1BRG register” deleted, - 00AAh to 00ABh “U1TB register” deleted, - 00ACh “U1C0 register” deleted, - 00ADh “U1C1 register” deleted, - 00AEh to 00AFh “U1RB register” deleted Table 4.4; - 00F5h “PINSR1 register” deleted C-2 317 to 320 21.3.2.1 to 21.3.2.4 added 0.10 Aug 01, 2007 2, 4 3, 5 6 7 8 9 10 11 15 16 18 19 20 REVISION HISTORY R8C/2E Group, R8C/2F Group Hardware Manual Description Rev. 0.10 Date Aug 01, 2007 Page 29 43 44 50 52 53 59 60 65 66 77 94 95 103 138 141 203 Figure 5.7 revised Summary Figure 7.1 P1_0 to P1_3 and P1_4 revised Figure 7.2 revised Figure 7.9 PINSR1 register deleted, Figure 7.10 PMR register revised Table 7.4 revised Table 7.9 revised Table 7.30 and Table 7.31 revised, Table 7.32 revised Table 7.33 revised Table 10.1 NOTE2 revised Figure 10.1 revised 10.4.1.3 “low-speed clock mode” → “low-speed on-chip oscillator mode” revised Table 12.2 revised Figure 12.3 Registers S1TIC and S1RIC deleted Figure 12.11 revised 14.2 “The reload register and counter are allocated at the same address.” deleted Figure 14.15 “Programmable one-shot generation mode” mode name revised Figure 14.64 revised 207 to 223 15. Serial Interface; “UART1” deleted (“UARTi (i = 0 or 1)” → “UART0” and “i (i = 0 or 1)” → “0” revised) 207 208 209 210 211 212 213 214 215 216 218 219 220 221 222 223 224 Figure 15.1 revised Figure 15.2 revised Figure 15.3 U1TB register and U1RB register deleted Figure 15.4 U1BRG register and U1MR register deleted, U0MR register NOTE1 revised Figure 15.5 U1C0 register deleted Figure 15.6 U1C1 register deleted, Figure 15.7 PMR register revised Table 15.1 revised Table 15.2 and Table 15.3 revised Figure 15.8 revised Figure 15.9 and Figure 15.10 revised Table 15.4 revised Table 15.5 and Table 15.6 revised Figure 15.11 revised Figure 15.12 revised Figure 15.13 revised 15.3 revised Figure 16.1 revised C-3 REVISION HISTORY R8C/2E Group, R8C/2F Group Hardware Manual Description Rev. 0.10 Date Aug 01, 2007 Page 229 230 233 236 294 296 297 298 299 301 304 305 308 320 327 329 Figure 16.5 revised Summary Figure 16.6 “Zero to one cycle of” revised Figure 16.9 revised Figure 16.12 revised Table 21.2 revised Table 21.5 and Table 21.6 revised Table 21.7 revised Table 21.8 NOTE4 added Table 21.10 and Figure 21.3 revised Table 21.14 revised Table 21.18 and Figure 21.6 “i (i = 0 or 1)” → “0” revised Table 21.20 revised Table 21.24 and Figure 21.10 “i (i = 0 or 1)” → “0” revised 22.4 “i (i = 0 or 1)” → “0” revised 23 (1) deleted Appendix Figure 2.1 NOTE2 added, Appendix Figure 2.2 revised Table 1.1 and Table 1.3 “Interrupts” revised Table 1.5 and Table 1.6 “(D)” deleted Figure 3.1 and Figure 3.2 “Expanded area” deleted Table 4.1 “002Ch” added 5.2 “2.5 V” → “2.6 V” revised Figure 10.1 revised Figure 10.6 “FRA7 Register” added 10.2.2 revised 10.3.8 added Table 10.3 revised Table 12.2 revised Figure 14.1 “TSTART” → “TCSTF” revised Figure 14.36 TRCIOR0: b3 revised, NOTE4 added 14.3.4 and Table 14.16 revised Figure 14.42 revised Figure 14.43 b3 revised, NOTE3 added Figure 14.47 b3 revised Figure 16.9 revised Figure 17.10 revised Table 21.2 IOH(sum) and NOTE2 revised Table 21.11 Symbol “fOCO40M”: Parameter added 1.00 Dec 14, 2007 All pages “Under development” deleted 2, 4 6, 7 15, 16 17 29 66 71 74 75 79 94 122 170 177 178 179 184 233 250 294 300 C-4 R8C/2E Group, R8C/2F Group Hardware Manual Publication Date: Rev.0.01 Rev.1.00 Nov 17, 2006 Dec 14, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. © 2007. Renesas Technology Corp., All rights reserved. Printed in Japan R8C/2E Group, R8C/2F Group Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan