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REJ09B0387-0100 16 R8C/2G Group Hardware Manual RENESAS MCU R8C FAMILY / R8C/2x SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com). Rev.1.00 Revision Date: Apr 04, 2008 w ww.renesas.com Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. 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When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.  The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.  The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.  The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.  When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems.  The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products. How to Use This Manual 1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual. The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral functions, and electrical characteristics; and usage notes. Particular attention should be paid to the precautionary notes when using the manual. These notes occur within the body of the text, at the end of each section, and in the Usage Notes section. The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer to the text of the manual for details. The following documents apply to the R8C/2G Group. Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site. Description Document Title Document No. REJ03B0223 Hardware overview and electrical characteristics R8C/2G Group Datasheet R8C/2G Group This hardware Hardware manual Hardware specifications (pin assignments, Hardware Manual manual memory maps, peripheral function specifications, electrical characteristics, timing charts) and operation description Note: Refer to the application notes for details on using peripheral functions. Software manual Description of CPU instruction set R8C/Tiny Series REJ09B0001 Software Manual Available from Renesas Application note Information on using peripheral functions and Technology Web site. application examples Sample programs Information on writing programs in assembly language and C Renesas Product specifications, updates on documents, technical update etc. Document Type Datasheet 2. Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word “register,” “bit,” or “pin” to distinguish the three categories. Examples the PM03 bit in the PM0 register P3_5 pin, VCC pin Notation of Numbers The indication “b” is appended to numeric values given in binary format. However, nothing is appended to the values of single bits. The indication “h” is appended to numeric values given in hexadecimal format. Nothing is appended to numeric values given in decimal format. Examples Binary: 11b Hexadecimal: EFA0h Decimal: 1234 (2) 3. Register Notation The symbols and terms used in register diagrams are described below. XXX Register b7 b6 b5 b4 b3 b2 b1 b0 *1 Symbol XXX Address XXX After Reset 00h 0 Bit Symbol XXX0 Bit Name XXX bits b1 b0 Function 1 0: XXX 0 1: XXX 1 0: Do not set. 1 1: XXX RW RW RW *2 XXX1 (b2) Nothing is assigned. If necessary, set to 0. When read, the content is undefined. *3 RW (b3) Reserved bits Set to 0. Function varies according to the operating mode. *4 XXX4 XXX bits RW XXX5 WO XXX6 XXX bit 0: XXX 1: XXX RW XXX7 RO *1 Blank: Set to 0 or 1 according to the application. 0: Set to 0. 1: Set to 1. X: Nothing is assigned. *2 RW: Read and write. RO: Read only. WO: Write only. −: Nothing is assigned. *3 • Reserved bit Reserved bit. Set to specified value. *4 • Nothing is assigned Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0. • Do not set to a value Operation is not guaranteed when a value is set. • Function varies according to the operating mode. The function of the bit varies with the peripheral function mode. Refer to the register diagram for information on the individual modes. 4. List of Abbreviations and Acronyms Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SIM UART VCO Full Form Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access Direct Memory Access Controller Global System for Mobile Communications High Impedance Inter Equipment Bus Input / Output Infrared Data Association Least Significant Bit Most Significant Bit Non-Connect Phase Locked Loop Pulse Width Modulation Subscriber Identity Module Universal Asynchronous Receiver / Transmitter Voltage Controlled Oscillator All trademarks and registered trademarks are the property of their respective owners. Table of Contents SFR Page Reference ........................................................................................................................... B - 1 1. Overview ......................................................................................................................................... 1 1.1 1.1.1 1.1.2 1.2 1.3 1.4 1.5 2. Features ..................................................................................................................................................... Applications .......................................................................................................................................... Specifications ........................................................................................................................................ Product List ............................................................................................................................................... Block Diagram .......................................................................................................................................... Pin Assignment .......................................................................................................................................... Pin Functions ............................................................................................................................................. 1 1 1 3 4 5 7 Central Processing Unit (CPU) ....................................................................................................... 8 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.8.1 2.8.2 2.8.3 2.8.4 2.8.5 2.8.6 2.8.7 2.8.8 2.8.9 2.8.10 Data Registers (R0, R1, R2, and R3) ........................................................................................................ 9 Address Registers (A0 and A1) ................................................................................................................. 9 Frame Base Register (FB) ......................................................................................................................... 9 Interrupt Table Register (INTB) ................................................................................................................ 9 Program Counter (PC) ............................................................................................................................... 9 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) .................................................................... 9 Static Base Register (SB) .......................................................................................................................... 9 Flag Register (FLG) .................................................................................................................................. 9 Carry Flag (C) ....................................................................................................................................... 9 Debug Flag (D) ..................................................................................................................................... 9 Zero Flag (Z) ......................................................................................................................................... 9 Sign Flag (S) ......................................................................................................................................... 9 Register Bank Select Flag (B) .............................................................................................................. 9 Overflow Flag (O) ................................................................................................................................ 9 Interrupt Enable Flag (I) ..................................................................................................................... 10 Stack Pointer Select Flag (U) .............................................................................................................. 10 Processor Interrupt Priority Level (IPL) ............................................................................................. 10 Reserved Bit ........................................................................................................................................ 10 3. 4. 5. Memory .......................................................................................................................................... 11 Special Function Registers (SFRs) ............................................................................................... 12 Resets ........................................................................................................................................... 24 5.1 5.1.1 5.1.2 5.2 5.3 5.4 5.5 5.6 5.7 Hardware Reset ....................................................................................................................................... When Power Supply is Stable ............................................................................................................. Power On ............................................................................................................................................ Power-On Reset Function ....................................................................................................................... Voltage Monitor 0 Reset ......................................................................................................................... Voltage Monitor 1 Reset ......................................................................................................................... Voltage Monitor 2 Reset ......................................................................................................................... Watchdog Timer Reset ............................................................................................................................ Software Reset ......................................................................................................................................... 27 27 27 29 30 30 30 31 31 6. Voltage Detection Circuit .............................................................................................................. 32 6.1 VCC Input Voltage .................................................................................................................................. 40 6.1.1 Monitoring Vdet0 ............................................................................................................................... 40 A-1 6.1.2 Monitoring Vdet1 ............................................................................................................................... 6.1.3 Monitoring Vdet2 ............................................................................................................................... 6.2 Voltage Monitor 0 Reset ......................................................................................................................... 6.3 Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset ..................................................................... 6.4 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset ..................................................................... 7. 40 40 41 42 44 Comparator ................................................................................................................................... 46 7.1 7.2 7.3 7.3.1 7.3.2 7.4 7.4.1 7.4.2 7.5 7.5.1 7.5.2 7.6 Overview ................................................................................................................................................. Register Description ................................................................................................................................ Monitoring Comparison Results ............................................................................................................. Monitoring Comparator 1 ................................................................................................................... Monitoring Comparator 2 ................................................................................................................... Functional Description ............................................................................................................................ Comparator 1 ...................................................................................................................................... Comparator 2 ...................................................................................................................................... Comparator 1 and Comparator 2 Interrupts ............................................................................................ Non-Maskable Interrupts .................................................................................................................... Maskable Interrupts ............................................................................................................................ Adjusting Internal Reference Voltage (Vref) .......................................................................................... 46 48 55 55 55 56 56 59 62 62 62 63 8. I/O Ports ........................................................................................................................................ 65 8.1 8.2 8.3 8.4 8.5 8.6 8.6.1 Functions of I/O Ports ............................................................................................................................. Effect on Peripheral Functions ................................................................................................................ Pins Other than Programmable I/O Ports ................................................................................................ Port Setting .............................................................................................................................................. Unassigned Pin Handling ........................................................................................................................ Notes on I/O Ports ................................................................................................................................... Port P4_3, P4_4 .................................................................................................................................. 65 66 66 75 83 84 84 9. 9.1 10. 11. Processor Mode ............................................................................................................................ 85 Processor Modes ...................................................................................................................................... 85 Bus ................................................................................................................................................ 86 Clock Generation Circuit ............................................................................................................... 87 On-Chip Oscillator Clocks ...................................................................................................................... Low-Speed On-Chip Oscillator Clock ................................................................................................ High-Speed On-Chip Oscillator Clock ............................................................................................... XCIN Clock ............................................................................................................................................. CPU Clock and Peripheral Function Clock ............................................................................................. System Clock ...................................................................................................................................... CPU Clock .......................................................................................................................................... Peripheral Function Clock (f1, f2, f4, f8, and f32) ............................................................................. fOCO ................................................................................................................................................... fOCO-F ............................................................................................................................................... fOCO-S ............................................................................................................................................... fC4 and fC32 ....................................................................................................................................... Power Control .......................................................................................................................................... Standard Operating Mode ................................................................................................................... A-2 96 96 96 97 98 98 98 98 98 98 98 98 99 99 11.1 11.1.1 11.1.2 11.2 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 11.3.7 11.4 11.4.1 11.4.2 Wait Mode ........................................................................................................................................ 101 11.4.3 Stop Mode ......................................................................................................................................... 103 11.5 Notes on Clock Generation Circuit ....................................................................................................... 106 11.5.1 Stop Mode ......................................................................................................................................... 106 11.5.2 Wait Mode ........................................................................................................................................ 106 11.5.3 Oscillation Circuit Constants ............................................................................................................ 106 12. 13. Protection .................................................................................................................................... 107 Interrupts ..................................................................................................................................... 108 Interrupt Overview ................................................................................................................................ Types of Interrupts ............................................................................................................................ Software Interrupts ........................................................................................................................... Special Interrupts .............................................................................................................................. Peripheral Function Interrupt ............................................................................................................ Interrupts and Interrupt Vectors ........................................................................................................ Interrupt Control ............................................................................................................................... INT Interrupt ......................................................................................................................................... INTi Interrupt (i = 0, 1, 2, 4) ............................................................................................................. INTi Input Filter (i = 0, 1, 2, 4) ......................................................................................................... Key Input Interrupt ................................................................................................................................ Address Match Interrupt ........................................................................................................................ Notes on Interrupts ................................................................................................................................ Reading Address 00000h .................................................................................................................. SP Setting .......................................................................................................................................... External Interrupt and Key Input Interrupt ....................................................................................... Changing Interrupt Sources .............................................................................................................. Changing Interrupt Control Register Contents ................................................................................. 108 108 109 110 110 111 113 121 121 124 125 127 129 129 129 129 130 131 13.1 13.1.1 13.1.2 13.1.3 13.1.4 13.1.5 13.1.6 13.2 13.2.1 13.2.2 13.3 13.4 13.5 13.5.1 13.5.2 13.5.3 13.5.4 13.5.5 14. ID Code Areas ............................................................................................................................ 132 14.1 Overview ............................................................................................................................................... 132 14.2 Functions ............................................................................................................................................... 132 14.3 Notes on ID Code Areas ........................................................................................................................ 133 14.3.1 Setting Example of ID Code Areas ................................................................................................... 133 15. Option Function Select Area ....................................................................................................... 134 134 135 136 136 15.1 Overview ............................................................................................................................................... 15.2 OFS Register ......................................................................................................................................... 15.3 Notes on Option Function Select Area .................................................................................................. 15.3.1 Setting Example of Option Function Select Area ............................................................................. 16. 16.1 16.2 17. Watchdog Timer .......................................................................................................................... 137 Count Source Protection Mode Disabled .............................................................................................. 141 Count Source Protection Mode Enabled ............................................................................................... 142 Timers ......................................................................................................................................... 143 17.1 Timer RA ............................................................................................................................................... 145 17.1.1 Timer Mode ...................................................................................................................................... 148 17.1.2 Pulse Output Mode ........................................................................................................................... 150 A-3 17.1.3 Event Counter Mode ......................................................................................................................... 17.1.4 Pulse Width Measurement Mode ...................................................................................................... 17.1.5 Pulse Period Measurement Mode ..................................................................................................... 17.1.6 Notes on Timer RA ........................................................................................................................... 17.2 Timer RB ............................................................................................................................................... 17.2.1 Timer Mode ...................................................................................................................................... 17.2.2 Programmable Waveform Generation Mode .................................................................................... 17.2.3 Programmable One-shot Generation Mode ...................................................................................... 17.2.4 Programmable Wait One-Shot Generation Mode ............................................................................. 17.2.5 Notes on Timer RB ........................................................................................................................... 17.3 Timer RE ............................................................................................................................................... 17.3.1 Real-Time Clock Mode .................................................................................................................... 17.3.2 Output Compare Mode ..................................................................................................................... 17.3.3 Notes on Timer RE ........................................................................................................................... 17.4 Timer RF ............................................................................................................................................... 17.4.1 Input Capture Mode .......................................................................................................................... 17.4.2 Output Compare Mode ..................................................................................................................... 17.4.3 Notes on Timer RF ........................................................................................................................... 18. 152 154 157 160 161 165 168 171 175 178 182 183 191 197 200 205 208 212 Serial Interface ............................................................................................................................ 213 218 221 221 222 223 227 228 18.1 Clock Synchronous Serial I/O Mode ..................................................................................................... 18.1.1 Polarity Select Function .................................................................................................................... 18.1.2 LSB First/MSB First Select Function ............................................................................................... 18.1.3 Continuous Receive Mode ................................................................................................................ 18.2 Clock Asynchronous Serial I/O (UART) Mode .................................................................................... 18.2.1 Bit Rate ............................................................................................................................................. 18.3 Notes on Serial Interface ....................................................................................................................... 19. Hardware LIN .............................................................................................................................. 229 Features ................................................................................................................................................. Input/Output Pins .................................................................................................................................. Register Configuration .......................................................................................................................... Functional Description .......................................................................................................................... Master Mode ..................................................................................................................................... Slave Mode ....................................................................................................................................... Bus Collision Detection Function ..................................................................................................... Hardware LIN End Processing ......................................................................................................... Interrupt Requests .................................................................................................................................. Notes on Hardware LIN ........................................................................................................................ 229 230 231 233 233 236 240 241 242 243 19.1 19.2 19.3 19.4 19.4.1 19.4.2 19.4.3 19.4.4 19.5 19.6 20. Flash Memory ............................................................................................................................. 244 Overview ............................................................................................................................................... Memory Map ......................................................................................................................................... Functions to Prevent Rewriting of Flash Memory ................................................................................ ID Code Check Function .................................................................................................................. ROM Code Protect Function ............................................................................................................ CPU Rewrite Mode ............................................................................................................................... Register Description ......................................................................................................................... Status Check Procedure .................................................................................................................... A-4 244 245 246 246 247 248 249 254 20.1 20.2 20.3 20.3.1 20.3.2 20.4 20.4.1 20.4.2 20.4.3 EW0 Mode ........................................................................................................................................ 20.4.4 EW1 Mode ........................................................................................................................................ 20.5 Standard Serial I/O Mode ...................................................................................................................... 20.5.1 ID Code Check Function .................................................................................................................. 20.6 Parallel I/O Mode .................................................................................................................................. 20.6.1 ROM Code Protect Function ............................................................................................................ 20.7 Notes on Flash Memory ........................................................................................................................ 20.7.1 CPU Rewrite Mode ........................................................................................................................... 21. 255 261 266 266 268 268 269 269 Reducing Power Consumption ................................................................................................... 271 271 271 271 271 271 271 271 271 271 272 273 274 21.1 Overview ............................................................................................................................................... 21.2 Key Points and Processing Methods for Reducing Power Consumption ............................................. 21.2.1 Voltage Detection Circuit ................................................................................................................. 21.2.2 Ports .................................................................................................................................................. 21.2.3 Clocks ............................................................................................................................................... 21.2.4 Selecting Oscillation Drive Capacity ................................................................................................ 21.2.5 Wait Mode, Stop Mode ..................................................................................................................... 21.2.6 Stopping Peripheral Function Clocks ............................................................................................... 21.2.7 Timers ............................................................................................................................................... 21.2.8 Reducing Internal Power Consumption ............................................................................................ 21.2.9 Stopping Flash Memory .................................................................................................................... 21.2.10 Low-Current-Consumption Read Mode ........................................................................................... 22. 23. Electrical Characteristics ............................................................................................................ 275 Usage Notes ............................................................................................................................... 292 Notes on I/O Ports ................................................................................................................................. Port P4_3, P4_4 ................................................................................................................................ Notes on Clock Generation Circuit ....................................................................................................... Stop Mode ......................................................................................................................................... Wait Mode ........................................................................................................................................ Oscillation Circuit Constants ............................................................................................................ Notes on Interrupts ................................................................................................................................ Reading Address 00000h .................................................................................................................. SP Setting .......................................................................................................................................... External Interrupt and Key Input Interrupt ....................................................................................... Changing Interrupt Sources .............................................................................................................. Changing Interrupt Control Register Contents ................................................................................. Notes on ID Code Areas ........................................................................................................................ Setting Example of ID Code Areas ................................................................................................... Notes on Option Function Select Area .................................................................................................. Setting Example of Option Function Select Area ............................................................................. Notes on Timers .................................................................................................................................... Notes on Timer RA ........................................................................................................................... Notes on Timer RB ........................................................................................................................... Notes on Timer RE ........................................................................................................................... Notes on Timer RF ........................................................................................................................... Notes on Serial Interface ....................................................................................................................... Notes on Hardware LIN ........................................................................................................................ A-5 292 292 293 293 293 293 294 294 294 294 295 296 297 297 298 298 299 299 300 304 307 308 309 23.1 23.1.1 23.2 23.2.1 23.2.2 23.2.3 23.3 23.3.1 23.3.2 23.3.3 23.3.4 23.3.5 23.4 23.4.1 23.5 23.5.1 23.6 23.6.1 23.6.2 23.6.3 23.6.4 23.7 23.8 23.9 Notes on Flash Memory ........................................................................................................................ 310 23.9.1 CPU Rewrite Mode ........................................................................................................................... 310 23.10 Notes on Noise ...................................................................................................................................... 312 23.10.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and Latch-up ............................................................................................................................................ 312 23.10.2 Countermeasures against Noise Error of Port Control Registers ..................................................... 312 24. Notes for On-Chip Debugger ...................................................................................................... 313 Appendix 1. Package Dimensions ........................................................................................................ 314 Appendix 2. Connection Examples with On-Chip Debugging Emulator ............................................... 315 Appendix 3. Example of Oscillation Evaluation Circuit ......................................................................... 316 Index ..................................................................................................................................................... 317 A-6 SFR Page Reference Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Register Symbol Page Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh Register Comparator 1 Interrupt Control Register Comparator 2 Interrupt Control Register Symbol VCMP1IC VCMP2IC Page 113 113 Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 PM0 PM1 CM0 CM1 85 85 89 90 Protect Register System Clock Select Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0 PRCR OCD WDTR WDTS WDC RMAD0 107 91 139 139 139 128 Timer RE Interrupt Control Register UART2 Transmit Interrupt Control Register UART2 Receive Interrupt Control Register Key Input Interrupt Control Register TREIC S2TIC S2RIC KUPIC 113 113 113 113 Compare 1 Interrupt Control Register CMP1IC UART0 Transmit Interrupt Control Register S0TIC UART0 Receive Interrupt Control Register S0RIC 113 113 113 Address Match Interrupt Enable Register Address Match Interrupt Register 1 AIER RMAD1 128 128 INT2 Interrupt Control Register Timer RA Interrupt Control Register Timer RB Interrupt Control Register INT1 Interrupt Control Register Timer RF Interrupt Control Register Compare 0 Interrupt Control Register INT0 Interrupt Control Register INT4 Interrupt Control Register Capture Interrupt Control Register INT2IC TRAIC TRBIC INT1IC TRFIC CMP0IC INT0IC INT4IC CAPIC 114 113 113 114 113 113 114 114 113 Count Source Protection Mode Register CSPR 140 High-Speed On-Chip Oscillator Control Register 0 HRA0 High-Speed On-Chip Oscillator Control Register 1 HRA1 High-Speed On-Chip Oscillator Control Register 2 HRA2 92 92 92 Clock Prescaler Reset Flag CPSRF High-Speed On-Chip Oscillator Control Register 4 FRA4 High-Speed On-Chip Oscillator Control Register 6 FRA6 93 93 93 BGR Trimming Auxiliary Register A BGR Trimming Auxiliary Register B Voltage Detection Register 1 Voltage Detection Register 2 BGRTRMA BGRTRMB VCA1 VCA2 48 48 35, 49 35, 49, 94 Voltage Monitor 1 Circuit Control Register Voltage Monitor 2 Circuit Control Register Voltage Monitor 0 Circuit Control Register VW1C VW2C VW0C 37, 50 38, 51 36 Voltage Detection Circuit External Input Control Register Comparator Mode Register Voltage Monitor Circuit Edge Select Register BGR Control Register BGR Trimming Register VCAB ALCMR VCAC BGRCR BGRTRM 52 52 39, 53 53 54 NOTE: 1. The blank regions are reserved. Do not access locations in these regions. B-1 Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh Register Symbol Page UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register U0MR U0BRG U0TB U0C0 U0C1 U0RB 215 215 216 216 217 217 Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh Register Symbol Page Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P3 Register Port P3 Direction Register Port P4 Register Port P4 Direction Register Port P6 Register Port P6 Direction Register P0 P1 PD0 PD1 P3 PD3 P4 PD4 P6 PD6 72 72 71 71 72 71 72 71 72 71 Pin Select Register 2 Pin Select Register 3 Port Mode Register External Input Enable Register INT Input Filter Select Register Key Input Enable Register Pull-Up Control Register 0 Pull-Up Control Register 1 PINSR2 PINSR3 PMR INTEN INTF KIEN PUR0 PUR1 73 73 74 121 122 126 74 74 NOTE: 1. The blank regions are reserved. Do not access locations in these regions. B-2 Address Register 0100h Timer RA Control Register 0101h Timer RA I/O Control Register 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh Timer RA Mode Register Timer RA Prescaler Register Timer RA Register LIN Control Register LIN Status Register Timer RB Control Register Timer RB One-Shot Control Register Timer RB I/O Control Register Timer RB Mode Register Timer RB Prescaler Register Timer RB Secondary Register Timer RB Primary Register Symbol TRACR TRAIOC TRAMR TRAPRE TRA LINCR LINST TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBSC TRBPR Page 146 146, 148, 151, 153, 155, 158 147 147 147 231 232 162 162 163, 165, 169, 172, 176 163 164 164 164 Timer RE Second Data Register / Counter Data Register Timer RE Minute Data Register / Compare Data Register Timer RE Hour Data Register Timer RE Day of Week Data Register Timer RE Control Register 1 Timer RE Control Register 2 Timer RE Count Source Select Register Timer RE Real-Time Clock Precision Adjust Register TRESEC TREMIN TREHR TREWK TRECR1 TRECR2 TRECSR TREOPR 185, 193 185, 193 186 186 187, 194 188, 194 189, 195 189 Address 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh Register Symbol Page NOTE: 1. The blank regions are reserved. Do not access locations in these regions. B-3 Address 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh Register UART2 Transmit/Receive Mode Register UART2 Bit Rate Register UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register Symbol U2MR U2BRG U2TB U2C0 U2C1 U2RB Page 215 215 216 216 217 217 Address Register 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h 01B3h Flash Memory Control Register 4 01B4h 01B5h Flash Memory Control Register 1 01B6h 01B7h Flash Memory Control Register 0 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01C0h 01C1h 01C2h 01C3h 01C4h 01C5h 01C6h 01C7h 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh Symbol Page FMR4 FMR1 FMR0 253 252 249 NOTE: 1. The blank regions are reserved. Do not access locations in these regions. B-4 Address 01E0h 01E1h 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh 01F0h 01F1h 01F2h 01F3h 01F4h 01F5h 01F6h 01F7h 01F8h 01F9h 01FAh 01FBh 01FCh 01FDh 01FEh 01FFh 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020Ah 020Bh 020Ch 020Dh 020Eh 020Fh 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021Ah 021Bh 021Ch 021Dh 021Eh 021Fh Register Symbol Page Address 0220h 0221h 0222h 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022Ah 022Bh 022Ch 022Dh 022Eh 022Fh 0230h 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023Ah 023Bh 023Ch 023Dh 023Eh 023Fh 0240h 0241h 0242h 0243h 0244h 0245h 0246h 0247h 0248h 0249h 024Ah 024Bh 024Ch 024Dh 024Eh 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh Register Symbol Page NOTE: 1. The blank regions are reserved. Do not access locations in these regions. B-5 Address 0260h 0261h 0262h 0263h 0264h 0265h 0266h 0267h 0268h 0269h 026Ah 026Bh 026Ch 026Dh 026Eh 026Fh 0270h 0271h 0272h 0273h 0274h 0275h 0276h 0277h 0278h 0279h 027Ah 027Bh 027Ch 027Dh 027Eh 027Fh 0280h 0281h 0282h 0283h 0284h 0285h 0286h 0287h 0288h 0289h 028Ah 028Bh 028Ch 028Dh 028Eh 028Fh 0290h 0291h 0292h 0293h 0294h 0295h 0296h 0297h 0298h 0299h 029Ah 029Bh 029Ch 029Dh 029Eh 029Fh Register Symbol Page Timer RF Register TRF 202 Timer RF Control Register 2 Timer RF Control Register 0 Timer RF Control Register 1 Capture and Compare 0 Register Compare 1 Register TRFCR2 TRFCR0 TRFCR1 TRFM0 TRFM1 203 203 204 202 202 Address 02A0h 02A1h 02A2h 02A3h 02A4h 02A5h 02A6h 02A7h 02A8h 02A9h 02AAh 02ABh 02ACh 02ADh 02AEh 02AFh 02B0h 02B1h 02B2h 02B3h 02B4h 02B5h 02B6h 02B7h 02B8h 02B9h 02BAh 02BBh 02BCh 02BDh 02BEh 02BFh 02C0h 02C1h 02C2h 02C3h 02C4h 02C5h 02C6h 02C7h 02C8h 02C9h 02CAh 02CBh 02CCh 02CDh 02CEh 02CFh 02D0h 02D1h 02D2h 02D3h 02D4h 02D5h 02D6h 02D7h 02D8h 02D9h 02DAh 02DBh 02DCh 02DDh 02DEh 02DFh Register Symbol Page NOTE: 1. The blank regions are reserved. Do not access locations in these regions. B-6 Address 02E0h 02E1h 02E2h 02E3h 02E4h 02E5h 02E6h 02E7h 02E8h 02E9h 02EAh 02EBh 02ECh 02EDh 02EEh 02EFh 02F0h 02F1h 02F2h 02F3h 02F4h 02F5h 02F6h 02F7h 02F8h 02F9h 02FAh 02FBh 02FCh 02FDh 02FEh 02FFh FFFFh Register Symbol Page Pin Select Register 4 External Input Enable Register 2 INT Input Filter Select Register 2 Timer RF Output Control Register Option Function Select Register PINSR4 INTEN2 INTF2 TRFOUT OFS 39, 54, 73 122 123 204 26, 135, 140, 247 NOTE: 1. The blank regions are reserved. Do not access locations in these regions. B-7 R8C/2G Group RENESAS MCU REJ09B0387-0100 Rev.1.00 Apr 04, 2008 1. 1.1 Overview Features The R8C/2G Group of single-chip MCUs incorporates the R8C/Tiny Series CPU core, employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high speed. In addition, the CPU core boasts a multiplier for high-speed operation processing. Power consumption is low, and the supported operating modes allow additional power control. These MCUs also use an anti-noise configuration to reduce emissions of electromagnetic noise and are designed to withstand EMI. Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of system components. 1.1.1 Applications Electric power meters, electronic household appliances, office equipment, audio equipment, consumer equipment, etc. 1.1.2 Specifications Table 1.1 outlines the Specifications for R8C/2G Group. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 1 of 318 R8C/2G Group 1. Overview Table 1.1 Item CPU Specifications for R8C/2G Group Function Central processing unit Specification R8C/Tiny series core • Number of fundamental instructions: 89 • Minimum instruction execution time: 125 ns (System clock = 8 MHz, VCC = 2.7 to 5.5 V) 250 ns (System clock = 4 MHz, VCC = 2.2 to 5.5 V) • Multiplier: 16 bits × 16 bits → 32 bits • Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits • Operation mode: Single-chip mode (address space: 1 Mbyte) Refer to Table 1.2 Product List for R8C/2G Group. • Power-on reset • Voltage detection 3 • • • • • 2 circuits (shared with voltage monitor 1 and voltage monitor 2) External reference voltage input is available Output-only: 1 CMOS I/O ports: 27, selectable pull-up resistor 2 circuits: On-chip oscillator (high-speed, low-speed) (high-speed on-chip oscillator has a frequency adjustment function), XCIN clock oscillation circuit (32 kHz) • Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16 • Low power consumption modes: Standard operating mode (low-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode Real-time clock (timer RE) • External: 5 sources, Internal: 17 sources, Software: 4 sources • Priority levels: 7 levels 15 bits × 1 (with prescaler), reset start selectable 8 bits × 1 (with 8-bit prescaler) Timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode 8 bits × 1 (with 8-bit prescaler) Timer mode (period timer), programmable waveform generation mode (PWM output), programmable one-shot generation mode, programmable wait oneshot generation mode 8 bits × 1 Real-time clock mode (count seconds, minutes, hours, days of week), output compare mode 16 bits × 1 (with capture/compare register pin and compare register pin) Input capture mode, output compare mode Clock synchronous serial I/O/UART × 2 Hardware LIN: 1 (timer RA, UART0) • Programming and erasure voltage: VCC = 2.7 to 5.5 V • Programming and erasure endurance: 100 times • Program security: ROM code protect, ID code check • Debug functions: On-chip debug, on-board flash rewrite function System clock = 8 MHz (VCC = 2.7 to 5.5 V) System clock = 4 MHz (VCC = 2.2 to 5.5 V) 5 mA (VCC = 5 V, system clock = 8 MHz) 23 µA (VCC = 3 V, wait mode (low-speed on-chip oscillator on)) 0.7 µA (VCC = 3 V, stop mode, BGR trimming circuit disabled) -20 to 85°C (N version) -40 to 85°C (D version)(1) 32-pin LQFP Package code: PLQP0032GB-A (previous code: 32P6U-A) Memory ROM, RAM Power Supply Voltage detection Voltage circuit Detection Comparator I/O Ports Clock Clock generation circuits Interrupts Watchdog Timer Timer Timer RA Timer RB Timer RE Timer RF Serial UART0, UART2 Interface LIN Module Flash Memory Operating Frequency/Supply Voltage Current consumption Operating Ambient Temperature Package NOTE: 1. Specify the D version if D version functions are to be used. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 2 of 318 R8C/2G Group 1. Overview 1.2 Product List Table 1.2 lists Product List for R8C/2G Group, Figure 1.1 shows a Part Number, Memory Size, and Package of R8C/2G Group. Table 1.2 Product List for R8C/2G Group ROM Capacity 16 Kbytes 24 Kbytes 32 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes RAM Capacity 512 bytes 1 Kbytes 1 Kbytes 512 bytes 1 Kbytes 1 Kbytes Package Type PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A Current of Apr. 2008 Remarks N version Part No. R5F212G4SNFP R5F212G5SNFP R5F212G6SNFP R5F212G4SDFP R5F212G5SDFP R5F212G6SDFP D version Part No. R 5 F 21 2G 4 S N FP Package type: FP: PLQP0032GB-A Classification N: Operating ambient temperature -20°C to 85°C D: Operating ambient temperature -40°C to 85°C S: Low-voltage version (other no symbols) ROM capacity 4: 16 KB 5: 24 KB 6: 32 KB R8C/2G Group R8C/Tiny Series Memory type F: Flash memory version Renesas MCU Renesas semiconductor Figure 1.1 Part Number, Memory Size, and Package of R8C/2G Group Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 3 of 318 R8C/2G Group 1. Overview 1.3 Block Diagram Figure 1.2 shows a Block Diagram. 4 8 8 2 1 5 I/O ports Port P0 Port P1 Port P3 Port P4 Port P6 Peripheral functions UART or clock synchronous serial I/O (8 bits × 2 channels) System clock generation circuit High-speed on-chip oscillator Low-Speed on-chip oscillator XCIN-XCOUT Timers Timer RA (8 bits) Timer RB (8 bits) Timer RE (8 bits) Timer RF (16 bits) LIN module (1 channel) Voltage detection circuit (3 circuits) Comparator (2 circuits) Watchdog timer (15 bits) R8C/Tiny Series CPU core R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG Memory ROM(1) RAM(2) Multiplier NOTES: 1. ROM size varies with MCU type. 2. RAM size varies with MCU type. Figure 1.2 Block Diagram Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 4 of 318 R8C/2G Group 1. Overview 1.4 Pin Assignment Figure 1.3 shows Pin Assignment (Top View). Table 1.3 outlines the Pin Name Information by Pin Number. P1_3/KI3/VCOUT1/(TRBO)(1) P1_0/KI0/TRFO00/VCMP1 P1_1/KI1/TRFO01/VCMP2 P6_5/CLK2/(TREO) (1) P1_2/KI2/TRFO02/CVREF P3_4/TRFO11 P3_3/TRFO10/TRFI 24 23 22 21 20 19 18 17 P1_4/TXD0 P0_7/(Kl0)(1) P0_6/INT4 P0_5 P0_4/(TREO)(1) P6_3/TXD2 P6_0/TREO P6_6/(Kl1)(1) P6_4/RXD2 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 16 15 R8C/2G Group PLQP0032GB-A (32P6U-A) (top view) 14 13 12 11 10 9 P1_5/RXD0/(TRAIO)/(INT1)(1) P1_6/CLK0/VCOUT2 P3_2/INT2 P3_0/TRAO P3_1/TRBO P3_6/(INT1)(1) P1_7/TRAIO/INT1 P4_5/INT0 P3_5/TRFO12 P3_7/(TRAO)/(TRFO11)(1) RESET XCOUT/(P4_4)(1) VSS XCIN/(P4_3)(1) NOTES: 1. Can be assigned to the pin in parentheses by a program. 2. Confirm the pin 1 position on the package by referring to the package dimensions. Figure 1.3 Pin Assignment (Top View) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 5 of 318 MODE VCC R8C/2G Group 1. Overview Table 1.3 Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name Information by Pin Number Control Pin Port P3_5 P3_7 RESET XCOUT VSS XCIN VCC MODE P4_5 P1_7 P3_6 P3_1 P3_0 P3_2 P1_6 P1_5 P1_4 P1_3 P1_2 P6_5 P1_1 P1_0 P3_3 P3_4 P0_7 P0_6 P0_5 P0_4 P6_3 P6_0 P6_6 P6_4 (Kl1)(1) RXD2 TREO (TREO)(1) TXD2 (Kl0)(1) INT4 KI1 KI0 KI3 KI2 (TRBO)(1) TRFO02 (TREO)(1) TRFO01 TRFO00 TRFO10/TRFI TRFO11 CLK2 VCMP2 VCMP1 (INT1)(1) (TRAIO)(1) INT2 CLK0 RXD0 TXD0 VCOUT1 CVREF VCOUT2 INT0 INT1 (INT1)(1) TRBO TRAO TRAIO (P4_3) (P4_4) I/O Pin Functions for of Peripheral Modules Interrupt Timer TRFO12 (TRAO)/(TRFO11)(1) Serial Interface Comparator NOTE: 1. Can be assigned to the pin in parentheses by a program. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 6 of 318 R8C/2G Group 1. Overview 1.5 Pin Functions Table 1.4 lists Pin Functions. Table 1.4 Type Power supply input Reset input MODE XCIN clock input XCIN clock output INT interrupt input Key input interrupt Timer RA Timer RB Timer RE Timer RF Pin Functions Symbol VCC, VSS RESET MODE XCIN XCOUT INT0 to INT2, INT4 KI0 to KI3 TRAIO TRAO TRBO TREO TRFI TRFO00 to TRFO02, TRFO10 to TRFO12 I/O Type Description Apply 2.2 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin. Input “L” on this pin resets the MCU. Connect this pin to VCC via a resistor. These pins are provided for XCIN clock generation circuit I/O. Connect a crystal oscillator between the XCIN and XCOUT pins.(1) To use an external clock, input it to the XCIN pin and leave the XCOUT pin open. INT interrupt input pins Key input interrupt input pins Timer RA I/O pin Timer RA output pin Timer RB output pin Divided clock output pin Timer RF input pin Timer RF output pins Clock I/O pin Serial data input pin Serial data output pin Analog input pins to comparator Reference voltage input pin to comparator Comparator output pins CMOS I/O ports. Each port has an I/O select direction register, allowing each pin in the port to be directed for input or output individually. Any port set to input can be set to use a pull-up resistor or not by a program. Output-only port – I I I O I I I/O O O O I O I/O I O I I O I/O Serial interface CLK0, CLK2 RXD0, RXD2 TXD0, TXD2 Comparator VCMP1, VCMP2 CVREF VCOUT1, VCOUT2 I/O port P0_4 to P0_7, P1_0 to P1_7, P3_0 to P3_7, P4_3, P4_5, P6_0, P6_3 to P6_6 P4_4 Output port O I: Input O: Output I/O: Input and output NOTE: 1. Refer to the oscillator manufacturer for oscillation characteristics. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 7 of 318 R8C/2G Group 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank. b31 b15 b8b7 b0 R2 R3 R0H (high-order of R0) R0L (low-order of R0) R1H (high-order of R1) R1L (low-order of R1) Data registers(1) R2 R3 A0 A1 FB b19 b15 b0 Address registers(1) Frame base register(1) INTBH INTBL Interrupt table register The 4 high order bits of INTB are INTBH and the 16 low order bits of INTB are INTBL. b19 b0 PC Program counter b15 b0 USP ISP SB b15 b0 User stack pointer Interrupt stack pointer Static base register FLG b15 b8 b7 b0 Flag register IPL U I OBSZDC Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bit Processor interrupt priority level Reserved bit NOTE: 1. These registers comprise a register bank. There are two register banks. Figure 2.1 CPU Registers Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 8 of 318 R8C/2G Group 2. Central Processing Unit (CPU) 2.1 Data Registers (R0, R1, R2, and R3) R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is analogous to R2R0. 2.2 Address Registers (A0 and A1) A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 to be used as a 32-bit address register (A1A0). 2.3 Frame Base Register (FB) FB is a 16-bit register for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is a 20-bit register that indicates the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is 20 bits wide and indicates the address of the next instruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between USP and ISP. 2.7 Static Base Register (SB) SB is a 16-bit register for SB relative addressing. 2.8 Flag Register (FLG) FLG is an 11-bit register indicating the CPU state. 2.8.1 Carry Flag (C) The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 Debug Flag (D) The D flag is for debugging only. Set it to 0. 2.8.3 Zero Flag (Z) The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 Sign Flag (S) The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 Register Bank Select Flag (B) Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1. 2.8.6 Overflow Flag (O) The O flag is set to 1 when an operation results in an overflow; otherwise to 0. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 9 of 318 R8C/2G Group 2. Central Processing Unit (CPU) 2.8.7 Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged. 2.8.8 Stack Pointer Select Flag (U) ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1. The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled. 2.8.10 Reserved Bit If necessary, set to 0. When read, the content is undefined. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 10 of 318 R8C/2G Group 3. Memory 3. Memory Figure 3.1 is a Memory Map of R8C/2G Group. The R8C/2G group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1-Kbyte internal RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users. 00000h SFR (Refer to 4. Special Function Registers (SFRs)) 002FFh 00400h Internal RAM 0XXXh 0FFDCh 0YYYYh Internal ROM (program ROM) 0FFFFh 0FFFFh Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer/voltage monitor/comparator (Reserved) (Reserved) Reset FFFFFh NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Part Number R5F212G4SNFP, R5F212G4SDFP R5F212G5SNFP, R5F212G5SDFP R5F212G6SNFP, R5F212G6SDFP Internal ROM Size 16 Kbytes 24 Kbytes 32 Kbytes Address 0YYYYh 0C000h 0A000h 08000h Size 512 bytes 1 Kbyte 1 Kbyte Internal RAM Address 0XXXXh 005FFh 007FFh 007FFh Figure 3.1 Memory Map of R8C/2G Group Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 11 of 318 R8C/2G Group 4. Special Function Registers (SFRs) 4. Special Function Registers (SFRs) An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.12 list the special function registers. Table 4.1 Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh SFR Information (1)(1) Register Symbol After reset Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 PM0 PM1 CM0 CM1 00h 00h 01011000b 00h Protect Register System Clock Select Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0 PRCR OCD WDTR WDTS WDC RMAD0 00h 00000100b XXh XXh 00X11111b 00h 00h 00h 00h 00h 00h 00h Address Match Interrupt Enable Register Address Match Interrupt Register 1 AIER RMAD1 Count Source Protection Mode Register CSPR 00h 10000000b(2) High-Speed On-Chip Oscillator Control Register 0 High-Speed On-Chip Oscillator Control Register 1 High-Speed On-Chip Oscillator Control Register 2 HRA0 HRA1 HRA2 00h When Shipping 00h Clock Prescaler Reset Flag High-Speed On-Chip Oscillator Control Register 4 High-Speed On-Chip Oscillator Control Register 6 CPSRF FRA4 FRA6 00h When Shipping When Shipping BGR Trimming Auxiliary Register A BGR Trimming Auxiliary Register B BGRTRMA BGRTRMB When Shipping When Shipping X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. The CSPROINI bit in the OFS register is set to 0. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 12 of 318 R8C/2G Group 4. Special Function Registers (SFRs) Table 4.2 Address 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh SFR Information (2)(1) Register Voltage Detection Register 1(2) Voltage Detection Register 2(2) VCA1 VCA2 Symbol After reset 00001000b 00h(3) 00100000b(4) Voltage Monitor 1 Circuit Control Register(5) Voltage Monitor 2 Circuit Control Register(5) Voltage Monitor 0 Circuit Control Register(2) VW1C VW2C VW0C 00001010b 00000010b 1000X010b(3) 1100X011b(4) Voltage Detection Circuit External Input Control Register Comparator Mode Register Voltage Monitor Circuit Edge Select Register BGR Control Register BGR Trimming Register Comparator 1 Interrupt Control Register Comparator 2 Interrupt Control Register VCAB ALCMR VCAC BGRCR BGRTRM VCMP1IC VCMP2IC 00h 00h 00h 00h When Shipping XXXXX000b XXXXX000b Timer RE Interrupt Control Register UART2 Transmit Interrupt Control Register UART2 Receive Interrupt Control Register Key Input Interrupt Control Register TREIC S2TIC S2RIC KUPIC XXXXX000b XXXXX000b XXXXX000b XXXXX000b Compare 1 Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register CMP1IC S0TIC S0RIC XXXXX000b XXXXX000b XXXXX000b INT2 Interrupt Control Register Timer RA Interrupt Control Register Timer RB Interrupt Control Register INT1 Interrupt Control Register Timer RF Interrupt Control Register Compare 0 Interrupt Control Register INT0 Interrupt Control Register INT4 Interrupt Control Register Capture Interrupt Control Register INT2IC TRAIC TRBIC INT1IC TRFIC CMP0IC INT0IC INT4IC CAPIC XX00X000b XXXXX000b XXXXX000b XX00X000b XXXXX000b XXXXX000b XX00X000b XX00X000b XXXXX000b X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register. 3. The LVD0ON bit in the OFS register is set to 1 and hardware reset. 4. Power-on reset, voltage monitor 0 reset, or the LVD0ON bit in the OFS register is set to 0 and hardware reset. 5. Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect b2 and b3. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 13 of 318 R8C/2G Group 4. Special Function Registers (SFRs) Table 4.3 Address 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh SFR Information (3)(1) Register Symbol After reset UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register U0MR U0BRG U0TB U0C0 U0C1 U0RB 00h XXh XXh XXh 00001000b 00000010b XXh XXh X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 14 of 318 R8C/2G Group 4. Special Function Registers (SFRs) Table 4.4 Address 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh SFR Information (4)(1) Register Symbol After reset Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P3 Register Port P3 Direction Register Port P4 Register Port P4 Direction Register Port P6 Register Port P6 Direction Register P0 P1 PD0 PD1 P3 PD3 P4 PD4 P6 PD6 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 15 of 318 R8C/2G Group 4. Special Function Registers (SFRs) Table 4.5 Address 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh SFR Information (5)(1) Register Symbol After reset Pin Select Register 2 Pin Select Register 3 Port Mode Register External Input Enable Register INT Input Filter Select Register Key Input Enable Register Pull-Up Control Register 0 Pull-Up Control Register 1 PINSR2 PINSR3 PMR INTEN INTF KIEN PUR0 PUR1 00h 00h 00h 00h 00h 00h 00h 00h Timer RA Control Register Timer RA I/O Control Register Timer RA Mode Register Timer RA Prescaler Register Timer RA Register LIN Control Register LIN Status Register Timer RB Control Register Timer RB One-Shot Control Register Timer RB I/O Control Register Timer RB Mode Register Timer RB Prescaler Register Timer RB Secondary Register Timer RB Primary Register TRACR TRAIOC TRAMR TRAPRE TRA LINCR LINST TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBSC TRBPR 00h 00h 00h FFh FFh 00h 00h 00h 00h 00h 00h FFh FFh FFh Timer RE Second Data Register / Counter Data Register Timer RE Minute Data Register / Compare Data Register Timer RE Hour Data Register Timer RE Day of Week Data Register Timer RE Control Register 1 Timer RE Control Register 2 Timer RE Count Source Select Register Timer RE Real-Time Clock Precision Adjust Register TRESEC TREMIN TREHR TREWK TRECR1 TRECR2 TRECSR TREOPR XXh XXh X0XXXXXXb X0000XXXb XXX0X0X0b 00XXXXXXb 00001000b 00h X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 16 of 318 R8C/2G Group 4. Special Function Registers (SFRs) Table 4.6 Address 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh SFR Information (6)(1) Register Symbol After reset UART2 Transmit/Receive Mode Register UART2 Bit Rate Register UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register U2MR U2BRG U2TB U2C0 U2C1 U2RB 00h XXh XXh XXh 00001000b 00000010b XXh XXh X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 17 of 318 R8C/2G Group 4. Special Function Registers (SFRs) Table 4.7 Address 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh SFR Information (7)(1) Register Symbol After reset X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 18 of 318 R8C/2G Group 4. Special Function Registers (SFRs) Table 4.8 Address 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh 01C0h 01C1h 01C2h 01C3h 01C4h 01C5h 01C6h 01C7h 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh 01E0h 01E1h 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh SFR Information (8)(1) Register Symbol After reset Flash Memory Control Register 4 Flash Memory Control Register 1 Flash Memory Control Register 0 FMR4 FMR1 FMR0 01000000b 1000000Xb 00000001b X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 19 of 318 R8C/2G Group 4. Special Function Registers (SFRs) Table 4.9 Address 01F0h 01F1h 01F2h 01F3h 01F4h 01F5h 01F6h 01F7h 01F8h 01F9h 01FAh 01FBh 01FCh 01FDh 01FEh 01FFh 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020Ah 020Bh 020Ch 020Dh 020Eh 020Fh 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021Ah 021Bh 021Ch 021Dh 021Eh 021Fh 0220h 0221h 0222h 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022Ah 022Bh 022Ch 022Dh 022Eh 022Fh SFR Information (9)(1) Register Symbol After reset X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 20 of 318 R8C/2G Group 4. Special Function Registers (SFRs) Table 4.10 Address 0230h 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023Ah 023Bh 023Ch 023Dh 023Eh 023Fh 0240h 0241h 0242h 0243h 0244h 0245h 0246h 0247h 0248h 0249h 024Ah 024Bh 024Ch 024Dh 024Eh 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0260h 0261h 0262h 0263h 0264h 0265h 0266h 0267h 0268h 0269h 026Ah 026Bh 026Ch 026Dh 026Eh 026Fh SFR Information (10)(1) Register Symbol After reset X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 21 of 318 R8C/2G Group 4. Special Function Registers (SFRs) Table 4.11 Address 0270h 0271h 0272h 0273h 0274h 0275h 0276h 0277h 0278h 0279h 027Ah 027Bh 027Ch 027Dh 027Eh 027Fh 0280h 0281h 0282h 0283h 0284h 0285h 0286h 0287h 0288h 0289h 028Ah 028Bh 028Ch 028Dh 028Eh 028Fh 0290h 0291h 0292h 0293h 0294h 0295h 0296h 0297h 0298h 0299h 029Ah 029Bh 029Ch 029Dh 029Eh 029Fh 02A0h 02A1h 02A2h 02A3h 02A4h 02A5h 02A6h 02A7h 02A8h 02A9h 02AAh 02ABh 02ACh 02ADh 02AEh 02AFh SFR Information (11)(1) Register Symbol After reset Timer RF Register TRF 00h 00h Timer RF Control Register 2 Timer RF Control Register 0 Timer RF Control Register 1 Capture and Compare 0 Register Compare 1 Register TRFCR2 TRFCR0 TRFCR1 TRFM0 TRFM1 00h 00h 00h 0000h(2) FFFFh(3) FFh FFh X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. After input capture mode. 3. After output compare mode. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 22 of 318 R8C/2G Group 4. Special Function Registers (SFRs) Table 4.12 Address 02B0h 02B1h 02B2h 02B3h 02B4h 02B5h 02B6h 02B7h 02B8h 02B9h 02BAh 02BBh 02BCh 02BDh 02BEh 02BFh 02C0h 02C1h 02C2h 02C3h 02C4h 02C5h 02C6h 02C7h 02C8h 02C9h 02CAh 02CBh 02CCh 02CDh 02CEh 02CFh 02D0h 02D1h 02D2h 02D3h 02D4h 02D5h 02D6h 02D7h 02D8h 02D9h 02DAh 02DBh 02DCh 02DDh 02DEh 02DFh 02E0h 02EFh 02F0h 02F1h 02F2h 02F3h 02F4h 02F5h 02F6h 02F7h 02F8h 02F9h 02FAh 02FBh 02FCh 02FDh 02FEh 02FFh FFFFh SFR Information (12)(1) Register Symbol After reset Pin Select Register 4 External Input Enable Register 2 INT Input Filter Select Register 2 Timer RF Output Control Register Option Function Select Register PINSR4 INTEN2 INTF2 TRFOUT OFS 00h 00h 00h 00h (Note 2) X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. The OFS register cannot be changed by a program. Use a flash programmer to write to it. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 23 of 318 R8C/2G Group 5. Resets 5. Resets The following resets are implemented: hardware reset, power-on reset, voltage monitor 0 reset, voltage monitor 1 reset, voltage monitor 2 reset, watchdog timer reset, and software reset. Table 5.1 lists the Reset Names and Sources. Figure 5.1 lists the Block Diagram of Reset Circuit. Table 5.1 Reset Names and Sources Reset Name Hardware reset Power-on reset Voltage monitor 0 reset Voltage monitor 1 reset Voltage monitor 2 reset Watchdog timer reset Software reset Source Input voltage of RESET pin is held “L” VCC rises VCC falls (monitor voltage: Vdet0) VCC falls (monitor voltage: Vdet1) VCC falls (monitor voltage: Vdet2) Underflow of watchdog timer Write 1 to PM03 bit in PM0 register RESET Hardware reset SFRs Bits VCA25, VW0C0, and VW0C6 SFRs VCC Power-on reset circuit Power-on reset Bits VCA25, VW0C0, and VW0C6 Voltage detection circuit Voltage monitor 0 reset Voltage monitor 1 reset SFRs Bits VCA13, VCA26, VCA27, VW1C2, VW1C3, VW2C2, VW2C3, VW0C1, VW0F0, VW0F1, and VW0C7 Voltage monitor 2 reset Watchdog timer Watchdog timer reset CPU Pin, CPU, and SFR bits other than those listed above(1) Software reset VCA13: Bit in VCA1 register VCA25, VCA26, VCA27: Bits in VCA2 register VW0C0, VW0C1, VW0C6, VW0F0, VW0F1, VW0C7: Bits in VW0C register VW1C2, VW1C3: Bits in VW1C register VW2C2, VW2C3: Bits in VW2C register NOTE: 1. The following registers and bits are not reset. • Registers TRESEC, TREMIN, TREWK, and TRECR2 • Bits PM, H12_H24, and TSTART in the TRECR1 register Figure 5.1 Block Diagram of Reset Circuit Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 24 of 318 R8C/2G Group 5. Resets Table 5.2 shows the Pin Functions while RESET Pin Level is “L”, Figure 5.2 shows the CPU Register Status after Reset, Figure 5.3 shows the Reset Sequence, and Figure 5.4 shows the OFS Register. Table 5.2 Pin Functions while RESET Pin Level is “L” Pin Functions Input port Input port Input port Output port Input port b15 b0 Pin Name P0_4 to P0_7 P1, P3 P4_3, P4_5 P4_4 P6_0, P6_3 to P6_6 0000h 0000h 0000h 0000h 0000h 0000h 0000h b19 b0 Data register(R0) Data register(R1) Data register(R2) Data register(R3) Address register(A0) Address register(A1) Frame base register(FB) 00000h Content of addresses 0FFFEh to 0FFFCh b15 b0 Interrupt table register(INTB) Program counter(PC) 0000h 0000h 0000h b15 b0 User stack pointer(USP) Interrupt stack pointer(ISP) Static base register(SB) 0000h b15 b8 b7 b0 Flag register(FLG) IPL U I OBSZDC Figure 5.2 fOCO-S CPU Register Status after Reset RESET pin 10 cycles or more are needed(1) fOCO-S clock × 32 cycles(2) Internal reset signal Start time of flash memory (CPU clock × 14 cycles) CPU clock 0FFFCh Address (internal address signal) 0FFFDh Content of reset vector NOTES: 1. Hardware reset. 2. When the “L” input width to the RESET pin is set to fOCO-S clock × 32 cycles or more, setting the RESET pin to “H” also sets the internal reset signal to “H” at the same. 0FFFEh CPU clock × 28 cycles Figure 5.3 Reset Sequence Page 25 of 318 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 R8C/2G Group 5. Resets Option Function Select Register(1) b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 Symbol OFS Bit Symbol WDTON — (b1) ROMCR ROMCP1 — (b4) Address 0FFFFh Bit Name Watchdog timer start select bit Reserved bit ROM code protect disabled bit ROM code protect bit Reserved bit Voltage detection 0 circuit start bit(2) When Shipping FFh(3) Function 0 : Starts w atchdog timer automatically after reset 1 : Watchdog timer is inactive after reset Set to 1. 0 : ROM code protect disabled 1 : ROMCP1 enabled 0 : ROM code protect enabled 1 : ROM code protect disabled Set to 1. 0 : Voltage monitor 0 reset enabled after hardw are reset 1 : Voltage monitor 0 reset disabled after hardw are reset Set to 1. 0 : Count source protect mode enabled after reset 1 : Count source protect mode disabled after reset RW RW RW RW RW RW LVD0ON RW — (b6) Reserved bit RW Count source protect CSPROINI mode after reset select bit RW NOTES: 1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not w rite additions to the OFS register. 2. Setting the LVD0ON bit is only valid after a hardw are reset. To use the pow er-on reset, set the LVD0ON bit to 0 (voltage monitor 0 reset enabled after hardw are reset). 3. If the block including the OFS register is erased, FFh is set to the OFS register. Figure 5.4 OFS Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 26 of 318 R8C/2G Group 5. Resets 5.1 Hardware Reset A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the supply voltage meets the recommended operating conditions, pins, CPU, and SFRs are all reset (refer to Table 5.2 Pin Functions while RESET Pin Level is “L”). When the input level applied to the RESET pin changes from “L” to “H”, a program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected as the CPU clock. Refer to 4. Special Function Registers (SFRs) for the state of the SFRs after reset. The internal RAM is not reset. If the RESET pin is pulled “L” while writing to the internal RAM is in progress, the contents of internal RAM will be undefined. Figure 5.5 shows an Example of Hardware Reset Circuit and Operation and Figure 5.6 shows an Example of Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation. 5.1.1 When Power Supply is Stable (1) Apply “L” to the RESET pin. (2) Wait for 10 µs. (3) Apply “H” to the RESET pin. 5.1.2 Power On (1) Apply “L” to the RESET pin. (2) Let the supply voltage increase until it meets the recommended operating conditions. (3) Wait for td(P-R) or more to allow the internal power supply to stabilize (refer to 22. Electrical Characteristics). (4) Wait for 10 µs. (5) Apply “H” to the RESET pin. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 27 of 318 R8C/2G Group 5. Resets VCC VCC 0V RESET RESET 0V 2.2 V 0.2 VCC or below NOTE: td(P-R) + 10µs or more 1. Refer to 22. Electrical Characteristics. Figure 5.5 Example of Hardware Reset Circuit and Operation Supply voltage detection circuit 5V VCC 0V 5V RESET 2.2 V RESET VCC 0V td(P-R) + 10µs or more Example when VCC = 5 V NOTE: 1. Refer to 22. Electrical Characteristics. Figure 5.6 Example of Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 28 of 318 R8C/2G Group 5. Resets 5.2 Power-On Reset Function When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises while the rise gradient is trth or more, the power-on reset function is enabled and the MCU resets its pins, CPU, and SFR. When a capacitor is connected to the RESET pin, too, always keep the voltage to the RESET pin 0.8VCC or more. When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock starts counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H” and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock divided by 8 is automatically selected as the CPU clock after reset. Refer to 4. Special Function Registers (SFRs) for the states of the SFR after power-on reset. The voltage monitor 0 reset is enabled after power-on reset. Figure 5.7 shows an Example of Power-On Reset Circuit and Operation. VCC 4.7 kΩ (reference) RESET Vdet0(3) 2.2 V External Power VCC Vpor1 tw(por1) Sampling time(1, 2) trth trth Vpor2 Vdet0(3) Internal reset signal (“L” valid) 1 × 32 fOCO-S 1 × 32 fOCO-S NOTES: 1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage range (2.2 V or above) during the sampling time. 2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details. 3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection Circuit for details. 4. Refer to 22. Electrical Characteristics. 5. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1. Figure 5.7 Example of Power-On Reset Circuit and Operation Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 29 of 318 R8C/2G Group 5. Resets 5.3 Voltage Monitor 0 Reset A reset is applied using the on-chip voltage detection 0 circuit. The voltage detection 0 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet0. When the input voltage to the VCC pin reaches the Vdet0 level or below, the pins, CPU, and SFR are reset. When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock start counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H” and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock divided by 8 is automatically selected as the CPU clock after reset. The LVD0ON bit in the OFS register can be used to enable or disable voltage monitor 0 reset after a hardware reset. Setting the LVD0ON bit is only valid after a hardware reset. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1. The LVD0ON bit cannot be changed by a program. To set the LVD0ON bit, write 0 (voltage monitor 0 reset enabled after hardware reset) or 1 (voltage monitor 0 reset disabled after hardware reset) to bit 5 of address 0FFFFh using a flash programmer. Refer to Figure 5.4 OFS Register for details of the OFS register. Refer to 4. Special Function Registers (SFRs) for the status of the SFR after voltage monitor 0 reset. The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet0 level or below while writing to the internal RAM is in progress, the contents of internal RAM are undefined. Refer to 6. Voltage Detection Circuit for details of voltage monitor 0 reset. 5.4 Voltage Monitor 1 Reset A reset is applied using the on-chip voltage detection 1 circuit. The voltage detection 1 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet1. When the input voltage to the VCC pin reaches the Vdet1 level or below, the pins, CPU, and SFR are reset and a program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected as the CPU clock. The voltage monitor 1 does not reset some portions of the SFR. Refer to 4. Special Function Registers (SFRs) for details. The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet1 level or below while writing to the internal RAM is in progress, the contents of internal RAM are undefined. Refer to 6. Voltage Detection Circuit for details of voltage monitor 1 reset. 5.5 Voltage Monitor 2 Reset A reset is applied using the on-chip voltage detection 2 circuit. The voltage detection 2 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet2. When the input voltage to the VCC pin reaches the Vdet2 level or below, the pins, CPU, and SFR are reset and the program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected as the CPU clock. The voltage monitor 2 does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details. The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet2 level or below while writing to the internal RAM is in progress, the contents of internal RAM are undefined. Refer to 6. Voltage Detection Circuit for details of voltage monitor 2 reset. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 30 of 318 R8C/2G Group 5. Resets 5.6 Watchdog Timer Reset When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins, CPU, and SFR if the watchdog timer underflows. Then the program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected as the CPU clock. The watchdog timer reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details. The internal RAM is not reset. When the watchdog timer underflows, the contents of internal RAM are undefined. Refer to 16. Watchdog Timer for details of the watchdog timer. 5.7 Software Reset When the PM03 bit in the PM0 register is set to 1 (MCU reset), the MCU resets its pins, CPU, and SFR. The program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected for the CPU clock. The software reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details. The internal RAM is not reset. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 31 of 318 R8C/2G Group 6. Voltage Detection Circuit 6. Voltage Detection Circuit The voltage detection circuit monitors the input voltage to the VCC pin. This circuit can be used to monitor the VCC input voltage by a program. Alternately, voltage monitor 0 reset, voltage monitor 1 interrupt, voltage monitor 1 reset, voltage monitor 2 interrupt, and voltage monitor 2 reset can also be used. Note that voltage monitor 1 and voltage monitor 2 share the voltage detection circuit with comparator 1 and comparator 2. Either voltage monitor 1 and voltage monitor 2 or comparator 1 and comparator 2 can be selected. Table 6.1 lists the Specifications of Voltage Detection Circuit and Figures 6.1 to 6.4 show the Block Diagrams. Figures 6.5 to 6.10 show the Associated Registers. Table 6.1 VCC Monitor Specifications of Voltage Detection Circuit Item Voltage to monitor Detection target Monitor Voltage Detection 1 Vdet1 Passing through Vdet1 by rising or falling VW1C3 bit in VW1C register Whether VCC is higher or lower than Vdet1 Voltage monitor 0 reset Voltage monitor 1 reset Reset at Vdet0 > VCC; Reset at Vdet1 > VCC; restart CPU operation at restart CPU operation VCC > Vdet0 after a specified time None Voltage monitor 1 interrupt Interrupt request at both or either of Vdet1 > VCC and VCC > Vdet1 Available Available (Divide-by-n of fOCO-S) (Divide-by-n of fOCO-S) ×2 ×4 n: 1, 2, 4, and 8 n: 1, 2, 4, and 8 Voltage Detection 0 Vdet0 Whether passing through Vdet0 by falling None Voltage Detection 2 Vdet2 Passing through Vdet2 by rising or falling VCA13 bit in VCA1 register Whether VCC is higher or lower than Vdet2 Voltage monitor 2 reset Reset at Vdet2 > VCC; restart CPU operation after a specified time Voltage monitor 2 interrupt Interrupt request at both or either of Vdet2 > VCC and VCC > Vdet2 Available (Divide-by-n of fOCO-S) ×2 n: 1, 2, 4, and 8 Process Reset When Voltage is Detected Interrupt Digital Filter Switch enabled/disabled Sampling time Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 32 of 318 R8C/2G Group 6. Voltage Detection Circuit VCC Shared with comparator VCA27 VCMP2 VCAB6 = 1 + VCAB6 = 0 Noise filter ≥ Vdet2 Voltage detection 2 signal - VCA1 register b3 VCA13 bit VCA26 VCMP1 VCAB5 = 1 + VCAB5 = 0 Noise filter ≥ Vdet1 Voltage detection 1 signal - VW1C register b3 VW1C3 bit VCA25 + Voltage detection 0 signal Internal reference voltage - ≥ Vdet0 VCA13: Bit in VCA1 register VCA25, VCA26, VCA27: Bits in VCA2 register VW1C3: Bit in VW1C register VCAB5, VCAB6: Bits in VCAB register Figure 6.1 Block Diagram of Voltage Detection Circuit Voltage monitor 0 reset generation circuit VW0F1 to VW0F0 = 00b = 01b Voltage detection 0 circuit fOCO-S VCA25 = 10b 1/2 1/2 1/2 = 11b VW0C1 VCC Internal reference voltage + Voltage detection 0 signal Voltage detection 0 signal is held “H” when VCA25 bit is set to 0 (disabled) Digital filter VW0C1 Voltage monitor 0 reset signal VW0C0 VW0C7 VW0C6 VW0C0 to VW0C1, VW0F0 to VW0F1, VW0C6, VW0C7: Bits in VW0C register VCA25: Bit in VCA2 register Figure 6.2 Block Diagram of Voltage Monitor 0 Reset Generation Circuit Page 33 of 318 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 R8C/2G Group 6. Voltage Detection Circuit Voltage monitor 1 interrupt/reset generation circuit VW1F1 to VW1F0 = 00b = 01b = 10b VW1C2 bit is set to 0 (not detected) by writing 0 by a program. When VCA26 bit is set to 0 (voltage detection 1 circuit disabled), VW1C2 bit is set to 0 Watchdog timer interrupt signal VW1C2 Edge Selection circuit Voltage detection 1 circuit VCA26 VCAB5 = 1 VCMP1 VCC VCAB5 = 0 Internal reference voltage + Noise filter (Filter width: 200 ns) fOCO-S 1/2 1/2 1/2 = 11b VW1C3 VW1C1 = 0 Voltage detection 1 signal Digital filter VW1C1 = 1 Voltage detection 1 signal is held “H” when VCA26 bit is set to 0 (disabled) Voltage monitor 1 interrupt signal Non-maskable interrupt signal Comparator interrupt signal VW1C0 VW1C6 Voltage monitor 1 reset signal VW1C0 to VW1C3, VW1F0, VW1F1, VW1C6, VW1C7: Bits in VW1C register VCA26: Bit in VCA2 register VCAB5: Bit in VCAB register Figure 6.3 Block Diagram of Voltage Monitor 1 Interrupt/Reset Generation Circuit Voltage monitor 2 interrupt/reset generation circuit VW2F1 to VW2F0 = 00b = 01b Voltage detection 2 circuit fOCO-S VCA27 VCAB6 = 1 VCMP2 VCC VCAB6 = 0 Internal reference voltage + Noise filter (Filter width: 200 ns) Voltage detection 2 signal VCA13 VW2C1 = 0 = 10b 1/2 1/2 1/2 = 11b VW2C2 bit is set to 0 (not detected) by writing 0 by a program. When VCA27 bit is set to 0 (voltage detection 2 circuit disabled), VW2C2 bit is set to 0 Watchdog timer interrupt signal VW2C2 Edge Selection circuit Digital filter VW2C1 = 1 Voltage detection 2 signal is held “H” when VCA27 bit is set to 0 (disabled) Voltage monitor 2 interrupt signal Non-maskable interrupt signal Watchdog timer block VW2C3 Watchdog timer underflow signal Comparator interrupt signal This bit is set to 0 (not detected) by writing 0 by a program. VW2C0 VW2C6 Voltage monitor 2 reset signal VW2C0 to VW2C3, VW2F0, VW2F1, VW2C6, VW2C7: Bits in VW2C register VCA13: Bit in VCA1 register VCA27: Bit in VCA2 register VCAB6: Bit in VCAB register Figure 6.4 Block Diagram of Voltage Monitor 2 Interrupt/Reset Generation Circuit Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 34 of 318 R8C/2G Group 6. Voltage Detection Circuit Voltage Detection Register 1 b7 b6 b5 b4 b3 b2 b1 b0 0000 000 Symbol Address 0031h VCA1 Bit Symbol Bit Name Reserved bits — (b2-b0) VCA13 — (b7-b4) Voltage detection 2 signal monitor flag(1) Reserved bits After Reset(2) 00001000b Function Set to 0. 0 : VCC < Vdet2 1 : VCC ≥ V det2 or voltage detection 2 circuit disabled Set to 0. RW RW RO RW NOTES: 1. The VCA13 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled). The VCA13 bit is set to 1 (VCC ≥ V det 2) w hen the VCA27 bit in the VCA2 register is set to 0 (voltage detection 2 circuit disabled). 2. Softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this register. Voltage Detection Register 2(1) b7 b6 b5 b4 b3 b2 b1 b0 0000 Symbol Address VCA2 Bit Symbol VCA20 — (b4-b1) VCA25 VCA26 VCA27 0032h Bit Name Internal pow er low consumption enable bit(6) Reserved bits Voltage detection 0 enable bit(2) Voltage detection 1 enable bit(3) Voltage detection 2 enable bit(4) After Reset(5) The LVD0ON bit in the OFS register is set to 1 and hardw are reset : 00h Pow er-on reset, voltage monitor 0 reset or LVD0ON bit in the OFS register is set to 0, and hardw are reset : 00100000b Function 0 : Low consumption disabled 1 : Low consumption enabled(7) Set to 0. 0 : Voltage detection 0 circuit disabled 1 : Voltage detection 0 circuit enabled 0 : Voltage detection 1 circuit disabled 1 : Voltage detection 1 circuit enabled 0 : Voltage detection 2 circuit disabled 1 : Voltage detection 2 circuit enabled RW RW RW RW RW RW NOTES: 1. Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting to the VCA2 register. 2. To use the voltage monitor 0 reset, set the VCA25 bit to 1. After the VCA25 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting operation. 3. To use the voltage monitor 1 interrupt/reset or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1. After the VCA26 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting operation. 4. To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1. After the VCA27 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting operation. 5. Softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this register. 6. Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in Figure 11.9 Handling Procedure of Internal Pow er Low Consum ption Using VCA20 Bit . 7. When the VCA20 bit is set to 1 (low consumption enabled), do not set the CM10 bit in the CM1 register to 1 (stop mode). Figure 6.5 Registers VCA1 and VCA2 Page 35 of 318 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 R8C/2G Group 6. Voltage Detection Circuit Voltage Monitor 0 Circuit Control Register (1) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol Address After Reset(2) The LVD0ON bit in the OFS register is set to 1 and hardw are reset : 1000X010b Pow er-on reset, voltage monitor 0 reset or LVD0ON bit in the OFS register is set to 0, and hardw are reset : 1100X011b Function 0 : Disable 1 : Enable RW RW VW0C Bit Symbol VW0C0 0038h Bit Name Voltage monitor 0 reset enable bit(3) VW0C1 Voltage monitor 0 digital filter 0 : Digital filter enabled mode (digital filter circuit enabled) disable mode select bit 1 : Digital filter disabled mode (digital filter circuit disabled) Reserved bit Reserved bit Sampling clock select bits Set to 0. When read, the content is undefined. b5 b4 RW VW0C2 — (b3) VW0F0 RW RO RW VW0F1 Voltage monitor 0 circuit mode select bit Voltage monitor 0 reset generation condition select bit(4) 0 0 : fOCO-S divided by 0 1 : fOCO-S divided by 1 0 : fOCO-S divided by 1 1 : fOCO-S divided by 1 2 4 8 RW VW0C6 When the VW0C0 bit is set to 1 (voltage monitor 0 reset enabled), set to 1. When the VW0C1 bit is set to 1 (digital filter disabled mode), set to 1. RW VW0C7 RW NOTES: 1. Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting to the VW0C register. 2. The value remains unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset. 3. The VW0C0 bit is enabled w hen the VCA25 bit in the VCA2 register is set to 1 (voltage detection 0 circuit enabled). Set the VW0C0 bit to 0 (disable), w hen the VCA25 bit is set to 0 (voltage detection 0 circuit disabled). To set VW0C0 bit to 1 (enable), follow the procedure show n in Table 6.2 Procedure for Setting Bits Associated w ith Voltage Monitor 0 Reset. 4. The VW0C7 bit is enabled w hen the VW0C1 bit set to 1 (digital filter disabled mode). Figure 6.6 VW0C Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 36 of 318 R8C/2G Group 6. Voltage Detection Circuit Voltage Monitor 1 Circuit Control Register (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol VW1C Bit Symbol VW1C0 Address 0036h Bit Name Voltage monitor 1 interrupt/reset enable bit(6) Voltage monitor 1 digital filter disable mode select bit(2) After Reset(8) 00001010b Function 0 : Disable 1 : Enable 0 : Digital filter enabled mode (digital filter circuit enabled) 1 : Digital filter disabled mode (digital filter circuit disabled) 0 : Not detected 1 : Vdet1 crossing detected RW RW VW1C1 RW VW1C2 Voltage change detection flag(3, 4, 8) RW VW1C3 Voltage detection 1 signal monitor 0 : VCC < Vdet1 flag(3, 8) 1 : VCC ≥ V det1 or voltage detection 1 circuit disabled Sampling clock select bits b5 b4 RO VW1F0 VW1F1 VW1C6 VW1C7 Voltage monitor 1 circuit mode select bit(5) Voltage monitor 1 interrupt/reset generation condition select bit(7, 9) 0 0 : fOCO-S divided by 0 1 : fOCO-S divided by 1 0 : fOCO-S divided by 1 1 : fOCO-S divided by 1 2 4 8 RW RW RW RW 0 : Voltage monitor 1 interrupt mode 1 : Voltage monitor 1 reset mode 0 : When VCC reaches Vdet1 or above 1 : When VCC reaches Vdet1 or below NOTES: 1. Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting to the VW1C register. When the VW1C register is rew ritten, the VW1C2 bit may be set to 1. Set the VW1C2 bit to 0 after rew riting the VW1C register. 2. To use the voltage monitor 1 interrupt to exit stop mode and to return again, w rite 0 to the VW1C1 bit before w riting 1. 3. Bits VW1C2 and VW1C3 are enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled). 4. Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is w ritten to it). 5. The VW1C6 bit is enabled w hen the VW1C0 bit is set to 1 (voltage monitor 1 interrupt/reset enabled). 6. The VW1C0 bit is enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled). Set the VW1C0 bit to 0 (disable) w hen the VCA26 bit is set to 0 (voltage detection 1 circuit disabled). To set VW1C0 bit to 1 (enable), follow the procedure show n in Table 6.3 Procedure for Setting Bits Associated w ith Voltage Monitor 1 Interrupt and Reset . 7. The VW1C7 bit is enabled w hen the VCAC1 bit in the VCAC register is set to 0 (one edge). Set the VW1C7 bit after setting the VCAC1 bit to 0. 8. Bits VW1C2 and VW1C3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset. 9. When the VW1C6 bit is set to 1 (voltage monitor 1 reset mode), set the VW1C7 bit to 1 (w hen VCC reaches Vdet1 or below ). (Do not set to 0.) Figure 6.7 VW1C Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 37 of 318 R8C/2G Group 6. Voltage Detection Circuit Voltage Monitor 2 Circuit Control Register (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol VW2C Bit Symbol VW2C0 Address 0037h Bit Name Voltage monitor 2 interrupt/reset enable bit(6) Voltage monitor 2 digital filter disable mode select bit(2) After Reset(8) 00000010b Function 0 : Disable 1 : Enable 0 : Digital filter enabled mode (digital filter circuit enabled) 1 : Digital filter disabled mode (digital filter circuit disabled) 0 : Not detected 1 : Vdet2 crossing detected 0 : Not detected 1 : Detected b5 b4 RW RW VW2C1 RW VW2C2 VW2C3 VW2F0 Voltage change detection flag(3, 4, 8) WDT detection flag(4, 8) Sampling clock select bits RW RW VW2F1 VW2C6 VW2C7 Voltage monitor 2 circuit mode select bit(5) Voltage monitor 2 interrupt/reset generation condition select bit(7, 9) 0 0 : fOCO-S divided by 0 1 : fOCO-S divided by 1 0 : fOCO-S divided by 1 1 : fOCO-S divided by 1 2 4 8 RW RW RW RW 0 : Voltage monitor 2 interrupt mode 1 : Voltage monitor 2 reset mode 0 : When VCC reaches Vdet2 or above 1 : When VCC reaches Vdet2 or below NOTES: 1. Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting to the VW2C register. When the VW2C register is rew ritten, the VW2C2 bit may be set to 1. Set the VW2C2 bit to 0 after rew riting the VW2C register. 2. To use the voltage monitor 2 interrupt to exit stop mode and to return again, w rite 0 to the VW2C1 bit before w riting 1. 3. The VW2C2 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled). 4. Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is w ritten to it). 5. The VW2C6 bit is enabled w hen the VW2C0 bit is set to 1 (voltage monitor 2 interrupt/reset enabled). 6. The VW2C0 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled). Set the VW2C0 bit to 0 (disable) w hen the VCA27 bit is set to 0 (voltage detection 2 circuit disabled). To set VW2C0 bit to 1 (enable), follow the procedure show n in Table 6.4 Procedure for Setting Bits Associated w ith Voltage Monitor 2 Interrupt and Reset. 7. The VW2C7 bit is enabled w hen the VCAC2 bit in the VCAC register is set to 0 (one edge). Set the VW2C7 bit after setting the VCAC2 bit to 0. 8. Bits VW2C2 and VW2C3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset. 9. When the VW2C6 bit is set to 1 (voltage monitor 2 reset mode), set the VW2C7 bit to 1 (w hen VCC reaches Vdet2 or below ). (Do not set to 0.) Figure 6.8 VW2C Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 38 of 318 R8C/2G Group 6. Voltage Detection Circuit Voltage Monitor Circuit Edge Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address 003Dh VCAC Bit Symbol Bit Name — Nothing is assigned. If necessary, set to 0. (b0) When read, the content is 0. VCAC1 VCAC2 — (b7-b3) Voltage monitor 1 circuit edge select bit(1) Voltage monitor 2 circuit edge select bit(2) 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges After Reset 00h Function RW — RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. NOTES: 1. The VW1C7 bit in the VW1C register is enabled w hen the VCAC1 bit is set to 0 (one edge). Set the VW1C7 bit after setting the VCAC1 bit to 0. 2. The VW2C7 bit in the VW2C register is enabled w hen the VCAC2 bit is set to 0 (one edge). Set the VW2C7 bit after setting the VCAC2 bit to 0. Figure 6.9 VCAC Register Pin Select Register 4 b7 b6 b5 b4 b3 b2 b1 b0 000 Symbol PINSR4 Bit Symbol TRFOSEL COMPSEL KI0SEL KI1SEL — (b6-b4) TREOSEL2 Address 02FBh Bit Name TRFO11 pin select bit Voltage monitor/comparator select bit KI0 pin select bit After Reset 00h Function 0 : P3_4 1 : P3_7 0 : Voltage monitor 1, voltage monitor 2 1 : Comparator 1, comparator 2 0 : P1_0 1 : P0_7 0 : P1_1 1 : P6_6 Set to 0. 0 : TREOSEL bit in PINSR3 register enabled 1 : P6_5 RW RW RW RW RW RW RW ____ ____ KI1 pin select bit Reserved bits TREO pin select 2 bit Figure 6.10 PINSR4 Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 39 of 318 R8C/2G Group 6. Voltage Detection Circuit 6.1 6.1.1 VCC Input Voltage Monitoring Vdet0 Vdet0 cannot be monitored. 6.1.2 Monitoring Vdet1 Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled). After td(E-A) has elapsed (refer to 22. Electrical Characteristics), Vdet1 can be monitored by the VW1C3 bit in the VW1C register. 6.1.3 Monitoring Vdet2 Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled). After td(E-A) has elapsed (refer to 22. Electrical Characteristics), Vdet2 can be monitored by the VCA13 bit in the VCA1 register. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 40 of 318 R8C/2G Group 6. Voltage Detection Circuit 6.2 Voltage Monitor 0 Reset Table 6.2 lists the Procedure for Setting Bits Associated with Voltage Monitor 0 Reset and Figure 6.11 shows an Example of Voltage Monitor 0 Reset Operation. To use the voltage monitor 0 reset to exit stop mode, set the VW0C1 bit in the VW0C register to 1 (digital filter disabled). Table 6.2 Step 1 2 3 4(1) 5(1) 6 7 8 9 Procedure for Setting Bits Associated with Voltage Monitor 0 Reset When Using Digital Filter When Not Using Digital Filter Set the VCA25 bit in the VCA2 register to 1 (voltage detection 0 circuit enabled) Wait for td(E-A) Select the sampling clock of the digital filter Set the VW0C7 bit in the VW0C register to by the VW0F0 to VW0F1 bits in the VW0C 1 register Set the VW0C1 bit in the VW0C register to Set the VW0C1 bit in the VW0C register to 0 (digital filter enabled) 1 (digital filter disabled) Set the VW0C6 bit in the VW0C register to 1 (voltage monitor 0 reset mode) Set the VW0C2 bit in the VW0C register to 0 Set the CM14 bit in the CM1 register to 0 − (low-speed on-chip oscillator on) Wait for 4 cycles of the sampling clock of − (No wait time required) the digital filter Set the VW0C0 bit in the VW0C register to 1 (voltage monitor 0 reset enabled) NOTE: 1. When the VW0C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1 instruction). VCC Vdet0 Sampling clock of digital filter × 4 cycles When the VW0C1 bit is set to 0 (digital filter enabled) Internal reset signal 1 × 32 fOCO-S 1 × 32 fOCO-S When the VW0C1 bit is set to 1 (digital filter disabled) and the VW0C7 bit is set to 1 Internal reset signal VW0C1 and VW0C7: Bits in VW0C register The above applies under the following conditions. • VCA25 bit in VCA2 register = 1 (voltage detection 0 circuit enabled) • VW0C0 bit in VW0C register = 1 (voltage monitor 0 reset enabled) • VW0C6 bit in VW0C register = 1 (voltage monitor 0 reset mode) When the internal reset signal is held “L”, the pins, CPU and SFR are reset. The internal reset signal level changes from “L” to “H”, and a program is executed beginning with the address indicated by the reset vector. Refer to 4. Special Function Registers (SFRs) for the SFR status after reset. Figure 6.11 Example of Voltage Monitor 0 Reset Operation Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 41 of 318 R8C/2G Group 6. Voltage Detection Circuit 6.3 Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset. Figure 6.12 shows an Example of Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Operation. To use the voltage monitor 1 interrupt or voltage monitor 1 reset to exit stop mode, set the VW1C1 bit in the VW1C register to 1 (digital filter disabled). Table 6.3 Step 1 2 3 4 5(2) Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset When Using Digital Filter When Not Using Digital Filter Voltage Monitor 1 Voltage Monitor 1 Voltage Monitor 1 Voltage Monitor 1 Interrupt Reset Interrupt Reset Set the COMPSEL bit in the PINSR4 register to 0 (voltage monitor 1, voltage monitor 2) Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled) Wait for td(E-A) Select the sampling clock of the digital filter Set the VW1C1 bit in the VW1C register to 1 by the VW1F0 to VW1F1 bits in the VW1C (digital filter disabled) register Set the VW1C1 bit in the VW1C register to 0 − (digital filter enabled) Select the timing of the interrupt and reset Select the timing of the interrupt and reset request by the VCAC1 bit in the VCAC request by the VCAC1 bit in the VCAC register and the VW1C7 bit in the VW1C register and the VW1C7 bit in the VW1C (1) register register(1) Set the VW1C6 bit in Set the VW1C6 bit in Set the VW1C6 bit in Set the VW1C6 bit in the VW1C register to the VW1C register to the VW1C register to the VW1C register to 0 (voltage monitor 1 1 (voltage monitor 1 0 (voltage monitor 1 1 (voltage monitor 1 reset mode) interrupt mode) reset mode) interrupt mode) Set the VW1C2 bit in the VW1C register to 0 (Vdet1 crossing is not detected) Set the CM14 bit in the CM1 register to 0 − (low-speed on-chip oscillator on) Wait for 2 cycles of the sampling clock of the − (No wait time required) digital filter Set the VW1C0 bit in the VW1C register to 1 (voltage monitor 1 interrupt/reset enabled) 6 7 8 9 10 11 NOTES: 1. Set the VW1C7 bit to 1 (when VCC reaches Vdet1 or below) for the voltage monitor 1 reset. 2. When the VW1C0 bit is set to 0, steps 4 and 5 can be executed simultaneously (with 1 instruction). Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 42 of 318 R8C/2G Group 6. Voltage Detection Circuit VCC Vdet1 2.2 V(1) 1 VW1C3 bit 0 2 cycles of sampling clock of digital filter 1 VW1C2 bit 0 When the VW1C1 bit is set to 0 (digital filter enabled) and the VCAC1 bit is set to 1 (both edges) Voltage monitor 1 interrupt request (VW1C6 = 0) Internal reset signal (VW1C6 = 1) Set to 0 by a program Set to 0 by interrupt request acknowledgement 2 cycles of sampling clock of digital filter When the VW1C1 bit is set to 0 (digital filter enabled), and the VCAC1 bit is set to 0 (one edge), and the VW1C7 bit is set to 0 (when VCC reaches Vdet1 or above) 1 VW1C2 bit 0 Voltage monitor 1 interrupt request (VW1C6 = 0) Set to 0 by a program Set to 0 by interrupt request acknowledgement 1 VW1C2 bit When the VW1C1 bit is set to 0 (digital filter enabled), and the VCAC1 bit is set to 0 (one edge), and the VW1C7 bit is set to 1 (when VCC reaches Vdet1 or below) 0 Voltage monitor 1 interrupt request (VW1C6 = 0) Internal reset signal (VW1C6 = 1) Set to 0 by a program Set to 0 by interrupt request acknowledgement Set to 0 by a program 1 VW1C2 bit 0 When the VW1C1 bit is set to 1 (digital filter disabled) and the VCAC1 bit is set to 1 (both edges) Voltage monitor 1 interrupt request (VW1C6 = 0) Internal reset signal (VW1C6 = 1) Set to 0 by a program Set to 0 by interrupt request acknowledgement When the VW1C1 bit is set to 1 (digital filter disabled), and the VCAC1 bit is set to 0 (one edge), and the VW1C7 bit is set to 0 (when VCC reaches Vdet1 or above) 1 VW1C2 bit 0 Voltage monitor 1 interrupt request (VW1C6 = 0) Set to 0 by a program Set to 0 by interrupt request acknowledgement 1 VW1C2 bit When the VW1C1 bit is set to 1 (digital filter disabled), and the VCAC1 bit is set to 0 (one edge), and the VW1C7 bit is set to 1 (when VCC reaches Vdet1 or below) 0 Voltage monitor 1 interrupt request (VW1C6 = 0) Internal reset signal (VW1C6 = 1) Set to 0 by interrupt request acknowledgement VW1C1, VW1C2, VW1C3, VW1C6, VW1C7: Bits in VW1C register VCAC1: Bit in VCAC register The above applies under the following conditions. • VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled) • VW1C0 bit in VW1C register = 1 (voltage monitor 1 interrupt and voltage monitor 1 reset enabled) NOTE: 1. If voltage monitor 0 reset is not used, set the power supply to VCC ≥ 2.2. Figure 6.12 Example of Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Operation Page 43 of 318 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 R8C/2G Group 6. Voltage Detection Circuit 6.4 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Table 6.4 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset. Figure 6.13 shows an Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation. To use the voltage monitor 2 interrupt or voltage monitor 2 reset to exit stop mode, set the VW2C1 bit in the VW2C register to 1 (digital filter disabled). Table 6.4 Step 1 2 3 4 5(2) 6 Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset When Using Digital Filter When Not Using Digital Filter Voltage Monitor 2 Voltage Monitor 2 Voltage Monitor 2 Voltage Monitor 2 Interrupt Reset Interrupt Reset Set the COMPSEL bit in the PINSR4 register to 0 (voltage monitor 1, voltage monitor 2) Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled) Wait for td(E-A) Select the sampling clock of the digital filter Set the VW2C1 bit in the VW2C register to 1 by the VW2F0 to VW2F1 bits in the VW2C (digital filter disabled) register Set the VW2C1 bit in the VW2C register to 0 − (digital filter enabled) Select the timing of the interrupt and reset Select the timing of the interrupt and reset request by the VCAC2 bit in the VCAC request by the VCAC2 bit in the VCAC register and the VW2C7 bit in the VW2C register and the VW2C7 bit in the VW2C (1) register register(1) Set the VW2C6 bit in Set the VW2C6 bit in Set the VW2C6 bit in Set the VW2C6 bit in the VW2C register to the VW2C register to the VW2C register to the VW2C register to 0 (voltage monitor 2 1 (voltage monitor 2 0 (voltage monitor 2 1 (voltage monitor 2 reset mode) interrupt mode) reset mode) interrupt mode) Set the VW2C2 bit in the VW2C register to 0 (Vdet2 crossing is not detected) Set the CM14 bit in the CM1 register to 0 − (low-speed on-chip oscillator on) Wait for 2 cycles of the sampling clock of the − (No wait time required) digital filter Set the VW2C0 bit in the VW2C register to 1 (voltage monitor 2 interrupt/reset enabled) 7 8 9 10 11 NOTES: 1. Set the VW2C7 bit to 1 (when VCC reaches Vdet2 or below) for the voltage monitor 2 reset. 2. When the VW2C0 bit is set to 0, steps 4 and 5 can be executed simultaneously (with 1 instruction). Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 44 of 318 R8C/2G Group 6. Voltage Detection Circuit VCC Vdet2 2.2 V(1) 1 VCA13 bit 0 2 cycles of sampling clock of digital filter 1 VW2C2 bit 0 When the VW2C1 bit is set to 0 (digital filter enabled) and the VCAC2 bit is set to 1 (both edges) Set to 0 by a program Set to 0 by interrupt request acknowledgement 2 cycles of sampling clock of digital filter Voltage monitor 2 interrupt request (VW2C6 = 0) Internal reset signal (VW2C6 = 1) When the VW2C1 bit is set to 0 (digital filter enabled), and the VCAC2 bit is set to 0 (one edge), and the VW2C7 bit is set to 0 (when VCC reaches Vdet2 or above) 1 VW2C2 bit 0 Voltage monitor 2 interrupt request (VW2C6 = 0) Set to 0 by a program Set to 0 by interrupt request acknowledgement 1 VW2C2 bit When the VW2C1 bit is set to 0 (digital filter enabled), and the VCAC2 bit is set to 0 (one edge), and the VW2C7 bit is set to 1 (when VCC reaches Vdet2 or below) 0 Voltage monitor 2 interrupt request (VW2C6 = 0) Internal reset signal (VW2C6 = 1) Set to 0 by a program Set to 0 by interrupt request acknowledgement Set to 0 by a program 1 VW2C2 bit 0 When the VW2C1 bit is set to 1 (digital filter disabled) and the VCAC2 bit is set to 1 (both edges) Voltage monitor 2 interrupt request (VW2C6 = 0) Internal reset signal (VW2C6 = 1) Set to 0 by a program Set to 0 by interrupt request acknowledgement When the VW2C1 bit is set to 1 (digital filter disabled), and the VCAC2 bit is set to 0 (one edge), and the VW2C7 bit is set to 0 (when VCC reaches Vdet2 or above) 1 VW2C2 bit 0 Voltage monitor 2 interrupt request (VW2C6 = 0) Set to 0 by a program Set to 0 by interrupt request acknowledgement 1 VW2C2 bit When the VW2C1 bit is set to 1 (digital filter disabled), and the VCAC2 bit is set to 0 (one edge), and the VW2C7 bit is set to 1 (when VCC reaches Vdet2 or below) 0 Voltage monitor 2 interrupt request (VW2C6 = 0) Internal reset signal (VW2C6 = 1) Set to 0 by interrupt request acknowledgement VCA13: Bit in VCA1 register VW2C1, VW2C2, VW2C6, VW2C7: Bits in VW2C register VCAC2: Bit in VCAC register The above applies under the following conditions. • VCA27 bit in VCA2 register = 1 (voltage detection 2 circuit enabled) • VW2C0 bit in VW2C register = 1 (voltage monitor 2 interrupt and voltage monitor 2 reset enabled) NOTE: 1. When voltage monitor 0 reset is not used, set the power supply to VCC ≥ 2.2. Figure 6.13 Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation Page 45 of 318 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 R8C/2G Group 7. Comparator 7. Comparator The comparators compare a reference input voltage and an analog input voltage. Comparator 1 and comparator 2 are independent of each other. Note that comparator 1 and comparator 2 share the voltage detection circuit with voltage monitor 1 and voltage monitor 2. Either comparator 1 and comparator 2 or voltage monitor 1 and voltage monitor 2 can be selected to use the voltage detection circuit. 7.1 Overview The comparison result of the reference input voltage and analog input voltage can be read by software. The result also can be output from the VCOUTi (i = 1 or 2) pin. An internal reference voltage or input voltage to the CVREF pin can be selected as the reference input voltage. The comparator 1 interrupt and comparator 2 interrupt also can be used. Table 7.1 lists the Specifications of Comparator, Figure 7.1 shows the Block Diagram of Comparator, and Table 7.2 lists the Pin Configuration of Comparator. Table 7.1 Specifications of Comparator Comparator 1 Comparator 2 Input voltage to VCMP1 pin Input voltage to VCMP2 pin Internal reference voltage or input voltage to CVREF pin Whether passing thorough reference input voltage by rising or falling VW1C3 bit in VW1C register VCA13 bit in VCA1 register Whether higher or lower than reference input voltage Comparator 1 interrupt (non-makable or Comparator 2 interrupt (non-makable or maskable selectable) maskable selectable) Interrupt request at both or either of Interrupt request at both or either of reference input voltage > input voltage to reference input voltage > input voltage to VCMP1 pin and input voltage to VCMP1 VCMP2 pin and input voltage to VCMP2 pin > reference input voltage pin > reference input voltage Available Item Analog input voltage Reference input voltage Comparison target Comparison result monitor Interrupt Digital Filter (fOCO-S divided by n) × 2 n: 1, 2, 4, 8 Output from VCOUT2 pin (Whether the Comparison result output Output from VCOUT1 pin (Whether the comparison result output is inverted or not comparison result output is inverted or not can be selected) can be selected) Switch enabled/disabled Sampling time Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 46 of 318 R8C/2G Group 7. Comparator Shared with voltage monitor 1 circuit VCAB5 0 VCA26 VW1F1 to VW1F0 = 00b fOCO-S = 01b fOCO-S/2 = 10b fOCO-S/4 = 11b fOCO-S/8 VW1C1 0 1 Sampling clock LCM1POR Pin output selection circuit CM1OE 0 1 VCMP1 1 + VW1C3 Digital filter VW1C2 selection circuit Edge VCOUT1 non-maskable interrupts maskable interrupts Shared with voltage monitor 2 circuit VCAB6 0 VCA27 = 01b fOCO-S/2 = 10b fOCO-S/4 = 11b fOCO-S/8 VW2C1 0 1 fOCO-S VW2F1 to VW2F0 = 00b Sampling clock VW1C0 IRQ1SEL LCM2POR VCMP2 1 + - CM2OE Digital filter VW2C2 selection circuit Edge 0 1 VCOUT2 1 VCAB7 VCA13 non-maskable interrupts maskable interrupts CVREF 0 VW2C0 IRQ2SEL Internal reference voltage VCA13: Bit in VCA1 register VCA26, VCA27: Bits in VCA2 register VW1C0 to VW1C3, VW1F0 to VW1F1: Bits in VW1C register VW2C0, VW2C2, VW2F0 to VW2F1: Bits in VW2C register VCAB5 to VCAB7: Bits in VCAB register LCM1POR, LCM2POR, CM1OE, CM2OE, IRQ1SEL, IRQ2SEL: Bits in ALCMR register Figure 7.1 Block Diagram of Comparator Table 7.2 Pin Name VCMP1 VCOUT1 VCMP2 VCOUT2 CVREF Pin Configuration of Comparator I/O Input Output Input Output Input Function Comparator 1 analog pin Comparator 1 comparison result output pin Comparator 2 analog pin Comparator 2 comparison result output pin Comparator reference voltage pin Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 47 of 318 R8C/2G Group 7. Comparator 7.2 Register Description Figures 7.2 to 7.11 show the registers associated with the comparator when comparator 1 or comparator 2 is selected. BGR Trimming Auxiliary Register A b7 b6 b5 b4 b3 b2 b1 b0 Symbol BGRTRMA Address 002Eh After Reset When Shipping RW RO Function Stores data for internal reference voltage (Vref) correction w hen VCC = 3.6 to 5.5 V. (The value is the same as that of the BGRTRM register after a reset). Optimal correction to match the voltage conditions can be achieved by transferring this value to the BGRTRM register. BGR Trimming Auxiliary Register B b7 b6 b5 b4 b3 b2 b1 b0 Symbol BGRTRMB Address 002Fh After Reset When Shipping RW RO Function Stores data for internal reference voltage (Vref) correction w hen VCC = 2.2 to 3.6 V. Optimal correction to match the voltage conditions can be achieved by transferring this value to the BGRTRM register. Figure 7.2 Registers BGRTRMA and BGRTRMB Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 48 of 318 R8C/2G Group 7. Comparator Voltage Detection Register 1 b7 b6 b5 b4 b3 b2 b1 b0 0000 000 Symbol Address 0031h VCA1 Bit Symbol Bit Name — Reserved bits (b2-b0) Comparator 2 signal monitor flag(1) VCA13 — (b7-b4) Reserved bits After Reset(2) 00001000b Function Set to 0. 0: VCMP2 < reference voltage 1: VCMP2 ≥ r eference voltage or comparator 2 circuit disabled Set to 0. RW RW RO RW NOTES: 1. The VCA13 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (comparator 2 circuit enabled). The VCA13 bit is set to 1 (VCMP2 ≥ reference voltage) w hen the VCA27 bit in the VCA2 register is set to 0 (comparator 2 circuit disabled). 2. Softw are reset and w atchdog timer reset do not affect this register. Voltage Detection Register 2(1) b7 b6 b5 b4 b3 b2 b1 b0 0000 Symbol Address VCA2 Bit Symbol VCA20 — (b4-b1) VCA25 VCA26 VCA27 0032h Bit Name Internal pow er low consumption enable bit(3) Reserved bits Voltage detection 0 enable bit(4) Comparator 1 enable bit(5) Comparator 2 enable bit(6) After Reset(2) The LVD0ON bit in the OFS register is set to 1 and hardw are reset : 00h Pow er-on reset, voltage monitor 0 reset or the LVD0ON bit in the OFS register is set to 0, and hardw are reset : 00100000b Function 0: Low consumption disabled 1: Low consumption enabled(7) Set to 0. 0: Voltage detection 0 circuit disabled 1: Voltage detection 0 circuit enabled 0: Comparator 1 circuit disabled 1: Comparator 1 circuit enabled 0: Comparator 2 circuit disabled 1: Comparator 2 circuit enabled RW RW RW RW RW RW NOTES: 1. Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting the VCA2 register. 2. Softw are reset and w atchdog timer reset do not affect this register. 3. Use the VCA20 bit only w hen the MCU enters w ait mode. To set the VCA20 bit, follow the procedure show n in Figure 11.9 Handling Procedure of Internal Pow er Low Consum ption Using VCA20 Bit. 4. To use the voltage monitor 0 reset, set the VCA25 bit to 1. After the VCA25 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting operation. 5. To use the comparator 1 interrupt or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1. After the VCA26 bit is set to 1 from 0, the comparator 1 circuit w aits for td(E-A) to elapse before starting operation. 6. To use the comparator 2 interrupt or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1. After the VCA27 bit is set to 1 from 0, the comparator 2 circuit w aits for td(E-A) to elapse before starting operation. 7. When the VCA20 bit is set to 1 (low consumption enabled), do not set the CM10 bit in the CM1 register to 1 (stop mode). Figure 7.3 Registers VCA1 and VCA2 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 49 of 318 R8C/2G Group 7. Comparator Voltage Monitor 1 Circuit Control Register (1) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol VW1C Bit Symbol VW1C0 Address 0036h Bit Name Comparator 1 interrupt enable bit(3) 0: Disable 1: Enable Comparator 1 digital filter disable mode select bit(4) After Reset(2) 00001010b Function RW RW VW1C1 0: Digital filter enable mode (digital filter circuit enabled) 1: Digital filter disable mode (digital filter circuit disabled) [Source for setting this bit to 0] 0: Write 0 [Source for setting this bit to 0] 1: When interrupt request is generated 0: VCMP1 < reference voltage 1: VCMP1 ≥ r eference voltage or comparator 1 circuit disabled b5 b4 RW VW1C2 Comparator 1 interrupt flag(2, 5, 6) RW VW1C3 Comparator 1 signal monitor flag(2, 5) Sampling clock select bits RO VW1F0 VW1F1 VW1C6 Reserved bit 0 0: fOCO-S divided by 0 1: fOCO-S divided by 1 0: fOCO-S divided by 1 1: fOCO-S divided by Set to 0. 1 2 4 8 RW RW RW VW1C7 Comparator 1 interrupt generation 0: When VCMP1 reaches reference condition select bit(7) voltage or above 1: When VCMP1 reaches reference voltage or below RW NOTES: 1. Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting the VW1C register. When the VW1C register is rew ritten, the VW1C2 bit may be set to 1. Set the VW1C2 bit to 0 after rew riting the VW1C register. 2. Bits VW1C2 and VW1C3 remain unchanged after a softw are reset or w atchdog timer reset. 3. The VW1C0 is enabled w hen the VCA26 bit in the VCA2 register is set to 1 (comparator 1 circuit enabled). When the VCA26 bit is set to 0 (comparator 1 circuit disabled), set the VW1C0 bit to 0 (disable). To set the VW1C0 bit to 1 (enable), follow the procedure show n in T able 7.3 Procedure for Setting Bits Associated w ith Com parator 1 Interrupt. 4. To use the comparator 1 interrupt to exit stop mode and to return again, w rite 1 to the VW1C1 bit after w riting 0. 5. Bits VW1C2 and VW1C3 are enabled w hen the VCA26 bit in the VCA2 register is set to 1 (comparator 1 circuit enabled). 6. Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is w ritten to it). 7. The VW1C7 bit is enabled w hen the VCAC1 bit in the VCAC register is set to 0 (one edge). Set the VW1C7 bit after setting the VCAC1 bit to 0. Figure 7.4 VW1C Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 50 of 318 R8C/2G Group 7. Comparator Voltage Monitor 2 Circuit Control Register (1) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol VW2C Bit Symbol VW2C0 Address 0037h Bit Name Comparator 2 interrupt enable bit(3) 0: Disable 1: Enable Comparator 2 digital filter disable mode select bit(4) After Reset(2) 00000010b Function RW RW VW2C1 0: Digital filter enabled mode (digital filter circuit enabled) 1: Digital filter disabled mode (digital filter circuit disabled) [Source for setting this bit to 0] 0: Write 0 [Source for setting this bit to 0] 1: When interrupt request is generated 0: Not detected 1: Detected b5 b4 RW VW2C2 Comparator 2 interrupt flag(2, 5, 6) RW VW2C3 VW2F0 WDT detection flag(2, 6) Sampling clock select bits RW 1 2 4 8 RW VW2F1 VW2C6 Reserved bit 0 0: fOCO-S divided by 0 1: fOCO-S divided by 1 0: fOCO-S divided by 1 1: fOCO-S divided by Set to 0. RW RW VW2C7 Comparator 2 interrupt generation 0: When VCMP2 reaches reference condition select bit(7) voltage or above 1: When VCMP2 reaches reference voltage or below RW NOTES: 1. Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting the VW2C register. When the VW2C register is rew ritten, the VW2C2 bit may be set to 1. Set the VW2C2 bit to 0 after rew riting the VW2C register. 2. Bits VW2C2 and VW2C3 remain unchanged after a softw are reset or w atchdog timer reset. 3. The VW2C0 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (comparator 2 circuit enabled). Set the VW2C0 bit to 0 (disable) w hen the VCA27 bit is set to 0 (comparator 2 circuit disabled). To set the VW2C0 bit to 1 (enable), follow the procedure show n in T able 7.4 Procedure for Setting Bits Associated w ith Com parator 2 Interrupt. 4. To use the comparator 2 interrupt to exit stop mode and to return again, w rite 1 to the VW2C1 bit after w riting 0. 5. The VW2C2 is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (comparator 2 circuit enabled). 6. Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is w ritten to it). 7. The VW2C7 bit is enabled w hen the VCAC2 bit in the VCAC register is set to 0 (one edge). Set the VW2C7 bit after setting the VCAC2 bit to 0. Figure 7.5 VW2C Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 51 of 318 R8C/2G Group 7. Comparator Voltage Detection Circuit External Input Control Register(1) b7 b6 b5 b4 b3 b2 b1 b0 00000 Symbol Address 003Bh VCAB Bit Symbol Bit Name — Reserved bits (b4-b0) VCAB5 VCAB6 VCAB7 After Reset 00h Function Set to 0. RW RW RW RW RW VCMP1 comparison voltage external 0: Supply voltage (VCC) input select bit 1: VCMP1 pin input voltage VCMP2 comparison voltage external 0: Supply voltage (VCC) input select bit 1: VCMP2 pin input voltage Comparator circuit reference voltage 0: Internal reference voltage select bit 1: CVREF pin input voltage NOTE: 1. Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting the VCAB register. Figure 7.6 VCAB Register Comparator Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol ALCMR Bit Symbol LCM1POR Address 003Ch Bit Name VCOUT1 output polarity select bit After Reset 00h Function 0: Non-inverted comparator 1 comparison result is output to VCOUT1 1: Inverted comparator 1 comparison result is output to VCOUT1 0: Non-inverted comparator 2 comparison result is output to VCOUT2 1: Inverted comparator 2 comparison result is output to VCOUT2 0: Output disabled 1: Output enabled 0: Output disabled 1: Output enabled 0: Non-maskable interrupt 1: Maskable interrupt 0: Non-maskable interrupt 1: Maskable interrupt RW RW LCM2POR VCOUT2 output polarity select bit RW CM1OE CM2OE IRQ1SEL IRQ2SEL — (b7-b6) VCOUT1 output enable bit VCOUT2 output enable bit Comparator 1 interrupt type select bit Comparator 2 interrupt type select bit RW RW RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. Figure 7.7 ALCMR Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 52 of 318 R8C/2G Group 7. Comparator Voltage Monitor Circuit Edge Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address 003Dh VCAC Bit Symbol Bit Name — Nothing is assigned. If necessary, set to 0. (b0) When read, the content is 0. VCAC1 VCAC2 — (b7-b3) Comparator 1 circuit edge select bit(1) Comparator 2 circuit edge select bit(2) 0: One edge 1: Both edges 0: One edge 1: Both edges After Reset 00h Function RW — RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. NOTES: 1. The VW1C7 bit in the VW1C register is enabled w hen the VCAC1 bit is set to 0 (one edge). Set the VW1C7 bit after setting the VCAC1 bit to 0. 2. The VW2C7 bit in the VW2C register is enabled w hen the VCAC2 bit is set to 0 (one edge). Set the VW2C7 bit after setting the VCAC2 bit to 0. Figure 7.8 VCAC Register BGR Control Register(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol BGRCR Bit Symbol BGRCR0 — (b7-b1) Address 003Eh Bit Name Internal reference voltage (Vref) adjustment circuit (BGR trimming circuit) enable bit(2) After Reset 00h Function 0: Enabled 1: Disabled RW RW Nothing is assigned. If necessary, set to 0. When read, the content is 0. RW NOTES: 1. Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting the BGRCR register. 2. When the BGRCR0 bit is set to 1 (disabled), the accuracy/precision of the follow ing is not guaranteed: • Internal reference voltage for comparator 1 and comparator 2 • Detection voltage for voltage detection circuit 0 to voltage detection circuit 2 • Oscillation frequency of the high-speed on-chip oscillator Use these functions w hile the BGRCR0 bit is set to 0 (enabled). To set the BGRCR0 bit to 1 (disabled), first disable voltage detection circuits 0 to 2 and disable comparators 1 and 2 w ith the internal reference voltage selected. Also stop the high-speed on-chip oscillator. Then set the BGRCR0 bit to 1 (disabled). Figure 7.9 BGRCR Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 53 of 318 R8C/2G Group 7. Comparator BGR Trimming Register(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol BGRTRM Address 003Fh After Reset When Shipping RW Function Bits 0 to 7 can be used to adjust the level of the internal reference voltage (Vref). Write either of the follow ing values into the BGRTRM register. • Value stored in the BGRTRMA register • Value stored in the BGRTRMB register • 15h Do not w rite values other than the above into the BGRTRM register. Follow the procedure show n in Figure 7.16 for w riting data to the BGRTRM register. NOTE: 1. Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting the BGRTRM register. RW Figure 7.10 BGRTRM Register Pin Select Register 4 b7 b6 b5 b4 b3 b2 b1 b0 000 Symbol PINSR4 Bit Symbol TRFOSEL COMPSEL KI0SEL KI1SEL — (b6-b4) TREOSEL2 Address 02FBh Bit Name TRFO11 pin select bit Voltage monitor/comparator select bit After Reset 00h Function 0 : P3_4 1 : P3_7 0 : Voltage monitor 1, voltage monitor 2 1 : Comparator 1, comparator 2 0 : P1_0 1 : P0_7 0 : P1_1 1 : P6_6 Set to 0. 0 : TREOSEL bit in PINSR3 register enabled 1 : P6_5 RW RW RW RW RW RW RW KI0 pin select bit ____ ____ KI1 pin select bit Reserved bits TREO pin select 2 bit Figure 7.11 PINSR4 Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 54 of 318 R8C/2G Group 7. Comparator 7.3 7.3.1 Monitoring Comparison Results Monitoring Comparator 1 After the following settings are made, the comparison result of comparator 1 can be monitored by the VW1C3 bit in the VW1C register after td(E-A) has elapsed (refer to 22. Electrical Characteristics). (1) Set the COMPSEL bit in the PINSR4 register is set to 1 (comparator 1, comparator 2). (2) Set the VCAB5 bit in the VCAB register to 1 (VCMP1 pin input voltage). (3) Set the VCA26 bit in the VCA2 register to 1 (comparator 1 circuit enabled). 7.3.2 Monitoring Comparator 2 After the following settings are made, the comparison result of comparator 2 can be monitored by the VCA13 bit in the VCA1 register after td(E-A) has elapsed (refer to 22. Electrical Characteristics). (1) Set the COMPSEL bit in the PINSR4 register to 1 (comparator 1, comparator 2). (2) Set the VCAB6 bit in the VCAB register to 1 (VCMP2 pin input voltage). (3) Set the VCA27 bit in the VCA2 register to 1 (comparator 2 circuit enabled). Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 55 of 318 R8C/2G Group 7. Comparator 7.4 Functional Description Comparator 1 and comparator 2 operate independently. The comparison result of the reference input voltage and analog input voltage can be read by software. The result can also be output from the VCOUTi (i = 1 or 2) pin. An internal reference voltage or input voltage to the CVREF pin can be selected as the reference input voltage. The comparator 1 interrupt or the comparator 2 interrupt also can be used by selecting non-maskable or maskable for each interrupt. 7.4.1 Comparator 1 Table 7.3 lists the Procedure for Setting Bits Associated with Comparator 1 Interrupt, Figure 7.12 shows an Operating Example of Comparator 1 (When Digital Filter Enabled), and Figure 7.13 shows an Operating Example of Comparator 1 (When Digital Filter Disabled). Table 7.3 Step 1 2 3 4 5 6 7(1) 8 9 10 11 12 Procedure for Setting Bits Associated with Comparator 1 Interrupt When Using Digital Filter When Not Using Digital Filter Set the COMPSEL bit in the PINSR4 register to 1 (comparator 1, comparator 2) Set the VCAB5 bit in the VCAB register to 1 (VCMP1 pin input voltage) Set the VCA26 bit in the VCA2 register to 1 (comparator 1 circuit enabled) Wait for td(E-A) Select the interrupt type by the IRQ1SEL bit in the ALCMR register Select the sampling clock by bits VW1F0 Set the VW1C1 bit in the VW1C register to 1 (digital and VW1F1 in the VW1C register filter disabled) Set the VW1C1 bit in the VW1C register − to 0 (digital filter enabled) Select the interrupt request timing by the VCAC1 bit in the VCAC register and the VW1C7 bit in the VW1C register Set the VW1C2 bit in the VW1C register to 0 Set the CM14 bit in the CM1 register to 0 − (low-speed on-chip oscillator on) Wait for 2 cycles of the sampling clock of − (No wait time required) the digital filter. Set the VW1C0 bit in the VW1C register to 1 (comparator 1 interrupt enabled) NOTE: 1. When the VW1C0 bit is set to 0, steps 6 and 7 can be executed at the same time (with one instruction) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 56 of 318 R8C/2G Group 7. Comparator VCMP1 Reference voltage 1 VW1C3 bit 0 2 cycles of sampling clock of digital filter 1 VW1C2 bit 0 Set to 0 by a program When the VW1C1 bit is set to 0 (digital filter enabled) and the VCAC1 bit is set to 1 (both edges) Set to 0 by interrupt request acknowledgement, or by a program 2 cycles of sampling clock of digital filter IR bit in VCMP1IC register (IRQ1SEL = 1) 1 0 VCOUT1 output (LCM1POR = 0) 1 0 Set to 0 by a program 1 VW1C2 bit 0 When the VW1C1 bit is set to 0 (digital filter enabled), the VCAC1 bit is set to 0 (one edge), and the VW1C7 bit is set to 0 (VCMP1 reaches reference voltage or above) IR bit in VCMP1IC register (IRQ1SEL = 1) 1 0 1 0 Set to 0 by interrupt request acknowledgement, or by a program VCOUT1 output (LCM1POR = 0) 1 VW1C2 bit When the VW1C1 bit is set to 0 (digital filter enabled), the VCAC1 bit is set to 0 (one edge), and the VW1C7 bit is set to 1 (VCMP1 reaches reference voltage or below) 0 IR bit in VCMP1IC register (IRQ1SEL = 1) 1 0 1 0 Set to 0 by a program Set to 0 by interrupt request acknowledgement, or by a program VCOUT1 output (LCM1POR = 1) VW1C1, VW1C2, VW1C3, VW1C7: Bits in VW1C register VCAC1: Bit in VCAC register LCM1POR, IRQ1SEL: Bits in ALCMR register The above applies under the following conditions. • VCA26 bit in VCA2 register = 1 (comparator 1 circuit enabled) • VW1C0 bit in VW1C register = 1 (comparator 1 interrupt enabled) • CM1OE bit in ALCMR register = 1 (output enabled) • VCAB5 bit in VCAB register = 1 (VCMP1 pin input) • COMPSEL bit in PINSR4 register = 1 (comparator 1, comparator 2 selected) Figure 7.12 Operating Example of Comparator 1 (When Digital Filter Enabled) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 57 of 318 R8C/2G Group 7. Comparator VCMP1 Reference voltage 1 VW1C3 bit 0 Set to 0 by a program 1 VW1C2 bit 0 When the VW1C1 bit is set to 1 (digital filter disabled) and the VCAC1 bit is set to 1 (both edges) IR bit in VCMP1IC register (IRQ1SEL = 1) 1 0 1 0 Set to 0 by a program 1 VW1C2 bit 0 When the VW1C1 bit is set to 1 (digital filter disabled), the VCAC1 bit is set to 0 (one edge), and the VW1C7 bit is set to 0 (VCMP1 reaches reference voltage or above) IR bit in VCMP1IC register (IRQ1SEL = 1) 1 0 1 0 Set to 0 by interrupt request acknowledgement, or by a program Set to 0 by interrupt request acknowledgement, or by a program VCOUT1 output (LCM1POR = 0) VCOUT1 output (LCM1POR = 0) 1 VW1C2 bit When the VW1C1 bit is set to 1 (digital filter disabled), the VCAC1 bit is set to 0 (one edge), and the VW1C7 bit is set to 1 (VCMP1 reaches reference voltage or below) 0 IR bit in VCMP1IC register (IRQ1SEL = 1) VCOUT1 output (LCM1POR = 1) 1 0 1 0 Set to 0 by a program Set to 0 by interrupt request acknowledgement, or by a program VW1C1, VW1C2, VW1C3, VW1C7: Bits in VW1C register VCAC1: Bit in VCAC register LCM1POR, IRQ1SEL: Bits in ALCMR register The above applies under the following conditions. • VCA26 bit in VCA2 register = 1 (comparator 1 circuit enabled) • VW1C0 bit in VW1C register = 1 (comparator 1 interrupt enabled) • CM1OE bit in ALCMR register = 1 (output enabled) • VCAB5 bit in VCAB register = 1 (VCMP1 pin input) • COMPSEL bit in PINSR4 register = 1 (comparator 1, comparator 2 selected) Figure 7.13 Operating Example of Comparator 1 (When Digital Filter Disabled) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 58 of 318 R8C/2G Group 7. Comparator 7.4.2 Comparator 2 Table 7.4 lists the Procedure for Setting Bits Associated with Comparator 2 Interrupt, Figure 7.14 shows an Operating Example of Comparator 2 (When Digital Filter Enabled), and Figure 7.15 shows an Operating Example of Comparator 2 (When Digital Filter Disabled). Table 7.4 Step 1 2 3 4 5 6 7(1) 8 9 10 11 12 Procedure for Setting Bits Associated with Comparator 2 Interrupt When Using Digital Filter When Not Using Digital Filter Set the COMPSEL bit in the PINSR4 register to 1 (comparator 1, comparator 2) Set the VCAB6 bit in the VCAB register to 1 (VCMP2 pin input voltage) Set the VCA27 bit in the VCA2 register to 1 (comparator 2 circuit enabled) Wait for td(E-A) Select the interrupt type by the IRQ2SEL bit in the ALCMR register Select the sampling clock by bits VW2F0 Set the VW2C1 bit in the VW2C register to 1 (digital and VW2F1 in the VW2C register filter disabled) Set the VW2C1 bit in the VW2C register − to 0 (digital filter enabled) Select the interrupt request timing by the VCAC2 bit in the VCAC register and the VW2C7 bit in the VW2C register Set the VW2C2 bit in the VW2C register to 0 Set the CM14 bit in the CM1 register to 0 − (low-speed on-chip oscillator on) Wait for 2 cycles of the sampling clock of − (No wait time required) the digital filter. Set the VW2C0 bit in the VW2C register to 1 (comparator 2 interrupt enabled) NOTE: 1. When the VW2C0 bit is set to 0, steps 6 and 7 can be executed at the same time (with one instruction). Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 59 of 318 R8C/2G Group 7. Comparator VCMP2 Reference voltage 1 VCA13 bit 0 2 cycles of sampling clock of digital filter 1 VW2C2 bit 0 Set to 0 by a program When the VW2C1 bit is set to 0 (digital filter enabled) and the VCAC2 bit is set to 1 (both edges) Set to 0 by interrupt request acknowledgement, or by a program 2 cycles of sampling clock of digital filter IR bit in VCMP2IC register (IRQ2SEL = 1) 1 0 VCOUT2 output (LCM2POR = 0) 1 0 Set to 0 by a program 1 VW2C2 bit 0 When the VW2C1 bit is set to 0 (digital filter enabled), the VCAC2 bit is set to 0 (one edge), and the VW2C7 bit is set to 0 (VCMP2 reaches reference voltage or above) IR bit in VCMP2IC register (IRQ2SEL = 1) 1 0 1 0 Set to 0 by interrupt request acknowledgement, or by a program VCOUT2 output (LCM2POR = 0) 1 VW2C2 bit When the VW2C1 bit is set to 0 (digital filter enabled), the VCAC2 bit is set to 0 (one edge), and the VW2C7 bit is set to 1 (VCMP2 reaches reference voltage or below) 0 IR bit in VCMP2IC register (IRQ2SEL = 1) 1 0 1 0 Set to 0 by a program Set to 0 by interrupt request acknowledgement, or by a program VCOUT2 output (LCM2POR = 1) VCA13: Bit in VCA1 register VW2C1, VW2C2, VW2C7: Bits in VW2C register VCAC2: Bit in VCAC register LCM2POR, IRQ2SEL: Bits in ALCMR register The above applies under the following conditions. • VCA27 bit in VCA2 register = 1 (comparator 2 circuit enabled) • VW2C0 bit in VW2C register = 1 (comparator 2 interrupt enabled) • CM2OE bit in ALCMR register = 1 (output enabled) • VCAB6 bit in VCAB register = 1 (VCMP2 pin input) • COMPSEL bit in PINSR4 register = 1 (comparator 1, comparator 2 selected) Figure 7.14 Operating Example of Comparator 2 (When Digital Filter Enabled) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 60 of 318 R8C/2G Group 7. Comparator VCMP2 Reference voltage 1 VCA13 bit 0 Set to 0 by a program 1 VW2C2 bit 0 When the VW2C1 bit is set to 1 (digital filter disabled) and the VCAC2 bit is set to 1 (both edges) IR bit in VCMP2IC register (IRQ2SEL = 1) 1 0 1 0 Set to 0 by a program 1 VW2C2 bit 0 When the VW2C1 bit is set to 1 (digital filter disabled), the VCAC2 bit is set to 0 (one edge), and the VW2C7 bit is set to 0 (VCMP2 reaches reference voltage or above) IR bit in VCMP2IC register (IRQ2SEL = 1) 1 0 1 0 Set to 0 by interrupt request acknowledgement, or by a program Set to 0 by interrupt request acknowledgement, or by a program VCOUT2 output (LCM2POR = 0) VCOUT2 output (LCM2POR = 0) 1 VW2C2 bit When the VW2C1 bit is set to 1 (digital filter disabled), the VCAC2 bit is set to 0 (one edge), and the VW2C7 bit is set to 1 (VCMP2 reaches reference voltage or below) 0 IR bit in VCMP2IC register (IRQ2SEL = 1) VCOUT2 output (LCM2POR = 1) 1 0 1 0 Set to 0 by a program Set to 0 by interrupt request acknowledgement, or by a program VCA13: Bit in VCA1 register VW2C1, VW2C2, VW2C7: Bits in VW2C register VCAC2: Bit in VCAC register LCM2POR, IRQ2SEL: Bits in ALCMR register The above applies under the following conditions. • VCA27 bit in VCA2 register = 1 (comparator 2 circuit enabled) • VW2C0 bit in VW2C register = 1 (comparator 2 interrupt enabled) • CM2OE bit in ALCMR register = 1 (output enabled) • VCAB6 bit in VCAB register = 1 (VCMP2 pin input) • COMPSEL bit in PINSR4 register = 1 (comparator 1, comparator 2 selected) Figure 7.15 Operating Example of Comparator 2 (When Digital Filter Disabled) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 61 of 318 R8C/2G Group 7. Comparator 7.5 Comparator 1 and Comparator 2 Interrupts Two interrupt requests are generated, one each for comparator 1 and comparator 2. Non-maskable or maskable can be selected for each interrupt type. Refer to 13. Interrupts for interrupts. 7.5.1 Non-Maskable Interrupts When IRQiSEL (i = 1 or 2) bit in the ALCMR register is set to 0, the comparator i interrupt functions as a nonmaskable interrupt. When the selected interrupt request timing occurs, the VWiC2 bit in the VWiC register is set to 1. At this time, a non-maskable interrupt request for comparator i is generated. 7.5.2 Maskable Interrupts When the IRQiSEL (i = 1 or 2) bit in the ALCMR register is set to 1, the comparator i interrupt functions as a maskable interrupt. The comparator i interrupt uses the single VCMPiIC register (bits IR and ILVL0 to ILVL2) and a single vector. When the selected interrupt request timing occurs, the VWiC2 bit in the VWiC register is set to 1. At this time, the IR bit in the VCMPiIC register is set to 1 (interrupt requested). Refer to 13.1.6 Interrupt Control for the VCMPiIC register and 13.1.5.2 Relocatable Vector Tables for interrupt vectors. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 62 of 318 R8C/2G Group 7. Comparator 7.6 Adjusting Internal Reference Voltage (Vref) The level of the internal reference voltage (Vref) can be adjusted with the value of the BGRTRM register. The values for correcting the Vref are stored in registers BGRTRMA and BGRTRMB before shipping the MCU. The value of the BGRTRMA register is the same as that of the BGRTRM register after reset. To use separate correction values to match the supply voltage ranges, transfer them from registers BGRTRMA and BGRTRMB to the BGRTRM register. Figure 7.16 shows the Procedure for Adjusting Internal Reference Voltage (Vref). When the BGRCR0 bit in the BGRCR register to 1 (disabled), the internal reference voltage (Vref) adjustment circuit (BGR trimming circuit) is disabled and the value of the BGRTRM register is also disabled. When the BGR trimming circuit is disabled, the accuracy of the internal reference voltage (Vref) is not guaranteed. Disable voltage detection circuits 0 to 2 and disable comparators 1 and 2 with the internal reference voltage selected. The high-speed on-chip oscillator should also be stopped as necessary because the precision of its oscillation frequency is not also guaranteed. Start adjusting the internal reference voltage (Vref) Determine the supply voltage(1) Vcc ≥ 3.6 V ? Yes Transfer the value of the BGRTRMA register to the BGRTRM register No Transfer the value of the BGRTRMB register to the BGRTRM register Wait for 10µs Adjustment of the internal reference voltage (Vref) completed NOTE: 1. The supple voltage can be determined by reading the monitor flag (VCA13 bit in VCA1 register) for voltage detection 2. Figure 7.17 shows an Example of Adjusting Internal Reference Voltage (Vref) (Voltage Detection 2 Used for Determining Supply Voltage). Figure 7.16 Procedure for Adjusting Internal Reference Voltage (Vref) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 63 of 318 R8C/2G Group 7. Comparator Start adjusting the internal reference voltage (Vref) Transfer the value of the BGRTRMA register to the BGRTRM register Wait for 10µs Enable the voltage detection 2 circuit (Set the VCA27 bit to 1 and the VW2C0 bit to 0) Wait for td(E-A) or 100µs VCA13 bit = 0 ? Yes Transfer the value of the BGRTRMB register to the BGRTRM register No Wait for 10µs VCA13: Bit in VCA1 register VCA27: Bit in VCA2 register VW2C0: Bit in VW2C register Adjustment of the internal reference voltage (Vref) completed Figure 7.17 Example of Adjusting Internal Reference Voltage (Vref) (Voltage Detection 2 Used for Determining Supply Voltage) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 64 of 318 R8C/2G Group 8. I/O Ports 8. I/O Ports There are 27 I/O ports P0_4 to P0_7, P1, P3, P4_3, P4_5, P6_0, P6_3 to P6_6. When the XCIN clock oscillation circuit is not used, P4_3 can be used as an I/O port and P4_4 can be used as an output port. Table 8.1 lists an Overview of I/O Ports. Table 8.1 Overview of I/O Ports I/O I/O I/O I/O I/O I/O Type of Output CMOS3 State CMOS3 State CMOS3 State CMOS3 State CMOS3 State I/O Setting Set per bit Set per bit Set per bit(3) Set per bit Set per bit Set per bit Internal Pull-Up Resister Set every 4 bits(1) Set every bit(2) None Set every bit(2) Set every 2 bits(2) Set every 3 bits(2) Ports P0_4 to P0_7, P1, P3 P4_3 P4_4 P4_5 P6_0, P6_3 P6_4 to P6_6 Output CMOS3 State NOTES: 1. In input mode, whether an internal pull-up resistor is connected or not can be selected by PUR0 register. 2. In input mode, whether an internal pull-up resistor is connected or not can be selected by PUR1 register. 3. Do not use port P4_4 as an input port (input mode). 8.1 Functions of I/O Ports The PDi_j (j = 0 to 7) bit in the PDi (i = 0, 1, 3, 4, 6) register controls I/O of the ports P0_4 to P0_7, P1, P3, P4_3 to P4_5, P6_0, P6_3 to P6_6. The Pi register consists of a port latch to hold output data and a circuit to read pin states. Figures 8.1 to 8.3 show the Configurations of I/O Ports. Table 8.2 lists the Functions of I/O Ports. Also, Figure 8.5 shows the PDi (i = 0, 1, 3, 4, or 6) Register. Figure 8.6 shows the Pi (i = 0, 1, 3, 4, or 6) Register, Figure 8.7 shows Registers PINSR2, PINSR3, and PINSR4, Figure 8.8 shows the PMR Register, Figure 8.9 shows Registers PUR0 and PUR1. Table 8.2 Functions of I/O Ports Operation When Value of PDi_j Bit in PDi Register(1) Accessing When PDi_j Bit is Set to 0 (Input Mode) When PDi_j Bit is Set to 1 (Output Mode) Pi Register Reading Read pin input level Read the port latch Write to the port latch. The value written to Writing Write to the port latch the port latch is output from the pin. i = 0, 1, 3, 4, 6, j = 0 to 7 NOTE: 1. Nothing is assigned to bits PD0_0 to PD0_3, PD4_0 to PD4_2, PD4_6, PD4_7, PD6_1, PD6_2, PD6_7. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 65 of 318 R8C/2G Group 8. I/O Ports 8.2 Effect on Peripheral Functions I/O ports function as I/O ports for peripheral functions (refer to Table 1.3 Pin Name Information by Pin Number). Table 8.3 lists the Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 0, 1, 3, 4, 6, j = 0 to 7). Refer to the description of each function for information on how to set peripheral functions. Table 8.3 Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 0, 1, 3, 4, 6, j = 0 to 7) I/O of Peripheral Functions PDi_j Bit Settings for Shared Pin Functions(1) Input Set this bit to 0 (input mode). Output This bit can be set to either 0 or 1 (output regardless of the port setting) NOTE: 1. Nothing is assigned to bits PD0_0 to PD0_3, PD4_0 to PD4_2, PD4_6, PD4_7, PD6_1, PD6_2, PD6_7. 8.3 Pins Other than Programmable I/O Ports Figure 8.4 shows the Configuration of I/O Pins. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 66 of 318 R8C/2G Group 8. I/O Ports P0_4, P1_4, P3_0, P3_1, P3_4, P3_5, P3_7, P6_0, and P6_3 Pull-up selection Direction register 1 (Note 1) Output from individual peripheral function Data bus Port latch (Note 1) P0_5 Direction register Pull-up selection (Note 1) Data bus Port latch (Note 1) P0_6, P3_2, P3_6, and P4_5 Pull-up selection Direction register (Note 1) Data bus Port latch (Note 1) INT0, INT1, INT2, and INT4 input Digital filter NOTE: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. Figure 8.1 Configuration of I/O Ports (1) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 67 of 318 R8C/2G Group 8. I/O Ports P0_7, P6_4, and P6_6 Pull-up selection Direction register (Note 1) Data bus Port latch (Note 1) Input to individual peripheral function P1_0 to P1_2 Direction register Pull-up selection 1 (Note 1) Output from individual peripheral function Data bus Port latch (Note 1) Input to individual peripheral function Analog input P1_3, P1_6, P3_3, and P6_5 Pull-up selection Direction register 1 (Note 1) Output from individual peripheral function Data bus Port latch (Note 1) Input to individual peripheral function NOTE: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. Figure 8.2 Configuration of I/O Ports (2) Page 68 of 318 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 R8C/2G Group 8. I/O Ports P1_5 and P1_7 Direction register Pull-up selection 1 (Note 1) Output from individual peripheral function Data bus Port latch (Note 1) INT1 input Input to individual peripheral function Digital filter P4_3/XCIN Direction register Pull-up selection (Note 1) Data bus Port latch (Note 1) Clocked inverter(2) (Note 3) P4_4/XCOUT Direction register (Note 1) Data bus Port latch (Note 1) NOTES: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. 2. When CM10 = 1 or CM04 = 0, the clocked inverter is cut off. 3. When CM04 = 0 the feedback resistor is disconnected. Figure 8.3 Configuration of I/O Ports (3) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 69 of 318 R8C/2G Group 8. I/O Ports MODE MODE signal input (Note 1) RESET RESET signal input (Note 1) (Note 1) NOTE: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. Figure 8.4 Configuration of I/O Pins Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 70 of 318 R8C/2G Group 8. I/O Ports Port Pi Direction Register (i = 0, 1, 3, 4, or 6)(1, 2, 3, 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PD0 PD1 PD3 PD4 PD6 Bit Symbol PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7 Address 00E2h 00E3h 00E7h 00EAh 00EEh Bit Name Port Pi_0 direction bit Port Pi_1 direction bit Port Pi_2 direction bit Port Pi_3 direction bit Port Pi_4 direction bit Port Pi_5 direction bit Port Pi_6 direction bit Port Pi_7 direction bit After Reset 00h 00h 00h 00h 00h Function 0 : Input mode (functions as an input port) 1 : Output mode (functions as an output port) RW RW RW RW RW RW RW RW RW NOTES: 1. Set the PD0 register by using the next instruction after setting the PRC2 bit in the PRCR register to 1 (w rite enable). 2. Bits PD0_0 to PD0_3 in the PD0 register are unavailable on this MCU. If it is necessary to set bits PD0_0 to PD0_3 , set to 0 (input mode). When read, the content is 0. 3. Bits PD4_0 to PD4_2, PD4_6, and PD4_7 in the PD4 register are unavailable on this MCU. If it is necessary to set bits PD4_0 to PD4_2, PD4_6, and PD4_7, set to 0 (input mode). When read, the content is 0. To use port P4_4 as an output port, set the PD4_4 bit to 1 (output mode). Do not use port P4_4 as an input port. 4. Bits PD6_1, PD6_2, and PD6_7 in the PD6 register are unavailable on this MCU. If it is necessary to set bits PD6_1, PD6_2, and PD6_7, set to 0 (input mode). When read, the content is 0. Figure 8.5 PDi (i = 0, 1, 3, 4, or 6) Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 71 of 318 R8C/2G Group 8. I/O Ports Port Pi Register (i = 0, 1, 3, 4, or 6)(1, 2, 3) b7 b6 b5 b4 b3 b2 b1 b0 Symbol P0 P1 P3 P4 P6 Bit Symbol Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 Pi_5 Pi_6 Pi_7 Address 00E0h 00E1h 00E5h 00E8h 00ECh Bit Name Port Pi_0 bit Port Pi_1 bit Port Pi_2 bit Port Pi_3 bit Port Pi_4 bit Port Pi_5 bit Port Pi_6 bit Port Pi_7 bit After Reset 00h 00h 00h 00h 00h Function The pin level of any I/O port w hich is set to input mode can be read by reading the corresponding bit in this register. The pin level of any I/O port w hich is set to output mode can be controlled by w riting to the corresponding bit in this register. 0 : “L” level 1 : “H” level RW RW RW RW RW RW RW RW RW NOTES: 1. Bits P0_0 to P0_3 in the P0 register are unavailable on this MCU. If it is necessary to set bits P0_0 to P0_3, set to 0 (“L” level). When read, the content is 0. 2. Bits P4_0 to P4_2, P4_6, and P4_7 in the P4 register are unavailable on this MCU. If it is necessary to set bits P4_0 to P4_2, P4_6, and P4_7, set to 0 (“L” level). When read, the content is 0. 3. Bits P6_1, P6_2, and P6_7 in the P6 register are unavailable on this MCU. If it is necessary to set bits P6_1, P6_2, and P6_7, set to 0 (“L” level). When read, the content is 0. Figure 8.6 Pi (i = 0, 1, 3, 4, or 6) Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 72 of 318 R8C/2G Group 8. I/O Ports Pin Select Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PINSR2 Bit Symbol — (b3-b0) TRAOSEL — (b5) TRBOSEL — (b7) Address 00F6h Bit Name Nothing is assigned. If necessary, set to 0. When read, the content is 0. TRAO pin select bit 0 : P3_0 1 : P3_7 After Reset 00h Function RW — RW — RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. TRBO pin select bit 0 : P3_1 1 : P1_3 Nothing is assigned. If necessary, set to 0. When read, the content is 0. Pin Select Register 3 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PINSR3 Bit Symbol — (b4-b0) TREOSEL — (b7-b6) Address 00F7h Bit Name Nothing is assigned. If necessary, set to 0. When read, the content is 0. TREO pin select bit 0 : P6_0 1 : P0_4 After Reset 00h Function RW — RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. Pin Select Register 4 b7 b6 b5 b4 b3 b2 b1 b0 000 Symbol PINSR4 Bit Symbol TRFOSEL COMPSEL KI0SEL KI1SEL — (b6-b4) TREOSEL2 Address 02FBh Bit Name TRFO11 pin select bit Voltage monitor/comparator select bit After Reset 00h Function 0 : P3_4 1 : P3_7 0 : Voltage monitor 1, voltage monitor 2 1 : Comparator 1, comparator 2 0 : P1_0 1 : P0_7 0 : P1_1 1 : P6_6 Set to 0. 0 : TREOSEL bit in PINSR3 register enabled 1 : P6_5 RW RW RW RW RW RW RW KI0 pin select bit ____ ____ KI1 pin select bit Reserved bits TREO pin select 2 bit Figure 8.7 Registers PINSR2, PINSR3, and PINSR4 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 73 of 318 R8C/2G Group 8. I/O Ports Port Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PMR Bit Symbol INT1SEL — (b7-b1) Address 00F8h Bit Name _____ INT1 pin select bit After Reset 00h Function 0 : P1_5, P1_7 1 : P3_6 RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. Figure 8.8 PMR Register Pull-Up Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address 00FCh PUR0 Bit Symbol Bit Name Nothing is assigned. If necessary, set to 0. — When read, the content is 0. (b0) PU01 PU02 PU03 — (b5-b4) PU06 PU07 (1) After Reset 00h Function RW — RW RW RW — RW RW 0 : Not pulled up P0_4 to P0_7 pull-up 1 : Pulled up P1_0 to P1_3 pull-up(1) P1_4 to P1_7 pull-up(1) Nothing is assigned. If necessary, set to 0. When read, the content is 0. P3_0 to P3_3 pull-up P3_4 to P3_7 pull-up(1) (1) 0 : Not pulled up 1 : Pulled up NOTE: 1. When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up. Pull-Up Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR1 Bit Symbol PU10 PU11 — (b3-b2) PU14 PU15 — (b7-b6) Address 00FDh Bit Name P4_3 pull-up(1) P4_5 pull-up(1) Nothing is assigned. If necessary, set to 0. When read, the content is 0. After Reset 00h Function 0 : Not pulled up 1 : Pulled up RW RW RW — RW RW — P6_0, P6_3 pull-up(1) 0 : Not pulled up 1 : Pulled up P6_4 to P6_6 pull-up(1) Nothing is assigned. If necessary, set to 0. When read, the content is 0. NOTE: 1. When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up. Figure 8.9 Registers PUR0 and PUR1 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 74 of 318 R8C/2G Group 8. I/O Ports 8.4 Port Setting Table 8.4 to Table 8.33 list the port setting. Table 8.4 Register Bit Setting value Port P0_4/(TREO) PD0 PD0_4 0 1 X 0 PINSR4 TREOSEL2 PINSR3 TREOSEL Other than 011b Other than 011b 1 1 TRECR1 TOENA Function Input port(1) Output port TREO output X: 0 or 1 NOTE: 1. Pulled up by setting the PU01 bit in the PUR0 register to 1. Table 8.5 Register Bit Setting value Port P0_5 PD0 PD0_5 0 1 Input port(1) Output port Function NOTE: 1. Pulled up by setting the PU01 bit in the PUR0 register to 1. Table 8.6 Register Bit Setting value Port P0_6/INT4 PD0 PD0_6 0 1 0 INTEN2 INT4EN 0 0 1 Input port(1) Output port INT4 input (1) Function NOTE: 1. Pulled up by setting the PU01 bit in the PUR0 register to 1. Table 8.7 Register Bit Setting value Port P0_7/(KI0) PD0 PD0_7 0 1 0 PINSR4 KI0SEL X X 1 KIEN KI0EN 0 0 1 Input port(1) Output port KI0 input(1) Function X: 0 or 1 NOTE: 1. Pulled up by setting the PU01 bit in the PUR0 register to 1. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 75 of 318 R8C/2G Group 8. I/O Ports Table 8.8 Register Bit Port P1_0/KI0/TRFO00/VCMP1 PD1 PD1_0 0 1 TRFOUT TRFOUT0 0 0 1 0 0 PINSR4 KI0SEL X X X 0 X KIEN KI0EN 0 0 0 1 0 VCAB VCAB5 0 0 0 0 1 Input port(1) Output port TRFO00 output KI0 input(1) VCMP1 input(1) Function Setting value X 0 0 X: 0 or 1 NOTE: 1. Pulled up by setting the PU02 bit in the PUR0 register to 1. Table 8.9 Register Bit Port P1_1/KI1/TRFO01/VCMP2 PD1 PD1_1 0 1 TRFOUT TRFOUT1 0 0 1 0 0 PINSR4 KI1SEL X X X 0 X KIEN KI1EN 0 0 0 1 0 VCAB VCAB6 0 0 0 0 1 Input port(1) Output port TRFO01 output KI1 input(1) VCMP2 input(1) Function Setting value X 0 0 X: 0 or 1 NOTE: 1. Pulled up by setting the PU02 bit in the PUR0 register to 1. Table 8.10 Register Bit Port P1_2/KI2/TRFO02/CVREF PD1 PD1_2 0 1 X 0 0 TRFOUT TRFOUT2 0 0 1 0 0 KIEN KI2EN 0 0 0 1 0 VCAB VCAB7 0 0 0 0 1 Input port(1) Output port TRFO02 output KI2 input(1) CVREF input(1) Function Setting value X: 0 or 1 NOTE: 1. Pulled up by setting the PU02 bit in the PUR0 register to 1. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 76 of 318 R8C/2G Group 8. I/O Ports Table 8.11 Register Bit Port P1_3/KI3/VCOUT1/(TRBO) PD1 PD1_3 0 1 0 X X Timer RB Setting − Other than TRBO usage conditions Other than TRBO usage conditions Other than TRBO usage conditions Refer to Table 8.12 TRBO Pin Setting Other than TRBO usage conditions KIEN KI3EN 0 0 1 0 0 ALCMR CM1OE 0 0 0 0 1 Input port(1) Output port KI3 input(1) TRBO output VCOUT1 output Function Setting value X: 0 or 1 NOTE: 1. Pulled up by setting the PU02 bit in the PUR0 register to 1. Table 8.12 Register Bit TRBO Pin Setting PINSR2 TRBOSEL 1 1 TRBIOC TOCNT(1) 0 0 0 1 TMOD1 0 1 1 0 TRBMR TMOD0 1 0 1 1 Function Programmable waveform generation mode Programmable one-shot generation mode Programmable wait one-shot generation mode P1_3 output port Other than TRBO usage conditions Setting value 1 1 Other than above NOTE: 1. Set the TOCNT bit in the TRBIOC register to 0 in modes except for programmable waveform generation mode. Table 8.13 Register Bit Port P1_4/TXD0 PD1 PD1_4 0 1 SMD2 0 0 0 X 0 1 1 U0MR SMD1 0 0 SMD0 0 0 1 0 1 0 TXD0 output(2) Input port(1) Output port Function Setting value X: 0 or 1 NOTES: 1. Pulled up by setting the PU03 bit in the PUR0 register to 1. 2. N-channel open-drain output by setting the NCH bit in the U0C0 register to 1. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 77 of 318 R8C/2G Group 8. I/O Ports Table 8.14 Register Bit Port P1_5/RXD0/(TRAIO)/(INT1) PD1 PD1_5 0 0 1 0 1 0 1 1 1 1 TRAIOC TIOSEL TOPCR(2) X 1 0 X 0 X 0 0 1 0 0 0 TMOD2 X 0 X 0 X TRAMR TMOD1 X 0 X 0 X Other than 001b 0 0 1 TMOD0 X 1 0 X 0 X X 0 Input port(1) PMR INT1SEL INTEN INT1EN Function 1 Setting value 0 0 0 0 X X 0 X 0 0 0 1 X 1 X Output port RXD0 input(1) INT1 input(1) TRAIO input(1) TRAIO input/INT1 input(1) TRAIO output Other than 000b, 001b Other than 000b, 001b X 0 1 1 0 0 X X: 0 or 1 NOTES: 1. Pulled up by setting the PU03 bit in the PUR0 register to 1. 2. Set the TOPCR bit in the TRAIOC register to 0 in modes except for pulse output mode. Table 8.15 Register Bit Port P1_6/CLK0/VCOUT2 PD1 PD1_6 0 ALCMR CM2OE 0 0 0 0 1 CKDIR 0 1 X 0 1 X 0 X X X SMD2 U0MR SMD1 Other than 001b X Other than 001b 0 X X 1 X X X SMD0 Function Input port(1) Output port CLK0 output CLK0 input(1) VCOUT2 output Setting value 1 X 0 X X: 0 or 1 NOTE: 1. Pulled up by setting the PU03 bit in the PUR0 register to 1. Table 8.16 Register Bit Port P1_7/TRAIO/INT1 PD1 PD1_7 0 1 0 1 0 0 0 0 0 TRAIOC TIOSEL TOPCR(2) X 1 0 X 0 0 1 0 0 0 TMOD2 X 0 X 0 0 TRAMR TMOD1 X 0 X 0 0 TMOD0 X 1 0 X 0 0 1 X 0 X 0 X 0 1 X 1 X Output port INT1 input(1) TRAIO input(1) TRAIO input/INT1 input(1) TRAIO output X 0 Input port(1) PMR INT1SEL INTEN INT1EN Function Setting value 1 0 0 0 X Other than 000b, 001b Other than 000b, 001b 0 0 1 X: 0 or 1 NOTES: 1. Pulled up by setting the PU03 bit in the PUR0 register to 1. 2. Set the TOPCR bit in the TRAIOC register to 0 in modes except for pulse output mode. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 78 of 318 R8C/2G Group 8. I/O Ports Table 8.17 Register Bit Setting value Port P3_0/TRAO PD3 PD3_0 0 1 X PINSR2 TRAOSEL X X 0 TRAIOC TOENA 0 0 1 Input port(1) Output port TRAO output Function X: 0 or 1 NOTE: 1. Pulled up by setting the PU06 bit in the PUR0 register to 1. Table 8.18 Register Bit Setting value Port P3_1/TRBO PD3 PD3_1 0 1 X Timer RB Setting − Other than TRBO usage conditions Other than TRBO usage conditions Refer to Table 8.19 TRBO Pin Setting Input port(1) Output port TRBO output Function X: 0 or 1 NOTE: 1. Pulled up by setting the PU06 bit in the PUR0 register to 1. Table 8.19 Register Bit TRBO Pin Setting PINSR2 TRBOSEL 0 0 0 0 TRBIOC TOCNT(1) 0 0 0 1 TMOD1 0 1 1 0 TRBMR TMOD0 1 0 1 1 Function Programmable waveform generation mode Programmable one-shot generation mode Programmable wait one-shot generation mode P3_1 output port Other than TRBO usage conditions Setting value Other than above NOTE: 1. Set the TOCNT bit in the TRBIOC register to 0 in modes except for programmable waveform generation mode. Table 8.20 Register Bit Setting value Port P3_2/INT2 PD3 PD3_2 0 1 0 INTEN INT2EN 0 0 1 Input port(1) Output port INT2 input Function NOTE: 1. Pulled up by setting the PU06 bit in the PUR0 register to 1. Table 8.21 Register Bit Setting value Port P3_3/TRFO10/TRFI PD3 PD3_3 0 1 X 0 TRFOUT TRFOUT3 0 0 1 0 Input port(1) Output port TRFO10 output TRFI input(1) Function X: 0 or 1 NOTE: 1. Pulled up by setting the PU06 bit in the PUR0 register to 1. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 79 of 318 R8C/2G Group 8. I/O Ports Table 8.22 Register Bit Setting value Port P3_4/TRFO11 PD3 PD3_4 0 1 X PINSR4 TRFOSEL X X 0 TRFOUT TRFOUT4 0 0 1 Input port(1) Output port TRFO11 output Function X: 0 or 1 NOTE: 1. Pulled up by setting the PU07 bit in the PUR0 register to 1. Table 8.23 Register Bit Setting value Port P3_5/TRFO12 PD3 PD3_5 0 1 X TRFOUT TRFOUT5 0 0 1 Input port(1) Output port TRFO12 output Function X: 0 or 1 NOTE: 1. Pulled up by setting the PU07 bit in the PUR0 register to 1. Table 8.24 Register Bit Setting value Port P3_6/(INT1) PD3 PD3_6 0 1 0 PMR INT1SEL X X 1 INTEN INT1EN 0 0 1 Input port(1) Output port INT1 input(1) Function X: 0 or 1 NOTE: 1. Pulled up by setting the PU07 bit in the PUR0 register to 1. Table 8.25 Register Bit Setting value Port P3_7/(TRAO)/(TRFO11) PD3 PD3_7 0 1 X X PINSR2 TRAOSEL X X 1 X TRAIOC TOENA 0 0 1 0 PINSR4 TRFOSEL X X X 1 TRFOUT TRFOUT4 0 0 0 1 Input port(1) Output port TRAO output TRFO11 output Function X: 0 or 1 NOTE: 1. Pulled up by setting the PU07 bit in the PUR0 register to 1. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 80 of 318 R8C/2G Group 8. I/O Ports Table 8.26 Register Bit Port P4_3/(XCIN) PD4 PD4_3 0 1 X CM0 CM04 0 0 1 1 1 1 CM10 X X 0 0 1 0 CM1 CM12 X X 0 1 0 1 0 1 Circuit specifications Oscillation Feedback buffer resistor OFF OFF ON ON OFF OFF ON ON OFF OFF ON OFF ON OFF ON OFF Input port(1, 2) Output port(2) XCIN clock oscillation (on-chip feedback resistor enabled) XCIN clock oscillation (on-chip feedback resistor disabled) XCIN clock oscillation stop External XCIN clock input Function Setting value X X X X: 0 or 1 NOTES: 1. Pulled up by setting the PU10 bit in the PUR1 register to 1. 2. Refer to 8.6.1 Port P4_3, P4_4. Table 8.27 Register Bit Port P4_4/(XCOUT) PD4 PD4_4 1 X CM0 CM04 0 1 1 1 1 CM10 X 0 0 1 0 CM1 CM12 X 0 1 0 1 0 1 Circuit specifications Oscillation Feedback buffer resistor OFF OFF ON ON OFF OFF ON ON ON OFF ON OFF ON OFF Function Output port(1) XCIN clock oscillation (on-chip feedback resistor enabled) XCIN clock oscillation (on-chip feedback resistor disabled) XCIN clock oscillation stop External XCOUT clock output (inverted output of XCIN clock) Setting value X X X X: 0 or 1 NOTE: 1. Refer to 8.6.1 Port P4_3, P4_4. Table 8.28 Register Bit Setting value Port P4_5/INT0 PD4 PD4_5 0 1 0 INTEN INT0EN 0 0 1 Input port(1) Output port INT0 input Function NOTE: 1. Pulled up by setting the PU11 bit in the PUR1 register to 1. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 81 of 318 R8C/2G Group 8. I/O Ports Table 8.29 Register Bit Setting value Port P6_0/TREO PD6 PD6_0 0 1 X 0 PINSR4 TREOSEL2 PINSR3 TREOSEL Other than 001b Other than 001b 0 1 TRECR1 TOENA Function Input port(1) Output port TREO output X: 0 or 1 NOTE: 1. Pulled up by setting the PU14 bit in the PUR1 register to 1. Table 8.30 Register Bit Port P6_3/TXD2 PD6 PD6_3 0 1 SMD2 0 0 0 X 0 1 1 U2MR SMD1 0 0 SMD0 0 0 1 0 1 0 TXD2 output(2) Input port(1) Output port Function Setting value X: 0 or 1 NOTES: 1. Pulled up by setting the PU14 bit in the PUR1 register to 1. 2. N-channel open-drain output by setting the NCH bit in the U2C0 register to 1. Table 8.31 Register Bit Setting value Port P6_4/RXD2 PD6 PD6_4 0 1 0 Input port(1) Output port RXD2 input(1) Function NOTE: 1. Pulled up by setting the PU15 bit in the PUR1 register to 1. Table 8.32 Register Bit Port P6_5/CLK2/(TREO) PD6 PD6_5 0 PINSR4 TREOSEL2 0 0 0 0 1 TRECR1 TOENA X X X X 1 CKDIR 0 1 X 0 1 X 0 X X X SMD2 U2MR SMD1 Other than 001b X Other than 001b 0 X X 1 X X X SMD0 Function Input port(1) Output port CLK2 output CLK2 input(1) TREO output Setting value 1 X 0 X X: 0 or 1 NOTE: 1. Pulled up by setting the PU15 bit in the PUR1 register to 1. Table 8.33 Register Bit Setting value Port P6_6/(KI1) PD6 PD6_6 0 1 0 PINSR4 KI1SEL X X 1 INTEN INT0EN 0 0 1 Input port(1) Output port KI1 input(1) Function X: 0 or 1 NOTE: 1. Pulled up by setting the PU15 bit in the PUR1 register to 1. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 82 of 318 R8C/2G Group 8. I/O Ports 8.5 Unassigned Pin Handling Table 8.34 lists Unassigned Pin Handling. Table 8.34 Unassigned Pin Handling Pin Name Connection Ports P0_4 to P0_7, P1, P3, • After setting to input mode, connect each pin to VSS via a resistor P4_3 to P4_5, P6_0, P6_3 to P6_6 (pull-down) or connect each pin to VCC via a resistor (pull-up).(2) • After setting to output mode, leave these pins open.(1, 2) RESET (3) Connect to VCC via a pull-up resistor(2) NOTES: 1. If these ports are set to output mode and left open, they remain in input mode until they are switched to output mode by a program. The voltage level of these pins may be undefined and the power current may increase while the ports remain in input mode. The content of the direction registers may change due to noise or program runaway caused by noise. In order to enhance program reliability, the program should periodically repeat the setting of the direction registers. 2. Connect these unassigned pins to the MCU using the shortest wire length (2 cm or less) possible. 3. When the power-on reset function is in use. MCU Port P0_4 to P0_7, (Input mode ) : P1, P3 : P4_3 to P4_5, (Input mode) P6_0, P6_3 to P6_6 (Output mode) : : Open RESET(1) NOTE: 1. When the power-on reset function is in use. Figure 8.10 Unassigned Pin Handling Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 83 of 318 R8C/2G Group 8. I/O Ports 8.6 8.6.1 Notes on I/O Ports Port P4_3, P4_4 Ports P4_3 and P4_4 are also used as the XCIN function and the XCOUT function, respectively. During a reset period and after a reset release, these ports are set to the XCIN and XCOUT functions. Pins P4_3 and P4_4 can be switched to the port functions by setting the CM04 bit in the CM0 register to 0 (ports P4_3 and P4_4) by a program. To use ports P4_3 and P4_4 as ports, note the following: • Port P4_3 After a reset until the CM04 bit is set to 0 (ports P4_3 and P4_4) by a program, a typical 10 MΩ impedance is connected between the P4_3 pin and the MCU power supply or GND. If the XCIN is set to intermediate-level input or left floating, a shoot-through current flows into the oscillation driver. • Port P4_4 Use port P4_4 as an output port by setting the PD4_4 bit in the PD4 register to 1 (output mode). After a reset until the CM04 bit is set to 0 (ports P4_3 and P4_4) by a program, the P4_4 pin may output an intermediate potential of about 2.0 V. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 84 of 318 R8C/2G Group 9. Processor Mode 9. 9.1 Processor Mode Processor Modes Single-chip mode can be selected as the processor mode. Table 9.1 lists Features of Processor Mode. Figure 9.1 shows the PM0 Register and Figure 9.2 shows the PM1 Register. Table 9.1 Features of Processor Mode Accessible Areas Pins Assignable as I/O Port Pins SFR, internal RAM, internal ROM All pins are I/O ports or peripheral function I/O pins Processor Mode Single-chip mode Processor Mode Register 0(1) b7 b6 b5 b4 b3 b2 b1 b0 000 Symbol Address PM0 0004h Bit Symbol Bit Name — Reserved bits (b2-b0) PM03 — (b7-b4) Softw are reset bit After Reset 00h Function Set to 0. The MCU is reset w hen this bit is set to 1. When read, the content is 0. RW RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. NOTE: 1. Set the PRC1 bit in the PRCR register to 1 (w rite enable) before rew riting the PM0 register. Figure 9.1 PM0 Register Processor Mode Register 1(1) b7 b6 b5 b4 b3 b2 b1 b0 0 00 Symbol Address PM1 0005h Bit Symbol Bit Name — Reserved bits (b1-b0) PM12 — (b6-b3) — (b7) WDT interrupt/reset sw itch bit After Reset 00h Function Set to 0. 0 : Watchdog timer interrupt 1 : Watchdog timer reset(2) RW RW RW — RW Nothing is assigned. If necessary, set to 0. When read, the content is 0. Reserved bit Set to 0. NOTES: 1. Set the PRC1 bit in the PRCR register to 1 (w rite enable) before rew riting the PM1 register. 2. The PM12 bit is set to 1 by a program (It remains unchanged even if 0 is w ritten to it). When the CSPRO bit in the CSPR register is set to 1 (count source protect mode enabled), the PM12 bit is automatically s et to 1. Figure 9.2 PM1 Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 85 of 318 R8C/2G Group 10. Bus 10. Bus The bus cycles differ when accessing ROM/RAM, and when accessing SFR. Table 10.1 lists Bus Cycles by Access Space of the R8C/2G Group. ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units, these areas are accessed twice in 8-bit units. Table 10.2 lists Access Units and Bus Operations. Table 10.1 SFR ROM/RAM Table 10.2 Area Even address Byte access CPU clock Address Data Odd address Byte access CPU clock Address Data Even address Word access CPU clock Address Data Odd address Word access CPU clock Address Data Odd Data Odd + 1 Data Even Data Even + 1 Data Even Data Bus Cycles by Access Space of the R8C/2G Group Access Area Bus Cycle 2 cycles of CPU clock 1 cycle of CPU clock Access Units and Bus Operations SFR CPU clock Address Data CPU clock Odd Data Address Data CPU clock Address Data CPU clock Address Data Odd Data Odd + 1 Data Even Data Even + 1 Data Odd Data Even Data ROM, RAM Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 86 of 318 R8C/2G Group 11. Clock Generation Circuit 11. Clock Generation Circuit The clock generation circuit has: • XCIN clock oscillation circuit • Low-speed on-chip oscillator • High-speed on-chip oscillator Table 11.1 lists Specifications of Clock Generation Circuit. Figure 11.1 shows a Clock Generation Circuit. Figures 11.2 to 11.8 show clock associated registers. Figure 11.9 shows a Handling Procedure of Internal Power Low Consumption Using VCA20 Bit. Table 11.1 Item Applications Specifications of Clock Generation Circuit XCIN Clock Oscillation Circuit • CPU clock source • Peripheral function clock source 32.768 kHz • Crystal oscillator XCIN, XCOUT(1) Usable Oscillate On-Chip Oscillator High-Speed On-Chip Oscillator Low-Speed On-Chip Oscillator • CPU clock source • CPU clock source • Peripheral function clock • Peripheral function clock source source Approx. 8 MHz Approx. 125 kHz − − −(1) Usable Stop −(1) Usable Oscillate − Clock frequency Connectable oscillator Oscillator connect pins Oscillation stop, restart function Oscillator status after reset Others • Externally generated clock can − be input(2) • On-chip feedback resistor RfXCIN (connected/ not connected, selectable) NOTES: 1. These pins can be used as P4_3 or P4_4 when using the on-chip oscillator clock as the CPU clock while the XCIN clock oscillation circuit is not used. 2. Set the CM04 bit in the CM0 register to 1 (XCIN-XCOUT pin) when an external clock is input. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 87 of 318 R8C/2G Group 11. Clock Generation Circuit fC4 fC HRA1 register Frequency adjustable HRA00 High-speed on-chip oscillator HRA2 register 1/4 1/8 fC32 Clock prescaler fOCO-F Watchdog timer HRA01 = 1 HRA01 = 0 On-chip oscillator clock fOCO INT0 Timer RA Timer RB Timer RE Timer RF UART0 UART2 Stop signal CM14 Low-speed on-chip oscillator fOCO-S Power-on reset circuit Voltage detection circuit b c d f1 f2 f4 e f8 g a f32 XCIN XCOUT OCD2 = 1 CM04 OCD2 = 0 Divider CPU clock XCIN clock CM02 CM10 = 1 (stop mode) RESET Power-on reset Software reset Interrupt request WAIT instruction System clock SQ R b SQ R CM06 = 0 CM17 to CM16 = 11b CM06 = 1 c 1/2 1/2 d 1/2 e 1/2 1/2 g a CM06 = 0 CM17 to CM16 = 10b CM02, CM04, CM06: Bits in CM0 register CM10, CM14, CM16, CM17: Bits in CM1 register OCD2: Bits in OCD register HRA00, HRA01: Bits in HRA0 register CM06 = 0 CM17 to CM16 = 01b CM06 = 0 CM17 to CM16 = 00b h Detail of divider Figure 11.1 Clock Generation Circuit Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 88 of 318 R8C/2G Group 11. Clock Generation Circuit System Clock Control Register 0(1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol Address 0006h CM0 Bit Symbol Bit Name — Nothing is assigned. If necessary, set to 0. (b0) When read, the content is 0. — (b1) Reserved bit WAIT peripheral function clock stop bit Set to 0. After Reset 01011000b Function RW — RW CM02 0 : Peripheral function clock does not stop in w ait mode 1 : Peripheral function clock stops in w ait mode 0 : LOW 1 : HIGH RW CM03 CM04 — (b5) CM06 — (b7) XCIN-XCOUT drive capacity select bit(2) RW RW — RW RW Port, XCIN-XCOUT sw itch bit(3, 4) 0 : Ports P4_3, P4_4 1 : XCIN-XCOUT pin Nothing is assigned. If necessary, set to 0. When read, the content is 0. System clock division select bit 0(5) Reserved bit 0 : CM16, CM17 enabled 1 : Divide-by-8 mode Set to 0. NOTES: 1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM0 register. 2. When entering stop mode, the CM03 bit is set to 1 (HIGH). Rew rite the CM03 bit w hile the XCIN clock oscillation stabilizes. 3. P4_3 and P4_4 can be used as ports w hen the CM04 bit is set to 0 (ports P4_3 and P4_4). To use the XCIN clock, set the CM04 bit to 1 (XCIN-XCOUT pin). Also, set port P4_3 as input port w ithout pull-up. 4. If the CM10 bit in the CM1 register is set to 1 (stop mode), w hen the CM04 bit is set to 1 (XCIN-XCOUT pin), the XCIN(P4_3) pin is set to the high-impedance state and the XCOUT (P4_4) pin is set to “H”. When the CM04 bit is set to 0 (I/O ports P4_3 and P4_4), pins XCIN (P4_3) and XOUT (P4_4) retain the I/O status (status just before stop mode is entered). 5. When entering stop mode, the CM06 bit is set to 1 (divide-by-8 mode). Figure 11.2 CM0 Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 89 of 318 R8C/2G Group 11. Clock Generation Circuit System Clock Control Register 1(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol CM1 Bit Symbol CM10 — (b1) CM12 — (b3) CM14 — (b5) CM16 Address 0007h Bit Name All clock stop control bit(2, 3, 4) After Reset 00h Function 0 : Clock operates 1 : Stops all clocks (stop mode) RW RW — RW — RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. XCIN-XCOUT on-chip feedback resistor select bit 0 : On-chip feedback resistor enabled 1 : On-chip feedback resistor disabled Nothing is assigned. If necessary, set to 0. When read, the content is 0. Low -speed on-chip oscillation stop bit(4, 5, 6, 7) 0 : Low -speed on-chip oscillator on 1 : Low -speed on-chip oscillator off Nothing is assigned. If necessary, set to 0. When read, the content is 0. System clock division select bits 1(8) b7 b6 CM17 0 0 : No division mode 0 1 : Divide-by-2 mode 1 0 : Divide-by-4 mode 1 1 : Divide-by-16 mode RW RW NOTES: 1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM1 register. 2. If the CM10 bit is set to 1 (stop mode), the on-chip feedback resistor is disabled. 3. If the CM10 bit is set to 1 (stop mode), w hen the CM04 bit in the CM0 register is set to 1 (XCIN-XCOUT pin), the XCIN(P4_3) pin is set to the high-impedance state and the XCOUT (P4_4) pin is set to “H”. When the CM04 bit is set to 0 (I/O ports P4_3 and P4_4), pins XCIN (P4_3) and XOUT (P4_4) retain the I/O status (status just before stop mode is entered). 4. In count source protect mode enabled of w atchdog timer (refer to 16.2 Count Source Protection Mode Enabled), the value remains unchanged even if bits CM10 and CM14 are set. 5. When the OCD2 bit in the OCD register is set to 0 (XCIN clock selected), the CM14 bit is set to 1 (low -speed on-chip oscillator off). When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low -speed on-chip oscillator on). It remains unchanged even if 1 is w ritten to it. 6. When using the voltage monitor 1 interrupt or voltage monitor 2 interrupt (w hen using the digital filter), set the CM14 bit to 0 (low -speed on-chip oscillator on). 7. In count source protect mode enabled, the CM14 bit is set to 0 (low -speed on-chip oscillator on). It remains unchanged even if 1 is w ritten to it. 8. When the CM06 bit in the CM0 register is set to 0 (bits CM16, CM17 enabled), bits CM16 to CM17 are enabled. Figure 11.3 CM1 Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 90 of 318 R8C/2G Group 11. Clock Generation Circuit System Clock Select Register(1) b7 b6 b5 b4 b3 b2 b1 b0 000 Symbol Address 000Ch OCD Bit Symbol Bit Name — Nothing is assigned. If necessary, set to 0. (b1-b0) When read, the content is 0. OCD2 — (b3) — (b6-b4) — (b7) System clock select bit After Reset 00000100b Function RW — RW — RW — 0 : Selects XCIN clock 1 : Selects on-chip oscillator clock(2) Nothing is assigned. If necessary, set to 0. When read, the content is 0. Reserved bits Set to 0. Nothing is assigned. If necessary, set to 0. When read, the content is 0. NOTES: 1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting to the OCD register. 2. The CM14 in the CM1 register bit is set to 0 (low -speed on-chip oscillator on) if the OCD2 bit is set to 1 (on-chip oscillator clock selected). Figure 11.4 OCD Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 91 of 318 R8C/2G Group 11. Clock Generation Circuit High-Speed On-Chip Oscillator Control Register 0(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol HRA0 Bit Symbol HRA00 HRA01 — (b7-b2) Address 0020h Bit Name High-speed on-chip oscillator enable bit High-speed on-chip oscillator select bit(2) After Reset 00h Function 0 : High-speed on-chip oscillator off 1 : High-speed on-chip oscillator on 0 : Selects low -speed on-chip oscillator (3) 1 : Selects high-speed on-chip oscillator RW RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. NOTES: 1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the HRA0 register. 2. Change the HRA01 bit under the follow ing conditions. • HRA00 = 1 (high-speed on-chip oscillation on) • The CM14 bit in the CM1 register = 0 (low -speed on-chip oscillator on) 3. When setting the HRA01 bit to 0 (low -speed on-chip oscillator selected), do not set the HRA00 bit to 0 (high-speed on-chip oscillator off) at the same time. Set the HRA00 bit to 0 after setting the HRA01 bit to 0. High-Speed On-Chip Oscillator Control Register 1(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol HRA1 Address 0021h After Reset When Shipping RW Function The frequency of the high-speed on-chip oscillator is adjusted w ith bits 0 to 7.(2) High-speed on-chip oscillator frequency = 8 MHz (HRA1 register = value w hen shipping; fOCO-fast mode 0) Setting the HRA1 register to a low er value results in a higher frequency. Setting the HRA1 register to a higher value results in a low er frequency. RW NOTES: 1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the HRA1 register. 2. When changing the values of the HRA1 register, adjust these bits not to exceed the maximum value of the system clock. High-Speed On-Chip Oscillator Control Register 2(1) b7 b6 b5 b4 b3 b2 b1 b0 000 0 Symbol Address 0022h HRA2 Bit Symbol Bit Name Reserved bit — (b0) High-speed on-chip oscillator mode select bit(3) After Reset 00h Function Set to 0. 0: fOCO-fast mode 0 (8 MHz w hen the HRA1 register is set to the value w hen shipping ) 1: fOCO-fast mode 2(2) Set to 0. RW RW HRA21 RW — (b4-b2) — (b7-b5) Reserved bits RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. NOTES: 1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the HRA2 register. 2. Sw itching fOCO-fast mode 0 to fOCO-fast mode 2 multiplies the frequency by 0.5. 3. Set this bit not to exceed the maximum value of the system clock. Figure 11.5 Registers HRA0, HRA1, and HRA2 Page 92 of 318 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 R8C/2G Group 11. Clock Generation Circuit Clock Prescaler Reset Flag b7 b6 b5 b4 b3 b2 b1 b0 0000000 Symbol Address 0028h CPSRF Bit Symbol Bit Name — Reserved bits (b6-b0) CPSR Clock prescaler reset flag(1) After Reset 00h Function Set to 0. Setting this bit to 1 initializes the clock prescaler. (When read, the content is 0) RW RW RW NOTE: 1. Only w rite 1 to this bit w hen selecting the XCIN clock as the CPU clock, . Figure 11.6 CPSRF Register High-Speed On-Chip Oscillator Control Register 4 b7 b6 b5 b4 b3 b2 b1 b0 Symbol FRA4 Address 0029h After Reset When Shipping RW RO Function Stores data for frequency correction w hen VCC = 2.7 to 5.5 V. (The value is the same as that of the HRA1 register after a reset.) Optimal frequency correction to match the voltage conditions can be achieved by transferring this value to the HRA1 register. High-Speed On-Chip Oscillator Control Register 6 b7 b6 b5 b4 b3 b2 b1 b0 Symbol FRA6 Address 002Bh After Reset When Shipping RW RO Function Stores data for frequency correction w hen VCC = 2.2 to 5.5 V. Optimal frequency correction to match the voltage conditions can be achieved by transferring this value to the HRA1 register. Figure 11.7 Registers FRA4 and FRA6 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 93 of 318 R8C/2G Group 11. Clock Generation Circuit Voltage Detection Register 2(1) b7 b6 b5 b4 b3 b2 b1 b0 0000 Symbol Address VCA2 Bit Symbol VCA20 — (b4-b1) VCA25 VCA26 VCA27 0032h Bit Name Internal pow er low consumption enable bit(6) Reserved bits Voltage detection 0 enable bit(2) Voltage detection 1 enable bit(3) Voltage detection 2 enable bit(4) After Reset(5) The LVD0ON bit in the OFS register is set to 1 and hardw are reset : 00h Pow er-on reset, voltage monitor 0 reset or LVD0ON bit in the OFS register is set to 0, and hardw are reset : 00100000b Function 0 : Low consumption disabled 1 : Low consumption enabled(7) Set to 0. 0 : Voltage detection 0 circuit disabled 1 : Voltage detection 0 circuit enabled 0 : Voltage detection 1 circuit disabled 1 : Voltage detection 1 circuit enabled 0 : Voltage detection 2 circuit disabled 1 : Voltage detection 2 circuit enabled RW RW RW RW RW RW NOTES: 1. Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting to the VCA2 register. 2. To use the voltage monitor 0 reset, set the VCA25 bit to 1. After the VCA25 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting operation. 3. To use the voltage monitor 1 interrupt/reset or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1. After the VCA26 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting operation. 4. To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1. After the VCA27 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting operation. 5. Softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this register. 6. Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in Figure 11.9 Handling Procedure of Internal Pow er Low Consum ption Using VCA20 Bit. 7. When the VCA20 bit is set to 1 (low consumption enabled), do not set the CM10 bit in the CM1 register to 1 (stop mode). Figure 11.8 VCA2 Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 94 of 318 R8C/2G Group 11. Clock Generation Circuit Exit wait mode by interrupt Handling procedure of internal power low consumption enabled by VCA20 bit (Note 1) In interrupt routine Step (1) Enter low-speed clock mode or low-speed on-chip oscillator mode Step (5) VCA20 ← 0 (internal power low consumption disabled)(2) Step (2) Stop high-speed on-chip oscillator clock Step (6) Start high-speed on-chip oscillator clock Step (3) VCA20 ← 1 (internal power low consumption enabled)(2) Step (7) (Wait until high-speed on-chip oscillator clock oscillation stabilizes) If it is necessary to start the high-speed on-chip oscillator in the interrupt routine, execute steps (5) to (8) in the interrupt routine. Step (4) Enter wait mode(3) Step (8) Enter high-speed on-chip oscillator mode Step (5) VCA20 ← 0 (internal power low consumption disabled)(2) Interrupt handling Step (6) Start high-speed on-chip oscillator clock Step (1) Enter low-speed clock mode or low-speed on-chip oscillator mode If high-speed on-chip oscillator is started in the interrupt routine, execute steps (1) to (3) at the last of the interrupt routine. Step (7) (Wait until high-speed on-chip oscillator clock oscillation stabilizes) Step (2) Stop high-speed on-chip oscillator clock Step (8) Enter high-speed on-chip oscillator mode Step (3) VCA20 ← 1 (internal power low consumption enabled)(2, 3) Interrupt handling completed NOTES: 1. Execute this routine to handle all interrupts generated in wait mode. However, this does not apply if it is not necessary to start high-speed on-chip oscillator during the interrupt routine. 2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite. 3. When entering wait mode, follow 11.5.2 Wait Mode. VCA20: Bit in VCA2 register Figure 11.9 Handling Procedure of Internal Power Low Consumption Using VCA20 Bit Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 95 of 318 R8C/2G Group The clocks generated by the clock generation circuits are described below. 11. Clock Generation Circuit 11.1 On-Chip Oscillator Clocks These clocks are supplied by the on-chip oscillators (high-speed on-chip oscillator and a low-speed on-chip oscillator). The on-chip oscillator clock is selected by the HRA01 bit in the HRA0 register. 11.1.1 Low-Speed On-Chip Oscillator Clock The clock generated by the low-speed on-chip oscillator is used as the clock source for the CPU clock, peripheral function clock, fOCO, and fOCO-S. After reset, the on-chip oscillator clock generated by the low-speed on-chip oscillator divided by 8 is selected as the CPU clock. The frequency of the low-speed on-chip oscillator varies depending on the supply voltage and the operating ambient temperature. Application products must be designed with sufficient margin to allow for frequency changes. 11.1.2 High-Speed On-Chip Oscillator Clock The clock generated by the high-speed on-chip oscillator is used as the clock source for the CPU clock, peripheral function clock, fOCO, and fOCO-F. After reset, the on-chip oscillator clock generated by the high-speed on-chip oscillator stops. Oscillation is started by setting the HRA00 bit in the HRA0 register to 1 (high-speed on-chip oscillator on). The frequency can be adjusted by registers HRA1 and HRA2. Furthermore, frequency correction data corresponding to the supply voltage ranges listed below is stored in registers FRA4 and FRA6. To use separate correction values to match these voltage ranges, transfer them from register FRA4 or FRA6 to the HRA1 register. • FRA4 register: Stores data for frequency correction corresponding to VCC = 2.7 V to 5.5 V. (The value is the same as that of the HRA1 register after a reset.) • FRA6 register: Stores data for frequency correction corresponding to VCC = 2.2 V to 5.5 V. Since there are differences in the amount of frequency adjustment among the bits in the HRA1 register, make adjustments by changing the settings of individual bits. Adjust the HRA1 register so that the frequency of the high-speed on-chip oscillator clock does not exceed the maximum value of the system clock. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 96 of 318 R8C/2G Group 11. Clock Generation Circuit 11.2 XCIN Clock This clock is supplied by the XCIN clock oscillation circuit. This clock is used as the clock source for the CPU clock, peripheral function clock. The XCIN clock oscillation circuit is configured by connecting a resonator between the XCIN and XCOUT pins. The XCIN clock oscillation circuit includes an on-chip a feedback resistor, which is disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed in the chip. The XCIN clock oscillation circuit may also be configured by feeding an externally generated clock to the XCIN pin. Figure 11.10 shows Examples of XCIN Clock Connection Circuits. During and after reset, the XCIN clock oscillates. The XCIN clock starts oscillating when the CM04 bit in the CM0 register is set to 1 (XCIN-XCOUT pin). To use the XCIN clock for the CPU clock source, set the OCD2 bit in the OCD register to 0 (selects XCIN clock) after the XCIN clock is oscillating stably. This MCU has an on-chip feedback resistor and on-chip resistor disable/enable switching is possible by the CM12 bit in the CM1 register. In stop mode, all clocks including the XCIN clock stop. Refer to 11.4 Power Control for details. MCU (on-chip feedback resistor) XCIN Rf(1) XCOUT MCU (on-chip feedback resistor) XCIN XCOUT Open Rd(1) Externally derived clock CIN COUT VCC VSS External clock input circuit External crystal oscillator circuit NOTE: 1. Insert a damping resistor and feedback resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the manufacturer of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added to the chip externally, insert a feedback resistor between XCIN and XCOUT following the instructions. Figure 11.10 Examples of XCIN Clock Connection Circuits Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 97 of 318 R8C/2G Group 11. Clock Generation Circuit 11.3 CPU Clock and Peripheral Function Clock There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer to Figure 11.1 Clock Generation Circuit. 11.3.1 System Clock The system clock is the clock source for the CPU and peripheral function clocks. Either the XCIN clock or the on-chip oscillator clock can be selected. 11.3.2 CPU Clock The CPU clock is an operating clock for the CPU and watchdog timer. The system clock can be divided by 1 (no division), 2, 4, 8, or 16 to produce the CPU clock. Use the CM06 bit in the CM0 register and bits CM16 to CM17 in the CM1 register to select the value of the division. Use the XCIN clock while the XCIN clock oscillation stabilizes. After reset, the low-speed on-chip oscillator clock divided by 8 provides the CPU clock. When entering stop mode from high-speed clock mode, the CM06 bit is set to 1 (divide-by-8 mode). 11.3.3 Peripheral Function Clock (f1, f2, f4, f8, and f32) The peripheral function clock is the operating clock for the peripheral functions. The clock fi (i = 1, 2, 4, 8, and 32) is generated by the system clock divided by i. The clock fi is used for timers RA, RB, RE, and RF, and the serial interface. When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to 1 (peripheral function clock stops in wait mode), the clock fi stop. 11.3.4 fOCO fOCO is an operating clock for the peripheral functions. fOCO runs at the same frequency as the on-chip oscillator clock and can be used as the source for timer RA. When the WAIT instruction is executed, the clocks fOCO does not stop. 11.3.5 fOCO-F fOCO-F is generated by the high-speed on-chip oscillator and supplied by setting the HRA00 bit to 1. When the WAIT instruction is executed, the clock fOCO-F does not stop. 11.3.6 fOCO-S fOCO-S is an operating clock for the watchdog timer and voltage detection circuit. fOCO-S is supplied by setting the CM14 bit to 0 (low-speed on-chip oscillator on) and uses the clock generated by the low-speed onchip oscillator. When the WAIT instruction is executed or in count source protect mode of the watchdog timer, fOCO-S does not stop. 11.3.7 fC4 and fC32 The clock fC4 is used for timer RE and the clock fC32 is used for timer RA, timer RF, and watchdog timer. Use fC4 and fC32 while the XCIN clock oscillation stabilizes. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 98 of 318 R8C/2G Group 11. Clock Generation Circuit 11.4 Power Control There are three power control modes. All modes other than wait mode and stop mode are referred to as standard operating mode. 11.4.1 Standard Operating Mode Standard operating mode is further separated into three modes. In standard operating mode, the CPU clock and the peripheral function clock are supplied to operate the CPU and the peripheral function clocks. Power consumption control is enabled by controlling the CPU clock frequency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU clock frequency, the more power consumption decreases. When unnecessary oscillator circuits stop, power consumption is further reduced. Before the clock sources for the CPU clock can be switched over, the new clock source needs to be oscillating and stable. If the new clock source is the XCIN clock, allow sufficient wait time in a program until oscillation is stabilized before exiting. Table 11.2 Settings and Modes of Clock Associated Bits Modes CM0 Register CM06 CM04 0 − 0 − 0 − 1 − 0 − 0 − 0 − 0 − 1 − 0 − 0 1 0 1 0 1 1 1 0 1 HRA0 Register HRA01 HRA00 1 1 1 1 1 1 1 1 1 1 0 − 0 − 0 − 0 − 0 − − − − − − − − − − − OCD Register CM1 Register OCD2 CM17, CM16 CM14 High-speed on-chip No division 1 00b − oscillator mode Divide-by-2 1 01b − Divide-by-4 1 10b − Divide-by-8 1 − − Divide-by-16 1 11b − Low-speed on-chip No division 1 00b 0 oscillator mode Divide-by-2 1 01b 0 Divide-by-4 1 10b 0 Divide-by-8 1 − 0 Divide-by-16 1 11b 0 Low-speed clock No division 0 00b − mode Divide-by-2 0 01b − Divide-by-4 0 10b − Divide-by-8 0 − − Divide-by-16 0 11b − −: Can be 0 or 1, no change in outcome Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 99 of 318 R8C/2G Group 11. Clock Generation Circuit 11.4.1.1 High-Speed On-Chip Oscillator Mode The high-speed on-chip oscillator is used as the on-chip oscillator clock when the HRA00 bit in the HRA0 register is set to 1 (high-speed on-chip oscillator on) and the HRA01 bit in the HRA0 register is set to 1. The onchip oscillator divided by 1 (no division), 2, 4, 8, or 16 provides the CPU clock. Set the CM06 bit to 1 (divideby-8 mode) when transiting to high-speed clock mode. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used as the watchdog timer and voltage detection circuit. 11.4.1.2 Low-Speed On-Chip Oscillator Mode If the CM14 bit in the CM1 register is set to 0 (low-speed on-chip oscillator on) or the HRA01 bit in the HRA0 register is set to 0, the low-speed on-chip oscillator provides the on-chip oscillator clock. The on-chip oscillator clock divided by 1 (no division), 2, 4, 8 or 16 provides the CPU clock. The on-chip oscillator clock is also the clock source for the peripheral function clocks. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used as the watchdog timer and voltage detection circuit. In this mode, stopping the high-speed on-chip oscillator, and setting the FMR47 bit in the FMR4 register to 1 (flash memory low consumption current read mode enabled) enables low consumption operation. To enter wait mode from low-speed on-chip oscillator mode, setting the VCA20 bit in the VCA2 register to 1 (internal power low consumption enabled) enables lower consumption current in wait mode. Refer to 21. Reducing Power Consumption for how to reduce the power consumption. 11.4.1.3 Low-Speed Clock Mode The XCIN clock divided by 1 (no division), 2, 4, 8, or 16 provides the CPU clock. Set the CM06 bit to 1 (divide by-8 mode) when transiting to high-speed on-chip oscillator mode, low-speed on-chip oscillator mode. If the CM14 bit is set to 0 (low-speed on-chip oscillator on) or the HRA00 bit in the HRA0 register is set to 1 (high speed on-chip oscillator on), fOCO can be used as timer RA. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used as the watchdog timer and voltage detection circuit. In this mode, stopping the high-speed on-chip oscillator, and setting the FMR47 bit in the FMR4 register to 1 (flash memory low consumption current read mode enabled) enables low consumption operation. To enter wait mode from low-speed clock mode, setting the VCA20 bit in the VCA2 register to 1 (internal power low consumption enabled) enables lower consumption current in wait mode. Refer to 21. Reducing Power Consumption for how to reduce the power consumption. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 100 of 318 R8C/2G Group 11. Clock Generation Circuit 11.4.2 Wait Mode Since the CPU clock stops in wait mode, the CPU, which operates using the CPU clock, and the watchdog timer, when count source protection mode is disabled, stop. The XCIN clock and on-chip oscillator clock do not stop and the peripheral functions using these clocks continue operating. 11.4.2.1 Peripheral Function Clock Stop Function If the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the f1, f2, f4, f8, and f32 clocks stop in wait mode. This reduces power consumption. 11.4.2.2 Entering Wait Mode The MCU enters wait mode when the WAIT instruction is executed. 11.4.2.3 Pin Status in Wait Mode The I/O port is the status before wait mode was entered is maintained. 11.4.2.4 Exiting Wait Mode The MCU exits wait mode by a reset or a peripheral function interrupt. The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is set to 0 (peripheral function clock does not stop in wait mode), all peripheral function interrupts can be used to exit wait mode. When the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the peripheral functions using the peripheral function clock stop operating and the peripheral functions operated by external signals or on-chip oscillator clock can be used to exit wait mode. Table 11.3 lists Interrupts to Exit Wait Mode and Usage Conditions. Table 11.3 Interrupts to Exit Wait Mode and Usage Conditions CM02 = 0 Usable when operating with internal or external clock Usable Usable in all modes CM02 = 1 Usable when operating with external clock Usable Can be used if there is no filter in event counter mode. Usable by selecting fOCO or fC32 as count source. (Do not use) Usable when operating in real time clock mode (Do not use) Can be used if there is no filter Usable Usable Interrupt Serial interface interrupt Key input interrupt Timer RA interrupt Timer RB interrupt Timer RE interrupt Timer RF interrupt Usable in all modes Usable in all modes Usable in all modes INT0, INT1, INT2, INT4 interrupt Usable Voltage monitor 1 interrupt Usable Voltage monitor 2 interrupt Usable Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 101 of 318 R8C/2G Group 11. Clock Generation Circuit Figure 11.11 shows the Time from Wait Mode to Interrupt Routine Execution. When using a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT instruction. (1) Set the interrupt priority level in bits ILVL2 to ILVL0 in the interrupt control registers of the peripheral function interrupts to be used for exiting wait mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used for exiting wait mode to 000b (interrupt disabled). (2) Set the I flag to 1. (3) Operate the peripheral function to be used for exiting wait mode. When exiting by a peripheral function interrupt, the time (number of cycles) between interrupt request generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 register, as described in Figure 11.11. The CPU clock, when exiting wait mode by a peripheral function interrupt, is the same clock as the CPU clock when the WAIT instruction is executed. FMR0 Register FMSTP Bit 0 (flash memory operates) 1 (flash memory stops) Time until Flash Memory is Activated (T1) Period of system clock × 12 cycles + 30 µs (max.) Period of system clock × 12 cycles Time until CPU Clock is Supplied (T2) Period of CPU clock × 6 cycles Same as above Time for Interrupt Sequence (T3) Remarks Period of CPU clock Following total time is the time × 20 cycles from wait mode until an interrupt routine is Same as above executed. T1 Wait mode Flash memory activation sequence Interrupt request generated T2 CPU clock restart sequence T3 Interrupt sequence Figure 11.11 Time from Wait Mode to Interrupt Routine Execution Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 102 of 318 R8C/2G Group 11. Clock Generation Circuit 11.4.3 Stop Mode Since the oscillator circuits stop in stop mode, the CPU clock and peripheral function clock stop and the CPU and peripheral functions that use these clocks stop operating. The least power required to operate the MCU is in stop mode. If the voltage applied to the VCC pin is VRAM or more, the contents of internal RAM is maintained. The peripheral functions clocked by external signals continue operating. Table 11.4 lists Interrupts to Exit Stop Mode and Usage Conditions. Table 11.4 Interrupts to Exit Stop Mode and Usage Conditions Usage Conditions − Interrupt Key input interrupt INT0, INT1, INT2, INT4 interrupt Can be used if there is no filter Timer RA interrupt When there is no filter and external pulse is counted in event counter mode Serial interface interrupt When external clock is selected Voltage monitor 1 interrupt Usable in digital filter disabled mode (VW1C1 bit in VW1C register is set to 1) Voltage monitor 2 interrupt Usable in digital filter disabled mode (VW2C1 bit in VW2C register is set to 1) 11.4.3.1 Entering Stop Mode The MCU enters stop mode when the CM10 bit in the CM1 register is set to 1 (all clocks stop). At the same time, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode), the CM03 bit in the CM0 register is set to 1 (XCIN clock oscillator circuit drive capacity high). 11.4.3.2 Pin Status in Stop Mode The status before wait mode was entered is maintained. When the CM04 bit in the CM0 register is set to 1 (XCIN-XCOUT pin), the XCIN(P4_3) pin is set to the highimpedance state and the XCOUT (P4_4) pin is set to “H”. When the CM04 bit is set to 0 (I/O ports P4_3 and P4_4), pins XCIN (P4_3) and XOUT (P4_4) retain the I/O status (status just before stop mode is entered). Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 103 of 318 R8C/2G Group 11. Clock Generation Circuit 11.4.3.3 Exiting Stop Mode The MCU exits stop mode by a reset or peripheral function interrupt. Figure 11.12 shows the Time from Stop Mode to Interrupt Routine Execution. When using a peripheral function interrupt to exit stop mode, set up the following before setting the CM10 bit to 1. (1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peripheral function interrupts to be used for exiting stop mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used for exiting stop mode to 000b (interrupt disabled). (2) Set the I flag to 1. (3) Operates the peripheral function to be used for exiting stop mode. When exiting by a peripheral function interrupt, the interrupt sequence is executed when an interrupt request is generated and the CPU clock supply is started. If the clock used immediately before stop mode is a system clock and stop mode is exited by a peripheral function interrupt, the CPU clock becomes the previous system clock divided by 8. FMR0 Register FMSTP Bit 0 (flash memory operates) 1 (flash memory stops) Time until Flash Memory is Activated (T2) Period of system clock × 12 cycles + 30 µs (max.) Period of system clock × 12 cycles Time until CPU Clock is Supplied (T3) Period of CPU clock × 6 cycles Same as above Time for Interrupt Sequence (T4) Remarks Period of CPU clock Following total time of T0 to T4 is × 20 cycles the time from stop mode until an interrupt handling Same as above is executed. T0 Stop mode Internal power stability time T1 Oscillation time of CPU clock source used immediately before stop mode T2 Flash memory activation sequence T3 CPU clock restart sequence T4 Interrupt sequence 150 µs Interrupt (max.) request generated Figure 11.12 Time from Stop Mode to Interrupt Routine Execution Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 104 of 318 R8C/2G Group Figure 11.13 shows the State Transitions in Power Control Mode. 11. Clock Generation Circuit Reset Standard operating mode Low-speed on-chip oscillator mode CM14 = 0 OCD2 = 1 HRA01 = 0 CM04 = 1 OCD2 = 0 CM14 = 0 OCD2 = 1 HRA01 = 0 CM14 = 0 HRA01 = 0 HRA00 = 1 HRA01 = 1 Low-speed clock mode CM04 = 1 OCD2 = 0 CM04 = 1 OCD2 = 0 OCD2 = 1 HRA00 = 1 HRA01 = 1 High-speed on-chip oscillator mode OCD2 = 1 HRA00 = 1 HRA01 = 1 Interrupt WAIT instruction Interrupt CM10 = 1 Wait mode CPU operation stops CM04: Bit in CM0 register CM10, CM14: Bits in CM1 register OCD2: Bit in OCD register HRA00, HRA01: Bits in HRA0 register Stop mode All oscillators stop Figure 11.13 State Transitions in Power Control Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 105 of 318 R8C/2G Group 11. Clock Generation Circuit 11.5 11.5.1 Notes on Clock Generation Circuit Stop Mode When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit to 1 (stop mode) and the program stops. Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets the CM10 bit to 1. • Program example to enter stop mode BCLR BSET FSET BSET JMP.B LABEL_001 : NOP NOP NOP NOP 1,FMR0 0,PRCR I 0,CM1 LABEL_001 ; CPU rewrite mode disabled ; Protect disabled ; Enable interrupt ; Stop mode 11.5.2 Wait Mode When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the program stops. Insert at least 4 NOP instructions after the WAIT instruction. • Program example to execute the WAIT instruction BCLR 1,FMR0 FSET I WAIT NOP NOP NOP NOP ; CPU rewrite mode disabled ; Enable interrupt ; Wait mode 11.5.3 Oscillation Circuit Constants Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 106 of 318 R8C/2G Group 12. Protection 12. Protection The protection function protects important registers from being easily overwritten when a program runs out of control. Figure 12.1 shows the PRCR Register. The registers protected by the PRCR register are listed below. • Registers protected by PRC0 bit: Registers CM0, CM1, OCD, HRA0, HRA1, and HRA2 • Registers protected by PRC1 bit: Registers PM0 and PM1 • Registers protected by PRC2 bit: PD0 register • Registers protected by PRC3 bit: Registers VCA2, VW0C, VW1C, VW2C, VCAB, BGRCR, and BGRTRM Protect Register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol PRCR Bit Symbol Address 000Ah Bit Name Protect bit 0 PRC0 After Reset 00h Function Writing to registers CM0, CM1, OCD, HRA0, HRA1, and HRA2 is enabled. 0 : Disables w riting 1 : Enables w riting Writing to registers PM0 and PM1 is enabled. 0 : Disables w riting 1 : Enables w riting Writing to the PD0 register is enabled. 0 : Disables w riting 1 : Enables w riting(1) Writing to registers VCA2, VW0C, VW1C, VW2C, VCAB, BGRCR, and BGRTRM is enabled. 0 : Disables w riting 1 : Enables w riting Set to 0. RW RW Protect bit 1 PRC1 Protect bit 2 PRC2 Protect bit 3 PRC3 RW RW RW — (b5-b4) — (b7-b6) Reserved bits RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. NOTE: 1. This PRC2 bit is set to 0 after w riting 1 to this bit and executing a w rite to any address. Since the other bits are not set to 0, set them to 0 by a program. Figure 12.1 PRCR Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 107 of 318 R8C/2G Group 13. Interrupts 13. Interrupts 13.1 13.1.1 Interrupt Overview Types of Interrupts Figure 13.1 shows the Types of Interrupts. Software (non-maskable interrupts) Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Watchdog timer Voltage monitor 1 Voltage monitor 2 Comparator 1(2) Comparator 2(2) Single step(3) Address break(3) Address match Interrupts Special (non-maskable interrupts) Peripheral functions(1) (maskable interrupts) Hardware NOTES: 1. Peripheral function interrupts in the MCU are used to generate peripheral interrupts. 2. When non-maskable interrupts is selected. 3. Do not use this interrupt. This is for use with development tools only. Figure 13.1 Types of Interrupts • Maskable Interrupts: • Non-Maskable Interrupts: The interrupt enable flag (I flag) enables or disables these interrupts. The interrupt priority order can be changed based on the interrupt priority level. The interrupt enable flag (I flag) does not enable or disable these interrupts. The interrupt priority order cannot be changed based on interrupt priority level. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 108 of 318 R8C/2G Group 13. Interrupts 13.1.2 Software Interrupts A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable. 13.1.2.1 Undefined Instruction Interrupt The undefined instruction interrupt is generated when the UND instruction is executed. 13.1.2.2 Overflow Interrupt The overflow interrupt is generated when the O flag is set to 1 (arithmetic operation overflow) and the INTO instruction is executed. Instructions that set the O flag are: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, and SUB. 13.1.2.3 BRK Interrupt A BRK interrupt is generated when the BRK instruction is executed. 13.1.2.4 INT Instruction Interrupt An INT instruction interrupt is generated when the INT instruction is executed. The INT instruction can select software interrupt numbers 0 to 63. Software interrupt numbers 3 to 31 are assigned to the peripheral function interrupt. Therefore, the MCU executes the same interrupt routine when the INT instruction is executed as when a peripheral function interrupt is generated. For software interrupt numbers 0 to 31, the U flag is saved to the stack during instruction execution and the U flag is set to 0 (ISP selected) before the interrupt sequence is executed. The U flag is restored from the stack when returning from the interrupt routine. For software interrupt numbers 32 to 63, the U flag does not change state during instruction execution, and the selected SP is used. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 109 of 318 R8C/2G Group 13. Interrupts 13.1.3 Special Interrupts Special interrupts are non-maskable. However, the comparator 1 and comparator 2 can select maskable interrupts, too. 13.1.3.1 Watchdog Timer Interrupt The watchdog timer interrupt is generated by the watchdog timer. For details of the watchdog timer, refer to 16. Watchdog Timer. 13.1.3.2 Voltage Monitor 1 Interrupt The voltage monitor 1 interrupt is generated by the voltage monitor 1 circuit. For details of the voltage monitor 1 circuit, refer to 6. Voltage Detection Circuit. 13.1.3.3 Voltage Monitor 2 Interrupt The voltage monitor 2 interrupt is generated by the voltage monitor 2 circuit. For details of the voltage monitor 2, refer to 6. Voltage Detection Circuit. 13.1.3.4 Comparator 1 Interrupt The comparator 1 interrupt is generated by the comparator 1. The non-maskable interrupt or maskable interrupt can be selected. For details of the comparator 1 interrupt, refer to 7. Comparator. 13.1.3.5 Comparator 2 Interrupt The comparator 2 interrupt is generated by the comparator 2. The non-maskable interrupt or maskable interrupt can be selected. For details of the comparator 2 interrupt, refer to 7. Comparator. 13.1.3.6 Single-Step Interrupt, and Address Break Interrupt Do not use these interrupts. They are for use by development tools only. 13.1.3.7 Address Match Interrupt The address match interrupt is generated immediately before executing an instruction that is stored at an address indicated by registers RMAD0 to RMAD1 when the AIER0 or AIER1 bit in the AIER register is set to 1 (address match interrupt enable). For details of the address match interrupt, refer to 13.4 Address Match Interrupt. 13.1.4 Peripheral Function Interrupt The peripheral function interrupt is generated by the internal peripheral function of the MCU and is a maskable interrupt. Refer to Table 13.2 Relocatable Vector Tables for sources of the peripheral function interrupt. For details of peripheral functions, refer to the descriptions of individual peripheral functions. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 110 of 318 R8C/2G Group 13. Interrupts 13.1.5 Interrupts and Interrupt Vectors There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector. Figure 13.2 shows an Interrupt Vector. MSB LSB Vector address (L) Low address Mid address 0000 High address 0000 Vector address (H) Figure 13.2 Interrupt Vector 0000 13.1.5.1 Fixed Vector Tables The fixed vector tables are allocated addresses 0FFDCh to 0FFFFh. Table 13.1 lists the Fixed Vector Tables. The vector addresses (H) of fixed vectors are used by the ID code check function. For details, refer to 20.3 Functions to Prevent Rewriting of Flash Memory. Table 13.1 Fixed Vector Tables Vector Addresses Remarks Reference Address (L) to (H) 0FFDCh to 0FFDFh Interrupt on UND R8C/Tiny Series Software instruction Manual 0FFE0h to 0FFE3h Interrupt on INTO instruction 0FFE4h to 0FFE7h If the content of address 0FFE7h is FFh, program execution starts from the address shown by the vector in the relocatable vector table. 0FFE8h to 0FFEBh 13.4 Address Match Interrupt 0FFECh to 0FFEFh 0FFF0h to 0FFF3h 16. Watchdog Timer 6. Voltage Detection Circuit 7. Comparator Interrupt Source Undefined instruction Overflow BRK instruction Address match Single step(1) Watchdog timer, Voltage monitor 1, Voltage monitor 2, Comparator 1, Comparator 2 Address break(1) (Reserved) Reset 0FFF4h to 0FFF7h 0FFF8h to 0FFFBh 0FFFCh to 0FFFFh 5. Resets NOTE: 1. Do not use these interrupts. They are for use by development tools only. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 111 of 318 R8C/2G Group 13. Interrupts 13.1.5.2 Relocatable Vector Tables The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register. Table 13.2 lists the Relocatable Vector Tables. Table 13.2 Relocatable Vector Tables Vector Addresses(1) Address (L) to Address (H) +0 to +3(0000h to 0003h) +4 to +7(0004h to 0007h) +8 to +11(0008h to 000Bh) +40 to +43(0028h to 002Bh) +44 to +47(002Ch to 002Fh) +48 to +51(0030h to 0033h) +52 to +55(0034h to 0037h) Software Interrupt Control Reference Interrupt Register Number 0 − R8C/Tiny Series Software Manual 1 VCMP1IC 7. Comparator 2 VCMP2IC − − 3 to 9 10 TREIC 17.3 Timer RE 11 S2TIC 18. Serial Interface 12 S2RIC 13 KUPIC 13.3 Key Input Interrupt 14 − − 15 − − 16 CMP1IC 17.4 Timer RF 17 S0TIC 18. Serial Interface 18 S0RIC 19 − − 20 − − 21 INT2IC 13.2 INT Interrupt 22 23 24 25 26 27 28 29 30 31 32 to 63 TRAIC − TRBIC INT1IC − TRFIC CMP0IC INT0IC Interrupt Source BRK instruction(2) Comparator 1 Comparator 2 (Reserved) Timer RE UART2 transmit UART2 receive Key input (Reserved) (Reserved) Compare 1 UART0 transmit UART0 receive (Reserved) (Reserved) INT2 Timer RA (Reserved) Timer RB INT1 (Reserved) Timer RF Compare 0 INT0 INT4 Capture Software interrupt(2) +64 to +67(0040h to 0043h) +68 to +71(0044h to 0047h) +72 to +75(0048h to 004Bh) +84 to +87(0054h to 0057h) +88 to +91(0058h to 005Bh) +96 to +99(0060h to 0063h) +100 to +103(0064h to 0067h) +108 to +111(006Ch to 006Fh) +112 to +115(0070h to 0073h) +116 to +119(0074h to 0077h) +120 to +123(0078h to 007Bh) +124 to +127(007Ch to 007Fh) +128 to +131(0080h to 0083h) to +252 to +255(00FCh to 00FFh) 17.1 Timer RA − 17.2 Timer RB 13.2 INT Interrupt 17.4 Timer RF 13.2 INT Interrupt 17.4 Timer RF R8C/Tiny Series Software Manual INT4IC CAPIC − NOTES: 1. These addresses are relative to those in the INTB register. 2. The I flag does not disable these interrupts. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 112 of 318 R8C/2G Group 13. Interrupts 13.1.6 Interrupt Control The following describes enabling and disabling the maskable interrupts and setting the priority for acknowledgement. The explanation does not apply to nonmaskable interrupts. Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in each interrupt control register to enable or disable maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control register. Figure 13.3 shows the Interrupt Control Register and Figure 13.4 shows the INTiIC Register (i=0, 1, 2, 4). Interrupt Control Register(2) Symbol VCMP1IC VCMP2IC TREIC S2TIC S2RIC KUPIC CMP1IC S0TIC S0RIC TRAIC TRBIC TRFIC CMP0IC CAPIC Bit Symbol ILVL0 Address 0041h 0042h 004Ah 004Bh 004Ch 004Dh 0050h 0051h 0052h 0056h 0058h 005Bh 005Ch 005Fh Bit Name Interrupt priority level select bits After Reset XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b Function b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 RW RW ILVL1 ILVL2 Interrupt request bit 0 0 0 : Level 0 (interrupt disable) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : Requests no interrupt 1 : Requests interrupt RW RW IR — (b7-b4) RW(1) — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. NOTES: 1. Only 0 can be w ritten to the IR bit. Do not w rite 1. 2. Rew rite the interrupt control register w hen the interrupt request w hich is applicable for its register is not generated. Refer to 13.5.5 Changing Interrupt Control Register Contents . Figure 13.3 Interrupt Control Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 113 of 318 R8C/2G Group 13. Interrupts INTi Interrupt Control Register (i=0, 1, 2, 4)(2) Symbol INT2IC INT1IC INT0IC INT4IC Bit Symbol ILVL0 Address 0055h 0059h 005Dh 005Eh Bit Name Interrupt priority level select bits After Reset XX00X000b XX00X000b XX00X000b XX00X000b Function b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 0 RW RW ILVL1 ILVL2 Interrupt request bit Polarity sw itch bit(4) Reserved bit 0 0 0 : Level 0 (interrupt disable) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : Requests no interrupt 1 : Requests interrupt 0 : Selects falling edge 1 : Selects rising edge(3) Set to 0. RW RW IR POL — (b5) — (b7-b6) RW(1) RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. NOTES: 1. Only 0 can be w ritten to the IR bit. (Do not w rite 1.) 2. Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated. Refer to 13.5.5 Changing Interrupt Control Register Contents . 3. If the INTiPL bit in registers INTEN and INTEN2 are set to 1 (both edges), set the POL bit to 0 (selects falling edge). 4. The IR bit may be set to 1 (requests interrupt) w hen the POL bit is rew ritten. Refer to 13.5.4 Changing Interrupt Sources . Figure 13.4 INTiIC Register (i=0, 1, 2, 4) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 114 of 318 R8C/2G Group 13. Interrupts 13.1.6.1 I Flag The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable interrupts. Setting the I flag to 0 (disabled) disables all maskable interrupts. 13.1.6.2 IR Bit The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. Then, when the interrupt request is acknowledged and the CPU branches to the corresponding interrupt vector, the IR bit is set to 0 (= interrupt not requested). The IR bit can be set to 0 by a program. Do not write 1 to this bit. 13.1.6.3 ILVL2 to ILVL0 Bits and IPL Interrupt priority levels can be set using bits ILVL2 to ILVL0. Table 13.3 lists the Settings of Interrupt Priority Levels and Table 13.4 lists the Interrupt Priority Levels Enabled by IPL. The following are conditions under which an interrupt is acknowledged: • I flag = 1 • IR bit = 1 • Interrupt priority level > IPL The I flag, IR bit, bits ILVL2 to ILVL0, and IPL are independent of each other. They do not affect one another. Table 13.3 ILVL2 to ILVL0 Bits 000b 001b 010b 011b 100b 101b 110b 111b Settings of Interrupt Priority Levels Interrupt Priority Level Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High Priority Order − Low Table 13.4 IPL 000b 001b 010b 011b 100b 101b 110b 111b Interrupt Priority Levels Enabled by IPL Enabled Interrupt Priority Levels Interrupt level 1 and above Interrupt level 2 and above Interrupt level 3 and above Interrupt level 4 and above Interrupt level 5 and above Interrupt level 6 and above Interrupt level 7 and above All maskable interrupts are disabled Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 115 of 318 R8C/2G Group 13. Interrupts 13.1.6.4 Interrupt Sequence An interrupt sequence is performed between an interrupt request acknowledgement and interrupt routine execution. When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle. However, for the SMOVB, SMOVF, SSTR, or RMPA instructions, if an interrupt request is generated while the instruction is being executed, the MCU suspends the instruction to start the interrupt sequence. The interrupt sequence is performed as indicated below. Figure 13.5 shows the Time Required for Executing Interrupt Sequence. (1) The CPU gets interrupt information (interrupt number and interrupt request level) by reading address 00000h. The IR bit for the corresponding interrupt is set to 0 (interrupt not requested). (2) The FLG register is saved to a temporary register(1) in the CPU immediately before entering the interrupt sequence. (3) The I, D and U flags in the FLG register are set as follows: The I flag is set to 0 (interrupts disabled). The D flag is set to 0 (single-step interrupt disabled). The U flag is set to 0 (ISP selected). However, the U flag does not change state if an INT instruction for software interrupt number 32 to 63 is executed. (4) The CPU’s internal temporary register(1) is saved to the stack. (5) The PC is saved to the stack. (6) The interrupt priority level of the acknowledged interrupt is set in the IPL. (7) The starting address of the interrupt routine set in the interrupt vector is stored in the PC. After the interrupt sequence is completed, instructions are executed from the starting address of the interrupt routine. 1 CPU Clock Address Bus Data Bus RD WR 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Address 0000h Interrupt information Undefined Undefined Undefined SP-2 SP-1 SP-4 SP-3 SP-3 contents VEC VEC contents VEC+1 VEC+1 contents VEC+2 VEC+2 contents PC SP-2 SP-1 SP-4 contents contents contents The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is ready to acknowledge instructions. Figure 13.5 Time Required for Executing Interrupt Sequence NOTE: 1. This register cannot be used by user. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 116 of 318 R8C/2G Group 13. Interrupts 13.1.6.5 Interrupt Response Time Figure 13.6 shows the Interrupt Response Time. The interrupt response time is the period between an interrupt request generation and the execution of the first instruction in the interrupt routine. The interrupt response time includes the period between interrupt request generation and the completion of execution of the instruction (refer to (a) in Figure 13.6) and the period required to perform the interrupt sequence (20 cycles, refer to (b) in Figure 13.6). Interrupt request is generated. Interrupt request is acknowledged. Time Instruction (a) Interrupt sequence 20 cycles (b) Instruction in interrupt routine Interrupt response time (a) Period between interrupt request generation and the completion of execution of an instruction. The length of time varies depending on the instruction being executed. The DIVX instruction requires the longest time, 30 cycles (no wait and when the register is set as the divisor) (b) 21 cycles for address match and single-step interrupts. Figure 13.6 Interrupt Response Time 13.1.6.6 IPL Change when Interrupt Request is Acknowledged When an interrupt request of a maskable interrupt is acknowledged, the interrupt priority level of the acknowledged interrupt is set in the IPL. When a software interrupt or special interrupt request is acknowledged, the level listed in Table 13.5 is set in the IPL. Table 13.5 lists the IPL Value When Software or Special Interrupt Is Acknowledged. Table 13.5 IPL Value When Software or Special Interrupt Is Acknowledged Value Set in IPL 7 Not changed Interrupt Source Watchdog timer, voltage monitor 1, voltage monitor 2, comparator 1(1), comparator 2(1), address break Software, address match, single-step NOTE: 1. When non-maskable interrupts is selected. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 117 of 318 R8C/2G Group 13. Interrupts 13.1.6.7 Saving a Register In the interrupt sequence, the FLG register and PC are saved to the stack. After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG register, are saved to the stack, the 16 low-order bits in the PC are saved. Figure 13.7 shows the Stack State Before and After Acknowledgement of Interrupt Request. The other necessary registers are saved by a program at the beginning of the interrupt routine. The PUSHM instruction can save several registers in the register bank being currently used(1) with a single instruction. NOTE: 1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB. Address MSB Stack LSB Address MSB Stack LSB m−4 m−3 m−2 m−1 m m+1 m−4 m−3 m−2 m−1 PCL PCM FLGL FLGH PCH [SP] New SP value Previous stack contents Previous stack contents [SP] SP value before interrupt is generated m Previous stack contents Previous stack contents m+1 PCH PCM PCL FLGH FLGL : 4 High-order bits of PC : 8 Middle-order bits of PC : 8 Low-order bits of PC : 4 High-order bits of FLG : 8 Low-order bits of FLG Stack state before interrupt request is acknowledged Stack state after interrupt request is acknowledged NOTE: 1.When executing software number 32 to 63 INT instructions, this SP is specified by the U flag. Otherwise it is ISP. Figure 13.7 Stack State Before and After Acknowledgement of Interrupt Request The register saving operation, which is performed as part of the interrupt sequence, saved in 8 bits at a time in four steps. Figure 13.8 shows the Register Saving Operation. Stack Sequence in which order registers are saved [SP]−5 [SP]−4 [SP]−3 [SP]−2 [SP]−1 [SP] Address PCL PCM FLGL FLGH PCH (3) (4) Saved, 8 bits at a time (1) (2) Completed saving registers in four operations. PCH PCM PCL FLGH FLGL : 4 High-order bits of PC : 8 Middle-order bits of PC : 8 Low-order bits of PC : 4 High-order bits of FLG : 8 Low-order bits of FLG NOTE: 1. [SP] indicates the initial value of the SP when an interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. When executing software number 32 to 63 INT instructions, this SP is specified by the U flag. Otherwise it is ISP. Figure 13.8 Register Saving Operation Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 118 of 318 R8C/2G Group 13. Interrupts 13.1.6.8 Returning from an Interrupt Routine When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have been saved to the stack, are automatically restored. The program, that was running before the interrupt request was acknowledged, starts running again. Restore registers saved by a program in an interrupt routine using the POPM instruction or others before executing the REIT instruction. 13.1.6.9 Interrupt Priority If two or more interrupt requests are generated while a single instruction is being executed, the interrupt with the higher priority is acknowledged. Set bits ILVL2 to ILVL0 to select the desired priority level for maskable interrupts (peripheral functions). However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware, and the higher priority interrupts acknowledged. The priority levels of special interrupts, such as reset (reset has the highest priority) and watchdog timer, are set by hardware. Figure 13.9 shows the Priority Levels of Hardware Interrupts. The interrupt priority does not affect software interrupts. The MCU jumps to the interrupt routine when the instruction is executed. Reset Address break Watchdog timer Voltage monitor 1 Voltage monitor 2 Comparator 1(1) Comparator 2(1) Peripheral function Single step Address match High Low NOTE: 1. When non-maskable interrupts is selected. Figure 13.9 Priority Levels of Hardware Interrupts Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 119 of 318 R8C/2G Group 13. Interrupts 13.1.6.10 Interrupt Priority Judgement Circuit The interrupt priority judgement circuit selects the highest priority interrupt, as shown in Figure 13.10. Priority level of interrupt Level 0 (default value) Highest INT4 Compare 0 Timer RB Timer RA Comparator 2(1) Capture INT0 Timer RF INT1 UART0 receive Compare 1 UART2 receive Timer RE INT2 UART0 transmit Key input UART2 transmit Comparator 1(1) IPL Lowest Interrupt request level judgment output signal Interrupt request acknowledged Priority of peripheral function interrupts (if priority levels are same) I flag Address match Watchdog timer Voltage monitor 1 Voltage monitor 2 Comparator 1(2) Comparator 2(2) NOTES: 1. When maskable interrupts is selected. 2. When non-maskable interrupts is selected. Figure 13.10 Interrupt Priority Level Judgement Circuit Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 120 of 318 R8C/2G Group 13. Interrupts 13.2 13.2.1 INT Interrupt INTi Interrupt (i = 0, 1, 2, 4) The INTi interrupt is generated by an INTi input. Table 13.6 lists the Pin Configuration of INT Interrupt. When using the INTi interrupt, the INTiEN bit in registers INTEN and INTEN2 are set to 1 (enable). The edge polarity is selected using the INTiPL bit in registers INTEN and INTEN2, and the POL bit in the INTiIC register. Inputs can be passed through a digital filter with three different sampling clocks. Figure 13.11 shows the INTEN Register. Figure 13.12 shows the INTF Register. Figure 13.13 shows the INTEN2 Register. Figure 13.14 shows the INTF2 Register. Table 13.6 INT0 (P4_5) INT1 (P1_5, P1_7, or P3_6)(1) INT2 (P3_2) INT4 (P0_6) Pin Configuration of INT Interrupt Pin name Input/Output Input Input Input Input INT1 interrupt input INT2 interrupt input INT4 interrupt input Function INT0 interrupt input, Timer RB external trigger input NOTE: 1. The INT1 pin is selected by the INT1SEL bit in the PMR register and the TIOSEL bit in the TRAIOC register. Refer to 8. I/O Ports for details. External Input Enable Register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol INTEN Bit Symbol INT0EN INT0PL INT1EN INT1PL INT2EN INT2PL — (b7-b6) Address 00F9h Bit Name _____ INT0 input enable bit INT0 input polarity select bit(1, 2) _____ _____ After Reset 00h Function 0 : Disable 1 : Enable 0 : One edge 1 : Both edges 0 : Disable 1 : Enable 0 : One edge 1 : Both edges 0 : Disable 1 : Enable 0 : One edge 1 : Both edges Set to 0. RW RW RW RW RW RW RW RW INT1 input enable bit INT1 input polarity select bit(1, 2) _____ _____ INT2 input enable bit INT2 input polarity select bit(1, 2) Reserved bits _____ NOTES: 1. When setting the INTiPL bit (i = 0, 1, 2) to 1 (both edges), set the POL bit in the INTiIC register to 0 (selects falling edge). 2. The IR bit in the INTiIC register may be set to 1 (requests interrupt) w hen the INTiPL bit is rew ritten. Refer to 13.5.4 Changing Interrupt Sources . Figure 13.11 INTEN Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 121 of 318 R8C/2G Group 13. Interrupts _____ INT Input Filter Select Register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol INTF Bit Symbol _____ Address 00FAh Bit Name INT0 input filter select bits b1 b0 After Reset 00h Function 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling RW RW INT0F0 INT0F1 _____ RW INT1F0 INT1 input filter select bits b3 b2 INT1F1 _____ 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling RW RW INT2F0 INT2 input filter select bits b5 b4 INT2F1 — (b7-b6) Reserved bits 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling Set to 0. RW RW RW Figure 13.12 INTF Register External Input Enable Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol INTEN2 Bit Symbol INT4EN INT4PL — (b7-b2) Address 02FDh Bit Name _____ INT4 input enable bit INT4 input polarity select bit(1, 2) _____ After Reset 00h Function 0 : Disable 1 : Enable 0 : One edge 1 : Both edges RW RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. NOTES: 1. When setting the INT4PL bit to 1 (both edges), set the POL bit in the INT4IC register to 0 (selects falling edge). 2. The IR bit in the INT4IC register may be set to 1 (requests interrupt) w hen the INT4PL bit is rew ritten. Refer to 13.5.4 Changing Interrupt Sources . Figure 13.13 INTEN2 Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 122 of 318 R8C/2G Group 13. Interrupts _____ INT Input Filter Select Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol INTF2 Bit Symbol _____ Address 02FEh Bit Name INT4 input filter select bits b1 b0 After Reset 00h Function 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling RW RW INT4F0 INT4F1 — (b7-b2) RW Nothing is assigned. If necessary, set to 0. When read, the content is undefined. — Figure 13.14 INTF2 Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 123 of 318 R8C/2G Group 13. Interrupts 13.2.2 INTi Input Filter (i = 0, 1, 2, 4) The INTi input contains a digital filter. The sampling clock is selected by bits INTiF1 to INTiF0 in registers INTF and INTF2. The IR bit in the INTiIC register is set to 1 (interrupt requested) when the INTi level is sampled for every sampling clock and the sampled input level matches three times. Figure 13.15 shows the Configuration of INTi Input Filter. Figure 13.16 shows an Operating Example of INTi Input Filter. INTiF1 to INTiF0 f1 f8 f32 INTi Port direction register(1) = 01b = 10b = 11b Sampling clock INTiEN Other than INTiF1 to INTiF0 = 00b Digital filter (input level matches 3x) INTi interrupt INTiPL = 0 = 00b INTiF0, INTiF1: Bits in registers INTF and INTF2 INTiEN, INTiPL: Bits in registers INTEN and INTEN2 i = 0, 1, 2, 4 NOTE: 1. INT0: Port P4_5 direction register INT1: Port P1_5 direction register when using the P1_5 pin, Port P1_7 direction register when using the P1_7 pin, Port P3_6 direction register when using the P3_6 pin INT2: Port P3_2 direction register INT4: Port P0_6 direction register Both edges detection INTiPL = 1 circuit Figure 13.15 Configuration of INTi Input Filter INTi input Sampling timing IR bit in INTiIC register Set to 0 by a program NOTE: 1. This is an operation example when bits INTiF1 to INTiF0 in registers INTF and INTF2 are set to 01b, 10b, or 11b (passing digital filter). i = 0, 1, 2, 4 Figure 13.16 Operating Example of INTi Input Filter Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 124 of 318 R8C/2G Group 13. Interrupts 13.3 Key Input Interrupt A key input interrupt request is generated by one of the input edges of the K10 to K13 pins. Table 13.7 lists the Pin Configuration of Key Input Interrupt. The key input interrupt can be used as a key-on wake-up function to exit wait or stop mode. The KIiEN (i = 0 to 3) bit in the KIEN register can select whether the pins are used as KIi input. The KIiPL bit in the KIEN register can select the input polarity. When inputting “L” to the KIi pin which sets the KIiPL bit to 0 (falling edge), the input of the other pins K10 to K13 is not detected as interrupts. Also, when inputting “H” to the KIi pin, which sets the KIiPL bit to 1 (rising edge), the input of the other pins K10 to K13 is not detected as interrupts. Figure 13.17 shows a Block Diagram of Key Input Interrupt and Figure 13.18 shows the KIEN Register. Table 13.7 Pin Configuration of Key Input Interrupt Pin name KI0 (P0_7 or P1_0(1)) KI1 (P1_1 or P6_6(2)) KI2 (P1_2) KI3 (P1_3) Input/Output Input Input Input Input KI0 input KI1 input KI2 input KI3 input Function NOTES: 1. The KI0 pin is selected by the KI0SEL bit in the PINSR4 register. Refer to 8. I/O Ports for details. 2. The KI1 pin is selected by the KI1SEL bit in the PINSR4 register. Refer to 8. I/O Ports for details. PU02 bit in PUR0 register Pull-up transistor PD1_3 bit in PD1 register KI3EN bit PD1_3 bit KI3PL = 0 KI3 KI3PL = 1 Pull-up transistor KI2 KI2PL = 1 Pull-up transistor KI1 KI1PL = 1 Pull-up transistor KI0 KI0PL = 1 KI0EN bit PD1_0 bit KI0PL = 0 KI0EN, KI1EN, KI2EN, KI3EN, KI0PL, KI1PL, KI2PL, KI3PL: Bits in KIEN register PD1_0, PD1_1, PD1_2, PD1_3: Bits in PD1 register KI1EN bit PD1_1 bit KI1PL = 0 KI2EN bit PD1_2 bit Interrupt control circuit Key input interrupt request KUPIC register KI2PL = 0 Figure 13.17 Block Diagram of Key Input Interrupt Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 125 of 318 R8C/2G Group 13. Interrupts Key Input Enable Register(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol KIEN Bit Symbol KI0EN KI0PL KI1EN KI1PL KI2EN KI2PL KI3EN KI3PL Address 00FBh Bit Name KI0 input enable bit KI0 input polarity select bit KI1 input enable bit KI1 input polarity select bit KI2 input enable bit KI2 input polarity select bit KI3 input enable bit KI3 input polarity select bit After Reset 00h Function 0 : Disable 1 : Enable 0 : Falling edge 1 : Rising edge 0 : Disable 1 : Enable 0 : Falling edge 1 : Rising edge 0 : Disable 1 : Enable 0 : Falling edge 1 : Rising edge 0 : Disable 1 : Enable 0 : Falling edge 1 : Rising edge RW RW RW RW RW RW RW RW RW NOTE: 1. The IR bit in the KUPIC register may be set to 1 (requests interrupt) w hen the KIEN register is rew ritten. Refer to 13.5.4 Changing Interrupt Sources . Figure 13.18 KIEN Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 126 of 318 R8C/2G Group 13. Interrupts 13.4 Address Match Interrupt An address match interrupt request is generated immediately before execution of the instruction at the address indicated by the RMADi register (i = 0 or 1). This interrupt is used as a break function by the debugger. When using the on-chip debugger, do not set an address match interrupt (registers of AIER, RMAD0, and RMAD1 and fixed vector tables) in a user system. Set the starting address of any instruction in the RMADi register. Bits AIER0 and AIER1 in the AIER0 register can be used to select enable or disable of the interrupt. The I flag and IPL do not affect the address match interrupt. The value of the PC (refer to 13.1.6.7 Saving a Register for the value of the PC) which is saved to the stack when an address match interrupt is acknowledged varies depending on the instruction at the address indicated by the RMADi register. (The appropriate return address is not saved on the stack.) When returning from the address match interrupt, return by one of the following means: • Change the content of the stack and use the REIT instruction. • Use an instruction such as POP to restore the stack as it was before the interrupt request was acknowledged. Then use a jump instruction. Table 13.8 lists the Values of PC Saved to Stack when Address Match Interrupt is Acknowledged and Table 13.9 lists the Correspondence Between Address Match Interrupt Sources and Associated Registers. Figure 13.19 shows Registers AIER and RMAD0 to RMAD1. Table 13.8 Values of PC Saved to Stack when Address Match Interrupt is Acknowledged PC Value Saved(1) Address indicated by RMADi register + 2 Address Indicated by RMADi Register (i = 0 or 1) • Instruction with 2-byte operation code(2) • Instruction with 1-byte operation code(2) ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ #IMM8,dest STNZ #IMM8,dest STZX #IMM81,#IMM82,dest CMP.B:S #IMM8,dest PUSHM src POPM dest JMPS #IMM8 JSRS #IMM8 MOV.B:S #IMM,dest (however, dest = A0 or A1) Instructions other than the above Address indicated by RMADi register + 1 NOTES: 1. Refer to the 13.1.6.7 Saving a Register for the PC value saved. 2. Operation code: Refer to the R8C/Tiny Series Software Manual (REJ09B0001). Chapter 4. Instruction Code/Number of Cycles contains diagrams showing operation code below each syntax. Operation code is shown in the bold frame in the diagrams. Table 13.9 Correspondence Between Address Match Interrupt Sources and Associated Registers Address Match Interrupt Source Address Match Interrupt Enable Bit Address Match Interrupt Register Address match interrupt 0 AIER0 RMAD0 Address match interrupt 1 AIER1 RMAD1 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 127 of 318 R8C/2G Group 13. Interrupts A ddress Match Interrupt Enable Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER Bit Symbol AIER0 AIER1 — (b7-b2) Address 0013h Bit Name Address match interrupt 0 enable bit 0 : Disable 1 : Enable Address match interrupt 1 enable bit 0 : Disable 1 : Enable Nothing is assigned. If necessary, set to 0. When read, the content is 0. After Reset 00h Function RW RW RW — Address Match Interrupt Register i (i = 0 or 1) (b23) b7 (b19) b3 (b16) (b15) b0 b7 (b8) b0 b7 b0 Symbol RMAD0 RMAD1 Function Address 0012h-0010h 0016h-0014h After Reset 000000h 000000h Setting Range 00000h to FFFFFh RW RW — Address setting register for address match interrupt — Nothing is assigned. If necessary, set to 0. (b7-b4) When read, the content is 0. Figure 13.19 Registers AIER and RMAD0 to RMAD1 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 128 of 318 R8C/2G Group 13. Interrupts 13.5 13.5.1 Notes on Interrupts Reading Address 00000h Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At this time, the acknowledged interrupt IR bit is set to 0. If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be generated. 13.5.2 SP Setting Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset. Therefore, if an interrupt is acknowledged before setting a value in the SP, the program may run out of control. 13.5.3 External Interrupt and Key Input Interrupt Either “L” level or an “H” level of width shown in the Electrical Characteristics is necessary for the signal input to pins INT0, INT1, INT2, INT4 and pins KI0 to KI3, regardless of the CPU clock. For details, refer to Table 22.17 (VCC = 5V), Table 22.23 (VCC = 3V), and Table 22.29 (VCC = 2.2V) External Interrupt INTi (i = 0, 1, 2, 4) Input. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 129 of 318 R8C/2G Group 13. Interrupts 13.5.4 Changing Interrupt Sources The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source. In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to individual software interrupt numbers, polarities, and timing. Therefore, if a mode change of a peripheral function involves interrupt sources, edge polarities, and timing, set the IR bit to 0 (no interrupt requested) after the change. Refer to the individual peripheral function for its related interrupts. Figure 13.20 shows an Example of Procedure for Changing Interrupt Sources. Interrupt source change Disable interrupts(2, 3) Change interrupt source (including mode of peripheral function) Set the IR bit to 0 (interrupt not requested) using the MOV instruction(3) Enable interrupts (2, 3) Change completed IR bit: The interrupt control register bit of an interrupt whose source is changed. NOTES: 1. Execute the above settings individually. Do not execute two or more settings at once (by one instruction). 2. To prevent interrupt requests from being generated, disable the peripheral function before changing the interrupt source. In this case, use the I flag if all maskable interrupts can be disabled. If all maskable interrupts cannot be disabled, use bits ILVL0 to ILVL2 of the interrupt whose source is changed. 3. Refer to 13.5.5 Changing Interrupt Control Register Contents for the instructions to be used and usage notes. Figure 13.20 Example of Procedure for Changing Interrupt Sources Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 130 of 318 R8C/2G Group 13. Interrupts 13.5.5 Changing Interrupt Control Register Contents (a) The contents of an interrupt control register can only be changed while no interrupt requests corresponding to that register are generated. If interrupt requests may be generated, disable interrupts before changing the interrupt control register contents. (b) When changing the contents of an interrupt control register after disabling interrupts, be careful to choose appropriate instructions. Changing any bit other than IR bit If an interrupt request corresponding to a register is generated while executing the instruction, the IR bit may not be set to 1 (interrupt requested), and the interrupt request may be ignored. If this causes a problem, use the following instructions to change the register: AND, OR, BCLR, BSET Changing IR bit If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used. Therefore, use the MOV instruction to set the IR bit to 0. (c) When disabling interrupts using the I flag, set the I flag as shown in the sample programs below. Refer to (b) regarding changing the contents of interrupt control registers by the sample programs. Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before the interrupt control register is changed for reasons of the internal bus or the instruction queue buffer. Example 1: Use NOP instructions to prevent I flag from being set to 1 before interrupt control register is changed INT_SWITCH1: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h NOP ; NOP FSET I ; Enable interrupts Example 2: Use dummy read to delay FSET instruction INT_SWITCH2: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h MOV.W MEM,R0 ; Dummy read FSET I ; Enable interrupts Example 3: Use POPC instruction to change I flag INT_SWITCH3: PUSHC FLG FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h POPC FLG ; Enable interrupts Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 131 of 318 R8C/2G Group 14. ID Code Areas 14. ID Code Areas 14.1 Overview The ID code areas are used to implement a function that prevents the flash memory from being rewritten in standard serial I/O mode. This function prevents the flash memory from read, rewritten, or erased. The ID code areas are assigned to 0FFDFh, 0FFE3h, 0FFEBh, 0FFEFh, 0FFF3h, 0FFF7h, and 0FFFBh of the respective vector highest-order addresses of the fixed vector table. Figure 14.1 shows the ID Code Areas. ID code areas Address 0FFDFh to 0FFDCh 0FFE3h to 0FFE0h 0FFE7h to 0FFE4h 0FFEBh to 0FFE8h 0FFEFh to 0FFECh 0FFF3h to 0FFF0h 0FFF7h to 0FFF4h 0FFFBh to 0FFF8h 0FFFFh to 0FFFCh ID3 ID4 ID5 ID6 ID7 OFS ID1 ID2 Undefined instruction vector Overflow vector BRK instruction vector Address match vector Single step vector Watchdog timer/voltage monitor 1 and voltage monitor 2/comparator 1 and comparator 2 vector Address break vector (Reserved) Reset vector 4 bytes Figure 14.1 ID Code Areas 14.2 Functions The ID code areas are used in standard serial I/O mode. Unless 3 bytes (addresses from 0FFFCh to 0FFFEh) of the reset vector are set to FFFFFFh, the ID codes stored in the ID code areas and the ID codes sent from the serial programmer or the on-chip debugging emulator are checked to see if they match. If the ID codes match, the commands sent from the serial programmer or the on-chip debugging emulator are acknowledged. If the ID codes do not match, the commands are not acknowledged. To use the serial programmer or the on-chip debugging simulator, first write predetermined ID codes to the ID code areas. As the ID code areas are allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing an instruction. Write appropriate values when creating a program. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 132 of 318 R8C/2G Group 14. ID Code Areas 14.3 14.3.1 Notes on ID Code Areas Setting Example of ID Code Areas As the ID code areas are allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing an instruction. Write appropriate values when creating a program. The following shows a setting example. • To set 55h in all of the ID code areas .org 00FFDCH .lword dummy | (55000000h) ; UND .lword dummy | (55000000h) ; INTO .lword dummy ; BREAK .lword dummy | (55000000h) ; ADDRESS MATCH .lword dummy | (55000000h) ; SET SINGLE STEP .lword dummy | (55000000h) ; WDT .lword dummy | (55000000h) ; ADDRESS BREAK .lword dummy | (55000000h) ; RESERVE (Programming formats vary depending on the compiler. Check the compiler manual.) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 133 of 318 R8C/2G Group 15. Option Function Select Area 15. Option Function Select Area 15.1 Overview The option function select area is used to select the MCU state after reset or the function to prevent rewriting in parallel I/O mode. The reset vector highest-order-address, 0FFFFh, is assigned as the option function select area. Figure 15.1 shows the Option Function Select Area. Option function select area Address 0FFFFh to 0FFFCh OFS Reset vector 4 bytes Figure 15.1 Option Function Select Area Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 134 of 318 R8C/2G Group 15. Option Function Select Area 15.2 OFS Register The OFS register is used to select the MCU state after reset or the function to prevent rewriting in parallel I/O mode. Figure 15.2 shows the OFS Register. Option Function Select Register(1) b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 Symbol OFS Bit Symbol WDTON — (b1) ROMCR ROMCP1 — (b4) Address 0FFFFh Bit Name Watchdog timer start select bit Reserved bit ROM code protect disabled bit ROM code protect bit Reserved bit Voltage detection 0 circuit start bit(2) When Shipping FFh(3) Function 0 : Starts w atchdog timer automatically after reset 1 : Watchdog timer is inactive after reset Set to 1. 0 : ROM code protect disabled 1 : ROMCP1 enabled 0 : ROM code protect enabled 1 : ROM code protect disabled Set to 1. 0 : Voltage monitor 0 reset enabled after hardw are reset 1 : Voltage monitor 0 reset disabled after hardw are reset Set to 1. 0 : Count source protect mode enabled after reset 1 : Count source protect mode disabled after reset RW RW RW RW RW RW LVD0ON RW — (b6) Reserved bit RW Count source protect CSPROINI mode after reset select bit RW NOTES: 1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not w rite additions to the OFS register. 2. Setting the LVD0ON bit is only valid after a hardw are reset. To use the pow er-on reset, set the LVD0ON bit to 0 (voltage monitor 0 reset enabled after hardw are reset). 3. If the block including the OFS register is erased, FFh is set to the OFS register. Figure 15.2 OFS Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 135 of 318 R8C/2G Group 15. Option Function Select Area 15.3 15.3.1 Notes on Option Function Select Area Setting Example of Option Function Select Area As the option function select area is allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing an instruction. Write appropriate values when creating a program. The following shows a setting example. • To set FFh in the OFS register .org 00FFFCH .lword reset | (0FF000000h) ; RESET (Programming formats vary depending on the compiler. Check the compiler manual.) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 136 of 318 R8C/2G Group 16. Watchdog Timer 16. Watchdog Timer The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is recommended to improve the reliability of the system. The watchdog timer contains a 15-bit counter and allows selection of count source protection mode enable or disable. Table 16.1 lists information on the Watchdog Timer Specifications. Refer to 5.6 Watchdog Timer Reset for details on the watchdog timer. Figure 16.1 shows the Block Diagram of Watchdog Timer. Figure 16.2 shows the Registers WDTR, WDTS, and WDC. Figure 16.3 shows the Registers CSPR and OFS. Table 16.1 Item Count source CPU clock Watchdog Timer Specifications Count Source Protection Mode Disabled XCIN clock divided by 32 (fC32) Count Source Protection Mode Enabled Low-speed on-chip oscillator clock Count operation Decrement Count start condition Either of the following can be selected • After reset, count starts automatically • Count starts by writing to WDTS register Count stop condition Stop mode, wait mode Stop mode None Reset condition of • Reset • Write 00h to the WDTR register before writing FFh watchdog timer • Underflow Operation at the time Watchdog timer interrupt or watchdog timer reset Watchdog timer reset of underflow Select functions • Division ratio of prescaler (when select the CPU clock as the count source) Selected by the WDC7 bit in the WDC register • The default value of the watchdog timer (when select fC32 as the count source) Selected by bits CVS0 to CVS1 in the CSPR register • Count source protection mode Whether count source protection mode is enabled or disabled after a reset can be selected by the CSPROINI bit in the OFS register (flash memory). If count source protection mode is disabled after a reset, it can be enabled or disabled by the CSPRO bit in the CSPR register (program). • Starts or stops of the watchdog timer after a reset Selected by the WDTON bit in the OFS register (flash memory). Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 137 of 318 R8C/2G Group 16. Watchdog Timer Prescaler 1/16 CPU clock 1/128 WDC7 = 0 CSS = 0 CSPRO = 0 WDC7 = 1 PM12 = 0 Watchdog timer interrupt request fC32 fOCO-S Write to WDTR register Internal reset signal CSS = 1 Watchdog timer PM12 = 1 Watchdog timer reset CSPRO = 1 Set to default value(1) NOTE: 1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set. When the CSPRO bit is set to 0 (count source protection mode disabled), the initial value depends on the settings of bits CVS0, CVS1, and CSS in the CSPR register. CSS, CSPRO: Bits in CSPR register WDC7: Bit in WDC register PM12: Bit in PM1 register Figure 16.1 Block Diagram of Watchdog Timer Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 138 of 318 R8C/2G Group 16. Watchdog Timer Watchdog Timer Reset Register b7 b0 Address After Reset 000Dh Undefined Function When 00h is w ritten before w riting FFh, the w atchdog timer is reset.(1) The w atchdog timer initial value depends on the CSPR register setting. CSPRO 0 0 0 0 0 1(2) X: 0 or 1 CSPR register CSS CVS1 0 X 1 0 1 0 1 1 1 1 X X CVS0 X 0 1 0 1 X Default value 7FFFh 01FFh 03FFh 07FFh 0FFFh 0FFFh Symbol WDTR RW WO NOTES: 1. Do not generate an interrupt betw een w hen 00h and FFh are w ritten. 2. When the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled), 0FFFh is set in the w atchdog timer. Watchdog Timer Start Register b7 b0 Symbol WDTS Address 000Eh After Reset Undefined RW WO Function The w atchdog timer starts counting after a w rite instruction to this register. Watchdog Timer Control Register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol Address 000Fh WDC Bit Symbol Bit Name — High-order bits of w atchdog timer (b4-b0) — (b5) — (b6) WDC7 Reserved bit Reserved bit Prescaler select bit After Reset 00X11111b Function RW RO RW RW RW Set to 0. When read, the content is undefined. Set to 0. 0 : Divide-by-16 1 : Divide-by-128 Figure 16.2 Registers WDTR, WDTS, and WDC Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 139 of 318 R8C/2G Group 16. Watchdog Timer Count Source Protection Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol CSPR Bit Symbol CVS0 Address 001Ch Bit Name Watchdog timer default value select bit(2) After Reset(1) 00h Function b1 b0 RW RW CVS1 Count source select bit(3) 0 0 : 01FFh (512) 0 1 : 03FFh (1024) 1 0 : 07FFh (2048) 1 1 : 0FFFh (4096) 0 : CPU clock 1 : fC32 RW CSS — (b6-b3) CSPRO RW — RW Nothing is assigned. If necessary, set to 0. When read, the content is 0. Count source protection mode 0 : Count source protection mode disabled select bit(4) 1 : Count source protection mode enabled NOTES: 1. When 0 is w ritten to the CSPROINI bit in the OFS register, the value after reset is 10000000b. 2. When the CSS bit is set to 1 (fC32), Bits CVS0 to CVS1 are enabled. 3. When the CSPRO bit is set to 0 (count source protection mode disabled), the CSS bit is enabled. 4. Write 0 before w riting 1 to set the CSPRO bit to 1. 0 cannot be set by a program. Option Function Select Register(1) b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 Symbol OFS Bit Symbol WDTON — (b1) ROMCR ROMCP1 — (b4) Address 0FFFFh Bit Name Watchdog timer start select bit Reserved bit ROM code protect disabled bit ROM code protect bit Reserved bit Voltage detection 0 circuit start bit(2) When Shipping FFh(3) Function 0 : Starts w atchdog timer automatically after reset 1 : Watchdog timer is inactive after reset Set to 1. 0 : ROM code protect disabled 1 : ROMCP1 enabled 0 : ROM code protect enabled 1 : ROM code protect disabled Set to 1. 0 : Voltage monitor 0 reset enabled after hardw are reset 1 : Voltage monitor 0 reset disabled after hardw are reset Set to 1. 0 : Count source protect mode enabled after reset 1 : Count source protect mode disabled after reset RW RW RW RW RW RW LVD0ON RW — (b6) Reserved bit RW Count source protect CSPROINI mode after reset select bit RW NOTES: 1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not w rite additions to the OFS register. 2. Setting the LVD0ON bit is only valid after a hardw are reset. To use the pow er-on reset, set the LVD0ON bit to 0 (voltage monitor 0 reset enabled after hardw are reset). 3. If the block including the OFS register is erased, FFh is set to the OFS register. Figure 16.3 Registers CSPR and OFS Page 140 of 318 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 R8C/2G Group 16. Watchdog Timer 16.1 Count Source Protection Mode Disabled The count source of the watchdog timer is either the CPU clock or the XCIN clock divided by 32 (fC32) can be selected when count source protection mode is disabled. fC32 does not stop in wait mode, the watchdog timer to count continues. Table 16.2 lists the Watchdog Timer Specifications (with Count Source Protection Mode Disabled). Table 16.2 Watchdog Timer Specifications (with Count Source Protection Mode Disabled) Specification XCIN clock divided by 32 (fC32) 32 ---------------------------- × count value of watchdog timer (m)(1) XCIN clock Item Count source CPU clock Count operation Decrement Period Division ratio of prescaler (n) count value of watchdog --------------------------------------------------------------------------- × timer (32768)(1, 2) CPU clock n: 16 or 128 (selected by WDC7 bit in WDC m: 512, 1024, 2048 or 4096 (selected by bits register) CVS0 to CVS1 in the CSPR register) Example: When the CPU clock frequency is 8 MHz Example: When the XCIN clock frequency is and prescaler divided by 16, the period is 32.768 kHz and the count value by approximately 65.5 ms 512, the period is 0.5 s Reset condition • Reset of watchdog • Write 00h to the WDTR register before writing FFh timer • Underflow Count start The WDTON bit(3) in the OFS register (0FFFFh) selects the operation of the watchdog timer after a condition reset • When the WDTON bit is set to 1 (watchdog timer is in stop state after reset) The watchdog timer and prescaler stop after a reset and the count starts when the WDTS register is written to • When the WDTON bit is set to 0 (watchdog timer starts automatically after exiting) The watchdog timer and prescaler start counting automatically after a reset Count stop Stop and wait modes (inherit the count from the Stop mode (inherit the count from the held condition held value after exiting modes) value after exiting modes) Operation at • When the PM12 bit in the PM1 register is set to 0 time of Watchdog timer interrupt underflow • When the PM12 bit in the PM1 register is set to 1 Watchdog timer reset (refer to 5.6 Watchdog Timer Reset) NOTES: 1. The watchdog timer is reset when 00h is written to the WDTR register before FFh. 2. The prescaler is reset after the MCU is reset. Some errors in the period of the watchdog timer may be caused by the prescaler. 3. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address 0FFFFh with a flash programmer. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 141 of 318 R8C/2G Group 16. Watchdog Timer 16.2 Count Source Protection Mode Enabled The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection mode is enabled. If the CPU clock stops when a program is out of control, the clock can still be supplied to the watchdog timer. Table 16.3 lists the Watchdog Timer Specifications (with Count Source Protection Mode Enabled). Table 16.3 Watchdog Timer Specifications (with Count Source Protection Mode Enabled) Item Count source Count operation Period Specification Low-speed on-chip oscillator clock Decrement Count value of watchdog timer (4096) Low-speed on-chip oscillator clock Example: Period is approximately 32.8 ms when the low-speed onchip oscillator clock frequency is 125 kHz • Reset • Write 00h to the WDTR register before writing FFh • Underflow The WDTON bit(1) in the OFS register (0FFFFh) selects the operation of the watchdog timer after a reset. • When the WDTON bit is set to 1 (watchdog timer is in stop state after reset) The watchdog timer and prescaler stop after a reset and the count starts when the WDTS register is written to • When the WDTON bit is set to 0 (watchdog timer starts automatically after reset) The watchdog timer and prescaler start counting automatically after a reset None (The count does not stop in wait mode after the count starts. The MCU does not enter stop mode.) Watchdog timer reset (refer to 5.6 Watchdog Timer Reset) • When setting the CSPPRO bit in the CSPR register to 1 (count source protection mode is enabled)(2), the following are set automatically - Set 0FFFh to the watchdog timer - Set the CM14 bit in the CM1 register to 0 (low-speed on-chip oscillator on) - Set the PM12 bit in the PM1 register to 1 (The watchdog timer is reset when watchdog timer underflows) • The following conditions apply in count source protection mode - Writing to the CM10 bit in the CM1 register is disabled (It remains unchanged even if it is set to 1. The MCU does not enter stop mode.) - Writing to the CM14 bit in the CM1 register is disabled (It remains unchanged even if it is set to 1. The low-speed on-chip oscillator does not stop.) Reset condition of watchdog timer Count start condition Count stop condition Operation at time of underflow Registers, bits NOTES: 1. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address 0FFFFh with a flash programmer. 2. Even if 0 is written to the CSPROINI bit in the OFS register, the CSPRO bit is set to 1. The CSPROINI bit cannot be changed by a program. To set the CSPROINI bit, write 0 to bit 7 of address 0FFFFh with a flash programmer. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 142 of 318 R8C/2G Group 17. Timers 17. Timers The MCU has two 8-bit timers with 8-bit prescalers, one 16-bit timer, and a timer with a 4-bit counter and an 8-bit counter. The two 8-bit timers with 8-bit prescalers are timer RA and timer RB. These timers contain a reload register to store the default value of the counter. The one 16-bit timer is timer RF and have input capture and output compare functions. The 4-bit and 8-bit counters are timer RE, and has an output compare function. All the timers operate independently. Table 17.1 lists Functional Comparison of Timers. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 143 of 318 R8C/2G Group 17. Timers Table 17.1 Item Configuration Count Count sources Functional Comparison of Timers Timer RA 8-bit timer with 8-bit prescaler (with reload register) Decrement • f1 • f2 • f8 • fOCO • fC32 Timer mode Event counter mode Timer RB 8-bit timer with 8-bit prescaler (with reload register) Decrement • f1 • f2 • f8 • Timer RA underflow Timer mode — Timer RE 4-bit counter 8-bit counter Increment • f4 • f8 • f32 • fC4 — — — Timer RF 16-bit timer (with input capture and output compare) Increment • f1 • f8 • f32 Output compare mode — Input capture mode Function Count of the internal count source Count of the external count source External pulse width/ period measurement PWM output One-shot waveform output Timer Input pin Output pin Related interrupt Pulse width — measurement mode, pulse period measurement mode Pulse output mode(1), Programmable Event counter mode(1) waveform generation mode — Programmable oneshot generation mode, Programmable wait one-shot generation mode Timer mode (only fC32 — count) TRAIO INT0 TRAO TRBO TRAIO Timer RB interrupt, Timer RA interrupt, INT0 interrupt INT1 interrupt Provided Provided Output compare mode(1) — Output compare mode — Timer stop TRFI TRFO00 to TRFO02, TRFO10 to TRFO12 Timer RE interrupt Timer RF interrupt, Compare 0 interrupt, Compare 1 interrupt, Capture interrupt Provided Provided Real-time clock mode — TREO — NOTE: 1. Rectangular waves are output in these modes. Since the waves are inverted at each overflow, the “H” and “L” level widths of the pulses are the same. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 144 of 318 R8C/2G Group 17. Timers 17.1 Timer RA Timer RA is an 8-bit timer with an 8-bit prescaler. The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated at the same address, and can be accessed when accessing registers TRAPRE and TRA (refer to Tables 17.2 to 17.6 the Specifications of Each Mode). The count source for timer RA is the operating clock that regulates the timing of timer operations such as counting and reloading. Figure 17.1 shows a Block Diagram of Timer RA. Figures 17.2 and 17.3 show the registers associated with timer RA. Timer RA has the following five operating modes: • Timer mode: The timer counts the internal count source. • Pulse output mode: The timer counts the internal count source and outputs pulses of which polarity inverted by underflow of the timer. • Event counter mode: The timer counts external pulses. • Pulse width measurement mode: The timer measures the pulse width of an external pulse. • Pulse period measurement mode: The timer measures the pulse period of an external pulse. Data bus TCK2 to TCK0 f1 f8 fOCO f2 fC32 = 000b = 001b = 010b = 011b = 100b TCKCUT TMOD2 to TMOD0 = other than 010b Reload register TCSTF Counter TRAPRE register (prescaler) Reload register Underflow signal Timer RA interrupt TIPF1 to TIPF0 f1 = 10b f8 = 11b f32 = 01b TMOD2 to TMOD0 = 010b Counter TRA register (timer) TIPF1 to TIPF0 TIOSEL = 0 = other than 000b INT1/TRAIO (P1_7) pin TMOD2 to TMOD0 = 011b or 100b Digital filter Polarity switching Count control circle INT1/TRAIO (P1_5) pin TIOSEL = 1 = 00b Measurement completion signal TMOD2 to TMOD0 = 001b TEDGSEL = 1 TOPCR Q TOENA TRAO (P3_0) pin TRAO (P3_7) pin TRAOSEL = 0 Q TEDGSEL = 0 Toggle flip-flop CK CLR Write to TRAMR register Write 1 to TSTOP bit TCSTF, TSTOP: Bits in TRACR register TEDGSEL, TOPCR, TOENA, TIOSEL, TIPF1, TIPF0: Bits in TRAIOC register TMOD2 to TMOD0, TCK2 to TCK0, TCKCUT: Bits in TRAMR register TRAOSEL: Bit in the PINSR2 register TRAOSEL = 1 Figure 17.1 Block Diagram of Timer RA Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 145 of 318 R8C/2G Group 17. Timers Timer RA Control Register(4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRACR Bit Symbol TSTART TCSTF TSTOP — (b3) TEDGF Address 0100h Bit Name Timer RA count start bit(1) Timer RA count status flag(1) Timer RA count forcible stop bit(2) After Reset 00h Function 0 : Count stops 1 : Count starts 0 : Count stops 1 : During count When this bit is set to 1, the count is forcibly stopped. When read, its content is 0. RW RW RO RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. Active edge judgment flag(3, 5) Timer RA underflow flag(3, 5) 0 : Active edge not received 1 : Active edge received (end of measurement period) 0 : No underflow 1 : Underflow RW TUNDF — (b7-b6) RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. NOTES: 1. Refer to 17.1.6 Notes on Tim er RA. 2. When the TSTOP bit is set to 1, bits TSTART and TCSTF and registers TRAPRE and TRA are set to the values after a reset. 3. Bits TEDGF and TUNDF can be set to 0 by w riting 0 to these bits by a program. How ever, their value remains unchanged w hen 1 is w ritten. 4. In pulse w idth measurement mode and pulse period measurement mode, use the MOV instruction to set the TRACR register. If it is necessary to avoid changing the values of bits TEDGF and TUNDF, w rite 1 to them. 5. Set to 0 in timer mode, pulse output mode, and event counter mode. Timer RA I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 — (b7-b6) Address 0101h Bit Name TRAIO polarity sw itch bit TRAIO output control bit TRAO output enable bit _____ After Reset 00h Function Function varies depending on operating mode. RW RW RW RW RW RW — INT1/TRAIO select bit TRAIO input filter select bits Nothing is assigned. If necessary, set to 0. When read, the content is 0. Figure 17.2 Registers TRACR and TRAIOC Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 146 of 318 R8C/2G Group 17. Timers Timer RA Mode Register(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRAMR Bit Symbol TMOD0 Address 0102h Bit Name Timer RA operating mode select bits After Reset 00h Function b2 b1 b0 RW RW TMOD1 TMOD2 — (b3) TCK0 0 0 0 : Timer mode 0 0 1 : Pulse output mode 0 1 0 : Event counter mode 0 1 1 : Pulse w idth measurement mode 1 0 0 : Pulse period measurement mode 101: 1 1 0 : Do not set. 111: RW RW Nothing is assigned. If necessary, set to 0. When read, the content is 0. Timer RA count source select bits b6 b5 b4 — TCK1 TCK2 Timer RA count source cutoff bit 0 0 0 : f1 0 0 1 : f8 0 1 0 : fOCO 0 1 1 : f2 1 0 0 : fC32 101: 1 1 0 : Do not set. 111: 0 : Provides count source 1 : Cuts off count source RW RW RW TCKCUT RW NOTE: 1. When both the TSTART and TCSTF bits in the TRACR register are set to 0 (count stops), rew rite this register. Timer RA Prescaler Register b7 b0 Symbol TRAPRE Mode Timer mode Pulse output mode Event counter mode Pulse w idth measurement mode Pulse period measurement mode Counts Counts Counts Counts Address 0103h Function an internal count source an internal count source an external count source internal count source After Reset FFh(1) Setting Range 00h to FFh 00h to FFh 00h to FFh 00h to FFh 00h to FFh RW RW RW RW RW RW NOTE: 1. When the TSTOP bit in the TRACR register is set to 1, the TRAPRE register is set to FFh. Timer RA Register b7 b0 Symbol TRA Mode All modes Address 0104h Function Counts on underflow of timer RA prescaler register After Reset FFh(1) Setting Range 00h to FFh RW RW NOTE: 1. When the TSTOP bit in the TRACR register is set to 1, the TRA register is set to FFh. Figure 17.3 Registers TRAMR, TRAPRE, and TRA Page 147 of 318 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 R8C/2G Group 17. Timers 17.1.1 Timer Mode In this mode, the timer counts an internally generated count source (refer to Table 17.2 Timer Mode Specifications). Figure 17.4 shows TRAIOC Register in Timer Mode. Table 17.2 Timer Mode Specifications Specification f1, f2, f8, fOCO, fC32 • Decrement • When the timer underflows, the contents of the reload register are reloaded and the count is continued. 1/(n+1)(m+1) n: Value set in TRAPRE register, m: Value set in TRA register 1 (count starts) is written to the TSTART bit in the TRACR register. • 0 (count stops) is written to the TSTART bit in the TRACR register. • 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. When timer RA underflows [timer RA interrupt]. Programmable I/O port, or INT1 interrupt input Programmable I/O port The count value can be read by reading registers TRA and TRAPRE. • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter. • When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 17.1.1.1 Timer Write Control during Count Operation). Item Count sources Count operations Divide ratio Count start condition Count stop conditions Interrupt request generation timing INT1/TRAIO pin function TRAO pin function Read from timer Write to timer Timer RA I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 00 000 Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 — (b7-b6) Address 0101h Bit Name TRAIO polarity sw itch bit TRAIO output control bit TRAO output enable bit INT1/TRAIO select bit _____ After Reset 00h Function Set to 0 in timer mode. RW RW RW RW 0 : INT1/TRAIO pin (P1_7) _____ 1 : INT1/TRAIO pin (P1_5) TRAIO input filter select bits Set to 0 in timer mode. Nothing is assigned. If necessary, set to 0. When read, the content is 0. _____ RW RW — Figure 17.4 TRAIOC Register in Timer Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 148 of 318 R8C/2G Group 17. Timers 17.1.1.1 Timer Write Control during Count Operation Timer RA has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each consist of a reload register and a counter. When writing to the prescaler or timer, values are written to both the reload register and counter. However, values are transferred from the reload register to the counter of the prescaler in synchronization with the count source. In addition, values are transferred from the reload register to the counter of the timer in synchronization with prescaler underflows. Therefore, if the prescaler or timer is written to when count operation is in progress, the counter value is not updated immediately after the WRITE instruction is executed. Figure 17.5 shows an Operating Example of Timer RA when Counter Value is Rewritten during Count Operation. Set 01h to the TRAPRE register and 25h to the TRA register by a program. Count source After writing, the reload register is written to at the first count source. Reloads register of timer RA prescaler Previous value Reload at second count source Counter of timer RA prescaler 06h 05h 04h 01h 00h New value (01h) Reload at underflow 01h 00h 01h 00h 01h 00h After writing, the reload register is written to at the first underflow. Reloads register of timer RA Previous value New value (25h) Reload at the second underflow Counter of timer RA 03h 02h 25h 24h IR bit in TRAIC register 0 The IR bit remains unchanged until underflow is generated by a new value. The above applies under the following conditions. Both bits TSTART and TCSTF in the TRACR register are set to 1 (During count). Figure 17.5 Operating Example of Timer RA when Counter Value is Rewritten during Count Operation Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 149 of 318 R8C/2G Group 17. Timers 17.1.2 Pulse Output Mode In pulse output mode, the internally generated count source is counted, and a pulse with inverted polarity is output from the TRAIO pin each time the timer underflows (refer to Table 17.3 Pulse Output Mode Specifications). Figure 17.6 shows TRAIOC Register in Pulse Output Mode. Table 17.3 Pulse Output Mode Specifications Specification f1, f2, f8, fOCO, fC32 • Decrement • When the timer underflows, the contents in the reload register is reloaded and the count is continued. Divide ratio 1/(n+1)(m+1) n: Value set in TRAPRE register, m: Value set in TRA register Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register. Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register. • 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. Interrupt request When timer RA underflows [timer RA interrupt]. generation timing INT1/TRAIO pin Pulse output, programmable output port, or INT1 interrupt(1) function Programmable I/O port or inverted output of TRAIO(1) TRAO pin function The count value can be read by reading registers TRA and TRAPRE. Read from timer Write to timer • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter. • When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 17.1.1.1 Timer Write Control during Count Operation). Select functions • TRAIO output polarity switch function The TEDGSEL bit in the TRAIOC register selects the level at the start of pulse output.(1) • TRAO output function Pulses inverted from the TRAIO output polarity can be output from the TRAO pin (selectable by the TOENA bit in the TRAIOC register). • TRAO pin select function P3_0 or P3_7 is selected by the TRAOSEL bit in the PINSR2 register. • Pulse output stop function Output from the TRAIO pin is stopped by the TOPCR bit in the TRAIOC register. • INT1/TRAIO pin select function P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register. NOTE: 1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR register is written to. Item Count sources Count operations Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 150 of 318 R8C/2G Group 17. Timers Timer RA I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol TRAIOC Bit Symbol TEDGSEL TOPCR Address 0101h Bit Name TRAIO polarity sw itch bit TRAIO output control bit TRAO output enable bit After Reset 00h Function 0 : TRAIO output starts at “H” 1 : TRAIO output starts at “L” 0 : TRAIO output 1 : Port P1_7 or P1_5 0 : Port P3_0 (P3_7) 1 : TRAO output (inverted TRAIO output from P3_0 (P3_7)) _____ RW RW RW TOENA INT1/TRAIO select bit _____ RW TIOSEL TIPF0 TIPF1 — (b7-b6) 0 : INT1/TRAIO pin (P1_7) _____ 1 : INT1/TRAIO pin (P1_5) TRAIO input filter select bits Set to 0 in pulse output mode. Nothing is assigned. If necessary, set to 0. When read, the content is 0. RW RW RW — Figure 17.6 TRAIOC Register in Pulse Output Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 151 of 318 R8C/2G Group 17. Timers 17.1.3 Event Counter Mode In event counter mode, external signal inputs to the INT1/TRAIO pin are counted (refer to Table 17.4 Event Counter Mode Specifications). Figure 17.7 shows TRAIOC Register in Event Counter Mode. Table 17.4 Event Counter Mode Specifications Specification External signal which is input to TRAIO pin (active edge selectable by a program) • Decrement • When the timer underflows, the contents of the reload register are reloaded and the count is continued. Divide ratio 1/(n+1)(m+1) n: setting value of TRAPRE register, m: setting value of TRA register Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register. Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register. • 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. Interrupt request • When timer RA underflows [timer RA interrupt]. generation timing INT1/TRAIO pin Count source input (INT1 interrupt input) function Programmable I/O port or pulse output(1) TRAO pin function Read from timer The count value can be read by reading registers TRA and TRAPRE. Write to timer • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter. • When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 17.1.1.1 Timer Write Control during Count Operation). Select functions • NT1 input polarity switch function The TEDGSEL bit in the TRAIOC register selects the active edge of the count source. • Count source input pin select function P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register. • Pulse output function Pulses of inverted polarity can be output from the TRAO pin each time the timer underflows (selectable by the TOENA bit in the TRAIOC register).(1) • TRAO pin select function P3_0 or P3_7 is selected by the TRAOSEL bit in the PINSR2 register. • Digital filter function Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital filter and select the sampling frequency. NOTE: 1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR register is written to. Item Count source Count operations Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 152 of 318 R8C/2G Group 17. Timers Timer RA I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol TRAIOC Bit Symbol TEDGSEL Address 0101h Bit Name TRAIO polarity sw itch bit After Reset 00h Function 0 : Starts counting at rising edge of the TRAIO input or TRAIO starts output at “L” 1 : Starts counting at falling edge of the TRAIO input or TRAIO starts output at “H” Set to 0 in event counter mode. 0 : Port P3_0 (P3_7) 1 : TRAO output 0 : INT1/TRAIO pin (P1_7) _____ 1 : INT1/TRAIO pin (P1_5) b5 b4 _____ RW RW TOPCR TOENA TIOSEL TRAIO output control bit TRAO output enable bit _____ RW RW RW INT1/TRAIO select bit TIPF0 TRAIO input filter select bits (1) TIPF1 — (b7-b6) 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling RW Nothing is assigned. If necessary, set to 0. When read, the content is 0. — NOTE: 1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined. Figure 17.7 TRAIOC Register in Event Counter Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 153 of 318 R8C/2G Group 17. Timers 17.1.4 Pulse Width Measurement Mode In pulse width measurement mode, the pulse width of an external signal input to the INT1/TRAIO pin is measured (refer to Table 17.5 Pulse Width Measurement Mode Specifications). Figure 17.8 shows TRAIOC Register in Pulse Width Measurement Mode and Figure 17.9 shows an Operating Example of Pulse Width Measurement Mode. Table 17.5 Pulse Width Measurement Mode Specifications Item Count sources Count operations Specification f1, f2, f8, fOCO, fC32 • Decrement • Continuously counts the selected signal only when measurement pulse is “H” level, or conversely only “L” level. • When the timer underflows, the contents of the reload register are reloaded and the count is continued. Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register. Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register. • 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. Interrupt request • When timer RA underflows [timer RA interrupt]. • Rising or falling of the TRAIO input (end of measurement period) [timer RA generation timing interrupt] INT1/TRAIO pin function Measured pulse input (INT1 interrupt input) Programmable I/O port TRAO pin function Read from timer The count value can be read by reading registers TRA and TRAPRE. Write to timer • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter. • When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 17.1.1.1 Timer Write Control during Count Operation). Select functions • Measurement level select • The TEDGSEL bit in the TRAIOC register selects the “H” or “L” level period. • Measured pulse input pin select function P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register. • Digital filter function Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital filter and select the sampling frequency. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 154 of 318 R8C/2G Group 17. Timers Timer RA I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL Address 0101h Bit Name TRAIO polarity sw itch bit TRAIO output control bit TRAO output enable bit _____ After Reset 00h Function 0 : TRAIO input starts at “L” 1 : TRAIO input starts at “H” Set to 0 in pulse w idth measurement mode. RW RW RW RW INT1/TRAIO select bit TRAIO input filter select bits (1) 0 : INT1/TRAIO pin (P1_7) _____ 1 : INT1/TRAIO pin (P1_5) b5 b4 _____ RW TIPF0 TIPF1 — (b7-b6) 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling RW Nothing is assigned. If necessary, set to 0. When read, the content is 0. — NOTE: 1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined. Figure 17.8 TRAIOC Register in Pulse Width Measurement Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 155 of 318 R8C/2G Group 17. Timers n = high level: the contents of TRA register, low level: the contents of TRAPRE register FFFFh n Content of counter (hex) Count start Underflow Count stop Count stop 0000h Set to 1 by program TSTART bit in TRACR register 1 0 Count start Count start Period Measured pulse (TRAIO pin input) 1 0 Set to 0 when interrupt request is acknowledged, or set by program IR bit in TRAIC register 1 0 Set to 0 by program TEDGF bit in TRACR register 1 0 Set to 0 by program TUNDF bit in TRACR register 1 0 The above applies under the following conditions. • “H” level width of measured pulse is measured. (TEDGSEL = 1) • TRAPRE = FFh Figure 17.9 Operating Example of Pulse Width Measurement Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 156 of 318 R8C/2G Group 17. Timers 17.1.5 Pulse Period Measurement Mode In pulse period measurement mode, the pulse period of an external signal input to the INT1 /TRAIO pin is measured (refer to Table 17.6 Pulse Period Measurement Mode Specifications). Figure 17.10 shows TRAIOC Register in Pulse Period Measurement Mode and Figure 17.11 shows an Operating Example of Pulse Period Measurement Mode. Table 17.6 Pulse Period Measurement Mode Specifications Specification f1, f2, f8, fOCO, fC32 • Decrement • After the active edge of the measured pulse is input, the contents of the readout buffer are retained at the first underflow of timer RA prescaler. Then timer RA reloads the contents in the reload register at the second underflow of timer RA prescaler and continues counting. Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register. Count stop conditions • 0 (count stops) is written to TSTART bit in the TRACR register. • 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. Interrupt request • When timer RA underflows or reloads [timer RA interrupt]. • Rising or falling of the TRAIO input (end of measurement period) [timer RA generation timing interrupt] INT1/TRAIO pin function Measured pulse input(1) (INT1 interrupt input) Programmable I/O port TRAO pin function Read from timer The count value can be read by reading registers TRA and TRAPRE. Write to timer • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter. • When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 17.1.1.1 Timer Write Control during Count Operation). Select functions • Measurement period select The TEDGSEL bit in the TRAIOC register selects the measurement period of the input pulse. • Measured pulse input pin select function P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register. • Digital filter function Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital filter and select the sampling frequency. NOTE: 1. Input a pulse with a period longer than twice the timer RA prescaler period. Input a pulse with a longer “H” and “L” width than the timer RA prescaler period. If a pulse with a shorter period is input to the TRAIO pin, the input may be ignored. Item Count sources Count operations Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 157 of 318 R8C/2G Group 17. Timers Timer RA I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol TRAIOC Bit Symbol TEDGSEL Address 0101h Bit Name TRAIO polarity sw itch bit After Reset 00h Function 0 : Measures measurement pulse from one rising edge to next rising edge 1 : Measures measurement pulse from one falling edge to next falling edge Set to 0 in pulse period measurement mode. RW RW TOPCR TOENA TIOSEL TRAIO output control bit TRAO output enable bit _____ RW RW INT1/TRAIO select bit 0 : INT1/TRAIO pin (P1_7) _____ 1 : INT1/TRAIO pin (P1_5) b5 b4 _____ RW TIPF0 TRAIO input filter select bits (1) TIPF1 — (b7-b6) 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling RW Nothing is assigned. If necessary, set to 0. When read, the content is 0. — NOTE: 1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined. Figure 17.10 TRAIOC Register in Pulse Period Measurement Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 158 of 318 R8C/2G Group 17. Timers Underflow signal of timer RA prescaler Set to 1 by program TSTART bit in TRACR register 1 0 Starts counting Measurement pulse (TRAIO pin input) 1 0 TRA reloads TRA reloads Contents of TRA 0Fh 0Eh 0Dh 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 0Fh 0Eh 0Dh 01h 00h 0Fh 0Eh Underflow Retained Retained Contents of read-out buffer(1) 0Fh 0Eh 0Dh TRA read(3) 0Bh 0Ah 09h 0Dh 01h 00h 0Fh 0Eh TEDGF bit in TRACR register 1 0 (Note 2) (Note 2) Set to 0 by program (Note 4) (Note 6) TUNDF bit in TRACR register 1 0 Set to 0 by program (Note 5) IR bit in TRAIC register 1 0 Set to 0 when interrupt request is acknowledged, or set by program Conditions: The period from one rising edge to the next rising edge of the measured pulse is measured (TEDGSEL = 0) with the default value of the TRA register as 0Fh. NOTES: 1. The contents of the read-out buffer can be read by reading the TRA register in pulse period measurement mode. 2. After an active edge of the measured pulse is input, the TEDGF bit in the TRACR register is set to 1 (active edge found) when the timer RA prescaler underflows for the second time. 3. The TRA register should be read before the next active edge is input after the TEDGF bit is set to 1 (active edge found). The contents in the read-out buffer are retained until the TRA register is read. If the TRA register is not read before the next active edge is input, the measured result of the previous period is retained. 4. To set to 0 by a program, use a MOV instruction to write 0 to the TEDGF bit in the TRACR register. At the same time, write 1 to the TUNDF bit in the TRACR register. 5. To set to 0 by a program, use a MOV instruction to write 0 to the TUNDF bit. At the same time, write 1 to the TEDGF bit. 6. Bits TUNDF and TEDGF are both set to 1 if timer RA underflows and reloads on an active edge simultaneously. Figure 17.11 Operating Example of Pulse Period Measurement Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 159 of 318 R8C/2G Group 17. Timers 17.1.6 Notes on Timer RA • Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the count starts. • Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by the MCU. Consequently, the timer value may be updated during the period when these two registers are being read. • In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by writing 0 to these bits by a program. However, these bits remain unchanged if 1 is written. When using the READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0 although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or TUNDF bit which is not supposed to be set to 0 with the MOV instruction. • When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts. • The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts. • When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler immediately after the count starts, then set the TEDGF bit to 0. • The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1 (count starts) while the count is stopped. During this time, do not access registers associated with timer RA(1) other than the TCSTF bit. Timer RA starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count). The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RA(1) other than the TCSTF bit. NOTE: 1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA. • When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the count source clock for each write interval. • When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 160 of 318 R8C/2G Group 17. Timers 17.2 Timer RB Timer RB is an 8-bit timer with an 8-bit prescaler. The prescaler and timer each consist of a reload register and counter (refer to Tables 1 7.7 to 17.10 the Specifications of Each Mode). Timer RB has timer RB primary and timer RB secondary as reload registers. The count source for timer RB is the operating clock that regulates the timing of timer operations such as counting and reloading. Figure 17.12 shows a Block Diagram of Timer RB. Figures 17.13 to 17.15 show the registers associated with timer RB. Timer RB has four operation modes listed as follows: • Timer mode: • Programmable waveform generation mode: • Programmable one-shot generation mode: • Programmable wait one-shot generation mode: The timer counts an internal count source (peripheral function clock or timer RA underflows). The timer outputs pulses of a given width successively. The timer outputs a one-shot pulse. The timer outputs a delayed one-shot pulse. TCK1 to TCK0 f1 f8 Timer RA underflow = 00b = 01b = 10b = 11b Reload register TCKCUT Counter TRBPRE register (prescaler) TSTART Data bus TRBSC register Reload register TRBPR register Reload register Timer RB interrupt Counter (timer RB) (Timer) TMOD1 to TMOD0 = 10b or 11b TOSSTF f2 INT0 interrupt INT0 pin Digital filter Input polarity selected to be one edge or both edges Polarity select INOSEG TOPL = 1 Q Q INT0PL TMOD1 to TMOD0 = 01b, 10b, 11b TRBO (P3_1) pin TRBO (P1_3) pin TRBOSEL = 0 INOSTG INT0EN TOCNT = 0 P3_1 bit in P3 register TOCNT = 1 TOPL = 0 Toggle flip-flop CLR CK TRBOSEL = 1 TSTART, TCSTF: Bits in TRBCR register TOSSTF: Bit in TRBOCR register TOPL, TOCNT, INOSTG, INOSEG: Bits in TRBIOC register TMOD1 to TMOD0, TCK1 to TCK0, TCKCUT: Bits in TRBMR register TRBOSEL: Bit in PINSR2 register TCSTF TMOD1 to TMOD0 = 01b, 10b, 11b Figure 17.12 Block Diagram of Timer RB Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 161 of 318 R8C/2G Group 17. Timers Timer RB Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRBCR Bit Symbol TSTART TCSTF TSTOP — (b7-b3) Address 0108h Bit Name Timer RB count start bit(1) After Reset 00h Function 0 : Count stops 1 : Count starts RW RW RO RW — Timer RB count status flag(1) 0 : Count stops 1 : During count(3) Timer RB count forcible stop When this bit is set to 1, the count is forcibly bit(1, 2) stopped. When read, its content is 0. Nothing is assigned. If necessary, set to 0. When read, the content is 0. NOTES: 1. Refer to 17.2.5 Notes on Tim er RB f or precautions regarding bits TSTART, TCSTF and TSTOP. 2. When the TSTOP bit is set to 1, registers TRBPRE, TRBSC, TRBPR, and bits TSTART and TCSTF, and the TOSSTF bit in the TRBOCR register are set to values after a reset. 3. Indicates that count operation is in progress in timer mode or programmable w aveform mode. In programmable oneshot generation mode or programmable w ait one-shot generation mode, indicates that a one-shot pulse trigger has been acknow ledged. Timer RB One-Shot Control Register(2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRBOCR Bit Symbol TOSST Address 0109h Bit Name Timer RB one-shot start bit Timer RB one-shot stop bit After Reset 00h Function When this bit is set to 1, one-shot trigger generated. When read, its content is 0. When this bit is set to 1, counting of one-shot pulses (including programmable w ait one-shot pulses) stops. When read, its content is 0. 0 : One-shot stopped 1 : One-shot operating (Including w ait period) RW RW TOSSP Timer RB one-shot status flag(1) RW TOSSTF — (b7-b3) RO — Nothing is assigned. If necessary, set to 0. When read, the content is 0. NOTES: 1. When 1 is set to the TSTOP bit in the TRBCR register, the TOSSTF bit is set to 0. 2. This register is enabled w hen bits TMOD1 to TMOD0 in the TRBMR register is set to 10b (programmable one-shot generation mode) or 11b (programmable w ait one-shot generation mode). Figure 17.13 Registers TRBCR and TRBOCR Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 162 of 318 R8C/2G Group 17. Timers Timer RB I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRBIOC Bit Symbol TOPL TOCNT INOSTG INOSEG — (b7-b4) Address After Reset 010Ah 00h Bit Name Function Timer RB output level select Function varies depending on operating mode. bit Timer RB output sw itch bit One-shot trigger control bit One-shot trigger polarity select bit Nothing is assigned. If necessary, set to 0. When read, the content is 0. RW RW RW RW RW — Timer RB Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRBMR Bit Symbol TMOD0 Address 010Bh Bit Name Timer RB operating mode select bits (1) After Reset 00h Function b1 b0 RW RW TMOD1 — (b2) TWRC 0 0 : Timer mode 0 1 : Programmable w aveform generation mode 1 0 : Programmable one-shot generation mode 1 1 : Programmable w ait one-shot generation mode RW Nothing is assigned. If necessary, set to 0. When read, the content is 0. Timer RB w rite control bit(2) Timer RB count source select bits (1) 0 : Write to reload register and counter 1 : Write to reload register only b5 b4 — RW TCK0 TCK1 — (b6) TCKCUT 0 0 : f1 0 1 : f8 1 0 : Timer RA underflow 1 1 : f2 RW RW Nothing is assigned. If necessary, set to 0. When read, the content is 0. Timer RB count source cutoff bit(1) 0 : Provides count source 1 : Cuts off count source — RW NOTES: 1. Change bits TMOD1 and TMOD0; TCK1 and TCK0; and TCKCUT w hen both the TSTART and TCSTF bits in the TRBCR register set to 0 (count stops). 2. The TWRC bit can be set to either 0 or 1 in timer mode. In programmable w aveform generation mode, programmable one-shot generation mode, or programmable w ait one-shot generation mode, the TWRC bit must be set to 1 (w rite to reload register only). Figure 17.14 Registers TRBIOC and TRBMR Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 163 of 318 R8C/2G Group 17. Timers Timer RB Prescaler Register(1) b7 b0 Symbol TRBPRE Mode Timer mode Programmable w aveform generation mode Programmable one-shot generation mode Programmable w ait one-shot generation mode Address 010Ch Function Counts an internal count source or timer RA underflow s After Reset FFh Setting Range 00h to FFh 00h to FFh 00h to FFh 00h to FFh RW RW RW RW RW NOTE: 1. When the TSTOP bit in the TRBCR register is set to 1, the TRBPRE register is set to FFh. Timer RB Secondary Register(3, 4) b7 b0 Symbol TRBSC Mode Timer mode Programmable w aveform generation mode Programmable one-shot generation mode Disabled Address 010Dh Function After Reset FFh Setting Range 00h to FFh 00h to FFh 00h to FFh 00h to FFh RW — WO(2) — WO(2) Counts timer RB prescaler underflow s (1) Disabled Programmable w ait one-shot Counts timer RB prescaler underflow s generation mode (one-shot w idth is counted) NOTES: 1. The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted. 2. The count value can be read out by reading the TRBPR register even w hen the secondary period is being counted. 3. When the TSTOP bit in the TRBCR register is set to 1, the TRBSC register is set to FFh. 4. To w rite to the TRBSC register, perform the follow ing steps. (1) Write the value to the TRBSC register. (2) Write the value to the TRBPR register. (If the value does not change, w rite the same value second time.) Timer RB Primary Register(2) b7 b0 Symbol TRBPR Mode Timer mode Programmable w aveform generation mode Programmable one-shot generation mode Address 010Eh Function Counts timer RB prescaler underflow s Counts timer RB prescaler underflow s (1) Counts timer RB prescaler underflow s (one-shot w idth is counted) After Reset FFh Setting Range 00h to FFh 00h to FFh 00h to FFh 00h to FFh RW RW RW RW RW Programmable w ait one-shot Counts timer RB prescaler underflow s generation mode (w ait period w idth is counted) NOTES: 1. The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted. 2. When the TSTOP bit in the TRBCR register is set to 1, the TRBPR register is set to FFh. Figure 17.15 Registers TRBPRE, TRBSC, and TRBPR Page 164 of 318 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 R8C/2G Group 17. Timers 17.2.1 Timer Mode In timer mode, a count source which is internally generated or timer RA underflows are counted (refer to Table 17.7 Timer Mode Specifications). Registers TRBOCR and TRBSC are not used in timer mode. Figure 17.16 shows TRBIOC Register in Timer Mode. Table 17.7 Timer Mode Specifications Specification f1, f2, f8, timer RA underflow • Decrement • When the timer underflows, it reloads the reload register contents before the count continues (when timer RB underflows, the contents of timer RB primary reload register is reloaded). 1/(n+1)(m+1) n: setting value in TRBPRE register, m: setting value in TRBPR register 1 (count starts) is written to the TSTART bit in the TRBCR register. • 0 (count stops) is written to the TSTART bit in the TRBCR register. • 1 (count forcibly stop) is written to the TSTOP bit in the TRBCR register. When timer RB underflows [timer RB interrupt]. Programmable I/O port Programmable I/O port or INT0 interrupt input The count value can be read out by reading registers TRBPR and TRBPRE. • When registers TRBPRE and TRBPR are written while the count is stopped, values are written to both the reload register and counter. • When registers TRBPRE and TRBPR are written to while count operation is in progress: If the TWRC bit in the TRBMR register is set to 0, the value is written to both the reload register and the counter. If the TWRC bit is set to 1, the value is written to the reload register only. (Refer to 17.2.1.1 Timer Write Control during Count Operation.) Item Count sources Count operations Divide ratio Count start condition Count stop conditions Interrupt request generation timing TRBO pin function INT0 pin function Read from timer Write to timer Timer RB I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 0000 Symbol TRBIOC Bit Symbol TOPL TOCNT INOSTG INOSEG — (b7-b4) Address After Reset 010Ah 00h Bit Name Function Timer RB output level select Set to 0 in timer mode. bit Timer RB output sw itch bit One-shot trigger control bit One-shot trigger polarity select bit Nothing is assigned. If necessary, set to 0. When read, the content is 0. RW RW RW RW RW — Figure 17.16 TRBIOC Register in Timer Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 165 of 318 R8C/2G Group 17. Timers 17.2.1.1 Timer Write Control during Count Operation Timer RB has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each consist of a reload register and a counter. In timer mode, the TWRC bit in the TRBMR register can be used to select whether writing to the prescaler or timer during count operation is performed to both the reload register and counter or only to the reload register. However, values are transferred from the reload register to the counter of the prescaler in synchronization with the count source. In addition, values are transferred from the reload register to the counter of the timer in synchronization with prescaler underflows. Therefore, even if the TWRC bit is set for writing to both the reload register and counter, the counter value is not updated immediately after the WRITE instruction is executed. In addition, if the TWRC bit is set for writing to the reload register only, the synchronization of the writing will be shifted if the prescaler value changes. Figure 17.17 shows an Operating Example of Timer RB when Counter Value is Rewritten during Count Operation. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 166 of 318 R8C/2G Group 17. Timers When the TWRC bit is set to 0 (write to reload register and counter) Set 01h to the TRBPRE register and 25h to the TRBPR register by a program. Count source After writing, the reload register is written with the first count source. Reloads register of timer RB prescaler Previous value Reload with the second count source Reload on underflow New value (01h) Counter of timer RB prescaler 06h 05h 04h 01h 00h 01h 00h 01h 00h 01h 00h After writing, the reload register is written on the first underflow. Reloads register of timer RB Previous value New value (25h) Reload on the second underflow Counter of timer RB 03h 02h 25h 24h IR bit in TRBIC register 0 The IR bit remains unchanged until underflow is generated by a new value. When the TWRC bit is set to 1 (write to reload register only) Set 01h to the TRBPRE register and 25h to the TRBPR register by a program. Count source After writing, the reload register is written with the first count source. Reloads register of timer RB prescaler Previous value New value (01h) Reload on underflow Counter of timer RB prescaler 06h 05h 04h 03h 02h 01h 00h 01h 00h 01h 00h 01h 00h 01h After writing, the reload register is written on the first underflow. Reloads register of timer RB Previous value New value (25h) Reload on underflow Counter of timer RB 03h 02h 01h 00h 25h IR bit in TRBIC register 0 Only the prescaler values are updated, extending the duration until timer RB underflow. The above applies under the following conditions. Both bits TSTART and TCSTF in the TRBCR register are set to 1 (During count). Figure 17.17 Operating Example of Timer RB when Counter Value is Rewritten during Count Operation Page 167 of 318 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 R8C/2G Group 17. Timers 17.2.2 Programmable Waveform Generation Mode In programmable waveform generation mode, the signal output from the TRBO pin is inverted each time the counter underflows, while the values in registers TRBPR and TRBSC are counted alternately (refer to Table 17.8 Programmable Waveform Generation Mode Specifications). Counting starts by counting the setting value in the TRBPR register. The TRBOCR register is unused in this mode. Figure 17.18 shows TRBIOC Register in Programmable Waveform Generation Mode. Figure 17.19 shows an Operating Example of Timer RB in Programmable Waveform Generation Mode. Table 17.8 Programmable Waveform Generation Mode Specifications Specification f1, f2, f8, timer RA underflow • Decrement • When the timer underflows, it reloads the contents of the primary reload and secondary reload registers alternately before the count continues. Primary period: (n+1)(m+1)/fi Secondary period: (n+1)(p+1)/fi Period: (n+1){(m+1)+(p+1)}/fi fi: Count source frequency n: Value set in TRBPRE register m: Value set in TRBPR register p: Value set in TRBSC register 1 (count start) is written to the TSTART bit in the TRBCR register. • 0 (count stop) is written to the TSTART bit in the TRBCR register. • 1 (count forcibly stop) is written to the TSTOP bit in the TRBCR register. In half a cycle of the count source, after timer RB underflows during the secondary period (at the same time as the TRBO output change) [timer RB interrupt] Programmable output port or pulse output Programmable I/O port or INT0 interrupt input The count value can be read out by reading registers TRBPR and TRBPRE.(1) • When registers TRBPRE, TRBSC, and TRBPR are written while the count is stopped, values are written to both the reload register and counter. • When registers TRBPRE, TRBSC, and TRBPR are written to during count operation, values are written to the reload registers only.(2) • Output level select function The TOPL bit in the TRBIOC register selects the output level during primary and secondary periods. • TRBO pin output switch function Timer RB pulse output or P3_1 (P1_3) latch output is selected by the TOCNT bit in the TRBIOC register.(3) • TRBO pin select function P3_1 or P1_3 is selected by the TRBOSEL bit in the PINSR2 register. Item Count sources Count operations Width and period of output waveform Count start condition Count stop conditions Interrupt request generation timing TRBO pin function INT0 pin function Read from timer Write to timer Select functions NOTES: 1. Even when counting the secondary period, the TRBPR register may be read. 2. The set values are reflected in the waveform output beginning with the following primary period after writing to the TRBPR register. 3. The value written to the TOCNT bit is enabled by the following. • When counting starts. • When a timer RB interrupt request is generated. The contents after the TOCNT bit is changed are reflected from the output of the following primary period. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 168 of 318 R8C/2G Group 17. Timers Timer RB I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol TRBIOC Bit Symbol TOPL Address 010Ah Bit Name Timer RB output level select 0 : Outputs bit Outputs Outputs 1 : Outputs Outputs Outputs Timer RB output sw itch bit One-shot trigger control bit One-shot trigger polarity select bit After Reset 00h Function “H” for primary period “L” for secondary period “L” w hen the timer is stopped “L” for primary period “H” for secondary period “H” w hen the timer is stopped RW RW TOCNT INOSTG INOSEG — (b7-b4) 0 : Outputs timer RB w aveform 1 : Outputs value in P3_1 (P1_3) port register Set to 0 in programmable w aveform generation mode. RW RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. Figure 17.18 TRBIOC Register in Programmable Waveform Generation Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 169 of 318 R8C/2G Group 17. Timers Set to 1 by program TSTART bit in TRBCR register 1 0 Count source Timer RB prescaler underflow signal Timer RB secondary reloads Timer RB primary reloads Counter of timer RB 01h 00h 02h 01h 00h 01h 00h 02h IR bit in TRBIC register 1 0 Set to 0 by program Set to 0 when interrupt request is acknowledged, or set by program. TOPL bit in TRBIO register 1 0 Waveform output starts Waveform output inverted Waveform output starts TRBO pin output 1 0 Primary period Secondary period Primary period Initial output is the same level as during secondary period. The above applies under the following conditions. TRBPRE = 01h, TRBPR = 01h, TRBSC = 02h TRBIOC register TOCNT = 0 (timer RB waveform is output from the TRBO pin) Figure 17.19 Operating Example of Timer RB in Programmable Waveform Generation Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 170 of 318 R8C/2G Group 17. Timers 17.2.3 Programmable One-shot Generation Mode In programmable one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (refer to Table 17.9 Programmable One-Shot Generation Mode Specifications). When a trigger is generated, the timer starts operating from the point only once for a given period equal to the set value in the TRBPR register. The TRBSC register is not used in this mode. Figure 17.20 shows TRBIOC Register in Programmable One-Shot Generation Mode. Figure 17.21 shows an Operating Example of Programmable One-Shot Generation Mode. Table 17.9 Programmable One-Shot Generation Mode Specifications Specification f1, f2, f8, timer RA underflow • Decrement the setting value in the TRBPR register • When the timer underflows, it reloads the contents of the reload register before the count completes and the TOSSTF bit is set to 0 (one-shot stops). • When the count stops, the timer reloads the contents of the reload register before it stops. One-shot pulse (n+1)(m+1)/fi output time fi: Count source frequency, n: Setting value in TRBPRE register, m: Setting value in TRBPR register(2) Count start conditions • The TSTART bit in the TRBCR register is set to 1 (count starts) and the next trigger is generated • Set the TOSST bit in the TRBOCR register to 1 (one-shot starts) • Input trigger to the INT0 pin Count stop conditions • When reloading completes after timer RB underflows during primary period • When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops) • When the TSTART bit in the TRBCR register is set to 0 (stops counting) • When the TSTOP bit in the TRBCR register is set to 1 (forcibly stops counting) Interrupt request In half a cycle of the count source, after the timer underflows (at the same time as generation timing the TRBO output ends) [timer RB interrupt] TRBO pin function Pulse output INT0 pin functions • When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger disabled): programmable I/O port or INT0 interrupt input • When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger enabled): external trigger (INT0 interrupt input) The count value can be read out by reading registers TRBPR and TRBPRE. • When registers TRBPRE and TRBPR are written while the count is stopped, values are written to both the reload register and counter. • When registers TRBPRE and TRBPR are written during the count, values are written to the reload register only (the data is transferred to the counter at the following reload).(1) • Output level select function The TOPL bit in the TRBIOC register selects the output level of the one-shot pulse waveform. • One-shot trigger select function Refer to 17.2.3.1 One-Shot Trigger Selection. • TRBO pin select function P3_1 or P1_3 is selected by the TRBOSEL bit in the PINSR2 register. Item Count sources Count operations Read from timer Write to timer Select functions NOTES: 1. The set value is reflected at the following one-shot pulse after writing to the TRBPR register. 2. Do not set both the TRBPRE and TRBPR registers to 00h. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 171 of 318 R8C/2G Group 17. Timers Timer RB I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol TRBIOC Bit Symbol TOPL Address 010Ah Bit Name Timer RB Output Level Select Bit 0 : Outputs Outputs 1 : Outputs Outputs After Reset 00h Function one-shot pulse “H” “L” w hen the timer is stopped one-shot pulse “L” “H” w hen the timer is stopped RW RW TOCNT INOSTG INOSEG — (b7-b4) Timer RB Output Sw itch Bit One-Shot Trigger Control Bit(1) One-Shot Trigger Polarity Select Bit(1) Set to 0 in programmable one-shot generation mode. 0 : INT0 pin one-shot trigger disabled _____ 1 : INT0 pin one-shot trigger enabled 0 : Falling edge trigger 1 : Rising edge trigger _____ RW RW RW — Nothing is assigned. If necessary, set to 0. When read, its content is 0. NOTE: 1. Refer to 17.2.3.1 One-Shot Trigger Selection. Figure 17.20 TRBIOC Register in Programmable One-Shot Generation Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 172 of 318 R8C/2G Group 17. Timers Set to 1 by program TSTART bit in TRBCR register 1 0 Set to 1 by program Set to 0 when counting ends Set to 1 by INT0 pin input trigger TOSSTF bit in TRBOCR register 1 0 INT0 pin input Count source Timer RB prescaler underflow signal Count starts Timer RB primary reloads Count starts Timer RB primary reloads Counter of timer RB 01h 00h 01h 00h 01h Set to 0 when interrupt request is acknowledged, or set by program IR bit in TRBIC register 1 0 Set to 0 by program TOPL bit in TRBIOC register 1 0 Waveform output starts Waveform output ends Waveform output starts Waveform output ends TRBIO pin output 1 0 The above applies under the following conditions. TRBPRE = 01h, TRBPR = 01h TRBIOC register TOPL = 0, TOCNT = 0 INOSTG = 1 (INT0 one-shot trigger enabled) INOSEG = 1 (edge trigger at rising edge) Figure 17.21 Operating Example of Programmable One-Shot Generation Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 173 of 318 R8C/2G Group 17. Timers 17.2.3.1 One-Shot Trigger Selection In programmable one-shot generation mode and programmable wait one-shot generation mode, operation starts when a one-shot trigger is generated while the TCSTF bit in the TRBCR register is set to 1 (count starts). A one-shot trigger can be generated by either of the following causes: • 1 is written to the TOSST bit in the TRBOCR register by a program. • Trigger input from the INT0 pin. When a one-shot trigger occurs, the TOSSTF bit in the TRBOCR register is set to 1 (one-shot operation in progress) after one or two cycles of the count source have elapsed. Then, in programmable one-shot generation mode, count operation begins and one-shot waveform output starts. (In programmable wait one-shot generation mode, count operation starts for the wait period.) If a one-shot trigger occurs while the TOSSTF bit is set to 1, no retriggering occurs. To use trigger input from the INT0 pin, input the trigger after making the following settings: • Set the PD4_5 bit in the PD4 register to 0 (input port). • Select the INT0 digital filter with bits INT0F1 and INT0F0 in the INTF register. • Select both edges or one edge with the INT0PL bit in INTEN register. If one edge is selected, further select falling or rising edge with the INOSEG bit in TRBIOC register. • Set the INT0EN bit in the INTEN register to 0 (enabled). • After completing the above, set the INOSTG bit in the TRBIOC register to 1 (INT pin one-shot trigger enabled). Note the following points with regard to generating interrupt requests by trigger input from the INT0 pin. • Processing to handle the interrupts is required. Refer to 13. Interrupts, for details. • If one edge is selected, use the POL bit in the INT0IC register to select falling or rising edge. (The INOSEG bit in the TRBIOC register does not affect INT0 interrupts). • If a one-shot trigger occurs while the TOSSTF bit is set to 1, timer RB operation is not affected, but the value of the IR bit in the INT0IC register changes. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 174 of 318 R8C/2G Group 17. Timers 17.2.4 Programmable Wait One-Shot Generation Mode In programmable wait one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (refer to Table 17.10 Programmable Wait One-Shot Generation Mode Specifications). When a trigger is generated from that point, the timer outputs a pulse only once for a given length of time equal to the setting value in the TRBSC register after waiting for a given length of time equal to the setting value in the TRBPR register. Figure 17.22 shows TRBIOC Register in Programmable Wait One-Shot Generation Mode. Figure 17.23 shows an Operating Example of Programmable Wait One-Shot Generation Mode. Table 17.10 Programmable Wait One-Shot Generation Mode Specifications Specification f1, f2, f8, timer RA underflow • Decrement the timer RB primary setting value. • When a count of the timer RB primary underflows, the timer reloads the contents of timer RB secondary before the count continues. • When a count of the timer RB secondary underflows, the timer reloads the contents of timer RB primary before the count completes and the TOSSTF bit is set to 0 (one-shot stops). • When the count stops, the timer reloads the contents of the reload register before it stops. (n+1)(m+1)/fi fi: Count source frequency n: Value set in the TRBPRE register, m Value set in the TRBPR register(2) (n+1)(p+1)/fi fi: Count source frequency n: Value set in the TRBPRE register, p: Value set in the TRBSC register • The TSTART bit in the TRBCR register is set to 1 (count starts) and the next trigger is generated. • Set the TOSST bit in the TRBOCR register to 1 (one-shot starts). • Input trigger to the INT0 pin • When reloading completes after timer RB underflows during secondary period. • When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops). • When the TSTART bit in the TRBCR register is set to 0 (starts counting). • When the TSTOP bit in the TRBCR register is set to 1 (forcibly stops counting). In half a cycle of the count source after timer RB underflows during secondary period (complete at the same time as waveform output from the TRBO pin) [timer RB interrupt]. Pulse output • When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger disabled): programmable I/O port or INT0 interrupt input • When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger enabled): external trigger (INT0 interrupt input) The count value can be read out by reading registers TRBPR and TRBPRE. • When registers TRBPRE, TRBSC, and TRBPR are written while the count stops, values are written to both the reload register and counter. • When registers TRBPRE, TRBSC, and TRBPR are written to during count operation, values are written to the reload registers only.(1) • Output level select function The TOPL bit in the TRBIOC register selects the output level of the one-shot pulse waveform. • One-shot trigger select function Refer to 17.2.3.1 One-Shot Trigger Selection. • TRBO pin select function P3_1 or P1_3 is selected by the TRBOSEL bit in the PINSR2 register. Item Count sources Count operations Wait time One-shot pulse output time Count start conditions Count stop conditions Interrupt request generation timing TRBO pin function INT0 pin functions Read from timer Write to timer Select functions NOTES: 1. The set value is reflected at the following one-shot pulse after writing to registers TRBSC and TRBPR. 2. Do not set both the TRBPRE and TRBPR registers to 00h. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 175 of 318 R8C/2G Group 17. Timers Timer RB I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol TRBIOC Bit Symbol TOPL Address After Reset 010Ah 00h Bit Name Function Timer RB output level select 0: Outputs one-shot pulse “H”. bit Outputs “L” w hen the timer stops or during w ait. 1: Outputs one-shot pulse “L”. Outputs “H” w hen the timer stops or during w ait. Timer RB output sw itch bit Set to 0 in programmable w ait one-shot generation mode. _____ RW RW TOCNT INOSTG INOSEG — (b7-b4) RW RW RW — One-shot trigger control bit(1) 0 : INT0 pin one-shot trigger disabled _____ 1 : INT0 pin one-shot trigger enabled One-shot trigger polarity 0 : Falling edge trigger select bit(1) 1 : Rising edge trigger Nothing is assigned. If necessary, set to 0. When read, the content is 0. NOTE: 1. Refer to 17.2.3.1 One-Shot Trigger Selection. Figure 17.22 TRBIOC Register in Programmable Wait One-Shot Generation Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 176 of 318 R8C/2G Group 17. Timers Set to 1 by program TSTART bit in TRBCR register 1 0 Set to 1 by setting 1 to TOSST bit in TRBOCR register, or INT0 pin input trigger. Set to 0 when counting ends TOSSTF bit in TRBOCR register 1 0 INT0 pin input Count source Timer RB prescaler underflow signal Count starts Timer RB secondary reloads Timer RB primary reloads Counter of timer RB 01h 00h 04h 03h 02h 01h 00h 01h Set to 0 when interrupt request is acknowledged, or set by program. IR bit in TRBIC register 1 0 Set to 0 by program TOPL bit in TRBIOC register 1 0 Wait starts Waveform output starts Waveform output ends TRBIO pin output 1 0 Wait (primary period) One-shot pulse (secondary period) The above applies under the following conditions. TRBPRE = 01h, TRBPR = 01h, TRBSC = 04h INOSTG = 1 (INT0 one-shot trigger enabled) INOSEG = 1 (edge trigger at rising edge) Figure 17.23 Operating Example of Programmable Wait One-Shot Generation Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 177 of 318 R8C/2G Group 17. Timers 17.2.5 Notes on Timer RB • Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the count starts. • Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the MCU. Consequently, the timer value may be updated during the period when these two registers are being read. • In programmable one-shot generation mode and programmable wait one-shot generation mode, when setting the TSTART bit in the TRBCR register to 0, 0 (stops counting) or setting the TOSSP bit in the TRBOCR register to 1 (stops one-shot), the timer reloads the value of reload register and stops. Therefore, in programmable one-shot generation mode and programmable wait one-shot generation mode, read the timer count value before the timer stops. • The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to 1 (count starts) while the count is stopped. During this time, do not access registers associated with timer RB(1)other than the TCSTF bit. Timer RB starts counting at the first valid edge of the count source after the TCSTF bit is set to 1 (during count). The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RB(1) other than the TCSTF bit. NOTE: 1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and TRBPR. • If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately. • If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes after one or two cycles of the count source have elapsed. If the TOSSP bit is written to 1 during the period between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit may be set to either 0 or 1. 17.2.5.1 Timer mode The following workaround should be performed in timer mode. To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: • When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 178 of 318 R8C/2G Group 17. Timers 17.2.5.2 Programmable waveform generation mode The following three workarounds should be performed in programmable waveform generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: • When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval. (2) To change registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), synchronize the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period A shown in Figures 17.24 and 17.25. The following shows the detailed workaround examples. • Workaround example (a): As shown in Figure 17.24, write to registers TRBSC and TRBPR in the timer RB interrupt routine. These write operations must be completed by the beginning of period A. Period A Count source/ prescaler underflow signal TRBO pin output Primary period Secondary period IR bit in TRBIC register (a) Interrupt request is acknowledged (b) Ensure sufficient time Interrupt request is generated Interrupt Instruction in sequence interrupt routine Set the secondary and then the primary register immediately (a) Period between interrupt request generation and the completion of execution of an instruction. The length of time varies depending on the instruction being executed. The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as the divisor). (b) 20 cycles. 21 cycles for address match and single-step interrupts. Figure 17.24 Workaround Example (a) When Timer RB interrupt is Used Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 179 of 318 R8C/2G Group 17. Timers • Workaround example (b): As shown in Figure 17.25 detect the start of the primary period by the TRBO pin output level and write to registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A. If the port register’s bit value is read after the port direction register’s bit corresponding to the TRBO pin is set to 0 (input mode), the read value indicates the TRBO pin output value. Period A Count source/ prescaler underflow signal TRBO pin output Read value of the port register’s bit corresponding to the TRBO pin (when the bit in the port direction register is set to 0) Primary period Secondary period (i) (ii) (iii) Ensure sufficient time The TRBO output inversion is detected at the end of the secondary period. Upon detecting (i), set the secondary and then the primary register immediately. Figure 17.25 Workaround Example (b) When TRBO Pin Output Value is Read (3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case, registers TRBPRE and TRBPR are initialized and their values are set to the values after reset. 17.2.5.3 Programmable one-shot generation mode The following two workarounds should be performed in programmable one-shot generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: • When the TRBPRE register is written continuously during count operation (TCSTF bit is set to 1), allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval. (2) Do not set both the TRBPRE and TRBPR registers to 00h. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 180 of 318 R8C/2G Group 17. Timers 17.2.5.4 Programmable wait one-shot generation mode The following three workarounds should be performed in programmable wait one-shot generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: • When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval. (2) Do not set both the TRBPRE and TRBPR registers to 00h. (3) Set registers TRBSC and TRBPR using the following procedure. (a) To use “INT0 pin one-shot trigger enabled” as the count start condition Set the TRBSC register and then the TRBPR register. At this time, after writing to the TRBPR register, allow an interval of 0.5 or more cycles of the count source before trigger input from the INT0 pin. (b) To use “writing 1 to TOSST bit” as the start condition Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the TRBPR register, allow an interval of 0.5 or more cycles of the count source before writing to the TOSST bit. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 181 of 318 R8C/2G Group 17. Timers 17.3 Timer RE Timer RE has the 4-bit counter and 8-bit counter. Timer RE has the following 2 modes: • Real-time clock mode Generate 1-second signal from fC4 and count seconds, minutes, hours, and days of the week. • Output compare mode Count a count source and detect compare matches. The count source for timer RE is the operating clock that regulates the timing of timer operations. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 182 of 318 R8C/2G Group 17. Timers 17.3.1 Real-Time Clock Mode In real-time clock mode, a 1-second signal is generated from fC4 using a divide-by-2 frequency divider, 4-bit counter, and 8-bit counter and used to count seconds, minutes, hours, and days of the week. Figure 17.26 shows a Block Diagram of Real-Time Clock Mode and Table 17.11 lists the Real-Time Clock Mode Specifications. Figures 17.27 to 17.31 and 17.33 to 17.35 show the Registers Associated with Real-Time Clock Mode. Table 17.12 lists the Interrupt Sources, Figure 17.32 shows the Definition of Time Representation and Figure 17.36 shows the Operating Example in Real-Time Clock Mode. RCS6 to RCS4 f2 fC f4 (1/16) fC4 (8.192kHz) 1/2 4-bit counter (1/256) 8-bit counter PLUS MIN US TREOPR register (1s) Overflow f8 = 000b = 001b = 010b = 100b = 011b TOENA TREOSEL2=1 TREOSEL=0 TREOSEL2=0 TREOSEL=1 TREO (P0_4) pin TREO (P6_0) pin TREO (P6_5) pin Data (D5 to D0) Data bus Overflow Overflow Overflow TRESEC register TREMIN register TREHR register TREWK register 000 PM bit WKIE H12_H24 bit DYIE HRIE MNIE Timing control Timer RE interrupt INT bit SEIE BSY bit TOENA, H12_H24, PM, INT: Bits in TRECR1 register SEIE, MNIE, HRIE, DYIE, WKIE: Bits in TRECR2 register BSY: Bit in TRESEC, TREMIN, TREHR, TREWK register RCS4 to RCS6: Bits in TRECSR register TREOSEL: Bit in PINSR3 register TREOSEL2: Bit in PINSR4 register Figure 17.26 Block Diagram of Real-Time Clock Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 183 of 318 R8C/2G Group 17. Timers Table 17.11 Real-Time Clock Mode Specifications Specification fC4 Increment 1 (count starts) is written to TSTART bit in TRECR1 register 0 (count stops) is written to TSTART bit in TRECR1 register Select any one of the following: • Update second data • Update minute data • Update hour data • Update day of week data • When day of week data is set to 000b (Sunday) Programmable I/O ports or output of f2, fC, f4, f8 or, 1Hz When reading TRESEC, TREMIN, TREHR, or TREWK register, the count value can be read. The values read from registers TRESEC, TREMIN, and TREHR are represented by the BCD code. When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer stops), the value can be written to registers TRESEC, TREMIN, TREHR, and TREWK. The values written to registers TRESEC, TREMIN, and TREHR are represented by the BCD codes. • 12-hour mode/24-hour mode switch function • Counter precision adjustment function • TREO pin select function P0_4, P6_0, or P6_5 is selected by the TREOSEL bit in the PINSR3 register and the TREOSEL2 bit in the PINSR4 register. Item Count source Count operation Count start condition Count stop condition Interrupt request generation timing TREO pin function Read from timer Write to timer Selectable functions Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 184 of 318 R8C/2G Group 17. Timers Timer RE Second Data Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRESEC Bit Symbol SC00 SC01 SC02 SC03 SC10 SC11 SC12 Address 0118h Bit Name 1st digit of second count bits After Reset Undefined Function Setting Range RW RW RW RW RW RW RW RW Count 0 to 9 every second. When the 0 to 9 digit moves up, 1 is added to the 2nd (BCD digit of second. code) When counting 0 to 5, 60 seconds are counted. 0 to 5 (BCD code) 2nd digit of second count bits Timer RE busy flag BSY This bit is set to 1 w hile registers TRESEC, TREMIN, TREHR, and TREWK are updated. RO Figure 17.27 TRESEC Register in Real-Time Clock Mode Timer RE Minute Data Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TREMIN Bit Symbol MN00 MN01 MN02 MN03 MN10 MN11 MN12 Address 0119h Bit Name 1st digit of minute count bits After Reset Undefined Function Setting Range RW RW RW RW RW RW RW RW Count 0 to 9 every minute. When the 0 to 9 digit moves up, 1 is added to the 2nd (BCD digit of minute. code) When counting 0 to 5, 60 minutes are 0 to 5 counted. (BCD code) This bit is set to 1 w hile registers TRESEC, TREMIN, TREHR, and TREWK are updated. 2nd digit of minute count bits Timer RE busy flag BSY RO Figure 17.28 TREMIN Register in Real-Time Clock Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 185 of 318 R8C/2G Group 17. Timers Timer RE Hour Data Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TREHR Bit Symbol HR00 HR01 HR02 HR03 HR10 HR11 — (b6) BSY Address 011Ah Bit Name 1st digit of hour count bits After Reset X0XXXXXXb Function Setting Range RW RW RW RW RW RW RW — Count 0 to 9 every hour. When the 0 to 9 digit moves up, 1 is added to the 2nd (BCD digit of hour. code) Count 0 to 1 w hen the H12_H24 bit is 0 to 2 set to 0 (12-hour mode). (BCD Count 0 to 2 w hen the H12_H24 bit is code) set to 1 (24-hour mode). 2nd digit of hour count bits Nothing is assigned. If necessary, set to 0. When read, the content is 0. Timer RE busy flag This bit is set to 1 w hile registers TRESEC, TREMIN, TREHR, and TREWK are updated. RO Figure 17.29 TREHR Register in Real-Time Clock Mode Timer RE Day of Week Data Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TREWK Bit Symbol WK0 Address 011Bh Bit Name Day of w eek count bits After Reset X0000XXXb Function b2 b1 b0 RW RW WK1 WK2 — (b6-b3) BSY 0 0 0 : Sunday 0 0 1 : Monday 0 1 0 : Tuesday 0 1 1 : Wednesday 1 0 0 : Thursday 1 0 1 : Friday 1 1 0 : Saturday 1 1 1 : Do not set. RW RW Nothing is assigned. If necessary, set to 0. When read, the content is 0. Timer RE busy flag This bit is set to 1 w hile registers TRESEC, TREMIN, TREHR, and TREWK are updated. — RO Figure 17.30 TREWK Register in Real-Time Clock Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 186 of 318 R8C/2G Group 17. Timers Timer RE Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address 011Ch TRECR1 Bit Symbol Bit Name — Nothing is assigned. If necessary, set to 0. (b0) When read, the content is 0. TCSTF TOENA INT Timer RE count status flag TREO pin output enable bit Interrupt request timing bit Timer RE reset bit 0 : Count stopped 1 : Counting After Reset XXX0X0X0b Function RW — RO RW RW 0 : Disable clock output 1 : Enable clock output Set to 1 in real-time clock mode. When setting this bit to 0, after setting it to 1, the follow ings w ill occur. • Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2 are set to 00h. • Bits TCSTF, INT, PM, H12_H24, and TSTART in the TRECR1 register are set to 0. • The 8-bit counter is set to 00h and the 4-bit counter is set to 0h. When the H12_H24 bit is set to 0 (12-hour mode)(1) 0 : a.m. 1 : p.m. When the H12_H24 bit is set to 1 (24-hour mode), its value is undefined. 0 : 12-hour mode 1 : 24-hour mode 0 : Count stops 1 : Count starts TRERST RW A.m./p.m. bit PM RW H12_H24 TSTART Operating mode select bit Timer RE count start bit RW RW NOTE: 1. This bit is automatically modified w hile timer RE counts. Figure 17.31 TRECR1 Register in Real-Time Clock Mode Noon H12_H24 bit = 1 (24-hour mode) H12_H24 bit = 0 (12-hour mode) Contents of TREHR Register 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 0 13 1 14 2 15 3 16 4 17 5 Contents of PM bit Contents in TREWK register 0 (a.m.) 000 (Sunday) Date changes 1 (p.m.) Contents of TREHR Register H12_H24 bit = 1 (24-hour mode) H12_H24 bit = 0 (12-hour mode) 18 6 19 7 20 8 21 9 22 10 23 11 0 0 1 1 2 2 3 3 ⋅⋅⋅ ⋅⋅⋅ ⋅⋅⋅ ⋅⋅⋅ Contents of PM bit Contents in TREWK register 1 (p.m.) 000 (Sunday) 0 (a.m.) 001 (Monday) PM bit and H12_H24 bits: Bits in TRECR1 register The above applies to the case when count starts from a.m. 0 on Sunday. Figure 17.32 Definition of Time Representation Page 187 of 318 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 R8C/2G Group 17. Timers Timer RE Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol TRECR2 Bit Symbol SEIE Address 011Dh Bit Name Periodic interrupt triggered every second enable bit(1) After Reset 00XXXXXXb Function 0 : Disable periodic interrupt triggered every second 1 : Enable periodic interrupt triggered every second 0 : Disable periodic interrupt triggered every minute 1 : Enable periodic interrupt triggered every minute 0 : Disable periodic interrupt triggered every hour 1 : Enable periodic interrupt triggered every hour RW RW MNIE Periodic interrupt triggered every minute enable bit(1) RW HRIE Periodic interrupt triggered every hour enable bit(1) RW DYIE Periodic interrupt triggered every day 0 : Disable periodic interrupt triggered enable bit(1) every day 1 : Enable periodic interrupt triggered every day Periodic interrupt triggered every w eek enable bit(1) 0 : Disable periodic interrupt triggered every w eek 1 : Enable periodic interrupt triggered every w eek Set to 0 in real-time clock mode. RW WKIE RW COMIE — (b7-b6) Compare match interrupt enable bit RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. NOTE: 1. Do not set multiple enable bits to 1 (enable interrupt). Figure 17.33 TRECR2 Register in Real-Time Clock Mode Table 17.12 Interrupt Sources Interrupt Source Value in TREWK register is set to 000b (Sunday) (1-week period) TREWK register is updated (1-day period) TREHR register is updated (1-hour period) TREMIN register is updated (1-minute period) TRESEC register is updated (1-second period) Interrupt Enable Bit WKIE DYIE HRIE MNIE SEIE Factor Periodic interrupt triggered every week Periodic interrupt triggered every day Periodic interrupt triggered every hour Periodic interrupt triggered every minute Periodic interrupt triggered every second Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 188 of 318 R8C/2G Group 17. Timers Timer RE Count Source Select Register b7 b6 b5 b4 b3 b2 b1 b0 1000 Symbol TRECSR Bit Symbol RCS0 RCS1 RCS2 RCS3 RCS4 RCS5 Address 011Eh Bit Name Count source select bits After Reset 00001000b Function Set to 00b in real-time clock mode. RW RW RW 4-bit counter select bit Real-time clock mode select bit Clock output select bits (1) Set to 0 in real-time clock mode. Set to 1 in real-time clock mode. b6 b5 b4 RW RW RW RW RCS6 — (b7) 0 0 0 : f2 0 0 1 : fC 0 1 0 : f4 0 1 1 : 1Hz 1 0 0 : f8 Other than above : Do not set. Nothing is assigned. If necessary, set to 0. When read, the content is 0. RW — NOTE: 1. Write to bits RCS4 to RCS6 w hen the TOENA bit in the TRECR1 register is set to 0 (disable clock output). Figure 17.34 TRECSR Register in Real-Time Clock Mode Timer RE Real-Time Clock Precision Adjust Register(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TREOPR Bit Symbol D0 D1 D2 D3 D4 D5 MINUS Address 011Fh Bit Name 8-bit counter adjust bit After Reset 00h Function The correction value of the 8-bit counter is stored. When read, the content is 000000b. Setting Range 00h to 3Ch RW RW RW RW RW RW RW RW 8-bit counter subtract bit(2) 8-bit counter add bit(2) PLUS When this bit is set to 1, the correction value set by D0 to D5 is subtracted from the 8-bit counter value. When read, the content is 0. When this bit is set to 1, the correction value set by D0 to D5 is added to the 8-bit counter value. When read, the content is 0. RW NOTES: 1. Use the MOV instruction for setting the TREOPR register. Allow a period (s) of the XCIN clock × 2064 or more betw een w rites to the TREOPR register. 2. Write 1 to either the MINUS bit or the PLUS bit only once during each interrupt routine for the w eek/day/hour/minute/second cycle. When 00b or 11b is w ritten to bits MINUS and PLUS, the 8-bit counter value is not added or subtracted. Figure 17.35 TREOPR Register in Real-Time Clock Mode Page 189 of 318 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 R8C/2G Group 17. Timers 1s Approx. 62.5 ms BSY bit Approx. 62.5 ms Bits SC12 to SC00 in TRESEC register 58 59 00 Bits MN12 to MN00 in TREMIN register 03 04 Bits HR11 to HR00 in TREHR register (Not changed) PM bit in TRECR1 register 1 (Not changed) 0 Bits WK2 to WK0 in TREWK register (Not changed) Set to 0 by acknowledgement of interrupt request or a program IR bit in TREIC register (when SEIE bit in TRECR2 register is set to 1 (enable periodic interrupt triggered every second)) IR bit in TREIC register (when MNIE bit in TRECR2 register is set to 1 (enable periodic interrupt triggered every minute)) 1 0 1 0 BSY: Bit in registers TRESEC, TREMIN, TREHR, and TREWK Figure 17.36 Operating Example in Real-Time Clock Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 190 of 318 R8C/2G Group 17. Timers 17.3.2 Output Compare Mode In output compare mode, the internal count source divided by 2 is counted using the 4-bit or 8-bit counter and compare value match is detected with the 8-bit counter. Figure 17.37 shows a Block Diagram of Output Compare Mode and Table 17.13 lists the Output Compare Mode Specifications. Figures 17.38 to 17.42 show the Registers Associated with Output Compare Mode, and Figure 17.43 shows the Operating Example in Output Compare Mode. RCS6 to RCS4 f4 f8 RCS1 to RCS0 = 00b = 01b f32 fC4 = 10b = 11b RCS2 = 0 f2 fC =000b =001b =010b =100b TREOSEL2=0 TREOSEL=1 TREO (P0_4) pin TREO (P6_0) pin TREO (P6_5) pin 1/2 4-bit counter RCS2 = 1 TOENA TREOSEL2=1 TREOSEL=0 8-bit counter TQ R =110b Comparison circuit TRERST, TOENA: Bits in TRECR1 register COMIE: Bit in TRECR2 register RCS0 to RCS2, RCS5 to RCS6: Bits in TRECSR register TREOSEL: Bit in PINSR3 register TREOSEL2: Bit in PINSR4 register Match signal Reset TRERST COMIE Timer RE interrupt TRESEC TREMIN Data bus Figure 17.37 Block Diagram of Output Compare Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 191 of 318 R8C/2G Group 17. Timers Table 17.13 Output Compare Mode Specifications Specification f4, f8, f32, fC4 • Increment • When the 8-bit counter content matches with the TREMIN register content, the value returns to 00h and count continues. The count value is held while count stops. • When RCS2 = 0 (4-bit counter is not used) 1/fi x 2 x (n+1) • When RCS2 = 1 (4-bit counter is used) 1/fi x 32 x (n+1) fi: Frequency of count source n: Setting value of TREMIN register 1 (count starts) is written to the TSTART bit in the TRECR1 register 0 (count stops) is written to the TSTART bit in the TRECR1 register When the 8-bit counter content matches with the TREMIN register content Select any one of the following: • Programmable I/O ports • Output f2, fC, f4, or f8 • Compare output When reading the TRESEC register, the 8-bit counter value can be read. When reading the TREMIN register, the compare value can be read. Writing to the TRESEC register is disabled. When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer stops), writing to the TREMIN register is enabled. • Select use of 4-bit counter • Compare output function Every time the 8-bit counter value matches the TREMIN register value, TREO output polarity is reversed. The TREO pin outputs “L” after reset is deasserted and the timer RE is reset by the TRERST bit in the TRECR1 register. Output level is held by setting the TSTART bit to 0 (count stops). • TREO pin select function P0_4, P6_0, or P6_5 is selected by the TREOSEL bit in the PINSR3 register and the TREOSEL2 bit in the PINSR4 register. Item Count sources Count operations Count period Count start condition Count stop condition Interrupt request generation timing TREO pin function Read from timer Write to timer Selectable functions Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 192 of 318 R8C/2G Group 17. Timers Timer RE Counter Data Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRESEC Address 0118h Function After Reset Undefined RW RO 8-bit counter data can be read. Although Timer RE stops counting, the count value is held. The TRESEC register is set to 00h at the compare match. Figure 17.38 TRESEC Register in Output Compare Mode Timer RE Compare Data Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TREMIN 8-bit compare data is stored. Address 0119h Function After Reset Undefined RW RW Figure 17.39 TREMIN Register in Output Compare Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 193 of 318 R8C/2G Group 17. Timers Timer RE Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 00 0 Symbol Address 011Ch TRECR1 Bit Symbol Bit Name — Nothing is assigned. If necessary, set to 0. (b0) When read, the content is 0. TCSTF TOENA INT Timer RE count status flag TREO pin output enable bit Interrupt request timing bit Timer RE reset bit 0 : Count stopped 1 : Counting After Reset XXX0X0X0b Function RW — RO RW RW 0 : Disable clock output 1 : Enable clock output Set to 0 in output compare mode. When setting this bit to 0, after setting it to 1, the follow ing w ill occur. • Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2 are set to 00h. • Bits TCSTF, INT, PM, H12_H24, and TSTART in the TRECR1 register are set to 0. • The 8-bit counter is set to 00h and the 4-bit counter is set to 0h. Set to 0 in output compare mode. 0 : Count stops 1 : Count starts TRERST RW PM H12_H24 TSTART A.m./p.m. bit Operating mode select bit Timer RE count start bit RW RW RW Figure 17.40 TRECR1 Register in Output Compare Mode Timer RE Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 00000 Symbol TRECR2 Bit Symbol SEIE MNIE HRIE DYIE WKIE COMIE — (b7-b6) Address 011Dh Bit Name Periodic interrupt triggered every second enable bit Periodic interrupt triggered every minute enable bit Periodic interrupt triggered every hour enable bit Periodic interrupt triggered every day enable bit Periodic interrupt triggered every w eek enable bit Compare match interrupt enable bit After Reset 00XXXXXXb Function Set to 0 in output compare mode. RW RW RW RW RW RW 0 : Disable compare match interrupt 1 : Enable compare match interrupt RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. Figure 17.41 TRECR2 Register in Output Compare Mode Page 194 of 318 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 R8C/2G Group 17. Timers Timer RE Count Source Select Register b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol TRECSR Bit Symbol RCS0 Address 011Eh Bit Name Count source select bits (1) After Reset 00001000b Function b1 b0 RW RW RCS1 4-bit counter select bit Real-time clock mode select bit Clock output select bits (2) 0 0 : f4 0 1 : f8 1 0 : f32 1 1 : fC4 RW RCS2 RCS3 RCS4 RCS5 0 : Not used 1 : Used Set to 0 in output compare mode. b6 b5 b4 RW RW RW RW RCS6 — (b7) 0 0 0 : f2 0 0 1 : fC 0 1 0 : f4 1 0 0 : f8 1 1 0 : Compare output Other than above : Do not set. Nothing is assigned. If necessary, set to 0. When read, the content is 0. RW — NOTES: 1. Write to bits RCS0 to RCS1 w hen the TCSTF bit in the TRECR1 register is set to 0 (count stopped). 2. Write to bits RCS4 to RCS6 w hen the TOENA bit in the TRECR1 register is set to 0 (disable clock output). Figure 17.42 TRECSR Register in Output Compare Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 195 of 318 R8C/2G Group 17. Timers Count starts 8-bit counter content (hexadecimal number) TREMIN register setting value Matched Matched Matched 00h Set to 1 by a program Time TSTART bit in TRECR1 register 1 0 2 cycles of maximum count source TCSTF bit in TRECR1 register 1 0 Set to 0 by acknowledgement of interrupt request or a program IR bit in TREIC register 1 0 1 0 Output polarity is inverted when the compare matches TREO output The above applies under the following conditions. TOENA bit in TRECR1 register = 1 (enable clock output) COMIE bit in TRECR2 register = 1 (enable compare match interrupt) RCS6 to RCS5 bits in TRECSR register = 11b (compare output) Figure 17.43 Operating Example in Output Compare Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 196 of 318 R8C/2G Group 17. Timers 17.3.3 Notes on Timer RE Starting and Stopping Count 17.3.3.1 Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates count start or stop. Bits TSTART and TCSTF are in the TRECR1 register. Timer RE starts counting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to 1. During this time, do not access registers associated with timer RE(1) other than the TCSTF bit. Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0 (count stops). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF bit. NOTE: 1. Registers associated with timer RE: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2, TRECSR, and TREOPR. 17.3.3.2 Register Setting Write to the following registers or bits when timer RE is stopped. • Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2 • Bits H12_H24, PM, and INT in TRECR1 register • Bits RCS0 to RCS3 in TRECSR register Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped). Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the TRECR2 register. Figure 17.44 shows a Setting Example in Real-Time Clock Mode. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 197 of 318 R8C/2G Group 17. Timers TRERST in TRECR1 register = 1 TRERST in TRECR1 register = 0 TSTART in TRECR1 register = 0 Timer RE register and control circuit reset Stop timer RE operation TCSTF in TRECR1 register = 0? Disable timer RE clock output (When it is necessary) TOENA in TRECR1 register = 0 TREIC register ← 00h (disable timer RE interrupt) Setting of registers TRECSR, TRESEC, TREMIN, TREHR, TREWK, and bits H12_H24, PM, and INT in TRECR1 register Select clock output Select clock source Seconds, minutes, hours, days of week, operating mode Set a.m./p.m., interrupt timing Setting of TRECR2 register Setting of TREIC register (IR bit ← 0, select interrupt priority level) TOENA in TRECR1 register = 1 TSTART in TRECR1 register = 1 Select interrupt source Enable timer RE clock output (When it is necessary) Start timer RE operation TCSTF in TRECR1 register = 1? Figure 17.44 Setting Example in Real-Time Clock Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 198 of 318 R8C/2G Group 17. Timers 17.3.3.3 Time Reading Procedure of Real-Time Clock Mode In real-time clock mode, read registers TRESEC, TREMIN, TREHR, and TREWK when time data is updated and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (not while data is updated). Also, when reading several registers, an incorrect time will be read if data is updated before another register is read after reading any register. In order to prevent this, use the reading procedure shown below. • Using an interrupt Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register in the timer RE interrupt routine. • Monitoring with a program 1 Monitor the IR bit in the TREIC register with a program and read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the IR bit in the TREIC register is set to 1 (timer RE interrupt request generated). • Monitoring with a program 2 (1) Monitor the BSY bit. (2) Monitor until the BSY bit is set to 0 after the BSY bit is set to 1 (approximately 62.5 ms while the BSY bit is set to 1). (3) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the BSY bit is set to 0. • Using read results if they are the same value twice (1) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register. (2) Read the same register as (1) and compare the contents. (3) Recognize as the correct value if the contents match. If the contents do not match, repeat until the read contents match with the previous contents. Also, when reading several registers, read them as continuously as possible. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 199 of 318 R8C/2G Group 17. Timers 17.4 Timer RF Timer RF is a 16-bit timer. The count source for timer RF is the operating clock that regulates the timing of timer operations. Figure 17.45 shows a Block Diagram of Timer RF. Figure 17.46 shows a Block Diagram of CMP Waveform Generation Unit. Figure 17.47 shows a Block Diagram of CMP Waveform Output Unit. Timer RF has two modes: input capture mode and output compare mode. Figures 17.48 to 17.51 show the timer RF associated registers. fC32 TIPF1 to TIPF0 f1 = 01b Sampling clock f8 = 10b = 11b = other than f32 Digital 00b filter = 00b TRFC20 = 1 TRFC20 = 0 Edge detection Capture interrupt TRFI Capture signal Capture, Compare 0 register TRFM0 register Comparator Compare 0 interrupt CMP waveform output unit CMP waveform output unit Counter TRF register TSTART CCLR = 1 Timer RF interrupt CCLR = 0 Timer RF counter clear signal Compare 1 interrupt CMP waveform generation unit CMP waveform output unit CMP waveform output unit TRFOSEL = 0 CMP waveform output unit TRFOSEL = 1 CMP waveform output unit TRFO00 TRFO01 TRFO02 TRFO10 TRFO11 (P3_4) TRFO11 (P3_7) TRFO12 Data bus TCK1 to TCK0 f1 = 00b f8 = 01b f32 = 10b Compare 1 register TRFM1 register Comparator TSTART, TCK0 to TCK1: Bits in TRFCR0 register TIPF0 to TIPF1, CCLR: Bits in TRFCR1 register TRFC20: Bit in TRFCR2 register TRFOSEL: Bit in PINSR4 register Figure 17.45 Block Diagram of Timer RF Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 200 of 318 R8C/2G Group 17. Timers TRFC14 TRFC15 Compare 0 interrupt signal Compare 1 interrupt signal TRFC16 TRFC17 “H” “L” Inverted TRFC17 to TRFC16 = 11b = 10b = 01b D T Latch R Q CMP output (internal signal) Reset Inverted “L” “H” TRFC15 to TRFC14 = 01b = 10b = 11b TRFC14 to TRFC17: Bits in TRFC1 register Figure 17.46 Block Diagram of CMP Waveform Generation Unit CMP output (Internal signal) TRFOUT6 = 0 TRFOUT0 = 1 Inverted TRFOUT6 = 1 TRFOUT0 = 0 TRFO00 P1_0 bit This diagram is a block diagram of the TRFO00 waveform output unit. The TRFO01 to TRFO02 and TRFO10 to TRFO12 waveform output units have the same configuration. TRFOUT0 and TRFOUT6: Bits in TRFOUT register P1_0: Bit in P1 register Figure 17.47 Block Diagram of CMP Waveform Output Unit Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 201 of 318 R8C/2G Group 17. Timers Timer RF Register(1) (b15) b7 (b8) b0 b7 b0 Symbol TRF Address 0291h-0290h Function After Reset 0000h RW RO Count source increment . 0000h can be read w hen the TSTART bit is set to 0 (count stops). Count value can be read w hen the TSTART bit is set to 1 (count starts). NOTE: 1. Access the TRF register in 16-bit units. Capture and Compare 0 Register(1) (b15) b7 (b8) b0 b7 b0 Symbol TRFM0 Mode Input capture mode Output compare mode(3) Address 029Dh-029Ch Function When the active edge of the measured pulse is input, store the value in the TRF register Store the value compared w ith TRF register (counter) After Reset 0000h(2) Setting Range ― 0000h to FFFFh RW RO RW NOTES: 1. Access the TRFM0 register in 16-bit units. 2. When the TMOD bit in the TRFCR1 register is set to 1, the value is set to FFFFh. 3. When setting a value in the TRFM0 register, set the TMOD bit in the TRFCR1 register to 1 (output compare mode). When the TMOD bit is set to 0 (input capture mode), no value can be w ritten. Compare 1 Register(1) (b15) b7 (b8) b0 b7 b0 Symbol TRFM1 Mode Output compare mode NOTE: 1. Access the TRFM1 register in 16-bit units. Address 029Fh-029Eh Function Store the value compared w ith TRF register (counter) After Reset FFFFh Setting Range 0000h to FFFFh RW RW Figure 17.48 Registers TRF, TRFM0, and TRFM1 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 202 of 318 R8C/2G Group 17. Timers Timer RF Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol TRFCR2 Bit Symbol TRFC20 — (b4-b1) — (b6-b5) — (b7) Address 0299h Bit Name Timer RF capture input select bit After Reset 00h Function 0 : TRFI pin input 1 : fC32 RW RW — RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. Reserved bits Set to 0. Nothing is assigned. If necessary, set to 0. When read, the content is 0. Timer RF Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol TRFCR0 Bit Symbol TSTART TCK0 Address 029Ah Bit Name Timer RF count start bit Timer RF count source select bits (1) After Reset 00h Function 0 : Count stops 1 : Count starts b2 b1 RW RW RW TCK1 Capture polarity select bits (1) 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : Do not set. b4 b3 RW TRFC03 TRFC04 CMP output select bit 0 w hen count stops CMP output select bit 1 w hen count stops Reserved bit 0 0 : Rising edge 0 1 : Falling edge 1 0 : Both edges 1 1 : Do not set. 0 : TRFC06 bit disabled Holds output level before count stops 1 : TRFC06 bit enabled 0 : “L” output w hen count stops 1 : “H” output w hen count stops Set to 0. RW RW TRFC05 RW TRFC06 — (b7) RW RW NOTE: 1. Rew rite this bit w hen the TSTART bit is set to 0 (count stops). Figure 17.49 Registers TRFCR2 and TRFCR0 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 203 of 318 R8C/2G Group 17. Timers Timer RF Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRFCR1 Bit Symbol TIPF0 Address 029Bh Bit Name TRFI filter select bits (1) After Reset 00h Function b1 b0 RW RW TIPF1 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling TRF register count operation 0 : Free-running operation 1 : Set TRF register to 0000h w hen compare select bit(2, 3) 1 is matched. Timer RF operation mode select bit(3) Compare 0 output select bits (2) 0 : Input capture mode(2, 4) 1 : Output compare mode b5 b4 CMP output w hen compare 0 is matched 0 0 : Unchanged 0 1 : Inverted 1 0 : “L” 1 1 : “H” RW CCLR RW TMOD RW TRFC14 RW TRFC15 Compare 1 output select bits (2) TRFC16 TRFC17 b7 b6 CMP output w hen compare 0 is matched 0 0 : Unchanged 0 1 : Inverted 1 0 : “L” 1 1 : “H” RW NOTES: 1. If filter enabled, w hen the same value from the TRFI pin is sampled three times continuously, the input is determined. 2. When the TMOD bit is set to 0 (input capture mode), set bits CCLR, and TRFC14 to TRFC17 to 0. 3. When the TSTART bit in the TRFCR0 register is set to 0 (count stops), rew rite bits CCLR and TMOD. 4. When the TMOD bit is set to 0 (input capture mode), set bits ILVL2 to ILVL0 in the CMP1IC register to 000b (level 0) and set the IR bit to 0 (no interrupt requested). Figure 17.50 TRFCR1 Register Timer RF Output Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRFOUT Bit Symbol TRFOUT0 TRFOUT1 TRFOUT2 TRFOUT3 TRFOUT4 TRFOUT5 TRFOUT6 TRFOUT7 Address 02FFh Bit Name TRFO00 output enable bit TRFO01 output enable bit TRFO02 output enable bit TRFO10 output enable bit TRFO11 output enable bit TRFO12 output enable bit TRFO00 to TRFO02 output invert bit TRFO10 to TRFO12 output invert bit After Reset 00h Function 0 : Output disabled 1 : Output enabled RW RW RW RW RW RW RW RW RW 0 : Output not inverted 1 : Output inverted Figure 17.51 TRFOUT Register Page 204 of 318 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 R8C/2G Group 17. Timers 17.4.1 Input Capture Mode In input capture mode, the edge of the TRFI pin input signal or fC32 is used as a trigger to latch the timer value and the width or the period of external signal is measured. The TRFI input is equipped with a digital filter, and this prevents errors caused by noise or the like from occurring. Table 17.14 shows the Input Capture Mode Specifications. Figure 17.52 shows an Operating Example in Input Capture Mode. Table 17.14 Input Capture Mode Specifications Specification f1, f8, f32 • Increment • Transfer the value in the TRF register to the TRFM0 register at the valid edge of the measured pulse. 1/fk × 65536 fk: Frequency of count source The TSTART bit in the TRFCR0 register is set to 1 (count starts). The TSTART bit in the TRFCR0 register is set to 0 (count stops). • The valid edge of TRFI input or fC32 [capture interrupt] • When timer RF overflows [timer RF interrupt] Item Count sources Count operations Count period Count start condition Count stop condition Interrupt request generation timing TRFI pin function Measured pulse input TRFO00 to TRFO02, Programmable I/O port TRFO11 to TRFO12 pin functions Counter value reset timing In the following cases, the value in the TRF register is set to 0000h. • When the TSTART bit in the TRFCR0 register is set to 0 (count stops). Read from timer • The count value can be read out by reading the TRF register. • The count value at the measured pulse valid edge input can be read out by reading the TRFM0 register. Write to timer Write to the TRF and TRFM0 registers is disabled. Select functions • TRFI or fC32 polarity selected Selects the valid edge of the measured pulse. (Bits TRFC03 to TRFC04 in the TRFCR0 register.) • Digital filter function The TRFI input is sampled, and when the sampled input level matches as three times, the level is determined. Selects the sampling clock of the digital filter. (Bits TIPF0 to TIPF1 in the TRFCR1 register.) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 205 of 318 R8C/2G Group 17. Timers Overflow FFFFh Counter contents (hex) Count starts ← Measurement value 2 ← Measurement value 1 ← Measurement value 3 0000h Set to 1 by a program TSTART bit in TRFCR0 register 1 0 The delay caused by digital filter and one count source cycle delay (max.). Measured pulse (TRFI pin input) 1 0 Set to 0 by a program Time When the count stops, the value is set to 0000h. TRFM0 register Undefined Measured value 1 Measured value 2 Measured value 3 Undefined Set to 0 when interrupt request is acknowledged, or set by a program. IR bit in CAPIC register 1 0 Set to 0 when interrupt request is acknowledged, or set by a program. IR bit in TRFIC register 1 0 Measurement value 2 measurement value 1 (10000h - measurement value 2) + measurement value 3 The above applies under the following conditions. Bits TRFC04 to TRFC03 in TRFCR0 register = 01b (Capture input polarity is set for falling edge.) TRFC20 bit in TRFCR2 register = 0 (TRFI pin input) Figure 17.52 Operating Example in Input Capture Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 206 of 318 R8C/2G Group 17. Timers 17.4.1.1 Digital Filter The TRFI input is sampled, and when the sampled input level matches three times, its level is determined. Select the digital filter function and sampling clock by the TRFCR1 register. TIPF1 to TIPF0 f1 f8 f32 = 01b = 10b = 11b Sampling clock TIPF1 to TIPF0 C TRFI input signal D Latch Count source C D Latch Q Q D Latch C Q D Latch C Q D Latch C Q Match detection circuit = 01b, 10b, 11b Edge detection circuit TMOD TRFC04 to TRFC03 = 00b Clock period selected by bits TIPF1 to TIPF0 Sampling clock TRFI input signal Input signal through digital filtering Recognition of the signal change with three times match Signal transmission delayed up to five sampling clock Transmission cannot be performed without three times match because the input signal is assumed to be noise. TRFC03 to TRFC04: Bits in TRFCR0 register TIPF0 to TIPF1 and TMOD: Bits in TRFCR1 register Figure 17.53 Block Diagram of Digital Filter Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 207 of 318 R8C/2G Group 17. Timers 17.4.2 Output Compare Mode In output compare mode, when the value of the TRF register matches the value of the TRFM0 (compare 0 match) or TRFM1 (compare 1 match) register, a user-set level is output mode from the output-compare output pin. Table 17.15 shows the Output Compare Mode Specifications. Table 17.16 shows the Output in Output Compare Mode (Example of TRFO00 Pin). Figure 17.54 shows an Operating Example in Output Compare Mode. Figure 17.55 shows an Operating Example in Output Compare Mode (“L” and “H” Held Output in Count Stops). Table 17.15 Output Compare Mode Specifications Specification f1, f8, f32 Increment PWM period: 1/fk × (n + 1) “L” level width: 1/fk × (m + 1) “H” level width: 1/fk × (n - m) fk: Frequency of count source m: Value set in the TRFM0 register n: Value set in the TRFM1 register m+1 n-m Item Count sources Count operations PWM waveform n+1 It applies under the following conditions. • CMP output “H” when compare 0 is matched • CMP output “L” when compare 1 is matched • CMP output not inverted Count start condition Count stop condition Interrupt request generation timing TRFO00 to TRFO12 pin functions Counter value reset timing The TSTART bit in the TRFCR0 register is set to 1 (count starts). The TSTART bit in the TRFCR0 register is set to 0 (count stops). • When compare 0 match is generated [compare 0 interrupt] • When compare 1 match is generated [compare 1 interrupt] • When time RF overflows [timer RF interrupt]. Programmable I/O port or output-compare output In the following cases, the value in the TRF register is set to 0000h. • When the TSTART bit in the TRFCR0 register is set to 0 (count stops). • The CCLR bit in the TRFCR1 register is set to 1 (the TRF register is set to 0000h at compare 1 match) in the compare 1 matches. • The count value can be read out by reading the TRF register. • The value in the compare register can be read out by reading registers TRFM0 and TRFM1. Write to the TRF register is disabled • Output-compare output pin selected Either 1 pin or multiple pins among TRFO00 to TRFO02, or TRFO10 to TRFO12 (bits TRFOUT0 to TRFOUT5 in the TRFOUT register). • Output level at the compare match Selects “H”, “L”, inverted, or unchanged (bits TRFC14 to TRFC17 in the TRFCR1 register). • Output level inverted Selects output level inverted or not inverted (bits TRFOUT6 to TRFOUT7 in the TRFOUT register). • Output level at the count stops Selects “H”, “L”, or unchanged (bits TRFC05 to TRFC06 in the TRFCR0 register). • Timing to set the TRF register to 0000h Overflow or compare 1 match in the TRFM1 register (the CCLR bit in the TRFCR1 register). • TRFO11 pin select function P3_4 or P3_7 is selected by the TRFOSEL bit in the PINSR4 register. Read from timer Write to timer Select functions Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 208 of 318 R8C/2G Group 17. Timers Table 17.16 Output in Output Compare Mode (Example of TRFO00 Pin) Bit Setting Value TRFCR0 Register TRFOUT Register P1 Register TRFC06 TRFC05 TSTART TRFOUT6 TRFOUT0 P1_0 X X 1 0 1 1 X X 1 1 1 1 X X X 0 1 X X 0 1 1 1 1 0 0 0 0 1 X X X 1 1 1 1 1 0 0 1 1 1 TRFO00 Output Counting CMP output Inverted output of CMP output “L” output “H” output Count Holds output level stops before count stops “L” output “H” output X: 0 or 1 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 209 of 318 R8C/2G Group 17. Timers Value set in TRFM1 register Counter content (hex) Match Count starts Value set in TRFM0 register Match Match 0000h Time Set to 1 by a program TSTART bit in TRFCR0 register 1 0 Set to 0 when interrupt request is acknowledged, or set by a program. IR bit in CMP0IC register 1 0 Set to 0 when interrupt request is acknowledged, or set by a program. IR bit in CMP1IC register 1 0 When the count stops, the value is set to 0000h. TRFO00 output 1 0 TRFO10 output 1 0 The above applies under the following conditions. TRFC05 bit in TRFCR0 register = 1, TRFC06 bit in TRFCR0 register = 0 (“L” output when count stops) CCLR bit in TRFCR1 register = 1 (TRF register is set to 0000h at compare 1 match occurrence) TMOD bit in TRFCR1 register = 1 (output compare mode) Bits TRFC15 to TRFC14 in TRFCR1 register = 11b (CMP output level is set to “H” at compare 0 match) Bits TRFC17 to TRFC16 in TRFCR1 register = 10b (CMP output level is set to “L” at compare 1 match) TRFOUT6 bit in TRFOUT register = 0 (not inverted) TRFOUT7 bit in TRFOUT register = 1 (inverted) TRFOUT0 bit in TRFOUT register = 1 (TRFO00 output enabled) TRFOUT3 bit in TRFOUT register = 1 (TRFO10 output enabled) P1_0 bit in P1 register = 1 (“H”) P3_3 bit in P3 register = 1 (“H”) Figure 17.54 Operating Example in Output Compare Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 210 of 318 R8C/2G Group 17. Timers Set to 1 by a program P1_0 bit in P1 register 1 0 Set to 0 by a program P3_3 bit in P3 register 1 0 CMP output (internal signal) TRFO00 output TRFO10 output The above applies under the following conditions. TRFOUT0 bit in TRFOUT register = 1 (TRFO00 output enabled) TRFOUT3 bit in TRFOUT register = 1 (TRFO10 output enabled) TRFOUT6 bit in TRFOUT register = 0 (TRFO00 to TRFO02 output not inverted) TRFOUT7 bit in TRFOUT register = 1 (TRFO10 to TRFO12 output inverted) TSTART bit in TRFCR0 register = 1 (count starts) Figure 17.55 Operating Example in Output Compare Mode (“L” and “H” Held Output in Count Stops) In output compare mode, the same PWM waveform is output from all of pins TRFO00 to TRFO02 and TRFO10 to TRFO12 during count operation. Note that the output waveform can be inverted for pins TRFO00 to TRFO02 or for pins TRFO10 to TRFO12. The output can also be fixed at “L” or “H” for individual pins for a given period. The behavior when count operation stops can be selected from the following two options: the output level before the count stops is maintained, or output is fixed at “L” or “H”. The values in the compare i register can be read by reading the TRFMi (i = 0 or 1) register. Writing to the TRFMi register causes the values to be stored in the compare i register in the following timing: • If the TSTART bit is set to 0 (count stops) Values are stored simultaneously with the write to the TRFMi register. • If the TSTART bit is set to 1 (count starts) and the CCLR bit in the TRFCR1 register is set to 0 (free running) Values are stored when the TRF register (counter) overflows. • If the TSTART bit is set to 1 and the CCLR bit is set to 1 (TRF register set to 0000h at compare 1 match) Values are stored when the compare 1 and TRF register (counter) values match. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 211 of 318 R8C/2G Group 17. Timers 17.4.3 Notes on Timer RF • Access registers TRF, TRFM0, and TRFM1 in 16-bit units. Example of reading timer RF: MOV.W 0290H,R0 ; Read out timer RF • In input capture mode, a capture interrupt request is generated by inputting an edge selected by bits TRFC03 and TRFC04 in the TRFCR0 register even when the TSTART bit in the TRFCR0 register is set to 0 (count stops). Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 212 of 318 R8C/2G Group 18. Serial Interface 18. Serial Interface The serial interface consists of two channels (UART0 or UART2). Each UARTi (i = 0 or 2) has an exclusive timer to generate the transfer clock and operates independently. Figure 18.1 shows a UARTi (i = 0 or 2) Block Diagram. Figure 18.2 shows a UARTi Transmit/Receive Unit. UARTi has two modes: clock synchronous serial I/O mode and clock asynchronous serial I/O mode (UART mode). Figures 18.3 to 18.5 show the Registers Associated with UARTi. UARTi RXDi CLK1 to CLK0 = 00b f1 f8 f32 = 01b = 10b CKDIR = 0 Internal U0BRG register TXDi 1/16 UART reception Clock synchronous type Reception control circuit Receive clock 1/(n0+1) External CKDIR = 1 1/16 UART transmission Clock synchronous type Transmission control circuit CKDIR = 0 CKDIR = 1 Transmit clock Transmit/ receive unit CLKi CLK polarity switch circuit Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) Clock synchronous type (when internal clock is selected) 1/2 i = 0 or 2 CKDIR: Bit in UiMR register CLK0 to CLK1: Bits in UiC0 register Figure 18.1 UARTi (i = 0 or 2) Block Diagram Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 213 of 318 R8C/2G Group 18. Serial Interface 1SP PRYE = 0 Clock PAR disabled synchronous type Clock synchronous type UART (7 bits) UART (8 bits) UART (7 bits) UARTi receive register RXDi SP 2SP SP PAR PAR UART enabled PRYE = 1 UART (9 bits) Clock synchronous type UART (8 bits) UART (9 bits) 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UiRB register MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits MSB/LSB conversion circuit D8 D7 UART (8 bits) UART (9 bits) Clock synchronous type D6 D5 D4 D3 D2 D1 D0 UiTB register 2SP PRYE = 1 PAR enabled UART UART (9 bits) SP SP 1SP PAR Clock PAR disabled synchronous PRYE = 0 type 0 UART (7 bits) UART (8 bits) Clock synchronous type UART (7 bits) UARTi transmit register i = 0 or 2 SP: Stop bit PAR: Parity bit TXDi Figure 18.2 UARTi Transmit/Receive Unit Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 214 of 318 R8C/2G Group 18. Serial Interface UARTi Transmit/Receive Mode Register (i = 0 or 2) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol U0MR U2MR Bit Symbol SMD0 Address 00A0h 0160h Bit Name Serial I/O mode select bits After Reset 00h 00h Function b2 b1 b0 RW RW SMD1 SMD2 CKDIR STPS 0 0 0 : Serial interface disabled 0 0 1 : Clock synchronous serial I/O mode 1 0 0 : UART mode transfer data 7 bits long 1 0 1 : UART mode transfer data 8 bits long 1 1 0 : UART mode transfer data 9 bits long Other than above : Do not set. Internal/external clock select bit 0 : Internal clock 1 : External clock Stop bit length select bit Odd/even parity select bit 0 : 1 stop bit 1 : 2 stop bits Enable w hen PRYE = 1 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled Set to 0. RW RW RW RW PRY Parity enable bit Reserved bit RW PRYE — (b7) RW RW UARTi Bit Rate Register (i = 0 or 2)(1, 2, 3) b7 b0 Address 00A1h 0161h Function Assuming the set value is n, UiBRG divides the count source by n+1 NOTES: 1. Write to this register w hile the serial I/O is neither transmitting nor receiving. 2. Use the MOV instruction to w rite to this register. 3. After setting the CLK0 to CLK1 bits of the UiC0 register, w rite to the UiBRG register. Symbol U0BRG U2BRG After Reset Undefined Undefined Setting Range 00h to FFh RW WO Figure 18.3 Registers U0MR, U2MR and U0BRG, U2BRG Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 215 of 318 R8C/2G Group 18. Serial Interface UARTi Transmit Buffer Register (i = 0 or 2)(1, 2) (b15) b7 (b8) b0 b7 b0 Symbol U0TB U2TB — (b8-b0) — (b15-b9) Transmit data Address 00A3h-00A2h 0163h-0162h Function After Reset Undefined Undefined RW WO — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. NOTES: 1. When the transfer data length is 9 bits, w rite data to high byte first, then low byte. 2. Use the MOV instruction to w rite to this register. UARTi Transmit/Receive Control Register 0 (i = 0 or 2) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol U0C0 U2C0 Bit Symbol CLK0 CLK1 — (b2) TXEPT — (b4) NCH Address 00A4h 0164h Bit Name BRG count source select b1 b0 bits (1) 0 0 : Selects f1 0 1 : Selects f8 1 0 : Selects f32 1 1 : Do not set. Reserved bit Transmit register empty flag Set to 0. After Reset 00001000b 00001000b Function RW RW RW RW 0 : Data in transmit register (during transmit) 1 : No data in transmit register (transmit completed) RO Nothing is assigned. If necessary, set to 0. When read, the content is 0. Data output select bit CLK polarity select bit 0 : TXDi pin is for CMOS output 1 : TXDi pin is for N-channel open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge — RW CKPOL RW UFORM Transfer format select bit 0 : LSB first 1 : MSB first RW NOTE: 1. If the BRG count source is sw itched, set the UiBRG register again. Figure 18.4 Registers U0TB, U2TB and U0C0, U2C0 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 216 of 318 R8C/2G Group 18. Serial Interface UARTi Transmit/Receive Control Register 1 (i = 0 or 2) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol U0C1 U2C1 Bit Symbol TE TI RE RI UiIRS UiRRM — (b6) — (b7) Address 00A5h 0165h Bit Name Transmit enable bit Transmit buffer empty flag Receive enable bit Receive complete flag(1) UARTi transmit interrupt cause select bit UARTi continuous receive mode enable bit(2) Reserved bit After Reset 00000010b 00000010b Function 0 : Disables transmission 1 : Enables transmission 0 : Data in UiTB register 1 : No data in UiTB register 0 : Disables reception 1 : Enables reception 0 : No data in UiRB register 1 : Data in UiRB register 0 : Transmission buffer empty (TI=1) 1 : Transmission completed (TXEPT=1) 0 : Disables continuous receive mode 1 : Enables continuous receive mode Set to 0. RW RW RO RW RO RW RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. NOTES: 1. The RI bit is set to 0 w hen the higher byte of the UiRB register is read out. 2. Set the UiRRM bit to 0 (disables continuous receive mode) in UART mode. UARTi Receive Buffer Register (i = 0 or 2)(1) (b15) b7 (b8) b0 b7 b0 Symbol U0RB U2RB Bit Symbol — (b7-b0) — (b8) — (b11-b9) OER FER PER SUM Bit Name — — Address 00A7h-00A6h 0167h-0166h After Reset Undefined Undefined Function Receive data (D7 to D0) Receive data (D8) RW RO RO — RO RO RO RO Nothing is assigned. If necessary, set to 0. When read, the content is undefined. Overrun error flag(2) Framing error flag(2) Parity error flag(2) Error sum flag(2) 0 : No overrun error 1 : Overrun error 0 : No framing error 1 : Framing error 0 : No parity error 1 : Parity error 0 : No error 1 : Error NOTES: 1. Read out the UiRB register in 16-bit units. 2. Bits SUM, PER, FER, and OER are set to 0 (no error) w hen bits SMD2 to SMD0 in the UiMR register are set to 000b (serial interface disabled) or the RE bit in the UiC1 register is set to 0 (receive disabled). The SUM bit is set to 0 (no error) w hen bits PER, FER, and OER are set to 0 (no error). Bits PER and FER are set to 0 even w hen the higher byte of the UiRB register is read out. Also, bits PER and FER are set to 0 w hen reading the high-order byte of the UiRB register. Figure 18.5 Registers U0C1, U2C1 and U0RB, U2RB Page 217 of 318 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 R8C/2G Group 18. Serial Interface 18.1 Clock Synchronous Serial I/O Mode In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock. Table 18.1 lists the Clock Synchronous Serial I/O Mode Specifications. Table 18.2 lists the Registers Used and Settings in Clock Synchronous Serial I/O Mode(1). Table 18.1 Clock Synchronous Serial I/O Mode Specifications Specification • Transfer data length: 8 bits • CKDIR bit in UiMR register is set to 0 (internal clock): fi/(2(n+1)) fi = f1, f8, f32 n = value set in UiBRG register: 00h to FFh • The CKDIR bit is set to 1 (external clock): input from CLKi pin • Before transmission starts, the following requirements must be met(1) - The TE bit in the UiC1 register is set to 1 (transmission enabled) - The TI bit in the UiC1 register is set to 0 (data in the UiTB register) • Before reception starts, the following requirements must be met(1) - The RE bit in the UiC1 register is set to 1 (reception enabled) - The TE bit in the UiC1 register is set to 1 (transmission enabled) - The TI bit in the UiC1 register is set to 0 (data in the UiTB register) • When transmitting, one of the following conditions can be selected - The UiIRS bit is set to 0 (transmit buffer empty): When transferring data from the UiTB register to UARTi transmit register (when transmission starts). - The UiIRS bit is set to 1 (transmission completes): When completing data transmission from UARTi transmit register. • When receiving When data transfer from the UARTi receive register to the UiRB register (when reception completes). • Overrun error(2) This error occurs if the serial interface starts receiving the next data item before reading the UiRB register and receives the 7th bit of the next data. • CLK polarity selection Transfer data input/output can be selected to occur synchronously with the rising or the falling edge of the transfer clock. • LSB first, MSB first selection Whether transmitting or receiving data begins with bit 0 or begins with bit 7 can be selected. • Continuous receive mode selection Receive is enabled immediately by reading the UiRB register. Item Transfer data format Transfer clocks Transmit start conditions Receive start conditions Interrupt request generation timing Error detection Select functions i = 0 or 2 NOTES: 1. If an external clock is selected, ensure that the external clock is “H” when the CKPOL bit in the UiC0 register is set to 0 (transmit data output at falling edge and receive data input at rising edge of transfer clock), and that the external clock is “L” when the CKPOL bit is set to 1 (transmit data output at rising edge and receive data input at falling edge of transfer clock). 2. If an overrun error occurs, the receive data (b0 to b8) of the UiRB register will be undefined. The IR bit in the SiRIC register remains unchanged. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 218 of 318 R8C/2G Group 18. Serial Interface Table 18.2 Register UiTB UiRB UiBRG UiMR UiC0 Registers Used and Settings in Clock Synchronous Serial I/O Mode(1) Bit 0 to 7 0 to 7 OER 0 to 7 SMD2 to SMD0 CKDIR CLK1 to CLK0 TXEPT NCH CKPOL UFORM TE TI RE RI UiIRS UiRRM Set data transmission Data reception can be read Overrun error flag Set bit rate Set to 001b Function UiC1 Select the internal clock or external clock Select the count source in the UiBRG register Transmit register empty flag Select TXDi pin output mode Select the transfer clock polarity Select the LSB first or MSB first Set this bit to 1 to enable transmission/reception Transmit buffer empty flag Set this bit to 1 to enable reception Reception complete flag Select the UARTi transmit interrupt source Set this bit to 1 to use continuous receive mode i = 0 or 2 NOTE: 1. Set bits which are not in this table to 0 when writing to the above registers in clock synchronous serial I/O mode. Table 18.3 lists the I/O Pin Functions in Clock Synchronous Serial I/O Mode. The TXDi pin outputs “H” level between the operating mode selection of UARTi (i = 0 or 2) and transfer start. (If the NCH bit is set to 1 (N-channel open-drain output), this pin is in a high-impedance state.) Table 18.3 Pin Name TXD0 (P1_4) RXD0 (P1_5) I/O Pin Functions in Clock Synchronous Serial I/O Mode Function Output serial data Input serial data Selection Method (Outputs dummy data when performing reception only) PD1_5 bit in PD1 register = 0 (P1_5 can be used as an input port when performing transmission only) CKDIR bit in U0MR register = 0 CKDIR bit in U0MR register = 1 PD1_6 bit in PD1 register = 0 (Outputs dummy data when performing reception only) PD6_4 bit in PD6 register = 0 (P6_4 can be used as an input port when performing transmission only) CKDIR bit in U2MR register = 0 CKDIR bit in U2MR register = 1 PD6_5 bit in PD6 register = 0 CLK0 (P1_6) Output transfer clock Input transfer clock Output serial data Input serial data TXD2 (P6_3) RXD2 (P6_4) CLK2 (P6_5) Output transfer clock Input transfer clock Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 219 of 318 R8C/2G Group 18. Serial Interface • Example of transmit timing (when internal clock is selected) TC Transfer clock TE bit in UiC1 register TI bit in UiC1 register 1 0 1 0 Set data in UiTB register Transfer from UiTB register to UARTi transmit register TCLK Stop pulsing because the TE bit is set to 0 CLKi TXDi D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 TXEPT bit in UiC0 register 1 0 IR bit in SiTIC register 1 0 Set to 0 when interrupt request is acknowledged, or set by a program TC=TCLK=2(n+1)/fi fi: Frequency of UiBRG count source (f1, f8, f32) The above applies under the following settings: n: Setting value to UiBRG register • CKDIR bit in UiMR register = 0 (internal clock) • CKPOL bit in UiC0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock) • UiIRS bit in UiC1 register = 0 (an interrupt request is generated when the transmit buffer is empty) • Example of receive timing (when external clock is selected) RE bit in UiC1 register TE bit in UiC1 register TI bit in UiC1 register 1 0 1 0 1 0 Transfer from UiTB register to UARTi transmit register 1/fEXT Write dummy data to UiTB register CLKi Receive data is taken in RXDi RI bit in UiC1 register D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 1 0 1 0 Transfer from UARTi receive register to UiRB register Read out from UiRB register IR bit in SiRIC register Set to 0 when interrupt request is acknowledged, or set by a program The above applies under the following settings: • CKDIR bit in UiMR register = 1 (external clock) • CKPOL bit in UiC0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock) The following conditions are met when “H” is applied to the CLKi pin before receiving data: • TE bit in UiC1 register = 1 (enables transmit) • RE bit in UiC1 register = 1 (enables receive) • Write dummy data to the UiTB register fEXT: Frequency of external clock i = 0 or 2 Figure 18.6 Transmit and Receive Timing Example in Clock Synchronous Serial I/O Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 220 of 318 R8C/2G Group 18. Serial Interface 18.1.1 Polarity Select Function Figure 18.7 shows the Transfer Clock Polarity. Use the CKPOL bit in the UiC0 (i = 0 or 2) register to select the transfer clock polarity. • When the CKPOL bit in the UiC0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock) CLKi(1) TXDi D0 D1 D2 D3 D4 D5 D6 D7 RXDi D0 D1 D2 D3 D4 D5 D6 D7 • When the CKPOL bit in the UiC0 register = 1 (output transmit data at the rising edge and input receive data at the falling edge of the transfer clock) CLKi(2) TXDi D0 D1 D2 D3 D4 D5 D6 D7 RXDi D0 D1 D2 D3 D4 D5 D6 D7 NOTES: 1. When not transferring, the CLKi pin level is “H”. 2. When not transferring, the CLKi pin level is “L”. i = 0 or 2 Figure 18.7 Transfer Clock Polarity 18.1.2 LSB First/MSB First Select Function Figure 18.8 shows the Transfer Format. Use the UFORM bit in the UiC0 (i = 0 or 2) register to select the transfer format. • When UFORM bit in UiC0 register = 0 (LSB first)(1) CLKi TXDi D0 D1 D2 D3 D4 D5 D6 D7 RXDi D0 D1 D2 D3 D4 D5 D6 D7 • When UFORM bit in UiC0 register = 1 (MSB first)(1) CLKi TXDi D7 D6 D5 D4 D3 D2 D1 D0 RXDi D7 D6 D5 D4 D3 D2 D1 D0 NOTE: 1. The above applies when the CKPOL bit in the UiC0 register is set to 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock). i = 0 or 2 Figure 18.8 Transfer Format Page 221 of 318 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 R8C/2G Group 18. Serial Interface 18.1.3 Continuous Receive Mode Continuous receive mode is selected by setting the UiRRM (i = 0 or 2) bit in the UiC1 register to 1 (enables continuous receive mode). In this mode, reading the UiRB register sets the TI bit in the UiC1 register to 0 (data in the UiTB register). When the UiRRM bit is set to 1, do not write dummy data to the UiTB register by a program. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 222 of 318 R8C/2G Group 18. Serial Interface 18.2 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows data transmission and reception after setting the desired bit rate and transfer data format. Table 18.4 lists the UART Mode Specifications. Table 18.5 lists the Registers Used and Settings for UART Mode. Table 18.4 UART Mode Specifications Specification • Character bit (transfer data): Selectable among 7, 8 or 9 bits • Start bit: 1 bit • Parity bit: Selectable among odd, even, or none • Stop bit: Selectable among 1 or 2 bits • CKDIR bit in UiMR register is set to 0 (internal clock): fj/(16(n+1)) fj = f1, f8, f32 n = value set in UiBRG register: 00h to FFh • CKDIR bit is set to 1 (external clock): fEXT/(16(n+1)) fEXT: Input from CLKi pin, n = value set in UiBRG register: 00h to FFh • Before transmission starts, the following are required - TE bit in UiC1 register is set to 1 (transmission enabled) - TI bit in UiC1 register is set to 0 (data in UiTB register) • Before reception starts, the following are required - RE bit in UiC1 register is set to 1 (reception enabled) - Start bit detected • When transmitting, one of the following conditions can be selected - UiIRS bit is set to 0 (transmit buffer empty): When transferring data from the UiTB register to UARTi transmit register (when transmission starts). - UiIRS bit is set to 1 (transfer ends): When serial interfac.e completes transmitting data from the UARTi transmit register • When receiving When transferring data from the UARTi receive register to UiRB register (when reception ends). • Overrun error(1) This error occurs if the serial interface starts receiving the next data item before reading the UiRB register and receive the bit preceding the final stop bit of the next data item. • Framing error This error occurs when the set number of stop bits is not detected. • Parity error This error occurs when parity is enabled, and the number of 1’s in parity and character bits do not match the number of 1’s set. • Error sum flag This flag is set is set to 1 when an overrun, framing, or parity error is generated. Item Transfer data formats Transfer clocks Transmit start conditions Receive start conditions Interrupt request generation timing Error detection i = 0 or 2 NOTE: 1. If an overrun error occurs, the receive data (b0 to b8) of the UiRB register will be undefined. The IR bit in the SiRIC register remains unchanged. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 223 of 318 R8C/2G Group 18. Serial Interface Table 18.5 Register UiTB UiRB UiBRG UiMR Registers Used and Settings for UART Mode Bit 0 to 8 0 to 8 OER,FER,PER,SUM 0 to 7 SMD2 to SMD0 Set transmit data(1) Receive data can be read(1, 2) Error flag Set a bit rate Set to 100b when transfer data is 7 bits long Set to 101b when transfer data is 8 bits long Set to 110b when transfer data is 9 bits long Select the internal clock or external clock Select the stop bit Select whether parity is included and whether odd or even Select the count source for the UiBRG register Transmit register empty flag Select TXDi pin output mode Set to 0 LSB first or MSB first can be selected when transfer data is 8 bits long. Set to 0 when transfer data is 7 or 9 bits long. Set to 1 to enable transmit Transmit buffer empty flag Set to 1 to enable receive Receive complete flag Select the source of UARTi transmit interrupt Set to 0 Function UiC0 CKDIR STPS PRY, PRYE CLK0, CLK1 TXEPT NCH CKPOL UFORM TE TI RE RI UiIRS UiRRM UiC1 i = 0 or 2 NOTES: 1. The bits used for transmit/receive data are as follows: Bits 0 to 6 when transfer data is 7 bits long; bits 0 to 7 when transfer data is 8 bits long; bits 0 to 8 when transfer data is 9 bits long. 2. The following bits are undefined: Bits 7 and 8 when transfer data is 7 bits long; bit 8 when transfer data is 8 bits long. Table 18.6 lists the I/O Pin Functions in UART Mode. After the UARTi (i = 0 or 2) operating mode is selected, the TXDi pin outputs “H” level. (If the NCH bit is set to 1 (N-channel open-drain output), this pin is in a highimpedance state) until transfer starts.) Table 18.6 I/O Pin Functions in UART Mode Selection Method (Cannot be used as a port when performing reception only) PD1_5 bit in PD1 register = 0 (P1_5 can be used as an input port when performing transmission only) Programmable I/O Port CKDIR bit in U0MR register = 0 Input transfer clock CKDIR bit in U0MR register = 1 PD1_6 bit in PD1 register = 0 Output serial data (Cannot be used as a port when performing reception only) Input serial data PD6_4 bit in PD6 register = 0 (P6_4 can be used as an input port when performing transmission only) Programmable I/O Port CKDIR bit in U2MR register = 0 Input transfer clock CKDIR bit in U2MR register = 1 PD6_5 bit in PD6 register = 0 Pin name Function TXD0 (P1_4) Output serial data RXD0 (P1_5) Input serial data CLK0 (P1_6) TXD2 (P6_3) RXD2 (P6_4) CLK2 (P6_5) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 224 of 318 R8C/2G Group 18. Serial Interface • Transmit timing when transfer data is 8 bits long (parity enabled, 1 stop bit) TC Transfer clock TE bit in UiC1 register TI bit in UiC1 register 1 0 1 0 Write data to UiTB register Transfer from UiTB register to UARTi transmit register Start bit Parity Stop bit bit Stop pulsing because the TE bit is set to 0 TXDi ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 TXEPT bit in UiC0 register 1 0 IR bit SiTIC register 1 0 Set to 0 when interrupt request is acknowledged, or set by a program TC=16 (n + 1) / fj or 16 (n + 1) / fEXT The above timing diagram applies under the following conditions: • PRYE bit in UiMR register = 1 (parity enabled) fj: Frequency of UiBRG count source (f1, f8, f32) • STPS bit in UiMR register = 0 (1 stop bit) fEXT: Frequency of UiBRG count source (external clock) • UiIRS bit in UiC1 register = 1 (an interrupt request is generated when transmit completes) n: Setting value to UiBRG register i = 0 or 2 • Transmit timing when transfer data is 9 bits long (parity disabled, 2 stop bits) TC Transfer clock TE bit in UiC1 register TI bit in UiC1 register 1 0 1 0 Write data to UiTB register Transfer from UiTB register to UARTi transmit register Start bit Stop Stop bit bit TXDi ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 TXEPT bit in UiC0 register 1 0 IR bit in SiTIC register 1 0 Set to 0 when interrupt request is acknowledged, or set by a program The above timing diagram applies under the following conditions: • PRYE bit in UiMR register = 0 (parity disabled) • STPS bit in UiMR register = 1 (2 stop bits) • UiIRS bit in UiC1 register = 0 (an interrupt request is generated when transmit buffer is empty) TC=16 (n + 1) / fj or 16 (n + 1) / fEXT fj: Frequency of UiBRG count source (f1, f8, f32) fEXT: Frequency of UiBRG count source (external clock) n: Setting value to UiBRG register i = 0 or 2 Figure 18.9 Transmit Timing in UART Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 225 of 318 R8C/2G Group 18. Serial Interface • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) UiBRG output UiC1 register RE bit RXDi 1 0 Stop bit Start bit D0 D1 D7 Determined to be “L” Receive data taken in Transfer clock Reception triggered when transfer clock is generated by falling edge of start bit UiC1 register RI bit SiRIC register IR bit 1 0 1 0 Transferred from UARTi receive register to UiRB register Set to 0 when interrupt request is accepted, or set by a program The above timing diagram applies when the register bits are set as follows: • UiMR register PRYE bit = 0 (parity disabled) • UiMR register STPS bit = 0 (1 stop bit) i = 0 or 2 Figure 18.10 Receive Timing Example in UART Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 226 of 318 R8C/2G Group 18. Serial Interface 18.2.1 Bit Rate In UART mode, the bit rate is the frequency divided by the UiBRG (i = 0 or 2) register. UART mode • Internal clock selected UiBRG register setting value = fj Bit Rate × 16 -1 Fj: Count source frequency of the UiBRG register (f1, f8, or f32) • External clock selected UiBRG register setting value = fEXT Bit Rate × 16 -1 fEXT: Count source frequency of the UiBRG register (external clock) i = 0 or 2 Figure 18.11 Calculation Formula of UiBRG (i = 0 or 2) Register Setting Value Table 18.7 Bit Rate Setting Example in UART Mode (Internal Clock Selected) BRG Count Source f8 f8 f8 f1 f1 f1 f1 f1 f1 f1 System Clock = 8 MHz UiBRG Setting Value Actual Time (bps) 51 (33h) 1201.92 25 (19h) 2403.85 12 (0Ch) 4807.69 51 (33h) 9615.38 34 (22h) 14285.71 25 (19h) 19230.77 16 (10h) 29411.76 15 (0Fh) 31250.00 12 (0Ch) 38461.54 9 (09h) 50000.00 Error (%) 0.16 0.16 0.16 0.16 -0.79 0.16 2.12 0.00 0.16 -2.34 Bit Rate (bps) 1200 2400 4800 9600 14400 19200 28800 31250 38400 51200 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 227 of 318 R8C/2G Group 18. Serial Interface 18.3 Notes on Serial Interface • When reading data from the UiRB (i = 0 or 2) register either in the clock synchronous serial I/O mode or in the clock asynchronous serial I/O mode. Ensure the data is read in 16-bit units. When the high-order byte of the UiRB register is read, bits PER and FER in the UiRB register and the RI bit in the UiC1 register are set to 0. To check receive errors, read the UiRB register and then use the read data. Example (when reading receive buffer register): MOV.W 00A6H,R0 ; Read the U0RB register • When writing data to the UiTB register in the clock asynchronous serial I/O mode with 9-bit transfer data length, write data to the high-order byte first then the low-order byte, in 8-bit units. Example (when reading transmit buffer register): MOV.B #XXH,00A3H ; Write the high-order byte of U0TB register MOV.B #XXH,00A2H ; Write the low-order byte of U0TB register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 228 of 318 R8C/2G Group 19. Hardware LIN 19. Hardware LIN The hardware LIN performs LIN communication in cooperation with timer RA and UART0. 19.1 Features The hardware LIN has the features listed below. Figure 19.1 shows a Block Diagram of Hardware LIN. Master mode • Generates Synch Break • Detects bus collision Slave mode • Detects Synch Break • Measures Synch Field • Controls Synch Break and Synch Field signal inputs to UART0 • Detects bus collision NOTE: 1. The WakeUp function is detected by INT1. Hardware LIN RXD0 pin Synch Field control circuit TIOSEL = 0 RXD data LSTART bit SBE bit LINE bit RXD0 input control circuit TIOSEL = 1 Interrupt control circuit BCIE, SBIE, and SFIE bits UART0 UART0 transfer clock UART0 TE bit Timer RA output pulse MST bit TXD0 pin LINE, MST, SBE, LSTART, BCIE, SBIE, SFIE: Bits in LINCR register TIOSEL: Bit in TRAIOC register TE: Bit in U0C1 register UART0 TXD data Timer RA underflow signal Timer RA interrupt Timer RA Bus collision detection circuit Figure 19.1 Block Diagram of Hardware LIN Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 229 of 318 R8C/2G Group 19. Hardware LIN 19.2 Input/Output Pins The pin configuration of the hardware LIN is listed in Table 19.1. Table 19.1 Pin Configuration Abbreviation RXD0 TXD0 Input/Output Input Output Function Receive data input pin of the hardware LIN Transmit data output pin of the hardware LIN Name Receive data input Transmit data output Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 230 of 318 R8C/2G Group 19. Hardware LIN 19.3 Register Configuration The hardware LIN contains the registers listed below. These registers are detailed in Figures 19.2 and 19.3. • LIN Control Register (LINCR) • LIN Status Register (LINST) LIN Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol LINCR Bit Symbol SFIE Address 0106h Bit Name Synch Field measurementcompleted interrupt enable bit After Reset 00h Function 0 : Disables Synch Field measurementcompleted interrupt 1 : Enables Synch Field measurementcompleted interrupt RW RW SBIE BCIE RXDSF Synch Break detection interrupt 0 : Disables Synch Break detection interrupt enable bit 1 : Enables Synch Break detection interrupt Bus collision detection interrupt 0 : Disables bus collision detection interrupt enable bit 1 : Enables bus collision detection interrupt RXD0 input status flag 0 : RXD0 input enabled 1 : RXD0 input disabled RW RW RO LSTART Synch Break detection start bit(1) When this bit is set to 1, timer RA input is enabled and RXD0 input is disabled. When read, the content is 0. RXD0 input unmasking timing 0 : Unmasked after Synch Break is detected select bit (effective only in slave 1 : Unmasked after Synch Field measurement mode) is completed LIN operation mode setting bit(2) 0 : Slave mode (Synch Break detection circuit actuated) 1 : Master mode (timer RA output OR’ed w ith TXD0) 0 : Causes LIN to stop 1 : Causes LIN to start operating(3) RW SBE RW MST RW LINE LIN operation start bit RW NOTES: 1. After setting the LSTART bit, confirm that the RXDSF flag is set to 1 before Synch Break input starts. 2. Before changing LIN operation modes, temporarily stop the LIN operation (LINE bit = 0). 3. Inputs to timer RA and UART0 are prohibited immediately after this bit is set to 1. (Refer to Figure 19.5 Exam ple of Header Field Transm ission Flow chart (1) and Figure 19.9 Exam ple of Header Field Reception Flow chart (2) .) Figure 19.2 LINCR Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 231 of 318 R8C/2G Group 19. Hardware LIN LIN Status Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol LINST Bit Symbol SFDCT SBDCT BCDCT B0CLR B1CLR B2CLR — (b7-b6) Address 0107h Bit Name Synch Field measurementcompleted flag Synch Break detection flag Bus collision detection flag SFDCT bit clear bit SBDCT bit clear bit BCDCT bit clear bit After Reset 00h Function 1 show s Synch Field measurement completed. 1 show s Synch Break detected or Synch Break generation completed. 1 show s Bus collision detected. When this bit is set to 1, the SFDCT bit is set to 0. When read, the content is 0. When this bit is set to 1, the SBDCT bit is set to 0. When read, the content is 0. When this bit is set to 1, the BCDCT bit is set to 0. When read, the content is 0. RW RO RO RO RW RW RW — Nothing is assigned. If necessary, set to 0. When read, the content is 0. Figure 19.3 LINST Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 232 of 318 R8C/2G Group 19. Hardware LIN 19.4 19.4.1 Functional Description Master Mode Figure 19.4 shows typical operation of the hardware LIN when transmitting a header field in master mode. Figures 19.5 and 19.6 show an Example of Header Field Transmission Flowchart. When transmitting a header field, the hardware LIN operates as described below. (1) When the TSTART bit in the TRACR register for timer RA is set by writing 1 in software, the hardware LIN outputs “L” level from the TXD0 pin for the period that is set in registers TRAPRE and TRA for timer RA. (2) When timer RA underflows upon reaching the terminal count, the hardware LIN reverses the output of the TXD0 pin and sets the SBDCT flag in the LINST register to 1. Furthermore, if the SBIE bit in the LINCR register is set to 1, it generates a timer RA interrupt. (3) The hardware LIN transmits 55h via UART0. (4) The hardware LIN transmits an ID field via UART0 after it finishes sending 55h. (5) The hardware LIN performs communication for a response field after it finishes sending the ID field. Synch Break 1 0 1 0 1 0 (1) (2) (3) Synch Field IDENTIFIER TXD0 pin SBDCT flag in the LINST register IR bit in the TRAIC register Set by writing 1 to the B1CLR bit in the LINST register Cleared to 0 upon acceptance of interrupt request or by a program (4) (5) Shown above is the case where LINE = 1, MST = 1, SBIE = 1 Figure 19.4 Typical Operation when Sending a Header Field Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 233 of 318 R8C/2G Group 19. Hardware LIN Timer RA Set to timer mode Bits TMOD0 to TMOD2 in TRAMR register ← 000b Timer RA Set the pulse output level from low to start TEDGSEL bit in TRAIOC register ← 1 Timer RA Set the INT1/TRAIO pin to P1_5 TIOSEL bit in TRAIOC register ← 1 Timer RA Set the count source (f1, f2, f8, fOCO) Bits TCK0 to TCK2 in TRAMR register Timer RA Set the Synch Break width TRAPRE register TRA register UART0 Set to transmit/receive mode (Transfer data length: 8 bits, Internal clock, 1 stop bit, Parity disabled) U0MR register Set the BRG count source (f1, f8, f32) Bits CLK0 to CLK2 in U0C0 register Set the bit rate U0BRG register For the hardware LIN function, set the TIOSEL bit in the TRAIOC register to 1. Set the count source and registers TRA and TRAPRE as suitable for the Synch Break period. UART0 UART0 Set the BRG count source and U0BRG register as appropriate for the bit rate. Hardware LIN Set the LIN operation to stop LINCR register LINE bit ← 0 Hardware LIN Set to master mode MST bit in LINCR register ← 1 Hardware LIN Set the LIN operation to start LINE bit in LINCR register ← 1 Hardware LIN Set the register to enable interrupts (Bus collision detection, Synch Break detection, Synch Field measurement) Bits BCIE, SBIE, SFIE in LINCR register Hardware LIN Clear the status flags (Bus collision detection, Synch Break detection, Synch Field measurement) Bits B2CLR, B1CLR, B0CLR in LINST register ← 1 During master mode, the Synch Field measurementcompleted interrupt cannot be used. A Figure 19.5 Example of Header Field Transmission Flowchart (1) Page 234 of 318 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 R8C/2G Group 19. Hardware LIN A Timer RA Set the timer to start counting TSTART bit in TRACR register ← 1 Timer RA Read the count status flag TCSTF flag in TRACR register NO Timer RA generates Synch Break. If registers TRAPRE and TRA for timer RA do not need to be read or the register settings do not need to be changed after writing 1 to the TSTART bit, the procedure for reading TCSTF flag = 1 can be omitted. Zero to one cycle of the timer RA count source is required after timer RA starts counting before the TCSTF flag is set to 1. The timer RA interrupt may be used to terminate generation of Synch Break. One to two cycles of the CPU clock are required after Synch Break generation completes before the SBDCT flag is set to 1. After timer RA Synch Break is generated, the timer should be made to stop counting. If registers TRAPRE and TRA for timer RA do not need to be read or the register settings do not need to be changed after writing 0 to the TSTART bit, the procedure for reading TCSTF flag = 0 can be omitted. Zero to one cycle of the timer RA count source is required after timer RA stops counting before the TCSTF flag is set to 0. Transmit the Synch Field. TCSTF = 1 ? YES Hardware LIN Read the Synch Break detection flag SBDCT flag in LINST register NO SBDCT = 1 ? YES Timer RA Set the timer to stop counting TSTART bit in TRACR register ← 0 Timer RA Read the count status flag TCSTF flag in TRACR register NO TCSTF = 0 ? YES UART0 Communication via UART0 TE bit in U0C1 register ← 1 U0TB register ← 0055h UART0 Communication via UART0 U0TB register ← ID field Transmit the ID field. Figure 19.6 Example of Header Field Transmission Flowchart (2) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 235 of 318 R8C/2G Group 19. Hardware LIN 19.4.2 Slave Mode Figure 19.7 shows typical operation of the hardware LIN when receiving a header field in slave mode. Figure 19.8 through Figure 19.10 show an Example of Header Field Reception Flowchart. When receiving a header field, the hardware LIN operates as described below. (1) Synch Break detection is enabled by writing 1 to the LSTART bit in the LINCR register of the hardware LIN. (2) When “L” level is input for a duration equal to or greater than the period set in timer RA, the hardware LIN detects it as Synch Break. At this time, the SBDCT flag in the LINST register is set to 1. Furthermore, if the SBIE bit in the LINCR register is set to 1, the hardware LIN generates a timer RA interrupt. Then it goes to Synch Field measurement. (3) The hardware LIN receives a Synch Field (55h). At this time, it measures the period of the start bit and bits 0 to 6 by using timer RA. In this case, it is possible to select whether to input the Synch Field signal to RXD0 of UART0 by setting the SBE bit in the LINCR register accordingly. (4) The hardware LIN sets the SFDCT flag in the LINST register to 1 when it finishes measuring the Synch Field. Furthermore, if the SFIE bit in the LINCR register is set to 1, it generates a timer RA interrupt. (5) After it finishes measuring the Synch Field, calculate a transfer rate from the count value of timer RA and set to UART0 and registers TRAPRE and TRA of timer RA again. Then it receives an ID field via UART0. (6) The hardware LIN performs communication for a response field after it finishes receiving the ID field. Synch Break 1 0 1 0 1 0 1 0 1 0 1 0 (1) (2) (3) Synch Field IDENTIFIER RXD0 pin RXD0 input for UART0 RXDSF flag in the LINCR register SBDCT flag in the LINST register SFDCT flag in the LINST register IR bit in the TRAIC register Set by writing 1 to the LSTART bit in the LINCR register Set by writing 1 to the B1CLR bit in the LINST register Measure this period Cleared to 0 when Synch Field measurement finishes Set by writing 1 to the B0CLR bit in the LINST register Cleared to 0 upon acceptance of interrupt request or by a program (4) (5) (6) Shown above is the case where LINE = 1, MST = 0, SBE = 1, SBIE = 1, SFIE = 1 Figure 19.7 Typical Operation when Receiving a Header Field Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 236 of 318 R8C/2G Group 19. Hardware LIN Timer RA Set to pulse width measurement mode Bits TMOD0 to TMOD2 in the TRAMR register ← 011b Timer RA Set the pulse width measurement level low TEDGSEL bit in the TRAIOC register ← 0 Timer RA Set the INT1/TRAIO pin to P1_5 TIOSEL bit in the TRAIOC register ← 1 Timer RA Set the count source (f1, f2, f8, fOCO) Bits TCK0 to TCK2 in the TRAMR register Timer RA Set the Synch Break width TRAPRE register TRA register Hardware LIN Set the LIN operation to stop LINE bit in the LINCR register ← 0 Hardware LIN Set to slave mode MST bit in the LINCR register ← 0 Hardware LIN Set the LIN operation to start LINE bit in the LINCR register ← 1 Hardware LIN Set the RXD0 input unmasking timing (After Synch Break detection, or after Synch Field measurement) SBE bit in the LINCR register Hardware LIN Set the register to enable interrupts (Bus collision detection, Synch Break detection, Synch Field measurement) Bits BCIE, SBIE, SFIE in the LINCR register Select the timing at which to unmask the RXD0 input for UART0. If the RXD0 input is chosen to be unmasked after detection of Synch Break, the Synch Field signal is also input to UART0. For the hardware LIN function, set the TIOSEL bit in the TRAIOC register to 1. Set the count source and registers TRA and TRAPRE as appropriate for the Synch Break period. A Figure 19.8 Example of Header Field Reception Flowchart (1) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 237 of 318 R8C/2G Group 19. Hardware LIN A Hardware LIN Clear the status flags (Bus collision detection, Synch Break detection, Synch Field measurement) Bits B2CLR, B1CLR, B0CLR in the LINST register ← 1 Timer RA Set to start a pulse width measurement TSTART bit in the TRACR register ← 1 Timer RA Read the count status flag TCSTF flag in the TRACR register NO Zero to one cycle of the timer RA count source is required after timer RA starts counting before the TCSTF flag is set to 1. Hardware LIN waits until the RXD0 input for UART0 is masked. Do not apply “L” level to the RXD pin until the RXDSF flag reads 1 after writing 1 to the LSTART bit. This is because the signal applied during this time is input directly to UART0. One to two cycles of the CPU clock and zero to one cycle of the timer RA count source are required after the LSTART bit is set to 1 before the RXDSF flag is set to 1. After this, input to timer RA and UART0 is enabled. Hardware LIN detects a Synch Break. The interrupt of the timer RA may be used. When Synch Break is detected, timer RA is reloaded with the initially set count value. Even if the duration of the input “L” level is shorter than the set period, timer RA is reloaded with the initially set count value and waits until the next “L” level is input. One to two cycles of the CPU clock are required after Synch Break detection before the SBDCT flag is set to 1. When the SBE bit in the LINCR register is set to 0 (unmasked after Synch Break is detected), timer RA can be used in timer mode after the SBDCT flag in the LINST register is set to 1 and the RXDSF flag is set to 0. Timer RA waits until the timer starts counting. TCSTF = 1 ? YES Hardware LIN Set to start Synch Break detection LSTART bit in the LINCR register ← 1 Hardware LIN Read the RXD0 input status flag RXDSF flag in the LINCR register NO RXDSF = 1 ? YES Hardware LIN Read the Synch Break detection flag SBDCT flag in the LINST register NO SBDCT = 1 ? YES B Figure 19.9 Example of Header Field Reception Flowchart (2) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 238 of 318 R8C/2G Group 19. Hardware LIN B YES Hardware LIN Read the Synch Field measurementcompleted flag SFDCT flag in the LINST register NO SFDCT = 1 ? YES Hardware LIN measures the Synch Field. The interrupt of timer RA may be used (the SBDCT flag is set when the timer RA counter underflows upon reaching the terminal count). When the SBE bit in the LINCR register is set to 1 (unmasked after Synch Field measurement is completed), timer RA may be used in timer mode after the SFDCT bit in the LINST register is set to 1. Set a communication rate based on the Synch Field measurement result. UART0 Set the UART0 communication rate U0BRG register Timer RA Set the Synch Break width again TRAPRE register TRA register UART0 Communication via UART0 Clock asynchronous serial interface (UART) mode Transmit ID field Communication via UART0 (The SBDCT flag is set when the timer RA counter underflows upon reaching the terminal count.) Figure 19.10 Example of Header Field Reception Flowchart (3) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 239 of 318 R8C/2G Group 19. Hardware LIN 19.4.3 Bus Collision Detection Function The bus collision detection function can be used when UART0 is enabled for transmission (TE bit in the U0C1 register = 1). Figure 19.11 shows the Typical Operation when a Bus Collision is Detected. TXD0 pin 1 0 1 0 1 0 Set to 1 by a program 1 0 Set to 1 by a program 1 0 1 0 1 0 RXD0 pin Transfer clock LINE bit in the LINCR register TE bit in the U0C1 register BCDCT flag in the LINST register IR bit in the TRAIC register Set by writing 1 to the B2CLR bit in the LINST register Cleared to 0 upon acceptance of interrupt request or by a program Figure 19.11 Typical Operation when a Bus Collision is Detected Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 240 of 318 R8C/2G Group 19. Hardware LIN 19.4.4 Hardware LIN End Processing Figure 19.12 shows an Example of Hardware LIN Communication Completion Flowchart. Use the following timing for hardware LIN end processing: • If the hardware bus collision detection function is used Perform hardware LIN end processing after checksum transmission completes. • If the bus collision detection function is not used Perform hardware LIN end processing after header field transmission and reception complete. Timer RA Set the timer to stop counting TSTART bit in TRACR register ← 0 Read the count status flag TCSTF flag in TRACR register NO Set the timer to stop counting. Zero to one cycle of the timer RA count source is required after timer RA starts counting before the TCSTF flag is set to 1. Timer RA TCSTF = 0 ? YES UART0 Complete transmission via UART0 Hardware LIN Clear the status flags (Bus collision detection, Synch Break detection, Synch Field measurement) Bits B2CLR, B1CLR, B0CLR in the LINST register ← 1 Hardware LIN Set the LIN operation to stop LINE bit in the LINCR register ← 0 When the bus collision detection function is not used, end processing for the UART0 transmission is not required. After clearing hardware LIN status flag, stop the hardware LIN operation. Figure 19.12 Example of Hardware LIN Communication Completion Flowchart Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 241 of 318 R8C/2G Group 19. Hardware LIN 19.5 Interrupt Requests There are four interrupt requests that are generated by the hardware LIN: Synch Break detection, Synch Break generation completed, Synch Field measurement completed, and bus collision detection. These interrupts are shared with timer RA. Table 19.2 lists the Interrupt Requests of Hardware LIN. Table 19.2 Interrupt Requests of Hardware LIN Status Flag SBDCT Cause of Interrupt Generated when timer RA has underflowed after measuring the “L” level duration of RXD0 input, or when a “L” level is input for a duration longer than the Synch Break period during communication. Generated when “L” level output to TXD0 for the duration set by timer RA completes. SFDCT BCDCT Generated when measurement for 6 bits of the Synch Field by timer RA is completed. Generated when the RXD0 input and TXD0 output values differed at data latch timing while UART0 is enabled for transmission. Interrupt Request Synch Break detection Synch Break generation completed Synch Field measurement completed Bus collision detection Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 242 of 318 R8C/2G Group 19. Hardware LIN 19.6 Notes on Hardware LIN For the time-out processing of the header and response fields, use another timer to measure the duration of time with a Synch Break detection interrupt as the starting point. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 243 of 318 R8C/2G Group 20. Flash Memory 20. Flash Memory 20.1 Overview Rewrite operations to the flash memory can be performed in three modes: CPU rewrite, standard serial I/O, and parallel I/O. Table 20.1 lists the Flash Memory Performance (refer to Table 1.1 Specifications for R8C/2G Group for items not listed in Table 20.1). Table 20.1 Flash Memory Performance Specification 3 modes (CPU rewrite, standard serial I/O, and parallel I/O) Refer to Figure 20.1 Byte unit Block erase Program and erase control by software command Program ROM protection by FMR0 register 5 commands 100 times VCC = 2.7 to 5.5 V Standard serial I/O mode supported Parallel I/O mode supported Item Flash memory operating mode Division of erase block Programming method Erase method Programming and erasure control method Protection method Number of commands Programming and Blocks 0 and 1 (program erasure endurance(1) ROM) Programming and erasure voltage ID code check function ROM code protect NOTE: 1. Definition of programming and erasure endurance. The programming and erasure endurance is defined on a per-block basis. Table 20.2 Flash Memory Rewrite Modes CPU Rewrite Mode User ROM area is rewritten by executing software commands from the CPU. User ROM area User program Standard Serial I/O Mode User ROM area is rewritten by a dedicated serial programmer. User ROM area Standard boot program Parallel I/O Mode User ROM area is rewritten by a dedicated parallel programmer. User ROM area – Flash Memory Rewrite Mode Function Areas which can be rewritten Rewrite Program Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 244 of 318 R8C/2G Group 20. Flash Memory 20.2 Memory Map The flash memory contains a user ROM area and a boot ROM area (reserved area). Figure 20.1 shows the Flash Memory Block Diagram for R8C/2G Group. The user ROM area contains program ROM. The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite mode and standard serial I/O and parallel I/O modes. The rewrite control program (standard boot program) for standard serial I/O mode is stored in the boot ROM area before shipment. The boot ROM area and the user ROM area share the same address, but have separate memory areas. 32 Kbytes ROM product 08000h 24 Kbytes ROM product 0A000h 16 Kbytes ROM product 0C000h Block 0: 16 Kbytes 0FFFFh User ROM area 0FFFFh User ROM area 0BFFFh 0C000h Block 1: 8 Kbytes 0BFFFh 0C000h Block 0: 16 Kbytes 0FFFFh User ROM area 0E000h 0FFFFh Block 1: 16 Kbytes Program ROM Block 0: 16 Kbytes 8 Kbytes Boot ROM area (reserved area)(1) NOTE: 1. This area is for storing the standard boot program provided by Renesas Technology. Figure 20.1 Flash Memory Block Diagram for R8C/2G Group Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 245 of 318 R8C/2G Group 20. Flash Memory 20.3 Functions to Prevent Rewriting of Flash Memory Standard serial I/O mode has an ID code check function, and parallel I/O mode has a ROM code protect function to prevent the flash memory from being read or rewritten or erasure easily. 20.3.1 ID Code Check Function The ID code check function is used in standard serial I/O mode. Unless 3 bytes (addresses from 0FFFCh to 0FFFEh) of the reset vector are set to FFFFFFh, the ID codes sent from the serial programmer or the on-chip debugging emulator and the 7-byte ID codes written in the flash memory are checked to see if they match. If the ID codes do not match, the commands sent from the serial programmer or the on-chip debugging emulator are not acknowledged. For details of the ID code check function, refer to 14. ID Code Areas. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 246 of 318 R8C/2G Group 20. Flash Memory 20.3.2 ROM Code Protect Function The ROM protect function prevents the contents of the flash memory from being read, rewritten, or erased by means of the OFS register when parallel I/O mode is used. Figure 20.2 shows the OFS Register. Refer to 15. Option Function Select Area for details of the OFS register. The ROM code protect function is enabled by writing 0 to the ROMCP1 bit and 1 to the ROMCR bit. It disables reading or changing the contents of the on-chip flash memory. Once ROM code protect is enabled, the content in the internal flash memory cannot be rewritten in parallel I/O mode. To disable ROM code protect, erase the block including the OFS register with CPU rewrite mode or standard serial I/O mode. Option Function Select Register(1) b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 Symbol OFS Bit Symbol WDTON — (b1) ROMCR ROMCP1 — (b4) Address 0FFFFh Bit Name Watchdog timer start select bit Reserved bit ROM code protect disabled bit ROM code protect bit Reserved bit Voltage detection 0 circuit start bit(2) When Shipping FFh(3) Function 0 : Starts w atchdog timer automatically after reset 1 : Watchdog timer is inactive after reset Set to 1. 0 : ROM code protect disabled 1 : ROMCP1 enabled 0 : ROM code protect enabled 1 : ROM code protect disabled Set to 1. 0 : Voltage monitor 0 reset enabled after hardw are reset 1 : Voltage monitor 0 reset disabled after hardw are reset Set to 1. 0 : Count source protect mode enabled after reset 1 : Count source protect mode disabled after reset RW RW RW RW RW RW LVD0ON RW — (b6) Reserved bit RW Count source protect CSPROINI mode after reset select bit RW NOTES: 1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not w rite additions to the OFS register. 2. Setting the LVD0ON bit is only valid after a hardw are reset. To use the pow er-on reset, set the LVD0ON bit to 0 (voltage monitor 0 reset enabled after hardw are reset). 3. If the block including the OFS register is erased, FFh is set to the OFS register. Figure 20.2 OFS Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 247 of 318 R8C/2G Group 20. Flash Memory 20.4 CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU. Therefore, the user ROM area can be rewritten directly while the MCU is mounted on a board without using a ROM programmer. Execute the software command only to blocks in the user ROM area. Table 20.3 lists the Differences between EW0 Mode and EW1 Mode. Table 20.3 Differences between EW0 Mode and EW1 Mode EW0 Mode Single-chip mode RAM (Rewrite control program is executed after being transferred) User ROM EW1 Mode Single-chip mode User ROM or RAM Item Operating mode Areas in which a rewrite control program can be executed Areas which can be rewritten Software command restrictions None Modes after program or erase Modes after read status register CPU status during autowrite and auto-erase Flash memory status detection Read status register mode Read status register mode Operating User ROM However, blocks which contain a rewrite control program are excluded • Program and block erase commands Cannot be run on any block which contains a rewrite control program • Read status register command Cannot be executed Read array mode Do not execute this command CPU clock Hold state (I/O ports hold state before the command is executed) • Read bits FMR00, FMR06, and FMR07 Read bits FMR00, FMR06, and FMR07 in in the FMR0 register by a program the FMR0 register by a program • Execute the read status register command and read bits SR7, SR5, and SR4 in the status register. 5 MHz or below No restriction (on clock frequency to be used) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 248 of 318 R8C/2G Group 20. Flash Memory 20.4.1 Register Description The registers used in CPU rewrite mode are described. 20.4.1.1 FMR0 Register (FMR0) Figure 20.3 shows the FMR0 Register. Flash Memory Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol FMR0 Bit Symbol FMR00 FMR01 FMR02 Address 01B7h RY/BY s tatus flag CPU rew rite mode select bit(1) Blocks 0, 1 rew rite enable bit(2, 6) Flash memory stop bit(3, 5) ____ After Reset 00000001b Function 0 : Busy (w riting or erasing in progress) 1 : Ready 0 : CPU rew rite mode disabled 1 : CPU rew rite mode enabled 0 : Disables rew rite 1 : Enables rew rite 0 : Enables flash memory operation 1 : Stops flash memory (enters low -pow er consumption state and flash memory is reset) Set to 0. 0 : Completed successfully 1 : Terminated by error 0 : Completed successfully 1 : Terminated by error RW RO RW RW Bit Name FMSTP RW — (b5-b4) FMR06 FMR07 Reserved bits Program status flag(4) Erase status flag(4) RW RO RO NOTES: 1. To set this bit to 1, set it to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit to 0 and setting it to 1. Enter read array mode and set this bit to 0. 2. Set this bit to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1. Do not generate an interrupt betw een setting the bit to 0 and setting it to 1. 3. Set this bit by a program located in a space other than the flash memory. 4. This bit is set to 0 by executing the clear status command. 5. This bit is enabled w hen the FMR01 bit is set to 1 (CPU rew rite mode). When the FMR01 bit is set to 0, w riting 1 to the FMSTP bit causes the FMSTP bit to be set to 1. The flash memory does not enter low -pow er consumption state nor is it reset. 6. When setting the FMR01 bit to 0 (CPU rew rite mode disabled), the FMR02 bit is set to 0 (disables rew rite). Figure 20.3 FMR0 Register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 249 of 318 R8C/2G Group 20. Flash Memory • FMR00 Bit This bit indicates the operating status of the flash memory. The bits value is 0 during programming, erasure, or erase-suspend mode; otherwise, it is 1. • FMR01 Bit The MCU is made ready to accept commands by setting the FMR01 bit to 1 (CPU rewrite mode). • FMR02 Bit Rewriting of blocks 0 and 1 does not accept program or block erase commands if the FMR02 bit is set to 0 (rewrite disabled). Rewriting of blocks 0 and 1 is controlled by bits FMR15 and FMR16 if the FMR02 bit is set to 1 (rewrite enabled). • FMSTP Bit This bit is used to initialize the flash memory control circuits, and also to reduce the amount of current consumed by the flash memory. Access to the flash memory is disabled by setting the FMSTP bit to 1. Therefore, the FMSTP bit must be written to by a program transferred to the RAM. In the following cases, set the FMSTP bit to 1: - When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00 bit not reset to 1 (ready)) - To provide lower consumption in low-speed on-chip oscillator mode and low-speed clock mode. Note that when going to stop or wait mode while the CPU rewrite mode is disabled, the FMR0 register does not need to be set because the power for the flash memory is automatically turned off and is turned back on again after returning from stop or wait mode. • FMR06 Bit This is a read-only bit indicating the status of an auto-program operation. The bit is set to 1 when a program error occurs; otherwise, it is set to 0. For details, refer to the description in Table 20.4 Errors and FMR0 Register Status. • FMR07 Bit This is a read-only bit indicating the status of an auto-erase operation. The bit is set to 1 when an erase error occurs; otherwise, it is set to 0. Refer to Table 20.4 Errors and FMR0 Register Status for details. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 250 of 318 R8C/2G Group 20. Flash Memory Table 20.4 Errors and FMR0 Register Status Error Occurrence Condition FMR0 Register (Status Register) Status Error FMR07(SR5) FMR06(SR4) 1 1 Command sequence error 1 0 0 0 1 0 • When a command is not written correctly. • When D0h or FFh is not written in the 2nd byte of the block erase command.(1) • When the program command or block erase command is executed while rewriting is disabled by the FMR02 bit in the FMR0 register, or the FMR15 or FMR16 bit in the FMR1 register. • When an address not allocated in flash memory is input during erase command input • When attempting to erase the block for which rewriting is disabled during erase command input. • When an address not allocated in flash memory is input during write command input. • When attempting to write to a block for which rewriting is disabled during write command input. Erase error • When the block erase command is executed but auto-erasure does not complete correctly Program error • When the program command is executed but not auto-programming does not complete. Completed successfully – NOTE: 1. When FFh is written in the 2nd byte of the block erase command, the MCU enters read array mode, and the command code written in the 1st byte is disabled. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 251 of 318 R8C/2G Group 20. Flash Memory 20.4.1.2 FMR1 Register (FMR1) Figure 20.4 shows the FMR1 Register. Flash Memory Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 1 000 Symbol Address 01B5h FMR1 Bit Symbol Bit Name — Reserved bit (b0) FMR11 — (b4-b2) FMR15 FMR16 — (b7) EW1 mode select bit(1, 2) Reserved bits Block 0 rew rite disable bit(2,3) Block 1 rew rite disable bit(2,3) Reserved bit After Reset 1000000Xb Function When read, the content is undefined. 0 : EW0 mode 1 : EW1 mode Set to 0. 0 : Enables rew rite 1 : Disables rew rite 0 : Enables rew rite 1 : Disables rew rite Set to 1. RW RO RW RW RW RW RW NOTES: 1. To set this bit to 1, set it to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1 (CPU rew rite mode enable). Do not generate an interrupt betw een setting the bit to 0 and setting it to 1. 2. This bit is set to 0 by setting the FMR01 bit in the FMR0 register to 0 (CPU rew rite mode disabled). 3. While the FMR01 bit is set to 1 (CPU rew rite mode enabled), bits FMR15 and FMR16 can be w ritten to. To set this bit to 0, set it to 0 immediately after setting it first to 1. To set this bit to 1, set it to 1. Figure 20.4 FMR1 Register • FMR11 Bit Setting this bit to 1 (EW1 mode) places the MCU in EW1 mode. • FMR15 Bit When the FMR02 bit is set to 1 (rewrite enabled) and the FMR15 bit is set to 0 (rewrite enabled), block 0 accepts program and block erase commands. • FMR16 Bit When the FMR02 bit is set to 1 (rewrite enabled) and the FMR16 bit is set to 0 (rewrite enabled), block 1 accepts program and block erase commands. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 252 of 318 R8C/2G Group 20. Flash Memory 20.4.1.3 FMR4 Register (FMR4) Figure 20.5 shows the FMR4 Register. Flash Memory Control Register 4 b7 b6 b5 b4 b3 b2 b1 b0 000 Symbol Address 01B3h FMR4 Bit Symbol Bit Name — Reserved bits (b2-b0) FMR43 FMR44 — (b5) FMR46 FMR47 Erase command flag Program command flag After Reset 01000000b Function Set to 0. 0 : Erase not executed 1 : Erase execution in progress 0 : Program not executed 1 : Program execution in progress RW RW RO RO — RO RW Nothing is assigned. If necessary, set to 0. When read, the content is 0. Read status flag Low -current-consumption read mode enable bit (1, 2, 3) 0 : Disables reading 1 : Enables reading 0 : Disable 1 : Enable NOTES: 1. To set this bit to 1, set it to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit to 0 and setting it to 1. 2. In high-speed on-chip oscillator mode, set the FMR47 bit to 0 (disabled). 3. Set the FMR01 bit to 0 (CPU rew rite mode disabled) in low -current-consumption read mode. Figure 20.5 FMR4 Register • FMR43 Bit When the auto-erase operation starts, the FMR43 bit is set to 1 (erase execution in progress). When the auto-erase operation ends, the FMR43 bit is set to 0 (erase not executed). • FMR44 Bit When the auto-program operation starts, the FMR44 bit is set to 1 (program execution in progress). When the auto-program operation ends, the FMR44 bit is set to 0 (program not executed). • FMR46 Bit The FMR46 bit is set to 0 (reading disabled) during auto-program or auto-erase execution. Do not access the flash memory while this bit is set to 0. • FMR47 Bit Current consumption when reading the flash memory can be reduced by setting the FMR47 bit to 1 (enabled) in low-speed clock mode and low-speed on-chip oscillator mode. Refer to 21.2.10 Low-Current-Consumption Read Mode for details of the handling procedure. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 253 of 318 R8C/2G Group 20. Flash Memory 20.4.2 Status Check Procedure When an error occurs, bits FMR06 to FMR07 in the FMR0 register are set to 1, indicating the occurrence of an error. Therefore, checking these status bits (full status check) can be used to determine the execution result. Figure 20.6 shows the Full Status Check and Handling Procedure for Individual Errors. Command sequence error Full status check Execute the clear status register command (set these status flags to 0) FMR06 = 1 and FMR07 = 1? No Re-execute the command Yes Command sequence error Check if command is properly input FMR07 = 1? No Yes Erase error Erase error Execute the clear status register command (set these status flags to 0) Erase command re-execution times ≤ 3 times? FMR06 = 1? No Yes Program error Yes Re-execute block erase command No Block targeting for erasure cannot be used Program error Execute the clear status register command (set these status flags to 0) Full status check completed Specify the other address besides the write address where the error occurs for the program address(1) NOTE: 1. To rewrite to the address where the program error occurs, check if the full status check is complete normally and write to the address after the block erase command is executed. Re-execute program command Figure 20.6 Full Status Check and Handling Procedure for Individual Errors Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 254 of 318 R8C/2G Group 20. Flash Memory 20.4.3 EW0 Mode The MCU enters CPU rewrite mode and software commands can be acknowledged by setting the FMR01 bit in the FMR0 register to 1 (CPU rewrite mode enabled). In this case, since the FMR11 bit in the FMR1 register is set to 0, EW0 mode is selected. Use software commands to control program and erase operations. The FMR0 register or the status register can be used to determine when program and erase operations complete. Figure 20.7 shows How to Set and Exit EW0 Mode. EW0 Mode Operating Procedure Rewrite control program Write 0 to the FMR01 bit before writing 1 (CPU rewrite mode enabled)(2) Set registers(1) CM0 and CM1 Execute software commands Transfer a rewrite control program which uses CPU rewrite mode to the RAM. Execute the read array command(3) Jump to the rewrite control program which has been transferred to the RAM. (The subsequent process is executed by the rewrite control program in the RAM.) Write 0 to the FMR01 bit (CPU rewrite mode disabled) Jump to a specified address in the flash memory NOTES: 1. Select 5 MHz or below for the CPU clock by the CM06 bit in the CM0 register and bits CM16 to CM17 in the CM1 register. 2. To set the FMR01 bit to 1, write 0 to the FMR01 bit before writing 1. Do not generate an interrupt between writing 0 and 1. Write to the FMR01 bit in the RAM. 3. Disable the CPU rewrite mode after executing the read array command. Figure 20.7 How to Set and Exit EW0 Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 255 of 318 R8C/2G Group 20. Flash Memory 20.4.3.1 Software Commands There are five types of software commands: • Read array • Read status register • Clear status register • Program • Block erase Figure 20.8 shows Software Command Status Transition Diagram in EW0 Mode. Read array mode CPU rewrite disabled Reset (FMR46 = 1 Reading enabled) No command required Reading only available Write 1 to the FMR01 bit immediately after writing 0. FMR01 = 0 CPU rewrite mode (EW0 mode) Read array mode (FMR46 = 1 Reading enabled) (Program command) 40h (Read status register command) (Read array command) 70h (Block erase command) 20h (Clear status register command) 50h FFh Program (Read array command) FFh Clear ends (Programming starts) Write data Read status register mode Non-D0h and non-FFh Block erase D0h Clear status register (Block erasure starts) Auto-program (FMR46 = 0 Reading disabled) Auto-erase (FMR46 = 0 Reading disabled) Auto-programming completed Auto-erasure completed Figure 20.8 Software Command Status Transition Diagram in EW0 Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 256 of 318 R8C/2G Group 20. Flash Memory • Read Array Command The read array command reads the flash memory. When FFh is written to an address in the user ROM area, the MCU enters read array mode. In this mode, the contents of the specified address can be read. Read array mode continues until other commands are written. The MCU enters this mode after a reset is deasserted. • Read Status Register Command The read status register command is used to read the status register. Figure 20.9 shows Status Register. The status register indicates the operating status of the flash memory and whether an erase or program operation has completed normally or in error (refer to Table 20.4 Errors and FMR0 Register Status). When 70h is written to an address in the user ROM area, the MCU enters read status register mode. When the address in the user ROM area is read subsequently, the status register can be read. The MCU remains in read status register mode until the next read array command is written. The status of the status register can be determined by reading bits FMR00, FMR06, and FMR07 in the FMR0 register. D7 D6 D5 D4 D3 D2 D1 D0 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 Status register FMR0 register FMR06 bit FMR07 bit FMR00 bit D0 to D7: These indicate the read data buses when the read status command is executed. Figure 20.9 Status Register • Clear Status Register Command The clear status register command sets the status register to 0. When 50h is written to an address in the user ROM area, bits FMR07 and FMR06 in the FMR0 register and bits SR5 and SR4 in the status register are set to 00b. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 257 of 318 R8C/2G Group 20. Flash Memory • Program Command The program command writes data to the flash memory in 1-byte units. When 40h is written and then data is written to the write address, an auto-program operation (data program and verify) starts. The FMR00 bit in the FMR0 register can be used to determine whether auto-programming has completed. The FMR00 bit is set to 0 during auto-programming and set to 1 when auto-programming completes. The FMR06 bit in the FMR0 register can be used to determine the result of auto-programming after it has been finished (refer to 20.4.2 Status Check Procedure). Do not write additions to the already programmed addresses. Also, when the FMR02 bit in the FMR0 register is set to 0 (rewrite disabled), or the FMR02 bit is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1 register is set to 1 (rewrite disabled), program commands targeting block 0 are not acknowledged. When the FMR 16 bit is set to 1 (rewrite disabled), program commands targeting block 1 are not acknowledged. Figure 20.10 shows the Program Command in EW0 Mode. In EW0 mode, the MCU enters read status register mode at the same time auto-programming starts and the status register can be read. In this case, the MCU remains in read status register mode until the next read array command is written. Start Write the command code 40h to the write address Write data to the write address FMR00 = 1? Yes Full status check No Program completed Figure 20.10 Program Command in EW0 Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 258 of 318 R8C/2G Group 20. Flash Memory • Block Erase When 20h is first written and then D0h is written to a given block address, an auto-erase operation (erase and verify) of the specified block starts. The FMR00 bit in the FMR0 register can be used to determine whether auto-erasure has completed. The FMR00 bit is set to 0 during auto-erasure and set to 1 when auto-erasure completes. The FMR07 bit in the FMR0 register can be used to determine the result of auto-erasure after auto-erasure has completed (refer to 20.4.2 Status Check Procedure). Also, when the FMR02 bit in the FMR0 register is set to 0 (rewrite disabled), or the FMR02 bit is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1 register is set to 1 (rewrite disabled), block erase commands targeting block 0 are not acknowledged. When the FMR16 bit is set to 1 (rewrite disabled), block erase commands targeting block 1 are not acknowledged. In EW0 mode, the MCU enters read status register mode at the same time auto-erasure starts and the status register can be read. In this case, the MCU remains in read status register mode until the next read array command is written. Figure 20.11 shows the Block Erase Command in EW0 Mode. If the programming and erasure endurance is n (n = 100, 1000, or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1-Kbyte block, and then the block is erased, the erase count stands at one. When performing 100 or more rewrites, the actual erase count can be reduced by executing programming operations in such a way that all blank areas are used before performing an erase operation. Avoid rewriting only particular blocks and try to average out the programming and erasure endurance of the blocks. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. Start Write the command code 20h Write D0h to any block address FMR00 = 1? Yes Full status check No Block erase completed Figure 20.11 Block Erase Command in EW0 Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 259 of 318 R8C/2G Group 20. Flash Memory 20.4.3.2 EW0 Mode Interrupts In EW0 mode, maskable interrupts can be used by allocating a vector in RAM. Table 20.5 lists the EW0 Mode Interrupts. Refer to 20.7.1.3 Non-Maskable Interrupts for details of the non-maskable interrupt. Table 20.5 EW0 Mode Interrupts When Maskable Interrupt Request is Acknowledged Interrupt handling is executed. Status During auto-erasure Auto-programming Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 260 of 318 R8C/2G Group 20. Flash Memory 20.4.4 EW1 Mode The MCU is switched to EW1 mode by setting the FMR11 bit to 1 (EW1 mode) after setting the FMR01 bit to 1 (CPU rewrite mode enabled). The FMR0 register can be used to determine when program and erase operations complete. Figure 20.12 shows How to Set and Exit EW1 Mode. EW1 Mode Operating Procedure Program in ROM Write 0 to the FMR01 bit before writing 1 (CPU rewrite mode enabled)(1) Write 0 to the FMR11 bit before writing 1 (EW1 mode) Execute software commands Write 0 to the FMR01 bit (CPU rewrite mode disabled) NOTE: 1. To set the FMR01 bit to 1, write 0 to the FMR01 bit before writing 1. Do not generate an interrupt between writing 0 and 1. Figure 20.12 How to Set and Exit EW1 Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 261 of 318 R8C/2G Group 20. Flash Memory 20.4.4.1 Software Commands There are four types of software commands: • Read array • Clear status register • Program • Block erase Do not execute read status register command in EW1 mode. Figure 20.13 shows Software Command Status Transition Diagram in EW1 Mode. CPU rewrite disabled Reset Read array mode (FMR46 = 1 Reading enabled) Write 1 to the FMR01 bit immediately after writing 0, and write 1 to the FMR11 bit immediately after writing 0. No command required Reading only available FMR01 = 0 CPU rewrite mode (EW1 mode) Read array mode (FMR46 = 1 Reading enabled) (Program command) (Read array command) 40h FFh (Block erase command) 20h (Clear status register command) 50h Clear ends Program Block erase Clear status register (Programming starts) Write data (Block erasure starts) D0h Auto-program (FMR46 = 0 Reading disabled) Auto-erase (FMR46 = 0 Reading disabled) CPU stops Auto-programming completed Auto-erasure completed Figure 20.13 Software Command Status Transition Diagram in EW1 Mode • Read Array Command The read array command reads the flash memory. When FFh is written to an address in the user ROM area, the MCU enters read array mode. In this mode, the contents of the specified address can be read. Read array mode continues until other commands are written. The MCU enters this mode after a reset is deasserted. • Clear Status Register Command The clear status register command sets the status register to 0. When 50h is written to an address in the user ROM area, bits FMR07 and FMR06 in the FMR0 register and bits SR5 and SR4 in the status register are set to 00b. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 262 of 318 R8C/2G Group 20. Flash Memory • Program Command The program command writes data to the flash memory in 1-byte units. When 40h is written and then data is written to the write address, an auto-program operation (data program and verify) starts. The FMR00 bit in the FMR0 register can be used to determine whether auto-programming has completed. The FMR00 bit is set to 0 during auto-programming and set to 1 when auto-programming completes. The FMR06 bit in the FMR0 register can be used to determine the result of auto-programming after it has been finished (refer to 20.4.2 Status Check Procedure). Do not write additions to the already programmed addresses. Also, when the FMR02 bit in the FMR0 register is set to 0 (rewrite disabled), or the FMR02 bit is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1 register is set to 1 (rewrite disabled), program commands targeting block 0 are not acknowledged. When the FMR 16 bit is set to 1 (rewrite disabled), program commands targeting block 1 are not acknowledged. In EW1 mode, do not execute this command for any address which a rewrite control program is allocated. Figure 20.14 shows the Program Command in EW1 Mode. Start Write the command code 40h to the write address Write data to the write address FMR00 = 1? Yes Full status check No Program completed Figure 20.14 Program Command in EW1 Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 263 of 318 R8C/2G Group 20. Flash Memory • Block Erase When 20h is first written and then D0h is written to a given block address, an auto-erase operation (erase and verify) of the specified block starts. The FMR00 bit in the FMR0 register can be used to determine whether auto-erasure has completed. The FMR00 bit is set to 0 during auto-erasure and set to 1 when auto-erasure completes. The FMR07 bit in the FMR0 register can be used to determine the result of auto-erasure after auto-erasure has completed (refer to 20.4.2 Status Check Procedure). Also, when the FMR02 bit in the FMR0 register is set to 0 (rewrite disabled), or the FMR02 bit is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1 register is set to 1 (rewrite disabled), block erase commands targeting block 0 are not acknowledged. When the FMR16 bit is set to 1 (rewrite disabled), block erase commands targeting block 1 are not acknowledged. Do not execute this command for any address to which a rewrite control program is allocated. Figure 20.15 shows the Block Erase Command in EW1 Mode. If the programming and erasure endurance is n (n = 100, 1000, or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1-Kbyte block, and then the block is erased, the erase count stands at one. When performing 100 or more rewrites, the actual erase count can be reduced by executing programming operations in such a way that all blank areas are used before performing an erase operation. Avoid rewriting only particular blocks and try to average out the programming and erasure endurance of the blocks. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. Start Write the command code 20h Write D0h to any block address FMR00 = 1? Yes Full status check No Block erase completed Figure 20.15 Block Erase Command in EW1 Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 264 of 318 R8C/2G Group 20. Flash Memory 20.4.4.2 EW1 Mode Interrupts In EW1 mode, maskable interrupts can be used. Table 20.6 lists the EW1 Mode Interrupts. Refer to 20.7.1.3 Non-Maskable Interrupts for details of the nonmaskable interrupt. Table 20.6 EW1 Mode Interrupts When Maskable Interrupt Request is Acknowledged Auto-erasure has priority and the interrupt request acknowledgement is put on standby. Interrupt handling is executed after auto-erasure completes. Auto-programming has priority and the interrupt request acknowledgement is put on standby. Interrupt handling is executed after auto-programming completes. Status During auto-erasure During auto- programming Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 265 of 318 R8C/2G Group 20. Flash Memory 20.5 Standard Serial I/O Mode In standard serial I/O mode, the user ROM area can be rewritten while the MCU is mounted on-board by using a serial programmer which is suitable for the MCU. There are three types of standard serial I/O modes: • Standard serial I/O mode 1 ............Clock synchronous serial I/O used to connect with a serial programmer • Standard serial I/O mode 2 ............Clock asynchronous serial I/O used to connect with a serial programmer • Standard serial I/O mode 3 ............Special clock asynchronous serial I/O used to connect with a serial programmer This MCU uses Standard serial I/O mode 3. Refer to Appendix 2. Connection Examples with On-Chip Debugging Emulator. Contact the manufacturer of your serial programmer for details. Refer to the user’s manual of your serial programmer for instructions on how to use it. Table 20.7 lists the Pin Functions (Flash Memory Standard Serial I/O Mode 3), and Figure 20.16 shows an Example of Pin Processing in Standard Serial I/O Mode 3. After processing the pins shown in Table 20.7 and rewriting the flash memory using the programmer, apply “H” to the MODE pin and reset the hardware to run a program in the flash memory in single-chip mode. 20.5.1 ID Code Check Function The ID code check function determines whether the ID codes sent from the serial programmer and those written in the flash memory match. Refer to 14. ID Code Areas for details of the ID code check. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 266 of 318 R8C/2G Group 20. Flash Memory Table 20.7 Pin VCC,VSS RESET P4_3/XCIN P4_4/XCOUT Pin Functions (Flash Memory Standard Serial I/O Mode 3) Name Power input Reset input P4_3 input/clock input P4_4 output/clock output Input port P0 Input port P1 Input port P3 Input port P4 Input port P6 MODE I/O Description Apply the voltage guaranteed for programming and erasure to the VCC pin and 0 V to the VSS pin. Reset input pin. Connect crystal oscillator between pins XCIN and XCOUT when connecting external oscillator. To use P4_3 as an input port, input a “H” or “L” level signal or leave the pin open. To use P4_4 as an output port, leave the pin open. Input a “H” or “L” level signal or leave the pin open. I I O P0_4 to P0_7 P1_0 to P1_7 P3_0 to P3_7 P4_5 P6_0, P6_3 to P6_6 MODE I I I I I I/O Serial data I/O pin. Connect to the flash programmer. MCU MODE I/O MODE VCC Reset input RESET User reset signal VSS NOTES: 1. Controlled pins and external circuits vary depending on the programmer. Refer to the programmer manual for details. 2. In this example, modes are switched between single-chip mode and standard serial I/O mode by connecting a programmer. 3. When operating with the on-chip oscillator clock, it is not necessary to connect an oscillating circuit. Figure 20.16 Example of Pin Processing in Standard Serial I/O Mode 3 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 267 of 318 R8C/2G Group 20. Flash Memory 20.6 Parallel I/O Mode Parallel I/O mode is used to input and output software commands, addresses and data necessary to control (read, program, and erase) the on-chip flash memory. Use a parallel programmer which supports this MCU. Contact the manufacturer of the parallel programmer for more information, and refer to the user’s manual of the parallel programmer for details on how to use it. ROM areas shown in Figure 20.1 can be rewritten in parallel I/O mode. 20.6.1 ROM Code Protect Function The ROM code protect function disables the reading and rewriting of the flash memory. (Refer to 20.3.2 ROM Code Protect Function.) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 268 of 318 R8C/2G Group 20. Flash Memory 20.7 20.7.1 Notes on Flash Memory CPU Rewrite Mode Operating Speed 20.7.1.1 Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit in the CM0 register and bits CM16 to CM17 in the CM1 register. This does not apply to EW1 mode. 20.7.1.2 Prohibited Instructions The following instructions cannot be used in EW0 mode because they reference data in the flash memory: UND, INTO, and BRK. 20.7.1.3 Non-Maskable Interrupts • EW0 Mode Once a watchdog timer, voltage monitor1, voltage monitor 2, comparator 1, or comparator 2 interrupt request is acknowledged, auto-erasure or auto-programming is forcibly stopped immediately and the flash memory is reset. Interrupt handling starts after a fixed period and the flash memory restarts. As the block during auto-erasure or the address during auto-programming is forcibly stopped, the normal value may not be readable. Execute auto-erasure again and ensure it completes normally. The watchdog timer does not stop during command operation, so that interrupt requests may be generated. Initialize the watchdog timer regularly. Do not use the address match interrupt while a command is being executed because the vector of the address match interrupt is allocated in ROM. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is allocated in block 0. • EW1 Mode Once a watchdog timer, voltage monitor1, voltage monitor 2, comparator 1, or comparator 2 interrupt request is acknowledged, auto-erasure or auto-programming is forcibly stopped immediately and the flash memory is reset. Interrupt handling starts after a fixed period and the flash memory restarts. As the block during auto-erasure or the address during auto-programming is forcibly stopped, the normal value may not be readable. Execute auto-erasure again and ensure it completes normally. The watchdog timer does not stop even during command operation, so that interrupt requests may be generated. Initialize the watchdog timer by using the erase-suspend function. Do not use the address match interrupt while a command is being executed because the vector of the address match interrupt is allocated in ROM. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is allocated in block 0. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 269 of 318 R8C/2G Group 20. Flash Memory 20.7.1.4 How to Access Write 0 before writing 1 when setting Bits FMR01, FMR02 in the FMR0 register, or FMR11 bit in the FMR1 register to 1. Do not generate an interrupt between writing 0 and 1. 20.7.1.5 Rewriting User ROM Area In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be rewritten correctly. In this case, use standard serial I/O mode. 20.7.1.6 Program Do not write additions to the already programmed address. 20.7.1.7 Program and Erase Voltage for Flash Memory To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform programming and erasure at less than 2.7 V. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 270 of 318 R8C/2G Group 21. Reducing Power Consumption 21. Reducing Power Consumption 21.1 Overview This chapter describes key points and processing methods for reducing power consumption. 21.2 Key Points and Processing Methods for Reducing Power Consumption Key points for reducing power consumption are shown below. They should be referred to when designing a system or creating a program. 21.2.1 Voltage Detection Circuit When voltage monitor 1 and comparator 1 are not used, set the VCA26 bit in the VCA2 register to 0 (voltage detection 1 circuit disabled). When voltage monitor 2 and comparator 2 are not used, set the VCA27 bit in the VCA2 register to 0 (voltage detection 2 circuit disabled). If the power-on reset and voltage monitor 0 reset are not used, set the VCA25 bit in the VCA2 register to 0 (voltage detection 0 circuit disabled). 21.2.2 Ports Even after the MCU enters wait mode or stop mode, the states of the I/O ports are retained. Current flows into the output ports in the active state, and shoot-through current flows into the input ports in the high-impedance state. Unnecessary ports should be set to input and fixed to a stable electric potential before the MCU enters wait mode or stop mode. 21.2.3 Clocks Power consumption generally depends on the number of the operating clocks and their frequencies. The fewer the number of operating clocks or the lower their frequencies, the more power consumption decreases. Unnecessary clocks should be stopped accordingly. Stopping low-speed on-chip oscillator oscillation: CM14 bit in CM1 register Stopping high-speed on-chip oscillator oscillation: HRA00 bit in HRA0 register 21.2.4 Selecting Oscillation Drive Capacity Set the drive capacity of the XCIN clock oscillation circuit to “LOW”. Confirm that the circuit oscillates stably while it is in the “LOW” state. Selecting XCIN-XCOUT drive capacity: CM03 bit in CM0 register 21.2.5 Wait Mode, Stop Mode Power consumption can be reduced in wait mode and stop mode. Refer to 11.4 Power Control for details. 21.2.6 Stopping Peripheral Function Clocks If the peripheral function f1, f2, f4, f8, and f32 clocks are not necessary in wait mode, set the CM02 bit in the CM0 register to 1 (peripheral function clock stops in wait mode). This will stop the f1, f2, f4, f8, and f32 clocks in wait mode. 21.2.7 Timers If timer RA is not used, set the TCKCUT bit in the TRAMR register to 1 (count source cutoff). If timer RB is not used, set the TCKCUT bit in the TRBMR register to 1 (count source cutoff). Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 271 of 318 R8C/2G Group 21. Reducing Power Consumption 21.2.8 Reducing Internal Power Consumption When the MCU enters wait mode using low-speed clock mode or low-speed on-chip oscillator mode, internal power consumption can be reduced by using the VCA20 bit in the VCA2 register. Figure 21.1 shows the Handling Procedure of Internal Power Low Consumption Using VCA20 Bit. To enable internal power low consumption by the VCA20 bit, follow Figure 21.1 Handling Procedure of Internal Power Low Consumption Using VCA20 Bit. Exit wait mode by interrupt Handling procedure of internal power low consumption enabled by VCA20 bit (Note 1) In interrupt routine Step (1) Enter low-speed clock mode or low-speed on-chip oscillator mode Step (5) VCA20 ← 0 (internal power low consumption disabled)(2) Step (2) Stop high-speed on-chip oscillator clock Step (6) Start high-speed on-chip oscillator clock Step (3) VCA20 ← 1 (internal power low consumption enabled)(2) Step (7) (Wait until high-speed on-chip oscillator clock oscillation stabilizes) If it is necessary to start the high-speed on-chip oscillator in the interrupt routine, execute steps (5) to (8) in the interrupt routine. Step (4) Enter wait mode(3) Step (8) Enter high-speed on-chip oscillator mode Step (5) VCA20 ← 0 (internal power low consumption disabled)(2) Interrupt handling Step (6) Start high-speed on-chip oscillator clock Step (1) Enter low-speed clock mode or low-speed on-chip oscillator mode If high-speed on-chip oscillator is started in the interrupt routine, execute steps (1) to (3) at the last of the interrupt routine. Step (7) (Wait until high-speed on-chip oscillator clock oscillation stabilizes) Step (2) Stop high-speed on-chip oscillator clock Step (8) Enter high-speed on-chip oscillator mode Step (3) VCA20 ← 1 (internal power low consumption enabled)(2, 3) Interrupt handling completed NOTES: 1. Execute this routine to handle all interrupts generated in wait mode. However, this does not apply if it is not necessary to start high-speed on-chip oscillator during the interrupt routine. 2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite. 3. When entering wait mode, follow 11.5.2 Wait Mode. VCA20: Bit in VCA2 register Figure 21.1 Handling Procedure of Internal Power Low Consumption Using VCA20 Bit Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 272 of 318 R8C/2G Group 21. Reducing Power Consumption 21.2.9 Stopping Flash Memory In low-speed on-chip oscillator mode and low-speed clock mode, power consumption can be further reduced by stopping the flash memory using the FMSTP bit in the FMR0 register. Access to the flash memory is disabled by setting the FMSTP bit to 1 (flash memory stops). The FMSTP bit must be written to by a program transferred to RAM. When the MUC enters stop mode or wait mode while CPU rewrite mode is disabled, the power for the flash memory is automatically turned off. It is turned back on again after the MCU exit stop mode or wait mode. This eliminates the need to set the FMR0 register. Figure 21.2 shows the Handling Procedure Example of Low Power Consumption Using FMSTP Bit. FMSTP bit setting program After writing 0 to FMR01 bit, write 1 (CPU rewrite mode enabled) Transfer FMSTP bit setting program to RAM Write 1 to FMSTP bit (flash memory stops. low power consumption state)(1) Jump to FMSTP bit setting program (The subsequent processing is executed by the program in the RAM) Enter low-speed clock mode or low-speed onchip oscillator mode Stop high-speed on-chip oscillator Process in low-speed clock mode, lowspeed on-chip oscillator mode Switch clock source for CPU clock(2) Write 0 to FMSTP bit (flash memory operates) Write 0 to FMR01 bit (CPU rewrite mode disabled) NOTES: 1. After setting the FMR01 bit to 1 (CPU rewrite mode enabled), set the FMSTP bit to 1 (flash memory stops). 2. Before switching the CPU clock source, make sure the designated clock is stable. 3. Insert a 30 µs wait time by a program. Do not access to the flash memory during this wait time. FMR01, FMSTP: Bits in FMR0 register Wait until flash memory circuit stabilizes (30 µs)(3) Jump to specified address in flash memory Figure 21.2 Handling Procedure Example of Low Power Consumption Using FMSTP Bit Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 273 of 318 R8C/2G Group 21. Reducing Power Consumption 21.2.10 Low-Current-Consumption Read Mode In low-speed clock mode and low-speed on-chip oscillator mode, the current consumption when reading the flash memory can be reduced by setting the FMR47 bit in the FMR4 register to 1 (enabled). Figure 21.3 shows the Handling Procedure Example of Low-Current-Consumption Read Mode. Handling procedure of low-current-consumption read mode enabled by FMR47 bit Step (1) Enter low-speed clock mode or low-speed on-chip oscillator mode Step (2) Stop high-speed on-chip oscillator clock Step (3) FMR47 ← 1 (low-current-consumption read mode enabled)(1) Step (4) Enter low-current-consumption read mode(2) Step (5) FMR47 ← 0 (low-current-consumption read mode disabled) Step (6) Start high-speed on-chip oscillator clock Step (7) (Wait until high-speed on-chip oscillator clock oscillation stabilizes) Step (8) Enter high-speed on-chip oscillator mode NOTES: 1. To set the FMR47 bit to 1, first write 0 and then write 1 immediately. After writing 0, do not generate an interrupt before writing 1. 2. In low-current-consumption read mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled). FMR47: Bit in FMR4 register Figure 21.3 Handling Procedure Example of Low-Current-Consumption Read Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 274 of 318 R8C/2G Group 22. Electrical Characteristics 22. Electrical Characteristics Table 22.1 Symbol VCC VI VO Pd Topr Tstg Supply voltage Input voltage Output voltage Power dissipation Operating ambient temperature Storage temperature Topr = 25°C Absolute Maximum Ratings Parameter Condition Rated Value −0.3 to 6.5 −0.3 to VCC + 0.3 −0.3 to VCC + 0.3 500 −20 to 85 (N version) / −40 to 85 (D version) −65 to 150 Unit V V V mW °C °C Table 22.2 Symbol VCC VSS VIH VIL IOH(sum) IOH(sum) IOH(peak) IOH(avg) IOL(sum) IOL(sum) IOL(peak) IOL(avg) f(XCIN) − Recommended Operating Conditions Parameter Supply voltage Supply voltage Input “H” voltage Input “L” voltage Peak sum output “H” Sum of all pins IOH(peak) current Average sum output “H” Sum of all pins IOH(avg) current Peak output “H” current All pins Average output “H” All pins current Peak sum output “L” Sum of all pins IOL(peak) currents Average sum output “L” Sum of all pins IOL(avg) currents Peak output “L” currents All pins Average output “L” current All pins XCIN clock input oscillation frequency System clock OCD2 = 0 XClN clock selected OCD2 = 1 On-chip oscillator clock selected Conditions Min. 2.2 − 0.8 VCC 0 − − − − − − − − 0 0 − − Standard Typ. − 0 − − − − − − − − − − − − 125 − Max. 5.5 − VCC 0.2 VCC −160 −80 −10 −5 160 80 10 5 70 70 − 8 Unit V V V V mA mA mA mA mA mA mA mA kHz kHz kHz MHz 2.2 V ≤ VCC ≤ 5.5 V 2.2 V ≤ VCC ≤ 5.5 V HRA01 = 0 Low-speed on-chip oscillator selected HRA01 = 1 High-speed on-chip oscillator selected 2.7 V ≤ VCC ≤ 5.5 V HRA01 = 1 High-speed on-chip oscillator selected 2.2 V ≤ VCC ≤ 5.5 V − − 4 MHz NOTES: 1. VCC = 2.2 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. 2. The average output current indicates the average value of current measured during 100 ms. P0 P1 P3 P4 P6 30pF Figure 22.1 Ports P0, P1, P3, P4, and P6 Timing Measurement Circuit Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 275 of 318 R8C/2G Group 22. Electrical Characteristics Table 22.3 Symbol − − − − − − − Flash Memory (Program ROM) Electrical Characteristics Parameter Program/erase endurance(2) Byte program time Block erase time Program, erase voltage Read voltage Program, erase temperature Data hold time(7) Ambient temperature = 55°C Conditions Standard Min. 100(3) − − 2.7 2.2 0 20 Typ. − 50 0.4 − − − − Max. − 400 9 5.5 5.5 60 − Unit times µs s V V °C year NOTES: 1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 276 of 318 R8C/2G Group 22. Electrical Characteristics Table 22.4 Symbol Vdet0 − td(E-A) Vccmin Voltage Detection 0 Circuit Electrical Characteristics Parameter Voltage detection level Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(2) MCU operating voltage minimum value VCA25 = 1, VCC = 5.0 V Condition Standard Min. 2.2 − − 2.2 Typ. 2.3 0.9 − − Max. 2.4 − 300 − Unit V µA µs V NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version). 2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2 register to 0. Table 22.5 Symbol Vdet1 − − td(E-A) Voltage Detection 1 Circuit Electrical Characteristics Parameter Voltage detection level(4) Voltage monitor 1 interrupt request generation time(2) VCA26 = 1, VCC = 5.0 V Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(3) Condition Standard Min. 2.70 − − − Typ. 2.85 40 0.6 − Max. 3.00 − − 100 Unit V µs µA µs NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version). 2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1. 3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0. 4. This parameter shows the voltage detection level when the power supply drops. The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply drops by approximately 0.1 V. Table 22.6 Symbol Vdet2 − − td(E-A) Voltage Detection 2 Circuit Electrical Characteristics Parameter Voltage detection level Voltage monitor 2 interrupt request generation time(2) Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(3) VCA27 = 1, VCC = 5.0 V Condition Standard Min. 3.3 − − − Typ. 3.6 40 0.6 − Max. 3.9 − − 100 Unit V µs µA µs NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version). 2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2. 3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2 register to 0. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 277 of 318 R8C/2G Group 22. Electrical Characteristics Table 22.7 Symbol Vpor1 Vpor2 trth Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics(3) Parameter Power-on reset valid voltage(4) Power-on reset or voltage monitor 0 reset valid voltage External power VCC rise gradient(2) Condition Standard Min. − 0 20 Typ. − − − Max. 0.1 Vdet0 − Unit V V mV/msec NOTES: 1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. 2. This condition (external power VCC rise gradient) does not apply if VCC ≥ 1.0 V. 3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1. 4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if −20°C ≤ Topr ≤ 85°C, maintain tw(por1) for 3,000 s or more if −40°C ≤ Topr < −20°C. Vdet0(3) External Power VCC Vpor1 tw(por1) Sampling time(1, 2) trth 2.2 V trth Vpor2 Vdet0(3) Internal reset signal (“L” valid) 1 × 32 fOCO-S 1 × 32 fOCO-S NOTES: 1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage range (2.2 V or above) during the sampling time. 2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details. 3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection Circuit for details. Figure 22.2 Reset Circuit Electrical Characteristics Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 278 of 318 R8C/2G Group 22. Electrical Characteristics Table 22.8 Symbol Vref Comparator Electrical Characteristics Parameter Internal reference voltage Condition VCC = 2.2 V to 5.5 V, Topr = 25°C VCC = 2.2 V to 5.5 V, Topr = −40 to 85°C Standard Min. 1.15 − 0.5 0.5 −0.3 − − Typ. 1.25 1.25 − − − 20 4 Max. 1.35 − VCC − 1.1 VCC − 1.5 VCC + 0.3 120 − V mV µs Unit V V V Vcref Vcin Vofs Tcrsp External input reference voltage External comparison voltage input range Input offset voltage Response time VCC = 2.2 V to 4.0 V VCC = 4.0 V to 5.5 V NOTE: 1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. Table 22.9 Symbol fOCO-F High-speed On-Chip Oscillator Circuit Electrical Characteristics Parameter High-speed on-chip oscillator frequency temperature • supply voltage dependence Condition VCC = 4.75 V to 5.25 V Topr = 0 to 60°C(2) VCC = 2.7 V to 5.5 V Topr = −20 to 85°C(2) VCC = 2.7 V to 5.5 V Topr = −40 to 85°C(2) VCC = 2.2 V to 5.5 V Topr = −20 to 85°C(3) VCC = 2.2 V to 5.5 V Topr = −40 to 85°C(3) Standard Min. 7.76 7.68 7.44 7.04 6.8 Typ. 8 8 8 8 8 Max. 8.24 8.32 8.32 8.96 9.2 Unit MHz MHz MHz MHz MHz NOTES: 1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. 2. These standard values show when the HRA1 register is set to the value before shipment and the HRA2 register is set to 00h. 3. These standard values show when the correction value in the FRA6 register is written into the HRA1 register. Table 22.10 Symbol fOCO-S − − Low-speed On-Chip Oscillator Circuit Electrical Characteristics Parameter Low-speed on-chip oscillator frequency Oscillation stability time Self power consumption at oscillation VCC = 5.0 V, Topr = 25°C Condition Standard Min. 30 − − Typ. 125 10 15 Max. 250 100 − Unit kHz µs µA NOTE: 1. VCC = 2.2 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. Table 22.11 Symbol td(P-R) td(R-S) Power Supply Circuit Timing Characteristics Parameter Time for internal power supply stabilization during power-on(2) STOP exit time(3) Condition Standard Min. 1 − Typ. − − Max. 2000 150 Unit µs µs NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = 25°C. 2. Waiting time until the internal power supply generation circuit stabilizes during power-on. 3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 279 of 318 R8C/2G Group 22. Electrical Characteristics Table 22.12 Symbol VOH VOL VT+-VT- Electrical Characteristics (1) [VCC = 5 V] Parameter Condition IOH = −5 mA IOH = −200 µA IOL = 5 mA IOL = 200 µA INT0, INT1, INT2, INT4, KI0, KI1, KI2, KI3, RXD0, RXD2, CLK0, CLK2 RESET VI = 5 V, VCC = 5 V VI = 0 V, VCC = 5 V VI = 0 V, VCC = 5 V XCIN During stop mode Standard Min. VCC − 2.0 VCC − 0.5 − − 0.1 Typ. − − − − 0.5 Max. VCC VCC 2.0 0.45 − Unit V V V V V Output “H” voltage Output “L” voltage Hysteresis 0.1 − − 30 − 2.0 1.0 − − 50 18 − − 5.0 −5.0 167 − − V µA µA kΩ MΩ V IIH IIL RfXCIN VRAM Input “H” current Input “L” current Feedback resistance RAM hold voltage RPULLUP Pull-up resistance NOTE: 1. VCC = 4.2 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 280 of 318 R8C/2G Group 22. Electrical Characteristics Table 22.13 Electrical Characteristics (2) [Vcc = 5 V] (Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.) Parameter Condition High-speed on-chip oscillator on = 8 MHz Low-speed on-chip oscillator on = 125 kHz No division High-speed on-chip oscillator on = 8 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) FMR47 = 1 High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) Program operation on RAM Flash memory off, FMSTP = 1 Symbol ICC Standard Min. − − − − Typ. 5 2 130 130 Max. 8 − 300 300 Unit mA mA µA µA Power supply current High-speed (VCC = 3.3 to 5.5 V) on-chip oscillator mode Single-chip mode, output pins are open, other pins are VSS Low-speed on-chip oscillator mode Low-speed clock mode High-speed on-chip oscillator off − 30 − µA Wait mode High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit disabled (BGRCR0 = 1) High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit disabled (BGRCR0 = 1) High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit enabled (BGRCR0 = 0) High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit enabled (BGRCR0 = 0) − 25 75 µA − 23 60 µA − 4 − µA − 2.2 − µA − 8 − µA − 6 − µA Stop mode XCIN clock off, Topr = 25°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit disabled (BGRCR0 = 1) XCIN clock off, Topr = 85°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit disabled (BGRCR0 = 1) XCIN clock off, Topr = 25°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit enabled (BGRCR0 = 0) XCIN clock off, Topr = 85°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit enabled (BGRCR0 = 0) − 0.8 3 µA − 1.2 − µA − 5 8 µA − 5.5 − µA Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 281 of 318 R8C/2G Group Timing Requirements (Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V] Table 22.14 Symbol tc(XCIN) tWH(XCIN) tWL(XCIN) XCIN input cycle time XCIN input “H” width XCIN input “L” width 22. Electrical Characteristics XCIN Input Parameter Standard Min. 14 7 7 Max. − − − Unit µs µs µs tC(XCIN) tWH(XCIN) VCC = 5 V XCIN input tWL(XCIN) Figure 22.3 XCIN Input Timing Diagram when VCC = 5 V Table 22.15 Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO) TRAIO Input Parameter TRAIO input cycle time TRAIO input “H” width TRAIO input “L” width Standard Min. 100 40 40 Max. − − − Unit ns ns ns tC(TRAIO) tWH(TRAIO) VCC = 5 V TRAIO input tWL(TRAIO) Figure 22.4 TRAIO Input Timing Diagram when VCC = 5 V Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 282 of 318 R8C/2G Group 22. Electrical Characteristics Table 22.16 Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 or 2 Serial Interface Parameter CLKi input cycle time CLKi input “H” width CLKi input “L” width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. 200 100 100 − 0 50 90 Max. − − − 50 − − − Unit ns ns ns ns ns ns ns tC(CK) tW(CKH) VCC = 5 V CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0 or 2 Figure 22.5 Serial Interface Timing Diagram when VCC = 5 V Table 22.17 Symbol tW(INH) tW(INL) External Interrupt INTi (i = 0, 1, 2, 4) Input Parameter INTi input “H” width INTi input “L” width Standard Min. 250(1) 250(2) Max. − − Unit ns ns NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. VCC = 5 V tW(INL) INTi input i = 0, 1, 2, 4 tW(INH) Figure 22.6 External Interrupt INTi Input Timing Diagram when VCC = 5 V Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 283 of 318 R8C/2G Group 22. Electrical Characteristics Table 22.18 Symbol VOH VOL VT+-VT- Electrical Characteristics (3) [VCC = 3 V] Parameter Condition IOH = −1 mA IOL = 1 mA INT0, INT1, INT2, INT4, KI0, KI1, KI2, KI3, RXD0, RXD2, CLK0, CLK2 RESET VI = 3 V, VCC = 3 V VI = 0 V, VCC = 3 V VI = 0 V, VCC = 3 V XCIN During stop mode Standard Min. VCC − 0.5 − 0.1 Typ. − − 0.3 Max. VCC 0.5 − Unit V V V Output “H” voltage Output “L” voltage Hysteresis 0.1 − − 66 − 1.8 0.4 − − 160 18 − − 4.0 −4.0 500 − − V µA µA kΩ MΩ V IIH IIL RfXCIN VRAM Input “H” current Input “L” current Feedback resistance RAM hold voltage RPULLUP Pull-up resistance NOTE: 1. VCC =2.7 to 3.3 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 284 of 318 R8C/2G Group 22. Electrical Characteristics Table 22.19 Electrical Characteristics (4) [Vcc = 3 V] (Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.) Parameter Condition High-speed on-chip oscillator on = 8 MHz Low-speed on-chip oscillator on = 125 kHz No division High-speed on-chip oscillator on = 8 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) FMR47 = 1 High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) Program operation on RAM Flash memory off, FMSTP = 1 Symbol ICC Standard Min. − − − − Typ. 5 2 130 130 Max. − − 300 300 Unit mA mA µA µA Power supply current High-speed (VCC = 2.7 to 3.3 V) on-chip oscillator mode Single-chip mode, output pins are open, other pins are VSS Low-speed on-chip oscillator mode Low-speed clock mode High-speed on-chip oscillator off − 30 − µA Wait mode High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit disabled (BGRCR0 = 1) High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit disabled (BGRCR0 = 1) High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit enabled (BGRCR0 = 0) High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit enabled (BGRCR0 = 0) − 25 70 µA − 23 55 µA − 3.8 − µA − 2 − µA − 8 − µA − 6 − µA Stop mode XCIN clock off, Topr = 25°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit disabled (BGRCR0 = 1) XCIN clock off, Topr = 85°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit disabled (BGRCR0 = 1) XCIN clock off, Topr = 25°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit enabled (BGRCR0 = 0) XCIN clock off, Topr = 85°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit enabled (BGRCR0 = 0) − 0.7 3 µA − 1.1 − µA − 5 7 µA − 5.5 − µA Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 285 of 318 R8C/2G Group Timing requirements (Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C) [VCC = 3 V] Table 22.20 Symbol tc(XCIN) tWH(XCIN) tWL(XCIN) XCIN input cycle time XCIN input “H” width XCIN input “L” width 22. Electrical Characteristics XCIN Input Parameter Standard Min. 14 7 7 Max. − − − Unit µs µs µs tC(XCIN) tWH(XCIN) VCC = 3 V XCIN input tWL(XCIN) Figure 22.7 XCIN Input Timing Diagram when VCC = 3 V Table 22.21 Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO) TRAIO Input Parameter TRAIO input cycle time TRAIO input “H” width TRAIO input “L” width Standard Min. 300 120 120 Max. − − − Unit ns ns ns tC(TRAIO) tWH(TRAIO) VCC = 3 V TRAIO input tWL(TRAIO) Figure 22.8 TRAIO Input Timing Diagram when VCC = 3 V Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 286 of 318 R8C/2G Group 22. Electrical Characteristics Table 22.22 Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 or 2 Serial Interface Parameter CLKi input cycle time CLKi input “H” width CLKi Input “L” width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. 300 150 150 − 0 70 90 Max. − − − 80 − − − Unit ns ns ns ns ns ns ns tC(CK) tW(CKH) VCC = 3 V CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0 or 2 Figure 22.9 Serial Interface Timing Diagram when VCC = 3 V Table 22.23 Symbol tW(INH) tW(INL) External Interrupt INTi (i = 0, 1, 2, 4) Input Parameter INTi input “H” width INTi input “L” width Standard Min. 380(1) 380(2) Max. − − Unit ns ns NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. VCC = 3 V tW(INL) INTi input tW(INH) i = 0, 1, 2, 4 Figure 22.10 External Interrupt INTi Input Timing Diagram when VCC = 3 V Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 287 of 318 R8C/2G Group 22. Electrical Characteristics Table 22.24 Symbol VOH VOL VT+-VT- Electrical Characteristics (5) [VCC = 2.2 V] Parameter Condition IOH = −1 mA IOL = 1 mA INT0, INT1, INT2, INT4, KI0, KI1, KI2, KI3, RXD0, RXD2, CLK0, CLK2 RESET VI = 2.2 V VI = 0 V VI = 0 V XCIN During stop mode Standard Min. VCC − 0.5 − 0.05 Typ. − − 0.3 Max. VCC 0.5 − Unit V V V Output “H” voltage Output “L” voltage Hysteresis 0.05 − − 100 − 1.8 0.15 − − 200 35 − − 4.0 −4.0 600 − − V µA µA kΩ MΩ V IIH IIL RfXCIN VRAM Input “H” current Input “L” current Feedback resistance RAM hold voltage RPULLUP Pull-up resistance NOTE: 1. VCC = 2.2 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 288 of 318 R8C/2G Group 22. Electrical Characteristics Table 22.25 Electrical Characteristics (6) [Vcc = 2.2 V] (Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.) Parameter Condition High-speed on-chip oscillator on = 4 MHz Low-speed on-chip oscillator on = 125 kHz No division High-speed on-chip oscillator on = 4 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) FMR47 = 1 High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) Program operation on RAM Flash memory off, FMSTP = 1 Symbol ICC Standard Min. − − − − Typ. 3.5 1.5 100 100 Max. − − 230 230 Unit mA mA µA µA Power supply current High-speed (VCC = 2.2 to 2.7 V) on-chip oscillator mode Single-chip mode, output pins are open, other pins are VSS Low-speed on-chip oscillator mode Low-speed clock mode High-speed on-chip oscillator off − 25 − µA Wait mode High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit disabled (BGRCR0 = 1) High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit disabled (BGRCR0 = 1) High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit enabled (BGRCR0 = 0) High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 BGR trimming circuit enabled (BGRCR0 = 0) − 22 60 µA − 20 55 µA − 3 − µA − 1.8 − µA − 7 − µA − 6 − µA Stop mode XCIN clock off, Topr = 25°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit disabled (BGRCR0 = 1) XCIN clock off, Topr = 85°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit disabled (BGRCR0 = 1) XCIN clock off, Topr = 25°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit enabled (BGRCR0 = 0) XCIN clock off, Topr = 85°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 BGR trimming circuit enabled (BGRCR0 = 0) − 0.7 3 µA − 1.1 − µA − 5 7 µA − 5.5 − µA Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 289 of 318 R8C/2G Group 22. Electrical Characteristics Timing requirements (Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25°C) [VCC = 2.2 V] Table 22.26 Symbol tc(XCIN) tWH(XCIN) tWL(XCIN) XCIN input cycle time XCIN input “H” width XCIN input “L” width XCIN Input Parameter Standard Min. 14 7 7 Max. − − − Unit µs µs µs tC(XCIN) tWH(XCIN) VCC = 2.2 V XCIN input tWL(XCIN) Figure 22.11 XCIN Input Timing Diagram when VCC = 2.2 V Table 22.27 Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO) TRAIO Input Parameter TRAIO input cycle time TRAIO input “H” width TRAIO input “L” width Standard Min. 500 200 200 Max. − − − Unit ns ns ns tC(TRAIO) tWH(TRAIO) VCC = 2.2 V TRAIO input tWL(TRAIO) Figure 22.12 TRAIO Input Timing Diagram when VCC = 2.2 V Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 290 of 318 R8C/2G Group 22. Electrical Characteristics Table 22.28 Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 or 2 Serial Interface Parameter CLKi input cycle time CLKi input “H” width CLKi input “L” width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. 800 400 400 − 0 150 90 Max. − − − 200 − − − Unit ns ns ns ns ns ns ns tC(CK) tW(CKH) VCC = 2.2 V CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0 or 2 Figure 22.13 Serial Interface Timing Diagram when VCC = 2.2 V Table 22.29 Symbol tW(INH) tW(INL) External Interrupt INTi (i = 0, 1, 2, 4) Input Parameter INTi input “H” width INTi input “L” width Standard Min. 1000(1) 1000(2) Max. − − Unit ns ns NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. VCC = 2.2 V tW(INL) INTi input i = 0, 1, 2, 4 tW(INH) Figure 22.14 External Interrupt INTi Input Timing Diagram when VCC = 2.2 V Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 291 of 318 R8C/2G Group 23. Usage Notes 23. Usage Notes 23.1 23.1.1 Notes on I/O Ports Port P4_3, P4_4 Ports P4_3 and P4_4 are also used as the XCIN function and the XCOUT function, respectively. During a reset period and after a reset release, these ports are set to the XCIN and XCOUT functions. Pins P4_3 and P4_4 can be switched to the port functions by setting the CM04 bit in the CM0 register to 0 (ports P4_3 and P4_4) by a program. To use ports P4_3 and P4_4 as ports, note the following: • Port P4_3 After a reset until the CM04 bit is set to 0 (ports P4_3 and P4_4) by a program, a typical 10 MΩ impedance is connected between the P4_3 pin and the MCU power supply or GND. If the XCIN is set to intermediate-level input or left floating, a shoot-through current flows into the oscillation driver. • Port P4_4 Use port P4_4 as an output port by setting the PD4_4 bit in the PD4 register to 1 (output mode). After a reset until the CM04 bit is set to 0 (ports P4_3 and P4_4) by a program, the P4_4 pin may output an intermediate potential of about 2.0 V. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 292 of 318 R8C/2G Group 23. Usage Notes 23.2 23.2.1 Notes on Clock Generation Circuit Stop Mode When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit to 1 (stop mode) and the program stops. Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets the CM10 bit to 1. • Program example to enter stop mode BCLR BSET FSET BSET JMP.B LABEL_001 : NOP NOP NOP NOP 1,FMR0 0,PRCR I 0,CM1 LABEL_001 ; CPU rewrite mode disabled ; Protect disabled ; Enable interrupt ; Stop mode 23.2.2 Wait Mode When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the program stops. Insert at least 4 NOP instructions after the WAIT instruction. • Program example to execute the WAIT instruction BCLR 1,FMR0 FSET I WAIT NOP NOP NOP NOP ; CPU rewrite mode disabled ; Enable interrupt ; Wait mode 23.2.3 Oscillation Circuit Constants Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 293 of 318 R8C/2G Group 23. Usage Notes 23.3 23.3.1 Notes on Interrupts Reading Address 00000h Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At this time, the acknowledged interrupt IR bit is set to 0. If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be generated. 23.3.2 SP Setting Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset. Therefore, if an interrupt is acknowledged before setting a value in the SP, the program may run out of control. 23.3.3 External Interrupt and Key Input Interrupt Either “L” level or an “H” level of width shown in the Electrical Characteristics is necessary for the signal input to pins INT0, INT1, INT2, INT4 and pins KI0 to KI3, regardless of the CPU clock. For details, refer to Table 22.17 (VCC = 5V), Table 22.23 (VCC = 3V), and Table 22.29 (VCC = 2.2V) External Interrupt INTi (i = 0, 1, 2, 4) Input. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 294 of 318 R8C/2G Group 23. Usage Notes 23.3.4 Changing Interrupt Sources The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source. In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to individual software interrupt numbers, polarities, and timing. Therefore, if a mode change of a peripheral function involves interrupt sources, edge polarities, and timing, set the IR bit to 0 (no interrupt requested) after the change. Refer to the individual peripheral function for its related interrupts. Figure 23.1 shows an Example of Procedure for Changing Interrupt Sources. Interrupt source change Disable interrupts(2, 3) Change interrupt source (including mode of peripheral function) Set the IR bit to 0 (interrupt not requested) using the MOV instruction(3) Enable interrupts (2, 3) Change completed IR bit: The interrupt control register bit of an interrupt whose source is changed. NOTES: 1. Execute the above settings individually. Do not execute two or more settings at once (by one instruction). 2. To prevent interrupt requests from being generated, disable the peripheral function before changing the interrupt source. In this case, use the I flag if all maskable interrupts can be disabled. If all maskable interrupts cannot be disabled, use bits ILVL0 to ILVL2 of the interrupt whose source is changed. 3. Refer to 13.5.5 Changing Interrupt Control Register Contents for the instructions to be used and usage notes. Figure 23.1 Example of Procedure for Changing Interrupt Sources Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 295 of 318 R8C/2G Group 23. Usage Notes 23.3.5 Changing Interrupt Control Register Contents (a) The contents of an interrupt control register can only be changed while no interrupt requests corresponding to that register are generated. If interrupt requests may be generated, disable interrupts before changing the interrupt control register contents. (b) When changing the contents of an interrupt control register after disabling interrupts, be careful to choose appropriate instructions. Changing any bit other than IR bit If an interrupt request corresponding to a register is generated while executing the instruction, the IR bit may not be set to 1 (interrupt requested), and the interrupt request may be ignored. If this causes a problem, use the following instructions to change the register: AND, OR, BCLR, BSET Changing IR bit If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used. Therefore, use the MOV instruction to set the IR bit to 0. (c) When disabling interrupts using the I flag, set the I flag as shown in the sample programs below. Refer to (b) regarding changing the contents of interrupt control registers by the sample programs. Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before the interrupt control register is changed for reasons of the internal bus or the instruction queue buffer. Example 1: Use NOP instructions to prevent I flag from being set to 1 before interrupt control register is changed INT_SWITCH1: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h NOP ; NOP FSET I ; Enable interrupts Example 2: Use dummy read to delay FSET instruction INT_SWITCH2: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h MOV.W MEM,R0 ; Dummy read FSET I ; Enable interrupts Example 3: Use POPC instruction to change I flag INT_SWITCH3: PUSHC FLG FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h POPC FLG ; Enable interrupts Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 296 of 318 R8C/2G Group 23. Usage Notes 23.4 23.4.1 Notes on ID Code Areas Setting Example of ID Code Areas As the ID code areas are allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing an instruction. Write appropriate values when creating a program. The following shows a setting example. • To set 55h in all of the ID code areas .org 00FFDCH .lword dummy | (55000000h) ; UND .lword dummy | (55000000h) ; INTO .lword dummy ; BREAK .lword dummy | (55000000h) ; ADDRESS MATCH .lword dummy | (55000000h) ; SET SINGLE STEP .lword dummy | (55000000h) ; WDT .lword dummy | (55000000h) ; ADDRESS BREAK .lword dummy | (55000000h) ; RESERVE (Programming formats vary depending on the compiler. Check the compiler manual.) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 297 of 318 R8C/2G Group 23. Usage Notes 23.5 23.5.1 Notes on Option Function Select Area Setting Example of Option Function Select Area As the option function select area is allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing an instruction. Write appropriate values when creating a program. The following shows a setting example. • To set FFh in the OFS register .org 00FFFCH .lword reset | (0FF000000h) ; RESET (Programming formats vary depending on the compiler. Check the compiler manual.) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 298 of 318 R8C/2G Group 23. Usage Notes 23.6 23.6.1 Notes on Timers Notes on Timer RA • Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the • count starts. Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by the MCU. Consequently, the timer value may be updated during the period when these two registers are being read. In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by writing 0 to these bits by a program. However, these bits remain unchanged if 1 is written. When using the READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0 although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or TUNDF bit which is not supposed to be set to 0 with the MOV instruction. When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts. The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts. When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler immediately after the count starts, then set the TEDGF bit to 0. The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1 (count starts) while the count is stopped. During this time, do not access registers associated with timer RA(1) other than the TCSTF bit. Timer RA starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count). The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RA(1) other than the TCSTF bit. NOTE: 1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA. • • • • • • When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the count source clock for each write interval. • When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 299 of 318 R8C/2G Group 23. Usage Notes 23.6.2 Notes on Timer RB • Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the count starts. • Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the MCU. Consequently, the timer value may be updated during the period when these two registers are being read. • In programmable one-shot generation mode and programmable wait one-shot generation mode, when setting the TSTART bit in the TRBCR register to 0, 0 (stops counting) or setting the TOSSP bit in the TRBOCR register to 1 (stops one-shot), the timer reloads the value of reload register and stops. Therefore, in programmable one-shot generation mode and programmable wait one-shot generation mode, read the timer count value before the timer stops. • The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to 1 (count starts) while the count is stopped. During this time, do not access registers associated with timer RB(1)other than the TCSTF bit. Timer RB starts counting at the first valid edge of the count source after the TCSTF bit is set to 1 (during count). The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RB(1) other than the TCSTF bit. NOTE: 1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and TRBPR. • If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately. • If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes after one or two cycles of the count source have elapsed. If the TOSSP bit is written to 1 during the period between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit may be set to either 0 or 1. 23.6.2.1 Timer mode The following workaround should be performed in timer mode. To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: • When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 300 of 318 R8C/2G Group 23. Usage Notes 23.6.2.2 Programmable waveform generation mode The following three workarounds should be performed in programmable waveform generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: • When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval. (2) To change registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), synchronize the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period A shown in Figures 23.2 and 23.3. The following shows the detailed workaround examples. • Workaround example (a): As shown in Figure 23.2, write to registers TRBSC and TRBPR in the timer RB interrupt routine. These write operations must be completed by the beginning of period A. Period A Count source/ prescaler underflow signal TRBO pin output Primary period Secondary period IR bit in TRBIC register (a) Interrupt request is acknowledged (b) Ensure sufficient time Interrupt request is generated Interrupt Instruction in sequence interrupt routine Set the secondary and then the primary register immediately (a) Period between interrupt request generation and the completion of execution of an instruction. The length of time varies depending on the instruction being executed. The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as the divisor). (b) 20 cycles. 21 cycles for address match and single-step interrupts. Figure 23.2 Workaround Example (a) When Timer RB interrupt is Used Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 301 of 318 R8C/2G Group 23. Usage Notes • Workaround example (b): As shown in Figure 23.3 detect the start of the primary period by the TRBO pin output level and write to registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A. If the port register’s bit value is read after the port direction register’s bit corresponding to the TRBO pin is set to 0 (input mode), the read value indicates the TRBO pin output value. Period A Count source/ prescaler underflow signal TRBO pin output Read value of the port register’s bit corresponding to the TRBO pin (when the bit in the port direction register is set to 0) Primary period Secondary period (i) (ii) (iii) Ensure sufficient time The TRBO output inversion is detected at the end of the secondary period. Upon detecting (i), set the secondary and then the primary register immediately. Figure 23.3 Workaround Example (b) When TRBO Pin Output Value is Read (3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case, registers TRBPRE and TRBPR are initialized and their values are set to the values after reset. 23.6.2.3 Programmable one-shot generation mode The following two workarounds should be performed in programmable one-shot generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: • When the TRBPRE register is written continuously during count operation (TCSTF bit is set to 1), allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval. (2) Do not set both the TRBPRE and TRBPR registers to 00h. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 302 of 318 R8C/2G Group 23. Usage Notes 23.6.2.4 Programmable wait one-shot generation mode The following three workarounds should be performed in programmable wait one-shot generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: • When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. • When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval. (2) Do not set both the TRBPRE and TRBPR registers to 00h. (3) Set registers TRBSC and TRBPR using the following procedure. (a) To use “INT0 pin one-shot trigger enabled” as the count start condition Set the TRBSC register and then the TRBPR register. At this time, after writing to the TRBPR register, allow an interval of 0.5 or more cycles of the count source before trigger input from the INT0 pin. (b) To use “writing 1 to TOSST bit” as the start condition Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the TRBPR register, allow an interval of 0.5 or more cycles of the count source before writing to the TOSST bit. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 303 of 318 R8C/2G Group 23. Usage Notes 23.6.3 Notes on Timer RE Starting and Stopping Count 23.6.3.1 Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates count start or stop. Bits TSTART and TCSTF are in the TRECR1 register. Timer RE starts counting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to 1. During this time, do not access registers associated with timer RE(1) other than the TCSTF bit. Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0 (count stops). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF bit. NOTE: 1. Registers associated with timer RE: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2, TRECSR, and TREOPR. 23.6.3.2 Register Setting Write to the following registers or bits when timer RE is stopped. • Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2 • Bits H12_H24, PM, and INT in TRECR1 register • Bits RCS0 to RCS3 in TRECSR register Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped). Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the TRECR2 register. Figure 23.4 shows a Setting Example in Real-Time Clock Mode. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 304 of 318 R8C/2G Group 23. Usage Notes TRERST in TRECR1 register = 1 TRERST in TRECR1 register = 0 TSTART in TRECR1 register = 0 Timer RE register and control circuit reset Stop timer RE operation TCSTF in TRECR1 register = 0? Disable timer RE clock output (When it is necessary) TOENA in TRECR1 register = 0 TREIC register ← 00h (disable timer RE interrupt) Setting of registers TRECSR, TRESEC, TREMIN, TREHR, TREWK, and bits H12_H24, PM, and INT in TRECR1 register Select clock output Select clock source Seconds, minutes, hours, days of week, operating mode Set a.m./p.m., interrupt timing Setting of TRECR2 register Setting of TREIC register (IR bit ← 0, select interrupt priority level) TOENA in TRECR1 register = 1 TSTART in TRECR1 register = 1 Select interrupt source Enable timer RE clock output (When it is necessary) Start timer RE operation TCSTF in TRECR1 register = 1? Figure 23.4 Setting Example in Real-Time Clock Mode Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 305 of 318 R8C/2G Group 23. Usage Notes 23.6.3.3 Time Reading Procedure of Real-Time Clock Mode In real-time clock mode, read registers TRESEC, TREMIN, TREHR, and TREWK when time data is updated and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (not while data is updated). Also, when reading several registers, an incorrect time will be read if data is updated before another register is read after reading any register. In order to prevent this, use the reading procedure shown below. • Using an interrupt Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register in the timer RE interrupt routine. • Monitoring with a program 1 Monitor the IR bit in the TREIC register with a program and read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the IR bit in the TREIC register is set to 1 (timer RE interrupt request generated). • Monitoring with a program 2 (1) Monitor the BSY bit. (2) Monitor until the BSY bit is set to 0 after the BSY bit is set to 1 (approximately 62.5 ms while the BSY bit is set to 1). (3) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the BSY bit is set to 0. • Using read results if they are the same value twice (1) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register. (2) Read the same register as (1) and compare the contents. (3) Recognize as the correct value if the contents match. If the contents do not match, repeat until the read contents match with the previous contents. Also, when reading several registers, read them as continuously as possible. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 306 of 318 R8C/2G Group 23. Usage Notes 23.6.4 Notes on Timer RF • Access registers TRF, TRFM0, and TRFM1 in 16-bit units. Example of reading timer RF: MOV.W 0290H,R0 ; Read out timer RF • In input capture mode, a capture interrupt request is generated by inputting an edge selected by bits TRFC03 and TRFC04 in the TRFCR0 register even when the TSTART bit in the TRFCR0 register is set to 0 (count stops). Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 307 of 318 R8C/2G Group 23. Usage Notes 23.7 Notes on Serial Interface • When reading data from the UiRB (i = 0 or 2) register either in the clock synchronous serial I/O mode or in the clock asynchronous serial I/O mode. Ensure the data is read in 16-bit units. When the high-order byte of the UiRB register is read, bits PER and FER in the UiRB register and the RI bit in the UiC1 register are set to 0. To check receive errors, read the UiRB register and then use the read data. Example (when reading receive buffer register): MOV.W 00A6H,R0 ; Read the U0RB register • When writing data to the UiTB register in the clock asynchronous serial I/O mode with 9-bit transfer data length, write data to the high-order byte first then the low-order byte, in 8-bit units. Example (when reading transmit buffer register): MOV.B #XXH,00A3H ; Write the high-order byte of U0TB register MOV.B #XXH,00A2H ; Write the low-order byte of U0TB register Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 308 of 318 R8C/2G Group 23. Usage Notes 23.8 Notes on Hardware LIN For the time-out processing of the header and response fields, use another timer to measure the duration of time with a Synch Break detection interrupt as the starting point. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 309 of 318 R8C/2G Group 23. Usage Notes 23.9 23.9.1 Notes on Flash Memory CPU Rewrite Mode Operating Speed 23.9.1.1 Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit in the CM0 register and bits CM16 to CM17 in the CM1 register. This does not apply to EW1 mode. 23.9.1.2 Prohibited Instructions The following instructions cannot be used in EW0 mode because they reference data in the flash memory: UND, INTO, and BRK. 23.9.1.3 Non-Maskable Interrupts • EW0 Mode Once a watchdog timer, voltage monitor1, voltage monitor 2, comparator 1, or comparator 2 interrupt request is acknowledged, auto-erasure or auto-programming is forcibly stopped immediately and the flash memory is reset. Interrupt handling starts after a fixed period and the flash memory restarts. As the block during auto-erasure or the address during auto-programming is forcibly stopped, the normal value may not be readable. Execute auto-erasure again and ensure it completes normally. The watchdog timer does not stop during command operation, so that interrupt requests may be generated. Initialize the watchdog timer regularly. Do not use the address match interrupt while a command is being executed because the vector of the address match interrupt is allocated in ROM. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is allocated in block 0. • EW1 Mode Once a watchdog timer, voltage monitor1, voltage monitor 2, comparator 1, or comparator 2 interrupt request is acknowledged, auto-erasure or auto-programming is forcibly stopped immediately and the flash memory is reset. Interrupt handling starts after a fixed period and the flash memory restarts. As the block during auto-erasure or the address during auto-programming is forcibly stopped, the normal value may not be readable. Execute auto-erasure again and ensure it completes normally. The watchdog timer does not stop even during command operation, so that interrupt requests may be generated. Initialize the watchdog timer by using the erase-suspend function. Do not use the address match interrupt while a command is being executed because the vector of the address match interrupt is allocated in ROM. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is allocated in block 0. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 310 of 318 R8C/2G Group 23. Usage Notes 23.9.1.4 How to Access Write 0 before writing 1 when setting Bits FMR01, FMR02 in the FMR0 register, or FMR11 bit in the FMR1 register to 1. Do not generate an interrupt between writing 0 and 1. 23.9.1.5 Rewriting User ROM Area In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be rewritten correctly. In this case, use standard serial I/O mode. 23.9.1.6 Program Do not write additions to the already programmed address. 23.9.1.7 Program and Erase Voltage for Flash Memory To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform programming and erasure at less than 2.7 V. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 311 of 318 R8C/2G Group 23. Usage Notes 23.10 Notes on Noise 23.10.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and Latch-up Connect a bypass capacitor (at least 0.1 µF) using the shortest and thickest write possible. 23.10.2 Countermeasures against Noise Error of Port Control Registers During rigorous noise testing or the like, external noise (mainly power supply system noise) can exceed the capacity of the MCU's internal noise control circuitry. In such cases the contents of the port related registers may be changed. As a firmware countermeasure, it is recommended that the port registers, port direction registers, and pull-up control registers be reset periodically. However, examine the control processing fully before introducing the reset routine as conflicts may be created between the reset routine and interrupt routines. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 312 of 318 R8C/2G Group 24. Notes for On-Chip Debugger 24. Notes for On-Chip Debugger When using the on-chip debugger to develop and debug programs for the R8C/2G Group take note of the following. (1) Some of the user flash memory and RAM areas are used by the on-ship debugger. These areas cannot be accessed by the user. Refer to the on-chip debugger manual for which areas are used. Do not set the address match interrupt (registers AIER, RMAD0, and RMAD1 and fixed vector tables) in a user system. Do not use the BRK instruction in a user system. Debugging is available under the condition of supply voltage VCC = 2.7 to 5.5 V. Debugging with the on-chip debugger under less than 2.7 V is not allowed. (2) (3) (4) Connecting and using the on-chip debugger has some special restrictions. Refer to the on-chip debugger manual for details. Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 313 of 318 R8C/2G Group Appendix 1. Package Dimensions Appendix 1. Package Dimensions Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas Technology website. JEITA Package Code P-LQFP32-7x7-0.80 RENESAS Code PLQP0032GB-A Previous Code 32P6U-A MASS[Typ.] 0.2g HD *1 D 24 17 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1 25 16 HE E c1 *2 c Reference Dimension in Millimeters Symbol Terminal cross section 32 1 ZD Index mark 8 ZE 9 A2 A F A1 L L1 D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 y e *3 Detail F bp x Min Nom Max 6.9 7.0 7.1 6.9 7.0 7.1 1.4 8.8 9.0 9.2 8.8 9.0 9.2 1.7 0.1 0.2 0 0.32 0.37 0.42 0.35 0.09 0.145 0.20 0.125 0° 8° 0.8 0.20 0.10 0.7 0.7 0.3 0.5 0.7 1.0 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 314 of 318 c R8C/2G Group Appendix 2. Connection Examples with On-Chip Debugging Emulator Appendix 2. Connection Examples with On-Chip Debugging Emulator Appendix Figure 2.1 shows a Connection Example with E8 Emulator (R0E000080KCE00). VCC Open collector buffer 29 28 25 30 31 26 32 27 4.7kΩ or more User logic 1 2 3 24 23 22 21 20 19 18 17 12 13 16 14 15 11 10 9 R8C/2G Group Connect oscillation circuit(1) VSS 4 5 6 14 12 10 8 VCC 6 4 2 VSS 13 RESET 4.7kΩ ±10% MODE 7 8 7 MODE E8 emulator (R0E000080KCE00) NOTE: 1. It is not necessary to connect an oscillation circuit when operating with the on-chip oscillator clock. Appendix Figure 2.1 Connection Example with E8 Emulator (R0E000080KCE00) Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 315 of 318 R8C/2G Group Appendix 3. Example of Oscillation Evaluation Circuit Appendix 3. Example of Oscillation Evaluation Circuit Appendix Figure 3.1 shows an Example of Oscillation Evaluation Circuit. VCC 29 28 30 25 26 31 32 27 1 2 24 23 R8C/2G Group RESET Connect oscillation circuit 3 4 22 21 20 19 18 17 VSS 5 6 7 8 12 13 16 14 15 11 10 NOTE: 1. After reset, the XCIN clock stop. Write a program to oscillate the XCIN clock. 9 Appendix Figure 3.1 Example of Oscillation Evaluation Circuit Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 316 of 318 R8C/2G Group Index Index [A] AIER .................................................................................... 128 ALCMR .................................................................................. 52 [B] BGRCR ................................................................................. 53 BGRTRM ............................................................................... 54 BGRTRMA ............................................................................ 48 BGRTRMB ............................................................................ 48 [C] CAPIC ................................................................................. 113 CM0 ....................................................................................... 89 CM1 ....................................................................................... 90 CMP0IC ............................................................................... 113 CMP1IC ............................................................................... 113 CPSRF .................................................................................. 93 CSPR .................................................................................. 140 [F] FMR0 .................................................................................. 249 FMR1 .................................................................................. 252 FMR4 .................................................................................. 253 FRA4 ..................................................................................... 93 FRA6 ..................................................................................... 93 [H] HRA0 ..................................................................................... 92 HRA1 ..................................................................................... 92 HRA2 ..................................................................................... 92 [I] INT0IC ................................................................................. 114 INT1IC ................................................................................. 114 INT2IC ................................................................................. 114 INT4IC ................................................................................. 114 INTEN ................................................................................. 121 INTEN2 ............................................................................... 122 INTF .................................................................................... 122 INTF2 .................................................................................. 123 [K] KIEN .................................................................................... 126 KUPIC ................................................................................. 113 [L] LINCR ................................................................................. 231 LINST .................................................................................. 232 [O] OCD ...................................................................................... 91 OFS ............................................................... 26, 135, 140, 247 [P] PDi (i = 0, 1, 3, 4, or 6) .......................................................... 71 Pi (i = 0, 1, 3, 4, or 6) ............................................................. 72 PINSR2 ................................................................................. 73 PINSR3 ................................................................................. 73 PINSR4 ..................................................................... 39, 54, 73 PM0 ....................................................................................... 85 PM1 ....................................................................................... 85 PMR ....................................................................................... 74 PRCR .................................................................................. 107 PUR0 ..................................................................................... 74 PUR1 ..................................................................................... 74 [R] RMAD0 ................................................................................ 128 RMAD1 ................................................................................ 128 [S] S0RIC S0TIC S2RIC S2TIC .................................................................................. 113 .................................................................................. 113 .................................................................................. 113 .................................................................................. 113 [T] TRA ..................................................................................... 147 TRACR ................................................................................ 146 TRAIC .................................................................................. 113 TRAIOC ....................................... 146, 148, 151, 153, 155, 158 TRAMR ................................................................................ 147 TRAPRE .............................................................................. 147 TRBCR ................................................................................ 162 TRBIC .................................................................................. 113 TRBIOC ............................................... 163, 165, 169, 172, 176 TRBMR ................................................................................ 163 TRBOCR ............................................................................. 162 TRBPR ................................................................................ 164 TRBPRE .............................................................................. 164 TRBSC ................................................................................ 164 TRECR1 ...................................................................... 187, 194 TRECR2 ...................................................................... 188, 194 TRECSR ...................................................................... 189, 195 TREHR ................................................................................ 186 TREIC .................................................................................. 113 TREMIN ....................................................................... 185, 193 TREOPR .............................................................................. 189 TRESEC ...................................................................... 185, 193 TREWK ................................................................................ 186 TRF ...................................................................................... 202 TRFCR0 .............................................................................. 203 TRFCR1 .............................................................................. 204 TRFCR2 .............................................................................. 203 TRFIC .................................................................................. 113 TRFM0 ................................................................................. 202 TRFM1 ................................................................................. 202 TRFOUT .............................................................................. 204 [U] U0BRG ................................................................................ 215 U0C0 ................................................................................... 216 U0C1 ................................................................................... 217 U0MR .................................................................................. 215 U0RB ................................................................................... 217 U0TB ................................................................................... 216 U2BRG ................................................................................ 215 U2C0 ................................................................................... 216 U2C1 ................................................................................... 217 U2MR .................................................................................. 215 U2RB ................................................................................... 217 U2TB ................................................................................... 216 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 317 of 318 R8C/2G Group Index [V] VCA1 ............................................................................... 35, 49 VCA2 ......................................................................... 35, 49, 94 VCAB .................................................................................... 52 VCAC .............................................................................. 39, 53 VCMP1IC ............................................................................ 113 VCMP2IC ............................................................................ 113 VW0C .................................................................................... 36 VW1C .............................................................................. 37, 50 VW2C .............................................................................. 38, 51 [W] WDC .................................................................................... 139 WDTR ................................................................................. 139 WDTS .................................................................................. 139 Rev.1.00 Apr 04, 2008 REJ09B0387-0100 Page 318 of 318 REVISION HISTORY REVISION HISTORY Rev. 0.01 0.10 Date Mar 30, 2007 Jul 20, 2007 R8C/2G Group Hardware Manual R8C/2G Group Hardware Manual Description Page − − − Summary First Edition issued “RENESAS TECHNICAL UPDATE” reflected: TN-16C-A164A/E, TN-16C-A167A/E Register/bit symbols revised: “CM1POR” → “LCM1POR”, “CM2POR” → “LCM2POR”, “ACMR” → “ALCMR” Table 1.1: Clock; “Real-time clock (timer RE)” added Figure 1.3 “P4_4/(XCOUT)(1)” → “P4_4/XCOUT”, “P4_3/(XCIN)(1)” → “P4_3/XCIN” Table 1.3 “(XCOUT)(1)” → “XCOUT”, “(XCIN)(1)” → “XCIN” Table 4.2, Figure 6.6: 0038h After reset; “0000X010b” → “1000X010b”, “0100X011b” → “1100X011b” Figure 5.3 revised 2 5 6 13, 36 25 26, 130, Figure 5.4, Figure 15.2, Figure 16.3, Figure 20.2: 135, 242 OFS Register; NOTE1 revised 83 139 144 156 159 162 173 229 230 231 Figure 11.1 revised Table 17.1: Timer RE; “• fC32” deleted Figure 17.5 revised 17.2 “The reload register .... same address” added Figure 17.15 “Programmable one-shot mode” → “Programmable oneshot generation mode” Figure 17.17 revised NOTE: “TRBIOC” added Figure 19.5 revised Figure 19.6 revised Figure 19.7: SFDCT flag in the LINST register; “Set by ....the B1CLR bit in the LINST register” → “Set by ....the B0CLR bit in the LINST register” Figure 19.9 revised Figure 19.12 revised Figure 20.23: Title is revised Figure 20.24: Title is revised Figure 21.2 NOTE4 deleted Table 22.9 Parameter: “High-speed on-chip oscillator temperature supply voltage dependence” → “High-speed on-chip oscillator frequency temperature • supply voltage dependence” Appendix Figure 2.1 revised Table 1.1 I/O Ports: “• Output-only: 1” added “• CMOS I/O ports: 28” → “• CMOS I/O ports: 27” Figure 1.2 revised C-1 233 236 268 270 276 282 317 0.20 Nov 12, 2007 2 4 REVISION HISTORY Rev. 0.20 Date Nov 12, 2007 R8C/2G Group Hardware Manual Description Page 5 6 7 12 16 Figure 1.3 revised Summary Table 1.3 Pin Number: 4, 6, 20 revised Table 1.4 I/O port: “P4_3 to P4_5” → “P4_3, P4_5” Output port added Table 4.1 0006h “01001000b” → “01011000b” Table 4.5 0118h to 011Dh: After reset revised 011Fh “Timer RE Real-Time Clock Precision Adjust Register” added Figure 6.13 revised 8. “There are 28 I/O ports ...... oscillation circuit is not used.” → “There are 27 I/O ports ...... used as an output port.” Table 8.1 revised, NOTE3 added Figure 8.3 revised Figure 8.5 NOTE3 “To use port P4_4 as ... an input port.” added Figure 8.7 b7 revised Figure 8.9 PUR1: b1 revised Table 8.4 revised Table 8.26 NOTE2 added, Table 8.27 revised Table 8.29, Table 8.32 revised 8.6 added Table 11.1 Oscillator status after reset: XCIN Clock Oscillation Circuit “Stop” → “Oscillate” Figure 11.2 revised 11.2 “During and after reset, the XCIN clock stops.” → “During and after reset, the XCIN clock oscillates.” Figure 17.1 “TSTART” → “TCSTF” Figure 17.26 revised Table 17.11 Select function revised Figure 17.27, Figure 17.28 After Reset “00h” → “Undefined” Figure 17.29 After Reset “00h” → “X0XXXXXXb” Figure 17.30 After Reset “00h” → “X0000XXXb” Figure 17.31 After Reset “00h” → “XXX0X0X0b” Figure 17.33 After Reset “00h” → “00XXXXXXb” Figure 17.35 added Figure 17.37 revised Table 17.13 Select functions: Specification revised Figure 17.38, Figure 17.39 After Reset “00h” → “Undefined” Figure 17.40 After Reset “00h” → “XXX0X0X0b” Figure 17.41 After Reset “00h” → “00XXXXXXb” 17.3.3.1 NOTE revised 45 61 65 67 69 70 71 77 78 80 83 85 93 141 179 180 181 182 183 184 185 187 188 189 190 193 C-2 REVISION HISTORY Rev. 0.20 Date Nov 12, 2007 R8C/2G Group Hardware Manual Description Page 194 200 234 279 309 Figure 17.44 revised Figure 17.50 NOTE4 added Figure 19.9 revised Table 22.2 NOTE2 revised Figure 23.4 revised Table 1.1 revised Summary 1.00 Apr 04, 2008 All pages “Under development” deleted 2 3 11 12 13 24 25 38, 51 48 53, 54 63, 64 107 144 161 171 235 238 244 248 250 251 253 Table 1.2 “(D): Under development” deleted Figure 3.1 “Expanded area” deleted Table 4.1 “002Eh” “002Fh” revised Table 4.2 “003Eh” “003Fh” revised Figure 5.1 NOTE1 added Table 5.2 revised Figure 6.8, Figure 7.5; “7. The VW2C7 ... 1.” → “7. The VW2C7 ... 0.” Figure 7.2 added Figure 7.9, Figure 7.10 added 7.6, Figure 7.16, Figure 7.17 added 12, Figure 12.1; “BGRCR, and BGRTRM” added Table 17.1 Timer RF “Capture interrupt” added Figure 17.12 “TSTRAT” → “TSTART” Table 17.9 “TRBP pin function” → “TRBO pin function” Figure 19.6 “Three to five ...” → “One to two ...” Figure 19.9 revised Table 20.1 “Suspend function” deleted 20.4 “The flash module ... (EW1 mode).” deleted Table 20.3 “... to erase-suspend” “... to program-suspend” deleted • FMR00 Bit “(including suspend periods)” deleted Table 20.4 “FRM0 Register ...” → “FMR0 Register ...” Figure 20.5 revised • FMR40 Bit, • FMR41 Bit, • FMR42 Bit, • FMR43 Bit, • FMR44 Bit, • FMR46 Bit; deleted Figure 20.8 revised • Program Command; revised Old Figure 20.11 deleted • Block Erase; revised Old Figure 20.13, Old 20.4.3.2, Old Figure 20.14, Old Figure 20.15; deleted Figure 20.13 revised • Program Command; revised Old Figure 20.19 deleted C-3 256 258 259 262 263 REVISION HISTORY Rev. 1.00 Date Apr 04, 2008 R8C/2G Group Hardware Manual Description Page 264 Summary • Block Erase; revised Old Figure 20.21, Old 20.4.4.2, Old Figure 20.22, Old Figure 20.23; deleted Table 20.6 revised Table 20.7 “P4_4 input/clock output” → “P4_4 output/clock output” Old 20.7.1.7, Old 20.7.1.8 deleted Table 22.3 revised Figure 22.2 deleted Table 22.8, Table 22.11 revised Table 22.9 revised, NOTE3 added Table 22.13 revised Table 22.19 revised Table 22.25 revised Old 23.9.1.7, Old 23.9.1.8 deleted 265 267 270 276 279 281 285 289 311 C-4 R8C/2G Group Hardware Manual Publication Date: Rev.0.01 Rev.1.00 Mar 30, 2007 Apr 04, 2008 Published by: Sales Strategic Planning Div. Renesas Technology Corp. © 2008. Renesas Technology Corp., All rights reserved. Printed in Japan R8C/2G Group Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan