R5F21347WJFP

Preliminary DATASHEET Specifications in this document are tentative and subject to change. R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group REJ03B0312-0010 Rev.0.10 Apr 09, 2010 RENESAS MCU 1. 1.1 Overview Features The R8C/34W Group, R8C/34X Group, R8C/34Y Group, and R8C/34Z Group of single-chip MCUs incorporate the R8C CPU core, employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high speed. In addition, the CPU core boasts a multiplier for high-speed operation processing. Power consumption is low, and the supported operating modes allow additional power control. These MCUs are designed to maximize EMI/EMS performance. Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of system components. The R8C/34W Group and R8C/34X Group have a single channel CAN module and are suitable for LAN systems in vehicles and for FA. The R8C/34Y Group and R8C/34Z Group do not have CAN modules. The R8C/34W Group and R8C/34Y Group have data flash (1 KB × 4 blocks) with the background operation (BGO) function. 1.1.1 Applications Automobiles and others REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 1 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 1. Overview R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group 1.1.2 Specifications Tables 1.1 and 1.2 outline the Specifications for R8C/34W Group, tables 1.3 and 1.4 outline the Specifications for R8C/34X Group, tables 1.5 and 1.6 outline the Specifications for R8C/34Y Group, and tables 1.7 and 1.8 outline the Specifications for R8C/34Z Group. Table 1.1 Item CPU Specifications for R8C/34W Group (1) Function Central processing unit Specification R8C CPU core • Number of fundamental instructions: 89 • Minimum instruction execution time: 50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V) • Multiplier: 16 bits × 16 bits → 32 bits • Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits • Operating mode: Single-chip mode (address space: 1 Mbyte) Refer to Table 1.9 Product List for R8C/34W Group. • Power-on reset • Voltage detection 3 (detection level of voltage detection 1 selectable) • Input-only: 1 pin • CMOS I/O ports: 43, selectable pull-up resistor 3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor), High-speed on-chip oscillator (with frequency adjustment function), Low-speed on-chip oscillator • Oscillation stop detection: XIN clock oscillation stop detection function • Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16 • Low power consumption modes: Standard operating mode (high-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode • Interrupt vectors: 69 • External: 9 sources (INT × 5, key input × 4) • Priority levels: 7 levels • 14 bits × 1 (with prescaler) • Reset start selectable • Low-speed on-chip oscillator for watchdog timer selectable • 1 channel • Activation sources: 31 • Transfer modes: 2 (normal mode, repeat mode) 8 bits (with 8-bit prescaler) × 1 Timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode 8 bits (with 8-bit prescaler) × 1 Timer mode (period timer), programmable waveform generation mode (PWM output), programmable one-shot generation mode, programmable wait oneshot generation mode 16 bits (with 4 capture/compare registers) × 1 Timer mode (input capture function, output compare function), PWM mode (output 3 pins), PWM2 mode (PWM output pin) 16 bits (with 4 capture/compare registers) × 2 Timer mode (input capture function, output compare function), PWM mode (output 6 pins), reset synchronous PWM mode (output three-phase waveforms (6 pins), sawtooth wave modulation), complementary PWM mode (output three-phase waveforms (6 pins), triangular wave modulation), PWM3 mode (PWM output 2 pins with fixed period) 8 bits × 1 Output compare mode Memory ROM, RAM, Data flash Power Supply Voltage detection Voltage circuit Detection I/O Ports Programmable I/O ports Clock Clock generation circuits Interrupts Watchdog Timer DTC (Data Transfer Controller) Timer Timer RA Timer RB Timer RC Timer RD Timer RE REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 2 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 1. Overview R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 1.2 Item Serial Interface Specifications for R8C/34W Group (2) Function UART0 UART2 Specification 1 channel Clock synchronous serial I/O, UART 1 channel Clock synchronous serial I/O, UART, I2C mode (I2C-bus), IE mode (IEBus), multiprocessor communication function 1 channel Hardware LIN: 1 (timer RA, UART0) 1 channel, 16 Mailboxes (conforms to the ISO 11898-1) 10-bit resolution × 12 channels, includes sample and hold function, with sweep mode • Programming and erasure voltage: VCC = 2.7 to 5.5 V • Programming and erasure endurance: 10,000 times (data flash) 1,000 times (program ROM) • Program security: ROM code protect, ID code check • Debug functions: On-chip debug, on-board flash rewrite function • Background operation (BGO) function (data flash) f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V) Typ. 7 mA (VCC = 5.0 V, f(XIN) = 20 MHz) -40 to 85°C (J version) -40 to 125°C (K version) (1) 48-pin LQFP Package code: PLQP0048KB-A (previous code: 48P6Q-A) Synchronous Serial Communication Unit (SSU) LIN Module CAN Module A/D Converter Flash Memory Operating Frequency/Supply Voltage Current Consumption Operating Ambient Temperature Package Note: 1. Specify the K version if K version functions are to be used. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 3 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 1. Overview R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 1.3 Item CPU Specifications for R8C/34X Group (1) Function Central processing unit Specification R8C CPU core • Number of fundamental instructions: 89 • Minimum instruction execution time: 50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V) • Multiplier: 16 bits × 16 bits → 32 bits • Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits • Operating mode: Single-chip mode (address space: 1 Mbyte) Refer to Table 1.10 Product List for R8C/34X Group. • Power-on reset • Voltage detection 3 (detection level of voltage detection 1 selectable) • Input-only: 1 pin • CMOS I/O ports: 43, selectable pull-up resistor 3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor), High-speed on-chip oscillator (with frequency adjustment function), Low-speed on-chip oscillator • Oscillation stop detection: XIN clock oscillation stop detection function • Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16 • Low power consumption modes: Standard operating mode (high-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode • Interrupt vectors: 69 • External: 9 sources (INT × 5, key input × 4) • Priority levels: 7 levels • 14 bits × 1 (with prescaler) • Reset start selectable • Low-speed on-chip oscillator for watchdog timer selectable • 1 channel • Activation sources: 31 • Transfer modes: 2 (normal mode, repeat mode) 8 bits (with 8-bit prescaler) × 1 Timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode 8 bits (with 8-bit prescaler) × 1 Timer mode (period timer), programmable waveform generation mode (PWM output), programmable one-shot generation mode, programmable wait oneshot generation mode 16 bits (with 4 capture/compare registers) × 1 Timer mode (input capture function, output compare function), PWM mode (output 3 pins), PWM2 mode (PWM output pin) 16 bits (with 4 capture/compare registers) × 2 Timer mode (input capture function, output compare function), PWM mode (output 6 pins), reset synchronous PWM mode (output three-phase waveforms (6 pins), sawtooth wave modulation), complementary PWM mode (output three-phase waveforms (6 pins), triangular wave modulation), PWM3 mode (PWM output 2 pins with fixed period) 8 bits × 1 Output compare mode Memory ROM, RAM, Data flash Power Supply Voltage detection Voltage circuit Detection I/O Ports Programmable I/O ports Clock Clock generation circuits Interrupts Watchdog Timer DTC (Data Transfer Controller) Timer Timer RA Timer RB Timer RC Timer RD Timer RE REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 4 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 1. Overview R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 1.4 Item Serial Interface Specifications for R8C/34X Group (2) Function UART0 UART2 Specification 1 channel Clock synchronous serial I/O, UART 1 channel Clock synchronous serial I/O, UART, I2C mode (I2C-bus), IE mode (IEBus), multiprocessor communication function 1 channel Hardware LIN: 1 (timer RA, UART0) 1 channel, 16 Mailboxes (conforms to the ISO 11898-1) 10-bit resolution × 12 channels, includes sample and hold function, with sweep mode • Programming and erasure voltage: VCC = 2.7 to 5.5 V • Programming and erasure endurance: 100 times (program ROM) • Program security: ROM code protect, ID code check • Debug functions: On-chip debug, on-board flash rewrite function f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V) Typ. 7 mA (VCC = 5.0 V, f(XIN) = 20 MHz) -40 to 85°C (J version) -40 to 125°C (K version) (1) 48-pin LQFP Package code: PLQP0048KB-A (previous code: 48P6Q-A) Synchronous Serial Communication Unit (SSU) LIN Module CAN Module A/D Converter Flash Memory Operating Frequency/Supply Voltage Current Consumption Operating Ambient Temperature Package Note: 1. Specify the K version if K version functions are to be used. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 5 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 1. Overview R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 1.5 Item CPU Specifications for R8C/34Y Group (1) Function Central processing unit Specification R8C CPU core • Number of fundamental instructions: 89 • Minimum instruction execution time: 50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V) • Multiplier: 16 bits × 16 bits → 32 bits • Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits • Operating mode: Single-chip mode (address space: 1 Mbyte) Refer to Table 1.11 Product List for R8C/34Y Group. • Power-on reset • Voltage detection 3 (detection level of voltage detection 1 selectable) • Input-only: 1 pin • CMOS I/O ports: 43, selectable pull-up resistor 3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor), High-speed on-chip oscillator (with frequency adjustment function), Low-speed on-chip oscillator • Oscillation stop detection: XIN clock oscillation stop detection function • Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16 • Low power consumption modes: Standard operating mode (high-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode • Interrupt vectors: 69 • External: 9 sources (INT × 5, key input × 4) • Priority levels: 7 levels • 14 bits × 1 (with prescaler) • Reset start selectable • Low-speed on-chip oscillator for watchdog timer selectable • 1 channel • Activation sources: 31 • Transfer modes: 2 (normal mode, repeat mode) 8 bits (with 8-bit prescaler) × 1 Timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode 8 bits (with 8-bit prescaler) × 1 Timer mode (period timer), programmable waveform generation mode (PWM output), programmable one-shot generation mode, programmable wait oneshot generation mode 16 bits (with 4 capture/compare registers) × 1 Timer mode (input capture function, output compare function), PWM mode (output 3 pins), PWM2 mode (PWM output pin) 16 bits (with 4 capture/compare registers) × 2 Timer mode (input capture function, output compare function), PWM mode (output 6 pins), reset synchronous PWM mode (output three-phase waveforms (6 pins), sawtooth wave modulation), complementary PWM mode (output three-phase waveforms (6 pins), triangular wave modulation), PWM3 mode (PWM output 2 pins with fixed period) 8 bits × 1 Output compare mode Memory ROM, RAM, Data flash Power Supply Voltage detection Voltage circuit Detection I/O Ports Programmable I/O ports Clock Clock generation circuits Interrupts Watchdog Timer DTC (Data Transfer Controller) Timer Timer RA Timer RB Timer RC Timer RD Timer RE REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 6 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 1. Overview R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 1.6 Item Serial Interface Specifications for R8C/34Y Group (2) Function UART0 UART2 Specification 1 channel Clock synchronous serial I/O, UART 1 channel Clock synchronous serial I/O, UART, I2C mode (I2C-bus), IE mode (IEBus), multiprocessor communication function 1 channel Hardware LIN: 1 (timer RA, UART0) 10-bit resolution × 12 channels, includes sample and hold function, with sweep mode • Programming and erasure voltage: VCC = 2.7 to 5.5 V • Programming and erasure endurance: 10,000 times (data flash) 1,000 times (program ROM) • Program security: ROM code protect, ID code check • Debug functions: On-chip debug, on-board flash rewrite function • Background operation (BGO) function (data flash) f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V) Typ. 7 mA (VCC = 5.0 V, f(XIN) = 20 MHz) -40 to 85°C (J version) -40 to 125°C (K version) (1) 48-pin LQFP Package code: PLQP0048KB-A (previous code: 48P6Q-A) Synchronous Serial Communication Unit (SSU) LIN Module A/D Converter Flash Memory Operating Frequency/Supply Voltage Current Consumption Operating Ambient Temperature Package Note: 1. Specify the K version if K version functions are to be used. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 7 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 1. Overview R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 1.7 Item CPU Specifications for R8C/34Z Group (1) Function Central processing unit Specification R8C CPU core • Number of fundamental instructions: 89 • Minimum instruction execution time: 50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V) • Multiplier: 16 bits × 16 bits → 32 bits • Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits • Operating mode: Single-chip mode (address space: 1 Mbyte) Refer to Table 1.12 Product List for R8C/34Z Group. • Power-on reset • Voltage detection 3 (detection level of voltage detection 1 selectable) • Input-only: 1 pin • CMOS I/O ports: 43, selectable pull-up resistor 3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor), High-speed on-chip oscillator (with frequency adjustment function), Low-speed on-chip oscillator • Oscillation stop detection: XIN clock oscillation stop detection function • Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16 • Low power consumption modes: Standard operating mode (high-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode • Interrupt vectors: 69 • External: 9 sources (INT × 5, key input × 4) • Priority levels: 7 levels • 14 bits × 1 (with prescaler) • Reset start selectable • Low-speed on-chip oscillator for watchdog timer selectable • 1 channel • Activation sources: 31 • Transfer modes: 2 (normal mode, repeat mode) 8 bits (with 8-bit prescaler) × 1 Timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode 8 bits (with 8-bit prescaler) × 1 Timer mode (period timer), programmable waveform generation mode (PWM output), programmable one-shot generation mode, programmable wait oneshot generation mode 16 bits (with 4 capture/compare registers) × 1 Timer mode (input capture function, output compare function), PWM mode (output 3 pins), PWM2 mode (PWM output pin) 16 bits (with 4 capture/compare registers) × 2 Timer mode (input capture function, output compare function), PWM mode (output 6 pins), reset synchronous PWM mode (output three-phase waveforms (6 pins), sawtooth wave modulation), complementary PWM mode (output three-phase waveforms (6 pins), triangular wave modulation), PWM3 mode (PWM output 2 pins with fixed period) 8 bits × 1 Output compare mode ROM, RAM, Data flash Power Supply Voltage detection Voltage circuit Detection I/O Ports Programmable I/O ports Clock Clock generation circuits Memory Interrupts Watchdog Timer DTC (Data Transfer Controller) Timer Timer RA Timer RB Timer RC Timer RD Timer RE REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 8 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 1. Overview R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 1.8 Item Serial Interface Specifications for R8C/34Z Group (2) Function UART0 UART2 Specification 1 channel Clock synchronous serial I/O, UART 1 channel Clock synchronous serial I/O, UART, I2C mode (I2C-bus), IE mode (IEBus), multiprocessor communication function 1 channel Hardware LIN: 1 (timer RA, UART0) 10-bit resolution × 12 channels, includes sample and hold function, with sweep mode • Programming and erasure voltage: VCC = 2.7 to 5.5 V • Programming and erasure endurance: 100 times (program ROM) • Program security: ROM code protect, ID code check • Debug functions: On-chip debug, on-board flash rewrite function f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V) Typ. 7 mA (VCC = 5.0 V, f(XIN) = 20 MHz) -40 to 85°C (J version) -40 to 125°C (K version) (1) 48-pin LQFP Package code: PLQP0048KB-A (previous code: 48P6Q-A) Synchronous Serial Communication Unit (SSU) LIN Module A/D Converter Flash Memory Operating Frequency/Supply Voltage Current Consumption Operating Ambient Temperature Package Note: 1. Specify the K version if K version functions are to be used. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 9 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 1. Overview R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group 1.2 Product List Table 1.9 lists Product List for R8C/34W Group, Table 1.10 lists Product List for R8C/34X Group, Table 1.11 lists Product List for R8C/34Y Group, and Table 1.12 lists Product List for R8C/34Z Group. Table 1.9 Product List for R8C/34W Group ROM Capacity Program ROM Data flash 32 Kbytes 1 Kbyte × 4 48 Kbytes 1 Kbyte × 4 64 Kbytes 1 Kbyte × 4 96 Kbytes 1 Kbyte × 4 128 Kbytes 1 Kbyte × 4 32 Kbytes 1 Kbyte × 4 48 Kbytes 1 Kbyte × 4 64 Kbytes 1 Kbyte × 4 96 Kbytes 1 Kbyte × 4 128 Kbytes 1 Kbyte × 4 RAM Capacity 2.5 Kbytes 4 Kbytes 6 Kbytes 8 Kbytes 10 Kbytes 2.5 Kbytes 4 Kbytes 6 Kbytes 8 Kbytes 10 Kbytes Current of Apr. 2010 Package Type PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A Remarks J version Part No. R5F21346WJFP (D) R5F21347WJFP (D) R5F21348WJFP (D) R5F2134AWJFP (D) R5F2134CWJFP (D) R5F21346WKFP (D) R5F21347WKFP (D) R5F21348WKFP (D) R5F2134AWKFP (D) R5F2134CWKFP (D) (D): Under development K version Part No. R 5 F 21 34 6 W J FP Package type: FP: PLQP0048KB-A (0.5 mm pin-pitch, 7 mm square body) CAN, Data Flash W: CAN module and Data Flash X : CAN module but no Data Flash Y : Data Flash but no CAN module Z : None Classification J: Operating ambient temperature −40 °C to 85 °C K: Operating ambient temperature −40 °C to 125 °C ROM capacity 6: 32 KB 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/34W Group R8C/3x Series Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.1 Part Number, Memory Size, and Package of R8C/34W Group REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 10 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 1. Overview R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 1.10 Product List for R8C/34X Group ROM Capacity Part No. RAM Capacity Program ROM R5F21346XJFP (D) 32 Kbytes 2.5 Kbytes R5F21347XJFP (D) 48 Kbytes 4 Kbytes R5F21348XJFP (D) 64 Kbytes 6 Kbytes R5F2134AXJFP (D) 96 Kbytes 8 Kbytes R5F2134CXJFP (D) 128 Kbytes 10 Kbytes R5F21346XKFP (D) 32 Kbytes 2.5 Kbytes R5F21347XKFP (D) 48 Kbytes 4 Kbytes R5F21348XKFP (D) 64 Kbytes 6 Kbytes R5F2134AXKFP (D) 96 Kbytes 8 Kbytes R5F2134CXKFP (D) 128 Kbytes 10 Kbytes Current of Apr. 2010 Package Type PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A Remarks J version K version (D): Under development Part No. R 5 F 21 34 6 X J FP Package type: FP: PLQP0048KB-A (0.5 mm pin-pitch, 7 mm square body) CAN, Data Flash W: CAN module and Data Flash X : CAN module but no Data Flash Y : Data Flash but no CAN module Z : None Classification J: Operating ambient temperature −40 °C to 85 °C K: Operating ambient temperature −40 °C to 125 °C ROM capacity 6: 32 KB 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/34X Group R8C/3x Series Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.2 Part Number, Memory Size, and Package of R8C/34X Group REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 11 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 1. Overview R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 1.11 Product List for R8C/34Y Group ROM Capacity Part No. Program ROM Data flash R5F21346YJFP (D) 32 Kbytes 1 Kbyte × 4 R5F21347YJFP (D) 48 Kbytes 1 Kbyte × 4 R5F21348YJFP (D) 64 Kbytes 1 Kbyte × 4 R5F2134AYJFP (D) 96 Kbytes 1 Kbyte × 4 R5F2134CYJFP (D) 128 Kbytes 1 Kbyte × 4 R5F21346YKFP (D) 32 Kbytes 1 Kbyte × 4 R5F21347YKFP (D) 48 Kbytes 1 Kbyte × 4 R5F21348YKFP (D) 64 Kbytes 1 Kbyte × 4 R5F2134AYKFP (D) 96 Kbytes 1 Kbyte × 4 R5F2134CYKFP (D) 128 Kbytes 1 Kbyte × 4 Current of Apr. 2010 RAM Capacity 2.5 Kbytes 4 Kbytes 6 Kbytes 8 Kbytes 10 Kbytes 2.5 Kbytes 4 Kbytes 6 Kbytes 8 Kbytes 10 Kbytes Package Type PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A Remarks J version K version (D): Under development Part No. R 5 F 21 34 6 Y J FP Package type: FP: PLQP0048KB-A (0.5 mm pin-pitch, 7 mm square body) CAN, Data Flash W: CAN module and Data Flash X : CAN module but no Data Flash Y : Data Flash but no CAN module Z : None Classification J: Operating ambient temperature −40 °C to 85 °C K: Operating ambient temperature −40 °C to 125 °C ROM capacity 6: 32 KB 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/34Y Group R8C/3x Series Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.3 Part Number, Memory Size, and Package of R8C/34Y Group REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 12 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 1. Overview R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 1.12 Product List for R8C/34Z Group ROM Capacity Part No. RAM Capacity Program ROM R5F21346ZJFP (D) 32 Kbytes 2.5 Kbytes R5F21347ZJFP (D) 48 Kbytes 4 Kbytes R5F21348ZJFP (D) 64 Kbytes 6 Kbytes R5F2134AZJFP (D) 96 Kbytes 8 Kbytes R5F2134CZJFP (D) 128 Kbytes 10 Kbytes R5F21346ZKFP (D) 32 Kbytes 2.5 Kbytes R5F21347ZKFP (D) 48 Kbytes 4 Kbytes R5F21348ZKFP (D) 64 Kbytes 6 Kbytes R5F2134AZKFP (D) 96 Kbytes 8 Kbytes R5F2134CZKFP (D) 128 Kbytes 10 Kbytes Current of Apr. 2010 Package Type PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A Remarks J version K version (D): Under development Part No. R 5 F 21 34 6 Z J FP Package type: FP: PLQP0048KB-A (0.5 mm pin-pitch, 7 mm square body) CAN, Data Flash W: CAN module and Data Flash X : CAN module but no Data Flash Y : Data Flash but no CAN module Z : None Classification J: Operating ambient temperature −40 °C to 85 °C K: Operating ambient temperature −40 °C to 125 °C ROM capacity 6: 32 KB 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/34Z Group R8C/3x Series Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.4 Part Number, Memory Size, and Package of R8C/34Z Group REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 13 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 1. Overview R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group 1.3 Block Diagram Figure 1.5 shows a Block Diagram. 8 8 8 6 5 1 8 I/O ports Peripheral functions Timers Timer RA (8 bits) Timer RB (8 bits) Timer RC (16 bits) Timer RD (16 bits × 2) Timer RE (8 bits) Port P0 Port P1 Port P2 Port P3 Port P4 Port 6 A/D converter (10 bits × 12 channels) UART or clock synchronous serial I/O (8 bits × 2 channels) System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator SSU (8 bits × 1 channel) DTC Watchdog timer (14 bits) CAN module (3) (1 channel) LIN module (1 channel) R8C CPU core R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG Memory ROM (1) RAM (2) Multiplier Notes: 1. ROM size varies with MCU type. 2. RAM size varies with MCU type. 3. Only in the R8C/34W Group and R8C/34X Group. Figure 1.5 Block Diagram REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 14 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 1. Overview R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group 1.4 Pin Assignment Figure 1.6 shows Pin Assignment (Top View). Tables 1.13 and 1.14 outline the Pin Name Information by Pin Number. 36 P0_6/AN1 P0_5/AN2 P0_4/TREO/AN3 VREF/P4_2(3) P6_0/(TREO)(1) P6_2/CRX0(2) P6_1/CTX0(2) P0_3/AN4 P0_2/AN5 P0_1/AN6 P0_0/AN7 P3_7/(TRAO)(1)/(TXD2)/(SDA2)/(RXD2)/(SCL2)(1)/SSO 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 P0_7/AN0 P6_3 P6_4 P6_5/INT4/(CLK2)(1) P3_0/(TRAO)(1) P3_1/(TRBO)(1) P1_0/KI0/AN8 P1_1/KI1/TRCIOA/TRCTRG/AN9 P1_2/KI2/TRCIOB/AN10 P6_7/(INT3)(1)/TRCIOD/(RXD2)/(SCL2)(1) P6_6/INT2/TRCIOC/(TXD2)/(SDA2)(1) P4_5/INT0/ADTRG 35 34 33 32 31 30 29 28 27 26 25 24 23 R8C/34W Group R8C/34X Group R8C/34Y Group R8C/34Z Group PLQP0048KB-A (48P6Q-A) (Top view) 22 21 20 19 18 17 16 15 14 13 P1_3/KI3/TRBO/AN11 P1_4/TRCCLK/TXD0 P1_5/(INT1)(1)/(TRAIO)(1)/RXD0 P1_6/CLK0 P1_7/INT1/(TRAIO)(1) P2_0/TRDIOA0/TRDCLK P2_1/TRDIOB0 P2_2/TRDIOC0 P2_3/TRDIOD0 P2_4/TRDIOA1 P2_5/TRDIOB1 P2_6/TRDIOC1 Notes: 1. Can be assigned to the pin in parentheses by a program. 2. Only in the R8C/34W Group and R8C/34X Group. 3. P4_2 is an input-only pin. 4. Confirm the pin 1 position on the package by referring to the Package Dimensions. Figure 1.6 Pin Assignment (Top View) REJ03B0312-0010 Rev.0.10 Apr 09, 2010 P3_5/(CLK2)(1)/SSCK P3_3/INT3/CTS2/RTS2/(SSI)(1)/SCS P3_4/(TXD2)/(SDA2)/(RXD2)/(SCL2)(1)/SSI/(SCS)(1) MODE P4_3 P4_4 RESET XOUT/P4_7 VSS/AVSS XIN/P4_6 VCC/AVCC P2_7/TRDIOD1 Page 15 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 1. Overview R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 1.13 Pin Number Pin Name Information by Pin Number (1) I/O Pin Functions for Peripheral Modules Port CAN Module (2) A/D Converter Voltage Detection Circuit Control Pin Interrupt Timer Serial Interface (CLK2) (1) SSU SSCK (SSI) (1)/SCS 1 2 P3_5 P3_3 INT3 CTS2/RTS2 (TXD2)/(SDA2)/ (RXD2)/(SCL2) (1) 3 P3_4 SSI/(SCS) (1) 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 MODE P4_3 P4_4 RESET XOUT VSS/AVSS XIN VCC/AVCC P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P4_5 P6_6 KI3 INT0 INT2 TRCIOC (TXD2)/(SDA2) (1) P4_7 P4_6 TRDIOD1 TRDIOC1 TRDIOB1 TRDIOA1 TRDIOD0 TRDIOC0 TRDIOB0 TRDIOA0/ TRDCLK INT1 (TRAIO) (1) CLK0 INT1 (1) (TRAIO) (1) RXD0 TXD0 AN11 ADTRG TRCCLK TRBO Notes: 1. This can be assigned to the pin in parentheses by a program. 2. Only for the R8C/34W Group and R8C/34X Group. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 16 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 1. Overview R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 1.14 Pin Number Pin Name Information by Pin Number (2) I/O Pin Functions for Peripheral Modules Port CAN Module (2) A/D Converter Voltage Detection Circuit Control Pin Interrupt INT3 (1) KI2 KI1 KI0 Timer TRCIOD TRCIOB TRCIOA/ TRCTRG Serial Interface (RXD2)/(SCL2) (1) SSU 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 P6_7 P1_2 P1_1 P1_0 P3_1 P3_0 P6_5 P6_4 P6_3 P0_7 P0_6 P0_5 P0_4 P4_2 P6_0 P6_2 P6_1 P0_3 P0_2 P0_1 P0_0 AN10 AN9 AN8 (TRBO) (1) (TRAO) (1) INT4 (CLK2) (1) AN0 AN1 AN2 TREO AN3 VREF (TREO) (1) CRX0 (2) CTX0 (2) AN4 AN5 AN6 AN7 (TRAO) (1) 48 P3_7 (TXD2)/(SDA2)/ (RXD2)/(SCL2) (1) SSO Notes: 1. This can be assigned to the pin in parentheses by a program. 2. Only for the R8C/34W Group and R8C/34X Group. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 17 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 1. Overview R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group 1.5 Pin Functions Tables 1.15 and 1.16 list Pin Functions. Table 1.15 Item Analog power supply input Reset input MODE XIN clock input XIN clock output INT interrupt input Key input interrupt Timer RA Timer RB Timer RC Pin Functions (1) Pin Name AVCC, AVSS RESET MODE XIN XOUT INT0 to INT4 KI0 to KI3 TRAIO TRAO TRBO TRCCLK TRCTRG TRCIOA, TRCIOB, TRCIOC, TRCIOD I/O Type − − I I I I/O I I I/O O O I I I/O I/O Description Apply 2.7 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin. Power supply for the A/D converter. Connect a capacitor between AVCC and AVSS. Input “L” on this pin resets the MCU. Connect this pin to VCC via a resistor. These pins are provided for XIN clock generation circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins (1). To use an external clock, input it to the XOUT pin and leave the XIN pin open. INT interrupt input pins. Key input interrupt input pins Timer RA I/O pin Timer RA output pin Timer RB output pin External clock input pin External trigger input pin Timer RC I/O pins Timer RD I/O pins Power supply input VCC, VSS Timer RD TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 TRDCLK TREO CLK0, CLK2 RXD0, RXD2 TXD0, TXD2 CTS2 RTS2 SCL2 SDA2 I O I/O I O I O I/O I/O I/O I/O I/O I/O External clock input pin Divided clock output pin Transfer clock I/O pins Serial data input pins Serial data output pins Transmission control input pin Reception control output pin I2C mode clock I/O pin I2C mode data I/O pin Data I/O pin Chip-select signal I/O pin Clock I/O pin Data I/O pin Timer RE Serial interface SSU SSI SCS SSCK SSO I: Input O: Output I/O: Input and output Note: 1. Refer to the oscillator manufacturer for oscillation characteristics. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 18 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 1. Overview R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 1.16 Item CAN module Pin Functions (2) Pin Name CRX0 CTX0 VREF AN0 to AN11 ADTRG P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_7, P6_0 to P6_7 P4_2 O: Output (1) (1) I/O Type I O I I I I/O CAN data input pin CAN data output pin Description Reference voltage input A/D converter I/O port Reference voltage input pin to A/D converter Analog input pins to A/D converter AD external trigger input pin CMOS I/O ports. Each port has an I/O select direction register, allowing each pin in the port to be directed for input or output individually. Any port set to input can be set to use a pull-up resistor or not by a program. Input port I: Input Note: I I/O: Input and output Input-only ports 1. Only in the R8C/34W Group and R8C/34X Group. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 19 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 2. Central Processing Unit (CPU) R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank. b31 b15 b8b7 b0 R2 R3 R0H (high-order of R0) R0L (low-order of R0) R1H (high-order of R1) R1L (low-order of R1) Data registers (1) R2 R3 A0 A1 FB b19 b15 b0 Address registers (1) Frame base register (1) INTBH INTBL Interrupt table register The 4 high order bits of INTB are INTBH and the 16 low order bits of INTB are INTBL. b19 b0 PC Program counter b15 b0 USP ISP SB b15 b0 User stack pointer Interrupt stack pointer Static base register FLG b15 b8 b7 b0 Flag register IPL U I OBSZDC Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bit Processor interrupt priority level Reserved bit Note: 1. These registers comprise a register bank. There are two register banks. Figure 2.1 CPU Registers REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 20 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 2. Central Processing Unit (CPU) R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group 2.1 Data Registers (R0, R1, R2, and R3) R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is analogous to R2R0. 2.2 Address Registers (A0 and A1) A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0). 2.3 Frame Base Register (FB) FB is a 16-bit register for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is a 20-bit register that indicates the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is 20 bits wide and indicates the address of the next instruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between USP and ISP. 2.7 Static Base Register (SB) SB is a 16-bit register for SB relative addressing. 2.8 Flag Register (FLG) FLG is an 11-bit register indicating the CPU state. 2.8.1 Carry Flag (C) The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 Debug Flag (D) The D flag is for debugging only. Set it to 0. 2.8.3 Zero Flag (Z) The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 Sign Flag (S) The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 Register Bank Select Flag (B) Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1. 2.8.6 Overflow Flag (O) The O flag is set to 1 when an operation results in an overflow; otherwise to 0. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 21 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 2. Central Processing Unit (CPU) R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group 2.8.7 Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged. 2.8.8 Stack Pointer Select Flag (U) ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1. The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled. 2.8.10 Reserved Bit If necessary, set to 0. When read, the content is undefined. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 22 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 3. Memory R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group 3. 3.1 Memory R8C/34W Group Figure 3.1 is a Memory Map of R8C/34W Group. The R8C/34W Group has a 1-Mbyte address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt routine is stored here. The internal ROM (data flash) is allocated addresses 03000h to 03FFFh. The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 4-Kbyte internal RAM area is allocated addresses 00400h to 013FFh. The internal RAM is used not only for data storage but also as a stack area when a subroutine is called or when an interrupt request is acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh (the SFR areas for the CAN, DTC, and other modules). Peripheral function control registers are allocated here. All unallocated spaces within the SFRs are reserved and cannot be accessed by users. 00000h SFR 002FFh 00400h (Refer to 4. Special Function Registers (SFRs)) Internal RAM 0XXXXh 02C00h 02FFFh 03000h SFR (2) 0FFDCh (Refer to 4. Special Function Registers (SFRs)) Internal ROM (data flash) (1) 03FFFh 0YYYYh Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer, oscillation stop detection, voltage monitor Internal ROM (program ROM) 0FFFFh 0FFFFh Address break (Reserved) Reset Internal ROM (program ROM) ZZZZZh FFFFFh Notes: 1. The Data Flash memory indicates blocks A (1 Kbyte), B (1 Kbyte), C (1 Kbyte), and D (1 Kbyte). 2. The SFR areas for the CAN, DTC and other modules are allocated to addresses 02C00h to 02FFFh. 3. The blank areas are reserved and cannot be accessed by users. Internal ROM Part Number R5F21346WJFP, R5F21346WKFP R5F21347WJFP, R5F21347WKFP R5F21348WJFP, R5F21348WKFP R5F2134AWJFP, R5F2134AWKFP R5F2134CWJFP, R5F2134CWKFP Size 32 Kbytes 48 Kbytes 64 Kbytes 96 Kbytes 128 Kbytes Address 0YYYYh 08000h 04000h 04000h 04000h 04000h 13FFFh 1BFFFh 23FFFh Address ZZZZZh Size 2.5 Kbytes 4 Kbytes 6 Kbytes 8 Kbytes 10 Kbytes Internal RAM Address 0XXXXh 00DFFh 013FFh 01BFFh 023FFh 02BFFh Figure 3.1 Memory Map of R8C/34W Group REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 23 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 3. Memory R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group 3.2 R8C/34X Group Figure 3.2 is a Memory Map of R8C/34X Group. The R8C/34X Group has a 1-Mbyte address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt routine is stored here. The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 4-Kbyte internal RAM area is allocated addresses 00400h to 013FFh. The internal RAM is used not only for data storage but also as a stack area when a subroutine is called or when an interrupt request is acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh (the SFR areas for the CAN, DTC, and other modules). Peripheral function control registers are allocated here. All unallocated spaces within the SFRs are reserved and cannot be accessed by users. 00000h SFR 002FFh 00400h (Refer to 4. Special Function Registers (SFRs)) Internal RAM 0XXXXh 02C00h SFR (1) 0FFDCh (Refer to 4. Special Function Registers (SFRs)) 02FFFh Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer, oscillation stop detection, voltage monitor 0YYYYh Internal ROM (program ROM) 0FFFFh 0FFFFh Address break (Reserved) Reset Internal ROM (program ROM) ZZZZZh FFFFFh Notes: 1. The SFR areas for the CAN, DTC and other modules are allocated to addresses 02C00h to 02FFFh. 2. The blank areas are reserved and cannot be accessed by users. Internal ROM Part Number R5F21346XJFP, R5F21346XKFP R5F21347XJFP, R5F21347XKFP R5F21348XJFP, R5F21348XKFP R5F2134AXJFP, R5F2134AXKFP R5F2134CXJFP, R5F2134CXKFP Size 32 Kbytes 48 Kbytes 64 Kbytes 96 Kbytes 128 Kbytes Address 0YYYYh 08000h 04000h 04000h 04000h 04000h 13FFFh 1BFFFh 23FFFh Address ZZZZZh Size 2.5 Kbytes 4 Kbytes 6 Kbytes 8 Kbytes 10 Kbytes Internal RAM Address 0XXXXh 00DFFh 013FFh 01BFFh 023FFh 02BFFh Figure 3.2 Memory Map of R8C/34X Group REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 24 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 3. Memory R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group 3.3 R8C/34Y Group Figure 3.3 is a Memory Map of R8C/34Y Group. The R8C/34Y Group has a 1-Mbyte address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt routine is stored here. The internal ROM (data flash) is allocated addresses 03000h to 03FFFh. The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 4-Kbyte internal RAM area is allocated addresses 00400h to 013FFh. The internal RAM is used not only for data storage but also as a stack area when a subroutine is called or when an interrupt request is acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh (the SFR areas for the DTC and other modules). Peripheral function control registers are allocated here. All unallocated spaces within the SFRs are reserved and cannot be accessed by users. 00000h SFR 002FFh 00400h (Refer to 4. Special Function Registers (SFRs)) Internal RAM 0XXXXh 02C00h 02FFFh 03000h SFR (2) 0FFDCh (Refer to 4. Special Function Registers (SFRs)) Internal ROM (data flash) (1) 03FFFh 0YYYYh Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer, oscillation stop detection, voltage monitor Internal ROM (program ROM) 0FFFFh 0FFFFh Address break (Reserved) Reset Internal ROM (program ROM) ZZZZZh FFFFFh Notes: 1. The Data Flash memory indicates blocks A (1 Kbyte), B (1 Kbyte), C (1 Kbyte), and D (1 Kbyte). 2. The SFR areas for the DTC and other modules are allocated to addresses 02C00h to 02FFFh. 3. The blank areas are reserved and cannot be accessed by users. Internal ROM Part Number R5F21346YJFP, R5F21346YKFP R5F21347YJFP, R5F21347YKFP R5F21348YJFP, R5F21348YKFP R5F2134AYJFP, R5F2134AYKFP R5F2134CYJFP, R5F2134CYKFP Size 32 Kbytes 48 Kbytes 64 Kbytes 96 Kbytes 128 Kbytes Address 0YYYYh 08000h 04000h 04000h 04000h 04000h 13FFFh 1BFFFh 23FFFh Address ZZZZZh Size 2.5 Kbytes 4 Kbytes 6 Kbytes 8 Kbytes 10 Kbytes Internal RAM Address 0XXXXh 00DFFh 013FFh 01BFFh 023FFh 02BFFh Figure 3.3 Memory Map of R8C/34Y Group REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 25 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 3. Memory R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group 3.4 R8C/34Z Group Figure 3.4 is a Memory Map of R8C/34Z Group. The R8C/34Z Group has a 1-Mbyte address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt routine is stored here. The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 4-Kbyte internal RAM area is allocated addresses 00400h to 013FFh. The internal RAM is used not only for data storage but also as a stack area when a subroutine is called or when an interrupt request is acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh (the SFR areas for the DTC and other modules). Peripheral function control registers are allocated here. All unallocated spaces within the SFRs are reserved and cannot be accessed by users. 00000h SFR 002FFh 00400h (Refer to 4. Special Function Registers (SFRs)) Internal RAM 0XXXXh 02C00h 02FFFh SFR (1) 0FFDCh (Refer to 4. Special Function Registers (SFRs)) Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer, oscillation stop detection, voltage monitor 0YYYYh Internal ROM (program ROM) 0FFFFh 0FFFFh Address break (Reserved) Reset Internal ROM (program ROM) ZZZZZh FFFFFh Notes: 1. The SFR areas for the DTC and other modules are allocated to addresses 02C00h to 02FFFh. 2. The blank areas are reserved and cannot be accessed by users. Internal ROM Part Number R5F21346ZJFP, R5F21346ZKFP R5F21347ZJFP, R5F21347ZKFP R5F21348ZJFP, R5F21348ZKFP R5F2134AZJFP, R5F2134AZKFP R5F2134CZJFP, R5F2134CZKFP Size 32 Kbytes 48 Kbytes 64 Kbytes 96 Kbytes 128 Kbytes Address 0YYYYh 08000h 04000h 04000h 04000h 04000h Address ZZZZZh Size 2.5 Kbytes 4 Kbytes 6 Kbytes 8 Kbytes 10 Kbytes Internal RAM Address 0XXXXh 00DFFh 013FFh 01BFFh 023FFh 02BFFh 13FFFh 1BFFFh 23FFFh Figure 3.4 Memory Map of R8C/34Z Group REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 26 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 4. Special Function Registers (SFRs) R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group 4. Special Function Registers (SFRs) An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.17 list the special function registers. Table 4.18 lists the ID Code Areas and Option Function Select Area. Table 4.1 Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h SFR Information (1) (1) Register Symbol After reset Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Module Standby Control Register System Clock Control Register 3 Protect Register Reset Source Determination Register Oscillation Stop Detection Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register PM0 PM1 CM0 CM1 MSTCR CM3 PRCR RSTFR OCD WDTR WDTS WDTC 00h 00h 00101000b 00100000b 00h 00h 00h 0XXXXXXXb (2) 00000100b XXh XXh 00111111b High-Speed On-Chip Oscillator Control Register 7 FRA7 When shipping Count Source Protection Mode Register CSPR 00h 10000000b (3) High-Speed On-Chip Oscillator Control Register 0 High-Speed On-Chip Oscillator Control Register 1 High-Speed On-Chip Oscillator Control Register 2 On-Chip Reference Voltage Control Register FRA0 FRA1 FRA2 OCVREFCR 00h When shipping 00h 00h High-Speed On-Chip Oscillator Control Register 4 High-Speed On-Chip Oscillator Control Register 5 High-Speed On-Chip Oscillator Control Register 6 FRA4 FRA5 FRA6 When Shipping When Shipping When Shipping High-Speed On-Chip Oscillator Control Register 3 Voltage Monitor Circuit Control Register Voltage Monitor Circuit Edge Select Register Voltage Detect Register 1 Voltage Detect Register 2 FRA3 CMPA VCAC VCA1 VCA2 When shipping 00h 00h 00001000b 00h (4) 00100000b (5) 00000111b 1100X010b (4) 1100X011b (5) 10001010b Voltage Detection 1 Level Select Register Voltage Monitor 0 Circuit Control Register VD1LS VW0C 0039h Voltage Monitor 1 Circuit Control Register VW1C X: Undefined Notes: 1. The blank areas are reserved and cannot be accessed by users. 2. The CWR bit in the RSTFR register is set to 0 after power-on and voltage monitor 0 reset. Hardware reset, Software reset, or watchdog timer reset does not affect this bit. 3. The CSPROINI bit in the OFS register is set to 0. 4. The LVDAS bit in the OFS register is set to 1. 5. The LVDAS bit in the OFS register is set to 0. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 27 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 4. Special Function Registers (SFRs) R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 4.2 SFR Information (2) (1) Symbol VW2C After reset 10000010b Address Register 003Ah Voltage Monitor 2 Circuit Control Register 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h Flash Memory Ready Interrupt Control Register 0042h 0043h 0044h 0045h 0046h INT4 Interrupt Control Register 0047h Timer RC Interrupt Control Register 0048h Timer RD0 Interrupt Control Register 0049h Timer RD1 Interrupt Control Register 004Ah Timer RE Interrupt Control Register 004Bh UART2 Transmit Interrupt Control Register 004Ch UART2 Receive Interrupt Control Register 004Dh Key Input Interrupt Control Register 004Eh A/D Conversion Interrupt Control Register 004Fh SSU Interrupt Control Register 0050h 0051h UART0 Transmit Interrupt Control Register 0052h UART0 Receive Interrupt Control Register 0053h 0054h 0055h INT2 Interrupt Control Register 0056h Timer RA Interrupt Control Register 0057h 0058h Timer RB Interrupt Control Register 0059h INT1 Interrupt Control Register 005Ah INT3 Interrupt Control Register 005Bh 005Ch 005Dh INT0 Interrupt Control Register 005Eh UART2 Bus Collision Detection Interrupt Control Register 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch CAN0 Successful Reception Interrupt Control Register 006Dh CAN0 Successful Transmission Interrupt Control Register 006Eh CAN0 Receive FIFO Interrupt Control Register 006Fh CAN0 Transmit FIFO Interrupt Control Register 0070h CAN0 Error Interrupt Control Register 0071h CAN0 Wake-up Interrupt Control Register 0072h Voltage Monitor 1 Level Interrupt Control Register 0073h Voltage Monitor 2 Level Interrupt Control Register 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. FMRDYIC XXXXX000b INT4IC TRCIC TRD0IC TRD1IC TREIC S2TIC S2RIC KUPIC ADIC SSUIC S0TIC S0RIC XX00X000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b INT2IC TRAIC TRBIC INT1IC INT3IC XX00X000b XXXXX000b XXXXX000b XX00X000b XX00X000b INT0IC U2BCNIC XX00X000b XXXXX000b C0RIC C0TIC C0FRIC C0FTIC C0EIC C0WIC VCMP1IC VCMP2IC XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 28 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 4. Special Function Registers (SFRs) R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 4.3 SFR Information (3) (1) Symbol DTCTL After reset 00h Address Register 0080h DTC Activation Control Register 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h DTC Activation Enable Register 0 0089h DTC Activation Enable Register 1 008Ah DTC Activation Enable Register 2 008Bh DTC Activation Enable Register 3 008Ch DTC Activation Enable Register 4 008Dh DTC Activation Enable Register 5 008Eh DTC Activation Enable Register 6 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h UART0 Transmit/Receive Mode Register 00A1h UART0 Bit Rate Register 00A2h UART0 Transmit Buffer Register 00A3h 00A4h UART0 Transmit/Receive Control Register 0 00A5h UART0 Transmit/Receive Control Register 1 00A6h UART0 Receive Buffer Register 00A7h 00A8h UART2 Transmit/Receive Mode Register 00A9h UART2 Bit Rate Register 00AAh UART2 Transmit Buffer Register 00ABh 00ACh UART2 Transmit/Receive Control Register 0 00ADh UART2 Transmit/Receive Control Register 1 00AEh UART2 Receive Buffer Register 00AFh 00B0h UART2 Digital Filter Function Select Register 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh UART2 Special Mode Register 5 00BCh UART2 Special Mode Register 4 00BDh UART2 Special Mode Register 3 00BEh UART2 Special Mode Register 2 00BFh UART2 Special Mode Register X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. DTCEN0 DTCEN1 DTCEN2 DTCEN3 DTCEN4 DTCEN5 DTCEN6 00h 00h 00h 00h 00h 00h 00h U0MR U0BRG U0TB U0C0 U0C1 U0RB U2MR U2BRG U2TB U2C0 U2C1 U2RB URXDF 00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h U2SMR5 U2SMR4 U2SMR3 U2SMR2 U2SMR 00h 00h 000X0X0Xb X0000000b X0000000b REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 29 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 4. Special Function Registers (SFRs) R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 4.4 SFR Information (4) (1) Symbol AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 After reset XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb Address Register 00C0h A/D Register 0 00C1h 00C2h A/D Register 1 00C3h 00C4h A/D Register 2 00C5h 00C6h A/D Register 3 00C7h 00C8h A/D Register 4 00C9h 00CAh A/D Register 5 00CBh 00CCh A/D Register 6 00CDh 00CEh A/D Register 7 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h A/D Mode Register 00D5h A/D Input Select Register 00D6h A/D Control Register 0 00D7h A/D Control Register 1 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h Port P0 Register 00E1h Port P1 Register 00E2h Port P0 Direction Register 00E3h Port P1 Direction Register 00E4h Port P2 Register 00E5h Port P3 Register 00E6h Port P2 Direction Register 00E7h Port P3 Direction Register 00E8h Port P4 Register 00E9h 00EAh Port P4 Direction Register 00EBh 00ECh Port P6 Register 00EDh 00EEh Port P6 Direction Register 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. ADMOD ADINSEL ADCON0 ADCON1 00h 11000000b 00h 00h P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 PD4 P6 PD6 XXh XXh 00h 00h XXh XXh 00h 00h XXh 00h XXh 00h REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 30 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 4. Special Function Registers (SFRs) R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 4.5 SFR Information (5) (1) Symbol TRACR TRAIOC TRAMR TRAPRE TRA LINCR2 LINCR LINST TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBSC TRBPR After reset 00h 00h 00h FFh FFh 00h 00h 00h 00h 00h 00h 00h FFh FFh FFh Address Register 0100h Timer RA Control Register 0101h Timer RA I/O Control Register 0102h Timer RA Mode Register 0103h Timer RA Prescaler Register 0104h Timer RA Register 0105h LIN Control Register 2 0106h LIN Control Register 0107h LIN Status Register 0108h Timer RB Control Register 0109h Timer RB One-Shot Control Register 010Ah Timer RB I/O Control Register 010Bh Timer RB Mode Register 010Ch Timer RB Prescaler Register 010Dh Timer RB Secondary Register 010Eh Timer RB Primary Register 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h Timer RE Counter Data Register 0119h Timer RE Compare Data Register 011Ah 011Bh 011Ch Timer RE Control Register 1 011Dh Timer RE Control Register 2 011Eh Timer RE Count Source Select Register 011Fh 0120h Timer RC Mode Register 0121h Timer RC Control Register 1 0122h Timer RC Interrupt Enable Register 0123h Timer RC Status Register 0124h Timer RC I/O Control Register 0 0125h Timer RC I/O Control Register 1 0126h Timer RC Counter 0127h 0128h Timer RC General Register A 0129h 012Ah Timer RC General Register B 012Bh 012Ch Timer RC General Register C 012Dh 012Eh Timer RC General Register D 012Fh 0130h Timer RC Control Register 2 0131h Timer RC Digital Filter Function Select Register 0132h Timer RC Output Master Enable Register 0133h Timer RC Trigger Control Register 0134h 0135h 0136h Timer RD Trigger Control Register 0137h Timer RD Start Register 0138h Timer RD Mode Register 0139h Timer RD PWM Mode Register 013Ah Timer RD Function Control Register 013Bh Timer RD Output Master Enable Register 1 013Ch Timer RD Output Master Enable Register 2 013Dh Timer RD Output Control Register 013Eh Timer RD Digital Filter Function Select Register 0 013Fh Timer RD Digital Filter Function Select Register 1 Note: 1. The blank areas are reserved and cannot be accessed by users. TRESEC TREMIN 00h 00h TRECR1 TRECR2 TRECSR TRCMR TRCCR1 TRCIER TRCSR TRCIOR0 TRCIOR1 TRC TRCGRA TRCGRB TRCGRC TRCGRD TRCCR2 TRCDF TRCOER TRCADCR 00h 00h 00001000b 01001000b 00h 01110000b 01110000b 10001000b 10001000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00011000b 00h 01111111b 00h TRDADCR TRDSTR TRDMR TRDPMR TRDFCR TRDOER1 TRDOER2 TRDOCR TRDDF0 TRDDF1 00h 11111100b 00001110b 10001000b 10000000b FFh 01111111b 00h 00h 00h REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 31 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 4. Special Function Registers (SFRs) R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 4.6 SFR Information (6) (1) Symbol TRDCR0 TRDIORA0 TRDIORC0 TRDSR0 TRDIER0 TRDPOCR0 TRD0 TRDGRA0 TRDGRB0 TRDGRC0 TRDGRD0 TRDCR1 TRDIORA1 TRDIORC1 TRDSR1 TRDIER1 TRDPOCR1 TRD1 TRDGRA1 TRDGRB1 TRDGRC1 TRDGRD1 After reset 00h 10001000b 10001000b 11100000b 11100000b 11111000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00h 10001000b 10001000b 11000000b 11100000b 11111000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh Address Register 0140h Timer RD Control Register 0 0141h Timer RD I/O Control Register A0 0142h Timer RD I/O Control Register C0 0143h Timer RD Status Register 0 0144h Timer RD Interrupt Enable Register 0 0145h Timer RD PWM Mode Output Level Control Register 0 0146h Timer RD Counter 0 0147h 0148h Timer RD General Register A0 0149h 014Ah Timer RD General Register B0 014Bh 014Ch Timer RD General Register C0 014Dh 014Eh Timer RD General Register D0 014Fh 0150h Timer RD Control Register 1 0151h Timer RD I/O Control Register A1 0152h Timer RD I/O Control Register C1 0153h Timer RD Status Register 1 0154h Timer RD Interrupt Enable Register 1 0155h Timer RD PWM Mode Output Level Control Register 1 0156h Timer RD Counter 1 0157h 0158h Timer RD General Register A1 0159h 015Ah Timer RD General Register B1 015Bh 015Ch Timer RD General Register C1 015Dh 015Eh Timer RD General Register D1 015Fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 32 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 4. Special Function Registers (SFRs) R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 4.7 SFR Information (7) (1) Symbol TRASR TRBRCSR TRCPSR0 TRCPSR1 TRDPSR0 TRDPSR1 TIMSR U0SR U2SR0 U2SR1 SSUIICSR INTSR PINSR After reset 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Address Register 0180h Timer RA Pin Select Register 0181h Timer RB/RC Pin Select Register 0182h Timer RC Pin Select Register 0 0183h Timer RC Pin Select Register 1 0184h Timer RD Pin Select Register 0 0185h Timer RD Pin Select Register 1 0186h Timer Pin Select Register 0187h 0188h UART0 Pin Select Register 0189h 018Ah UART2 Pin Select Register 0 018Bh UART2 Pin Select Register 1 018Ch SSU Pin Select Register 018Dh 018Eh INT Interrupt Input Pin Select Register 018Fh I/O Function Pin Select Register 0190h 0191h 0192h 0193h SS Bit Counter Register 0194h SS Transmit Data Register 0195h 0196h SS Receive Data Register 0197h 0198h SS Control Register H 0199h SS Control Register L 019Ah SS Mode Register 019Bh SS Enable Register 019Ch SS Status Register 019Dh SS Mode Register 2 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h Flash Memory Status Register 01B3h 01B4h Flash Memory Control Register 0 01B5h Flash Memory Control Register 1 01B6h Flash Memory Control Register 2 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. SSBR SSTDR SSRDR SSCRH SSCRL SSMR SSER SSSR SSMR2 11111000b FFh FFh FFh FFh 00h 01111101b 00010000b 00h 00h 00h FST FMR0 FMR1 FMR2 10000X00b 00h 00h 00h REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 33 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 4. Special Function Registers (SFRs) R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 4.8 SFR Information (8) (1) Symbol RMAD0 After reset XXh XXh 0000XXXXb 00h XXh XXh 0000XXXXb 00h Address Register 01C0h Address Match Interrupt Register 0 01C1h 01C2h 01C3h Address Match Interrupt Enable Register 0 01C4h Address Match Interrupt Register 1 01C5h 01C6h 01C7h Address Match Interrupt Enable Register 1 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh 01E0h Pull-Up Control Register 0 01E1h Pull-Up Control Register 1 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh 01F0h 01F1h 01F2h 01F3h 01F4h 01F5h Input Threshold Control Register 0 01F6h Input Threshold Control Register 1 01F7h 01F8h 01F9h 01FAh External Input Enable Register 0 01FBh External Input Enable Register 1 01FCh INT Input Filter Select Register 0 01FDh INT Input Filter Select Register 1 01FEh Key Input Enable Register 0 01FFh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. AIER0 RMAD1 AIER1 PUR0 PUR1 00h 00h VLT0 VLT1 00h 00h INTEN INTEN1 INTF INTF1 KIEN 00h 00h 00h 00h 00h REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 34 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 4. Special Function Registers (SFRs) R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 4.9 SFR Information (9) (1) Symbol XXh XXh XXh XXh XXh After reset Address Register 2C00h DTC Transfer Vector Area 2C01h DTC Transfer Vector Area 2C02h DTC Transfer Vector Area 2C03h DTC Transfer Vector Area 2C04h DTC Transfer Vector Area 2C05h 2C06h 2C07h 2C08h DTC Transfer Vector Area 2C09h DTC Transfer Vector Area 2C0Ah DTC Transfer Vector Area : DTC Transfer Vector Area : DTC Transfer Vector Area 2C3Ah 2C3Bh 2C3Ch 2C3Dh 2C3Eh 2C3Fh 2C40h DTC Control Data 0 2C41h 2C42h 2C43h 2C44h 2C45h 2C46h 2C47h 2C48h DTC Control Data 1 2C49h 2C4Ah 2C4Bh 2C4Ch 2C4Dh 2C4Eh 2C4Fh 2C50h DTC Control Data 2 2C51h 2C52h 2C53h 2C54h 2C55h 2C56h 2C57h 2C58h DTC Control Data 3 2C59h 2C5Ah 2C5Bh 2C5Ch 2C5Dh 2C5Eh 2C5Fh 2C60h DTC Control Data 4 2C61h 2C62h 2C63h 2C64h 2C65h 2C66h 2C67h 2C68h DTC Control Data 5 2C69h 2C6Ah 2C6Bh 2C6Ch 2C6Dh 2C6Eh 2C6Fh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. XXh XXh XXh XXh XXh DTCD0 DTCD1 DTCD2 DTCD3 DTCD4 DTCD5 XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 35 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 4. Special Function Registers (SFRs) R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 4.10 SFR Information (10) (1) Symbol DTCD6 After reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Address Register 2C70h DTC Control Data 6 2C71h 2C72h 2C73h 2C74h 2C75h 2C76h 2C77h 2C78h DTC Control Data 7 2C79h 2C7Ah 2C7Bh 2C7Ch 2C7Dh 2C7Eh 2C7Fh 2C80h DTC Control Data 8 2C81h 2C82h 2C83h 2C84h 2C85h 2C86h 2C87h 2C88h DTC Control Data 9 2C89h 2C8Ah 2C8Bh 2C8Ch 2C8Dh 2C8Eh 2C8Fh 2C90h DTC Control Data 10 2C91h 2C92h 2C93h 2C94h 2C95h 2C96h 2C97h 2C98h DTC Control Data 11 2C99h 2C9Ah 2C9Bh 2C9Ch 2C9Dh 2C9Eh 2C9Fh 2CA0h DTC Control Data 12 2CA1h 2CA2h 2CA3h 2CA4h 2CA5h 2CA6h 2CA7h 2CA8h DTC Control Data 13 2CA9h 2CAAh 2CABh 2CACh 2CADh 2CAEh 2CAFh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. DTCD7 DTCD8 DTCD9 DTCD10 DTCD11 DTCD12 DTCD13 REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 36 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 4. Special Function Registers (SFRs) R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 4.11 SFR Information (11) (1) Symbol DTCD14 After reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Address Register 2CB0h DTC Control Data 14 2CB1h 2CB2h 2CB3h 2CB4h 2CB5h 2CB6h 2CB7h 2CB8h DTC Control Data 15 2CB9h 2CBAh 2CBBh 2CBCh 2CBDh 2CBEh 2CBFh 2CC0h DTC Control Data 16 2CC1h 2CC2h 2CC3h 2CC4h 2CC5h 2CC6h 2CC7h 2CC8h DTC Control Data 17 2CC9h 2CCAh 2CCBh 2CCCh 2CCDh 2CCEh 2CCFh 2CD0h DTC Control Data 18 2CD1h 2CD2h 2CD3h 2CD4h 2CD5h 2CD6h 2CD7h 2CD8h DTC Control Data 19 2CD9h 2CDAh 2CDBh 2CDCh 2CDDh 2CDEh 2CDFh 2CE0h DTC Control Data 20 2CE1h 2CE2h 2CE3h 2CE4h 2CE5h 2CE6h 2CE7h 2CE8h DTC Control Data 21 2CE9h 2CEAh 2CEBh 2CECh 2CEDh 2CEEh 2CEFh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. DTCD15 DTCD16 DTCD17 DTCD18 DTCD19 DTCD20 DTCD21 REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 37 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 4. Special Function Registers (SFRs) R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 4.12 SFR Information (12) (1) Symbol DTCD22 After reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Address Register 2CF0h DTC Control Data 22 2CF1h 2CF2h 2CF3h 2CF4h 2CF5h 2CF6h 2CF7h 2CF8h DTC Control Data 23 2CF9h 2CFAh 2CFBh 2CFCh 2CFDh 2CFEh 2CFFh 2D00h 2D01h : 2E00h CAN0 Mailbox 0 : Message ID 2E01h 2E02h 2E03h 2E04h 2E05h CAN0 Mailbox 0 : Data length 2E06h CAN0 Mailbox 0 : Data field 2E07h 2E08h 2E09h 2E0Ah 2E0Bh 2E0Ch 2E0Dh 2E0Eh CAN0 Mailbox 0 : Time stamp 2E0Fh 2E10h CAN0 Mailbox 1 : Message ID 2E11h 2E12h 2E13h 2E14h 2E15h CAN0 Mailbox 1 : Data length 2E16h CAN0 Mailbox 1 : Data field 2E17h 2E18h 2E19h 2E1Ah 2E1Bh 2E1Ch 2E1Dh 2E1Eh CAN0 Mailbox 1 : Time stamp 2E1Fh 2E20h CAN0 Mailbox 2 : Message ID 2E21h 2E22h 2E23h 2E24h 2E25h CAN0 Mailbox 2 : Data length 2E26h CAN0 Mailbox 2 : Data field 2E27h 2E28h 2E29h 2E2Ah 2E2Bh 2E2Ch 2E2Dh 2E2Eh CAN0 Mailbox 2 : Time stamp 2E2Fh X : Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. DTCD23 C0MB0 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C0MB1 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C0MB2 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 38 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 4. Special Function Registers (SFRs) R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 4.13 SFR Information (13) (1) Symbol C0MB3 After reset XXXX XXXXh Address Register 2E30h CAN0 Mailbox 3 : Message ID 2E31h 2E32h 2E33h 2E34h 2E35h CAN0 Mailbox 3 : Data length 2E36h CAN0 Mailbox 3 : Data field 2E37h 2E38h 2E39h 2E3Ah 2E3Bh 2E3Ch 2E3Dh 2E3Eh CAN0 Mailbox3 : Time stamp 2E3Fh 2E40h CAN0 Mailbox4 : Message ID 2E41h 2E42h 2E43h 2E44h 2E45h CAN0 Mailbox4 : Data length 2E46h CAN0 Mailbox4 : Data field 2E47h 2E48h 2E49h 2E4Ah 2E4Bh 2E4Ch 2E4Dh 2E4Eh CAN0 Mailbox4 : Time stamp 2E4Fh 2E50h CAN0 Mailbox5 : Message ID 2E51h 2E52h 2E53h 2E54h 2E55h CAN0 Mailbox5 : Data length 2E56h CAN0 Mailbox5 : Data field 2E57h 2E58h 2E59h 2E5Ah 2E5Bh 2E5Ch 2E5Dh 2E5Eh CAN0 Mailbox5 : Time stamp 2E5Fh 2E60h CAN0 Mailbox6 : Message ID 2E61h 2E62h 2E63h 2E64h 2E65h CAN0 Mailbox6 : Data length 2E66h CAN0 Mailbox6 : Data field 2E67h 2E68h 2E69h 2E6Ah 2E6Bh 2E6Ch 2E6Dh 2E6Eh CAN0 Mailbox6 : Time stamp 2E6Fh X : Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. XXh XXXX XXXX XXXX XXXXh XXXXh C0MB4 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C0MB5 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C0MB6 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 39 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 4. Special Function Registers (SFRs) R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 4.14 SFR Information (14) (1) Symbol C0MB7 After reset XXXX XXXXh Address Register 2E70h CAN0 Mailbox7 : Message ID 2E71h 2E72h 2E73h 2E74h 2E75h CAN0 Mailbox7 : Data length 2E76h CAN0 Mailbox7 : Data field 2E77h 2E78h 2E79h 2E7Ah 2E7Bh 2E7Ch 2E7Dh 2E7Eh CAN0 Mailbox7 : Time stamp 2E7Fh 2E80h CAN0 Mailbox8 : Message ID 2E81h 2E82h 2E83h 2E84h 2E85h CAN0 Mailbox8 : Data length 2E86h CAN0 Mailbox8 : Data field 2E87h 2E88h 2E89h 2E8Ah 2E8Bh 2E8Ch 2E8Dh 2E8Eh CAN0 Mailbox8 : Time stamp 2E8Fh 2E90h CAN0 Mailbox9 : Message ID 2E91h 2E92h 2E93h 2E94h 2E95h CAN0 Mailbox9 : Data length 2E96h CAN0 Mailbox9 : Data field 2E97h 2E98h 2E99h 2E9Ah 2E9Bh 2E9Ch 2E9Dh 2E9Eh CAN0 Mailbox9 : Time stamp 2E9Fh 2EA0h CAN0 Mailbox10 : Message ID 2EA1h 2EA2h 2EA3h 2EA4h 2EA5h CAN0 Mailbox10 : Data length 2EA6h CAN0 Mailbox10 : Data field 2EA7h 2EA8h 2EA9h 2EAAh 2EABh 2EACh 2EADh 2EAEh CAN0 Mailbox10 : Time stamp 2EAFh X : Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. XXh XXXX XXXX XXXX XXXXh XXXXh C0MB8 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C0MB9 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C0MB10 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 40 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 4. Special Function Registers (SFRs) R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 4.15 SFR Information (15) (1) Symbol C0MB11 After reset XXXX XXXXh Address Register 2EB0h CAN0 Mailbox11 : Message ID 2EB1h 2EB2h 2EB3h 2EB4h 2EB5h CAN0 Mailbox11 : Data length 2EB6h CAN0 Mailbox11 : Data field 2EB7h 2EB8h 2EB9h 2EBAh 2EBBh 2EBCh 2EBDh 2EBEh CAN0 Mailbox11 : Time stamp 2EBFh 2EC0h CAN0 Mailbox12 : Message ID 2EC1h 2EC2h 2EC3h 2EC4h 2EC5h CAN0 Mailbox12 : Data length 2EC6h CAN0 Mailbox12 : Data field 2EC7h 2EC8h 2EC9h 2ECAh 2ECBh 2ECCh 2ECDh 2ECEh CAN0 Mailbox12 : Time stamp 2ECFh 2ED0h CAN0 Mailbox13 : Message ID 2ED1h 2ED2h 2ED3h 2ED4h 2ED5h CAN0 Mailbox13 : Data length 2ED6h CAN0 Mailbox13 : Data field 2ED7h 2ED8h 2ED9h 2EDAh 2EDBh 2EDCh 2EDDh 2EDEh CAN0 Mailbox13 : Time stamp 2EDFh 2EE0h CAN0 Mailbox14 : Message ID 2EE1h 2EE2h 2EE3h 2EE4h 2EE5h CAN0 Mailbox14 : Data length 2EE6h CAN0 Mailbox14 : Data field 2EE7h 2EE8h 2EE9h 2EEAh 2EEBh 2EECh 2EEDh 2EEEh CAN0 Mailbox14 : Time stamp 2EEFh X : Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. XXh XXXX XXXX XXXX XXXXh XXXXh C0MB12 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C0MB13 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C0MB14 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 41 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 4. Special Function Registers (SFRs) R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 4.16 SFR Information (16) (1) Symbol C0MB15 After reset XXXX XXXXh Address Register 2EF0h CAN0 Mailbox15 : Message ID 2EF1h 2EF2h 2EF3h 2EF4h 2EF5h CAN0 Mailbox15 : Data length 2EF6h CAN0 Mailbox15 : Data field 2EF7h 2EF8h 2EF9h 2EFAh 2EFBh 2EFCh 2EFDh 2EFEh CAN0 Mailbox15 : Time stamp 2EFFh 2F00h 2F01h 2F02h 2F03h 2F04h 2F05h 2F06h 2F07h 2F08h 2F09h 2F0Ah 2F0Bh 2F0Ch 2F0Dh 2F0Eh 2F0Fh 2F10h CAN0 Mask Register 0 2F11h 2F12h 2F13h 2F14h CAN0 Mask Register 1 2F15h 2F16h 2F17h 2F18h CAN0 Mask Register 2 2F19h 2F1Ah 2F1Bh 2F1Ch CAN0 Mask Register 3 2F1Dh 2F1Eh 2F1Fh 2F20h CAN0 FIFO Received ID Compare Register 0 2F21h 2F22h 2F23h 2F24h CAN0 FIFO Received ID Compare Register 1 2F25h 2F26h 2F27h 2F28h 2F29h 2F2Ah CAN0 Mask Invalid Register 2F2Bh 2F2Ch 2F2Dh 2F2Eh CAN0 Mailbox Interrupt Enable Register 2F2Fh 2F30h CAN0 Message Control Register 0 2F31h CAN0 Message Control Register 1 2F32h CAN0 Message Control Register 2 2F33h CAN0 Message Control Register 3 2F34h CAN0 Message Control Register 4 2F35h CAN0 Message Control Register 5 2F36h CAN0 Message Control Register 6 2F37h CAN0 Message Control Register 7 2F38h CAN0 Message Control Register 8 2F39h CAN0 Message Control Register 9 2F3Ah CAN0 Message Control Register 10 X : Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. XXh XXXX XXXX XXXX XXXXh XXXXh C0MKR0 XXXX XXXXh C0MKR1 XXXX XXXXh C0MKR2 XXXX XXXXh C0MKR3 XXXX XXXXh C0FIDCR0 XXXX XXXXh C0FIDCR1 XXXX XXXXh C0MKIVLR XXXXh C0MIER C0MCTL0 C0MCTL1 C0MCTL2 C0MCTL3 C0MCTL4 C0MCTL5 C0MCTL6 C0MCTL7 C0MCTL8 C0MCTL9 C0MCTL10 XXXXh 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 42 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 4. Special Function Registers (SFRs) R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 4.17 SFR Information (17) (1) Symbol C0MCTL11 C0MCTL12 C0MCTL13 C0MCTL14 C0MCTL15 C0CTLR C0STR C0BCR After reset 00h 00h 00h 00h 00h 0000 0101b 0000 0000b 0000 0101b 0000 0000b 00 0000h Address Register 2F3Bh CAN0 Message Control Register 11 2F3Ch CAN0 Message Control Register 12 2F3Dh CAN0 Message Control Register 13 2F3Eh CAN0 Message Control Register 14 2F3Fh CAN0 Message Control Register 15 2F40h CAN0 Control Register 2F41h 2F42h CAN0 Status Register 2F43h 2F44h CAN0 Bit Configuration Register 2F45h 2F46h 2F47h 2F48h CAN0 Receive FIFO Control Register 2F49h CAN0 Receive FIFO Pointer Control Register 2F4Ah CAN0 Transmit FIFO Control Register 2F4Bh CAN0 Transmit FIFO Pointer Control Register 2F4Ch CAN0 Error Interrupt Enable Register 2F4Dh CAN0 Error Interrupt Factor Judge Register 2F4Eh CAN0 Reception Error Count Register 2F4Fh CAN0 Transmission Error Count Register 2F50h CAN0 Error Code Store Register 2F51h CAN0 Channel Search Support Register 2F52h CAN0 Mailbox Search Status Register 2F53h CAN0 Mailbox Search Mode Register 2F54h CAN0 Time Stamp Register 2F55h 2F56h CAN0 Acceptance Filter Support Register 2F57h 2F58h CAN0 Test Control Register : 2FFFh X : Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. C0RFCR C0RFPCR C0TFCR C0TFPCR C0EIER C0EIFR C0RECR C0TECR C0ECSR C0CSSR C0MSSR C0MSMR C0TSR C0AFSR C0TCR 1000 0000b XXh 1000 0000b XXh 00h 00h 00h 00h 00h XXh 1000 0000b 00h 0000h XXXXh 00h Table 4.18 Address : FFDBh : FFDFh : FFE3h : FFEBh : FFEFh : FFF3h : FFF7h : FFFBh : FFFFh Notes: 1. ID Code Areas and Option Function Select Area Area Name Option Function Select Register 2 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Option Function Select Register OFS OFS2 Symbol After Reset (Note 1) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 1) 2. The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program. Do not write additions to the option function select area. If the block including the option function select area is erased, the option function select area is set to FFh. When blank products are shipped, the option function select area is set to FFh. It is set to the written value after written by the user. When factory-programming products are shipped, the value of the option function select area is the value programmed by the user. The ID code areas are allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program. Do not write additions to the ID code areas. If the block including the ID code areas is erased, the ID code areas are set to FFh. When blank products are shipped, the ID code areas are set to FFh. They are set to the written value after written by the user. When factory-programming products are shipped, the value of the ID code areas is the value programmed by the user. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 43 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 5. Electrical Characteristics R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group 5. Electrical Characteristics Table 5.1 Symbol VCC/AVCC Supply voltage VI IIN VO Pd Topr Tstg Notes: 1. 2. 3. 4. Input voltage (1) Input current (1) Output voltage Power dissipation Operating ambient temperature Storage temperature −40 °C ≤ Topr < 85 °C 85 °C ≤ Topr < 125 °C (2, 3, 4) Absolute Maximum Ratings Parameter Condition Rated Value −0.3 to 6.5 −0.3 to VCC + 0.3 −4 to 4 −0.3 to VCC + 0.3 300 125 −40 to 85 (J version) / −40 to 125 (K version) −65 to 150 Unit V V mA V mW mW °C °C Meet the specified range for the input voltage or the input current. Applicable ports: P0 to P2, P3_0, P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_5, P6 The total input current must be 12 mA or less. Even if no voltage is supplied to Vcc, the input current may cause the MCU to be powered on and operate. When a voltage is supplied to Vcc, the input current may cause the supply voltage to rise. Since operations in any cases other than above are not guaranteed, use the power supply circuit in the system to ensure the supply voltage for the MCU is stable within the specified range. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 44 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 5. Electrical Characteristics R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 5.2 Symbol Recommended Operating Conditions (1) Parameter Conditions Min. 2.7 − 0.8 VCC 0.5 VCC 0.55 VCC 0.65 VCC 0.7 VCC 0.85 VCC 0.85 VCC 1.2 0 0 0 0 0 0 0 0 − − − − − − − − − 32 − − − Standard Typ. − 0 − − − − − − − − − − − − − − − − − − − − − − − − − − − − − Unit Max. 5.5 V − V VCC V VCC V VCC V VCC V VCC V VCC V VCC V VCC V 0.2 VCC V 0.2 VCC V 0.2 VCC V 0.4 VCC V 0.3 VCC V 0.55 VCC V 0.45 VCC V 0.4 V −80 mA −40 mA −10 mA −5 mA 80 mA 40 mA 10 mA 5 mA 20 MHz 40 MHz 20 20 20 MHz MHz MHz VCC/AVCC Supply voltage VSS/AVSS Supply voltage Input “H” voltage Other than CMOS input VIH CMOS Input level Input level selection 4.0 V ≤ VCC ≤ 5.5 V input switching : 0.35 VCC 2.7 V ≤ VCC < 4.0 V function Input level selection 4.0 V ≤ VCC ≤ 5.5 V (I/O port) : 0.5 VCC 2.7 V ≤ VCC < 4.0 V Input level selection 4.0 V ≤ VCC ≤ 5.5 V : 0.7 VCC 2.7 V ≤ VCC < 4.0 V External clock input (XOUT) Input “L” voltage Other than CMOS input VIL CMOS Input level Input level selection 4.0 V ≤ VCC ≤ 5.5 V input switching : 0.35 VCC 2.7 V ≤ VCC < 4.0 V function Input level selection 4.0 V ≤ VCC ≤ 5.5 V (I/O port) : 0.5 VCC 2.7 V ≤ VCC < 4.0 V Input level selection 4.0 V ≤ VCC ≤ 5.5 V : 0.7 VCC 2.7 V ≤ VCC < 4.0 V External clock input (XOUT) Sum of all pins IOH(peak) IOH(sum) Peak sum output “H” Sum of all pins IOH(avg) IOH(sum) Average sum output “H” IOH(peak) Peak output “H” current Average output “H” current IOH(avg) Sum of all pins IOL(peak) IOL(sum) Peak sum output “L” Sum of all pins IOL(avg) IOL(sum) Average sum output “L” IOL(peak) Peak output “L” current Average output “L” current IOL(avg) XIN clock input oscillation frequency 2.7 V ≤ VCC ≤ 5.5 V f(XIN) fOCO40M When used as the count source for timer RC or timer RD 2.7 V ≤ VCC ≤ 5.5 V fOCO-F − f(BCLK) fOCO-F frequency System clock frequency CPU clock frequency 2.7 V ≤ VCC ≤ 5.5 V 2.7 V ≤ VCC ≤ 5.5 V 2.7 V ≤ VCC ≤ 5.5 V Notes: 1. VCC = 2.7 to 5.5 V at Topr = −40 to 85°C (J version) / −40 to 125°C (K version), unless otherwise specified. 2. The average output current indicates the average value of current measured during 100 ms. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 45 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 5. Electrical Characteristics R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 5.3 Symbol IIC(H) IIC(L) Σ|IIC| Recommended Operating Conditions (2) Parameter Conditions VI > VCC VI > VSS Min. − − − Standard Typ. Max. − 2 − − −2 8 Unit mA mA mA High input injection P0 to P2, P3_0, P3_1, P3_3 to P3_5, P3_7, current P4_3 to P4_5, P6 Low input injection current P0 to P2, P3_0, P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_5, P6 Total injection current Note: 1. VCC = 2.7 to 5.5 V at Topr = −40 to 85°C (J version) / −40 to 125°C (K version), unless otherwise specified. P0 P1 P2 P3_0, P3_1, P3_3 to P3_5, P3_7 P4_2 to P4_7 P6 30 pF Figure 5.1 Ports P0 to P2, P3_0, P3_1, P3_3 to P3_5, P3_7, P4_2 to P4_7, and P6 Timing Measurement Circuit REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 46 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 5. Electrical Characteristics R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 5.4 Symbol − − A/D Converter Characteristics Parameter Conditions Vref = AVCC 10-bit mode Vref = AVCC = 5.0 V Vref = AVCC = 3.0 V 8-bit mode Vref = AVCC = 5.0 V Vref = AVCC = 3.0 V AN0 to AN7 input, AN8 to AN11 input AN0 to AN7 input, AN8 to AN11 input AN0 to AN7 input, AN8 to AN11 input AN0 to AN7 input, AN8 to AN11 input Standard Min. − − − − − 2 2 − VCC = 5.0 V, XIN = f1 = φAD = 20 MHz 10-bit mode 8-bit mode Vref = AVCC = 5.0 V, φAD = 20 MHz Vref = AVCC = 5.0 V, φAD = 20 MHz φAD = 20 MHz − 2.2 2.2 0.75 2.7 0 2 MHz ≤ φAD ≤ 4 MHz 1.14 Typ. − − − − − − − 3 45 − − − − − 1.34 Max. 10 ±3 ±5 ±2 ±2 20 10 − − − − − AVCC Vref 1.54 Unit Bit LSB LSB LSB LSB MHz MHz kΩ µA µs µs µs V V V Resolution Absolute accuracy φAD − Ivref tCONV tSAMP Vref VIA A/D conversion clock Tolerance level impedance Vref current Conversion time Sampling time Reference voltage Analog input voltage (3) 4.0 ≤ Vref = AVCC = ≤ 5.5 (2) 2.7 ≤ Vref = AVCC = ≤ 5.5 (2) OCVREF On-chip reference voltage Notes: 1. VCC/AVCC = Vref = 2.7 to 5.5 V, VSS = 0 V at Topr = −40 to 85°C (J version) / −40 to 125°C (K version), unless otherwise specified. 2. The A/D conversion result will be undefined in wait mode, stop mode, when the flash memory stops, and in low-consumption current mode. Do not perform A/D conversion in these states or transition to these states during A/D conversion. 3. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in 8-bit mode. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 47 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 5. Electrical Characteristics R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 5.5 Symbol − − − − − − td(SR-SUS) − − td(CMDRSTREADY) − − − − Flash Memory (Program ROM) Electrical Characteristics Parameter Program/erase endurance (2) Byte program time (program/erase endurance ≤ 1,000 times) Byte program time (program/erase endurance > 1,000 times) Word program time (program/erase endurance ≤ 1,000 times) Word program time (program/erase endurance > 1,000 times) Block erase time Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Time from suspend until erase restart Time from when command is forcibly terminated until reading is enabled Program, erase voltage Read voltage Program, erase temperature Data hold time (7) Ambient temperature = 55°C (8) Conditions R8C/34X, R8C/34Z Group R8C/34W, R8C/34Y Group Standard Min. 100 (3) 1,000 (3) − − − − − − 0 − − 2.7 2.7 −40 20 Typ. − − 60 60 100 100 0.3 − − − − − − − − Max. − − 300 500 400 650 4 5+CPU clock × 3 cycles − 30+CPU clock × 1 cycle 30+CPU clock × 1 cycle 5.5 5.5 85 (J version) 125 (K version) − Unit times times µs µs µs µs s ms µs µs µs V V °C year Notes: 1. VCC = 2.7 to 5.5 V at Topr = −40 to 85°C (J version) / −40 to 125°C (K version) (under consideration), unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100, 1,000), each block can be erased n times. For example, if 1,024 1byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied. 8. This data hold time includes 3,000 hours in Ta = 125°C and 7,000 hours in Ta = 85°C. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 48 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 5. Electrical Characteristics R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 5.6 Symbol − − − − − td(SR-SUS) − − td(CMDRSTREADY) − − − − Flash Memory (Data flash Block A to Block D) Electrical Characteristics Parameter Program/erase endurance (2) Byte program time (program/erase endurance ≤ 1,000 times) Byte program time (program/erase endurance > 1,000 times) Block erase time (program/erase endurance ≤ 1,000 times) Block erase time (program/erase endurance > 1,000 times) Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Time from suspend until erase restart Time from when command is forcibly terminated until reading is enabled Program, erase voltage Read voltage Program, erase temperature Data hold time (7) Ambient temperature = 55 °C (8) Conditions Standard Min. 10,000 (3) − − − − − 0 − − 2.7 2.7 −40 20 Typ. − 160 300 0.2 0.3 − − − − − − − − Max. − 950 950 1 1 3+CPU clock × 3 cycles − 30+CPU clock × 1 cycle 30+CPU clock × 1 cycle 5.5 5.5 85 (J version) 125 (K version) − Unit times µs µs s s ms µs µs µs V V °C year Notes: 1. VCC = 2.7 to 5.5 V at Topr = −40 to 85°C (J version) / −40 to 125°C (K version), unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100, 1,000, 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A to D can further reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied. 8. This data hold time includes 3,000 hours in Ta = 125°C and 7,000 hours in Ta = 85°C. Suspend request (FMR21 bit) FST7 bit FST6 bit Fixed time Clock-dependent time Access restart td(SR-SUS) FST6, FST7: Bit in FST register FMR21: Bit in FMR2 register Figure 5.2 Time delay until Suspend REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 49 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 5. Electrical Characteristics R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 5.7 Symbol Vdet0 − − td(E-A) Voltage Detection 0 Circuit Electrical Characteristics Parameter Voltage detection level Voltage detection 0 circuit response time (3) Voltage detection circuit self power consumption Wait time until voltage detection circuit operation starts (2) Condition At the falling of VCC At the falling of Vcc from 5 V to (Vdet0 − 0.1) V VCA25 = 1, VCC = 5.0 V Standard Min. 2.70 − − − Typ. 2.85 6 1.5 − Max. 3.00 150 − 100 Unit V µs µA µs Notes: 1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = −40 to 85°C (J version) / −40 to 125°C (K version). 2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2 register to 0. 3. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0. Table 5.8 Symbol Vdet1 Voltage Detection 1 Circuit Electrical Characteristics Parameter Voltage detection level Vdet1_7 (2) Voltage detection level Vdet1_8 (2) Condition At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC Standard Min. 3.05 3.20 3.35 3.50 3.65 3.80 3.95 4.10 − Typ. 3.25 3.40 3.55 3.70 3.85 4.00 4.15 4.30 0.1 60 1.7 − Max. 3.45 3.60 3.75 3.90 4.05 4.20 4.35 4.50 − 150 − 100 Unit V V V V V V V V V µs µA µs Voltage detection level Vdet1_9 (2) Voltage detection level Vdet1_A (2) Voltage detection level Vdet1_B Voltage detection level Vdet1_C (2) (2) Voltage detection level Vdet1_D (2) Voltage detection level Vdet1_E (2) − − − td(E-A) Notes: 1. 2. 3. 4. Hysteresis width at the rising of Vcc in voltage detection 1 circuit Voltage detection 1 circuit response time (3) Voltage detection circuit self power consumption Wait time until voltage detection circuit operation starts (4) At the falling of Vcc from 5 V to (Vdet1_7 − 0.1) V VCA26 = 1, VCC = 5.0 V − − − The measurement condition is VCC = 2.7 V to 5.5 V and Topr = −40 to 85°C (J version) / −40 to 125°C (K version). Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0. Table 5.9 Symbol Vdet2 − − − td(E-A) Voltage Detection 2 Circuit Electrical Characteristics Parameter Voltage detection level Vdet2 Hysteresis width at the rising of Vcc in voltage detection 2 circuit Voltage detection 2 circuit response time (2) Voltage detection circuit self power consumption Wait time until voltage detection circuit operation starts (3) Condition At the falling of VCC Standard Min. 3.80 − Typ. 4.00 0.1 20 1.7 − Max. 4.20 − 150 − 100 Unit V V µs µA µs At the falling of Vcc from 5 V to (Vdet2 − 0.1) V VCA26 = 1, VCC = 5.0 V − − − Notes: 1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = −40 to 85°C (J version) / −40 to 125°C (K version). 2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2. 3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2 register to 0. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 50 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 5. Electrical Characteristics R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 5.10 Symbol trth Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics (2) Parameter External power VCC rise gradient (1) Condition Standard Min. 0 Typ. − Max. 50000 Unit mV/msec Notes: 1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = −40 to 85°C (J version) / −40 to 125°C (K version). 2. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0. Vdet0 (1) trth External Power VCC 0.5 V tw(por) (2) Voltage detection 0 circuit response time trth Vdet0 (1) Internal reset signal 1 × 32 fOCO-S 1 × 32 fOCO-S Notes: 1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection Circuit of User’s Manual: Hardware (REJ09B0605) for details. 2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain tw(por) for 1 ms or more. Figure 5.3 Power-on Reset Circuit Electrical Characteristics REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 51 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 5. Electrical Characteristics R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 5.11 Symbol − High-speed On-Chip Oscillator Circuit Electrical Characteristics Parameter Condition VCC = 2.7 V to 5.5 V, −40°C ≤ Topr ≤ 85°C (J version) / −40°C ≤ Topr ≤ 125°C (K version) Standard Min. − − Typ. 40 36.864 Max. − − Unit MHz MHz High-speed on-chip oscillator frequency after reset High-speed on-chip oscillator frequency when the FRA4 register correction value is written into the FRA1 register and the FRA5 register correction value into the FRA3 register (3) High-speed on-chip oscillator frequency when the FRA6 register correction value is written into the FRA1 register and the FRA7 register correction value into the FRA3 register High-speed on-chip oscillator frequency temperature • supply voltage dependence (2) − 32 − MHz −5 − VCC = 5.0 V, Topr = 25°C − − 200 400 5 − − % µs µA − − Oscillation stabilization time Self power consumption at oscillation Notes: 1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = −40 to 85°C (J version) / −40 to 125°C (K version). 2. This indicates the precision error for the oscillation frequency of the high-speed on-chip oscillator. 3. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in UART mode. Table 5.12 Symbol fOCO-S fOCO-WDT − − Low-speed On-Chip Oscillator Circuit Electrical Characteristics Parameter Low-speed on-chip oscillator frequency Low-speed on-chip oscillator frequency for watchdog timer Oscillation stabilization time Self power consumption at oscillation VCC = 5.0 V, Topr = 25°C VCC = 5.0 V, Topr = 25°C Condition Standard Min. 112.5 112.5 − − Typ. 125 125 30 3 Max. 137.5 137.5 100 − Unit kHz kHz µs µA Note: 1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = −40 to 85°C (J version) / −40 to 125°C (K version). Table 5.13 Symbol td(P-R) Power Supply Circuit Timing Characteristics Parameter Time for internal power supply stabilization during power-on (2) Condition Standard Min. − Typ. − Max. 2000 Unit µs Notes: 1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = −40 to 85°C (J version) / −40 to 125°C (K version). 2. Wait time until the internal power supply generation circuit stabilizes during power-on. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 52 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 5. Electrical Characteristics R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 5.14 Symbol tSUCYC tHI tLO tRISE tFALL tSU tH tLEAD tLAG tOD tSA tOR Timing Requirements of SSU (1) Parameter SSCK clock cycle time SSCK clock “H” width SSCK clock “L” width SSCK clock rising time SSCK clock falling time Master Slave Master Slave Conditions Standard Min. 4 0.4 0.4 − − − − 100 1 1tCYC + 50 1tCYC + 50 − 2.7 V ≤ VCC ≤ 5.5 V 2.7 V ≤ VCC ≤ 5.5 V − − Typ. − − − − − − − − − − − − − − Max. − 0.6 0.6 1 1 1 1 − − − − 1 1.5tCYC + 100 1.5tCYC + 100 Unit tCYC (2) tSUCYC tSUCYC tCYC (2) µs tCYC (2) µs ns tCYC (2) ns ns tCYC (2) ns ns SSO, SSI data input setup time SSO, SSI data input hold time SCS setup time SCS hold time SSI slave access time SSI slave out open time Slave Slave SSO, SSI data output delay time Notes: 1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = −40 to 85°C (J version) / −40 to 125°C (K version). 2. 1tCYC = 1/f1(s) REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 53 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 5. Electrical Characteristics R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group 4-Wire Bus Communication Mode, Master, CPHS = 1 VIH or VOH SCS (output) VIL or VOL tHI tFALL tRISE SSCK (output) (CPOS = 1) tLO tHI SSCK (output) (CPOS = 0) tLO tSUCYC SSO (output) tOD SSI (input) tSU tH 4-Wire Bus Communication Mode, Master, CPHS = 0 VIH or VOH SCS (output) VIL or VOL tHI tFALL tRISE SSCK (output) (CPOS = 1) tLO tHI SSCK (output) (CPOS = 0) tLO tSUCYC SSO (output) tOD SSI (input) tSU tH CPHS, CPOS: Bits in SSMR register Figure 5.4 I/O Timing of SSU (Master) REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 54 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 5. Electrical Characteristics R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group 4-Wire Bus Communication Mode, Slave, CPHS = 1 VIH or VOH SCS (input) VIL or VOL tLEAD tHI tFALL tRISE tLAG SSCK (input) (CPOS = 1) tLO tHI SSCK (input) (CPOS = 0) tLO tSUCYC SSO (input) tSU tH SSI (output) tSA tOD tOR 4-Wire Bus Communication Mode, Slave, CPHS = 0 SCS (input) VIH or VOH VIL or VOL tLEAD tHI tFALL tRISE tLAG SSCK (input) (CPOS = 1) tLO tHI SSCK (input) (CPOS = 0) tLO tSUCYC SSO (input) tSU tH SSI (output) tSA tOD tOR CPHS, CPOS: Bits in SSMR register Figure 5.5 I/O Timing of SSU (Slave) REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 55 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 5. Electrical Characteristics R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group tHI VIH or VOH SSCK VIL or VOL tLO tSUCYC SSO (output) tOD SSI (input) tSU tH Figure 5.6 I/O Timing of SSU (Clock Synchronous Communication Mode) REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 56 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 5. Electrical Characteristics R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 5.15 Symbol VOH Electrical Characteristics (1) [4.2 V ≤ VCC ≤ 5.5 V] Parameter Condition IOH = −5 mA IOH = −200 µA XOUT IOH = −200 µA IOL = 5 mA IOL = 200 µA XOUT IOH = −200 µA Standard Min. VCC − 2.0 VCC − 0.3 1.0 − − − Typ. − − − − − − Max. VCC VCC VCC 2.0 0.45 0.5 − Unit V V V V V V V Output “H” voltage Other than XOUT VOL Output “L” voltage Other than XOUT VT+-VT- Hysteresis INT0 to INT4, KI0 to KI3, TRAIO, TRBO, TRCIOA to TRCIOD, TRDIOA0 to TRDIOD0, TRDIOA1 to TRDIOD1, TRCCLK, TRDCLK, TRCTRG, ADTRG, RXD0, RXD2, CLK0, CLK2, SSI, SCL2, SDA2, SSO RESET VI = 5 V VI = 0 V VI = 0 V XIN During stop mode 0.1 1.2 0.1 − − 1.2 − − − V µA µA IIH IIL RfXIN VRAM Input “H” current Input “L” current Feedback resistance RAM hold voltage 1.0 −1.0 RPULLUP Pull-up resistance 25 − 50 0.3 − 100 − − kΩ MΩ V 2.0 Note: 1. 4.2 V ≤ VCC ≤ 5.5 V at Topr = −40 to 85°C (J version) / −40 to 125°C (K version), f(XIN) = 20 MHz, unless otherwise specified. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 57 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 5. Electrical Characteristics R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 5.16 Symbol ICC Electrical Characteristics (2) [3.3 V ≤ VCC ≤ 5.5 V] (Topr = −40 to 85°C (J version), unless otherwise specified.) Parameter Condition XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO-F = 20 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO-F = 20 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR27 = 1, VCA20 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off, Topr = 25°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Power supply High-speed current clock mode (1) (VCC = 3.3 to 5.5 V) Single-chip mode, output pins are open, other pins are VSS Min. − − − − − − − − − Standard Typ. Max. 7.0 15 Unit mA 5.6 12.5 − − − − mA 3.6 mA 3.0 mA 2.2 mA 1.5 mA High-speed on-chip oscillator mode (1) 7.0 15 − mA 3.0 mA µA Low-speed on-chip oscillator mode Wait mode 90 180 − 15 110 µA − 5 100 µA Stop mode − 2.0 5.0 µA − 15.0 − µA Note: 1. The typical value (Typ.) indicates the current value when the CPU and the memory operate. The maximum value (Max.) indicates the current when the CPU, the memory, and the peripheral functions operate and the flash memory is programmed/erased. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 58 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 5. Electrical Characteristics R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 5.17 Symbol ICC Electrical Characteristics (3) [3.3 V ≤ VCC ≤ 5.5 V] (Topr = −40 to 125°C (K version), unless otherwise specified.) Parameter Condition XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO-F = 20 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO-F = 20 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR27 = 1, VCA20 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off, Topr = 25°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 125°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Power supply High-speed current clock mode (1) (VCC = 3.3 to 5.5 V) Single-chip mode, output pins are open, other pins are VSS Min. − − − − − − − − − Standard Typ. Max. 7.0 15 Unit mA 5.6 12.5 − − − − mA 3.6 mA 3.0 mA 2.2 mA 1.5 mA High-speed on-chip oscillator mode (1) 7.0 15 − mA 3.0 mA µA Low-speed on-chip oscillator mode Wait mode 90 400 − 15 330 µA − 5 320 µA Stop mode − 2.0 5.0 µA − 60.0 − µA Note: 1. The typical value (Typ.) indicates the current value when the CPU and the memory operate. The maximum value (Max.) indicates the current when the CPU, the memory, and the peripheral functions operate and the flash memory is programmed/erased. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 59 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 5. Electrical Characteristics R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Timing Requirements (Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = −40°C to 85°C (J ver)/−40°C to 125°C (K ver)) Table 5.18 Symbol tc(XOUT) tWH(XOUT) tWL(XOUT) XOUT input cycle time XOUT input “H” width XOUT input “L” width External clock input (XOUT) Parameter Standard Min. 50 24 24 Max. − − − Unit ns ns ns tC(XOUT) tWH(XOUT) VCC = 5 V External Clock Input tWL(XOUT) Figure 5.7 Table 5.19 Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO) External Clock Input Timing Diagram when VCC = 5 V TRAIO Input Parameter TRAIO input cycle time TRAIO input “H” width TRAIO input “L” width Standard Min. 100 40 40 Max. − − − Unit ns ns ns tC(TRAIO) tWH(TRAIO) VCC = 5 V TRAIO input tWL(TRAIO) Figure 5.8 TRAIO Input Timing Diagram when VCC = 5 V REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 60 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 5. Electrical Characteristics R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 5.20 Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0, 2 Serial Interface Parameter CLKi input cycle time CLKi input “H” width CLKi input “L” width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. 200 100 100 − Max. − − − Unit ns ns ns ns ns ns ns 90 − − − 0 50 90 tC(CK) tW(CKH) VCC = 5 V CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0, 2 Figure 5.9 Serial Interface Timing Diagram when VCC = 5 V Table 5.21 Symbol tW(INH) tW(INL) External Interrupt INTi (i = 0 to 4) Input, Key Input Interrupt KIi (i = 0 to 3) Parameter INTi input “H” width, KIi input “H” width INTi input “L” width, KIi input “L” width Standard Min. 250 (1) 250 (2) Max. − − Unit ns ns Notes: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. VCC = 5 V INTi input (i = 0 to 4) KIi input (i = 0 to 3) tW(INL) tW(INH) Figure 5.10 Input Timing for External Interrupt INTi and Key Input Interrupt KIi when Vcc = 5 V REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 61 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 5. Electrical Characteristics R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 5.22 Symbol VOH VOL VT+-VT- Electrical Characteristics (3) [2.7 V ≤ VCC ≤ 4.2 V] Parameter Condition IOH = −1 mA IOH = −200 µA IOL = 1 mA IOL = 200 µA Standard Min. Typ. VCC − 0.5 − 1.0 − − − − − 0.1 0.4 Max. VCC VCC 0.5 0.5 − Unit V V V V V Output “H” voltage Output “L” voltage Hysteresis Other than XOUT XOUT Other than XOUT XOUT INT0 to INT4, KI0 to KI3, TRAIO, TRBO, TRCIOA to TRCIOD, TRDIOA0 to TRDIOD0, TRDIOA1 to TRDIOD1, TRCCLK, TRDCLK, TRCTRG, ADTRG, RXD0, RXD2, CLK0, CLK2, SSI, SCL2, SDA2, SSO IIH IIL RPULLUP RfXIN VRAM RESET Input “H” current Input “L” current Pull-up resistance Feedback resistance XIN RAM hold voltage 0.1 VI = 3 V VI = 0 V VI = 0 V During stop mode − − 42 − 2.0 0.5 − − 84 0.3 − − V µA µA kΩ MΩ V 1.0 −1.0 168 − − Note: 1. 2.7 V ≤ VCC ≤ 4.2 V at Topr = −40 to 85°C (J version) / −40 to 125°C (K version), f(XIN) = 20 MHz, unless otherwise specified. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 62 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 5. Electrical Characteristics R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 5.23 Electrical Characteristics (4) [2.7 V ≤ VCC ≤ 3.3 V] (Topr = −40 to 85°C (J version), unless otherwise specified.) Parameter Condition XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO-F = 20 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO-F = 20 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR27 = 1, VCA20 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off, Topr = 25°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Min. − Standard Typ. Max. 7.0 14.5 Unit mA Symbol ICC Power supply current High-speed (VCC = 2.7 to 3.3 V) clock mode (1) Single-chip mode, output pins are open, other pins are VSS − 5.6 12.0 mA − 3.6 − mA − 3.0 − mA − 2.2 − mA − 1.5 − mA High-speed on-chip oscillator mode (1) − 7.0 14.5 mA − 3.0 − mA Low-speed on-chip oscillator mode Wait mode − 85 180 µA − 15 110 µA − 5 100 µA Stop mode − 2.0 5.0 µA − 13.0 − µA Note: 1. The typical value (Typ.) indicates the current value when the CPU and the memory operate. The maximum value (Max.) indicates the current when the CPU, the memory, and the peripheral functions operate and the flash memory is programmed/erased. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 63 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 5. Electrical Characteristics R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Table 5.24 Electrical Characteristics (4) [2.7 V ≤ VCC ≤ 3.3 V] (Topr = −40 to 125°C (K version), unless otherwise specified.) Parameter Condition XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO-F = 20 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO-F = 20 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR27 = 1, VCA20 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off, Topr = 25°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 125°C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Min. − Standard Typ. Max. 7.0 14.5 Unit mA Symbol ICC Power supply current High-speed (VCC = 2.7 to 3.3 V) clock mode (1) Single-chip mode, output pins are open, other pins are VSS − 5.6 12.0 mA − 3.6 − mA − 3.0 − mA − 2.2 − mA − 1.5 − mA High-speed on-chip oscillator mode (1) − 7.0 14.5 mA − 3.0 − mA Low-speed on-chip oscillator mode Wait mode − 85 390 µA − 15 320 µA − 5 310 µA Stop mode − 2.0 5.0 µA − 55.0 − µA Note: 1. The typical value (Typ.) indicates the current value when the CPU and the memory operate. The maximum value (Max.) indicates the current when the CPU, the memory, and the peripheral functions operate and the flash memory is programmed/erased. REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 64 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 5. Electrical Characteristics R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Timing requirements (Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = −40°C to 85°C (J ver)/−40°C to 125°C (K ver)) Table 5.25 Symbol tc(XOUT) tWH(XOUT) tWL(XOUT) XOUT input cycle time XOUT input “H” width XOUT input “L” width External clock input (XOUT) Parameter Standard Min. Max. 50 − 24 − 24 − Unit ns ns ns tC(XOUT) tWH(XOUT) VCC = 3 V External Clock Input tWL(XOUT) Figure 5.11 Table 5.26 Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO) External Clock Input Timing Diagram when VCC = 3 V TRAIO Input Parameter TRAIO input cycle time TRAIO input “H” width TRAIO input “L” width Standard Min. Max. 300 − 120 − 120 − Unit ns ns ns tC(TRAIO) tWH(TRAIO) VCC = 3 V TRAIO input tWL(TRAIO) Figure 5.12 Table 5.27 Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0, 2 TRAIO Input Timing Diagram when VCC = 3 V Serial Interface Parameter CLKi input cycle time CLKi input “H” width CLKi Input “L” width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. Max. 300 − 150 − 150 − − 140 0 − 70 − 90 − Unit ns ns ns ns ns ns ns REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 65 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. 5. Electrical Characteristics R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group tC(CK) tW(CKH) VCC = 3 V CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0, 2 Figure 5.13 Serial Interface Timing Diagram when VCC = 3 V Table 5.28 Symbol tW(INH) tW(INL) External Interrupt INTi (i = 0 to 4) Input, Key Input Interrupt KIi (i = 0 to 3) Parameter INTi input “H” width, KIi input “H” width INTi input “L” width, KIi input “L” width Standard Min. Max. − 380 (1) 380 (2) − Unit ns ns Notes: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. INTi input (i = 0 to 4) KIi input (i = 0 to 3) VCC = 3 V tW(INL) tW(INH) Figure 5.14 Input Timing for External Interrupt INTi and Key Input Interrupt KIi when Vcc = 3 V REJ03B0312-0010 Rev.0.10 Apr 09, 2010 Page 66 of 67 Under development Preliminary document Specifications in this document are tentative and subject to change. Package Dimensions R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Package Dimensions Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas Electronics website. JEITA Package Code P-LQFP48-7x7-0.50 RENESAS Code PLQP0048KB-A Previous Code 48P6Q-A MASS[Typ.] 0.2g HD *1 D 36 25 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1 37 24 E HE c1 *2 c Reference Symbol Dimension in Millimeters Terminal cross section 48 ZE 13 1 ZD Index mark 12 A2 F S A1 L1 yS e *3 L D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Min 6.9 6.9 8.8 8.8 0 0.17 0.09 0° bp Detail F x 0.35 Nom Max 7.0 7.1 7.0 7.1 1.4 9.0 9.2 9.0 9.2 1.7 0.1 0.2 0.22 0.27 0.20 0.145 0.20 0.125 8° 0.5 0.08 0.10 0.75 0.75 0.5 0.65 1.0 A REJ03B0312-0010 Rev.0.10 Apr 09, 2010 c Page 67 of 67 REVISION REVISION HISTORY R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group Datasheet Rev. 0.10 Date Apr 09, 2010 Page — Description Summary First Edition issued All trademarks and registered trademarks are the property of their respective owners. C-1 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.  The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.  The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.  The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.  When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems.  The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products. Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. 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