To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1.
2.
3.
4.
5.
6.
7.
All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights
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You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
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When exporting the products or technology described in this document, you should comply with the applicable export control
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“Standard”:
8.
9.
10.
11.
12.
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support.
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PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
REJ03B0246-0010
Rev.0.10
Apr 17, 2008
RENESAS MCU
1.
Overview
1.1
Features
The R8C/34E Group, R8C/34F Group, R8C/34G Group, and R8C/34H Group of single-chip MCUs incorporate the
R8C/Tiny Series CPU core, employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of
address space, and it is capable of executing instructions at high speed. In addition, the CPU core boasts a
multiplier for high-speed operation processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs are
designed to maximize EMI/EMS performance.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
The R8C/34E Group and R8C/34F Group have a single channel CAN module and are suitable for LAN systems in
vehicles and for FA.
The R8C/34G Group and the R8C/34H Group do not have CAN modules.
The R8C/34E Group and the R8C/34G Group have data flash (1 KB × 4 blocks) with the background operation
(BGO) function.
1.1.1
Applications
Automobiles and others
REJ03B0246-0010 Rev.0.10
Page 1 of 44
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
1.1.2
1. Overview
Specifications
Tables 1.1 and 1.2 outline the Specifications for R8C/34E Group, tables 1.3 and 1.4 outline the Specifications
for R8C/34F Group, tables 1.5 and 1.6 outline the Specifications for R8C/34G Group, tables 1.7 and 1.8 outline
the Specifications for R8C/34H Group.
Table 1.1
Item
CPU
Specifications for R8C/34E Group (1)
Function
Central processing
unit
Memory
ROM, RAM, Data
flash
Power Supply Voltage detection
Voltage
circuit
Detection
I/O Ports
Programmable I/O
ports
Clock
Clock generation
circuits
Interrupts
Watchdog Timer
DTC (Data Transfer Controller)
Timer
Timer RA
Timer RB
Timer RC
Timer RD
Timer RE
REJ03B0246-0010 Rev.0.10
Page 2 of 44
Specification
R8C/Tiny series core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Refer to Table 1.9 Product List for R8C/34E Group.
• Power-on reset
• Voltage detection 3 (detection level of voltage detection 1 selectable)
• Input-only: 1 pin
• CMOS I/O ports: 43, selectable pull-up resistor
3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),
High-speed on-chip oscillator (with frequency adjustment function),
Low-speed on-chip oscillator
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, high-speed on-chip oscillator,
low-speed on-chip oscillator), wait mode, stop mode
• Interrupt Vectors: 69
• External: 9 sources (INT × 5 , key input × 4)
• Priority levels: 7 levels
• 15 bits × 1 (with prescaler)
• Reset start selectable
• Low-speed on-chip oscillator for watchdog timer selectable
• 1 channel
• Activation sources: 31
• Transfer modes: 2 (normal mode, repeat mode)
8 bits (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait oneshot generation mode
16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
16 bits × 2 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 6 pins), reset synchronous PWM mode (output three-phase
waveforms (6 pins), sawtooth wave modulation), complementary PWM mode
(output three-phase waveforms (6 pins), triangular wave modulation), PWM3
mode (PWM output 2 pins with fixed period)
8 bits × 1
Output compare mode
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 1.2
Item
Serial
Interface
1. Overview
Specifications for R8C/34E Group (2)
Function
UART0, 1
UART2
Specification
Clock synchronous serial I/O/UART × 2 channel
Clock synchronous serial I/O, UART, I2C mode (I2C-bus), IE mode (IE BUS (1)),
multiprocessor communication function
1
Synchronous Serial
Communication Unit (SSU)
LIN Module
CAN module
A/D Converter
Hardware LIN: 1 (timer RA, UART0)
One channel, 16 Mailboxes (conforms to the ISO 11898-1)
10-bit resolution × 12 channels, includes sample and hold function, with sweep
mode
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 10,000 times (data flash)
1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
• Background operation (BGO) function (data flash)
f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)
Flash Memory
Operating Frequency/Supply
Voltage
Current consumption
Operating Ambient Temperature
Package
TBD (VCC = 5.0 V, f(XIN) = 20 MHz)
TBD (VCC = 3.0 V, f(XIN) = 20 MHz)
-40 to 85°C (J version)
-40 to 125°C (K version) (2)
48-pin LQFP
Package code: PLQP0048KB-A (previous code: 48P6Q-A)
Notes:
1. IE BUS is a trademark of NEC Electronics Corporation.
2. Specify the K version if K version functions are to be used.
REJ03B0246-0010 Rev.0.10
Page 3 of 44
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 1.3
Item
CPU
Specifications for R8C/34F Group (1)
Function
Central processing
unit
Memory
ROM, RAM, Data
flash
Power Supply Voltage detection
Voltage
circuit
Detection
I/O Ports
Programmable I/O
ports
Clock
Clock generation
circuits
Interrupts
Watchdog Timer
DTC (Data Transfer Controller)
Timer
1. Overview
Timer RA
Timer RB
Timer RC
Timer RD
Timer RE
REJ03B0246-0010 Rev.0.10
Page 4 of 44
Specification
R8C/Tiny series core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Refer to Table 1.10 Product List for R8C/34F Group.
• Power-on reset
• Voltage detection 3 (detection level of voltage detection 1 selectable)
• Input-only: 1 pin
• CMOS I/O ports: 43, selectable pull-up resistor
3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),
High-speed on-chip oscillator (with frequency adjustment function),
Low-speed on-chip oscillator
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, high-speed on-chip oscillator,
low-speed on-chip oscillator), wait mode, stop mode
• Interrupt Vectors: 69
• External: 9 sources (INT × 5 , key input × 4)
• Priority levels: 7 levels
• 15 bits × 1 (with prescaler)
• Reset start selectable
• Low-speed on-chip oscillator for watchdog timer selectable
• 1 channel
• Activation sources: 31
• Transfer modes: 2 (normal mode, repeat mode)
8 bits (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait oneshot generation mode
16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
16 bits × 2 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 6 pins), reset synchronous PWM mode (output three-phase
waveforms (6 pins), sawtooth wave modulation), complementary PWM mode
(output three-phase waveforms (6 pins), triangular wave modulation), PWM3
mode (PWM output 2 pins with fixed period)
8 bits × 1
Output compare mode
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 1.4
Item
Serial
Interface
1. Overview
Specifications for R8C/34F Group (2)
Function
UART0, 1
UART2
Specification
Clock synchronous serial I/O/UART × 2 channel
Clock synchronous serial I/O, UART, I2C mode (I2C-bus), IE mode (IE BUS (1)),
multiprocessor communication function
1
Synchronous Serial
Communication Unit (SSU)
LIN Module
CAN module
A/D Converter
Hardware LIN: 1 (timer RA, UART0)
One channel, 16 Mailboxes (conforms to the ISO 11898-1)
10-bit resolution × 12 channels, includes sample and hold function, with sweep
mode
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 100 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)
Flash Memory
Operating Frequency/Supply
Voltage
Current consumption
Operating Ambient Temperature
Package
TBD (VCC = 5.0 V, f(XIN) = 20 MHz)
TBD (VCC = 3.0 V, f(XIN) = 20 MHz)
-40 to 85°C (J version)
-40 to 125°C (K version) (2)
48-pin LQFP
Package code: PLQP0048KB-A (previous code: 48P6Q-A)
Notes:
1. IE BUS is a trademark of NEC Electronics Corporation.
2. Specify the K version if K version functions are to be used.
REJ03B0246-0010 Rev.0.10
Page 5 of 44
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 1.5
Item
CPU
Specifications for R8C/34G Group (1)
Function
Central processing
unit
Memory
ROM, RAM, Data
flash
Power Supply Voltage detection
Voltage
circuit
Detection
I/O Ports
Programmable I/O
ports
Clock
Clock generation
circuits
Interrupts
Watchdog Timer
DTC (Data Transfer Controller)
Timer
1. Overview
Timer RA
Timer RB
Timer RC
Timer RD
Timer RE
REJ03B0246-0010 Rev.0.10
Page 6 of 44
Specification
R8C/Tiny series core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Refer to Table 1.11 Product List for R8C/34G Group.
• Power-on reset
• Voltage detection 3 (detection level of voltage detection 1 selectable)
• Input-only: 1 pin
• CMOS I/O ports: 43, selectable pull-up resistor
3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),
High-speed on-chip oscillator (with frequency adjustment function),
Low-speed on-chip oscillator
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, high-speed on-chip oscillator,
low-speed on-chip oscillator), wait mode, stop mode
• Interrupt Vectors: 69
• External: 9 sources (INT × 5 , key input × 4)
• Priority levels: 7 levels
• 15 bits × 1 (with prescaler)
• Reset start selectable
• Low-speed on-chip oscillator for watchdog timer selectable
• 1 channel
• Activation sources: 31
• Transfer modes: 2 (normal mode, repeat mode)
8 bits (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait oneshot generation mode
16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
16 bits × 2 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 6 pins), reset synchronous PWM mode (output three-phase
waveforms (6 pins), sawtooth wave modulation), complementary PWM mode
(output three-phase waveforms (6 pins), triangular wave modulation), PWM3
mode (PWM output 2 pins with fixed period)
8 bits × 1
Output compare mode
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 1.6
Item
Serial
Interface
1. Overview
Specifications for R8C/34G Group (2)
Function
UART0, 1
UART2
Specification
Clock synchronous serial I/O/UART × 2 channel
Clock synchronous serial I/O, UART, I2C mode (I2C-bus), IE mode (IE BUS (1)),
multiprocessor communication function
1
Synchronous Serial
Communication Unit (SSU)
LIN Module
A/D Converter
Hardware LIN: 1 (timer RA, UART0)
10-bit resolution × 12 channels, includes sample and hold function, with sweep
mode
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 10,000 times (data flash)
1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
• Background operation (BGO) function (data flash)
f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)
Flash Memory
Operating Frequency/Supply
Voltage
Current consumption
Operating Ambient Temperature
Package
TBD (VCC = 5.0 V, f(XIN) = 20 MHz)
TBD (VCC = 3.0 V, f(XIN) = 20 MHz)
-40 to 85°C (J version)
-40 to 125°C (K version) (2)
48-pin LQFP
Package code: PLQP0048KB-A (previous code: 48P6Q-A)
Notes:
1. IE BUS is a trademark of NEC Electronics Corporation.
2. Specify the K version if K version functions are to be used.
REJ03B0246-0010 Rev.0.10
Page 7 of 44
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 1.7
Item
CPU
Specifications for R8C/34H Group (1)
Function
Central processing
unit
Memory
ROM, RAM, Data
flash
Power Supply Voltage detection
Voltage
circuit
Detection
I/O Ports
Programmable I/O
ports
Clock
Clock generation
circuits
Interrupts
Watchdog Timer
DTC (Data Transfer Controller)
Timer
1. Overview
Timer RA
Timer RB
Timer RC
Timer RD
Timer RE
REJ03B0246-0010 Rev.0.10
Page 8 of 44
Specification
R8C/Tiny series core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Refer to Table 1.12 Product List for R8C/34H Group.
• Power-on reset
• Voltage detection 3 (detection level of voltage detection 1 selectable)
• Input-only: 1 pin
• CMOS I/O ports: 43, selectable pull-up resistor
3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),
High-speed on-chip oscillator (with frequency adjustment function),
Low-speed on-chip oscillator
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, high-speed on-chip oscillator,
low-speed on-chip oscillator), wait mode, stop mode
• Interrupt Vectors: 69
• External: 9 sources (INT × 5 , key input × 4)
• Priority levels: 7 levels
• 15 bits × 1 (with prescaler)
• Reset start selectable
• Low-speed on-chip oscillator for watchdog timer selectable
• 1 channel
• Activation sources: 31
• Transfer modes: 2 (normal mode, repeat mode)
8 bits (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait oneshot generation mode
16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
16 bits × 2 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 6 pins), reset synchronous PWM mode (output three-phase
waveforms (6 pins), sawtooth wave modulation), complementary PWM mode
(output three-phase waveforms (6 pins), triangular wave modulation), PWM3
mode (PWM output 2 pins with fixed period)
8 bits × 1
Output compare mode
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 1.8
Item
Serial
Interface
1. Overview
Specifications for R8C/34H Group (2)
Function
UART0, 1
UART2
Specification
Clock synchronous serial I/O/UART × 2 channel
Clock synchronous serial I/O, UART, I2C mode (I2C-bus), IE mode (IE BUS (1)),
multiprocessor communication function
1
Synchronous Serial
Communication Unit (SSU)
LIN Module
A/D Converter
Hardware LIN: 1 (timer RA, UART0)
10-bit resolution × 12 channels, includes sample and hold function, with sweep
mode
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 100 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)
Flash Memory
Operating Frequency/Supply
Voltage
Current consumption
Operating Ambient Temperature
Package
TBD (VCC = 5.0 V, f(XIN) = 20 MHz)
TBD (VCC = 3.0 V, f(XIN) = 20 MHz)
-40 to 85°C (J version)
-40 to 125°C (K version) (2)
48-pin LQFP
Package code: PLQP0048KB-A (previous code: 48P6Q-A)
Notes:
1. IE BUS is a trademark of NEC Electronics Corporation.
2. Specify the K version if K version functions are to be used.
REJ03B0246-0010 Rev.0.10
Page 9 of 44
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
1.2
1. Overview
Product List
Table 1.9 lists Product List for R8C/34E Group, Table 1.10 lists Product List for R8C/34F Group, Table 1.11 lists
Product List for R8C/34G Group, Table 1.12 lists Product List for R8C/34H Group.
Table 1.9
Product List for R8C/34E Group
Part No.
R5F21346EJFP (D)
R5F21347EJFP (D)
R5F21348EJFP (D)
R5F2134AEJFP (P)
R5F2134CEJFP (P)
R5F21346EKFP (D)
R5F21347EKFP (D)
R5F21348EKFP (D)
R5F2134AEKFP (P)
R5F2134CEKFP (P)
ROM Capacity
Program ROM
Data flash
32 Kbytes
1 Kbyte × 4
48 Kbytes
1 Kbyte × 4
64 Kbytes
1 Kbyte × 4
96 Kbytes
1 Kbyte × 4
128 Kbytes
1 Kbyte × 4
32 Kbytes
1 Kbyte × 4
48 Kbytes
1 Kbyte × 4
64 Kbytes
1 Kbyte × 4
96 Kbytes
1 Kbyte × 4
128 Kbytes
1 Kbyte × 4
Current of Apr. 2008
RAM
Capacity
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
Package Type
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
Remarks
J version
K version
(D): Under development
(P): Under planning
Part No.
R 5 F 21 34 6 E J FP
Package type:
FP: PLQP0048KB-A (0.5 mm pin-pitch, 7 mm square body)
CAN, DataFlash
E: CAN module and DataFlash
F: CAN module but no DataFlash
G: DataFlash but no CAN module
H: None
Classification
J: Operating ambient temperature -40°C to 85°C
K: Operating ambient temperature -40°C to 125°C
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/34E Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1
Part Number, Memory Size, and Package of R8C/34E Group
REJ03B0246-0010 Rev.0.10
Page 10 of 44
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Product List for R8C/34F Group
ROM Capacity
Part No.
RAM Capacity
Program ROM
R5F21346FJFP (D)
32 Kbytes
2.5 Kbytes
R5F21347FJFP (D)
48 Kbytes
4 Kbytes
R5F21348FJFP (D)
64 Kbytes
6 Kbytes
R5F2134AFJFP (P)
96 Kbytes
8 Kbytes
R5F2134CFJFP (P)
128 Kbytes
10 Kbytes
R5F21346FKFP (D)
32 Kbytes
2.5 Kbytes
R5F21347FKFP (D)
48 Kbytes
4 Kbytes
R5F21348FKFP (D)
64 Kbytes
6 Kbytes
R5F2134AFKFP (P)
96 Kbytes
8 Kbytes
R5F2134CFKFP (P)
128 Kbytes
10 Kbytes
1. Overview
Table 1.10
Current of Apr. 2008
Package Type
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
Remarks
J version
K version
(D): Under development
(P): Under planning
Part No.
R 5 F 21 34 6 F J FP
Package type:
FP: PLQP0048KB-A (0.5 mm pin-pitch, 7 mm square body)
CAN, DataFlash
E: CAN module and DataFlash
F: CAN module but no DataFlash
G: DataFlash but no CAN module
H: None
Classification
J: Operating ambient temperature -40°C to 85°C
K: Operating ambient temperature -40°C to 125°C
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/34F Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.2
Part Number, Memory Size, and Package of R8C/34F Group
REJ03B0246-0010 Rev.0.10
Page 11 of 44
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Product List for R8C/34G Group
ROM Capacity
Part No.
Program ROM
Data flash
R5F21346GJFP (D) 32 Kbytes
1 Kbyte × 4
R5F21347GJFP (D) 48 Kbytes
1 Kbyte × 4
R5F21348GJFP (D) 64 Kbytes
1 Kbyte × 4
R5F2134AGJFP (P) 96 Kbytes
1 Kbyte × 4
R5F2134CGJFP (P) 128 Kbytes
1 Kbyte × 4
R5F21346GKFP (D) 32 Kbytes
1 Kbyte × 4
R5F21347GKFP (D) 48 Kbytes
1 Kbyte × 4
R5F21348GKFP (D) 64 Kbytes
1 Kbyte × 4
R5F2134AGKFP (P) 96 Kbytes
1 Kbyte × 4
R5F2134CGKFP (P) 128 Kbytes
1 Kbyte × 4
1. Overview
Table 1.11
Current of Apr. 2008
RAM
Capacity
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
Package Type
Remarks
PLQP0048KB-A J version
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A K version
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
(D): Under development
(P): Under planning
Part No.
R 5 F 21 34 6 G J FP
Package type:
FP: PLQP0048KB-A (0.5 mm pin-pitch, 7 mm square body)
CAN, DataFlash
E: CAN module and DataFlash
F: CAN module but no DataFlash
G: DataFlash but no CAN module
H: None
Classification
J: Operating ambient temperature -40°C to 85°C
K: Operating ambient temperature -40°C to 125°C
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/34G Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.3
Part Number, Memory Size, and Package of R8C/34G Group
REJ03B0246-0010 Rev.0.10
Page 12 of 44
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Product List for R8C/34H Group
ROM Capacity
Part No.
RAM Capacity
Program ROM
R5F21346HJFP (D)
32 Kbytes
2.5 Kbytes
R5F21347HJFP (D)
48 Kbytes
4 Kbytes
R5F21348HJFP (D)
64 Kbytes
6 Kbytes
R5F2134AHJFP (P)
96 Kbytes
8 Kbytes
R5F2134CHJFP (P)
128 Kbytes
10 Kbytes
R5F21346HKFP (D)
32 Kbytes
2.5 Kbytes
R5F21347HKFP (D)
48 Kbytes
4 Kbytes
R5F21348HKFP (D)
64 Kbytes
6 Kbytes
R5F2134AHKFP (P)
96 Kbytes
8 Kbytes
R5F2134CHKFP (P)
128 Kbytes
10 Kbytes
1. Overview
Table 1.12
Current of Apr. 2008
Package Type
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
PLQP0048KB-A
Remarks
J version
K version
(D): Under development
(P): Under planning
Part No.
R 5 F 21 34 6 H J FP
Package type:
FP: PLQP0048KB-A (0.5 mm pin-pitch, 7 mm square body)
CAN, DataFlash
E: CAN module and DataFlash
F: CAN module but no DataFlash
G: DataFlash but no CAN module
H: None
Classification
J: Operating ambient temperature -40°C to 85°C
K: Operating ambient temperature -40°C to 125°C
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/34H Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.4
Part Number, Memory Size, and Package of R8C/34H Group
REJ03B0246-0010 Rev.0.10
Page 13 of 44
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
1.3
1. Overview
Block Diagram
Figure 1.5 shows a Block Diagram.
I/O ports
8
8
8
6
Port P0
Port P1
Port P2
Port P3
5
1
8
Port P4
Port 6
Peripheral functions
System clock
generation circuit
A/D converter
(10 bits × 12 channels)
Timers
Timer RA (8 bits)
Timer RB (8 bits)
Timer RC (16 bits)
Timer RD
(16 bits × 2)
Timer RE (8 bits)
Timer RF (16 bits)
Timer RG (16 bits)
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
UART or
clock synchronous serial I/O
(8 bits × 2 channels)
CAN module(3)
(1 channel)
clock synchronous serial I/O
with chip select
(8 bits × 1 channel)
LIN module
(1 channel)
DTC
Watchdog timer
(15 bits)
R8C/Tiny Series CPU core
R0H
R1H
R0L
R1L
R2
R3
A0
A1
FB
SB
USP
ISP
INTB
PC
Memory
ROM (1)
RAM (2)
FLG
Multiplier
Notes:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
3. Only in the R8C/34E Group and the R8C/34F Group.
Figure 1.5
Block Diagram
REJ03B0246-0010 Rev.0.10
Page 14 of 44
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
1.4
1. Overview
Pin Assignment
34
33
Apr 17, 2008
27
26
P4_5/INT0/ADTRG
28
P6_7/(INT3)(1)/TRCIOD/(RXD2)/(SCL2)(1)
P6_6/INT2/TRCIOC/(TXD2)/(SDA2)(1)
29
25
24
23
39
22
R8C/34E Group
R8C/34F Group
R8C/34G Group
R8C/34H Group
40
41
42
43
21
20
19
PLQP0048KB-A (48P6Q-A)
44
18
17
(Top view)
45
16
46
15
47
14
48
13
3
4
5
6
7
8
9
10 11 12
MODE
P4_3
P4_4
RESET
XOUT/P4_7
VSS/AVSS
XIN/P4_6
VCC/AVCC
P2_7/TRDIOD1
2
P3_5/(CLK2)(1)/SSCK
P3_3/INT3/CTS2/RTS2/(SSI)(1)/SCS
P3_4/(TXD2)/(SDA2)/(RXD2)/(SCL2)(1)/SSI/(SCS)(1)
REJ03B0246-0010 Rev.0.10
Page 15 of 44
30
38
Notes:
1. Can be assigned to the pin in parentheses by a program.
2. Only in the R8C/34E Group and the R8C/34F Group.
3. P4_2 is an input-only pin.
4. Confirm the pin 1 position on the package by referring to the package dimensions.
Pin Assignment (Top View)
31
37
1
Figure 1.6
32
P1_1/KI1/TRCIOA/TRCTRG/AN9
35
P1_2/KI2/TRCIOB/AN10
36
P0_6/AN1
P0_5/AN2
P0_4/TREO/AN3
VREF/P4_2(3)
P6_0/(TREO)(1)
P6_2/CRX0(2)
P6_1/CTX0(2)
P0_3/AN4
P0_2/AN5
P0_1/AN6
P0_0/AN7
P3_7/(TRAO)(1)/(TXD2)/(SDA2)/(RXD2)/(SCL2)(1)/SSO
P1_0/KI0/AN8
P0_7/AN0
P6_3/LVCMP2
P6_4
P6_5/INT4/(CLK2)(1)
P3_0/(TRAO)(1)
P3_1/(TRBO)(1)
Figure 1.6 shows Pin Assignment (Top View). Tables 1.13 and 1.14 outlines the Pin Name Information by Pin
Number.
P1_3/KI3/TRBO/AN11
P1_4/TRCCLK/TXD0
P1_5/(INT1)(1)/(TRAIO)(1)/RXD0
P1_6/CLK0
P1_7/INT1/(TRAIO)(1)
P2_0/TRDIOA0/TRDCLK
P2_1/TRDIOB0
P2_2/TRDIOC0
P2_3/TRDIOD0
P2_4/TRDIOA1
P2_5/TRDIOB1
P2_6/TRDIOC1
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 1.13
1. Overview
Pin Name Information by Pin Number (1)
I/O Pin Functions for of Peripheral Modules
Pin
Number
Control Pin
Port
1
P3_5
2
P3_3
3
P3_4
Interrupt
Timer
INT3
Serial Interface
Clock
Synchronous
Serial I/O
with Chip
Select
(CLK2)(1)
SSCK
CTS2/RTS2
(SSI)(1)/SCS
(TXD2)/(SDA2)/
(RXD2)/(SCL2)
SSI/(SCS)(1)
CAN
Module(2)
A/D Converter
Voltage Detection
Circuit
(1)
4
MODE
5
P4_3
6
P4_4
7
RESET
8
XOUT
9
VSS/AVSS
10
XIN
11
VCC/AVCC
P4_7
P4_6
12
P2_7
TRDIOD1
13
P2_6
TRDIOC1
14
P2_5
TRDIOB1
15
P2_4
TRDIOA1
16
P2_3
TRDIOD0
17
P2_2
TRDIOC0
18
P2_1
TRDIOB0
19
P2_0
TRDIOA0/
TRDCLK
20
P1_7
21
P1_6
22
P1_5
23
P1_4
24
P1_3
KI3
25
P4_5
INT0
26
P6_6
INT2
INT1
(TRAIO)
(1)
CLK0
INT1(1)
(TRAIO)
(1)
TRCCLK
RXD0
TXD0
TRBO
AN11
ADTRG
TRCIOC
(TXD2)/(SDA2)
(1)
Note:
1. This can be assigned to the pin in parentheses by a program.
2. Only for R8C/34E group and R8C/34F group.
REJ03B0246-0010 Rev.0.10
Page 16 of 44
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 1.14
1. Overview
Pin Name Information by Pin Number (2)
I/O Pin Functions for of Peripheral Modules
Pin
Number
Control Pin
Port
Interrupt
Timer
Serial Interface
Clock
Synchronous
Serial I/O
with Chip
Select
CAN
Module(2)
A/D Converter
Voltage Detection
Circuit
(RXD2)/(SCL2)
27
P6_7
INT3(1)
TRCIOD
28
P1_2
KI2
TRCIOB
AN10
29
P1_1
KI1
TRCIOA/
TRCTRG
AN9
30
P1_0
KI0
31
P3_1
(1)
AN8
(TRBO)
(1)
(TRAO)
32
P3_0
33
P6_5
34
P6_4
35
P6_3
LVCMP2
36
P0_7
AN0
37
P0_6
AN1
38
P0_5
AN2
39
P0_4
40
P4_2
41
P6_0
42
P6_2
CRX0(2)
43
P6_1
CTX0(2)
44
P0_3
AN4
45
P0_2
AN5
46
P0_1
AN6
47
P0_0
AN7
48
P3_7
(1)
(CLK2)(1)
INT4
TREO
AN3
VREF
(TREO)
(1)
(TRAO)
(1)
(TXD2)/(SDA2)/
(RXD2)/(SCL2)
(1)
Note:
1. This can be assigned to the pin in parentheses by a program.
2. Only for R8C/34E group and R8C/34F group.
REJ03B0246-0010 Rev.0.10
Page 17 of 44
Apr 17, 2008
SSO
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
1.5
1. Overview
Pin Functions
Tables 1.15 and 1.16 list Pin Functions.
Table 1.15
Pin Functions (1)
Item
Pin Name
I/O Type
Description
Power supply input VCC, VSS
−
Apply 2.7 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.
Analog power
supply input
AVCC, AVSS
−
Power supply for the A/D converter.
Connect a capacitor between AVCC and AVSS.
Reset input
RESET
I
Input “L” on this pin resets the MCU.
MODE
MODE
I
Connect this pin to VCC via a resistor.
XIN clock input
XIN
I
XIN clock output
XOUT
O
These pins are provided for XIN clock generation circuit I/O.
Connect a ceramic resonator or a crystal oscillator between
the XIN and XOUT pins (1). To use an external clock, input it
to the XIN pin and leave the XOUT pin open.
INT interrupt input
INT0 to INT4
I
INT interrupt input pins.
Key input interrupt
KI0 to KI3
I
Key input interrupt input pins
Timer RA
TRAIO
I/O
Timer RA I/O pin
TRAO
O
Timer RA output pin
Timer RB
TRBO
O
Timer RB output pin
Timer RC
TRCCLK
I
External clock input pin
TRCTRG
Timer RD
I
External trigger input pin
TRCIOA, TRCIOB,
TRCIOC, TRCIOD
I/O
Timer RC I/O pins
TRDIOA0, TRDIOA1,
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1
I/O
Timer RD I/O pins
TRDCLK
I
External clock input pin
Timer RE
TREO
O
Divided clock output pin
Serial interface
CLK0, CLK1, CLK2
I/O
Transfer clock I/O pins
SSU
RXD0, RXD2
I
Serial data input pins
TXD0, TXD2
O
Serial data output pins
CTS2
I
Transmission control input pin
RTS2
O
Reception control output pin
SCL2
I/O
I2C mode clock I/O pin
SDA2
I/O
I2C mode data I/O pin
SSI
I/O
Data I/O pin
SCS
I/O
Chip-select signal I/O pin
SSCK
I/O
Clock I/O pin
SSO
I/O
Data I/O pin
I: Input
O: Output
I/O: Input and output
Note:
1. Refer to the oscillator manufacturer for oscillation characteristics.
REJ03B0246-0010 Rev.0.10
Page 18 of 44
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 1.16
1. Overview
Pin Functions (2)
Item
CAN module
Pin Name
I/O Type
Description
CRX0(2)
I
CAN data input pin
CTX0(2)
O
CAN data output pin
Reference voltage
input
VREF
I
Reference voltage input pin to A/D converter
A/D converter
AN0 to AN11
I
Analog input pins to A/D converter
ADTRG
I
AD external trigger input pin
Voltage Detection
Circuit
LVCMP2
I
Detection target voltage pin for voltage detection 2
I/O port
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_1,
P3_3 to P3_5, P3_7,
P4_3 to P4_7,
P6_0 to P6_7
Input port
P4_2
I/O
I
CMOS I/O ports. Each port has an I/O select direction
register, allowing each pin in the port to be directed for input
or output individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
Input-only ports
I: Input
O: Output
I/O: Input and output
Note:
2. Only in the R8C/34E Group and the R8C/34F Group.
REJ03B0246-0010 Rev.0.10
Page 19 of 44
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
b31
b15
R2
R3
b8b7
b0
R0H (high-order of R0) R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
Data registers (1)
R2
R3
A0
A1
FB
b19
b15
Address registers (1)
Frame base register (1)
b0
Interrupt table register
INTBL
INTBH
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
b19
b0
PC
Program counter
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
b8
IPL
b7
Flag register
b0
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
Note:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Registers
REJ03B0246-0010 Rev.0.10
Page 20 of 44
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
2.1
2. Central Processing Unit (CPU)
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
REJ03B0246-0010 Rev.0.10
Page 21 of 44
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
2.8.7
2. Central Processing Unit (CPU)
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
REJ03B0246-0010 Rev.0.10
Page 22 of 44
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
3.
3. Memory
Memory
3.1
R8C/34E Group
Figure 3.1 is a Memory Map of R8C/34E Group. The R8C/34E Group has a 1-Mbyte address space from addresses
00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address
0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt
routine is stored here.
The internal ROM (data flash) is allocated addresses 03000h to 03FFFh.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 4-Kbyte internal
RAM area is allocated addresses 00400h to 013FFh. The internal RAM is used not only for data storage but also as
a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh (the SFR areas
for the CAN, DTC, and other modules). Peripheral function control registers are allocated here. All unallocated
spaces within the SFRs are reserved and cannot be accessed by users.
00000h
002FFh
SFR
(Refer to 4. Special
Function Registers
(SFRs))
00400h
Internal RAM
0XXXXh
02C00h
02FFFh
03000h
(2)
0FFDCh
SFR
(Refer to 4. Special Function
Registers (SFRs))
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Internal ROM
(data flash) (1)
03FFFh
0YYYYh
Watchdog timer, oscillation stop detection, voltage monitor
Address break
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. The DataFlash memory indicates blocks A (1 Kbyte), B (1 Kbyte), C (1 Kbyte), and D (1 Kbyte).
2. The SFR areas for the CAN, DTC and other modules are allocated to addresses 02C00h to 02FFFh.
3. The blank areas are reserved and cannot be accessed by users.
Internal ROM
Part Number
Size
Address 0YYYYh
R5F21346EJFP, R5F21346EKFP
32 Kbytes
R5F21347EJFP, R5F21347EKFP
R5F21348EJFP, R5F21348EKFP
R5F2134AEJFP, R5F2134AEKFP
R5F2134CEJFP, R5F2134CEKFP
Figure 3.1
Size
Address 0XXXXh
08000h
2.5 Kbytes
00DFFh
48 Kbytes
64 Kbytes
04000h
04000h
13FFFh
4 Kbytes
6 Kbytes
013FFh
01BFFh
96 Kbytes
128 Kbytes
04000h
04000h
1BFFFh
23FFFh
8 Kbytes
10 Kbytes
023FFh
02BFFh
Memory Map of R8C/34E Group
REJ03B0246-0010 Rev.0.10
Page 23 of 44
Internal RAM
Address ZZZZZh
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
3.2
3. Memory
R8C/34F Group
Figure 3.2 is a Memory Map of R8C/34F Group. The R8C/34F Group has a 1-Mbyte address space from addresses
00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address
0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt
routine is stored here.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 4-Kbyte internal
RAM area is allocated addresses 00400h to 013FFh. The internal RAM is used not only for data storage but also as
a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh (the SFR areas
for the CAN, DTC, and other modules). Peripheral function control registers are allocated here. All unallocated
spaces within the SFRs are reserved and cannot be accessed by users.
00000h
002FFh
SFR
(Refer to 4. Special
Function Registers
(SFRs))
00400h
Internal RAM
0XXXXh
02C00h
02FFFh
03000h
(1)
0FFDCh
SFR
(Refer to 4. Special Function
Registers (SFRs))
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer, oscillation stop detection, voltage monitor
0YYYYh
Address break
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. The SFR areas for the CAN, DTC and other modules are allocated to addresses 02C00h to 02FFFh.
2. The blank areas are reserved and cannot be accessed by users.
Internal ROM
Part Number
Internal RAM
Address ZZZZZh
Size
Address 0YYYYh
Size
Address 0XXXXh
R5F21346FJFP, R5F21346FKFP
32 Kbytes
08000h
2.5 Kbytes
00DFFh
R5F21347FJFP, R5F21347FKFP
R5F21348FJFP, R5F21348FKFP
R5F2134AFJFP, R5F2134AFKFP
48 Kbytes
64 Kbytes
04000h
04000h
13FFFh
4 Kbytes
6 Kbytes
013FFh
01BFFh
96 Kbytes
128 Kbytes
04000h
04000h
1BFFFh
23FFFh
8 Kbytes
10 Kbytes
023FFh
02BFFh
R5F2134CFJFP, R5F2134CFKFP
Figure 3.2
Memory Map of R8C/34F Group
REJ03B0246-0010 Rev.0.10
Page 24 of 44
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
3.3
3. Memory
R8C/34G Group
Figure 3.3 is a Memory Map of R8C/34G Group. The R8C/34G Group has a 1-Mbyte address space from addresses
00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address
0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt
routine is stored here.
The internal ROM (data flash) is allocated addresses 03000h to 03FFFh.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 4-Kbyte internal
RAM area is allocated addresses 00400h to 013FFh. The internal RAM is used not only for data storage but also as
a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh (the SFR areas
for the DTC and other modules). Peripheral function control registers are allocated here. All unallocated spaces
within the SFRs are reserved and cannot be accessed by users.
00000h
002FFh
SFR
(Refer to 4. Special
Function Registers
(SFRs))
00400h
Internal RAM
0XXXXh
02C00h
02FFFh
03000h
(2)
0FFDCh
SFR
(Refer to 4. Special Function
Registers (SFRs))
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Internal ROM
(data flash) (1)
03FFFh
0YYYYh
Watchdog timer, oscillation stop detection, voltage monitor
Address break
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. The DataFlash memory indicates blocks A (1 Kbyte), B (1 Kbyte), C (1 Kbyte), and D (1 Kbyte).
2. The SFR areas for the DTC and other modules are allocated to addresses 02C00h to 02FFFh.
3. The blank areas are reserved and cannot be accessed by users.
Internal ROM
Part Number
Size
Address 0YYYYh
R5F21346GJFP, R5F21346GKFP
32 Kbytes
R5F21347GJFP, R5F21347GKFP
R5F21348GJFP, R5F21348GKFP
R5F2134AGJFP, R5F2134AGKFP
R5F2134CGJFP, R5F2134CGKFP
Figure 3.3
Size
Address 0XXXXh
08000h
2.5 Kbytes
00DFFh
48 Kbytes
64 Kbytes
04000h
04000h
13FFFh
4 Kbytes
6 Kbytes
013FFh
01BFFh
96 Kbytes
128 Kbytes
04000h
04000h
1BFFFh
23FFFh
8 Kbytes
10 Kbytes
023FFh
02BFFh
Memory Map of R8C/34G Group
REJ03B0246-0010 Rev.0.10
Page 25 of 44
Internal RAM
Address ZZZZZh
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
3.4
3. Memory
R8C/34H Group
Figure 3.4 is a Memory Map of R8C/34H Group. The R8C/34H Group has a 1-Mbyte address space from addresses
00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address
0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt
routine is stored here.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 4-Kbyte internal
RAM area is allocated addresses 00400h to 013FFh. The internal RAM is used not only for data storage but also as
a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh (the SFR areas
for the DTC and other modules). Peripheral function control registers are allocated here. All unallocated spaces
within the SFRs are reserved and cannot be accessed by users.
00000h
002FFh
SFR
(Refer to 4. Special
Function Registers
(SFRs))
00400h
Internal RAM
0XXXXh
02C00h
02FFFh
03000h
(1)
0FFDCh
SFR
(Refer to 4. Special Function
Registers (SFRs))
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer, oscillation stop detection, voltage monitor
0YYYYh
Address break
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. The SFR areas for the DTC and other modules are allocated to addresses 02C00h to 02FFFh.
2. The blank areas are reserved and cannot be accessed by users.
Internal ROM
Part Number
Size
Address 0YYYYh
R5F21346HJFP, R5F21346HKFP
R5F21347HJFP, R5F21347HKFP
32 Kbytes
48 Kbytes
08000h
04000h
R5F21348HJFP, R5F21348HKFP
R5F2134AHJFP, R5F2134AHKFP
R5F2134CHJFP, R5F2134CHKFP
64 Kbytes
96 Kbytes
128 Kbytes
04000h
04000h
04000h
Figure 3.4
Memory Map of R8C/34H Group
REJ03B0246-0010 Rev.0.10
Page 26 of 44
Apr 17, 2008
Internal RAM
Address ZZZZZh
13FFFh
1BFFFh
23FFFh
Size
Address 0XXXXh
2.5 Kbytes
4 Kbytes
00DFFh
013FFh
6 Kbytes
8 Kbytes
10 Kbytes
01BFFh
023FFh
02BFFh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
4.
4. Special Function Registers (SFRs)
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.17 list the special
function registers.
Table 4.1
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
SFR Information (1) (1)
Register
Symbol
After reset
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Module Standby Control Register
System Clock Control Register 3
Protect Register
Reset Source Determination Register
Oscillation Stop Detection Register
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
PM0
PM1
CM0
CM1
MSTCR
CM3
PRCR
RSTFR
OCD
WDTR
WDTS
WDTC
00h
00h
00101000b
00100000b
00h
00h
00h
0XXX00XXb (2)
00000100b
XXh
XXh
00111111b
High-Speed On-Chip Oscillator Control Register 7
FRA7
When shipping
Count Source Protection Mode Register
CSPR
00h
10000000b (3)
High-Speed On-Chip Oscillator Control Register 0
High-Speed On-Chip Oscillator Control Register 1
High-Speed On-Chip Oscillator Control Register 2
On-Chip Reference Voltage Control Register
FRA0
FRA1
FRA2
OCVREFCR
00h
When shipping
00h
00h
High-Speed On-Chip Oscillator Control Register 4
High-Speed On-Chip Oscillator Control Register 5
High-Speed On-Chip Oscillator Control Register 6
FRA4
FRA5
FRA6
When Shipping
When Shipping
When Shipping
High-Speed On-Chip Oscillator Control Register 3
Voltage Monitor Circuit Control Register
Voltage Monitor Circuit Edge Select Register
FRA3
CMPA
VCAC
When shipping
00h
00h
Voltage Detect Register 1
Voltage Detect Register 2
VCA1
VCA2
00001000b
00h (4)
00100000b (5)
Voltage Detection 1 Level Select Register
VD1LS
00000111b
Voltage Monitor 0 Circuit Control Register
VW0C
1100X010b (4)
1100X011b (5)
10001010b
0039h
Voltage Monitor 1 Circuit Control Register
VW1C
X : Undefined
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
2. The CWR bit in the RSTFR register is set to 0 after power-on and voltage monitor 0 reset. Software reset, watchdog timer reset, or oscillation
stop detection reset does not affect this bit.
3. The CSPROINI bit in the OFS register is set to 0.
4. The LVDAS bit in the OFS register is set to 1.
5. The LVDAS bit in the OFS register is set to 0.
REJ03B0246-0010 Rev.0.10
Page 27 of 44
Apr 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 4.2
4. Special Function Registers (SFRs)
SFR Information (2) (1)
Address
Register
003Ah
Voltage Monitor 2 Circuit Control Register
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
Flash Memory Ready Interrupt Control Register
0042h
0043h
0044h
0045h
0046h
INT4 Interrupt Control Register
0047h
Timer RC Interrupt Control Register
0048h
Timer RD0 Interrupt Control Register
0049h
Timer RD1 Interrupt Control Register
004Ah
Timer RE Interrupt Control Register
004Bh
UART2 Transmit Interrupt Control Register
004Ch
UART2 Receive Interrupt Control Register
004Dh
Key Input Interrupt Control Register
004Eh
A/D Conversion Interrupt Control Register
004Fh
SSU Interrupt Control Register
0050h
0051h
UART0 Transmit Interrupt Control Register
0052h
UART0 Receive Interrupt Control Register
0053h
0054h
0055h
INT2 Interrupt Control Register
0056h
Timer RA Interrupt Control Register
0057h
0058h
Timer RB Interrupt Control Register
0059h
INT1 Interrupt Control Register
005Ah
INT3 Interrupt Control Register
005Bh
005Ch
005Dh
INT0 Interrupt Control Register
005Eh
UART2 Bus Collision Detection Interrupt Control Register
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
CAN0 Successful Reception Interrupt Control Register
006Dh
CAN0 Successful Transmission Interrupt Control Register
006Eh
CAN0 Receive FIFO Interrupt Control Register
006Fh
CAN0 Transmit FIFO Interrupt Control Register
0070h
CAN0 Error Interrupt Control Register
0071h
CAN0 Wake-up Interrupt Control Register
0072h
Voltage Monitor 1 Level Interrupt Control Register
0073h
Voltage Monitor 2 Level Interrupt Control Register
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
X : Undefined
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10
Page 28 of 44
Apr 17, 2008
VW2C
Symbol
After reset
10000010b
FMRDYIC
XXXXX000b
INT4IC
TRCIC
TRD0IC
TRD1IC
TREIC
S2TIC
S2RIC
KUPIC
ADIC
SSUIC
XX00X000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
S0TIC
S0RIC
XXXXX000b
XXXXX000b
INT2IC
TRAIC
XX00X000b
XXXXX000b
TRBIC
INT1IC
INT3IC
XXXXX000b
XX00X000b
XX00X000b
INT0IC
U2BCNIC
XX00X000b
XXXXX000b
C0RIC
C0TIC
C0FRIC
C0FTIC
C0EIC
C0WIC
VCMP1IC
VCMP2IC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 4.3
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
4. Special Function Registers (SFRs)
SFR Information (3) (1)
DTC Activation Control Register
Register
Symbol
DTCTL
00h
DTC Activation Enable Register 0
DTC Activation Enable Register 1
DTC Activation Enable Register 2
DTC Activation Enable Register 3
DTC Activation Enable Register 4
DTC Activation Enable Register 5
DTC Activation Enable Register 6
DTCEN0
DTCEN1
DTCEN2
DTCEN3
DTCEN4
DTCEN5
DTCEN6
00h
00h
00h
00h
00h
00h
00h
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
UART0 Transmit Buffer Register
U0MR
U0BRG
U0TB
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
UART2 Transmit Buffer Register
U2MR
U2BRG
U2TB
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
U2C0
U2C1
U2RB
UART2 Digital Filter Function Select Register
URXDF
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
UART2 Special Mode Register 5
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
U2SMR5
U2SMR4
U2SMR3
U2SMR2
U2SMR
00h
00h
000X0X0Xb
X0000000b
X0000000b
X : Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10
Page 29 of 44
Apr 17, 2008
After reset
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 4.4
4. Special Function Registers (SFRs)
SFR Information (4) (1)
Address
Register
00C0h
A/D Register 0
00C1h
00C2h
A/D Register 1
00C3h
00C4h
A/D Register 2
00C5h
00C6h
A/D Register 3
00C7h
00C8h
A/D Register 4
00C9h
00CAh
A/D Register 5
00CBh
00CCh
A/D Register 6
00CDh
00CEh
A/D Register 7
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
A/D Mode Register
00D5h
A/D Input Select Register
00D6h
A/D Control Register 0
00D7h
A/D Control Register 1
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
Port P0 Register
00E1h
Port P1 Register
00E2h
Port P0 Direction Register
00E3h
Port P1 Direction Register
00E4h
Port P2 Register
00E5h
Port P3 Register
00E6h
Port P2 Direction Register
00E7h
Port P3 Direction Register
00E8h
Port P4 Register
00E9h
00EAh
Port P4 Direction Register
00EBh
00ECh
Port P6 Register
00EDh
00EEh
Port P6 Direction Register
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
X : Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10
Page 30 of 44
Apr 17, 2008
Symbol
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
After reset
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
ADMOD
ADINSEL
ADCON0
ADCON1
00h
11000000b
00h
00h
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
PD4
00h
P6
XXh
PD6
00h
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 4.5
Address
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (5) (1)
Timer RA Control Register
Timer RA I/O Control Register
Timer RA Mode Register
Timer RA Prescaler Register
Timer RA Register
LIN0 Control Register 2
LIN0 Control Register
LIN0 Status Register
Timer RB Control Register
Timer RB One-Shot Control Register
Timer RB I/O Control Register
Timer RB Mode Register
Timer RB Prescaler Register
Timer RB Secondary Register
Timer RB Primary Register
Register
Symbol
TRACR
TRAIOC
TRAMR
TRAPRE
TRA
LIN0CR2
LIN0CR
LIN0ST
TRBCR
TRBOCR
TRBIOC
TRBMR
TRBPRE
TRBSC
TRBPR
00h
00h
00h
FFh
FFh
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
Timer RE Counter Data Register
Timer RE Compare Data Register
TRESEC
TREMIN
00h
00h
Timer RE Control Register 1
Timer RE Control Register 2
Timer RE Count Source Select Register
TRECR1
TRECR2
TRECSR
00h
00h
00001000b
Timer RC Mode Register
Timer RC Control Register 1
Timer RC Interrupt Enable Register
Timer RC Status Register
Timer RC I/O Control Register 0
Timer RC I/O Control Register 1
Timer RC Counter
TRCMR
TRCCR1
TRCIER
TRCSR
TRCIOR0
TRCIOR1
TRC
Timer RC General Register A
TRCGRA
Timer RC General Register B
TRCGRB
Timer RC General Register C
TRCGRC
Timer RC General Register D
TRCGRD
Timer RC Control Register 2
Timer RC Digital Filter Function Select Register
Timer RC Output Master Enable Register
Timer RC Trigger Control Register
TRCCR2
TRCDF
TRCOER
TRCADCR
01001000b
00h
01110000b
01110000b
10001000b
10001000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00011000b
00h
01111111b
00h
Timer RD Trigger Control Register
Timer RD Start Register
Timer RD Mode Register
Timer RD PWM Mode Register
Timer RD Function Control Register
Timer RD Output Master Enable Register 1
Timer RD Output Master Enable Register 2
Timer RD Output Control Register
Timer RD Digital Filter Function Select Register 0
Timer RD Digital Filter Function Select Register 1
TRDADCR
TRDSTR
TRDMR
TRDPMR
TRDFCR
TRDOER1
TRDOER2
TRDOCR
TRDDF0
TRDDF1
00h
11111100b
00001110b
10001000b
10000000b
FFh
01111111b
00h
00h
00h
The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10
Page 31 of 44
Apr 17, 2008
After reset
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 4.6
4. Special Function Registers (SFRs)
SFR Information (6) (1)
Address
Register
0140h
Timer RD Control Register 0
0141h
Timer RD I/O Control Register A0
0142h
Timer RD I/O Control Register C0
0143h
Timer RD Status Register 0
0144h
Timer RD Interrupt Enable Register 0
0145h
Timer RD PWM Mode Output Level Control Register 0
0146h
Timer RD Counter 0
0147h
0148h
Timer RD General Register A0
0149h
014Ah
Timer RD General Register B0
014Bh
014Ch
Timer RD General Register C0
014Dh
014Eh
Timer RD General Register D0
014Fh
0150h
Timer RD Control Register 1
0151h
Timer RD I/O Control Register A1
0152h
Timer RD I/O Control Register C1
0153h
Timer RD Status Register 1
0154h
Timer RD Interrupt Enable Register 1
0155h
Timer RD PWM Mode Output Level Control Register 1
0156h
Timer RD Counter 1
0157h
0158h
Timer RD General Register A1
0159h
015Ah
Timer RD General Register B1
015Bh
015Ch
Timer RD General Register C1
015Dh
015Eh
Timer RD General Register D1
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
X : Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10
Page 32 of 44
Apr 17, 2008
Symbol
TRDCR0
TRDIORA0
TRDIORC0
TRDSR0
TRDIER0
TRDPOCR0
TRD0
TRDGRA0
TRDGRB0
TRDGRC0
TRDGRD0
TRDCR1
TRDIORA1
TRDIORC1
TRDSR1
TRDIER1
TRDPOCR1
TRD1
TRDGRA1
TRDGRB1
TRDGRC1
TRDGRD1
After reset
00h
10001000b
10001000b
11100000b
11100000b
11111000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00h
10001000b
10001000b
11000000b
11100000b
11111000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 4.7
4. Special Function Registers (SFRs)
SFR Information (7) (1)
Address
Register
0180h
Timer RA Pin Select Register
0181h
Timer RB/RC Pin Select Register
0182h
Timer RC Pin Select Register 0
0183h
Timer RC Pin Select Register 1
0184h
Timer RD Pin Select Register 0
0185h
Timer RD Pin Select Register 1
0186h
Timer Pin Select Register
0187h
0188h
UART0 Pin Select Register
0189h
018Ah
UART2 Pin Select Register 0
018Bh
UART2 Pin Select Register 1
018Ch
SSU Pin Select Register
018Dh
018Eh
INT Interrupt Input Pin Select Register
018Fh
0190h
0191h
0192h
0193h
SS Bit Counter Register
0194h
SS Transmit Data Register
0195h
0196h
SS Receive Data Register
0197h
0198h
SS Control Register H
0199h
SS Control Register L
019Ah
SS Mode Register
019Bh
SS Enable Register
019Ch
SS Status Register
019Dh
SS Mode Register 2
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
Flash Memory Status Register
01B3h
01B4h
Flash Memory Control Register 0
01B5h
Flash Memory Control Register 1
01B6h
Flash Memory Control Register 2
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
X : Undefined
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10
Page 33 of 44
Apr 17, 2008
Symbol
TRASR
TRBRCSR
TRCPSR0
TRCPSR1
TRDPSR0
TRDPSR1
TIMSR
00h
00h
00h
00h
00h
00h
00h
U0SR
00h
U2SR0
U2SR1
SSUIICSR
00h
00h
00h
INTSR
00h
SSBR
SSTDR
SSCRH
SSCRL
SSMR
SSER
SSSR
SSMR2
11111000b
FFh
FFh
FFh
FFh
00h
01111101b
00011000b
00h
00h
00h
FST
10000X00b
FMR0
FMR1
FMR2
00h
00h
00h
SSRDR
After reset
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 4.8
4. Special Function Registers (SFRs)
SFR Information (8) (1)
Address
Register
01C0h
Address Match Interrupt Register 0
01C1h
01C2h
01C3h
Address Match Interrupt Enable Register 0
01C4h
Address Match Interrupt Register 1
01C5h
01C6h
01C7h
Address Match Interrupt Enable Register 1
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
Pull-Up Control Register 0
01E1h
Pull-Up Control Register 1
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
Input Threshold Control Register 0
01F6h
Input Threshold Control Register 1
01F7h
01F8h
01F9h
01FAh
External Input Enable Register 0
01FBh
External Input Enable Register 1
01FCh
INT Input Filter Select Register 0
01FDh
INT Input Filter Select Register 1
01FEh
Key Input Enable Register 0
01FFh
X : Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10
Page 34 of 44
Apr 17, 2008
Symbol
RMAD0
AIER1
After reset
XXh
XXh
0000XXXXb
00h
XXh
XXh
0000XXXXb
00h
PUR0
PUR1
00h
00h
VLT0
VLT1
00h
00h
INTEN
INTEN1
INTF
INTF1
KIEN
00h
00h
00h
00h
00h
AIER0
RMAD1
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 4.9
4. Special Function Registers (SFRs)
SFR Information (9) (1)
Address
Register
2C00h
DTC Transfer Vector Area
2C01h
DTC Transfer Vector Area
2C02h
DTC Transfer Vector Area
2C03h
DTC Transfer Vector Area
2C04h
DTC Transfer Vector Area
2C05h
DTC Transfer Vector Area
2C06h
DTC Transfer Vector Area
2C07h
DTC Transfer Vector Area
2C08h
DTC Transfer Vector Area
2C09h
DTC Transfer Vector Area
2C0Ah
DTC Transfer Vector Area
:
DTC Transfer Vector Area
:
DTC Transfer Vector Area
2C3Ah
DTC Transfer Vector Area
2C3Bh
DTC Transfer Vector Area
2C3Ch
DTC Transfer Vector Area
2C3Dh
DTC Transfer Vector Area
2C3Eh
DTC Transfer Vector Area
2C3Fh
DTC Transfer Vector Area
2C40h
DTC Control Data 0
2C41h
2C42h
2C43h
2C44h
2C45h
2C46h
2C47h
2C48h
DTC Control Data 1
2C49h
2C4Ah
2C4Bh
2C4Ch
2C4Dh
2C4Eh
2C4Fh
2C50h
DTC Control Data 2
2C51h
2C52h
2C53h
2C54h
2C55h
2C56h
2C57h
2C58h
DTC Control Data 3
2C59h
2C5Ah
2C5Bh
2C5Ch
2C5Dh
2C5Eh
2C5Fh
2C60h
DTC Control Data 4
2C61h
2C62h
2C63h
2C64h
2C65h
2C66h
2C67h
2C68h
DTC Control Data 5
2C69h
2C6Ah
2C6Bh
2C6Ch
2C6Dh
2C6Eh
2C6Fh
X : Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10
Page 35 of 44
Apr 17, 2008
Symbol
DTCD0
DTCD1
DTCD2
DTCD3
DTCD4
DTCD5
After reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 4.10
4. Special Function Registers (SFRs)
SFR Information (10) (1)
Address
Register
2C70h
DTC Control Data 6
2C71h
2C72h
2C73h
2C74h
2C75h
2C76h
2C77h
2C78h
DTC Control Data 7
2C79h
2C7Ah
2C7Bh
2C7Ch
2C7Dh
2C7Eh
2C7Fh
2C80h
DTC Control Data 8
2C81h
2C82h
2C83h
2C84h
2C85h
2C86h
2C87h
2C88h
DTC Control Data 9
2C89h
2C8Ah
2C8Bh
2C8Ch
2C8Dh
2C8Eh
2C8Fh
2C90h
DTC Control Data 10
2C91h
2C92h
2C93h
2C94h
2C95h
2C96h
2C97h
2C98h
DTC Control Data 11
2C99h
2C9Ah
2C9Bh
2C9Ch
2C9Dh
2C9Eh
2C9Fh
2CA0h
DTC Control Data 12
2CA1h
2CA2h
2CA3h
2CA4h
2CA5h
2CA6h
2CA7h
2CA8h
DTC Control Data 13
2CA9h
2CAAh
2CABh
2CACh
2CADh
2CAEh
2CAFh
X : Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10
Page 36 of 44
Apr 17, 2008
Symbol
DTCD6
DTCD7
DTCD8
DTCD9
DTCD10
DTCD11
DTCD12
DTCD13
After reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 4.11
4. Special Function Registers (SFRs)
SFR Information (11) (1)
Address
Register
2CB0h
DTC Control Data 14
2CB1h
2CB2h
2CB3h
2CB4h
2CB5h
2CB6h
2CB7h
2CB8h
DTC Control Data 15
2CB9h
2CBAh
2CBBh
2CBCh
2CBDh
2CBEh
2CBFh
2CC0h
DTC Control Data 16
2CC1h
2CC2h
2CC3h
2CC4h
2CC5h
2CC6h
2CC7h
2CC8h
DTC Control Data 17
2CC9h
2CCAh
2CCBh
2CCCh
2CCDh
2CCEh
2CCFh
2CD0h
DTC Control Data 18
2CD1h
2CD2h
2CD3h
2CD4h
2CD5h
2CD6h
2CD7h
2CD8h
DTC Control Data 19
2CD9h
2CDAh
2CDBh
2CDCh
2CDDh
2CDEh
2CDFh
2CE0h
DTC Control Data 20
2CE1h
2CE2h
2CE3h
2CE4h
2CE5h
2CE6h
2CE7h
2CE8h
DTC Control Data 21
2CE9h
2CEAh
2CEBh
2CECh
2CEDh
2CEEh
2CEFh
X : Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10
Page 37 of 44
Apr 17, 2008
Symbol
DTCD14
DTCD15
DTCD16
DTCD17
DTCD18
DTCD19
DTCD20
DTCD21
After reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 4.12
4. Special Function Registers (SFRs)
SFR Information (12) (1)
Address
Register
2CF0h
DTC Control Data 22
2CF1h
2CF2h
2CF3h
2CF4h
2CF5h
2CF6h
2CF7h
2CF8h
DTC Control Data 23
2CF9h
2CFAh
2CFBh
2CFCh
2CFDh
2CFEh
2CFFh
2D00h
2D01h
:
2E00h
CAN0 Mailbox 0 : Message ID
2E01h
2E02h
2E03h
2E04h
2E05h
CAN0 Mailbox 0 : Data length
2E06h
CAN0 Mailbox 0 : Data field
2E07h
2E08h
2E09h
2E0Ah
2E0Bh
2E0Ch
2E0Dh
2E0Eh
CAN0 Mailbox 0 : Time stamp
2E0Fh
2E10h
CAN0 Mailbox 1 : Message ID
2E11h
2E12h
2E13h
2E14h
2E15h
CAN0 Mailbox 1 : Data length
2E16h
CAN0 Mailbox 1 : Data field
2E17h
2E18h
2E19h
2E1Ah
2E1Bh
2E1Ch
2E1Dh
2E1Eh
CAN0 Mailbox 1 : Time stamp
2E1Fh
2E20h
CAN0 Mailbox 2 : Message ID
2E21h
2E22h
2E23h
2E24h
2E25h
CAN0 Mailbox 2 : Data length
2E26h
CAN0 Mailbox 2 : Data field
2E27h
2E28h
2E29h
2E2Ah
2E2Bh
2E2Ch
2E2Dh
2E2Eh
CAN0 Mailbox 2 : Time stamp
2E2Fh
X : Undefined
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10
Page 38 of 44
Apr 17, 2008
Symbol
DTCD22
DTCD23
C0MB0
After reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB1
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB2
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 4.13
4. Special Function Registers (SFRs)
SFR Information (13) (1)
Address
Register
2E30h
CAN0 Mailbox 3 : Message ID
2E31h
2E32h
2E33h
2E34h
2E35h
CAN0 Mailbox 3 : Data length
2E36h
CAN0 Mailbox 3 : Data field
2E37h
2E38h
2E39h
2E3Ah
2E3Bh
2E3Ch
2E3Dh
2E3Eh
CAN0 Mailbox3 : Time stamp
2E3Fh
2E40h
CAN0 Mailbox4 : Message ID
2E41h
2E42h
2E43h
2E44h
2E45h
CAN0 Mailbox4 : Data length
2E46h
CAN0 Mailbox4 : Data field
2E47h
2E48h
2E49h
2E4Ah
2E4Bh
2E4Ch
2E4Dh
2E4Eh
CAN0 Mailbox4 : Time stamp
2E4Fh
2E50h
CAN0 Mailbox5 : Message ID
2E51h
2E52h
2E53h
2E54h
2E55h
CAN0 Mailbox5 : Data length
2E56h
CAN0 Mailbox5 : Data field
2E57h
2E58h
2E59h
2E5Ah
2E5Bh
2E5Ch
2E5Dh
2E5Eh
CAN0 Mailbox5 : Time stamp
2E5Fh
2E60h
CAN0 Mailbox6 : Message ID
2E61h
2E62h
2E63h
2E64h
2E65h
CAN0 Mailbox6 : Data length
2E66h
CAN0 Mailbox6 : Data field
2E67h
2E68h
2E69h
2E6Ah
2E6Bh
2E6Ch
2E6Dh
2E6Eh
CAN0 Mailbox6 : Time stamp
2E6Fh
X : Undefined
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10
Page 39 of 44
Apr 17, 2008
Symbol
C0MB3
After reset
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB4
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB5
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB6
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 4.14
4. Special Function Registers (SFRs)
SFR Information (14) (1)
Address
Register
2E70h
CAN0 Mailbox7 : Message ID
2E71h
2E72h
2E73h
2E74h
2E75h
CAN0 Mailbox7 : Data length
2E76h
CAN0 Mailbox7 : Data field
2E77h
2E78h
2E79h
2E7Ah
2E7Bh
2E7Ch
2E7Dh
2E7Eh
CAN0 Mailbox7 : Time stamp
2E7Fh
2E80h
CAN0 Mailbox8 : Message ID
2E81h
2E82h
2E83h
2E84h
2E85h
CAN0 Mailbox8 : Data length
2E86h
CAN0 Mailbox8 : Data field
2E87h
2E88h
2E89h
2E8Ah
2E8Bh
2E8Ch
2E8Dh
2E8Eh
CAN0 Mailbox8 : Time stamp
2E8Fh
2E90h
CAN0 Mailbox9 : Message ID
2E91h
2E92h
2E93h
2E94h
2E95h
CAN0 Mailbox9 : Data length
2E96h
CAN0 Mailbox9 : Data field
2E97h
2E98h
2E99h
2E9Ah
2E9Bh
2E9Ch
2E9Dh
2E9Eh
CAN0 Mailbox9 : Time stamp
2E9Fh
2EA0h
CAN0 Mailbox10 : Message ID
2EA1h
2EA2h
2EA3h
2EA4h
2EA5h
CAN0 Mailbox10 : Data length
2EA6h
CAN0 Mailbox10 : Data field
2EA7h
2EA8h
2EA9h
2EAAh
2EABh
2EACh
2EADh
2EAEh
CAN0 Mailbox10 : Time stamp
2EAFh
X : Undefined
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10
Page 40 of 44
Apr 17, 2008
Symbol
C0MB7
After reset
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB8
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB9
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB10
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 4.15
4. Special Function Registers (SFRs)
SFR Information (15) (1)
Address
Register
2EB0h
CAN0 Mailbox11 : Message ID
2EB1h
2EB2h
2EB3h
2EB4h
2EB5h
CAN0 Mailbox11 : Data length
2EB6h
CAN0 Mailbox11 : Data field
2EB7h
2EB8h
2EB9h
2EBAh
2EBBh
2EBCh
2EBDh
2EBEh
CAN0 Mailbox11 : Time stamp
2EBFh
2EC0h
CAN0 Mailbox12 : Message ID
2EC1h
2EC2h
2EC3h
2EC4h
2EC5h
CAN0 Mailbox12 : Data length
2EC6h
CAN0 Mailbox12 : Data field
2EC7h
2EC8h
2EC9h
2ECAh
2ECBh
2ECCh
2ECDh
2ECEh
CAN0 Mailbox12 : Time stamp
2ECFh
2ED0h
CAN0 Mailbox13 : Message ID
2ED1h
2ED2h
2ED3h
2ED4h
2ED5h
CAN0 Mailbox13 : Data length
2ED6h
CAN0 Mailbox13 : Data field
2ED7h
2ED8h
2ED9h
2EDAh
2EDBh
2EDCh
2EDDh
2EDEh
CAN0 Mailbox13 : Time stamp
2EDFh
2EE0h
CAN0 Mailbox14 : Message ID
2EE1h
2EE2h
2EE3h
2EE4h
2EE5h
CAN0 Mailbox14 : Data length
2EE6h
CAN0 Mailbox14 : Data field
2EE7h
2EE8h
2EE9h
2EEAh
2EEBh
2EECh
2EEDh
2EEEh
CAN0 Mailbox14 : Time stamp
2EEFh
X : Undefined
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10
Page 41 of 44
Apr 17, 2008
Symbol
C0MB11
After reset
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB12
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB13
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MB14
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 4.16
4. Special Function Registers (SFRs)
SFR Information (16) (1)
Address
Register
2EF0h
CAN0 Mailbox15 : Message ID
2EF1h
2EF2h
2EF3h
2EF4h
2EF5h
CAN0 Mailbox15 : Data length
2EF6h
CAN0 Mailbox15 : Data field
2EF7h
2EF8h
2EF9h
2EFAh
2EFBh
2EFCh
2EFDh
2EFEh
CAN0 Mailbox15 : Time stamp
2EFFh
2F00h
2F01h
2F02h
2F03h
2F04h
2F05h
2F06h
2F07h
2F08h
2F09h
2F0Ah
2F0Bh
2F0Ch
2F0Dh
2F0Eh
2F0Fh
2F10h
CAN0 Mask Register 0
2F11h
2F12h
2F13h
2F14h
CAN0 Mask Register 1
2F15h
2F16h
2F17h
2F18h
CAN0 Mask Register 2
2F19h
2F1Ah
2F1Bh
2F1Ch
CAN0 Mask Register 3
2F1Dh
2F1Eh
2F1Fh
2F20h
CAN0 FIFO Received ID Compare Register 0
2F21h
2F22h
2F23h
2F24h
CAN0 FIFO Received ID Compare Register 1
2F25h
2F26h
2F27h
2F28h
2F29h
2F2Ah
CAN0 Mask Invalid Register
2F2Bh
2F2Ch
2F2Dh
2F2Eh
CAN0 Mailbox Interrupt Enable Register
2F2Fh
2F30h
CAN0 Message Control Register 0
2F31h
CAN0 Message Control Register 1
2F32h
CAN0 Message Control Register 2
2F33h
CAN0 Message Control Register 3
2F34h
CAN0 Message Control Register 4
2F35h
CAN0 Message Control Register 5
2F36h
CAN0 Message Control Register 6
2F37h
CAN0 Message Control Register 7
2F38h
CAN0 Message Control Register 8
2F39h
CAN0 Message Control Register 9
2F3Ah
CAN0 Message Control Register 10
X : Undefined
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0246-0010 Rev.0.10
Page 42 of 44
Apr 17, 2008
Symbol
C0MB15
After reset
XXXX XXXXh
XXh
XXXX XXXX
XXXX XXXXh
XXXXh
C0MKR0
XXXX XXXXh
C0MKR1
XXXX XXXXh
C0MKR2
XXXX XXXXh
C0MKR3
XXXX XXXXh
C0FIDCR0
XXXX XXXXh
C0FIDCR1
XXXX XXXXh
C0MKIVLR
XXXXh
C0MIER
XXXXh
C0MCTL0
C0MCTL1
C0MCTL2
C0MCTL3
C0MCTL4
C0MCTL5
C0MCTL6
C0MCTL7
C0MCTL8
C0MCTL9
C0MCTL10
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Table 4.17
4. Special Function Registers (SFRs)
SFR Information (17) (1)
Address
Register
2F3Bh
CAN0 Message Control Register 11
2F3Ch
CAN0 Message Control Register 12
2F3Dh
CAN0 Message Control Register 13
2F3Eh
CAN0 Message Control Register 14
2F3Fh
CAN0 Message Control Register 15
2F40h
CAN0 Control Register
2F41h
2F42h
CAN0 Status Register
2F43h
2F44h
CAN0 Bit Configuration Register
2F45h
2F46h
2F47h
2F48h
CAN0 Receive FIFO Control Register
2F49h
CAN0 Receive FIFO Pointer Control Register
2F4Ah
CAN0 Transmit FIFO Control Register
2F4Bh
CAN0 Transmit FIFO Pointer Control Register
2F4Ch
CAN0 Error Interrupt Enable Register
2F4Dh
CAN0 Error Interrupt Factor Judge Register
2F4Eh
CAN0 Reception Error Count Register
2F4Fh
CAN0 Transmission Error Count Register
2F50h
CAN0 Error Code Store Register
2F51h
CAN0 Channel Search Support Register
2F52h
CAN0 Mailbox Search Status Register
2F53h
CAN0 Mailbox Search Mode Register
2F54h
CAN0 Time Stamp Register
2F55h
2F56h
CAN0 Acceptance Filter Support Register
2F57h
2F58h
CAN0 Test Control Register
:
FFDBh
Option Function Select Register 2
:
FFFFh
Option Function Select Register
X : Undefined
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
2. This register cannot be changed by a program. Use a flash programmer to write to it.
REJ03B0246-0010 Rev.0.10
Page 43 of 44
Apr 17, 2008
Symbol
C0MCTL11
C0MCTL12
C0MCTL13
C0MCTL14
C0MCTL15
C0CTLR
C0BCR
After reset
00h
00h
00h
00h
00h
0000 0101b
0000 0000b
0000 0101b
0000 0000b
00 0000h
C0RFCR
C0RFPCR
C0TFCR
C0TFPCR
C0EIER
C0EIFR
C0RECR
C0TECR
C0ECSR
C0CSSR
C0MSSR
C0MSMR
C0TSR
1000 0000b
XXh
1000 0000b
XXh
00h
00h
00h
00h
00h
XXh
1000 0000b
XXXX XX00b
0000h
C0AFSR
XXXXh
C0TCR
00h
OFS2
(Note 2)
OFS
(Note 2)
C0STR
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Package Dimensions
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Technology website.
JEITA Package Code
P-LQFP48-7x7-0.50
RENESAS Code
PLQP0048KB-A
Previous Code
48P6Q-A
MASS[Typ.]
0.2g
HD
*1
D
36
25
37
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
24
bp
c
c1
*2
E
HE
b1
Reference Dimension in Millimeters
Symbol
48
13
1
ZE
Terminal cross section
12
c
A
F
A2
Index mark
ZD
A1
L
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
e
REJ03B0246-0010 Rev.0.10
Page 44 of 44
*3
bp
Detail F
x
Apr 17, 2008
8.8
8.8
0
0.17
0.09
0°
L1
y
Min
6.9
6.9
e
x
y
ZD
ZE
L
L1
0.35
Nom Max
7.0 7.1
7.0 7.1
1.4
9.0 9.2
9.0 9.2
1.7
0.1 0.2
0.22 0.27
0.20
0.145 0.20
0.125
8°
0.5
0.08
0.10
0.75
0.75
0.5 0.65
1.0
REVISION HISTORY
REVISION HISTORY
Rev.
Date
0.10
Apr 17, 2008
R8C/34E Group, R8C/34F Group, R8C/34G Group, R8C/34H Group
Shortsheet
R8C/34E Group, R8C/34F Group,
R8C/34G Group, R8C/34H Group
Shortsheet
Description
Page
−
Summary
First Edition issued
All trademarks and registered trademarks are the property of their respective owners.
C-1
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
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warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of Renesas or any third party with respect to the information in this document.
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but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
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destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
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result of errors or omissions in the information included in this document.
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(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
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Colophon .7.2
