R5F213G4DNSP

To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. Renesas Electronics products are classified according to the following three quality grades: “Standard”, “High Quality”, and “Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as “Specific” without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific” or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. “High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support. “Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. “Standard”: 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. R8C/3GD Group RENESAS MCU REJ03B0289-0100 Rev.1.00 Feb 26, 2010 1. 1.1 Overview Features The R8C/3GD Group of single-chip MCUs incorporates the R8C CPU core, employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high speed. In addition, the CPU core boasts a multiplier for high-speed operation processing. Power consumption is low, and the supported operating modes allow additional power control. These MCUs are designed to maximize EMI/EMS performance. Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of system components. 1.1.1 Applications Electronic household appliances, office equipment, audio equipment, consumer equipment, etc. REJ03B0289-0100 Rev.1.00 Page 1 of 41 Feb 26, 2010 R8C/3GD Group 1. Overview 1.1.2 Specifications Tables 1.1 and 1.2 outline the Specifications for R8C/3GD Group. Table 1.1 Item CPU Specifications for R8C/3GD Group (1) Function Central processing unit Specification R8C CPU core • Number of fundamental instructions: 89 • Minimum instruction execution time: 50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V) 200 ns (f(XIN) = 5 MHz, VCC = 1.8 to 5.5 V) • Multiplier: 16 bits × 16 bits 32 bits • Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits 32 bits • Operation mode: Single-chip mode (address space: 1 Mbyte) Refer to Table 1.3 Product List for R8C/3GD Group. • Power-on reset • Voltage detection 3 (detection level of voltage detection 0 and voltage detection 1 selectable) • Input-only: 1 pin • CMOS I/O ports: 19, selectable pull-up resistor • High current drive ports: 19 4 circuits: XIN clock oscillation circuit, XCIN clock oscillation circuit (32 kHz) High-speed on-chip oscillator (with frequency adjustment function), Low-speed on-chip oscillator, • Oscillation stop detection: XIN clock oscillation stop detection function • Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16 • Low power consumption modes: Standard operating mode (high-speed clock, low-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode Real-time clock (timer RE) • Number of interrupt vectors: 69 • External Interrupt: 7 (INT × 3, Key input × 4) • Priority levels: 7 levels • 14 bits × 1 (with prescaler) • Reset start selectable • Low-speed on-chip oscillator for watchdog timer selectable 8 bits × 1 (with 8-bit prescaler) Timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode 8 bits × 1 (with 8-bit prescaler) Timer mode (period timer), programmable waveform generation mode (PWM output), programmable one-shot generation mode, programmable wait oneshot generation mode 16 bits × 1 (with 4 capture/compare registers) Timer mode (input capture function, output compare function), PWM mode (output 3 pins), PWM2 mode (PWM output pin) 8 bits × 1 Real-time clock mode (count seconds, minutes, hours, days of week) Clock synchronous serial I/O/UART Clock synchronous serial I/O/UART, I2C mode (I2C-bus), multiprocessor communication function 10-bit resolution × 8 channels, includes sample and hold function, with sweep mode 2 circuits Memory Power Supply Voltage Detection I/O Ports ROM, RAM Voltage detection circuit Programmable I/O ports Clock generation circuits Clock Interrupts Watchdog Timer Timer Timer RA Timer RB Timer RC Timer RE Serial Interface A/D Converter Comparator B UART0 UART2 REJ03B0289-0100 Rev.1.00 Page 2 of 41 Feb 26, 2010 R8C/3GD Group 1. Overview Table 1.2 Item Flash Memory Specifications for R8C/3GD Group (2) Function Specification • Programming and erasure voltage: VCC = 2.7 to 5.5 V • Programming and erasure endurance: 1,000 times (program ROM) • Program security: ROM code protect, ID code check • Debug functions: On-chip debug, on-board flash rewrite function f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V) f(XIN) = 5 MHz (VCC = 1.8 to 5.5 V) Typ. 6.5mA (VCC = 5.0 V, f(XIN) = 20 MHz) Typ. 3.5mA (VCC = 3.0 V, f(XIN) = 10 MHz) Typ. 3.5 (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz)) Typ. 2.0 (VCC = 3.0 V, stop mode) -20 to 85 C (N version) -40 to 85 C (D version) (1) 24-pin LSSOP Package code: PLSP0024JB-A (previous code: 24P2F-A) Operating Frequency/Supply Voltage Current consumption Operating Ambient Temperature Package Note: 1. Specify the D version if D version functions are to be used. REJ03B0289-0100 Rev.1.00 Page 3 of 41 Feb 26, 2010 R8C/3GD Group 1. Overview 1.2 Product List Table 1.3 lists Product List for R8C/3GD Group, and Figure 1.1 shows a Part Number, Memory Size, and Package of R8C/3GD Group. Table 1.3 Product List for R8C/3GD Group ROM Capacity 4 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes 4 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes RAM Capacity 1 Kbyte 1 Kbyte 1 Kbyte 1 Kbyte 1 Kbyte 1 Kbyte 1 Kbyte 1 Kbyte 1 Kbyte 1 Kbyte Current of Feb. 2010 Package Type PLSP0024JB-A PLSP0024JB-A PLSP0024JB-A PLSP0024JB-A PLSP0024JB-A PLSP0024JB-A PLSP0024JB-A PLSP0024JB-A PLSP0024JB-A PLSP0024JB-A Remarks N version Part No. R5F213G1DNSP R5F213G2DNSP R5F213G4DNSP R5F213G5DNSP R5F213G6DNSP R5F213G1DDSP (D) R5F213G2DDSP (D) R5F213G4DDSP (D) R5F213G5DDSP (D) R5F213G6DDSP (D) (D): Under development D version Part No. R 5 F 21 3G 6 D N SP Package type: SP: PLSP0024JB-A (0.65 mm pin-pitch) Classification N: Operating ambient temperature -20° to 85° C C D: Operating ambient temperature -40° to 85° C C ROM capacity 1: 4KB 2: 8KB 4: 16KB 5: 24KB 6: 32KB R8C/3GD Group R8C/3x Series Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.1 Part Number, Memory Size, and Package of R8C/3GD Group REJ03B0289-0100 Rev.1.00 Page 4 of 41 Feb 26, 2010 R8C/3GD Group 1. Overview 1.3 Block Diagram Figure 1.2 shows a Block Diagram. 4 8 4 3 1 I/O ports Peripheral functions Timers Timer RA (8 bits 1) Timer RB (8 bits 1) Timer RC (16 bits 1) Timer RE (8 bits 1) Watchdog timer (14 bits) A/D converter (10 bits 8 channels) Port P0 Port P1 Port P3 Port P4 UART or clock synchronous serial I/O (8 bits 2) System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator XCIN-XCOUT Low-speed on-chip oscillator for watchdog timer Voltage detection circuit Comparator B R8C CPU core R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG Memory ROM (1) RAM (2) Multiplier Notes: 1. ROM size varies with MCU type. 2. RAM size varies with MCU type. Figure 1.2 Block Diagram REJ03B0289-0100 Rev.1.00 Page 5 of 41 Feb 26, 2010 R8C/3GD Group 1. Overview 1.4 Pin Assignment Figure 1.3 shows Pin Assignment (Top View). Table 1.4 outlines the Pin Name Information by Pin Number. P0_2/AN5(/TRCIOA/TRCTRG) P0_1/AN6(/TRCIOA/TRCTRG) P4_2/VREF MODE RESET P4_7/XOUT(/XCOUT) VSS/AVSS P4_6/XIN(/XCIN) VCC/AVCC P3_7/TRAO(/RXD2/SCL2/TXD2/SDA2) P3_5(/CLK2/TRCIOD) P3_4/IVREF3(/RXD2/SCL2/TXD2/SDA2/TRCIOC) 1 2 3 4 24 23 22 21 20 19 18 17 16 15 14 13 P0_6/AN1(/TRCIOD) P0_7/AN0(/TRCIOC) P1_0/AN8/KI0(/TRCIOD) P1_1/AN9/KI1(/TRCIOA/TRCTRG) P1_2/AN10/Kl2(/TRCIOB) P1_3/AN11//Kl3/TRBO(/TRCIOC) P1_4(/TXD0/TRCCLK) P1_5(/INT1/RXD0/TRAIO) P1_6//IVREF1(/CLK0) P1_7/IVCMP1/INT1(/TRAIO) P4_5/ADTRG/INT0(/RXD2/SCL2) P3_3/IVCMP3/INT3(/CTS2/RTS2/TRCCLK) R8C/3GD Group PLSP0024JB-A (24P2F-A) (top view) 5 6 7 8 9 10 11 12 Notes: 1. Can be assigned to the pin in parentheses by a program. 2. Confirm the pin 1 position on the package by referring to the package dimensions. Figure 1.3 Pin Assignment (Top View) REJ03B0289-0100 Rev.1.00 Page 6 of 41 Feb 26, 2010 R8C/3GD Group 1. Overview Table 1.4 Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name Information by Pin Number Control Pin Port P0_2 P0_1 P4_2 MODE I/O Pin Functions for Peripheral Modules A/D Converter, Timer Serial Interface Comparator B (TRCIOA/TRCTRG) AN5 (TRCIOA/TRCTRG) AN6 VREF Interrupt RESET XOUT(/XCOUT) VSS/AVSS XIN(/XCIN) VCC/AVCC P4_7 P4_6 P3_7 P3_5 P3_4 P3_3 P4_5 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 KI3 KI2 KI1 KI0 INT3 INT0 INT1 (INT1) (TRAIO) (TRAIO) (TRCCLK) TRBO(/TRCIOC) (TRCIOB) (TRCIOA/TRCTRG) (TRCIOD) (TRCIOC) (TRCIOD) (CLK0) (RXD0) (TXD0) AN11 AN10 AN9 AN8 AN0 AN1 TRAO (TRCIOD) (TRCIOC) (TRCCLK) (RXD2/SCL2/ TXD2/SDA2) (CLK2) (RXD2/SCL2/ TXD2/SDA2) (CTS2/RTS2) (RXD2/SCL2) IVREF3 IVCMP3 ADTRG IVCMP1 IVREF1 Note: 1. Can be assigned to the pin in parentheses by a program. REJ03B0289-0100 Rev.1.00 Page 7 of 41 Feb 26, 2010 R8C/3GD Group 1. Overview 1.5 Pin Functions Table 1.5 lists Pin Functions. Table 1.5 Item Power supply input Pin Functions Pin Name VCC, VSS I/O Type Description Apply 1.8 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin. Power supply for the A/D converter. Connect a capacitor between AVCC and AVSS. I I I I/O I O I I I/O O O I I I/O I/O I O I O I/O I/O I I I I I I/O Input “L” on this pin resets the MCU. Connect this pin to VCC via a resistor. These pins are provided for XIN clock generation circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins (1). To use an external clock, input it to the XOUT pin and leave the XIN pin open. These pins are provided for XCIN clock generation circuit I/O. Connect a crystal oscillator between the XCIN and XCOUT pins (1). To use an external clock, input it to the XCIN pin and leave the XCOUT pin open. INT interrupt input pins. INT0 is timer RB, and RC input pin. Key input interrupt input pins Timer RA I/O pin Timer RA output pin Timer RB output pin External clock input pin External trigger input pin Timer RC I/O pins Transfer clock I/O pins Serial data input pins Serial data output pins Transmission control input pin Reception control output pin I2C mode clock I/O pin I2C mode data I/O pin Reference voltage input pin to A/D converter Analog input pins to A/D converter A/D external trigger input pin Comparator B analog voltage input pins Comparator B reference voltage input pins CMOS I/O ports. Each port h as an I/O select direction register, allowing each pin in the port to be directed for input or output individually. Any port set to input can be set to use a pull-up resistor or not by a program. All ports can be used as LED drive ports. Input-only port Analog power supply AVCC, AVSS input Reset input MODE XIN clock input XIN clock output XCIN clock input XCIN clock output INT interrupt input Key input interrupt Timer RA Timer RB Timer RC RESET MODE XIN XOUT XCIN XCOUT INT0, INT1, INT3 KI0 to KI3 TRAIO TRAO TRBO TRCCLK TRCTRG TRCIOA, TRCIOB, TRCIOC, TRCIOD Serial interface CLK0, CLK2 RXD0, RXD2 TXD0, TXD2 CTS2 RTS2 SCL2 SDA2 Reference voltage input A/D converter VREF AN0, AN1, AN5, AN6, AN8 to AN11 ADTRG Comparator B I/O port IVCMP1, IVCMP3 IVREF1, IVREF3 P0_1, P0_2, P0_6, P0_7, P1_0 to P1_7, P3_3 to P3_5, P3_7, P4_5 to P4_7 Input port P4_2 I I: Input O: Output I/O: Input and output Note: 1. Refer to the oscillator manufacturer for oscillation characteristics. REJ03B0289-0100 Rev.1.00 Page 8 of 41 Feb 26, 2010 R8C/3GD Group 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank. b31 b15 b8b7 b0 R2 R3 R0H (high-order of R0) R0L (low-order of R0) R1H (high-order of R1) R1L (low-order of R1) Data registers (1) R2 R3 A0 A1 FB b19 b15 b0 Address registers (1) Frame base register (1) INTBH INTBL Interrupt table register The 4 high order bits of INTB are INTBH and the 16 low order bits of INTB are INTBL. b19 b0 PC Program counter b15 b0 USP ISP SB b15 b0 User stack pointer Interrupt stack pointer Static base register FLG b15 b8 b7 b0 Flag register IPL U I OBSZDC Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bit Processor interrupt priority level Reserved bit Note: 1. These registers comprise a register bank. There are two register banks. Figure 2.1 CPU Registers REJ03B0289-0100 Rev.1.00 Page 9 of 41 Feb 26, 2010 R8C/3GD Group 2. Central Processing Unit (CPU) 2.1 Data Registers (R0, R1, R2, and R3) R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is analogous to R2R0. 2.2 Address Registers (A0 and A1) A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0). 2.3 Frame Base Register (FB) FB is a 16-bit register for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is a 20-bit register that indicates the starting address of an interrupt vector table. 2.5 Program Counter (PC) PC is 20 bits wide and indicates the address of the next instruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between USP and ISP. 2.7 Static Base Register (SB) SB is a 16-bit register for SB relative addressing. 2.8 Flag Register (FLG) FLG is an 11-bit register indicating the CPU state. 2.8.1 Carry Flag (C) The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 Debug Flag (D) The D flag is for debugging only. Set it to 0. 2.8.3 Zero Flag (Z) The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 Sign Flag (S) The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 Register Bank Select Flag (B) Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1. 2.8.6 Overflow Flag (O) The O flag is set to 1 when an operation results in an overflow; otherwise to 0. REJ03B0289-0100 Rev.1.00 Page 10 of 41 Feb 26, 2010 R8C/3GD Group 2. Central Processing Unit (CPU) 2.8.7 Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged. 2.8.8 Stack Pointer Select Flag (U) ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1. The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled. 2.8.10 Reserved Bit If necessary, set to 0. When read, the content is undefined. REJ03B0289-0100 Rev.1.00 Page 11 of 41 Feb 26, 2010 R8C/3GD Group 3. Memory 3. 3.1 Memory R8C/3GD Group Figure 3.1 is a Memory Map of R8C/3GD Group. Th e R8C/3GD Group has a 1-Mbyte address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt routine is stored here. The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 1-Kbyte internal RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only for data storage but also as a stack area when a subroutine is called or when an interrupt request is acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh. Peripheral function control registers are allocated here. All unallocated spaces within the SFRs are reserved and cannot be accessed by users. 00000h 002FFh 00400h SFR (Refer to 4. Special Function Registers (SFRs)) Internal RAM 0XXXXh 0FFD8h Reserved area 0FFDCh Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer, oscillation stop detection, voltage monitor 0YYYYh Internal ROM (program ROM) 0FFFFh 0FFFFh (Reserved) (Reserved) Reset FFFFFh Note: 1. The blank areas are reserved and cannot be accessed by users. Internal ROM Part Number R5F213G1DNSP, R5F213G1DDSP R5F213G2DNSP, R5F213G2DDSP R5F213G4DNSP, R5F213G4DDSP R5F213G5DNSP, R5F213G5DDSP R5F213G6DNSP, R5F213G6DDSP Size 4 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes Address 0YYYYh 0F000h 0E000h 0C000h 0A000h 08000h Size 1 Kbyte 1 Kbyte 1 Kbyte 1 Kbyte 1 Kbyte Internal RAM Address 0XXXXh 007FFh 007FFh 007FFh 007FFh 007FFh Figure 3.1 Memory Map of R8C/3GD Group REJ03B0289-0100 Rev.1.00 Page 12 of 41 Feb 26, 2010 R8C/3GD Group 4. Special Function Registers (SFRs) 4. Special Function Registers (SFRs) An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.7 list the special function registers and Table 4.8 lists the ID Code Areas and Option Function Select Area. Table 4.1 Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h SFR Information (1) (1) Register Symbol After Reset Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Module Standby Control Register System Clock Control Register 3 Protect Register Reset Source Determination Register Oscillation Stop Detection Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register PM0 PM1 CM0 CM1 MSTCR CM3 PRCR RSTFR OCD WDTR WDTS WDTC 00h 00h 00101000b 00100000b 00h 00h 00h 0XXXXXXXb (2) 00000100b XXh XXh 00111111b High-Speed On-Chip Oscillator Control Register 7 FRA7 When shipping Count Source Protection Mode Register CSPR 00h 10000000b (3) High-Speed On-Chip Oscillator Control Register 0 High-Speed On-Chip Oscillator Control Register 1 High-Speed On-Chip Oscillator Control Register 2 On-Chip Reference Voltage Control Register Clock Prescaler Reset Flag High-Speed On-Chip Oscillator Control Register 4 High-Speed On-Chip Oscillator Control Register 5 High-Speed On-Chip Oscillator Control Register 6 FRA0 FRA1 FRA2 OCVREFCR CPSRF FRA4 FRA5 FRA6 00h When shipping 00h 00h 00h When Shipping When Shipping When Shipping High-Speed On-Chip Oscillator Control Register 3 Voltage Monitor Circuit Control Register Voltage Monitor Circuit Edge Select Register Voltage Detect Register 1 Voltage Detect Register 2 FRA3 CMPA VCAC VCA1 VCA2 When shipping 00h 00h 00001000b 00h (4) 00100000b (5) 00000111b 1100X010b (4) 1100X011b (5) 10001010b Voltage Detection 1 Level Select Register Voltage Monitor 0 Circuit Control Register VD1LS VW0C 0039h Voltage Monitor 1 Circuit Control Register VW1C X: Undefined Notes: 1. The blank areas are reserved and cannot be accessed by users. 2. The CWR bit in the RSTFR register is set to 0 after power-on and voltage monitor 0 reset. Hardware reset, software reset, or watchdog timer reset does not affect this bit. 3. The CSPROINI bit in the OFS register is set to 0. 4. The LVDAS bit in the OFS register is set to 1. 5. The LVDAS bit in the OFS register is set to 0. REJ03B0289-0100 Rev.1.00 Page 13 of 41 Feb 26, 2010 R8C/3GD Group 4. Special Function Registers (SFRs) Table 4.2 SFR Information (2) (1) Symbol VW2C After Reset 10000010b Address Register 003Ah Voltage Monitor 2 Circuit Control Register 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h Flash Memory Ready Interrupt Control Register 0042h 0043h 0044h 0045h 0046h 0047h Timer RC Interrupt Control Register 0048h 0049h 004Ah Timer RE Interrupt Control Register 004Bh UART2 Transmit Interrupt Control Register 004Ch UART2 Receive Interrupt Control Register 004Dh Key Input Interrupt Control Register 004Eh A/D Conversion Interrupt Control Register 004Fh 0050h 0051h UART0 Transmit Interrupt Control Register 0052h UART0 Receive Interrupt Control Register 0053h 0054h 0055h 0056h Timer RA Interrupt Control Register 0057h 0058h Timer RB Interrupt Control Register 0059h INT1 Interrupt Control Register 005Ah INT3 Interrupt Control Register 005Bh 005Ch 005Dh INT0 Interrupt Control Register 005Eh UART2 Bus Collision Detection Interrupt Control Register 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h Voltage Monitor 1 Interrupt Control Register 0073h Voltage Monitor 2 Interrupt Control Register 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. FMRDYIC XXXXX000b TRCIC XXXXX000b TREIC S2TIC S2RIC KUPIC ADIC XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b S0TIC S0RIC XXXXX000b XXXXX000b TRAIC TRBIC INT1IC INT3IC XXXXX000b XXXXX000b XX00X000b XX00X000b INT0IC U2BCNIC XX00X000b XXXXX000b VCMP1IC VCMP2IC XXXXX000b XXXXX000b REJ03B0289-0100 Rev.1.00 Page 14 of 41 Feb 26, 2010 R8C/3GD Group 4. Special Function Registers (SFRs) Table 4.3 Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh SFR Information (3) (1) Register Symbol After Reset UART0 Transmit / Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register UART0 Transmit / Receive Control Register 0 UART0 Transmit / Receive Control Register 1 UART0 Receive Buffer Register UART2 Transmit / Receive Mode Register UART2 Bit Rate Register UART2 Transmit Buffer Register UART2 Transmit / Receive Control Register 0 UART2 Transmit / Receive Control Register 1 UART2 Receive Buffer Register UART2 Digital Filter Function Select Register U0MR U0BRG U0TB U0C0 U0C1 U0RB U2MR U2BRG U2TB U2C0 U2C1 U2RB URXDF 00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h UART2 Special Mode Register 5 UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register U2SMR5 U2SMR4 U2SMR3 U2SMR2 U2SMR 00h 00h 000X0X0Xb X0000000b X0000000b X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. REJ03B0289-0100 Rev.1.00 Page 15 of 41 Feb 26, 2010 R8C/3GD Group 4. Special Function Registers (SFRs) Table 4.4 SFR Information (4) (1) Symbol AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 After Reset XXXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb Address Register 00C0h A/D Register 0 00C1h 00C2h A/D Register 1 00C3h 00C4h A/D Register 2 00C5h 00C6h A/D Register 3 00C7h 00C8h A/D Register 4 00C9h 00CAh A/D Register 5 00CBh 00CCh A/D Register 6 00CDh 00CEh A/D Register 7 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h A/D Mode Register 00D5h A/D Input Select Register 00D6h A/D Control Register 0 00D7h A/D Control Register 1 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h Port P0 Register 00E1h Port P1 Register 00E2h Port P0 Direction Register 00E3h Port P1 Direction Register 00E4h 00E5h Port P3 Register 00E6h 00E7h Port P3 Direction Register 00E8h Port P4 Register 00E9h 00EAh Port P4 Direction Register 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. ADMOD ADINSEL ADCON0 ADCON1 00h 11000000b 00h 00h P0 P1 PD0 PD1 P3 PD3 P4 PD4 XXh XXh 00h 00h XXh 00h XXh 00h REJ03B0289-0100 Rev.1.00 Page 16 of 41 Feb 26, 2010 R8C/3GD Group 4. Special Function Registers (SFRs) Table 4.5 Address 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh 0140h : 017Fh Note: 1. SFR Information (5) (1) Register Timer RA Control Register Timer RA I/O Control Register Timer RA Mode Register Timer RA Prescaler Register Timer RA Register Symbol TRACR TRAIOC TRAMR TRAPRE TRA After Reset 00h 00h 00h FFh FFh Timer RB Control Register Timer RB One-Shot Control Register Timer RB I/O Control Register Timer RB Mode Register Timer RB Prescaler Register Timer RB Secondary Register Timer RB Primary Register TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBSC TRBPR 00h 00h 00h 00h FFh FFh FFh Timer RE Second Data Register Timer RE Minute Data Register Timer RE Hour Data Register Timer RE Day of Week Data Register Timer RE Control Register 1 Timer RE Control Register 2 Timer RE Count Source Select Register Timer RC Mode Register Timer RC Control Register 1 Timer RC Interrupt Enable Register Timer RC Status Register Timer RC I/O Control Register 0 Timer RC I/O Control Register 1 Timer RC Counter Timer RC General Register A Timer RC General Register B Timer RC General Register C Timer RC General Register D Timer RC Control Register 2 Timer RC Digital Filter Function Select Register Timer RC Output Master Enable Register Timer RC Trigger Control Register TRESEC TREMIN TREHR TREWK TRECR1 TRECR2 TRECSR TRCMR TRCCR1 TRCIER TRCSR TRCIOR0 TRCIOR1 TRC TRCGRA TRCGRB TRCGRC TRCGRD TRCCR2 TRCDF TRCOER TRCADCR 00h 00h 00h 00h 00h 00h 00001000b 01001000b 00h 01110000b 01110000b 10001000b 10001000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00011000b 00h 01111111b 00h The blank areas are reserved and cannot be accessed by users. REJ03B0289-0100 Rev.1.00 Page 17 of 41 Feb 26, 2010 R8C/3GD Group 4. Special Function Registers (SFRs) Table 4.6 SFR Information (6) (1) Symbol TRASR TRBRCSR TRCPSR0 TRCPSR1 After Reset 00h 00h 00h 00h Address Register 0180h Timer RA Pin Select Register 0181h Timer RC Pin Select Register 0182h Timer RC Pin Select Register 0 0183h Timer RC Pin Select Register 1 0184h 0185h 0186h 0187h 0188h UART0 Pin Select Register 0189h 018Ah UART2 Pin Select Register 0 018Bh UART2 Pin Select Register 1 018Ch 018Dh 018Eh INT Interrupt Input Pin Select Register 018Fh I/O Function Pin Select Register 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h Flash Memory Status Register 01B3h 01B4h Flash Memory Control Register 0 01B5h Flash Memory Control Register 1 01B6h Flash Memory Control Register 2 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. U0SR U2SR0 U2SR1 00h 00h 00h INTSR PINSR 00h 00h FST FMR0 FMR1 FMR2 10000X00b 00h 00h 00h REJ03B0289-0100 Rev.1.00 Page 18 of 41 Feb 26, 2010 R8C/3GD Group 4. Special Function Registers (SFRs) Table 4.7 SFR Information (7) (1) Symbol RMAD0 After Reset XXh XXh 0000XXXXb 00h XXh XXh 0000XXXXb Address Register 01C0h Address Match Interrupt Register 0 01C1h 01C2h 01C3h Address Match Interrupt Enable Register 01C4h Address Match Interrupt Register 1 01C5h 01C6h 01C7h 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh 01E0h Pull-Up Control Register 0 01E1h Pull-Up Control Register 1 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh 01F0h Port P1 Drive Capacity Control Register 01F1h 01F2h Drive Capacity Control Register 0 01F3h Drive Capacity Control Register 1 01F4h 01F5h Input Threshold Control Register 0 01F6h Input Threshold Control Register 1 01F7h 01F8h Comparator B Control Register 0 01F9h 01FAh External Input Enable Register 0 01FBh 01FCh INT Input Filter Select Register 0 01FDh 01FEh Key Input Enable Register 0 01FFh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users. AIER RMAD1 PUR0 PUR1 00h 00h P1DRR DRR0 DRR1 VLT0 VLT1 INTCMP INTEN INTF KIEN 00h 00h 00h 00h 00h 00h 00h 00h 00h REJ03B0289-0100 Rev.1.00 Page 19 of 41 Feb 26, 2010 R8C/3GD Group 4. Special Function Registers (SFRs) Table 4.8 Address : FFDBh : FFDFh : FFE3h : FFEBh : FFEFh : FFF3h : FFF7h : FFFBh : FFFFh Notes: 1. ID Code Areas and Option Function Select Area Register Option Function Select Register 2 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Option Function Select Register OFS OFS2 Symbol After Reset (Note 1) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 1) 2. The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program. Do not write additions to the option function select area. If the block including the option function select area is erased, the option function select area is set to FFh. When blank products are shipped, the option function select area is set to FFh. It is set to the written value after written by the user. When factory-programming products are shipped, the value of the option function select area is the value programmed by the user. The ID code areas are allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program. Do not write additions to the ID code areas. If the block including the ID code areas is erased, the ID code areas are set to FFh. When blank products are shipped, the ID code areas are set to FFh. They are set to the written value after written by the user. When factory-programming products are shipped, the value of the ID code areas is the value programmed by the user. REJ03B0289-0100 Rev.1.00 Page 20 of 41 Feb 26, 2010 R8C/3GD Group 5. Electrical Characteristics 5. Electrical Characteristics Table 5.1 Symbol VCC/AVCC VI VO Pd Topr Tstg Input voltage Output voltage Power dissipation Operating ambient temperature Storage temperature 40 C Topr 85 C Absolute Maximum Ratings Parameter Supply voltage Condition Rated Value 0.3 to 6.5 0.3 to VCC + 0.3 0.3 to VCC + 0.3 500 20 to 85 (N version) / 40 to 85 (D version) 65 to 150 Unit V V V mW C C REJ03B0289-0100 Rev.1.00 Page 21 of 41 Feb 26, 2010 R8C/3GD Group 5. Electrical Characteristics Table 5.2 Symbol Recommended Operating Conditions Parameter Conditions Standard Min. 1.8 0 Other than CMOS input CMOS Input level Input level selection input switching : 0.35 VCC function (I/O port) Input level selection : 0.5 VCC 4.0 V 2.7 V 1.8 V 4.0 V 2.7 V 1.8 V Input level selection 4.0 V : 0.7 VCC 2.7 V 1.8 V External clock input (XOUT) VCC 5.5 V 0.8 VCC 0.5 VCC VCC < 4.0 V 0.55 VCC VCC < 2.7 V 0.65 VCC VCC 5.5 V 0.65 VCC 0.7 VCC 0.8 VCC 0.85 VCC VCC < 4.0 V VCC < 2.7 V VCC 5.5 V VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 0.2 VCC 0.2 VCC 0.2 VCC 0.2 VCC 0.4 VCC 0.3 VCC 0.2 VCC 0.55 VCC 0.45 VCC 0.35 VCC 0.4 160 80 10 40 5 20 160 80 10 40 5 20 2.7 V 1.8 V 1.8 V 2.7 V 2.7 V 1.8 V 2.7 V 1.8 V 2.7 V 1.8 V VCC VCC VCC VCC VCC VCC 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 32 32.768 20 5 50 40 20 5 20 5 20 5 VCC < 2.7 V Typ. Max. 5.5 Unit V V V V V V V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA MHz MH z kHz MHz MHz MH z MHz MH z MHz MH z VCC/AVCC Supply voltage VSS/AVSS Supply voltage VIH Input “H” voltage VCC < 4.0 V 0.85 VCC VCC < 2.7 V 0.85 VCC 1.2 0 VIL Input “L” voltage Other than CMOS input CMOS Input level Input level selection switching : 0.35 VCC input function (I/O port) Input level selection : 0.5 VCC 4.0 V 2.7 V 1.8 V 4.0 V 2.7 V 1.8 V Input level selection 4.0 V : 0.7 VCC 2.7 V 1.8 V External clock input (XOUT) VCC 5.5 V VCC < 4.0 V VCC < 2.7 V VCC 5.5 V VCC < 4.0 V VCC < 2.7 V VCC 5.5 V VCC < 4.0 V VCC < 2.7 V 0 0 0 0 0 0 0 0 0 0 IOH(sum) IOH(sum) IOH(peak) IOH(avg) IOL(sum) IOL(sum) IOL(peak) IOL(avg) f(XIN) f(XCIN) fOCO-F Peak sum output “H” current Peak output “H” current Average output “H” current Peak sum output “L” current Peak output “L” current Average output “L” current Sum of all pins IOH(peak) Drive capacity Low Drive capacity High Drive capacity Low Drive capacity High Sum of all pins IOL(peak) Drive capacity Low Drive capacity High Drive capacity Low Drive capacity High Average sum output “H” current Sum of all pins IOH(avg) Average sum output “L” current Sum of all pins IOL(avg) XIN clock input oscillation frequency XCIN clock input oscillation frequency fOCO-F frequency System clock frequency fOCO40M When used as the count source for timer RC (3) VCC < 2.7 V VCC < 2.7 V VCC < 2.7 V f(BCLK) CPU clock frequency Notes: 1. VCC = 1.8 to 5.5 V at Topr = 20 to 85 C (N version) / 40 to 85 C (D version), unless otherwise specified. 2. The average output current indicates the average value of current measured during 100 ms. 3. fOCO40M can be used as the count source for timer RC in the range of VCC = 2.7 V to 5.5 V. REJ03B0289-0100 Rev.1.00 Page 22 of 41 Feb 26, 2010 R8C/3GD Group 5. Electrical Characteristics P0 P1 P3 P4 30pF Figure 5.1 Ports P0, P1, P3, P4 Timing Measurement Circuit REJ03B0289-0100 Rev.1.00 Page 23 of 41 Feb 26, 2010 R8C/3GD Group 5. Electrical Characteristics Table 5.3 Symbol A/D Converter Characteristics Parameter Resolution Absolute accuracy 10-bit mode Vref = AVCC Vref = AVCC = 5.0 V Vref = AVCC = 3.3 V Vref = AVCC = 3.0 V Vref = AVCC = 2.2 V 8-bit mode Vref = AVCC = 5.0 V Vref = AVCC = 3.3 V Vref = AVCC = 3.0 V Vref = AVCC = 2.2 V AN0, AN1, AN5, AN6, AN8 to AN11 input AN0, AN1, AN5, AN6, AN8 to AN11 input AN0, AN1, AN5, AN6, AN8 to AN11 input AN0, AN1, AN5, AN6, AN8 to AN11 input AN0, AN1, AN5, AN6, AN8 to AN11 input AN0, AN1, AN5, AN6, AN8 to AN11 input AN0, AN1, AN5, AN6, AN8 to AN11 input AN0, AN1, AN5, AN6, AN8 to AN11 input 5.5 V (2) 5.5 V (2) 5.5 V (2) 5.5 V (2) Conditions Standard Min. Typ. Max. 10 ±3 ±5 ±5 ±5 ±2 ±2 ±2 ±2 2 2 2 2 3 2.15 2.15 0.75 45 2.2 0 AVCC Vref 1.34 1.49 20 16 10 5 Unit Bit LSB LSB LSB LSB LSB LSB LSB LSB MHz MHz MHz MHz k s s s A V V V AD A/D conversion clock 4.0 3.2 2.7 2.2 Vref = AVCC Vref = AVCC Vref = AVCC Vref = AVCC Tolerance level impedance tCONV tSAMP IVref Vref VIA Conversion time Sampling time Vref current Reference voltage Analog input voltage (3) 2 MHz AD 4 MHz 10-bit mode 8-bit mode Vref = AVCC = 5.0 V, AD = 20 MHz Vref = AVCC = 5.0 V, AD = 20 MHz AD = 20 MHz Vcc = 5 V, XIN = f1 = AD = 20 MHz OCVREF On-chip reference voltage 1.19 Notes: 1. VCC/AVCC = Vref = 2.2 to 5.5 V, VSS = 0 V at Topr = 20 to 85 C (N version) / 40 to 85 C (D version), unless otherwise specified. 2. The A/D conversion result will be undefined in wait mode, stop mode, when the flash memory stops, and in low-currentconsumption mode. Do not perform A/D conversion in these states or transition to these states during A/D conversion. 3. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in 8-bit mode. Table 5.4 Symbol Vref VI td ICMP Comparator B Electrical Characteristics Parameter IVREF1, IVREF3 input reference voltage IVCMP1, IVCMP3 input voltage Offset Comparator output delay time (2) Comparator operating current VI = Vref ± 100 mV VCC = 5.0 V Condition Standard Min. 0 0.3 5 0.1 17.5 Typ. Max. VCC VCC 1.4 0.3 Unit V V mV s A 100 Notes: 1. VCC = 2.7 to 5.5 V, Topr = 20 to 85 C (N version) / 40 to 85 C (D version), unless otherwise specified. 2. When the digital filter is disabled. REJ03B0289-0100 Rev.1.00 Page 24 of 41 Feb 26, 2010 R8C/3GD Group 5. Electrical Characteristics Table 5.5 Symbol Flash Memory (Program ROM) Electrical Characteristics Parameter Program/erase endurance (2) Byte program time Block erase time Conditions Standard Min. 1,000 (3) 80 0.3 5+CPU clock × 3 cycles 0 30+CPU clock × 1 cycle 30+CPU clock × 1 cycle 2.7 1.8 0 Ambient temperature = 55 C 20 5.5 5.5 60 500 Typ. Max. Unit times s s ms s s s V V C year td(SR-SUS) Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Time from suspend until erase restart td(CMDRSTREADY) Time from when command is forcibly stopped until reading is enabled Program, erase voltage Read voltage Program, erase temperature Data hold time (7) Notes: 1. VCC = 2.7 to 5.5 V at Topr = 0 to 60 C, unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 1,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied. Suspend request (FMR21 bit) FST7 bit FST6 bit Fixed time Clock-dependent time Access restart td(SR-SUS) FST6, FST7: Bit in FST register FMR21: Bit in FMR2 register Figure 5.2 Time delay until Suspend REJ03B0289-0100 Rev.1.00 Page 25 of 41 Feb 26, 2010 R8C/3GD Group 5. Electrical Characteristics Table 5.6 Symbol Vdet0 Voltage Detection 0 Circuit Electrical Characteristics Parameter Voltage detection level Vdet0_0 (2) Voltage detection level Vdet0_1 (2) Voltage detection level Vdet0_2 Voltage detection level Vdet0_3 (2) (2) Condition Standard Min. 1.80 2.15 2.70 3.55 Typ. 1.90 2.35 2.85 3.80 6 1.5 100 Max. 2.05 2.50 3.05 4.05 150 Unit V V V V s A s Voltage detection 0 circuit response time (4) Voltage detection circuit self power consumption td(E-A) Waiting time until voltage detection circuit operation starts (3) At the falling of Vcc from 5 V to (Vdet0_0 0.1) V VCA25 = 1, VCC = 5.0 V Notes: 1. The measurement condition is VCC = 1.8 V to 5.5 V and Topr = 20 to 85 C (N version) / 40 to 85 C (D version). 2. Select the voltage detection level with bits VDSEL0 and VDSEL1 in the OFS register. 3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2 register to 0. 4. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0. Table 5.7 Symbol Vdet1 Voltage Detection 1 Circuit Electrical Characteristics Parameter Voltage detection level Vdet1_0 (2) Voltage detection level Vdet1_1 (2) Condition At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC At the falling of VCC Vdet1_0 to Vdet1_5 selected Vdet1_6 to Vdet1_F selected Standard Min. 2.00 2.15 2.30 2.45 2.60 2.75 2.85 3.00 3.15 3.30 3.45 3.60 3.75 3.90 4.05 4.20 Typ. 2.20 2.35 2.50 2.65 2.80 2.95 3.10 3.25 3.40 3.55 3.70 3.85 4.00 4.15 4.30 4.45 0.07 0.10 60 1.7 100 150 Max. 2.40 2.55 2.70 2.85 3.00 3.15 3.40 3.55 3.70 3.85 4.00 4.15 4.30 4.45 4.60 4.75 Unit V V V V V V V V V V V V V V V V V V s A s Voltage detection level Vdet1_2 (2) Voltage detection level Vdet1_3 (2) Voltage detection level Vdet1_4 (2) Voltage detection level Vdet1_5 (2) Voltage detection level Vdet1_6 (2) Voltage detection level Vdet1_7 (2) Voltage detection level Vdet1_8 (2) Voltage detection level Vdet1_9 (2) Voltage detection level Vdet1_A (2) Voltage detection level Vdet1_B (2) Voltage detection level Vdet1_C (2) Voltage detection level Vdet1_D (2) Voltage detection level Vdet1_E (2) Voltage detection level Vdet1_F (2) Hysteresis width at the rising of Vcc in voltage detection 1 circuit Voltage detection 1 circuit response time (3) Voltage detection circuit self power consumption td(E-A) Notes: 1. 2. 3. 4. Waiting time until voltage detection circuit operation starts (4) At the falling of Vcc from 5 V to (Vdet1_0 0.1) V VCA26 = 1, VCC = 5.0 V The measurement condition is VCC = 1.8 V to 5.5 V and Topr = 20 to 85 C (N version) / 40 to 85 C (D version). Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0. REJ03B0289-0100 Rev.1.00 Page 26 of 41 Feb 26, 2010 R8C/3GD Group 5. Electrical Characteristics Table 5.8 Symbol Vdet2 Voltage Detection 2 Circuit Electrical Characteristics Parameter Voltage detection level Vdet2_0 Hysteresis width at the rising of Vcc in voltage detection 2 circuit Voltage detection 2 circuit response time (2) Voltage detection circuit self power consumption At the falling of Vcc from 5 V to (Vdet2_0 0.1) V VCA27 = 1, VCC = 5.0 V Condition At the falling of VCC Standard Min. 3.70 Typ. 4.00 0.10 20 1.7 100 150 Max. 4.30 Unit V V s A s td(E-A) Waiting time until voltage detection circuit operation starts (3) Notes: 1. The measurement condition is VCC = 1.8 V to 5.5 V and Topr = 20 to 85 C (N version) / 40 to 85 C (D version). 2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2. 3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2 register to 0. Table 5.9 Symbol trth Power-on Reset Circuit (2) Parameter External power VCC rise gradient (1) Condition Standard Min. 0 Typ. Max. 50000 Unit mV/msec Notes: 1. The measurement condition is Topr = 20 to 85 C (N version) / 40 to 85 C (D version), unless otherwise specified. 2. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0. Vdet0 (1) trth External Power VCC 0.5 V tw(por) (2) Voltage detection 0 circuit response time trth Vdet0 (1) Internal reset signal 1 fOCO-S 32 1 fOCO-S 32 Notes: 1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection Circuit of Hardware Manual (REJ09B0518) for details. 2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable a power-on reset. When turning on the power after it falls with voltage monitor 0 reset enabled, maintain tw(por) for 1 ms or more. Figure 5.3 Power-on Reset Circuit Electrical Characteristics REJ03B0289-0100 Rev.1.00 Page 27 of 41 Feb 26, 2010 R8C/3GD Group 5. Electrical Characteristics Table 5.10 Symbol High-speed On-Chip Oscillator Circuit Electrical Characteristics Parameter High-speed on-chip oscillator frequency after reset Condition VCC = 1.8 V to 5.5 V 20 C Topr 85 C VCC = 1.8 V to 5.5 V 40 C Topr 85 C High-speed on-chip oscillator frequency when the FRA4 register correction value is written into the FRA1 register and the FRA5 register correction value into the FRA3 register (2) High-speed on-chip oscillator frequency when the FRA6 register correction value is written into the FRA1 register and the FRA7 register correction value into the FRA3 register Oscillation stability time Self power consumption at oscillation VCC = 1.8 V to 5.5 V 20 C Topr 85 C VCC = 1.8 V to 5.5 V 40 C Topr 85 C VCC = 1.8 V to 5.5 V 20 C Topr 85 C VCC = 1.8 V to 5.5 V 40 C Topr 85 C VCC = 5.0 V, Topr = 25 C VCC = 5.0 V, Topr = 25 C Standard Min. 38.4 38.0 35.389 35.020 30.72 30.40 36.864 36.864 32 32 0.5 400 Typ. 40 Max. 41.6 42.0 38.338 38.707 33.28 33.60 3 Unit MHz MHz MHz MHz MHz MHz ms A Notes: 1. VCC = 1.8 to 5.5 V, Topr = 20 to 85 C (N version) / 40 to 85 C (D version), unless otherwise specified. 2. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in UART mode. Table 5.11 Symbol fOCO-S Low-speed On-Chip Oscillator Circuit Electrical Characteristics Parameter Low-speed on-chip oscillator frequency Oscillation stability time Self power consumption at oscillation VCC = 5.0 V, Topr = 25 C VCC = 5.0 V, Topr = 25 C Condition Standard Min. 60 Typ. 125 30 2 Max. 250 100 Unit kHz s A Note: 1. VCC = 1.8 to 5.5 V, Topr = 20 to 85 C (N version) / 40 to 85 C (D version), unless otherwise specified. Table 5.12 Symbol td(P-R) Power Supply Circuit Timing Characteristics Parameter Time for internal power supply stabilization during power-on (2) Condition Standard Min. Typ. Max. 2000 Unit s Notes: 1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = 25 C. 2. Waiting time until the internal power supply generation circuit stabilizes during power-on. REJ03B0289-0100 Rev.1.00 Page 28 of 41 Feb 26, 2010 R8C/3GD Group 5. Electrical Characteristics Table 5.13 Symbol VOH Electrical Characteristics (1) [4.2 V Parameter Vcc Condition 5.5 V] Standard Min. VCC VCC 1. 0 2.0 2.0 IOH = 5 mA IOH = 200 A IOL = 5 mA IOL = 200 A 0.1 1.2 Typ. Max. VCC VCC VCC 2.0 2.0 0.5 Unit V V V V V V V Output “H” voltage Output “L” voltage Hysteresis Other than XOUT XOUT Drive capacity High VCC = 5V IOH = 20 mA Drive capacity Low VCC = 5V VCC = 5V Drive capacity Low VCC = 5V VOL Other than XOUT XOUT Drive capacity High VCC = 5V IOL = 20 mA VCC = 5V VT+-VT- INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, TRBO, TRCIOA, TRCIOB, TRCIOC, TRCIOD, TRCTRG, TRCCLK, ADTRG, RXD0, RXD2, CLK0, CLK2 RESET VI = 5 V, VCC = 5.0V VI = 0 V, VCC = 5.0V VI = 0 V, VCC = 5.0V 0.1 1.2 5.0 5.0 V A A k M M V IIH IIL RfXIN RfXCIN VRAM Input “H” current Input “L” current Feedback resistance Feedback resistance XIN XCIN RPULLUP Pull-up resistance 25 50 0.3 8 100 RAM hold voltage VCC During stop mode 1.8 Note: 1. 4.2 V 5.5 V at Topr = 20 to 85 C (N version) / 40 to 85 C (D version), f(XIN) = 20 MHz, unless otherwise specified. REJ03B0289-0100 Rev.1.00 Page 29 of 41 Feb 26, 2010 R8C/3GD Group 5. Electrical Characteristics Table 5.14 Symbol ICC Electrical Characteristics (2) [3.3 V Vcc 5.5 V] (Topr = 20 to 85 C (N version) / 40 to 85 C (D version), unless otherwise specified.) Parameter Condition XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO-F = 20 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO-F = 20 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO-F = 4 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-16 MSTTRC = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR27 = 1, VCA20 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz No division FMR27 = 1, VCA20 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz No division Program operation on RAM Flash memory off, FMSTP = 1, VCA20 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (peripheral clock off) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off, Topr = 25 C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85 C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Min. High-speed Power supply clock mode current (VCC = 3.3 to 5.5 V) Single-chip mode, output pins are open, other pins are VSS Standard Typ. Max. 6.5 15 Unit mA 5.3 12.5 mA 3.6 mA 3.0 mA 2.2 mA 1.5 mA High-speed on-chip oscillator mode 7.0 15 mA 3.0 mA 1 mA Low-speed on-chip oscillator mode Low-speed clock mode 90 400 A 85 400 A 47 A Wait mode 15 100 A 4 90 A 3.5 A Stop mode 2.0 5.0 A 5.0 A REJ03B0289-0100 Rev.1.00 Page 30 of 41 Feb 26, 2010 R8C/3GD Group 5. Electrical Characteristics Timing Requirements (Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25 C) Table 5.15 Symbol tc(XOUT) tWH(XOUT) tWL(XOUT) tc(XCIN) tWH(XCIN) tWL(XCIN) XOUT input cycle time XOUT input “H” width XOUT input “L” width XCIN input cycle time XCIN input “H” width XCIN input “L” width External clock input (XOUT, XCIN) Parameter Standard Min. 50 24 24 14 7 7 Max. Unit ns ns ns s s s tC(XOUT), tC(XCIN) tWH(XOUT), tWH(XCIN) VCC = 5 V External Clock Input tWL(XOUT), tWL(XCIN) Figure 5.4 External Clock Input Timing Diagram when VCC = 5 V Table 5.16 Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO) TRAIO Input Parameter TRAIO input cycle time TRAIO input “H” width TRAIO input “L” width Standard Min. 100 40 40 Max. Unit ns ns ns tC(TRAIO) tWH(TRAIO) VCC = 5 V TRAIO input tWL(TRAIO) Figure 5.5 TRAIO Input Timing Diagram when VCC = 5 V REJ03B0289-0100 Rev.1.00 Page 31 of 41 Feb 26, 2010 R8C/3GD Group 5. Electrical Characteristics Table 5.17 Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0, 2 Serial Interface Parameter CLKi input cycle time CLKi input “H” width CLKi input “L” width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time 0 50 90 Standard Min. 200 100 100 50 Max. Unit ns ns ns ns ns ns ns tC(CK) tW(CKH) VCC = 5 V CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0, 2 Figure 5.6 Serial Interface Timing Diagram when VCC = 5 V Table 5.18 Symbol tW(INH) tW(INL) External Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 3) Parameter INTi input “H” width, KIi input “H” width INTi input “L” width, KIi input “L” width Standard Min. 250 (1) 250 (2) Max. Unit ns ns Notes: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. VCC = 5 V INTi input (i = 0, 1, 3) KIi input (i = 0 to 3) tW(INL) tW(INH) Figure 5.7 Input Timing for External Interrupt INTi and Key Input Interrupt KIi when Vcc = 5 V REJ03B0289-0100 Rev.1.00 Page 32 of 41 Feb 26, 2010 R8C/3GD Group 5. Electrical Characteristics Table 5.19 Symbol VOH Electrical Characteristics (3) [2.7 V Parameter Vcc < 4.2 V] Condition Standard Min. VCC VCC 1. 0 0.5 0.5 Typ. Max. VCC VCC VCC 0.5 0.5 0.5 0.1 0.4 Unit V V V V V V V Output “H” voltage Other than XOUT XOUT Drive capacity High IOH = 5 mA Drive capacity Low IOH = 1 mA IOH = 200 A Drive capacity High IOL = 5 mA Drive capacity Low IOL = 1 mA IOL = 200 A VCC = 3.0 V VOL Output “L” voltage Other than XOUT XOUT VT+-VT- Hysteresis INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, TRBO, TRCIOA, TRCIOB, TRCIOC, TRCIOD, TRCTRG, TRCCLK, ADTRG, RXD0, RXD2, CLK0, CLK2 RESET VCC = 3.0 V VI = 3 V, VCC = 3.0 V VI = 0 V, VCC = 3.0 V VI = 0 V, VCC = 3.0 V 0.1 0.5 4.0 4.0 V A A k M M V IIH IIL RfXIN RfXCIN VRAM Input “H” current Input “L” current Feedback resistance Feedback resistance RAM hold voltage XIN XCIN RPULLUP Pull-up resistance 42 84 0.3 8 168 During stop mode 1.8 Note: 1. 2.7 V VCC < 4.2 V at Topr = 20 to 85 C (N version) / 40 to 85 C (D version), f(XIN) = 10 MHz, unless otherwise specified. REJ03B0289-0100 Rev.1.00 Page 33 of 41 Feb 26, 2010 R8C/3GD Group 5. Electrical Characteristics Table 5.20 Symbol ICC Electrical Characteristics (4) [2.7 V Vcc < 3.3 V] (Topr = 20 to 85 C (N version) / 40 to 85 C (D version), unless otherwise specified.) Parameter Condition XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO-F = 20 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO-F = 20 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO-F = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO-F = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO-F = 4 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-16 MSTTRC = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR27 = 1, VCA20 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz No division FMR27 = 1, VCA20 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz No division Program operation on RAM Flash memory off, FMSTP = 1, VCA20 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (peripheral clock off) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off, Topr = 25 C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85 C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Min. Standard Typ. Max. 3.5 10 Unit mA Power supply current High-speed clock mode (VCC = 2.7 to 3.3 V) Single-chip mode, output pins are open, other pins are VSS High-speed on-chip oscillator mode 1.5 7.5 mA 7.0 15 mA 3.0 mA 4.0 mA 1.5 mA 1 mA Low-speed on-chip oscillator mode Low-speed clock mode 90 390 A 80 400 A 40 A Wait mode 15 90 A 4 80 A 3.5 A Stop mode 2.0 5.0 A 5.0 A REJ03B0289-0100 Rev.1.00 Page 34 of 41 Feb 26, 2010 R8C/3GD Group 5. Electrical Characteristics Timing Requirements (Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25 C) Table 5.21 Symbol tc(XOUT) tWH(XOUT) tWL(XOUT) tc(XCIN) tWH(XCIN) tWL(XCIN) XOUT input cycle time XOUT input “H” width XOUT input “L” width XCIN input cycle time XCIN input “H” width XCIN input “L” width External clock input (XOUT, XCIN) Parameter Standard Min. 50 24 24 14 7 7 Max. Unit ns ns ns s s s tC(XOUT), tC(XCIN) tWH(XOUT), tWH(XCIN) VCC = 3 V External Clock Input tWL(XOUT), tWL(XCIN) Figure 5.8 External Clock Input Timing Diagram when VCC = 3 V Table 5.22 Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO) TRAIO Input Parameter TRAIO input cycle time TRAIO input “H” width TRAIO input “L” width Standard Min. 300 120 120 Max. Unit ns ns ns tC(TRAIO) tWH(TRAIO) VCC = 3 V TRAIO input tWL(TRAIO) Figure 5.9 TRAIO Input Timing Diagram when VCC = 3 V REJ03B0289-0100 Rev.1.00 Page 35 of 41 Feb 26, 2010 R8C/3GD Group 5. Electrical Characteristics Table 5.23 Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0, 2 Serial Interface Parameter CLKi input cycle time CLKi input “H” width CLKi Input “L” width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time 0 70 90 Standard Min. 300 150 150 80 Max. Unit ns ns ns ns ns ns ns tC(CK) tW(CKH) VCC = 3 V CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0, 2 Figure 5.10 Serial Interface Timing Diagram when VCC = 3 V Table 5.24 Symbol tW(INH) tW(INL) External Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 3) Parameter INTi input “H” width, KIi input “H” width INTi input “L” width, KIi input “L” width Standard Min. 380 (1) 380 (2) Max. Unit ns ns Notes: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. INTi input (i = 0, 1, 3) KIi input (i = 0 to 3) VCC = 3 V tW(INL) tW(INH) Figure 5.11 Input Timing for External Interrupt INTi and Key Input Interrupt KIi when Vcc = 3 V REJ03B0289-0100 Rev.1.00 Page 36 of 41 Feb 26, 2010 R8C/3GD Group 5. Electrical Characteristics Table 5.25 Symbol VOH Electrical Characteristics (5) [1.8 V Parameter Vcc < 2.7 V] Condition Standard Min. VCC VCC 1. 0 0.5 0.5 Typ. Max. VCC VCC VCC 0.5 0.5 0.5 0.05 0.2 Unit V V V V V V V Output “H” voltage Other than XOUT XOUT Drive capacity High IOH = 2 mA Drive capacity Low IOH = 1 mA IOH = 200 A Drive capacity High IOL = 2 mA Drive capacity Low IOL = 1 mA IOL = 200 A VOL Output “L” voltage Other than XOUT XOUT VT+-VT- Hysteresis INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, TRBO, TRCIOA, TRCIOB, TRCIOC, TRCIOD, TRCTRG, TRCCLK, ADTRG, RXD0, RXD2, CLK0, CLK2 RESET VI = 2.2 V, VCC = 2.2 V VI = 0 V, VCC = 2.2 V VI = 0 V, VCC = 2.2 V XIN XCIN During stop mode 0.05 0.20 4.0 4.0 V A A k M M V IIH IIL RfXIN RfXCIN VRAM Input “H” current Input “L” current Feedback resistance Feedback resistance RAM hold voltage RPULLUP Pull-up resistance 70 140 0.3 8 300 1.8 Note: 1. 1.8 V VCC < 2.7 V at Topr = 20 to 85 C (N version) / 40 to 85 C (D version), f(XIN) = 5 MHz, unless otherwise specified. REJ03B0289-0100 Rev.1.00 Page 37 of 41 Feb 26, 2010 R8C/3GD Group 5. Electrical Characteristics Table 5.26 Electrical Characteristics (6) [1.8 V Vcc < 2.7 V] (Topr = 20 to 85 C (N version) / 40 to 85 C (D version), unless otherwise specified.) Parameter Condition XIN = 5 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 5 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO-F = 5 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO-F = 5 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO-F = 4 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-16 MSTTRC = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR27 = 1, VCA20 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz No division FMR27 = 1, VCA20 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz No division Program operation on RAM Flash memory off, FMSTP = 1, VCA20 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (peripheral clock off) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off, Topr = 25 C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85 C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Min. Standard Typ. Max. 2.2 Unit mA Symbol ICC Power supply current High-speed clock mode (VCC = 1.8 to 2.7 V) Single-chip mode, output pins are open, other pins are VSS 0.8 mA High-speed on-chip oscillator mode 2.5 10 mA 1.7 mA 1 mA Low-speed on-chip oscillator mode Low-speed clock mode 90 300 A 80 350 A 40 A Wait mode 15 90 A 4 80 A 3.5 A Stop mode 2.0 5 A 5.0 A REJ03B0289-0100 Rev.1.00 Page 38 of 41 Feb 26, 2010 R8C/3GD Group 5. Electrical Characteristics Timing Requirements (Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25 C) Table 5.27 Symbol tc(XOUT) tWH(XOUT) tWL(XOUT) tc(XCIN) tWH(XCIN) tWL(XCIN) XOUT input cycle time XOUT input “H” width XOUT input “L” width XCIN input cycle time XCIN input “H” width XCIN input “L” width External clock input (XOUT, XCIN) Parameter Standard Min. 200 90 90 14 7 7 Max. Unit ns ns ns s s s tC(XOUT), tC(XCIN) tWH(XOUT), tWH(XCIN) VCC = 2.2 V External Clock Input tWL(XOUT), tWL(XCIN) Figure 5.12 External Clock Input Timing Diagram when VCC = 2.2 V Table 5.28 Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO) TRAIO Input Parameter TRAIO input cycle time TRAIO input “H” width TRAIO input “L” width Standard Min. 500 200 200 Max. Unit ns ns ns tC(TRAIO) tWH(TRAIO) VCC = 2.2 V TRAIO input tWL(TRAIO) Figure 5.13 TRAIO Input Timing Diagram when VCC = 2.2 V REJ03B0289-0100 Rev.1.00 Page 39 of 41 Feb 26, 2010 R8C/3GD Group 5. Electrical Characteristics Table 5.29 Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0, 2 Serial Interface Parameter CLKi input cycle time CLKi input “H” width CLKi input “L” width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time 0 150 90 Standard Min. 800 400 400 200 Max. Unit ns ns ns ns ns ns ns tC(CK) tW(CKH) VCC = 2.2 V CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0, 2 Figure 5.14 Serial Interface Timing Diagram when VCC = 2.2 V Table 5.30 Symbol tW(INH) tW(INL) External Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 3) Parameter INTi input “H” width, KIi input “H” width INTi input “L” width, KIi input “L” width Standard Min. 1000 (1) 1000 (2) Max. Unit ns ns Notes: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency × 3) or the minimum value of standard, whichever is greater. INTi input (i = 0, 1, 3) KIi input (i = 0 to 3) VCC = 2.2 V tW(INL) tW(INH) Figure 5.15 Input Timing for External Interrupt INTi and Key Input Interrupt KIi when Vcc = 2.2 V REJ03B0289-0100 Rev.1.00 Page 40 of 41 Feb 26, 2010 R8C/3GD Group Package Dimensions Package Dimensions Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas Technology website. REJ03B0289-0100 Rev.1.00 Page 41 of 41 Feb 26, 2010 REVISION HISTORY Rev. 0.01 1.00 Date Sep. 10, 2009 4 R8C/3GD Group Datasheet Description Page First Edition issued Table 1.3 revised Summary Feb. 26, 2010 All pages “Preliminary”, “Under development” deleted 21 to 40 “5. Electrical Characteristics” added All trademarks and registered trademarks are the property of their respective owners. C-1 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: (1628) 585-100, Fax: (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: (21) 5877-1818, Fax: (21) 6887-7858/7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: 2265-6688, Fax: 2377-3473 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: (2) 2715-2888, Fax: (2) 3518-3399 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: 6213-0200, Fax: 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: (2) 796-3115, Fax: (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: 7955-9390, Fax: 7955-9510 © 2010. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .7.2