R5F2M120ADSP

Preliminary Datasheet Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group RENESAS MCU R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 1. 1.1 Overview Features The R8C/M11A Group and R8C/M12A Group of single-chip microcontrollers (MCUs) incorporate the R8C CPU core, which provides sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, the CPU core is capable of executing instructions at high speed. In addition, it features a multiplier for high-speed arithmetic processing. Power consumption is low, and additional power control is possible by selecting the operating mode. These MCUs are designed to suppress unnecessary radiation of noise and improve noise tolerance with countermeasure circuits. Integration of many peripheral functions on the same chip, including multifunction timer and serial interface, reduces the number of system components. The R8C/M11A Group and R8C/M12A Group include data flash (1 KB × 2 blocks). 1.1.1 Applications Home appliances, office equipment, audio equipment, consumer products, etc. R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 1 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 1. Overview 1.1.2 Differences between Groups Table 1.1 lists the Specification Comparison between R8C/M11A Group and R8C/M12A Group. The explanations in the chapters which follow apply to the R8C/M12A Group only unless otherwise specified. Table 1.1 Item Interrupts I/O ports Specification Comparison between R8C/M11A Group and R8C/M12A Group Function External interrupt inputs R8C/M11A Group R8C/M12A Group 8 (INT × 4, key input × 4) 20 6 (INT × 3, key input × 3) 14 Non-provided pins: P1_0/AN0/TRCIOD/KI0 P3_3/IVCMP3/TRCCLK/INT3 P3_4/IVREF3/TRCIOC/INT2 P3_5/TRCIOD/KI2/VCOUT3 P4_2/TRBO/TXD0/KI3 P4_5/INT0/ADTRG Number of CMOS I/O ports 11 Non-provided ports: P1_0, P3_3, P3_4, P3_5, P4_2, P4_5 Number of high-current drive 5 ports Non-provided ports: P3_3, P3_4, P3_5 A/D converter Number of A/D channels 5 channels Non-provided port: AN0 Comparator B Number of channels Comparator B1 Number of pins 17 8 6 channels Comparator B1, comparator B3 R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 2 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 1. Overview Table 1.2 lists the R8C/M11A Group Register Settings. These settings correspond to the specification differences between the R8C/M11A Group and R8C/M12A Group. Table 1.2 Related Function INT3 R8C/M11A Group Register Settings Register Name Address INTEN INTF0 ISCR0 ILVLD IRR3 KIEN 00038h 0003Ah 0003Ch 0004Dh 00053h 0003Eh 00042h 00052h 000A9h 000AFh 000B5h 000C1h 000C8h 000ABh 000B1h 000B7h 000BDh 000C3h 000CCh 000CDh 000ACh 000B2h 000B8h 000C4h 000CEh 000CFh 0009Dh 00180h 00182h Bit INT3EN INT3F0, INT3F1 INT3SA, INT3SB ILVLD0, ILVLD1 IRI3 KI0EN, KI0PL ILVL24, ILVL25 IRCMP3 PD1_0 P1_0 PU1_0 POD1_0 P10SEL0, P10SEL1 PD3_3, PD3_4, PD3_5 P3_3, P3_4, P3_5 PU3_3, PU3_4, PU3_5 DRR3_3, DRR3_4, DRR3_5 POD3_3, POD3_4, POD3_5 P33SEL0, P33SEL1 P34SEL0, P34SEL1, P35SEL0, P35SEL1 PD4_2, PD4_5 P4_2, P4_5 PU4_2, PU4_5 POD4_2, POD4_5 P42SEL0, P42SEL1 P45SEL0, P45SEL1 CH0, ADGSEL0, ADGSEL1 WCB3M0, WCB3OUT All bits Setting Method for Access Reserved bit. Set to 0. Reserved bits. Set to 0. Reserved bits. Set to 0. Reserved bits. Set to 0. Reserved bit. Reserved bits. Set to 0. Reserved bits. Set to 0. Reserved bit. Reserved bit. Set to 0. Reserved bit. Set to 0. Reserved bit. Set to 0. Reserved bit. Set to 0. Reserved bits. Set to 0. Reserved bits. Set to 0. Reserved bits. Set to 0. Reserved bits. Set to 0. Reserved bits. Set to 0. Reserved bits. Set to 0. Reserved bits. Set to 0. Reserved bits. Set to 0. Reserved bits. Set to 0. Reserved bits. Set to 0. Reserved bits. Set to 0. Reserved bits. Set to 0. Reserved bits. Set to 0. Reserved bits. Set to 0. Do not set to 000. Reserved bits. Set to 0. Reserved register. No access is allowed. KI0 Comparator B3 ILVL2 interrupt IRR2 P1_0 PD1 P1 PUR1 POD1 PML1 P3_3, P3_4, PD3 P3_5 P3 PUR3 DRR3 POD3 PML3 PMH3 P4_2, P4_5 AN0 Comparator B PD4 P4 PUR4 POD4 PML4 PMH4 ADINSEL WCMPR WCB3INTR R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 3 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 1. Overview 1.1.3 Specifications Tables 1.3 and 1.4 outline the Specifications. Table 1.3 Item CPU Specifications (1) Function Central processing unit Description R8C CPU core • Number of fundamental instructions: 89 • Minimum instruction execution time: 50 ns (f(XIN) = 20 MHz, VCC = 2.7 V to 5.5 V) 200 ns (f(XIN) = 5 MHz, VCC = 1.8 V to 5.5 V) • Multiplier: 16 bits × 16 bits → 32 bits • Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits • Operating mode: Single-chip mode (address space: 1 Mbyte) See Table 1.5 Product List. • Hardware reset by RESET • Power-on reset • Watchdog timer reset • Software reset • Reset by voltage detection 0 Voltage detection with two check points: Voltage detection 0, voltage detection 1 (detection levels selectable) • 14 bits × 1 (with prescaler) • Reset start function selectable • Count source protection function selectable • 3 circuits: XIN clock oscillation circuit, high-speed on-chip oscillator (with frequency adjustment function), low-speed on-chip oscillator • Oscillation stop detection: XIN clock oscillation stop detection function • Clock frequency divider circuit integrated • Standard operating mode • Wait mode (CPU stopped, peripheral functions in operation) • Stop mode (CPU and peripheral functions stopped) • Number of interrupt vectors: 69 • External interrupt inputs: 8 (INT × 4, key input × 4) • Priority levels: 2 • CMOS I/O: 17 (pull-up resistor selectable) • High-current drive ports: 8 16 bits × 1 Timer mode, pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode 8 bits × 1 (with 8-bit prescaler) or 16 bits × 1 (selectable) Timer mode, programmable waveform generation mode (PWM output), programmable one-shot generation mode, programmable wait one-shot generation mode 16 bits × 1 (with 4 capture/compare registers) Timer mode (output compare function, input capture function), PWM mode (3 outputs), PWM2 mode (1 PWM output) Clock synchronous serial I/O. Also used for asynchronous serial I/O. • Resolution: 10 bits × 6 channels • Sample and hold function, sweep mode 2 circuits Memory Reset sources ROM, RAM, data flash Voltage Voltage detection detection circuit Watchdog timer Clock Clock generation circuits Power control Interrupts I/O ports Timer Programmable I/O ports Timer RJ2 Timer RB2 Timer RC Serial UART0 interface A/D converter Comparator B R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 4 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 1. Overview Table 1.4 Item Flash memory Specifications (2) Function Description • Program/erase voltage for program ROM: VCC = 1.8 V to 5.5 V • Program/erase voltage for data flash: VCC = 1.8 V to 5.5 V • Program/erase endurance:10,000 times (data flash) 10,000 times (program ROM) • Program security: ID code check, protection enabled by lock bit • Debug functions: On-chip debug, on-board flash rewrite function f(XIN) = 20 MHz (VCC = 2.7 V to 5.5 V) f(XIN) = 5 MHz (VCC = 1.8 V to 5.5 V) -20 °C to 85 °C (N version) -40 °C to 85 °C (D version) (1) 14-pin TSSOP: [Package code] PTSP0014JA-B 14-pin DIP: [Package code] PRDP0014AC-A 20-pin LSSOP: [Package code] PLSP0020JB-A 20-pin DIP: [Package code] PRDP0020AD-A Operating frequency/ Power supply voltage Temperature range Package Note: 1. Specify the D version if its functions are to be used. R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 5 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 1. Overview 1.2 Product List Table 1.5 lists the Product List. Figure 1.1 shows the Product Part Number Structure. Table 1.5 Group Name R8C/M11A Group Product List Part No. Internal ROM Capacity Program ROM Data Flash 2 Kbytes 1 Kbyte × 2 4 Kbytes 1 Kbyte × 2 8 Kbytes 1 Kbyte × 2 2 Kbytes 1 Kbyte × 2 4 Kbytes 1 Kbyte × 2 8 Kbytes 1 Kbyte × 2 2 Kbytes 1 Kbyte × 2 4 Kbytes 1 Kbyte × 2 8 Kbytes 1 Kbyte × 2 2 Kbytes 1 Kbyte × 2 4 Kbytes 1 Kbyte × 2 8 Kbytes 1 Kbyte × 2 2 Kbytes 1 Kbyte × 2 4 Kbytes 1 Kbyte × 2 8 Kbytes 1 Kbyte × 2 2 Kbytes 1 Kbyte × 2 4 Kbytes 1 Kbyte × 2 8 Kbytes 1 Kbyte × 2 Internal RAM Capacity 256 bytes 384 bytes 512 bytes 256 bytes 384 bytes 512 bytes 256 bytes 384 bytes 512 bytes 256 bytes 384 bytes 512 bytes 256 bytes 384 bytes 512 bytes 256 bytes 384 bytes 512 bytes Current of Aug 2010 Package Type PTSP0014JA-B Remarks N version R5F2M110ANSP (D) R5F2M111ANSP (D) R5F2M112ANSP (D) R5F2M110ANDD (D) R5F2M111ANDD (D) R5F2M112ANDD (D) R5F2M110ADSP (D) R5F2M111ADSP (D) R5F2M112ADSP (D) R8C/M12A R5F2M120ANSP (D) Group R5F2M121ANSP (D) R5F2M122ANSP (D) R5F2M120ANDD (D) R5F2M121ANDD (D) R5F2M122ANDD (D) R5F2M120ADSP (D) R5F2M121ADSP (D) R5F2M122ADSP (D) (D): Under development PRDP0014AC-A PTSP0014JA-B D version PLSP0020JB-A N version PRDP0020AD-A PLSP0020JB-A D version Part No. R 5 F 2MX X X A N SP Package type: SP: PTSP0014JA-B, PLSP0020JB-A DD: PRDP0014AC-A, PRDP0020AD-A Classification N: Operating ambient temperature -20 °C to 85 °C D: Operating ambient temperature -40 °C to 85 °C ROM capacity 0: 2 KB 1: 4 KB 2: 8 KB Number of pins 1: 14 pins 2: 20 pins R8C/MXXA Group R8C/Mx Series Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.1 Product Part Number Structure R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 6 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 1. Overview 1.3 Block Diagram Figure 1.2 shows the Block Diagram. 8 4 4 1 I/O ports Peripheral functions Timers Timer RJ2 (16 bits × 1) Timer RB2 (8 bits × 1 or 16 bits × 1) Timer RC (16 bits × 1) Port P1 Port P3 Port P4 Port PA UART Clock synchronous serial I/O Clock asynchronous serial I/O System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator Comparator B Voltage detection circuit Watchdog timer (14 bits) A/D converter (10 bits × 6 channels) R8C CPU core R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG Memory ROM (1) RAM (2) Multiplier Notes: 1. ROM size varies with the product. 2. RAM size varies with the product. Figure 1.2 Block Diagram R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 7 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 1. Overview 1.4 Pin Assignment Figures 1.3 and 1.4 show Pin Assignment (Top View). Table 1.6 lists the Pin Name Information by Pin Number. P3_7/ADTRG/TRJO/TRCIOD RESET/PA_0 P4_7/XOUT/INT2 VSS/AVSS P4_6/XIN/RXD0/TXD0/INT1/ VCOUT1/TRJIO VCC/AVCC MODE 1 2 3 4 5 6 7 14 13 12 11 10 9 8 P1_1/AN1/TRCIOA/TRCTRG/KI1 P1_2/AN2/TRCIOB/KI2 P1_3/AN3/TRCIOC/KI3/TRBO P1_4/AN4/TXD0/RXD0/INT0/TRCIOB P1_5/RXD0/TRJIO/INT1/VCOUT1 P1_6/IVREF1/CLK0/TRJO/TRCIOB P1_7/AN7/IVCMP1/INT1/TRJIO/TRCCLK R8C/M11A Group PTSP0014JA-B PRDP0014AC-A (Top view) Note: 1. Confirm the pin 1 position on the package by referring to Package Dimensions. Figure 1.3 R8C/M11A Group Pin Assignment (Top View) P4_2/TRBO/TXD0/KI3 P3_7/ADTRG/TRJO/TRCIOD RESET/PA_0 P4_7/XOUT/INT2 VSS/AVSS P4_6/XIN/RXD0/TXD0/INT1/ VCOUT1/TRJIO VCC/AVCC MODE P3_5/TRCIOD/KI2/VCOUT3 P3_4/IVREF3/TRCIOC/INT2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 P1_0/AN0/TRCIOD/KI0 P1_1/AN1/TRCIOA/TRCTRG/KI1 P1_2/AN2/TRCIOB/KI2 P1_3/AN3/TRCIOC/KI3/TRBO P1_4/AN4/TXD0/RXD0/INT0/TRCIOB P1_5/RXD0/TRJIO/INT1/VCOUT1 P1_6/IVREF1/CLK0/TRJO/TRCIOB P1_7/AN7/IVCMP1/INT1/TRJIO/TRCCLK P4_5/INT0/ADTRG P3_3/IVCMP3/TRCCLK/INT3 R8C/M12A Group PLSP0020JB-A PRDP0020AD-A (Top view) 16 15 14 13 12 11 Note: 1. Confirm the pin 1 position on the package by referring to Package Dimensions. Figure 1.4 R8C/M12A Group Pin Assignment (Top View) R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 8 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 1. Overview Table 1.6 Pin Name Information by Pin Number Port P4_2 P3_7 RESET XOUT PA_0 P4_7 INT2 INT1 TRJIO RXD0/TXD0 VCOUT1 I/O Pins for Peripheral Functions A/D Converter, Serial Timer Comparator B, Interface Voltage Detection Circuit TRBO TXD0 TRJO/TRCIOD ADTRG Pin Number R8C/M11A R8C/M12A Control Pin Group Group 1 1 2 3 4 5 6 7 2 3 4 5 6 7 8 9 10 11 12 8 9 10 11 12 13 14 13 14 15 16 17 18 19 20 Interrupt KI3 VSS/AVSS XIN P4_6 VCC/AVCC MODE P3_5 P3_4 P3_3 P4_5 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 KI2 INT2 INT3 INT0 INT1 INT1 INT0 KI3 KI2 KI1 KI0 TRCIOD TRCIOC TRCCLK TRJIO/TRCCLK TRJO/TRCIOB TRJIO TRCIOB TRBO/TRCIOC TRCIOB TRCIOA/TRCTRG TRCIOD CLK0 RXD0 RXD0/TXD0 VCOUT3 IVREF3 IVCMP3 ADTRG AN7/IVCMP1 IVREF1 VCOUT1 AN4 AN3 AN2 AN1 AN0 R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 9 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 1. Overview 1.5 Pin Functions Table 1.7 lists the Pin Functions. Table 1.7 Pin Functions I/O — — I I I O Description Apply 1.8 V through 5.5 V to the VCC pin. Apply 0 V to the VSS pin. Power supply input for the A/D converter. Connect a capacitor between pins AVCC and AVSS. Applying a low level to this pin resets the MCU. Connect this pin to the VCC pin via a resistor. I/O for the XIN clock generation circuit. Connect a ceramic resonator or a crystal oscillator between pins XIN and XOUT. (1) To use an external clock, input it to the XIN pin and leave the XOUT pin open. INT interrupt input. Key input interrupt input. CMOS I/O ports. Each port has an I/O select direction register, enabling switching input and output for each port. For input ports other than PA_0, the presence or absence of a pull-up resistor can be selected by a program. P1_2 to P1_5, P3_3 to P3_5, and P3_7 can be used as LED drive ports. Timer RJ2 I/O. Pulse output. Timer RB2 output. External clock input. External trigger input. Timer RC I/O. Transfer clock I/O. Serial data input. Serial data output. Analog input for the A/D converter. External trigger input for the A/D converter. Analog voltage input for comparator B. Reference voltage input for comparator B. Comparison result output for comparator B. Item Pin Name Power supply input VCC, VSS Analog power supply input Reset input MODE XIN clock input XIN clock output AVCC, AVSS RESET MODE XIN XOUT INT interrupt input Key input interrupt I/O ports INT0 to INT3 KI0 to KI3 P1_0 to P1_7, P3_0 to P3_5, P3_7, P4_2, P4_5 to P4_7, PA_0 I I I/O Timer RJ2 Timer RB2 Timer RC Serial interface A/D converter Comparator B TRJIO TRJO TRBO TRCCLK TRCTRG TRCIOA, TRCIOB, TRCIOC, TRCIOD CLK0 RXD0 TXD0 AN0 to AN4, AN7 ADTRG IVCMP1, IVCMP3 IVREF1, IVREF3 VCOUT1, VCOUT3 I/O O O I I I/O I/O I O I I I I O Note: 1. Contact the oscillator manufacturer for oscillation characteristics. R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 10 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the 13 CPU Registers. The registers, R0, R1, R2, R3, A0, A1, and FB form a single register bank. The CPU has two register banks. b31 b15 b0 R2 R3 R0H (R0 high-order byte) R0L (R1 low-order byte) R1H (R0 high-order byte) R1L (R1 low-order byte) R2 R3 A0 A1 FB Data registers (1) Address registers (1) Frame base register (1) b19 b15 b0 INTBH INTBL Interrupt table register The higher 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL. b19 b0 PC Program counter b15 b0 USP ISP SB b15 b0 User stack pointer Interrupt stack pointer Static base register FLG b15 b8 b7 b0 Flag register IPL U I OBSZDC Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bits Processor interrupt priority level Reserved bit Note: 1. These registers form a single register bank. The CPU has two register banks. Figure 2.1 CPU Registers R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 11 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 2. Central Processing Unit (CPU) 2.1 Data Registers (R0, R1, R2, and R3) R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 through R3. R0 can be split into high-order (R0H) and low-order (R0L) registers to be used separately as 8-bit data registers. The same applies to R1H and R1L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). In the same way as with R0 and R2, R3 and R1 can be used as a 32-bit data register (R3R1). 2.2 Address Registers (A0 and A1) A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also used for transfer, arithmetic, and logic operations. A1 functions in the same manner as A0. A1 can be combined with A0 and used as a 32-bit address register (A1A0). 2.3 Frame Base Register (FB) FB is a 16-bit register used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is a 20-bit register that indicates the start address of a relocatable interrupt vector table. 2.5 Program Counter (PC) PC is a 20-bit register that indicates the address of the next instruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of the FLG register is used to switch between USP and ISP. 2.7 Static Base Register (SB) SB is a 16-bit register used for SB relative addressing. 2.8 Flag Register (FLG) FLG is an 11-bit register that indicates the CPU state. 2.8.1 Carry Flag (C) The C flag retains carry, borrow, or shift-out bits that have been generated in the arithmetic and logic unit. 2.8.2 Debug Flag (D) The D flag is for debugging only. It must only be set to 0. 2.8.3 Zero Flag (Z) The Z flag is set to 1 when an arithmetic operation results in 0. Otherwise it is set to 0. 2.8.4 Sign Flag (S) The S flag is set to 1 when an arithmetic operation results in a negative value. Otherwise it is set to 0. 2.8.5 Register Bank Select Flag (B) Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is 1. 2.8.6 Overflow Flag (O) The O flag is set to 1 when an operation results in an overflow. Otherwise it is set to 0. R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 12 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 2. Central Processing Unit (CPU) 2.8.7 Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupts are disabled when the I flag is 0, and are enabled when the I flag is 1. The I flag is set to 0 when an interrupt request is acknowledged. 2.8.8 Stack Pointer Select Flag (U) ISP is selected when the U flag is 0. USP is selected when the U flag is 1. The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction for a software interrupt numbered from 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is 3 bits wide and assigns eight processor interrupt priority levels from 0 to 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled. If IPL is set to levels from 2 to 7, all maskable interrupt requests are disabled. 2.8.10 Reserved Bit The write value must be 0. The read value is undefined. R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 13 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 3. Address Space 3. 3.1 Address Space Memory Map Figure 3.1 shows the Memory Map. The R8C/M11A Group and R8C/M12A Group have a 1-Mbyte address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated at lower addresses, beginning with address 0FFFFh. For example, an 8-Kbyte internal ROM area is allocated at addresses 0E000h to 0FFFFh. The fixed interrupt vector table is allocated at addresses 0FFDCh to 0FFFFh. The start address of each interrupt routine is stored here. The internal ROM (data flash) is allocated at addresses 03000h to 037FFh. The internal RAM is allocated at higher addresses, beginning with address 00400h. For example, a 512-byte internal RAM area is allocated at addresses 00400h to 005FFh. The internal RAM is used not only for data storage but also as a stack area when a subroutine is called or when an interrupt request is acknowledged. Special function registers (SFRs) are allocated at addresses 00000h to 02FFFh. Peripheral function control registers are allocated here. All unallocated spaces within the SFRs are reserved and cannot be accessed by users. 00000h 002FFh 00400h SFR (See 3.2 Special Function Registers (SFRs)) Internal RAM 0XXXXh 0FFD8h Reserved area 0FFDCh 03000h Undefined instruction Overflow BRK instruction Address match Single-step Watchdog timer, oscillation stop detection, voltage monitor 1 Internal ROM (data flash) (1) 037FFh 0YYYYh Internal ROM (program ROM) 0FFFFh 0FFFFh (Reserved) (Reserved) Reset Expanded area FFFFFh Notes: 1. Data flash indicates block A (1 Kbyte) and block B (1 Kbyte). 2. The blank areas are reserved. No access is allowed. Internal ROM Capacity 2 Kbytes 4 Kbytes 8 Kbytes Address 0YYYYh 0F800h 0F000h 0E000h Internal RAM Capacity 256 bytes 384 bytes 512 bytes Address 0XXXXh 004FFh 0057Fh 005FFh Part Number R5F2M110ANSP, R5F2M110ANDD, R5F2M110ADSP, R5F2M120ANSP, R5F2M120ANDD, R5F2M120ADSP R5F2M111ANSP, R5F2M111ANDD, R5F2M111ADSP, R5F2M121ANSP, R5F2M121ANDD, R5F2M121ADSP R5F2M112ANSP, R5F2M112ANDD, R5F2M112ADSP, R5F2M122ANSP, R5F2M122ANDD, R5F2M122ADSP Figure 3.1 Memory Map R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 14 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 3. Address Space 3.2 Special Function Registers (SFRs) An SFR (special function register) is a control register for a peripheral function. Tables 3.1 to 3.8 list the SFR Information. Table 3.9 lists the ID Code Area and Option Function Select Area. Table 3.1 Address 00000h 00001h 00002h 00003h 00004h 00005h 00006h 00007h 00008h 00009h 0000Ah 0000Bh 0000Ch 0000Dh 0000Eh 0000Fh 00010h 00011h 00012h 00013h 00014h 00015h 00016h 00017h 00018h 00019h 0001Ah 0001Bh 0001Ch 0001Dh 0001Eh 0001Fh 00020h 00021h 00022h 00023h 00024h 00025h 00026h 00027h 00028h 00029h 0002Ah 0002Bh 0002Ch 0002Dh 0002Eh 0002Fh 00030h 00031h 00032h 00033h 00034h SFR Information (1) (1) Register Name Symbol After Reset Processor Mode Register 0 Module Standby Control Register Protect Register PM0 MSTCR PRCR 00h 00h (2) 01110111b (3) 00h Hardware Reset Protect Register HRPR 00h External Clock Control Register On-Chip Oscillator Control Register System Clock f Control Register System Clock f Select Register Clock Stop Control Register Clock Control Register When Returning Oscillation Stop Detection Register EXCKCR OCOCR SCKCR PHISEL CKSTPR CKRSCR BAKCR 00h 00h 00h 00h 00h 00h 00h Reset Interrupt Select Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register Count Source Protection Mode Register RISR WDTR WDTS WDTC CSPR WDTIR Watchdog Timer Interrupt Control Register 00035h 00036h 00037h External Input Enable Register 00038h 00039h Notes: 1. The blank areas are reserved. No access is allowed. 2. The MSTINI bit in the OFS2 register is 0. 3. The MSTINI bit in the OFS2 register is 1. 4. The CSPROINI bit in the OFS register is 0. 5. The CSPROINI bit in the OFS register is 1. 10000000b (4) 00h (5) FFh FFh 01000000b 10000000b (4) 00h (5) 00h INTEN 00h R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 15 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 3. Address Space Table 3.2 Address 0003Ah 0003Bh 0003Ch 0003Dh 0003Eh 0003Fh 00040h 00041h 00042h 00043h 00044h 00045h 00046h 00047h 00048h 00049h 0004Ah 0004Bh 0004Ch 0004Dh 0004Eh 0004Fh 00050h 00051h 00052h 00053h 00054h 00055h 00056h 00057h 00058h 00059h 0005Ah 0005Bh 0005Ch SFR Information (2) (1) Register Name INT Input Filter Select Register 0 INT Input Edge Select Register 0 Key Input Enable Register Interrupt Priority Level Register 0 Interrupt Priority Level Register 2 Interrupt Priority Level Register 3 Interrupt Priority Level Register 4 Interrupt Priority Level Register 5 Interrupt Priority Level Register 6 Interrupt Priority Level Register 7 Interrupt Priority Level Register 8 Interrupt Priority Level Register 9 Interrupt Priority Level Register A Interrupt Priority Level Register B Interrupt Priority Level Register C Interrupt Priority Level Register D Interrupt Priority Level Register E Interrupt Monitor Flag Register 0 Interrupt Monitor Flag Register 1 Interrupt Monitor Flag Register 2 External Interrupt Flag Register INTF0 ISCR0 KIEN ILVL0 ILVL2 ILVL3 ILVL4 ILVL5 ILVL6 ILVL7 ILVL8 ILVL9 ILVLA ILVLB ILVLC ILVLD ILVLE IRR0 IRR1 IRR2 IRR3 Symbol 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h After Reset Voltage Monitor Circuit Edge Select Register Voltage Detect Register 2 Voltage Detection 1 Level Select Register Voltage Monitor 0 Circuit Control Register VCAC VCA2 VD1LS VW0C VW1C RSTFR 00h 00100100b (2) 00000100b (3) 00000111b 1100X011b (2) 1100X010b (3) 10001010b 0000XXXXb (4) Voltage Monitor 1 Circuit Control Register 0005Dh 0005Eh Reset Source Determination Register 0005Fh 00060h 00061h 00062h 00063h High-Speed On-Chip Oscillator 18.432 MHz Control Register 0 00064h High-Speed On-Chip Oscillator 18.432 MHz Control Register 1 00065h 00066h High-Speed On-Chip Oscillator Control Register 1 00067h High-Speed On-Chip Oscillator Control Register 2 00068h 00069h 0006Ah 0006Bh 0006Ch 0006Dh 0006Eh 0006Fh 00070h 00071h 00072h 00073h 00074h 00075h 00076h 00077h 00078h 00079h X: Undefined Notes: 1. The blank areas are reserved. No access is allowed. 2. The LVDAS bit in the OFS register is 0. 3. The LVDAS bit in the OFS register is 1. 4. The value after a reset differs depending on the reset source. FR18S0 FR18S1 FRV1 FRV2 Value when shipped Value when shipped Value when shipped Value when shipped R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 16 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 3. Address Space Table 3.3 SFR Information (3) (1) Symbol After Reset Address Register Name 0007Ah 0007Bh 0007Ch 0007Dh 0007Eh 0007Fh UART0 Transmit/Receive Mode Register 00080h UART0 Bit Rate Register 00081h UART0 Transmit Buffer Register 00082h 00083h UART0 Transmit/Receive Control Register 0 00084h UART0 Transmit/Receive Control Register 1 00085h UART0 Receive Buffer Register 00086h 00087h UART0 Interrupt Flag and Enable Register 00088h 00089h 0008Ah 0008Bh 0008Ch 0008Dh 0008Eh 0008Fh 00090h 00091h 00092h 00093h 00094h 00095h 00096h 00097h A/D Register 0 00098h 00099h A/D Register 1 0009Ah 0009Bh A/D Mode Register 0009Ch A/D Input Select Register 0009Dh A/D Control Register 0 0009Eh A/D Interrupt Control Status Register 0009Fh 000A0h 000A1h 000A2h 000A3h 000A4h 000A5h 000A6h 000A7h 000A8h Port P1 Direction Register 000A9h 000AAh Port P3 Direction Register 000ABh Port P4 Direction Register 000ACh Port PA Direction Register 000ADh 000AEh Port P1 Register 000AFh 000B0h Port P3 Register 000B1h Port P4 Register 000B2h Port PA Register 000B3h 000B4h Pull-Up Control Register 1 000B5h 000B6h Pull-Up Control Register 3 000B7h Pull-Up Control Register 4 000B8h Port I/O Function Control Register 000B9h 000BAh Drive Capacity Control Register 1 000BBh 000BCh Drive Capacity Control Register 3 000BDh 000BEh 000BFh X: Undefined Note: 1. The blank areas are reserved. No access is allowed. U0MR U0BRG U0TBL U0TBH U0C0 U0C1 U0RBL U0RBH U0IR 00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h AD0L AD0H AD1L AD1H ADMOD ADINSEL ADCON0 ADICSR XXh 000000XXb XXh 000000XXb 00h 00h 00h 00h PD1 PD3 PD4 PDA P1 P3 P4 PA PUR1 PUR3 PUR4 PINSR DRR1 DRR3 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 17 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 3. Address Space Table 3.4 Address 000C0h 000C1h 000C2h 000C3h 000C4h 000C5h 000C6h 000C7h 000C8h 000C9h 000CAh 000CBh 000CCh 000CDh 000CEh 000CFh 000D0h 000D1h 000D2h 000D3h 000D4h 000D5h 000D6h 000D7h 000D8h 000D9h 000DAh 000DBh 000DCh 000DDh 000DEh 000DFh 000E0h 000E1h 000E2h 000E3h 000E4h 000E5h 000E6h SFR Information (4) (1) Register Name Open-Drain Control Register 1 Open-Drain Control Register 3 Open-Drain Control Register 4 Port PA Mode Control Register POD1 POD3 POD4 PAMCR Symbol 00h 00h 00h 00010001b After Reset Port 1 Function Mapping Register 0 Port 1 Function Mapping Register 1 PML1 PMH1 00h 00h Port 3 Function Mapping Register 0 Port 3 Function Mapping Register 1 Port 4 Function Mapping Register 0 Port 4 Function Mapping Register 1 Port 1 Function Mapping Expansion Register PML3 PMH3 PML4 PMH4 PMH1E 00h 00h 00h 00h 00h Port 4 Function Mapping Expansion Register PMH4E 00h Timer RJ Counter Register Timer RJ Control Register Timer RJ I/O Control Register Timer RJ Mode Register Timer RJ Event Select Register Timer RJ Interrupt Request and Status Register Timer RB Control Register Timer RB One-Shot Control Register Timer RB I/O Control Register Timer RB Mode Register Timer RB Prescaler Register (2) Timer RB Primary/Secondary Register (Lower 8 Bits) (3) Timer RB Primary Register (2) Timer RB Primary Register (Higher 8 Bits) (3) Timer RB Secondary Register (2) Timer RB Secondary Register (Higher 8 Bits) (3) Timer RB Interrupt Request and Status Register Timer RC Counter TRJ TRJCR TRJIOC TRJMR TRJISR TRJIR TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBPR TRBSC TRBIR TRCCNT TRCGRA TRCGRB TRCGRC TRCGRD TRCMR TRCCR1 TRCIER TRCSR TRCIOR0 TRCIOR1 TRCCR2 TRCDF TRCOER TRCADCR TRCOPR FFh FFh 00h 00h 00h 00h 00h 00h 00h 00h 00h FFh FFh FFh 00h 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 01001000b 00h 01110000b 01110000b 10001000b 10001000b 00011000b 00h 01111111b 11110000b 00h 000E7h 000E8h 000E9h Timer RC General Register A 000EAh 000EBh Timer RC General Register B 000ECh 000EDh Timer RC General Register C 000EEh 000EFh Timer RC General Register D 000F0h 000F1h Timer RC Mode Register 000F2h Timer RC Control Register 1 000F3h Timer RC Interrupt Enable Register 000F4h Timer RC Status Register 000F5h Timer RC I/O Control Register 0 000F6h Timer RC I/O Control Register 1 000F7h Timer RC Control Register 2 000F8h Timer RC Digital Filter Function Select Register 000F9h Timer RC Output Enable Register 000FAh Timer RC A/D Conversion Trigger Control Register 000FBh Timer RC Waveform Output Manipulation Register 000FCh 000FDh 000FEh 000FFh Notes: 1. The blank areas are reserved. No access is allowed. 2. The TCNT16 bit in the TRBMR register is 0. 3. The TCNT16 bit in the TRBMR register is 1. R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 18 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 3. Address Space Table 3.5 SFR Information (5) (1) Symbol After Reset Address Register Name 00100h 00101h 00102h 00103h 00104h 00105h 00106h 00107h 00108h 00109h 0010Ah 0010Bh 0010Ch 0010Dh 0010Eh 0010Fh 00110h 00111h 00112h 00113h 00114h 00115h 00116h 00117h 00118h 00119h 0011Ah 0011Bh 0011Ch 0011Dh 0011Eh 0011Fh 00120h 00121h 00122h 00123h 00124h 00125h 00126h 00127h 00128h 00129h 0012Ah 0012Bh 0012Ch 0012Dh 0012Eh 0012Fh 00130h 00131h 00132h 00133h 00134h 00135h 00136h 00137h 00138h 00139h 0013Ah 0013Bh 0013Ch 0013Dh 0013Eh 0013Fh Note: 1. The blank areas are reserved. No access is allowed. R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 19 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 3. Address Space Table 3.6 SFR Information (6) (1) Symbol After Reset Address Register Name 00140h 00141h 00142h 00143h 00144h 00145h 00146h 00147h 00148h 00149h 0014Ah 0014Bh 0014Ch 0014Dh 0014Eh 0014Fh 00150h 00151h 00152h 00153h 00154h 00155h 00156h 00157h 00158h 00159h 0015Ah 0015Bh 0015Ch 0015Dh 0015Eh 0015Fh 00160h 00161h 00162h 00163h 00164h 00165h 00166h 00167h 00168h 00169h 0016Ah 0016Bh 0016Ch 0016Dh 0016Eh 0016Fh 00170h 00171h 00172h 00173h 00174h 00175h 00176h 00177h 00178h 00179h 0017Ah 0017Bh 0017Ch 0017Dh 0017Eh 0017Fh Note: 1. The blank areas are reserved. No access is allowed. R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 20 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 3. Address Space Table 3.7 SFR Information (7) (1) Symbol WCMPR WCB1INTR WCB3INTR After Reset 00h 00h 00h Address Register Name Comparator B Control Register 00180h Comparator B1 Interrupt Control Register 00181h Comparator B3 Interrupt Control Register 00182h 00183h 00184h 00185h 00186h 00187h 00188h 00189h 0018Ah 0018Bh 0018Ch 0018Dh 0018Eh 0018Fh 00190h 00191h 00192h 00193h 00194h 00195h 00196h 00197h 00198h 00199h 0019Ah 0019Bh 0019Ch 0019Dh 0019Eh 0019Fh 001A0h 001A1h 001A2h 001A3h 001A4h 001A5h 001A6h 001A7h 001A8h Flash Memory Status Register 001A9h Flash Memory Control Register 0 001AAh Flash Memory Control Register 1 001ABh Flash Memory Control Register 2 001ACh Flash Memory Refresh Control Register 001ADh 001AEh 001AFh 001B0h 001B1h 001B2h 001B3h 001B4h 001B5h 001B6h 001B7h 001B8h 001B9h 001BAh 001BBh 001BCh 001BDh 001BEh 001BFh Note: 1. The blank areas are reserved. No access is allowed. FST FMR0 FMR1 FMR2 FREFR 10000000b 00h 00h 00h 00h R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 21 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 3. Address Space Table 3.8 SFR Information (8) (1) Symbol AIADR0L AIADR0M AIADR0H AIEN0 AIADR1L AIADR1M AIADR1H AIEN1 After Reset 00h 00h 00h 00h 00h 00h 00h 00h Address Register Name Address Match Interrupt Register 0 001C0h 001C1h 001C2h Address Match Interrupt Enable Register 0 001C3h Address Match Interrupt Register 1 001C4h 001C5h 001C6h Address Match Interrupt Enable Register 1 001C7h 001C8h 001C9h 001CAh 001CBh 001CCh 001CDh 001CEh 001CFh 001D0h 001D1h 001D2h 001D3h 001D4h 001D5h 001D6h 001D7h 001D8h 001D9h 001DAh 001DBh 001DCh 001DDh 001DEh 001DFh 001E0h 001E1h 001E2h 001E3h 001E4h 001E5h 001E6h 001E7h 001E8h 001E9h 001EAh 001EBh 001ECh 001EDh 001EEh 001EFh 001F0h 001F1h 001F2h 001F3h 001F4h 001F5h 001F6h 001F7h 001F8h 001F9h 001FAh 001FBh 001FCh 001FDh 001FEh 001FFh Note: 1. The blank areas are reserved. No access is allowed. R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 22 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 3. Address Space Table 3.9 ID Code Area and Option Function Select Area Address Area Name Symbol After Reset : Option Function Select Register 2 OFS2 (Note 1) 0FFDBh : ID1 (Note 2) 0FFDFh : ID2 (Note 2) 0FFE3h : ID3 (Note 2) 0FFEBh : ID4 (Note 2) 0FFEFh : ID5 (Note 2) 0FFF3h : ID6 (Note 2) 0FFF7h : ID7 (Note 2) 0FFFBh : Option Function Select Register OFS (Note 1) 0FFFFh Notes: 1. The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program. Do not perform an additional write to the option function select area. Erasure of the block including the option function select area causes the option function select area to be set to FFh. 2. The ID code area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program. Do not perform an additional write to the ID code area. Erasure of the block including the ID code area causes the ID code area to be set to FFh. R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 23 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 4. Electrical Characteristics 4. Electrical Characteristics Table 4.1 Symbol VI Input voltage Absolute Maximum Ratings Parameter XIN Condition XIN-XOUT oscillation on (oscillation circuit used) (1) XIN-XOUT oscillation off (oscillation circuit not used) (1) Other pins Rated Value -0.3 to 6.5 -0.3 to 1.9 -0.3 to Vcc + 0.3 -0.3 to Vcc + 0.3 XIN-XOUT oscillation on (oscillation circuit used) (1) XIN-XOUT oscillation off (oscillation circuit not used) (1) Other pins -0.3 to 1.9 -0.3 to Vcc + 0.3 -0.3 to Vcc + 0.3 -40 °C ≤ Topr ≤ 85 °C 500 -20 to 85 (N version)/ -40 to 85 (D version) -60 to 150 Unit V V V V V V V mW °C °C VCC/AVCC Power supply voltage VO Output voltage XOUT Pd Topr Tstg Power consumption Operating ambient temperature Storage temperature Note: 1. When the oscillation circuit is used: bits CKPT1 to CKPT0 in the EXCKCR register are set to 11b When the oscillation circuit is not used: bits CKPT1 to CKPT0 in the EXCKCR register are set to any value other than 11b R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 24 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 4. Electrical Characteristics Table 4.2 Symbol Recommended Operating Conditions Parameter Condition Standard Min. 1.8 — Other than CMOS input CMOS input 4.0 V ≤ Vcc ≤ 5.5 V 2.7 V ≤ Vcc < 4.0 V 1.8 V ≤ Vcc < 2.7 V 0.8 Vcc 0.65 Vcc 0.7 Vcc 0.8 Vcc 0 4.0 V ≤ Vcc ≤ 5.5 V 2.7 V ≤ Vcc < 4.0 V 1.8 V ≤ Vcc < 2.7 V 0 0 0 — — When drive capacity is low When drive capacity is high (5) When drive capacity is low When drive capacity is high (5) Sum of all pins IOL(peak) Sum of all pins IOL(avg) When drive capacity is low When drive capacity is high (5) When drive capacity is low When drive capacity is high (5) Typ. — 0 — — — — — — — — — — — — — — — — — — — — — — — — 20 125 — — — — Max. 5.5 — Vcc Vcc Vcc Vcc 0.2 Vcc 0.4 Vcc 0.3 Vcc 0.2 Vcc -160 -80 -10 -40 -5 -20 160 80 10 40 5 20 20 5 20 5 — — 20 5 20 5 Unit V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA MHz MHz MHz MHz MHz kHz MHz MHz MHz MHz VCC/AVCC Power supply voltage VSS/AVSS VIH Power supply voltage Input high voltage VIL Input low voltage Other than CMOS input CMOS input IOH(sum) IOH(sum) IOH(peak) IOH(avg) IOL(sum) IOL(sum) IOL(peak) IOL(avg) f(XIN) Peak sum output high current Average sum output high current Peak output high current Average output high current Peak sum output low current Average sum output low current Peak output low current Average output low current XIN oscillation frequency Sum of all pins IOH(peak) Sum of all pins IOH(avg) — — — — — — — — — — 2 2 0 0 — — — — 0 0 2.7 V ≤ Vcc ≤ 5.5 V 1.8 V ≤ Vcc < 2.7 V 2.7 V ≤ Vcc ≤ 5.5 V 1.8 V ≤ Vcc < 2.7 V XIN clock input oscillation frequency fHOCO fLOCO — fs High-speed on-chip oscillator oscillation frequency (3) 1.8 V ≤ Vcc ≤ 5.5 V Low-speed on-chip oscillator oscillation frequency (4) 1.8 V ≤ Vcc ≤ 5.5 V System clock frequency CPU clock frequency 2.7 V ≤ Vcc ≤ 5.5 V 1.8 V ≤ Vcc < 2.7 V 2.7 V ≤ Vcc ≤ 5.5 V 1.8 V ≤ Vcc < 2.7 V Notes: 1. Vcc = 1.8 V to 5.5 V and Topr = -20 °C to 85 °C (N version)/-40 °C to 85 °C (D version), unless otherwise specified. 2. The average output current indicates the average value of current measured during 100 ms. 3. For details, see Table 4.10 High-Speed On-Chip Oscillator Circuit Electrical Characteristics. 4. For details, see Table 4.11 Low-Speed On-Chip Oscillator Circuit Electrical Characteristics. 5. The pins with high drive capacity are P1_2, P1_3, P1_4, P1_5, P3_3, P3_4, P3_5, and P3_7. P1 P3 P4 30 pF Figure 4.1 Ports P1, P3, and P4 Timing Measurement Circuit Page 25 of 45 R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 4. Electrical Characteristics Table 4.3 Symbol — — A/D Converter Characteristics Parameter Resolution Absolute accuracy AVcc = 5.0 V AVcc = 3.0 V AVcc = 1.8 V AN0 to AN4, AN7 input AN0 to AN4, AN7 input AN0 to AN4, AN7 input Condition Standard Min. — — — — 2 2 2 2 Typ. — — — — — — — — 3 AVcc = 5.0 V, φAD = 20 MHz φAD = 20 MHz 2.15 0.75 0 — — — — — AVcc Max. 10 ±3 ±5 ±5 20 16 10 5 Unit Bit LSB LSB LSB MHz MHz MHz MHz kΩ µs µs V φAD A/D conversion clock 4.0 V ≤ AVcc ≤ 5.5 V (2) 3.2 V ≤ AVcc ≤ 5.5 V (2) 2.7 V ≤ AVcc ≤ 5.5 V (2) 1.8 V ≤ AVcc ≤ 5.5 V (2) — tCONV tSAMP VIA Permissible signal source impedance Conversion time Sampling time Analog input voltage Notes: 1. Vcc/AVcc = 1.8 V to 5.5 V and Vss = 0 V and Topr = -20 °C to 85 °C (N version)/-40 °C to 85 °C (D version), unless otherwise specified. 2. The A/D conversion result will be undefined in stop mode, or when the flash memory is in low-current-consumption read mode or stopped. Do not perform A/D conversion in these states. Do not enter these states during A/D conversion. Table 4.4 Symbol Vref VI — td ICMP Comparator B Electrical Characteristics Parameter IVREF1, IVREF3 input reference voltage IVCMP1, IVCMP3 input voltage Offset Comparator output delay time (2) Comparator operating current VI = Vref ± 100 mV Vcc = 5.0 V Condition Standard Min. 0 -0.3 — — — Typ. — — 5 0.1 17.5 Max. Vcc - 1.4 Vcc + 0.3 100 — — Unit V V mV µs µA Notes: 1. Vcc = 2.7 V to 5.5 V and Topr = -20 °C to 85 °C (N version)/-40 °C to 85 °C (D version), unless otherwise specified. 2. When the digital filter is disabled. R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 26 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 4. Electrical Characteristics Table 4.5 Symbol — — Flash Memory (Program ROM) Electrical Characteristics Parameter Program/erase endurance (2) Byte programming time (program/erase endurance ≤ 1,000 times) Byte programming time (program/erase endurance > 1,000 times) Block erase time Transition time to suspend Time from suspend until erase restart Time from when command is forcibly terminated until reading is enabled Program/erase voltage Read voltage Program/erase temperature Data hold time (7) Condition Standard Min. 10,000 (3) — Typ. — 80 Max. — — Unit times µs — — 160 — µs — td(SR-SUS) — td(CMDRST READY) — — — — 1.8 1.8 0 Ambient temperature = 85 °C 10 0.12 — — — — — — — — 0.25 + CPU clock × 3 cycles 30 + CPU clock × 1 cycle 30 + CPU clock × 1 cycle 5.5 5.5 60 — s ms µs µs V V °C years — — — — Notes: 1. Vcc = 2.7 V to 5.5 V and Topr = 0 °C to 60 °C, unless otherwise specified. 2. Definition of program/erase endurance The number of program/erase cycles is defined on a per-block basis. If the number of cycles is 10,000, each block can be erased 10,000 times. For example, if 1,024 cycles of 1-byte-write are performed to different addresses in 1 Kbyte of block A, and then the block is erased, the number of cycles is counted as one. Note, however, that the same address must not be programmed more than once before completion of an erase (overwriting prohibited). 3. This indicates the number of times up to which all electrical characteristics can be guaranteed after the last programming/ erase operation. Operation is guaranteed for any number of operations in the range of 1 to the specified minimum (Min). 4. In a system that executes multiple programming operations, the actual erase count can be reduced by shifting the write addresses in sequence and programming so that as much of the flash memory as possible is used before performing an erase operation. For example, when programming in 16-byte units, the effective number of rewrites can be minimized by programming up to 128 units before erasing them all in one operation. It is also advisable to retain data on the number of erase operations for each block and establish a limit for the number of erase operations performed. 5. If an error occurs during a block erase, execute a clear status register command and then a block erase command at least three times until the erase error does not occur. 6. For information on the program/erase failure rate, contact a Renesas technical support representative. 7. The data hold time includes the time that the power supply is off and the time the clock is not supplied. R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 27 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 4. Electrical Characteristics Table 4.6 Symbol — — — td(SR-SUS) — Flash Memory (Blocks A and B of Data Flash) Electrical Characteristics Parameter Program/erase endurance (2) Byte programming time Block erase time Time delay from suspend request until suspend Time from suspend until erase restart Condition Standard Min. 10,000 (3) — — — — — 1.8 1.8 -20 (N version) -40 (D version) Typ. — 150 0.05 — — — — — — — — Max. — — 1 0.25 + CPU clock × 3 cycles 30 + CPU clock × 1 cycle 30 + CPU clock × 1 cycle 5.5 5.5 85 85 — Unit times µs s ms µs µs V V °C °C years td(CMDRST- Time from when command is forcibly READY) stopped until reading is enabled — — — Program/erase voltage Read voltage Program/erase temperature — Data hold time (7) Ambient temperature = 85 °C 10 Notes: 1. Vcc = 2.7 V to 5.5 V and Topr = -20 °C to 85 °C (N version)/-40 °C to 85 °C (D version), unless otherwise specified. 2. Definition of program/erase endurance The number of program/erase cycles is defined on a per-block basis. If the number of cycles is 10,000, each block can be erased 10,000 times. For example, if 1,024 cycles of 1-byte-write are performed to different addresses in 1 Kbyte of block A, and then the block is erased, the number of cycles is counted as one. Note, however, that the same address must not be programmed more than once before completion of an erase (overwriting prohibited). 3. This indicates the number of times up to which all electrical characteristics can be guaranteed after the last programming/ erase operation. Operation is guaranteed for any number of operations in the range of 1 to the specified minimum (Min). 4. In a system that executes multiple program operations, the actual erase count can be reduced by shifting the write addresses in sequence and programming so that as much of the flash memory as possible is used before performing an erase operation. For example, when programming in 16-byte units, the effective number of rewrites can be minimized by programming up to 128 units before erasing them all in one operation. It is also advisable to retain data on the number of erase operations for each block and establish a limit for the number of erase operations performed. 5. If an error occurs during a block erase, execute a clear status register command and then a block erase command at least three times until the erase error does not occur. 6. For information on the program/erase failure rate, contact a Renesas technical support representative. 7. The data hold time includes the time that the power supply is off and the time the clock is not supplied. Suspend request (FMR21) FST7 FST6 Fixed time Clock-dependent time Access restart td(SR-SUS) FST6, FST7: Bits in FST register FMR21: Bit in FMR2 register Figure 4.2 Transition Time until Suspend R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 28 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 4. Electrical Characteristics Table 4.7 Symbol Vdet0 Voltage Detection 0 Circuit Electrical Characteristics Parameter Voltage detection level Vdet0_0 (2) Voltage detection level Vdet0_1 (2) Voltage detection level Vdet0_2 (2) Voltage detection level Vdet0_3 (2) (3) Condition Standard Min. 1.80 2.15 2.70 3.55 Typ. 1.90 2.35 2.85 3.80 30 1.5 — Max. 2.05 2.50 3.05 4.05 — — 100 Unit V V V V µs µA µs — — td(E-A) Voltage detection 0 circuit response time When Vcc decreases from 5 V to (Vdet0_0 - 0.1) V VC0E = 1, Vcc = 5.0 V — — — Self power consumption in voltage detection circuit Wait time until voltage detection circuit operation starts (4) Notes: 1. The measurement condition is Vcc = 1.8 V to 5.5 V and Topr = -20 °C to 85 °C (N version)/-40 °C to 85 °C (D version). 2. Select the voltage detection level with bits VDSEL0 and VDSEL1 in the OFS register. 3. The response time is from when the voltage passes Vdet0 until the voltage monitor 0 reset is generated. 4. The wait time is necessary for the voltage detection circuit to operate when the VC0E bit in the VCA2 register is set to 0 and then 1. Table 4.8 Symbol Vdet1 Voltage Detection 1 Circuit Electrical Characteristics Parameter Voltage detection level Vdet1_1 (2) Voltage detection level Vdet1_3 (2) Voltage detection level Vdet1_5 (2) Voltage detection level Vdet1_7 Voltage detection level Vdet1_9 (2) (2) Condition When Vcc decreases When Vcc decreases When Vcc decreases When Vcc decreases When Vcc decreases When Vcc decreases When Vcc decreases When Vcc decreases Vdet1_1 to Vdet1_5 selected Vdet1_7 to Vdet1_F selected When Vcc decreases from 5 V to (Vdet1_0 - 0.1) V VC1E = 1, Vcc = 5.0 V Standard Min. 2.15 2.45 2.75 3.00 3.30 3.60 3.90 4.20 — — — — — Typ. 2.35 2.65 2.95 3.25 3.55 3.85 4.15 4.45 0.07 0.10 60 1.7 — Max. 2.55 2.85 3.15 3.55 3.85 4.15 4.45 4.75 — — 150 — 100 Unit V V V V V V V V V V µs µA µs Voltage detection level Vdet1_B (2) Voltage detection level Vdet1_D (2) Voltage detection level Vdet1_F — — — td(E-A) (2) Hysteresis width at the rising of Vcc in voltage detection 1 circuit Voltage detection 1 circuit response time (3) Self power consumption in voltage detection circuit Wait time until voltage detection circuit operation starts (4) Notes: 1. The measurement condition is Vcc = 1.8 V to 5.5 V and Topr = -20 °C to 85 °C (N version)/-40 °C to 85 °C (D version). 2. Select the voltage detection level with bits VD1S1 to VD1S3 in the VD1LS register. 3. The response time is from when the voltage passes Vdet1 until the voltage monitor 1 interrupt request is generated. 4. The wait time is necessary for the voltage detection circuit to operate when the VC1E bit in the VCA2 register is set to 0 and then 1. R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 29 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 4. Electrical Characteristics Table 4.9 Symbol trth Power-On Reset Circuit (2) Parameter External power Vcc rise gradient Condition Standard Min. 0 Typ. — Max. 50,000 Unit mV/msec Notes: 1. The measurement condition is Topr = -20 °C to 85 °C (N version)/-40 °C to 85 °C (D version), unless otherwise specified. 2. To use the power-on reset function, enable the voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0. Vdet0 (1) trth trth 0.5 V External power Vcc tw(por) (2) Internal reset signal (low active) 1 × 256 fLOCO Voltage detection 0 circuit response time 1 × 256 fLOCO Notes: 1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. For details, see 7. Voltage Detection Circuit in the User’s Manual: Hardware. 2. tw(por) is required for a power-on reset to be enabled with the external power Vcc held below the valid voltage (0.5 V) to enable a power-on reset. When Vcc decreases with voltage monitor 0 reset disabled and then turns on, maintain tw(por) for 1 ms or more. Figure 4.3 Power-On Reset Circuit Electrical Characteristics R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 30 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 4. Electrical Characteristics Table 4.10 Symbol — High-Speed On-Chip Oscillator Circuit Electrical Characteristics Parameter Condition Standard Min. TBD TBD Typ. 20 18.432 Max. TBD TBD Unit MHz MHz High-speed on-chip oscillator frequency after Vcc = 5.0 V, Topr = 25 °C reset is cleared High-speed on-chip oscillator frequency when the FR18S0 register adjustment value is written into the FRV1 register and the FR18S1 register adjustment value into the FRV2 register (2) High-speed on-chip oscillator frequency dependence on temperature and power supply voltage (3) Vcc = 2.7 V to 5.5 V -20 °C ≤ Topr ≤ 85 °C Vcc = 2.7 V to 5.5 V -40 °C ≤ Topr ≤ 85 °C Vcc = 2.2 V to 5.5 V -20 °C ≤ Topr ≤ 85 °C Vcc = 2.2 V to 5.5 V -40 °C ≤ Topr ≤ 85 °C Vcc = 1.8 V to 5.5 V -20 °C ≤ Topr ≤ 85 °C Vcc = 1.8 V to 5.5 V -40 °C ≤ Topr ≤ 85 °C TBD TBD TBD TBD TBD TBD — — — — — — — — 100 400 TBD TBD TBD TBD TBD TBD 450 — % % % % % % µs µA — — Oscillation stabilization time Self power consumption at oscillation Vcc = 5.0 V, Topr = 25 °C Vcc = 5.0 V, Topr = 25 °C Notes: 1. Vcc = 1.8 V to 5.5 V, Topr = -20 °C to 85 °C (N version)/-40 °C to 85 °C (D version), unless otherwise specified. 2. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0 % when the serial interface is used in UART mode. 3. This indicates the precision error for the oscillation frequency of the high-speed on-chip oscillator. Table 4.11 Symbol fLOCO — — Low-Speed On-Chip Oscillator Circuit Electrical Characteristics Parameter Condition Standard Min. 60 Vcc = 5.0 V, Topr = 25 °C Vcc = 5.0 V, Topr = 25 °C — — Typ. 125 10 2 Max. 250 100 — Unit kHz µs µA Low-speed on-chip oscillator frequency Oscillation stabilization time Self power consumption at oscillation Note: 1. Vcc = 1.8 V to 5.5 V, Topr = -20 °C to 85 °C (N version)/-40 °C to 85 °C (D version), unless otherwise specified. Table 4.12 Symbol td(P-R) Power Supply Circuit Timing Characteristics Parameter Condition Standard Min. — Typ. — Max. 2,000 Unit µs Time for internal power supply stabilization during power-on (2) Notes: 1. The measurement condition is Vcc = 1.8 V to 5.5 V and Topr = 25 °C. 2. Wait time until the internal power supply generation circuit stabilizes during power-on. R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 31 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 4. Electrical Characteristics Table 4.13 Symbol VOH DC Characteristics (1) [4.0 V ≤ Vcc ≤ 5.5 V] Parameter Condition Standard Min. Typ. — — — Max. Vcc Vcc Vcc Unit V V V Output high voltage P1_2, P1_3, P1_4, P1_5, When drive IOH = -20 mA Vcc - 2.0 P3_3, P3_4, P3_5, P3_7 (2) capacity is high When drive IOH = -5 mA Vcc - 2.0 capacity is low P1_0, P1_1, P1_6, P1_7, P4_2, P4_5, P4_6, P4_7, PA_0 IOH = -5 mA Vcc - 2.0 VOL Output low voltage P1_2, P1_3, P1_4, P1_5, When drive IOL = 20 mA P3_3, P3_4, P3_5, P3_7 (2) capacity is high When drive IOL = 5 mA capacity is low P1_0, P1_1, P1_6, P1_7, P4_2, P4_5, P4_6, P4_7, PA_0 IOL = 5 mA — — — — — — 2.0 2.0 2.0 V V V VT+-VT- Hysteresis INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, TRJIO, TRCIOA, TRCIOB, TRCIOC, TRCIOD, RXD0, CLK0 RESET Vcc = 5 V 0.1 1.2 — V Vcc = 5 V VI = 5 V, Vcc = 5.0 V VI = 0 V, Vcc = 5.0 V VI = 0 V, Vcc = 5.0 V In stop mode 0.1 — — 25 — 1.8 1.2 — — 50 2.2 — — 5.0 -5.0 100 — — V µA µA kΩ MΩ V IIH IIL RPULLUP RfXIN VRAM Input high current Input low current Pull-up resistance Feedback resistance XIN RAM hold voltage Notes: 1. 4.0 V ≤ Vcc ≤ 5.5 V and Topr = -20 °C to 85 °C (N version)/-40 °C to 85 °C (D version), f(XIN) = 20 MHz, unless otherwise specified. 2. High drive capacity can also be used while the peripheral output function is used. R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 32 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 4. Electrical Characteristics Table 4.14 DC Characteristics (2) [4.0 V ≤ Vcc ≤ 5.5 V] (Topr = -20 °C to 85 °C (N version)/-40 °C to 85 °C (D version), unless otherwise specified) Condition Oscillation Circuit XIN (2) On-Chip Oscillator HighSpeed Off Off Off Off Off Off 20 MHz 20 MHz 4 MHz (4) Off LowSpeed 125 kHz 125 kHz 125 kHz 125 kHz 125 kHz 125 kHz 125 kHz 125 kHz 125 kHz 125 kHz Low-PowerConsumption Setting — — — — — — Standard Other Min. — — — — — — — — MSTTRC = 1 FMR27 = 1 LPE = 0 — — Typ. (3) 3 2.5 1.7 1.5 1.2 1.0 3.5 2.0 1.0 60 Max. 7.0 6.0 — — — — 7.5 — — 270 mA mA mA mA mA mA mA mA mA µA Symbol Parameter CPU Clock No division No division No division Division by 8 Division by 8 Division by 8 No division Division by 8 Division by 16 Division by 8 Unit ICC Power supply current (1) High-speed clock mode 20 MHz 16 MHz 10 MHz 20 MHz 16 MHz 10 MHz High-speed on-chip oscillator mode Off Off Off Low-speed on-chip oscillator mode Wait mode Off Off Off 125 kHz — VC1E = 0 VC0E = 0 LPE = 1 Peripheral clock supplied during WAIT instruction execution Peripheral clock stopped during WAIT instruction execution Topr = 25 °C Peripheral clock stopped Topr = 85 °C Peripheral clock stopped — 15 100 µA Off Off 125 kHz — VC1E = 0 VC0E = 0 LPE = 1 WCKSTP = 1 VC1E = 0 VC0E = 0 STPM = 1 VC1E = 0 VC0E = 0 STPM = 1 — 4.0 90 µA Stop mode Off Off Off — — 1.0 4.0 µA Off Off Off — — 1.5 — µA Notes: 1. 2. 3. 4. Vcc = 4.0 V to 5.5 V, single-chip mode, output pins are open, and other pins are connected to Vss. When the XIN input is a square wave. Vcc = 5.0 V Set the system clock to 4 MHz with the PHISEL register. R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 33 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 4. Electrical Characteristics Timing Requirements (Vcc = 5 V, Vss = 0 V at Topr = 25 °C, unless otherwise specified) Table 4.15 Symbol tc(XIN) tWH(XIN) tWL(XIN) XIN Input Parameter Standard Min. 50 24 24 Max. — — — Unit ns ns ns XIN input cycle time XIN input high width XIN input low width tC(XIN) tWH(XIN) Vcc = 5 V XIN input tWL(XIN) Figure 4.4 XIN Input Timing When Vcc = 5 V Table 4.16 Symbol tc(TRJIO) tWH(TRJIO) tWL(TRJIO) TRJIO Input Parameter Standard Min. 100 40 40 Max. — — — Unit ns ns ns TRJIO input cycle time TRJIO input high width TRJIO input low width tC(TRJIO) tWH(TRJIO) Vcc = 5 V TRJIO input tWL(TRJIO) Figure 4.5 TRJIO Input Timing When Vcc = 5 V R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 34 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 4. Electrical Characteristics Table 4.17 Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Serial Interface Parameter Standard Min. 200 100 100 — 0 50 90 Max. — — — 50 — — — Unit ns ns ns ns ns ns ns CLK0 input cycle time CLK0 input high width CLK0 input low width TXD0 output delay time TXD0 hold time RXD0 input setup time RXD0 input hold time tC(CK) tW(CKH) Vcc = 5 V CLK0 tW(CKL) th(C-Q) TXD0 td(C-Q) tsu(D-C) th(C-D) RXD0 Figure 4.6 Serial Interface Timing When Vcc = 5 V Table 4.18 Symbol tW(INH) tW(INL) External Interrupt INTi Input, Key Input Interrupt KIi (i = 0 to 3) Parameter Standard Min. 250 (1) 250 (2) Max. — — Unit ns ns INTi input high width, KIi input high width INTi input low width, KIi input low width Notes: 1. When the digital filter is enabled by the INTi input filter select bit, the INTi input high width is (1/digital filter clock frequency × 3) or the minimum value of the standard, whichever is greater. 2. When the digital filter is enabled by the INTi input filter select bit, the INTi input low width is (1/digital filter clock frequency × 3) or the minimum value of the standard, whichever is greater. Vcc = 5 V tW(INL) INTi input KIi input (i = 0 to 3) tW(INH) Figure 4.7 Timing for External Interrupt INTi Input and Key Input Interrupt KIi When Vcc = 5 V R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 35 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 4. Electrical Characteristics Table 4.19 Symbol VOH DC Characteristics (3) [2.7 V ≤ Vcc < 4.0 V] Parameter Condition Standard Min. Vcc - 0.5 Vcc - 0.5 Vcc - 0.5 Typ. — — — Max. Vcc Vcc Vcc Unit V V V Output high voltage P1_2, P1_3, P1_4, P1_5, When drive IOH = -5 mA P3_3, P3_4, P3_5, P3_7 (2) capacity is high When drive IOH = -1 mA capacity is low P1_0, P1_1, P1_6, P1_7, P4_2, P4_5, P4_6, P4_7, PA_0 IOH = -1 mA VOL Output low voltage P1_2, P1_3, P1_4, P1_5, When drive IOL = 5 mA P3_3, P3_4, P3_5, P3_7 (2) capacity is high When drive IOL = 1 mA capacity is low P1_0, P1_1, P1_6, P1_7, P4_2, P4_5, P4_6, P4_7, PA_0 IOL = 1 mA — — — — — — 0.5 0.5 0.5 V V V VT+-VT- Hysteresis INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, TRJIO, TRCIOA, TRCIOB, TRCIOC, TRCIOD, RXD0, CLK0 RESET Vcc = 3 V 0.1 0.4 — V Vcc = 3 V VI = 3 V, Vcc = 3.0 V VI = 0 V, Vcc = 3.0 V VI = 0 V, Vcc = 3.0 V In stop mode 0.1 — — 42 — 1.8 0.5 — — 84 2.2 — — 4.0 -4.0 168 — — V µA µA kΩ MΩ V IIH IIL RPULLUP RfXIN VRAM Input high current Input low current Pull-up resistance Feedback resistance XIN RAM hold voltage Notes: 1. 2.7 V ≤ Vcc < 4.0 V and Topr = -20 °C to 85 °C (N version)/-40 °C to 85 °C (D version), f(XIN) = 10 MHz, unless otherwise specified. 2. High drive capacity can also be used while the peripheral output function is used. R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 36 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 4. Electrical Characteristics Table 4.20 DC Characteristics (4) [2.7 V ≤ Vcc < 4.0 V] (Topr = -20 °C to 85 °C (N version)/-40 °C to 85 °C (D version), unless otherwise specified) Condition Oscillation Circuit XIN (2) On-Chip Oscillator HighSpeed Off Off Off Off Off Off 20 MHz 20 MHz LowSpeed 125 kHz 125 kHz 125 kHz 125 kHz 125 kHz 125 kHz 125 kHz 125 kHz Low-PowerConsumption Setting — — — — — — Standard Other Min. — — — — — — — — — — MSTTRC = 1 FMR27 = 1 LPE = 0 — — Typ. (3) 3.0 2.5 1.6 1.5 1.2 0.9 3.5 2.0 2.2 1.4 1.0 60 Max. 7.0 6.0 5.0 — — 4.5 7.5 — — — — 260 mA mA mA mA mA mA mA mA mA mA mA µA Symbol Parameter CPU Clock No division No division No division Division by 8 Division by 8 Division by 8 No division Division by 8 No division Division by 8 Division by 16 Division by 8 Unit ICC Power supply current (1) High-speed clock mode 20 MHz 16 MHz 10 MHz 20 MHz 16 MHz 10 MHz High-speed on-chip oscillator mode Off Off Off Off Off 10 MHz (4) 125 kHz 10 MHz (4) 125 kHz 4 MHz (4) Off 125 kHz 125 kHz Low-speed on-chip oscillator mode Wait mode Off Off Off 125 kHz — VC1E = 0 VC0E = 0 LPE = 1 Peripheral clock supplied during WAIT instruction execution Peripheral clock stopped during WAIT instruction execution Topr = 25 °C Peripheral clock stopped Topr = 85 °C Peripheral clock stopped — 15 90 µA Off Off 125 kHz — VC1E = 0 VC0E = 0 LPE = 1 WCKSTP = 1 VC1E = 0 VC0E = 0 STPM = 1 VC1E = 0 VC0E = 0 STPM = 1 — 4.0 80 µA Stop mode Off Off Off — — 1.0 4.0 µA Off Off Off — — 1.5 — µA Notes: 1. 2. 3. 4. Vcc = 2.7 V to 4.0 V, single-chip mode, output pins are open, and other pins are connected to Vss. When the XIN input is a square wave. Vcc = 3.0 V Set the system clock to 10 MHz or 4 MHz with the PHISEL register. R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 37 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 4. Electrical Characteristics Timing Requirements (Vcc = 3 V, Vss = 0 V at Topr = 25 °C, unless otherwise specified) Table 4.21 Symbol tc(XIN) tWH(XIN) tWL(XIN) XIN Input Parameter Standard Min. 50 24 24 Max. — — — Unit ns ns ns XIN input cycle time XIN input high width XIN input low width tC(XIN) tWH(XIN) Vcc = 3 V XIN input tWL(XIN) Figure 4.8 XIN Input Timing When Vcc = 3 V Table 4.22 Symbol tc(TRJIO) tWH(TRJIO) tWL(TRJIO) TRJIO Input Parameter Standard Min. 300 120 120 Max. — — — Unit ns ns ns TRJIO input cycle time TRJIO input high width TRJIO input low width tC(TRJIO) tWH(TRJIO) Vcc = 3 V TRJIO input tWL(TRJIO) Figure 4.9 TRJIO Input Timing When Vcc = 3 V R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 38 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 4. Electrical Characteristics Table 4.23 Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Serial Interface Parameter Standard Min. 300 150 150 — 0 70 90 Max. — — — 80 — — — Unit ns ns ns ns ns ns ns CLK0 input cycle time CLK0 input high width CLK0 input low width TXD0 output delay time TXD0 hold time RXD0 input setup time RXD0 input hold time tC(CK) tW(CKH) Vcc = 3 V CLK0 tW(CKL) th(C-Q) TXD0 td(C-Q) tsu(D-C) th(C-D) RXD0 Figure 4.10 Serial Interface Timing When Vcc = 3 V Table 4.24 Symbol tW(INH) tW(INL) External Interrupt INTi Input, Key Input Interrupt KIi (i = 0 to 3) Parameter Standard Min. 380 (1) 380 (2) Max. — — Unit ns ns INTi input high width, KIi input high width INTi input low width, KIi input low width Notes: 1. When the digital filter is enabled by the INTi input filter select bit, the INTi input high width is (1/digital filter clock frequency × 3) or the minimum value of the standard, whichever is greater. 2. When the digital filter is enabled by the INTi input filter select bit, the INTi input low width is (1/digital filter clock frequency × 3) or the minimum value of the standard, whichever is greater. Vcc = 3 V tW(INL) INTi input KIi input (i = 0 to 3) tW(INH) Figure 4.11 Timing for External Interrupt INTi Input and Key Input Interrupt KIi When Vcc = 3 V R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 39 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 4. Electrical Characteristics Table 4.25 Symbol VOH DC Characteristics (5) [1.8 V ≤ Vcc < 2.7 V] Parameter Condition Standard Min. Vcc - 0.5 Vcc - 0.5 Vcc - 0.5 Typ. — — — Max. Vcc Vcc Vcc Unit V V V Output high voltage P1_2, P1_3, P1_4, P1_5, When drive IOH = -2 mA P3_3, P3_4, P3_5, P3_7 (2) capacity is high When drive IOH = -1 mA capacity is low P1_0, P1_1, P1_6, P1_7, P4_2, P4_5, P4_6, P4_7, PA_0 IOH = -1 mA VOL Output low voltage P1_2, P1_3, P1_4, P1_5, When drive IOL = 2 mA P3_3, P3_4, P3_5, P3_7 (2) capacity is high When drive IOL = 1 mA capacity is low P1_0, P1_1, P1_6, P1_7, P4_2, P4_5, P4_6, P4_7, PA_0 IOL = 1 mA — — — — — — 0.5 0.5 0.5 V V V VT+-VT- Hysteresis INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, TRJIO, TRCIOA, TRCIOB, TRCIOC, TRCIOD, RXD0, CLK0 RESET Vcc = 2.2 V 0.05 0.20 — V Vcc = 2.2 V VI = 2.2 V, Vcc = 2.2 V VI = 0 V, Vcc = 2.2 V VI = 0 V, Vcc = 2.2 V In stop mode 0.05 — — 70 — 1.8 0.20 — — 140 2.2 — — 4.0 -4.0 300 — — V µA µA kΩ MΩ V IIH IIL RPULLUP RfXIN VRAM Input high current Input low current Pull-up resistance Feedback resistance XIN RAM hold voltage Notes: 1. 1.8 V ≤ Vcc < 2.7 V and Topr = -20 °C to 85 °C (N version)/-40 °C to 85 °C (D version), f(XIN) = 5 MHz, unless otherwise specified. 2. High drive capacity can also be used while the peripheral output function is used. R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 40 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 4. Electrical Characteristics Table 4.26 DC Characteristics (6) [1.8 V ≤ Vcc < 2.7 V] (Topr = -20 °C to 85 °C (N version)/-40 °C to 85 °C (D version), unless otherwise specified) Condition Oscillation Circuit XIN (2) On-Chip Oscillator HighSpeed Off Off 5 MHz (4) 5 MHz (4) 4 MHz (4) Off LowSpeed 125 kHz 125 kHz 125 kHz 125 kHz 125 kHz 125 kHz Low-PowerConsumption Setting — — Standard Other Min. — — — — MSTTRC = 1 FMR27 = 1 LPE = 0 — — Typ. (3) 1.0 0.6 1.6 1.1 1.0 60 Max. — — 6.5 — — 200 mA mA mA mA mA µA Symbol Parameter CPU Clock No division Division by 8 No division Division by 8 Division by 16 Division by 8 Unit ICC Power supply current (1) High-speed clock mode 5 MHz 5 MHz High-speed on-chip oscillator mode Off Off Off Low-speed on-chip oscillator mode Wait mode Off Off Off 125 kHz — VC1E = 0 VC0E = 0 LPE = 1 Peripheral clock supplied during WAIT instruction execution Peripheral clock stopped during WAIT instruction execution Topr = 25 °C Peripheral clock stopped Topr = 85 °C Peripheral clock stopped — 15 90 µA Off Off 125 kHz — VC1E = 0 VC0E = 0 LPE = 1 WCKSTP = 1 VC1E = 0 VC0E = 0 STPM = 1 VC1E = 0 VC0E = 0 STPM = 1 — 4.0 80 µA Stop mode Off Off Off — — 1.0 4.0 µA Off Off Off — — 1.5 — µA Notes: 1. 2. 3. 4. Vcc = 1.8 V to 2.7 V, single-chip mode, output pins are open, and other pins are connected to Vss. When the XIN input is a square wave. Vcc = 2.2 V Set the system clock to 5 MHz or 4 MHz with the PHISEL register. R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 41 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 4. Electrical Characteristics Timing Requirements (Vcc = 2.2 V, Vss = 0 V at Topr = 25 °C, unless otherwise specified) Table 4.27 Symbol tc(XIN) tWH(XIN) tWL(XIN) XIN Input Parameter Standard Min. 200 90 90 Max. — — — Unit ns ns ns XIN input cycle time XIN input high width XIN input low width tC(XIN) tWH(XIN) Vcc = 2.2 V XIN input tWL(XIN) Figure 4.12 XIN Input Timing When Vcc = 2.2 V Table 4.28 Symbol tc(TRJIO) tWH(TRJIO) tWL(TRJIO) TRJIO Input Parameter Standard Min. 500 200 200 Max. — — — Unit ns ns ns TRJIO input cycle time TRJIO input high width TRJIO input low width tC(TRJIO) tWH(TRJIO) Vcc = 2.2 V TRJIO input tWL(TRJIO) Figure 4.13 TRJIO Input Timing When Vcc = 2.2 V R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 42 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group 4. Electrical Characteristics Table 4.29 Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Serial Interface Parameter Standard Min. 800 400 400 — 0 150 90 Max. — — — 200 — — — Unit ns ns ns ns ns ns ns CLK0 input cycle time CLK0 input high width CLK0 input low width TXD0 output delay time TXD0 hold time RXD0 input setup time RXD0 input hold time tC(CK) tW(CKH) Vcc = 2.2 V CLK0 tW(CKL) th(C-Q) TXD0 td(C-Q) tsu(D-C) th(C-D) RXD0 Figure 4.14 Serial Interface Timing When Vcc = 2.2 V Table 4.30 Symbol tW(INH) tW(INL) External Interrupt INTi Input, Key Input Interrupt KIi (i = 0 to 3) Parameter Standard Min. 1,000 (1) 1,000 (2) Max. — — Unit ns ns INTi input high width, KIi input high width INTi input low width, KIi input low width Notes: 1. When the digital filter is enabled by the INTi input filter select bit, the INTi input high width is (1/digital filter clock frequency × 3) or the minimum value of the standard, whichever is greater. 2. When the digital filter is enabled by the INTi input filter select bit, the INTi input low width is (1/digital filter clock frequency × 3) or the minimum value of the standard, whichever is greater. Vcc = 2.2 V tW(INL) INTi input KIi input (i = 0 to 3) tW(INH) Figure 4.15 Timing for External Interrupt INTi Input and Key Input Interrupt KIi When Vcc = 2.2 V R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 Page 43 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group Package Dimensions Package Dimensions Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas Electronics website. JEITA Package Code P-TSSOP14-4.4x5-0.65 RENESAS Code PTSP0014JA-B Previous Code TTP-14DV MASS[Typ.] 0.05g *1 D F 8 14 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp *2 HE E Index mark Terminal cross section ( Ni/Pd/Au plating ) 1 Z e *3 c 7 bp x M L1 Reference Symbol Dimension in Millimeters θ A1 L y Detail F D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 5.00 5.30 4.40 0.03 0.07 0.10 1.10 0.15 0.20 0.25 0.10 0.15 0.20 0° 8° 6.20 6.40 6.60 0.65 0.13 0.10 0.83 0.4 0.5 0.6 1.0 R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 A Page 44 of 45 Under development Preliminary document Specifications in this document are tentative and subject to change. R8C/M11A Group, R8C/M12A Group Package Dimensions JEITA Package Code P-LSSOP20-4.4x6.5-0.65 RENESAS Code PLSP0020JB-A Previous Code 20P2F-A MASS[Typ.] 0.1g 20 11 HE *1 E F NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 1 Index mark 10 c A2 A1 *2 D Reference Symbol Dimension in Millimeters e y *3 bp Detail F D E A2 A A1 bp c HE e y L Nom Max 6.5 6.6 4.4 4.5 1.15 1.45 0.1 0.2 0 0.17 0.22 0.32 0.13 0.15 0.2 0° 10° 6.2 6.4 6.6 0.53 0.65 0.77 0.10 0.3 0.5 0.7 R01DS0010EJ0010 Rev.0.10 Aug 25, 2010 A L Min 6.4 4.3 Page 45 of 45 REVISION HISTORY R8C/M11A Group, R8C/M12A Group Datasheet Description Rev. 0.01 0.10 Date Jan 14, 2010 Aug 25, 2010 Page — — 2, 3 4 5 First Edition issued Summary Document No. “REJ03B0308” → “R01DS0010EJ” 1.1.2 Differences between Groups added Table 1.3 “Reset by voltage detection 0” deleted Table 1.4 “... ROM: VCC = 2.7 V to 5.5 V” → “... ROM: VCC = 1.8 V to 5.5 V”, “1,000 times (program ROM)” → “10,000 times (program ROM)”, Note 1 added Table 1.5 revised Figures 1.3 and 1.4 revised Table 1.6 revised 2. Central Processing Unit (CPU), 3. Address Space, 4. Electrical Characteristics added 6 8 9 11 to 43 All trademarks and registered trademarks are the property of their respective owners. C-1 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.  The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.  The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.  The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.  When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems.  The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products. Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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