R5F35626DFE

M16C/5LD Group, M16C/56D Group RENESAS MCU REJ03B0307-0110 Rev.1.10 Dec 01, 2009 1. 1.1 Overview Features The M16C/5LD Group, M16C/56D Group’s MCUs are single-chip control units that utilize highperformance silicon gate CMOS technology with the M16C/60 Series CPU core. The M16C/5LD Group, M16C/56D Group are available in 64-pin and 80-pin plastic molded LQFP packages. These MCUs employ sophisticated instructions for a high level of efficiency and they are capable of executing instructions at high speed. In addition, the CPU core boasts a multiplier and DMAC for high-speed operation processing which makes it adequate for controlling office equipment, home appliances, and industrial equipment. The M16C/5LD Group has one CAN module, which makes it suitable for factory automation LAN system. 1.1.1 Applications Factory automation LAN system, audio components, cameras, televisions, household appliances, office equipment, communication devices, mobile devices, industrial equipment, and other applications. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 1 of 83 M16C/5LD Group, M16C/56D Group 1. Overview 1.2 Specifications Table 1.1 to Table 1.4 list specifications of the M16C/5LD Group, M16C/56D Group. Table 1.1 Item CPU Specifications (80-pin Version) (1/2) Function Specification Central processing unit M16C/60 Series CPU Core (Multiplier: 16 × 16 32 bits, Multiply-accumulate unit: 16 × 16 + 32 32 bits) • Basic instructions: 91 • Minimum instruction execution time: 31.25 ns (f(BCLK) = 32 MHz, VCC = 3.0 to 5.5 V) 40ns (f(BCLK) = 25MHz, VCC = 2.7 to 5.5V) • Operating mode: Single-chip mode Memory Voltage Detection Clock ROM, RAM, data flash Voltage detector Clock generator See Table 1.5. and Table 1.6 • 2 voltage detect points • 4 circuits (Main clock, sub clock, PLL frequency synthesizer, 125-kHz onchip oscillator) I/O Ports Interrupts Programmable I/O ports • Oscillation stop detector: Main clock oscillator stop/re-oscillation detection • Frequency divide circuit: Divide-by-1, 2, 4, 8, or 16 selectable • Low-power consumption modes: Wait mode, stop mode • Real time clock • 71 CMOS inputs/outputs, a pull-up resistor selectable • Interrupt vectors: 70 • External interrupt inputs: 11 (NMI, INT × 6, key input × 4) • Interrupt priority levels: 7 levels • 15 bits × 1 (with prescaler) • Automatic reset start function selectable • 125-kHz on-chip oscillator for watchdog timer • 4 channels, Cycle-steal transfer mode • Trigger sources: 42 • Transfer modes: 2 (single transfer, repeat transfer) Watchdog Timer DMA DMAC Timers 16-bit timer × 5 Timer mode, event counter mode, one-shot timer mode, pulse-width modulation (PWM) mode Two-phase pulse signal processing in event counter mode (two-phase encoder input) × 3 Programmable output mode × 3 Timer B 16-bit timer × 3 Timer mode, event counter mode, pulse frequency measurement mode, pulse-width measurement mode Timer function for three- Three-phase motor control timer ×1 (timers A1, A2, A4, and B2 used) phase motor control On-chip dead time timer Timer S (Input capture/ • 16-bit timer × 1 (base timer) output compare) • I/O: 8 channels Task monitoring timer Real-time clock UART0 to UART4 16-bit timer ×1 channel Count: seconds, minutes, hours, weeks 4 channels (UART, clock synchronous serial interface) 1 channels (UART, clock synchronous serial interface, I2C-bus, IEBus)(1) 10-bit resolution × 27 channels (A/D circuit) 10-bit resolution × 4 channels (A/D1 circuit) Timer A Serial Interface A/D Converter Note: 1. IEBus is a trademark of NEC Electronics Corporation. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 2 of 83 M16C/5LD Group, M16C/56D Group 1. Overview Table 1.2 Specifications (80-pin Version) (2/2) Function Specification Item CRC Calculator • 1 circuit • CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant • MSB/LSB selectable 1 channel 32-slot message buffer × 1 channel (M16C/5LD Group only) • Programming and erasure supply voltage: 2.7 to 5.5 V • Programming and erasure endurance: 1,000 times (program ROM 1, program ROM 2)/10,000 times (data flash) • Program security: ROM code protect, ID code check On-board flash rewrite function, address match × 4 32 MHz / 3.0 to 5.5 V 25 MHz / 2.7 to 5.5 V -40°C to 85°C 80-pin plastic mold LQFP: PLQP0080KB-A (Previous package code: 80P6Q-A) Multi-master I2C-bus interface CAN Module Flash Memory Debug Functions Operating Frequency/Power Supply Voltage Operating Temperature Package REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 3 of 83 M16C/5LD Group, M16C/56D Group 1. Overview Table 1.3 Item CPU Specifications (64-pin Version) (1/2) Function Central processing unit Specification M16C/60 Series CPU Core (Multiplier: 16 × 16 32 bits, Multiply-accumulate unit: 16 × 16 + 32 32 bits) • Basic instructions: 91 • Minimum instruction execution time: 31.25 ns (f(BCLK) = 32 MHz, VCC = 3.0 to 5.5 V) 40ns (f(BCLK) = 25MHz, VCC = 2.7 to 5.5V) • Operating mode: Single-chip mode See Table 1.5. and Table 1.6 2 voltage detect points Memory Voltage Detection Clock ROM, RAM, data flash Voltage detector Clock generator • 4 circuits (Main clock, sub clock, PLL frequency synthesizer, 125-kHz on-chip oscillator) I/O Ports Interrupts Programmable I/O ports • Oscillation stop detector: Main clock oscillator stop/re-oscillation detection • Frequency divide circuit: Divide-by-1, 2, 4, 8, or 16 selectable • Low-power consumption modes: Wait mode, stop mode • Real time clock • 55 CMOS inputs/outputs, a pull-up resistor selectable • Interrupt vectors: 70 • External interrupt inputs: 11 (NMI, INT × 6, key input × 4) • Interrupt priority levels: 7 levels • 15 bits × 1 (with prescaler) • Automatic reset start function selectable • 125-kHz on-chip oscillator for watchdog timer • 4 channels, Cycle-steal transfer mode • Trigger sources: 40 • Transfer modes: 2 (single transfer, repeat transfer) 16-bit timer × 5 Timer mode, event counter mode, one-shot timer mode, pulse-width modulation (PWM) mode Two-phase pulse signal processing in event counter mode (two-phase encoder input) × 3 Programmable output mode × 3 16-bit timer × 3 Timer mode, event counter mode, pulse frequency measurement mode, pulsewidth measurement mode Three-phase motor control timer ×1 (timers A1, A2, A4, and B2 used) On-chip dead time timer Watchdog Timer DMA DMAC Timer Timer A Timer B Serial Interface A/D Converter Timer function for three-phase motor control Timer S (Input capture/output compare) Task monitoring timer Real-time clock UART0 to UART3 • 16-bit timer × 1 (base timer) • I/O: 8 channels 16-bit timer ×1 channel Count: seconds, minutes, hours, weeks 3 channels (UART, clock synchronous serial interface) 1 channels (UART, clock synchronous serial interface, I2C-bus, IEBus)(1) 10-bit resolution × 16 channels (A/D circuit) 10-bit resolution × 4 channels (A/D1 circuit) Note: 1. IEBus is a trademark of NEC Electronics Corporation. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 4 of 83 M16C/5LD Group, M16C/56D Group 1. Overview Table 1.4 Specifications (64-pin Version) (2/2) Function Specification Item CRC Calculator • 1 circuit • CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant • MSB/LSB selectable 1 channel 32-slot message buffer × 1 channel (M16C/5LD Group only) Multi-master I2C-bus interface CAN Module Flash Memory • Programming and erasure supply voltage: 2.7 to 5.5 V • Programming and erasure endurance: 1,000 times (program ROM 1, program ROM 2)/10,000 times (data flash) • Program security: ROM code protect, ID code check Debug Functions Operating Frequency/Power Supply Voltage Operating Temperature Package On-board flash rewrite function, address match × 4 32 MHz / 3.0 to 5.5 V 25 MHz / 2.7 to 5.5 V -40°C to 85°C 64-pin plastic mold LQFP: PLQP0064KB-A (Previous package code: 64P6Q-A) REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 5 of 83 M16C/5LD Group, M16C/56D Group 1. Overview 1.3 Product List Table 1.5 shows product information on the M16C/5LD Group, M16C/56D Group. Figure 1.1 shows part numbers, memory sizes, and packages. Figure 1.2 shows marking drawing (top view). Table 1.5 Product List of M16C/5LD Group ROM Capacity Part Number Program ROM 1 64 Kbytes 96 Kbytes 128 Kbytes 256 Kbytes Program ROM 2 16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes Data flash 4 Kbytes x 2 blocks 4 Kbytes x 2 blocks 4 Kbytes x 2 blocks 4 Kbytes x 2 blocks RAM Capacity 4 Kbytes 8 Kbytes 1 channel 12 Kbytes 20 Kbytes CAN Package Name As of Dec.2009 Remarks R5F35L30DFF R5F35L23DFE R5F35L33DFF R5F35L26DFE R5F35L36DFF R5F35L2EDFE R5F35L3EDFF (D): Under development (P): Under planning PLQP0064KB-A PLQP0080KB-A PLQP0064KB-A PLQP0080KB-A PLQP0064KB-A PLQP0080KB-A PLQP0064KB-A The old package names are as follows: PLQP0080KB-A: 80P6Q-A PLQP0064KB-A: 64P6Q-A Table 1.6 Product List of M16C/56D Group ROM Capacity Program ROM 1 64 Kbytes 96 Kbytes 128 Kbytes 256 Kbytes Program ROM 2 16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes RAM Capacity 4 Kbytes 8 Kbytes N/A 12 Kbytes 20 Kbytes CAN Package Name As of Dec.2009 Remarks Part Number Data flash 4 Kbytes x 2 blocks 4 Kbytes x 2 blocks 4 Kbytes x 2 blocks 4 Kbytes x 2 blocks R5F35630DFF R5F35623DFE R5F35633DFF R5F35626DFE R5F35636DFF R5F3562EDFE R5F3563EDFF (D): Under development (P): Under planning PLQP0064KB-A PLQP0080KB-A PLQP0064KB-A PLQP0080KB-A PLQP0064KB-A PLQP0080KB-A PLQP0064KB-A The old package names are as follows: PLQP0080KB-A: 80P6Q-A PLQP0064KB-A: 64P6Q-A REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 6 of 83 M16C/5LD Group, M16C/56D Group 1. Overview MCU Part No. R 5 F 3 5L 2 0 D FE Package type FE: PLQP0080KB-A (80P6Q-A) FF: PLQP0064KB-A (64P6Q-A) Property code D: Operating temperature -40°C to 85°C Memory capacity Program ROM 1/RAM 0: 64 Kbytes/4 Kbytes 3: 96 Kbytes/8 Kbytes 6: 128 Kbytes/12 Kbytes E: 256 Kbytes/20 Kbytes Pin 2: 80-pin 3: 64-pin Group Name 5L: M16C/5LD Group 56: M16C/56D Group 16-bit MCU Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.1 Correspondence of Part Number, Memory Size, and Package M16C R5F35L20DFE XXXXXXX Part number (See Figure 1.1 “Correspondence of Part Number, Memory Size, and Package”.) Seven digit date code Figure 1.2 Marking Diagram of Flash Memory Version (Top View) REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 7 of 83 M16C/5LD Group, M16C/56D Group 1. Overview 1.4 Block Diagram Figure 1.3 shows a block diagram of M16C/5LD Group, M16C/56D Group 80-pin package. Figure 1.4 shows a block diagram of the M16C/5LD Group, M16C/56D Group 64-pin package. 8 8 8 8 I/O ports Peripherals Port P0 Port P1 Port P2 Port P3 Port P6 Timer (16-bit) Output (timer A): 5 Input (timer B): 3 Three-phase motor control circuit Timer S (Input capture/output compare) Time measurement: 8 channels Waveform generating: 8 channels UART/clock synchronous serial interface (8-bit x 5 channels) DMAC (4 channels) Multi-master I2 C bus CAN module (32-slot message buffer, 1 channel) (M16C/5LD Group only) Clock generator XIN-XOUT XCIN-XCOUT 125-kHz on-chip oscillator PLL frequency synthesizer 125-kHz on-chip oscillator dedicated to watchdog timer 8 Port P7 Port P8 8 CRC calculator (CCITT, CRC-16) Voltage detector 8 Task monitoring timer (1 channel) Real-time clock (8-bit x 1 channel) A/D converter (10-bit x 27 channels) (A/D circuit) (10-bit x 4 channels) (A/D1 circuit) Port P9 Power-on reset On-chip debugger 7 M16C/60 Series CPU core R0H R1H R0L R1L R2 R3 R3 A0 A1 FB FB SB USP ISP INTB PC FLG Memory ROM RAM ( 1) Port P10 8 Watchdog timer (15 bits) ( 2) Multiplier Notes: 1. ROM size depends on MCU type. 2. RAM size depends on MCU type Figure 1.3 M16C/5LD Group, M16C/56D Group 80-Pin Block Diagram REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 8 of 83 M16C/5LD Group, M16C/56D Group 1. Overview 4 3 8 4 I/O ports Peripherals Port P0 Port P1 Port P2 Port P3 Port P6 Timer (16-bit) Output (timer A): 5 Input (timer B): 3 Three-phase motor control circuit Timer S (Input capture/output compare) Time measurement: 8 channels Waveform generating: 8 channels UART/clock synchronous serial interface (8-bit x 4 channels) DMAC (4 channels) Multi-master I2 C bus CAN module (32-slot message buffer, 1 channel) (M16C/5LD Group only) Clock generator XIN-XOUT XCIN-XCOUT 125-kHz on-chip oscillator PLL frequency synthesizer 125-kHz on-chip oscillator dedicated to watchdog timer 8 Port P7 Port P8 8 CRC calculator (CCITT, CRC-16) Voltage detector Power-on reset On-chip debugger 8 Task monitoring timer (1 channel) Real-time clock (8-bit x 1 channel) A/D converter (10-bit x 16 channels) (A/D circuit) (10-bit x 4 channels) (A/D1 circuit) Port P9 4 M16C/60 Series CPU core R0H R1H R0L R1L R2 R3 R3 A0 A1 FB FB SB USP ISP INTB PC FLG Memory ROM RAM (1) Port P10 8 Watchdog timer (15 bits) (2) Multiplier Notes: 1. ROM size depends on MCU type. 2. RAM size depends on MCU type. Figure 1.4 M16C/5LD Group, M16C/56D Group 64-Pin Block Diagram REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 9 of 83 M16C/5LD Group, M16C/56D Group 1. Overview 1.5 Pin Assignments Figure 1.5 shows the pin assignments for 80-pin package, and Table 1.7 and Table 1.8 list pin names for 80-pin package. P0_7 / AN0_7 P1_0 / AN2_0 P1_1 / AN2_1 P1_2 / AN2_2 P1_3 / AN2_3 P1_4 P1_5 / INT3 / ADTRG / IDV P1_6 / INT4 / IDW P1_7 / INT5 / INPC1_7 / IDU P2_0 / OUTC1_0 / INPC1_0 / SDAMM P2_1 / OUTC1_1 / INPC1_1 / SCLMM P2_2 / OUTC1_2 / INPC1_2 P2_3 / OUTC1_3 / INPC1_3 P2_4 / OUTC1_4 / INPC1_4 P2_5 / OUTC1_5 / INPC1_5 P2_6 / OUTC1_6 / INPC1_6 P2_7 / OUTC1_7 / INPC1_7 P6_0 / RTCOUT / CTS0 / RTS0 P6_1 / CLK0 P6_2 / RXD0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 P0_6 / AN0_6 P0_5 / AN0_5 P0_4 / AN0_4 P0_3 / AN0_3 P0_2 / AN0_2 P0_1 / AN0_1 P0_0 / AN0_0 P10_7 / AN_7 / KI3 P10_6 / AN_6 / KI2 P10_5 / AN_5 / KI1 P10_4 / AN_4 / KI0 P10_3 / AN_3 P10_2 / AN_2 P10_1 / AN_1 AVSS P10_0 / AN_0 VREF AVCC P9_7 / AN2_7 / RXD4 P9_6 / AN2_6 / TXD4 41 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 M16C/5LD Group M16C/56D Group PLQP0080KB-A (80P6Q-A) (Top view) P6_3 P3_0 P3_1 P3_2 P3_3 P3_4 P3_5 P3_6 P3_7 P6_4 P6_5 P6_6 P6_7 P7_0 P7_1 P7_2 P7_3 P7_4 P7_5 P7_6 / / / / / TXD0 CLK3 RXD3 TXD3 CTS3 / RTS3 / / / / / / / / / / / CTS1 / RTS1 CLK1 RXD1 TXD1 TXD2 / SDA2 / TA0OUT / CTS1 / RTS1 RXD2 / SCL2 / TA0IN / CLK1 CLK2 / TA1OUT / V / RXD1 CTS2 / RTS2 / TA1IN / V / TXD1 TA2OUT / W TA2IN / W TA3OUT Note: 1. There are pins CTX0 and CRX0 only in the M16C/5LD group. Figure 1.5 Pin Assignment for 80-Pin Package (Top View) Set bits PACR2 to PACR0 in the PACR register to 010b before signals are input or output to individual pins after reset. When the PACR register is not set, signals are not input or output for some of the pins. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 10 of 83 P9_5 / AN2_5/ CLK4 P9_3 / AN2_4 /CTX0 (1) P9_2 / AN3_2 / TB2IN / CRX0 (1) P9_1 / AN3_1 / TB1IN P9_0 / AN3_0 / TB0IN / CLKOUT CNVSS P8_7 / XCIN P8_6 / XCOUT RESET XOUT VSS XIN VCC P8_5 / NMI / SD P8_4 / INT2 / ZP P8_3 / INT1 P8_2 / INT0 P8_1 / TA4IN / U P8_0 / TA4OUT / U P7_7 / TA3IN M16C/5LD Group, M16C/56D Group 1. Overview Table 1.7 Pin No. 1 2 3 4 5 6 7 8 9 CNVSS XCIN XCOUT RESET Control pin Pin Names, 80-Pin Package (1/2) Port Interrupt Pin Timer Pin Timer S Pin UART/CAN Pin Multimaster I2C-bus pin Analog Pin AN2_5 AN2_4 AN3_2 AN3_1 AN3_0 (1) P9_5 P9_3 P9_2 P9_1 CLKOUT P9_0 P8_7 P8_6 TB2IN TB1IN TB0IN CLK4 CTX0 (1) CRX0 10 XOUT 11 VSS 12 XIN 13 VCC 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7 P6_6 P6_5 P6_4 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 P3_0 P6_3 CTS3/RTS3 TXD3 RXD3 CLK3 TXD0 NMI INT2 INT1 INT0 TA4IN/U TA4OUT/U TA3IN TA3OUT TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V TA0IN TA0OUT CTS2/RTS2/TXD1 CLK2/RXD1 RXD2/SCL2/CLK1 TXD2/SDA2/CTS1/RTS1 TXD1 RXD1 CLK1 CTS1/RTS1 SD ZP Note 1. There are pins CTX0 and CRX0 only in the M16C/5LD Group. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 11 of 83 M16C/5LD Group, M16C/56D Group 1. Overview Table 1.8 Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 AVSS 76 77 VREF 78 AVCC 79 80 Control pin Pin Names, 80-Pin Package (2/2) Port Interrupt Pin Timer Pin Timer S Pin UART/CAN Pin Multimaster I2C-bus pin Analog Pin P6_2 P6_1 P6_0 P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 P10_7 KI3 P10_6 KI2 P10_5 KI1 P10_4 KI0 P10_3 P10_2 P10_1 P10_0 INT5 INT4 INT3 IDU IDW IDV RTCOUT OUTC1_7/INPC1_7 OUTC1_6/INPC1_6 OUTC1_5/INPC1_5 OUTC1_4/INPC1_4 OUTC1_3/INPC1_3 OUTC1_2/INPC1_2 OUTC1_1/INPC1_1 OUTC1_0/INPC1_0 INPC1_7 RXD0 CLK0 CTS0/RTS0 SCLMM SDAMM ADTRG AN2_3 AN2_2 AN2_1 AN2_0 AN0_7 AN0_6 AN0_5 AN0_4 AN0_3 AN0_2 AN0_1 AN0_0 AN_7 AN_6 AN_5 AN_4 AN_3 AN_2 AN_1 AN_0 P9_7 P9_6 RXD4 TXD4 AN2_7 AN2_6 REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 12 of 83 M16C/5LD Group, M16C/56D Group 1. Overview Figure 1.6 shows the pin assignments for 64-pin package and Table 1.9 and Table 1.10 list pin names for 64-pin package. 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 P0_2 / AN0_2 P0_1 / AN0_1 P0_0 / AN0_0 P10_7 / AN_7 / KI3 P10_6 / AN_6 / KI2 P10_5 / AN_5 / KI1 P10_4 / AN_4 / KI0 P10_3 / AN_3 P10_2 / AN_2 P10_1 / AN_1 AVSS P10_0 / AN_0 VREF AVCC P9_3 / AN2_4 /CTX0 (1) P9_2 / AN3_1 / TB2IN / CRX0 (1) 33 P0_3 / AN0_3 P1_5 / INT3 / ADTRG / IDV P1_6 / INT4 / IDW P1_7 / INT5 / INPC1_7 / IDU P2_0 / OUTC1_0 / INPC1_0 / SDAMM P2_1 / OUTC1_1 / INPC1_1 / SCLMM P2_2 / OUTC1_2 / INPC1_2 P2_3 / OUTC1_3 / INPC1_3 P2_4 / OUTC1_4 / INPC1_4 P2_5 / OUTC1_5 / INPC1_5 P2_6 / OUTC1_6 / INPC1_6 P2_7 / OUTC1_7 / INPC1_7 P6_0 / RTCOUT / CTS0 / RTS0 P6_1 / CLK0 P6_2 / RXD0 P6_3 / TXD0 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 32 31 30 29 M16C/5LD Group M16C/56D Group PLQP0064KB-A (64P6Q-A) (Top view) 28 27 26 25 24 23 22 21 20 19 18 17 P3_0 / CLK3 P3_1 / RXD3 P3_2 / TXD3 P3_3 / CTS3 / RTS3 P6_4 / RTS1 / CTS1 P6_5 / CLK1 P6_6 / RXD1 P6_7 / TXD1 P7_0 / TXD2 / SDA2 / TA0OUT / CTS1 / RTS1 P7_1 / RXD2 / SCL2 / TA0IN / CLK1 P7_2 / CLK2 / TA1OUT / V / RXD1 P7_3 / CTS2 / RTS2 / TA1IN / V / TXD1 P7_4 / TA2OUT / W P7_5 / TA2IN / W P7_6 / TA3OUT P7_7 / TA3IN Note: 1. There are pins CTX0 and CRX0 only in the M16C/5LD group. Figure 1.6 Pin Assignment for 64-Pin Package (Top View) Set bits PACR2 to PACR0 in the PACR register to 010b before signals are input or output to individual pins after reset. When the PACR register is not set, signals are not input or output for some of the pins. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 13 of 83 P9_1 / AN3_1 / TB1IN P9_0 / AN3_0 / TB0IN / CLKOUT CNVSS P8_7 / XCIN P8_6 / XCOUT RESET XOUT VSS XIN VCC P8_5 / NMI / SD P8_4 / INT2 / ZP P8_3 / INT1 P8_2 / INT0 P8_1 / TA4IN / U P8_0 / TA4OUT / U M16C/5LD Group, M16C/56D Group 1. Overview Table 1.9 Pin No. 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CNVSS XCIN XCOUT RESET XOUT VSS XIN Control pin Pin Names, 64-Pin Package (1/2) Port Interrupt Pin Timer Pin Timer S Pin UART/CAN Pin Multimaster I2C-bus pin Analog Pin AN3_1 AN3_0 P9_1 CLKOUT P9_0 P8_7 P8_6 TB1IN TB0IN 10 VCC P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7 P6_6 P6_5 P6_4 P3_3 P3_2 P3_1 P3_0 P6_3 P6_2 P6_1 P6_0 P2_7 P2_6 P2_5 P2_4 RTCOUT OUTC1_7/INPC1_7 OUTC1_6/INPC1_6 OUTC1_5/INPC1_5 OUTC1_4/INPC1_4 NMI INT2 INT1 INT0 TA4IN/U TA4OUT/U TA3IN TA3OUT TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V TA0IN TA0OUT CTS2/RTS2/TXD1 CLK2/RXD1 RXD2/SCL2/CLK1 TXD2/SDA2/CTS1/RTS1 TXD1 RXD1 CLK1 CTS1/RTS1 CTS3/RTS3 TXD3 RXD3 CLK3 TXD0 RXD0 CLK0 CTS0/RTS0 SD ZP REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 14 of 83 M16C/5LD Group, M16C/56D Group 1. Overview Table 1.10 Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 AVSS 60 61 VREF 62 AVCC 63 64 Control pin Pin Names, 64-Pin Package (2/2) Port Interrupt Pin Timer Pin Timer S Pin UART/CAN Pin Multimaster Analog Pin I2C-bus pin P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P0_3 P0_2 P0_1 P0_0 P10_7 KI3 P10_6 KI2 P10_5 KI1 P10_4 KI0 P10_3 P10_2 P10_1 P10_0 INT5 INT4 INT3 IDU IDW IDV OUTC1_3/INPC1_3 OUTC1_2/INPC1_2 OUTC1_1/INPC1_1 OUTC1_0/INPC1_0 INPC1_7 ADTRG AN0_3 AN0_2 AN0_1 AN0_0 AN_7 AN_6 AN_5 AN_4 AN_3 AN_2 AN_1 AN_0 SCLMM SDAMM P9_3 P9_2 TB2IN CTX0 (1) CRX0 (1) AN2_4 AN3_2 Note 1. There are pins CTX0 and CRX0 only in the M16C/5LD Group. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 15 of 83 M16C/5LD Group, M16C/56D Group 1. Overview 1.6 Pin Functions Pin Functions (64-Pin and 80-Pin Packages) Pin Name VCC, VSS AVCC, AVSS RESET CNVSS XIN XOUT O I/O I I I I I Description Apply 2.7 V to 5.5 V to VCC pin and 0 V to VSS pin. Power supply for the A/D converter. AVCC and AVSS should be connected to VCC and VSS, respectively. Low active input pin. Driving this low resets the MCU. Connect the CNVSS to VSS. Input/output pin for the main clock oscillator. Connect a ceramic resonator or crystal oscillator between XIN and XOUT. (1) To apply an external clock, connect it to XIN and leave XOUT open. When XIN is not used, connect XIN to VCC pin and leave XOUT open. Input/output for the sub clock oscillator. Connect a crystal oscillator between XCIN and XCOUT. This pin outputs the clock having the same frequency as f1, f8, f32, or fC. Low active input pins for INT interrupt. INT2 is used to input Z-phase of timer A. Low active input pin for NMI interrupt. Low active Input pins for the key input interrupt Timers A0 to A4 input/output pins Timers A0 to A4 input pins Input pin for Z-phase Timers B0 to B2 input pins Output pins for three-phase motor control timers Input pins for three-phase motor control timers Output pin for real time clock Input pins to control data transmission Output pins to control data reception Transfer clock input/output pins Serial data input pins Serial data output pins Serial data input/output pin Transfer clock input/output pin Serial data input/output pin Transfer clock input/output pin Table 1.11 Power supply Analog power supply Reset input CNVSS Signal Name Main clock input Main clock output Sub clock input Sub clock output Clock output INT interrupt input NMI input Key input interrupt Timer A XCIN XCOUT CLKOUT INT0 to INT5 NMI KI0 to KI3 TA0OUT to TA4OUT TA0IN to TA4IN ZP I O O I I I I/O I I I O I O I O I/O I O I/O I/O I/O Timer B TB0IN to TB2IN Three-phase motor U,U,V,V,W,W control timer IDU, IDW, IDV, SD Real time clock Serial interface RTCOUT CTS0 to CTS3 RTS0 to RTS3 CLK0 to CLK3 RXD0 to RXD3 TXD0 to TXD3 I2C mode I2C SDA2 SCL2 Multi-master bus SDAMM SCLMM Note 1. Please contact the oscillator manufacturer for oscillation characteristic. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 16 of 83 M16C/5LD Group, M16C/56D Group 1. Overview Table 1.12 Pin Functions (64-Pin and 80-Pin Packages) Signal Name Reference voltage input A/D converter Pin Name VREF AN_0 to AN_7 AN0_0 to AN0_3 AN2_4 AN3_0 to AN3_2 ADTRG I/O I I I I I O I O Description Reference voltage input pin for the A/D converter. Analog input pins for the A/D converter Low active input pin for an external A/D trigger Input pins for time measurement function Output pins for waveform generating function Input pin for CAN communication Output pin for CAN communication CMOS I/O ports. A direction register determines whether each pin is used as an input port or an output port. Pull-up resistor is selectable for every unit of 4 input ports. Timer S INPC1_0 to INPC1_7 OUTC1_0 to OUTC1_7 CAN Module (1) I/O port CRX0 CTX0 P0_0 to P0_3 P1_5 to P1_7 P2_0 to P2_7 P3_0 to P3_3 P6_0 to P6_7 P7_0 to P7_7 P8_0 to P8_7 P9_0 to P9_3 P10_0 to P10_7 I/O Note 1. There is Can module only in the M16C/5LD group. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 17 of 83 M16C/5LD Group, M16C/56D Group 1. Overview Table 1.13 Pin Functions (80-Pin Package Only) Signal Name Serial Interface Pin Name CLK4 RXD4 TXD4 I/O I O I Serial data input pin Serial data output pin Description I/O Transfer clock input/output pin A/D converter AN0_4 to AN0_7 AN2_0 to AN2_3 AN2_5 to AN2_7 P0_4 to P0_7 P1_0 to P1_4 P3_4 to P3_7 P9_5 to P9_7 Analog input pins for the A/D converter I/O port CMOS I/O ports. A direction register determines whether each pin is used as an input port or an output port. Pull-up I/O resistor is selectable for every unit of 4 input ports. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 18 of 83 M16C/5LD Group, M16C/56D Group 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of thirteen configure a register bank. There are two sets of register banks. b31 b15 b8 b7 b0 R2 R3 R0H(high-order bits of R0) R0L (low-order bits of R0) R1H(high-order bits of R1) R1L (low-order bits of R1) Data registers (1) R2 R3 A0 A1 FB Address registers (1) Frame base registers (1) b0 b19 b15 INTBH INTBL Interrupt table register INTBH is the 4 high-order bits of INTB register and INTBL is the 16 low-order bits b19 b0 PC b15 b0 Program counter USP ISP SB b15 b0 User stack pointer Interrupt stack pointer Static base register FLG b15 b8 b7 b0 Flag register IPL UI OB S Z DC Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area Note: 1. These registers configure a register bank. There are two register banks. Figure 2.1 Central Processing Unit Registers REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 19 of 83 M16C/5LD Group, M16C/56D Group 2. Central Processing Unit (CPU) 2.1 2.1.1 General Purpose Registers Data Registers (R0, R1, R2, and R3) The R0, R1, R2, and R3 are 16-bit registers used for transfer, arithmetic and logic operations. R0 and R1 can be split into high-order (R0H/R1H) and low-order bits (R0L/R1L) to be used separately as 8-bit data registers. R0 can be combined with R2 and used as a 32-bit data register (R2R0). The same applies to R3R1. 2.1.2 Address Registers (A0 and A1) A0 and A1 are 16-bit registers used for indirect addressing, relative addressing, transfer, arithmetic and logic operations. A0 can be combined with A1 and used as a 32-bit address register (A1A0). 2.1.3 Frame Base Register (FB) FB is a 16-bit register used for FB relative addressing. 2.1.4 Interrupt Table Register (INTB) INTB is a 20-bit register that indicates the start address of a relocatable interrupt vector table. 2.1.5 Program Counter (PC) PC is a 20-bit register that indicates the address of the next instruction to be executed. 2.1.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) The stack pointers (SP), USP and ISP, each have 16 bits. The U flag is used to switch between USP and ISP. 2.1.7 Static Base Register (SB) SB is a 16-bit register used for SB-relative addressing. 2.1.8 Flag Register (FLG) FLG is a 11-bit register that indicates the CPU state. 2.1.8.1 Carry Flag (C Flag) The C flag retains a carry, borrow, or shift-out bit that has been generated by the arithmetic/logic unit. 2.1.8.2 Debug Flag (D Flag) The D flag is for debugging purposes only. Set it to 0. 2.1.8.3 Zero Flag (Z Flag) The Z flag becomes 1 when an arithmetic operation results in 0; otherwise it becomes 0. 2.1.8.4 Sign Flag (S Flag) The S flag becomes 1 when an arithmetic operation results in a negative value; otherwise it becomes 0. 2.1.8.5 Register Bank Select Flag (B Flag) Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is 1. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 20 of 83 M16C/5LD Group, M16C/56D Group 2. Central Processing Unit (CPU) 2.1.8.6 Overflow Flag (O Flag) The O flag becomes set to 1 when an arithmetic operation results in an overflow; otherwise it becomes 0. 2.1.8.7 Interrupt Enable Flag (I Flag) The I flag enables maskable interrupts. Maskable interrupts are disabled when the I flag is 0, and enabled when it is 1. The I flag is 0 when an interrupt request is acknowledged. 2.1.8.8 Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is 0. USP is selected when the U flag is 1. The U flag becomes 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt number 0 to 31 is executed. 2.1.8.9 Processor Interrupt Priority Level (IPL) IPL is a 3-bit register and assigns processor interrupt priority levels from 0 to 7. If a requested interrupt has a higher priority than IPL, the interrupt is enabled. 2.1.8.10 Reserved Areas Only write 0 to bits assigned as reserved areas. The read value is undefined. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 21 of 83 M16C/5LD Group, M16C/56D Group 3. Memory 3. Memory Special Function Registers (SFRs) are allocated from address 00000h to 003FFh and from 0D000h to 0D7FFh. Peripheral function control registers are located here. All blank spaces within SFRs are reserved, so do not access any blank spaces. The internal RAM is allocated from address 00400h to superior direction. For example, a 8-Kbyte internal RAM is addressed from 00400h to 023FFh. The internal RAM is used not only for data storage but also for stack area when subroutines are called or when interrupt request are acknowledged. The internal ROM is flash memory. Three internal ROM areas are available: data flash, program ROM 1, and program ROM 2. The data flash is addressed from 0E000h to 0FFFFh. This data flash space is used not only for data storage but also for program storage. Program ROM 2 is assigned addresses 10000h to 13FFFh. Program ROM 1 is assigned addresses FFFFFh to inferior direction. For example, the 64-Kbyte program ROM 1 space has addresses F0000h to FFFFFh. The special page vectors are assigned addresses FFE00h to FFFD7h. They are used for the JMPS instruction and JSRS instruction. Refer to the M16C/60, M16C/20, M16C/Tiny Series Software Manual for details. The fixed vector table for interrupts, ID code write address, OFS1 address and OSF2 address are assigned addresses FFFDBh to FFFFFh. The 256 bytes beginning with the start address set in the INTB register compose the relocatable vector table for interrupts. 00000h 00400h XXXXXh SFRs Internal RAM Reserved 0D000h 0D800h 0E000h Internal RAM Capacity 4 Kbytes 8 Kbytes 12 Kbytes 20 Kbytes XXXXXh 013FFh 023FFh 033FFh 053FFh 10000h 14000h SFRs Reserved Internal ROM (Data flash) Internal ROM (Program ROM 2) 13000h 13FF0h User boot code area 13FFFh On-chip debugger monitor area Reserved Relocatable vector table 256 bytes beginning with the start address set in the INTB register Internal ROM Capacity 64 Kbytes 96 Kbytes 128 Kbytes 256 Kbytes YYYYYh F0000h E8000h E0000h C0000h FFFFFh YYYYYh Internal ROM (Program ROM 1) FFE00h FFFD8h FFFDBh Special page vector table Reserved Fixed vector table ID code address OFS1 address, OFS2 address FFFFFh Notes: 1. Do not access the reserved areas. 2. The figure above applies under the following conditions: -The PM10 bit in the PM1 register is set to 1 (addresses from 0E000h to 0FFFFh are used as data flash) -The PRG2C0 bit in the PRG2C register is set to 0 (program ROM 2 enabled) Figure 3.1 Memory Map REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 22 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) 4. 4.1 Special Function Registers (SFRs) SFRs An SFR is a control register for a peripheral function. Table 4.1 SFR List (1) to Table 4.35 SFR List (35) list SFR information. Table 4.1 Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh SFR List (1) Register Symbol Reset Value Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 PM0 PM1 CM0 CM1 00h 0000 1000b 0100 1000b 0010 0000b Protect Register Oscillation Stop Detection Register PRCR CM2 00h 0X00 0010b (2) Program 2 Area Control Register Peripheral Clock Select Register PRG2C PCLKR XXXX XX00b 0000 0011b Clock Prescaler Reset Flag CPSRF 0XXX XXXXb Reset Source Determine Register Voltage Detector 2 Flag Register Voltage Detector Operation Enable Register RSTFR VCR1 VCR2 XX0X 001Xb (Hardware Reset) (3) 0000 1000b (1) 000X 0000b (1, 4) 001X 0000b (1, 5) 0X01 X010b XX00 0X01b PLL Control Register 0 Processor Mode Register 2 PLC0 PM2 X: Undefined Blanks are reserved. No access is allowed. Notes: 1. Software reset, watchdog timer reset, oscillation stop detection reset, and voltage monitor 2 reset do not affect registers: VCR1 and VCR2. 2. Oscillation stop detection reset does not affect bits CM20, CM21, and CM27. 3. The state of the bits in the RSTFR register depends on the reset type. 4. When the LVDAS bit of address OFS1 is 1 at hardware reset. 5. This value shows the value after a voltage monitor 0 reset, power-on reset or when the LVDAS bit of address OFS1 is 0 at hardware reset. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 23 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.2 SFR List (2) Symbol Reset Value Address Register 0020h 0021h 0022h 0023h 0024h 0025h 0026h Voltage Monitor Function Select Register 0027h 0028h Voltage Detector 2 Level Select Register 0029h 002Ah 002Bh 002Ch Voltage Monitor 2 Control Register Voltage Monitor 0 Control Register VWCE VD2LS 00h 0000 0100b (1) 1100 1X10b (2, 3) 1100 1X11b (2, 4) 1000 0X10b (2, 5) VW0C VW2C 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh X: Undefined Blanks are reserved. No access is allowed. Notes: 1. Hardware reset, power-on reset, voltage monitor 0 reset, or voltage monitor 2 reset. 2. Software reset, watchdog timer reset, oscillation stop detection reset, voltage monitor 0 reset, and voltage monitor 2 reset do not affect the VW0C register or bits VW2C2 and VW2C3 in the VW2C register. 3. When the LVDAS bit of address OFS1 is 1 at hardware reset. 4. This value shows the value after a voltage monitor 0 reset, power-on reset, or when the LVDAS bit of address OFS1 is 0 at hardware reset. 5. Hardware reset, power-on reset, or voltage monitor 0 reset. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 24 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.3 Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh SFR List (3) Register Symbol Reset Value INT3 Interrupt Control Register INT3IC XX00 X000b INT5 Interrupt Control Register INT4 Interrupt Control Register UART2 Bus Collision Detection Interrupt Control Register, Task Monitoring Timer Interrupt Control Register DMA0 Interrupt Control Register DMA1 Interrupt Control Register Key Input Interrupt Control Register, A/D 1 Conversion Interrupt Control Register A/D Conversion Interrupt Control Register UART2 Transmit Interrupt Control Register UART2 Receive Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register Timer A0 Interrupt Control Register Timer A1 Interrupt Control Register Timer A2 Interrupt Control Register Timer A3 Interrupt Control Register Timer A4 Interrupt Control Register Timer B0 Interrupt Control Register Timer B1 Interrupt Control Register Timer B2 Interrupt Control Register INT0 Interrupt Control Register INT1 Interrupt Control Register INT2 Interrupt Control Register INT5IC INT4IC BCNIC, TMOSIC DM0IC DM1IC KUPIC, ADEIC ADIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC TB2IC INT0IC INT1IC INT2IC XX00 X000b XX00 X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XX00 X000b XX00 X000b XX00 X000b DMA2 Interrupt Control Register DMA3 Interrupt Control Register DM2IC DM3IC XXXX X000b XXXX X000b UART4 Transmit Interrupt Control Register, Real-Time Clock Compare Interrupt Control Register X: Undefined Blanks are reserved. No access is allowed. 006Fh S4TIC, RTCCIC XXXX X000b REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 25 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.4 SFR List (4) Symbol S4RIC C0WIC S3TIC, C0EIC S3RIC RTCTIC C0RIC C0TIC C0FRIC C0FTIC ICOC0IC ICOCH0IC ICOC1IC, IICIC ICOCH1IC, SCLDAIC ICOCH2IC ICOCH3IC BTIC Reset Value XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b Address Register 0070h UART4 Receive Interrupt Control Register 0071h CAN0 Wakeup Interrupt Control Register UART3 Transmit Interrupt Control Register, 0072h CAN0 Error Interrupt Control Register 0073h UART3 Receive Interrupt Control Register 0074h Real-Time Clock Cycle Interrupt Control Register 0075h CAN0 Receive Completion Interrupt Control Register 0076h CAN0 Transmit Completion Interrupt Control Register 0077h CAN0 Receive FIFO Interrupt Control Register 0078h CAN0 Transmit FIFO Interrupt Control Register 0079h IC/OC Interrupt 0 Control Register 007Ah IC/OC Channel 0 Interrupt Control Register IC/OC Interrupt 1 Control Register, 007Bh I2C-bus Interface Interrupt Control Register IC/OC Channel 1 Interrupt Control Register, 007Ch SCL/SDA Interrupt Control Register 007Dh IC/OC Channel 2 Interrupt Control Register 007Eh IC/OC Channel 3 Interrupt Control Register 007Fh IC/OC Base Timer Interrupt Control Register 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h to 012Fh X: Undefined Blanks are reserved. No access is allowed. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 26 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.5 SFR List (5) Symbol Reset Value Address Register 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh 0140h A/D1 Register 0 0141h 0142h A/D1 Register 1 0143h 0144h A/D1 Register 2 0145h 0146h A/D1 Register 3 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h A/D1 Trigger Control Register 0153h 0154h A/D1 Control Register 2 0155h 0156h A/D1 Control Register 0 0157h A/D1 Control Register 1 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh X: Undefined Blanks are reserved. No access is allowed. AD10 AD11 AD12 AD13 XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb AD1TRGCON AD1CON2 AD1CON0 AD1CON1 XXXX 00XXb 0000 X00Xb 0000 0XXXb 0000 X000b REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 27 of 83 M16C/5LD Group, M16C/56D Group Table 4.6 SFR List (6) 4. Special Function Registers (SFRs) Address Register 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh 0180h 0181h DMA0 Source Pointer 0182h 0183h 0184h 0185h DMA0 Destination Pointer 0186h 0187h 0188h DMA0 Transfer Counter 0189h 018Ah 018Bh 018Ch DMA0 Control Register 018Dh 018Eh 018Fh X: Undefined Blanks are reserved. No access is allowed. Symbol Reset Value SAR0 XXh XXh 0Xh XXh XXh 0Xh XXh XXh DAR0 TCR0 DM0CON 0000 0X00b REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 28 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.7 SFR List (7) Symbol SAR1 Reset Value XXh XXh 0Xh XXh XXh 0Xh XXh XXh Address Register 0190h 0191h DMA1 Source Pointer 0192h 0193h 0194h 0195h DMA1 Destination Pointer 0196h 0197h 0198h DMA1 Transfer Counter 0199h 019Ah 019Bh 019Ch DMA1 Control Register 019Dh 019Eh 019Fh 01A0h 01A1h DMA2 Source Pointer 01A2h 01A3h 01A4h 01A5h DMA2 Destination Pointer 01A6h 01A7h 01A8h DMA2 Transfer Counter 01A9h 01AAh 01ABh 01ACh DMA2 Control Register 01ADh 01AEh 01AFh 01B0h 01B1h DMA3 Source Pointer 01B2h 01B3h 01B4h 01B5h DMA3 Destination Pointer 01B6h 01B7h 01B8h DMA3 Transfer Counter 01B9h 01BAh 01BBh 01BCh DMA3 Control Register 01BDh 01BEh 01BFh X: Undefined Blanks are reserved. No access is allowed. DAR1 TCR1 DM1CON 0000 0X00b SAR2 XXh XXh 0Xh XXh XXh 0Xh XXh XXh DAR2 TCR2 DM2CON 0000 0X00b SAR3 XXh XXh 0Xh XXh XXh 0Xh XXh XXh DAR3 TCR3 DM3CON 0000 0X00b REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 29 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.8 SFR List (8) Symbol TB01 TB11 TB21 PPWFS1 TBCS0 TBCS1 Reset Value XXh XXh XXh XXh XXh XXh XXXX X000b 00h X0h Address Register 01C0h Timer B0-1 Register 01C1h 01C2h Timer B1-1 Register 01C3h 01C4h Timer B2-1 Register 01C5h 01C6h Pulse Period/Width Measurement Mode Function Select Register 1 01C7h 01C8h Timer B Count Source Select Register 0 01C9h Timer B Count Source Select Register 1 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h Timer A Count Source Select Register 0 01D1h Timer A Count Source Select Register 1 01D2h Timer A Count Source Select Register 2 01D3h 01D4h 16-Bit Pulse Width Modulation Mode Function Select Register 01D5h Timer A Waveform Output Function Select Register 01D6h 01D7h 01D8h Timer A Output Waveform Change Enable Register 01D9h 01DAh Three-Phase Protect Control Register 01DBh 01DCh 01DDh 01DEh 01DFh 01E0h 01E1h 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh X: Undefined Blanks are reserved. No access is allowed. TACS0 TACS1 TACS2 PWMFS TAPOFS 00h 00h X0h 0XX0 X00Xb XXX0 0000b TAOW TPRC XXX0 X00Xb 00h REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 30 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.9 SFR List (9) Symbol TMOS TMOSSR TMOSCS TMOSPR Reset Value XXh XXh XXXX XXX0b XXXX 0000b 00h Address Register 01F0h Task Monitor Timer Register 01F1h 01F2h Task Monitor Timer Count Start Flag 01F3h Task Monitor Timer Count Source Select Register 01F4h Task Monitor Timer Protect Register 01F5h 01F6h 01F7h 01F8h 01F9h 01FAh 01FBh 01FCh 01FDh 01FEh 01FFh 0200h 0201h 0202h 0203h 0204h 0205h Interrupt Source Select Register 3 0206h Interrupt Source Select Register 2 0207h Interrupt Source Select Register 0208h 0209h 020Ah 020Bh 020Ch 020Dh 020Eh Address Match Interrupt Enable Register 020Fh Address Match Interrupt Enable Register 2 0210h 0211h Address Match Interrupt Register 0 0212h 0213h 0214h 0215h Address Match Interrupt Register 1 0216h 0217h 0218h 0219h Address Match Interrupt Register 2 021Ah 021Bh 021Ch 021Dh Address Match Interrupt Register 3 021Eh 021Fh X: Undefined Blanks are reserved. No access is allowed. IFSR3A IFSR2A IFSR 00h 00h 00h AIER AIER2 RMAD0 XXXX XX00b XXXX XX00b 00h 00h X0h 00h 00h X0h 00h 00h X0h 00h 00h X0h RMAD1 RMAD2 RMAD3 REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 31 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.10 Address 0220h SFR List (10) Register Symbol FMR0 FMR1 FMR2 FMR3 Reset Value 0000 0001b (Other than user boot mode) 0010 0001b (User boot mode) 00X0 XX0Xb XXXX 0000b XXXX 0000b Flash Memory Control Register 0 0221h Flash Memory Control Register 1 0222h Flash Memory Control Register 2 0223h Flash Memory Control Register 3 0224h 0225h 0226h 0227h 0228h 0229h 022Ah 022Bh 022Ch 022Dh 022Eh 022Fh 0230h Flash Memory Control Register 6 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023Ah 023Bh 023Ch 023Dh 023Eh 023Fh 0240h 0241h 0242h 0243h 0244h 0245h 0246h 0247h 0248h UART0 Transmit/Receive Mode Register 0249h UART0 Bit Rate Register 024Ah UART0 Transmit Buffer Register 024Bh 024Ch UART0 Transmit/Receive Control Register 0 024Dh UART0 Transmit/Receive Control Register 1 024Eh UART0 Receive Buffer Register 024Fh X: Undefined Blanks are reserved. No access is allowed. FMR6 XX0X XX00b U0MR U0BRG U0TB U0C0 U0C1 U0RB 00h XXh XXh XXh 0000 1000b 0000 0010b XXh XXh REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 32 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.11 SFR List (11) Symbol Reset Value Address Register 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h UART1 Transmit/Receive Mode Register 0259h UART1 Bit Rate Register 025Ah UART1 Transmit Buffer Register 025Bh 025Ch UART1 Transmit/Receive Control Register 0 025Dh UART1 Transmit/Receive Control Register 1 025Eh UART1 Receive Buffer Register 025Fh 0260h 0261h 0262h 0263h 0264h UART2 Special Mode Register 4 0265h UART2 Special Mode Register 3 0266h UART2 Special Mode Register 2 0267h UART2 Special Mode Register 0268h UART2 Transmit/Receive Mode Register 0269h UART2 Bit Rate Register 026Ah UART2 Transmit Buffer Register 026Bh 026Ch UART2 Transmit/Receive Control Register 0 026Dh UART2 Transmit/Receive Control Register 1 026Eh UART2 Receive Buffer Register 026Fh 0270h 0271h 0272h 0273h 0274h 0275h 0276h 0277h 0278h 0279h 027Ah 027Bh 027Ch 027Dh 027Eh 027Fh X: Undefined Blanks are reserved. No access is allowed. U1MR U1BRG U1TB U1C0 U1C1 U1RB 00h XXh XXh XXh 0000 1000b 0000 0010b XXh XXh U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB 00h 000X 0X0Xb X000 0000b X000 0000b 00h XXh XXh XXh 0000 1000b 0000 0010b XXh XXh REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 33 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.12 SFR List (12) Symbol Reset Value Address Register 0280h 0281h 0282h 0283h 0284h 0285h 0286h 0287h 0288h 0289h 028Ah 028Bh 028Ch 028Dh 028Eh 028Fh 0290h 0291h 0292h 0293h 0294h 0295h 0296h 0297h 0298h UART4 Transmit/Receive Mode Register 0299h UART4 Bit Rate Register 029Ah UART4 Transmit Buffer Register 029Bh 029Ch UART4 Transmit/Receive Control Register 0 029Dh UART4 Transmit/Receive Control Register 1 029Eh UART4 Receive Buffer Register 029Fh 02A0h 02A1h 02A2h 02A3h 02A4h 02A5h 02A6h 02A7h 02A8h UART3 Transmit/Receive Mode Register 02A9h UART3 Bit Rate Register 02AAh UART3 Transmit Buffer Register 02ABh 02ACh UART3 Transmit/Receive Control Register 0 02ADh UART3 Transmit/Receive Control Register 1 02AEh UART3 Receive Buffer Register 02AFh X: Undefined Blanks are reserved. No access is allowed. U4MR U4BRG U4TB U4C0 U4C1 U4RB 00h XXh XXh XXh 0000 1000b 0000 0010b XXh XXh U3MR U3BRG U3TB U3C0 U3C1 U3RB 00h XXh XXh XXh 0000 1000b 0000 0010b XXh XXh REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 34 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.13 SFR List (13) Symbol S00 S0D0 S1D0 S20 S2D0 S3D0 S4D0 S10 S11 S0D1 S0D2 Reset Value XXh 0000 000Xb 0000 0000b 00h 0001 1010b 0011 0000b 0000 0000b 0001 000Xb XXXX X000b 0000 000Xb 0000 000Xb Address Register 02B0h I2C0 Data Shift Register 02B1h 02B2h I2C0 Address Register 0 02B3h I2C0 Control Register 0 02B4h I2C0 Clock Control Register 02B5h I2C0 Start/Stop Condition Control Register 02B6h I2C0 Control Register 1 02B7h I2C0 Control Register 2 02B8h I2C0 Status Register 0 02B9h I2C0 Status Register 1 02BAh I2C0 Address Register 1 02BBh I2C0 Address Register 2 02BCh 02BDh 02BEh 02BFh 02C0h Time Measurement Register 0 02C1h Waveform Generation Register 0 02C2h Time Measurement Register 1 02C3h Waveform Generation Register 1 02C4h Time Measurement Register 2 02C5h Waveform Generation Register 2 02C6h Time Measurement Register 3 02C7h Waveform Generation Register 3 02C8h Time Measurement Register 4 02C9h Waveform Generation Register 4 02CAh Time Measurement Register 5 02CBh Waveform Generation Register 5 02CCh Time Measurement Register 6 02CDh Waveform Generation Register 6 02CEh Time Measurement Register 7 02CFh Waveform Generation Register 7 02D0h Waveform Generation Control Register 0 02D1h Waveform Generation Control Register 1 02D2h Waveform Generation Control Register 2 02D3h Waveform Generation Control Register 3 02D4h Waveform Generation Control Register 4 02D5h Waveform Generation Control Register 5 02D6h Waveform Generation Control Register 6 02D7h Waveform Generation Control Register 7 02D8h Time Measurement Control Register 0 02D9h Time Measurement Control Register 1 02DAh Time Measurement Control Register 2 02DBh Time Measurement Control Register 3 02DCh Time Measurement Control Register 4 02DDh Time Measurement Control Register 5 02DEh Time Measurement Control Register 6 02DFh Time Measurement Control Register 7 X: Undefined Blanks are reserved. No access is allowed. G1TM0 G1PO0 G1TM1 G1PO1 G1TM2 G1PO2 G1TM3 G1PO3 G1TM4 G1PO4 G1TM5 G1PO5 G1TM6 G1PO6 G1TM7 G1PO7 G1POCR0 G1POCR1 G1POCR2 G1POCR3 G1POCR4 G1POCR5 G1POCR6 G1POCR7 G1TMCR0 G1TMCR1 G1TMCR2 G1TMCR3 G1TMCR4 G1TMCR5 G1TMCR6 G1TMCR7 XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh 0X00 XX00b 0X00 XX00b 0X00 XX00b 0X00 XX00b 0X00 XX00b 0X00 XX00b 0X00 XX00b 0X00 XX00b 00h 00h 00h 00h 00h 00h 00h 00h REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 35 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.14 SFR List (14) Symbol G1BT G1BCR0 G1BCR1 G1TPR6 G1TPR7 G1FE G1FS G1BTRR G1DV G1OER G1IOR0 G1IOR1 G1IR G1IE0 G1IE1 Reset Value XXh XXh 00h 00h 00h 00h 00h 00h XXh XXh 00h 00h 00h 00h XXh 00h 00h Address Register 02E0h Base Timer Register 02E1h 02E2h Base Timer Control Register 0 02E3h Base Timer Control Register 1 02E4h Time Measurement Prescaler Register 6 02E5h Time Measurement Prescaler Register 7 02E6h Function Enable Register 02E7h Function Select Register 02E8h Base Timer Reset Register 02E9h 02EAh Count Source Divide Register 02EBh 02ECh Waveform Output Master Enable Register 02EDh 02EEh Timer S I/O Control Register 0 02EFh Timer S I/O Control Register 1 02F0h Interrupt Request Register 02F1h Interrupt Enable Register 0 02F2h Interrupt Enable Register 1 02F3h 02F4h 02F5h 02F6h 02F7h 02F8h 02F9h 02FAh 02FBh 02FCh 02FDh 02FEh NMI Digital Debounce Register 02FFh P1_7 Digital Debounce Register 0300h 0301h 0302h Timer A1-1 Register 0303h 0304h Timer A2-1 Register 0305h 0306h Timer A4-1 Register 0307h 0308h Three-Phase PWM Control Register 0 0309h Three-Phase PWM Control Register 1 030Ah Three-Phase Output Buffer Register 0 030Bh Three-Phase Output Buffer Register 1 030Ch Dead Time Timer 030Dh Timer B2 Interrupt Generating Frequency Set Counter 030Eh Position-Data-Retain Function Control Register 030Fh X: Undefined Blanks are reserved. No access is allowed. NDDR P17DDR FFh FFh TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2 PDRF XXh XXh XXh XXh XXh XXh 00h 00h XX11 1111b XX11 1111b XXh XXh XXXX 0000b REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 36 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.15 SFR List (15) Symbol Reset Value Address Register 0310h 0311h 0312h 0313h 0314h 0315h 0316h 0317h 0318h Port Function Control Register 0319h 031Ah 031Bh 031Ch 031Dh 031Eh 031Fh 0320h Count Start Flag 0321h 0322h One-Shot Start Flag 0323h Trigger Select Register 0324h Increment/Decrement Flag 0325h 0326h Timer A0 Register 0327h 0328h Timer A1 Register 0329h 032Ah Timer A2 Register 032Bh 032Ch Timer A3 Register 032Dh 032Eh Timer A4 Register 032Fh 0330h Timer B0 Register 0331h 0332h Timer B1 Register 0333h 0334h Timer B2 Register 0335h 0336h Timer A0 Mode Register 0337h Timer A1 Mode Register 0338h Timer A2 Mode Register 0339h Timer A3 Mode Register 033Ah Timer A4 Mode Register 033Bh Timer B0 Mode Register 033Ch Timer B1 Mode Register 033Dh Timer B2 Mode Register 033Eh Timer B2 Special Mode Register 033Fh X: Undefined Blanks are reserved. No access is allowed. PFCR 0011 1111b TABSR ONSF TRGSR UDF 00h 00h 00h 00h XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh 00h 00h 00h 00h 00h 00XX 0000b 00XX 0000b 00XX 0000b X000 0000b TA0 TA1 TA2 TA3 TA4 TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 37 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.16 SFR List (16) Symbol RTCSEC RTCMIN RTCHR RTCWK RTCCR1 RTCCR2 RTCCSR RTCCSEC RTCCMIN RTCCHR Reset Value 00h X000 0000b XX00 0000b XXXX X000b 0000 X00Xb X000 0000b XXX0 0000b X000 0000b X000 0000b X000 0000b Address Register 0340h Real-Time Clock Second Data Register 0341h Real-Time Clock Minute Data Register 0342h Real-Time Clock Hour Data Register 0343h Real-Time Clock Day Data Register 0344h Real-Time Clock Control Register 1 0345h Real-Time Clock Control Register 2 0346h Real-Time Clock Count Source Select Register 0347h 0348h Real-Time Clock Second Compare Data Register 0349h Real-Time Clock Minute Compare Data Register 034Ah Real-Time Clock Hour Compare Data Register 034Bh 034Ch 034Dh 034Eh 034Fh 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh 0360h Pull-Up Control Register 0 0361h Pull-Up Control Register 1 0362h Pull-Up Control Register 2 0363h 0364h 0365h 0366h Port Control Register 0367h 0368h 0369h 036Ah 036Bh 036Ch 036Dh 036Eh 036Fh X: Undefined Blanks are reserved. No access is allowed. PUR0 PUR1 PUR2 00h 00h 00h PCR 0XX0 0XX0b REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 38 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.17 SFR List (17) Symbol PACR Reset Value 0XXX X000b Address Register 0370h Pin Assignment Control Register 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch Count Source Protect Mode Register 037Dh Watchdog Timer Refresh Register 037Eh Watchdog Timer Start Register 037Fh Watchdog Timer Control Register 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 038Ch 038Dh 038Eh 038Fh 0390h DMA2 Source Select Register 0391h 0392h DMA3 Source Select Register 0393h 0394h 0395h 0396h 0397h 0398h DMA0 Source Select Register 0399h 039Ah DMA1 Source Select Register 039Bh 039Ch 039Dh 039Eh 039Fh X: Undefined Blanks are reserved. No access is allowed. CSPR WDTR WDTS WDC 00h (1) XXh XXh 00XX XXXXb DM2SL DM3SL 00h 00h DM0SL DM1SL 00h 00h Note: 1. When the CSPROINI bit of the OFS1 address is 0, the reset value is 1000 0000b. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 39 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.18 Address 03A0h 03A1h 03A2h 03A3h 03A4h 03A5h 03A6h 03A7h 03A8h 03A9h 03AAh 03ABh 03ACh 03ADh 03AEh 03AFh 03B0h 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h 03B9h 03BAh 03BBh 03BCh 03BDh 03BEh 03BFh SFR List (18) Register Symbol Reset Value SFR Snoop Address Register CRC Mode Register CRCSAR CRCMR XXXX XXXXb 00XX XXXXb 0XXX XXX0b CRC Data Register CRC Input Register CRCD CRCIN XXh XXh XXh XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb 03C0h A/D Register 0 03C1h 03C2h A/D Register 1 03C3h 03C4h A/D Register 2 03C5h 03C6h A/D Register 3 03C7h 03C8h A/D Register 4 03C9h 03CAh A/D Register 5 03CBh 03CCh A/D Register 6 03CDh 03CEh A/D Register 7 03CFh X: Undefined Blanks are reserved. No access is allowed. AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 40 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.19 SFR List (19) Symbol Reset Value Address Register 03D0h 03D1h 03D2h A/D Trigger Control Register 03D3h 03D4h A/D Control Register 2 03D5h 03D6h A/D Control Register 0 03D7h A/D Control Register 1 03D8h 03D9h 03DAh 03DBh 03DCh 03DDh 03DEh 03DFh 03E0h Port P0 Register 03E1h Port P1 Register 03E2h Port P0 Direction Register 03E3h Port P1 Direction Register 03E4h Port P2 Register 03E5h Port P3 Register 03E6h Port P2 Direction Register 03E7h Port P3 Direction Register 03E8h 03E9h 03EAh 03EBh 03ECh Port P6 Register 03EDh Port P7 Register 03EEh Port P6 Direction Register 03EFh Port P7 Direction Register 03F0h Port P8 Register 03F1h Port P9 Register 03F2h Port P8 Direction Register 03F3h Port P9 Direction Register 03F4h Port P10 Register 03F5h 03F6h Port P10 Direction Register 03F7h 03F8h 03F9h 03FAh 03FBh 03FCh 03FDh 03FEh 03FFh 0400h to D4FFh X: Undefined Blanks are reserved. No access is allowed. ADTRGCON ADCON2 ADCON0 ADCON1 XXXX 00XXb 0000 X00Xb 0000 0XXXb 0000 X000b P0 P1 PD0 PD1 P2 P3 PD2 PD3 XXh XXh 00h 00h XXh XXh 00h 00h P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 PD10 XXh XXh 00h 00h XXh XXh 00h 000X 0000b XXh 00h REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 41 of 83 M16C/5LD Group, M16C/56D Group Table 4.20 SFR List (20) 4. Special Function Registers (SFRs) Address Register D500h D501h CAN0 Mailbox 0: Message Identifier D502h D503h D504h D505h CAN0 Mailbox 0: Data Length D506h D507h D508h D509h CAN0 Mailbox 0: Data Field D50Ah D50Bh D50Ch D50Dh D50Eh CAN0 Mailbox 0: Time Stamp D50Fh D510h D511h CAN0 Mailbox 1: Message Identifier D512h D513h D514h D515h CAN0 Mailbox 1: Data Length D516h D517h D518h D519h CAN0 Mailbox 1: Data Field D51Ah D51Bh D51Ch D51Dh D51Eh CAN0 Mailbox 1: Time Stamp D51Fh X: Undefined Blanks are reserved. No access is allowed. Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh C0MB0 C0MB1 REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 42 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.21 SFR List (21) Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Address Register D520h D521h CAN0 Mailbox 2: Message Identifier D522h D523h D524h D525h CAN0 Mailbox 2: Data Length D526h D527h D528h D529h CAN0 Mailbox 2: Data Field D52Ah D52Bh D52Ch D52Dh D52Eh CAN0 Mailbox 2: Time Stamp D52Fh D530h D531h CAN0 Mailbox 3: Message Identifier D532h D533h D534h D535h CAN0 Mailbox 3: Data Length D536h D537h D538h D539h CAN0 Mailbox 3: Data Field D53Ah D53Bh D53Ch D53Dh D53Eh CAN0 Mailbox 3: Time Stamp D53Fh D540h D541h CAN0 Mailbox 4: Message Identifier D542h D543h D544h D545h CAN0 Mailbox 4: Data Length D546h D547h D548h D549h CAN0 Mailbox 4: Data Field D54Ah D54Bh D54Ch D54Dh D54Eh CAN0 Mailbox 4: Time Stamp D54Fh X: Undefined Blanks are reserved. No access is allowed. C0MB2 C0MB3 C0MB4 REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 43 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.22 Address D550h D551h D552h D553h D554h D555h D556h D557h D558h D559h D55Ah D55Bh D55Ch D55Dh D55Eh D55Fh D560h D561h D562h D563h D564h SFR List (22) Register Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh CAN0 Mailbox 5: Message Identifier CAN0 Mailbox 5: Data Length C0MB5 CAN0 Mailbox 5: Data Field CAN0 Mailbox 5: Time Stamp CAN0 Mailbox 6: Message Identifier D565h CAN0 Mailbox 6: Data Length D566h D567h D568h D569h CAN0 Mailbox 6: Data Field D56Ah D56Bh D56Ch D56Dh D56Eh CAN0 Mailbox 6: Time Stamp D56Fh D570h D571h CAN0 Mailbox 7: Message Identifier D572h D573h D574h D575h CAN0 Mailbox 7: Data Length D576h D577h D578h D579h CAN0 Mailbox 7: Data Field D57Ah D57Bh D57Ch D57Dh D57Eh CAN0 Mailbox 7: Time Stamp D57Fh X: Undefined Blanks are reserved. No access is allowed. C0MB6 C0MB7 REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 44 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.23 SFR List (23) Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Address Register D580h D581h CAN0 Mailbox 8: Message Identifier D582h D583h D584h D585h CAN0 Mailbox 8: Data Length D586h D587h D588h D589h CAN0 Mailbox 8: Data Field D58Ah D58Bh D58Ch D58Dh D58Eh CAN0 Mailbox 8: Time Stamp D58Fh D590h D591h CAN0 Mailbox 9: Message Identifier D592h D593h D594h D595h CAN0 Mailbox 9: Data Length D596h D597h D598h D599h CAN0 Mailbox 9: Data Field D59Ah D59Bh D59Ch D59Dh D59Eh CAN0 Mailbox 9: Time Stamp D59Fh D5A0h D5A1h CAN0 Mailbox 10: Message Identifier D5A2h D5A3h D5A4h D5A5h CAN0 Mailbox 10: Data Length D5A6h D5A7h D5A8h D5A9h CAN0 Mailbox 10: Data Field D5AAh D5ABh D5ACh D5ADh D5AEh CAN0 Mailbox 10: Time Stamp D5AFh X: Undefined Blanks are reserved. No access is allowed. C0MB8 C0MB9 C0MB10 REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 45 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.24 SFR List (24) Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Address Register D5B0h D5B1h CAN0 Mailbox 11: Message Identifier D5B2h D5B3h D5B4h D5B5h CAN0 Mailbox 11: Data Length D5B6h D5B7h D5B8h D5B9h CAN0 Mailbox 11: Data Field D5BAh D5BBh D5BCh D5BDh D5BEh CAN0 Mailbox 11: Time Stamp D5BFh D5C0h D5C1h CAN0 Mailbox 12: Message Identifier D5C2h D5C3h D5C4h D5C5h CAN0 Mailbox 12: Data Length D5C6h D5C7h D5C8h D5C9h CAN0 Mailbox 12: Data Field D5CAh D5CBh D5CCh D5CDh D5CEh CAN0 Mailbox 12: Time Stamp D5CFh D5D0h D5D1h CAN0 Mailbox 13: Message Identifier D5D2h D5D3h D5D4h D5D5h CAN0 Mailbox 13: Data Length D5D6h D5D7h D5D8h D5D9h CAN0 Mailbox 13: Data Field D5DAh D5DBh D5DCh D5DDh D5DEh CAN0 Mailbox 13: Time Stamp D5DFh X: Undefined Blanks are reserved. No access is allowed. C0MB11 C0MB12 C0MB13 REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 46 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.25 SFR List (25) Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Address Register D5E0h D5E1h CAN0 Mailbox 14: Message Identifier D5E2h D5E3h D5E4h D5E5h CAN0 Mailbox 14: Data Length D5E6h D5E7h D5E8h D5E9h CAN0 Mailbox 14: Data Field D5EAh D5EBh D5ECh D5EDh D5EEh CAN0 Mailbox 14: Time Stamp D5EFh D5F0h D5F1h CAN0 Mailbox 15: Message Identifier D5F2h D5F3h D5F4h D5F5h CAN0 Mailbox 15: Data Length D5F6h D5F7h D5F8h D5F9h CAN0 Mailbox 15: Data Field D5FAh D5FBh D5FCh D5FDh D5FEh CAN0 Mailbox 15: Time Stamp D5FFh X: Undefined Blanks are reserved. No access is allowed. C0MB14 C0MB15 REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 47 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.26 SFR List (26) Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Address Register D600h D601h CAN0 Mailbox 16: Message Identifier D602h D603h D604h D605h CAN0 Mailbox 16: Data Length D606h D607h D608h D609h CAN0 Mailbox 16: Data Field D60Ah D60Bh D60Ch D60Dh D60Eh CAN0 Mailbox 16: Time Stamp D60Fh D610h D611h CAN0 Mailbox 17: Message Identifier D612h D613h D614h D615h CAN0 Mailbox 17: Data Length D616h D617h D618h D619h CAN0 Mailbox 17: Data Field D61Ah D61Bh D61Ch D61Dh D61Eh CAN0 Mailbox 17: Time Stamp D61Fh D620h D621h CAN0 Mailbox 18: Message Identifier D622h D623h D624h D625h CAN0 Mailbox 18: Data Length D626h D627h D628h D629h CAN0 Mailbox 18: Data Field D62Ah D62Bh D62Ch D62Dh D62Eh CAN0 Mailbox 18: Time Stamp D62Fh X: Undefined Blanks are reserved. No access is allowed. C0MB16 C0MB17 C0MB18 REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 48 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.27 SFR List (27) Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Address Register D630h D631h CAN0 Mailbox 19: Message Identifier D632h D633h D634h D635h CAN0 Mailbox 19: Data Length D636h D637h D638h D639h CAN0 Mailbox 19: Data Field D63Ah D63Bh D63Ch D63Dh D63Eh CAN0 Mailbox 19: Time Stamp D63Fh D640h D641h CAN0 Mailbox 20: Message Identifier D642h D643h D644h D645h CAN0 Mailbox 20: Data Length D646h D647h D648h D649h CAN0 Mailbox 20: Data Field D64Ah D64Bh D64Ch D64Dh D64Eh CAN0 Mailbox 20: Time Stamp D64Fh D650h D651h CAN0 Mailbox 21: Message Identifier D652h D653h D654h D655h CAN0 Mailbox 21: Data Length D656h D657h D658h D659h CAN0 Mailbox 21: Data Field D65Ah D65Bh D65Ch D65Dh D65Eh CAN0 Mailbox 21: Time Stamp D65Fh X: Undefined Blanks are reserved. No access is allowed. C0MB19 C0MB20 C0MB21 REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 49 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.28 SFR List (28) Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Address Register D660h D661h CAN0 Mailbox 22: Message Identifier D662h D663h D664h D665h CAN0 Mailbox 22: Data Length D666h D667h D668h D669h CAN0 Mailbox 22: Data Field D66Ah D66Bh D66Ch D66Dh D66Eh CAN0 Mailbox 22: Time Stamp D66Fh D670h D671h CAN0 Mailbox 23: Message Identifier D672h D673h D674h D675h CAN0 Mailbox 23: Data Length D676h D677h D678h D679h CAN0 Mailbox 23: Data Field D67Ah D67Bh D67Ch D67Dh D67Eh CAN0 Mailbox 23: Time Stamp D67Fh D680h D681h CAN0 Mailbox 24: Message Identifier D682h D683h D684h D685h CAN0 Mailbox 24: Data Length D686h D687h D688h D689h CAN0 Mailbox 24: Data Field D68Ah D68Bh D68Ch D68Dh D68Eh CAN0 Mailbox 24: Time Stamp D68Fh X: Undefined Blanks are reserved. No access is allowed. C0MB22 C0MB23 C0MB24 REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 50 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.29 SFR List (29) Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Address Register D690h D691h CAN0 Mailbox 25: Message Identifier D692h D693h D694h D695h CAN0 Mailbox 25: Data Length D696h D697h D698h D699h CAN0 Mailbox 25: Data Field D69Ah D69Bh D69Ch D69Dh D69Eh CAN0 Mailbox 25: Time Stamp D69Fh D6A0h D6A1h CAN0 Mailbox 26: Message Identifier D6A2h D6A3h D6A4h D6A5h CAN0 Mailbox 26: Data Length D6A6h D6A7h D6A8h D6A9h CAN0 Mailbox 26: Data Field D6AAh D6ABh D6ACh D6ADh D6AEh CAN0 Mailbox 26: Time Stamp D6AFh D6B0h D6B1h CAN0 Mailbox 27: Message Identifier D6B2h D6B3h D6B4h D6B5h CAN0 Mailbox 27: Data Length D6B6h D6B7h D6B8h D6B9h CCAN0 Mailbox 27: Data Field D6BAh D6BBh D6BCh D6BDh D6BEh CAN0 Mailbox 27: Time Stamp D6BFh X: Undefined Blanks are reserved. No access is allowed. C0MB25 C0MB26 C0MB27 REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 51 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.30 SFR List (30) Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Address Register D6C0h D6C1h CAN0 Mailbox 28: Message Identifier D6C2h D6C3h D6C4h D6C5h CAN0 Mailbox 28: Data Length D6C6h D6C7h D6C8h D6C9h CAN0 Mailbox 28: Data Field D6CAh D6CBh D6CCh D6CDh D6CEh CAN0 Mailbox 28: Time Stamp D6CFh D6D0h D6D1h CAN0 Mailbox 29: Message Identifier D6D2h D6D3h D6D4h D6D5h CAN0 Mailbox 29: Data Length D6D6h D6D7h D6D8h D6D9h CAN0 Mailbox 29: Data Field D6DAh D6DBh D6DCh D6DDh D6DEh CAN0 Mailbox 29: Time Stamp D6DFh D6E0h D6E1h CAN0 Mailbox 30: Message Identifier D6E2h D6E3h D6E4h D6E5h CAN0 Mailbox 30: Data Length D6E6h D6E7h D6E8h D6E9h CAN0 Mailbox 30: Data Field D6EAh D6EBh D6ECh D6EDh D6EEh CAN0 Mailbox 30: Time Stamp D6EFh X: Undefined Blanks are reserved. No access is allowed. C0MB28 C0MB29 C0MB30 REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 52 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.31 SFR List (31) Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Address Register D6F0h D6F1h CAN0 Mailbox 31: Message Identifier D6F2h D6F3h D6F4h D6F5h CAN0 Mailbox 31: Data Length D6F6h D6F7h D6F8h D6F9h CAN0 Mailbox 31: Data Field D6FAh D6FBh D6FCh D6FDh D6FEh CAN0 Mailbox 31: Time Stamp D6FFh D700h D701h CAN0 Mask Register 0 D702h D703h D704h D705h CAN0 Mask Register 1 D706h D707h D708h D709h CAN0 Mask Register 2 D70Ah D70Bh D70Ch D70Dh CAN0 Mask Register 3 D70Eh D70Fh D710h D711h CAN0 Mask Register 4 D712h D713h D714h D715h CAN0 Mask Register 5 D716h D717h D718h D719h CAN0 Mask Register 6 D71Ah D71Bh D71Ch D71Dh CAN0 Mask Register 7 D71Eh D71Fh X: Undefined Blanks are reserved. No access is allowed. C0MB31 C0MKR0 C0MKR1 C0MKR2 C0MKR3 C0MKR4 C0MKR5 C0MKR6 C0MKR7 REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 53 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.32 SFR List (32) Symbol Reset Value XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh Address Register D720h D721h CAN0 FIFO Receive ID Compare Register 0 D722h D723h D724h D725h CAN0 FIFO Receive ID Compare Register 1 D726h D727h D728h D729h CAN0 Mask Invalid Register D72Ah D72Bh D72Ch D72Dh CAN0 Mailbox Interrupt Enable Register D72Eh D72Fh D730h D731h D732h D733h D734h D735h D736h D737h D738h D739h D73Ah D73Bh D73Ch D73Dh D73Eh D73Fh D740h D741h D742h D743h D744h D745h D746h D747h D748h D749h D74Ah D74Bh D74Ch D74Dh D74Eh D74Fh D750h to D77Fh X: Undefined Blanks are reserved. No access is allowed. C0FIDCR0 C0FIDCR1 C0MKIVLR C0MIER REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 54 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.33 SFR List (33) Symbol Reset Value Address Register D780h D781h D782h D783h D784h D785h D786h D787h D788h D789h D78Ah D78Bh D78Ch D78Dh D78Eh D78Fh D790h D791h D792h D793h D794h D795h D796h D797h D798h D799h D79Ah D79Bh D79Ch D79Dh D79Eh D79Fh D7A0h CAN0 Message Control Register 0 D7A1h CAN0 Message Control Register 1 D7A2h CAN0 Message Control Register 2 D7A3h CAN0 Message Control Register 3 D7A4h CAN0 Message Control Register 4 D7A5h CAN0 Message Control Register 5 D7A6h CAN0 Message Control Register 6 D7A7h CAN0 Message Control Register 7 D7A8h CAN0 Message Control Register 8 D7A9h CAN0 Message Control Register 9 D7AAh CAN0 Message Control Register 10 D7ABh CAN0 Message Control Register 11 D7ACh CAN0 Message Control Register 12 D7ADh CAN0 Message Control Register 13 D7AEh CAN0 Message Control Register 14 D7AFh CAN0 Message Control Register 15 X: Undefined Blanks are reserved. No access is allowed. C0MCTL0 C0MCTL1 C0MCTL2 C0MCTL3 C0MCTL4 C0MCTL5 C0MCTL6 C0MCTL7 C0MCTL8 C0MCTL9 C0MCTL10 C0MCTL11 C0MCTL12 C0MCTL13 C0MCTL14 C0MCTL15 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 55 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.34 SFR List (34) Symbol C0MCTL16 C0MCTL17 C0MCTL18 C0MCTL19 C0MCTL20 C0MCTL21 C0MCTL22 C0MCTL23 C0MCTL24 C0MCTL25 C0MCTL26 C0MCTL27 C0MCTL28 C0MCTL29 C0MCTL30 C0MCTL31 C0CTLR C0STR Reset Value 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 0000 0101b 00h 0000 0101b 00h 00h 00h 00h 00h 1000 0000b XXh 1000 0000b XXh 00h 00h 00h 00h 00h XXh 1000 0000b 0000 0000b 00h 00h XXh XXh 00h Address Register D7B0h CAN0 Message Control Register 16 D7B1h CAN0 Message Control Register 17 D7B2h CAN0 Message Control Register 18 D7B3h CAN0 Message Control Register 19 D7B4h CAN0 Message Control Register 20 D7B5h CAN0 Message Control Register 21 D7B6h CAN0 Message Control Register 22 D7B7h CAN0 Message Control Register 23 D7B8h CAN0 Message Control Register 24 D7B9h CAN0 Message Control Register 25 D7BAh CAN0 Message Control Register 26 D7BBh CAN0 Message Control Register 27 D7BCh CAN0 Message Control Register 28 D7BDh CAN0 Message Control Register 29 D7BEh CAN0 Message Control Register 30 D7BFh CAN0 Message Control Register 31 D7C0h CAN0 Control Register D7C1h D7C2h CAN0 Status Register D7C3h D7C4h D7C5h CAN0 Bit Configuration Register D7C6h D7C7h CAN0 Clock Select Register D7C8h CAN0 Receive FIFO Control Register D7C9h CAN0 Receive FIFO Pointer Control Register D7CAh CAN0 Transmit FIFO Control Register D7CBh CAN0 Transmit FIFO pointer Control Register D7CCh CAN0 Error Interrupt Enable Register D7CDh CAN0 Error Interrupt Source Judge Register D7CEh CAN0 Receive Error Count Register D7CFh CAN0 Transmit Error Count Register D7D0h CAN0 Error Code Store Register D7D1h CAN0 Channel Search Support Register D7D2h CAN0 Mailbox Search Status Register D7D3h CAN0 Mailbox Search Mode Register D7D4h CAN0 Time Stamp Register D7D5h D7D6h CAN0 Acceptance Filter Support Register D7D7h D7D8h CAN0 Test Control Register D7D9h D7DAh D7DBh D7DCh D7DDh D7DEh D7DFh X: Undefined Blanks are reserved. No access is allowed. C0BCR C0CLKR C0RFCR C0RFPCR C0TFCR C0TFPCR C0EIER C0EIFR C0RECR C0TECR C0ECSR C0CSSR C0MSSR C0MSMR C0TSR C0AFSR C0TCR REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 56 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) Table 4.35 SFR List (35) Symbol Reset Value Address Register D7E0h D7E1h D7E2h D7E3h D7E4h D7E5h D7E6h D7E7h D7E8h D7E9h D7EAh D7EBh D7ECh D7EDh D7EEh D7EFh D7F0h D7F1h D7F2h D7F3h D7F4h D7F5h D7F6h D7F7h D7F8h D7F9h D7FAh D7FBh D7FCh D7FDh D7FEh D7FFh X: Undefined Blanks are reserved. No access is allowed. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 57 of 83 M16C/5LD Group, M16C/56D Group 4. Special Function Registers (SFRs) 4.2 4.2.1 Notes on SFRs Register Settings Table 4.36 lists Registers with Write-Only Bits and registers whose function differs between reading and writing. Set these registers with immediate values. When establishing the next value by altering the existing value, write the existing value to the RAM as well as to the registers. Transfer the next value to the register after making changes in the RAM. Table 4.36 Registers with Write-Only Bits Address 0249h 024Bh to 024Ah 0259h 025Bh to 025Ah 0269h 026Bh to 026Ah 0299h 029Bh to 029Ah 02A9h 02ABh to 02AAh 02B6h 02B8h 0303h to 0302h 0305h to 0304h 0307h to 0306h 030Ah 030Bh 030Ch 030Dh 0327h to 0326h 0329h to 0328h 032Bh to 032Ah 032Dh to 032Ch 032Fh to 032Eh 037Dh 037Eh D7C9h D7CBh Register Name UART0 Bit Rate Register UART0 Transmit Buffer Register UART1 Bit Rate Register UART1 Transmit Buffer Register UART2 Bit Rate Register UART2 Transmit Buffer Register UART4 Bit Rate Register UART4 Transmit Buffer Register UART3 Bit Rate Register UART3 Transmit Buffer Register I2C0 Control Register 1 I2C0 Status Register 0 Timer A1-1 Register Timer A2-1 Register Timer A4-1 Register Three-Phase Output Buffer Register 0 Three-Phase Output Buffer Register 1 Dead Time Timer Timer B2 Interrupt Generating Frequency Set Counter Timer A0 Register Timer A1 Register Timer A2 Register Timer A3 Register Timer A4 Register Watchdog Timer Refresh Register Watchdog Timer Start Register CAN0 Receive FIFO Pointer Control Register CAN0 Transmit FIFO pointer Control Register Symbol U0BRG U0TB U1BRG U1TB U2BRG U2TB U4BRG U4TB U3BRG U3TB S3D0 S10 TA11 TA21 TA41 IDB0 IDB1 DTT ICTB2 TA0 TA1 TA2 TA3 TA4 WDTR WDTS C0RFPCR C0TFPCR REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 58 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics 5. 5.1 Electrical Characteristics Electrical Characteristics (Common to 3 V and 5 V) Absolute Maximum Rating Absolute Maximum Ratings 5.1.1 Table 5.1 Symbol VCC AVCC VREF VI Characteristic Supply voltage Analog supply voltage Analog reference voltage Input voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7 XIN, RESET, CNVSS, VREF Output voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7 XOUT Condition VCC = AVCC VCC = AVCC Value -0.3 to 6.5 -0.3 to 6.5 −0.3 to VCC + 0.1 (1) Unit V V V -0.3 to VCC + 0.3 V VO -0.3 to VCC + 0.3 V Pd Topr Power consumption Operating While CPU operation temperature While flash memory range program and erase operation Storage temperature range -40°C ≤ Topr ≤ 85°C 300 -40 to 85 mW Programming area Data area 0 to 60 -40 to 85 -65 to 150 °C Tstg °C Note: 1. Maximum value is 6.5 V. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 59 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics 5.1.2 Table 5.2 Recommended Operating Conditions Operating Conditions (1) Value Min. 3.0 VCC 0 0 0.7 VCC 0.8 VCC When I2C-bus input level selected When SMBUS input level selected 0.7 VCC 2.1 0 0 When I2C-bus input level selected When SMBUS input level selected 0 0 VCC VCC VCC VCC 0.3 VCC 0.2 VCC 0.3 VCC 0.8 80.0 V V V V V V Typ. Max. 5.5 VCC = 2.7 V to 5.5 V, Topr = -40 to 85 °C unless otherwise specified. Symbol VCC AVCC VSS AVSS VIH Supply voltage Analog supply voltage Ground voltage Analog ground voltage High level P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0 input voltage to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7 XIN, RESET, CNVSS SDAMM, SCLMM Characteristic Unit V V V V V VIL Low level P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0 input voltage to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7 XIN, RESET, CNVSS SDAMM, SCLMM IOH(sum) High peak output current High level peak output current High level average output current (1) Low peak output current Low level peak output current Low level average output current (1) Sum of IOH(peak) at P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7 mA IOH(peak) -10.0 mA IOH(avg) -5.0 mA IOL(sum) Sum of IOL(peak) atP0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7 2 32.768 -80.0 mA IOL(peak) 10.0 mA IOL(avg) 5.0 mA f(XIN) f(XCIN) f(PLL) f(BCLK) tsu(PLL) Main clock input oscillation frequency (2) Sub clock oscillation oscillator frequency PLL clock oscillation frequency CPU operation frequency Wait time to stabilize PLL frequency synthesizer (2) 20 50 25 32 32 2 3 MHz kHz MHz MHz ms VCC = 2.7 V to 5.5 V VCC = 3.0 V to 5.5 V VCC = 5.0 V VCC = 3.0 V 10 10 2 Notes: 1. The mean output current is the mean value within 100ms. 2. Refer to “Figure 5.1 “Main clock input oscillation frequency, PLL clock oscillation frequency”” for the relationship between main clock oscillation frequency/PLL clock oscillation frequency and supply voltage. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 60 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics maximum operating frequency [MHz] Main clock input oscillation frequency maximum operating frequency [MHz] PLL clock oscillation frequency 32.0 25.0 20.0 10.0 10.0 2.0 0.0 2.7 5.5 0.0 2.7 3.0 5.5 Vcc [V] (main clock: no division) Vcc [V] (PLL clock oscillation) Figure 5.1 Main clock input oscillation frequency, PLL clock oscillation frequency Table 5.3 Recommended Operating Conditions (2/2) (1) VCC = 2.7 to 5.5 V, VSS = 0 V, and Topr = -40 to 85°C unless otherwise specified. The ripple voltage must not excess Vr(VCC) and/or dVr(VCC)/dt. Symbol Vr(VCC) Allowable ripple voltage Parameter VCC = 5.0 V VCC = 3.0 V dVr(VCC)/dt Ripple voltage falling gradient VCC = 5.0 V VCC = 3.0 V Standard Min. Typ. Max. 0.5 0.3 0.3 0.3 Unit Vp-p Vp-p V/ms V/ms Note: 1. The device is operationally guaranteed under these operating conditions. V CC Vr(VCC) Figure 5.2 Ripple Waveform REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 61 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics 5.1.3 A/D Conversion Characteristics . Table 5.4 A/D Conversion Characteristics (1, 3) VCC = AVCC = VREF = 3.0 to 5.5 V, VSS = AVSS = 0 V at Topr = -40 to 85°C unless otherwise specified Symbol —– INL Resolution Integral Non-Linearity Error Parameter Measuring Condition VREF = VCC VREF = VCC = 5.0 V (2) VREF = VCC = 3.3 V (2) —– Absolute Accuracy VREF = VCC = 5.0 V (2) VREF = VCC = 3.3 V (2) φAD A/D operating clock frequency 4.0 V ≤ VCC ≤ 5.5 V 3.2 V ≤ VCC ≤ 4.0 V 3.0 V ≤ VCC ≤ 3.2 V —– DNL —– —– tCONV tsamp VREF VIA Tolerance Level Impedance Differential Non-Linearity Error Offset Error Gain Error 10-bit Conversion Time Sampling time Reference Voltage Analog Input Voltage (4) (2) (2) (2) Standard Min. Typ. Max. 10 ±3 ±5 ±3 ±5 2 2 2 3 ±1 ±3 ±3 1.60 0.6 3.0 0 VCC VREF 25 16 10 Unit Bits LSB LSB LSB LSB MHz MHz MHz kΩ LSB LSB LSB μs μs V V VREF = VCC = 5V, φAD = 25 MHz Notes: 1. Use when AVCC = VCC 2. Flash memory rewrite disabled. Except for the analog input pin, set the pins to be measured as input ports and connect them to VSS. See Figure 5.3 “A/D Accuracy Measure Circuit”. 3. This applies when using A/D1 circuits, with the ADSTBY bit for the unused A/D converter set to 0 (A/D operation stopped (standby)). 4. When analog input voltage is over reference voltage, the result of A/D conversion is 3FFh. AN Analog input P0 to P10 AN: One of the analog input pin P0 to P10: I/O pins other than AN Figure 5.3 A/D Accuracy Measure Circuit REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 62 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics 5.1.4 Flash Memory Electrical Characteristics Table 5.5 CPU Clock When Operating Flash Memory (f(BCLK)) VCC = 2.7 to 5.5 V, at Topr = -40 to 85°C unless otherwise specified. Symbol f(SLOW_R) Parameter CPU rewrite mode Slow read mode Low current consumption read mode Data flash read 2.7 V < VCC ≤ 3.0 V 3.0 V < VCC ≤ 5.5 V fC(32.768) Conditions Standard Min. Typ. Max. 10 (1) 5 35 16 (3) Unit MHz MHz kHz MHz (2) 20 (2) Notes: 1. Set the PM17 bit in the PM1 register to 1 (one wait). 2. When the frequency is over this value, set the FMR17 bit in the FMR1 register to 0 (one wait) or the PM17 bit in the PM1 register to 1 (one wait) 3. Set the PM17 bit in the PM1 register to 1 (one wait). When using the 125 kHz on-chip oscillator clock or sub clock as the CPU clock source, a wait is not necessary. Table 5.6 Flash Memory (Program ROM 1, 2) Electrical Characteristics VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified. Symbol td(SR-SUS) tPS Parameter Conditions Standard Min. 1,000 (2) 150 70 0.2 4000 3000 3.0 5 + CPU clock × 3 cycles 0 20 30 + CPU clock × 1 cycle 2.7 Topr= -40 to 85°C 2.7 0 Ambient temperature = 55°C 20 5.5 5.5 60 50 Typ. Max. Unit times μs μs s ms μs ms μs V V °C μs year Program and erase cycles (1, 3, 4) VCC = 3.3 V, Topr = 25°C VCC = 3.3 V, Topr = 25°C Two words program time Lock bit program time Block erase time Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Suspend interval necessary for auto-erasure to complete (7) Time from suspend until erase restart Program, erase voltage Read voltage Program, erase temperature Flash Memory Circuit Stabilization Wait Time Data hold time (6) VCC = 3.3 V, Topr = 25°C VCC = 3.3 V, Topr = 25°C Notes: 1. Definition of program and erase cycles: The program and erase cycles refer to the number of per-block erasures. If the program and erase cycles are n (n = 1,000), each block can be erased n times. For example, if a 64 Kbyte block is erased after writing two word data 16,384 times, each to a different address, this counts as one program and erase cycles. Data cannot be written to the same address more than once without erasing the block (rewrite prohibited). 2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. It is advisable to retain data on the erasure cycles of each block and limit the number of erase operations to a certain number. 4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 5. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 6. The data hold time includes time that the power supply is off or the clock is not supplied. 7. After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request, the erase sequence cannot be completed. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 63 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics Table 5.7 Flash Memory (Data Flash) Electrical Characteristics VCC = 2.7 to 5.5 V at Topr = -40 to 85°C, unless otherwise specified. Symbol Parameter Program and erase cycles (1, 3, 4) Two words program time Lock bit program time Block erase time Conditions VCC = 3.3 V, Topr = 25°C VCC = 3.3 V, Topr = 25°C VCC = 3.3 V, Topr = 25°C VCC = 3.3 V, Topr = 25°C Standard Min. 10,000 (2) 300 140 0.2 4000 3000 3.0 5 + CPU clock × 3 cycles 0 20 30 + CPU clock × 1 cycle 2.7 2.7 −40 Ambient temperature = 55 °C 20 5.5 5.5 85 50 Typ. Max. Unit times μs μs s ms μs ms μs V V °C μs year td(SR-SUS) Time delay from suspend request until suspend tPS Interval from erase start/restart until following suspend request Suspend interval necessary for auto-erasure to complete (7) Time from suspend until erase restart Program, erase voltage Read voltage Program, erase temperature Flash Memory Circuit Stabilization Wait Time Data hold time (6) Notes: 1. Definition of program and erase cycles The program and erase cycles refer to the number of per-block erasures. If the program and erase cycles are n (n = 10,000), each block can be erased n times. For example, if a 4 Kbyte block is erased after writing two word data 1,024 times, each to a different address, this counts as one program and erase cycles. Data cannot be written to the same address more than once without erasing the block (rewrite prohibited). 2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 256 groups before erasing them all in one operation. In addition, averaging the erasure cycles between blocks A and B can further reduce the actual erasure cycles. It is also advisable to retain data on the erasure cycles of each block and limit the number of erase operations to a certain number. 4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 5. Customers desiring program and erase failure rate information should contact their Renesas technical support representative. 6. The data hold time includes time that the power supply is off or the clock is not supplied. 7. After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request, the erase sequence cannot be completed. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 64 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics 5.1.5 Voltage Detector and Power Supply Circuit Electrical Characteristics Table 5.8 Voltage Detector 0 Electrical Characteristics The measurement condition is VCC = 2.7 to 5.5 V, Topr = -40 to 85°C, unless otherwise specified. Symbol Vdet0 td(E-A) Parameter Voltage detection level Vdet0 Waiting time until voltage detector operation starts (1) Condition When VCC is falling. Standard Min. 2.70 Typ. 2.85 Max. 3.00 100 Unit V μs Notes: 1. Necessary time until the voltage detector operates when setting to 1 again after setting the VC25 bit in the VCR2 register to 0. Table 5.9 Voltage Detector 2 Electrical Characteristics The measurement condition is VCC = 2.7 to 5.5 V, Topr = -40 to 85°C, unless otherwise specified. Symbol Vdet2 td(E-A) 1. Parameter Voltage detection level Vdet2_4 Hysteresis width at the rising of VCC in voltage detector 2 Waiting time until voltage detector operation starts (1) Condition When VCC is falling Standard Min. 3.51 Typ. 3.81 0.15 100 Max. 4.11 Unit V V μs Necessary time until the voltage detector operates after setting to 1 again after setting the VC27 bit in the VCR2 register to 0. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 65 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics Table 5.10 Power-On Reset Circuit The measurement condition is Topr = -40 to 85°C, unless otherwise specified. Symbol trth tfth Vpor tw(por) Note: Parameter External power VCC rise gradient External power VCC fall gradient Voltage at which power-on reset enabled (1) Condition Standard Min. 2.0 Typ. Max. Unit 50000 mV/ms 50000 mV/ms 0.1 V ms Hold time at which power-on reset enabled 1.0 1. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS1 address to 0. Vdet0 External Power VCC Vpor tw(por) t rth t fth t rth Vdet0 Internal reset signal 1 fOCO-S 1 fOCO-S × 128 × 128 Figure 5.4 Power-On Reset Circuit Electrical Characteristics Table 5.11 Symbol td(P-R) td(R-S) td(W-S) Power Supply Circuit Timing Characteristics Parameter Measuring Condition Standard Min. Typ. Max. 5 300 150 Unit ms μs μs Time for Internal Power Supply Stabilization VCC = 3.0 V to 5.5V During Powering-On STOP Release Time Low Power Mode Wait Mode Release Time Note: 1. When VCC = 5 V. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 66 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics Time to stabilize internal supply voltage during powering-on t d(P-R) Recommended operating voltage VCC td(P-R) CPU clock t d(R-S) (a) Interrupt to exit from stop mode (b) Interrupt to exit from wait mode STOP release time Low power consumption mode wait mode exit time t d(W-S) CPU clock (a) (b) td(R-S) td(W-S) t d(E-A) Low voltage detection circuit operation start time VC25, VC27 Low voltage detection circuit Stop td(E-A) Operate Figure 5.5 Power Supply Circuit Timing Diagram 5.1.6 Oscillation Circuit Electrical Characteristics Table 5.12 125kHz On-chip Oscillator Oscillation Circuit Electrical Characteristics VCC = 2.7 to 5.5 V, Topr = −40 to 85°C, unless otherwise specified Symbol fOCO-S Characteristic 125-kHz on-chip oscillator oscillation frequency Condition Min. 100 Value Typ. 125 Max. 150 20 Unit kHz tsu(fOCO-S) Wait time until 125 kHz on-chip oscillator stabilizes 2.7 V ≤ VCC ≤ 5.5 V μs REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 67 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics 5.2 5.2.1 Electrical Characteristics (VCC = 5 V) Electrical Characteristics VCC = 5 V Table 5.13 Electrical Characteristics (1) Standard Min. Typ. Max. VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = -40 to 85°C, f(BCLK) = 32 MHz unless otherwise specified. Symbol Parameter P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7 HIGH POWER HIGH Output Voltage VOH HIGH Output Voltage XCOUT XOUT LOW POWER HIGH POWER LOW POWER Measuring Condition Unit VOH HIGH Output Voltage IOH=−5 mA VCC−2.0 VCC V VOH HIGH Output Voltage IOH = −200 μA IOH = −1 mA IOH = −0.5 mA With no load applied With no load applied VCC−−0.3 VCC−−2.0 VCC−−2.0 2.5 1.6 VCC V VCC VCC V V VOL LOW Output Voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7 HIGH POWER XOUT LOW POWER HIGH POWER LOW POWER IOL = 5 mA 2.0 V VOL LOW Output Voltage IOL = 200 μA 0.45 V LOW Output Voltage VOL LOW Output Voltage IOL = 1 mA IOL = 0.5 mA With no load applied With no load applied 0 0 2.0 V 2.0 V XCOUT VT+-VT- Hysteresis TA0IN to TA4IN, TB0IN to TB2IN, INT0 to INT5, NMI, ADTRG, CTS0 to CTS3, SCL2, SDA2, CLK0 to CLK4, TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD4, ZP, IDU, IDW, IDV, SD, INPC1_0 to INPC1_7, CRX0 RESET XIN P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7 XIN, RESET, CNVSS P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7 XIN, RESET, CNVSS P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7 0.2 2.5 V VT+-VTVT+-VT- Hysteresis Hysteresis 0.2 0.2 2.5 0.8 V V IIH HIGH Input Current VI = 5 V 5.0 μA IIL LOW Input Current VI = 0 V −5.0 μA RPULLUP Pull-Up Resistance VI = 0 V 30 50 170 kΩ RfXIN RfXCIN VRAM Feedback Resistance XIN Feedback Resistance XCIN RAM Retention Voltage At stop mode 2.0 1.5 15 MΩ MΩ V REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 68 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics VCC = 5 V Table 5.14 Electrical Characteristics (2) Topr = −40 to 85°C unless otherwise specified. Symbol Parameter Measuring Condition f(BCLK) = 32MHz, XIN = 8 MHz (square wave), PLL multiply-by-8 125-kHz on-chip oscillator operates High speed mode f(BCLK) = 20 MHz, XIN = 20 MHz (square wave), 125-KHz on-chip oscillator operates f(BCLK) = 16 MHz, XIN = 16 MHz (square wave), 125-KHz on-chip oscillator operates Power Supply Current 125-kHz on-chip oscillator (VCC =4.2V to 5.5 mode V) In single-chip mode, the output pins are open and Low power mode other pins are VSS Main clock stops 125-kHz on-chip oscillator operates Divide-by-8 FMR22 = FMR23 = 1 (Low-current consumption read mode) f(BCLK) = 32 kHz On Flash memory (1) FMR22 = FMR23 = 1 (Low-current consumption read mode) Main clock stops 125-kHz on-chip oscillator operates Peripheral clock operates Topr = 25°C Main clock stops 125-kHz on-chip oscillator operates Peripheral clock operates Topr = 85°C Topr = 25°C Topr = 85°C f(BCLK) = 10 MHz, PM17 = 1 (one wait) VCC = 5.0 V f(BCLK) = 10 MHz, PM17 = 1 (one wait) VCC = 5.0 V 160 μA Standard Min. Typ. 28 Max. 42 Unit mA 20 30 mA 16 mA 150 500 μA ICC 20 μA Wait mode 50 μA μA μA 18 45 20.0 30.0 3 6 30 Stop mode During flash memory program During flash memory erase Idet2 Idet0 Low Voltage Detection Dissipation Current Reset Area Detection Dissipation Current mA mA μA μA Note: 1. This indicates the memory in which the program to be executed exists. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 69 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics VCC = 5 V 5.2.2 Timing Requirements (Peripheral Functions and Others) Reset Input (RESET Input) Reset Input (RESET Input) Parameter RESET input low pulse width (VCC = 5 V, VSS = 0 V, at Topr = -40 to 85°C unless otherwise specified) 5.2.2.1 Table 5.15 Symbol tw(RSTL) Standard Min. 10 Max. Unit μs RESET input t w(RTSL) Figure 5.6 Reset Input (RESET Input) 5.2.2.2 Table 5.16 Symbol tc tw(H) tw(L) tr tf External Clock Input External Clock Input (XIN Input) (1) Parameter External Clock Input Cycle Time External Clock Input HIGH Pulse Width External Clock Input LOW Pulse Width External Clock Rise Time External Clock Fall Time Standard Min. Max. 50 20 20 9 9 Unit ns ns ns ns ns Note: 1. The condition is VCC = 3.0V to 5.0V XIN input tr t w(H) tf tc t w(L) Figure 5.7 External Clock Input (XIN Input) REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 70 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics VCC = 5 V Timing Requirements (VCC = 5 V, VSS = 0 V, at Topr = −40 to 85°C unless otherwise specified) 5.2.2.3 Table 5.17 Symbol tc(TA) tw(TAH) tw(TAL) Timer A Input Timer A Input (Counter Input in Event Counter Mode) Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. Max. 100 40 40 Standard Min. Max. 400 200 200 Unit ns ns ns Table 5.18 Symbol tc(TA) tw(TAH) tw(TAL) Timer A Input (Gating Input in Timer Mode) Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Unit ns ns ns Table 5.19 Symbol tc(TA) tw(TAH) tw(TAL) Timer A Input (External Trigger Input in One-shot Timer Mode) Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. Max. 200 100 100 Unit ns ns ns Table 5.20 Timer A Input (External Trigger Input in Pulse Width Modulation Mode and Programmable Output Mode) Parameter TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. Max. 100 100 Unit ns ns Symbol tw(TAH) tw(TAL) tc(TA) t w(TAH) TAiIN input t w(TAL) tc(UP) t w(UPH) TAiOUT input t w(UPL) Figure 5.8 Timer A Input REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 71 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics VCC = 5 V Timing Requirements (VCC = 5 V, VSS = 0 V, at Topr = −40 to 85°C unless otherwise specified) Table 5.21 Symbol tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) TAiIN Input Cycle Time TAiOUT Input Setup Time TAiIN Input Setup Time Timer A Input (Two-phase Pulse Input in Event Counter Mode) Parameter Standard Min. Max. 800 200 200 Unit ns ns ns Two-phase pulse input in event counter mode tc(TA) TAiIN input tsu(TAIN-TAOUT) TAiOUT input tsu(TAOUT-TAIN) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) Figure 5.9 Timer A Input (Two-Phase Pulse Input in Event Counter Mode) REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 72 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics VCC = 5 V Timing Requirements (VCC = 5 V, VSS = 0 V, at Topr = −40 to 85°C unless otherwise specified) 5.2.2.4 Table 5.22 Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Timer B Input Timer B Input (Counter Input in Event Counter Mode) Parameter TBiIN Input Cycle Time (counted on one edge) TBiIN Input HIGH Pulse Width (counted on one edge) TBiIN Input LOW Pulse Width (counted on one edge) TBiIN Input Cycle Time (counted on both edges) TBiIN Input HIGH Pulse Width (counted on both edges) TBiIN Input LOW Pulse Width (counted on both edges) Standard Min. 100 40 40 200 80 80 Max. Unit ns ns ns ns ns ns Table 5.23 Symbol tc(TB) tw(TBH) tw(TBL) Timer B Input (Pulse Period Measurement Mode) Parameter TBiIN Input Cycle Time TBiIN Input HIGH Pulse Width TBiIN Input LOW Pulse Width Standard Min. 400 200 200 Max. Unit ns ns ns Table 5.24 Symbol tc(TB) tw(TBH) tw(TBL) Timer B Input (Pulse Width Measurement Mode) Parameter TBiIN Input Cycle Time TBiIN Input HIGH Pulse Width TBiIN Input LOW Pulse Width Standard Min. 400 200 200 Max. Unit ns ns ns tc(TB) t w(TBH) TBiIN input t w(TBL) Figure 5.10 Timer B Input REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 73 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics VCC = 5 V Timing Requirements (VCC = 5 V, VSS = 0 V, at Topr = −40 to 85°C unless otherwise specified) 5.2.2.5 Table 5.25 Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Serial Interface Serial Interface Parameter CLKi Input Cycle Time CLKi Input HIGH Pulse Width CLKi Input LOW Pulse Width TXDi Output Delay Time TXDi Hold Time RXDi Input Setup Time RXDi Input Hold Time 0 70 90 Standard Min. 200 100 100 80 Max. Unit ns ns ns ns ns ns ns tc (CK) t w (CKH) CLKi t w (CKL) th (C-Q) TXDi td (C-Q) RXDi ts u(D-C) th (C-D) Figure 5.11 Serial Interface 5.2.2.6 Table 5.26 Symbol tw(INH) tw(INL) External Interrupt INTi Input External Interrupt INTi Input Parameter INTi Input HIGH Pulse Width INTi Input LOW Pulse Width Standard Min. 250 250 Max. Unit ns ns t w(INL) INTi input t w(INH) Figure 5.12 External Interrupt INTi Input REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 74 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics VCC = 5 V Timing Requirements (VCC = 5 V, VSS = 0 V, at Topr = −40 to 85°C unless otherwise specified) 5.2.2.7 Table 5.27 Symbol tBUF tHD;STA tLOW tR tHD;DAT tHIGH fF tsu;DAT tsu;STA tsu;STO Multi-master I2C-bus Multi-master I2C-bus Parameter Bus free time Hold time in start condition Hold time in SCL clock 0 status SCL, SDA signals’ rising time Data hold time Hold time in SCL clock 1 status SCL, SDA signals’ falling time Data setup time Setup time in restart condition Stop condition setup time 250 4.7 4.0 0 4.0 300 Standard Clock Mode Min. 4.7 4.0 4.7 1000 Max. High-speed Clock Mode Min. 1.3 0.6 1.3 20 + 0.1 Cb 0 0.6 20 + 0.1 Cb 100 0.6 0.6 300 300 0.9 Max. Unit μs μs μs ns μs μs ns ns μs μs SDA t BUF t HD;STA t LOW s t su;STO tR tF SCL p Sr p t HD;STA Figure 5.13 t HD;DTA t HIGH t su;DTA t su;STA Multi-master I2C-bus REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 75 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics 5.3 5.3.1 Electrical Characteristics (VCC = 3 V) Electrical Characteristics VCC = 3 V Table 5.28 Electrical Characteristics (1) Standard Min. VCC−0.5 VCC−0.5 VCC−0.5 2.5 1.6 Typ. Max. VCC VCC VCC VCC = 2.7 to 3.3V, VSS = 0 V at Topr = −40 to 85°C, f(BCLK)=25MHz unless otherwise specified. Symbol HIGH Output Voltage Parameter P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7 XOUT HIGH POWER LOW POWER HIGH POWER LOW POWER Measuring Condition Unit VOH IOH = −1 mA IOH = −0.1 mA IOH = −50 μA With no load applied With no load applied IOL = 1mA IOL = 0.1mA IOL = 50μA With no load applied With no load applied V HIGH Output Voltage VOH HIGH Output Voltage LOW Output Voltage V XCOUT V VOL P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7 XOUT HIGH POWER LOW POWER HIGH POWER LOW POWER 0.5 V LOW Output Voltage VOL LOW Output Voltage 0.5 0.5 0 0 V XCOUT V VT+-VT- Hysteresis TA0IN to TA4IN, TB0IN to TB2IN, INT0 to INT5, NMI, ADTRG, CTS0 to CTS3, SCL2, SDA2, CLK0 to CLK4, TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD4, ZP, IDU, IDW, IDV, SD, INPC1_0 to INPC1_7, CRX0 RESET 1.8 V VT+-VTVT+-VT- Hysteresis Hysteresis 1.8 0.8 V V XIN P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7 XIN, RESET, CNVSS P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7 XIN, RESET, CNVSS P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7 IIH HIGH Input Current VI = 3V 4.0 μA IIL LOW Input Current VI = 0V −4.0 μA RPULLUP RfXIN RfXCIN VRAM Pull-Up Resistance VI = 0V 50 100 500 kΩ MΩ MΩ V Feedback Resistance XIN Feedback Resistance XCIN RAM Retention Voltage At stop mode 2.0 3.0 25 REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 76 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics VCC = 3 V Table 5.29 Electrical Characteristics (2) Topr = −40 to 85°C unless otherwise specified. Symbol Parameter Measuring Condition f(BCLK) = 25MHz, XIN = 8 MHz (square wave), PLL multiply-by-8 125-kHz on-chip oscillator operates High speed mode f(BCLK) = 20 MHz, XIN = 20 MHz (square wave), 125-kHz on-chip oscillator operates f(BCLK) = 16 MHz, XIN = 16 MHz (square wave), 125-kHz on-chip oscillator operates Main clock stops 125-kHz on-chip oscillator operates Divide-by-8 FMR22 = FMR23 = 1 (Low-current consumption read mode) f(BCLK) = 32 kHz On Flash memory (1) FMR22 = FMR23 = 1 (Low-current consumption read mode) Main clock stops 125-kHz on-chip oscillator operates Peripheral clock operates Topr = 25°C Main clock stops 125-kHz on-chip oscillator operates Peripheral clock operates Topr = 85°C Topr = 25°C Topr = 85°C f(BCLK) = 10 MHz, PM17 = 1 (one wait) VCC = 3.0 V f(BCLK) = 10 MHz, PM17 = 1 (one wait) VCC = 3.0 V 160 μA Standard Min. Typ. 26 Max. 40 Unit mA 19 28 mA 15 mA ICC Power Supply Current (VCC = 3.0 V to 3.6 V) Low power mode In single-chip mode, the output pins are open and other pins are VSS Wait mode 125-kHz on-chip oscillator mode 150 500 μA 20 μA 50 μA μA μA 17 45 20.0 30.0 3 6 27 Stop mode During flash memory program During flash memory erase Idet2 Idet0 Low Voltage Detection Dissipation Current Reset Area Detection Dissipation Current mA mA μA μA Note: 1. This indicates the memory in which the program to be executed exists. REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 77 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics VCC = 3 V 5.3.2 Timing Requirements (Peripheral Functions and Others) Reset Input (RESET Input) Reset Input (RESET Input) Parameter RESET input low pulse width (VCC = 3 V, VSS = 0 V, at Topr = -40 to 85°C unless otherwise specified) 5.3.2.1 Table 5.30 Symbol tw(RSTL) Standard Min. 10 Max. Unit μs RESET input t w(RTSL) Figure 5.14 Reset Input (RESET Input) 5.3.2.2 Table 5.31 Symbol tc tw(H) tw(L) tr tf External Clock Input External Clock Input (XIN input) (1) Parameter External Clock Input Cycle Time External Clock Input HIGH Pulse Width External Clock Input LOW Pulse Width External Clock Rise Time External Clock Fall Time Standard Min. Max. 50 20 20 9 9 Unit ns ns ns ns ns Note: 1. The condition is VCC = 2.7V to 3.0V. XIN input tr t w(H) tf tc t w(L) Figure 5.15 External Clock Input (XIN Input) REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 78 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics VCC = 3 V Timing Requirements (VCC = 3 V, VSS = 0 V, at Topr = −40 to 85°C unless otherwise specified) 5.3.2.3 Table 5.32 Symbol tc(TA) tw(TAH) tw(TAL) Timer A Input Timer A Input (Counter Input in Event Counter Mode) Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. Max. 150 60 60 Unit ns ns ns Table 5.33 Symbol tc(TA) tw(TAH) tw(TAL) Timer A Input (Gating Input in Timer Mode) Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. Max. 600 300 300 Unit ns ns ns Table 5.34 Symbol tc(TA) tw(TAH) tw(TAL) Timer A Input (External Trigger Input in One-shot Timer Mode) Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. Max. 300 150 150 Unit ns ns ns Table 5.35 Timer A Input (External Trigger Input in Pulse Width Modulation Mode and Programmable Output Mode) Parameter TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. Max. 150 150 Unit ns ns Symbol tw(TAH) tw(TAL) tc(TA) t w(TAH) TAiIN input t w(TAL) tc(UP) t w(UPH) TAiOUT input t w(UPL) Figure 5.16 Timer A Input REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 79 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics VCC = 3 V Timing Requirements (VCC = 3 V, VSS = 0 V, at Topr = −40 to 85°C unless otherwise specified) Table 5.36 Symbol tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) TAiIN Input Cycle Time TAiOUT Input Setup Time TAiIN Input Setup Time Timer A Input (Two-phase Pulse Input in Event Counter Mode) Parameter Standard Min. Max. 2 500 500 Unit μs ns ns Two-phase pulse input in event counter mode tc(TA) TAiIN input tsu(TAIN-TAOUT) TAiOUT input tsu(TAOUT-TAIN) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) Figure 5.17 Timer A Input (Two-Phase Pulse Input in Event Counter Mode) REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 80 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics VCC = 3 V Timing Requirements (VCC = 3 V, VSS = 0 V, at Topr = −40 to 85°C unless otherwise specified) 5.3.2.4 Table 5.37 Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Timer B Input Timer B Input (Counter Input in Event Counter Mode) Parameter TBiIN Input Cycle Time (counted on one edge) TBiIN Input HIGH Pulse Width (counted on one edge) TBiIN Input LOW Pulse Width (counted on one edge) TBiIN Input Cycle Time (counted on both edges) TBiIN Input HIGH Pulse Width (counted on both edges) TBiIN Input LOW Pulse Width (counted on both edges) Standard Min. 150 60 60 300 120 120 Max. Unit ns ns ns ns ns ns Table 5.38 Symbol tc(TB) tw(TBH) tw(TBL) Timer B Input (Pulse Period Measurement Mode) Parameter TBiIN Input Cycle Time TBiIN Input HIGH Pulse Width TBiIN Input LOW Pulse Width Standard Min. 600 300 300 Max. Unit ns ns ns Table 5.39 Symbol tc(TB) tw(TBH) tw(TBL) Timer B Input (Pulse Width Measurement Mode) Parameter TBiIN Input Cycle Time TBiIN Input HIGH Pulse Width TBiIN Input LOW Pulse Width Standard Min. 600 300 300 Max. Unit ns ns ns tc(TB) t w(TBH) TBiIN input t w(TBL) Figure 5.18 Timer B Input REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 81 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics VCC = 3 V Timing Requirements (VCC = 3 V, VSS = 0 V, at Topr = −40 to 85°C unless otherwise specified) 5.3.2.5 Table 5.40 Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Serial Interface Serial Interface Parameter CLKi Input Cycle Time CLKi Input HIGH Pulse Width CLKi Input LOW Pulse Width TXDi Output Delay Time TXDi Hold Time RXDi Input Setup Time RXDi Input Hold Time 0 100 90 Standard Min. 300 150 150 160 Max. Unit ns ns ns ns ns ns ns tc (CK) t w (CKH) CLKi t w (CKL) th (C-Q) TXDi td (C-Q) RXDi ts u(D-C) th (C-D) Figure 5.19 Serial Interface 5.3.2.6 Table 5.41 Symbol tw(INH) tw(INL) External Interrupt INTi Input External Interrupt INTi Input Parameter INTi Input HIGH Pulse Width INTi Input LOW Pulse Width Standard Min. 380 380 Max. Unit ns ns t w(INL) INTi input t w(INH) Figure 5.20 External Interrupt INTi Input REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 82 of 83 M16C/5LD Group, M16C/56D Group 5. Electrical Characteristics VCC = 3 V Timing Requirements (VCC = 3 V, VSS = 0 V, at Topr = −40 to 85°C unless otherwise specified) 5.3.2.7 Table 5.42 Symbol tBUF tHD;STA tLOW tR tHD;DAT tHIGH fF tsu;DAT tsu;STA tsu;STO Multi-master I2C-bus Multi-master I2C-bus Parameter Bus free time Hold time in start condition Hold time in SCL clock 0 status SCL, SDA signals’ rising time Data hold time Hold time in SCL clock 1 status SCL, SDA signals’ falling time Data setup time Setup time in restart condition Stop condition setup time 250 4.7 4.0 0 4.0 300 Standard Clock Mode Min. 4.7 4.0 4.7 1000 Max. High-speed Clock Mode Min. 1.3 0.6 1.3 20 + 0.1 Cb 0 0.6 20 + 0.1 Cb 100 0.6 0.6 300 300 0.9 Max. Unit μs μs μs ns μs μs ns ns μs μs SDA t BUF t HD;STA t LOW s t su;STO tR tF SCL p Sr p t HD;STA t HD;DTA t HIGH t su;DTA t su;STA Figure 5.21 Multi-master I2C-bus REJ03B0307-0110 Rev.1.10 Dec 01, 2009 Page 83 of 83 REVISION HISTORY Rev. 1.10 Date Dec. 01, 2009 Page — M16C/5LD Group, M16C/56D Group Datasheet Revision History First Edition issued All trademarks and registered trademarks are the property of their respective owners. IEBus is a trademark of NEC Electronics Corporation. A- 1 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. 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