Datasheet
M16C/65C Group
RENESAS MCU
1.
R01DS0015EJ0110
Rev.1.10
Jul 31, 2012
Overview
1.1
Features
The M16C/65C Group microcomputer (MCU) incorporates the M16C/60 Series CPU core and flash
memory, employing sophisticated instructions for a high level of efficiency. This MCU has 1 MB of address
space (expandable to 4 MB), and it is capable of executing instructions at high speed. In addition, the
CPU core boasts a multiplier for high-speed operation processing.
This MCU consumes low power, and supports operating modes that allow additional power control. The
MCU also uses an anti-noise configuration to reduce emissions of electromagnetic noise and is designed
to withstand electromagnetic interference (EMI). By integrating many of the peripheral functions, including
the multifunction timer and serial interface, the number of system components has been reduced.
1.1.1
Applications
This MCU can be used in audio components, cameras, televisions, household appliances, office
equipment, communication devices, mobile devices, industrial equipment, and other applications.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 1 of 109
M16C/65C Group
1.2
1. Overview
Specifications
The M16C/65C Group includes 128-pin and 100-pin packages. Table 1.1 to Table 1.4 list specifications.
Table 1.1
Specifications for the 128-Pin Package (1/2)
Item
Function
Description
CPU
Central processing unit
M16C/60 Series core
(multiplier: 16 bit × 16 bit 32 bit,
multiply and accumulate instruction: 16 bit × 16 bit + 32 bit 32 bit)
• Number of basic instructions: 91
• Minimum instruction execution time:
31.25 ns (f(BCLK) = 32 MHz, VCC1 = VCC2 = 2.7 to 5.5 V)
• Operating modes: Single-chip, memory expansion, and microprocessor
Memory
ROM, RAM, data flash
See Table 1.5 “Product List (N-Version)” to Table 1.6 “Product List (DVersion)”.
Voltage
Detection
Voltage detector
• Power-on reset
• 3 voltage detection points (detection level of voltage detection 0 and 1
selectable)
• 5 circuits: Main clock, sub clock, low-speed on-chip oscillator (125 kHz),
high-speed on-chip oscillator (40 MHz ±5%), PLL frequency synthesizer
• Oscillation stop detection: Main clock oscillation stop/restart detection
Clock
Clock generator
function
• Frequency divider circuit: Divide ratio selectable from 1, 2, 4, 8, and 16
• Power saving features: Wait mode, stop mode
• Real-time clock
• Address space: 1 MB
• External bus interface: 0 to 8 waits inserted, 4 chip select outputs,
External Bus
Bus memory expansion
Expansion
I/O Ports
Programmable I/O ports
Interrupts
Watchdog Timer
DMA
DMAC
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
memory area expansion function (expandable to 4 MB), 3 V and 5 V
interfaces
• Bus format: Separate bus or multiplexed bus selectable, data bus width
selectable (8 or 16 bits), number of address buses selectable (12, 16, or
20)
• CMOS I/O ports: 111 (selectable pull-up resistors)
• N-channel open drain ports: 3
• Interrupt vectors: 70
• External interrupt inputs: 13 (NMI, INT × 8, key input × 4)
• Interrupt priority levels: 7
15-bit timer × 1 (with prescaler)
Automatic reset start function selectable
• 4 channels, cycle steal mode
• Trigger sources: 43
• Transfer modes: 2 (single transfer, repeat transfer)
Page 2 of 109
M16C/65C Group
Table 1.2
1. Overview
Specifications for the 128-Pin Package (2/2)
Item
Timers
Function
Description
Timer A
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse width
modulation (PWM) mode
Event counter two-phase pulse signal processing (two-phase encoder
input) × 3
Programmable output mode × 3
Timer B
16-bit timer × 6
Timer mode, event counter mode, pulse period measurement mode,
pulse width measurement mode
Three-phase motor control
timer functions
• Three-phase inverter control (timer A1, timer A2, timer A4, timer B2)
• On-chip dead time timer
Real-time clock
Count: seconds, minutes, hours, days of the week
PWM function
8 bits × 2
• 2 circuits
• 4 wave pattern matchings (differentiate wave pattern for headers, data
Remote control signal receiver
0, data 1, and special data)
• 6-byte receive buffer (1 circuit only)
• Operating frequency of 32 kHz
Serial
Interface
Multi-master
UART0 to UART2, UART5 to
UART7
Clock synchronous/asynchronous × 6 channels
I2C-bus, IEBus, special mode 2
SIM (UART2)
SI/O3, SI/O4
Clock synchronization only × 2 channels
I2C-bus
Interface
1 channel
CEC Functions (2)
CEC transmit/receive, arbitration lost detection, ACK automatic output,
operation frequency of 32 kHz
A/D Converter
10-bit resolution × 26 channels, including sample and hold function
Conversion time: 1.72 µs
D/A Converter
8-bit resolution × 2 circuits
CRC Calculator
CRC-CCITT (X16 + X12 + X5 + 1),
CRC-16 (X16 + X15 + X2 + 1) compliant
Flash Memory
• Program and erase power supply voltage: 2.7 to 5.5 V
• Program and erase cycles: 1,000 times (program ROM 1, program
ROM 2), 10,000 times (data flash)
• Program security: ROM code protect, ID code check
Debug Functions
On-chip debug, on-board flash rewrite, address match interrupt × 4
Operation Frequency/Supply Voltage
32 MHz/VCC1 = 2.7 to 5.5 V, VCC2 = 2.7 V to VCC1
Current Consumption
Refer to the Electrical Characteristics chapter
Operating Temperature
-20°C to 85°C, -40°C to 85°C (1)
Package
128-pin LQFP: PLQP0128KB-A (Previous package code: 128P6Q-A)
Notes:
1. See Table 1.5 “Product List (N-Version)” to Table 1.6 “Product List (D-Version)” for the operating temperature.
2. The CEC function indicates circuitry which supports the transmission and reception of CEC signals standardized
by the High-Definition Multimedia Interface (HDMI). HDMI and High-Definition Multimedia Interface are
registered trademarks of HDMI Licensing, LLC.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 3 of 109
M16C/65C Group
Table 1.3
1. Overview
Specifications for the 100-Pin Package (1/2)
Item
Function
Description
CPU
Central processing unit
M16C/60 Series core
(multiplier: 16 bit × 16 bit 32 bit,
multiply and accumulate instruction: 16 bit × 16 bit + 32 bit 32 bit)
• Number of basic instructions: 91
• Minimum instruction execution time:
31.25 ns (f(BCLK) = 32 MHz, VCC1 = VCC2 = 2.7 to 5.5 V)
• Operating modes: Single-chip, memory expansion, and microprocessor
Memory
ROM, RAM, data flash
See Table 1.5 “Product List (N-Version)” to Table 1.6 “Product List (DVersion)”.
Voltage
Detection
Voltage detector
• Power-on reset
• 3 voltage detection points (detection level of voltage detection 0 and 1
selectable)
• 5 circuits: Main clock, sub clock, low-speed on-chip oscillator (125 kHz),
high-speed on-chip oscillator (40 MHz ±5%), PLL frequency synthesizer
• Oscillation stop detection: Main clock oscillation stop/restart detection
Clock
Clock generator
function
• Frequency divider circuit: Divide ratio selectable from 1, 2, 4, 8, and 16
• Power saving features: Wait mode, stop mode
• Real-time clock
• Address space: 1 MB
• External bus interface: 0 to 8 waits inserted, 4 chip select outputs,
External Bus
Bus memory expansion
Expansion
I/O Ports
Programmable I/O ports
Interrupts
Watchdog Timer
DMA
DMAC
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
memory area expansion function (expandable to 4 MB), 3 V and 5 V
interfaces
• Bus format: Separate bus or multiplexed bus selectable, data bus width
selectable (8 or 16 bits), number of address buses selectable (12, 16, or
20)
• CMOS I/O ports: 85 (selectable pull-up resistors)
• N-channel open drain ports: 3
• Interrupt vectors: 70
• External interrupt inputs: 13 (NMI, INT × 8, key input × 4)
• Interrupt priority levels: 7
15-bit timer × 1 (with prescaler)
Automatic reset start function selectable
• 4 channels, cycle steal mode
• Trigger sources: 43
• Transfer modes: 2 (single transfer, repeat transfer)
Page 4 of 109
M16C/65C Group
Table 1.4
1. Overview
Specifications for the 100-Pin Package (2/2)
Item
Timers
Function
Description
Timer A
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse width
modulation (PWM) mode
Event counter two-phase pulse signal processing (two-phase encoder
input) × 3
Programmable output mode × 3
Timer B
16-bit timer × 6
Timer mode, event counter mode, pulse period measurement mode,
pulse width measurement mode
Three-phase motor control
timer functions
• Three-phase inverter control (timer A1, timer A2, timer A4, timer B2)
• On-chip dead time timer
Real-time clock
Count: seconds, minutes, hours, days of the week
PWM function
8 bits × 2
• 2 circuits
• 4 wave pattern matchings (differentiate wave pattern for headers, data
Remote control signal receiver
0, data 1, and special data)
• 6-byte receive buffer (1 circuit only)
• Operating frequency of 32 kHz
Serial
Interface
Multi-master
UART0 to UART2, UART5 to
UART7
Clock synchronous/asynchronous × 6 channels
I2C-bus, IEBus, special mode 2
SIM (UART2)
SI/O3, SI/O4
Clock synchronization only × 2 channels
I2C-bus
Interface
1 channel
CEC Functions (2)
CEC transmit/receive, arbitration lost detection, ACK automatic output,
operation frequency of 32 kHz
A/D Converter
10-bit resolution × 26 channels, including sample and hold function
Conversion time: 1.72 µs
D/A Converter
8-bit resolution × 2 circuits
CRC Calculator
CRC-CCITT (X16 + X12 + X5 + 1),
CRC-16 (X16 + X15 + X2 + 1) compliant
Flash Memory
• Program and erase power supply voltage: 2.7 to 5.5 V
• Program and erase cycles: 1,000 times (program ROM 1, program
ROM 2), 10,000 times (data flash)
• Program security: ROM code protect, ID code check
Debug Functions
On-chip debug, on-board flash rewrite, address match interrupt × 4
Operation Frequency/Supply Voltage
25 MHz/VCC1 = 2.7 to 5.5 V, VCC2 = 2.7 V to VCC1
32 MHz/VCC1 = 2.7 to 5.5 V, VCC2 = 2.7 V to VCC1
Current Consumption
Refer to the Electrical Characteristics chapter
Operating Temperature
-20°C to 85°C, -40°C to 85°C (1)
Package
100-pin QFP: PRQP0100JD-B (Previous package code: 100P6F-A)
100-pin LQFP: PLQP0100KB-A (Previous package code: 100P6Q-A)
Notes:
1. See Table 1.5 “Product List (N-Version)” to Table 1.6 “Product List (D-Version)” for the operating temperature.
2. The CEC function indicates circuitry which supports the transmission and reception of CEC signals standardized
by the High-Definition Multimedia Interface (HDMI). HDMI and High-Definition Multimedia Interface are
registered trademarks of HDMI Licensing, LLC.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 5 of 109
M16C/65C Group
1.3
1. Overview
Product List
Table 1.5 and Table 1.6 list product information. Figure 1.1 shows the Part No., with Memory Size and
Package, and Figure 1.2 shows the Marking Diagram (Top View).
Table 1.5
Product List (N-Version)
Part No.
R5F36506CNFA
R5F36506CNFB
Program
ROM 1
128 KB
ROM Capacity
Program
Data flash
ROM 2
16 KB
256 KB
16 KB
R5F3650ECNFB
20 KB
Remarks
PRQP0100JD-B
PLQP0100KB-A
PRQP0100JD-B
PLQP0100KB-A
384 KB
16 KB
512 KB
16 KB
4 KB
× 2 blocks
31 KB
4 KB
× 2 blocks
47 KB
R5F3651MCNFC
R5F3650MCNFB
31 KB
PRQP0100JD-B Operating
temperature
PLQP0100KB-A -20°C to 85°C
PLQP0128KB-A
PRQP0100JD-B
PLQP0100KB-A
PLQP0128KB-A
R5F3651NCNFC
R5F3650NCNFA
4 KB
× 2 blocks
4 KB
× 2 blocks
R5F3650KCNFB
R5F3650MCNFA
12 KB
Package Code
PLQP0128KB-A
R5F3651KCNFC
R5F3650KCNFA
4 KB
× 2 blocks
RAM
Capacity
PLQP0128KB-A
R5F3651ECNFC
R5F3650ECNFA
As of July, 2012
512 KB
16 KB
R5F3650NCNFB
PRQP0100JD-B
PLQP0100KB-A
(D): Under development
(P): Planning
Note:
1. Previous package codes are as follows:
PLQP0128KB-A: 128P6Q-A, PRQP0100JD-B: 100P6F-A, PLQP0100KB-A: 100P6Q-A
Table 1.6
Product List (D-Version)
Part No.
R5F36506CDFA
R5F36506CDFB
16 KB
4 KB
× 2 blocks
12 KB
256 KB
16 KB
4 KB
× 2 blocks
20 KB
R5F3650ECDFB
R5F3651KCDFC
R5F3650KCDFA
4 KB
× 2 blocks
31 KB
512 KB
16 KB
4 KB
× 2 blocks
31 KB
R5F3650MCDFB
R5F3651NCDFC
R5F3650NCDFA
512 KB
R5F3650NCDFB
16 KB
4 KB × 2
blocks
Remarks
PRQP0100JD-B
PLQP0100KB-A
PRQP0100JD-B
PLQP0100KB-A
16 KB
R5F3651MCDFC
Package Code
PLQP0128KB-A
384 KB
R5F3650KCDFB
R5F3650MCDFA
RAM
Capacity
128 KB
R5F3651ECDFC
R5F3650ECDFA
As of July, 2012
ROM Capacity
Program
Program
Data flash
ROM 1
ROM 2
PLQP0128KB-A
PRQP0100JD-B Operating
temperature
PLQP0100KB-A -40°C to 85°C
PLQP0128KB-A
PRQP0100JD-B
PLQP0100KB-A
PLQP0128KB-A
47 KB
PRQP0100JD-B
PLQP0100KB-A
(D): Under development
(P): Planning
Note:
1. Previous package codes are as follows:
PLQP0128KB-A: 128P6Q-A, PRQP0100JD-B: 100P6F-A, PLQP0100KB-A: 100P6Q-A
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 6 of 109
M16C/65C Group
Part No.
1. Overview
R 5 F 3 65 0
6 C D FA
Package type
FC: Package PLQP0128KB-A (128P6Q-A)
FA: Package PRQP0100JD-B (100P6F-A)
FB: Package PLQP0100KB-A (100P6Q-A)
Property Code
N: Operating temperature: -20°C to 85°C
D: Operating temperature: -40°C to 85°C
Memory capacity
Program ROM 1/RAM
6: 128 KB/12 KB
E: 256 KB/20 KB
K: 384 KB/31 KB
M: 512 KB/31 KB
N: 512 KB/47 KB
Number of pins
0: 100 pins
1: 128 pins
M16C/65C Group
16-bit MCU
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1
Part No., with Memory Size and Package
M16C
R5F36506CDFA
XXXXXXX
Type No. (See Figure 1.1 “Part No., with Memory Size and Package”)
Running No. 0 to 9, A to Z (except for I, O, Q)
Week code (from 01 to 54)
Last one digit of year
Figure 1.2
Marking Diagram (Top View)
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 7 of 109
M16C/65C Group
1.4
1. Overview
Block Diagram
Figure 1.3 to Figure 1.4 show block diagrams.
8
Port P0
8
Port P1
8
8
Port P2
8
Port P3
8
Port P4
8
Port P5
8
Port P12
Port P13
VCC2 ports
Internal peripheral functions
Timer (16 bit)
System clock generator
UART or
clock synchronous serial I/O
(6 channels)
Outputs (timer A): 5
Inputs (timer B): 6
Clock synchronous serial I/O
(8 bit x 2 channels)
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator (125 kHz)
High-speed on-chip oscillator
Three-phase
motor control circuit
Multi-master I2C-bus interface
(1 channel)
DMAC
(4 channels)
CEC function
CRC arithmetic circuit
(CRC-CCITT or CRC-16)
Real-time clock
PWM function (8 bit x 2)
Voltage detector
Remote control signal
receiver (2 circuits)
Power-on reset
Watchdog timer
(15 bit)
On-chip debugger
A/D converter
(10-bit resolution x 26
channels)
Memory
M16C/60 Series CPU core
R0H
R1H
D/A converter
(8-bit resolution x 2
circuits)
ROM (1)
SB
R0L
R1L
USP
R2
R3
ISP
RAM (2)
INTB
A0
A1
FB
PC
Multiplier
FLG
VCC1 ports
Port P14
2
Port P11
Port P10
8
8
Port P9
8
Port P8
8
Port P7
8
Port P6
8
Notes:
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.
Figure 1.3
Block Diagram for the 128-Pin Package
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 8 of 109
M16C/65C Group
1. Overview
8
Port P0
8
Port P1
8
8
Port P2
8
Port P3
8
Port P4
Port P5
VCC2 ports
Internal peripheral functions
System clock generator
Timer (16 bit)
UART or
clock synchronous serial I/O
(6 channels)
Outputs (timer A): 5
Inputs (timer B): 6
Clock synchronous serial I/O
(8 bit x 2 channels)
Three-phase motor control
circuit
Multi-master I2C-bus interface
(1 channel)
DMAC (4 channels)
CEC function
CRC arithmetic circuit
(CRC-CCITT or CRC-16)
Real-time clock
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator (125 kHz)
High-speed on-chip oscillator
PWM function (8 bit x 2)
Remote control signal
receiver (2 circuits)
Voltage detector
Watchdog timer
(15 bit)
On-chip debugger
Power-on reset
A/D converter
(10-bit resolution x 26
channels)
Memory
M16C/60 Series CPU core
R0H
R1H
D/A converter
(8-bit resolution x 2
circuits)
SB
R0L
R1L
ROM (1)
USP
R2
R3
ISP
RAM (2)
INTB
A0
A1
FB
PC
FLG
Multiplier
VCC1 ports
Port P10
Port P9
8
Port P8
8
8
Port P7
8
Port P6
8
Notes:
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.
Figure 1.4
Block Diagram for the 100-Pin Package
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 9 of 109
VREF
AVCC
P9_7/ADTRG/SIN4
P9_6/ANEX1/SOUT4
P9_5/ANEX0/CLK4
P9_4/DA1/TB4IN/PWM1
P9_3/DA0/TB3IN/PWM0
P9_2/TB2IN/PMC0/SOUT3
P9_1/TB1IN/PMC1/SIN3
P9_0/TB0IN/CLK3
P14_1
P14_0
BYTE
CNVSS
P8_7/XCIN
P8_6/XCOUT
RESET
XOUT
VSS
XIN
VCC1
P8_5/NMI/SD/CEC (1)
P8_4/INT2/ZP
P8_3/INT1
P8_2/INT0
P8_1/TA4IN/U/CTS5/RTS5
P8_0/TA4OUT/U/RXD5/SCL5
P7_7/TA3IN/CLK5
P7_6/TA3OUT/TXD5/SDA5
P7_5/TA2IN/W
P7_4/TA2OUT/W
P7_3/CTS2/RTS2/TA1IN/V
P7_2/CLK2/TA1OUT/V
P7_1/RXD2/SCL2/SCLMM/TA0IN/TB5IN (1)
P7_0/TXD2/SDA2/SDAMM/TA0OUT (1)
P6_7/TXD1/SDA1
VCC1
P6_6/RXD1/SCL1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
P1_1/CLK6/D9
P1_2/RXD6/SCL6/D10
P1_3/TXD6/SDA6/D11
P1_4/D12
P1_5/INT3/IDV/D13
P1_6/INT4/IDW/D14
P1_7/INT5/IDU/D15
P2_0/AN2_0/A0, [A0/D0], A0
P2_1/AN2_1/A1, [A1/D1], [A1/D0]
P2_2/AN2_2/A2, [A2/D2], [A2/D1]
P2_3/AN2_3/A3, [A3/D3], [A3/D2]
P2_4/INT6/AN2_4/A4, [A4/D4], [A4/D3]
P2_5/INT7/AN2_5/A5, [A5/D5], [A5/D4]
P2_6/AN2_6/A6, [A6/D6], [A6/D5]
P2_7/AN2_7/A7, [A7/D7], [A7/D6]
VSS
P3_0/A8 [A8/D7]
VCC2
P12_0
P12_1
P12_2
P12_3
P12_4
P3_1/A9
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
P4_2/A18
P4_3/A19
P4_4/CTS7/RTS7/CS0
P4_5/CLK7/CS1
P4_6/PWM0/RXD7/SCL7/CS2
P4_7/PWM1/TXD7/SDA7/CS3
M16C/65C Group
1.5
P1_0/CTS6/RTS6/D8
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P11_7
P11_6
P11_5
P11_4
P11_3
P11_2
P11_1
P11_0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
Figure 1.5
1. Overview
Pin Assignments
Figure 1.5 to Figure 1.7 show pin assignments. Table 1.7 to Table 1.11 list pin names.
(See Note 3)
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
VCC2 ports
M16C/65C Group
PLQP0128KB-A
(128P6Q-A)
(Top view)
VCC1 ports
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
P12_5
P12_6
P12_7
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P13_0
P13_1
P13_2
P13_3
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P13_4
P13_5
P13_6
P13_7
P6_0/RTCOUT/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
VSS
Notes:
1. N-channel open drain output.
2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions.
3. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two
separate functional signals.
Pin Assignment for the 128-Pin Package
Page 10 of 109
M16C/65C Group
Table 1.7
1. Overview
Pin Names for the 128-Pin Package (1/3)
I/O Pin for Peripheral Function
Pin No. Control Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Port
Interrupt
Timer
Serial interface
A/D converter,
D/A converter
Bus Control
Pin
VREF
AVCC
P9_7
P9_6
P9_5
P9_4
P9_3
P9_2
P9_1
P9_0
P14_1
P14_0
BYTE
CNVSS
XCIN
XCOUT
RESET
XOUT
VSS
XIN
VCC1
SIN4
SOUT4
CLK4
TB4IN/PWM1
TB3IN/PWM0
TB2IN/PMC0
TB1IN/PMC1
TB0IN
ADTRG
ANEX1
ANEX0
DA1
DA0
SOUT3
SIN3
CLK3
P8_7
P8_6
P8_5
P8_4
P8_3
P8_2
P8_1
P8_0
P7_7
P7_6
P7_5
P7_4
P7_3
P7_2
P7_1
P7_0
P6_7
NMI
INT2
INT1
INT0
SD
ZP
CEC
TA4IN/U
TA4OUT/U
TA3IN
TA3OUT
TA2IN/W
TA2OUT/W
TA1IN/V
TA1OUT/V
TA0IN/TB5IN
TA0OUT
CTS5/RTS5
RXD5/SCL5
CLK5
TXD5/SDA5
CTS2/RTS2
CLK2
RXD2/SCL2/SCLMM
TXD2/SDA2/SDAMM
TXD1/SDA1
VCC1
P6_6
RXD1/SCL1
P6_5
P6_4
P6_3
P6_2
P6_1
P6_0
P13_7
P13_6
P13_5
P13_4
P5_7
CLK1
CTS1/RTS1/CTS0/CLKS1
TXD0/SDA0
RXD0/SCL0
CLK0
CTS0/RTS0
VSS
CLKOUT
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
RTCOUT
RDY
Page 11 of 109
M16C/65C Group
Table 1.8
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1. Overview
Pin Names for the 128-Pin Package (2/3)
Control
Pin
I/O Pin for Peripheral Function
Port
Interrupt
P5_6
P5_5
P5_4
P13_3
P13_2
P13_1
P13_0
P5_3
P5_2
P5_1
P5_0
P12_7
P12_6
P12_5
P4_7
P4_6
P4_5
P4_4
P4_3
P4_2
P4_1
P4_0
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
P12_4
P12_3
P12_2
P12_1
P12_0
Timer
Serial interface
A/D converter,
D/A converter
Bus Control Pin
ALE
HOLD
HLDA
BCLK
RD
WRH/BHE
WRL/WR
PWM1
PWM0
CS3
CS2
CS1
CS0
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
TXD7/SDA7
RXD7/SCL7
CLK7
CTS7/RTS7
VCC2
P3_0
A8, [A8/D7]
VSS
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P1_7
P1_6
P1_5
P1_4
P1_3
AN2_7
AN2_6
AN2_5
AN2_4
AN2_3
AN2_2
AN2_1
AN2_0
INT7
INT6
INT5
INT4
INT3
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
IDU
IDW
IDV
TXD6/SDA6
A7, [A7/D7], [A7/D6]
A6, [A6/D6], [A6/D5]
A5, [A5/D5], [A5/D4]
A4[A4/D4], [A4/D3]
A3, [A3/D3], [A3/D2]
A2, [A2/D2], [A2/D1]
A1, [A1/D1], [A1/D0]
A0, [A0/D0], A0
D15
D14
D13
D12
D11
Page 12 of 109
M16C/65C Group
Table 1.9
Pin
No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Control
Pin
1. Overview
Pin Names for the 128-Pin Package (3/3)
I/O Pin for Peripheral Function
Port
P1_2
P1_1
P1_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
P11_7
P11_6
P11_5
P11_4
P11_3
P11_2
P11_1
P11_0
P10_7
P10_6
P10_5
P10_4
P10_3
P10_2
P10_1
Interrupt
Timer
Serial interface
A/D converter,
D/A converter
RXD6/SCL6
CLK6
CTS6/RTS6
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
AN0_2
AN0_1
AN0_0
KI3
KI2
KI1
KI0
Bus Control Pin
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AVSS
P10_0
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
AN0
Page 13 of 109
P9_6/ANEX1/SOUT4
P9_5/ANEX0/CLK4
P9_4/DA1/TB4IN/PWM1
P9_3/DA0/TB3IN/PWM0
P9_2/TB2IN/PMC0/SOUT3
P9_1/TB1IN/PMC1/SIN3
P9_0/TB0IN/CLK3
BYTE
CNVSS
P8_7/XCIN
P8_6/XCOUT
RESET
XOUT
VSS
XIN
VCC1
P8_5/NMI/SD/CEC (1)
P8_4/INT2/ZP
P8_3/INT1
P8_2/INT0
P8_1/TA4IN/U/CTS5/RTS5
P8_0/TA4OUT/U/RXD5/SCL5
P7_7/TA3IN/CLK5
P7_6/TA3OUT/TXD5/SDA5
P7_5/TA2IN/W
P7_4/TA2OUT/W
P7_3/CTS2/RTS2/TA1IN/V
P7_2/CLK2/TA1OUT/V
P7_1/RXD2/SCL2/SCLMM/TA0IN/TB5IN (1)
P7_0/TXD2/SDA2/SDAMM/TA0OUT (1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P1_0/CTS6/RTS6/D8
P1_1/CLK6/D9
P1_2/RXD6/SCL6/D10
P1_3/TXD6/SDA6/D11
P1_4/D12
P1_5/INT3/IDV/D13
P1_6/INT4/IDW/D14
P1_7/INT5/IDU/D15
P2_0/AN2_0/A0, [A0/D0], A0
P2_1/AN2_1/A1, [A1/D1], [A1/D0]
P2_2/AN2_2/A2, [A2/D2], [A2/D1]
P2_3/AN2_3/A3, [A3/D3], [A3/D2]
P2_4/INT6/AN2_4/A4, [A4/D4], [A4/D3]
P2_5/INT7/AN2_5/A5, [A5/D5], [A5/D4]
P2_6/AN2_6/A6, [A6/D6], [A6/D5]
P2_7/AN2_7/A7, [A7/D7], [A7/D6]
VSS
P3_0/A8 [A8/D7]
VCC2
P3_1/A9
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
P4_2/A18
P4_3/A19
M16C/65C Group
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
AVCC
P9_7/ADTRG/SIN4
Figure 1.6
1. Overview
(See Note 3)
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VCC2 ports
M16C/65C Group
PRQP0100JD-B
(100P6F-A)
(Top view)
VCC1 ports
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P4_4/CTS7/RTS7/CS0
P4_5/CLK7/CS1
P4_6/PWM0/RXD7/SCL7/CS2
P4_7/PWM1/TXD7/SDA7/CS3
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P6_0/RTCOUT/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
Notes:
1. N-channel open drain output.
2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions.
3. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two
separate functional signals.
Pin Assignment for the 100-Pin Package
Page 14 of 109
M16C/65C Group
1. Overview
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P1_3/TXD6/SDA6/D11
P1_4/D12
P1_5/INT3/IDV/D13
P1_6/INT4/IDW/D14
P1_7/INT5/IDU/D15
P2_0/AN2_0/A0, [A0/D0], A0
P2_1/AN2_1/A1, [A1/D1], [A1/D0]
P2_2/AN2_2/A2, [A2/D2], [A2/D1]
P2_3/AN2_3/A3, [A3/D3], [A3/D2]
P2_4/INT6/AN2_4/A4, [A4/D4], [A4/D3]
P2_5/INT7/AN2_5/A5, [A5/D5], [A5/D4]
P2_6/AN2_6/A6, [A6/D6], [A6/D5]
P2_7/AN2_7/A7, [A7/D7], [A7/D6]
VSS
P3_0/A8 [A8/D7]
VCC2
P3_1/A9
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
(See Note 3)
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VCC2 ports
M16C/65C Group
PLQP0100KB-A
(100P6Q-A)
(Top view)
VCC1 ports
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P4_2/A18
P4_3/A19
P4_4/CTS7/RTS7/CS0
P4_5/CLK7/CS1
P4_6/PWM0/RXD7/SCL7/CS2
P4_7/PWM1/TXD7/SDA7/CS3
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P6_0/RTCOUT/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P7_0/TXD2/SDA2/SDAMM/TA0OUT (1)
P7_1/RXD2/SCL2/SCLMM/TA0IN/TB5IN (1)
P7_2/CLK2/TA1OUT/V
RESET
XOUT
VSS
XIN
VCC1
P8_5/NMI/SD/CEC (1)
P8_4/INT2/ZP
P8_3/INT1
P8_2/INT0
P8_1/TA4IN/U/CTS5/RTS5
P8_0/TA4OUT/U/RXD5/SCL5
P7_7/TA3IN/CLK5
P7_6/TA3OUT/TXD5/SDA5
P7_5/TA2IN/W
P7_4/TA2OUT/W
P7_3/CTS2/RTS2/TA1IN/V
P9_4/DA1/TB4IN/PWM1
P9_3/DA0/TB3IN/PWM0
P9_2/TB2IN/PMC0/SOUT3
P9_1/TB1IN/PMC1/SIN3
P9_0/TB0IN/CLK3
BYTE
CNVSS
P8_7/XCIN
P8_6/XCOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P1_2/RXD6/SCL6/D10
P1_1/CLK6/D9
P1_0/CTS6/RTS6/D8
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
AVCC
P9_7/ADTRG/SIN4
P9_6/ANEX1/SOUT4
P9_5/ANEX0/CLK4
Notes:
1. N-channel open drain output.
2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions.
3. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two
separate functional signals.
Figure 1.7
Pin Assignment for the 100-Pin Package
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 15 of 109
M16C/65C Group
Table 1.10
1. Overview
Pin Names for the 100-Pin Package (1/2)
Pin No.
FA
FB
I/O Pin for Peripheral Function
Control Pin
Port
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
99
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
34
32
P6_4
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
P6_3
P6_2
P6_1
P6_0
P5_7
P5_6
P5_5
P5_4
P5_3
P5_2
P5_1
P5_0
P4_7
P4_6
P4_5
P4_4
Interrupt
P9_6
P9_5
P9_4
P9_3
P9_2
P9_1
P9_0
BYTE
CNVSS
XCIN
XCOUT
RESET
XOUT
VSS
XIN
VCC1
Serial interface
SOUT4
CLK4
TB4IN/PWM1
TB3IN/PWM0
TB2IN/PMC0
TB1IN/PMC1
TB0IN
A/D converter,
D/A converter
ANEX1
ANEX0
DA1
DA0
Bus Control
Pin
SOUT3
SIN3
CLK3
P8_7
P8_6
P8_5
P8_4
P8_3
P8_2
P8_1
P8_0
P7_7
P7_6
P7_5
P7_4
P7_3
P7_2
P7_1
P7_0
P6_7
P6_6
P6_5
CLKOUT
Timer
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
NMI
INT2
INT1
INT0
SD
ZP
CEC
TA4IN/U
TA4OUT/U
TA3IN
TA3OUT
TA2IN/W
TA2OUT/W
TA1IN/V
TA1OUT/V
TA0IN/TB5IN
TA0OUT
CTS5/RTS5
RXD5/SCL5
CLK5
TXD5/SDA5
RTCOUT
PWM1
PWM0
CTS2/RTS2
CLK2
RXD2/SCL2/SCLMM
TXD2/SDA2/SDAMM
TXD1/SDA1
RXD1/SCL1
CLK1
CTS1/RTS1/CTS0/
CLKS1
TXD0/SDA0
RXD0/SCL0
CLK0
CTS0/RTS0
TXD7/SDA7
RXD7/SCL7
CLK7
CTS7/RTS7
RDY
ALE
HOLD
HLDA
BCLK
RD
WRH/BHE
WRL/WR
CS3
CS2
CS1
CS0
Page 16 of 109
M16C/65C Group
Table 1.11
Pin No.
FA
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
FB
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
1. Overview
Pin Names for the 100-Pin Package (2/2)
Control
Pin
Port
Interrupt
I/O Pin for Peripheral Function
A/D converter,
Timer
Serial interface
D/A converter
Bus Control Pin
P4_3
P4_2
P4_1
P4_0
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
P3_0
A8, [A8/D7]
VCC2
VSS
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
P10_7
P10_6
P10_5
P10_4
P10_3
P10_2
P10_1
AN2_7
AN2_6
AN2_5
AN2_4
AN2_3
AN2_2
AN2_1
AN2_0
INT7
INT6
INT5
INT4
INT3
IDU
IDW
IDV
TXD6/SDA6
RXD6/SCL6
CLK6
CTS6/RTS6
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
AN0_2
AN0_1
AN0_0
AN7
AN6
AN5
AN4
AN3
AN2
AN1
KI3
KI2
KI1
KI0
A7, [A7/D7], [A7/D6]
A6, [A6/D6], [A6/D5]
A5, [A5/D5], [A5/D4]
A4, [A4/D4], [A4/D3]
A3, [A3/D3], [A3/D2]
A2, [A2/D2], [A2/D1]
A1, [A1/D1], [A1/D0]
A0, [A0/D0], A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
AVSS
P10_0
AN0
VREF
AVCC
P9_7
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
SIN4
ADTRG
Page 17 of 109
M16C/65C Group
1.6
1. Overview
Pin Functions
Table 1.12
Pin Functions for the 128-Pin Package (1/3)
Signal Name
Pin Name
I/O
Power Supply
Description
Power supply
input
VCC1,
VCC2,
VSS
I
-
Apply 2.7 to 5.5 V to pins VCC1 and VCC2 (VCC1 ≥ VCC2),
and 0 V to the VSS pin.
Analog power
supply input
AVCC,
AVSS
I
VCC1
This is the power supply for the A/D and D/A converters.
Connect the AVCC pin to VCC1, and connect the AVSS pin
to VSS.
Reset input
RESET
I
VCC1
Driving this pin low resets the MCU.
VCC1
Input pin to switch processor modes. After a reset, to start
operating in single-chip mode, connect the CNVSS pin to
VSS via a resistor. To start operating in microprocessor
mode, connect the pin to VCC1.
CNVSS
External data bus
width select input
CNVSS
I
BYTE
I
VCC1
Input pin to select the data bus of the external area. The data
bus is 16 bits when it is low and 8 bits when it is high. This
pin must be fixed either high or low. Connect the BYTE pin to
VSS in single-chip mode.
D0 to D7
I/O
VCC2
Inputs or outputs data (D0 to D7) while accessing an
external area with a separate bus.
D8 to D15
I/O
VCC2
Inputs or outputs data (D8 to D15) while accessing an
external area with a 16-bit separate bus.
A0 to A19
O
VCC2
Outputs address bits A0 to A19.
A0/D0 to
A7/D7
I/O
VCC2
Inputs or outputs data (D0 to D7) and outputs address bits
(A0 to A7) by timesharing, while accessing an external area
with an 8-bit multiplexed bus.
A1/D0 to
A8/D7
I/O
VCC2
Inputs or outputs data (D0 to D7) and outputs address bits
(A1 to A8) by timesharing, while accessing an external area
with a 16-bit multiplexed bus.
CS0 to CS3
O
VCC2
Outputs chip-select signals CS0 to CS3 to specify an
external area.
WRL/WR
WRH/BHE
RD
O
VCC2
Outputs WRL, WRH, (WR, BHE), and RD signals. WRL and
WRH can be switched with BHE and WR.
• WRL, WRH, and RD selected
If the external data bus is 16 bits, data is written to an even
address in an external area when WRL is driven low. Data
is written to an odd address when WRH is driven low. Data
is read when RD is driven low.
• WR, BHE, and RD selected
Data is written to an external area when WR is driven low.
Data in an external area is read when RD is driven low. An
odd address is accessed when BHE is driven low. Select
WR, BHE, and RD when using an 8-bit external data bus.
ALE
O
VCC2
Outputs an ALE signal to latch the address.
HOLD
I
VCC2
HOLD input is unavailable. Connect the HOLD pin to VCC2
via a resistor (pull-up).
HLDA
O
VCC2
In a hold state, HLDA outputs a low-level signal.
RDY
I
VCC2
The MCU bus is placed in wait state while the RDY pin is
driven low.
Bus control
pins
Power supply: VCC2 is used to supply power to the external bus associated pins. The dual power supply configuration
allows VCC2 to interface at a different voltage than VCC1.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 18 of 109
M16C/65C Group
Table 1.13
1. Overview
Pin Functions for the 128-Pin Package (2/3)
Signal Name
Pin Name
I/O
Power Supply
Description
XIN
I
VCC1
Main clock output
XOUT
O
VCC1
I/O for the main clock oscillator. Connect a ceramic
resonator or crystal between pins XIN and XOUT. (1)
Input an external clock to XIN pin and leave XOUT
pin open.
Sub clock input
XCIN
I
VCC1
XCOUT
O
VCC1
I/O for a sub clock oscillator. Connect a crystal
between pins XCIN and XCOUT. (1) Input an external
clock to XCIN pin and leave XCOUT pin open.
BCLK output
BCLK
O
VCC2
Outputs the BCLK signal.
Clock output
CLKOUT
O
VCC2
Outputs a clock with the same frequency as fC, f1, f8,
or f32.
INT0 to INT2
I
VCC1
INT3 to INT7
I
VCC2
NMI interrupt input
NMI
I
VCC1
Input for the NMI interrupt.
Key input interrupt
input
KI0 to KI3
I
VCC1
Input for the key input interrupt.
TA0OUT to
TA4OUT
I/O
VCC1
I/O for timers A0 to A4 (TA0OUT is N-channel open
drain output).
Timer A
TA0IN to TA4IN
I
VCC1
Input for timers A0 to A4.
ZP
I
VCC1
Input for Z-phase.
Timer B
TB0IN to TB5IN
I
VCC1
Input for timers B0 to B5.
U, U, V, V, W, W
O
VCC1
Output for the three-phase motor control timer.
SD
I
VCC1
Forced cutoff input.
IDU, IDV, IDW
I
VCC2
Input for the position data.
RTCOUT
O
VCC1
Output for the real-time clock.
PWM output
PWM0, PWM1
O
Remote control
signal receiver input
PMC0, PMC1
I
VCC1
CTS0 to CTS2,
CTS5
I
VCC1
CTS6, CTS7
I
VCC2
RTS0 to RTS2,
RTS5
O
VCC1
RTS6, RTS7
O
VCC2
CLK0 to CLK2,
CLK5
I/O
VCC1
CLK6, CLK7
I/O
VCC2
RXD0 to RXD2,
RXD5
I
VCC1
RXD6, RXD7
I
VCC2
TXD0 to TXD2,
TXD5
O
VCC1
TXD6, TXD7
O
VCC2
CLKS1
O
VCC1
Main clock input
Sub clock output
INT interrupt input
Three-phase motor
control timer
Real-time clock
output
Serial interface
UART0 to UART2,
UART5 to UART7
Input for the INT interrupt.
VCC1, VCC2 PWM output.
Input for the remote control signal receiver.
Input pins to control data transmission.
Output pins to control data reception.
Transmit/receive clock I/O.
Serial data input.
Serial data output. (2)
Output for the transmit/receive clock multiple-pin
output function.
Notes:
1. Contact the manufacturer of crystal/ceramic resonator regarding the oscillation characteristics.
2. TXD2, SDA2, and SCL2 are N-channel open drain output pins. TXDi (i = 0, 1, 5 to 7), SDAi, and SCLi can be
selected as CMOS output pins or N-channel open drain output pins.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 19 of 109
M16C/65C Group
Table 1.14
1. Overview
Pin Functions for the 128-Pin Package (3/3)
Signal Name
Pin Name
I/O
Power Supply
SDA0 to SDA2,
SDA5
I/O
VCC1
SDA6, SDA7
I/O
VCC2
SCL0 to SCL2,
SCL5
I/O
VCC1
SCL6, SCL7
I/O
VCC2
CLK3, CLK4
I/O
VCC1
Transmit/receive clock I/O.
SIN3, SIN4
I
VCC1
Serial data input.
SOUT3, SOUT4
O
VCC1
Serial data output.
SDAMM
I/O
VCC1
Serial data I/O (N-channel open drain output).
SCLMM
I/O
VCC1
Transmit/receive clock I/O (N-channel open drain
output).
CEC I/O
CEC
I/O
VCC1
CEC I/O (N-channel open drain output).
Reference
voltage input
VREF
I
VCC1
Reference voltage input for the A/D and D/A converters.
AN0 to AN7
I
VCC1
AN0_0 to AN0_7
AN2_0 to AN2_7
I
VCC2
ADTRG
I
VCC1
External trigger input.
ANEX0, ANEX1
I
VCC1
Extended analog input.
DA0, DA1
O
VCC1
Output pin the D/A converter.
VCC2
8-bit CMOS I/O ports. A direction register determines
whether each pin is used as an input port or an output
port. A pull-up resistor may be enabled or disabled for
input ports in 4-bit units.
UART0 to UART2,
UART5 to UART7
I2C mode
Serial interface
SI/O3, SI/O4
Multi-master I2Cbus interface
A/D converter
D/A converter
I/O ports
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_7
P3_0 to P3_7
P4_0 to P4_7
P5_0 to P5_7
P12_0 to P12_7
P13_0 to P13_7
I/O
Description
Serial data I/O.
Transmit/receive clock I/O.
Analog input.
P6_0 to P6_7
P7_0 to P7_7
P8_0 to P8_7
P9_0 to P9_7
P10_0 to P10_7
P11_0 to P11_7
I/O
VCC1
8-bit I/O ports having equivalent functions to P0.
However, P7_0, P7_1, and P8_5 are N-channel open
drain output ports. No pull-up resistor is provided. P8_5
is an input port for verifying the NMI pin level and shares
a pin with NMI.
P14_0, P14_1
I/O
VCC1
I/O ports having equivalent functions to P0.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 20 of 109
M16C/65C Group
Table 1.15
1. Overview
Pin Functions for the 100-Pin Package (1/3)
Signal Name
Pin Name
I/O
Power Supply
Description
Power supply
input
VCC1,
VCC2, VSS
I
-
Apply 2.7 to 5.5 V to pins VCC1 and VCC2 (VCC1 ≥ VCC2)
and 0 V to the VSS pin.
Analog power
supply input
AVCC, AVSS
I
VCC1
This is the power supply for the A/D and D/A converters.
Connect the AVCC pin to VCC1, and connect the AVSS pin
to VSS.
RESET
I
VCC1
Driving this pin low resets the MCU.
VCC1
Input pin to switch processor modes. After a reset, to start
operating in single-chip mode, connect the CNVSS pin to
VSS via a resistor. To start operating in microprocessor
mode, connect the pin to VCC1.
Reset input
CNVSS
External data bus
width select input
CNVSS
I
BYTE
I
VCC1
Input pin to select the data bus of the external area. The data
bus is 16 bits when it is low, and 8 bits when it is high. This
pin must be fixed either high or low. Connect the BYTE pin to
VSS in single-chip mode.
D0 to D7
I/O
VCC2
Inputs or outputs data (D0 to D7) while accessing an
external area with a separate bus.
D8 to D15
I/O
VCC2
Inputs or outputs data (D8 to D15) while accessing an
external area with a 16-bit separate bus.
A0 to A19
O
VCC2
Outputs address bits A0 to A19.
A0/D0 to
A7/D7
I/O
VCC2
Inputs or outputs data (D0 to D7) and outputs address bits
(A0 to A7) by timesharing, while accessing an external area
with an 8-bit multiplexed bus.
A1/D0 to
A8/D7
I/O
VCC2
Inputs or outputs data (D0 to D7) and outputs address bits
(A1 to A8) by timesharing, while accessing an external area
with a 16-bit multiplexed bus.
CS0 to CS3
O
VCC2
Outputs chip-select signals CS0 to CS3 to specify an
external area.
WRL/WR
WRH/BHE
RD
O
VCC2
Outputs WRL, WRH, (WR, BHE), and RD signals. WRL and
WRH can be switched with BHE and WR.
• WRL, WRH, and RD selected
If the external data bus is 16 bits, data is written to an even
address in an external area when WRL is driven low. Data
is written to an odd address when WRH is driven low. Data
is read when RD is driven low.
• WR, BHE, and RD selected
Data is written to an external area when WR is driven low.
Data in an external area is read when RD is driven low. An
odd address is accessed when BHE is driven low. Select
WR, BHE, and RD when using an 8-bit external data bus.
ALE
O
VCC2
Outputs an ALE signal to latch the address.
HOLD
I
VCC2
HOLD input is unavailable. Connect the HOLD pin to VCC2
via a resistor (pull-up).
HLDA
O
VCC2
In a hold state, HLDA outputs a low-level signal.
RDY
I
VCC2
The MCU bus is placed in a wait state while the RDY pin is
driven low.
Bus control pins
Power supply: VCC2 is used to supply power to the external bus associated pins. The dual power supply configuration
allows VCC2 to interface at a different voltage than VCC1.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 21 of 109
M16C/65C Group
Table 1.16
1. Overview
Pin Functions for the 100-Pin Package (2/3)
Signal Name
Pin Name
I/O Power Supply
Description
I/O for the main clock oscillator. Connect a ceramic
resonator or crystal between pins XIN and XOUT. (1)
Input an external clock to XIN pin and leave XOUT pin
open.
Main clock input
XIN
I
VCC1
Main clock output
XOUT
O
VCC1
Sub clock input
XCIN
I
VCC1
XCOUT
O
VCC1
I/O for a sub clock oscillator. Connect a crystal between
XCIN pin and XCOUT pin. (1) Input an external clock to
XCIN pin and leave XCOUT pin open.
BCLK output
BCLK
O
VCC2
Outputs the BCLK signal.
Clock output
CLKOUT
O
VCC2
Outputs a clock with the same frequency as fC, f1, f8, or
f32.
INT0 to INT2
I
VCC1
INT3 to INT7
I
VCC2
NMI interrupt input
NMI
I
VCC1
Input for the NMI interrupt.
Key input interrupt
input
KI0 to KI3
I
VCC1
Input for the key input interrupt.
TA0OUT to
TA4OUT
I/O
VCC1
I/O for timers A0 to A4 (TA0OUT is N-channel open drain
output).
TA0IN to TA4IN
I
VCC1
Input for timers A0 to A4.
Sub clock output
INT interrupt input
Timer A
Input for the INT interrupt.
ZP
I
VCC1
Input for Z-phase.
TB0IN to TB5IN
I
VCC1
Input for timers B0 to B5.
U, U, V, V, W, W
O
VCC1
Output for the three-phase motor control timer.
SD
I
VCC1
Forced cutoff input.
IDU, IDV, IDW
I
VCC2
Input for the position data.
RTCOUT
O
VCC1
Output for the real-time clock.
PWM output
PWM0, PWM1
O
Remote control
signal receiver input
PMC0, PMC1
I
VCC1
CTS0 to CTS2,
CTS5
I
VCC1
Timer B
Three-phase motor
control timer
Real-time clock
output
Serial interface
UART0 to UART2,
UART5 to UART7
VCC1, VCC2 PWM output.
CTS6, CTS7
I
VCC2
RTS0 to RTS2,
RTS5
O
VCC1
RTS6, RTS7
O
VCC2
CLK0 to CLK2,
CLK5
I/O
VCC1
CLK6, CLK7
I/O
VCC2
RXD0 to RXD2,
RXD5
I
VCC1
RXD6, RXD7
I
VCC2
TXD0 to TXD2,
TXD5
O
VCC1
TXD6, TXD7
O
VCC2
CLKS1
O
VCC1
Input for the remote control signal receiver.
Input pins to control data transmission.
Output pins to control data reception.
Transmit/receive clock I/O.
Serial data input.
Serial data output. (2)
Output for the transmit/receive clock multiple-pin output
function.
Notes:
1. Contact the manufacturer of crystal/ceramic resonator regarding the oscillation characteristics.
2. TXD2, SDA2, and SCL2 are N-channel open drain output pins. TXDi (i = 0, 1, 5 to 7), SDAi, and SCLi can be
selected as CMOS output pins or N-channel open drain output pins.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 22 of 109
M16C/65C Group
Table 1.17
1. Overview
Pin Functions for the 100-Pin Package (3/3)
Signal Name
Pin Name
I/O
Power Supply
SDA0 to SDA2,
SDA5
I/O
VCC1
SDA6, SDA7
I/O
VCC2
SCL0 to SCL2,
SCL5
I/O
VCC1
SCL6, SCL7
I/O
VCC2
CLK3, CLK4
I/O
VCC1
Transmit/receive clock I/O.
SIN3, SIN4
I
VCC1
Serial data input.
SOUT3, SOUT4
O
VCC1
Serial data output.
SDAMM
I/O
VCC1
Serial data I/O (N-channel open drain output).
SCLMM
I/O
VCC1
Transmit/receive clock I/O (N-channel open drain
output).
CEC I/O
CEC
I/O
VCC1
CEC I/O (N-channel open drain output).
Reference voltage
input
VREF
I
VCC1
Reference voltage input for the A/D and D/A converters.
AN0 to AN7
I
VCC1
AN0_0 to AN0_7
AN2_0 to AN2_7
I
VCC2
ADTRG
I
VCC1
External trigger input.
ANEX0, ANEX1
I
VCC1
Extended analog input.
DA0, DA1
O
VCC1
Output for the D/A converter.
VCC2
8-bit CMOS I/O ports. A direction register determines
whether each pin is used as an input port or an output
port. A pull-up resistor may be enabled or disabled for
input ports in 4-bit units.
VCC1
8-bit I/O ports having equivalent functions to P0.
However, P7_0, P7_1, and P8_5 are N-channel open
drain output ports. No pull-up resistor is provided. P8_5
is an input port for verifying the NMI pin level and shares
a pin with NMI.
UART0 to UART2,
UART5 to UART7
I2C mode
Serial interface
SI/O3, SI/O4
Multi-master I2Cbus interface
A/D converter
D/A converter
I/O ports
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_7
P3_0 to P3_7
P4_0 to P4_7
P5_0 to P5_7
P6_0 to P6_7
P7_0 to P7_7
P8_0 to P8_7
P9_0 to P9_7
P10_0 to P10_7
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
I/O
I/O
Description
Serial data I/O.
Transmit/receive clock I/O.
Analog input.
Page 23 of 109
M16C/65C Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of 13 compose a
register bank, and there are two register banks.
b31
b15
b8 b7
b0
R2
R0H (upper bits of R0)
R0L (lower bits of R0)
R3
R1H (upper bits of R1)
R1L (lower bits of R1)
Data registers (1)
R2
R3
A0
Address registers (1)
A1
FB
b19
Frame base registers (1)
b15
b0
INTBH
Interrupt table register
INTBL
INTBH is the 4 upper bits of the INTB register and INTBL
is the 16 lower bits.
b19
b0
PC
Program counter
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
b8
IPL
Flag register
b7
U
b0
I
O B
S
Z
D
C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note:
1. These registers compose a register bank. There are two register banks.
Figure 2.1
CPU Registers
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 24 of 109
M16C/65C Group
2.1
2. Central Processing Unit (CPU)
Data Registers (R0, R1, R2, and R3)
R0, R1, R2, and R3 are 16-bit registers used for transfer, arithmetic, and logic operations. R0 and R1 can
be split into upper (R0H/R1H) and lower (R0L/R1L) bits to be used separately as 8-bit data registers.
R0 can be combined with R2, and R3 can be combined with R1 and be used as 32-bit data registers
R2R0 and R3R1, respectively.
2.2
Address Registers (A0 and A1)
A0 and A1 are 16-bit registers used for indirect addressing, relative addressing, transfer, arithmetic, and
logic operations. A0 can be combined with A1 and used as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register that is used for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of a relocatable interrupt vector table.
2.5
Program Counter (PC)
The PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The USP and ISP stack pointers (SP) are each comprised of 16 bits. The U flag is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register used for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register that indicates the CPU state.
2.8.1
Carry Flag (C Flag)
The C flag retains a carry, borrow, or shift-out bit generated by the arithmetic/logic unit.
2.8.2
Debug Flag (D Flag)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z Flag)
The Z flag becomes 1 when an arithmetic operation results in 0. Otherwise, it becomes 0.
2.8.4
Sign Flag (S Flag)
The S flag becomes 1 when an arithmetic operation results in a negative value. Otherwise, it becomes
0.
2.8.5
Register Bank Select Flag (B Flag)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is 1.
2.8.6
Overflow Flag (O Flag)
The O flag becomes 1 when an arithmetic operation results in an overflow. Otherwise, it becomes 0.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 25 of 109
M16C/65C Group
2.8.7
2. Central Processing Unit (CPU)
Interrupt Enable Flag (I Flag)
The I flag enables maskable interrupts.
Maskable interrupts are disabled when the I flag is 0, and enabled when it is 1. The I flag becomes 0
when an interrupt request is accepted.
2.8.8
Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is 0. USP is selected when the U flag is 1.
The U flag becomes 0 when a hardware interrupt request is accepted, or the INT instruction of software
interrupt number 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from 0 to 7.
If a requested interrupt has higher priority than IPL, the interrupt request is enabled.
2.8.10
Reserved Areas
Only set these bits to 0. The read value is undefined.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 26 of 109
M16C/65C Group
3.
3.1
3. Address Space
Address Space
Address Space
The M16C/65C Group has a 1 MB address space from 00000h to FFFFFh. Address space is expandable to
4 MB with the memory area expansion function. Addresses 40000h to BFFFFh can be used as external
areas from bank 0 to bank 7. Figure 3.1 shows the Address Space. Areas that can be accessed vary
depending on processor mode and the status of each control bit.
Memory expansion mode
00000h
SFR
00400h
Internal RAM
The internal RAM is allocated
from address 00400h higher.
Reserved area
04000h
0D000h
0D800h
1 MB
address space
External area
SFR
External area
0E000h
Internal ROM
(data flash)
10000h
Internal ROM
(program ROM 2)
In 4 MB mode
When data flash is enabled
Bank 7
When program ROM 2
is enabled
Bank 6
Bank 5
14000h
External area
27000h
Bank 4
Bank 3
Bank 2
Reserved area
28000h
Bank 1
40000h
External area
Bank 0
BFFFFh
D0000h
512 KB × 8
Reserved area
Internal ROM
(program ROM 1)
Program ROM 1 is allocated from
address FFFFFh lower.
FFFFFh
Notes:
1. Do not access reserved areas.
2. The figure above applies under the following condition:
- The PM13 bit in the PM1 register is 0
(addresses 04000h to 0CFFFh and 80000h to CFFFFh are used as external areas)
Figure 3.1
Address Space
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 27 of 109
M16C/65C Group
3.2
3. Address Space
Memory Map
Special function registers (SFRs) are allocated from address 00000h to 003FFh and from 0D000h to
0D7FFh. Peripheral function control registers are located here. All blank areas within SFRs are reserved.
Do not access these areas.
Internal RAM is allocated from address 00400h and higher, with 10 KB of internal RAM allocated from
00400h to 02BFFh. Internal RAM is used not only for data storage, but also for the stack area when
subroutines are called or when an interrupt request is accepted.
The internal ROM is flash memory. Three internal ROM areas are available: data flash, program ROM 1,
and program ROM 2.
The data flash is allocated from 0E000h to 0FFFFh. This data flash area is mostly used for data storage, but
can also store programs.
Program ROM 2 is allocated from 10000h to 13FFFh. Program ROM 1 is allocated from FFFFFh and lower,
with the 64 KB program ROM 1 area allocated from address F0000h to FFFFFh.
The special page vectors are allocated from FFE00h to FFFD7h. They are used for the JMPS and JSRS
instructions. Refer to the M16C/60, M16C/20, M16C/Tiny Series Software Manual for details.
The fixed vector table for interrupts is allocated from FFFDCh to FFFFFh.
The 256 bytes beginning with the start address set in the INTB register compose the relocatable vector table
for interrupts.
Figure 3.2 shows the Memory Map.
00000h
Internal RAM
00400h
SFR
Internal RAM
XXXXXh
Size
Address XXXXXh
12 KB
033FFh
20 KB
053FFh
0D000h
31 KB
07FFFh
0D800h
47 KB
0BFFFh
0E000h
Reserved area (1)
10000h
14000h
27000h
SFR
External area
Internal ROM
(data flash)
Internal ROM
(program ROM 2)
13000h
13FF0h
13FFFh
On-chip debugger
monitor area
User boot code area
External area
Reserved area (1)
28000h
Relocatable vector table
External area
256 bytes beginning with the
start address set in the INTB
register
Program ROM 1
Size
Address YYYYYh
128 KB
E0000h
256 KB
C0000h
384 KB
A0000h
512 KB
80000h
80000h
Reserved area (1)
FFE00h
FFFD8h
YYYYYh
Internal ROM
(program ROM 1)
FFFFFh
FFFDCh
Special page vector table
Reserved area (3)
Fixed vector table
Address for ID code stored
FFFFFh
OFS1 address
Notes:
1. Do not access reserved areas.
2. The figure above applies under the following conditions:
- Memory expansion mode
- The PM10 bit in the PM1 register is 1
(addresses 0E000h to 0FFFFh are used as data flash)
- The PRG2C0 bit in the PRG2C register is 0 (program ROM 2 enabled)
- The PM13 bit in the PM1 register is 1
(all areas in internal RAM, and the program ROM 1 area from 80000h are usable)
3. Do not change the data from FFh.
Figure 3.2
Memory Map
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 28 of 109
M16C/65C Group
3.3
3. Address Space
Accessible Area in Each Mode
Areas that can be accessed vary depending on processor mode and the status of each control bit. Figure
3.3 shows the Accessible Area in Each Mode.
In single-chip mode, the SFRs, internal RAM, and internal ROM can be accessed.
In memory expansion mode, the SFRs, internal RAM, internal ROM, and external areas can be accessed.
Address space is expandable to 4 MB with the memory area expansion function.
In microprocessor mode, the SFRs, internal RAM, and external areas can be accessed. Address space is
expandable to 4 MB with the memory area expansion function. Allocate ROM to the fixed vector table
from FFFDCh to FFFFFh.
Single-Chip Mode
00000h
SFR
00400h
Memory Expansion Mode
00000h
SFR
00000h
00400h
00400h
Internal RAM
Internal RAM
SFR
0D000h
0D800h
Reserved area
0D800h
0E000h
Internal ROM
(data flash)
Internal ROM
(program ROM 2)
0E000h
10000h
14000h
10000h
14000h
27000h
SFR
External area
SFR
Internal RAM
Reserved area
Reserved area
0D000h
Microprocessor Mode
Reserved area
0D000h
SFR
0D800h
Internal ROM
(data flash)
Internal ROM
(program ROM 2)
External area
External area
Reserved area
27000h
Reserved area
28000h
28000h
External area
Reserved area
80000h
Reserved area
Internal ROM
(program ROM 1)
Internal ROM
(program ROM 1)
FFFFFh
External area
FFFFFh
FFFFFh
Notes:
1. Do not access reserved areas.
2. The figure above applies under the following conditions:
Single-chip mode and memory expansion mode
- The PM10 bit in the PM1 register is 1
(addresses 0E000h to 0FFFFh are used as data flash)
- The PRG2C0 bit in the PRG2C register is 0 (program ROM 2 enabled)
- The PM13 bit in the PM1 register is 1
(all areas in internal RAM, and the program ROM 1 area from 80000h are usable)
Microprocessor mode
- The PM10 bit is 0 (addresses 0E000h to 0FFFFh are used as the CS2 area)
- The PRG2C0 bit is 1 (program ROM 2 disabled)
Figure 3.3
Accessible Area in Each Mode
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 29 of 109
M16C/65C Group
4.
4. Special Function Registers (SFRs)
Special Function Registers (SFRs)
4.1
SFRs
An SFR is a control register for a peripheral function.
Table 4.1
SFR Information (1) (1)
Address
0000h
0001h
0002h
0003h
Register
Symbol
0000 0000b
(CNVSS pin is low)
0000 0011b
(CNVSS pin is high) (2)
0000 1000b
0100 1000b
0010 0000b
01h
XXXX XX00b
00h
00h
0004h
Processor Mode Register 0
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Chip Select Control Register
External Area Recovery Cycle Control Register
Protect Register
Data Bank Register
Oscillation Stop Detection Register
PM1
CM0
CM1
CSR
EWR
PRCR
DBR
CM2
Program 2 Area Control Register
External Area Wait Control Expansion Register
Peripheral Clock Select Register
PRG2C
EWC
PCLKR
XXXX XX00b
00h
0000 0011b
Clock Prescaler Reset Flag
Peripheral Clock Stop Register 1
CPSRF
PCLKSTP1
0XXX XXXXb
0XXX XX00b
0018h
Reset Source Determine Register
RSTFR
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
Voltage Detector 2 Flag Register
Voltage Detector Operation Enable Register
Chip Select Expansion Control Register
PLL Control Register 0
Processor Mode Register 2
PM0
Reset Value
VCR1
VCR2
CSE
PLC0
PM2
0X00 0010b (3)
XX00 001Xb
(hardware reset) (4)
0000 1000b (5)
00h (5)
00h
0X01 X010b
XX00 0X01b
X: Undefined
Notes:
1.
The blank areas are reserved. No access is allowed.
2.
Software reset, watchdog timer reset, oscillator stop detect reset, voltage monitor 1 reset, and voltage monitor 2 reset
do not affect the following bits: bits PM01 and PM00 in the PM0 register.
3.
Oscillator stop detect reset does not affect bits CM20, CM21, and CM27.
4.
The state of bits in the RSTFR register depends on the reset type.
5.
This is the reset value after hardware reset. Refer to the explanation of each register for details.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 30 of 109
M16C/65C Group
Table 4.2
Address
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
4. Special Function Registers (SFRs)
SFR Information (2) (1)
Register
Symbol
Reset Value
40 MHz On-Chip Oscillator Control Register 0
FRA0
XXXX XX00b
Voltage Monitor Function Select Register
VWCE
00h
Voltage Detector 1 Level Select Register
VD1LS
0000 1010b (2)
Voltage Monitor 0 Control Register
Voltage Monitor 1 Control Register
Voltage Monitor 2 Control Register
VW0C
VW1C
VW2C
1000 XX10b (2)
1000 1010b (2)
1000 0X10b (2)
X: Undefined
Notes:
1.
The blank areas are reserved. No access is allowed.
2.
This is the reset value after hardware reset. Refer to the explanation of each register for details.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 31 of 109
M16C/65C Group
Table 4.3
4. Special Function Registers (SFRs)
SFR Information (3) (1)
Address
0040h
Register
Symbol
Reset Value
0041h
0042h
INT7 Interrupt Control Register
INT7IC
XX00 X000b
0043h
INT6 Interrupt Control Register
INT6IC
XX00 X000b
0044h
0045h
INT3 Interrupt Control Register
Timer B5 Interrupt Control Register
Timer B4 Interrupt Control Register
UART1 Bus Collision Detection Interrupt Control Register
Timer B3 Interrupt Control Register
UART0 Bus Collision Detection Interrupt Control Register
SI/O4 Interrupt Control Register
INT5 Interrupt Control Register
SI/O3 Interrupt Control Register
INT4 Interrupt Control Register
UART2 Bus Collision Detection Interrupt Control Register
INT3IC
TB5IC
TB4IC
U1BCNIC
TB3IC
U0BCNIC
S4IC
INT5IC
S3IC
INT4IC
BCNIC
XX00 X000b
XXXX X000b
0046h
0047h
0048h
0049h
004Ah
XXXX X000b
XXXX X000b
XX00 X000b
XX00 X000b
XXXX X000b
004Bh
DMA0 Interrupt Control Register
DM0IC
XXXX X000b
004Ch
DMA1 Interrupt Control Register
DM1IC
XXXX X000b
004Dh
Key Input Interrupt Control Register
KUPIC
XXXX X000b
004Eh
A/D Conversion Interrupt Control Register
ADIC
XXXX X000b
004Fh
UART2 Transmit Interrupt Control Register
S2TIC
XXXX X000b
0050h
UART2 Receive Interrupt Control Register
S2RIC
XXXX X000b
0051h
UART0 Transmit Interrupt Control Register
S0TIC
XXXX X000b
0052h
UART0 Receive Interrupt Control Register
S0RIC
XXXX X000b
0053h
UART1 Transmit Interrupt Control Register
S1TIC
XXXX X000b
0054h
UART1 Receive Interrupt Control Register
S1RIC
XXXX X000b
0055h
Timer A0 Interrupt Control Register
TA0IC
XXXX X000b
0056h
Timer A1 Interrupt Control Register
TA1IC
XXXX X000b
0057h
Timer A2 Interrupt Control Register
TA2IC
XXXX X000b
0058h
Timer A3 Interrupt Control Register
TA3IC
XXXX X000b
0059h
Timer A4 Interrupt Control Register
TA4IC
XXXX X000b
005Ah
Timer B0 Interrupt Control Register
TB0IC
XXXX X000b
005Bh
Timer B1 Interrupt Control Register
TB1IC
XXXX X000b
005Ch
Timer B2 Interrupt Control Register
TB2IC
XXXX X000b
005Dh
INT0 Interrupt Control Register
INT0IC
XX00 X000b
005Eh
INT1 Interrupt Control Register
INT1IC
XX00 X000b
005Fh
INT2 Interrupt Control Register
INT2IC
XX00 X000b
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 32 of 109
M16C/65C Group
Table 4.4
Address
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
0080h to
017Fh
4. Special Function Registers (SFRs)
SFR Information (4) (1)
Register
DMA2 Interrupt Control Register
DMA3 Interrupt Control Register
UART5 Bus Collision Detection Interrupt Control Register
CEC1 Interrupt Control Register
UART5 Transmit Interrupt Control Register
CEC2 Interrupt Control Register
UART5 Receive Interrupt Control Register
UART6 Bus Collision Detection Interrupt Control Register
Real-Time Clock Periodic Interrupt Control Register
Symbol
Reset Value
DM2IC
DM3IC
U5BCNIC
CEC1IC
S5TIC
CEC2IC
S5RIC
U6BCNIC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
UART6 Transmit Interrupt Control Register
Real-Time Clock Compare Interrupt Control Register
UART6 Receive Interrupt Control Register
UART7 Bus Collision Detection Interrupt Control Register
Remote Control Signal Receiver 0 Interrupt Control Register
UART7 Transmit Interrupt Control Register
Remote Control Signal Receiver 1 Interrupt Control Register
UART7 Receive Interrupt Control Register
RTCTIC
S6TIC
RTCCIC
S6RIC
U7BCNIC
PMC0IC
S7TIC
PMC1IC
S7RIC
I2C-bus Interface Interrupt Control Register
SCL/SDA Interrupt Control Register
IICIC
SCLDAIC
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
XXXX X000b
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 33 of 109
M16C/65C Group
Table 4.5
Address
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
4. Special Function Registers (SFRs)
SFR Information (5) (1)
Register
Symbol
Reset Value
XXh
XXh
0Xh
DMA0 Source Pointer
SAR0
DMA0 Destination Pointer
DAR0
XXh
XXh
0Xh
DMA0 Transfer Counter
TCR0
XXh
XXh
DMA0 Control Register
DM0CON
0000 0X00b
DMA1 Source Pointer
SAR1
XXh
XXh
0Xh
DMA1 Destination Pointer
DAR1
XXh
XXh
0Xh
DMA1 Transfer Counter
TCR1
XXh
XXh
DMA1 Control Register
DM1CON
0000 0X00b
DMA2 Source Pointer
SAR2
XXh
XXh
0Xh
DMA2 Destination Pointer
DAR2
XXh
XXh
0Xh
DMA2 Transfer Counter
TCR2
XXh
XXh
DMA2 Control Register
DM2CON
0000 0X00b
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 34 of 109
M16C/65C Group
Table 4.6
Address
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
4. Special Function Registers (SFRs)
SFR Information (6) (1)
Register
Symbol
Reset Value
XXh
XXh
0Xh
DMA3 Source Pointer
SAR3
DMA3 Destination Pointer
DAR3
XXh
XXh
0Xh
DMA3 Transfer Counter
TCR3
XXh
XXh
DMA3 Control Register
DM3CON
0000 0X00b
Timer B0-1 Register
TB01
Timer B1-1 Register
TB11
Timer B2-1 Register
TB21
Pulse Period/Pulse Width Measurement Mode Function Select
Register 1
XXh
XXh
XXh
XXh
XXh
XXh
PPWFS1
XXXX X000b
TBCS0
TBCS1
00h
X0h
TCKDIVC0
0000 X000b
TACS0
TACS1
TACS2
00h
00h
X0h
PWMFS
TAPOFS
0XX0 X00Xb
XXX0 0000b
Timer A Output Waveform Change Enable Register
TAOW
XXX0 X00Xb
Three-Phase Protect Control Register
TPRC
00h
Timer B Count Source Select Register 0
Timer B Count Source Select Register 1
Timer AB Division Control Register 0
Timer A Count Source Select Register 0
Timer A Count Source Select Register 1
Timer A Count Source Select Register 2
16-bit Pulse Width Modulation Mode Function Select Register
Timer A Waveform Output Function Select Register
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 35 of 109
M16C/65C Group
Table 4.7
4. Special Function Registers (SFRs)
SFR Information (7) (1)
Address
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
Note:
1.
Register
Symbol
Timer B3-1 Register
TB31
Timer B4-1 Register
TB41
Timer B5-1 Register
TB51
Pulse Period/Pulse Width Measurement Mode Function Select Register 2
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
PPWFS2
XXXX X000b
Timer B Count Source Select Register 2
Timer B Count Source Select Register 3
TBCS2
TBCS3
00h
X0h
PMC0 Function Select Register 0
PMC0 Function Select Register 1
PMC0 Function Select Register 2
PMC0 Function Select Register 3
PMC0 Status Register
PMC0 Interrupt Source Select Register
PMC0 Compare Control Register
PMC0 Compare Data Register
PMC1 Function Select Register 0
PMC1 Function Select Register 1
PMC1 Function Select Register 2
PMC1 Function Select Register 3
PMC1 Status Register
PMC1 Interrupt Source Select Register
PMC0CON0
PMC0CON1
PMC0CON2
PMC0CON3
PMC0STS
PMC0INT
PMC0CPC
PMC0CPD
PMC1CON0
PMC1CON1
PMC1CON2
PMC1CON3
PMC1STS
PMC1INT
00h
00XX 0000b
0000 00X0b
00h
00h
00h
XXX0 X000b
00h
XXX0 X000b
XXXX 0X00b
0000 00X0b
00h
X000 X00Xb
X000 X00Xb
IFSR3A
IFSR2A
IFSR
00h
00h
00h
Interrupt Source Select Register 3
Interrupt Source Select Register 2
Interrupt Source Select Register
Address Match Interrupt Enable Register
Address Match Interrupt Enable Register 2
AIER
AIER2
XXXX XX00b
XXXX XX00b
X: Undefined
The blank areas are reserved. No access is allowed.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 36 of 109
M16C/65C Group
Table 4.8
4. Special Function Registers (SFRs)
SFR Information (8) (1)
Address
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
Register
Symbol
Reset Value
00h
00h
X0h
Address Match Interrupt Register 0
RMAD0
Address Match Interrupt Register 1
RMAD1
00h
00h
X0h
Address Match Interrupt Register 2
RMAD2
00h
00h
X0h
Address Match Interrupt Register 3
RMAD3
00h
00h
X0h
0220h
Flash Memory Control Register 0
FMR0
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
Flash Memory Control Register 1
Flash Memory Control Register 2
Flash Memory Control Register 3
FMR1
FMR2
FMR3
0000 0001b
(Other than user boot mode)
0010 0001b
(User boot mode)
00X0 XX0Xb
XXXX 0000b
XXXX 0000b
Flash Memory Control Register 6
FMR6
XX0X XX00b
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 37 of 109
M16C/65C Group
Table 4.9
4. Special Function Registers (SFRs)
SFR Information (9) (1)
Address
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
024Ch
024Dh
024Eh
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
026Ch
026Dh
026Eh
026Fh
Register
UART0 Special Mode Register 4
UART0 Special Mode Register 3
UART0 Special Mode Register 2
UART0 Special Mode Register
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
Symbol
Reset Value
U0SMR4
U0SMR3
U0SMR2
U0SMR
U0MR
U0BRG
UART0 Transmit Buffer Register
U0TB
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
U0C0
U0C1
UART0 Receive Buffer Register
U0RB
UART Transmit/Receive Control Register 2
UCON
00h
000X 0X0Xb
X000 0000b
X000 0000b
00h
XXh
XXh
XXh
0000 1000b
00XX 0010b
XXh
XXh
X000 0000b
UCLKSEL0
X0h
U1SMR4
U1SMR3
U1SMR2
U1SMR
U1MR
U1BRG
00h
000X 0X0Xb
X000 0000b
X000 0000b
00h
XXh
XXh
XXh
0000 1000b
00XX 0010b
XXh
XXh
UART Clock Select Register
UART1 Special Mode Register 4
UART1 Special Mode Register 3
UART1 Special Mode Register 2
UART1 Special Mode Register
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Register
UART1 Transmit Buffer Register
U1TB
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
U1C0
U1C1
UART1 Receive Buffer Register
U1RB
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
UART2 Transmit Buffer Register
U2TB
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
U2C0
U2C1
UART2 Receive Buffer Register
U2RB
00h
000X 0X0Xb
X000 0000b
X000 0000b
00h
XXh
XXh
XXh
0000 1000b
0000 0010b
XXh
XXh
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 38 of 109
M16C/65C Group
Table 4.10
4. Special Function Registers (SFRs)
SFR Information (10) (1)
SI/O3 Transmit/Receive Register
S3TRR
Reset Value
XXh
SI/O3 Control Register
SI/O3 Bit Rate Register
SI/O4 Transmit/Receive Register
S3C
S3BRG
S4TRR
0100 0000b
XXh
XXh
SI/O4 Control Register
SI/O4 Bit Rate Register
SI/O3, 4 Control Register 2
S4C
S4BRG
S34C2
0100 0000b
XXh
00XX X0X0b
U5SMR4
U5SMR3
U5SMR2
U5SMR
U5MR
U5BRG
00h
000X 0X0Xb
X000 0000b
X000 0000b
00h
XXh
XXh
XXh
0000 1000b
0000 0010b
XXh
XXh
Address
0270h
0271h
0272h
0273h
0274h
0275h
0276h
0277h
0278h
0279h
027Ah
027Bh
027Ch
027Dh
027Eh
027Fh
0280h
0281h
0282h
0283h
0284h
0285h
0286h
0287h
0288h
0289h
028Ah
028Bh
028Ch
028Dh
028Eh
028Fh
0290h
0291h
0292h
0293h
0294h
0295h
0296h
0297h
0298h
0299h
029Ah
029Bh
029Ch
029Dh
029Eh
029Fh
Note:
1.
Register
UART5 Special Mode Register 4
UART5 Special Mode Register 3
UART5 Special Mode Register 2
UART5 Special Mode Register
UART5 Transmit/Receive Mode Register
UART5 Bit Rate Register
Symbol
UART5 Transmit Buffer Register
U5TB
UART5 Transmit/Receive Control Register 0
UART5 Transmit/Receive Control Register 1
U5C0
U5C1
UART5 Receive Buffer Register
U5RB
UART6 Special Mode Register 4
UART6 Special Mode Register 3
UART6 Special Mode Register 2
UART6 Special Mode Register
UART6 Transmit/Receive Mode Register
UART6 Bit Rate Register
U6SMR4
U6SMR3
U6SMR2
U6SMR
U6MR
U6BRG
UART6 Transmit Buffer Register
U6TB
UART6 Transmit/Receive Control Register 0
UART6 Transmit/Receive Control Register 1
U6C0
U6C1
UART6 Receive Buffer Register
U6RB
00h
000X 0X0Xb
X000 0000b
X000 0000b
00h
XXh
XXh
XXh
0000 1000b
0000 0010b
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 39 of 109
M16C/65C Group
Table 4.11
4. Special Function Registers (SFRs)
SFR Information (11) (1)
Address
02A0h
02A1h
02A2h
02A3h
02A4h
02A5h
02A6h
02A7h
02A8h
02A9h
02AAh
02ABh
02ACh
02ADh
02AEh
02AFh
02B0h
02B1h
02B2h
02B3h
02B4h
02B5h
02B6h
02B7h
02B8h
02B9h
02BAh
02BBh
02BCh
02BDh
02BEh
02BFh
02C0h to
02FFh
Register
UART7 Special Mode Register 4
UART7 Special Mode Register 3
UART7 Special Mode Register 2
UART7 Special Mode Register
UART7 Transmit/Receive Mode Register
UART7 Bit Rate Register
Symbol
Reset Value
U7SMR4
U7SMR3
U7SMR2
U7SMR
U7MR
U7BRG
S00
00h
000X 0X0Xb
X000 0000b
X000 0000b
00h
XXh
XXh
XXh
0000 1000b
0000 0010b
XXh
XXh
XXh
S0D0
S1D0
S20
S2D0
S3D0
S4D0
S10
S11
S0D1
S0D2
0000 000Xb
00h
00h
0001 1010b
0011 0000b
00h
0001 000Xb
XXXX X000b
0000 000Xb
0000 000Xb
UART7 Transmit Buffer Register
U7TB
UART7 Transmit/Receive Control Register 0
UART7 Transmit/Receive Control Register 1
U7C0
U7C1
UART7 Receive Buffer Register
U7RB
I2C0 Data Shift Register
I2C0 Address Register 0
I2C0 Control Register 0
I2C0 Clock Control Register
I2C0 Start/Stop Condition Control Register
I2C0 Control Register 1
I2C0 Control Register 2
I2C0 Status Register 0
I2C0 Status Register 1
I2C0 Address Register 1
I2C0 Address Register 2
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 40 of 109
M16C/65C Group
Table 4.12
Address
0300h
0301h
0302h
0303h
0304h
0305h
0306h
0307h
0308h
0309h
030Ah
030Bh
030Ch
030Dh
030Eh
030Fh
0310h
0311h
0312h
0313h
0314h
0315h
0316h
0317h
0318h
0319h
031Ah
031Bh
031Ch
031Dh
031Eh
031Fh
0320h
0321h
0322h
0323h
0324h
0325h
0326h
0327h
0328h
0329h
032Ah
032Bh
032Ch
032Dh
032Eh
032Fh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (12) (1)
Register
Timer B3/B4/B5 Count Start Flag
Symbol
TBSR
Timer A1-1 Register
TA11
Timer A2-1 Register
TA21
Timer A4-1 Register
TA41
Three-Phase PWM Control Register 0
Three-Phase PWM Control Register 1
Three-Phase Output Buffer Register 0
Three-Phase Output Buffer Register 1
Dead Time Timer
Timer B2 Interrupt Generation Frequency Set Counter
Position-Data-Retain Function Control Register
INVC0
INVC1
IDB0
IDB1
DTT
ICTB2
PDRF
Timer B3 Register
TB3
Timer B4 Register
TB4
Timer B5 Register
TB5
Port Function Control Register
Reset Value
000X XXXXb
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
XX11 1111b
XX11 1111b
XXh
XXh
XXXX 0000b
XXh
XXh
XXh
XXh
XXh
XXh
PFCR
0011 1111b
Timer B3 Mode Register
Timer B4 Mode Register
Timer B5 Mode Register
TB3MR
TB4MR
TB5MR
00XX 0000b
00XX 0000b
00XX 0000b
Count Start Flag
TABSR
00h
One-Shot Start Flag
Trigger Select Register
Increment/Decrement Flag
ONSF
TRGSR
UDF
00h
00h
00h
Timer A0 Register
TA0
Timer A1 Register
TA1
Timer A2 Register
TA2
Timer A3 Register
TA3
Timer A4 Register
TA4
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
The blank areas are reserved. No access is allowed.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 41 of 109
M16C/65C Group
Table 4.13
4. Special Function Registers (SFRs)
SFR Information (13) (1)
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
Reset Value
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
00h
00h
00h
00XX 0000b
00XX 0000b
00XX 0000b
X000 0000b
RTCSEC
RTCMIN
RTCHR
RTCWK
RTCCR1
RTCCR2
RTCCSR
00h
X000 0000b
XX00 0000b
XXXX X000b
0000 X00Xb
X000 0000b
XXX0 0000b
Real-Time Clock Second Compare Data Register
Real-Time Clock Minute Compare Data Register
Real-Time Clock Hour Compare Data Register
RTCCSEC
RTCCMIN
RTCCHR
X000 0000b
X000 0000b
X000 0000b
CEC Function Control Register 1
CEC Function Control Register 2
CEC Function Control Register 3
CEC Function Control Register 4
CEC Flag Register
CEC Interrupt Source Select Register
CEC Transmit Buffer Register 1
CEC Transmit Buffer Register 2
CEC Receive Buffer Register 1
CEC Receive Buffer Register 2
CEC Receive Follower Address Set Register 1
CEC Receive Follower Address Set Register 2
CECC1
CECC2
CECC3
CECC4
CECFLG
CISEL
CCTB1
CCTB2
CCRB1
CCRB2
CRADRI1
CRADRI2
XXXX X000b
00h
XXXX 0000b
00h
00h
00h
00h
XXXX XX00b
00h
XXXX X000b
00h
00h
Address
0330h
0331h
0332h
0333h
0334h
0335h
0336h
0337h
0338h
0339h
033Ah
033Bh
033Ch
033Dh
033Eh
033Fh
0340h
0341h
0342h
0343h
0344h
0345h
0346h
0347h
0348h
0349h
034Ah
034Bh
034Ch
034Dh
034Eh
034Fh
0350h
0351h
0352h
0353h
0354h
0355h
0356h
0357h
0358h
0359h
035Ah
035Bh
035Ch
035Dh
035Eh
035Fh
Register
Symbol
Timer B0 Register
TB0
Timer B1 Register
TB1
Timer B2 Register
TB2
Timer A0 Mode Register
Timer A1 Mode Register
Timer A2 Mode Register
Timer A3 Mode Register
Timer A4 Mode Register
Timer B0 Mode Register
Timer B1 Mode Register
Timer B2 Mode Register
Timer B2 Special Mode Register
Real-Time Clock Second Data Register
Real-Time Clock Minute Data Register
Real-Time Clock Hour Data Register
Real-Time Clock Day Data Register
Real-Time Clock Control Register 1
Real-Time Clock Control Register 2
Real-Time Clock Count Source Select Register
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 42 of 109
M16C/65C Group
Table 4.14
Address
0360h
0361h
0362h
0363h
0364h
0365h
0366h
0367h
0368h
0369h
036Ah
036Bh
036Ch
036Dh
036Eh
036Fh
0370h
0371h
0372h
0373h
0374h
0375h
0376h
0377h
0378h
0379h
037Ah
037Bh
037Ch
037Dh
037Eh
037Fh
0380h to
038Fh
4. Special Function Registers (SFRs)
SFR Information (14) (1)
Pull-Up Control Register 0
Pull-Up Control Register 1
Register
Symbol
PUR0
PUR1
Pull-Up Control Register 2
Pull-Up Control Register 3
PUR2
PUR3
0000 0010b
00h
00h
Port Control Register
PCR
0000 0XX0b
NMIDF
XXXX X000b
PWM Control Register 0
PWMCON0
00h
PWM0 Prescaler
PWM0 Register
PWM1 Prescaler
PWM1 Register
PWM Control Register 1
PWMPRE0
PWMREG0
PWMPRE1
PWMREG1
PWMCON1
00h
00h
00h
00h
00h
CSPR
WDTR
WDTS
WDC
00h (3)
XXh
XXh
00XX XXXXb
NMI/SD Digital Filter Register
Count Source Protection Mode Register
Watchdog Timer Refresh Register
Watchdog Timer Start Register
Watchdog Timer Control Register
Reset Value
00h
0000 0000b (2)
X: Undefined
Notes:
1.
The blank areas are reserved. No access is allowed.
2.
Values after hardware reset, power-on reset, or voltage monitor 0 reset are as follows:
- 00000000b when a low-level signal is input to the CNVSS pin
- 00000010b when a high-level signal is input to the CNVSS pin
Values after voltage monitor 1 reset, voltage monitor 2 reset, software reset, watchdog timer reset, or oscillation stop
detect reset are as follows:
- 00000000b when bits PM01 and PM00 in the PM0 register are 00b (single-chip mode).
- 00000010b when bits PM01 and PM00 in the PM0 register are 01b (memory expansion mode) or 11b
(microprocessor mode).
3.
When the CSPROINI bit in the OFS1 address is 0, the reset value is 1000 0000b.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 43 of 109
M16C/65C Group
Table 4.15
Address
0390h
0391h
0392h
0393h
0394h
0395h
0396h
0397h
0398h
0399h
039Ah
039Bh
039Ch
039Dh
039Eh
039Fh
03A0h
03A1h
03A2h
03A3h
03A4h
03A5h
03A6h
03A7h
03A8h
03A9h
03AAh
03ABh
03ACh
03ADh
03AEh
03AFh
03B0h
03B1h
03B2h
03B3h
03B4h
03B5h
03B6h
03B7h
03B8h
03B9h
03BAh
03BBh
03BCh
03BDh
03BEh
03BFh
4. Special Function Registers (SFRs)
SFR Information (15) (1)
Register
DMA2 Source Select Register
Symbol
DM2SL
Reset Value
00h
DMA3 Source Select Register
DM3SL
00h
DMA0 Source Select Register
DM0SL
00h
DMA1 Source Select Register
DM1SL
00h
Open-Circuit Detection Assist Function Register
AINRST
XX00 XXXXb
SFR Snoop Address Register
CRCSAR
CRC Mode Register
CRCMR
CRC Data Register
CRCD
CRC Input Register
CRCIN
XXXX XXXXb
00XX XXXXb
0XXX XXX0b
XXh
XXh
XXh
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 44 of 109
M16C/65C Group
Table 4.16
Address
03C0h
03C1h
03C2h
03C3h
03C4h
03C5h
03C6h
03C7h
03C8h
03C9h
03CAh
03CBh
03CCh
03CDh
03CEh
03CFh
03D0h
03D1h
03D2h
03D3h
03D4h
03D5h
03D6h
03D7h
03D8h
03D9h
03DAh
03DBh
03DCh
03DDh
03DEh
03DFh
03E0h
03E1h
03E2h
03E3h
03E4h
03E5h
03E6h
03E7h
03E8h
03E9h
03EAh
03EBh
03ECh
03EDh
03EEh
03EFh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (16) (1)
Register
Symbol
A/D Register 0
AD0
A/D Register 1
AD1
A/D Register 2
AD2
A/D Register 3
AD3
A/D Register 4
AD4
A/D Register 5
AD5
A/D Register 6
AD6
A/D Register 7
AD7
Reset Value
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
XXXX XXXXb
0000 00XXb
A/D Control Register 2
ADCON2
0000 X00Xb
A/D Control Register 0
A/D Control Register 1
D/A0 Register
ADCON0
ADCON1
DA0
0000 0XXXb
0000 X000b
00h
DA1
00h
DACON
00h
D/A1 Register
D/A Control Register
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
Port P3 Register
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
Port P5 Register
Port P4 Direction Register
Port P5 Direction Register
Port P6 Register
Port P7 Register
Port P6 Direction Register
Port P7 Direction Register
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
P7
PD6
PD7
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
X: Undefined
The blank areas are reserved. No access is allowed.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 45 of 109
M16C/65C Group
Table 4.17
Address
03F0h
03F1h
03F2h
03F3h
03F4h
03F5h
03F6h
03F7h
03F8h
03F9h
03FAh
03FBh
03FCh
03FDh
03FEh
03FFh
4. Special Function Registers (SFRs)
SFR Information (17) (1)
Port P8 Register
Port P9 Register
Port P8 Direction Register
Port P9 Direction Register
Port P10 Register
Port P11 Register
Port P10 Direction Register
Port P11 Direction Register
Port P12 Register
Port P13 Register
Port P12 Direction Register
Port P13 Direction Register
Port P14 Register
Register
Symbol
P8
P9
PD8
PD9
P10
P11
PD10
PD11
P12
P13
PD12
PD13
P14
Reset Value
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
Port P14 Direction Register
PD14
XXXX XX00b
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 46 of 109
M16C/65C Group
Table 4.18
4. Special Function Registers (SFRs)
SFR Information (18) (1)
Address
D080h
D081h
D082h
D083h
D084h
D085h
D086h
D087h
D088h
D089h
D08Ah
D08Bh
D08Ch
D08Dh
D08Eh
D08Fh
D090h
D091h
D092h
D093h
D094h
D095h
D096h
D097h
D098h
D099h
D09Ah
D09Bh
D09Ch
D09Dh
D09Eh
D09Fh
Register
Symbol
PMC0 Header Pattern Set Register (Min)
PMC0HDPMIN
PMC0 Header Pattern Set Register (Max)
PMC0HDPMAX
PMC0 Data 0 Pattern Set Register (Min)
PMC0 Data 0 Pattern Set Register (Max)
PMC0 Data 1 Pattern Set Register (Min)
PMC0 Data 1 Pattern Set Register (Max)
PMC0D0PMIN
PMC0D0PMAX
PMC0D1PMIN
PMC0D1PMAX
PMC0 Measurements Register
PMC0 Receive Data Store Register 0
PMC0 Receive Data Store Register 1
PMC0 Receive Data Store Register 2
PMC0 Receive Data Store Register 3
PMC0 Receive Data Store Register 4
PMC0 Receive Data Store Register 5
PMC0 Receive Bit Count Register
PMC0TIM
PMC0DAT0
PMC0DAT1
PMC0DAT2
PMC0DAT3
PMC0DAT4
PMC0DAT5
PMC0RBIT
PMC1 Header Pattern Set Register (Min)
PMC1HDPMIN
PMC1 Header Pattern Set Register (Max)
PMC1HDPMAX
PMC1 Data 0 Pattern Set Register (Min)
PMC1 Data 0 Pattern Set Register (Max)
PMC1 Data 1 Pattern Set Register (Min)
PMC1 Data 1 Pattern Set Register (Max)
PMC1D0PMIN
PMC1D0PMAX
PMC1D1PMIN
PMC1D1PMAX
PMC1 Measurements Register
PMC1TIM
Reset Value
0000 0000b
XXXX X000b
0000 0000b
XXXX X000b
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
XX00 0000b
0000 0000b
XXXX X000b
0000 0000b
XXXX X000b
00h
00h
00h
00h
00h
00h
X: Undefined
Note:
1.
The blank areas are reserved. No access is allowed.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 47 of 109
M16C/65C Group
4.2
4. Special Function Registers (SFRs)
Notes on SFRs
4.2.1
Register Settings
Table 4.19 lists Registers with Write-Only Bits and registers whose function differs between reading and
writing. Set these registers with immediate values. Do not use read-modify-write instructions. When
establishing the next value by altering the existing value, write the existing value to the RAM as well as
to the register. Transfer the next value to the register after making changes in the RAM.
Read-modify-write instructions can be used when writing to the no register bits.
Table 4.19
Registers with Write-Only Bits
Address
0249h
024Bh to 024Ah
0259h
025Bh to 025Ah
0269h
026Bh to 026Ah
0273h
Register
UART0 Bit Rate Register
UART0 Transmit Buffer Register
UART1 Bit Rate Register
UART1 Transmit Buffer Register
UART2 Bit Rate Register
UART2 Transmit Buffer Register
SI/O3 Bit Rate Register
Symbol
U0BRG
U0TB
U1BRG
U1TB
U2BRG
U2TB
S3BRG
0277h
SI/O4 Bit Rate Register
S4BRG
0289h
UART5 Bit Rate Register
U5BRG
028Bh to 028Ah
0299h
029Bh to 029Ah
02A9h
02ABh to 02AAh
02B6h
02B8h
UART5 Transmit Buffer Register
UART6 Bit Rate Register
UART6 Transmit Buffer Register
UART7 Bit Rate Register
U5TB
U6BRG
U6TB
U7BRG
UART7 Transmit Buffer Register
U7TB
I2C0 Control Register 1
S3D0
I2C0 Status Register 0
S10
0303h to 0302h
Timer A1-1 Register
TA11
0305h to 0304h
Timer A2-1 Register
TA21
0307h to 0306h
Timer A4-1 Register
TA41
030Ah
Three-Phase Output Buffer Register 0
IDB0
030Bh
Three-Phase Output Buffer Register 1
IDB1
030Ch
Dead Time Timer
DTT
030Dh
Timer B2 Interrupt Generation Frequency Set Counter
ICTB2
0327h to 0326h
Timer A0 Register
TA0
0329h to 0328h
Timer A1 Register
TA1
032Bh to 032Ah
Timer A2 Register
TA2
032Dh to 032Ch
Timer A3 Register
TA3
032Fh to 032Eh
Timer A4 Register
TA4
037Dh
Watchdog Timer Refresh Register
WDTR
037Eh
Watchdog Timer Start Register
WDTS
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 48 of 109
M16C/65C Group
Table 4.20
4. Special Function Registers (SFRs)
Read-Modify-Write Instructions
Function
Transfer
Bit processing
Shifting
Arithmetic operation
Decimal operation
Logical operation
Jump
Mnemonic
MOVDir
BCLR, BMCnd, BNOT, BSET, BTSTC, and BTSTS
ROLC, RORC, ROT, SHA, and SHL
ABS, ADC, ADCF, ADD, DEC, DIV, DIVU, DIVX, EXTS, INC, MUL, MULU, NEG,
SBB, and SUB
DADC, DADD, DSBB, and DSUB
AND, NOT, OR, and XOR
ADJNZ, SBJNZ
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 49 of 109
M16C/65C Group
5.
5. Electrical Characteristics
Electrical Characteristics
5.1
Electrical Characteristics (Common to 3 V and 5 V)
5.1.1
Table 5.1
Absolute Maximum Rating
Absolute Maximum Ratings
Rated Value
Unit
VCC1
Symbol
Supply voltage
Parameter
VCC1 = AVCC
Condition
−0.3 to 6.5
V
VCC2
Supply voltage
VCC1 = AVCC
−0.3 to VCC1 + 0.1 (1)
V
AVCC
Analog supply voltage
VCC1 = AVCC
−0.3 to 6.5
V
VREF
Analog reference voltage
VCC1 = AVCC
−0.3 to VCC1 + 0.1 (1)
V
VI
Input voltage
RESET, CNVSS, BYTE,
P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
XIN
−0.3 to VCC1 + 0.3 (1)
V
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
−0.3 to VCC2 + 0.3 (1)
V
−0.3 to 6.5
V
P7_0, P7_1, P8_5
VO
−0.3 to VCC1 + 0.3
Output voltage P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
XOUT
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
P7_0, P7_1, P8_5
Pd
Power consumption
Topr
Operating
temperature
−40°C < Topr ≤ 85°C
When the MCU is operating
Flash program erase
Program area
Data area
Tstg
Storage temperature
(1)
V
−0.3 to VCC2 + 0.3 (1)
V
−0.3 to 6.5
V
300
mW
−20 to 85/−40 to 85
°C
0 to 60
−20 to 85/−40 to 85
−65 to 150
°C
Note:
1. Maximum value is 6.5 V.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 50 of 109
M16C/65C Group
5.1.2
5. Electrical Characteristics
Recommended Operating Conditions
Table 5.2
Recommended Operating Conditions (1/3)
VCC1 = VCC2 = 2.7 to 5.5 V at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified.
Symbol
Parameter
VCC1,
VCC2
Supply voltage (VCC1 ≥ VCC2)
AVCC
Analog supply voltage
VSS
CEC function is not used
CEC function is used
Min.
2.7
2.7
Standard
Typ.
5.0
Max.
5.5
3.63
Unit
V
V
VCC1
V
Supply voltage
0
V
AVSS
Analog supply voltage
0
V
VIH
High input P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
voltage
P12_0 to P12_7, P13_0 to P13_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(in single-chip mode)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(data input in memory expansion and microprocessor
modes)
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7,
P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0,
P14_1
XIN, RESET, CNVSS, BYTE
P7_0, P7_1, P8_5
CEC
VIL
Low input
voltage
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(in single-chip mode)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(data input in memory expansion and microprocessor mode)
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7,P11_0 to P11_7, P14_0, P14_1
XIN, RESET, CNVSS, BYTE
CEC
IOH(sum) High peak Sum of IOH(peak) at P0_0 to P0_7, P1_0 to P1_7,
output
P2_0 to P2_7
current
Sum of IOH(peak) at P3_0 to P3_7, P4_0 to P4_7,
P5_0 to P5_7, P12_0 to P12_7, and P13_0 to P13_7
Sum of IOH(peak) at P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4
Sum of IOH(peak) at P8_6, P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P14_0 to P14_1
IOH(peak) High peak P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
output
P4_0 to P4_7, P5_0 to P5_7,
current
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7,
P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,
P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
IOH(avg) High
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
average
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
output
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7,
current (1) P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,
P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
0.8VCC2
VCC2
V
0.8VCC2
VCC2
V
0.5VCC2
VCC2
V
0.8VCC1
VCC1
V
0.8VCC1
6.5
V
0.7VCC1
V
0
0.2VCC2
V
0
0.2VCC2
V
0
0.16VCC2
V
0
0.2VCC1
V
0.26VCC1
V
-40.0
mA
-40.0
mA
-40.0
mA
-40.0
mA
−10.0
mA
−5.0
mA
Note:
1. The average output current is the mean value within 100 ms.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 51 of 109
M16C/65C Group
Table 5.3
5. Electrical Characteristics
Recommended Operating Conditions (2/3)
VCC1 = VCC2 = 2.7 to 5.5 V at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified.
Symbol
IOL(sum)
Parameter
Standard
Min.
Typ.
Low peak Sum of IOL(peak) at P0_0 to P0_7, P1_0 to P1_7,
output
P2_0 to P2_7, P8_6, P8_7, P9_0 to P9_7,
current
P10_0 to P10_7, P11_0 to P11_7, P14_0 to P14_1
Max.
Unit
80.0
mA
Sum of IOL(peak) at P3_0 to P3_7, P4_0 to P4_7,
P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_5, P12_0 to P12_7, P13_0 to P13_7
80.0
mA
IOL(peak) Low peak P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
output
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
current
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,
P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
10.0
mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,
P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
5.0
mA
20
MHz
50
kHz
10
32
MHz
2
32
MHz
VCC1 = 5.0 V
2
ms
VCC1 = 3.0 V
3
ms
IOL(avg)
Low
average
output
current (1)
f(XIN)
Main clock input
oscillation frequency
f(XCIN)
Sub clock oscillation frequency
f(PLL)
PLL clock oscillation
frequency
f(BCLK)
CPU operation clock
tSU(PLL)
PLL frequency
synthesizer
stabilization wait time
VCC1 = 2.7 V to 5.5 V
VCC1 = 2.7 V to 5.5 V
2
32.768
Note:
1. The average output current is the mean value within 100 ms.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 52 of 109
M16C/65C Group
Table 5.4
5. Electrical Characteristics
Recommended Operating Conditions (3/3) (1)
VCC1 = 2.7 to 5.5 V, VSS = 0 V, and Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified.
The ripple voltage must not exceed Vr(VCC1) and/or dVr(VCC1)/dt.
Symbol
Vr(VCC1)
Standard
Parameter
Allowable ripple voltage
dVr(VCC1)/dt Ripple voltage falling gradient
Min.
Typ.
Max.
Unit
VCC1 = 5.0 V
0.5
Vp-p
VCC1 = 3.0 V
0.3
Vp-p
VCC1 = 5.0 V
0.3
V/ms
VCC1 = 3.0 V
0.3
V/ms
Note:
1. The device is operationally guaranteed under these operating conditions.
VCC1
Figure 5.1
Vr( VCC1)
Ripple Waveform
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 53 of 109
M16C/65C Group
5.1.3
Table 5.5
5. Electrical Characteristics
A/D Conversion Characteristics
A/D Conversion Characteristics (1/2) (1)
VCC1 = AVCC = 3.0 to 5.5 V ≥ VCC2 ≥ VREF, VSS = AVSS = 0 V at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise
specified.
Symbol
Parameter
Measuring Condition
-
Resolution
AVCC = VCC1 ≥ VCC2 ≥ VREF
INL
Integral non-linearity error 10 bits
VCC1 = AN0 to AN7 input,
AN0_0 to AN0_7 input,
5.0 V
AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
(Note 2)
VCC1 = AN0 to AN7 input,
AN0_0 to AN0_7 input,
3.3 V
AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
(Note 2)
VCC1 = AN0 to AN7 input,
AN0_0 to AN0_7 input,
3.0 V
AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
(Note 2)
VCC1 = AN0 to AN7 input,
AN0_0 to AN0_7 input,
5.0 V
AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
(Note 2)
VCC1 = AN0 to AN7 input,
AN0_0 to AN0_7 input,
3.3 V
AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
(Note 2)
VCC1 = AN0 to AN7 input,
AN0_0 to AN0_7 input,
3.0 V
AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
(Note 2)
-
Absolute accuracy
10 bits
Min.
Standard
Typ.
Max.
10
Unit
Bits
±3
LSB
±3
LSB
±3
LSB
±3
LSB
±3
LSB
±3
LSB
Notes:
1. Use when AVCC = VCC1.
2. Flash memory rewrite disabled. Except for the analog input pin, set the pins to be measured as input ports and
connect them to VSS. See Figure 5.2 “A/D Accuracy Measure Circuit”.
AN
Analog input
P0 to P14
Figure 5.2
AN: One of the analog input pin
P0 to P14: I/O pins other than AN
A/D Accuracy Measure Circuit
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 54 of 109
M16C/65C Group
Table 5.6
5. Electrical Characteristics
A/D Conversion Characteristics (2/2) (1)
VCC1 = AVCC = 3.0 to 5.5 V ≥ VCC2 ≥ VREF, VSS = AVSS = 0 V at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise
specified.
Symbol
φAD
Parameter
A/D operating clock
frequency
Measuring Condition
Standard
Min.
Typ.
Max.
Unit
AN0 to AN7 input, 4.0 V ≤ VCC1 ≤ 5.5 V
ANEX0 to ANEX1 3.2 V ≤ V
CC1 ≤ 4.0 V
input
3.0 V ≤ VCC1 ≤ 3.2 V
2
25
MHz
2
16
MHz
2
10
MHz
AN0_0 to AN0_7 4.0 V ≤ VCC2 ≤ 5.5 V
input, AN2_0 to
3.2 V ≤ VCC2 ≤ 4.0 V
AN2_7 input
≤ 3.2 V
3.0 V ≤ V
2
25
MHz
2
16
MHz
2
10
MHz
CC2
kΩ
-
Tolerance level impedance
DNL
Differential non-linearity error
(4)
3
±1
LSB
-
Offset error
(4)
±3
LSB
-
Gain error
(4)
±3
LSB
tCONV
10-bit conversion time
VCC1 = 5 V, φAD = 25 MHz
tSAMP
Sampling time
0.60
VREF
Reference voltage
3.0
VCC1
V
VIA
Analog input voltage (2), (3)
0
VREF
V
μs
1.60
μs
Notes:
1. Use when AVCC = VCC1.
2. When VCC1 ≥ VCC2, set as below:
Analog input voltage (AN0 to AN7, ANEX0, and ANEX1) ≤ VCC1
Analog input voltage (AN0_0 to AN0_7 and AN2_0 to AN2_7) ≤ VCC2.
3. When analog input voltage is over reference voltage, the result of A/D conversion is 3FFh.
4. Flash memory rewrite disabled. Except for the analog input pin, set the pins to be measured as input ports and
connect them to VSS. See Figure 5.2 “A/D Accuracy Measure Circuit”.
5.1.4
Table 5.7
D/A Conversion Characteristics
D/A Conversion Characteristics
VCC1 = AVCC = VREF = 3.0 to 5.5 V, VSS = AVSS = 0 V at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified.
Symbol
-
Parameter
Measuring Condition
Standard
Min.
Typ.
Resolution
-
Absolute Accuracy
tSU
Setup Time
RO
Output Resistance
IVREF
Reference Power Supply Input Current
5
See Notes 1 and 2
6
Max.
Unit
8
Bits
2.5
LSB
3
μs
8.2
kΩ
1.5
mA
Notes:
1. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to 00h.
2. The current consumption of the A/D converter is not included. Also, the IVREF of the D/A converter will flow even
if the ADSTBY bit in the ADCON1 register is 0 (A/D operation stopped (standby)).
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 55 of 109
M16C/65C Group
5.1.5
5. Electrical Characteristics
Flash Memory Electrical Characteristics
Table 5.8
CPU Clock When Operating Flash Memory (f(BCLK))
VCC1 = 2.7 to 5.5 V, Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified.
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
-
CPU rewrite mode
10 (1)
MHz
f(SLOW_R)
Slow read mode
5 (3)
MHz
-
Low current consumption read mode
-
Data flash read
35
kHz
2.7 V ≤ VCC1 ≤ 3.0 V
fC(32.768)
16 (2)
MHz
3.0 V < VCC1 ≤ 5.5 V
20 (2)
MHz
Notes:
1. Set the PM17 bit in the PM1 register to 1 (one wait).
2. When the frequency is over this value, set the FMR17 bit in the FMR1 register to 0 (one wait) or the PM17 bit in
the PM1 register to 1 (one wait)
3. Set the PM17 bit in the PM1 register to 1 (one wait). When using 125 kHz on-chip oscillator clock or sub clock as
the CPU clock source, a wait is not necessary.
Table 5.9
Flash Memory (Program ROM 1, 2) Electrical Characteristics
VCC1 = 2.7 to 5.5 V at Topr = 0°C to 60°C (option: -40°C to 85°C), unless otherwise specified.
Symbol
Parameter
Conditions
-
Program and erase cycles (1), (3), (4) VCC1 = 3.3 V, Topr = 25°C
VCC1 = 3.3 V, Topr = 25°C
2 word program time
-
Lock bit program time
Block erase time
-
-
Min.
Standard
Typ.
Max.
1,000 (2)
Unit
times
150
4000
μs
VCC1 = 3.3 V, Topr = 25°C
70
3000
μs
VCC1 = 3.3 V, Topr = 25°C
0.2
3.0
s
3 5 + --------------f ( BCLK )
ms
td(SR-SUS) Time delay from suspend request
until suspend
Interval from erase start/restart
until following suspend request
Suspend interval necessary for
auto-erasure to complete (7)
Time from suspend until erase
restart
Program, erase voltage
Topr= -20°C to 85°C/-40°C to 85°C
-
Read voltage
tPS
Program, erase temperature
Flash memory circuit stabilization wait time
-
Data hold time (6)
Ambient temperature = 55°C
0
μs
20
ms
2.7
1 30 + --------------f ( BCLK )
5.5
2.7
5.5
V
0
60
°C
50
20
μs
V
μs
year
Notes:
1. Definition of program and erase cycles:
The program and erase cycles refer to the number of per-block erasures. If the program and erase cycles are n
(n = 1,000), each block can be erased n times. For example, if a block is erased after writing 2 word data 16,384
times, each to a different address, this counts as one program and erase cycles. Data cannot be written to the
same address more than once without erasing the block (rewrite prohibited).
2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing
to sequential addresses in turn so that as much of the block as possible is used up before performing an erase
operation. It is advisable to retain data on the erasure cycles of each block and limit the number of erase
operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the
block erase command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office.
6. The data hold time includes time that the power supply is off or the clock is not supplied.
7. After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request, the
erase sequence cannot be completed.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 56 of 109
M16C/65C Group
Table 5.10
5. Electrical Characteristics
Flash Memory (Data Flash) Electrical Characteristics
VCC1 = 2.7 to 5.5 V at Topr = -20 to 85°C/-40 to 85°C, unless otherwise specified.
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
-
Program and erase cycles (1), (3), (4) VCC1 = 3.3 V, Topr = 25°C
-
2 word program time
VCC1 = 3.3 V, Topr = 25°C
300
4000
μs
-
Lock bit program time
VCC1 = 3.3 V, Topr = 25°C
140
3000
μs
-
Block erase time
VCC1 = 3.3 V, Topr = 25°C
0.2
3.0
s
td(SR-SUS)
Time delay from suspend request
until suspend
3 5 + --------------f ( BCLK )
ms
-
Interval from erase start/restart until
following suspend request
0
μs
-
Suspend interval necessary for
auto-erasure to complete (7)
20
ms
-
Time from suspend until erase
restart
-
Program, erase voltage
-
Read voltage
-
Program, erase temperature
tPS
Flash memory circuit stabilization wait time
-
Data hold time (6)
Ambient temperature = 55°C
10,000 (2)
times
1 30 + --------------f ( BCLK )
μs
2.7
5.5
V
2.7
5.5
V
−20/−40
85
°C
50
μs
20
year
Notes:
1. Definition of program and erase cycles
The program and erase cycles refer to the number of per-block erasures.
If the program and erase cycles are n (n = 10,000), each block can be erased n times.
For example, if a 4 KB block is erased after writing 2 word data 1,024 times, each to a different address, this
counts as one program and erase cycles. Data cannot be written to the same address more than once without
erasing the block (rewrite prohibited).
2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing
to sequential addresses in turn so that as much of the block as possible is used up before performing an erase
operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be
minimized by programming up to 256 groups before erasing them all in one operation. In addition, averaging the
erasure cycles between blocks A and B can further reduce the actual erasure cycles. It is also advisable to retain
data on the erasure cycles of each block and limit the number of erase operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the
block erase command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office.
6. The data hold time includes time that the power supply is off or the clock is not supplied.
7. After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request, the
erase sequence cannot be completed.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 57 of 109
M16C/65C Group
5.1.6
Table 5.11
5. Electrical Characteristics
Voltage Detector and Power Supply Circuit Electrical Characteristics
Voltage Detector 0 Electrical Characteristics
The measurement condition is VCC1 = 2.7 to 5.5 V, Topr = -20°C to 85°C/-40°C to 85°C, unless otherwise specified.
Symbol
Vdet0
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
Voltage detection level Vdet0_0 (1)
When VCC1 is falling.
1.80
1.90
2.10
V
Voltage detection level Vdet0_2 (1)
When VCC1 is falling.
2.70
2.85
3.00
V
200
μs
-
Voltage detector 0 response time
-
Voltage detector self power consumption
td(E-A)
Waiting time until voltage detector operation
starts (2)
(3)
When VCC1 falls from 5 V
to (Vdet0_0 - 0.1) V
VC25 = 1, VCC1 = 5.0 V
μA
1.5
100
μs
Notes:
1. Select the voltage detection level with the VDSEL1 bit in the OFS1 address.
2. Necessary time until the voltage detector operates when setting to 1 again after setting the VC25 bit in the VCR2
register to 0.
3. Time from when passing the Vdet0 until when a voltage monitor 0 reset is generated.
Table 5.12
Voltage Detector 1 Electrical Characteristics
The measurement condition is VCC1 = 2.7 to 5.5 V, Topr = -20°C to 85°C/-40°C to 85°C, unless otherwise specified.
Symbol
Vdet1
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
Voltage detection level Vdet1_6 (1)
When VCC1 is falling.
2.80
3.10
3.40
V
Voltage detection level Vdet1_B
(1)
When VCC1 is falling.
3.55
3.85
4.15
V
Voltage detection level Vdet1_F
(1)
When VCC1 is falling.
4.15
4.45
4.75
V
-
Hysteresis width when VCC1 of voltage detector
1 is rising
-
Voltage detector 1 response time (3)
When VCC1 falls from 5 V
to (Vdet1_0 - 0.1) V
-
Voltage detector self power consumption
VC26 = 1, VCC1 = 5.0 V
td(E-A)
Waiting time until voltage detector operation
starts (2)
0.15
V
200
μs
μA
1.7
100
μs
Notes:
1. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register.
2. Necessary time until the voltage detector operates when setting to 1 again after setting the VC26 bit in the VCR2
register to 0.
3. Time from when passing the Vdet1 until when a voltage monitor 1 reset is generated.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 58 of 109
M16C/65C Group
Table 5.13
5. Electrical Characteristics
Voltage Detector 2 Electrical Characteristics
The measurement condition is VCC1 = 2.7 to 5.5 V, Topr = -20°C to 85°C/-40°C to 85°C, unless otherwise specified.
Symbol
Parameter
When VCC1 is falling
Vdet2
Voltage detection level Vdet2_0
-
Hysteresis width at the rising of VCC1 in voltage
detector 2
-
Voltage detector 2 response time (2)
-
Voltage detector self power consumption
td(E-A)
Standard
Condition
Min.
Typ.
Max.
3.70
4.00
4.30
0.15
Waiting time until voltage detector operation starts
V
V
When VCC1 falls from 5
V to (Vdet2_0 - 0.1) V
200
VC27 = 1, VCC1 = 5.0 V
Unit
μs
μA
1.7
(1)
100
μs
Notes:
1. Necessary time until the voltage detector operates after setting to 1 again after setting the VC27 bit in the VCR2
register to 0.
2. Time from when passing the Vdet2 until when a voltage monitor 2 reset is generated.
Table 5.14
Power-On Reset Circuit
The measurement condition is VCC1 = 2.0 to 5.5 V, Topr = -20°C to 85°C/ -40°C to 85°C, unless otherwise specified.
Symbol
Parameter
Standard
Condition
Min.
Vpor1
Voltage at which power-on reset enabled (1)
trth
External power VCC1 rise gradient
2.0
tw(por)
Time necessary to enable power-on reset
300
Typ.
Max.
0.5
Unit
V
50000 mV/ms
ms
Note:
1. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS1 address
to 0. Also, set the VDSEL1 bit to 0 (Vdet0_2).
Vdet0 (1)
VCC1
Vdet0 (1)
t rth
t rth
Vpor1
Voltage detection 0
circuit response time
tw(por)
Internal
reset signal
1
× 32
fOCO-S
1
× 32
fOCO-S
Note:
1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit.
Figure 5.3
Power-On Reset Circuit Electrical Characteristics
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 59 of 109
M16C/65C Group
5. Electrical Characteristics
Table 5.15
Power Supply Circuit Timing Characteristics
The measurement condition is VCC1 = 2.7 to 5.5 V and Topr = 25°C, unless otherwise specified.
Symbol
Parameter
Standard
Condition
td(P-R)
Internal power supply stability time when power is on (1)
td(R-S)
td(W-S)
Min.
Typ.
Max.
Unit
5
ms
STOP release time
150
μs
Low power mode wait mode release time
150
μs
Note:
1. Waiting time until the internal power supply generator stabilizes when power is on.
td(P-R)
Internal power supply stability
time when power is on
Recommended
operation voltage
VCC1
td(P-R)
CPU clock
td(R-S)
STOP release time
td(W-S)
Low power mode
wait mode release time
Interrupt for
(a) Stop mode release
or
(b) Wait mode release
CPU clock
(a)
(b)
td(E-A)
Voltage detector
operation start time
td(R-S)
td(W-S)
VC25, VC26, VC27
Voltage detector
Stop
Operate
td(E-A)
Figure 5.4
Power Supply Circuit Timing Diagram
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 60 of 109
M16C/65C Group
5.1.7
Table 5.16
5. Electrical Characteristics
Oscillator Electrical Characteristics
40 MHz On-Chip Oscillator Electrical Characteristics (1/2)
VCC1 = 2.7 to 5.5 V, Topr = -20°C to 85°C/-40°C to 85°C, unless otherwise specified.
Symbol
fOCO40M
Parameter
Condition
40 MHz on-chip oscillator frequency Average frequency in a 10 ms period
Standard
Typ.
Max.
38
40
42
MHz
2
ms
tsu(fOCO40M) Wait time until 40 MHz on-chip
oscillator stabilizes
Table 5.17
Unit
Min.
125 kHz On-Chip Oscillator Electrical Characteristics
VCC1 = 2.7 to 5.5 V, Topr = −20°C to 85°C/−40°C to 85°C, unless otherwise specified.
Symbol
Parameter
fOCO-S
125 kHz on-chip oscillator frequency
tsu(fOCO-S)
Wait time until 125 kHz on-chip
oscillator stabilizes
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Condition
Standard
Unit
Min.
Typ.
Max.
Average frequency in a 10 ms period 100
125
150
kHz
20
μs
Page 61 of 109
M16C/65C Group
5.2
5. Electrical Characteristics
Electrical Characteristics (VCC1 = VCC2 = 5 V)
5.2.1
Electrical Characteristics
VCC1 = VCC2 = 5 V
Table 5.18
Electrical Characteristics (1)
(1)
VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V at Topr = −20°C to 85°C/−40°C to 85°C, f(BCLK) = 32 MHz unless otherwise
specified.
Symbol
VOH
Measuring
Condition
Parameter
VCC1 − 2.0
VCC1
IOH = −5 mA
VCC2 − 2.0
VCC2
High output P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, IOH = −200 μA
voltage
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
VCC1 − 0.3
VCC1
IOH = −200 μA
VCC2 − 0.3
VCC2
HIGH POWER
IOH = −1 mA
VCC1 − 2.0
VCC1
LOW POWER
IOH = −0.5 mA
VCC1 − 2.0
VCC1
HIGH POWER
With no load
applied
2.6
LOW POWER
With no load
applied
2.2
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
VOH
High output voltage
XOUT
High output voltage
VOL
VOL
VOL
Typ. Max.
High output P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, IOH = −5 mA
voltage
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
VOH
Standard
Min.
XCOUT
IOL = 5 mA
2.0
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOL = 5 mA
2.0
Low output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
voltage
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
IOL = 200 μA
0.45
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOL = 200 μA
0.45
2.0
XOUT
HIGH POWER
IOL = 1 mA
LOW POWER
IOL = 0.5 mA
Low output voltage
XCOUT
HIGH POWER
With no load
applied
0
LOW POWER
With no load
applied
0
V
V
V
V
Low output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
voltage
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
Low output voltage
Unit
V
V
V
2.0
V
Note:
1. When VCC1 ≠ VCC2, refer to 5 V or 3 V standard depending on the voltage.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 62 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Table 5.19
Electrical Characteristics (2)
(1)
VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V at Topr = −20°C to 85°C/−40°C to 85°C, f(BCLK) = 32 MHz unless otherwise specified.
Symbol
Parameter
Measuring
Condition
Standard
Min.
Typ. Max.
Unit
VT+ - VT- Hysteresis
HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN,
INT0 to INT7, NMI, ADTRG, CTS0 to CTS2,
CTS5 to CTS7, SCL0 to SCL2, SCL5 to SCL7,
SDA0 to SDA2, SDA5 to SDA7, CLK0 to CLK7,
TA0OUT to TA4OUT,
KI0 to KI3, RXD0 to RXD2, RXD5 to RXD7,
SIN3, SIN4, SD, PMC0, PMC1, SCLMM,
SDAMM, CEC, ZP, IDU, IDV, IDW
0.5
2.0
V
VT+ - VT- Hysteresis
RESET
0.5
2.5
V
IIH
High input
current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7,
P13_0 to P13_7, P14_0, P14_1
XIN, RESET, CNVSS, BYTE
VI = 5 V
5.0
μA
IIL
Low input
current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7,
P13_0 to P13_7, P14_0, P14_1
XIN, RESET, CNVSS, BYTE
VI = 0 V
−5.0
μA
RPULLUP Pull-up
resistance
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7,
P13_0 to P13_7, P14_0, P14_1
VI = 0 V
100
kΩ
RfXIN
Feedback resistance XIN
VRAM
RAM retention voltage
30
50
1.5
In stop mode
1.8
MΩ
V
Note:
1. When VCC1 ≠ VCC2, refer to 5 V or 3 V standard depending on the voltage.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 63 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Table 5.20
Electrical Characteristics (3)
R5F36506CNFA, R5F36506CNFB, R5F3650ECNFA, R5F3650ECNFB, R5F36506CDFA, R5F36506CDFB,
R5F3650ECDFA, R5F3650ECDFB
VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V at Topr = −20°C to 85°C/−40°C to 85°C, f(BCLK) = 32 MHz unless otherwise specified.
Symbol
RfXCIN
ICC
Note:
1.
Parameter
Measuring Condition
Feedback resistance
XCIN
Power supply current High-speed mode f(BCLK) = 32 MHz
XIN = 4 MHz (square wave), PLL multiplied by 8
In single-chip, mode,
125 kHz on-chip oscillator stopped
the output pin are
f(BCLK) =32 MHz, A/D conversion
open and other pins
XIN = 4 MHz (square wave), PLL multiplied by 8
are VSS
125 kHz on-chip oscillator stopped
f(BCLK) = 20 MHz
XIN = 20 MHz (square wave)
125 kHz on-chip oscillator stopped
40 MHz on-chip
Main clock stopped
oscillator mode
40 MHz on-chip oscillator on,
divide-by-4 (f(BCLK) = 10 MHz)
125 kHz on-chip oscillator stopped
125 kHz on-chip
Main clock stopped
oscillator mode
40 MHz on-chip oscillator stopped,
125 kHz on-chip oscillator on, no division
FMR22 = 1 (slow read mode)
Low-power mode f(BCLK) = 32 kHz
In low-power mode
FMR22 = FMR23 = 1
On flash memory (1)
f(BCLK) = 32 kHz
In low-power mode
On RAM (1)
Wait mode
Main clock stopped
40 MHz on-chip oscillator stopped
125 kHz on-chip oscillator on
Peripheral clock operating
Topr = 25°C
f(BCLK) = 32 kHz (oscillation capacity High)
40 MHz on-chip oscillator stopped
125 kHz on-chip oscillator stopped
Peripheral clock operating
Topr = 25°C
f(BCLK) = 32 kHz (oscillation capacity Low)
40 MHz on-chip oscillator stopped
125 kHz on-chip oscillator stopped
Peripheral clock operating
Topr = 25°C
XIN = 6 MHz
40 MHz on-chip oscillator stopped
125 kHz on-chip oscillator stopped
Peripheral clock f1 provision disabled except
timers (PCKSTP1A = 1)
Main clock as a timer clock source
(PCKSTP11 = 0, PCKSTP17 = 1)
A given timer operating
Stop mode
Main clock stopped
40 MHz on-chip oscillator stopped
125 kHz on-chip oscillator stopped
Peripheral clock stopped
Topr = 25°C
During flash
f(BCLK) = 10 MHz, PM17 = 1 (one wait)
memory program VCC1 = 5.0 V
During flash
f(BCLK) = 10 MHz, PM17 = 1 (one wait)
memory erase
VCC1 = 5.0 V
Min.
Standard
Typ.
Max.
Unit
8
MΩ
24.0
mA
24.7
mA
16.0
mA
17.0
mA
500.0
μA
160.0
μA
45.0
μA
20.0
μA
11.0
μA
6.0
μA
1.2
mA
1.7
μA
20.0
mA
30.0
mA
This indicates the memory in which the program to be executed exists.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 64 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Table 5.21
Electrical Characteristics (4)
R5F3651ECNFC, R5F3651KCNFC, R5F3650KCNFA, R5F3650KCNFB, R5F3651MCNFC, R5F3650MCNFA, R5F3650MCNFB,
R5F3651NCNFC, R5F3650NCNFA, R5F3650NCNFB, R5F3651ECDFC, R5F3651KCDFC, R5F3650KCDFA, R5F3650KCDFB,
R5F3651MCDFC, R5F3650MCDFA, R5F3650MCDFB, R5F3651NCDFC, R5F3650NCDFA, R5F3650NCDFB
VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V at Topr = −20°C to 85°C/−40°C to 85°C, f(BCLK) = 32 MHz unless otherwise specified.
Symbol
RfXCIN
ICC
Parameter
Measuring Condition
Feedback resistance
XCIN
Power supply current High-speed mode
f(BCLK) = 32 MHz
XIN = 4 MHz (square wave), PLL multiplied by 8
In single-chip, mode,
125 kHz on-chip oscillator stopped
the output pin are
f(BCLK) = 32 MHz, A/D conversion
open and other pins
XIN = 4 MHz (square wave), PLL multiplied by 8
are VSS
125 kHz on-chip oscillator stopped
f(BCLK) = 20 MHz
XIN = 20 MHz (square wave)
125 kHz on-chip oscillator stopped
40 MHz on-chip
Main clock stopped
oscillator mode
40 MHz on-chip oscillator on,
divide-by-4 (f(BCLK) = 10 MHz)
125 kHz on-chip oscillator stopped
125 kHz on-chip
Main clock stopped
oscillator mode
40 MHz on-chip oscillator stopped
125 kHz on-chip oscillator on, no division
FMR22 = 1 (slow read mode)
Low-power mode
f(BCLK) = 32 kHz
In low-power mode
FMR22 = FMR23 = 1
on flash memory (1)
f(BCLK) = 32 kHz
In low-power mode
on RAM (1)
Wait mode
Main clock stopped
40 MHz on-chip oscillator stopped
125 kHz on-chip oscillator on
Peripheral clock operating
Topr = 25°C
f(BCLK) = 32 kHz (oscillation capacity High)
40 MHz on-chip oscillator stopped
125 kHz on-chip oscillator stopped
Peripheral clock operating
Topr = 25°C
f(BCLK) = 32 kHz (oscillation capacity low)
40 MHz on-chip oscillator stopped
125 kHz on-chip oscillator stopped
Peripheral clock operating
Topr = 25°C
XIN = 6 MHz
40 MHz on-chip oscillator stopped
125 kHz on-chip oscillator stopped
Peripheral clock f1 provision disabled except
timers (PCKSTP1A = 1)
Main clock as a timer clock source
(PCKSTP11 = 0, PCKSTP17 = 1)
A given timer operating
Stop mode
Main clock stopped
40 MHz on-chip oscillator stopped
125 kHz on-chip oscillator stopped
Peripheral clock stopped
Topr = 25°C
During flash memory f(BCLK) = 10 MHz, PM17 = 1 (one wait)
program
VCC1 = 5.0 V
During flash memory f(BCLK) = 10 MHz, PM17 = 1 (one wait)
erase
VCC1 = 5.0 V
Min.
Standard
Typ.
Max.
Unit
8
MΩ
26.0
mA
27.0
mA
17.0
mA
18.0
mA
550.0
μA
170.0
μA
45.0
μA
20.5
μA
11.0
μA
6.0
μA
1.2
mA
1.7
μA
20.0
mA
30.0
mA
Note:
1. This indicates the memory in which the program to be executed exists.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 65 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
5.2.2
Timing Requirements (Peripheral Functions and Others)
(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.2.2.1
Reset Input (RESET Input)
Table 5.22
Reset Input (RESET Input)
Symbol
Standard
Parameter
Min.
RESET input low pulse width
tw(RSTL)
Max.
Unit
μs
10
RESET input
t w(RTSL)
Figure 5.5
5.2.2.2
Table 5.23
Reset Input (RESET Input)
External Clock Input
External Clock Input (XIN Input) (1)
Symbol
Standard
Parameter
tc
External clock input cycle time
Min.
Max.
50
Unit
ns
tw(H)
External clock input high pulse width
20
ns
tw(L)
External clock input low pulse width
20
ns
tr
External clock rise time
9
ns
tf
External clock fall time
9
ns
Note:
1. The condition is VCC1 = VCC2 = 3.0 to 5.0 V.
XIN input
tr
t w(H)
tf
t w(L)
tc
Figure 5.6
External Clock Input (XIN Input)
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 66 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 =
Timing Requirements
(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.2.2.3
Table 5.24
Timer A Input
Timer A Input (Counter Input in Event Counter Mode)
Symbol
Standard
Parameter
Min.
Unit
Max.
tc(TA)
TAiIN input cycle time
100
ns
tw(TAH)
TAiIN input high pulse width
40
ns
tw(TAL)
TAiIN input low pulse width
40
ns
Table 5.25
Timer A Input (Gating Input in Timer Mode)
Symbol
Standard
Parameter
Min.
Unit
Max.
tc(TA)
TAiIN input cycle time
400
ns
tw(TAH)
TAiIN input high pulse width
200
ns
tw(TAL)
TAiIN input low pulse width
200
ns
Table 5.26
Timer A Input (External Trigger Input in One-Shot Timer Mode)
Symbol
Standard
Parameter
Min.
Unit
Max.
tc(TA)
TAiIN input cycle time
200
ns
tw(TAH)
TAiIN input high pulse width
100
ns
tw(TAL)
TAiIN input low pulse width
100
ns
Table 5.27
5V
Timer A Input (External Trigger Input in Pulse Width Modulation Mode and
Programmable Output Mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tw(TAH)
TAiIN input high pulse width
100
ns
tw(TAL)
TAiIN input low pulse width
100
ns
tc(TA)
t w(TAH)
TAiIN input
t w(TAL)
tc(UP)
t w(UPH)
TAiOUT input
t w(UPL)
Figure 5.7
Timer A Input
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 67 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 =
Timing Requirements
(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
Table 5.28
5V
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
800
ns
tsu(TAIN-TAOUT)
TAiOUT input setup time
200
ns
tsu(TAOUT-TAIN)
TAiIN input setup time
200
ns
Two-phase pulse input in event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
Figure 5.8
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 68 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 =
Timing Requirements
(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.2.2.4
Table 5.29
5V
Timer B Input
Timer B Input (Counter Input in Event Counter Mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time (counted on one edge)
100
ns
tw(TBH)
TBiIN input high pulse width (counted on one edge)
40
ns
tw(TBL)
TBiIN input low pulse width (counted on one edge)
40
ns
tc(TB)
TBiIN input cycle time (counted on both edges)
200
ns
tw(TBH)
TBiIN input high pulse width (counted on both edges)
80
ns
tw(TBL)
TBiIN input low pulse width (counted on both edges)
80
ns
Table 5.30
Timer B Input (Pulse Period Measurement Mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
TBiIN input high pulse width
200
ns
tw(TBL)
TBiIN input low pulse width
200
ns
Table 5.31
Timer B Input (Pulse Width Measurement Mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
TBiIN input high pulse width
200
ns
tw(TBL)
TBiIN input low pulse width
200
ns
tc(TB)
t w(TBH)
TBiIN input
t w(TBL)
Figure 5.9
Timer B Input
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 69 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 =
Timing Requirements
(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.2.2.5
Table 5.32
5V
Serial Interface
Serial Interface
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
200
ns
tw(CKH)
CLKi input high pulse width
100
ns
tw(CKL)
CLKi input low pulse width
100
td(C-Q)
TXDi output delay time
th(C-Q)
TXDi hold time
0
ns
tsu(D-C)
RXDi input setup time
70
ns
th(C-D)
RXDi input hold time
90
ns
ns
80
ns
tc(CK)
t w(CKH)
CLKi
t w(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
Figure 5.10
5.2.2.6
Table 5.33
Serial Interface
External Interrupt INTi Input
External Interrupt INTi Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tw(INH)
INTi input high pulse width
250
ns
tw(INL)
INTi input low pulse width
250
ns
t w(INL)
INTi input
t w(INH)
Figure 5.11
External Interrupt INTi Input
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 70 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 =
Timing Requirements
(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5V
Multi-master I2C-bus
5.2.2.7
Multi-master I2C-bus
Table 5.34
Symbol
Standard Clock Mode
Parameter
Min.
Fast-mode
Max.
Min.
Unit
Max.
tBUF
Bus free time
4.7
1.3
μs
tHD;STA
Hold time in start condition
4.0
0.6
μs
tLOW
Hold time in SCL clock 0 status
4.7
1.3
μs
tR
SCL, SDA signals’ rising time
tHD;DAT
Data hold time
tHIGH
Hold time in SCL clock 1 status
fF
SCL, SDA signals’ falling time
tsu;DAT
Data setup time
250
100
ns
tsu;STA
Setup time in restart condition
4.7
0.6
μs
tsu;STO
Stop condition setup time
4.0
0.6
μs
1000
20 + 0.1 Cb
300
ns
0
0
0.9
μs
4.0
0.6
300
20 + 0.1 Cb
μs
300
ns
SDA
t HD;STA
t BUF
t su;STO
t LOW
tR
SCL
p
t HD;STA
Figure 5.12
tF
Sr
s
t HD;DAT
t HIGH
t su;DAT
p
t su;STA
Multi-master I2C-bus
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 71 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 =
Timing Requirements
(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.2.3
5V
Timing Requirements (Memory Expansion Mode and Microprocessor
Mode)
Table 5.35
Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
Standard
Min.
Max.
Unit
tac1(RD-DB)
Data input access time (for setting with no wait)
(Note 1)
ns
tac2(RD-DB)
Data input access time (for setting with 1 to 3 waits)
(Note 2)
ns
tac3(RD-DB)
Data input access time (when accessing multiplex bus area)
(Note 3)
ns
tac4(RD-DB)
Data input access time (for setting with 2φ + 3φ or more)
(Note 4)
ns
tsu(DB-RD)
Data input setup time
50
ns
tsu(RDY-BCLK)
RDY input setup time
80
ns
th(RD-DB)
Data input hold time
0
ns
th(BCLK-RDY)
RDY input hold time
0
ns
Notes:
1. Calculated according to the BCLK frequency as follows:
9
0.5
× 10 - – 45 [ ns ]
--------------------f ( BCLK )
2.
Calculated according to the BCLK frequency as follows:
9
( n + 0.5 ) × 10 - – 45 [ ns ]
----------------------------------f ( BCLK )
3.
n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.
Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) × 10 - – 45 [ ns ]
----------------------------------f ( BCLK )
4.
n is 2 for 2 waits setting, and 3 for 3 waits setting.
Calculated according to the BCLK frequency as follows:
9
n × 10 - – 45 [ ns ]
----------------f ( BCLK )
n is 3 for 2φ + 3φ, 4 for 2φ + 4φ, 4 for 3φ + 4φ, and 5 for 4φ + 5φ.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 72 of 109
M16C/65C Group
5. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode
VCC1 = VCC2 = 5 V
(Effective in wait state setting)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY-BCLK)
th(BCLK-RDY)
Measuring conditions
y VCC1 = VCC2 = 5 V
y Input timing voltage: VIL = 1.0 V, VIH = 4.0 V
y Output timing voltage: VOL = 2.5 V, VOH = 2.5 V
Figure 5.13
Timing Diagram
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 73 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
5.2.4
Switching Characteristics (Memory Expansion Mode and Microprocessor
Mode)
(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.2.4.1
Table 5.36
In No Wait State Setting
Memory Expansion Mode and Microprocessor Mode (in No Wait State Setting)
Symbol
Parameter
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (in relation to BCLK)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
Chip select output delay time
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
td(BCLK-ALE)
ALE signal output delay time
Standard
Measuring
Condition
Min.
Max.
25
Unit
ns
0
ns
Address output hold time (in relation to RD)
0
ns
Address output hold time (in relation to WR)
(Note 2)
ns
th(BCLK-ALE)
ALE signal output hold time
td(BCLK-RD)
RD signal output delay time
25
0
ns
15
−4
See
Figure 5.14
ns
ns
ns
25
ns
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(BCLK-DB)
Data output delay time (in relation to BCLK)
td(DB-WR)
Data output delay time (in relation to WR)
(Note 1)
ns
th(WR-DB)
Data output hold time (in relation to WR) (3)
(Note 4)
ns
0
ns
25
0
ns
ns
40
ns
Notes:
1. Calculated according to the BCLK frequency as follows:
9
0.5
× 10 - – 40 [ ns ]
--------------------f(BCLK) is 12.5 MHz or less.
f ( BCLK )
2.
Calculated according to the BCLK frequency as follows:
9
0.5
× 10 - – 10 [ ns ]
--------------------f ( BCLK )
3.
4.
This standard value shows the timing when the output is off, and does not
show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up (pull-down)
resistance value.
Hold time of data bus is expressed in
t = −CR × ln(1−VOL/VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ, hold time of output
low level is
t = −30 pF × 1 kΩ × In(1 − 0.2VCC2/VCC2)
= 6.7 ns.
Calculated according to the BCLK frequency as follows:
R
DBi
C
9
0.5
× 10 - – 20 [ ns ]
--------------------f ( BCLK )
Hold time is equal to or less than 0 ns when the BCLK frequency exceeds 25 MHz.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 74 of 109
M16C/65C Group
5. Electrical Characteristics
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
Figure 5.14
30 pF
Ports P0 to P14 Measurement Circuit
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 75 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Memory Expansion Mode and Microprocessor Mode
(in no wait state setting)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
25ns(max.)
0ns(min.)
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
25ns(max.)
ADi
BHE
td(BCLK-ALE)
15ns(max.)
0ns(min.)
th(BCLK-ALE)
-4ns(min.)
th(RD-AD)
0ns(min.)
ALE
th(BCLK-RD)
td(BCLK-RD)
25ns(max.)
0ns(min.)
RD
tac1(RD-DB)
(0.5 × t cyc - 45)ns(max.)
Hi-Z
DBi
tsu(DB-RD)
50ns(min.)
th(RD-DB)
0ns(min.)
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
25ns(max.)
0ns(min.)
CSi
tcyc
ADi
BHE
td(BCLK-AD)
th(BCLK-AD)
25ns(max.)
0ns(min.)
td(BCLK-ALE)
15ns(max.)
th(BCLK-ALE)
-4ns(min.)
th(WR-AD)
(0.5 × t cyc - 10)ns(min.)
td(BCLK-WR)
th(BCLK-WR)
ALE
25ns(max.)
0ns(min.)
WR, WRL,
WRH
td(BCLK-DB)
40ns(max.)
Hi-Z
DBi
td(DB-WR)
th(WR-DB)
(0.5 × t cyc - 40)ns(min.) (0.5 × t cyc - 20)ns(min.)
tcyc =
1
f(BCLK)
Measuring conditions
y VCC1 = VCC2 = 5V
y Input timing voltage: VIL = 0.8 V, VIH = 2.0 V
y Output timing voltage: VOL = 0.4 V, VOH = 2.4 V
Figure 5.15
Timing Diagram
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 76 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 =
Switching Characteristics
(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.2.4.2
Table 5.37
5V
In 1 to 3 Waits Setting and When Accessing External Area
Memory Expansion Mode and Microprocessor Mode (in 1 to 3 Waits Setting and When
Accessing External Area)
Symbol
Parameter
Standard
Measuring
Condition
Min.
Max.
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (in relation to BCLK)
0
ns
th(RD-AD)
Address output hold time (in relation to RD)
0
ns
th(WR-AD)
Address output hold time (in relation to WR)
(Note 2)
ns
td(BCLK-CS)
Chip select output delay time
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
td(BCLK-ALE)
ALE signal output delay time
th(BCLK-ALE)
ALE signal output hold time
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(BCLK-DB)
Data output delay time (in relation to BCLK)
td(DB-WR)
Data output delay time (in relation to WR)
(Note 1)
ns
th(WR-DB)
Data output hold time (in relation to WR)(3)
(Note 4)
ns
25
ns
25
ns
0
ns
15
ns
-4
See
Figure 5.14
ns
25
ns
0
ns
25
ns
0
ns
40
ns
Notes:
1. Calculated according to the BCLK frequency as follows:
9
(----------------------------------n – 0.5 ) × 10 - – 40 [ ns ]
f ( BCLK )
2.
n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.
When n = 1, f(BCLK) is 12.5 MHz or less.
Calculated according to the BCLK frequency as follows:
9
0.5
× 10 - – 10 [ ns ]
--------------------f ( BCLK )
3.
4.
This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR × ln(1 − VOL/VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ, hold
time of output low level is
t = −30 pF × 1 kΩ × In(1 − 0.2VCC2/VCC2)
= 6.7 ns.
Calculated according to the BCLK frequency as follows:
R
DBi
C
9
0.5
× 10 - – 20 [ ns ]
--------------------f ( BCLK )
Hold time is equal to or less than 0 ns when the BCLK frequency exceeds 25 MHz.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 77 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Memory Expansion Mode and Microprocessor Mode
(in 1 to 3 waits setting and when accessing external area)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
25ns(max.)
0ns(min.)
CSi
tcyc
ADi
BHE
td(BCLK-AD)
th(BCLK-AD)
25ns(max.)
0ns(min.)
td(BCLK-ALE)
15ns(max.)
th(BCLK-ALE)
th(RD-AD)
-4ns(min.)
0ns(min.)
ALE
th(BCLK-RD)
td(BCLK-RD)
0ns(min.)
25ns(max.)
RD
tac2(RD-DB)
{(n+0.5) × tcyc -45}ns(max.)
Hi-Z
DBi
th(RD-DB)
tsu(DB-RD)
0ns(min.)
50ns(min.)
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
25ns(max.)
0ns(min.)
CSi
tcyc
th(BCLK-AD)
td(BCLK-AD)
0ns(min.)
25ns(max.)
ADi
BHE
td(BCLK-ALE)
15ns(max.)
th(BCLK-ALE)
th(WR-AD)
(0.5 × t cyc - 10)ns(min.)
-4ns(min.)
ALE
th(BCLK-WR)
td(BCLK-WR)
WR, WRL,
WRH
0ns(min.)
25ns(max.)
td(BCLK-DB)
40ns(max.)
Hi-Z
DBi
td(DB-WR)
th(WR-DB)
{(n-0.5) × tcyc -40}ns(min.) (0.5 × t cyc - 20)ns(min.)
tcyc =
1
f(BCLK)
Measuring conditions
y VCC1 = VCC2 = 5V
y Input timing voltage: VIL = 0.8 V, VIH = 2.0 V
y Output timing voltage: VOL = 0.4 V, VOH = 2.4 V
Figure 5.16
n: 1 (when 1 wait)
2 (when 2 waits)
3 (when 3 waits)
Timing Diagram
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 78 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 =
Switching Characteristics
(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5V
5.2.4.3
In 2 or 3 Waits Setting, and When Accessing External Area and Using
Multiplexed Bus
Table 5.38
Memory Expansion Mode and Microprocessor Mode (in 2 or 3 Waits Setting, and When
Accessing External Area and Using Multiplexed Bus) (5)
Symbol
Measuring
Condition
Parameter
Standard
Min.
Max.
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (in relation to BCLK)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
Chip select output delay time
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
0
ns
th(RD-CS)
Chip select output hold time (in relation to RD)
(Note 1)
ns
th(WR-CS)
Chip select output hold time (in relation to WR)
(Note 1)
ns
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(BCLK-DB)
Data output delay time (in relation to BCLK)
td(DB-WR)
Data output delay time (in relation to WR)
(Note 2)
ns
th(WR-DB)
Data output hold time (in relation to WR)
(Note 6)
ns
td(BCLK-ALE)
ALE signal output delay time (in relation to BCLK)
th(BCLK-ALE)
ALE signal output hold time (in relation to BCLK)
td(AD-ALE)
25
ns
0
ns
Address output hold time (in relation to RD)
(Note 1)
ns
Address output hold time (in relation to WR)
(Note 1)
ns
25
25
0
ns
ns
25
See
Figure 5.14
ns
0
ns
ns
40
15
ns
ns
−4
ns
ALE signal output delay time (in relation to Address)
(Note 3)
ns
th(AD-ALE)
ALE signal output hold time (in relation to Address)
(Note 4)
ns
td(AD-RD)
RD signal output delay from the end of address
0
ns
td(AD-WR)
WR signal output delay from the end of address
0
ns
tdz(RD-AD)
Address output floating start time
8
ns
Notes:
1.
Calculated according to the BCLK frequency as follows:
9
0.5
× 10 - – 10 [ ns ]
--------------------f ( BCLK )
2.
Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) × 10 - – 40 [ ns ]
----------------------------------n is 2 for 2-wait setting, 3 for 3-wait setting.
f ( BCLK )
3.
Calculated according to the BCLK frequency as follows:
9
0.5
× 10 - – 25 [ ns ]
--------------------f ( BCLK )
4.
Calculated according to the BCLK frequency as follows:
9
0.5
× 10 - – 15 [ ns ]
--------------------f ( BCLK )
5.
When using multiplex bus, set f(BCLK) 12.5 MHz or less.
6.
Calculated according to the BCLK frequency as follows: ---------------------- – 20 [ ns ]
9
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
0.5 × 10
f ( BCLK )
Page 79 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Memory Expansion Mode and Microprocessor Mode
(in 2 or 3 waits setting, and when accessing external area and using multiplexed bus )
Read timing
BCLK
th(BCLK-CS)
td(BCLK-CS)
th(RD-CS)
tcyc
25ns(max.)
0ns(min.)
(0.5 × t cyc-10)ns(min.)
CSi
td(AD-ALE)
(0.5 × t cyc-25ns(min.)
ADi
/DBi
th(ALE-AD)
(0.5 × t cyc-15ns(min.)
Address
Address
Data input
tdz(RD-AD)
8ns(max.)
tsu(DB-RD)
tac3(RD-DB)
{(n-0.5) × tcyc -45}ns(max.) 50ns(min.)
th(RD-DB)
0ns(min.)
td(AD-RD)
td(BCLK-AD)
0ns(min.)
25ns(max.)
th(BCLK-AD)
0ns(min.)
ADi
BHE
td(BCLK-ALE)
15ns(max.)
th(BCLK-ALE)
th(RD-AD)
(0.5 × t cyc-10)ns(min.)
-4ns(min.)
ALE
td(BCLK-RD)
25ns(max.)
th(BCLK-RD)
0ns(min.)
RD
Write timing
BCLK
td(BCLK-CS)
tcyc
25ns(max.)
th(WR-CS)
(0.5 × t cyc-10)ns(min.)
th(BCLK-CS)
0ns(min.)
CSi
td(BCLK-DB)
40ns(max.)
ADi
/DBi
Address
Address
Data output
td(DB-WR)
{(n-0.5) × tcyc -40}ns(min.)
td(AD-ALE)
(0.5 × t cyc-25ns(min.)
th(WR-DB)
(0.5 × t cyc-20)ns(min.)
td(BCLK-AD)
th(BCLK-AD)
25ns(max.)
ADi
BHE
td(BCLK-ALE)
15ns(max.)
0ns(min.)
th(BCLK-ALE)
td(AD-WR)
-4ns(min.)
0ns(min.)
th(WR-AD)
(0.5 × t cyc-10)ns(min.)
ALE
th(BCLK-WR)
td(BCLK-WR)
25ns(max.)
0ns(min.)
WR, WRL,
WRH
Measuring conditions
y VCC1 = VCC2 = 5V
y Input timing voltage: VIL = 0.8 V, VIH = 2.0 V
y Output timing voltage: VOL = 0.4 V, VOH = 2.4 V
Figure 5.17
n: 2 (when 2 waits)
3 (when 3 waits)
Timing Diagram
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 80 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 =
Switching Characteristics
(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5V
5.2.4.4
In Wait State Setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and When
Accessing External Area
Table 5.39
Memory Expansion Mode and Microprocessor Mode (in Wait State Setting 2 φ + 3 φ, 2 φ
+ 4φ, 3φ + 4φ, and 4φ + 5φ, and When Accessing External Area)
Symbol
Standard
Measuring
Condition
Parameter
Min.
Max.
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (in relation to BCLK)
0
ns
th(RD-AD)
Address output hold time (in relation to RD)
0
ns
th(WR-AD)
Address output hold time (in relation to WR)
(Note 2)
ns
td(BCLK-CS)
Chip select output delay time
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
td(BCLK-ALE)
ALE signal output delay time
th(BCLK-ALE)
ALE signal output hold time
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(BCLK-DB)
Data output delay time (in relation to BCLK)
td(DB-WR)
Data output delay time (in relation to WR)
th(WR-DB)
Data output hold time (in relation to WR)
25
ns
25
ns
0
ns
15
ns
-4
See
Figure 5.14
ns
25
ns
0
ns
25
ns
0
ns
40
(3)
ns
(Note 1)
ns
(Note 4)
ns
Notes:
1. Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) × 10
------------------------------------ – 40 [ ns ]
f ( BCLK )
2.
n is 3 for 2φ + 3φ, 4 for 2φ + 4φ, 4 for 3φ + 4φ, and 5 for 4φ + 5φ.
Calculated according to the BCLK frequency as follows:
9
0.5
× 10 - – 10 [ ns ]
--------------------f ( BCLK )
3.
This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR × ln(1 − VOL/VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ, hold
time of output low level is
t = −30 pF × 1 kΩ × In(1 − 0.2VCC2/VCC2)
= 6.7 ns.
R
DBi
C
9
4.
0.5 × 10
Calculated according to the BCLK frequency as follows: ---------------------- – 20 [ ns ]
f ( BCLK )
Hold time is equal to or less than 0 ns when the BCLK frequency exceeds 25 MHz.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 81 of 109
M16C/65C Group
5. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode
(in wait state setting 2 φ + 3 φ, 2 φ + 4 φ, 3φ + 4 φ, and 4 φ + 5 φ, and
when accessing external area)
Read timing
VCC1 = VCC2 = 5V
tcyc
BCLK
th(BCLK-CS)
0ns(min.)
td(BCLK-CS)
25ns(max.)
CSi
td(BCLK-AD)
25ns(max.)
th(BCLK-AD)
0ns(min.)
ADi
BHE
td(BCLK-ALE)
15ns(max.)
th(RD-AD)
0ns(min.)
th(BCLK-ALE)
-4ns(min.)
ALE
td(BCLK-RD)
25ns(max.)
th(BCLK-RD)
0ns(min.)
RD
tac4(RD-DB)
(n × tcyc-45)ns(max.)
Hi-Z
DBi
tsu(DB-RD)
50ns(min.)
Write timing
th(RD-DB)
0ns(min.)
tcyc
BCLK
td(BCLK-CS)
25ns(max.)
th(BCLK-CS)
0ns(min.)
td(BCLK-AD)
25ns(max.)
th(BCLK-AD)
0ns(min.)
CSi
ADi
BHE
td(BCLK-ALE)
15ns(max.)
th(WR-AD)
(0.5 × tcyc -10)ns(min.)
th(BCLK-ALE)
-4ns(min.)
ALE
th(BCLK-WR)
0ns(min.)
td(BCLK-WR)
25ns(max.)
WR, WRL
WRH
td(BCLK-DB)
40ns(max.)
Hi-Z
DBi
1
tcyc =
f(BCLK)
Measuring conditions
y VCC1 = VCC2 = 5V
y Input timing voltage: VIL = 0.8 V, VIH = 2.0 V
y Output timing voltage: VOL = 0.4 V, VOH = 2.4 V
Figure 5.18
td(DB-WR)
{(n-0.5) × tcyc -40}ns(min.)
th(WR-DB)
(0.5 × tcyc -20)ns(min.)
n: 3 (when 2 φ + 3 φ)
4 (when 2 φ + 4 φ or 3 φ + 4 φ)
5 (when 4 φ + 5 φ)
Timing Diagram
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 82 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 =
Switching Characteristics
(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.2.4.5
5V
In Wait State Setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and When
Inserting 1 to 3 Recovery Cycles and Accessing External Area
Table 5.40
Memory Expansion and Microprocessor Modes (in Wait State Setting 2φ + 3φ, 2φ + 4φ,
3φ + 4φ, and 4φ + 5φ, and When Inserting 1 to 3 Recovery Cycles and Accessing
External Area)
Symbol
Parameter
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (in relation to BCLK)
Measuring
Condition
Standard
Min.
Unit
Max.
25
ns
0
ns
th(RD-AD)
Address output hold time (in relation to RD)
(Note 4)
ns
th(WR-AD)
Address output hold time (in relation to WR)
(Note 2)
ns
td(BCLK-CS)
Chip select output delay time
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
td(BCLK-ALE)
ALE signal output delay time
25
ns
15
ns
0
ns
th(BCLK-ALE)
ALE signal output hold time
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(BCLK-DB)
Data output delay time (in relation to BCLK)
td(DB-WR)
Data output delay time (in relation to WR)
(Note 1)
ns
th(WR-DB)
Data output hold time (in relation to WR) (3)
(Note 5)
ns
See
Figure 5.14
-4
ns
25
ns
0
ns
25
ns
0
ns
40
ns
Notes:
1.
Calculated according to the BCLK frequency as follows:
9
n × 10 - – 40 [ ns ]
----------------f ( BCLK )
2.
Calculated according to the BCLK frequency as follows:
9
m
× 10 - – 10 [ ns ]
-----------------f ( BCLK )
3.
4.
m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and
3 when 3 recovery cycles are inserted.
This standard value shows the timing when the output is off, and does not
show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up (pull-down)
resistance value.
Hold time of data bus is expressed in
t = −CR × ln(1−VOL/VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ, hold time of output
low level is
t = −30 pF × 1 kΩ × In(1 − 0.2VCC2/VCC2)
= 6.7 ns.
Calculated according to the BCLK frequency as follows:
9
m
× 10 - + 0 [ ns ]
-----------------f ( BCLK )
5.
n is 3 for 2φ + 3φ, 4 for 2φ + 4φ, 4 for 3φ + 4φ, and 5 for 4φ + 5φ.
R
DBi
C
m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and
3 when 3 recovery cycles are inserted.
Calculated according to the BCLK frequency as follows:
9
m
× 10 - – 20 [ ns ]
-----------------f ( BCLK )
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and
3 when 3 recovery cycles are inserted.
Page 83 of 109
M16C/65C Group
5. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode
(in wait state setting 2 φ + 3 φ, 2 φ + 4 φ, 3φ + 4 φ, and 4 φ + 5 φ, and
when inserting 1 to 3 recovery cycles and accessing external area)
Read timing
VCC1 = VCC2 = 5V
tcyc
BCLK
th(BCLK-CS)
0ns(min.)
td(BCLK-CS)
25ns(max.)
CSi
th(BCLK-AD)
0ns(min.)
td(BCLK-AD)
25ns(max.)
ADi
BHE
td(BCLK-ALE)
15ns(max.)
th(RD-AD)
(m × tcyc+0)ns(min.)
th(BCLK-ALE)
-4ns(min.)
ALE
th(BCLK-RD)
0ns(min.)
td(BCLK-RD)
25ns(max.)
RD
tac4(RD-DB)
(n × tcyc -45)ns(max.)
Hi-Z
DBi
tsu(DB-RD)
50ns(min.)
th(RD-DB)
0ns(min.)
Write timing
tcyc
BCLK
td(BCLK-CS)
25ns(max.)
th(BCLK-CS)
0ns(min.)
td(BCLK-AD)
25ns(max.)
th(BCLK-AD)
0ns(min.)
CSi
ADi
BHE
td(BCLK-ALE)
15ns(max.)
th(WR-AD)
(m × tcyc -10)ns(min.)
th(BCLK-ALE)
-4ns(min.)
ALE
th(BCLK-WR)
0ns(min.)
td(BCLK-WR)
25ns(max.)
WR, WRL
WRH
Hi-Z
DBi
td(BCLK-DB)
40ns(max.)
1
tcyc =
f(BCLK)
Measuring conditions
y VCC1 = VCC2 = 5V
y Input timing voltage: VIL = 0.8 V, VIH = 2.0 V
y Output timing voltage: VOL = 0.4 V, VOH = 2.4 V
Figure 5.19
td(DB-WR)
(n × tcyc -40)ns(min.)
th(WR-DB)
(m × tcyc -20)ns(min.)
n: 3 (when 2 φ + 3 φ)
4 (when 2 φ + 4 φ or 3 φ + 4 φ)
5 (when 4 φ + 5 φ)
m: 1 (when 1 recovery cycle inserted )
2 (when 2 recovery cycles inserted)
3 (when 3 recovery cycles inserted)
Timing Diagram
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 84 of 109
M16C/65C Group
5.3
5. Electrical Characteristics
Electrical Characteristics (VCC1 = VCC2 = 3 V)
5.3.1
Electrical Characteristics
VCC1 = VCC2 = 3 V
Table 5.41
Electrical Characteristics (1)
(1)
VCC1 = VCC2 = 2.7 to 3.3 V, VSS = 0 V at Topr = -20°C to 85°C/-40°C to 85°C, f(BCLK) = 32 MHz unless otherwise specified.
Symbol
VOH
VOH
Parameter
High
output
voltage
VOL
VT+-VT-
Standard
Min.
Typ.
IOH = −1 mA
VCC1 − 0.5
VCC1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOH = −1 mA
VCC2 − 0.5
VCC2
HIGH POWER
IOH = −0.1 mA
VCC1 − 0.5
VCC1
LOW POWER
IOH = −50 μA
VCC1 − 0.5
VCC1
High output voltage
XOUT
XCOUT
HIGH POWER
With no load applied
2.6
LOW POWER
With no load applied
2.2
Low output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to
IOL = 1 mA
voltage
P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOL = 1 mA
CEC
IOL = 1 mA
Low output voltage
XOUT
Low output voltage
XCOUT
0
IOL = 0.1 mA
LOW POWER
IOL = 50 μA
HIGH POWER
With no load applied
0
LOW POWER
With no load applied
0
0.2
0.2
0.2
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,
P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
XIN, RESET, CNVSS, BYTE
−
Leakage current in powered-off state
IIL
Low input
current
V
V
0.5
V
0.5
V
0.5
CEC
High input
current
V
0.5
RESET
IIH
Unit
V
0.5
HIGH POWER
Hysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to
INT7, NMI, ADTRG, CTS0 to CTS2, CTS5 to CTS7,
SCL0 to SCL2, SCL5 to SCL7, SDA0 to SDA2, SDA5
to SDA7, CLK0 to CLK7, TA0OUT to TA4OUT, KI0 to
KI3, RXD0 to RXD2, RXD5 to RXD7, SIN3, SIN4, SD,
PMC0, PMC1, SCLMM, SDAMM, ZP, IDU, IDV, IDW
RPULLUP Pull-up
resistance
Max.
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
High output voltage
VOL
Measuring Condition
0.5
VI = 3 V
V
1.0
V
1.0
V
1.8
V
4.0
μA
VCC1 = 0 V
1.8
μA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,
P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
XIN, RESET, CNVSS, BYTE
VI = 0 V
−4.0
μA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to
P13_7, P14_0, P14_1
VI = 0 V
50
150
kΩ
In stop mode
1.8
RfXIN
Feedback resistance XIN
VRAM
RAM retention voltage
CEC
80
3.0
MΩ
V
Note:
1. When VCC1 ≠ VCC2, refer to 5 V or 3 V standard depending on the voltage.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 85 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 = 3 V
Table 5.42
Electrical Characteristics (2)
R5F36506CNFA, R5F36506CNFB, R5F36506CDFA, R5F36506CDFB, R5F3650ECNFA, R5F3650ECNFB,
R5F3650ECDFA, R5F3650ECDFB
VCC1 = VCC2 = 2.7 to 3.3 V, VSS = 0 V at Topr = −20°C to 85°C/−40°C to 85°C, f(BCLK) = 32 MHz unless otherwise specified.
Symbol
RfXCIN
ICC
Parameter
Measuring Condition
Feedback resistance
XCIN
Power supply current High-speed mode
In single-chip, mode,
the output pin are
open and other pins
are VSS
40 MHz on-chip
oscillator mode
125 kHz on-chip
oscillator mode
Low-power mode
Wait mode
Stop mode
During flash
memory program
During flash
memory erase
Note:
1.
f(BCLK) = 32 MHz
XIN = 4 MHz (square wave), PLL multiplied by 8
125 kHz on-chip oscillator stopped
f(BCLK) = 32 MHz, A/D conversion
XIN = 4 MHz (square wave), PLL multiplied by 8
125 kHz on-chip oscillator stopped
f(BCLK) = 20 MHz
XIN = 20 MHz (square wave)
125 kHz on-chip oscillator stopped
Main clock stopped
40 MHz on-chip oscillator on,
divide-by-4 (f(BCLK) = 10 MHz)
125 kHz on-chip oscillator stopped
Main clock stopped
40 MHz on-chip oscillator stopped
125 kHz on-chip oscillator on, no division
FMR22 = 1 (slow read mode)
f(BCLK) = 32 MHz
In low-power mode
FMR 22 = FMR23 = 1
On flash memory (1)
f(BCLK) = 32 MHz
In low-power mode
On RAM (1)
Main clock stopped
40 MHz on-chip oscillator stopped
125 kHz on-chip oscillator on
Peripheral clock operating
Topr = 25°C
f(BCLK) = 32 MHz (oscillation capacity High)
40 MHz on-chip oscillator stopped
125 kHz on-chip oscillator stopped
Peripheral clock operating
Topr = 25°C
f(BCLK) = 32 kHz (oscillation capacity Low)
40 MHz on-chip oscillator stopped
125 kHz on-chip oscillator stopped
Peripheral clock operating
Topr = 25°C
XIN = 6 MHz
40 MHz on-chip oscillator stopped
125 kHz on-chip oscillator stopped
Peripheral clock f1 provision disabled except
timers (PCKSTP1A = 1)
Main clock as a timer clock source
(PCKSTP11 = 0, PCKSTP17 = 1)
A given timer operating
Main clock stopped
40 MHz on-chip oscillator stopped
125 kHz on-chip oscillator stopped
Peripheral clock stopped
Topr = 25°C
f(BCLK) = 10 MHz, PM17 = 1 (one wait)
VCC1 = 3.0 V
f(BCLK) = 10 MHz, PM17 = 1 (one wait)
VCC1 = 3.0 V
Min.
Standard
Typ.
Max.
Unit
16
MΩ
24.0
mA
24.7
mA
16.0
mA
17.0
mA
450.0
μA
160.0
μA
40.0
μA
20.0
μA
8.0
μA
4.0
μA
0.5
mA
1.6
μA
20.0
mA
30.0
mA
This indicates the memory in which the program to be executed exists.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 86 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 = 3 V
Table 5.43
Electrical Characteristics (3) (1/2)
R5F3651ECNFC, R5F3651KCNFC, R5F3650KCNFA, R5F3650KCNFB, R5F3651MCNFC, R5F3650MCNFA,
R5F3650MCNFB, R5F3651NCNFC, R5F3650NCNFA, R5F3650NCNFB,
R5F3651ECDFC, R5F3651KCDFC, R5F3650KCDFA, R5F3650KCDFB, R5F3651MCDFC, R5F3650MCDFA,
R5F3650MCDFB, R5F3651NCDFC, R5F3650NCDFA, R5F3650NCDFB
VCC1 = VCC2 = 2.7 to 3.3 V, VSS = 0 V at Topr = −20°C to 85°C/−40°C to 85°C, f(BCLK) = 32 MHz unless otherwise specified.
Symbol
RfXCIN
ICC
Parameter
Measuring Condition
Feedback resistance
XCIN
Power supply current High-speed mode
In single-chip, mode,
the output pin are
open and other pins
are VSS
40 MHz on-chip
oscillator mode
125 kHz on-chip
oscillator mode
Low-power mode
Wait mode
f(BCLK) = 32 MHz
XIN = 4 MHz (square wave),
PLL multiplied by 8
125 kHz on-chip oscillator stopped
Min.
Standard
Typ.
Max.
Unit
16
MΩ
26.0
mA
27.0
mA
17.0
mA
f(BCLK) = 32 MHz, A/D conversion
XIN = 4 MHz (square wave),
PLL multiplied by 8
125 kHz on-chip oscillator stopped
f(BCLK) = 20 MHz
XIN = 20 MHz (square wave)
125 kHz on-chip oscillator stopped
Main clock stopped
40 MHz on-chip oscillator on,
divide-by-4 (f(BCLK) = 10 MHz)
125 kHz on-chip oscillator stopped
Main clock stopped
40 MHz on-chip oscillator stopped
125 kHz on-chip oscillator on, no division
FMR22 = 1 (slow read mode)
f(BCLK) = 32 MHz
In low-power mode, FMR 22 = FMR23 = 1
on flash memory (1)
f(BCLK) = 32 MHz
In low-power mode,
on RAM (1)
Main clock stopped
40 MHz on-chip oscillator stopped
125 kHz on-chip oscillator on
Peripheral clock operating
Topr = 25°C
18.0
mA
500.0
μA
170.0
μA
40.0
μA
20.0
μA
f(BCLK) = 32 MHz (oscillation capacity High)
40 MHz on-chip oscillator stopped
125 kHz on-chip oscillator stopped
Peripheral clock operating
Topr = 25°C
8.0
μA
f(BCLK) = 32 kHz (oscillation capacity Low)
40 MHz on-chip oscillator stopped
125 kHz on-chip oscillator stopped
Peripheral clock operating
Topr = 25°C
4.0
μA
XIN = 6 MHz
40 MHz on-chip oscillator stopped
125 kHz on-chip oscillator stopped
Peripheral clock f1 provision disabled except
timers (PCKSTP1A = 1)
Main clock as a timer clock source
(PCKSTP11 = 0, PCKSTP17 = 1)
A given timer operating
0.5
mA
Note:
1. This indicates the memory in which the program to be executed exists.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 87 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 = 3 V
Table 5.44
Electrical Characteristics (3) (2/2)
R5F3651ECNFC, R5F3651KCNFC, R5F3650KCNFA, R5F3650KCNFB, R5F3651MCNFC, R5F3650MCNFA,
R5F3650MCNFB, R5F3651NCNFC, R5F3650NCNFA, R5F3650NCNFB,
R5F3651ECDFC, R5F3651KCDFC, R5F3650KCDFA, R5F3650KCDFB, R5F3651MCDFC, R5F3650MCDFA,
R5F3650MCDFB, R5F3651NCDFC, R5F3650NCDFA, R5F3650NCDFB
VCC1 = VCC2 = 2.7 to 3.3 V, VSS = 0 V at Topr = −20°C to 85°C/−40°C to 85°C, f(BCLK) = 32 MHz unless otherwise specified.
Symbol
ICC
Parameter
Measuring Condition
Power supply current Stop mode
In single-chip, mode,
the output pin are
open and other pins
are VSS
During flash
memory program
During flash
memory erase
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Min.
Standard
Typ.
Max.
Unit
Main clock stopped
40 MHz on-chip oscillator stopped
125 kHz on-chip oscillator stopped
Peripheral clock stopped
Topr = 25°C
1.6
μA
f(BCLK) = 10 MHz, PM17 = 1 (one wait)
VCC1 = 3.0 V
20.0
mA
f(BCLK) = 10 MHz, PM17 = 1 (one wait)
VCC1 = 3.0 V
30.0
mA
Page 88 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 = 3 V
5.3.2
Timing Requirements (Peripheral Functions and Others)
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.3.2.1
Reset Input (RESET Input)
Table 5.45
Reset Input (RESET Input)
Symbol
Standard
Parameter
Min.
RESET input low pulse width
tw(RSTL)
Max.
Unit
μs
10
RESET input
t w(RTSL)
Figure 5.20
5.3.2.2
Table 5.46
Reset Input (RESET Input)
External Clock Input
External Clock Input (XIN Input) (1)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc
External clock input cycle time
50
ns
tw(H)
External clock input high pulse width
20
ns
tw(L)
External clock input low pulse width
20
tr
External clock rise time
9
ns
tf
External clock fall time
9
ns
Note:
1.
ns
The condition is VCC1 = VCC2 = 2.7 to 3.0 V.
XIN input
tr
t w(H)
tf
t w(L)
tc
Figure 5.21
External Clock Input (XIN Input)
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 89 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 =
Timing Requirements
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.3.2.3
Table 5.47
Timer A Input
Timer A Input (Counter Input in Event Counter Mode)
Symbol
Standard
Parameter
Min.
Unit
Max.
tc(TA)
TAiIN input cycle time
150
ns
tw(TAH)
TAiIN input high pulse width
60
ns
tw(TAL)
TAiIN input low pulse width
60
ns
Table 5.48
Timer A Input (Gating Input in Timer Mode)
Symbol
Standard
Parameter
Min.
Unit
Max.
tc(TA)
TAiIN input cycle time
600
ns
tw(TAH)
TAiIN input high pulse width
300
ns
tw(TAL)
TAiIN input low pulse width
300
ns
Table 5.49
Timer A Input (External Trigger Input in One-Shot Timer Mode)
Symbol
Standard
Parameter
Min.
Unit
Max.
tc(TA)
TAiIN input cycle time
300
ns
tw(TAH)
TAiIN input high pulse width
150
ns
tw(TAL)
TAiIN input low pulse width
150
ns
Table 5.50
3V
Timer A Input (External Trigger Input in Pulse Width Modulation Mode and
Programmable Output Mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tw(TAH)
TAiIN input high pulse width
150
ns
tw(TAL)
TAiIN input low pulse width
150
ns
tc(TA)
t w(TAH)
TAiIN input
t w(TAL)
tc(UP)
t w(UPH)
TAiOUT input
t w(UPL)
Figure 5.22
Timer A Input
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 90 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 =
Timing Requirements
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
Table 5.51
3V
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
2
μs
tsu(TAIN-TAOUT)
TAiOUT input setup time
500
ns
tsu(TAOUT-TAIN)
TAiIN input setup time
500
ns
Two-phase pulse input in event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
Figure 5.23
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 91 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 =
Timing Requirements
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.3.2.4
Table 5.52
3V
Timer B Input
Timer B Input (Counter Input in Event Counter Mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time (counted on one edge)
150
ns
tw(TBH)
TBiIN input high pulse width (counted on one edge)
60
ns
tw(TBL)
TBiIN input low pulse width (counted on one edge)
60
ns
tc(TB)
TBiIN input cycle time (counted on both edges)
300
ns
tw(TBH)
TBiIN input high pulse width (counted on both edges)
120
ns
tw(TBL)
TBiIN input low pulse width (counted on both edges)
120
ns
Table 5.53
Timer B Input (Pulse Period Measurement Mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
600
ns
tw(TBH)
TBiIN input high pulse width
300
ns
tw(TBL)
TBiIN input low pulse width
300
ns
Table 5.54
Timer B Input (Pulse Width Measurement Mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
600
ns
tw(TBH)
TBiIN input high pulse width
300
ns
tw(TBL)
TBiIN input low pulse width
300
ns
tc(TB)
t w(TBH)
TBiIN input
t w(TBL)
Figure 5.24
Timer B Input
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 92 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 =
Timing Requirements
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.3.2.5
Table 5.55
3V
Serial Interface
Serial Interface
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
300
ns
tw(CKH)
CLKi input high pulse width
150
ns
tw(CKL)
CLKi input low pulse width
150
td(C-Q)
TXDi output delay time
th(C-Q)
TXDi hold time
tsu(D-C)
th(C-D)
ns
160
ns
0
ns
RXDi input setup time
100
ns
RXDi input hold time
90
ns
tc(CK)
t w(CKH)
CLKi
t w(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
Figure 5.25
5.3.2.6
Table 5.56
Serial Interface
External Interrupt INTi Input
External Interrupt INTi Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tw(INH)
INTi input high pulse width
380
ns
tw(INL)
INTi input low pulse width
380
ns
t w(INL)
INTi input
t w(INH)
Figure 5.26
External Interrupt INTi Input
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 93 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 =
Timing Requirements
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
3V
Multi-master I2C-bus
5.3.2.7
Multi-master I2C-bus
Table 5.57
Symbol
Standard Clock Mode
Parameter
Min.
Fast-mode
Max.
Min.
Unit
Max.
tBUF
Bus free time
4.7
1.3
μs
tHD;STA
Hold time in start condition
4.0
0.6
μs
tLOW
Hold time in SCL clock 0 status
4.7
1.3
μs
tR
SCL, SDA signals’ rising time
tHD;DAT
Data hold time
tHIGH
Hold time in SCL clock 1 status
fF
SCL, SDA signals’ falling time
tsu;DAT
Data setup time
250
100
ns
tsu;STA
Setup time in restart condition
4.7
0.6
μs
tsu;STO
Stop condition setup time
4.0
0.6
μs
1000
20 + 0.1 Cb
300
ns
0
0
0.9
μs
4.0
0.6
300
20 + 0.1 Cb
μs
300
ns
SDA
t HD;STA
t BUF
t su;STO
t LOW
tR
SCL
p
t HD;STA
Figure 5.27
tF
Sr
s
t HD;DAT
t HIGH
t su;DAT
p
t su;STA
Multi-master I2C-bus
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 94 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 =
Timing Requirements
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.3.3
3V
Timing Requirements (Memory Expansion Mode and Microprocessor
Mode)
Table 5.58
Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
Standard
Min.
Max.
Unit
tac1(RD-DB)
Data input access time (for setting with no wait)
(Note 1)
ns
tac2(RD-DB)
Data input access time (for setting with wait)
(Note 2)
ns
tac3(RD-DB)
Data input access time (when accessing multiplex bus area)
(Note 3)
ns
tac4(RD-DB)
Data input access time (for setting with 2 φ + 3 φ or more)
(Note 4)
ns
tsu(DB-RD)
Data input setup time
60
ns
tsu(RDY-BCLK)
RDY input setup time
85
ns
th(RD-DB)
Data input hold time
0
ns
th(BCLK-RDY)
RDY input hold time
0
ns
Notes:
1. Calculated according to the BCLK frequency as follows:
9
0.5
× 10 - – 60 [ ns ]
--------------------f ( BCLK )
2.
Calculated according to the BCLK frequency as follows:
9
( n + 0.5 ) × 10 - – 60 [ ns ]
----------------------------------f ( BCLK )
3.
n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.
Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) × 10 - – 60 [ ns ]
----------------------------------f ( BCLK )
4.
n is 2 for 2 waits setting, 3 for 3 waits setting.
Calculated according to the BCLK frequency as follows:
9
n × 10 - – 60 [ ns ]
----------------f ( BCLK )
n is 3 for 2 φ + 3 φ, 4 for 2 φ + 4 φ, 4 for 3 φ + 4 φ, 5 for 4 φ + 5 φ,.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 95 of 109
M16C/65C Group
5. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode
VCC1 = VCC2 = 3 V
(Effective in wait state setting)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY-BCLK)
th(BCLK-RDY)
Measuring conditions
y VCC1 = VCC2 = 3 V
y Input timing voltage: VIL = 0.6 V, VIH = 2.4 V
y Output timing voltage: VOL = 1.5 V, VOH = 1.5 V
Figure 5.28
Timing Diagram
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 96 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 = 3 V
5.3.4
Switching Characteristics (Memory Expansion Mode and Microprocessor
Mode)
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.3.4.1
Table 5.59
In No Wait State Setting
Memory Expansion and Microprocessor Modes (in No Wait State Setting)
Symbol
Parameter
Standard
Min.
Max.
Measuring
Condition
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (in relation to BCLK)
0
ns
th(RD-AD)
Address output hold time (in relation to RD)
0
ns
th(WR-AD)
Address output hold time (in relation to WR)
(Note 2)
ns
td(BCLK-CS)
Chip select output delay time
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
td(BCLK-ALE)
ALE signal output delay time
30
ns
30
ns
0
ns
25
ns
−4
th(BCLK-ALE)
ALE signal output hold time
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(BCLK-DB)
Data output delay time (in relation to BCLK)
td(DB-WR)
Data output delay time (in relation to WR)
(Note 1)
ns
th(WR-DB)
Data output hold time (in relation to WR) (3)
(Note 4)
ns
See
Figure 5.29
ns
30
ns
0
ns
30
ns
0
ns
40
ns
Notes:
1. Calculated according to the BCLK frequency as follows:
9
0.5
× 10 - – 40 [ ns ]
--------------------f ( BCLK )
2.
f(BCLK) is 12.5 MHz or less.
Calculated according to the BCLK frequency as follows:
9
0.5
× 10 - – 15 [ ns ]
--------------------f ( BCLK )
3.
4.
This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR × ln(1 − VOL/VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ,
hold time of output low level is
t = −30 pF × 1 kΩ × In(1 − 0.2VCC2/VCC2)
= 6.7 ns.
Calculated according to the BCLK frequency as follows:
R
DBi
C
9
0.5
× 10 - – 25 [ ns ]
--------------------f ( BCLK )
Hold time is equal to or less than 0 ns when the BCLK frequency exceeds 20 MHz.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 97 of 109
M16C/65C Group
5. Electrical Characteristics
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
Figure 5.29
30 pF
Ports P0 to P14 Measurement Circuit
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 98 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 = 3V
Memory Expansion Mode and Microprocessor Mode
(in no wait state setting)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
30ns(max.)
0ns(min.)
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
30ns(max.)
ADi
BHE
td(BCLK-ALE)
25ns(max.)
0ns(min.)
th(BCLK-ALE)
th(RD-AD)
-4ns(min.)
0ns(min.)
ALE
th(BCLK-RD)
td(BCLK-RD)
30ns(max.)
0ns(min.)
RD
tac1(RD-DB)
(0.5 × t cyc-60)ns(max.)
Hi-Z
DBi
tsu(DB-RD)
th(RD-DB)
60ns(min.)
0ns(min.)
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
30ns(max.)
0ns(min.)
CSi
tcyc
th(BCLK-AD)
td(BCLK-AD)
0ns(min.)
30ns(max.)
ADi
BHE
td(BCLK-ALE)
25ns(max.)
th(BCLK-ALE)
-4ns(min.)
th(WR-AD)
(0.5 × t cyc-15)ns(min.)
td(BCLK-WR)
th(BCLK-WR)
ALE
30ns(max.)
0ns(min.)
WR, WRL,
WRH
td(BCLK-DB)
40ns(max.)
Hi-Z
DBi
td(DB-WR)
(0.5 × t cyc-40)ns(min.)
tcyc =
th(WR-DB)
(0.5 × t cyc-25)ns(min.)
1
f(BCLK)
Measuring conditions
y VCC1 = VCC2 = 3V
y Input timing voltage: VIL = 0.6 V, VIH = 2.4 V
y Output timing voltage: VOL = 1.5 V, VOH = 1.5 V
Figure 5.30
Timing Diagram
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 99 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 =
Switching Characteristics
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.3.4.2
Table 5.60
3V
In 1 to 3 Waits Setting and When Accessing External Area
Memory Expansion Mode and Microprocessor Mode (in 1 to 3 Waits Setting and When
Accessing External Area)
Symbol
Parameter
Standard
Measuring
Condition
Min.
Max.
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (in relation to BCLK)
0
ns
th(RD-AD)
Address output hold time (in relation to RD)
0
ns
th(WR-AD)
Address output hold time (in relation to WR)
(Note 2)
ns
td(BCLK-CS)
Chip select output delay time
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
td(BCLK-ALE)
ALE signal output delay time
th(BCLK-ALE)
ALE signal output hold time
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(BCLK-DB)
Data output delay time (in relation to BCLK)
td(DB-WR)
Data output delay time (in relation to WR)
(Note 1)
ns
th(WR-DB)
Data output hold time (in relation to WR) (3)
(Note 4)
ns
30
ns
30
ns
0
ns
25
ns
-4
See
Figure 5.29
ns
30
ns
0
ns
30
ns
0
ns
40
ns
Notes:
1. Calculated according to the BCLK frequency as follows:
9
(----------------------------------n – 0.5 ) × 10 - – 40 [ ns ]
f ( BCLK )
2.
n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.
When n = 1, f(BCLK) is 12.5 MHz or less.
Calculated according to the BCLK frequency as follows:
9
0.5
× 10 - – 15 [ ns ]
--------------------f ( BCLK )
3.
4.
This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR × ln(1−VOL/VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ, hold
time of output low level is
t = −30 pF × 1 kΩ × In(1 − 0.2VCC2/VCC2)
= 6.7 ns.
Calculated according to the BCLK frequency as follows:
R
DBi
C
9
0.5
× 10 - – 25 [ ns ]
--------------------f ( BCLK )
Hold time is equal to or less than 0 ns when the BCLK frequency exceeds 20 MHz.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 100 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 = 3V
Memory Expansion Mode and Microprocessor Mode
(in 1 to 3 waits setting and when accessing external area)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
30ns(max.)
0ns(min.)
CSi
tcyc
ADi
BHE
td(BCLK-AD)
th(BCLK-AD)
30ns(max.)
0ns(min.)
td(BCLK-ALE)
25ns(max.)
th(BCLK-ALE)
th(RD-AD)
-4ns(min.)
0ns(min.)
ALE
th(BCLK-RD)
td(BCLK-RD)
0ns(min.)
30ns(max.)
RD
tac2(RD-DB)
{(n+0.5) × tcyc -60}ns(max.)
Hi-Z
DBi
th(RD-DB)
tsu(DB-RD)
0ns(min.)
60ns(min.)
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
30ns(max.)
0ns(min.)
CSi
tcyc
th(BCLK-AD)
td(BCLK-AD)
0ns(min.)
30ns(max.)
ADi
BHE
td(BCLK-ALE)
25ns(max.)
th(BCLK-ALE)
th(WR-AD)
-4ns(min.)
(0.5 × t cyc-15)ns(min.)
ALE
th(BCLK-WR)
td(BCLK-WR)
0ns(min.)
30ns(max.)
WR, WRL,
WRH
td(BCLK-DB)
40ns(max.)
Hi-Z
DBi
td(DB-WR)
{(n-0.5) × tcyc -40}ns(min.)
tcyc =
(0.5 × t cyc-25)ns(min.)
1
f(BCLK)
Measuring conditions
y VCC1 = VCC2 = 3V
y Input timing voltage: VIL = 0.6 V, VIH = 2.4 V
y Output timing voltage: VOL = 1.5 V, VOH = 1.5 V
Figure 5.31
th(WR-DB)
n: 1 (when 1 wait)
2 (when 2 waits)
3 (when 3 waits)
Timing Diagram
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 101 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 =
Switching Characteristics
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
3V
5.3.4.3
In 2 or 3 Waits Setting, and When Accessing External Area and Using
Multiplexed Bus
Table 5.61
Memory Expansion Mode and Microprocessor Mode (in 2 or 3 Waits Setting, and When
Accessing External Area and Using Multiplexed Bus) (5)
Symbol
Measuring
Condition
Parameter
Standard
Min.
Max.
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (in relation to BCLK)
0
ns
th(RD-AD)
Address output hold time (in relation to RD)
(Note 1)
ns
th(WR-AD)
Address output hold time (in relation to WR)
(Note 6)
td(BCLK-CS)
Chip select output delay time
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
0
ns
th(RD-CS)
Chip select output hold time (in relation to RD)
(Note 1)
ns
th(WR-CS)
Chip select output hold time (in relation to WR)
(Note 1)
ns
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(BCLK-DB)
Data output delay time (in relation to BCLK)
50
ns
50
ns
40
ns
50
ns
ns
0
td(DB-WR)
Data output delay time (in relation to WR)
(Note 2)
th(WR-DB)
Data output hold time (in relation to WR)
(Note 7)
td(BCLK-ALE)
ALE signal output delay time (in relation to BCLK)
ns
40
0
See
Figure 5.29
ns
ns
ns
ns
25
ns
th(BCLK-ALE)
ALE signal output hold time (in relation to BCLK)
−4
ns
td(AD-ALE)
ALE signal output delay time (in relation to Address)
(Note 3)
ns
th(AD-ALE)
ALE signal output hold time (in relation to Address)
(Note 4)
ns
td(AD-RD)
RD signal output delay from the end of address
0
ns
td(AD-WR)
WR signal output delay from the end of address
0
ns
tdz(RD-AD)
Address output floating start time
8
ns
Notes:
9
0.5 × 10
f ( BCLK )
1.
Calculated according to the BCLK frequency as follows: ---------------------- – 10 [ ns ]
2.
Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) × 10 - – 50 [ ns ]
----------------------------------f ( BCLK )
n is 2 for 2 waits setting, 3 for 3 waits setting.
9
0.5 × 10
f ( BCLK )
3.
Calculated according to the BCLK frequency as follows: ---------------------- – 40 [ ns ]
4.
Calculated according to the BCLK frequency as follows: ---------------------- – 15 [ ns ]
5.
When using multiplexed bus, set f(BCLK) 12.5 MHz or less.
6.
Calculated according to the BCLK frequency as follows: ---------------------- – 15 [ ns ]
7.
Calculated according to the BCLK frequency as follows: ---------------------- – 25 [ ns ]
9
0.5 × 10
f ( BCLK )
9
0.5 × 10
f ( BCLK )
9
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
0.5 × 10
f ( BCLK )
Page 102 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 = 3V
Memory Expansion Mode and Microprocessor Mode
(in 2 or 3 waits setting, and when accessing external area and using multiplexed bus )
Read timing
BCLK
th(BCLK-CS)
td(BCLK-CS)
th(RD-CS)
tcyc
50ns(max.)
0ns(min.)
(0.5 × t cyc-10)ns(min.)
CSi
td(AD-ALE)
(0.5 × t cyc-40ns(min.)
ADi
/DBi
th(ALE-AD)
(0.5 × t cyc-15ns(min.)
Address
Address
Data input
tdz(RD-AD)
8ns(max.)
tsu(DB-RD)
tac3(RD-DB)
{(n-0.5) × tcyc -60}ns(max.) 60ns(min.)
th(RD-DB)
0ns(min.)
td(AD-RD)
td(BCLK-AD)
0ns(min.)
50ns(max.)
th(BCLK-AD)
0ns(min.)
ADi
BHE
td(BCLK-ALE)
25ns(max.)
th(BCLK-ALE)
th(RD-AD)
(0.5 × t cyc-10)ns(min.)
-4ns(min.)
ALE
td(BCLK-RD)
40ns(max.)
th(BCLK-RD)
0ns(min.)
RD
Write timing
BCLK
td(BCLK-CS)
tcyc
50ns(max.)
th(WR-CS)
(0.5 × t cyc-10)ns(min.)
th(BCLK-CS)
0ns(min.)
CSi
td(BCLK-DB)
50ns(max.)
ADi
/DBi
Address
Address
Data output
td(DB-WR)
td(AD-ALE)
(0.5 × t cyc-40ns(min.)
{(n-0.5) × tcyc -50}ns(min.)
th(WR-DB)
(0.5 × t cyc-25)ns(min.)
td(BCLK-AD)
th(BCLK-AD)
50ns(max.)
ADi
BHE
td(BCLK-ALE)
25ns(max.)
0ns(min.)
th(BCLK-ALE)
td(AD-WR)
-4ns(min.)
0ns(min.)
th(WR-AD)
(0.5 × t cyc-15)ns(min.)
ALE
th(BCLK-WR)
td(BCLK-WR)
40ns(max.)
0ns(min.)
WR, WRL,
WRH
WR, WRL,
tcyc =
1
f(BCLK)
Measuring conditions
y VCC1 = VCC2 = 3V
y Input timing voltage: VIL = 0.6 V, VIH = 2.4 V
y Output timing voltage: VOL = 1.5 V, VOH = 1.5 V
Figure 5.32
n: 2 (when 2 waits)
3 (when 3 waits)
Timing Diagram
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 103 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 =
Switching Characteristics
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.3.4.4
Table 5.62
3V
In Wait State Setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and When
Accessing External Area
Memory Expansion and Microprocessor Modes (in Wait State Setting 2φ + 3φ, 2φ + 4φ,
3φ + 4φ, and 4φ + 5φ, and When Accessing External Area)
Symbol
Standard
Measuring
Condition
Parameter
Min.
Max.
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (in relation to BCLK)
0
ns
th(RD-AD)
Address output hold time (in relation to RD)
0
ns
th(WR-AD)
Address output hold time (in relation to WR)
(Note 2)
ns
td(BCLK-CS)
Chip select output delay time
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
td(BCLK-ALE)
ALE signal output delay time
th(BCLK-ALE)
ALE signal output hold time
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(BCLK-DB)
Data output delay time (in relation to BCLK)
td(DB-WR)
Data output delay time (in relation to WR)
(Note 1)
ns
th(WR-DB)
Data output hold time (in relation to WR) (3)
(Note 4)
ns
30
ns
30
ns
0
ns
25
ns
-4
See
Figure 5.29
ns
30
ns
0
ns
30
ns
0
ns
40
ns
Notes:
1. Calculated according to the BCLK frequency as follows:
9
(----------------------------------n – 0.5 ) × 10 - – 40 [ ns ]
f ( BCLK )
2.
n is 3 for 2φ + 3φ, 4 for 2φ + 4φ, 4 for 3φ + 4φ, and 5 for 4φ + 5φ.
Calculated according to the BCLK frequency as follows:
9
0.5
× 10 - – 15 [ ns ]
--------------------f ( BCLK )
3.
This standard value shows the timing when the output is
off, and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pullup (pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR × ln(1 − VOL/VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ,
hold time of output low level is
t = −30 pF × 1 kΩ × In(1 − 0.2VCC2/VCC2)
= 6.7 ns.
R
DBi
C
9
4.
× 10 - – 25 [ ns ]
Calculated according to the BCLK frequency as follows: 0.5
--------------------f ( BCLK )
Hold time is equal to or less than 0 ns when the BCLK frequency exceeds 20 MHz.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 104 of 109
M16C/65C Group
5. Electrical Characteristics
Memory Expansion Mode, Microprocessor Mode
(in wait state setting 2 φ + 3 φ, 2 φ + 4 φ, 3φ + 4 φ, and 4 φ + 5 φ, and
when accessing external area)
Read timing
VCC1 = VCC2 = 3V
tcyc
BCLK
th(BCLK-CS)
0ns(min.)
td(BCLK-CS)
30ns(max.)
CSi
td(BCLK-AD)
30ns(max.)
th(BCLK-AD)
0ns(min.)
ADi
BHE
td(BCLK-ALE)
25ns(max.)
th(RD-AD)
0ns(min.)
th(BCLK-ALE)
-4ns(min.)
ALE
td(BCLK-RD)
30ns(max.)
th(BCLK-RD)
0ns(min.)
RD
tac4(RD-DB)
(n × tcyc-60)ns(max.)
Hi-Z
DBi
tsu(DB-RD)
60ns(min.)
Write timing
th(RD-DB)
0ns(min.)
tcyc
BCLK
td(BCLK-CS)
30ns(max.)
th(BCLK-CS)
0ns(min.)
td(BCLK-AD)
30ns(max.)
th(BCLK-AD)
0ns(min.)
CSi
ADi
BHE
td(BCLK-ALE)
25ns(max.)
th(WR-AD)
(0.5 × tcyc -15)ns(min.)
th(BCLK-ALE)
-4ns(min.)
ALE
th(BCLK-WR)
0ns(min.)
td(BCLK-WR)
30ns(max.)
WR, WRL
WRH
td(BCLK-DB)
40ns(max.)
Hi-Z
DBi
tcyc =
1
th(WR-DB)
(0.5 × tcyc -25)ns(min.)
f(BCLK)
Measuring conditions
y VCC1 = VCC2 = 3V
y Input timing voltage: VIL = 0.6 V, VIH = 2.4 V
y Output timing voltage: VOL = 1.5 V, VOH = 1.5 V
Figure 5.33
td(DB-WR)
{(n-0.5) × tcyc -40}ns(min.)
n: 3 (when 2 φ + 3 φ)
4 (when 2 φ + 4 φ or 3 φ + 4 φ)
5 (when 4 φ + 5 φ)
Timing Diagram
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 105 of 109
M16C/65C Group
5. Electrical Characteristics
VCC1 = VCC2 =
Switching Characteristics
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
3V
5.3.4.5
In Wait State Setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and Inserting 1
to 3 Recovery Cycles and Accessing External Area
Table 5.63
Memory Expansion Mode and Microprocessor Mode (in Wait State Setting 2φ + 3φ, 2φ +
4φ, 3φ + 4φ, and 4φ + 5φ, and Inserting 1 to 3 Recovery Cycles and Accessing External
Area)
Symbol
Measuring
Condition
Parameter
Standard
Min.
Address output delay time
td(BCLK-AD)
Max.
30
Unit
ns
th(BCLK-AD)
Address output hold time (in relation to BCLK)
0
ns
th(RD-AD)
Address output hold time (in relation to RD)
(Note 4)
ns
(Note 2)
ns
th(WR-AD)
Address output hold time (in relation to WR)
td(BCLK-CS)
Chip select output delay time
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
td(BCLK-ALE)
ALE signal output delay time
th(BCLK-ALE)
ALE signal output hold time
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
30
See
Figure 5.29
ns
-4
ns
30
ns
0
ns
30
th(BCLK-WR)
WR signal output hold time
Data output delay time (in relation to BCLK)
td(DB-WR)
Data output delay time (in relation to WR)
Data output hold time (in relation to WR)
ns
25
td(BCLK-DB)
th(WR-DB)
ns
0
ns
0
(3)
ns
40
ns
(Note 1)
ns
(Note 5)
ns
Notes:
1.
Calculated according to the BCLK frequency as follows:
9
n × 10 - – 40 [ ns ]
----------------f ( BCLK )
2.
Calculated according to the BCLK frequency as follows:
9
m
× 10 - – 15 [ ns ]
-----------------f ( BCLK )
3.
4.
m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and
3 when 3 recovery cycles are inserted.
This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR × ln(1 − VOL/VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ, hold time
of output low level is
t = −30 pF × 1 kΩ × In(1 − 0.2VCC2/VCC2)
= 6.7 ns.
Calculated according to the BCLK frequency as follows:
9
m
× 10 - + 0 [ ns ]
-----------------f ( BCLK )
5.
n is 3 for 2φ + 3φ, 4 for 2φ + 4φ, 4 for 3φ + 4φ, and 5 for 4φ + 5φ.
R
DBi
C
m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and
3 when 3 recovery cycles are inserted.
Calculated according to the BCLK frequency as follows:
9
m
× 10 - – 25 [ ns ]
-----------------f ( BCLK )
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
m is 1 when 1 recovery cycle is inserted, 2 when 2 recovery cycles are inserted, and
3 when 3 recovery cycles are inserted.
Page 106 of 109
M16C/65C Group
5. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode
(in wait state setting 2 φ + 3 φ, 2 φ + 4 φ, 3φ + 4 φ, and 4 φ + 5 φ, and
when inserting 1 to 3 recovery cycles inserted and accessing external area)
Read timing
VCC1 = VCC2 = 3V
tcyc
BCLK
th(BCLK-CS)
0ns(min.)
td(BCLK-CS)
30ns(max.)
CSi
th(BCLK-AD)
0ns(min.)
td(BCLK-AD)
30ns(max.)
ADi
BHE
td(BCLK-ALE)
25ns(max.)
th(RD-AD)
(m × tcyc+0)ns(min.)
th(BCLK-ALE)
-4ns(min.)
ALE
th(BCLK-RD)
0ns(min.)
td(BCLK-RD)
30ns(max.)
RD
tac4(RD-DB)
(n × tcyc -60)ns(max.)
Hi-Z
DBi
tsu(DB-RD)
60ns(min.)
th(RD-DB)
0ns(min.)
Write timing
tcyc
BCLK
td(BCLK-CS)
30ns(max.)
th(BCLK-CS)
0ns(min.)
td(BCLK-AD)
30ns(max.)
th(BCLK-AD)
0ns(min.)
CSi
ADi
BHE
td(BCLK-ALE)
25ns(max.)
th(WR-AD)
(m × tcyc -15)ns(min.)
th(BCLK-ALE)
-4ns(min.)
ALE
th(BCLK-WR)
0ns(min.)
td(BCLK-WR)
30ns(max.)
WR, WRL
WRH
Hi-Z
DBi
td(BCLK-DB)
40ns(max.)
1
tcyc =
f(BCLK)
Measuring conditions
y VCC1 = VCC2 = 3V
y Input timing voltage: VIL = 0.6 V, VIH = 2.4 V
y Output timing voltage: VOL = 1.5 V, VOH = 1.5 V
Figure 5.34
td(DB-WR)
(n × tcyc -40)ns(min.)
th(WR-DB)
(m × tcyc -25)ns(min.)
n: 3 (when 2 φ + 3 φ)
4 (when 2 φ + 4 φ or 3 φ + 4 φ)
5 (when 4 φ + 5 φ)
m: 1 (when 1 recovery cycle inserted )
2 (when 2 recovery cycles inserted)
3 (when 3 recovery cycles inserted)
Timing Diagram
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 107 of 109
M16C/65C Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
The information on the latest package dimensions or packaging may be obtained from “Packages“ on the
Renesas Electronics website.
JEITA Package Code
P-LQFP128-14x20-0.50
RENESAS Code
PLQP0128KB-A
Previous Code
128P6Q-A
MASS[Typ.]
0.9g
HD
*1
D
102
65
103
64
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
bp
E
c
*2
HE
c1
b1
Reference
Symbol
Terminal cross section
ZE
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
128
39
38
A
Index mark
c
ZD
A2
1
A1
F
L
*3
y
e
JEITA Package Code
P-QFP100-14x20-0.65
RENESAS Code
PRQP0100JD-B
L1
bp
x
e
x
y
ZD
ZE
L
L1
DetailF
Previous Code
100P6F-A
Dimension in Millimeters
Min Nom Max
19.9 20.0 20.1
13.9 14.0 14.1
1.4
21.8 22.0 22.2
15.8 16.0 16.2
1.7
0.05 0.125 0.2
0.17 0.22 0.27
0.20
0.09 0.145 0.20
0.125
0°
8°
0.5
0.10
0.10
0.75
0.75
0.35 0.5 0.65
1.0
MASS[Typ.]
1.8g
HD
*1
D
80
51
81
50
HE
*2
E
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
ZE
Reference Dimension in Millimeters
Symbol
100
31
30
c
F
A2
Index mark
ZD
A1
A
1
L
*3
e
y
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
bp
x
Detail F
D
E
A2
HD
HE
A
A1
bp
c
e
x
y
ZD
ZE
L
Min Nom Max
19.8 20.0 20.2
13.8 14.0 14.2
2.8
22.5 22.8 23.1
16.5 16.8 17.1
3.05
0.1 0.2
0
0.25 0.3 0.4
0.13 0.15 0.2
0°
10°
0.65
0.13
0.10
0.575
0.825
0.4 0.6 0.8
Page 108 of 109
M16C/65C Group
Appendix 1. Package Dimensions
JEITA Package Code
P-LQFP100-14x14-0.50
RENESAS Code
PLQP0100KB-A
Previous Code
100P6Q-A / FP-100U / FP-100UV
MASS[Typ.]
0.6g
HD
*1
D
51
75
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
50
76
bp
c1
Reference Dimension in Millimeters
Symbol
c
E
*2
HE
b1
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
100
26
1
ZE
Terminal cross section
25
Index mark
ZD
y
e
*3
bp
A1
c
A
A2
F
L
x
L1
Detail F
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
e
x
y
ZD
ZE
L
L1
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.08
1.0
1.0
0.35 0.5 0.65
1.0
Page 109 of 109
REVISION HISTORY
Rev.
Date
0.10
Oct 29, 2010
1.00
Feb 07, 2011
M16C/65C Group Datasheet
Description
Page
-
Overall
Summary
First Edition issued.
Changed terminologies are as follows:
• “oscillation/oscillator circuit” to “oscillator”
• “oscillator” to “a crystal/ceramic resonator”
• “oscillator manufacturer” to “manufacturer of crystal/ceramic resonator”
• “on-chip oscillator oscillation circuit” to “on-chip oscillator”
Overview
3, 5
6
Table 1.2 Specifications for the 128-Pin Package (2/2), Table 1.4 Specifications for the 100-Pin
Package (2/2): Changed the Description column of the Current Consumption row.
Table 1.5 Product List (N-Version), Table 1.6 Product List (D-Version): Changed the development
status.
Electrical Characteristics
VCC = 5 V
64, 65
Table 5.20 Electrical Characteristics (3), Table 5.21 Electrical Characteristics (4):
Added conditions with XIN is 6MHz to the Wait mode measuring condition.
In Switching Characteristics (Memory Expansion Mode and Microprocessor Mode),
74, 77, 79, Table 5.36, Table 5.37, Table 5.38, Table 5.39, Table 5.40:
• Deleted the th(BCLK-DB) row.
81, 83
• Changed the formula of th(WR-DB) for minimum standard.
Figure 5.15, Figure 5.16, Figure 5.17, Figure 5.18, Figure 5.19:
76, 78, 80,
Deleted the description of th(BCLK-DB), and changed the formula of th(WR-DB) in the Write
82, 84
timing.
VCC = 3 V
86, 87
Table 5.42 Electrical Characteristics (2), Table 5.43 Electrical Characteristics (3) (1/2):
Added conditions with XIN is 6MHz to the Wait mode measuring condition.
In Switching Characteristics (Memory Expansion Mode and Microprocessor Mode),
95, 97, Table 5.58, Table 5.59, Table 5.60, Table 5.61, Table 5.62:
100, 102, • Deleted the th(BCLK-DB) row.
• Changed the formula of th(WR-AD) for minimum standard.
104
• Changed the formula of th(WR-DB) for minimum standard.
99, 101, Figure 5.30, Figure 5.31, Figure 5.32, Figure 5.33, Figure 5.34:
103, 105, • Deleted the description of th(BCLK-DB), and changed the formulas of th(WR-AD) and
th(WR-DB) in the Write timing.
107
1.10
Jul 31, 2012 Overview
6
Table 1.5 Product List (N-Version), Table 1.6 Product List (D-Version):
Changed development statuses.
Electrical Characteristics
Vcc = 5 V
64, 65
Table 5.20 Electrical Characteristics (3) and Table 5.21 Electrical Characteristics (4): Changed the
Measuring Condition column of 40 MHz on-chip oscillator for the 40 MHz on-chip oscillator mode in
the ICC.
Vcc = 3 V
86, 87
Table 5.42 Electrical Characteristics (2) and Table 5.43 Electrical Characteristics (3) (1/2):
Changed the Measuring Condition column of 40 MHz on-chip oscillator for the 40 MHz on-chip
oscillator mode in the ICC.
All trademarks and registered trademarks are the property of their respective owners.
A-1
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
2.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
3.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
4.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or
5.
Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on
third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.
the product's quality grade, as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; and industrial robots etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical
implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it
in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses
incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
6.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or systems manufactured by you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
9.
Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or
regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the
development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the
contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics
products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-585-100, Fax: +44-1628-585-900
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632
Tel: +65-6213-0200, Fax: +65-6278-8001
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2012 Renesas Electronics Corporation. All rights reserved.
Colophon 2.0
工商网监
湘ICP备2023018690号
