R5F3650KNFB

REJ09B0484-0030 16 M16C/65 Group HARDWARE MANUAL RENESAS MCU M16C FAMILY / M16C/60 PRELIMINARY M16C/65 Group Hardware Manual Note: All information contained in this document is provided on an “as is” basis. The information on products or specifications is subject to change without notice. Please verify the latest information available on our website prior to use. Rev.0.30 Revision Date: Sep 09, 2008 www.renesas.com Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.  The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.  The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.  The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.  When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems.  The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products. HOW TO USE THIS MANUAL 1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual. The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral functions, and electrical characteristics; and usage notes. Particular attention should be paid to the precautionary notes when using the manual. These notes occur within the body of the text, at the end of each section, and in the Usage Notes section. The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer to the text of the manual for details. The following documents apply to the M16C/64 Group. Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site. Description Document Title Document No. Hardware overview and electrical characteristics M16C/65 Group Datasheet M16C/65 Group This hardware Hardware manual Hardware specifications (pin assignments, Hardware Manual manual memory maps, peripheral function specifications, electrical characteristics, timing charts) and operation description Note: Refer to the application notes for details on using peripheral functions. Software manual Descriptions of CPU instruction set M16C/60, M16C/ REJ09B0137 20, M16C/Tiny Series Software Manual Available from Renesas Application note Information on using peripheral functions and Technology Web site. application examples Sample programs Information on writing programs in assembly language and C Renesas Product specifications, updates on documents, technical update etc. Document Type Datasheet 2. Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word “register,” “bit,” or “pin” to distinguish the three categories. Examples the PM03 bit in the PM0 register P3_5 pin, VCC pin (2) Notation of Numbers The indication “b” is appended to numeric values given in binary format. However, nothing is appended to the values of single bits. The indication “h” is appended to numeric values given in hexadecimal format. Nothing is appended to numeric values given in decimal format. Examples Binary: 11b Hexadecimal: EFA0h Decimal: 1234 3. Register Notation The symbols and terms used in register diagrams are described below. XXX Register b7 b6 b5 b4 b3 b2 b1 b0 *1 Symbol XXX Address XXX After Reset 00h 0 Bit Symbol XXX0 Bit Name XXX bits b1 b0 Function 1 0: XXX 0 1: XXX 1 0: Do not set. 1 1: XXX RW RW *2 XXX1 RW (b2) Nothing is assigned. If necessary, set to 0. When read, the content is undefined. *3 RW (b3) Reserved bits Set to 0. *4 XXX4 XXX bits Function varies according to the operating mode. RW XXX5 WO XXX6 0: XXX 1: XXX RW XXX7 XXX bit RO *1 Blank: Set to 0 or 1 according to the application. 0: Set to 0. 1: Set to 1. X: Nothing is assigned. *2 RW: Read and write. RO: Read only. WO: Write only. −: Nothing is assigned. *3 • Reserved bit Reserved bit. Set to specified value. *4 • Nothing is assigned Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0. • Do not set to a value Operation is not guaranteed when a value is set. • Function varies according to the operating mode. The function of the bit varies with the peripheral function mode. Refer to the register diagram for information on the individual modes. 4. List of Abbreviations and Acronyms Full Form Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access Direct Memory Access Controller Global System for Mobile Communications High Impedance Inter Equipment bus Input/Output Infrared Data Association Least Significant Bit Most Significant Bit Non-Connection Phase Locked Loop Pulse Width Modulation Subscriber Identity Module Universal Asynchronous Receiver/Transmitter Voltage Controlled Oscillator Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SIM UART VCO All trademarks and registered trademarks are the property of their respective owners. IEBus is a registered trademark of NEC Electronics Corporation. HDMI and High-Definition Multimedia Interface are registered trademarks of HDMI Licensing, LLC. SFR Page Reference B-1 1. Overview .................................................................................................. 1 1.1 1.2 1.3 1.4 1.5 1.6 Features .............................................................................................................. 1 Applications .................................................................................................. 1 Product List ........................................................................................................ 8 Block Diagram ................................................................................................... 10 Pin Assignments................................................................................................ 13 Pin Functions..................................................................................................... 24 Specifications ...................................................................................................... 2 1.1.1 2. Central Processing Unit (CPU)............................................................... 32 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Data Registers (R0, R1, R2, and R3)................................................................ 32 Address Registers (A0 and A1)......................................................................... 33 Frame Base Register (FB) ................................................................................ 33 Interrupt Table Register (INTB) ......................................................................... 33 Program Counter (PC) ...................................................................................... 33 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) ............................. 33 Static Base Register (SB).................................................................................. 33 Flag Register (FLG)........................................................................................... 33 Carry Flag (C Flag)..................................................................................... 33 Debug Flag (D Flag) ................................................................................... 33 Zero Flag (Z Flag)....................................................................................... 33 Sign Flag (S Flag)....................................................................................... 33 Register Bank Select Flag (B Flag) ............................................................ 33 Overflow Flag (O Flag) ............................................................................... 33 Interrupt Enable Flag (I Flag)...................................................................... 33 Stack Pointer Select Flag (U Flag) ............................................................. 34 Processor Interrupt Priority Level (IPL) ...................................................... 34 Reserved Space ......................................................................................... 34 2.8.1 2.8.2 2.8.3 2.8.4 2.8.5 2.8.6 2.8.7 2.8.8 2.8.9 2.8.10 3. Address Space ....................................................................................... 35 3.1 3.2 3.3 Address Space .................................................................................................. 35 Memory Map ..................................................................................................... 36 Accessible Area in Each Mode.......................................................................... 37 A-1 4. Special Function Registers (SFRs) ........................................................ 38 4.1 4.2 SFRs ................................................................................................................. 38 Notes on SFRs .................................................................................................. 54 Register Settings ........................................................................................ 54 4.2.1 5. Protection ............................................................................................... 55 5.1 5.2 5.3 Introduction........................................................................................................ 55 Register ............................................................................................................. 55 Protect Register (PRCR) ............................................................................ 55 Notes on Protection........................................................................................... 57 5.2.1 6. Resets .................................................................................................... 58 6.1 6.2 Introduction........................................................................................................ 58 Registers ........................................................................................................... 59 Processor Mode Register 0 (PM0) ............................................................. 60 Reset Source Determine Register (RSTFR) .............................................. 61 Optional Function Select Address 1 (OFS1) .............................................. 63 Status After Reset....................................................................................... 65 Hardware Reset.......................................................................................... 68 Power-On Reset Function .......................................................................... 69 Voltage Monitor 0 Reset ............................................................................. 70 Voltage Monitor 1 Reset ............................................................................. 70 Voltage Monitor 2 Reset ............................................................................. 71 Oscillation Stop Detection Reset ................................................................ 71 Watchdog Timer Reset ............................................................................... 72 Software Reset ........................................................................................... 72 Cold Start-Up/Warm Start-Up Discrimination.............................................. 73 Power Supply Rising Gradient.................................................................... 74 Power-On Reset ......................................................................................... 74 OSDR Bit (Oscillation Stop Detection Reset Detection Flag) ..................... 74 6.2.1 6.2.2 6.3 6.4 6.3.1 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.4.8 6.4.9 6.4.10 6.5 6.5.1 6.5.2 6.5.3 Optional Function Select Area........................................................................... 63 Operations......................................................................................................... 65 Notes on Resets................................................................................................ 74 7. Voltage Detector..................................................................................... 75 7.1 Introduction........................................................................................................ 75 A-2 7.2 Registers ........................................................................................................... 77 Voltage Detection 2 Circuit Flag Register (VCR1)...................................... 78 Voltage Detection Circuit Operation Enable Register (VCR2).................... 79 Voltage Monitor Function Select Register (VWCE) .................................... 80 Voltage Detection 1 Level Select Register (VD1LS)................................... 80 Voltage Monitor 0 Circuit Control Register (VW0C).................................... 82 Voltage Monitor 1 Circuit Control Register (VW1C).................................... 83 Voltage Monitor 2 Circuit Control Register (VW2C).................................... 85 Optional Function Select Address (OFS1) ................................................. 87 Digital Filter................................................................................................. 88 Voltage Detection 0 Circuit ......................................................................... 89 Voltage Detection 1 Circuit ......................................................................... 91 Voltage Detection 2 Circuit ......................................................................... 94 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.3 7.4 7.3.1 7.4.1 7.4.2 7.4.3 7.4.4 7.5 Optional Function Select Area........................................................................... 87 Operations......................................................................................................... 88 Interrupts ........................................................................................................... 97 8. Clock Generator ..................................................................................... 98 8.1 8.2 Introduction........................................................................................................ 98 Registers ......................................................................................................... 101 Processor Mode Register 0 (PM0) ........................................................... 102 System Clock Control Register 0 (CM0)................................................... 103 System Clock Control Register 1 (CM1)................................................... 105 Oscillation Stop Detection Register (CM2) ............................................... 107 Peripheral Clock Select Register (PCLKR) .............................................. 109 PLL Control Register 0 (PLC0)................................................................. 110 Processor Mode Register 2 (PM2) ............................................................111 40 MHz On-Chip Oscillator Control Register 0 (FRA0) ............................ 112 Main Clock................................................................................................ 113 PLL Clock ................................................................................................. 115 fOCO40M ................................................................................................. 116 fOCO-F ..................................................................................................... 116 125 kHz On-Chip Oscillator Clock (fOCO-S)............................................ 117 Sub Clock (fC) .......................................................................................... 118 A-3 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 Clocks Generated by Clock Generators.......................................................... 113 8.4 CPU Clock and Peripheral Function Clocks.................................................... 119 CPU Clock and BCLK............................................................................... 119 Peripheral Function Clocks (f1, fOCO40M, fOCO-F, fOCO-S, fC32, fC).. 119 8.4.1 8.4.2 8.5 8.6 8.7 Clock Output Function..................................................................................... 121 System Clock Protection Function .................................................................. 121 Oscillation Stop/Re-Oscillation Detect Function .............................................. 122 Operation When CM27 Bit is 0 (Oscillation Stop Detection Reset) .......... 122 Operation When CM27 Bit is 1 (Oscillation Stop, Re-Oscillation Detect Interrupt) ................................................................................................... 123 Using the Oscillation Stop, Re-Oscillation Detect Function ...................... 124 Oscillation Circuit Using an Oscillator....................................................... 125 Noise Countermeasure............................................................................. 126 CPU ClockW............................................................................................. 127 Oscillation Stop, Re-Oscillation Detect Function ...................................... 127 PLL Frequency Synthesizer ..................................................................... 128 8.7.1 8.7.2 8.7.3 8.8 8.8.1 8.8.2 8.8.3 8.8.4 8.8.5 Notes on Clock Generator............................................................................... 125 9. Power Control....................................................................................... 129 9.1 9.2 Introduction...................................................................................................... 129 Registers ......................................................................................................... 129 Flash Memory Control Register 0 (FMR0)................................................ 130 Flash Memory Control Register 2 (FMR2)................................................ 131 Normal Operating Mode ........................................................................... 132 Mode Transitions ...................................................................................... 136 Wait Mode ................................................................................................ 139 Stop Mode ................................................................................................ 143 Stopping Flash Memory............................................................................ 146 Reading Flash Memory ............................................................................ 147 Ports ......................................................................................................... 149 A/D Converter........................................................................................... 149 D/A Converter........................................................................................... 149 Stopping Peripheral Functions.................................................................. 149 Switching the Oscillation-Driving Capacity ............................................... 149 A-4 9.2.1 9.2.2 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.4 9.4.1 9.4.2 9.5 9.5.1 9.5.2 9.5.3 9.5.4 9.5.5 Clock ............................................................................................................... 132 Power Control in Flash Memory ...................................................................... 146 Reducing Power Consumption........................................................................ 149 9.6 Notes on Power Control .................................................................................. 150 CPU Clock ................................................................................................ 150 Wait Mode ................................................................................................ 150 Stop Mode ................................................................................................ 151 Low Current Consumption Read Mode .................................................... 151 9.6.1 9.6.2 9.6.3 9.6.4 10. Processor Mode ................................................................................... 152 10.1 10.2 Introduction...................................................................................................... 152 Registers ......................................................................................................... 153 Processor Mode Register 0 (PM0) ........................................................... 153 Processor Mode Register 1 (PM1) ........................................................... 154 Program 2 Area Control Register (PRG2C) ............................................. 156 Processor Mode Settings ......................................................................... 157 10.2.1 10.2.2 10.2.3 10.3 10.3.1 Operations....................................................................................................... 157 11. Bus ....................................................................................................... 159 11.1 11.2 Introduction...................................................................................................... 159 Registers ......................................................................................................... 160 Chip Select Control Register (CSR) ......................................................... 161 Chip Select Expansion Control Register (CSE)........................................ 162 External Area Wait Control Expansion Register (EWC) ........................... 163 External Area Recovery Cycle Control Register (EWR)........................... 164 Common Specifications of Internal Bus and External Bus ....................... 165 Internal Bus .............................................................................................. 166 External Bus ............................................................................................. 167 External Bus Mode ................................................................................... 167 External Bus Control................................................................................. 168 Reading Data Flash.................................................................................. 181 External Bus ............................................................................................. 181 External Access Soon After Writing to the SFRs...................................... 181 11.2.1 11.2.2 11.2.3 11.2.4 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.4 11.4.1 11.4.2 11.4.3 Operations....................................................................................................... 165 Notes on Bus................................................................................................... 181 12. Memory Space Expansion Function ..................................................... 182 12.1 12.2 Introduction...................................................................................................... 182 Registers ......................................................................................................... 182 A-5 12.2.1 12.3 12.3.1 12.3.2 Data Bank Register (DBR) ....................................................................... 183 1-Mbyte Mode........................................................................................... 184 4-Mbyte Mode........................................................................................... 186 Operations....................................................................................................... 184 13. Programmable I/O Ports....................................................................... 192 13.1 13.2 13.3 Introduction...................................................................................................... 192 I/O Ports and Pins ........................................................................................... 194 Registers ......................................................................................................... 204 Pull-Up Control Register 0 (PUR0)........................................................... 205 Pull-Up Control Register 1 (PUR1)........................................................... 206 Pull-Up Control Register 2 (PUR2)........................................................... 207 Pull-Up Control Register 3 (PUR3)........................................................... 208 Port Control Register (PCR) ..................................................................... 209 Port Pi Registers (Pi) (i = 0 to 14) ............................................... 210 ............................. 212 Port Pi Direction Registers (PDi) (i = 0 to 14) 13.3.1 13.3.2 13.3.3 13.3.4 13.3.5 13.3.6 13.3.7 13.3.8 13.4 13.4.1 13.4.2 13.4.3 13.4.4 13.5 13.6 NMI/SD Digital Filter Register (NMIDF).................................................... 213 Peripheral Function I/O and Port Direction Bits........................................ 214 Priority Level of Peripheral Function I/O................................................... 214 NMI/SD Digital Filter ................................................................................. 215 CNVSS ..................................................................................................... 215 Peripheral Function I/O ................................................................................... 214 Unassigned Pin Handling ................................................................................ 216 Notes on Programmable I/O Ports .................................................................. 218 Influence of the SD Input .......................................................................... 218 Influence of SI/O3 and SI/O4.................................................................... 218 100-Pin Package ...................................................................................... 218 80-Pin Package ........................................................................................ 218 13.6.1 13.6.2 13.6.3 13.6.4 14. Interrupts .............................................................................................. 219 14.1 14.2 Introduction...................................................................................................... 219 Registers ......................................................................................................... 220 Processor Mode Register 2 (PM2) ........................................................... 222 14.2.1 A-6 14.2.2 Interrupt Control Register 1 (TB5IC, TB4IC/U1BCNIC, TB3IC/U0BCNIC, BCNIC, DM0IC to DM3IC, KUPIC, ADIC, S0TIC to S2TIC, S0RIC to S2RIC, TA0IC to TA4IC, TB0IC to TB2IC, U5BCNIC/CEC1IC, S5TIC/CEC2IC, S5RIC to S7RIC, U6BCNIC/ RTCTIC, S6TIC/RTCCIC, U7BCNIC/PMC0IC, S7TIC/PMC1IC, IICIC, SCLDAIC)................................................................................................. 223 Interrupt Control Register 2 (INT7IC, INT6IC, INT3IC, S4IC/INT5IC, S3IC/INT4IC, INT0IC to INT2IC) .......................... 224 Interrupt Source Select Register 3 (IFSR3A) ........................................... 225 Interrupt Source Select Register 2 (IFSR2A) ........................................... 226 Interrupt Source Select Register (IFSR)................................................... 227 Address Match Interrupt Enable Register (AIER)..................................... 228 Address Match Interrupt Enable Register 2 (AIER2)................................ 228 Address Match Interrupt Register i (RMADi) (i = 0 to 3) ........................ 229 14.2.3 14.2.4 14.2.5 14.2.6 14.2.7 14.2.8 14.2.9 14.2.10 Port Control Register (PCR) ..................................................................... 230 14.2.11 NMI/SD Digital Filter Register (NMIDF).................................................... 231 14.3 14.4 Types of Interrupt ............................................................................................ 232 Software Interrupts .......................................................................................... 233 Undefined Instruction Interrupt ................................................................. 233 Overflow Interrupt ..................................................................................... 233 BRK Interrupt............................................................................................ 233 INT Instruction Interrupt............................................................................ 233 Special Interrupts...................................................................................... 234 Peripheral Function Interrupts .................................................................. 234 Fixed Vector Tables .................................................................................. 236 Relocatable Vector Tables ........................................................................ 236 Maskable Interrupt Control ....................................................................... 239 Interrupt Sequence ................................................................................... 240 Interrupt Response Time .......................................................................... 241 Variation of IPL When Interrupt Request is Accepted .............................. 241 Saving Registers ...................................................................................... 242 Returning from an Interrupt Routine ......................................................... 243 Interrupt Priority ........................................................................................ 243 Interrupt Priority Level Select Circuit ........................................................ 243 A-7 14.4.1 14.4.2 14.4.3 14.4.4 14.5 14.5.1 14.5.2 14.6 14.6.1 14.6.2 14.7 14.7.1 14.7.2 14.7.3 14.7.4 14.7.5 14.7.6 14.7.7 14.7.8 Hardware Interrupts......................................................................................... 234 Interrupts and Interrupt Vectors....................................................................... 235 Interrupt Control .............................................................................................. 239 14.7.9 14.8 14.9 Multiple Interrupts ..................................................................................... 246 INT Interrupt .................................................................................................... 247 NMI Interrupt ................................................................................................... 248 14.10 Key Input Interrupt........................................................................................... 248 14.11 Address Match Interrupt .................................................................................. 249 14.12 Non-Maskable Interrupt Source Discrimination............................................... 250 14.13 Notes on Interrupts.......................................................................................... 251 14.13.1 Reading Address 00000h ......................................................................... 251 14.13.2 SP Setting................................................................................................. 251 14.13.3 NMI Interrupt............................................................................................. 251 14.13.4 Changing an Interrupt Source .................................................................. 252 14.13.5 Rewriting the Interrupt Control Register ................................................... 253 14.13.6 INT Interrupt ............................................................................................. 254 15. Watchdog Timer ................................................................................... 255 15.1 15.2 Introduction...................................................................................................... 255 Registers ......................................................................................................... 256 Voltage Monitor 2 Circuit Control Register (VW2C).................................. 256 Count Source Protection Mode Register (CSPR)..................................... 257 Watchdog Timer Reset Register (WDTR) ................................................ 258 Watchdog Timer Start Register (WDTS)................................................... 258 Watchdog Timer Control Register (WDC) ................................................ 259 Optional Function Select Address 1 (OFS1) ............................................ 260 Count Source Protection Mode Disabled ................................................. 261 Count Source Protection Mode Enabled .................................................. 262 15.2.1 15.2.2 15.2.3 15.2.4 15.2.5 15.3 15.4 15.3.1 15.4.1 15.4.2 15.5 15.6 Optional Function Select Area......................................................................... 260 Operations....................................................................................................... 261 Interrupts ......................................................................................................... 263 Notes on Watchdog Timer............................................................................... 264 16. DMAC................................................................................................... 265 16.1 16.2 Introduction...................................................................................................... 265 Registers ......................................................................................................... 267 DMAi Source Pointer (SARi) (i = 0 to 3) ................................................ 268 DMAi Destination Pointer (DARi) (i = 0 to 3) ......................................... 268 DMAi Transfer Counter (TCRi) (i = 0 to 3) ............................................. 269 A-8 16.2.1 16.2.2 16.2.3 16.2.4 16.2.5 16.3 16.3.1 16.3.2 16.3.3 16.3.4 16.3.5 16.3.6 16.3.7 16.4 16.5 DMAi Control Register (DMiCON) (i = 0 to 3) ........................................ 270 DMAi Source Select Register (DMiSL) (i = 0 to 3) ................................ 271 Operations....................................................................................................... 274 DMA Enabled ........................................................................................... 274 DMA Request ........................................................................................... 274 Transfer Cycles ........................................................................................ 275 DMAC Transfer Cycles ............................................................................. 277 Single Transfer Mode ............................................................................... 278 Repeat Transfer Mode.............................................................................. 279 Channel Priority and DMA Transfer Timing .............................................. 279 Interrupts ......................................................................................................... 281 Notes on DMAC .............................................................................................. 282 Write to the DMAE Bit in the DMiCON Register (i = 0 to 3)...................... 282 Changing DMA Request Source .............................................................. 282 16.5.1 16.5.2 17. Timer A ................................................................................................. 283 17.1 17.2 Introduction...................................................................................................... 283 Registers ......................................................................................................... 287 Peripheral Clock Select Register (PCLKR) .............................................. 288 Clock Prescaler Reset Flag (CPSRF) ...................................................... 288 Timer AB Division Control Register 0 (TCKDIVC0) .................................. 289 Timer A Count Source Select Register i (TACSi) (i = 0 to 2) .................. 290 16-Bit Pulse Width Modulation Mode Function Select Register (PWMFS) .................................................................................................................. 291 Timer A Waveform Output Function Select Register (TAPOFS) .............. 292 Timer A Output Waveform Change Enable Register (TAOW) .................. 293 Timer Ai Register (TAi) (i = 0 to 4) ........................................................ 294 Timer Ai-1 Register (TAi1) (i = 1, 2, 4) .................................................... 295 17.2.1 17.2.2 17.2.3 17.2.4 17.2.5 17.2.6 17.2.7 17.2.8 17.2.9 17.2.10 Count Start Flag (TABSR) ........................................................................ 296 17.2.11 One-Shot Start Flag (ONSF) .................................................................... 297 17.2.12 Trigger Select Register (TRGSR) ............................................................. 298 17.2.13 Up/Down Flag (UDF) ................................................................................ 299 17.2.14 Timer Ai Mode Register (TAiMR) (i = 0 to 4) 17.3 17.3.1 17.3.2 ........................................ 300 Operations....................................................................................................... 301 Common Operations ................................................................................ 301 Timer Mode .............................................................................................. 303 A-9 17.3.3 17.3.4 17.3.5 17.3.6 17.3.7 17.4 17.5 Event Counter Mode (When Not Processing Two-Phase Pulse Signal) .. 307 Event Counter Mode (When Processing Two-Phase Pulse Signal) ......... 311 One-Shot Timer Mode .............................................................................. 316 Pulse Width Modulation (PWM) Mode...................................................... 320 Programmable Output Mode (Timers A1, A2, and A4)............................. 325 Interrupts ......................................................................................................... 329 Notes on Timer A ............................................................................................ 330 Timer A (Timer Mode)............................................................................... 330 Timer A (Event Counter Mode)................................................................. 331 Timer A (One-Shot Timer Mode) .............................................................. 332 Timer A (Pulse Width Modulation Mode) .................................................. 333 Timer A (Programmable Output Mode) .................................................... 334 17.5.1 17.5.2 17.5.3 17.5.4 17.5.5 18. Timer B ................................................................................................. 335 18.1 18.2 Introduction...................................................................................................... 335 Registers ......................................................................................................... 338 Peripheral Clock Select Register (PCLKR) .............................................. 339 Clock Prescaler Reset Flag (CPSRF) ...................................................... 339 Timer Bi Register (TBi) (i = 0 to 5) Timer Bi-1 Register (TBi1) (i = 0 to 5) ....................................................... 340 .................................................. 341 18.2.1 18.2.2 18.2.3 18.2.4 18.2.5 18.2.6 18.2.7 18.2.8 18.2.9 18.3 18.3.1 18.3.2 18.3.3 18.3.4 18.4 18.5 Pulse Period/Pulse Width Measurement Mode Function Select Register i (PPWFSi) (i = 1, 2) .................................................................................. 342 Timer B Count Source Select Register i (TBCSi) (i = 0 to 3) ................. 343 Timer AB Division Control Register 0 (TCKDIVC0) .................................. 344 Count Start Flag (TABSR) Timer B3/B4/B5 Count Start Flag (TBSR) ................................................ 345 Timer Bi Mode Register (TBiMR) (i = 0 to 5) ....................................... 346 Operations....................................................................................................... 347 Common Operations ................................................................................ 347 Timer Mode .............................................................................................. 349 Event Counter Mode................................................................................. 351 Pulse Period/Pulse Width Measurement Modes ...................................... 354 Interrupts ......................................................................................................... 359 Notes on Timer B ............................................................................................ 360 Timer B (Timer Mode)............................................................................... 360 Timer B (Event Counter Mode)................................................................. 361 A - 10 18.5.1 18.5.2 18.5.3 Timer B (Pulse Period/Pulse Width Measurement Modes) ...................... 362 19. Three-Phase Motor Control Timer Function ......................................... 363 19.1 19.2 Introduction...................................................................................................... 363 Registers ......................................................................................................... 367 Timer B2 Register (TB2)........................................................................... 368 Timer Ai, Ai-1 Register (TAi, TAi1) (i = 1, 2, 4) ..................................... 368 Three-Phase PWM Control Register 0 (INVC0) ....................................... 369 Three-Phase PWM Control Register 1 (INVC1) ....................................... 371 Three-Phase Output Buffer Register i (IDBi) (i = 0, 1) ............................. 373 Dead Time Timer (DTT)............................................................................ 373 Timer B2 Interrupt Generation Frequency Set Counter (ICTB2) .............. 374 Timer B2 Special Mode Register (TB2SC) ............................................... 375 Position-Data-Retain Function Control Register (PDRF) ......................... 376 19.2.1 19.2.2 19.2.3 19.2.4 19.2.5 19.2.6 19.2.7 19.2.8 19.2.9 19.2.10 Port Function Control Register (PFCR) .................................................... 377 19.2.11 Three-Phase Protect Control Register (TPRC) ........................................ 377 19.3 Operations....................................................................................................... 378 Common Operations in Multiple Modes ................................................... 378 Triangular Wave Modulation Three-Phase Mode 0 .................................. 384 Triangular Wave Modulation Three-Phase Mode 1 .................................. 389 Sawtooth Wave Modulation Mode ............................................................ 396 Timer B2 Interrupt..................................................................................... 401 Timers A1, A2 and A4 Interrupts .............................................................. 401 Timer A, Timer B....................................................................................... 402 Forced Cutoff Input................................................................................... 402 19.3.1 19.3.2 19.3.3 19.3.4 19.4 19.4.1 19.4.2 19.5 19.5.1 19.5.2 Interrupts ......................................................................................................... 401 Notes on Three-Phase Motor Control Timer Function..................................... 402 20. Real-Time Clock ................................................................................... 403 20.1 20.2 Introduction...................................................................................................... 403 Registers ......................................................................................................... 405 Real-Time Clock Second Data Register (RTCSEC)................................. 406 Real-Time Clock Minute Data Register (RTCMIN) ................................... 407 Real-Time Clock Hour Data Register (RTCHR) ....................................... 408 Real-Time Clock Day Data Register (RTCWK) ........................................ 409 Real-Time Clock Control Register 1 (RTCCR1) ...................................... 410 A - 11 20.2.1 20.2.2 20.2.3 20.2.4 20.2.5 20.2.6 20.2.7 20.2.8 20.2.9 20.3 Real-Time Clock Control Register 2 (RTCCR2) ...................................... 412 Real-Time Clock Count Source Select Register (RTCCSR) .................... 414 Real-Time Clock Second Compare Data Register (RTCCSEC)............... 415 Real-Time Clock Minute Compare Data Register (RTCCMIN)................. 416 20.2.10 Real-Time Clock Hour Compare Data Register (RTCCHR) ..................... 417 Operations....................................................................................................... 418 Basic Operation ........................................................................................ 418 Compare Mode......................................................................................... 421 20.3.1 20.3.2 20.4 20.5 Interrupts ......................................................................................................... 427 Notes on Real-Time Clock............................................................................... 428 Starting and Stopping Count..................................................................... 428 Register Setting (Time Data etc.) ............................................................. 428 Register Setting (Compare Data) ............................................................. 428 Time Reading Procedure of Real-Time Clock Mode ................................ 429 20.5.1 20.5.2 20.5.3 20.5.4 21. Pulse Width Modulator ......................................................................... 430 21.1 21.2 Introduction...................................................................................................... 430 Registers ......................................................................................................... 431 PWM Control Register 0 (PWMCON0)..................................................... 432 PWMi Prescaler (PWMPREi) (i = 0, 1) .................................................... 433 PWMi Register (PWMREGi) (i = 0, 1) ..................................................... 434 PWM Control Register 1 (PWMCON1)..................................................... 435 Setting Procedure..................................................................................... 437 Operation Example................................................................................... 437 21.2.1 21.2.2 21.2.3 21.2.4 21.3 21.3.1 21.3.2 Operations....................................................................................................... 437 22. Remote Control Signal Receiver .......................................................... 440 22.1 22.2 Introduction...................................................................................................... 440 Registers ......................................................................................................... 443 PMCi Function Select Register (PMCiCON0) (i = 0, 1) ........................... 445 PMCi Function Select Register (PMCiCON1) (i = 0, 1) ........................... 447 PMCi Function Select Register 2 (PMCiCON2) (i = 0, 1) ........................ 449 PMCi Function Select Register 3 (PMCiCON3) (i = 0, 1) ........................ 451 PMCi Status Register (PMCiSTS) (i = 0, 1) ............................................. 452 PMCi Interrupt Source Register (PMCiINT) (i = 0, 1) .............................. 455 22.2.1 22.2.2 22.2.3 22.2.4 22.2.5 22.2.6 A - 12 22.2.7 22.2.8 PMCi Header Pattern Set Register (MIN) (PMCiHDPMIN) (i = 0, 1) PMCi Header Pattern Set Register (MAX) (PMCiHDPMAX) (i = 0, 1) ..... 456 PMCi Data 0 Pattern Set Register (MIN) (PMCiD0PMIN) (i = 0, 1) PMCi Data 0 Pattern Set Register (MAX) (PMCiD0PMAX) (i = 0, 1) PMCi Data 1 Pattern Set Register (MIN) (PMCiD1PMIN) (i = 0, 1) PMCi Data 1 Pattern Set Register (MAX) (PMCiD1PMAX) (i = 0, 1) ...... 457 PMCi Measurements Register (PMCiTIM) (i = 0, 1) ................................ 458 22.2.9 22.2.10 PMCi Counter Value Register (PMCiBC) (i = 0, 1) .................................. 458 22.2.11 PMC0 Receive Bit Count Register (PMC0RBIT)...................................... 458 22.2.12 PMC0 Receive Data Store Register i (PMC0DATi) (i = 0 to 5) ............ 459 22.2.13 PMC0 Compare Control Register (PMC0CPC)........................................ 460 22.2.14 PMC0 Compare Data Register (PMC0CPD) ............................................ 461 22.3 Operations....................................................................................................... 462 Common Operations in Multiple Modes ................................................... 462 Pattern Match Mode (PMC0 and PMC1 Operate Individually) ................. 464 Pattern Match Mode (Connected Operation of PMC0 and PMC1)........... 471 Input Capture Mode (PMC0 and PMC1 Operate Individually).................. 476 Input Capture Mode (Simultaneous Count Operation of PMC0 and PMC1) .................................................................................................................. 480 22.3.1 22.3.2 22.3.3 22.3.4 22.3.5 22.4 22.5 Interrupt ........................................................................................................... 483 Notes on Remote Control Signal Receiver...................................................... 486 Start/Stop of PMCi .................................................................................... 486 Register Reading Procedure .................................................................... 486 22.5.1 22.5.2 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) ............................................. 487 23.1 23.2 Introduction...................................................................................................... 487 Registers ......................................................................................................... 492 UART Clock Select Register (UCLKSEL0)............................................... 494 Peripheral Clock Select Register (PCLKR) ............................................. 494 UARTi Transmit Buffer Register (UiTB) (i = 0 to 2, 5 to 7)........................ 495 UARTi Receive Buffer Register (UiRB) (i = 0 to 2, 5 to 7) ........................ 496 UARTi Bit Rate Register (UiBRG) (i = 0 to 2, 5 to 7) ................................ 498 UARTi Transmit/Receive Mode Register (UiMR) (i = 0 to 2, 5 to 7) ......... 498 UARTi Transmit/Receive Control Register 0 (UiC0) (i = 0 to 2, 5 to 7)..... 499 UARTi Transmit/Receive Control Register 1 (UiC1) (i = 0 to 2, 5 to 7)..... 501 UART Transmit/Receive Control Register 2 (UCON) ............................... 503 23.2.1 23.2.2 23.2.3 23.2.4 23.2.5 23.2.6 23.2.7 23.2.8 23.2.9 23.2.10 UARTi Special Mode Register (UiSMR) (i = 0 to 2, 5 to 7) ....................... 504 A - 13 23.2.11 UARTi Special Mode Register 2 (UiSMR2) (i = 0 to 2, 5 to 7) .................. 505 23.2.12 UARTi Special Mode Register 3 (UiSMR3) (i = 0 to 2, 5 to 7) .................. 506 23.2.13 UARTi Special Mode Register 4 (UiSMR4) (i = 0 to 2, 5 to 7) .................. 507 23.3 Operations....................................................................................................... 508 Clock Synchronous Serial I/O Mode......................................................... 508 Clock Asynchronous Serial I/O (UART) Mode.......................................... 517 Special Mode 1 (I2C mode) ...................................................................... 527 Special Mode 2 ......................................................................................... 537 Special Mode 3 (IE mode) ........................................................................ 542 Special Mode 4 (SIM Mode) (UART2) ...................................................... 544 Interrupt Related Registers....................................................................... 549 Reception Interrupt ................................................................................... 550 Clock Synchronous Serial I/O................................................................... 551 UART (Clock Asynchronous Serial I/O) Mode.......................................... 553 Special Mode 1 (I2C Mode) ...................................................................... 553 Special Mode 4 (SIM Mode) ..................................................................... 553 23.3.1 23.3.2 23.3.3 23.3.4 23.3.5 23.3.6 23.4 23.4.1 23.4.2 23.5 23.5.1 23.5.2 23.5.3 23.5.4 Interrupts ......................................................................................................... 549 Notes on Serial Interface UARTi (i = 0 to 2, 5 to 7) ......................................... 551 24. Serial Interface SI/O3 and SI/O4.......................................................... 554 24.1 24.2 Introduction...................................................................................................... 554 Registers ......................................................................................................... 556 Peripheral Clock Select Register (PCLKR) .............................................. 557 SI/O Transmit/Receive Register (SiTRR) (i = 3, 4) .................................. 557 SI/Oi Control Register (SiC) (i = 3, 4) ...................................................... 558 SI/Oi Bit Rate Register (SiBRG) (i = 3, 4) ................................................ 559 SI/O3, 4 Control Register 2 (S34C2) ........................................................ 559 Basic Operations ...................................................................................... 560 CLK Polarity Selection.............................................................................. 560 LSB First or MSB First Selection .............................................................. 561 Internal Clock............................................................................................ 562 Function for Selecting SOUTi State after Transmission............................ 563 External Clock .......................................................................................... 564 SOUTi Pin................................................................................................. 564 A - 14 24.2.1 24.2.2 24.2.3 24.2.4 24.2.5 24.3 24.3.1 24.3.2 24.3.3 24.3.4 24.3.5 24.3.6 24.3.7 Operations....................................................................................................... 560 24.3.8 24.4 24.5 Function for Setting SOUTi Initial Value ................................................... 565 Interrupt ........................................................................................................... 566 Notes on Serial Interface SI/O3 and SI/O4 ..................................................... 567 SOUTi Pin Level When SOUTi Output Disabled ...................................... 567 External Clock Control.............................................................................. 567 Register Access When Using External Clock........................................... 567 SiTRR Register Access ............................................................................ 567 Pin Function Switch When Using Internal Clock ...................................... 567 Operation After Reset When Selecting External Clock ............................ 567 24.5.1 24.5.2 24.5.3 24.5.4 24.5.5 24.5.6 25. Multi-Master I2C-bus Interface ............................................................. 568 25.1 25.2 Introduction...................................................................................................... 568 Registers Descriptions .................................................................................... 571 Peripheral Clock Select Register (PCLKR) .............................................. 572 I2C0 Data Shift Register (S00) ................................................................. 573 I2C0 Address Register i (S0Di) (i = 0 to 2) ............................................. 574 I2C0 Control Register (S1D0)................................................................... 575 I2C0 Clock Control Register (S20) ........................................................... 578 I2C0 Start/Stop Condition Control Register (S2D0).................................. 581 I2C0 Control Register 1 (S3D0)................................................................ 582 I2C0 Control Register 2 (S4D0)................................................................ 587 I2C0 Status Register 0 (S10).................................................................... 589 25.2.1 25.2.2 25.2.3 25.2.4 25.2.5 25.2.6 25.2.7 25.2.8 25.2.9 25.3 25.2.10 I2C0 Status Register 1 (S11) .................................................................... 594 Operations....................................................................................................... 595 Clock......................................................................................................... 595 Generation of Start Condition ................................................................... 598 Generation of Stop Condition ................................................................... 600 Generation of Restart Condition ............................................................... 601 Start Condition Overlap Protect ................................................................ 602 Arbitration Lost ......................................................................................... 604 Start Condition and Stop Condition Detection .......................................... 605 Operation After Completion of Slave Address/Data Transmit/Receive .... 608 Timeout Detection .................................................................................... 609 25.3.1 25.3.2 25.3.3 25.3.4 25.3.5 25.3.6 25.3.7 25.3.8 25.3.9 25.4 25.3.10 Data Transmit/Receive Examples ............................................................ 610 Interrupts ......................................................................................................... 615 A - 15 25.5 Notes on Multi-Master I2C-bus Interface ......................................................... 618 Limitation on CPU Clock........................................................................... 618 Register Access........................................................................................ 618 25.5.1 25.5.2 26. Consumer Electronics Control (CEC) Function.................................... 619 26.1 26.2 Introduction...................................................................................................... 619 Registers ......................................................................................................... 622 CEC Function Control Register 1 (CECC1).............................................. 622 CEC Function Control Register 2 (CECC2).............................................. 623 CEC Function Control Register 3 (CECC3).............................................. 625 CEC Function Control Register 4 (CECC4).............................................. 627 CEC Flag Register (CECFLG).................................................................. 629 CEC Interrupt Source Select Register (CISEL) ........................................ 630 CEC Transmit Buffer Register 1 (CCTB1) ................................................ 631 CEC Transmit Buffer Register 2 (CCTB2) ................................................ 631 CEC Receive Buffer Register 1 (CCRB1) ................................................ 632 26.2.1 26.2.2 26.2.3 26.2.4 26.2.5 26.2.6 26.2.7 26.2.8 26.2.9 26.2.10 CEC Receive Buffer Register 2 (CCRB2) ................................................ 632 26.2.11 CEC Receive Follower Address Set Register 1 (CRADRI1), CEC Receive Follower Address Set Register 2 (CRADRI2) .................... 633 26.2.12 Port Control Register (PCR) ..................................................................... 634 26.3 Operations....................................................................................................... 635 Standard Value and I/O Timing................................................................. 635 Count Source............................................................................................ 635 CEC Input/Output ..................................................................................... 635 Digital Filter............................................................................................... 636 Reception ................................................................................................. 637 Transmission ............................................................................................ 643 26.3.1 26.3.2 26.3.3 26.3.4 26.3.5 26.3.6 26.4 26.5 Interrupts ......................................................................................................... 648 Notes on CEC (Consumer Electronics Control) .............................................. 650 Registers and Bit Operation ..................................................................... 650 26.5.1 27. A/D Converter....................................................................................... 651 27.1 27.2 Introduction...................................................................................................... 651 Registers ......................................................................................................... 653 Peripheral Clock Stop Register (PCLKSTP1)........................................... 654 Port Control Register (PCR) ..................................................................... 655 A - 16 27.2.1 27.2.2 27.2.3 27.2.4 27.2.5 27.2.6 27.2.7 27.3 27.3.1 27.3.2 27.3.3 27.3.4 27.3.5 27.3.6 27.4 27.4.1 27.4.2 27.4.3 27.4.4 27.4.5 27.5 27.6 27.7 Open-Circuit Detection Assist Function Register (AINRST)..................... 656 AD Register i (ADi) (i = 0 to 7) ........................................................... 657 A/D Control Register 2 (ADCON2) ........................................................... 658 A/D Control Register 0 (ADCON0) ........................................................... 660 A/D Control Register 1 (ADCON1) ........................................................... 662 A/D Conversion Cycle .............................................................................. 663 A/D Conversion Start Conditions .............................................................. 665 A/D Conversion Result ............................................................................. 666 Extended Analog Input Pins ..................................................................... 666 Current Consumption Reduce Function ................................................... 666 Open-Circuit Detection Assist Function.................................................... 666 One-Shot Mode ........................................................................................ 668 Repeat Mode ............................................................................................ 671 Single Sweep Mode.................................................................................. 674 Repeat Sweep Mode 0 ............................................................................. 676 Repeat Sweep Mode 1 ............................................................................. 678 Operations....................................................................................................... 663 Operational Modes .......................................................................................... 668 External Sensor............................................................................................... 681 Interrupt ........................................................................................................... 683 Notes on A/D Converter .................................................................................. 684 Analog Input Pin ....................................................................................... 684 fAD Frequency.......................................................................................... 684 Pin Configuration ...................................................................................... 684 Register Access........................................................................................ 684 A/D Conversion Start ................................................................................ 684 A/D Operation Mode Change ................................................................... 685 State When Forcibly Terminated............................................................... 685 A/D Open-Circuit Detection Assist Function............................................. 685 Detection of Completion of A/D Conversion ............................................. 685 27.7.1 27.7.2 27.7.3 27.7.4 27.7.5 27.7.6 27.7.7 27.7.8 27.7.9 27.7.10 Register Settings ...................................................................................... 685 28. D/A Converter....................................................................................... 686 28.1 28.2 Introduction...................................................................................................... 686 Registers ......................................................................................................... 687 A - 17 28.2.1 28.2.2 28.3 28.4 D/Ai Register (DAi) (i = 0 to 1).................................................................. 687 D/A Control Register (DACON) ................................................................ 687 Operations....................................................................................................... 688 Notes on D/A Converter .................................................................................. 689 Not Using D/A Converter .......................................................................... 689 28.4.1 29. CRC Calculator .................................................................................... 690 29.1 29.2 Introduction...................................................................................................... 690 Registers ......................................................................................................... 691 CRC Data Register (CRCD) ..................................................................... 691 CRC Input Register (CRCIN).................................................................... 691 CRC Mode Register (CRCMR)................................................................. 692 SFR Snoop Address Register (CRCSAR)................................................ 692 Basic Operation ........................................................................................ 693 CRC Snoop .............................................................................................. 693 29.2.1 29.2.2 29.2.3 29.2.4 29.3 29.3.1 29.3.2 Operations....................................................................................................... 693 30. Flash Memory....................................................................................... 696 30.1 30.2 30.3 Introduction...................................................................................................... 696 Memory Map ................................................................................................... 698 Registers ......................................................................................................... 700 Flash Memory Control Register 0 (FMR0)................................................ 700 Flash Memory Control Register 1 (FMR1)................................................ 703 Flash Memory Control Register 2 (FMR2)................................................ 704 Flash Memory Control Register 3 (FMR3)................................................ 705 Flash Memory Control Register 6 (FMR6)................................................ 706 30.3.1 30.3.2 30.3.3 30.3.4 30.3.5 30.4 30.5 30.6 30.7 30.8 Optional Function Select Address 1 (OFS1) ................................................... 707 Flash Memory Rewrite Disable Function......................................................... 708 Boot Mode ....................................................................................................... 708 User Boot Function.......................................................................................... 709 CPU Rewrite Mode.......................................................................................... 711 Operating Speed....................................................................................... 712 Data Protect Function............................................................................... 712 Suspend Function (under review)............................................................. 713 Software Command.................................................................................. 714 Status Register ......................................................................................... 721 A - 18 30.8.1 30.8.2 30.8.3 30.8.4 30.8.5 30.8.6 30.8.7 30.9 30.9.1 30.9.2 30.9.3 30.9.4 30.9.5 30.9.6 EW0 Mode................................................................................................ 724 EW1 Mode................................................................................................ 729 ID Code Check Function .......................................................................... 735 Forced Erase Function ............................................................................. 736 Standard Serial I/O Mode Disable Function ............................................. 736 Standard Serial I/O Mode 1 ...................................................................... 737 Standard Serial I/O Mode 2 ...................................................................... 739 Parallel I/O Mode...................................................................................... 740 Standard Serial I/O Mode ................................................................................ 734 30.10 Notes on Flash Memory .................................................................................. 741 30.10.1 Functions to Prevent Flash Memory from Being Rewritten ...................... 741 30.10.2 Reading of Data Flash.............................................................................. 741 30.10.3 CPU Rewrite Mode................................................................................... 741 30.10.4 Standard Serial I/O Mode ......................................................................... 743 31. Precautions .......................................................................................... 744 31.1 31.2 31.3 31.4 31.5 OFS1 Address and ID Code Storage Address ................................................ 744 Notes on Noise................................................................................................ 744 Notes on SFRs ................................................................................................ 746 Register Settings ...................................................................................... 746 Notes on Protection......................................................................................... 747 Notes on Resets.............................................................................................. 748 Power Supply Rising Gradient.................................................................. 748 Power-On Reset ....................................................................................... 748 OSDR Bit (Oscillation Stop Detection Reset Detection Flag) ................... 748 Oscillation Circuit Using an Oscillator....................................................... 749 Noise Countermeasure............................................................................. 750 CPU ClockW............................................................................................. 751 Oscillation Stop, Re-Oscillation Detect Function ...................................... 751 PLL Frequency Synthesizer ..................................................................... 752 CPU Clock ................................................................................................ 753 Wait Mode ................................................................................................ 753 Stop Mode ................................................................................................ 754 A - 19 31.3.1 31.5.1 31.5.2 31.5.3 31.6 31.6.1 31.6.2 31.6.3 31.6.4 31.6.5 31.7 31.7.1 31.7.2 31.7.3 Notes on Clock Generator............................................................................... 749 Notes on Power Control .................................................................................. 753 31.7.4 31.8 31.9 Low Current Consumption Read Mode .................................................... 754 Notes on Processor Mode............................................................................... 755 Notes on Bus................................................................................................... 756 Reading Data Flash.................................................................................. 756 External Bus ............................................................................................. 756 External Access Soon After Writing to the SFRs...................................... 756 31.9.1 31.9.2 31.9.3 31.10 Notes on Memory Space Expansion Function ................................................ 757 31.11 Notes on Programmable I/O Ports .................................................................. 758 31.11.1 Influence of the SD Input .......................................................................... 758 31.11.2 Influence of SI/O3 and SI/O4.................................................................... 758 31.11.3 100-Pin Package ...................................................................................... 758 31.11.4 80-Pin Package ........................................................................................ 758 31.12 Notes on Interrupts.......................................................................................... 759 31.12.1 Reading Address 00000h ......................................................................... 759 31.12.2 SP Setting................................................................................................. 759 31.12.3 NMI Interrupt............................................................................................. 759 31.12.4 Changing an Interrupt Source .................................................................. 760 31.12.5 Rewriting the Interrupt Control Register ................................................... 761 31.12.6 INT Interrupt ............................................................................................. 762 31.13 Notes on Watchdog Timer............................................................................... 763 31.14 Notes on DMAC .............................................................................................. 764 31.14.1 Write to the DMAE Bit in the DMiCON Register (i = 0 to 3)...................... 764 31.14.2 Changing DMA Request Source .............................................................. 764 31.15 Notes on Timer A ............................................................................................ 765 31.15.1 Timer A (Timer Mode)............................................................................... 765 31.15.2 Timer A (Event Counter Mode)................................................................. 766 31.15.3 Timer A (One-Shot Timer Mode) .............................................................. 767 31.15.4 Timer A (Pulse Width Modulation Mode) .................................................. 768 31.15.5 Timer A (Programmable Output Mode) .................................................... 769 31.16 Notes on Timer B ............................................................................................ 770 31.16.1 Timer B (Timer Mode)............................................................................... 770 31.16.2 Timer B (Event Counter Mode)................................................................. 771 31.16.3 Timer B (Pulse Period/Pulse Width Measurement Modes) ...................... 772 31.17 Notes on Three-Phase Motor Control Timer Function..................................... 773 31.17.1 Timer A, Timer B....................................................................................... 773 A - 20 31.17.2 Forced Cutoff Input................................................................................... 773 31.18 Notes on Real-Time Clock............................................................................... 774 31.18.1 Starting and Stopping Count..................................................................... 774 31.18.2 Register Setting (Time Data etc.) ............................................................. 774 31.18.3 Register Setting (Compare Data) ............................................................. 774 31.18.4 Time Reading Procedure of Real-Time Clock Mode ................................ 775 31.19 Notes on Pulse Width Modulator..................................................................... 776 31.20 Notes on Remote Control Signal Receiver...................................................... 777 31.20.1 Start/Stop of PMCi .................................................................................... 777 31.20.2 Register Reading Procedure .................................................................... 777 31.21 Notes on Serial Interface UARTi (i = 0 to 2, 5 to 7) ........................................ 778 31.21.1 Clock Synchronous Serial I/O................................................................... 778 31.21.2 UART (Clock Asynchronous Serial I/O) Mode.......................................... 780 31.21.3 Special Mode 1 (I2C Mode) ...................................................................... 780 31.21.4 Special Mode 4 (SIM Mode) ..................................................................... 780 31.22 Notes on SI/O3 and SI/O4............................................................................... 781 31.22.1 SOUTi Pin Level When SOUTi Output Disabled ...................................... 781 31.22.2 External Clock Control.............................................................................. 781 31.22.3 Register Access When Using External Clock........................................... 781 31.22.4 SiTRR Register Access ............................................................................ 781 31.22.5 Pin Function Switch When Using Internal Clock ...................................... 781 31.22.6 Operation After Reset When Selecting External Clock ............................ 781 31.23 Notes on Multi-Master I2C-bus Interface ......................................................... 782 31.23.1 Limitation on CPU Clock........................................................................... 782 31.23.2 Register Access........................................................................................ 782 31.24 Notes on CEC (Consumer Electronics Control) .............................................. 783 31.24.1 Registers and Bit Operation ..................................................................... 783 31.25 Notes on A/D Converter .................................................................................. 784 31.25.1 Analog Input Pin ....................................................................................... 784 31.25.2 fAD Frequency.......................................................................................... 784 31.25.3 Pin Configuration ...................................................................................... 784 31.25.4 Register Access........................................................................................ 784 31.25.5 A/D Conversion Start ................................................................................ 784 31.25.6 A/D Operation Mode Change ................................................................... 785 31.25.7 State When Forcibly Terminated............................................................... 785 A - 21 31.25.8 A/D Open-Circuit Detection Assist Function............................................. 785 31.25.9 Detection of Completion of A/D Conversion ............................................. 785 31.25.10 Register Settings ...................................................................................... 785 31.26 Notes on D/A Converter .................................................................................. 786 31.26.1 Not Using D/A Converter .......................................................................... 786 31.27 Notes on Flash Memory .................................................................................. 787 31.27.1 Functions to Prevent Flash Memory from Being Rewritten ...................... 787 31.27.2 Reading of Data Flash.............................................................................. 787 31.27.3 CPU Rewrite Mode................................................................................... 787 31.27.4 Standard Serial I/O Mode ......................................................................... 789 Appendix 1. Package Dimensions ............................................................... 790 A - 22 SFR Page Reference Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h XXXX X000b 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0073h 0074h 0075h 0076h 0077h Note: 1. Blank columns are all reserved space. No access is allowed. 0078h 0072h 0070h 0071h 006Fh 006Ch 006Dh 006Eh Voltage Monitor 0 Circuit Control Register Voltage Monitor 1 Circuit Control Register Voltage Monitor 2 Circuit Control Register VW0C VW1C VW2C 82 83 85 Voltage Detection 1 Level Select Register VD1LS 80 Voltage Monitor Function Select Register VWCE 80 40 MHz On-Chip Oscillator Control Register 0 FRA0 112 Processor Mode Register 2 PM2 111 Reset Source Determine Register Voltage Detection 2 Circuit Flag Register Voltage Detection Circuit Operation Enable Register Chip Select Expansion Control Register PLL Control Register 0 RSTFR VCR1 VCR2 CSE PLC0 61 78 79 162 110 Clock Prescaler Reset Flag Program 2 Area Control Register External Area Wait Control Expansion Register Peripheral Clock Select Register PRG2C EWC PCLKR SCM0 156 164 109 Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Chip Select Control Register External Area Recovery Cycle Control Register Protect Register Data Bank Register Oscillation Stop Detection Register PM0 PM1 CM0 CM1 CSR EWR PRCR DBR CM2 60 154 103 105 161 164 55 183 107 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h CPSRF 288 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh DMA2 Interrupt Control Register DMA3 Interrupt Control Register UART5 Bus Collision Detection Interrupt Control Register UART5 Bus Collision Detection Interrupt Control Register UART5 Transmit Interrupt Control Register CEC2 Interrupt Control Register UART5 Receive Interrupt Control Register UART6 Bus Collision Detection Interrupt Control Register Real-Time Clock Period Interrupt Control Register UART6 Transmit Interrupt Control Register Real-Time Clock Compare Match Interrupt Control Register UART6 Receive Interrupt Control Register UART7 Bus Collision Detection Interrupt Control Register Remote Control Signal Receiver 0 Interrupt Control Register UART7 Transmit Interrupt Control Register Remote Control Signal Receiver 1 Interrupt Control Register UART7 Receive Interrupt Control Register DM2IC DM3IC U5BCNIC CEC1IC 223 223 223 0048h 0049h 0047h Register Symbol Page Address 0042h Register INT7 Interrupt Control Register Symbol INT7IC Page 224 Address 0043h 0044h 0045h 0046h Register INT6 Interrupt Control Register INT3 Interrupt Control Register Timer B5 Interrupt Control Register Timer B4 Interrupt Control Register UART1 Bus Collision Detection Interrupt Control Register Timer B3 Interrupt Control Register UART0 Bus Collision Detection Interrupt Control Register SI/O4 Interrupt Control Register INT5 Interrupt Control Register SI/O3 Interrupt Control Register INT4 Interrupt Control Register UART2 Bus Collision Detection Interrupt Control Register DMA0 Interrupt Control Register DMA1 Interrupt Control Register Key Input Interrupt Control Register A/D Conversion Interrupt Control Register UART2 Transmit Interrupt Control Register UART2 Receive Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register Timer A0 Interrupt Control Register Timer A1 Interrupt Control Register Timer A2 Interrupt Control Register Timer A3 Interrupt Control Register Timer A4 Interrupt Control Register Timer B0 Interrupt Control Register Timer B1 Interrupt Control Register Timer B2 Interrupt Control Register INT0 Interrupt Control Register INT1 Interrupt Control Register INT2 Interrupt Control Register Symbol INT6IC INT3IC TB5IC TB4IC U1BCNIC TB3IC U0BCNIC S4IC INT5IC S3IC INT4IC BCNIC DM0IC DM1IC KUPIC ADIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC TB2IC INT0IC INT1IC INT2IC Page 224 224 223 223 223 224 224 223 223 223 223 223 223 223 223 223 223 223 223 223 223 223 223 223 223 223 224 224 224 S5TIC CEC2IC S5RIC U6BCNIC RTCTIC 223 223 223 S6TIC RTCCIC S6RIC U7BCNIC PMC0IC 223 223 223 S7TIC PMC1IC S7RIC 223 223 B-1 Address 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh 0080h to 017Fh 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh Register Symbol Page Address 01BBh 01BCh 01BDh 01BEh 01BFh 01C0h 01C1h 01C2h 01C3h 01C4h 01C5h 01C6h 01C7h Register DMA3 Control Register Symbol DM3CON Page 270 IICBus Interface Interrupt Control Register SCL/SDA Interrupt Control Register IICIC SCLDAIC 223 223 Timer B0-1 Register Timer B1-1 Register Timer B2-1 Register Pulse Period/Pulse Width Measurement Mode Function Select Register 1 Timer B Count Source Select Register 0 Timer B Count Source Select Register 1 Timer AB Division Control Register 0 TB01 TB11 TB21 PPWFS1 341 341 341 342 DMA0 Source Pointer SAR0 268 DMA0 Destination Pointer DAR0 268 01C8h 01C9h 01CAh 01CBh TBCS0 TBCS1 TCKDIVC0 343 343 289 DMA0 Transfer Counter TCR0 269 01CCh 01CDh 01CEh 01CFh DMA0 Control Register DM0CON 270 01D0h 01D1h 01D2h 01D3h Timer A Count Source Select Register 0 Timer A Count Source Select Register 1 Timer A Count Source Select Register 2 16-Bit Pulse Width Modulation Mode Function Select Register Timer A Waveform Output Function Select Register TACS0 TACS1 TACS2 PWMFS TAPOFS 290 290 290 291 292 DMA1 Source Pointer SAR1 268 01D4h 01D5h 01D6h DMA1 Destination Pointer DAR1 268 01D7h 01D8h 01D9h Timer A Output Waveform Change Enable Register Three-Phase Protect Control Register TAOW 293 DMA1 Transfer Counter TCR1 269 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh 01E0h 01E1h 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h TPRC 377 DMA1 Control Register DM1CON 270 Timer B3-1 Register Timer B4-1 Register Timer B5-1 Register Pulse Period/Pulse Width Measurement Mode Function Select Register 2 Timer B Count Source Select Register 2 Timer B Count Source Select Register 3 TB31 TB41 TB51 PPWFS2 341 341 341 342 DMA2 Source Pointer SAR2 268 DMA2 Destination Pointer DAR2 268 TBCS2 TBCS3 343 343 DMA2 Transfer Counter TCR2 269 01EAh 01EBh 01ECh 01EDh DMA2 Control Register DM2CON 270 01EEh 01EFh 01F0h 01F1h PMC0 Function Select Register 0 PMC0 Function Select Register 1 PMC0 Function Select Register 2 PMC0 Function Select Register 3 PMC0 Status Register PMC0 Interrupt Source Select Register PMC0 Compare Control Register PMC0 Compare Data Register PMC1 Function Select Register 0 PMC1 Function Select Register 1 PMC1 Function Select Register 2 PMC0CON0 PMC0CON1 PMC0CON2 PMC0CON3 PMC0STS PMC0INT PMC0CPC PMC0CPD PMC1CON0 PMC1CON1 PMC1CON2 445 447 449 451 452 455 460 461 445 447 449 DMA3 Source Pointer SAR3 268 01F2h 01F3h 01F4h 01F5h DMA3 Destination Pointer DAR3 268 01F6h 01F7h 01F8h 01F9h DMA3 Transfer Counter TCR3 269 01FAh Note: 1. Blank columns are all reserved space. No access is allowed. B-2 Address 01FBh 01FCh 01FDh 01FEh 01FFh 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020Ah 020Bh 020Ch 020Dh 020Eh 020Fh 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021Ah 021Bh 021Ch 021Dh 021Eh 021Fh 0220h 0221h 0222h 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022Ah 022Bh 022Ch 022Dh 022Eh 022Fh 0230h 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023Ah 023Bh 023Ch 023Dh 023Eh 023Fh Register PMC1 Function Select Register 3 PMC1 Status Register PMC1 Interrupt Source Select Register Symbol PMC1CON3 PMC1STS PMC1INT Page 451 452 455 Address 0240h 0241h 0242h 0243h 0244h 0245h 0246h 0247h 0248h 0249h Register Symbol Page UART0 Special Mode Register 4 UART0 Special Mode Register 3 UART0 Special Mode Register 2 UART0 Special Mode Register UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register UART Transmit/Receive Control Register 2 UART Clock Select Register UART1 Special Mode Register 4 UART1 Special Mode Register 3 UART1 Special Mode Register 2 UART1 Special Mode Register UART1 Transmit/Receive Mode Register UART1 Bit Rate Register UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register U0SMR4 U0SMR3 U0SMR2 U0SMR U0MR U0BRG U0TB U0C0 U0C1 U0RB UCON UCLKSEL0 U1SMR4 U1SMR3 U1SMR2 U1SMR U1MR U1BRG U1TB U1C0 U1C1 U1RB 507 506 505 504 498 498 495 499 501 496 503 494 507 506 505 504 498 498 495 499 501 496 Interrupt Source Select Register 3 Interrupt Source Select Register 2 Interrupt Source Select Register IFSR3A IFSR2A IFSR 225 226 227 024Ah 024Bh 024Ch 024Dh 024Eh 024Fh 0250h 0251h 0252h Address Match Interrupt Enable Register Address Match Interrupt Enable Register 2 Address Match Interrupt Register 0 AIER AIER2 RMAD0 228 228 229 0253h 0254h 0255h 0256h 0257h 0258h Address Match Interrupt Register 1 RMAD1 229 0259h 025Ah 025Bh 025Ch Address Match Interrupt Register 2 RMAD2 229 025Dh 025Eh 025Fh 0260h Address Match Interrupt Register 3 RMAD3 229 0261h 0262h 0263h 0264h UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register UART2 Transmit/Receive Mode Register UART2 Bit Rate Register UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register SI/O3 Transmit/Receive Register SI/O3 Control Register SI/O3 Bit Rate Register SI/O4 Transmit/Receive Register SI/O4 Control Register SI/O4 Bit Rate Register SI/O3, 4 Control Register 2 U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB S3TRR S3C S3BRG S4TRR S4C S4BRG S34C2 507 506 505 504 498 498 495 499 501 496 557 558 559 557 558 559 559 Flash Memory Control Register 0 Flash Memory Control Register 1 Flash Memory Control Register 2 Flash Memory Control Register 3 FMR0 FMR1 FMR2 FMR3 130 701 131 703 0265h 0266h 0267h 0268h 0269h 026Ah 026Bh 026Ch 026Dh 026Eh 026Fh 0270h 0271h 0272h 0273h 0274h Flash Memory Control Register 6 FMR6 704 0275h 0276h 0277h 0278h 0279h 027Ah 027Bh 027Ch 027Dh 027Eh 027Fh 0280h 0281h 0282h Note: 1. Blank columns are all reserved space. No access is allowed. B-3 Address 0283h 0284h 0285h 0286h 0287h 0288h 0289h 028Ah 028Bh 028Ch 028Dh 028Eh 028Fh 0290h 0291h 0292h 0293h 0294h 0295h 0296h 0297h 0298h 0299h 029Ah 029Bh 029Ch 029Dh 029Eh 029Fh 02A0h 02A1h 02A2h 02A3h 02A4h 02A5h 02A6h 02A7h 02A8h 02A9h 02AAh 02ABh 02ACh 02ADh 02AEh 02AFh 02B0h 02B1h 02B2h 02B3h 02B4h 02B5h 02B6h 02B7h 02B8h 02B9h 02BAh 02BBh 02BCh 02BDh 02BEh 02BFh 02C0h to 02FFh 0300h 0301h 0302h 0303h Register UART5 Special Mode Register 4 UART5 Special Mode Register 3 UART5 Special Mode Register 2 UART5 Special Mode Register UART5 Transmit/Receive Mode Register UART5 Bit Rate Register UART5 Transmit Buffer Register UART5 Transmit/Receive Control Register 0 UART5 Transmit/Receive Control Register 1 UART5 Receive Buffer Register Symbol U5SMR4 U5SMR3 U5SMR2 U5SMR U5MR U5BRG U5TB U5C0 U5C1 U5RB Page 507 506 505 504 498 498 495 499 501 496 Address 0304h 0305h 0306h 0307h 0308h 0309h 030Ah 030Bh 030Ch 030Dh 030Eh 030Fh 0310h 0311h 0312h 0313h Register Timer A2-1 Register Timer A4-1 Register Three-Phase PWM Control Register 0 Three-Phase PWM Control Register 1 Three-Phase Output Buffer Register 0 Three-Phase Output Buffer Register 1 Dead Time Timer Timer B2 Interrupt Generation Frequency Set Counter Position-Data-Retain Function Control Register Timer B3 Register Timer B4 Register Timer B5 Register Symbol TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2 PDRF Page 295 295 369 371 373 373 373 374 376 TB3 TB4 TB5 340 340 340 UART6 Special Mode Register 4 UART6 Special Mode Register 3 UART6 Special Mode Register 2 UART6 Special Mode Register UART6 Transmit/Receive Mode Register UART6 Bit Rate Register UART6 Transmit Buffer Register UART6 Transmit/Receive Control Register 0 UART6 Transmit/Receive Control Register 1 UART6 Receive Buffer Register U6SMR4 U6SMR3 U6SMR2 U6SMR U6MR U6BRG U6TB U6C0 U6C1 U6RB 507 506 505 504 498 498 495 499 501 496 0314h 0315h 0316h 0317h 0318h 0319h 031Ah 031Bh 031Ch 031Dh 031Eh 031Fh 0320h 0321h 0322h 0323h Port Function Control Register PFCR 377 Timer B3 Mode Register Timer B4 Mode Register Timer B5 Mode Register TB3MR TB4MR TB5MR 346 346 346 Count Start Flag One-Shot Start Flag Trigger Select Register Up/Down Flag Timer A0 Register Timer A1 Register Timer A2 Register Timer A3 Register Timer A4 Register Timer B0 Register Timer B1 Register Timer B2 Register Timer A0 Mode Register Timer A1 Mode Register Timer A2 Mode Register Timer A3 Mode Register Timer A4 Mode Register Timer B0 Mode Register Timer B1 Mode Register Timer B2 Mode Register Timer B2 Special Mode Register Real-Time Clock Second Data Register Real-Time Clock Minute Data Register Real-Time Clock Hour Data Register Real-Time Clock Day Data Register Real-Time Clock Control Register 1 Real-Time Clock Control Register 2 TABSR ONSF TRGSR UDF TA0 TA1 TA2 TA3 TA4 TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC RTCSEC RTCMIN RTCHR RTCWK RTCCR1 RTCCR2 296 297 298 299 294 294 294 294 294 340 340 340 300 300 300 300 300 346 346 346 375 406 407 408 409 410 412 UART7 Special Mode Register 4 UART7 Special Mode Register 3 UART7 Special Mode Register 2 UART7 Special Mode Register UART7 Transmit/Receive Mode Register UART7 Bit Rate Register UART7 Transmit Buffer Register UART7 Transmit/Receive Control Register 0 UART7 Transmit/Receive Control Register 1 UART7 Receive Buffer Register I2C0 Data Shift Register I2C0 Address Register 0 I2C0 Control Register I2C0 Clock Control Register I2C0 Start/Stop Condition Control Register I2C0 Control Register 1 I2C0 Control Register 2 I2C0 Status Register 0 I2C0 Status Register 1 I2C0 Address Register 1 I2C0 Address Register 2 U7SMR4 U7SMR3 U7SMR2 U7SMR U7MR U7BRG U7TB U7C0 U7C1 U7RB S00 S0D0 S1D0 S20 S2D0 S3D0 S4D0 S10 S11 S0D1 S0D2 507 506 505 504 498 498 495 499 501 496 573 574 575 578 581 582 587 589 594 574 574 0324h 0325h 0326h 0327h 0328h 0329h 032Ah 032Bh 032Ch 032Dh 032Eh 032Fh 0330h 0331h 0332h 0333h 0334h 0335h 0336h 0337h 0338h 0339h 033Ah 033Bh 033Ch 033Dh 033Eh 033Fh 0340h 0341h 0342h 0343h 0344h 0345h Timer B3/B4/B5 Count Start Flag Timer A1-1 Register TBSR TA11 345 295 Note: 1. Blank columns are all reserved space. No access is allowed. B-4 Address 0346h 0347h 0348h 0349h 034Ah 034Bh 034Ch 034Dh 034Eh 034Fh 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh 0360h 0361h 0362h 0363h 0364h 0365h 0366h 0367h 0368h 0369h 036Ah 036Bh 036Ch 036Dh 036Eh 036Fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h Register Real-Time Clock Count Source Select Register Real-Time Clock Second Compare Data Register Real-Time Clock Minute Compare Data Register Real-Time Clock Hour Compare Data Register Symbol RTCCSR Page 414 Address 0388h 0389h 038Ah Register Symbol Page RTCCSEC RTCCMIN RTCCHR 415 416 417 038Bh 038Ch 038Dh 038Eh 038Fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039Ah 039Bh 039Ch 039Dh 039Eh 039Fh 03A0h 03A1h 03A2h 03A3h Open-Circuit Detection Assist Function Register AINRST 655 DMA1 Source Select Register DM1SL 271 DMA0 Source Select Register DM0SL 271 DMA3 Source Select Register DM3SL 271 DMA2 Source Select Register DM2SL 271 CEC Function Control Register 1 CEC Function Control Register 2 CEC Function Control Register 3 CEC Function Control Register 4 CEC Flag Register CEC Interrupt Source Select Register CEC Transmit Buffer Register 1 CEC Transmit Buffer Register 2 CEC Receive Buffer Register 1 CEC Receive Buffer Register 2 CEC Receive Follower Address Set Register 1 CEC Receive Follower Address Set Register 2 CECC1 CECC2 CECC3 CECC4 CECFLG CISEL CCTB1 CCTB2 CCRB1 CCRB2 CRADRI1 CRADRI2 622619 623620 625621 627 629 630 631 631 632 632 633 633 Pull-Up Control Register 0 Pull-Up Control Register 1 Pull-Up Control Register 2 Pull-Up Control Register 3 PUR0 PUR1 PUR2 PUR3 205 206 207 208 03A4h 03A5h 03A6h 03A7h 03A8h 03A9h Port Control Register PCR 209 03AAh 03ABh 03ACh NMI/SD Digital Filter Register NMIDF 213 03ADh 03AEh 03AFh 03B0h 03B1h 03B2h 03B3h PWM Control Register 0 PWM0 Prescaler PWM0 Register PWM1 Prescaler PWM1 Register PWM Control Register 1 PWMCON0 PWMPRE0 PWMREG0 PWMPRE1 PWMREG1 PWMCON1 432 433 434 433 434 435 03B4h 03B5h 03B6h 03B7h 03B8h 03B9h 03BAh 03BBh 03BCh 03BDh 03BEh 03BFh SFR Snoop Address Register CRC Mode Register CRCSAR CRCMR 690 690 CRC Data Register CRC Input Register A/D Register 0 A/D Register 1 A/D Register 2 A/D Register 3 A/D Register 4 CRCD CRCIN AD0 AD1 AD2 AD3 AD4 689 689 661 661 661 661 661 Count Source Protection Mode Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register CSPR WDTR WDTS WDC 257 258 258 259 03C0h 03C1h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C8h 03C9h Note: 1. Blank columns are all reserved space. No access is allowed. B-5 Address 03CAh 03CBh 03CCh 03CDh 03CEh 03CFh 03D0h 03D1h 03D2h 03D3h 03D4h 03D5h 03D6h 03D7h 03D8h 03D9h 03DAh 03DBh 03DCh 03DDh 03DEh 03DFh 03E0h 03E1h 03E2h 03E3h 03E4h 03E5h 03E6h 03E7h 03E8h 03E9h 03EAh 03EBh 03ECh 03EDh 03EEh 03EFh 03F0h 03F1h 03F2h 03F3h 03F4h 03F5h 03F6h 03F7h 03F8h 03F9h 03FAh 03FBh 03FCh 03FDh 03FEh 03FFh D000h to D07Fh Register A/D Register 5 A/D Register 6 A/D Register 7 Symbol AD5 AD6 AD7 Page 661 661 661 Address D080h D081h D082h D083h D084h D085h D086h D087h D088h D089h Register PMC0 Header Pattern Set Register (Min) PMC0 Header Pattern Set Register (Max) PMC0 Data0 Pattern Set Register (Min) PMC0 Data0 Pattern Set Register (Max) PMC0 Data1 Pattern Set Register (Min) PMC0 Data1 Pattern Set Register (Max) PMC0 Measurements Register PMC0 Counter Value Register PMC0 Receive Data Store Register 0 PMC0 Receive Data Store Register 1 PMC0 Receive Data Store Register 2 PMC0 Receive Data Store Register 3 PMC0 Receive Data Store Register 4 PMC0 Receive Data Store Register 5 PMC0 Receive Bit Count Register PMC1 Hedder Pattern Set Register (Min) PMC1 Header Pattern Set Register (Max) PMC1 Data0 Pattern Set Register (Min) PMC1 Data0 Pattern Set Register (Max) PMC1 Data1 Pattern Set Register (Min) PMC1 Data1 Pattern Set Register (Max) PMC1 Measurements Register PMC1 Counter Value Register Symbol PMC0HDPMIN PMC0HDPMAX PMC0D0PMIN PMC0D0PMAX PMC0D1PMIN PMC0D1PMAX PMC0TIM PMC0BC PMC0DAT0 PMC0DAT1 PMC0DAT2 PMC0DAT3 PMC0DAT4 PMC0DAT5 PMC0RBIT PMC1HDPMIN PMC1HDPMAX PMC1D0PMIN PMC1D0PMAX PMC1D1PMIN PMC1D1PMAX PMC1TIM PMC1BC Page 456 456 457 457 457 457 458 458 459 459 459 459 459 459 458 456 456 457 457 457 457 458 458 A/D Control Register 2 A/D Control Register 0 A/D Control Register 1 D/A0 Register D/A1 Register D/A Control Register ADCON2 ADCON0 ADCON1 DA0 DA1 DACON 657 658 660 685 685 685 D08Ah D08Bh D08Ch D08Dh D08Eh D08Fh D090h D091h D092h D093h D094h D095h Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register Port P11 Register Port P10 Direction Register Port P11 Direction Register Port P12 Register Port P13 Register Port P12 Direction Register Port P13 Direction Register Port P14 Register Port P14 Direction Register P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 P11 PD10 PD11 P12 P13 PD12 PD13 P14 PD14 210 210 212 212 210 210 212 212 210 210 212 212 210 210 212 212 210 210 212 212 210 210 212 212 210 210 212 212 210 212 D096h D097h D098h D099h D09Ah D09Bh D09Ch D09Dh D09Eh D09Fh Note: 1. Blank columns are all reserved space. No access is allowed. FFFFFh Optional Function Select Address 1 OFS1 63 Note: 1. OFS1 address is not an SFR. B-6 PRELIMINARY M16C/65 Group RENESAS MCU 1. 1.1 Overview Features The M16C/65 Group microcomputer (MCU) incorporates the M16C/60 Series CPU core and flash memory, employing sophisticated instructions for a high level of efficiency. This MCU has 1 Mbyte of address space (expandable to 4 Mbytes), and it is capable of executing instructions at high speed. In addition, the CPU core boasts a multiplier for high-speed operation processing. Power consumption is low, and the M16C/65 Group supports operating modes that allow additional power control. The MCU also uses an anti-noise configuration to reduce emissions of electromagnetic noise and is designed to withstand electromagnetic interference (EMI). By integrating many of the peripheral functions, including the multifunction timer and serial interface, the number of system components has been reduced. 1.1.1 Applications Audio components, cameras, televisions, household appliances, office equipment, communication devices, mobile devices, industrial equipment, etc. Information in this manual is beleived to be accurate, but is not guaranteed to be entirely free of error. Specifications in this manual are subject to change for functional or performance improvements. Please make sure your manual is the latest edition. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 1 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview 1.2 Specifications The M16C/65 Group includes 128-pin, 100-pin, and 80-pin packages. Table 1.1 to Table 1.6 list specifications. Table 1.1 Item CPU Specifications (128-Pin Package) (1/2) Function Central processing unit Specification M16C/60 core (multiplier: 16-bit × 16-bit 32-bit, multiply and accumulate instruction: 16-bit × 16-bit + 32-bit 32-bit) • Number of basic instructions: 91 • Minimum instruction execution time: 31.25 ns (f(BCLK) = 32 MHz, VCC1 = 3.0 to 5.5 V) • Operating modes: Single-chip, memory expansion, and microprocessor See Table 1.7 “Product List”. Memory Voltage Detection Clock ROM, RAM, data flash Voltage detector Clock generator • Power-on reset • 3 voltage detection points (detection level of voltage detection 0 and 1 selectable) • 5 circuits: Main clock, sub clock, low-speed on-chip oscillator (125 kHz), high-speed on-chip oscillator (40 MHz ± 10%), PLL frequency synthesizer • Oscillation stop detection: Main clock oscillation stop detection and reoscillation detection function External Bus Bus and memory Expansion expansion • Frequency divider circuit: Divide ratio selectable from 1, 2, 4, 8, and 16 • Power save: Wait mode, stop mode • Real time clock • Address space: 1 Mbyte • External bus interface: 0 to 8 wait states, 4 chip select outputs, memory area expansion function (extension enable up to 4 Mbytes), 3 V and 5 V interfaces • Bus format: Separate bus or multiplexed bus selectable, data bus width selectable (8 or 16 bits), number of address buses selectable (12, 16, or 20) I/O Ports Interrupts Programmable I/O ports • CMOS I/O ports: 111, selectable pull-up resistor • N-channel open drain ports: 3 • Interrupt vectors: 70 • External interrupt input: 13 (NMI, INT × 8, key input × 4) • Interrupt priority levels: 7 15 bits × 1 (with prescaler) Automatic reset start function selectable Watchdog Timer DMA DMAC • 4 channels, cycle steal mode • Trigger sources: 43 • Transfer modes: 2 (single transfer, repeat transfer) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 2 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview Table 1.2 Item Timer Specifications (128-Pin Package) (2/2) Function Timer A Specification 16-bit timer × 5 Timer mode, event counter mode, one-shot timer mode, pulse width modulation (PWM) mode Event counter two-phase pulse signal processing (two-phase encoder input) ×3 Programmable output mode × 3 16-bit timer × 6 Timer mode, event counter mode, pulse period measurement mode, pulse width measurement mode Three-phase inverter control (timer A1, timer A2, timer A4, timer B2), on-chip dead time timer Count: second, minute, hour, day of week 8 bits × 2 Timer B Three-phase motor control timer function Real-time clock PWM function Remote control signal receiver • 2 circuits • 4 wave pattern matchings (differentiate wave pattern for headers, data 0, data 1, and special data) • 6-byte receive buffer (1 circuit) • Operating frequency of 32 kHz Serial Interface UART0 to UART2, UART5 to UART7 SI/O3, SI/O4 Multi-master I2C (3) Clock synchronous/asynchronous × 6 channels I2C-bus, IEBus (1), special mode 2 SIM (UART2) Clock synchronization only × 2 channels bus interface 1 channel CEC transmit/receive, arbitration lost detection, ACK signal generation, operation frequency of 32 kHz 10-bit resolution × 26 channels, including sample and hold function Conversion time: 1.72 µs 8-bit resolution × 2 CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant Programming and erasure power supply voltage: 2.7 to 5.5 V Programming and erasure endurance: 1,000 times (program ROM 1, program ROM 2)/10,000 times (data flash) Program security: ROM code protect, ID code check Functions on-chip debug, on-board flash rewrite function, address match × 4 25 MHz/VCC1 = 2.7 to 5.5 V, VCC2 = 2.7 V to VCC1 32 MHz/VCC1 = 3.0 to 5.5 V, VCC2 = 2.7 V to VCC1 TBD (32 MHz/VCC1 = VCC2 = 3 V) TBD (VCC1 = VCC2 = 3 V, in stop mode) -20°C to 85°C, -40°C to 85°C (2) 128-pin LQFP: PLQP0128KB-A (Previous package code: 128P6Q-A) CEC function A/D Converter D/A Converter CRC Calculator Flash Memory Debug Function Operation Frequency/Supply Voltage Current Consumption Operating Temperature Package Notes: 1. IEBus is a registered trademark of NEC Electronics Corporation. 2. See Table 1.7 “Product List” for the operating temperature. 3. The CEC function indicates circuitry which supports the transmission and reception of CEC signals standardized by the High-Definition Multimedia Interface (HDMI). HDMI and High-Definition Multimedia Interface are registered trademarks of HDMI Licensing, LLC. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 3 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview Table 1.3 Item CPU Specifications (100-Pin Package) (1/2) Function Central processing unit Specification M16C/60 core (multiplier: 16-bit × 16-bit 32-bit, multiply and accumulate instruction: 16-bit × 16-bit + 32-bit 32-bit) • Number of basic instructions: 91 • Minimum instruction execution time: 31.25 ns (f(BCLK) = 32 MHz, VCC1 = 3.0 to 5.5 V) • Operating modes: Single-chip, memory expansion, and microprocessor See Table 1.7 “Product List”. Memory Voltage Detection Clock ROM, RAM, data flash Voltage detector • Power-on reset • 3 voltage detection points (detection level of voltage detection 0 and 1 selectable) Clock generator • 5 circuits: Main clock, sub clock, low-speed on-chip oscillator (125 kHz), high-speed on-chip oscillator (40 MHz ± 10%), PLL frequency synthesizer • Oscillation stop detection: Main clock oscillation stop detection and reoscillation detection function External Bus Bus and memory Expansion expansion • Frequency divider circuit: Divide ratio selectable from 1, 2, 4, 8, and 16 • Power save: Wait mode, stop mode • Real time clock • Address space: 1 Mbyte • External bus interface: 0 to 8wait states, 4 chip select outputs, memory area expansion function (extension enable up to 4-Mbyte), 3 V, 5 V interface • Bus format: Separate bus or multiplexed bus selectable, data bus width selectable (8 or 16 bits), number of address buses selectable (12, 16, or 20) I/O Ports Interrupts Programmable I/O ports • CMOS I/O ports: 85, selectable pull-up resistor • N-channel open drain ports: 3 • Interrupt vectors: 70 • External interrupt input: 13 (NMI, INT × 8, key input × 4) • Interrupt priority levels: 7 15 bits × 1 (with prescaler) Automatic reset start function selectable Watchdog Timer DMA DMAC • 4 channels, cycle steal mode • Trigger sources: 43 • Transfer modes: 2 (single transfer, repeat transfer) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 4 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview Table 1.4 Item Timer Specifications (100-Pin Package) (2/2) Function Timer A Specification 16-bit timer × 5 Timer mode, event counter mode, one-shot timer mode, pulse width modulation (PWM) mode Event counter two-phase pulse signal processing (two-phase encoder input) × 3 Programmable output mode × 3 16-bit timer × 6 Timer mode, event counter mode, pulse period measurement mode, pulse width measurement mode Three-phase inverter control (timer A1, timer A2, timer A4, timer B2), on-chip dead time timer Count: second, minute, hour, day of week 8 bits × 2 Timer B Three-phase motor control timer function Real-time clock PWM function Remote control signal receiver • 2 circuits • 4 wave pattern matchings (differentiate wave pattern for headers, data 0, data 1, and special data) • 6-byte receive buffer (1 circuit) • Operating frequency of 32 kHz Serial Interface UART0 to UART2, UART5 to UART7 SI/O3, SI/O4 Multi-master I2C (3) Clock synchronous/asynchronous × 6 channels I2C-bus, IEBus (1), special mode 2 SIM (UART2) Clock synchronization only × 2 channels bus interface 1 channel CEC transmit/receive, arbitration lost detection, ACK signal generation, operation frequency of 32 kHz 10-bit resolution × 26 channels, including sample and hold function Conversion time: 1.72 µs 8-bit resolution × 2 CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant Programming and erasure power supply voltage: 2.7 to 5.5 V Programming and erasure endurance: 1,000 times (program ROM 1, program ROM 2)/10,000 times (data flash) Program security: ROM code protect, ID code check Functions on-chip debug, on-board flash rewrite function, address match × 4 25 MHz/VCC1 = 2.7 to 5.5 V, VCC2 = 2.7 V to VCC132 MHz/VCC1 = 3.0 to 5.5 V, VCC2 = 2.7 V to VCC1 TBD (32 MHz/VCC1 = VCC2 = 3 V) TBD (VCC1 = VCC2 = 3 V, in stop mode) -20°C to 85°C, -40°C to 85°C (2) 100-pin QFP: PRQP0100JD-B (Previous package code: 100P6F-A) 100-pin LQFP: PLQP0100KB-A (Previous package code: 100P6Q-A) CEC function A/D Converter D/A Converter CRC Calculator Flash Memory Debug Function Operation Frequency/Supply Voltage Current Consumption Operating Temperature Package Notes: 1. IEBus is a registered trademark of NEC Electronics Corporation. 2. See Table 1.7 “Product List” for the operating temperature. 3. The CEC function indicates circuitry which supports the transmission and reception of CEC signals standardized by the High-Definition Multimedia Interface (HDMI). HDMI and High-Definition Multimedia Interface are registered trademarks of HDMI Licensing, LLC. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 5 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview Table 1.5 Item CPU Specifications (80-Pin Package) (1/2) Function Central processing unit Specification M16C/60 core (multiplier: 16-bit × 16-bit 32-bit, multiply and accumulate instruction: 16-bit × 16-bit + 32-bit • Number of basic instructions: 91 • Minimum instruction execution time: 31.25 ns (f(BCLK) = 32 MHz, VCC1 = 3.0 to 5.5 V) • Operating modes: Single-chip See Table 1.7 “Product List”. 32-bit) Memory Voltage Detection Clock ROM, RAM, data flash Voltage detector • Power-on reset • 3 voltage detection points (detection level of voltage detection 0 and 1 selectable) Clock generator • 5 circuits: Main clock, sub clock, low-speed on-chip oscillator (125 kHz), high-speed on-chip oscillator (40 MHz ± 10%), PLL frequency synthesizer • Oscillation stop detection: Main clock oscillation stop detection and reoscillation detection function I/O Ports Interrupts Programmable I/O ports • Frequency divider circuit: Divide ratio selectable from 1, 2, 4, 8, and 16 • Power save: Wait mode, stop mode • Real time clock • CMOS I/O ports: 68, selectable pull-up resistor • N-channel open drain ports: 3 • Interrupt vectors: 70 • External interrupt input: 10 (NMI, INT × 5, key input × 4) • Interrupt priority levels: 7 15 bits × 1 (with prescaler) Automatic reset start function selectable Watchdog Timer DMA DMAC • 4 channels, cycle steal mode • Trigger sources: 43 • Transfer modes: 2 (single transfer, repeat transfer) 16-bit timer × 5 Timer mode × 5 Event counter mode, one shot timer mode, pulse width modulation (PWM) mode × 3 Event counter two-phase pulse signal processing (two-phase encoder input) × 2 Programmable output mode × 1 16-bit timer × 6 Timer mode × 6 Event counter mode, pulse period measurement mode, pulse width measurement mode × 5 Count: second, minute, hour, day of week 8 bits × 2 Timer Timer A Timer B Real-time clock PWM function Remote control signal receiver • 2 circuits • 4 wave pattern matchings (differentiate wave pattern for headers, data 0, data 1, and special data) • 6-byte receive buffer (1 circuit) • Operating frequency of 32 kHz REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 6 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview Table 1.6 Item Serial Interface Specifications (80-Pin Package) (2/2) Function UART0 to UART2, UART5 Specification Clock synchronous/asynchronous × 3 channels I2C-bus, IEBus (1), special mode 2 SIM (UART2) Clock asynchronous × 1 channel I2C-bus, IEBus (1) Clock synchronization only × 2 channels (SI/O3 is used for transmission only) CEC transmit/receive, arbitration lost detection, ACK signal generation, operation frequency of 32 kHz 10-bit resolution × 26 channels, including sample and hold function Conversion time: 1.72 µs 8-bit resolution × 2 CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant Programming and erasure power supply voltage: 2.7 to 5.5 V Programming and erasure endurance: 1,000 times (program ROM 1, program ROM 2)/10,000 times (data flash) Program security: ROM code protect, ID code check Functions on-chip debug, on-board flash rewrite function, address match × 4 25 MHz/VCC1 = 2.7 to 5.5 V 32 MHz/VCC1 = 3.0 to 5.5 V TBD (32 MHz/VCC1 = 3 V) TBD (VCC1 = 3 V, in stop mode) -20°C to 85°C, -40°C to 85°C (2) 80-pin LQFP: PLQP080JA-A (Previous package code: FP-80W) SI/O3, SI/O4 Multi-master I2C bus interface 1 channel CEC function (3) A/D Converter D/A Converter CRC Calculator Flash Memory Debug Function Operation Frequency/Supply Voltage Current Consumption Operating Temperature Package Notes: 1. IEBus is a registered trademark of NEC Electronics Corporation. 2. See Table 1.7 “Product List” for the operating temperature. 3. The CEC function indicates circuitry which supports the transmission and reception of CEC signals standardized by the High-Definition Multimedia Interface (HDMI). HDMI and High-Definition Multimedia Interface are registered trademarks of HDMI Licensing, LLC. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 7 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview 1.3 Product List Table 1.7 lists product information. Figure 1.1 shows Correspondence of Part No., with Memory Size and Package, and Figure 1.2 shows Marking Diagram of Flash Memory Package (Top View). Table 1.7 Product List Part No. Program ROM1 ROM Capacity Program Data Flash ROM2 RAM Capacity Remarks Package Code Operating temperature -20°C to 85°C Operating temperature -40°C to 85°C Operating temperature -20°C to 85°C Operating temperature -40°C to 85°C Operating temperature -20°C to 85°C Operating temperature -40°C to 85°C Operating temperature -20°C to 85°C Operating temperature -40°C to 85°C Operating temperature -20°C to 85°C Operating temperature -40°C to 85°C Operating temperature -20°C to 85°C Operating temperature -40°C to 85°C R5F36506NFA (P) PRQP0100JD-B R5F36506NFB (P) PLQP0100KB-A R5F36526NFP (P) PLQP0080JA-A 4 Kbytes 128 Kbytes 16 Kbytes 12 Kbytes × 2 blocks R5F36506DFA (P) PRQP0100JD-B R5F36506DFB (P) PLQP0100KB-A R5F36526DFP (P) PLQP0080JA-A R5F3651ENFC (P) PLQP0128KB-A R5F3650ENFA (P) PRQP0100JD-B R5F3650ENFB (P) PLQP0100KB-A 4 Kbytes 256 Kbytes 16 Kbytes 20 Kbytes × 2 blocks R5F3651EDFC (P) PLQP0128KB-A R5F3650EDFA (D) PRQP0100JD-B R5F3650EDFB (D) PLQP0100KB-A R5F3651KNFC (P) PLQP0128KB-A R5F3650KNFB (P) PRQP0100JD-B R5F3650KNFA (P) PLQP0100KB-A 4 Kbytes 384 Kbytes 16 Kbytes 31 Kbytes × 2 blocks R5F3651KDFC (P) PLQP0128KB-A R5F3650KDFB (P) PRQP0100JD-B R5F3650KDFA (P) PLQP0100KB-A R5F3651MNFC (P) PLQP0128KB-A R5F3650MNFA (P) PRQP0100JD-B R5F3650MNFB (P) PLQP0100KB-A 4 Kbytes 512 Kbytes 16 Kbytes 31 Kbytes × 2 blocks R5F3651MDFC (P) PLQP0128KB-A R5F3650MDFA (P) PRQP0100JD-B R5F3650MDFB (P) PLQP0100KB-A R5F3651RNFC (P) PLQP0128KB-A R5F3650RNFB (P) PRQP0100JD-B R5F3650RNFA (P) PLQP0100KB-A 4 Kbytes 640 Kbytes 16 Kbytes 47 Kbytes × 2 blocks R5F3651RDFC (P) PLQP0128KB-A R5F3650RDFB (P) PRQP0100JD-B R5F3650RDFA (P) PLQP0100KB-A R5F3651TNFC (D) PLQP0128KB-A R5F3650TNFA (P) PRQP0100JD-B R5F3650TNFB (P) PLQP0100KB-A 4 Kbytes 768 Kbytes 16 Kbytes 47 Kbytes × 2 blocks R5F3651TDFC (D) PLQP0128KB-A R5F3650TDFA (P) PRQP0100JD-B R5F3650TDFB (P) PLQP0100KB-A (D): Under development (P): Planning Note: 1. Previous package codes are as follows. PLQP0128KB-A: 128P6Q-A, PRQP0100JD-B: 100P6F-A, PLQP0100KB-A: 100P6Q-A, PLQP0080JA-A: FP-80W REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 8 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview Part No. R 5 F 3 65 0 6 D FA Package type FC: Package PLQP0128KB-A (128P6Q-A) FA: Package PRQP0100JD-B (100P6F-A) FB: Package PLQP0100KB-A (100P6Q-A) FP: Package PLQP0080JA-A (FP-80W) Property Code N: Operating temperature -20°C to 85°C D: Operating temperature -40°C to 85°C Memory capacity Program ROM 1/RAM 6 : 128 Kbytes/12 Kbytes E : 256 Kbytes/20 Kbytes K : 384 Kbytes/31 Kbytes M : 512 Kbytes/31 Kbytes R : 640 Kbytes/47 Kbytes T : 768 Kbytes/47 Kbytes Number of pins 0 : 100 pins 1 : 128 pins 2 : 80 pins M16C/65 Group 16-bit MCU Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.1 Correspondence of Part No., with Memory Size and Package M1 6 C R 5 F 3 6 5 0 6 DF A XXXXXXX Type No. (See Figure 1.1 Correspondence of Part No., Memory Size, and Package.) Date code seven digits Figure 1.2 Marking Diagram of Flash Memory Package (Top View) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 9 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview 1.4 Block Diagram Figure 1.3 to Figure 1.5 show block diagrams. 8 Port P0 8 Port P1 8 Port P2 8 Port P3 8 Port P4 8 Port P5 8 Port P12 8 Port P13 VCC2 ports Internal peripheral functions Timer (16-bit) Outputs (timer A) : 5 Inputs (timer B) : 6 Three-phase motor control circuit UART or clock synchronous serial I/O (6 channels) Clock synchronous serial I/O (8 bits x 2 channels) Multi-master I2C bus interface System clock generator XIN-XOUT XCIN-XCOUT PLL frequency synthesizer On-chip oscillator (125 kHz) High-speed on-chip oscillator (1 channel) CEC function DMAC (4 channels) CRC arithmetic circuit (CCITT or CRC-16) Voltage detection circuit Power-on reset On-chip debugger Real time clock PWM function (8 bits X 2) Remote control signal receiver (2 circuits) Watchdog timer (15 bits X 1) A/D converter (10 bits X 26 channels) D/A converter (8 bits X 2 channels) M16C/60 series CPU core R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG Memory ROM(1) RAM(2) Multiplier VCC1 ports Port P14 2 Port P11 8 Port P10 8 Port P9 8 Port P8 8 Port P7 8 Port P6 8 Notes : 1. ROM size depends on MCU type. 2. RAM size depends on MCU type. Figure 1.3 Block Diagram (128 pins) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 10 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview 8 Port P0 8 Port P1 8 Port P2 8 Port P3 8 Port P4 8 Port P5 VCC2 ports Internal peripheral functions Timer (16-bit) Outputs (timer A) : 5 Inputs (timer B) : 6 Three-phase motor control circuit UART or clock synchronous serial I/O (6 channels) Clock synchronous serial I/O (8 bits x 2 channels) Multi-master I2C bus interface System clock generator XIN-XOUT XCIN-XCOUT PLL frequency synthesizer On-chip oscillator (125 kHz) High-speed on-chip oscillator (1 channel) CEC function DMAC (4 channels) CRC arithmetic circuit (CCITT or CRC-16) Voltage detection circuit Power-on reset On-chip debugger Real time clock PWM function (8 bits X 2) Remote control signal receiver (2 circuits) Watchdog timer (15 bits X 1) A/D converter (10 bits X 26 channels) D/A converter (8 bits X 2 channels) M16C/60 series CPU core R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG Memory ROM(1) RAM(2) Multiplier VCC1 ports Port P10 8 Port P9 8 Port P8 8 Port P7 8 Port P6 8 Notes : 1. ROM size depends on MCU type. 2. RAM size depends on MCU type. Figure 1.4 Block Diagram (100 pins) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 11 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview 8 Port P0 8 Port P2 8 Port P3 4 Port P4 8 Port P5 VCC1 ports Internal peripheral functions Timer (16-bit) Outputs (timer A) : 5 Inputs (timer B) : 6 UART or clock synchronous serial I/O (3 channels) UART (1 channel) Clock synchronous serial I/O (8 bits x 2 channels) Multi-master I2C bus interface System clock generator XIN-XOUT XCIN-XCOUT PLL frequency synthesizer On-chip oscillator (125 kHz) High-speed on-chip oscillator DMAC (4 channels) CRC arithmetic circuit (CCITT or CRC-16) Voltage detection circuit Power-on reset On-chip debugger Real time clock PWM function (8 bits X 2) Remote control signal receiver (2 circuits) (1 channel) CEC function Watchdog timer (15 bits X 1) A/D converter (10 bits X 26 channels) D/A converter (8 bits X 2 channels) M16C/60 series CPU core R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG Memory ROM(1) RAM(2) Multiplier VCC1 ports Port P10 8 Port P9 7 Port P8 8 Port P7 4 Port P6 8 Notes : 1. ROM size depends on MCU type. 2. RAM size depends on MCU type. Figure 1.5 Block Diagram (80 pins) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 12 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview 1.5 Pin Assignments Figure 1.6 to Figure 1.9 show pin assignments (top view). Table 1.8 to Table 1.14 list pin names. (3) P1_1/CLK6/D9 P1_2/RXD6/SCL6/D10 P1_3/TXD6/SDA6/D11 P1_4/D12 P1_5/INT3/IDV/D13 P1_6/INT4/IDW/D14 P1_7/INT5/IDU/D15 P2_0/AN2_0/A0, [A0/D0], A0 P2_1/AN2_1/A1, [A1/D1], [A1/D0] P2_2/AN2_2/A2, [A2/D2], [A2/D1] P2_3/AN2_3/A3, [A3/D3], [A3/D2] P2_4/INT6/AN2_4/A4, [A4/D4], [A4/D3] P2_5/INT7/AN2_5/A5, [A5/D5], [A5/D4] P2_6/AN2_6/A6, [A6/D6], [A6/D5] P2_7/AN2_7/A7, [A7/D7], [A7/D6] VSS P3_0/A8 [A8/D7] VCC2 P12_0 P12_1 P12_2 P12_3 P12_4 P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17 P4_2/A18 P4_3/A19 P4_4/CTS7/RTS7/CS0 P4_5/CLK7/CS1 P4_6/PWM0/RXD7/SCL7/CS2 P4_7/PWM1/TXD7/SDA7/CS3 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 P1_0/CTS6/RTS6/D8 P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P11_7 P11_6 P11_5 P11_4 P11_3 P11_2 P11_1 P11_0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 1 VCC2 ports 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 M16C/65 Group PLQP0128KB-A (128P6Q-A) (top view) VCC1 ports 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 P12_5 P12_6 P12_7 P5_0/WRL/WR P5_1/WRH/BHE P5_2/RD P5_3/BCLK P13_0 P13_1 P13_2 P13_3 P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT P13_4 P13_5 P13_6 P13_7 P6_0/RTCOUT/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 VSS Notes: 1. N-channel open drain output. 2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions. 3. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two separate functional signals. Figure 1.6 Pin Assignment (128 pins) (Top View) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 13 of 791 VREF AVCC P9_7/ADTRG/SIN4 P9_6/ANEX1/SOUT4 P9_5/ANEX0/CLK4 P9_4/DA1/TB4IN/PWM1 P9_3/DA0/TB3IN/PWM0 P9_2/TB2IN/PMC0/SOUT3 P9_1/TB1IN/PMC1/SIN3 P9_0/TB0IN/CLK3 P14_1 P14_0 BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI/SD/CEC(1) P8_4/INT2/ZP P8_3/INT1 P8_2/INT0 P8_1/TA4IN/U/CTS5/RTS5 P8_0/TA4OUT/U/RXD5/SCL5 P7_7/TA3IN/CLK5 P7_6/TA3OUT/TXD5/SDA5 P7_5/TA2IN/W P7_4/TA2OUT/W P7_3/CTS2/RTS2/TA1IN/V P7_2/CLK2/TA1OUT/V P7_1/RXD2/SCL2/SCLMM/TA0IN/TB5IN(1) P7_0/TXD2/SDA2/SDAMM/TA0OUT(1) P6_7/TXD1/SDA1 VCC1 P6_6/RXD1/SCL1 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview Table 1.8 Pin Names, 128-Pin Package (1/3) I/O Pin for Peripheral Function Port Interrupt Timer Serial interface A/D converter, Bus Control Pin D/A converter Pin No. Control Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VREF AVCC P9_7 P9_6 P9_5 P9_4 P9_3 P9_2 P9_1 P9_0 P14_1 P14_0 BYTE CNVSS XCIN XCOUT RESET XOUT VSS XIN VCC1 SIN4 SOUT4 CLK4 TB4IN/PWM1 TB3IN/PWM0 TB2IN/PMC0 TB1IN/PMC1 TB0IN ADTRG ANEX1 ANEX0 DA1 DA0 SOUT3 SIN3 CLK3 P8_7 P8_6 P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7 VCC1 P6_6 VSS P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 P13_7 P13_6 P13_5 P13_4 P5_7 NMI INT2 INT1 INT0 SD ZP CEC TA4IN/U TA4OUT/U TA3IN TA3OUT TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V TA0IN/TB5IN TA0OUT CTS5/RTS5 RXD5/SCL5 CLK5 TXD5/SDA5 CTS2/RTS2 CLK2 RXD2/SCL2/SCLMM TXD2/SDA2/SDAMM TXD1/SDA1 RXD1/SCL1 CLK1 CTS1/RTS1/CTS0/CLKS1 TXD0/SDA0 RXD0/SCL0 CLK0 CTS0/RTS0 RTCOUT CLKOUT RDY REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 14 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview Table 1.9 Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Names, 128-Pin Package (2/3) Control Pin I/O Pin for Peripheral Function Port P5_6 P5_5 P5_4 P13_3 P13_2 P13_1 P13_0 P5_3 P5_2 P5_1 P5_0 P12_7 P12_6 P12_5 P4_7 P4_6 P4_5 P4_4 P4_3 P4_2 P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 P12_4 P12_3 P12_2 P12_1 P12_0 Interrupt Timer Serial interface A/D converter, D/A converter Bus Control Pin ALE HOLD HLDA BCLK RD WRH/BHE WRL/WR PWM1 PWM0 TXD7/SDA7 RXD7/SCL7 CLK7 CTS7/RTS7 CS3 CS2 CS1 CS0 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 VCC2 P3_0 VSS P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 AN2_7 AN2_6 AN2_5 AN2_4 AN2_3 AN2_2 AN2_1 AN2_0 IDU IDW IDV TXD6/SDA6 A7, [A7/D7], [A7/D6] A6, [A6/D6], [A6/D5] A5, [A5/D5], [A5/D4] A4[A4/D4], [A4/D3] A3, [A3/D3], [A3/D2] A2, [A2/D2], [A2/D1] A1, [A1/D1], [A1/D0] A0, [A0/D0], A0 D15 D14 D13 D12 D11 A8, [A8/D7] INT7 INT6 INT5 INT4 INT3 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 15 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview Table 1.10 Pin No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Control Pin Pin Names, 128-Pin Package (3/3) I/O Pin for Peripheral Function Port P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 P11_7 P11_6 P11_5 P11_4 P11_3 P11_2 P11_1 P11_0 P10_7 P10_6 P10_5 P10_4 P10_3 P10_2 P10_1 Interrupt Timer Serial interface RXD6/SCL6 CLK6 CTS6/RTS6 AN0_7 AN0_6 AN0_5 AN0_4 AN0_3 AN0_2 AN0_1 AN0_0 A/D converter, D/A converter D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Bus Control Pin KI3 KI2 KI1 KI0 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 AVSS P10_0 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 16 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview (3) P1_0/CTS6/RTS6/D8 P1_1/CLK6/D9 P1_2/RXD6/SCL6/D10 P1_3/TXD6/SDA6/D11 P1_4/D12 P1_5/INT3/IDV/D13 P1_6/INT4/IDW/D14 P1_7/INT5/IDU/D15 P2_0/AN2_0/A0, [A0/D0], A0 P2_1/AN2_1/A1, [A1/D1], [A1/D0] P2_2/AN2_2/A2, [A2/D2], [A2/D1] P2_3/AN2_3/A3, [A3/D3], [A3/D2] P2_4/INT6/AN2_4/A4, [A4/D4], [A4/D3] P2_5/INT7/AN2_5/A5, [A5/D5], [A5/D4] P2_6/AN2_6/A6, [A6/D6], [A6/D5] P2_7/AN2_7/A7, [A7/D7], [A7/D6] VSS P3_0/A8 [A8/D7] VCC2 P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17 P4_2/A18 P4_3/A19 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 VREF AVCC P9_7/ADTRG/SIN4 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 2 3 4 5 6 7 8 50 VCC2 ports 49 48 47 46 M16C/65 Group PRQP0100JD-B (100P6F-A) (top view) VCC1 ports 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P4_4/CTS7/RTS7/CS0 P4_5/CLK7/CS1 P4_6/PWM0/RXD7/SCL7/CS2 P4_7/PWM1/TXD7/SDA7/CS3 P5_0/WRL/WR P5_1/WRH/BHE P5_2/RD P5_3/BCLK P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT P6_0/RTCOUT/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 Notes: 1. N-channel open drain output. 2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions. 3. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two separate functional signals. Figure 1.7 Pin Assignment (100 pins) (Top View) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 17 of 791 P9_6/ANEX1/SOUT4 P9_5/ANEX0/CLK4 P9_4/DA1/TB4IN/PWM1 P9_3/DA0/TB3IN/PWM0 P9_2/TB2IN/PMC0/SOUT3 P9_1/TB1IN/PMC1/SIN3 P9_0/TB0IN/CLK3 BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI/SD/CEC (1) P8_4/INT2/ZP P8_3/INT1 P8_2/INT0 P8_1/TA4IN/U/CTS5/RTS5 P8_0/TA4OUT/U/RXD5/SCL5 P7_7/TA3IN/CLK5 P7_6/TA3OUT/TXD5/SDA5 P7_5/TA2IN/W P7_4/TA2OUT/W P7_3/CTS2/RTS2/TA1IN/V P7_2/CLK2/TA1OUT/V P7_1/RXD2/SCL2/SCLMM/TA0IN/TB5IN (1) P7_0/TXD2/SDA2/SDAMM/TA0OUT (1) Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview (3) P1_3/TXD6/SDA6/D11 P1_4/D12 P1_5/INT3/IDV/D13 P1_6/INT4/IDW/D14 P1_7/INT5/IDU/D15 P2_0/AN2_0/A0, [A0/D0], A0 P2_1/AN2_1/A1, [A1/D1], [A1/D0] P2_2/AN2_2/A2, [A2/D2], [A2/D1] P2_3/AN2_3/A3, [A3/D3], [A3/D2] P2_4/INT6/AN2_4/A4, [A4/D4], [A4/D3] P2_5/INT7/AN2_5/A5, [A5/D5], [A5/D4] P2_6/AN2_6/A6, [A6/D6], [A6/D5] P2_7/AN2_7/A7, [A7/D7], [A7/D6] VSS P3_0/A8 [A8/D7] VCC2 P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 P1_2/RXD6/SCL6/D10 P1_1/CLK6/D9 P1_0/CTS6/RTS6/D8 P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 VREF AVCC P9_7/ADTRG/SIN4 P9_6/ANEX1/SOUT4 P9_5/ANEX0/CLK4 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 53 52 51 50 VCC2 ports 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 M16C/65 Group PLQP0100KB-A (100P6Q-A) (top view) VCC1 ports P4_2/A18 P4_3/A19 P4_4/CTS7/RTS7/CS0 P4_5/CLK7/CS1 P4_6/PWM0/RXD7/SCL7/CS2 P4_7/PWM1/TXD7/SDA7/CS3 P5_0/WRL/WR P5_1/WRH/BHE P5_2/RD P5_3/BCLK P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT P6_0/RTCOUT/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 P7_0/TXD2/SDA2/SDAMM/TA0OUT (1) P7_1/RXD2/SCL2/SCLMM/TA0IN/TB5IN (1) P7_2/CLK2/TA1OUT/V 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Notes: 1. N-channel open drain output. 2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions. 3. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two separate functional signals. Figure 1.8 Pin Assignment (100 pins) (Top View) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 18 of 791 P9_4/DA1/TB4IN/PWM1 P9_3/DA0/TB3IN/PWM0 P9_2/TB2IN/PMC0/SOUT3 P9_1/TB1IN/PMC1/SIN3 P9_0/TB0IN/CLK3 BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI/SD/CEC (1) P8_4/INT2/ZP P8_3/INT1 P8_2/INT0 P8_1/TA4IN/U/CTS5/RTS5 P8_0/TA4OUT/U/RXD5/SCL5 P7_7/TA3IN/CLK5 P7_6/TA3OUT/TXD5/SDA5 P7_5/TA2IN/W P7_4/TA2OUT/W P7_3/CTS2/RTS2/TA1IN/V 24 25 1 2 3 4 5 6 7 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview Table 1.11 Pin No. FA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 FB 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Names, 100-Pin Package (1/2) I/O Pin for Peripheral Function Control Pin Port P9_6 P9_5 P9_4 P9_3 P9_2 P9_1 P9_0 BYTE CNVSS XCIN XCOUT RESET XOUT VSS XIN VCC1 Interrupt Timer Serial interface SOUT4 CLK4 TB4IN/PWM1 TB3IN/PWM0 TB2IN/PMC0 TB1IN/PMC1 TB0IN A/D converter, D/A converter ANEX1 ANEX0 DA1 DA0 Bus Control Pin SOUT3 SIN3 CLK3 P8_7 P8_6 P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7 P6_6 P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 P5_7 P5_6 P5_5 P5_4 P5_3 P5_2 P5_1 P5_0 P4_7 P4_6 P4_5 P4_4 NMI INT2 INT1 INT0 SD ZP CEC TA4IN/U TA4OUT/U TA3IN TA3OUT TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V TA0IN/TB5IN TA0OUT CTS5/RTS5 RXD5/SCL5 CLK5 TXD5/SDA5 RTCOUT CTS2/RTS2 CLK2 RXD2/SCL2/SCLMM TXD2/SDA2/SDAMM TXD1/SDA1 RXD1/SCL1 CLK1 CTS1/RTS1/CTS0/ CLKS1 TXD0/SDA0 RXD0/SCL0 CLK0 CTS0/RTS0 RDY ALE HOLD HLDA BCLK RD WRH/BHE WRL/WR CS3 CS2 CS1 CS0 CLKOUT PWM1 PWM0 TXD7/SDA7 RXD7/SCL7 CLK7 CTS7/RTS7 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 19 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview Table 1.12 Pin No. FA 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 FB 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 Pin Names, 100-Pin Package (2/2) Control Pin Port P4_3 P4_2 P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 VCC2 P3_0 VSS P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 P10_7 P10_6 P10_5 P10_4 P10_3 P10_2 P10_1 AVSS P10_0 VREF AVCC P9_7 SIN4 ADTRG Interrupt I/O Pin for Peripheral Function A/D converter, Timer Serial interface D/A converter A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 Bus Control Pin A8, [A8/D7] AN2_7 AN2_6 AN2_5 AN2_4 AN2_3 AN2_2 AN2_1 AN2_0 IDU IDW IDV TXD6/SDA6 RXD6/SCL6 CLK6 CTS6/RTS6 AN0_7 AN0_6 AN0_5 AN0_4 AN0_3 AN0_2 AN0_1 AN0_0 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 A7, [A7/D7], [A7/D6] A6, [A6/D6], [A6/D5] A5, [A5/D5], [A5/D4] A4, [A4/D4], [A4/D3] A3, [A3/D3], [A3/D2] A2, [A2/D2], [A2/D1] A1, [A1/D1], [A1/D0] A0, [A0/D0], A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 INT7 INT6 INT5 INT4 INT3 KI3 KI2 KI1 KI0 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 20 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview P2_4/INT6/AN2_4 P2_5/INT7/AN2_5 P0_7/AN0_7 P2_0/AN2_0 P2_1/AN2_1 P2_2/AN2_2 P2_3/AN2_3 P2_6/AN2_6 P2_7/AN2_7 P3_0 P3_1 P3_2 P3_3 P3_4 P3_5 P3_6 P3_7 P4_0 P4_1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P4_2 P0_6/AN0_6 P0_5/AN0_5 P0_4/AN0_4 P0_3/AN0_3 P0_2/AN0_2 P0_1/AN0_1 P0_0/AN0_0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 VREF AVCC P9_7/ADTRG/SIN4 P9_6/ANEX1/SOUT4 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 M16C/65 Group PLQP0080JA-A (FP-80W) (top view) 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P4_3 P5_0 P5_1 P5_2 P5_3 P5_4 P5_5 P5_6 P5_7/CLKOUT P6_0/RTCOUT/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 P7_0/TXD2/SDA2/TA0OUT/SDAMM (1) P7_1/RXD2/SCL2/TA0IN/TB5IN/SCLMM (1) P7_6/TA3OUT/TXD5/SDA5 P9_0/TB0IN/CLK3 CNVSS(BYTE) Notes: 1. N-channel open drain output. 2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions. Figure 1.9 Pin Assignment (80 pins) (Top View) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 21 of 791 P8_0/TA4OUT/RXD5/SCL5 P9_3/DA0/TB3IN/PWM0 P9_2/TB2IN/PMC0/SOUT3 P8_2/INT0 P8_1/TA4IN/CTS5/RTS5 P9_4/DA1/TB4IN/PWM1 P8_5/NMI/SD/CEC (1) P9_5/ANEX0/CLK4 P7_7/TA3IN/CLK5 VSS P8_7/XCIN XIN P8_4/INT2/ZP XOUT P8_6/XCOUT RESET VCC1 P8_3/INT1 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview Table 1.13 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Names, 80-Pin Package (1/2) I/O Pin for Peripheral Function Control Pin Port P9_5 P9_4 P9_3 P9_2 P9_0 Interrupt Timer TB4IN/PWM1 TB3IN/PWM0 TB2IN/PMC0 TB0IN Serial interface CLK4 A/D converter, D/A converter ANEX0 DA1 DA0 SOUT3 CLK3 CNVSS XCIN XCOUT RESET XOUT VSS XIN VCC1 P8_7 P8_6 P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_1 P7_0 P6_7 P6_6 P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 P5_7 P5_6 P5_5 P5_4 P5_3 P5_2 P5_1 P5_0 P4_3 NMI INT2 INT1 INT0 SD ZP CEC TA4IN TA4OUT TA3IN TA3OUT TA0IN/TB5IN TA0OUT RTCOUT CTS5/RTS5 RXD5/SCL5 SCL5 TXD5/SDA5 RXD2/SCL2/SCLMM TXD2/SDA2/SDAMM TXD1/SDA1 RXD1/SCL1 CLK1 CTS1/RTS1/CTS0/ CLKS1 TXD0/SDA0 RXD0/SCL0 CLK0 CTS0/RTS0 CLKOUT REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 22 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview Table 1.14 Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Names, 80-Pin Package (2/2) I/O Pin for Peripheral Function Control Pin Port P4_2 P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 P3_0 P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 P10_7 P10_6 P10_5 P10_4 P10_3 P10_2 P10_1 Interrupt Timer Serial interface A/D converter, D/A converter INT7 INT6 KI3 KI2 KI1 KI0 AN2_7 AN2_6 AN2_5 AN2_4 AN2_3 AN2_2 AN2_1 AN2_0 AN0_7 AN0_6 AN0_5 AN0_4 AN0_3 AN0_2 AN0_1 AN0_0 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 AVSS P10_0 VREF AVCC P9_7 P9_6 SIN4 SOUT4 ADTRG ANEX1 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 23 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview 1.6 Pin Functions Pin Functions (128-Pin Package) (1/3) Pin Name VCC1 VCC2 VSS AVCC AVSS RESET Table 1.15 Power supply input Analog power supply input Reset input CNVSS Signal Name I/O I Power Supply - Description Apply 2.7 to 5.5 V to pins VCC1 and VCC2 (VCC1 ≥ VCC2) and 0 V to the VSS pin. (1) Apply the power supply for the A/D converter. Connect the AVCC pin to VCC1. Connect the AVSS pin to VSS. Low active input pin. Driving this pin low resets the MCU. Input pin to switch processor mode. Connect the CNVSS pin to VSS via a resistor to start up after a reset in single-chip mode. To start up in microprocessor mode, connect it to VCC1. I I I VCC1 VCC1 VCC1 CNVSS External data bus width select input Bus control pins BYTE I VCC1 Input pin to select the data bus of the external area. The data bus is 16 bits when it is low and 8 bits when it is high. This pin must be fixed either high or low. Connect the BYTE pin to VSS in single-chip mode. Inputs or outputs data (D0 to D7) while accessing an external area with separate bus Inputs or outputs data (D8 to D15) while accessing an external area with 16-bit separate bus Outputs address bits A0 to A19 Inputs or outputs data (D0 to D7) and outputs address bits (A0 to A7) by timesharing, while accessing an external area with 8-bit multiplexed bus Inputs or outputs data (D0 to D7) and outputs address bits (A1 to A8) by timesharing, while accessing an external area with 16-bit multiplexed bus Outputs chip-select signals CS0 to CS3 to specify an external area Low active output pins. Outputs WRL, WRH, (WR, BHE), RD signals. WRL and WRH can be switched with BHE and WR by a program. • WRL, WRH and RD selected If the external data bus is 16 bits, data is written to an even address in external area when WRL is driven low. Data is written to an odd address when WRH is driven low. Data is read when RD is driven low. • WR, BHE and RD selected Data is written to external area when WR is driven low. Data in external area is read when RD is driven low. An odd address is accessed when BHE is driven low. Select WR, BHE, and RD for external 8-bit data bus. Output ALE signal to latch address. Low active input pin. The MCU is placed in hold state while the HOLD pin is driven low. Low active output pin. In a hold state, HLDA outputs a lowlevel signal. Low active input pin. The MCU bus is placed in wait state while the RDY pin is driven low. D0 to D7 D8 to D15 A0 to A19 A0/D0 to A7/D7 A1/D0 to A8/D7 CS0 to CS3 WRL/WR WRH/BHE RD I/O I/O O I/O VCC2 VCC2 VCC2 VCC2 I/O VCC2 O O VCC2 VCC2 ALE HOLD HLDA RDY O I O I VCC2 VCC2 VCC2 VCC2 Power supply: VCC2 is used to supply power to external bus associated pins. The dual power supply configuration allows VCC2 to interface at a different voltage than VCC1. Note: 1. VCC1 is hereinafter referred to as VCC unless otherwise noted. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 24 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview Table 1.16 Pin Functions (128-Pin Package) (2/3) Pin Name XIN XOUT XCIN XCOUT BCLK CLKOUT INT0 to INT2 INT3 to INT7 NMI KI0 to KI3 Signal Name Main clock input Main clock output Sub clock input Sub clock output BCLK output Clock output INT interrupt input NMI interrupt input I/O I O I O O O I I I I I/O I I I O I I O O I I I O O I/O I/O I I O O O Power Supply VCC1 VCC1 VCC1 VCC1 VCC2 VCC2 VCC1 VCC2 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC2 VCC1 VCC1, VCC2 VCC1 VCC1 VCC2 VCC1 VCC2 VCC1 VCC2 VCC1 VCC2 VCC1 VCC2 VCC1 Serial data input pins Description I/O pins for the main clock oscillator. Connect a ceramic resonator or crystal oscillator between XIN and XOUT (1). To apply an external clock, connect it to XIN and leave XOUT open. I/O pins for a sub clock oscillator. Connect a crystal oscillator between XCIN and XCOUT (1). To apply an external clock, connect it to XCIN and leave XCOUT open. Outputs BCLK signal This pin outputs the clock having the same frequency as fC, f8, or f32. Input pins for INT interrupt Input pin for NMI interrupt Input pins for key input interrupt Timer A0 to A4 I/O pins (TA0OUT as an output pin is N-channel open drain output) Timer A0 to A4 input pins Input pin for Z-phase Timer B0 to B5 input pins Output pins for three-phase motor control timer output Forced cutoff input Input for position data Output for real time clock PWM output Input for remote control signal receiver Input pins to control data transmission Key input interrupt input Timer A TA0OUT to TA4OUT TA0IN to TA4IN ZP Timer B Three-phase motor control timer TB0IN to TB5IN U, U, V, V, W, W SD IDU, IDV, IDW Real time clock output PWM output RTCOUT PWM0, PWM1 Remote control PMC0, PMC1 signal receiver input Serial interface UART0 to UART2, UART5 to UART7 CTS0 to CTS2, CTS5 CTS6, CTS7 RTS0 to RTS2, RTS5 RTS6, RTS7 Output pins to control data reception CLK0 to CLK2, CLK5 CLK6, CLK7 RXD0 to RXD2, RXD5 RXD6, RXD7 TXD0 to TXD2, TXD5 TXD6, TXD7 CLKS1 Transmit/receive clock I/O pins Serial data output pins (2) Output pin for transmit/receive clock multiple-pin output function Notes: 1. Contact the oscillator manufacturer regarding the oscillation characteristics. 2. TXD2, SDA2, and SCL2 are N-channel open drain output pins. TXDi (i = 0, 1, 5 to 7), SDAi, and SCLi can be selected as CMOS output pins or N-channel open drain output pins by a program. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 25 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview Table 1.17 Signal Name UART0 to UART2, UART5 to UART7 I2C mode Pin Functions (128-Pin Package) (3/3) Pin Name SDA0 to SDA2, SDA5 SDA6, SDA7 SCL0 to SCL2, SCL5 SCL6, SCL7 CLKS3, CLKS4 SIN3, SIN4 SOUT3, SOUT4 I/O I/O I/O I/O I/O I/O I O I/O I/O I/O I I I I I O I/O Power Supply VCC1 VCC2 VCC1 VCC2 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC2 VCC1 VCC1 VCC1 VCC2 Input pin for an external A/D trigger Extended analog input pin for the A/D converter Output pin for the D/A converter 8-bit CMOS I/O ports. A direction register determines whether each pin is used as an input port or an output port. A pull-up resistor may be enabled or disabled for input ports in 4-bit units. Transmit/receive clock I/O pins Serial data input pins Serial data output pins Serial data I/O pin (Output is N-channel open drain) Transmit/receive clock I/O pin (Output is N-channel open drain) CEC I/O pin (Output is N-channel open drain) Reference voltage input pins for the A/D converter and D/A converter Analog input pins for the A/D converter I2C mode transmit/receive clock I/O pins Description I2C mode serial data I/O pins Serial interface SI/03, SI/04 Multi-master SDAMM I2C-bus SCLMM Interface CEC I/O CEC Reference VREF voltage input A/D converter AN0 to AN7 AN0_0 to AN0_7 AN2_0 to AN2_7 ADTRG ANEX0, ANEX1 D/A converter I/O port DA0, DA1 P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_7 P12_0 to P12_7 P13_0 to P13_7 P6_0 to P6_7 P7_0 to P7_7 P8_0 to P8_7 P9_0 to P9_7 P10_0 to P10_7 P11_0 to P11_7 P14_0, P14_1 I/O VCC1 8-bit I/O ports having equivalent functions to P0. However, P7_0, P7_1, and P8_5 are N-channel open drain output ports. No pull-up resistor is provided. P8_5 is an input port for verifying the NMI pin level and shares a pin with NMI. I/O VCC1 I/O ports having equivalent functions to P0 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 26 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview Table 1.18 Power supply input Analog power supply input Reset input CNVSS Pin Functions (100-Pin Package) (1/3) Pin Name VCC1 VCC2 VSS AVCC AVSS RESET Signal Name I/O I Power Supply - Description Apply 2.7 to 5.5 V to pins VCC1 and VCC2 (VCC1 ≥ VCC2) and 0 V to the VSS pin. (1) Apply the power supply for the A/D converter. Connect the AVCC pin to VCC1. Connect the AVSS pin to VSS. Low active input pin. Driving this pin low resets the MCU. Input pin to switch processor mode. Connect the CNVSS pin to VSS via a resistor to start up after a reset in single-chip mode. To start up in microprocessor mode, connect it to VCC1. Input pin to select the data bus of the external area. The data bus is 16 bits when it is low, and 8 bits when it is high. This pin must be fixed either high or low. Connect the BYTE pin to VSS in single-chip mode. Inputs or outputs data (D0 to D7) while accessing an external area with separate bus Inputs or outputs data (D8 to D15) while accessing an external area with 16-bit separate bus Outputs address bits A0 to A19 Inputs or outputs data (D0 to D7) and outputs address bits (A0 to A7) by timesharing, while accessing an external area with 8-bit multiplexed bus Inputs or outputs data (D0 to D7) and outputs address bits (A1 to A8) by timesharing, while accessing an external area with 16-bit multiplexed bus Outputs chip-select signals CS0 to CS3 to specify an external area Low active output pins. Outputs WRL, WRH, (WR, BHE), and RD signals. WRL and WRH can be switched with BHE and WR by a program. • WRL, WRH and RD selected If the external data bus is 16 bits, data is written to an even address in an external area when WRL is driven low. Data is written to an odd address when WRH is driven low. Data is read when RD is driven low. • WR, BHE and RD selected Data is written to external area when WR is driven low. Data in an external area is read when RD is driven low. An odd address is accessed when BHE is driven low. Select WR, BHE, and RD for external 8-bit data bus. Outputs ALE signal to latch address. Low active input pin. The MCU is placed in a hold state while the HOLD pin is driven low. Low active output pin. In a hold state, HLDA outputs a lowlevel signal. Low active input pin. The MCU bus is placed in a wait state while the RDY pin is driven low. I I I VCC1 VCC1 VCC1 CNVSS External data bus width select input Bus control pins BYTE I VCC1 D0 to D7 D8 to D15 A0 to A19 A0/D0 to A7/D7 A1/D0 to A8/D7 CS0 to CS3 WRL/WR WRH/BHE RD I/O I/O O I/O VCC2 VCC2 VCC2 VCC2 I/O VCC2 O O VCC2 VCC2 ALE HOLD HLDA RDY O I O I VCC2 VCC2 VCC2 VCC2 Power supply: VCC2 is used to supply power to external bus associated pins. The dual power supply configuration allows VCC2 to interface at a different voltage than VCC1. Note: 1. VCC1 is hereinafter referred to as VCC unless otherwise noted. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 27 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview Table 1.19 Pin Functions (100-Pin Package) (2/3) Pin Name XIN XOUT XCIN XCOUT BCLK CLKOUT INT0 to INT2 INT3 to INT7 NMI KI0 to KI3 Signal Name Main clock input Main clock output Sub clock input Sub clock output BCLK output Clock output INT interrupt input NMI interrupt input I/O I O I O O O I I I I I/O I I I O I I O O I I I O O I/O I/O I I O O O Power Supply VCC1 VCC1 VCC1 VCC1 VCC2 VCC2 VCC1 VCC2 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC2 VCC1 VCC1, VCC2 VCC1 VCC1 VCC2 VCC1 VCC2 VCC1 VCC2 VCC1 VCC2 VCC1 VCC2 VCC1 Serial data input pins Description I/O pins for the main clock oscillator. Connect a ceramic resonator or crystal oscillator between XIN and XOUT (1). To apply an external clock, connect it to XIN and leave XOUT open. I/O pins for a sub clock oscillator. Connect a crystal oscillator between XCIN and XCOUT (1). To apply an external clock, connect it to XCIN and leave XCOUT open. Outputs BCLK signal This pin outputs the clock having the same frequency as fC, f8, or f32. Input pins for INT interrupt Input pin for NMI interrupt Input pins for key input interrupt Timer A0 to A4 I/O pins (TA0OUT as an output pin is N-channel open drain output) Timer A0 to A4 input pins Input pin for Z-phase Timer B0 to B5 input pins Output pins for three-phase motor control timer output Forced cutoff input Input for position data Output for real time clock PWM output Input for remote control signal receiver Input pins to control data transmission Key input interrupt input Timer A TA0OUT to TA4OUT TA0IN to TA4IN ZP Timer B Three-phase motor control timer TB0IN to TB5IN U, U, V, V, W, W SD IDU, IDV, IDW Real time clock output RTCOUT PWM output PWM0, PWM1 Remote control PMC0, PMC1 signal receiver input Serial interface UART0 to UART2, UART5 to UART7 CTS0 to CTS2, CTS5 CTS6, CTS7 RTS0 to RTS2, RTS5 RTS6, RTS7 Output pins to control data reception CLK0 to CLK2, CLK5 CLK6, CLK7 RXD0 to RXD2, RXD5 RXD6, RXD7 TXD0 to TXD2, TXD5 TXD6, TXD7 CLKS1 Transmit/receive clock I/O pins Serial data output pins (2) Output pin for transmit/receive clock multiple-pin output function Notes: 1. Contact the oscillator manufacturer regarding the oscillation characteristics. 2. TXD2, SDA2, and SCL2 are N-channel open drain output pins. TXDi (i = 0, 1, 5 to 7), SDAi, and SCLi can be selected as CMOS output pins or N-channel open drain output pins by a program. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 28 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview Table 1.20 Signal Name UART0 to UART2, UART5 to UART7 I2C mode Pin Functions (100-Pin Package) (3/3) Pin Name SDA0 to SDA2, SDA5 SDA6, SDA7 SCL0 to SCL2, SCL5 SCL6, SCL7 CLKS3, CLKS4 SIN3, SIN4 SOUT3, SOUT4 I/O I/O I/O I/O I/O I/O I O I/O I/O I/O I I I I I O I/O Power Supply VCC1 VCC2 VCC1 VCC2 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC2 VCC1 VCC1 VCC1 VCC2 Input pin for an external A/D trigger Extended analog input pin for the A/D converter Output pin for the D/A converter 8-bit CMOS I/O ports. A direction register determines whether each pin is used as an input port or an output port. A pull-up resistor may be enabled or disabled for input ports in 4-bit units. Transmit/receive clock I/O pins Serial data input pins Serial data output pins Serial data I/O pin (output is N-channel open drain) Transmit/receive clock I/O pin (output is N-channel open drain) CEC I/O pin (output is N-channel open drain) Reference voltage input pins for the A/D converter and D/A converter Analog input pins for the A/D converter I2C mode transmit/receive clock I/O pins Description I2C mode serial data I/O pins Serial interface SI/03, SI/04 Multi-master SDAMM I2C-bus SCLMM Interface CEC I/O CEC Reference VREF voltage input A/D converter AN0 to AN7 AN0_0 to AN0_7 AN2_0 to AN2_7 ADTRG ANEX0, ANEX1 D/A converter I/O port DA0, DA1 P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_7 P6_0 to P6_7 P7_0 to P7_7 P8_0 to P8_7 P9_0 to P9_7 P10_0 to P10_7 I/O VCC1 8-bit I/O ports having equivalent functions to P0. However, P7_0, P7_1, and P8_5 are N-channel open drain output ports. No pull-up resistor is provided. P8_5 is an input port for verifying the NMI pin level and shares a pin with NMI. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 29 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview Table 1.21 Power supply input Analog power supply input Reset input CNVSS Pin Functions (80-Pin Package) (1/2) Pin Name VCC1 VSS AVCC AVSS RESET Signal Name I/O I I I I Power Supply VCC1 VCC1 VCC1 Description Apply 2.7 to 5.5 V to the VCC1 pin and 0 V to the VSS pin. Apply the power supply for the A/D converter. Connect the AVCC pin to VCC1. Connect the AVSS pin to VSS. Low active input pin. Driving this pin low resets the MCU. Input pin to switch processor mode. Connect the CNVSS pin to VSS via a resistor to start up after a reset in single-chip mode. I/O pins for the main clock oscillator. Connect a ceramic resonator or crystal oscillator between XIN and XOUT (1). To apply an external clock, connect it to XIN and leave XOUT open. I/O pins for a sub clock oscillator. Connect a crystal oscillator between XCIN and XCOUT (1). To apply an external clock, connect it to XCIN and leave XCOUT open. This pin outputs the clock having the same frequency as fC, f8, or f32. Input pins for INT interrupt Input pin for NMI interrupt Input pins for key input interrupt Timer A0, timer A3, timer A4 I/O pins (TA0OUT as an output pin is N-channel open drain output) Timer A0, timer A3, timer A4 input pins CNVSS Main clock input XIN I O I O O I I I I I/O VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 Main clock output XOUT Sub clock input Sub clock output Clock output XCIN XCOUT CLKOUT INT interrupt input INT0 to INT2 INT6, INT7 NMI interrupt input NMI KI0 to KI3 Key input interrupt input Timer A TA0OUT TA3OUT TA4OUT TA0IN, TA3IN, TA4IN ZP I VCC1 I I VCC1 VCC1 Input pin for Z-phase Timer B0, timers B2 to B5 input pins Timer B TB0IN, TB2IN to TB5IN RTCOUT PWM0, PWM1 PMC0 Real time clock output PWM output Remote control signal receiver input O O I VCC1 VCC1 VCC1 Output for real time clock PWM output Input for remote control signal receiver Note: 1. Contact the oscillator manufacturer regarding oscillation characteristics. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 30 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 1. Overview Table 1.22 Pin Functions (80-Pin Package) (2/2) Pin Name CTS0, CTS1, CTS5 RTS0, RTS1, RTS5 Signal Name Serial interface UART0 to UART2, UART5 I/O I O I/O I O O I/O I/O I/O I O I/O I/O I/O I I I I I O I/O Power Supply VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 Description Input pins to control data transmission Output pins to control data reception Transmit/receive clock I/O pins Serial data input pins Serial data output pins (1) Output pin for transmit/receive clock multiple-pin output function I2C mode serial data I/O pins I2C mode transmit/receive clock I/O pins Transmit/receive clock I/O pins Serial data input pins Serial data output pins Serial data I/O pin (output is N-channel open drain) Transmit/receive clock I/O pin (output is N-channel open drain) CEC I/O pin (output is N-channel open drain) Reference voltage input pins for the A/D converter and D/A converter Analog input pins for the A/D converter CLK0, CLK1, CLK5 RXD0 to RXD2, RXD5 TXD0 to TXD2, TXD5 CLKS1 UART0 to UART2, UART5 I2C mode Serial interface SI/03, SI/04 Multi-master Interface CEC I/O Reference voltage input A/D converter I2C-bus SDA0 to SDA2, SDA5 SCL0 to SCL2, SCL5 CLKS3, CLKS4 SIN4 SOUT3, SOUT4 SDAMM SCLMM CEC VREF AN0 to AN7 AN0_0 to AN0_7 AN2_0 to AN2_7 ADTRG Input pin for an external A/D trigger Extended analog input pin for the A/D converter Output pin for the D/A converter 8-bit CMOS I/O ports. A direction register determines whether each pin is used as an input port or an output port. A pull-up resistor may be enabled or disabled for input ports in 4-bit units. P8_5 is an N-channel open drain output port. No pullup resistor is provided. P8_5 is an input port for verifying the NMI pin level and shares a pin with NMI. I/O ports having equivalent functions to P0. However, P7_0 and P7_1 are N-channel open drain output ports. No pull-up resistor is provided. ANEX0, ANEX1 D/A converter I/O port DA0, DA1 P0_0 to P0_7 P2_0 to P2_7 P3_0 to P3_7 P5_0 to P5_7 P6_0 to P6_7 P8_0 to P8_7 P10_0 to P10_7 P4_0 to P4_3 P7_0, P7_1 P7_6, P7_7 P9_0, P9_2 to P9_7 Note: 1. I/O VCC1 TXD2, SDA2, and SCL2 are N-channel open drain output pins. TXDi (i = 0, 1, 5), SDAi, and SCLi can be selected as CMOS output pins or N-channel open drain output pins by a program. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 31 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of thirteen compose a register bank. There are two sets of register banks. b31 b15 b8 b7 b0 R2 R3 R0H(high-order bits of R0) R0L (low-order bits of R0) R1H(high-order bits of R1) R1L (low-order bits of R1) Data Registers (1) R2 R3 A0 A1 FB Address Registers (1) Frame Base Registers (1) b0 b19 b15 INTBH INTBL Interrupt Table Register INTBH is the 4 high-order bits of the INTB register and INTBL is 16 low-order bits. b19 b0 PC b15 b0 Program Counter USP ISP SB b15 b0 User Stack Pointer Interrupt Stack Pointer Static Base Register FLG b15 b8 b7 b0 Flag Register IPL UI OB S Z DC Carry Flag Debug Flag Zero Flag Sign Flag Register Bank Select Flag Overflow Flag Interrupt Enable Flag Stack Pointer Select Flag Reserved Area Processor Interrupt Priority Level Reserved Area Note: 1. These registers compose a register bank. There are two register banks. Figure 2.1 Central Processing Unit Register 2.1 Data Registers (R0, R1, R2, and R3) R0, R1, R2, and R3 are 16-bit registers used for transfer, arithmetic and logic operations. R0 and R1 can be split into high-order (R0H/R1H) and low-order (R0L/R1L) bits to be used separately as 8-bit data registers. R0 can be combined with R2 and used as a 32-bit data register (R2R0). Also, R3R1 is the combination of R3 and R1. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 32 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 2. Central Processing Unit (CPU) 2.2 Address Registers (A0 and A1) A0 and A1 are 16-bit registers used for indirect addressing, relative addressing, transfer, arithmetic and logic operations. A0 can be combined with A1 and used as a 32-bit address register (A1A0). 2.3 Frame Base Register (FB) The FB is a 16-bit register that is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) The INTB is a 20-bit register that indicates the start address of a relocatable interrupt vector table. 2.5 Program Counter (PC) The PC is 20 bits wide and indicates the address of the next instruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) The stack pointers (SP), USP, and ISP are each comprised of 16 bits. The U flag is used to switch between USP and ISP. 2.7 Static Base Register (SB) The SB is a 16-bit register used for SB-relative addressing. 2.8 Flag Register (FLG) The FLG is an 11-bit register that indicates the CPU state. 2.8.1 Carry Flag (C Flag) The C flag retains a carry, borrow, or shift-out bit generated by the arithmetic/logic unit. 2.8.2 Debug Flag (D Flag) The D flag is for debugging only. Set it to 0. 2.8.3 Zero Flag (Z Flag) The Z flag becomes 1 when an arithmetic operation results in 0. Otherwise it becomes 0. 2.8.4 Sign Flag (S Flag) The S flag is set to 1 when an arithmetic operation results in a negative value. Otherwise it is set to 0. 2.8.5 Register Bank Select Flag (B Flag) Register bank 0 is selected when the B flag is set to 0. Register bank 1 is selected when this flag is set to 1. 2.8.6 Overflow Flag (O Flag) The O flag is set to 1 when an arithmetic operation results in an overflow. Otherwise it is set to 0. 2.8.7 Interrupt Enable Flag (I Flag) The I flag enables maskable interrupts. Maskable interrupts are disabled when the I flag is set to 0, and enabled when it is set to 1. The I flag is set to 0 when an interrupt request is acknowledged. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 33 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 2. Central Processing Unit (CPU) 2.8.8 Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is set to 0. USP is selected when the U flag is set to 1. The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt number 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is 3 bits wide and assigns processor interrupt priority levels from 0 to 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled. 2.8.10 Reserved Space Only write 0 to bits assigned as reserved bits. The read value is undefined. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 34 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 3. Address Space 3. 3.1 Address Space Address Space The M16C/65 Group has a 1 Mbyte address space from address 00000h to FFFFFh. Address space is expandable to 4 Mbytes with the memory capacity-enhancing feature. Address 40000h to BFFFFh can be used as external areas from bank 0 to bank 7. Figure 3.1 shows Address Space. The accessible area depends on processor mode and control bit status. Memory expand mode 00000h 00400h Internal RAM Reserved area 04000h 0D000h 0D800h 0E000h 10000h Address space 1 Mbyte 14000h External area 27000h Reserved area 28000h 40000h External area Bank 0 BFFFFh D0000h Reserved area Internal ROM (program ROM1) FFFFFh Notes: 1. Do not access reserved areas. 2. The figure above applies under the following conditions: - The PM13 bit in the PM1 register is set to 0 (addresses from 04000h to 0CFFFh and from 80000h to CFFFFh are used as external areas) - The IRON bit in the PRG2C register is set to 0 (addresses from 40000h to 7FFFFh are used as an external area) Program ROM 1 is allocated from address FFFFFh to lower. 512 Kbytes × 8 External area SFR External area Internal ROM (data flash) Internal ROM (program ROM2) In 4-Mbyte mode When data flash is enabled When program ROM 2 is enabled Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 SFR Internal RAM is allocated from address 00400h to higher. Figure 3.1 Address Space REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 35 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 3. Address Space 3.2 Memory Map Special Function Registers (SFRs) are allocated from address 00000h to 003FFh and from 0D000h to 0D7FFh. Peripheral function control registers are located here. All blank spaces within SFRs are reserved, and should not be accessed by the user. Internal RAM is allocated from address 00400h and higher, with 10 Kbytes of internal RAM addressed from 00400h to 02BFFh. Internal RAM is used not only for data storage, but also for the stack area when subroutines are called or when an interrupt request is acknowledged. The internal ROM is flash memory. Three internal ROM areas are available: data flash, program ROM 1, and program ROM 2. The data flash is addressed from 0E000h to 0FFFFh. This data flash space is used not only for data storage, but also for program storage. Program ROM 2 is assigned addresses 10000h to 13FFFh. Program ROM 1 is assigned addresses FFFFFh and lower, with the 64-Kbyte program ROM 1 space addressed to F0000h to FFFFFh. The special page vectors are assigned addresses FFE00h to FFFD7h. They are used for the JMPS instruction and JSRS instruction. Refer to the M16C/60, M16C/20, M16C/Tiny Series Software Manual for details. The fixed vector table for interrupts is assigned addresses FFFDCh to FFFFFh. The 256 bytes beginning with the start address set in the INTB register compose the relocatable vector table for interrupts. Figure 3.2 shows the Memory Map. 00000h Internal RAM Size 12 Kbytes 20 Kbytes 31 Kbytes 47 Kbytes Address XXXXXh SFR Internal RAM 00400h XXXXXh Reserved area 0D000h 0D800h 0E000h 10000h 14000h External area 27000h 28000h Relocatable vector table 033FFh 053FFh 07FFFh 0BFFFh SFR External area Internal ROM (data flash) Internal ROM (program ROM 2) 13800h 13FF0h 13FFFh On-chip debugger monitor area User boot code area Reserved area External area Program ROM 1 Address YYYYYh Size 128 Kbytes 256 Kbytes 384 Kbytes 512 Kbytes 640 Kbytes 768 Kbytes E0000h C0000h A0000h 80000h 60000h 40000h FFFFFh YYYYYh Internal ROM (program ROM 1) Reserved area FFE00h 40000h 256 bytes beginning with the start address set in the INTB register FFFD8h FFFDCh Special page vector table Reserved area Fixed vector table Address for ID code stored FFFFFh OFS1 address Notes: 1. Do not access reserved areas. 2. The figure above applies under the following conditions: - Memory expansion mode - The PM10 bit in the PM1 register is set to 1 (addresses from 0E000h to 0FFFFh are used as data flash) - The PRG2C0 bit in the PRG2C register is set to 0 (program ROM 2 enabled) - The PM13 bit in the PM1 register is set to 1 (the entire internal RAM and entire program ROM 1 from address 80000h are usable) - The IRON bit in the PRG2C register is set to 1 (program ROM 1 addresses from 40000h to 7FFFFh enabled) Figure 3.2 Memory Map REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 36 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 3. Address Space 3.3 Accessible Area in Each Mode The accessible area varies depending on processor mode and control bit status. Figure 3.3 shows Accessible Area in Each Mode. In single-chip mode, the SFRs, internal RAM, and internal ROM can be accessed. In memory expansion mode, the SFRs, internal RAM, internal ROM, and external areas can be accessed. Address space is expandable to 4 Mbytes with the memory capacity-enhancing feature. In microprocessor mode, the SFRs, internal RAM, and external areas can be accessed. Address space is expandable to 4 Mbytes with the memory capacity-enhancing feature. Assign ROM to the fixed vector table addresses from FFFDCh to FFFFFh. Single-Chip Mode 00000h 00400h Internal RAM Reserved area 0D000h 0D800h 0E000h 10000h 14000h SFR Reserved area Internal ROM (data flash) Internal ROM (program ROM 2) SFR Memory Expansion Mode 00000h SFR 00400h Internal RAM Reserved area 0D000h 0D800h 0E000h 10000h 14000h External area 27000h Reserved area 28000h SFR External area Internal ROM (data flash) Internal ROM (program ROM 2) Microprocessor Mode 00000h 00400h Internal RAM Reserved area 0D000h 0D800h SFR SFR External area 27000h Reserved area 28000h External area Reserved area 40000h Reserved area External area Internal ROM (program ROM 1) FFFFFh FFFFFh Internal ROM (program ROM 1) FFFFFh Notes: 1. Do not access reserved areas. 2. The figure above applies under the following conditions: Single-chip mode and memory expansion mode - The PM10 bit in the PM1 register is set to 1 (addresses from 0E000h to 0FFFFh are used as data flash) - The PRG2C0 bit in the PRG2C register is set to 0 (program ROM 2 enabled) - The PM13 bit in the PM1 register is set to 1 (the entire internal RAM and entire program ROM 1 from address 80000h are usable) - The IRON bit in the PRG2C register is set to 1 (program ROM 1 addresses from 40000h to 7FFFFh enabled) Microprocessor mode - The PM10 bit is set to 0 (addresses from 0E000h to 0FFFFh are used as CS2 area) - The PRG2C0 bit is set to 1 (program ROM 2 disabled) Figure 3.3 Accessible Area in Each Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 37 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 4. Special Function Registers (SFRs) 4. 4.1 Special Function Registers (SFRs) SFRs An SFR is a control register for a peripheral function. Table 4.1 to Table 4.15 list SFR information. Table 4.1 Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh Notes: 1. 2. 3. 4. 5. 6. SFR Information (1/16) (1) Register Symbol After Reset Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Chip Select Control Register External Area Recovery Cycle Control Register Protect Register Data Bank Register Oscillation Stop Detection Register PM0 PM1 CM0 CM1 CSR EWR PRCR DBR CM2 0000 0000b (CNVSS pin is low) 0000 0011b (CNVSS pin is high) (2) 0000 1000b 0100 1000b 0010 0000b 01h XXXX XX00b 00h 00h 0X00 0010b (3) Program 2 Area Control Register External Area Wait Control Expansion Register Peripheral Clock Select Register PRG2C EWC PCLKR XXXX XX00b 00h 0000 0011b Clock Prescaler Reset Flag CPSRF 0XXX XXXXb Reset Source Determine Register Voltage Detection 2 Circuit Flag Register Voltage Detection Circuit Operation Enable Register Chip Select Expansion Control Register PLL Control Register 0 Processor Mode Register 2 RSTFR VCR1 VCR2 CSE PLC0 PM2 XX00 001Xb (hardware reset) (4) 0000 X000b (2) 000X 0000b (2), (5) 001X 0000b (2), (6) 00h 0X01 X010b XX00 0X01b X: Undefined The blank areas are reserved. No access is allowed. Software reset, watchdog timer reset, oscillation stop detection reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect the following bits: Bits PM01 and PM00 in the PM0 register, VCR1 register, and VCR2 register. Oscillation stop detection reset does not affect bits CM20, CM21, and CM27. The state of bits in the RSTFR register depends on a reset type. When the LVDAS bit of address OFS1 is 1 at hardware reset This value shows the value after any of the following resets. - Voltage monitor 0 reset - When the LVDAS bit of address OFS1 is 0 at hardware reset - Power-on reset REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 38 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 4. Special Function Registers (SFRs) Table 4.2 Address 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh Notes: 1. 2. 3. 4. SFR Information (2/16) (1) Register Symbol After Reset 40 MHz On-Chip Oscillator Control Register 0 FRA0 XXXX XX00b Voltage Monitor Function Select Register Voltage Detection 1 Level Select Register Voltage Monitor 0 Circuit Control Register Voltage Monitor 1 Circuit Control Register Voltage Monitor 2 Circuit Control Register VWCE VD1LS VW0C VW1C VW2C 00h (5) 0000 1010b (5) 1100 1X10b (2), (3) 1100 1X11b (2), (4) 1000 XX10b (6) 1000 0X10b (6) INT7 Interrupt Control Register INT6 Interrupt Control Register INT3 Interrupt Control Register Timer B5 Interrupt Control Register Timer B4 Interrupt Control Register UART1 Bus Collision Detection Interrupt Control Register Timer B3 Interrupt Control Register UART0 Bus Collision Detection Interrupt Control Register SI/O4 Interrupt Control Register INT5 Interrupt Control Register SI/O3 Interrupt Control Register INT4 Interrupt Control Register UART2 Bus Collision Detection Interrupt Control Register DMA0 Interrupt Control Register DMA1 Interrupt Control Register Key Input Interrupt Control Register A/D Conversion Interrupt Control Register UART2 Transmit Interrupt Control Register INT7IC INT6IC INT3IC TB5IC TB4IC U1BCNIC TB3IC U0BCNIC S4IC INT5IC S3IC INT4IC BCNIC DM0IC DM1IC KUPIC ADIC S2TIC XX00 X000b XX00 X000b XX00 X000b XXXX X000b XXXX X000b XXXX X000b XX00 X000b XX00 X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b 5. 6. X: Undefined The blank areas are reserved. No access is allowed. Software reset, watchdog timer reset, oscillation stop detection reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect the following register or bit: VW0C register and VW2C3 bit in the VW2C register. When the LVDAS bit of address OFS1 is 1 at hardware reset This value shows the value after any of the following resets. - Voltage monitor 0 reset - When the LVDAS bit of address OFS1 is 0 at hardware reset - Power-on reset Hardware reset, power-on reset, voltage monitor 0 reset, voltage monitor 1 reset, or voltage monitor 2 reset Hardware reset, power-on reset, or voltage monitor 0 reset REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 39 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 4. Special Function Registers (SFRs) Table 4.3 Address 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh 0080h to 017Fh Note: 1. SFR Information (3/16) (1) Register UART2 Receive Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register Timer A0 Interrupt Control Register Timer A1 Interrupt Control Register Timer A2 Interrupt Control Register Timer A3 Interrupt Control Register Timer A4 Interrupt Control Register Timer B0 Interrupt Control Register Timer B1 Interrupt Control Register Timer B2 Interrupt Control Register INT0 Interrupt Control Register INT1 Interrupt Control Register INT2 Interrupt Control Register Symbol S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC TB2IC INT0IC INT1IC INT2IC After Reset XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XX00 X000b XX00 X000b XX00 X000b DMA2 Interrupt Control Register DMA3 Interrupt Control Register UART5 Bus Collision Detection Interrupt Control Register CEC1 Interrupt Control Register UART5 Transmit Interrupt Control Register CEC2 Interrupt Control Register UART5 Receive Interrupt Control Register UART6 Bus Collision Detection Interrupt Control Register Real-Time Clock Period Interrupt Control Register UART6 Transmit Interrupt Control Register Real-Time Clock Compare Match Interrupt Control Register UART6 Receive Interrupt Control Register UART7 Bus Collision Detection Interrupt Control Register Remote Control Signal Receiver 0 Interrupt Control Register UART7 Transmit Interrupt Control Register Remote Control Signal Receiver 1 Interrupt Control Register UART7 Receive Interrupt Control Register DM2IC DM3IC U5BCNIC CEC1IC S5TIC, CEC2IC S5RIC U6BCNIC RTCTIC S6TIC RTCCIC S6RIC U7BCNIC PMC0IC S7TIC PMC1IC S7RIC XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b IICBus Interface Interrupt Control Register SCL/SDA Interrupt Control Register IICIC SCLDAIC XXXX X000b XXXX X000b X: Undefined The blank areas are reserved. No access is allowed. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 40 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 4. Special Function Registers (SFRs) Table 4.4 Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh Note: 1. SFR Information (4/16) (1) Register DMA0 Source Pointer Symbol SAR0 XXh XXh 0Xh XXh XXh 0Xh XXh XXh After Reset DMA0 Destination Pointer DAR0 DMA0 Transfer Counter TCR0 DMA0 Control Register DM0CON 0000 0X00b DMA1 Source Pointer SAR1 XXh XXh 0Xh XXh XXh 0Xh XXh XXh DMA1 Destination Pointer DAR1 DMA1 Transfer Counter TCR1 DMA1 Control Register DM1CON 0000 0X00b DMA2 Source Pointer SAR2 XXh XXh 0Xh XXh XXh 0Xh XXh XXh DMA2 Destination Pointer DAR2 DMA2 Transfer Counter TCR2 DMA2 Control Register DM2CON 0000 0X00b X: Undefined The blank areas are reserved. No access is allowed. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 41 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 4. Special Function Registers (SFRs) Table 4.5 Address 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh 01C0h 01C1h 01C2h 01C3h 01C4h 01C5h 01C6h 01C7h 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh Note: 1. SFR Information (5/16) (1) Register DMA3 Source Pointer Symbol SAR3 XXh XXh 0Xh XXh XXh 0Xh XXh XXh After Reset DMA3 Destination Pointer DAR3 DMA3 Transfer Counter TCR3 DMA3 Control Register DM3CON 0000 0X00b Timer B0-1 Register Timer B1-1 Register Timer B2-1 Register Pulse Period/Pulse Width Measurement Mode Function Select Register 1 Timer B Count Source Select Register 0 Timer B Count Source Select Register 1 Timer AB Division Control Register 0 TB01 TB11 TB21 PPWFS1 TBCS0 TBCS1 TCKDIVC0 XXh XXh XXh XXh XXh XXh XXXX X000b 00h X0h 0000 X000b Timer A Count Source Select Register 0 Timer A Count Source Select Register 1 Timer A Count Source Select Register 2 16-Bit Pulse Width Modulation Mode Function Select Register Timer A Waveform Output Function Select Register TACS0 TACS1 TACS2 PWMFS TAPOFS 00h 00h X0h 0XX0 X00Xb XXX0 0000b Timer A Output Waveform Change Enable Register Three-Phase Protect Control Register TAOW TPRC XXX0 X00Xb 00h X: Undefined The blank areas are reserved. No access is allowed. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 42 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 4. Special Function Registers (SFRs) Table 4.6 Address 01E0h 01E1h 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh 01F0h 01F1h 01F2h 01F3h 01F4h 01F5h 01F6h 01F7h 01F8h 01F9h 01FAh 01FBh 01FCh 01FDh 01FEh 01FFh 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020Ah 020Bh 020Ch 020Dh 020Eh 020Fh Note: 1. SFR Information (6/16) (1) Register Timer B3-1 Register Timer B4-1 Register Timer B5-1 Register Pulse Period/Pulse Width Measurement Mode Function Select Register 2 Timer B Count Source Select Register 2 Timer B Count Source Select Register 3 TB31 TB41 TB51 PPWFS2 TBCS2 TBCS3 Symbol After Reset XXh XXh XXh XXh XXh XXh XXXX X000b 00h X0h PMC0 Function Select Register 0 PMC0 Function Select Register 1 PMC0 Function Select Register 2 PMC0 Function Select Register 3 PMC0 Status Register PMC0 Interrupt Source Select Register PMC0 Compare Control Register PMC0 Compare Data Register PMC1 Function Select Register 0 PMC1 Function Select Register 1 PMC1 Function Select Register 2 PMC1 Function Select Register 3 PMC1 Status Register PMC1 Interrupt Source Select Register PMC0CON0 PMC0CON1 PMC0CON2 PMC0CON3 PMC0STS PMC0INT PMC0CPC PMC0CPD PMC1CON0 PMC1CON1 PMC1CON2 PMC1CON3 PMC1STS PMC1INT 00h 00XX 0000b 00h 00h 00h 00h XXX0 X000b 00h XXX0 X000b XXXX 0X00b 00h 00h X000 X00Xb X000 X00Xb Interrupt Source Select Register 3 Interrupt Source Select Register 2 Interrupt Source Select Register IFSR3A IFSR2A IFSR 00h 00h 00h Address Match Interrupt Enable Register Address Match Interrupt Enable Register 2 The blank areas are reserved. No access is allowed. AIER AIER2 XXXX XX00b XXXX XX00b X: Undefined REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 43 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 4. Special Function Registers (SFRs) Table 4.7 Address 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021Ah 021Bh 021Ch 021Dh 021Eh 021Fh 0220h SFR Information (7/16) (1) Register Address Match Interrupt Register 0 Symbol RMAD0 00h 00h X0h 00h 00h X0h 00h 00h X0h 00h 00h X0h After Reset Address Match Interrupt Register 1 RMAD1 Address Match Interrupt Register 2 RMAD2 Address Match Interrupt Register 3 RMAD3 Flash Memory Control Register 0 FMR0 0221h 0222h 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022Ah 022Bh 022Ch 022Dh 022Eh 022Fh 0230h 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023Ah 023Bh 023Ch 023Dh 023Eh 023Fh Note: 1. Flash Memory Control Register 1 Flash Memory Control Register 2 Flash Memory Control Register 3 FMR1 FMR2 FMR3 0000 0001b (Other than user boot mode) 0010 0001b (User boot mode) 00X0 XX0Xb XXXX 0000b XXXX 0000b Flash Memory Control Register 6 FMR6 XX0X XX00b X: Undefined The blank areas are reserved. No access is allowed. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 44 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 4. Special Function Registers (SFRs) Table 4.8 Address 0240h 0241h 0242h 0243h 0244h 0245h 0246h 0247h 0248h 0249h 024Ah 024Bh 024Ch 024Dh 024Eh 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0260h 0261h 0262h 0263h 0264h 0265h 0266h 0267h 0268h 0269h 026Ah 026Bh 026Ch 026Dh 026Eh 026Fh Note: 1. SFR Information (8/16) (1) Register Symbol After Reset UART0 Special Mode Register 4 UART0 Special Mode Register 3 UART0 Special Mode Register 2 UART0 Special Mode Register UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register UART Transmit/Receive Control Register 2 UART Clock Select Register UART1 Special Mode Register 4 UART1 Special Mode Register 3 UART1 Special Mode Register 2 UART1 Special Mode Register UART1 Transmit/Receive Mode Register UART1 Bit Rate Register UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register U0SMR4 U0SMR3 U0SMR2 U0SMR U0MR U0BRG U0TB U0C0 U0C1 U0RB UCON UCLKSEL0 U1SMR4 U1SMR3 U1SMR2 U1SMR U1MR U1BRG U1TB U1C0 U1C1 U1RB 00h 000X 0X0Xb X000 0000b X000 0000b 00h XXh XXh XXh 0000 1000b 00XX 0010b XXh XXh X000 0000b X0h 00h 000X 0X0Xb X000 0000b X000 0000b 00h XXh XXh XXh 0000 1000b 00XX 0010b XXh XXh UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register UART2 Transmit/Receive Mode Register UART2 Bit Rate Register UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB 00h 000X 0X0Xb X000 0000b X000 0000b 00h XXh XXh XXh 0000 1000b 0000 0010b XXh XXh X: Undefined The blank areas are reserved. No access is allowed. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 45 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 4. Special Function Registers (SFRs) Table 4.9 Address 0270h 0271h 0272h 0273h 0274h 0275h 0276h 0277h 0278h 0279h 027Ah 027Bh 027Ch 027Dh 027Eh 027Fh 0280h 0281h 0282h 0283h 0284h 0285h 0286h 0287h 0288h 0289h 028Ah 028Bh 028Ch 028Dh 028Eh 028Fh 0290h 0291h 0292h 0293h 0294h 0295h 0296h 0297h 0298h 0299h 029Ah 029Bh 029Ch 029Dh 029Eh 029Fh Note: 1. SFR Information (9/16) (1) Register SI/O3 Transmit/Receive Register SI/O3 Control Register SI/O3 Bit Rate Register SI/O4 Transmit/Receive Register SI/O4 Control Register SI/O4 Bit Rate Register SI/O3, 4 Control Register 2 Symbol S3TRR S3C S3BRG S4TRR S4C S4BRG S34C2 XXh After Reset 0100 0000b XXh XXh 0100 0000b XXh 00XX X0X0b UART5 Special Mode Register 4 UART5 Special Mode Register 3 UART5 Special Mode Register 2 UART5 Special Mode Register UART5 Transmit/Receive Mode Register UART5 Bit Rate Register UART5 Transmit Buffer Register UART5 Transmit/Receive Control Register 0 UART5 Transmit/Receive Control Register 1 UART5 Receive Buffer Register U5SMR4 U5SMR3 U5SMR2 U5SMR U5MR U5BRG U5TB U5C0 U5C1 U5RB 00h 000X 0X0Xb X000 0000b X000 0000b 00h XXh XXh XXh 0000 1000b 0000 0010b XXh XXh UART6 Special Mode Register 4 UART6 Special Mode Register 3 UART6 Special Mode Register 2 UART6 Special Mode Register UART6 Transmit/Receive Mode Register UART6 Bit Rate Register UART6 Transmit Buffer Register UART6 Transmit/Receive Control Register 0 UART6 Transmit/Receive Control Register 1 UART6 Receive Buffer Register U6SMR4 U6SMR3 U6SMR2 U6SMR U6MR U6BRG U6TB U6C0 U6C1 U6RB 00h 000X 0X0Xb X000 0000b X000 0000b 00h XXh XXh XXh 0000 1000b 0000 0010b XXh XXh X: Undefined The blank areas are reserved. No access is allowed. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 46 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 4. Special Function Registers (SFRs) Table 4.10 Address 02A0h 02A1h 02A2h 02A3h 02A4h 02A5h 02A6h 02A7h 02A8h 02A9h 02AAh 02ABh 02ACh 02ADh 02AEh 02AFh 02B0h 02B1h 02B2h 02B3h 02B4h 02B5h 02B6h 02B7h 02B8h 02B9h 02BAh 02BBh 02BCh 02BDh 02BEh 02BFh 02C0h to 02FFh 0300h 0301h 0302h 0303h 0304h 0305h 0306h 0307h 0308h 0309h 030Ah 030Bh 030Ch 030Dh 030Eh 030Fh Note: 1. SFR Information (10/16) (1) Register Symbol After Reset UART7 Special Mode Register 4 UART7 Special Mode Register 3 UART7 Special Mode Register 2 UART7 Special Mode Register UART7 Transmit/Receive Mode Register UART7 Bit Rate Register UART7 Transmit Buffer Register UART7 Transmit/Receive Control Register 0 UART7 Transmit/Receive Control Register 1 UART7 Receive Buffer Register I2C0 Data Shift Register I2C0 Address Register 0 I2C0 Control Register I2C0 Clock Control Register I2C0 Start/Stop Condition Control Register I2C0 Control Register 1 I2C0 Control Register 2 I2C0 Status Register 0 I2C0 Status Register 1 I2C0 Address Register 1 I2C0 Address Register 2 U7SMR4 U7SMR3 U7SMR2 U7SMR U7MR U7BRG U7TB U7C0 U7C1 U7RB S00 S0D0 S1D0 S20 S2D0 S3D0 S4D0 S10 S11 S0D1 S0D2 00h 000X 0X0Xb X000 0000b X000 0000b 00h XXh XXh XXh 0000 1000b 0000 0010b XXh XXh XXh 0000 000Xb 00h 00h 0001 1010b 0011 0000b 00h 0001 000Xb 00h 0000 000Xb 0000 000Xb Timer B3/B4/B5 Count Start Flag Timer A1-1 Register Timer A2-1 Register Timer A4-1 Register Three-Phase PWM Control Register 0 Three-Phase PWM Control Register 1 Three-Phase Output Buffer Register 0 Three-Phase Output Buffer Register 1 Dead Time Timer Timer B2 Interrupt Generation Frequency Set Counter Position-Data-Retain Function Control Register TBSR TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2 PDRF 000X XXXXb XXh XXh XXh XXh XXh XXh 00h 00h XX11 1111b XX11 1111b XXh XXh XXXX 0000b X: Undefined The blank areas are reserved. No access is allowed. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 47 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 4. Special Function Registers (SFRs) Table 4.11 Address 0310h 0311h 0312h 0313h 0314h 0315h 0316h 0317h 0318h 0319h 031Ah 031Bh 031Ch 031Dh 031Eh 031Fh 0320h 0321h 0322h 0323h 0324h 0325h 0326h 0327h 0328h 0329h 032Ah 032Bh 032Ch 032Dh 032Eh 032Fh 0330h 0331h 0332h 0333h 0334h 0335h 0336h 0337h 0338h 0339h 033Ah 033Bh 033Ch 033Dh 033Eh 033Fh Note: 1. SFR Information (11/16) (1) Register Timer B3 Register Timer B4 Register Timer B5 Register TB3 TB4 TB5 Symbol XXh XXh XXh XXh XXh XXh After Reset Port Function Control Register PFCR 0011 1111b Timer B3 Mode Register Timer B4 Mode Register Timer B5 Mode Register TB3MR TB4MR TB5MR 00XX 0000b 00XX 0000b 00XX 0000b Count Start Flag One-Shot Start Flag Trigger Select Register Up/Down Flag Timer A0 Register Timer A1 Register Timer A2 Register Timer A3 Register Timer A4 Register Timer B0 Register Timer B1 Register Timer B2 Register Timer A0 Mode Register Timer A1 Mode Register Timer A2 Mode Register Timer A3 Mode Register Timer A4 Mode Register Timer B0 Mode Register Timer B1 Mode Register Timer B2 Mode Register Timer B2 Special Mode Register TABSR ONSF TRGSR UDF TA0 TA1 TA2 TA3 TA4 TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC 00h 00h 00h 00h XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh 00h 00h 00h 00h 00h 00XX 0000b 00XX 0000b 00XX 0000b XXXX XX00b X: Undefined The blank areas are reserved. No access is allowed. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 48 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 4. Special Function Registers (SFRs) Table 4.12 Address 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034Ah 034Bh 034Ch 034Dh 034Eh 034Fh 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh 0360h 0361h 0362h 0363h 0364h 0365h 0366h 0367h 0368h 0369h 036Ah 036Bh 036Ch 036Dh 036Eh 036Fh Notes: 1. 2. SFR Information (12/16) (1) Register Symbol RTCSEC RTCMIN RTCHR RTCWK RTCCR1 RTCCR2 RTCCSR RTCCSEC RTCCMIN RTCCHR After Reset 00h X000 0000b XX00 0000b XXXX X000b 0000 X00Xb X000 0000b XXX0 0000b X000 0000b X000 0000b X000 0000b Real-Time Clock Second Data Register Real-Time Clock Minute Data Register Real-Time Clock Hour Data Register Real-Time Clock Day Data Register Real-Time Clock Control Register 1 Real-Time Clock Control Register 2 Real-Time Clock Count Source Select Register Real-Time Clock Second Compare Data Register Real-Time Clock Minute Compare Data Register Real-Time Clock Hour Compare Data Register CEC Function Control Register 1 CEC Function Control Register 2 CEC Function Control Register 3 CEC Function Control Register 4 CEC Flag Register CEC Interrupt Source Select Register CEC Transmit Buffer Register 1 CEC Transmit Buffer Register 2 CEC Receive Buffer Register 1 CEC Receive Buffer Register 2 CEC Receive Follower Address Set Register 1 CEC Receive Follower Address Set Register 2 CECC1 CECC2 CECC3 CECC4 CECFLG CISEL CCTB1 CCTB2 CCRB1 CCRB2 CRADRI1 CRADRI2 XXXX X000b 00h XXXX 0000b 00h 00h 00h 00h XXXX XX00b 00h XXXX X000b 00h 00h Pull-Up Control Register 0 Pull-Up Control Register 1 Pull-Up Control Register 2 Pull-Up Control Register 3 PUR0 PUR1 PUR2 PUR3 00h 0000 0000b (2) 0000 0010b 00h 00h Port Control Register PCR 0000 0XX0b NMI/SD Digital Filter Register NMIDF XXXX X000b X: Undefined The blank areas are reserved. No access is allowed. Values after hardware reset, power-on reset, or voltage monitor 0 reset are as follows: - 00000000b when a low-level signal is input to the CNVSS pin - 00000010b when a high-level signal is input to the CNVSS pin Values after voltage monitor 1 reset, voltage monitor 2 reset, software reset, watchdog timer reset, or oscillation stop detection reset are as follows: - 00000000b when bits PM01 and PM00 in the PM0 register are 00b (single-chip mode). - 00000010b when bits PM01 and PM00 in the PM0 register are 01b (memory expansion mode) or 11b (microprocessor mode). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 49 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 4. Special Function Registers (SFRs) Table 4.13 Address 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 038Ch 038Dh 038Eh 038Fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039Ah 039Bh 039Ch 039Dh 039Eh 039Fh Notes: 1. 2. SFR Information (13/16) (1) Register Symbol PWMCON0 PWMPRE0 PWMREG0 PWMPRE1 PWMREG1 PWMCON1 00h 00h 00h 00h 00h 00h After Reset PWM Control Register 0 PWM0 Prescaler PWM0 Register PWM1 Prescaler PWM1 Register PWM Control Register 1 Count Source Protection Mode Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register CSPR WDTR WDTS WDC 00h (2) XXh XXh 00XX XXXXb DMA2 Source Select Register DMA3 Source Select Register DM2SL DM3SL 00h 00h DMA0 Source Select Register DMA1 Source Select Register DM0SL DM1SL 00h 00h X: Undefined The blank areas are reserved. No access is allowed. When the CSPROINT bit in the OFS1 address is 0, value after reset is 10000000b REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 50 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 4. Special Function Registers (SFRs) Table 4.14 Address 03A0h 03A1h 03A2h 03A3h 03A4h 03A5h 03A6h 03A7h 03A8h 03A9h 03AAh 03ABh 03ACh 03ADh 03AEh 03AFh 03B0h 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h 03B9h 03BAh 03BBh 03BCh 03BDh 03BEh 03BFh 03C0h 03C1h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C8h 03C9h 03CAh 03CBh 03CCh 03CDh 03CEh 03CFh Note: 1. SFR Information (14/16) (1) Register Symbol After Reset Open-Circuit Detection Assist Function Register AINRST XX00 0000b SFR Snoop Address Register CRC Mode Register CRCSAR CRCMR XXXX XXXXb 00XX XXXXb 0XXX XXX0b CRC Data Register CRC Input Register A/D Register 0 A/D Register 1 A/D Register 2 A/D Register 3 A/D Register 4 A/D Register 5 A/D Register 6 A/D Register 7 CRCD CRCIN AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 XXh XXh XXh XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb X: Undefined The blank areas are reserved. No access is allowed. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 51 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 4. Special Function Registers (SFRs) Table 4.15 Address 03D0h 03D1h 03D2h 03D3h 03D4h 03D5h 03D6h 03D7h 03D8h 03D9h 03DAh 03DBh 03DCh 03DDh 03DEh 03DFh 03E0h 03E1h 03E2h 03E3h 03E4h 03E5h 03E6h 03E7h 03E8h 03E9h 03EAh 03EBh 03ECh 03EDh 03EEh 03EFh 03F0h 03F1h 03F2h 03F3h 03F4h 03F5h 03F6h 03F7h 03F8h 03F9h 03FAh 03FBh 03FCh 03FDh 03FEh 03FFh 0400h to D07Fh Note: 1. SFR Information (15/16) (1) Register Symbol After Reset A/D Control Register 2 A/D Control Register 0 A/D Control Register 1 D/A0 Register D/A1 Register D/A Control Register ADCON2 ADCON0 ADCON1 DA0 DA1 DACON 0000 X00Xb 0000 0XXXb 0000 X000b 00h 00h 00h Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register Port P11 Register Port P10 Direction Register Port P11 Direction Register Port P12 Register Port P13 Register Port P12 Direction Register Port P13 Direction Register Port P14 Register Port P14 Direction Register P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 P11 PD10 PD11 P12 P13 PD12 PD13 P14 PD14 XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXXX XX00b X: Undefined The blank areas are reserved. No access is allowed. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 52 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 4. Special Function Registers (SFRs) Table 4.16 Address D080h D081h D082h D083h D084h D085h D086h D087h D088h D089h D08Ah D08Bh D08Ch D08Dh D08Eh D08Fh D090h D091h D092h D093h D094h D095h D096h D097h D098h D099h D09Ah D09Bh D09Ch D09Dh D09Eh D09Fh Note: 1. SFR Information (16/16) (1) Register Symbol PMC0HDPMIN PMC0HDPMAX PMC0D0PMIN PMC0D0PMAX PMC0D1PMIN PMC0D1PMAX PMC0TIM PMC0BC PMC0DAT0 PMC0DAT1 PMC0DAT2 PMC0DAT3 PMC0DAT4 PMC0DAT5 PMC0RBIT PMC1HDPMIN PMC1HDPMAX PMC1D0PMIN PMC1D0PMAX PMC1D1PMIN PMC1D1PMAX PMC1TIM PMC1BC After Reset 00h XXXX X000b 00h XXXX X000b 00h 00h 00h 00h 0000h 0000h 00h 00h 00h 00h 00h 00h XX00 0000b 00h XXXX X000b 00h XXXX X000b 00h 00h 00h 00h 00h 00h 00h 00h X: Undefined PMC0 Header Pattern Set Register (Min) PMC0 Header Pattern Set Register (Max) PMC0 Data0 Pattern Set Register (Min) PMC0 Data0 Pattern Set Register (Max) PMC0 Data1 Pattern Set Register (Min) PMC0 Data1 Pattern Set Register (Max) PMC0 Measurements Register PMC0 Counter Value Register PMC0 Receive Data Store Register 0 PMC0 Receive Data Store Register 1 PMC0 Receive Data Store Register 2 PMC0 Receive Data Store Register 3 PMC0 Receive Data Store Register 4 PMC0 Receive Data Store Register 5 PMC0 Receive Bit Count Register PMC1 Hedder Pattern Set Register (Min) PMC1 Header Pattern Set Register (Max) PMC1 Data0 Pattern Set Register (Min) PMC1 Data0 Pattern Set Register (Max) PMC1 Data1 Pattern Set Register (Min) PMC1 Data1 Pattern Set Register (Max) PMC1 Measurements Register PMC1 Counter Value Register The blank areas are reserved. No access is allowed. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 53 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 4. Special Function Registers (SFRs) 4.2 4.2.1 Notes on SFRs Register Settings Table 4.17 lists Registers with Write-Only Bits and registers whose function differs between reading and writing. Set these registers with immediate values. When establishing the next value by altering the existing value, write the existing value to the RAM as well as to the register. Transfer the next value to the register after making changes in the RAM. Table 4.17 Registers with Write-Only Bits Register Watchdog Timer Reset Register Watchdog Timer Start Register Timer A0 Register Timer A1 Register Timer A2 Register Timer A3 Register Timer A4 Register Timer A1-1 Register Timer A2-1 Register Timer A4-1 Register Three-Phase Output Buffer Register 0 Three-Phase Output Buffer Register 1 Dead Time Timer Timer B2 Interrupt Generation Frequency Set Counter UART0 Bit Rate Register UART1 Bit Rate Register UART2 Bit Rate Register UART5 Bit Rate Register UART6 Bit Rate Register UART7 Bit Rate Register UART0 Transmit Buffer Register UART1 Transmit Buffer Register UART2 Transmit Buffer Register UART5 Transmit Buffer Register UART6 Transmit Buffer Register UART7 Transmit Buffer Register SI/O3 Bit Rate Register SI/O4 Bit Rate Register I2C0 Control Register 1 I2C0 Status Register 0 Symbol WDTR WDTS TA0 TA1 TA2 TA3 TA4 TA11 TA21 TA41 IDB0 IDB1 DTT ICTB2 U0BRG U1BRG U2BRG U5BRG U6BRG U7BRG U0TB U1TB U2TB U5TB U6TB U7TB S3BRG S4BRG S3D0 S10 Address 037Dh 037Eh 0327h to 0326h 0329h to 0328h 032Bh to 032Ah 032Dh to 032Ch 032Fh to 032Eh 0303h to 0302h 0305h to 0304h 0307h to 0306h XX11 1111b XX11 1111b 030Ch 030Dh 0249h 0259h 0269h 0289h 0299h 02A9h 024Bh to 024Ah 025Bh to 025Ah 026Bh to 026Ah 028Bh to 028Ah 029Bh to 029Ah 02ABh to 02AAh 0273h 0277h 02B6h 02B8h REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 54 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 5. Protection 5. 5.1 Protection Introduction In the event that a program runs out of control, this function protects the important registers listed below so that they will not be rewritten easily. 5.2 Register Register Structure Table 5.1 Address 000Ah Register Name Protect Register Register Symbol PRCR 00h After Reset 5.2.1 Protect Register (PRCR) Protect Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PRCR Bit Symbol Bit Name Address 000Ah Function 0 00 After Reset 00h RW PRC0 Protect bit 0 PRC1 Protect bit 1 Enable write to registers CM0, CM1, CM2, PLC0, PCLKR, and FRA0 0 : Write protected 1 : Write enabled Enable write to registers PM0, PM1, PM2, TB2SC, INVC0, and INVC1 0 : Write protected 1 : Write enabled Enable write to registers PD9, S3C, and S4C 0 : Write protected 1 : Write enabled Enable write to registers VCR2, VWCE, VD1LS, VW0C, VW1C, and VW2C 0 : Write protected 1 : Write enabled Set to 0 Enable write to the PRG2C register 0 : Write protected 1 : Write enabled Set to 0 RW RW PRC2 Protect bit 2 RW PRC3 Protect bit 3 RW — (b5-b4) PRC6 — (b7) Reserved bits RW Protect bit 6 RW Reserved bit RW REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 55 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 5. Protection PRC6, PRC3, PRC1, PRC0 (Protect Bits 6, 3, 1, 0) (b6, b3, b1, b0) When setting bits PRC6, PRC3, PRC1, and PRC0 to 1 (write enabled) by a program, the bits remain 1 (write enabled). To change registers protected by these bits, follow the procedures below: (1) Set the PRCi (i = 0, 1, 3, 6) to 1. (2) Write to the register protected by the PRCi bit. (3) Set the PRCi bit to 0 (write protected). PRC2 (Protect Bit 2) (b2) After setting the PRC2 bit to 1 (write enabled), by writing to a given SFR, the PRC2 bit becomes 0. Change the registers protected by the PRC2 bit in the next instruction after setting the PRC2 bit to 1. The procedure is shown below. Make sure there are no interrupts or DMA transfers between procedure 1 and 2. (1) Set the PRC2 bit to 1. (2) Write to the register protected by the PRC2 bit. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 56 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 5. Protection 5.3 Notes on Protection After setting the PRC2 bit to 1 (write enabled), by writing to a given SFR, the PRC2 bit becomes 0. Change the registers protected by the PRC2 bit in the next instruction after setting the PRC2 bit to 1. Make sure there are no interrupts or DMA transfers between the instruction that sets the PRC2 bit to 1 and the next instruction. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 57 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 6. Resets 6. 6.1 Resets Introduction The following resets can be used to reset the MCU: hardware reset, power-on reset, voltage monitor 0 reset, voltage monitor 1 reset, voltage monitor 2 reset, oscillation stop detection reset, watchdog timer reset, and software reset. Table 6.1 lists the Types of Resets, Figure 6.1 shows the Reset Circuit Block Diagram, and Table 6.2 lists the I/O Pins. Table 6.1 Types of Resets Reset Name Hardware reset Power-on reset Voltage monitor 0 reset Voltage monitor 1 reset Voltage monitor 2 reset Oscillation stop detection reset Watchdog timer reset Software reset The rise of the voltage on VCC1 Trigger A low-level signal is applied to the RESET pin. The drop of the voltage on VCC1 (reference voltage: Vdet0) The drop of the voltage on VCC1 (reference voltage: Vdet1) The drop of the voltage on VCC1 (reference voltage: Vdet2) The main clock oscillator stop is detected. Watchdog timer underflows. Setting the PM03 bit in the PM0 register to 1 RESET Hardware reset VCC1 Power-on reset circuit Power-on reset Voltage monitor 0 reset Voltage detection circuit Voltage monitor 1 reset Voltage monitor 2 reset Watchdog timer reset SFR VCR1 register VCR2 register VW0C register VWCE register Bits VW1C2 and VW1C3 in the VW1C register Bits VW2C2 and VW2C3 in the VW2C register Bits PM00 and PM01 in the PM0 register Watchdog timer Software reset CPU SFR Bits CM20, CM21, and CM27 in the CM2 register Pins, CPU, or SFR not listed above XIN Oscillation stop/ re-oscillation detection circuit Oscillation stop reset This diagram shows that reset signals are output to SFRs. Refer to 4. SFR for values after reset. Figure 6.1 Reset Circuit Block Diagram Table 6.2 I/O Pins I/O Pin RESET I/O Type Input Input Hardware reset input Function Power input. The power-on reset, voltage monitor 0 reset, voltage monitor 1 reset, and voltage monitor 2 reset are generated by monitoring VCC1. VCC1 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 58 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group Table 6.2 I/O Pins 6. Resets I/O Pin XIN I/O Type Input Function Main clock input. The oscillation stop detection reset is generated by monitoring the main clock. 6.2 Registers Refer to 7. “Voltage Detector” for registers used for the voltage monitor 0 reset, voltage monitor 1 reset, and voltage monitor 2 reset. Refer to 15. “Watchdog Timer” for registers used for the watchdog timer reset. Refer to 8.7 “Oscillation Stop/Re-Oscillation Detect Function” for registers used for oscillation stop detection reset. Table 6.3 Register Structure Address 0004h Register Name Processor Mode Register 0 0018h Note: 1. Reset Source Determine Register Register Symbol After Reset PM0 0000 0000b (CNVSS pin is low) 0000 0011b (CNVSS pin is high) RSTFR XX00 001Xb (hardware reset) (1) When not using the cold start-up/warm start-up discrimination flag in hardware reset. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 59 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 6. Resets 6.2.1 Processor Mode Register 0 (PM0) Processor Mode Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PM0 Address 0004h After Reset 0000 0000b (CNVSS pin is held low) 0000 0011b (CNVSS pin is held high) Function b1 b0 Bit Symbol PM00 Bit Name RW RW Processor mode bit PM01 0 0 1 1 0 : Single-chip mode 1 : Memory expansion mode 0 : Do not set 1 : Microprocessor mode RW PM02 R/W mode select bit 0 : RD, BHE, WR 1 : RD, WRH, WRL Setting this bit to 1 resets the MCU. Read as 0. b5 b4 RW PM03 Software reset bit RW PM04 Multiplexed bus space select bit PM05 0 0 1 1 0 : Multiplexed bus is unused (separate bus in the entire CS space) 1 : Allocated to CS2 space 0 : Allocated to CS1 space 1 : Allocated to the entire CS space RW RW PM06 Port P4_0 to P4_3 function select bit 0 : Address output 1 : Port function (address is not output) 0 : BCLK is output 1 : BCLK is not output (pin is left in high-impedance) RW PM07 BCLK output disable bit RW Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enabled). The software reset, watchdog timer reset, oscillation stop detection reset, voltage monitor 1 reset, and voltage monitor 2 reset have no effect on bits PM01 to PM00. PM03 (Software Reset Bit) (b3) The software reset is generated by setting the PM03 bit to 1. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 60 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 6. Resets 6.2.2 Reset Source Determine Register (RSTFR) Reset Source Determine Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol RSTFR Bit Symbol CWR Address 0018h Bit Name Cold start-up/warm start-up discrimination flag Hardware reset detection flag 0 : Cold start 1 : Warm start 0 : Not detected 1 : Detected 0 : Not detected 1 : Detected After Reset See Table 6.4 Function RW RW HWR RO SWR Software reset detection flag RO WDR Watchdog timer reset detection 0 : Not detected 1 : Detected flag Voltage monitor 1 reset detection flag Voltage monitor 2 reset detection flag 0 : Not detected 1 : Detected 0 : Not detected 1 : Detected RO LVD1R RO LVD2R RO OSDR — (b7) Oscillation stop detection reset 0 : Not detected 1 : Detected detection flag Reserved bit If necessary, set to 0. Read as undefined value. RW RW Table 6.4 Bit Values in the RSTFR Register after Reset Reset Hardware reset Power-on reset Voltage monitor 0 reset Voltage monitor 1 reset Voltage monitor 2 reset Oscillation stop detection reset Watchdog timer reset Software reset Bits in the RSTFR Register OSDR No change 0 0 0 0 1 0 0 LVD2R 0 0 0 0 1 0 0 0 LVD1R 0 0 0 1 0 0 0 0 WDR 0 0 0 0 0 0 1 0 SWR 0 0 0 0 0 0 0 1 HWR 1 0 0 0 0 0 0 0 CWR No change 0 0 No change No change No change No change No change REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 61 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 6. Resets CWR (Cold Start-Up/Warm Start-Up Discrimination Flag) (b0) Condition to become 0: • Power-on • Power-on reset, voltage monitor 0 reset Condition to become 1: • Writing 1 to the CWR bit OSDR (Oscillation Stop Detection Reset Detection Flag) (b6) This bit becomes 0 by writing a 0 by a program. Writing a 1 has no effect. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 62 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 6. Resets 6.3 Optional Function Select Area In the optional function select area, the MCU state after reset and the function to prevent rewrite in parallel I/O mode are selected. The optional function select area is not an SFR, and therefore cannot be rewritten by a program. Set a proper value when writing a program in flash memory. The entire optional function select area becomes FFh when the block including the optional function select area is erased. 6.3.1 Optional Function Select Address 1 (OFS1) Optional Function Select Address 1 b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol OFS1 Bit Symbol Bit Name Address FFFFFh Function Factory Setting FFh RW WDTON Watchdog timer start select bit 0 : Watchdog timer starts automatically after reset. 1 : Watchdog timer is in a stopped state after reset. Set to 1. 0 : ROM code protection cancelled. 1 : ROMCP1 bit enabled. 0 : ROM code protection enabled. 1 : ROM code protection disabled. Set to 1. 0 : 2.85 V (Vdet0_2) 1 : 1.90 V (Vdet0_0) 0 : Voltage monitor 0 reset enabled after hardware reset. 1 : Voltage monitor 0 reset disabled after hardware reset. 0 : Count source protection mode enabled after reset. 1 : Count source protection mode disabled after reset. RW — (b1) ROMCR Reserved bit RW ROM code protect cancel bit RW ROMCP1 ROM code protect bit — (b4) VDSEL1 RW Reserved bit RW Vdet0 select bit 1 RW LVDAS Voltage detection 0 circuit start bit RW After-reset count source CSPROINI protection mode select bit RW WDTON (Watchdog Timer Start Select Bit) (b0) CSPROINI (After-Reset Count Source Protection Mode Select Bit) (b7) These bits select the state of watchdog timer after reset. Set the WDTON bit to 0 (watchdog timer starts automatically after reset) when setting the CSPROINI bit to 0 (count source protection mode enabled after reset). Refer to 15. “Watchdog Timer” for details of the watchdog timer and count source protection mode. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 63 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 6. Resets ROMCR (ROM Code Protect Cancel Bit) (b2) ROMCP1 (ROM Code Protect Bit) (b3) This bit prevents reading and changing of flash memory in parallel I/O mode. Table 6.5 ROM Code Protection Bit Setting ROMCR bit 0 0 1 1 ROMCP1 0 1 0 1 ROM Code Protection Cancelled Enabled Cancelled VDSEL1 (Vdet0 Select Bit 1) (b5) Set the VDSEL1 bit to 0 (Vdet0 is 2.85 V) when using power-on reset or voltage monitor 0 reset. Refer to 6.4.10 “Cold Start-Up/Warm Start-Up Discrimination”. LVDAS (Voltage Detection 0 Circuit Start Bit) (b6) Set the LVDAS bit to 0 (voltage monitor 0 reset enabled after hardware reset) when using power-on reset. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 64 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 6. Resets 6.4 6.4.1 Operations Status After Reset The status of SFRs after reset depends on the reset type. Refer to values after reset in 4. “Special Function Registers (SFRs)”. Table 6.6 lists Pin Status When RESET Pin Level is Low, Figure 6.2 shows CPU Register Status after Reset, and Figure 6.3 shows Reset Sequence. Table 6.6 Pin Status When RESET Pin Level is Low Status (1) Pin Name P0 P1 Single-Chip Mode (CNVSS = VSS) Input port Input port Microprocessor Mode (CNVSS = VCC1, P5_5 = high) BYTE = VSS Data input Data input Address output (undefined) BYTE = VCC1 Data input Input port Address output (undefined) Boot Mode (CNVSS = VCC1, P5_5 = low) Input port Input port Input port P2, P3, Input port P4_0 to P4_3 P4_4 Input port CS0 output (High level is output) CS0 output (High level is output) Input port Input port CE input (2) P4_5 to Input port P4_7 P5_0 P5_1 P5_2 P5_3 P5_4 Input port Input port Input port Input port Input port Input port (pulled high) WR output (High level is output) BHE output (undefined) RD output (High level is output) Input port (pulled high) WR output (High level is output) BHE output (undefined) RD output (High level is output) Input port Input port Input port Input port BCLK output BCLK output HLDA output HLDA output (The output value depends (The output value depends on the input to the HOLD pin) on the input to the HOLD pin) HOLD input (2) HOLD input (2) P5_5 P5_6 P5_7 Input port Input port Input port EPM input (3) ALE output (Low level is output) RDY input ALE output (Low level is output) RDY input Input port Input port Input port P6, P7, Input port P8, P9, P10 Input port Input port Notes: 1. These two columns show the valid pin state when the internal power supply voltage has stabilized after power on. The pin state is undefined until the internal power supply voltage stabilizes. 2. Input a high-level signal. 3. Input a low-level signal. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 65 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 6. Resets b15 b0 0000h 0000h 0000h 0000h 0000h 0000h 0000h Data register (R0) Data register (R1) Data register (R2) Data register (R3) Address register (A0) Address register (A1) Frame base register (FB) b0 b19 00000h Content of addresses FFFFEh to FFFFCh b15 b0 Interrupt table register (INTB) Program counter (PC) 0000h 0000h 0000h b15 b0 User stack pointer (USP) Interrupt stack pointer (ISP) Static base register (SB) 0000h b15 b8 b7 b0 Flag register (FLG) IPL Figure 6.2 UI OB S Z DC CPU Register Status after Reset REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 66 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 6. Resets VCC1, VCC2 XIN Microprocessor mode BYTE = high RESET td(P-R) More than f(OCOS) BCLK 48 cycles (fOCO-S divided by 8 x 48) BCLK Address FFFFCh FFFFDh FFFFEh Content of reset vector RD WR CS0 Microprocessor mode BYTE = low Address FFFFCh FFFFEh Content of reset vector RD WR CS0 Single-chip mode Address FFFFCh Content of reset vector FFFFEh Figure 6.3 Reset Sequence REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 67 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 6. Resets 6.4.2 Hardware Reset This reset is triggered by the R ESET p in. If the power supply voltage meets the recommended operating conditions, the MCU resets the pins, CPU, and SFRs when a low-level signal is applied to the RESET pin. When the signal applied to the RESET pin changes from low to high, the MCU executes the program at the address indicated by the reset vector. The fOCO-S divided by 8 is automatically selected as the CPU clock after reset. The HWR bit in the RSTFR register becomes 1 (hardware reset detected) after hardware reset. Refer to 4. “Special Function Registers (SFRs)” for the rest of the SFR states after reset. The internal RAM is not reset. When a low-level signal is applied to the RESET pin while writing data to the internal RAM, the internal RAM is in an undefined state. The procedures for generating a hardware reset are as follows: When Power Supply is Stable (1) Apply a low-level signal to the RESET pin. (2) Wait for f(OCOS). (3) Apply a high-level signal to the RESET pin. When Power is Turned on (4) Apply a low-level signal to the RESET pin. (5) Raise the power supply voltage to the recommended operating level. (6) Wait for td(P-R) until the internal voltage stabilizes. (7) Wait for f(OCOS). (8) Apply a high-level signal to the RESET pin. Figure 6.4 shows an Example Reset Circuit. Recommended operating VCC1 voltage 0V RESET VCC1 RESET 0.2 VCC1 or below 0V td(P-R) + f(OCOS) or above Note : 1. If VCC1 > VCC2, make sure that the VCC2 voltage is lower than that of VCC1 when the power is turned on or off. Figure 6.4 Example Reset Circuit 0.2 VCC1 or below REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 68 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 6. Resets 6.4.3 Power-On Reset Function When the RESET pin is connected to the VCC1 pin via a pull-up resistor, and the VCC1 pin voltage level rises while the rise gradient is trth or more, the power-on reset function is enabled and the MCU resets its pins, CPU, and SFRs. Also, when a capacitor is connected to the RESET pin, always keep the voltage to the RESET pin 0.8 VCC or more. When the input voltage to the VCC1 pin reaches the Vdet0 level or above, the fOCO-S starts counting. When the fOCO-S count reaches 32, the internal reset signal is held high and the MCU executes the program at the address indicated by the reset vector. The fOCO-S divided by 8 is automatically selected as the CPU clock after reset. The CWR bit in the RSTFR register becomes 0 (cold start-up) after power-on reset. Refer to 4. “Special Function Registers (SFRs)” for the remaining SFR states after reset. The internal RAM is not reset. Use the voltage monitor 0 reset together with the power-on reset. Set the LVDAS bit in the OFS1 address to 0 (voltage monitor 0 reset enabled after hardware reset) to use the power-on reset. In this case, the voltage monitor 0 reset is enabled (the VW0C0 bit and bit 6 in the VW0C register are 1 and the VC25 bit in the VCR2 register is 1). Do not set these bits to 0 by a program. Refer to 7. “Voltage Detector” for details of the voltage monitor 0 reset. Figure 6.5 shows Example of Power-On Reset Circuit and Operation. VCC 4.7 kΩ (reference) RESET Vdet0 trth External power VCC Vpor1 tw(por1) Sampling clock of digital filter × 4 cycles trth Vpor2 Vdet0 Internal reset signal (low active) 1 × 32 fOCO-S Power-on reset function 1 × 32 fOCO-S Voltage monitor 0 reset Figure 6.5 Example of Power-On Reset Circuit and Operation REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 69 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 6. Resets 6.4.4 Voltage Monitor 0 Reset This reset is triggered by the MCU's on-chip voltage detection 0 circuit. The voltage detection 0 circuit monitors the voltage applied to the VCC1 pin (Vdet0). The MCU resets the pins, CPU, and SFRs when the voltage applied to the VCC1 pin drops to Vdet0 or below. Then, the fOCO-S starts counting when the voltage applied to the VCC1 pin rises to Vdet0 or above. The internal reset signal becomes high after 32 cycles of the fOCO-S, and then the MCU executes the program at the address indicated by the reset vector. The fOCO-S divided by 8 is automatically selected as the CPU clock after reset. The CWR bit in the RSTFR register becomes 0 (cold start-up) after voltage monitor 0 reset. Refer to 4. “Special Function Registers (SFRs)” for the remaining SFR states after reset. The internal RAM is not reset. When the voltage applied to the VCC1 pin drops to Vdet0 or below while writing data to the internal RAM, the internal RAM is in an undefined state. Refer to 7. “Voltage Detector” for details of the voltage monitor 0 reset. 6.4.5 Voltage Monitor 1 Reset This reset is triggered by the MCU's on-chip voltage detection 1 circuit. The voltage detection 1 circuit monitors the voltage applied to the VCC1 pin (Vdet1). When the VW1C6 bit in the VW1C register is 1 (voltage monitor 1 reset when Vdet1 passage is detected), the MCU resets the pins, CPU, and SFRs when the voltage applied to the VCC1 pin drops to Vdet1 or below. Then, after the set amount of time, the MCU executes the program at the address indicated by the reset vector. The fOCO-S divided by 8 is automatically selected as the CPU clock after reset. The LVD1R bit in the RSTFR register becomes 1 (voltage monitor 1 reset detected) after voltage monitor 1 reset. Some SFRs are not reset at voltage monitor 1 reset. Refer to 4. “Special Function Registers (SFRs)” for details. The processor mode remains unchanged since bits PM01 to PM00 in the PM0 register are not reset. The internal RAM is not reset. Refer to 7. “Voltage Detector” for details of the voltage monitor 1 reset. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 70 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 6. Resets 6.4.6 Voltage Monitor 2 Reset This reset is triggered by the MCU's on-chip voltage detection 2 circuit. The voltage detection 2 circuit monitors the voltage applied to the VCC1 pin (Vdet2). When the VW2C6 bit in the VW2C register is 1 (voltage monitor 2 reset when Vdet2 passage is detected), the MCU resets the pins, CPU, and SFRs when the voltage applied to the VCC1 pin drops to Vdet2 or below. Then, after the set amount of time, the MCU executes the program at the address indicated by the reset vector. The fOCO-S divided by 8 is automatically selected as the CPU clock after reset. The LVD2R bit in the RSTFR register becomes 1 (voltage monitor 2 reset detected) after voltage monitor 2 reset. Some SFRs are not reset at voltage monitor 2 reset. Refer to 4. “Special Function Registers (SFRs)” for details. The processor mode remains unchanged since bits PM01 to PM00 in the PM0 register are not reset. The internal RAM is not reset. Refer to 7. “Voltage Detector” for details of the voltage monitor 2 reset. 6.4.7 Oscillation Stop Detection Reset The MCU resets and stops the pins, CPU, and SFRs when the CM27 bit in the CM2 register is 0 (reset when oscillation stop detected), if it detects that the main clock oscillator has stopped. The OSDR bit in the RSTFR register becomes 1 (oscillation stop detection reset detected). Some SFRs are not reset at oscillation stop detection reset. Refer to 4. “Special Function Registers (SFRs)” for details. The processor mode remains unchanged since bits PM01 to PM00 in the PM0 register are not reset. The internal RAM is not reset. When the main clock oscillation stop is detected while writing data to the internal RAM, the internal RAM is in an undefined state. Oscillation stop detection reset is canceled by hardware reset or voltage monitor 0 reset. Refer to 8.7 “Oscillation Stop/Re-Oscillation Detect Function” for details. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 71 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 6. Resets 6.4.8 Watchdog Timer Reset The MCU resets the pins, CPU, and SFRs when the PM12 bit in the PM1 register is 1 (reset when watchdog timer underflows) and the watchdog timer underflows. Then the MCU executes the program at the address determined by the reset vector. The fOCO-S divided by 8 is automatically selected as the CPU clock after reset. The WDR bit in the RSTFR register becomes 1 (watchdog timer reset detected). Some SFRs are not reset at watchdog timer reset. Refer to 4. “Special Function Registers (SFRs)” f or details. The processor mode remains unchanged since bits PM01 to PM00 in the PM0 register are not reset. The internal RAM is not reset. When the watchdog timer underflows while writing data to the internal RAM, the internal RAM is in an undefined state. Refer to 15. “Watchdog Timer” for details. 6.4.9 Software Reset The MCU resets the pins, CPU, and SFRs when the PM03 bit in the PM0 register is 1 (MCU reset). Then the MCU executes the program at the address determined by the reset vector. The fOCO-S divided by 8 is automatically selected as the CPU clock after reset. The SWR bit in the RSTFR register becomes 1 (software reset detected). Some SFRs are not reset at software reset. Refer to 4. “Special Function Registers (SFRs)” f or details. The processor mode remains unchanged since bits PM01 to PM00 in the PM0 register are not reset. The internal RAM is not reset. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 72 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 6. Resets 6.4.10 Cold Start-Up/Warm Start-Up Discrimination The cold start-up/warm start-up discrimination detects whether or not voltage applied to the VCC1 pin drops to the RAM hold voltage or below. The reference voltage is Vdet0. Therefore, the voltage monitor 0 reset is used for cold start-up/warm start-up discrimination. Follow Table 7.6 “Steps to Set Voltage Monitor 0 Reset Related Bits” to set the bits related to the voltage monitor 0 reset. The CWR bit in the RSTFR register is 0 (cold start-up) when power is turned on. The CWR bit also becomes 0 after power-on reset or voltage monitor 0 reset. The CWR bit becomes 1 (warm start-up) by writing 1 by a program and remains unchanged at hardware reset, voltage monitor 1 reset, voltage monitor 2 reset, oscillation stop detection reset, watchdog timer reset, or software reset. In the cold start-up/warm start-up discrimination, the Vdet0 level can be selected by setting the VDSEL1 bit in the OFS1 address. • When power-on reset or voltage monitor 0 reset is used Set the VDSEL1 bit to 0 (Vdet0 = 2.85 V (Vdet0_2)). • When neither power-on reset nor voltage monitor 0 reset is used as the user system Set the VDSEL1 bit to 1 (Vdet0 = 1.90 V (Vdet0_0)). In this case, voltage monitor 0 reset and its cancellation are based on Vdet0_0. Therefore, execute hardware reset after the cancellation of voltage monitor 0 reset. Figure 6.6 shows the Cold Start-Up/Warm Start-Up Discrimination Example. 5V VCC1 Vdet0 0V Set to 1 by a program Set to 1 by a program CWR bit Voltage monitor 0 reset The above diagram shows an instance in which the digital filter is not used. Figure 6.6 Cold Start-Up/Warm Start-Up Discrimination Example REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 73 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 6. Resets 6.5 6.5.1 Notes on Resets Power Supply Rising Gradient When supplying power to the MCU, make sure that the power supply voltage applied to the VCC1 pin meets the SVCC conditions. Standard Min. Typ. Max. 0.05 Symbol SVCC Parameter Power supply rising gradient (VCC1) (Voltage range: 0 to 2) Unit V/ms Voltage SVCC Power supply rising gradient (VCC1) 2V SVCC 0V Figure 6.7 Timing of SVCC Time 6.5.2 Power-On Reset Use the voltage monitor 0 reset together with the power-on reset. To use power-on reset, set the LVDAS bit in the OFS1 address to 0 (voltage monitor 0 reset enabled after hardware reset). In this case, the voltage monitor 0 reset is enabled (the VW0C0 bit and bit 6 in the VW0C register are 1, and the VC25 bit in the VCR2 register is 1) after power-on reset. Do not disable the bits by a program. 6.5.3 OSDR Bit (Oscillation Stop Detection Reset Detection Flag) When the oscillation stop detection reset is generated, the MCU is reset and then stopped. This state is canceled by hardware reset or voltage monitor 0 reset. Note that the OSDR bit remains unchanged at hardware reset, but is set to 0 (not detected) at voltage monitor 0 reset. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 74 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 7. Voltage Detector 7. 7.1 Voltage Detector Introduction The voltage detection circuit monitors the voltage applied to the VCC1 pin. This circuit can be programmed to monitor the VCC1 input voltage. Alternately, voltage monitor 0 reset, voltage monitor 1 interrupt, voltage monitor 1 reset, voltage monitor 2 interrupt, and voltage monitor 2 reset can also be used. Table 7.1 lists the Voltage Detector Specifications and Figure 7.1 shows Voltage Detection Circuit. Table 7.1 VCC1 monitor Voltage Detector Specifications Item Voltage to monitor Detection target Monitor Voltage Detection 0 Vdet0 Whether passing Vdet0 by rising or falling None Voltage Detection 1 Vdet1 Whether passing Vdet1 by rising or falling VW1C3 bit in VW1C register Whether VCC1 is higher or lower than Vdet1 Voltage Detection 2 Vdet2 Whether passing Vdet2 by rising or falling VC13 bit in VCR1 register Whether VCC1 is higher or lower than Vdet2 Voltage monitor 2 reset Reset at Vdet2 > VCC1; restart CPU operation after a specified time Voltage monitor 2 interrupt Interrupt request at Vdet2 > VCC1 and VCC1 > Vdet2 when digital filter is enabled; interrupt request at Vdet2 > VCC1 or VCC1 > Vdet2 when digital filter is disabled Available (Divide-by-n of fOCO-S) ×3 n: 1, 2, 4, 8 Process when voltage is detected Reset Voltage monitor 0 reset Reset at Vdet0 > VCC1; restart CPU operation at VCC1 > Vdet0 Voltage monitor 1 reset Reset at Vdet1 > VCC1; restart CPU operation after a specified time Voltage monitor 1 interrupt Interrupt request at Vdet1 > VCC1 and VCC1 > Vdet1 when digital filter is enabled; interrupt request at Vdet1 > VCC1 or VCC1 > Vdet1 when digital filter is disabled Interrupt None Digital filter Switch enabled/ disabled Sampling time Available (Divide-by-n of fOCO-S) ×3 n: 1, 2, 4, 8 Available (Divide-by-n of fOCO-S) ×3 n: 1, 2, 4, 8 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 75 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 7. Voltage Detector VCC1 VC27 + Internal reference voltage Voltage detection 2 signal - ≥ Vdet2 VC13 bit in the VCR1 register VC26 + - Voltage detection 1 signal ≥ Vdet1 VW1C3 bit in the VW1C register VC25 + - Voltage detection 0 signal ≥ Vdet0 Figure 7.1 Voltage Detection Circuit REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 76 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 7. Voltage Detector 7.2 Registers Register Structure Table 7.2 Address 0019h 001Ah 0026h 0028h 002Ah 002Bh 002Ch Register Name Voltage Detection 2 Circuit Flag Register Voltage Detection Circuit Operation Enable Register Voltage Monitor Function Select Register Voltage Detection 1 Level Select Register Voltage Monitor 0 Circuit Control Register Voltage Monitor 1 Circuit Control Register Voltage Monitor 2 Circuit Control Register Register Symbol After Reset VCR1 0000 X000b (1) VCR2 000X 0000b (2) 001X 0000b (3) VWCE VD1LS VW0C VW1C VW2C 00h (4) 0000 1010b (4) 1100 1X10b (2) 1100 1X11b (3) 1000 XX10b (1) 1000 0X10b (1) Notes: 1. Hardware reset, power-on reset, or voltage monitor 0 reset 2. When the LVDAS bit of address OFS1 is 1 at hardware reset 3. This value shows the value after any of the following resets. - Voltage monitor 0 reset - When the LVDAS bit of address OFS1 is 0 at hardware reset - Power-on reset 4. Hardware reset, power-on reset, voltage monitor 0 reset, voltage monitor 1 reset or voltage monitor 2 reset REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 77 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 7. Voltage Detector 7.2.1 Voltage Detection 2 Circuit Flag Register (VCR1) Voltage Detection 2 Circuit Flag Register b7 b6 b5 b4 b3 b2 b1 b0 0000 000 Symbol VCR1 Address 0019h After Reset 0000 X000b (hardware reset, power-on reset, voltage monitor 0 reset) Function Set to 0 0 : VCC1 < Vdet2 1 : VCC1 ≥ Vdet2 or voltage detection circuit disabled Set to 0 RW RW Bit Symbol — (b2-b0) Bit Name Reserved bits VC13 Low-voltage monitor flag RO — (b7-b4) Reserved bits RW This register does not change at voltage monitor 1 reset, voltage monitor 2 reset, oscillation stop detection reset, watchdog timer reset, or software reset. VC13 (Low-Voltage Monitor Flag) (b3) The VC13 bit is enabled when the VW12E bit in the VWCE register is 1 (voltage detection 1 and 2 circuits enabled) and the VC27 bit in the VCR2 register is 1 (voltage detection 2 circuit enabled). Condition to become 0: • VCC1 < Vdet 2 (when the VW12E bit is 1 and the VC27 bit is 1) Condition to become 1: • VCC1 ≥ Vdet 2 (when the VW12E bit is 1 and the VC27 bit is 1) • The VC27 bit in the VCR2 register is 0 (voltage detector 2 disabled). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 78 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 7. Voltage Detector 7.2.2 Voltage Detection Circuit Operation Enable Register (VCR2) Voltage Detection Circuit Operation Enable Register b7 b6 b5 b4 b3 b2 b1 b0 0000 Symbol VCR2 Bit Symbol — (b3-b0) — (b4) VC25 Address 001Ah Bit Name Reserved bits Set to 0 After Reset 000X 0000b (1) 001X 0000b (2) Function RW RW No register bit. If necessary, set to 0. Read as undefined value 0 : Disable voltage detection 0 circuit 1 : Enable voltage detection 0 circuit 0 : Disable voltage detection 1 circuit 1 : Enable voltage detection 1 circuit 0 : Disable voltage detection 2 circuit 1 : Enable voltage detection 2 circuit — Voltage detection 0 enable bit RW VC26 Voltage detection 1 enable bit RW VC27 Voltage detection 2 enable bit RW Notes : 1. When the LVDAS bit of address OFS1 is 1 at hardware reset 2. This value shows the value after any of the following resets: - Voltage monitor 0 reset - When the LVDAS bit of address OFS1 is 0 at hardware reset - Power-on reset Write to the VCR2 register after setting the PRC3 bit in the PRCR register to 1 (write enabled). This register does not change at voltage monitor 1 reset, voltage monitor 2 reset, oscillation stop detection reset, watchdog timer reset, or software reset. VC25 (Voltage Detection 0 Enable Bit) (b5) To use voltage monitor 0 reset, set the VC25 bit to 1 (voltage detection 0 circuit enabled). After changing the VC25 bit to 1, the detection circuit starts operating when the td(E-A) elapses. VC26 (Voltage Detection 1 Enable Bit) (b6) The voltage detection 1 circuit is enabled when the VW12E bit in the VWCE register is set to 1 (voltage detection 1 and 2 circuits enabled) and the VC26 bit is set to 1 (voltage detection 1 circuit enabled). Set bits VW12E and VC26 to 1 under the following conditions: • When using voltage monitor 1 interrupt/reset • When using bits VW1C2 and VW1C3 in the VW1C register The detection circuit does not start operation until td(E-A) elapses after the VC26 bit is changed from 0 to 1. VC27 (Voltage Detection 2 Enable Bit) (b7) The voltage detection 2 circuit is enabled when the VW12E bit in the VWCE register is set to 1 (voltage detection 1 and 2 circuits enabled) and the VC27 bit is set to 1 (voltage detection 2 circuit enabled). Set bits VW12E and VC27 to 1 under the following conditions: • When using voltage monitor 2 interrupt/reset • When using the VC13 bit in the VCR1 register • When using the VW2C2 bit in the VW2C register The detection circuit does not start operation until td(E-A) elapses after the VC27 bit is changed from 0 to 1. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 79 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 7. Voltage Detector 7.2.3 Voltage Monitor Function Select Register (VWCE) Voltage Monitor Function Select Register b7 b6 b5 b4 b3 b2 b1 b0 0000000 Symbol VWCE Address 0026h After Reset 00h (hardware reset, power-on reset, voltage monitor 0 reset, voltage monitor 1 reset, voltage monitor 2 reset) Function RW RW Bit Symbol VW12E — (b7-b1) Bit Name Voltage detection 1, 2 circuit 0 : Voltage detection 1 and 2 circuits disabled enable bit 1 : Voltage detection 1 and 2 circuits enabled Reserved bits Set to 0 RW Set the PCR3 bit in the PRCR register to 1 (write enabled) before the VWCE register is rewritten. This register does not change at watchdog timer reset, oscillation stop detection reset, or software reset. VW12E Bit Set the VW12E bit to 1 (enabled) when either or both of bits VC26 and VC27 in the VCR2 register are 1 (enabled). 7.2.4 Voltage Detection 1 Level Select Register (VD1LS) Voltage Detection 1 Level Select Register b7 b6 b5 b4 b3 b2 b1 b0 0000 Symbol VD1LS Address 0028h After Reset 0000 1010b (Hardware reset, power-on reset, voltage monitor 0 reset, voltage monitor 1 reset, voltage monitor 2 reset) Function RW RW b3 b2 b1 b0 Bit Symbol VD1LS0 Bit Name VD1LS1 Vdet1 Select Bit VD1LS2 0 1 1 0 : 3.09 V (Vdet1_6) 1 0 1 1 : 3.84 V (Vdet1_B) 1 1 1 1 : 4.44 V (Vdet1_F) Do not set values other than the above RW RW VD1LS3 — (b7-b4) RW Reserved bits Set to 0. — Set the PCR3 bit in the PRCR register to 1 (write enabled) before the VD1LS register is rewritten. This register does not change at watchdog timer reset, oscillation stop detection reset, or software reset. The value of the VD1LS register is affected by the VW12E bit in the VWCE register. Table 7.3 lists Value of the VD1LS Register. When setting the VW12E bit to 0 and then 1 after setting a value to the VD1LS register, the setting value to the VD1LS register is returned. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 80 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 7. Voltage Detector Table 7.3 Value of the VD1LS Register VW12E Bit 0 1 Value of the VD1LS Register 0000 1010b Value set in the VD1LS register (0000 0111b when no value is set in the VD1LS register) VD1LS3-VD1LS0 (Vdet1 Select Bit) (b3-b0) To use the voltage detection 1 circuit, set the values shown in the above figure. When the voltage detection 1 circuit is not used, the values after reset can remain as is. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 81 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 7. Voltage Detector 7.2.5 Voltage Monitor 0 Circuit Control Register (VW0C) Voltage Monitor 0 Circuit Control Register b7 b6 b5 b4 b3 b2 b1 b0 11 0 Symbol VW0C Bit Symbol VW0C0 Address 002Ah Bit Name Voltage monitor 0 reset enable bit 0 : Disabled 1 : Enabled Function After Reset 1100 1X10b (1) 1100 1X11b (2) RW RW VW0C1 — (b2) — (b3) VW0F0 Voltage monitor 0 digital filter 0 : Enable digital filter disable mode select bit 1 : Disable digital filter Reserved bit Set to 0. Read as undefined value Read as undefined value b5 b4 RW RW Reserved bit RO Sampling clock select bit VW0F1 — (b7-b6) 0 0 1 1 0 : fOCO-S divided by 1 1 : fOCO-S divided by 2 0 : fOCO-S divided by 4 1 : fOCO-S divided by 8 RW Reserved bits Set to 1 RW Notes : 1. When the LVDAS bit of address OFS1 is 1 at hardware reset 2. This value shows the value after any of the following resets: - Voltage monitor 0 reset - When the LVDAS bit of address OFS1 is 0 at hardware reset - Power-on reset Set the PRC3 bit in the PRCR register to 1 (write enabled) before writing to the VW0C register. This register does not change at voltage monitor 1 reset, voltage monitor 2 reset, oscillation stop detection reset, watchdog timer reset, or software reset. VW0C0 (Voltage Monitor 0 Reset Enable Bit) (b0) The VW0C0 bit is enabled when the VC25 bit in the VCR2 register is 1 (voltage detection 0 circuit enabled). Set the VW0C0 bit to 0 (disabled) when the VC25 bit is 0 (voltage detection 0 circuit disabled). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 82 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 7. Voltage Detector 7.2.6 Voltage Monitor 1 Circuit Control Register (VW1C) Voltage Monitor 1 Circuit Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol VW1C Address 002Bh After Reset 1000 XX10b(hardware reset, power-on reset, voltage monitor 0 reset) Function 0 : Disabled 1 : Enabled RW RW Bit Symbol VW1C0 Bit Name Voltage monitor 1 interrupt/ reset enable bit VW1C1 Voltage monitor 1 digital filter 0 : Enable digital filter disable mode select bit 1 : Disable digital filter Voltage change detection flag Voltage detection 1 signal monitor flag 0 : Not detected 1 : Vdet1 passage detected 0 : VCC1 < Vdet1 1 : VCC1 ≥ Vdet1 or voltage detection 1 circuit disabled b5 b4 RW VW1C2 RW VW1C3 RO VW1F0 Sampling clock select bit VW1F1 Voltage monitor 1 circuit mode select bit Voltage monitor 1 interrupt/ reset generation condition select bit 0 0 1 1 0 : fOCO-S divided by 1 1 : fOCO-S divided by 2 0 : fOCO-S divided by 4 1 : fOCO-S divided by 8 RW VW1C6 0 : Voltage monitor 1 interrupt at Vdet1 passage 1 : Voltage monitor 1 reset at Vdet1 passage 0 : When VCC1 reaches Vdet1 or above 1 : When VCC1 reaches Vdet1 or below RW VW1C7 RW Set the PRC3 bit in the PRCR register to 1 (write enabled) before writing to the VW1C register. The VW1C2 bit may become 1 when the VW1C register is rewritten. Therefore, set the VW1C2 bit to 0 after rewriting the VW1C register. VW1C0 (Voltage Monitor 1 Interrupt/Reset Enable Bit) (b0) The VW1C0 bit is enabled when the VW12E bit in the VWCE register is 1 (voltage detection 1 and 2 circuits enabled) and the VC26 bit in the VCR2 register is 1 (voltage detection 1 circuit enabled). Set the VW1C0 bit to 0 (disabled) when the VC26 bit is 0 (voltage detection 1 circuit disabled). VW1C1 (Voltage Monitor 1 Digital Filter Disable Mode Select Bit) (b1) After using the voltage monitor 1 interrupt to exit stop mode, to use it again to exit stop mode, set the VW1C1 bit to 0 first, and then to 1. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 83 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 7. Voltage Detector VW1C2 (Voltage Change Detection Flag) (b2) The VW1C2 bit is enabled when the VC26 bit in the VCR2 register is 1 (voltage detection 1 circuit enabled). The VW1C2 remains unchanged even if 1 is written by a program. Condition to become 0: • Writing 0 by a program Condition to become 1: Table 7.4 WV1C1 0 1 Conditions Under which the VW1C2 Bit Becomes 1 Bit Setting VW1C6 0 1 0 1 VW1C7 0 or 1 1 0 1 1 Conditions under Which the VW1C2 Bit Becomes 1 The VW1C3 bit changes (from 0 to 1 and from 1 to 0). The VW1C3 bit changes from 1 to 0. The VW1C3 bit changes from 0 to 1. The VW1C3 bit changes from 1 to 0. The VW1C3 bit changes from 1 to 0. Note: 1. Do not set values not listed above. VW1C3 (Voltage Detection 1 Signal Monitor Flag) (b3) The VW1C3 bit is enabled when the VW12E bit in the VWCE register is 1 (voltage detection 1 and 2 circuits enabled) and the VC26 bit in the VCR2 register is 1 (voltage detection 1 circuit enabled). Condition to become 0: • VCC1 < Vdet1 (when the VW12E bit is 1 and the VC26 bit is 1) Condition to become 1: • VCC1 ≥ Vdet1 (when the VW12E bit is 1 and the VC26 bit is 1) • The VC26 bit in the VCR2 register is 0 (voltage detection 1 circuit disabled). VW1C6 (Voltage Monitor 1 Circuit Mode Select Bit) (b6) The VW1C6 bit is enabled when the VW1C0 bit is 1 (voltage monitor 1 interrupt/reset enabled). VW1C7 (Voltage Monitor 1 Interrupt/Reset Generation Condition Select Bit) (b7) The voltage monitor 1 interrupt/reset generation condition can be selected by the VW1C7 bit when the VW1C6 bit is 0 (voltage monitor 1 interrupt at Vdet1 passage) and the VW1C1 bit is 1 (digital filter disabled). When the VW1C6 bit is 1 (voltage monitor 1 reset at Vdet1 passage), set the VW1C7 bit to 1 (when VCC1 reaches Vdet1 or below). (Do not set the VW1C7 bit to 0.) When the VW1C1 bit is 0 (digital filter enabled), regardless of the VW1C7 bit setting, the voltage monitor 1 interrupt is generated when VCC1 reaches Vdet1 or above and also when VCC1 reaches Vdet1 or below. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 84 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 7. Voltage Detector 7.2.7 Voltage Monitor 2 Circuit Control Register (VW2C) Voltage Monitor 2 Circuit Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol VW2C Address 002Ch After Reset 1000 0X10b (hardware reset, power-on reset, voltage monitor 0 reset) Function 0 : Disabled 1 : Enabled RW RW Bit Symbol VW2C0 Bit Name Voltage monitor 2 interrupt/ reset enable bit VW2C1 Voltage monitor 2 digital filter 0 : Enable digital filter disable mode select bit 1 : Disable digital filter Voltage change detection flag WDT detection flag 0 : Not detected 1 : Vdet2 passage detected 0 : Not detected 1 : Watchdog timer underflow detected b5 b4 RW VW2C2 RW VW2C3 RW VW2F0 Sampling clock select bit VW2F1 Voltage monitor 2 circuit mode select bit Voltage monitor 2 interrupt/ reset generation condition select bit 0 0 1 1 0 : fOCO-S divided by 1 1 : fOCO-S divided by 2 0 : fOCO-S divided by 4 1 : fOCO-S divided by 8 RW VW2C6 0 : Voltage monitor 2 interrupt at Vdet2 passage 1 : Voltage monitor 2 reset at Vdet2 passage 0 : When VCC1 reaches Vdet2 or above 1 : When VCC1 reaches Vdet2 or below RW VW2C7 RW Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VW2C register. When rewriting the VW2C register, the VW2C2 bit may become 1. Set the VW2C2 bit to 0 after rewriting the VW2C register. The VW2C3 bit does not change at voltage monitor 1 reset, voltage monitor 2 reset, oscillation stop detection reset, watchdog timer reset, or software reset. VW2C0 (Voltage Monitor 2 Interrupt/Reset Enable Bit) (b0) The VW2C0 bit is enabled when the VW12E bit in the VWCE register is 1 (voltage detection 1 and 2 circuits enabled) and the VC27 bit in the VCR2 register is 1 (voltage detection 2 circuit enabled). Set the VW2C0 bit to 0 (disabled) when the VC27 bit is 0 (voltage detection 2 circuit disabled). VW2C1 (Voltage Monitor 2 Digital Filter Disable Mode Select Bit) (b1) After using the voltage monitor 2 interrupt to exit stop mode, to use it again to exit stop mode, set the VW2C1 bit to 0 first and then to 1. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 85 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 7. Voltage Detector VW2C2 (Voltage Change Detection Flag) (b2) The VW2C2 bit is enabled when the VC27 bit in the VCR2 register is 1 (voltage detection 2 circuit enabled). The VW2C2 remains unchanged even if 1 is written by a program. Condition to become 0: • Writing 0 by a program Condition to become 1: Table 7.5 WV2C1 0 1 Conditions Under which the VW2C2 Bit Becomes 1 Bit Setting VW2C6 0 1 0 1 VW2C7 0 or 1 1 0 1 1 Conditions under Which the VW2C2 Bit Becomes 1 The VW1C3 bit changes (from 0 to 1 and from 1 to 0). The VW1C3 bit changes from 1 to 0. The VW1C3 bit changes from 0 to 1. The VW1C3 bit changes from 1 to 0. The VW1C3 bit changes from 1 to 0. Note: 1. Do not set values not listed above. VW2C6 (Voltage Monitor 2 Circuit Mode Select Bit) (b6) The VW2C6 bit is enabled when the VW2C0 bit is 1 (voltage monitor 2 interrupt/reset enabled). VW2C7 (Voltage Monitor 2 Interrupt/Reset Generation Condition Select Bit) (b7) The voltage monitor 2 interrupt/reset generation condition can be selected by the VW2C7 bit when the VW2C6 bit is 0 (voltage monitor 2 interrupt at Vdet2 passage) and the VW2C1 bit is 1 (digital filter disabled). When the VW2C6 bit is 1 (voltage monitor 2 reset at Vdet2 passage), set the VW2C7 bit to 1 (when VCC1 reaches Vdet2 or below). (Do not set the VW2C7 bit to 0.) When the VW2C1 bit is 0 (digital filter enabled), regardless of the VW2C7 bit setting, the voltage monitor 2 interrupt is generated when VCC1 reaches Vdet2 or above, and also when VCC2 reaches Vdet1 or below. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 86 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 7. Voltage Detector 7.3 Optional Function Select Area In the optional function select area, the MCU state after reset and the function to prevent rewrite in parallel I/O mode are selected. The optional function select area is not an SFR, and therefore cannot be rewritten by a program. Set a proper value when writing a program in flash memory. The entire optional function select area is set to FFh when the block including the optional function select area is erased. 7.3.1 Optional Function Select Address (OFS1) Optional Function Select Address 1 b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol OFS1 Bit Symbol Bit Name Address FFFFFh Function Factory Setting FFh RW WDTON Watchdog timer start select bit 0 : Watchdog timer starts automatically after reset. 1 : Watchdog timer is in a stopped state after reset. Set to 1. 0 : ROM code protection cancelled. 1 : ROMCP1 bit enabled. 0 : ROM code protection enabled. 1 : ROM code protection disabled. Set to 1. 0 : 2.85 V (Vdet0_2) 1 : 1.90 V (Vdet0_0) 0 : Voltage monitor 0 reset enabled after hardware reset. 1 : Voltage monitor 0 reset disabled after hardware reset. 0 : Count source protection mode enabled after reset. 1 : Count source protection mode disabled after reset. RW — (b1) ROMCR Reserved bit RW ROM code protect cancel bit RW ROMCP1 ROM code protect bit — (b4) VDSEL1 RW Reserved bit RW Vdet0 select bit 1 RW LVDAS Voltage detection 0 circuit start bit RW CSPROINI After-reset count source protection mode select bit RW VDSEL1 (Vdet0 Select Bit 1) (b5) The Vdet0 level used in the voltage detection 0 circuit is selectable. The voltage detection 0 circuit operates based on Vdet0. Set the VDSEL1 bit to 0 (Vdet0 is 2.85 V) when using power-on reset or voltage monitor 0 reset. Refer to 6.4.10 “Cold Start-Up/Warm Start-Up Discrimination”. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 87 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 7. Voltage Detector 7.4 7.4.1 Operations Digital Filter A digital filter can be used to monitor VCC1 input voltage. For the voltage detection i circuit (i = 0 to 2), the digital filter is enabled when the VWiC1 bit in the VWiC register is set to 0 (digital filter enabled). The fOCO-S divided by 1, 2, 4, or 8 is selected as a sampling clock. When using the digital filter, set the CM14 bit in the CM1 register to 0 (125 kHz on-chip oscillator on). The VCC1 input level is sampled by the digital filter for every sampling clock. When the same sampled level is detected two times in a row, at the next sampling timing, the internal reset signal goes low or a voltage monitor i interrupt request is generated. Therefore, when the digital filter is used, the time from when the VCC1 input voltage level passes Vdeti until when a reset or an interrupt is generated is up to three cycles of the sampling clock. Since the fOCO-S stops in stop mode, the digital filter does not function. When using the voltage detection i circuit to exit stop mode, set the VWiC1 bit in the VWiC register to 1 (digital filter disabled). Figure 7.2 shows Digital Filter Operation Example. VCC1 Up to 3 cycles of the sampling clock Up to 3 cycles of the sampling clock Vdet1 VW1C3 bit in the VW1C register Sampling timing of the digital filter VW1C2 bit in the VW1C register Internal signal (Voltage monitor 1 interrupt request) Set to 0 by a program The above diagram applies to the following cases: •The VW12E bit in the VWCE register is 1 (voltage detection 1 and 2 circuits enabled). •The VW1C0 bit in the VW1C register is 1 (voltage monitor 1 interrupt/reset enabled). •The VW1C1 bit in the VW1C register is 0 (digital filter enabled). •The VW1C6 bit in the VW1C register is 0 (voltage monitor 1 interrupt at Vdet1 passage). Figure 7.2 Digital Filter Operation Example REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 88 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 7. Voltage Detector 7.4.2 Voltage Detection 0 Circuit When the VC25 bit in the VCR2 register is 1 (voltage detection 0 circuit enabled), the voltage detection 0 circuit monitors the voltage applied to the VCC1 pin and detects whether the voltage passes Vdet0 by rising or falling. The level of Vdet0 can be selected by the VDSEL1 bit in the OFS1 address. Voltage monitor 0 reset generator VW0F1 to VW0F0 00b 01b Voltage detection 0 circuit VC25 fOCO-S 1/2 1/2 10b 1/2 11b VCC1 Internal reference voltage + - Voltage detection 0 signal Digital filter 0 1 VW0C1 When the VC25 bit is set to 0 (disabled), the voltage detection 0 signal goes high. VW0C0 Voltage monitor 0 reset signal VW0C0 to VW0C1, VW0F0 to VW0F1: Bits in the VW0C register VC25: Bit in the VCR2 register Figure 7.3 Voltage Monitor 0 Reset Generator REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 89 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 7. Voltage Detector 7.4.2.1 Voltage Monitor 0 Reset When using voltage monitor 0 reset, set the VDSEL1 bit in the OFS1 address to 0 (Vdet0 is 2.85 V (Vdet0_2)). Table 7.6 lists Steps to Set Voltage Monitor 0 Reset Related Bits. Table 7.6 Steps to Set Voltage Monitor 0 Reset Related Bits Step 1 2 3 4 When Using the Digital Filter Set the CM14 bit in the CM1 register to 0 (125 kHz on-chip oscillator enabled). When Not Using the Digital Filter Wait for digital filter sampling clock x 3 cycles. - (no wait time) Set the VC25 bit in the VCR2 register to 1 (voltage detection 0 circuit enabled). Wait for td(E (E-A). Use bits VW0F0 to VW0F1 in the VW0C register to select the digital filter sampling clock. Set the VW0C1 bit to 0 (digital filter enabled), and bits 6 and 7 to 1. Set the VW0C1 bit in the VW0C register to 1 (digital filter disabled), and bits 6 and 7 to 1. 5 6 7 Set bit 2 in the VW0C register to 0. Set bit 2 to 0 once again after procedure 4. Set the VW0C0 bit in the VW0C register to 1 (voltage monitor 0 reset enabled). When using voltage monitor 0 reset to exit stop mode, set the VW0C1 bit in the VW0C register to 1 (digital filter disabled). When voltage monitor 0 reset is generated, the CWR bit in the RSTFR register is automatically set to 0 (cold start-up). Refer to 6.4.4 “Voltage Monitor 0 Reset” for status after reset. Figure 7.4 shows Voltage Monitor 0 Reset Operation Example. VCC1 Vdet0 Digital filter sampling clock × 3 cycles When the VW0C1 bit is 0 (digital filter enabled) Internal reset signal (1) 1 × 32 fOCO-S 1 × 32 fOCO-S When the VW0C1 bit is 1 (digital filter disabled) Internal reset signal VW0C1: Bit in the VW0C register The above diagram applies under the following conditions. •The VC25 bit in the VCR2 register is 1 (voltage detection 0 circuit enabled). •The VW0C0 bit in the VW0C register is 1 (voltage monitor 0 reset enabled). The pins, CPU, and SFRs are initialized when the internal reset signal goes low. The MCU executes the program at the address indicated by the reset vector when the internal reset signal changes from low to high. Refer to 4. “SFRs” for the SFR status after reset. Note: 1. Make sure that VCC1 does not drop to 2.7 V or below during sampling time. Figure 7.4 Voltage Monitor 0 Reset Operation Example REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 90 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 7. Voltage Detector 7.4.3 Voltage Detection 1 Circuit When the VW12E bit in the VWCE register is 1 (voltage detection 1 and 2 circuits enabled) and the VC26 bit in the VCR2 register is 1 (voltage detection 1 circuit enabled), the voltage detection 1 circuit monitors the voltage applied to the VCC1 pin and detects whether the voltage passes Vdet1 by rising or falling. Voltage monitor 1 interrupt/reset generator VW1F1 to VW1F0 00b 01b Voltage detection 1 circuit fOCO-S VC26 1/2 1/2 10b 1/2 11b VW1C3 VCC1 Internal reference voltage + - Voltage detection 1 signal Digital filter VW1C1 0 1 VW1C1 Watchdog timer interrupt signal VW1C2 Voltage monitor 1 interrupt signal Voltage monitor 2 interrupt signal The voltage detection 1 signal becomes high level when the VC26 bit is set to 0 (disabled). Non-maskable interrupt signal VW1C7 Oscillation stop detection interrupt signal VW1C6 VW1C0 Voltage monitor 1 reset signal VW1C0 to VW1C3, VW1F0 to VW1F1, VW1C6 to VW1C7 : Bits in the VW1C register VC26 : Bit in the VCR2 register Figure 7.5 Voltage Monitor 1 Interrupt/Reset Generator 7.4.3.1 Monitoring Vdet1 Set the VW12E bit in the VWCE register to 1 (voltage detection 1 and 2 circuits enabled) and the VC26 bit in the VCR2 register to 1 (voltage detection 1 circuit enabled). Vdet1 can be monitored by using the VW1C3 bit in the VW1C register after td(E-A) elapses. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 91 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 7. Voltage Detector 7.4.3.2 Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Table 7.7 lists Steps to Set Voltage Monitor 1 Interrupt/Reset Related Bits. Table 7.7 Steps to Set Voltage Monitor 1 Interrupt/Reset Related Bits When Using the Digital Filter Step Voltage Monitor 1 Interrupt Voltage Monitor 1 Reset When Not Using the Digital Filter Voltage Monitor 1 Interrupt Voltage Monitor 1 Reset 1 2 3 4 5 6 7 Set the CM14 bit in the CM1 register to 0 (125 kHz on-chip oscillator on) Wait for digital filter sampling clock x 3 cycles. - (no wait time) Set the VW12E bit in the VWCE register to 1 (voltage detection 1 and 2 circuits enabled). Set bits VD1LS3 to VD1LS0 in the VD1LS register to select Vdet1. Set the VC26 bit in the VCR2 register to 1 (voltage detection 1 circuit enabled). Wait for td(E (E-A). Use bits VW1F0 to VW1F1 in the VW1C register to select the digital filter sampling clock. Set the VW1C1 bit in the VW1C register to 0 (digital filter enabled). Set the VW1C6 bit in the VW1C register to 0 (voltage monitor 1 interrupt mode). Set the VW1C6 bit in the VW1C register to 1 (voltage monitor 1 reset mode). Use the VW1C7 bit in the VW1C register to select the timing of the interrupt and reset request. (1) Set the VW1C1 bit in the VW1C register to 1 (digital filter disabled). Set the VW1C6 bit in the VW1C register to 0 (voltage monitor 1 interrupt mode). Set the VW1C6 bit in the VW1C register to 1 (voltage monitor 1 reset mode). 8 (2) 9 (2) 10 11 Set the VW1C2 bit in the VW1C register to 0 (Vdet1 passage not detected). Set the VW1C0 bit in the VW1C register to 1 (voltage monitor 1 interrupt/reset enabled). Notes: 1. Set the VW1C7 bit to 1 (when VCC reaches Vdet1 or below) for the voltage monitor 1 reset. 2. When the VW1C0 bit is 0, procedures 7, 8, and 9 can be executed simultaneously (with one instruction). When using voltage monitor 1 interrupt or voltage monitor 1 reset to exit stop mode, set the VW1C1 bit in the VW1C register to 1 (digital filter disabled). When voltage monitor 1 reset is generated, the LVD1R bit in the RSTFR register is automatically set to 1 (voltage monitor 1 reset detected). Refer to 6.4.5 “Voltage Monitor 1 Reset” for status after reset. Figure 7.6 shows Voltage Monitor 1 Interrupt/Reset Operation Example. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 92 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 7. Voltage Detector VCC1 Vdet1 VW1C3 bit Digital filter sampling clock × 3 c ycles VW1C2 bit When the VW1C1 bit is 0 (digital filter enabled) Set to 0 by a program Voltage monitor 1 interrupt request (when VW1C6 is 0) Internal reset signal (when VW1C6 is 1) Set to 0 by a program When the VW1C1 bit is 1 (digital filter disabled) and the VW1C7 bit is 0 (when VCC1 reaches Vdet1 or above) VW1C2 bit Voltage monitor 1 interrupt request (when VW1C6 is 0) Set to 0 by a program VW1C2 bit When the VW1C1 bit is 1 (digital filter Voltage monitor 1 disabled) and the interrupt request VW1C7 bit is 1 (when VCC1 reaches Vdet1 (when VW1C6 is 0) or below) Internal reset signal (when VW1C6 is 1) Set to 0 automatically by accepting an interrupt request Set to 0 automatically by accepting an interrupt request Digital filter sampling clock × 3 c ycles Set to 0 automatically by accepting an interrupt request VW1C1, VW1C2, VW1C3, VW1C6, VW1C7 : Bits in the VW1C register The above diagram applies under the following conditions: • The VC26 bit in the VCR2 register is 1 (voltage detection 1 circuit enabled). • The VW1C0 bit in the VW1C register is 1 (voltage monitor 1 interrupt/reset enabled). Note: 1. When not using the voltage monitor 0 reset, operate at 2.7 V or above (VCC1). Figure 7.6 Voltage Monitor 1 Interrupt/Reset Operation Example REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 93 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 7. Voltage Detector 7.4.4 Voltage Detection 2 Circuit When the VW12E bit in the VWCE register is 1 (voltage detection 1 and 2 circuits enabled) and the VC27 bit in the VCR2 register is 1 (voltage detection 2 circuit enabled), the voltage detection 2 circuit monitors the voltage applied to the VCC1 pin and detects whether the voltage passes Vdet2 by rising or falling. Voltage monitor 2 interrupt/reset generator VW2F1 to VW2F0 00b 01b Voltage detection 2 circuit fOCO-S VC27 VC13 VCC1 Internal reference voltage + - 1/2 1/2 10b 11b 1/2 Watchdog timer interrupt signal Voltage detection 2 signal Digital filter VW2C7 0 1 VW2C1 VW2C2 Voltage monitor 1 interrupt signal Voltage monitor 2 interrupt signal Non-maskable The voltage detection 2 signal becomes high level when the VC27 bit is set to 0 (disabled). interrupt signal Oscillation stop detection interrupt signal VW2C0 VW2C6 Voltage monitor 2 reset signal VW2C0 to VW2C2, VW2F0 to VW2F1, VW2C6 to VW2C7 : Bits in the VW2C register VC13 : Bit in the VCR1 register VC27 : Bit in the VCR2 register Figure 7.7 Voltage Monitor 2 Interrupt/Reset Generator 7.4.4.1 Monitoring Vdet2 Set the VW12E bit in the VWCE register to 1 (voltage detection 1 and 2 circuits enabled) and the VC27 bit in the VCR2 register to 1 (voltage detection 2 circuit enabled). Vdet2 can be monitored by using the VCA13 bit in the VCA1 register after td(E-A) elapses. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 94 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 7. Voltage Detector 7.4.4.2 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Table 7.8 lists Steps to Set Voltage Monitor 2 Interrupt/Reset Related Bits. Table 7.8 Steps to Set Voltage Monitor 2 Interrupt/Reset Related Bits When Using the Digital Filter Step 1 2 3 4 5 6 Voltage Monitor 2 Interrupt Voltage Monitor 2 Reset When Not Using the Digital Filter Voltage Monitor 2 Interrupt Voltage Monitor 2 Reset Set the CM14 bit in the CM1 register to 0 (125 kHz on-chip oscillator on) Wait for digital filter sampling clock x 3 cycles. - (no wait time) Set the VW12E bit in the VWCE register to 1 (voltage detection circuit enabled). Set the VC27 bit in the VCR2 register to 1 (voltage detection 2 circuit enabled). Wait for td(E (E-A). Use bits VW2F0 to VW2F1 in the VW2C register to select the digital filter sampling clock. Set the VW2C1 bit in the VW2C register to 0 (digital filter enabled). Set the VW2C6 bit in the VW2C register to 0 (voltage monitor 2 interrupt mode). Set the VW2C6 bit in the VW2C register to 1 (voltage monitor 2 reset mode). Use the VW2C7 bit in the VW2C register to select the timing of the interrupt and reset request. (1) Set the VW2C1 bit in the VW2C register to 1 (digital filter disabled). Set the VW2C6 bit in the VW2C register to 0 (voltage monitor 2 interrupt mode). Set the VW2C6 bit in the VW2C register to 1 (voltage monitor 2 reset mode). 7 (2) 8 (2) 9 10 Set the VW2C2 bit in the VW2C register to 0 (Vdet2 passage not detected). Set the VW2C0 bit in the VW2C register to 1 (voltage monitor 2 interrupt/reset enabled). Notes: 1. Set the VW2C7 bit to 1 (when VCC reaches Vdet2 or below) for the voltage monitor 2 reset. 2. When the VW2C0 bit is 0, procedures 6, 7, and 8 can be executed simultaneously (with one instruction). When using voltage monitor 2 interrupt or voltage monitor 2 reset to exit stop mode, set the VW2C1 bit in the VW2C register to 1 (digital filter disabled). When voltage monitor 2 reset is generated, the LVD2R bit in the RSTFR register is automatically set to 1 (voltage monitor 2 reset detected). Refer to 6.4.6 “Voltage Monitor 2 Reset” for status after reset. Figure 7.8 shows Voltage Monitor 2 Interrupt/Reset Operation Example. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 95 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 7. Voltage Detector VCC1 Vdet2 VC13 bit Digital filter sampling clock × 3 c ycles VW2C2 bit When the VW2C1 bit is 0 (digital filter enabled) Set to 0 by a program Voltage monitor 2 interrupt request (when VW2C6 is 0) Internal reset signal (when VW2C6 is 1) Set to 0 by a program VW2C2 bit Voltage monitor 2 interrupt request (when VW2C6 is 0) Set to 0 by a program When the VW2C1 bit is 1 (digital filter disabled) and the VW2C7 bit is 1 (when VCC1 reaches Vdet2 or below) VW2C2 bit Voltage monitor 2 interrupt request (when VW2 C6 is 0) Internal reset signal (when VW2C6 is 1) Set to 0 automatically by accepting an interrupt request Set to 0 automatically by accepting an interrupt request Set to 0 automatically by accepting an interrupt request Digital filter sampling clock × 3 c ycles When the VW2C1 bit is 1 (digital filter disabled) and the VW2C7 bit is 0 (when VCC1 reaches Vdet2 or above) VC13 : Bit in the VCR1 register VW2C1, VW2C2, VW2C6, VW2C7 : Bits in the VW2C register The above diagram applies under the following conditions: • The VC27 bit in the VCR2 register is 1 (voltage detection 2 circuit enabled). • The VW2C0 bit in the VW2C register is 1 (voltage monitor 2 interrupt/reset enabled). Note: 1. When not using the voltage monitor 0 reset, operate at 2.7 V or above (VCC1). Figure 7.8 Voltage Monitor 2 Interrupt/Reset Operation Example REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 96 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 7. Voltage Detector 7.5 Interrupts The voltage monitor 1 interrupt and voltage monitor 2 interrupt are non-maskable interrupts. The watchdog timer interrupt, oscillation stop and re-oscillation detection interrupt, voltage monitor 1 interrupt, and voltage monitor 2 interrupt share the same interrupt vector. When using some functions together, read the detect flags of the events in an interrupt processing program, and determine the interrupt source of the interrupt request. The detect flag for voltage monitor 1 is the VW1C2 bit in the VW1C register, and the detect flag for voltage monitor 2 is the VW2C2 bit in the VW2C register. After the interrupt source is determined, set bits VW1C2 and VW2C2 to 0 (not detected). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 97 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8. 8.1 Clock Generator Introduction The clock generator generates operating clocks for the CPU and peripheral circuits. Five circuits are incorporated to generate the system clock signals. • Main clock oscillation circuit • PLL frequency synthesizer • 40 MHz on-chip oscillator • 125 kHz on-chip oscillator • Sub clock oscillation circuit Table 8.1 lists Clock Generator Specifications, and Figure 8.1 shows System Clock Generator Circuitry. Table 8.1 Item Application Clock Generator Specifications On-Chip Oscillator Main Clock PLL Frequency 40 MHz On-Chip 125 kHz On-Chip Oscillation Circuit Synthesizer Oscillator Oscillator Sub clock Oscillation Circuit • CPU clock source • Peripheral function clock source • CPU clock source • Peripheral function clock source • CPU clock source • Peripheral function clock source • CPU and peripheral function clock sources when the main clock stops oscillating • CPU clock source • Peripheral function clock source • CPU clock source • Peripheral function clock source • CPU and peripheral function clock sources when the main clock stops oscillating • Watchdog timer count source when CPU clock is stopped Clock frequency Connectable oscillators Pins connecting to oscillator 0 to 20 MHz 10 to 32 MHz - (1) Approx. 40 MHz Approx. 125 kHZ - 32.768 kHz Crystal oscillator • Ceramic oscillator • Crystal oscillator XIN, XOUT - (1) Yes Stopped - (1) Yes Stopped - Yes Oscillating - XCIN, XCOUT Yes Stopped An externally generated clock can be input. Oscillation start, Yes stop function Oscillator status Oscillating after reset Other An externally generated clock can be input. Note: 1. The PLL frequency synthesizer uses the main clock oscillation circuit as a reference clock source. The items above are based on the main clock oscillation circuit. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 98 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator Sub-clock oscillation circuit XCIN CM04 Subclock XCOUT I/O ports CM01 to CM00 = 00b, PCLK5 = 0 PM01 to PM00 = 00b, CM01 to CM00 = 01b, PCLK5 = 0 PM01 to PM00 = 00b, CM01 to CM00 = 10b, PCLK5 = 0 f8 CLKOUT PM01 to PM00 = 00b, PM01 to PM00 = 00b, CM01 to CM00 = 00b, CM01 to CM00 = 11b, PCLK5 = 0 PCLK5 = 1 f32 fC 1/32 FRA00 40 MHz on-chip oscillator 1/2 fOCO40M fOCO-F fC fC32 fOCO40M Peripheral function clock CM14 125 kHz on-chip oscillator fOCO-S Oscillation stop/reoscillation detection circuit PLL frequency synthesizer 1 FRA01 0 fOCO-F fOCO-S f1 CM10 = 1 (stop mode) SQ XIN R Main clock CM05 Main clock oscillation circuit XOUT 1 CM21 b a c d 1 CM07 0 CPU clock BCLK 1 0 PLL clock CM11 0 Divider CM02 S WAIT instruction R Q b a 1/2 1/2 PM24 CM06 = 0 CM17 to CM16 = 01b c 1/2 1/2 1/32 1/16 CM06 = 0 CM17 to CM16 = 11b RESET Software reset NMI Interrupt request level judgement output 1/2 1/4 1/2 1/8 CM06 = 0 CM17 to CM16 = 10b CM06 = 1 Voltage monitor 0 reset Voltage monitor 1 reset Voltage monitor 2 reset Voltage monitor 1 interrupt Voltage monitor 2 interrupt Watchdog timer reset Oscillation stop detect reset CM00 to CM04, CM05 to CM07 : Bits in the CM0 register CM10, CM11, CM14, CM16, CM17 : Bits in the CM1 register PCLK5 : Bit in the PCLKR register CM21, CM27 : Bits in the CM2 register PM00, PM01 : Bits in the PM0 register PM24 : Bit in the PM2 register FRA00, FRA01 : Bits in the FRA0 register d CM06 = 0, CM17 to CM16 = 00b Detail of Divider Oscillation Stop/Re-Oscillation Detection Circuit Main Clock Pulse generation circuit for clock edge detection and charge/ discharge control CM27 = 0 Charge/ discharge circuit CM27 = 1 Reset generation circuit Oscillation stop/ re-oscillation detection interrupt generation circuit Oscillation stop detection reset Oscillation stop/ re-oscillation detection interrupt signal CM21 switch signal PLL Frequency Synthesizer 1/32 Phase comparator Main Clock Reference clock divider Charge pump Voltage control oscillator (VCO) Divider PLL clock Internal lowpass filter Figure 8.1 System Clock Generator Circuitry REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 99 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator Table 8.2 Pin Name I/O Pins I/O Type Function XIN XOUT XCIN XCOUT Input Output Input (1) Output (1) Output Output I/O pins for the main clock oscillation circuit I/O pins for a sub clock oscillation circuit CLKOUT Clock output (in single-chip mode) BCLK BCLK output (in memory expansion mode, microprocessor mode) Note: 1. Set the port direction bits which share pins to 0 (input mode). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 100 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8.2 Registers Register Structure Table 8.3 Address 0004h Register Name Processor Mode Register 0 0006h 0007h 000Ch System Clock Control Register 0 System Clock Control Register 1 Oscillation Stop Detection Register Register Symbol After Reset PM0 0000 0000b (CNVSS pin is low) 0000 0011b (CNVSS pin is high) CM0 0100 1000b CM1 0010 0000b CM2 0X00 0010b (1) 0012h Peripheral Clock Select Register PCLKR 0000 0011b 001Ch PLL Control Register 0 PLC0 0X01 X010b 001Eh Processor Mode Register 2 PM2 XX00 0X01b 0022h 40 MHz On-Chip Oscillator Control Register 0 FRA0 XXXX XX00b Note: 1. Bits CM20, CM21, and CM27 remain unchanged at oscillation stop detection reset. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 101 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8.2.1 Processor Mode Register 0 (PM0) Processor Mode Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PM0 Address 0004h After Reset 0000 0000b (CNVSS pin is held low) 0000 0011b (CNVSS pin is held high) Function b1 b0 Bit Symbol PM00 Bit Name RW RW Processor mode bit PM01 0 0 1 1 0 : Single-chip mode 1 : Memory expansion mode 0 : Do not set 1 : Microprocessor mode RW PM02 R/W mode select bit 0 : RD, BHE, WR 1 : RD, WRH, WRL Setting this bit to 1 resets the MCU. Read as 0. b5 b4 RW PM03 Software reset bit RW PM04 Multiplexed bus space select bit PM05 0 0 1 1 0 : Multiplexed bus is unused (separate bus in the entire CS space) 1 : Allocated to CS2 space 0 : Allocated to CS1 space 1 : Allocated to the entire CS space RW RW PM06 Port P4_0 to P4_3 function select bit 0 : Address output 1 : Port function (address is not output) 0 : BCLK is output 1 : BCLK is not output (pin is left in high-impedance) RW PM07 BCLK output disable bit RW Write to the PM0 register after setting the PRC1 bit in the PRCR register to 1 (write enabled). Bits PM01 to PM00 do not change at software reset, watchdog timer reset, oscillation stop detection reset, voltage monitor 1 reset, or voltage monitor 2 reset. PM07 (BCLK Output Disable Bit) (b7) This bit is enabled in memory expansion mode and microprocessor mode. A clock with the same frequency as that of the CPU clock is output as the BCLK signal from the BCLK pin. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 102 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8.2.2 System Clock Control Register 0 (CM0) System Clock Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol CM0 Bit Symbol CM00 Bit Name Address 0006h Function b1 b0 After Reset 0100 1000b RW CM01 Clock output function select bit 0 0 (valid in single-chip mode 1 only) 1 0 : I/O port P5_7 1 : Output fC 0 : Output f8 1 : Output f32 RW CM02 Wait mode peripheral function clock stop bit XCIN-XCOUT drive capacity select bit Port XC select bit 0 : Peripheral function clock f1 does not stop in wait mode 1 : Peripheral function clock f1 stops in wait mode 0 : Low 1 : High 0 : I/O ports 1 : XCIN-XCOUT oscillation function 0 : On 1 : Off 0 : CM16 and CM17 enabled 1 : Divide-by-8 mode 0 : Main clock, PLL clock or on-chip oscillator clock 1 : Sub-clock RW CM03 RW CM04 RW CM05 Main clock stop bit Main clock division select bit 0 System clock select bit RW CM06 RW CM07 RW Rewrite the CM0 register after setting the PRC0 bit in the PRCR register to 1 (write enabled). Refer to Table 9.3 “Clock Related Bit Setting and Modes” to select a clock and a mode. CM01-CM00 (Clock Output Function Select Bit) (b1-b0) The CLKOUT pin outputs can be selected. These bits are enabled when the PCLK5 bit in the PCLKR register is set to 0 (bits CM01 to CM00 enabled) in single-chip mode. When the PCLK5 bit is 1, set bits CM01 to CM00 to 00b. Table 8.4 shows CLKOUT Pin Functions for Single-Chip Mode. Table 8.4 CLKOUT Pin Functions for Single-Chip Mode CM0 Register CM01 bit CM00 bit CLKOUT Pin Output PCLKR Register PCLK5 bit 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 Only set the combinations listed above. I/O port Output fC Output f8 Output f32 Output f1 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 103 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator CM02 (Wait Mode Peripheral Function Clock Stop Bit) (b2) The CM02 bit is used to stop the peripheral function clock f1 in wait mode. The peripheral functions fC, fC32, fOCO-S, fOCO-F, and fOCO40M are not affected by the CM02 bit. When the PM21 bit in the PM2 register is set to 1 (clock change disabled), the CM02 bit remains unchanged even when written to. CM03 (XCIN-XCOUT Drive Capacity Select Bit) (b3) Setting the driving capacity to low while sub-clock oscillation is stable reduces power consumption. The CM03 bit is set to 1 (high) while the CM04 bit is 0 (P8_6 and P8_7 are I/O ports), or when entering stop mode. CM04 (Port XC Select Bit) (b4) The CM03 bit is set to 1 (high) while the CM04 bit is 0 (P8_6 and P8_7 are I/O ports). CM05 (Main Clock Stop Bit) (b5) The CM05 bit is provided to stop the main clock when selecting the low power mode or 125 kHz on-chip oscillator low power mode, or when stopping the main clock at 40 MHz on-chip oscillator mode. The CM05 bit cannot be used to detect whether the main clock is stopped or not. Refer to 8.7 “Oscillation Stop/Re-Oscillation Detect Function” for the main clock stop detection. When the PM21 bit in the PM2 register is 1 (clock change disabled), the CM05 bit remains unchanged even when written to. CM06 (Main Clock Division Select Bit) (b6) The CM06 bit becomes 1 (divide-by-8 mode) under the following conditions: • When entering stop mode • When the CM07 bit is 1 (sub clock used as CPU clock) and the CM05 bit is 1 (main clock off) CM07 (System Clock Select Bit) (b7) The CPU clock source and the peripheral function clock f1 depend on combinations of the bit status of the CM07 bit, the CM11 bit in the CM1 register, and the CM21 bit in the CM2 register. When the CM07 bit is 0 (main clock, PLL clock or on-chip oscillator clock used as CPU clock), the CPU clock source and the peripheral function clock f1 can be selected by combinations of the bit status of the CM11 bit and the CM21 bit. When the CM07 bit is 1 (sub clock used as CPU clock), the CPU clock source is fC, and the peripheral function clock f1 can be selected by combinations of the bit status of bits CM11 and CM21. When setting the PM21 bit in the PM2 register to 1 (clock change disabled), set the CM07 bit to 0 (main clock) before setting the PM21 bit to 1. When the PM21 bit is set to 1, this bit remains unchanged even when written to. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 104 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8.2.3 System Clock Control Register 1 (CM1) System Clock Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol CM1 Bit Symbol CM10 Bit Name All clock stop control bit Address 0007h Function 0 : Clock on 1 : All clocks off (stop mode) 0 : Main clock 1 : PLL clock Set to 0 After Reset 0010 0000b RW RW CM11 — (b2) CM13 System clock select bit 1 RW Reserved bit XIN-XOUT feedback resistor select bit RW 0 : Internal feedback resistor connected 1 : Internal feedback resistor not connected RW CM14 125 kHz on-chip oscillator stop 0 : 125 kHz on-chip oscillator on bit 1 : 125 kHz on-chip oscillator off XIN-XOUT drive capacity select bit 0 : Low 1 : High b7 b6 RW CM15 RW CM16 Main clock division select bit 1 CM17 0 0 1 1 0 : No division mode 1 : Divide-by-2 mode 0 : Divide-by-4 mode 1 : Divide-by-16 mode RW Rewrite the CM1 register after setting the PRC0 bit in the PRCR register to 1 (write enabled). Refer to Table 9.3 “Clock Related Bit Setting and Modes” to select a clock and a mode. CM10 (All Clock Stop Control Bit) (b0) When the CM11 bit is 1 (PLL clock), or the CM20 bit in the CM2 register is 1 (oscillation stop detection function enabled), do not set the CM10 bit to 1. When the PM21 bit in the PM2 register is 1 (clock change disabled), the CM10 bit remains unchanged even when written to (stop mode is not entered). When the CSPRO bit in the CSPR register is 1 (watchdog timer count source protection mode), the CM10 bit remains unchanged even when written to (stop mode is not entered). CM11 (System Clock Select Bit) (b1) The CM11 bit is valid when the CM21 bit in the CM2 register is set to 0 (main clock or PLL clock). The CPU clock source and the peripheral function clock f1 can be selected by the CM11 bit when the CM07 bit is 0 (main clock, PLL clock, or on-chip oscillator clock used as CPU clock). The peripheral function clock f1 can be selected by the CM11 bit when the CM07 bit is 1 (sub clock used as CPU clock). When the PM21 bit in the PM2 register is 1 (clock change disabled), the CM11 bit remains unchanged even when written to. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 105 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator CM13 (XIN-XOUT Feedback Resistor Select Bit) (b3) The CM13 bit can be used when the main clock is not used at all, or when the externally generated clock is supplied to the XIN pin. When connecting a resonator between pins XIN and XOUT, set the CM13 bit to 0 (internal feedback resistor connected). Do not set this bit to 1. When the CM10 bit is 1 (stop mode), the feedback resistor is not connected regardless of the CM13 bit status. CM14 (125 kHz On-Chip Oscillator Stop Bit) (b4) The CM14 bit can be set to 1 (125 kHz on-chip oscillator off) when the CM21 bit is 0 (main clock or PLL clock). When the CM21 bit is set to 1 (on-chip oscillator clock), the CM14 bit is automatically set to 0 (125 kHz on-chip oscillator on) and remains unchanged even when 1 is written to this bit. Note that the 125 kHz on-chip oscillator does not stop. When the CSPRO bit in the CSPR register is 1 (watchdog timer count source protection mode), the CM14 bit is automatically set to 0 (125 kHz on-chip oscillator on) and remains unchanged even when 1 is written to this bit. Note that the 125 kHz on-chip oscillator does not stop. CM15 (XIN-XOUT Drive Capacity Select Bit) (b5) When entering stop mode or the CM05 bit is set to 1 (main clock stopped) in low speed mode, the CM15 bit is automatically set to 1 (drive capacity high). CM17-CM16 (Main Clock Division Select Bit 1) (b7-b6) Bits CM17 to CM16 are valid when the CM06 bit is set to 0 (bits CM16 and CM17 enabled). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 106 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8.2.4 Oscillation Stop Detection Register (CM2) Oscillation Stop Detection Register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol CM2 Bit Symbol Bit Name Address 000Ch Function After Reset 0X00 0010b RW CM20 0: Oscillation stop and re-oscillation Oscillation stop and detection function disabled re-oscillation detection enable 1: Oscillation stop and re-oscillation bit detection function enabled System clock select bit 2 Oscillation stop and re-oscillation detection flag XIN monitor flag 0: Main clock or PLL clock 1: On-chip oscillator clock 0: Main clock stopped and re-oscillation not detected 1: Main clock stopped and re-oscillation detected 0: Main clock oscillating 1: Main clock stopped Set to 0 RW CM21 RW CM22 RW CM23 — (b5-b4) — (b6) CM27 RO Reserved bits RW No register bit. If necessary, set to 0. Read as undefined value Operation select bit (when an oscillation stop or re-oscillation is detected) 0: Oscillation stop detection reset 1: Oscillation stop/re-oscillation detection interrupt — RW Rewrite the CM2 register after setting the PRC0 bit in the PRCR register to 1 (write enabled). Bits CM20, CM21, and CM27 do not change at oscillation stop detection reset. Refer to Table 9.3 “Clock Related Bit Setting and Modes” to select a clock and a mode. CM20 (Oscillation Stop and Re-Oscillation Detection Enable Bit) (b0) Set the CM20 bit to 0 (oscillation stop and re-oscillation detection function disabled) to enter stop mode. Set the CM20 bit back to 1 (enabled) after stop mode is exited. When the PM21 bit in the PM2 register is 1 (clock change disabled), the CM20 bit remains unchanged even when being written. CM21 (System Clock Select Bit 2) (b1) When the CM07 bit is 0 (main clock, PLL clock, or on-chip oscillator clock used as CPU clock source), the CPU clock source and the peripheral function clock f1 can be selected by the CM21 bit. When the CM07 bit is 1 (sub clock used as CPU clock source), the peripheral function clock f1 can be selected by the CM21 bit. To set the CM21 bit to 1 (on-chip oscillator clock), set the FRA01 bit in the FRA0 register to select either the 125 kHz on-chip oscillator, or the 40 MHz on-chip oscillator. When the CM20 bit is 1 (oscillation stop and re-oscillation detection function enabled) and the CM23 bit is 1 (main clock stopped), do not set the CM21 bit to 0 (main clock or PLL clock). When the CM20 bit is 1 (oscillation stop and re-oscillation detection function enabled), the CM27 bit is 1 (oscillation stop and re-oscillation detection interrupt), and the main clock is used as a CPU clock source, the CM21 bit is automatically set to 1 (on-chip oscillator clock) if main clock stop is detected. See 8.7 “Oscillation Stop/Re-Oscillation Detect Function” for details. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 107 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator CM22 (Oscillation Stop and Re-Oscillation Detection Flag) (b2) Condition to become 0: • Set it to 0. Condition to become 1: • Main clock stop is detected. • Main clock re-oscillation is detected. (The CM22 bit remains unchanged even if 1 is written.) When the CM22 bit changes state from 0 to 1, an oscillation stop/re-oscillation detection interrupt is generated. Use this bit in an interrupt routine to determine the factors of interrupts between the oscillation stop and re-oscillation detection interrupt and the watchdog timer interrupt. When the CM22 bit is 1 and oscillation stop or re-oscillation is detected, an oscillation stop/re-oscillation detection interrupt is not generated. The bit is not set to 0 even if an oscillation stop/re-oscillation detection interrupt request is accepted. CM23 (XIN Monitor Flag) (b3) Determine the main clock status by reading the CM23 bit several times in the oscillation stop and reoscillation detection interrupt routine. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 108 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8.2.5 Peripheral Clock Select Register (PCLKR) Peripheral Clock Select Register b7 b6 b5 b4 b3 b2 b1 b0 00 000 Symbol PCLKR Bit Symbol Bit Name Address 0012h Function After Reset 0000 0011b RW PCLK0 Timers A and B clock select bit (clock source for timers A and B, the dead time timer, and muliti-master I2C-bus interface) SI/O clock select bit (clock source for UART0 to UART2, UART5 to UART7, SI/O3, and SI/O4) Reserved bits Clock output function extension bit (valid in single-chip mode) Reserved bits 0: f2TIMAB/f2IIC 1: f1TIMAB/f1IIC RW PCLK1 0: f2SIO 1: f1SIO RW — (b4-b2) PCLK5 — (b7-b6) Set to 0 0: Selected by bits CM01 to CM00 in the CM0 register 1: Output f1 Set to 0 RW RW RW Write to the PCLKR register after setting the PRC0 bit in the PRCR register to 1 (write enabled). PCLK5 (Clock Output Function Extension Bit) (b5) The PCLK5 bit is valid in single-chip mode. Output from the CLKOUT pin is selectable. When the PCLK5 bit is 1, set bits CM01 to CM00 to 00b. Refer to Table 8.4 “CLKOUT Pin Functions for SingleChip Mode”. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 109 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8.2.6 PLL Control Register 0 (PLC0) PLL Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PLC0 Bit Symbol PLC00 PLL multiplying factor select bit Bit Name Address 001Ch Function b2 b1 b0 After Reset 0X01 X010b RW RW PLC01 PLC02 — (b3) PLC04 Reference frequency counter set bit PLC05 — (b6) PLC07 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : Do not set 1 : Multiply-by-2 0 : Multiply-by-4 1 : Multiply-by-6 0 : Multiply-by-8 1: 0: Do not set these values 1: RW RW Reserved bit Read as undefined value b5 b4 RO 0 0 1 1 0 : No division 1 : Divide-by-2 0 : Divide-by-4 1 : Do not set RW RW No register bit. If necessary, set to 0. Read as undefined value 0 : PLL off 1 : PLL on — Operation enable bit RW Rewrite the PLC0 register after setting the PRC0 bit in the PRCR register to 1 (write enabled). PLC02-PLC00 (PLL Multiplying Factor Select Bit) (b2-b0) Write to bits PLC00 to PLC02 when the PLC07 bit is 0 (PLL off). When the PM21 bit in the PM2 register is 1 (clock change disabled), writing to bits PLC02 to PLC00 has no effect. PLC05-PLC04 (Reference Frequency Counter Set Bit) (b5-b4) Write to bits PLC05 to PLC04 when the PLC07 bit is 0 (PLL off). When the PM21 bit in the PM2 register is 1 (clock change disabled), writing to bits PLC05 to PLC04 has no effect. PLC07 (Operation Enable Bit) (b7) When the PM21 bit in the PM2 register is 1 (clock change disabled), writing to the PLC07 bit has no effect. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 110 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8.2.7 Processor Mode Register 2 (PM2) Processor Mode Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol PM2 Bit Symbol PM20 Bit Name Address 001Eh Function After Reset XX00 0X01b RW RW Specifying wait when accessing 0 : 2 waits SFR at PLL operation 1 : 1 wait System clock protection bit 0 : Clock is protected by PRCR register 1 : Clock change disabled PM21 — (b2) — (b3) PM24 RW No register bit. If necessary, set to 0. Read as 0 — Reserved bit Set to 0 0 : NMI interrupt disabled 1 : NMI interrupt enabled 0 : Provided 1 : Not provide RW NMI interrupt enable bit RW PM25 — (b7-b6) Peripheral clock fC provide bit RW No register bits. If necessary, set to 0. Read as undefined value — Rewrite the PM2 register after setting the PRC1 bit in the PRCR register to 1 (write enabled). PM20 (Specifying Wait When Accessing SFR at PLL Operation) (b0) Change the PM20 bit when the PLC07 bit is 0 (PLL off). The PM20 bit becomes enabled when the PLC07 bit in the PLC0 register is set to 1 (PLL on). PM21 (System Clock Protection Bit) (b1) The PM21 bit is used to protect the CPU clock. (See 8.6 “System Clock Protection Function”.) If the PM21 bit is set to 1, writing to the following bits has no effect. • Bits CM02, CM05, and CM07 in the CM0 register • Bits CM10 and CM11 in the CM1 register • The CM20 bit in the CM20 register • All bits in the PLC0 register Do not execute the WAIT instruction when the PM21 bit is 1. PM25 (Peripheral Clock fC Provide Bit) (b5) The PM25 bit provides fC to the real-time clock, CEC function, and remote control signal receiver. (See Figure 8.5 “Peripheral Function Clocks”.) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 111 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8.2.8 40 MHz On-Chip Oscillator Control Register 0 (FRA0) 40 MHz On-Chip Oscillator Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol FRA0 Bit Symbol FRA00 Bit Name Address 0022h Function After Reset XXXX XX00b RW RW 40 MHz on-chip oscillator start 0 : 40 MHz on-chip oscillator off bit 1 : 40 MHz on-chip oscillator on On-chip oscillator select bit 0 : 125 kHz on-chip oscillator 1 : 40 MHz on-chip oscillator FRA01 — (b7-b2) RW No register bits. If necessary, set to 0. Read as undefined value — Rewrite the FRA0 register after setting the PRC0 bit in the PRCR register to 1 (write enabled). Refer to Table 9.3 “Clock Related Bit Setting and Modes”Table 9.3 “Clock Related Bit Setting and Modes” to select a clock and a mode. FRA00 (40 MHz On-Chip Oscillator Start Bit) (b0) When using an oscillation stop/re-oscillation detection interrupt, do not set the FRA00 bit to 0 (40 MHz on-chip oscillator off), and the FRA01 bit to 1 (40 MHz on-chip oscillator). FRA01 (40 MHz On-Chip Oscillator Select Bit) (b1) Change the FRA01 bit if the both conditions below are met. • When the FRA00 bit is 1 (40 MHz on-chip oscillator on) and oscillation is stable • When the CM14 bit in the CM1 register is 0 (125 kHz on-chip oscillator on) and oscillation is stable When setting the FRA01 bit to 0 (125 kHz on-chip oscillator), do not set the FRA00 bit to 0 (40 MHz onchip oscillator off) at the same time. Set the FRA00 bit to 0 after setting the FRA01 bit to 0. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 112 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8.3 Clocks Generated by Clock Generators The clocks generated by the clock generators are described below. 8.3.1 Main Clock This clock is supplied by the main clock oscillator circuit and used as a clock source for the CPU and peripheral function clocks. After reset, the main clock is running, but is not used as a clock source for the CPU. The main clock oscillator circuit is configured by connecting a resonator between pins XIN and XOUT. The main clock oscillator circuit contains a feedback resistor, which is separated from the oscillator circuit in stop mode in order to reduce the amount of power consumed by the chip. The main clock oscillator circuit may also be configured by feeding an externally generated clock to the XIN pin. Figure 8.2 shows Main Clock Connection Examples. MCU (Built-in feedback resistor) CIN XIN Oscillator XOUT Rd VSS (1) MCU (Built-in feedback resistor) XIN External clock VCC1 VSS COUT XOUT Open Note : 1. Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the oscillator manufacturer. When the oscillation drive capacity is set to low, check if oscillation is stable in low status. Also, place a feedback resistor between XIN and XOUT if the oscillator manufacturer recommends placing the resistor externally. Figure 8.2 Main Clock Connection Examples REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 113 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator The XOUT becomes high by setting the CM05 bit in the CM0 register to 1 (main clock oscillator circuit turned off) after switching the clock source for the CPU clock to the sub clock (fC) or on-chip oscillator clock (fOCO-F, fOCO-S). In this case, the XIN is pulled high to the XOUT via the feedback resistor because the internal feedback resistor remains connected. When the main clock oscillator circuit is not used, setting the CM13 bit in the CM1 register to 1 enables to select the internal feedback resistor not connected. Perform the following steps to start or stop the main clock. Refer to 8.2 “Registers” for access to register and bit. Main clock oscillation start (1) Set the CM15 bit to 1 (drive capacity high) when a resonator is connected between pins XIN and XOUT. (2) Set the CM05 bit to 0 (main clock oscillating). (3) Wait until main clock oscillation stabilizes. (Enter the external clock when entering it from the XIN pin.) Main clock oscillation stop (1) Set the CM20 bit in the CM2 register to 0 (oscillation stop/re-oscillation detection function disabled). (2) Set the CM05 bit to 1 (stop). (3) Stop the external clock (when entering the external clock from the XIN pin). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 114 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8.3.2 PLL Clock The PLL clock is generated by the PLL frequency synthesizer. This clock is used as the clock source for the CPU and peripheral function clocks. After reset, the PLL frequency synthesizer is stopped. The PLL clock is the main clock divided by the selected values of bits PLC05 to PLC04 in the PLC0 register, and then multiplied by the selected values of bits PLC02 to PLC00. Set bits PLC05 to PLC04 to fit divided frequency between 2 MHz and 5 MHz. Figure 8.3 shows Relation between Main Clock and PLL Clock. Main clock Divided by n (1) Multiplied by m (2) PLL clock n m : 1, 2, 4 (selected by bits PLC05 to PLC04 in the PLC0 register) : 2, 4, 6, 8 (selected by bits PLC02 to PLC00 in the PLC0 register) Notes : 1. Set the frequency divided by n to between 2 MHz and 5 MHz. 2. Set 10 MHz ≤ PLL clock frequency ≤ 32 MHz Figure 8.3 Relation between Main Clock and PLL Clock Bits PLC05 to PLC04 and bits PLC02 to PLC00 can be set only once after reset. Table 8.5 lists Example Settings for PLL Clock Frequencies. Table 8.5 Example Settings for PLL Clock Frequencies Setting Value Bits PLC05 to PLC04 Bits PLC02 to PLC00 PLL Clock Main Clock 10 MHz 5 MHz 12 MHz 6 MHz 16 MHz 8 MHz 01b (divide-by-2) 00b (not divided) 10b (divide-by-4) 01b (divide-by-2) 10b (divide-by-4) 01b (divide-by-2) 010b (multiply-by-4) 010b (multiply-by-4) 100b (multiply-by-8) 100b (multiply-by-8) 100b (multiply-by-8) 100b (multiply-by-8) 20 MHz 24 MHz 32 MHz REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 115 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8.3.3 fOCO40M The fOCO40M is a 40 MHz clock (approx.), which is supplied by the 40 MHz on-chip oscillator. It is used as the clock source for φAD of AD converter. Follow the steps below to start or stop the 40 MHz on-chip oscillator clock. Refer to 8.2 “Registers” for access to register and bit. 40 MHz on-chip oscillator clock oscillation start (1) Set the FRA00 bit in the FRA0 register to 1 (40 MHz on-chip oscillator on). (2) Wait for td (OCOF). 40 MHz on-chip oscillator clock oscillation stop (1) Set the FRA01 bit in the FRA0 register to 0 (125 MHz on-chip oscillator) (when the CM27 bit is 1 (oscillation stop/re-oscillation detection interrupt)). (2) Set the FRA00 bit in the FRA0 register to 0 (40 MHz on-chip oscillator off). 8.3.4 fOCO-F The fOCO-F is a 40 MHz clock (approx.), which is supplied by the 40 MHz on-chip oscillator, divided by 2. It is used as the clock source for the CPU and peripheral function clocks. After reset, the 40 MHz on-chip oscillator is stopped. If the main clock stops oscillating and the FRA01 bit is 1 when the CM20 bit in the CM2 register is 1 (oscillation stop/re-oscillation detection function enabled), and the CM27 bit is 1 (oscillation stop/reoscillation detection interrupt), the fOCO-F is used as the clock source for the CPU. Follow the steps below to start or stop the 40 MHz on-chip oscillator clock. Refer to 8.2 “Registers” for access to registers and bits. 40 MHz on-chip oscillator clock oscillation start (1) Set the FRA00 bit in the FRA0 register to 1 (40 MHz on-chip oscillator on). (2) Wait for td (OCOF). 40 MHz on-chip oscillator clock oscillation stop (1) Set the FRA01 bit in the FRA0 register to 0 (125 MHz on-chip oscillator) (when the CM27 bit is 1 (oscillation stop/re-oscillation detection interrupt)). (2) Set the FRA00 bit in the FRA0 register to 0 (40 MHz on-chip oscillator off). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 116 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8.3.5 125 kHz On-Chip Oscillator Clock (fOCO-S) This clock is approximately 125 kHz, and is supplied by the 125 kHz on-chip oscillator. It is used as the clock source for the CPU and peripheral function clocks. In addition, when the CSPRO bit in the CSPR register is 1 (count source protection mode enabled), this clock is used as the count source for the watchdog timer (refer to 15.4.2 “Count Source Protection Mode Enabled”). After reset, the fOCO-S divided by 8 is used as the CPU clock. If the main clock stops oscillating and the FRA01 bit is 0, when the CM20 bit in the CM2 register is 1 (oscillation stop/re-oscillation detection function enabled) and the CM27 bit is 1 (oscillation stop/reoscillation detection interrupt), the 125 kHz on-chip oscillator automatically starts operating and supplying the necessary clock for the MCU. Follow the steps below to start or stop the fOCO-S. Refer to 8.2 “Registers” for access to register and bit. fOCO-S start (1) Set the CM14 bit in the CM1 register to 0 (125 kHz on-chip oscillator on). (2) Wait for td (OCOS). fOCO-S stop (1) Set the CM14 bit in the CM1 register to 1 (125 kHz on-chip oscillator off). When the CM21 bit is 1 (on-chip oscillator used as the clock source for the CPU), the CM14 bit becomes 0 (125 kHz on-chip oscillator on). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 117 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8.3.6 Sub Clock (fC) The sub clock is supplied by the sub clock oscillator circuit. This clock is used as the clock source for count sources of the CPU clock, timer A, timer B, real-time clock, CEC function, and remote control signal receiver. The sub clock oscillator circuit is configured by connecting a crystal resonator between pins XCIN and XCOUT. The sub clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed by the chip. The sub clock oscillator circuit may also be configured by feeding an externally generated clock to the XCIN pin. Figure 8.4 shows Sub Clock Connection Examples. MCU (Built-in feedback resistor) CCIN XCIN Oscillator XCOUT RCd (1) VSS CCOUT MCU (Built-in feedback resistor) XCIN External clock VCC1 VSS XCOUT Open Note : 1. Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the oscillator manufacturer. When the oscillation drive capacity is set to low, check if oscillation is stable in low status. Also, place a feedback resistor between XCIN and XCOUT if the oscillator manufacturer recommends placing the resistor externally. Figure 8.4 Sub Clock Connection Examples After reset, the sub clock is stopped. At this time, the feedback resistor is disconnected from the oscillator circuit. Follow the steps below to start the sub clock. Refer to 8.2 “Registers” for access to registers and bits. (1)Set the PU21 bit in the PUR2 register to 0 (P8_4 to P8_7 not pulled high). (2)Set bits PD8_6 and PD8_7 in the PD8 register to 0 (P8_6, P8_7 function as input ports). (3)Set the CM04 bit to 1 (XCIN-XCOUT oscillation function). Set the CM03 bit to 1 (XCIN-XCOUT drive capacity high). (4)Wait until sub clock oscillation stabilizes (enter the external clock when entering it from the XCIN pin). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 118 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8.4 CPU Clock and Peripheral Function Clocks The CPU is run by the CPU clock, and the peripheral functions are run by the peripheral function clocks. 8.4.1 CPU Clock and BCLK The CPU clock is an operating clock for the CPU and watchdog timer. Also it is used as a sampling clock of the NMI/SD digital filter. The main clock, PLL clock, fOCO-F, fOCO-S, or fC can be selected as the clock source for the CPU clock. (See Table 9.2 “Clocks in Normal Operating Mode”.) When the main clock, PLL clock, fOCO-F, or fOCO-S is selected as the clock source for the CPU clock, the selected clock source can be divided by 1 (no division), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit in the CM0 register, and bits CM17 to CM16 in the CM1 register to select a frequencydivided value. When fC is selected as the clock source for the CPU clock, it is not divided and is used directly as the CPU clock. After reset, the fOCO-S divided by 8 is used as the CPU clock. Note that when entering stop mode or when the CM05 bit in the CM0 register is set to 1 (stop) in low-speed mode, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode). BCLK is a bus reference clock. In memory expansion or microprocessor mode, a BCLK signal with the same frequency as the CPU clock can be output from the BCLK pin by setting the PM07 bit in the PM0 register to 0 (output enabled). 8.4.2 Peripheral Function Clocks (f1, fOCO40M, fOCO-F, fOCO-S, fC32, fC) f1, fOCO40M, fOCO-F, fOCO-S, and fC32 are operating clocks for the peripheral functions. f1 is produced from one of the following: • Main clock divided by 1 (no division) • PLL clock divided by 1 (no division) • fOCO-S divided by 1 (no division) • fOCO-F divided by 1 (no division) f1 is used for timers A and B, PWM, real-time clock, remote control signal receiver, UART0 to UART2, UART5 to UART7, SI/O3, SI/O4, multi-master I2C-bus interface, and the A/D converter. When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to 1 (peripheral function clock f1 turned off during wait mode), the f1 clock is stopped. fOCO40M can be used for A/D converter. fOCO40M can be used when the FRA00 bit in the FRA0 register is 1 (40 MHz on-chip oscillator on). fOCO-F can be used for timers A and B, UART0 to UART2, UART5 to UART7, SI/O3, and SI/O4. fOCOF can be used when the FRA00 bit in the FRA0 register is 1 (40 MHz on-chip oscillator on). fOCO-S is used for timers A and B. It is also used for reset, voltage detector and watchdog timer. fOCO-S is also used when the CM14 bit in the CM1 register is set to 0 (125 kHz on-chip oscillator on). fC is divided by 32 to produce fC32. fC32 is used for timers A and B, and is enabled when the sub clock is on. fC is used for the watchdog timer. fC is also used as the clock source for the real-time clock, remote control signal receiver, and CEC function, when the PM25 bit in the PM2 register is 1 (peripheral clock fC provided). fC can be used when the sub clock is on. Figure 8.5 shows Peripheral Function Clocks. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 119 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator CPU clock NMI/SD digital filter fC (no influence of PM25) fOCO-S CPU clock CPU Voltage detector Watchdog timer Reset Clock generator Main clock PLL clock fOCO40M 125 kHz on-chip oscillator clock Sub-clock Divider Divider fC32 f1 f1 Timer A Timer B Real-time clock fOCO-F fOCO-S 1/32 PM25 f1 stops if the CM02 bit is 1 while in wait mode. fC32 fOCO-F Pulse width modulator Remote control signal receiver UART0 to UART2 fC (influenced by PM25) SI/O3, SI/O4 UART5 to UART7 Multi-master I 2C bus interface A/D converter CEC function PM25: Bit in the PM2 register Figure 8.5 Peripheral Function Clocks REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 120 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8.5 Clock Output Function In single-chip mode, the f1, f8, f32 or fC clock can be output from the CLKOUT pin. Use bits CM01 to CM00 in the CM0 register, and the PCLK5 bit in the PCLKR register to select the clock. f8 has the same frequency as f1 divided by 8, and f32 has the same frequency as f1 divided by 32. Set the frequency of a clock output from the CLKOUT pin to 25 MHz or below. 8.6 System Clock Protection Function The system clock protection function prohibits the CPU clock from changing clock sources when the main clock is selected as the CPU clock source. This is to prevent the CPU clock from stopping due to an unexpected program operation. When the PM21 bit in the PM2 register is set to 1 (clock change disabled), the following bits remain unchanged even if they are written to. • The CM02 bit in the CM0 register (peripheral function clock f1 in wait mode) • The CM05 bit in the CM0 register (to prevent the main clock from being stopped) • The CM07 bit in the CM0 register (clock source of the CPU clock) • The CM10 bit in the CM1 register (stop mode is not entered) • The CM11 bit in the CM1 register (clock source of the CPU clock) • The CM20 bit in the CM2 register (oscillation stop/re-oscillation detect function set) • All bits in the PLC0 register (PLL frequency synthesizer set) To use the system clock protect function, set the CM05 bit in the CM0 register to 0 (main clock oscillation) and CM07 bit to 0 (main clock as CPU clock source), and then follow the procedures below. (1)Set the PRC1 bit in the PRCR register to 1 (write to PM2 register enabled). (2)Set the PM21 bit in the PM2 register to 1 (clock change disabled). (3)Set the PRC1 bit in the PRCR register to 0 (write to PM2 register disabled). When the PM21 bit is 1, do not execute the WAIT instruction. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 121 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8.7 Oscillation Stop/Re-Oscillation Detect Function This function is to detect the stop and re-oscillation of the main clock oscillation circuit. The oscillation stop and re-oscillation detect function can be enabled and disabled with the CM20 bit in the CM2 register. A reset or oscillation stop/re-oscillation detection interrupt is generated when an oscillation stop or reoscillation is detected. Set the CM27 bit in the CM2 register to select the reset or interrupt. Table 8.6 lists Specification Overview of Oscillation Stop and Re-Oscillation Detect Function. Table 8.6 Specification Overview of Oscillation Stop and Re-Oscillation Detect Function Item Specification Oscillation stop detectable clock and frequency bandwidth Enabling condition for oscillation stop/ re-oscillation detect function Operation at oscillation stop/ re-oscillation detection f(XIN) ≥ 2 MHz Set CM20 bit to 1 (enabled) When CM27 bit is 0: Oscillation stop detection reset generated When CM27 bit is 1: Oscillation stop/re-oscillation detection interrupt generated 8.7.1 Operation When CM27 Bit is 0 (Oscillation Stop Detection Reset) When main clock stop is detected while the CM20 bit is 1 (oscillation stop/re-oscillation detection function enabled), the MCU is initialized, and then stops (oscillation stop reset). (Refer to 4. “Special Function Registers (SFRs)” and 6. “Resets”.) The status is cancelled at hardware reset or voltage monitor 0 reset. The MCU can also be initialized and stopped when re-oscillation is detected, but do not use the MCU in this manner (during main clock stop, do not set the CM20 bit to 1 and the CM27 bit to 0). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 122 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8.7.2 Operation When CM27 Bit is 1 (Oscillation Stop, Re-Oscillation Detect Interrupt) When the CM20 bit is 1 (oscillation stop/re-oscillation detect function enabled), the system is placed in the state shown in Table 8.7 if the main clock detects oscillation stop or re-oscillation. The CM21 bit is automatically set to 1 in high-speed, medium-speed, or low-speed mode. The FRA01 bit does not change. Thus, high-speed and medium-speed mode become 125 kHz on-chip oscillator mode or 40 MHz on-chip oscillator mode. Because the CM07 bit does not change, low-speed mode remains in low-speed mode, but clock sources for the peripheral functions become fOCO-S or fOCO-F. When the CM21 bit is set to 1, the CM14 bit is set to 0 (125 kHz on-chip oscillator on), but the FRA00 bit remains unchanged (40 MHz on-chip oscillator does not oscillate automatically). Thus, when the FRA01 bit is set to 1 (40 MHz on-chip oscillator selected), set the FRA00 bit to 1 (40 MHz on-chip oscillator on). Do not set the FRA00 bit to 0 while the FRA01 bit is 1, and vice versa. Since the CM21 bit remains unchanged in PLL operating mode, select 125 kHz on-chip oscillator mode or 40 MHz on-chip oscillator mode inside the interrupt routine. Table 8.7 State after Oscillation Stop and Re-Oscillation Detect When CM27 Bit is 1 Condition Main clock High-speed mode oscillation Medium-speed stop detected mode Low-speed mode 40 MHz on-chip oscillator mode 125 kHz on-chip oscillator mode After Detection • Oscillation stop, re-oscillation detection interrupt is generated • CM14 bit is 0 (125 kHz on-chip oscillator on) • CM21 bit is 1 (fOCO-S or fOCO-F is used as the clock source for the CPU and peripheral function clocks) (1), (2) • CM22 bit is 1 (main clock stop detected) • CM23 bit is 1 (main clock stopped) PLL operating mode • Oscillation stop, re-oscillation detection interrupt is generated • CM14 bit is 0 (125 kHz on-chip oscillator on) • CM21 bit remains unchanged • CM22 bit is 1 (main clock stop detected) • CM23 bit is 1 (main clock stopped) Main clock re-oscillation detected - • Oscillation stop, re-oscillation detection interrupt is generated • CM14 bit is 0 (125 kHz on-chip oscillator on) • CM21 bit remains unchanged • CM22 bit is 1 (main clock stop detected) • CM23 bit is 0 (main clock oscillating) Notes: 1. fOCO-S or fOCO-F is selected depending on the FRA01 bit status. 2. fC is used as the CPU clock in low-speed mode. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 123 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8.7.3 Using the Oscillation Stop, Re-Oscillation Detect Function • The oscillation stop/re-oscillation detect interrupt shares a vector with the watchdog timer interrupt, voltage monitor 1 interrupt, and voltage monitor 2 interrupt. If the oscillation stop/re-oscillation detection interrupt is used with a watchdog timer interrupt, voltage monitor 1 interrupt, or voltage monitor 2 interrupt, read the CM22 bit (oscillation stop/re-oscillation detection), VW1C2 bit (Vdet1 passage detection), VW2C2 bit (Vdet2 passage detection) and VW2C3 bit (watchdog timer underflow detection) in an interrupt routine to determine which interrupt source is requesting the interrupt. • After oscillation stop is detected, if the main clock re-oscillates, set the main clock back to the clock source for the CPU clock and peripheral functions by a program. Figure 8.6 shows the Procedure to Switch Clock Source from On-Chip Oscillator to Main Clock. Switch the main clock Main clock stopped Determine several times whether the CM23 bit is set to 0 (main clock oscillates) Main clock oscillating Set the CM06 bit to 1 (divide-by-8) Set the CM22 bit to 0 (main clock stop, re-oscillation not detected) Set the CM21 bit to 0 (main clock or PLL clock) End CM06 bit : Bit in the CM0 register Bits CM21 to CM23 : Bits in the CM2 register Figure 8.6 Procedure to Switch Clock Source from On-Chip Oscillator to Main Clock • The CM22 bit becomes 1 at the same time an oscillation stop/re-oscillation detection interrupt is generated. When the CM22 bit is 1, the oscillation stop/re-oscillation detection interrupt is disabled. When setting the CM22 bit to 0 by a program, the oscillation stop/re-oscillation detection interrupt is enabled. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 124 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8.8 8.8.1 Notes on Clock Generator Oscillation Circuit Using an Oscillator To connect an oscillator, follow these instructions: • The oscillation characteristics are tied closely to the user’s board design. Perform a careful evaluation of the board before connecting an oscillator. • Oscillation circuit structure depends on the oscillator. The M16C/65 Group contains a feedback resistor, but an external feedback resistor may be required. Contact the oscillator manufacturer regarding circuit constants, as they are dependent on the oscillator or stray capacitance of the mounted circuit. • Check output from the CLKOUT pin to confirm that the clock generated by the oscillation circuit is properly transmitted to the MCU. Procedures for outputting a clock from the CLKOUT pin are listed below. Set the clock output from the CLKOUT pin to 25 MHz or below. Outputting the main clock (1) Set the PRC0 bit in the PRCR register to 1 (write enabled). (2) Set the CM11 bit in the CM1 register to 0, the CM07 bit in the CM0 register to 0, and the CM21 bit in the CM2 register to 0 (main clock selected). (3) Select the clock output from the CLKOUT pin (refer to the following table). (4) Set the PRC0 bit in the PRCR register to 0 (write disabled) Table 8.8 Output from CLKOUT Pin When Selecting Main Clock Bit Setting PCLKR Register CM0 Register PCLK5 Bit Bits CM01 to CM00 1 00b 0 10b 0 11b Output from CLKOUT Pin Clock with the same frequency as the main clock Main clock divided by 8 Main clock divided by 32 Outputting the sub clock (1) Set the PRC0 bit in the PRCR register to 1 (write enabled). (2) Set the CM07 bit in the CM0 register to 1 (sub clock selected). (3) Set the PCLK5 bit in the PCLKR register to 0, and bits CM01 to CM00 in the CM0 register to 01b (fC output from CLKOUT pin). (4) Set the PRC0 bit in the PRCR register to 0 (write disabled) MCU XIN Rf feedback resistor XOUT Rd damping resistor VSS CIN Oscillator COUT Figure 8.7 Oscillation Circuit Example REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 125 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8.8.2 8.8.2.1 Noise Countermeasure Clock I/O Pin Wiring • Connect the shortest possible wiring to the clock I/O pin. • Connect (a) the capacitor's ground lead connected to the oscillator, and (b) the MCU's VSS pin, with the shortest possible wiring (maximum 20 mm). Noise XIN VSS XOUT XIN VSS XOUT Bad Figure 8.8 Clock I/O Pin Wiring Good Reason If noise enters the clock I/O pin, the clock waveform becomes unstable, which causes an error in operation or a program runaway. Also, if a potential difference attributed to the noise occurs between the VSS level of the MCU and the VSS level of the oscillator, an accurate clock is not input to the MCU. 8.8.2.2 Large Current Signal Line For large currents that go above the MCU's current range, wire the signal lines as far away from the MCU as possible (especially the oscillator). Reason In the system using the MCU, there are signal lines for controlling motors, LEDs, and thermal heads. When a large current flows through these signal lines, noise is generated due to mutual inductance. MCU Mutual inductance M XIN Large current VSS XOUT GND Figure 8.9 Large Current Signal Line Wiring REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 126 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8.8.2.3 Signal Line Whose Level Changes at a High-Speed For a signal line whose level changes at a high-speed, wire it as far away from the oscillator and the oscillator wiring pattern as possible. Do not wire it across or extend it parallel to a clock-related signal line or other signal lines which are sensitive to noise. Reason A signal whose level changes at a high-speed (such as the signal from the TAOUT pin) affects other signal lines due to the level change at rising or falling edges. Specially when the signal line crosses the clock-related signal line, the clock waveform becomes unstable, which causes an error in operation or a program runaway. TAiOUT Do not cross XIN VSS XOUT Bad Figure 8.10 Wiring of Signal Line Whose Level Changes at High-Speed 8.8.3 CPU ClockW • When the external clock is entered from the XIN pin and the main clock is used as the CPU clock, do not stop the external clock. 8.8.4 Oscillation Stop, Re-Oscillation Detect Function • In the following cases, set the CM20 bit to 0 (oscillation stop/re-oscillation detect function disabled), and then change the status of each bit. When the CM05 bit is set to 1 (main clock stopped) When the CM10 bit is set to 1 (stop mode) • To enter wait mode while using the oscillation stop/re-oscillation detection function, set the CM02 bit to 0 (peripheral function clock f1 not turned off during wait mode). • This function cannot be used if the main clock frequency is 2 MHz or below. In that case, set the CM20 bit to 0 (oscillation stop/re-oscillation detect function disabled). • While the CM27 bit is 1 (oscillation stop/re-oscillation detect interrupt), when the FRA01 bit is 1 (40 MHz on-chip oscillator selected), set the FRA00 bit to 1 (40 MHz on-chip oscillator on). (Do not set the FRA00 bit to 0 while FRA01 bit is 1, and vice versa.) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 127 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 8. Clock Generator 8.8.5 PLL Frequency Synthesizer To use the PLL frequency synthesizer, stabilize the supply voltage to meet the power supply ripple standard. Standard Typ. Max. 10 0.5 0.3 0.3 0.3 Symbol f (ripple) VP-P (ripple) VCC (|ΔV /ΔT|) Parameter Power supply ripple allowable frequency (VCC1) Power supply ripple allowable (VCC1 = 5 V) amplitude voltage (VCC1 = 3 V) Power supply ripple rising/falling (VCC1 = 5 V) gradient (VCC1 = 3 V) Min. Unit kHz V V V/ms V/ms f (ripple) Power supply ripple allowable frequency (VCC1) Vp-p (ripple) Power supply ripple allowable amplitude voltage f (ripple) VCC1 Vp-p (ripple) Figure 8.11 Voltage Fluctuation Timing REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 128 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 9. Power Control 9. 9.1 Power Control Introduction The following describes how to reduce the amount of current consumption. 9.2 Registers Refer to 8. “Clock Generator” for the clock-related registers. Table 9.1 Register Structure Address 0220h Register Name Flash Memory Control Register 0 Symbol FMR0 0222h Flash Memory Control Register 2 FMR2 After Reset 0000 0001b (Other than user boot mode) 0010 0001b (User boot mode) XXXX 0000b REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 129 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 9. Power Control 9.2.1 Flash Memory Control Register 0 (FMR0) Flash Memory Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol FMR0 Address 0220h After Reset 0000 0001b (other than user boot mode) 0010 0001b (user boot mode) Function RW RO 00 Bit Symbol FMR00 Bit Name RY/BY status flag 0 : Busy (being written or erased) 1 : Ready FMR01 CPU rewrite mode select 0 : CPU rewrite mode disabled 1 : CPU rewrite mode enabled bit 0 : Lock bit enabled Lock bit disable select bit 1 : Lock bit disabled 0 : Flash memory operation enabled 1 : Flash memory operation stopped (placed in low power mode, flash memory initialized) Set to 0 Set to 0 in other than user boot mode. Set to 1 in user boot mode. 0 : Terminated normally 1 : Terminated in error 0 : Terminated normally 1 : Terminated in error RW FMR02 RW FMSTP Flash memory stop bit RW — (b4) — (b5) FMR06 Reserved bit Reserved bit Program status flag RW RW RO FMR07 Erase Status Flag RO FMR01 (CPU Rewrite Mode Select Bit) (b1) To set the FMR01 bit to 1, write 0 and then 1 in succession. Make sure no interrupts or DMA transfers occur before writing 1 after writing 0. In EW0 mode, write to this bit by a program in any area other than the flash memory. Enter read array mode first to set this bit to 0. FMSTP (Flash Memory Stop Bit) (b3) Write to the FMSTP bit by a program in any area other than the flash memory. The FMSTP bit is enabled when the FMR01 bit is 1 (CPU rewrite mode). When the FMR01 bit is 0, although the FMSTP bit can be set to 1, the flash memory is neither placed in low power mode nor initialized. When the FMR23 bit is 1 (low current consumption read mode enabled), do not set the FMSTP bit to 1 (flash memory stopped). Also, when the FMSTP bit is 1, do not set the FMR23 bit to 1. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 130 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 9. Power Control 9.2.2 Flash Memory Control Register 2 (FMR2) Flash Memory Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol FMR2 Bit Symbol — (b1-b0) FMR22 Bit Name Reserved bits Slow read mode enable bit Address 0222h Function Set to 0 0 : Disabled 1 : Enabled After Reset XXXX 0000b RW RW 00 RW FMR23 — (b7-b4) Low current consumption 0 : Disabled read mode enable bit 1 : Enabled No register bits. If necessary, set to 0. Read as undefined value RW — FMR22 (Slow Read Mode Enable Bit) (b2) This bit enables mode which reduces the amount of current consumption when reading the flash memory. When rewriting the flash memory (CPU rewrite mode), set the FMR22 bit to 0 (slow read mode disabled). Slow read mode can be used when f(BCLK) is 5 MHz or below. When f(BCLK) is above 5 MHz, set the FMR22 bit to 0 (slow read mode disabled). To set the FMR22 bit to 1, write 0 and then 1 in succession. Make sure no interrupts or DMA transfers occur before writing 1 and after writing 0. Set the FMR23 bit to 1 (low current consumption read mode enabled) after the FMR22 bit is set to 1 (slow read mode enabled). Also, set the FMR22 bit to 0 (slow read mode disabled) after the FMR23 bit is set to 0 (slow read mode disabled). Do not change the FMR22 bit and FMR23 bit at the same time. FMR23 (Low Current Consumption Read Mode Enable Bit) (b3) When this bit is enabled, the slow read mode reduces the amount of current consumption when reading the flash memory. When rewriting the flash memory (CPU rewrite mode), set the FMR23 bit to 0 (slow read mode disabled). Low current consumption read mode can be used when the CM07 bit in the CM0 register is 1 (sub clock used as CPU clock). When the CM07 bit is 0, set the FMR23 bit to 0 (slow read mode disabled). To set the FMR23 bit to 1, write 0 and then 1 in succession. Make sure no interrupts or DMA transfers occur before writing 1 and after writing 0. Set the FMR23 bit to 1 (low current consumption read mode enabled) after the FMR22 bit is set to 1 (slow read mode enabled). Also, set the FMR22 bit to 0 (slow read mode disabled) after the FMR23 bit is set to 0 (slow read mode disabled). Do not change bits FMR22 and FMR23 at the same time. When the FMR23 bit is 1, do not set the FMSTP bit in the FMR0 register to 1 (flash memory stopped). Also, when the FMSTP bit is 1, do not set the FMR23 bit to 1. When the FMR23 bit in the FMR2 register is 1 (low current consumption read mode enabled), do not enter wait mode or stop mode. To enter wait mode or stop mode, set the FMR23 bit to 0 (low current consumption read mode disabled) before entering. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 131 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 9. Power Control 9.3 Clock The amount of current consumption correlates with the number of operating clocks and frequency. If there are fewer operating clocks and a lower frequency, current consumption will be low. Normal operating mode, wait mode, and stop mode are provided to control power consumption. All mode states, except wait mode and stop mode, are called normal operating mode in this document. 9.3.1 Normal Operating Mode In normal operating mode, because both the CPU clock and the peripheral function clocks are supplied, the CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock frequency. The higher the CPU clock frequency, the greater the processing capability. The lower the CPU clock frequency, the smaller the power consumption in the chip. If unnecessary oscillator circuits are turned off, power consumption is further reduced. 9.3.1.1 High-Speed Mode and Medium-Speed Mode In high-speed mode, the main clock divided by 1 (no division) is used as the CPU clock. In medium-speed mode, the main clock divided by 2, 4, 8 or 16 is used as the CPU clock. f1 with the same frequency of the main clock divided by 1 is used as the peripheral function clocks in both high-speed and medium-speed modes. When fC is supplied, fC and fC32 can be used as the peripheral function clocks. When fOCO-S is supplied, it can be used as the peripheral function clocks. When fOCO40M and fOCO-F are supplied, they can be used as the peripheral function clocks. 9.3.1.2 PLL Operating Mode The PLL clock divided by 1 (no division), 2, 4, 8 or 16 is used as the CPU clock. f1 with the same frequency of the PLL clock divided by 1 (no division) is used as the peripheral function clocks. When fC is supplied, fC and fC32 can be used as the peripheral function clocks. When fOCO-S is supplied, it can be used as the peripheral function clocks. When fOCO40M and fOCO-F are supplied, they can be used as the peripheral function clocks. PLL operating mode can be entered and exited from high-speed mode or medium-speed mode. To enter other modes including wait mode and stop mode, enter high-speed mode or medium-speed mode first, and then enter the intended mode (refer to Figure 9.1 “Clock Mode Transition”). 9.3.1.3 40 MHz On-Chip Oscillator Mode The fOCO-F clock divided by 1 (no division), 2, 4, 8 or 16 is used as the CPU clock. f1 with the same frequency of the fOCO-F clock divided by 1 is used as the peripheral function clocks. When fC is supplied, fC and fC32 can be used as the peripheral function clocks. When fOCO-S is supplied, it can be used as the peripheral function clocks. fOCO40M and fOCO-F can be used as the peripheral function clocks. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 132 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 9. Power Control 9.3.1.4 125 kHz On-Chip Oscillator Mode The fOCO-S clock divided by 1 (no division), 2, 4, 8 or 16 is used as the CPU clock. f1 with the same frequency of the fOCO-S clock divided by 1 is used as the peripheral function clocks. When fC is supplied, fC and fC32 can be used as the peripheral function clocks. fOCO-S can be used as the peripheral function clocks. When fOCO40M and fOCO-F are supplied, they can be used as the peripheral function clocks. 9.3.1.5 125 kHz On-Chip Oscillator Low Power Mode The main clock and fOCO-F are turned off after the MCU enters 125 kHz on-chip oscillator mode. The fOCO-S clock divided by 1 (no division), 2, 4, 8 or 16 is used as the CPU clock. f1 with the same frequency of the fOCO-S clock divided by 1 is used as the peripheral function clocks. When fC is supplied, fC and fC32 can be used as the peripheral function clocks. fOCO-S can be used as the peripheral function clocks. 9.3.1.6 Low-Speed Mode fC is used as the CPU clock. When the CM21 bit is 0 and the CM11 bit is 0 (main clock), f1 with the same frequency of the main clock divided by 1 is used as the peripheral function clocks. When the CM21 bit is 0 and the CM11 bit is 1 (PLL clock), f1 with the same frequency of the PLL clock divided by 1 is used as the peripheral function clocks. When the CM21 bit is 1 (on-chip oscillator clock) and the FRA01 bit is 0 (125 kHz onchip oscillator clock), f1 with the same frequency of the fOCO-S clock divided by 1 is used as the peripheral function clocks. When the CM21 bit is 1 (on-chip oscillator clock) and the FRA01 bit is 1 (40 MHz on-chip oscillator clock), f1 with the same frequency of the fOCO-F clock divided by 1 is used as the peripheral function clocks. fC and fC32 can be used as the peripheral function clocks. When fOCO-S is supplied, it can be used as the peripheral function clocks. When fOCO40M and fOCO-F are supplied, they can be used as the peripheral function clocks. 9.3.1.7 Low Power Mode The main clock and fOCO-F are turned off after the MCU enters low speed mode. fC is used as the CPU clock. When the CM21 bit is 1 (on-chip oscillator clock) and the FRA01 bit is 0 (125 kHz on-chip oscillator clock), f1 with the same frequency of the fOCO-S clock divided by 1 is used as the peripheral function clocks. fC and fC32 can be used as the peripheral function clocks. When fOCO-S is supplied, it can be used as the peripheral function clocks. When this mode is selected, the CM06 bit in the CM0 register simultaneously becomes 1 (divide- by8 mode). In low power mode, do not change the CM06 bit. Consequently, select the divide-by-8 mode when any clock (except the sub clock) is used for the next operation. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 133 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 9. Power Control Table 9.2 Clocks in Normal Operating Mode Peripheral Clocks Mode High-speed mode CPU Clock Main clock divided by 1 (1) f1 Main clock divided by 1 fOCO-F fOCO40M Enabled Enabled Enabled fC, fC32 fOCO-S (3) (2) (4) Medium-speed Main clock mode divided by n (1) PLL operating mode 40 MHz onchip oscillator mode 125 kHz onchip oscillator mode 125 kHz onchip oscillator low power mode Low-speed mode PLL clock divided by n (1) PLL clock divided by 1 fOCO-F divided by n (1) fOCO-F divided by 1 Enabled Enabled Enabled (2) (3) fOCO-S divided by n (1) fOCO-S divided by 1 Enabled Enabled Enabled (2) (4) fOCO-S divided by n (1) fOCO-S divided by 1 Enabled Enabled Disabled (2) fC Any of the following: Enabled Enabled Enabled (3) (4) Main clock divided by 1 (5) (when the CM21 is 0 and the CM11 is 0) PLL clock divided by 1 (when the CM21 is 0 and the CM11 is 1) (6) fOCO-F divided by 1 (when the CM21 is 1 and the FRA01 is 1) (4) fOCO-S divided by 1 (when the CM21 is 0 and the FRA01 is 0) (3) Low power mode fC fOCO-S divided by 1 (when the CM21 is 1 and the FRA01 is 0) (3) Enabled Enabled Disabled (3) CM11 : Bit in the CM1 register CM21 : Bit in the CM2 register FRA01 : Bit in the FRA0 register Notes: 1. Select by using the CM06 bit in the CM0 register and bits CM17 to CM16 in the CM1 register. 2. When the fC is supplied. 3. When the fOCO-S is supplied. 4. When the fOCO40M and fOCO-F are supplied. 5. When the main clock is supplied. 6. When the PLL clock is supplied. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 134 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 9. Power Control Table 9.3 Clock Related Bit Setting and Modes Mode High-speed mode, medium-speed mode PLL operating mode 40 MHz on-chip oscillator mode 125 kHz on-chip oscillator mode CM2 Register CM1 Register CM0 Register FRA0 Register CM21 CM14 CM11 CM07 CM05 CM04 FRA01 FRA00 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 (1) 1 0 (1) 1 1 1 1 0 0 1 1 (1) 0 1 (1) 0 125 kHz on-chip oscillator low 1 0 0 power mode Low-speed mode 0 Low power mode 0 Note: 1. Both or either the main clock and fOCO-F are oscillated Table 9.4 Selecting Clock Division Related Bits (1) Division Divide-by-1 (no division) (2) Divide-by-2 Divide-by-4 Divide-by-8 Divide-by-16 CM1 Register Bits CM17 to CM16 00b 01b 10b 11b CM0 Register CM16 bit 0 0 0 1 0 Notes: 1. While in high-speed mode, medium-speed mode, PLL operating mode, 125 kHz on-chip oscillator mode, or 125 kHz on-chip oscillator low power mode. 2. Select divide-by-1 (no division) in high-speed mode. Table 9.5 Example Settings for 40 MHz On-Chip Oscillator Mode Division Related Bits Division Divide-by-2 Divide-by-4 Divide-by-8 Divide-by-16 Divide-by-32 CPU Clock Frequency Approx. 20 MHz Approx. 10 MHz Approx. 5 MHz Approx. 2.5 MHz Approx. 1.25 MHz CM1 Register Bits CM17 to CM16 00b (divide-by-1 (no division)) 0 01b (divide-by-2) 10b (divide-by-4) 11b (divide-by-16) 0 0 CM0 Register CM06 bit 1 (divide-by-8) 0 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 135 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 9. Power Control 9.3.2 Mode Transitions Figure 9.1 shows Clock Mode Transition. Arrows indicate that mode transitions are enabled between modes. Reset Normal Operating Mode Transitions to wait mode and stop mode enabled i 40 MHz on-chip oscillator mode d e g 125 kHz on-chip oscillator mode h 125 kHz on-chip oscillator low power mode d a e f a c PLL operating mode b High-speed, medium-speed mode f Low-speed mode a g h Low power mode Interrupt or reset Wait mode WAIT instruction Interrupt or reset Stop mode CM10 = 1 CPU operation stop All oscillations stop CM10 : Bit in the CM1 register Figure 9.1 Clock Mode Transition To start or stop clock oscillations, or to change modes in normal operating mode, follow the instructions below. • Enter a mode after the clock for the mode entered stabilizes completely. • To stop a clock, stop the clock for the mode exited after mode transition is completed. Do not stop the clock at the same time as mode transition. • Execute mode transition according to the following procedures. To access registers and bits, see 9.2 “Registers”. Letters a to h correspond to those in Figure 9.1 “Clock Mode Transition”. • For oscillation start and stop, see 8.3.1 “Main Clock” to 8.3.6 “Sub Clock (fC)”. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 136 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 9. Power Control a.Entering high-speed mode or medium-speed mode from 40 MHz on-chip oscillator mode, 125 kHz on-chip oscillator mode, or low-speed mode (1)Oscillate the main clock and wait until the oscillation stabilizes. See 8.3.1 “Main Clock”. (2)Set the CM06 bit to 1 (divide-by-8 mode). (3)Set the CM11 bit to 0, the CM21 bit to 0, and the CM07 bit to 0 (main clock selected as CPU clock source). b.Entering PLL operating mode from high-speed mode or medium-speed mode (1)Set a multiplying factor and reference frequency counter by using bits PLC05 to PLC04 and bits PLC02 to PLC00 in the PLC0 register. (2)Specify wait for SFR accessing by the PM20 bit. (3)Set the PLC07 bit to 1 (PLL on). (4)Wait for tsu(PLL) until the PLL clock stabilizes. (5)Set the CM11 bit to 1, the CM21 bit to 0, and the CM07 bit to 0 (PLL clock selected as CPU clock source). c.Entering high-speed mode or medium-speed mode from PLL operating mode (1)Select a divide ratio by setting the CM06 bit and bits CM17 to CM16. (2)Set the CM11 bit to 0, the CM21 bit to 0, and the CM07 bit to 0 (main clock selected as CPU clock source). (3)Set the PLC07 bit to 0 (PLL off). d.Entering 40 MHz on-chip oscillator mode from high-speed mode, medium-speed mode, or 125 kHz on-chip oscillator mode (1)Oscillate the 40 MHz on-chip oscillator and wait until the oscillation stabilizes. See 8.3.4 “fOCO-F”. (2)Set the CM06 bit to 1 (divide-by-8 mode). (3)Set the FRA01 bit to 1 (40 MHz on-chip oscillator). (4)Set the CM21 bit to 1 (on-chip oscillator clock selected as CPU clock source). (5)Set the CM07 bit to 0 (main clock, PLL clock, or on-chip oscillator clock selected as CPU clock source). e.Entering 125 kHz on-chip oscillator mode from high-speed mode, medium-speed mode, or low-speed mode (1)Oscillate the 125 kHz on-chip oscillator and wait until the oscillation stabilizes. See 8.3.5 “125 kHz On-Chip Oscillator Clock (fOCO-S)”. (2)Set the FRA01 bit to 0 (125 kHz on-chip oscillator). (3)Set the CM21 bit to 1 (on-chip oscillator clock selected as CPU clock source). (4)Set the CM07 bit to 0 (main clock, PLL clock, or on-chip oscillator clock selected as CPU clock source). f.Entering low-speed mode from high-speed mode, medium-speed mode, or 125 kHz on-chip oscillator mode (1)Oscillate the sub clock and wait until the oscillation stabilizes. See 8.3.6 “Sub Clock (fC)”. (2)Set the CM07 bit to 1 (sub clock selected as CPU clock source). g.Entering 125 kHz on-chip oscillator low power mode from 125kHz on-chip oscillator mode Entering low power mode from low-speed mode Follow both or either of the procedures below (in no particular order). (1)Stop oscillating the main clock. See 8.3.1 “Main Clock” (2)Stop oscillating the 40 MHz on-chip oscillator. See 8.3.4 “fOCO-F”. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 137 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 9. Power Control h.Entering 125 kHz on-chip oscillator mode from 125 kHz on-chip oscillator low power mode Entering low-speed mode from low power mode Follow both or either of the procedures below (in no particular order). (1)Oscillate the main clock and wait until the oscillation stabilizes. See 8.3.1 “Main Clock”. (2)Oscillate the 40 MHz on-chip oscillator and wait until the oscillation stabilizes. See 8.3.4 “fOCO-F”. i.Entering 125 kHz on-chip oscillator mode from 40 MHz on-chip oscillator mode (1)Oscillate the 125 kHz on-chip oscillator and wait until the oscillation stabilizes. See 8.3.5 “125 kHz On-Chip Oscillator Clock (fOCO-S)”. (2)Set the CM06 bit to 1 (divide-by-8 mode). (3)Set the FRA01 bit to 0 (125 kHz on-chip oscillator). (4)Set the CM21 bit to 1 (on-chip oscillator clock selected as CPU clock source). (5)Set the CM07 bit to 0 (main clock, PLL clock, or on-chip oscillator clock selected as CPU clock source). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 138 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 9. Power Control 9.3.3 Wait Mode In wait mode, the CPU clock, CPU, watchdog timer, and NMI/SD digital filter are turned off as they are operated by the CPU clock. However, if the CSPRO bit in the CSPR register is 1 (count source protection enabled), the watchdog timer remains active. Because the main clock, fOCO-F, fOCO-S, and fC do not stop, the peripheral functions using these clocks keep operating. 9.3.3.1 Peripheral Function Clock Stop Function When the CM02 bit is 1 (peripheral function clock f1 turned off during wait mode), the f1 clock is turned off while in wait mode, and power consumption is reduced. However, all the peripheral clocks except f1 (i.e. fOCO-F, fOCO-S, fC, and fC32) do not stop. 9.3.3.2 Entering Wait Mode The MCU enters wait mode by executing a WAIT instruction. When the CM11 bit is 1 (PLL clock selected as CPU clock source), set the CM11 bit to 0 (main clock selected as CPU clock source) before entering wait mode. Chip power consumption can be reduced by setting the PLC07 bit to 0 (PLL off). 9.3.3.3 Pin Status in Wait Mode Table 9.6 lists Pin Status in Wait Mode. Table 9.6 Pin Status in Wait Mode Pin A0 to A19, D0 to D15, CS0 to CS3, BHE RD, WR, WRL, WRH HLDA, BCLK Memory Expansion Mode Microprocessor Mode Retains the status just prior to entering wait mode High High Low Retains the status just prior to entering wait mode Single-Chip Mode Cannot be used as a bus control pin ALE I/O ports CLKOUT fC selected f1, f8, f32 selected Retains the status just prior to entering wait mode Does not stop Does not stop when the CM02 bit is 0. When the CM02 bit is 1, the status immediately prior to entering wait mode is maintained Cannot be used as a CLKOUT pin REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 139 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 9. Power Control 9.3.3.4 Exiting Wait Mode The MCU exits wait mode by a reset or interrupt. Table 9.7 lists Resets and Interrupts to Exit Wait Mode and Conditions for Use. The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is 0 (peripheral function clock f1 not turned off in wait mode), peripheral function interrupts can be used to exit wait mode. When the CM02 bit is 1 (peripheral function clock f1 turned off in wait mode), the peripheral functions using the peripheral function clock f1 stop operating, so that the peripheral functions activated by external signals and the peripheral function clocks except f1 (fOCO40M, fOCO-F, fOCOS, fC, fC32) can be used to exit wait mode. The fOCO-S is also used for the digital filter in the voltage detection circuit, so wait mode is exited when the digital filter is disabled or when the fOCO-S is supplied. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 140 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 9. Power Control Table 9.7 Resets and Interrupts to Exit Wait Mode and Conditions for Use Interrupt, Reset Interrupt Peripheral INT function Key input interrupt timer A, timer B Usable Usable Conditions for Use CM02 = 0 Usable Usable Usable when fOCO-F, fOCO-S or fC32 is supplied and is used as count source. Usable when counting external signals in event counter mode Usable when fC is supplied and is used as count source. Usable when fOCO-F, fOCO-S, or fC32 is supplied and is used as count source for timer B1 or B2, and timer B1 or B2 underflow is used as count source for remote control signal receiver. Usable in external clock Usable when fOCO-F is supplied and is used as internal clock CM02 = 1 Usable in all modes Remote Usable control signal receiver Serial interface Multi-master I2C-bus interface Usable in internal clock or external clock Both I2C-bus interface and SCL/SDA is usable SCL/SDA are usable Usable when fC is supplied and is used as count source. CEC function Usable A/D converter Usable in one-shot mode or Usable when fOCO40M is supplied and is single sweep mode used as fAD in one-shot mode or single sweep mode Real-time clock Voltage detection 1, Voltage detection 2 NMI Usable when fC is supplied and is used as count source Usable when the digital filter is disabled or fOCO-S is supplied Usable when the digital filter is disabled (bits NMIDF2 to NMIDF0 in the NMIDF register are 000b) Usable Reset Hardware reset Voltage detection 0 reset, Usable when the digital filter is disabled or fOCO-S is supplied Voltage detection 1 reset, Voltage detection 2 reset Watchdog timer Usable when count source protection mode is enabled (CSPRO = 1) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 141 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 9. Power Control When the MCU exits wait mode by hardware reset, voltage monitor 0 reset, voltage monitor 1 reset, voltage monitor 2 reset, watchdog timer reset, NMI interrupt, voltage monitor 1 interrupt, or voltage monitor 2 interrupt, set bits ILVL2 to ILVL0 in peripheral function interrupt to 000b (interrupt disabled) before executing the WAIT instruction. When the MCU exits wait mode by peripheral function interrupts, make the following settings before executing a WAIT instruction: (1) Set the interrupt priority level of bits ILVL2 to ILVL0 in the interrupt control register for peripheral function interrupts which are used to exit wait mode. Set bits ILVL2 to ILVL0 in all other interrupt control registers, for peripheral function interrupts not used to exit wait mode, to 000b (interrupt disabled). (2) Set the I flag to 1. (3) Start operating the peripheral functions used to exit wait mode. When exiting wait mode by means of an interrupt, an interrupt routine is performed after an interrupt request is generated, and then the CPU clock is supplied again. When the MCU exits wait mode by an interrupt, the CPU clock is the same CPU clock used while executing the WAIT instruction. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 142 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 9. Power Control 9.3.4 Stop Mode In stop mode, all oscillator circuits, the CPU clock, and peripheral function clocks are turned off. Therefore, the CPU and the peripheral functions using these clocks stop operating. The least amount of power is consumed in this mode. If the voltage applied to pins VCC1 and VCC2 is VRAM or greater, the contents of internal RAM are retained. When applying 2.7 V or less to pins VCC1 and VCC2, make sure VCC1 ≥ VCC2 ≥ VRAM. However, the peripheral functions activated by external signals keep operating. 9.3.4.1 Entering Stop Mode The MCU enters stop mode by setting the CM10 bit in the CM1 register to 1 (all clocks turned off). At the same time, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode), and the CM15 bit in the CM1 register is set to 1 (main clock oscillator circuit drive capability high). Before entering stop mode, set the CM20 bit to 0 (oscillation stop/re-oscillation detection function disabled). Also, when the CM11 bit is 1 (PLL clock used as the CPU clock source), set the CM11 bit to 0 (main clock used as the CPU clock source), and then the PLC07 bit to 0 (PLL turned off) before entering stop mode. 9.3.4.2 Pin Status in Stop Mode Table 9.8 lists Pin Status in Stop Mode. Table 9.8 Pin Status in Stop Mode Pin A0 to A19, D0 to D15, CS0 to CS3, BHE RD, WR, WRL, WRH HLDA, BCLK Memory Expansion Mode Microprocessor Mode Retains status just prior to stop mode High High Undefined Retains status just prior to stop mode Cannot be used as CLKOUT pin Single-Chip Mode Cannot be used as bus control pin ALE I/O ports CLKOUT fC selected f1, f8, f32 selected XOUT XCIN, XCOUT Retains status just prior to stop mode High Retains status just prior to stop mode High High-impedance REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 143 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 9. Power Control 9.3.4.3 Exiting Stop Mode Use a reset or an interrupt to exit stop mode. Table 9.9 lists Resets and Interrupts to Exit Stop Mode and Conditions for Use. Table 9.9 Resets and Interrupts to Exit Stop Mode and Conditions for Use Interrupt, Reset Interrupt Peripheral function interrupt INT Conditions for Use Usable Usable Usable when counting external signals in event counter mode Usable when an external clock is selected SCL/SDA is usable Key input timer A, timer B Serial interface Multi-master I2C-bus interface Voltage detection 1 interrupt, Usable when the digital filter is disabled (VW1C1 bit in the VW1C register is 1) Voltage detection 2 interrupt Usable when the digital filter is disabled (VW2C1 bit in the VW2C register is 1) NMI Usable when the digital filter is disabled (bits NMIDF2 to NMIDF0 in the NMIDF register are 000b) Usable Usable when the digital filter is disabled (VW0C1 bit in the VW0C register is 1) Reset Hardware reset Voltage detection 0 reset To exit stop mode by using hardware reset, voltage monitor 0 reset, NMI interrupt, voltage monitor 1 interrupt, or voltage monitor 2 interrupt, set bits ILVL2 to ILVL0 in the interrupt control registers for the peripheral function interrupt to 000b (interrupt disabled) before setting the CM10 bit to 1. To use a peripheral function interrupt to exit stop mode, set the CM10 bit to 1 after the following settings are completed. (1) Set the interrupt priority level of bits ILVL2 to ILVL0 in the interrupt control register for peripheral function interrupts which are used to exit stop mode. Set bits ILVL2 to ILVL0 in all other interrupt control registers, for peripheral function interrupts not used to exit stop mode, to 000b (interrupt disabled). (2) Set the I flag to 1. (3) Start operating the peripheral functions used to exit stop mode. When exiting stop mode by means of a peripheral function interrupt, an interrupt routine is performed after an interrupt request is generated and then the CPU clock is supplied again. When stop mode is exited by means of an interrupt, the CPU clock source varies depending on the CPU clock source setting before the MCU had entered stop mode. Table 9.10 lists CPU Clock After Exiting Stop Mode. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 144 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 9. Power Control Table 9.10 CPU Clock After Exiting Stop Mode CPU Clock Before Entering Stop Mode Main clock divided by 1 (no division), 2, 4, 8 or 16 fOCO-S divided by 1 (no division), 2, 4, 8 or 16 fOCO-F divided by 1 (no division), 2, 4, 8 or 16 fC CPU Clock After Exiting Stop Mode Main clock divided by 8 fOCO-S divided by 8 fOCO-F divided by 8 fC REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 145 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 9. Power Control 9.4 9.4.1 Power Control in Flash Memory Stopping Flash Memory When the flash memory is stopped, consumption current is reduced. Execute a program in any area other than the flash memory. Figure 9.2 shows Stop and Restart of the Flash Memory. Follow the flowchart of Figure 9.2. Transfer the program within the dashed line below to an area other than the flash memory Jump to the program within the dashed line below transferred to an area other than the flash memory. (Execute the following steps in an area other than the flash memory.) Stop Procedure Set the FMR01 bit to 0 first, and then set it to 1 (CPU rewrite mode enabled). Set the FMSTP bit to 1 (The flash memory stops operating, low-power state) (1) Switch clock sources of the CPU clock. Main clock stop, 40 MHz on-chip oscillator stop, etc. (2) Processing (4) Start oscillating main clock or 40 MHz on-chip oscillator Wait until oscillation stabilizes Switch clock source of the CPU clock (2) Set the FMSTP bit to 0 (flash memory operation). Set the FMR01 bit to 0 (CPU rewrite mode disabled). Restart Procedure Wait until the flash memory stabilizes (tps). (3) Jump to the desired address in the flash memory. Notes: 1. Set the FMSTP bit to 1 after the FMR01 bit is set to 1 (CPU rewrite mode enabled). 2. Wait until the clock stabilizes before switching the clock source of the CPU clock. 3. Add tps wait time by a program. Do not access the flash memory during this wait time. 4. To enter stop mode or wait mode, set the FMR01 bit to 0 (CPU rewrite mode disabled). Figure 9.2 Stop and Restart of the Flash Memory REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 146 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 9. Power Control 9.4.2 Reading Flash Memory Consumption current while reading the flash memory can be reduced by using bits FMR22 and FMR23. 9.4.2.1 Slow Read Mode Slow read mode can be used when f(BCLK) is 5 MHz or below. Figure 9.3 shows Setting and Canceling of Slow Read Mode. Slow read mode Set the CPU clock less than or equal to 5 MHz. Setting Procedure Set the FMR22 bit to 0, and then to 1 (enabled). Processing in slow read mode Set the FMR22 bit to 0. Canceling Procedure Restore the CPU clock. Completed Figure 9.3 Setting and Canceling of Slow Read Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 147 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 9. Power Control 9.4.2.2 Low Current Consumption Read Mode Low current consumption read mode can be used when the CM07 bit in the CM0 register is 1 (sub clock used as CPU clock). Figure 9.4 shows Setting and Canceling of Low Current Consumption Read Mode. Low current consumption read mode Set the CM07 bit to 1 (sub-clock used as a CPU clock) (1) Set the CM05 bit to 1 (main clock oscillation stop) and the FRA00 bit to 0 (40 MHz on-chip oscillator stopped). Setting Procedure Set the FMR22 bit to 0, and then to 1 (enabled). Set the FMR23 bit to 0, and then to 1 (enabled). Processing in low current consumption read mode Set the FMR23 bit to 0 (1) Set the FMR22 bit to 0 (1) Canceling Procedure Restore the CPU clock Completed Note: 1. Do not rewrite bits FMR22 and FMR23 simultaneously. Figure 9.4 Setting and Canceling of Low Current Consumption Read Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 148 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 9. Power Control 9.5 Reducing Power Consumption To reduce power consumption, refer to the following descriptions when designing a system or writing a program. 9.5.1 Ports The MCU retains the state of each I/O port even when it enters wait mode or stop mode. A current flows in the active output ports. A shoot-through current flows to the input ports in the high-impedance state. When entering wait mode or stop mode, set unused ports to input and stabilize the potential. 9.5.2 A/D Converter When not executing A/D conversion, set the ADSTBY bit in the ADCON1 register to 0 (A/D operation stop). When executing A/D conversion, start the A/D conversion after setting the ADSTBY bit to 1 (A/D operation enabled) and waiting 1 φAD cycle or more. 9.5.3 D/A Converter When not executing D/A conversion, set the DAiE bit (i = 0, 1) in the DACON register to 0 (output inhibited) and the DAi register to 00h. 9.5.4 Stopping Peripheral Functions Use the CM02 bit in the CM0 register to stop the unnecessary peripheral functions while in wait mode. 9.5.5 Switching the Oscillation-Driving Capacity Set the driving capacity to low when oscillation is stable. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 149 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 9. Power Control 9.6 9.6.1 Notes on Power Control CPU Clock • When switching clock sources of the CPU clock, wait until the clock oscillation switched to is stabilized. 9.6.2 Wait Mode • After the WAIT instruction, insert at least four NOP instructions. When entering wait mode, the instruction queue reads ahead the instructions following WAIT. Thus, depending on timing, some of the instructions may be executed before the MCU enters wait mode. Program example when entering wait mode is shown below. Program Example: FSET WAIT NOP NOP NOP NOP I ; ; Enter wait mode ; More than four NOP instructions • Do not enter wait mode when the FMR23 bit in the FMR2 register is 1 (low current consumption read mode enabled). Set the FMR23 bit to 0 (low current consumption read mode disabled) and the FMR01 bit to 0 (CPU rewrite mode disabled), and disable DMA transfer before entering wait mode. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 150 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 9. Power Control 9.6.3 Stop Mode • When exiting stop mode by hardware reset, drive the RESET pin low until main clock oscillation is stabilized. • Set the MR0 bit in the TAiMR register (i = 0 to 4) to 0 (pulse not output) when using timer A to exit stop mode. • When entering stop mode, insert a JMP.B instruction immediately after executing an instruction that sets the CM10 bit in the CM1 register to 1, and then insert at least four NOP instructions. When entering stop mode, the instruction queue reads ahead the instructions following the instruction which sets the CM10 bit to 1 (all clock stop). Thus, some of the instructions may be executed before the MCU enters stop mode or before the interrupt routine for returning from stop mode. Program example when entering stop mode Program Example: FSET BSET JMP.B L2: NOP NOP NOP NOP I 0, CM1 L2 ; Enter stop mode ; Insert a JMP.B instruction ; At least four NOP instructions • The CLKOUT pin outputs a high-level signal in stop mode. Thus, if stop mode is entered right after output on the CLKOUT pin changes state from high to low, the high-level durations of the output signal to the CLKOUT pin becomes shorter. Stop mode CLKOUT pin output • When the FMR23 bit in the FMR2 register is 1 (low current consumption read mode enabled), do not enter stop mode. To enter stop mode, execute an instruction to set the CM10 bit in the CM1 register to 1 (stop mode) after setting the FMR23 bit to 0 (low current consumption read mode disabled), setting the FMR01 bit to 0 (CPU rewrite mode disabled), and disabling DMA transfer. 9.6.4 Low Current Consumption Read Mode • Enter low current consumption read mode through slow read mode (refer to Figure 9.4 “Setting and Canceling of Low Current Consumption Read Mode”). • When the FMR23 bit in the FMR2 register is 1 (low current consumption read mode enabled), do not set the FMSTP bit to 1 (flash memory stopped). Also, when the FMSTP bit is 1, do not set the FMR23 bit to 1. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 151 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 10. Processor Mode 10. Processor Mode Note Do not use memory expansion mode and microprocessor mode in the 80-pin package. 10.1 Introduction Three processor modes are available to choose from: single-chip mode, memory expansion mode, and microprocessor mode. Table 10.1 shows the Features of Processor Modes. Table 10.1 Features of Processor Modes Processor Mode Single-chip mode Access Space SFR, internal RAM, internal ROM Pins Assigned as I/O Ports All pins are I/O ports or peripheral function I/O pins Some pins serve as bus control pins (1) Memory expansion mode SFR, internal RAM, internal ROM, external area (1) Microprocessor mode Note: 1. SFR, internal RAM, external area (1) Some pins serve as bus control pins (1) Refer to 11. “Bus” for details. I/O Pins Table 10.2 Pin Name CNVSS Input I/O Type Function Selects a processor mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 152 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 10. Processor Mode 10.2 Registers Register Structure Table 10.3 Address 0004h 0005h 0010h Register Name Processor Mode Register 0 Processor Mode Register 1 Program 2 Area Control Register PM0 PM1 Symbol After Reset 0000 0000b (CNVSS pin is low) 0000 0011b (CNVSS pin is high) 0000 1000b XXXX XX00b PRG2C 10.2.1 Processor Mode Register 0 (PM0) Processor Mode Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PM0 Address 0004h After Reset 0000 0000b (CNVSS pin is held low) 0000 0011b (CNVSS pin is held high) Function b1 b0 Bit Symbol PM00 Bit Name RW RW Processor mode bit PM01 0 0 1 1 0 : Single-chip mode 1 : Memory expansion mode 0 : Do not set 1 : Microprocessor mode RW PM02 R/W mode select bit 0 : RD, BHE, WR 1 : RD, WRH, WRL Setting this bit to 1 resets the MCU. Read as 0. b5 b4 RW PM03 Software reset bit RW PM04 Multiplexed bus space select bit PM05 0 0 1 1 0 : Multiplexed bus is unused (separate bus in the entire CS space) 1 : Allocated to CS2 space 0 : Allocated to CS1 space 1 : Allocated to the entire CS space RW RW PM06 Port P4_0 to P4_3 function select bit 0 : Address output 1 : Port function (address is not output) 0 : BCLK is output 1 : BCLK is not output (pin is left in high-impedance) RW PM07 BCLK output disable bit RW Rewrite this register after setting the PRC1 bit in the PRCR register to 1 (write enabled). Bits PM01 to PM00 do not change at software reset, watchdog timer reset, oscillation stop detection reset, voltage monitor 1 reset, and voltage monitor 2 reset. PM01 to PM00 (Processor Mode Bit) (b1 to b0) Do not rewrite bits PM01 to PM00 and PM07 to PM02 at the same time. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 153 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 10. Processor Mode 10.2.2 Processor Mode Register 1 (PM1) Processor Mode Register 1 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol PM1 Bit Symbol PM10 Address 0005h Bit Name CS2 area switch bit (data flash enable bit) Port P3_7 to P3_4 function select bit After Reset 0000 1000b Function 0 : CS2 (0E000h to 0FFFFh ) 1 : Data flash (0E000h to 0FFFFh) 0 : Address output 1 : Port function RW RW PM11 RW PM12 Watchdog timer function select 0 : Watchdog timer interrupt bit 1 : Watchdog timer reset Internal area expansion bit 0 Refer to the bit explanation below “PM13 (Internal Area Expansion Bit 0) (b3)” b5 b4 RW PM13 RW PM14 Memory area expansion bit PM15 — (b6) PM17 0 0 1 1 0 : 1-Mbyte mode (no expansion) 1 : Do not set 0 : Do not set 1 : 4-Mbyte mode RW RW Reserved bit Set to 0 0 : No wait state 1 : Wait state (1 wait) RW Wait bit RW Rewrite this register after setting the PRC1 bit in the PRCR register to 1 (write enabled). The PM12 bit is set to 1 by writing 1 by a program (writing 0 has no effect). PM10 (CS2 Area Switch Bit (Data Flash Enable Bit)) (b0) This bit is used to select the function of addresses 0E000h to 0FFFFh. Table 10.4 lists Data Flash (Addresses 0E000h to 0FFFFh). Table 10.4 Data Flash (Addresses 0E000h to 0FFFFh) PM10 bit in PM1 Register Processor Mode Single-chip mode Memory expansion mode Microprocessor mode 0 Reserved area External area External area Data flash Data flash 1 Reserved area Data flash includes block A (addresses 0E000h to 0EFFFh) and block B (addresses 0F000h to 0FFFFh). When data flash is selected by the setting of the PM10 bit, both block A and block B can be used. The PM10 bit is automatically set to 1 while the FMR01 bit in the FMR0 register is set to 1 (CPU rewrite mode). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 154 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 10. Processor Mode PM13 (Internal Area Expansion Bit 0) (b3) This bit is used to select the range of the RAM, program ROM 1, and external area. When the PM13 bit is 0, the size of the RAM and program ROM 1 is limited, but a wide range can be selected for the external area. When the PM13 bit is 1, the entire RAM and the program ROM 1 in addresses 80000h to CFFFFh are available. Table 10.5 lists the Functions of Bits PM13 and IRON and Table 10.6 lists Functions of Addresses 80000h to CFFFFh. Table 10.5 Functions of Bits PM13 and IRON Bit Setting Access Area Internal RAM PM13 = 0 IRON = 0 (1) Addresses 00400h up to 03FFFh (15 Kbytes) are available (addresses 0400h to 0CFFFh cannot be used). Addresses D0000h up to FFFFFh (192 Kbytes) are available (addresses 40000h to CFFFFh cannot be used). IRON = 0 The entire area is usable. PM13 = 1 IRON = 1 The entire area is usable. Program ROM 1 Addresses 80000h up to FFFFFh are available (addresses 40000h to 7FFFFh cannot be used). Reserved Usable Reserved Reserved Usable Usable The entire area is usable. External Memory 04000h to Usable expansion 0CFFFh mode 40000h to Usable 7FFFFh 80000 to CFFFFh Microprocessor mode Usable Reserved Reserved Reserved Reserved Usable Usable 04000h to Usable 0CFFFh 40000h to Usable 7FFFFh 80000 to CFFFFh Usable PM13: Bit in the PM1 register IRON: Bit in the PRG2C register Note: 1. When the PM13 bit is 0, set the IRON bit to 0. Table 10.6 Functions of Addresses 80000h to CFFFFh PM13 Bit in PM1 Register Processor Mode Single-chip mode Memory expansion mode Microprocessor mode 0 1 Reserved area Program ROM 1 (when program ROM 1 exists) External area if not, reserved area External area External area The PM13 bit is automatically set to 1 while the FMR01 bit in the FMR0 register is set to 1 (CPU rewrite mode). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 155 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 10. Processor Mode 10.2.3 Program 2 Area Control Register (PRG2C) Program 2 Area Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PRG2C Address 0010h After Reset XXXX XX00b Bit Symbol PRG2C0 Bit Name Program ROM 2 disable bit Function 0 : Enable program ROM 2 1 : Disable program ROM 2 RW RW IRON — (b7-b2) Program ROM 1 addresses (40000h to 7FFFFh) Internal area expansion bit 1 0 : Disabled 1 : Enabled No register bits. If necessary, set to 0. Read as undefined value RW — Rewrite this register after setting the PRC6 bit in the PRCR register to 1 (write enabled). PRG2C0 (Program ROM 2 Disable Bit) (b0) This bit is used to select the function of addresses 10000h to 13FFFh. Table 10.7 lists Program ROM 2 (Addresses 10000h to 13FFFh). Table 10.7 Program ROM 2 (Addresses 10000h to 13FFFh) PRG2C0 bit in PRG2C Register Processor Mode Single-chip mode Memory expansion mode Microprocessor mode 0 Program ROM 2 Program ROM 2 Reserved area 1 Reserved area External area External area Program ROM 2 includes the on-chip debugger monitor area and user boot code area (refer to 30.7 “User Boot Function”). IRON (Internal Area Expansion Bit 1) (b1) This bit enables the program ROM 1 (addresses 40000h to 7FFFFh) for products with the size of program ROM 1 over 512 Kbytes. Table 10.8 lists Functions of Addresses 40000h to 7FFFFh. Table 10.5 lists Functions of Bits PM13 and IRON. Set the IRON bit to 0 when either of the following is true. • The PM13 bit in the PM1 register is 0 (maximum of 192 Kbytes are available in program ROM 1). • Bits PM15 and PM14 in the PM1 register are set to “11b” (4-Mbyte mode). Table 10.8 Functions of Addresses 40000h to 7FFFFh IRON Bit in PRG2C Register Processor Mode Single-chip mode 0 1 Reserved area Program ROM 1(when program ROM 1 exists) Memory expansion mode External area if not, reserved area Microprocessor mode External area External area REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 156 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 10. Processor Mode 10.3 10.3.1 Operations Processor Mode Settings Processor mode is set by using the CNVSS pin and bits PM01 to PM00 in the PM0 register. In hardware reset, power-on reset, or voltage monitor 0 reset, the processor mode is selected by the CNVSS pin input level. Table 10.9 lists Processor Mode after Hardware Reset, Power-On Reset, or Voltage Monitor 0 Reset. Table 10.9 Processor Mode after Hardware Reset, Power-On Reset, or Voltage Monitor 0 Reset CNVSS Pin Input Level VSS VCC1 Processor Mode Single-chip mode Microprocessor mode Bits PM01 to PM00 in the PM0 Register 00b (single-chip mode) 11b (microprocessor mode) Rewriting bits PM01 to PM00 places the MCU in the mode corresponding to bits PM01 to PM00 regardless of whether the input level of the CNVSS pin is high or low. When VCC1 is applied to the CNVSS pin and then the MCU is reset by hardware reset, power-on reset, or voltage monitor 0 reset, the internal ROM cannot be accessed regardless of the value of bits PM01 to PM00. Table 10.10 lists Bits PM01 to PM00 Set Values and Processor Modes. Do not rewrite these bits to enter microprocessor mode in the internal ROM, or to exit microprocessor mode in areas overlapping the internal ROM. Table 10.10 Bits PM01 to PM00 Set Values and Processor Modes Bits PM01 to PM00 00b 01b 10b 11b Processor Mode Single-chip mode Memory expansion mode Do not set Microprocessor mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 157 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group Figure 10.1 shows Memory Map in Single-Chip Mode. 10. Processor Mode Single-Chip Mode 00000h SFR 00400h Internal RAM XXXXXh Reserved area 0D000h SFR 0D800h Reserved area 0E000h Internal ROM (2) (data flash) Address XXXXXh PM13 bit in PM1 register RAM size 12 Kbytes 20 Kbytes 31 Kbytes 47 Kbytes 0 033FFh 03FFFh 03FFFh 03FFFh 1 033FFh 053FFh 07FFFh 0BFFFh 10000h 14000h Internal ROM (program ROM 2) Reserved area (3) YYYYYh Internal ROM (program ROM 1) Address YYYYYh IRON bit in PRG2C register PM13 bit in PM1 register Program 128 Kbytes ROM 1 256 Kbytes size 384 Kbytes 512 Kbytes 640 Kbytes 768 Kbytes 0 0 E0000h D0000h D0000h D0000h D0000h D0000h 1 E0000h C0000h A0000h 80000h 80000h 80000h 0 Do not set Do not set Do not set Do not set Do not set Do not set 1 1 E0000h C0000h A0000h 80000h 60000h 40000h FFFFFh Notes : 1. If the PM13 bit is 0, 15 Kbytes of internal RAM and 192 Kbytes of internal ROM can be used. 2. Data flash can be used when the PM10 bit in the PM1 register is 1 (0E000h to 0FFFFh are used as data flash). 3. Program ROM 2 can be used when the PRG2C0 bit in the PRG2C register is 0 (program ROM 2 enabled). Figure 10.1 Memory Map in Single-Chip Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 158 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 11. Bus 11. Bus Note Do not use bus control pins for the 80-pin package. 11.1 Introduction Two types of buses are available: • Internal bus in the MCU • External bus which is used to access to external devices in memory expansion mode or microprocessor mode Table 11.1 Bus Specifications Item Internal bus Specification External bus • Used in all processor modes • Separate bus • 16-bit data bus width • 0 to 2 software waits can be inserted • Used in memory expansion mode or microprocessor mode • Separate bus or multiplexed bus selectable • Data bus width selectable (8 or 16 bits) • Number of address buses selectable (12, 16, or 20 buses) • 4 chip select outputs CS0 to CS3 • Combinations of read and write signals selectable (RD, BHE, WR or RD, WRL, WRH) • RDY available • HOLD, HDLA available • 0 to 8 software waits can be inserted • Memory area expansion function (up to 4 Mbytes) (Refer to 12. “Memory Space Expansion Function”) • 3 V or 5 V interface REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 159 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 11. Bus 11.2 Registers Table 11.2 lists bus related registers. Refer to 10. “Processor Mode” for registers PM1 and PM2. Refer to 30. “Flash Memory” for the FMR1 register. Table 11.2 Register Structure Address 0005h 0008h 0009h 0011h 001Bh 001Eh 0221h Register Name Processor Mode Register 1 Chip Select Control Register External Area Recovery Cycle Control Register External Area Wait Control Expansion Register Chip Select Expansion Control Register Processor Mode Register 2 Flash Memory Control Register 1 Register Symbol After Reset PM1 0000 1000b CSR 01h EWR XXXX XX00b EWC CSE PM2 FMR1 00h 00h XX00 0X01b 00X0 XX0Xb REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 160 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 11. Bus 11.2.1 Chip Select Control Register (CSR) Chip Select Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol CSR Address 0008h After Reset 01h Bit Symbol CS0 Bit Name CS0 output enable bit Function 0 : Chip select output disabled (functions as I/O port) 1 : Chip select output enabled RW RW CS1 CS1 output enable bit RW CS2 CS2 output enable bit RW CS3 CS3 output enable bit 0 : Wait state 1 : No wait state RW CS0W CS0 wait bit RW CS1W CS1 wait bit RW CS2W CS2 wait bit RW CS3W CS3 wait bit RW CSiW (CSi Wait Bit) (b7-b4) (i = 0 to 3) Set the CSiW bit to 0 (wait state) under the following conditions: • The RDY signal is used in the area indicated by CSi. • Multiplexed bus is used in the area indicated by CSi. • The PM17 bit in the PM1 register is 1 (wait state). When the CSiW bit is 0 (wait state), the number of wait states can be selected using bits CSEi1W to CSEi0W in the CSE register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 161 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 11. Bus 11.2.2 Chip Select Expansion Control Register (CSE) Chip Select Expansion Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol CSE Address 001Bh After Reset 00h Bit Symbol CSE00W Bit Name b1 b0 Function 0 0 1 1 b3 RW RW RW RW RW RW RW RW RW CS0 wait expansion bit CSE01W CSE10W CS1 wait expansion bit CSE11W CSE20W CS2 wait expansion bit CSE21W CSE30W CS3 wait expansion bit CSE31W 0 : 1 wait (1φ + 1φ) 1 : 2 waits (1φ + 2φ) 0 : 3 waits (1φ + 3φ) 1 : Select wait states by bits EWC01 and EWC00 in the EWC register 0 : 1 wait (1φ + 1φ) 1 : 2 waits (1φ + 2φ) 0 : 3 waits (1φ + 3φ) 1 : Select wait states by bits EWC11 and EWC10 in the EWC register 0 : 1 wait (1φ + 1φ) 1 : 2 waits (1φ + 2φ) 0 : 3 waits (1φ + 3φ) 1 : Select wait states by bits EWC21 and EWC20 in the EWC register 0 : 1 wait (1φ + 1φ) 1 : 2 waits (1φ + 2φ) 0 : 3 waits (1φ + 3φ) 1 : Select wait states by bits EWC31 and EWC30 in the EWC register b2 0 0 1 1 b5 b4 0 0 1 1 b7 b6 0 0 1 1 Set the CSiW bit (i = 0 to 3) in the CSR register to 0 (wait state) before writing to bits CSEi1W to CSEi0W. To set the CSiW bit to 1 (no wait state), set bits CSEi1W to CSEi0W to 00b first, and then set the CSiW bit to 1. Do not set bits CSEi1W and CSEi0W to 11b for a multiplexed bus area. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 162 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 11. Bus 11.2.3 External Area Wait Control Expansion Register (EWC) External Area Wait Control Extension Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol EWC Address 0011h After Reset 00h Bit Symbol EWC00 Bit Name b1 b0 Function 0:2φ+3φ 1:2φ+4φ 0:3φ+4φ 1:4φ+5φ 0:2φ+3φ 1:2φ+4φ 0:3φ+4φ 1:4φ+5φ 0:2φ+3φ 1:2φ+4φ 0:3φ+4φ 1:4φ+5φ 0:2φ+3φ 1:2φ+4φ 0:3φ+4φ 1:4φ+5φ RW RW CS0 area wait extention bit EWC01 0 0 1 1 RW b3 b2 EWC10 CS1 area wait extention bit EWC11 0 0 1 1 RW RW b5 b4 EWC20 CS2 area wait extention bit EWC21 0 0 1 1 RW RW b7 b6 EWC30 CS3 area wait extention bit EWC31 0 0 1 1 RW RW This register can be used as a separate bus area. When bits CSEi1W and CSEi0W in the CSE register are 11b (select wait states by bits EWCi1 to EWCi0), bits EWCi1 to EWCi0 are enabled. (i = 0 to 3) The number of cycles is as follows. Example: 2φ + 3φ The number of cycles between the falling edge and the rising edge of the RD or WR signal The number of cycles between bus access start and the falling edge of the RD or WR signal REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 163 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 11. Bus 11.2.4 External Area Recovery Cycle Control Register (EWR) External Area Recovery Cycle Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol EWR Address 0009h After Reset XXXX XX00b Bit Symbol EWR0 Bit Name b1 b0 Function RW RW Recovery cycle insert bit EWR1 — (b7-b2) 0 0 1 1 0 : No recovery cycle 1 : 1 recovery cycle inserted 0 : 2 recovery cycles inserted 1 : 3 recovery cycles inserted RW No register bits. If necessary, set to 0. Read as undefined value — The EWR register is enabled when bits CSEi1W to CSEi0W in the CSE register is 11b. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 164 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 11. Bus 11.3 11.3.1 Operations Common Specifications of Internal Bus and External Bus Reference Clock 11.3.1.1 Both the internal and external buses operate based on the BCLK. However, the area accessed and wait states affect bus operation. Refer to 11.3.2.1 “Software Wait States of the Internal Bus” and 11.3.5.10 “Software Wait States” for details. 11.3.1.2 Bus Hold Both the internal and external buses are in a hold state under the following conditions: • Rewriting the flash memory in EW1 mode while auto-programming or auto-erasing • Inputting a low-level signal to the HOLD pin in memory expansion mode or microprocessor mode When the bus is in hold state, the following occur: • CPU is stopped • DMAC is stopped • Watchdog timer is stopped when the CSPRO bit in the CSPR register is 0 (count source protection mode disabled) Bus use priority is given to bus hold, DMAC, and CPU in descending order. However, if the CPU is accessing an odd address in word units, the DMAC cannot gain control of the bus between two separate accesses. Bus Hold > DMAC > CPU Figure 11.1 Bus Use Priority REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 165 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 11. Bus 11.3.2 Internal Bus The internal bus is used to access the internal area in the MCU. 11.3.2.1 Software Wait States of the Internal Bus The PM17 bit in the PM1 register, which is a software-wait-related bit, affects both the internal memory and the external area. Table 11.3 lists Bits and Bus Cycles Related to Software Wait States (SFR and Internal Memory). The data flash of the internal ROM is affected by both the PM17 bit in the PM1 register and the FMR17 bit in the FMR1 register. Table 11.3 Bits and Bus Cycles Related to Software Wait States (SFR and Internal Memory) Area SFR Internal RAM Internal ROM Setting of Software-Wait-Related Bits Software PM2 Register FMR1 Register PM1 Register Wait Bus cycle States FMR17 Bit PM17 Bit PM20 Bit (1) 1 0 or 1 0 or 1 1 2 BCLK cycles (2) 0 0 or 1 0 or 1 2 3 BCLK cycles 0 or 1 0 or 1 0 None 1 BCLK cycle (2) 0 or 1 0 1 1 0 1 0 or 1 0 1 1 None 1 1 None 1 2 BCLK cycles 1 BCLK cycle (2) 2 BCLK cycles 2 BCLK cycles (2) 1 BCLK cycle 2 BCLK cycle Program ROM 1 0 or 1 Program ROM 2 Data flash 0 or 1 Notes: 1. The PM20 bit is valid when the PLC07 bit in the PLC0 register is set to 1 (PLL operation). 2. Status after reset. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 166 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 11. Bus 11.3.3 External Bus The external bus is used to access external devices in memory expansion mode or microprocessor mode. In memory expansion or microprocessor mode, some pins serve as the bus control pins to perform data input to and output from external devices. The bus control pins are as follows: A0 to A19, D0 to D15, CS0 to CS3, RD, WRL /WR, WRH / BHE, ALE, RDY, HOLD, HLDA, and BCLK. 11.3.4 External Bus Mode Multiplexed bus mode or separate bus mode can be selected using bits PM05 to PM04 in the PM0 register. Table 11.4 shows the Difference between Separate Bus and Multiplexed Bus Modes. 11.3.4.1 Separate Bus In external bus mode, data and address are separate. 11.3.4.2 Multiplexed Bus In external bus mode, data and address are multiplexed. • When input level to the BYTE pin is high (8-bit data bus) D0 to D7 and A0 to A7 are multiplexed. • When input level to the BYTE pin is low (16-bit data bus) D0 to D7 and A1 to A8 are multiplexed. D8 to D15 are not multiplexed (do not use these pins). External devices connected to a multiplexed bus are assigned only even addresses of the MCU. Table 11.4 Difference between Separate Bus and Multiplexed Bus Modes Pin Name (1) P0_0 to P0_7/D0 to D7 Separate Bus Multiplexed Bus BYTE = high BYTE = low (Note 2) I/O port P1_0 to P1_7 A0 D0 (Note 2) D0 to D7 P1_0 to P1_7/D8 to D15 D8 to D15 (Note 2) P2_0/A0 (/ D0 / -) P2_1 to P2_7/A1 to A7 (/ D1 to D7 / D0 to D6) P3_0/A8 (/ - / D7) A0 A0 A1 to A7 A1 to A7 D1 to D7 A1 to A7 D0 to D6 A8 A8 A8 D7 Notes: 1. See Table 11.9 “Pin Functions for Each Processor Mode”, for bus control signals other than the above. 2. Depends on the setting of PM05 and PM04, and area being accessed. See Table 11.9 “Pin Functions for Each Processor Mode”, for details. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 167 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 11. Bus 11.3.5 External Bus Control The following describes the signals needed for accessing external devices and the functionality of software wait states. 11.3.5.1 Address Bus The address bus consists of 20 lines: A0 to A19. The address bus width can be set to 12, 16, or 20 bits using the PM06 bit in the PM0 register, and the PM11 bit in the PM1 register. Table 11.5 lists the Set Value of Bits PM06 and PM11 and the Corresponding Address Bus Widths. Table 11.5 Set Value of Bits PM06 and PM11 and the Corresponding Address Bus Widths Pin Function Bit Set Value (1) PM11 = 1 P3_4 to P3_7 PM06 = 1 P4_0 to P4_3 PM11 = 0 A12 to A15 PM06 = 1 P4_0 to P4_3 PM11 = 0 A12 to A15 PM06 = 0 A16 to A19 Note: 1. Only the values listed above can be set. Address Bus Width 12 bits 16 bits 20 bits When the processor mode is changed from single-chip mode to memory expansion mode, the address bus is undefined until an external area is accessed. 11.3.5.2 Data Bus When input to the BYTE pin is high (8-bit width), eight lines (D0 to D7) comprise the data bus. When input to the BYTE pin is low (16-bit width), 16 lines (D0 to D15) comprise the data bus. Do not change the input level to the BYTE pin. 11.3.5.3 Chip Select Signal The chip select signals (hereafter referred to as CS) are output from the CSi (i = 0 to 3) pin. These pins can be set to function as I/O ports or as CS using the CSi bit in the CSR register. In 1-Mbyte mode, the external area can be separated into a maximum of four spaces by the CSi signal. In 4-Mbyte mode, a C Si s ignal or bank number is output from the C Si pin. Refer to 12. “Memory Space Expansion Function”. Figure 11.2 shows Examples of Address Bus and CSi Signal Output in 1-Mbyte Mode. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 168 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 11. Bus Example 1 Accessing the external area indicated by CSj in the next cycle after accessing the external area indicated by CSi. The address bus and chip select signal both change state between these two cycles. Example 2 Accessing the internal ROM or internal RAM in the next cycle after accessing the external area indicated by CSi. The chip select signal changes state but the address bus does not change state. Access to the external area indicated by CSi Access to the external area indicated by CSj Access to the external area indicated by CSi Access to the internal ROM or internal RAM BCLK Read signal Data bus Address bus CSi CSj Data Data BCLK Read signal Data bus Address bus CSi Data Address Address Address Example 3 Accessing the external area indicated by CSi in the next cycle after accessing the external area indicated by the same CSi. The address bus changes state but the chip select signal does not change state. Example 4 Not accessing any area (no instruction prefetch generated) in the next cycle after accessing the external area indicated by CSi. Neither the address bus nor the chip select signal changes state between these two cycles. Access to the external area indicated by CSi Access to the same external area Access to the external area indicated by CSi No access BCLK Read signal Data bus Address bus CSi Data Data BCLK Read signal Data bus Address bus CSi Data Address Address Address Note: 1. These examples show the address bus and chip select signal when accessing areas in two successive cycles. The chip select bus cycle may be extended to more than two cycles depending on the combination of these examples. Shown above is the case where separate bus is selected and the area is accessed for read without wait states. i = 0 to 3, j = 0 to 3 (not including i, however) Figure 11.2 Examples of Address Bus and CSi Signal Output in 1-Mbyte Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 169 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 11. Bus 11.3.5.4 Read and Write Signals When the data bus is 16 bits wide, the read and write signals can be selected based on combinations of RD, BHE, and WR, or combinations of RD, WRL, and WRH using the PM02 bit in the PM0 register. When the data bus is 8 bits wide, use combinations of RD, WR, and BHE. Table 11.6 shows Operation of the RD, WRL and WRH Signals. Table 11.7 shows Operation of the RD, WR and BHE Signals. Table 11.6 Operation of the RD, WRL and WRH Signals RD WRL WRH Data Bus Width 16-bit (BYTE pin input = low) Status of External Data Bus Read data Write 1 byte of data to an even address Write 1 byte of data to an odd address Write data to both even and odd addresses L H H H H L H L H H L L Table 11.7 Operation of the RD, WR and BHE Signals RD WR BHE Data Bus Width 16-bit (BYTE pin input = low) A0 H H L L L L Status of External Data Bus H L H L H L L H L H L H L H L L H H L L − (1) − (1) 8-bit H (BYTE pin L input = high) Note: 1. Do not use. Write 1 byte of data to an odd address. Read 1 byte of data from an odd address. Write 1 byte of data to an even address. Read 1 byte of data from an even address. Write data to both even and odd addresses. Read data from both even and odd addresses. H or L Write 1 byte of data. H or L Read 1 byte of data. 11.3.5.5 ALE Signal The ALE signal is used to latch the address when a multiplexed bus space is accessed. Latch the address at the falling edge of the ALE signal. When BYTE pin input is high ALE A0/D0 to A7/D7 When BYTE pin input is low ALE A0 Address Address Data When bits PM05 and PM04 are 01b or 10b (the multiplexed bus is either the CS2 or CS1 area) A8 to A19 Address A1/D0 to A8/D7 Address Data A9 to A19 When bits PM05 and PM04 are 11b (the entire CS area is the multiplexed bus) A8 Address Address Figure 11.3 ALE Signal, Address Bus, and Data Bus REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 170 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 11. Bus 11.3.5.6 RDY Signal This signal is provided for accessing external devices which need to be accessed at low speed. If input to the RDY pin is low at the last falling edge of BCLK in the bus cycle, one wait state is inserted in the bus cycle. While in wait state, the following signals retain the state in which they were when the RDY signal was acknowledged: A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE, ALE, HLDA Then, when input to the RDY pin is detected high at the falling edge of BCLK, the remaining bus cycle is executed. Figure 11.4 shows Examples in Which Wait State Was Inserted into Read Cycle by RDY Signal. To use the RDY signal, set the corresponding bit (among bits CS3W to CS0W) in the CSR register to 0 (with wait state). When not using the RDY signal, pull-up the RDY pin. Separate bus BCLK RD CSi (i = 0 to 3) RDY tsu (RDY-BCLK) Accept timing of RDY signal Multiplexed bus BCLK RD CSi (i = 0 to 3) RDY tsu (RDY-BCLK) Accept timing of RDY signal : Wait using RDY signal : Wait using software tsu (RDY - BCLK) : Duration for RDY input setup Shown above is a case where bits CSEi1W to CSEi0W (i = 0 to 3) in the CSE register are 00b (one wait state). Figure 11.4 Examples in Which Wait State Was Inserted into Read Cycle by RDY Signal REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 171 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 11. Bus 11.3.5.7 HOLD Signal This signal is used to transfer control of the bus from the CPU or DMAC to an external circuit. When input to the HOLD pin is pulled low, the bus is placed in a hold state after the current bus access is completed. While the HOLD pin is held low, the bus remains in a hold state. When the bus is in a hold state, the HLDA pin outputs a low-level signal. Table 11.8 shows the Pin Status in Hold State Caused by the HOLD Input. Table 11.8 Pin Status in Hold State Caused by the HOLD Input Item BCLK A0 to A19, D0 to D15, CS0 to CS3, RD, WRL,WRH, WR, BHE I/O ports HLDA Status Output High-impedance High-impedance Maintains status when HOLD signal is received Low-level output Undefined P0, P1, P3, P4 (1) P6 to P14 ALE Note: 1. When I/O port function is selected. 11.3.5.8 BCLK Output When the PM07 bit in the PM0 register is set to 0 (output enabled), a clock with the same frequency as the CPU clock is output as BCLK from the BCLK pin. Refer to 8.4 “CPU Clock and Peripheral Function Clocks”. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 172 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 11. Bus Table 11.9 Pin Functions for Each Processor Mode Memory Expansion Mode or Microprocessor Mode 00b (separate bus) 01b (CS2 is for multiplexed bus and the others are for separate bus) 10b (CS1 is for multiplexed bus and the others are for separate bus) 8 bits High D0 to D7 (6) I/O ports A0/D0 (4) Processor Mode Bits PM05 to PM04 Memory Expansion Mode 11b (the entire space of CS is for multiplexed bus) (1), (2), (3) 8 bits High I/O ports I/O ports A0/D0 A1 to A7 /D1 to D7 A8 I/O ports I/O ports I/O ports Data bus width BYTE Pin P0_0 to P0_7 P1_0 to P1_7 P2_0 P2_1 to P2_7 P3_0 P3_1 to P3_3 P3_4 to P3_7 P4_0 to P4_3 P4_4 P4_5 P4_6 P4_7 P5_0 P5_1 P5_2 P5_3 P5_4 P5_5 P5_6 P5_7 PM11 = 0 PM11 = 1 PM06 = 0 PM06 = 1 CS0 = 0 CS0 = 1 CS1 = 0 CS1 = 1 CS2 = 0 CS2 = 1 CS3 = 0 CS3 = 1 PM02 = 0 PM02 = 1 PM02 = 0 PM02 = 1 8 bits High D0 to D7 I/O ports A0 A1 to A7 A8 A9 to A11 A12 to A15 I/O ports A16 to A19 I/O ports I/O ports CS0 16 bits Low D0 to D7 D8 to D15 A0 A1 to A7 A8 16 bits Low D0 to D7 (6) D8 to A0 A1 to A7 /D0 to D6 (4) A8/D7 (4) D15(6) A1 to A7 /D1 to D7 (4) A8 I/O ports CS1 I/O ports CS2 I/O ports CS3 WR − (5) BHE − (5) RD WRH − (5) WRH − (5) WRL − (5) WRL − (5) BCLK HLDA HOLD ALE RDY I/O port: Functions as I/O ports or peripheral function I/O pins. Notes: 1. When bits PM01 to PM00 are 01b (memory expansion mode), and bits PM05 to PM04 are set to 11b (multiplexed bus assigned to the entire CS space), apply a high-level signal to the BYTE pin (external data bus 8 bits wide). 2. While the CNVSS pin is driven high (= VCC1), do not set bits PM05 to PM04 to 11b. 3. When bits PM05 to PM04 are set to 11b in memory expansion mode, P3_1 to P3_7 and P4_0 to P4_3 become I/O ports, in which case the accessible area for each CS is 256 bytes. 4. In separate bus mode, these pins serve as the address bus. 5. When the data bus is 8 bits wide, set the PM02 bit to 0 (RD, BHE, WR). 6. When accessing an area using a multiplexed bus, these pins output an undefined value while writing. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 173 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 11. Bus 11.3.5.9 External Bus Status When Internal Area is Accessed Table 11.10 lists the External Bus Status When an Internal Area is Accessed. Figure 11.5 shows the Typical Bus Timings When Accessing SFRs. Table 11.10 A0 to A19 D0 to D15 Read Write RD, WR, WRL, WRH BHE CS0 to CS3 External Bus Status When an Internal Area is Accessed Item SFR Accessed Address output High-impedance Data output RD, WR, WRL, WRH output BHE output Internal ROM or RAM Accessed Maintain the last accessed address of external area or SFR High-impedance Undefined High-level output Maintain the last accessed status of external area or SFRs High-level output Low-level output High-level output Low-level output ALE (1) 1 Wait State (1 φ + 1φ) Bus cycle = 2φ BCLK Address High Bus cycle = 2φ A A CSi Data RD WR, WRL, WRH WD RD (2) 2 Wait States (1φ + 2φ) Bus cycle = 3φ BCLK Address High Bus cycle = 3φ A A CSi Data RD WR, WRL, WRH WD RD i = 0 to 3 A : Address RD : Read data WD : Write data Figure 11.5 Typical Bus Timings When Accessing SFRs REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 174 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 11. Bus 11.3.5.10 Software Wait States The PM17 bit in the PM1 register, which is a software-wait-related bit, affects both the internal memory and the external area. Software wait states can be inserted to the external area by setting the PM17 bit or setting the CSiW bit in the CSR register or bits CSEi1W to CSEi0W in the CSE register for each CSi (i = 0 to 3). To use the RDY signal, set the corresponding CSiW bit to 0 (wait state). Refer to Table 11.11 “Bits and Bus Cycles Related to Software Wait States (External Area)”, for details. Table 11.11 Bits and Bus Cycles Related to Software Wait States (External Area) Area Bus Mode External area Separate bus Setting of Software-Wait-Related Bits PM17 CSiW CSEi1W, EWCi1, CSEi0W EWCi0 0 1 00b - Software Wait Cycles None Bus Cycles 1 BCLK cycle (read) 2 BCLK cycles (write) 2 BCLK cycles (4) 3 BCLK cycles 4 BCLK cycles 5 BCLK cycles 6 BCLK cycles 7 BCLK cycles 9 BCLK cycles 2 BCLK cycles 3 BCLK cycles 3 BCLK cycles 4 BCLK cycles 3 BCLK cycles - 0 0 0 0 00b 01b 10b 11b 00b 01b 10b 11b - 1 (1φ + 1φ) 2 (1φ + 2φ) 3 (1φ + 3φ) (2φ + 3φ) (2φ + 4φ) (3φ + 4φ) (4φ + 5φ) 1 (1φ + 1φ) 1 2 3 1 1 Multiplexed bus 1 0 (3) 0 (2) 0 0 0 (2) (2) (2), (3) 00b 00b 01b 10b 00b i = 0 to 3 − indicates that either 0 or 1 can be set. PM17: Bit in the PM1 register CSiW: Bits in the CSR register (1) CSEi1W, CSEi0W: Bits in the CSE register EWCi1, EWCi0: Bits in the EWC register Notes: 1. To use the RDY signal, set the CSiW bit to 0 (wait state). 2. To access in multiplexed bus mode, set the CSiW bit to 0 (wait state). 3. To access an external area when the PM17 bit is 1, set the CSiW bit to 0 (wait state). 4. After reset, the PM17 bit is set to 0 (no wait state), bits CS0W to CS3W are set to 0 (wait state), and the CSE register is set to 00h (one wait state for CS0 to CS3). Therefore, all external areas are accessed with one wait state. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 175 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 11. Bus (1) Separate Bus, No Wait States Bus cycle = 2φ Bus cycle = 2φ BCLK Address CSi Data RD WR, WRL, WRH (Note 1) A A WD RD (2) Separate Bus, One Wait State (1 φ + 1φ) Bus cycle = 2φ BCLK Address CSi Data RD WR, WRL, WRH (Note 1) Bus cycle = 2φ A A WD RD (3) Separate Bus, Two Wait States (1 φ + 2φ) Bus cycle = 3φ BCLK Address CSi Data RD WR, WRL, WRH WD A Bus cycle = 3φ A RD (Note 1) i = 0 to 3 A : Address RD : Read data (input) WD : Write data (output) Note: 1. When accessing consecutively to the same chip-select area, CSi keeps ouputting low level. Figure 11.6 Typical Bus Timings Using Software Wait States (1/4) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 176 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 11. Bus (1) Separate Bus, Three Wait States (1 φ + 3φ) Bus cycle = 4φ Bus cycle = 4φ BCLK Address CSi Data RD WR, WRL, WRH (Note 1) A A WD RD (2) Multiplexed Bus, One or Two Wait States (1 φ + 2φ) Bus cycle = 3φ BCLK Address Address/Data ALE CSi RD WR, WRL, WRH (Note 1) Bus cycle = 3φ A A WD A A RD (3) Multiplexed Bus, Three Wait States (1 φ + 3φ) Bus cycle = 4φ BCLK Address Address/Data ALE CSi RD WR, WRL, WRH i = 0 to 3 A : Address (Note 1) Bus cycle = 4φ A A WD A A RD RD : Read data (input) WD : Write data (output) Note: 1. When accessing consecutively to the same chip-select area, CSi keeps ouputting low level. Figure 11.7 Typical Bus Timings Using Software Wait States (2/4) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 177 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 11. Bus (1) Bus cycle 2 φ + 3 φ 1 bus cycle = 5 φ BCLK Address CSi Read data RD Write data WR, WRL, WRH WD RD A (Note1) (2) Bus cycle 2 φ + 4 φ 1 bus cycle = 6 φ BCLK Address CSi Read data RD Write data WR, WRL, WRH WD A (Note1) RD i = 0 to 3 A : Address RD : Read data (input) WD : Write data (output) Note: 1. When accessing consecutively to the same chip-select area, CSi keeps ouputting low level. Figure 11.8 Typical Bus Timings Using Software Wait States (3/4) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 178 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 11. Bus (3) Bus cycle 3φ + 4φ 1 bus cycle = 7φ BCLK Address CSi Read data RD Write data WR, WRL, WRH WD RD A (Note1) (4) Bus cycle 4φ + 5φ 1 bus cycle = 9φ BCLK Address CSi Read data RD Write data WR, WRL, WRH WD RD A (Note1) i = 0 to 3 A : Address RD : Read data (input) WD : Write data (output) Note: 1. When accessing consecutively to the same chip-select area, CSi keeps ouputting low level. Figure 11.9 Typical Bus Timings Using Software Wait States (4/4) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 179 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 11. Bus Recovery cycle BCLK Address CSi Read data RD Write data WR, WRL, WRH WD RD A ← Address is held (1) ← Data is held i = 0 to 3 A: Address RD: Read data (input) WD: Write data (output) Note: 1. When consecutively accessing to the same chip-select area, CSi keeps outputting a low level. The above diagram shows a case under the following conditions: - Bits EWR1 and EWR0 in the EWR register are 01b (one recovery cycle inserted). - The CSiW bit in the CSR register is 0 (wait state). - Bits CSEi1W and CSEi0W in the CSE register are 11b (select a bus cycle pattern by the EWC register ). - Bits EWCi1 and EWCi0 in the EWC register are 00b (2 φ + 3 φ). Figure 11.10 Recovery Cycle REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 180 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 11. Bus 11.4 11.4.1 Notes on Bus Reading Data Flash When 2.7 V ≤ VCC1 ≤ 3.0 V and f(BCLK) ≥ 16 MHz, or when 3.0 V < VCC1 ≤ 5.5 V and f(BCLK) ≥ 20 MHz, one wait state is necessary to read data flash. Use the PM17 bit or the FMR17 bit to specify one wait state. 11.4.2 External Bus When a hardware reset, power-on reset or voltage monitor 0 reset is performed with a high-level input on the CNVSS pin, contents of internal ROM cannot be read. 11.4.3 External Access Soon After Writing to the SFRs When writing to the SFRs is followed by accessing to an external device, the write signal and CSi signal switch simultaneously. Thus, adjust the capacity of individual signal not to make a write signal delay. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 181 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 12. Memory Space Expansion Function 12. Memory Space Expansion Function Note Do not use this function for the 80-pin package. 12.1 Introduction The following describes the memory space expansion function. In memory expansion or microprocessor mode, the memory space expansion function allows the access space to be expanded. Table 12.1 lists Specifications of Memory Space Expansion Function. In this chapter, the space for the external devices accessed by the CSi (i = 0 to 3) signal is referred to as the CSi area. Table 12.1 Specifications of Memory Space Expansion Function Item 1-Mbyte mode 4-Mbyte mode Specifications • Memory space 1 Mbyte (no expansion) • Specify the space for the external devices accessed by the CSi signal. • Memory space 4 Mbytes • Select bank numbers to access to data. • Allows the accessed address to be offset by 40000h • The CSi pin function differs depending on the area to be accessed. i = 0 to 3 12.2 Registers Table 12.2 lists registers related to the memory expansion function. Refer to 10. “Processor Mode” for the PM1 register. Table 12.2 Register Structure Address 0005h 000Bh Register Name Processor Mode Register 1 Data Bank Register Register Symbol After Reset PM1 0000 1000b DBR 00h REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 182 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 12. Memory Space Expansion Function 12.2.1 Data Bank Register (DBR) Data Bank Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DBR Bit Symbol — (b1-b0) OFS Address 000Bh Bit Name After Reset 00h Function RW — No register bits. If necessary, set to 0. Read as 0 0 : No offset 1 : Offset Offset bit RW BSR0 b5 b4 b3 b5 b4 b3 RW 0 0 1 1 0 1 0 1 0 0 0 0 : Bank 0 : Bank 2 : Bank 4 : Bank 6 0 0 1 1 0 1 0 1 1 1 1 1 : Bank 1 : Bank 3 : Bank 5 : Bank 7 BSR1 Bank select bit RW BSR2 — (b7-b6) RW No register bits. If necessary, set to 0. Read as 0 — The DBR register is valid when bits PM01 to PM00 in the PM0 register are 01b (memory expansion mode) or 11b (microprocessor mode). A write to the DBR register is enabled when bits PM15 to PM14 in the PM1 register is 11b (4-Mbyte mode). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 183 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 12. Memory Space Expansion Function 12.3 12.3.1 Operations 1-Mbyte Mode In 1-Mbyte mode, the memory space is 1 Mbyte. The external area to be accessed is specified using the CSi signals. Figure 12.1 and Figure 12.2 show the memory mapping and CS areas in 1-Mbyte mode. Memory expansion mode 00000h 00400h XXXXXh Reserved area 04000h 08000h 0D000h 0D800h 0E000h 10000h 14000h 27000h 28000h 30000h External area SFR Data flash (2) Program ROM 2 (3) Microprocessor mode SFR Internal RAM (1) Reserved area SFR Internal RAM (1) CS3 (16 Kbytes) SFR Reserved, external area Reserved, external area (4) (5) CS2 Reserved area Reserved area CS1(32 Kbytes) External area D0000h YYYYYh CS0 Reserved area Program ROM 1 (1) FFFFFh Notes : 1. When the PM13 bit in the PM1 register is 0, 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used. See the table below for addresses XXXXXh and YYYYYh. Internal RAM Program ROM1 Capacity Address XXXXXh Capacity Address YYYYYh 12 Kbytes 128 Kbytes 033FFh E0000h 20 Kbytes 256 Kbytes D0000h 03FFFh 384 Kbytes D0000h 31 Kbytes 03FFFh D0000h 47 Kbytes 512 Kbytes 03FFFh 640 Kbytes 768 Kbytes D0000h D0000h 2. When the PM10 bit is 0, this area is used as an external area; when 1, used as internal ROM (data flash). 3. When the PRG2C0 bit in the PRG2C register is 1, this area is used as an external area; when 0, used as internal ROM (program ROM 2). 4. When the PM10 bit is 0, this area is used as an external area; when 1, used as a reserved area. 5. When the PRG2C0 bit in the PRG2C register is 1, this area is used as an external area; when 0, used as a reserved area. Figure 12.1 Memory Mapping and CS Areas in 1-Mbyte Mode (PM13 = 0) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 184 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 12. Memory Space Expansion Function Memory expansion mode 00000h 00400h Internal RAM (1) XXXXXh SFR Microprocessor mode SFR Internal RAM (1) 08000h 0D000h 0D800h 0E000h 10000h 14000h 27000h 28000h 30000h Reserved area SFR Data flash (2) Program ROM 2 (3) Reserved area SFR Reserved, external area Reserved, external area (4) (5) CS2 Reserved area Reserved area CS1 (32 Kbytes) External area External area CS0 80000h YYYYYh Program ROM 1 (1) FFFFFh Notes : 1. See the table below for addresses XXXXXh and YYYYYh. Internal RAM Capacity Address XXXXXh Capacity 128 Kbytes 12 Kbytes 033FFh 256 Kbytes 20 Kbytes 053FFh 384 Kbytes 31 Kbytes 07FFFh 512 Kbytes 47 Kbytes 0BFFFh 640 Kbytes 768 Kbytes IRON : Bit in the PRG2C register 2. When the PM10 bit is 0, this area is used as an external area; when 1, used as internal ROM (data flash). 3. When the PRG2C0 bit in the PRG2C register is 1, this area is used as an external area; when 0, used as internal ROM (program ROM 2). 4. When the PM10 bit is 0, this area is used as an external area; when 1, used as a reserved area. 5. When the PRG2C0 bit in the PRG2C register is 1, this area is used as an external area; when 0, used as a reserved area. Program ROM1 Address YYYYYh Reserved area E0000h C0000h A0000h 80000h 80000h (when IRON = 0) 60000h (when IRON = 1) 80000h (when IRON = 0) 40000h (when IRON = 1) Figure 12.2 Memory Mapping and CS Areas in 1-Mbyte Mode (PM13 = 1) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 185 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 12. Memory Space Expansion Function 12.3.2 4-Mbyte Mode In 4-Mbyte mode, the memory space is 4 Mbytes. Set the IRON bit in the PRG2C register to 0 (program ROM 1 addresses 40000h to 7FFFFh disabled). Bits BSR2 to BSR0 in the DBR register select the bank number to be accessed to read or write data. Setting the OFS bit to 1 (offset) allows the accessed address to be offset by 40000h. In 4-Mbyte mode, the CSi pin function differs depending on the area to be accessed. 12.3.2.1 Addresses 04000h to 3FFFFh, C0000h to FFFFFh • The CSi signal is output from the CSi pin (same operation as 1-Mbyte mode, except the last address of the CS1 area is up to 3FFFFh). 12.3.2.2 Addresses 40000h to BFFFFh • The CS0 pin outputs a low-level signal. • Pins CS1 to CS3 output the setting values of bits BSR2 to BSR0 (bank number). Figure 12.3 and Figure 12.4 show the memory mapping and CS areas in 4-Mbyte mode. Note that banks 0 to 6 are data-only areas. Place programs in bank 7 or the CSi area. Memory expansion mode 00000h 00400h XXXXXh Reserved area 04000h 08000h 0D000h 0D800h 0E000h 10000h 14000h 27000h 28000h 40000h External area SFR Data flash (2) Program ROM 2 (3) SFR Internal RAM (1) Microprocessor mode SFR Internal RAM (1) Reserved area CS3 (16 Kbytes) SFR Reserved, external area (4) Reserved, external area (5) CS2 Reserved area Reserved area CS1 (96 Kbytes) External area Other than the CS area (512 Kbytes x 8 banks) CS0 (memory expansion mode : 64 Kbytes) C0000h D0000h YYYYYh Program ROM 1 FFFFFh (1) Reserved area CS0 Notes : 1. When the PM13 bit in the PM1 register is 0, 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used. See the table below for addresses XXXXXh and YYYYYh. Internal RAM Capacity Address XXXXXh 12 Kbytes 033FFh 03FFFh 20 Kbytes 03FFFh 31 Kbytes 47 Kbytes 03FFFh Program ROM 1 Capacity Address YYYYYh 128 Kbytes E0000h 256 Kbytes D0000h 384 Kbytes D0000h D0000h 512 Kbytes 640 Kbytes 768 Kbytes D0000h D0000h 2. When the PM10 bit is 0, this area is used as an external area; when 1, used as internal ROM (data flash). 3. When the PRG2C0 bit in the PRG2C register is 1, this area is used as an external area; when 0, used as internal ROM (program ROM 2). 4. When the PM10 bit is 0, this area is used as an external area; when 1, used as a reserved area. 5. When the PRG2C0 bit in the PRG2C register is 1, this area is used as an external area; when 0, used as a reserved area. 6. The CS0 pin outputs a low signal, and pins CS1 to CS3 output a bank number. Figure 12.3 Memory Mapping and CS Areas in 4-Mbyte Mode (PM13 = 0) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 186 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 12. Memory Space Expansion Function Memory expansion mode 00000h 00400h XXXXXh SFR Internal RAM (1) Microprocessor mode SFR Internal RAM (1) 08000h 0D000h 0D800h 0E000h 10000h 14000h 27000h 28000h 40000h Reserved area SFR Data flash (2) Program ROM 2 (3) Reserved area SFR Reserved, external area Reserved, external area (4) (5) CS2 Reserved area Reserved area CS1 (96 Kbytes) External area External area Other than the CS area (Note 6) 80000h C0000h YYYYYh FFFFFh Notes : 1. See the table below for addresses XXXXXh and YYYYYh. Internal RAM Capacity Address XXXXXh 12 Kbytes 033FFh 053FFh 20 Kbytes 07FFFh 31 Kbytes 47 Kbytes 0BFFFh Program ROM 1 Capacity Address YYYYYh 128 Kbytes E0000h 256 Kbytes C0000h 384 Kbytes A0000h 80000h 512 Kbytes 640 Kbytes 768 Kbytes 80000h 80000h Reserved area CS0 (256 Kbytes) Program ROM 1 (1) 2. When the PM10 bit is 0, this area is used as an external area; when 1, used as internal ROM (data flash). 3. When the PRG2C0 bit in the PRG2C register is 1, this area is used as an external area; when 0, used as internal ROM (program ROM 2). 4. When the PM10 bit is 0, this area is used as an external area; when 1, used as a reserved area. 5. When the PRG2C0 bit in the PRG2C register is 1, this area is used as an external area; when 0, used as a reserved area. 6. The CS0 pin outputs a low signal, and pins CS1 to CS3 output a bank number. Figure 12.4 Memory Mapping and CS Areas in 4-Mbyte Mode (PM13 = 1) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 187 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 12. Memory Space Expansion Function In the example below, the CS pin of a 4-Mbyte ROM is connected to the MCU’s CS0 pin. The 4-Mbyte ROM address input pins AD21, AD20, and AD19 are connected to the MCU’s CS3, CS2, and CS1 pins, respectively. The address input AD18 pin is connected to the MCU’s A19 pin. Figure 12.6 to Figure 12.8 show the relationship of addresses between the 4-Mbyte ROM and the MCU in the connection example of Figure 12.5. In microprocessor mode or memory expansion mode, where the PM13 bit in the PM1 register is 0, banks are located every 512 Kbytes. Setting the OFS bit in the DBR register to 1 (offset) allows the accessed address to be offset by 40000h, allowing even data overlapping at a bank boundary to be accessed in succession. In memory expansion mode, where the PM13 bit is 1, each 512-Kbyte bank can be accessed in 256 Kbyte units by switching them with the OFS bit. Because the SRAM can be accessed when the chip select signals S2 is high and S1 is low, CS0 and CS2 can be connected to S2 and S1, respectively. If SRAM does not have the input pins that accept high active and low active chip select signals (S1, S2), CS0 and CS2 should be decoded externally to the chip. D0 to D7 A0 to A16 A17 A19 8 DQ0 to DQ7 17 AD0 to AD16 AD18 AD19 AD20 AD21 OE CS DQ0 to DQ7 AD0 to AD16 OE S2 S1 (1) W CS1 CS2 CS3 RD CS0 Note : 1. If only one chip select pin (S1 or S2) is present, an external circuit must be used for decoding. Figure 12.5 External Memory Connection Example in 4-Mbyte Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 188 of 791 128-Kbyte SRAM WR 4-Mbyte ROM AD17 MCU Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 12. Memory Space Expansion Function Memory expansion mode where PM13 is 0 ROM address MCU address OFS bit in DBR register = 0 000000h 40000h OFS bit in DBR register = 1 Output from the MCU Pins Bank Number OFS Access Area CS Output CS3 CS2 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 CS1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 A19 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 1 1 Address Output A18 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 1 A17 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 A16 A15 to A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0 0 40000h 40000h BFFFFh 40000h BFFFFh 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 000000h 07FFFFh 040000h 0BFFFFh 080000h 0FFFFFh 0C0000h 13FFFFh 100000h 17FFFFh 140000h 1BFFFFh 180000h 1FFFFFh 1C0000h 23FFFFh 200000h 27FFFFh 240000h 2BFFFFh 280000h 2FFFFFh 2C0000h 33FFFFh 300000h 37FFFFh 340000h 3BFFFFh 380000h 3BFFFFh 3C0000h 3FFFFFh 3C0000h 3CFFFFh Internal ROM access Internal ROM access Internal ROM access Internal ROM access 040000h 080000h bank 0 (512 Kbytes) BFFFFh 40000h 1 0 1 1 0 2 1 0 3 1 0 4 1 0 5 1 0 6 1 bank 0 (512 Kbytes) BFFFFh 40000h bank 1 0C0000h 100000h (512 Kbytes) BFFFFh 40000h 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h 7FFFFh 80000h BFFFFh C0000h CFFFFh D0000h DFFFFh D0000h DFFFFh bank 1 (512 Kbytes) BFFFFh 40000h bank 2 140000h (512 Kbytes) BFFFFh 40000h bank 2 (512 Kbytes) BFFFFh 40000h 180000h Data only 1C0000h bank 3 (512 Kbytes) BFFFFh 40000h bank 3 (512 Kbytes) BFFFFh 40000h 200000h bank 4 240000h 280000h (512 Kbytes) BFFFFh 40000h bank 4 (512 Kbytes) BFFFFh 40000h bank 5 2C0000h (512 Kbytes) BFFFFh 40000h 300000h bank 5 (512 Kbytes) BFFFFh 40000h bank 6 340000h (512 Kbytes) BFFFFh 40000h bank 6 (512 Kbytes) BFFFFh Program or data Program or data 380000h bank 7 3C0000h 3FFFFFh (512 Kbytes) BFFFFh 7 0 A21 A20 A19 A18 N.C. A17 A16 A15 to A0 Address input for 4-Mbyte ROM 4-Mbyte ROM access area Figure 12.6 Relationship between Addresses in 4-Mbyte ROM and Those in MCU (1/3) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 189 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 12. Memory Space Expansion Function Memory expansion mode where PM13 is 1 ROM address MCU address OFS bit in DBR register = 0 000000h Output from the MCU Pins Bank Number OFS Access Area CS Output CS3 CS2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 CS1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 A19 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 Address Output A18 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A17 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A15 to A0 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh OFS bit in DBR register = 1 bank 0 40000h (256 Kbytes) 7FFFFh 0 bank 0 40000h 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh 80000h FFFFFh 40000h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 000000h 03FFFFh 040000h 07FFFFh 080000h 0BFFFFh 0C0000h 0FFFFFh 100000h 13FFFFh 140000h 17FFFFh 180000h 1BFFFFh 1C0000h 1FFFFFh 200000h 23FFFFh 240000h 27FFFFh 280000h 2BFFFFh 2C0000h 2FFFFFh 300000h 33FFFFh 340000h 37FFFFh 380000h 3BFFFFh Internal ROM access Internal ROM access 040000h 080000h 0 1 0 (256 Kbytes) 7FFFFh bank 1 40000h (256 Kbytes) 7FFFFh 0C0000h 100000h bank 1 bank 2 40000h (256 Kbytes) 7FFFFh 40000h (256 Kbytes) 7FFFFh 1 1 0 140000h bank 2 bank 3 40000h (256 Kbytes) 7FFFFh 40000h (256 Kbytes) 7FFFFh 2 1 0 180000h Data only 1C0000h bank 3 bank 4 40000h (256 Kbytes) 7FFFFh 40000h (256 Kbytes) 7FFFFh 3 1 0 200000h 240000h 280000h bank 4 bank 5 40000h (256 Kbytes) 7FFFFh 40000h 4 1 0 (256 Kbytes) 7FFFFh 2C0000h bank 5 bank 6 40000h (256 Kbytes) 7FFFFh 40000h (256 Kbytes) 7FFFFh 5 1 0 300000h 340000h bank 6 bank 7 40000h (256 Kbytes) 7FFFFh 40000h 6 1 (256 Kbytes) 7FFFFh Program or data Data only 380000h 3C0000h 3FFFFFh bank 7 40000h 7 0 (256 Kbytes) 7FFFFh 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0000h FFFFh 3C0000h 3FFFFFh Internal ROM access Internal ROM access 7 1 7FFFFh 80000h FFFFFh A21 A20 A19 A18 N.C. A17 A16 A15 to A0 Address input for 4-Mbyte ROM 4-Mbyte ROM access area Figure 12.7 Relationship between Addresses in 4-Mbyte ROM and Those in MCU (2/3) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 190 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 12. Memory Space Expansion Function Microprocessor mode ROM address MCU address OFS bit in DBR register = 0 000000h 40000h Output from the MCU Pins Bank Number OFS Access Area CS Output CS3 CS2 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 A20 CS1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 A19 A19 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 1 1 A18 Address Output A18 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 1 N.C. A17 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A17 A16 A15 to A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh OFS bit in DBR register = 1 0 bank 0 040000h 080000h (512 Kbytes) BFFFFh 40000h 40000h 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h 7FFFFh 80000h BFFFFh C0000h FFFFFh 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A21 000000h 07FFFFh 040000h 0BFFFFh 080000h 0FFFFFh 0C0000h 13FFFFh 100000h 17FFFFh 140000h 1BFFFFh 180000h 1FFFFFh 1C0000h 23FFFFh 200000h 27FFFFh 240000h 2BFFFFh 280000h 2FFFFFh 2C0000h 33FFFFh 300000h 37FFFFh 340000h 3BFFFFh 380000h 3BFFFFh 3C0000h 3FFFFFh 3C0000h 3FFFFFh 4-Mbyte ROM access area 0 1 bank 0 (512 Kbytes) BFFFFh 40000h 0 1 1 bank 1 0C0000h (512 Kbytes) BFFFFh 40000h bank 1 (512 Kbytes) BFFFFh 40000h 100000h 0 2 1 bank 2 140000h (512 Kbytes) BFFFFh 40000h bank 2 (512 Kbytes) BFFFFh 40000h 180000h 0 3 1 Data only 1C0000h bank 3 (512 Kbytes) BFFFFh 40000h bank 3 (512 Kbytes) BFFFFh 40000h 200000h 0 4 1 0 5 1 bank 4 240000h 280000h (512 Kbytes) BFFFFh 40000h bank 4 (512 Kbytes) BFFFFh 40000h bank 5 2C0000h (512 Kbytes) BFFFFh 40000h bank 5 (512 Kbytes) 300000h 0 bank 6 340000h (512 Kbytes) BFFFFh bank 7 40000h (512 Kbytes) 7FFFFh C0000h FFFFFh BFFFFh 40000h 6 1 bank 6 (512 Kbytes) BFFFFh Program or data Program or data 380000h 3C0000h 3FFFFFh 7 0 A16 A15 to A0 Address input for 4-Mbyte ROM Figure 12.8 Relationship between Addresses in 4-Mbyte ROM and Those in MCU (3/3) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 191 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports 13. Programmable I/O Ports Note P1, P4_4 to P4_7, P7_2 to P7_5, and P9_1 of the 80-pin package have no external connections. Program the direction bits of these ports to 1 (output mode) and the output data to 0 (low level). For the 80-pin and 100-pin packages, do not access the addresses of registers P11 to P14, PD11 to PD14 and PUR3. 13.1 Introduction Table 13.1 lists Programmable I/O Ports Specifications (hereafter referred to as I/O ports). Each pin functions as an I/O port, a peripheral function input/output, or a bus control pin. To set peripheral functions, refer to the description for the individual function. To use ports as peripheral function input/output pins, refer to 13.4 “Peripheral Function I/O”. To use ports as bus control pins, refer to 11.3.5 “External Bus Control”. Table 13.1 Programmable I/O Ports Specifications Item The number of ports Total CMOS output Specification 128-pin package 114 111 88 85 3 100-pin package 71 68 3 P0, P2 to P10 80-pin package N-channel open-drain 3 output Input/output VCC2 level VCC1 level Input/output level Select function Note: 1. P6 to P11, P14 (1) P0 to P5, P12, P13 (1) P0 to P5 P6 to P10 Select input or output for each individual port by a program. Select a pull-up resistor in 4-bit units. P11 to P14 can be used when the PU37 bit in the PUR3 register is 1 (P11 to P14 enabled). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 192 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports Table 13.2 I/O Pins Pin Name I/O Type Function Input/output port CMOS output, pull-up resistor selectable P0_0 to P0_7, P1_0 to P1_7, I/O P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7 P7_0 to P7_7 I/O Input/output port P7_0 to P7_1: N-channel open-drain output, no pull-up resistor P7_2 to P7_7: CMOS output, pull-up resistor selectable Input/output port P8_0 to P8_4, P8_6, P8_7: CMOS output, pull-up resistor selectable P8_5: N-channel open-drain output, no pull-up resistor Input/output port CMOS output, pull-up resistor selectable P8_0 to P8_7 I/O P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_1 I/O REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 193 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports 13.2 I/O Ports and Pins Figure 13.1 to Figure 13.9 show I/O Ports, and Figure 13.10 shows I/O Pins. Pull-up selection P0_0 to P0_7, P2_0 to P2_3, P2_6 to P2_7, P10_0 to P10_3 (dotted section included) Direction register Data bus Port latch P3_0 to P3_7, P4_0 to P4_3, P5_0 to P5_4, P5_6, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 (Note 1) (dotted section not included) Analog input Pull-up selection Direction register 1 P1_0 PCR0 bit output Data bus Port latch (Note 1) Input to respective peripheral functions Note: 1. Symbolizes a parasitic diode. Make sure the input voltage to each port will never exceed VCC. VCC: VCC1 for ports P6 to P11 and P14, and VCC2 for ports P0 to P5, P12 and P13. (128-pin and 100-pin packages) VCC1 (80-pin package) Figure 13.1 I/O Ports (1/9) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 194 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports Pull-up selection Direction register 1 P1_1 to P1_3 PCR0 bit output Data bus Port latch (Note 1) CMOS output/ Nch open-drain output selection Input to respective peripheral functions Pull-up selection Direction register P1_4 (dotted section not included) P1_5 to P1_7 (dotted section included) PCR0 bit Data bus Port latch (Note 1) Input to respective peripheral functions Note: 1. Symbolizes a parasitic diode. Make sure the input voltage to each port will never exceed VCC. VCC: VCC1 for ports P6 to P11 and P14, and VCC2 for ports P0 to P5, P12 and P13. (128-pin and 100-pin packages) VCC1 (80-pin package). Figure 13.2 I/O Ports (2/9) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 195 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports Pull-up selection P2_4, P2_5 P10_4 to P10_7 Direction register Data bus Port latch (Note 1) Analog input Input to respective peripheral functions PCR register (Bits PCR5, PCR6, PCR7) Pull-up selection Direction register 1 P4_4, P6_0, P6_4, P7_3 to P7_5, P8_1, P9_0, P9_2 output Data bus Port latch (Note 1) Input to respective peripheral functions Note: 1. Symbolizes a parasitic diode. Make sure the input voltage to each port will never exceed VCC. VCC: VCC1 for ports P6 to P10, and VCC2 for ports P0 to P5. Figure 13.3 I/O Ports (3/9) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 196 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports Pull-up selection Direction register 1 P5_7 output Data bus Port latch (Note 1) RDY input Pull-up selection Direction register 1 P4_5, P6_1 to P6_3, P6_5 to P6_7, P7_2, P7_6 to P7_7, P8_0 Data bus output Port latch (Note 1) CMOS output/ Nch open-drain output selection Input to respective peripheral functions Note: 1. Symbolizes a parasitic diode. Make sure the input voltage to each port will never exceed VCC. VCC: VCC1 for ports P6 to P10, and VCC2 for ports P0 to P5. Figure 13.4 I/O Ports (4/9) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 197 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports Pull-up selection Direction register 1 P4_6, P4_7 PWM output output Data bus Port latch (Note 1) CMOS output/ Nch open-drain output selection Input to respective peripheral functions Pull-up selection P5_5 Direction register Data bus Port latch (Note 1) HOLD input Note: 1. Symbolizes a parasitic diode. Make sure the input voltage to each port will never exceed VCC. VCC: VCC1 for ports P6 to P10, and VCC2 for ports P0 to P5. Figure 13.5 I/O Ports (5/9) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 198 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports Pull-up selection Direction register P8_2 to P8_4, P9_1, P9_7 Data bus Port latch (Note 1) P7_0, P7_1 Input to respective peripheral functions Direction register 1 output Data bus Port latch (Note 1) Input to respective peripheral functions Note: 1. Symbolizes a parasitic diode. Make sure the input voltage to each port will never exceed VCC. VCC: VCC1 for ports P6 to P11 and P14, and VCC2 for ports P0 to P5, P12 and P13. (128-pin and 100-pin packages) VCC1 (80-pin package) Figure 13.6 I/O Ports (6/9) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 199 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports PM24 bit (NMI enabled) Direction register P8_5 CEC output Data bus Port latch (Note 1) SD/CEC input NMI interrupt input Digital filter PM24 bit (NMI enabled) Pull-up selection Bits DA0E and DA1E (D/A output enabled) Direction register P9_3, P9_4 PWM output Data bus Port latch (Note 1) Input to respective peripheral functions Analog input Bits DA0E and DA1E (D/A output enabled) Note: 1. Symbolizes a parasitic diode. Make sure the input voltage to each port will never exceed VCC. VCC: VCC1 for ports P6 to P11 and P14, and VCC2 for ports P0 to P5, P12 and P13. (128-pin and 100-pin packages) VCC1 (80-pin package) Figure 13.7 I/O Ports (7/9) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 200 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports Pull-up selection Direction register 1 P9_5 (dotted section included) P9_6 (dotted section not included) output Data bus Port latch (Note 1) Input to respective peripheral functions Analog input Note: 1. Symbolizes a parasitic diode. Make sure the input voltage to each port will never exceed VCC. VCC: VCC1 for ports P6 to P11 and P14, and VCC2 for ports P0 to P5, P12 and P13. (128-pin and 100-pin packages) VCC1 (80-pin package) Figure 13.8 I/O Ports (8/9) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 201 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports Pull-up selection CM04 bit Direction register P8_7 Data bus Port latch (Note 1) fC CM04 bit Pull-up selection CM04 bit Direction register Rf Oscillation circuit (under review) P8_6 Rd CM04 bit (XCIN-XCOUT) Data bus Port latch (Note 1) Note: 1. Symbolizes a parasitic diode. Make sure the input voltage to each port will never exceed VCC. VCC: VCC1 for ports P6 to P11 and P14, and VCC2 for ports P0 to P5, P12 and P13. (128-pin and 100-pin packages) VCC1 (80-pin package) Figure 13.9 I/O Ports (9/9) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 202 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports BYTE BYTE signal input (Note 1) Internal signal CNVSS CNVSS signal input (Note 1) RESET RESET signal input (Note 1) Note: 1. Symbolizes a parasitic diode. Make sure the input voltage to each port will never exceed VCC1. Figure 13.10 I/O Pins REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 203 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports 13.3 Registers Register Structure Table 13.3 Address 0360h 0361h 0362h 0363h 0366h 0369h 03E0h 03E1h 03E2h 03E3h 03E4h 03E5h 03E6h 03E7h 03E8h 03E9h 03EAh 03EBh 03ECh 03EDh 03EEh 03EFh 03F0h 03F1h 03F2h 03F3h 03F4h 03F5h 03F6h 03F7h 03F8h 03F9h 03FAh 03FBh 03FCh 03FEh Note: 1. Register Name Pull-Up Control Register 0 Pull-Up Control Register 1 Pull-Up Control Register 2 Pull-Up Control Register 3 Port Control Register NMI/SD Digital Filter Register Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register Port P11 Register Port P10 Direction Register Port P11 Direction Register Port P12 Register Port P13 Register Port P12 Direction Register Port P13 Direction Register Port P14 Register Port P14 Direction Register Register Symbol After Reset PUR0 00h PUR1 0000 0000b (1) 0000 0010b PUR2 00h PUR3 00h PCR 0000 0XX0b NMIDF XXXX X000b P0 XXh P1 XXh PD0 00h PD1 00h P2 XXh P3 XXh PD2 00h PD3 00h P4 XXh P5 XXh PD4 00h PD5 00h P6 XXh P7 XXh PD6 00h PD7 00h P8 XXh P9 XXh PD8 00h PD9 00h P10 XXh P11 XXh PD10 00h PD11 00h P12 XXh P13 XXh PD12 00h PD13 00h P14 XXh PD14 XXXX XX00b Values after hardware reset, power-on reset, or voltage monitor 0 reset are as follows: • 00000000b when input on the CNVSS pin is low • 00000010b when input on the CNVSS pin is high Values after voltage monitor 1 reset, voltage monitor 2 reset, software reset, watchdog timer reset, or oscillation stop detection reset are as follows: • 00000000b when bits PM01 to PM00 in the PM0 register are 00b (single-chip mode). • 00000010b when bits PM01 to PM00 in the PM0 register are 01b (memory expansion mode) or 11b (microprocessor mode). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 204 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports 13.3.1 Pull-Up Control Register 0 (PUR0) Pull-Up Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR0 Bit Symbol PU00 PU01 PU02 PU03 PU04 PU05 PU06 PU07 Bit Name P0_0 to P0_3 pull-up P0_4 to P0_7 pull-up P1_0 to P1_3 pull-up P1_4 to P1_7 pull-up P2_0 to P2_3 pull-up P2_4 to P2_7 pull-up P3_0 to P3_3 pull-up P3_4 to P3_7 pull-up Address 0360h Function 0 : Not pulled high 1 : Pulled high After Reset 00h RW RW RW RW RW RW RW RW RW In memory expansion or microprocessor mode, the corresponding register contents can be modified, but the pins are not pulled high. PU0i Bit (b7-b0) (i = 0 to 7) The pin for which the PU0i bit is 1 (pulled high) and the direction bit is 0 (input mode) is pulled high. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 205 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports 13.3.2 Pull-Up Control Register 1 (PUR1) Pull-Up Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR1 Bit Symbol PU10 PU11 PU12 PU13 PU14 PU15 PU16 PU17 Bit Name P4_0 to P4_3 pull-up P4_4 to P4_7 pull-up P5_0 to P5_3 pull-up P5_4 to P5_7 pull-up P6_0 to P6_3 pull-up P6_4 to P6_7 pull-up P7_2 to P7_3 pull-up P7_4 to P7_7 pull-up Address 0361h Function 0 : Not pulled high 1 : Pulled high After Reset 0000 0000b 0000 0010b RW RW RW RW RW RW RW RW RW Values after hardware reset, power-on reset, or voltage monitor 0 reset are as follows: • 00000000b when input on the CNVSS pin is low • 00000010b when input on the CNVSS pin is high Values after voltage monitor 1 reset, voltage monitor 2 reset, software reset, watchdog timer reset, ro oscillation stop detection reset are as follows: • 00000000b when bits PM01 to PM00 are 00b (single-chip mode) • 00000010b when bits PM01 to PM00 are 01b (memory expansion mode) or 11b (microprocessor mode) PU10 (P4_0 to P4_3 Pull-Up) (b0) PU11 (P4_4 to P4_7 Pull-Up) (b1) PU12 (P5_0 to P5_3 Pull-Up) (b2) PU13 (P5_4 to P5_7 Pull-Up) (b3) The pin for which the bit in the PU1i bit (i = 0 to 3) is 1 (pulled high) and the direction bit is 0 (input mode) is pulled high. In memory expansion and microprocessor modes, pins are not pulled high although the contents of these bits can be modified. PU14 (P6_0 to P6_3 Pull-Up) (b4) PU15 (P6_4 to P6_7 Pull-Up) (b5) PU17 (P7_4 to P7_7 Pull-Up) (b7) The pin for which the bit in the PU1i bit (i = 4, 5, 7) is 1 (pulled high) and the direction bit is 0 (input mode) is pulled high. PU16 (P7_2 to P7_3 Pull-Up) (b6) The pin for which the bit in the PU16 bit is 1 (pulled high) and the direction bit is 0 (input mode) is pulled high. Pins P7_0 and P7_1 are not pulled high. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 206 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports 13.3.3 Pull-Up Control Register 2 (PUR2) Pull-up Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR2 Bit Symbol PU20 PU21 PU22 PU23 PU24 PU25 — (b7-b6) Bit Name P8_0 to P8_3 pull-up P8_4 to P8_7 pull-up P9_0 to P9_3 pull-up P9_4 to P9_7 pull-up P10_0 to P10_3 pull-up P10_4 to P10_7 pull-up Address 0362h Function 0 : Not pulled high 1 : Pulled high After Reset 00h RW RW RW RW RW RW RW — No register bits. If necessary, set to 0. Read as 0 The pin for which the bit in the PUR2 register is 1 (pulled high) and the direction bit is 0 (input mode) is pulled high. PU21 (P8_4 to P8_7 Pull-Up) (b1) The P8_5 pin is not pulled high. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 207 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports 13.3.4 Pull-Up Control Register 3 (PUR3) Pull-Up Control Register 3 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR3 Bit Symbol PU30 PU31 PU32 PU33 PU34 PU35 PU36 PU37 Bit Name P11_0 to P11_3 pull-up P11_4 to P11_7 pull-up P12_0 to P12_3 pull-up P12_4 to P12_7 pull-up P13_0 to P13_3 pull-up P13_4 to P13_7 pull-up P14_0, P14_1 pull-up P11 to P14 enable bit Address 0363h Function 0 : Not pulled high 1 : Pulled high After Reset 00h RW RW RW RW RW RW RW RW 0 : Disabled 1 : Enabled RW PU3i Bit (b6-b0) (i = 0 to 6) The pin for which the PU3i bit is 1 (pulled high) and the direction bit is 0 (input mode) is pulled high. PU37 (P11 to P14 Enable Bit) (b7) When the PU37 bit is 1 (P11 to P14 enabled), registers P11 to P14 and registers PD0 to PD14 are enabled. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 208 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports 13.3.5 Port Control Register (PCR) Port Control Register b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol PCR Bit Symbol Bit Name Address 0366h Function After Reset 0000 0XX0b RW PCR0 Port P1 control bit Operation performed when the P1 register is read 0 : When the port is set to input, the input levels of pins P1_0 to P1_7 are read. When set to output, the port latch is read. 1 : The port latch is read regardless of whether the port is set to input or output. RW — (b2-b1) — (b3) PCR4 PCR5 PCR6 PCR7 No register bits. If necessary, set to 0. Read as undefined Reserved bit CEC output enable bit INT6 input enable bit INT7 input enable bit Key input enable bit Set to 0 0 : CEC output disabled 1 : CEC output enabled 0 : Enabled 1 : Disabled 0 : Enabled 1 : Disabled 0 : Enabled 1 : Disabled — RW RW RW RW RW PCR0 (Port P1 Control Bit) (b0) When the P1 register is read after the PCR0 bit is set to 1, the corresponding port latch is read regardless of the PD1 register setting. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 209 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports 13.3.6 Port Pi Registers (Pi) (i = 0 to 14) Port Pi Register (i = 0 to 13) b7 b6 b5 b4 b3 b2 b1 b0 Symbol P0 to P3 P4 to P7 P8 to P11 P12 to P13 Bit Symbol Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 Pi_5 Pi_6 Pi_7 Address 03E0h, 03E1h, 03E4h, 03E5h 03E8h, 03E9h, 03ECh, 03EDh 03F0h, 03F1h, 03F4h, 03F5h 03F8h, 03F9h Bit Name Port Pi_0 bit Port Pi_1 bit Port Pi_2 bit Port Pi_3 bit Port Pi_4 bit Port Pi_5 bit Port Pi_6 bit Port Pi_7 bit Function After Reset Undefined Undefined Undefined Undefined RW RW RW RW RW RW RW RW RW The pin level of any I/O port which is set to input mode can be read by reading the corresponding bit in this register. The pin level of any I/O port which is set to output mode can be controlled by writing to the corresponding bit in this register 0 : Low level 1 : High level Port P14 Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol P14 Bit Symbol Bit Name Address 03FCh Function After Reset Undefined RW P14_0 Port P14_0 bit P14_1 Port P14_1 bit The pin level of any I/O port which is set to input mode can be read by reading the corresponding bit in this register. The pin level of any I/O port which is set to output mode can be controlled by writing to the corresponding bit in this register 0 : Low level 1 : High level RW RW — (b7-b2) No register bit. If necessary, set to 0. Read as undefined value — Data input/output to and from external devices are accomplished by reading and writing to the Pi register. Each bit of the Pi register consists of a port latch to hold the output data and a circuit to read the pin status. For ports set to input mode, the input level of the pin can be read by reading the corresponding Pi register, and data can be written to the port latch by writing to the Pi register. For ports set to output mode, the port latch can be read by reading the corresponding Pi register, and data can be written to the port latch by writing to the Pi register. The data written to the port latch is output from the pin. Each bit in the Pi register corresponds to one port. In memory expansion and microprocessor modes, the Pi register for the pins functioning as bus control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and BCLK) cannot be modified (writing a value has no effect). Since P7_0, P7_1, and P8_5 are N-channel open- drain ports, when set to 1, the pin status becomes high-impedance. When the CM04 bit in the CM0 register is 1 (XCIN-XCOUT oscillation function) and bits PD8_6 and PD8_7 in the PD8 register are 0 (input mode), values of bits P8_6 and P8_7 in the P8 register are undefined. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 210 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports Registers P11 to P14 are enabled when the PU37 bit in the PUR3 register is 1 (P11 to P14 enabled). Access to registers P11 to P14 after setting the PU37 bit to 1. When the PU37 bit in the PUR3 register is 0 (P11 to P14 disabled), the contents of registers P11 to P14 are retained. In this case, read as undefined value. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 211 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports 13.3.7 Port Pi Direction Registers (PDi) (i = 0 to 14) Port Pi Direction Register (i = 0 to 13) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PD0 to PD3 PD4 to PD7 PD8 to PD11 PD12 to PD13 Bit Symbol PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7 Address 03E2h, 03E3h, 03E6h, 03E7h 03EAh, 03EBh, 03EEh, 03EFh 03F2h, 03F3h, 03F6h, 03F7h 03FAh, 03FBh Bit Name Port Pi_0 direction bit Port Pi_1 direction bit Port Pi_2 direction bit Port Pi_3 direction bit Port Pi_4 direction bit Port Pi_5 direction bit Port Pi_6 direction bit Port Pi_7 direction bit Function 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) After Reset 00h 00h 00h 00h RW RW RW RW RW RW RW RW RW Port P14 Direction Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PD14 Bit Symbol PD14_0 PD14_1 — (b7-b2) Bit Name Port P14_0 direction bit Port P14_1 direction bit Address 03FEh Function 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) After Reset XXXX XX00b RW RW RW — No register bit. If necessary, set to 0. Read as undefined value Write to the PD9 register in the next instruction after setting the PRC2 bit in the PRCR register to 1 (write enabled). These registers select whether I/O ports are to be used for input or output. Each bit in the PDi register has its corresponding port. In memory expansion mode or microprocessor mode, the PDi register for the pins functioning as bus control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and BCLK) cannot be modified (Writing a value has no effect). Registers PD11 to PD14 are enabled when the PU37 bit in the PUR3 register is 1 (P11 to P14 enabled). Access to registers PD11 to PD14 after setting the PU37 bit to 1. When the PU37 bit in the PUR3 register is 0 (P11 to P14 disabled), the contents of registers PD11 to PD14 are retained. In this case, read as undefined value. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 212 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports 13.3.8 NMI/SD Digital Filter Register (NMIDF) NMI/SD Digital Filter Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol NMIDF Bit Symbol NMIDF0 NMI/SD filter sampling clock select bit Bit Name Address 0369h Function b2 b1 b0 After Reset XXXX X000b RW RW NMIDF1 NMIDF2 — (b7-b3) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : No filter 1 : CPU clock divided by 2 0 : CPU clock divided by 4 1 : CPU clock divided by 8 0 : CPU clock divided by 16 1 : CPU clock divided by 32 0 : CPU clock divided by 64 1 : CPU clock divided by 128 RW RW No register bits. If necessary, set to 0. Read as undefined value — REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 213 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports 13.4 13.4.1 Peripheral Function I/O Peripheral Function I/O and Port Direction Bits Programmable I/O ports can share pins with peripheral function I/O. (See to Table 1.11 to Table 1.12 “Pin Names, Pin Package”.) Some peripheral function I/O are affected by a port direction bit which shares the same pin. Table 13.4 lists The Setting of Direction Bits Functioning as Peripheral Function I/ O. For peripheral function settings, see descriptions of each function. Table 13.4 The Setting of Direction Bits Functioning as Peripheral Function I/O Peripheral Function I/O Input Output PWM D/A converter Others The Setting of the Port Direction Bit Sharing the Same Pin Set to 0 (input mode). Set to 1 (output mode). Set to 0 (input mode). Set to either 0 or 1. (Outputs regardless of the direction bit setting) 13.4.2 Priority Level of Peripheral Function I/O Multiple peripheral functions can share the same pin. For example, when peripheral function A and peripheral function B share a pin, input and output are as follows: • When the pin functions as input for peripheral functions A and B The same signal is input as each input signal. However, the timing of accepting the signal differs depending on conditions (e.g. internal delay) of functions A and B. • When the pin functions as output for peripheral function A and as input for peripheral function B Peripheral function A outputs a signal from the pin, and peripheral function B inputs the signal. • When the pin functions as output for peripheral functions A and B Peripheral function with higher priority is output. Table 13.5 lists Priority Level of Peripheral Function Output. Table 13.5 Priority Level of Peripheral Function Output Priority Level High PWM Function Multi-master I2C-bus interface Serial interface UART0 to UART2, UART5 to UART7, SI/O3, SI/O4 CEC Timer timer A, three-phase control timer function SCLMM, SDAMM PWM0, PWM1 Output Pin RTSi, CLKi, TXDi, SCLi, SDAi (i = 0 to 2, 5 to 7), CLK3, SOUT3, CLK4, SOUT4 CEC TA0OUT, TA1OUT, TA2OUT, TA3OUT, TA4OUT U, V, W, U, V, W RTCOUT DA0, DA1 Low Real-time clock D/A converter REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 214 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports 13.4.3 NMI/SD Digital Filter The NMI/SD input circuit includes a digital filter. Sampling clock can be selected by bits NMIDF2 to NMIDF0 in the NMIDF register. The NMI level is sampled for every sampling clock. When the same sampled level is detected three times in a row, the level is transferred to the internal circuit. When using the NMI/SD digital filter, do not enter wait mode or stop mode. Port P8_5 is not affected by the digital filter. When using the CEC function, set bits NMIDF2 to NMIDF0 to 000b (NMI/SD digital filter disabled). Figure 13.11 shows NMI/SD Digital Filter, and Figure 13.12 shows NMI/SD Digital Filter Operation Example. NMIDF2 to NMIDF0 CPU clock Divider Sampling clock PM24 NMIDF2 to NMIDF0 Other than 000b P8_5/NMI/SD/CEC Digital Filter 000b SD input CEC input P8_5 input PM24: Bit in the PM2 register NMIDF2 to NMIDF0: Bits in the NMIDF register NMI interrupt Figure 13.11 NMI/SD Digital Filter Sampling timing NMI/SD pin 3 levels agreed NMI/SD input NMI interrupt is generated when the PM 24 bit in the PM2 register is 1 (NMI interrupt enabled). Note that the above applies when bits NMIDF2 to NMIDF0 in the NMIDF register are set to a value other than 000b (NMI/SD filter enabled). Figure 13.12 NMI/SD Digital Filter Operation Example 13.4.4 CNVSS The built-in pull-up resistor of the CNVSS pin is activated after watchdog timer reset, hardware reset, power-on reset or voltage monitor 0 reset. Thus, the CNVSS pin outputs a high-level signal up to two cycles of the fOCO-S. Connect the CNVSS pin to VSS via a resistor to use it in single-chip mode. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 215 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports 13.5 Unassigned Pin Handling Unassigned Pin Handling in Single-Chip Mode Table 13.6 Pin Name Connection (2) Ports P0 to P5, P12, One of the following: P13 • Set to input mode and connect a pin to VSS via a resistor (pull-down) • Set to input mode and connect a pin to VCC2 via a resistor (pull-up) (5) • Set to output mode and leave the pins open (1) Ports P6 to P11, P14 One of the following: • Set to input mode and connect a pin to VSS via a resistor (pull-down) • Set to input mode and connect a pin to VCC1 via a resistor (pull-up) • Set to output mode and leave the pins open (1), (3) Open XOUT (4) XIN AVCC AVSS, VREF, BYTE Notes: 1. Connect to VCC1 via a resistor (pull-up) Connect to VCC1 Connect to VSS 2. 3. 4. 5. When setting a port to output mode and leaving it open, be aware that the port remains in input mode until it is switched to output mode by a program after reset. For this reason, the voltage level on the pin becomes undefined, causing the power supply current to increase while the port remains in input mode. Furthermore, since the contents of the direction registers could be changed by noise or noise-induced loss of control, it is recommended that the contents of the direction registers be regularly reset in software to improve the reliability of the program. Make sure the unassigned pins are connected with the shortest possible wiring from the MCU pins (maximum 2 cm). Ports P7_0, P7_1 and P8_5 are N-channel open-drain outputs. When ports P7_0, P7_1 and P8_5 are set to output mode, make sure a low-level signal is output from the pins. This applies when an external clock is input to the XIN pin or when VCC1 is connected via a resistor. In 80-package, a port is set to input mode and is connected to VCC1 via a resistor (pull-up). MCU Ports P0 to P14 (Input mode) . . . . . . (Input mode) (Output mode) Open VCC1 XIN XOUT Open VCC1 AVCC BYTE AVSS VREF VSS Single-chip mode Figure 13.13 Unassigned Pin Handling in Single-Chip Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 216 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports Table 13.7 Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode Connection (2) One of the following: • Set to input mode and connect a pin to VSS via a resistor (pull-down) • Set to input mode and connect a pin to VCC2 via a resistor (pull-up) • Set to output mode and leave the pins open (1), (3) One of the following: • Set to input mode and connect a pin to VSS via a resistor (pull-down) • Set to input mode and connect a pin to VCC1 via a resistor (pull-up) • Set to output mode and leave the pins open (1), (4) Open Connect to VCC2 via a resistor (pull-up) Connect to VCC1 via a resistor (pull-up) Connect to VCC1 Connect to VSS Pin Name Ports P0 to P5, P12, P13 Ports P6 to P11, P14 BHE, ALE, HLDA, XOUT (5), BCLK (6) HOLD , RDY XIN AVCC AVSS, VREF Notes: 1. 2. 3. 4. 5. 6. When setting a port to output mode and leaving it open, be aware that the port remains in input mode until it is switched to output mode by a program after reset. For this reason, the voltage level on the pin becomes undefined, causing the power supply current to increase while the port remains in input mode. Furthermore, since the contents of the direction registers could be changed by noise or noise-induced loss of control, it is recommended that the contents of the direction registers be regularly reset in software to improve the reliability of the program. Make sure the unassigned pins are connected with the shortest possible wiring from the MCU pins (maximum 2 cm). If the CNVSS pin has the VSS level applied to it, these pins are set as input ports until the processor mode is switched by a program after reset. For this reason, the voltage levels on these pins become undefined, causing the power supply current to increase while they remain set as input ports. Ports P7_0, P7_1, and P8_5 are N-channel open-drain outputs. When ports P7_0, P7_1, and P8_5 are set to output mode, make sure a low-level signal is output from the pins. This applies when an external clock is input to the XIN pin or when VCC1 is connected via a resistor. If the PM07 bit in the PM0 register is set to 1 (BCLK not output), connect this pin to VCC2 via a resistor (pulled high). MCU Ports P6 to P14 (Input mode) . . . . . . (Input mode) (Output mode) XIN BHE HLDA ALE XOUT BCLK HOLD RDY AVCC AVSS VREF Open VCC1 Open VCC2 VCC1 VSS Memory expansion mode or microprocessor mode Figure 13.14 Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 217 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 13. Programmable I/O Ports 13.6 13.6.1 Notes on Programmable I/O Ports Influence of the SD Input If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is 1 (threephase output forcible cutoff by input on the SD pin enabled), pins P7_2 to P7_5 and P8_0 and P8_1 go to the high-impedance state. 13.6.2 Influence of SI/O3 and SI/O4 Setting the SM32 bit in the S3C register to 1 causes the P9_2 pin to go to the high-impedance state. Similarly, setting the SM42 bit in the S4C register to 1 causes the P9_6 pin to go to the high-impedance state. 13.6.3 100-Pin Package Do not access to the addresses assigned to registers P11 to P14 and the PUR register. 13.6.4 80-Pin Package Do not access to the addresses assigned to registers P11 to P14 and the PUR register. Set the direction bits of the ports corresponding to P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 to 1 (output mode). Set the output data to 0 (low-level signal). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 218 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14. Interrupts Note Do not use INT3 to INT5 for the 80-pin package. 14.1 Introduction Table 14.1 lists Types of Interrupt, and Table 14.2 lists I/O Pins. The pins shown in Table 14.2 are external interrupt input pins. Refer to the peripheral functions for the pins related to the peripheral functions. Table 14.1 Types of Interrupt Type Software Interrupt Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Function An interrupt is generated by executing an instruction. Non-maskable interrupt (2) Hardware Specific NMI Interrupt by the MCU hardware Watchdog timer Non-maskable interrupt (2) Oscillation stop and re-oscillation detection Voltage monitor 1 Voltage monitor 2 Address match Single step (1) DBC (1) Peripheral INT, timers, etc. Interrupt by the peripheral functions in the MCU function (See 14.6.2 “Relocatable Vector Maskable interrupt Tables”.) (interrupt priority level: 7 levels) (2) Notes: 1. This interrupt is provided exclusively for developers and should not be used. 2. Maskable interrupt: Interrupt status (enabled or disabled) can be selected by the interrupt enable flag (I flag). Interrupt priority can be changed by the interrupt priority level. Non-maskable interrupt: Interrupt status (enabled or disabled) cannot be selected by the interrupt enable flag (I flag). Interrupt priority cannot be changed by the interrupt priority level. Table 14.2 NMI INTi KI0 to KI3 I/O Pins Pin Name I/O Type I I (1) I (1) NMI interrupt input INTi interrupt input Function Key input i = 0 to 7 Note: 1. Set the port direction bits which share pins to 0 (input mode). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 219 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.2 Registers Register Structure (1/2) Table 14.3 Address 001Eh 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0069h 006Ah 006Bh 006Ch 006Dh Register Name Processor Mode Register 2 INT7 Interrupt Control Register INT6 Interrupt Control Register INT3 Interrupt Control Register Timer B5 Interrupt Control Register Timer B4 Interrupt Control Register UART1 Bus Collision Detection Interrupt Control Register Timer B3 Interrupt Control Register, UART0 Bus Collision Detection Interrupt Control Register SI/O4 Interrupt Control Register, INT5 Interrupt Control Register SI/O3 Interrupt Control Register, INT4 Interrupt Control Register UART2 Bus Collision Detection Interrupt Control Register DMA0 Interrupt Control Register DMA1 Interrupt Control Register Key Input Interrupt Control Register A/D Conversion Interrupt Control Register UART2 Transmit Interrupt Control Register UART2 Receive Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Transmit Interrupt Control Register Timer A0 Interrupt Control Register Timer A1 Interrupt Control Register Timer A2 Interrupt Control Register Timer A3 Interrupt Control Register Timer A4 Interrupt Control Register Timer B0 Interrupt Control Register Timer B1 Interrupt Control Register Timer B2 Interrupt Control Register INT0 Interrupt Control Register INT1 Interrupt Control Register INT2 Interrupt Control Register DMA2 Interrupt Control Register DMA3 Interrupt Control Register UART5 Bus Collision Detection Interrupt Control Register CEC1 Interrupt Control Register UART5 Transmit Interrupt Control Register CEC2 Interrupt Control Register UART5 Receive Interrupt Control Register Register Symbol PM2 INT7IC INT6IC INT3IC TB5IC TB4IC, U1BCNIC TB3IC, U0BCNIC S4IC, INT5IC S3IC, INT4IC BCNIC DM0IC DM1IC KUPIC ADIC S2TIC S2RIC S0TIC S0RIC S1TIC S1TIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC TB2IC INT0IC INT1IC INT2IC DM2IC DM3IC U5BCNIC, CEC1IC S5TIC, CEC2IC S5RIC After Reset XX00 0X01b XX00 X000b XX00 X000b XX00 X000b XXXX X000b XXXX X000b XXXX X000b XX00 X000b XX00 X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XX00 X000b XX00 X000b XX00 X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 220 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts Table 14.4 Register Structure (2/2) Address 006Eh 006Fh 0070h 0071h 0072h 0073h 007Bh 007Ch 0205h 0206h 0207h 020Eh 020Fh 0210h 0211h 0212h 0214h 0215h 0216h 0218h 0219h 021Ah 021Ch 021Dh 021Eh 0366h 0369h Register Name UART6 Bus Collision Detection Interrupt Control Register, Real-Time Clock Period Interrupt Control Register UART6 Transmit Interrupt Control Register, Real-Time Clock Compare Match Interrupt Control Register UART6 Receive Interrupt Control Register UART7 Bus Collision Detection Interrupt Control Register, Remote Control Signal Receiver 0 Interrupt Control Register UART7 Transmit Interrupt Control Register, Remote Control Signal Receiver 1 Interrupt Control Register UART7 Receive Interrupt Control Register IICBus Interface Interrupt Control Register SCL/SDA Interrupt Control Register Interrupt Source Select Register 3 Interrupt Source Select Register 2 Interrupt Source Select Register Address Match Interrupt Enable Register Address Match Interrupt Enable Register 2 Address Match Interrupt Register 0 Register Symbol After Reset U6BCNIC, XXXX X000b RTCTIC S6TIC, RTCCIC S6RIC U7BCNIC, PMC0IC S7TIC, PMC1IC S7RIC IICIC SCLDAIC IFSR3A IFSR2A IFSR AIER AIER2 RMAD0 XXXX X000b XXXX X000b XXXX X000b XXXX X000b Address Match Interrupt Register 1 RMAD1 Address Match Interrupt Register 2 RMAD2 Address Match Interrupt Register 3 RMAD3 Port Control Register NMI/SD Digital Filter Register PCR NMIDF XXXX X000b XXXX X000b XXXX X000b 00h 00h 00h XXXX XX00b XXXX XX00b 00h 00h X0h 00h 00h X0h 00h 00h X0h 00h 00h X0h 0000 0XX0b XXXX X000b REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 221 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.2.1 Processor Mode Register 2 (PM2) Processor Mode Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol PM2 Bit Symbol PM20 Bit Name Address 001Eh Function After Reset XX00 0X01b RW RW Specifying wait when accessing 0 : 2 waits SFR at PLL operation 1 : 1 wait System clock protection bit 0 : Clock is protected by PRCR register 1 : Clock change disabled PM21 — (b2) — (b3) PM24 RW No register bit. If necessary, set to 0. Read as 0 — Reserved bit Set to 0 0 : NMI interrupt disabled 1 : NMI interrupt enabled 0 : Provided 1 : Not provide RW NMI interrupt enable bit RW PM25 — (b7-b6) Peripheral clock fC provide bit RW No register bits. If necessary, set to 0. Read as undefined value — Set the PRC1 bit in the PRCR register to 1 (write enabled) before the PM2 register is rewritten. PM24 (NMI Interrupt Enable Bit) (b4) Once this bit is set to 1, it cannot be set to 0 by a program (writing a 0 has no effect). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 222 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.2.2 Interrupt Control Register 1 (TB5IC, TB4IC/U1BCNIC, TB3IC/U0BCNIC, BCNIC, DM0IC to DM3IC, KUPIC, ADIC, S0TIC to S2TIC, S0RIC to S2RIC, TA0IC to TA4IC, TB0IC to TB2IC, U5BCNIC/CEC1IC, S5TIC/CEC2IC, S5RIC to S7RIC, U6BCNIC/RTCTIC, S6TIC/RTCCIC, U7BCNIC/PMC0IC, S7TIC/PMC1IC, IICIC, SCLDAIC) Interrupt Control Register 1 Symbol b7 b6 b5 b4 b3 b2 b1 b0 Address 0045h 0046h 0047h 004Ah 004Bh, 004Ch, 0069h, 006Ah 004Dh 004Eh 0051h, 0053h, 004Fh 0052h, 0054h, 0050h 0055h to 0059h 005Ah to 005Ch 006Bh 006Ch 006Dh, 0070h, 0073h 006Eh 006Fh 0071h 0072h 007Bh 007Ch Function b2 b1 b0 After Reset XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b RW RW TB5IC TB4IC/U1BCNIC TB3IC/U0BCNIC BCNIC DM0IC to DM3IC KUPIC ADIC S0TIC to S2TIC S0RIC to S2RIC TA0IC to TA4IC TB0IC to TB2IC U5BCNIC/CEC1IC S5TIC/CEC2IC S5RIC to S7RIC U6BCNIC/RTCTIC S6TIC/RTCCIC U7BCNIC/PMC0IC S7TIC/PMC1IC IICIC SCLDAIC Bit Symbol ILVL0 Bit Name ILVL1 Interrupt priority level select bit ILVL2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : Level 0 (interrupt disabled) 1 : Level 1 0 : Level 2 1 : Level 3 0 : Level 4 1 : Level 5 0 : Level 6 1 : Level 7 RW RW IR — (b7-b4) Interrupt request bit 0: Interrupt not requested 1: Interrupt requested RW No register bits. If necessary, set to 0. Read as undefined value — Rewrite this register at a point that does not generate an interrupt request. When multiple interrupt sources share the register, select an interrupt source in registers IFSR2A and IFSR3A. IR (Interrupt Request Bit) (b3) The IR bit can only be set to 0 (do not write 1). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 223 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.2.3 Interrupt Control Register 2 (INT7IC, INT6IC, INT3IC, S4IC/INT5IC, S3IC/INT4IC, INT0IC to INT2IC) Interrupt Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol INT7IC INT6IC INT3IC S4IC/INT5IC S3IC/INT4IC INT0IC to INT2IC Bit Symbol ILVL0 Bit Name Address 0042h 0043h 0044h 0048h 0049h 005Dh to 005Fh Function b2 b1 b0 After Reset XX00 X000b XX00 X000b XX00 X000b XX00 X000b XX00 X000b XX00 X000b RW RW ILVL1 Interrupt priority level select bit ILVL2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : Level 0 (interrupt disabled) 1 : Level 1 0 : Level 2 1 : Level 3 0 : Level 4 1 : Level 5 0 : Level 6 1 : Level 7 RW RW IR Interrupt request bit 0: Interrupt not requested 1: Interrupt requested 0 : Select falling edge 1 : Select rising edge Set to 0 RW (1) POL — (b5) — (b7-b6) Polarity select bit RW Reserved bit RW No register bits. If necessary, set to 0. Read as undefined value — Rewrite this register at a point that does not generate an interrupt request. When multiple interrupt sources share the register, select an interrupt source in the IFSR register. ILVL2-ILVL0 (Interrupt Priority Level Select Bit) (b2-b0) In memory expansion or microprocessor mode, set bits ILVL2 to ILVL0 in registers INT6IC and INT7IC to 000b (interrupts disabled). When the BYTE pin is low in memory expansion or microprocessor mode, set bits ILVL2 to ILVL0 in registers INT3IC, INT4IC, and INT5IC to 000b (interrupts disabled). IR (Interrupt Request Bit) (b3) The IR bit can only be set to 0 (do not write 1). POL (Polarity Select Bit) (b4) When the IFSRi bit in the IFSR register is 1 (both edges), set the POL bit in the INTiIC register to 0 (falling edge) (i = 0 to 5). Similarly, when bits IFSR30 and IFSR31 in the IFSR3A register are 1 (both edges), set the POL bit in registers INT6IC and INT7IC to 0 (falling edge). Set the POL bit in the S3IC or S4IC register to 0 (falling edge) when the IFSR6 bit in the IFSR register is 0 (SI/O3 selected) or IFSR7 bit is 0 (SI/O4 selected), respectively. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 224 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.2.4 Interrupt Source Select Register 3 (IFSR3A) Interrupt Source Select Register 3 b7 b6 b5 b4 b3 b2 b1 b0 0 000 Symbol IFSR3A Bit Symbol IFSR30 Bit Name Address 0205h Function 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges Set to 0 After Reset 00h RW RW INT6 interrupt polarity select bit INT7 interrupt polarity select bit Reserved bit Interrupt request source select bit IFSR31 — (b2) IFSR33 RW RW 0 : UART5 start/stop condition detection, bus collision detection 1 : CEC1 RW IFSR34 Interrupt request source select 0 : UART5 transmission, NACK bit 1 : CEC2 Interrupt request source select bit 0 : UART6 start/stop condition detection, bus collision detection 1 : Real-time clock cycle RW IFSR35 RW IFSR36 — (b7) Interrupt request source select 0 : UART6 transmission, NACK bit 1 : Real-time clock compare match Reserved bit Set to 0 RW RW IFSR30 (INT6 Interrupt Polarity Select Bit) (b0) When setting this bit to 1 (both edges), make sure the POL bit in the INT6IC register is set to 0 (falling edge). IFSR31 (INT7 Interrupt Polarity Select Bit) (b1) When setting this bit to 1 (both edges), make sure the POL bit in the INT7IC register is set to 0 (falling edge). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 225 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.2.5 Interrupt Source Select Register 2 (IFSR2A) Interrupt Source Select Register 2 b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol IFSR2A Bit Symbol — (b1-b0) IFSR22 Bit Name Reserved bits Address 0206h Function Set to 0 After Reset 00h RW RW Interrupt request source select 0 : Not used bit 1 : I2C bus interface Interrupt request source select 0 : Not used bit 1 : SCL/SDA Interrupt request source select bit 0 : UART7 start/stop condition detection, bus collision detection 1 : Remote control 0 RW IFSR23 RW IFSR24 RW IFSR25 Interrupt request source select 0 : UART7 transmission, NACK bit 1 : Remote control 1 0 : Timer B3 Interrupt request source select 1 : UART0 start/stop condition detection, bit bus collision detection 0 : Timer B4 Interrupt request source select 1 : UART1 start/stop condition detection, bit bus collision detection RW IFSR26 RW IFSR27 RW REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 226 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.2.6 Interrupt Source Select Register (IFSR) Interrupt Source Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol IFSR Bit Symbol IFSR0 Bit Name Address 0207h Function After Reset 00h RW RW INT0 interrupt polarity select 0 : One edge bit 1 : Both edges INT1 interrupt polarity select 0 : One edge bit 1 : Both edges INT2 interrupt polarity select 0 : One edge bit 1 : Both edges INT3 interrupt polarity select 0 : One edge bit 1 : Both edges INT4 interrupt polarity select 0 : One edge bit 1 : Both edges INT5 interrupt polarity select 0 : One edge bit 1 : Both edges Interrupt request source select bit Interrupt request source select bit 0 : SI/O3 1 : INT4 0 : SI/O4 1 : INT5 IFSR1 RW IFSR2 RW IFSR3 RW IFSR4 RW IFSR5 RW IFSR6 RW IFSR7 RW IFSR5-IFSR0 (INT5-INT0 Interrupt Polarity Select Bit) (b5-b0) When setting this bit to 1 (both edges), make sure the POL bit in registers INT0IC to INT5IC are set to 0 (falling edge). IFSR7, IFSR6 (Interrupt Request Source Select Bit) (b7, b6) In memory expansion or microprocessor mode, when the data bus is 16 bits wide (BYTE pin is low), set this bit to 0 (SI/O3, SI/O4). When setting this bit to 0 (SI/O3, SI/O4), make sure the POL bit in registers S3IC and S4IC are set to 0 (falling edge). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 227 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.2.7 Address Match Interrupt Enable Register (AIER) Address Match Interrupt Enable Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER Bit Symbol AIER0 Bit Name Address 020Eh Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After Reset XXXX XX00b RW RW Address match interrupt 0 enable bit Address match interrupt 1 enable bit AIER1 — (b7-b2) RW No register bits. If necessary, set to 0. Read as undefined value — 14.2.8 Address Match Interrupt Enable Register 2 (AIER2) Address Match Interrupt Enable Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER2 Bit Symbol AIER20 Bit Name Address 020Fh Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After Reset XXXX XX00b RW RW Address match interrupt 2 enable bit Address match interrupt 3 enable bit AIER21 — (b7-b2) RW No register bits. If necessary, set to 0. Read as undefined value — REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 228 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.2.9 Address Match Interrupt Register i (RMADi) (i = 0 to 3) Address Match Interrupt Register i (i = 0 to 3) (b23) b7 (b19) b3 (b16) (b15) b0 b7 (b8) b0 b7 b0 Symbol RMAD0 RMAD1 RMAD2 RMAD3 Function Address 0212h to 0210h 0216h to 0214h 021Ah to 0218h 021Eh to 021Ch After Reset X0 0000h X0 0000h X0 0000h X0 0000h Setting Range 00000h to FFFFFh RW RW Address setting register for address match interrupt (b19 to b0) No register bits. If necessary, set to 0. Read as undefined value — REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 229 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.2.10 Port Control Register (PCR) Port Control Register b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol PCR Bit Symbol Bit Name Address 0366h Function After Reset 0000 0XX0b RW PCR0 Port P1 control bit Operation performed when the P1 register is read 0 : When the port is set to input, the input levels of pins P1_0 to P1_7 are read. When set to output, the port latch is read. 1 : The port latch is read regardless of whether the port is set to input or output. RW — (b2-b1) — (b3) PCR4 PCR5 PCR6 PCR7 No register bits. If necessary, set to 0. Read as undefined Reserved bit CEC output enable bit INT6 input enable bit INT7 input enable bit Key input enable bit Set to 0 0 : CEC output disabled 1 : CEC output enabled 0 : Enabled 1 : Disabled 0 : Enabled 1 : Disabled 0 : Enabled 1 : Disabled — RW RW RW RW RW INT6 Input Enable Bit (PCR5) (b5) To use the AN2_4 pin as an analog input pin, set the PCR5 bit to 1 (INT6 input disabled). INT7 Input Enable Bit (PCR5) (b5) To use the AN2_5 pin as an analog input pin, set the PCR6 bit to 1 (INT7 input disabled). Key Input Enable Bit(PCR7) (b7) To use pins AN4 to AN7 as analog input pins, set the PCR7 bit to 1 (key input disabled). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 230 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.2.11 NMI/SD Digital Filter Register (NMIDF) NMI/SD Digital Filter Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol NMIDF Bit Symbol NMIDF0 Bit Name Address 0369h Function b2 b1 b0 After Reset XXXX X000b RW RW NMIDF1 NMI/SD filter sampling clock select bit NMIDF2 — (b7-b3) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : No filter 1 : CPU clock divided by 2 0 : CPU clock divided by 4 1 : CPU clock divided by 8 0 : CPU clock divided by 16 1 : CPU clock divided by 32 0 : CPU clock divided by 64 1 : CPU clock divided by 128 RW RW No register bits. If necessary, set to 0. Read as undefined value — REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 231 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.3 Types of Interrupt Figure 14.1 shows Types of Interrupt. Software (non-maskable interrupt) Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Interrupt Special (non-maskable interrupt) Hardware Peripheral function (1) (maskable interrupt) NMI DBC (2) Watchdog timer Oscillation stop and reoscillation detection Voltage monitor 1 Voltage monitor 2 Single-step (2) Address match Note : 1. The peripheral functions in the MCU are used to generate peripheral interrupts. 2. Do not use this interrupt because it is provided exclusively for use by development tools. Figure 14.1 Types of Interrupt • Maskable interrupt • Non-maskable interrupt : The interrupt priority can be changed by enabling (disabling) an interrupt with the interrupt enable flag (I flag) or by using interrupt priority levels. : The interrupt priority cannot be changed by enabling (disabling) an interrupt with the interrupt enable flag (I flag) or by using interrupt priority levels. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 232 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.4 Software Interrupts A software interrupt occurs when executing instructions. Software interrupts are non-maskable interrupts. 14.4.1 Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction. 14.4.2 Overflow Interrupt An overflow interrupt occurs when executing the INTO instruction with the O flag in the FLG register set to 1 (the operation resulted in an overflow). The following are instructions whose O flag changes by an arithmetic operation: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, and SUB 14.4.3 BRK Interrupt A BRK interrupt occurs when the BRK instruction is executed. 14.4.4 INT Instruction Interrupt An INT instruction interrupt occurs when the INT instruction is executed. Software interrupt numbers 0 to 63 can be specified for the INT instruction. Because software interrupt numbers 2 to 31, 41 to 51, 59, and 60 are assigned to peripheral function interrupts, the same interrupt routine used for peripheral function interrupts can be executed by executing the INT instruction. For software interrupt numbers 0 to 31, the U flag is saved on the stack during instruction execution and is cleared to 0 (ISP selected) before executing an interrupt sequence. The U flag is restored from the stack when returning from the interrupt routine. For software interrupt numbers 32 to 63, the U flag does not change state during instruction execution, and the SP selected at the time is used. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 233 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.5 Hardware Interrupts Hardware interrupts are classified into two types: special interrupts and peripheral function interrupts. 14.5.1 Special Interrupts NMI Interrupt Special interrupts are non-maskable interrupts. 14.5.1.1 An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details about the NMI interrupt, refer to 14.9 “NMI Interrupt”. 14.5.1.2 DBC Interrupt Do not use this interrupt because it is provided exclusively for use by development tools. 14.5.1.3 Watchdog Timer Interrupt The interrupt is generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to refresh the watchdog timer. For details about the watchdog timer, refer to 15. “Watchdog Timer”. 14.5.1.4 Oscillation Stop and Re-Oscillation Detection Interrupt The interrupt is generated by the oscillation stop and re-oscillation detection function. For details about the oscillation stop and re-oscillation detection function, refer to 8. “Clock Generator”. 14.5.1.5 Voltage Monitor 1, Voltage Monitor 2 The interrupt is generated by the voltage detection circuit. For details about the voltage detection circuit, refer to 7. “Voltage Detector”. 14.5.1.6 Single-Step Interrupt Do not use this interrupt because it is provided exclusively for use by development tools. 14.5.1.7 Address Match Interrupt When the AIER0 or AIER1 bit in the AIER register, or the AIER20 or AIER21 bit in the AIER2 register is 1 (address match interrupt enabled), an address match interrupt is generated immediately before executing an instruction at the address indicated by the corresponding registers RMAD0 to RMAD3. For details about the address match interrupt, refer to 14.11 “Address Match Interrupt”. 14.5.2 Peripheral Function Interrupts A peripheral function interrupt occurs when a request from a peripheral function in the MCU is acknowledged. Peripheral function interrupts are maskable interrupts. See Table 14.6 and Table 14.7 “Relocatable Vector Tables”. Refer to the descriptions of each function for details on how the corresponding peripheral function interrupt is generated. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 234 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.6 Interrupts and Interrupt Vectors One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector. Figure 14.2 shows an Interrupt Vector. MSB Vector address (L) LSB Low-order address Middle-order address 0000 High-order address 0000 Vector address (H) 0000 Figure 14.2 Interrupt Vector REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 235 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.6.1 Fixed Vector Tables The fixed vector tables are allocated to addresses from FFFDCh to FFFFFh. Table 14.5 lists the Fixed Vector Tables. In the flash memory MCU version, the vector addresses (H) of fixed vectors are used for the ID code check function and OFS1 address. For details, refer to 30.5 “Flash Memory Rewrite Disable Function”. Table 14.5 Fixed Vector Tables Interrupt Source Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction (2) Address match Single-step (1) Watchdog timer, oscillation stop and re-oscillation detection, voltage monitor 1, voltage monitor 2 DBC (1) NMI Vector Table Addresses Address (L) to Address (H) FFFDCh to FFFDFh FFFE0h to FFFE3h FFFE4h to FFFE7h FFFE8h to FFFEBh FFFECh to FFFEFh FFFF0h to FFFF3h Reference M16C/60, M16C/20, M16C/ Tiny Series Software Manual 14.11 “Address Match Interrupt” 15. “Watchdog Timer” 8. “Clock Generator” 7. “Voltage Detector” 14.9 “NMI Interrupt” 6. “Resets” FFFF4h to FFFF7h FFFF8h to FFFFBh FFFFCh to FFFFFh Reset Notes: 1. Do not use this interrupt because it is provided exclusively for use by development tools. 2. If the content of address FFFE6h is FFh, program execution starts from the address shown by the vector in the relocatable vector table. 14.6.2 Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register compose a relocatable vector table area. Table 14.6 and Table 14.7 list the Relocatable Vector Tables. Setting an even address in the INTB register results in the interrupt sequence being executed faster than setting an odd address. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 236 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts Table 14.6 Relocatable Vector Tables (1/2) Vector Address (1) Address (L) to Address (H) +0 to +3 (0000h to 0003h) Interrupt Source BRK instruction (5) - (Reserved) INT7 INT6 INT3 Software Interrupt Number 0 1 Reference M16C/60, M16C/20, M16C/Tiny Series Software Manual 14.8 “INT Interrupt” +8 to +11 (0008h to 000Bh) +16 to +19 (0010h to 0013h) +20 to +23 (0014h to 0017h) 2 4 5 6 +12 to +15 (000Ch to 000Fh) 3 18. “Timer B” 18. “Timer B” 23. “Serial Interface UARTi (i = 0 to 2, 5 to 7)” 14.8 “INT Interrupt” 24. “Serial Interface SI/O3 and SI/O4” 23. “Serial Interface UARTi (i = 0 to 2, 5 to 7)” 16. “DMAC” 14.10 “Key Input Interrupt” 27. “A/D Converter” 23. “Serial Interface UARTi (i = 0 to 2, 5 to 7)” Timer B5 Timer B4, UART1 start/stop condition +24 to +27 (0018h to 001Bh) detection, bus collision detection (4) Timer B3, UART0 start/stop condition +28 to +31 (001Ch to 001Fh) 7 detection, bus collision detection (4) SI/O4, INT5 (2) SI/O3, INT4 (2) +32 to +35 (0020h to 0023h) +36 to +39 (0024h to 0027h) +40 to +43 (0028h to 002Bh) 8 9 10 UART2 start/stop condition detection, bus collision detection (4) DMA0 DMA1 Key input interrupt A/D converter UART2 transmit, NACK2 (3) UART2 receive, ACK2 (3) UART0 transmit, NACK0 (3) UART0 receive, ACK0 (3) UART1 transmit, NACK1 (3) UART1 receive, ACK1 (3) Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 Notes: 1. 2. 3. 4. 5. +44 to +47 (002Ch to 002Fh) 11 +48 to +51 (0030h to 0033h) +52 to +55 (0034h to 0037h) +56 to +59 (0038h to 003Bh) 12 13 14 +60 to +63 (003Ch to 003Fh) 15 +64 to +67 (0040h to 0043h) +68 to +71 (0044h to 0047h) +72 to +75 (0048h to 004Bh) +80 to +83 (0050h to 0053h) +84 to +87 (0054h to 0057h) +88 to +91 (0058h to 005Bh) +96 to +99 (0060h to 0063h) 16 17 18 20 21 22 24 +76 to +79 (004Ch to 004Fh) 19 17. “Timer A” +92 to +95 (005Ch to 005Fh) 23 +100 to +103 (0064h to 0067h) 25 +104 to +107 (0068h to 006Bh) 26 +108 to +111 (006Ch to 006Fh) 27 +112 to +115 (0070h to 0073h) 28 18. “Timer B” Address relative to address in INTB. Use bits IFSR6 and IFSR7 in the IFSR register to select a source. In I2C mode, NACK and ACK are interrupt sources. Use bits IFSR26 and IFSR27 in the IFSR2A register to select a source. These interrupts cannot be disabled using the I flag. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 237 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts Table 14.7 Relocatable Vector Tables (2/2) Interrupt Source INT0 INT1 INT2 Vector Address (1) Address (L) to Address (H) +116 to +119 (0074h to 0077h) +120 to +123 (0078h to 007Bh) +124 to +127 (007Ch to 007Fh) +128 to +131 (0080h to 0083h) to +160 to +163 (00A0h to 00A3h) +164 to +167 (00A4h to 00A7h) +168 to +171 (00A8h to 00ABh) +172 to +175 (00ACh to 0AFh) Software Interrupt Number 29 30 31 32 to 40 Reference 14.8 “INT Interrupt” INT instruction interrupt (3) M16C/60, M16C/20, M16C/Tiny Series Software Manuall 16. “DMAC” 23. “Serial Interface UARTi (i = 0 to 2, 5 to 7)” 26. “Consumer Electronics Control (CEC) Function” 20. “Real-Time Clock” 23. “Serial Interface UARTi (i = 0 to 2, 5 to 7)” DMA2 DMA3 UART5 start/stop condition detection, bus collision detection, CEC1 (4) (2), (4) 41 42 43 UART5 transmit, NACK5, CEC2 +176 to +179 (00B0h to 00B3h) UART5 receive, ACK5 (2) +180 to +183 (00B4h to 00B7h) 44 45 46 UART6 start/stop condition +184 to +187 (00B8h to 00BBh) detection, bus collision detection, real-time clock cycle (5) UART6 transmit, NACK6, +188 to +191 (00BCh to 00BFh) real-time clock compare match (2), (5) UART6 receive, ACK6 (2) UART7 start/stop condition detection, bus collision detection, remote control 0 (6) UART7 transmit, NACK7, remote control 1 (2), (6) UART7 receive, ACK7 (2) - (Reserved) I2C-bus interface interrupt (7) 47 48 49 +192 to +195 (00C0h to 00C3h) +196 to +199 (00C4h to 00C7h) +200 to +203 (00C8h to 00CBh) +204 to +207 (00CCh to 00CFh) +236 to +239 (00ECh to 00EFh) +240 to +243 (00F0h to 00F3h) 50 51 52 to 58 59 60 61 to 63 22. “Remote Control Signal Receiver” 23. “Serial Interface UARTi (i = 0 to 2, 5 to 7)” SCL/SDA interrupt (7) - (Reserved) Notes: 1. 2. 3. 4. 5. 6. 7. 25. “Multi-Master I2Cbus Interface” Address relative to address in INTB. In I2C mode, NACK and ACK are the interrupt sources. These interrupts cannot be disabled using the I flag. Use bits IFSR33 and IFSR34 in the IFSR3 register to select a source. Use bits IFSR35 and IFSR36 in the IFSR3 register to select a source. Use bits IFSR24 and IFSR25 in the IFSR2 register to select a source. Use bits IFSR22 and IFSR23 in the IFSR2 register to select a source. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 238 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.7 14.7.1 Interrupt Control Maskable Interrupt Control The settings of enabling/disabling the maskable interrupts and of the acceptance priority are explained below. Note that these explanations do not apply to non-maskable interrupts. Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in the corresponding interrupt control register to enable or disable a maskable interrupt. Whether an interrupt is requested or not is indicated by the IR bit in the corresponding interrupt control register. 14.7.1.1 I Flag The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable interrupts. Setting the I flag to 0 (disabled) disables all maskable interrupts. 14.7.1.2 IR Bit The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. Then, when the interrupt request is accepted, the IR bit is automatically set to 0 (interrupt not requested). The IR bit can be set to 0 by a program. Do not write 1 to this bit. 14.7.1.3 Bits ILVL2 to ILVL0 and IPL Interrupt priority levels can be set using bits ILVL2 to ILVL0. Table 14.8 lists the Settings of Interrupt Priority Levels and Table 14.9 lists the Interrupt Priority Levels Enabled by IPL. An interrupt request is accepted under the following conditions. • I flag = 1 • IR bit = 1 • Interrupt priority level > IPL The I flag, IR bit, bits ILVL2 to ILVL0 and IPL are independent each other. In no case do they affect one another. Table 14.8 Settings of Interrupt Priority Levels Interrupt Priority Level Level 0 (interrupt disabled) Table 14.9 IPL 000b 001b 010b 011b 100b 101b 110b 111b Interrupt Priority Levels Enabled by IPL Enabled Interrupt Priority Levels Level 1 and above are enabled Level 2 and above are enabled Level 3 and above are enabled Level 4 and above are enabled Level 5 and above are enabled Level 6 and above are enabled Level 7 and above are enabled All maskable interrupts are disabled Bits ILVL2 to ILVL0 000b 001b 010b 011b 100b 101b 110b 111b Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Priority Low High REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 239 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.7.2 Interrupt Sequence The interrupt sequence is explained here. The sequence starts when an interrupt request is accepted and ends when the interrupt routine is executed. If an interrupt request occurs during execution of an instruction, the processor determines its priority after the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. However, if an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR, or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. The CPU behavior during the interrupt sequence is described below. Figure 14.3 shows Time Required for Executing Interrupt Sequence. (1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading address 00000h. Then, the IR bit applicable to the interrupt information is set to 0 (interrupt not requested). (2) The FLG register, prior to the interrupt sequence, is saved to a temporary register (1) within the CPU. (3) Flags I, D, and U in the FLG register are set as follows: • The I flag is set to 0 (interrupt disabled) • The D flag is set to 0 (single-step interrupt disabled). • The U flag is set to 0 (ISP selected). Note that the U flag does not change states when an INT instruction for software interrupt numbers 32 to 63 is executed. (4) The temporary register (1) within the CPU is saved on the stack. (5) The PC is saved on the stack. (6) The interrupt priority level of the acknowledged interrupt is set in the IPL. (7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC. After the interrupt sequence is completed, an instruction is executed from the starting address of the interrupt routine. Note: 1. Temporary registers cannot be modified by users. 1 CPU clock Address bus Data bus RD WR (2) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Address 00000h Interrupt information Undefined (1) Undefined (1) Undefined (1) SP-2 SP-2 contents SP-4 SP-4 contents vec vec contents vec+2 vec+2 contents PC Notes : 1. The undefined state depends on the instruction queue buffer. A read cycle is generated when the instruction queue buffer is ready to accept instructions. 2. The WR signal timing shown here applies when the stack is located in the internal RAM. Figure 14.3 Time Required for Executing Interrupt Sequence REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 240 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.7.3 Interrupt Response Time Figure 14.4 shows the Interrupt Response Time. The interrupt response or interrupt acknowledge time denotes the time from when an interrupt request is generated until the first instruction in the interrupt routine is executed. Specifically, it consists of the time from when an interrupt request is generated until the executing instruction is completed ((a) in Figure 14.4) and the time during which the interrupt sequence is executed ((b) in Figure 14.4). Interrupt request generated Interrupt request acknowledged Time Instruction (a) Interrupt sequence (b) Instruction in interrupt routine Interrupt response time (a) The time from when an interrupt request is generated until the instruction currently executing is completed. The length of this time varies with the instruction being executed. The DIVX instruction requires the longest time, which is equal to 30 cycles (no wait state, and when the divisor is a register). (b) The time during which the interrupt sequence is executed. For details, see the table below. Note, however, that the values in this table must be increased by two cycles for the DBC interrupt and by one cycle for the address match and single-step interrupts. Interrupt Vector Address SP Value Even Even Odd Odd Even Odd Even Odd 16-Bit Bus, No Wait States 18 cycles 19 cycles 19 cycles 20 cycles 8-Bit Bus, No Wait States 20 cycles 20 cycles 20 cycles 20 cycles Figure 14.4 Interrupt Response Time 14.7.4 Variation of IPL When Interrupt Request is Accepted When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed in Table 14.10 is set in the IPL. Table 14.10 lists the IPL Level Set in IPL When Software or Special Interrupt is Accepted. Table 14.10 IPL Level Set in IPL When Software or Special Interrupt is Accepted Interrupt Source Watchdog timer, NMI, oscillation stop and re-oscillation detection, voltage monitor1, voltage monitor 2 Software, address match, DBC, single-step Level Set in IPL 7 Not changed REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 241 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.7.5 Saving Registers In the interrupt sequence, the FLG register and PC are saved on the stack. At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG register, 16 bits in total, are saved on the stack first. Next, the 16 low-order bits of the PC are saved. Figure 14.5 shows the Stack Status Before and After Acceptance of Interrupt Request. The other necessary registers must be saved by a program at the beginning of the interrupt routine. Use the PUSHM instruction, and all registers except SP can be saved with a single instruction. Address MSB Stack LSB Address MSB Stack LSB [SP] New SP value m-4 m-3 m-2 m-1 m m+1 Contents of previous stack Contents of previous stack [SP] SP value before interrupt request is accepted. m-4 m-3 m-2 m-1 m m+1 FLGH PCL PCM FLGL PCH Contents of previous stack Contents of previous stack PCL PCM PCH FLGL FLGH : 8 low-order bits of PC : 8 middle-order bits of PC : 4 high-order bits of PC : 8 low-order bits of FLG : 4 high-order bits of FLG Stack status before interrupt request is acknowledged Stack status after interrupt request is acknowledged Figure 14.5 Stack Status Before and After Acceptance of Interrupt Request The register save operation carried out in the interrupt sequence is dependent on whether the SP (1), at the time of acceptance of an interrupt request, is even or odd. If the SP (1) is even, the FLG register and the PC are saved 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time. Figure 14.6 shows the Register Save Operation. Note: 1. When an INT instruction with software numbers 32 to 63 has been executed, it is the SP indicated by the U flag. Otherwise, it is the ISP. (1) SP contains even number Address Stack Sequence in which registers are saved (2) SP contains odd number Address Stack Sequence in which registers are saved [SP] - 5 (Odd) [SP] - 4 (Even) [SP] - 3 (Odd) [SP] - 2 (Even) [SP] - 1 (Odd) [SP] (Even) Completed saving registers in two operations. FLGH PCL PCM FLGL PCH (1) All 16 bits saved simultaneously (2) All 16 bits saved simultaneously [SP] - 5 (Even) [SP] - 4 (Odd) [SP] - 3 (Even) [SP] - 2 (Odd) [SP] - 1 (Even) [SP] (Odd) Completed saving registers in four operations. PCL PCM PCH FLGL FLGH : 8 low-order bits of PC : 8 middle-order bits of PC : 4 high-order bits of PC : 8 low-order bits of FLG : 4 high-order bits of FLG FLGH PCL PCM FLGL PCH (3) (4) Saved 8 bits at a time (1) (2) Note : 1. [SP] denotes the initial value of the SP when an interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. Figure 14.6 Register Save Operation REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 242 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.7.6 Returning from an Interrupt Routine The FLG register and PC saved in the stack immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine. Then, the CPU returns to the program which was being executed before the interrupt request was accepted. Restore the other registers saved by a program within the interrupt routine using the POPM or another instruction before executing the REIT instruction. The register bank is switched back to the bank used prior to the interrupt sequence by the REIT instruction. 14.7.7 Interrupt Priority If two or more interrupt requests occur at the same sampling points (the point in time at which interrupt requests are detected), the interrupt with the highest priority is acknowledged. For maskable interrupts (peripheral function interrupts), any priority level can be selected using bits ILVL2 to ILVL0. However, if two or more maskable interrupts have the same priority level, their interrupt priority is selected by hardware, with the highest priority interrupt accepted. The watchdog timer interrupt and other special interrupts have their priority levels set in hardware. Figure 14.7 shows the Hardware Interrupt Priority. Software interrupts are not affected by the interrupt priority. When an instruction is executed, control always branches to the interrupt routine. Reset NMI DBC Watchdog timer, oscillation stop and re-oscillation detection, voltage monitor 1, voltage monitor 2 Peripheral functions Single-step Address match Figure 14.7 Hardware Interrupt Priority High Low 14.7.8 Interrupt Priority Level Select Circuit The interrupt priority level select circuit selects the highest priority interrupt among sampled interrupt requests at the same sampling point. Figure 14.8 shows the Interrupt Priority Select Circuit 1, and Figure 14.9 shows the Interrupt Priority Select Circuit 2. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 243 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts Higher Priority level of each interrupt SCL/SDA I2C bus interface UART7 transmit, NACK7, remote control 1 UART6 receive, ACK6 UART6 start/stop condition Level 0 (initial value) Priority level of each interrupt Timer B1 Timer A4 Timer A2 Timer B3, UART0 start/stop condition detection, bus collision detection detection, bus collision detection, real-time clock cycle UART5 transmit, NACK5, CEC2 UART0 receive, ACK0 DMA3 UART2 receive, ACK2 UART7 receive, ACK7 A/D conversion UART7 start/stop condition detection, bus collision detection, remote control 0 DMA1 UART2 start/stop condition detection, bus collision detection Timer B5 UART1 receive, ACK1 Priority of peripheral function interrupts (if priority levels are same) UART6 transmit, NACK6, real-time clock compare UART5 receive, ACK5 SI/O4, INT5 UART5 start/stop condition detection, bus collision detection, CEC1 DMA2 Timer A0 UART1 transmit, NACK1 UART0 transmit, NACK0 INT1 UART2 transmit, NACK2 Timer B2 Key input interrupt Timer B0 DMA0 Timer A3 Timer A1 Timer B4, UART1 start/stop condition SI/O4, INT5 INT6 INT7 detection, bus collision detection INT3 INT2 INT0 To “Interrupt Priority Select Circuit 2” (A) Lower Higher Priority of peripheral function interrupts (if priority levels are same) Lower Figure 14.8 Interrupt Priority Select Circuit 1 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 244 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts (A) IPL Determine and output interrupt request level to clock generating circuit I flag Address match Watchdog timer Oscillation stop and re-oscillation detection Voltage monitor 1 Voltage monitor 2 DBC NMI Interrupt request accepted Figure 14.9 Interrupt Priority Select Circuit 2 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 245 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.7.9 Multiple Interrupts The following shows the internal bit states when control has branched to an interrupt routine. • I flag = 0 (interrupt disabled) • IR bit = 0 (interrupt not requested) • Interrupt priority level= IPL By setting the I flag to 1 (interrupt enabled) in the interrupt routine, an interrupt request with higher priority than the IPL can be acknowledged. The interrupt requests not acknowledged because of their low interrupt priority level are kept pending. When the IPL is restored by an REIT instruction and interrupt priority is resolved against it, the pending interrupt request is acknowledged if the following condition is met: Interrupt priority level of pending interrupt request > Restored IP REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 246 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.8 INT Interrupt The INTi interrupt (i = 0 to 7) is triggered by the edges of external inputs. The edge polarity is selected using the IFSRi bit in the IFSR register, or the IFSR30 or IFSR31 bit in the IFSR3A register. The INT4 and INT5 each share an interrupt vector and interrupt control register with SI/O3 and SI/O4, respectively. To use the INT4 interrupt, set the IFSR6 bit in the IFSR register to 1 (INT4). To use the INT5 interrupt, set the IFSR7 bit in the IFSR register to 1 (INT5). After modifying the IFSR6 or IFSR7 bit, set the corresponding IR bit to 0 (interrupt not requested) before enabling the interrupt. To use the INT6 interrupt, set the PCR5 bit in the PCR register to 0 (INT6 input enabled). To use the INT7 interrupt, set the PCR6 bit in the PCR register to 0 (INT7 input enabled). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 247 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.9 NMI Interrupt An NMI interrupt is generated when input to the NMI pin changes state from high to low. The NMI interrupt is a non-maskable interrupt. To use the NMI interrupt, set the PM24 bit in the PM2 register to 1 (NMI function). The NMI input uses the digital filter. Refer to 13. “Programmable I/O Ports” for the digital filter. Figure 14.10 shows NMI Interrupt Block Diagram. NMIDF2 to NMIDF0 NMI Digital filter PM24 NMI interrupt NMIDF2 to NMIDF0 : Bits in the NMIDF register PM24 : Bit in the PM2 register Figure 14.10 NMI Interrupt Block Diagram 14.10 Key Input Interrupt If the PCR7 bit in the PCR register is 0 (KI0 to KI3 key input enabled), set bits PD10_4 to PD10_7 in the PD10 register to 0 (input). When input to any pin from P10_4 to P10_7 becomes low, the IR bit in the KUPIC register becomes 1 (key input interrupt request). When using any pin from KI0 to KI3 for the key input interrupt, do not use all four pins AN4 to AN7 as analog input pins. While input to any pin from P10_4 to P10_7 is low, inputs to all other pins of the port are not detected as interrupts. Key input interrupts can be used as a key-on wake up function for getting the MCU out of wait or stop mode. Figure 14.11 shows Block Diagram of Key Input Interrupt. Pull-up transistor PU25 bit in the PUR2 register PD10_7 bit in the PD10 register PD10_7 bit in the PD10 register KI3 Pull-up transistor KI2 Pull-up transistor KI1 Pull-up transistor KI0 PD10_4 bit in the PD10 register PD10_5 bit in the PD10 register PD10_6 bit in the PD10 register PCR7 bit in the PCR register Key input interrupt request (IR bit in the KUPIC register) Figure 14.11 Block Diagram of Key Input Interrupt REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 248 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.11 Address Match Interrupt An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMADi register (i = 0 to 3). Set the start address of any instruction in the RMADi register. Use bits AIER0 and AIER1 in the AIER register, and bits AIER20 and AIER21 in the AIER2 register to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL. When an address match interrupt request is acknowledged, the value of the PC that is saved to the stack area (refer to 14.7.5 “Saving Registers”) varies depending on the instruction at the address indicated by the RMADi register. (The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow one of the methods described below to return from the address match interrupt. • Rewrite the contents of the stack and then use the REIT instruction to return. • Restore the stack to its previous state by using the POP or other instructions before the interrupt request was accepted and then use a jump instruction to return. Table 14.11 lists the Value of PC Saved on Stack Area When Address Match Interrupt Request Accepted. Note that when using an 8-bit external bus, no address match interrupts can be used for external areas. Refer to 14.2.7 “Address Match Interrupt Enable Register (AIER)”, 14.2.8 “Address Match Interrupt Enable Register 2 (AIER2)”, 14.2.9 “Address Match Interrupt Register i (RMADi) (i = 0 to 3)”. Table 14.11 Value of PC Saved on Stack Area When Address Match Interrupt Request Accepted Instruction at the Address Indicated by the RMADi Register Value of the PC that is saved to the stack area The address indicated by the RMADi register +2 • 16-bit operation code instructions • Instruction shown below among 8-bit operation code instructions ADD.B:S OR.B:S STNZ CMP.B:S JMPS MOV.B:S #IMM8, dest SUB.B:S #IMM8, dest AND.B:S #IMM8, dest #IMM8, dest MOV.B:S #IMM8, dest STZ #IMM8, dest #IMM8, dest STZX #IMM81, #IMM82,dest #IMM8, dest PUSHM src POPM dest #IMM8 JSRS #IMM8 #IMM, dest (However, dest = A0 or A1) Instructions other than the above The address indicated by the RMADi register +1 Value of PC that saved on stack area: Refer to 14.7.5 “Saving Registers”. Table 14.12 Relationship between Address Match Interrupt Sources and Associated Registers Address Match Interrupt Sources Address Match Interrupt Enable Bit Address Match Interrupt Register Address match interrupt 0 Address match interrupt 1 Address match interrupt 2 Address match interrupt 3 AIER0 AIER1 AIER20 AIER21 RMAD0 RMAD1 RMAD2 RMAD3 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 249 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.12 Non-Maskable Interrupt Source Discrimination The watchdog timer interrupt, oscillation stop and re-oscillation detection interrupt, voltage monitor 1 interrupt, and voltage monitor 2 interrupt share the same interrupt vector. When using some functions together, read the detect flags of the events in an interrupt processing program, and determine the interrupt source of the interrupt request. Table 14.13 lists Bits Used for Non-Maskable Interrupt Source Discrimination. Table 14.13 Bits Used for Non-Maskable Interrupt Source Discrimination Interrupt Watchdog timer Detect Flag Bit Position VW2C3 bit in the VW2C register (watchdog timer underflow detected) Function 0: not detected 1: detected Oscillation stop and CM22 bit in the CM2 register re-oscillation detection (oscillation stop and re-oscillation detected) Voltage monitor 1 Voltage monitor 2 VW1C2 bit in the VW1C register (Vdet1 passage detected) VW2C2 bit in the VW2C register (Vdet2 passage detected) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 250 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.13 Notes on Interrupts 14.13.1 Reading Address 00000h Do not read the address 00000h by a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from address 00000h during the interrupt sequence. At this time, the IR bit of the accepted interrupt is cleared to 0. If the address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to 0. Thus, some problems may be caused: interrupts may be canceled, and an unexpected interrupt request may be generated. 14.13.2 SP Setting Set a value in the SP (USP, ISP) before accepting an interrupt. The SP (USP, ISP) is set to 0000h after reset. Therefore, if an interrupt is accepted before setting a value in the SP (USP, ISP), the program may go out of control. Especially when using the NMI interrupt, set a value in the ISP at the beginning of the program. For the first instruction after reset only, all interrupts including the NMI interrupt are disabled. 14.13.3 NMI Interrupt • When the NMI interrupt is not used, set the PM24 bit in the PM2 register to 0 (NMI interrupt disabled). • Stop mode cannot be entered while the 24 bit is 1 (NMI interrupt enabled) and input on the NMI pin is low. When input on the NMI pin is low, the CM10 bit in the CM1 register is fixed to 0. • Do not enter wait mode while the 24 bit is 1 (NMI interrupt enabled) and input on the NMI pin is low because the CPU clock remains active even though the CPU stops, and therefore, the current consumption of the chip does not drop. In this case, the normal condition is restored by the next interrupt generated. • Set the low- and high-level durations of the input signal to the NMI pin to 2 CPU clock cycles + 300 ns or more. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 251 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.13.4 Changing an Interrupt Source If the interrupt source is changed, the IR bit in the interrupt control register may inadvertently be set to 1 (interrupt requested). To use an interrupt, change the interrupt source, and then set the IR bit to 0 (interrupt not requested). In this section, the changing of an interrupt source refers to all elements (e.g. changing the mode of a peripheral function) used in changing the interrupt source, polarity, and timing assigned to each software interrupt number. When using an element to change the interrupt source, polarity, or timing, make the change before setting the IR bit to 0 (interrupt not requested). Refer to the descriptions of the individual peripheral functions for details of the peripheral function interrupts. Figure 14.12 shows the Procedure for Changing the Interrupt Generate Factor. Change the interrupt source Disable interrupts (2, 3) Change the interrupt source (including a mode change of peripheral function) Use the MOV instruction to set the IR bit to 0 (interrupt not requested) (3) Enable interrupts (2, 3) Change completed IR bit: A bit in the interrupt control register for the interrupt whose interrupt source is to be changed Notes : 1. The above settings must be executed individually. Do not execute two or more settings simultaneously (using one instruction). 2. Use the I flag for the INTi interrupt (i = 0 to 7). For the interrupts from peripheral functions other than the INTi interrupt, turn off the peripheral function that is the source of the interrupt in order not to generate an interrupt request before changing the interrupt source. In this case, if the maskable interrupts can all be disabled without causing a problem, use the I flag. Otherwise, use the corresponding bits ILVL2 to ILVL0 for the interrupt whose interrupt source is to be changed. 3. Refer to the following “Rewriting the Interrupt Control Register” for details about the instructions to use and the notes to be taken for instruction execution. Figure 14.12 Procedure for Changing the Interrupt Generate Factor REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 252 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.13.5 Rewriting the Interrupt Control Register (a) The interrupt control register for any interrupt should be modified in places where no requests for that register may occur. If an interrupt request generation is a possibility, disable an interrupt and then rewrite the contents of the interrupt control register. (b) When rewriting the contents of the interrupt control register after disabling an interrupt, be careful with the instruction used. • Changing bits other than the IR bit When interrupts corresponding to the register occur, the IR bit may not be set to 1 (interrupt requested) and the interrupts may be ignored. If this causes a problem, use one of the following instructions to change the registers. Instructions: AND, OR, BCLR, or BSET. • Changing the IR bit Depending on the instruction used, the IR bit may not always be set to 0 (interrupt not requested). Therefore, use the MOV instruction to set the IR bit to 0. (c) When using the I flag to disable an interrupt, set the I flag as shown in the sample program code shown below. (Refer to (b) regarding rewriting the contents of the interrupt control registers using the sample program code.) Examples 1 through 3 show how to prevent the I flag from being set to 1 (interrupt enabled) before the contents of the interrupt control register are rewritten, owing to the effects of the internal bus and the instruction queue buffer. Example 1: Using the NOP instruction to pause the program until the interrupt control register is modified INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Set the TA0IC register to 00h. NOP ; NOP FSET I ; Enable interrupts. The number of the NOP instructions is as follows. PM20 = 1 (1 wait): 2, PM20 = 0 (2 waits): 3, when using the HOLD function: 4. Example 2: Using a dummy read to delay the FSET instruction INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Set the TA0IC register to 00h. MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3: Using the POPC instruction to change the I flag INT_SWITCH3: PUSHC FLG FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Set the TA0IC register to 00h. POPC FLG ; Enable interrupts. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 253 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 14. Interrupts 14.13.6 INT Interrupt • Either a low level of at least tw (INL) width or a high level of at least tw (INH) width is necessary for the signal input to pins INT0 through INT7 regardless of the CPU operation clock. • If the POL bit in registers INT0IC to INT7IC, bits IFSR7 to IFSR0 in the IFSR register, or bits IFSR31 to IFSR30 in the IFSR3A register are changed, the IR bit may inadvertently be set to 1 (interrupt requested). Be sure to set the IR bit to 0 (interrupt not requested) after changing any of these register bits. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 254 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 15. Watchdog Timer 15. Watchdog Timer 15.1 Introduction The watchdog timer contains a 15-bit counter, and the count source protection mode (enabled/disabled) can be set. Table 15.1 shows Watchdog Timer Specification. Refer to 6.4.8 “Watchdog Timer Reset” for details of watchdog timer reset. Figure 15.1 shows Watchdog Timer Block Diagram. Table 15.1 Watchdog Timer Specification Count Source Protection Mode Disabled Count Source Protection Mode Enabled CPU clock fOCO-S Decrement Either of the following can be selected (selected by the WDTON bit in the OFS1 address). • Count automatically starts after reset. • Count starts by writing to the WDTS register. Stop mode, wait mode, bus hold None • Reset (Refer to 6. “Resets”) • Write 00h, and then FFh to the WDTR register. • Underflow Watchdog timer interrupt or watchdog Watchdog timer reset timer reset • Prescaler divide ratio Divide-by-16 or divide-by-128 (selected by the WDC7 bit in the WDC register) However, divide-by-2 is selected when the CM07 bit in the CM0 register is 1 (sub clock). • Count source protection mode Enabled or disabled (selected by the CSPROINI bit in the OFS1 address and the CSPRO bit in the CSPR register) Item Count source Count operation Count start conditions Count stop condition Watchdog timer counter initial value setting conditions Operation when the timer underflows Selectable functions Write to the WDTR register Internal reset signal (low active) WDTR register written WDTON bit Prescaler WDC7 1/16 CM07 Refresh 1/128 CPU clock Bus hold fOCO-S 1/2 0 CSPRO Watchdog timer counter b14 b10 b3 b0 1 PM12 WDC4 to WDC0 Underflow 0 Watchdog timer interrupt 1 Watchdog timer reset Figure 15.1 Watchdog Timer Block Diagram REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 255 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 15. Watchdog Timer 15.2 Registers Register Structure Table 15.2 Address 002Ch 037Ch 037Dh 037Eh 037Fh Note: 1. When the CSPROINI bit in the OFS1 address is 0, the value after reset becomes 1000 0000b. Register Name Register Symbol After Reset Voltage Monitor 2 Circuit Control Register VW2C 1000 0X10b Count Source Protection Mode Register CSPR 00h (1) Watchdog Timer Reset Register WDTR XXh Watchdog Timer Start Register WDTS XXh Watchdog Timer Control Register WDC 00XX XXXXb 15.2.1 Voltage Monitor 2 Circuit Control Register (VW2C) Voltage Monitor 2 Circuit Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol VW2C Address 002Ch After Reset 1000 0X10b (hardware reset, power-on reset, voltage monitor 0 reset) Function 0 : Disabled 1 : Enabled RW RW Bit Symbol VW2C0 Bit Name Voltage monitor 2 interrupt/ reset enable bit VW2C1 Voltage monitor 2 digital filter 0 : Enable digital filter disable mode select bit 1 : Disable digital filter Voltage change detection flag WDT detection flag 0 : Not detected 1 : Vdet2 passage detected 0 : Not detected 1 : Watchdog timer underflow detected b5 b4 RW VW2C2 RW VW2C3 RW VW2F0 Sampling clock select bit VW2F1 Voltage monitor 2 circuit mode select bit Voltage monitor 2 interrupt/ reset generation condition select bit 0 0 1 1 0 : fOCO-S divided by 1 1 : fOCO-S divided by 2 0 : fOCO-S divided by 4 1 : fOCO-S divided by 8 RW VW2C6 0 : Voltage monitor 2 interrupt at Vdet2 passage 1 : Voltage monitor 2 reset at Vdet2 passage 0 : When VCC1 reaches Vdet2 or above 1 : When VCC1 reaches Vdet2 or below RW VW2C7 RW Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VW2C register. Since rewriting the VW2C register may set the VW2C2 bit to 1, set the VW2C2 bit to 0 after rewriting the VW2C register. Bits VW2C2 and VW2C3 do not change at voltage monitor 1 reset, voltage monitor 2 reset, oscillation stop detection reset, watchdog timer reset, or software reset. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 256 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 15. Watchdog Timer VW2C3 (WDT Detection Flag) (b3) Use this bit in an interrupt routine to determine the source of the interrupts from the watchdog timer, the oscillation stop/re-oscillation detection, the voltage monitor 1, and the voltage monitor 2. Conditions to become 0: • Hardware reset, power-on reset, or voltage monitor 0 reset • Writing 0 by a program Condition to become 1: • Watchdog timer underflow detected (This flag remains unchanged even if 1 is written by a program.) 15.2.2 Count Source Protection Mode Register (CSPR) Count Source Protection Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol CSPR Address 037Ch After Reset 0000 0000b (When the CSPROINT bit in the OFS1 address is 1) 1000 0000b (When the CSPROINT bit in the OFS1 address is 0) Function Set to 0 0 : Count source protection mode disabled 1 : Count source protection mode enabled RW RW 0000000 Bit Symbol — (b6-b0) CSPRO Bit Name Reserved bits Count source protection mode select bit RW CSPRO (Count Source Protection Mode Select Bit) (b7) Select the CSPRO bit before the watchdog timer starts counting. Once counting starts, do not change the CSPRO bit. Condition to become 0: • Reset when the CSPROINI bit in the OFS1 address is 1. (This flag remains unchanged even if 0 is written by a program.) Condition to become 1: • When the CSPROINI bit in the OFS1 address is 0 • Write 0, and then write 1. Make sure no interrupts or DMA transfers will occur between setting the bit to 0 and setting it to 1. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 257 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 15. Watchdog Timer 15.2.3 Watchdog Timer Reset Register (WDTR) Watchdog Timer Reset Register b7 b0 Symbol WDTR Address 037Dh Function After Reset Undefined RW WO Setting 00h and then FFh refreshes the watchdog timer. After the watchdog timer interrupt occurs, refresh the watchdog timer by setting the WDTR register. 15.2.4 Watchdog Timer Start Register (WDTS) Watchdog Timer Start Register b7 b0 Symbol WDTS Address 037Eh Function After Reset Undefined RW WO The watchdog timer starts counting after a write instruction to this register The WDTS register is enabled when the WDTON bit in the OFS1 address is 1 (watchdog timer is in a stopped state after reset). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 258 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 15. Watchdog Timer 15.2.5 Watchdog Timer Control Register (WDC) Watchdog Timer Control Register b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol WDC Bit Symbol WDC0 Bit Name Address 037Fh Function After Reset 00XX XXXXb RW RO WDC1 RO WDC2 Higher-order bits (b14 to b10) of the watchdog timer can be read RO WDC3 RO WDC4 — (b5) — (b6) WDC7 RO No register bit. If necessary, set to 0. Read as 0 — Reserved bit Set to 0 0 : Divide-by-16 1 : Divide-by-1128 RW Prescaler select bit RW WDC4-WDC0 (b4-b0) When reading the watchdog timer value while the CSPRO bit in the CSPR register is 1 (count source protection mode enabled), read bits WDC4 to WDC0 more than three times to determine the values. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 259 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 15. Watchdog Timer 15.3 15.3.1 Optional Function Select Area Optional Function Select Address 1 (OFS1) Optional Function Select Address 1 b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol OFS1 Bit Symbol Bit Name Address FFFFFh Function Factory Setting FFh RW WDTON Watchdog timer start select bit 0 : Watchdog timer starts automatically after reset. 1 : Watchdog timer is in a stopped state after reset. Set to 1. 0 : ROM code protection cancelled. 1 : ROMCP1 bit enabled. 0 : ROM code protection enabled. 1 : ROM code protection disabled. Set to 1. 0 : 2.85 V (Vdet0_2) 1 : 1.90 V (Vdet0_0) 0 : Voltage monitor 0 reset enabled after hardware reset. 1 : Voltage monitor 0 reset disabled after hardware reset. 0 : Count source protection mode enabled after reset. 1 : Count source protection mode disabled after reset. RW — (b1) ROMCR Reserved bit RW ROM code protect cancel bit RW ROMCP1 ROM code protect bit — (b4) VDSEL1 RW Reserved bit RW Vdet0 select bit 1 RW LVDAS Voltage detection 0 circuit start bit RW After-reset count source CSPROINI protection mode select bit RW The OFS1 address exists in flash memory. Set a proper value when writing a program in flash memory. The OFS1 address is set to FFh when the block including the OFS1 address is erased. WDTON (Watchdog Timer Start Select Bit) (b0) Set the WDTON bit to 0 (watchdog timer starts automatically after reset) when setting the CSPROINI bit to 0 (count source protection mode enabled after reset). CSPROINI (After-Reset Count Source Protection Mode Select Bit) (b7) Set the WDTON bit to 0 (watchdog timer starts automatically after reset) when setting the CSPROINI bit to 0 (count source protection mode enabled after reset). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 260 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 15. Watchdog Timer 15.4 15.4.1 Operations Count Source Protection Mode Disabled The CPU clock is used as the watchdog timer count source when count source protection mode is disabled. Table 15.3 lists Watchdog Timer Specifications (Count Source Protection Mode Disabled). Table 15.3 Watchdog Timer Specifications (Count Source Protection Mode Disabled) Item Count source Count operation Cycles Specification CPU clock Decrement When the CM07 bit in the CM0 register is 0 (main clock, PLL clock, fOCO-F, fOCO-S): Prescaler divide value (n) × watchdog timer count value (32768) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------ (1) CPU clock n: 16 or 128 (selected by the WDC7 bit in the WDC register) ex.) When CPU clock frequency is 16 MHz and the prescaler division rate is 16, the watchdog timer cycle is approximately 32.8 ms. When the CM07 bit is 1 (sub clock): Prescaler divide value (2) × watchdog timer count value (32768) (1) -----------------------------------------------------------------------------------------------------------------------------------------------------------------------CPU clock Watchdog timer counter initial value setting Count start conditions • Reset (Refer to 6. “Resets”.) • Write 00h, and then FFh to the WDTR register. • Underflow Set the WDTON bit in the OFS1 address to select the watchdog timer operation after reset. • WDTON bit is 1 (watchdog timer is in stop state after reset) The watchdog timer and prescaler stop after reset and count starts by writing to the WDTS register. • WDTON bit is 0 (watchdog timer starts automatically after reset) The watchdog timer and prescaler start counting automatically after reset. • Stop mode • Wait mode • Bus hold (Count resumes from the hold value after exiting.) • PM12 bit in the PM1 register is 0 Watchdog timer interrupt • PM12 bit in the PM1 register is 1 Watchdog timer reset (See 6.4.8 “Watchdog Timer Reset”.) Count stop conditions Operation when timer underflows Notes: 1. Writing 00h and then FFh to the WDTR register initializes the watchdog timer, but not the prescaler. Thus, some errors in the watchdog timer period may be caused by the prescaler. The prescaler is initialized after reset. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 261 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 15. Watchdog Timer 15.4.2 Count Source Protection Mode Enabled The fOCO-S is used as the watchdog timer count source when the count source protection mode is enabled. Table 15.4 lists the Watchdog Timer Specifications (Count Source Protection Mode Enabled). Table 15.4 Watchdog Timer Specifications (Count Source Protection Mode Enabled) Item Count source Count operation Cycle Specification fOCO-S (The 125 kHz on-chip oscillator clock automatically starts oscillating.) Decrement Watchdog timer count value (4096) -------------------------------------------------------------------------------------------fOCO-S (The watchdog timer cycle is approximately 32.8 ms.) Watchdog timer • Reset (Refer to 6. “Resets”.) counter initial value • Write 00h, and then FFh to the WDTR register. setting • Underflow Count start Set the WDTON bit in the OFS1 address to select the watchdog timer operation conditions after reset. • WDTON bit is 1 (watchdog timer is stopped after reset) The watchdog timer and prescaler stop after reset and count starts by writing to the WDTS register. • WDTON bit is 0 (watchdog timer starts automatically after reset) The watchdog timer and prescaler start counting automatically after reset. Count stop None (Count does not stop in wait mode or by bus hold once count starts. The MCU condition does not enter stop mode.) Operation when Watchdog timer reset (See 6.4.8 “Watchdog Timer Reset”). timer underflows When the CSPRO bit in the CSPR register is 1 (count source protection mode enabled), the watchdog timer counter underflows every 4096 cycles because three low-order bits are not used. Also when the CSPRO bit is set to 1 (count source protection mode enabled), the following bits change: • The CM14 bit in the CM1 register becomes 0 (125 kHz on-chip oscillator on). It remains unchanged even if 1 is written, and the 125 kHz on-chip oscillator does not stop. • The PM12 bit in the PM1 register becomes 1 (watchdog timer reset when watchdog timer counter underflows). • The CM10 bit in the CM1 register remains unchanged even if 1 is written, and the MCU does not enter stop mode. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 262 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 15. Watchdog Timer 15.5 Interrupts Watchdog timer interrupts are non-maskable interrupts. The watchdog timer interrupt, oscillation stop and re-oscillation detection interrupt, voltage monitor 1 interrupt, and voltage monitor 2 interrupt share an vector. When using multiple functions, read the detect flag in an interrupt process program to determine which interrupt factor sends an interrupt request. The VW2C3 bit in the VW2C register is the detect flag for the watchdog timer. After the interrupt factor is determined, set the VW2C3 bit to 0 (not detected) by a program. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 263 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 15. Watchdog Timer 15.6 Notes on Watchdog Timer After the watchdog timer interrupt occurs, use the WDTR register to refresh the watchdog timer counter. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 264 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 16. DMAC 16. DMAC 16.1 Introduction The direct memory access controller (DMAC) allows data to be transferred without CPU intervention. Four DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8- or 16bit) unit of data from the source address to the destination address. The DMAC uses the same data bus used by the CPU. Because the DMAC has higher priority for bus control than the CPU, and because it makes use of a cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time after a DMA request is generated. Figure 16.1 shows the DMAC Block Diagram. Table 16.1 lists DMAC Specifications, and Figure 16.1 shows DMAC Block Diagram. Table 16.1 DMAC Specifications Item Number of channels Transfer memory spaces Maximum number of bytes transferred DMA request factors (1) Specification 4 (cycle steal method) • From a given address in the 1-Mbyte space to a fixed address • From a fixed address to a given address in the 1-Mbyte space • From a fixed address to a fixed address 128 Kbytes (with 16-bit transfers) or 64 Kbytes (with 8-bit transfers) 43 factors Falling edge of INT0 to INT7 (8) Both edges of INT0 to INT7 (8) Timer A0 to timer A4 interrupt requests (5) Timer B0 to timer B5 interrupt requests (6) UART0 to 2, UART5 to 7 transmission interrupt requests (6) UART0 to 2, UART5 to 7 reception/ACK interrupt requests (6) SI/O3, SI/O4 interrupt requests (2) A/D conversion interrupt requests (1) Software triggers (1) Channel priority DMA0 > DMA1 > DMA2 > DMA3 (DMA0 takes precedence) Transfers 8 bits or 16 bits Transfer address direction Forward or fixed (The source and destination addresses cannot both be in the forward direction.) Transfer Single transfer Transfer is completed when the DMAi transfer counter underflows. mode Repeat When the DMAi transfer counter underflows, it is reloaded with the value of the transfer DMAi transfer counter reload register and DMA transfer continues. DMA interrupt request When the DMAi transfer counter underflows generation timing DMA transfer start Data transfer is initiated each time a DMA request is generated when the DMAE bit in the DMAiCON register is 1 (enabled). Single transfer • When the DMAE bit is set to 0 (disabled) DMA transfer • After the DMAi transfer counter underflows stop Repeat When the DMAE bit is set to 0 (disabled) transfer Reload timing for forward When a data transfer is started after setting the DMAE bit to 1 (enabled), the address pointer and DMAi forward address pointer is reloaded with the value of the SARi or DARi pointer whichever is specified to be in the forward direction and the DMAi transfer transfer counter counter is reloaded with the value of the DMAi transfer counter reload register. DMA transfer cycles Minimum 3 cycles between SFR and internal RAM i = 0 to 3 Note: 1. The selectable sources of DMA requests differ for each channel. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 265 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 16. DMAC Address bus DMA0 source pointer SAR0 DMA0 destination pointer DAR0 DMA0 forward address pointer DMA1 source pointer SAR1 DMA1 destination pointer DAR1 DMA1 forward address pointer DMA2 source pointer SAR2 DMA2 destination pointer DAR2 DMA2 forward address pointer DMA3 source pointer SAR3 DMA3 destination pointer DAR3 DMA3 forward address pointer DMA latch high-order bits DMA latch low-order bits DMA0 transfer counter reload register TCR0 DMA0 transfer counter TCR0 DMA1 transfer counter reload register TCR1 DMA1 transfer counter TCR1 DMA2 transfer counter reload register TCR2 DMA2 transfer counter TCR2 DMA3 transfer counter reload register TCR3 DMA3 transfer counter TCR3 Data bus low-order bits Data bus high-order bits Figure 16.1 DMAC Block Diagram REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 266 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 16. DMAC 16.2 Registers Table 16.2 lists Register Structure. Do not access these registers during DMAC operation. Table 16.2 Register Structure Address 0180h 0181h 0182h 0184h 0185h 0186h 0188h 0189h 018Ch 0190h 0191h 0192h 0194h 0195h 0196h 0198h 0199h 019Ch 01A0h 01A1h 01A2h 01A4h 01A5h 01A6h 01A8h 01A9h 01ACh 01B0h 01B1h 01B2h 01B4h 01B5h 01B6h 01B8h 01B9h 01BCh 0390h 0392h 0398h 039Ah Register Name DMA0 Source Pointer DMA0 Destination Pointer DMA0 Transfer Counter DMA0 Control Register DMA1 Source Pointer DMA1 Destination Pointer DMA1 Transfer Counter DMA1 Control Register DMA2 Source Pointer DMA2 Destination Pointer DMA2 Transfer Counter DMA2 Control Register DMA3 Source Pointer DMA3 Destination Pointer DMA3 Transfer Counter DMA3 Control Register DMA2 Source Select Register DMA3 Source Select Register DMA0 Source Select Register DMA1 Source Select Register Register Symbol After Reset SAR0 XXh XXh 0Xh DAR0 XXh XXh 0Xh TCR0 XXh XXh DM0CON 0000 0X00b SAR1 XXh XXh 0Xh DAR1 XXh XXh 0Xh TCR1 XXh XXh DM1CON 0000 0X00b SAR2 XXh XXh 0Xh DAR2 XXh XXh 0Xh TCR2 XXh XXh DM2CON 0000 0X00b SAR3 XXh XXh 0Xh DAR3 XXh XXh 0Xh TCR3 XXh XXh DM3CON 0000 0X00b DM2SL 00h DM3SL 00h DM0SL 00h DM1SL 00h REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 267 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 16. DMAC 16.2.1 DMAi Source Pointer (SARi) (i = 0 to 3) DMAi Source Pointer (i = 0 to 3) (b23) b7 (b19) b3 (b16) (b15) b0 b7 (b8) b0 b7 b0 Symbol SAR0 SAR1 SAR2 SAR3 Function Set the source address of transfer Address 0182h to 0180h 0192h to 0190h 01A2h to 01A0h 01B2h to 01B0h After Reset 0X XXXXh 0X XXXXh 0X XXXXh 0X XXXXh Setting Range 00000h to FFFFFh RW RW No register bits. If necessary, set to 0. Read as 0 — If the DSD bit in the DMiCON register is 0 (fixed), write to this register when the DMAE bit in the DMiCON register is 0 (DMA disabled). If the DSD bit is 1 (forward direction), this register can be written to at any time. If the DSD bit is 1 and the DMAE bit is 1 (DMA enabled), the DMAi forward address pointer can be read from this register. Otherwise, the value written to it can be read. The forward address pointer is incremented when a DMA request is accepted. 16.2.2 DMAi Destination Pointer (DARi) (i = 0 to 3) DMAi Destination Pointer (i = 0 to 3) (b23) b7 (b19) b3 (b16) (b15) b0 b7 (b8) b0 b7 b0 Symbol DAR0 DAR1 DAR2 DAR3 Function Set the destination address of transfer Address 0186h to 0184h 0196h to 0194h 01A6h to 01A4h 01B6h to 01B4h After Reset 0X XXXXh 0X XXXXh 0X XXXXh 0X XXXXh Setting Range 00000h to FFFFFh RW RW No register bits. If necessary, set to 0. Read as 0 — If the DAD bit in the DMiCON register is 0 (fixed), write to this register when the DMAE bit in the DMiCON register is 0 (DMA disabled). If the DAD bit is 1 (forward direction), this register can be written to at any time. If the DAD bit is 1 and the DMAE bit is 1 (DMA enabled), the DMAi forward address pointer can be read from this register. Otherwise, the value written to it can be read. The forward address pointer is incremented on accepting a DMA request. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 268 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 16. DMAC 16.2.3 DMAi Transfer Counter (TCRi) (i = 0 to 3) DMAi Transfer Counter (i = 0 to 3) (b15) b7 (b8) b0 b7 b0 Symbol TCR0 TCR1 TCR2 TCR3 Function Set the transfer count minus 1. Address 0189h to 0188h 0199h to 0198h 01A9h to 01A8h 01B9h to 01B8h After Reset Undefined Undefined Undefined Undefined Setting Range 0000h to FFFFh RW RW The written value in the TCRi register is stored in the DMAi transfer counter reload register. The value of the DMAi transfer counter reload register is transferred to the DMAi transfer counter in either of the following cases: • When the DMAE bit in the DMiCON register is set to 1 (DMA enabled) (single transfer mode, repeat transfer mode) • When the DMAi transfer counter underflows (repeat transfer mode) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 269 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 16. DMAC 16.2.4 DMAi Control Register (DMiCON) (i = 0 to 3) DMAi Control Register (i = 0 to 3) b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM0CON DM1CON DM2CON DM3CON Bit Symbol DMBIT Bit Name Address 018Ch 019Ch 01ACh 01BCh Function 0 : 16 bits 1 : 8 bits After Reset 0000 0X00b 0000 0X00b 0000 0X00b 0000 0X00b RW RW Transfer unit bit select bit DMASL Repeat transfer mode select 0 : Single transfer bit 1 : Repeat transfer DMA request bit 0 : DMA not requested 1 : DMA requested 0 : Disabled 1 : Enabled 0 : Fixed 1 : Forward RW DMAS RW DMAE DMA enable bit Source address direction select bit RW DSD RW DAD — (b7-b6) Destination address direction 0 : Fixed select bit 1 : Forward No register bits. If necessary, set to 0. Read as 0 RW — DMAS (DMA Request Bit) (b2) Conditions to become 0: • Set the bit to 0. • Starting data transfer Condition to become 1: • Set the bit to 1. DMAE (DMA Enable Bit) (b3) Conditions to become 0: • Set the bit to 0. • The DMA transfer counter underflows (single transfer mode) Condition to become 1: • Set the bit to 1. DSD (Source Address Direction Select Bit) (b4) Set at least one of the DAD bit and DSD bit to 0 (address direction fixed). DAD (Destination Address Direction Select Bit) (b5) Set at least one of the DAD bit and DSD bit to 0 (address direction fixed). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 270 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 16. DMAC 16.2.5 DMAi Source Select Register (DMiSL) (i = 0 to 3) DMAi Source Select Register (i = 0 to 3) b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM0SL DM1SL DM2SL DM3SL Bit Symbol DSEL0 DSEL1 Bit Name Address 0398h 039Ah 0390h 0392h Function After Reset 00h 00h 00h 00h RW RW RW DSEL2 DSEL3 DSEL4 — (b5) DMS DMA request source select bit See the bit explanation below. RW RW No register bit. If necessary, set to 0. Read as 0 DMA request source expansion select bit 0: Basic request source 1: Extended request source A DMA request is generated by setting this bit to 1 when the DMS bit is 0 (basic source) and bits DSEL4 to DSEL0 are 00001b (software trigger). Read as 0 — RW DSR Software DMA request bit RW DSEL4-DSEL0 (DMA Request Source Select Bit) (b4-b0) The sources of DMAi requests can be selected by a combination of the DMS bit and bits DSEL4 to DSEL0 in the manner shown in Table 16.3 to Table 16.6. Table 16.3 to Table 16.6 list the sources of DMAi requests. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 271 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 16. DMAC Table 16.3 Source of DMA Request (DMA0) DMS = 1 (Extended Source of Request) – – – – – – Both edges of INT0 pin Timer B3 Timer B4 Timer B5 – – – – – – Falling edge of INT4 pin Both edges of INT4 pin – – – – – – – DSEL4 to DSEL0 DMS = 0 (Basic Source of Request) 0 0000b Falling edge of INT0 pin 0 0001b Software trigger 0 0010b Timer A0 0 0011b Timer A1 0 0100b Timer A2 0 0101b Timer A3 0 0110b Timer A4 0 0111b Timer B0 0 1000b Timer B1 0 1001b Timer B2 0 1010b UART0 transmission 0 1011b UART0 reception 0 1100b UART2 transmission 0 1101b UART2 reception 0 1110b A/D conversion 0 1111b UART1 transmission 1 0000b UART1 reception 1 0001b UART5 transmission 1 0010b UART5 reception 1 0011b UART6 transmission 1 0100b UART6 reception 1 0101b UART7 transmission 1 0110b UART7 reception 1 0111b – 1 1XXXb – X indicates 0 or 1. – indicates no setting. Table 16.4 Source of DMA Request (DMA1) DMS = 1 (Extended Source of Request) – – – – – SI/O3 SI/O4 Both edges of INT1 pin – – – – – – – – Falling edge of INT5 pin Both edges of INT5 pin – – – – – – – DSEL4 to DSEL0 DMS = 0 (Basic Source of Request) 0 0000b Falling edge of INT1 pin 0 0001b Software trigger 0 0010b Timer A0 0 0011b Timer A1 0 0100b Timer A2 0 0101b Timer A3 0 0110b Timer A4 0 0111b Timer B0 0 1000b Timer B1 0 1001b Timer B2 0 1010b UART0 transmission 0 1011b UART0 reception/ACK0 0 1100b UART2 transmission 0 1101b UART2 reception/ACK2 0 1110b A/D conversion 0 1111b UART1 reception/ACK1 1 0000b UART1 transmission 1 0001b UART5 transmission 1 0010b UART5 reception/ACK5 1 0011b UART6 transmission 1 0100b UART6 reception/ACK6 1 0101b UART7 transmission 1 0110b UART7 reception/ACK7 1 0111b – 1 1XXXb – X indicates 0 or 1. – indicates no setting. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 272 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 16. DMAC Table 16.5 Source of DMA Request (DMA2) DMS = 1 (Extended Source of Request) – – – – – – Both edges of INT2 pin Timer B3 Timer B4 Timer B5 – – – – – – Falling edge of INT6 pin Both edges of INT6 pin – – – – – – – DSEL4 to DSEL0 DMS = 0 (Basic Source of Request) 0 0000b Falling edge of INT2 pin 0 0001b Software trigger 0 0010b Timer A0 0 0011b Timer A1 0 0100b Timer A2 0 0101b Timer A3 0 0110b Timer A4 0 0111b Timer B0 0 1000b Timer B1 0 1001b Timer B2 0 1010b UART0 transmission 0 1011b UART0 reception 0 1100b UART2 transmission 0 1 1 0 1b UART2 reception 0 1110b A/D conversion 0 1111b UART1 transmission 1 0000b UART1 reception 1 0001b UART5 transmission 1 0010b UART5 reception 1 0011b UART6 transmission 1 0100b UART6 reception 1 0101b UART7 transmission 1 0110b UART7 reception 1 0111b – 1 1XXXb – X indicates 0 or 1. – indicates no setting. Table 16.6 Source of DMA Request (DMA3) DMS = 1 (Extended Source of Request) – – – – – SI/O3 SI/O4 Both edges of INT3 pin – – – – – – – – Falling edge of INT7 pin Both edges of INT7 pin – – – – – – – DSEL4 to DSEL0 DMS = 0 (Basic Source of Request) 0 0000b Falling edge of INT3 pin 0 0001b Software trigger 0 0010b Timer A0 0 0011b Timer A1 0 0100b Timer A2 0 0101b Timer A3 0 0110b Timer A4 0 0111b Timer B0 0 1000b Timer B1 0 1001b Timer B2 0 1010b UART0 transmission 0 1011b UART0 reception/ACK0 0 1100b UART2 transmission 0 1 1 0 1b UART2 reception/ACK2 0 1110b A/D conversion 0 1111b UART1 reception/ACK1 1 0000b UART1 transmission 1 0001b UART5 transmission 1 0010b UART5 reception/ACK5 1 0011b UART6 transmission 1 0100b UART6 reception/ACK6 1 0101b UART7 transmission 1 0110b UART7 reception/ACK7 1 0111b – 1 1XXXb – X indicates 0 or 1. – indicates no setting. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 273 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 16. DMAC 16.3 16.3.1 Operations DMA Enabled When data transfer starts after setting the DMAE bit in the DMiCON register (i = 0 to 3) to 1 (enabled), the DMAC operates as listed below. If 1 is written to the DMAE bit when it is already set to 1, the DMAC also performs the following operation. • The forward address pointer is reloaded with the SARi register value when the DSD bit in the DMiCON register is 1 (forward), or the DARi register value when the DAD bit in the DMiCON register is 1 (forward). • The DMAi transfer counter is reloaded with the DMAi transfer counter reload register value. 16.3.2 DMA Request The DMAC can generate a DMA request as triggered by the request source that is selected with the DMS bit and bits DSEL4 to DSEL0 in the DMiSL register (i = 0 to 3) on either channel. Table 16.7 lists the Timing at Which the DMAS Bit Changes State. Whenever a DMA request is generated, the DMAS bit is set to 1 (DMA requested) regardless of whether or not the DMAE bit is set. If the DMAE bit is set to 1 (enabled) when this occurs, the DMAS bit is set to 0 (DMA not requested) immediately before a data transfer starts. This bit cannot be set to 1 by a program (writing a 1 has no effect). If the DMAE bit is 1, the DMAS bit in almost all cases is 0 when read in a program, because a data transfer starts immediately after a DMA request is generated. Read the DMAE bit to determine whether the DMAC is enabled. When a DMA request transfer cycle is shorter than a DMA transfer cycle, the number of transfer requests and the number of transfers do not agree. When the peripheral function is selected as a DMA source, relations with interrupts are as follows: • DMA transfers are not affected by the I flag or interrupt control registers. DMA requests are always accepted even when interrupt requests are not accepted. • The IR bit in the interrupt control register retains its value when a DMA transfer is accepted. Table 16.7 Timing at Which the DMAS Bit Changes State DMA Source Software trigger External factor Peripheral function DMAS Bit in the DMiCON Register Timing at Which the Bit is Set to 1 Timing at Which the Bit is Set to 0 When the DSR bit in the DMiSL register • Immediately before a data transfer is set to 1 starts When an input edge of pins INT0 to • When set by writing a 0 by a program INT7 agrees with what is selected by bits DSEL4 to DSEL0 in the DMiSL register. When an interrupt request of the peripheral function selected by bits DSEL4 to DSEL0 and DMS in the DMiSL register is generated. (If the IR bit in an interrupt control register is 0, the timing is when 0 is changed to 1.) i = 0 to 3 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 274 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 16. DMAC 16.3.3 Transfer Cycles A transfer cycle is composed of a bus cycle to read data from a source address (source read), and a bus cycle to write data to a destination address (destination write). The number of read and write bus cycles depends on the source and destination addresses. Figure 16.2 shows Transfer Cycles for Source Read Operations. For convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. When calculating transfer cycles, take into consideration each condition for the source read and the destination write cycle. For example, when data is transferred in 16-bit units using an 8-bit bus ((2) in Figure 16.2), two source read bus cycles and two destination write bus cycles are required. 16.3.3.1 Effect of Source and Destination Addresses When a 16-bit unit of data is transferred with a 16-bit data bus and the source address starts with an odd address, the source-read cycle is incremented by one bus cycle, compared to a source address starting with an even address. When a 16-bit unit of data is transferred with a 16-bit data bus and the destination address starts with an odd address, the destination-write cycle is incremented by one bus cycle, compared to a destination address starting with an even address. 16.3.3.2 Effect of Software Wait For memory or SFR accesses in which one or more software wait states are inserted, the number of bus cycles required increases by an amount equal to the number of software wait states. 16.3.3.3 Memory Expansion Mode and Microprocessor Mode In memory expansion or microprocessor mode, the transfer cycle is also affected by the BYTE pin level. Furthermore, the bus cycle itself is extended by a software wait or RDY signal. If 16 bits of data are transferred on an 8-bit data bus (input to the BYTE pin is high), the operation is accomplished by transferring 8 bits of data twice. Therefore, this operation requires two bus cycles to read data and two bus cycles to write data. Furthermore, if the DMAC accesses an internal area (internal ROM, internal RAM, or SFR), unlike in the case of the CPU, the DMAC uses the data bus width selected by the BYTE pin. DMA transfers to and from an external area are affected by the RDY signal. Refer to 11.3.5.6 “RDY Signal” for more information. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 275 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 16. DMAC (1) Transfers are performed in 8-bit or 16-bit units, and source of transfer is an even address. BCLK Address bus RD signal WR signal Data bus CPU use Source Destination Dummy cycle CPU use CPU use Source Destination Dummy cycle CPU use (2) Transfers are performed in 16-bit units, and the source address of transfer is an odd address. BCLK Address bus RD signal WR signal Data bus CPU use Source Source + 1 Destination Dummy cycle CPU use CPU use Source Source + 1 Destination Dummy cycle CPU use (3) Source read cycle under condition (1) with one wait state inserted BCLK Address bus RD signal WR signal Data bus CPU use Source Destination Dummy cycle CPU use CPU use Source Destination Dummy cycle CPU use (4) Source read cycle under condition (2) with one wait state inserted BCLK Address bus RD signal WR signal Data bus CPU use Source Source + 1 Destination Dummy cycle CPU use CPU use Source Source + 1 Destination Dummy cycle CPU use Note : 1. The same timing changes occur with the respective conditions at the destination as at the source. Figure 16.2 Transfer Cycles for Source Read Operations REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 276 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 16. DMAC 16.3.4 DMAC Transfer Cycles The number of DMA transfer cycles can be calculated as shown below. Table 16.8 lists the DMAC Transfer Cycles, and Table 16.9 and Table 16.10 list coefficients j and k. Number of transfer cycles per transfer unit = Number of read cycles × j + Number of write cycles × k Table 16.8 DMAC Transfer Cycles Transfer Unit 8-bit transfers (DMBIT = 1) Bus Width 16-bit (BYTE = low) 8-bit (BYTE = high) Access Address Even Odd Even Odd Even Odd Even Odd Single-Chip Mode No. of Read Cycles 1 1 N/A N/A 1 2 N/A N/A No. of Write Cycles 1 1 N/A N/A 1 2 N/A N/A 16-bit transfers 16-bit (DMBIT = 0) (BYTE = low) 8-bit (BYTE = high) Table 16.9 Memory Expansion Mode Microprocessor Mode No. of Read No. of Write Cycles Cycles 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 Coefficients j and k (1/2) Internal Area Internal ROM, RAM SFR 1 wait state 2 wait states No wait Wait states (2) (2) states External Area Multiplex bus Wait states (1) 1 wait state 2 wait states 3 wait states 3 3 4 3 3 4 j 1 2 2 3 k 1 2 2 3 Notes: 1. Depends on the set value of the CSE register. 2. Depends on the set value of the PM20 bit in the PM2 register. Table 16.10 Coefficients j and k (2/2) External Area Separate bus (1) No wait states 1wait state (1φ + 1φ) 2 2 Wait states (2) 2 wait states 3 wait states 2φ + 3φ (1φ + 2φ) (1φ + 3φ) 3 4 5 3 4 5 2φ + 4φ 3φ + 4φ 4φ + 5φ j 1 6 7 9 k 2 6 7 9 Notes: 1. When recovery cycle inserted is selected at bits EWR1 and EWR0 in the EWR register, add the recovery cycle. 2. Depends on the set values of registers CSE and EWC. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 277 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 16. DMAC 16.3.5 Single Transfer Mode In single transfer mode, the transfer stops when the DMAi transfer counter underflows. Figure 16.3 shows Operation Example in Single Transfer Mode. Single Transfer Mode Bus CPU DMA CPU DMA CPU DMA CPU When a transfer begins, the DMAS bit is set to 0. DMAS bit Underflow TCRi bit Undefined 02h Reload 01h 00h FFh Set to 0 by an interrupt request acknowledgement or by a program. IR bit DMAE bit Set to 1 by a program. i = 0 to 3 DMAS, DMAE : Bits in the DMiCON register IR : Bit in the DMiIC register The above diagram applies when the register bit is set as follows: Value in the TCRi register = 02h (there are three transfers). Figure 16.3 Operation Example in Single Transfer Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 278 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 16. DMAC 16.3.6 Repeat Transfer Mode In repeat transfer mode, when the DMAi transfer counter underflows, it is reloaded with the value of the DMAi transfer counter reload register and DMA transfer continues. Figure 16.4 shows Operation Example in Repeat Transfer Mode. Repeat Transfer Mode Bus CPU DMA CPU DMA CPU DMA CPU DMA CPU When a transfer begins, the DMAS bit is set to 0. DMAS bit Underflow TCRi bit Undefined 02h Reload 01h 00h 02h 01h Set to 0 by an interrupt request acknowledgement or by a program. IR bit DMAE bit Set to 1 by a program. i = 0 to 3 DMAS, DMAE : Bits in the DMiCON register IR : Bit in the DMiIC register The above diagram applies when the register bit is set as follows: Value in the TCRi register = 02h (there are three transfers). Figure 16.4 Operation Example in Repeat Transfer Mode 16.3.7 Channel Priority and DMA Transfer Timing If multiple channels among DMA0 to DMA3 are enabled and DMA transfer request signals are detected active in the same sampling period (one period from a falling edge to the next falling edge of BCLK), the DMAS bit on each channel is set to 1 (DMA requested) at the same time. In this case, the DMA requests are arbitrated according to the following channel priority: DMA0 > DMA1 > DMA2 > DMA3. The DMAC operation when DMA0 and DMA1 requests are detected active in the same sampling period is described below. Figure 16.5 shows an example of DMA Transfer by External Sources. In Figure 16.5, DMA0, which has a high channel priority, is received first to start a transfer when DMA0 and DMA1 requests are generated simultaneously. After one DMA0 transfer is completed, the bus access privilege is returned to the CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one DMA1 transfer is completed, the bus access privilege is again returned to the CPU. In addition, DMA requests cannot be incremented since each channel has one DMAS bit. Therefore, when DMA requests, such as DMA1 in Figure 16.5, occur more than once, the DMAS bit is set to 0 after receiving the bus access privilege. The bus access privilege is returned to the CPU when one transfer is completed. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 279 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 16. DMAC Example when DMA requests for external sources are detected active at the same time and DMA transfer is executed in the shortest cycle BCLK DMA0 DMA1 CPU INT0 DMAS bit in DMA0 INT1 DMAS bit in DMA1 Figure 16.5 DMA Transfer by External Sources Bus access privilege REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 280 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 16. DMAC 16.4 Interrupts Refer to operation examples for interrupt request generation timing. For the details of interrupt control, refer to 14.7 “Interrupt Control”. Table 16.11 lists DMAC Interrupt Related Registers. Table 16.11 DMAC Interrupt Related Registers Address 004Bh 004Ch 0069h 006Ah Register Name DMA0 Interrupt Control Register DMA1 Interrupt Control Register DMA2 Interrupt Control Register DMA3 Interrupt Control Register Register Symbol DM0IC DM1IC DM2IC DM3IC After Reset XXXX X000b XXXX X000b XXXX X000b XXXX X000b When the DMS bit or bits DSEL4 to DSEL0 in the DMiSL register are changed, the DMAS bit in the DMiCON sometimes becomes 1 (DMA requested). Therefore, set the DMAS bit to 0 (DMA not requested) after the DMS bit or bits DSEL4 to DSEL0 in the DMiSL register are changed. Refer to 14.13 “Notes on Interrupts”. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 281 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 16. DMAC 16.5 16.5.1 Notes on DMAC Write to the DMAE Bit in the DMiCON Register (i = 0 to 3) When both of following conditions are met, follow steps (1) and (2) below. • Write a 1 (DMAi is in active state) to the DMAE bit when it is 1. • A DMA request may occur simultaneously when the DMAE bit is being written. Steps (1) Write a 1 to the DMAE bit and DMAS bit in the DMiCON register simultaneously (1). (2) Make sure that the DMAi is in an initialized state (2) in a program. If the DMAi is not in an initialized state, repeat these two steps. Notes: 1. The DMAS bit remains unchanged even if a 1 is written. However, if a 0 is written to this bit, it is set to 0 (DMA not requested). In order to prevent the DMAS bit from being modified to 0, 1 should be written to the DMAS bit when 1 is written to the DMAE bit. In this way, the state of the DMAS bit immediately before being written can be maintained. Similarly, when writing to the DMAE bit with a read-modify-write instruction, write a 1 to the DMAS bit to maintain a DMA request which is generated during execution. 2. Read the TCRi register to verify whether the DMAi is in an initialized state. If the read value is equal to a value that was written to the TCRi register before DMA transfer start, the DMAi is in an initialized state. (When a DMA request occurs after writing to the DMAE bit, the read value is a value written to the TCRi register minus one.) If the read value is a value in the middle of a transfer, the DMAi is not in an initialized state. 16.5.2 Changing DMA Request Source When the DMS bit or bits DSEL4 to DSEL0 in the DMiSL register are changed, the DMAS bit in the DMiCON sometimes becomes 1 (DMA requested). Set the DMAS bit to 0 (DMA not requested) after the DMS bit or bits DSEL4 to DSEL0 in the DMiSL register are changed. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 282 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17. Timer A Note The 80-pin package does not have pins TA1IN, TA1OUT, TA2IN and TA2OUT. Do not use functions associated with these pins. 17.1 Introduction Timers A0 to A4 are provided for timer A. Each timer operates independently of the others. Table 17.1 lists Specifications of Timer A, Table 17.2 lists Differences in Timer A Mode, Figure 17.1 shows Timer A and B Count Sources, Figure 17.2 shows Timer A Configuration, Figure 17.3 shows Timer A Block Diagram, and Table 17.3 lists I/O Ports. Table 17.1 Item Configuration Operating mode 16-bit timer × 5 • Timer mode The timer counts an internal count source. • Event counter mode The timer counts pulses from an external device or overflows and underflows of other timers. • One-shot timer mode The timer outputs a pulse only once before it reaches the minimum count 0000h. • Pulse width modulation (PWM) mode The timer outputs pulses of given width and cycle successively. • Programmable output mode The timer outputs a given pulse width of a high-/low- level signal (timers A1, A2, and A4). Overflow/underflow × 5 Specifications of Timer A Specification Interrupt source Table 17.2 Differences in Timer A Mode Item Event counter mode (two-phase pulse signal processing) Programmable output mode Timer A0 No No A1 No Yes A2 Yes Yes A3 Yes No A4 Yes Yes REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 283 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A Clock Generator Main clock generator or PLL frequency synthesizer 40 MHz on-chip oscillator fOCO-F f1TIMAB 1 PCLK0 Divider fOCO-F 1 CM21 0 1 f1 0 0 TCDIV00 fOCO-F f1TIMAB or f2TIMAB f8TIMAB 1/4 Timer AB divider 1/2 f32TIMAB f64TIMAB fOCO-S 1/2 1/8 f2TIMAB 0 1 FRA01 125 KHz on-chip oscillator Sub clock generator fOCO-S fOCO-S fC 1/32 Reset Set the CPSR bit in the CPSRF register to 1 (prescaler reset). fC32 CM21 PCLK0 FRA01 TCDIV00 fC32 : Bit in the CM2 register : Bit in the PCLKR register : Bit in the FRA0 register : Bit in the TCKDIVC0 register Figure 17.1 Timer A and B Count Sources REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 284 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A fC32 fOCO-S f64TIMAB f32TIMAB f8TIMAB f1TIMAB or f2TIMAB 00 01 10 11 TCK1 to TCK0 0 TCS3 TMOD1 to TMOD0 10 00: Timer mode 10: One-shot timer mode 11: PWM mode, programmable output mode 1 000 001 010 011 101 110 Timer A0 interrupt Timer A0 01: Event counter mode TCS2 to TCS0 01 00 11 TA0TGH to TA0TGL TA0IN (1) 00 01 10 11 Noise filter TCK1 to TCK0 0 TCS7 TMOD1 to TMOD0 10 00: Timer mode 10: One-shot timer mode 11: PWM mode, programmable output mode TCS6 to TCS4 000 001 010 011 101 110 1 01 00 Timer A1 01: Event counter mode Timer A1 interrupt 11 TA1TGH to TA1TGL TA1IN 00 01 10 11 Noise filter TCK1 to TCK0 0 TCS3 TMOD1 to TMOD0 10 00: Timer mode 10: One-shot timer mode 11: PWM mode, programmable output mode 1 000 001 010 011 101 110 Timer A2 interrupt TCS2 to TCS0 01 00 Timer A2 01: Event counter mode 11 TA2TGH to TA2TGL TA2IN 00 01 10 11 Noise filter TCK1 to TCK0 0 TCS7 TMOD1 to TMOD0 10 00: Timer mode 10: One-shot timer mode 11: PWM mode, programmable output mode 1 000 001 010 011 101 110 TCS6 to TCS4 01 00 Timer A3 01: Event counter mode Timer A3 interrupt 11 TA3TGH to TA3TGL TA3IN 00 01 10 11 Noise filter TCK1 to TCK0 0 TCS3 TMOD1 to TMOD0 10 00: Timer mode 10: One-shot timer mode 11: PWM mode, programmable output mode 1 000 001 010 011 101 110 Timer A4 interrupt TCS2 to TCS0 01 00 Timer A4 01: Event counter mode 11 TA4TGH to TA4TGL TA4IN Noise filter Timer B2 overflow or underflow TCK1 to TCK0, TMOD1 to TMOD0 : Bits in the TAiMR register TAiGH to TAiGL : Bits in the ONSF register or TRGSR register TCS0 to TCS7 : Bits in registers TACS0 to TACS2 i = 0 to 4 Note: 1. TA0IN shares pins with TB5IN. Figure 17.2 Timer A Configuration REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 285 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A fC32 fOCO-S fOCO-F f64TIMAB f32TIMAB f8TIMAB f1TIMAB or f2TIMAB PWMFSi TAi1 register Count source select 00 01 10 11 Data Bus TAi register TCK1 to TCK0 0 TCS3 or TCS7 ·Timer: TMOD1 to TMOD0 = 00, MR2 = 0 ·One-shot timer: TMOD1 to TMOD0 = 10 TMOD1 to TMOD0, ·Pulse width modulation, MR2 programmable output: TMOD1 to TMOD0 = 11 ·Timer (gate function): TMOD1 to TMOD0 = 00, MR2 = 1 Reload register 000 001 010 011 100 101 110 TCS2 to TCS0 or TCS6 to TCS4 1 ·Event counter: TMOD1 to TMOD0 = 01 Counter Increment/decrement Always decrement except in event counter mode TAiS Polarity select TAiIN TB2 overflow (1) TAj overflow (1) TAk overflow (1) 00 01 10 11 Decrement TAiUD 00 10 11 01 TMOD1 to TMOD0 To external trigger circuit TAiTGH to TAiTGL MR0 POFSi TAiOUT 0 1 Toggle flip-flop i = 0 to 4 j = i - 1, except j = 4 if i = 0 k = i + 1, except k = 0 if i = 4 Note: 1. Overflow or underflow TAi TAj Timer A0 Timer A4 TCK1 to TCK0, TMOD1 to TMOD0, MR2 to MR0 : Bits in the TAiMR register Timer A0 TAiTGH to TAiTGL : Bits in the ONSF register when i=0, bits in the TRGSR register when i = 1 to 4 Timer A1 Timer A2 Timer A1 TAiS : Bits in the TABSR register TAiUD : Bits in the UDF register Timer A3 Timer A2 TCS0 to TCS7 : Bits in the registers TACS0 to TACS2 Timer A4 Timer A3 POFSi : Bits in the TAPOFS register PWMFSi : Bits in the PWMFS register TAk Timer A1 Timer A2 Timer A3 Timer A4 Timer A0 Figure 17.3 Timer A Block Diagram Table 17.3 I/O Ports Pin Name TAiIN I/O Type Input (1) Function Gate input (timer mode) Count source input (event counter mode) Two-phase signal input (event counter mode (two-phase pulse signal processing)) Trigger input (one-shot timer mode, PWM mode) (2) TAiOUT Pulse output (timer mode, event counter mode, one-shot timer Output mode, PWM mode, and programmable output mode) Increment/decrement select input (event counter mode) Input (1) Two-phase pulse input (event counter mode (two-phase pulse signal processing)) ZP Z-phase (counter initialization) input (event counter mode (twoInput (1) phase pulse signal processing)) i = 0 to 4; however, i = 2, 3, 4 for two-phase pulse input, and i = 1, 2, 4 in programmable output mode Notes: 1. When using pins TAiIN, TAiOUT, and ZP for input, set the port direction bits corresponding to the pins to 0 (input mode). 2. The TA0OUT pin is an N-channel open-drain output. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 286 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.2 Registers Table 17.4 lists registers associated with timer A. Set the TCDIV00 bit in the TCKDIVC0 register before setting other registers associated with timer A. After changing the TCDIV00 bit, set other registers associated with timer A again. Refer to “registers and the setting” in each mode for registers and bit settings. Table 17.4 Register Structure Address 0012h 0015h 01CBh 01D0h 01D1h 01D2h 01D4h 01D5h 01D8h 0302h 0303h 0304h 0305h 0306h 0307h 0320h 0322h 0323h 0324h 0326h 0327h 0328h 0329h 032Ah 032Bh 032Ch 032Dh 032Eh 032Fh 0336h 0337h 0338h 0339h 033Ah Register Name Peripheral Clock Select Register Clock Prescaler Reset Flag Timer AB Division Control Register 0 Timer A Count Source Select Register 0 Timer A Count Source Select Register 1 Timer A Count Source Select Register 2 16-Bit Pulse Width Modulation Mode Function Select Register Timer A Waveform Output Function Select Register Timer A Output Waveform Change Enable Register Timer A1-1 Register Timer A2-1 Register Timer A4-1 Register Count Start Flag One-Shot Start Flag Trigger Select Register Up/Down Flag Timer A0 Register Timer A1 Register Timer A2 Register Timer A3 Register Timer A4 Register Timer A0 Mode Register Timer A1 Mode Register Timer A2 Mode Register Timer A3 Mode Register Timer A4 Mode Register Register Symbol PCLKR CPSRF TCKDIVC0 TACS0 TACS1 TACS2 PWMFS TAPOFS TAOW TA11 TA21 TA41 TABSR ONSF TRGSR UDF TA0 TA1 TA2 TA3 TA4 TA0MR TA1MR TA2MR TA3MR TA4MR After Reset 0000 0011b 0XXX XXXXb 0000 X000b 00h 00h X0h 0XX0 X00Xb XXX0 0000b XXX0 X00Xb XXh XXh XXh XXh XXh XXh 00h 00h 00h 00h XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh 00h 00h 00h 00h 00h REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 287 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.2.1 Peripheral Clock Select Register (PCLKR) Peripheral Clock Select Register b7 b6 b5 b4 b3 b2 b1 b0 00 000 Symbol PCLKR Bit Symbol Bit Name Address 0012h Function After Reset 0000 0011b RW PCLK0 Timers A and B clock select bit (clock source for timers A and B, the dead time timer, and muliti-master I2C-bus interface) SI/O clock select bit (clock source for UART0 to UART2, UART5 to UART7, SI/O3, and SI/O4) Reserved bits Clock output function extension bit (valid in single-chip mode) Reserved bits 0: f2TIMAB/f2IIC 1: f1TIMAB/f1IIC RW PCLK1 0: f2SIO 1: f1SIO RW — (b4-b2) PCLK5 — (b7-b6) Set to 0 0: Selected by bits CM01 to CM00 in the CM0 register 1: Output f1 Set to 0 RW RW RW Set the PCLKR register after the PRC0 bit in the PRCR register is set to 1 (write enabled). 17.2.2 Clock Prescaler Reset Flag (CPSRF) Clock Prescaler Reset Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol CPSRF Bit Symbol — (b6-b0) CPSR Bit Name Address 0015h Function After Reset 0XXX XXXXb RW — No register bits. If necessary, set to 0. Read as undefined value Setting this bit to 1 initializes the prescaler for the timekeeping clock. (Read as 0) Clock prescaler reset flag RW REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 288 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.2.3 Timer AB Division Control Register 0 (TCKDIVC0) Timer AB Division Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 0000 00 Symbol TCKDIVC0 Bit Symbol TCDIV00 — (b2-b1) — (b3) — (b7-b4) Bit Name Address 01CBh Function After Reset 0000 X000b RW RW Clock select prior to timer AB 0 : f1 1 : fOCO-F division bit Reserved bits Set to 0 RW No register bit. If necessary, set to 0. Read as undefined value — Reserved bits Set to 0 RW TCDIV00 (Clock Select Prior to Timer AB Division Bit) (b1) Set the TCDIV00 bit while timer A and B stops. Set the TCDIV00 bit before setting other registers associated with timer A. After changing the TCDIV00 bit, set other registers associated with timer A again. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 289 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.2.4 Timer A Count Source Select Register i (TACSi) (i = 0 to 2) Timer A Count Source Select Register 0, Timer A Count Source Select Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol TACS0 to TACS1 Bit Symbol TCS0 Bit Name Address 01D0h to 01D1h Function b2 b1 b0 After Reset 00h RW RW TCS1 TAi count source select bit TCS2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : f1TIMAB or f2TIMAB 1 : f8TIMAB 0 : f32TIMAB 1 : f64TIMAB 0 : fOCO-F 1 : fOCO-S 0 : fC32 1 : Do not set RW RW TCS3 TAi count source option specified bit 0 : TCK0, TCK1 enabled, TCS0 to TCS2 disabled 1 : TCK0, TCK1 disabled, TCS0 to TCS2 enabled b6 b5 b4 RW TCS4 TCS5 TAj count source select bit TCS6 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : f1TIMAB or f2TIMAB 1 : f8TIMAB 0 : f32TIMAB 1 : f64TIMAB 0 : fOCO-F 1 : fOCO-S 0 : fC32 1 : Do not set RW RW RW TCS7 TAj count source option specified bit 0 : TCK0, TCK1 enabled, TCS4 to TCS6 disabled 1 : TCK0, TCK1 disabled, TCS4 to TCS6 enabled RW TACS0 register: i = 0, j = 1 TACS1 register: i = 2, j = 3 Timer A Count Source Select Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol TACS2 Bit Symbol TCS0 Bit Name Address 01D2h Function b2 b1 b0 After Reset X0h RW RW TCS1 TA4 count source select bit TCS2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 : : : : : : : : f1TIMAB or f2TIMAB f8TIMAB f32TIMAB f64TIMAB fOCO-F fOCO-S fC32 Do not set RW RW TCS3 TA4 count source option specified bit 1 : TCK0 to TCK1 enabled, TCS0 to TCS2 disabled 0 : TCK0 to TCK1 disabled, TCS0 to TCS2 enabled RW — (b7-b4) No register bits. If necessary, set to 0. Read as undefined value. — TCS2-TCS0 (TAi Count Source Select Bit) (b2-b0) (i = 0, 2, 4) TCS6-TCS4 (TAj Count Source Select Bit) (b6-b4) (i = 1, 3) Select f1TIMAB or f2TIMAB by the PCLK0 bit in the PCLKR register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 290 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.2.5 16-Bit Pulse Width Modulation Mode Function Select Register (PWMFS) 16-Bit Pulse Width Modulation Mode Function Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PWMFS Bit Symbol — (b0) PWMFS1 Bit Name Address 01D4h Function After Reset 0XX0 X00Xb RW — 0 No register bit. If necessary, set to 0. Read as undefined value Timer A1 programmable output mode select bit Timer A2 programmable output mode select bit 0 : PWM mode 16-bit PWM 1 : Programmable output mode 0 : PWM mode 16-bit PWM 1 : Programmable output mode RW PWMFS2 — (b3) PWMFS4 — (b6-b5) — (b7) RW No register bit. If necessary, set to 0. Read as undefined value Timer A4 programmable output mode select bit 0 : PWM mode 16-bit PWM 1 : Programmable output mode — RW No register bits. If necessary, set to 0. Read as undefined value — Reserved bit Set to 0 RW PWMFS1 (Timer A1 Programmable Output Mode Select Bit) (b1) PWMFS2 (Timer A2 Programmable Output Mode Select Bit) (b2) PWMFS4 (Timer A4 Programmable Output Mode Select Bit) (b4) The bits are enabled when bits TMOD1 to TMOD0 in the TAiMR register are 11b (PWM mode or programmable output mode), and the MR3 bit in the TAiMR register is 0 (16-bit PWM mode). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 291 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.2.6 Timer A Waveform Output Function Select Register (TAPOFS) Timer A Waveform Output Function Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TAPOFS Bit Symbol POFS0 POFS1 POFS2 POFS3 POFS4 — (b7-b5) Bit Name Address 01D5h Function After Reset XXX0 0000b RW RW RW RW RW RW — TA0OUT output polar control bit TA1OUT output polar control bit TA2OUT output polar control bit TA3OUT output polar control bit TA4OUT output polar control bit 0 : Output waveform high-level active 1 : Output waveform high-level active (output reversed) No register bits. If necessary, set to 0. Read as undefined value REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 292 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.2.7 Timer A Output Waveform Change Enable Register (TAOW) Timer A Output Waveform Change Enable Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TAOW Bit Symbol — (b0) TA1OW Bit Name Address 01D8h Function After Reset XXX0 X00Xb RW — No register bit. If necessary, set to 0. Read as undefined value Timer A1 output waveform change enable bit Timer A2 output waveform change enable bit 0 : Change disabled 1 : Change enabled 0 : Change disabled 1 : Change enabled RW TA2OW — (b3) TA4OW — (b7-b5) RW No register bit. If necessary, set to 0. Read as undefined value Timer A4 output waveform change enable bit 0 : Change disabled 1 : Change enabled — RW No register bit. If necessary, set to 0. Read as undefined value — The TAOW register is enabled in programmable output mode. To change cycles or width of the output waveform, follow the instructions below. (1)Set the TAiOW bit to 0 (output waveform change disabled). (i = 1, 2, 4) (2)Write to the TAi register and/or the TAi1 register. (3)Set the TAiOW bit to 1 (output waveform change enabled). The updated value is reloaded when the TAiOW bit is 1 (output waveform change enabled) at one cycle before the rising edge of the TAiOUT output (the falling edge when the TOFSi bit is 1). The value before the update is reloaded when the TAiOW bit is 0 (output waveform change disabled). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 293 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.2.8 Timer Ai Register (TAi) (i = 0 to 4) Timer Ai Register (i = 0 to 4) (b15) b7 (b8) b0 b7 b0 Symbol TA0 TA1 TA2 TA3 TA4 Mode Address 0327h to 0326h 0329h to 0328h 032Bh to 032Ah 032Dh to 032Ch 032Fh to 032Eh Function When n = set value, count cycle: (n + 1) fj After Reset Undefined Undefined Undefined Undefined Undefined Setting Range RW Timer mode 0000h to FFFFh RW When n = set value, Event counter mode FFFFh - n + 1 count (at increment) n + 1 count (at decrement) When n = set value, One-shot timer mode pulse width: n fj Pulse width When n = set value, modulation mode PWM period: (216 – 1) (16-bit PWM mode) fj PWM pulse width: n fj When n = high-order address set value, m = low-order address set value, PWM period: (28 – 1) × (m + 1) fj PWM pulse width: (m + 1)n fj When n = set value of TAi1 register, m = set value of TAi register, high-level duration: m fj low-level duration: n fj 0000h to FFFFh RW 0000h to FFFFh 0000h to FFFEh WO WO Pulse width modulation mode (8-bit PWM mode) 00h to FEh (High-order address) 00h to FFh (Low-order address) WO Programmable output mode 0000h to FFFFh WO fj : Count source frequency Access the register in 16-bit units. Use the MOV instruction to write to the TAi register. Event Counter Mode The timer counts pulses from an external device, or the overflows/underflows of other timers. One-Shot Timer Mode If the TAi register is set to 0000h, the counter does not work and timer Ai interrupt requests are not generated. Furthermore, if pulse output is selected, no pulses are output from the TAiOUT pin. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 294 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A Pulse Width Modulation Mode (16-Bit PWM Mode) If the TAi register is set to 0000h, the counter does not work, the output level on the TAiOUT pin remains low, and timer Ai interrupt requests are not generated. Pulse Width Modulation Mode (8-Bit PWM Mode) This mode operates as 8-bit prescaler (eight low-order bits) and 8-bit pulse width modulator (eight highorder bits). When the eight high-order bits of the TAi register are set to 00h, the counter does not work, the output level on the TAiOUT pin remains low, and timer Ai interrupt requests are not generated. 17.2.9 Timer Ai-1 Register (TAi1) (i = 1, 2, 4) Timer Ai-1 Register (i = 1, 2, 4) (b15) b7 (b8) b0 b7 b0 Symbol TA11 TA21 TA41 Mode Address 0303h to 0302h 0305h to 0304h 0307h to 0306h Function When n = set value of TAi1 register, m = set value of TAi register, high-level duration: m fj low-level duration: n fj After Reset Undefined Undefined Undefined Setting Range RW Programmable output mode 0001h to FFFFh WO fj: Count source frequency Access the register in 16-bit units. Use the MOV instruction to write to the TAi1 register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 295 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.2.10 Count Start Flag (TABSR) Count Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Bit Symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Bit Name Address 0320h Function 0 : Stop counting 1 : Start counting After Reset 00h RW RW RW RW RW RW RW RW RW Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 296 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.2.11 One-Shot Start Flag (ONSF) One-Shot Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol ONSF Bit Symbol Address 0322h Bit Name Timer A0 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag Z-phase input enable bit 0 : Z-phase input disabled 1 : Z-phase input enabled b7 b6 After Reset 00h Function The timer starts counting by setting this bit to 1. Read as 0 RW RW RW RW RW RW RW TA0OS TA1OS TA2OS TA3OS TA4OS TAZIE TA0TGL TA0TGH 0 Timer A0 event/trigger select 0 bit 1 1 0: 1: 0: 1: Input on TA0IN pin selected Timer B2 selected Timer A4 selected Timer A1 selected RW RW i = 0 to 4 TAiOS (Timer Ai One-Shot Start Flag) (b4-b0) (i = 0 to 4) This bit is enabled in one-shot timer mode. When the MR2 bit in the TAi register is 0 (TAiOS bit enabled), the timer Ai count starts by setting the TAiOS bit to 1 after setting the TAiS bit in the TABSR register to 1 (start counting). TAZIE (Z-Phase Input Enable Bit) (b5) This bit is used in event counter mode (two-phase pulse signal processing) of timer A3. Refer to 17.3.4.3 “Counter Initialization by Two-Phase Pulse Signal Processing” for details. TA0TGH-TA0TGL (Timer A0 Event/Trigger Select Bit) (b7-b6) This bit is used to select an event or a trigger of the following modes: • An event in event counter mode (not using two-phase pulse signal processing) • A trigger in one-shot timer mode or PWM mode The above applies when the MR2 bit in the TA0MR register is 1 (trigger selected by bits TA0TGH to TA0TGL). The active edge of input signals can be selected by the MR1 bit in the TA0MR register when bits TA0TGH to TA0TGL are 00b. When bits TA0TGH to TA0TGL are set to 01b, 10b, or 11b, an event or a trigger occurs when an interrupt request of the selected timer is generated. (An event or a trigger occurs while an interrupt is disabled because bits TA0TGH to TA0TGL are not influenced by I flag, IPL, or the interrupt control registers.) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 297 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.2.12 Trigger Select Register (TRGSR) Trigger Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRGSR Bit Symbol TA1TGL TA1TGH TA2TGL TA2TGH TA3TGL TA3TGH TA4TGL TA4TGH Timer A4 event/trigger select bit Timer A3 event/trigger select bit Timer A2 event/trigger select bit Bit Name Timer A1 event/trigger select bit Address 0323h Function b1 0 0 1 1 b3 0 0 1 1 b5 0 0 1 1 b7 0 0 1 1 b0 0 : Input on TA1IN selected 1 : TB2 selected 0 : TA0 selected 1 : TA2 selected b2 0 : Input on TA2IN selected 1 : TB2 selected 0 : TA1 selected 1 : TA3 selected b4 0 : Input on TA3IN selected 1 : TB2 selected 0 : TA2 selected 1 : TA4 selected b6 0 : Input on TA4IN selected 1 : TB2 selected 0 : TA3 selected 1 : TA0 selected After Reset 00h RW RW RW RW RW RW RW RW RW TA1TGH-TA1TGL (Timer A1 Event/Trigger Select Bit) (b1-b0) TA2TGH-TA2TGL (Timer A2 Event/Trigger Select Bit) (b3-b2) TA3TGH-TA3TGL (Timer A3 Event/Trigger Select Bit) (b5-b4) TA4TGH-TA4TGL (Timer A4 Event/Trigger Select Bit) (b7-b6) These bits are used to select an event or a trigger of the following modes: • Event in event counter mode (not using two-phase pulse signal processing) • Trigger in one-shot timer mode, PWM mode, or programmable output mode The above applies when the MR2 bit in the TAiMR register is 1 (trigger selected by bits TAiTGH to TAiTGL). The active edge of input signals can be selected by the MR1 bit in the TAiMR register when bits TAiTGH to TAiTGL are 00b. When bits TAiTGH to TAiTGL are set to 01b, 10b, or 11b, an event or a trigger occurs when an interrupt request of the selected timer is generated. (An event or a trigger occurs while an interrupt is disabled because bits TAiTGH to TAiTGL are not influenced by I flag, IPL, or the interrupt control registers.) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 298 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.2.13 Up/Down Flag (UDF) Up/Down Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol UDF Bit Symbol TA0UD TA1UD TA2UD TA3UD TA4UD Bit Name Timer A0 up/down flag Timer A1 up/down flag Timer A2 up/down flag Timer A3 up/down flag Timer A4 up/down flag Timer A2 two-phase pulse signal processing select bit Timer A3 two-phase pulse signal processing select bit Timer A4 two-phase pulse signal processing select bit Address 0324h Function 0 : Decrement 1 : Increment After Reset 00h RW RW RW RW RW RW TA2P 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing enabled RW TA3P RW TA4P RW TAiUD (Timer Ai Up/Down Flag) (bi) (i = 0 to 4) Enabled in event counter mode (when not using two-phase pulse signal processing). TA2P (Timer A2 Two-Phase Pulse Signal Processing Select Bit) (b5) TA3P (Timer A3 Two-Phase Pulse Signal Processing Select Bit) (b6) TA4P (Timer A4 Two-Phase Pulse Signal Processing Select Bit) (b7) Set these bits to 0 when not using two-phase pulse signal processing. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 299 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.2.14 Timer Ai Mode Register (TAiMR) (i = 0 to 4) Timer Ai Mode Register (i= 0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TA0MR to TA4MR Bit Symbol Address 0336h to 033Ah Bit Name Function b1 b0 After Reset 00h RW RW Operation mode select bit TMOD0 TMOD1 MR0 MR1 0 0 1 1 0 : Timer mode 1 : Event counter mode 0 : One-shot timer mode 1 : Pulse width modulation (PWM) mode or programmable output mode RW RW RW Function varies with the operation mode MR2 MR3 TCK0 Count source select bit TCK1 RW RW RW RW REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 300 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.3 17.3.1 Operations Common Operations Operating Clock 17.3.1.1 The count source for each timer acts as a clock, controlling such timer operations as counting and reloading. If the conditions to start counting are met, the counter not operating starts counting at the count timing of the first count source. For this reason, a delay exists between when the count start conditions are met and the counter starts counting. Figure 17.4 shows Output Example of One-Shot Timer Mode. Count source TAiIN (trigger input) Trigger input TAiOUT (one-shot pulse output) Maximum 1.5 cycles of the count source Figure 17.4 Output Example of One-Shot Timer Mode Count start = output start 17.3.1.2 Counter Reload Timing Timer Ai starts counting from the value (n) set in the TAi register. The TAi register consists of a counter and a reload register. The counter starts decrementing the count source from n, reloads a value in the reload register at the next count source after the value becomes 0000h, and continues decrementing. (When incrementing, the counter reloads a value in the reload register at the next count source after the value becomes FFFFh.) The value written in the TAi register is reflected in the counter and the reload register at the timings below. • When the count is stopped • Between when the count starts and the first count source is input A value written to the TAi register is immediately written to the counter and the reload register. • After the count starts and the first count source is input A value written to the TAi register is immediately written to the reload register. The counter continues counting and reloads the value in the reload register at the next count source after the value becomes 0000h (or FFFFh). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 301 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.3.1.3 Count Source Internal clocks are counted in timer mode, one-shot timer mode, PWM mode, and programmable output mode. (Refer to Figure 17.1 “Timer A and B Count Sources”.) Table 17.5 lists Timer A Count Source. Timer A, B, and multi-master I2C-bus interface share the divider. f1 or fOCO-F can be selected before the timer AB divider. f1 is any of the following. Select f1 by the CM21 bit in the CM2 register and the FRA01 bit in the FRA0 register. (Refer to 8. “Clock Generator”.) • Main clock divided by 1 (no division) • PLL clock divided by 1 (no division) • fOCO-S divided by 1 (no division) • fOCO-F divided by 1 (no division) Table 17.5 Timer A Count Source Count Source f1TIMAB f2TIMAB f8TIMAB f32TIMAB f64TIMAB fOCO-F fOCO-S fC32 Bit Set Value TCS2 to TCS3 TCS0 PCLK0 TCS4 to TCS7 TCS6 1 0 1 000b 0 0 1 000b 0 1 001b 0 1 010b 1 011b - TCK1 to TCK0 00b 00b 01b 10b - Remarks f1 or fOCO-F (1) f1 divided by 2 or fOCO-F divided by 2 (1) f1 divided by 8 or fOCO-F divided by 8 (1) f1 divided by 32 or fOCO-F divided by 32 (1) f1 divided by 64 or fOCO-F divided by 64 (1) fOCO-F fOCO-S fC32 1 100b 1 101b 0 11b 1 110b PCLK0: Bit in the PCLKR register TCS7 to TCS0: Bits in registers TACS0 to TACS2 TCK1 to TCK0: Bits in the TAiMR register (i = 0 to 4) Note: 1. Select f1 or fOCO-F by the TCDIV00 bit in the TCKDIVC0 register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 302 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.3.2 Timer Mode In timer mode, the timer counts a count source generated internally. Table 17.6 lists Specifications of Timer Mode, Table 17.7 lists Registers and the Setting in Timer Mode, and Figure 17.5 shows Operation Example in Timer Mode. Table 17.6 Specifications of Timer Mode Specification f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB, f64TIMAB, fOCO-F, fOCO-S, fC32 Item Count source Count operation • Decrement • When the timer underflows, it reloads the reload register contents and continues counting. (n + 1) ----------------fj n: set value of TAi register 0000h to FFFFh Counter cycles fj: frequency of count source Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Set the TAiS bit in the TABSR register to 1 (start counting). Set the TAiS bit to 0 (stop counting). Timer underflow I/O port or gate input I/O port or pulse output Count value can be read by reading the TAi register. • When not counting Value written to the TAi register is written to both reload register and counter. • When counting Value written to the TAi register is written to only reload register (transferred to counter when reloaded next). Selectable functions • Gate function Counting can be started and stopped by an input signal to the TAiIN pin. • Pulse output function Whenever the timer underflows, the output polarity of the TAiOUT pin is inverted. When the TAiS bit is set to 0 (stop counting), the pin outputs a low-level signal. • Output polarity control While the output polarity of the TAiOUT pin is inverted (the TAiS bit is set to 0 (stop counting)), the pin outputs a high-level signal. i = 0 to 4 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 303 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A Table 17.7 Registers and the Setting in Timer Mode (1) Register PCLKR CPSRF TCKDIVC0 PWMFS TACS0 to TACS2 TAPOFS TAi1 TABSR ONSF Bit PCLK0 CPSR TCDIV00 PWMFSi 7 to 0 POFSi Setting TRGSR UDF TAi TAiMR i = 0 to 4 Note: 1. This table does not describe a procedure. Select the count source. Write a 1 to reset the clock prescaler. Select a clock used prior to timer AB frequency dividing. Set to 0. Select the count source. Select the output polarity when the MR0 bit in the TAiMR register is 1 (pulse output). 7 to 0 - (does not need to be set) TAiS Set to 1 when starting counting. Set to 0 when stopping counting. TAiOS Set to 0. TAZIE Set to 0. TAiTGH to TAiTGL Set to 00b. TAiTGH to TAiTGL Set to 00b. TAiUD Set to 0. TAiP Set to 0. 7 to 0 Set the counter value. 7 to 0 Refer to the following TAiMR register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 304 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A Timer Mode Timer Ai Mode Register (i = 0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TA0MR to TA4MR Bit Symbol TMOD0 Operation mode select bit TMOD1 Bit Name Address 0336h to 033Ah Function After Reset 00h RW RW RW 0 00 b1 b0 0 0 : Timer mode MR0 Pulse output function select bit 0 : No pulse output (TAiOUT pin functions as I/O port) 1 : Pulse output (TAiOUT pin functions as a pulse output pin) b4 b3 RW MR1 Gate function select bit MR2 MR3 TCK0 Count source select bit TCK1 Set to 0 in timer mode 0 0 1 1 0: Gate function not available 1: (TAiIN pin functions as I/O port) 0 : Counts while input on the TAiIN pin is low 1 : Counts while input on the TAiIN pin is high RW RW RW b1 b0 0 0 1 1 0 : f1TIMAB or f2TIMAB 1 : f8TIMAB 0 : f32TIMAB 1 : fC32 RW TCK1-TCK0 (Count Source Select Bit) (b7-b6) Valid when the TCS3 bit or TCS7 bit in registers TACS0 to TACS2 is set to 0 (TCK0 to TCK1 enabled). Select f1TIMAB or f2TIMAB by the PCLK0 bit in the PCLKR register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 305 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A Count source Count stop by TAiIN gate function n Count operations Count start Count stop by TAiS bit 0000h Underflow reload TAiS bit in TABSR register TAiIN input TAiOUT output POFSi = 0 POFSi = 1 IR bit in TAiIC register High-level output at count stop n+1 Low-level output at count stop Output reversed at underflow Low-level output when the TAiS bit is 0. High-level output when the TAiS bit is 0. Output reversed at underflow Set to 0 by an interrupt request acknowledgement or by a program. i = 0 to 4 POFSi : Bits in the TAPOFS register The above timing diagram applies when the register bits are set as follows: - The MR0 bit in the TAiMR register = 1 (pulse output) - Bits MR2 to MR1 in the TAiMR register = 10b (counts while a low-level signal is applied to the TAiIN pin) - Value in the TAi register (n) = 0004h Figure 17.5 Operation Example in Timer Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 306 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.3.3 Event Counter Mode (When Not Processing Two-Phase Pulse Signal) In event counter mode, the timer counts pulses from an external device, or overflows/underflows of other timers. Timers A2, A3, and A4 can count two-phase external signals (refer to 17.3.4 “Event Counter Mode (When Processing Two-Phase Pulse Signal)”). Table 17.8 lists Specifications in Event Counter Mode (When Not Processing Two-Phase Pulse Signal). Table 17.9 lists Registers and the Setting in Event Counter Mode (When Not Processing Two-Phase Pulse Signal). Figure 17.6 shows Operation Example in Event Counter Mode. Table 17.8 Specifications in Event Counter Mode (When Not Processing Two-Phase Pulse Signal) Item Count source Specification • External signals input to the TAiIN pin (active edge can be selected by a program) Count operations • Timer B2 overflows or underflows • Timer Aj overflows or underflows (j = i - 1, except j = 4 if i = 0) • Timer Ak overflows or underflows (k = i + 1, except k=0 if i = 4) • Increment or decrement can be selected by a program. • When the timer overflows or underflows, it reloads the reload register contents and continues counting. When operating in free-running mode, the timer continues counting without reloading. • FFFFh - n + 1 for increment • n + 1 for decrement n: set value of the TAi register 0000h to FFFFh Set the TAiS bit in the TABSR register to 1 (start counting). Set the TAiS bit to 0 (stop counting). Timer overflow or underflow I/O port or count source input I/O port or pulse output Count value can be read by reading the TAi register. • When not counting Value written to the TAi register is written to both reload register and counter. • When counting Value written to the TAi register is written to only reload register (transferred to counter when reloaded next). • Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded. • Pulse output function Whenever the timer underflows or underflows, the output polarity of the TAiOUT pin is inverted. When the TAiS bit is set to 0 (stop counting), the pin outputs a low-level signal. • Output polarity control While the output polarity of the TAiOUT pin is inverted (the TAiS bit is set to 0 (stop counting)), the pin outputs a high-level signal. Number of counts Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Selectable functions i = 0 to 4 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 307 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A Table 17.9 Registers and the Setting in Event Counter Mode (When Not Processing Two-Phase Pulse Signal) (1) Register PCLKR CPSRF TCKDIVC0 PWMFS TACS0 to TACS2 TAPOFS TAi1 TABSR ONSF Bit PCLK0 CPSR TCDIV00 PWMFSi 7 to 0 POFSi Setting TRGSR UDF TAi TAiMR i = 0 to 4 Note: 1. This table does not describe a procedure. Set to 1. Write a 1 to reset the clock prescaler. Set to 0. Set to 0. Set to 00b. Select the output polarity when the MR0 bit in the TAiMR register is 1 (pulse output). 7 to 0 - (setting unnecessary) TAiS Set to 1 when starting counting. Set to 0 when stopping counting. TAiOS Set to 0. TAZIE Set to 0. TAiTGH to TAiTGL Select a count source. TAiTGH to TAiTGL Select a count source. TAiUD Select a count operation. TAiP Set to 0. 7 to 0 Set the counter value. 7 to 0 Refer to the following TAiMR register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 308 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A Event Counter Mode (When Not Using Two-Phase Pulse Signal Processing) Timer Ai Mode Register (i = 0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TA0MR to TA4MR Bit Symbol TMOD0 TMOD1 Bit Name Address 0336h to 033Ah Function b1 b0 After Reset 00h RW RW RW 00 01 Operation mode select bit 0 1 : Event counter mode MR0 Pulse output function select bit 0 : Pulse is not output (TAiOUT pin functions as I/O port) 1 : Pulse is output (TAiOUT pin functions as pulse output pin) 0 : Counts falling edge of external signal 1 : Counts rising edge of external signal RW MR1 MR2 MR3 TCK0 TCK1 Count polarity select bit RW RW RW RW RW Set to 0 in event counter mode Set to 0 in event counter mode Count operation type select bit 0 : Reload type 1 : Free-run type Can be 0 or 1 when not using two-phase pulse signal processing MR1 (Count Polarity Select Bit) (b3) Valid when bits TAiTGH to TAiTGL in the ONSF or TRGSR register are 00b (TAiIN pin input). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 309 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A TAiIN input Overflow reload FFFFh Decrement Count operations n Count start 0000h n+1 TAiS bit in TABSR register TAiUD bit in UDF register TAiOUT output POFSi = 0 POFSi = 1 Low-level output at count stop High-level output at count stop Underflow reload Increment FFFFh-n+1 Count stop Output reversed at underflow or overflow Low-level output at count stop High-level output at count stop IR bit in TAiIC register Set to 0 by an interrupt request acknowledgement or by a program. i = 0 to 4 POFSi: Bits in the TAPOFS register The above timing diagram applies when the register bits are set as follows: - Bits TAiTGH to TAiTGL in the ONSF or TRGSR register = 00b - The MR1 bit in the TAiMR register =0 - The MR0 bit in the TAiMR register = 1 (pulse output) - The TCK0 bit in the TAiMR register = 0 (reload type) (The falling edge of the TAiIN pin input is counted.) Figure 17.6 Operation Example in Event Counter Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 310 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.3.4 Event Counter Mode (When Processing Two-Phase Pulse Signal) Timers A2, A3, and A4 can be used to count two-phase pulse signals. Table 17.10 lists Specifications of Event Counter Mode (When Processing Two-Phase Pulse Signal with Timers A2, A3, and A4). Table 17.11 lists Registers and the Setting in Event Counter Mode (When Processing Two-Phase Pulse Signal). Table 17.10 Specifications of Event Counter Mode (When Processing Two-Phase Pulse Signal with Timers A2, A3, and A4) Item Count source Count operations Number of counts Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Specification Two-phase pulse signals input to the TAiIN or TAiOUT pin • Increment or decrement can be selected by a two-phase pulse signal. • When the timer overflows or underflows, it reloads the reload register contents and continues counting. When operating in free-running mode, the timer continues counting without reloading. • FFFFh - n + 1 for increment • n + 1 for decrement n: set value of the TAi register 0000h to FFFFh Set the TAiS bit in the TABSR register to 1 (start counting). Set the TAiS bit to 0 (stop counting). Timer overflow or underflow Two-phase pulse input Two-phase pulse input Count value can be read by reading timer A2, A3, or A4 register. • When not counting Value written to the TAi register is written to both reload register and counter. • When counting Value written to the TAi register is written to only reload register (transferred to counter when reloaded next). • Select normal or multiply-by-4 processing operation (timer A3). • Counter initialization by Z-phase input (timer A3) The timer count value is initialized to 0 by Z-phase input. Selectable functions i = 2 to 4 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 311 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A Table 17.11 Registers and the Setting in Event Counter Mode (When Processing Two-Phase Pulse Signal) (1) Register PCLKR CPSRF TCKDIVC0 PWMFS TACS0 to TACS2 TAPOFS TAi1 TABSR ONSF Bit PCLK0 CPSR TCDIV00 PWMFSi 7 to 0 POFSi 7 to 0 TAiS Setting TRGSR UDF TAi TAiMR i = 2 to 4 Note: 1. This table does not describe a procedure. Set to 1. Write a 1 to reset the clock prescaler. Set to 0. Set to 0. Set to 00b. Set to 0. - (setting unnecessary) Set to 1 when starting counting. Set to 0 when stopping counting. TAiOS Set to 0. TAZIE Set to 1 when using Z-phase input at timer A3. TAiTGH to TAiTGL Set to 00b. TAiTGH to TAiTGL Set to 00b. TAiUD Set to 0. TAiP Set to 1. 7 to 0 Set the counter value. 7 to 0 Refer to the following TAiMR register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 312 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A Event Counter Mode (When Using Two-Phase Pulse Signal Processing) Timer Ai Mode Register (i = 2 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TA2MR to TA4MR Bit Symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 Bit Name Address 0338h to 033Ah Function b1 b0 After Reset 00h RW RW RW 010001 Operation mode select bit 0 1 : Event counter mode Set to 0 to use two-phase signal processing Set to 0 to use two-phase signal processing Set to 1 to use two-phase signal processing Set to 0 to use two-phase signal processing Count operation type select bit 0 : Reload type 1 : Free-run type RW RW RW RW RW TCK1 Two-phase pulse signal 0 : Normal processing operation processing operation type 1 : Multiply-by-4 processing operation select bit RW TCK1 (Two-Phase Pulse Signal Processing Operation Type Select Bit) (b7) The TCK1 bit can be set only for timer A3 mode register. No matter how this bit is set, timers A2 and A4 always operate in normal processing mode and multiply-by-4 processing mode, respectively. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 313 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.3.4.1 Normal Processing The timer increments rising edges or decrements falling edges on the TAjIN pin when input signals on the TAjOUT (j = 2, 3) pin is high level. Figure 17.7 shows Normal Processing. TAjOUT TAjIN Increment Increment Increment Decrement Decrement Decrement j = 2, 3 Figure 17.7 Normal Processing 17.3.4.2 Multiply-by-4 Processing If the phase relationship is such that TAkIN pin goes high when the input signal on the TAkOUT pin (k = 3, 4) is high, the timer increments rising and falling edges on pins TAkOUT and TAkIN. If the phase relationship is such that the TAkIN pin goes low when the input signal on the TAkOUT pin is high, the timer decrements rising and falling edges on pins TAkOUT and TAkIN. Figure 17.8 shows Multiply-by-4 Processing. TAkOUT Increment all edges TAkIN Decrement all edges Increment all edges k = 3, 4 Figure 17.8 Multiply-by-4 Processing Decrement all edges REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 314 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.3.4.3 Counter Initialization by Two-Phase Pulse Signal Processing This function initializes the timer count value to 0000h by Z-phase (counter initialization) input during two-phase pulse signal processing. This function can only be used in timer A3 event counter mode during two-phase pulse signal processing, free-running type, multiply-by-4 processing, with Z-phase entered from the ZP pin. Counter initialization by Z-phase input is enabled by writing 0000h to the TA3 register and setting the TAZIE bit in the ONSF register to 1 (Z-phase input enabled). Counter initialization is accomplished by Z-phase input edge detection. The rising or falling edge can be selected as the active edge by using the POL bit in the INT2IC register. The Z-phase pulse width applied to the ZP pin must be equal to or greater than one clock cycle of timer A3 count source. The counter is initialized at the next count timing after recognizing Z-phase input. Figure 17.9 shows the Relationship between the Two-Phase Pulse (A-Phase and B-Phase) and the Z-Phase. If timer A3 overflow or underflow coincides with counter initialization by Z-phase input, a timer A3 interrupt request is generated twice in succession. Do not use the timer A3 interrupt when using this function. TA3OUT (A phase) TA3IN (B phase) Count source ZP (1) Input equal to or greater than one clock cycle of count source Timer A3 m m+1 1 2 3 4 5 Note : 1. This timing diagram applies when the POL bit in the INT2IC register is 1 (rising edge). Figure 17.9 Relationship between the Two-Phase Pulse (A-Phase and B-Phase) and the Z-Phase REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 315 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.3.5 One-Shot Timer Mode In one-shot timer mode, the timer is activated only once by one trigger. When the trigger occurs, the timer starts and continues operating for a given period. Table 17.12 lists Specifications of One-Shot Timer Mode. Table 17.13 lists Registers and the Setting in One-Shot Timer Mode. Figure 17.10 shows Operation Example in One-Shot Timer Mode. Table 17.12 Specifications of One-Shot Timer Mode Item Count source Count operations Specification f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB, f64TIMAB, fOCO-F, fOCO-S, fC32 • Decrement • When the counter reaches 0000h, it stops counting after reloading a new value. • When a trigger occurs while counting, the timer reloads a new value and restarts counting. n -fj n Pulse width n: Count start condition set value of the TAi register 0000h to FFFFh However, the counter does not work if 0000h is set. fj: count source frequency The TAiS bit in the TABSR register is 1 (start counting) and one of the following triggers occurs: • External trigger input from the TAiIN pin • Timer B2 overflow or underflow • Timer Aj overflow or underflow (j = i - 1, except j = 4 if i = 0) • Timer Ak overflow or underflow (k = i + 1, except k = 0 if i = 4) • The TAiOS bit in the ONSF register is set to 1 (timer starts). Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer • When the counter is reloaded after reaching 0000h • The TAiS bit is set to 0 (stop counting) When the counter reaches 0000h I/O port or trigger input I/O port or pulse output An undefined value is read by reading the TAi register. • When not counting and until the first count source is input after counting starts, the value written to the TAi register is written to both reload register and counter. • When counting (after first count source input), the value written to the TAi register is written to only the reload register (transferred to the counter when reloaded next). • Pulse output function The timer outputs a low-level signal when not counting and a high-level signal when counting. • Output polarity control The output polarity of TAiOUT pin is inverted. (While the TAiS bit is set to 0 (stop counting), the pin outputs a high-level signal.) Selectable functions i = 0 to 4 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 316 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A Table 17.13 Registers and the Setting in One-Shot Timer Mode (1) Register PCLKR CPSRF TCKDIVC0 PWMFS TACS0 to TACS2 TAPOFS TAi1 TABSR ONSF Bit PCLK0 CPSR TCDIV00 PWMFSi 7 to 0 POFSi Setting TRGSR UDF TAi Select the count source. Write a 1 to reset the clock prescaler. Select a clock used prior to timer AB frequency dividing. Set to 0. Select the count source. Select the output polarity when the MR0 bit in the TAiMR register is 1 (pulse output). 7 to 0 - (setting unnecessary) TAiS Set to 1 when starting counting. Set to 0 when stopping counting. TAiOS Set to 1 when starting counting while the MR2 bit is 0. TAZIE Set to 0. TAiTGH to TAiTGL Select a count trigger. TAiTGH to TAiTGL Select a count trigger. TAiUD Set to 0. TAiP Set to 0. 7 to 0 Set a high-level pulse width. (2) TAiMR 7 to 0 Refer to the following TAiMR register. i = 0 to 4 Notes: 1. This table does not describe a procedure. 2. This applies when the POFSi bit in the TAPOFS register is 0. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 317 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A One-Shot Timer Mode Timer Ai Mode Register (i = 0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TA0MR to TA4MR Bit Symbol TMOD0 Operation mode select bit TMOD1 Bit Name Address 0336h to 033Ah Function b1 b0 After Reset 00h RW RW RW 0 10 1 0 : One-shot timer mode MR0 Pulse output function select bit 0 : No pulse output (TAiOUT pin functions as I/O port) 1 : Pulse output (TAiOUT pin functions as a pulse output pin) 0 : Falling edge of input signal to TAiIN pin 1 : Rising edge of input signal to TAiIN pin 0 : TAiOS bit enabled 1 : Selected by bits TAiTGH and TAiTGL RW MR1 External trigger select bit Trigger select bit RW MR2 MR3 TCK0 RW RW Set to 0 in one-shot timer mode b7 b6 Count source select bit TCK1 0 0 1 1 0 : f1TIMAB or f2TIMAB 1 : f8TIMAB 0 : f32TIMAB 1 : fC32 RW MR1 (External Trigger Select Bit) (b3) Valid when the MR2 bit is set to 1 and bits TAiTGH to TAiTGL in the ONSF register or TRGSR register are set to 00b (TAiIN pin input). TCK1-TCK0 (Count Source Select Bit) (b7-b6) Valid when the TCS3 bit or TCS7 bit in registers TACS0 to TACS2 is set to 0 (TCK0 to TCK1 enabled). Select f1TIMAB or f2TIMAB by the PCLK0 bit in the PCLKR register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 318 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A Count source Count starts with a maximum of a 1.5 cycle delay of the count source after an external trigger. Reload n Count operations Reload and stop counting 0000h n Reload and stop counting when 0000h is set. After re-trigger, n+1 Re-trigger while counting TAiS bit in TABSR register Trigger TAiIN input TAiOUT output POFSi = 0 POFSi = 1 Low-level output at count stop High-level output at count start High-level output at count stop Low-level output at count start IR bit in TAiIC register Low-level output at count stop High-level output at count stop Interrupt request at the falling edge of TAiOUT when POFSi is 0 Interrupt request at the rising edge of TAiOUT when POFSi is 1 Low-level output at count stop High-level output at count stop One cycle of the CPU clock Set to 0 by an interrupt request acknowledgement or by a program. i = 0 to 4 POFSi : Bits in the TAPOFS register The above timing diagram applies when the register bits are set as follows: - The MR0 bit in the TAiMR register = 1 (pulse output) - The MR1 bit in the TAiMR register =1 (The rising edge of the TAiIN pin input is the trigger.) - The MR2 bit in the TAiMR register =1 - Bits TAiTGH to TAiTGL in the ONSF or TRGSR register = 00b - Value in the TAi register (n) = 0005h Figure 17.10 Operation Example in One-Shot Timer Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 319 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.3.6 Pulse Width Modulation (PWM) Mode In PWM mode, the timer outputs pulses of a given width in succession. The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Table 17.14 lists Specifications of PWM Mode. Table 17.15 lists Registers and the Setting in PWM Mode. Figure 17.11 and Figure 17.12 show Operation Example in 16-Bit Pulse Width Modulation Mode and Operation Example in 8-Bit Pulse Width Modulation Mode, respectively. Table 17.14 Specifications of PWM Mode Item Count source Count operations Specification f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB, f64TIMAB, fOCO-F, fOCO-S, fC32 • Decrement (operating as an 8-bit or a 16-bit pulse width modulator) • The timer reloads a new value at a rising edge of PWM pulse and continues counting. • The timer is not affected by a trigger that occurs during counting. -• Pulse width n fj 16-bit PWM n 216 - 1 16 (2 – 1) • Cycle time ---------------------- fj n: set value of the TAi register fj: count source frequency 8-bit PWM ---------------------------• Pulse width n × ( m + 1 ) fj n × (m + 1) (28 - 1) × (m + 1) • Cycle time (2 – 1) × (m + 1) --------------------------------------------fj m: set value of the TAi register low-order address n: set value of the TAi register high-order address fj: count source frequency 8 Count start condition • The TAiS bit of the TABSR register is set to 1 (start counting). • The TAiS bit is 1 and external trigger input from the TAiIN pin • The TAiS bit is 1 and one of the following external triggers occurs Timer B2 overflow or underflow Timer Aj overflow or underflow (j = i - 1, except j = 4 if i = 0) Timer Ak overflow or underflow (k = i + 1, except k = 0 if i = 4) The TAiS bit is set to 0 (stop counting). On the falling edge of the PWM pulse I/O port or trigger input Pulse output An indeterminate value is read by reading the TAi register. Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer • When not counting Value written to the TAi register is written to both reload register and counter. • When counting Value written to the TAi register is written to only reload register (transferred to counter when reloaded next). Selectable functions • Output polarity control The output polarity of TAiOUT pin is inverted. (While the TAiS bit is set to 0 (stop counting), the pin outputs a high-level signal.) i = 0 to 4 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 320 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A Table 17.15 Registers and the Setting in PWM Mode (1) Register PCLKR CPSRF TCKDIVC0 PWMFS TACS0 to TACS2 TAPOFS TAi1 TABSR ONSF Bit PCLK0 CPSR TCDIV00 PWMFSi 7 to 0 POFSi 7 to 0 TAiS Setting TRGSR UDF TAi TAiMR i = 0 to 4 Note: 1. This table does not describe a procedure. Select the count source. Write a 1 to reset the clock prescaler. Select a clock used prior to timer AB frequency dividing. Set to 0. Select the count source. Select the output polarity. - (setting unnecessary) Set to 1 when starting counting. Set to 0 when stopping counting. TAiOS Set to 0. TAZIE Set to 0. TAiTGH to TAiTGL Select a count trigger. TAiTGH to TAiTGL Select a count trigger. TAiUD Set to 0. TAiP Set to 0. 7 to 0 Select the pulse width and cycles. 7 to 0 Refer to the following TAiMR register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 321 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A Pulse Width Modulation (PWM) Mode Timer Ai Mode Register (i = 0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TA0MR to TA4MR Bit Symbol TMOD0 TMOD1 Bit Name Address 0336h to 033Ah Function After Reset 00h RW RW RW 11 Operation mode select bit b1 b0 1 1 : PWM mode or programmable output mode 0 : No pulse output (TAiOUT pin functions as I/O port) 1 : Pulse output (TAiOUT pin functions as a pulse output pin) 0 : Falling edge of input signal to TAiIN pin 1 : Rising edge of input signal to TAiIN pin 0 : Write 1 to the TAiS bit in the TABSR register 1 : Selected by bits TAiTGH to TAiTGL 0 : 16-bit PWM mode 1 : 8-bit PWM mode b7 b6 MR0 Pulse output function select bit RW MR1 External trigger select bit Trigger select bit 16/8-bit PWM mode select bit RW MR2 RW MR3 TCK0 RW Count source select bit TCK1 0 0 1 1 0 : f1TIMAB or f2TIMAB 1 : f8TIMAB 0 : f32TIMAB 1 : fC32 RW MR1 (External Trigger Select Bit) (b3) Valid when the MR2 bit is set to 1 and bits TAiTGH to TAiTGL in the ONSF register or TRGSR register are set to 00b (TAiIN pin input). TCK1-TCK0 (Count Source Select Bit) (b7-b6) Valid when the TCS3 bit or TCS7 bit in registers TACS0 to TACS2 is set to 0 (TCK0 to TCK1 enabled). Select f1TIMAB or f2TIMAB by the PCLK0 bit in the PCLKR register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 322 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 65535 65535 65535 Reload count start when a value except 0000h is written. 65535-n Count start n 0000h n TAiS bit in TABSR register TAiIN input Low-level output at count stop TAiOUT output POFSi = 0 High-level output at count stop 65535-n Write 0000h in the TAi register during this period. Reload 0000h and stop counting. Count stop Set to 0 by a program Count stop Low-level output at count stop Cannot be a re-trigger after count start POFSi = 1 n fj 65535 fj Interrupt request generated - when TAiOUT changes state from high to low while POFSi is 0. - when TAiOUT changes state from low to high while POFSi is 1. No intrrupt request Interrupt request generated - When TAiOUT changes state from high to low while POFSi is 0. - When TAiOUT changes state from low to high while POFSi is 1. (The IR bit does not change when output has no change.) IR bit in TAiIC register Set to 0 by an interrupt request acknowledgement or by a program. i = 0 to 4 The above timing diagram applies when the register bits are set as follows: - The MR0 bit in the TAiMR register = 1 (pulse output) - The MR3 bit in the TAiMR register = 0 (16-bit PWM mode) - The MR1 bit in the TAiMR register = 1 (The rising edge of the TAiIN pin input is the trigger.) - The MR2 bit in the TAiMR register = 1 - Bits TAiTGH to TAiTGL in the ONSF or TRGSR register = 00b 15 TAi register n 0 Operates as 16-bit pulse width modulator fj: Count source frequency Figure 17.11 Operation Example in 16-Bit Pulse Width Modulation Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 323 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A Count start m Count operations 0000h of low-order bits 255-n n Count operations of high-order bits 0000h n+1 n 255 255-n m+1 Count start TAiS bit in TABSR register TAiOUT output POFSi = 0 POFSi = 1 (n+1)(m+1) fj n(m+1) fj 255(m+1) fj n(m+1) fj 255(m+1) fj Low-level output immediately after count start IR bit in TAiIC register Set to 0 by an interrupt request acknowledgement or by a program. i = 0 to 4 POFSi: Bits in the TAPOFS register The above timing diagram applies when the register bits are set as follows: - The MR0 bit in the TAiMR register = 1 (pulse output) - The MR2 bit in the TAiMR register = 0 (The TAiS bit in the TABSR is a trigger.) - The MR3 bit in the TAiMR register = 1 (8-bit PWM mode) 15 TAi register n Operates as 8-bit pulse width modulator 87 m Operates as a prescaler 0 n = 03h m = 02h fj: Count source frequency Figure 17.12 Operation Example in 8-Bit Pulse Width Modulation Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 324 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.3.7 Programmable Output Mode (Timers A1, A2, and A4) In programmable output mode, the timer outputs low- and high-levels of pulse width successively. Table 17.16 lists Specifications of Programmable Output Mode. Table 17.17 lists Registers and the Setting in Programmable Output Mode. Figure 17.13 shows Operation Example in Programmable Output Mode. Table 17.16 Specifications of Programmable Output Mode Item Count source Count operations Specification f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB, f64TIMAB, fOCO-F, fOCO-S, fC32 • Decrement • Reloads on the rising edge of pulse and continues counting • When a trigger occurs while counting, the timer reloads a new value and restarts counting. ---• High-level pulse width m fj Pulse width m n -• Low-level pulse width n fj Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer m: set value of the TAi register n: set value of the TAi1 register fj: count source frequency • The TAiS bit of the TABSR register is set to 1 (start counting). • The TAiS bit is 1 and external trigger input from the TAiIN pin • The TAiS bit is 1 and one of the following external triggers occurs Timer B2 overflow or underflow Timer Aj overflow or underflow (j = i - 1) Timer Ak overflow or underflow (k = i + 1, except k = 0 if i = 4) The TAiS bit is set to 0 (stop counting). At the rising edge of pulse I/O port or trigger input Pulse output An undefined value is read by reading registers TAi and TAi1. • When writing to registers TAi and TAi1 while not counting, the value is written to both reload register and counter. • When writing to registers TAi and TAi1 while counting, the value is written to the reload register. (transferred to the counter when reloaded next). Output polarity control The output polarity of TAiOUT pin is inverted. (While the TAiS bit is set to 0 (stop counting), the pin outputs a high-level signal.) Selectable functions i = 1, 2, and 4 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 325 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A Table 17.17 Registers and the Setting in Programmable Output Mode (1) Register PCLKR CPSRF TCKDIVC0 PWMFS TACS0 to TACS2 TAPOFS TAi1 TABSR ONSF Bit PCLK0 CPSR TCDIV00 PWMFSi 7 to 0 POFSi 7 to 0 Setting Select the count source. Write a 1 to reset the clock prescaler. Select a clock used prior to timer AB frequency dividing. Set to 1. Select the count source. Select the output polarity. TRGSR UDF TAi Set a low-level pulse width. (2) TAiS Set to 1 when starting counting. Set to 0 when stopping counting. TAiOS Set to 0. TAZIE Set to 0. TAiTGH to TAiTGL Select a count trigger. TAiTGH to TAiTGL Select a count trigger. TAiUD Set to 0. TAiP Set to 0. 7 to 0 Set a high-level pulse width. (2) TAiMR 7 to 0 Refer to the following TAiMR register. i = 1, 2, and 4 Notes: 1. This table does not describe a procedure. 2. This applies when the POFSi bit in the TAPOFS register is 0. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 326 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A Programmable Output Mode Timer Ai Mode Register (i = 1, 2, 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TA0MR to TA4MR Bit Symbol TMOD0 Operation mode select bit TMOD1 Bit Name Address 0336h to 033Ah Function After Reset 00h RW RW RW 11 b1 b0 1 1 : PWM mode or programmable output mode MR0 Pulse output function select bit External trigger select bit Trigger select bit 0 : No pulse output (TAiOUT pin functions as I/O port) 1 : Pulse output (TAiOUT pin functions as a pulse output pin) 0 : Falling edge of input signal to TAiIN pin 1 : Rising edge of input signal to TAiIN pin 0 : Write 1 to the TAiS bit in the TABSR register 1 : Selected by bits TAiTGH to TAiTGL RW MR1 RW MR2 MR3 TCK0 RW RW Set to 0 in programmable output mode b1 b0 Count source select bit TCK1 0 0 1 1 0 : f1TIMAB or f2TIMAB 1 : f8TIMAB 0 : f32TIMAB 1 : fC32 RW MR1 (External Trigger Select Bit) (b3) Valid when bits TAiTGH to TAiTGL in the ONSF register or TRGSR register are set to 00b (TAiIN pin input). TCK1-TCK0 (Count Source Select Bit) (b7-b6) Valid when the TCS3 bit or TCS7 bit in registers TACS0 to TACS2 is set to 0 (TCK0 to TCK1 enabled). Select f1TIMAB or f2TIMAB by the PCLK0 bit in the PCLKR register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 327 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A m2 n1 Count start m1 0000h m1 TAiS bit in TABSR register TAiIN input TAiOW bit in TAOW register TAi register TAi1 register Set to 0 by a program Update a value by a program m1 n1 Set to 1 by a program m2 n2 Do not change the output waveform during this period. (When reloading, use the value before updated.) TAiOUT output POFSi = 0 n1 Update registers TAi and TAi1 during this period. Count the updated value. Count stop Set to 0 by a program Count stop Cannot be a re-trigger after count start Low-level output at count stop POFSi = 1 m1 fj n1 fj Interrupt request generated - when TAiOUT changes state from high to low while POFSi is 0. - when TAiOUT changes state from low to high while POFSi is 1. IR bit in TAiIC register Interrupt request generated - when TAiOUT changes state from high to low while POFSi is 0. - when TAiOUT changes state from low to high while POFSi is 1. (The IR bit does not change when output has no change.) Set to 0 by an interrupt request acknowledgement or by a program. i = 1, 2, 4 The above timing diagram applies when the register bits are set as follows: - The MR0 bit in the TAiMR register = 1 (pulse output) - The MR1 bit in the TAiMR register = 1 The rising edge of the TAiIN pin input is the trigger. - The MR2 bit in the TAiMR register = 1 - Bits TAiTGH to TAiTGL in the ONSF or TRGSR register = 00b fj: Count source frequency POFSi: Bits in the TAPOFS register Figure 17.13 Operation Example in Programmable Output Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 328 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.4 Interrupts Refer to individual operation examples for interrupt request generating timing. Refer to 14.7 “Interrupt Control” for details of interrupt control. Table 17.18 lists Timer A Interrupt Related Registers. Table 17.18 Timer A Interrupt Related Registers Address 0055h 0056h 0057h 0058h 0059h Register Name Timer A0 Interrupt Control Register Timer A1 Interrupt Control Register Timer A2 Interrupt Control Register Timer A3 Interrupt Control Register Timer A4 Interrupt Control Register Register Symbol TA0IC TA1IC TA2IC TA3IC TA4IC After Reset XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b The IR bit in the TAiIC register may become 1 (interrupt requested) when the TMOD1 bit in the TAiMR register is changed from 0 to 1 (change from timer mode or event counter mode to one-shot timer mode, PWM mode, or programmable output mode). Make sure to follow the procedure below when setting the TMOD1 bit to 1. Refer to 14.13 “Notes on Interrupts” as well. (1)Set bits ILVL2 to ILVL0 in the TAiIC register to 000b (interrupt disabled). (2)Set the TAiMR register. (3)Set the IR bit in the TAiIC register to 0 (interrupt not requested). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 329 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.5 17.5.1 Notes on Timer A Timer A (Timer Mode) Register Setting 17.5.1.1 The timer stops after reset. Set the mode, count source, counter value, etc., using registers TAiMR, TAi, TACS0 to TACS2, TAPOFS, TCKDIVC0, and PCLKR before setting the TAiS bit in the TABSR register to 1 (count starts) (i = 0 to 4). Always make sure registers TAiMR, TACS0 to TACS2, TAPOFS, TCKDIVC0, and PCLKR are modified while the TAiS bit is 0 (count stops), regardless of whether after reset or not. 17.5.1.2 Read from Timer While counting is in progress, the counter value can be read at any time by reading the TAi register. However, if the counter is read at the same time as it is reloaded, the value FFFFh is read. Also, if the counter is read before it starts counting and after a value is set in the TAi register while not counting, the set value is read. 17.5.1.3 Influence of SD If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is 1 (threephase output forcible cutoff by input on the SD pin enabled), pins TA1OUT, TA2OUT, and TA4OUT go to the high-impedance state. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 330 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.5.2 17.5.2.1 Timer A (Event Counter Mode) Register Setting The timer is stopped after reset. Set the mode, count source, counter value, etc., using the TAiMR register, the TAi register, the UDF register, bits TAZIE, TA0TGL, and TA0TGH in the ONSF register, the TRGSR register, and the TAPOFS register before setting the TAiS bit in the TABSR register to 1 (count starts) (i = 0 to 4). Always make sure the TAiMR register, the UDF register, bits TAZIE, TA0TGL, and TA0TGH in the ONSF register, the TRGSR register, and the TAPOFS register are modified while the TAiS bit is 0 (count stops), regardless of whether after reset or not. 17.5.2.2 Read from Timer While counting is in progress, the counter value can be read at any time by reading the TAi register. However, while reloading, FFFFh can be read in underflow, and 0000h in overflow. When the counter is read before it starts counting and after a value is set in the TAi register while not counting, the set value is read. 17.5.2.3 Influence of SD If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is 1 (threephase output forcible cutoff by input on SD pin enabled), pins TA1OUT, TA2OUT, and TA4OUT go to the high-impedance state. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 331 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.5.3 17.5.3.1 Timer A (One-Shot Timer Mode) Register Setting The timer is stopped after reset. Set the mode, count source, counter value, etc., using the TAiMR register, the TAi register, bits TA0TGL and TA0TGH in the ONSF register, the TRGSR register, registers TACS0 to TACS2, the TAPOFS register, the TCKDIVC0 register, and the PCLKR register before setting the TAiS bit in the TABSR register to 1 (count starts) (i = 0 to 4). Always make sure the TAiMR register, bits TA0TGL and TA0TGH in the ONSF register, the TRGSR register, registers TACS0 to TACS2, the TAPOFS register, the TCKDIVC0 register, and the PCLKR register are modified while the TAiS bit is 0 (count stops), regardless of whether after reset or not. 17.5.3.2 Stop While Counting When setting the TAiS bit to 0 (count stops), the following occurs: • The counter stops counting and the contents of the reload register are reloaded. • The TAiOUT pin outputs a low-level signal when the POFSi bit in the TAPOFS register is 0 and outputs a high-level signal when it is 1. • After one cycle of the CPU clock, the IR bit in the TAiIC register is set to 1 (interrupt requested). 17.5.3.3 Delay between the Trigger Input and Timer Output One-shot timer output synchronizes with a count source generated internally. When an external trigger is selected, a maximum 1.5 cycle delay of the count source occurs between the trigger input to the TAiIN pin and timer output. 17.5.3.4 Operating Mode Change The IR bit is set to 1 when timer operating mode is set with any of the following procedures: • Selecting one-shot timer mode after reset • Changing the operating mode from timer mode to one-shot timer mode • Changing the operating mode from event counter mode to one-shot timer mode To use the timer Ai interrupt (IR bit), set the IR bit to 0 after the changes listed above are made. 17.5.3.5 Re-Trigger When a trigger occurs while counting, the counter reloads the reload register to continue counting after generating a re-trigger and counting down once. To generate a trigger while counting, generate a re-trigger after more than one cycle of the timer count source has elapsed following the previous trigger. When an external trigger occurs, do not generate a re-trigger for 300 ns before the count value becomes 0000h. The one-shot timer may stop counting. 17.5.3.6 Influence of SD If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is 1 (threephase output forcible cutoff by input on the SD pin enabled), pins TA1OUT, TA2OUT, and TA4OUT enter a high-impedance state. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 332 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.5.4 17.5.4.1 Timer A (Pulse Width Modulation Mode) Register Setting The timer is stopped after reset. Set the mode, count source, counter value, etc., using the TAiMR register, the TAi register, bits TA0TGL and TA0TGH in the ONSF register, the TRGSR register, registers TACS0 to TACS2, the TAPOFS register, TCKDIVC0 register, the PWMFS register, and the PCLKR register before setting the TAiS bit in the TABSR register to 1 (count starts) (i = 0 to 4). Always make sure the TAiMR register, bits TA0TGL and TA0TGH in the ONSF register, the TRGSR register, registers TACS0 to TACS2, the TAPOFS register, TCKDIVC0 register, the PWMFS register, and the PCLKR register are modified while the TAiS bit is 0 (count stops), regardless of whether after reset or not. 17.5.4.2 Operating Mode Change The IR bit is set to 1 when setting a timer operating mode with any of the following procedures: • Selecting PWM mode or programmable output mode after reset • Changing the operating mode from timer mode to PWM mode or programmable output mode • Changing the operating mode from event counter mode to PWM mode or programmable output mode To use the timer Ai interrupt (IR bit), set the IR bit to 0 by a program after the changes listed above are made. 17.5.4.3 Stop While Counting When setting the TAiS bit to 0 (count stops) during PWM pulse output, the following actions occur. When the POFSi bit in the TAPOFS register is 0: • Counting stops. • When the TAiOUT pin is high, the output level goes low and the IR bit is set to 1. • When the TAiOUT pin is low, both the output level and the IR bit remain unchanged. When the POFSi bit in the TAPOFS register is 1: • Stop counting. • If the TAiOUT pin output is low, the output level goes high and the IR bit is set to 1. • If the TAiOUT pin output is high, both the output level and the IR bit remain unchanged. 17.5.4.4 Influence of SD If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is 1 (threephase output forcible cutoff by input on the SD pin enabled), pins TA1OUT, TA2OUT, and TA4OUT go to the high-impedance state. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 333 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 17. Timer A 17.5.5 17.5.5.1 Timer A (Programmable Output Mode) Register Setting The timer is stopped after reset. Set the mode, count source, counter value, etc., using the TAiMR register, the TAi register, the TRGSR register, registers TACS0 to TACS2, the TAPOF register, TCKDIVC0 register, the PWMFS register, the PCLKR register, and the TAi1 register before setting the TAiS bit in the TABSR register to 1 (count starts) (i = 1, 2, 4). Always make sure the TAiMR register, the TRGSR register, registers TACS0 to TACS2, the TAPOFS register, TCKDIVC0 register, the PWMFS register, and the PCLKR register are modified while the TAiS bit is 0 (count stops), regardless of whether after reset or not. 17.5.5.2 Operating Mode Change The IR bit is set to 1 when setting a timer operating mode with any of the following procedures: • Selecting PWM mode or programmable output mode after reset • Changing the operating mode from timer mode to PWM mode or programmable output mode • Changing the operating mode from event counter mode to PWM mode or programmable output mode To use the timer Ai interrupt (IR bit), set the IR bit to 0 by a program after the changes listed above are made. 17.5.5.3 Stop While Counting When setting the TAiS bit to 0 (count stops) during pulse output, the following actions occur. When the POFSi bit in the TAPOFS register is 0: • Counting stops. • When the TAiOUT pin is high, the output level goes low and the IR bit is set to 1. • When the TAiOUT pin is low, both the output level and the IR bit remain unchanged. When the POFSi bit in the TAPOFS register is 1: • Stop counting. • If the TAiOUT pin output is low, the output level goes high and the IR bit is set to 1. • If the TAiOUT pin output is high, both the output level and the IR bit remain unchanged. 17.5.5.4 Influence of SD If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is 1 (threephase output forcible cutoff by input on the SD pin enabled), pins TA1OUT, TA2OUT, and TA4OUT go to the high-impedance state. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 334 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B 18. Timer B Note The 80-pin package does not have the TB1IN pin. Do not use functions associated with this pin. 18.1 Introduction Timers B0 to B5 are provided for timer B. Each timer operates independently of the others. Table 18.1 lists Specifications of Timer B, Figure 18.1 shows Timer A and B Count Sources, Figure 18.2 shows Timer B Configuration, Figure 18.3 shows Timer B Block Diagram, and Table 18.2 lists I/O Ports. Table 18.1 Item Configuration Operating mode 16-bit timer × 6 • Timer mode The timer counts an internal count source. • Event counter mode The timer counts pulses from an external device, or overflows and underflows of other timers. • Pulse period/pulse width measurement modes The timer measures pulse period or pulse width of an external signal. Overflow/underflow/active edge of measurement pulse × 6 Specifications of Timer B Specification Interrupt source Clock Generator Main clock generator or PLL frequency synthesizer 40 MHz on-chip oscillator fOCO-F f1TIMAB 1 PCLK0 Divider fOCO-F 1 CM21 0 1 f1 0 0 TCDIV00 fOCO-F f1TIMAB or f2TIMAB f8TIMAB 1/4 Timer AB divider 1/2 f32TIMAB f64TIMAB fOCO-S 1/2 1/8 f2TIMAB 0 1 FRA01 125 KHz on-chip oscillator Sub clock generator fOCO-S fOCO-S fC 1/32 Reset Set the CPSR bit in the CPSRF register to 1 (prescaler reset). fC32 CM21 PCLK0 FRA01 TCDIV00 fC32 : Bit in the CM2 register : Bit in the PCLKR register : Bit in the FRA0 register : Bit in the TCKDIVC0 register Figure 18.1 Timer A and B Count Sources REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 335 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B fC32 fOCO-S fOCO-F f64TIMAB f32TIMAB f8TIMAB f1TIMAB or f2TIMAB 00 01 10 11 Timer B2 overflow or underflow (to timer A count source) ↑ TCK1 to TCK0 0 TCS3 TMOD1 to TMOD0 00: Timer mode 10: Pulse period, pulse width measurement mode Timer B0 interrupt TCS2 to TCS0 1 000 001 010 011 100 101 110 1 0 Timer B0 TCK1 01: Event counter mode TB0IN 00 01 10 11 Noise filter TCK1 to TCK0 0 TCS7 TMOD1 to TMOD0 00: Timer mode 10: Pulse period, pulse width measurement mode 1 0 000 001 010 011 100 101 110 TCS6 to TCS4 1 Timer B1 TCK1 Timer B1 interrupt 01: Event counter mode TB1IN 00 01 10 11 000 001 010 011 100 101 110 Noise filter TCK1 to TCK0 0 TCS3 TMOD1 to TMOD0 00: Timer mode 10: Pulse period, pulse width measurement mode 1 0 TCS2 to TCS0 1 Timer B2 TCK1 Timer B2 interrupt 01: Event counter mode TB2IN 00 01 10 11 Noise filter TCK1 to TCK0 0 TCS3 TMOD1 to TMOD0 00: Timer mode 10: Pulse period, pulse width measurement mode 1 0 000 001 010 011 100 101 110 TCS2 to TCS0 1 Timer B3 TCK1 Timer B3 interrupt 01: Event counter mode TB3IN 00 01 10 11 000 001 010 011 100 101 110 Noise filter TCK1 to TCK0 0 TCS7 TMOD1 to TMOD0 00: Timer mode 10: Pulse period, pulse width measurement mode 1 0 TCS6 to TCS4 1 Timer B4 TCK1 Timer B4 interrupt 01: Event counter mode TB4IN 00 01 10 11 000 001 010 011 100 101 110 Noise filter TCK1 to TCK0 0 TCS3 TMOD1 to TMOD0 00: Timer mode 10: Pulse period, pulse width measurement mode 1 0 TCS2 to TCS0 1 Timer B5 TCK1 Timer B5 interrupt 01: Event counter mode TB5IN (1) Noise filter TCK1 to TCK0, TMOD1 to TMOD0 : Bits in the TBiMR register TCS0 to TCS7 : Bits in registers TBCS0 to TBCS3 i = 0 to 5 Note: 1. TA0IN shares pins with TB5IN. Figure 18.2 Timer B Configuration REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 336 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B Data Bus PPWFS12 to PPWFS10 PPWFS22 to PPWFS20 TBi1 register TBi register f1TIMAB or f2TIMAB f8TIMAB f32TIMAB fC32 f1TIMAB or f2TIMAB f8TIMAB f32TIMAB f64TIMAB fOCO-F fOCO-S fC32 Clock source select TCK1 to TCK0 TCS3 00 or TCS7 01 0 10 11 TCS2 to TCS0 or TCS6 to TCS4 000 001 010 011 100 101 110 1 Reload register 00: Timer mode TMOD1 to TMOD0 10: Pulse period, pulse width measurement mode Reload register Selector 1 TCK1 01 : Event counter Counter TBj overflow (1) 0 TBiS Polarity select, edge pulse Counter reset circuit TBiIN Note: 1. Overflow or underflow TCK1 to TCK0, TMOD1 to TMOD0 : Bits in the TBiMR register TBiS : Bits in the TABSR register or TBSR register TCS0 to TCS7 : Bits in the registers TBCS0 to TBCS3 PPWFS12 to PPWFS10 : Bits in the PPWFS1 register PPWFS22 to PPWFS20 : Bits in the PPWFS2 register i = 0 to 5 j = i - 1, except j = 2 if i = 0, and j = 5 if i = 3 TBi Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 Timer B5 TBj Timer B2 Timer B0 Timer B1 Timer B5 Timer B3 Timer B4 Figure 18.3 Timer B Block Diagram Table 18.2 I/O Ports Pin Name TBiIN I/O Type Input (1) Function Count source input (event counter mode) Measurement pulse input (pulse period measurement mode, pulse width measurement mode) i = 0 to 5 Note: 1. When using the TBiIN pin for input, set the port direction bit corresponding to the pin to 0 (input mode). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 337 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B 18.2 Registers Table 18.3 lists registers associated with timer B. Set the TCDIV00 bit in the TCKDIVC0 register before setting other registers associated with timer B. After changing the TCDIV00 bit, set other registers associated with timer B again. Refer to “registers and the setting” in each mode for registers and bit settings. Table 18.3 Register Structure Address 0012h 0015h 01C0h 01C1h 01C2h 01C3h 01C4h 01C5h 01C6h 01C8h 01C9h 01CBh 01E0h 01E1h 01E2h 01E3h 01E4h 01E5h 01E6h 01E8h 01E9h 0300h 0310h 0311h 0312h 0313h 0314h 0315h 031Bh 031Ch 031Dh 0320h 0330h 0331h 0332h 0333h 0334h 0335h 033Bh 033Ch 033Dh Register Name Peripheral Clock Select Register Clock Prescaler Reset Flag Timer B0-1 Register Timer B1-1 Register Timer B2-1 Register Pulse Period/Pulse Width Measurement Mode Function Select Register 1 Timer B Count Source Select Register 0 Timer B Count Source Select Register 1 Timer AB Division Control Register 0 Timer B3-1 Register Timer B4-1 Register Timer B5-1 Register Pulse Period/Pulse Width Measurement Mode Function Select Register 2 Timer B Count Source Select Register 2 Timer B Count Source Select Register 3 Timer B3/B4/B5 Count Start Flag Timer B3 Register Timer B4 Register Timer B5 Register Timer B3 Mode Register Timer B4 Mode Register Timer B5 Mode Register Count Start Flag Timer B0 Register Timer B1 Register Timer B2 Register Timer B0 Mode Register Timer B1 Mode Register Timer B2 Mode Register Register Symbol After Reset PCLKR 0000 0011b CPSRF 0XXX XXXXb TB01 XXh XXh TB11 XXh XXh TB21 XXh XXh PPWFS1 XXXX X000b TBCS0 TBCS1 TCKDIVC0 TB31 TB41 TB51 PPWFS2 TBCS2 TBCS3 TBSR TB3 TB4 TB5 TB3MR TB4MR TB5MR TABSR TB0 TB1 TB2 TB0MR TB1MR TB2MR 00h X0h 0000 X000b XXh XXh XXh XXh XXh XXh XXXX X000b 00h X0h 000X XXXXb XXh XXh XXh XXh XXh XXh 00XX 0000b 00XX 0000b 00XX 0000b 00h XXh XXh XXh XXh XXh XXh 00XX 0000b 00XX 0000b 00XX 0000b REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 338 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B 18.2.1 Peripheral Clock Select Register (PCLKR) Peripheral Clock Select Register b7 b6 b5 b4 b3 b2 b1 b0 00 000 Symbol PCLKR Bit Symbol Bit Name Address 0012h Function After Reset 0000 0011b RW PCLK0 Timers A and B clock select bit (clock source for timers A and B, the dead time timer, and muliti-master I2C-bus interface) SI/O clock select bit (clock source for UART0 to UART2, UART5 to UART7, SI/O3, and SI/O4) Reserved bits Clock output function extension bit (valid in single-chip mode) Reserved bits 0: f2TIMAB/f2IIC 1: f1TIMAB/f1IIC RW PCLK1 0: f2SIO 1: f1SIO RW — (b4-b2) PCLK5 — (b7-b6) Set to 0 0: Selected by bits CM01 to CM00 in the CM0 register 1: Output f1 Set to 0 RW RW RW Write to the PCLKR register after setting the PRC0 bit in the PRCR register to 1 (write enabled). 18.2.2 Clock Prescaler Reset Flag (CPSRF) Clock Prescaler Reset Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol CPSRF Bit Symbol — (b6-b0) CPSR Bit Name Address 0015h Function After Reset 0XXX XXXXb RW — No register bits. If necessary, set to 0. Read as undefined value Setting this bit to 1 initializes the prescaler for the timekeeping clock. (Read as 0) Clock prescaler reset flag RW REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 339 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B 18.2.3 Timer Bi Register (TBi) (i = 0 to 5) Timer Bi Register (i = 0 to 5) (b15) b7 (b8) b0 b7 b0 Symbol TB0 TB1 TB2 TB3 TB4 TB5 Mode Address 0331h to 0330h 0333h to 0332h 0335h to 0334h 0311h to 0310h 0313h to 0312h 0315h to 0314h Function When n = set value, Counter cycle: (n + 1) fj When n = set value, n + 1 count Set an initial value. Measures a pulse period or width. Read the counter value while counting is in progress. After Reset Undefined Undefined Undefined Undefined Undefined Undefined Setting Range RW Timer mode 0000h to FFFFh RW Event counter mode Pulse period measurement mode, Pulse width measurement mode fj : Count source frequency 0000h to FFFFh RW 0000h to FFFFh RW Access this register in 16-bit units. Event Counter Mode The timer counts pulses from an external device or overflows or underflows of other timers. Pulse Period Measurement Mode, Pulse Width Measurement Mode Set these modes when the TBiS bit in the TABSR or TBSR register is set to 0 (count stops). Read only (RO) when the TBiS bit in the TABSR or TBSR register is set to 1 (count starts). The counter starts counting the count source at an active edge of the measurement pulse, transfers the count value to a register at the next active edge, and continues counting. The measurement result can be read by reading the TBi register when bits PPWFS12 to PPWFS10 in the PPWFS1 register and bits PPWFS22 to PPWFS20 in the PPWFS2 register are 0. While counting is in progress, the counter value can be read by reading the TBi register when bits PPWFS12 to PPWFS10 and bits PPWFS22 to PPWFS20 are 1. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 340 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B 18.2.4 Timer Bi-1 Register (TBi1) (i = 0 to 5) Timer Bi-1 Register (i = 0 to 5) (b15) b7 (b8) b0 b7 b0 Symbol TB01 TB11 TB21 TB31 TB41 TB51 Mode Pulse period measurement mode Pulse width measurement mode Address 01C1h to 01C0h 01C3h to 01C2h 01C5h to 01C4h 01E1h to 01E0h 01E3h to 01E2h 01E5h to 01E4h Function After Reset Undefined Undefined Undefined Undefined Undefined Undefined Setting Range RW Measures a pulse period or width 0000h to FFFFh RO Access the register in 16-bit units. The measurement result can be read by reading the TBi-1 register when bits PPWFS12 to PPWFS10 in the PPWFS1 register and bits PPWFS22 to PPWFS20 in the PPWFS2 register are 1. The value in the TBi1 register is undefined when bits PPWFS12 to PPWFS10 and bits PPWFS22 to PPWFS20 are 0. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 341 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B 18.2.5 Pulse Period/Pulse Width Measurement Mode Function Select Register i (PPWFSi) (i = 1, 2) Pulse Period/Pulse Width Measurement Mode Function Select Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PPWFS1 Bit Symbol Bit Name Address 01C6h Function 0 : Measurement result is stored in the TB0 register. The TB01 register is not used 1 : The counter value is read in the TB01 register. Measurement result is stored in the TB0 register 0 : Measurement result is stored in the TB1 register. The TB11 register is not used 1 : The counter value is read in the TB11 register. Measurement result is stored in the TB1 register 0 : Measurement result is stored in the TB2 register. The TB21 register is not used 1 : The counter value is read in the TB21 register. Measurement result is stored in the TB2 register After Reset XXXX X000b RW Timer B0 pulse period/pulse PPWFS10 width measurement mode function select bit RW Timer B1 pulse period/pulse PPWFS11 width measurement mode function select bit RW Timer B2 pulse period/pulse PPWFS12 width measurement mode function select bit RW — POFS0 (b7-b3) No register bits. If necessary, set to 0. Read as undefined value — Pulse Period/Pulse Width Measurement Mode Function Select Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PPWFS2 Bit Symbol Bit Name Address 01E6h Function 0 : Measurement result is stored in the TB3 register. The TB31 register is not used 1 : The counter value is read in the TB31 register. Measurement result is stored in the TB3 register 0 : Measurement result is stored in the TB4 register. The TB41 register is not used 1 : The counter value is read in the TB41 register. Measurement result is stored in the TB4 register 0 : Measurement result is stored in the TB5 register. The TB51 register is not used 1 : The counter value is read in the TB51 register. Measurement result is stored in the TB5 register After Reset XXXX X000b RW Timer B3 pulse period/pulse PPWFS20 width measurement mode function select bit RW Timer B4 pulse period/pulse PPWFS21 width measurement mode function select bit RW Timer B5 pulse period/pulse PPWFS22 width measurement mode function select bit RW — POFS0 (b7-b3) No register bits. If necessary, set to 0. Read as undefined value — Enabled in pulse period measurement mode or pulse width measurement mode. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 342 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B 18.2.6 Timer B Count Source Select Register i (TBCSi) (i = 0 to 3) Timer B Count Source Select Register 0, Timer B Count Source Select Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol TBCS0 TBCS2 Bit Symbol TCS0 Bit Name Address 01C8h 01E8h Function b2 b1 b0 After Reset 00h 00h RW RW TBi count source select bit TCS1 TCS2 TCS3 TBi count source option specified bit TBj count source select bit 0 0 0 : f1TIMAB or f2TIMAB 0 0 1 : f8TIMAB 0 1 0 : f32TIMAB 0 1 1 : f64TIMAB 1 0 0 : fOCO-F 1 0 1 : fOCO-S 1 1 0 : fC32 1 1 1 : Do not set 1 : TCK0 to TCK1 enabled, TCS0 to TCS2 disabled 0 : TCK0 to TCK1 disabled, TCS0 to TCS2 enabled b6 b5 b4 RW RW RW TCS4 TCS5 TCS6 TCS7 TBj count source option specified bit 0 0 0 : f1TIMAB or f2TIMAB 0 0 1 : f8TIMAB 0 1 0 : f32TIMAB 0 1 1 : f64TIMAB 1 0 0 : fOCO-F 1 0 1 : fOCO-S 1 1 0 : fC32 1 1 1 : Do not set 1 : TCK0 to TCK1 enabled, TCS4 to TCS6 disabled 0 : TCK0 to TCK1 disabled, TCS4 to TCS6 enabled RW RW RW RW TBCS0 register: i = 0, j = 1 TBCS2 register: i = 3, j = 4 Timer B Count Source Select Register 1, Timer B Count Source Select Register 3 b7 b6 b5 b4 b3 b2 b1 b0 Symbol TBCS1 TBCS3 Bit Symbol TCS0 Bit Name Address 01C9h 01E9h Function b2 b1 b0 After Reset X0h X0h RW RW TBi count source select bit TCS1 TCS2 TCS3 TBi count source option specified bit 0 0 0: f1TIMAB or f2TIMAB 0 0 1: f8TIMAB 0 1 0: f32TIMAB 0 1 1: f64TIMAB 1 0 0: fOCO-F 1 0 1: fOCO-S 1 1 0: fC32 1 1 1: Do not set 1: TCK0 to TCK1 enabled, TCS0 to TCS2 disabled 0: TCK0 to TCK1 disabled, TCS0 to TCS2 enabled RW RW RW — (b7-b4) TBCS1 register: i = 2 No register bits. If necessary, set to 0. Read as undefined value — TBCS3 register: i = 5 TCS2-TCS0 (TBi Count Source Select Bit) (b2-b0) TCS6-TCS4 (TBj Count Source Select Bit) (b6-b4) Select f1TIMAB or f2TIMAB by the PCLK0 bit in the PCLKR register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 343 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B 18.2.7 Timer AB Division Control Register 0 (TCKDIVC0) Timer AB Division Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 0000 00 Symbol TCKDIVC0 Bit Symbol TCDIV00 — (b2-b1) — (b3) — (b7-b4) Bit Name Address 01CBh Function After Reset 0000 X000b RW RW Clock select prior to timer AB 0 : f1 1 : fOCO-F division bit Reserved bits Set to 0 RW No register bit. If necessary, set to 0. Read as undefined value — Reserved bits Set to 0 RW TCDIV00 (Clock Select Prior to Timer AB Division Bit) (b1) Set the TCDIV00 bit while timer A and B stops. Set the TCDIV00 bit before setting other registers associated with timer B. After changing the TCDIV00 bit, set other registers associated with timer B again. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 344 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B 18.2.8 Count Start Flag (TABSR) Timer B3/B4/B5 Count Start Flag (TBSR) Count Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Bit Symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Bit Name Address 0320h Function 0 : Stop counting 1 : Start counting After Reset 00h RW RW RW RW RW RW RW RW RW Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag Timer B3/B4/B5 Count Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TBSR Bit Symbol — POFS0 (b4-b0) TB3S TB4S TB5S Bit Name Address 0300h Function After Reset 000X XXXXb RW — RW RW RW No register bits. If necessary, set to 0. Read as undefined value Timer B3 count start flag Timer B4 count start flag Timer B5 count start flag 0 : Stop counting 1 : Start counting REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 345 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B 18.2.9 Timer Bi Mode Register (TBiMR) (i = 0 to 5) Timer Bi Mode Register (i = 0 to 5) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TB0MR to TB2MR TB3MR to TB5MR Bit Symbol TMOD0 Bit Name Address 033Bh to 033Dh 031Bh to 031Dh Function b1 b0 After Reset 00XX 0000b 00XX 0000b RW RW Operation mode select bit 0 0 1 1 TMOD1 MR0 0 : Timer mode 1 : Event counter mode 0 : Pulse period measurement mode Pulse width measurement mode 1 : Do not set RW RW Function varies with the operation mode MR1 — (b4) MR3 TCK0 TCK1 No register bit. If necessary, set to 0. Read as undefined value Function varies with the operation mode Count source select bit (Function varies with the operation mode) RW — RO RW RW REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 346 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B 18.3 18.3.1 Operations Common Operations Operating Clock 18.3.1.1 The count source for each timer acts as a clock, controlling such timer operations as counting and reloading. 18.3.1.2 Counter Reload Timing Timer Bi starts counting from the value (n) set in the TBi register. The TBi register consists of a counter and a reload register. The counter starts decrementing the count source from n, reloads a value in the reload register at the next count source after the value becomes 0000h, and continues decrementing. The value written in the TBi register takes effect in the counter and the reload register at the timings below. • When the count is stopped • Between the count starts and the first count source is input A value written to the TBi register is immediately written to the counter and the reload register. • After the count starts and the first count source is input A value written to the TBi register is immediately written to the reload register. The counter continues counting and reloads the value in the reload register at the next count source after the value becomes 0000h. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 347 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B 18.3.1.3 Count Source Internal clocks are counted in timer mode, pulse period measurement mode, and pulse width measurement mode. (Refer to Figure 18.1 “Timer A and B Count Sources”.) Table 18.4 lists Timer B Count Source. Timer A, B, and multi-master I2C-bus interface share the divider. f1 or fOCO-F can be selected before the timer AB divider. f1 is any of the clocks listed below. Select f1 by the CM21 bit in the CM2 register and the FRA01 bit in the FRA0 register. (Refer to 8. “Clock Generator”.) • Main clock divided by 1 (no division) • PLL clock divided by 1 (no division) • fOCO-S divided by 1 (no division) • fOCO-F divided by 1 (no division) Table 18.4 Timer B Count Source Count Source f1TIMAB f2TIMAB f8TIMAB f32TIMAB f64TIMAB fOCO-F fOCO-S fC32 Bit Set Value TCS2 to TCS3 TCS0 PCLK0 TCS4 to TCS7 TCS6 1 0 1 000b 0 0 1 000b 0 1 001b 0 1 010b 1 011b - TCK1 to TCK0 00b 00b 01b 10b - Remarks f1 or fOCO-F (1) f1 divided by 2 or fOCO-F divided by 2 (1) f1 divided by 8 or fOCO-F divided by 8 (1) f1 divided by 32 or fOCO-F divided by 32 (1) f1 divided by 64 or fOCO-F divided by 64 (1) fOCO-F fOCO-S fC32 1 100b 1 101b 0 11b 1 110b PCLK0: Bit in the PCLKR register TCS7 to TCS0: Bits in registers TBCS0 toTBCS3 TCK1 to TCK0: Bits in the TBiMR register (i = 0 to 5) Note: 1. Select f1 or fOCO-F by the TCDIV00 bit in the TCKDIVC0 register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 348 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B 18.3.2 Timer Mode In timer mode, the timer counts a count source generated internally. Table 18.5 lists Specifications of Timer Mode, Table 18.6 lists Registers and the Setting in Timer Mode, and Figure 18.4 shows Operation Example in Timer Mode. Table 18.5 Specifications of Timer Mode Item Count source Count operations Specification f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB, f64TIMAB, fOCO-F, fOCO-S, fC32 • Decrement • When the timer underflows, it reloads the reload register contents and continues counting. 1 ----------------(n + 1) Counter cycles n: set value of the TBi register Count start condition Count stop condition Interrupt request generation timing TBiIN pin function Read from timer Write to timer (1) 0000h to FFFFh Set the TBiS bit to 1 (start counting). Set the TBiS bit to 0 (stop counting). Timer underflow I/O port Count value can be read by reading the TBi register. • When not counting The value written to the TBi register is written to both the reload register and the counter. • When counting The value written to the TBi register is only written to the reload register (transferred to the counter when reloaded next). i = 0 to 5 Note: 1. Bits TB0S to TB2S are assigned to bits 5 to 7 in the TABSR register, and bits TB3S to TB5S are assigned to bits 5 to 7 in the TBSR register. Table 18.6 Registers and the Setting in Timer Mode (1) Bit Setting PCLK0 Select the count source. CPSR Write a 1 to reset the clock prescaler. 7 to 0 - (setting unnecessary) PPWFS12 to Set to 0. PPWFS10 PPWFS22 to PPWFS20 TCKDIVC0 TCDIV00 Select a clock used prior to timer AB frequency dividing. TBCS0 to TBCS3 7 to 0 Select the count source. TABSR TAiS Set to 1 when starting counting. TBSR Set to 0 when stopping counting. TBi 7 to 0 Set the count value. TBiMR 7 to 0 Refer to the TBiMR register below. i = 0 to 5 Note: 1. This table does not describe a procedure. Register PCLKR CPSRF TBi1 PPWFS1 to PPWFS2 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 349 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B Timer Mode Timer Bi Mode Register (i = 0 to 5) b7 b6 b5 b4 b3 b2 b1 b0 0000 Symbol TB0MR to TB2MR TB3MR to TB5MR Bit Symbol TMOD0 Operation mode select bit TMOD1 MR0 Set to 0 in timer mode MR1 — Bit Name Address 033Bh to 033Dh 031Bh to 031Dh Function After Reset 00XX 0000b 00XX 0000b RW RW RW RW RW b1 b0 0 0 : Timer mode No register bit. If necessary, set to 0. Read as undefined value Write 0 in timer mode. Read as undefined value in timer mode b7 b6 — MR3 RO TCK0 Count source select bit TCK1 0 0 1 1 0 : f1TIMAB or f2TIMAB 1 : f8TIMAB 0 : f32TIMAB 1 : fC32 RW RW TCK1-TCK0 (Count Source Select Bit) (b7-b6) Enabled when the TCS3 or TCS7 bit in registers TBCS0 to TBCS3 is set to 0 (TCK0 to TCK1 enabled). Select f1TIMAB or f2TIMAB by the PCLK0 bit in the PCLKR register. Count start n Count operations Count stop by TBiS bit 0000h Underflow reload TBiS bit in TABSR register or TBSR register IR bit in TBiIC register Set to 0 by an interrupt request acknowledgement or by a program. i = 0 to 5 The above timing diagram applies when the register bits are set as follows: -Value in the TBi register (n) = 0004h n+1 Figure 18.4 Operation Example in Timer Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 350 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B 18.3.3 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Table 18.7 lists Specifications of Event Counter Mode, Table 18.8 lists Registers and the Setting in Event Counter Mode, and Figure 18.5 shows Operation Example in Event Counter Mode. Table 18.7 Specifications of Event Counter Mode Item Count source Specification • External signals input to TBiIN pin (active edge can be selected by a program: rising edge, falling edge, or both rising and falling edges) • Timer Bj overflow or underflow Count operations • Decrement • When the timer underflows, it reloads the reload register contents and continues counting. 1 ----------------(n + 1) Number of counts n: set value of the TBi register Count start condition Count stop condition Interrupt request generation timing TBiIN pin function Read from timer Write to timer (1) 0000h to FFFFh Set the TBiS bit to 1 (start counting). Set the TBiS bit to 0 (stop counting). Timer underflow i = 0 to 5 Note: 1. Bits TB0S to TB2S are assigned to bits 5 to 7 in the TABSR register, and bits TB3S to TB5S are assigned to bits 5 to 7 in the TBSR register. Table 18.8 Registers and the Setting in Event Counter Mode (1) Count source input Count value can be read by reading the TBi register. • When not counting Value written to the TBi register is written to both reload register and counter. • When counting Value written to the TBi register is written to only reload register (transferred to counter when reloaded next). j = i - 1, except j = 2 if i = 0, j = 5 if i = 3 PCLK0 Set to 1. CPSR Write a 1 to reset the clock prescaler. 7 to 0 - (setting unnecessary) PPWFS12 to Set to 0. PPWFS10 PPWFS22 to PPWFS20 TCKDIVC0 TCDIV00 Set to 0. TBCS0 to TBCS3 7 to 0 Set to 00b. TABSR TBiS Set to 1 when starting counting. TBSR Set to 0 when stopping counting. TBi 7 to 0 Set the count value. TBiMR 7 to 0 Refer to the TBiMR register below. i = 0 to 5 Note: 1. This table does not describe a procedure. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 351 of 791 Register PCLKR CPSRF TBi1 PPWFS1 to PPWFS2 Bit Setting Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B Event Counter Mode Timer Bi Mode Register (i = 0 to 5) b7 b6 b5 b4 b3 b2 b1 b0 01 Symbol TB0MR to TB2MR TB3MR to TB5MR Bit Symbol TMOD0 TMOD1 Bit Name Address 033Bh to 033Dh 031Bh to 031Dh Function b1 b0 After Reset 00XX 0000b 00XX 0000b RW RW RW Operation mode select bit 0 1 : Event counter mode b3 b2 MR0 Count polarity select bit MR1 0 0 1 1 0 : Counts falling edges of external signal 1 : Counts rising edges of external signal 0 : Counts falling and rising edges of an external signal 1 : Do not set RW RW — No register bit. If necessary, set to 0. Read as undefined value Write 0 in event counter mode. Read as undefined value in event counter mode Invalid in event counter mode. Set 0 or 1 Event clock select 0 : Input from TBiIN pin 1 : TBj overflow or underflow (j = i – 1; however, j = 2 if i = 0, j = 5 if i = 3) — MR3 RO TCK0 RW TCK1 RW MR1-MR0 (Count Polarity Select Bit) (b3-b2) Valid when the TCK1 bit is 0 (input from TBiIN pin). If the TCK1 bit is 1 (TBj overflow or underflow), these bits can be set to 0 or 1. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 352 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B TBiIN input Count start n Count operations Count stop by TBiS bit 0000h TBiS bit in TABSR register or TBSR register IR bit in TBiIC register Set to 0 by an interrupt request acknowledgement or by a program. i = 0 to 5 The above timing diagram applies when the register bits are set as follows: -Bits MR1 to MR0 in the TBiMR register = 10b (the falling edge and rising edge of an external signal) -The TCK1 bit in the TBiMR register = 0 (input signals from the TBiIN pin counted) -Value in the TBi register (n) = 0004h Underflow reload n+1 Figure 18.5 Operation Example in Event Counter Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 353 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B 18.3.4 Pulse Period/Pulse Width Measurement Modes In pulse period and pulse width measurement modes, the timer measures pulse period or pulse width of an external signal. Table 18.9 lists Specifications of Pulse Period/Pulse Width Measurement Modes, Table 18.10 lists Registers and the Setting in Pulse Period/Pulse Width Measurement Modes, Figure 18.6 shows Operation Example in Pulse Period Measurement Mode, and Figure 18.7 shows Operation Example in Pulse Width Measurement Mode. Table 18.9 Specifications of Pulse Period/Pulse Width Measurement Modes Item Count source Count operations Count start condition Count stop condition Interrupt request generation timing TBiIN pin function Read from timer Specification f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB, f64TIMAB, fOCO-F, fOCO-S, fC32 • Increment • Counter value is transferred to reload register at an active edge of the measurement pulse. The counter value is set to 0000h to continue counting. Set the TBiS bit (3) to 1 (start counting). Set the TBiS bit to 0 (stop counting). • When an active edge of measurement pulse is input (1) • Timer overflow. When an overflow occurs, the MR3 bit in the TBiMR register is set to 1 (overflowed) simultaneously. Measurement pulse input When bits PPWFS12 to PPWFS10 and PPWFS22 to PPWFS20 in registers PPWFS1 and PPWFS2 are 0 • Contents of the reload register (measurement result) can be read by reading the TBi register (2) When bits PPWFS12 to PPWFS10 and PPWFS22 to PPWFS20 in registers PPWFS1 and PPWFS2 are 1 • Contents of the counter (counter value) can be read by reading the TBi register • Contents of the reload register (measurement result) can be read by reading the TBi1 register • When not counting Value written to the TBi register is written to both reload register and counter. • When counting Value written to the TBi register is written to only reload register (transferred to counter when reloaded next). Write to timer i = 0 to 5 Notes: 1. No Interrupt request is generated when the first active edge is input after the timer starts counting. 2. Value read from the TBi register is undefined until the second active edge is input after the timer starts counting. 3. Bits TB0S to TB2S are assigned to bits 5 to 7 in the TABSR register, and bits TB3S to TB5S are assigned to bits 5 to 7 in the TBSR register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 354 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B Table 18.10 Registers and the Setting in Pulse Period/Pulse Width Measurement Modes (1) Register PCLKR CPSRF TBi1 PPWFS1 to PPWFS2 Bit PCLK0 CPSR 7 to 0 Setting Select the count source. Write a 1 to reset the clock prescaler. Measurement result can be read when the bits in the PPWFS1 or PPWFS2 register corresponding to timer Bi are 1. Set to 1 to read the counter value while counting. PPWFS12 to PPWFS10 PPWFS22 to PPWFS20 TCKDIVC0 TCDIV00 TBCS0 to TBCS3 7 to 0 TBiS TABSR TBSR TBi 7 to 0 TBiMR 7 to 0 i = 0 to 5 Note: 1. This table does not describe a procedure. Select a clock used prior to timer AB frequency dividing. Select the count source. Set to 1 when starting counting. Set to 0 when stopping counting. Set the initial value. The measurement result can be read when the bits in the PPWFS1 or PPWFS register corresponding to timer Bi are 0. The counter value can be read when the bits in the PPWFS1 or PPWFS2 register corresponding to timer Bi are 1. Refer to the following TBiMR register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 355 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B Pulse Period/Pulse Width Measurement Modes Timer Bi Mode Register (i = 0 to 5) b7 b6 b5 b4 b3 b2 b1 b0 10 Symbol TB0MR to TB2MR TB3MR to TB5MR Bit Symbol TMOD0 TMOD1 Bit Name Address 033Bh to 033Dh 031Bh to 031Dh Function b1 b0 After Reset 00XX 0000b 00XX 0000b RW RW RW Operation mode select bit 1 0 : Pulse period/pulse width measurement modes 0 : Pulse period measurement (Measurement between a falling edge and the next falling edge of measured pulse) 1 : Pulse period measurement (Measurement between a rising edge and the next rising edge of measured pulse) 0 : Pulse width measurement (Measurement between a falling edge and the next rising edge of measured pulse and between a rising edge and the next falling edge) 1 : Do not set b3 b2 0 MR0 0 Measurement mode select bit MR1 1 — RW 1 RW No register bit. If necessary, set to 0. Read as undefined value 0 : No overflow 1 : Overflow b7 b6 — MR3 TCK0 Timer Bi overflow flag RO RW RW Count source select bit TCK1 0 0 1 1 0 : f1TIMAB or f2TIMAB 1 : f8TIMAB 0 : f32TIMAB 1 : fC32 MR3 (Timer Bi Overflow Flag) (b5) This flag is undefined after reset. The MR3 bit is cleared to 0 (no overflow) by writing to the TBiMR register. The MR3 bit cannot be set to 1 by a program. TCK1-TCK0 (Count Source Select Bit) (b7-b6) Enabled when the TCS3 bit or TCS7 bit in registers TBCS0 to TBCS3 is set to 0 (TCK0, TCK1 enabled). Select f1TIMAB or f2TIMAB by the PCLK0 bit in the PCLKR register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 356 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B Count source Transfer to the TBi register (Measured value 3) (Undefined value) Transfer to the TBi register Transfer to the TBi register (Measured value 4) (Undefined value) Count start 0000h (Measured value 1) (Measured value 2) Set to 0000h automatically TBiS bit in TABSR register Set to 0000h automatically TBiIN input Measured value 1 TBi register IR bit in TBiIC register Undefined value Undefined value Measured value 2 Interrupt request by an effective edge of the measured pulse Measured value 3 Measured value 4 Set to 0 by an interrupt request acknowledgement or by a program. i = 0 to 5 The above timing diagram applies when the register bits are set as follows: -Bits MR1 to MR0 in the TBiMR register = 00b (measurement between a falling edge and the next falling edge of measured pulse) -Bits PPWFS12 to PPWFS10 and PPWFS22 to PPWFS20 in registers PPWFS1 and PPWFS2 = 0 (measurement result stored in the TBi register) -No initial value is set while timer Bi is stopped. Figure 18.6 Operation Example in Pulse Period Measurement Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 357 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B Count source FFFFh (Undefined value) Transfer to the TBi register Transfer to the TBi register (Measured value 3) (Undefined value) Count start 0000h TBiS bit in TABSR register or TBSR register TBiIN input (Measured value 1) (Measured value 2) Set to 0000h automatically Set to 0000h automatically Measured value 1 TBi register IR bit in TBiIC register Undefined value Undefined value Measured value 2 Interrupt request by an effective edge of the measured pulse Interrupt request by overflow Measured value 3 Set to 0 by an interrupt request acknowledgement or by a program. MR3 bit in TBiMR register Set to 0 by writing to the TBiMR register i = 0 to 5 The above timing diagram applies when the register bits are set as follows: -Bits MR1 to MR0 in the TBiMR register = 10b (measure pulse width) -Bits PPWFS12 to PPWFS10 and PPWFS22 to PPWFS20 in registers PPWFS1 and PPWFS2 = 0 (measurement result stored in the TBi register) -No initial value is set while timer Bi is stopped. Figure 18.7 Operation Example in Pulse Width Measurement Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 358 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B 18.4 Interrupts Refer to individual operation examples for interrupt request generating timing. Refer to 14.7 “Interrupt Control” for details of interrupt control. Table 18.11 lists Timer B Interrupt Related Registers. Table 18.11 Timer B Interrupt Related Registers Address 0045h 0046h 0047h 005Ah 005Bh 005Ch 0206h Register Name Timer B5 Interrupt Control Register Timer B4 Interrupt Control Register Timer B3 Interrupt Control Register Timer B0 Interrupt Control Register Timer B1 Interrupt Control Register Timer B2 Interrupt Control Register Interrupt Source Select Register 2 Register Symbol TB5IC TB4IC TB3IC TB0IC TB1IC TB2IC IFSR2A After Reset XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b 00h Timers B3 and B4 share interrupt vectors and interrupt control registers with other peripheral functions. When using the timer B3 interrupt, set the IFSR26 bit in the IFSR2A register to 0 (timer B3). When using the timer B4 interrupt, set the IFSR27 bit in the IFSR2A register to 0 (timer B4). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 359 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B 18.5 18.5.1 Notes on Timer B Timer B (Timer Mode) Register Setting 18.5.1.1 The timer is stopped after reset. Set the mode, count source, counter value, etc., using registers TBiMR, TBi, TBCS0 to TBCS3, TCKDIVC0, and PCLKR before setting the TBiS bit in the TABSR or the TBSR register to 1 (count starts) (i = 0 to 5). Always make sure registers TBiMR, TBCS0 to TBCS3, TCKDIVC0, and PCLKR are modified while the TBiS bit is 0 (count stops), regardless of whether after reset or not. 18.5.1.2 Read from Timer The value of the counter while counting can be read from the TBi register at any time. FFFFh is read while reloading. If the counter is read before it starts counting and after a value is set in the TBi register while not counting, the set value is read. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 360 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B 18.5.2 18.5.2.1 Timer B (Event Counter Mode) Register Setting The timer is stopped after reset. Set the mode, count source, counter value, etc., using the TBiMR register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to 1 (count starts) (i = 0 to 5). Always make sure the TBiMR register is modified while the TBiS bit is 0 (count stops), regardless of whether after reset or not. 18.5.2.2 Read from Timer While counting is in progress, the counter value can be read out at any time by reading the TBi register. However, if this register is read at the same time the counter is reloaded, the read value is always FFFFh. If the TBi register is read after setting a value in it while not counting but before the counter starts counting, the read value is the value set in the register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 361 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 18. Timer B 18.5.3 18.5.3.1 Timer B (Pulse Period/Pulse Width Measurement Modes) Register Setting The timer is stopped after reset. Set the mode, count source, etc., using registers TBiMR, TBCS0 to TBCS3, TBi, TCKDIVC0, PCLKR, PPWFS1, and PPWFS2 before setting the TBiS bit in the TABSR or TBSR register to 1 (count starts) (i = 0 to 5). Always make sure registers TBiMR, TBCS0 to TBCS3, TCKDIVC0, PCLKR, PPWFS1, and PPWFS2 are modified while the TBiS bit is 0 (count stops), regardless of whether after reset or not. To clear the MR3 bit to 0 by writing to the TBiMR register while the TBiS bit is 1 (count starts), be sure to write the same value as previously written to bits TMOD0, TMOD1, MR0, MR1, TCK0, and TCK1 and a 0 to bit 4. 18.5.3.2 Interrupts The IR bit in the TBiIC register is set to 1 (interrupt requested) when an active edge of a measurement pulse is input or timer Bi overflows (i = 0 to 5). The source of an interrupt request can be determined by using the MR3 bit in the TBiMR register within the interrupt routine. Use the IR bit in the TBiIC register to detect overflows only. Use the MR3 bit only to determine the interrupt source. 18.5.3.3 Operations between Count Start and the First Measurement When a count is started and the first active edge is input, an undefined value is transferred to the reload register. At this time, timer Bi interrupt request is not generated. The value of the counter is undefined after reset. If count is started in this state, the MR3 bit may be set to 1 and timer Bi interrupt request may be generated after count start before an effective edge is input. When a value is set in the TBi register while the TBiS bit is 0 (count stops), the same value is written to the counter. 18.5.3.4 Pulse Period Measurement Mode When an overflow occurs at an active edge, an input is not recognized at the effective edge because an interrupt request is generated only once. Use this mode where an overflow does not occur, or use pulse width measurement. 18.5.3.5 Pulse Width Measurement Mode In pulse width measurement, pulse widths are measured successively. Use a program to check whether the measurement result is a high-level width or a low-level width. When an interrupt request is generated, read the TBiIN pin level inside the interrupt routine, and check whether it is the edge of an input pulse or an overflow. The TBiIN level can be read from bits in the P9 register of corresponding ports. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 362 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19. Three-Phase Motor Control Timer Function Note Do not use this function for the 80-pin package. 19.1 Introduction Timers A1, A2, A4, and B2 can be used to output three-phase motor drive waveforms. Table 19.1 lists Three-Phase Motor Control Timer Functions Specifications. Three-Phase Motor Control Timer Function Block Diagrams are shown in Figure 19.1 and Figure 19.2. Table 19.2 lists I/O Ports. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 363 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function Table 19.1 Three-Phase Motor Control Timer Functions Specifications Item Operation modes Three-phase waveform output pin Forced cutoff input Used timers Specification • Triangular wave modulation three-phase mode 0 Three-phase PWM waveform of triangular wave modulation is output. Output data is updated every half cycle of the carrier wave, and output waveform is generated. • Triangular wave modulation three-phase mode 1 Three-phase PWM waveform of triangular wave modulation is output. Output data is updated every cycle of the carrier wave, and output waveform is generated. • Sawtooth wave modulation mode Three-phase PWM waveform of sawtooth wave modulation is output. Six pins (U, U, V, V, W, W) Input a low-level signal to the SD pin Timers A4, A1, A2 (used in one-shot timer mode) Timer A4: U-/U-phase waveform control Timer A1: V-/V-phase waveform control Timer A2: W-/W-phase waveform control Timer B2 (used in timer mode) Carrier wave cycle control Dead time timer (three eight-bit timers and shared reload register) Dead time control Triangular wave modulation, sawtooth wave modulation • All high or low outputs for one cycle supported • Output logic of high- and low-side turn-on signals can be set separately. (m + 1) × 2 Triangular wave modulation : ---------------------------- Output waveform Carrier wave cycle fi ------------Sawtooth wave modulation : m + 1 fi m: Setting value of the TB2 register, 0000h to FFFFh fi: Count source frequency (f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB, f64TIMAB, fOCO-F, fOCO-S, fC32) Three-phase PWM output width -----------Triangular wave modulation : n × 2 fi -Sawtooth wave modulation : n fi n: Setting value of registers TA4, TA1, and TA2 (of registers TA4, TA41, TA1, TA11, TA2, and TA21 when setting the INV11 bit to 1), 0001h to FFFFh fi: Count source frequency (f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB, f64TIMAB, fOCO-F, fOCO-S, fC32) Dead time (width) p -- or no dead time fi Active level Simultaneous conduction prevention function Interrupt frequency p: Setting value of the DTT register, 01h to FFh fi: Count source frequency (f1TIMAB, f2TIMAB, f1TIMAB divided by 2, f2TIMAB divided by 2) Selectable either active high or active low Simultaneous conduction prevention Simultaneous conduction detection Timer B2 interrupt is generated every carrier wave cycle to every 15 carrier wave cycles. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 364 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function INV13 INV00 Timer B Reload PWCON 1 0 Counter (Timer mode) Write signal to timer B2 INV10 Start trigger signal for timers A1, A2, and A4 INV07 Timer B2 underflow 0 1/2 1 INV12 INV06 INV01 INV11 1 0 PWCON DTT register Reload register n = 1 to 255 Trigger ICTB2 register Circuit to set interrupt generation frequency ICTB2 counter n = 1 to 15 n = 1 to 15 Timer B2 underflow Timer B2 interrupt request bit To block diagram 2 (A) f1 or f2 INV15 INV14 Inverse control U-phase output (internal signal) Transfer trigger (1) Dead time timer INV16 n = 1 to 255 Trigger 0 1 U-phase output control circuit DQ T TA4 register TA41 register Timer A4 reload control signal DU1 bit DU0 bit Reload Trigger Counter Transfer trigger (1) Timer A4 one-shot pulse DQ T DUB1 bit DQ T DUB0 bit U-phase output signal Three-phase output shift register (U-phase) DQ T Inverse control U-phase output (internal signal) (One-shot timer mode) TQ INV11 When setting the TA4S bit to 0, signal is set to 0. DQ T DQ T U-phase output signal TA1 register TA11 register Timer A1 reload control signal INV06 Trigger Trigger Dead time timer n = 1 to 255 INV15 Reload Trigger Counter (One-shot timer mode) TQ INV11 Timer A1 one-shot pulse V-phase output control circuit V-phase output signal V-phase output signal DQ T DQ T Inverse control Inverse control V-phase output (internal signal) V-phase output (internal signal) When setting the TA1S bit to 0, signal is set to 0. TA2 register TA21 register Timer A2 reload control signal INV06 Trigger Trigger Dead Time Timer n = 1 to 255 INV15 Reload Trigger Counter (One-shot timer mode) TQ INV11 Timer A2 one-shot pulse W-phase output control circuit W-phase output signal W-phase output signal DQ T DQ T Inverse control Inverse control W-phase output (internal signal) W-phase output (internal signal) When setting the TA2S bit to 0, signal is set to 0. Note: 1. When the INV06 bit is set to 0 (triangular wave modulation mode), a transfer trigger is generated only at the first timer B2 underflow after writing to registers IDB0 and IDB1. INV07, INV06, INV01, INV00 : Bits in the INVC0 register INV16 to INV10 : Bits in the INVC1 register DUW0, DU0 : Bits in the IDB0 register DUW1, DU1 : Bits in the IDB1 register PWCOM : Bit in the TB2SC register Figure 19.1 Three-Phase Motor Control Timer Function Block Diagram 1 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 365 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function IVPCR1 Reset SD SQ R INV03 Data bus D Q R PFC0 PD8_0 INV04 (A) INV05 P8_0 port latch U-phase output (internal signal) 0 1 U (pin) PDRT The above diagram shows an example of U-phase. IVPCR1 INV03 to INV05 PD8_0 PFC0 PDRT, PDRU : Bit in the TB2SC register : Bits in the INVC0 register : Bit in the PD8 register : Bit in the PFCR register : Bits in the PDRF register 0 1 DQ T PDRU Figure 19.2 Three-Phase Motor Control Timer Function Block Diagram 2 Table 19.2 I/O Ports Pin Name I/O Type U, U, V, V, W, W Output SD Input (1) IDU, IDV, IDW Input (2) Function Three-phase PWM waveform output Forced cutoff input Position-data-retain function input Notes: 1. Set the port direction bits which share pins to 0 (input mode). When not using the three-phase output forced cutoff function, input a high-level signal to the SD pin. 2. Set the port direction bits which share pins to 0 (input mode). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 366 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.2 Registers Refer to “registers used and settings” in each mode for register and bit settings. Three-phase motor control timer function uses timers A1, A2, A4, and B2. For other registers related to A1, A2, A4, and B2, refer to 17. “Timer A” and 18. “Timer B”. Table 19.3 Register Structure Address 01DAh 0302h 0303h 0304h 0305h 0306h 0307h 0308h 0309h 030Ah 030Bh 030Ch 030Dh 030Eh 0318h 0328h 0329h 032Ah 032Bh 032Eh 032Fh 0334h 0335h 033Eh Register Name Three-Phase Protect Control Register Timer A1-1 Register Timer A2-1 Register Timer A4-1 Register Three-Phase PWM Control Register 0 Three-Phase PWM Control Register 1 Three-Phase Output Buffer Register 0 Three-Phase Output Buffer Register 1 Dead Time Timer Timer B2 Interrupt Generation Frequency Set Counter Position-Data-Retain Function Control Register Port Function Control Register Timer A1 Register Timer A2 Register Timer A4 Register Timer B2 Register Timer B2 Special Mode Register Register Symbol TPRC TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2 PDRF PFCR TA1 TA2 TA4 TB2 TB2SC After Reset 00h XXh XXh XXh XXh XXh XXh 00h 00h XX11 1111b XX11 1111b XXh XXh XXXX 0000b 0011 1111b XXh XXh XXh XXh XXh XXh XXh XXh XXXX XX00b REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 367 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.2.1 Timer B2 Register (TB2) Timer B2 Register (b15) b7 (b8) b0 b7 b0 Symbol TB2 Address 0335h to 0334h After Reset Undefined Function If setting value is n, counter frequency is Setting Range RW n+1 fj Timers A1, A2, and A4 start every time an underflow occurs. fj : Count source frequency 0000h to FFFFh RW Read and write in 16-bit units. Carrier wave cycle is determined by this counter. Timer B underflow is a one-shot trigger of timers A1, A2, and A4. In three-phase mode 1, the reload timing of the TB2 register can be selected by the PWCON bit in the TB2SC register. 19.2.2 Timer Ai, Ai-1 Register (TAi, TAi1) (i = 1, 2, 4) Timer Ai, Ai-1 Register (i = 1, 2, 4) (b15) b7 (b8) b0 b7 b0 Symbol TA1, TA2, TA4 TA11, TA21, TA41 Address 0329h to 0328h, 032Bh to 032Ah, 032Fh to 032Eh 0303h to 0302h, 0305h to 0304h, 0307h to 0306h Function Setting Range After Reset Undefined Undefined RW If the setting value is n, the timer stops when the nth count source is counted after a start trigger is generated. Output signals of each phase change when timers A1, A2, and A4 stop. 0000h to FFFFh WO Write to this register in 16-bit units. Use the MOV instruction to set registers TAi and TAi1. If the TAi or TAi1 register is set to 0000h, no counters start and no timer Ai interrupt is generated. The TAi or TAi1 register is used to determine waveforms of U-, V-, and W-phases. It is triggered by timer B underflow, and operates in one-shot timer mode. Registers TA1, TA2, and TA4 are used in sawtooth wave modulation mode and three-phase mode 0 of triangular wave modulation mode. Registers TA1, TA2, TA4, TA11, TA21, and TA41 are used in three-phase mode 1 of triangular wave modulation mode. When the INV15 bit in the INVC1 register is set to 0 (dead time enabled), some high- and low-side turnon signals, whose output level changes from inactive to active, switch the output level when the dead time timer stops. In three-phase mode 1, the value of the TAi1 register is first counted. Then the values of registers TAi and TAi1 are counted alternately. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 368 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.2.3 Three-Phase PWM Control Register 0 (INVC0) Three-Phase PWM Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol INVC0 Bit Symbol Bit Name Address 0308h Function b1 b0 After Reset 00h RW INV00 ICTB2 count condition select bit INV01 Three-phase motor control timer function enable bit Three-phase motor control timer output control bit 0 0 1 1 0 1 0 1 : Timer B2 underflow : Timer B2 underflow when timer A1 reload control signal is 0 : Timer B2 underflow when timer A1 reload control signal is 1 RW RW INV02 0 : Three-phase motor control timer function not used 1 : Three-phase motor control timer function used 0 : Three-phase motor control timer output disabled 1 : Three-phase motor control timer output enabled RW INV03 RW INV04 High- and low-side 0 : Simultaneous turn-on enabled simultaneous turn-on disable bit 1 : Simultaneous turn-on disabled High- and low-side 0 : Not detected simultaneous turn-on detect flag 1 : Detected Modulation mode select bit 0 : Triangular wave modulation mode 1 : Sawtooth wave modulation mode Transfer trigger is generated when the INV07 bit is set to 1. Trigger to the dead time timer is also generated when setting the INV06 bit to 1. Read as 0. RW INV05 RW INV06 RW INV07 Software trigger select bit RW Set the INVC0 register after the PRC1 bit in the PRCR register is set to 1 (write enabled). Rewrite bits INV00 to INV02, INV04, and INV06 when timers A1, A2, A4, and B2 are stopped. INV01-INV00 (ICTB Count Condition Select Bit) (b1-b0) Bits INV00 and INV01 are enabled only when the INV11 bit is set to 1 (three-phase mode 1). To set the INV01 bit to 1, set the value of the ICTB2 register first, and then set the INV01 bit to 1. Set the TAIS bit in the TABSR register (timer A1 count start flag) to 1 prior to the first timer B2 underflow. When the INV11 bit is 0 (three-phase mode 0), the timer B2 underflow is counted regardless of the values of bits INV01 and INV00. INV02 (Three-Phase Motor Control Timer Function Enable Bit) (b2) Set the INV02 bit to 1 to operate the dead time timer, U-, V- and, W-phase output control circuits and ICTB2 counter. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 369 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function INV03 (Three-Phase Motor Control Timer Output Control Bit) (b3) Conditions to become 0: • Reset • The INV04 bit is 1 (simultaneous turn-on disabled) and the INV05 bit is 1 (simultaneous turn-on detected). • The INV03 bit is set to 0 by a program. • A signal applied to the SD pin is low. INV05 (High- and Low-Side Simultaneous Turn-On Detect Flag) (b5) The INV05 bit cannot be set to 1 by a program. Set the INV04 bit to 0 as well when setting the INV05 bit to 0. INV06 (Modulation Mode Select Bit) (b6) The following table describes the influence the INV06 bit. Table 19.4 INV06 Bit Item Mode Transfer timing from registers IDB0 and IDB1 to three-phase output shift register Trigger timing of the dead time timer when the INV16 bit is 0 INV13 bit INV06 = 0 Triangular wave modulation mode Transferred once by generating a transfer trigger after setting registers IDB0 and IDB1 Falling edge of a one-shot pulse of the timers A1, A2, or A4 INV06 = 1 Sawtooth wave modulation mode Transferred every time a transfer trigger is generated • Falling edge of a one-shot pulse of the timer A1, A2, or A4 • Transfer trigger Enabled when the INV11 bit is 1 and the Disabled INV06 bit is 0 One of the following conditions must be met to trigger a transfer: • Timer B2 underflows and a value is written to the INV07 bit • A value is written to the TB2 register when the INV10 bit is 1 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 370 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.2.4 Three-Phase PWM Control Register 1 (INVC1) Three-Phase PWM Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol INVC1 Bit Symbol Bit Name Address 0309h Function After Reset 00h RW INV10 Timer A1, A2 and A4 start trigger select bit Timer A1-1, A2-1 and A4-1 control bit Dead time timer count source select bit Carrier wave rise/fall detect flag Active level control bit 0 : Timer B2 underflow 1 : Timer B2 underflow and write to timer B2 0 : Three-phase mode 0 1 : Three-phase mode 1 0 : f1TIMAB or f2TIMAB 1 : f1TIMAB divided by 2 or f2TIMAB divided by 2 0 : Timer A1 reload control signal is 0. 1 : Timer A1 reload control signal is 1. 0 : Active low 1 : Active high 0 : Dead time enabled 1 : Dead time disabled 0 : Falling edge of one-shot pulse of timer (A4, A1 and A2) 1 : Rising edge of the three-phase output shift register (U-, V-, W-phase) output Set to 0 RW INV11 RW INV12 RW INV13 RO INV14 RW INV15 Dead time disable bit RW INV16 Dead time timer trigger select bit RW — (b7) Reserved bit RW Rewrite the INVC1 register after the PRC1 bit in the PRCR register is set to 1 (write enabled). Rewrite the INVC1 register while timers A1, A2, A4, and B2 are stopped. INV11 (Timer A1, A2 and A4 Start Trigger Select Bit) (b1) The following table lists items influenced by the INV11 bit. Table 19.5 INV11 Bit Item Mode Registers TA11, TA21 and TA41 Bits INV00 and INV01 in the INVC0 register INV13 bit Not used INV11 = 0 Three-phase mode 0 Used Enabled INV11 = 1 Three-phase mode 1 Disabled The ICTB2 counter is decremented whenever timer B2 underflows Disabled Enabled when INV11 is 1 and INV06 is 0 When the INV06 bit is set to 1 (sawtooth wave modulation mode), set the INV11 bit to 0 (three-phase mode 0). Also, when the INV11 bit is set to 0, set the PWCON bit in the TB2SC register to 0 (timer B2 is reloaded when timer B2 underflows). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 371 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function INV13 (Carrier Wave Rise/Fall Detect Flag) (b3) The INV13 bit is enabled only when the INV06 bit is set to 0 (triangular wave modulation mode) and the INV11 bit to 1 (three-phase mode 1). INV16 (Dead Time Timer Trigger Select Bit) (b6) If both of the following conditions are met, set the INV16 bit to 1 (rising edge of the three-phase output shift register output). • The INV15 bit is set to 0 (dead time timer enabled) • The Dij bit and DiBj bit always have different values when the INV03 bit is set to 1 (three-phase control timer output enabled). (The high- and low-side signals always output opposite level signals at any time except dead time.) (i = U, V or W; j = 0, 1). If either of the above conditions is not met, set the INV16 bit to 0 (dead time timer is triggered on the falling edge of a one-shot pulse of timers). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 372 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.2.5 Three-Phase Output Buffer Register i (IDBi) (i = 0, 1) Three-Phase Output Buffer Register i (i = 0, 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol IDB0 IDB1 Bit Symbol DUi Bit Name U-phase output buffer i Address 030Ah 030Bh Function After Reset XX11 1111b XX11 1111b RW RW DUBi U-phase output buffer i Set the output logical value of the threephase output shift registers. The set value is reflected in each turn-on signal as follows: 0 : Active (on) 1 : Inactive (off) When read, the contents of the threephase output shift registers are read. RW DVi V-phase output buffer i RW DVBi V-phase output buffer i RW DWi W-phase output buffer i RW DWBi — (b7-b6) W-phase output buffer i RW No register bits. If necessary, set to 0. Read as undefined value — Values of registers IDB0 and IDB1 are transferred to the three-phase output shift register in response to a transfer trigger. After the transfer trigger occurs, the values written in the IDB0 register determine each phase output signal (internal signal) first. Then, the value written in the IDB1 register on the falling edge of timers A1, A2, and A4 one-shot pulse determines each phase output signal (internal signal). Reading registers IDB0 and IDB1 returns each phase output signal (internal signal). Therefore, the same value is returned regardless of which register is read. 19.2.6 Dead Time Timer (DTT) Dead Time Timer b7 b0 Symbol DTT Function Address 030Ch After Reset Undefined Setting Range 1 to 255 RW WO If a setting value is n, the count source is counted n times after the start trigger occurs, and then the timer stops. Use the MOV instruction to set the DTT register. The DTT register acts as a one-shot timer which delays the timing for a turn-on signal to be switched to its active level in order to prevent the upper and lower transistors from being turned on simultaneously. The DTT register is enabled when the INV15 bit in the INVC1 register is set to 0 (dead time enabled). No dead time can be set when the INV15 bit is set to 1 (dead time disabled). Select a trigger by the INV16 bit in the INVC1 register, and a count source by the INV12 bit in the INVC1 register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 373 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.2.7 Timer B2 Interrupt Generation Frequency Set Counter (ICTB2) Timer B2 Interrupt Generation Frequency Set Counter b7 b0 Symbol ICTB2 Function Address 030Dh After Reset Undefined Setting Range RW When a setting value is n, timer B2 interrupt is generated every nth count timer B2 underflow meets the condition selected by bits INV01 and INV00. No register bits. If necessary, set to 0 1 to 15 WO — Use the MOV instruction to set the ICTB2 register. If the INV01 bit in the INVC0 register is set to 1, set the ICTB2 register when the TB2S bit in the TABSR register is set to 0 (timer B2 counter stopped). If the INV01 bit is set to 0 and the TB2S bit to 1 (timer B2 counter start), do not set the ICTB2 register when timer B2 underflows. When bits INV01 and INV00 are 11b, the first interrupt is generated when timer B2 underflows n-1 times if a setting value in the ICTB2 counter is n. Subsequent interrupts are generated every n times timer B2 underflows. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 374 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.2.8 Timer B2 Special Mode Register (TB2SC) Timer B2 Special Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TB2SC Bit Symbol PWCON Bit Name Timer B2 reload timing switch bit Address 033Eh Function After Reset XXXX XX00b RW RW 0 : Timer B2 underflow 1 : Timer A output at odd-numbered occurrences 0 : Three-phase output forced cutoff by SD input (high-impedance) disabled 1 : Three-phase output forced cutoff by SD input (high-impedance) enabled Set to 0 IVPCR1 Three-phase output port SD control bit 1 RW — (b6-b2) — (b7) Reserved bits RW No register bits. If necessary, set to 0. Read as 0 — Write to this register after the PRC1 bit in the PRCR register is set to 1 (write enabled). PWCON (Timer B2 Reload Timing Switch Bit) (b0) If the INV11 bit is 0 (three-phase mode 0) or the INV06 bit is 1 (sawtooth wave modulation mode), set the PWCON bit to 0 (timer B2 underflow). IVPCR1 (Three-Phase Output Port SD Control Bit 1) (b1) Related pins are U, U, V, V, W, and W. If a low-level signal is applied to the SD pin when the IVPCR1 bit is 1, three-phase motor control timer output is disabled (INV03 = 0). Then, the target pins go to a high-impedance state regardless of which functions of those pins are being used. After forced cutoff, input a high-level signal to the SD pin and set the IVPCR1 bit to 0 to cancel forced cutoff. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 375 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.2.9 Position-Data-Retain Function Control Register (PDRF) Position-Data-Retain Function Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PDRF Address 030Eh After Reset XXXX 0000b Bit Symbol Bit Name Function RW PDRW Input level at IDW pin is retained. W-phase position data retain 0: Low level bit 1: High level V-phase position data retain bit Input level at IDV pin is retained. 0: Low level 1: High level RO PDRV RO PDRU Input level at IDU pin is retained. U-phase position data retain 0: Low level bit 1: High level Retain-trigger polarity select bit Select polarity of a retain-trigger 0: Rising edge of high-side output signal 1: Falling edge of high-side output signal RO PDRT — (b7-b4) RW No register bits. If necessary, set to 0. Read as undefined value RW This register is valid in three-phase mode only. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 376 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.2.10 Port Function Control Register (PFCR) Port Function Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PFCR Bit Symbol Bit Name Address 0318h Function After Reset 0011 1111b RW PFC0 Port P8_0 output function select bit Port P8_1 output function select bit Port P7_2 output function select bit Port P7_3 output function select bit Port P7_4 output function select bit Port P7_5 output function select bit 0: Input/output port P8_0 1: Three-phase PWM output (U-phase output) 0: Input/output port P8_1 1: Three-phase PWM output (U-phase output) 0: Input/output port P7_2 1: Three-phase PWM output (V-phase output) 0: Input/output port P7_3 1: Three-phase PWM output (V-phase output) 0: Input/output port P7_4 1: Three-phase PWM output (W-phase output) 0: Input/output port P7_5 1: Three-phase PWM output (W-phase output) RW PFC1 RW PFC2 RW PFC3 RW PFC4 RW PFC5 — (b7-b6) RW No register bits. If necessary, set to 0. Read as 0 — This register is valid only when the INV03 bit in the INVC0 register is set to 1 (three-phase motor control timer output enabled). Write to this register after the TPRC0 bit in the TPRC register is set to 1 (write enabled). 19.2.11 Three-Phase Protect Control Register (TPRC) Three-Phase Protect Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TPRC Bit Symbol Bit Name Address 01DAh Funtion Enable write to the PFCR register 0: Write disabled 1: Write enabled After Reset 00h RW TPRC0 — (b7-b1) Three-phase protect control bit RW No register bits. If necessary, set to 0. Read as 0 — Once the TPRC0 bit is set to 1 (write enabled) by a program, the set value 1 is retained. To change the registers protected by this bit, follow the steps below. (1) Set the TPRC0 bit to 1. (2) Set values in the PFCR register. (3) Set the TPRC0 bit to 0 (write disabled). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 377 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.3 19.3.1 Operations Common Operations in Multiple Modes Carrier Wave Cycle Control 19.3.1.1 Timer B2 controls the cycle of the carrier wave. In triangular wave modulation mode, the cycle of the carrier wave is double the cycle of timer B2 underflow. In sawtooth wave modulation mode, the cycle of carrier wave equals to the cycle of timer B2 underflow. Figure 19.3 shows Relationship between Carrier Wave Cycle and Timer B2. Timer B2 underflow is a start trigger for timers A1, A2, and A4, which control the three-phase PWM waveform. However, when the INV10 bit in the INVC1 register is 1, writing to the TB2 register also generates a trigger for timers A1, A2, and A4. The frequency of timer B2 interrupt requests can be selected for three-phase motor control timers. In triangular wave modulation three-phase mode 0 and sawtooth wave modulation mode, when a setting value in the ICTB2 register is n, the timer B2 interrupt request is generated every nth count of timer B2 underflow. In triangular wave modulation three-phase mode 1, when a setting value in the ICTB2 register is n, a timer B2 interrupt request is generated every nth time of the timing selected by bits INV01 and INV00 in the INVC1 register. However, when bits INV01 and INV00 are 11b, the first interrupt is generated at the n-1th time of timer B2 underflow. Triangular wave Carrier wave Signal wave Sawtooth wave Carrier wave Signal wave Cycle of timer B2 Timer B2 underflow signal Timer A1, A2 or A4 one-shot pulse Figure 19.3 Relationship between Carrier Wave Cycle and Timer B2 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 378 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.3.1.2 Three-Phase PWM Wave Control Timer A4 controls U- and U-phase waveforms, timer A1 controls V- and V-phase waveforms, and timer A2 controls W- and W-phase waveforms. Timer Ai (i = 1, 2, 4) starts counting by a trigger selected by the INV10 bit in the INVC1 register, and generates a one-shot pulse (internal signal). The output signal of each phase changes at the falling edge of the one-shot pulse. Triangular wave modulation three-phase mode 1 counts values in the TAi1 register and TAi register alternately, and generates a one-shot pulse. 19.3.1.3 Dead Time Control Due to delays in the transistors turning off, the upper and lower transistors are turned on simultaneously. To prevent this, there are three 8-bit dead time timers, one in each phase. The reload resistor is shared. When the INV15 bit in the INVC1 register is 0 (dead time enabled), the dead time set in the DTT register is valid. When the INV15 bit is 1 (dead time disabled), no dead time is set. Select a count source for the dead time timer by the INV12 bit in the INVC1 register. A trigger for the dead time timer can be selected by the INV16 bit in the INVC1 register. When both conditions below are met, set the INV16 bit to 1 (the rising edge of the three-phase output shift register is a trigger for the dead time timer). • The INV15 bit is 0 (dead time enabled). • The Dij bit and DiBj bit have different values whenever the INV03 bit is set to 1 (three-phase motor control timer output enabled) (i = U, V or W; j = 0, 1). (During the period except dead time, the highand low-side output signals always output opposite level signals.) If either of the conditions above is not met, set the INV16 bit to 0 (a trigger for the dead time timer is the falling edge of one-shot pulse of the timer). In sawtooth wave modulation mode, the generation of a transfer trigger causes a trigger for the dead time timer. 19.3.1.4 Output Level of Three-Phase PWM Output Pins Set a value in registers IDB0 and IDB1 to select the state of each high- or low-side output signal (either active (on) or not active (off)). The values of registers IDB0 and IDB1 are transferred to the three-phase output shift register by a transfer trigger. After a transfer trigger is generated, the value set in the IDB0 register becomes the first output signal of each phase (internal signal), and then at the falling edge of one-shot pulse of timer A1, A2, or A4 (internal signal), the value set in the IDB1 register becomes the output signal of each phase. A transfer trigger is generated under any of the following conditions: • At the first timer B2 underflow after registers IDB0 and IDB1 are written (in triangular wave modulation mode) • Each time timer B2 underflows (in sawtooth wave modulation mode) • Writing to the TB2 register (when the INV10 bit in the INVC1 register is 1) • Setting the INV07 bit in the INVC0 register to 1 (software trigger) The active level can be selected by the INV14 bit in the INVC1 register. Table 19.6 Output Level of Three-Phase PWM Output Pins Value Set in Registers IDB0 and IDV1 0 (active (on)) 1 (not active (off)) Output Signal of Each Phase (Internal Signal) 0 1 Value Set in INV14 Bit in INVC1 Register 0 (active, low level) Low High 1 (active, high level) High Low REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 379 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.3.1.5 Simultaneous Conduction Prevention This function prevents the upper and lower output signals from being active simultaneously due to program errors or an unexpected program operation. When the high- and low-side output signals become active at the same time while the simultaneous conduction is disabled by the INV04 bit in the INVC0 register, the following occur: • The INV03 bit in the INVC0 register becomes 0 (three-phase motor control timer output disabled). • The INV05 bit in the INVC0 register becomes 1 (simultaneous conduction detected). • Pins U, U, V, V, W, and W go to a high-impedance state. 19.3.1.6 Three-Phase PWM Waveform Output Pins Pins U, U, V, V, W, and W output the PWM waveform under the following conditions: • The INVC02 bit in the INVC0 register is 1 (three-phase motor control timer function). • The INVC03 bit is 1 (three-phase motor control timer output enabled). • The PFCi bit in the PFCR register is 1 (three-phase PWM output (selected independently for each pin)). The three-phase output forced cutoff by the SD pin is available. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 380 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.3.1.7 Three-Phase PWM Output Pin Select Pins U, U, V, V, W, and W output the three-phase PWM waveform when the PFCi bit (i = 0 to 5) in the PFCR register is 1 (three-phase PWM output). When the PFCi bit is 0 (I/O port), these pins are used as I/O ports (or other peripheral function I/O ports). Therefore, while some of the six pins output the three-phase PWM waveform, the other pins can be used as I/O ports (or other peripheral function I/O ports). The PFCR register can be rewritten when the TPRC0 bit in the TPRC register is 1 (write to the PFCR register enabled). The functions of the three-phase PWM waveform output pins are protected from being rewritten due to an unexpected program operation. To prevent rewrite, follow these steps: (1) Set the TPRC0 bit to 1. (2) Rewrite the PFCR register. (3) Set the TPRC0 bit to 0 (write to the PFCR register disabled). Figure 19.4 shows Usage Example of Three-Phase Output and I/O Port Switch Function. Timer B2 U-pin output V-pin output Functions as a port W-pin output Functions as a port Write to the PFCR register PFC0 bit = 1 PFC2 bit = 1 PFC4 bit = 0 Write to the PFCR register PFC0 bit = 1 PFC2 bit = 0 PFC4 bit = 1 The above applies under the following conditions. The output data of the ports which share a pin with pins V and W respectively are both 0 (low-level). The direction bits of the ports which share a pin with pins V and W respectively are both 1 (output mode). Figure 19.4 Usage Example of Three-Phase Output and I/O Port Switch Function REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 381 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.3.1.8 Three-Phase Output Forced Cutoff Function While the INV02 bit in the INVC0 register is 1 (three-phase motor control timer function) and the INV03 bit is 1 (three-phase motor control timer output enabled), when a low-level signal is applied to the SD pin, the INV03 bit in the INVC0 register becomes 0 (three-phase motor control timer output disabled), and pins corresponding to U, U, V, V, W and W outputs change all together as follows: • When the IVPCR1 bit in the TB2SC register is 1 (three-phase output forced cutoff enabled) High-impedance state • When the IVPCR1 bit in the TB2SC register is 0 (three-phase output forced cutoff disabled) I/O ports or other peripheral function I/O ports However, applying a low-level signal to the SD pin while the IVPCR1 bit is 1 places the pins in a highimpedance state even when the pins are used as functions other than U, U, V, V, W and W outputs. Table 19.7 lists State of Pins U, U, V, V, W, and W. Table 19.7 State of Pins U, U, V, V, W, and W State of Bit and Pin IVPCR1 bit in TB2SC register 1 0 Note: 1. SD input Function or State of Pins U, U, V, V, W and W Three-phase PWM output High-impedance Three-phase PWM output I/O port or other peripheral functions High Low High Low In the above case, bits INVC02, INVC03 and PFCi are all 1. The digital filter is available for the SD pin. When the value of bits NMIDF2 to NMIDF0 in the NMIDF register is other than 000b (digital filter enabled), the SD level is sampled for every sampling clock. When the same sampled level is detected three times in a row, the level is transferred to the internal circuit. Refer to 13.4.3 “NMI/SD Digital Filter”. To return the pin function to the three-phase PWM output after the forced cutoff, follow these steps below: (1) Apply a high-level signal to the SD pin. (2) Wait for more than three cycles of the digital filter sampling clock. (3) Set the INV03 bit in the INVC0 register to 1 (three-phase motor control timer output enabled). (4) Confirm that the INV03 bit is 1. If the bit is 0, return to step 3. (5) Set the IVPCR1 bit to 0 (three-phase output forced cutoff disabled). (6) Set the IVPCR1 bit to 1 (when enabling three-phase output forced cutoff again). When not using the three-phase output forced cutoff function, set a port direction bit which shares the pin with SD input to 0 (input port), and apply a high-level signal to the SD pin. The same pin is used for both SD input and NMI input. To disable the NMI interrupt, set the PM24 bit in the PM2 register to 0 (NMI interrupt disabled). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 382 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.3.1.9 Position-Data-Retain Function Three position-data input pins for U-, V-, and W-phases are available. Input levels of IDU, IDV and IDW inputs are retained. The falling edge or rising edge of the high-side output signal of each phase can be selected by the PDRT bit in the PDRF register as a position-data-retain trigger. For example, in the case of U-phase, when the U-phase trigger is generated, the state at the IDU pin is transferred to the PDRU bit in the PDRF register. Until the next trigger of the U-phase waveform output, the value is retained. Figure 19.5 shows Usage Example of Position-Data-Retain Function (U-Phase). Carrier wave U-phase waveform output (internal signal) U-phase waveform output (internal signal) IDU pin PDRU bit in the PDRF register (U-phase position data retain bit) Transfer Transfer Transfer Transfer The above applies under the following conditions: The INV06 bit in the INVC0 register is 0 (triangular wave modulation mode). The PDRT bit in the PDRF register is 0 (the falling edge of upper energization signal is a trigger). Figure 19.5 Usage Example of Position-Data-Retain Function (U-Phase) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 383 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.3.2 Triangular Wave Modulation Three-Phase Mode 0 Triangular wave modulation uses the timer B2 cycle as a reference cycle. Table 19.8 lists Three-Phase Mode 0 Specifications, and Figure 19.6 shows Usage Example of Three-Phase Mode 0. Table 19.8 Three-Phase Mode 0 Specifications Item Carrier wave cycle Specification (m + 1) × 2 ---------------------------fi m: Setting value of the TB2 register, 0 to FFFFh fi: Count source frequency (f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB, f64TIMAB, fOCO-F, fOCO-S, fC32) Three-phase PWM output width n×2 -----------fi Detection of a carrier wave cycle (first half or last half) i = 1, 2, 4 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 384 of 791 Differences from three-phase mode 1 Reference cycle Timer B2 reload timing Three-phase PWM waveform control Timer B2 interrupt n: Setting value of the TAi register, 1 to FFFFh fi: Count source frequency (f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB, f64TIMAB, fOCO-F, fOCO-S, fC32) Timer B2 cycle (one-half cycle of the carrier wave) Timer B2 underflow Counts the value of the TAi register every time a timer Ai start trigger is generated (the TAi1 register is not used). When the setting value in the ICTB2 register is n, a timer B2 interrupt request is generated every nth time of timer B2 underflow (no bits INV00 and INV01 in the INVC1 register). Not detected (the INV13 bit in the INVC1 register is invalid). Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function Table 19.9 Register INVC0 Registers Used and Settings in Three-Phase Mode 0 (1/2) Bit INV00 INV01 INV02 INV03 INV04 INV05 INV06 INV07 1 (three-phase motor control timer function used) 1 (three-phase motor control timer output enabled) Select simultaneous conduction enabled or disabled. Simultaneous conduction detect flag Set to 0 (triangular wave modulation mode). Software trigger bit Select a start trigger for timers A1, A2, and A4. Set to 0 (three-phase mode 0). Select a count source for the dead time timer. Invalid Select the active level (either active high or active high). Select the dead time enabled or disabled. Select a trigger for the dead time timer. Set to 0. Set an output logic of the three-phase output shift register. Set the dead time. Set the frequency of timer B2 interrupts. Set to 0 (timer B2 underflow). Select three-phase output forced cutoff enabled or disabled. Set to 0. Position-data-retain bit Select a position-data-retain trigger. Select I/O port or three-phase PWM output. Set to 1 when writing to the PFCR register, or to 0 when not writing to it. Set the one-shot pulse width. Not used. Set one-half cycle of the carrier wave. 01b (when using V-phase output control circuit) 01b (when using W-phase output control circuit) Not used for three-phase motor control timer. 01b (when using U-phase output control circuit) Functions, Setting Value Invalid (Despite the settings, the ICTB2 register counts timer B2 underflow.) INVC1 INV10 INV11 INV12 INV13 INV14 INV15 INV16 7 IDB0, IDB1 DTT ICTB2 TB2SC 5 to 0 7 to 0 3 to 0 PWCON IVPCR1 b7 to b2 PDRF PDRU, PDRV, PDRW PDRT PFC5 to PFC0 TPRC0 15 to 0 15 to 0 15 to 0 TA1TGH to TA1TGL TA2TGH to TA2TGL TA3TGH to TA3TGL TA4TGH to TA4TGL PFCR TPRC TA1, TA2, TA4 TA11, TA21, TA41 TB2 TRGSR i = 1, 2, 4 Note: 1. This table does not show the procedures. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 385 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function Table 19.10 Register TABSR Registers Used and Settings in Three-Phase Mode 0 (2/2) Bit TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Functions, Setting Value Not used for three-phase motor control timer. Set to 1 when starting counting, and to 0 when stopping counting. Set to 1 when starting counting, and to 0 when stopping counting. Not used for three-phase motor control timer. Set to 1 when starting counting, and to 0 when stopping counting. Not used for three-phase motor control timer. Not used for three-phase motor control timer. Set to 1 when starting counting, and to 0 when stopping counting. Set to 10b (one-shot timer mode). Set to 0. Set to 0. 1 (Select a trigger by bits TAiTGH and TAiTGL.) Set to 0. Select a count source. Set to 00b (timer mode). Set to 00b. Set to 0. Set to 0. Select a count source. Select a count source. Select a clock prior to timer AB division. Select a count source. Select a count source. Set to 0. Set to 0. TA1MR, TA2MR, TA4MR TMOD1 to TMOD0 MR0 MR1 MR2 MR3 TCK1 to TCK0 TB2MR TMOD1 to TMOD0 MR1 to MR0 4 MR3 TCK1 to TCK0 PCLKR TCKDIVC0 TACS0 to TACS2 TBCS1 TAPOFS UDF PCLK0 TCDIV00 7 to 0 TCS3 to TCS0 POFSi TAiP i = 1, 2, 4 Note: 1. This table does not show the procedures. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 386 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function Triangular Waveform as a Carrier Wave Carrier wave Signal wave TB2S bit in TABSR register Timer B2 Timer A1 reload control signal (1) IR bit in TB2IC register (timer B2 interrupt request) TA4 register Reload register Timer A4 start trigger signal (1) a’ Timer A4 one-shot pulse (1) U-phase output signal (1) Rewrite of registers IDB0 and IDB1 U-phase output signal (1) a’ a’ a a b’ b’ b b c' c’ c c d’ d’ d d a b’ b c’ c d’ d The rewritten values are reflected at this point. Dead time timer output (1) U-pin output U-pin output Dead time INV14 = 0 (Active low) INV14 = 1 (Active high) U-pin output U-pin output The above applies under the following conditions. The INVC0 register - The INV02 bit is 1 (three-phase motor control timer function used). - The INV03 bit is 1 (three-phase motor control timer output enabled). - The INV06 bit is 0 (triangular wave modulation mode). The INVC1 register - The INV16 bit is 1 (The dead time timer is triggered on the rising edge of the three-phase output shift register). - The INV15 bit is 0 (dead time timer enabled). - The INV11 bit is 0 (three-phase mode 0). - The INV10 bit is 0 (Timer B2 underflow is a start trigger for timers A1, A2 and A4 ). The ICTB2 register is 1h (Timer B interrupt request is generated at every timer B2 underflow.). The PWCOM bit in the TB2CS register is 0 (timer B2 reload at the timing of timer B2 underflow) Bits PFC1 and PFC0 in the PFCR register are 11b (U-, U-phase outputs). The TA4 register - Initial value : a’ - Changes at every timer B2 interrupt 1st : a, 2nd : b’, 3rd : b, 4th: c’, 5th : c, 6th : d’, 7th : d Registers IDB0 and IDB1 - Initial values : DU0 = 1, DUB0 = 0, DU1 = 0, DUB1 = 1 - The values are changed to DU0 = 1, DUB0 = 0, DU1 = 1, DUB1 = 0 at the 6th timer B2 interrupt. Note: 1. Internal signal. Refer to Figure 19.1. Figure 19.6 Usage Example of Three-Phase Mode 0 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 387 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.3.2.1 Three-Phase PWM Wave Output Timing Control In three-phase mode 0, when a start trigger for timers A1, A2, and A4 is generated, the counter starts counting the value of the TAi register (i = 1, 2, 4). 19.3.2.2 Three-Phase PWM Waveform Output Level Control In triangular wave modulation mode, the output levels set in registers IDB0 and IDB1 are transferred to the three-phase output shift register by a transfer trigger. After a transfer trigger is generated, first the value set in the IDB0 register, and then, at the falling edge of one-shot pulse for timers A1, A2, and A4, the values set in the IDB1 register become output signals for each phase (internal signal) and consequently the three-phase PWM output changes. Afterward, the values in registers IDB0 and IDB1 alternately become an output signal for each phase at every falling edge of the one-shot pulse for timers A1, A2 and A4. When the INV15 bit in the INVC1 register is 0 (dead time enabled), a phase changing from active to nonactive changes simultaneously with output signals for each phase (internal signal), while a phase changing from nonactive to active changes when the dead time timer stops. A transfer trigger is generated under the following conditions: • The first timer B2 underflow after registers IDB0 and IDB1 are written • Writing to the TB2 register (when the INV10 bit in the INVC1 register is 1) • Setting the INV07 bit in the INVC0 register to 1 (software trigger) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 388 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.3.3 Triangular Wave Modulation Three-Phase Mode 1 Triangular wave modulation uses twice the cycles of timer B2 as a reference cycle. Table 19.11 lists Three-Phase Mode 1 Specifications, and Figure 19.7 shows Usage Example of Three-Phase Mode 1. Table 19.11 Three-Phase Mode 1 Specifications Item Carrier wave cycle Specification (m + 1) × 2 ---------------------------fi m: Setting value of the TB2 register, 0 to FFFFh fi: Count source frequency (f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB, f64TIMAB, fOCO-F, fOCO-S, fC32) Three-phase PWM output width n×2 -----------fi n: Setting value of the TAi register, 1 to FFFFh fi: Count source frequency (f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB, f64TIMAB, fOCO-F, fOCO-S, fC32) Differences Reference cycle Twice the cycle of timer B2 (cycle of the carrier wave) from Timer B2 reload timing Select either of the following: three• Timer B2 underflow phase • Timer A output at an odd number of times mode 0 Three-phase PWM Counts the values of registers TAi and TAi1 alternately every time waveform control the Timer Ai start trigger is generated Timer B2 interrupt Select a count timing for the ICTB2 register: • Timer B2 underflow • When the INV13 bit changes its value from 0 to 1 • When the INV13 bit changes its value from 1 to 0 When the setting value in the ICTB2 register is n, the timer B2 interrupt request is generated every nth time of the timing selected by bits INV00 and INV01 in the INVC1 register. Detection of a carrier Detected wave cycle (The INV13 bit in the INVC1 register is valid.) (first half or last half) i = 1, 2, 4 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 389 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function Table 19.12 Register INVC0 Registers Used and Settings in Three-Phase Mode 1 (1/2) Bit INV00 INV01 INV02 INV03 INV04 INV05 INV06 INV07 1 (three-phase motor control timer function used) 1 (three-phase motor control timer output enabled) Select simultaneous conduction enabled or disabled. Simultaneous conduction detect flag Set to 0 (triangular wave modulation mode). Software trigger bit Select a start trigger for timers A1, A2, and A4. Set to 1 (three-phase mode 1). Select a count source for the dead time timer. Carrier wave state detect flag Select the active level (either active high or active high). Select the dead time enabled or disabled. Select a trigger for the dead time timer. Set to 0. Set an output logic of the three-phase output shift register. Set the dead time. Set the frequency of timer B2 interrupts. Select timer B2 reload timing. Select three-phase output forced cutoff enabled or disabled. Set to 0. Position-data-retain bit Select a position-data-retain trigger. Select I/O port or three-phase PWM output. Set to 1 when writing to the PFCR register, or to 0 when not writing to it. Set the one-shot pulse width. Set the one-shot pulse width. Set one-half cycle of the carrier wave. Functions, Setting Value Select the timing that the ICTB2 register starts counting. INVC1 INV10 INV11 INV12 INV13 INV14 INV15 INV16 7 IDB0, IDB1 DTT ICTB2 TB2SC 5 to 0 7 to 0 3 to 0 PWCON IVPCR1 b7 to b2 PDRF PDRU, PDRV, PDRW PDRT PFC5 to PFC0 TPRC0 15 to 0 15 to 0 15 to 0 PFCR TPRC TA1, TA2, TA4 TA11, TA21, TA41 TB2 i = 1, 2, 4 Note: 1. This table does not show the procedures. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 390 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function Table 19.13 Register TRGSR Registers Used and Settings in Three-Phase Mode 1 (2/2) Bit TA1TGH to TA1TGL TA2TGH to TA2TGL TA3TGH to TA3TGL TA4TGH to TA4TGL Functions, Setting Value 01b (when using V-phase output control circuit) 01b (when using W-phase output control circuit) (Not used for three-phase motor control timer.) 01b (when using U-phase output control circuit) Not used for three-phase motor control timer. Set to 1 when starting counting, and to 0 when stopping counting. Set to 1 when starting counting, and to 0 when stopping counting. Not used for three-phase motor control timer. Set to 1 when starting counting, and to 0 when stopping counting. Not used for three-phase motor control timer. Not used for three-phase motor control timer. Set to 1 when starting counting, and to 0 when stopping counting. Set to 10b (one-shot timer mode). Set to 0. Set to 0. 1 (Select a trigger by bits TAiTGH and TAiTGL.) Set to 0. Select a count source. Set to 00b (timer mode). Set to 00b. Set to 0. Set to 0. Select a count source. Select a count source. Select a clock prior to timer AB division. Select a count source. Select a count source. Set to 0. Set to 0. TABSR TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S TA1MR, TA2MR, TA4MR TMOD1 to TMOD0 MR0 MR1 MR2 MR3 TCK1 to TCK0 TB2MR TMOD1 to TMOD0 MR1 to MR0 4 MR3 TCK1 to TCK0 PCLKR TCKDIVC0 TACS0 to TACS2 TBCS1 TAPOFS UDF PCLK0 TCDIV00 7 to 0 TCS3 to TCS0 POFSi TAiP i = 1, 2, 4 Note: 1. This table does not show the procedures. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 391 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function Triangular Waveform as a Carrier Wave Carrier wave Signal wave TB2S bit in TABSR register Timer B2 Timer A1 reload control signal (1) INV13 bit IR bit in TB2IC register (timer B2 interrupt request) TA4 register TA41 register Reload register Timer A4 start trigger signal (1) a’ Timer A4 one-shot pulse (1) U-phase output signal (1) Rewrite of registers IDB0 and IDB1 U-phase output signal (1) Dead time timer output (1) U-pin output U-pin output Dead time The rewritten values are reflected at this point. a b’ b c’ c d’ d a’ a a’ a a’ b’ b b’ b b’ c’ c c’ c c’ d’ d d’ d d’ INV14 = 0 (Active low) INV14 = 1 (Active high) U-pin output U-pin output The above applies under the following conditions: The INVC0 register - The INV02 bit is 1 (three-phase motor control timer function used). - The INV03 bit is 1 (three-phase motor control timer output enabled). - The INV06 bit is 0 (triangular wave modulation mode). - The INV01 bit is 0 and the ICTB2 register is 2h (timer B2 interrupt at every second timer B2 underflow) or bits INV01 and INV00 are 11b and the ICTB2 register is 1h (timer B2 interrupt at timer B2 underflow while the timer A1 reload control signal is 1). The INVC1 register - The INV16 bit is 1 (The dead time timer is triggered on the rising edge of the three-phase output shift register). - The INV15 bit is 0 (dead time timer enabled). - The INV11 bit is 1 (three-phase mode 1). - The INV10 bit is 0 (Timer B2 underflow is a start trigger for timers A1, A2 and A4 ). The PWCOM bit in the TB2CS register is 0 (timer B2 reload at the timing of timer B2 underflow) Bits PFC1 and PFC0 in the PFCR register are 11b (U-, U-phase outputs). Registers TA4 and TA41 - Initial value: TA41 = a’, TA4 = a - Registers TA4 and TA41 change at every timer B2 interrupt 1st : TA41 = b’, TA4 = b, 2nd : TA41 = c’, TA4 = c, 3rd: TA41 = d’, TA4 = d Registers IDB0 and IDB1 - Initial values: DU0 = 1, DUB0 = 0, DU1 = 0, DUB1 = 1 - The values are changed to DU0 = 1, DUB0 = 0, DU1 = 1, DUB1 = 0 at the 3rd timer B2 interrupt. Note: 1. Internal signal. Refer to Figure 19.1. Figure 19.7 Usage Example of Three-Phase Mode 1 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 392 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.3.3.1 The INV13 Bit in the INVC1 Register In three-phase mode 1, the INV13 bit can be used to detect whether the cycle of the carrier wave is the first half or the last half. The INV13 bit is a flag which checks the state of timer A1 reload control signals. Timer A1 reload control signal becomes 0 while timer A1 is stopped, and the value is reversed at every start trigger signal for timers A1, A2, and A4. Thus, if the cycle of carrier wave starts at the first timer B2 underflow, the first half comes when the INV13 bit is 1, and the last half comes when it is 0. Table 19.14 lists The Relations of the INV13 Bit with Other Factors. Table 19.14 The Relations of the INV13 Bit with Other Factors INV13 bit Timer A1 reload control signal One-shot pulse count value Timer B2 underflow Carrier wave i = 1, 2, 4 1 Value at the TAi1 register At an odd number of times First half 0 Value at the TAi register At an even number of times Last half REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 393 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.3.3.2 Three-Phase PWM Waveform Output Timing Control In three-phase mode 1, a start trigger for timers A1, A2, and A4 is generated, the value set in the TAi1 register is counted first. Afterward, the values in registers TAi1 and TAi alternately are counted every time a start trigger for timers A1, A2, and A4 is generated. When the values in registers TAi1 and TAi are rewritten during the process, the updated value is output from the next carrier wave cycle. Figure 19.8 shows Three-Phase Mode 1 Update Timing of Registers TAi and TAi1. Update when the INV13 bit is 1 The INV13 bit in the INVC1 register TAi register a Update by a program TAi1 register a’ b’ Transfer to the reload register by the next timer Ai start trigger. Reload register a’ a b’ b b’ b b’ b a’ Timer Ai1 one-shot pulse (internal signal) a b’ b b’ b Carrier wave cycle Update when the INV13 bit is 0 The INV13 bit in the INVC1 register TAi register a Update by a program TAi1 register a’ b’ Transfer to the reload register immediately. Reload register a’ a a’ b’ b b’ b b’ b a’ Timer Ai1 one-shot pulse (internal signal) a b’ b b’ b Carrier wave cycle Figure 19.8 Three-Phase Mode 1 Update Timing of Registers TAi and TAi1 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 394 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.3.3.3 Carrier Wave Control In three-phase mode 1, the reload timing of the TB2 register can be selected by the PWCON bit in the TB2SC register. 19.3.3.4 Three-Phase PWM Waveform Output Level Control In triangular wave modulation mode, the output levels set in registers IDB0 and IDB1 are transferred to the three-phase output shift register by a transfer trigger. After a transfer trigger is generated, first the value set in the IDB0 register, and then, at the falling edge of one-shot pulse for timers A1, A2, and A4, the values set in the IDB1 register become output signals for each phase (internal signal) and consequently the three-phase PWM output changes. Afterward, the values in registers IDB0 and IDB1 alternately become an output signal for each phase at every falling edge of one-shot pulse for timers A1, A2, and A4. When the INV15 bit in the INVC1 register is 0 (dead time enabled), a phase changing from active to nonactive changes simultaneously with output signals for each phase (internal signal), while a phase changing from nonactive to active changes when the dead time timer stops. A transfer trigger is generated under the following conditions: • The first timer B2 underflow after registers IDB0 and IDB1 are written • Writing to the TB2 register (when the INV10 bit in the INVC1 register is 1) • Setting the INV07 bit in the INVC0 register to 1 (software trigger) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 395 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.3.4 Sawtooth Wave Modulation Mode The sawtooth wave is modulated. Table 19.15 lists Sawtooth Wave Modulation Mode Specifications, and Figure 19.9 shows Usage Example of Sawtooth Wave Modulation Mode. Table 19.15 Sawtooth Wave Modulation Mode Specifications Item Carrier wave cycle Specification m+1 ------------fi m: Setting value of the TB2 register, 0 to FFFFh fi: Count source frequency (f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB, f64TIMAB, fOCO-F, fOCO-S, fC32) Three-phase PWM output width n -fi n: Setting value of the TAi register, 1 to FFFFh fi: Count source frequency (f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB, f64TIMAB, fOCO-F, fOCO-S, fC32) Differences Reference cycle Timer B2 cycle (one-half cycle of the carrier wave) from Timer B2 reload timing Timer B2 underflow triangular Three-phase PWM Counts the value of the TAi register every time the timer Ai start wave waveform control trigger is generated (the TAi1 register is not used). modulation The output levels set in registers IDB0 and IDB1 are transferred to mode the three-phase output shift register at every timer B2 underflow. Timer B2 interrupt When the setting value in the ICTB2 register is n, the timer B2 interrupt request is generated every nth time of timer B2 underflow (no bits INV00 and INV01 in the INVC1 register). Dead time timer trigger Both of the following: • Transfer trigger (generated at every timer B2 underflow) • Falling edge of timer Ai one-shot pulse Detection of a carrier wave cycle (first half or last half) i = 1, 2, 4 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 396 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function Table 19.16 Register INVC0 Registers Used and Settings in Sawtooth Wave Modulation Mode (1/2) Bit INV00 INV01 INV02 INV03 INV04 INV05 INV06 INV07 1 (three-phase motor control timer function used) 1 (three-phase motor control timer output enabled) Select simultaneous conduction enabled or disabled. Simultaneous conduction detect flag Set to 1 (sawtooth wave modulation mode). Software trigger bit Select a start trigger for timers A1, A2, and A4. Set to 0. Select a count source for the dead time timer. Invalid Select the active level (either active high or active high). Select the dead time enabled or disabled. Select a trigger for the dead time timer. Set to 0. Set an output logic of the three-phase output shift register. Set the dead time. Set the frequency of timer B2 interrupts. Set to 0 (timer B2 underflow). Select three-phase output forced cutoff enabled or disabled. Set to 0. Position-data-retain bit Select a position-data-retain trigger. Select I/O port or three-phase PWM output. Set to 1 when writing to the PFCR register, or to 0 when not writing to it. Set the one-shot pulse width. Not used Set the cycle of the carrier wave. Functions, Setting Value Invalid (despite the settings, the ICTB2 register counts timer B2 underflow) INVC1 INV10 INV11 INV12 INV13 INV14 INV15 INV16 7 IDB0, IDB1 DTT ICTB2 TB2SC 5 to 0 7 to 0 3 to 0 PWCON IVPCR1 b7 to b2 PDRF PDRU, PDRV, PDRW PDRT PFC5 to PFC0 TPRC0 15 to 0 15 to 0 15 to 0 PFCR TPRC TA1, TA2, TA4 TA11, TA21, TA41 TB2 i = 1, 2, 4 Note: 1. This table does not show the procedures. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 397 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function Table 19.17 Register TRGSR Registers Used and Settings in Sawtooth Wave Modulation Mode (2/2) Bit TA1TGH to TA1TGL TA2TGH to TA2TGL TA3TGH to TA3TGL TA4TGH to TA4TGL Functions, Setting Value 01b (when using V-phase output control circuit) 01b (when using W-phase output control circuit) (Not used for three-phase motor control timer.) 01b (when using U-phase output control circuit) Not used for three-phase motor control timer. Set to 1 when starting counting, and to 0 when stopping counting. Set to 1 when starting counting, and to 0 when stopping counting. Not used for three-phase motor control timer. Set to 1 when starting counting, and to 0 when stopping counting. Not used for three-phase motor control timer. Not used for three-phase motor control timer. Set to 1 when starting counting, and to 0 when stopping counting. Set to 10b (one-shot timer mode). Set to 0. Set to 0. 1 (select a trigger by bits TAiTGH and TAiTGL) Set to 0. Select a count source. Set to 00b (timer mode). Set to 00b. Set to 0. Set to 0. Select a count source. Select a count source. Select a clock prior to timer AB division. Select a count source. Select a count source. Set to 0. Set to 0. TABSR TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S TA1MR, TA2MR, TA4MR TMOD1 to TMOD0 MR0 MR1 MR2 MR3 TCK1 to TCK0 TB2MR TMOD1 to TMOD0 MR1 to MR0 4 MR3 TCK1 to TCK0 PCLKR TCKDIVC0 TACS0 to TACS2 TBCS1 TAPOFS UDF PCLK0 TCDIV00 7 to 0 TCS3 to TCS0 POFSi TAiP i = 1, 2, 4 Note: 1. This table does not show the procedures. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 398 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function Sawtooth Waveform as a Carrier Wave Carrier wave Signal wave TB2S bit in TABSR register Timer B2 IR bit in TB2IC register (timer B2 interrupt request) Timer A4 start trigger signal (1) Timer A4 one-shot pulse (1) Rewrite of registers IDB0 and IDB1 The rewritten values are reflected at this point. U-phase output signal (1) U-phase output signal (1) Dead time timer output (1) Dead time INV14 = 0 (Active low) U-pin output U-pin output U-pin output INV14 = 1 (Active high) U-pin output The above applies under the following conditions. The INVC0 register - The INV02 bit is 1 (three-phase motor control timer function used). - The INV03 bit is 1 (three-phase motor control timer output enabled). - The INV06 bit is 1 (sawtooth wave modulation mode). - The INV10 bit is 0 (Timer B2 underflow is a start trigger for timers A1, A2 and A4.). The INVC1 register - The INV11 bit is 0 and the ICTB2 register is 1h (Timer B interrupt request is generated at every timer B2 underflow.). - The INV15 bit is 0 (dead time timer enabled). - The INV16 bit is 0 (The dead time timer is triggered on the falling edge of timers A4, A1 and A2 one-shot pulse.). The PWCOM bit in the TB2CS register is 0 (timer B2 reload at the timing of timer B2 underflow) Bits PFC1 and PFC0 in the PFCR register are 11b (U-, U-phase outputs). Registers IDB0 and IDB1 - Initial values : DU0 = 0, DUB0 = 1, DU1 = 1, DUB1 = 1 - The values are changed to DU0 = 1, DUB0 = 1, DU1 = 1, DUB1 = 1 at the 3rd timer B2 interrupt. - The values are changed to DU0 = 1, DUB0 = 0, DU1 = 1, DUB1 = 1 at the 5th timer B2 interrupt. Note: 1. Internal signal. Refer to Figure 19.1. Figure 19.9 Usage Example of Sawtooth Wave Modulation Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 399 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.3.4.1 Three-Phase PWM Waveform Output Timing Control In sawtooth wave modulation mode, when a start trigger for timers A1, A2, and A4 is generated, the counter starts counting the value of the TAi register (i = 1, 2, 4). 19.3.4.2 Three-Phase PWM Waveform Output Level Control In sawtooth wave modulation mode, the output levels set in registers IDB0 and IDB1 are transferred to the three-phase output shift register by a transfer trigger. After a transfer trigger is generated, first the value set in the IDB0 register, and then at the falling edge of one-shot pulse for timers A1, A2, and A4, the value set in the IDB1 register become output signals for each phase (internal signal) and consequently the three-phase PWM output changes. Afterward, the following two actions are repeated: (1) The setting levels are transferred to the three-phase output shift register by a transfer trigger generated at timer B2 underflow, and therefore, the value in the IDB0 register becomes output signals for each phase. (2) The values set in the IDB1 register become output signals for each phase at the falling edge of one-shot pulse for timers A1, A2, and A4. When the INV15 bit in the INVC1 register is 0 (dead time enabled), a phase changing from active to nonactive changes simultaneously with output signals for each phase (internal signal), while a phase changing from nonactive to active changes when the dead time timer stops. A transfer trigger is generated under the following conditions: • Timer B2 underflow (each time) • Writing to the TB2 register (when the INV10 bit in the INVC1 register is 1) • Setting the INV07 bit in the INVC0 register to 1 (software trigger) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 400 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.4 Interrupts The timer B2 interrupt and timer A1, A2 and A4 interrupts are available for the three-phase motor control timer. 19.4.1 Timer B2 Interrupt When the setting value in the ICTB2 register is n, a timer B2 interrupt request is generated at the timings below. For details, refer to the specifications and usage examples of each mode. In triangular wave modulation three-phase mode 0 and sawtooth wave modulation mode, the interrupt request is generated at the nth count of timer B2 underflow (when setting value in the ICTB2 register is n). In triangular wave modulation three-phase mode 1, the interrupt request is generated at the nth count of the following timings selected by bits INV01 and INV00 in the INVC0 register: • Timer B2 underflow • When the INV13 bit changes its value from 0 to 1 • When the INV13 bit changes its value from 1 to 0 Refer to 14.7 “Interrupt Control” for details of interrupt control. Table 19.18 lists Timer B2 Interrupt Related Register. Table 19.18 Timer B2 Interrupt Related Register Address 005Ch Register Name Timer B2 Interrupt Control Register Register Symbol After Reset TB2IC XXXX X000b 19.4.2 Timers A1, A2 and A4 Interrupts A timer Ai interrupt request is generated at the falling edge of timer Ai (i = 1, 2, 4) one-shot pulse (internal signal). Refer to 14.7 “Interrupt Control” for details of interrupt control. Table 19.19 lists Timers A1, A2, and A4 Interrupts Related Registers. Table 19.19 Timers A1, A2, and A4 Interrupts Related Registers Address 0056h 0057h 0059h Register Name Timer A1 Interrupt Control Register Timer A2 Interrupt Control Register Timer A4 Interrupt Control Register Register Symbol After Reset TA1IC XXXX X000b TA2IC XXXX X000b TA4IC XXXX X000b In the timer Ai interrupt, when the TMOD1 bit in the TAiMR register is changed from 0 to 1 (from timer mode or event counter mode to one-shot timer mode, PWM mode or programmable output mode), the IR bit in the TAiIC register is sometimes automatically set to 1 (interrupt requested). Thus, when changing the TMOD1 bit, follow the steps below. Also refer to 14.13 “Notes on Interrupts”. (1) Set bits ILVL2 to ILVL0 in the TAiIC register to 000b (interrupt disabled). (2) Set the TAiMR register. (3) Set the IR bit in the TAiIC register to 0 (interrupt not requested). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 401 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 19. Three-Phase Motor Control Timer Function 19.5 19.5.1 Notes on Three-Phase Motor Control Timer Function Timer A, Timer B Refer to 17.5 “Notes on Timer A” and 18.5 “Notes on Timer B”. 19.5.2 Forced Cutoff Input The following pins are affected by the three-phase forced cutoff due to the SD pin input: P7_2/CLK2/TA1OUT/V, P7_3/CTS2/RTS2/TA1IN/V, P7_4/TA2OUT/W, P7_5/TA2IN/W, P8_0/TA4OUT/RXD5/SCL5/U, P8_1/TA4IN/CTS5/RTS5/U REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 402 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock 20. Real-Time Clock 20.1 Introduction The real-time clock generates a 1-second signal from a count source and counts seconds, minutes, hours, a.m./p.m., a day, and a week. It also detects matches with specified seconds, minutes, and hours. Table 20.1 lists Real-Time Clock Specifications, Figure 20.1 shows a Real-Time Clock Block Diagram, and Table 20.2 lists the I/O Port. Table 20.1 Real-Time Clock Specifications Item Count source Count operation Count start condition Count stop condition Interrupt request generation timing RTCOUT pin function Read from timer Write to timer Select function Specification f1, fC • Increment • Compare mode 1 or not using compare mode The count value is continuously used, and the count continues • Compare mode 2 When a compare match is detected, the count value is set to 0 and the count continues. • Compare mode 3 When a compare match is detected, the count value is set to 0 and the count stops. 1 (count starts) is written to the TSTART bit in RTCCR1 register 0 (count stops) is written to the TSTART bit in RTCCR1 register Select one of the following: • Update second data • Update minute data • Update hour data • Update day data • When day data is set to 000b • When the count data and the compare data match Programmable I/O ports or compare output When the RTCSEC, RTCMIN, RTCHR, or RTCWK register is read, the count value can be read. The values read from registers RTCSEC, RTCMIN, and RTCHR are represented by the BCD code. When bits TSTART and TCSTF in the RTCCR1 register are 0 (timer stopped), the RTCSEC, RTCMIN, RTCHR, and RTCWK registers can be written to. The values written to registers RTCSEC, RTCMIN, and RTCHR are represented by the BCD codes. • 12-hour mode / 24-hour mode switch function • Compare output Note: 1. In this manual, day refers to one day of the week. Refer to 20.2.4 “Real-Time Clock Day Data Register (RTCWK)” for details. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 403 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock RTCCMP0 RTCCMP1 RTCCSEC RTCCMIN RTCCHR PMCMP BSY HRIE MNIE SEIE TOENA RTCOUT pin Comparator Match Comparator Match Comparator Match Match Control Circuit RTC compare interrupt (IR bit in RTCCIC register) Comparator RTCCMP0 RTCCMP1 Write 1 RCS1, RCS0 f1 00b fC 10b TSTART R TCSTF SQ RTCPM Initialize RTCCMP1 1 sec generation circuit BSY RTCSEC Overflow RTCMIN Overflow RTCHR RTCWK “000b” RCS1, RCS0 RCS4 to RCS2 H12H24 Overflow DYIE HRIE MNIE WKIE RTC periodic interrupt (IR bit in RTCTIC register) SEIE TCSTF, TOENA, RTCPM, H12H24, TSTART SEIE, MNIE, HRIE, DYIE, WKIE, RTCCMP0, RTCCMP1 RCS4 to RCS0 : Bits in the RTCCSR register BSY : Bit in the RTCSEC register PMCMP : Bit in the RTCCHR register RTCWK RTCHR RTCMIN RTCSEC : Bits in the RTCCR1 register : Bits in the RTCCR2 register : Bits WK2 to WK0 in the RTCWK register : Bits HR11 to HR10 and HR03 to HR00 in the RTCHR register : Bits MN12 to MN10 and MN03 to MN00 in the RTCMIN register : Bits SC12 to SC10 and SC03 to SC00 in the RTCSEC register RTCCHR : Bits HCMP11 to HCMP10 and HCMP03 to HCMP00 in the RTCCHR register RTCCMIN : Bits MCMP12 to MCMP10 and MCMP03 to MCMP00 in the RTCCMIN register RTCCSEC : Bits SCMP12 to SCMP10 and SCMP03 to SCMP00 in the RTCCSEC register Figure 20.1 Real-Time Clock Block Diagram Table 20.2 I/O Port Pin Name RTCOUT I/O Type Output Function Compare output REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 404 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock 20.2 Registers Register Structure Table 20.3 Address 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0348h 0349h 034Ah Register Name Real-Time Clock Second Data Register Real-Time Clock Minute Data Register Real-Time Clock Hour Data Register Real-Time Clock Day Data Register Real-Time Clock Control Register 1 Real-Time Clock Control Register 2 Real-Time Clock Count Source Select Register Real-Time Clock Second Compare Data Register Real-Time Clock Minute Compare Data Register Real-Time Clock Hour Compare Data Register Register Symbol RTCSEC RTCMIN RTCHR RTCWK RTCCR1 RTCCR2 RTCCSR RTCCSEC RTCCMIN RTCCHR After Reset 00h X000 0000b XX00 0000b XXXX X000b 0000 X00Xb X000 0000b XXX0 0000b X000 0000b X000 0000b X000 0000b REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 405 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock 20.2.1 Real-Time Clock Second Data Register (RTCSEC) Real-Time Clock Second Data Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol RTCSEC Bit Symbol SC00 Bit Name Address 0340h Function After Reset 00h Setting Range RW RW SC01 1st digit of second count bit SC02 Count 0 to 9 every second. When the digit moves up, 1 is added to the 2nd digit of second RW 0 to 9 RW SC03 RW SC10 When counting 0 to 5, 60 seconds are counted RW SC11 2nd digit of second count bit 0 to 5 RW SC12 This bit is 1 while registers RTCSEC, RTCMIN, RTCHR or RTCWK are updated RW BSY Real-time clock busy flag RO SC03-SC00 (1st Digit of Second Count Bit) (b3-b0) SC12-SC10 (2nd Digit of Second Count Bit) (b6-b4) Set a value between 00 and 59 by the BCD codes. These bits become 00 at compare match in compare 2 mode and compare 3 mode. Write to bits SC12 to SC10 and SC03 to SC00 in the RTCSEC register when both bits TSTART and TCSTF in the RTCCR1 register are 0 (timer stops). Read when the BSY bit is 0 (not while data is updated). BSY (Real-Time Clock Busy Flag) (b7) This bit is 1 while data is updated. Read the following bits when the BSY bit is 0 (not while data is updated). • Bits SC12 to SC10 and SC03 to SC00 in the RTCSEC register • Bits MN12 to MN10 and MN03 to MN00 in the RTCMIN register • Bits HR11 to HR10 and HR03 to HR00 in the RTCHR register • Bits WK2 to WK0 in the RTCWK register REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 406 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock 20.2.2 Real-Time Clock Minute Data Register (RTCMIN) Real-Time Clock Minute Data Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol RTCMIN Bit Symbol MN00 Bit Name Address 0341h Function After Reset X000 0000b Setting Range RW RW MN01 1st digit of minute count bit MN02 Count 0 to 9 every minute. When the digit moves up, 1 is added to the 2nd digit of minute RW 0 to 9 RW MN03 RW MN10 When counting 0 to 5, 60 minutes are counted RW MN11 2nd digit of minute count bit 0 to 5 RW MN12 — (b7) RW Reserved bit Read as undefined value RO MN03-MN00 (1st Digit of Minute Count Bit) (b3-b0) MN12-MN10 (2nd Digit of Minute Count Bit) (b6-b4) Set a value between 00 and 59 by the BCD codes. These bits become 00 at compare match in compare 2 mode and compare 3 mode. Write to bits MN12 to MN10 and MN03 to MN00 in the RTCMIN register when both bits TSTART and TCSTF in the RTCCR1 register are 0 (timer stops). Read when the BSY bit in the RTCSEC is 0 (not while data is updated). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 407 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock 20.2.3 Real-Time Clock Hour Data Register (RTCHR) Real-Time Clock Hour Data Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol RTCHR Bit Symbol HR00 Bit Name Address 0342h Function After Reset XX00 0000b Setting Range RW RW HR01 1st digit of hour count bit HR02 Count 0 to 9 every hour. When the digit moves up, 1 is added to the 2nd digit of hour. RW 0 to 9 RW HR03 Count 0 to 1 when the H12H24 bit is set to 0 (12hour mode). Count 0 to 2 when the H12H24 bit is set to 1 (24-hour mode). RW HR10 2nd digit of hour count bit HR11 — (b6) — (b7) RW 0 to 2 RW No register bit. If necessary, set to 0. Read as undefined value — Reserved bit Read as undefined value RO HR03-HR00 (1st Digit of Hour Count Bit) (b3-b0) HR11-HR10 (2nd Digit of Hour Count Bit) (b5-b4) When the H12H24 bit in the RTCCR1 register is 0 (12-hour mode), set a value between 00 and 11 by BCD code. When the H12H24 bit in the RTCCR1 register is 1 (24-hour mode), set a value between 00 and 23 by the BCD codes. These bits become 00 at compare match in compare 2 mode and compare 3 mode. Write to bits HR11 to HR10 and HR03 to HR00 in the RTCHR register when both bits TSTART and TCSTF in the RTCCR1 register are 0 (timer stops). Read when the BSY bit in the RTCSEC register is 0 (not while data is updated). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 408 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock 20.2.4 Real-Time Clock Day Data Register (RTCWK) Real-Time Clock Day Data Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol RTCWK Bit Symbol WK0 Bit Name Address 0343h Function b2 b1 b0 After Reset XXXX X000b RW RW WK1 Day count bit WK2 — (b6-b3) — (b7) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : Day 1 1 : Day 2 0 : Day 3 1 : Day 4 0 : Day 5 1 : Day 6 0 : Day 7 1 : Do not set RW RW — No register bits. If necessary, set to 0. Read as undefined value Reserved bit Read as undefined value RO WK2-WK0 (Day Count Bit) (b2-b0) A week is counted by counting from 000b (Day 1) to 110b (Day 7) repeatedly. Do not set to 111b. These bits become 000b at compare match in compare 2 mode and compare 3 mode. Write to bits WK2 to WK0 in the RTCWK register when both bits TSTART and TCSTF in the RTCCR1 register are 0 (timer stops). Read when the BSY bit in the RTCSEC register is 0 (not while data is updated). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 409 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock 20.2.5 Real-Time Clock Control Register 1 (RTCCR1) Real-Time Clock Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol RTCCR1 Bit Symbol — (b0) TCSTF Bit Name Reserved bit Address 0344h Function Set to 0 0 : Count stopped 1 : Counting 0 : Compare output disabled 1 : Compare output enabled Set to 0 0 After Reset 0000 X00Xb RW RW Real-time clock count status flag RTCOUT pin output bit RO TOENA — (b3) RTCRST RW Reserved bit RW Real-time clock reset bit Setting this bit to 0 after setting it to 1 resets the real-time clock 0 : a.m. 1 : p.m. 0 : 12-hour mode 1 : 24-hour mode 0 : Count stops 1 : Count starts RW RTCPM A.m./p.m. bit RW H12H24 Operating mode select bit RW TSTART Real-time clock count start bit RW TCSTF (Real-Time Clock Count Status Flag) (b1) TSTART (Real-Time Clock Count Start Bit) (b7) The real-time clock has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates count start or stop. The real-time clock starts counting and the TCSTF bit becomes 1 (count starts) when the TSTART bit is set to 1 (count starts). It takes up to two cycles of the count source until the TCSTF bit becomes 1 after setting the TSTART bit to 1. During this time, do not access registers associated with the real-time clock (1) other than the TCSTF bit. Also, when setting the TSTART bit to 0 (count stops), the real-time clock stops counting and the TCSTF bit becomes 0 (count stops). It takes the time for up to three cycles of the count source until the TCSTF bit becomes 0 after setting the TSTART bit to 0. During this time, do not access registers associated with the real-time clock (1) other than the TCSTF bit. Note: 1. Registers associated with the real-time clock: RTCSEC, RTCMIN, RTCHR, RTCWK, RTCCR1, RTCCR2, and RTCCSR. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 410 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock RTCRST (Real-Time Clock Reset Bit) (b4) When setting this bit to 0 after setting it to 1, the following are set automatically. • The values are reset in registers RTCSEC, RTCMIN, RTCHR, RTCWK, RTCCR2, RTCCSR, RTCCSEC, RTCCMIN, and RTCCHR. • Bits TCSTF, RTCPM, H12H24, and TSTART in the RTCCR1 register become 0. RTCPM (A.M./P.M. Bit) (b5) Write to the RTCPM bit when both bits TSTART and TCSTF in the RTCCR1 register are 0 (timer stops). Read this bit when the BSY bit in the RTCSEC register is 0 (not while data is updated). The RTCPM bit is enabled when the H12H24 bit is 0 (12-hour mode) or 1 (24-hour mode). Set the RTCPM bit as below to set time while the H12H24 bit is 1. • Set the RTCPM bit to 0 when bits HR11 to HR10 and HR03 to HR00 in the RTCHR register are 00 to 11. • Set the RTCPM bit to 1 when bits HR11 to HR10 and HR03 to HR00 in the RTCHR register are 12 to 23. The RTCPM bit changes as follows while counting. • Becomes 0 when the RTCPM bit is 1 (p.m.) while the clock increments from 11:59:59 (23:59:59 for 24-hour mode) to 00:00:00. • Becomes 1 when the RTCPM bit is 0 (a.m.) while the clock increments from 11:59:59 to 00:00:00 (12:00:00 for 24-hour mode). Figure 20.2 shows Definition of Time Representation. Noon H12H24 bit = 1 (24-hour mode) H12H24 bit = 0 (12-hour mode) Contents of RTCHR Register 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 0 13 1 14 2 15 3 16 4 17 5 Contents of RTCPM bit Contents in RTCWK register 0 (a.m.) 000 (Day 1) 1 (p.m.) Date changes H12H24 bit = 1 (24-hour mode) H12H24 bit = 0 (12-hour mode) Contents of RTCHR Register 18 6 19 7 20 8 21 9 22 10 23 11 0 0 1 1 2 2 3 3 ... ... ... ... Contents of RTCPM bit Contents in RTCWK register 1 (p.m.) 000 (Day 1) 0 (a.m.) 001 (Day 2) Bits RTCPM and H12H24 : Bits in the RTCCR1 register The above applies to the case when count starts from 0 a.m.of day 1. Figure 20.2 Definition of Time Representation H12H24 (Operating Mode Select Bit) (b6) Write to the H12H24 bit when both bits TSTART and TCSTF in the RTCCR1 register are 0 (timer stops). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 411 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock 20.2.6 Real-Time Clock Control Register 2 (RTCCR2) Real-Time Clock Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol RTCCR2 Bit Symbol Bit Name Address 0345h Function After Reset X000 0000b RW SEIE Periodic interrupt triggered every second enable bit 0 : Disable periodic interrupt triggered every second 1 : Enable periodic interrupt triggered every second 0 : Disable periodic interrupt triggered every minute 1 : Enable periodic interrupt triggered every minute 0 : Disable periodic interrupt triggered every hour 1 : Enable periodic interrupt triggered every hour 0 : Disable periodic interrupt triggered every day 1 : Enable periodic interrupt triggered every day 0 : Disable periodic interrupt triggered every week 1 : Enable periodic interrupt triggered every week b6 b5 RW MNIE Periodic interrupt triggered every minute enable bit RW HRIE Periodic interrupt triggered every hour enable bit RW DYIE Periodic interrupt triggered every day enable bit RW WKIE Periodic interrupt triggered every week enable bit RW RTCCMP0 Compare mode select bit RTCCMP1 — (b7) 0 0 1 1 0: 1: 0: 1: No compare mode Compare 1 mode Compare 2 mode Compare 3 mode RW RW No register bit. If necessary, set to 0. Read as undefined value — Write to the RTCCR2 register when both bits TSTART and TCSTF in the RTCCR1 register are 0 (timer stops). While bits RTCCMP1 to RTCCMP0 are 00b (no compare mode), an interrupt request can be generated every second, minute, hour, day, or week. To generate an interrupt request, set one of the following bits to 1 (interrupt enabled): SEIE, MNIE, HRIE, DAYIE, and WKIE (Be sure to set only one bit to 1). Table 20.4 lists Periodic Interrupt Sources. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 412 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock Table 20.4 Periodic Interrupt Sources Factor Periodic interrupt triggered every week Periodic interrupt triggered every day Periodic interrupt triggered every hour Interrupt Source Value in RTCWK register is set to 000b (1-week period) RTCWK register is updated (1-day period) RTCHR register is updated (1-hour period) Interrupt Enable Bit WKIE DYIE HRIE MNIE SEIE RTCMIN register is updated (1-minute period) Periodic interrupt triggered every minute Periodic interrupt RTCSEC register is updated (1-second period) triggered every second When bits RTCCMP1 to RTCCMP0 are 01b, 10b, or 11b (any compare mode), set as follows depending on what to compare. • When comparing to the RTCCSEC register, set the SEIE bit to 1 (interrupt enabled). • When comparing to the RTCCMIN register, set both bits SEIE and MNIE to 1. • When comparing to the RTCCHR register, set all the bits SEIE, MNIE, and HRIE to 1. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 413 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock 20.2.7 Real-Time Clock Count Source Select Register (RTCCSR) Real-Time Clock Count Source Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol RTCCSR Bit Symbol RCS0 Count source select bit RCS1 Bit Name Address 0346h Function b1 b0 0 After Reset XXX0 0000b RW RW 0 0 1 1 b4 0 : f1 1 : Do not set 0 : fC 1 : Do not set b3 b2 RW RCS2 RCS3 RCS4 — (b6-b5) — (b7) 0 0 0 Count source frequency select 0 bit 1 1 1 1 0 0 1 1 0 0 1 1 0 : f1 = fC or 4 MHz 1 : f1 = 6 MHz 0 : f1 = 8 MHz 1 : f1 = 16 MHz 0 : f1 = 20 MHz 1 : f1 = 24 MHz 0 : f1 = 32 MHz 1 : Do not set RW RW RW No register bits. If necessary, set to 0. Read as undefined value — Reserved bit Set to 0 RW When bits RCS1 to RCS0 are 10b (fC), set bits RCS4 to RCS2 to 000b. When bits RCS1 to RCS0 are 00b (f1), select a frequency matched to f1 by bits RCS4 to RCS2. Write to the RTCCSR register when both bits TSTART and TCSTF in the RTCCR1 register are 0 (timer stops). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 414 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock 20.2.8 Real-Time Clock Second Compare Data Register (RTCCSEC) Real-Time Clock Second Compare Data Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol RTCCSEC Bit Symbol SCMP00 Bit Name Address 0348h Function After Reset X000 0000b Setting Range RW RW SCMP01 1st digit of second compare data bit SCMP02 Store compare data 0 to 9 RW RW SCMP03 RW SCMP10 2nd digit of second compare data bit RW SCMP11 Store compare data 0 to 5 RW SCMP12 — (b7) RW No register bit. If necessary, set to 0. Read as undefined value — The RTCCSEC register is enabled when bits RTCCMP1 to RTCCMP0 in the RTCCR2 register are 01b, 10b, or 11b (any compare mode). SCMP03-SCMP00 (1st Digit of Second Compare Data Bit) (b3-b0) SCMP12-SCMP10 (2nd Digit of Second Compare Data Bit) (b6-b4) Set a value between 00 and 59 by the BCD codes. Write to these bits when the BSY bit in the RTCSEC register is 0 (not while data is updated). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 415 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock 20.2.9 Real-Time Clock Minute Compare Data Register (RTCCMIN) Real-Time Clock Minute Compare Data Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol RTCCMIN Bit Symbol MCMP00 Bit Name Address 0349h Function After Reset X000 0000b Setting Range RW RW MCMP01 1st digit of minute compare data bit MCMP02 Store compare data 0 to 9 RW RW MCMP03 RW MCMP10 2nd digit of minute compare data bit RW MCMP11 Store compare data 0 to 5 RW MCMP12 — (b7) RW No register bit. If necessary, set to 0. Read as undefined value — The RTCCMIN register is enabled when bits RTCCMP1 to RTCCMP0 in the RTCCR2 register are 01b, 10b, or 11b (any compare mode). MCMP03-MCMP00 (1st Digit of Minute Compare Data Bit) (b3-b0) MCMP12-MCMP10 (2nd Digit of Minute Compare Data Bit) (b6-b4) Set a value between 00 and 59 by the BCD codes. Write to these bits when the BSY bit in the RTCSEC register is 0 (not while data is updated). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 416 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock 20.2.10 Real-Time Clock Hour Compare Data Register (RTCCHR) Real-Time Clock Hour Compare Data Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol RTCCHR Bit Symbol HCMP00 Bit Name Address 034Ah Function After Reset X000 0000b Setting Range RW RW HCMP01 1st digit of hour compare data Store compare data bit HCMP02 0 to 9 RW RW HCMP03 RW HCMP10 2nd digit of hour compare data Store compare data bit HCMP11 0 : a.m. 1 : p.m. 0 to 2 RW RW PMCMP — (b7) A.m./p.m. compare bit RW No register bit. If necessary, set to 0. Read as undefined value — The RTCCHR register is enabled when bits RTCCMP1 to RTCCMP0 in the RTCCR2 register are 01b, 10b, or 11b (any compare mode). HCMP03-HCMP00 (1st Digit of Hour Compare Data Bit) (b3-b0) HCMP11-HCMP10 (2nd Digit of Hour Compare Data Bit) (b5-b4) When the H12H24 bit in the RTCCR1 register is 0 (12-hour mode), set a value between 00 and 11 by the BCD codes. When the H12H24 bit in the RTCCR1 register is 1 (24-hour mode), set a value between 00 and 23 by the BCD codes. Write to these bits when the BSY bit in the RTCSEC register is 0 (not while data is updated). PMCMP (A.M./P.M Compare Bit) (b6) This bit is enabled both when the H12H24 bit in the RTCCR1 register is 0 (12-hour mode) or 1 (24-hour mode). When the H12H24 bit is 1, set as follows. • When bits HCMP11 to HCMP10 and HCMP03 to HCMP00 are 00 to 11, set the PMCMP bit to 0. • When bits HCMP11 to HCMP10 and HCMP03 to HCMP00 are 12 to 23, set the PMCMP bit to 1. Write to these bits when the BSY bit in the RTCSEC register is 0 (not while data is updated). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 417 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock 20.3 20.3.1 Operations Basic Operation Real-time clock generates one-second signal from the count source selected in the RTCCSR register and counts seconds, minutes, hours, a.m./p.m., a day, and a week. Time and day to start counting are settable by registers RTCSEC, RTCMIN, RTCHR, RTCWK, and the RTCPM bit in the RTCCR1 register. Current time and day are read from registers RTCSEC, RTCMIN, RTCHR, RTCWK, and the RTCPM bit in the RTCCR1 register. However, do not read these registers when the BSY bit in the RTCSEC register is 1 (while data is updated). An interrupt request can be generated every second, minute, hour, day, or week. While bits RTCCMP1 to RTCCMP0 are 00b (no compare mode), use the RTCCR2 register to enable one of the periodic interrupts triggered every second, minute, hour, day and week. When a periodic interrupt is generated, the IR bit in the RTCTIC register becomes 1 (interrupt request). Figure 20.3 shows Real-Time Clock Basic Operating Example, Figure 20.4 shows Time and Day Change Procedure (No Compare Mode or Compare 1 Mode), and Figure 20.5 shows Time and Day Change Procedure (Compare 2 Mode or Compare 3 Mode). 1s Approx. 62.5ms BSY bit Approx. 62.5ms Bits SC12 to SC00 in RTCSEC register 58 Undefined 59 Undefined 00 Bits MN12 to MN00 in RTCMIN register 03 Undefined 04 Bits HR11 to HR00 in RTCHR register (Not changed) RTCPM Bit in RTCCR1 register (Not changed) Bits WK2 to WK0 in RTCWK register (Not changed) This bit becomes low when an interrupt request is accepted, or by setting the bit to 0. IR bit in RTCTIC register (when SEIE bit in RTCCR2 register is 1 (enable periodic interrupt triggered every second)) IR bit in RTCTIC register (when MNIE bit in RTCCR2 register is 1 (enable periodic interrupt triggered every minute)) BSY : Bit in RTCSEC register Figure 20.3 Real-Time Clock Basic Operating Example REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 418 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock Time and day change TSTART bit in RTCCR1 register = 0 Stop real-time clock operation (not necessary while count is stop) TCSTF bit in RTCCR1 register = 0? 0 RTCTIC register ← 00h RTCCIC register ← 00h Setting of RTCCSR register Setting of H12H24 bit in RTCCR1 register Setting of registers RTCSEC, RTCMIN, RTCHR,and RTCWK Setting of RTCPM bit in RTCCR1 register Setting of RTCCR2 register Setting of registeres RTCTIC and RTCCIC 1 Disable real-time clock periodic interrupt Disable real-time clock compare interrupt Select clock source Set a.m./p.m. operating mode Set second, minute, hour, day Set a.m./p.m. Select interrupt source (IR bit ← 0, select interrupt priority level) TSTART bit in RTCCR1 register = 1 Start real-time clock operation TCSTF bit in RTCCR1 register = 1? 1 End 0 Figure 20.4 Time and Day Change Procedure (No Compare Mode or Compare 1 Mode) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 419 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock Time and day change TSTART bit in RTCCR1 register = 0 Stop real-time clock operation (not necessary while count is stopped or in compare 3 mode) 1 TCSTF bit in RTCCR1 register = 0? 0 RTCTIC register ← 00h RTCCIC register ← 00h Setting of RTCCSR register Setting of H12H24 bit in RTCCR1 register Disable real-time clock periodic interrupt Disable real-time clock compare interrupt Select clock source Set a.m./p.m. operating mode Setting of registers RTCSEC, RTCMIN, RTCHR,and RTCWK Setting of RTCPM bit in RTCCR1 register Set second, minute, hour, day, a.m./p.m. (1) NG Confirmation of RTCPM bit in RTCCR1 register and registers RTCSEC, RTCMIN, RTCHR, and RTCWK OK Setting of RTCCR2 register Setting of registeres RTCTIC and RTCCIC Select interrupt source (IR bit ← 0, select interrupt priority level) TSTART bit in RTCCR1 register = 1 Start real-time clock operation TCSTF bit in RTCCR1 register = 1? 1 End 0 Note: 1. One cycle of the count source is sometimes necessary to write a correct value after compare match. Figure 20.5 Time and Day Change Procedure (Compare 2 Mode or Compare 3 Mode) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 420 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock 20.3.2 Compare Mode In compare mode, time data (1) and compare data (1) are compared, and compare value match is detected. When match is detected, the following occur. • Compare interrupt request Refer to 20.4 “Interrupts” for details. • RTCOUT pin output level inversion While the TOENA bit in the RTCCR1 register is 1 (compare output enabled), when compare value match is detected, RTCOUT pin output level is converted. Notes: 1. Bits for time data are as follows: Bits SC12 to SC10 and SC03 to SC00 in the RTCSEC register Bits MN12 to MN10 and MN03 to MN00 in the RTCMIN register Bits HR11 to HR10 and HR03 to HR00 in the RTCHR register The RTCPM bit in the RTCCR1 register Bits for compare data are as follows: Bits SCMP12 to SCMP10 and SCMP03 to SCMP00 in the RTCCSEC register Bits MCMP12 to MCMP10 and MCMP03 to MCMP00 in the RTCCMIN register Bits HCMP11 to HCMP10 and HCMP03 to HCMP00 in the RTCCHR register The PMCMP bit in the RTCCHR register In compare mode, set the SEIE, MNIE, or HRIE bit in the RTCCR2 register to 1 (interrupt enabled) according to compare data (second, minute, or hour). Refer to 20.2.6 “Real-Time Clock Control Register 2 (RTCCR2)” for details. Compare mode has three modes: compare 1 mode, compare 2 mode, and compare 3 mode. Operation after compare value match differs depending on a compare mode. • Compare 1 mode The time data is used continuously and counting continues. • Compare 2 mode The value after reset is used as the time data and counting continues. • Compare 3 mode The value after reset is used as the time data and counting stops. Figure 20.6 shows Difference between Compare Modes, Figure 20.7 shows Count Start/Stop Operating Example, Figure 20.8 shows Compare 1 Mode Operating Example, Figure 20.9 shows Compare 2 Mode Operating Example, and Figure 20.10 shows Compare 3 Mode Operating Example. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 421 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock RTCPM Time Data RTCHR RTCMIN RTCSEC Control by bits SEIE, MNIE, and HRIE in RTCCR2 register Compare Compare Data (when 0:01:23:45) PMCMP 0 Compare 01 Compare RTCCMIN 23 Compare RTCCSEC 45 RTCCHR Values of RTCPM, RTCHR, RTCMIN, RTCSEC and count operation Compare 1 Mode : 0 : 01 : 23 : 43 0 : 01 : 23 : 44 0 : 01 : 23 : 45 0 : 01 : 23 : 46 0 : 01 : 23 : 47 : Continue counting Compare 2 Mode : 0 : 01 : 23 : 43 0 : 01 : 23 : 44 0 : 00 : 00 : 00 0 : 00 : 00 : 01 0 : 00 : 00 : 02 : The value is set back to the value after reset and counting continues. Compare 3 Mode : 0 : 01 : 23 : 43 Time 0 : 01 : 23 : 44 (change 0 : 00 : 00 : 00 every second) 0 : 00 : 00 : 00 0 : 00 : 00 : 00 : The value is set back to the value after reset and counting stops. Compare value match request 0 : 01 : 23 : 43 Values of RTCPM, RTCHR, RTCMIN, RTCSEC The above diagram shows an instance in which the following conditions are met: The H12H24 bit in the RTCCR1 register is 0 (12-hour mode). Bits SEIE, MNIE, and HRIE in the RTCCR2 register are 1. RTCPM : RTCPM bit in RTCCR1 register RTCHR : Bits HR11 to HR10 and HR03 to HR00 in RTCHR register RTCMIN : Bits MN12 to MN10 and MN03 to MN00 in RTCMIN register RTCSEC : Bits SC12 to SC10 and SC03 to SC00 in RTCSEC register PMCMP : PMCMP bit in RTCCHR register RTCCHR : Bits HCMP11 to HCMP10 and HCMP03 to HCMP00 in RTCCHR register RTCCMIN : Bits MCMP12 to MCMP10 and MCMP03 to MCMP00 in RTCCMIN register RTCCSEC : Bits SCMP12 to SCMP10 and SCMP03 to SCMP00 in RTCCSEC register Figure 20.6 Difference between Compare Modes REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 422 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock 1s BSY bit Set to 1 by a program TSTART bit in RTCCR1 register TCSTF bit in RTCCR1 register RTCSEC RTCMIN RTCHR RTCPM bit RTCOUT pin output Low is output when the RTCOUT pin is used first, e.g., after reset. When count stops after selecting the RTCOUT pin, the state before stop is retained. 44 Undefined 1s Set to 0 by a program Start counting Stop counting 45 Undefined 46 23 1 0 Low is output after counting starts. The state before stop is retained. The diagram above applies under the following conditions: The TOENA bit in the RTCCR1 register is 1 (compare output enabled). Bits RTCCMP1 to RTCCMP0 in the RTCCR2 register is 01b (compare 1 mode) BSY bit RTCSEC RTCMIN RTCHR RTCPM bit : Bit in RTCSEC register : Bits SC12 to SC10 and SC03 to SC00 in RTCSEC register : Bits MN12 to MN10 and MN03 to MN00 in RTCMIN register : Bits HR11 to HR10 and HR03 to HR00 in RTCHR register : Bit in RTCCR1 register Figure 20.7 Count Start/Stop Operating Example REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 423 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock 1s BSY bit TCSTF bit in RTCCR1 register RTCSEC RTCMIN RTCHR RTCPM bit IR bit in RTCCIC register IR bit in RTCTIC register RTCOUT pin output The bit becomes low when an interrupt request is accepted, or by setting the bit to 0. 1 Compare value match Continue counting 46 Continue using the count value Undefined 44 Undefined 45 23 1 0 Output polarity inversion The diagram above applies under the following conditions: The TOENA bit in the RTCCR1 register is 1 (compare output enabled). Bits RTCCMP1 to RTCCMP0 in the RTCCR2 register are 01b (compare 1 mode). Bits SEIE, MNIE, and HRIE in the RTCCR2 are 1 (compare by seconds, minutes, and hours. Interrupt enabled). Bits SCMP12 to SCMP10 and SCMP03 to SCMP00 in the RTCCSEC register are 4 and 5 respectively (second setting: 45). Bits MCMP12 to MCMP10 and MCMP03 to MCMP00 in the RTCCMIN register are 2 and 3 respectively (minute setting: 23). Bits HCMP11 to HCMP10 and HCMP03 to HCMP00 in the RTCCHR register are 0 and 1 respectively (hour setting: 1). The PMCMP bit in the RTCCHR register is 0 (a.m.). BSY bit RTCSEC RTCMIN RTCHR RTCPM bit : Bit in RTCSEC register : Bits SC12 to SC10 and SC03 to SC00 in RTCSEC register : Bits MN12 to MN10 and MN03 to MN00 in RTCMIN register : Bits HR11 to HR10 and HR03 to HR00 in RTCHR register : Bit in RTCCR1 register Figure 20.8 Compare 1 Mode Operating Example REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 424 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock 1s BSY bit TCSTF bit in RTCCR1 register RTCSEC RTCMIN RTCHR RTCPM bit IR bit in RTCCIC register IR bit in RTCTIC register RTCOUT pin output The bit becomes low when an interrupt request is accepted, or by setting the bit to 0. 1 Compare value match Continue counting 1 Set back to the value after reset Undefined 44 Undefined 0 0 Undefined 23 1 Undefined 0 0 Undefined 0 Output polarity inversion The diagram above applies under the following conditions: The TOENA bit in the RTCCR1 register is 1 (compare output enabled). Bits RTCCMP1 to RTCCMP0 in the RTCCR2 register are 10b (compare 2 mode). Bits SEIE, MNIE, and HRIE in the RTCCR2 register are 1 (compare by seconds, minutes, and hours. Interrupt enabled). Bits SCMP12 to SCMP10 and SCMP03 to SCMP00 in the RTCCSEC register are 4 and 5 respectively (second setting: 45). Bits MCMP12 to MCMP10 and MCMP03 to MCMP00 in the RTCCMIN register are 2 and 3 respectively (minute setting: 23). Bits HCMP11 to HCMP10 and HCMP03 to HCMP00 in the RTCCHR register are 0 and 1 respectively (hour setting: 1). The PMCMP bit in the RTCCHR register is 0 (a.m.). BSY bit RTCSEC RTCMIN RTCHR RTCPM bit : Bit in RTCSEC register : Bits SC12 to SC10 and SC03 to SC00 in RTCSEC register : Bits MN12 to MN10 and MN03 to MN00 in RTCMIN register : Bits HR11 to HR10 and HR03 to HR00 in RTCHR register : Bit in RTCCR1 register Figure 20.9 Compare 2 Mode Operating Example REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 425 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock BSY bit TCSTF bit in RTCCR1 register Stop counting Compare value match RTCSEC RTCMIN RTCHR RTCPM bit IR bit in RTCCIC register IR bit in RTCTIC register RTCOUT pin output The bit becomes low when an interrupt request is accepted, or by setting the bit to 0. 44 Undefined 0 Set back to the value after reset 0 Undefined 23 1 Undefined 0 0 Undefined 0 Output polarity inversion The diagram above applies under the following conditions: The TOENA bit in the RTCCR1 register is 1 (compare output enabled). Bits RTCCMP1 to RTCCMP0 in the RTCCR2 register are 11b (compare 3 mode). Bits SEIE, MNIE, and HRIE in the RTCCR2 register are 1 (compare by seconds, minutes, and hours. Interrupt enabled). Bits SCMP12 to SCMP10 and SCMP03 to SCMP00 in the RTCCSEC register are 4 and 5 respectively (second setting: 45). Bits MCMP12 to MCMP10 and MCMP03 to MCMP00 in the RTCCMIN register are 2 and 3 respectively (minute setting: 23). Bits HCMP11 to HCMP10 and HCMP03 to HCMP00 in the RTCCHR register are 0 and 1 respectively (hour setting: 1). The PMCMP bit in the RTCCHR register is 0 (a.m.). BSY bit RTCSEC RTCMIN RTCHR RTCPM bit : Bit in RTCSEC register : Bits SC12 to SC10 and SC03 to SC00 in RTCSEC register : Bits MN12 to MN10 and MN03 to MN00 in RTCMIN register : Bits HR11 to HR10 and HR03 to HR00 in RTCHR register : Bit in RTCCR1 register Figure 20.10 Compare 3 Mode Operating Example REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 426 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock 20.4 Interrupts Real-time clock generates the following two types of interrupts. • Periodic interrupts triggered every second, minute, hour, day, and week • Compare value match interrupt Refer to Table 20.4 Periodic Interrupt Sources for details of periodic interrupt sources, each mode’s specification and operating example for the interrupt request generating timing, and 14.7 “Interrupt Control” for details of interrupt control. Table 20.5 lists Real-Time Clock Interrupt-Associated Registers. Table 20.5 Real-Time Clock Interrupt-Associated Registers Address 006Eh 006Fh 0205h Register Name Real-Time Clock Period Interrupt Control Register Real-Time Clock Compare Match Interrupt Control Register Interrupt Source Select Register 3 Register Symbol After Reset RTCTIC XXXX X000b RTCCIC XXXX X000b IFSR3A 00h Real-time clock shares the interrupt vectors and interrupt control registers with other peripheral functions. To use period interrupts, set the IFSR35 bit in the IFSR3A register to 1 (real-time clock cycle), and to use compare interrupts, set the IFSR36 bit in the IFSR3A register to 1 (real-time clock compare). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 427 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock 20.5 20.5.1 Notes on Real-Time Clock Starting and Stopping Count Real-time clock has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates count start or stop. Bits TSTART and TCSTF are in the RTCCR1 register. Real-time clock starts counting and the TCSTF bit becomes 1 (count starts) when the TSTART bit is set to 1 (count starts). It takes up to two cycles of the count source until the TCSTF bit becomes 1 after setting the TSTART bit to 1. During this time, do not access registers associated with real-time clock (1) other than the TCSTF bit. Also, real-time clock stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit becomes 0 (count stops). It takes up to three cycles of the count source until the TCSTF bit becomes 0 after setting the TSTART bit to 0. During this time, do not access registers associated with real-time clock other than the TCSTF bit. Note: 1. Registers associated with real-time clock: RTCSEC, RTCMIN, RTCHR, RTCWK, RTCCR1, RTCCR2, RTCCSR, RTCCSEC, RTCCMIN, and RTCCHR. 20.5.2 Register Setting (Time Data etc.) Write to the following registers or bits while real-time clock is stopped. • Registers RTCSEC, RTCMIN, RTCHR, RTCWK, and RTCCR2 • Bits H12H24 and RTCPM in the RTCCR1 register • Bits RCS0 to RCS4 in the RTCCSR register Real-time clock is stopped when bits TSTART and TCSTF in the RTCCR1 register are 0 (real-time clock stopped). Also, set all above-mentioned registers and bits (immediately before real-time clock count starts) before setting the RTCCR2 register. Figure 20.4 shows Time and Day Change Procedure (No Compare Mode or Compare 1 Mode), and Figure 20.5 shows Time and Day Change Procedure (Compare 2 Mode or Compare 3 Mode). 20.5.3 Register Setting (Compare Data) Write to the following registers when the BSY bit in the RTCSEC register is 0 (not while data is updated). • Registers RTCCSEC, RTCCMIN, and RTCCHR REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 428 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 20. Real-Time Clock 20.5.4 Time Reading Procedure of Real-Time Clock Mode In real-time clock mode, read time data bits (1) when the BSY bit in the RTCSEC register is 0 (not while data is updated). When reading multiple registers, if data is rewritten between reading registers, an errant time will be read. In order to prevent this, use the reading procedure shown below. • Using an interrupt Read necessary contents of time data bits in the real-time clock interrupt routine. • Monitoring by a program 1 Monitor the IR bit in the RTCTIC register by a program and read necessary contents of time data bits after the IR bit in the RTCTIC register becomes 1 (periodic interrupt request generated). • Monitoring by a program 2 (1)Monitor the BSY bit. (2)Monitor until the BSY bit becomes 0 after the BSY bit becomes 1 (the BSY bit is set to 1 for approximately 62.5 ms). (3)Read necessary contents of time data bits after the BSY bit becomes 0. • Using read results if they are the same value twice (1)Read necessary contents of time data bits. (2)Read the same bit as (1) and compare the contents. (3)Recognize as the correct value if the contents match. If the contents do not match, repeat until the read contents match with the previous contents. Also, when reading several registers, read them as continuously as possible. Note: 1. Time data bits are shown below. Bits SC12 to SC10 and SC03 to SC00 in the RTCSEC register Bits MN12 to MN10 and MN03 to MN00 in the RTCMIN register Bits HR11 to HR10 and HR03 to HR00 in the RTCHR register Bits WK2 to WK0 in the RTCWK The RTCPM bit in the RTCCR1 register REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 429 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 21. Pulse Width Modulator 21. Pulse Width Modulator Note The 80-pin package does not have pins P4_6 and P4_7. Use pins P9_3 and P9_4 for PWM0 and PWM1 output. 21.1 Introduction The pulse width modulator (PWM) consists of two independent PWM circuits. Table 21.1 lists PWM Specification, Figure 21.1 shows Block Diagram of PWM, and Table 21.2 lists I/O Port. Table 21.1 PWM Specification Item Resolution Count source PWM Cycle Specification 8 bits f1 divided by 2, 4, 8, or 16 (Unit : s) fj m: PWMPREi register setting value fj: Count source frequency (Unit : Hz) High-level pulse width (Unit : s) fj m: PWMPREi register setting value n: PWMREGi register setting value fj: Count source frequency (Unit : Hz) Select output pin: P4 or P9 (28 - 1) × (m + 1) (m + 1) × n Selectable function i = 0, 1 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 430 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 21. Pulse Width Modulator Data bus PWM0 prescaler pre-latch PWM0 register pre-latch PWMEN0 Transfer control circuit PWMCLK1 and PWMCLK0 f1 1/2 1/4 1/8 1/16 =00b =01b =10b =11b PWM0 presclaer latch PWM0 register latch PWM0 prescaler PWM0 register PWMPORT0 PD4_6 PWMSEL0 PWM0 PWM0 PD9_3 The above shows an example block diagram of PWM0. PWMSEL0, PWMCLK1, PWMCLK0 : Bits in the PWMCOM0 register PWMEN0, PWMPORT0 : Bits in the PWMCOM1 register PD4_6 : Bit in the PD4 register PD9_3 : Bit in the PD9 register Figure 21.1 Block Diagram of PWM Table 21.2 I/O Port Port I/O Function PWM0 O (1) PWM output PWM1 Note: 1. Set the direction bit corresponding to selected pin to 1 (output mode) 21.2 Registers Register Structure Table 21.3 Address 0370h 0372h 0373h 0374h 0375h 0376h Register Name PWM Control Register 0 PWM0 Prescaler PWM0 Register PWM1 Prescaler PWM1 Register PWM Control Register 1 Symbol PWMCON0 PWMPRE0 PWMREG0 PWMPRE1 PWMREG1 PWMCON1 After Reset 00h 00h 00h 00h 00h 00h REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 431 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 21. Pulse Width Modulator 21.2.1 PWM Control Register 0 (PWMCON0) PWM Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 0000 Symbol PWMCON0 Bit Symbol Bit Name Address 0370h Function 0: output PWM0 signal from P9_3 1: output PWM0 signal from P4_6 0: output PWM1 signal from P9_4 1: output PWM1 signal from P4_7 Set to 0 b7 b6 After Reset 00h RW RW PWMSEL0 PWM0 output pin select bit PWMSEL1 PWM1 output pin select bit — (b5-b2) PWMCLK0 RW Reserved bits RW 0 PWM count source select bit 0 1 PWMCLK1 1 0: fi divided by 2 1: fi divided by 4 0: fi divided by 8 1: fi divided by 16 RW RW Set bits PWMSELi and PWMCLKi (i = 0, 1) in the PWMCON0 register when the PWMENi bit in the PWMCON1 register is 0 (PWMi output disabled). PWMSEL0 (PWM0 Output Select Bit) (b0) This bit select a PWM output pin. See Table 21.4 “PWM Pin and Bit Setting”. PWMSEL1 (PWM1 Output Select Bit) (b1) This bit select a PWM output pin. See Table 21.4 “PWM Pin and Bit Setting”. PWMCLK1-PWMCLK0 (PWM Count Source Select Bit) (b7-b6) Bits PWMCLK1 and PWMCLK0 select a count source for PWMi prescaler. Prescalers PWM0 and PWM1 share the same count source. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 432 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 21. Pulse Width Modulator 21.2.2 PWMi Prescaler (PWMPREi) (i = 0, 1) PWMi Prescaler (i = 0, 1) b7 b0 Symbol PWMPRE0 PWMPRE1 Function PWM cycle Address 0372h 0374h Setting Range 00h to FFh After Reset 00h 00h RW RW REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 433 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 21. Pulse Width Modulator 21.2.3 PWMi Register (PWMREGi) (i = 0, 1) PWMi Register (i = 0, 1) b7 b0 Symbol PWMREG0 PWMREG1 Function Output high-level pulse width Address 0373h 0375h Setting Range 00h to FFh After Reset 00h 00h RW RW The PWMi register (i = 0, 1) sets the PWMi cycle (i = 0, 1) and high-level pulse width. The PWM cycle and high-level pulse width are given by: PWM cycle = (28 - 1) × (m + 1) (Unit : s) fj (m + 1) × n (Unit : s) fj High level pulse width = fj: PWM count source frequency (Unit : Hz) m: PWMPREi register setting n: PWMREGi register setting The written value in the PWMPREi register is written into the PWMi prescaler prelatch. The state in the PWMi prescaler prelatch cannot be read. At the beginning of the next PWM cycle, the PWMi prescalser prelatch value is transferred to the PWMi prescaler latch and the PWMi prescaler, and then the associated PWMi waveform is output. When reading the PWMPREi register, the state in the PWMi prescaler latch can be read. (See Figure 21.1 “Block Diagram of PWM”) The written value in the PWMREGi register is written into the PWMi register prelatch. The state in the PWMi register prelatch cannot be read. At the beginning of the next PWM cycle, the PWMi register prelatch value is transferred to the PWMi register latch and the PWMi register, and then the associated PWMi waveform is output. When reading the PWMREGi register, the state in the PWMi register latch can be read. Therefore, the written value in registers PWMPREi and PWMREGi may differ from the values read from registers PWMPREi and PWMREGi. Even if the PWMENi bit is set to 1 (PWMi output enabled) when the PWMPREi and PWMREGi register values are rewritten while the PWMENi bit in the PWMCON1 register is set to 0 (PWMi output disabled), the rewritten values are not reflected immediately. The values prior to the change are reflected for the first one cycle of PWM output. The values read from registers PWMPREi and PWMREGi during this cycle are the values prior to the change. When the second PWM cycle begins, the rewritten values should be read from registers PWMPREi and PWMREGi and the associated PWM waveform is output. See 21.3.2 “Operation Example” for output waveforms and transfer timings. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 434 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 21. Pulse Width Modulator 21.2.4 PWM Control Register 1 (PWMCON1) PWM Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 0000 Symbol PWMCON1 Bit Symbol Bit Name Address 0376h Function 0: output disabled 1: output enabled 0: output disabled 1: output enabled 0: I/O port 1: PWM0 output 0: I/O port 1: PWM1 output Set to 0 After Reset 00h RW RW PWMEN0 PWM0 output enable bit PWMEN1 PWM1 output enable bit RW PWMPORT0 PWM0 port switch bit RW PWMPORT1 PWM1 port switch bit RW — (b7-b4) Reserved bits RW PWMEN0 (PWM0 Output Enable Bit) (b0) The PWMEN0 bit is used to start PWM output. See Table 21.4 “PWM Pin and Bit Setting” for details. PWMEN1 (PWM1 Output Enable Bit) (b1) The PWMEN1 bit is used to start PWM output. See Table 21.4 “PWM Pin and Bit Setting” for details. PWMPORT0 (PWM0 Port Switch Bit) (b2) A PWM output pin can be selected. See Table 21.4 “PWM Pin and Bit Setting”. PWMPORT1 (PWM1 Port Switch Bit) (b3) A PWM output pin can be selected. See Table 21.4 “PWM Pin and Bit Setting”. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 435 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 21. Pulse Width Modulator Table 21.4 PWM Pin and Bit Setting Bit Setting Pin Function or State PWMCON0 register PWMCON1 register i=0 i=1 PWMSELi bit PWMPORTi PWMENi bit P9_3 P9_4 P4_6 P4_7 bit 0 0 0 or 1 I/O port or pin for other I/O port or pin for other peripheral function peripheral function (1) 0 PWM0 output level 1 maintained (2) 1 PWM0 pulse output 1 0 0 or 1 I/O port or pin for other I/O port or pin for other peripheral function peripheral function 0 PWM1 output level 1 (1) maintained (2) 1 PWM1 pulse output i = 0, 1 Notes: 1. Set the direction bit corresponding to selected pin to 1 (output mode). 2. Even if the PWMENi bit is set from 1 to 0 during PWMi output, maintain the PWMi output remains unchanged. The PWM output signal is in the low-level state immediately after the MCU is reset. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 436 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 21. Pulse Width Modulator 21.3 21.3.1 Operations Setting Procedure Follow the procedures below to set the individual register in order to start PWMi (i = 0, 1) output. (all SFRs are assumed to be reset. Refer the register descriptions to access registers or bits.) (1) Write output data of the port corresponding to the pin for PWMi output to the P9 or P4 register. Then, set the direction bit for the corresponding port to 1 (output mode). (2) Set the PWMSELi bit in the PWMCON0 register to select a pin for PWMi output. Set the PWMCLKi bit to select the count source. (3) Set registers PWMPREi and PWMREGi to set the PWM cycle and high-level pulse width. (4) Set the PWMPORTi bit in the PWMCON1 register to 1 (PWMi function) and the PWMENi bit to 1 (PWM output enabled). 21.3.2 Operation Example The values written to the PWMPREi and PWMREGi register during PWMi (i = 0, 1) output is not reflected until the next cycle of PWMi output begins. The PWM output signal is in the low state immediately after the MCU is reset. Then the associated waveform output starts. The PWMi output level remains unchanged even if the PWMENi bit is changed from 1 (PWMi output enabled) to 0 (PWMi output disabled) during PWMi output. Registers PWMPREi and PWMREGi maintains the value before the PWMi output is disabled. When the PWMENi bit is set to 1 after registers PWMPREi and PWMREGi are rewritten during PWMi output disabled, the PWMPREi and PWMREGi register values prior to the change are reflected for the first cycle of PWM output. The rewritten register values are reflected in the following PWMi cycle. Figure 21.2 to Figure 21.4 shows PWMi output examples. Set to 1 (PWM output enabled) by a program PWMENi bit in the PWMCON1 register PWMi prescaler pre-latch reset value PWMi register pre-latch 00h 00h m1 m2 Set registers PWMPREi and PWMREGi by a program n1 n2 PWMi prescaler latch 00h reset value m1 m2 PWMi register latch 00h n1 Rewritten value after reset but before PWMi output enabled is reflected in the 2nd cycle of PWMi output (m1+1) × n1 fj n2 Value rewritten during PWM output is reflected in the next cycle (m2+1) × n2 fj Low-level output PWMi output (28-1) × (0+1) fj (28-1) × (m1+1) fj (28-1) × (m2+1) fj This length of low-level signal is output for first cycle after reset. i: 0, 1 fj: PWM count source frequency The above applies when the PWMPORTi bit in the PWMCON1 register is set to 1 (PWMi output). Figure 21.2 PWMi Output Example (after reset and during PWM output) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 437 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 21. Pulse Width Modulator PWMENi bit in the PWMCON1 register PWMi prescaler pre-latch 1 m Set the PWMREGi register by a program PWMi register pre-latch n 00h n FFh n PWMi prescaler latch m PWMi register latch n (m+1) × n fj 00h n FFh n Low level is output in this cycle when PWMi register latch is 00h High level is output in this cycle when PWMi register latch is FFh PWMi output (28-1) × (m+1) fj PWMPREi register remains unchaged and so does PWM cycle i: 0, 1 fj: PWM count source frequency The above applies when the PWMPORTi bit in the PWMCON1 register is set to 1 (PWMi output). Figure 21.3 PWMi Output Example (Duty 0%, Duty 100%) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 438 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 21. Pulse Width Modulator change by a program PWMENi bit in the PWMCON1 register PWMi output disabled PWMi prescaler pre-latch m1 m2 Set registers PWMPREi and PWMREGi by a program. PWMi register pre-latch n1 n2 PWMi prescaler latch m1 m2 PWMi register latch n1 n2 Rewritten value is reflected in 2nd cycle of PWM output (m1+1) × n1 fj PWMi output e.g.1 (28-1) × (m1+1) fj Maintain output level of when PWMi output is disabled (m1+1) × n1 fj e.g.2 (28-1) × (m1+1) fj (m1+1) × n1 fj (m2+1) × n2 fj (28-1) × (m1+1) fj (28-1) × (m2+1) fj PWMi outputs with value before the PWMi output is disabled for first cycle after PWMi output is enabled i: 0, 1 fj: PWM count source frequency The above applies when the PWMPORTi bit in the PWMCON1 register is set to 1 (PWMi output). Figure 21.4 PWMi Output Example (PWM Output Disabled and PWM Output Resumed) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 439 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22. Remote Control Signal Receiver Note The 80-pin package does not have the PMC1 pin. Use the PMC0 pin for external pulse input. 22.1 Introduction Remote control signal receiver has two circuits for checking width and period of external pulse. Table 22.1 lists Remote Control Receiver Specifications, Figure 22.1 to Figure 22.3 show remote control signal receiver block diagram, and Table 22.2 lists Input/Output Pin. Table 22.1 Remote Control Receiver Specifications Content PMC0 circuit PMC1 circuit One of the following Count sources Clock sources One of the following • fC • fC • f1 • f1 • Timer B2 underflow • Timer B1 underflow • Count source of PMC1 • Timer B2 underflow Division No division, divided-by-8, divided-by-32, or divided-by-64 Count operation Increment Operation modes • Pattern match mode Determines that external pulse matches specified pattern • Input capture mode Measures width and period of external pulse Pattern match Detect patterns • Header mode • Data 0 • Data 1 • Special data Receive buffer 6 bytes (48 bits) None Interrupt request • Receive error • Receive error generation timing • Completion of data reception • Completion of data reception • Header match • Header match • Data 0/1 match • Data 0/1 match • Special data match • Receive buffer full • Compare match Selectable functions • Input signal inversion • Digital filter Input capture Measurement items • Pulse period (between rising edge and rising edge) mode • Pulse period (between falling edge and falling edge) • Pulse width Interrupt request • Timer measurement generation timing • Counter overflow Selectable functions • Input signal inversion • Digital filter • Individual count of two inputs or simultaneous count of two inputs Item REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 440 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver PMCiBC INFLG PMCi internal input signal Edge detection PMCi count source Counter CEFLG Only PCM0 PMCiTIM PMC0RBIT Comparator PMC0DAT0 PMC0DAT1 PMC0DAT5 BFULFLG PMCiHDPMIN PMCiHDPMAX PMCiD0PMIN PMCiD0PMAX REFLG DRFLG PTHDFLG PTD0FLG PTD1FLG SDFLG Comparator CPFLG CPEN CPN2 to CPN0 PMCiD1PMIN PMCiD1PMAX PMC0CPD i = 0, 1 INFLG, CEFLG: Bits in registers PMC1CON2 and PMC0CON2 REFLG, DRFLG, PTHDFLG, PTD0FLG, PTD1FLG: Bits in registers PMC0STS and PMC1STS SDFLG, CPFLG, BFULFLG: Bits in the PMC0STS register CPEN, CPN2 to CPN0: Bits in the PM0CPC register Figure 22.1 Remote Control Signal Receiver Block Diagram (1/3) SINV PMC0 pin 0 0 1 1 00b FIL Bits PSEL1 to PSEL0 in PMC0CON2 register 01b Digital filter PMC0 internal input signal Bits PSEL1 to PSEL0 in PMC1CON2 register 01b 0 SINV FIL 0 1 1 PMC1 pin 10b PMC1 internal input signal Digital filter i = 0, 1 FIL, SINV: Bits in the PMCiCON0 register Figure 22.2 Remote Control Signal Receiver Block Diagram (2/3) (PMCi Input) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 441 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver Clock source f1 Timer B1 underflow fC Timer B2 underflow PMC1CON3 register CSR1 to CSR0 00b 01b 10b 11b Dividedby-8 Dividedby-4 CDIV1 to CDIV0 00b 01b 10b Dividedby-2 11b PMC1 count source Sampling clock of PMC1 digital filter ONC0CON3 register CSR1 to CSR0 00b 01b 10b 11b Dividedby-8 Dividedby-4 CDIV1 to CDIV0 00b 01b 10b Dividedby-2 11b PMC0 count source Sampling clock of PMC0 digital filter i = 0, 1 CDIV1, CDIV0: Bits in the PMCiCON3 register Figure 22.3 Remote Control Signal Receiver Block Diagram (3/3) (PMCi Count Source) Table 22.2 Input/Output Pin Pin Name Input/Output Function (1) External pulse input PMC0 Input PMC1 Note: 1. Set the port direction bits sharing pins to 0 (input mode). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 442 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.2 Registers Register Structure (PMC0 Circuit) Table 22.3 Address 01F0h 01F1h 01F2h 01F3h 01F4h 01F5h 01F6h 01F7h D080h D081h D082h D083h D084h D085h D086h D087h D088h D089h D08Ah D08Bh D08Ch D08Dh D08Eh D08Fh D090h D091h D092h Register Name PMC0 Function Select Register 0 PMC0 Function Select Register 1 PMC0 Function Select Register 2 PMC0 Function Select Register 3 PMC0 Status Register PMC0 Interrupt Source Select Register PMC0 Compare Control Register PMC0 Compare Data Register PMC0 Header Pattern Set Register (Min) PMC0 Header Pattern Set Register (Max) PMC0 Data0 Pattern Set Register (Min) PMC0 Data0 Pattern Set Register (Max) PMC0 Data1 Pattern Set Register (Min) PMC0 Data1 Pattern Set Register (Max) PMC0 Measurements Register PMC0 Counter Value Register PMC0 Receive Data Store Register 0 PMC0 Receive Data Store Register 1 PMC0 Receive Data Store Register 2 PMC0 Receive Data Store Register 3 PMC0 Receive Data Store Register 4 PMC0 Receive Data Store Register 5 PMC0 Receive Bit Count Register Register Symbol PMC0CON0 PMC0CON1 PMC0CON2 PMC0CON3 PMC0STS PMC0INT PMC0CPC PMC0CPD PMC0HDPMIN PMC0HDPMAX PMC0D0PMIN PMC0D0PMAX PMC0D1PMIN PMC0D1PMAX PMC0TIM PMC0BC PMC0DAT0 PMC0DAT1 PMC0DAT2 PMC0DAT3 PMC0DAT4 PMC0DAT5 PMC0RBIT After Reset 00h 00XX 0000b 00h 00h 00h 00h XXX0 X000b 00h 00h XXXX X000b 00h XXXX X000b 00h 00h 00h 00h 0000h 0000h 00h 00h 00h 00h 00h 00h XX00 0000b REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 443 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver Table 22.4 Register Structure (PMC1 Circuit) Address 01F8h 01F9h 01FAh 01FBh 01FCh 01FDh D094h D095h D096h D097h D098h D099h D09Ah D09Bh D09Ch D09Dh D09Eh D09Fh Register Name PMC1 Function Select Register 0 PMC1 Function Select Register 1 PMC1 Function Select Register 2 PMC1 Function Select Register 3 PMC1 Status Register PMC1 Interrupt Source Select Register PMC1 Hedder Pattern Set Register (Min) PMC1 Header Pattern Set Register (Max) PMC1 Data0 Pattern Set Register (Min) PMC1 Data0 Pattern Set Register (Max) PMC1 Data1 Pattern Set Register (Min) PMC1 Data1 Pattern Set Register (Max) PMC1 Measurements Register PMC1 Counter Value Register Register Symbol PMC1CON0 PMC1CON1 PMC1CON2 PMC1CON3 PMC1STS PMC1INT PMC1HDPMIN PMC1HDPMAX PMC1D0PMIN PMC1D0PMAX PMC1D1PMIN PMC1D1PMAX PMC1TIM PMC1BC After Reset XXX0 X000b XXXX 0X00b 00h 00h X000 X00Xb X000 X00Xb 00h XXXX X000b 00h XXXX X000b 00h 00h 00h 00h 00h 00h 00h 00h REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 444 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.2.1 PMCi Function Select Register (PMCiCON0) (i = 0, 1) PMC0 Function Select Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PMC0CON0 Bit Symbol EN SINV FIL Address 01F0h Bit Name PMC0 operation enable bit Input signal polarity invert bit Filter enable bit Function 0: Operation disabled 1: Operation enabled 0: Not inverted 1: Inverted 0: Filter disabled 1: Filter enabled After Reset 00h RW RW RW RW EHOLD Error flag hold bit State of the REFLG bit in the PMCiSTS register: 0: Held until next data received 1: Held even after next data received 0: Header disabled 1: Header enabled 0: Special data pattern disabled 1: Special data pattern enabled Interrupt request is generated under the following conditions: b7 b6 RW HDEN SDEN Header pattern enable bit Special data pattern enable bit RW RW DRINT0 Receive interrupt control bit DRINT1 0 0: When reception completed 0 1: When compare match occurs and RW reception completed 1 0: When no receive error occurs and reception completed 1 1: When compare match and no receive error occurs, and reception completed PMC1 Function Select Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PMC1CON0 Bit Symbol EN SINV FIL — (b3) HDEN — (b7-b5) Address 01F8h Bit Name PMC1 operation enable bit Input signal polarity invert bit Filter enable bit Function 0: Operation disabled 1: Operation enabled 0: Not inverted 1: Inverted 0: Filter disabled 1: Filter enabled After Reset XXX0 X000b RW RW RW RW — RW — No register bit. If necessary, set to 0. Read as undefined value. Header pattern enable bit 0: Header disabled 1: Header enabled No register bits. If necessary, set to 0. Read as undefined value. EN (PMC0 Operation Enable Bit) (b0) The EN bit is used to control start/stop of PMCi operation. Confirm that the operation has started or stopped by the ENFLG bit in the PMCiCON2 register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 445 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver EHOLD (Error Flag Hold Bit) (b3) When receive error occurs, period when the REFLG bit in the PMC0STS register holds 1 (receive error) can be selected. Refer to “REFLG (Receive Error Flag) (b1)” in 22.2.5 “PMCi Status Register (PMCiSTS) (i = 0, 1)” for details. HDEN (Header Pattern Enable Bit) (b4) If the HDEN bit is set to 1 (header enabled), the following occur when detecting data 0, data 1, or special data before detecting header. • The REFLG bit in the PMCiSTS register becomes 1 (error occurs) • Bits PTD0FLG, PTD1FLG, and SDFLG in the PMCiSTS register remain unchanged. • Registers PMCDAT0 to PMCDAT5 remain unchanged. DRINT1-DRINT0 (Receive Interrupt Control Bit) (b7-b6) A condition for generating a data reception complete interrupt request can be selected. Set the DRINT bit in the PMC0INT register to 1 (reception complete interrupt enabled) after setting bits DRINT1 to DRINT0. When setting the DRINT1 bit to 1, set the EHOLD bit in the PMC0CON0 register to 1 (hold the REFLG bit state after next data received). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 446 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.2.2 PMCi Function Select Register (PMCiCON1) (i = 0, 1) PMC0 Function Select Register 1 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol PMC0CON1 Bit Symbol Address 01F1h Bit Name b1 b0 After Reset 00XX 0000b Function 0 0 : Period measurement (between rising edge and rising edge) 0 1 : In pattern match mode, high level width measurement (between rising edge and falling edge) In input capture mode, period measurement (between falling edge and falling edge) 1 0 : Pulse width measurement (between rising edge and falling edge, and falling edge and rising edge) 1 1 : Do not set. RW TYP0 Receive mode select bit RW TYP1 CSS — (b3) — (b5-b4) EXSDEN EXHDEN Counter start control bit Reserved bit 0: Counters operate individually 1: Counters operate simultaneously Set to 0. RW RW — RW RW No register bits. If necessary, set to 0. Read as undefined value. Special pattern detect block select bit Header pattern detect block select bit 0: PMC0 1: PMC1 0: PMC0 1: PMC1 PMC1 Function Select Register 1 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol PMC1CON1 Bit Symbol Address 01F9h Bit Name b1 b0 After Reset XXXX 0X00b Function 0 0 : Period measurement (between rising edge and rising edge) 0 1 : In pattern match mode, high level width measurement (between rising edge and falling edge) In input capture mode, period measurement (between falling edge and falling edge) 1 0 : Pulse width measurement (between rising edge and falling edge, and falling edge and rising edge) 1 1 : Do not set. RW TYP0 Receive mode select bit RW TYP1 — (b2) — (b3) — (b7-b4) No register bit. If necessary, set to 0. Read as undefined value. Reserved bit Set to 0. — RW — No register bits. If necessary, set to 0. Read as undefined value. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 447 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver EXSDEN (Special Pattern Detect Block Select Bit) (b6) EXHDEN (Header Pattern Detect Block Select Bit) (b7) Use these bits when PMC0 and PMC1 are linked and operated in pattern match mode. Otherwise, set to 0. Set bits EXHDEN and EXSDEN to 01b or 10b when setting the HDEN bit in the PMC0CON0 register to 1 (header enabled) and SDEN bit to 1 (special data enabled). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 448 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.2.3 PMCi Function Select Register 2 (PMCiCON2) (i = 0, 1) PMC0 Function Select Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol PMC0CON2 Bit Symbol ENFLG — (b1) — (b2) INFLG CEFLG CEINT PSEL0 Address 01F2h Bit Name PMC0 status flag Reserved bit Reserved bit Input signal flag Counter overflow flag Counter overflow interrupt enable bit 0: Stops 1: Operating Read as undefined value Set to 0 Function After Reset 00h RW RO RO RW RO RO RW 0: PMCi internal input signal level is low 1: PMCi internal input signal level is high 0: No overflow 1: Overflows 0: Disabled 1: Enabled b7 b6 Input pin select bit PSEL1 0 0 1 1 0 : Same as PMC1 1 : PMC0 pin 0 : Do not set 1 : Do not set RW PMC1 Function Select Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol PMC1CON2 Bit Symbol ENFLG — (b1) — (b2) INFLG CEFLG CEINT PSEL0 Address 01FAh Bit Name PMC1 status flag Reserved bit Reserved bit Input signal flag Counter overflow flag Counter overflow interrupt enable bit 0: Stops 1: Operating Read as undefined value Set to 0 Function After Reset 00h RW RO RO RW RO RO RW 0: PMCi internal input signal level is low 1: PMCi internal input signal level is high 0: No overflow 1: Overflows 0: Disabled 1: Enabled b7 b6 Input pin select bit PSEL1 0 0 1 1 0 : In an idle state 1 : PMC0 pin 0 : PMC1 pin 1 : Do not set RW REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 449 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver CEFLG (Counter Overflow Flag) (b4) Condition to become 0: • The EN bit is 0 (PMCi operation stops) • Measurement timing selected by bits TYP1 to TYP0 in the PMCiCON1 register Condition to become 1: • The first counter overflow (the value exceeds FFFFh) PSEL1-PSEL0 (Input Pin Select Bit) (b7-b6) Change these bits when the EN bit in the PMCiCON0 register and the ENFLG bit in the PMCiCON2 register are both 0 (PMCi stops). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 450 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.2.4 PMCi Function Select Register 3 (PMCiCON3) (i = 0, 1) PMC0 Function Select Register 3 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PMC0CON3 Bit Symbol CRE CFR Address 01F3h Bit Name Function After Reset 00h RW b3 b2 b1 b0 Mode select bit CST PD CSRC0 Clock source select bit CSRC1 CDIV0 Count source divisor select bit CDIV1 0 0 0 0 : Pattern match mode 1 1 1 1 : Input capture mode Do not set values not listed above. RW b5 b4 0 0 1 1 0 0 1 1 0 : Same as PMC1 1 : f1 0 : fC1 1 : Timer B2 underflow 0 : No division 1 : Divided-by-8 0 : Divided-by-32 1 : Divided-by-64 RW b7 b6 RW PMC1 Function Select Register 3 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PMC1CON3 Bit Symbol CRE CFR Address 01FBh Bit Name Function After Reset 00h RW b3 b2 b1 b0 Mode select bit CST PD CSRC0 Clock source select bit CSRC1 CDIV0 Count source divisor select bit CDIV1 0 0 0 0 : Pattern match mode 1 1 1 1 : Input capture mode Do not set values not listed above. RW b5 b4 0 0 1 1 0 0 1 1 0 : f1 1 : Timer B1 underflow 0 : fC1 1 : Timer B2 underflow 0 : No division 1 : Divided-by-8 0 : Divided-by-32 1 : Divided-by-64 RW b7 b6 RW CDIV1-CDIV0 (Clock Source Select Bit) (b5-b4) When bits CSCR1 to CSCR0 in the PMC0CON3 register is set to 00b (same as PMC1), set bits CDIV1 to CDIV0 in the PMC0CON3 register to 00b (no division). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 451 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.2.5 PMCi Status Register (PMCiSTS) (i = 0, 1) PMC0 Status Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PMC0STS Bit Symbol CPFLG REFLG DRFLG BFULFLG PTHDFLG PTD0FLG PTD1FLG SDFLG Address 01F4h Bit Name Compare match flag Receive error flag Data receiving flag Receive buffer full flag Header pattern match flag Data 0 pattern match flag Data 1 pattern match flag Special pattern match flag 0: Not match 1: Match 0: No error occurs 1: Error occurs 0: Waiting for data reception 1: Data receiving Function After Reset 00h RW RO RO RO RO RO RO RO RO 0: Receive buffer empty 1: Receive buffer full (48 bits received) 0: Not match 1: Match 0: Not match 1: Match 0: Not match 1: Match 0: Not match 1: Match PMC1 Status Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PMC1STS Bit Symbol — (b0) REFLG DRFLG — (b3) PTHDFLG PTD0FLG PTD1FLG — (b7) Address 01FCh Bit Name Function After Reset X000 X00Xb RW — RO RO — RO RO RO — No register bit. If necessary, set to 0. Read as undefined value. Receive error flag Data receiving flag 0: No error occurs 1: Error occurs 0: Waiting for data reception 1: Data receiving No register bit. If necessary, set to 0. Read as undefined value. Header pattern match falg Data 0 pattern match flag Data 1 pattern match flag 0: Not match 1: Match 0: Not match 1: Match 0: Not match 1: Match No register bit. If necessary, set to 0. Read as undefined value. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 452 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver CPFLG (Compare Match Flag) (b0) This bit is valid when the CPEN bit in the PMC0CPC register is set to 1 (compare enabled). Condition to become 0: • When the DRFLG bit in the PMC0STS register changes from 0 to 1 (next frame reception starts). • When the 48th bit is received after the CPFLG bit becomes 1, and then (the DRFLG bit remains 1 (receiving)) no compare match occurs after receiving bit n (n = value set by bits CPN2 to CPN0 in the PMC0CPC register) Condition to become 1: • The PMC0CPD register matches the PMC0DAT0 register (when the setting value of bits CPN2 to CPN0 in the PMC0CPC register is n, bits n to 0 in the PMC0CPD register matches bits n to 0 in the PMC0DAT0 register). REFLG (Receive Error Flag) (b1) The REFLG bit is a flag indicating receive error. Conditions for changing the REFLG bit are affected by the HDEN bit in the PMCiCOM0 register and bits EHOLD and SDEN in the PMC0COM0 register. Table 22.5 lists Conditions for Changing the REFLG Bit. Table 22.5 Conditions for Changing the REFLG Bit Conditions for Changing the REFLG Bit Conditions for Changing the REFLG bit to 1 (2) to 0 (2)(3) Input signal width is neither data 0 nor Receive data 0 or data 1 (or special data 1 (special data) data) 0 1 • Input signal width is none of header, • Receive header data 0, or data 1 (special data) • Receive header prior to data 0 or data • Detect data 0 or data 1 (or special 1 (or special data) data) prior to header 1 0 Input signal width is neither data 0 nor data 1 (special data) 1 1 • Input signal width is none of header, • Receive header data 0, or data 1 (special data) • Detect data 0 or data1 (or special data) prior to header EHOLD: Bit in the PMC0COM0 register HDEN: Bit in the PMCiCOM0 register (i = 0, 1) Notes: 1. Refer to EHOLD = 0 when operating PMC1 individually. 2. Special data is added to the conditions when the SDEN bit in the PMC0COM0 register is 1 (special data enabled) 3. The REFLG bit becomes 0 regardless of bits HEDN and EHOLD under the following conditions: •EN bit is 0 (PMCi stops) •The DRFLG bit in the PMCiSTS register changes from 0 to 1 (next frame reception starts) Bit Setting (1) EHOLD HDEN 0 0 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 453 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver DRFLG (Data Receiving Flag) (b2) The DRFLG bit indicates the receiving state of the remote control signal. Condition to become 0: • The counter value is larger than values of registers PMCiHDPMAX, PMCiD0PMAX, and PMCiD1PMAX (if the counter value is larger than these register values, this bit becomes 0 after waiting for 1 to 2 cycles of the count source). Condition to become 1: It depends on bits TYP1 to TYP0 in the PMCiCON1 register (receive mode select). • When bits TYP1 to TYP0 are 00b (pulse period measurement) or 01b (high level width measurement): rising edge of the PMCi internal input signal • When bits TYP1 to TYP0 are 10b (pulse width measurement): rising edge and falling edge of the PMCi internal input signal BFULFLG (Receive Buffer Full Flag) (b3) Condition to become 0: • The value of the PMC0RBIT register changes from 48 to 1. Condition to become 1: • The value of the PMC0RBIT register is 48. PTHDFLG (Header Pattern Match Flag) (b4), PTD0FLG (Data 0 Pattern Match Flag) (b5), PTD1FLG (Data 1 Pattern Match Flag) (b6), SDFLG (Special Pattern Match Flag) (b7) Condition to become 0: • The EN bit is 0 (PMCi stops) • DRFLG bit in the PMCiSTS register changes from 0 to 1 (next frame reception starts) • Refer to Table 22.6 “Measurements and Flag”. Condition to become 1: • Refer to Table 22.6 “Measurements and Flag”. Table 22.6 Measurements and Flag Value (Measurements) of the PMCiTIM Register Between PMCiHDPMIN and PMCiHDPMAX (header measurement in PMCi) Between PMCiD0PMIN and PMCiD0PMAX Between PMCiD1PMIN and PMCiD1PMAX PTHDFLG 1 0 Flag PTD0FLG PTD1FLG 0 1 (1) 0 0 0 (1) SDFLG 0 0 0 0 1 Between PMCiHDPMIN and PMCiHDPMAX 0 0 0 1 (1) (special data measurement in PMCi) Other than those above 0 0 0 0 Note: 1. When the HDEN bit in the PMCiCON0 register is 1(header enabled), PTD0FLG, PTD1FLG, and SDFLG remain unchanged until header is detected. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 454 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.2.6 PMCi Interrupt Source Register (PMCiINT) (i = 0, 1) PMC0 Interrupt Source Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PMC0INT Bit Symbol CPINT REINT DRINT BFULINT PTHDINT PTDINT TIMINT SDINT Address 01F5h Bit Name Compare match flag interrupt enable bit Receive error flag interrupt enable bit Data reception complete interrupt enable bit Receive buffer full flag interrupt enable bit Header match flag interrupt enable bit Data 0/1 match flag interrupt enable bit Timer measure interrupt enable bit Special data match flag interrupt enable bit 0: Disabled 1: Enabled 0: Disabled 1: Enabled 0: Disabled 1: Enabled 0: Disabled 1: Enabled 0: Disabled 1: Enabled 0: Disabled 1: Enabled 0: Disabled 1: Enabled 0: Disabled 1: Enabled Function After Reset 00h RW RW RW RW RW RW RW RW RW PMC1 Interrupt Source Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PMC1INT Bit Symbol — (b0) REINT DRINT — (b3) PTHDINT PTDINT TIMINT — (b7) Address 01FDh Bit Name Function After Reset X000 X00Xb RW — RW RW — RW RW RW — No register bit. If necessary, set to 0. Read as undefined value. Receive error flag interrupt enable bit Data reception complete interrupt enable bit 0: Disabled 1: Enabled 0: Disabled 1: Enabled No register bit. If necessary, set to 0. Read as undefined value. Header match flag interrupt enable bit Data 0/1 match flag interrupt enable bit Timer measure interrupt enable bit 0: Disabled 1: Enabled 0: Disabled 1: Enabled 0: Disabled 1: Enabled No register bit. If necessary, set to 0. Read as undefined value. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 455 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.2.7 PMCi Header Pattern Set Register (MIN) (PMCiHDPMIN) (i = 0, 1) PMCi Header Pattern Set Register (MAX) (PMCiHDPMAX) (i = 0, 1) PMCi Header Pattern Set Register (MIN) (i = 0, 1) (b15) b7 (b8) b0 b7 b0 Symbol PMC0HDPMIN PMC1HDPMIN Address D081h to D080h D095h to D094h Function After Reset XXXX X000 0000 0000b XXXX X000 0000 0000b Setting Range 0000h to 07FFh RW RW Set the minimum width of header pattern or special data pattern. No register bits. If necessary, set to 0. Read as undefined value. — PMCi Header Pattern Set Register (MAX) (i = 0, 1) (b15) b7 (b8) b0 b7 b0 Symbol PMC0HDPMAX PMC1HDPMAX Address D083h to D082h D097h to D096h Function After Reset XXXX X000 0000 0000b XXXX X000 0000 0000b Setting Range 0000h to 07FFh RW RW Set the maximum width of header pattern or special data pattern. No register bits. If necessary, set to 0. Read as undefined value. — S et the minimum width of header or special data pattern to the PMCiHDPMIN register and the maximum width to the PMCiHDPMAX. Minimum width (maximum width) of header or special data pattern Count source Setting value n = Set the different value from data 0 or data 1 to these register. Set the following: PMCiHDPMIN register value < PMCiHDPMAX register value. When not using header or special data detection, set registers PMCiHDPMIN and PMCiHDPMAX to 0000h. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 456 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.2.8 PMCi Data 0 Pattern Set Register (MIN) (PMCiD0PMIN) (i = 0, 1) PMCi Data 0 Pattern Set Register (MAX) (PMCiD0PMAX) (i = 0, 1) PMCi Data 1 Pattern Set Register (MIN) (PMCiD1PMIN) (i = 0, 1) PMCi Data 1 Pattern Set Register (MAX) (PMCiD1PMAX) (i = 0, 1) PMCi Data 0 Pattern Set Register (MIN) (i = 0, 1) b7 b0 Symbol PMC0D0PMIN PMC1D0PMIN Address D084h D098h Function After Reset 00h 00h Setting Range 00h to FFh RW RW Set the minimum width of data 0 pattern. PMCi Data 0 Pattern Set Register (MAX) (i = 0, 1) b7 b0 Symbol PMC0D0PMAX PMC1D0PMAX Address D085h D099h Function After Reset 00h 00h Setting Range 00h to FFh RW RW Set the maximum width of data 0 pattern. PMCi Data 1 Pattern Set Register (MIN) (i = 0, 1) b7 b0 Symbol PMC0D1PMIN PMC1D1PMIN Address D086h D09Ah Function After Reset 00h 00h Setting Range 00h to FFh RW RW Set the minimum width of data 1 pattern. PMCi Data 1 Pattern Set Register (MAX) (i = 0, 1) b7 b0 Symbol PMC0D1PMAX PMC1D1PMAX Address D087h D09Bh Function After Reset 00h 00h Setting Range 00h to FFh RW RW Set the maximum width of data 1 pattern. Set the minimum width of data 0 pattern to the PMCiD0PMIN register and the maximum width to the PMCiD0PMAX register. Also set the minimum width of data 1 pattern to the PMCiD1PMIN register and the maximum width to the PMCiD1PMAX register. minimum width (maximum width) of data 0/1 pattern count source Setting value n = Data 0, data 1, and header or special data pattern must be the different values. Set the following: PMCiD0PMIN register value < PMCiD0PMAX register value, and PMCiD1PMIN < PMCiD1PMAX. When not detecting data 0, registers PMCiD0PMIN and PMCiD0PMAX to 00h. When not detecting data 1, registers PMCiD1PMIN and PMCiD1PMAX to 00h. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 457 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.2.9 PMCi Measurements Register (PMCiTIM) (i = 0, 1) PMCi Measurements Register (b15) b7 (b8) b0 b7 b0 Symbol PMC0TIM PMC1TIM Address D089h to D088h D09Dh to D09Ch Function After Reset 0000h 0000h RW RO Measurements of pulse period and pulse width can be read. 22.2.10 PMCi Counter Value Register (PMCiBC) (i = 0, 1) PMCi Counter Value Register (i = 0, 1) (b15) b7 (b8) b0 b7 b0 Symbol PMC0BC PMC1BC Address D08Bh to D08Ah D09Fh to D09Eh Function After Reset 0000h 0000h RW RO The state of the counter can be read. 22.2.11 PMC0 Receive Bit Count Register (PMC0RBIT) PMC0 Receive Bit Count Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PMC0RBIT Address D092h Function After Reset XX00 0000b RW RO — Receive bit count can be read. No register bit. If necessary, set to 0. Read as undefined value. Bit position of the storing buffer is specified by counting detected data 0/1. When the receive bit count exceeds 48, it returns 1. Header and special data are not counted. When the DRFLG bit in the PMC0STS register changes from 0 to 1, the PMC0RBIT register becomes 0. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 458 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.2.12 PMC0 Receive Data Store Register i (PMC0DATi) (i = 0 to 5) PMC0 Receive Data Store Register i (i = 0 to 5) b7 b0 Symbol PMC0DAT0 PMC0DAT1 PMC0DAT2 PMC0DAT3 PMC0DAT4 PMC0DAT5 Address D08Ch D08Dh D08Eh D08Fh D090h D091h Function After Reset 00h 00h 00h 00h 00h 00h RW RO Received data is stored. When detecting data 0 or data 1, the result is stored bit by bit according to the PMC0RBIT register. The data is stored into the PMC0DATi register starting from the bit 0 in the PMC0DAT0 register. Table 22.7 lists Order of Storing Data. When the data exceeds 48 bits, the PMC0DATi register is sequentially overwritten from the first bit in the PMC0DAT0 register. Also, after the DRFLG bit in the PMCiSTS register changes from 0 to 1 (next frame reception starts), the PMC0DATi register is sequentially overwritten from the first bit in the PMC0DAT0 register. Header and special data are not stored. Table 22.7 Order of Storing Data Register PMC0DAT0 PMC0DAT1 PMC0DAT2 PMC0DAT3 PMC0DAT4 PMC0DAT5 b7 8 16 24 32 40 48 b6 7 15 23 31 39 47 b5 6 14 22 30 38 46 b4 5 13 21 29 37 45 b3 4 12 20 28 36 44 b2 3 11 19 27 35 43 b1 2 10 18 26 34 42 b0 1 9 17 25 33 41 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 459 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.2.13 PMC0 Compare Control Register (PMC0CPC) PMC0 Compare Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PMC0CPC Bit Symbol CPN0 CPN1 CPN2 — (b3) CPEN — (b7-b5) Address 01F6h Bit Name Function After Reset XXX0 X000b RW RW Compare bit specified bit When the setting value is n, bits n to 0 are compared. RW RW No register bit. If necessary, set to 0. Read as undefined value. Compare enable bit 0: Compare disabled 1: Compare enabled — RW — No register bits. If necessary, set to 0. Read as undefined value. CPN2-CPN0 (Compare Bit Specified Bit) (b2-b0) These bits are valid when the CPEN bit is 1 (compare enabled). When the setting value of bits CPN2 to CPN0 is n, bits n to 0 are compared. e.g.1 Setting value = 0 Bit 0 in the PMC0CPD register and bit 0 in the PMC0DAT0 register are compared. e.g.2 Setting value = 7 Bits 7 to 0 in the PMC0CPD register and bits 7 to 0 in the PMC0DAT0 register are compared. CPEN (Compare Enable Bit) (b4) When the CPEN bit is 1 (compare enabled), contents of registers PMC0CPD and PMC0DAT0 are compared. The contents are matched, the CPFLG bit in the PMC0STS register becomes 1 (compare match). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 460 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.2.14 PMC0 Compare Data Register (PMC0CPD) PMC0 Compare Data Register b7 b0 Symbol PMC0CPD Address 01F7h After Reset 00h Function Compare data RW RW This register is valid when the CPEN bit in the PMC0CPC register is 1 (compare enabled). Bits to be compared are selected by bits CPN2 to CPN0 in the PMC0CPC register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 461 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.3 22.3.1 Operations Common Operations in Multiple Modes Count Source 22.3.1.1 Clock source and divisor of the count source can be selected by bits CSRC1 to CSRC0 and bits CDIV1 to CDIV0 in the PMCiCON3 register (Refer to Figure 22.3 “Remote Control Signal Receiver Block Diagram (3/3) (PMCi Count Source)”). When using fC, set the PM25 bit in the PM2 register to 1 (peripheral clock fC provided). Refer to 8. “Clock Generator” for details of fC. When using timer B1 or B2 underflow, the internal signal of a timer B1 or B2 is inverted every time the timer B1 or B2 underflows. This internal signal is the count source. One cycle of the count source consists of two timer B1 or B2 underflow cycles. Figure 22.4 shows Clock Source When Selecting Timer B1 or B2 Underflow. Use the timer B1 or B2 in timer mode. Refer to 18. “Timer B” for details. Timer B2 underflow cycle Count source (timer B2 internal signal) Timer B2 underflow cycle Inverted by underflow Clock source cycle The above diagram shows an instance of timer B2 Operation is the same in timer B1. Figure 22.4 Clock Source When Selecting Timer B1 or B2 Underflow To use the same count source in PMC0 and PMC1, set bits CSRC1 to CSRC0 in the PMC0CON3 register to 00b (same count source as PMC1), and bits CDIV1 to CDIV0 in the PMC0CON3 register to 00b (no division). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 462 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.3.1.2 PMCi Input The following can be selected in PMCi input (Refer to Figure 22.2 “Remote Control Signal Receiver Block Diagram (2/3) (PMCi Input)”). • Input pin • Input polarity • Digital filter A pin to which the PMCi signal is input is selected by bits PSEL1 to PSEL0 in the PMCiCON2 register. Input polarity of the PMCi pin can be inverted. Whether to invert or not can be selected by the SINV bit in the PMCiCON0 register. If the signal input to the PMCi pin holds the same level four sequential cycles when the FIL bit in the PMCiCON0 register is 1 (digital filter enabled), that level is transferred to internal circuit. Sampling clock of the digital filter is the count source. Input to the PMCi pin is transferred to the internal circuit in synchronization with the count source. Internal processing causes delay. Figure 22.5 shows PMCi Input Delay. Sampling clock (count source) PMCi pin input Holds the same level during four sequential cycles Internal processing (2 cycles) Holds the same level during four sequential cycles Digital filter output (internal signal) PMCi internal input signal FIL = 1(digital filter enabled) FIL = 0(digital filter disabled) Internal processing Internal processing (5 to 6 cycles) i = 0, 1 FIL: Bit in the PMCiCON0 register Figure 22.5 PMCi Input Delay REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 463 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.3.2 Pattern Match Mode (PMC0 and PMC1 Operate Individually) Pattern match mode determines whether external pulse matches specified pattern. Header, data 0, and data 1 patterns can be measured in PMC0 and PMC1 separately. Table 22.8 lists Specifications in Pattern Match Mode (Individual Operation), Table 22.9 and Table 22.10 list registers and setting values in pattern match mode (individual operation), Figure 22.6 shows Difference of Operations in Receive Modes (Pattern Match Mode), and Figure 22.7 shows Flag Operation Example. Table 22.8 Specifications in Pattern Match Mode (Individual Operation) Contents PMC0 Circuit PMC1 Circuit One of the following: Count Clock One of the following: sources sources • fC • fC • f1 • f1 • Timer B2 underflow • Timer B1 underflow • Count source of PMC1 • Timer B2 underflow Division No division, divided-by-8, divided-by-32, or divided-by-64 Count operation Increment Detect patterns • Header or special data • Header • Data 0 • Data 0 • Data 1 • Data 1 Receive buffer 6 bytes (48 bits) None Interrupt request generation • Receive error • Receive error timing • Completion of data reception • Completion of data reception • Header match • Header match • Data 0/1 match • Data 0/1 match • Special data match • Receive buffer full • Compare match Selectable functions • Input signal inversion • Digital filter Item REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 464 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver Table 22.9 Registers and Setting Values in Pattern Match Mode (Individual Operation) (1/2) Register PMCiCON0 EN SINV FIL EHOLD HDEN SDEN Bit Function PMC0 1 Select input signal polarity Select filter enabled or disabled Select receive error holding period Select header enabled or disabled Select special data enabled or disabled Select receive interrupt generating condition Select measuring object 0 0 0 Flag indicating PMCi operated/ stopped Input signal flag Not used 0 01b 0 0 0 0 Select clock source Select count source divisor Compare match flag Receive error flag Data receiving flag Receive buffer full flag Header pattern match flag Data 0 pattern match flag Data 1 pattern match flag Special pattern match flag PMC1 1 Select input signal polarity Select filter enabled or disabled Select header enabled or disabled Select measuring object Flag indicating PMCi operated/ stopped Input signal flag Not used 0 Select input pin 0 0 0 0 Select clock source Select count source divisor Receive error flag Data receiving flag Header pattern match flag Data 0 pattern match flag Data 1 pattern match flag - PMCiCON1 PMCiCON2 DRINT0 DRINT1 TYP0 TYP1 CSS EXSDEN EXHDEN ENFLG INFLG CEFLG CEINT PSEL0 PSEL1 CRE CFR CST PD CSRC0 CSRC1 CDIV0 CDIV1 CPFLG REFLG DRFLG BFULFLG PTHDFLG PTD0FLG PTD1FLG SDFLG PMCiCON3 PMCiSTS i = 0, 1 -: No register bits in PMC1 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 465 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver Table 22.10 Registers and Setting Values in Pattern Match Mode (Individual Operation) (2/2) Register PMCiINT CPINT REINT DRINT Bit BFULINT PTHDINT PTDINT TIMINT SDINT PMCiCPC CPN0 CPN1 CPN2 CPEN 0 to 7 0 to 10 0 to 10 0 to 7 Function PMC0 PMC1 Set to 1 when using compare match flag interrupt Set to 1 when using receive Set to 1 when using receive error flag interrupt error flag interrupt Set to 1 when using data Set to 1 when using data reception complete interrupt reception complete interrupt Set to 1 when using receive buffer full flag interrupt Set to 1 when using header Set to 1 when using header match flag interrupt match flag interrupt Set to 1 when using data 0/1 Set to 1 when using data 0/1 match flag interrupt match flag interrupt Set to 1 when using timer Set to 1 when using timer measure interrupt measure interrupt Set to 1 when using special data match flag interrupt Select bits to be compared when using compare function Set to 1 when using compare function Set compare value when using compare function Set minimum value of header pattern Set maximum value of header pattern Set minimum value of data 0 pattern Set maximum value of data 0 pattern Set minimum value of data 1 pattern Set maximum value of data 1 pattern Measured value of pulse period or width can be read Counter value can be read Received data can be read Set minimum value of header pattern Set maximum value of header pattern Set minimum value of data 0 pattern Set maximum value of data 0 pattern Set minimum value of data 1 pattern Set maximum value of data 1 pattern Measured value of pulse period or width can be read Counter value can be read - PMCiCPD PMCiHDPMIN PMCiHDPMAX PMCiD0PMIN PMCiD0PMAX PMCiD1PMIN PMCiD1PMAX PMCiTIM 0 to 7 0 to 7 0 to 7 0 to 15 PMCiBC 0 to 15 PMCiDAT0 to 0 to 7 PMCiDAT5 PMC0RBIT 0 to 5 i = 0, 1 -: No register bit in PMC1 Received bit count can be read - REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 466 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver PMCi internal input signal EN bit Bits TYP1 to TYP0 are 00b (period measurement) a Counter operation Count starts Overflow at the setting value b Count stops Count starts PMCiTIM register a b IR bit The bit becomes 0 when an interrupt request is accepted, or by setting the bit to 0. Bits TYP1 to TYP0 are 01b (high level width measurement) Counter operation a b c Overflow at the setting value Count stops Count starts PMCiTIM register a b c IR bit The bit becomes 0 when an interrupt request is accepted, or by setting the bit to 0. Bits TYP1 to TYP0 are 10b (pulse width measurement) Counter operation a b c d e Overflow at the setting value Count stops Count starts PMCiTIM register a b c d e IR bit The bit becomes 0 when an interrupt request is accepted, or by setting the bit to 0. DRFLG i = 0, 1 Frame ends Next frame stars EN: Bit in the PMCiCON0 register DRFLG: Bit in the PMCiSTS register IR: Bit in the PMCiIC register Overflow at the setting value: Counter value is larger than values of registers PMCiHDPMAX, PMCiD0PMAX, and PMCiD1MAX. The above diagram shows an instance in which the following conditions are met: The TIMINT bit in the PMCiINT register is 1(timer measure interrupt enabled) Bits other than the TIMINT bit in the PMCiINT register are 0 (interrupt disabled) The COINT bit in the PMCiCON2 register is 0 (interrupt disabled) Figure 22.6 Difference of Operations in Receive Modes (Pattern Match Mode) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 467 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver Frame ends Data 0 PMCi internal input signal DRFLG Receive error Data 1 Data 0 Next frame starts PTD0FLG PTD1FLG REFLG (EHOLD = 0) REFLG (EHOLD = 1, HDEN = 0) Receive error is detected Becomes 0 when next data is detected Becomes 0 when next data is detected i = 0, 1 REFLG, DRFLG, PTD0FLG, PTD1FLG: Bits in the PMCiSTS register Figure 22.7 Flag Operation Example REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 468 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.3.2.1 Header Detection (PMC0, PMC1) When the HDEN bit in the PMCiCON0 register is 1 (header enabled), the following occur by detecting data 0, data 1, or special data prior to header. • The REFLG bit in the PMCiSTS register becomes 1 (error occurs). • Bits PTD0FLG, PTD1FLG, and SDFLG in the PMCiSTS register remain unchanged. • Registers PMCDAT0 to PMCDAT5 remain unchanged. When detecting header in PMC0, set the SDEN bit in the PMC0CON0 register to 0 (special data disabled). 22.3.2.2 Special Data Detection (PMC0) When the SDEN bit in the PMC0COM0 register is 1 (special data enabled), special data can be detected. When detecting the special data, set the HDEN bit in the PMC0CON0 register to 0 (header disabled). 22.3.2.3 Receive Data Buffer (PMC0) There is a 6-byte (48-bit) buffer for storing received data. When the data exceeds 48 bits, the buffer is sequentially overwritten from the first bit. Refer to 22.2.12 “PMC0 Receive Data Store Register i (PMC0DATi) (i = 0 to 5)” and 22.2.11 “PMC0 Receive Bit Count Register (PMC0RBIT)”. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 469 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.3.2.4 Compare Function (PMC0) Contents of registers PMC0CPD and PMCDAT0 are compared. Reception of the specific data which is 1 to 8 bits can be detected. When using compare function, follow the instructions below: • The CPEN bit in the PMC0CPC register: 1 (compare enabled) • Select bits to be compared by bits CPN2 to CPN0 in the PMC0CPC register (when setting value is n, bits n to 0 are compared. n: 0 to 7) • Set the compare data in the PMC0CPD register The contents which have been compared are matched, the CPFLG bit in the PMC0STS register becomes 1 (compare match). Data 0 PMC0 internal input signal ENFLG bit in the PMC0CON2 register PMC0RBIT register 0 Data 1 Data 1 Data 0 Data 1 Data 0 1 2 3 4 8 9 PMC0DAT0 register 0000 0000b 0000 0000b 0000 0010b 0000 0110b 0000 0110b Data 0 is stored in bit 0 Data 1 is stored in bit 1 Data 1 is stored in bit 2 Data 0 is stored in bit 3 1111 0110b Data 1 is stored in bit 7 0000 0001b Data 1 is stored in bit 8 PMC0DAT1 register 0000 0000b PMC0CPD register XXXX X110b CPFLG bit in the PMC0STS register Compare match The above diagram shows an instance in which the following conditions are met: The CPEN bit in the PMC0CPC register is 1 (compare enabled) Bits CPN2 to CPN0 in the PMC0CPC register is 2 (bits 2 to 0 are compared) Figure 22.8 Receive Buffer and Compare Function REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 470 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.3.3 Pattern Match Mode (Connected Operation of PMC0 and PMC1) PMC0 and PMC1 is connected and one remote control signal can be received. In connected operation, data 0 and data 1 are detected in PMC1. Whether to detect header and special data in PMC0 or PMC 1 can be selected. Select count source and remote control signal input pins in PMC1. Table 22.11 lists Specifications in Pattern Match Mode (Connected Operation) and Figure 22.1 and Figure 22.2 shows registers and setting values in pattern match mode (connected operation). Table 22.11 Specifications in Pattern Match Mode (Connected Operation) Item Count sources Clock sources Content PMC0 Circuit Count source of PMC1 PMC1 Circuit One of the following: • fC • f1 • Timer B1 underflow • Timer B2 underflow No division, divided-by-8, dividedby-32, or divided-by-64 Division Count operation Detect patterns No division Increment • Header • Data 0 • Data 1 • Special data 6 bytes (48 bits) • Receive error • Completion of data reception • Header match • Data 0/1 match • Special data match • Receive buffer full • Compare match • Input signal inversion • Digital filter • Header • Special data None Not used Receive buffer Interrupt request generation timing Selectable functions REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 471 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver Table 22.12 Registers and Setting Values in Pattern Match Mode (Connected Operation) (1/2) Register PMCiCON0 EN SINV FIL EHOLD HDEN SDEN Bit PMCiCON1 PMCiCON2 DRINT0 DRINT1 TYP0 TYP1 CSS EXSDEN EXHDEN ENFLG INFLG CEFLG CEINT PSEL0 PSEL1 CRE CFR CST PD CSRC0 CSRC1 CDIV0 CDIV1 CPFLG REFLG DRFLG BFULFLG PTHDFLG PTD0FLG PTD1FLG SDFLG Function PMC0 PMC1 1. Refer to 22.3.3.1 “Setting 1. Refer to 22.3.3.1 “Setting Procedure” Procedure” 0 Select input signal polarity 0 Select filter enabled/disabled Select receive error holding period Select header enabled/ 1 disabled Select special data enabled/ disabled Select receive interrupt generating condition Select measuring object Select measuring object 0 Select block in which header and special pattern is detected Flag indicating PMCi operated/ stopped Input signal flag Not used 0 00b 0 0 0 0 00b 00b Compare match flag Receive error flag Data receiving flag Receive buffer full flag Header pattern match flag Data 0 pattern match flag Data 1 pattern match flag Special pattern match flag Flag indicating PMCi operated/ stopped Not used Not used 0 Select input pin 0 0 0 0 Select clock source Select count source divisor Not used Not used Not used Not used Not used - PMCiCON3 PMCiSTS i = 0, 1 -: No register bit in PMC1 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 472 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver Table 22.13 Registers and Setting Values in Pattern Match Mode (Connected Operation) (2/2) Register PMCiINT CPINT REINT DRINT Bit BFULINT PTHDINT PTDINT TIMINT SDINT PMCiCPC CPN0 CPN1 CPN2 CPEN 0 to 7 0 to 10 0 to 10 0 to 7 0 to 7 0 to 7 0 to 7 0 to 15 Function PMC0 Set to 1 when using compare match flag interrupt Set to 1 when using receive 0 error flag interrupt Set to 1 when using data 0 reception complete interrupt Set to 1 when using receive buffer full flag interrupt Set to 1 when using header 0 match flag interrupt Set to 1 when using data 0/1 0 match flag interrupt Set to 1 when using timer 0 measure interrupt Set to 1 when using special data match flag interrupt Select bits to be compared when using compare function Set to 1 when using compare function Set compare value when using compare function Set minimum value of header pattern or special data pattern Set maximum value of header pattern or special data pattern Set minimum value of data 0 pattern Set maximum value of data 0 pattern Set minimum value of data 1 pattern Set maximum value of data 1 pattern Measured value of pulse period or width can be read Counter value can be read Received data can be read - PMC1 PMCiCPD PMCiHDPMIN PMCiHDPMAX PMCiD0PMIN PMCiD0PMAX PMCiD1PMIN PMCiD1PMAX PMCiTIM Set minimum value of header pattern or special data pattern Set maximum value of header pattern or special data pattern 00h 00h 00h 00h Not used Not used - PMCiBC 0 to 15 PMCiDAT0 to 0 to 7 PMCiDAT5 PMC0RBIT 0 to 5 i = 0, 1 -: No register bit in PMC1 Received bit count can be read - REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 473 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.3.3.1 Setting Procedure To start or stop counting, follow procedures below: (1) Set the EN bit in the PMC0CON0 register to 1 (0 to stop). (2) Set the EN bit in the PMC1CON0 register to 1 (1 to stop). (3) Wait for two cycles of count source. (4) Confirm that the ENFLG bit in the PMC0CON2 register is 1 (0 to stop). (The ENFLG bit in the PMC1CON2 register is disabled) 22.3.3.2 Header and Special Data Detection Header and special data can be detected. Table 22.14 lists Selection of Header and Special Data Detecting Block. Table 22.14 Selection of Header and Special Data Detecting Block Bit Setting PMC0CON0 register PMC0CON1 register PMC0 PMC1 HDEN bit SDEN bit EXHDEN bit EXSDEN bit Header 1 0 1 0 Special data 0 1 0 1 Header Special data 1 1 0 1 Special data Header 1 1 1 0 -: Neither header nor special data is detected Note: 1. Do not set values not listed above. When header is valid, the following occur by detecting data 0, data 1, or special data prior to header. • The REFLG bit in the PMCiSTS register becomes 1 (error occurs). • Bits PTD0FLG, PTD1FLG, and SDFLG in the PMCiSTS register remain unchanged. • Registers PMCDAT0 to PMCDAT5 remain unchanged. Detected Item 22.3.3.3 Status Flag and Interrupt When connecting PMC0 and PMC1, use flags and interrupt control in PMC0. The object bits are as follows: Each bit in the PMC0STS register Each bit in the PMC0INT register INFLG bit in the PMC0CON2 register Even when detecting header or special data in PMC1, the result including those data can be detected in the above registers. 22.3.3.4 Receive Data Buffer (PMC0) There is a 6-byte (48-bit) buffer for storing received data. When the data exceeds 48 bits, the buffer is sequentially overwritten from the first bit. Refer to 22.2.12 “PMC0 Receive Data Store Register i (PMC0DATi) (i = 0 to 5)” and 22.2.11 “PMC0 Receive Bit Count Register (PMC0RBIT)”. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 474 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.3.3.5 Compare Function (PMC0) Contents of registers PMC0CPD and PMCDAT0 are compared. Reception of the specific data which is 1 to 8 bits can be detected. When using compare function, follow the instructions below: • The CPEN bit in the PMC0CPC register: 1 (compare enabled) • Select bits to be compared by bits CPN2 to CPN0 in the PMC0CPC register (when setting value is n, bits n to 0 are compared. n: 0 to 7) • Set the compare data in the PMC0CPD register The contents which have been compared are matched, the CPFLG bit in the PMC0STS register becomes 1 (compare match). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 475 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.3.4 Input Capture Mode (PMC0 and PMC1 Operate Individually) Input capture mode measures width or period of external pulse. PMC0 and PMC1 can be measured individually. Table 22.15 lists Specifications in Input Capture Mode (Individual Operation), Table 22.16 and Table 22.17 list registers and setting values in input capture mode (individual operation), and Figure 22.9 shows Difference of Operations in Receive Modes (Input Capture Mode). Table 22.15 Specifications in Input Capture Mode (Individual Operation) Item Count sources Clock sources Content PMC0 Circuit PMC1 Circuit One of the following: One of the following: • fC • fC • f1 • f1 • Timer B2 underflow • Timer B1 underflow • Count source of PMC1 • Timer B2 underflow No division, divided-by-8, divided-by-32, or divided-by-64 Increment One of the following: Pulse period (between rising edge and rising edge) Pulse period (between falling edge and falling edge) Pulse width (both high level and low level) • Timer measurement • Counter overflow • Input signal inversion • Digital filter Division Count operation Measurement items Interrupt request generation timing Selectable functions REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 476 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver Table 22.16 Registers and Setting Values in Input Capture Mode (Individual Operation) (1/2) Register PMCiCON0 Bit EN SINV FIL EHOLD HDEN SDEN DRINT0 DRINT1 TYP0 TYP1 CSS EXSDEN EXHDEN ENFLG INFLG CEFLG CEINT PSEL0 PSEL1 CRE CFR CST PD CSRC0 CSRC1 CDIV0 CDIV1 CPFLG REFLG DRFLG BFULFLG PTHDFLG PTD0FLG PTD1FLG SDFLG Function PMC0 1 Select input signal polarity Select filter enabled or disabled 0 0 0 00b Select measuring object 0 0 0 Flag indicating PMCi operated/ stopped Input signal flag Counter overflow flag Set to 1 when using counter overflow interrupt 01b 1 1 1 1 Select clock source Select count source divisor Not used (read as undefined value) Not used (read as undefined value) Not used (read as undefined value) Not used (read as undefined value) Not used (read as undefined value) Not used (read as undefined value) Not used (read as undefined value) Not used (read as undefined value) PMC1 1 Select input signal polarity Select filter enabled or disabled 0 Select measuring object Flag indicating PMCi operated/ stopped Input signal flag Counter overflow flag Set to 1 when using counter overflow interrupt 10b 1 1 1 1 Select clock source Select count source divisor Not used (read as undefined value) Not used (read as undefined value) Not used (read as undefined value) Not used (read as undefined value) Not used (read as undefined value) - PMCiCON1 PMCiCON2 PMCiCON3 PMCiSTS i = 0, 1 -: No register bits in PMC1 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 477 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver Table 22.17 Registers and Setting Values in Input Capture Mode (Individual Operation) (2/2) Register PMCiINT Bit CPINT REINT DRINT BFULINT PTHDINT PTDINT TIMINT SDINT CPN0 CPN1 CPN2 CPEN 0 to 7 0 to 10 0 to 10 0 to 7 0 to 7 0 to 7 0 to 7 0 to 15 Function PMC0 0 0 0 0 0 0 Set to 1 when using timer measure interrupt 0 000b PMC1 0 0 0 0 Set to 1 when using timer measure interrupt - PMCiCPC PMCiCPD PMCiHDPMIN PMCiHDPMAX PMCiD0PMIN PMCiD0PMAX PMCiD1PMIN PMCiD1PMAX PMCiTIM PMCiBC 0 to 15 PMCiDAT0 to 0 to 7 PMCiDAT5 PMC0RBIT 0 to 5 i = 0, 1 -: No register bit in PMC1 0 00h 0000h 0000h 00h 00h 00h 00h Measured value of pulse period or width can be read Counter value can be read Not used Not used 0000h 0000h 00h 00h 00h 00h Measured value of pulse period or width can be read Counter value can be read Not used Not used REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 478 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver PMCi internal input signal EN bit FFFFh Counter operation Count starts Counter value a b c d e f Bits TYP1 to TYP0 are 00b (period measurement (between rising edge and rising edge) PMCiTIM register b d f IR bit The bit becomes 0 when an interrupt request is accepted, or by setting the bit to 0. CEFLG bit Bits TYP1 to TYP0 are 01b (period measurement between falling edge and falling edge) PMCiTIM register a c e IR bit The bit becomes 0 when an interrupt request is accepted, or by setting the bit to 0. CEFLG bit Bits TYP1 to TYP0 are 10b (pulse width measurement) PMCiTIM register a b c d e f IR bit The bit becomes 0 when an interrupt request is accepted, or by setting the bit to 0. CEFLG bit i = 0, 1 The above diagram shows an instance in which the following condition is met: The TIMINT bit in the PMCiINT register is 1 (timer measure interrupt enabled) Figure 22.9 Difference of Operations in Receive Modes (Input Capture Mode) 22.3.4.1 Count Operation In input capture mode, the counter counts from 0000h to FFFFh, and then return to 0000h to continue counting. When the counter becomes 0000h after FFFFh, the CEFLG bit in the PMCiCON2 register becomes 1 (counter overflow) and holds 1 until the next measurement timing. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 479 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.3.5 Input Capture Mode (Simultaneous Count Operation of PMC0 and PMC1) Table 22.18 lists Specifications in Input Capture Mode (Simultaneous Count Operation) and Table 22.19 and Table 22.20 list registers and setting values in input capture mode (simultaneous count operation). Table 22.18 Specifications in Input Capture Mode (Simultaneous Count Operation) Item Count sources Clock sources Content PMC0 Circuit Count source of PMC1 PMC1 Circuit One of the following: • fC • f1 • Timer B1 underflow • Timer B2 underflow No division, divided-by-8, dividedby-32, or divided-by-64 Division Count operation Measurement items No division Interrupt request generation timing Selectable functions Increment One of the following: Pulse period (between rising edge and rising edge) Pulse period (between falling edge and falling edge) Pulse width (both high level and low level) • Timer measurement • Counter overflow • Input signal inversion • Digital filter REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 480 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver Table 22.19 Registers and Setting Values in Input Capture Mode (Simultaneous Count Operation) (1/2) Register PMCiCON0 EN Bit Function PMC0 1. (Refer to 22.3.5.1 “Setting Procedure”) Select input signal polarity Select filter enabled/disabled 0 0 0 00b Select measuring object 1 0 0 Flag indicating PMCi operated/ stopped Input signal flag Counter overflow flag Set to 1 when using counter overflow interrupt 01b 1 1 1 1 00b 00b Not used (read as undefined value) Not used (read as undefined value) Not used (read as undefined value) Not used (read as undefined value) Not used (read as undefined value) Not used (read as undefined value) Not used (read as undefined value) Not used (read as undefined value) PMC1 1. (Refer to 22.3.5.1 “Setting Procedure”) Select input signal polarity Select filter enabled/disabled 0 Select measuring object Flag indicating PMCi operated/ stopped Input signal flag Counter overflow flag Set to 1 when using counter overflow interrupt 10b 1 1 1 1 Select clock source Select count source divisor Not used (read as undefined value) Not used (read as undefined value) Not used (read as undefined value) Not used (read as undefined value) Not used (read as undefined value) - PMCiCON1 PMCiCON2 SINV FIL EHOLD HDEN SDEN DRINT0 DRINT1 TYP0 TYP1 CSS EXSDEN EXHDEN ENFLG INFLG CEFLG CEINT PSEL0 PSEL1 CRE CFR CST PD CSRC0 CSRC1 CDIV0 CDIV1 CPFLG REFLG DRFLG BFULFLG PTHDFLG PTD0FLG PTD1FLG SDFLG PMCiCON3 PMCiSTS i = 0, 1 -: No register bit in PMC1 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 481 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver Table 22.20 Registers and Setting Values in Input Capture Mode (Simultaneous Count Operation) (2/2) Register PMCiINT Bit CPINT REINT DRINT BFULINT PTHDINT PTDINT TIMINT SDINT CPN0 CPN1 CPN2 CPEN 0 to 7 0 to 10 0 to 10 0 to 7 0 to 7 0 to 7 0 to 7 0 to 15 Function PMC0 0 0 0 0 0 0 Set to 1 when using timer measure interrupt 0 000b PMC1 0 0 0 0 Set to 1 when using timer measure interrupt - PMCiCPC PMCiCPD PMCiHDPMIN PMCiHDPMAX PMCiD0PMIN PMCiD0PMAX PMCiD1PMIN PMCiD1PMAX PMCiTIM PMCiBC 0 to 15 PMCiDAT0 to 0 to 7 PMCiDAT5 PMC0RBIT 0 to 5 i = 0, 1 -: No register bit in PMC1 0 00h 0000h 0000h 00h 00h 00h 00h Measured value of pulse period or width can be read Counter value can be read Not used Not used 0000h 0000h 00h 00h 00h 00h Measured value of pulse period or width can be read Counter value can be read Not used Not used 22.3.5.1 Setting Procedure To start or stop counting, follow procedures below: (1) Set the EN bit in the PMC0CON0 register to 1 (0 to stop). (2) Set the EN bit in the PMC1CON0 register to 1 (1 to stop). (3) Wait for two cycles of count source. (4) Confirm that the ENFLG bit in the PMC0CON2 register is 1 (0 to stop). (The ENFLG bit in the PMC1CON2 register is disabled) 22.3.5.2 Count Operation In input capture mode, the counter counts from 0000h to FFFFh, and then return to 0000h to continue counting. When the counter becomes 0000h after FFFFh, the CEFLG bit in the PMCiCON2 register becomes 1 (counter overflow) and holds 1. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 482 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.4 Interrupt The remote control signal receiver has remote control signal receiver 0 interrupt and remote control signal receiver 1 interrupt. The remote control signal receiver 0 interrupt and remote control signal receiver 1 interrupt are interrupts in PMC0 and PMC1 respectively. A remote control signal receiver i interrupt request signal is generated every time the conditions are met. If the interrupt enable bit in the PMCiCON2 or PMCiINT register is 1, the IR bit in the PMCiIC register becomes 1 (interrupt request) when the corresponding interrupt request signal is generated. Table 22.21 lists Interrupt Source of Remote Control Signal Receiver i Interrupt (i = 0, 1). Table 22.21 Interrupt Source of Remote Control Signal Receiver i Interrupt (i = 0, 1) Mode Pattern match mode Interrupt Source Completion of data reception Interrupt Request Generating Condition Counter value is larger than values of registers PMCiHDPMAX, PMCiD0PMAX, and PMCiD1PMAX Header match The measured result is within the range set by registers PMCiHDPMIN and PMCiHDPMAX (when header is enabled) Data 0/1 match The measured result is within the range set by registers PMCiD0PMIN and PMCiD0PMAX or registers PMCiD1PMIN and PMCiD1PMAX Special data match The measured result is within the range set by registers PMCiHDPMIN and PMCiHDPMAX (when special data is enabled) Receive error Input signal width is none of header, data 0, data 1, and special data Data 0 or data 1 is detected before detecting header when the HDEN bit is 1 Receive buffer full The value of the PMC0RBIT register is 48 Compare match The values of registers PMC0CPD and PMC0DAT0 are matched (only bits selected by the CPN bit in the PMC0CPC register are compared) Timer measurement Measurement end edge of PMCi internal input signal Input Timer measurement Measurement end edge of PMCi internal input capture signal mode Counter overflow Counter overflow (counter value exceeds FFFFh and becomes 0000h) Measured result: Content of the PMCiTIM register Interrupt enable bit Register Bit PMCiINT DRINT PMCiINT PTHDINT PMCiINT PTDINT PMC0INT SDINT PMCiINT REINT PMC0INT PMC0INT BFULINT CPINT PMCiINT PMCiINT TIMINT TIMINT PMCiCON2 CEINT REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 483 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group Figure 22.10 shows Interrupt of Remote Control Signal Receiver. 22. Remote Control Signal Receiver CPINT DRINT1 to DRINT0 DRINT Compare match interrupt request REINT Receive error interrupt request 00b 01b 10b 11b Data reception complete interrupt request BFULINT Receive buffer full interrupt request PTHDINT Header pattern match interrupt request PTDINT Data 0/1 pattern match interrupt request TIMINT Timer measure interrupt request SDINT Special pattern match interrupt request PMC0 interrupt (IR bit in the PMC0IC register) CEINT Counter overflow interrupt request REINT Receive error interrupt request DRINT Data reception complete interrupt request PTHDINT Header pattern match interrupt request PTDINT Data 0/1 pattern match interrupt request TIMINT Timer measure interrupt request PMC1 interrupt (IR bit in the PMC1IC register) CEINT Counter overflow interrupt request Figure 22.10 Interrupt of Remote Control Signal Receiver REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 484 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver Refer to 14.7 “Interrupt Control” for details of interrupt control. Table 22.22 lists Registers Associated with Interrupt of Remote Control Signal Receiver. Table 22.22 Registers Associated with Interrupt of Remote Control Signal Receiver Address 0071h 0072h 0206h Register Name UART7 Bus Collision Detection Interrupt Control Register Remote Control Signal Receiver 0 Interrupt Control Register UART7 Transmit Interrupt Control Register Remote Control Signal Receiver 1 Interrupt Control Register Interrupt Source Select Register 2 Register Symbol After Reset U7BCNIC/ XXXX X000b PMC0IC S7TIC/PMC1IC IFSR2A XXXX X000b 00h The remote control signal receiver shares interrupt vectors or interrupt control registers with other peripheral functions. To use remote control signal receiver 0 interrupt, set the IFSR24 bit in the IFSR2A register to 1 (remote control signal receiver 0). To use remote control signal receiver 1 interrupt, set the IFSR25 bit in the IFSR2A register to 1 (remote control signal receiver 1). The IR bit in registers PMC0IC and PMC1IC is different from another IR bit in the following respects: •If the interrupt enable bit in the PMCiCON2 or PMCiINT register is 1, the IR bit in the PMCiIC register becomes 1 (interrupt request) when the corresponding interrupt request signal is generated. • If multiple interrupts are enabled, IR bit becomes 1 and then remains 1 when another request source is generated. • The IR bit does not become 0 automatically when the interrupt is accepted. Set the IR bit to 0 within interrupt routine. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 485 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 22. Remote Control Signal Receiver 22.5 22.5.1 Notes on Remote Control Signal Receiver Start/Stop of PMCi The EN bit in the PMCiCON0 register controls start/stop of PMCi. The ENFLG bit in the PMCiCON2 register indicates that the operation starts or stops. The PMCi circuit starts operating by setting the EN bit to 1 (operation starts) and the ENFLG bit becomes 1. It takes up to two cycles of the count source until the ENFLG bit becomes 1 after setting the EN bit to 1. During this period, do not access registers associated with PMCi (registers listed in Table 22.3 and Table 22.4 “register structure (PMCi circuit)”) excluding the ENFLG bit. When the EN bit is set to 0 (operation stops), PMCi circuit stops operating and the ENFLG bit becomes 0 (operation stops). It takes up to one cycle of the count source until the ENFLG bit becomes 0 after setting the EN bit to 0. 22.5.2 Register Reading Procedure If reading the following registers when the data changes, undefined value may be read. Each flag in registers PMCiCON2 and PMCiSTS Registers PMCiTIM, PMC0DAT0 to PMC0DAT5, PMCiBC, and PMC0RBIT Read above registers as follows to avoid reading the undefined value. In pattern match mode • Using interrupt Set the DRINT bit in the PMCiINT register to 1 (data reception complete interrupt enabled) and read the registers within PMCi interrupt routine. • Monitoring by a program 1 Set the DRINT bit in the PMCiINT register to 1 (data reception complete interrupt enabled) and monitor the IR bit in the PMCiIC register by a program. Read the registers when the IR bit becomes 1 (interrupt request is generated). • Monitoring by a program 2 (1) Monitor the DRFLG bit in the PMCiSTS register (2) When the DRFLG bit becomes 1, monitor the DRFLG bit until it becomes 0. (3) Read the necessary content of the registers when the DRFLG bit becomes 0. In input capture mode • Using interrupt Set the TIMINT bit in the PMCiINT register to 1 (timer measure interrupt enabled) and read the registers within PMCi interrupt routine. • Monitoring by a program 1 Set the TIMINT bit in the PMCiINT register to 1 (timer measure interrupt enabled) and monitor the IR bit in the PMCiIC register by a program. Read the registers when the IR bit becomes 1 (interrupt request is generated). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 486 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Note The 80-pin package does not have pins CLK2 and CTS2/RTS2 for UART2. Do not use functions associated with these pins. UART6 and UART7 are not included. 23.1 Introduction Each UARTi has a dedicated timer to generate a transmit/receive clock, so it operates independently of the others. Table 23.1 lists Specifications of UARTi (i = 0 to 2, 5 to 7), Table 23.2 lists Specification Difference in UART0 to UART2 and UART5 to UART7, Figure 23.1 to Figure 23.3 show UARTi Block Diagram, and Figure 23.4 shows UARTi Transmit/Receive Unit Block Diagram. Table 23.1 Specifications of UARTi (i = 0 to 2, 5 to 7) Item Operational mode Specification • Clock synchronous serial I/O mode • Clock asynchronous serial I/O mode (UART mode) • Special mode 1 (I2C mode) • Special mode 2 The simplified I2C-bus interface is supported. • Special mode 3 (bus collision detection function, IE mode) A 1-byte wave of the UART mode approximates 1-bit of the IEBus. • Special mode 4 (SIM mode) UART2 is available. The SIM interface is supported. Table 23.2 Specification Difference in UART0 to UART2 and UART5 to UART7 Mode UART0 UART1 UART2 Clock synchronous serial I/O mode Available Available Clock asynchronous serial I/O mode Available Available (UART mode) Available Available Special mode 1 (I2C mode) Special mode 2 Special mode 3 (IE mode) Special mode 4 (SIM mode) Memory expansion mode or microprocessor mode Available Available Not available Can be used Available Available Available UART5 Available Available Available Available Available Not available UART6 UART7 Available Available Available Available Available Not available Do not use. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 487 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) OCOSEL0 f1 fOCO-F 1/2 f2SIO f1SIO PCLK1 0 1 f1SIO or f2SIO f8SIO 1/4 f32SIO 1/8 RXD0 RXD polarity switching circuit 1/16 UART reception SMD2 to SMD0 010, 100, 101, 110 Clock sync type 001 Clock source selection CLK1 to CLK0 CKDIR f1SIO or 00 Internal f2SIO 01 0 f8SIO 10 f32SIO 1 External Reception control circuit Receive clock TXD polarity switching circuit TXD0 Transmit/ receive unit U0BRG register 1/(n+1) 1/16 UART transmission 1/2 Transmission 010, 100, 101, 110 control circuit Clock sync type 001 Clock synchronous type (when internal clock is selected) 0 Transmit clock CKPOL CLK0 CLK polarity reversing circuit 1 Clock synchronous type (when external clock is selected) CKDIR Clock synchronous type (when internal clock is selected) CTS/RTS disabled CTS/RTS selected CTS0/ RTS0 RTS0 0 1 RCSP 0 1 VSS CTS/RTS disabled 1 CRS 0 CTS0 from UART1 CTS0 CRD n: Value set to the U0BRG register PCLK1 : Bit in the PCLKR register SMD2 to SMD0, CKDIR : Bits in the U0MR register CLK1 to CLK0, CKPOL, CRD, CRS : Bits in the U0C0 register RCSP : Bit in the UCON register OCOSEL0 : Bit in the UCLKSEL0 register Figure 23.1 UART0 Block Diagram REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 488 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) PCLK1 OCOSEL0 f1 fOCO-F 1/8 1/4 f8SIO f32SIO TXD polarity switching circuit 1/2 f2SIO f1SIO 0 1 f1SIO or f2SIO TXD1 RXD1 RXD polarity switching circuit 1/16 UART reception SMD2 to SMD0 010, 100, 101, 110 Clock sync type 001 Clock source selection f1SIO or f2SIO f8SIO f32SIO CLK1 to CLK0 CKDIR 00 Internal 01 0 10 1 External Reception control circuit Receive clock Transmit/ receive unit U1BRG register 1/(n+1) 1/16 UART transmission 010, 100, 101, 110 Clock sync type 001 Clock synchronous type (when internal clock is selected) 0 1 CKDIR Transmission control circuit Transmit clock 1/2 Clock synchronous type (when external clock is selected) CKPOL CLK1 CLK polarity reversing circuit 0 CLKMD0 Clock synchronous type (when internal clock is selected) 1 CTS1/RTS1/ CTS0/CLKS1 Clock output pin select 1 CTS/RTS selected CRS 1 0 CTS/RTS disabled RTS1 CTS/RTS disabled CLKMD1 0 0 0 1 CTS1 to CTS0 in UART0 VSS 1 CRD RCSP n: Value set to the U1BRG register PCLK1 : Bit in the PCLKR register SMD2 to SMD0, CKDIR : Bits in the U1MR register CLK1 to CLK0, CKPOL, CRD, CRS : Bits in the U1C0 register CLKMD0, CLKMD1, RCSP : Bits in the UCON register OCOSEL0 : Bit in the UCLKSEL0 register Figure 23.2 UART1 Block Diagram REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 489 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) OCOSEL0 or OCOSEL1 f1 fOCO-F 1/2 f2SIO f1SIO PCLK1 0 1 f1SIO or f2SIO f8SIO 1/4 f32SIO 1/8 RXDi RXD polarity switching circuit 1/16 UART reception SMD2 to SMD0 010, 100, 101, 110 Clock sync type 001 Clock source selection f1SIO or f2SIO f8SIO f32SIO CLK1 to CLK0 CKDIR 00 Internal 01 0 10 1 External Reception control circuit Receive clock Transmit/ receive unit TXD polarity switching circuit (1) TXDi UiBRG register 1/(n+1) UART transmission 1/16 010, 100, 101, 110 Clock sync type 001 Clock synchronous type (when internal clock is selected) 0 Transmission control circuit Transmit clock 1/2 CKPOL 1 Clock synchronous type (when external clock is selected) CKDIR Clock synchronous type (when internal clock is selected) CLKi CLK polarity reversing circuit CTS/RTS disabled CTS/RTS selected RTSi 0 1 VSS CRD CTS/RTS disabled CTSi/ RTSi 1 CRS 0 CTSi n: Value set to the UiBRG register i = 2, 5 to 7 PCLK1 : Bit in the PCLKR register SMD2 to SMD0, CKDIR : Bits in the UiMR register CLK1 to CLK0, CKPOL, CRD, CRS : Bits in the UiC0 register OCOSEL1, OCOSEL0 : Bits in the UCLKSEL0 register Note : 1. UART2 is an N-channel open-drain output. CMOS output cannot be selected. Figure 23.3 Block Diagram of UART2, and UART5 to UART7 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 490 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) IOPOL RXDi RXD data reverse circuit No reverse 0 1 Reverse STPS 1SP 0 SP 1 2SP SP PAR PRYE PAR disabled I2C clock sync type 0 1 SMD2 to SMD0 Clock sync type UART (7 bits) UART (8 bits) 0 0 UART (7 bits) 0 UARTi receive register PAR enabled UART 1 UART (9 bits) 1 I2C I2C 1 clock sync type UART (8 bits) UART (9 bits) 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UiRB register Logic reverse circuit + MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits Logic reverse circuit + MSB / LSB conversion circuit D8 D7 UART (8 bits) UART (9 bits) D6 D5 D4 D3 D2 D1 D0 UiTB register I2C STPS 2SP 1 SP SP 0 1SP PAR I2C clock sync type PRYE PAR enabled SMD2 to SMD0 UART UART (9 bits) 1 1 0 I2C clock sync type 1 1 0 PAR disabled 0 UART (7 bits) UART (8 bits) Clock sync type 0 UART (7 bits) UARTi transmit register Error signal output disabled SP : Stop bit PAR: Parity bit i = 0 to 2, 5 to 7 0 Error signal output circuit IOPOL 0 No reverse TXDi UiERE 1 Reverse 1 TXD data reverse circuit Error signal output enabled SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR : Bits in the UiMR register CLK1 to CLK0, CKPOL, CRD, CRS : Bits in the UiC0 register UiERE : Bit in the UiC1 register Figure 23.4 UARTi Transmit/Receive Unit Block Diagram REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 491 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2 Registers Table 23.3 and Table 23.4 list registers associated with UART0 to UART2 and UART5 to UART7. Set the OCOSEL0 or OCOSEL1 bit in the UCLKSEL0 register before setting other registers associated with UART0 to UART2 and UART5 to UART7. After changing the OCOSEL0 or OCOSEL1 bit, set other registers associated with UART0 to UART2 and UART5 to UART7 again. Refer to “Registers Used and Settings” in each mode for the settings of registers and bits. Table 23.3 Register Structure (1/2) Address 0012h 0244h 0245h 0246h 0247h 0248h 0249h 024Ah 024Bh 024Ch 024Dh 024Eh 024Fh 0250h 0252h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0264h 0265h 0266h 0267h 0268h 0269h 026Ah 026Bh 026Ch 026Dh 026Eh 026Fh 0284h 0285h Register Name Peripheral Clock Select Register UART0 Special Mode Register 4 UART0 Special Mode Register 3 UART0 Special Mode Register 2 UART0 Special Mode Register UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register UART Transmit/Receive Control Register 2 UART Clock Select Register UART1 Special Mode Register 4 UART1 Special Mode Register 3 UART1 Special Mode Register 2 UART1 Special Mode Register UART1 Transmit/Receive Mode Register UART1 Bit Rate Register UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register UART2 Transmit/Receive Mode Register UART2 Bit Rate Register UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register UART5 Special Mode Register 4 UART5 Special Mode Register 3 Register Symbol PCLKR U0SMR4 U0SMR3 U0SMR2 U0SMR U0MR U0BRG U0TB U0C0 U0C1 U0RB UCON UCLKSEL0 U1SMR4 U1SMR3 U1SMR2 U1SMR U1MR U1BRG U1TB U1C0 U1C1 U1RB U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB U5SMR4 U5SMR3 After Reset 0000 0011b 00h 000X 0X0Xb X000 0000b X000 0000b 00h XXh XXh XXh 0000 1000b 00XX 0010b XXh XXh X000 0000b X0h 00h 000X 0X0Xb X000 0000b X000 0000b 00h XXh XXh XXh 0000 1000b 00XX 0010b XXh XXh 00h 000X 0X0Xb X000 0000b X000 0000b 00h XXh XXh XXh 0000 1000b 0000 0010b XXh XXh 00h 000X 0X0Xb REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 492 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Table 23.4 Register Structure (2/2) Address 0286h 0287h 0288h 0289h 028Ah 028Bh 028Ch 028Dh 028Eh 028Fh 0294h 0295h 0296h 0297h 0298h 0299h 029Ah 029Bh 029Ch 029Dh 029Eh 029Fh 02A4h 02A5h 02A6h 02A7h 02A8h 02A9h 02AAh 02ABh 02ACh 02ADh 02AEh 02AFh Register Name UART5 Special Mode Register 2 UART5 Special Mode Register UART5 Transmit/Receive Mode Register UART5 Bit Rate Register UART5 Transmit Buffer Register UART5 Transmit/Receive Control Register 0 UART5 Transmit/Receive Control Register 1 UART5 Receive Buffer Register UART6 Special Mode Register 4 UART6 Special Mode Register 3 UART6 Special Mode Register 2 UART6 Special Mode Register UART6 Transmit/Receive Mode Register UART6 Bit Rate Register UART6 Transmit Buffer Register UART6 Transmit/Receive Control Register 0 UART6 Transmit/Receive Control Register 1 UART6 Receive Buffer Register UART7 Special Mode Register 4 UART7 Special Mode Register 3 UART7 Special Mode Register 2 UART7 Special Mode Register UART7 Transmit/Receive Mode Register UART7 Bit Rate Register UART7 Transmit Buffer Register UART7 Transmit/Receive Control Register 0 UART7 Transmit/Receive Control Register 1 UART7 Receive Buffer Register Register Symbol U5SMR2 U5SMR U5MR U5BRG U5TB U5C0 U5C1 U5RB U6SMR4 U6SMR3 U6SMR2 U6SMR U6MR U6BRG U6TB U6C0 U6C1 U6RB U7SMR4 U7SMR3 U7SMR2 U7SMR U7MR U7BRG U7TB U7C0 U7C1 U7RB After Reset X000 0000b X000 0000b 00h XXh XXh XXh 0000 1000b 0000 0010b XXh XXh 00h 000X 0X0Xb X000 0000b X000 0000b 00h XXh XXh XXh 0000 1000b 0000 0010b XXh XXh 00h 000X 0X0Xb X000 0000b X000 0000b 00h XXh XXh XXh 0000 1000b 0000 0010b XXh XXh REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 493 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2.1 UART Clock Select Register (UCLKSEL0) UART Clock Select Register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol UCLKSEL0 Bit Symbol — (b1-b0) OCOSEL0 Bit Name Reserved bits Address 0252h Function Set to 0 0 : f1 1 : fOCO-F 0 : f1 1 : fOCO-F After Reset X0h RW RW Clock select prior to UART0 to UART2 division bit Clock select prior to UART5 to UART7 division bit RW OCOSEL1 — (b7-b4) RW No register bits. If necessary, set to 0. Read as undefined value — OCOSEL0 (Clock Select Prior to UART0 to UART2 Division Bit) (b2) OCOSEL1 (Clock Select Prior to UART5 to UART 7 Division Bit) (b3) Set bits OCOSEL0 and OCOSEL1 while transmission/reception of UART0 to UART2 and UART5 to UART7 stops. Set the OCOSEL0 or OCOSEL1 bit before setting other registers associated with UART0 to UART2 and UART5 to UART7. After changing the OCOSEL0 or OCOSEL1 bit, set other registers associated with UART0 to UART2 and UART5 to UART7 again. 23.2.2 Peripheral Clock Select Register (PCLKR) Peripheral Clock Select Register b7 b6 b5 b4 b3 b2 b1 b0 00 000 Symbol PCLKR Bit Symbol Bit Name Address 0012h Function After Reset 0000 0011b RW PCLK0 Timers A and B clock select bit (clock source for timers A and B, the dead time timer, and muliti-master I2C-bus interface) SI/O clock select bit (clock source for UART0 to UART2, UART5 to UART7, SI/O3, and SI/O4) Reserved bits Clock output function extension bit (valid in single-chip mode) Reserved bits 0: f2TIMAB/f2IIC 1: f1TIMAB/f1IIC RW PCLK1 0: f2SIO 1: f1SIO RW — (b4-b2) PCLK5 — (b7-b6) Set to 0 0: Selected by bits CM01 to CM00 in the CM0 register 1: Output f1 Set to 0 RW RW RW Set the PRC0 bit in the PRCR register to 1 (write enabled) before the PCLKR register is rewritten. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 494 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2.3 UARTi Transmit Buffer Register (UiTB) (i = 0 to 2, 5 to 7) UARTi Transmit Buffer Register (i = 0 to 2, 5 to 7) (b15) b7 (b8) b0 b7 b0 Symbol U0TB U1TB U2TB U5TB U6TB U7TB Address 024Bh to 024Ah 025Bh to 025Ah 026Bh to 026Ah 028Bh to 028Ah 029Bh to 029Ah 02ABh to 02AAh Function After Reset Undefined Undefined Undefined Undefined Undefined Undefined RW WO Transmit data No register bits. If necessary, set to 0. Read as undefined value — Use MOV instruction to write to this register. When character bit is 9 bits long, write in 16-bit units, or write in 8-bit units in the order of high-order bytes to low-order bytes. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 495 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2.4 UARTi Receive Buffer Register (UiRB) (i = 0 to 2, 5 to 7) UARTi Receive Buffer Register (i = 0 to 2, 5 to 7) (b15) b7 (b8) b0 b7 b0 Symbol U0RB U1RB U2RB U5RB U6RB U7RB Bit Symbol — (b7-b0) — (b8) — (b10-b9) ABT Bit Name Address 024Fh to 024Eh 025Fh to 025Eh 026Fh to 026Eh 028Fh to 028Eh 029Fh to 029Eh 02AFh to 02AEh Function Receive data (D7 to D0) After Reset Undefined Undefined Undefined Undefined Undefined Undefined RW RO Receive data (D8) RO No register bits. If necessary, set to 0. Read as undefined value 0 : Not detected 1 : Detected 0 : No overrun error 1 : Overrun error found 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found — Arbitration lost detect flag RW OER Overrun error flag RO FER Framing error flag RO PER Parity error flag RO SUM Error sum flag RO When bits SMD2 to SMD0 in the UiMR register is 100b, 101b or 110b, read in 16-bit units, or read in 8bit units in the order of high-order bytes to low-order bytes. Bits FER and PER arranged in the high-order bytes become 0 when the lower bytes of the UiRB register are read. If an overrun error occurs, the receive data of the UiRB register will be undefined. ABT (Arbitration Lost Detect Flag) (b11) The ABT bit is set to 0 by a program. (It remains unchanged even if 1 is written.) OER (Overrun Error Flag) (b12) Condition to become 0: • Bits SMD2 to SMD0 in the UiMR register are 000b (serial interface disabled). • The RE bit in the UiC1 register is 0 (reception disabled). Condition to become 1: • The RI bit in the UiC1 register is 1 (data present in UiRB register), and the last bit of the next data is received. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 496 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) FER (Framing Error Flag) (b13) The FER bit is disabled when bits SMD2 to SMD0 are set to 001b (clock synchronous serial I/O mode) or to 010b (I2C mode). Read as undefined value. Condition to become 0: • Bits SMD2 to SMD0 in the UiMR register are 000b (serial interface disabled). • The RE bit in the UiC1 register is 0 (reception disabled). • The lower bytes of the UiRB register are read. Condition to become 1: • The set number of stop bits is not detected. (detected when the received data is transferred from the UARTi receive register to the UiRB register.) PER (Parity Error Flag) (b14) The PER bit is disabled when bits SMD2 to SMD0 are set to 001b (clock synchronous serial I/O mode) or to 010b (I2C mode). Read as undefined value. Condition to become 0: • Bits SMD2 to SMD0 in the UiMR register are 000b (serial interface disabled). • The RE bit in the UiC1 register is 0 (reception disabled). • The lower bytes of the UiRB register are read. Condition to become 1: • The number of 1s of the parity bit and character bit does not match the set value of the PRY bit in the UiMR register. (detected when the received data is transferred from the UARTi receive register to the UiRB register.) SUM (Error Sum Flag) (b15) The SUM bit is disabled when bits SMD2 to SMD0 are set to 001b (clock synchronous serial I/O mode) or to 010b (I2C mode). Read as undefined value. Condition to become 0: • Bits SMD2 to SMD0 in the UiMR register are 000b (serial interface disabled). • The RE bit in the UiC1 register is 0 (reception disabled). • All of bits PER, FER and OER are 0 (no error). Condition to become 1: • More than one of bits PER, FER or OER is 1 (error found). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 497 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2.5 UARTi Bit Rate Register (UiBRG) (i = 0 to 2, 5 to 7) UARTi Bit Rate Register (i = 0 to 2, 5 to 7) b7 b0 Symbol U0BRG, U1BRG, U2BRG U5BRG, U6BRG, U7BRG Function Address 0249h, 0259h, 0269h 0289h, 0299h, 02A9h After Reset Undefined Undefined Setting Range 00h to FFh RW WO If set value is n, UiBRG divides the count source by n + 1 Write to the UiBRG register while serial interface is neither transmitting nor receiving. Use MOV instruction to write to the UiBRG register. Write to the UiBRG register after setting bits CLK1 to CLK0 in the UiC0 register. 23.2.6 UARTi Transmit/Receive Mode Register (UiMR) (i = 0 to 2, 5 to 7) UARTi Transmit/Receive Mode Register (i = 0 to 2, 5 to 7) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0MR, U1MR, U2MR U5MR, U6MR, U7MR Bit Symbol SMD0 Bit Name Address 0248h, 0258h, 0268h 0288h, 0298h, 02A8h Function b2 b1 b0 After Reset 00h 00h RW RW SMD1 SMD2 0 0 0 : Serial interface disabled 0 0 1 : Clock synchronous serial I/O mode 0 1 0 : I2C mode Serial I/O mode select bit 1 0 0 : UART mode character bit length is 7 bits 1 0 1 : UART mode character bit length is 8 bits 1 1 0 : UART mode character bit length is 9 bits Do not set values other than the above Internal/external clock select bit Stop bit length select bit 0 : Internal clock 1 : External clock 0 : 1 stop bit 1 : 2 stop bits RW RW CKDIR RW STPS RW PRY Valid when PRYE is 1 Odd/even parity select bit 0 : Odd parity 1 : Even parity Parity enable bit TXD, RXD I/O polarity reverse bit 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse RW PRYE RW IOPOL RW REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 498 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2.7 UARTi Transmit/Receive Control Register 0 (UiC0) (i = 0 to 2, 5 to 7) UARTi Transmit/Receive Control Register 0 (i = 0 to 2, 5 to 7) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0C0, U1C0, U2C0 U5C0, U6C0, U7C0 Bit Symbol CLK0 Bit Name Address 024Ch, 025Ch, 026Ch 028Ch, 029Ch, 02ACh Function b1 b0 After Reset 0000 1000b 0000 1000b RW RW UiBRG count source select bit CLK1 0 0 1 1 0 : f1SIO or f2SIO selected 1 : f8SIO selected 0 : f32SIO selected 1 : Do not set RW CRS CTS/RTS function select bit Valid when CRD is 0 0 : CTS function selected 1 : RTS function selected 0 : Data present in transmit register (transmission in progress) 1 : No data present in transmit register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled 0 : Pins TXDi/SDAi and SCLi are CMOS output 1 : Pins TXDi/SDAi and SCLi are N-channel open-drain output 0 : Transmit data is output at the falling edge of transmit/receive clock and receive data is input at the rising edge 1 : Transmit data is output at the rising edge of transmit/receive clock and receive data is input at the falling edge 0 : LSB first 1 : MSB first RW TXEPT Transmit register empty flag RO CRD CTS/RTS disable bit RW NCH Data output select bit RW CKPOL CLK polarity select bit RW UFORM Bit order select bit RW CLK1 to CLK0 (UiBRG Count Source Select Bit) (b1-b0) When bits CLK1 to CLK0 are 00b (f1SIO or f2SIO selected), select f1SIO or f2SIO by the PCLK1 bit in the PCLKR register. Set bits CLK1 to CLK0 after setting registers UCLKSEL0 and PCLKR. If bits CLK1 to CLK0 are changed, set the UiBRG register. CRS (CTS/RTS Function Select Bit) (b2) CTS1/RTS1 can be used when the CLKMD1 bit in the UCON register is 0 (CLK output is only from CLK1) and the RCSP bit in the UCON register is 0 (CTS0/RTS0 not separated). CRD (CTS/RTS Disable Bit) (b4) When the CRD bit is 1 (CTS/RTS function disabled), the CTSi/RTSi pin can be used as an input/output port. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 499 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) NCH (Data Output Select Bit) (b5) TXD2/SDA2 and SCL2 are N-channel open-drain outputs. They cannot be set to CMOS output. Nothing is assigned in the NCH bit in the U2C0 register. If necessary, set to 0. This function is used to set P-channel transistor of the COMS output buffer always off, but not to change pins TXDi/SDAi and SCLi to open-drain output completely. Check electrical characteristics for the input voltage range. UFORM (Bit Order Select Bit) (b7) The UFORM bit is enabled when bits SMD2 to SMD0 in the UiMR register are 001b (clock synchronous serial I/O mode), or 101b (UART mode, 8-bit character data). Set the UFORM bit to 1 when bits SMD2 to SMD0 are 010b (I2C mode), and to 0 when bits SMD2 to SMD0 are 100b (UART mode, 7-bit character data) or 110b (UART mode, 9-bit character data). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 500 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2.8 UARTi Transmit/Receive Control Register 1 (UiC1) (i = 0 to 2, 5 to 7) UARTi Transmit/Receive Control Register 1 (i = 0, 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0C1, U1C1 Bit Symbol TE Bit Name Transmit enable bit Address 024Dh, 025Dh Function 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in UiTB register 1 : No data present in UiTB register 0 : Reception disabled 1 : Reception enabled 0 : No data present in UiRB register 1 : Data present in UiRB register After Reset 00XX 0010b RW RW TI Transmit buffer empty flag RO RE Receive enable bit RW RI — (b5-b4) UiLCH Receive complete flag RO No register bits. If necessary, set to 0. Read as undefined value 0 : No reverse 1 : Reverse 0 : Output disabled 1 : Output enabled — Data logic select bit RW UiERE Error signal output enable bit RW UARTi Transmit/Receive Control Register 1 (i = 2, 5 to 7) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2C1 U5C1, U6C1, U7C1 Bit symbol TE Bit Name Transmit enable bit Address 026Dh 028Dh, 029Dh, 02ADh Function 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in UiTB register 1 : No data present in UiTB register 0 : Reception disabled 1 : Reception enabled 0 : No data present in UiRB register 1 : Data present in UiRB register 0 : UiTB register empty (TI = 1) 1 : Transmit completed (TXEPT = 1) After Reset 0000 0010b 0000 0010b RW RW TI Transmit buffer empty flag RO RE Receive enable bit RW RI Receive complete flag UARTi transmit interrupt source select bit UARTi continuous receive mode enable bit Data logic select bit RO UilRS RW UiRRM 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled 0 : No reverse 1 : Reverse 0 : Output disabled 1 : Output enabled RW UiLCH RW UiERE Error signal output enable bit RW Bits UiIRS and UiRRM of UART0 and UART1 are bits in the UCON register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 501 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) UiLCH (Data Logic Select Bit) (b6) The UiLCH bit enabled when bits SMD2 to SMD0 in the UiMR register are 001b (clock synchronous serial I/O mode), 100b (UART mode, 7-bit character data), or 101b (UART mode, 8-bit character data). Set this bit to 0 when bits SMD2 to SMD0 are set to 010b (I2C mode) or 110b (UART mode, 9-bit character data). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 502 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2.9 UART Transmit/Receive Control Register 2 (UCON) UART Transmit/Receive Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UCON Bit symbol U0IRS Bit Name Address 0250h Function After Reset X000 0000b RW RW UART0 transmit interrupt source select bit UART1 transmit interrupt source select bit UART0 continuous receive mode enable bit UART1 continuous receive mode enable bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled U1IRS RW U0RRM RW U1RRM RW CLKMD0 Valid when CLKMD1 is 1 UART1CLK, CLKS select bit 0 0 : Clock output from CLK1 1 : Clock output from CLKS1 0 : CLK output is only from CLK1 UART1CLK, CLKS select bit 1 1 : Transmit/receive clock output from multiple-pin output function selected Separate UART0 CTS/RTS bit 0 : CTS/RTS shared pin 1 : CTS/RTS separated RW CLKMD1 RW RCSP — (b7) RW No register bit. If necessary, set to 0. Read as undefined value — Bits UiIRS and UiRRM of UART2 and UART5 to UART7 are bits in the UiC1 register. CLKMD1 (UART1CLK, CLKS Select Bit 1) (b5) When using multiple transmit/receive clock output pins, make sure the following condition is met: the CKDIR bit in the U1MR register = 0 (internal clock) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 503 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2.10 UARTi Special Mode Register (UiSMR) (i = 0 to 2, 5 to 7) UARTi Special Mode Register (i = 0 to 2, 5 to 7) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol U0SMR, U1SMR, U2SMR U5SMR, U6SMR, U7SMR Bit Symbol IICM Bit Name I2C mode select bit Arbitration lost detect flag control bit Bus busy flag Address 0247h, 0257h, 0267h 0287h, 0297h, 02A7h Function 0 : Other than I2C mode 1 : I2C mode 0 : Update per bit 1 : Update per byte 0 : Stop-condition detected 1 : Start-condition detected (busy) Set to 0 After Reset X000 0000b X000 0000b RW RW ABC RW BBS — (b3) ABSCS RW Reserved bit RW Bus collision detect sampling 0 : Rising edge of transmit/receive clock clock select bit 1 : Underflow signal of timer Aj Auto clear function select bit 0 : No auto clear function of transmit enable bit 1 : Auto clear at occurrence of bus collision Transmit start condition select bit 0 : Not synchronized to RXDi 1 : Synchronized to RXDi RW ACSE RW SSS — (b7) RW No register bit. If necessary, set to 0. Read as undefined value — BBS (Bus Busy Flag) (b2) The BBS bit is set to 0 by a program. (It remains unchanged even if 1 is written.) ABSCS (Bus Collision Detect Sampling Clock Select Bit) (b4) When the ABSCS bit is 1, the combinations of UARTi and timer Aj are as follows: UART0, UART6: Underflow signal of timer A3 UART1, UART7: Underflow signal of timer A4 UART2, UART5: Underflow signal of timer A0 SSS (Transmit Start Condition Select Bit) (b6) When a transmit starts, the SSS bit is set to 0 (not synchronized to RXDi). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 504 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2.11 UARTi Special Mode Register 2 (UiSMR2) (i = 0 to 2, 5 to 7) UARTi Special Mode Register 2 (i = 0 to 2, 5 to 7) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0SMR2, U1SMR2, U2SMR2 U5SMR2, U6SMR2, U7SMR2 Bit Symbol IICM2 Bit Name I2C mode select bit 2 Address 0246h, 0256h, 0266h 0286h, 0296h, 02A6h Function After Reset X000 0000b X000 0000b RW RW See table 23.18 “I2C Mode Functions” 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0: Transmit/receive clock 1: Low-level output 0: Enabled 1: Disabled (high-impedance) CSC Clock synchronization bit RW SWC SCL wait output bit RW ALS SDA output stop bit RW STAC UARTi initialization bit RW SWC2 SCL wait output bit 2 RW SDHI — (b7) SDA output disable bit RW No register bit. If necessary, set to 0. Read as undefined value — REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 505 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2.12 UARTi Special Mode Register 3 (UiSMR3) (i = 0 to 2, 5 to 7) UARTi Special Mode Register 3 (i = 0 to 2, 5 to 7) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0SMR3, U1SMR3, U2SMR3 U5SMR3, U6SMR3, U7SMR3 Bit Symbol — (b0) CKPH — (b2) NODC — (b4) DL0 SDAi digital delay setup bit Bit Name Address 0245h, 0255h, 0265h 0285h, 0295h, 02A5h Function After Reset 000X 0X0Xb 000X 0X0Xb RW — No register bit. If necessary, set to 0. Read as undefined value 0 : No clock delay 1 : With clock delay Clock phase set bit RW No register bit. If necessary, set to 0. Read as undefined value 0 : CLKi is CMOS output 1 : CLKi is N-channel open drain output — Clock output select bit RW No register bit. If necessary, set to 0. Read as undefined value b7 b6 b5 — DL1 DL2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : No delay 1 : 1 to 2 cycle(s) of UiBRG count source 0 : 2 to 3 cycles of UiBRG count source 1 : 3 to 4 cycles of UiBRG count source 0 : 4 to 5 cycles of UiBRG count source 1 : 5 to 6 cycles of UiBRG count source 0 : 6 to 7 cycles of UiBRG count source 1 : 7 to 8 cycles of UiBRG count source RW RW RW NODC (Clock Output Select Bit) (b3) This function is used to set P-channel transistor of the COMS output buffer always off, but not to change the CLKi pin to open-drain output completely. Check electrical characteristics for the input voltage range. DL2-DL0 (SDAi Digital Delay Setup Bit) (b7-b5) Bits DL2 to DL0 are used to generate a delay in SDAi output by digital means in I2C mode. Except for I2C mode, set these bits to 000b (no delay). The amount of delay varies with the load on pins SCLi and SDAi. Also, when using an external clock, the amount of delay increases by about 100 ns. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 506 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.2.13 UARTi Special Mode Register 4 (UiSMR4) (i = 0 to 2, 5 to 7) UARTi Special Mode Register 4 (i = 0 to 2, 5 to 7) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0SMR4, U1SMR4, U2SMR4 U5SMR4, U6SMR4, U7SMR4 Bit Symbol STAREQ Bit Name Start condition generate bit Restart condition generate bit Stop condition generate bit Address 0244h, 0254h, 0264h 0284h, 0294h, 02A4h Function 0 : Clear 1 : Start 0 : Clear 1 : Start 0 : Clear 1 : Start After Reset 00h 00h RW RW RSTAREQ RW STPREQ RW STSPSEL SCL, SDA output select bit 0 : Start and stop conditions not output 1 : Start and stop conditions output 0 : ACK 1 : NACK 0 : Serial interface data output 1 : ACK data output 0 : Disabled 1 : Enabled 0 : SCL low hold disabled 1 : SCL low hold enabled RW ACKD ACK data bit RW ACKC ACK data output enable bit RW SCLHI SCL output stop enable bit RW SWC9 SCL wait bit 3 RW STAREQ (Start Condition Generate Bit) (b0) The STAREQ bit becomes 0 when the start condition is generated. RSTAREQ (Restart Condition Generate Bit) (b1) The RSTAREQ bit becomes 0 when the restart condition is generated. STPREQ (Stop Condition Generate Bit) (b2) The STPREQ bit becomes 0 when the stop condition is generated. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 507 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3 23.3.1 Operations Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode uses a transmit/receive clock to transmit/receive data. Table 23.5 lists the Clock Synchronous Serial I/O Mode Specifications. Table 23.5 Data format Transmit/receive clock Clock Synchronous Serial I/O Mode Specifications Item Character bit length: 8 bits Specification • CKDIR bit in the UiMR register = 0 (internal clock): fj -------------------2( n + 1) fj = f1SIO, f2SIO, f8SIO, f32SIO n = Setting value of UiBRG register • CKDIR bit = 1 (external clock): Input from CLKi pin 00h to FFh Transmission and reception Selectable from CTS function, RTS function or CTS/RTS function disabled control Transmission start conditions To start transmission, satisfy the following requirements (1) • The TE bit in the UiC1 register = 1 (transmission enabled) • The TI bit in the UiC1 register = 0 (data present in UiTB register) • If CTS function is selected, input on the CTSi pin is low. Reception start conditions To start reception, satisfy the following requirements (1) • The RE bit in the UiC1 register = 1 (reception enabled) • The TE bit in the UiC1 register = 1 (transmission enabled) • The TI bit in the UiC1 register = 0 (data present in the UiTB register) Transmit interrupt: One of the following can be selected. • The UiIRS bit = 0 (transmit buffer empty): When transferring data from the UiTB register to the UARTi transmit register (at start of transmission) • The UiIRS bit =1 (transmission completed): When the serial interface completed sending data from the UARTi transmit register Receive interrupt: • When transferring data from the UARTi receive register to the UiRB register (at completion of reception) Overrun error (2) This error occurs if the serial interface started receiving the next unit of data before reading the UiRB register and received the 7th bit of the next unit of data Interrupt request generation timing Error detection Selectable functions • CLK polarity selection Data input/output can be selected to occur synchronously with the rising or the falling edge of the transmit/receive clock • LSB first, MSB first selection Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected • Continuous receive mode selection Reception is enabled immediately by reading the UiRB register • Switching serial data logic This function reverses the logic value of the transmit/receive data • Transmit/receive clock output from multiple pins selection (UART1) The output pin can be selected by a program by setting two UART1 transmit/receive clock pins. • Separate CTS/RTS pins (UART0) CTS0 and RTS0 are input/output from separate pins i = 0 to 2, 5 to 7 Notes: 1. When an external clock is selected, either of the following conditions must be met: If the CKPOL bit in the UiC0 register is 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transmit/receive clock), the external clock is in the high state; if the CKPOL bit in the UiC0 register is 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transmit/ receive clock), the external clock is in the low state. 2. If an overrun error occurs, the receive data of the UiRB register will be undefined. The IR bit in the SiRIC register remains unchanged. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 508 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Table 23.6 lists Pin Functions in Clock Synchronous Serial I/O Mode (Multiple Transmit/Receive Clock Output Pin Function Not Selected). Table 23.7 lists P6_4 Pin Functions in Clock Synchronous Serial I/O Mode. Note that for a period from when UARTi operating mode is selected to when transmission starts, the TXDi pin outputs a high-level signal. (If N-channel open-drain output is selected, this pin is in high-impedance state.) Table 23.6 Pin Functions in Clock Synchronous Serial I/O Mode (Multiple Transmit/Receive Clock Output Pin Function Not Selected) Pin Name I/O TXDi Output RXDi Input Input CLKi Output Input CTSi/RTSi Input Function Serial data output Serial data input Input port Transmit/receive clock output Transmit/receive clock input CTS input Method of Selection (Outputs dummy data when performing reception only.) Set the port direction bits sharing pins to 0. Set the port direction bits to 0. (can be used as an input port when performing transmission only) The CKDIR bit in the UiMR register = 0 The CKDIR bit in the UiMR register = 1 Set the port direction bits sharing pins to 0. The CRD bit in the UiC0 register = 0 The CRS bit in the UiC0 register = 0 Set the port direction bits sharing pins to 0. The CRD bit in the UiC0 register = 0 The CRS bit in the UiC0 register = 1 The CRD bit in the UiC0 register = 1 Output Input/ output i = 0 to 2, 5 to 7 Table 23.7 RTS output I/O port P6_4 Pin Functions in Clock Synchronous Serial I/O Mode Pin Function P6_4 CTS1 RTS1 CTS0 (1) CLKS1 1 0 0 0 - U1C0 Register CRD CRS 0 1 0 - Bit Set Value UCON Register RCSP CLKMD1 CLKMD0 0 0 0 0 0 0 1 0 1 (2) 1 PD6 Register PD6_4 Input: 0, Output: 1 0 0 - - indicates either 0 or 1 Notes: 1. In addition to this, set the CRD bit in the U0C0 register to 0 (CTS0/RTS0 enabled) and the CRS bit in the U0C0 register to 1 (RTS0 selected). 2. When the CLKMD1 bit is 1 and the CLKMD0 bit is 0, the following logic levels are output. •High if the CLKPOL bit in the U1C0 register is 0 •Low if the CLKPOL bit in the U1C0 register is 1 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 509 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Table 23.8 lists Registers Used and Settings in Clock Synchronous Serial I/O Mode. Table 23.8 Registers Used and Settings in Clock Synchronous Serial I/O Mode Register UiTB UiRB (2) (2) Bits 0 to 7 0 to 7 OER 0 to 7 SMD2 to SMD0 CKDIR IOPOL CLK1 to CLK0 CRS TXEPT CRD NCH CKPOL UFORM TE TI RE RI UjIRS UjRRM UiLCH UiERE 0 to 7 0 to 7 0 to 2 NODC 4 to 7 0 to 7 U0IRS U1IRS U0RRM U1RRM CLKMD0 CLKMD1 RCSP 7 IFSR34 IFSR36 IFSR25 Set transmission data Function Reception data can be read. Overrun error flag Set bit rate. Set to 001b. Select the internal clock or external clock. Set to 0. Select the count source for the UiBRG register. If CTS or RTS is used, select which function to use. Transmit register empty flag Enable or disable the CTS or RTS function. Select TXDi pin output mode. (1) Select the transmit/receive clock polarity. Select LSB first or MSB first. Set to 1 to enable transmission/reception. Transmit buffer empty flag Set to 1 to enable reception. Reception complete flag Select source of UARTj transmit interrupt. Set to 1 to use continuous receive mode. Set to 1 to use inverted data logic. Set to 0. Set to 0. Set to 0. Set to 0. Select clock output mode. Set to 0. Set to 0. Select source of UART0 transmit interrupt. Select source of UART1 transmit interrupt. Set to 1 to use continuous receive mode. Set to 1 to use continuous receive mode. Select the transmit/receive clock output pin when CLKMD1 is 1. Set to 1 to output UART1 transmit/receive clock from two pins. Set to 1 to separate the CTS0/RTS signal of UART0. Set to 0. Set to 0 to use UART5 transmit interrupt. Set to 0 to use UART6 transmit interrupt. Set to 0 to use UART7 transmit interrupt. UiBRG UiMR (2) UiC0 UiC1 UiSMR UiSMR2 UiSMR3 UiSMR4 UCON IFSR3A IFSR2A i = 0 to 2, 5 to 7 j = 2, 5 to 7 Notes: 1. The TXD2 pin is N channel open-drain output. Nothing is assigned in the NCH bit in the U2C0 register. If necessary, set to 0. 2. Set bits not listed above to 0 when writing to the registers in clock synchronous serial I/O mode. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 510 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) (1) Example of Transmit Timing (Internal Clock Selected) Tc Transmit/receive clock 1 0 1 0 High CTSi Low Data is transferred from the UiTB register to the UARTi transmit register. TE bit in UiC1 register TI bit in UiC1 register Set the data in the UiTB register. TCLK Pulse stops because a highlevel signal is applied to CTSi Pulse stops because the TE bit is set to 0 CLKi TXDi TXEPT flag in UiC0 register IR bit in SiTIC register D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 1 0 1 0 Set to 0 by an interrupt request acknowledgement or by a program. TC = TCLK = 2(n + 1)/fj fj: Frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO) n: Value set to the UiBRG register i = 0 to 2, 5 to 7 The above timing diagram applies when the register bits are set as follows: · The CKDIR bit in the UiMR register = 0 (internal clock) · The CRD bit in the UiC0 register = 0 (CTS/RTS enabled), the CRS bit = 0 (CTS selected) · The CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transmit/receive clock) · The UiIRS bit in the UiC1 register = 0 (an interrupt request occurs when the UiTB register becomes empty) (2) Example of Receive Timing (External Clock Selected) RE bit in UiC1 register TE bit in UiC1 register TI bit in UiC1 register 1 0 1 0 1 0 High Data is transferred from the UiTB register to the UARTi transmit register. Set the dummy data in the UiTB register. RTSi Low CLKi 1/fEXT A low-level signal is applied when the UiRB register is read. Received data is taken in RXDi RI bit in UiC1 register IR bit in SiRIC register D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 Read the UiRB register D7 D0 D1 D2 D3 D4 D5 D6 1 0 1 0 Data is transferred from the UARTi receive register to the UiRB register Set to 0 by an interrupt request acknowledgement or by a program. OER flag in UiRB register 1 0 i = 0 to 2, 5 to 7 Make sure the following conditions are met when input to the CLKi pin before receiving data is high: · The TE bit in the UiC1 register = 1 (transmit enabled) · The RE bit in the UiC1 register = 1 (receive enabled) · Write dummy data to the UiTB register The above timing diagram applies to the case where the register bits are set as follows: · The CKDIR bit in the UiMR register = 1 (external clock) · The CRD bit in the UiC0 register = 0 (CTS/RTS enabled), the CRS bit = 1 (RTS selected) · The CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transmit/ receive clock) fEXT: Frequency of the external clock Figure 23.5 Transmit/Receive Operation during Clock Synchronous Serial I/O Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 511 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.1.1 Transmit/Receive Register Initialization When the transmit/receive register needs to be initialized due to an interrupted transmission/ reception, follow the procedures below. • Initializing the UiRB register (i = 0 to 2, 5 to 7) (1) Set the RE bit in the UiC1 register to 0 (reception disabled). (2) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled). (3) Set bits SMD2 to SMD0 in the UiMR register to 001b (clock synchronous serial I/O mode). (4) Set the RE bit in the UiC1 register to 1 (reception enabled). • Initializing the UiTB register (i = 0 to 2, 5 to 7) (1) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled). (2) Set bits SMD2 to SMD0 in the UiMR register to 001b (clock synchronous serial I/O mode). (3) Write a 1 to the RE bit in the UiC1 register (transmission enabled), regardless of the value of the TE bit in the UiCi register. 23.3.1.2 CLK Polarity Select Function Use the CKPOL bit in the UiC0 register (i = 0 to 2, 5 to 7) to select the transmit/receive clock polarity. Figure 23.6 shows the Transmit/Receive Clock Polarity. (1) CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transmit/receive clock) CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 A high-level signal is output from the CLKi pin during no transmission/reception. D7 D7 (2) CKPOL bit = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transmit/receive clock) A low-level signal is output from the CLKi pin during no transmission/reception. CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 The above applies under the following conditions. The CKDIR bit in the UiMR register is 0 (internal clock), the UFORM bit in the UiC0 register is 0 (LSB first), and the UiLCH bit in the UiC1 register is 0 (no reverse). i = 0 to 2, 5 to 7 Figure 23.6 Transmit/Receive Clock Polarity REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 512 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.1.3 LSB First/MSB First Select Function Use the UFORM bit in the UiC0 register (i = 0 to 2, 5 to 7) to select the bit order. Figure 23.7 shows the Bit Order. (1) UFORM bit in the UiC0 register = 0 (LSB first) CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 (2) UFORM bit in the UiC0 register = 1 (MSB first) CLKi TXDi RXDi D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 The above applies under the following conditions. The CKPOL bit in the UiC0 register is 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transmit/receive clock), and the UiLCH bit in the UiC1 register is 0 (no reverse). i = 0 to 2, 5 to 7 Figure 23.7 Bit Order REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 513 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.1.4 Continuous Receive Mode In continuous receive mode, receive operation is enabled when the receive buffer register is read. It is not necessary to write dummy data to the transmit buffer register to enable receive operation in this mode. However, a dummy read of the receive buffer register is required when starting the operating mode. When the UiRRM bit (i = 0 to 2, 5 to 7) is 1 (continuous receive mode), the TI bit in the UiC1 register is set to 0 (data present in the UiTB register) by reading the UiRB register. In this case (UiRRM bit = 1), do not write dummy data to the UiTB register by a program. When using an external clock, read the UiRB register between the eighth bit of data is received and the next transmission starts. Figure 23.8 shows Operation Example in Continuous Receive Mode. When using an external clock, read the UiRB register during this period. CLKi RXDi D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 When using an external clock, read the UiRB register during this period. D5 D6 D7 D0 D1 D2 D7 received i = 0 to 2, 5 to 7 Next transmission starts. D7 received Next transmission starts. The above applies under the following conditions. - The CKPOL bit in the UiC0 register is 0 (receive data input at the falling edge of the transmit/receive clock). - The UFORM bit in the UiC0 register is 0 (LSB first). - The CKDIR bit in the UiMR register is 1 (external clock). Figure 23.8 Operation Example in Continuous Receive Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 514 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.1.5 Serial Data Logic Switching Function When the UiLCH bit in the UiC1 register (i = 0 to 2, 5 to 7) is 1 (reverse), the data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the UiRB register. Figure 23.9 shows Serial Data Logic. (1) UiLCH bit in the UiC1 register = 0 (no reverse) Transmit/receive clock TXDi (no reverse) H L H L D0 D1 D2 D3 D4 D5 D6 D7 (2) UiLCH bit in the UiC1 register = 1 (reverse) Transmit/receive clock TXDi (reverse) H L H L D0 D1 D2 D3 D4 D5 D6 D7 The above applies under the following conditions. - The CKPOL bit in the UiC0 register is 0 (transmit data output at the falling edge of the transmit/receive clock). - The UFORM bit in the UiC0 register is 0 (LSB first). i = 0 to 2, 5 to 7 Figure 23.9 Serial Data Logic 23.3.1.6 Transmit/Receive Clock Output from Multiple Pins (UART1) Use bits CLKMD1 to CLKMD0 in the UCON register to select one of the two transmit/receive clock output pins (see Figure 23.10). This function can be used when the selected transmit/receive clock for UART1 is an internal clock. MCU TXD1 (P6_7) CLKS1 (P6_4) CLK1 (P6_5) IN CLK IN CLK Transmit/receive enabled when the CLKMD0 bit in the UCON register is 0 Transmit/receive enabled when the CLKMD0 bit in the UCON register is 1 The above applies under the following conditions. - The CKDIR bit in the U1MR register is 0 (internal clock). - The CLKMD1 bit in the UCON register is 1 (transmit/receive clock output from multiple pins). Figure 23.10 Transmit/Receive Clock Output from Multiple Pins REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 515 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.1.7 CTS/RTS Function The CTS function is used to start transmit/receive operation when a low-level signal is applied to the CTSi/RTSi (i = 0 to 2, 5 to 7) pin. Transmit/receive operation begins when input to the CTSi/RTSi pin becomes low. If the low-level signal is switched to high during a transmit or receive operation, the operation stops before the next data. For the RTS function, the CTSi/RTSi pin outputs a low-level signal when the MCU is ready to receive. The output level goes high on the first falling edge of the CLKi pin. Refer to Table 23.6 “Pin Functions in Clock Synchronous Serial I/O Mode (Multiple Transmit/Receive Clock Output Pin Function Not Selected)”. 23.3.1.8 CTS/RTS Separate Function (UART0) This function separates CTS0/RTS0, outputs RTS0 from the P6_0 pin, and inputs CTS0 from the P6_4 pin. To use this function, set the register bits as shown below. • The CRD bit in the U0C0 register= 0 (enable CTS/RTS of UART0) • The CRS bit in the U0C0 register= 1 (output RTS of UART0) • The CRD bit in the U1C0 register= 0 (enable CTS/RTS of UART1) • The CRS bit in the U1C0 register= 0 (input CTS of UART1) • The RCSP bit in the UCON register= 1 (inputs CTS0 from the P6_4 pin) • The CLKMD1 bit in the UCON register= 0 (CLKS1 not used) Note that when using the CTS/RTS separate function, CTS/RTS of UART1 function cannot be used. MCU TXD0 (P6_3) RXD0 (P6_2) CLK0 (P6_1) IN OUT CLK CTS RTS IC RTS0 (P6_0) CTS0 (P6_4) Figure 23.11 CTS/RTS Separate Function REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 516 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.2 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after setting the desired bit rate and bit order. Table 23.9 lists the UART Mode Specifications. Table 23.9 Item Data format UART Mode Specifications Specification Transmit/receive clock • Character bits : Selectable from 7, 8, or 9 bits • Start bit : 1 bit • Parity bit : Selectable from odd, even, or none • Stop bit : Selectable from 1 bit or 2 bits • The CKDIR bit in the UiMR register = 0 (internal clock): fj -----------------------16 ( n + 1 ) fEXT -----------------------16 ( n + 1 ) fj = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of UiBRG register 00h to FFh • CKDIR bit = 1 (external clock): fEXT: Input from CLKi pin n: Setting value of UiBRG register 00h to FFh Transmission and reception control Transmission start conditions Selectable from CTS function, RTS function or CTS/RTS function disabled To start transmission, satisfy the following requirements. • The TE bit in the UiC1 register = 1 (transmission enabled) • The TI bit in the UiC1 register = 0 (data present in the UiTB register) • If CTS function is selected, input on the CTSi pin is low. Reception start conditions To start reception, satisfy the following requirements. • The RE bit in the UiC1 register = 1 (reception enabled) • Start bit detection Interrupt request Transmit interrupt: One of the following can be selected. generation timing • The UiIRS bit = 0 (transmit buffer empty): When transferring data from the UiTB register to the UARTi transmit register (at start of transmission) • The UiIRS bit =1 (transmission completed): When the serial interface completes sending data from the UARTi transmit register Receive interrupt: • When transferring data from the UARTi receive register to the UiRB register (at completion of reception) Error detection • Overrun error (1) This error occurs if the serial interface starts receiving the next unit of data before reading the UiRB register and receives the bit one before the last stop bit of the next unit of data. • Framing error This error occurs when the number of stop bits set is not detected • Parity error This error occurs when the number of 1s of the parity bit and character bit does not match the set value of the PRY bit in the UiMR register. • Error sum flag This flag is set to 1 when an overrun, framing, or parity error occurs. Selectable functions • LSB first, MSB first selection Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected • Serial data logic switch This function reverses the logic of the transmit/receive data. The start and stop bits are not reversed. • TXD, RXD I/O polarity switch This function reverses the polarities of the TXD pin output and RXD pin input. The logic levels of all I/O data are reversed. • Separate CTS/RTS pins (UART0) CTS0 and RTS0 are input/output from separate pins. i = 0 to 2, 5 to 7 Note: 1. If an overrun error occurs, the receive data of the UiRB register will be undefined. The IR bit in the SiRIC register remains unchanged. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 517 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Table 23.10 lists I/O Pin Functions in UART Mode. Table 23.11 lists the P6_4 Pin Functions in UART Mode. Note that for a period from when the UARTi operating mode is selected to when transmission starts, the TXDi pin outputs a high-level signal. (If N-channel open-drain output is selected, this pin is in high-impedance state.) Table 23.10 I/O Pin Functions in UART Mode Pin Name I/O TXDi Output RXDi Input Input CLKi Input/ output Input Function Serial data output Serial data input Input port Input/output port Transmit/receive clock input CTS input Method of Selection (High-level output when performing reception only.) Set the port direction bits sharing pins to 0. Set the port direction bits sharing pins to 0. (can be used as an input port when performing transmission only) The CKDIR bit in the UiMR register = 0 The CKDIR bit in the UiMR register = 1 Set the port direction bits sharing pins to 0. The CRD bit in the UiC0 register = 0 The CRS bit in the UiC0 register = 0 Set the port direction bits sharing pins to 0. The CRD bit in the UiC0 register = 0 The CRS bit in the UiC0 register = 1 The CRD bit in the UiC0 register = 1 CTSi/RTSi Input Output Input/ output i = 0 to 2, 5 to 7 Table 23.11 RTS output I/O port P6_4 Pin Functions in UART Mode Pin Function P6_4 CTS1 RTS1 CTS0 (1) − indicates either 0 or1. Note: 1. In addition to this, set the CRD bit in the U0C0 register to 0 (CTS0/RTS0 enabled) and the CRS bit in the U0C0 register to 1 (RTS0 selected). U1C0 Register CRD CRS 1 0 0 0 1 0 0 Bit Set Value UCON Register RCSP CLKMD1 0 0 0 0 0 0 1 0 PD6 Register PD6_4 Input: 0, Output: 1 0 0 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 518 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Table 23.12 lists Registers Used and Settings in UART Mode. Table 23.12 Registers Used and Settings in UART Mode Bits Set transmission data. (1), (3) Register UiTB 0 to 8 UiRB UiBRG UiMR 0 to 8 Function Reception data can be read. (1) Error flag Set bit rate. Set to 100b when character bit length is 7 bits. Set to 101b when character bit length is 8 bits. Set to 110b when character bit length is 9 bits. Select the internal clock or external clock. Select number of stop bits. Select whether parity is included and whether odd or even. Select the TXD/RXD input/output polarity. Select the count source for the UiBRG register. If CTS or RTS is used, select which function to use. Transmit register empty flag Enable or disable the CTS or RTS function. Select TXDi pin output mode. (2) Set to 0. LSB first or MSB first can be selected when character bit length is 8 bits. Set to 0 when character bit length is 7 or 9 bits. Set to 1 to enable transmission. Transmit buffer empty flag Set to 1 to enable reception. Reception complete flag Select source of UARTj transmit interrupt. Set to 0. Set to 1 to use reversed data logic. Set to 0. Set to 0. Set to 0. Set to 0. Set to 0. Select source of UART0 transmit interrupt. Select source of UART1 transmit interrupt. Set to 0. Set to 0. Invalid because CLKMD1 is 0 Set to 0. Set to 1 to input CTS0 signal of UART0 from the P6_4 pin. Set to 0. Set to 0 to use UART5 transmit interrupt. Set to 0 to use UART6 transmit interrupt. Set to 0 to use UART7 transmit interrupt. OER, FER, PER, SUM 0 to 7 SMD2 to SMD0 UiC0 CKDIR STPS PRY, PRYE IOPOL CLK0, CLK1 CRS TXEPT CRD NCH CKPOL UFORM UiC1 TE TI RE RI UjIRS UjRRM UiLCH UiERE 0 to 7 0 to 7 0 to 7 0 to 7 U0IRS U1IRS U0RRM U1RRM CLKMD0 CLKMD1 RCSP 7 IFSR34 IFSR36 IFSR25 UiSMR UiSMR2 UiSMR3 UiSMR4 UCON IFSR3A IFSR2A i = 0 to 2, 5 to 7 j = 2, 5 to 7 Notes: 1. The bits used for transmit/receive data are as follows: Bits 0 to 6 when character bit length is 7 bits; bits 0 to 7 when character bit length is 8 bits; bits 0 to 8 when character bit length is 9 bits. 2. TXD2 pin is N channel open-drain output. Nothing is assigned in the NCH bit in the U2C0 register. If necessary, set to 0. 3. The contents of bits 7 and 8 are undefined when character bit length is 7 bits. The contents of bit 8 is undefined when character bit length is 8 bits. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 519 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) (1) 8-bit Data Transmit Timing (with a Parity and 1 Stop Bit) The transmit/receive clock stops once because a high-level signal is applied to the CTS pin when the stop bit is verified. The transmit/receive clock resumes running as soon as a low-level signal is applied to the CTS pin. Tc Transmit/receive clock TE bit in UiC1 register 0 TI bit in 1 UiC1 register 0 1 Set the data in the UiTB register. High Data is transferred from the UiTB register to the UARTi transmit register. CTSi Low Start bit Parity bit D1 D2 D3 D4 D5 D6 D7 P SP Stop bit ST D0 D1 D2 D3 D4 D5 Pulse stops because the TE bit is set to 0. D6 D7 P SP ST D0 D1 TXDi TXEPT bit in 1 UiC0 register 0 IR bit in 1 SiTIC register 0 ST D0 Set to 0 by an interrupt request acknowledgement or by a program. i = 0 to 2, 5 to 7 The above timing diagram applies when the register bits are set as follows: · The PRYE bit in the UiMR register = 1 (parity enabled) · The STPS bit in the UiMR register = 0 (1 stop bit) · The CRD bit in the UiC0 register = 0 (CTS/RTS enabled) · The CRS bit in the UiC0 register = 0 (CTS selected) · The UiIRS bit in the UiC1 register = 1 (an interrupt request occurs when transmit completed) Tc = 16(n + 1)/fj or 16(n + 1)/fEXT fj : Frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO) fEXT : Frequency of UiBRG count source (external clock) n : Value set to UiBRG (2) 9-bit Data Transmit Timing (with No Parity and 2 Stop Bits) Tc Transmit/receive clock TE bit in UiC1 register 0 TI bit in 1 UiC1 register 0 Stop bit D1 D2 D3 D4 D5 D6 D7 D8 SP SP 1 Set the data in the UiTB register. Data is transferred from the UiTB register to the UARTi transmit register. Start bit Stop bit ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 TXDi TXEPT bit in 1 UiC0 register 0 IR bit in 1 SiTIC register 0 ST D0 Set to 0 by an interrupt request acknowledgement or by a program. i = 0 to 2, 5 to 7 The above timing diagram applies when the register bits are set as follows: · The PRYE bit in the UiMR register = 0 (parity disabled) · The STPS bit in the UiMR register = 1 (2 stop bits) · The CRD bit in the UiC0 register = 1 (CTS/RTS disabled) · The UiIRS bit in the UiC1 register = 0 (an interrupt request occurs when transmit buffer becomes empty) TC = 16(n + 1)/fj or 16(n + 1)/fEXT fj : Frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO) fEXT: Frequency of UiBRG count source (external clock) n : Value set to UiBRG Figure 23.12 Transmit Timing in UART Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 520 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Example of Receive Timing When Character Bit Length is 8 Bits (Parity Disabled, One Stop Bit) UiBRG count source RE bit in UiC1 register RXDi 1 0 Stop bit Start bit Sampled as low Receive data taken in D0 D1 D7 Transmit/ receive clock RI bit in UiC1 register RTSi IR bit in SiRIC register 1 0 High Low 1 0 Reception triggered when transmit/receive clock is generated by falling edge of start bit. Transferred from UARTi receive register to UiRB register. Set to 0 by an interrupt request acknowledgement or by a program. The above timing diagram applies when the register bits are set as follows: · The PRYE bit in the UiMR register = 0 (parity disabled) · The STPS bit in the UiMR register = 0 (1 stop bit) · The CRD bit in the UiC0 register = 0 (CTSi/RTSi enabled) · The CRS bit in the UiC0 register = 1 (RTSi selected) i = 0 to 2, 5 to 7 Figure 23.13 Receive Timing in UART Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 521 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.2.1 Bit Rate In UART mode, the frequency set by the UiBRG register (i = 0 to 2, 5 to 7) divided by 16 become the bit rate. The setting value (n) of the UiBRG register is calculated by the following formula. fj n = ---------------------------------------------- – 1 bitrate ( bps ) × 16 fj = f1SIO, f2SIO, f8SIO, f32SIO n = 00h to FFh Table 23.13 lists Example Bit Rates and Settings. Table 23.13 Example Bit Rates and Settings Bit Rate (bps) 1200 2400 4800 9600 14400 19200 28800 31250 38400 51200 Note: 1. Count Source of UiBRG f8SIO f8SIO f8SIO f1SIO f1SIO f1SIO f1SIO f1SIO f1SIO f1SIO Peripheral Function Clock f1: 16 MHz Peripheral Function Clock f1: 24 MHz Set Value of Set value of Bit Rate (bps) Bit Rate (bps) UiBRG: n UiBRG: n 103 (67h) 1202 155 (9Bh) 1202 51 (33h) 2404 77 (4Dh) 2404 25 (19h) 4808 38 (26h) 4808 103 (67h) 9615 155 (9Bh) 9615 68 (44h) 14493 103 (67h) 14423 51 (33h) 19231 77 (4Dh) 19231 34 (22h) 28571 51 (33h) 28846 31 (1Fh) 31250 47 (2Fh) 31250 25 (19h) 38462 38 (26h) 38462 19 (13h) 50000 28 (1Ch) 51724 This applies when the OCOSEL0 bit or OCOSEL1 bit in the UCLKSEL0 register is 0 (f1). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 522 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.2.2 Transmit/Receive Register Initialization When the transmit/receive register needs to be initialized due to an interrupted transmission/ reception, follow the procedures below. • Initializing the UiRB register (i = 0 to 2, 5 to 7) (1) Set the RE bit in the UiC1 register to 0 (reception disabled). (2) Set the RE bit in the UiC1 register to 1 (reception enabled). • Initializing the UiTB register (1) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled). (2) Reset bits SMD2 to SMD0 in the UiMR register to 001b, 101b, and 110b. (3) Set 1 (transmission enabled), regardless of the set value of the TE bit in the UiC1 register. 23.3.2.3 LSB First/MSB First Select Function As shown in Figure 23.14, the bit order can be selected by using the UFORM bit in the UiC0 register. This function is valid when the character bit length is 8 bits. (1) UFORM bit in the UiC0 register = 0 (LSB first) CLKi TXDi RXDi ST ST D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 P P SP SP (2) UFORM bit in the UiC0 register = 1 (MSB first) CLKi TXDi RXDi ST ST D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 P P SP SP ST : Start bit P : Parity bit SP : Stop bit i = 0 to 2, 5 to 7 The above applies under the following conditions. - The CKPOL bit in the UiC0 register is 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transmit/receive clock). - The UiLCH bit in the UiC1 register is 0 (no reverse). - The STPS bit in the UiMR register is 0 (1 stop bit). - The PRYE bit in the UiMR register is 1 (parity enabled). Figure 23.14 Bit Order REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 523 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.2.4 Serial Data Logic Switching Function The logic of the data written to the UiTB register is reversed and then transmitted. Similarly, the reversed logic of the received data is read when the UiRB register is read. Figure 23.15 shows Serial Data Logic. (1) UiLCH bit in the UiC1 register = 0 (no reverse) Transmit/ receive clock TXDi (no reverse) High Low High Low ST D0 D1 D2 D3 D4 D5 D6 D7 P SP (2) UiLCH bit in the UiC1 register = 1 (reverse) Transmit/ receive clock TXDi (reverse) High Low High Low ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST : Start bit P : Parity bit SP : Stop bit i = 0 to 2, 5 to 7 The above applies under the following conditions. - The CKPOL bit in the UiC0 register is0 (transmit data output at the falling edge of the transmit/receive clock). - The UFORM bit in the UiC0 register is 0 (LSB first). - The STPS bit in the UiMR register is 0 (1 stop bit). - The PRYE bit in the UiMR register is 1 (parity enabled). - The IOPOL bit in the UiMR register is 0 (TXD, RXD I/O not reversed). Figure 23.15 Serial Data Logic REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 524 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.2.5 TXD and RXD I/O Polarity Reverse Function This function reverses the polarities of the TXDi pin output and RXDi pin input. The logic levels of all input/output data (including bits for start, stop, and parity) are reversed. Figure 23.16 shows TXD and RXD I/O Polarity Reversal. (1) IOPOL bit in the UiMR register = 0 (no reverse) Transmit/receive clock TXDi (no reverse) RXDi (no reverse) High Low High Low High Low ST ST D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 P P SP SP (2) IOPOL bit in the UiMR register = 1 (reverse) Transmit/receive clock TXDi (reverse) RXDi (reverse) ST: Start bit P : Parity bit SP: Stop bit i = 0 to 2, 5 to 7 High Low High Low High Low ST ST D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 P P SP SP The above applies under the following conditions. - The UFORM bit in the UiC0 register is 0 (LSB first). - The STPS bit in the UiMR register is 0 (1 stop bit). - The PRYE bit in the UiMR register is 1 (parity enabled). - The UiLCH bit in the UiC1 register is 0 (serial data logic not reversed). Figure 23.16 TXD and RXD I/O Polarity Reversal REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 525 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.2.6 CTS/RTS Function The CTS function is used to start transmit operation when a low-level signal is applied to the CTSi/ RTSi (i = 0 to 2, 5 to 7) pin. Transmit operation begins when input to the CTSi/RTSi pin becomes low. If the low-level signal is switched to high during a transmit operation, the operation stops after the ongoing transmit/receive operation is completed. When the RTS function is used, the CTSi/RTSi pin outputs a low-level signal when the MCU is ready to receive. The output level goes high when a start bit is detected. Refer to Table 23.10 “I/O Pin Functions in UART Mode”. 23.3.2.7 CTS/RTS Separate Function (UART0) This function separates CTS0 and RTS0, outputs RTS0 from the P6_0 pin, and inputs CTS0 from the P6_4 pin. To use this function, set the register bits as shown below. • The CRD bit in the U0C0 register= 0 (enable CTS/RTS of UART0) • The CRS bit in the U0C0 register= 1 (output RTS of UART0) • The CRD bit in the U1C0 register= 0 (enable CTS/RTS of UART1) • The CRS bit in the U1C0 register= 0 (input CTS of UART1) • The RCSP bit in the UCON register= 1 (inputs CTS0 from the P6_4 pin) • The CLKMD1 bit in the UCON register= 0 (CLKS1 not used) Note that when using the CTS/RTS separate function, CTS/RTS of UART1 function cannot be used. MCU TXD0 (P6_3) RXD0 (P6_2) IN OUT IC RTS0 (P6_0) CTS0 (P6_4) CTS RTS Figure 23.17 CTS/RTS Separate Function REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 526 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.3 Special Mode 1 (I2C mode) I2C mode supports the simplified I2C interface. Table 23.14 lists the specifications of I2C mode. Table 23.16 and Table 23.17 list the registers used in I2C mode and the register settings. Table 23.18 lists the I2C Mode Specifications. Figure 23.18 shows I2C Mode Block Diagram. Figure 23.19 shows Transfer to UiRB Register and Interrupt Timing. As shown in Table 23.18, the MCU is placed in I2C mode by setting bits SMD2 to SMD0 to 010b and the IICM bit to 1. Because SDAi transmit output has a delay circuit attached, SDAi output changes its state after SCLi goes low and remains stably low. Table 23.14 I2C Mode Specifications Item Data format Transmit/receive clock Specification Character bit length: 8 bits • Master mode CKDIR bit in the UiMR register = 0 (internal clock): fj -------------------2( n + 1) fj = f1SIO, f2SIO, f8SIO, f32SIO n = setting value of the UiBRG register 00h to FFh • Slave mode CKDIR bit = 1 (external clock): Input from the SCLi pin Transmission start conditions Reception start conditions To start transmission, satisfy the following requirements. (1) • The TE bit in the UiC1 register = 1 (transmission enabled) • The TI bit in the UiC1 register = 0 (data present in UiTB register) To start reception, satisfy the following requirements. (1) • The RE bit in the UiC1 register = 1 (reception enabled) • The TE bit in the UiC1 register = 1 (transmission enabled) • The TI bit in the UiC1 register = 0 (data present in the UiTB register) Transmission interrupt • Acknowledge undetected or transmit Reception interrupt • Acknowledge undetected or receive Start/stop condition detection interrupt • Start or stop condition detected Overrun error (2) This error occurs if the serial interface starts receiving the next unit of data before reading the UiRB register and receives the 8th bit of the unit of next data. • Arbitration lost Timing that the ABT bit in the UiRB register is updated can be selected. • SDAi digital delay No digital delay or a delay of 2 to 8 UiBRG count source clock cycles can be selected. • Clock phase setting With or without clock delay can be selected. Interrupt request generation timing Error detection Selectable functions i = 0 to 2, 5 to 7 Notes: 1. When an external clock is selected, the conditions must be met while the external clock is in the high state. 2. If an overrun error occurs, the received data of the UiRB register will be undefined. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 527 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) SDAi STSPSEL = 1 Delay circuit STSPSEL = 0 ACKC = 0 SDHI ACKD bit DQ T Start and stop condition generation block SDA (STSP) SCL (STSP) IICM2 = 1 DMA0 to DMA3 request ACKC = 1 Transmission register UARTi ALS IICM = 1 and IICM2 = 0 UARTi transmit, NACKi interrupt request Arbitration Reception register UARTi IICM2 = 1 DMA0, DMA2 request Noise filter Start condition detection S R Q IICM = 1 and IICM2 = 0 UARTi receive, ACKi interrupt request, DMA1, DMA3 request Bus busy NACK Stop condition detection DQ T DQ T SCLi Falling edge detection IICM = 0 I/O port Q R Port register (1) Internal clock SWC2 External clock R S ACK 9th bit STSPSEL=0 UARTi STSPSEL IICM = 1 =1 Noise filter CLK control UARTi 9th bit falling edge SWC Start/stop condition detection interrupt request This diagram applies when bits SMD2 to SMD0 in the UiMR register are 010b and the IICM bit in the UiSMR register is 1. IICM : Bit in the UiSMR register IICM2, SWC, ALS, SWC2, SDHI : Bits in the UiSMR2 register STSPSEL, ACKD, ACKC : Bits in the UiSMR4 register i = 0 to 2, 5 to 7 Note: If the IICM bit is 1, the pin can be read even when the port direction bit corresponding to the SCLi pin is 1 (output mode). Figure 23.18 I2C Mode Block Diagram Table 23.15 I/O Pin Functions in I2C Mode Pin Name I/O Function SCLi Input/output Clock Input or output SDAi Input/output Data Input or output i = 0 to 2, 5 to 7 Note: 1. Pins CLKi and CTSi/RTSi are not used. (They can be used as I/O ports.) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 528 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Table 23.16 Register UiTB UiRB (2) Registers Used and Settings in I2C Mode (1/2) Bits Function Master Set transmission data. Reception data can be read. ACK or NACK is set in this bit. Arbitration lost detection flag Overrun error flag Set a bit rate. Set to 010b. Set to 0. Set to 0. Select the count source for the UiBRG register. Invalid because CRD is 1 Transmit register empty flag Set to 1. Set to 1. (1) Set to 0. Set to 1. Set to 1 to enable transmission. Transmit buffer empty flag Set to 1 to enable reception. Reception complete flag Set to 1. Set to 0. Slave Set transmission data. Reception data can be read. ACK or NACK is set in this bit. Invalid Overrun error flag Invalid Set to 010b. Set to 1. Set to 0. Invalid Invalid because CRD is 1 Transmit register empty flag Set to 1. Set to 1. (1) Set to 0. Set to 1. Set to 1 to enable transmission. Transmit buffer empty flag Set to 1 to enable reception. Reception complete flag Set to 1. Set to 0. UiBRG UiMR (2) UiC0 0 to 7 0 to 7 8 ABT OER 0 to 7 SMD2 to SMD0 CKDIR IOPOL CLK1, CLK0 CRS TXEPT CRD (3) NCH CKPOL UFORM TE TI RE RI UjIRS UjRRM, UiLCH, UiERE IICM ABC BBS 3 to 7 IICM2 CSC SWC ALS STAC SWC2 SDHI 7 UiC1 UiSMR Set to 1. Select the timing that arbitration lost is detected. Bus busy flag Set to 0. See Table 23.18 “I2C Mode Functions”. Set to 1 to enable clock synchronization. Set to 1 to fix SCLi output to low at the falling edge of the 9th bit of clock. Set to 1 to stop SDAi output when arbitration lost is detected. Set to 0. Set to 1 to forcibly pull SCLi output low. Set to 1 to disable SDAi output. Set to 0. Set to 1. Invalid Bus busy flag Set to 0. See Table 23.18 “I2C Mode Functions”. Set to 0. Set to 1 to fix SCLi output to low at the falling edge of the 9th bit of clock. Set to 0. Set to 1 to initialize UARTi at start condition detection. Set to 1 to forcibly pull SCLi output low. Set to 1 to disable SDAi output. Set to 0. UiSMR2 i = 0 to 2, 5 to 7 j = 2, 5 to 7 Notes: 1. The TXD2 pin is N channel open-drain output. Nothing is assigned in the NCH bit in the U2C0 register. If necessary, set to 0. 2. Set the bits not listed above to 0 when writing in I2C mode. 3. when using UART1 in I2C mode, to enable the CTS/RTS separate function of UART0, set the CRD bit in the U1C0 register to 0 (CTS/RTS enabled) and the CRS bit to 0 (CTS input). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 529 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Table 23.17 Registers Used and Settings in I2C Mode (2/2) Register Bits Set to 0. Function Master Set to 0. See Table 23.18 “I2C Mode Functions”. Set the amount of SDAi digital delay. Set to 0. Set to 0. Set to 0. Set to 0. Select ACK or NACK. Set to 1 to output ACK data. Set to 0. Set to 1 to set the SCLi to remain low at the falling edge of the 9th bit of clock. Set to 1. Set to 1. Set to 0. Set to 0. Set to 0. Set to 0. Set to 0. Set to 0. Set to 0 when UART5 start and stop condition detection interrupts are used. Set to 0 when UART5 NACK interrupt is used. Set to 0 when UART6 start and stop condition detection interrupts are used. Set to 0 when UART6 NACK interrupt is used. Set to 0 when UART7 start and stop condition detection interrupts are used. Set to 0 when UART7 NACK interrupt is used. Set to 1 when UART0 start and stop condition detection interrupts are used. Set to 1 when UART1 start and stop condition detection interrupts are used. Slave UiSMR3 0, 2, 4 NODC CKPH DL2 to DL0 UiSMR4 STAREQ RSTAREQ STPREQ STSPSEL ACKD ACKC SCLHI SWC9 UCON U0IRS U1IRS U0RRM U1RRM CLKMD0 CLKMD1 RCSP 7 IFSR3A IFSR33 IFSR34 IFSR35 IFSR36 IFSR2A IFSR24 IFSR25 IFSR26 IFSR27 i = 0 to 2, 5 to 7 See Table 23.18 “I2C Mode Functions”. Set the amount of SDAi digital delay. Set to 1 to generate start condition. Set to 1 to generate restart condition. Set to 1 to generate stop condition. Set to 1 to output each condition. Select ACK or NACK. Set to 1 to output ACK data. Set to 1 to stop SCLi output when stop condition is detected. Set to 0. Set to 1. Set to 1. Set to 0. Set to 0. Set to 0. Set to 0. Set to 0. Set to 0. Set to 0 when UART5 start and stop condition detection interrupts are used. Set to 0 when UART5 NACK interrupt is used. Set to 0 when UART6 start and stop condition detection interrupts are used. Set to 0 when UART6 NACK interrupt is used. Set to 0 when UART7 start and stop condition detection interrupts are used. Set to 0 when UART7 NACK interrupt is used. Set to 1 when UART0 start and stop condition detection interrupts are used. Set to 1 when UART1 start and stop condition detection interrupts are used. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 530 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) In I2C mode, the functions and timings vary depending on the combination of the IICM2 bit in the UiSMR2 register and CKPH bit in the UiSMR3 register. Figure 23.19 shows Transfer to UiRB Register and Interrupt Timing. Refer to Figure 23.19 for the timing of transferring to the UiRB register, the bit position of the data stored in the UiRB register, types of interrupts, interrupt requests and DMA request generation timing. Table 23.18 “I2C Mode Functions” lists comparison of other functions in clock synchronous serial I/O mode with I2C mode. Table 23.18 Function I2C Mode Functions Clock Synchronous Serial I/O Mode (SMD2 to SMD0 = 001b, IICM = 0) I2C Mode (SMD2 to SMD0 = 010b, IICM = 1) IICM2 = 0 (NACK/ACK Interrupt) CKPH = 0 (No clock delay) CKPH = 1 (Clock delay) IICM2 = 1 (UART Transmit/Receive Interrupt) CKPH = 0 (No clock delay) CKPH = 1 (Clock delay) Start and stop condition detection interrupts Transmission, NACK interrupt (2) UARTi transmission Transmission started or completed (selected by UiIRS) Start condition detection or stop condition detection (See Figure 23.21 “STSPSEL Bit Functions”) No acknowledgment detection (NACK) Rising edge of SCLi 9th bit UARTi transmission Rising edge of SCLi 9th bit UARTi transmission Falling edge of SCLi next to the 9th bit Reception, ACK interrupt (2) UARTi reception Acknowledgment detection (ACK) When 8th bit received Rising edge of SCLi 9th bit CKPOL = 0 (rising edge) CKPOL = 1 (falling edge) CKPOL = 0 (rising edge) Rising edge of SCLi 9th bit CKPOL = 1 (falling edge) Not delayed 15 ns Possible when the corresponding port direction bit = 0 CKPOL = 0 (high) CKPOL = 1 (low) UARTi reception 1st to 8th bits of the received data are stored in bits 0 to 7 in the UiRB register. Delayed 200 ns UARTi reception Falling edge of SCLi 9th bit Timing for transferring data from UART reception shift register to UiRB register UARTi transmission output delay Noise filter width Read RXDi and SCLi pin levels Initial value of TXDi and SDAi outputs Initial and end values of SCLi DMA1, DMA3 Factor (2) Read received data Falling edge of SCLi 9th bit Falling and rising edges of SCLi 9th bit Always possible no matter how the corresponding port direction bit is set The value set in the port register before setting I2C mode (1) High Low High Low Acknowledgment detection (ACK) 1st to 8th bits of the received data are stored in bits 7 to 0 in the UiRB register. UARTi reception Falling edge of SCLi 9th bit 1st to 7th bits of the received data are stored in bits 6 to 0 in the UiRB register. 8th bit is stored into bit 8 in the UiRB register. When reading by reception interrupt, 1st to 7th bits of the received data are stored in bits 6 to 0 in the UiRB register. 8th bit is stored into bit 8 in the UiRB register. When reading by transmission interrupt, 1st to 8th bits are stored into bits 7 to 0 in the UiRB register. i = 0 to 2, 5 to 7 Notes: 1. Set the initial value of SDAi output while bits SMD2 to SMD0 in the UiMR register are 000b (serial interface disabled). 2. See Figure 23.19 “Transfer to UiRB Register and Interrupt Timing”. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 531 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) (1) IICM2 = 0 (ACK and NACK interrupts), CKPH = 0 (no clock delay) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 Initial value and end value are high. D8 (ACK, NACK) ACK interrupt (DMA1, DMA3 request), NACK interrupt Transfer to UiRB register b15 b9 b8 b7 b0 ... D8 D7 D6 D5 D4 D3 D2 D1 D0 UiRB register (2) IICM2 = 0, CKPH = 1 (clock delay) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit Initial value and end value are low. SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK) ACK interrupt (DMA1, DMA3 request), NACK interrupt Transfer to UiRB register b15 b9 b8 b7 b0 ... D8 D7 D6 D5 D4 D3 D2 D1 D0 UiRB register (3) IICM2 = 1 (UART transmit/receive interrupt), CKPH = 0 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 Initial value and end value are high. D8 (ACK, NACK) Receive interrupt Transmit (DMA1, DMA3 interrupt request) Transfer to UiRB register b15 b9 b8 b7 D0 b0 D7 D6 D5 D4 D3 D2 D1 ... UiRB register (4) IICM2 = 1, CKPH = 1 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit Initial value and end value are low. SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK) Transmit interrupt Receive interrupt (DMA1, DMA3 request) Transfer to UiRB register b15 b9 b8 b7 D0 b0 D7 D6 D5 D4 D3 D2 D1 Transfer to UiRB register b15 b9 b8 b7 b0 ... ... D8 D7 D6 D5 D4 D3 D2 D1 D0 i = 0 to 2, 5 to 7 UiRB register (read by reception interrupt) UiRB register (read by transmission interrupt) This diagram applies when the following condition is met. · The CKDIR bit in the UiMR register = 1 (slave selected) Figure 23.19 Transfer to UiRB Register and Interrupt Timing REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 532 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.3.1 Detection of Start and Stop Conditions Whether a start or a stop condition has been detected is determined. A start condition detect interrupt request is generated when the SDAi pin changes state from high to low while the SCLi pin is in the high state. A stop condition detect interrupt request is generated when the SDAi pin changes state from low to high while the SCLi pin is in the high state. Because the start and stop condition detect interrupts share an interrupt control register and vector, check the BBS bit in the UiSMR register to determine which interrupt source is requesting the interrupt. 3 to 6 cycles < setup time (1) 3 to 6 cycles < hold time (1) Setup time SCLi SDAi Hold time (Start condition) SDAi (Stop condition) i = 0 to 2, 5 to 7 When the PCLK1 bit in the PCLKR register is 1, this is the cycle count of f1SIO, and the PCLK1 bit is 0, the cycle count of f2SIO. Figure 23.20 Detection of Start and Stop Conditions 23.3.3.2 Output of Start and Stop Conditions A start condition is generated by setting the STAREQ bit in the UiSMR4 register (i = 0 to 2, 5 to 7) to 1 (start). A restart condition is generated by setting the RSTAREQ bit in the UiSMR4 register to 1 (start). A stop condition is generated by setting the STPREQ bit in the UiSMR4 register to 1 (start). The output procedure is as follows. (1) Set the STAREQ bit, RSTAREQ bit, or STPREQ bit to 1 (start). (2) Set the STSPSEL bit in the UiSMR4 register to 1 (output). The functions of the STSPSEL bit are shown in Table 23.19 and Figure 23.21. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 533 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Table 23.19 STSPSEL Bit Functions Function Output of pins SCLi and SDAi Start/stop condition interrupt request generation timing STSPSEL = 0 Output of transmit/receive clock and data Output of start/stop condition is accomplished by a program using ports (not automatically generated in hardware). Detection of start/stop condition STSPSEL = 1 Output of a start/stop condition according to bits STAREQ, RSTAREQ, and STPREQ Completion of start/stop condition generation (1) Slave mode CKDIR = 1 (external clock) STSPSEL bit SCLi SDAi 0 1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit Start condition detection interrupt Stop condition detection interrupt (2) Master mode CKDIR = 0 (internal clock), CKPH = 1 (clock delayed) STSPSEL bit Set to 1 by Set to 0 by a program a program SCLi SDAi Set to 1 by Set to 0 by a program a program 1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit Set STAREQ = 1 (start) i = 0 to 2, 5 to 7 Start condition detection interrupt Set STPREQ=1 (start) Stop condition detection interrupt Figure 23.21 STSPSEL Bit Functions 23.3.3.3 Arbitration Unmatching of the transmit data and SDAi pin input data is checked in synchronization with the rising edge of SCLi. Use the ABC bit in the UiSMR register to select the point at which the ABT bit in the UiRB register is updated. If the ABC bit is 0 (update per bit), the ABT bit is set to 1 at the same time unmatching is detected during check, and is set to 0 when not detected. If the ABC bit is set to 1, if unmatching is ever detected, the ABT bit is set to 1 (unmatching detected) at the falling edge of the clock pulse of the 9th bit. If the ABT bit needs to be updated per byte, set the ABT bit to 0 (undetected) after detecting acknowledge for the first byte, before transmitting/receiving the next byte. Setting the ALS bit in the UiSMR2 register to 1 (SDA output stop enabled) causes an arbitration-lost to occur, in which case the SDAi pin is placed in the high-impedance state at the same time the ABT bit is set to 1 (unmatching detected). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 534 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.3.4 Transmit/Receive Clock The transmit/receive clock is used to transmit/receive data as is shown in Figure 23.19. The CSC bit in the UiSMR2 register is used to synchronize an internally generated clock (internal SCLi) and an external clock supplied to the SCLi pin. If the CSC bit is set to 1 (clock synchronization enabled), if a falling edge on the SCLi pin is detected while the internal SCLi is high, the internal SCLi goes low, at which time the value of the UiBRG register is reloaded with and starts counting the lowlevel intervals. If the internal SCLi changes state from low to high while the SCLi pin is low, counting stops, and when the SCLi pin goes high, counting restarts. In this way, the UARTi transmit/receive clock is equivalent to AND of the internal SCLi and the clock signal applied to the SCLi pin. The transmit/receive clock works from a half cycle before the falling edge of the internal SCLi 1st bit to the rising edge of the 9th bit. To use this function, select an internal clock for the transmit/receive clock. The SWC bit in the UiSMR2 register determines whether the SCLi pin is fixed low or freed from lowlevel output at the falling edge of the 9th clock pulse. If the SCLHI bit in the UiSMR4 register is set to 1 (enabled), SCLi output is turned off (placed in the high-impedance state) when a stop condition is detected. When the SWC2 bit in the UiSMR2 register is set to 1 (0 output), a low-level signal can be forcibly output from the SCLi pin even while transmitting or receiving data. When the SWC2 bit is set to 0 (transmit/receive clock), a low-level signal output from the SCLi pin is cancelled, and the transmit/ receive clock is input and output. If the SWC9 bit in the UiSMR4 register is set to 1 (SCL hold low enabled) when the CKPH bit in the UiSMR3 register is 1, the SCLi pin is fixed low at the falling edge of the clock pulse next to the 9th. Setting the SWC9 bit to 0 (SCL hold low disabled) frees the SCLi pin from low-level output. 23.3.3.5 SDA Output The data written to bits 7 to 0 (D7 to D0) in the UiTB register is output in descending order from D7. The 9th bit (D8) is ACK or NACK. Set the initial value of SDAi transmit output when IICM is 1 (I2C mode) and bits SMD2 to SMD0 in the UiMR register are 000b (serial interface disabled). Bits DL2 to DL0 in the UiSMR3 register allow addition of no delays or a delay of 2 to 8 UiBRG count source clock cycles to the SDAi output. Setting the SDHI bit in the UiSMR2 register to 1 (SDA output disabled) forcibly places the SDAi pin in the high-impedance state. Do not write to the SDHI bit at the rising edge of the UARTi transmit/ receive clock. This is because the ABT bit may inadvertently be set to 1 (detected). 23.3.3.6 SDA Input When the IICM2 bit is 0, the 1st to 8th bits (D7 to D0) of received data are stored in bits 7 to 0 in the UiRB register. The 9th bit (D8) is ACK or NACK. When the IICM2 bit is 1, the 1st to 7th bits (D7 to D1) of received data are stored in bits 6 to 0 in the UiRB register and the 8th bit (D0) is stored in bit 8 in the UiRB register. Even when the IICM2 bit is 1, the same data as when the IICM2 bit is 0 can be read, provided the CKPH bit is 1. To read the data, read the UiRB register after the rising edge of 9th bit of the clock. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 535 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.3.7 ACK and NACK If the STSPSEL bit in the UiSMR4 register is set to 0 (start and stop conditions not generated) and the ACKC bit in the UiSMR4 register is set to 1 (ACK data output), the value of the ACKD bit in the UiSMR4 register is output from the SDAi pin. If the IICM2 bit is 0, a NACK interrupt request is generated if the SDAi pin remains high at the rising edge of the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDAi pin is low at the rising edge of the 9th bit of the transmit clock. If ACKi is selected to generate a DMA1 or DMA3 request source, a DMA transfer can be activated by detection of an acknowledge. 23.3.3.8 Initialization of Transmission/Reception If a start condition is detected while the STAC bit is 1 (UARTi initialization enabled), the serial interface operates as described below. • The transmit shift register is initialized, and the contents of the UiTB register are transferred to the transmit shift register. In this way, the serial interface starts sending data when the next clock pulse is applied. However, the UARTi output value does not change state and remains the same as when a start condition was detected until the first bit of data is output in synchronization with the input clock. • The receive shift register is initialized, and the serial interface starts receiving data when the next clock pulse is applied. • The SWC bit is set to 1 (SCL wait output enabled). Consequently, the SCLi pin is pulled low at the falling edge of the 9th clock pulse. Note that when UARTi transmission/reception is started using this function, the TI bit does not change state. Select the external clock as the transmit/receive clock to start UARTi transmission/ reception with this setting. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 536 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.4 Special Mode 2 Special mode 2 supports serial communication between one or multiple master devices and multiple slaves devices. The transmit/receive clock polarity and phase are selectable. Table 23.20 lists the Special Mode 2 Specifications. Table 23.20 Special Mode 2 Specifications Item Data format Transmit/receive clock Character data length: 8 bits Specification • Master mode The CKDIR bit in the UiMR register = 0 (internal clock): fj -------------------- fj = f1SIO, f2SIO, f8SIO, f32SIO 2(n + 1) n: Setting value of UiBRG register 00h to FFh • Slave mode The CKDIR bit = 1 (external clock selected): Input from the CLKi pin Transmit/receive control Controlled by input/output ports Transmission start Conditions To start transmission, satisfy the following requirements. (1) • The TE bit in the UiC1 register = 1 (transmission enabled) • The TI bit in the UiC1 register = 0 (data present in UiTB register) Reception start Conditions To start reception, satisfy the following requirements. (1) • The RE bit in the UiC1 register = 1 (reception enabled) • The TE bit = 1 (transmission enabled) • The TI bit = 0 (data present in the UiTB register) Transmit interrupt: One of the following can be selected. • The UiIRS bit in the UiC1 register= 0 (transmit buffer empty): When transferring data from the UiTB register to the UARTi transmit register (at start of transmission) • The UiIRS bit =1 (transmission completed): When the serial interface completed sending data from the UARTi transmit register Receive interrupt: • When transferring data from the UARTi receive register to the UiRB register (at completion of reception) Overrun error (2) This error occurs if the serial interface starts receiving the next unit of data before reading the UiRB register and receives the 7th bit of the next unit of data. Interrupt request generation timing Error detection Selectable functions • CLK polarity selection Data input/output can be chosen to occur synchronously with the rising or the falling edge of the transmit/receive clock. • LSB first, MSB first selection Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected. • Continuous receive mode selection Reception is enabled immediately by reading the UiRB register. • Switching serial data logic This function reverses the logic value of the transmit/receive data. • Clock phase setting Selectable from four combinations of transmit/receive clock polarities and phases i = 0 to 2, 5 to 7 Notes: 1. When an external clock is selected, either of the following conditions must be met. If the CKPOL bit in the UiC0 register is 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transmit/receive clock), the external clock is in high state; if the CKPOL bit is 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transmit/receive clock), the external clock is in low state. 2. If an overrun error occurs, the received data of the UiRB register will be undefined. The IR bit in the SiRIC register remains unchanged. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 537 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) P1_3 P1_2 P9_3 P7_2(CLK2) P7_1(RXD2) P7_0(TXD2) MCU (slave) P7_2(CLK2) P7_1(RXD2) P7_0(TXD2) MCU (master) P9_3 P7_2(CLK2) P7_1(RXD2) P7_0(TXD2) MCU (slave) Figure 23.22 Serial Bus Communication Control Example (UART2) Table 23.21 I/O Pin Functions in Special Mode 2 Pin Name I/O CLKi Output Input TXDi RXDi Output Input Input Function Clock output Clock input Serial data output Serial data input Input port Method of Selection The CKDIR bit in the UiMR register = 0 The CKDIR bit in the UiMR register = 1 Set the port direction bits sharing pins to 0. (Dummy data output when performing reception only.) Set the port direction bits sharing pins to 0. Set the port direction bits sharing pins to 0. (can be used as an input port when performing transmission only) i = 0 to 2, 5 to 7 Pins CLKi and CTSi/RTSi are not used. (They can be used as I/O ports.) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 538 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Table 23.22 Registers Used and Settings in Special Mode 2 Register UiTB UiRB (1) (2) Bits 0 to 7 0 to 7 OER 0 to 7 SMD2 to SMD0 CKDIR IOPOL CLK0, CLK1 CRS TXEPT CRD NCH CKPOL UFORM TE TI RE RI UjIRS UjRRM UiLCH UiERE 0 to 7 0 to 7 CKPH NODC 0, 2, 4 to 7 0 to 7 U0IRS U1IRS U0RRM U1RRM CLKMD0 CLKMD1, RCSP, 7 IFSR34 IFSR36 IFSR25 Set transmission data. Function Reception data can be read. Overrun error flag Set bit rate. Set to 001b. Set to 0 in master mode or 1 in slave mode. Set to 0. Select the count source for the UiBRG register. Invalid because CRD is 1 Transmit register empty flag Set to 1. Select TXDi pin output format. (1) Clock phases can be set in combination with the CKPH bit in the UiSMR3 register. Select the LSB first or MSB first. Set to 1 to enable transmission/reception. Transmit buffer empty flag Set to 1 to enable reception. Reception complete flag Select UARTj transmit interrupt source. Set to 1 to use continuous receive mode. Set to 1 to use inverted data logic. Set to 0. Set to 0. Set to 0. Clock phases can be set in combination with the CKPOL bit in the UiC0 register. Set to 0. Set to 0. Set to 0. Select UART0 transmit interrupt source. Select UART1 transmit interrupt source. Set to 1 to use continuous receive mode. Set to 1 to use continuous receive mode. Invalid because CLKMD1 is 0 Set to 0. Set to 0 to use UART5 transmit interrupt. Set to 0 to use UART6 transmit interrupt. Set to 0 to use UART7 transmit interrupt. UiBRG UiMR (2) UiC0 UiC1 UiSMR UiSMR2 UiSMR3 UiSMR4 UCON IFSR3A IFSR2A i = 0 to 2, 5 to 7 j = 2, 5 to 7 Notes: 1. The TXD2 pin is N channel open-drain output. No NCH bit in the U2C0 register is assigned. Only write 0 to this bit. 2. Set the bits not listed above to 0 when writing to the registers in special mode 2. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 539 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.4.1 Clock Phase Setting Function One of four combinations of transmit/receive clock phases and polarities can be selected using the CKPH bit in the UiSMR3 register and the CKPOL bit in the UiC0 register. Make sure the transmit/receive clock polarity and phase are the same for the master and salve devices to be used for communication. Figure 23.23 shows the Transmission and Reception Timing in Master Mode (Internal Clock). Figure 23.24 shows the Transmission and Reception Timing (CKPH = 0) in Slave Mode (External Clock) while Figure 23.25 shows the Transmission and Reception Timing (CKPH = 1) in Slave Mode (External Clock). High Clock output (CKPOL = 0, CKPH = 0) Low Clock output High (CKPOL = 1, CKPH = 0) Low High Clock output (CKPOL = 0, CKPH = 1) Low High Clock output (CKPOL = 1, CKPH = 1) Low Data output timing High Low D0 D1 D2 D3 D4 D5 D6 D7 Data input timing Figure 23.23 Transmission and Reception Timing in Master Mode (Internal Clock) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 540 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) High Slave control input Low High Clock input (CKPOL = 0, CKPH = 0) Low High Clock input (CKPOL = 1, CKPH = 0) Low Data output timing (1) High Low undefined D0 D1 D2 D3 D4 D5 D6 D7 Data input timing Note: 1. UART2 output is N-channel open-drain and must be pulled-up externally. Figure 23.24 Transmission and Reception Timing (CKPH = 0) in Slave Mode (External Clock) High Slave control input Low Clock input (CKPOL=0, CKPH=1) High Low Clock input (CKPOL=1, CKPH=1) High Low Data output timing (1) High Low D0 D1 D2 D3 D4 D5 D6 D7 Data input timing Note: 1. UART2 output is N-channel open-drain and must be pulled-up externally. Figure 23.25 Transmission and Reception Timing (CKPH = 1) in Slave Mode (External Clock) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 541 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.5 Special Mode 3 (IE mode) In this mode, one bit of IEBus is approximated by one byte of UART mode waveform. Table 23.23 lists the Registers Used and Settings in IE Mode. Figure 23.26 shows the Bus Collision Detect Function-Related Bits. If the TXDi pin (i = 0 to 2, 5 to 7) output level and RXDi pin input level do not match, a UARTi bus collision detect interrupt request is generated. Use bits IFSR26 and IFSR27 in the IFSR2A register to enable the UART0/UART1 bus collision detect function. Table 23.23 Register UiTB UiRB (3) UiBRG UiMR Registers Used and Settings in IE Mode Bits 0 to 8 0 to 8 OER, FER, PER, SUM 0 to 7 SMD2 to SMD0 CKDIR STPS PRY PRYE IOPOL CLK1, CLK0 CRS TXEPT CRD NCH CKPOL UFORM TE TI RE RI UjIRS (1) Function Set transmission data. Reception data can be read. Error flag Set bit rate. Set to 110b. Select internal clock or external clock. Set to 0. Invalid because PRYE is 0 Set to 0. Select the TXD and RXD input/output polarity. Select the count source for the UiBRG register. Invalid because CRD is 1 Transmit register empty flag Set to 1. Select TXDi pin output format. (2) Set to 0. Set to 0. Set to 1 to enable transmission. Transmit buffer empty flag Set to 1 to enable reception. Reception complete flag Select the source of UARTj transmit interrupt. Set to 0. Set to 0. Select the sampling timing to detect a bus collision. Set to 1 to use the auto clear function of transmit enable bit. Select the transmit start condition. Set to 0. Set to 0. Set to 0. Set to 1. Select the source of UART0/UART1 transmit interrupt. Set to 0. Invalid because CLKMD1 is 0 Set to 0. UiC0 UiC1 UjRRM (1), UiLCH, UiERE UiSMR 0 to 3, 7 ABSCS ACSE SSS UiSMR2 0 to 7 UiSMR3 0 to 7 UiSMR4 0 to 7 IFSR2A IFSR26, IFSR27 UCON U0IRS, U1IRS U0RRM, U1RRM CLKMD0 CLKMD1, RCSP, 7 i = 0 to 2, 5 to 7 Notes: 1. 2. 3. Set bits 4 and 5 in registers U0C0 and U1C1 to 0. Bits U0IRS, U1IRS, U0RRM, and U1RRM are in the UCON register. The TXD2 pin is N channel open-drain output. Nothing is assigned in the NCH bit in the U2C0 register. If necessary, set to 0. Set the bits not listed above to 0 when writing to the registers in IE mode. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 542 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) (1) ABSCS bit in UiSMR register (bus collision detect sampling clock select) (i = 0 to 2, 5 to 7) When ABSCS is 0, bus collision is determined at the rising edge of the transmit/receive clock. Transmit/receive clock ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP TXDi RXDi Trigger signal is applied to the TAjIN pin Timer Aj When ABSCS is 1, bus collision is determined when timer Aj (one-shot timer mode) underflows. Timer Aj: Timer A3 in UART0; timer A4 in UART1; timer A0 in UART2 timer A0 in UART5; timer A3 in UART6; timer A4 in UART7 (2) ACSE bit in UiSMR register (auto clear of transmit enable bit) Transmit/receive clock ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP TXDi RXDi IR bit in UiBCNIC and BCNIC register TE bit in UiC1 register When ACSE bit is 1 (automatically clear when bus collision occurs), the TE bit is cleared to 0 (transmission disabled) when the IR bit in the UiBCNIC register is 1 (unmatching detected). (3) SSS bit in the UiSMR register (transmit start condition select) When SSS bit is 0, the serial interface starts sending data one transmit/receive clock cycle after the transmission enable condition is met. Transmit/receive clock ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP TXDi Transmit enable conditions are met. When SSS bit is 1, the serial interface starts sending data at the rising edge of RXDi. (1) CLKi ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP TXDi RXDi (2) Notes : 1. The falling edge of RXDi when IOPOL is 0; the rising edge of RXDi when IOPOL is 1. 2. The transmit conditions must be met before the falling edge of RXD. The above diagram applies when IOPOL is 1 (reversed). i = 0 to 2, 5 to 7 Figure 23.26 Bus Collision Detect Function-Related Bits REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 543 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.6 Special Mode 4 (SIM Mode) (UART2) SIM interface devices can communicate in UART mode. Both direct and inverse formats are available. The TXD2 pin outputs a low-level signal when a parity error is detected. Table 23.24 lists the SIM Mode Specifications. Table 23.25 lists the Registers Used and Settings in SIM Mode. Table 23.24 SIM Mode Specifications Item Data formats Transmit/receive clock Specification • Direct format • Inverse format • The CKDIR bit in the U2MR register = 0 (internal clock): fi/(16(n + 1)) fi = f1SIO, f2SIO, f8SIO, f32SIO n = Setting value of the U2BRG register 00h to FFh • The CKDIR bit = 1 (external clock): fEXT/(16(n + 1)) fEXT = input from the CLK2 pin n = Setting value of the U2BRG register 00h to FFh To start transmission, satisfy the following requirements. • The TE bit in the U2C1 register = 1 (transmission enabled) • The TI bit in the U2C1 register = 0 (data present in the U2TB register) To start reception, satisfy the following requirements. • The RE bit in the U2C1 register = 1 (reception enabled) • Start bit detection Transmission start conditions Reception start conditions Interrupt request generation timing (2) • Transmission When the serial interface completed sending data from the UART2 transmit register (the U2IRS bit =1) • Reception When transferring data from the UART2 receive register to the U2RB register (at completion of reception) Error detection • Overrun error (1) This error occurs if the serial interface starts receiving the next unit of data before reading the U2RB register and receives the bit one before the last stop bit of the next unit of data. • Framing error (3) This error occurs when the number of stop bits set is not detected. • Parity error (3) During reception, if a parity error is detected, parity error signal is output from the TXD2 pin. During transmission, a parity error is detected by the level of input to the RXD2 pin when a transmission interrupt occurs. • Error sum flag This flag is set to 1 when an overrun, framing, or parity error occurs. Notes: 1. If an overrun error occurs, the received data of the U2RB register will be undefined. The IR bit in the S2RIC register remains unchanged. 2. After reset, a transmit interrupt request is generated by setting the U2IRS bit to 1 (transmission completed) and the U2ERE bit to 1 (error signal output) in the U2C1 register. Therefore, when using SIM mode, set the IR bit to 0 (interrupt not requested) after setting the bits. 3. The timing that the framing error flag and the parity error flag are set is detected when data is transferred from the UART2 receive register to the U2RB register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 544 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Table 23.25 Registers Used and Settings in SIM Mode Register U2TB (1) Bits 0 to 7 0 to 7 OER,FER,PER,SUM 0 to 7 SMD2 to SMD0 CKDIR STPS PRY PRYE IOPOL CLK0,CLK1 CRS TXEPT CRD NCH CKPOL UFORM TE TI RE RI U2IRS U2RRM U2LCH U2ERE 0 to 3 Set transmission data. Function Reception data can be read. Error flag Set bit rate. Set to 101b. Select the internal clock or external clock. Set to 0. Set to 1 in direct format or 0 in inverse format. Set to 1. Set to 0. Select the count source for the U2BRG register. Invalid because CRD is 1 Transmit register empty flag Set to 1. Set to 0. Set to 0. Set to 0 in direct format or 1 in inverse format. Set to 1 to enable transmission. Transmit buffer empty flag Set to 1 to enable reception. Reception complete flag Set to 1. Set to 0. Set to 0 in direct format or 1 in inverse format. Set to 1. Set to 0. U2RB (1) U2BRG U2MR U2C0 U2C1 U2SMR (1) U2SMR2 0 to 7 Set to 0. U2SMR3 0 to 7 Set to 0. U2SMR4 0 to 7 Set to 0. Note: 1. Set the bits not listed above to 0 when writing to the registers in SIM mode. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 545 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) (1) Transmit Timing Transmit/receive clock TE bit in U2C1 register TI bit in U2C1 register 1 0 1 0 Tc Data is written to the U2TB register. (Note 1) Data is transferred from the U2TB register to the UART2 transmit register TXD2 Parity error signal returned from receiving end Start bit ST D0 D1 D2 D3 D4 D5 D6 Parity bit D7 P SP Stop bit ST D0 D1 D2 D3 D4 D5 D6 D7 P SP A low-level signal is applied from the SIM card due to a parity error. ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP RXD2 pin level (2) TXEPT bit in U2C0 register IR bit in S2TIC register 1 0 1 0 An interrupt routine detects the level. An interrupt routine detects the level. Set to 0 by an interrupt request acknowledgement or by a program. The above timing diagram applies when data is transmitted in the direct format. • The STPS bit in the U2MR register = 0 (1 stop bit) • The PRY bit in the U2MR register = 1 (even parity) • The UFORM bit in the U2C0 register = 0 (LSB first) • The U2LCH bit in the U2C1 register = 0 (no reverse) • The U2IRS bit in the U2C1 register = 1 (transmit completed) TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : Frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO) fEXT : Frequency of U2BRG count source (external clock) n : Value set to U2BRG (2) Receive Timing Transmit/receive clock 1 0 Start bit ST D0 D1 Tc RE bit in U2C1 register Transmit waveform from transmitting end Parity bit D2 D3 D4 D5 D6 D7 P SP Stop bit ST D0 D1 D2 D3 D4 D5 D6 D7 P SP TXD2 RXD2 pin level (3) ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 TXD2 provides low-level output due to a parity error. D2 D3 D4 D5 D6 D7 P SP RI bit in U2C1 register 1 0 1 Read the U2RB register. IR bit in S2RIC register 0 Set to 0 by an interrupt request acknowledgement or by a program. The above timing diagram applies when data is received in the direct format. • The STPS bit in the U2MR register = 0 (1 stop bit) • The PRY bit in the U2MR register = 1 (even parity) • The UFORM bit in the U2C0 register = 0 (LSB first) • The U2LCH bit in the U2C1 register = 0 (no reverse) • The U2IRS bit in the U2C1 register = 1 (transmit completed) TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : Frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO) fEXT : Frequency of U2BRG count source (external clock) n : Value set to U2BRG Notes: 1. Data transmission starts when BRG overflows after a value is set in the U2TB register on the rising edge of the TI bit. 2. Because pins TXD2 and RXD2 are connected, a composite waveform, consisting of the transmit waveform from the TXD2 pin and parity error signal from the receiving end, is generated. 3. Because pins TXD2 and RXD2 are connected, a composite waveform, consisting of the transmit waveform from the transmitting end and parity error signal from the TXD2 pin, is generated. Figure 23.27 Transmit/Receive Timing in SIM Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 546 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Figure 23.28 shows an Example of SIM Interface Connection. Connect TXD2 and RXD2, and then connect a pull-up resistor. MCU SIM card TXD2 RXD2 Figure 23.28 Example of SIM Interface Connection 23.3.6.1 Parity Error Signal Output The parity error signal is enabled by setting the U2ERE bit in the U2C1 register to 1 (error signal output). The parity error signal is output when a parity error is detected while receiving data. A low-level signal is output from the TXD2 pin in the timing shown in Figure 23.29. If the U2RB register is read while outputting a parity error signal, the PER bit is cleared to 0 (no parity error) and at the same time the TXD2 output again goes high. When transmitting, a transmission complete interrupt request is generated at the falling edge of the transmit/receive pulse that immediately follows the stop bit. Therefore, whether or not a parity error signal has been returned can be determined by reading the port that shares the RXD2 pin in a transmission complete interrupt routine. Transmit/receive clock High Low RXD2 High Low ST D0 D1 D2 D3 D4 D5 D6 D7 P SP TXD2 RI bit in U2C1 register High Low 1 0 (NOTE 1) This timing diagram applies to the case where the direct format is implemented. Note: 1. The output of the MCU is in the high-impedance state (pulled up externally). ST : Start bit P : Even parity SP : Stop bit Figure 23.29 Parity Error Signal Output Timing REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 547 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.3.6.2 Format Two formats are available: direct format and inverse format. For direct format, set the PRYE bit in the U2MR register to 1 (parity enabled), the PRY bit to 1 (even parity), the UFORM bit in the U2C0 register to 0 (LSB first) and the U2LCH bit in the U2C1 register to 0 (not inverted). When data is transmitted, the contents of the U2TB register are transmitted with the even-numbered parity, starting from D0. When data is received, the receive data are stored in the U2RB register, starting from D0. The even-numbered parity is used to determine when a parity error occurs. For inverse format, set the PRYE bit to 1, the PRY bit to 0 (odd parity), the UFORM bit to 1 (MSB first), and the U2LCH bit to 1 (inverted). When data is transmitted, the contents of the U2TB register are logically inverted and are transmitted with odd-numbered parity, starting from D7. When data is received, the receive data is logically inverted and stored in the U2RB register, starting from D7. The odd-numbered parity is used to determine when a parity error occurs. Figure 23.30 shows SIM Interface Format. (1) Direct format High Low High Low Transmit/receive clock TXD2 D0 D1 D2 D3 D4 D5 D6 D7 P P : Even parity (2) Inverse format Transmit/receive clock TXD2 High Low High Low D7 D6 D5 D4 D3 D2 D1 D0 P P : Odd parity Figure 23.30 SIM Interface Format REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 548 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.4 Interrupts UART0 to UART2 and UART5 to UART7 include interrupts by transmission, reception, ACK, NACK, start/ stop condition detection, and bus collision detection. 23.4.1 Interrupt Related Registers Refer to operation examples in each mode for interrupt sources and interrupt request generation timing. For the details of interrupt control, refer to 14.7 “Interrupt Control”. Table 23.26 lists UART0 to UART2, UART5 to UART7 Interrupt Related Registers. Table 23.26 UART0 to UART2, UART5 to UART7 Interrupt Related Registers Address 0046h 0047h 004Ah 004Fh 0050h 0051h 0052h 0053h 0054h 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0205h 0206h Register Name UART1 Bus Collision Detection Interrupt Control Register UART0 Bus Collision Detection Interrupt Control Register UART2 Bus Collision Detection Interrupt Control Register UART2 Transmit Interrupt Control Register UART2 Receive Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register UART5 Bus Collision Detection Interrupt Control Register UART5 Transmit Interrupt Control Register UART5 Receive Interrupt Control Register UART6 Bus Collision Detection Interrupt Control Register UART6 Transmit Interrupt Control Register UART6 Receive Interrupt Control Register UART7 Bus Collision Detection Interrupt Control Register UART7 Transmit Interrupt Control Register UART7 Receive Interrupt Control Register Interrupt Source Select Register 3 Interrupt Source Select Register 2 Register Symbol After Reset U1BCNIC XXXX X000b U0BCNIC BCNIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC U5BCNIC S5TIC S5RIC U6BCNIC S6TIC S6RIC U7BCNIC S7TIC S7RIC IFSR3A IFSR2A XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b 00h 00h REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 549 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) Some interrupts of UART0 to UART2 and UART5 to UART7 share interrupt vectors and interrupt control registers with other peripheral functions. When using these interrupts, select them by interrupt source select registers. Table 23.27 lists Interrupt Select in UART0 to UART2 and UART5 to UART7. Table 23.27 Interrupt Select in UART0 to UART2 and UART5 to UART7 Interrupt Source UART0 start/stop condition detection, bus collision detection UART1 start/stop condition detection, bus collision detection UART5 start/stop condition detection, bus collision detection UART5 transmission, NACK UART6 start/stop condition detection, bus collision detection UART6 transmission, NACK UART7 start/stop condition detection, bus collision detection UART7 transmission, NACK Interrupt Source Select Register Settings Register Bit Setting Value IFSR2A IFSR26 1 IFSR2A IFSR27 1 IFSR3A IFSR33 0 IFSR3A IFSR34 0 IFSR3A IFSR35 0 IFSR3A IFSR36 0 IFSR2A IFSR24 0 IFSR2A IFSR25 0 An interrupt request may be generated by bit contents change in the following modes. • Special mode 1 (I2C mode) Set the IR bit in the interrupt control register of UARTi to 0 (interrupt not requested), when the following bits are changed: Bits SMD2 to SMD0 in the UiMR register, the IICM bit in the UiSMR register, the IICM2 bit in the UiSMR2 register, the CKPH bit in the UiSMR3 register • Special mode 4 (SIM mode) After reset, when bits U2IRS and U2ERE in the U2C1 register are set to 1 (transmission completed) and 1 (interrupt not requested) respectively, a transmission interrupt request is generated. In SIM mode, set these bits first, and then set the IR bit in the S2TIC register to 0 (interrupt not requested). 23.4.2 Reception Interrupt • The case that bits SMD2 to SMD0 in the UiMR register are not set to 010b (I2C mode) When the RI bit in the UiC1 register is changed from 0 (no data in the UiRB register) to 1 (data present in the UiRB register), the IR bit in the SiRIC register is automatically set to 1 (interrupt requested). If an overrun error occurs (when the RI bit is 1, the next data is received), the RI bit remains 1, and therefore, the IR bit in the SiRIC register remains unchanged. • The case that bits SMD2 to SMD0 in the UiMR register are set to 010b (I2C mode) When the RI bit in the UiC1 register is changed from 0 (no data in the UiRB register) to 1 (data present in the UiRB register), the IR bit in the SiRIC register is automatically set to 1 (interrupt requested). When an overrun error occurs, the IR bit in the SiRIC register also becomes 1. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 550 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.5 Notes on Serial Interface UARTi (i = 0 to 2, 5 to 7) If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is 1 (threephase output forcible cutoff by input on SD pin enabled), the following pins go to high-impedance state: P7_2/CLK2/TA1OUT/V, P7_3/ CTS2 / RTS2 /TA1IN/ V, P7_4/TA2OUT/W, P7_5/TA2IN/ W, P8_0/ TA4OUT/RXD5/SCL5/U, P8_1/TA4IN/CTS5/RTS5/U 23.5.1 23.5.1.1 Clock Synchronous Serial I/O Transmission/Reception When the RTS function is used with an external clock, RTSi pin (i = 0 to 2, 5 to 7) outputs a low-level signal, which informs the transmitting side that the MCU is ready for a receive operation. The RTSi pin outputs a high-level signal when a receive operation starts. Therefore, a transmit timing and receive timing can be synchronized by connecting the RTSi pin to the CTSi pin of the transmitting side. The RTS function is disabled when an internal clock is selected. 23.5.1.2 Transmission If an external clock is selected, the following conditions must be met while the external clock is held high when the CKPOL bit in the UiC0 register (i = 0 to 2, 5 to 7) is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the transmit and receive clock), or while the external clock is held low when the CKPOL bit is set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the transmit and receive clock). • The TE bit in the UiC1 register is 1 (transmission enabled). • The TI bit in the UiC1 register is 0 (data present in the UiTB register). • When CTS function is selected, input on the CTSi pin is low. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 551 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.5.1.3 Reception In clock synchronous serial I/O mode, the shift clock is generated by activating a transmitter. Set the UARTi-associated registers for a transmit operation even if the MCU is used for receive operation only. Dummy data is output from the TXDi pin (i = 0 to 2, 5 to 7) while receiving. When an internal clock is selected, the shift clock is generated by setting the TE bit in the UiC1 register to 1 (transmission enabled) and placing dummy data in the UiTB register. When an external clock is selected, set the TE bit to 1 (transmission enabled), place dummy data in the UiTB register, and input an external clock to the CLKi pin to generate the shift clock. If data is received consecutively, an overrun error occurs when the RI bit in the UiC1 register is set to 1 (data present in the UiRB register) and the next receive data is received in the UARTi receive register. And then, the OER bit in the UiRB register is set to 1 (overrun error occurred). At this time, the UiRB register is undefined. When an overrun error occurs, program the transmitting and receiving sides to retransmit the previous data. If an overrun error occurs, the IR bit in the SiRIC register remains unchanged. To receive data consecutively, set dummy data in the low-order byte in the UiTB register per each receive operation. When an external clock is selected, the following conditions must be met while the external clock is held high when the CKPOL bit is 0 (transmit data output at the falling edge and receive data input at the rising edge of the serial clock), or while the external clock is held low when the CKPOL bit is 1 (transmit data output at the rising edge and receive data input at the falling edge of the serial clock). • The RE bit in the UiC1 register is 1 (reception enabled). • The TE bit in the UiC1 register is 1 (transmission enabled). • The TI bit in the UiC1 register is 0 (data present in the UiTB register). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 552 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7) 23.5.2 23.5.2.1 UART (Clock Asynchronous Serial I/O) Mode Transmission/Reception When the RTS function is used with an external clock, the RTSi pin (i = 0 to 2, 5 to 7) outputs a lowlevel signal, which informs the transmitting side that the MCU is ready for a receive operation. The RTSi pin outputs a high-level signal when a receive operation starts. Therefore, a transmit timing and receive timing can be synchronized by connecting the RTSi pin to the CTSi pin of the transmitting side. The RTS function is disabled when an internal clock is selected. 23.5.2.2 Transmission When an external clock is selected, the following conditions must be met while the external clock is held high when the CKPOL bit in the UiC0 register (i = 0 to 2, 5 to 7) is 0 (transmit data output at the falling edge and receive data input at the rising edge of the transmit and receive clock), or while the external clock is held low when the CKPOL bit is 1 (transmit data output at the rising edge and receive data input at the falling edge of the transmit and receive clock). • The TE bit in the UiC1 register is 1 (transmission enabled). • The TI bit in the UiC1 register is 0 (data present in the UiTB register). • When CTS function is selected, input on the CTSi pin is low. 23.5.3 23.5.3.1 Special Mode 1 (I2C Mode) Generation of Start and Stop Conditions When generating start, stop and restart conditions, set the STSPSEL bit in the UiSMR4 register (i = 0 to 2, 5 to 7) to 0 and wait for more than half cycle of the transmit and receive clock. Then set each condition generation bit (STAREQ, RSTAREQ and STPREQ) from 0 to 1. 23.5.3.2 IR Bit Set the following bits first, and then set the IR bit in the UARTi interrupt control registers to 0 (interrupt not requested). Bits SMD2 to SMD0 in the UiMR register, the IICM bit in the UiSMR register, the IICM2 bit in the UiSMR2 register, the CKPH bit in the UiSMR3 register 23.5.4 Special Mode 4 (SIM Mode) After reset, a transmit interrupt request is generated by setting bits U2IRS and U2ERE in the U2C1 register to 1 (transmission completed) and 1 (error signal output), respectively. Therefore, when using SIM mode, make sure to set the IR bit to 0 (interrupt not requested) after setting these bits. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 553 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 24. Serial Interface SI/O3 and SI/O4 24. Serial Interface SI/O3 and SI/O4 Note The 80-pin package does not have the SIN3 pin for SI/O3. SI/O3 is used for transmission only. No reception is possible. 24.1 Introduction SI/O3 and SI/O4 are dedicated clock-synchronous serial I/O ports. Table 24.1 lists SI/O3 and SI/O4 Specifications. Figure 24.1 shows SI/O3 and SI/O4 Block Diagram, and Table 24.2 lists the Input/Output Pins. Table 24.1 SI/O3 and SI/O4 Specifications Item Data format Transmit/Receive clocks Specification Character length: 8 bits • The SMi6 bit in the SiC register = 1 (internal clock): fj -------------------2( n + 1) Transmission/reception start condition Interrupt request generation timing Selectable functions fj = f1SIO, f8SIO, f32SIO n = setting value of the SiBRG register 00h to FFh The SMi6 bit = 0 (external clock): Input from the CLKi pin (1) Before transmission/reception starts, satisfy the following requirements. Write transmit data into the SiTRR register. (2) • SMi4 bit in the SiC register = 0 The rising edge of the last transmit/receive clock • the SMi4 bit = 1 The falling edge of the last transmit/receive clock • CLK polarity selection Whether data is output/input at the rising or falling edge of the transmit/ receive clock can be selected. • LSB first or MSB first selection Whether to start transmitting/receiving data from bit 0 or from bit 7 can be selected. • SOUTi initial value setting function When the SMi6 bit in the SiC register = 0 (external clock), the SOUTi pin output level while not transmitting can be selected. • SOUTi state selection after transmission Whether to set to high-impedance or retain the last bit level can be selected when the SMi6 bit in the SiC register is 1 (internal clock). i = 3, 4 Notes: 1. The data is shifted every time the external clock is input. When completing data transmission/ reception of the 8th bit, read or write into the SiTRR register before inputting the clock for the next data transmission/reception. 2. When the SMi6 bit in the SiC register is 0 (external clock), follow the procedure described below. • If the SMi4 bit in the SiC register is 0, write transmit data into the SiTRR register while input to the CLKi pin is high. • If the SMi4 bit is 1, write transmit data into the SiTRR register while input to the CLKi pin is low. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 554 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 24. Serial Interface SI/O3 and SI/O4 f1 fOCO-F 0 1 SM22 f1SIO f2SIO 1/2 1/8 0 1 PCLK1 1/4 0 SMi4 CLKi CLK polarity recversing circuit Clock source select SMi1 to SMi0 00b f8SIO 01b Synchronous 1/2 1/(n+1) circuit f32SIO 10b SiBRG register 1 SMi3 SMi6 SMi6 S I/O counter i SI/Oi interrupt (IR bit in the SiIC register) SMi2 SMi3 SOUTi SINi SMi5 LSB MSB SiTRR register i = 3, 4 n: Value set in the SiBRG register Figure 24.1 SI/O3 and SI/O4 Block Diagram Table 24.2 Input/Output Pins Pin Name Input/Output Function Selecting Method CLKi Output Transmit/receive clock output SMi3 bit in the SiC register = 1 SMi6 bit in the SiC register = 1 Input Transmit/receive clock input SMi3 bit in the SiC register = 1 SMi6 bit in the SiC register = 0 Port direction bits sharing pins = 0 SOUTi Output Serial data output SMi3 bit in the SiC register = 1 SMi2 bit in the SiC register = 0 SINi Input Serial data input SMi3 bit in the SiC register = 1 Port direction bits sharing pins = 0 (Dummy data is input only when transmitting.) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 555 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 24. Serial Interface SI/O3 and SI/O4 24.2 Registers Table 24.3 lists registers associated with SI/O3 and SI/O4. Set the SM22 bit in the S34C2 register before setting other registers associated with SI/O3 and SI/O4. After changing the SM22 bit, set other registers associated with SI/O3 and SI/O4 again. Table 24.3 Register Structure Address 0012h 0270h 0272h 0273h 0274h 0276h 0277h 0278h Register Name Peripheral Clock Select Register SI/O3 Transmit/Receive Register SI/O3 Control Register SI/O3 Bit Rate Register SI/O4 Transmit/Receive Register SI/O4 Control Register SI/O4 Bit Rate Register SI/O3, 4 Control Register 2 Register Symbol PCLKR S3TRR S3C S3BRG S4TRR S4C S4BRG S34C2 After Reset 0000 0011b XXh 0100 0000b XXh XXh 0100 0000b XXh 00XX X0X0b REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 556 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 24. Serial Interface SI/O3 and SI/O4 24.2.1 Peripheral Clock Select Register (PCLKR) Peripheral Clock Select Register b7 b6 b5 b4 b3 b2 b1 b0 00 000 Symbol PCLKR Bit Symbol Bit Name Address 0012h Function After Reset 0000 0011b RW PCLK0 Timers A and B clock select bit (clock source for timers A and B, the dead time timer, and muliti-master I2C-bus interface) SI/O clock select bit (clock source for UART0 to UART2, UART5 to UART7, SI/O3, and SI/O4) Reserved bits Clock output function extension bit (valid in single-chip mode) Reserved bits 0: f2TIMAB/f2IIC 1: f1TIMAB/f1IIC RW PCLK1 0: f2SIO 1: f1SIO RW — (b4-b2) PCLK5 — (b7-b6) Set to 0 0: Selected by bits CM01 to CM00 in the CM0 register 1: Output f1 Set to 0 RW RW RW Rewrite the PCLKR register after setting the PRC0 bit in the PRCR register to 1 (write enabled). 24.2.2 SI/O Transmit/Receive Register (SiTRR) (i = 3, 4) SI/Oi Transmit/Receive Register (i = 3, 4) b7 b0 Symbol S3TRR S4TRR Address 0270h 0274h Function After Reset Undefined Undefined RW RW Transmission/reception starts by writing transmit data into this register. After transmission/reception completes, receive data can be read. Write into the SiTRR register while serial interface is neither transmitting nor receiving. Write the value into the SiTRR register every time one byte data is received even when data is only received. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 557 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 24. Serial Interface SI/O3 and SI/O4 24.2.3 SI/Oi Control Register (SiC) (i = 3, 4) SI/Oi Control Register (i = 3, 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol S3C S4C Bit symbol SMi0 Internal synchronous clock select bit SMi1 SMi2 SOUTi output disable bit Bit Name Address 0272h 0276h Function b1 b0 0 0 : Selecting f1SIO or f2SIO 0 1 : Selecting f8SIO 1 0 : Selecting f32SIO 1 1 : Do not set After Reset 0100 0000b 0100 0000b RW RW 0 : SOUTi output enabled 1 : SOUTi output disabled (high-impedance) 0 : Input/output port serial interface disabled 1 : SOUTi output, CLKi function serial interface enabled 0 : Transmit data is output at falling edge of transmit/receive clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transmit/receive clock and receive data is input at falling edge 0 : LSB first 1 : MSB first 0 : External clock 1 : Internal clock Valid when SMi6 = 0 0 : Low output 1 : High output RW SMi3 SI/Oi port select bit RW SMi4 CLK polarity select bit RW SMi5 Bit order select bit Synchronous clock select bit SOUTi initial output set bit RW SMi6 RW SMi7 RW Write into the SiC register by the next instruction after setting the PRC2 bit in the PRCR register to 1 (write enabled). SMi1-SMi0 (Internal Synchronous Clock Select Bit) (b1-b0) Select f1SIO or f2SIO by the PCLK1 bit in the PCLKR register. Set the SiBRG register when changing bits SMi1 to SMi0. SMi2 (SOUTi Output Disable Bit) (b2) When the SMi2 bit is set to 1 (SOUTi output disabled), the target pin goes to high-impedance state regardless of which function of the pin is being used. SMi7 (SOUTi Initial Value Set Bit) (b7) Set the SMi7 bit when the SMi3 bit is 0 (input/output port, serial interface disabled). The level selected by the SMi7 bit is output from the SOUTi pin by setting the SMi3 bit to 1 and SMi2 bit to 0 (SOUTi output). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 558 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 24. Serial Interface SI/O3 and SI/O4 24.2.4 SI/Oi Bit Rate Register (SiBRG) (i = 3, 4) SI/Oi Bit Rate Register (i = 3, 4) b7 b0 Symbol S3BRG S4BRG Function Address 0273h 0277h After Reset Undefined Undefined Setting Range 00h to FFh RW WO SiBRG divides the count source by n + 1 where n = set value Use MOV instruction to write into the SiBRG register. Write into the SiBRG register after setting bits SMi1 to SMi0 in the SiC register and while serial interface is neither transmitting nor receiving. 24.2.5 SI/O3, 4 Control Register 2 (S34C2) SI/O3, 4 Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol S34C2 Bit Symbol — (b0) — (b1) SM22 — (b5-b3) SM26 Bit Name Reserved bit Address 0278h Function Set to 0 After Reset 00XX X0X0b RW RW No register bit. If necessary, set to 0. Read as undefined value SI/O3, SI/O4 before-division clock select bit 0: f1 1: fOCO-F — RW No register bits. If necessary, set to 0. Read as undefined value SOUT3 state after transmission 0 : High-impedance 1 : Last bit level retained SOUT4 state after transmission 0 : High-impedance 1 : Last bit level retained — SOUT3 output control bit RW SM27 SOUT4 output control bit RW SM22 (SI/O3, SI/O4 Before-division Clock Select Bit) (b2) Set the SM22 bit while transmission/reception of SI/O3 and SI/O4 stops. Set the SM22 bit before setting other registers associated with SI/O3 and SI/O4. After changing the SM22 bit, set other registers associated with SI/O3 and SI/O4 again. SM26 (SOUT3 Output Control Bit) (b6) SM27 (SOUT4 Output Control Bit) (b7) Bits SM26 and SM27 are valid when the SMi6 bit in the SiC register is set to 1 (internal clock). Set the SMi3 bit in the SiC register to 1 (serial interface enabled) after setting bits SM26 and SM27. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 559 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 24. Serial Interface SI/O3 and SI/O4 24.3 24.3.1 Operations Basic Operations SI/Oi transmits and receive data simultaneously. The SiTRR register is not divided into the register for transmission/reception and buffer. Write transmit data into the SiTRR register while transmission/ reception stops. Read receive data from the SiTRR register while transmission/reception stops. 24.3.2 CLK Polarity Selection The SMi4 bit in the SiC register allows selection of the polarity of the transmit/receive clock. Figure 24.2 shows Polarity of Transmit/Receive Clock. . (1) When the SMi4 bit in the SiC register = 0 CLKi SOUTi SINi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 High level is output if not transmitting/receiving data (2) When the SMi4 bit = 1 CLKi SOUTi SINi i = 3, 4 Low level is output if not transmitting/receiving data D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Notes: The above diagram applies under the following conditions. 1. The SMi5 bit in the SiC register is 0 (LSB first). 2. The SMi6 bit in the SiC register is 1 (internal clock). 3. The SM26 bit or SM27 bit in the S32C2 register is 1 (SOUTi output retains last bit level) Figure 24.2 Polarity of Transmit/Receive Clock REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 560 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 24. Serial Interface SI/O3 and SI/O4 24.3.3 LSB First or MSB First Selection Bit order is selected by the SMi5 bit in the SiC register (i = 3, 4). Figure 24.3 shows Bit Order. (1) The SMi5 bit in the SiC register is set to 0 (LSB first) CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 (2) The SMi5 bit in the SiC register is set to 1 (MSB first) CLKi TXDi RXDi D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 The above diagram applies under the following condition: The SMi4 bit in the SiC register is set to 0 (transmit data is output at falling edge of transmit/receive clock and receive data is input at rising edge) i = 3, 4 Figure 24.3 Bit Order REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 561 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 24. Serial Interface SI/O3 and SI/O4 24.3.4 Internal Clock When the SMi6 bit in the SiC register is 1, data is transmitted/received using internal clock. The internal clock is selected by the SM22 bit in the S32C2 register, the PCLK1 bit in the PLCKR register, and bits SMi1 to SMi0 in the SiC register. When the internal clock is used as transmit/receive clock, the SOUTi pin becomes high-impedance from when the SMi3 bit in the SiC register is set to 1 (SI/Oi enabled) and the SMi2 bit is set to 0 (SOUTi output enabled) to when the first data is output. When writing the transmit data into the SiTRR register, data transmission/reception starts by outputting the transmit/receive clock from the CLKi pin after waiting for 0.5 to 1.0 cycles of the transmit/receive clock. When completing the transmission/reception of 8 bits data, the transmit/receive clock from the CLKi pin stops. Figure 24.4 shows SI/Oi Operation Timing (Internal Clock). Transmission/reception starts after waiting for 0.5 to 1.0 cycles of transmit/receive clock by writing into the SiTRR register. Si/Oi internal clock CLKi output Write signal to the SiTRR register Hi-Z D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 Hi-Z D7 D7 SOUTi output SINi input IR bit in the SiIC register i = 3, 4 The above diagram applies under the following conditions: In the SiC register, SMi2 = 0 (SOUTi output), SMi3 = 1 (SOUTi output, CLKi function), SMi4 = 0 (transmit data is output at falling edge of transmist/receive clock and receive data is input at rising edge), SMi5 = 0 (LSB first), SMi6 = 1 (internal clock). In the S34C2 register, the SM26 bit (SOUT3) or SM27 bit (SOUT4) = 0 (high-impedance after transmission). Figure 24.4 SI/Oi Operation Timing (Internal Clock) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 562 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 24. Serial Interface SI/O3 and SI/O4 24.3.5 Function for Selecting SOUTi State after Transmission The SOUTi pin state after transmission is selected when the SMi6 bit in the SiC register is set to 1 (internal clock). If bits SM26 and SM27 in the S34C2 register are set to 1 (last bit level retained), output from the SOUTi pin retains the last bit level after transmission. Figure 24.5 shows Level of SOUT3 Pin after Transmission. SI/O internal clock High Low High CLK3 output Low Hi-Z When SM26 = 0 (high-impedance) SOUT3 output When SM26 = 1 (last bit level retained) D6 D7 D6 D7 The above SOUT3 example applies under the following conditions. The SM32 bit in the S3C register is 0 (SOUT3 output), The SM33 bit in the S3C register is 1 (SOUT3 output, CLK3 selected), The SM34 bit in the S3C register is 0 (transmit data output at the falling edge of the transmit/receive clock and the receive data is input at the rising edge ), The SM35 bit in the S3C register is 0 (LSB first), and The SM36 bit in the S3C register is 1 (internal clock) Figure 24.5 Level of SOUT3 Pin after Transmission REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 563 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 24. Serial Interface SI/O3 and SI/O4 24.3.6 External Clock When the SMi6 bit in the SiC register is set to 0, data is transmitted/received using external clock. The external clock is used as transmit/receive clock, the SOUTi output level from when the SMi3 bit in the SiC register is set to 1 (SI/Oi enabled) and SMi2 bit is set to 0 (SOUTi output enabled) to when the first data is output can be selected by the SMi7 bit in the SiC register. Refer to 24.3.8 “Function for Setting SOUTi Initial Value”. Transmission/reception starts with the external clock after writing the transmit data into the SiTRR register. The data written into the SiTRR register is shifted every time the external clock is input. When completing data transmission/reception of the 8th bit, read or write into the SiTRR register before inputting the clock for the next data transmission/reception. Figure 24.6 shows SI/Oi Operation Timing (External Clock). If the SMi4 bit is set to 0, write into the SiTRR register when CLKi input is the high level . CLKi input Write signal to the SiTRR register D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 SOUTi output SINi input IR bit in the SiIC register i = 3, 4 The above diagram applies under the following conditions. In the SiC register, SMi2 = 0 (SOUTi output), SMi3 = 1 (SOUTi output, CLKi function), SMi4 = 0 (transmit data is output at falling edge of transmit/receive clock and receive data is input at rising edge), SMi5 = 0 (LSB first), SMi6 = 0 (external clock) Figure 24.6 SI/Oi Operation Timing (External Clock) When the SMi6 bit in the SiC register is set to 0 (external clock), write into the SiTRR register and SMi7 bit in the SiC register under the following conditions: • When the SMi4 bit in the SiC register is set to 0 (transmit data is output at falling edge of transmit/ receive clock and receive data is input at rising edge): CLKi input is high level. • When the SMi4 bit is set to 1 (transmit data is output at rising edge of transmit/receive clock and receive data is input at falling edge): CLKi input is low level. 24.3.7 SOUTi Pin The SOUTi pin state can be selected by bits SMi2 and SMi3 in the SiC register. Table 24.4 lists SOUTi Pin State. Table 24.4 SOUTi Pin State Bit Setting SiC register SMi2 SMi3 0 0 1 1 0/1 SOUTi Pin State I/O port or another peripheral function SOUTi output High-impedance REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 564 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 24. Serial Interface SI/O3 and SI/O4 24.3.8 Function for Setting SOUTi Initial Value If the SMi6 bit in the SiC register is set to 0 (external clock), the SOUTi pin output can be fixed high or low when not transmitting/receiving data. High or low can be selected by the SMi7 bit in the SiC register. However, the last bit value of the previous unit of data is retained between adjacent units of data when using external clock. Figure 24.7 shows Timing Chart for Setting SOUTi Initial Value and How to Set It. (Example) When High Selected for SOUTi Initial Value Write signal to SiTRR register Initial value setting of SOUTi output and starting of transmission/reception SMi7 bit SMi3 bit Set the SMi3 bit to 0 (SOUTi pin functions as an I/O port) SOUTi (internal) D0 Set the SMi7 bit to 1 (SOUTi initial value = high) SOUTi pin output (i = 3, 4) Port output Initial value = high D0 Set the SMi3 bit to 1 (SOUTi pin functions as SOUTi output) High level is output from the SOUTi pin Write into the SiTRR register Setting the SOUTi Port selection switching initial value to high (1) (I/O port → SOUTi) This diagram applies under the following conditions. SMi2 = 0 (SOUTi output), SMi5 = 0 (LSB first), SMi6 = 0 (external clock) Note: 1. SOUTi can only be initialized when input on the CLKi pin is in the high state if the SMi4 bit in the SiC register = 0 (transmit data is output at the falling edge of the transmit receive clock) or in the low state if the SMi4 bit = 1 (transmit data is output at the rising edge of the transmit/receive clock). Serial transmission/reception starts Figure 24.7 Timing Chart for Setting SOUTi Initial Value and How to Set It REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 565 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 24. Serial Interface SI/O3 and SI/O4 24.4 Interrupt Refer to the operation example for interrupt source or interrupt request generation timing. Refer to 14.7 “Interrupt Control” for interrupt control. Table 24.5 lists Registers Associated with SI/O3 and SI/O4. Table 24.5 Registers Associated with SI/O3 and SI/O4 Address 0048h 0049h 0207h Register Name SI/O4 Interrupt Control Register SI/O3 Interrupt Control Register Interrupt Source Select Register Register Symbol S4IC S3IC IFSR After Reset XX00 X000b XX00 X000b 00h The following interrupts share the interrupt vector and interrupt control register with other peripheral functions. To use the following interrupts, set bits as follows. • SI/O3: Set the IFSR6 bit in the IFSR register to 0 (SI/O3). • SI/O4: Set the IFSR7 bit in the IFSR register to 0 (SI/O4). Set the POL bit in the SiIC register to 0 (falling edge). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 566 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 24. Serial Interface SI/O3 and SI/O4 24.5 24.5.1 Notes on Serial Interface SI/O3 and SI/O4 SOUTi Pin Level When SOUTi Output Disabled When the SMi2 bit in the SiC register is set to 1 (SOUTi output disabled), the target pin goes to highimpedance state regardless of which function of the pin is being used. 24.5.2 External Clock Control The data written into the SiTRR register is shifted every time the external clock is input. When completing data transmission/reception of the 8th bit, read or write into the SiTRR register before inputting the clock for the next data transmission/reception. 24.5.3 Register Access When Using External Clock When the SMi6 bit in the SiC register is set to 0 (external clock), write into the SMi7 bit in the SiC register and the SiTRR register under the following conditions: • When the SMi4 bit in the SiC register is set to 0 (transmit data is output at falling edge of transmit/ receive clock and receive data is input at rising edge): CLKi input is high level. • When the SMi4 bit in the SiC register is set to 1 (transmit data is output at rising edge of transmit/ receive clock and receive data is input at falling edge): CLKi input is low level. 24.5.4 SiTRR Register Access Write transmit data into the SiTRR register while transmission/reception stops. Read receive data from the SiTRR register while transmission/reception stops. The IR bit in the SiIC register becomes 1 (interrupt request) during output of the 8th bit. If the SM26 bit (SOUT3) or SM27 bit (SOUT4) in the S32C2 register is set to 0 (high-impedance after transmission), SOUTi pin becomes high-impedance when the transmit data is written into the SiTRR register immediately after an interrupt request is generated, and hold time of the transmit data becomes shorter. 24.5.5 Pin Function Switch When Using Internal Clock If the SMi3 bit in the SiC register (i = 3, 4) changes from 0 (I/O port) to 1 (SOUTi output, CLK function) when setting the SMi2 bit to 0 (SOUTi output) and the SMi6 bit to 1 (internal clock), SOUTi initial value set to the SOUTi pin by the SMi7 bit may be output about for 10 ns. After that, the SOUTi pin becomes high-impedance. If the output level from the SOUTi pin when the SMi3 bit changes from 0 to 1 becomes a problem, set the SOUTi initial value by the SMi7 bit. 24.5.6 Operation After Reset When Selecting External Clock When the SMi6 bit in the SiC register is set to 0 (external clock) after reset, the IR bit in the SiIC register becomes 1 (interrupt request) by inputting the external clock for 8 bits to the CLKi pin. This will also happen even when the SMi3 bit in the SiC register is 0 (serial interface disabled) or before the value is written into the SiTRR register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 567 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25. Multi-Master I2C-bus Interface 25.1 Introduction The multi-master I2C-bus interface (I2C interface) is a serial communication circuit based on I2C-bus data transmit/receive format, equipped with arbitration lost detection and clock synchronous functions. Table 25.1 lists Multi-master I2C-bus Interface Specification, Table 25.2 lists Detections of I2C Interface, Figure 25.1 shows Multi-master I2C-bus Interface Block Diagram, and Table 25.3 lists I/O Ports. Table 25.1 Multi-master I2C-bus Interface Specification Item Format Based on standard: 7-bit addressing format High-speed clock mode Standard clock mode I2C-bus Function Communication mode Bit rate I/O pin Based on I2C-bus standard: Master-transmitter Master-receiver Slave-transmitter Slave-receiver 16.1 kbps to 400 kbps (fVIIC = 4 MHz) Serial data line SDAMM (SDA) Serial clock line SCLMM (SCL) Interrupt request generating I2C-bus interrupt source Completion of transmission Completion of reception Slave address match detection General call detection Stop condition detection Timeout detection • SDA/SCL interrupt Rising or falling edge of the SDAMM/SCLMM line Selectable functions • I2C-bus interface pin input level select Selectable input level with I2C-bus input level or SMBus input level • SDA/port, SCL/port selection A function to change pins SDAMM and SCLMM to output ports respectively. • Timeout detection A function to detect that SCLMM pin is driven high for over a certain period of time when the bus is busy. • Free format select A function to generate an interrupt request when receiving the 1st byte data, regardless of the slave address value. fVIIC: I2C-bus system clock REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 568 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface Table 25.2 Detections of I2C Interface Item Slave address match General call Arbitration lost Bus busy Function A function to detect a slave address match as a slave-transmitter or receiver. When own slave address is matched with the calling address sent from a master, ACK is generated automatically. When an address match is not found, no ACK is generated and no more data is transmitted or received. One slave can have up to three slave addresses. A function to detect a general call as a slave-receiver. A function to detect arbitration lost to stop the SDAMM clock output immediately. A function to detect a bus busy state and set/reset the BB bit. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 569 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface I2C0 control register 1 (S3D0) b7 ICK1 ICK0 b0 SCL SDA PEC PED WIT SIM M M b7 I2C0 address register 2(S0D2) b0 SAD SAD SAD SAD SAD SAD SAD 6 5 4 3 2 1 0 b7 I2C0 address register 1(S0D1) b0 SAD SAD SAD SAD SAD SAD SAD 6 5 4 3 2 1 0 b7 I2C0 status register 1(S11) b0 AAS AAS AAS 2 1 0 b7 I2C0 address register 0(S0D0) b0 SAD SAD SAD SAD SAD SAD SAD 6 5 4 3 2 1 0 Interrupt generator SCL/SDA interrupt request b7 SA Address comparator D6 b0 Interrupt generator I2C-bus interface interrupt request I2C0 data shift register (S00) Data controller SDAMM (SDA) Noise filter I2C0 status register 0 (S10) b7 AL AAS ADR LRB 0 b0 PIN b7 STSP SIS SEL b0 SIP SSC SSC SSC SSC SSC 4 3 2 1 0 MST TRX BB AL circuit I2C0 start/stop condition control register (S2D0) I2C0 control register 2 (S4D0) SCPI MSL TOS ICK4 ICK3 ICK2 TOF TOE N AD EL BB circuit b7 TISS IHR b0 ALS ES0 BC2 BC1 BC0 Timeout detector I2C0 control register 0 (S1D0) SCLMM (SCL) Noise filter Clock controller b7 ACK ACK CLK BIT FAST MODE b0 CCR CCR CCR CCR CCR 4 3 2 1 0 Bit counter I2C0 clock control register (S20) Clock divider I2C-bus system clock (fVIIC) PCLKR register PCLK0=1 f1IIC fIIC f2IIC PCLK0=0 System clock selector Figure 25.1 Multi-master I2C-bus Interface Block Diagram Table 25.3 I/O Ports Pin Name SDAMM SCLMM I/O Type I/O I/O Function I/O pin for SDA (N channel open drain output) I/O pin for SCL (N channel open drain output) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 570 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.2 Registers Descriptions Table 25.4 lists registers associated with multi-master I2C-bus interface. When the CM07 bit in the CM0 register is set to 1 (sub clock is CPU clock), registers listed in Table 25.4 should not be accessed. Set them after the CM07 bit is set to 0 (main clock, PLL clock, or on-chip oscillator clock). Table 25.4 Register Configuration Address 0012h 02B0h 02B2h 02B3h 02B4h 02B5h 02B6h 02B7h 02B8h 02B9h 02BAh 02BBh Register Name Peripheral Clock Select Register I2C0 Data Shift Register I2C0 Address Register 0 I2C0 Control Register I2C0 Clock Control Register I2C0 Start/Stop Condition Control Register I2C0 Control Register 1 I2C0 Control Register 2 I2C0 Status Register 0 I2C0 Status Register 1 I2C0 Address Register 1 I2C0 Address Register 2 Symbol PCLKR S00 S0D0 S1D0 S20 S2D0 S3D0 S4D0 S10 S11 S0D1 S0D2 After Reset 0000 0011b XXh 0000 000Xb 00h 00h 0001 1010b 0011 0000b 00h 0001 000Xb 00h 0000 000Xb 0000 000Xb REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 571 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.2.1 Peripheral Clock Select Register (PCLKR) Peripheral Clock Select Register b7 b6 b5 b4 b3 b2 b1 b0 00 000 Symbol PCLKR Bit Symbol Bit Name Address 0012h Function After Reset 0000 0011b RW PCLK0 Timers A and B clock select bit (clock source for timers A and B, the dead time timer, and muliti-master I2C-bus interface) SI/O clock select bit (clock source for UART0 to UART2, UART5 to UART7, SI/O3, and SI/O4) Reserved bits Clock output function extension bit (valid in single-chip mode) Reserved bits 0: f2TIMAB/f2IIC 1: f1TIMAB/f1IIC RW PCLK1 0: f2SIO 1: f1SIO RW — (b4-b2) PCLK5 — (b7-b6) Set to 0 0: Selected by bits CM01 to CM00 in the CM0 register 1: Output f1 Set to 0 RW RW RW Write to the PCLKR register after setting the PRC0 bit in the PRCR register to 1 (write enabled). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 572 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.2.2 I2C0 Data Shift Register (S00) I2C0 Data Shift Register b7 b0 Symbol S00 Address 02B0h Function After Reset Undefined RW RW Transmit/receive data is stored. When the I2C interface is a transmitter, write a transmit data to the S00 register. When the I2C interface is a receiver, a received data can be read from the S00 register. In master mode, this register is used to generate a start condition or stop condition on a bus. (Refer to 25.3.2 “Generation of Start Condition” and 25.3.3 “Generation of Stop Condition”.) Write to the S00 register when the ES0 bit in the S1D0 register is set to 1 (I2C interface enabled). The S00 register should not be written when data transmission/reception is in progress. When the I2C interface is a transmitter, the data written in the S00 register is transmitted to other devices. The MSB (bit 7) is transmitted first, synchronizing with the SCLMM clock. Every time one-bit data is output, the content of the S00 register is one-bit shifted to the left. When the I2C interface is a receiver, a data is transferred to the S00 register from other devices. The LSB (bit 0) is input first, synchronizing with the SCLMM clock. Every time one-bit data is output, the content of the S00 register is one-bit shifted to the left. Figure 25.2 shows Timing to Store The Received Data into The S00 Register. SCLMM SDAMM tdfil Internal SCL Internal SDA tdfil tdsft Shift clock (Internal signal) Data is stored into the bit 0 at the rising edge of shift clock S00 register Data Data tdfil: Noise filter delay time, 1 to 2 fVIIC cycles tdsft: Shift clock delay time, 1 fVIIC cycle Data shifts for one bit to the left Figure 25.2 Timing to Store The Received Data into The S00 Register REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 573 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.2.3 I2C0 Address Register i (S0Di) (i = 0 to 2) I2C0 Address Register i (i = 0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol S0D0 S0D1 S0D2 Bit Symbol — (b0) SAD0 Bit Name Address 02B2h 02BAh 02BBh After Reset 0000 000Xb 0000 000Xb 0000 000Xb Function RW — No register bit. If necessary, set to 0. Read as undefined value RW SAD1 RW SAD2 RW SAD3 Slave Address Set a slave address RW SAD4 RW SAD5 RW SAD6 RW SAD6-SAD0 (Slave Address) (b7-b1) Bits SAD6 to SAD0 indicate a slave address to be compared for a slave address match detection in slave mode. An I2C interface can have maximum of three slave addresses. Set bits SAD6 to SAD0 in the S0Di register to 0000000b when not setting the slave address. However, when the MSLAD bit in the S4D0 register is 0, registers S0D1 and S0D2 are disabled. Only the slave address set to the S0D0 register is compared with address data received. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 574 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.2.4 I2C0 Control Register (S1D0) I2C0 Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol S1D0 Bit Symbol BC0 Bit Name Address 02B3h Function b2 b1 b0 0 After Reset 00X0 0000b RW RW BC1 Bit counter (number of transmitted/received bits) BC2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0: 1: 0: 1: 0: 1: 0: 1: 8 7 6 5 4 3 2 1 RW RW ES0 I2C bus interface enable bit 0: Disabled 1: Enabled 0: Addressing format 1: Free data format Set to 0. 0: reset is deasserted (automatically) 1: reset 0: I2C-bus input 1: SMBus input RW ALS — (b5) IHR Data format select bit RW Reserved bit RW I2C-bus interface reset bit I2C-bus interface pin input level select bit RW TISS RW BC2-BC0 (Bit Counter) (b2-b0) Bits BC2 to BC0 become 000b (8 bits) when start or stop condition is detected. When the ACKCLK bit in the S20 register is 0 (no ACK clock), and data for the number of bits selected by bits BC2 to BC0 is transmitted or received, bits BC2 to BC0 become 000b again. When the ACKCLK bit in the S20 register is 1 (ACK clock), data for the number of bits selected and an ACK is transmitted or received, bits BC2 to BC0 become 000b again. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 575 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface ES0 (I2C bus Interface Enable Bit) (b3) The ES0 bit enables the I2C interface. When the ES0 bit is set to 0, the I2C interface status becomes as follows. • Pins SDAMM and SCLMM: I/O port or other peripheral pins • Write disable to the S00 register • I2C-bus system clock (hereinafter called fVIIC) stops • S10 register ADR0 bit: 0 (general call not detected) AAS bit: 0 (slave address not matched) AL bit: 0 (arbitration lost not detected) PIN bit: 1 (no I2C-bus interrupt request) BB bit: 0 (bus free) TRX bit: 0 (receive mode) MST bit: 0 (slave mode) • Bits AAS2 to AAS0 in the S11 register: 0 (slave address not matches) • TOF bit in the S4D0 register: 0 (timeout not detected) ALS (Data Format Select Bit) (b4) The ALS bit is enabled in slave mode. When the ALS bit is 0 (addressing format), the slave address match detection is performed. When any of the slave address stored into bits SAD6 to SAD0 in the S0Di register (i = 0 to 2) is compared and matched with the calling address by a master, or when a general call address is received, the IR bit in the IICIC register becomes 1 (interrupt requested). When the ALS bit is 1 (free format), the slave address match detection is not performed. Therefore, the IR bit in the IICIC register becomes 1 (interrupt requested), regardless of the calling address by a master. IHR (I2C bus Interface Reset Bit) (b6) The IHR bit resets the I2C interface if a difficulty in transmission/reception is encountered. When the ES0 bit in the S1D0 register is 1 (I2C interface enabled) and then the IHR bit is set to 1 (reset), the I2C interface becomes as follows. • S10 register ADR0 bit: 0 (general call not detected) AAS bit: 0 (slave address not matched) AL bit: 0 (arbitration lost not detected) PIN bit: 1 (No I2C-bus interrupt request) BB bit: 0 (bus free) TRX bit: 0 (receive mode) MST bit: 0 (slave mode) • Bits AAS2 to AAS0 in the S11 register: 0 (slave address not matches) • TOF bit in the S4D0 register: 0 (timeout not detected) When the IHR bit is set to 1, the I2C interface is reset and the IHR bit becomes 0 automatically. It takes maximum of 2.5 fVIIC cycles to complete reset sequence. Figure 25.3 shows Reset Timing of I2C Interface. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 576 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface Set to 1 by a program IHR bit in the S1D0 register Reset signal of I2C-bus circuit 2.5 fVIIC cycles Figure 25.3 Reset Timing of I2C Interface TISS (I2C bus Interface Pin Input Level Select Bit) (b7) The TISS bit selects the input level of the SCLMM pin and SDAMM pin for the I2C interface. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 577 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.2.5 I2C0 Clock Control Register (S20) I2C0 Clock Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol S20 Address 02B4h After Reset 00h Bit Symbol CCR0 Bit Name Function RW RW CCR1 Refer to bits CCR4 to CCR0 (Bit Rate Control Bit) (b4 to b0) in the S20 register. RW CCR2 Bit rate control bit RW CCR3 RW CCR4 0: Standard-speed clock mode 1: High-speed clock mode 0: ACK is returned 1: ACK is not returned 0: No ACK clock present 1: ACK clock present RW FASTMODE SCL mode select bit RW ACKBIT ACK bit RW ACKCLK ACK clock bit RW REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 578 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface CCR4-CCR0 (Bit Rate Control Bit) (b4-b0) The setting range of bits CCR4 to CCR0 (CCR value) is 0 to 31. If the setting values of bits CCR4 to CCR0 are the CCR value (CCR value: 3 to 31), the bit rate can be determined by the following equations. Refer to 25.3.1.2 “Bit Rate and Duty Cycle” for more details. In standard speed clock mode, fVIIC Bit rate = ---------------------------------------- ≤ 100 kbps 8 × CCR value When the CCR value is other than 5 in high-speed clock mode, fVIIC Bit rate = ---------------------------------------- ≤ 400 kbps 4 × CCR value When the CCR value is 5 in high-speed clock mode, the bit rate is assumed to reach 400 kbps, the maximum bit rate in high-speed clock mode. fVIIC - fVIIC Bit rate = ---------------------------------------- = ------------- ≤ 400 kbps 2 × CCR value 10 The CCR value should not be set to 0 to 2 regardless of the fVIIC frequency. Bits CCR4 to CCR0 should not be rewritten during transmission/reception. FASTMODE (SCL Mode Select Bit) (b5) When using the high-speed clock mode I2C-bus standard (400 kbps at maximum), set the FASTMODE bit to 1 (high-speed clock mode) and set fVIIC at 4 MHz or more. The FASTMODE bit should not be rewritten during transmission/reception. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 579 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface ACKBIT (ACK bit) (b6) The ACK bit is enabled when the I2C interface is a master-receiver or slave-receiver. It is also enabled when receiving a slave address. When receiving a slave address, the SDAMM pin level during the ACK clock pulse is determined by the combination of bits ALS and ACKBIT in the S1D0 register and the received slave address. When receiving data, the SDAMM pin level during the ACK clock pulse is determined by the ACKBIT bit. Table 25.5 lists the SDAMM Pin Level during the ACK Clock Pulse. Table 25.5 SDAMM Pin Level during the ACK Clock Pulse Received Content Slave Address 0 ALS Bit in the S1D0 Register ACKBIT Bit in the S20 Register 0 Slave Address Content Matched with bits SAD6 to SAD0 in any of registers S0D0 to S0D2 0000000b Others SDAMM Pin Level at ACK Clock L (ACK) L (ACK) H (NACK) H (NACK) L (ACK) H (NACK) L (ACK) H (NACK) 1 1 Data — 0 1 0 1 — — — — — ACKCLK (ACK Clock Bit) (b7) When the ACKCLK bit is 1 (ACK clock presents), an ACK clock is generated immediately after one-byte data is transmitted or received (8 clocks). When the ACKCLK bit is 0 (no ACK clock), no ACK clock is generated after one-byte data is transmitted or received (8 clocks). At the falling edge of the data transmission/reception (the falling edge of the 8th clock), the IR bit in the IICIC register becomes 1 (interrupt requested). The ACKCLK bit should not be rewritten during transmission/reception. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 580 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.2.6 I2C0 Start/Stop Condition Control Register (S2D0) I2C0 Start/Stop Condition Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol S2D0 Bit Symbol SSC0 Bit Name Address 02B5h Function After Reset 0001 1010b RW RW SSC1 Refer to "SSC4 to SSC0 (Start/Stop Condition Setting Bit)" in the same page RW SSC2 Start/stop condition setting bit RW SSC3 RW SSC4 SCL/SDA interrupt pin polarity select bit SCL/SDA interrupt pin select bit 0: Falling edge 1: Rising edge 0: SDAMM 1: SCLMM RW SIP RW SIS RW STSPSEL Start/stop condition generation 0: Short setup/hold time mode select bit 1: Long setup/hold time mode RW SSC4-SSC0 (Start/Stop Condition Setting Bit) (b4-b0) Bits SSC4 to SSC0 select the start/stop condition detect condition (SCL open time, setup time, hold time) in standard clock mode. Refer to 25.3.7 “Start Condition and Stop Condition Detection”. Do not set odd values or 00000b to bits SSC4 to SSC0. SIP (SCL/SDA Interrupt Pin Polarity Select Bit) (b5) SIS (SCL/SDA Interrupt Pin Select Bit) (b6) The IR bit in the SCLDAIC register is set to 1 (interrupt requested) when the I2C interface detects the edge selected by the SIP bit for the pin signal selected by the SIS bit. Refer to 25.4 “Interrupts”. STSPSEL (Start/Stop Condition Generation Select Bit) (b7) Refer to Table 25.13 “Setup/Hold Time for Start/Stop Condition Generation”. If the fVIIC frequency is more than 4 MHz, set the STSPSEL bit to 1 (long mode). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 581 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.2.7 I2C0 Control Register 1 (S3D0) I2C0 Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol S3D0 Bit Symbol Bit Name Address 02B6h Function After Reset 0011 0000b RW SIM 0: I2C-bus interrupt by stop condition Stop condition detect interrupt detection is disabled enable bit 1: I2C-bus interrupt by stop condition detection is enabled When write, 0: I2C-bus interrupt at 8th clock is disabled 1: I2C-bus interrupt is enabled at 8th clock RW WIT Data receive interrupt enable bit RW When read, internal WAIT bit monitor 0: I2C-bus interrupt by falling edge of ACK clock 1: I2C-bus interrupt at 8th clock PED SDAMM/port function select bit SCLMM/port function select bit Internal SDA output monitor bit Internal SCL output monitor bit I2C-bus system clock select bit (Enabled when bits ICK4 to ICK2 in the S4D0 register are 000b) 0: SDAMM I/O pin 1: Port output pin 0: SCLMM I/O pin 1: Port output pin 0: Logic 0 output 1: Logic 1 output 0: Logic 0 output 1: Logic 1 output b7 b6 RW PEC RW SDAM RO SCLM RO ICK0 ICK1 0 0 1 1 0: fIIC divided by 2 1: fIIC divided by 4 0: fIIC divided by 8 1: Should not be set RW RW Do not use the bit managing instruction (read-modify-write instruction) to access the S3D0 register. Use MOV instruction to write to the S3D0 register. SIM (Stop Condition Detect Interrupt Enable Bit) (b0) When the SIM bit is 1 (I2C-bus interrupt by stop condition detection enabled) and a stop condition is detected, the SCPIN bit in the S4D0 register becomes 1 (stop condition detect interrupt requested) and the IR bit in the IICIC register becomes 1 (interrupt requested). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 582 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface WIT (Data Receive Interrupt Enable Bit) (b1) The WIT bit is enabled when the I2C interface is a master-receiver or slave-receiver. The WIT bit has two functions. • Select the I2C-bus interrupt timing when data is received. (write) • Monitor the state of the internal WAIT flag. (read) The WIT bit can select whether to generate an I2C-bus interrupt request at eighth clock (before ACK clock) during the data reception. When the ACKCLK bit in the S20 register is 1 (ACK clock) and the WIT bit is set to 1 (enable I2C-bus interrupt at 8th clock), an I2C-bus interrupt request is generated at the eighth clock (before ACK clock). Then, the PIN bit in the S10 register becomes 0 (interrupt requested). When the ACKCLK bit in the S20 register is 0 (no ACK clock), write a 0 to the WIT bit to disable the I2Cbus interrupt by data reception. During data transmission and slave address reception, any interrupt request will not be generated at the eighth clock (before ACK clock) regardless of the value written to the WIT bit. Reads of the WIT bit returns the internal WAIT flag status. The I2C-bus interrupt request is generated at the falling edge of the ninth clock (ACK clock) regardless of the value written to the WIT bit. Then, the PIN bit in the S10 register becomes 0 (interrupt requested). Therefore, read the internal WAIT flag status to determine whether the I2C-bus interrupt request is generated at eighth clock (before ACK clock) or at the falling edge of the ACK clock. When a 1 is written to the WIT bit to enable the I2C-bus interrupt by data reception, the internal WAIT flag changes under the following condition. Condition to become 0: • The S20 register (ACKBIT bit) is written. Condition to become 1: • The S00 register is written. During data transmission and slave address reception, the internal WAIT flag is 0 and the I2C-bus interrupt request will be generated only at the falling edge of the ninth clock (ACK clock), regardless of the value written to the WIT bit. Table 25.6 lists an interrupt request generation timing and the conditions to restart transmission/ reception during data reception. Figure 25.4 shows Interrupt Request Generation Timing in Receive Mode. Table 25.6 Generating Interrupt Request and Restarting Transmission/Reception During Data Reception I2C-bus Interrupt Request Generation Timing Internal WAIT Flag Status At the falling edge of 8th clock of data (before 1 the ACK clock) (1) At the falling edge of 9th clock (ACK clock) (2) 0 Conditions to Restart Transmission/Reception Write to the ACKBIT bit in the S20 register (3) Write to the S00 register Notes: 1. See the timing of (1) on the IR bit in the IICIC register in Figure 25.4. 2. See the timing of (2) on the IR bit in the IICIC register in Figure 25.4. 3. Do not change the value of the bits other than ACKBIT bit in the S20 at this time. Also, do not write to the S00 register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 583 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface When setting the WIT bit to 1 in receive mode, and ACK clock is present: (I2C-bus interrupt is enabled at 8th clock) SCLMM 7 8 9 ACK clock SDAMM 7th bit 8th bit 1st bit ACKBIT bit in the S20 register Write by a program PIN bit in the S10 register Internal WAIT flag (1) IR bit in the IICIC register (2) Write signal to the S00 register Set to 0 by an interrupt acceptance or by a program When setting the WIT bit to 0 in receive mode, and ACK clock is present: (I2C-bus interrupt is disabled at 8th clock) SCLMM 7 8 9 ACK clock 1 SDAMM 7th bit 8th bit ACK bit 1st bit ACKBIT bit in the S20 register 0 PIN bit in the S10 register Internal WAIT flag 0 (2) IR bit in the IICIC register Set to 0 by an interrupt acceptance or by a program Write signal to the S00 register Figure 25.4 Interrupt Request Generation Timing in Receive Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 584 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface PED (SDAMM Port Function Switch Bit) (b2) PEC (SCLMM Port Function Switch Bit) (b3) Bits PEC and PED are enabled when the ES0 bit in the S1D0 register is set to 1 (I2 C interface enabled). When the PEC bit is set to 1 (output port), the P7_1 bit value is output from the SCLMM pin regardless of the internal SCL output signal and PD7_1 bit value. When the PED bit is set to 1 (output port), the P7_0 bit value is output from the SDAMM pin regardless of the internal SDA output signal and PD7_0 bit value. The signal level on the bus is input to the internal SDA and internal SCL. When bits P7_1 to P7_0 in the P7 register are read after setting bits PD7_1 and PD7_0 in the PD7 register to 0 (input mode), the level on the bus can be read regardless of the setting values of bits PED and PEC. Table 25.7 lists SCLMM and SDAMM Pin Functions. Table 25.7 SCLMM and SDAMM Pin Functions Pin P7_1/SCLMM S1D0 Register ES0 bit 0 1 S3D0 Register PED bit 0 1 PEC bit 0 1 - Pin Function I/O port or other peripheral pins SCLMM (SCL input/output) Output port (output P7_1 bit value) I/O port or other peripheral pins SDAMM (SDA input/output) Output port (output P7_0 bit value) P7_0/SDAMM 0 1 –: 0 or 1 SDAM (Internal SDA Output Monitor Bit) (b4) SCLM (Internal SCL Output Monitor Bit) (b5) The internal SDA and SCL output signal levels are the same as the output level of the I2C interface before it has any effect from the external device output. Bits SDAM and SCLM are read only bits. Should be written with 0. ICK1-ICK0 (I2C bus System Clock Select Bit) (b7-b6) Bits ICK1 to ICK0 should be rewritten when the ES0 bit in the S1D0 register is 0 (I 2 C interface disabled). The fVIIC is selected by setting all the bits ICK1 to ICK0, bits ICK4 to ICK2 in the S4D0 register, and the PCLK0 bit in the PCLKR register. Refer to 25.3.1.2 “Bit Rate and Duty Cycle”. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 585 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface Table 25.8 I2C-bus System Clock Select Bits S4D0 Register ICK4 Bit 0 0 0 0 0 0 1 ICK3 Bit 0 0 0 0 1 1 0 ICK2 Bit 0 0 0 1 0 1 0 0 0 1 – – – – S3D0 Register ICK1 Bit ICK0 Bit 0 1 0 – – – – fVIIC fIIC divided-by-2 fIIC divided-by-4 fIIC divided-by-8 fIIC divided-by-2.5 fIIC divided-by-3 fIIC divided-by-5 fIIC divided-by-6 –: 0 or 1 Do not set any combination other than the above. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 586 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.2.8 I2C0 Control Register 2 (S4D0) I2C0 Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol S4D0 Address 02B7h After Reset 00b Bit Symbol TOE Bit Name Timeout detect function enable bit Timeout detect flag 0: Disabled 1: Enabled 0: Not detected 1: Detected 0: Long time 1: Short time b5 b4 b3 Function RW RW TOF RO TOSEL Timeout detect time select bit RW ICK2 I2C-bus system clock select bit ICK3 ICK4 0 0 0: Bits ICK1 and ICK0 in the S3D0 register are enabled 0 0 1: fIIC divided by 2.5 0 1 0: fIIC divided by 3 0 1 1: fIIC divided by 5 1 0 0: fIIC divided by 6 Do not set other than the above values. 0: S0D0 register only 1: Registers S0D0 to S0D2 RW RW RW MSLAD Slave address compare bit RW SCPIN Stop condition detect interrupt 0: I2C-bus interrupt not requested request bit 1: I2C-bus interrupt requested RW TOE (Timeout Detect Function Enable Bit) (b0) The TOE bit enables the timeout detect function. Refer to 25.3.9 “Timeout Detection” for details. TOF (Timeout Detect Flag) (b1) The TOF bit is enabled when the TOE is set to 1. When the TOF bit is set to 1 (detected), the IR bit in the IICIC register is set to 1 (requested) at the same time. Condition to become 0: • The ES0 bit in the S1D0 register is set to 0 (I2C interface disabled). • The IHR bit in the S1D0 register is set to 1 (I2C interface reset). Condition to become 1: • The BB bit in the S10 register is set to 1 (bus busy) and the SCLMM high period is greater than the timeout detect period. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 587 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface TOSEL (Timeout Detection Period Select Bit) (b2) The TOSEL bit selects timeout detection period. The TOSEL bit is enabled when the TOE bit is 1 (timeout detect function enabled). When long time is selected, the internal counter increments fVIIC as a 16-bit counter. when short time is selected, it increments fVIIC as a 14-bit counter. Therefore, timeout detect period is as follows. When the TOSEL bit is set to 0 (long time), 165536 × ------------fVIIC When the TOSEL bit is set to 1 (short time), 116384 × ------------fVIIC Table 25.9 lists Timeout Detect Period. Table 25.9 Timeout Detect Period fVIIC TOSEL Bit: 0 (Long time) 4 MHz 2 MHz 1 MHz 16.4 ms 32.8 ms 65.6 ms Timeout Detect TOSEL bit: 1 (Short time) 4.1 ms 8.2 ms 16.4 ms ICK4-ICK2 (I2C bus System Clock Select Bit) (b5-b3) Bits ICK4 to ICK2 should be rewritten when the ES0 bit in the S1D0 register is set to 0 (I2C interface disabled). The fVIIC is selected by setting all the bits ICK4 to ICK2, bits ICK1 to ICK0 in the S3D0 register, and the PCLK0 bit in the PCLKR register. Refer to Table 25.8 “I2C-bus System Clock Select Bits” and 25.3.1.2 “Bit Rate and Duty Cycle”. MSLAD (Slave Address Control Bit) (b6) The MSLAD bit is enabled when the ALS bit in the S1D0 register is set to 0 (addressing format). The MSLAD bit selects the S0Di register (i = 0 to 2) that is used for address match detection. SCPIN (Stop Condition Detect Interrupt Request Bit) (b7) The SCPIN bit is enabled when the SIM bit in the S3D0 register is set to 1 (enable I2C-bus interrupt by stop condition detection). Condition to become 0: • Writing a 0 by a program. Condition to become 1: • Stop condition is detected (writing a 1 by a program has no effect). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 588 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.2.9 I2C0 Status Register 0 (S10) I2C0 Status Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol S10 Bit Symbol Bit Name Address 02B8h Function After Reset 0001 000Xb RW LRB Last receive bit When read, 0: Last bit = 0 1: Last bit = 1 When write, refer to Table 24.10 Functions enabled by S10 register. When read, 0: Not detected 1: Detected When write, refer to Table 24.10 Functions enabled by S10 register. When read, 0: No address matched 1: Address matched When write, refer to Table 24.10 Functions enabled by S10 register. When read, 0: Not detected 1: Detected When write, refer to Table 24.10 Functions enabled by S10 register. When read, 0: Interrupt requested 1: No interrupt requested When write, refer to Table 24.10 Functions enabled by S10 register. When read, 0: Bus free 1: Bus busy When write, refer to Table 24.10 Functions enabled by S10 register. 0: Receive mode 1: Transmit mode 0: Slave mode 1: Master mode RW ADR0 General call detection flag RW AAS Slave address compare flag RW AL Arbitration lost detection flag RW PIN I2C bus interface interrupt request bit RW BB Bus busy flag RW TRX Communication mode select bit 0 Communication mode select bit 0 RW MST RW Do not use the bit managing instruction (read-modify-write instruction) to access the S10 register. Use MOV instruction to write to the S10 register. Bit 5 to bit 0 in the S10 register (six lower bits) monitors the state of the I2C interface. The bit values cannot be changed by a program. However, a write to the S10 register, including the six lower bits, is used to generate start/stop condition. Bits MST and TRX are read and write bits. To change bits MST or TRX without generating the start/ stop condition, set 1111b to four lower bits in the S10 register. Table 21.10 lists the functions enabled by write access to the S10 register. Do not write other than the values listed in Table 21.10. If the values listed in Table 21.10 are written to the S10 register, six lower bits in the S10 register will not be changed. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 589 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface Table 25.10 MST 1 1 0/1 –: 0 or 1 TRX 1 1 0/1 Functions Enabled by Writing to the S10 Register Bit Setting of the S10 Register BB 1 0 – PIN 0 0 0 AL 0 0 1 AAS 0 0 1 ADR0 0 0 1 LRB 0 0 1 Function Sets the I2C interface to start condition standby state in master transmit/receive mode Sets the I2C interface to stop condition standby state in master transmit/receive mode Selects communication mode Refer to 25.3.2 “Generation of Start Condition” and 25.3.3 “Generation of Stop Condition” for start/stop condition generation. LRB (Last Receive Bit) (b0) The LRB bit function in read access is described as follows. See Table 25.10 “Functions Enabled by Writing to the S10 Register” for the bit function in write access. The LRB bit stores the last bit value of the received data. It is used to check whether the ACK is received. Condition to become 0: • An ACK response is sent from a receiver at ACK clock. • The ACKCLK bit is set to 0 (no ACK clock) and the last bit value is 0. • The S00 register is written. Condition to become 1: • No ACK response is sent from a receiver at ACK clock. • The ACKCLK bit is set to 0 (no ACK clock) and the last bit value is 1. ADR0 (General Call Detection Flag) (b1) The ADR0 bit function in read access is described as follows. See Table 25.10 “Functions Enabled by Writing to the S10 Register” for the bit function in write access. Condition to become 0: • Stop condition is detected. • Start condition is detected. • The ES0 bit in the S1D0 register is set to 0 (I2C interface disabled). • The IHR bit in the S1D0 register is set to 1 (I2C interface reset). Condition to become 1: • The ALS bit in the S1D0 register is set to 0 (addressing format) and the received slave address is 0000000b (general call) in slave mode. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 590 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface AAS (Slave Address Compare Flag) (b2) The AAS bit function in read access is described as follows. See Table 25.10 “Functions Enabled by Writing to the S10 Register” for the bit function in write access. Condition to become 0: • The S00 register is written. • The ES0 bit in the S1D0 register is set to 0 (I2C interface disabled). • The IHR bit in the S1D0 register is set to 1 (I2C interface reset). Condition to become 1: • In slave-receiver mode, the ALS bit in the S1D0 register is set to 0 (addressing format) and the received slave address is matched with bits SAD6 to SAD0 in any of registers S0D0 to S0D2. • In slave-receiver mode, the ALS bit in the S1D0 register is set to 0 (addressing format) and the general call address (0000000b) is received. AL (Arbitration Lost Detection Flag) (b3) The AL bit function in read access is described as follows. See Table 25.10 “Functions Enabled by Writing to the S10 Register” for the bit function in write access. Condition to become 0: • The S00 register is written. • The ES0 bit in the S1D0 register is set to 0 (I2C interface disabled). • The IHR bit in the S1D0 register is set to 1 (I2C interface reset). Condition to become 1: • In master-transmitter mode or master-receiver mode, the SDAMM pin level changes to low by an external device, not by the ACK clock, when slave address is transmitted. • The SDAMM pin level changes to low by an external device for other than the ACK clock when data is transmitted in master-transmitter mode. • In master-transmitter mode or master-receiver mode, the SDAMM pin level changes to low by an external device when start condition is transmitted. • In master-transmitter mode or master-receiver mode, the SDAMM pin level changes to low by an external device when stop condition is transmitted. • The function to avoid start condition overlaps is started. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 591 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface PIN (I2C bus Interface Interrupt Request Bit) (b4) The PIN bit function in read access is described as follows. See Table 25.10 “Functions Enabled by Writing to the S10 Register” for the bit function in write access. Condition to become 0: • Slave address transmission is completed in master mode (including a case of detecting arbitration lost). • One-byte data transmission is completed (including a case of detecting arbitration lost). • One-byte data reception is completed (the falling edge of 8th clock is detected when the ACKCKL bit is set to 0. The falling edge of ACK clock when the ACKCKL bit is set to 1.). • The WIT bit in the S3D0 register is set to 1 (I2C-bus interrupt enabled at 8th clock) and 1-byte data is received (before ACK clock). • In slave-receiver mode, the ALS bit in the S1D0 register is set to 0 (addressing format) and any of the slave address stored into bits SAD6 to SAD0 in the S0Di register (i = 0 to 2) is matched with the received slave address (slave address match). • In slave-receiver mode, the ALS bit in the S1D0 register is set to 0 (addressing format) and the general call address (0000000b) is received. • In slave-receiver mode, the ALS bit in the S1D0 register is set to 1 (free format) and the slave address reception is completed. Condition to become 1: • The S00 register is written. • The S20 register is written (when the WIT bit is 1 and internal WAIT flag is 1). • The ES0 bit in the S1D0 register is set to 0 (I2C interface disabled). • The IHR bit in the S1D0 register is set to 1 (I2C interface reset). The IR bit in the IICIC register is set to 1 (interrupt requested) as soon as the PIN bit is set to 0 (I2C-bus interrupt requested). When the PIN bit is set to 0, the SCLMM pin output level is low. However, the SCLMM pin output level does not become low when all the following conditions are met. • In master mode, when arbitration lost is detected by a slave address, the ALS bit in the S1D0 register is 0 (addressing format), and the received address not 0000000b (general call) does not match any of bits SAD6 to SAD0 in the registers S0D0 to S0D2. • In master mode, when arbitration lost is detected by data, the ALS bit in the S1D0 register is 0 (addressing format), and the slave address not 0000000b (general call) does not match any of bits SAD6 to SAD0 in the registers S0D0 to S0D2. BB (Bus Busy Flag) (b5) The BB bit function in read access is described as follows. See Table 25.10 “Functions Enabled by Writing to the S10 Register” for the bit function in write access. The BB bit indicates the state of the bus system, whether the bus is free or not. The BB bit changes depending on the SCLMM and SDAMM input signals, regardless of master mode or slave mode. Condition to become 0: • Stop condition is detected. • The ES0 bit in the S1D0 register is set to 0 (I2C interface disabled). • The IHR bit in the S1D0 register is set to 1 (I2C interface reset). Condition to become 1: • Start condition is detected. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 592 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface TRX (Communication Mode Select Bit 0) (b6) The TRX selects transmit mode or receive mode. Condition to become 0: • The TRX bit is set to 0 by a program. • Arbitration lost is detected. • Stop condition is detected. • Start condition overlap protect function is enabled. • Start condition is detected when the MST bit in the S10 register is set to 0 (slave mode). • No ACK is detected from a receiver when the MST bit in the S10 register is set to 0 (slave mode). • The ES0 bit in the S1D0 register is set to 0 (I2C interface disabled). • The IHR bit in the S1D0 register is set to 1 (I2C interface reset). Condition to become 1: • The TRX bit is set to 1 by a program. • The ALS bit in the S1D0 register is set to 0 (addressing format), the AAS bit is set to 1 (address matched) after receiving the slave address, and the received R/W bit is set to 1, in slave mode. MST (Communication Mode Select Bit 1) (b7) The MST bit selects master mode or slave mode. Condition to become 0: • The MST bit is set to 0 by a program. • The one-byte data that lost arbitration is completed transmitting/receiving when arbitration lost is detected. • Stop condition is detected. • Start condition overlap protect function is enabled. • The ES0 bit in the S1D0 register is set to 0 (I2C interface disabled. • The IHR bit in the S1D0 register is set to 1 (I2C interface reset). Condition to become 1: • The MST bit is set to 1 by a program. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 593 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.2.10 I2C0 Status Register 1 (S11) I2C0 Status Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol S11 Bit Symbol Bit Name Address 02B9h Function 0: No address matched 1: Address matched 0: No address matched 1: Address matched 0: No address matched 1: Address matched 00000 After Reset XXXX XXX0b RW RO AAS0 Slave address 0 compare flag AAS1 Slave address 1 compare flag RO AAS2 Slave address 2 compare flag RO — (b7-b3) Reserved bits Set to 0 RO AAS0 Bit (Slave Address 0 Compare Flag) (b0) AAS1 Bit (Slave Address 1 Compare Flag) (b1) AAS2 Bit (Slave Address 2 Compare Flag) (b2) The AASi bit indicates the address match when the ALS bit in the S1D0 register is set to 0 (addressing format) and any of the slave address stored into bits SAD6 to SAD0 in the S0Di register (i = 0 to 2) is compared with the received slave address. The AASi bit is set to 1 when there is an address match or when a general call address is received. Bits AAS2 to AAS0 are set to 0 under the following conditions. • The ES0 bit in the S1D0 register is set to 0 (I2C interface disabled). • The IHR bit in the S1D0 register is set to 1 (I2C interface reset). • The S00 register is written. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 594 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.3 25.3.1 Operations Clock Figure 25.5 shows I2C-bus Interface Clock. f1 Divide-by-2 f1IIC f2IIC PCLKR register PCLK0 = 1 fIIC PCLK0 = 0 System clock select circuit Divide-by-m I2C-bus system clock fVIIC S20 register FASTMODE = 0 Divide-by-8 FASTMODE= 1 ≠5 Divide-by-4 Divide-by-n (1) Clock control circuit =5 CCR4 to CCR0 Divide-by-2 m: 2, 4, 8, 2.5, 3, 5, 6 (selectable by bits ICK1 to ICK0 in the S3D0 register and bits ICK4 to ICK2 in the S4D0 register) n: 3 to 31 (setting values for bits CCR4 to CCR0 in the S20 register) Note: 1. Select 100 kHz or below for the CPU clock in standard clock mode, and 400 kHz or below in high-speed clock mode. Figure 25.5 I2C-bus Interface Clock 25.3.1.1 fVIIC The fVIIC is determined by the setting combination of the following. • The frequency of peripheral clock f1 • The PCLK0 bit in the PCLKR register • Bits ICK1 to ICK0 in the S3D0 register • Bits ICK4 to ICK2 in the S4D0 register The fVIIC stops when the ES0 bit in the S1D0 register is 0 (I2C interface disabled). Refer to Table 25.8 “I2C-bus System Clock Select Bits” for details. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 595 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.3.1.2 Bit Rate and Duty Cycle Bit rate is determined by the setting combination of the fVIIC and bits CCR4 to CCR0 in the S20 register. Table 25.11 lists Bit Rate of Internal SCL Output and Duty Cycle. Even if there is a change in duty cycle, the bit rate does not change. The bit rate and duty cycle described here are the ones before the I2C interface have any effect from the SCL output of external device. Table 25.11 Bit Rate of Internal SCL Output and Duty Cycle Item Bit rate (bps) Duty cycle Standard Clock Mode fVIIC -------------------------------------8 × CCR value High-Speed Clock Mode (CCR value = other than 5) fVIIC -------------------------------------4 × CCR value High-Speed Clock Mode (CCR value = 5) fVIIC ------------------------------------- = fVIIC -------------2 × CCRvalue 10 50% (1) 50% (2) 35 to 45% CCR value: Setting value of bits CCR4 to CCR0 Notes: 1. Fluctuation of high level: -4 to +2 fVIIC cycles 2. Fluctuation of high level: -2 to +2 fVIIC cycles When the setting value (CCR value) of bits CCR4 to CCR0 is 5 (00100b) in high-speed clock mode, the maximum bit rate should be 400 kbps in high-speed clock mode. The bit rate and duty cycle are as follows. • Bit rate: f VIIC fVIIC -------------------------------------- = -------------2 × CCR value 10 When fVIIC is 4 MHz, the bit rate is 400 kbps. • Duty cycle is 35 to 45% Even if the bit rate is 400 kbps, the minimum low period of SCLMM clock of 1.3 μs (I2C-bus standard) is ensured. Table 25.12 lists Bit Setting of Bits CCR4 to CCR0 and Bit Rate (fVIIC = 4 MHz). Table 25.12 CCR4 0 0 0 0 0 0 0 : 1 1 1 CCR3 0 0 0 0 0 0 0 : 1 1 1 Bit Setting of Bits CCR4 to CCR0 and Bit Rate (fVIIC = 4 MHz) Bit Rate (kbps) Standard Clock Mode Do not set (1) Do not set (1) Do not set (1) Do not set (2) Do not set (2) 100 83.3 : 17.2 16.6 16.1 High-Speed Clock Mode Do not set (1) Do not set (1) Do not set (1) 333 250 400 166 : 34.5 33.3 32.3 CCR2 0 0 0 0 1 1 1 : 1 1 1 CCR1 0 0 1 1 0 0 1 : 0 1 1 CCR0 0 1 0 1 0 1 0 : 1 0 1 Bits CCR4 to CCR0 in the S20 Register Notes: 1. Bits CCR4 to CCR0 should not be set to 0 to 2 regardless of the fVIIC frequency. 2. The maximum bit rate is 100 kbps in standard clock mode and 400 kbps in high-speed clock mode. Do not exceed the maximum bit rate. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 596 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.3.1.3 Slave Address Receive in Wait Mode and Stop Mode When the CM02 bit in the CM0 register is set to 0 (peripheral clock f1 does not stop in wait mode) and wait mode is entered, the I2C interface receives slave address even in wait mode. When the CM02 bit in the CM0 register is set to 1 (peripheral clock f1 stops in wait mode), and wait mode, stop mode, or low-power consumption mode is entered, the I2C interface stops operating because fVIIC also stops. The SCL/SDA interrupt can be used in both wait mode and stop mode. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 597 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.3.2 Generation of Start Condition Follow the procedure below when the ES0 bit in the S1D0 register is 1 (I2C interface enabled) and the BB bit in the S10 register is set to 0 (bus free). Figure 25.6 shows Start Condition Generation Procedure. (1) Write “E0h” to the S10 register. The I2C interface enters the start condition standby state and the SDAMM pin is left open. (2) Write a slave address to the S00 register. A start condition is generated. Then, the bit counter becomes 000b, the SCL clock signal is output for one byte, and the slave address is transmitted. Write access to the S10 register is disabled during 1.5 fVIIC cycles after a stop condition is generated and the BB bit becomes 0 (bus free). Therefore, when writing E0h to the S10 register and a slave address to the S00 register during the 1.5 fVIIC cycles, start condition standby state is not entered, and a start condition is not generated accordingly. When generating a start condition immediately after the falling edge of the BB bit, check both TRX and MST bits are 1 after the procedure (1), and then execute the procedure (2). Start condition generated Interrupt disabled BB bit in the S10 register = 0? 1 (Bus busy) Bus status checked 0 (Bus free) Set E0h to the S10 register Start condition standby Set slave address to the S00 register Start condition trigger generated Interrupt enabled Completed Figure 25.6 Start Condition Generation Procedure REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 598 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface The start condition generation timing depends on the modes (standard clock mode or high-speed clock mode). Figure 25.7 shows Start Condition Generation Timing. Table 25.13 lists Setup/Hold Time for Start/Stop Condition Generation. Write signal to the S00 register SCLMM Setup Hold SDAMM Setup BB bit BB bit in the S10 register Figure 25.7 Start Condition Generation Timing Table 25.13 Setup/Hold Time for Start/Stop Condition Generation Item STSPSEL Bit Standard Clock Mode fVIIC cycles fVIIC = 4 MHz 5.0 μs 13.0 μs 5.0 μs 13.0 μs SSC value – 1 ------------------------------------ + 2 2 High-speed Clock Mode fVIIC cycles 10 26 10 26 3.5 fVIIC = 4MHz 2.5 μs 6.5 μs 2.5 μs 6.5 μs 0.875 μs Setup time 0 (short mode) 20 1 (long mode) Hold time BB bit set/ reset time 1 (long mode) 52 52 0 (short mode) 20 3.375 μs (1) -: 0 or 1 STSPSEL: Bit in the S2D0 register SSC value: Value of bits SSC4 to SSC0 in the S2D0 register Note: 1. Example value when bits SSC4 to SSC0 are 11000b. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 599 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.3.3 Generation of Stop Condition Follow the procedure below when the ES0 bit in the S1D0 register is 1 (I2C interface enabled). (1) Write C0h to the S10 register. The I2C interface enters the stop condition standby state and the SDAMM pin is driven low. (2) Write a dummy data to the S00 register. A stop condition is generated. The stop condition generation timing depends on the modes (standard clock mode or high-speed clock mode). Figure 25.8 shows Sop Condition Generation Timing. Refer to Table 25.13 “Setup/Hold Time for Start/Stop Condition Generation” for setup/hold time. Write signal to the S00 register SCLMM Setup Hold SDAMM Setup BB bit BB bit in the S10 register Figure 25.8 Sop Condition Generation Timing The S10 register or S00 register should not be written until the BB bit in the S10 register becomes 0 (bus free) after the instructions to generate a stop condition (refer to above (2)) are executed. If the SCLMM pin input signal becomes low until the BB bit in the S10 register becomes 0 (bus free) from the instruction to generate a stop condition is executed and the SCLMM pin becomes high-level, the internal SCL output becomes low. In this case, perform one of the procedures below to stop the low signal output from the SCLMM pin (leave the SCLMM pin open). • Generate a stop condition (perform the procedures (1) and (2) described previously). • Set the ES0 bit in the S1D0 register to 0 (I2C interface disabled). • Write a 1 to the IHR bit (I2C interface reset). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 600 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.3.4 Generation of Restart Condition Follow the procedure below to generate a restart condition when one-byte data is transmitted/received. (1) Write E0h to the S10 register. (Start condition standby state. SDAMM pin becomes highimpedance.) (2) Wait until the SDAMM pin level becomes high. (3) Write a slave address to the S00 register (a start condition trigger generated) Figure 25.9 shows Restart Condition Generation Timing. SCLMM 8 9 (ACK clock) SDAMM Write signal to the S10 register (Start condition standby) Wait until the SDAMM becomes high level. Write signal to the S00 register (Start condition trigger generation) Figure 25.9 Restart Condition Generation Timing REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 601 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.3.5 Start Condition Overlap Protect I2C The interface generates a start condition by setting registers S10 and S00 by a program. The bus system must be free before setting these registers. Check whether the bus is free with the BB bit in the S10 register by a program before setting the registers. However, even if the bus system is checked free, other master devices may generate a start condition before setting registers S10 and S00. In this case, when the I2C interface detects the start condition, the BB bit becomes 1 (bus busy) and the start condition overlap protect function is performed. The start condition overlap protect function operates as follows. • The start condition standby state is not entered even if the S10 register is set to E0h. • If the I2C interface is in the start condition standby state, exit the state. • A start condition trigger is not generated even if a data is written to the S00 register by program. • Bits MST and TRX in the S10 register are set to 0 (slave-receiver mode). • The AL bit in the S10 register becomes 1 (arbitration lost detected). Figure 25.10 shows Start Condition Overlap Protect Operation. The following is an example for start condition overlap protect operation if start condition is generated by an external device in start condition standby state SCLMM Start condition set by an external device SDAMM Bus busy BB bit in the S10 register Bus free Start condition overlap protect operates Check that BB bit is 0 (bus free) by a program Enter the start condition standby state by a program Start condition standby state exited Start condition trigger generation disabled AL bit becomes 1 AL bit in the S10 register MST bit in the S10 register TRX bit in the S10 register 1.5 fVIIC cycles Figure 25.10 Start Condition Overlap Protect Operation The start condition overlap protect is enabled from the falling edge of SDAMM (start condition) to the completion of the slave address receive. If data is written to register S10 and S00 during the period, the above operation is performed. Figure 25.11 shows Start Condition Overlap Protect Function Enable Period. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 602 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface SCLMM 1 2 3 8 9 ACK clock SDAMM 1st bit 2nd bit 3rd bit 8th bit ACK bit BB bit in the S10 register Start condition overlap protect function enabled Figure 25.11 Start Condition Overlap Protect Function Enable Period REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 603 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.3.6 Arbitration Lost When the following conditions are all met, the signal level of SDAMM pin becomes low by an external device and the I2C interface determines that it has lost arbitration. (1) Transmit/receive (one of the following) • Slave address transmit in master-transmitter mode or master-receiver mode • Data transmit (ACK clock not included) in master-transmitter mode • Start condition generated in master-transmitter mode or master-receiver mode • Stop condition generated in master-transmitter mode or master-receiver mode (2) Internal SDA output: High (3) SDAMM pin level: Low (sampling at the rising edge of the clock of SCLMM pin.) Figure 25.12 shows Operation Example When Arbitration Lost is Detected. During slave address transmission for example: Slave address 1 2 3 4 5 6 7 ACK clock 9 SCLMM SDAMM Internal SDA output Levels matched SDA line open Levels not matched Arbitration lost detected AL bit in the S10 regiser PIN bit in the S10 regiser TRX bit in the S10 regiser MST bit in the S10 regiser IR bit in the IICIC register Set to 0 by interrupt request acceptance or by a program Figure 25.12 Operation Example When Arbitration Lost is Detected When arbitration lost is detected, • The AL bit in the S10 register becomes 1 (arbitration lost detected) • Internal SDA output becomes high. (SDAMM becomes high-impedance) • Slave-receiver mode is entered by setting the TRX bit in the S10 register to 0 (receive mode) and the MST bit in the S10 register to 0 (slave mode). In order to write the AL bit to 0 again after arbitration lost is detected, set a value to the S00 register. When arbitration is lost in slave address transmission, the I2C interface enters the slave-receiver mode automatically and receives slave address which sent from another master. When the ALS bit in the S1D0 register is 1 (addressing format), slave address comparison result is determined by reading bits ADR0 and AAS in the S10 register When arbitration is lost during data transmission, slave-receiver mode is automatically entered. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 604 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.3.7 Start Condition and Stop Condition Detection Figure 25.13 shows Start Condition Detection, Figure 25.14 shows Stop Condition Detection, and Table 25.14 lists Conditions to Detect Start/Stop Condition. Start/Stop condition is detected only when the start/stop condition detect conditions (SCL open time, setup time, and hold time) are selected by bits SSC4 to SSC0 in the S2D0 register, and the signals input to pins SCLMM and SDAMM meet all three conditions (SCLMM open time, setup time, and hold time) listed in Table 25.14. The BB bit in the S10 register becomes 1 when a start condition is detected. It becomes 0 when a stop condition is detected. The set timing and reset timing of the BB bit depends on the mode, standard mode or high-speed clock mode. Refer to BB bit set/reset time in Table 25.15. Table 25.15 lists Recommended SSCi (i = 0 to 4) Bit Value in Standard Clock Mode. SCLMM open SCLMM SDAMM Setup Hold Setting BB bit BB bit in the S10 register TRX bit in the S10 register (In slave mode) Bits BC2 to BC0 in the S1D0 register 000b Figure 25.13 Start Condition Detection REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 605 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface SCLMM open SCLMM SDAMM Setup Hold Resetting BB bit BB bit TRX MST BC2 to BC0 000b 0.5 fVIIC cycles Figure 25.14 Stop Condition Detection REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 606 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface Table 25.14 Conditions to Detect Start/Stop Condition Standard Clock Mode SCLMM open time SSC value + 1 cycle Setup time SSC value --------------------------- + 1 cycles 2 SSC value --------------------------- cycles 2 BB bit set/ reset time High-speed Clock Mode 4 cycles 2 cycles Hold time 2 cycles 3.5 cycles SSC value – 1 + 2 cycles -----------------------------------2 Unit: fVIIC cycles SSC value: Value of bits SSC4 to SSC0 in the S2D0 register Table 25.15 Recommended SSCi (i = 0 to 4) Bit Value in Standard Clock Mode fVIIC SSC Value Start/stop Condition (recommen SCLMM Open Setup Time ded) Time 11110b 11010b 11000b 01100b 01010b 00100b 6.2 μs (31) 6.75 μs (27) 6.25 μs (25) 6.5 μs (13) 5.5 μs (11) 5.0 μs (5) 3.2 μs (16) 3.5 μs (14) 3.25 μs (13) 3.5 μs (7) 3.0 μs (6) 3.0 μs (3) Hold Time 3.0 μs (15) 3.25 μs (13) 3.0 μs (12) 3.0 μs (6) 2.5 μs (5) 2.0 μs (2) BB Bit Set/reset Time 4.125 μs (16.5) 3.625 μs (14.5) 3.375 μs (13.5) 3.75 μs (7.5) 3.25 μs (6.5) 3.5 μs (3.5) 5 MHz 4 MHz 2 MHz 1 MHz SSC value: Value of bits SSC4 to SSC0 in the S2D0 register ( ): fVIIC cycles REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 607 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.3.8 Operation After Completion of Slave Address/Data Transmit/Receive After completing transmission/reception of slave address or one-byte data, the PIN bit in the S10 register is set to 0 (interrupt requested) at the falling edge of ACK clock. The IR bit in the IICIC register becomes 1 (interrupt requested) at the same time. The value in the S10 register and so on changes depending on the state of transmit/receive data, and the level of pins SCLMM and SDAMM. Figure 25.15 shows Operation After Completion of Slave Address/Data Transmit/Receive. SCLMM SCLMM pin outputs low when PIN bit is 0 ACK clock SDAMM PIN bit in the S10 register Bits BC2 to BC0 in the S1D0 register MST bit in the S10 register TRX bit in the S10 register A/A 000b (When arbitration is lost) (When no ACK is returned in slave transmit mode) 2 fVIIC cycles TRX bit in the S10 register ADR0 bit in the S10 register 1 fVIIC cycles (R/W bit is set to 1 in slave address receive mode (General call in slave address receive mode) (General call address or normal address matches in slave address receive mode) AAS bit in the S10 register IR bit in the IICIC register Set to 0 by an interrupt request acceptance or by a program Figure 25.15 Operation After Completion of Slave Address/Data Transmit/Receive REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 608 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.3.9 Timeout Detection If the SCL clock is stopped in transmit/receive mode, each device stops operating, keeping the communication state. Timeout detection is a function to detect timeout and generate an I2 C-bus interrupt request when the SCLMM pin is driven high for more than the selected timeout detection period in transmit/receive mode. Figure 25.16 shows Timeout Detect Timing. Refer to “TOSEL (Timeout Detection Period Select Bit) (b2)” of 25.2.8 “I2C0 Control Register 2 (S4D0)” for timeout detection period. When the TOE bit in the S4D0 register is 1 (timeout detection enabled): SCLMM 1 2 3 SDAMM 1st bit 2nd bit 3rd bit BB bit in the S10 register TOF bit in the S4D0 register Timeout period (1) IR bit in the IICIC register Set to 0 by interrupt request acceptance or by a program Note: 1. Select by the TOSEL bit in the S4D0 register. Figure 25.16 Timeout Detect Timing Timeout is detected when the following conditions are all met: • The TOE bit in the S4D0 register is set to 1 (timeout detection enabled) • The BB bit in the S10 register is set to 1 (bus busy) • Driving the SCLMM pin high for more than timeout detect period When the timeout is detected, • the TOF bit in the S4D0 register becomes 1 (timeout detected) • the IR bit in the IICIC register becomes 1 (I2C-bus interrupt requested) When the timeout is detected, perform one of the following. • Set the ES0 bit in the S1D0 register to 0 (disabled). • Set the IHR bit in the S1D0 register to 1 (I2C interface reset). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 609 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.3.10 Data Transmit/Receive Examples The data transmit/receive examples are described in this section. The conditions for the examples are follows. • Slave address: 7 bits • Data: 8 bits • ACK clock • Standard clock mode, bit rate: 100 kbps (fIIC: 20 MHz, fVIIC: 4 MHz) 20 MHz (fIIC) divided-by-5 = 4 MHz (fVIIC), 4 MHz (fVIIC) divided-by-8 and further divided-by-5 =100 kbps (bit rate) • In receive mode, ACK response is sent for other than the last data. NACK is returned after the last data is received. • When receiving data, I2C-bus interrupt at 8th clock (just before ACK clock): disabled • Stop condition interrupt: enabled • Timeout interrupt: disabled • Set an own slave address to the S0D0 register (registers S0D1 or S0D2 should not be used) If an I2C-bus interrupt at 8th clock (just before ACK clock) is enabled in data receive, a receiver generates ACK or NACK after each byte of data has been received. 25.3.10.1 Initial Setting Follow the initial setting procedures below for 25.3.10.2 to 25.3.10.5. (1) Write an own slave address to bits SAD6 to SAD0 in the S0D0 register. (2) Write 85h to the S20 register. (CCR value: 5, standard mode selected, ACK clock presents) (3) Write 18h to the S4D0 register. (fVIIC: fIIC divided-by-5, timeout interrupt disabled) (4) Write 01h to the S3D0 register. (stop condition detect interrupt enabled and I2C-bus interrupt at 8th clock is disabled when receiving data) (5) Write 0Fh to the S10 register. (slave-receiver mode) (6) Write 98h to the S2D0 register (SSC value: 18h, start/stop condition generation timing: long mode) (7) Write 08h to the S1D0 register (bit counter: 8, I2C interface enabled, addressing format, input level: I2C-bus input) If the MCU uses a single-master system and it is a master, start the initial setting procedures from (2). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 610 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.3.10.2 Master Transmission The master transmission is described in this section. The initial settings described in 25.3.10.1 “Initial Setting” are assumed to be completed. Figure 21.17 shows the operation of master transmission. The following programs (A) to (C) are executed at the (A) to (C) in Figure 25.17, respectively. S: Start condition P: Stop condition m S Slave address (7 bits) A: ACK A: NACK s WA m Data (8 bits) R: Read W: Write s A m: Master outputs to SDA s: Slave outputs to SDA m Data (8 bits) s A/A m P SCLMM SDAMM Set to 0 by interrupt request acceptance or by program IR bit in the IICIC register (C) End of master transmission Stop condition (B) Data transmission (A) Slave address transmission Figure 25.17 Example of Master Transmission (A) Slave address transmission (1) The BB bit in the S10 register must be 0 (bus free). (2) Write E0h to the S10 register. (Start condition standby) (3) Write a slave address to the seven most significant bits (MSB) and a 0 to the least significant bit (LSB). (Start condition generated, then slave address transmitted) (B) Data transmission (in I2C-bus interrupt routine) (1) Write transmit data to the S00 register. (data transmission) (C) Completion of Master transmission (in I2C-bus interrupt routine) (1) Write C0h to the S10 register. (Stop condition standby state) (2) Write a dummy data to the S00 register. (stop condition generated) When the transmission is completed or ACK is not returned from slave device (NACK returned), master transmission should be completed as above. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 611 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.3.10.3 Master Reception The master reception is described in this section. The initial settings described in 25.3.10.1 “Initial Setting” are assumed to be completed. Figure 25.18 shows the operation example of master reception. The following programs (A) to (D) are executed at the (A) to (D) in Figure 25.18, respectively. S: Start condition P: Stop condition m S Slave address (7 bits) A: ACK A: NACK s RA Data (8 bits) R: Read W: Write m A m: Master outputs to SDA s: Slave outputs to SDA s Data (8 bits) A m P SCLMM SDAMM Set to 0 by interrupt request acceptance or by program IR bit in the IICIC register (B) Data reception 1 (A) Slave address transmission (C) Data reception 2 (D) End of master reception Stop condition Figure 25.18 Example of Master Reception (A) Slave address transmission (1) The BB bit in the S10 register must be 0 (bus free). (2) Write E0h to the S10 register. (Start condition standby) (3) Write a slave address to the seven most significant bits (MSB) and a 0 to the least significant bit (LSB). (Start condition generated, then slave address transmitted) (B) Data reception 1 (after slave address transmission) (In I2C-bus interrupt routine) (1) Write AFh to the S10 register. (Master-receiver mode) (2) Set the ACKBIT bit in the S20 register to 0 (ACK presents) because the data is not the last one. (3) Write a dummy data to the S00 register (C) Data reception 2 (data reception) (In I2C-bus interrupt routine) (1) Read the received data from the S00 register (2) Set the ACKBIT bit in the S20 register to 1 (no ACK) because the data is the last one. (3) Write a dummy data to the S00 register (D) End of master reception (In I2C-bus interrupt routine) (1) Read the received data from the S00 register (2) Write C0h to the S10 register. (Stop condition standby state) (3) Write a dummy data to the S00 register (stop condition generated) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 612 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.3.10.4 Slave Reception The slave reception is described in this section. The initial settings described in 225.3.10.1 “Initial Setting” are assumed to be completed. Figure 25.19 shows the example of slave reception. The following programs (A) to (C) are executed at the (A) to (C) in Figure 25.19, respectively. S: Start condition P: Stop condition m S Slave address (7 bits) A: ACK A: NACK s WA m Data (8 bits) R: Read W: Write s A m: Master outputs to SDA s: Slave outputs to SDA m Data (8 bits) s A/A m P SCLMM SDAMM Set to 0 by interrupt request acceptance or by program IR bit in the IICIC register (A) Start of slave reception (B) Data reception 1 (C) Data reception 2 End of slave reception Figure 25.19 Example of Slave Reception (A) Slave receive is started. (In I2C-bus interrupt routine) (1) Check the content of S10 register. When the TRX bit is 0, the I2C interface is in slave-receiver mode. (2) Write a dummy data to the S00 register. (B) Data reception 1 (In I2C-bus interrupt routine) (1) Read the received data from the S00 register. (2) Set the ACKBIT bit in the S20 register to 0 (ACK presents) because the data is not the last one. (3) Write a dummy data to the S00 register. (C) Data reception 2 (In I2C-bus interrupt routine) (1) Read the received data from the S00 register (2) Set the ACKBIT bit in the S20 register to 1 (no ACK presents) because the data is the last one. (3) Write a dummy data to the S00 register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 613 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.3.10.5 Slave Transmission The slave transmission is described in this section. The initial settings described in 25.3.10.1 “Initial Setting” are assumed to be completed. Figure 25.20 shows the example of slave transmission. The following programs (A) to (B) are executed at the (A) and (B) in Figure 25.20, respectively. S: Start condition P: Stop condition m S Slave address (7 bits) A: ACK A: NACK s RA Data (8 bits) R: Read W: Write m A m: Master outputs to SDA s: Slave outputs to SDA s Data (8 bits) A m P SCLMM SDAMM Set to 0 by interrupt request acceptance or by program IR bit in the IICIC register (A) Start of slave transmission (B) Data transmission Stop condition Figure 25.20 Example of Slave Transmission (A) Start of slave transmission (In I2C-bus interrupt routine) (1) Check the content of the S10 register. When the TRX bit is set to 1, the I2C interface is in slavetransmitter mode. (2) Write a transmit data to the S00 register (B) Data transmission (In I2C-bus interrupt routine) (1) Write a transmit data to the S00 register Write a dummy data to the S00 register even if an interrupt occurs at an ACK clock of the last transmit data. When the S00 register is written, the SCLMM pin becomes high-impedance. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 614 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.4 I2C Interrupts interface generates an interrupt request. Figure 25.21 shows I2C Interface Interrupts, and Table 25.16 lists I2C-bus Interrupts. I2C-bus Interrupt ACKCLK bit in the S20 register Falling edge of the last bit clock of transmit/receive data detected Falling edge of the ACK clock detected WIT bit in the S3D0 register Falling edge of the last bit clock of received data detected TRX bit in the S10 register MST bit in the S10 register ASL bit in the S1D0 register AAS bit in the S10 register (General call detected) ADR0 bit in the S10 register (Slave address match detected) (Data received) (Data transmit/receive completed) PIN I2C-bus interrupt request (to the IR bit in the IICIC register) Slave address reception completed Slave address transmission completed SIM bit in the S3D0 register Stop condition detected TOE bit in the S4D0 register Timeout detected (Slave address reception completed by address match detection disabled) SCPIN bit in the S4D0 register (Stop condition detected) TOF bit in the S4D0 register (Timeout detected) SCL/SDA Interrupt S2D0 register SIS=1 SCLMM SDAMM SIS=0 SIP bit in the S2D0 register SCL/SDA interrupt request (to IR bit in the SCLDAIC register) Edge selector Figure 25.21 I2C Interface Interrupts REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 615 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface Table 25.16 I2C-bus Interrupts Interrupt Interrupt Source Associated Bits (Register) Interrupt enabled Interrupt request PIN (S10) Interrupt Control Register IICIC — I2C-bus Completion of data transmit/receive When the ACKCKL = 0, Interrupt Detection of the falling edge of the last clock of transmit/receive data through SCLMM pin When the ACKCKL = 1, Detection of the falling edge of ACK clock through SCLMM pin Data reception (before ACK clock) Detection of the falling edge of the last clock of transmit/receive data through SCLMM pin WIT (S3D0) — Detection of slave address match Received slave address matches bits SAD6 to SAD0 in slave-receiver mode with addressing format (AAS bit in the S10 register = 1) Detection of general call General call in slave-receiver mode with addressing format (ADR0 bit in the S10 register = 1) Completion of receiving slave address in slave-receiver mode with free format Stop condition detected Timeout detected SCL/ SDA interrupt SIM (S3D0) TOE (S4D0) SCPIN (S4D0) TOF (S4D0) — SCLDAIC Detection of the falling edge or rising edge of — input/output signal for the SCLMM or SDAMM pin Refer to 14.7 “Interrupt Control”. Table 25.17 lists Registers Associated with I2C Interface Interrupts. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 616 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface Table 25.17 Registers Associated with I2C Interface Interrupts Address 007Bh 007Ch 0206h Register Name SCL/SDA Interrupt Control Register Interrupt Source Select Register 2 Register Symbol SCLDAIC IFSR2A Value After Reset XXXX X000b XXXX X000b 00h IICBus Interface Interrupt Control Register IICIC When using the I2C-bus interface interrupt, set the IFSR22 bit in the IFSR2A register to 1 (I2C-bus interrupt). When using SCL/SDA interrupt, set the IFSR23 bit in the IFSR2A register to 1 (SCL/SDA interrupt). The SCL/SDA interrupt is enabled even in wait mode and stop mode. The IR bit in the SCLDAIC register may become 1 (interrupt requested) when the ES0 bit in the S1D0 register, SIP bit in the S2D0 register, or SIS bit in the S2D0 register is changed. Therefore, follow the procedure below to change these bits. Refer to 14.13 “Notes on Interrupts”. (1) Set bits ILVL2 to ILVL0 in the SCLDAIC register to 000b (interrupt disabled). (2) Set the ES0 bit in the S1D0 register and bits SIP and SIS in the S2D0 register. (3) Set the IR bit in the SCLDAIC register to 0 (no interrupt request). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 617 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 25. Multi-Master I2C-bus Interface 25.5 25.5.1 Notes on Multi-Master I2C-bus Interface Limitation on CPU Clock When the CM07 bit in the CM0 register is 1 (CPU clock is a sub clock), do not access the registers listed in Table 25.4 “Register Configuration”. Set the CM07 bit to 0 (main clock, PLL clock, or on-chip oscillator clock) to access these registers. 25.5.2 Register Access Notes are described to access the I2C interface control registers. The period from the rising edge of 1st clock of slave address or one-byte data transmission/reception to the falling edge of an ACK clock is considered as “period of transmission/reception”. When the ACKCLK bit is 0 (no ACK clock), the period of transmission/reception is from the rising edge of 1st clock of slave address or one-byte data transmission/reception to the falling edge of 8th clock. 25.5.2.1 S00 Register Do not write to the S00 register during transmission/reception. 25.5.2.2 S10 Register Do not change bits other than the IHR bit in the S10 register during transmission/reception. 25.5.2.3 S20 Register Do not change bits other than the ACKBIT bit in the S20 register during transmission/reception. 25.5.2.4 S3D0 Register • Do not use the bit managing instruction (read-modify-write instruction) to access the S3D0 register. • Bits ICK1 and ICK0 should be changed when the ES0 bit in the S1D0 register is 0 (I2C interface disabled). 25.5.2.5 S4D0 Register Bits ICK4 to ICK2 should be changed when the ES0 bit in the S1D0 register is 0 (I2C interface disabled). 25.5.2.6 S10 Register • Do not use the bit managing instruction (read-modify-write instruction) to access the S10 register. • Do not write to the S10 register when bits MST and TRX change their values. Figure 25.13 “Start Condition Detection” to Figure 25.15 “Operation After Completion of Slave Address/ Data Transmit/Receive” shows when bits MST and TRX change. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 618 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function 26. Consumer Electronics Control (CEC) Function 26.1 Introduction The CEC function indicates circuitry which supports the transmission and reception of CEC signals standardized by the HDMI (High-Definition Multimedia Interface). Table 26.1 and Table 26.2 list CEC function specifications, Figure 26.1 shows CEC Function Block Diagram and Table 26.3 lists I/O Pin. Table 26.1 CEC Function Specifications (1/2) Item Count source Specification fC, timer A0 underflow In either case, the frequency should be 32.768 kHz and oscillation allowable error should be within ± 1%. Start bit: 1 bit Data bit: 8 bits EOM bit: 1 bit ACK bit: 1 bit Before transmission starts, satisfy the following requirement. • The CTXDEN bit in the CECC3 register = 1 (transmission enabled) Before reception starts, satisfy the following requirements. • The CRXDEN bit in the CECC3 register = 1 (reception enabled) • Start bit detected Transmit interrupt • When 8 bits of data is transmitted completely. • When 10 bits of data is transmitted completely. Transmit error interrupt • When transmit arbitration lost occurs. • When NACK is received in transmission (ACK received in Broadcast transmission). Receive interrupt • When 8 bits of data is received completely. • When 10 bits of data is received completely. • The above receive interrupts can be confined to when matching Destination address or in Broadcast • When the start bit is received completely. Receive error interrupt • A signal out of the acceptable range is received. Arbitration lost If one of the following conditions occurs during transmission, arbitration lost is detected: • When changing the CEC pin from Hi-Z to low output, the pin level is already low. • When changing the CEC pin from low output to Hi-Z, the pin level remains low even after being out of the acceptable range. Transmission error A value of the CCTBA bit in the CCTB2 register matches a value of the CTNACK bit in the CECC2 register. Acceptable range error Low or high period of the data bit is out of the acceptable range. Data format Transmission start condition Reception start condition Interrupt request generation timing Error detection REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 619 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function Table 26.2 CEC Function Specifications (2/2) Item Select functions Specification Digital filter enabled/disabled Transmission stop selected Transmission stop by receiving ACK or NACK can be selected. Arbitration lost detection conditions One of the following conditions can be selected. • When transmitting the start bit and the data bit of Initiator address • When transmitting the start bit and all data bits Transmit rising timing selected • Selected from 8 levels, standard value -180 μs to standard value +30μs Transmit falling timing selected • Start bit: standard value -160μs to standard value • Data bit: selectable from 4 levels, standard value -310 μs to standard value Receive edge detection selected One of the following conditions can be selected. • Only a falling edge detected • Both falling and rising edges detected ACK output in receiving process One of the following conditions can be selected. • Inserted by program Set by the CCRBAO bit of CCRB2 register. • Inserted by hardware ACK is output when matching Destination address. Otherwise, NACK is output. Start bit acceptable range • Select ± 200μs or ± 300μs Data bit acceptable range One of the following conditions can be selected. • Period between a falling edge and a rising edge ± 200 μs, Period between a falling edge and a falling edge ± 350 μs • Period between a falling edge and a rising edge ± 300 μs, Period between a falling edge and a falling edge ± 500 μs Low pulse output when receive error occurs • Whether error low pulse is output or not can be selected when the receive error occurs. Low pulse output wait control when receive error occurs. One of the following conditions can be selected. • Error low pulse is output in synchronization with the rising edge of the CEC input signal if the CEC input signal is low level when the receive error occurs. • Error low pulse is output immediately after the error occurs regardless of the CEC input signal state. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 620 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function CCLK1 to CCLK0 fC Timer A underflow 00b 01b Clock control circuit CTNACK, CTACKEN CCTB1 Providing to CEC blocks (32.768kHz) PCR4 CEC CTXDEN CCTBE CTFLG Transmission circuit CRACK ACK output 0 1 CTD8FLG Detect transmission of 8 bits of data CCRBAO Address comparator CSTRRNG CRRNG CRADRI1 CRADRI2 Detect Destination address match or Broadcast CRXDEN 0 Digital filter CFIL Start bit detection CDATRNG CRFLG 0/1 determination Receiving circuit CRD8FLG (Detect reception of 8/10 bits of data) CTNACKFLG (Detect NACK in transmission) CCTBA CCRBE CCRBAI CRERRFLG (Receive signals out of acceptable range) CTABTFLG (Detect arbitration lost) 1 CTABTS Arbitration detection CCRB1 CCLK1, CCKL0: Bits in the CECC1 register CRRNG, CTNACK, CTACKEN, CRACK, CTABTS, CFIL, CSTRRNG, CDATRNG: Bits in the CECC2 register CTXDEN, CRXDEN: Bits in the CECC3 register CRFLG, CTFLG, CRERRFLG, CTABTFLG, CTNACKFLG, CRD8FLG, CTD8FLG : Bits in the CECFLG register CCTBE, CCTBA: Bits in the CCTB2 register CCRBE, CCRBAO, CCRBAI: Bits in the CCRB2 register PCR4: Bit in the PCR register CCTB1: CCTB1 register CCRB1: CCRB1 register CRADRI1, CRADRI2: Registers CRADRI1 and CRADRI2 Figure 26.1 CEC Function Block Diagram Table 26.3 I/O Pin Pin Name I/O Type Description CEC Input/Output CEC input and output (N-channel open-drain output) Note: 1. Set the direction bit of the ports sharing a pin to 0 (input mode). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 621 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function 26.2 Registers The registers and the bits of the CEC function are synchronized with the count source. The contents of the register is changed immediately after rewriting the value of the register by a program, while the internal circuit starts to operate from the next count source timing. Table 26.4 Register Structure Address 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh 0366h Register Name CEC Function Control Register 1 CEC Function Control Register 2 CEC Function Control Register 3 CEC Function Control Register 4 CEC Flag Register CEC Interrupt Source Select Register CEC Transmit Buffer Register 1 CEC Transmit Buffer Register 2 CEC Receive Buffer Register 1 CEC Receive Buffer Register 2 CEC Receive Follower Address Set Register 1 CEC Receive Follower Address Set Register 2 Port Control Register Register Symbol CECC1 CECC2 CECC3 CECC4 CECFLG CISEL CCTB1 CCTB2 CCRB1 CCRB2 CRADRI1 CRADRI2 PCR After Reset XXXX X000b 00h XXXX 0000b 00h 00h 00h 00h XXXX XX00b 00h XXXX X000b 00h 00h 0000 0XX0b 26.2.1 CEC Function Control Register 1 (CECC1) CEC Function Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol CECC1 Bit Symbol CECEN CCLK0 Bit Name CEC enable bit Address 0350h Function 0: Disabled 1: Enabled b2 b1 After Reset XXXX X000b RW RW Clock source select bit CCLK1 — (b7-b3) Reserved bits 0 0 1 1 0 1 0 1 : fC : Timer A0 underflow : Do not set : Do not set RW Set to 0. Read as undefined value. RW CECEN (CEC Enable Bit) (b0) Set the CECEN bit to 1 (CEC enabled) when the count source is selected by using bits CCLK1 to CCLK0 and the count source is stable. When the CECEN bit is set to 0 (CEC disabled), the circuit of the CEC function is reset. CCLK1-CCLK0 (Clock Source Select Bit) (b2-b1) Change the clock source when the CECEN bit is set 0 (CEC disabled). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 622 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function 26.2.2 CEC Function Control Register 2 (CECC2) CEC Function Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol CECC2 Bit Symbol Bit Name Address 0351h Function After Reset 00h RW CRRNG Receive edge detection select bit Transmit NACK (ACK) end select bit Transmit NACK (ACK) end control bit ACK output control bit 0: Detects falling edge acceptable range 1: Detects both edges acceptable range 0: End with ACK 1: End with NACK 0: Continue to transmit 1: End with NACK/ACK 0: Inserted by program 1: Inserted by hardware 0: When transmitting start bit and Initiator address 1: When transmitting start bit and all data bits 0: Filter disabled 1: Filter enabled 0: ±200 µs 1: ±300 µs 0: Period between falling edge and rising edge ± 200 µs Period between falling edge and falling edge ± 350 µs 1: Period between falling edge and rising edge ± 300 µs Period between falling edge and falling edge ± 500 µs RW CTNACK CTACKEN CRACK RW RW RW CTABTS Arbitration lost detect condition select bit RW CFIL CSTRRNG Digital filter enable bit Start bit acceptable range select bit RW RW CDATRNG Data bit acceptable range select bit RW CTNACK (Transmit NACK (ACK) End Select Bit) (b1) This bit is enabled when the CTACKEN bit is set to 1 (end with ANCK/ACK). CTACKEN (Transmit NACK (ACK) End Control Bit) (b2) Select the end condition by using the CTNACK bit when the CTACKEN bit is set to 1 (end with NACK/ ACK). CRACK (ACK Output Control Bit) (b3) When the CRACK bit is set 0 (inserted by program), the value of the CCRBAO bit in the CCRB2 register is output as ACK data. When the CRACK bit is set to 1 (inserted by hardware), ACK is output if the received Destination address matches the address selected by the CRADRI1 or CRADRI2 register. Table 26.5 lists ACK Output When Inserted by Hardware. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 623 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function Table 26.5 ACK Output When Inserted by Hardware Received Destination Address Directly address (0000b to 1110b) Broadcast (1111b) Destination Address Address Selected by the CRADRI1 or CRADRI2 Register (Own Address) Matches the received Destination address Not match the received Destination address 1111b (matches the received Destination address) 0000b to 1110b ACK Output ACK NACK ACK NACK CTABTS (Arbitration Lost Detect Condition Select Bit) (b4) When the CEC output is low, the range of detecting arbitration lost if the level becomes Hi-z (rising edge) by the external source can be selected. When the CEC output is Hi-z, arbitration lost is detected regardless of the rage selected by the CTABTS bit, if the level becomes low (falling edge) by the external source. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 624 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function 26.2.3 CEC Function Control Register 3 (CECC3) CEC Function Control Register 3 b7 b6 b5 b4 b3 b2 b1 b0 Symbol CECC3 Bit Symbol CTXDEN CRXDEN Bit Name Address 0352h Function 0: Disabled 1: Enabled 0: Disabled 1: Enabled After Reset XXXX 0000b RW RW RW Transmit enable bit Receive enable bit Receive edge detect flag clear bit EOM disable bit CREGCLR The CREGFLG bit in the CECC4 register becomes 0 by setting 1 to this bit 0: EOM enabled 1: EOM disabled (EOM ignored) RW CEOMI — (b7-b4) RW — No register bits. If necessary, set to 0. Read as undefined value CTXDEN (Transmit Enable Bit) (b0) CRXDEN (Receive Enable Bit) (b1) When changing the value of these bits, transmission/reception is enabled or disabled after one or more cycles of the clock source elapses. CREGCLR (Receive Edge Detect Flag Clear Bit) (b2) The CREGFLG bit in the CECC4 register is set to 0 by setting the CREGCLR bit to 1 when the CEC input is Hi-Z. When the CEC input is low, the CREGFLG bit remain unchanged even if the CREGCLR bit is set to 1. The CREGCLR bit holds the written value. To set the CREGCLR bit to 1 in order to set the CREGFLG bit to 0 again, write 0 and then 1. Figure 26.2 shows Operation of Bits CREGFLG and CREGCLR. CEC Become 1 when CEC is low. CREGFLG bit The CREGFLG bit becomes 0 by setting the CREGCLR bit to 0 when CEC is high. Become 1 when CEC is low. (The CREGFLG bit remain unchanged even if the CREGCLR bit is set to 1) CREGCLR bit CREGCLR: Bit in the CECC3 register CREGFLG: Bit in the CECC4 register Figure 26.2 Operation of Bits CREGFLG and CREGCLR REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 625 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function CEOMI (EOM Disable Bit) (b3) Whether the operation continues or stops can be selected when the EOM is 1. Table 26.6 lists Operation When the EOM is 1. When the CEOMI bit is set to 1 (EOM disabled), data transmission continues even though the EOM is 1. To stop transmitting, set the CTXDEN bit in the CECC3 register to 0 (transmission disabled). Table 26.6 Operation When the EOM is 1 CEOMI Bit 0 Operation When EOM is 1 Reception Subsequent data reception is ignored once the data that the EOM is 1 (wait for start bit) is received. ACK/NACK is returned even if the data that the EOM is 1 is received. Transmission Subsequent data is not transmitted once the data that the EOM is 1 is transmitted. Data is transmitted even if the data that the EOM is 1 is transmitted. 1 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 626 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function 26.2.4 CEC Function Control Register 4 (CECC4) CEC Function Control Register 4 b7 b6 b5 b4 b3 b2 b1 b0 Symbol CECC4 Bit Symbol CRISE0 Bit Name Address 0353h Function b2 b1 b0 After Reset 00h RW RW CRISE1 Rising timing select bit CTXDEN CRISE2 Error low pulse output enabled bit 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0: Standard value 1: Standard value - 30 μs 0: Standard value - 60 μs 1: Standard value - 90 μs 0: Standard value - 120 μs 1: Standard value - 150 μs 0: Standard value - 180 μs 1: Standard value + 30 μs RW RW CABTEN 0: Disabled 1: Enabled RW CFALL0 Falling timing select bit CFALL1 0: Not detected 1: Detected 0: Low pulse output regardless of CEC signal state 1: Low pulse output at the rising edge of the CEC signal Refer to the following. RW RW CREGFLG Receive edge detect flag RO CABTWEN Error low pulse output wait control bit RW CRISE2-CRISE0 (Rising Timing Select Bit) (b2-b0) The rising timing of the signal in transmission is selected. The rising timing is common to the start bit and data bit. CABTEN (Error Low Pulse Output Enable Bit) (b3) When the CABTEN bit is set to 1 (low pulse output enabled in receive error), 3.6 ms of low pulse is output if the data bit in reception is out of the acceptable range. Output timing is selected by the CABTWEN bit. CFALL1-CFALL0 (Falling Timing Select Bit) (b5-b4) The falling timing of the signal in transmission is specified. Table 26.7 Falling Timing of Signal in Transmission Bits CFALL1 to CFALL0 00b 01b 10b 11b Falling Timing Start Bit Standard value Standard value - 40 μs Standard value - 100 μs Standard value - 160 μs Data Bit Standard value Standard value - 190 μs Standard value - 250 μs Standard value - 310 μs REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 627 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function CREGFLG (Receive Edge Detect Flag) (b6) Refer to Figure 26.2 “Operation of Bits CREGFLG and CREGCLR”. Condition to become 0. • Set the CREGCLR bit in the CECC3 register to 1 when the CEC input is Hi-Z. Condition to become 1. • The CEC input is low level. CABTWEN (Error Low Pulse Output Wait Control Bit) (b7) This bit is enabled when the CABTEN bit is set to 1 (low pulse output enabled in reception error). If the receive error occurs when the CABTWEN bit is set to 1 (low pulse output at rising edge of the CEC signal) and the CEC input is low, 3.6 ms of low pulse is output from the rising edge of the CEC signal after the error. If there is no rising edge of the CEC signal within 3.6 ms from the reception error, low pulse is not output because it is assumed that another device outputs error low pulse. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 628 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function 26.2.5 CEC Flag Register (CECFLG) CEC Flag Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol CECFLG Bit Symbol CRFLG CTFLG Bit Name Address 0354h Function 0: Waiting 1: Receiving 0: Waiting 1: Receiving After Reset 00h RW RO RO Receive status flag Transmit status flag Receive error detect flag Arbitration lost detect flag CRERRFLG 0: Not detected 1: Error detected (out of the determinable range) 0: Not detected 1: Detected 0: Not detected 1: NACK detected (when transmitting Directly addressed) ACK detected (in Broadcast) 0: 8th bit not received or 10th bit received 1: 8th bit received 0: 8th bit not transmitted or 10th bit transmitted 1: The 8th bit transmitted 0: Start bit not detected or 8th bit received. 1: Start bit detected RO CTABTFLG RO CTNACKFLG Transmit NACK detect flag RO CRD8FLG 8th bit of data receive flag RO CTD8FLG 8th bit of data transmit flag RO CRSTFLG Start bit detection RO CRFLG (Receive Status Flag) (b0) Condition to become 0. • Waiting Condition to become 1. • Receiving • Error low pulse is being output when the CABTEN bit in the CECC4 register is set to 1 (error low pulse output enabled). CRERRFLG (Receive Error Detect Flag) (b2) Condition to become 0. • Set the CRXDEN bit in the CECC3 to 0 (receive disabled). Condition to become 1. • Low or high period of the data bit is out of the acceptable range CTABTFLG (Arbitration Lost Detect Flag) (b3) Condition to become 0. • Set the CTXDEN bit in the CECC3 register to 0 (transmit disabled). CTNACKFLG (Transmit NACK Detect Flag) (b4) Condition to become 0. • Set the CTXDEN bit in the CECC3 register to 0 (transmit disabled). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 629 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function 26.2.6 CEC Interrupt Source Select Register (CISEL) CEC Interrupt Source Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol CISEL Bit Symbol CRISEL0 CRISEL1 CRISEL2 Bit Name Address 0355h Function 0: Disabled 1: Enabled 0: Disabled 1: Enabled 0: Disabled 1: Enabled After Reset 00h RW RW RW RW 8th bit receive interrupt enable bit 10th bit receive interrupt enable bit Receive error interrupt enable bit CRISELM Receive interrupt mode select bit 0: No limitation of 8th/10th bit receive interrupt 1: 8th/10th bit receive interrupt occurs only when matching Destination address or in Broadcast 0: Disabled 1: Enabled 0: Disabled 1: Enabled 0: Disabled 1: Enabled 0: Disabled 1: Enabled RW CTISEL0 CTISEL1 CTISEL2 CRISELS 8th bit transmit interrupt enable bit 10th bit transmit interrupt enable bit Transmit NACK receive interrupt enable bit Reception start bit interrupt enable bit RW RW RW RW Set the CECEN bit in the CECC1 register to 0 (CEC disabled) to change the CISEL register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 630 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function 26.2.7 CEC Transmit Buffer Register 1 (CCTB1) CEC Transmit Buffer Register 1 b7 b0 Symbol CCTB1 Address 0356h Function After Reset 00h RW RW Sets the transmit data Rewrite the CCTB1 register when the CTXDEN bit in the CECC3 register is set to 0 (transmit disabled), or the CTXDEN bit is set to 1 and the CTD8FLG in the CECFLG register is set to 1 (while bits EOM and ACK are being transmitted after the 8th bit has been transmitted). Do not rewrite the CCTB1 register when the CTXDEN bit is set to 1 and the CTD8FLG bit is set to 0 (while the 1st bit to 8th bit are being transmitted). 26.2.8 CEC Transmit Buffer Register 2 (CCTB2) CEC Transmit Buffer Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol CCTB2 Bit Symbol CCTBE CCTBA — (b7-b2) Bit Name Address 0357h Function 0: Data block continues 1: Data block ends 0: ACK input 1: NACK input After Reset XXXX XX00b RW RW RW — Transmit data EOM bit Transmit data ACK input bit No register bits. If necessary, set to 0. Read as undefined value CCTBE (Transmit Data EOM Bit) (b0) Rewrite the CCTBE bit when the CTXDEN bit in the CECC3 register is set to 0 (transmit disabled), or the CTXDEN bit is set to 1 and the CTD8FLG in the CECFLG register is set to 1 (while bits EOM and ACK are being transmitted after the 8th bit has been transmitted). Do not rewrite the CCTBE bit when the CTXDEN bit is set to 1 and the CTD8FLG bit is set to 0 (while the 1st bit to 8th bit are being transmitted). CCTBA (Transmit Data ACK Input Bit) (bs1) Read the CCTBA bit after transmitting the 10th bit (ACK bit) (the CTD8FLG bit in the CECFLG register changes from 1 to 0). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 631 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function 26.2.9 CEC Receive Buffer Register 1 (CCRB1) CEC Receive Buffer Register 1 b7 b0 Symbol CCRB1 Address 0358h Function After Reset 00h RW RW Reads the receive data. Read the CCRB1 register after receiving the 8th bit (the CRD8FLG bit in the CECFLG register changes from 0 to 1). 26.2.10 CEC Receive Buffer Register 2 (CCRB2) CEC Receive Buffer Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol CCRB2 Bit Symbol CCRBE CCRBAO CCRBAI — (b7-b3) Bit Name Address 0359h Function 0: Data block continues 1: Data block ends 0: ACK output 1: NACK output 0: ACK input 1: NACK input After Reset XXXX X000b RW RO RW RO — Receive data EOM bit Receive data ACK output bit Receive data ACK input bit No register bits. If necessary, set to 0. Read as undefined value CCRBE (Receive Data EOM bit) (b0) Read the CCRBE bit after receiving the 10th bit (ACK bit) (the CRD8FLG bit in the CECFL register changes from 1 to 0). CCRBAO (Receive Data ACK Output Bit) (b1) The CCRBAO bit is valid when the CRACK bit in the CECC2 register is set to 0 (inserted by program). Rewrite the CCRBAO bit when the CRXDEN bit in the CECC3 register is set to 0 (receive disabled), or the CRXDEN bit is set to 1 and the start bit to EOM bit are being received. Do not rewrite the CCRBAO bit when the ACK bit is being transmitted. CCRBAI (Receive Data ACK Input Bit) (b2) Read the CCRBAI bit after the 10th bit (ACK bit) is received (the CRD8FLG bit in the CECFL register changes from 1 to 0). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 632 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function 26.2.11 CEC Receive Follower Address Set Register 1 (CRADRI1), CEC Receive Follower Address Set Register 2 (CRADRI2) CEC Receive Follower Address Set Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol CRADRI1 Bit Symbol CRADRI10 CRADRI11 CRADRI12 CRADRI13 CRADRI14 CRADRI15 CRADRI16 CRADRI17 Bit Name 0000b select bit 0001b select bit 0010b select bit 0011b select bit 0100b select bit 0101b select bit 0110b select bit 0111b select bit Address 035Ah Function 0: Not selected 1: Selected After Reset 00h RW RW RW RW RW RW RW RW RW CEC Receive Follower Address Set Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol CRADRI2 Bit Symbol CRADRI20 CRADRI21 CRADRI22 CRADRI23 CRADRI24 CRADRI25 CRADRI26 CRADRI27 Bit Name 1000b select bit 1001b select bit 1010b select bit 1011b select bit 1100b select bit 1101b select bit 1110b select bit 1111b select bit Address 035Bh Function 0: Not selected 1: Selected After Reset 00h RW RW RW RW RW RW RW RW RW Select the receive follower address (own address). Set the CECEN bit in the CECC1 register to 0 (CEC disabled) to change registers CRADRI1 and CRADRI2. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 633 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function ACK is returned by setting the CRADRI27 bit to 1 (selects 1111b) when the Follower address is 1111b (Broadcast) and the CRACK bit in the CECC2 register is 1 (ACK output in reception is inserted by hardware). When the received Destination address matches the address selected by the CRADRI1 or CRADRI2 register, it may be described as Destination address match in this chapter. 26.2.12 Port Control Register (PCR) Port Control Register b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol PCR Bit Symbol Bit Name Address 0366h Function After Reset 0000 0XX0b RW PCR0 Port P1 control bit When reading the P1 register: 0 : Input level of pins P1_0 to P1_7 is read when the port is set to input. Port latch is read when the port is set to output. 1 : Port latch is read whether the port is set to input or output. RW — (b2-b1) PCR3 PCR4 PCR5 PCR6 PCR7 No register bits. If necessary, set to 0. Read as undefined value Reserved bit CEC output enable bit INT6 input enable bit INT7 input enable bit Key input enable bit Set to 0 0 : CEC output disabled 1 : CEC output enabled 0 : Enabled 1 : Disabled 0 : Enabled 1 : Disabled 0 : Enabled 1 : Disabled RW RW RW RW RW RW PCR4 (CEC Output Enable Bit) (b4) To use the CEC function, set the PCR4 bit to 1 (CEC output enabled). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 634 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function 26.3 26.3.1 Operations Standard Value and I/O Timing The CEC transmission/reception is based on the count source cycle. When outputting, an output waveform is based on the count source cycle which is closest to the CEC standard value. When inputting, an input waveform is sampled in the count source cycle Also, the input/output is practically performed based on the count source cycle closest to the acceptable range or output timing. 26.3.2 Count Source Select fC or timer A0 underflow by bits CCLK1 to CCLK0 in the CECC1 register. In either case, the clock frequency should be 32.768kHz and oscillation allowable error should be within ± 1%. Set the CECEN bit in the CECC1 register to 1 (CEC enabled), after the count source is selected by bits CCLK1 and CCLK0 and when the count source is stable. To use fC, set the PM25 bit in the PM2 register to 1 (peripheral clock fC provided). Refer to 8. “Clock Generator” for details. When the timer A0 underflow is used as the count source, each time timer A0 underflows the internal signal of the timer A0 is reversed. Since this internal signal is the count source, two cycles of timer A0 underflows are one cycle of the count source. Figure 26.3 shows Count Source When Timer A0 Underflow Selected. Use the timer A0 without timer mode and gate function. Refer to 17. “Timer A” for details. Timer A0 underflow cycle Count source (Timer A0 internal signal) Timer A0 underflow cycle Reversed by underflow 1 32.768 kHz Figure 26.3 Count Source When Timer A0 Underflow Selected 26.3.3 CEC Input/Output The CEC input and output share pins with the I/O port and NMI input. To use CEC input and output, set bits as follows: • set the PM24 bit in the PM2 register to 0 (NMI interrupt disabled) • set bits NMIDF2 to NMIDF0 in the NMIDF register to 000b (NMI/SD filter disabled) • set the PCR4 bit in the PCR register to 1 (CEC output enabled) • set the PD8_5 bit in the PD8 register to 0 (input mode) Also, the CEC input has a digital filter besides the NMI/SD filter (refer to 26.3.4 “Digital Filter”). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 635 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function 26.3.4 Digital Filter The input to the CEC pin goes into the internal circuit in synchronization with the count source. If the same level signal is input to the CEC pin twice in a row that level is transferred to the internal circuit, when the CFIL bit in the CECC2 register is set to 1 (digital filter enable). Figure 26.4 shows Digital Filter. Count source CEC pin input Same level Same level Same level Internal CEC input When the CFIL bit is set to 0 (filter disabled) Same level Same level Same level Same level Internal CEC input When the CFIL bit is set to 1 (filter enabled) CFIL: Bit in the CECC2 register Figure 26.4 Digital Filter REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 636 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function 26.3.5 26.3.5.1 Reception Start Bit Detection The detect timing of the start bit and data bit is selected by the CRRNG bit in the CEC2 register. Select the start bit acceptable range by the CSTRRNG bit in the CECC2 register. Figure 26.5 shows Start Bit Acceptable Range. When the start bit within the acceptable range is detected, the CRSTFLG bit in the CECFLG register becomes 1 (start bit detected). When the CRRNG bit is set to 0, When the CRRNG bit is set to 1, Acceptable range When the CSTRRNG bit is set to 0: ±200µs When the CSTRRNG bit is set to 1: ±300µs CEC input Only a falling edge is detected Both edges are detected Acceptable range ±200µs ±300µs 0 ms 3.7 ms 4.5 ms CRRNG, CSTRRNG: Bits in the CECC2 register Figure 26.5 Start Bit Acceptable Range REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 637 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function 26.3.5.2 Data Bit Detection The detect timing of the start bit and data bit (other than start bit) is selected by the CRRNG bit in the CECC2 register. Select the data bit acceptable range by the CDATRNG bit in the CECC2 register. Figure 26.6 shows Data Bit Acceptable Range (CRRNG Bit = 0). When the CRRNG bit is set to 0 (detects falling edge acceptable range), the input data is determined as data 1 if the rising edge is detected before 1.05ms and the input data is determined as data 0 if the rising edge is detected after 1.05 ms. Only a falling edge is detected Acceptable range When the CDATRNG bit is set to 0: ±350µs When the CDATRNG bit is set to 1: ±500µs Determined as data 0 after 1.05ms CEC input (input data: 0) 0ms 1.05ms 2.4ms Only a falling edge is detected Acceptable range When the CDATRNG bit is set to 0: ±350µs When the CDATRNG bit is set to 1: ±500µs Determined as data 1 before 1.05ms CEC input (iput data: 1) 1.05ms 2.4ms 0ms CRRNG and CDATRNG: Bits in the CECC2 register. Figure 26.6 Data Bit Acceptable Range (CRRNG Bit = 0) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 638 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function Both edges are detected Acceptable range Acceptable range When the CDATRNG bit is set to 0: ±200µs When the CDATRNG bit is set to 1: ±300µs CEC input (input data: 0) 0 ms 1.5 ms Both edges are detected ±350µs ±500µs 2.4 ms Acceptable range Acceptable range When the CDATRNG bit is set to 0: ±200µs When the CDATRNG bit is set to 1: ±300µs CEC input (input data: 1) 0.6 ms ±350µs ±500µs 0 ms 2.4 ms CRRNG, CDATRNG: Bits in the CECC2 register Figure 26.7 Data Bit Acceptable Range (CRRNG Bit = 1) If the data bit is out of the acceptable range, the receive error occurs. The operations when the receive error occurs are as follows: • The CRERRFLG bit in the CECFLG register is set to 1 (receive error) • 3.6 ms of low pulse is output when the CABTEN bit in the CECC4 register is set to 1 (low pulse output enabled in receive error). Low pulse output timing can be selected by the CABTWEN bit in the CECC4 register when the CABTEN bit is set to 1 (low pulse output enabled in receive error). Figure 26.8 shows Low Pulse Output in Receive Error. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 639 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function When the CABTWEN bit is set to 0: Low pulse is immediately output regardless of the CEC signal state. Receive error occurs CEC 3.6 ms 3 to 4 cycles of count source When the CABTWEN bit is set to 1: Low pulse is output at the riging edge of the CEC signal. Receive error occurs 3.6 ms Low pulse is output at the rising edge within 3.6 ms after the receive error occurs. CEC 3.6 ms 3 to 4 cycles of count source CEC If the low level lasts for 3.6 ms or longer after the receive error occurs, low pulse is not output even if the rising edge is detected thereafter. The above diagram applies under the following condition. The CABTEN bit in the CECC4 register is set to 1 (low pulse output enabled in receive error). CABTWEN: Bit in the CECC4 register Figure 26.8 Low Pulse Output in Receive Error 26.3.5.3 ACK Bit Output The output value of the 10th bit (ACK bit) can be selected. When the CRACK bit in the CECC2 register is set to 0 (inserted by program), the value of the CCRBAO bit in the CCRB2 register is output as ACK data. When the CRACK bit is set to 1 (inserted by hardware), ACK is output when the received Destination address matches the address selected by the CRADRI1 or CRADRI2 register (own address). Table 26.8 lists ACK Output. Table 26.8 ACK Output CRACK Bit 0 1 CCRBAO Bit 0 1 - Received Destination Address Directly address (0000b to1110b) Broadcast address (1111b) Destination Address Address selected by the CRADRI1 or CRADRI2 Register (Own Address) Matches received Destination address Not match received Destination address 1111b (matches received Destination address) 0000b to 1110b ACK Output ACK NACK ACK NACK ACK NACK REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 640 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function 26.3.5.4 Reception Examples Figure 26.9 shows a Reception Example and Figure 26.10 shows a Reception Example (Change from Error Low Pulse Output Disabled to Enabled When an Error Occurs). When a receive error occurs, the CRERRFLG bit in the CECFLG register becomes 1 (receive error). If a reception ends due to the error during the reception, set the CRXDEN bit in the CECC3 register to 0 (receive disabled). When the CRXDEN bit is set to 0, the CRERRFLG bit becomes 0. To restart the reception, set the CRXDEN bit to 0 (reception disabled), and then set the CRXDEN bit to 1 (reception enabled) after waiting for one or more cycles of the count source. Header block CEC ST H7 H6 .... Data block H0 EOM ACK D7 D6 .... H1 D1 D0 EOM ACK CRXDEN bit CRFLG bit CRSTFLG bit CRD8FLG bit Set to 0 by acceptance of an interrupt request or by a program Set to 0 by acceptance of an interrupt request or by a program IR bit CCRB1 register Undefined Header block data Data block data CCRBE bit Undefined Header block EOM Data block EOM CCRBAI bit Undefined Header block ACK Data block ACK CRXDEN bit: Bit in the CECC3 register Bits CRFLG, CRD8FLG, and CRSTFLG: Bits in the CECFLG register IR bit: Bit in the CEC2IC register Bits CCRBE and CCRBAI: Bits in the CCRB2 register The above diagram applies under the following conditions. The CFIL bit in the CICC2 register is set to 0 (filter disabled). The CRISEL0 bit in the CISEL register is set to 0 (8th bit receive interrupt disabled). The CRISEL1 bit in the CISEL register is set to 1 (10th bit receive interrupt enabled). The CRISELS bit in the CISEL register is set to 1 (reception start bit interrupt enabled). Figure 26.9 Reception Example REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 641 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function Header block CEC ST H7 H3 H2 Error low pulse Set to 0 by a program Receive error occurs CRXDEN bit CABTEN bit CRFLG bit Become 0 in synchronization with the count source CRSTFLG bit 0 Change in synchronization with the count source CRERRFLG bit Set to 0 by acceptance of an interrupt or by a program Become 0 in synchronization with the count source IR bit CCRB1 bit Undefined CCRBE bit Undefined CCRBAI bit Undefined CRXDEN bit: Bit in the CECC3 register Bits CRFLG, CRERRFLG, and CRSTFLG: Bits in the CECFLG register IR bit: Bit in the CEC2IC register Bits CCRBE and CCRBAI: Bits in the CCRB2 register The above diagram applies under the following conditions. The CFIL bit in the CECC2 register is se to 0 (filter disabled) The CABTEN bit in the CECC4 register is set to 1 (error low pulse output enabled) The CRISEL2 bit in the CISEL register is set to 1 (receive error interrupt enabled) The CRISELS bit in the CISEL register is se to 0 (reception start bit interrupt disabled) Figure 26.10 Reception Example (Change from Error Low Pulse Output Disabled to Enabled When an Error Occurs) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 642 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function 26.3.6 26.3.6.1 Transmission Transmit Signal Timing Select Rising or falling timing of the transmit signal can be selected. The rising timing of the transmit signal is selected by bits CRISE2 to CRISE0 in the CECC4 register. Figure 26.11 shows Rising Timing of Transmit Signal. CEC output CRISE2 to CRISE0 = 110b: standard value - 180 ms 101b: standard value - 150 ms 100b: standard value - 120 ms 011b: standard value - 90 ms 010b: standard value - 60 ms 001b: standard value - 30 ms 11b: standard value + 30 ms 000b: standard value Figure 26.11 Rising Timing of Transmit Signal The falling timing of the transmit signal is selected by bits CFALL1 to CFALL0 in the CECC4 register. Figure 26.12 shows Falling Timing of Transmit Signal. Start bit CEC output CFALL1 to CFALL0 = 11b: standard value - 160 ms 10b: standard value - 100 ms 01b: standard value - 40 ms 000b: standard value Data bit CEC output CFALL1 to CFALL0 = 11b: standard value - 310 ms 10b: standard value - 250 ms 01b: standard value - 190 ms 000b: standard value Figure 26.12 Falling Timing of Transmit Signal REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 643 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function 26.3.6.2 Arbitration Lost Detection When data is transmitted, an arbitration lost is detected in the following cases. •The CEC output changes from Hi-Z to low by the external source (falling edge). •The CEC output changes from low to Hi-Z by the external source (rising edge). A range for detecting the arbitration lost the rising edge is selected by the CTABTS bit in the CECC2 register. Figure 26.13 shows Arbitration Lost Detectable Range. When the arbitration lost is detected, the CTABTFLG bit in the CECFLG register becomes 1 (arbitration lost detected). Initiator address CEC ST H7 H6 H5 H4 Destination address H3 H2 H1 H0 EOM ACK D7 ・・・ D0 EOM ACK The detectable range when the CTABTS bit is set to 0 The detectable range when the CTABTS bit is set to 1 CTABTS bit: Bit in the CECC2 register Figure 26.13 Arbitration Lost Detectable Range 26.3.6.3 Transmission Example Figure 26.14 shows a Transmission Example, Figure 26.15 shows a Transmission Example (When NACK Received) and Figure 26.16 shows a Transmission Example (When an Arbitration Lost Detected). Set the CTXDEN bit in the CECC3 register to 0 (transmit disabled) after the transmission. To continue the transmission, set the CTXDEN bit to 0 (transmit disabled) after sending one frame (one header block and one or more data blocks), and wait for one or more cycles of the count source before setting the CTXDEN bit to 1 (transmit enabled). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 644 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function Header block CEC ST H7 H6 H1 H0 EOM ACK D7 D6 Data block D1 D0 EOM ACK Set to 0 by a program Set to 0 by a program CTXDEN bit Transmission starts at the rising edge of the count source CTFLG bit CTD8FLG bit IR bit in the CEC1IC register Set to 0 by acceptance of an interrupt or by a program CCTB1 register Rewritable period by a program (Do not rewrite) Rewritable period by a program (Do not rewrite) 1 Rewritable period by a program Undefined (Do not rewrite) Rewritable period by a program (Do not rewrite) Rewritable period by a program Header block ACK CCTBE bit 0 Rewritable period by a program CCTBA bit Data block ACK CRXDEN bit CRFLG bit CRSTFLG bit CRD8FLG bit IR bit in the CEC2IC register CCRB1 register Set to 0 by acceptance of an interrupt or by a program Set to 0 by acceptance of an interrupt or by a program Undefined Header block data Data block data CCRBE bit Undefined Header block EOM Data block EOM CCRBAI bit Undefined Header block ACK Data block ACK Bits CTXDEN and CRXDEN: Bits in the CECC3 register Bits CTFLG, CTD8FLG, CRFLG, CRD8FLG, and CRSTFLG: Bits in the CECFLG register Bits CCTBE and CCTBA: Bits in the CCTB2 register Bits CCRBE and CCRBAI: Bits in the CCRB2 register The above diagram applies under the following conditions: The CTISEL0 bit in the CISEL register is set to 1 (8th bit transmit interrupt enabled). The CTISEL1 bit in the CISEL register is set to 0 (10th bit transmit interrupt disabled). The CEMOM bit in the CECC3 register is set to 0 (EOM enabled). The CFIL bit in the CECC2 register is set to 0 (filter disabled). The CRISEL0 bit in the CISEL register is set to 0 (8th bit receive interrupt disabled). The CRISEL1 bit in the CISEL register is set to 1 (10th bit receive interrupt enabled). The CRISELS bit in the CISEL register is set to 1 (reception start bit interrupt enabled). Figure 26.14 Transmission Example REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 645 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function Header block CEC ST Set to 1 by a program H7 H6 .... H1 H0 EOM NACK CTXDEN bit Transmission starts at the rising edge of the count source Set to 0 by a program CTFLG bit CTD8FLG bit Becomes 0 in synchronization with the count source. Set to 0 by acceptance of an interrupt or by a program CTNACKFLG bit IR bit CCTB1 register Rewritable period by a program (Do not rewrite) Rewritable period by a program (Do not rewrite) 0/1 Rewritable period by a program Undefined 1 (NACK) CCTBE bit 0 Rewritable period by a program CCTBA bit CTXDEN bit: Bit in the CECC3 register Bits CTFLG, CTD8FLG, and CTNACKFLG: Bits in the CECFLG register IR bit: Bit in the CEC1IC register Bits CCTBE and CCTBA: Bits in the CCTB2 register The above diagram applies under the following conditions. The CTISEL2 bit in the CISEL register is set to 1 (transmit NACK interrupt enabled). The CTNACK bit in the CECC2 register is set to 1, and the CTACKEN bit is 1 (transmission stops with NACK). Figure 26.15 Transmission Example (When NACK Received) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 646 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function Arbitration lost occurs CEC ST H7 H6 H5 H4 H3 H2 H1 H0 EOM ACK Set to 1 by a program Set to 0 by a program CTXDEN bit Transmission starts at the rising edge of the count source CTFLG bit Set to 0 in synchronization with the count source Set to 0 by acceptance of an interrupt or by a program CTABTFLG bit IR bit in the CEC1IC register CCTB1 register Rewritable period by a program (Do not rewrite) CCTBE bit 0 Rewritable period by a program (Do not rewrite) CRXDEN bit CRFLG bit CRSTFLG bit CRD8FLG bit IR bit in the CEC2IC register CCRB1 register Set to 0 by acceptance of an interrupt or by a program Set to 0 by acceptance of an interrupt or by a program Undefined Header block data CCRBE bit Undefined Header block EOM CCRBAI bit Undefined Header block ACK Bits CTXDEN and CRXDEN: Bits in the CECC3 register Bits CTFLG, CTABTFLG, CRFLG, CRD8FLG, and CRSTFLG: Bits in the CECFLG register Bits CCRBE and CCRBAI: Bits in the CCRB2 register CCTBE bit: Bit in the CCTB2 register The above diagram applies under the following conditions: The CTISEL1 bit in the CISEL register is set to 1 (transmit arbitration lost interrupt enabled). The CFIL bit in the CECC2 register is set to 0 (filter enabled). The CRISEL0 bit in the CISEL register is set to 0 (8th bit receive interrupt disabled). The CRISEL1 bit in the CISEL register is set to 1 (10th bit receive interrupt enabled). The CRISELS bit in the CISEL register is set to 1 (reception start bit interrupt enabled). Figure 26.16 Transmission Example (When an Arbitration Lost Detected) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 647 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function 26.4 Interrupts The CEC function has CEC1 interrupt and CEC2 interrupt. Table 26.9 and Table 26.10 list CEC Interrupt Sources. These sources cause a request of CEC1 interrupt or CEC2 interrupt. When the CRISELM bit in the CISEL register is set to 1, the 8th/10th bit receive interrupt request is generated if the received Destination address is either one of the following case: • Matches the address selected by the CRADRI1 or CRADRI2 register. • Broadcast (1111b) Figure 26.17 shows CEC Function Interrupt. Table 26.9 CEC1 Interrupt Sources Type Transmit interrupt Source 8th bit transmitted 10th bit transmitted Interrupt Request Timing When the CTD8FLG bit change from 0 to 1. When the CTD8FLG bit changes from 1 to 0. Interrupt Enable Bit CRISEL0 CRISEL1 Transmit error Arbitration lost interrupt NACK received (Directly address) ACK received (Broadcast) When the CTABTFLG bit changes CTISEL2 from 0 to 1. When the CTNACKFLG bit changes from 0 to 1. CTD8FLG, CTABTFLG, CTNACKFLG: Bits in the CECFLG register Table 26.10 CEC2 Interrupt Sources Interrupt Enable Bit Receive 8th bit received When the CRD8FLG bit changes CRISEL0 interrupt from 0 to 1 (1) 10th bit received When the CRD8FLG bit changes CRISEL1 from 1 to 0 (1) Start bit detected When the CRSTFLG bit changes CRISELS from 0 to 1 Receive error Nonstandard signal received Wen the CRERRFLG bit changes CRISEL2 interrupt from 0 to 1 CRD8FLG, CRSTFLG, CRERRFLG: Bits in the CECFLG register Note: 1. The CRISELM bit in the CISEL register affects the interrupt. Source Type Interrupt Request Timing REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 648 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function CTISEL0 CTD8FLG CEC1 interrupt (IR bit in the CEC1IC register) CTISEL1 CTISEL2 CTABTFLG CTNACKFLG Broadcast Destination address CRISELM CRISEL0 CRD8FLG CEC2 interrupt (IR bit in the CEC2IC register) CRISEL1 CRERRFLG CRISEL2 CRISELS CRSTFLG CRISELS, CTISEL2, CTISEL1, CTISEL0, CRISELM, CRISEL2, CRISEL1, CRISEL0: Bits in the CISEL register CRSTFLG, CTD8FLG, CRD8FLG, CTNACKFLG, CTABTFLG, CRERRFLG: Bits in the CECFLG register Figure 26.17 CEC Function Interrupt For the interrupt request timing, refer to the operation examples. For interrupt control, refer to 14.7 “Interrupt Control”. Table 26.11 lists CEC Function Interrupt-Associated Registers. Table 26.11 CEC Function Interrupt-Associated Registers Address Register Name 006Bh CEC1 Interrupt Control Register 006Ch CEC2 Interrupt Control Register 0205h Interrupt Source Select Register 3 Register Symbol After Reset CEC1IC XXXX X000b CEC2IC XXXX X000b IFSR3A 00h The CEC function shares the interrupt vectors and the interrupt control registers with other peripheral functions. To use CEC1 interrupt, set the IFSR33 bit in the IFSR3A register to 1 (CEC1). To use CEC2 interrupt, set the IFSR34 bit in the IFSR3A register to 1 (CEC2). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 649 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 26. Consumer Electronics Control (CEC) Function 26.5 26.5.1 Notes on CEC (Consumer Electronics Control) Registers and Bit Operation The registers and the bits of the CEC function are synchronized with the count source. Therefore, the internal circuit starts to operate from the next count source timing, while the contents of the register is changed immediately after rewriting the value of the register. When changing the value of the same bit successively or reading the bit changed under the influence of another bit, wait for one or more cycles of the count source. Example: when changing the value of the same bit successively (1) Change the bit to 0. (2) Wait for one or more cycles of the count source. (3) Change the same bit to 1. Example: when reading the bit changed under the influence of another bit (after the reception is disabled, to ensure that the CRERRFLG bit in the CECFLG register becomes 0 (no reception error detected) ). (1) Set the CRXDEN bit in the CECC3 register to 0 (reception disabled) (2) Wait for one or more cycles of the count source (3) Read the CRERRFLG bit in the CECFLG register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 650 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27. A/D Converter 27.1 Introduction A/D converter consists of one 10-bit successive approximation A/D converter. Table 27.1 shows A/D Converter Specifications, Figure 27.1 shows an A/D Converter Block Diagram. Table 27.1 A/D Converter Specifications Item A/D conversion method Analog input voltage Operating clock φAD Specification Successive approximation 0 V to AVCC (VCC1) f1, f1 divided by 2, f1 divided by 3, f1 divided by 4, f1 divided by 6, f1 divided by 12, fOCO40M divided by 2, fOCO40M divided by 3, fOCO40M divided by 4, fOCO40M divided by 6, or fOCO40M divided by 12 10 bits AVCC = VREF = 5 V AN0 to AN7, AN0_0 to AN0_7, or AN2_0 to AN2_7 input: ±3 LSB ANEX0 or ANEX1 input: ±3 LSB AVCC = VREF = 3.0 V AN0 to AN7, AN0_0 to AN0_7, or AN2_0 to AN2_7 input: ±3 LSB ANEX0 or ANEX1 input: ±3 LSB One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, repeat sweep mode 1 8 pins (AN0 to AN7) + 2 pins (ANEX0 and ANEX1) + 8 pins (AN0_0 to AN0_7) + 8 pins (AN2_0 to AN2_7) • Software trigger The ADST bit in the ADCON0 register is set to 1 (A/D conversion start). • External trigger (retrigger is enabled) Input to the ADTRG pin changes from high to low after the ADST bit is set to 1(A/ D conversion start). Minimum 43 φAD cycles Resolution Integral nonlinearity error Operation modes Analog input pins A/D conversion start conditions Conversion rate per pin REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 651 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter VREF AVSS 0 1 ADSTBY Analog circuit Successive conversion register ADCON1 register ADCON0 register AD0 register (16 bits) AD1 register (16 bits) AD2 register (16 bits) AD3 register (16 bits) AD4 register (16 bits) AD5 register (16 bits) AD6 register (16 bits) AD7 register (16 bits) Data bus (high-order) Decoder for register ADCON2 register Data bus (low-order) PM00 PM01 Vref Decoder for channel selection Port P10 group AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADGSEL1.0 ANEX1.0 = 00b = 00b = 00b = 00b = 00b = 00b = 00b = 00b = 00b = 00b = 00b = 00b = 00b = 00b = 00b = 00b CH2 to CH0 = 000b = 001b = 010b = 011b = 100b = 101b = 110b = 111b VIN Comparator Port P0 group PM01 to PM00 = 00b ADGSEL1.0 ANEX1.0 = 00b = 10b = 10b = 00b = 10b = 00b = 10b = 00b = 10b = 00b = 10b = 00b = 10b = 00b = 10b = 00b CH2 to CH0 = 000b = 001b = 010b = 011b = 100b = 101b = 110b = 111b AN0_0 AN0_1 AN0_2 AN0_3 AN0_4 AN0_5 AN0_6 AN0_7 Port P2 group PM01 to PM00 = 00b ADGSEL1.0 = 11b AN2_0 = 11b AN2_1 = 11b AN2_2 = 11b AN2_3 = 11b AN2_4 = 11b AN2_5 = 11b AN2_6 = 11b AN2_7 ANEX1.0 = 00b = 00b = 00b = 00b = 00b = 00b = 00b = 00b CH2 to CH0 = 000b = 001b = 010b = 011b = 100b = 101b = 110b = 111b ADEX1 to ADEX0 = 01b ADEX1 to ADEX0 = 10b ANEX0 ANEX1 Figure 27.1 A/D Converter Block Diagram REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 652 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter Table 27.2 I/O Pins Pin Name Input/Output Function AN0 to AN7 Input Analog input ANEX0, ANEX1 Input Analog input AN0_0 to AN0_7 Input Analog input AN2_0 to AN2_7 Input Analog input Input Trigger input ADTRG Note: 1. Set the direction bit of the ports sharing a port to 0 (input mode). 27.2 Registers Table 27.3 lists registers associated with A/D converter. Set the CKS3 bit in the ADCON2 register before setting other registers associated with A/D converter excluding the PCR register. However, bits in the ADCON2 register and the CKS3 bit can be set simultaneously. After changing the CKS3 bit, set the registers in the same way again. The PCR register can be set before setting the CKS3 bit. After changing the CKS3 bit, the PCR register does not need to be set again. Table 27.3 Register Structure Address 0366h 03A2h 03C0h 03C1h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C8h 03C9h 03CAh 03CBh 03CCh 03CDh 03CEh 03CFh 03D4h 03D6h 03D7h Register Name Port Control Register Open-Circuit Detection Assist Function Register A/D Register 0 A/D Register 1 A/D Register 2 A/D Register 3 A/D Register 4 A/D Register 5 A/D Register 6 A/D Register 7 A/D Control Register 2 A/D Control Register 0 A/D Control Register 1 Register Symbol PCR AINRST AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ADCON2 ADCON0 ADCON1 After Reset 0000 0XX0b XX00 0000b XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb XXXX XXXXb 0000 00XXb 0000 X00Xb 0000 0XXXb 0000 X000b REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 653 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.2.1 Port Control Register (PCR) Port Control Register b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol PCR Bit Symbol Bit Name Address 0366h Function After Reset 0000 0XX0b RW PCR0 Port P1 control bit Operation performed when the P1 register is read 0 : When the port is set to input, the input levels of pins P1_0 to P1_7 are read. When set to output, the port latch is read. 1 : The port latch is read regardless of whether the port is set to input or output. RW — (b2-b1) — (b3) PCR4 PCR5 PCR6 PCR7 No register bits. If necessary, set to 0. Read as undefined Reserved bit CEC output enable bit INT6 input enable bit INT7 input enable bit Key input enable bit Set to 0 0 : CEC output disabled 1 : CEC output enabled 0 : Enabled 1 : Disabled 0 : Enabled 1 : Disabled 0 : Enabled 1 : Disabled — RW RW RW RW RW PCR5 (INT6 Input Enable Bit) (b5) Set the PCR5 bit to 1 (INT6 input disabled) when using the AN2_4 pin is used for analog input. PCR6 (INT7 Input Enable Bit) (b6) Set the PCR6 bit to 1 (INT7 input disabled) when using AN2_5 pin is used for analog input. PCR7 (key Input Enable Bit) (b7) Set the PCR7 bit to 1 (key input disabled) when using pins AN4 to AN7 are used for analog input. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 654 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.2.2 Open-Circuit Detection Assist Function Register (AINRST) Open-Circuit Detection Assist Function Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol AINRST Bit Symbol — (b3-b0) AINRST0 Bit Name Address 03A2h Function After Reset XX00 0000b RW — No register bits. If necessary, set to 0. Read as undefined value b5 b4 0 Open-circuit detection assist 0 function enable bit 1 AINRST1 1 — (b7-b6) 0 : Open-circuit detection disabled 1 : Precharge before conversion 0 : Discharge before conversion 1 : Do not set RW RW No register bits. If necessary, set to 0. Read as undefined value — AINRST1-AINRST0 (Open-circuit Detection Assist Function Enable Bit) (b5-b4) To enable the A/D open-circuit detection assist function, set the AINRST0 bit or AINRST1 bit to 1, and then set the ADST bit in the ADCON0 register to 1 (A/D conversion) after waiting for one cycle of φAD. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 655 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.2.3 AD Register i (ADi) (i = 0 to 7) A/D Register (i = 0 to 7) (b15) b7 (b8) b0 b7 b0 Symbol AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Address 03C1h to 03C0h 03C3h to 03C2h 03C5h to 03C4h 03C7h to 03C6h 03C9h to 03C8h 03CBh to 03CAh 03CDh to 03CCh 03CFh to 03CEh Function After Reset 0000 00XX XXXX XXXXb 0000 00XX XXXX XXXXb 0000 00XX XXXX XXXXb 0000 00XX XXXX XXXXb 0000 00XX XXXX XXXXb 0000 00XX XXXX XXXXb 0000 00XX XXXX XXXXb 0000 00XX XXXX XXXXb RW RO RO — RO Eight low-order bits of A/D conversion result Two high-order bits of A/D conversion result No register bits. If necessary, set to 0. Read as 0 Reserved bit Read as 0 The A/D conversion result is stored in the ADi register corresponding to pins ANi, ANEXi, AN0_i, and AN2_i. Table 27.4 lists Analog Pin and A/D Conversion Result Storing Register. Table 27.4 Analog Pin and A/D Conversion Result Storing Register AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ANEX0 ANEX1 Analog Pin AN0_0 AN0_1 AN0_2 AN0_3 AN0_4 AN0_5 AN0_6 AN0_7 AN2_0 AN2_1 AN2_2 AN2_3 AN2_4 AN2_5 AN2_6 AN2_7 A/D Conversion Result Storing Register AN0 register AN1 register AN2 register AN3 register AN4 register AN5 register AN6 register AN7 register REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 656 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.2.4 A/D Control Register 2 (ADCON2) A/D Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol ADCON2 Bit Symbol — (b0) ADGSEL0 Bit Name Address 03D4h Function After Reset 0000 X00Xb RW — No register bit. If necessary, set to 0. Read as undefined value b2 b1 0 0 : AN0 to AN7 0 1 : Do not set 1 0 : AN0_0 to AN0_7 1 1 : AN2_0 to AN2_7 RW A/D input group select bit ADGSEL1 — (b3) CKS2 — (b6-b5) CKS3 RW No register bit. If necessary, set to 0. Read as undefined value Refer to the CKS0 bit in the ADCON0 register. Set to 0 0: f1 1: fOCO40M — Frequency select bit 2 RW Reserved bits RW fAD select bit RW If the ADCON2 register is rewritten during A/D conversion, the conversion result is undefined. ADGSEL1-ADGSEL0 (A/D Input Group Select Bit) (b2-b1) AN0_0 to AN0_7 are used as analog input pins even if bits PM01 to PM00 are set to 01b (memory expansion mode) and bits PM05 to PM04 are 11b (multiplexed bus is allocated to the entire CS space). CKS3 (fAD Select Bit) (b7) Set the CKS3 bit while A/D conversion stops. Set the CKS3 bit, and then set other A/D converter related registers. Also, after changing the CKS3 bit, set the A/D converter related registers again. Note that bits in the ADCON2 register and the CKS3 bit can be set simultaneously. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 657 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.2.5 A/D Control Register 0 (ADCON0) A/D Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON0 Bit Symbol CH0 CH1 CH2 Bit Name Address 03D6h Function After Reset 0000 0XXXb RW RW Analog input pin select bit Function varies with operation mode RW RW b4 b3 MD0 A/D operation mode select bit 0 MD1 0 0 1 1 0 : One-shot mode 1 : Repeat mode 0 : Single sweep mode 1 : Repeat sweep mode 0 or repeat sweep mode 1 RW RW TRG Trigger select bit 0 : Software trigger 1 : ADTRG trigger 0 : A/D conversion stop 1 : A/D conversion start Refer to the next page. RW ADST CKS0 A/D conversion start flag Frequency select bit 0 RW RW If the ADCON0 register is rewritten during A/D conversion, the conversion result is undefined. MD1-MD0 (A/D Operation Mode Select Bit) (b4-b3) A/D operation mode is selected by a combination of bits MD1 to MD0 and the MD2 bit in the ADCON1 register. Table 27.5 lists A/D Operation Mode. Table 27.5 A/D Operation Mode Bit Setting ADCON1 Register ADCON0 Register MD2 MD1 MD0 0 0 0 0 0 1 0 1 0 0 1 1 1 1 1 Do not set bit combinations not listed above. A/D Operation Mode One-shot mode Repeat mode Single sweep mode Repeat sweep mode 0 Repeat sweep mode 1 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 658 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter CKS0 (Frequency Select Bit) (b7) φAD frequency is selected by a combination of the CKS0 bit in the ADCON0 register, the CKS1 bit in the ADCON1 register, and bits CKS3 and CKS2 in the ADCON2 register. Select bits CKS2 to CKS0 after setting the CKS3 bit in the ADCON2 register. Note that bits CKS3 and CKS2 can be set simultaneously. Table 27.6 lists φ A/D Frequency. Table 27.6 φ A/D Frequency CKS2 0 0 0 0 1 1 1 1 0 0 1 1 1 1 CKS1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 CKS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CKS3 0 φA/D fAD(f1) divided by 4 fAD(f1) divided by 2 fAD(f1) fAD(f1) divided by 12 fAD(f1) divided by 6 fAD(f1) divided by 3 fAD(fOCO40M) divided by 4 fAD(fOCO40M) divided by 2 fAD(fOCO40M) divided by 12 fAD(fOCO40M) divided by 6 fAD(fOCO40M) divided by 3 1 Note: 1. Do not set bit combinations not listed above. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 659 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.2.6 A/D Control Register 1 (ADCON1) A/D Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON1 Bit Symbol SCAN0 A/D sweep pin select bit SCAN1 MD2 — (b3) CKS1 Bit Name Address 03D7h Function After Reset 0000 X000b RW RW Function varies with operation mode RW A/D operation mode select 0 : Any mode other than repeat sweep mode 1 bit 1 1 : Repeat sweep mode 1 No register bit. If necessary, set to 0. Read as undefined value Frequency select bit 1 Refer to the CKS0 bit in the ADCON0 register 0 : A/D operation stopped (standby) 1 : A/D operation enabled RW — RW RW RW ADSTBY A/D standby bit ADEX0 Extended pin select bit ADEX1 Function varies with operation mode RW If the ADCON1 register is rewritten during A/D conversion, the conversion result is undefined. MD2 (A/D Operation Mode Select Bit 1) (b2) A/D operation mode is selected by a combination of bits MD1 to MD0 in the ADCON0 register and the MD2 bit. Refer to Table 27.5 “A/D Operation Mode”. ADSTBY (A/D Standby Bit) (b5) If the ADSTBY bit is changed from 0 (A/D operation stopped) to 1 (A/D operation enabled), wait for 1 φA/D cycle or more before starting A/D conversion. When the A/D converter is not used, no current flows in the A/D converter by setting the ADSTBY bit to 0 (A/D operation stopped: standby). This helps the power consumption to be reduced. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 660 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.3 27.3.1 Operations A/D Conversion Cycle A/D conversion cycle is based on fAD and φAD. Figure 27.2 shows fAD and φAD. When the CKS3 bit in the ADCON2 register is 1 (fOCO40M is fAD), do not set the CKS2 bit in the ADCON2 register to 0 and the CKS1 bit in the ADCON1 register to 1 (fDA = φAD). Set the A/D converter related registers after setting the CKS3 bit. Select A/D conversion speed 0 CKS2 0 1 CKS3 1 0 CKS1 f1 fOCO40M fAD fAD 1/2 1/3 1 1/2 1 0 CKS0 φAD CKS0: Bit in the ADCON0 register CKS1: Bit in the ADCON1 register CKS2, CKS3: Bits in the ADCON2 register Figure 27.2 fAD and φAD Figure 27.3 shows A/D Conversion Timing. Start processing Open-circuit detection First bit conversion time Compare time Second bit Third bit Compare Compare time time 2.5 φAD End Tenth bit processing Compare End time processing 2 to 3 fAD Open-circuit Start detection charge processing time Processing cycle 1 to 2 fAD 2 φAD Sampling time 15 φAD 40 φAD 42 φAD The above figure applies under the following conditions: One-shot mode φAD = fAD Figure 27.3 A/D Conversion Timing REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 661 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter Table 27.7 lists Cycles of A/D Conversion Item. A/D conversion period is as follows. Start processing time depends on which φAD is selected. A/D conversion starts after the start processing time elapses by setting the ADST bit in the ADCON0 register to 1 (A/D conversion start). When reading the ADST bit before starting A/D conversion, 0 (A/D conversion stop) is read. When selecting multiple pins and in A/D conversion repeat mode, between-execution processing time is inserted between A/D conversions. In one-shot mode and single sweep mode, the ADST bit becomes 0 at the end processing time and the last A/D conversion result is stored in the ADi register. One-shot mode: Start processing time + A/D conversion execution time + end processing time Two pins are selected in single sweep mode: Start processing time + (A/D conversion execution time + between-execution processing time + A/D conversion execution time) + end processing time Table 27.7 Cycles of A/D Conversion Item A/D Conversion Item Start processing time φAD = fAD φAD = fAD divided by 2 φAD = fAD divided by 3 φAD = fAD divided by 4 φAD = fAD divided by 6 φAD = fAD divided by 12 A/D conversion Open-circuit detection disabled execution time Open-circuit detection enabled Between-execution processing time End processing time Cycle 1 to 2 cycles of fAD 2 to 3 cycles of fAD 3 to 4 cycles of fAD 3 to 4 cycles of fAD 4 to 5 cycles of fAD 7 to 8 cycles of fAD 40 cycles of φAD 42 cycles of φAD 1 cycle of φAD 2 to 3 cycles of fAD REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 662 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.3.2 A/D Conversion Start Conditions An A/D conversion start trigger has a software trigger and an external trigger. Figure 27.4 shows A/D Conversion Start Trigger. TRG ADST 0 A/D conversion start trigger 1 ADTRG pin ADST, TRG: Bits in the ADCON0 register Figure 27.4 A/D Conversion Start Trigger 27.3.2.1 Software Trigger When the TRG bit in the ADCON0 register is 0 (software trigger), A/D conversion starts by setting the ADST bit in the ADCON0 register to 1 (A/D conversion start). 27.3.2.2 External Trigger When the TRG bit in the ADCON0 register is 1 (ADTRG trigger), A/D conversion starts if the input level at the ADTRG pin changes from high to low under the following conditions: • The direction bit of the port sharing a pin is set to 0 (input mode) • The TRG bit in the ADCON0 register is set to 1 (ADTRG trigger) • The ADST bit in the ADCON0 register is set to 1 (A/D conversion start) Under the above conditions, when input to the ADTRG pin is changed from high to low, the A/D conversion starts. Set the high- and low-level durations of the pulse input to the ADTRG pin to two or more cycles of fAD. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 663 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.3.3 A/D Conversion Result When reading the ADi register before A/D conversion is completed, the undefined value is read. Read the ADi register after completing A/D conversion. Use the following procedure to detect the completion of A/D conversion. • In one-shot mode and single sweep mode: The IR bit in the ADIC register becomes 1 (interrupt requested) at the completion of A/D conversion. Ensure that the IR bit becomes 1 to read the ADi register. when not using A/D interrupt, set the IR bit to 0 (interrupt not requested) by a program after reading the ADi register. • In repeat mode, repeat sweep mode 0, and repeat sweep mode 1: The IR bit remain unchanged (no interrupt request is generated). At first, read the ADi register after one A/D conversion period elapses (refer to 27.3.1 “A/D Conversion Cycle”). After that, whenever the ADi register is read, the conversion result which has been obtained before reading is read. The ADi register is overwritten in every A/D conversion. Read the value before the ADi register is overwritten. 27.3.4 Extended Analog Input Pins In one-shot mode and repeat modes, pins ANEX0 and ANEX1 can be used as analog input pins by setting bits ADEX1 to ADEX0 in the ADCON1 register. The A/D conversion result of pins ANEX0 and ANEX1 are respectively stored in registers AD0 and AD1. 27.3.5 Current Consumption Reduce Function When the A/D converter is not in use, the power consumption can be reduced by setting the ADSTBY bit in the ADCON1 register to 0 (A/D operation stopped: standby) to shut off any analog circuit current flow. To use the A/D converter, set the ADSTBY bit to 1 (A/D operation enabled) and wait for 1 φAD cycle or more before setting the ADST bit in the ADCON0 register to 1 (A/D conversion start). Do not set bits ADST and ADSTBY to 1 at the same time. Also, do not set the ADSTBY bit to 0 (A/D operation stopped: standby) during A/D conversion. 27.3.6 Open-Circuit Detection Assist Function The A/D converter has a function to set charge of the sampling capacitor to a predefined state (AVCC or AVSS) before A/D conversion starts in order to prevent the effect of analog input voltage of previous conversion. This function enables to detect open-circuit of a trace connected to the analog input pin certainly. Figure 27.5 shows A/D Open-Circuit Detection Example on AVCC (Precharge) and Figure 27.6 shows A/D Open-Circuit Detection Example on AVSS (Predischarge). The conversion result in open-circuit depends on the external circuit. Use this function only after careful evaluation for the system. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 664 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter On Precharge External circuit example AINRST0 = 1 R Off Precharge control signal Discharge control signal Analog input ANi Sampling capacitor C Open-circuit ANi: ANi (i = 0 to 7), ANEXi, AN0-i, AN2-i AINRST0: Bit in the AINRST register Figure 27.5 A/D Open-Circuit Detection Example on AVCC (Precharge) Off Precharge control signal AINRST1 = 1 External circuit example Analog input ANi Discharge On Discharge control signal Open-circuit Sampling capacitor R C ANi: ANi (i = 0 to 7), ANEXi, AN0-i, AN2-i AINRST1: Bit in the AINRST register Figure 27.6 A/D Open-Circuit Detection Example on AVSS (Predischarge) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 665 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.4 27.4.1 Operational Modes One-Shot Mode In one-shot mode, the analog voltage applied to a selected pin is converted to a digital code once. Table 27.8 shows One-Shot Mode Specifications. Table 27.8 One-Shot Mode Specifications Item Function A/D conversion start conditions A/D conversion stop conditions Interrupt request generation timing Analog input pin Reading of A/D conversion result Specification Bits CH2 to CH0 in the ADCON0 register and bits ADGSEL1 to ADGSEL0 in the ADCON2 register, or bits ADEX1 to ADEX0 in the ADCON1 register are used to select a pin. The analog voltage applied to the pin is converted to a digital code once. • When the TRG bit in the ADCON0 register is 0 (software trigger) the ADST bit in the ADCON0 register is set to 1 (A/D conversion starts). • When the TRG bit is 1 (ADTRG trigger) input level at the ADTRG pin changes from high to low after the ADST bit is set to 1 (A/D conversion start). • Completion of A/D conversion (if a software trigger is selected, the ADST bit becomes 0 (A/D conversion stop)). • Set the ADST bit to 0. Completion of A/D conversion. Select one pin from among AN0 to AN7, AN0_0 to AN0_7, AN2_0 to AN2_7, ANEX0, and ANEX1. Read the register among AD0 to AD7 that corresponds to the selected pin. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 666 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.4.1.1 A/D Control Register 0 (ADCON0) (In One-Shot Mode) A/D Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol ADCON0 Bit Symbol CH0 CH1 CH2 MD0 MD1 TRG Bit Name Address 03D6h Function b2 b1 b0 After Reset 0000 0XXXb RW RW RW RW RW RW Analog input pin select bit 0 0 0 0 1 1 1 1 b4 0 0 1 1 0 0 1 1 b3 0 : AN0 1 : AN1 0 : AN2 1 : AN3 0 : AN4 1 : AN5 0 : AN6 1 : AN7 A/D operation mode select bit 0 0 0 : One-shot mode Trigger select bit 0 : Software trigger 1 : ADTRG trigger 0 : A/D conversion stop 1 : A/D conversion start Refer to the CKS0 bit in the ADCON0 register RW ADST CKS0 A/D conversion start flag Frequency select bit 0 RW RW If the ADCON0 register is rewritten during A/D conversion, the conversion result is undefined. CH2-CH0 (analog input pin select bit) (b2-b0) AN0_0 to AN0_7 and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7. Use bits ADGSEL1 to ADGSEL0 in the ADCON2 register to select the desired group. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 667 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.4.1.2 A/D Control Register 1 (ADCON1) (In One-Shot Mode) A/D Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit Symbol SCAN0 A/D sweep pin select bit SCAN1 MD2 — (b3) CKS1 Bit Name Address 03D7h Function After Reset 0000 X000b RW RW Invalid in one-shot mode RW A/D operation mode select Set to 0 in one-shot mode. bit 1 No register bit. If necessary, set to 0. Read as undefined value Frequency select bit 1 Refer to the CKS0 bit in the ADCON2 register Set to 1 (A/D operation enabled) b7 b6 RW — RW RW RW RW ADSTBY A/D standby bit ADEX0 Extended pin select bit ADEX1 0 0 1 1 0: ANEX0 and ANEX1 are not used 1: ANEX0 input is A/D converted 0: ANEX1 input is A/D converted 1: Do not set If the ADCON1 register is rewritten during A/D conversion, the conversion result is undefined. A/D conversion start AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 IR bit in the ADIC register Set to 0 by acceptance of an interrupt request or by a program A/D conversion The above diagram applies under the following conditions: Bits CH2 to CH0 in the ADCON0 register are set to 010b (AN2). Bits ADGSEL1 to ADGSEL0 in the ADCON2 register are set to 00b (AN0 to AN7). Figure 27.7 Operation Example in One-Shot Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 668 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.4.2 Repeat Mode In repeat mode, the analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 27.9 lists Repeat Mode Specifications. Table 27.9 Repeat Mode Specifications Item Function A/D conversion start conditions A/D conversion stop condition Interrupt request generation timing Analog input pin Reading of A/D conversion result Specification Bits CH2 to CH0 in the ADCON0 register and bits ADGSEL1 to ADGSEL0 in the ADCON2 register, or bits ADEX1 to ADEX0 in the ADCON1 register are used to select a pin. The analog voltage applied to the pin is repeatedly converted to a digital code. • When the TRG bit in the ADCON0 register is 0 (software trigger) the ADST bit in the ADCON0 register is set to 1 (A/D conversion start). • When the TRG bit is 1 (ADTRG trigger) input level at the ADTRG pin changes from high to low after the ADST bit is set to 1 (A/D conversion start). Set the ADST bit to 0 (A/D conversion stop). No interrupt requests generated Select one pin from among AN0 to AN7, AN0_0 to AN0_7, AN2_0 to AN2_7, ANEX0, and ANEX1. Read the register among AD0 to AD7 that corresponds to the selected pin. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 669 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.4.2.1 A/D Control Register 0 (ADCON0) (In Repeat Mode) A/D Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 01 Symbol ADCON0 Bit Symbol CH0 Bit Name Address 03D6h Function b2 b1 b0 0 0 0: AN0 0 0 1: AN1 0 1 0: AN2 0 1 1: AN3 1 0 0: AN4 1 0 1: AN5 1 1 0: AN6 1 1 1: AN7 b4 b3 0 1: Repeat mode After Reset 0000 0XXXb RW RW CH1 Analog input pin select bit RW CH2 MD0 MD1 TRG RW RW RW A/D operation mode select bit 0 Trigger select bit 0: Software trigger 1: ADTRG trigger 0: A/D conversion stop 1: A/D conversion start Refer to the CKS0 bit in the ADCON2 register RW ADST CKS0 A/D conversion start flag Frequency select bit 0 RW RW If the ADCON0 register is rewritten during A/D conversion, the conversion result is undefined. CH2-CH0 (analog input pin select bit) (b2-b0) AN0_0 to AN0_7 and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7. Use bits ADGSEL1 to ADGSEL0 in the ADCON2 register to select the desired group. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 670 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.4.2.2 A/D Control Register 1 (ADCON1) (In Repeat Mode) A/D Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit Symbol SCAN0 A/D sweep pin select bit SCAN1 MD2 — (b3) CKS1 Bit Name Address 03D7h Function After Reset 0000 X000b RW RW Invalid in repeat mode RW A/D operation mode select Set to 0 in repeat mode. bit 1 No register bit. If necessary, set to 0. Read as undefined value Frequency select bit 1 Refer to the CKS0 bit in the ADCON0 register Set to 1 (A/D operation enabled) b7 b6 0 0: ANEX0 and ANEX1 are not used 0 1: ANEX0 input is A/D converted 1 0: ANEX1 input is A/D converted 1 1: Do not set RW — RW RW RW RW ADSTBY A/D standby bit ADEX0 Extended pin select bit ADEX1 If the ADCON1 register is rewritten during A/D conversion, the conversion result is undefined. A/D conversion start AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 The above diagram applies under the following conditions. Bits CH2 to CH0 in the ADCON0 register are set to 010b (AN2). Bits ADGSEL1 to ADGSEL0 in the ADCON2 register are set to 00b (AN0 to AN7). Figure 27.8 Operation Example in Repeat Mode A/D conversion REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 671 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.4.3 Single Sweep Mode In single sweep mode, the analog voltage applied to selected pins is converted one-by-one to a digital code. Table 27.10 shows the Single Sweep Mode Specifications. Table 27.10 Single Sweep Mode Specifications Item Function A/D conversion start conditions A/D conversion stop conditions Interrupt request generation timing Analog input pin Specification Bits SCAN1 to SCAN0 in the ADCON1 register and bits ADGSEL1 to ADGSEL0 in the ADCON2 register are used to select pins. The analog voltage applied to the pins is converted one-by-one to a digital code. • When the TRG bit in the ADCON0 register is 0 (software trigger) the ADST bit in the ADCON0 register is set to 1 (A/D conversion start). • When the TRG bit is 1 (ADTRG trigger) input level at the ADTRG pin changes from high to low after the ADST bit is set to 1 (A/D conversion start). • Completion of A/D conversion (if a software trigger is selected, the ADST bit is set to 0 (A/D conversion stop)). • Set the ADST bit to 0. Completion of A/D conversion Select from AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), and AN0 to AN7 (8 pins). AN0_0 to AN0_7 and AN2_0 to AN2_7 can be selected in the same way. Read the registers among AD0 to AD7 that corresponds to the selected pin. Reading of A/D conversion result 27.4.3.1 A/D Control Register 0 (ADCON0) (In Single Sweep Mode) A/D Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 10 Symbol ADCON0 Bit Symbol CH0 CH1 CH2 MD0 MD1 TRG Bit Name Address 03D6h Function After Reset 0000 0XXXb RW RW Analog input pin select bit Invalid in single sweep mode RW RW A/D operation mode select bit 0 b4 b3 RW RW RW 1 0 : Single sweep mode Trigger select bit 0 : Software trigger 1 : ADTRG trigger 0 : A/D conversion stop 1 : A/D conversion start Refer to the CKS0 bit in the ADCON0 register ADST CKS0 A/D conversion start flag Frequency select bit 0 RW RW If the ADCON0 register is rewritten during A/D conversion, the conversion result is undefined. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 672 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.4.3.2 A/D Control Register 1 (ADCON1) (In Single Sweep Mode) A/D Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit Symbol SCAN0 A/D sweep pin select bit SCAN1 MD2 — (b3) CKS1 Bit Name Address 03D7h Function After Reset 0000 X000b RW RW RW RW — RW RW RW RW When single sweep mode is selected b1 b0 0 0 1 1 0: AN0 to AN1 (2 pins) 1: AN0 to AN3 (4 pins) 0: AN0 to AN5 (6 pins) 1: AN0 to AN7 (8 pins) A/D operation mode select Set to 0 in single sweep mode. bit 1 No register bit. If necessary, set to 0. Read as undefined value Frequency select bit 1 Refer to the CKS0 bit in the ADCON0 register Set to 1 (A/D operation enabled) b7 b6 ADSTBY A/D standby bit ADEX0 Extended pin select bit ADEX1 0 0 1 1 0: ANEX0 and ANEX1 are not used 1: Do not set 0: Do not set 1: Do not set If the ADCON1 register is rewritten during A/D conversion, the conversion result is undefined. SCAN1-SCAN0 (A/D sweep pin select bit) (b1-b0) AN0_0 to AN0_7 and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7. Use bits ADGSEL1 to ADGSEL0 in the ADCON2 register to select the desired group. A/D conversion start A/D conversion AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 IR bit in the ADIC register The above diagram applies under the following conditions: Bits SCAN1 to SCAN0 in the ADCON1 register are set to 01b (AN0 to AN3 (4 pins)). Bits ADGSEL1 to ADGSEL0 in the ADCON2 register are set to00b (AN0 to AN7). Set to 0 by acceptance of an interrupt request or by a program Figure 27.9 Operation Example in Single Sweep Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 673 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.4.4 Repeat Sweep Mode 0 In repeat sweep mode 0, the analog voltage applied to selected pins is repeatedly converted to a digital code. Table 27.11 shows the Repeat Sweep Mode 0 Specifications. Table 27.11 Repeat Sweep Mode 0 Specifications Item Function A/D conversion start conditions A/D conversion stop condition Interrupt request generation timing Analog input pin Specification Bits SCAN1 to SCAN0 in the ADCON1 register and bits ADGSEL1 to ADGSEL0 in the ADCON2 register are used to select pins. Analog voltage applied to the pins is repeatedly converted to a digital code. • When the TRG bit in the ADCON0 register is 0 (software trigger) the ADST bit in the ADCON0 register is set to 1 (A/D conversion start). • When the TRG bit is 1 (ADTRG trigger) input level at the ADTRG pin changes from high to low after the ADST bit is set to 1 (A/D conversion start). Set the ADST bit to 0 (A/D conversion stop). No interrupt requests generated Select from AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), and AN0 to AN7 (8 pins). AN0_0 to AN0_7 and AN2_0 to AN2_7 can be selected in the same way. Read the registers among AD0 to AD7 that corresponds to the selected pins. Reading of A/D conversion result 27.4.4.1 A/D Control Register 0 (ADCON0) (In Repeat Sweep Mode 0) A/D Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 11 Symbol ADCON0 Bit Symbol CH0 CH1 CH2 MD0 MD1 TRG Bit Name Address 03D6h Function After Reset 0000 0XXXb RW RW Analog input pin select bit Invalid in repeat sweep mode 0 RW RW A/D operation mode select bit 0 b4 b3 RW RW RW 1 1 : Repeat sweep mode 0 or repeat sweep mode 1 Trigger select bit 0 : Software trigger 1 : ADTRG trigger 0 : A/D conversion stop 1 : A/D conversion start Refer to the CKS0 bit in the ADCON0 register ADST CKS0 A/D conversion start flag Frequency select bit 0 RW RW If the ADCON0 register is rewritten during A/D conversion, the conversion result is undefined. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 674 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.4.4.2 A/D Control Register 1 (ADCON1) (In Repeat Sweep Mode 0) A/D Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit Symbol SCAN0 A/D sweep pin select bit SCAN1 MD2 — (b3) CKS1 Bit Name Address 03D7h Function After Reset 0000 X000b RW RW RW RW — RW RW RW RW When repeat sweep mode 0 is selected b1 b0 0 0 1 1 0: AN0 to AN1 (2 pins) 1: AN0 to AN3 (4 pins) 0: AN0 to AN5 (6 pins) 1: AN0 to AN7 (8 pins) A/D operation mode select bit 1 Set to 0 in repeat sweep mode 0 No register bit. If necessary, set to 0. Read as undefined value Frequency select bit 1 Refer to the CKS0 bit in the ADCON0 register Set to 1 (A/D operation enabled) b7 b6 ADSTBY A/D standby bit ADEX0 Extension pin select bit ADEX1 0 0 1 1 0: ANEX0 and ANEX1 are not used 1: Do not set 0: Do not set 1: Do not set If the ADCON1 register is rewritten during A/D conversion, the conversion result is undefined. SCAN1-SCAN0 (A/D sweep pin select bit) (b1-b0) AN0_0 to AN0_7 and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7. Use bits ADGSEL1 to ADGSEL0 in the ADCON2 register to select the desired group. A/D conversion start AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 The above diagram applies under the following conditions: Bits SCAN1 to SCAN0 in the ADCON1 are set to 01b (AN0 to AN3 (4 pins)). Bits ADGSEL1 to ADGSEL0 in the ADCON2 are set to 00b (AN0 to AN7). A/D conversion Figure 27.10 Operation Example in Repeat Sweep Mode 0 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 675 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.4.5 Repeat Sweep Mode 1 In repeat sweep mode 1, the analog voltage applied to eight selected pins including some prioritized pins is repeatedly converted to a digital code. Table 27.12 lists the Repeat Sweep Mode 1 Specifications. Table 27.12 Repeat Sweep Mode 1 Specifications Item Function A/D conversion start conditions A/D conversion stop condition Interrupt request generation timing Specification The input voltage of all eight pins selected by bits ADGSEL1 to ADGSEL0 in the ADCON2 register is repeatedly converted to a digital code. One to four pins selected by SCAN1 to SCAN0 in the ADCON1 register is/are converted by priority. Example: If AN0 is prioritized, input voltage is converted to a digital code in the following order: AN0→AN1→AN0→AN2→AN0→AN3 ••• • When the TRG bit in the ADCON0 register is 0 (software trigger), the ADST bit in the ADCON0 register is set to 1 (A/D conversion start). • When the TRG bit is 1 (ADTRG trigger), input level at the ADTRG pin changes from high to low after the ADST bit is set to 1 (A/D conversion start). Set the ADST bit to 0 (A/D conversion stop). No interrupt requests generated Analog input pins to be given Select from AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), and priority when A/D converted AN0 to AN3 (4 pins). AN0_0 to AN0_3 and AN2_0 to AN2_3 can be selected in the same way. Reading of A/D conversion Read the registers among AD0 to AD7 that corresponds to the selected result pins. 27.4.5.1 A/D Control Register 0 (ADCON0) (In Repeat Sweep Mode 1) A/D Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 11 Symbol ADCON0 Bit Symbol CH0 CH1 CH2 MD0 MD1 TRG Bit Name Address 03D6h Function After Reset 0000 0XXXb RW RW Analog input pin select bit Invalid in repeat sweep mode 1 RW RW b4 b3 A/D operation mode select bit 0 1 1 : Repeat sweep mode 0 or repeat sweep mode 1 RW RW Trigger select bit 0 : Software trigger 1 : ADTRG trigger 0 : A/D conversion stop 1 : A/D conversion start Refer to the CKS0 bit in the ADCON0 register RW ADST CKS0 A/D conversion start flag Frequency select bit 0 RW RW If the ADCON0 register is rewritten during A/D conversion, the conversion result is undefined. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 676 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.4.5.2 A/D Control Register 1 (ADCON1) (In Repeat Sweep Mode 1) A/D Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit Symbol SCAN0 A/D sweep pin select bit SCAN1 MD2 — (b3) CKS1 Bit Name Address 03D7h Function After Reset 0000 X000b RW RW RW RW — RW RW RW RW When repeat sweep mode 1 is selected b1 b0 0 0 1 1 0: AN0 (1 pin) 1: AN0 to AN1 (2 pins) 0: AN0 to AN2 (3 pins) 1: AN0 to AN3 (4 pins) A/D operation mode select bit 1 1 : Repeat sweep mode 1 No register bit. If necessary, set to 0. Read as undefined value Frequency select bit 1 Refer to the CKS0 bit in the ADCON0 register Set to 1 (A/D operation enabled) b7 b6 ADSTBY A/D standby bit ADEX0 Extended pin select bit ADEX1 0 0 1 1 0: ANEX0 and ANEX1 are not used 1: Do not set 0: Do not set 1: Do not set If the ADCON0 register is rewritten during A/D conversion, the conversion result is undefined. SCAN1-SCAN0 (A/D sweep pin select bit) (b1-b0) AN0_0 to AN0_7 and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7. Use bits ADGSEL1 to ADGSEL0 in the ADCON2 register to select the desired group. A/D conversion A/D conversion start AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 The above diagram applies under the following conditions. Bits SCAN1 to SCAN0 in the ADCON1 register are set to 00b (AN0 (one pin)). Bits ADGSEL1 to ADGSEL0 in the ADCON2 register are set to 00b (A0 to AN7). Figure 27.11 Operation Example in Repeat Sweep Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 677 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter When ANi_0 is prioritized (single pin) ANi_0 ANi_1 ANi_2 ANi_3 ANi_4 ANi_5 ANi_6 ANi_7 Time When ANi_0 and ANi_1 are prioritized (2 pins) ANi_0 ANi_1 ANi_2 ANi_3 ANi_4 ANi_5 ANi_6 ANi_7 When ANi_0 to ANi_2 are prioritized (3 pins) ANi_0 ANi_1 ANi_2 ANi_3 ANi_4 ANi_5 ANi_6 ANi_7 When ANi_0 to ANi_3 are prioritized (4 pins) ANi_0 ANi_1 ANi_2 ANi_3 ANi_4 ANi_5 ANi_6 ANi_7 : A/D conversion i = none, 0, 2, 15 Figure 27.12 Transition Diagram of Pins Used in A/D Conversion in Repeat Sweep Mode 1 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 678 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.5 External Sensor Figure 27.13 shows Analog Input Pin and External Sensor Equivalent Circuit. R1 in Figure 27.13 is obtained by the following formulas. C 2 ( E x – V samp ) – t samp I 2 = ------------------------------------------------------------ exp -----------------------------------------------------------C in × R 1 + C 2 ( R 1 + R 2 ) C in × R 1 + C 2 ( R 1 + R 2 ) Time required to charge C2: – t samp > C in × R 1 + C 2 ( R 1 + R 2 ) Sampling time t samp – C 2 × R 2 R1 < ---------------------------------------C in + C 2 15 t samp = ----------φ AD MCU Sensor equivalent circuit R1 Ex I2 Vref Cin R2 (10kΩ) (15pF) C2 (10pF) Vsamp Sampling time 15 φAD Figure 27.13 Analog Input Pin and External Sensor Equivalent Circuit Cin : Input pin capacity : Sampling capacity C2 : Sensor output resistance R1 : Selector resistance R2 : Sensor output voltage Ex Vsamp : Sampled voltage Vref : A/D converter reference voltage REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 679 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter When capacitor C1 is connected, C1 is obtained by the following formulas. Figure 27.14 shows Analog Input Pin and External Sensor Equivalent Circuit (Capacitor is Connected). If R1 is infinite, C2 is charged from C1. When the difference of voltages generated by divided capacitor, C1 and C2 is VP: C2 V P = ------------------- × ( E x – V samp ) … ( 1 ) C1 + C2 When the difference generated by the conversion is Vp1: 1 VREF V P = V P1 × ---i < ---------------- … ( 2 ) x 2 A×2 X = 10 (bits) 1 A: VP1= --- LSB (e.g. when VP1 = 0.1 LSB, A = 10) A From (1) and (2) Ex – V2 C 1 = C 2 × ⎛ ------------------ – 1⎞ … ( 3 ) ⎝V ⎠ P1 x1 ∴C 1 > C 2 ⎛ A × 2 ---i – 1⎞ … ( 4 ) ⎝ ⎠ 2 In 10-bit resolution A/D converter, C1 is 0.21 μF or more when C2 = 10 pF. MCU Sensor equivalent circuit R1 Ex l1 Ii l2 Vref Sampling time R2 (10kΩ) Cin (15pF) C2 (10pF) Vsamp 15 φAD C1 Figure 27.14 Analog Input Pin and External Sensor Equivalent Circuit (Capacitor is Connected) C1 : Board parasitic capacitance Cin : Input pin capacity : Sampling capacity C2 : Sensor output resistance R1 : Selector resistance R2 : Sensor output voltage Ex Vsamp : Sampled voltage Vref : A/D converter reference voltage REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 680 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.6 Interrupt Refer to the operation examples for timing of generating interrupt requests. Also, refer to 14.7 “Interrupt Control” for details. Table 27.13 lists Registers Associated with A/D Converter Interrupt. Table 27.13 Registers Associated with A/D Converter Interrupt Address 004Eh Register Name A/D Conversion Interrupt Control Register Register Symbol After Reset ADIC XXXX X000b REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 681 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.7 27.7.1 Notes on A/D Converter Analog Input Pin When VCC1 ≥ VCC2, set analog input voltage as follows: analog input voltage (AN_0 to AN_7, ANEX0, and ANEX1) ≤ VCC1 analog input voltage (AN0_0 to AN0_7 and AN2_7 to AN2_7) ≤ VCC2 Do not use any of four pins AN4 to AN7 as analog input pins if a key input interrupt is to be used (key input interrupt request is generated when analog input voltage becomes low level). 27.7.2 φAD Frequency Set φAD to 2 MHz or more, but an upper limit is set as follows: 4.0 ≤ VCC1 ≤ 5.5V: φAD ≤ 25 MHz 3.2 ≤ VCC1 ≤ 4.0V: φAD ≤ 16 MHz 3.0 ≤ VCC1 ≤ 3.2V: φAD ≤ 10 MHz 27.7.3 Pin Configuration Three capacitors should be respectively put between pins AVCC, VREF, analog input (ANi (i = 0 to 7), ANEXi, AN0_i, and AN2_i) and the AVSS pin to protect from error operations caused by noise, latchup, or to reduce conversion errors. Also, a capacitor between the VCC1 pin and the VSS pin. Figure 27.15 shows Example of Pin Configuration. MCU VCC1 VCC1 C4 VSS VCC2 VCC2 C5 VSS ANi: ANi (i = 0 to 7), AN0_i, AN2_i, ANEXi Notes: 1.C1 ≥ 0 .1 μF, C2 ≥ 0 .1 μF, C3 ≥ 100pF, C4 ≥ 0 .1 μF, C5 ≥ 0.1 μF (reference values). 2.The traces for the capacitor and MCU should be short and wide as much as physically possible. ANi VREF C1 AVSS C3 C2 AVCC VCC1 Figure 27.15 Example of Pin Configuration 27.7.4 Register Access Set registers ADCON0 (exclude bit 6), ADCON1, and ADCON2 when A/D conversion stops (before trigger is generated). Set the ADSTBY bit which is 1 to 0 after A/D conversion stops. 27.7.5 A/D Conversion Start If the ADSTBY bit in the ADCON1 is changed from 0 (A/D operation stopped) to 1 (A/D operation enabled), wait for 1 φA/D cycle or more before starting A/D conversion. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 682 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 27. A/D Converter 27.7.6 A/D Operation Mode Change When A/D operation mode has been changed, re-select analog input pins by using bits CH2 to CH0 in the ADCON0 register or bits SCAN1 to SCAN0 in the ADCON1 register. 27.7.7 State When Forcibly Terminated If A/D conversion in progress is halted by setting the ADST bit in the ADCON0 register to 0, the conversion result is undefined. In addition to that, the unconverted ADi register may also become undefined. Do not use any ADi registers when setting the ADST bit to 0 by a program during A/D conversion. 27.7.8 A/D Open-Circuit Detection Assist Function The conversion result in open-circuit depends on the external circuit. Use this function only after careful evaluation for the system. Do not use this function when VCC1 > VCC2. When A/D conversion starts after changing the AINRST register, follow these procedures: (1) Change bits AINRST1 to AINRST0 in the AINRST register. (2) Wait for one cycle of φAD. (3) Set the ADST bit in the ADCON0 register to 1 (A/D conversion start). 27.7.9 Detection of Completion of A/D Conversion In one-shot mode and single sweep mode, use the IR bit in the ADIC register to detect completion of A/D conversion. When not using interrupt, set the IR bit to 0 by a program after the detection. When 1 is written to the ADST bit in the ADCON0 register, the ADST bit becomes 1 (A/D conversion start) after start processing time (refer to Table 27.7 “Cycles of A/D Conversion Item”) elapses. When reading the ADST bit shortly after writing 1, 0 (A/D conversion stop) may be read. Write 1 to the ADST bit by a program. ADST bit in the ADCON0 register Start processing time IR bit in the ADIC register A/D conversion Set to 0 by acceptance of an interrupt request or by a program. Figure 27.16 ADST Bit Operation 27.7.10 Register Settings Set the CKS3 bit, and then set other A/D converter related registers. Also, after changing the CKS3 bit, set the A/D converter related registers again. Note that bits in the ADCON2 register and the CKS3 bit can be set simultaneously. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 683 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 28. D/A Converter 28. D/A Converter 28.1 Introduction The D/A converter consists of two independent 8-bit R-2R type D/A converters. Table 28.1 lists D/A Converter Specifications and Figure 28.1 shows D/A Converter Block Diagram. Table 28.1 D/A Converter Specifications Item D/A conversion method Resolution Specification R-2R 8 bits Low-Order Bits of Data Bus DA0 register DA0E bit R-2R resistor ladder DA0 DA1 register DA1E bit R-2R resistor ladder DA1 Figure 28.1 D/A Converter Block Diagram Table 28.2 Input Pin Pin Name DA0 DA1 Note: 1. Output Input/Output (1) Function D/A comparator output Set the direction bit of the ports sharing a pin to 0 (input mode). When the DAiE bit is se to 1, the corresponding port cannot be pulled up. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 684 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 28. D/A Converter 28.2 Registers Register Structure Table 28.3 Address 03D8h 03DAh 03DCh Register Name D/A0 Register D/A1 Register D/A Control Register Register Symbol DA0 DA1 DACON After Reset 00h 00h 00h 28.2.1 D/Ai Register (DAi) (i = 0 to 1) D/Ai Register (i = 0 to 1) b7 b0 Symbol DA0 DA1 Function Output value of D/A conversion Address 03D8h 03DAh After Reset 00h 00h Setting Range 00h to FFh RW RW 28.2.2 D/A Control Register (DACON) D/A Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DACON Bit Symbol DA0E Bit Name D/A 0 output enable bit Address 03DCh Function 0 : Output disabled 1 : Output enabled 0 : Output disabled 1 : Output enabled After Reset 00h RW RW DA1E — (b7-b2) D/A 1 output enable bit RW No register bits. If necessary, set to 0. Read as 0 — REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 685 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 28. D/A Converter 28.3 Operations D/A conversion is performed by writing a value to the DAi register (i = 0 to 1). Output analog voltage (V) is determined by the value n (n = decimal) set in the DAi register. n V = VREF × --------- (n = 0 to 255) 256 VREF: Reference voltage Figure 28.2 shows D/A Converter Equivalent Circuit. r DAi DAiE bit R R R R R R R 2R 2R MSB DAi register AVSS VREF (2) i = 0 to 1 2R 2R 2R 2R 2R 2R 2R LSB 0 1 Notes: 1. The above diagram applies when the DAi register is set to 2Ah. 2. VREF is not related to the ADSTBY bit in the ADCON1 register. Figure 28.2 D/A Converter Equivalent Circuit REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 686 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 28. D/A Converter 28.4 28.4.1 Notes on D/A Converter Not Using D/A Converter When the D/A converter is not used, set the DAiE bit (i = 0 to 1) to 0 (output disabled) and the DAi register to 00h in order to minimize unnecessary current consumption and prevent the flow of a current to R-2R resistor. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 687 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 29. CRC Calculator 29. CRC Calculator 29.1 Introduction The CRC (Cyclic Redundancy Check) calculator detects errors in data blocks. This CRC calculator is enhanced by additional feature, CRC snoop, in order to monitor reads from and writes to a certain SFR address, and perform CRC calculations automatically on the data read from and data written to the aforementioned SFR address. Figure 29.1 shows CRC Calculator Block Diagram. Figure 29.2 shows CRC Operation (CRC-CCITT). Table 29.1 CRC Calculator Specification Item Operation polynomial Selectable function Specification CRC-CCITT + + • MSB/LSB selectable • CRC snoop (X16 X12 X5 + 1) or CRC-16 (X16 + X15 + X2 + 1) High-order bit of data bus Low-order bit of data bus 8 low-order bits CRCD register (16) 8 high-order bits (03BDh, 03BCh) CRC snoop block CRC generator X16+X12+X5+1 or X16+X15+X2+1 SFR to snoop CRCIN register (8) (03BEh) =? Snoop enabled Address bus Figure 29.1 CRC Calculator Block Diagram REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 688 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 29. CRC Calculator 29.2 Registers Register Structure Table 29.2 Address 03B4h 03B5h 03B6h 03BCh 03BDh 03BEh Register Name SFR Snoop Address Register CRC Mode Register CRC Data Register CRC Input Register Symbol CRCSAR CRCMR CRCD CRCIN After Reset XXXX XXXXb 00XX XXXXb 0XXX XXX0b XXh XXh XXh 29.2.1 CRC Data Register (CRCD) CRC Data Register (b15) b7 (b8) b0 b7 b0 Symbol CRCD Address 03BDh to 03BCh After Reset Undefined Function When data is written to the CRCIN register after setting the initial value in the CRCD register, the CRC can be read out from this register. Setting Range 0000h to FFFFh RW RW 29.2.2 CRC Input Register (CRCIN) CRC Input Register b7 b0 Symbol CRCIN Address 03BEh After Reset Undefined Function Data input Setting Range 00h to FFh RW RW REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 689 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 29. CRC Calculator 29.2.3 CRC Mode Register (CRCMR) CRC Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol CRCMR Bit Symbol CRCPS — (b6-b1) CRCMS Bit Name Address 03B6h Function 0: X16+X12+X5+1 (CRC-CCITT) 1: X16+X15+X2+1 (CRC-16) After Reset 0XXX XXX0b RW RW CRC polynomial select bit No register bits. If necessary, set to 0. Read as undefined value 0: LSB first 1: MSB first — CRC mode select bit RW 29.2.4 SFR Snoop Address Register (CRCSAR) SFR Snoop Address Register b15 b8 b7 b0 Symbol CRCSAR Bit Symbol CRCSAR9 to CRCSAR0 Address 03B5 to 03B4h Bit Name After Reset 00XX XXXX XXXX XXXXb Function RW RW SFR snoop address bit Set the SFR address to snoop — (b13-b10) CRCSR No register bits. If necessary, set to 0. Read as undefined value. Snoop-on-read enable bit Snoop-on-write enable bit 0: Disabled 1: Enabled 0: Disabled 1: Enabled — RW CRCSW RW CRCSR (CRC Snoop On Read Enable Bit) (b14) Do not set bits CRCSR and CRCSW to 1 simultaneously. When the CRCSW bit is set to 1, set the CRCSR bit to 0. CRCSW (Snoop On Write Enable Bit) (b15) Do not set bits CRCSR and CRCSW to 1 simultaneously. When the CRCSR bit is set to 1, set the CRCSW bit to 0. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 690 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 29. CRC Calculator 29.3 29.3.1 Operations Basic Operation The CRC (Cyclic Redundancy Check) calculation detects an error in data blocks. The MCU uses two generator polynomials of CRC-CCITT (X 16 + X12 + X5 + 1 ) and CRC-16 (X 16 + X 15 + X2 + 1 ) to generate CRC. The CRC is 16-bit code generated for a given length of a data block in 8 bits unit. After setting the default value in the CRCD register, the CRC is stored in the CRCD register every time one-byte of data is written to the CRCIN register. CRC generation for one-byte data is completed in two CPU clock cycles. 29.3.2 CRC Snoop CRC snoop monitors reads from and writes to a certain SFR address and performs CRC calculation on the data read from and written to the aforementioned SFR address automatically. Because CRC snoop recognizes writes to and reads from a certain SFR address as a trigger to perform CRC calculation automatically, there is no need to write data to the CRCIN register. All SFR addresses from 0020h to 03FFh are subject to the CRC snoop. The CRC snoop is useful to monitor writes to the UART TX buffer, and reads from the UART RX buffer. To use this function, write a target SFR address to bits CRCSAR9 to CRCSAR0 in the CRCSAR register. Then, set the CRCSW bit in the CRCSAR register to 1 to enable snooping on writes to the target or the CRCSR bit in the CRCSAR register to 1 to enable snooping on reads from the target. When setting the CRCSW bit to 1, and writing data to a target SFR address by CPU or DMA, CRC calculator stores the data into the CRCIN register and performs CRC calculation. Similarly, when setting the CRCSR bit to 1, and reading data in a target SFR address by CPU or DMA, CRC calculator stores the data into the CRCIN register and performs CRC calculation. The CRC calculation is performed on one-byte at a time. When the target SFR address is accessed in word (16 bits), CRC is generated on the lower byte (one byte) of data. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 691 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 29. CRC Calculator CRC calculation and setting procedure to generate CRC, 80C4h, with CRC-CCITT (LSB first selected) • CRC operation specification CRC: remainder of a division, inverted value of the CRCIN register generator polynomial Generator polynomial: X16 + X12 + X5 + 1 (1 0001 0000 0010 0001b) • Setting procedures (1) Reverse the bit position of the value 80C4h by a program in 1-byte units. 80h → 01h, C4h→23h (1) Write 0000h (initial value) to the CRCD register b15 b0 CRCD register 0000h (2) Write 01h (reversed value of 80h) to the CRCIN register b7 b0 CRCIN register 01h After two cycles, "1189h", which is a bitposition-reverse value of "9188h" (CRC for "80h") is stored in the CRCD register. b15 b0 CRCD register 1189h (3) Write 23h (reversed value of C4h) to the CRCIN register b7 b0 CRCIN register 23h b15 b0 CRCD register 0A41h After two cycles, "0A41h", which is a bitposition-reverse value of "8250h" (CRC for "80C4h") is stored in the CRCD register. • Details on CRC calculation As shown in (3) above, bit position of 01h (0000 0001b) written to the CRCIN register is reversed and becomes 80h (1000 0000b). Add 1000 0000 0000 0000 0000 0000b, as 1000 0000b plus 16 digits, to 0000 0000 0000 0000 0000 0000b, as 0000 0000 0000 0000b plus 8 digits as the default value of the CRCD register to perform the modulo-2 division. 1000 1000 0001 0000 1 Generator polynomial 1000 1000 1000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 CRC 0001 0001 1000 1001b (1189h), the remainder 1001 0001 1000 1000b (9188h) with inversed bit position, can be read from the CRCD register. When going on to (4) above, 23h(0010 0011b) written in the CRCIN register is inversed and becomes C4h (1100 0100b). Add 1100 0100 0000 0000 0000 0000b, as 1100 0100b plus 16 digits, to 1001 0001 1000 1000 0000 0000b, as 1001 0001 1000 1000b plus 8 digits as a remainder of (3) left in the CRCD register to perform the modulo-2 division. 0000 1010 0100 0001b (0A41h), the remainder 1000 0010 0101 0000b (8250h) with inversed bit position, can be read from the CRCD register. Data Modulo-2 operation is operation that complies with the law given below. 0+0=0 0+1=1 1+0=1 1+1=0 -1 = 1 Figure 29.2 CRC Operation (CRC-CCITT) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 692 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 29. CRC Calculator CRC calculation and setting procedure to generate CRC, 80C4h with CRC-16 (MSB first selected) • CRC operation specification CRC: remainder of a division, the CRCIN register generator polynomial Generator polynomial: X16 + X15 +X2 + 1(1 1000 0000 0000 0101b) • Setting procedures (1) Write 0000h (initial value) to the CRCD register b15 b0 CRCD register (2) Write 80h to the CRCIN register 0000h b7 b0 CRCIN register 80h After two cycles, "8303h" (CRC for 80h) is stored into the CRCD register. b15 b0 CRCD register 8303h (3) Write C4h to the CRCIN register b7 b0 CRCIN register C4h After two cycles, "0292h" (CRC for 80C4h) is stored into the CRCD register. b15 b0 CRCD register 0292h • Details on CRC calculation As shown in (2) above, add 1000 0000 0000 0000 0000 0000b, as 80h (1000 0000b) written in the CRCIN register plus 16 digits, to 0000 0000 0000 0000 0000 0000b, as 0000 0000 0000 0000b plus 8 digits as the default value of the CRCD register. Perform the modulo-2 division on the result. The remainder, 1000 0011 0000 0011b (8303h) can be read from the CRCD register. When going on to (3) above, add 1100 0100 0000 0000 0000 0000b, as C4h (1100 0100b) written in the CRCIN register plus 16 digits, to 1000 0011 0000 0011 0000 0000b, as 8303h (1000 0011 0000 0011b) plus 8 digits as a remainder of (2) left in the CRCD register to perform the modulo-2 division. The remainder, 0000 0010 1001 0010b (0292h) can be read from the CRCD register. Figure 29.3 CRC Operation (CRC-16) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 693 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30. Flash Memory Note P1, P4_4 to P4_7, P7_2 to P7_5, P9_1 of the 80-pin package have no external connections. There are no P11 to P14 in the 80-pin and 100-pin packages. For the 80-pin and 100-pin packages, do not use these pins for the entry of user boot function. 30.1 Introduction Flash memory is used as ROM in this product. The flash memory in this chapter indicates the flash memory inside a microcomputer. In this product, the flash memory can perform in three rewrite modes: CPU rewrite mode, standard serial I/O mode, and parallel I/O mode. Table 30.1 lists Flash Memory Specifications (see to Table 1.1 to Table 1.6 “Specifications” for the items not listed in Table 30.1. Table 30.1 Flash Memory Specifications Specification 3 modes (CPU rewrite, standard serial I/O, and parallel I/O) See Figure 30.1 “Flash Memory Block Diagram”. 1 block (16 Kbytes) 2 blocks (4 Kbytes each) In units of 2 words Block erase Program and erase controlled by software command Program suspend and erase suspend A lock bit protects each block 8 commands 1,000 times (1) 10,000 times (1) 20 years Parallel I/O mode ROM code protect function Standard serial I/O mode ID code check function, forced erase function, and standard serial I/O mode disable function User boot mode Item Flash memory rewrite mode Erase block Program ROM 1 Program ROM 2 Data flash Program method Erase method Program and erase control method Suspend function (under review) Protect method Number of commands Program and erase Program ROM 1 and program ROM 2 cycles Data flash Data retention Flash memory rewrite disable function User boot function Note: 1. Definition of program and erase cycles The program and erase cycles is the number of erase operations performed on a per-block basis. For example, assume a case where a 4-Kbyte block is programmed in 1,024 operations, writing two words at a time, and erased thereafter. In this case, the block is reckoned as having been programmed and erased once. If the program and erase cycles are 1,000 times, each block can be erased up to 1,000 times. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 694 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory Table 30.2 Flash Memory Rewrite Modes Overview CPU Rewrite Mode The flash memory is rewritten when the CPU executes software commands. EW0 mode: Rewritable in areas other than the flash memory EW1 mode: Rewritable in the flash memory Standard Serial I/O Mode The flash memory is rewritten using a dedicated serial programmer. Standard serial I/O mode 1: Clock synchronous serial I/O Standard serial I/O mode 2: Two-wire clock asynchronous serial I/O Parallel I/O Mode The flash memory is rewritten using a dedicated parallel programmer. Flash Memory Rewrite Mode Function Program ROM 1, program ROM 2, and data flash ROM programmer None Areas which can be rewritten Program ROM 1, program ROM 2, Program ROM 1, program and data flash ROM 2, and data flash Serial programmer Parallel programmer REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 695 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.2 Memory Map The flash memory is used as ROM in this product. The flash memory comprises program ROM 1, program ROM 2, and data flash. Figure 30.1 shows a Flash Memory Block Diagram. The flash memory is divided into several blocks, each of which can be protected (locked) from programming or erasing. The flash memory can be rewritten in CPU rewrite, standard serial I/O, and parallel I/O modes. If the size of program ROM 1 is over 512 Kbytes, blocks 8 to 11 can be used when the IRON bit in the PRG2C register is 1 (program ROM 1 addresses 40000h to 7FFFFh enabled). Program ROM 2 can be used when the PRG2C0 bit in the PRG2C register is set to 0 (program ROM 2 enabled). Program ROM 2 includes a user boot code area. Data flash can be used when the PM10 bit in the PM1 register is set to 1 (0E000h to 0FFFFh: data flash). Data flash is divided into block A and block B. Table 30.3 lists the differences among program ROM 1, program ROM 2, and data flash. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 696 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 00E000h 00EFFFh 00F000h 00FFFFh 010000h 013FFFh Block A: 4 Kbytes Data flash Block B: 4 Kbytes Program ROM 2: 16 Kbytes 040000h Block 11: 64 Kbytes 04FFFFh 050000h Block 10: 64 Kbytes 05FFFFh 060000h Block 9: 64 Kbytes 06FFFFh 070000h Block 8: 64 Kbytes 07FFFFh 080000h Block 7: 64 Kbytes 08FFFFh 090000h Block 6: 64 Kbytes Program ROM1 size 768 Kbytes Program ROM1 size 640 Kbytes Program ROM1 size 512 Kbytes Program ROM1 size 384 Kbytes Program ROM1 size 256 Kbytes Program ROM1 size 128 Kbytes 09FFFFh 0A0000h Block 5: 64 Kbytes 0AFFFFh 0B0000h Block 4: 64 Kbytes 0BFFFFh 0C0000h Block 3: 64 Kbytes 0CFFFFh 0D0000h Block 2: 64 Kbytes 0DFFFFh 0E0000h Block 1: 64 Kbytes 0EFFFFh 0F0000h Block 0: 64 Kbytes 0FFFFFh Program ROM1 Figure 30.1 Flash Memory Block Diagram Table 30.3 Program ROM 1, Program ROM 2, and Data Flash Item Flash Memory Program ROM 2 Data Flash 10,000 times Disabled Yes Program ROM 1 Program and erase cycles 1,000 times Forced erase function Enabled Frequency limit when reading No REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 697 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.3 Registers Register Structure Register Name Flash Memory Control Register 0 Flash Memory Control Register 1 Flash Memory Control Register 2 Flash Memory Control Register 3 Flash Memory Control Register 6 Register Symbol FMR0 FMR1 FMR2 FMR3 FMR6 After Reset 0000 0001b (Other than user boot mode) 0010 0001b (User boot mode) 00X0 XX0Xb XXXX 0000b XXXX 0000b XX0X XX00b Table 30.4 Address 0220h 0221h 0222h 0223h 0230h 30.3.1 Flash Memory Control Register 0 (FMR0) Flash Memory Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol FMR0 Bit Symbol FMR00 Bit Name RY/BY status flag Address 0220h 00 After Reset 0000 0001b (other than user boot mode) 0010 0001b (user boot mode) Function RW RO 0 : Busy (being written or erased) 1 : Ready FMR01 CPU rewrite mode select 0 : CPU rewrite mode disabled 1 : CPU rewrite mode enabled bit 0 : Lock bit enabled Lock bit disable select bit 1 : Lock bit disabled 0 : Flash memory operation enabled 1 : Flash memory operation stopped (low power-mode, flash memory initialized) Set to 0 Set to 0 in other than user boot mode Set to 1 in user boot mode 0 : Completed as expected 1 : Completed in error 0 : Completed as expected 1 : Completed in error RW FMR02 RW FMSTP Flash memory stop bit RW — (b4) — (b5) FMR06 Reserved bit Reserved bit Program status flag RW RW RO FMR07 Erase Status Flag RO FMR00 (RY/BY Status Flag) (b0) This bit indicates the flash memory operating state. Condition to become 0: During the following commands execution: Program, block erase, lock bit program, read lock bit status, and block blank check Condition to become 1: Other than those above. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 698 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory FMR01 (CPU Rewrite Mode Select Bit) (b1) Commands can be accepted by setting the FMR01 bit to 1 (CPU rewrite mode enabled). To set the FMR01 bit to 1, write 0 and then 1 in succession. Make sure no interrupts or DMA transfers will occur before writing 1 after writing 0. While in EW0 mode, write to this bit from a program in an area other than flash memory. Enter read array mode, and then set this bit to 0. FMR02 (Lock Bit Disable Select Bit) (b2) The lock bit is disabled by setting the FMR02 bit to 1 (lock bit disabled) (Refer to 30.8.2 “Data Protect Function”). The FMR02 bit does not change the lock bit data but disables the lock bit function. If an erase command is executed when the FMR02 bit is set to 1, the lock bit data status changes from 0 (locked) to 1 (unlocked) after command execution is completed. To set the FMR02 bit to 1, write 0 and then 1 in succession when the FMR01 bit is 1. Make sure no interrupts or DMA transfers will occur before writing 1 after writing 0. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 699 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory FMSTP (Flash Memory Stop Bit) (b3) The FMSTP bit resets flash memory control circuits and minimizes current consumption in the flash memory. Access to the internal flash memory is disabled when the FMSTP bit is set to 1 (flash memory operation stopped). Set the FMSTP bit by a program located in an area other than the flash memory. Set the FMSTP bit to 1 under the following condition. • A flash memory access error occurs while erasing or programming in EW0 mode (the FMR00 bit does not switch back to 1 (ready)). Use the following steps to rewrite the FMSTP bit. To stop the flash memory: (1)Set the FMSTP bit to 1. (2)Wait the wait time to stabilize flash memory circuit (tps). To restart the flash memory: (1)Set the FMSTP bit to 0. (2)Wait the wait time to stabilize flash memory circuit (tps). The FMSTP bit is valid when the FMR01 bit is 1 (CPU rewrite mode). If the FMR01 bit is 0, although the FMSTP bit can be set to 1 by writing 1, the flash memory is neither placed in low-power mode nor initialized. When the FMR23 bit is set to 1 (low-current consumption read mode enabled), do not set the FMSTP bit in the FMR0 register to 1 (flash memory operation stopped). Also, when the FMSTP bit is set to 1, do not set the FMR23 bit to 1. FMR06 (Program Status Flag) (b6) This bit indicates the auto-program operation state. Condition to become 0: • Execute the clear status command. Condition to become 1: • Refer to 30.8.5.4 “Full Status Check”. The following commands cannot be accepted when the FMR06 bit is 1: Program, block erase, lock bit program, read lock bit status, and block blank check. FMR07 (Erase Status Flag) (b7) This bit indicates the auto-erase operation state. Condition to become 0: • Execute the clear status command Condition to become 1: • Refer to 30.8.5.4 “Full Status Check”. The following commands cannot be accepted when the FMR07 bit is 1: Program, block erase, lock bit program, read lock bit status, and block blank check. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 700 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.3.2 Flash Memory Control Register 1 (FMR1) Flash Memory Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol FMR1 Bit Symbol — (b0) FMR11 — (b3-b2) — (b4) — (b5) FMR16 FMR17 Bit Name Reserved bit Write to FMR6 register enable bit Reserved bits Reserved bit Address 0221h Function Read as undefined value 0 : Disabled 1 : Enabled Read as undefined value Set to 0 After Reset 00X0 XX0Xb RW RO 0 RW RO RW RW RO RW No register bit. If necessary, set to 0. Read as undefined value Lock bit status flag Data flash wait bit 0 : Lock 1 : Unlock 0 : 1 wait 1 : Follow the setting of the PM17 bit FMR16 (Lock Bit Status Flag) (b6) This bit indicates the execution result of the read lock bit status command. FMR17 (Data Flash Wait Bit) (b7) This bit is used to select the number of wait states for data flash. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 701 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.3.3 Flash Memory Control Register 2 (FMR2) Flash Memory Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol FMR2 Bit Symbol Address 0222h Bit Name Function Set to 0 0 : Disabled 1 : Enabled After Reset XXXX 0000b RW RW 00 — (b1-b0) FMR22 FMR23 — (b7-b4) Reserved bits Slow read mode enable bit RW RW — Low-current consumption 0 : Disabled 1 : Enabled read mode enabled bit No register bits. If necessary, set to 0. Read as undefined value. FMR22 (Slow Read Mode Enable Bit) (b2) Refer to 9.4 “Power Control in Flash Memory”. FMR23 (Low-current Consumption Read Mode Enable Bit) (b3) Refer to 9.4 “Power Control in Flash Memory”. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 702 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.3.4 Flash Memory Control Register 3 (FMR3) Flash Memory Control Register 3 b7 b6 b5 b4 b3 b2 b1 b0 Symbol FMR3 Bit Symbol FMR30 Bit Name Suspend function enable bit Suspend request bit Address 0223h Function 0 : Disabled 1 : Enabled 0 : Command restart 1 : Suspend request After Reset XXXX 0000b RW RW FMR31 RW FMR32 : Erase not accepted Erase suspend status flag 0 : Erase suspend accepted 1 suspend Program suspend status flag Reserved bit 0 : Program suspend not accepted 1 : Program suspend accepted Read as undefined value RO FMR33 — (b4) — (b7-b5) RO RO No register bits. If necessary, set to 0. Read as undefined value — FMR30 (Suspend Function Enable Bit) (b0) To set the FMR30 bit to 1, write 0 and then 1 in succession. Make sure no interrupts or DMA transfers will occur before writing 1 after writing 0. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 703 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.3.5 Flash Memory Control Register 6 (FMR6) Flash Memory Control Register 6 b7 b6 b5 b4 b3 b2 b1 b0 Symbol FMR6 Bit Symbol FMR60 Bit Name EW1 mode select bit Address 0230h Function 0 : EW0 mode 1 : EW1 mode Set to 1 After Reset XX0X XX00b RW RW 0 1 FMR61 — (b4-b2) — (b5) — (b7-b6) Reserved bit RW Reserved bits Reserved bit Reserved bits Read as undefined value Set to 0 Read as undefined value RO RW RO FMR60 (EW1 Mode Select Bit) (b0) To set the FMR60 bit to 1, write 1 when both bits FMR01 and FMR11 are 1. FMR61 (b1) Set the FMR61 bit to 1 when using CPU rewrite mode. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 704 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.4 Optional Function Select Address 1 (OFS1) In an option function select area, the MCU state after reset and the function to prevent rewrite in parallel I/ O mode are selected. The option function select area is not a special function register (SFR), and therefore cannot be rewritten by a program. Set a proper value when writing a program in the flash memory. The whole option function select area is set to FFh when the block including the option function select area is erased. Optional Function Select Address 1 b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol OFS1 Bit Symbol Bit Name Address FFFFFh Function Factory Setting FFh RW WDTON Watchdog timer start select bit 0 : Watchdog timer starts automatically after reset. 1 : Watchdog timer is in a stopped state after reset. Set to 1. 0 : ROM code protection cancelled. 1 : ROMCP1 bit enabled. 0 : ROM code protection enabled. 1 : ROM code protection disabled. Set to 1. 0 : 2.85 V (Vdet0_2) 1 : 1.90 V (Vdet0_0) 0 : Voltage monitor 0 reset enabled after hardware reset. 1 : Voltage monitor 0 reset disabled after hardware reset. 0 : Count source protection mode enabled after reset. 1 : Count source protection mode disabled after reset. RW — (b1) ROMCR Reserved bit RW ROM code protect cancel bit RW ROMCP1 ROM code protect bit — (b4) VDSEL1 RW Reserved bit RW Vdet0 select bit 1 RW LVDAS Voltage detection 0 circuit start bit RW After-reset count source CSPROINI protection mode select bit RW ROMCR (ROM Code Protect Disable Bit) (b2) ROMCP1 (ROM Code Protect Bit) (b3) These bits are used to inhibit the flash memory from being read or rewritten during parallel I/O mode. Table 30.5 ROM Code Protect 0 0 1 1 Bit Setting ROMCR bit ROMCP1 bit 0 1 0 1 ROM Code Protect Disabled Enabled Disabled REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 705 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.5 Flash Memory Rewrite Disable Function This function inhibits the flash memory from being read, written, and erased. The details are shown for each mode. Parallel I/O mode ROM code protect function Standard serial I/O mode ID code check function, forced erase function, and standard serial I/O mode disable function 30.6 Boot Mode A hardware reset occurs while a low-level signal is applied to the P5_5 pin and a high-level signal is applied to pins CNVSS and P5_0. After reset, the MCU enters boot mode. In boot mode, user boot mode or standard serial I/O mode is selected in accordance with the content of a user boot code area. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 706 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.7 User Boot Function User boot mode can be selected by the status of a port when the MCU starts in boot mode. Table 30.6 shows the User Boot Function Specifications. Table 30.6 User Boot Function Specifications Item Specification Entry pin None or select a port from P0 to P14 User boot start level Select high or low User boot start address Address 10000h (the start address of program ROM 2) Set “UserBoot” in ASCII code to the addresses 13FF0h to 13FF7h in the user boot code area, select a port for entry from addresses 13FF8h to 13FF9h and 13FFAh, and select the start level with the address 13FFBh. After starting boot mode, user boot mode or standard serial I/O mode is selected in accordance with the level of the selected port. In addition, if addresses 13FF0h to 13FF7h are set to “UserBoot” in ASCII code and addresses 13FF8h to 13FFBh are set to “00h”, user boot mode is selected. In user boot mode, the program of address 10000h (the start address of program ROM2) is executed. The content of the OFS1 address is valid. Figure 30.2 shows User Boot Code Area, Table 30.7 lists Start Mode (When the Port Pi_j is Selected for Entry) (1), Table 30.8 lists “UserBoot” in ASCII Code, and Table 30.9 lists Addresses of Selectable Ports for Entry. Program ROM 2 10000h User Boot Start Address 13FF0h User Boot Code Area Boot Code 13FF8h 13FFAh 13FFBh 13FFCh 13FFFh Address Bit Start Level Select Reserved Space Port information for entry 13800h 13FF0h 13FFFh On-chip Debugger Monitor Area User Boot Code Area Figure 30.2 User Boot Code Area REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 707 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory Table 30.7 Start Mode (When the Port Pi_j is Selected for Entry) (1) Boot Code (13FF0h to 13FF7h) Port information for entry Address (13FF8h to 13FF9h) Bit (13FFAh) 00h Start level Select (13FFBh) 00h Port Pi_j input level – high low high low – Start Mode “UserBoot” in 0000h ASCII code (2) Pi register address (3) Pi register address (3) Other than “UserBoot” in ASCII code – User boot mode Standard serial I/O mode User boot mode User boot mode Standard serial I/O mode Standard serial I/O mode 00h to 07h 00h (value of j) 00h to 07h 01h (value of j) – – i=0 to 14, j=0 to 7 (when i = 14, j = 0, 1) Notes: 1. Do not use the combinations of values not listed in Table 30.7. 2. Refer to Table 30.8 ““UserBoot” in ASCII Code” 3. Refer to Table 30.9 “Addresses of Selectable Ports for Entry” Table 30.8 “UserBoot” in ASCII Code Address 13FF0h 13FF1h 13FF2h 13FF3h 13FF4h 13FF5h 13FF6h 13FF7h Table 30.9 Port P0 P1 P2 P3 P4 P5 ASCII Code 55h (upper-case U) 73h (lower-case s) 65h (lower-case e) 72h (lower-case r) 42h (upper-case B) 6Fh (lower-case o) 6Fh (lower-case o) 74h (lower-case t) Addresses of Selectable Ports for Entry Address Port Address 03E0h P6 03ECh 03E1h P7 03EDh 03E4h P8 03F0h 03E5h P9 03F1h 03E8h P10 03F4h 03E9h P11 03F5h Port P12 P13 P14 - Address 03F8h 03F9h 03FCh - REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 708 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.8 CPU Rewrite Mode In CPU rewrite mode, the flash memory can be rewritten when the CPU executes software commands. Program ROM 1, program ROM 2, and data flash can be rewritten with the MCU mounted on a board and without using a ROM programmer. The program and block erase commands are executed only in individual block areas of program ROM 1, program ROM 2, and data flash. Erase-write 0 mode (EW0 mode) and erase-write 1 mode (EW1 mode) are available in CPU rewrite mode. Table 30.10 lists the differences between EW0 mode and EW1 mode. Table 30.10 EW0 Mode and EW1 Mode Item Operating mode Rewrite control Program allocatable area EW0 Mode • Single-chip mode • Memory expansion mode EW1 Mode Single-chip mode • Program ROM 1 • Program ROM 2 • External area • Program ROM 1 • Program ROM 2 The rewrite control program can be executed in program ROM 1 and program ROM 2. The rewrite control program must be Rewrite Control Program Executable transferred to an area other than the flash memory (e.g., RAM) before being Area executed. Rewritable area • Program ROM 1 • Program ROM 2 • Data flash • Program ROM 1 • Program ROM 2 • Data flash Excluding blocks with the rewrite control program • Program and block erase commands Do not execute in a block with the rewrite control program. • Read status register command Do not execute. Read array mode Hold state is maintained. (I/O ports maintains the state before the command execution) (1) Read bits FMR00, FMR06, and FMR07 in the FMR0 register by a program. Software command restriction None Mode after program Read status register mode or erase State during auto Hold state is not maintained. write and auto erase Flash memory status detection • Read bits FMR00, FMR06, and FMR07 in the FMR0 register by a program. • Execute the read status register command, and then read bits SR7, SR5 and SR4 in the status register. Note: 1. Do not generate an interrupt (except NMI interrupt) or start a DMA transfer. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 709 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.8.1 Operating Speed Set a CPU clock frequency of 10 MHz or less by the CM06 bit in the CM0 register and bits CM17 and CM16 in the CM1 register before entering CPU rewrite mode (EW0 or EW1 mode). Also, set the PM17 bit in the PM1 register to 1 (wait state). 30.8.2 Data Protect Function Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR02 bit to 0 (lock bit enabled). The lock bit allows blocks to be individually protected (locked) against programming and erasure. This prevents data from being inadvertently written to or erased from the flash memory. Table 30.11 lists Lock Bit and Block State. Table 30.11 Lock Bit and Block State FMR02 Bit in the FMR0 Register 0 (enabled) 1 (disabled) Lock Bit 0 (locked) 1 (unlocked) 0 (locked) 1 (unlocked) Block State Protected against programming and erasure Can be programmed or erased Can be programmed or erased Condition to become 0: • Execute the lock bit command Condition to become 1: • Execute the block erase command while the FMR02 bit in the FMR0 register is set to 1 (lock bit disabled). If the block erase command is executed while the FMR02 bit is set to 1, the target block is erased regardless of lock bit status. The lock bit data can be read by the read lock bit status command. Refer to 30.8.4 “Software Command”, for details on each command. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 710 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.8.3 Suspend Function (under review) The suspend function suspends automatic programming and erasure. It can be used for an interrupt operation because program ROM1, program ROM2, and data flash can be read while automatic programming or erasure is suspended. Enable the interrupts used to enter suspend mode beforehand. The program command, erase command, and lock bit program command are subjects for suspend. Suspend operation is the same for the program command and lock bit program command, so both commands are described together as program suspend. Do not suspend again in suspend mode. Table 30.12 lists Operation after the Program, Erase, or Lock Bit Program Command is Issued during Suspend. Table 30.12 Operation after the Program, Erase, or Lock Bit Program Command is Issued during Suspend Operation Suspend Command Blocks erased or programmed Other blocks before the suspend mode is entered Erase Program command Commands are not executed. Program command is executed. suspend Command sequence error occurs. Program suspend does not start or an error does not occur even when the FMR31 bit is set to 1 (suspend request). Erase command Commands are not executed. Command sequence error occurs. Lock bit program Commands are not executed. Lock bit program can be executed. command Command sequence error occurs. Program Program command Commands are not executed. Command sequence error occurs. suspend Erase command Lock bit program command REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 711 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.8.4 Software Command Table 30.13 and show Software Commands. Read or write commands and data in 16-bit units. When command code is written, the 8 high-order bits (D15 to D8) are ignored. Table 30.13 Software Commands (Program ROM 1 is not over 512 Kbytes) First Bus Cycle Second Bus Cycle Third Bus Cycle Data Data Data Command Mode Address (D15 to Mode Address (D15 to Mode Address (D15 to D0) D0) D0) Read array Write x xxFFh Read status register Write x xx70h Read x SRD Clear status register Write x xx50h Program Write WA xx41h Write WA WD0 Write WA WD1 Block erase Write x xx20h Write BA xxD0h Lock bit program Write BA xx77h Write BA xxD0h Read lock bit status Write x xx71h Write BA xxD0h Block blank check Write x xx25h Write BA xxD0h SRD : Data in the status register (D7 to D0) WA : Write address (Set the end of the address to 0, 4, 8, or C (hexadecimal).) WD0 : Write data low-order word (16 bits) WD1 : Write data high-order word (16 bits) BA : Highest-order block address (even address) x : Any even address in program ROM 1, program ROM 2, or data flash xx : Eight high-order bits of command code (ignored) Table 30.14 Software Commands (Program ROM 1 is over 512 Kbytes) First Bus Cycle Second Bus Cycle Third Bus Cycle Fourth Bus Cycle Data Data Data Data Mode Address (D15 Mode Address (D15 Mode Address (D15 Mode Address (D15 to D0) to D0) to D0) to D0) Write B0-7 xxFFh Write B8 xxFFh - Command Read array Read status Write BA xx70h Read X SRD register Clear status Write B0-7 xx50h Write B8 xx50h register Program Write BX xx70h Write WA xx41h Write WA WD0 Write WA WD1 Block erase Write BX xx70h Write BA xx20h Write BA xxD0h Lock bit Write BA xx77h Write BA xxD0h program Read lock Write BA xx71h Write BA xxD0h bit status Block blank Write BX xx70h Write BA xx25h Write BA xxD0h check SRD : Data in the status register (D7 to D0) WA : Write address (Make sure 0, 4, 8 or C (hexadecimal) comes at the end of the write address, e.g. xxxx0h.) WD0 : Write data low-order word (16 bits) WD1 : Write data high-order word (16 bits) BA : Highest-order block address (even address) x : Any even address in program ROM 1, program ROM 2, or data flash B0-7 : Any even address in blocks 0 to 7, program ROM 2, or data flash B8 : Any even address in blocks after 8. xx : Eight high-order bits of command code (ignored) BX : Any even address in blocks after block 8 when the target blocks are blocks 0 to 7, program ROM 2, or data flash. Any even address in blocks 0 to 7, program ROM 2, or data flash when the target blocks are blocks after 8. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 712 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory Software commands when program ROM1 is not over 512 Kbytes are described below. Refer to 30.8.3 “Suspend Function (under review)” for program, block erase, and lock bit program commands when using suspend function. 30.8.4.1 Read Array Command The read array command is used to read the flash memory. By writing the command code xxFFh in the first bus cycle, the flash memory enters read array mode. The content of the specified address can be read in 16-bit units by entering the address to be read after the next bus cycle. The flash memory remains in read array mode until another command is written. Therefore, the contents of multiple addresses can be read consecutively. 30.8.4.2 Read Status Register Command The read status register command is used to read the status register. By writing the command code xx70h in the first bus cycle, the status register can be read in the second bus cycle. (Refer to 30.8.5 “Status Register”). To read the status register, read an even address in the program ROM 1, program ROM 2, or data flash. Do not execute this command in EW1 mode. 30.8.4.3 Clear Status Register Command The clear status register command is used to clear the status register. By writing the command code xx50h in the first cycle, bits FMR07 and FMR06 in the FMR0 register are set to 00b, and bits SR5 and SR4 in the status register are set to 00b. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 713 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.8.4.4 Program Command The program command is used to write two words (4 bytes) of data to the flash memory. By writing xx41h in the first bus cycle and data to the write address in the second and third bus cycles, auto-program operation (data program and verify) is started. Make sure 0, 4, 8 or C (hexadecimal) comes at the end of the write address, e.g. xxxx0h. The FMR00 bit in the FMR0 register indicates whether the auto-program operation has been completed. The FMR00 bit is set to 0 (busy) during the auto-program operation and to 1 (ready) after the auto-program operation is completed. After the auto-program operation is completed, the FMR06 bit in the FMR0 register indicates whether or not the auto-program operation has been completed as expected. (Refer to 30.8.5.4 “Full Status Check”). Do not rewrite the addresses already programmed. Figure 30.3 shows a Flow Chart of the Program Command Programming (Suspend Function Disabled). The lock bit protects individual blocks from being programmed inadvertently. (Refer to 30.8.2 “Data Protect Function”.) In EW1 mode, do not execute this command on a block to which the rewrite control program is allocated. In EW0 mode, the flash memory enters read status register mode as soon as the auto-program operation starts. The status register can be read. The SR7 bit in the status register is set to 0 at the same time the auto-program operation starts. It is set to 1 when the auto-program operation is completed. The flash memory remains in read status register mode until the read array command is written. After the auto-program operation is completed, the status register indicates whether or not the auto-program operation has been completed as expected. Start Write the command code xx41h to the write address Write data to the write address FMR00 = 1? NO YES Full status check Program operation is completed Note: 1. Write the command code and data to even addresses. Figure 30.3 Program Command (Suspend Function Disabled) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 714 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.8.4.5 Block Erase Command By writing xx20h in the first bus cycle and xxD0h to the highest-order even address of a block in the second bus cycle, an auto-erase operation (erase and verify) is started on the specified block. The FMR00 bit in the FMR0 register indicates whether the auto-erase operation has been completed. The FMR00 bit is set to 0 (busy) during the auto-erase operation and to 1 (ready) when the autoerase operation is completed. After the auto erase operation is completed, the FMR07 bit in the FMR0 register indicates whether or not the auto erase operation has been completed as expected. (Refer to 30.8.5.4 “Full Status Check”). Figure 30.4 shows a Flow Chart of the Block Erase Command Programming (Suspend Function Disabled). The lock bit protects individual blocks from being erased inadvertently. (Refer to 30.8.2 “Data Protect Function”.) In EW1 mode, do not execute this command on the block to which the rewrite control program is allocated. In EW0 mode, the flash memory enters read status register mode as soon as the auto-erase operation starts. The status register can be read. The SR7 bit in the status register is set to 0 at the same time an auto erase operation starts. It is set to 1 when the auto-erase operation is completed. The flash memory remains in read status register mode until the read array command or read lock bit status command is written. If an erase error occurs, execute the clear status register command and then block erase command at least three times until the erase error is not generated. Start Write the command code xx20h (1) Write xxD0h to the highestorder block address FMR00 YES = 1? YES Full status check NO Block erase operation is completed Notes: 1. Write the command code and data to even addresses. Figure 30.4 Block Erase Command (Suspend Function Disabled) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 715 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.8.4.6 Lock Bit Program Command The lock bit program command is used to set the lock bit for a specified block to 0 (locked). By writing xx77h in the first bus cycle and xxD0h to the highest-order even address of a block in the second bus cycle, the lock bit for the specified block is set to 0. The address value specified in the first bus cycle must be the same highest-order address of a block specified in the second bus cycle. Figure 30.5 shows a Flow Chart of the Lock Bit Program Command Programming (Suspend Function Disabled). Execute the read lock bit status command to read the lock bit state (lock bit data). The FMR00 bit in the FMR0 register indicates whether a lock bit program operation has been completed. Refer to 30.8.2 “Data Protect Function”, for details on lock bit functions and how to set it to 1 (unlocked). Start Write the command code xx77h to the highest-order block address Write xxD0h to the highestorder block address FMR00 = 1? NO YES Full status check Lock bit program operation is completed Note: 1. Write the command code and data to even addresses. Figure 30.5 Lock Bit Program Command (Suspend Function Disabled) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 716 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.8.4.7 Read Lock Bit Status The read lock bit status command is used to read the lock bit state of a specified block. By writing xx71h in the first bus cycle and xxD0h to the highest-order even address of a block in the second bus cycle, the FMR16 bit in the FMR1 register stores information on the lock bit status of a specified block. Read the FMR16 bit after the FMR00 bit in the FMR0 register is set to 1 (ready). Figure 30.6 shows a Flow Chart of the Read Lock Bit Status Command Programming. Start Write the command code xx71h Write xxD0h to the highestorder block address NO FMR00 = 1? YES FMR16 = 0? YES NO Block is locked Block is not locked Note: 1. Write the command code and data to even addresses. Figure 30.6 Read Lock Bit Status Command REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 717 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.8.4.8 Block Blank Check Command The block blank check command is used to check whether or not a specified block is blank (state after erase). By writing xx25h in the first bus cycle and xxD0h in the second bus cycle to the highest-order even address of a block, the check result is stored in the FMR07 bit in the FMR0 register. Read the FMR07 bit after the FMR00 bit in the FMR0 register is set to 1 (ready). The block blank check command is valid for unlocked blocks. If the block blank check command is executed on a block whose lock bit is 0 (locked), the FMR07 bit (SR5) is set to 1 (not blank) regardless of the FMR02 bit state. Figure 30.7 shows a Flow Chart of the Block Blank Check Command Programming. Start Write the command code xx25h Write xxD0h to the highestorder block address NO FMR00 = 1? YES FMR07 = 1? YES NO Blank Not blank Note: 1. Write the command code and data to even addresses. Figure 30.7 Block Blank Check Command REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 718 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.8.5 Status Register The status register indicates flash memory operating state and whether or not an erase or program operation has completed as expected. Bits FMR00, FMR06, and FMR07 in the FMR0 register indicate status register states. In EW0 mode, the status register can be read in one of the following cases. • Any even address in program ROM 1, program ROM 2, or data flash is read after the read status register command is written. • Any even address in the program ROM 1, program ROM 2, or data flash is read from when the program command, block erase command, lock bit program command, or block blank check command is executed until when the read array command is executed. Table 30.15 shows Status Register. Table 30.15 Status Register Bits in Status Register SR0 (D0) SR1 (D1) SR2 (D2) SR3 (D3) SR4 (D4) Bit in FMR0 Register FMR06 Status 0 Reserved bit Reserved bit Reserved bit Reserved bit Program status Definition 1 Value after Reset 0 0 1 Completed as Completed in error expected SR5 (D5) FMR07 Erase status Completed as Completed in error expected SR6 (D6) Reserved bit SR7 (D7) FMR00 Sequencer status Busy Ready D0 to D7: The data buses read when the read status register command is executed. 30.8.5.1 Sequencer Status (Bits SR7 and FMR00) The sequencer status indicates flash memory operating state. Condition to become 0: • During the following commands execution: Program, block erase, lock bit program, read lock bit status, block blank check Condition to become 1: • Other than those above 30.8.5.2 Erase Status (Bits SR5 and FMR07) The erase status indicates auto erase state. Condition to become 0: • Execute the clear status command Condition to become 1: • Refer to 30.8.5.4 “Full Status Check”. When the FMR07 bit is 1, the following commands cannot be accepted: Program, block erase, lock bit program, read lock bit status, block blank check REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 719 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.8.5.3 Program Status (Bits SR4 and FMR06) The program status indicates auto-program operating state. Condition to become 0: • Execute the clear status command Condition to become 1: • Refer to 30.8.5.4 “Full Status Check”. When the FMR06 bit is 1, the following commands cannot be accepted: Program, block erase, lock bit program, read lock bit status, block blank check 30.8.5.4 Full Status Check If an error occurs, bits FMR06 and FMR07 in the FMR0 register are set to 1, indicating the occurrence of an error. Therefore, the execution results can be confirmed by checking these status bits (full status check). Table 30.16 lists Errors and FMR0 Register States and Figure 30.8 shows Full Status Check and Handling Procedure for Errors. Table 30.16 Errors and FMR0 Register States FMR00 Register (Status Register) State FMR07 bit FMR06 bit (SR5 bit) (SR4 bit) Error Command Sequence error Error Occurrence Conditions 1 1 • Command is written incorrectly. • Invalid data (data other than xxD0h or xxFFh) is written in the second bus cycle of the lock bit program or block erase command. (1) • The block erase command is executed on a locked block. (2) • The block erase command is executed on an unlocked block, but the auto-erase operation is not completed as expected. • The block blank check command is executed, and the check result is not blank. • The program command is executed on a locked block. (2) • The program command is executed on an unlocked block, but auto-program operation is not completed as expected. • The lock bit program command is executed, but the lock bit is not written as expected. (2) Erase error 1 0 Program error 0 1 Notes: 1. The flash memory enters read array mode by writing command code xxFFh in the second bus cycle of the command. The command code written in the first bus cycle becomes invalid. 2. When the FMR02 bit is set to 1 (lock bit disabled), no error occurs even under the conditions above. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 720 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory Full status check FMR06 =1 and FMR07=1? NO YES Command sequence error (1) Execute the clear status register command and set bits FMR06 and FMR07 to 0 (completed as expected) . (2) Check if the command is written correctly and execute the correct command. FMR07=0? NO Erase error (1) Execute the clear status register command and set the FMR07 bit to 0 (completed as expected). (2) Execute the read lock bit status command. Set the FMR02 bit in the FMR0 register to 1 (lock bit disabled) if the lock bit in the block where the error occurred is set to 0 (locked). (3) Execute the block erase command again. (4) Execute (1), (2), and (3) at least 3 times until an erase error is not generated. NOTE: If an error still occurs, do not use that block. YES FMR06=0? NO Program error [When a program operation is executed] (1) Execute the clear status register command and set the FMR06 bit to 0 (completed as expected) . (2) Execute the read lock bit status command. Set the FMR02 bit in the FMR0 register to 1 if the lock bit in the block where the error occurred is set to 0. If the lock bit is set to 1 (unlocked), do not use the address in which error has occurred as it is. Execute the block erase command to erase the block, in which error has occurred, before executing the program command to write to the same address again. (3) Execute the program command again. NOTE: If an error occurs, do not use that block. [When a lock bit program operation is executed] (1) Execute the clear status register command and set the FMR06 bit to 0. (2) Set the FMR02 bit in the FMR0 register to 1. (3) Execute the block erase command to erase the block where the error occurred. (4) Execute the lock bit program command again after writing the data as needed NOTE: If an error occurs, do not use that block. Full status check completed FMR07, FMR06: Bits in the FMR0 register Note: When either FMR06 or FMR07 bit is set to 1 (terminated by error), the program, block erase, lock bit program, block blank check, and read lock bit status commands cannot be accepted. Execute the clear status register command before executing each command. Figure 30.8 Full Status Check and Handling Procedure for Errors REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 721 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.8.6 EW0 Mode The MCU enters CPU rewrite mode when the FMR01 bit in the FMR0 register is set to 1 (CPU rewrite mode enabled) and is ready to accept commands. EW0 mode is selected by setting the FMR60 bit in the FMR6 register to 0. Figure 30.9 shows Setting and Resetting of EW0 Mode Software commands control programming and erasing. The FMR0 register or status register indicates whether a program or erase operation is completed as expected or not. Procedure to Enter EW0 Mode Rewrite control program Single-chip mode or memory expansion mode Set the FMR01 bit to 0, and then 1 (CPU rewrite mode enabled). Set the FMR11 bit to 1 (FMR6 register write enabled), then set the FMR6 register to 02h (EW0 mode), and then set the FMR11 bit to 0 (FMR6 register write disabled). Transfer the rewrite control program to an area other than flash memory Execute the software commands Set registers CM0, CM1, and PM1 Execute the read array command Jump to the rewrite control program transferred to an area other than the flash memory. (In the following steps, use the rewrite control program in an area other than the flash memory) Set the FMR01 bit to 0 (CPU rewrite mode disabled) Jump to the desired address in the flash memory Figure 30.9 Setting and Resetting of EW0 Mode Do not execute the following instructions: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction. The following are interrupts which can be used in EW0 mode and operations when the interrupts occur during auto-erase operation or auto-program operation: • Maskable interrupt (suspend disabled) To use the interrupt, allocate a variable vector table in areas other than the flash memory. • Maskable interrupt (suspend enabled) To use the interrupt, allocate a variable vector table in areas other than the flash memory. When the FMR00 bit in the FMR0 register is checked in the interrupt routine and the result is 0 (being written or erased), auto-erase operation or auto-program operation suspends after td(SRSUS) elapses by setting the FMR31 bit in the FMR3 register to 1 (suspend request). Auto-erase operation or auto-program operation restarts by setting the FMR31 bit to 0 (command restart) at the completion of the interrupt. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 722 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory • NMI, watchdog timer, oscillation stop/re-oscillation detect, voltage detect 1, and voltage detect 2 interrupts Auto-erase operation or auto-program operation forcibly stops as soon as the interrupt occurs, and the flash memory is reset. The flash memory restarts after a certain period of time, and then the interrupt process starts. After the flash memory restart, execute auto-erase operation again and confirm that it is completed as expected in order to read the correct value. The watchdog timer is not stopped during the command operation, and the interrupt request can be generated. Initialize the watchdog timer regularly. 30.8.6.1 Suspend Function (EW0 Mode) (under review) When using suspend function in EW0 mode, check the status of the flash memory in the interrupt routine and enter suspend mode. Program suspend or erase suspend is not accepted until td (SRSUS) elapses after the FMR31 bit is set to 1. Access to the flash memory after confirming the acceptance of program suspend or erase suspend by the FMR33 or FMR32 bit. Set the FMR31 bit to 0 (command restart) to restart auto-program and auto-erase operations at the completion of the access to the flash memory. Figure 30.10 to Figure 30.12 show a flow chart in EW0 mode when the suspend function is enabled, and Figure 30.13 shows Suspend Operation Example in EW0 Mode. Start Maskable interrupt (1) Write 0 and then 1 to the FMR30 bit Suspend enabled FMR00 = 0 ? Yes FMR31 ← 1 (3) No Write the command code XX41h to the write address Suspend request I flag ← 1 Interrupt enabled (2) FMR33 = 1 ? No Write data to the write address Access flash memory Yes Program suspend accpeted Access flash memory No FMR00 = 1 ? FMR31 ← 0 Command restart Yes Full status check REIT Program completed Notes : 1. In EW0 mode, set the interrupt vector table for interrupts to be used and the interrupt routine in areas other than flash memory. 2. When interrupts are not used, an instruction to enable interrupts are not necessary. 3. Program is not suspended until td(SR-SUS) elapses after the FMR31 bit is set to 1. Figure 30.10 Program Flowchart in EW0 Mode (Suspend Function Enabled) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 723 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory Start Maskable interrupt (1) Write 0 and then 1 to the FMR30 bit Suspend enabled FMR00 = 0 ? Yes FMR31 ← 1 (3) No Write the command code XX20h to the desired block address Suspend request I flag ←1 Interrupt enabled (2) FMR32 = 1 ? No Write XXD0h to the highest-order block address Access flash memory Yes Erase suspend accepted Access flash memory FMR00 = 1 ? No FMR31 ← 0 Command request Yes Full status check REIT Block erase completed Notes : 1. In EW0 mode, set the interrupt vector table for interrupts to be used and the interrupt routine in areas other than flash memory. 2. When interrupts are not used, an instruction to enable interrupts are not necessary. 3. Erase is not suspended until td(SR-SUS) elapses after the FMR31 bit is set to 1. Figure 30.11 Block Erase Flowchart in EW0 Mode (Suspend Function Enabled) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 724 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory Start Maskable interrupt (1) Write 0 and then 1 to the FMR30 bit Suspend request FMR00 = 0 ? Yes FMR31 ← 1 (3) No Write the command code XX77h to the highest-order block address I flag ← 1 Suspend request Interrupt enabled (2) FMR33 = 1 ? No Write XXD0h to the highestorder block address Access flash memory Yes Program suspend accepted Access flash memory No FMR00 = 1 ? Yes FMR31 ← 0 Command restart REIT Full status check Program completed Notes : 1. In EW0 mode, set the interrupt vector table for interrupts to be used and the interrupt routine in areas other than flash memory. 2. When interrupts are not used, an instruction to enable interrupts are not necessary. 3. Program is not suspended until td(SR-SUS) elapses after the FMR31 bit is set to 1. Figure 30.12 Lock Bit Program Flowchart in EW0 Mode (Suspend Function Enabled) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 725 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory Program Suspend Program command or lock bit program command issued Program completed Programming Programming FMR00 bit Set to 1 by a program Set to 0 by a program FMR31 bit FMR33 bit td(SR-SUS) Program suspend Erase Suspend Erase command issued Program command issued Program completed Erase completed Erasing Programming Erasing FMR00 bit Set to 1 by a program Set to 0 by a program FMR31 bit FMR32 bit td(SR-SUS) Erase suspend FMR00 : Bit in the FMR0 register FMR33, FMR32, FMR31 : Bits in the FMR3 register The above diagram applies under the following condition. The FMR30 bit in the FMR3 register is 1 (suspend enabled). Figure 30.13 Suspend Operation Example in EW0 Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 726 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.8.7 EW1 Mode EW1 mode is selected by setting the FMR60 bit to 1 after setting the FMR01 bit to 1. Figure 30.14 shows Setting and Resetting of EW1 Mode. The FMR0 register indicates whether or not a program or erase operation has completed as expected. The status register cannot be read in EW1 mode. When a program or erase operation is initiated, the CPU halts all program execution until the operation is completed. Procedure to Enter EW1 Mode Program in ROM Single-chip mode Set registers CM0, CM1, and PM1 Write 0 and then 1 (CPU rewrite mode enabled) to the FMR01 bit . Set the FMR11 bit to 1 (FMR6 register rewrite enabled), then set the FMR6 register to 03h (EW1 mode), and then set the FMR11 bit to 0 (FMR6 register rewrite disabled). Execute the software commands Set the FMR01 bit to 0 (CPU rewrite mode disabled) Figure 30.14 Setting and Resetting of EW1 Mode The following are interrupts which can be used in EW1 mode and operations when the interrupts occur during auto-erase operation or auto-program operation: • Maskable interrupt (suspend function enabled) Auto-erase operation or auto-program operation suspends after td(SR-SUS) elapses and the interrupt process is executed. Auto-erase operation or auto-program operation restarts by setting the FMR31 bit in the FMR3 register to 0 (command restart) after the interrupt process is completed. • Maskable interrupt (suspend function disabled) Auto-erase operation or auto-program operation has a higher priority level and the interrupt request has to wait. The interrupt process is executed after auto-erase operation or auto-program operation is completed. • NMI, watchdog timer, oscillation stop/re-oscillation detect, voltage detect 1, and voltage detect 2 interrupts Auto-erase operation or auto-program operation forcibly stops as soon as the interrupt occurs, and the flash memory is reset. The flash memory restarts after a certain period of time, and then the interrupt process starts. After the flash memory restart, execute auto-erase operation again and confirm that it is completed as expected in order to read the correct value. The watchdog timer stops its counting during auto-erasure or auto-programming, but counts during erase suspend or program suspend. The interrupt request can be generated. Initialize the watchdog timer regularly by using the suspend function. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 727 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.8.7.1 Suspend Function (EW1 Mode) (under review) When using suspend function in EW1 mode, an interrupt request is not accepted until td(SR-SUS) elapses after the interrupt request is generated. When the interrupt request is accepted, the flash memory enters erase suspend or program suspend. Set the FMR31 bit to 0 (command restart) to restart automatic program and erase operations at the completion of the interrupt. Figure 30.15 to Figure 30.17 show a flowchart in EW1 mode when the suspend function is enabled, and Figure 30.18 shows Suspend Operation Example in EW1 Mode. Start Maskable interrupt (1) Write 0 and then 1 to the FMR30 bit Suspend enabled Access flash memory Write the command code XX41h to the write address REIT I flag ← 1 Interrupt enabled Write data to the write address NOP instruction × 6 FMR31 ← 0 Command restart FMR00 = 1 ? Yes Full status check No Program completed Note : 1. An interrupt request is not accepted until td(SR-SUS) elapses after the interrupt request is generated. Enable interrupts used to enter suspend mode beforehand. Figure 30.15 Program Flowchart in EW1 Mode (Suspend Function Enabled) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 728 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory Start Maskable interrupt (1) Write 0 and then 1 to the FMR30 bit Suspend enabled Access flash memory Write the command code XX20h to the desired block address REIT I flag ← 1 Interrupt enabled Write XXD0h to the highest-order block address NOP instruction × 6 FMR31 ← 0 Command restart FMR00 = 1 ? No Yes Full status check Block erase completed Note : 1. An interrupt request is not accepted until td(SR-SUS) elapses after the interrupt request is generated. Enable interrupts used to enter suspend mode beforehand. Figure 30.16 Block Erase Flowchart in EW1 Mode (Suspend Function Enabled) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 729 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory Start Maskable interrupt (1) Write 0 and then 1 to the FMR30 bit Write the command code XX77h to the highest-order block address I flag ← 1 Suspend enabled Access flash memory REIT Interrupt enabled Write XXD0h to the highestorder block address NOP instruction × 6 FMR31 ← 0 Command restart FMR00 = 1 ? No Yes Full status check Program completed Note : 1. An interrupt request is not accepted until td(SR-SUS) elapses after the interrupt request is generated. Enable interrupts used to enter suspend mode beforehand. Figure 30.17 Lock Bit Program Flowchart in EW1 Mode (Suspend Function Enabled) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 730 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory Program Suspend Program command or lock bit program command issued Program completed Programming Programming FMR00 bit Set to 0 by a program FMR31 bit Set to 1 by an interrupt request FMR33 bit IR bit td(SR-SUS) Interrupt request accepted Program suspend Erase Suspend Erase command issued Program command issued Program completed Erase completed Erasing Programming Erasing FMR00 bit Set to 1 by an interrupt request Set to 0 by a program FMR31 bit FMR32 bit IR bit td(SR-SUS) Interrupt request accepted Erase suspend FMR00 : Bit in the FMR0 register FMR33, FMR32, FMR31 : Bits in the FMR3 register IR : Interrupt control register to enter suspend mode The above diagram applies under the following condition. The FMR30 bit in the FMR3 register is 1 (suspend enabled). Figure 30.18 Suspend Operation Example in EW1 Mode REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 731 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.9 Standard Serial I/O Mode In standard serial I/O mode, a serial programmer supporting the M16C/65 Group can be used to rewrite program ROM 1, program ROM 2, and data flash while the MCU mounted on a board. Standard serial I/O mode has the following two modes: • Standard serial I/O mode 1: The MCU is connected to the serial programmer by using clock synchronous serial I/O • Standard serial I/O mode 2: The MCU is connected to the serial programmer by using two-wire clock asynchronous serial I/O For more information about the serial programmers, contact the serial programmer manufacturer. Refer to the user’s manual included with your serial programmer for instructions. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 732 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.9.1 ID Code Check Function Use the ID code check function in standard serial I/O mode. This function determines whether the ID codes sent from the serial programmer match those written in the flash memory. If the ID codes do not match, commands sent from the serial programmer are not accepted. However, if the four bytes of the reset vector are “FFFFFFFFh”, ID codes are not compared, allowing all commands to be accepted. The ID codes are 7-byte data stored consecutively, starting with the first byte, at addresses 0FFFDFh, 0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and 0FFFFBh. The flash memory must have a program with the ID codes set in these addresses. Figure 30.19 shows ID Code Storage Addresses. The ID code of “ALeRASE” in ASCII code is used for forced erase function. The ID code of “Protect” in ASCII code is used for standard serial I/O mode disable function. Table 30.17 lists Reserved Word of ID Code. All ID code storage addresses and data must match the combinations listed in Table 30.17. When the forced erase function or standard serial I/O mode disable function is not used, use another combination of ID codes. Table 30.17 Reserved Word of ID Code Reserved word of lD Code (ASCII) ALeRASE Protect FFFDFh ID1 41h (upper-case A) 50h (upper-case P) FFFE3h ID2 4Ch (upper-case L) 72h (lower-case r) FFFEBh ID3 65h (lower-case e) 6Fh (lower-case o) FFFEFh ID4 52h (upper-case R) 74h (lower-case t) FFFF3h ID5 41h (upper-case A) 65h (lower-case e) FFFF7h ID6 53h (upper-case S) 63h (lower-case c) FFFFBh ID7 45h (upper-case E) 74h (lower-case t) All ID code storage addresses and data must match the combinations listed in Table 30.17. ID Code Storage Address Address 0FFFDFh to 0FFFDCh 0FFFE3h to 0FFFE0h 0FFFE7h to 0FFFE4h 0FFFEBh to 0FFFE8h 0FFFEFh to 0FFFECh 0FFFF3h to 0FFFF0h 0FFFF7h to 0FFFF4h 0FFFFBh to 0FFFF8h 0FFFFFh to 0FFFFCh ID3 ID4 ID5 ID6 ID7 OFS1 ID1 ID2 Undefined instruction vector Overflow vector BRK instruction vector Address match vector Single step vector Watchdog timer vector DBC vector NMI vector Reset vector 4 bytes Figure 30.19 ID Code Storage Addresses REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 733 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.9.2 Forced Erase Function Use the forced erase function in standard serial I/O mode. When the reserved word, “ALeRASE” in ASCII code, are sent from the serial programmer as ID codes, the contents of program ROM 1 and program ROM 2 will be erased at once. However, if the ID codes stored in the ID code storage addresses are set to other than a reserved word “ALeRASE” (other than the combination table listed in Table 30.17) when the ROMCP1 bit in the OFS1 address is set to 0 (ROM code protect enabled), forced erase function is ignored and ID code check is executed by ID code check function. Table 30.18 lists conditions and functions for forced erase function. When both the ID codes sent from the serial programmer and the ID codes stored in the ID code storage addresses correspond to the reserved word “ALeRASE”, program ROM 1 and program ROM 2 will be erased. However, when the serial programmer sends other than “ALeRASE”, even if the ID codes stored in the ID code storage addresses are “ALeRASE”, there is no ID match and any command is ignored. The flash memory cannot be operated. Table 30.18 Forced Erase Function Condition ID code from serial Code in ID code programmer storage address ALeRASE ALeRASE Other than ALeRASE (1) Other than ALeRASE ALeRASE Other than ALeRASE (1) ROMCP1 bit in the OFS1 address – 1 (ROM code protect disabled) 0 (ROM code protect enabled) – – Function Program ROM 1 and program ROM 2 all erase (forced erase function) ID code check (ID code check function) ID code check (ID code check function. No ID match) ID code check (ID code check function) Note: 1. For the combination of the stored addresses is “Protect”, refer to 30.9.3 “Standard Serial I/O Mode Disable Function”. 30.9.3 Standard Serial I/O Mode Disable Function Use the standard serial I/O mode disable function in standard serial I/O mode. When the ID codes in the ID code stored addresses are set to “Protect” in ASCII code (refer to Table 30.17 “Reserved Word of ID Code”), the MCU does not communicate with the serial programmer. Therefore, the flash memory cannot be read, written or erased by the serial programmer. User boot mode can be selected, when the ID codes are set to “Protect”. When the ID codes are set to “Protect” and the ROMCP1 bit in the OFS1 address is set to 0 (ROM code protect enabled), ROM code protection cannot be disabled by the serial programmer. Therefore, the flash memory cannot be read, written or erased by the serial or parallel programmer. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 734 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.9.4 Standard Serial I/O Mode 1 In standard serial I/O mode 1, a serial programmer is connected to the MCU by using clock synchronous serial I/O. Table 30.19 lists Pin Functions (Flash Memory Standard Serial I/O Mode 1) and Table 30.20 lists Setting of Standard Serial I/O Mode 1. Figure 30.20 shows Circuit Application in Standard Serial I/O Mode 1. Control pins vary by programmer. For more information, refer to the programmer manual. Table 30.19 Pin VCC1, VCC2, VSS CNVSS RESET XIN XOUT Pin Functions (Flash Memory Standard Serial I/O Mode 1) Name Power input I/O Power Supply Description Apply the flash program and erase voltage to the VCC1 pin, and VCC2 to the VCC2 pin. The VCC application condition is that VCC2 ≤ VCC1. Apply 0 V to the VSS pin. Connect to the VCC1 pin. Reset input pin. During td(OCOS), input a low-level signal to the RESET pin. Input a high-level signal to the XIN pin and open the XOUT pin when a main clock is not used. Connect a ceramic resonator or crystal oscillator between pins XIN and XOUT when the main clock is used. To input an externally generated clock, input it to the XIN pin and open the XOUT pin. Connect this pin to VSS or VCC1. Connect AVCC to VCC1 and AVSS to VSS, respectively. Reference voltage input pin for A/D converter. CNVSS Reset input Clock input Clock output I I I O VCC1 VCC1 VCC1 BYTE AVCC, AVSS VREF P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_1 to P5_4, P5_6, P5_7 P5_0 P5_5 P6_0 to P6_3 P6_4 / RTS1 P6_5/CLK1 P6_6 / RXD1 P6_7 / TXD1 P7_0 to P7_7 P8_0 to P8_7 P9_0 to P9_7 P10_0 to P10_7 P11_0 to P11_7 P12_0 to P12_7 P13_0 to P13_7 P14_0 to P14_1 BYTE input Analog power supply input Reference voltage input Input port P0 Input port P1 Input port P2 Input port P3 Input port P4 Input port P5 CE input EPM input Input port P6 BUSY output SCLK input RXD input TXD output Input port P7 Input port P8 Input port P9 Input port P10 Input port P11 Input port P12 Input port P13 Input port P14 I VCC1 I I I I I I I I I I O I I O I I I I I I I I VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC2 VCC2 VCC1 Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. Input a high-level signal. Input a low-level signal. Input a high- or low-level signal or leave open. BUSY signal output pin Serial clock input pin Serial data input pin. Serial data output pin. Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 735 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory Table 30.20 Setting of Standard Serial I/O Mode 1 Signal CNVSS EPM RESET CE SCLK Input Level VCC1 VSS VSS → VCC1 VCC2 VCC1 VCC1 VCC2 MCU SCLK input TXD output BUSY output RXD input VCC1 VCC1 P6_5/CLK1 P5_0 (CE) P6_7/TXD1 P6_4/RTS1 P6_6/RXD1 CNVSS P5_5 (EPM) VCC1 Reset input User reset signal RESET Notes: 1. Control pins and external circuitry will vary depending on the programmer. For more information, refer to the programmer manual. 2. In this example, modes are switched between single-chip mode and standard serial I/O mode by controlling the CNVSS input with a switch. 3. If in standard serial I/O mode 1 there is a possibility that the user reset signal will go low during serial I/O mode, break the connection between the user reset signal and RESET pin by using, for example, a jumper switch. Figure 30.20 Circuit Application in Standard Serial I/O Mode 1 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 736 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.9.5 Standard Serial I/O Mode 2 In standard serial I/O mode 2, a serial programmer is connected to the MCU by using two-wire clock asynchronous serial I/O. Table 30.21 lists Pin Functions (Flash Memory Standard Serial I/O Mode 2) and Table 30.22 lists Setting of Standard Serial I/O Mode 2. Figure 30.21 shows Circuit Application in Standard Serial I/O Mode 2. Control pins vary by programmer. For more information, refer to the programmer manual. Table 30.21 Pin VCC1, VCC2, VSS CNVSS RESET XIN XOUT Pin Functions (Flash Memory Standard Serial I/O Mode 2) Name Power input I/O Power Supply Description Apply the flash program and erase voltage to the VCC1 pin, and VCC2 to the VCC2 pin. The VCC application condition is that VCC2 ≤ VCC1. Apply 0 V to the VSS pin. Connect to the VCC1 pin. Reset input pin. During td(OCOS), input a low-level signal to the RESET pin. Input a high-level signal to the XIN pin and open the XOUT pin when a main clock is not used. Connect a ceramic resonator or crystal oscillator between pins XIN and XOUT when the main clock is used. To input an externally generated clock, input it to the XIN pin and open the XOUT pin. Connect this pin to VSS or VCC1. Connect AVCC to VCC1 and AVSS to VSS, respectively. Reference voltage input pin for A/D converter. CNVSS Reset input Clock input Clock output I I I O VCC1 VCC1 VCC1 VCC1 BYTE AVCC, AVSS VREF P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_1 to P5_4, P5_6, P5_7 P5_0 P5_5 P6_0 to P6_3 P6_4 / RTS1 P6_5/CLK1 P6_6 / RXD1 P6_7 / TXD1 P7_0 to P7_7 P8_0 to P8_7 P9_0 to P9_7 P10_0 to P10_7 P11_0 to P11_7 P12_0 to P12_7 P13_0 to P13_7 P14_0 to P14_1 BYTE input Analog power supply input Reference voltage input Input port P0 Input port P1 Input port P2 Input port P3 Input port P4 Input port P5 CE input EPM input Input port P6 BUSY output I VCC1 I I I I I I I I I I O I I O I I I I I I I I VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC2 VCC2 VCC1 Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. Input a high-level signal. Input a low-level signal. Input a high- or low-level signal or leave open. Monitor signal output pin for checking the boot program operation. Input a low-level signal Serial data input pin. Serial data output pin. Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. Input a high- or low-level signal or leave open. SCLK input RXD input TXD output Input port P7 Input port P8 Input port P9 Input port P10 Input port P11 Input port P12 Input port P13 Input port P14 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 737 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory Table 30.22 Setting of Standard Serial I/O Mode 2 Signal CNVSS EPM RESET CE P6_5/CLK1 Input Level VCC1 VSS VSS → VCC1 VCC2 VSS VCC2 MCU P6_5/CLK1 TXD output Monitor output RXD intput VCC1 P5_0 (CE) P5_5 (EPM) VCC1 P6_7/TXD1 P6_4/RTS1 P6_6/RXD1 CNVSS Reset input User reset signal RESET Note: 1. In this example, modes are switched between single-chip mode and standard serial I/O mode by controlling the CNVSS input with a switch. Figure 30.21 Circuit Application in Standard Serial I/O Mode 2 30.9.6 Parallel I/O Mode In parallel I/O mode, program ROM 1, program ROM 2, and data flash can be rewritten using a parallel programmer supporting the M16C/65 Group. Contact the parallel programmer manufacturer for more information. Refer to the user’s manual included with your parallel programmer for instructions. 30.9.6.1 ROM Code Protect Function The ROM code protect function inhibits the flash memory from being read or rewritten during parallel I/O mode. Refer to 30.4 “Optional Function Select Address 1 (OFS1)”. The OFS1 address is located in block 0 in program ROM 1. The ROM code protect function is enabled when the ROMCP1 bit is set to 0. To cancel ROM code protect, erase block 0 including the OFS1 address using standard serial I/O mode or CPU rewrite mode. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 738 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.10 Notes on Flash Memory 30.10.1 Functions to Prevent Flash Memory from Being Rewritten Addresses 0FFFDFh, 0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and 0FFFFBh store ID codes. When the wrong data is written to these addresses, the flash memory is prevented from being read or written in standard serial I/O mode. 0FFFFFh is OFS1 address. When the wrong data is written to this address, the flash memory is prevented from being read or written in parallel I/O mode. These addresses correspond to the vector address (H) in fixed vector. 30.10.2 Reading of Data Flash When 2.7 V ≤ VCC1 ≤ 3.0 V and f(BCLK) ≥ 16 MHz, or 3.0 V < VCC1 ≤ 5.5 V and f(BCLK) ≥ 20 MHz, one wait state is necessary to execute the program on the data flash and read the data. Use the PM17 in the PM1 register or FMR17 bit in the FMR1 register to set one wait state. 30.10.3 CPU Rewrite Mode 30.10.3.1 Operating Speed Set a CPU clock frequency of 10 MHz or less by the CM06 bit in the CM0 register and bits CM17 and CM16 in the CM1 register before entering CPU rewrite mode (EW0 or EW1 mode). Also, set the PM17 bit in the PM1 register to 1 (wait state). 30.10.3.2 Prohibited Instructions Do not use the following instructions in EW0 mode: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction. 30.10.3.3 Interrupts (EW0 Mode and EW1 Mode) • Do not use an address match interrupt during command execution because the address match interrupt vector is located in ROM. • Do not use a non-maskable interrupt during block 0 erasure because fixed vector is located in block 0. 30.10.3.4 Rewrite (EW0 Mode) If the power supply voltage drops while rewriting the block where the rewrite control program is stored, the rewrite control program is not correctly rewritten. This may prevent the flash memory from being rewritten. If this error occurs, use standard serial I/O mode or parallel I/O mode for rewriting. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 739 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.10.3.5 Rewrite (EW1 Mode) Do not rewrite any blocks in which the rewrite control program is stored. 30.10.3.6 DMA transfer In EW1 mode, do not generate a DMA transfer while the FMR00 bit in the FMR0 register is set to 0 (auto programming or auto erasing). 30.10.3.7 Wait Mode To enter wait mode, set the FMR01 bit to 0 (CPU rewrite mode disabled) before executing the WAIT instruction. 30.10.3.8 Stop Mode To enter stop mode, set the FMR01 bit to 0 (CPU rewrite mode disabled), and then disable DMA transfer before setting the CM10 bit to 1 (stop mode). 30.10.3.9 Low Power Mode and On-Chip Oscillator Low Power Mode When the CM05 bit is set to 1 (main clock stopped), do not execute the following commands: • Program • Block erase • Lock bit program • Read lock bit status • Block blank check 30.10.3.10 PM13 Bit The PM13 bit in the PM1 register becomes 1 while the FMR01 bit in the FMR0 register is 1 (CPU rewrite mode enabled). The PM13 bit returns to the former value by setting the FMR01 bit to 0 (CPU rewrite mode disabled). When the PM13 bit is changed during CPU rewrite mode, the value of the PM13 bit after being changed is not reflected until the FMR01 bit is set to 0. 30.10.3.11 Area Where Rewrite Control Program is Executed Bits PM10 and PM13 in the PM1 register become 1 in CPU rewrite mode. Execute the rewrite program in internal RAM or an external area which can be used when both bits PM10 and PM13 are 1. Do not use the area (40000h to BFFFFh) where accessible space is expanded when the PM13 bit is 0 and 4-Mbyte mode is set. 30.10.3.12 Program and Erase Cycles and Execution Time Execution time of program, block erase and lock bit program command becomes longer as the number of programming and erasing increases. 30.10.3.13 Suspend of Auto-Erase Operation and Auto-Program Operation When program, block erase, and lock bit program commands are suspended, the blocks for those commands must be erased. Execute program and lock bit program commands again after erasing. Those commands are suspended by the following reset or interrupts: • Reset • NMI, watchdog timer, oscillation stop/re-oscillation detection, voltage monitor 1, and voltage monitor 2 interrupts. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 740 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 30. Flash Memory 30.10.4 Standard Serial I/O Mode 30.10.4.1 User Boot Mode To use user boot mode after standard serial I/O mode, turn off the power when exiting standard serial I/O mode, and then turn on the power again (cold start). The MCU enters user boot mode under the right conditions. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 741 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31. Precautions 31.1 OFS1 Address and ID Code Storage Address OFS1 address and ID code storage address are part of flash memory. When writing a program to flash memory, write an appropriate value to those addresses simultaneously. In the OFS1 address, the MCU state after reset and the function to prevent rewrite in parallel I/O mode are selected. The OFS1 address is 0FFFFFh. This is the most significant address of block 0 in program ROM and upper address of reset vector. Also, the ID code storage address is in block 0 and upper address of interrupt vector. When using a compiler to create a program, the reset vector of interrupt vector is created by the compiler and the OFS1 address or ID code storage address becomes FFh. Write the appropriate value to those addresses separately. The following is an example when writing to the OFS1 address by an assembler. ex) Set FEh to the OFS1 address When using an address control instruction and logical addition: .org 0FFFCh RESET: .lword start | 0FE000000h When using an address control instruction: .org 0FFFCh RESET: .addr start .byte 0FEh 31.2 Notes on Noise Connect a bypass capacitor (approximately 0.1 µF) across pins VCC1 and VSS, and pins VCC2 and VSS using the shortest and thicker possible wiring. Figure 31.1 shows the Bypass Capacitor Connection. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 742 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions Bypass Capacitor Connecting Pattern Connecting Pattern VSS VCC2 M16C/65 Group VSS VCC1 Connecting Pattern Connecting Pattern Bypass Capacitor Figure 31.1 Bypass Capacitor Connection REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 743 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.3 31.3.1 Notes on SFRs Register Settings Table 31.1 lists Registers with Write-Only Bits and registers whose function differs between reading and writing. Set these registers with immediate values. When establishing the next value by altering the existing value, write the existing value to the RAM as well as to the register. Transfer the next value to the register after making changes in the RAM. Table 31.1 Registers with Write-Only Bits Register Watchdog Timer Reset Register Watchdog Timer Start Register Timer A0 Register Timer A1 Register Timer A2 Register Timer A3 Register Timer A4 Register Timer A1-1 Register Timer A2-1 Register Timer A4-1 Register Three-Phase Output Buffer Register 0 Three-Phase Output Buffer Register 1 Dead Time Timer Timer B2 Interrupt Generation Frequency Set Counter UART0 Bit Rate Register UART1 Bit Rate Register UART2 Bit Rate Register UART5 Bit Rate Register UART6 Bit Rate Register UART7 Bit Rate Register UART0 Transmit Buffer Register UART1 Transmit Buffer Register UART2 Transmit Buffer Register UART5 Transmit Buffer Register UART6 Transmit Buffer Register UART7 Transmit Buffer Register SI/O3 Bit Rate Register SI/O4 Bit Rate Register I2C0 Control Register 1 I2C0 Status Register 0 Symbol WDTR WDTS TA0 TA1 TA2 TA3 TA4 TA11 TA21 TA41 IDB0 IDB1 DTT ICTB2 U0BRG U1BRG U2BRG U5BRG U6BRG U7BRG U0TB U1TB U2TB U5TB U6TB U7TB S3BRG S4BRG S3D0 S10 Address 037Dh 037Eh 0327h to 0326h 0329h to 0328h 032Bh to 032Ah 032Dh to 032Ch 032Fh to 032Eh 0303h to 0302h 0305h to 0304h 0307h to 0306h XX11 1111b XX11 1111b 030Ch 030Dh 0249h 0259h 0269h 0289h 0299h 02A9h 024Bh to 024Ah 025Bh to 025Ah 026Bh to 026Ah 028Bh to 028Ah 029Bh to 029Ah 02ABh to 02AAh 0273h 0277h 02B6h 02B8h REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 744 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.4 Notes on Protection After setting the PRC2 bit to 1 (write enabled), by writing to a given SFR, the PRC2 bit becomes 0. Change the registers protected by the PRC2 bit in the next instruction after setting the PRC2 bit to 1. Make sure there are no interrupts or DMA transfers between the instruction that sets the PRC2 bit to 1 and the next instruction. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 745 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.5 31.5.1 Notes on Resets Power Supply Rising Gradient When supplying power to the MCU, make sure that the power supply voltage applied to the VCC1 pin meets the SVCC conditions. Standard Min. Typ. Max. 0.05 Symbol SVCC Parameter Power supply rising gradient (VCC1) (Voltage range: 0 to 2) Unit V/ms Voltage SVCC Power supply rising gradient (VCC1) 2V SVCC 0V Figure 31.2 Timing of SVCC Time 31.5.2 Power-On Reset Use the voltage monitor 0 reset together with the power-on reset. To use power-on reset, set the LVDAS bit in the OFS1 address to 0 (voltage monitor 0 reset enabled after hardware reset). In this case, the voltage monitor 0 reset is enabled (the VW0C0 bit and bit 6 in the VW0C register are 1, and the VC25 bit in the VCR2 register is 1) after power-on reset. Do not disable the bits by a program. 31.5.3 OSDR Bit (Oscillation Stop Detection Reset Detection Flag) When the oscillation stop detection reset is generated, the MCU is reset and then stopped. This state is canceled by hardware reset or voltage monitor 0 reset. Note that the OSDR bit remains unchanged at hardware reset, but is set to 0 (not detected) at voltage monitor 0 reset. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 746 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.6 31.6.1 Notes on Clock Generator Oscillation Circuit Using an Oscillator To connect an oscillator, follow these instructions: • The oscillation characteristics are tied closely to the user’s board design. Perform a careful evaluation of the board before connecting an oscillator. • Oscillation circuit structure depends on the oscillator. The M16C/65 Group contains a feedback resistor, but an external feedback resistor may be required. Contact the oscillator manufacturer regarding circuit constants, as they are dependent on the oscillator or stray capacitance of the mounted circuit. • Check output from the CLKOUT pin to confirm that the clock generated by the oscillation circuit is properly transmitted to the MCU. Procedures for outputting a clock from the CLKOUT pin are listed below. Set the clock output from the CLKOUT pin to 25 MHz or below. Outputting the main clock (1) Set the PRC0 bit in the PRCR register to 1 (write enabled). (2) Set the CM11 bit in the CM1 register to 0, the CM07 bit in the CM0 register to 0, and the CM21 bit in the CM2 register to 0 (main clock selected). (3) Select the clock output from the CLKOUT pin (refer to the following table). (4) Set the PRC0 bit in the PRCR register to 0 (write disabled) Table 31.2 Output from CLKOUT Pin When Selecting Main Clock Bit Setting PCLKR Register CM0 Register PCLK5 Bit Bits CM01 to CM00 1 00b 0 10b 0 11b Output from CLKOUT Pin Clock with the same frequency as the main clock Main clock divided by 8 Main clock divided by 32 Outputting the sub clock (1) Set the PRC0 bit in the PRCR register to 1 (write enabled). (2) Set the CM07 bit in the CM0 register to 1 (sub clock selected). (3) Set the PCLK5 bit in the PCLKR register to 0, and bits CM01 to CM00 in the CM0 register to 01b (fC output from CLKOUT pin). (4) Set the PRC0 bit in the PRCR register to 0 (write disabled) MCU XIN Rf feedback resistor XOUT Rd damping resistor VSS CIN Oscillator COUT Figure 31.3 Oscillation Circuit Example REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 747 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.6.2 31.6.2.1 Noise Countermeasure Clock I/O Pin Wiring • Connect the shortest possible wiring to the clock I/O pin. • Connect (a) the capacitor's ground lead connected to the oscillator, and (b) the MCU's VSS pin, with the shortest possible wiring (maximum 20 mm). Noise XIN VSS XOUT XIN VSS XOUT Bad Figure 31.4 Clock I/O Pin Wiring Good Reason If noise enters the clock I/O pin, the clock waveform becomes unstable, which causes an error in operation or a program runaway. Also, if a potential difference attributed to the noise occurs between the VSS level of the MCU and the VSS level of the oscillator, an accurate clock is not input to the MCU. 31.6.2.2 Large Current Signal Line For large currents that go above the MCU's current range, wire the signal lines as far away from the MCU as possible (especially the oscillator). Reason In the system using the MCU, there are signal lines for controlling motors, LEDs, and thermal heads. When a large current flows through these signal lines, noise is generated due to mutual inductance. MCU Mutual inductance M XIN Large current VSS XOUT GND Figure 31.5 Large Current Signal Line Wiring REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 748 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.6.2.3 Signal Line Whose Level Changes at a High-Speed For a signal line whose level changes at a high-speed, wire it as far away from the oscillator and the oscillator wiring pattern as possible. Do not wire it across or extend it parallel to a clock-related signal line or other signal lines which are sensitive to noise. Reason A signal whose level changes at a high-speed (such as the signal from the TAOUT pin) affects other signal lines due to the level change at rising or falling edges. Specially when the signal line crosses the clock-related signal line, the clock waveform becomes unstable, which causes an error in operation or a program runaway. TAiOUT Do not cross XIN VSS XOUT Bad Figure 31.6 Wiring of Signal Line Whose Level Changes at High-Speed 31.6.3 CPU ClockW • When the external clock is entered from the XIN pin and the main clock is used as the CPU clock, do not stop the external clock. 31.6.4 Oscillation Stop, Re-Oscillation Detect Function • In the following cases, set the CM20 bit to 0 (oscillation stop/re-oscillation detect function disabled), and then change the status of each bit. When the CM05 bit is set to 1 (main clock stopped) When the CM10 bit is set to 1 (stop mode) • To enter wait mode while using the oscillation stop/re-oscillation detection function, set the CM02 bit to 0 (peripheral function clock f1 not turned off during wait mode). • This function cannot be used if the main clock frequency is 2 MHz or below. In that case, set the CM20 bit to 0 (oscillation stop/re-oscillation detect function disabled). • While the CM27 bit is 1 (oscillation stop/re-oscillation detect interrupt), when the FRA01 bit is 1 (40 MHz on-chip oscillator selected), set the FRA00 bit to 1 (40 MHz on-chip oscillator on). (Do not set the FRA00 bit to 0 while FRA01 bit is 1, and vice versa.) REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 749 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.6.5 PLL Frequency Synthesizer To use the PLL frequency synthesizer, stabilize the supply voltage to meet the power supply ripple standard. Standard Typ. Max. 10 0.5 0.3 0.3 0.3 Symbol f (ripple) VP-P (ripple) VCC (|ΔV /ΔT|) Parameter Power supply ripple allowable frequency (VCC1) Power supply ripple allowable (VCC1 = 5 V) amplitude voltage (VCC1 = 3 V) Power supply ripple rising/falling (VCC1 = 5 V) gradient (VCC1 = 3 V) Min. Unit kHz V V V/ms V/ms f (ripple) Power supply ripple allowable frequency (VCC1) Vp-p (ripple) Power supply ripple allowable amplitude voltage f (ripple) VCC1 Vp-p (ripple) Figure 31.7 Voltage Fluctuation Timing REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 750 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.7 31.7.1 Notes on Power Control CPU Clock • When switching clock sources of the CPU clock, wait until the clock oscillation switched to is stabilized. 31.7.2 Wait Mode • After the WAIT instruction, insert at least four NOP instructions. When entering wait mode, the instruction queue reads ahead the instructions following WAIT. Thus, depending on timing, some of the instructions may be executed before the MCU enters wait mode. Program example when entering wait mode is shown below. Program Example: FSET WAIT NOP NOP NOP NOP I ; ; Enter wait mode ; More than four NOP instructions • Do not enter wait mode when the FMR23 bit in the FMR2 register is 1 (low current consumption read mode enabled). Set the FMR23 bit to 0 (low current consumption read mode disabled) and the FMR01 bit to 0 (CPU rewrite mode disabled), and disable DMA transfer before entering wait mode. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 751 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.7.3 Stop Mode • When exiting stop mode by hardware reset, drive the RESET pin low until main clock oscillation is stabilized. • Set the MR0 bit in the TAiMR register (i = 0 to 4) to 0 (pulse not output) when using timer A to exit stop mode. • When entering stop mode, insert a JMP.B instruction immediately after executing an instruction that sets the CM10 bit in the CM1 register to 1, and then insert at least four NOP instructions. When entering stop mode, the instruction queue reads ahead the instructions following the instruction which sets the CM10 bit to 1 (all clock stop). Thus, some of the instructions may be executed before the MCU enters stop mode or before the interrupt routine for returning from stop mode. Program example when entering stop mode Program Example: FSET BSET JMP.B L2: NOP NOP NOP NOP I 0, CM1 L2 ; Enter stop mode ; Insert a JMP.B instruction ; At least four NOP instructions • The CLKOUT pin outputs a high-level signal in stop mode. Thus, if stop mode is entered right after output on the CLKOUT pin changes state from high to low, the high-level durations of the output signal to the CLKOUT pin becomes shorter. Stop mode CLKOUT pin output • When the FMR23 bit in the FMR2 register is 1 (low current consumption read mode enabled), do not enter stop mode. To enter stop mode, execute an instruction to set the CM10 bit in the CM1 register to 1 (stop mode) after setting the FMR23 bit to 0 (low current consumption read mode disabled), setting the FMR01 bit to 0 (CPU rewrite mode disabled), and disabling DMA transfer. 31.7.4 Low Current Consumption Read Mode • Enter low current consumption read mode through slow read mode (refer to Figure 9.4 “Setting and Canceling of Low Current Consumption Read Mode”). • When the FMR23 bit in the FMR2 register is 1 (low current consumption read mode enabled), do not set the FMSTP bit to 1 (flash memory stopped). Also, when the FMSTP bit is 1, do not set the FMR23 bit to 1. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 752 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.8 Notes on Processor Mode Note Do not use memory expansion mode and microprocessor mode in the 80-pin package. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 753 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.9 Notes on Bus Note Do not use bus control pins for the 80-pin package. 31.9.1 Reading Data Flash When 2.7 V ≤ VCC1 ≤ 3.0 V and f(BCLK) ≥ 16 MHz, or when 3.0 V < VCC1 ≤ 5.5 V and f(BCLK) ≥ 20 MHz, one wait state is necessary to read data flash. Use the PM17 bit or the FMR17 bit to specify one wait state. 31.9.2 External Bus When a hardware reset, power-on reset or voltage monitor 0 reset is performed with a high-level input on the CNVSS pin, contents of internal ROM cannot be read. 31.9.3 External Access Soon After Writing to the SFRs When writing to the SFRs is followed by accessing to an external device, the write signal and CSi signal switch simultaneously. Thus, adjust the capacity of individual signal not to make a write signal delay. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 754 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.10 Notes on Memory Space Expansion Function Note Do not use this function for the 80-pin package. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 755 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.11 Notes on Programmable I/O Ports Note P1, P4_4 to P4_7, P7_2 to P7_5, and P9_1 of the 80-pin package have no external connections. Program the direction bits of these ports to 1 (output mode) and the output data to 0 (low level). For the 80-pin and 100-pin packages, do not access the addresses of registers P11 to P14, PD11 to PD14 and PUR3. 31.11.1 Influence of the SD Input If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is 1 (threephase output forcible cutoff by input on the SD pin enabled), pins P7_2 to P7_5 and P8_0 and P8_1 go to the high-impedance state. 31.11.2 Influence of SI/O3 and SI/O4 Setting the SM32 bit in the S3C register to 1 causes the P9_2 pin to go to the high-impedance state. Similarly, setting the SM42 bit in the S4C register to 1 causes the P9_6 pin to go to the high-impedance state. 31.11.3 100-Pin Package Do not access to the addresses assigned to registers P11 to P14 and the PUR register. 31.11.4 80-Pin Package Do not access to the addresses assigned to registers P11 to P14 and the PUR register. Set the direction bits of the ports corresponding to P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 to 1 (output mode). Set the output data to 0 (low-level signal). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 756 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.12 Notes on Interrupts Note Do not use INT3 to INT5 for the 80-pin package. 31.12.1 Reading Address 00000h Do not read the address 00000h by a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from address 00000h during the interrupt sequence. At this time, the IR bit of the accepted interrupt is cleared to 0. If the address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to 0. Thus, some problems may be caused: interrupts may be canceled, and an unexpected interrupt request may be generated. 31.12.2 SP Setting Set a value in the SP (USP, ISP) before accepting an interrupt. The SP (USP, ISP) is set to 0000h after reset. Therefore, if an interrupt is accepted before setting a value in the SP (USP, ISP), the program may go out of control. Especially when using the NMI interrupt, set a value in the ISP at the beginning of the program. For the first instruction after reset only, all interrupts including the NMI interrupt are disabled. 31.12.3 NMI Interrupt • When the NMI interrupt is not used, set the PM24 bit in the PM2 register to 0 (NMI interrupt disabled). • Stop mode cannot be entered while the 24 bit is 1 (NMI interrupt enabled) and input on the NMI pin is low. When input on the NMI pin is low, the CM10 bit in the CM1 register is fixed to 0. • Do not enter wait mode while the 24 bit is 1 (NMI interrupt enabled) and input on the NMI pin is low because the CPU clock remains active even though the CPU stops, and therefore, the current consumption of the chip does not drop. In this case, the normal condition is restored by the next interrupt generated. • Set the low- and high-level durations of the input signal to the NMI pin to 2 CPU clock cycles + 300 ns or more. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 757 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.12.4 Changing an Interrupt Source If the interrupt source is changed, the IR bit in the interrupt control register may inadvertently be set to 1 (interrupt requested). To use an interrupt, change the interrupt source, and then set the IR bit to 0 (interrupt not requested). In this section, the changing of an interrupt source refers to all elements (e.g. changing the mode of a peripheral function) used in changing the interrupt source, polarity, and timing assigned to each software interrupt number. When using an element to change the interrupt source, polarity, or timing, make the change before setting the IR bit to 0 (interrupt not requested). Refer to the descriptions of the individual peripheral functions for details of the peripheral function interrupts. Figure 31.8 shows the Procedure for Changing the Interrupt Generate Factor. Change the interrupt source Disable interrupts (2, 3) Change the interrupt source (including a mode change of peripheral function) Use the MOV instruction to set the IR bit to 0 (interrupt not requested) (3) Enable interrupts (2, 3) Change completed IR bit: A bit in the interrupt control register for the interrupt whose interrupt source is to be changed Notes : 1. The above settings must be executed individually. Do not execute two or more settings simultaneously (using one instruction). 2. Use the I flag for the INTi interrupt (i = 0 to 7). For the interrupts from peripheral functions other than the INTi interrupt, turn off the peripheral function that is the source of the interrupt in order not to generate an interrupt request before changing the interrupt source. In this case, if the maskable interrupts can all be disabled without causing a problem, use the I flag. Otherwise, use the corresponding bits ILVL2 to ILVL0 for the interrupt whose interrupt source is to be changed. 3. Refer to the following “Rewriting the Interrupt Control Register” for details about the instructions to use and the notes to be taken for instruction execution. Figure 31.8 Procedure for Changing the Interrupt Generate Factor REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 758 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.12.5 Rewriting the Interrupt Control Register (a) The interrupt control register for any interrupt should be modified in places where no requests for that register may occur. If an interrupt request generation is a possibility, disable an interrupt and then rewrite the contents of the interrupt control register. (b) When rewriting the contents of the interrupt control register after disabling an interrupt, be careful with the instruction used. • Changing bits other than the IR bit When interrupts corresponding to the register occur, the IR bit may not be set to 1 (interrupt requested) and the interrupts may be ignored. If this causes a problem, use one of the following instructions to change the registers. Instructions: AND, OR, BCLR, or BSET. • Changing the IR bit Depending on the instruction used, the IR bit may not always be set to 0 (interrupt not requested). Therefore, use the MOV instruction to set the IR bit to 0. (c) When using the I flag to disable an interrupt, set the I flag as shown in the sample program code shown below. (Refer to (b) regarding rewriting the contents of the interrupt control registers using the sample program code.) Examples 1 through 3 show how to prevent the I flag from being set to 1 (interrupt enabled) before the contents of the interrupt control register are rewritten, owing to the effects of the internal bus and the instruction queue buffer. Example 1: Using the NOP instruction to pause the program until the interrupt control register is modified INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Set the TA0IC register to 00h. NOP ; NOP FSET I ; Enable interrupts. The number of the NOP instructions is as follows. PM20 = 1 (1 wait): 2, PM20 = 0 (2 waits): 3, when using the HOLD function: 4. Example 2: Using a dummy read to delay the FSET instruction INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Set the TA0IC register to 00h. MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3: Using the POPC instruction to change the I flag INT_SWITCH3: PUSHC FLG FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Set the TA0IC register to 00h. POPC FLG ; Enable interrupts. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 759 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.12.6 INT Interrupt • Either a low level of at least tw (INL) width or a high level of at least tw (INH) width is necessary for the signal input to pins INT0 through INT7 regardless of the CPU operation clock. • If the POL bit in registers INT0IC to INT7IC, bits IFSR7 to IFSR0 in the IFSR register, or bits IFSR31 to IFSR30 in the IFSR3A register are changed, the IR bit may inadvertently be set to 1 (interrupt requested). Be sure to set the IR bit to 0 (interrupt not requested) after changing any of these register bits. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 760 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.13 Notes on Watchdog Timer After the watchdog timer interrupt occurs, use the WDTR register to refresh the watchdog timer counter. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 761 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.14 Notes on DMAC 31.14.1 Write to the DMAE Bit in the DMiCON Register (i = 0 to 3) When both of following conditions are met, follow steps (1) and (2) below. • Write a 1 (DMAi is in active state) to the DMAE bit when it is 1. • A DMA request may occur simultaneously when the DMAE bit is being written. Steps (1) Write a 1 to the DMAE bit and DMAS bit in the DMiCON register simultaneously (1). (2) Make sure that the DMAi is in an initialized state (2) in a program. If the DMAi is not in an initialized state, repeat these two steps. Notes: 1. The DMAS bit remains unchanged even if a 1 is written. However, if a 0 is written to this bit, it is set to 0 (DMA not requested). In order to prevent the DMAS bit from being modified to 0, 1 should be written to the DMAS bit when 1 is written to the DMAE bit. In this way, the state of the DMAS bit immediately before being written can be maintained. Similarly, when writing to the DMAE bit with a read-modify-write instruction, write a 1 to the DMAS bit to maintain a DMA request which is generated during execution. 2. Read the TCRi register to verify whether the DMAi is in an initialized state. If the read value is equal to a value that was written to the TCRi register before DMA transfer start, the DMAi is in an initialized state. (When a DMA request occurs after writing to the DMAE bit, the read value is a value written to the TCRi register minus one.) If the read value is a value in the middle of a transfer, the DMAi is not in an initialized state. 31.14.2 Changing DMA Request Source When the DMS bit or bits DSEL4 to DSEL0 in the DMiSL register are changed, the DMAS bit in the DMiCON sometimes becomes 1 (DMA requested). Set the DMAS bit to 0 (DMA not requested) after the DMS bit or bits DSEL4 to DSEL0 in the DMiSL register are changed. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 762 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.15 Notes on Timer A Note T he 80-pin package does not have pins TA1IN, TA1OUT, TA2IN and TA2OUT. Do not use functions associated with these pins. 31.15.1 Timer A (Timer Mode) 31.15.1.1 Register Setting The timer stops after reset. Set the mode, count source, counter value, etc., using registers TAiMR, TAi, TACS0 to TACS2, TAPOFS, TCKDIVC0, and PCLKR before setting the TAiS bit in the TABSR register to 1 (count starts) (i = 0 to 4). Always make sure registers TAiMR, TACS0 to TACS2, TAPOFS, TCKDIVC0, and PCLKR are modified while the TAiS bit is 0 (count stops), regardless of whether after reset or not. 31.15.1.2 Read from Timer While counting is in progress, the counter value can be read at any time by reading the TAi register. However, if the counter is read at the same time as it is reloaded, the value FFFFh is read. Also, if the counter is read before it starts counting and after a value is set in the TAi register while not counting, the set value is read. 31.15.1.3 Influence of SD If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is 1 (threephase output forcible cutoff by input on the SD pin enabled), pins TA1OUT, TA2OUT, and TA4OUT go to the high-impedance state. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 763 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.15.2 Timer A (Event Counter Mode) 31.15.2.1 Register Setting The timer is stopped after reset. Set the mode, count source, counter value, etc., using the TAiMR register, the TAi register, the UDF register, bits TAZIE, TA0TGL, and TA0TGH in the ONSF register, the TRGSR register, and the TAPOFS register before setting the TAiS bit in the TABSR register to 1 (count starts) (i = 0 to 4). Always make sure the TAiMR register, the UDF register, bits TAZIE, TA0TGL, and TA0TGH in the ONSF register, the TRGSR register, and the TAPOFS register are modified while the TAiS bit is 0 (count stops), regardless of whether after reset or not. 31.15.2.2 Read from Timer While counting is in progress, the counter value can be read at any time by reading the TAi register. However, while reloading, FFFFh can be read in underflow, and 0000h in overflow. When the counter is read before it starts counting and after a value is set in the TAi register while not counting, the set value is read. 31.15.2.3 Influence of SD If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is 1 (threephase output forcible cutoff by input on SD pin enabled), pins TA1OUT, TA2OUT, and TA4OUT go to the high-impedance state. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 764 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.15.3 Timer A (One-Shot Timer Mode) 31.15.3.1 Register Setting The timer is stopped after reset. Set the mode, count source, counter value, etc., using the TAiMR register, the TAi register, bits TA0TGL and TA0TGH in the ONSF register, the TRGSR register, registers TACS0 to TACS2, the TAPOFS register, the TCKDIVC0 register, and the PCLKR register before setting the TAiS bit in the TABSR register to 1 (count starts) (i = 0 to 4). Always make sure the TAiMR register, bits TA0TGL and TA0TGH in the ONSF register, the TRGSR register, registers TACS0 to TACS2, the TAPOFS register, the TCKDIVC0 register, and the PCLKR register are modified while the TAiS bit is 0 (count stops), regardless of whether after reset or not. 31.15.3.2 Stop While Counting When setting the TAiS bit to 0 (count stops), the following occurs: • The counter stops counting and the contents of the reload register are reloaded. • The TAiOUT pin outputs a low-level signal when the POFSi bit in the TAPOFS register is 0 and outputs a high-level signal when it is 1. • After one cycle of the CPU clock, the IR bit in the TAiIC register is set to 1 (interrupt requested). 31.15.3.3 Delay between the Trigger Input and Timer Output One-shot timer output synchronizes with a count source generated internally. When an external trigger is selected, a maximum 1.5 cycle delay of the count source occurs between the trigger input to the TAiIN pin and timer output. 31.15.3.4 Operating Mode Change The IR bit is set to 1 when timer operating mode is set with any of the following procedures: • Selecting one-shot timer mode after reset • Changing the operating mode from timer mode to one-shot timer mode • Changing the operating mode from event counter mode to one-shot timer mode To use the timer Ai interrupt (IR bit), set the IR bit to 0 after the changes listed above are made. 31.15.3.5 Re-Trigger When a trigger occurs while counting, the counter reloads the reload register to continue counting after generating a re-trigger and counting down once. To generate a trigger while counting, generate a re-trigger after more than one cycle of the timer count source has elapsed following the previous trigger. When an external trigger occurs, do not generate a re-trigger for 300 ns before the count value becomes 0000h. The one-shot timer may stop counting. 31.15.3.6 Influence of SD If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is 1 (threephase output forcible cutoff by input on the SD pin enabled), pins TA1OUT, TA2OUT, and TA4OUT enter a high-impedance state. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 765 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.15.4 Timer A (Pulse Width Modulation Mode) 31.15.4.1 Register Setting The timer is stopped after reset. Set the mode, count source, counter value, etc., using the TAiMR register, the TAi register, bits TA0TGL and TA0TGH in the ONSF register, the TRGSR register, registers TACS0 to TACS2, the TAPOFS register, TCKDIVC0 register, the PWMFS register, and the PCLKR register before setting the TAiS bit in the TABSR register to 1 (count starts) (i = 0 to 4). Always make sure the TAiMR register, bits TA0TGL and TA0TGH in the ONSF register, the TRGSR register, registers TACS0 to TACS2, the TAPOFS register, TCKDIVC0 register, the PWMFS register, and the PCLKR register are modified while the TAiS bit is 0 (count stops), regardless of whether after reset or not. 31.15.4.2 Operating Mode Change The IR bit is set to 1 when setting a timer operating mode with any of the following procedures: • Selecting PWM mode or programmable output mode after reset • Changing the operating mode from timer mode to PWM mode or programmable output mode • Changing the operating mode from event counter mode to PWM mode or programmable output mode To use the timer Ai interrupt (IR bit), set the IR bit to 0 by a program after the changes listed above are made. 31.15.4.3 Stop While Counting When setting the TAiS bit to 0 (count stops) during PWM pulse output, the following actions occur. When the POFSi bit in the TAPOFS register is 0: • Counting stops. • When the TAiOUT pin is high, the output level goes low and the IR bit is set to 1. • When the TAiOUT pin is low, both the output level and the IR bit remain unchanged. When the POFSi bit in the TAPOFS register is 1: • Stop counting. • If the TAiOUT pin output is low, the output level goes high and the IR bit is set to 1. • If the TAiOUT pin output is high, both the output level and the IR bit remain unchanged. 31.15.4.4 Influence of SD If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is 1 (threephase output forcible cutoff by input on the SD pin enabled), pins TA1OUT, TA2OUT, and TA4OUT go to the high-impedance state. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 766 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.15.5 Timer A (Programmable Output Mode) 31.15.5.1 Register Setting The timer is stopped after reset. Set the mode, count source, counter value, etc., using the TAiMR register, the TAi register, the TRGSR register, registers TACS0 to TACS2, the TAPOF register, TCKDIVC0 register, the PWMFS register, the PCLKR register, and the TAi1 register before setting the TAiS bit in the TABSR register to 1 (count starts) (i = 1, 2, 4). Always make sure the TAiMR register, the TRGSR register, registers TACS0 to TACS2, the TAPOFS register, TCKDIVC0 register, the PWMFS register, and the PCLKR register are modified while the TAiS bit is 0 (count stops), regardless of whether after reset or not. 31.15.5.2 Operating Mode Change The IR bit is set to 1 when setting a timer operating mode with any of the following procedures: • Selecting PWM mode or programmable output mode after reset • Changing the operating mode from timer mode to PWM mode or programmable output mode • Changing the operating mode from event counter mode to PWM mode or programmable output mode To use the timer Ai interrupt (IR bit), set the IR bit to 0 by a program after the changes listed above are made. 31.15.5.3 Stop While Counting When setting the TAiS bit to 0 (count stops) during pulse output, the following actions occur. When the POFSi bit in the TAPOFS register is 0: • Counting stops. • When the TAiOUT pin is high, the output level goes low and the IR bit is set to 1. • When the TAiOUT pin is low, both the output level and the IR bit remain unchanged. When the POFSi bit in the TAPOFS register is 1: • Stop counting. • If the TAiOUT pin output is low, the output level goes high and the IR bit is set to 1. • If the TAiOUT pin output is high, both the output level and the IR bit remain unchanged. 31.15.5.4 Influence of SD If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is 1 (threephase output forcible cutoff by input on the SD pin enabled), pins TA1OUT, TA2OUT, and TA4OUT go to the high-impedance state. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 767 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.16 Notes on Timer B Note The 80-pin package does not have the TB1IN pin. Do not use functions associated with this pin. 31.16.1 Timer B (Timer Mode) 31.16.1.1 Register Setting The timer is stopped after reset. Set the mode, count source, counter value, etc., using registers TBiMR, TBi, TBCS0 to TBCS3, TCKDIVC0, and PCLKR before setting the TBiS bit in the TABSR or the TBSR register to 1 (count starts) (i = 0 to 5). Always make sure registers TBiMR, TBCS0 to TBCS3, TCKDIVC0, and PCLKR are modified while the TBiS bit is 0 (count stops), regardless of whether after reset or not. 31.16.1.2 Read from Timer The value of the counter while counting can be read from the TBi register at any time. FFFFh is read while reloading. If the counter is read before it starts counting and after a value is set in the TBi register while not counting, the set value is read. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 768 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.16.2 Timer B (Event Counter Mode) 31.16.2.1 Register Setting The timer is stopped after reset. Set the mode, count source, counter value, etc., using the TBiMR register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to 1 (count starts) (i = 0 to 5). Always make sure the TBiMR register is modified while the TBiS bit is 0 (count stops), regardless of whether after reset or not. 31.16.2.2 Read from Timer While counting is in progress, the counter value can be read out at any time by reading the TBi register. However, if this register is read at the same time the counter is reloaded, the read value is always FFFFh. If the TBi register is read after setting a value in it while not counting but before the counter starts counting, the read value is the value set in the register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 769 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.16.3 Timer B (Pulse Period/Pulse Width Measurement Modes) 31.16.3.1 Register Setting The timer is stopped after reset. Set the mode, count source, etc., using registers TBiMR, TBCS0 to TBCS3, TBi, TCKDIVC0, PCLKR, PPWFS1, and PPWFS2 before setting the TBiS bit in the TABSR or TBSR register to 1 (count starts) (i = 0 to 5). Always make sure registers TBiMR, TBCS0 to TBCS3, TCKDIVC0, PCLKR, PPWFS1, and PPWFS2 are modified while the TBiS bit is 0 (count stops), regardless of whether after reset or not. To clear the MR3 bit to 0 by writing to the TBiMR register while the TBiS bit is 1 (count starts), be sure to write the same value as previously written to bits TMOD0, TMOD1, MR0, MR1, TCK0, and TCK1 and a 0 to bit 4. 31.16.3.2 Interrupts The IR bit in the TBiIC register is set to 1 (interrupt requested) when an active edge of a measurement pulse is input or timer Bi overflows (i = 0 to 5). The source of an interrupt request can be determined by using the MR3 bit in the TBiMR register within the interrupt routine. Use the IR bit in the TBiIC register to detect overflows only. Use the MR3 bit only to determine the interrupt source. 31.16.3.3 Operations between Count Start and the First Measurement When a count is started and the first active edge is input, an undefined value is transferred to the reload register. At this time, timer Bi interrupt request is not generated. The value of the counter is undefined after reset. If count is started in this state, the MR3 bit may be set to 1 and timer Bi interrupt request may be generated after count start before an effective edge is input. When a value is set in the TBi register while the TBiS bit is 0 (count stops), the same value is written to the counter. 31.16.3.4 Pulse Period Measurement Mode When an overflow occurs at an active edge, an input is not recognized at the effective edge because an interrupt request is generated only once. Use this mode where an overflow does not occur, or use pulse width measurement. 31.16.3.5 Pulse Width Measurement Mode In pulse width measurement, pulse widths are measured successively. Use a program to check whether the measurement result is a high-level width or a low-level width. When an interrupt request is generated, read the TBiIN pin level inside the interrupt routine, and check whether it is the edge of an input pulse or an overflow. The TBiIN level can be read from bits in the P9 register of corresponding ports. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 770 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.17 Notes on Three-Phase Motor Control Timer Function Note Do not use this function for the 80-pin package. 31.17.1 Timer A, Timer B Refer to 17.5 “Notes on Timer A” and 18.5 “Notes on Timer B”. 31.17.2 Forced Cutoff Input The following pins are affected by the three-phase forced cutoff due to the SD pin input: P7_2/CLK2/TA1OUT/V, P7_3/CTS2/RTS2/TA1IN/V, P7_4/TA2OUT/W, P7_5/TA2IN/W, P8_0/TA4OUT/RXD5/SCL5/U, P8_1/TA4IN/CTS5/RTS5/U REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 771 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.18 Notes on Real-Time Clock 31.18.1 Starting and Stopping Count Real-time clock has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates count start or stop. Bits TSTART and TCSTF are in the RTCCR1 register. Real-time clock starts counting and the TCSTF bit becomes 1 (count starts) when the TSTART bit is set to 1 (count starts). It takes up to two cycles of the count source until the TCSTF bit becomes 1 after setting the TSTART bit to 1. During this time, do not access registers associated with real-time clock (1) other than the TCSTF bit. Also, real-time clock stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit becomes 0 (count stops). It takes up to three cycles of the count source until the TCSTF bit becomes 0 after setting the TSTART bit to 0. During this time, do not access registers associated with real-time clock other than the TCSTF bit. Note: 1. Registers associated with real-time clock: RTCSEC, RTCMIN, RTCHR, RTCWK, RTCCR1, RTCCR2, RTCCSR, RTCCSEC, RTCCMIN, and RTCCHR. 31.18.2 Register Setting (Time Data etc.) Write to the following registers or bits while real-time clock is stopped. • Registers RTCSEC, RTCMIN, RTCHR, RTCWK, and RTCCR2 • Bits H12H24 and RTCPM in the RTCCR1 register • Bits RCS0 to RCS4 in the RTCCSR register Real-time clock is stopped when bits TSTART and TCSTF in the RTCCR1 register are 0 (real-time clock stopped). Also, set all above-mentioned registers and bits (immediately before real-time clock count starts) before setting the RTCCR2 register. Figure 20.4 shows Time and Day Change Procedure (No Compare Mode or Compare 1 Mode), and Figure 20.5 shows Time and Day Change Procedure (Compare 2 Mode or Compare 3 Mode). 31.18.3 Register Setting (Compare Data) Write to the following registers when the BSY bit in the RTCSEC register is 0 (not while data is updated). • Registers RTCCSEC, RTCCMIN, and RTCCHR REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 772 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.18.4 Time Reading Procedure of Real-Time Clock Mode In real-time clock mode, read time data bits (1) when the BSY bit in the RTCSEC register is 0 (not while data is updated). When reading multiple registers, if data is rewritten between reading registers, an errant time will be read. In order to prevent this, use the reading procedure shown below. • Using an interrupt Read necessary contents of time data bits in the real-time clock interrupt routine. • Monitoring by a program 1 Monitor the IR bit in the RTCTIC register by a program and read necessary contents of time data bits after the IR bit in the RTCTIC register becomes 1 (periodic interrupt request generated). • Monitoring by a program 2 (1)Monitor the BSY bit. (2)Monitor until the BSY bit becomes 0 after the BSY bit becomes 1 (the BSY bit is set to 1 for approximately 62.5 ms). (3)Read necessary contents of time data bits after the BSY bit becomes 0. • Using read results if they are the same value twice (1)Read necessary contents of time data bits. (2)Read the same bit as (1) and compare the contents. (3)Recognize as the correct value if the contents match. If the contents do not match, repeat until the read contents match with the previous contents. Also, when reading several registers, read them as continuously as possible. Note: 1. Time data bits are shown below. Bits SC12 to SC10 and SC03 to SC00 in the RTCSEC register Bits MN12 to MN10 and MN03 to MN00 in the RTCMIN register Bits HR11 to HR10 and HR03 to HR00 in the RTCHR register Bits WK2 to WK0 in the RTCWK The RTCPM bit in the RTCCR1 register REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 773 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.19 Notes on Pulse Width Modulator Note The 80-pin package does not have pins P4_6 and P4_7. Use pins P9_3 and P9_4 for PWM0 and PWM1 output. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 774 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.20 Notes on Remote Control Signal Receiver Note The 80-pin package does not have the PMC1 pin. Use the PMC0 pin for external pulse input. 31.20.1 Start/Stop of PMCi The EN bit in the PMCiCON0 register controls start/stop of PMCi. The ENFLG bit in the PMCiCON2 register indicates that the operation starts or stops. The PMCi circuit starts operating by setting the EN bit to 1 (operation starts) and the ENFLG bit becomes 1. It takes up to two cycles of the count source until the ENFLG bit becomes 1 after setting the EN bit to 1. During this period, do not access registers associated with PMCi (registers listed in Table 22.3 and Table 22.4 “register structure (PMCi circuit)”) excluding the ENFLG bit. When the EN bit is set to 0 (operation stops), PMCi circuit stops operating and the ENFLG bit becomes 0 (operation stops). It takes up to one cycle of the count source until the ENFLG bit becomes 0 after setting the EN bit to 0. 31.20.2 Register Reading Procedure If reading the following registers when the data changes, undefined value may be read. Each flag in registers PMCiCON2 and PMCiSTS Registers PMCiTIM, PMC0DAT0 to PMC0DAT5, PMCiBC, and PMC0RBIT Read above registers as follows to avoid reading the undefined value. In pattern match mode • Using interrupt Set the DRINT bit in the PMCiINT register to 1 (data reception complete interrupt enabled) and read the registers within PMCi interrupt routine. • Monitoring by a program 1 Set the DRINT bit in the PMCiINT register to 1 (data reception complete interrupt enabled) and monitor the IR bit in the PMCiIC register by a program. Read the registers when the IR bit becomes 1 (interrupt request is generated). • Monitoring by a program 2 (1) Monitor the DRFLG bit in the PMCiSTS register (2) When the DRFLG bit becomes 1, monitor the DRFLG bit until it becomes 0. (3) Read the necessary content of the registers when the DRFLG bit becomes 0. In input capture mode • Using interrupt Set the TIMINT bit in the PMCiINT register to 1 (timer measure interrupt enabled) and read the registers within PMCi interrupt routine. • Monitoring by a program 1 Set the TIMINT bit in the PMCiINT register to 1 (timer measure interrupt enabled) and monitor the IR bit in the PMCiIC register by a program. Read the registers when the IR bit becomes 1 (interrupt request is generated). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 775 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.21 Notes on Serial Interface UARTi (i = 0 to 2, 5 to 7) Note The 80-pin package does not have pins CLK2 and CTS2/RTS2 for UART2. Do not use functions associated with these pins. UART6 and UART7 are not included. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is 1 (threephase output forcible cutoff by input on SD pin enabled), the following pins go to high-impedance state: P7_2/CLK2/TA1OUT/V, P7_3/ CTS2 / RTS2 /TA1IN/ V, P7_4/TA2OUT/W, P7_5/TA2IN/ W, P8_0/ TA4OUT/RXD5/SCL5/U, P8_1/TA4IN/CTS5/RTS5/U 31.21.1 Clock Synchronous Serial I/O 31.21.1.1 Transmission/Reception When the RTS function is used with an external clock, RTSi pin (i = 0 to 2, 5 to 7) outputs a low-level signal, which informs the transmitting side that the MCU is ready for a receive operation. The RTSi pin outputs a high-level signal when a receive operation starts. Therefore, a transmit timing and receive timing can be synchronized by connecting the RTSi pin to the CTSi pin of the transmitting side. The RTS function is disabled when an internal clock is selected. 31.21.1.2 Transmission If an external clock is selected, the following conditions must be met while the external clock is held high when the CKPOL bit in the UiC0 register (i = 0 to 2, 5 to 7) is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the transmit and receive clock), or while the external clock is held low when the CKPOL bit is set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the transmit and receive clock). • The TE bit in the UiC1 register is 1 (transmission enabled). • The TI bit in the UiC1 register is 0 (data present in the UiTB register). • When CTS function is selected, input on the CTSi pin is low. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 776 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.21.1.3 Reception In clock synchronous serial I/O mode, the shift clock is generated by activating a transmitter. Set the UARTi-associated registers for a transmit operation even if the MCU is used for receive operation only. Dummy data is output from the TXDi pin (i = 0 to 2, 5 to 7) while receiving. When an internal clock is selected, the shift clock is generated by setting the TE bit in the UiC1 register to 1 (transmission enabled) and placing dummy data in the UiTB register. When an external clock is selected, set the TE bit to 1 (transmission enabled), place dummy data in the UiTB register, and input an external clock to the CLKi pin to generate the shift clock. If data is received consecutively, an overrun error occurs when the RI bit in the UiC1 register is set to 1 (data present in the UiRB register) and the next receive data is received in the UARTi receive register. And then, the OER bit in the UiRB register is set to 1 (overrun error occurred). At this time, the UiRB register is undefined. When an overrun error occurs, program the transmitting and receiving sides to retransmit the previous data. If an overrun error occurs, the IR bit in the SiRIC register remains unchanged. To receive data consecutively, set dummy data in the low-order byte in the UiTB register per each receive operation. When an external clock is selected, the following conditions must be met while the external clock is held high when the CKPOL bit is 0 (transmit data output at the falling edge and receive data input at the rising edge of the serial clock), or while the external clock is held low when the CKPOL bit is 1 (transmit data output at the rising edge and receive data input at the falling edge of the serial clock). • The RE bit in the UiC1 register is 1 (reception enabled). • The TE bit in the UiC1 register is 1 (transmission enabled). • The TI bit in the UiC1 register is 0 (data present in the UiTB register). REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 777 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.21.2 UART (Clock Asynchronous Serial I/O) Mode 31.21.2.1 Transmission/Reception When the RTS function is used with an external clock, the RTSi pin (i = 0 to 2, 5 to 7) outputs a lowlevel signal, which informs the transmitting side that the MCU is ready for a receive operation. The RTSi pin outputs a high-level signal when a receive operation starts. Therefore, a transmit timing and receive timing can be synchronized by connecting the RTSi pin to the CTSi pin of the transmitting side. The RTS function is disabled when an internal clock is selected. 31.21.2.2 Transmission When an external clock is selected, the following conditions must be met while the external clock is held high when the CKPOL bit in the UiC0 register (i = 0 to 2, 5 to 7) is 0 (transmit data output at the falling edge and receive data input at the rising edge of the transmit and receive clock), or while the external clock is held low when the CKPOL bit is 1 (transmit data output at the rising edge and receive data input at the falling edge of the transmit and receive clock). • The TE bit in the UiC1 register is 1 (transmission enabled). • The TI bit in the UiC1 register is 0 (data present in the UiTB register). • When CTS function is selected, input on the CTSi pin is low. 31.21.3 Special Mode 1 (I2C Mode) 31.21.3.1 Generation of Start and Stop Conditions When generating start, stop and restart conditions, set the STSPSEL bit in the UiSMR4 register (i = 0 to 2, 5 to 7) to 0 and wait for more than half cycle of the transmit and receive clock. Then set each condition generation bit (STAREQ, RSTAREQ and STPREQ) from 0 to 1. 31.21.3.2 IR Bit Set the following bits first, and then set the IR bit in the UARTi interrupt control registers to 0 (interrupt not requested). Bits SMD2 to SMD0 in the UiMR register, the IICM bit in the UiSMR register, the IICM2 bit in the UiSMR2 register, the CKPH bit in the UiSMR3 register 31.21.4 Special Mode 4 (SIM Mode) After reset, a transmit interrupt request is generated by setting bits U2IRS and U2ERE in the U2C1 register to 1 (transmission completed) and 1 (error signal output), respectively. Therefore, when using SIM mode, make sure to set the IR bit to 0 (interrupt not requested) after setting these bits. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 778 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.22 Notes on SI/O3 and SI/O4 Note The 80-pin package does not have the SIN3 pin for SI/O3. SI/O3 is used for transmission only. No reception is possible. 31.22.1 SOUTi Pin Level When SOUTi Output Disabled When the SMi2 bit in the SiC register is set to 1 (SOUTi output disabled), the target pin goes to highimpedance state regardless of which function of the pin is being used. 31.22.2 External Clock Control The data written into the SiTRR register is shifted every time the external clock is input. When completing data transmission/reception of the 8th bit, read or write into the SiTRR register before inputting the clock for the next data transmission/reception. 31.22.3 Register Access When Using External Clock When the SMi6 bit in the SiC register is set to 0 (external clock), write into the SMi7 bit in the SiC register and the SiTRR register under the following conditions: • When the SMi4 bit in the SiC register is set to 0 (transmit data is output at falling edge of transmit/ receive clock and receive data is input at rising edge): CLKi input is high level. • When the SMi4 bit in the SiC register is set to 1 (transmit data is output at rising edge of transmit/ receive clock and receive data is input at falling edge): CLKi input is low level. 31.22.4 SiTRR Register Access Write transmit data into the SiTRR register while transmission/reception stops. Read receive data from the SiTRR register while transmission/reception stops. The IR bit in the SiIC register becomes 1 (interrupt request) during output of the 8th bit. If the SM26 bit (SOUT3) or SM27 bit (SOUT4) in the S32C2 register is set to 0 (high-impedance after transmission), SOUTi pin becomes high-impedance when the transmit data is written into the SiTRR register immediately after an interrupt request is generated, and hold time of the transmit data becomes shorter. 31.22.5 Pin Function Switch When Using Internal Clock If the SMi3 bit in the SiC register (i = 3, 4) changes from 0 (I/O port) to 1 (SOUTi output, CLK function) when setting the SMi2 bit to 0 (SOUTi output) and the SMi6 bit to 1 (internal clock), SOUTi initial value set to the SOUTi pin by the SMi7 bit may be output about for 10 ns. After that, the SOUTi pin becomes high-impedance. If the output level from the SOUTi pin when the SMi3 bit changes from 0 to 1 becomes a problem, set the SOUTi initial value by the SMi7 bit. 31.22.6 Operation After Reset When Selecting External Clock When the SMi6 bit in the SiC register is set to 0 (external clock) after reset, the IR bit in the SiIC register becomes 1 (interrupt request) by inputting the external clock for 8 bits to the CLKi pin. This will also happen even when the SMi3 bit in the SiC register is 0 (serial interface disabled) or before the value is written into the SiTRR register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 779 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.23 Notes on Multi-Master I2C-bus Interface 31.23.1 Limitation on CPU Clock When the CM07 bit in the CM0 register is 1 (CPU clock is a sub clock), do not access the registers listed in Table 25.4 “Register Configuration”. Set the CM07 bit to 0 (main clock, PLL clock, or on-chip oscillator clock) to access these registers. 31.23.2 Register Access Notes are described to access the I2C interface control registers. The period from the rising edge of 1st clock of slave address or one-byte data transmission/reception to the falling edge of an ACK clock is considered as “period of transmission/reception”. When the ACKCLK bit is 0 (no ACK clock), the period of transmission/reception is from the rising edge of 1st clock of slave address or one-byte data transmission/reception to the falling edge of 8th clock. 31.23.2.1 S00 Register Do not write to the S00 register during transmission/reception. 31.23.2.2 S10 Register Do not change bits other than the IHR bit in the S10 register during transmission/reception. 31.23.2.3 S20 Register Do not change bits other than the ACKBIT bit in the S20 register during transmission/reception. 31.23.2.4 S3D0 Register • Do not use the bit managing instruction (read-modify-write instruction) to access the S3D0 register. • Bits ICK1 and ICK0 should be changed when the ES0 bit in the S1D0 register is 0 (I2C interface disabled). 31.23.2.5 S4D0 Register Bits ICK4 to ICK2 should be changed when the ES0 bit in the S1D0 register is 0 (I2C interface disabled). 31.23.2.6 S10 Register • Do not use the bit managing instruction (read-modify-write instruction) to access the S10 register. • Do not write to the S10 register when bits MST and TRX change their values. Figure 25.13 “Start Condition Detection” to Figure 25.15 “Operation After Completion of Slave Address/ Data Transmit/Receive” shows when bits MST and TRX change. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 780 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.24 Notes on CEC (Consumer Electronics Control) 31.24.1 Registers and Bit Operation The registers and the bits of the CEC function are synchronized with the count source. Therefore, the internal circuit starts to operate from the next count source timing, while the contents of the register is changed immediately after rewriting the value of the register. When changing the value of the same bit successively or reading the bit changed under the influence of another bit, wait for one or more cycles of the count source. Example: when changing the value of the same bit successively (1) Change the bit to 0. (2) Wait for one or more cycles of the count source. (3) Change the same bit to 1. Example: when reading the bit changed under the influence of another bit (after the reception is disabled, to ensure that the CRERRFLG bit in the CECFLG register becomes 0 (no reception error detected) ). (1) Set the CRXDEN bit in the CECC3 register to 0 (reception disabled) (2) Wait for one or more cycles of the count source (3) Read the CRERRFLG bit in the CECFLG register. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 781 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.25 Notes on A/D Converter 31.25.1 Analog Input Pin When VCC1 ≥ VCC2, set analog input voltage as follows: analog input voltage (AN_0 to AN_7, ANEX0, and ANEX1) ≤ VCC1 analog input voltage (AN0_0 to AN0_7 and AN2_7 to AN2_7) ≤ VCC2 Do not use any of four pins AN4 to AN7 as analog input pins if a key input interrupt is to be used (key input interrupt request is generated when analog input voltage becomes low level). 31.25.2 φAD Frequency Set φAD to 2 MHz or more, but an upper limit is set as follows: 4.0 ≤ VCC1 ≤ 5.5V: φAD ≤ 25 MHz 3.2 ≤ VCC1 ≤ 4.0V: φAD ≤ 16 MHz 3.0 ≤ VCC1 ≤ 3.2V: φAD ≤ 10 MHz 31.25.3 Pin Configuration Three capacitors should be respectively put between pins AVCC, VREF, analog input (ANi (i = 0 to 7), ANEXi, AN0_i, and AN2_i) and the AVSS pin to protect from error operations caused by noise, latchup, or to reduce conversion errors. Also, a capacitor between the VCC1 pin and the VSS pin. Figure 31.9 shows Example of Pin Configuration. MCU VCC1 V CC1 C4 VSS VCC2 VCC2 C5 VSS ANi: ANi (i = 0 to 7), AN0_i, AN2_i, ANEXi Notes: 1.C1 ≥ 0 .1 μF, C2 ≥ 0 .1 μF, C3 ≥ 100pF, C4 ≥ 0 .1 μF, C5 ≥ 0.1 μF (reference values). 2.The traces for the capacitor and MCU should be short and wide as much as physically possible. ANi VREF C1 AVSS C3 C2 AVCC VCC1 Figure 31.9 Example of Pin Configuration 31.25.4 Register Access Set registers ADCON0 (exclude bit 6), ADCON1, and ADCON2 when A/D conversion stops (before trigger is generated). Set the ADSTBY bit which is 1 to 0 after A/D conversion stops. 31.25.5 A/D Conversion Start If the ADSTBY bit in the ADCON1 is changed from 0 (A/D operation stopped) to 1 (A/D operation enabled), wait for 1 φA/D cycle or more before starting A/D conversion. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 782 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.25.6 A/D Operation Mode Change When A/D operation mode has been changed, re-select analog input pins by using bits CH2 to CH0 in the ADCON0 register or bits SCAN1 to SCAN0 in the ADCON1 register. 31.25.7 State When Forcibly Terminated If A/D conversion in progress is halted by setting the ADST bit in the ADCON0 register to 0, the conversion result is undefined. In addition to that, the unconverted ADi register may also become undefined. Do not use any ADi registers when setting the ADST bit to 0 by a program during A/D conversion. 31.25.8 A/D Open-Circuit Detection Assist Function The conversion result in open-circuit depends on the external circuit. Use this function only after careful evaluation for the system. Do not use this function when VCC1 > VCC2. When A/D conversion starts after changing the AINRST register, follow these procedures: (1) Change bits AINRST1 to AINRST0 in the AINRST register. (2) Wait for one cycle of φAD. (3) Set the ADST bit in the ADCON0 register to 1 (A/D conversion start). 31.25.9 Detection of Completion of A/D Conversion In one-shot mode and single sweep mode, use the IR bit in the ADIC register to detect completion of A/D conversion. When not using interrupt, set the IR bit to 0 by a program after the detection. When 1 is written to the ADST bit in the ADCON0 register, the ADST bit becomes 1 (A/D conversion start) after start processing time (refer to Table 27.7 “Cycles of A/D Conversion Item”) elapses. When reading the ADST bit shortly after writing 1, 0 (A/D conversion stop) may be read. Write 1 to the ADST bit by a program. ADST bit in the ADCON0 register Start processing time IR bit in the ADIC register A/D conversion Set to 0 by acceptance of an interrupt request or by a program. Figure 31.10 ADST Bit Operation 31.25.10 Register Settings Set the CKS3 bit, and then set other A/D converter related registers. Also, after changing the CKS3 bit, set the A/D converter related registers again. Note that bits in the ADCON2 register and the CKS3 bit can be set simultaneously. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 783 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.26 Notes on D/A Converter 31.26.1 Not Using D/A Converter When the D/A converter is not used, set the DAiE bit (i = 0 to 1) to 0 (output disabled) and the DAi register to 00h in order to minimize unnecessary current consumption and prevent the flow of a current to R-2R resistor. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 784 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.27 Notes on Flash Memory Note P1, P4_4 to P4_7, P7_2 to P7_5, P9_1 of the 80-pin package have no external connections. There are no P11 to P14 in the 80-pin and 100-pin packages. For the 80-pin and 100-pin packages, do not use these pins for the entry of user boot function. 31.27.1 Functions to Prevent Flash Memory from Being Rewritten Addresses 0FFFDFh, 0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and 0FFFFBh store ID codes. When the wrong data is written to these addresses, the flash memory is prevented from being read or written in standard serial I/O mode. 0FFFFFh is OFS1 address. When the wrong data is written to this address, the flash memory is prevented from being read or written in parallel I/O mode. These addresses correspond to the vector address (H) in fixed vector. 31.27.2 Reading of Data Flash When 2.7 V ≤ VCC1 ≤ 3.0 V and f(BCLK) ≥ 16 MHz, or 3.0 V < VCC1 ≤ 5.5 V and f(BCLK) ≥ 20 MHz, one wait state is necessary to execute the program on the data flash and read the data. Use the PM17 in the PM1 register or FMR17 bit in the FMR1 register to set one wait state. 31.27.3 CPU Rewrite Mode 31.27.3.1 Operating Speed Set a CPU clock frequency of 10 MHz or less by the CM06 bit in the CM0 register and bits CM17 and CM16 in the CM1 register before entering CPU rewrite mode (EW0 or EW1 mode). Also, set the PM17 bit in the PM1 register to 1 (wait state). 31.27.3.2 Prohibited Instructions Do not use the following instructions in EW0 mode: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction. 31.27.3.3 Interrupts (EW0 Mode and EW1 Mode) • Do not use an address match interrupt during command execution because the address match interrupt vector is located in ROM. • Do not use a non-maskable interrupt during block 0 erasure because fixed vector is located in block 0. 31.27.3.4 Rewrite (EW0 Mode) If the power supply voltage drops while rewriting the block where the rewrite control program is stored, the rewrite control program is not correctly rewritten. This may prevent the flash memory from being rewritten. If this error occurs, use standard serial I/O mode or parallel I/O mode for rewriting. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 785 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.27.3.5 Rewrite (EW1 Mode) Do not rewrite any blocks in which the rewrite control program is stored. 31.27.3.6 DMA transfer In EW1 mode, do not generate a DMA transfer while the FMR00 bit in the FMR0 register is set to 0 (auto programming or auto erasing). 31.27.3.7 Wait Mode To enter wait mode, set the FMR01 bit to 0 (CPU rewrite mode disabled) before executing the WAIT instruction. 31.27.3.8 Stop Mode To enter stop mode, set the FMR01 bit to 0 (CPU rewrite mode disabled), and then disable DMA transfer before setting the CM10 bit to 1 (stop mode). 31.27.3.9 Low Power Mode and On-Chip Oscillator Low Power Mode When the CM05 bit is set to 1 (main clock stopped), do not execute the following commands: • Program • Block erase • Lock bit program • Read lock bit status • Block blank check 31.27.3.10 PM13 Bit The PM13 bit in the PM1 register becomes 1 while the FMR01 bit in the FMR0 register is 1 (CPU rewrite mode enabled). The PM13 bit returns to the former value by setting the FMR01 bit to 0 (CPU rewrite mode disabled). When the PM13 bit is changed during CPU rewrite mode, the value of the PM13 bit after being changed is not reflected until the FMR01 bit is set to 0. 31.27.3.11 Area Where Rewrite Control Program is Executed Bits PM10 and PM13 in the PM1 register become 1 in CPU rewrite mode. Execute the rewrite program in internal RAM or an external area which can be used when both bits PM10 and PM13 are 1. Do not use the area (40000h to BFFFFh) where accessible space is expanded when the PM13 bit is 0 and 4-Mbyte mode is set. 31.27.3.12 Program and Erase Cycles and Execution Time Execution time of program, block erase and lock bit program command becomes longer as the number of programming and erasing increases. 31.27.3.13 Suspend of Auto-Erase Operation and Auto-Program Operation When program, block erase, and lock bit program commands are suspended, the blocks for those commands must be erased. Execute program and lock bit program commands again after erasing. Those commands are suspended by the following reset or interrupts: • Reset • NMI, watchdog timer, oscillation stop/re-oscillation detection, voltage monitor 1, and voltage monitor 2 interrupts. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 786 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group 31. Precautions 31.27.4 Standard Serial I/O Mode 31.27.4.1 User Boot Mode To use user boot mode after standard serial I/O mode, turn off the power when exiting standard serial I/O mode, and then turn on the power again (cold start). The MCU enters user boot mode under the right conditions. REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 787 of 791 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group Appendix 1. Package Dimensions Appendix 1. Package Dimensions JEITA Package Code P-QFP100-14x20-0.65 RENESAS Code PRQP0100JD-B Previous Code 100P6F-A MASS[Typ.] 1.8g HD *1 80 D 51 81 50 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. *2 HE E Reference Dimension in Millimeters Symbol ZE 100 31 1 ZD Index mark 30 F c A2 L e y *3 bp x Detail F D E A2 HD HE A A1 bp c e x y ZD ZE L Min Nom Max 19.8 20.0 20.2 13.8 14.0 14.2 2.8 22.5 22.8 23.1 16.5 16.8 17.1 3.05 0.1 0.2 0 0.25 0.3 0.4 0.13 0.15 0.2 10° 0° 0.65 0.13 0.10 0.575 0.825 0.4 0.6 0.8 A REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 788 of 791 A1 Under development Preliminary Specification This is a preliminary specification and is subject to change. M16C/65 Group Appendix 1. Package Dimensions JEITA Package Code P-LQFP100-14x14-0.50 RENESAS Code PLQP0100KB-A Previous Code 100P6Q-A / FP-100U / FP-100UV MASS[Typ.] 0.6g HD *1 D 75 51 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 76 50 bp b1 HE E Reference Dimension in Millimeters Symbol *2 c1 c Terminal cross section 1 Index mark ZD 25 F ZE 100 26 A2 A D E A2 HD HE A A1 bp b1 c c1 c A1 y e *3 bp L L1 Detail F x e x y ZD ZE L L1 Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0° 8° 0.5 0.08 0.08 1.0 1.0 0.35 0.5 0.65 1.0 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 789 of 791 M16C/65 Group [A] AD0 to AD7 ...................................... 656, 661 ADCMPCR ....................................... 655, 661 ADCON0 .......... 658, 667, 670, 672, 674, 676 ADCON1 .......... 660, 668, 671, 673, 675, 677 ADCON2 .......................................... 657, 661 ADIC ....................................................... 223 AIER ....................................................... 228 AIER2 ...................................................... 228 FMR1 ...................................................... 701 FMR2 .............................................. 131, 702 FMR3 ...................................................... 703 FMR6 ...................................................... 704 FRA0 ....................................................... 112 [I] ICTB2 ...................................................... 374 IDB0, IDB1 ............................................... 373 IFSR ........................................................ 227 IFSR2A .................................................... 226 IFSR3A .................................................... 225 IICIC ........................................................ 223 INT0IC to INT2IC ...................................... 224 INT3IC ..................................................... 224 INT6IC ..................................................... 224 INT7IC ..................................................... 224 INVC0 ...................................................... 369 INVC1 ...................................................... 371 [B] BCNIC ..................................................... 223 [C] CCRB1 .................................................... 632 CCRB2 .................................................... 632 CCTB1 .................................................... 631 CCTB2 .................................................... 631 CECC1 .................................................... 622 CECC2 .................................................... 623 CECC3 .................................................... 625 CECC4 .................................................... 627 CECFLG .................................................. 629 CISEL ...................................................... 630 CM0 ........................................................ 103 CM1 ........................................................ 105 CM2 ........................................................ 107 CPSRF ............................................ 288, 339 CRADRI1 ................................................. 633 CRADRI2 ................................................. 633 CRCD ...................................................... 689 CRCIN ..................................................... 689 CRCMR ................................................... 690 CRCSAR ................................................. 690 CSE ........................................................ 162 CSPR ...................................................... 257 CSR ........................................................ 161 [K] KUPIC ..................................................... 223 [N] NMIDF ............................................. 213, 231 [O] OFS1 ......................................... 63, 260, 705 ONSF ...................................................... 297 [P] P0 to P10 ................................................. 210 PCLKR ............ 109, 288, 339, 494, 557, 572 PCR ................................ 209, 230, 634, 654 PD0 to PD14 ............................................ 212 PDRF ...................................................... 376 PFCR ...................................................... 377 PLC0 ....................................................... 110 PM0 ........................................... 60, 102, 153 PM1 ......................................................... 154 PM2 ................................................. 111, 222 PMC0BC, PMC1BC .................................. 458 PMC0CON0, PMC1CON0 ......................... 445 PMC0CON1, PMC1CON1 ......................... 447 PMC0CON2, PMC1CON2 ......................... 449 PMC0CON3, PMC1CON3 ......................... 451 PMC0CPC ............................................... 460 PMC0CPD ............................................... 461 PMC0D0PMAX, PMC1D0PMAX ................. 457 PMC0D0PMIN, PMC1D0PMIN ................... 457 PMC0D1PMAX, PMC1D1PMAX ................. 457 PMC0D1PMIN, PMC1D1PMIN ................... 457 PMC0DAT0 to PMC0DAT5 ......................... 459 PMC0HDPMAX, PMC1HDPMAX ................ 456 [D] DA0, DA1 ................................................. 685 DACON ................................................... 685 DAR0 to DAR3 ......................................... 268 DBR ........................................................ 183 DM0CON to DM3CON .............................. 270 DM0IC to DM3IC ...................................... 223 DM0SL to DM3SL ..................................... 271 DTT ......................................................... 373 [E] EWC ....................................................... 163 EWR ....................................................... 164 [F] FMR0 .............................................. 130, 698 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 790 of 791 M16C/65 Group PMC0HDPMIN, PMC1HDPMIN .................. 456 PMC0INT, PMC1INT ................................. 455 PMC0RBIT ............................................... 458 PMC0STS, PMC1STS ............................... 452 PMC0TIM, PMC1TIM ................................ 458 PPWFS1, PPWFS2 ................................... 342 PRCR ........................................................ 55 PRG2C .................................................... 156 PUR0 ...................................................... 205 PUR1 ...................................................... 206 PUR2 ...................................................... 207 PUR3 ...................................................... 208 PWMCON0 .............................................. 432 PWMCON1 .............................................. 435 PWMFS ................................................... 291 PWMPRE0, PWMPRE1 ............................. 433 PWMREG0, PWMREG1 ............................ 434 [R] RMAD0 to RMAD3 .................................... 229 RSTFR ...................................................... 61 RTCCR1 .................................................. 410 RTCCSEC ............................................... 415 RTCCSR .................................................. 414 RTCHR .................................................... 408 RTCMIN .................................................. 407 RTCSEC .................................................. 406 RTCWK ................................................... 409 TA0 to TA4 ............................................... 294 TA1, TA2, TA4 ........................................... 368 TA11, TA21, TA41 ............................. 295, 368 TABSR ............................................. 296, 345 TACS0 to TACS2 ...................................... 290 TAOW ...................................................... 293 TAPOFS .................................................. 292 TB0IC to TB2IC ........................................ 223 TB0MR to TB5MR ..................................... 346 TB0 to TB5 ............................................... 340 TB11 to TB51 ........................................... 341 TB2 ......................................................... 368 TB2SC ..................................................... 375 TB3IC/U0BCNIC ....................................... 223 TB4IC/U1BCNIC ....................................... 223 TB5IC ...................................................... 223 TBCS0 to TBCS3 ...................................... 343 TBSR ....................................................... 345 TCKDIVC0 ....................................... 289, 344 TCR0 to TCR3 .......................................... 269 TPRC ...................................................... 377 TRGSR .................................................... 298 [U] U0BRG to U2BRG, U5BRG to U7BRG ........ 498 U0C0 to U2C0, U5C0 to U7C0 ................... 499 U0C1 to U2C1, U5C1 to U7C1 ................... 501 U0MR to U2MR, U5MR to U7MR ................ 498 U0RB to U2RB, U5RB to U7RB .................. 496 U0SMR2 to U2SMR2, U5SMR2 to U7SMR2 505 U0SMR3 to U2SMR3, U5SMR3 to U7SMR3 506 U0SMR4 to U2SMR4, U5SMR4 to U7SMR4 507 U0SMR to U2SMR, U5SMR to U7SMR ....... 504 U0TB to U2TB, U5TB to U7TB ................... 495 U5BCNIC/CEC1IC .................................... 223 U6BCNIC/RTCTIC .................................... 223 U7BCNIC/PMC0IC .................................... 223 UCLKSEL0 ............................................... 494 UCON ...................................................... 503 UDF ......................................................... 299 [S] S00 ......................................................... 573 S0D0 to S0D2 .......................................... 574 S0RIC to S2RIC ....................................... 223 S0TIC to S2TIC ........................................ 223 S10 ......................................................... 589 S11 ......................................................... 594 S1D0 ....................................................... 575 S20 ......................................................... 578 S2D0 ....................................................... 581 S34C2 ..................................................... 559 S3BRG, S4BRG ........................................ 559 S3C, S4C ................................................. 558 S3D0 ....................................................... 582 S3IC/INT4IC ............................................. 224 S3TRR, S4TRR ........................................ 557 S4D0 ....................................................... 587 S4IC/INT5IC ............................................. 224 S5RIC to S7RIC ....................................... 223 S5TIC/CEC2IC ......................................... 223 S6TIC/RTCCIC ......................................... 223 S7TIC/PMC1IC ......................................... 223 SAR0 to SAR3 .......................................... 268 SCLDAIC ................................................. 223 [V] VCR1 ......................................................... 78 VCR2 ......................................................... 79 VD1LS ....................................................... 80 VW0C ........................................................ 82 VW1C ........................................................ 83 VW2C ................................................ 85, 256 VWCE ....................................................... 80 [W] WDC ....................................................... 259 WDTR ..................................................... 258 WDTS ...................................................... 258 [T] TA0IC to TA4IC ......................................... 223 TA0MR to TA4MR ............................. 300, 322 REJ09B0484-0030 Rev.0.30 Sep 09, 2008 Page 791 of 791 Revision History Rev. 0.30 Date Sep 09, 2008 Page - M16C/65 Group Hardware Manual Description Summary First Edition issued. C-1 M16C/65 Group Hardware Manual Publication Date: Sep 09, 2008 Sep 09, 2008 Published by: Rev.0.30 Rev.0.30 Sales Strategic Planning Div. Renesas Technology Corp. 2-6-2, Otemachi, Chiyoda-ku, Tokyo 100-0004 © 2008. Renesas Technology Corp., All rights reserved. Printed in Japan. M16C/65 GROUP HARDWARE MANUAL 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan