R5F51104ADFM#10

Datasheet RX110 Group R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Renesas MCUs 32 MHz 32-bit RX MCUs, 50 DMIPS, up to 128 Kbytes of flash memory, up to 5 comms channels, 12-bit A/D, RTC Features ■ 32-bit RX CPU core  32 MHz maximum operating frequency Capable of 50 DMIPS when operating at 32 MHz  Accumulator handles 64-bit results (for a single instruction) from 32-bit × 32-bit operations  Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycle)  Fast interrupt  CISC Harvard architecture with five-stage pipeline  Variable-length instruction format, ultra-compact code  On-chip debugging circuit ■ Low power consumption functions  Operation from a single 1.8 to 3.6 V supply  Three low power modes  Supply current High-speed operating mode: 0.1 mA/MHz Software standby mode: 0.35 μA  Recovery time from software standby mode: 4.8 μs ■ On-chip flash memory for code, no wait states  Operation at 32 MHz, read cycle of 31.25 ns  No wait states for reading at full CPU speed  8 to 128 Kbyte capacities  Programmable at 1.8 V  For instructions and operands ■ On-chip SRAM, no wait states  8 to 16 Kbyte capacities ■ Data transfer controller (DTC)  Four transfer modes  Transfer can be set for each interrupt source. ■ Reset and power supply voltage management  Six types including the power-on reset (POR)  Low voltage detection (LVD) with voltage settings ■ Clock functions  External clock input frequency: Up to 20 MHz  Main clock oscillator frequency: 1 to 20 MHz  Sub-clock oscillator frequency: 32.768 kHz  Low-speed on-chip oscillator: 4 MHz  High-speed on-chip oscillator: 32 MHz±1% (20 to 85°C)  IWDT-dedicated on-chip oscillator: 15 kHz  Generate a dedicated 32.768-kHz clock for the RTC  On-chip clock frequency accuracy measurement circuit (CAC) ■ Real-time clock (RTC)  30-second, leap year, and error adjustment functions  Calendar count mode or binary count mode selectable  Capable initiating exit from software standby mode R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 PLQP0064KB-A 10 × 10 mm, 0.5 mm pitch PLQP0064GA-A 14 × 14 mm, 0.8 mm pitch PLQP0048KB-A 7 × 7 mm, 0.5 mm pitch PWQN0048KB-A 7 × 7 mm, 0.5 mm pitch PWQN0040KC-A 6 × 6 mm, 0.5 mm pitch PWLG0064KA-A 5 × 5 mm, 0.5 mm pitch PWLG0036KA-A 4 × 4 mm, 0.5 mm pitch ■ Independent watchdog timer (WDT)  15-kHz on-chip oscillator produces a dedicated clock signal to drive IWDT operation. ■ On-chip functions for IEC 60730 compliance  Clock frequency accuracy measurement circuit, IWDT, functions to assist in RAM testing, etc. ■ Up to five channels for communication  SCI: Asynchronous mode, clock synchronous mode, smart card interface (up to seven channels)  I2C bus interface: Transfer at up to 400 kbps, capable of SMBus operation (one channel)  RSPI: Up to 16 Mbps (one channel) ■ Up to 6 extended-function timers  16-bit MTU: Input capture/output compare, phase counting mode (four channels)  16-bit CMT (two channels) ■ 12-bit A/D converter  Up to 14 channels  1.0 μs minimum conversion speed  Double trigger (data duplication) function for motor control ■ Temperature sensor ■ General I/O ports  5-V tolerant, open drain, input pull-up ■ Multi-function pin controller (MPC)  Multiple I/O pins can be selected for peripheral functions. ■ Unique ID  32-byte ID code for the MCU ■ Operating temperature range  40 to 85C  40 to 105°C Page 1 of 108 RX110 Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different packages. Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different Packages. Table 1.1 Outline of Specifications (1/3) Classification Module/Function Description CPU CPU             Memory Maximum operating frequency: 32 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per one clock cycle Address space: 4-Gbyte linear Register set General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit register Basic instructions: 73 DSP instructions: 9 Addressing modes: 10 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32-bit × 32-bit → 64-bit On-chip divider: 32-bit ÷ 32-bit → 32 bits Barrel shifter: 32 bits ROM  Capacity: 8 K /16 K /32 K /64 K /96 K /128 Kbytes  32 MHz, no-wait memory access  Programming/erasing method: Serial programming (asynchronous serial communication), self-programming RAM  Capacity: 8 K /10 K /16 Kbytes  32 MHz, no-wait memory access MCU operating mode Single-chip mode Clock  Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator, and IWDT-dedicated on-chip oscillator  Oscillation stop detection: Available  Clock frequency accuracy measurement circuit (CAC)  Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock (FCLK) The CPU and system sections such as other bus masters run in synchronization with the system clock (ICLK): 32 MHz (at max.) Peripheral modules run in synchronization with the PCLK: 32 MHz (at max.) The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.)  The ICLK frequency can only be set to FCLK, PCLKB, or PCLKD multiplied by n (n: 1, 2, 4, 8, 16, 32, 64). Clock generation circuit Resets RES# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and software reset Voltage detection Voltage detection circuit (LVDAa)  When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt is generated. Voltage detection circuit 1 is capable of selecting the detection voltage from 10 levels Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels Low power consumption Low power consumption functions  Module stop function  Three low power consumption modes Sleep mode, deep sleep mode, and software standby mode Function for lower operating power consumption  Operating power control modes High-speed operating mode, middle-speed operating mode, and low-speed operating mode Interrupt Interrupt controller (ICUb)  Interrupt vectors: 65  External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)  Non-maskable interrupts: 4 (NMI pin, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt, and IWDT interrupt)  16 levels specifiable for the order of priority DMA Data transfer controller (DTCa)  Transfer modes: Normal transfer, repeat transfer, and block transfer  Activation sources: Interrupts  Chain transfer function R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 2 of 108 RX110 Group Table 1.1 1. Overview Outline of Specifications (2/3) Classification Module/Function Description I/O ports General I/O ports 64-pin /48-pin /40-pin /36-pin  I/O: 50/34/28/24  Input: 2/2/1/1  Pull-up resistors: 42/28/23/20  Open-drain outputs: 38/28/23/20  5-V tolerance: 4/4/4/4 Multi-function pin controller (MPC) Capable of selecting the input/output function from multiple pins Timers Multi-function timer pulse unit 2 (MTU2b)  (16 bits × 4 channels) × 1 unit  Time bases for the four 16-bit timer channels can be provided via up to 8 pulse-input/output lines and three pulse-input lines  Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4, PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than channel 5, for which only four signals are available.  Input capture function  13 output compare/input capture registers  Pulse output mode  Phase counting mode  Generation of triggers for A/D converter conversion Compare match timer (CMT)  (16 bits × 2 channels) × 1 unit  Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512) Independent watchdog timer (IWDTa)  14 bits × 1 channel  Count clock: Dedicated low-speed on-chip oscillator for the IWDT Frequency divided by 1, 16, 32, 64, 128, or 256 Realtime clock (RTCA)  Clock source: Sub-clock  Calendar count mode or binary count mode selectable  Interrupts: Alarm interrupt, periodic interrupt, and carry interrupt Serial communications interfaces (SCIe, SCIf)           I2C bus interface (RIIC)  1 channel  Communications formats: I2C bus format/SMBus format  Master mode or slave mode selectable  Supports fast mode Serial peripheral interface (RSPI)  1 channel  Transfer facility Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPI clock (RSPCK) signals enables serial transfer through SPI operation (four lines) or clocksynchronous operation (three lines)  Capable of handling serial transfer as a master or slave  Data formats  Choice of LSB first or MSB first transfer The number of bits in each transfer can be changed to 8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24, or 32 bits. 128-bit buffers for transmission and reception Up to four frames can be transmitted or received in a single transfer operation (with each frame having up to 32 bits)  Double buffers for both transmission and reception Communication functions 3 channels (channel 1, 5: SCIe, channel 12: SCIf) Serial communications modes: Asynchronous, clock synchronous, and smart card interface On-chip baud rate generator allows selection of the desired bit rate Choice of LSB first or MSB first transfer Average transfer rate clock can be input from MTU2 timers Simple I2C Simple SPI Master/slave mode supported (SCIf only) Start frame and information frame are included (SCIf only) Start-bit detection in asynchronous mode: Low level or falling edge is selectable (SCIe/SCIf) 12-bit A/D converter (S12ADb)     Temperature sensor (TEMPSA)  1 channel  The voltage of the temperature is converted into a digital value by the 12-bit A/D converter. CRC calculator (CRC)  CRC code generation for arbitrary amounts of data in 8-bit units  Select any of three generating polynomials: X8 + X2 + X + 1, X16 + X15 + X2 + 1, or X16 + X12 + X5 + 1  Generation of CRC codes for use with LSB first or MSB first communications is selectable. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 1 unit (1 unit × 14 channels) 12-bit resolution Minimum conversion time: 1.0 µs per channel when the ADCLK is operating at 32 MHz Operating modes Scan mode (single scan mode, continuous scan mode, and group scan mode)  Double trigger mode (duplication of A/D conversion data)  A/D conversion start conditions A software trigger, a trigger from a timer (MTU), or an external trigger signal Page 3 of 108 RX110 Group Table 1.1 Classification 1. Overview Outline of Specifications (3/3) Module/Function Description Data operation circuit (DOC) Comparison, addition, and subtraction of 16-bit data Unique ID 32-byte ID code for the MCU Power supply voltages/Operating frequencies VCC = 1.8 to 2.4 V: 8 MHz, VCC = 2.4 to 2.7 V: 16 MHz, VCC = 2.7 to 3.6 V: 32 MHz Supply current 3.2 mA at 32 MHz (typ.) Operating temperatures D version: 40 to +85°C, G version: 40 to +105°C Packages 64-pin LFQFP (PLQP0064KB-A) 10 × 10 mm, 0.5 mm pitch 64-pin LQFP (PLQP0064GA-A) 14 × 14 mm, 0.8 mm pitch 64-pin WFLGA (PWLG0064KA-A) 5 × 5 mm, 0.5 mm pitch 48-pin LFQFP (PLQP0048KB-A) 7 × 7 mm, 0.5 mm pitch 48-pin HWQFN (PWQN0048KB-A) 7 × 7 mm, 0.5 mm pitch 40-pin HWQFN (PWQN0040KC-A) 6 × 6 mm, 0.5 mm pitch 36-pin WFLGA (PWLG0036KA-A) 4 × 4 mm, 0.5 mm pitch On-chip debugging system E1 emulator (FINE interface) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 4 of 108 RX110 Group Table 1.2 1. Overview Comparison of Functions for Different Packages RX110 Group Module/Functions Interrupts External interrupts DMA Data transfer controller Timers Multi-function timer pulse unit 2 64 Pins 48 Pins Supported 4 channels (MTU0 to MTU2, MTU5) 2 channels × 1 unit Realtime clock Supported Independent watchdog timer Not supported Supported Serial communications interfaces [simple I2C, simple SPI] 2 channels (SCI1, SCI5) Serial communications interface [simple I2C, simple SPI] 1 channel (SCI12) I2C bus interface Serial peripheral interface 12-bit A/D converter (including high-precision channels) 1 channel 1 channel 14 channels (6 channels) 1 channel 1 channel (SSLA1 and SSLA3 are not supported) (SSLA1 to SSLA3 are not supported) 10 channels (4 channels) 8 channels (3 channels) Temperature sensor Supported CRC calculator Supported Packages R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 36 Pins NMI, IRQ0 to IRQ7 Compare match timer Communication functions 40 Pins 64-pin LFQFP 64-pin LQFP 64-pin WFLGA 48-pin LFQFP 48-pin HWQFN 40-pin HWQFN 7 channels (2 channels) 36-pin WFLGA Page 5 of 108 RX110 Group 1.2 1. Overview List of Products Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part no., memory capacity, and package type. Table 1.3 List of Products (1/2) Group Part No. Orderable Part No. Package RX110 R5F51105AGFM R5F51105AGFM#30 PLQP0064KB-A R5F51105AGFK R5F51105AGFK#30 PLQP0064GA-A R5F51105AGFL R5F51105AGFL#30 PLQP0048KB-A R5F51105AGNE R5F51105AGNE#U0 PWQN0048KB-A R5F51104AGFM R5F51104AGFM#30 PLQP0064KB-A R5F51104AGFK R5F51104AGFK#30 PLQP0064GA-A R5F51104AGFL R5F51104AGFL#30 PLQP0048KB-A R5F51104AGNE R5F51104AGNE#U0 PWQN0048KB-A R5F51103AGFM R5F51103AGFM#30 PLQP0064KB-A R5F51103AGFK R5F51103AGFK#30 PLQP0064GA-A R5F51103AGFL R5F51103AGFL#30 PLQP0048KB-A R5F51103AGNE R5F51103AGNE#U0 PWQN0048KB-A R5F51103AGNF R5F51103AGNF#U0 PWQN0040KC-A R5F51101AGFM R5F51101AGFM#30 PLQP0064KB-A R5F51101AGFK R5F51101AGFK#30 PLQP0064GA-A R5F51101AGFL R5F51101AGFL#30 PLQP0048KB-A R5F51101AGNE R5F51101AGNE#U0 PWQN0048KB-A R5F51101AGNF R5F51101AGNF#U0 PWQN0040KC-A R5F5110JAGFM R5F5110JAGFM#30 PLQP0064KB-A R5F5110JAGFK R5F5110JAGFK#30 PLQP0064GA-A R5F5110JAGFL R5F5110JAGFL#30 PLQP0048KB-A R5F5110JAGNE R5F5110JAGNE#U0 PWQN0048KB-A R5F5110JAGNF R5F5110JAGNF#U0 PWQN0040KC-A R5F5110HAGNF R5F5110HAGNF#U0 PWQN0040KC-A R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 ROM Capacity RAM Capacity Maximum Operating Frequency Operating Temperature 32 MHz 40 to +105°C 128 Kbytes 16 Kbytes 96 Kbytes 64 Kbytes 10 Kbytes 32 Kbytes 16 Kbytes 8 Kbytes 8 Kbytes Page 6 of 108 RX110 Group Table 1.3 1. Overview List of Products (2/2) Group Part No. Orderable Part No. Package RX110 R5F51105ADFM R5F51105ADFM#30 PLQP0064KB-A R5F51105ADFK R5F51105ADFK#30 PLQP0064GA-A R5F51105ADLF R5F51105ADLF#U0 PWLG0064KA-A R5F51105ADFL R5F51105ADFL#30 PLQP0048KB-A Note: R5F51105ADNE R5F51105ADNE#U0 PWQN0048KB-A R5F51104ADFM R5F51104ADFM#30 PLQP0064KB-A R5F51104ADFK R5F51104ADFK#30 PLQP0064GA-A R5F51104ADLF R5F51104ADLF#U0 PWLG0064KA-A R5F51104ADFL R5F51104ADFL#30 PLQP0048KB-A R5F51104ADNE R5F51104ADNE#U0 PWQN0048KB-A R5F51103ADFM R5F51103ADFM#30 PLQP0064KB-A R5F51103ADFK R5F51103ADFK#30 PLQP0064GA-A R5F51103ADLF R5F51103ADLF#U0 PWLG0064KA-A R5F51103ADFL R5F51103ADFL#30 PLQP0048KB-A R5F51103ADNE R5F51103ADNE#U0 PWQN0048KB-A R5F51103ADLM R5F51103ADLM#U0 PWLG0036KA-A R5F51103ADNF R5F51103ADNF#U0 PWQN0040KC-A R5F51101ADFM R5F51101ADFM#30 PLQP0064KB-A R5F51101ADFK R5F51101ADFK#30 PLQP0064GA-A R5F51101ADLF R5F51101ADLF#U0 PWLG0064KA-A R5F51101ADFL R5F51101ADFL#30 PLQP0048KB-A R5F51101ADNE R5F51101ADNE#U0 PWQN0048KB-A R5F51101ADLM R5F51101ADLM#U0 PWLG0036KA-A R5F51101ADNF R5F51101ADNF#U0 PWQN0040KC-A R5F5110JADFM R5F5110JADFM#30 PLQP0064KB-A R5F5110JADFK R5F5110JADFK#30 PLQP0064GA-A R5F5110JADLF R5F5110JADLF#U0 PWLG0064KA-A R5F5110JADFL R5F5110JADFL#30 PLQP0048KB-A R5F5110JADNE R5F5110JADNE#U0 PWQN0048KB-A R5F5110JADLM R5F5110JADLM#U0 PWLG0036KA-A R5F5110JADNF R5F5110JADNF#U0 PWQN0040KC-A R5F5110HADLM R5F5110HADLM#U0 PWLG0036KA-A R5F5110HADNF R5F5110HADNF#U0 PWQN0040KC-A ROM Capacity RAM Capacity Maximum Operating Frequency Operating Temperature 32MHz 40 to +85°C 128 Kbytes 16 Kbytes 96 Kbytes 64 Kbytes 10 Kbytes 32 Kbytes 16 Kbytes 8 Kbytes 8 Kbytes Orderable part numbers are current as of when this manual was published. Please make sure to refer to the relevant product page on the Renesas website for the latest part numbers. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 7 of 108 RX110 Group 1. Overview R 5 F 5 1 1 0 5 A D F M #3 0 Production identification code Packing, Terminal material (Pb-free) #3: Tray/Sn (Tin) only #U: Tray/SnCu and others Package type, number of pins, and pin pitch FM: LFQFP/64/0.50 FK: LQFP/64/0.80 LF: WFLGA/64/0.50 FL: LFQFP/48/0.50 NE: HWQFN/48/0.50 NF: HWQFN/40/0.50 LM: WFLGA/36/0.50 D: Operating temperature (-40°C to +85°C) G: Operating temperature (-40°C to +105°C) ROM and RAM capacity 5: 128 Kbytes/16 Kbytes 4: 96 Kbytes/16 Kbytes 3: 64 Kbytes/10 Kbytes 1: 32 Kbytes/10 Kbytes J: 16 Kbytes/8 Kbytes H: 8 Kbytes/8 Kbytes Group name 10: RX110 Group 11: RX111 Group Series name RX100 Series Type of memory F: Flash memory version Renesas MCU Renesas semiconductor product Figure 1.1 How to Read the Product Part No., Memory Capacity, and Package Type R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 8 of 108 RX110 Group 1.3 1. Overview Block Diagram Figure 1.2 shows a block diagram. IWDTa CRC SCIe × 2 channels SCIf × 1 channel Internal main bus 2 DTCa RIIC × 1 channel MTU2b × 4 channels RX CPU Clock generation circuit Port 0 Port 1 Port 2 CMT × 2 channels (unit 0) Port 3 RTCA Port 4 12-bit A/D converter × 14 channels Port 5 Temperature sensor Port A DOC Port B CAC Port C Internal main bus 1 RAM Operand bus Instruction bus ROM Internal peripheral buses 1, 2, 4 to 6 ICUb RSPI × 1 channel Port E Port H Port J ICUb: DTCa: IWDTa: CRC: SCIe/SCIf: RSPI: Figure 1.2 Interrupt controller Data transfer controller Independent watchdog timer CRC (cyclic redundancy check) calculator Serial communications interface Serial peripheral interface RIIC: MTU2b: CMT: RTCA: DOC: CAC: I2C bus interface Multi-function timer pulse unit 2 Compare match timer Realtime clock Data operation circuit Clock frequency accuracy measurement circuit Block Diagram R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 9 of 108 RX110 Group 1.4 1. Overview Pin Functions Table 1.4 lists the pin functions. Table 1.4 Pin Functions (1/3) Classifications Pin Name I/O Description Power supply VCC Input Power supply pin. Connect it to the system power supply. VCL — Connect this pin to the VSS pin via the 4.7 μF smoothing capacitor used to stabilize the internal power supply. Place the capacitor close to the pin. VSS Input Ground pin. Connect it to the system power supply (0 V). AVCC0 Input Analog voltage supply pin for the 12-bit A/D converter. Connect this pin to VCC when not using the 12-bit A/D converter. AVSS0 Input Analog ground pin for the 12-bit A/D converter. Connect this pin to VSS when not using the 12-bit A/D converter. VREFH0 Input Analog reference voltage supply pin for the 12-bit A/D converter. Connect this pin to VCC when not using the 12-bit A/D converter. VREFL0 Input Analog reference ground pin for the 12-bit A/D converter. Connect this pin to VSS when not using the 12-bit A/D converter. XTAL Output/ Pins for connecting a crystal resonator. An external clock can be input Input *1 through the XTAL pin. EXTAL Input Analog power supply Clock XCIN Input XCOUT Output CLKOUT Output Clock output pin. Operating mode control MD Input Pin for setting the operating mode. The signal levels on this pin must not be changed during operation. System control RES# Input Reset pin. This LSI enters the reset state when this signal goes low. CAC CACREF Input Input pin for the clock frequency accuracy measurement circuit. On-chip emulator FINED I/O FINE interface pin. LVD CMPA2 Input Detection target voltage pin for voltage detection 2. Interrupts NMI Input Non-maskable interrupt request pin. IRQ0 to IRQ7 Input/output pins for the sub-clock oscillator. Connect a crystal resonator between XCIN and XCOUT. Input Interrupt request pins. Multi-function MTIOC0A, MTIOC0B timer pulse unit 2 MTIOC0C, MTIOC0D I/O The TGRA0 to TGRD0 input capture input/output compare output/PWM output pins. MTIOC1A, MTIOC1B I/O The TGRA1 and TGRB1 input capture input/output compare output/PWM output pins. MTIOC2A, MTIOC2B I/O The TGRA2 and TGRB2 input capture input/output compare output/PWM output pins. MTIC5U, MTIC5V, MTIC5W Input The TGRU5, TGRV5, and TGRW5 input capture input/external pulse input pins. MTCLKA, MTCLKB, MTCLKC, MTCLKD Input Input pins for the external clock. RTCOUT Output Output pin for the 1-Hz/64-Hz clock. Realtime clock Serial communications interface (SCIe)  Asynchronous mode/clock synchronous mode SCK1, SCK5 I/O Input/output pins for the clock. RXD1, RXD5 Input Input pins for receiving data. TXD1, TXD5 Output Output pins for transmitting data. CTS1#, CTS5# Input Input pins for controlling the start of transmission and reception. RTS1#, RTS5# Output Output pins for controlling the start of transmission and reception. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 10 of 108 RX110 Group Table 1.4 1. Overview Pin Functions (2/3) Classifications Pin Name I/O Description Serial communications interface (SCIe)  Simple SSCL1, SSCL5 I/O Input/output pins for the I2C clock. SSDA1, SSDA5 I/O Input/output pins for the I2C data. I2C mode  Simple SPI mode Serial communications interface (SCIf) SCK1, SCK5 I/O Input/output pins for the clock. SMISO1, SMISO5 I/O Input/output pins for slave transmit data. SMOSI1, SMOSI5 I/O Input/output pins for master transmit data. SS1#, SS5# Input Chip-select input pins.  Asynchronous mode/clock synchronous mode SCK12 I/O Input/output pin for the clock. RXD12 Input Input pin for receiving data. TXD12 Output Output pin for transmitting data. CTS12# Input Input pin for controlling the start of transmission and reception. RTS12# Output Output pin for controlling the start of transmission and reception. SSCL12 I/O Input/output pin for the I2C clock. SSDA12 I/O Input/output pin for the I2C data.  Simple I2C mode  Simple SPI mode SCK12 I/O Input/output pin for the clock. SMISO12 I/O Input/output pin for slave transmit data. SMOSI12 I/O Input/output pin for master transmit data. SS12# Input Chip-select input pin. Input Input pin for data reception by SCIf.  Extended serial mode RXDX12 I2C bus interface Serial peripheral interface 12-bit A/D converter I/O ports TXDX12 Output Output pin for data transmission by SCIf. SIOX12 I/O Input/output pin for data reception or transmission by SCIf. SCL0 I/O Input/output pin for I2C bus interface clocks. Bus can be directly driven by the N-channel open drain output. SDA0 I/O Input/output pin for I2C bus interface data. Bus can be directly driven by the N-channel open drain output. RSPCKA I/O Input/output pin for the RSPI clock. MOSIA I/O Input/output pin for transmitting data from the RSPI master. MISOA I/O Input/output pin for transmitting data from the RSPI slave. SSLA0 I/O Input/output pin to select the slave for the RSPI. SSLA1 to SSLA3 Output Output pins to select the slave for the RSPI. AN000 to AN004, AN006, AN008 to AN015 Input Input pins for the analog signals to be processed by the A/D converter. ADTRG0# Input Input pin for the external trigger signals that start the A/D conversion. P03, P05 I/O 2-bit input/output pins. P14 to P17 I/O 4-bit input/output pins. P26, P27 I/O 2-bit input/output pins. P30 to P32, P35 I/O 4-bit input/output pins (P35 input pin). P40 to P44, P46 I/O 6-bit input/output pins. P54, P55 I/O 2-bit input/output pins. PA0, PA1, PA3, PA4, PA6 I/O 5-bit input/output pins. PB0, PB1, PB3, PB5 to PB7 I/O 6-bit input/output pins. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 11 of 108 RX110 Group Table 1.4 1. Overview Pin Functions (3/3) Classifications Pin Name I/O Description I/O ports PC0 to PC7 I/O 8-bit input/output pins. PE0 to PE7 I/O 8-bit input/output pins. PH0 to PH3 I/O 4-bit input/output pins. PH7 Input 1-bit input pin. PJ6, PJ7 I/O 2-bit input/output pins. Note 1. For external clock input. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 12 of 108 RX110 Group 1.5 1. Overview Pin Assignments VSS PB0 VCC PB1 PB3 PB5 PB6/PC0 PB7/PC1 39 38 37 36 35 34 33 PA3 40 PA1 43 PA4 PA0 44 PA6 PE5 45 41 PE4 46 42 PE3 47 PE2 49 32 PC2 PE1 50 31 PC3 PE0 51 30 PC4 PE7 52 29 PC5 PE6 53 28 PC6 P46 54 27 PC7 P44 55 26 P54 P43 56 25 P55 P42 57 24 PH0 P41 58 23 PH1 PJ7/VREFL0 59 22 PH2 P40 60 21 PH3 PJ6/VREFH0 61 20 P14 AVSS0 62 19 P15 AVCC0 63 18 P16 P05 64 17 P17 Note: Figure 1.3 48 Figure 1.3 to Figure 1.7 show the pin assignments. Table 1.5 to Table 1.9 show the lists of pins and pin functions. 12 13 14 15 16 VCL VSS VCC P32 8 XCOUT EXTAL 7 RES# 11 6 MD XTAL 5 P31 9 4 P30 10 3 P26 P35/NMI 2 P27 PH7/XCIN 1 P03 RX110 Group PLQP0064KB-A PLQP0064GA-A (64-pin LFQFP/LQFP) (Top view) This figure indicates the power supply pins and I/O ports. For the pin configuration, see the table “List of Pins and Pin Functions (64-Pin LFQFP/LQFP)”. Pin Assignments of the 64-Pin LFQFP/LQFP R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 13 of 108 RX110 Group 1. Overview RX110 Group PWLG0064KA-A (64-pin WFLGA) (Upper perspective view) A B C D E F G H 8 PE3 PE4 PA0 VSS VCC PB5 PB6 PB7 8 7 PE2 PE1 PA1 PA3 PB0 PC4 PC3 PC2 7 6 P46 PE6 PE5 PA4 PB1 PC7 PC5 PH0 6 5 P43 P44 PE7 PA6 PB3 P54 PC6 PH1 5 4 PJ7/ VREFL0 P42 P41 PE0 P55 P14 P15 PH2 4 3 PJ6/ VREFH0 P40 P27 P26 P31 P35 P16 PH3 3 2 AVCC0 P03 P05 P30 MD P32 P17 VCC 2 1 AVSS0 XCOUT PH7/ XCIN RES# XTAL EXTAL VCL VSS 1 A B C D E F G H Note: Note: Figure 1.4 This figure indicates the power supply pins and I/O port pins. For the pin configuration, see the table “List of Pins and Pin Functions (64-Pin WFLGA)”. For the position of A1 pin in the package, see “Package Dimensions”. Pin Assignments of the 64-Pin WFLGA R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 14 of 108 PA4 VSS PB0/PC0 VCC PB1/PC1 PB3/PC2 PB5/PC3 30 29 28 27 26 25 PA3 24 PC4 38 23 PC5 PE0 39 22 PC6 PE7 40 21 PC7 P46 41 20 PH0 P42 42 19 PH1 P41 43 18 PH2 PJ7/VREFL0 44 17 PH3 P40 45 16 P14 PJ6/VREFH0 46 15 P15 AVSS0 47 14 P16 AVCC0 48 13 P17 RX110 Group PLQP0048KB-A (48-pin LFQFP) VSS VCC 26 PB3/PC2 25 PB5/PC3 12 10 VCL 27 PB1/PC1 11 9 EXTAL 7 P35/NMI 30 VSS 28 VCC 6 PH7/XCIN 31 PA6 8 5 XCOUT 32 PA4 XTAL 4 RES# 33 PA3 29 PB0/PC0 3 MD 34 PA1 2 P26 35 PE4 1 P27 36 PE3 (Top view) PE2 37 24 PC4 PE1 38 23 PC5 PE0 39 22 PC6 RX110 Group PWQN0048KB-A (48-pin HWQFN) P42 42 P41 43 PJ7/VREFL0 44 21 PC7 20 PH0 19 PH1 18 PH2 17 PH3 (Top view) P40 45 16 P14 VCC 12 VSS 11 VCL 10 EXTAL 9 7 XTAL 8 P35/NMI PH7/XCIN 6 XCOUT 5 13 P17 RES# 4 14 P16 AVCC0 48 MD 3 15 P15 AVSS0 47 P26 2 PJ6/VREFH0 46 P27 1 Figure 1.5 PA6 PA1 33 37 PE1 P46 41 Note: 31 PE4 34 PE2 PE7 40 Note: 32 PE3 35 1. Overview 36 RX110 Group This figure indicates the power supply pins and I/O port pins. For the pin configuration, see the table “List of Pins and Pin Functions (48-Pin LFQFP/HWQFN)”. It is recommended that the exposed die pad of HWQFN should be connected to VSS . Pin Assignments of the 48-Pin LFQFP/HWQFN R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 15 of 108 PA4 VSS PB0 VCC PB3 24 23 22 21 PA3 19 PH0 18 PH1 RX110 Group PWQN0040KC-A (40-pin HWQFN) (Top view) P42 35 P41 36 PJ7/VREFL0 37 PJ6/VREFH0 38 Figure 1.6 PA6 PA1 27 20 PC4 PE1 32 P46 34 Note: 25 PE4 28 PE2 31 PE0 33 Note: 26 PE3 29 1. Overview 30 RX110 Group 17 PH2 16 PH3 15 P14 14 P15 13 P16 2 3 4 5 6 7 8 9 MD RES# P35/NMI XTAL EXTAL VCL VSS VCC 10 1 11 P32 P26 12 P17 AVCC0 40 P27 AVSS0 39 This figure indicates the power supply pins and I/O port pins. For the pin configuration, see the table “List of Pins and Pin Functions (40-Pin HWQFN)”. It is recommended that the exposed die pad of HWQFN should be connected to VSS. Pin Assignments of the 40-Pin HWQFN R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 16 of 108 RX110 Group 1. Overview RX110 Group PWLG0036KA-A (36-pin WFLGA) (Upper perspective view) 6 PE2 PA3 VSS PB0 VCC PH0 5 P41 PE1 PA4 PB3 PC4 PH1 4 P42 PE0 PE4 PA6 P15 PH2 3 PJ6/ VREFH0 PJ7/ VREFL0 PE3 P14 P16 PH3 2 AVCC0 P27 MD P35 P17 VCC 1 AVSS0 RES# XTAL EXTAL VCL VSS A B C D E F Note: Note: Figure 1.7 This figure indicates the power supply pins and I/O port pins. For the pin configuration, see the table “List of Pins and Pin Functions (36-Pin WFLGA)”. For the position of A1 pin in the package, see “Package Dimensions”. Pin Assignments of the 36-Pin WFLGA R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 17 of 108 RX110 Group Table 1.5 Pin No. 1. Overview List of Pins and Pin Functions (64-Pin LFQFP/LQFP) (1/2) Power Supply, Clock, System Control I/O Port Timers (MTU, RTC) Communication (SCIe, SCIf, RSPI, RIIC) Others 1 P03 2 P27 MTIOC2B SCK1/SCK12 3 P26 MTIOC2A TXD1/SMOSI1/SSDA1 4 P30 RXD1/SMISO1/SSCL1 IRQ0 5 P31 CTS1#/RTS1#/SS1# IRQ1 6 MD 7 RES# 8 XCOUT 9 XCIN 10 11 IRQ3/CMPA2/ CACREF/ADTRG0# FINED PH7 P35 NMI XTAL 12 EXTAL 13 VCL 14 VSS 15 VCC 16 P32 MTIOC0C/RTCOUT IRQ2 17 P17 MTIOC0C SCK1/MISOA/SDA0/RXD12/RXDX12/ SMISO12/SSCL12 IRQ7 18 P16 RTCOUT TXD1/SMOSI1/SSDA1/MOSIA/SCL0 IRQ6/ADTRG0# 19 P15 MTIOC0B/MTCLKB RXD1/SMISO1/SSCL1/RSPCKA IRQ5/CLKOUT 20 P14 MTIOC0A/MTCLKA CTS1#/RTS1#/SS1#/SSLA0/TXD12/ TXDX12/SIOX12/SMOSI12/SSDA12 IRQ4 21 PH3 MTIOC1A 22 PH2 IRQ1 23 PH1 IRQ0 24 PH0 25 P55 26 P54 MTIOC1B CACREF 27 PC7 MTCLKB TXD1/SMOSI1/SSDA1/MISOA 28 PC6 MTCLKA RXD1/SMISO1/SSCL1/MOSIA SCK1/RSPCKA 29 PC5 MTCLKD 30 PC4 MTCLKC 31 PC3 TXD5/SMOSI5/SSDA5 32 PC2 RXD5/SMISO5/SSCL5/SSLA3 33 PB7/PC1 34 PB6/PC0 SCK5/SSLA0 CACREF IRQ2/CLKOUT 35 PB5 MTIOC2A/MTIOC1B 36 PB3 MTIOC0A PB1 MTIOC0C PB0 MTIC5W/MTIOC0C/ RTCOUT SCL0/RSPCKA IRQ2/ADTRG0# PA6 MTIC5V/MTCLKB/MTIOC2A CTS5#/RTS5#/SS5#/SDA0/MOSIA IRQ3 37 38 39 40 41 IRQ4 VCC VSS 42 PA4 MTIC5U/MTCLKA/MTIOC2B TXD5/SMOSI5/SSDA5/SSLA0 IRQ5 43 PA3 MTIOC0D/MTCLKD/ MTIOC1B RXD5/SMISO5/SSCL5/MISOA IRQ6 44 PA1 MTIOC0B/MTCLKC/ RTCOUT SCK5/SSLA2 R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 18 of 108 RX110 Group Table 1.5 Pin No. 1. Overview List of Pins and Pin Functions (64-Pin LFQFP/LQFP) (2/2) Power Supply, Clock, System Control I/O Port Timers (MTU, RTC) 45 PA0 46 PE5 MTIOC2B 47 PE4 MTIOC1A MTIOC0A/MTIOC1B Communication (SCIe, SCIf, RSPI, RIIC) Others SSLA1 CACREF IRQ5/AN013 MOSIA IRQ4/AN012 48 PE3 CTS12#/RTS12#/SS12#/RSPCKA IRQ3/AN011 49 PE2 RXD12/RXDX12/SMISO12/SSCL12 IRQ7/AN010 50 PE1 TXD12/TXDX12/SIOX12/SMOSI12/ SSDA12 IRQ1/AN009 51 PE0 52 PE7 IRQ7/AN015 53 PE6 IRQ6/AN014 54 P46*1 AN006 55 P44*1 AN004 56 P43*1 AN003 57 P42*1 AN002 58 P41*1 AN001 59 VREFL0 P40*1 PJ6*1 61 VREFH0 AVSS0 63 AVCC0 64 SCK12 IRQ0/AN008 PJ7*1 60 62 MTIOC2A AN000 P05 Note 1. The power source of the I/O buffer for these pins is AVCC0. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 19 of 108 RX110 Group Table 1.6 1. Overview List of Pins and Pin Functions (64-Pin WFLGA) (1/2) Pin No. Power Supply, Clock, System Control A1 AVSS0 A2 AVCC0 A3 VREFH0 PJ6*1 A4 VREFL0 PJ7*1 I/O Port Timers (MTU, RTC) Communication (SCIe, SCIf, RSPI, RIIC) Others A5 P43*1 AN003 A6 P46*1 AN006 A7 PE2 A8 PE3 B1 MTIOC0A/MTIOC1B RXD12/RXDX12/SMISO12/SSCL12 IRQ7/AN010 CTS12#/RTS12#/SS12#/RSPCKA IRQ3/AN011 XCOUT B2 P03 B3 P40*1 AN000 B4 P42*1 AN002 B5 P44*1 AN004 B6 PE6 B7 PE1 B8 PE4 C1 XCIN IRQ6/AN014 TXD12/TXDX12/SIOX12/SMOSI12/ SSDA12 IRQ1/AN009 MTIOC1A MOSIA IRQ4/AN012 MTIOC2B SCK1/SCK12 IRQ3/CMPA2/ CACREF/ADTRG0# PH7 C2 P05 C3 P27 C4 P41*1 AN001 C5 PE7 IRQ7/AN015 C6 PE5 MTIOC2B C7 PA1 MTIOC0B/MTCLKC/ RTCOUT C8 D1 IRQ5/AN013 SCK5/SSLA2 PA0 SSLA1 CACREF P30 RXD1/SMISO1/SSCL1 IRQ0 RES# D2 D3 P26 MTIOC2A TXD1/SMOSI1/SSDA1 D4 PE0 MTIOC2A SCK12 IRQ0/AN008 D5 PA6 MTIC5V/MTIOC2A/MTCLKB CTS5#/RTS5#/SS5#/SDA0/MOSIA IRQ3 D6 PA4 MTIC5U/MTIOC2B/MTCLKA TXD5/SMOSI5/SSDA5/SSLA0 IRQ5 D7 PA3 MTIOC0D/MTCLKD/ MTIOC1B RXD5/SMISO5/SSCL5/MISOA IRQ6 CTS1#/RTS1#/SS1# IRQ1 D8 VSS E1 XTAL E2 MD FINED E3 P31 E4 P55 E5 PB3 MTIOC0A E6 PB1 MTIOC0C E7 PB0 MTIC5W/MTIOC0C/ RTCOUT F2 P32 MTIOC0C/RTCOUT F3 P35 F4 P14 E8 VCC F1 EXTAL R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 IRQ4 SCL0/RSPCKA IRQ2/ADTRG0# IRQ2 NMI MTIOC0A/MTCLKA CTS1#/RTS1#/SS1#/TXD12/ TXDX12/SIOX12/SMOSI12/SSDA12/ SSLA0 IRQ4 Page 20 of 108 RX110 Group Table 1.6 Pin No. 1. Overview List of Pins and Pin Functions (64-Pin WFLGA) (2/2) Power Supply, Clock, System Control I/O Port Timers (MTU, RTC) Communication (SCIe, SCIf, RSPI, RIIC) Others F5 P54 F6 PC7 MTCLKB TXD1/SMOSI1/SSDA1/MISOA CACREF F7 PC4 MTCLKC SCK5/SSLA0 IRQ2/CLKOUT PB5 MTIOC1B/MTIOC2A P17 MTIOC0C SCK1/MISOA/SDA0/RXD12/RXDX12/ SMISO12/SSCL12 IRQ7 F8 G1 VCL G2 G3 P16 RTCOUT TXD1/SMOSI1/SSDA1/SCL0/MOSIA IRQ6/ADTRG0# G4 P15 MTIOC0B/MTCLKB RXD1/SMISO1/SSCL1/RSPCKA IRQ5/CLKOUT G5 PC6 MTCLKA RXD1/SMISO1/SSCL1/MOSIA G6 PC5 MTCLKD G7 PC3 G8 SCK1/RSPCKA TXD5/SMOSI5/SSDA5 PB6/PC0 H1 VSS H2 VCC H3 PH3 H4 PH2 H5 PH1 H6 PH0 H7 PC2 H8 PB7/PC1 MTIOC1A IRQ1 IRQ0 MTIOC1B CACREF RXD5/SMISO5/SSCL5/SSLA3 Note 1. The power source of the I/O buffer for these pins is AVCC0. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 21 of 108 RX110 Group Table 1.7 Pin No. List of Pins and Pin Functions (48-Pin LFQFP/HWQFN) (1/2) Power Supply, Clock, System Control 1 2 3 MD 4 RES# 5 XCOUT 6 XCIN 7 8 1. Overview I/O Port Timers (MTU, RTC) Communication (SCIe, SCIf, RSPI, RIIC) P27 MTIOC2B SCK1/SCK12 P26 MTIOC2A TXD1/SMOSI1/SSDA1 Others IRQ3/CMPA2/ CACREF/ADTRG0# FINED PH7 P35 NMI XTAL 9 EXTAL 10 VCL 11 VSS 12 VCC 13 P17 MTIOC0C SCK1/MISOA/SDA0/RXD12/RXDX12/ SMISO12/SSCL12 IRQ7 14 P16 RTCOUT TXD1/SMOSI1/SSDA1/MOSIA/SCL0 IRQ6/ADTRG0# 15 P15 MTIOC0B/MTCLKB RXD1/SMISO1/SSCL1/RSPCKA IRQ5/CLKOUT 16 P14 MTIOC0A/MTCLKA CTS1#/RTS1#/SS1#/SSLA0/TXD12/ TXDX12/SIOX12/SMOSI12/SSDA12 IRQ4 17 PH3 MTIOC1A 18 PH2 IRQ1 19 PH1 20 PH0 MTIOC1B 21 PC7 MTCLKB TXD1/SMOSI1/SSDA1/MISOA 22 PC6 MTCLKA RXD1/SMISO1/SSCL1/MOSIA 23 PC5 MTCLKD SCK1/RSPCKA 24 PC4 MTCLKC SCK5/SSLA0 25 PB5/PC3 MTIOC2A/MTIOC1B 26 PB3/PC2 MTIOC0A PB1/PC1 MTIOC0C PB0/PC0 MTIC5W/MTIOC0C/ RTCOUT SCL0/RSPCKA IRQ2/ADTRG0# PA6 MTIC5V/MTCLKB/MTIOC2A CTS5#/RTS5#/SS5#/SDA0/MOSIA IRQ3 27 28 CACREF CACREF IRQ2/CLKOUT IRQ4 VCC 29 30 IRQ0 VSS 31 32 PA4 MTIC5U/MTCLKA/MTIOC2B TXD5/SMOSI5/SSDA5/SSLA0 IRQ5 33 PA3 MTIOC0D/MTCLKD/ MTIOC1B RXD5/SMISO5/SSCL5/MISOA IRQ6 34 PA1 MTIOC0B/MTCLKC/ RTCOUT SCK5/SSLA2 35 PE4 MTIOC1A MOSIA IRQ4/AN012 36 PE3 MTIOC0A/MTIOC1B CTS12#/RTS12#/SS12#/RSPCKA IRQ3/AN011 37 PE2 RXD12/RXDX12/SMISO12/SSCL12 IRQ7/AN010 38 PE1 TXD12/TXDX12/SIOX12/SMOSI12/ SSDA12 IRQ1/AN009 39 PE0 40 PE7 IRQ7/AN015 41 P46*1 AN006 42 P42*1 AN002 43 P41*1 AN001 44 PJ7*1 VREFL0 R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 MTIOC2A SCK12 IRQ0/AN008 Page 22 of 108 RX110 Group Table 1.7 Pin No. 1. Overview List of Pins and Pin Functions (48-Pin LFQFP/HWQFN) (2/2) Power Supply, Clock, System Control I/O Port 45 P40*1 PJ6*1 46 VREFH0 47 AVSS0 48 AVCC0 Timers (MTU, RTC) Communication (SCIe, SCIf, RSPI, RIIC) Others AN000 Note 1. The power source of the I/O buffer for these pins is AVCC0. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 23 of 108 RX110 Group Table 1.8 Pin No. 1. Overview List of Pins and Pin Functions (40-Pin HWQFN) Power Supply, Clock, System Control 1 2 3 MD 4 RES# 5 I/O Port Timers (MTU, RTC) Communication (SCIe, SCIf, RSPI, RIIC) P27 MTIOC2B SCK1/SCK12 P26 MTIOC2A TXD1/SMOSI1/SSDA1 XTAL 7 EXTAL 8 VCL 9 VSS 10 VCC IRQ3/CMPA2/ CACREF/ADTRG0# FINED P35 6 Others NMI 11 P32 MTIOC0C 12 P17 MTIOC0C 13 P16 IRQ2 SCK1/MISOA/SDA0/RXD12/RXDX12/ SMISO12/SSCL12 IRQ7 TXD1/SMOSI1/SSDA1/SCL0/MOSIA IRQ6/ADTRG0# 14 P15 MTIOC0B/MTCLKB RXD1/SMISO1/SSCL1/RSPCKA IRQ5/CLKOUT 15 P14 MTIOC0A/MTCLKA CTS1#/RTS1#/SS1#/SSLA0/TXD12/ TXDX12/SIOX12/SMOSI12/SSDA12 IRQ4 16 PH3 MTIOC1A 17 PH2 IRQ1 18 PH1 19 PH0 MTIOC1B 20 PC4 MTCLKC 21 PB3 MTIOC0A PB0 22 CACREF SCK5/SSLA0 IRQ2/CLKOUT MTIOC0C/MTIC5W SCL0/RSPCKA IRQ2/ADTRG0# IRQ3 VCC 23 24 IRQ0 VSS 25 PA6 MTIOC2A/MTIC5V/MTCLKB CTS5#/RTS5#/SS5#/SDA0/MOSIA 26 PA4 MTIOC2B/MTIC5U/MTCLKA TXD5/SMOSI5/SSDA5/SSLA0 IRQ5 27 PA3 MTIOC0D/MTIOC1B/ MTCLKD RXD5/SMISO5/SSCL5/MISOA IRQ6 28 PA1 MTIOC0B/MTCLKC SCK5/SSLA2 29 PE4 MTIOC1A MOSIA IRQ4/AN012 MTIOC0A/MTIOC1B 30 PE3 CTS12#/RTS12#/SS12#/RSPCKA IRQ3/AN011 31 PE2 RXD12/RXDX12/SMISO12/SSCL12 IRQ7/AN010 32 PE1 TXD12/TXDX12/SIOX12/SMOSI12/ SSDA12 IRQ1/AN009 33 PE0 34 P46*1 AN006 35 P42*1 AN002 36 P41*1 AN001 37 VREFL0 PJ7*1 38 VREFH0 PJ6*1 39 AVSS0 40 AVCC0 MTIOC2A SCK12 IRQ0/AN008 Note 1. The power source of the I/O buffer for these pins is AVCC0. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 24 of 108 RX110 Group Table 1.9 1. Overview List of Pins and Pin Functions (36-Pin WFLGA) Pin No. Power Supply, Clock, System Control A1 AVSS0 A2 AVCC0 A3 VREFH0 I/O Port P42*1 A5 P41*1 A6 PE2 Others AN002 AN001 RXD12/RXDX12/SMISO12/SSCL12 IRQ7/AN010 SCK1/SCK12 IRQ3/CMPA2/ CACREF/ADTRG0# RES# B2 B3 Communication (SCIe, SCIf, RSPI, RIIC) PJ6*1 A4 B1 Timers (MTU, RTC) P27 VREFL0 PJ7*1 B4 PE0 B5 PE1 B6 PA3 C3 C4 C1 XTAL C2 MD C5 C6 VSS D1 EXTAL MTIOC2B MTIOC2A SCK12 IRQ0/AN008 TXD12/TXDX12/SIOX12/SMOSI12/ SSDA12 IRQ1/AN009 MTIOC0D/MTCLKD/ MTIOC1B RXD5/SMISO5/SSCL5/MISOA IRQ6 PE3 MTIOC0A/MTIOC1B CTS12#/RTS12#/SS12#/RSPCKA IRQ3/AN011 PE4 MTIOC1A MOSIA IRQ4/AN012 PA4 MTIOC2B/MTIC5U/MTCLKA TXD5/SMOSI5/SSDA5/SSLA0 IRQ5 FINED D2 P35 D3 P14 MTIOC0A/MTCLKA CTS1#/RTS1#/SS1#/SSLA0/TXD12/ TXDX12/SIOX12/SMOSI12/SSDA12 IRQ4 D4 PA6 MTIC5V/MTCLKB/MTIOC2A CTS5#/RTS5#/SS5#/SDA0/MOSIA IRQ3 D5 PB3 MTIOC0A D6 PB0 MTIOC0C/MTIC5W SCL0/RSPCKA IRQ2/ADTRG0# E2 P17 MTIOC0C SCK1/MISOA/SDA0/RXD12/RXDX12/ SMISO12/SSCL12 IRQ7 E3 P16 TXD1/SMOSI1/SSDA1/SCL0/MOSIA IRQ6/ADTRG0# E1 NMI VCL E4 P15 MTIOC0B/MTCLKB RXD1/SMISO1/SSCL1/RSPCKA IRQ5/CLKOUT E5 PC4 MTCLKC SCK5/SSLA0 IRQ2/CLKOUT MTIOC1A E6 VCC F1 VSS F2 VCC F3 PH3 F4 PH2 IRQ1 F5 PH1 IRQ0 F6 PH0 MTIOC1B CACREF Note 1. The power source of the I/O buffer for these pins is AVCC0. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 25 of 108 RX110 Group 2. 2. CPU CPU Figure 2.1 shows the register set of the CPU. General-purpose registers b31 b0 R0 (SP)*1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Control registers b31 b0 ISP (Interrupt stack pointer) USP (User stack pointer) INTB (Interrupt table register) PC (Program counter) PSW (Processor status word) BPC (Backup PC) BPSW (Backup PSW) FINTV (Fast interrupt vector register) DSP instruction register b63 b0 ACC (Accumulator) Note 1. The stack pointer (SP) can be the interrupt stack pointer (ISP) or user stack pointer (USP), according to the value of the U bit in the PSW register. Figure 2.1 Register Set of the CPU R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 26 of 108 RX110 Group 2.1 2. CPU General-Purpose Registers (R0 to R15) This CPU has 16 general-purpose registers (R0 to R15). R0 to R15 can be used as data registers or address registers. R0, a general-purpose register, also functions as the stack pointer (SP). The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the stack pointer select bit (U) in the processor status word (PSW). 2.2 (1) Control Registers Interrupt Stack Pointer (ISP)/User Stack Pointer (USP) The stack pointer (SP) can be either of two types, the interrupt stack pointer (ISP) or the user stack pointer (USP). Whether the stack pointer operates as the ISP or USP depends on the value of the stack pointer select bit (U) in the processor status word (PSW). Set the ISP or USP to a multiple of 4, as this reduces the numbers of cycles required to execute interrupt sequences and instructions entailing stack manipulation. (2) Interrupt Table Register (INTB) The interrupt table register (INTB) specifies the address where the relocatable vector table starts. (3) Program Counter (PC) The program counter (PC) indicates the address of the instruction being executed. (4) Processor Status Word (PSW) The processor status word (PSW) indicates the results of instruction execution or the state of the CPU. (5) Backup PC (BPC) The backup PC (BPC) is provided to speed up response to interrupts. After a fast interrupt has been generated, the contents of the program counter (PC) are saved in the BPC register. (6) Backup PSW (BPSW) The backup PSW (BPSW) is provided to speed up response to interrupts. After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in the BPSW. The allocation of bits in the BPSW corresponds to that in the PSW. (7) Fast Interrupt Vector Register (FINTV) The fast interrupt vector register (FINTV) is provided to speed up response to interrupts. The FINTV register specifies a branch destination address when a fast interrupt has been generated. 2.3 (1) Register Associated with DSP Instructions Accumulator (ACC) The accumulator (ACC) is a 64-bit register used for DSP instructions. The accumulator is also used for the multiply and multiply-and-accumulate instructions; EMUL, EMULU, MUL, and RMPA, in which case the prior value in the accumulator is modified by execution of the instruction. Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The MVTACHI and MVTACLO instructions write data to the higher-order 32 bits (bits 63 to 32) and the lower-order 32 bits (bits 31 to 0), respectively. Use the MVFACHI and MVFACMI instructions for reading data from the accumulator. The MVFACHI and MVFACMI instructions read data from the higher-order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 27 of 108 RX110 Group 3. Address Space 3.1 Address Space 3. Address Space This MCU has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is, linear access to an address space of up to 4 Gbytes is possible, and this contains program area. Figure 3.1 shows the memory map. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 28 of 108 RX110 Group 3. Address Space Single-chip mode*1 0000 0000h RAM*2 0000 4000h Reserved area*3 0008 0000h Peripheral I/O registers 0010 0000h Reserved area*3 007F C000h 007F C500h Peripheral I/O registers Reserved area*3 007F FC00h 0080 0000h Peripheral I/O registers Reserved area*3 FFFE 0000h On-chip ROM (program ROM)*2 FFFF FFFFh Note 1. Note 2. The address space in boot mode is the same as the address space in single-chip mode. The capacity of ROM/RAM differs depending on the products. ROM (bytes) RAM (bytes) Capacity Address Capacity Address 128 K FFFE 0000h to FFFF FFFFh 16 K 0000 0000h to 0000 3FFFh 96 K FFFE 8000h to FFFF FFFFh 10 K 0000 0000h to 0000 27FFh 8K 0000 0000h to 0000 1FFFh 64 K FFFF 0000h to FFFF FFFFh 32 K FFFF 8000h to FFFF FFFFh 16 K FFFF C000h to FFFF FFFFh 8K FFFF E000h to FFFF FFFFh Note:See Table 1.3, List of Products, for the product type name. Note 3. Reserved areas should not be accessed. Figure 3.1 Memory Map R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 29 of 108 RX110 Group 4. 4. I/O Registers I/O Registers This section provides information on the on-chip I/O register addresses and bit configuration. The information is given as shown below. Notes on writing to I/O registers are also given below. (1) I/O register addresses (address order)  Registers are listed from the lower allocation addresses.  Registers are classified according to module symbols.  Numbers of cycles for access indicate numbers of cycles of the given base clock.  Among the internal I/O register area, addresses not listed in the list of registers are reserved. Reserved addresses must not be accessed. Do not access these addresses; otherwise, the operation when accessing these bits and subsequent operations cannot be guaranteed. (2) Notes on writing to I/O registers While writing to an I/O register, the CPU starts executing subsequent instructions before the I/O register write access is completed. This may cause the subsequent instructions to be executed before the write value is reflected in the operation. The examples below show how subsequent instructions must be executed after a write access to an I/O register is completed. [Examples of cases requiring special care]  The subsequent instruction must be executed while an interrupt request is disabled with the IENj bit in IERn of the ICU (interrupt request enable bit) set to 0.  A WAIT instruction is executed immediately after the preprocessing for causing a transition to the low power consumption state. In the above cases, after writing to an I/O register, wait until the write operation is completed using the following procedure and then execute the subsequent instruction. (a) (b) (c) (d) Write to an I/O register. Read the value in the I/O register and write it to a general register. Execute the operation using the value read. Execute the subsequent instruction. Example of instructions  Byte-size I/O registers MOV.L #SFR_ADDR, R1 MOV.B #SFR_DATA, [R1] CMP [R1].UB, R1 ;; Next process  Word-size I/O registers MOV.L #SFR_ADDR, R1 MOV.W #SFR_DATA, [R1] CMP [R1].W, R1 ;; Next process R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 30 of 108 RX110 Group 4. I/O Registers  Longword-size I/O registers MOV.L #SFR_ADDR, R1 MOV.L #SFR_DATA, [R1] CMP [R1].L, R1 ;; Next process When executing an instruction after writing to multiple registers, only read the last I/O register written to and execute the instruction using that value; it is not necessary to execute the instruction using the values written to all the registers. (3) Number of cycles necessary for accessing I/O registers See Table 4.1 for details on the number of clock cycles necessary for accessing I/O registers. The number of access cycles to I/O registers is obtained by following equation.*1 Number of access cycles to I/O registers = Number of bus cycles for internal main bus 1 + Number of divided clock synchronization cycles + Number of bus cycles for internal peripheral buses 1, 2, and 4 to 6 The number of bus cycles of internal peripheral buses 1, 2, and 4 to 6 differs according to the register to be accessed. When peripheral functions connected to internal peripheral buses 2, and 4 to 6 or registers for the external bus control unit (except for bus error related registers) are accessed, the number of divided clock synchronization cycles is added. The number of divided clock synchronization cycles differs depending on the frequency ratio between ICLK and PCLK (or FCLK) or bus access timing. In the peripheral function unit, when the frequency ratio of ICLK is equal to or greater than that of PCLK (or FCLK), the sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will be one cycle of PCLK (or FCLK) at a maximum. Therefore, one PCLK (or FCLK) has been added to the number of access cycles shown in Table 4.1. When the frequency ratio of ICLK is lower than that of PCLK (or FCLK), the subsequent bus access is started from the ICLK cycle following the completion of the access to the peripheral functions. Therefore, the access cycles are described on an ICLK basis. Note 1. This applies to the number of cycles when the access from the CPU does not conflict with the bus access from the different bus master (DTC). (4) Notes on sleep mode and mode transitions During sleep mode or mode transitions, do not write to the system control related registers (indicated by ‘SYSTEM’ in the Module Symbol column in Table 4.1, List of I/O Registers (Address Order)). R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 31 of 108 RX110 Group 4.1 I/O Register Addresses (Address Order) Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (1/13) Module Symbol Register Name Register Symbol Number of Bits Access Size Number of Access States 0008 0000h SYSTEM Mode Monitor Register MDMONR 16 16 3 ICLK 0008 0008h SYSTEM System Control Register 1 SYSCR1 16 16 3 ICLK 3 ICLK 0008 000Ch SYSTEM Standby Control Register SBYCR 16 16 0008 0010h SYSTEM Module Stop Control Register A MSTPCRA 32 32 3 ICLK 0008 0014h SYSTEM Module Stop Control Register B MSTPCRB 32 32 3 ICLK 0008 0018h SYSTEM Module Stop Control Register C MSTPCRC 32 32 3 ICLK 0008 0020h SYSTEM System Clock Control Register SCKCR 32 32 3 ICLK 0008 0026h SYSTEM System Clock Control Register 3 SCKCR3 16 16 3 ICLK 0008 0032h SYSTEM Main Clock Oscillator Control Register MOSCCR 8 8 3 ICLK 0008 0033h SYSTEM Sub-Clock Oscillator Control Register SOSCCR 8 8 3 ICLK 0008 0034h SYSTEM Low-Speed On-Chip Oscillator Control Register LOCOCR 8 8 3 ICLK 0008 0035h SYSTEM IWDT-Dedicated On-Chip Oscillator Control Register ILOCOCR 8 8 3 ICLK 0008 0036h SYSTEM High-Speed On-Chip Oscillator Control Register HOCOCR 8 8 3 ICLK 0008 003Ch SYSTEM Oscillation Stabilization Flag Register OSCOVFSR 8 8 3 ICLK 0008 003Eh SYSTEM CLKOUT Output Control Register CKOCR 16 16 3 ICLK 3 ICLK 0008 0040h SYSTEM Oscillation Stop Detection Control Register OSTDCR 8 8 0008 0041h SYSTEM Oscillation Stop Detection Status Register OSTDSR 8 8 3 ICLK 0008 00A0h SYSTEM Operating Power Control Register OPCCR 8 8 3 ICLK 0008 00A1h SYSTEM Sleep Mode Return Clock Source Switching Register RSTCKCR 8 8 3 ICLK 0008 00A2h SYSTEM Main Clock Oscillator Wait Control Register MOSCWTCR 8 8 3 ICLK 0008 00A5h SYSTEM High-Speed On-Chip Oscillator Wait Control Register HOCOWTCR 8 8 3 ICLK 0008 00AAh SYSTEM Sub Operating Power Control Register SOPCCR 8 8 3 ICLK 0008 00C0h SYSTEM Reset Status Register 2 RSTSR2 8 8 3 ICLK 0008 00C2h SYSTEM Software Reset Register SWRR 16 16 3 ICLK 3 ICLK 0008 00E0h SYSTEM Voltage Monitoring 1 Circuit Control Register 1 LVD1CR1 8 8 0008 00E1h SYSTEM Voltage Monitoring 1 Circuit Status Register LVD1SR 8 8 3 ICLK 0008 00E2h SYSTEM Voltage Monitoring 2 Circuit Control Register 1 LVD2CR1 8 8 3 ICLK 0008 00E3h SYSTEM Voltage Monitoring 2 Circuit Status Register LVD2SR 8 8 3 ICLK 0008 03FEh SYSTEM Protect Register PRCR 16 16 3 ICLK 0008 1300h BSC Bus Error Status Clear Register BERCLR 8 8 2 ICLK 0008 1304h BSC Bus Error Monitoring Enable Register BEREN 8 8 2 ICLK 0008 1308h BSC Bus Error Status Register 1 BERSR1 8 8 2 ICLK 0008 130Ah BSC Bus Error Status Register 2 BERSR2 16 16 2 ICLK 0008 1310h BSC Bus Priority Control Register BUSPRI 16 16 2 ICLK 0008 2400h DTC DTC Control Register DTCCR 8 8 2 ICLK 0008 2404h DTC DTC Vector Base Register DTCVBR 32 32 2 ICLK 0008 2408h DTC DTC Address Mode Register DTCADMOD 8 8 2 ICLK 0008 240Ch DTC DTC Module Start Register DTCST 8 8 2 ICLK 0008 240Eh DTC DTC Status Register DTCSTS 16 16 2 ICLK 0008 7010h ICU Interrupt Request Register 016 IR016 8 8 2 ICLK 0008 701Bh ICU Interrupt Request Register 027 IR027 8 8 2 ICLK 0008 701Ch ICU Interrupt Request Register 028 IR028 8 8 2 ICLK 2 ICLK 0008 701Dh ICU Interrupt Request Register 029 IR029 8 8 0008 7020h ICU Interrupt Request Register 032 IR032 8 8 2 ICLK 0008 7021h ICU Interrupt Request Register 033 IR033 8 8 2 ICLK 0008 7022h ICU Interrupt Request Register 034 IR034 8 8 2 ICLK 0008 7024h ICU Interrupt Request Register 036 IR036 8 8 2 ICLK 0008 7025h ICU Interrupt Request Register 037 IR037 8 8 2 ICLK 0008 7026h ICU Interrupt Request Register 038 IR038 8 8 2 ICLK 0008 702Ch ICU Interrupt Request Register 044 IR044 8 8 2 ICLK R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 32 of 108 RX110 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (2/13) Module Symbol Register Name Register Symbol Number of Bits Access Size Number of Access States 0008 702Dh ICU Interrupt Request Register 045 IR045 8 8 2 ICLK 0008 702Eh ICU Interrupt Request Register 046 IR046 8 8 2 ICLK 0008 702Fh ICU Interrupt Request Register 047 IR047 8 8 2 ICLK 0008 7039h ICU Interrupt Request Register 057 IR057 8 8 2 ICLK 0008 703Fh ICU Interrupt Request Register 063 IR063 8 8 2 ICLK 0008 7040h ICU Interrupt Request Register 064 IR064 8 8 2 ICLK 0008 7041h ICU Interrupt Request Register 065 IR065 8 8 2 ICLK 0008 7042h ICU Interrupt Request Register 066 IR066 8 8 2 ICLK 0008 7043h ICU Interrupt Request Register 067 IR067 8 8 2 ICLK 0008 7044h ICU Interrupt Request Register 068 IR068 8 8 2 ICLK 0008 7045h ICU Interrupt Request Register 069 IR069 8 8 2 ICLK 0008 7046h ICU Interrupt Request Register 070 IR070 8 8 2 ICLK 0008 7047h ICU Interrupt Request Register 071 IR071 8 8 2 ICLK 0008 7058h ICU Interrupt Request Register 088 IR088 8 8 2 ICLK 0008 7059h ICU Interrupt Request Register 089 IR089 8 8 2 ICLK 0008 705Ah ICU Interrupt Request Register 090 IR090 8 8 2 ICLK 0008 705Ch ICU Interrupt Request Register 092 IR092 8 8 2 ICLK 0008 705Dh ICU Interrupt Request Register 093 IR093 8 8 2 ICLK 0008 7066h ICU Interrupt Request Register 102 IR102 8 8 2 ICLK 0008 7067h ICU Interrupt Request Register 103 IR103 8 8 2 ICLK 0008 706Ah ICU Interrupt Request Register 106 IR106 8 8 2 ICLK 0008 7072h ICU Interrupt Request Register 114 IR114 8 8 2 ICLK 0008 7073h ICU Interrupt Request Register 115 IR115 8 8 2 ICLK 0008 7074h ICU Interrupt Request Register 116 IR116 8 8 2 ICLK 0008 7075h ICU Interrupt Request Register 117 IR117 8 8 2 ICLK 0008 7076h ICU Interrupt Request Register 118 IR118 8 8 2 ICLK 0008 7077h ICU Interrupt Request Register 119 IR119 8 8 2 ICLK 0008 7078h ICU Interrupt Request Register 120 IR120 8 8 2 ICLK 0008 7079h ICU Interrupt Request Register 121 IR121 8 8 2 ICLK 0008 707Ah ICU Interrupt Request Register 122 IR122 8 8 2 ICLK 0008 707Bh ICU Interrupt Request Register 123 IR123 8 8 2 ICLK 0008 707Ch ICU Interrupt Request Register 124 IR124 8 8 2 ICLK 0008 707Dh ICU Interrupt Request Register 125 IR125 8 8 2 ICLK 0008 707Eh ICU Interrupt Request Register 126 IR126 8 8 2 ICLK 0008 707Fh ICU Interrupt Request Register 127 IR127 8 8 2 ICLK 0008 7080h ICU Interrupt Request Register 128 IR128 8 8 2 ICLK 0008 7081h ICU Interrupt Request Register 129 IR129 8 8 2 ICLK 0008 7082h ICU Interrupt Request Register 130 IR130 8 8 2 ICLK 0008 7083h ICU Interrupt Request Register 131 IR131 8 8 2 ICLK 0008 7084h ICU Interrupt Request Register 132 IR132 8 8 2 ICLK 0008 7085h ICU Interrupt Request Register 133 IR133 8 8 2 ICLK 0008 7086h ICU Interrupt Request Register 134 IR134 8 8 2 ICLK 0008 7087h ICU Interrupt Request Register 135 IR135 8 8 2 ICLK 0008 7088h ICU Interrupt Request Register 136 IR136 8 8 2 ICLK 0008 7089h ICU Interrupt Request Register 137 IR137 8 8 2 ICLK 0008 708Ah ICU Interrupt Request Register 138 IR138 8 8 2 ICLK 0008 708Bh ICU Interrupt Request Register 139 IR139 8 8 2 ICLK 0008 708Ch ICU Interrupt Request Register 140 IR140 8 8 2 ICLK 0008 708Dh ICU Interrupt Request Register 141 IR141 8 8 2 ICLK 0008 70AAh ICU Interrupt Request Register 170 IR170 8 8 2 ICLK 0008 70ABh ICU Interrupt Request Register 171 IR171 8 8 2 ICLK 0008 70DAh ICU Interrupt Request Register 218 IR218 8 8 2 ICLK R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 33 of 108 RX110 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (3/13) Module Symbol Register Name Register Symbol Number of Bits Access Size Number of Access States 0008 70DBh ICU Interrupt Request Register 219 IR219 8 8 2 ICLK 0008 70DCh ICU Interrupt Request Register 220 IR220 8 8 2 ICLK 0008 70DDh ICU Interrupt Request Register 221 IR221 8 8 2 ICLK 0008 70DEh ICU Interrupt Request Register 222 IR222 8 8 2 ICLK 0008 70DFh ICU Interrupt Request Register 223 IR223 8 8 2 ICLK 0008 70E0h ICU Interrupt Request Register 224 IR224 8 8 2 ICLK 0008 70E1h ICU Interrupt Request Register 225 IR225 8 8 2 ICLK 0008 70EEh ICU Interrupt Request Register 238 IR238 8 8 2 ICLK 0008 70EFh ICU Interrupt Request Register 239 IR239 8 8 2 ICLK 0008 70F0h ICU Interrupt Request Register 240 IR240 8 8 2 ICLK 0008 70F1h ICU Interrupt Request Register 241 IR241 8 8 2 ICLK 0008 70F2h ICU Interrupt Request Register 242 IR242 8 8 2 ICLK 0008 70F3h ICU Interrupt Request Register 243 IR243 8 8 2 ICLK 0008 70F4h ICU Interrupt Request Register 244 IR244 8 8 2 ICLK 0008 70F5h ICU Interrupt Request Register 245 IR245 8 8 2 ICLK 0008 70F6h ICU Interrupt Request Register 246 IR246 8 8 2 ICLK 0008 70F7h ICU Interrupt Request Register 247 IR247 8 8 2 ICLK 0008 70F8h ICU Interrupt Request Register 248 IR248 8 8 2 ICLK 0008 70F9h ICU Interrupt Request Register 249 IR249 8 8 2 ICLK 0008 711Bh ICU DTC Activation Enable Register 027 DTCER027 8 8 2 ICLK 0008 711Ch ICU DTC Activation Enable Register 028 DTCER028 8 8 2 ICLK 0008 711Dh ICU DTC Activation Enable Register 029 DTCER029 8 8 2 ICLK 0008 712Dh ICU DTC Activation Enable Register 045 DTCER045 8 8 2 ICLK 0008 712Eh ICU DTC Activation Enable Register 046 DTCER046 8 8 2 ICLK 0008 7140h ICU DTC Activation Enable Register 064 DTCER064 8 8 2 ICLK 0008 7141h ICU DTC Activation Enable Register 065 DTCER065 8 8 2 ICLK 0008 7142h ICU DTC Activation Enable Register 066 DTCER066 8 8 2 ICLK 0008 7143h ICU DTC Activation Enable Register 067 DTCER067 8 8 2 ICLK 0008 7144h ICU DTC Activation Enable Register 068 DTCER068 8 8 2 ICLK 0008 7145h ICU DTC Activation Enable Register 069 DTCER069 8 8 2 ICLK 0008 7146h ICU DTC Activation Enable Register 070 DTCER070 8 8 2 ICLK 0008 7147h ICU DTC Activation Enable Register 071 DTCER071 8 8 2 ICLK 0008 7166h ICU DTC Activation Enable Register 102 DTCER102 8 8 2 ICLK 0008 7167h ICU DTC Activation Enable Register 103 DTCER103 8 8 2 ICLK 0008 7172h ICU DTC Activation Enable Register 114 DTCER114 8 8 2 ICLK 0008 7173h ICU DTC Activation Enable Register 115 DTCER115 8 8 2 ICLK 0008 7174h ICU DTC Activation Enable Register 116 DTCER116 8 8 2 ICLK 0008 7175h ICU DTC Activation Enable Register 117 DTCER117 8 8 2 ICLK 0008 7179h ICU DTC Activation Enable Register 121 DTCER121 8 8 2 ICLK 0008 717Ah ICU DTC Activation Enable Register 122 DTCER122 8 8 2 ICLK 0008 717Dh ICU DTC Activation Enable Register 125 DTCER125 8 8 2 ICLK 0008 717Eh ICU DTC Activation Enable Register 126 DTCER126 8 8 2 ICLK 0008 718Bh ICU DTC Activation Enable Register 139 DTCER139 8 8 2 ICLK 0008 718Ch ICU DTC Activation Enable Register 140 DTCER140 8 8 2 ICLK 0008 718Dh ICU DTC Activation Enable Register 141 DTCER141 8 8 2 ICLK 0008 71DBh ICU DTC Activation Enable Register 219 DTCER219 8 8 2 ICLK 0008 71DCh ICU DTC Activation Enable Register 220 DTCER220 8 8 2 ICLK 0008 71DFh ICU DTC Activation Enable Register 223 DTCER223 8 8 2 ICLK 0008 71E0h ICU DTC Activation Enable Register 224 DTCER224 8 8 2 ICLK 0008 71EFh ICU DTC Activation Enable Register 239 DTCER239 8 8 2 ICLK 0008 71F0h ICU DTC Activation Enable Register 240 DTCER240 8 8 2 ICLK 0008 71F7h ICU DTC Activation Enable Register 247 DTCER247 8 8 2 ICLK R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 34 of 108 RX110 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (4/13) Module Symbol Register Name Register Symbol Number of Bits Access Size Number of Access States 0008 71F8h ICU DTC Activation Enable Register 248 DTCER248 8 8 2 ICLK 0008 7202h ICU Interrupt Request Enable Register 02 IER02 8 8 2 ICLK 0008 7203h ICU Interrupt Request Enable Register 03 IER03 8 8 2 ICLK 0008 7204h ICU Interrupt Request Enable Register 04 IER04 8 8 2 ICLK 0008 7205h ICU Interrupt Request Enable Register 05 IER05 8 8 2 ICLK 0008 7207h ICU Interrupt Request Enable Register 07 IER07 8 8 2 ICLK 0008 7208h ICU Interrupt Request Enable Register 08 IER08 8 8 2 ICLK 0008 720Bh ICU Interrupt Request Enable Register 0B IER0B 8 8 2 ICLK 0008 720Ch ICU Interrupt Request Enable Register 0C IER0C 8 8 2 ICLK 0008 720Eh ICU Interrupt Request Enable Register 0E IER0E 8 8 2 ICLK 0008 720Fh ICU Interrupt Request Enable Register 0F IER0F 8 8 2 ICLK 0008 7210h ICU Interrupt Request Enable Register 10 IER10 8 8 2 ICLK 0008 7211h ICU Interrupt Request Enable Register 11 IER11 8 8 2 ICLK 0008 721Bh ICU Interrupt Request Enable Register 1B IER1B 8 8 2 ICLK 0008 721Ch ICU Interrupt Request Enable Register 1C IER1C 8 8 2 ICLK 0008 721Dh ICU Interrupt Request Enable Register 1D IER1D 8 8 2 ICLK 0008 721Eh ICU Interrupt Request Enable Register 1E IER1E 8 8 2 ICLK 0008 721Fh ICU Interrupt Request Enable Register 1F IER1F 8 8 2 ICLK 0008 72E0h ICU Software Interrupt Activation Register SWINTR 8 8 2 ICLK 0008 72F0h ICU Fast Interrupt Set Register FIR 16 16 2 ICLK 0008 7300h ICU Interrupt Source Priority Register 000 IPR000 8 8 2 ICLK 0008 7303h ICU Interrupt Source Priority Register 003 IPR003 8 8 2 ICLK 0008 7304h ICU Interrupt Source Priority Register 004 IPR004 8 8 2 ICLK 0008 7305h ICU Interrupt Source Priority Register 005 IPR005 8 8 2 ICLK 0008 7320h ICU Interrupt Source Priority Register 032 IPR032 8 8 2 ICLK 0008 7321h ICU Interrupt Source Priority Register 033 IPR033 8 8 2 ICLK 0008 7322h ICU Interrupt Source Priority Register 034 IPR034 8 8 2 ICLK 0008 732Ch ICU Interrupt Source Priority Register 044 IPR044 8 8 2 ICLK 0008 7339h ICU Interrupt Source Priority Register 057 IPR057 8 8 2 ICLK 0008 733Fh ICU Interrupt Source Priority Register 063 IPR063 8 8 2 ICLK 0008 7340h ICU Interrupt Source Priority Register 064 IPR064 8 8 2 ICLK 0008 7341h ICU Interrupt Source Priority Register 065 IPR065 8 8 2 ICLK 0008 7342h ICU Interrupt Source Priority Register 066 IPR066 8 8 2 ICLK 0008 7343h ICU Interrupt Source Priority Register 067 IPR067 8 8 2 ICLK 0008 7344h ICU Interrupt Source Priority Register 068 IPR068 8 8 2 ICLK 0008 7345h ICU Interrupt Source Priority Register 069 IPR069 8 8 2 ICLK 0008 7346h ICU Interrupt Source Priority Register 070 IPR070 8 8 2 ICLK 0008 7347h ICU Interrupt Source Priority Register 071 IPR071 8 8 2 ICLK 0008 7358h ICU Interrupt Source Priority Register 088 IPR088 8 8 2 ICLK 0008 7359h ICU Interrupt Source Priority Register 089 IPR089 8 8 2 ICLK 0008 735Ch ICU Interrupt Source Priority Register 092 IPR092 8 8 2 ICLK 0008 735Dh ICU Interrupt Source Priority Register 093 IPR093 8 8 2 ICLK 0008 7366h ICU Interrupt Source Priority Register 102 IPR102 8 8 2 ICLK 0008 7367h ICU Interrupt Source Priority Register 103 IPR103 8 8 2 ICLK 0008 7372h ICU Interrupt Source Priority Register 114 IPR114 8 8 2 ICLK 0008 7376h ICU Interrupt Source Priority Register 118 IPR118 8 8 2 ICLK 0008 7379h ICU Interrupt Source Priority Register 121 IPR121 8 8 2 ICLK 0008 737Bh ICU Interrupt Source Priority Register 123 IPR123 8 8 2 ICLK 0008 737Dh ICU Interrupt Source Priority Register 125 IPR125 8 8 2 ICLK 0008 737Fh ICU Interrupt Source Priority Register 127 IPR127 8 8 2 ICLK 0008 738Bh ICU Interrupt Source Priority Register 139 IPR139 8 8 2 ICLK 0008 73DAh ICU Interrupt Source Priority Register 218 IPR218 8 8 2 ICLK R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 35 of 108 RX110 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (5/13) Module Symbol Register Name Register Symbol Number of Bits Access Size Number of Access States 0008 73DEh ICU Interrupt Source Priority Register 222 IPR222 8 8 2 ICLK 0008 73EEh ICU Interrupt Source Priority Register 238 IPR238 8 8 2 ICLK 0008 73F2h ICU Interrupt Source Priority Register 242 IPR242 8 8 2 ICLK 0008 73F3h ICU Interrupt Source Priority Register 243 IPR243 8 8 2 ICLK 0008 73F4h ICU Interrupt Source Priority Register 244 IPR244 8 8 2 ICLK 0008 73F5h ICU Interrupt Source Priority Register 245 IPR245 8 8 2 ICLK 0008 73F6h ICU Interrupt Source Priority Register 246 IPR246 8 8 2 ICLK 0008 73F7h ICU Interrupt Source Priority Register 247 IPR247 8 8 2 ICLK 0008 73F8h ICU Interrupt Source Priority Register 248 IPR248 8 8 2 ICLK 0008 73F9h ICU Interrupt Source Priority Register 249 IPR249 8 8 2 ICLK 0008 7500h ICU IRQ Control Register 0 IRQCR0 8 8 2 ICLK 0008 7501h ICU IRQ Control Register 1 IRQCR1 8 8 2 ICLK 0008 7502h ICU IRQ Control Register 2 IRQCR2 8 8 2 ICLK 0008 7503h ICU IRQ Control Register 3 IRQCR3 8 8 2 ICLK 0008 7504h ICU IRQ Control Register 4 IRQCR4 8 8 2 ICLK 0008 7505h ICU IRQ Control Register 5 IRQCR5 8 8 2 ICLK 0008 7506h ICU IRQ Control Register 6 IRQCR6 8 8 2 ICLK 0008 7507h ICU IRQ Control Register 7 IRQCR7 8 8 2 ICLK 0008 7510h ICU IRQ Pin Digital Filter Enable Register 0 IRQFLTE0 8 8 2 ICLK 0008 7514h ICU IRQ Pin Digital Filter Setting Register 0 IRQFLTC0 16 16 2 ICLK 0008 7580h ICU Non-Maskable Interrupt Status Register NMISR 8 8 2 ICLK 0008 7581h ICU Non-Maskable Interrupt Enable Register NMIER 8 8 2 ICLK 0008 7582h ICU Non-Maskable Interrupt Status Clear Register NMICLR 8 8 2 ICLK 0008 7583h ICU NMI Pin Interrupt Control Register NMICR 8 8 2 ICLK 0008 7590h ICU NMI Pin Digital Filter Enable Register NMIFLTE 8 8 2 ICLK 0008 7594h ICU NMI Pin Digital Filter Setting Register NMIFLTC 8 8 2 ICLK 0008 8000h CMT Compare Match Timer Start Register 0 CMSTR0 16 16 2 or 3 PCLKB 0008 8002h CMT0 Compare Match Timer Control Register CMCR 16 16 2 or 3 PCLKB 0008 8004h CMT0 Compare Match Timer Counter CMCNT 16 16 2 or 3 PCLKB 0008 8006h CMT0 Compare Match Timer Constant Register CMCOR 16 16 2 or 3 PCLKB 0008 8008h CMT1 Compare Match Timer Control Register CMCR 16 16 2 or 3 PCLKB 0008 800Ah CMT1 Compare Match Timer Counter CMCNT 16 16 2 or 3 PCLKB 0008 800Ch CMT1 Compare Match Timer Constant Register CMCOR 16 16 2 or 3 PCLKB 0008 8030h IWDT IWDT Refresh Register IWDTRR 8 8 2 or 3 PCLKB 0008 8032h IWDT IWDT Control Register IWDTCR 16 16 2 or 3 PCLKB 0008 8034h IWDT IWDT Status Register IWDTSR 16 16 2 or 3 PCLKB 0008 8036h IWDT IWDT Reset Control Register IWDTRCR 8 8 2 or 3 PCLKB 0008 8038h IWDT IWDT Count Stop Control Register IWDTCSTPR 8 8 2 or 3 PCLKB 0008 8280h CRC CRC Control Register CRCCR 8 8 2 or 3 PCLKB 0008 8281h CRC CRC Data Input Register CRCDIR 8 8 2 or 3 PCLKB 0008 8282h CRC CRC Data Output Register CRCDOR 16 16 2 or 3 PCLKB 0008 8300h RIIC0 I2C Bus Control Register 1 ICCR1 8 8 2 or 3 PCLKB 0008 8301h RIIC0 I2C Bus Control Register 2 ICCR2 8 8 2 or 3 PCLKB 0008 8302h RIIC0 I2C Bus Mode Register 1 ICMR1 8 8 2 or 3 PCLKB 0008 8303h RIIC0 I2C Bus Mode Register 2 ICMR2 8 8 2 or 3 PCLKB 0008 8304h RIIC0 I2C Bus Mode Register 3 ICMR3 8 8 2 or 3 PCLKB 0008 8305h RIIC0 I2C Bus Function Enable Register ICFER 8 8 2 or 3 PCLKB 0008 8306h RIIC0 I2C Bus Status Enable Register ICSER 8 8 2 or 3 PCLKB 0008 8307h RIIC0 I2C Bus Interrupt Enable Register ICIER 8 8 2 or 3 PCLKB 0008 8308h RIIC0 I2C Bus Status Register 1 ICSR1 8 8 2 or 3 PCLKB 0008 8309h RIIC0 I2C Bus Status Register 2 ICSR2 8 8 2 or 3 PCLKB 0008 830Ah RIIC0 Slave Address Register L0 SARL0 8 8 2 or 3 PCLKB R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 36 of 108 RX110 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (6/13) Module Symbol Register Name Register Symbol Number of Bits Access Size Number of Access States 0008 830Ah RIIC0 Timeout Internal Counter L TMOCNTL 8 8 2 or 3 PCLKB 0008 830Bh RIIC0 Slave Address Register U0 SARU0 8 8 2 or 3 PCLKB 0008 830Bh RIIC0 Timeout Internal Counter U TMOCNTU 8 8 *1 2 or 3 PCLKB 0008 830Ch RIIC0 Slave Address Register L1 SARL1 8 8 2 or 3 PCLKB 0008 830Dh RIIC0 Slave Address Register U1 SARU1 8 8 2 or 3 PCLKB 0008 830Eh RIIC0 Slave Address Register L2 SARL2 8 8 2 or 3 PCLKB 0008 830Fh RIIC0 Slave Address Register U2 SARU2 8 8 2 or 3 PCLKB 0008 8310h RIIC0 I2C Bus Bit Rate Low-Level Register ICBRL 8 8 2 or 3 PCLKB 0008 8311h RIIC0 I2C Bus Bit Rate High-Level Register ICBRH 8 8 2 or 3 PCLKB 0008 8312h RIIC0 I2C Bus Transmit Data Register ICDRT 8 8 2 or 3 PCLKB 0008 8313h RIIC0 I2C Bus Receive Data Register ICDRR 8 8 2 or 3 PCLKB 0008 8380h RSPI0 RSPI Control Register SPCR 8 8 2 or 3 PCLKB 0008 8381h RSPI0 RSPI Slave Select Polarity Register SSLP 8 8 2 or 3 PCLKB 2 or 3 PCLKB 0008 8382h RSPI0 RSPI Pin Control Register SPPCR 8 8 0008 8383h RSPI0 RSPI Status Register SPSR 8 8 2 or 3 PCLKB 0008 8384h RSPI0 RSPI Data Register SPDR 32 16, 32 2 or 3 PCLKB/2ICLK 0008 8388h RSPI0 RSPI Sequence Control Register SPSCR 8 8 2 or 3 PCLKB 0008 8389h RSPI0 RSPI Sequence Status Register SPSSR 8 8 2 or 3 PCLKB 0008 838Ah RSPI0 RSPI Bit Rate Register SPBR 8 8 2 or 3 PCLKB 0008 838Bh RSPI0 RSPI Data Control Register SPDCR 8 8 2 or 3 PCLKB 0008 838Ch RSPI0 RSPI Clock Delay Register SPCKD 8 8 2 or 3 PCLKB 0008 838Dh RSPI0 RSPI Slave Select Negation Delay Register SSLND 8 8 2 or 3 PCLKB 0008 838Eh RSPI0 RSPI Next-Access Delay Register SPND 8 8 2 or 3 PCLKB 0008 838Fh RSPI0 RSPI Control Register 2 SPCR2 8 8 2 or 3 PCLKB 0008 8390h RSPI0 RSPI Command Register 0 SPCMD0 16 16 2 or 3 PCLKB 0008 8392h RSPI0 RSPI Command Register 1 SPCMD1 16 16 2 or 3 PCLKB 0008 8394h RSPI0 RSPI Command Register 2 SPCMD2 16 16 2 or 3 PCLKB 0008 8396h RSPI0 RSPI Command Register 3 SPCMD3 16 16 2 or 3 PCLKB 0008 8398h RSPI0 RSPI Command Register 4 SPCMD4 16 16 2 or 3 PCLKB 0008 839Ah RSPI0 RSPI Command Register 5 SPCMD5 16 16 2 or 3 PCLKB 0008 839Ch RSPI0 RSPI Command Register 6 SPCMD6 16 16 2 or 3 PCLKB 2 or 3 PCLKB 0008 839Eh RSPI0 RSPI Command Register 7 SPCMD7 16 16 0008 8680h MTU Timer Start Register TSTR 8 8, 16 2 or 3 PCLKB 0008 8681h MTU Timer Synchronous Register TSYR 8 8, 16 2 or 3 PCLKB 0008 8690h MTU0 Noise Filter Control Register NFCR 8 8, 16 2 or 3 PCLKB 0008 8691h MTU1 Noise Filter Control Register NFCR 8 8, 16 2 or 3 PCLKB 0008 8692h MTU2 Noise Filter Control Register NFCR 8 8, 16 2 or 3 PCLKB 0008 8695h MTU5 Noise Filter Control Register NFCR 8 8, 16 2 or 3 PCLKB 2 or 3 PCLKB 0008 8700h MTU0 Timer Control Register TCR 8 8 0008 8701h MTU0 Timer Mode Register TMDR 8 8 2 or 3 PCLKB 0008 8702h MTU0 Timer I/O Control Register H TIORH 8 8 2 or 3 PCLKB 0008 8703h MTU0 Timer I/O Control Register L TIORL 8 8 2 or 3 PCLKB 0008 8704h MTU0 Timer Interrupt Enable Register TIER 8 8 2 or 3 PCLKB 0008 8705h MTU0 Timer Status Register TSR 8 8 2 or 3 PCLKB 0008 8706h MTU0 Timer Counter TCNT 16 16 2 or 3 PCLKB 0008 8708h MTU0 Timer General Register A TGRA 16 16 2 or 3 PCLKB 0008 870Ah MTU0 Timer General Register B TGRB 16 16 2 or 3 PCLKB 0008 870Ch MTU0 Timer General Register C TGRC 16 16 2 or 3 PCLKB 2 or 3 PCLKB 0008 870Eh MTU0 Timer General Register D TGRD 16 16 0008 8720h MTU0 Timer General Register E TGRE 16 16 2 or 3 PCLKB 0008 8722h MTU0 Timer General Register F TGRF 16 16 2 or 3 PCLKB 0008 8724h MTU0 Timer Interrupt Enable Register 2 TIER2 8 8 2 or 3 PCLKB R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 37 of 108 RX110 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (7/13) Module Symbol Register Name Register Symbol Number of Bits Access Size Number of Access States 0008 8726h MTU0 Timer Buffer Operation Transfer Mode Register TBTM 8 8 2 or 3 PCLKB 0008 8780h MTU1 Timer Control Register TCR 8 8 2 or 3 PCLKB 0008 8781h MTU1 Timer Mode Register TMDR 8 8 2 or 3 PCLKB 0008 8782h MTU1 Timer I/O Control Register TIOR 8 8 2 or 3 PCLKB 0008 8784h MTU1 Timer Interrupt Enable Register TIER 8 8 2 or 3 PCLKB 0008 8785h MTU1 Timer Status Register TSR 8 8 2 or 3 PCLKB 0008 8786h MTU1 Timer Counter TCNT 16 16 2 or 3 PCLKB 0008 8788h MTU1 Timer General Register A TGRA 16 16 2 or 3 PCLKB 2 or 3 PCLKB 0008 878Ah MTU1 Timer General Register B TGRB 16 16 0008 8790h MTU1 Timer Input Capture Control Register TICCR 8 8 2 or 3 PCLKB 0008 8800h MTU2 Timer Control Register TCR 8 8 2 or 3 PCLKB 2 or 3 PCLKB 0008 8801h MTU2 Timer Mode Register TMDR 8 8 0008 8802h MTU2 Timer I/O Control Register TIOR 8 8 2 or 3 PCLKB 0008 8804h MTU2 Timer Interrupt Enable Register TIER 8 8 2 or 3 PCLKB 0008 8805h MTU2 Timer Status Register TSR 8 8 2 or 3 PCLKB 0008 8806h MTU2 Timer Counter TCNT 16 16 2 or 3 PCLKB 0008 8808h MTU2 Timer General Register A TGRA 16 16 2 or 3 PCLKB 0008 880Ah MTU2 Timer General Register B TGRB 16 16 2 or 3 PCLKB 2 or 3 PCLKB 0008 8880h MTU5 Timer Counter U TCNTU 16 16 0008 8882h MTU5 Timer General Register U TGRU 16 16 2 or 3 PCLKB 0008 8884h MTU5 Timer Control Register U TCRU 8 8 2 or 3 PCLKB 0008 8886h MTU5 Timer I/O Control Register U TIORU 8 8 2 or 3 PCLKB 0008 8890h MTU5 Timer Counter V TCNTV 16 16 2 or 3 PCLKB 0008 8892h MTU5 Timer General Register V TGRV 16 16 2 or 3 PCLKB 2 or 3 PCLKB 0008 8894h MTU5 Timer Control Register V TCRV 8 8 0008 8896h MTU5 Timer I/O Control Register V TIORV 8 8 2 or 3 PCLKB 0008 88A0h MTU5 Timer Counter W TCNTW 16 16 2 or 3 PCLKB 0008 88A2h MTU5 Timer General Register W TGRW 16 16 2 or 3 PCLKB 0008 88A4h MTU5 Timer Control Register W TCRW 8 8 2 or 3 PCLKB 0008 88A6h MTU5 Timer I/O Control Register W TIORW 8 8 2 or 3 PCLKB 0008 88B2h MTU5 Timer Interrupt Enable Register TIER 8 8 2 or 3 PCLKB 0008 88B4h MTU5 Timer Start Register TSTR 8 8 2 or 3 PCLKB 0008 88B6h MTU5 Timer Compare Match Clear Register TCNTCMPCLR 8 8 2 or 3 PCLKB 0008 9000h S12AD A/D Control Register ADCSR 16 16 2 or 3 PCLKB 0008 9004h S12AD A/D Channel Select Register A ADANSA 16 16 2 or 3 PCLKB 0008 9008h S12AD A/D-Converted Value Addition Mode Select Register ADADS 16 16 2 or 3 PCLKB 0008 900Ch S12AD A/D-Converted Value Addition Count Select Register ADADC 8 8 2 or 3 PCLKB 0008 900Eh S12AD A/D Control Extended Register ADCER 16 16 2 or 3 PCLKB 0008 9010h S12AD A/D Start Trigger Select Register ADSTRGR 16 16 2 or 3 PCLKB 0008 9012h S12AD A/D Converted Extended Input Control Register ADEXICR 16 16 2 or 3 PCLKB 0008 9014h S12AD A/D Channel Select Register B ADANSB 16 16 2 or 3 PCLKB 0008 9018h S12AD A/D Data Duplication Register ADDBLDR 16 16 2 or 3 PCLKB 0008 901Ah S12AD A/D Temperature Sensor Data Register ADTSDR 16 16 2 or 3 PCLKB 0008 901Ch S12AD A/D Internal Reference Voltage Data Register ADOCDR 16 16 2 or 3 PCLKB 0008 9020h S12AD A/D Data Register 0 ADDR0 16 16 2 or 3 PCLKB 0008 9022h S12AD A/D Data Register 1 ADDR1 16 16 2 or 3 PCLKB 0008 9024h S12AD A/D Data Register 2 ADDR2 16 16 2 or 3 PCLKB 0008 9026h S12AD A/D Data Register 3 ADDR3 16 16 2 or 3 PCLKB 2 or 3 PCLKB 0008 9028h S12AD A/D Data Register 4 ADDR4 16 16 0008 902Ch S12AD A/D Data Register 6 ADDR6 16 16 2 or 3 PCLKB 0008 9030h S12AD A/D Data Register 8 ADDR8 16 16 2 or 3 PCLKB 0008 9032h S12AD A/D Data Register 9 ADDR9 16 16 2 or 3 PCLKB R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 38 of 108 RX110 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (8/13) Module Symbol Register Name Register Symbol Number of Bits Access Size Number of Access States 0008 9034h S12AD A/D Data Register 10 ADDR10 16 16 2 or 3 PCLKB 0008 9036h S12AD A/D Data Register 11 ADDR11 16 16 2 or 3 PCLKB 0008 9038h S12AD A/D Data Register 12 ADDR12 16 16 2 or 3 PCLKB 0008 903Ah S12AD A/D Data Register 13 ADDR13 16 16 2 or 3 PCLKB 0008 903Ch S12AD A/D Data Register 14 ADDR14 16 16 2 or 3 PCLKB 0008 903Eh S12AD A/D Data Register 15 ADDR15 16 16 2 or 3 PCLKB 0008 9060h S12AD A/D Sampling State Register 0 ADSSTR0 8 8 2 or 3 PCLKB 0008 9061h S12AD A/D Sampling State Register L ADSSTRL 8 8 2 or 3 PCLKB 2 or 3 PCLKB 0008 9070h S12AD A/D Sampling State Register T ADSSTRT 8 8 0008 9071h S12AD A/D Sampling State Register O ADSSTRO 8 8 2 or 3 PCLKB 0008 9073h S12AD A/D Sampling State Register 1 ADSSTR1 8 8 2 or 3 PCLKB 0008 9074h S12AD A/D Sampling State Register 2 ADSSTR2 8 8 2 or 3 PCLKB 0008 9075h S12AD A/D Sampling State Register 3 ADSSTR3 8 8 2 or 3 PCLKB 0008 9076h S12AD A/D Sampling State Register 4 ADSSTR4 8 8 2 or 3 PCLKB 0008 9078h S12AD A/D Sampling State Register 6 ADSSTR6 8 8 2 or 3 PCLKB 0008 A020h SCI1 Serial Mode Register SMR 8 8 2 or 3 PCLKB 0008 A021h SCI1 Bit Rate Register BRR 8 8 2 or 3 PCLKB 0008 A022h SCI1 Serial Control Register SCR 8 8 2 or 3 PCLKB 0008 A023h SCI1 Transmit Data Register TDR 8 8 2 or 3 PCLKB 0008 A024h SCI1 Serial Status Register SSR 8 8 2 or 3 PCLKB 0008 A025h SCI1 Receive Data Register RDR 8 8 2 or 3 PCLKB 0008 A026h SCI1 Smart Card Mode Register SCMR 8 8 2 or 3 PCLKB 0008 A027h SCI1 Serial Extended Mode Register SEMR 8 8 2 or 3 PCLKB 0008 A028h SCI1 Noise Filter Setting Register SNFR 8 8 2 or 3 PCLKB 0008 A029h SCI1 I2C Mode Register 1 SIMR1 8 8 2 or 3 PCLKB 0008 A02Ah SCI1 I2C Mode Register 2 SIMR2 8 8 2 or 3 PCLKB 0008 A02Bh SCI1 I2C Mode Register 3 SIMR3 8 8 2 or 3 PCLKB 0008 A02Ch SCI1 I2C Status Register SISR 8 8 2 or 3 PCLKB 0008 A02Dh SCI1 SPI Mode Register SPMR 8 8 2 or 3 PCLKB 0008 A0A0h SCI5 Serial Mode Register SMR 8 8 2 or 3 PCLKB 0008 A0A1h SCI5 Bit Rate Register BRR 8 8 2 or 3 PCLKB 0008 A0A2h SCI5 Serial Control Register SCR 8 8 2 or 3 PCLKB 0008 A0A3h SCI5 Transmit Data Register TDR 8 8 2 or 3 PCLKB 2 or 3 PCLKB 0008 A0A4h SCI5 Serial Status Register SSR 8 8 0008 A0A5h SCI5 Receive Data Register RDR 8 8 2 or 3 PCLKB 0008 A0A6h SCI5 Smart Card Mode Register SCMR 8 8 2 or 3 PCLKB 0008 A0A7h SCI5 Serial Extended Mode Register SEMR 8 8 2 or 3 PCLKB 0008 A0A8h SCI5 Noise Filter Setting Register SNFR 8 8 2 or 3 PCLKB 0008 A0A9h SCI5 I2C Mode Register 1 SIMR1 8 8 2 or 3 PCLKB 0008 A0AAh SCI5 I2C Mode Register 2 SIMR2 8 8 2 or 3 PCLKB 0008 A0ABh SCI5 I2C Mode Register 3 SIMR3 8 8 2 or 3 PCLKB 0008 A0ACh SCI5 I2C Status Register SISR 8 8 2 or 3 PCLKB 0008 A0ADh SCI5 SPI Mode Register SPMR 8 8 2 or 3 PCLKB 0008 B000h CAC CAC Control Register 0 CACR0 8 8 2 or 3 PCLKB 0008 B001h CAC CAC Control Register 1 CACR1 8 8 2 or 3 PCLKB 0008 B002h CAC CAC Control Register 2 CACR2 8 8 2 or 3 PCLKB 0008 B003h CAC CAC Interrupt Request Enable Register CAICR 8 8 2 or 3 PCLKB 0008 B004h CAC CAC Status Register CASTR 8 8 2 or 3 PCLKB 0008 B006h CAC CAC Upper-Limit Value Setting Register CAULVR 16 16 2 or 3 PCLKB 0008 B008h CAC CAC Lower-Limit Value Setting Register CALLVR 16 16 2 or 3 PCLKB 0008 B00Ah CAC CAC Counter Buffer Register CACNTBR 16 16 2 or 3 PCLKB 0008 B080h DOC DOC Control Register DOCR 8 8 2 or 3 PCLKB R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 39 of 108 RX110 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (9/13) Module Symbol Register Name Register Symbol Number of Bits Access Size Number of Access States 2 or 3 PCLKB 0008 B082h DOC DOC Data Input Register DODIR 16 16 0008 B084h DOC DOC Data Setting Register DODSR 16 16 2 or 3 PCLKB 0008 B300h SCI12 Serial Mode Register SMR 8 8 2 or 3 PCLKB 0008 B301h SCI12 Bit Rate Register BRR 8 8 2 or 3 PCLKB 2 or 3 PCLKB 0008 B302h SCI12 Serial Control Register SCR 8 8 0008 B303h SCI12 Transmit Data Register TDR 8 8 2 or 3 PCLKB 0008 B304h SCI12 Serial Status Register SSR 8 8 2 or 3 PCLKB 0008 B305h SCI12 Receive Data Register RDR 8 8 2 or 3 PCLKB 0008 B306h SCI12 Smart Card Mode Register SCMR 8 8 2 or 3 PCLKB 0008 B307h SCI12 Serial Extended Mode Register SEMR 8 8 2 or 3 PCLKB 0008 B308h SCI12 Noise Filter Setting Register SNFR 8 8 2 or 3 PCLKB 0008 B309h SCI12 I2C Mode Register 1 SIMR1 8 8 2 or 3 PCLKB 0008 B30Ah SCI12 I2C Mode Register 2 SIMR2 8 8 2 or 3 PCLKB 0008 B30Bh SCI12 I2C Mode Register 3 SIMR3 8 8 2 or 3 PCLKB 0008 B30Ch SCI12 I2C Status Register SISR 8 8 2 or 3 PCLKB 0008 B30Dh SCI12 SPI Mode Register SPMR 8 8 2 or 3 PCLKB 0008 B320h SCI12 Extended Serial Mode Enable Register ESMER 8 8 2 or 3 PCLKB 0008 B321h SCI12 Control Register 0 CR0 8 8 2 or 3 PCLKB 0008 B322h SCI12 Control Register 1 CR1 8 8 2 or 3 PCLKB 0008 B323h SCI12 Control Register 2 CR2 8 8 2 or 3 PCLKB 0008 B324h SCI12 Control Register 3 CR3 8 8 2 or 3 PCLKB 0008 B325h SCI12 Port Control Register PCR 8 8 2 or 3 PCLKB 0008 B326h SCI12 Interrupt Control Register ICR 8 8 2 or 3 PCLKB 0008 B327h SCI12 Status Register STR 8 8 2 or 3 PCLKB 0008 B328h SCI12 Status Clear Register STCR 8 8 2 or 3 PCLKB 0008 B329h SCI12 Control Field 0 Data Register CF0DR 8 8 2 or 3 PCLKB 0008 B32Ah SCI12 Control Field 0 Compare Enable Register CF0CR 8 8 2 or 3 PCLKB 0008 B32Bh SCI12 Control Field 0 Receive Data Register CF0RR 8 8 2 or 3 PCLKB 0008 B32Ch SCI12 Primary Control Field 1 Data Register PCF1DR 8 8 2 or 3 PCLKB 0008 B32Dh SCI12 Secondary Control Field 1 Data Register SCF1DR 8 8 2 or 3 PCLKB 0008 B32Eh SCI12 Control Field 1 Compare Enable Register CF1CR 8 8 2 or 3 PCLKB 0008 B32Fh SCI12 Control Field 1 Receive Data Register CF1RR 8 8 2 or 3 PCLKB 0008 B330h SCI12 Timer Control Register TCR 8 8 2 or 3 PCLKB 0008 B331h SCI12 Timer Mode Register TMR 8 8 2 or 3 PCLKB 0008 B332h SCI12 Timer Prescaler Register TPRE 8 8 2 or 3 PCLKB 0008 B333h SCI12 Timer Count Register TCNT 8 8 2 or 3 PCLKB 0008 C000h PORT0 Port Direction Register PDR 8 8 2 or 3 PCLKB 0008 C001h PORT1 Port Direction Register PDR 8 8 2 or 3 PCLKB 0008 C002h PORT2 Port Direction Register PDR 8 8 2 or 3 PCLKB 0008 C003h PORT3 Port Direction Register PDR 8 8 2 or 3 PCLKB 0008 C004h PORT4 Port Direction Register PDR 8 8 2 or 3 PCLKB 0008 C005h PORT5 Port Direction Register PDR 8 8 2 or 3 PCLKB 0008 C00Ah PORTA Port Direction Register PDR 8 8 2 or 3 PCLKB 0008 C00Bh PORTB Port Direction Register PDR 8 8 2 or 3 PCLKB 2 or 3 PCLKB 0008 C00Ch PORTC Port Direction Register PDR 8 8 0008 C00Eh PORTE Port Direction Register PDR 8 8 2 or 3 PCLKB 0008 C011h PORTH Port Direction Register PDR 8 8 2 or 3 PCLKB 0008 C012h PORTJ Port Direction Register PDR 8 8 2 or 3 PCLKB 0008 C020h PORT0 Port Output Data Register PODR 8 8 2 or 3 PCLKB 0008 C021h PORT1 Port Output Data Register PODR 8 8 2 or 3 PCLKB 0008 C022h PORT2 Port Output Data Register PODR 8 8 2 or 3 PCLKB 0008 C023h PORT3 Port Output Data Register PODR 8 8 2 or 3 PCLKB R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 40 of 108 RX110 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (10/13) Module Symbol Register Name Register Symbol Number of Bits Access Size Number of Access States 0008 C024h PORT4 Port Output Data Register PODR 8 8 2 or 3 PCLKB 0008 C025h PORT5 Port Output Data Register PODR 8 8 2 or 3 PCLKB 0008 C02Ah PORTA Port Output Data Register PODR 8 8 2 or 3 PCLKB 0008 C02Bh PORTB Port Output Data Register PODR 8 8 2 or 3 PCLKB 2 or 3 PCLKB 0008 C02Ch PORTC Port Output Data Register PODR 8 8 0008 C02Eh PORTE Port Output Data Register PODR 8 8 2 or 3 PCLKB 0008 C031h PORTH Port Output Data Register PODR 8 8 2 or 3 PCLKB 0008 C032h PORTJ Port Output Data Register PODR 8 8 2 or 3 PCLKB 0008 C040h PORT0 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 0008 C041h PORT1 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 0008 C042h PORT2 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 0008 C043h PORT3 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 0008 C044h PORT4 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 0008 C045h PORT5 Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 0008 C04Ah PORTA Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 0008 C04Bh PORTB Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 0008 C04Ch PORTC Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 0008 C04Eh PORTE Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 0008 C051h PORTH Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 0008 C052h PORTJ Port Input Data Register PIDR 8 8 3 or 4 PCLKB cycles when reading, 2 or 3 PCLKB cycles when writing 0008 C060h PORT0 Port Mode Register PMR 8 8 2 or 3 PCLKB 0008 C061h PORT1 Port Mode Register PMR 8 8 2 or 3 PCLKB 0008 C062h PORT2 Port Mode Register PMR 8 8 2 or 3 PCLKB 0008 C063h PORT3 Port Mode Register PMR 8 8 2 or 3 PCLKB 0008 C064h PORT4 Port Mode Register PMR 8 8 2 or 3 PCLKB 0008 C065h PORT5 Port Mode Register PMR 8 8 2 or 3 PCLKB 0008 C06Ah PORTA Port Mode Register PMR 8 8 2 or 3 PCLKB 0008 C06Bh PORTB Port Mode Register PMR 8 8 2 or 3 PCLKB 0008 C06Ch PORTC Port Mode Register PMR 8 8 2 or 3 PCLKB 0008 C06Eh PORTE Port Mode Register PMR 8 8 2 or 3 PCLKB 0008 C071h PORTH Port Mode Register PMR 8 8 2 or 3 PCLKB 0008 C072h PORTJ Port Mode Register PMR 8 8 2 or 3 PCLKB 0008 C083h PORT1 Open Drain Control Register 1 ODR1 8 8, 16 2 or 3 PCLKB 0008 C085h PORT2 Open Drain Control Register 1 ODR1 8 8, 16 2 or 3 PCLKB 0008 C086h PORT3 Open Drain Control Register 0 ODR0 8 8, 16 2 or 3 PCLKB 0008 C094h PORTA Open Drain Control Register 0 ODR0 8 8, 16 2 or 3 PCLKB 0008 C095h PORTA Open Drain Control Register 1 ODR1 8 8, 16 2 or 3 PCLKB 0008 C096h PORTB Open Drain Control Register 0 ODR0 8 8, 16 2 or 3 PCLKB 0008 C097h PORTB Open Drain Control Register 1 ODR1 8 8, 16 2 or 3 PCLKB 0008 C098h PORTC Open Drain Control Register 0 ODR0 8 8, 16 2 or 3 PCLKB 0008 C099h PORTC Open Drain Control Register 1 ODR1 8 8, 16 2 or 3 PCLKB 0008 C09Ch PORTE Open Drain Control Register 0 ODR0 8 8, 16 2 or 3 PCLKB 0008 C09Dh PORTE Open Drain Control Register 1 ODR1 8 8, 16 2 or 3 PCLKB 0008 C0C0h PORT0 Pull-Up Control Register PCR 8 8 2 or 3 PCLKB 0008 C0C1h PORT1 Pull-Up Control Register PCR 8 8 2 or 3 PCLKB 0008 C0C2h PORT2 Pull-Up Control Register PCR 8 8 2 or 3 PCLKB R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 41 of 108 RX110 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (11/13) Module Symbol Register Name Register Symbol Number of Bits Access Size Number of Access States 0008 C0C3h PORT3 Pull-Up Control Register PCR 8 8 2 or 3 PCLKB 0008 C0C5h PORT5 Pull-Up Control Register PCR 8 8 2 or 3 PCLKB 0008 C0CAh PORTA Pull-Up Control Register PCR 8 8 2 or 3 PCLKB 0008 C0CBh PORTB Pull-Up Control Register PCR 8 8 2 or 3 PCLKB 0008 C0CCh PORTC Pull-Up Control Register PCR 8 8 2 or 3 PCLKB 0008 C0CEh PORTE Pull-Up Control Register PCR 8 8 2 or 3 PCLKB 0008 C0D1h PORTH Pull-Up Control Register PCR 8 8 2 or 3 PCLKB 0008 C11Fh MPC Write-Protect Register PWPR 8 8 2 or 3 PCLKB 0008 C120h PORT Port Switching Register B PSRB 8 8 2 or 3 PCLKB 0008 C121h PORT Port Switching Register A PSRA 8 8 2 or 3 PCLKB 0008 C14Ch MPC P14 Pin Function Control Register P14PFS 8 8 2 or 3 PCLKB 0008 C14Dh MPC P15 Pin Function Control Register P15PFS 8 8 2 or 3 PCLKB 0008 C14Eh MPC P16 Pin Function Control Register P16PFS 8 8 2 or 3 PCLKB 0008 C14Fh MPC P17 Pin Function Control Register P17PFS 8 8 2 or 3 PCLKB 0008 C156h MPC P26 Pin Function Control Register P26PFS 8 8 2 or 3 PCLKB 0008 C157h MPC P27 Pin Function Control Register P27PFS 8 8 2 or 3 PCLKB 0008 C158h MPC P30 Pin Function Control Register P30PFS 8 8 2 or 3 PCLKB 0008 C159h MPC P31 Pin Function Control Register P31PFS 8 8 2 or 3 PCLKB 0008 C15Ah MPC P32 Pin Function Control Register P32PFS 8 8 2 or 3 PCLKB 0008 C160h MPC P40 Pin Function Control Register P40PFS 8 8 2 or 3 PCLKB 0008 C161h MPC P41 Pin Function Control Register P41PFS 8 8 2 or 3 PCLKB 0008 C162h MPC P42 Pin Function Control Register P42PFS 8 8 2 or 3 PCLKB 0008 C163h MPC P43 Pin Function Control Register P43PFS 8 8 2 or 3 PCLKB 0008 C164h MPC P44 Pin Function Control Register P44PFS 8 8 2 or 3 PCLKB 0008 C166h MPC P46 Pin Function Control Register P46PFS 8 8 2 or 3 PCLKB 0008 C190h MPC PA0 Pin Function Control Register PA0PFS 8 8 2 or 3 PCLKB 0008 C191h MPC PA1 Pin Function Control Register PA1PFS 8 8 2 or 3 PCLKB 0008 C193h MPC PA3 Pin Function Control Register PA3PFS 8 8 2 or 3 PCLKB 0008 C194h MPC PA4 Pin Function Control Register PA4PFS 8 8 2 or 3 PCLKB 0008 C196h MPC PA6 Pin Function Control Register PA6PFS 8 8 2 or 3 PCLKB 0008 C198h MPC PB0 Pin Function Control Register PB0PFS 8 8 2 or 3 PCLKB 0008 C199h MPC PB1 Pin Function Control Register PB1PFS 8 8 2 or 3 PCLKB 0008 C19Bh MPC PB3 Pin Function Control Register PB3PFS 8 8 2 or 3 PCLKB 0008 C19Dh MPC PB5 Pin Function Control Register PB5PFS 8 8 2 or 3 PCLKB 0008 C19Eh MPC PB6 Pin Function Control Register PB6PFS 8 8 2 or 3 PCLKB 0008 C19Fh MPC PB7 Pin Function Control Register PB7PFS 8 8 2 or 3 PCLKB 0008 C1A2h MPC PC2 Pin Function Control Register PC2PFS 8 8 2 or 3 PCLKB 0008 C1A3h MPC PC3 Pin Function Control Register PC3PFS 8 8 2 or 3 PCLKB 0008 C1A4h MPC PC4 Pin Function Control Register PC4PFS 8 8 2 or 3 PCLKB 0008 C1A5h MPC PC5 Pin Function Control Register PC5PFS 8 8 2 or 3 PCLKB 0008 C1A6h MPC PC6 Pin Function Control Register PC6PFS 8 8 2 or 3 PCLKB 0008 C1A7h MPC PC7 Pin Function Control Register PC7PFS 8 8 2 or 3 PCLKB 0008 C1B0h MPC PE0 Pin Function Control Register PE0PFS 8 8 2 or 3 PCLKB 0008 C1B1h MPC PE1 Pin Function Control Register PE1PFS 8 8 2 or 3 PCLKB 0008 C1B2h MPC PE2 Pin Function Control Register PE2PFS 8 8 2 or 3 PCLKB 0008 C1B3h MPC PE3 Pin Function Control Register PE3PFS 8 8 2 or 3 PCLKB 0008 C1B4h MPC PE4 Pin Function Control Register PE4PFS 8 8 2 or 3 PCLKB 0008 C1B5h MPC PE5 Pin Function Control Register PE5PFS 8 8 2 or 3 PCLKB 0008 C1B6h MPC PE6 Pin Function Control Register PE6PFS 8 8 2 or 3 PCLKB 0008 C1B7h MPC PE7 Pin Function Control Register PE7PFS 8 8 2 or 3 PCLKB 0008 C1C8h MPC PH0 Pin Function Control Register PH0PFS 8 8 2 or 3 PCLKB 0008 C1C9h MPC PH1 Pin Function Control Register PH1PFS 8 8 2 or 3 PCLKB R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 42 of 108 RX110 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (12/13) Module Symbol Register Name Register Symbol Number of Bits Access Size Number of Access States 0008 C1CAh MPC PH2 Pin Function Control Register PH2PFS 8 8 2 or 3 PCLKB 0008 C1CBh MPC PH3 Pin Function Control Register PH3PFS 8 8 2 or 3 PCLKB 0008 C1D6h MPC PJ6 Pin Function Control Register PJ6PFS 8 8 2 or 3 PCLKB 0008 C1D7h MPC PJ7 Pin Function Control Register PJ7PFS 8 8 2 or 3 PCLKB 0008 C290h SYSTEM Reset Status Register 0 RSTSR0 8 8 4 or 5 PCLKB 0008 C291h SYSTEM Reset Status Register 1 RSTSR1 8 8 4 or 5 PCLKB 0008 C293h SYSTEM Main Clock Oscillator Forced Oscillation Control Register MOFCR 8 8 4 or 5 PCLKB 0008 C297h SYSTEM Voltage Monitoring Circuit Control Register LVCMPCR 8 8 4 or 5 PCLKB 0008 C298h SYSTEM Voltage Detection Level Select Register LVDLVLR 8 8 4 or 5 PCLKB 0008 C29Ah SYSTEM Voltage Monitoring 1 Circuit Control Register 0 LVD1CR0 8 8 4 or 5 PCLKB 0008 C29Bh SYSTEM Voltage Monitoring 2 Circuit Control Register 0 LVD2CR0 8 8 4 or 5 PCLKB 0008 C400h RTC 64-Hz Counter R64CNT 8 8 2 or 3 PCLKB 0008 C402h RTC Second Counter RSECCNT 8 8 2 or 3 PCLKB 0008 C402h RTC Binary Counter 0 BCNT0 8 8 2 or 3 PCLKB 0008 C404h RTC Minute Counter RMINCNT 8 8 2 or 3 PCLKB 0008 C404h RTC Binary Counter 1 BCNT1 8 8 2 or 3 PCLKB 0008 C406h RTC Hour Counter RHRCNT 8 8 2 or 3 PCLKB 0008 C406h RTC Binary Counter 2 BCNT2 8 8 2 or 3 PCLKB 0008 C408h RTC Day-Of-Week Counter RWKCNT 8 8 2 or 3 PCLKB 0008 C408h RTC Binary Counter 3 BCNT3 8 8 2 or 3 PCLKB 0008 C40Ah RTC Date Counter RDAYCNT 8 8 2 or 3 PCLKB 0008 C40Ch RTC Month Counter RMONCNT 8 8 2 or 3 PCLKB 0008 C40Eh RTC Year Counter RYRCNT 16 16 2 or 3 PCLKB 0008 C410h RTC Second Alarm Register RSECAR 8 8 2 or 3 PCLKB 2 or 3 PCLKB 0008 C410h RTC Binary Counter 0 Alarm Register BCNT0AR 8 8 0008 C412h RTC Minute Alarm Register RMINAR 8 8 2 or 3 PCLKB 0008 C412h RTC Binary Counter 1 Alarm Register BCNT1AR 8 8 2 or 3 PCLKB 0008 C414h RTC Hour Alarm Register RHRAR 8 8 2 or 3 PCLKB 0008 C414h RTC Binary Counter 2 Alarm Register BCNT2AR 8 8 2 or 3 PCLKB 0008 C416h RTC Day-of-Week Alarm Register RWKAR 8 8 2 or 3 PCLKB 0008 C416h RTC Binary Counter 3 Alarm Register BCNT3AR 8 8 2 or 3 PCLKB 0008 C418h RTC Date Alarm Register RDAYAR 8 8 2 or 3 PCLKB 0008 C418h RTC Binary Counter 0 Alarm Enable Register BCNT0AER 8 8 2 or 3 PCLKB 0008 C41Ah RTC Month Alarm Register RMONAR 8 8 2 or 3 PCLKB 0008 C41Ah RTC Binary Counter 1 Alarm Enable Register BCNT1AER 8 8 2 or 3 PCLKB 0008 C41Ch RTC Year Alarm Register RYRAR 16 16 2 or 3 PCLKB 0008 C41Ch RTC Binary Counter 2 Alarm Enable Register BCNT2AER 16 16 2 or 3 PCLKB 0008 C41Eh RTC Year Alarm Enable Register RYRAREN 8 8 2 or 3 PCLKB 0008 C41Eh RTC Binary Counter 3 Alarm Enable Register BCNT3AER 8 8 2 or 3 PCLKB 0008 C422h RTC RTC Control Register 1 RCR1 8 8 2 or 3 PCLKB 0008 C424h RTC RTC Control Register 2 RCR2 8 8 2 or 3 PCLKB 0008 C426h RTC RTC Control Register 3 RCR3 8 8 2 or 3 PCLKB 0008 C42Eh RTC Time Error Adjustment Register RADJ 8 8 2 or 3 PCLKB 007F C0ACh TEMPS Temperature Sensor Calibration Data Register TSCDRL 8 8 1 or 2 PCLKB 007F C0ADh TEMPS Temperature Sensor Calibration Data Register TSCDRH 8 8 1 or 2 PCLKB 007F C0B0h FLASH Flash Start-Up Setting Monitor Register FSCMR 16 16 2 or 3 FCLK 007F C0B2h FLASH Flash Access Window Start Address Monitor FAWSMR 16 16 2 or 3 FCLK 007F C0B4h FLASH Flash Access Window End Address Monitor Register FAWEMR 16 16 2 or 3 FCLK 007F C0B6h FLASH Flash Initial Setting Register FISR 8 8 2 or 3 FCLK 007F C0B7h FLASH Flash Extra Area Control Register FEXCR 8 8 2 or 3 FCLK 007F C0B8h FLASH Flash Error Address Monitor Register L FEAML 16 16 2 or 3 FCLK 007F C0BAh FLASH Flash Error Address Monitor Register H FEAMH 8 8 2 or 3 FCLK R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 43 of 108 RX110 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (13/13) Module Symbol Register Name Register Symbol Number of Bits Access Size Number of Access States 2 or 3 FCLK 007F C0C0h FLASH Protection Unlock Register FPR 8 8 007F C0C1h FLASH Protection Unlock Status Register FPSR 8 8 2 or 3 FCLK 007F C0C2h FLASH Flash Read Buffer Register L FRBL 16 16 2 or 3 FCLK 007F C0C4h FLASH Flash Read Buffer Register H FRBH 16 16 2 or 3 FCLK 007F FF80h FLASH Flash P/E Mode Control Register FPMCR 8 8 2 or 3 FCLK 007F FF81h FLASH Flash Area Select Register FASR 8 8 2 or 3 FCLK 007F FF82h FLASH Flash Processing Start Address Register L FSARL 16 16 2 or 3 FCLK 007F FF84h FLASH Flash Processing Start Address Register H FSARH 8 8 2 or 3 FCLK 007F FF85h FLASH Flash Control Register FCR 8 8 2 or 3 FCLK 007F FF86h FLASH Flash Processing End Address Register L FEARL 16 16 2 or 3 FCLK 007F FF88h FLASH Flash Processing End Address Register H FEARH 8 8 2 or 3 FCLK 007F FF89h FLASH Flash Reset Register FRESETR 8 8 2 or 3 FCLK 007F FF8Ah FLASH Flash Status Register 0 FSTATR0 8 8 2 or 3 FCLK 007F FF8Bh FLASH Flash Status Register 1 FSTATR1 8 8 2 or 3 FCLK 007F FF8Ch FLASH Flash Write Buffer Register L FWBL 16 16 2 or 3 FCLK 007F FF8Eh FLASH Flash Write Buffer Register H FWBH 16 16 2 or 3 FCLK 007F FFB2h FLASH Flash P/E Mode Entry Register FENTRYR 16 16 2 or 3 FCLK Note 1. Odd addresses cannot be accessed in 16-bit units. When accessing a register in 16-bit units, access the address of the TMOCNTL register. Table 24.6 lists register allocation for 16-bit access in the User’s Manual: Hardware. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 44 of 108 RX110 Group 5. Electrical Characteristics 5. Electrical Characteristics 5.1 Absolute Maximum Ratings Table 5.1 Conditions: Absolute Maximum Ratings VSS = AVSS0 = VREFL0 = 0 V Item Power supply voltage Input voltage Symbol Value Unit VCC –0.3 to +4.6 V tolerant*1 Vin –0.3 to +6.5 V Ports P40 to P44, P46, ports PJ6, PJ7 Vin –0.3 to AVCC0 +0.3 V Ports other than above Vin –0.3 to VCC +0.3 V VREFH0 –0.3 to AVCC0 +0.3 V Ports for 5 V Reference power supply voltage Analog power supply voltage AVCC0 –0.3 to +4.6 V Analog input voltage VAN –0.3 to AVCC0 + 0.3 (when AN000 to AN004 and AN006 used) –0.3 to VCC + 0.3 (when AN008 to AN015 used) V Operating temperature*2 Topr –40 to +85 –40 to +105 °C Storage temperature Tstg –55 to +125 °C Caution: Permanent damage to the MCU may result if absolute maximum ratings are exceeded. To preclude any malfunctions due to noise interference, insert capacitors of high frequency characteristics between the VCC and VSS pins, between the AVCC0 and AVSS0 pins, and between the VREFH0 and VREFL0 pins. Place capacitors of about 0.1 μF as close as possible to every power supply pin and use the shortest and heaviest possible traces. Also, connect capacitors as stabilization capacitance. Connect the VCL pin to a VSS pin via a 4.7 μF capacitor. The capacitor must be placed close to the pin, refer to section 5.9.1, Connecting VCL Capacitor and Bypass Capacitors. Do not input signals or an I/O pull-up power supply to ports other than 5-V tolerant ports while the device is not powered. The current injection that results from input of such a signal or I/O pull-up may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. If input voltage (within the specified range from -0.3 to + 6.5V) is applied to 5-V tolerant ports, it will not cause problems such as damage to the MCU. Note 1. Ports P16, P17, PA6, and PB0 are 5 V tolerant. Note 2. The upper limit of operating temperature is 85°C or 105°C, depending on the product. For details, refer to 1.2 List of Products. Table 5.2 Recommended Operating Conditions Item Power supply voltages Analog power supply voltages Symbol Min. Typ. Max. Unit VCC*1 1.8 — 3.6 V VSS — 0 — V AVCC0*1, *2 1.8 — 3.6 V AVSS0 — 0 — V VREFH0 1.8 — AVCC0 V VREFL0 — 0 — V Note 1. Supply AVCC0 simultaneously with or after supplying VCC. Note 2. Refer to section 27.6.10, Voltage Range of Analog Power Supply Pins in the User’s Manual: Hardware to determine the AVCC0 voltage. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 45 of 108 RX110 Group 5.2 5. Electrical Characteristics DC Characteristics Table 5.3 DC Characteristics (1) Conditions: 2.7 V ≤ VCC ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Item Schmitt trigger input voltage Symbol Min. Typ. Max. Unit VIH VCC × 0.7 — 5.8 V Ports P16, P17, port PA6, port PB0 (5 V tolerant) VCC × 0.8 — 5.8 Ports P03, P05, ports P14, P15, ports P26, P27, ports P30 to P32, P35, ports P54, P55, ports PA0, PA1, PA3, PA4, ports PB1, PB3, PB5 to PB7, ports PC0 to PC7, ports PE0 to PE7, ports PH0 to PH3, PH7, RES# VCC × 0.8 — VCC + 0.3 –0.3 — VCC × 0.3 –0.3 — VCC × 0.2 VCC × 0.05 — — VCC × 0.1 — — VCC × 0.9 — VCC + 0.3 VCC × 0.8 — VCC + 0.3 AVCC0 × 0.7 — AVCC0 + 0.3 2.1 — VCC + 0.3 –0.3 — VCC × 0.1 RIIC input pin (except for SMBus, 5 V tolerant) RIIC input pin (except for SMBus) VIL Other than RIIC input pin RIIC input pin (except for SMBus) ∆VT Other than RIIC input pin Input voltage (except for Schmitt trigger input pins) MD VIH XTAL (external clock input) Ports P40 to P44, P46, ports PJ6, PJ7 RIIC input pin (SMBus) MD VIL XTAL (external clock input) –0.3 — VCC × 0.2 Ports P40 to P44, P46, ports PJ6, PJ7 –0.3 — AVCC0 × 0.3 RIIC input pin (SMBus) –0.3 — 0.8 R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Test Conditions V Page 46 of 108 RX110 Group Table 5.4 5. Electrical Characteristics DC Characteristics (2) Conditions: 1.8 V ≤ VCC < 2.7 V, 1.8 V ≤ AVCC0 < 2.7 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Item Schmitt trigger input voltage Ports P16, P17, port PA6, port PB0 (5 V tolerant) Symbol Min. Typ. Max. Unit VIH VCC × 0.8 — 5.8 V VCC × 0.8 — VCC + 0.3 Ports P03, P05, ports P14, P15, ports P26, P27, ports P30 to P32, P35, ports P54, P55, ports PA0, PA1, PA3, PA4, ports PB1, PB3, PB5 to PB7, ports PC0 to PC7, ports PE0 to PE7, ports PH0 to PH3, PH7, RES# All pins Input voltage (except for Schmitt trigger input pins) –0.3 — VCC × 0.2 All pins ∆VT VCC × 0.01 — — MD VIH VCC × 0.9 — VCC + 0.3 VCC × 0.8 — VCC + 0.3 AVCC0 × 0.7 — AVCC0 + 0.3 –0.3 — VCC × 0.1 XTAL (external clock input) Ports P40 to P44, P46, ports PJ6, PJ7 MD Table 5.5 VIL XTAL (external clock input) –0.3 — VCC × 0.2 Ports P40 to P44, P46, ports PJ6, PJ7 –0.3 — AVCC0 × 0.3 Test Conditions V DC Characteristics (3) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Item Input leakage current RES#, MD, port P35, port PH7 Three-state leakage current (off-state) Ports for 5 V tolerant Input capacitance Symbol Min. Typ. Max. Unit Iin — — 1.0 µA Vin = 0 V, VCC ITSI — — 1.0 µA Vin = 0 V, 5.8 V — — 1.0 — — 15 — — 30 Pins other than above All input pins (except for port P16, port P35) Cin Port P16, port P35 Table 5.6 Conditions: Vin = 0 V, VCC pF Vin = 0 mV, Frequency: 1 MHz, Ta = 25°C DC Characteristics (4) 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Item Input pull-up resistor Test Conditions All ports (except for port P35, port PH7) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Symbol Min. Typ. Max. Unit RU 10 20 100 kΩ Test Conditions Vin = 0 V Page 47 of 108 RX110 Group Table 5.7 Conditions: 5. Electrical Characteristics DC Characteristics (5) (1/2) 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Symbol Typ *4 Max Unit ICC 3.2 — mA ICLK = 16 MHz 2.1 — ICLK = 8 MHz 1.5 — ICLK = 32 MHz 9.6 — ICLK = 16 MHz 5.6 — Item Supply current*1 High-speed operating mode Normal operating mode No peripheral operation*2 All peripheral operation: Normal*3 Sleep mode ICLK = 8 MHz 3.5 — All peripheral operation: Max.*3 ICLK = 32 MHz — 21.6 No peripheral operation*2 ICLK = 32 MHz 1.5 — ICLK = 16 MHz 1.2 — ICLK = 8 MHz 1.0 — ICLK = 32 MHz 5.1 — ICLK = 16 MHz 3.1 — All peripheral operation: Normal*3 Deep sleep mode No peripheral operation*2 All peripheral operation: Normal*3 Middle-speed operating modes Normal operating mode No peripheral operation*5 — 1.0 — ICLK = 16 MHz 0.80 — ICLK = 8 MHz 0.70 — ICLK = 32 MHz 3.4 — ICLK = 16 MHz 2.2 — ICLK = 8 MHz 1.5 — — 1.3 — ICLK = 1 MHz 0.72 — ICLK = 12 MHz 4.2 — ICLK = 8 MHz 3.3 — ICLK = 1 MHz 1.2 — All peripheral operation: Max.*6 ICLK = 12 MHz — 10 No peripheral operation*5 ICLK = 12 MHz 1.0 — ICLK = 8 MHz 0.82 — ICLK = 1 MHz 0.65 — ICLK = 12 MHz 2.3 — ICLK = 8 MHz 1.9 — ICLK = 1 MHz 1.0 — ICLK = 12 MHz 0.8 — ICLK = 8 MHz 0.66 — ICLK = 1 MHz 0.58 — ICLK = 12 MHz 1.6 — No peripheral operation*5 All peripheral operation: Normal*6 R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 2.0 ICLK = 32 MHz 1.7 All peripheral operation: Normal*6 Deep sleep mode ICLK = 8 MHz ICLK = 8 MHz All peripheral operation: Normal*6 Sleep mode ICLK = 32 MHz ICLK = 12 MHz ICC ICLK = 8 MHz 1.5 — ICLK = 1 MHz 0.87 — Test Conditions mA Page 48 of 108 RX110 Group Table 5.7 5. Electrical Characteristics DC Characteristics (5) (2/2) 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Conditions: Item Supply current*1 Low-speed operating mode Normal operating mode Sleep mode Deep sleep mode Symbol Typ *4 Max Unit ICC 3.9 — μA No peripheral operation*7 ICLK = 32.768 kHz All peripheral operation: Normal*8, *9 ICLK = 32.768 kHz 10.4 — All peripheral operation: Max.*8, *9 ICLK = 32.768 kHz — 36 No peripheral operation*7 ICLK = 32.768 kHz 2.1 — All peripheral operation: Normal*8 ICLK = 32.768 kHz 5.6 — No peripheral operation*7 ICLK = 32.768 kHz 1.7 — All peripheral operation: Normal*8 ICLK = 32.768 kHz 3.9 — Test Conditions Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up MOSs are in the off state. Note 2. Clock supply to the peripheral functions is stopped. The clock source is HOCO. FCLK and PCLK are set to divided by 64. Note 3. Clocks are supplied to the peripheral functions. The clock source is HOCO. FCLK and PCLK are set to the same frequency as ICLK. Note 4. Values when VCC = 3.3 V. Note 5. Clock supply to the peripheral functions is stopped. The clock source is the main oscillation circuit when ICLK = 12 MHz and HOCO when ICLK = 8 or 1 MHz. FCLK and PCLK are set to divided by 64. Note 6. Clocks are supplied to the peripheral functions. The clock source is the main oscillation circuit when ICLK = 12 MHz and HOCO when ICLK = 8 or 1 MHz. FCLK and PCLK are set to the same frequency as ICLK. Note 7. Clock supply to the peripheral functions is stopped. The clock source is the sub-clock oscillator. FCLK and PCLK are set to divided by 64. Note 8. Clocks are supplied to the peripheral functions. The clock source is the sub-clock oscillator. FCLK and PCLK are set to the same frequency as ICLK. Note 9. Values when the MSTPCRA.MSTPA17 bit (12-bit A/D converter module stop bit) is set to “transition to the module stop state is made”. 18 16 Ta = 85/105°C, ICLK = 32 MHz*2 14 ICC (mA) 12 Ta = 25°C, ICLK = 32 MHz*1 10 Ta = 85/105°C, ICLK = 16 MHz*2 8 Ta = 85/105°C, ICLK = 8 MHz*2 6 Ta = 25°C, ICLK = 16 MHz*1 4 Ta = 25°C, ICLK = 8 MHz*1 2 0 1.5 2.0 2.5 3.0 3.5 4.0 VCC (V) Note 1. All peripheral operation is normal. Average value of the tested middle samples during product evaluation. Note 2. All peripheral operation is maximum. Average value of the tested upper-limit samples during product evaluation. Figure 5.1 Voltage Dependency in High-Speed Operating Mode (Reference Data) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 49 of 108 RX110 Group 5. Electrical Characteristics 8 7 Ta = 85/105°C, ICLK = 12 MHz*2 6 Ta = 85/105°C, ICLK = 8 MHz*2 ICC (mA) 5 Ta = 25°C, ICLK = 12 MHz*1 4 Ta = 25°C, ICLK = 8 MHz*1 3 Ta = 85/105°C, ICLK = 1 MHz*2 2 1 Ta = 25°C, ICLK = 1 MHz*1 0 1.5 2.0 2.5 3.0 3.5 4.0 VCC (V) Note 1. All peripheral operation is normal. Average value of the tested middle samples during product evaluation. Note 2. All peripheral operation is maximum. Average value of the tested upper-limit samples during product evaluation. Figure 5.2 Voltage Dependency in Middle-Speed Operating Mode (Reference Data) 30 25 Ta = 105°C, ICLK = 32KHz*2 ICC (µA) 20 Ta = 85°C, ICLK = 32KHz*2 15 10 Ta = 25°C, ICLK = 32KHz*1 5 0 1.5 2.0 2.5 3.0 3.5 4.0 VCC (V) Note 1. All peripheral operation is normal. Average value of the tested middle samples during product evaluation. Note 2. All peripheral operation is maximum. Average value of the tested upper-limit samples during product evaluation. Figure 5.3 Voltage Dependency in Low-Speed Operating Mode (Reference Data) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 50 of 108 RX110 Group Table 5.8 5. Electrical Characteristics DC Characteristics (6) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Symbol Typ.*3 Max. Unit ICC 0.35 0.53 μA Ta = 55°C 0.54 1.17 Ta = 85°C 1.38 5.2 Ta = 105°C 2.8 11.4 0.31 — RCR3.RTCDV[2:0] = 010b 1.09 — RCR3.RTCDV[2:0] = 100b 0.37 — Item Supply current*1 Software standby mode*2 Increment for RTC Ta = 25°C operation*4 Increment for IWDT operation Note 1. Note 2. Note 3. Note 4. Test Conditions Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state. The IWDT and LVD are stopped. VCC = 3.3 V. Includes the oscillation circuit. 100 Ta = 105°C*2 10 ICC (µA) Ta = 85°C*2 Ta = 105°C*1 Ta = 85°C*1 Ta = 55°C*2 1 Ta = 55°C*1 Ta = 25°C*2 Ta = 25°C*1 0.1 1.5 2 2.5 3 3.5 4 VCC (V) Note 1. Average value of the tested middle samples during product evaluation. Note 2. Average value of the tested upper-limit samples during product evaluation. Figure 5.4 Voltage Dependency in Software Standby Mode (Reference Data) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 51 of 108 RX110 Group 5. Electrical Characteristics 100 10 ICC (µA) *2 *1 1 0.1 –40 –20 0 20 40 60 80 100 120 Ta (°C) Note 1. Average value of the tested middle samples during product evaluation. Note 2. Average value of the tested upper-limit samples during product evaluation. Figure 5.5 Table 5.9 Temperature Dependency in Software Standby Mode (Reference Data) DC Characteristics (7) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V Item Permissible total consumption power*1 Symbol Typ. Max. Unit Pd — 300 mW — 105 Test Conditions D version (Ta = -40 to 85°C) G version (Ta = -40 to 105°C)*2 Note 1. Total power dissipated by the entire chip (including output currents). Note 2. Please contact Renesas Electronics sales office for derating under Ta = +85°C to 105°C. Derating is the systematic reduction of load for the sake of improved reliability. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 52 of 108 RX110 Group Table 5.10 5. Electrical Characteristics DC Characteristics (8) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Item Analog power supply current Symbol During A/D conversion (at high-speed conversion) Min. Typ.*2 IAVCC Waiting for A/D conversion (all units) Reference power supply current During A/D conversion (at high-speed conversion) LDV1, 2 Unit — 0.7 1.2 mA — — 0.3 μA — 25 52 μA — — 60 nA ITEMP — 75 — μA ILVD — 0.15 — μA IREFH0 Waiting for A/D conversion (all units) Temperature sensor*1 Max. Per channel Test Conditions Note 1. Current consumed by the power supply (VCC). Note 2. When VCC = AVCC0 = 3.3 V. Table 5.11 DC Characteristics (9) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Item RAM standby voltage Table 5.12 Symbol Min. Typ. Max. Unit VRAM 1.8 — — V Test Conditions DC Characteristics (10) Conditions: 0 V ≤ VCC ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Item Power-on VCC rising gradient Note: Note 1. Note 2. Note 3. Note 4. Symbol Min. Typ. Max. Unit SrVCC 0.02 — 20 ms/V During fast startup time*2 0.02 — 2 Voltage monitoring 1 reset enabled at startup*3, *4 0.02 — — At normal startup*1 Test Conditions When powering on AVCC0 and VCC, power them on at the same time or VCC first. When OFS1.(STUPLVD1REN, FASTSTUP) = 11b. When OFS1.(STUPLVD1REN, FASTSTUP) = 10b. When OFS1.STUPLVD1REN = 0. Turn on the power supply voltage according to the normal startup rising gradient because the register settings set by OFS1 are not read in boot mode. Table 5.13 DC Characteristics (11) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (3.6 V) and lower limit (1.8 V). When VCC change exceeds VCC ±10%, the allowable voltage change rising/falling gradient dt/dVCC must be met. Item Allowable ripple frequency Allowable voltage change rising/ falling gradient R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Symbol Min. Typ. Max. Unit Test Conditions fr (VCC) — — 10 kHz Figure 5.6 Vr (VCC) ≤ VCC × 0.2 — — 1 MHz Figure 5.6 Vr (VCC) ≤ VCC × 0.08 — — 10 MHz Figure 5.6 Vr (VCC) ≤ VCC × 0.06 1.0 — — ms/V When VCC change exceeds VCC ±10% dt/dVCC Page 53 of 108 RX110 Group 5. Electrical Characteristics 1/fr(VCC) VCC Figure 5.6 Table 5.14 Vr(VCC) Ripple Waveform DC Characteristics (12) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Item Permissible error of VCL pin external capacitance Note: Symbol Min. Typ. Max. Unit CVCL 1.4 4.7 7.0 μF Test Conditions The recommended capacitance is 4.7 μF. Variations in connected capacitors should be within the above range. Table 5.15 Permissible Output Currents (1) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +85°C (D version) Item Permissible output low current (average value per pin) Permissible output low current (maximum value per pin) Permissible output low current Ports P40 to P44, P46, ports PJ6, PJ7 Symbol Max. Unit IOL 0.4 mA Ports other than above 8.0 Ports P40 to P44, P46, ports PJ6, PJ7 0.4 Ports other than above 8.0 Total of ports P40 to P44, P46, ports PJ6, PJ7 IOL 30 Total of ports P14 to P17, port P32, ports P54, P55, ports PB0, PB1, PB3, PB5 to PB7, ports PC2 to PC7, ports PH0 to PH3 30 Total of ports PA0, PA1, PA3, PA4, PA6, ports PE0 to PE7 30 Total of all output pins Permissible output high current (average value per pin) 2.4 Total of ports P03, P05, ports P26, P27, ports P30, P31 Ports P40 to P44, P46, ports PJ6, PJ7 60 IOH Ports other than above –0.1 –4.0 Permissible output high current (maximum value per pin) Ports P40 to P44, P46, ports PJ6, PJ7 –0.1 Ports other than above –4.0 Permissible output high current Total of ports P40 to P44, P46, ports PJ6, PJ7 Note: IOH –0.6 Total of ports P03, P05, ports P26, P27, ports P30, P31 –10 Total of ports P14 to P17, port P32, ports P54, P55, ports PB0, PB1, PB3, PB5 to PB7, ports PC2 to PC7, ports PH0 to PH3 –15 Total of ports PA0, PA1, PA3, PA4, PA6, ports PE0 to PE7 –15 Total of all output pins –40 Do not exceed the permissible total supply current. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 54 of 108 RX110 Group Table 5.16 5. Electrical Characteristics Permissible Output Currents (2) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C (G version) Item Symbol Max. Unit IOL 0.4 mA Permissible output low current (average value per pin) Ports P40 to P44, P46, ports PJ6, PJ7 Ports other than above 8.0 Permissible output low current (maximum value per pin) Ports P40 to P44, P46, ports PJ6, PJ7 0.4 Ports other than above 8.0 Permissible output low current Total of ports P40 to P44, P46, ports PJ6, PJ7 IOL 1.6 Total of ports P03, P05, ports P26, P27, ports P30, P31 20 Total of ports P14 to P17, port P32, ports P54, P55, ports PB0, PB1, PB3, PB5 to PB7, ports PC2 to PC7, ports PH0 to PH3 20 Total of ports PA0, PA1, PA3, PA4, PA6, ports PE0 to PE7 20 Total of all output pins 40 Ports P40 to P44, P46, ports PJ6, PJ7 Permissible output high current (maximum value per pin) Ports P40 to P44, P46, ports PJ6, PJ7 –0.1 Ports other than above –4.0 Permissible output high current Total of ports P40 to P44, P46, ports PJ6, PJ7 Note: IOH –0.1 Permissible output high current (average value per pin) Ports other than above –4.0 IOH –0.6 Total of ports P03, P05, ports P26, P27, ports P30, P31 –10 Total of ports P14 to P17, port P32, ports P54, P55, ports PB0, PB1, PB3, PB5 to PB7, ports PC2 to PC7, ports PH0 to PH3 –15 Total of ports PA0, PA1, PA3, PA4, PA6, ports PE0 to PE7 –15 Total of all output pins –40 Do not exceed the permissible total supply current. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 55 of 108 RX110 Group Table 5.17 Conditions: 5. Electrical Characteristics Output Voltage (1) 2.7 V ≤ VCC ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +10°C Item Low-level output voltage All output ports (except for RIIC, ports P40 to P44, P46, ports PJ6, PJ7) Symbol Min. Max. Unit VOL — 0.6 V — 0.4 — 0.4 IOL = 0.4 mA RIIC pins — 0.4 IOL = 3.0 mA Standard mode All output ports (except for ports P40 to P44, P46, ports PJ6, PJ7) VOH Ports P40 to P44, P46, ports PJ6, PJ7 Table 5.18 Conditions: 0.6 — AVCC0 – 0.5 — IOL = 6.0 mA V IOH = –2.0 mA IOH = –0.1 mA Output Voltage (2) All output ports (except for ports P40 to P44, P46, ports PJ6, PJ7) Symbol Min. Max. Unit VOL — 0.6 V — 0.4 VOH VCC – 0.5 — AVCC0 – 0.5 — Ports P40 to P44, P46, ports PJ6, PJ7 High-level output voltage — VCC – 0.5 1.8 V ≤ VCC ≤ 2.7 V, 1.8 V ≤ AVCC0 ≤ 2.7 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Item Low-level output voltage IOL = 1.5 mA Ports P40 to P44, P46, ports PJ6, PJ7 Fast mode High-level output voltage Test Conditions IOL = 3.0 mA All output ports (except for ports P40 to P44, P46, ports PJ6, PJ7) Ports P40 to P44, P46, ports PJ6, PJ7 R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Test Conditions IOL = 1.5 mA IOL = 0.4 mA V IOH = –1.0 mA IOH = –0.1 mA Page 56 of 108 RX110 Group 5. Electrical Characteristics 5.2.1 Standard I/O Pin Output Characteristics (1) Figure 5.7 to Figure 5.10 show the characteristics of general ports (except for the RIIC output pin, ports P40 to P44, P46, ports PJ6, PJ7). IOH/IOL vs VOH/VOL 40 VCC = 3.3 V 30 VCC = 2.7 V IOH/IOL [mA] 20 VCC = 1.8 V 10 0 0 0.5 1 1.5 2 2.5 3 3.5 VCC = 1.8 V –10 VCC = 2.7 V –20 VCC = 3.3 V –30 VOH/VOL [V] VOH/VOL and IOH/IOL Voltage Characteristics of General Ports (Except for the RIIC Output Pin, Ports P40 to P44, P46, Ports PJ6, PJ7) at Ta = 25°C (Reference Data) Figure 5.7 IOH/IOL vs VOH/VOL 10 Ta = –40°C 8 Ta = 25°C Ta = 105°C 6 IOH/IOL [mA] 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 –2 Ta = 105°C –4 Ta = 25°C Ta = –40°C –6 VOH/VOL [V] Figure 5.8 VOH/VOL and IOH/IOL Temperature Characteristics of General Ports (Except for the RIIC Output Pin, Ports P40 to P44, P46, Ports PJ6, PJ7) at VCC = 1.8 V (Reference Data) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 57 of 108 RX110 Group 5. Electrical Characteristics IOH/IOL vs VOH/VOL 30 Ta = –40°C 25 Ta = 25°C 20 Ta = 105°C IOH/IOL [mA] 15 10 5 0 0 0.5 1 1.5 2 2.5 3 –5 Ta = 105°C –10 Ta = 25°C –15 Ta = –40°C –20 VOH/VOL [V] Figure 5.9 VOH/VOL and IOH/IOL Temperature Characteristics of General Ports (Except for the RIIC Output Pin, Ports P40 to P44, P46, Ports PJ6, PJ7) at VCC = 2.7 V (Reference Data) IOH/IOL vs VOH/VOL 50 Ta = –40°C 40 Ta = 25°C IOH/IOL [mA] 30 Ta = 105°C 20 10 0 0 –10 –20 0.5 1 1.5 2 2.5 3 3.5 4 Ta = 105°C Ta = 25°C Ta = –40°C –30 VOH/VOL [V] Figure 5.10 VOH/VOL and IOH/IOL Temperature Characteristics of General Ports (Except for the RIIC Output Pin, Ports P40 to P44, P46, Ports PJ6, PJ7) at VCC = 3.3 V (Reference Data) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 58 of 108 RX110 Group 5. Electrical Characteristics 5.2.2 Standard I/O Pin Output Characteristics (2) Figure 5.11 to Figure 5.13 show the characteristics of the RIIC output pin. IOL vs VOL 40 VCC = 3.3 V 35 30 VCC = 2.7 V IOL [mA] 25 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 3.5 VOH/VOL [V] Figure 5.11 VOL and IOL Voltage Characteristics of RIIC Output Pin at Ta = 25°C (Reference Data) IOL vs VOL 30 Ta = –40°C 25 Ta = 25°C Ta = 105°C IOL [mA] 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 VOL [V] Figure 5.12 VOL and IOL Temperature Characteristics of RIIC Output Pin at VCC = 2.7 V (Reference Data) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 59 of 108 RX110 Group 5. Electrical Characteristics IOL vs VOL 50 45 Ta = –40°C 40 Ta = 25°C 35 Ta = 105°C IOL [mA] 30 25 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 VOL [V] Figure 5.13 VOL and IOL Temperature Characteristics of RIIC Output Pin at VCC = 3.3 V (Reference Data) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 60 of 108 RX110 Group 5. Electrical Characteristics 5.2.3 Standard I/O Pin Output Characteristics (3) Figure 5.14 to Figure 5.17 show the characteristics ports P40 to P44, P46, ports PJ6, PJ7. IOH/IOL vs VOH/VOL 14 VCC = 3.3 V 12 10 VCC = 2.7 V IOH/IOL [mA] 8 6 4 VCC = 1.8 V 2 0 0 VCC = 1.8 V 0.5 –2 1 1.5 2 2.5 3 3.5 VCC = 2.7 V VCC = 3.3 V –4 VOH/VOL [V] VOH/VOL and IOH/IOL Voltage Characteristics of Ports P40 to P44, P46, Ports PJ6, PJ7 at Ta = 25°C (Reference Data) Figure 5.14 IOH/IOL vs VOH/VOL 4 3 Ta = –40°C 3 Ta = 25°C Ta = 105°C IOH/IOL [mA] 2 2 1 1 0 –1 –1 0 0.2 Ta = 105°C Ta = 25°C 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Ta = –40°C VOH/VOL [V] Figure 5.15 VOH/VOL and IOH/IOL Temperature Characteristics of Ports P40 to P44, P46, Ports PJ6, PJ7 at VCC = 1.8 V (Reference Data) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 61 of 108 RX110 Group 5. Electrical Characteristics IOH/IOL vs VOH/VOL 10 Ta = –40°C 8 Ta = 25°C Ta = 105°C IOH/IOL [mA] 6 4 2 0 0 Ta = 105°C –2 0.5 1 1.5 2 2.5 3 Ta = 25°C Ta = –40°C –4 VOH/VOL [V] Figure 5.16 VOH/VOL and IOH/IOL Temperature Characteristics of Ports P40 to P44, P46, Ports PJ6, PJ7 at VCC = 2.7 V (Reference Data) IOH/IOL vs VOH/VOL 16 14 Ta = –40°C 12 Ta = 25°C Ta = 105°C 10 IOH/IOL [mA] 8 6 4 2 0 –2 0 Ta = 105°C 0.5 Ta = 25°C –4 1 1.5 2 2.5 3 3.5 4 Ta = –40°C VOH/VOL [V] Figure 5.17 VOH/VOL and IOH/IOL Temperature Characteristics of Ports P40 to P44, P46, Ports PJ6, PJ7 at VCC = 3.3 V (Reference Data) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 62 of 108 RX110 Group 5.3 5. Electrical Characteristics AC Characteristics 5.3.1 Table 5.19 Conditions: Clock Timing Operation Frequency Value (High-Speed Operating Mode) 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C VCC Item Maximum operating frequency Symbol fmax System clock (ICLK) FlashIF clock (FCLK)*1, *2 Unit 1.8 to 2.4 V 2.4 to 2.7 V 2.7 to 3.6 V 8 16 32 8 16 32 Peripheral module clock (PCLKB) 8 16 32 Peripheral module clock (PCLKD)*3 8 16 32 MHz Note 1. The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When using FCLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note 2. The frequency accuracy of FCLK should be ±3.5%. Confirm the frequency accuracy of the clock source. Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the A/D converter is in use. Table 5.20 Operation Frequency Value (Middle-Speed Operating Mode) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C VCC Item Maximum operating frequency Symbol System clock (ICLK) 2.4 to 2.7 V 2.7 to 3.6 V 8 12 12 FlashIF clock (FCLK)*1, *2 8 12 12 Peripheral module clock (PCLKB) 8 12 12 8 12 12 Peripheral module clock fmax Unit 1.8 to 2.4 V (PCLKD)*3 MHz Note 1. The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When using FCLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note 2. The frequency accuracy of FCLK should be ±3.5%. Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the A/D converter is in use. Table 5.21 Operation Frequency Value (Low-Speed Operating Mode) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Item Maximum operating frequency VCC Symbol System clock (ICLK) Unit 1.8 to 2.4 V fmax 2.4 to 2.7 V 32.768 FlashIF clock (FCLK)*1 32.768 Peripheral module clock (PCLKB) 32.768 Peripheral module clock (PCLKD)*2 32.768 2.7 to 3.6 V kHz Note 1. Programming and erasing the flash memory is impossible. Note 2. The A/D converter cannot be used. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 63 of 108 RX110 Group Table 5.22 5. Electrical Characteristics Clock Timing Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Item Symbol XTAL external clock input cycle time tXcyc Min. Typ. Max. 50 — — Unit ns — ns Test Conditions Figure 5.18 XTAL external clock input high pulse width tXH 20 — XTAL external clock input low pulse width tXL 20 — — ns XTAL external clock rising time tXr — — 5 ns tXf — — 5 ns tEXWT 0.5 — — µs fMAIN 1 — 20 MHz 1 — 8 tMAINOSC — 3 — tMAINOSC — 50 LOCO clock oscillation frequency fLOCO 3.44 4.0 4.56 MHz LOCO clock oscillation stabilization time tLOCO — — 0.5 µs IWDT-dedicated clock oscillation frequency fILOCO 12.75 15 17.25 kHz IWDT-dedicated clock oscillation stabilization time tILOCO — — 50 μs HOCO clock oscillation frequency fHOCO 31.52 32 32.48 MHz 31.68 32 32.32 Ta = –20 to 85°C 31.36 32 32.64 Ta = –40 to 105°C XTAL external clock falling time XTAL external clock input wait time*1 2.4 ≤ VCC ≤ 3.6 Main clock oscillator oscillation frequency 1.8 ≤ VCC < 2.4 Main clock oscillation stabilization time (crystal)*2 Main clock oscillation stabilization time (ceramic resonator)*2 HOCO clock oscillation stabilization time Sub-clock oscillator oscillation ms µs tHOCO2 — — 56 µs frequency*4 fSUB — 32.768 — kHz time*3 tSUBOSC — 0.5 — s Sub-clock oscillation stabilization Figure 5.20 Figure 5.21 Figure 5.19 Ta = –40 to 85°C Figure 5.23 Figure 5.24 Note 1. Time until the clock can be used after the main clock oscillator stop bit (MOSCCR.MOSTP) is set to 0 (operating) when the external clock is stable. Note 2. Reference values when an 8-MHz oscillator is used. When specifying the main clock oscillator stabilization time, set the MOSCWTCR register with a stabilization time value that is equal to or greater than the oscillator-manufacturer-recommended value. After changing the setting of the MOSCCR.MOSTP bit so that the main clock oscillator operates, read the OSCOVFSR.MOOVF flag to confirm that is has become 1, and then start using the main clock. Note 3. After changing the setting of the SOSCCR.SOSTP bit or RCR3.RTCEN bit so that the sub-clock oscillator operates, only start using the sub-clock after the sub-clock oscillation stabilization wait time that is equal to or greater than the oscillatormanufacturer-recommended value has elapsed. Reference value when a 32.768-kHz resonator is used. Note 4. Only 32.768 kHz can be used. tEXcyc tEXH XTAL external clock input VCC × 0.5 tEXr Figure 5.18 tEXL tEXf XTAL External Clock Input Timing R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 64 of 108 RX110 Group 5. Electrical Characteristics ILOCOCR.ILCSTP tILOCO IWDT-dedicated clock oscillator output Figure 5.19 IWDT-Dedicated Clock Oscillation Start Timing MOSCCR.MOSTP tMAINOSC Main clock oscillator output Figure 5.20 Main Clock Oscillation Start Timing LOCOCR.LCSTP tLOCO LOCO clock oscillator output Figure 5.21 LOCO Clock Oscillation Start Timing RES# Internal reset tRESWT OFS1.HOCOEN HOCO clock Figure 5.22 HOCO Clock Oscillation Start Timing (After Reset is Canceled by Setting OFS1.HOCOEN Bit to 0) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 65 of 108 RX110 Group 5. Electrical Characteristics HOCOCR.HCSTP tHOCO HOCO clock Figure 5.23 HOCO Clock Oscillation Start Timing (Oscillation is Started by Setting HOCOCR.HCSTP Bit) SOSCCR.SOSTP tSUBOSC Sub-clock oscillator output Figure 5.24 Sub-Clock Oscillation Start Timing R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 66 of 108 RX110 Group 5. Electrical Characteristics 5.3.2 Reset Timing Table 5.23 Reset Timing Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Item RES# pulse width Symbol Min. Typ. Max. Unit tRESWP 3 — — ms Figure 5.25 Other than above tRESW 30 — — μs Figure 5.26 At normal startup*1 tRESWT — 8.5 — ms Figure 5.25 At power-on Wait time after RES# cancellation (at power-on) Test Conditions tRESWT — 560 — μs Wait time after RES# cancellation (during powered-on state) tRESWT — 114 — μs Figure 5.26 Independent watchdog timer reset period tRESWIW — 1 — IWDT clock cycle Figure 5.27 tRESWSW — 1 — ICLK cycle tRESW2 — 300 — μs tRESW2 — 168 — μs During fast startup time*2 Software reset period Wait time after independent watchdog timer reset cancellation*3 Wait time after software reset cancellation Note 1. When OFS1.(STUPLVD1REN, FASTSTUP) = 11b. Note 2. When OFS1.(STUPLVD1REN, FASTSTUP) ≠ 11b. Note 3. When IWDTCR.CKS[3:0] = 0000b. VCC RES# tRESWP Internal reset tRESWT Figure 5.25 Reset Input Timing at Power-On tRESW RES# Internal reset tRESWT Figure 5.26 Reset Input Timing (1) tRESWIW, tRESWSW Independent watchdog timer reset Software reset Internal reset tRESWT2 Figure 5.27 Reset Input Timing (2) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 67 of 108 RX110 Group 5. Electrical Characteristics 5.3.3 Timing of Recovery from Low Power Consumption Modes Table 5.24 Timing of Recovery from Low Power Consumption Modes (1) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Item Recovery time from software standby mode*1 High-speed mode Symbol Min. Typ. Max. Unit Test Conditions Figure 5.28 Crystal connected to main clock oscillator Main clock oscillator operating*2 tSBYMC — 2 3 ms External clock input to main clock oscillator Main clock oscillator operating*3 tSBYEX — 35 50 μs Sub-clock oscillator operating tSBYSC — 650 800 μs HOCO clock oscillator operating*4 tSBYHO — 40 55 μs LOCO clock oscillator operating tSBYLO — 40 55 μs Note: When the division ratios of PCLKB, PCLKD, FCLK, and ICLK are all set to 1. Note 1. The recovery time varies depending on the state of each oscillator when the WAIT instruction is executed. The recovery time when multiple oscillators are operating varies depending on the operating state of the oscillators that are not selected as the system clock source. This applies when only the oscillator listed in each item is operating and the other oscillators are stopped. Note 2. When the frequency of the crystal is 20 MHz. When the main clock oscillator wait control register (MOSCWTCR) is set to 04h. Note 3. When the frequency of the external clock is 20 MHz. When the main clock oscillator wait control register (MOSCWTCR) is set to 00h. Note 4. When the frequency of HOCO is 32 MHz. When the high-speed clock oscillator wait control register (HOCOWTCR) is set to 05h. Table 5.25 Timing of Recovery from Low Power Consumption Modes (2) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Item Recovery time from software standby mode*1 Middle-speed mode Symbol Min. Typ. Max. Unit Test Conditions Figure 5.28 Crystal connected to main clock oscillator Main clock oscillator operating*2 tSBYMC — 2 3 ms External clock input to main clock oscillator Main clock oscillator operating*3 tSBYEX — 3 4 μs tSBYSC — 600 750 μs tSBYHO — 40 50 μs tSBYLO — 4.8 7 μs Sub-clock oscillator operating HOCO clock oscillator operating*4 LOCO clock oscillator operating Note: When the division ratios of PCLKB, PCLKD, FCLK, and ICLK are all set to 1. Note 1. The recovery time varies depending on the state of each oscillator when the WAIT instruction is executed. The recovery time when multiple oscillators are operating varies depending on the operating state of the oscillators that are not selected as the system clock source. This applies when only the oscillator listed in each item is operating and the other oscillators are stopped. Note 2. When the frequency of the crystal is 12 MHz. When the main clock oscillator wait control register (MOSCWTCR) is set to 04h. Note 3. When the frequency of the external clock is 12 MHz. When the main clock oscillator wait control register (MOSCWTCR) is set to 00h. Note 4. When the frequency of HOCO is 8 MHz. When the high-speed clock oscillator wait control register (HOCOWTCR) is set to 05h. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 68 of 108 RX110 Group Table 5.26 5. Electrical Characteristics Timing of Recovery from Low Power Consumption Modes (3) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Item Recovery time from software standby mode*1 Low-speed mode Sub-clock oscillator operating Symbol Min. Typ. Max. Unit tSBYSC — 600 750 μs Test Conditions Figure 5.28 Note: When the division ratios of PCLKB, PCLKD, FCLK, and ICLK are all set to 1. Note 1. The sub-clock continues oscillating in software standby mode during low-speed mode. Oscillator ICLK IRQ Software standby mode tSBYMC, tSBYPC, tSBYEX, tSBYPE, tSBYHO, tSBYLO Oscillator ICLK IRQ Software standby mode tSBYSC Figure 5.28 Software Standby Mode Cancellation Timing R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 69 of 108 RX110 Group Table 5.27 5. Electrical Characteristics Timing of Recovery from Low Power Consumption Modes (4) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Item Recovery time from deep sleep mode*1 Note: Note 1. Note 2. Note 3. Note 4. Symbol Min. Typ. Max. Unit High-speed mode*2 tDSLP — 2 3.5 μs Middle-speed mode*3 tDSLP — 3 4 μs Low-speed mode*4 tDSLP — 400 500 μs Test Conditions When the division ratios of PCLKB, PCLKD, FCLK, and ICLK are all set to 1. Oscillators continue oscillating in deep sleep mode. When the frequency of the system clock is 32 MHz. When the frequency of the system clock is 12 MHz. When the frequency of the system clock is 32.768 kHz. Oscillator ICLK IRQ Deep sleep mode tDSLP Figure 5.29 Table 5.28 Deep Sleep Mode Cancellation Timing Timing of Recovery from Low Power Consumption Modes (5) Operating Mode Transition Time Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = -40 to +105°C Mode before Transition Mode after Transition ICLK Frequency Transition Time Min. Typ. Max. Unit High-speed operating mode Middle-speed operating mode 8 MHz — 10 — μs Middle-speed operating mode High-speed operating mode 8 MHz — 37.5 — μs Low-speed operating mode Middle-speed operating mode, high-speed operating mode 32.768 kHz — 213.62 — μs Middle-speed operating mode, high-speed operating mode Low-speed operating mode 32.768 kHz — 183.11 — μs Note: When the division ratios of PCLKB, PCLKD, FCLK, and ICLK are all set to 1. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 70 of 108 RX110 Group 5. Electrical Characteristics 5.3.4 Control Signal Timing Table 5.29 Control Signal Timing Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Item NMI pulse width IRQ pulse width Symbol Min. Typ. Max. Unit tNMIW 200 — — ns tPcyc × 2*1 — — 200 — — tNMICK × 3.5*2 — — 200 — — tIRQW tPcyc × 2*1 — — 200 — — tIRQCK × 3.5*3 — — Test Conditions NMI digital filter disabled (NMIFLTE.NFLTEN = 0) NMI digital filter enabled (NMIFLTE.NFLTEN = 1) ns IRQ digital filter disabled (IRQFLTE0.FLTENi = 0) IRQ digital filter enabled (IRQFLTE0.FLTENi = 1) tPcyc × 2 ≤ 200 ns tPcyc × 2 > 200 ns tNMICK × 3 ≤ 200 ns tNMICK × 3 > 200 ns tPcyc × 2 ≤ 200 ns tPcyc × 2 > 200 ns tIRQCK × 3 ≤ 200 ns tIRQCK × 3 > 200 ns Note: 200 ns minimum in software standby mode. Note 1. tPcyc indicates the cycle of PCLKB. Note 2. tNMICK indicates the cycle of the NMI digital filter sampling clock. Note 3. tIRQCK indicates the cycle of the IRQi digital filter sampling clock (i = 0 to 7). NMI tNMIW Figure 5.30 NMI Interrupt Input Timing IRQ tIRQW Figure 5.31 IRQ Interrupt Input Timing R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 71 of 108 RX110 Group 5. Electrical Characteristics 5.3.5 Timing of On-Chip Peripheral Modules Table 5.30 Timing of On-Chip Peripheral Modules (1) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Item I/O ports Input data pulse width MTU2 Input capture input pulse width Single-edge setting Min. Max. Unit*1 tPRW 1.5 — tPcyc Figure 5.32 1.5 — tPcyc Figure 5.33 2.5 — tPcyc Figure 5.34 tPcyc Figure 5.35 tTICW Both-edge setting Timer clock pulse width Single-edge setting Both-edge setting tTCKWH, tTCKWL Phase counting mode SCI — — 2.5 — 4 — 6 — Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr — 20 ns Input clock fall time tSCKf — 20 ns tScyc 16 — tPcyc 4 — Asynchronous Clock synchronous Output clock cycle Asynchronous Clock synchronous Output clock pulse width tSCKW 0.4 0.6 tScyc Output clock rise time tSCKr — 20 ns tSCKf — 20 ns tTXD — 40 ns Output clock fall time Transmit data delay time (master) Clock synchronous Transmit data delay time (slave) Clock synchronous Receive data setup time (master) Clock synchronous Receive data setup time (slave) Clock synchronous Receive data hold time Clock synchronous A/D converter Trigger input pulse width CAC CACREF input pulse width 2.7 V or above — 65 ns 1.8 V or above — 100 ns 2.7 V or above 65 — ns 90 — ns 40 — ns tRXH 40 — ns tTRGW 1.5 — tPcyc tCACREF 4.5 tcac + 3 tPcyc — ns — ns — ns — ns 15 ns tRXS 1.8 V or above tPcyc ≤ tcac*2 tPcyc > tcac*2 CLKOUT 1.5 2.5 tScyc Input clock cycle CLKOUT pin output cycle*4 VCC = 2.7 V or above VCC = 2.7 V or above tCcyc VCC = 2.7 V or above tCH VCC = 2.7 V or above 125 35 70 tCL VCC = 1.8 V or above CLKOUT pin output rise time 35 70 tCr — VCC = 1.8 V or above CLKOUT pin output fall time VCC = 2.7 V or above VCC = 1.8 V or above Figure 5.37 250 VCC = 1.8 V or above CLKOUT pin low pulse width*3 Figure 5.36 C = 30 pF 5 tcac + 6.5 tPcyc VCC = 1.8 V or above CLKOUT pin high pulse width*3 Test Conditions Symbol 30 tCf — 15 ns 30 Note 1. tPcyc: PCLK cycle Note 2. tcac: CAC count clock source cycle Note 3. When the LOCO is selected as the clock output source (CKOCR.CKOSEL[2:0] bits = 000b), set the clock output division ratio selection to divided by 2 (CKOCR.CKODIV[2:0] bits = 001b). Note 4. When the XTAL external clock input or an oscillator is used with divided by 1 (CKOCR.CKOSEL[2:0] bits = 010b and CKOCR.CKODIV[2:0] bits = 000b) to output from CLKOUT, the above should be satisfied with an input duty cycle of 45 to 55%. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 72 of 108 RX110 Group Table 5.31 5. Electrical Characteristics Timing of On-Chip Peripheral Modules (2) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C, C = 30 pF Item RSPI RSPCK clock cycle Master Symbol Min. Max. Unit Test Conditions tSPcyc 2 4096 Figure 5.39 8 4096 tPcyc *1 (tSPcyc – tSPCKr – tSPCKf)/2 – 3 — (tSPcyc – tSPCKr – tSPCKf)/2 — (tSPcyc – tSPCKr– tSPCKf)/2 – 3 — (tSPcyc – tSPCKr – tSPCKf)/2 — Slave RSPCK clock high pulse width Master tSPCKWH Slave RSPCK clock low pulse width Master tSPCKWL Slave RSPCK clock rise/fall time Output Master tSPCKr, tSPCKf — 10 — 15 — 1 μs 2.7 V or above tSU 10 — ns 1.8 V or above Slave Data input hold time Master Data output delay time Master — RSPCK set to PCLKB divided by 2 tHF 0 — tH 20 + 2 × tPcyc — Data output hold time Master 2.7 V or above MOSI and MISO rise/fall time — ns tPcyc tLAG –30 + N*3 × tSPcyc — ns 2 — tPcyc tOD — 14 ns 1.8 V or above — 30 2.7 V or above — 3 × tPcyc + 65 1.8 V or above — 3 × tPcyc +105 0 — –20 — 2.7 V or above tOH 1.8 V or above Master tTD Slave Output 2.7 V or above tDr, tDf 1.8 V or above Output Input Slave access time 2.7 V or above 2.7 V or above 1.8 V or above — 8 × tSPcyc + 2 × tPcyc 4 × tPcyc — — 10 — 20 ns ns 1 μs tSSLr, tSSLf — 20 ns — 1 μs tSA — 6 tPcyc — 7 — 5 — 6 1.8 V or above Slave output release time 0 tSPcyc + 2 × tPcyc ns — Input SSL rise/fall time × tSPcyc tREL Figure 5.40 to Figure 5.45 ns — Slave Successive transmission delay time –30 + N*2 ns 2 tLEAD Slave Slave — tPcyc Master Master — tH Slave SSL hold time 30 25 – tPcyc RSPCK set to a division ratio other than PCLKB divided by 2 Slave SSL setup time ns 1.8 V or above 2.7 V or above Input Data input setup time ns Figure 5.44, Figure 5.45 tPcyc Note 1. tPcyc: PCLK cycle Note 2. N: An integer from 1 to 8 that can be set by the RSPI clock delay register (SPCKD) Note 3. N: An integer from 1 to 8 that can be set by the RSPI slave select negation delay register (SSLND) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 73 of 108 RX110 Group Table 5.32 5. Electrical Characteristics Timing of On-Chip Peripheral Modules (3) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C, C = 30 pF Item Simple SPI SCK clock cycle output (master) Symbol Min. Max. Unit*1 tSPcyc 4 65536 tPcyc 6 65536 tSPCKWH 0.4 0.6 tSPcyc tSPCKWL 0.4 0.6 tSPcyc tSPCKr, tSPCKf — 20 ns ns SCK clock cycle input (slave) SCK clock high pulse width SCK clock low pulse width SCK clock rise/fall time Data input setup time (master) 2.7 V or above tSU 1.8 V or above Data input setup time (slave) 65 — 95 — 40 — Data input hold time tH 40 — ns SS input setup time tLEAD 3 — tPcyc SS input hold time tLAG 3 — tPcyc Data output delay time (master) tOD — 40 ns 2.7 V or above — 65 1.8 V or above — 85 Data output delay time (slave) Data output hold time (master) 2.7 V or above tOH 1.8 V or above Data output hold time (slave) Data rise/fall time SS input rise/fall time –10 — –20 — –10 — tDr, tDf — 20 Test Conditions Figure 5.39 Figure 5.40, Figure 5.42 ns ns tSSLr, tSSLf — 20 ns Slave access time tSA — 6 tPcyc Slave output release time tREL — 6 tPcyc Figure 5.44, Figure 5.45 Note 1. tPcyc: PCLK cycle R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 74 of 108 RX110 Group Table 5.33 5. Electrical Characteristics Timing of On-Chip Peripheral Modules (4) Conditions: 2.7 V ≤ VCC ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, fPCLKB ≤ 32 MHz, Ta = –40 to +105°C Symbol Min.*1 Max. SCL0 input cycle time tSCL 6 (12) × tIICcyc + 1300 — ns SCL0 input high pulse width tSCLH 3 (6) × tIICcyc + 300 — ns SCL0 input low pulse width tSCLL 3 (6) × tIICcyc + 300 — ns SCL0, SDA0 input rise time tSr — 1000 ns SCL0, SDA0 input fall time tSf — 300 ns Item RIIC (Standard mode, SMBus) SCL0, SDA0 input spike pulse removal time tSP 0 1 (4) × tIICcyc ns SDA0 input bus free time tBUF 3 (6) × tIICcyc + 300 — ns START condition input hold time tSTAH tIICcyc + 300 — ns Repeated START condition input setup time tSTAS 1000 — ns STOP condition input setup time tSTOS 1000 — ns Data input setup time tSDAS tIICcyc + 50 — ns Data input hold time tSDAH 0 — ns SCL0, SDA0 capacitive load RIIC (Fast mode) Unit Test Conditions Cb — 400 pF SCL0 input cycle time tSCL 6 (12) × tIICcyc + 600 — ns SCL0 input high pulse width tSCLH 3 (6) × tIICcyc + 300 — ns SCL0 input low pulse width tSCLL 3 (6) × tIICcyc + 300 — ns SCL0, SDA0 input rise time tSr —*2 300 ns SCL0, SDA0 input fall time tSf —*2 300 ns SCL0, SDA0 input spike pulse removal time tSP 0 1 (4) × tIICcyc ns SDA0 input bus free time tBUF 3 (6) × tIICcyc + 300 — ns START condition input hold time tSTAH tIICcyc + 300 — ns Repeated START condition input setup time tSTAS 300 — ns STOP condition input setup time tSTOS 300 — ns Data input setup time tSDAS tIICcyc + 50 — ns Data input hold time tSDAH 0 — ns Cb — 400 pF SCL0, SDA0 capacitive load Figure 5.46 Figure 5.46 Note: tIICcyc: RIIC internal reference count clock (IICφ) cycle Note 1. The value in parentheses is used when the ICMR3.NF[1:0] bits are set to 11b while a digital filter is enabled with the ICFER.NFE bit = 1. Note 2. The minimum tsr and tsf specifications for fast mode are not set. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 75 of 108 RX110 Group Table 5.34 5. Electrical Characteristics Timing of On-Chip Peripheral Modules (5) Conditions: 2.7 V ≤ VCC ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, fPCLKB ≤ 32 MHz, Ta = –40 to +105°C Item Simple I2C SDA0 input rise time (Standard mode) SDA0 input fall time Min. Max. Unit tSr — 1000 ns tSf — 300 ns tSP 0 4 × tpcyc*1 ns Data input setup time tSDAS 250 — ns Data input hold time SDA0 input spike pulse removal time Simple I2C (Fast mode) Symbol tSDAH 0 — ns SCL0, SDA0 capacitive load Cb — 400 pF SCL0, SDA0 input rise time tSr — 300 ns SCL0, SDA0 input fall time tSf — 300 ns SCL0, SDA0 input spike pulse removal time tSP 0 4 × tpcyc*1 ns Data input setup time tSDAS 100 — ns Data input hold time tSDAH 0 — ns Cb — 400 pF SCL0, SDA0 capacitive load Test Conditions Figure 5.46 Figure 5.46 Note: tPcyc: PCLK cycle Note 1. This applies when the SMR.CKS[1:0] bits = 00b and the SNFR.NFCS[2:0] bits = 010b while the SNFR.NFE bit = 1 and the digital filter is enabled. PCLK Port tPRW Figure 5.32 I/O Port Input Timing PCLK Output compare output Input capture input Figure 5.33 tTICW MTU2 Input/Output Timing R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 76 of 108 RX110 Group 5. Electrical Characteristics PCLK MTCLKA to MTCLKH tTCKWL Figure 5.34 tTCKWH MTU2 Clock Input Timing tSCKW tSCKr tSCKf SCKn (n = 1, 5, 12) tScyc Figure 5.35 SCK Clock Input Timing SCKn tTXD TXDn tRXS tRXH RXDn (n = 1, 5, 12) Figure 5.36 SCI Input/Output Timing: Clock Synchronous Mode R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 77 of 108 RX110 Group 5. Electrical Characteristics PCLK ADTRG0# tTRGW Figure 5.37 A/D Converter External Trigger Input Timing tCcyc tCH tCf CLKOUT pin output tCL tCr Test conditions: VOH = VCC × 0.7, VOL = VCC × 0.3, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF Figure 5.38 CLKOUT Output Timing RSPI Simple SPI RSPCKA Master select output SCKn Master select output tSPCKr tSPCKWH VOH VOH VOL tSPCKf VOH VOH VOL tSPCKWL VOL tSPcyc tSPCKr tSPCKWH VIH RSPCKA Slave select input SCKn Slave select input VIH VIL (n = 1, 5, 12) tSPCKf VIH VIL tSPCKWL VIH VIL tSPcyc VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC Figure 5.39 RSPI Clock Timing and Simple SPI Clock Timing R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 78 of 108 RX110 Group RSPI 5. Electrical Characteristics Simple SPI tTD SSLA0 to SSLA3 output tLEAD RSPCKA CPOL = 0 output SCKn CKPOL = 0 output RSPCKA CPOL = 1 output SCKn CKPOL = 1 output tSSLr, tSSLf tSU MISOA input tLAG SMISOn input tH MSB IN DATA tDr, tDf MOSIA output SMOSIn output LSB IN tOH MSB OUT MSB IN tOD DATA LSB OUT IDLE MSB OUT (n = 1, 5, 12) Figure 5.40 RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKB Set to Division Ratio Other Than Divided by 2) and Simple SPI Timing (Master, CKPH = 1) tTD SSLA0 to SSLA3 output tLEAD tLAG tSSLr, tSSLf RSPCKA CPOL = 0 output RSPCKA CPOL = 1 output tSU MISOA input tHF MSB IN tDr, tDf MOSIA output Figure 5.41 tHF tOH MSB OUT LSB IN DATA MSB IN tOD DATA LSB OUT IDLE MSB OUT RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKB Set to Divided by 2) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 79 of 108 RX110 Group RSPI 5. Electrical Characteristics Simple SPI tTD SSLA0 to SSLA3 output tLEAD RSPCKA CPOL = 0 output SCKn CKPOL = 1 output RSPCKA CPOL = 1 output SCKn CKPOL = 0 output tLAG tSSLr, tSSLf tSU MISOA input SMISOn input tH MSB IN DATA tOH MOSIA output SMOSIn output LSB IN tOD MSB OUT MSB IN tDr, tDf DATA LSB OUT IDLE MSB OUT (n = 1, 5, 12) Figure 5.42 RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKB Set to Division Ratio Other Than Divided by 2) and Simple SPI Timing (Master, CKPH = 0) tTD SSLA0 to SSLA3 output tLEAD tLAG tSSLr, tSSLf RSPCKA CPOL = 0 output RSPCKA CPOL = 1 output tSU MISOA input tHF MSB IN tOH MOSIA output Figure 5.43 tH DATA LSB IN tOD MSB OUT MSB IN tDr, tDf DATA LSB OUT IDLE MSB OUT RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKB Set to Divided by 2) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 80 of 108 RX110 Group 5. Electrical Characteristics RSPI Simple SPI SSLA0 input SSn# input tTD tLEAD RSPCKA CPOL = 0 input SCKn CKPOL = 0 input RSPCKA CPOL = 1 input SCKn CKPOL = 1 input tLAG tSA MISOA output tOH SMISOn output MSB OUT tSU MOSIA input tOD SMOSIn input tREL DATA LSB OUT tH MSB IN MSB OUT tDr, tDf MSB IN DATA LSB IN MSB IN (n = 1, 5, 12) Figure 5.44 RSPI Timing (Slave, CPHA = 0) and Simple SPI Timing (Slave, CKPH = 1) RSPI Simple SPI SSLA0 input SSn# input tTD tLEAD RSPCKA CPOL = 0 input SCKn CKPOL = 1 input RSPCKA CPOL = 1 input SCKn CKPOL = 0 input MISOA output SMISOn output tSA tLAG tOH tOD LSB OUT (Last data) MSB OUT tSU MOSIA input SMOSIn input tREL DATA tH MSB IN LSB OUT MSB OUT tDr, tDf DATA LSB IN MSB IN (n = 1, 5, 12) Figure 5.45 RSPI Timing (Slave, CPHA = 1) and Simple SPI Timing (Slave, CKPH = 0) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 81 of 108 RX110 Group 5. Electrical Characteristics VIH SDA0 VIL tBUF tSCLH tSTAS tSTAH tSTOS tSP SCL0 P*1 tSCLL tSr tSf tSCL tSDAS tSDAH Note 1. S, P, and Sr indicate the following conditions, respectively. S: START condition P: STOP condition Sr: Repeated START condition Figure 5.46 P*1 Sr*1 S*1 Test conditions VIH = VCC × 0.7, VIL = VCC × 0.3 RIIC Bus Interface Input/Output Timing and Simple I2C Bus Interface Input/Output Timing R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 82 of 108 RX110 Group 5.4 5. Electrical Characteristics A/D Conversion Characteristics Table 5.35 A/D Conversion Characteristics (1) Conditions: 2.7 V ≤ VCC ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C Item Min. Typ. Max. Unit Test Conditions Frequency 4 — 32 MHz Resolution — — 12 Bit 1.031 (0.313)*2 — — µs 1.375 (0.641)*2 — — Analog input effective range 0 — VREFH0 V Offset error — ±0.5 ±4.5 LSB High-precision channel PJ6PFS.ASEL bit = 1 PJ7PFS.ASEL bit = 1 ±6.0 LSB Other than above Full-scale error — ±0.75 ±4.5 LSB High-precision channel PJ6PFS.ASEL bit = 1 PJ7PFS.ASEL bit = 1 ±6.0 LSB Other than above time*1 Conversion (Operation at PCLKD = 32 MHz) Permissible signal source impedance (Max.) = 0.3 kΩ High-precision channel ADCSR.ADHSC bit = 1 ADSSTRn.SST[7:0] bits = 09h Normal-precision channel ADCSR.ADHSC bit = 1 ADSSTRn.SST[7:0] bits = 14h Quantization error — ±0.5 — LSB Absolute accuracy — ±1.25 ±5.0 LSB High-precision channel PJ6PFS.ASEL bit = 1 PJ7PFS.ASEL bit = 1 ±8.0 LSB Other than above DNL differential nonlinearity error — ±1.0 — LSB INL integral nonlinearity error — ±1.0 ±3.0 LSB Note: The characteristics apply when no pin functions other than A/D converter input are used. Absolute accuracy includes quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. As the test conditions, the number of sampling states is indicated. Note 2. The value in parentheses indicates the sampling time. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 83 of 108 RX110 Group 5. Electrical Characteristics AVREFH0 5.0 Characteristics listed in Table 5.35 A/D Conversion Characteristics (1) 4.0 3.6 Characteristics listed in Table 5.36 A/D Conversion Characteristics (2) 3.0 2.7 2.4 2.0 1.8 Characteristics listed in Table 5.37 A/D Conversion Characteristics (3) 1.0 1.0 Figure 5.47 1.8 2.4 2.7 2.0 3.0 3.6 4.0 5.0 AVCC0 AVCC0 to AVREFH Voltage Range R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 84 of 108 RX110 Group Table 5.36 5. Electrical Characteristics A/D Conversion Characteristics (2) Conditions: 2.4 V ≤ VCC ≤ 3.6 V, 2.4 V ≤ AVCC0 ≤ 3.6 V, 2.4 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C Item Frequency Resolution Conversion time*1 (Operation at PCLKD = 16 MHz) Permissible signal source impedance (Max.) = 1.0 kΩ Min. Typ. Max. Unit 4 — 16 MHz Test Conditions — — 12 Bit 2.062 (0.625)*2 — — µs High-precision channel ADCSR.ADHSC bit = 1 ADSSTRn.SST[7:0] bits = 09h 2.750 (1.313)*2 — — µs Normal-precision channel ADCSR.ADHSC bit = 1 ADSSTRn.SST[7:0] bits = 14h Analog input effective range 0 — VREFH0 V Offset error — ±0.5 ±6.0 LSB Full-scale error — ±1.25 ±6.0 LSB Quantization error — ±0.5 — LSB Absolute accuracy — ±3.0 ±8.0 LSB DNL differential nonlinearity error — ±1.0 — LSB INL integral nonlinearity error — ±1.5 ±3.0 LSB Note: The characteristics apply when no pin functions other than A/D converter input are used. Absolute accuracy includes quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. As the test conditions, the number of sampling states is indicated. Note 2. The value in parentheses indicates the sampling time. Table 5.37 A/D Conversion Characteristics (3) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, 1.8 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C Item Min. Typ. Max. Unit Frequency 1 Resolution — — 8 MHz — 12 Bit 4.875 (1.250)*2 — — µs 6.250 (2.625)*2 — — Analog input effective range 0 — VREFH0 Offset error — ±0.5 ±24.0 LSB Full-scale error — ±1.25 ±24.0 LSB Quantization error — ±0.5 — LSB Absolute accuracy — ±2.75 ±32.0 LSB DNL differential nonlinearity error — ±1.0 — LSB INL integral nonlinearity error — ±1.25 ±12.0 LSB time*1 Conversion (Operation at PCLKD = 8 MHz) Permissible signal source impedance (Max.) = 5.0 kΩ Test Conditions High-precision channel ADCSR.ADHSC bit = 0 ADSSTRn.SST[7:0] bits = 09h Normal-precision channel ADCSR.ADHSC bit = 0 ADSSTRn.SST[7:0] bits = 14h V Note: The characteristics apply when no pin functions other than A/D converter input are used. Absolute accuracy includes quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. As the test conditions, the number of sampling states is indicated. Note 2. The value in parentheses indicates the sampling time. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 85 of 108 RX110 Group Table 5.38 5. Electrical Characteristics A/D Converter Channel Classification Classification Channel Conditions High-precision channel AN000 to AN004, AN006 Normal-precision channel AN008 to AN015 Internal reference voltage input channel Internal reference voltage AVCC0 = 2.0 to 3.6 V Temperature sensor input channel Temperature sensor output AVCC0 = 2.0 to 3.6 V Table 5.39 Remarks AVCC0 = 1.8 to 3.6 V Pins AN000 to AN004 and AN006 cannot be used as digital outputs when the A/D converter is in use. A/D Internal Reference Voltage Characteristics Conditions: 2.0 V ≤ VCC ≤ 3.6 V, 2.0 V ≤ AVCC0 ≤ 3.6 V*1, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C Item Internal reference voltage input channel*2 Min. Typ. Max. Unit 1.36 1.43 1.50 V Test Conditions Note 1. The internal reference voltage cannot be selected for input channels when AVCC0 < 2.0 V. Note 2. The A/D internal reference voltage indicates the voltage when the internal reference voltage is input to the A/D converter. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 86 of 108 RX110 Group 5. Electrical Characteristics FFFh Full-scale error Integral nonlinearity error (INL) A/D converter output code Ideal line of actual A/D conversion characteristic Actual A/D conversion characteristic Ideal A/D conversion characteristic Differential nonlinearity error (DNL) 1-LSB width for ideal A/D conversion characteristic Differential nonlinearity error (DNL) 1-LSB width for ideal A/D conversion characteristic Absolute accuracy 000h Offset error 0 Figure 5.48 Analog input voltage VREFH0 (full-scale) Illustration of A/D Converter Characteristic Terms Absolute accuracy Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of analog input voltage (1-LSB width), that can meet the expectation of outputting an equal code based on the theoretical A/D conversion characteristics, is used as an analog input voltage. For example, if 12-bit resolution is used and if reference voltage (VREFH0 = 3.072 V), then 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, 1.5 mV, ... are used as analog input voltages. If analog input voltage is 6 mV, absolute accuracy = ±5 LSB means that the actual A/D conversion result is in the range of 003h to 00Dh though an output code, 008h, can be expected from the theoretical A/D conversion characteristics. Integral nonlinearity error (INL) Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale errors are zeroed, and the actual output code. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 87 of 108 RX110 Group 5. Electrical Characteristics Differential nonlinearity error (DNL) Differential nonlinearity error is the difference between 1-LSB width based on the ideal A/D conversion characteristics and the width of the actually output code. Offset error Offset error is the difference between a transition point of the ideal first output code and the actual first output code. Full-scale error Full-scale error is the difference between a transition point of the ideal last output code and the actual last output code. 5.5 Temperature Sensor Characteristics Table 5.40 Temperature Sensor Characteristics Conditions: 2.0 V ≤ VCC ≤ 3.6 V, 2.0 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Item Relative accuracy Symbol Min. Typ. Max. Unit ― ― ±1.5 ― °C ― ±2.0 ― ― ― –3.65 ― mV/°C Output voltage (at 25°C) ― ― 1.05 ― V tSTART ― ― 5 μs ― 5 ― ― μs Sampling time R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 2.4 V or above Below 2.4 V Temperature slope Temperature sensor start time Test Conditions VCC = 3.3 V Page 88 of 108 RX110 Group 5.6 5. Electrical Characteristics Power-On Reset Circuit and Voltage Detection Circuit Characteristics Table 5.41 Power-On Reset Circuit and Voltage Detection Circuit Characteristics (1) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Item Voltage detection level Symbol Min. Typ. Max. Unit Power-on reset (POR) VPOR 1.35 1.50 1.65 V Figure 5.49, Figure 5.50 Test Conditions Voltage detection circuit (LVD1)*1 Vdet1_4 3.00 3.10 3.20 V Figure 5.51 Vdet1_5 2.91 3.00 3.09 Vdet1_6 2.81 2.90 2.99 Vdet1_7 2.70 2.79 2.88 Vdet1_8 2.60 2.68 2.76 Vdet1_9 2.50 2.58 2.66 Vdet1_A 2.40 2.48 2.56 Vdet1_B 1.99 2.06 2.13 Vdet1_C 1.90 1.96 2.02 Vdet1_D 1.80 1.86 1.92 At falling edge VCC Note: These characteristics apply when noise is not superimposed on the power supply. When a setting is made so that the voltage detection level overlaps with that of the voltage detection circuit (LVD2), it cannot be specified which of LVD1 and LVD2 is used for voltage detection. Note 1. n in the symbol Vdet1_n denotes the value of the LVDLVLR.LVD1LVL[3:0] bits. Table 5.42 Power-On Reset Circuit and Voltage Detection Circuit Characteristics (2) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Item Symbol Min. Typ. Max. Unit Vdet2_0 2.71 2.90 3.09 V Vdet2_1 2.43 2.60 2.77 Vdet2_2 1.87 2.00 2.13 Vdet2_3*2 1.69 1.80 1.91 tPOR ― 9.1 ― tPOR ― 1.6 ― tLVD1 ― 568 ― ― 100 ― tLVD2 ― 100 ― μs Figure 5.52 tdet ― ― 350 μs Figure 5.49 Minimum VCC down time*5 tVOFF 350 ― ― μs Figure 5.49, VCC = 1.0 V or above Power-on reset enable time tW(POR) 1 ― ― ms Figure 5.50, VCC = below 1.0 V LVD operation stabilization time (after LVD is enabled) Td(E-A) ― ― 300 μs Figure 5.51, Figure 5.52 VLVH ― 70 ― mV ― 60 ― Vdet1_5 to 9, LVD2 selected ― 50 ― When selection is from among Vdet1_A to B. ― 40 ― When selection is from among Vdet1_C to D. Voltage detection level Voltage detection circuit (LVD2)*1 Wait time after power-on reset cancellation At normal startup*3 Wait time after voltage monitoring 1 reset cancellation Power-on voltage monitoring 1 reset disabled*3 During fast startup time*4 Power-on voltage monitoring 1 reset enabled*4 Wait time after voltage monitoring 2 reset cancellation Response delay time Hysteresis width (LVD1 and LVD2) Note: Note 1. Note 2. Note 3. Note 4. Note 5. Test Conditions Figure 5.52 At falling edge VCC ms Figure 5.50 μs Figure 5.51 Vdet1_4 selected These characteristics apply when noise is not superimposed on the power supply. When a setting is made so that the voltage detection level overlaps with that of the voltage detection circuit (LVD1), it cannot be specified which of LVD1 and LVD2 is used for voltage detection. n in the symbol Vdet2_n denotes the value of the LVDLVLR.LVD2LVL[3:0] bits. Vdet2_3 selection can be used only when the CMPA2 pin input voltage is selected and cannot be used when the power supply voltage (VCC) is selected. When OFS1.(STUPLVD1REN, FASTSTUP) = 11b. When OFS1.(STUPLVD1REN, FASTSTUP) ≠ 11b. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet0, Vdet1, and Vdet2 for the POR/LVD. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 89 of 108 RX110 Group 5. Electrical Characteristics tVOFF VCC VPOR 1.0 V Internal reset signal (active-low) tdet Figure 5.49 tdet tPOR Voltage Detection Reset Timing VPOR VCC 1.0 V tw(POR) Internal reset signal (active-low) *1 tdet tPOR Note 1. tw(por) is the time required for a power-on reset to be enabled while the external power VCC is being held below the valid voltage (1.0 V). When VCC turns on, maintain tw(por) for 1.0 ms or more. Figure 5.50 Power-On Reset Timing R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 90 of 108 RX110 Group 5. Electrical Characteristics tVOFF VCC VLVH Vdet1 LVD1E Td(E-A) LVD1 Comparator output LVD1CMPE LVD1MON Internal reset signal (active-low) When LVD1RN = L tdet tdet tLVD1 When LVD1RN = H tLVD1 Figure 5.51 Voltage Detection Circuit Timing (Vdet1) tVOFF VCC VLVH Vdet2 LVD2E Td(E-A) LVD2 Comparator output LVD2CMPE LVD2MON Internal reset signal (active-low) When LVD2RN = L tdet tdet tLVD2 When LVD2RN = H tLVD2 Figure 5.52 Voltage Detection Circuit Timing (Vdet2) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 91 of 108 RX110 Group 5.7 5. Electrical Characteristics Oscillation Stop Detection Timing Table 5.43 Oscillation Stop Detection Circuit Characteristics Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C Item Detection time Symbol Min. Typ. Max. Unit tdr — — 1 ms Test Conditions Figure 5.53 Main clock tdr OSTDSR.OSTDF LOCO clock ICLK Figure 5.53 Oscillation Stop Detection Timing R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 92 of 108 RX110 Group 5.8 5. Electrical Characteristics ROM (Flash Memory for Code Storage) Characteristics Table 5.44 ROM (Flash Memory for Code Storage) Characteristics (1) Item Reprogramming/erasure Data hold time Symbol cycle*1 Min. Typ. Max. Unit NPEC 1000 — — Times tDRP 20*2, *3 — — Year After 1000 times of NPEC Conditions Ta = +85°C Note 1. Definition of reprogram/erase cycle: The reprogram/erase cycle is the number of erasing for each block. When the reprogram/ erase cycle is n times (n = 1000), erasing can be performed n times for each block. For instance, when 4-byte programming is performed 256 times for different addresses in 1-Kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming the same address for several times as one erasing is not enabled (overwriting is prohibited). Note 2. Characteristic when using the flash memory programmer and the self-programming library provided from Renesas Electronics. Note 3. This result is obtained from reliability testing. Table 5.45 ROM (Flash Memory for Code Storage) Characteristics (2) High-speed operating mode Conditions: 2.7 V ≤ VCC ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V Temperature range for the programming/erasure operation: Ta = –40 to +105°C Item Symbol FCLK = 1 MHz Min. FCLK = 32 MHz Typ. Max. Min. Typ. Max. Unit Programming time 4-byte tP4 — 103 931 — 52 489 μs Erasure time 1-Kbyte tE1K — 8.23 267 — 5.48 214 ms tE128K — 203 463 — 20 228 ms 4-byte tBC4 — — 48 — — 15.9 μs 1-Kbyte tBC1K — — 1.58 — — 0.127 ms tSED — — 21.6 — — 12.8 μs Start-up area switching setting time tSAS — 12.6 543 — 6.16 432 ms Access window time tAWS — 12.6 543 — 6.16 432 ms ROM mode transition wait time 1 tDIS 2 — — 2 — — μs ROM mode transition wait time 2 tMS 5 — — 5 — — μs 128-Kbyte Blank check time Erase operation forcible stop time Note: Note: Note: Does not include the time until each operation of the flash memory is started after instructions are executed by software. The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When using FCLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. The frequency accuracy of FCLK should be ±3.5%. Confirm the frequency accuracy of the clock source. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 93 of 108 RX110 Group Table 5.46 5. Electrical Characteristics ROM (Flash Memory for Code Storage) Characteristics (3) Middle-speed operating mode Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V Temperature range for the programming/erasure operation: Ta = –40 to +85°C Item Symbol FCLK = 1 MHz FCLK = 8 MHz Min. Typ. Max. Min. Typ. Max. Unit Programming time 4-byte tP4 — 143 1330 — 96.8 932 μs Erasure time 1-Kbyte tE1K — 8.3 269 — 5.85 219 ms 128-Kbyte tE128K — 203 464 — 40 260 ms 4-byte tBC4 — — 78 — — 50 μs 1-Kbyte tBC1K — — 1.61 — — 0.369 ms Erase operation forcible stop time tSED — — 33.6 — — 25.6 μs Start-up area switching setting time tSAS — 13.2 549 — 7.6 445 ms Access window time tAWS — 13.2 549 — 7.6 445 ms ROM mode transition wait time 1 tDIS 2 — — 2 — — μs ROM mode transition wait time 2 tMS 3 — — 3 — — μs Blank check time Note: Note: Note: Does not include the time until each operation of the flash memory is started after instructions are executed by software. The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When using FCLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. The frequency accuracy of FCLK should be ±3.5%. Confirm the frequency accuracy of the clock source. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 94 of 108 RX110 Group 5.9 5. Electrical Characteristics Usage Notes 5.9.1 Connecting VCL Capacitor and Bypass Capacitors This MCU integrates an internal voltage-down circuit, which is used for lowering the power supply voltage in the internal MCU to adjust automatically to the optimum level. A 4.7-μF capacitor needs to be connected between this internal voltage-down power supply (VCL pin) and VSS pin. Figure 5.54 to Figure 5.55 shows how to connect external capacitors. Place an external capacitor close to the pins. Do not apply the power supply voltage to the VCL pin. Insert a multilayer ceramic capacitor as a bypass capacitor between each pair of the power supply pins. Implement a bypass capacitor to the MCU power supply pins as close as possible. Use a recommended value of 0.1 μF as the capacitance of the capacitors. For the capacitors related to crystal oscillation, see section 9, Clock Generation Circuit in the User’s Manual: Hardware. For the capacitors related to analog modules, also see section 27, 12-Bit A/D Converter (S12ADb) in the User’s Manual: Hardware. For notes on designing the printed circuit board, see the descriptions of the application note "Hardware Design Guide" (R01AN1411EJ). The latest version can be downloaded from Renesas Electronics Website. 33 34 35 36 32 31 51 30 52 29 53 28 54 27 RX110 Group PLQP0064KB-A PLQP0064GA-A (64-pin LFQFP/LQFP) (Top view) 55 56 57 58 59 26 25 24 23 22 20 62 AVSS0 19 63 AVCC0 18 17 16 12 11 10 9 8 7 6 5 4 3 2 1 64 15 VCC 21 61 14 VSS 60 13 VCL Bypass capacitor 0.1 µF 37 39 50 VCC 38 41 49 VSS 40 42 43 44 45 46 47 48 Bypass capacitor 0.1 µF Bypass Bypass capacitor capacitor 4.7 µF 0.1 µF Note. Do not apply the power supply voltage to the VCL pin. Use a 4.7-µF multilayer ceramic for the VCL pin and place it close to the pin. A recommended value is shown for the capacitance of the bypass capacitors. Figure 5.54 Connecting Capacitors (64 Pins) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 95 of 108 RX110 Group 5. Electrical Characteristics 25 26 29 27 24 38 23 39 22 40 21 41 RX110 Group 42 PLQP0048KB-A (48-pin LFQFP) (Top view) 43 44 20 19 18 17 Bypass capacitor 4.7 µF 12 VCC 11 VSS 10 VCL 9 13 8 48 AVCC0 7 14 6 47 AVSS0 5 15 4 46 3 16 2 45 1 Bypass capacitor 0.1 µF VCC 28 37 VSS 30 31 32 33 34 35 36 Bypass capacitor 0.1 µF Bypass capacitor 0.1 µF Note. Do not apply the power supply voltage to the VCL pin. Use a 4.7-µF multilayer ceramic for the VCL pin and place it close to the pin. A recommended value is shown for the capacitance of the bypass capacitors. Figure 5.55 Connecting Capacitors (48-pin LFQFP) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 96 of 108 RX110 Group Appendix 1. Package Dimensions Appendix 1. Package Dimensions Information on the latest version of the package dimensions or mountings has been displayed in “Packages” on Renesas Electronics Corporation website. JEITA Package Code P-LFQFP64-10x10-0.50 RENESAS Code PLQP0064KB-A Previous Code 64P6Q-A / FP-64K / FP-64KV MASS[Typ.] 0.3g HD *1 D 48 33 49 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 32 bp 64 1 c1 Terminal cross section ZE 17 Reference Symbol c E *2 HE b1 16 Index mark ZD c A *3 A1 y S e A2 F S bp L x L1 Detail F Figure A D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Dimension in Millimeters Min Nom Max 9.9 10.0 10.1 9.9 10.0 10.1 1.4 11.8 12.0 12.2 11.8 12.0 12.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0° 8° 0.5 0.08 0.08 1.25 1.25 0.35 0.5 0.65 1.0 64-Pin LFQFP (PLQP0064KB-A) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 97 of 108 RX110 Group Appendix 1. Package Dimensions JEITA Package Code P-LQFP64-14x14-0.80 RENESAS Code PLQP0064GA-A Previous Code 64P6U-A/ ⎯ MASS[Typ.] 0.7g HD *1 D 33 48 49 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 32 bp c Reference Symbol *2 E HE c1 b1 ZE Terminal cross section 64 17 c Index mark A2 16 ZD A 1 F A1 S L D E A2 HD HE A A1 bp b1 c c1 L1 y S e Figure B Detail F *3 bp x e x y ZD ZE L L1 Dimension in Millimeters Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.1 0.2 0 0.32 0.37 0.42 0.35 0.09 0.145 0.20 0.125 0° 8° 0.8 0.20 0.10 1.0 1.0 0.3 0.5 0.7 1.0 64-Pin LQFP (PLQP0064GA-A) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 98 of 108 RX110 Group Appendix 1. Package Dimensions 64-PIN PLASTIC FLGA (5x5) 60x b x M S AB A D w S A ZD e 8 ZE 7 6 B 5 E 4 3.90 3 2 C D INDEX MARK w S B 1 H G F E D C B E A 3.90 y1 A S S y S DETAIL C DETAIL E DETAIL D R0.17o0.015 0.70o0.03 0.55o0.04 R0.125o 0.02 0.75 0.55 R0.17o0.015 0.70o0.03 R0.125o0.02 0.55o0.04 0.75 0.55 b (LAND PAD) 0.34o0.03 (APERTURE OF SOLDER RESIST) 0.55 0.75 0.55o0.04 0.70o0.03 0.55 0.75 0.55o0.04 0.70o0.03 R0.275o0.02 R0.35o0.015 (UNIT:mm) ITEM D DIMENSIONS 5.00o0.10 E 5.00o0.10 w 0.20 e A 0.50 0.69o0.07 b 0.25o0.04 x 0.05 y 0.08 y1 0.20 ZD 0.75 ZE 0.75 P64FC-50-AN5 2011 Renesas Electronics Corporation. All rights reserved. Figure C 64-Pin WFLGA (PWLG0064KA-A) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 99 of 108 RX110 Group Appendix 1. Package Dimensions JEITA Package Code P-LFQFP48-7x7-0.50 RENESAS Code PLQP0048KB-A Previous Code 48P6Q-A MASS[Typ.] 0.2g HD *1 D 36 25 37 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 24 bp c c1 HE *2 E b1 Reference Symbol 48 13 1 ZE Terminal cross section 12 c A F A2 Index mark ZD S A1 L D E A2 HD HE A A1 bp b1 c c1 y S Figure D *3 bp Detail F x Min 6.9 6.9 8.8 8.8 0 0.17 0.09 0° L1 e Dimension in Millimeters e x y ZD ZE L L1 0.35 Nom Max 7.0 7.1 7.0 7.1 1.4 9.0 9.2 9.0 9.2 1.7 0.1 0.2 0.22 0.27 0.20 0.145 0.20 0.125 8° 0.5 0.08 0.10 0.75 0.75 0.5 0.65 1.0 48-Pin LFQFP (PLQP0048KB-A) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 100 of 108 RX110 Group Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-HWQFN48-7x7-0.50 PWQN0048KB-A 48PJN-A P48K8-50-5B4-5 0.13 D DETAIL OF E S A PART A A S y S Referance Symbol D2 A EXPOSED DIE PAD 1 12 Min Nom Max D 6.95 7.00 7.05 E 6.95 7.00 7.05 A 0.70 0.75 0.80 b 0.18 0.25 0.30 e 13 48 Dimension in Millimeters Lp B 0.50 0.30 0.40 0.50 x 0.05 y 0.05 E2 ITEM 37 24 36 25 Lp EXPOSED DIE PAD VARIATIONS D2 E2 MIN NOM MAX MIN NOM MAX A 5.45 5.50 5.55 5.45 5.50 5.55 e b x M S AB 2012 Renesas Electronics Corporation. All rights reserved. Figure E 48-Pin HWQFN (PWQN0048KB-A) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 101 of 108 RX110 Group Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-HWQFN40-6x6-0.50 PWQN0040KC-A P40K8-50-4B4-4 0.09 D DETAIL OF A PART E S A A S y Referance Symbol S D2 A 1 EXPOSED DIE PAD 10 Min Nom Max D 5.95 6.00 6.05 E 5.95 6.00 6.05 A 0.70 0.75 0.80 b 0.18 0.25 0.30 e Lp 11 40 Dimension in Millimeters 0.50 0.30 0.40 0.50 x 0.05 y 0.05 B E2 ITEM 31 20 21 30 Lp E2 A 4.45 4.50 4.55 4.45 4.50 4.55 e b Figure F EXPOSED DIE PAD VARIATIONS D2 MIN NOM MAX MIN NOM MAX x M S AB 2012 Renesas Electronics Corporation. All rights reserved. 40-Pin HWQFN (PWQN0040KC-A) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 102 of 108 RX110 Group Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-WFLGA36-4x4-0.50 PWLG0036KA-A P36FC-50-AA4-2 0.023 32x b S AB e ZE w S A M A ZD D x 6 5 B 4 E 3 2.90 2 C INDEX MARK y1 D w S B S 1 F E D C B A E 2.90 A S y S DETAIL C DETAIL E DETAIL D R0.17± 0.05 0.70 ±0.05 0.55 ±0.05 R0.12 ±0.05 0.75 0.55 (UNIT:mm) R0.17 ±0.05 0.70 ±0.05 R0.12 ±0.05 0.55 ±0.05 0.75 0.55 φb (LAND PAD) φ 0.34±0.05 (APERTURE OF SOLDER RESIST) 0.55 0.75 0.55±0.05 0.70± 0.05 0.55 0.75 0.55±0.05 R0.275±0.05 R0.35±0.05 ITEM D DIMENSIONS E 4.00±0.10 w 0.20 4.00±0.10 e 0.50 A 0.69±0.07 b 0.24±0.05 x 0.05 y 0.08 y1 0.20 ZD 0.75 ZE 0.75 0.70±0.05 2012 Renesas Electronics Corporation. All rights reserved. Figure G 36-Pin WFLGA (PWLG0036KA-A) R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 103 of 108 REVISION HISTORY RX110 Group REVISION HISTORY REVISION HISTORY Rev. Date 0.51 1.00 Jul 03, 2013 Dec , 2013 RX110 Group Datasheet Description Page Summary — First edition, issued 1. Overview 6, 7 Table 1.3 List of Products changed 8 Figure 1.1 How to Read the Product Part No., Memory Capacity, and Package Type changed 9 Figure 1.2 Block Diagram changed 4. I/O Registers 44 Table 4.1 List of I/O Registers (Address Order) changed 5. Electrical Characteristics 45 to 91 Changed R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 104 of 108 RX110 Group REVISION HISTORY Classifications - Items with Technical Update document number: Changes according to the corresponding issued Technical Update - Items without Technical Update document number: Minor changes that do not require Technical Update to be issued Rev. Date 1.20 Jul 29, 2016 Page 1. Overview 18 to 25 Description Summary Table 1.5 to 1.9 Note 1 regarding I/O power source is AVCC0 for the ports (P4, PJ6, and PJ7), added 5. Electrical Characteristics 45 Table 5.1 Absolute Maximum Ratings, Analog power supply voltage added 45 Table 5.2 Recommended Operating Conditions, VREFH0 / VREFL0 added 51 Table 5.8 DC Characteristics (6), Increment for IWDT operation added 52 Table 5.9 DC Characteristics (7) Permissible total consumption power added 53 Table 5.10 DC Characteristics (8), LDV1,2 added 54, 55 Table 5.15 Permissible Output Currents is divided into D version and G version 93 Table 5.45 ROM (Flash Memory for Code Storage) Characteristics (2), Erasure time - 128-Kbyte added 94 Table 5.46 ROM (Flash Memory for Code Storage) Characteristics (3), Temperature range for the programming/erasure operation changed and Erasure time - 128-Kbyte added 95, 96 5.9 Usage Notes added Classification TN-RX*-A135A/E TN-RX*-A132A/E TN-RX*-A132A/E All trademarks and registered trademarks are the property of their respective owners. R01DS0202EJ0120 Rev.1.20 Jul 29, 2016 Page 105 of 108 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. Handling of Unused Pins Handle unused pins in accordance with the directions given under Handling of Unused Pins in the manual. ¾ The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. ¾ The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. ¾ The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. ¾ When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to a product with a different part number, confirm that the change will not lead to problems. ¾ The characteristics of Microprocessing unit or Microcontroller unit products in the same group but having a different part number may differ in terms of the internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-evaluation test for the given product. Notice 1. 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