R5F52108ADFG

Preliminary Data Sheet Specifications in this document are tentative and subject to change. RX210 Group Renesas MCUs 50-MHz 32-bit RX MCUs, 78 DMIPS, up to 512-KB flash memory, 12-bit AD, 10-bit DA, ELC, MPC, RTC, up to 9 comms interfaces; incorporating functions for IEC60730 compliance R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Features ■ 32-bit RX CPU core  Max. operating frequency: 50 MHz Capable of 78 DMIPS in operation at 50 MHz  Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations  Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle)  Fast interrupt  CISC Harvard architecture with 5-stage pipeline  Variable-length instructions, ultra-compact code  On-chip debugging circuit ■ Low-power design and architecture  Operation from a single 1.62- to 5.5-V supply  1.62-V operation available (at up to 20 MHz)  Deep software standby mode with RTC remaining usable  Four low-power modes ■ On-chip flash memory for code, no wait states  50-MHz operation, 20-ns read cycle  No wait states for reading at full CPU speed  128- to 512-Kbyte capacities  User code programmable via the SCI  Programmable at 1.62 V  For instructions and operands ■ On-chip data flash memory  Eight Kbytes, reprogrammable up to TBD times  Erasing and programming impose no load on the CPU. ■ On-chip SRAM, no wait states  20- to 64-Kbyte size capacities ■ DMA  DMACA: Incorporates four channels  DTC: Four transfer modes ■ ELC  Module operation can be initiated by event signals without going through interrupts.  Modules can operate while the CPU is sleeping. ■ Reset and supply management  Nine types of reset, including the power-on reset (POR)  Low voltage detection (LVD) with voltage settings ■ Clock functions  Frequency of external clock: Up to 20 MHz  Frequency of the oscillator for sub-clock generation: 32.768 kHz  PLL circuit input: 4 to 12.5 MHz  On-chip low- and high-speed oscillators, dedicated onchip low-speed oscillator for the IWDT  Generation of a dedicated 32.768-kHz clock for the RTC  Clock frequency accuracy measurement circuit (CAC) ■ Real-time clock  Adjustment functions (30 seconds, leap year, and error)  Time capture function  Time capture on event-signal input through external pins  RTC capable of initiating return from deep software standby mode PLQP0100KB-A PLQP0080KB-A PLQP0080JA-A PLQP0064KB-A PLQP0064GA-A 14 × 14 mm, 0.5-mm pitch 12 × 12 mm, 0.5-mm pitch 14 × 14 mm, 0.65-mm pitch 10 × 10 mm, 0.5-mm pitch 14 × 14 mm, 0.8-mm pitch PTLG0100JA-A 7 × 7 mm, 0.65-mm pitch ■ Independent watchdog timer  125-kHz on-chip low-speed oscillator produces a dedicated clock signal to drive IWDT operation. ■ Useful functions for IEC60730 compliance  Self-diagnostic and disconnection-detection functions for the AD converter, clock-frequency accuracymeasurement circuit, independent watchdog timer, functions to assist in RAM testing, etc. ■ Up to nine communications interfaces  SCI with many useful functions (up to seven interfaces)  Asynchronous mode, clock synchronous mode, smart card interface  I2C bus interface: Transfer at up to 1 Mbps, capable of SMBus operation (1 interface)  RSPI (1) ■ External address space  Four CS areas (4 × 16 Mbytes)  8- or 16-bit bus space is selectable per area ■ Up to 14 extended-function timers  16-bit MTU2: input capture, output capture, complementary PWM output, phase counting mode (6 channels)  8-bit TMR (4 channels)  16-bit compare-match timers (4 channels) ■ 12-bit A/D converter  Capable of conversion within 1 μs  Sample-and-hold circuits (for three channels)  Three-channel synchronized sampling available  Self-diagnostic function and analog input disconnection detection assistance function ■ 10-bit D/A converter ■ Analog comparator ■ Programmable I/O ports  5-V tolerant, open drain, input pull-up, switching of driving ability ■ MPC  Multiple locations are selectable for I/O pins of peripheral functions ■ Temperature sensor ■ Operating temp. range  -40 C to +85C R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 1 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 1. Overview 1. 1.1 Overview Outline of Specifications Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different packages. Table 1.1 is for products with the greatest number of functions, so numbers of peripheral modules and channels will differ in accord with the package. For details, see Table 1.2, Comparison of Functions for Different Packages. Table 1.1 Classification CPU Outline of Specifications (1 / 3) Module/Function CPU Description      Maximum operating frequency: 50 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set of the CPU General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit register Basic instructions: 73 DSP instructions: 9 Addressing modes: 10 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32 x 32  64 bits On-chip divider: 32 / 32  32 bits Barrel shifter: 32 bits        Memory ROM  ROM capacity: 512 Kbytes (max.)  Three on-board programming modes Boot mode (The user mat and the user boot mat are programmable via the SCI.) User boot mode User program mode  Parallel programmer mode (for off-board programming) RAM capacity: 64 Kbytes (max.) E2 data flash capacity: 8 Kbytes Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled expansion mode (software switching)  Main clock oscillator, sub-clock oscillator, Low-speed on-chip oscillator, high-speed on-chip oscillator, PLL frequency synthesizer, and dedicated low-speed on-chip oscillator for IWDT  Oscillation stop detection  Measuring circuit for accurcy of clock frequency (clock-accurcy check: CAC)  Independent frequency-division and multiplication settings for the system clock (ICLK), peripheral module clock (PCLK), external bus clock (BCLK), and flashIF clock (FCLK) The CPU and system sections such as other bus masters run in synchronization with the system clock (ICLK): 50 MHz (at max.) Peripheral modules run in synchronization with the peripheral module clock (PCLK): 32 MHz (at max.) Devices connected to the external bus run in synchronization with the external bus clock (BCLK): 12.5 MHz (at max.) The flash peripheral circuit runs in synchronization with the flash peripheral clock (FCLK): 32 MHz (at max.) Pin reset, power-on reset, voltage-monitoring reset, watchdog timer reset, independent watchdog timer reset, deep software standby reset, and software reset RAM E2 data flash MCU operating mode Clock Clock generation circuit Reset Voltage detection Voltage detection circuit (LVD)  When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt is generated. Voltage detection circuit 0 is capable of selecting the detection voltage from 4 levels Voltage detection circuit 1 is capable of selecting the detection voltage from 16 levels Voltage detection circuit 2 is capable of selecting the detection voltage from 16 levels  Module stop function  Four low power consumption modes Sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode  Interrupt vectors: 117  External interrupts: 9 (NMI and IRQ0 to IRQ7 pins)  Non-maskable interrupts: 6 (the NMI pin, oscillation stop detection interrupt, voltage-monitoring interrupt 1, voltage-monitoring interrupt 2, WDT interrupt, and IWDT interrupt)  16 levels specifiable for the order of priority Low power consumption Interrupt Low power consumption facilities Interrupt control unit (ICU) R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 2 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group Table 1.1 Classification 1. Overview Outline of Specifications (2 / 3) Module/Function Description  The external address space can be divided into four areas (CS0 to CS3), each with independent control of access settings. Capacity of each area: 16 Mbytes (CS0 to CS3) A chip-select signal (CS0# to CS3#) can be output for each area. Each area is specifiable as an 8- or 16-bit bus space The data arrangement in each area is selectable as little or big endian (only for data). Bus format: Separate bus, multiplex bus  Wait control  Write buffer facility  4 channels  Three transfer modes: Normal transfer, repeat transfer, and block transfer  Activation sources: Software trigger, external interrupts, and interrupt requests from peripheral functions  Three transfer modes: Normal transfer, repeat transfer, and block transfer  Activation sources: Interrupts  Chain transfer function 100-pin LQFP/80-pin LQFP/64-pin LQFP  I/O pin: 84/64/48  Input: 1/1/1  Pull-up resistors: 85/65/49  Open-drain outputs: 54/44/35  5-V tolerance: 4/4/2  Event signals of 59 types can be directly connected to the module  Operations of timer modules are selectable at event input  Capable of event link operation for ports B and E  Capable of selecting input/output function from multiple pins  (16 bits x 6 channels) x 1 unit  Time bases for the six 16-bit timer channels can be provided via up to 16 pulse-input/output lines and three pulse-input lines  Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4, PCLK/16, PCLK/64, PCLK/256, PCLK/1024, TCLKA, TCLKB, TCLKC, TCLKD) other than channel 5, for which only four signals are available.  Input capture function  21 output compare/input capture registers  Pulse output mode  Complementary PWM output mode  Reset synchronous PWM mode  Phase-counting mode  Generation of triggers for A/D converter conversion External bus extension DMA DMA controller (DMACA) Data transfer controller (DTC) I/O ports Programmable I/O ports Event link controller (ELC) Multifunction pin controller (MPC) Timers Multi-function timer pulse unit 2 (MTU2) Port output enable2 (POE2) Controls the high-impedance state of the MTU2’s waveform output pins from multiple pins 8-bit timer (TMR)  (8 bits x 2 channels) x 2 units  Select from among seven internal clock signals (PCLK, PCLK/2, PCLK/8, PCLK/32, PCLK/64, PCLK/1024, PCLK/8192) and one external clock signal  Capable of output of pulse trains with desired duty cycles or of PWM signals  The 2 channels of each unit can be cascaded to create a 16-bit timer  Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12  (16 bits x 2 channels) x 2 units  Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)  14 bits x 1 channel  Select from among 6 counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/512, PCLK/2048, PCLK/8192)  14 bits x 1 channel  Counter-input clock: Dedicated low-speed on-chip oscillator for IWDT Frequency divided by 1, 16, 32, 64, 128, or 256     Clock source: Subclock Time/calendar Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt Time-capture facility for three values Compare match timer (CMT) Watchdog timer (WDT) Independent watchdog timer (IWDT) Realtime clock (RTC) R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 3 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group Table 1.1 Classification Communication function 1. Overview Outline of Specifications (3 / 3) Module/Function Serial communications interfaces (SCIc, SCId) Description  7 channels (channel 0, 1, 5, 6, 8, 9: SCIc, channel 12: SCId)  Serial communications modes: Asynchronous, clock synchronous, and smart-card interface  On-chip baud rate generator allows selection of the desired bit rate  Choice of LSB-first or MSB-first transfer  Average transfer rate clock can be input from TMR timers (SCL5, SCL6, and SCL12)  Simple IIC  Simple SPI  Master/slave mode supported (SCId only)  Start frame and information frame are included (SCId only)  1 channel  Communications formats: I2C bus format/SMBus format  Master/slave selectable  Supports the first mode  1 channel  RSPI transfer facility Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPI clock (RSPCK) signals enables serial transfer through SPI operation (four lines) or clocksynchronous operation (three lines)  Capable of handling serial transfer as a master or slave  Data formats  Choice of LSB-first or MSB-first transfer The number of bits in each transfer can be changed to any number of bits from 8 to 16, 20, 24, or 32 bits. 128-bit buffers for transmission and reception Up to four frames can be transmitted or received in a single transfer operation (with each frame having up to 32 bits)  Double buffers for both transmission and reception          12 bits (16 channels x 1 unit) 12-bit resolution Conversion time: 1.0 s per channel (in operation with ADCLK at 50 MHz) Operating modes Scan mode (single-cycle scan mode, continuous scan mode, and group scan mode) Sample-and-hold function Self-diagnosis for the A/D converter Assistance in detecting disconnected analog inputs Double-trigger mode (duplexing of A/D-converted data) A/D conversion start conditions Conversion can be started by software, a conversion start trigger from a timer (MTU2), an external trigger signal, or ELC. I2C bus interface (RIIC) Serial peripheral interface (RSPI) 12-bit A/D converter Temperature sensor D/A converter  Outputs the voltage that changes depending on the temperature  PGA gain switchable: Four levels according to the voltage range  2 channels  10-bit resolution  Output voltage: 0 V to VREFH  CRC code generation for arbitrary amounts of data in 8-bit units  Select any of three generating polynomials: X8 + X2 + X + 1, X16 + X15 + X2 + 1, or X16 + X12 + X5 + 1  Generation of CRC codes for use with LSB-first or MSB-first communications is selectable.  2 channels  Comparison of reference voltage and analog input voltage  2 channels  Comparison of reference voltage and analog input voltage VCC = 1.62 to 5.5 V: 20 MHz (TBD), VCC = 2.7 to 5.5 V: 50 MHz TBD mA (typ.) 40 to +85C 100-pin TFLGA (PTLG0100JA-A) 100-pin LQFP (PLQP0100KB-A) 80-pin LQFP (PLQP0080KB-A) 80-pin LQFP (PLQP0080JA-A) 64-pin LQFP (PLQP0064KB-A) 64-pin LQFP (PLQP0064GA-A) CRC calculator (CRC) Comparator A Comparator B Power supply voltage/ Operating frequency Supply current Operating temperature Package R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 4 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group Table 1.2 Comparison of Functions for Different Packages RX210 Group Module/Functions External bus Interrupt DMA CS areas: 4 (CS0 to CS3) External interrupts DMA controller (DMAC) Data transfer controller (DTC) Timers Multi-function timer pulse unit 2 (MTU2) Port output enable 2 (POE2) 8-bit timer (TMR) Compare match timer (CMT) Realtime clock (RTC) Watchdog timer (WDT) Independent watchdog timer (IWDT) Communication function Serial communications interface (SCIc) Serial communications interface (SCId) I2 C bus interface (RIIC) 6 channels (SCI0, 1, 5, 6, 8, 9) 1 channel (SCI12) 1 channel 1 channel 16 channels (AN000 to AN015) 14 channels (AN000 to AN013) 100 Pins Supported 80 Pins Not supported NMI, IRQ0 to IRQ7 4 channels (DMAC0 to DMAC3) Supported 6 channels (MTU0 to MTU5) POE0# to POE3#, POE8# 2 channels × 2 units 2 channels × 2 units Supported Supported Supported 64 Pins 1. Overview Not supported 5 channels (SCI1, 5, 6, 8, 9) Serial peripheral interface (RSPI) 12-bit A/D converter 12 channels (AN000 to AN004, AN006, AN008 to AN013) Temperature sensor D/A converter CRC calculator (CRC) Event link controller (ELC) Comparator A Comparator B Package 100-pin TFLGA 100-pin LQFP Supported 2 channels Supported Supported 2 channels 2 channels 80-pin LQFP 64-pin LQFP R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 5 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 1. Overview 1.2 List of Products Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part no., memory capacity, and package type. Table 1.3 Group RX210 List of Products Part No. R5F52108ADFP R5F52108ADFG R5F52108ADFN R5F52108ADFF R5F52108ADFM R5F52108ADFK R5F52108ADLJ R5F52107ADFP R5F52107ADFG R5F52107ADFN R5F52107ADFF R5F52107ADFM R5F52107ADFK R5F52107ADLJ R5F52106ADFP R5F52106ADFG R5F52106ADFN R5F52106ADFF R5F52106ADFM R5F52106ADFK R5F52106ADLJ R5F52105ADFP R5F52105ADFG R5F52105ADFN R5F52105ADFF R5F52105ADFM R5F52105ADFK R5F52105ADLJ Package PLQP0100KB-A T.B.D PLQP0080KB-A PLQP0080JA-A PLQP0064KB-A PLQP0064GA-A PTLG0100JA-A PLQP0100KB-A T.B.D PLQP0080KB-A PLQP0080JA-A PLQP0064KB-A PLQP0064GA-A PTLG0100JA-A PLQP0100KB-A T.B.D PLQP0080KB-A PLQP0080JA-A PLQP0064KB-A PLQP0064GA-A PTLG0100JA-A PLQP0100KB-A T.B.D PLQP0080KB-A PLQP0080JA-A PLQP0064KB-A PLQP0064GA-A PTLG0100JA-A ROM Capacity 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 384 Kbytes 384 Kbytes 384 Kbytes 384 Kbytes 384 Kbytes 384 Kbytes 384 Kbytes 256 Kbytes 256 Kbytes 256 Kbytes 256 Kbytes 256 Kbytes 256 Kbytes 256 Kbytes 128 Kbytes 128 Kbytes 128 Kbytes 128 Kbytes 128 Kbytes 128 Kbytes 128 Kbytes 20 Kbytes 32 Kbytes 8 Kbytes 50 MHz 64 Kbytes RAM Capacity E2 Data Flash Operating Frequency (Max.) R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 6 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 1. Overview R5 F 5 2 10 8AD F P Package type, number of pins, and pin pitch FP : LQFP/100/0.50 FN : LQFP/80/0.50 FM : LQFP/64/0.50 FG : LQFP/100/0.65 FF : LQFP/80/0.65 FK : LQFP/64/0.80 LJ : TFLGA/100/0.65 D : Products with wide temperature-range spec. (-40 to +85°C) ROM, RAM, and E2 data flash capacity 8: 512 Kbytes/64 Kbytes/8 Kbytes 7: 384 Kbytes/64 Kbytes/8 Kbytes 6: 256 Kbytes/32 Kbytes/8 Kbytes 5: 128 Kbytes/20 Kbytes/8 Kbytes Group name 10 : RX210 Group Series name RX200 Series Type of memory F: Flash memory version Renesas MCU Renesas semiconductor product Figure 1.1 How to Read the Product Part No., Memory Capacity, and Package Type R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 7 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 1. Overview 1.3 Block Diagram Figure 1.2 shows a block diagram. E2 data flash WDT IWDT ELC CRC SCIc × 6 channels SCId × 1 channel RSPI × 1 channel RIIC × 1 channel Internal peripheral buses 1 to 6 MTU2 × 6 channels POE2 TMR × 2 channels (unit 0) TMR x 2 channels (unit 1) CMT x 2 channels (unit 0) CMT x 2 channels (unit 1) Port 1 Port 2 Port 3 Port 4 Port 5 Port A Port B Comparator A × 2 channels Comparator B × 2 channels CAC Port C Port D Port E Port H BSC External bus Port 0 ROM ICU RTC 12-bit A/D converter × 16 channels DTC Instruction bus Operand bus Internal main bus 2 Temperature sensor 10-bit D/A converter × 2 channels DOC RAM DMACA × 4 channels RX CPU Internal main bus 1 Clock generation circuit Port J ICU: Interrupt control unit DTC: Data transfer controller DMACA: DMA controller BSC: Bus controller WDT: Watchdog timer IWDT: Independent watchdog timer ELC: Event link controller CRC: CRC (cyclic redundancy check) calculator SCI: Serial communications interface RSPI: RIIC: MTU2: POE2: TMR: CMT: RTC: DOC: CAC: Serial peripheral interface I2C bus interface Multi-function timer pulse unit 2 Port output enable 2 8-bit timer Compare match timer Realtime clock Data operation circuit Clock-frequency accuracy measuring circuit Figure 1.2 Block Diagram R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 8 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 1. Overview 1.4 Pin Functions Table 1.4 lists the pin functions. Table 1.4 Classifications Pin Functions (1 / 4) Pin Name I/O Description Power supply VCC VCL VSS Input Input Input Output Input Output Input Output Input Input Input I/O Input Output I/O Output Output Output Power supply pin. Connect it to the system power supply. Connect this pin to VSS via a 0.1F capacitor. The capacitor should be placed close to the pin. Ground pin. Connect it to the system power supply (0 V). Pins for connecting a crystal resonator. An external clock signal can be input through the EXTAL pin. Outputs the external bus clock for external devices. Input/output pins for the subclock generation circuit. Connect a crystal resonator between XCIN and XCOUT. Pins for setting the operating mode. The signal levels on this pin must not be changed during operation. Reset signal input pin. This LSI enters the reset state when this signal goes low. Input pin for the measuring circuit for clock frequency precision. FINE interface pin. Clock pin for FINE interface. Output pins for the address. Input and output pins for the bidirectional data bus. Strobe signal which indicates that reading from the external bus interface space is in progress. Strobe signal which indicates that writing to the external bus interface space is in progress, in single-write strobe mode. Strobe signals which indicate that either group of data bus pins (D7 to D0, and D15 to D8) is valid in writing to the external bus interface space, in byte strobe mode. Strobe signals which indicate that either group of data bus pins (D7 to D0 and D15 to D8) is valid in access to the external bus interface space, in single-write strobe mode. Select signals for areas 0 to 3. Input pins for wait request signals in access to the external space. Address latch signal when address/data multiplexed bus is selected. Non-maskable interrupt request signal. Interrupt request signals. Clock XTAL EXTAL BCLK XCIN XCOUT Operating mode control System control CAC On-chip emulator MD RES# CACREF FINED FINEC Address bus Data bus Bus control A0 to A23 D0 to D15 RD# WR# WR0#, WR1# BC0#, BC1# Output CS0# to CS3# WAIT# ALE# Interrupt (ICU) NMI IRQ0 to IRQ7 Output Input Output Input Input R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 9 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group Table 1.4 Classifications 1. Overview Pin Functions (2 / 4) Pin Name I/O Description Multi-function timer pulse unit 2 (MTU2) MTIOC0A, MTIOC0B MTIOC0C, MTIOC0D MTIOC1A, MTIOC1B MTIOC2A, MTIOC2B MTIOC3A, MTIOC3B MTIOC3C, MTIOC3D MTIOC4A, MTIOC4B MTIOC4C, MTIOC4D MTIC5U, MTIC5V, MTIC5W MTCLKA, MTCLKB, MTCLKC, MTCLKD I/O I/O I/O I/O I/O Input Input Input Output Input Input Output Input The TGRA0 to TGRD0 input capture input/output compare output/ PWM output pins. The TGRA1 and TGRB1 input capture input/output compare output/ PWM output pins. The TGRA2 and TGRB2 input capture input/output compare output/ PWM output pins. The TGRA3 to TGRD3 input capture input/output compare output/ PWM output pins. The TGRA4 to TGRD4 input capture input/output compare output/ PWM output pins. The TGRU5, TGRV5, and TGRW5 input capture input/external pulse input pins. Input pins for external clock signals. Input pins for request signals to place the MTU2 pins in the high impedance state. Compare match output pins. Input pins for external clocks to be input to the counter. Input pins for the counter reset. Output pin for 1-Hz clock. Tamper resistant event input pins. Port output enable 2 (POE2) 8-bit timer (TMR) POE0# to POE3#, POE8# TMO0 to TMO3 TMCI0 to TMCI3 TMRI0 to TMRI3 Realtime clock (RTC) Serial communications interface (SCIc) RTCOUT RTCIC0 to RTCIC2  Asynchronous mode/clock synchronous mode SCK0, SCK1, SCK5, SCK6, SCK8, SCK9 RXD0, RXD1, RXD5, RXD6, RXD8, RXD9 TXD0, TXD1, TXD5, TXD6, TXD8, TXD9 CTS0#, CTS1#, CTS5#, CTS6#, CTS8#, CTS9# RTS0#, RTS1#, RTS5#, RTS6#, RTS8#, RTS9#  Simple I2C mode I/O Input Output Input Output Input/output pins for clock signals Input pins for received data Output pins for transmitted data Input pins for controlling the start of transmission and reception Output pins for controlling the start of transmission and reception SSCL0, SSCL1, SSCL5, SSCL6, SSCL8, SSCL9 SSDA0, SSDA1, SSDA5, SSDA6, SSDA8, SSDA9  Simple SPI mode I/O I/O Input/output pins for the I2C clock Input/output pins for the I2C data SCK0, SCK1, SCK5, SCK6, SCK8, SCK9 SMISO0, SMISO1, SMISO5, SMISO6, SMISO8, SMISO9 SMOSI0, SMOSI1, SMOSI5, SMOSI6, SMOSI8, SMOSI9 SS0# to SS11# I/O I/O I/O Input Input/output pins for the clock Input/output pins for slave transmission of data Input/output pins for master transmission of data Chip-select input pins R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 10 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group Table 1.4 Classifications 1. Overview Pin Functions (3 / 4) Pin Name I/O Description  Asynchronous mode/clock synchronous mode Serial communications interface (SCId) SCK12 RXD12 TXD12 CTS12# RTS12#  Simple I2C mode I/O Input Output Input Output Input/output pin for the clock signal Input pin for received data Output pin for transmitted data Input pin for controlling the start of transmission and reception Output pin for controlling the start of transmission and reception SSCL12 SSDA12  Simple SPI mode I/O I/O Input/output pin for the I2C clock Input/output pin for the I2C data SCK12 SMISO12 SMOSI12 SS12#  Extended serial mode I/O I/O I/O Input Input/output pin for the clock Input/output pin for slave transmit data Input/output pin for master transmit data Chip-select input pin RXDX12 TXDX12 SIOX12 I2C bus interface (RIIC) SCL SDA Serial peripheral interface (RSPI) RSPCKA MOSIA MISOA SSLA0 SSLA1 to SSLA3 12-bit A/D converter AN000 to AN015 ADTRG0# D/A converter Comparator A DA0, DA1 CMPA1 CMPA2 CVREFA Comparator B CMPB0 CVREFB0 CMPB1 CVREFB1 Input Output I/O I/O I/O I/O I/O I/O I/O Output Input Input Output Input Input Input Input Input Input Input Input pin for data reception by SCId Output pin for data transmission by SCId Input/output pin for data reception or transmission by SCId Input/output pin for I2C bus interface clocks. Bus can be directly driven by the NMOS open drain output. Input/output pin for I2C bus interface data. Bus can be directly driven by the NMOS open drain output. Clock input/output pin for the RSPI. Input or output data output from the master for the RSPI. Input or output data output from the slave for the RSPI. Input/output pin to select the slave for the RSPI. Output pins to select the slave for the RSPI. Input pin for the analog signals to be processed by the A/D converter. Input pin for the external trigger signals that start the A/D conversion. Output pins for the analog signals to be processed by the D/A converter. Input pin for the comparator A1 analog signals. Input pin for the comparator A2 analog signals. Input pin for the comparator reference voltage. Input pin for the comparator B0 analog signals. Input pin for the comparator B0 reference voltage. Input pin for the comparator B1 analog signals. Input pin for the comparator B1 reference voltage. R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 11 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group Table 1.4 Classifications 1. Overview Pin Functions (4 / 4) Pin Name I/O Description Analog power supply AVCC0 AVSS0 VREFH0 VREFL0 VREFH VREFL Input Input Input Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Analog voltage supply pin for the 12-bit A/D converter. Connect this pin to VCC if the 12-bit A/D converter is not to be used. Analog ground pin for the 12-bit A/D converter. Connect this pin to VSS if the 12-bit A/D converter is not to be used. Analog reference voltage supply pin for the 12-bit A/D converter. Connect this pin to VCC if the 12-bit A/D converter is not to be used. Analog reference ground pin for the 12-bit A/D converter. Connect this pin to VSS if the 12-bit A/D converter is not to be used. Analog voltage supply pin for the D/A converter. Connect this pin to VCC if the D/A converter is not to be used. Analog ground pin for the D/A converter. Connect this pin to VSS if the D/A converter is not to be used. 3-bit input/output pins. 6-bit input/output pins. 8-bit input/output pins. 8-bit input/output pins. (P35 input pins) 8-bit input/output pins. 6-bit input/output pins. 8-bit input/output pins. 8-bit input/output pins. 8-bit input/output pins. 8-bit input/output pins. 8-bit input/output pins. 4-bit input/output pins. 2-bit input/output pins. I/O ports P03, P05, P07 P12 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P55 PA0 to PA7 PB0 to PB7 PC0 to PC7 PD0 to PD7 PE0 to PE7 PH0 to PH3 PJ1, PJ3 R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 12 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 1. Overview 1.5 Pin Assignments Figure 1.4 to Figure 1.6 show the pin assignments. Table 1.5 to Table 1.8 show the lists of pins and pin functions. RX210 Group PTLG0100JA-A (100-pin TFLGA) (Upper perspective view) 10 K J H G F E D C B A PC2 PC1 PB7 VCC VSS PA3 PA0 PE4 PE3 PE2 10 9 PC3 PC0 PB6 PB1 PA7 PA5 PA1 PE5 PD7 PE1 9 8 PC5 PC4 PC6 PB4 PB0 PA4 PE7 PD5 PD6 PE0 8 7 P51 P50 PC7 PB5 PB2 PA6 PE6 PD2 PD3 PD4 7 6 PH1 PH3 P54 P52 PB3 PA2 P46 P47 PD1 PD0 6 5 PH2 PH0 P55 P53 P12 P41 P45 P42 P44 P43 5 4 P14 P13 P15 P27 P32 P34 PJ1 3 P20 P17 P16 P30 P35 RES# 2 P22 P21 P25 P31 VCC VSS 1 P23 P24 P26 P33 P36/ EXTAL K J H G F E D C B A P37/ XTAL MD PJ3 XCOUT XCIN VCL P03 P05 1 VREFH0 VREFL P40 AVCC0 AVSS0 VREFL0 P07 3 VREFH 4 2 Note: • This figure indicates the power supply pins and I/O port pins. For the pin configuration, see the table “List of Pins and Pin Functions (100-Pin TFLGA)”. • For the position of A1 pin in the package, see “Package Dimensions”. Figure 1.3 Pin Assignments of the 100-Pin TFLGA (Upper Perspective View) R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 13 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 1. Overview 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Note: • This figure indicates the power supply pins and I/O port pins. For the pin configuration, see the table “List of Pins and Pin Functions (100-Pin LQFP)”. Figure 1.4 Pin Assignments of the 100-Pin LQFP R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 VREFH P03 VREFL PJ3 VCL PJ1 MD XCIN XCOUT RES# P37/XTAL VSS P36/EXTA L VCC P35 P34 P33 P32 P31 P30 P27 P26 P25 P24 P23 25 PE2 PE1 PE0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 P47 P46 P45 P44 P43 P42 P41 VREFL0 P40 VREFH0 AVCC0 P07 AVSS0 P05 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 51 50 49 48 47 46 45 44 43 42 PE3 PE4 PE5 PE6 PE7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 VSS PB0 VCC PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 RX210 Group PLQP0100KB-A (100-pin LQFP) (Top view) 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 PC2 PC3 PC4 PC5 PC6 PC7 P50 P51 P52 P53 P54 P55 PH0 PH1 PH2 PH3 P12 P13 P14 P15 P16 P17 P20 P21 P22 Page 14 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 1. Overview VCC VSS PE3 PE4 PE5 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PB0 PB1 PB2 PB3 PB4 PB5 43 PB6 42 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PE2 PE1 PE0 PD2 PD1 PD0 P47 P46 P45 P44 P43 P42 P41 VREFL0 P40 VREFH0 AVCC0 P07 AVSS0 P05 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 PB7 PC2 PC3 PC4 PC5 PC6 PC7 P54 P55 PH0 PH1 PH2 PH3 P12 P13 P14 P15 P16 P17 P20 P21 RX210 Group PLQP0080KB-A (80-pin LQFP) (Top view) VREFH MD XCIN VREFL RES# P37/XTAL P36/EXTAL XCOUT VCC PJ1 VSS VCL P34 P32 P31 P30 P27 Note: • This figure indicates the power supply pins and I/O port pins. For the pin configuration, see the table “List of Pins and Pin Functions (80-Pin LQFP)”. Figure 1.5 Pin Assignments of the 80-Pin LQFP R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 P03 P26 P35 Page 15 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 1. Overview VCC VSS PE3 PE4 PE5 PA0 PA1 PA3 PA4 PA6 PB0 PB1 PB3 PB5 35 PB6 34 48 47 46 45 44 43 42 41 40 39 38 37 36 PE2 PE1 PE0 VREFL P46 VREFH P44 P43 P42 P41 VREFL0 P40 VREFH0 AVCC0 P05 AVSS0 33 PB7 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 32 31 30 29 28 PC2 PC3 PC4 PC5 PC6 PC7 P54 P55 PH0 PH1 PH2 PH3 P14 P15 P16 P17 RX210 Group PLQP0064KB-A (64-pin LQFP) (Top view) 27 26 25 24 23 22 21 20 19 18 17 XCOUT RES# P37/XTAL VSS P36/EXTAL P03 P35 P32 P31 P30 P27 VCL XCIN Note: • This figure indicates the power supply pins and I/O port pins. For the pin configuration, see the table “List of Pins and Pin Functions (64-Pin LQFP)”. Figure 1.6 Pin Assignments of the 64-Pin LQFP R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 VCC P26 MD Page 16 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group Table 1.5 Pin No. 1. Overview List of Pins and Pin Functions (100-Pin TFLGA) (1 / 3) I/O Port External Bus Timers (MTU2, TMR, POE2) Communications (SCIc, SCId, RSPI, RIIC) Others Power Supply, Clock, System Control A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 E1 E2 E3 E4 E5 E6 XTAL VSS RES# XCIN XCOUT MD VREFH0 VCL VREFL AVSS0 AVCC0 VREFL0 VREFH P05 DA1 P07 ADTRG0# P43 PD0 PD4 PE0 PE1 PE2 P03 D0[A0/D0] D4[A4/D4] D8[A8/D8] D9[A9/D9] D10[A10/D10] MTIOC4C MTIOC4A POE3# SCK12 TXD12/TXDX12/SIOX12/ SMOSI12/SSDA12 RXD12/RXDX12/ SMISO12/SSCL12 AN003 IRQ0 IRQ4 AN008 AN009/CMPB0 IRQ7-DS/AN010/ CVREFB0 DA0 P40 P44 PD1 PD3 PD6 PD7 PE3 D1[A1/D1] D3[A3/D3] D6[A6/D6] D7[A7/D7] D11[A11/D11] MTIOC4B POE8# MTIC5V/POE1# MTIC5U/POE0# MTIOC4B/POE8# CTS12#/RTS12#/SS12# AN000 AN004 IRQ1 IRQ3 IRQ6 IRQ7 AN011/CMPA1 PJ3 MTIOC3C CTS6#/RTS6#/SS6# P42 P47 PD2 PD5 PE5 PE4 D2[A2/D2] D5[A5/D5] D13[A13/D13] D12[A12/D12] MTIOC4D MTIC5W/POE2# MTIOC4C/MTIOC2B MTIOC4D/MTIOC1A AN002 AN007 IRQ2 IRQ5 IRQ5/AN013 AN012/LVCMP2 FINED PJ1 P45 P46 PE6 PE7 PA1 PA0 P37 D14[A14/D14] D15[A15/D15] A1 A0/BC0# MTIOC0B/MTCLKC MTIOC4A SCK5/SSLA2 SSLA1 MTIOC3A AN005 AN006 IRQ6/AN014 IRQ7/AN015 CVREFA CACREF P34 P41 PA2 A2 MTIOC0A/TMCI3/ POE2# SCK6 IRQ4 AN001 RXD5/SMISO5/SSCL5/ SSLA3 R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 17 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group Table 1.5 Pin No. 1. Overview List of Pins and Pin Functions (100-Pin TFLGA) (2 / 3) I/O Port External Bus Timers (MTU2, TMR, POE2) Communications (SCIc, SCId, RSPI, RIIC) Others Power Supply, Clock, System Control E7 E8 E9 E10 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 J1 J2 J3 J4 J5 VCC BCLK VSS EXTAL VCC PA6 PA4 PA5 PA3 P36 A6 A4 A5 A3 MTIC5V/MTCLKB/ TMCI3/POE2# MTIC5U/MTCLKA/ TMRI0 CTS5#/RTS5#/SS5#/ MOSIA TXD5/SMOSI5/SSDA5/ SSLA0 RSPCKA IRQ5-DS/CVREFB1 MTIOC0D/MTCLKD RXD5/SMISO5/SSCL5 IRQ6-DS/CMPB1 P35 P32 P12 PB3 PB2 PB0 PA7 A11 A10 A8 A7 MTIC5W MTIOC0C/TMO3 TMCI1 MTIOC0A/MTIOC4A/ TMO0/POE3# TXD6/SMOSI6/SSDA6 SCL SCK6 CTS6#/RTS6#/SS6# RXD6/SMISO6/SSCL6/ RSPCKA MISOA NMI IRQ2-DS/RTCOUT/ RTCIC2 IRQ2 P33 P31 P30 P27 P53 P52 PB5 PB4 PB1 RD# A13 A12 A9 CS3# MTIOC0D/TMRI3/ POE3# MTIOC4D/TMCI2 MTIOC4B/TMRI3/ POE8# MTIOC2B/TMCI3 RXD6/SMISO6/SSCL6 CTS1#/RTS1#/SS1# RXD1/SMISO1/SSCL1 SCK1 IRQ3-DS IRQ1-DS/RTCIC1 IRQ0-DS/RTCIC0 FINEC MTIOC2A/MTIOC1B/ TMRI1/POE1# SCK9 CTS9#/RTS9#/SS9# MTIOC0C/MTIOC4C/ TMCI0 TXD6/SMOSI6/SSDA6 IRQ4-DS P26 P25 P16 P15 P55 P54 PC7 PC6 PB6 PB7 P24 P21 P17 P13 PH0 CS2# CS1# MTIOC2A/TMO1 MTIOC4C/MTCLKB MTIOC3C/MTIOC3D/ TMO2 MTIOC0B/MTCLKB/ TMCI2 TXD1/SMOSI1/SSDA1 ADTRG0# TXD1/SMOSI1/SSDA1/ MOSIA/SCL-DS RXD1/SMISO1/SSCL1 IRQ6/RTCOUT/ ADTRG0# IRQ5 WAIT# ALE A23/CS0# A22/CS1# A14 A15 CS0# MTIOC4D/TMO3 MTIOC4B/TMCI1 MTIOC3A/TMO2/ MTCLKB MTIOC3C/MTCLKA/ TMCI2 MTIOC3D MTIOC3B MTIOC4A/MTCLKA/ TMRI1 MTIOC1B/TMCI0 MTIOC3A/MTIOC3B/ TMO1/POE8# MTIOC0B/TMO3 RXD0/SMISO0/SSCL0 SCK1/MISOA/ SDA-DS SDA IRQ7 IRQ3 CACREF TXD8/SMOSI8/SSDA8/ MISOA RXD8/SMISO8/SSCL8/ MOSIA RXD9/SMISO9/SSCL9 TXD9/SMOSI9/SSDA9 CACREF R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 18 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group Table 1.5 Pin No. 1. Overview List of Pins and Pin Functions (100-Pin TFLGA) (3 / 3) I/O Port External Bus Timers (MTU2, TMR, POE2) Communications (SCIc, SCId, RSPI, RIIC) Others Power Supply, Clock, System Control J6 J7 J8 J9 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 PH3 P50 PC4 PC0 PC1 P23 P22 P20 P14 PH2 PH1 P51 PC5 PC3 PC2 WR1#/BC1#/WAIT# A21/CS2#/WAIT# A19 A18 WR0#/WR# A20/CS3# A16 A17 TMCI0 MTIOC3D/MTCLKC/ TMCI1/POE0# MTIOC3C MTIOC3A MTIOC3D/MTCLKD MTIOC3B/MTCLKC/ TMO0 MTIOC1A/TMRI0 MTIOC3A/MTCLKA/ TMRI2 TMRI0 TMO0 SCK5/CTS8#/RTS8#/ SS8#/SSLA0 CTS5#/RTS5#/SS5#/ SSLA1 SCK5/SSLA2 CTS0#/RTS0#/SS0# SCK0 TXD0/SMOSI0/SSDA0 CTS1#/RTS1#/SS1# IRQ4 IRQ1 IRQ0 MTIOC3B/MTCLKD/ TMRI2 MTIOC4D MTIOC4B SCK8/RSPCKA TXD5/SMOSI5/SSDA5 RXD5/SMISO5/SSCL5/ SSLA3 Note: • Pin names to which –DS is appended are for pins that can be used to trigger release from deep software standby mode. R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 19 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group Table 1.6 Pin No. 1. Overview List of Pins and Pin Functions (100-Pin LQFP) (1 / 3) I/O Port External Bus Timers (MTU2, TMR, POE2) Communications (SCIc, SCId, RSPI, RIIC) Others Power Supply, Clock, System Control 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 VREFH P03 VREFL PJ3 VCL PJ1 MD XCIN XCOUT RES# XTAL VSS EXTAL VCC P35 P34 P33 P32 P31 P30 P27 P26 P25 P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 PH3 PH2 PH1 PH0 P55 P54 BCLK P53 P52 RD# WAIT# ALE MTIOC4D/TMO3 MTIOC4B/TMCI1 CS3# CS2# CS1# CS0# MTIOC0A/TMCI3/ POE2# MTIOC0D/TMRI3/ POE3# MTIOC0C/TMO3 MTIOC4D/TMCI2 MTIOC4B/TMRI3/ POE8# MTIOC2B/TMCI3 MTIOC2A/TMO1 MTIOC4C/MTCLKB MTIOC4A/MTCLKA/ TMRI1 MTIOC3D/MTCLKD MTIOC3B/MTCLKC/ TMO0 MTIOC1B/TMCI0 MTIOC1A/TMRI0 MTIOC3A/MTIOC3B/ TMO1/POE8# MTIOC3C/MTIOC3D/ TMO2 MTIOC0B/MTCLKB/ TMCI2 MTIOC3A/MTCLKA/ TMRI2 MTIOC0B/TMO3 TMCI1 TMCI0 TMRI0 TMO0 IRQ1 IRQ0 CACREF CTS0#/RTS0#/SS0# SCK0 RXD0/SMISO0/SSCL0 TXD0/SMOSI0/SSDA0 SCK1/MISOA/ SDA-DS TXD1/SMOSI1/SSDA1/ MOSIA/SCL-DS RXD1/SMISO1/SSCL1 CTS1#/RTS1#/SS1# SDA SCL IRQ7 IRQ6/RTCOUT/ ADTRG0# IRQ5 IRQ4 IRQ3 IRQ2 SCK6 RXD6/SMISO6/SSCL6 TXD6/SMOSI6/SSDA6 CTS1#/RTS1#/SS1# RXD1/SMISO1/SSCL1 SCK1 TXD1/SMOSI1/SSDA1 ADTRG0# NMI IRQ4 IRQ3-DS IRQ2-DS/RTCOUT/ RTCIC2 IRQ1-DS/RTCIC1 IRQ0-DS/RTCIC0 FINEC P36 P37 MTIOC3A FINED MTIOC3C CTS6#/RTS6#/SS6# DA0 R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 20 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group Table 1.6 Pin No. 1. Overview List of Pins and Pin Functions (100-Pin LQFP) (2 / 3) I/O Port External Bus Timers (MTU2, TMR, POE2) Communications (SCIc, SCId, RSPI, RIIC) Others Power Supply, Clock, System Control 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 VSS VCC P51 P50 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 WR1#/BC1#/WAIT# WR0#/WR# A23/CS0# A22/CS1# A21/CS2#/WAIT# A20/CS3# A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 MTIOC0C/MTIOC4C/ TMCI0 MTIOC0A/MTIOC4A/ TMO0/POE3# MTIOC3A/TMO2/ MTCLKB MTIOC3C/MTCLKA/ TMCI2 MTIOC3B/MTCLKD/ TMRI2 MTIOC3D/MTCLKC/ TMCI1/POE0# MTIOC4D MTIOC4B MTIOC3A MTIOC3C MTIOC3B MTIOC3D MTIOC2A/MTIOC1B/ TMRI1/POE1# TXD8/SMOSI8/SSDA8/ MISOA RXD8/SMISO8/SSCL8/ MOSIA SCK8/RSPCKA SCK5/CTS8#/RTS8#/ SS8#/SSLA0 TXD5/SMOSI5/SSDA5 RXD5/SMISO5/SSCL5/ SSLA3 SCK5/SSLA2 CTS5#/RTS5#/SS5#/ SSLA1 TXD9/SMOSI9/SSDA9 RXD9/SMISO9/SSCL9 SCK9 CTS9#/RTS9#/SS9# SCK6 CTS6#/RTS6#/SS6# TXD6/SMOSI6/SSDA6 IRQ4-DS CACREF PB0 A8 MTIC5W RXD6/SMISO6/SSCL6/ RSPCKA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PD7 PD6 PD5 A7 A6 A5 A4 A3 A2 A1 A0/BC0# D15[A15/D15] D14[A14/D14] D13[A13/D13] D12[A12/D12] D11[A11/D11] D10[A10/D10] D9[A9/D9] D8[A8/D8] D7[A7/D7] D6[A6/D6] D5[A5/D5] MTIC5U/POE0# MTIC5V/POE1# MTIC5W/POE2# MTIOC4C/MTIOC2B MTIOC4D/MTIOC1A MTIOC4B/POE8# MTIOC4A MTIOC4C MTIOC0B/MTCLKC MTIOC4A MTIC5U/MTCLKA/ TMRI0 MTIOC0D/MTCLKD MTIC5V/MTCLKB/ TMCI3/POE2# MISOA CTS5#/RTS5#/SS5#/ MOSIA RSPCKA TXD5/SMOSI5/SSDA5/ SSLA0 RXD5/SMISO5/SSCL5 RXD5/SMISO5/SSCL5/ SSLA3 SCK5/SSLA2 SSLA1 CVREFA CACREF IRQ7/AN015 IRQ6/AN014 IRQ5/AN013 AN012/LVCMP2 CTS12#/RTS12#/SS12# RXD12/RXDX12/ SMISO12/SSCL12 TXD12/TXDX12/SIOX12/ SMOSI12/SSDA12 SCK12 AN011/CMPA1 IRQ7-DS/AN010/ CVREFB0 AN009/CMPB0 AN008 IRQ7 IRQ6 IRQ5 IRQ5-DS/CVREFB1 IRQ6-DS/CMPB1 R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 21 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group Table 1.6 Pin No. 1. Overview List of Pins and Pin Functions (100-Pin LQFP) (3 / 3) I/O Port External Bus Timers (MTU2, TMR, POE2) Communications (SCIc, SCId, RSPI, RIIC) Others Power Supply, Clock, System Control 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 AVSS0 VREFH0 AVCC0 VREFL0 PD4 PD3 PD2 PD1 PD0 P47 P46 P45 P44 P43 P42 P41 D4[A4/D4] D3[A3/D3] D2[A2/D2] D1[A1/D1] D0[A0/D0] POE3# POE8# MTIOC4D MTIOC4B IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 AN007 AN006 AN005 AN004 AN003 AN002 AN001 P40 AN000 P07 ADTRG0# P05 DA1 Note: • Pin names to which –DS is appended are for pins that can be used to trigger release from deep software standby mode. R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 22 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group Table 1.7 Pin No. 1. Overview List of Pins and Pin Functions (80-Pin LQFP) (1 / 2) Power Supply, Clock, System Control I/O Port Timers (MTU2, TMR, POE2) Communications (SCIc, SCId, RSPI, RIIC) Others 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 VREFH P03 VREFL VCL PJ1 MD XCIN XCOUT RES# XTAL VSS EXTAL VCC P35 P34 P32 P31 P30 P27 P26 P21 P20 P17 P16 P15 P14 P13 P12 PH3 PH2 PH1 PH0 P55 P54 PC7 PC6 PC5 PC4 PC3 PC2 PB7 PB6 PB5 PB4 PB3 MTIOC0A/MTIOC4A/TMO0/ POE3# MTIOC4D/TMO3 MTIOC4B/TMCI1 MTIOC3A/TMO2/MTCLKB MTIOC3C/MTCLKA/TMCI2 MTIOC3B/MTCLKD/TMRI2 MTIOC3D/MTCLKC/TMCI1/ POE0# MTIOC4D MTIOC4B MTIOC3B MTIOC3D MTIOC2A/MTIOC1B/TMRI1/ POE1# TXD8/SMOSI8/SSDA8/MISOA RXD8/SMISO8/SSCL8/MOSIA SCK8/RSPCKA SCK5/CTS8#/RTS8#/SS8#/ SSLA0 TXD5/SMOSI5/SSDA5 RXD5/SMISO5/SSCL5/SSLA3 TXD9/SMOSI9/SSDA9 RXD9/SMISO9/SSCL9 SCK9 CTS9#/RTS9#/SS9# SCK6 CACREF MTIOC0A/TMCI3/POE2# MTIOC0C/TMO3 MTIOC4D/TMCI2 MTIOC4B/TMRI3/POE8# MTIOC2B/TMCI3 MTIOC2A/TMO1 MTIOC1B/TMCI0 MTIOC1A/TMRI0 MTIOC3A/MTIOC3B/TMO1/ POE8# MTIOC3C/MTIOC3D/TMO2 MTIOC0B/MTCLKB/TMCI2 MTIOC3A/MTCLKA/TMRI2 MTIOC0B/TMO3 TMCI1 TMCI0 TMRI0 TMO0 IRQ1 IRQ0 CACREF SCK6 TXD6/SMOSI6/SSDA6 CTS1#/RTS1#/SS1# RXD1/SMISO1/SSCL1 SCK1 TXD1/SMOSI1/SSDA1 RXD0/SMISO0/SSCL0 TXD0/SMOSI0/SSDA0 SCK1/MISOA/ SDA-DS TXD1/SMOSI1/SSDA1/MOSIA/ SCL-DS RXD1/SMISO1/SSCL1 CTS1#/RTS1#/SS1# SDA SCL IRQ7 IRQ6/RTCOUT/ ADTRG0# IRQ5 IRQ4 IRQ3 IRQ2 NMI IRQ4 IRQ2-DS/RTCOUT/ RTCIC2 IRQ1-DS/RTCIC1 IRQ0-DS/RTCIC0 FINEC P36 P37 MTIOC3A FINED DA0 R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 23 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group Table 1.7 Pin No. 1. Overview List of Pins and Pin Functions (80-Pin LQFP) (2 / 2) Power Supply, Clock, System Control I/O Port Timers (MTU2, TMR, POE2) Communications (SCIc, SCId, RSPI, RIIC) Others 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 AVSS0 VREFH0 AVCC0 VREFL0 VSS VCC PB2 PB1 MTIOC0C/MTIOC4C/TMCI0 CTS6#/RTS6#/SS6# TXD6/SMOSI6/SSDA6 IRQ4-DS PB0 MTIC5W RXD6/SMISO6/SSCL6/RSPCKA PA6 PA5 PA4 PA3 PA2 PA1 PA0 PE5 PE4 PE3 PE2 PE1 PE0 PD2 PD1 PD0 P47 P46 P45 P44 P43 P42 P41 MTIC5V/MTCLKB/TMCI3/ POE2# CTS5#/RTS5#/SS5#/MOSIA RSPCKA MTIC5U/MTCLKA/TMRI0 MTIOC0D/MTCLKD TXD5/SMOSI5/SSDA5/SSLA0 RXD5/SMISO5/SSCL5 RXD5/SMISO5/SSCL5/SSLA3 IRQ5-DS/CVREFB1 IRQ6-DS/CMPB1 MTIOC0B/MTCLKC MTIOC4A MTIOC4C/MTIOC2B MTIOC4D/MTIOC1A MTIOC4B/POE8# MTIOC4A MTIOC4C SCK5/SSLA2 SSLA1 CVREFA CACREF IRQ5/AN013 AN012/LVCMP2 CTS12#/RTS12#/SS12# RXD12/RXDX12/SMISO12/ SSCL12 TXD12/TXDX12/SIOX12/ SMOSI12/SSDA12 SCK12 AN011/CMPA1 IRQ7-DS/AN010/ CVREFB0 AN009/CMPB0 AN008 IRQ2 IRQ1 IRQ0 AN007 AN006 AN005 AN004 AN003 AN002 AN001 MTIOC4D MTIOC4B P40 AN000 P07 ADTRG0# P05 DA1 Note: • Pin names to which –DS is appended are for pins that can be used to trigger release from deep software standby mode. R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 24 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group Table 1.8 Pin No. 1. Overview List of Pins and Pin Functions (64-Pin LQFP) (1 / 2) Power Supply, Clock, System Control I/O Port Timers (MTU2, TMR, POE2) Communication (SCIc, SCId, RSPI, RIIC) Others 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 VSS VCC VCL MD XCIN XCOUT RES# XTAL VSS EXTAL VCC P03 DA0 FINED P37 P36 P35 P32 P31 P30 P27 P26 P17 P16 P15 P14 PH3 PH2 PH1 PH0 P55 P54 PC7 PC6 PC5 PC4 PC3 PC2 PB7 PB6 PB5 PB3 PB1 MTIOC4D/TMO3 MTIOC4B/TMCI1 MTIOC3A/TMO2/MTCLKB MTIOC3C/MTCLKA/TMCI2 MTIOC3B/MTCLKD/TMRI2 MTIOC3D/MTCLKC/TMCI1/ POE0# MTIOC4D MTIOC4B MTIOC3B MTIOC3D MTIOC2A/MTIOC1B/TMRI1/ POE1# MTIOC0A/MTIOC4A/TMO0/ POE3# MTIOC0C/MTIOC4C/TMCI0 TXD8/SMOSI8/SSDA8/MISOA RXD8/SMISO8/SSCL8/MOSIA SCK8/RSPCKA SCK5/CTS8#/RTS8#/SS8#/ SSLA0 TXD5/SMOSI5/SSDA5 RXD5/SMISO5/SSCL5/SSLA3 TXD9/SMOSI9/SSDA9 RXD9/SMISO9/SSCL9 SCK9 SCK6 TXD6/SMOSI6/SSDA6 MTIOC0C/TMO3 MTIOC4D/TMCI2 MTIOC4B/TMRI3/POE8# MTIOC2B/TMCI3 MTIOC2A/TMO1 MTIOC3A/MTIOC3B/TMO1/ POE8# MTIOC3C/MTIOC3D/TMO2 MTIOC0B/MTCLKB/TMCI2 MTIOC3A/MTCLKA/TMRI2 TMCI0 TMRI0 TMO0 TXD6/SMOSI6/SSDA6 CTS1#/RTS1#/SS1# RXD1/SMISO1/SSCL1 SCK1 TXD1/SMOSI1/SSDA1 SCK1/MISOA/SDA-DS TXD1/SMOSI1/SSDA1/MOSIA/ SCL-DS RXD1/SMISO1/SSCL1 CTS1#/RTS1#/SS1# NMI IRQ2-DS/RTCOUT/ RTCIC2 IRQ1-DS/RTCIC1 IRQ0-DS/RTCIC0 FINEC IRQ7 IRQ6/RTCOUT/ ADTRG0# IRQ5 IRQ4 IRQ1 IRQ0 CACREF CACREF IRQ4-DS PB0 MTIC5W RXD6/SMISO6/SSCL6/RSPCKA PA6 PA4 PA3 PA1 MTIC5V/MTCLKB/TMCI3/ POE2# MTIC5U/MTCLKA/TMRI0 MTIOC0D/MTCLKD MTIOC0B/MTCLKC CTS5#/RTS5#/SS5#/MOSIA TXD5/SMOSI5/SSDA5/SSLA0 RXD5/SMISO5/SSCL5 SCK5/SSLA2 IRQ5-DS/CVREFB1 IRQ6-DS/CMPB1 CVREFA R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 25 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group Table 1.8 Pin No. 1. Overview List of Pins and Pin Functions (64-Pin LQFP) (2 / 2) Power Supply, Clock, System Control I/O Port Timers (MTU2, TMR, POE2) Communication (SCIc, SCId, RSPI, RIIC) Others 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 AVSS0 VREFH0 AVCC0 VREFL0 VREFH VREFL PA0 PE5 PE4 PE3 PE2 PE1 PE0 MTIOC4A MTIOC4C/MTIOC2B MTIOC4D/MTIOC1A MTIOC4B/POE8# MTIOC4A MTIOC4C SSLA1 CACREF IRQ5/AN013 AN012/LVCMP2 CTS12#/RTS12#/SS12# RXD12/RXDX12/SMISO12/ SSCL12 TXD12/TXDX12/SIOX12/ SMOSI12/SSDA12 SCK12 AN011/CMPA1 IRQ7-DS/AN010/ CVREFB0 AN009/CMPB0 AN008 P46 AN006 P44 P43 P42 P41 AN004 AN003 AN002 AN001 P40 AN000 P05 DA1 Note: • Pin names to which –DS is appended are for pins that can be used to trigger release from deep software standby mode. R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 26 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 2. CPU 2. CPU The RX210 Group is an MCU with the high-speed, high-performance RX CPU as its core. A variable-length instruction format has been adopted for the RX CPU. Allocating the more frequently used instructions to the shorter instruction lengths facilitates the development of efficient programs that take up less memory. The CPU has 73 basic instructions and and nine DSP instructions, for a total of 82 instructions. It has 10 addressing modes and caters to register–register operations, register–memory operations, immediate–register operations, immediate–memory operations, memory–memory transfer, and bitwise operations. High-speed operation was realized by achieving execution in a single cycle not only for register–register operations, but also for other types of multiple instructions. The CPU includes an internal multiplier and an internal divider for high-speed multiplication and division. The RX CPU has a five-stage pipeline for processing instructions. The stages are instruction fetching, instruction decoding, execution, memory access, and write-back. In cases where pipeline processing is drawn-out by memory access, subsequent operations may in fact be executed earlier. By adopting “out-of-order completion” of this kind, the execution of instructions is controlled to optimize numbers of clock cycles. 2.1 Features  High instruction execution rate: One instruction in one clock cycle  Address space: 4-Gbyte linear  Register set of the CPU General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit register  Basic instructions: 73 (arithmetic/logic instructions, data-transfer instructions, branch instructions, bit-manipulation instructions, string-manipulation instructions, and system-manipulation instructions) Relative branch instructions to suit branch distances Variable-length instruction format (lengths from one to eight bytes) Short formats for frequently used instructions  DSP instructions: 9 Supports 16-bit  16-bit multiplication and multiply-and-accumulate operations. Rounds the data in the accumulator.  Addressing modes: 10  Five-stage pipeline Adoption of out-of-order completion  Processor modes A supervisor mode and a user mode are supported.  Data arrangement Selectable as little endian or big endian R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 27 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 2. CPU 2.2 Register Set of the CPU The RX CPU has sixteen general-purpose registers, eight control registers, and one accumulator used for DSP instructions. General-purpose register b31 R0 (SP) *1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 b0 Control register b31 ISP USP INTB PC PSW BPC BPSW FINTV (Interrupt stack pointer) (User stack pointer) (Interrupt table register) (Program counter) (Processor status word) (Backup PC) (Backup PSW) (Fast interrupt vector register) b0 DSP instruction register b63 ACC (Accumulator) Note 1. The stack pointer (SP) can be the interrupt stack pointer (ISP) or user stack pointer (USP), according to the value of the U bit in the PSW register. b0 Figure 2.1 Register Set of the CPU R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 28 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 2. CPU 2.2.1 General-Purpose Registers (R0 to R15) This CPU has sixteen general-purpose registers (R0 to R15). R1 to R15 can be used as data registers or address registers. R0, a general-purpose register, also functions as the stack pointer (SP). The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the stack pointer select bit (U) in the processor status word (PSW). 2.2.2 Control Registers This CPU has the following eight control registers.  Interrupt stack pointer (ISP)  User stack pointer (USP)  Interrupt table register (INTB)  Program counter (PC)  Processor status word (PSW)  Backup PC (BPC)  Backup PSW (BPSW)  Fast interrupt vector register (FINTV) R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 29 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 2. CPU 2.2.2.1 Interrupt Stack Pointer (ISP)/User Stack Pointer (USP) b31 b0 ISP Value after reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b0 b31 USP Value after reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The stack pointer (SP) can be either of two types, the interrupt stack pointer (ISP) or the user stack pointer (USP). Whether the stack pointer operates as the ISP or USP depends on the value of the stack pointer select bit (U) in the processor status word (PSW). Set the ISP or USP to a multiple of four, as this reduces the numbers of cycles required to execute interrupt sequences and instructions entailing stack manipulation. 2.2.2.2 Interrupt Table Register (INTB) b31 b0 Value after reset: Undefined The interrupt table register (INTB) specifies the address where the relocatable vector table starts. 2.2.2.3 Program Counter (PC) b31 b0 Value after reset: Contents of addresses FFFFFFFCh to FFFFFFFFh The program counter (PC) indicates the address of the instruction being executed. R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 30 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 2. CPU 2.2.2.4 Processor Status Word (PSW) b31 — b30 — 0 b14 — 0 b29 — 0 b13 — 0 b28 — 0 b12 — 0 0 b11 — 0 b27 b26 b25 b24 b23 — 0 b8 — 0 0 b7 — 0 b22 — 0 b6 — 0 b21 — 0 b5 — 0 b20 PM 0 b4 — 0 b19 — 0 b3 O 0 b18 — 0 b2 S 0 b17 U 0 b1 Z 0 b16 I 0 b0 C 0 IPL[3:0] 0 b10 — 0 0 b9 — 0 Value after reset: 0 b15 — Value after reset: 0 Bit Symbol Bit Name Description R/W b0 b1 b2 b3 b15 to b4 b16 b17 b19, b18 b20 C Z S O — I*1 U*1 — PM*1,*2,*3 Carry Flag Zero Flag Sign Flag Overflow Flag Reserved Interrupt Enable Stack Pointer Select Reserved Processor Mode Select Reserved Processor Interrupt Priority Level 0: No carry has occurred. 1: A carry has occurred. 0: Result is non-zero. 1: Result is 0. 0: Result is a positive value or 0. 1: Result is a negative value. 0: No overflow has occurred. 1: An overflow has occurred. R/W R/W R/W R/W These bits are always read as 0. The write value should be 0. R/W 0: Interrupt disabled. 1: Interrupt enabled. 0: Interrupt stack pointer (ISP) is selected. 1: User stack pointer (USP) is selected. R/W R/W These bits are always read as 0. The write value should be 0. R/W 0: Supervisor mode is selected. 1: User mode is selected. R/W b23 to b21 — b27 to b24 IPL[3:0]*1 These bits are always read as 0. The write value should be 0. R/W b27 b24 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0: Priority level 0 (lowest) 1: Priority level 1 0: Priority level 2 1: Priority level 3 0: Priority level 4 1: Priority level 5 0: Priority level 6 1: Priority level 7 0: Priority level 8 1: Priority level 9 0: Priority level 10 1: Priority level 11 0: Priority level 12 1: Priority level 13 0: Priority level 14 1: Priority level 15 (highest) R/W b31 to b28 — Reserved These bits are always read as 0. The write value should be 0. R/W Note 1. In user mode, writing to the IPL[3:0], PM, U, and I bits by an MVTC or a POPC instruction is ignored. Writing to the IPL[3:0] bits by an MVTIPL instruction generates a privileged instruction exception. Note 2. In supervisor mode, writing to the PM bit by an MVTC or a POPC instruction is ignored, but writing to the other bits is possible. Note 3. Switching from supervisor mode to user mode requires execution of an RTE instruction after having set the PSW.PM bit saved on the stack to 1 or executing an RTFI instruction after having set the BPSW.PM bit to 1. R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 31 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group The processor status word (PSW) indicates the results of instruction execution or the state of the CPU. C Flag (Carry Flag) This flag indicates whether a carry, borrow, or shift-out has occurred as the result of an operation. Z Flag (Zero Flag) This flag indicates that the result of an operation was 0. S Flag (Sign Flag) This flag indicates that the result of an operation was negative. O Flag (Overflow Flag) This flag indicates that an overflow occurred during an operation. I Bit (Interrupt Enable) This bit enables interrupt requests. When an exception is accepted, the value of this bit becomes 0. U Bit (Stack Pointer Select) 2. CPU This bit specifies the stack pointer as either the ISP or USP. When an exception request is accepted, this bit is set to 0. When the processor mode is switched from supervisor mode to user mode, this bit is set to 1. PM Bit (Processor Mode Select) This bit specifies the processor mode. When an exception is accepted, the value of this bit becomes 0. IPL[3:0] Bits (Processor Interrupt Priority Level) The IPL[3:0] bits specify the processor interrupt priority level as one of sixteen levels from zero to fifteen, wherein priority level zero is the lowest and priority level fifteen the highest. When the priority level of a requested interrupt is higher than the processor interrupt priority level, the interrupt is enabled. Setting the IPL[3:0] bits to level fifteen (Fh) disables all interrupt requests. The IPL[3:0] bits are set to level fifteen (Fh) when a non-maskable interrupt is generated. When interrupts in general are generated, the bits are set to the priority levels of accepted interrupts. 2.2.2.5 Backup PC (BPC) b31 b0 Value after reset: Undefined The backup PC (BPC) is provided to speed up response to interrupts. After a fast interrupt has been generated, the contents of the program counter (PC) are saved in the BPC register. R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 32 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 2. CPU 2.2.2.6 Backup PSW (BPSW) b31 b0 Value after reset: Undefined The backup PSW (BPSW) is provided to speed up response to interrupts. After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in the BPSW. The allocation of bits in the BPSW corresponds to that in the PSW. 2.2.2.7 Fast Interrupt Vector Register (FINTV) b31 b0 Value after reset: Undefined The fast interrupt vector register (FINTV) is provided to speed up response to interrupts. The FINTV register specifies a branch destination address when a fast interrupt has been generated. 2.2.3 2.2.3.1 Register Associated with DSP Instructions Accumulator (ACC) Range for reading by MVFACMI b63 b48 b47 b32 b31 b16 b15 b0 Range for reading and writing by MVTACHI and MVFACHI Value after reset: Undefined Range for writing by MVTACLO The accumulator (ACC) is a 64-bit register used for DSP instructions. The accumulator is also used for the multiply and multiply-and-accumulate instructions; EMUL, EMULU, MUL, and RMPA, in which case the prior value in the accumulator is modified by execution of the instruction. Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The MVTACHI and MVTACLO instructions write data to the higher-order 32 bits (bits 63 to 32) and the lower-order 32 bits (bits 31 to 0), respectively. Use the MVFACHI and MVFACMI instructions for reading data from the accumulator. The MVFACHI and MVFACMI instructions read data from the higher-order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively. R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 33 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 2. CPU 2.3 Processor Mode The RX CPU supports two processor modes, supervisor and user. These processor modes enable the realization of a hierarchical CPU resource protection. Each processor mode imposes a level on rights of access to the CPU resources and the instructions that can be executed. Supervisor mode carries greater rights than those of user mode. The initial state after a reset is supervisor mode. 2.3.1 Supervisor Mode In supervisor mode, all CPU resources are accessible and all instructions are available. However, writing to the processor mode select bit (PM) in the processor status word (PSW) by executing an MVTC or a POPC instruction will be ignored. For details on how to write to the PM bit, refer to section 2.2.2.4, Processor Status Word (PSW). 2.3.2 User Mode In user mode, write access to the CPU resources listed below is restricted. The restriction applies to any instruction capable of write access.  Some bits (bits IPL[3:0], PM, U, and I) in the processor status word (PSW)  Interrupt stack pointer (ISP)  Interrupt table register (INTB)  Backup PSW (BPSW)  Backup PC (BPC)  Fast interrupt vector register (FINTV) 2.3.3 Privileged Instruction Privileged instructions can only be executed in supervisor mode. Executing a privileged instruction in user mode produces a privileged instruction exception. Privileged instructions include the RTFI, MVTIPL, RTE, and WAIT instructions. 2.3.4 Switching Between Processor Modes Manipulating the processor mode select bit (PM) in the processor status word (PSW) switches the processor mode. However, rewriting to the PM bit by executing an MVTC or a POPC instruction is prohibited. Switch the processor mode by following the procedures described below. (1) Switching from user mode to supervisor mode After an exception has been generated, the PSW.PM bit is set to 0 and the CPU switches to supervisor mode. The hardware pre-processing is executed in supervisor mode. The state of the processor mode before the exception was generated is retained in the the copy of PSW.PM bit is saved on the stack. (2) Switching from supervisor mode to user mode Executing an RTE instruction when the value of the copy of the PSW.PM bit that has been preserved on the stack is 1 or an RTFI instruction when the value of the copy of the PSW.PM bit that has been preserved in the backup PSW (BPSW) is 1 causes a transition to user mode. In the transition to user mode, the value of the stack pointer designation bit (the U bit in the PSW) becomes 1. R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 34 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 2. CPU 2.4 Data Types The RX CPU can handle three types of data: integer, bit, and string. 2.4.1 Integer An integer can be signed or unsigned. For signed integers, negative values are represented by two's complements. Signed byte (8-bit) integer b7 S b7 b0 b0 Unsigned byte (8-bit) integer b15 S b15 Unsigned word (16-bit) integer b31 S b31 Unsigned longword (32-bit) integer S: Signed bit b0 b0 Signed word (16-bit) integer b0 Signed longword (32-bit) integer b0 Figure 2.2 Integer R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 35 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 2. CPU 2.4.2 Bitwise Operations Five bit-manipulation instructions are provided for bitwise operations: BCLR, BMCnd, BNOT, BSET, and BTST. A bit in a register is specified as the destination register and a bit number in the range from 31 to 0. A bit in memory is specified as the destination address and a bit number from 7 to 0. The addressing modes available to specify addresses are register indirect and register relative. Register b31 #bit, Rn (bit: 31 to 0, n: 0 to 15) b0 Example #30,R1 (register R1, bit 30) Memory b7 #bit, mem (bit: 7 to 0) b0 Example #2,[R2] (address [R2], bit 2) Figure 2.3 Bit 2.4.3 Strings The string data type consists of an arbitrary number of consecutive byte (8-bit), word (16-bit), or longword (32-bit) units. Seven string manipulation instructions are provided for use with strings: SCMPU, SMOVB, SMOVF, SMOVU, SSTR, SUNTIL, and SWHILE. String of byte (8-bit) data 8 String of word (16-bit) data 16 String of longword (32-bit) data 32 Figure 2.4 String R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 36 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 2. CPU 2.5 Endian For the RX CPU, instructions are always little endian, but the treatment of data is selectable as little or big endian. 2.5.1 Switching the Endian As arrangements of bytes, the RX210 Group supports both big endian, where the higher-order byte (MSB) is at location 0, and little endian, where the lower-order byte (LSB) is at location 0. For details on the endian setting, see section 3, Operating Modes. Operations for access differ according to the endian setting and, depending on the instruction, whether 8-, 16- or 32-bit access has been selected. Operations for access in the various possible cases are described in Table 2.1 to Table 2.12. In the tables, LL indicates bits D7 to D0 of the general-purpose register, LH indicates bits D15 to D8 of the general-purpose register, HL indicates bits D23 to D16 of the general-purpose register, and HH indicates bits D31 to D24 of the general-purpose register. D31 to D24 D23 to D16 D15 to D8 D7 to D0 General purpose register: Rm HH HL LH LL Table 2.1 32-Bit Read Operations when Little Endian has been Selected Operation Reading a 32-bit unit Reading a 32-bit unit Reading a 32-bit unit Reading a 32-bit unit Reading a 32-bit unit from address 0 from address 1 from address 2 from address 3 from address 4 Transfer to LL Transfer to LH Transfer to HL Transfer to HH — — — — — Transfer to LL Transfer to LH Transfer to HL Transfer to HH — — — — — Transfer to LL Transfer to LH Transfer to HL Transfer to HH — — — — — Transfer to LL Transfer to LH Transfer to HL Transfer to HH — — — — — Transfer to LL Transfer to LH Transfer to HL Transfer to HH Address of src Address 0 Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Table 2.2 32-Bit Read Operations when Big Endian has been Selected Operation Reading a 32-bit unit Reading a 32-bit unit Reading a 32-bit unit Reading a 32-bit unit Reading a 32-bit unit from address 0 from address 1 from address 2 from address 3 from address 4 Transfer to HH Transfer to HL Transfer to LH Transfer to LL — — — — — Transfer to HH Transfer to HL Transfer to LH Transfer to LL — — — — — Transfer to HH Transfer to HL Transfer to LH Transfer to LL — — — — — Transfer to HH Transfer to HL Transfer to LH Transfer to LL — — — — — Transfer to HH Transfer to HL Transfer to LH Transfer to LL Address of src Address 0 Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 37 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 2. CPU Table 2.3 32-Bit Write Operations when Little Endian has been Selected Operation Address of dest Address 0 Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Writing a 32-bit unit to address 0 Transfer from LL Transfer from LH Transfer from HL Transfer from HH — — — — Writing a 32-bit unit to address 1 — Transfer from LL Transfer from LH Transfer from HL Transfer from HH — — — Writing a 32-bit unit to address 2 — — Transfer from LL Transfer from LH Transfer from HL Transfer from HH — — Writing a 32-bit unit to address 3 — — — Transfer from LL Transfer from LH Transfer from HL Transfer from HH — Writing a 32-bit unit to address 4 — — — — Transfer from LL Transfer from LH Transfer from HL Transfer from HH Table 2.4 32-Bit Write Operations when Big Endian has been Selected Operation Address of dest Address 0 Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Writing a 32-bit unit to address 0 Transfer from HH Transfer from HL Transfer from LH Transfer from LL — — — — Writing a 32-bit unit to address 1 — Transfer from HH Transfer from HL Transfer from LH Transfer from LL — — — Writing a 32-bit unit to address 2 — — Transfer from HH Transfer from HL Transfer from LH Transfer from LL — — Writing a 32-bit unit to address 3 — — — Transfer from HH Transfer from HL Transfer from LH Transfer from LL — Writing a 32-bit unit to address 4 — — — — Transfer from HH Transfer from HL Transfer from LH Transfer from LL R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 38 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 2. CPU Table 2.5 Operation Address of src 16-Bit Read Operations when Little Endian has been Selected Reading Reading Reading Reading Reading Reading Reading a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from address 0 address 1 address 2 address 3 address 4 address 5 address 6 Address 0 Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Transfer to LL Transfer to LH — — — — — — — Transfer to LL Transfer to LH — — — — — — — Transfer to LL Transfer to LH — — — — — — — Transfer to LL Transfer to LH — — — — — — — Transfer to LL Transfer to LH — — — — — — — Transfer to LL Transfer to LH — — — — — — — Transfer to LL Transfer to LH Table 2.6 Operation Address of src 16-Bit Read Operations when Big Endian has been Selected Reading Reading Reading Reading Reading Reading Reading a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from address 0 address 1 address 2 address 3 address 4 address 5 address 6 Address 0 Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Transfer to LH Transfer to LL — — — — — — — Transfer to LH Transfer to LL — — — — — — — Transfer to LH Transfer to LL — — — — — — — Transfer to LH Transfer to LL — — — — — — — Transfer to LH Transfer to LL — — — — — — — Transfer to LH Transfer to LL — — — — — — — Transfer to LH Transfer to LL R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 39 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 2. CPU Table 2.7 Operation Address of dest 16-Bit Write Operations when Little Endian has been Selected Writing a 16-bit unit to address 0 Writing a 16-bit unit to address 1 Writing a 16-bit unit to address 2 Writing a 16-bit unit to address 3 Writing a 16-bit unit to address 4 Writing a 16-bit unit to address 5 Writing a 16-bit unit to address 6 Address 0 Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Transfer from LL Transfer from LH — — — — — — — Transfer from LL Transfer from LH — — — — — — — Transfer from LL Transfer from LH — — — — — — — Transfer from LL Transfer from LH — — — — — — — Transfer from LL Transfer from LH — — — — — — — Transfer from LL Transfer from LH — — — — — — — Transfer from LL Transfer from LH Table 2.8 Operation Address of dest 16-Bit Write Operations when Big Endian has been Selected Writing a 16-bit unit to address 0 Writing a 16-bit unit to address 1 Writing a 16-bit unit to address 2 Writing a 16-bit unit to address 3 Writing a 16-bit unit to address 4 Writing a 16-bit unit to address 5 Writing a 16-bit unit to address 6 Address 0 Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Transfer from LL Transfer from LH — — — — — — — Transfer from LL Transfer from LH — — — — — — — Transfer from LL Transfer from LH — — — — — — — Transfer from LL Transfer from LH — — — — — — — Transfer from LL Transfer from LH — — — — — — — Transfer from LL Transfer from LH — — — — — — — Transfer from LL Transfer from LH R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 40 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 2. CPU Table 2.9 Address of src 8-Bit Read Operations when Little Endian has been Selected Operation Reading an 8-bit unit from address 0 Reading an 8-bit unit from address 1 Reading an 8-bit unit from address 2 Reading an 8-bit unit from address 3 Address 0 Address 1 Address 2 Address 3 Transfer to LL — — — — Transfer to LL — — — — Transfer to LL — — — — Transfer to LL Table 2.10 Address of src 8-Bit Read Operations when Big Endian has been Selected Operation Reading an 8-bit unit from address 0 Reading an 8-bit unit from address 1 Reading an 8-bit unit from address 2 Reading an 8-bit unit from address 3 Address 0 Address 1 Address 2 Address 3 Transfer to LL — — — — Transfer to LL — — — — Transfer to LL — — — — Transfer to LL Table 2.11 8-Bit Write Operations when Little Endian has been Selected Operation Writing an 8-bit unit to address 0 Writing an 8-bit unit to address 1 Writing an 8-bit unit to address 2 Writing an 8-bit unit to address 3 Address of dest Address 0 Address 1 Address 2 Address 3 Transfer from LL — — — — Transfer from LL — — — — Transfer from LL — — — — Transfer from LL Table 2.12 8-Bit Write Operations when Big Endian has been Selected Operation Writing an 8-bit unit to address 0 Writing an 8-bit unit to address 1 Writing an 8-bit unit to address 2 Writing an 8-bit unit to address 3 Address of dest Address 0 Address 1 Address 2 Address 3 Transfer from LL — — — — Transfer from LL — — — — Transfer from LL — — — — Transfer from LL 2.5.2 Access to I/O Registers The addresses of I/O registers are fixed, and this is regardless of whether the setting is for little endian or big endian. Accordingly, changes to the endian do not affect access to I/O registers. For the arrangements of I/O registers, refer to the descriptions of registers in the relevant sections. R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 41 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 2. CPU 2.5.3 Notes on Access to I/O Registers Ensure that access to I/O registers is in accord with the following rules.  With I/O registers for which a bus width of eight bits is indicated, use instructions having operands of the same width (eight bits). That is, access these registers by using instructions with .B as the size specifier (.size), or with .B or .UB as the size-extension specifier (.memex).  With I/O registers for which a bus width of 16 bits is indicated, use instructions having operands of the same width (16 bits). That is, access these registers by using instructions with .W as the size specifier (.size), or with .W or .UW as the size-extension specifier (.memex).  With I/O registers for which a bus width of 32 bits is indicated, use instructions having operands of the same width (32 bits). That is, access these registers by using instructions with .L as the size specifier (.size), or with .L sizeextension specifier (.memex). R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 42 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 2. CPU 2.5.4 2.5.4.1 Data Arrangement Data Arrangement in Registers Figure 2.5 shows the relation between the sizes of registers and bit numbers. b7 Byte (8-bit) data b15 Word (16-bit) data b31 Longword (32-bit) data MSB b0 b0 b0 LSB Figure 2.5 Data Arrangement in Registers 2.5.4.2 Data Arrangement in Memory Data in memory have three sizes: byte (8-bit), word (16-bit), and longword (32-bit). The data arrangement is selectable as little endian or big endian. Figure 2.6 shows the arrangement of data in memory. Data type Address Data image (Little endian) Data image (Big endian) b7 1-bit data Address L b0 6 5 4 3 2 1 0 b7 7 6 5 4 3 2 1 b0 0 7 Byte data Address L MSB LSB MSB LSB Word data Address M Address M+1 LSB MSB MSB LSB Longword data Address N Address N+1 Address N+2 Address N+3 LSB MSB MSB LSB Figure 2.6 Data Arrangement in Memory 2.5.5 Notes on the Allocation of Instruction Codes The allocation of instruction codes to an external space where the endian differs from that of the chip is prohibited. If the instruction codes are allocated to the external space, they must be allocated to areas where the endian setting is the same as that for the chip. R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 43 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 2. CPU 2.6 Vector Table There are two types of vector table: fixed and relocatable. Each vector in the vector table consists of four bytes and specifies the address where the corresponding exception handling routine starts. 2.6.1 Fixed Vector Table The fixed vector table is allocated to a fixed address range. The individual vectors for the privileged instruction exception, undefined instruction exception, non-maskable interrupt, and reset are allocated to addresses in the range from FFFFFF80h to FFFFFFFFh. Figure 2.7 shows the fixed vector table. MSB FFFFFF80h (Reserved) LSB FFFFFFCCh FFFFFFD0h FFFFFFD4h FFFFFFD8h FFFFFFDCh FFFFFFE0h FFFFFFE4h FFFFFFE8h FFFFFFECh FFFFFFF0h FFFFFFF4h FFFFFFF8h FFFFFFFCh (Reserved) Privileged instruction exception (Reserved) (Reserved) Undefined instruction exception (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Non-maskable interrupt Reset Figure 2.7 Fixed Vector Table R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 44 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 2. CPU 2.6.2 Relocatable Vector Table The address where the relocatable vector table is placed can be adjusted. The table is a 1,024-byte region that contains all vectors for unconditional traps and interrupts and starts at the address (IntBase) specified in the interrupt table register (INTB). Figure 2.8 shows the relocatable vector table. Each vector in the relocatable vector table has a vector number from 0 to 255. Each of the INT instructions, which act as the sources of unconditional traps, is allocated to the vector that has the same number as is specified as the operand of the instruction itself (from 0 to 255). The BRK instruction is allocated to the vector with number 0. Furthermore, vector numbers (from 0 to 255) are allocated to interrupt requests in a fixed way for each product. For more on interrupt vector numbers, see section 14.3.1, Interrupt Vector Table. b31 INTB IntBase b0 IntBase+4 IntBase+8 0 1 2 Interrupt vectors are allocated in this order. IntBase+1020 255 Figure 2.8 Relocatable Vector Table R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 45 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 2. CPU 2.7 2.7.1 Operation of Instructions Data Prefetching by the RMPA Instruction and the String-Manipulation Instructions The RMPA instruction and the string-manipulation instructions except the SSTR instruction (that is, SCMPU, SMOVB, SMOVF, SMOVU, SUNTIL, and SWHILE instructions) may prefetch data from the memory to speed up the read processing. Data is prefetched from the prefetching start position with three bytes as the upper limit. The prefetching start positions of each operation are shown below.  RMPA instruction: The multiplicand address specified by R1, and the multiplier address specified by R2  SCMPU instruction: The source address specified by R1 for comparison, and the destination address specified by R2 for comparison  SUNTIL and SWHILE instructions: The destination address specified by R1 for comparison  SMOVB, SMOVF, and SMOVU instructions: The source address specified by R2 for transfer R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 46 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 2. CPU 2.8 2.8.1 Pipeline Overview The RX CPU has 5-stage pipeline structure. The RX CPU instruction is converted into one or more micro-operations, which are then executed in pipeline processing. In the pipeline stage, the IF stage is executed in the unit of instructions, while the D and subsequent stages are executed in the unit of micro-operations. The operation of pipeline and respective stages is described below. (1) IF stage (instruction fetch stage) In the IF stage, the CPU fetches instructions from the memory. As the RX CPU has four 4-byte instruction queues, it fetches instructions until the instruction queue is full, regardless of the completion of decoding in the D (decoding) stage. (2) D stage (decoding stage) The CPU decodes instructions in the D stage and converts them into micro-operations. The CPU reads the register information (RF) in this stage and executes a bypass process (BYP) if the result of the preceding instruction will be used in a subsequent instruction. The write of operation result to the register (RW) can be executed with the register reference by using the bypass process. (3) E stage (execution stage) Operations and address calculations (OP) are processed in the E stage. (4) M stage (memory access stage) Operand memory accesses (OA1, OA2) are processed in the M stage. This stage is used only when the memory is accessed, and is divided into two sub-stages, M1 and M2. The RX CPU enables respective memory accesses for M1 and M2.  M1 stage (memory-access stage 1) Operand memory access (OA1) is processed. Store operation: The pipeline processing ends when a write request is received via the bus. Load operation: The operation proceeds to the M2 stage when a read request is received via the bus. If a request and load data are received at the same timing (no-wait memory access), the operation proceeds to the WB stage.  M2 stage (memory-access stage 2) Operand memory access (OA2) is processed. The CPU waits for the load data in the M2 stage. When the load data is received, the operation proceeds to the WB stage. (5) WB stage (write-back stage) The operation result and the data read from memory are written to the register (RW) in the WB stage. The data read from memory and the other type of data, such as the operation result, can be written to the register in the same clock cycles. R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 47 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group Figure 2.9 shows the pipeline configuration and its operation. 2. CPU One cycle M stage Pipeline stage IF stage D stage E stage M1 stage M2 stage WB stage BYP Execution processing IF DEC RF OP OA1 RW OA2 Figure 2.9 Pipeline Configuration and its Operation R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 48 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 2. CPU 2.8.2 Instructions and Pipeline Processing The operands in the table below indicate the following meaning. #IMM: Immediate Rs, Rs2, Rd, Rd2, Ri, Rb: General-purpose register, CR: Control register dsp: dsp5, dsp8, dsp16, dsp24 pcdsp: pcdsp3, pcdsp8, pcdsp16, pcdsp24 2.8.2.1 Instructions Converted into Single Micro-Operation and Pipeline Processing The table below lists the instructions that are converted into a single micro-operation. The number of cycles in the table indicates the number of cycles during no-wait memory access. Table 2.13 Instruction Instructions that are Converted into a Single Micro-Operation Mnemonic (indicates the common operation when the size is omitted)  {ABS, ADC, ADD, AND, CMP, MAX, MIN, MUL, NEG, NOP, NOT, OR, ROLC, RORC, ROTL, ROTR, SAT, SBB, SHAR, SHLL, SHLR, SUB, TST, XOR} “#IMM, Rd”/“Rd”/ “Rs, Rd”/“Rs, Rs2, Rd”  DIV “#IMM, Rd”/“Rs, Rd”  DIVU “#IMM, Rd”/“Rs, Rd”  {MOV, MOVU, REVL, REVW} “#IMM, Rd”/“Rs, Rd”  SCCnd “Rd”  {STNZ, STZ} “#IMM, Rd”  {MOV, MOVU} “[Rs], Rd”/“dsp[Rs], Rd”/“[Rs+], Rd”/ “[-Rs], Rd”/“Rs, [Ri, Rb]”  POP “Rd”  MOV “Rs, [Rd]”/“Rs, dsp[Rd]”/“Rs, [Rd+]”/“Rs, [-Rd]”/ “Rs, [Ri, Rb]”  PUSH “Rs”  PUSHC “CR”  {BCLR, BNOT, BSET, BTST} “#IMM, Rd”/“Rs, Rd”  BMCnd “#IMM, Rd”  BCnd “pcdsp”  {BRA, BSR} “pcdsp”/“Rs”  {JMP, JSR} “Rs”         Reference Figure Number of Cycles Arithmetic/logic instructions (register-register, immediate-register) Except EMUL, EMULU, RMPA, DIV, DIVU and SATR Arithmetic/logic instructions (division) Data transfer instructions (register-register, immediate-register) Transfer instructions (load operation) Figure 2.10 1 Figure 2.10 Figure 2.10 Figure 2.10 3 to 20*1 2 to 18*1 1 Figure 2.11 Throughput: 1 Latency: 2*2 1 Transfer instructions (store operation) Figure 2.12 Bit manipulation instructions (register) Branch instructions Figure 2.10 Figure 2.20 1 Branch taken: 3 Branch not taken: 1 1 System manipulation instructions CLRPSW, SETPSW “#IMM” MVTC “#IMM, CR”/“Rs, CR” MVFC “CR, Rd” MVTIPL“#IMM” {MACHI, MACLO, MULHI, MULLO} “Rs, Rs2” {MVFACHI, MVFACMI} “Rd” {MVTACHI, MVTACLO} “Rs” RACW“#IMM” — DSP instructions Figure 2.10 1 Note 1. The number of cycles for the dividing instruction varies according to the divisor and dividend. Note 2. For the number of cycles for throughput and latency, see section 2.8.3, Calculation of the Instruction Processing Time. R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 49 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 2. CPU Figure 2.10 to Figure 2.12 show the operation of instructions that are converted into a basic single micro-operation. 4 stages ADD R1, R2 IF D E WB Note: • Multi-cycle instructions (DIV, DIVU) are executed in multiple cycles in the E stage. DIV R3, R4 IF D E E WB Figure 2.10 Operation for Register-Register, Immediate-Register 5 stages MOV [R1], R2 IF D E M1 WB Note: • When the load operation is executed to the no-wait memory, the M1 stage is executed in one cycle. In other cases, the M stage (M1 or M2) is executed in multiple cycles. MOV [R1], R2 IF D E M1 M1 M2 WB Figure 2.11 Load Operation 4 stages MOV R2, [R1] IF D E M1 Note: • The M1 stage is executed until a write request is received during the store operation. (If the store operation is executed to the no-wait memory, the M1 stage is executed in one cycle.) IF D E M1 M1 M1 Figure 2.12 Store Operation R01DS0041EJ0050 Rev.0.50 Apr 15, 2011 Page 50 of 90 Under development Preliminary document Specifications in this document are tentative and subject to change. RX210 Group 2. CPU 2.8.2.2 Instructions Converted into Multiple Micro-Operations and Pipeline Processing The table below lists the instructions that are converted into multiple micro-operations. The number of cycles in the table indicates the number of cycles during no-wait memory access. Table 2.14 Instruction Instructions that are Converted into Multiple Micro-Operations (1 / 2) Mnemonic (indicates the common operation when the size is omitted)  {ADC, ADD, AND, CMP, MAX, MIN, MUL, OR, SBB, SUB, TST, XOR} “[Rs], Rd”/“dsp[Rs], Rd”  DIV “[Rs],Rd / dsp[Rs],Rd”  DIVU“[Rs],Rd / dsp[Rs],Rd”  {EMUL, EMULU} “#IMM, Rd”/“Rs, Rd” Reference Figure Number of Cycles Arithmetic/logic instructions (memory source operand) Arithmetic/logic instructions (division) Arithmetic/logic instructions (multiplier: 32 × 32  64 bits) (register-register, registerimmediate) Arithmetic/logic instructions (multiply-and-accumulate operation) Figure 2.13 — — Figure 2.15 3 5 to 22 4 to 20 2  RMPA.B — 6+7×floor(n/4)+4×(n%4) n: Number of processing bytes*1 6+5×floor(n/2)+4×(n%2) n: Number of processing words*1 6+4n n: Number of processing longwords*1 3  RMPA.W —  RMPA.L — Arithmetic/logic instructions (64bit signed saturation processing for the RMPA instruction) Data transfer instructions (memory-memory transfer) Bit manipulation instructions (memory source operand) Transfer instructions (load operation) Transfer instructions (save operation of multiple registers) Transfer instructions (restore operation of multiple registers)  SATR —  MOV “[Rs], [Rd]”/“dsp[Rs], [Rd]”/“[Rs], dsp[Rd]”/ “dsp[Rs], [Rd]”  PUSH “[Rs]”/“dsp[Rs]”  {BCLR, BNOT, BSET, BTST} “#IMM, [Rd]”/ “#IMM, dsp[Rd]”  BMCnd “#IMM, [Rd]”/“#IMM, dsp[Rd]”  POPC “CR”  PUSHM “Rs-Rs2”  POPM “Rs-Rs2” Figure 2.14 3 Figure 2.14 3 — — — Throughput: 3 Latency: 4*2 n n: Number of registers*3 Throughput: n Latency: n + 1 n: Number of registers*2,*4 2 2 5 5 Throughput: n