Datasheet
RX220 Group
Renesas MCUs
32-MHz 32-bit RX MCUs, 49 DMIPS, up to 256-KB flash memory,
12-bit A/D, ELC, MPC, IrDA, RTC, up to 7 comms channels;
incorporating functions for IEC60730 compliance
R01DS0130EJ0110
Rev.1.10
Dec 20, 2013
Features
■ 32-bit RX CPU core
Max. operating frequency: 32 MHz
Capable of 49 DMIPS in operation at 32 MHz
Accumulator handles 64-bit results (for a single
instruction) from 32- × 32-bit operations
Multiplication and division unit handles 32- × 32-bit
operations (multiplication instructions take one CPU
clock cycle)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions, ultra-compact code
On-chip debugging circuit
■ Low-power design and architecture
Operation from a single 1.62-V to 5.5-V supply
1.62-V operation available (at up to 8 MHz)
Three low-power modes
■ On-chip flash memory for code, no wait states
32-MHz operation, 31.25-ns read cycle
No wait states for reading at full CPU speed
Up to 256-Kbyte capacity
User code programmable via the SCI
Programmable at 1.62 V
For instructions and operands
■ On-chip data flash memory
8 Kbytes (Number of times of reprogramming: 100,000)
Erasing and programming impose no load on the CPU.
■ On-chip SRAM, no wait states
Up to 16-Kbyte size capacity
■ DMA
DMAC: Incorporates four channels
DTC: Four transfer modes
■ ELC
Module operation can be initiated by event signals
without going through interrupts.
Modules can operate while the CPU is sleeping.
■ Reset and supply management
Seven types of reset, including the power-on reset (POR)
Low voltage detection (LVD) with voltage settings
■ Clock functions
Frequency of external clock: Up to 20 MHz
Frequency of the oscillator for sub-clock generation:
32.768 kHz
On-chip low- and high-speed oscillators, dedicated onchip low-speed oscillator for the IWDT
Generation of a dedicated 32.768-kHz clock for the RTC
Clock frequency accuracy measurement circuit (CAC)
PLQP0100KB-A
PLQP0064KB-A
PLQP0048KB-A
PLQP0064GA-A
14 × 14 mm, 0.5-mm pitch
10 × 10 mm, 0.5-mm pitch
7 × 7 mm, 0.5-mm pitch
14 × 14 mm, 0.8-mm pitch
■ Independent watchdog timer
125-kHz on-chip oscillator produces a dedicated clock
signal to drive IWDT operation.
■ Useful functions for IEC60730 compliance
Self-diagnostic and disconnection-detection assistance
functions for the A/D converter, clock-frequency
accuracy-measurement circuit, independent watchdog
timer, functions to assist in RAM testing, etc.
■ Up to seven communications channels
SCI with many useful functions (up to five channels)
Asynchronous mode, clock synchronous mode, smart
card interface mode
IrDA Interface (one channel, in cooperation with the
SCI5)
I2C bus interface: Transfer at up to 400 kbps, capable of
SMBus operation (one channel)
RSPI (one channel)
■ Up to 14 extended-function timers
16-bit MTU: input capture, output capture,
complementary PWM output, phase counting mode
(six channels)
8-bit TMR (four channels)
16-bit compare-match timers (four channels)
■ 12-bit A/D converter
Capable of conversion within 1.56 μs
Self-diagnostic function and analog input disconnection
detection assistance function
■ Analog comparator
■ General I/O ports
5-V tolerant, open drain, input pull-up, switching of
driving ability
■ MPC
Multiple locations are selectable for I/O pins of
peripheral functions
■ Operating temp. range
40C to +85C
40C to +105C
■ Real-time clock
Adjustment functions (30 seconds, leap year, and error)
Year and month display or 32-bit second display (binary
counter) is selectable
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 1 of 105
RX220 Group
1. Overview
1.
Overview
1.1
Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different
packages.
Table 1.1 is for products with the greatest number of functions, so numbers of peripheral modules and channels will
differ in accord with the package. For details, see Table 1.2, Comparison of Functions for Different Packages.
Table 1.1
Outline of Specifications (1 / 3)
Classification
Module/Function
Description
CPU
CPU
Memory
Maximum operating frequency: 32 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per state (cycle of the system clock)
Address space: 4-Gbyte linear
Register
General purpose: Sixteen 32-bit registers
Control: Eight 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32 32 64 bits
On-chip divider: 32 / 32 32 bits
Barrel shifter: 32 bits
ROM
Capacity: 32 K/64 K/128 K/256 Kbytes
32 MHz, no-wait memory access
On-board programming: 3 types
RAM
Capacity: 4 K/8 K/16 Kbytes
32 MHz, no-wait memory access
E2 DataFlash
E2 DataFlash capacity: 8 Kbytes
MCU operating mode
Single-chip mode
Clock
Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator,
and IWDT-dedicated on-chip oscillator
Oscillation stop detection
Measuring circuit for accuracy of clock frequency (clock-accuracy check: CAC)
Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and flashIF clock
(FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 32 MHz (at max.)
Peripheral modules run in synchronization with the peripheral module clock (PCLK): 32 MHz (at
max.)
The flash peripheral circuit runs in synchronization with the flash peripheral clock (FCLK): 32 MHz (at
max.)
Clock generation circuit
Reset
RES# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and
software reset
Voltage detection
Voltage detection circuit
(LVDAa)
When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt
is generated.
Voltage detection circuit 0 is capable of selecting the detection voltage from 4 levels
Voltage detection circuit 1 is capable of selecting the detection voltage from 16 levels
Voltage detection circuit 2 is capable of selecting the detection voltage from 16 levels
Low power
consumption
Low power consumption
facilities
Module stop function
Three low power consumption modes
Sleep mode, all-module clock stop mode, and software standby mode
Function for lower
operating power
consumption
Four operating power control modes
Middle-speed operating mode 1A, middle-speed operating mode 1B, low-speed operating mode 1,
low-speed operating mode 2
Interrupt controller (ICUb)
Interrupt vectors: 106
External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)
Non-maskable interrupts: 5 (the NMI pin, oscillation stop detection interrupt, voltage monitoring 1
interrupt, voltage monitoring 2 interrupt, and IWDT interrupt)
16 levels specifiable for the order of priority
Interrupt
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 2 of 105
RX220 Group
Table 1.1
1. Overview
Outline of Specifications (2 / 3)
Classification
Module/Function
Description
DMA
DMA controller (DMACA)
4 channels
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software trigger, external interrupts, and interrupt requests from peripheral
functions
Data transfer controller
(DTCa)
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Interrupts
Chain transfer function
General I/O ports
100-pin/64-pin/48-pin
I/O pin: 84/48/34
Input: 1/1/1
Pull-up resistors: 84/48/34
Open-drain outputs: 35/26/20
5-V tolerance: 4/2/2
8-bit port switching function: Not supported/supported/supported
I/O ports
Event link controller (ELC)
Event signals of 46 types can be directly connected to the module
Operations of timer modules are selectable at event input
Capable of event link operation for port B
Multi-function pin controller (MPC)
Capable of selecting input/output function from multiple pins
Timers
Multi-function timer pulse
unit 2 (MTU2a)
(16 bits 6 channels) 1 unit
Time bases for the six 16-bit timer channels can be provided via up to 16 pulse-input/output lines and
three pulse-input lines
Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than
channel 5, for which only four signals are available.
Input capture function
21 output compare/input capture registers
Pulse output mode
Complementary PWM output mode
Reset synchronous PWM mode
Phase-counting mode
Generation of triggers for A/D converter conversion
Port output enable 2
(POE2a)
Controls the high-impedance state of the MTU’s waveform output pins
8-bit timer (TMR)
(8 bits 2 channels) 2 units
Select from among seven internal clock signals (PCLK/1, PCLK/2, PCLK/8, PCLK/32, PCLK/64,
PCLK/1024, PCLK/8192) and one external clock signal
Capable of output of pulse trains with desired duty cycles or of PWM signals
The 2 channels of each unit can be cascaded to create a 16-bit timer
Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12
Compare match timer
(CMT)
(16 bits 2 channels) 2 units
Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
Independent watchdog
timer (IWDTa)
14 bits 1 channel
Counter-input clock: IWDT-dedicated on-chip oscillator
Frequency divided by 1, 16, 32, 64, 128, or 256
Realtime clock (RTCc)
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Clock source: Sub-clock
Time count or 32-bit binary count in second units basis selectable
Time/calendar
Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
Page 3 of 105
RX220 Group
Table 1.1
1. Overview
Outline of Specifications (3 / 3)
Classification
Module/Function
Description
Communication
function
Serial communications
interfaces (SCIe, SCIf)
5 channels (channel 1, 5, 6, and 9: SCIe, channel 12: SCIf) (including one channel for IrDA)
Serial communications modes:
Asynchronous, clock synchronous, and smart-card interface
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Average transfer rate clock can be input from TMR timers (SCI5, SCI6, and SCI12)
Simple IIC
Simple SPI
Master/slave mode supported (SCIf only)
Start frame and information frame are included (SCIf only)
Detection of a start bit in asynchronous mode: Low level or falling edge is selectable (SCIe/SCIf)
IrDA interface (IRDA)
1 channel (SCI5 is used)
Supports encoding/decoding the waveforms conforming to the IrDA specification version 1.0
I2C bus interface (RIIC)
1 channel
Communications formats:
I2C bus format/SMBus format
Master/slave selectable
Supports the fast mode
Serial peripheral
interface (RSPI)
1 channel
Transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPCK
(RSPI clock) signals enables serial transfer through SPI operation (four lines) or clock-synchronous
operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Choice of LSB-first or MSB-first transfer
The number of bits in each transfer can be changed to any number of bits from 8 to 16, 20, 24, or 32
bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with each frame
having up to 32 bits)
Double buffers for both transmission and reception
12-bit A/D converter (S12ADb)
12 bits (16 channels 1 unit)
12-bit resolution
Minimum conversion time: 1.56 s per channel (in operation with ADCLK at 32 MHz)
Operating modes
Scan mode (single scan mode, continuous scan mode, and group scan mode)
Sample-and-hold function
Self-diagnosis for the A/D converter
Assistance in detecting disconnected analog inputs
Double-trigger mode (duplication of A/D conversion data)
A/D conversion start conditions
A software trigger, a trigger from a timer (MTU), an external trigger signal, or ELC
CRC calculator (CRC)
CRC code generation for any desired data in 8-bit units
Select any of three generating polynomials:
X8 + X2 + X + 1, X16 + X15 + X2 + 1, or X16 + X12 + X5 + 1
Generation of CRC codes for use with LSB-first or MSB-first communications is selectable.
Comparator A (CMPA)
2 channels
Comparison of reference voltage and analog input voltage
Data Operation Circuit (DOC)
Comparison, addition, and subtraction of 16-bit data
Power supply voltage/Operating frequency
VCC = 1.62 to 2.7 V: 8 MHz, VCC = 2.7 to 5.5 V: 32 MHz
Operating temperature
D version: 40 to +85°C, G version: 40 to +105°C*1
Package
100-pin LQFP (PLQP0100KB-A)
64-pin LQFP (PLQP0064KB-A)
64-pin LQFP (PLQP0064GA-A)
48-pin LQFP (PLQP0048KB-A)
Note 1. Please contact Renesas Electronics sales office for derating of operation under Ta = +85°C to +105°C. Derating is the
systematic reduction of load for the sake of improved reliability.
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 4 of 105
RX220 Group
Table 1.2
1. Overview
Comparison of Functions for Different Packages
RX220 Group
Module/Functions
Interrupt
External interrupts
DMA
DMA controller
100 Pins
64 Pins
NMI, IRQ0 to IRQ7
NMI, IRQ0 to IRQ2,
IRQ4 to IRQ7
Supported
Multi-function timer pulse unit 2
6 channels (MTU0 to MTU5)
Port output enable 2
POE0# to POE3#, POE8#
8-bit timer
2 channels × 2 units
Compare match timer
2 channels × 2 units
Realtime clock
Supported
Independent watchdog timer
Communication
function
Serial communications interface
(SCIe)
Not supported
Supported
4 channels
(SCI1, 5, 6, 9) (including one channel for IrDA)
Serial communications interface
(SCIf)
1 channel
Serial peripheral interface
1 channel
16 channels
(AN000 to AN015)
CRC calculator
12 channels
(AN000 to AN004,
AN006,
AN008 to AN013)
Supported
Comparator A
2 channels
Package
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
8 channels
(AN000, AN003, AN004,
AN006,
AN009 to AN012)
Supported
Event link controller
8-bit port switching function
3 channels
(SCI1, 5, 6)
(including one channel
for IrDA)
1 channel (SCI12)
I2C bus interface
12-bit A/D converter
NMI, IRQ0, IRQ1,
IRQ4 to IRQ7
4 channels (DMAC0 to DMAC3)
Data transfer controller
Timers
48 Pins
Not supported in
100-pin packages
Supported in 64-pin
packages
Switches PB6 to PC0
and PB7 to PC1
Supported in 48-pin
packages
Switches PB0 to PC0,
PB1 to PC1, PB3 to
PC2, and PB5 to PC3
100-pin LQFP
64-pin LQFP
48-pin LQFP
Page 5 of 105
RX220 Group
1.2
1. Overview
List of Products
Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part no., memory capacity, and package
type.
Table 1.3
List of Products
Group
Part No.
Package
RX220
R5F52206BDFP
PLQP0100KB-A
R5F52206BDFM
PLQP0064KB-A
R5F52206BDFK
PLQP0064GA-A
R5F52206BDFL
PLQP0048KB-A
R5F52205BDFP
PLQP0100KB-A
R5F52205BDFM
PLQP0064KB-A
R5F52205BDFK
PLQP0064GA-A
R5F52205BDFL
PLQP0048KB-A
R5F52203BDFP
PLQP0100KB-A
R5F52203BDFM
PLQP0064KB-A
R5F52203BDFK
PLQP0064GA-A
R5F52203BDFL
PLQP0048KB-A
R5F52201BDFM
PLQP0064KB-A
R5F52201BDFK
PLQP0064GA-A
R5F52201BDFL
PLQP0048KB-A
R5F52206BGFP
PLQP0100KB-A
R5F52206BGFM
PLQP0064KB-A
R5F52206BGFK
PLQP0064GA-A
R5F52206BGFL
PLQP0048KB-A
R5F52205BGFP
PLQP0100KB-A
R5F52205BGFM
PLQP0064KB-A
R5F52205BGFK
PLQP0064GA-A
R5F52205BGFL
PLQP0048KB-A
R5F52203BGFP
PLQP0100KB-A
R5F52203BGFM
PLQP0064KB-A
R5F52203BGFK
PLQP0064GA-A
R5F52203BGFL
PLQP0048KB-A
R5F52201BGFM
PLQP0064KB-A
R5F52201BGFK
PLQP0064GA-A
R5F52201BGFL
PLQP0048KB-A
ROM
Capacity
RAM
Capacity
256 Kbytes
16 Kbytes
Operating
Frequency (Max.)
Operating
temperature
32 MHz
40 to +85°C
32 MHz
40 to +105°C
128 Kbytes
8 Kbytes
64 Kbytes
32 Kbytes
4Kbytes
256 Kbytes
16 Kbytes
128 Kbytes
8 Kbytes
64 Kbytes
32 Kbytes
4Kbytes
Note: • Please contact Renesas Electronics sales office for derating of operation under Ta = +85°C to +105°C. Derating is the
systematic reduction of load for the sake of improved reliability.
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 6 of 105
RX220 Group
R
5
1. Overview
F
5
2 2
0
6
B
D
F
P
Package type, number of pins, and pin pitch
FP: LQFP/100/0.50
FM: LQFP/64/0.50
FK: LQFP/64/0.80
FL: LQFP/48/0.50
D: Operating temperature (–40 to +85°C)
G: Operating temperature (–40 to +105°C)
ROM, RAM, and E2 DataFlash capacity
6: 256 Kbytes/16 Kbytes/8 Kbytes
5: 128 Kbytes/8 Kbytes/8 Kbytes
3: 64 Kbytes/8 Kbytes/8 Kbytes
1: 32 Kbytes/4 Kbytes/8 Kbytes
Group name
20: RX220 Group
Series name
RX200 Series
Type of memory
F: Flash memory version
Renesas MCU
Renesas semiconductor product
Figure 1.1
How to Read the Product Part No., Memory Capacity, and Package Type
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 7 of 105
RX220 Group
1.3
1. Overview
Block Diagram
Figure 1.2 shows a block diagram.
E2 DataFlash
IWDTa
ELC
CRC
SCIe × 4 channels
(including one channel for IrDA)
SCIf × 1 channel
RSPI × 1 channel
Internal peripheral buses 1 to 6
RIIC × 1 channel
MTU2a × 6 channels
POE2a
Port 0
TMR × 2 channels (unit 0)
TMR × 2 channels (unit 1)
CMT × 2 channels (unit 0)
Internal main bus 2
RAM
Operand bus
Instruction bus
DTCa
Port 2
CMT × 2 channels (unit 1)
Port 3
RTCc
Port 4
12-bit A/D converter × 16 channels
Port 5
DOC
Port A
Comparator A × 2 channels
Port B
CAC
Port C
ICUb
ROM
Port 1
DMACA × 4
channels
Port D
Clock
generation
circuit
ICUb:
DTCa:
DMACA:
BSC:
IWDTa:
ELC:
CRC:
SCIe, SCIf:
IrDA:
Figure 1.2
Internal main bus 1
RX CPU
Interrupt controller
Data transfer controller
DMA controller
Bus controller
Independent watchdog timer
Event link controller
CRC (cyclic redundancy check) calculator
Serial communications interface
Infrared Data Association
Port E
Port H
Port J
BSC
RSPI: Serial peripheral interface
RIIC: I2C bus interface
MTU2a: Multi-function timer pulse unit 2
POE2a: Port output enable 2
TMR: 8-bit timer
CMT: Compare match timer
RTCc: Realtime clock
DOC: Data operation circuit
CAC: Clock-frequency accuracy measuring circuit
Block Diagram
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 8 of 105
RX220 Group
1.4
1. Overview
Pin Functions
Table 1.4 lists the pin functions.
Table 1.4
Pin Functions (1 / 3)
Classifications
Pin Name
I/O
Description
Power supply
VCC
Input
Power supply pin. Connect it to the system power supply.
VCL
—
Connect this pin to the VSS pin via the 0.1 μF smoothing capacitor
used to stabilize the internal power supply. Place the capacitor close
to the pin.
VSS
Input
Ground pin. Connect it to the system power supply (0 V).
XTAL
Output
EXTAL
Input
Pins for connecting a crystal resonator. An external clock signal can
be input through the EXTAL pin.
XCIN
Input
Clock
Input/output pins for the sub-clock generation circuit. Connect a
crystal resonator between XCIN and XCOUT.
XCOUT
Output
Operating mode
control
MD
Input
Pin for setting the operating mode. The signal levels on this pin
must not be changed during operation.
System control
RES#
Input
Reset signal input pin. This LSI enters the reset state when this
signal goes low.
CAC
CACREF
Input
Input pin for the measuring circuit for clock frequency precision.
On-chip emulator
FINED
I/O
FINE interface pin.
Interrupt
NMI
Input
Non-maskable interrupt request pin.
IRQ0 to IRQ7
Input
Interrupt request pins.
Multi-function timer
pulse unit
MTIOC0A, MTIOC0B
MTIOC0C, MTIOC0D
I/O
The TGRA0 to TGRD0 input capture input/output compare output/
PWM output pins.
MTIOC1A, MTIOC1B
I/O
The TGRA1 and TGRB1 input capture input/output compare output/
PWM output pins.
MTIOC2A, MTIOC2B
I/O
The TGRA2 and TGRB2 input capture input/output compare output/
PWM output pins.
MTIOC3A, MTIOC3B
MTIOC3C, MTIOC3D
I/O
The TGRA3 to TGRD3 input capture input/output compare output/
PWM output pins.
MTIOC4A, MTIOC4B
MTIOC4C, MTIOC4D
I/O
The TGRA4 to TGRD4 input capture input/output compare output/
PWM output pins.
MTIC5U, MTIC5V, MTIC5W
Input
The TGRU5, TGRV5, and TGRW5 input capture input/external
pulse input pins.
MTCLKA, MTCLKB,
MTCLKC, MTCLKD
Input
Input pins for external clock.
POE0# to POE3#, POE8#
Input
Input pins for request signals to place the MTU pins in the high
impedance state.
Port output enable
8-bit timer
Realtime clock
TMO0 to TMO3
Output
Compare match output pins.
TMCI0 to TMCI3
Input
Input pins for external clocks to be input to the counter.
TMRI0 to TMRI3
Input
Input pins for the counter reset.
RTCOUT
Output
Output pin for 1-Hz clock.
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 9 of 105
RX220 Group
Table 1.4
1. Overview
Pin Functions (2 / 3)
Classifications
Pin Name
I/O
Description
Serial
communications
interface (SCIe)
Asynchronous mode/clock synchronous mode
SCK1, SCK5, SCK6, SCK9
I/O
Input/output pins for clock
RXD1, RXD5, RXD6, RXD9
Input
Input pins for received data
TXD1, TXD5, TXD6, TXD9
Output
Output pins for transmitted data
CTS1#, CTS5#, CTS6#,
CTS9#
Input
Input pins for controlling the start of transmission and reception
RTS1#, RTS5#, RTS6#,
RTS9#
Output
Output pins for controlling the start of transmission and reception
SSCL1, SSCL5, SSCL6,
SSCL9
I/O
Input/output pins for the I2C clock
SSDA1, SSDA5, SSDA6,
SSDA9
I/O
Input/output pins for the I2C data
SCK1, SCK5, SCK6, SCK9
I/O
Input/output pins for the clock
SMISO1, SMISO5, SMISO6,
SMISO9
I/O
Input/output pins for slave transmission of data
SMOSI1, SMOSI5, SMOSI6,
SMOSI9
I/O
Input/output pins for master transmission of data
SS1#, SS5#, SS6#, SS9#
Input
Chip-select input pins
IRTXD5
Output
Data output pin in the IrDA format
IRRXD5
Input
Data input pin in the IrDA format
Simple I2C mode
Simple SPI mode
IrDA Interface
Serial
communications
interface (SCIf)
Asynchronous mode/clock synchronous mode
SCK12
I/O
Input/output pin for the clock
RXD12
Input
Input pin for received data
TXD12
Output
Output pin for transmitted data
CTS12#
Input
Input pin for controlling the start of transmission and reception
RTS12#
Output
Output pin for controlling the start of transmission and reception
SSCL12
I/O
Input/output pin for the I2C clock
SSDA12
I/O
Input/output pin for the I2C data
Simple I2C mode
Simple SPI mode
SCK12
I/O
Input/output pin for the clock
SMISO12
I/O
Input/output pin for slave transmit data
SMOSI12
I/O
Input/output pin for master transmit data
SS12#
Input
Chip-select input pin
RXDX12
Input
Input pin for data reception by SCIf
TXDX12
Output
Output pin for data transmission by SCIf
SIOX12
I/O
Input/output pin for data reception or transmission by SCIf
SCL
I/O
Input/output pin for I2C bus interface clocks. Bus can be directly
driven by the N-channel open-drain output.
SDA
I/O
Input/output pin for I2C bus interface data. Bus can be directly
driven by the N-channel open-drain output.
Extended serial mode
I2C
bus interface
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Dec 20, 2013
Page 10 of 105
RX220 Group
Table 1.4
1. Overview
Pin Functions (3 / 3)
Classifications
Pin Name
I/O
Description
Serial peripheral
interface
RSPCKA
I/O
Clock input/output pin for the RSPI.
MOSIA
I/O
Input or output data output from the master for the RSPI.
MISOA
I/O
Input or output data output from the slave for the RSPI.
SSLA0
I/O
Input/output pin to select the slave for the RSPI.
SSLA1 to SSLA3
Output
Output pins to select the slave for the RSPI.
AN000 to AN015
Input
Input pin for the analog signals to be processed by the A/D
converter.
ADTRG0#
Input
Input pin for the external trigger signals that start the A/D
conversion.
12-bit A/D converter
Comparator A
Analog power
supply
I/O ports
CMPA1
Input
Input analog pin for the comparator A1.
CMPA2
Input
Input analog pin for the comparator A2.
CVREFA
Input
Input pin for the comparator reference voltage.
AVCC0
Input
Analog voltage supply pin for the 12-bit A/D converter. Connect this
pin to VCC if the 12-bit A/D converter is not to be used.
AVSS0
Input
Analog ground pin for the 12-bit A/D converter. Connect this pin to
VSS if the 12-bit A/D converter is not to be used.
VREFH0
Input
Analog reference voltage supply pin for the 12-bit A/D converter.
Connect this pin to VCC if the 12-bit A/D converter is not to be used.
VREFL0
Input
Analog reference ground pin for the 12-bit A/D converter. Connect
this pin to VSS if the 12-bit A/D converter is not to be used.
P03, P05, P07
I/O
3-bit input/output pins.
P12 to P17
I/O
6-bit input/output pins.
P20 to P27
I/O
8-bit input/output pins.
P30 to P37
I/O
8-bit input/output pins. (P35 input pin)
P40 to P47
I/O
8-bit input/output pins.
P50 to P55
I/O
6-bit input/output pins.
PA0 to PA7
I/O
8-bit input/output pins.
PB0 to PB7
I/O
8-bit input/output pins.
PC0 to PC7
I/O
8-bit input/output pins.
PD0 to PD7
I/O
8-bit input/output pins.
PE0 to PE7
I/O
8-bit input/output pins.
PH0 to PH3
I/O
4-bit input/output pins.
PJ1, PJ3
I/O
2-bit input/output pins.
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 11 of 105
RX220 Group
1.5
1. Overview
Pin Assignments
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
76
50
77
49
78
48
79
47
80
46
81
45
82
44
83
43
84
42
RX220 Group
PLQP0100KB-A
(100-pin LQFP)
(Top view)
85
86
87
88
89
90
91
41
40
39
38
37
36
35
25
24
23
22
21
20
19
18
17
16
15
14
13
12
PC2
PC3
PC4
PC5
PC6
PC7
P50
P51
P52
P53
P54
P55
PH0
PH1
PH2
PH3
P12
P13
P14
P15
P16
P17
P20
P21
P22
NC
P03
NC
PJ3
VCL
PJ1
MD
XCIN
XCOUT
RES#
P37/XTAL
VSS
P36/EXTAL
VCC
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
P23
11
26
10
27
100
9
28
99
8
29
98
7
30
97
6
31
96
5
32
95
4
33
94
3
34
93
2
92
1
PE2
PE1
PE0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
P47
P46
P45
P44
P43
P42
P41
VREFL0
P40
VREFH0
AVCC0
P07
AVSS0
P05
74
75
PE3
PE4
PE5
PE6
PE7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
VSS
PB0
VCC
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
Figure 1.3 to Figure 1.5 show the pin assignments. Table 1.5 to Table 1.7 show the lists of pins and pin functions.
Note: • This figure indicates the power supply pins and I/O port pins. For the pin configuration, see the
table “List of Pins and Pin Functions (100-Pin LQFP)”.
Figure 1.3
Pin Assignments of the 100-Pin LQFP
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 12 of 105
VSS
PB0
VCC
PB1
PB3
PB5
PB6/PC0
PB7/PC1
39
38
37
36
35
34
33
PA3
40
PA1
43
PA4
PA0
44
PA6
PE5
45
41
PE4
46
42
PE3
47
1. Overview
48
RX220 Group
PE2
49
32
PC2
PE1
50
31
PC3
PE0
51
30
PC4
NC
52
29
PC5
P46
53
28
PC6
NC
54
27
PC7
P44
55
26
P54
P43
56
25
P55
P42
57
24
PH0
P41
58
23
PH1
VREFL0
59
22
PH2
P40
60
21
PH3
VREFH0
61
20
P14
AVCC0
62
19
P15
P05
63
18
P16
AVSS0
64
17
P17
16
P26
15
P27
14
P30
13
P31
12
P32
11
P35
9
10
VCC
P36/EXTAL
8
VSS
7
P37/XTAL
6
RES#
5
XCOUT
4
XCIN
3
2
MD
1
P03
VCL
RX220 Group
PLQP0064KB-A
PLQP0064GA-A
(64-pin LQFP)
(Top view)
Note: • This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see the table “List of Pins and Pin Functions (64-Pin LQFP)”.
PE3
PE4
PA1
PA3
PA4
PA6
VSS
PB0/PC0
VCC
PB1/PC1
PB3/PC2
PB5/PC3
36
35
34
33
32
31
30
29
28
27
26
25
Pin Assignments of the 64-Pin LQFP
PE2
37
24
PC4
PE1
38
23
PC5
NC
39
22
PC6
P46
40
21
PC7
NC
41
20
PH0
P42
42
19
PH1
P41
43
18
PH2
VREFL0
44
17
PH3
P40
45
16
P14
VREFH0
46
15
P15
AVCC0
47
14
P16
AVSS0
48
13
P17
1
2
3
4
5
6
7
8
9
10
11
12
MD
RES#
P37/XTAL
VSS
P36/EXTAL
VCC
P35
P31
P30
P27
P26
RX220 Group
PLQP0048KB-A
(48-pin LQFP)
(Top view)
VCL
Figure 1.4
Note: • This figure indicates the power supply pins and I/O port pins. For the pin
configuration, see the table “List of Pins and Pin Functions (48-Pin LQFP)”.
Figure 1.5
Pin Assignments of the 48-Pin LQFP
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 13 of 105
RX220 Group
Table 1.5
1. Overview
List of Pins and Pin Functions (100-Pin LQFP) (1 / 3)
Pin
No.
Power Supply, Clock,
System Control
1
NC (Non-Connection)
2
3
Communications
(SCIe, SCIf, RSPI, RIIC)
PJ3
MTIOC3C
CTS6#/RTS6#/SS6#
PJ1
MTIOC3A
Others
P03
NC (Non-Connection)
4
5
Timers (MTU, TMR, POE)
I/O Port
VCL
6
7
MD
8
XCIN
9
XCOUT
10
RES#
11
XTAL
12
VSS
13
EXTAL
14
VCC
FINED
P37
P36
15
P35
16
P34
MTIOC0A/TMCI3/POE2#
SCK6
NMI
IRQ4
17
P33
MTIOC0D/TMRI3/POE3#
RXD6/SMISO6/SSCL6
IRQ3
18
P32
MTIOC0C/TMO3
TXD6/SMOSI6/SSDA6
IRQ2/RTCOUT
19
P31
MTIOC4D/TMCI2
CTS1#/RTS1#/SS1#
IRQ1
IRQ0
20
P30
MTIOC4B/TMRI3/POE8#
RXD1/SMISO1/SSCL1
21
P27
MTIOC2B/TMCI3
SCK1
22
P26
MTIOC2A/TMO1
TXD1/SMOSI1/SSDA1
23
P25
MTIOC4C/MTCLKB
24
P24
MTIOC4A/MTCLKA/TMRI1
MTIOC3D/MTCLKD
25
P23
26
P22
MTIOC3B/MTCLKC/TMO0
27
P21
MTIOC1B/TMCI0
ADTRG0#
28
P20
MTIOC1A/TMRI0
29
P17
MTIOC3A/MTIOC3B/TMO1/
POE8#
SCK1/MISOA/SDA
IRQ7
30
P16
MTIOC3C/MTIOC3D/TMO2
TXD1/SMOSI1/SSDA1/MOSIA/
SCL
IRQ6/RTCOUT/ADTRG0#
31
P15
MTIOC0B/MTCLKB/TMCI2
RXD1/SMISO1/SSCL1
IRQ5
32
P14
MTIOC3A/MTCLKA/TMRI2
CTS1#/RTS1#/SS1#
IRQ4
33
P13
MTIOC0B/TMO3
SDA
IRQ3
34
P12
TMCI1
SCL
IRQ2
35
PH3
TMCI0
36
PH2
TMRI0
IRQ1
37
PH1
TMO0
IRQ0
38
PH0
39
P55
MTIOC4D/TMO3
CACREF
40
P54
MTIOC4B/TMCI1
41
P53
42
P52
43
P51
44
P50
45
PC7
MTIOC3A/TMO2/MTCLKB
MISOA
46
PC6
MTIOC3C/MTCLKA/TMCI2
MOSIA
47
PC5
MTIOC3B/MTCLKD/TMRI2
RSPCKA
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
CACREF
Page 14 of 105
RX220 Group
Table 1.5
Pin
No.
1. Overview
List of Pins and Pin Functions (100-Pin LQFP) (2 / 3)
Power Supply, Clock,
System Control
Communications
(SCIe, SCIf, RSPI, RIIC)
I/O Port
Timers (MTU, TMR, POE)
48
PC4
MTIOC3D/MTCLKC/TMCI1/
POE0#
SCK5/SSLA0
49
PC3
MTIOC4D
TXD5/SMOSI5/SSDA5/IRTXD5
50
PC2
MTIOC4B
RXD5/SMISO5/SSCL5/IRRXD5/
SSLA3
51
PC1
MTIOC3A
SCK5/SSLA2
52
PC0
MTIOC3C
CTS5#/RTS5#/SS5#/SSLA1
53
PB7
MTIOC3B
TXD9/SMOSI9/SSDA9
54
PB6
MTIOC3D
RXD9/SMISO9/SSCL9
55
PB5
MTIOC2A/MTIOC1B/TMRI1/
POE1#
SCK9
56
PB4
57
PB3
CTS9#/RTS9#/SS9#
MTIOC0A/MTIOC4A/TMO0/
POE3#
SCK6
58
PB2
59
PB1
MTIOC0C/MTIOC4C/TMCI0
TXD6/SMOSI6/SSDA6
PB0
MTIC5W
RXD6/SMISO6/SSCL6/RSPCKA
60
CTS6#/RTS6#/SS6#
IRQ4
VCC
61
62
Others
VSS
63
PA7
64
PA6
MISOA
MTIC5V/MTCLKB/TMCI3/
POE2#
CTS5#/RTS5#/SS5#/MOSIA
65
PA5
66
PA4
MTIC5U/MTCLKA/TMRI0
RSPCKA
TXD5/SMOSI5/SSDA5/IRTXD5/
SSLA0
IRQ5
67
PA3
MTIOC0D/MTCLKD
RXD5/SMISO5/SSCL5/IRRXD5
IRQ6
68
PA2
69
PA1
MTIOC0B/MTCLKC
SCK5/SSLA2
70
PA0
MTIOC4A
SSLA1
71
PE7
RXD5/SMISO5/SSCL5/SSLA3/
IRRXD5
CVREFA
CACREF
IRQ7/AN015
72
PE6
73
PE5
MTIOC4C/MTIOC2B
IRQ6/AN014
IRQ5/AN013
74
PE4
MTIOC4D/MTIOC1A
AN012/CMPA2
75
PE3
MTIOC4B/POE8#
CTS12#/RTS12#/SS12#
AN011/CMPA1
76
PE2
MTIOC4A
RXD12/RXDX12/SMISO12/
SSCL12
IRQ7/AN010
77
PE1
MTIOC4C
TXD12/TXDX12/SIOX12/
SMOSI12/SSDA12
AN009
78
PE0
79
PD7
MTIC5U/POE0#
SCK12
IRQ7
AN008
80
PD6
MTIC5V/POE1#
IRQ6
81
PD5
MTIC5W/POE2#
IRQ5
82
PD4
POE3#
IRQ4
83
PD3
POE8#
IRQ3
84
PD2
MTIOC4D
IRQ2
85
PD1
MTIOC4B
86
PD0
IRQ0
AN007
IRQ1
87
P47
88
P46
AN006
89
P45
AN005
90
P44
AN004
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 15 of 105
RX220 Group
Table 1.5
Pin
No.
1. Overview
List of Pins and Pin Functions (100-Pin LQFP) (3 / 3)
Power Supply, Clock,
System Control
I/O Port
Timers (MTU, TMR, POE)
Communications
(SCIe, SCIf, RSPI, RIIC)
Others
91
P43
AN003
92
P42
AN002
P41
AN001
P40
AN000
P07
ADTRG0#
93
94
VREFL0
95
96
VREFH0
97
AVCC0
98
99
100
AVSS0
P05
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 16 of 105
RX220 Group
Table 1.6
Pin
No.
1. Overview
List of Pins and Pin Functions (64-Pin LQFP) (1 / 2)
Power Supply, Clock,
System Control
1
I/O Port
Timers (MTU, TMR, POE)
Communication
(SCIe, SCIf, RSPI, RIIC)
Others
P03
2
VCL
3
MD
4
XCIN
5
XCOUT
6
RES#
7
XTAL
8
VSS
9
EXTAL
10
VCC
FINED
P37
P36
11
P35
12
P32
MTIOC0C/TMO3
TXD6/SMOSI6/SSDA6
NMI
IRQ2/RTCOUT
13
P31
MTIOC4D/TMCI2
CTS1#/RTS1#/SS1#
IRQ1
14
P30
MTIOC4B/TMRI3/POE8#
RXD1/SMISO1/SSCL1
IRQ0
15
P27
MTIOC2B/TMCI3
SCK1
16
P26
MTIOC2A/TMO1
TXD1/SMOSI1/SSDA1
17
P17
MTIOC3A/MTIOC3B/TMO1/
POE8#
SCK1/MISOA/SDA
IRQ7
18
P16
MTIOC3C/MTIOC3D/TMO2
TXD1/SMOSI1/SSDA1/MOSIA/
SCL
IRQ6/RTCOUT/ADTRG0#
19
P15
MTIOC0B/MTCLKB/TMCI2
RXD1/SMISO1/SSCL1
IRQ5
20
P14
MTIOC3A/MTCLKA/TMRI2
CTS1#/RTS1#/SS1#
IRQ4
21
PH3
TMCI0
22
PH2
TMRI0
IRQ1
23
PH1
TMO0
IRQ0
24
PH0
25
P55
26
P54
MTIOC4B/TMCI1
27
PC7
MTIOC3A/TMO2/MTCLKB
MISOA
28
PC6
MTIOC3C/MTCLKA/TMCI2
MOSIA
29
PC5
MTIOC3B/MTCLKD/TMRI2
RSPCKA
30
PC4
MTIOC3D/MTCLKC/TMCI1/
POE0#
SCK5/SSLA0
31
PC3
MTIOC4D
TXD5/SMOSI5/SSDA5/IRTXD5
32
PC2
MTIOC4B
RXD5/SMISO5/SSCL5/IRRXD5/
SSLA3
CACREF
MTIOC4D/TMO3
CACREF
33
PB7/PC1
MTIOC3B
TXD9/SMOSI9/SSDA9
34
PB6/PC0
MTIOC3D
RXD9/SMISO9/SSCL9
35
PB5
MTIOC2A/MTIOC1B/TMRI1/
POE1#
SCK9
36
PB3
MTIOC0A/MTIOC4A/TMO0/
POE3#
SCK6
37
PB1
MTIOC0C/MTIOC4C/TMCI0
TXD6/SMOSI6/SSDA6
PB0
MTIC5W
RXD6/SMISO6/SSCL6/RSPCKA
41
PA6
MTIC5V/MTCLKB/TMCI3/
POE2#
CTS5#/RTS5#/SS5#/MOSIA
42
PA4
MTIC5U/MTCLKA/TMRI0
TXD5/SMOSI5/SSDA5/IRTXD5/
SSLA0
IRQ5
43
PA3
MTIOC0D/MTCLKD
RXD5/SMISO5/SSCL5/IRRXD5
IRQ6
38
VCC
39
40
IRQ4
VSS
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 17 of 105
RX220 Group
Table 1.6
Pin
No.
1. Overview
List of Pins and Pin Functions (64-Pin LQFP) (2 / 2)
Power Supply, Clock,
System Control
I/O Port
Timers (MTU, TMR, POE)
Communication
(SCIe, SCIf, RSPI, RIIC)
Others
44
PA1
MTIOC0B/MTCLKC
SCK5/SSLA2
CVREFA
45
PA0
MTIOC4A
SSLA1
CACREF
46
PE5
MTIOC4C/MTIOC2B
IRQ5/AN013
47
PE4
MTIOC4D/MTIOC1A
AN012/CMPA2
48
PE3
MTIOC4B/POE8#
CTS12#/RTS12#/SS12#
AN011/CMPA1
49
PE2
MTIOC4A
RXD12/RXDX12/SMISO12/
SSCL12
IRQ7/AN010
50
PE1
MTIOC4C
TXD12/TXDX12/SIOX12/
SMOSI12/SSDA12
AN009
SCK12
AN008
51
52
PE0
NC (Non-Connection)
53
54
P46
AN006
P44
AN004
NC (Non-Connection)
55
56
P43
AN003
57
P42
AN002
P41
AN001
P40
AN000
58
59
VREFL0
60
61
VREFH0
62
AVCC0
63
64
P05
AVSS0
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 18 of 105
RX220 Group
Table 1.7
1. Overview
List of Pins and Pin Functions (48-Pin LQFP) (1 / 2)
Pin No.
Power Supply, Clock,
System Control
1
VCL
2
MD
3
RES#
4
XTAL
5
VSS
6
EXTAL
7
VCC
I/O Port
Timers (MTU, TMR, POE)
Communication
(SCIe, SCIf, RSPI, RIIC)
Others
FINED
P37
P36
8
P35
9
P31
MTIOC4D/TMCI2
CTS1#/RTS1#/SS1#
NMI
IRQ1
10
P30
MTIOC4B/TMRI3/POE8#
RXD1/SMISO1/SSCL1
IRQ0
11
P27
MTIOC2B/TMCI3
SCK1
12
P26
MTIOC2A/TMO1
TXD1/SMOSI1/SSDA1
13
P17
MTIOC3A/MTIOC3B/TMO1/
POE8#
SCK1/MISOA/SDA
IRQ7
14
P16
MTIOC3C/MTIOC3D/TMO2
TXD1/SMOSI1/SSDA1/MOSIA/
SCL
IRQ6/ADTRG0#
15
P15
MTIOC0B/MTCLKB/TMCI2
RXD1/SMISO1/SSCL1
IRQ5
16
P14
MTIOC3A/MTCLKA/TMRI2
CTS1#/RTS1#/SS1#
IRQ4
17
PH3
TMCI0
18
PH2
TMRI0
IRQ1
19
PH1
TMO0
IRQ0
20
PH0
21
PC7
MTIOC3A/TMO2/MTCLKB
MISOA
22
PC6
MTIOC3C/MTCLKA/TMCI2
MOSIA
CACREF
CACREF
23
PC5
MTIOC3B/MTCLKD/TMRI2
RSPCKA
24
PC4
MTIOC3D/MTCLKC/TMCI1/
POE0#
SCK5/SSLA0
25
PB5/PC3
MTIOC2A/MTIOC1B/TMRI1/
POE1#
26
PB3/PC2
MTIOC0A/MTIOC4A/TMO0/
POE3#
SCK6
27
PB1/PC1
MTIOC0C/MTIOC4C/TMCI0
TXD6/SMOSI6/SSDA6
PB0/PC0
MTIC5W
RXD6/SMISO6/SSCL6/RSPCKA
31
PA6
MTIC5V/MTCLKB/TMCI3/
POE2#
CTS5#/RTS5#/SS5#/MOSIA
32
PA4
MTIC5U/MTCLKA/TMRI0
TXD5/SMOSI5/SSDA5/IRTXD5/
SSLA0
IRQ5
28
VCC
29
30
IRQ4
VSS
33
PA3
MTIOC0D/MTCLKD
RXD5/SMISO5/SSCL5/IRRXD5
IRQ6
34
PA1
MTIOC0B/MTCLKC
SCK5/SSLA2
CVREFA
35
PE4
MTIOC4D/MTIOC1A
36
PE3
MTIOC4B/POE8#
CTS12#/RTS12#
AN011/CMPA1
37
PE2
MTIOC4A
RXD12/RXDX12/SSCL12
IRQ7/AN010
38
PE1
MTIOC4C
TXD12/TXDX12/SIOX12/
SSDA12
AN009
39
AN012/CMPA2
NC (Non-Connection)
40
P46
AN006
42
P42
AN002
43
P41
AN001
41
NC (Non-Connection)
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 19 of 105
RX220 Group
Table 1.7
1. Overview
List of Pins and Pin Functions (48-Pin LQFP) (2 / 2)
Pin No.
Power Supply, Clock,
System Control
44
VREFL0
45
I/O Port
P40
46
VREFH0
47
AVCC0
48
AVSS0
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Timers (MTU, TMR, POE)
Communication
(SCIe, SCIf, RSPI, RIIC)
Others
AN000
Page 20 of 105
RX220 Group
2.
2. CPU
CPU
Figure 2.1 shows the register set of the CPU.
General-purpose register
b31
b0
R0 (SP) *1
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
Control register
b31
b0
ISP
(Interrupt stack pointer)
USP
(User stack pointer)
INTB
(Interrupt table register)
PC
(Program counter)
PSW
(Processor status word)
BPC
(Backup PC)
BPSW
(Backup PSW)
FINTV
(Fast interrupt vector register)
DSP instruction register
b63
b0
ACC (Accumulator)
Note 1. The stack pointer (SP) can be the interrupt stack pointer (ISP) or user stack pointer (USP), according to
the value of the U bit in the PSW register.
Figure 2.1
Register Set of the CPU
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RX220 Group
2.1
2. CPU
General-Purpose Registers (R0 to R15)
This CPU has sixteen general-purpose registers (R0 to R15). R1 to R15 can be used as data registers or address registers.
R0, a general-purpose register, also functions as the stack pointer (SP). The stack pointer is switched to operate as the
interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the stack pointer select bit (U) in the processor
status word (PSW).
2.2
(1)
Control Registers
Interrupt Stack Pointer (ISP)/User Stack Pointer (USP)
The stack pointer (SP) can be either of two types, the interrupt stack pointer (ISP) or the user stack pointer (USP).
Whether the stack pointer operates as the ISP or USP depends on the value of the stack pointer select bit (U) in the
processor status word (PSW).
Set the ISP or USP to a multiple of four, as this reduces the numbers of cycles required to execute interrupt sequences
and instructions entailing stack manipulation.
(2)
Interrupt Table Register (INTB)
The interrupt table register (INTB) specifies the address where the relocatable vector table starts.
(3)
Program Counter (PC)
The program counter (PC) indicates the address of the instruction being executed.
(4)
Processor Status Word (PSW)
The processor status word (PSW) indicates the results of instruction execution or the state of the CPU.
(5)
Backup PC (BPC)
The backup PC (BPC) is provided to speed up response to interrupts.
After a fast interrupt has been generated, the contents of the program counter (PC) are saved in the BPC register.
(6)
Backup PSW (BPSW)
The backup PSW (BPSW) is provided to speed up response to interrupts.
After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in the BPSW. The
allocation of bits in the BPSW corresponds to that in the PSW.
(7)
Fast Interrupt Vector Register (FINTV)
The fast interrupt vector register (FINTV) is provided to speed up response to interrupts.
The FINTV register specifies a branch destination address when a fast interrupt has been generated.
2.3
(1)
Register Associated with DSP Instructions
Accumulator (ACC)
The accumulator (ACC) is a 64-bit register used for DSP instructions. The accumulator is also used for the multiply and
multiply-and-accumulate instructions; EMUL, EMULU, MUL, and RMPA, in which case the prior value in the
accumulator is modified by execution of the instruction.
Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The MVTACHI and MVTACLO
instructions write data to the higher-order 32 bits (bits 63 to 32) and the lower-order 32 bits (bits 31 to 0), respectively.
Use the MVFACHI and MVFACMI instructions for reading data from the accumulator. The MVFACHI and MVFACMI
instructions read data from the higher-order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively.
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RX220 Group
3.
Address Space
3.1
Address Space
3. Address Space
This LSI has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is,
linear access to an address space of up to 4 Gbytes is possible, and this contains both program and data areas.
Figure 3.1 shows the memory map.
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RX220 Group
3. Address Space
Single-chip mode*1
0000 0000h
RAM*2
0000 4000h
Reserved area*3
0008 0000h
Peripheral I/O registers
0010 0000h
On-chip ROM (E2 DataFlash)
(8 KB)
0010 2000h
Reserved area*3
007F C000h
007F C500h
Peripheral I/O registers
Reserved area*3
007F FC00h
0080 0000h
Peripheral I/O registers
Reserved area*3
00FC 0000h
On-chip ROM (program ROM)
(write only) (256 KB)
0100 0000h
Reserved area*3
FF7F C000h
On-chip ROM (user boot)
(read only) (16 KB)
FF80 0000h
FFFC 0000h
FFFF FFFFh
Reserved area*3
On-chip ROM (program ROM)
(read only)*2
Note 1. The address space in boot mode and user boot mode is the same as the address space in single-chip mode.
Note 2. The capacity of ROM/RAM differs depending on the products.
ROM (bytes)
Capacity
Address
RAM (bytes)
Capacity
Address
256 K
FFFC 0000h to FFFF FFFFh
16 K
0000 0000h to 0000 3FFFh
128 K
FFFE 0000h to FFFF FFFFh
8K
0000 0000h to 0000 1FFFh
4K
0000 0000h to 0000 0FFFh
64K
FFFF 0000h to FFFF FFFFh
32 K
FFFF 8000h to FFFF FFFFh
Note:•See Table 1.3, List of Products, for the product type name.
Note 3. Reserved areas should not be accessed.
Figure 3.1
Memory Map
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RX220 Group
4.
4. I/O Registers
I/O Registers
This section provides information on the on-chip I/O register addresses and bit configuration. The information is given as
shown below. Notes on writing to registers are also given below.
(1)
I/O register addresses (address order)
Registers are listed from the lower allocation addresses.
Registers are classified according to module symbols.
Numbers of cycles for access indicate numbers of cycles of the given base clock.
Among the internal I/O register area, addresses not listed in the list of registers are reserved. Reserved addresses
must not be accessed. Do not access these addresses; otherwise, the operation when accessing these bits and
subsequent operations cannot be guaranteed.
(2)
Notes on writing to I/O registers
When writing to an I/O register, the CPU starts executing the subsequent instruction before completing I/O register write.
This may cause the subsequent instruction to be executed before the post-update I/O register value is reflected on the
operation.
As described in the following examples, special care is required for the cases in which the subsequent instruction must be
executed after the post-update I/O register value is actually reflected.
[Examples of cases requiring special care]
The subsequent instruction must be executed while an interrupt request is disabled with the IENj bit in IERn of the
ICU (interrupt request enable bit) cleared to 0.
A WAIT instruction is executed immediately after the preprocessing for causing a transition to the low power
consumption state.
In the above cases, after writing to an I/O register, wait until the write operation is completed using the following
procedure and then execute the subsequent instruction.
(a)
(b)
(c)
(d)
Write to an I/O register.
Read the value from the I/O register to a general register.
Execute the operation using the value read.
Execute the subsequent instruction.
[Instruction examples]
Byte-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.B #SFR_DATA, [R1]
CMP [R1].UB, R1
;; Next process
Word-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.W #SFR_DATA, [R1]
CMP [R1].W, R1
;; Next process
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RX220 Group
4. I/O Registers
Longword-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.L #SFR_DATA, [R1]
CMP [R1].L, R1
;; Next process
If multiple registers are written to and a subsequent instruction should be executed after the write operations are entirely
completed, only read the I/O register that was last written to and execute the operation using the value; it is not necessary
to read or execute operation for all the registers that were written to.
(3)
Number of Access Cycles to I/O Registers
For numbers of clock cycles for access to I/O registers, see Table 4.1, List of I/O Registers (Address Order).
The number of access cycles to I/O registers is obtained by following equation.*1
Number of access cycles to I/O registers = Number of bus cycles for internal main bus 1 +
Number of divided clock synchronization cycles +
Number of bus cycles for internal peripheral bus 1 to 6
The number of bus cycles of internal peripheral bus 1 to 6 differs according to the register to be accessed.
When peripheral functions connected to internal peripheral bus 2 to 6 are accessed, the number of divided clock
synchronization cycles is added.
The number of divided clock synchronization cycles differs depending on the frequency ratio between ICLK and PCLK
(or FCLK) or bus access timing.
In the peripheral function unit, when the frequency ratio of ICLK is equal to or greater than that of PCLK (or FCLK), the
sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will
be one cycle of PCLK (or FCLK) at a maximum. Therefore, one PCLK (or FCLK) has been added to the number of
access cycles shown in Table 4.1.
When the frequency ratio of ICLK is lower than that of PCLK (or FCLK), the subsequent bus access is started from the
ICLK cycle following the completion of the access to the peripheral functions. Therefore, the access cycles are described
on an ICLK basis.
Note 1.
This applies to the number of cycles when the access from the CPU does not conflict with the instruction bus
access from the different bus master (DMAC or DTC).
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RX220 Group
4.1
4. I/O Registers
I/O Register Addresses (Address Order)
Table 4.1
List of I/O Registers (Address Order) (1 / 20)
Number of Access Cycles
Address
Module
Symbol
Register Name
Register
Symbol
0008 0000h
SYSTEM
Mode monitor register
ICLK
PCLK
Number
of Bits
Access
Size
ICLK <
PCLK
MDMONR
16
16
3 ICLK
3 ICLK
0008 0002h
SYSTEM
Mode status register
MDSR
16
16
0008 0008h
SYSTEM
System control register 1
SYSCR1
16
16
3 ICLK
0008 000Ch
SYSTEM
Standby control register
SBYCR
16
16
3 ICLK
0008 0010h
SYSTEM
Module stop control register A
MSTPCRA
32
32
3 ICLK
0008 0014h
SYSTEM
Module stop control register B
MSTPCRB
32
32
3 ICLK
0008 0018h
SYSTEM
Module stop control register C
MSTPCRC
32
32
3 ICLK
0008 0020h
SYSTEM
System clock control register
SCKCR
32
32
3 ICLK
0008 0026h
SYSTEM
System clock control register 3
SCKCR3
16
16
3 ICLK
0008 0032h
SYSTEM
Main clock oscillator control register
MOSCCR
8
8
3 ICLK
0008 0033h
SYSTEM
Sub-clock oscillator control register
SOSCCR
8
8
3 ICLK
0008 0035h
SYSTEM
IWDT-dedicated on-chip oscillator control register
ILOCOCR
8
8
3 ICLK
0008 0036h
SYSTEM
High-speed on-chip oscillator control register
HOCOCR
8
8
3 ICLK
0008 0037h
SYSTEM
High-speed on-chip oscillator control register 2
HOCOCR2
8
8
3 ICLK
0008 0040h
SYSTEM
Oscillation stop detection control register
OSTDCR
8
8
3 ICLK
0008 0041h
SYSTEM
Oscillation stop detection status register
OSTDSR
8
8
3 ICLK
0008 00A0h
SYSTEM
Operating power control register
OPCCR
8
8
3 ICLK
0008 00A1h
SYSTEM
Sleep mode return clock source switching register
RSTCKCR
8
8
3 ICLK
3 ICLK
0008 00A2h
SYSTEM
Main clock oscillator wait control register
MOSCWTCR
8
8
0008 00A3h
SYSTEM
Sub-clock oscillator wait control register
SOSCWTCR
8
8
3 ICLK
0008 00A9h
SYSTEM
HOCO wait control register 2
HOCOWTCR2
8
8
3 ICLK
0008 00C0h
SYSTEM
Reset status register 2
RSTSR2
8
8
3 ICLK
0008 00C2h
SYSTEM
Software reset register
SWRR
16
16
3 ICLK
0008 00E0h
SYSTEM
Voltage monitoring 1 circuit/comparator A1 control register 1
LVD1CR1
8
8
3 ICLK
0008 00E1h
SYSTEM
Voltage monitoring 1 circuit/comparator A1 status register
LVD1SR
8
8
3 ICLK
0008 00E2h
SYSTEM
Voltage monitoring 2 circuit/comparator A2 control register 1
LVD2CR1
8
8
3 ICLK
0008 00E3h
SYSTEM
Voltage monitoring 2 circuit/comparator A2 status register
LVD2SR
8
8
3 ICLK
0008 03FEh
SYSTEM
Protect register
PRCR
16
16
3 ICLK
0008 1300h
BSC
Bus error status clear register
BERCLR
8
8
2 ICLK
0008 1304h
BSC
Bus error monitoring enable register
BEREN
8
8
2 ICLK
0008 1308h
BSC
Bus error status register 1
BERSR1
8
8
2 ICLK
0008 130Ah
BSC
Bus error status register 2
BERSR2
16
16
2 ICLK
0008 1310h
BSC
Bus priority control register
BUSPRI
16
16
2 ICLK
0008 2000h
DMAC0
DMA source address register
DMSAR
32
32
2 ICLK
0008 2004h
DMAC0
DMA destination address register
DMDAR
32
32
2 ICLK
0008 2008h
DMAC0
DMA transfer count register
DMCRA
32
32
2 ICLK
0008 200Ch
DMAC0
DMA block transfer count register
DMCRB
16
16
2 ICLK
0008 2010h
DMAC0
DMA transfer mode register
DMTMD
16
16
2 ICLK
0008 2013h
DMAC0
DMA interrupt setting register
DMINT
8
8
2 ICLK
0008 2014h
DMAC0
DMA address mode register
DMAMD
16
16
2 ICLK
0008 2018h
DMAC0
DMA offset register
DMOFR
32
32
2 ICLK
0008 201Ch
DMAC0
DMA transfer enable register
DMCNT
8
8
2 ICLK
0008 201Dh
DMAC0
DMA software start register
DMREQ
8
8
2 ICLK
0008 201Eh
DMAC0
DMA status register
DMSTS
8
8
2 ICLK
0008 201Fh
DMAC0
DMA activation source flag control register
DMCSL
8
8
2 ICLK
0008 2040h
DMAC1
DMA source address register
DMSAR
32
32
2 ICLK
0008 2044h
DMAC1
DMA destination address register
DMDAR
32
32
2 ICLK
0008 2048h
DMAC1
DMA transfer count register
DMCRA
32
32
2 ICLK
0008 204Ch
DMAC1
DMA block transfer count register
DMCRB
16
16
2 ICLK
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RX220 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (2 / 20)
Number of Access Cycles
Address
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
ICLK
PCLK
ICLK <
PCLK
0008 2050h
DMAC1
DMA transfer mode register
DMTMD
16
16
2 ICLK
0008 2053h
DMAC1
DMA interrupt setting register
DMINT
8
8
2 ICLK
0008 2054h
DMAC1
DMA address mode register
DMAMD
16
16
2 ICLK
0008 205Ch
DMAC1
DMA transfer enable register
DMCNT
8
8
2 ICLK
0008 205Dh
DMAC1
DMA software start register
DMREQ
8
8
2 ICLK
0008 205Eh
DMAC1
DMA status register
DMSTS
8
8
2 ICLK
0008 205Fh
DMAC1
DMA activation source flag control register
DMCSL
8
8
2 ICLK
0008 2080h
DMAC2
DMA source address register
DMSAR
32
32
2 ICLK
0008 2084h
DMAC2
DMA destination address register
DMDAR
32
32
2 ICLK
0008 2088h
DMAC2
DMA transfer count register
DMCRA
32
32
2 ICLK
0008 208Ch
DMAC2
DMA block transfer count register
DMCRB
16
16
2 ICLK
0008 2090h
DMAC2
DMA transfer mode register
DMTMD
16
16
2 ICLK
0008 2093h
DMAC2
DMA interrupt setting register
DMINT
8
8
2 ICLK
0008 2094h
DMAC2
DMA address mode register
DMAMD
16
16
2 ICLK
0008 209Ch
DMAC2
DMA transfer enable register
DMCNT
8
8
2 ICLK
0008 209Dh
DMAC2
DMA software start register
DMREQ
8
8
2 ICLK
0008 209Eh
DMAC2
DMA status register
DMSTS
8
8
2 ICLK
0008 209Fh
DMAC2
DMA activation source flag control register
DMCSL
8
8
2 ICLK
0008 20C0h
DMAC3
DMA source address register
DMSAR
32
32
2 ICLK
0008 20C4h
DMAC3
DMA destination address register
DMDAR
32
32
2 ICLK
0008 20C8h
DMAC3
DMA transfer count register
DMCRA
32
32
2 ICLK
0008 20CCh
DMAC3
DMA block transfer count register
DMCRB
16
16
2 ICLK
0008 20D0h
DMAC3
DMA transfer mode register
DMTMD
16
16
2 ICLK
0008 20D3h
DMAC3
DMA interrupt setting register
DMINT
8
8
2 ICLK
0008 20D4h
DMAC3
DMA address mode register
DMAMD
16
16
2 ICLK
2 ICLK
0008 20DCh
DMAC3
DMA transfer enable register
DMCNT
8
8
0008 20DDh
DMAC3
DMA software start register
DMREQ
8
8
2 ICLK
0008 20DEh
DMAC3
DMA status register
DMSTS
8
8
2 ICLK
0008 20DFh
DMAC3
DMA activation source flag control register
DMCSL
8
8
2 ICLK
0008 2200h
DMAC
DMA module activation register
DMAST
8
8
2 ICLK
0008 2400h
DTC
DTC control register
DTCCR
8
8
2 ICLK
0008 2404h
DTC
DTC vector base register
DTCVBR
32
32
2 ICLK
0008 2408h
DTC
DTC address mode register
DTCADMOD
8
8
2 ICLK
2 ICLK
0008 240Ch
DTC
DTC module start register
DTCST
8
8
0008 240Eh
DTC
DTC status register
DTCSTS
16
16
2 ICLK
0008 7010h
ICU
Interrupt request register 016
IR016
8
8
2 ICLK
0008 7015h
ICU
Interrupt request register 021
IR021
8
8
2 ICLK
0008 7017h
ICU
Interrupt request register 023
IR023
8
8
2 ICLK
0008 701Bh
ICU
Interrupt request register 027
IR027
8
8
2 ICLK
0008 701Ch
ICU
Interrupt request register 028
IR028
8
8
2 ICLK
0008 701Dh
ICU
Interrupt request register 029
IR029
8
8
2 ICLK
0008 701Eh
ICU
Interrupt request register 030
IR030
8
8
2 ICLK
0008 701Fh
ICU
Interrupt request register 031
IR031
8
8
2 ICLK
0008 7020h
ICU
Interrupt request register 032
IR032
8
8
2 ICLK
0008 7021h
ICU
Interrupt request register 033
IR033
8
8
2 ICLK
2 ICLK
0008 7022h
ICU
Interrupt request register 034
IR034
8
8
0008 702Ch
ICU
Interrupt request register 044
IR044
8
8
2 ICLK
0008 702Dh
ICU
Interrupt request register 045
IR045
8
8
2 ICLK
0008 702Eh
ICU
Interrupt request register 046
IR046
8
8
2 ICLK
0008 702Fh
ICU
Interrupt request register 047
IR047
8
8
2 ICLK
0008 7039h
ICU
Interrupt request register 057
IR057
8
8
2 ICLK
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RX220 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (3 / 20)
Number of Access Cycles
Register
Symbol
Number
of Bits
Access
Size
ICLK
PCLK
Address
Module
Symbol
Register Name
ICLK <
PCLK
0008 703Fh
ICU
Interrupt request register 063
IR063
8
8
2 ICLK
0008 7040h
ICU
Interrupt request register 064
IR064
8
8
2 ICLK
0008 7041h
ICU
Interrupt request register 065
IR065
8
8
2 ICLK
0008 7042h
ICU
Interrupt request register 066
IR066
8
8
2 ICLK
0008 7043h
ICU
Interrupt request register 067
IR067
8
8
2 ICLK
0008 7044h
ICU
Interrupt request register 068
IR068
8
8
2 ICLK
0008 7045h
ICU
Interrupt request register 069
IR069
8
8
2 ICLK
0008 7046h
ICU
Interrupt request register 070
IR070
8
8
2 ICLK
0008 7047h
ICU
Interrupt request register 071
IR071
8
8
2 ICLK
0008 7058h
ICU
Interrupt request register 088
IR088
8
8
2 ICLK
0008 7059h
ICU
Interrupt request register 089
IR089
8
8
2 ICLK
0008 705Ch
ICU
Interrupt request register 092
IR092
8
8
2 ICLK
0008 705Dh
ICU
Interrupt request register 093
IR093
8
8
2 ICLK
0008 7066h
ICU
Interrupt request register 102
IR102
8
8
2 ICLK
0008 7067h
ICU
Interrupt request register 103
IR103
8
8
2 ICLK
0008 706Ah
ICU
Interrupt request register 106
IR106
8
8
2 ICLK
0008 7072h
ICU
Interrupt request register 114
IR114
8
8
2 ICLK
0008 7073h
ICU
Interrupt request register 115
IR115
8
8
2 ICLK
0008 7074h
ICU
Interrupt request register 116
IR116
8
8
2 ICLK
0008 7075h
ICU
Interrupt request register 117
IR117
8
8
2 ICLK
0008 7076h
ICU
Interrupt request register 118
IR118
8
8
2 ICLK
0008 7077h
ICU
Interrupt request register 119
IR119
8
8
2 ICLK
0008 7078h
ICU
Interrupt request register 120
IR120
8
8
2 ICLK
0008 7079h
ICU
Interrupt request register 121
IR121
8
8
2 ICLK
0008 707Ah
ICU
Interrupt request register 122
IR122
8
8
2 ICLK
0008 707Bh
ICU
Interrupt request register 123
IR123
8
8
2 ICLK
0008 707Ch
ICU
Interrupt request register 124
IR124
8
8
2 ICLK
0008 707Dh
ICU
Interrupt request register 125
IR125
8
8
2 ICLK
0008 707Eh
ICU
Interrupt request register 126
IR126
8
8
2 ICLK
0008 707Fh
ICU
Interrupt request register 127
IR127
8
8
2 ICLK
0008 7080h
ICU
Interrupt request register 128
IR128
8
8
2 ICLK
0008 7081h
ICU
Interrupt request register 129
IR129
8
8
2 ICLK
0008 7082h
ICU
Interrupt request register 130
IR130
8
8
2 ICLK
0008 7083h
ICU
Interrupt request register 131
IR131
8
8
2 ICLK
0008 7084h
ICU
Interrupt request register 132
IR132
8
8
2 ICLK
0008 7085h
ICU
Interrupt request register 133
IR133
8
8
2 ICLK
0008 7086h
ICU
Interrupt request register 134
IR134
8
8
2 ICLK
0008 7087h
ICU
Interrupt request register 135
IR135
8
8
2 ICLK
0008 7088h
ICU
Interrupt request register 136
IR136
8
8
2 ICLK
0008 7089h
ICU
Interrupt request register 137
IR137
8
8
2 ICLK
0008 708Ah
ICU
Interrupt request register 138
IR138
8
8
2 ICLK
0008 708Bh
ICU
Interrupt request register 139
IR139
8
8
2 ICLK
0008 708Ch
ICU
Interrupt request register 140
IR140
8
8
2 ICLK
0008 708Dh
ICU
Interrupt request register 141
IR141
8
8
2 ICLK
0008 70AAh
ICU
Interrupt request register 170
IR170
8
8
2 ICLK
0008 70ABh
ICU
Interrupt request register 171
IR171
8
8
2 ICLK
0008 70AEh
ICU
Interrupt request register 174
IR174
8
8
2 ICLK
0008 70AFh
ICU
Interrupt request register 175
IR175
8
8
2 ICLK
0008 70B0h
ICU
Interrupt request register 176
IR176
8
8
2 ICLK
0008 70B1h
ICU
Interrupt request register 177
IR177
8
8
2 ICLK
0008 70B2h
ICU
Interrupt request register 178
IR178
8
8
2 ICLK
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 29 of 105
RX220 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (4 / 20)
Number of Access Cycles
Address
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
ICLK
PCLK
ICLK <
PCLK
0008 70B3h
ICU
Interrupt request register 179
IR179
8
8
2 ICLK
0008 70B4h
ICU
Interrupt request register 180
IR180
8
8
2 ICLK
0008 70B5h
ICU
Interrupt request register 181
IR181
8
8
2 ICLK
0008 70B6h
ICU
Interrupt request register 182
IR182
8
8
2 ICLK
0008 70B7h
ICU
Interrupt request register 183
IR183
8
8
2 ICLK
0008 70B8h
ICU
Interrupt request register 184
IR184
8
8
2 ICLK
0008 70B9h
ICU
Interrupt request register 185
IR185
8
8
2 ICLK
0008 70C6h
ICU
Interrupt request register 198
IR198
8
8
2 ICLK
0008 70C7h
ICU
Interrupt request register 199
IR199
8
8
2 ICLK
0008 70C8h
ICU
Interrupt request register 200
IR200
8
8
2 ICLK
0008 70C9h
ICU
Interrupt request register 201
IR201
8
8
2 ICLK
0008 70DAh
ICU
Interrupt request register 218
IR218
8
8
2 ICLK
0008 70DBh
ICU
Interrupt request register 219
IR219
8
8
2 ICLK
0008 70DCh
ICU
Interrupt request register 220
IR220
8
8
2 ICLK
0008 70DDh
ICU
Interrupt request register 221
IR221
8
8
2 ICLK
0008 70DEh
ICU
Interrupt request register 222
IR222
8
8
2 ICLK
0008 70DFh
ICU
Interrupt request register 223
IR223
8
8
2 ICLK
0008 70E0h
ICU
Interrupt request register 224
IR224
8
8
2 ICLK
0008 70E1h
ICU
Interrupt request register 225
IR225
8
8
2 ICLK
0008 70E2h
ICU
Interrupt request register 226
IR226
8
8
2 ICLK
0008 70E3h
ICU
Interrupt request register 227
IR227
8
8
2 ICLK
0008 70E4h
ICU
Interrupt request register 228
IR228
8
8
2 ICLK
0008 70E5h
ICU
Interrupt request register 229
IR229
8
8
2 ICLK
0008 70EAh
ICU
Interrupt request register 234
IR234
8
8
2 ICLK
0008 70EBh
ICU
Interrupt request register 235
IR235
8
8
2 ICLK
0008 70ECh
ICU
Interrupt request register 236
IR236
8
8
2 ICLK
0008 70EDh
ICU
Interrupt request register 237
IR237
8
8
2 ICLK
0008 70EEh
ICU
Interrupt request register 238
IR238
8
8
2 ICLK
0008 70EFh
ICU
Interrupt request register 239
IR239
8
8
2 ICLK
0008 70F0h
ICU
Interrupt request register 240
IR240
8
8
2 ICLK
0008 70F1h
ICU
Interrupt request register 241
IR241
8
8
2 ICLK
0008 70F2h
ICU
Interrupt request register 242
IR242
8
8
2 ICLK
0008 70F3h
ICU
Interrupt request register 243
IR243
8
8
2 ICLK
0008 70F4h
ICU
Interrupt request register 244
IR244
8
8
2 ICLK
0008 70F5h
ICU
Interrupt request register 245
IR245
8
8
2 ICLK
0008 70F6h
ICU
Interrupt request register 246
IR246
8
8
2 ICLK
0008 70F7h
ICU
Interrupt request register 247
IR247
8
8
2 ICLK
0008 70F8h
ICU
Interrupt request register 248
IR248
8
8
2 ICLK
0008 70F9h
ICU
Interrupt request register 249
IR249
8
8
2 ICLK
0008 711Bh
ICU
DTC activation enable register 027
DTCER027
8
8
2 ICLK
0008 711Ch
ICU
DTC activation enable register 028
DTCER028
8
8
2 ICLK
0008 711Dh
ICU
DTC activation enable register 029
DTCER029
8
8
2 ICLK
0008 711Eh
ICU
DTC activation enable register 030
DTCER030
8
8
2 ICLK
0008 711Fh
ICU
DTC activation enable register 031
DTCER031
8
8
2 ICLK
0008 712Dh
ICU
DTC activation enable register 045
DTCER045
8
8
2 ICLK
0008 712Eh
ICU
DTC activation enable register 046
DTCER046
8
8
2 ICLK
0008 7140h
ICU
DTC activation enable register 064
DTCER064
8
8
2 ICLK
0008 7141h
ICU
DTC activation enable register 065
DTCER065
8
8
2 ICLK
0008 7142h
ICU
DTC activation enable register 066
DTCER066
8
8
2 ICLK
0008 7143h
ICU
DTC activation enable register 067
DTCER067
8
8
2 ICLK
0008 7144h
ICU
DTC activation enable register 068
DTCER068
8
8
2 ICLK
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 30 of 105
RX220 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (5 / 20)
Number of Access Cycles
Address
Module
Symbol
Register Name
Register
Symbol
0008 7145h
ICU
DTC activation enable register 069
0008 7146h
ICU
DTC activation enable register 070
0008 7147h
ICU
0008 7166h
0008 7167h
ICLK
PCLK
Number
of Bits
Access
Size
DTCER069
8
8
2 ICLK
DTCER070
8
8
2 ICLK
DTC activation enable register 071
DTCER071
8
8
2 ICLK
ICU
DTC activation enable register 102
DTCER102
8
8
2 ICLK
ICU
DTC activation enable register 103
DTCER103
8
8
2 ICLK
0008 716Ah
ICU
DTC activation enable register 106
DTCER106
8
8
2 ICLK
0008 7172h
ICU
DTC activation enable register 114
DTCER114
8
8
2 ICLK
0008 7173h
ICU
DTC activation enable register 115
DTCER115
8
8
2 ICLK
0008 7174h
ICU
DTC activation enable register 116
DTCER116
8
8
2 ICLK
0008 7175h
ICU
DTC activation enable register 117
DTCER117
8
8
2 ICLK
0008 7179h
ICU
DTC activation enable register 121
DTCER121
8
8
2 ICLK
0008 717Ah
ICU
DTC activation enable register 122
DTCER122
8
8
2 ICLK
0008 717Dh
ICU
DTC activation enable register 125
DTCER125
8
8
2 ICLK
0008 717Eh
ICU
DTC activation enable register 126
DTCER126
8
8
2 ICLK
0008 7181h
ICU
DTC activation enable register 129
DTCER129
8
8
2 ICLK
0008 7182h
ICU
DTC activation enable register 130
DTCER130
8
8
2 ICLK
0008 7183h
ICU
DTC activation enable register 131
DTCER131
8
8
2 ICLK
0008 7184h
ICU
DTC activation enable register 132
DTCER132
8
8
2 ICLK
0008 7186h
ICU
DTC activation enable register 134
DTCER134
8
8
2 ICLK
0008 7187h
ICU
DTC activation enable register 135
DTCER135
8
8
2 ICLK
0008 7188h
ICU
DTC activation enable register 136
DTCER136
8
8
2 ICLK
0008 7189h
ICU
DTC activation enable register 137
DTCER137
8
8
2 ICLK
0008 718Ah
ICU
DTC activation enable register 138
DTCER138
8
8
2 ICLK
0008 718Bh
ICU
DTC activation enable register 139
DTCER139
8
8
2 ICLK
0008 718Ch
ICU
DTC activation enable register 140
DTCER140
8
8
2 ICLK
0008 718Dh
ICU
DTC activation enable register 141
DTCER141
8
8
2 ICLK
0008 71AEh
ICU
DTC activation enable register 174
DTCER174
8
8
2 ICLK
0008 71AFh
ICU
DTC activation enable register 175
DTCER175
8
8
2 ICLK
0008 71B1h
ICU
DTC activation enable register 177
DTCER177
8
8
2 ICLK
0008 71B2h
ICU
DTC activation enable register 178
DTCER178
8
8
2 ICLK
0008 71B4h
ICU
DTC activation enable register 180
DTCER180
8
8
2 ICLK
0008 71B5h
ICU
DTC activation enable register 181
DTCER181
8
8
2 ICLK
0008 71B7h
ICU
DTC activation enable register 183
DTCER183
8
8
2 ICLK
0008 71B8h
ICU
DTC activation enable register 184
DTCER184
8
8
2 ICLK
0008 71C6h
ICU
DTC activation enable register 198
DTCER198
8
8
2 ICLK
0008 71C7h
ICU
DTC activation enable register 199
DTCER199
8
8
2 ICLK
0008 71C8h
ICU
DTC activation enable register 200
DTCER200
8
8
2 ICLK
0008 71C9h
ICU
DTC activation enable register 201
DTCER201
8
8
2 ICLK
0008 71DBh
ICU
DTC activation enable register 219
DTCER219
8
8
2 ICLK
0008 71DCh
ICU
DTC activation enable register 220
DTCER220
8
8
2 ICLK
0008 71DFh
ICU
DTC activation enable register 223
DTCER223
8
8
2 ICLK
0008 71E0h
ICU
DTC activation enable register 224
DTCER224
8
8
2 ICLK
0008 71E3h
ICU
DTC activation enable register 227
DTCER227
8
8
2 ICLK
0008 71E4h
ICU
DTC activation enable register 228
DTCER228
8
8
2 ICLK
0008 71EBh
ICU
DTC activation enable register 235
DTCER235
8
8
2 ICLK
0008 71ECh
ICU
DTC activation enable register 236
DTCER236
8
8
2 ICLK
0008 71EFh
ICU
DTC activation enable register 239
DTCER239
8
8
2 ICLK
0008 71F0h
ICU
DTC activation enable register 240
DTCER240
8
8
2 ICLK
0008 71F7h
ICU
DTC activation enable register 247
DTCER247
8
8
2 ICLK
0008 71F8h
ICU
DTC activation enable register 248
DTCER248
8
8
2 ICLK
0008 7202h
ICU
Interrupt request enable register 02
IER02
8
8
2 ICLK
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
ICLK <
PCLK
Page 31 of 105
RX220 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (6 / 20)
Number of Access Cycles
Address
Module
Symbol
Register Name
Register
Symbol
0008 7203h
ICU
Interrupt request enable register 03
0008 7204h
ICU
Interrupt request enable register 04
0008 7205h
ICU
0008 7207h
0008 7208h
ICLK
PCLK
Number
of Bits
Access
Size
ICLK <
PCLK
IER03
8
8
2 ICLK
IER04
8
8
2 ICLK
Interrupt request enable register 05
IER05
8
8
2 ICLK
ICU
Interrupt request enable register 07
IER07
8
8
2 ICLK
ICU
Interrupt request enable register 08
IER08
8
8
2 ICLK
0008 720Bh
ICU
Interrupt request enable register 0B
IER0B
8
8
2 ICLK
0008 720Ch
ICU
Interrupt request enable register 0C
IER0C
8
8
2 ICLK
0008 720Dh
ICU
Interrupt request enable register 0D
IER0D
8
8
2 ICLK
0008 720Eh
ICU
Interrupt request enable register 0E
IER0E
8
8
2 ICLK
0008 720Fh
ICU
Interrupt request enable register 0F
IER0F
8
8
2 ICLK
0008 7210h
ICU
Interrupt request enable register 10
IER10
8
8
2 ICLK
0008 7211h
ICU
Interrupt request enable register 11
IER11
8
8
2 ICLK
0008 7215h
ICU
Interrupt request enable register 15
IER15
8
8
2 ICLK
0008 7216h
ICU
Interrupt request enable register 16
IER16
8
8
2 ICLK
0008 7217h
ICU
Interrupt request enable register 17
IER17
8
8
2 ICLK
0008 7218h
ICU
Interrupt request enable register 18
IER18
8
8
2 ICLK
0008 7219h
ICU
Interrupt request enable register 19
IER19
8
8
2 ICLK
0008 721Bh
ICU
Interrupt request enable register 1B
IER1B
8
8
2 ICLK
0008 721Ch
ICU
Interrupt request enable register 1C
IER1C
8
8
2 ICLK
0008 721Dh
ICU
Interrupt request enable register 1D
IER1D
8
8
2 ICLK
0008 721Eh
ICU
Interrupt request enable register 1E
IER1E
8
8
2 ICLK
0008 721Fh
ICU
Interrupt request enable register 1F
IER1F
8
8
2 ICLK
0008 72E0h
ICU
Software interrupt activation register
SWINTR
8
8
2 ICLK
0008 72F0h
ICU
Fast interrupt set register
FIR
16
16
2 ICLK
0008 7300h
ICU
Interrupt source priority register 000
IPR000
8
8
2 ICLK
0008 7301h
ICU
Interrupt source priority register 001
IPR001
8
8
2 ICLK
0008 7302h
ICU
Interrupt source priority register 002
IPR002
8
8
2 ICLK
0008 7303h
ICU
Interrupt source priority register 003
IPR003
8
8
2 ICLK
0008 7304h
ICU
Interrupt source priority register 004
IPR004
8
8
2 ICLK
0008 7305h
ICU
Interrupt source priority register 005
IPR005
8
8
2 ICLK
0008 7306h
ICU
Interrupt source priority register 006
IPR006
8
8
2 ICLK
0008 7307h
ICU
Interrupt source priority register 007
IPR007
8
8
2 ICLK
0008 7320h
ICU
Interrupt source priority register 032
IPR032
8
8
2 ICLK
0008 7321h
ICU
Interrupt source priority register 033
IPR033
8
8
2 ICLK
0008 7322h
ICU
Interrupt source priority register 034
IPR034
8
8
2 ICLK
0008 732Ch
ICU
Interrupt source priority register 044
IPR044
8
8
2 ICLK
0008 7339h
ICU
Interrupt source priority register 057
IPR057
8
8
2 ICLK
0008 733Fh
ICU
Interrupt source priority register 063
IPR063
8
8
2 ICLK
0008 7340h
ICU
Interrupt source priority register 064
IPR064
8
8
2 ICLK
0008 7341h
ICU
Interrupt source priority register 065
IPR065
8
8
2 ICLK
0008 7342h
ICU
Interrupt source priority register 066
IPR066
8
8
2 ICLK
0008 7343h
ICU
Interrupt source priority register 067
IPR067
8
8
2 ICLK
0008 7344h
ICU
Interrupt source priority register 068
IPR068
8
8
2 ICLK
0008 7345h
ICU
Interrupt source priority register 069
IPR069
8
8
2 ICLK
0008 7346h
ICU
Interrupt source priority register 070
IPR070
8
8
2 ICLK
0008 7347h
ICU
Interrupt source priority register 071
IPR071
8
8
2 ICLK
0008 7358h
ICU
Interrupt source priority register 088
IPR088
8
8
2 ICLK
0008 7359h
ICU
Interrupt source priority register 089
IPR089
8
8
2 ICLK
0008 735Ch
ICU
Interrupt source priority register 092
IPR092
8
8
2 ICLK
0008 735Dh
ICU
Interrupt source priority register 093
IPR093
8
8
2 ICLK
0008 7366h
ICU
Interrupt source priority register 102
IPR102
8
8
2 ICLK
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 32 of 105
RX220 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (7 / 20)
Number of Access Cycles
Address
Module
Symbol
Register Name
Register
Symbol
0008 7367h
ICU
Interrupt source priority register 103
0008 736Ah
ICU
Interrupt source priority register 106
0008 7372h
ICU
0008 7376h
0008 7379h
ICLK
PCLK
Number
of Bits
Access
Size
ICLK <
PCLK
IPR103
8
8
IPR106
8
8
2 ICLK
Interrupt source priority register 114
IPR114
8
8
2 ICLK
ICU
Interrupt source priority register 118
IPR118
8
8
2 ICLK
ICU
Interrupt source priority register 121
IPR121
8
8
2 ICLK
0008 737Bh
ICU
Interrupt source priority register 123
IPR123
8
8
2 ICLK
0008 737Dh
ICU
Interrupt source priority register 125
IPR125
8
8
2 ICLK
0008 737Fh
ICU
Interrupt source priority register 127
IPR127
8
8
2 ICLK
0008 7381h
ICU
Interrupt source priority register 129
IPR129
8
8
2 ICLK
0008 7385h
ICU
Interrupt source priority register 133
IPR133
8
8
2 ICLK
0008 7386h
ICU
Interrupt source priority register 134
IPR134
8
8
2 ICLK
0008 738Ah
ICU
Interrupt source priority register 138
IPR138
8
8
2 ICLK
0008 738Bh
ICU
Interrupt source priority register 139
IPR139
8
8
2 ICLK
0008 73AAh
ICU
Interrupt source priority register 170
IPR170
8
8
2 ICLK
0008 73ABh
ICU
Interrupt source priority register 171
IPR171
8
8
2 ICLK
0008 73AEh
ICU
Interrupt source priority register 174
IPR174
8
8
2 ICLK
0008 73B1h
ICU
Interrupt source priority register 177
IPR177
8
8
2 ICLK
0008 73B4h
ICU
Interrupt source priority register 180
IPR180
8
8
2 ICLK
0008 73B7h
ICU
Interrupt source priority register 183
IPR183
8
8
2 ICLK
0008 73C6h
ICU
Interrupt source priority register 198
IPR198
8
8
2 ICLK
0008 73C7h
ICU
Interrupt source priority register 199
IPR199
8
8
2 ICLK
0008 73C8h
ICU
Interrupt source priority register 200
IPR200
8
8
2 ICLK
0008 73C9h
ICU
Interrupt source priority register 201
IPR201
8
8
2 ICLK
0008 73DAh
ICU
Interrupt source priority register 218
IPR218
8
8
2 ICLK
0008 73DEh
ICU
Interrupt source priority register 222
IPR222
8
8
2 ICLK
0008 73E2h
ICU
Interrupt source priority register 226
IPR226
8
8
2 ICLK
0008 73EAh
ICU
Interrupt source priority register 234
IPR234
8
8
2 ICLK
0008 73EEh
ICU
Interrupt source priority register 238
IPR238
8
8
2 ICLK
0008 73F2h
ICU
Interrupt source priority register 242
IPR242
8
8
2 ICLK
0008 73F3h
ICU
Interrupt source priority register 243
IPR243
8
8
2 ICLK
2 ICLK
0008 73F4h
ICU
Interrupt source priority register 244
IPR244
8
8
2 ICLK
0008 73F5h
ICU
Interrupt source priority register 245
IPR245
8
8
2 ICLK
0008 73F6h
ICU
Interrupt source priority register 246
IPR246
8
8
2 ICLK
0008 73F7h
ICU
Interrupt source priority register 247
IPR247
8
8
2 ICLK
0008 73F8h
ICU
Interrupt source priority register 248
IPR248
8
8
2 ICLK
0008 73F9h
ICU
Interrupt source priority register 249
IPR249
8
8
2 ICLK
0008 7400h
ICU
DMAC activation request select register 0
DMRSR0
8
8
2 ICLK
0008 7404h
ICU
DMAC activation request select register 1
DMRSR1
8
8
2 ICLK
0008 7408h
ICU
DMAC activation request select register 2
DMRSR2
8
8
2 ICLK
0008 740Ch
ICU
DMAC activation request select register 3
DMRSR3
8
8
2 ICLK
0008 7500h
ICU
IRQ control register 0
IRQCR0
8
8
2 ICLK
0008 7501h
ICU
IRQ control register 1
IRQCR1
8
8
2 ICLK
0008 7502h
ICU
IRQ control register 2
IRQCR2
8
8
2 ICLK
0008 7503h
ICU
IRQ control register 3
IRQCR3
8
8
2 ICLK
0008 7504h
ICU
IRQ control register 4
IRQCR4
8
8
2 ICLK
0008 7505h
ICU
IRQ control register 5
IRQCR5
8
8
2 ICLK
0008 7506h
ICU
IRQ control register 6
IRQCR6
8
8
2 ICLK
0008 7507h
ICU
IRQ control register 7
IRQCR7
8
8
2 ICLK
0008 7510h
ICU
IRQ pin digital filter enable register 0
IRQFLTE0
8
8
2 ICLK
0008 7514h
ICU
IRQ pin digital filter setting register 0
IRQFLTC0
16
16
2 ICLK
0008 7580h
ICU
Non-maskable interrupt status register
NMISR
8
8
2 ICLK
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 33 of 105
RX220 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (8 / 20)
Number of Access Cycles
Address
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
ICLK
PCLK
ICLK <
PCLK
0008 7581h
ICU
Non-maskable interrupt enable register
NMIER
8
8
2 ICLK
0008 7582h
ICU
Non-maskable interrupt clear register
NMICLR
8
8
2 ICLK
0008 7583h
ICU
NMI pin interrupt control register
NMICR
8
8
2 ICLK
0008 7590h
ICU
NMI pin digital filter enable register
NMIFLTE
8
8
2 ICLK
0008 7594h
ICU
NMI pin digital filter setting register
NMIFLTC
8
8
0008 8000h
CMT
Compare match timer start register 0
CMSTR0
16
16
2, 3 PCLKB
2 ICLK
0008 8002h
CMT0
Compare match timer control register
CMCR
16
16
2, 3 PCLKB
2 ICLK
2 ICLK
2 ICLK
0008 8004h
CMT0
Compare match timer counter
CMCNT
16
16
2, 3 PCLKB
0008 8006h
CMT0
Compare match timer constant register
CMCOR
16
16
2, 3 PCLKB
2 ICLK
0008 8008h
CMT1
Compare match timer control register
CMCR
16
16
2, 3 PCLKB
2 ICLK
2 ICLK
0008 800Ah
CMT1
Compare match timer counter
CMCNT
16
16
2, 3 PCLKB
0008 800Ch
CMT1
Compare match timer constant register
CMCOR
16
16
2, 3 PCLKB
2 ICLK
0008 8010h
CMT
Compare match timer start register 1
CMSTR1
16
16
2, 3 PCLKB
2 ICLK
0008 8012h
CMT2
Compare match timer control register
CMCR
16
16
2, 3 PCLKB
2 ICLK
0008 8014h
CMT2
Compare match timer counter
CMCNT
16
16
2, 3 PCLKB
2 ICLK
0008 8016h
CMT2
Compare match timer constant register
CMCOR
16
16
2, 3 PCLKB
2 ICLK
0008 8018h
CMT3
Compare match timer control register
CMCR
16
16
2, 3 PCLKB
2 ICLK
2 ICLK
0008 801Ah
CMT3
Compare match timer counter
CMCNT
16
16
2, 3 PCLKB
0008 801Ch
CMT3
Compare match timer constant register
CMCOR
16
16
2, 3 PCLKB
2 ICLK
0008 8030h
IWDT
IWDT refresh register
IWDTRR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 8032h
IWDT
IWDT control register
IWDTCR
16
16
2, 3 PCLKB
0008 8034h
IWDT
IWDT status register
IWDTSR
16
16
2, 3 PCLKB
2 ICLK
0008 8036h
IWDT
IWDT reset control register
IWDTRCR
8
8
2, 3 PCLKB
2 ICLK
0008 8038h
IWDT
IWDT count stop control register
IWDTCSTPR
8
8
2, 3 PCLKB
2 ICLK
0008 8200h
TMR0
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8201h
TMR1
Timer counter control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8202h
TMR0
Timer control/status register
TCSR
8
8
2, 3 PCLKB
2 ICLK
0008 8203h
TMR1
Timer control/status register
TCSR
8
8
2, 3 PCLKB
2 ICLK
0008 8204h
TMR0
Time constant register A
TCORA
8
8
2, 3 PCLKB
2 ICLK
0008 8205h
TMR1
Time constant register A
TCORA
8
8*1
2, 3 PCLKB
2 ICLK
0008 8206h
TMR0
Time constant register B
TCORB
8
8
2, 3 PCLKB
2 ICLK
0008 8207h
TMR1
Time constant register B
TCORB
8
8*1
2, 3 PCLKB
2 ICLK
0008 8208h
TMR0
Timer counter
TCNT
8
8
2, 3 PCLKB
2 ICLK
0008 8209h
TMR1
Timer counter
TCNT
8
8*1
2, 3 PCLKB
2 ICLK
0008 820Ah
TMR0
Timer counter control register
TCCR
8
8
2, 3 PCLKB
2 ICLK
0008 820Bh
TMR1
Timer counter control register
TCCR
8
8*1
2, 3 PCLKB
2 ICLK
0008 820Ch
TMR0
Time count start register
TCSTR
8
8
2, 3 PCLKB
2 ICLK
0008 8210h
TMR2
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8211h
TMR3
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8212h
TMR2
Timer control/status register
TCSR
8
8
2, 3 PCLKB
2 ICLK
0008 8213h
TMR3
Timer control/status register
TCSR
8
8
2, 3 PCLKB
2 ICLK
0008 8214h
TMR2
Time constant register A
TCORA
8
8
2, 3 PCLKB
2 ICLK
0008 8215h
TMR3
Time constant register A
TCORA
8
8*1
2, 3 PCLKB
2 ICLK
0008 8216h
TMR2
Time constant register B
TCORB
8
8
2, 3 PCLKB
2 ICLK
0008 8217h
TMR3
Time constant register B
TCORB
8
8*1
2, 3 PCLKB
2 ICLK
0008 8218h
TMR2
Timer counter
TCNT
8
8
2, 3 PCLKB
2 ICLK
0008 8219h
TMR3
Timer counter
TCNT
8
8*1
2, 3 PCLKB
2 ICLK
0008 821Ah
TMR2
Timer counter control register
TCCR
8
8
2, 3 PCLKB
2 ICLK
0008 821Bh
TMR3
Timer counter control register
TCCR
8
8*1
2, 3 PCLKB
2 ICLK
0008 821Ch
TMR2
Time count start register
TCSTR
8
8
2, 3 PCLKB
2 ICLK
0008 8280h
CRC
CRC control register
CRCCR
8
8
2, 3 PCLKB
2 ICLK
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 34 of 105
RX220 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (9 / 20)
Number of Access Cycles
Number
of Bits
Access
Size
ICLK
PCLK
Address
Module
Symbol
Register Name
Register
Symbol
ICLK <
PCLK
0008 8281h
CRC
CRC data input register
CRCDIR
8
8
2, 3 PCLKB
0008 8282h
CRC
CRC data output register
CRCDOR
16
16
2, 3 PCLKB
2 ICLK
0008 8300h
RIIC0
I2C bus control register 1
ICCR1
8
8
2, 3 PCLKB
2 ICLK
0008 8301h
RIIC0
I2C bus control register 2
ICCR2
8
8
2, 3 PCLKB
2 ICLK
0008 8302h
RIIC0
I2C bus mode register 1
ICMR1
8
8
2, 3 PCLKB
2 ICLK
0008 8303h
RIIC0
I2C bus mode register 2
ICMR2
8
8
2, 3 PCLKB
2 ICLK
0008 8304h
RIIC0
I2C bus mode register 3
ICMR3
8
8
2, 3 PCLKB
2 ICLK
0008 8305h
RIIC0
I2C bus function enable register
ICFER
8
8
2, 3 PCLKB
2 ICLK
0008 8306h
RIIC0
I2C bus status enable register
ICSER
8
8
2, 3 PCLKB
2 ICLK
0008 8307h
RIIC0
I2C bus interrupt enable register
ICIER
8
8
2, 3 PCLKB
2 ICLK
0008 8308h
RIIC0
I2C bus status register 1
ICSR1
8
8
2, 3 PCLKB
2 ICLK
0008 8309h
RIIC0
I2C bus status register 2
ICSR2
8
8
2, 3 PCLKB
2 ICLK
0008 830Ah
RIIC0
Slave address register L0
SARL0
8
8
2, 3 PCLKB
2 ICLK
0008 830Ah
RIIC0
Timeout internal counter L
TMOCNTL
8
8
2, 3 PCLKB
2 ICLK
0008 830Bh
RIIC0
Slave address register U0
SARU0
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 830Bh
RIIC0
Timeout internal counter U
TMOCNTU
8
8*2
2, 3 PCLKB
2 ICLK
0008 830Ch
RIIC0
Slave address register L1
SARL1
8
8
2, 3 PCLKB
2 ICLK
0008 830Dh
RIIC0
Slave address register U1
SARU1
8
8
2, 3 PCLKB
2 ICLK
0008 830Eh
RIIC0
Slave address register L2
SARL2
8
8
2, 3 PCLKB
2 ICLK
0008 830Fh
RIIC0
Slave address register U2
SARU2
8
8
2, 3 PCLKB
2 ICLK
0008 8310h
RIIC0
I2C bus bit rate low-level register
ICBRL
8
8
2, 3 PCLKB
2 ICLK
0008 8311h
RIIC0
I2C bus bit rate high-level register
ICBRH
8
8
2, 3 PCLKB
2 ICLK
0008 8312h
RIIC0
I2C bus transmit data register
ICDRT
8
8
2, 3 PCLKB
2 ICLK
0008 8313h
RIIC0
I2 C
ICDRR
8
8
2, 3 PCLKB
2 ICLK
0008 8380h
RSPI0
RSPI control register
SPCR
8
8
2, 3 PCLKB
2 ICLK
0008 8381h
RSPI0
RSPI slave select polarity register
SSLP
8
8
2, 3 PCLKB
2 ICLK
0008 8382h
RSPI0
RSPI pin control register
SPPCR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
bus receive data register
0008 8383h
RSPI0
RSPI status register
SPSR
8
8
2, 3 PCLKB
0008 8384h
RSPI0
RSPI data register
SPDR
32
16, 32
2, 3 PCLKB
2 ICLK
0008 8388h
RSPI0
RSPI sequence control register
SPSCR
8
8
2, 3 PCLKB
2 ICLK
0008 8389h
RSPI0
RSPI sequence status register
SPSSR
8
8
2, 3 PCLKB
2 ICLK
0008 838Ah
RSPI0
RSPI bit rate register
SPBR
8
8
2, 3 PCLKB
2 ICLK
0008 838Bh
RSPI0
RSPI data control register
SPDCR
8
8
2, 3 PCLKB
2 ICLK
0008 838Ch
RSPI0
RSPI clock delay register
SPCKD
8
8
2, 3 PCLKB
2 ICLK
0008 838Dh
RSPI0
RSPI slave select negation delay register
SSLND
8
8
2, 3 PCLKB
2 ICLK
0008 838Eh
RSPI0
RSPI next-access delay register
SPND
8
8
2, 3 PCLKB
2 ICLK
0008 838Fh
RSPI0
RSPI control register 2
SPCR2
8
8
2, 3 PCLKB
2 ICLK
0008 8390h
RSPI0
RSPI command register 0
SPCMD0
16
16
2, 3 PCLKB
2 ICLK
0008 8392h
RSPI0
RSPI command register 1
SPCMD1
16
16
2, 3 PCLKB
2 ICLK
0008 8394h
RSPI0
RSPI command register 2
SPCMD2
16
16
2, 3 PCLKB
2 ICLK
0008 8396h
RSPI0
RSPI command register 3
SPCMD3
16
16
2, 3 PCLKB
2 ICLK
0008 8398h
RSPI0
RSPI command register 4
SPCMD4
16
16
2, 3 PCLKB
2 ICLK
0008 839Ah
RSPI0
RSPI command register 5
SPCMD5
16
16
2, 3 PCLKB
2 ICLK
0008 839Ch
RSPI0
RSPI command register 6
SPCMD6
16
16
2, 3 PCLKB
2 ICLK
0008 839Eh
RSPI0
RSPI command register 7
SPCMD7
16
16
2, 3 PCLKB
2 ICLK
0008 8410h
IRDA
IrDA control register
IRCR
8
8
2, 3 PCLKB
2 ICLK
0008 8600h
MTU3
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8601h
MTU4
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8602h
MTU3
Timer mode register
TMDR
8
8
2, 3 PCLKB
2 ICLK
0008 8603h
MTU4
Timer mode register
TMDR
8
8
2, 3 PCLKB
2 ICLK
0008 8604h
MTU3
Timer I/O control register H
TIORH
8
8
2, 3 PCLKB
2 ICLK
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 35 of 105
RX220 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (10 / 20)
Number of Access Cycles
Address
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
ICLK
PCLK
ICLK <
PCLK
0008 8605h
MTU3
Timer I/O control register L
TIORL
8
8
2, 3 PCLKB
2 ICLK
0008 8606h
MTU4
Timer I/O control register H
TIORH
8
8
2, 3 PCLKB
2 ICLK
0008 8607h
MTU4
Timer I/O control register L
TIORL
8
8
2, 3 PCLKB
2 ICLK
0008 8608h
MTU3
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
0008 8609h
MTU4
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
0008 860Ah
MTU
Timer output master enable register
TOER
8
8
2, 3 PCLKB
2 ICLK
0008 860Dh
MTU
Timer gate control register
TGCR
8
8
2, 3 PCLKB
2 ICLK
0008 860Eh
MTU
Timer output control register 1
TOCR1
8
8
2, 3 PCLKB
2 ICLK
0008 860Fh
MTU
Timer output control register 2
TOCR2
8
8
2, 3 PCLKB
2 ICLK
0008 8610h
MTU3
Timer counter
TCNT
16
16
2, 3 PCLKB
2 ICLK
2 ICLK
0008 8612h
MTU4
Timer counter
TCNT
16
16
2, 3 PCLKB
0008 8614h
MTU
Timer cycle data register
TCDR
16
16
2, 3 PCLKB
2 ICLK
0008 8616h
MTU
Timer dead time data register
TDDR
16
16
2, 3 PCLKB
2 ICLK
0008 8618h
MTU3
Timer general register A
TGRA
16
16
2, 3 PCLKB
2 ICLK
0008 861Ah
MTU3
Timer general register B
TGRB
16
16
2, 3 PCLKB
2 ICLK
0008 861Ch
MTU4
Timer general register A
TGRA
16
16
2, 3 PCLKB
2 ICLK
0008 861Eh
MTU4
Timer general register B
TGRB
16
16
2, 3 PCLKB
2 ICLK
0008 8620h
MTU
Timer subcounter
TCNTS
16
16
2, 3 PCLKB
2 ICLK
0008 8622h
MTU
Timer cycle buffer register
TCBR
16
16
2, 3 PCLKB
2 ICLK
2 ICLK
0008 8624h
MTU3
Timer general register C
TGRC
16
16
2, 3 PCLKB
0008 8626h
MTU3
Timer general register D
TGRD
16
16
2, 3 PCLKB
2 ICLK
0008 8628h
MTU4
Timer general register C
TGRC
16
16
2, 3 PCLKB
2 ICLK
0008 862Ah
MTU4
Timer general register D
TGRD
16
16
2, 3 PCLKB
2 ICLK
0008 862Ch
MTU3
Timer status register
TSR
8
8
2, 3 PCLKB
2 ICLK
0008 862Dh
MTU4
Timer status register
TSR
8
8
2, 3 PCLKB
2 ICLK
0008 8630h
MTU
Timer interrupt skipping set register
TITCR
8
8
2, 3 PCLKB
2 ICLK
0008 8631h
MTU
Timer interrupt skipping counter
TITCNT
8
8
2, 3 PCLKB
2 ICLK
0008 8632h
MTU
Timer buffer transfer set register
TBTER
8
8
2, 3 PCLKB
2 ICLK
0008 8634h
MTU
Timer dead time enable register
TDER
8
8
2, 3 PCLKB
2 ICLK
0008 8636h
MTU
Timer output level buffer register
TOLBR
8
8
2, 3 PCLKB
2 ICLK
0008 8638h
MTU3
Timer buffer operation transfer mode register
TBTM
8
8
2, 3 PCLKB
2 ICLK
0008 8639h
MTU4
Timer buffer operation transfer mode register
TBTM
8
8
2, 3 PCLKB
2 ICLK
0008 8640h
MTU4
Timer A/D converter start request control register
TADCR
16
16
2, 3 PCLKB
2 ICLK
0008 8644h
MTU4
Timer A/D converter start request cycle set register A
TADCORA
16
16
2, 3 PCLKB
2 ICLK
0008 8646h
MTU4
Timer A/D converter start request cycle set register B
TADCORB
16
16
2, 3 PCLKB
2 ICLK
0008 8648h
MTU4
Timer A/D converter start request cycle set buffer register A
TADCOBRA
16
16
2, 3 PCLKB
2 ICLK
0008 864Ah
MTU4
Timer A/D converter start request cycle set buffer register B
TADCOBRB
16
16
2, 3 PCLKB
2 ICLK
2 ICLK
0008 8660h
MTU
Timer waveform control register
TWCR
8
8, 16
2, 3 PCLKB
0008 8680h
MTU
Timer start register
TSTR
8
8, 16
2, 3 PCLKB
2 ICLK
0008 8681h
MTU
Timer synchronous register
TSYR
8
8, 16
2, 3 PCLKB
2 ICLK
0008 8684h
MTU
Timer read/write enable register
TRWER
8
8, 16
2, 3 PCLKB
2 ICLK
0008 8690h
MTU0
Noise filter control register
NFCR
8
8, 16
2, 3 PCLKB
2 ICLK
0008 8691h
MTU1
Noise filter control register
NFCR
8
8, 16
2, 3 PCLKB
2 ICLK
0008 8692h
MTU2
Noise filter control register
NFCR
8
8, 16
2, 3 PCLKB
2 ICLK
0008 8693h
MTU3
Noise filter control register
NFCR
8
8, 16
2, 3 PCLKB
2 ICLK
0008 8694h
MTU4
Noise filter control register
NFCR
8
8, 16
2, 3 PCLKB
2 ICLK
0008 8695h
MTU5
Noise filter control register
NFCR
8
8, 16
2, 3 PCLKB
2 ICLK
0008 8700h
MTU0
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8701h
MTU0
Timer mode register
TMDR
8
8
2, 3 PCLKB
2 ICLK
0008 8702h
MTU0
Timer I/O control register H
TIORH
8
8
2, 3 PCLKB
2 ICLK
0008 8703h
MTU0
Timer I/O control register L
TIORL
8
8
2, 3 PCLKB
2 ICLK
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 36 of 105
RX220 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (11 / 20)
Number of Access Cycles
Address
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
ICLK
PCLK
ICLK <
PCLK
0008 8704h
MTU0
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
0008 8705h
MTU0
Timer status register
TSR
8
8
2, 3 PCLKB
2 ICLK
0008 8706h
MTU0
Timer counter
TCNT
16
16
2, 3 PCLKB
2 ICLK
0008 8708h
MTU0
Timer general register A
TGRA
16
16
2, 3 PCLKB
2 ICLK
0008 870Ah
MTU0
Timer general register B
TGRB
16
16
2, 3 PCLKB
2 ICLK
2 ICLK
0008 870Ch
MTU0
Timer general register C
TGRC
16
16
2, 3 PCLKB
0008 870Eh
MTU0
Timer general register D
TGRD
16
16
2, 3 PCLKB
2 ICLK
0008 8720h
MTU0
Timer general register E
TGRE
16
16
2, 3 PCLKB
2 ICLK
0008 8722h
MTU0
Timer general register F
TGRF
16
16
2, 3 PCLKB
2 ICLK
0008 8724h
MTU0
Timer interrupt enable register 2
TIER2
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 8726h
MTU0
Timer buffer operation transfer mode register
TBTM
8
8
2, 3 PCLKB
0008 8780h
MTU1
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8781h
MTU1
Timer mode register
TMDR
8
8
2, 3 PCLKB
2 ICLK
0008 8782h
MTU1
Timer I/O control register
TIOR
8
8
2, 3 PCLKB
2 ICLK
0008 8784h
MTU1
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
0008 8785h
MTU1
Timer status register
TSR
8
8
2, 3 PCLKB
2 ICLK
0008 8786h
MTU1
Timer counter
TCNT
16
16
2, 3 PCLKB
2 ICLK
0008 8788h
MTU1
Timer general register A
TGRA
16
16
2, 3 PCLKB
2 ICLK
0008 878Ah
MTU1
Timer general register B
TGRB
16
16
2, 3 PCLKB
2 ICLK
2 ICLK
0008 8790h
MTU1
Timer input capture control register
TICCR
8
8
2, 3 PCLKB
0008 8800h
MTU2
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8801h
MTU2
Timer mode register
TMDR
8
8
2, 3 PCLKB
2 ICLK
0008 8802h
MTU2
Timer I/O control register
TIOR
8
8
2, 3 PCLKB
2 ICLK
0008 8804h
MTU2
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
0008 8805h
MTU2
Timer status register
TSR
8
8
2, 3 PCLKB
2 ICLK
0008 8806h
MTU2
Timer counter
TCNT
16
16
2, 3 PCLKB
2 ICLK
0008 8808h
MTU2
Timer general register A
TGRA
16
16
2, 3 PCLKB
2 ICLK
0008 880Ah
MTU2
Timer general register B
TGRB
16
16
2, 3 PCLKB
2 ICLK
0008 8880h
MTU5
Timer counter U
TCNTU
16
16
2, 3 PCLKB
2 ICLK
0008 8882h
MTU5
Timer general register U
TGRU
16
16
2, 3 PCLKB
2 ICLK
0008 8884h
MTU5
Timer control register U
TCRU
8
8
2, 3 PCLKB
2 ICLK
0008 8886h
MTU5
Timer I/O control register U
TIORU
8
8
2, 3 PCLKB
2 ICLK
0008 8890h
MTU5
Timer counter V
TCNTV
16
16
2, 3 PCLKB
2 ICLK
0008 8892h
MTU5
Timer general register V
TGRV
16
16
2, 3 PCLKB
2 ICLK
0008 8894h
MTU5
Timer control register V
TCRV
8
8
2, 3 PCLKB
2 ICLK
0008 8896h
MTU5
Timer I/O control register V
TIORV
8
8
2, 3 PCLKB
2 ICLK
0008 88A0h
MTU5
Timer counter W
TCNTW
16
16
2, 3 PCLKB
2 ICLK
0008 88A2h
MTU5
Timer general register W
TGRW
16
16
2, 3 PCLKB
2 ICLK
0008 88A4h
MTU5
Timer control register W
TCRW
8
8
2, 3 PCLKB
2 ICLK
0008 88A6h
MTU5
Timer I/O control register W
TIORW
8
8
2, 3 PCLKB
2 ICLK
0008 88B2h
MTU5
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
0008 88B4h
MTU5
Timer start register
TSTR
8
8
2, 3 PCLKB
2 ICLK
0008 88B6h
MTU5
Timer compare match clear register
TCNTCMPCLR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 8900h
POE
Input level control/status register 1
ICSR1
16
8, 16
2, 3 PCLKB
0008 8902h
POE
Output level control/status register 1
OCSR1
16
8, 16
2, 3 PCLKB
2 ICLK
0008 8908h
POE
Input level control/status register 2
ICSR2
16
8, 16
2, 3 PCLKB
2 ICLK
0008 890Ah
POE
Software port output enable register
SPOER
8
8
2, 3 PCLKB
2 ICLK
0008 890Bh
POE
Port output enable control register 1
POECR1
8
8
2, 3 PCLKB
2 ICLK
0008 890Ch
POE
Port output enable control register 2
POECR2
8
8
2, 3 PCLKB
2 ICLK
0008 890Eh
POE
Input level control/status register 3
ICSR3
16
8, 16
2, 3 PCLKB
2 ICLK
0008 9000h
S12AD
A/D control register
ADCSR
16
16
2, 3 PCLKB
2 ICLK
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 37 of 105
RX220 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (12 / 20)
Number of Access Cycles
Address
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
ICLK
PCLK
ICLK <
PCLK
0008 9004h
S12AD
A/D channel select register A
ADANSA
16
16
2, 3 PCLKB
0008 9008h
S12AD
A/D-converted value addition mode select register
ADADS
16
16
2, 3 PCLKB
2 ICLK
2 ICLK
0008 900Ch
S12AD
A/D-converted value addition count select register
ADADC
8
8
2, 3 PCLKB
2 ICLK
0008 900Eh
S12AD
A/D control extended register
ADCER
16
16
2, 3 PCLKB
2 ICLK
0008 9010h
S12AD
A/D start trigger select register
ADSTRGR
16
16
2, 3 PCLKB
2 ICLK
0008 9012h
S12AD
A/D converted extended input control register
ADEXICR
16
16
2, 3 PCLKB
2 ICLK
0008 9014h
S12AD
A/D channel select register B
ADANSB
16
16
2, 3 PCLKB
2 ICLK
0008 9018h
S12AD
A/D double register
ADDBLDR
16
16
2, 3 PCLKB
2 ICLK
0008 901Ch
S12AD
A/D internal reference voltage data register
ADOCDR
16
16
2, 3 PCLKB
2 ICLK
0008 901Eh
S12AD
A/D self-diagnosis data register
ADRD
16
16
2, 3 PCLKB
2 ICLK
0008 9020h
S12AD
A/D data register 0
ADDR0
16
16
2, 3 PCLKB
2 ICLK
0008 9022h
S12AD
A/D data register 1
ADDR1
16
16
2, 3 PCLKB
2 ICLK
0008 9024h
S12AD
A/D data register 2
ADDR2
16
16
2, 3 PCLKB
2 ICLK
0008 9026h
S12AD
A/D data register 3
ADDR3
16
16
2, 3 PCLKB
2 ICLK
2 ICLK
0008 9028h
S12AD
A/D data register 4
ADDR4
16
16
2, 3 PCLKB
0008 902Ah
S12AD
A/D data register 5
ADDR5
16
16
2, 3 PCLKB
2 ICLK
0008 902Ch
S12AD
A/D data register 6
ADDR6
16
16
2, 3 PCLKB
2 ICLK
0008 902Eh
S12AD
A/D data register 7
ADDR7
16
16
2, 3 PCLKB
2 ICLK
0008 9030h
S12AD
A/D data register 8
ADDR8
16
16
2, 3 PCLKB
2 ICLK
2 ICLK
0008 9032h
S12AD
A/D data register 9
ADDR9
16
16
2, 3 PCLKB
0008 9034h
S12AD
A/D data register 10
ADDR10
16
16
2, 3 PCLKB
2 ICLK
0008 9036h
S12AD
A/D data register 11
ADDR11
16
16
2, 3 PCLKB
2 ICLK
0008 9038h
S12AD
A/D data register 12
ADDR12
16
16
2, 3 PCLKB
2 ICLK
0008 903Ah
S12AD
A/D data register 13
ADDR13
16
16
2, 3 PCLKB
2 ICLK
0008 903Ch
S12AD
A/D data register 14
ADDR14
16
16
2, 3 PCLKB
2 ICLK
0008 903Eh
S12AD
A/D data register 15
ADDR15
16
16
2, 3 PCLKB
2 ICLK
0008 9060h
S12AD
A/D sampling state register 0
ADSSTR0
8
8
2, 3 PCLKB
2 ICLK
0008 9061h
S12AD
A/D sampling state register L
ADSSTRL
8
8
2, 3 PCLKB
2 ICLK
0008 9071h
S12AD
A/D sampling state register O
ADSSTRO
8
8
2, 3 PCLKB
2 ICLK
0008 9073h
S12AD
A/D sampling state register 1
ADSSTR1
8
8
2, 3 PCLKB
2 ICLK
0008 9074h
S12AD
A/D sampling state register 2
ADSSTR2
8
8
2, 3 PCLKB
2 ICLK
0008 9075h
S12AD
A/D sampling state register 3
ADSSTR3
8
8
2, 3 PCLKB
2 ICLK
0008 9076h
S12AD
A/D sampling state register 4
ADSSTR4
8
8
2, 3 PCLKB
2 ICLK
0008 9077h
S12AD
A/D sampling state register 5
ADSSTR5
8
8
2, 3 PCLKB
2 ICLK
0008 9078h
S12AD
A/D sampling state register 6
ADSSTR6
8
8
2, 3 PCLKB
2 ICLK
0008 9079h
S12AD
A/D sampling state register 7
ADSSTR7
8
8
2, 3 PCLKB
2 ICLK
0008 907Ah
S12AD
A/D disconnecting detection control register
ADDISCR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 A020h
SCI1
Serial mode register
SMR
8
8
2, 3 PCLKB
0008 A021h
SCI1
Bit rate register
BRR
8
8
2, 3 PCLKB
2 ICLK
0008 A022h
SCI1
Serial control register
SCR
8
8
2, 3 PCLKB
2 ICLK
0008 A023h
SCI1
Transmit data register
TDR
8
8
2, 3 PCLKB
2 ICLK
0008 A024h
SCI1
Serial status register
SSR
8
8
2, 3 PCLKB
2 ICLK
0008 A025h
SCI1
Receive data register
RDR
8
8
2, 3 PCLKB
2 ICLK
0008 A026h
SCI1
Smart card mode register
SCMR
8
8
2, 3 PCLKB
2 ICLK
0008 A027h
SCI1
Serial extended mode register
SEMR
8
8
2, 3 PCLKB
2 ICLK
0008 A028h
SCI1
Noise filter setting register
SNFR
8
8
2, 3 PCLKB
2 ICLK
0008 A029h
SCI1
I2C mode register 1
SIMR1
8
8
2, 3 PCLKB
2 ICLK
0008 A02Ah
SCI1
I2C mode register 2
SIMR2
8
8
2, 3 PCLKB
2 ICLK
0008 A02Bh
SCI1
I2C mode register 3
SIMR3
8
8
2, 3 PCLKB
2 ICLK
0008 A02Ch
SCI1
I2C status register
SISR
8
8
2, 3 PCLKB
2 ICLK
0008 A02Dh
SCI1
SPI mode register
SPMR
8
8
2, 3 PCLKB
2 ICLK
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 38 of 105
RX220 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (13 / 20)
Number of Access Cycles
ICLK
PCLK
Address
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
ICLK <
PCLK
0008 A0A0h
SCI5
Serial mode register
0008 A0A1h
SCI5
Bit rate register
SMR
8
8
2, 3 PCLKB
BRR
8
8
2, 3 PCLKB
0008 A0A2h
SCI5
Serial control register
2 ICLK
SCR
8
8
2, 3 PCLKB
2 ICLK
0008 A0A3h
SCI5
Transmit data register
TDR
8
8
2, 3 PCLKB
2 ICLK
0008 A0A4h
SCI5
Serial status register
SSR
8
8
2, 3 PCLKB
2 ICLK
0008 A0A5h
SCI5
Receive data register
RDR
8
8
2, 3 PCLKB
2 ICLK
0008 A0A6h
SCI5
Smart card mode register
SCMR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 A0A7h
SCI5
Serial extended mode register
SEMR
8
8
2, 3 PCLKB
2 ICLK
0008 A0A8h
SCI5
Noise filter setting register
SNFR
8
8
2, 3 PCLKB
2 ICLK
0008 A0A9h
SCI5
I2C mode register 1
SIMR1
8
8
2, 3 PCLKB
2 ICLK
0008 A0AAh
SCI5
I2 C
mode register 2
SIMR2
8
8
2, 3 PCLKB
2 ICLK
0008 A0ABh
SCI5
I2C mode register 3
SIMR3
8
8
2, 3 PCLKB
2 ICLK
0008 A0ACh
SCI5
I2C status register
SISR
8
8
2, 3 PCLKB
2 ICLK
0008 A0ADh
SCI5
SPI mode register
SPMR
8
8
2, 3 PCLKB
2 ICLK
0008 A0C0h
SCI6
Serial mode register
SMR
8
8
2, 3 PCLKB
2 ICLK
0008 A0C1h
SCI6
Bit rate register
BRR
8
8
2, 3 PCLKB
2 ICLK
0008 A0C2h
SCI6
Serial control register
SCR
8
8
2, 3 PCLKB
2 ICLK
0008 A0C3h
SCI6
Transmit data register
TDR
8
8
2, 3 PCLKB
2 ICLK
0008 A0C4h
SCI6
Serial status register
SSR
8
8
2, 3 PCLKB
2 ICLK
0008 A0C5h
SCI6
Receive data register
RDR
8
8
2, 3 PCLKB
2 ICLK
0008 A0C6h
SCI6
Smart card mode register
SCMR
8
8
2, 3 PCLKB
2 ICLK
0008 A0C7h
SCI6
Serial extended mode register
SEMR
8
8
2, 3 PCLKB
2 ICLK
0008 A0C8h
SCI6
Noise filter setting register
SNFR
8
8
2, 3 PCLKB
2 ICLK
0008 A0C9h
SCI6
I2 C
mode register 1
SIMR1
8
8
2, 3 PCLKB
2 ICLK
0008 A0CAh
SCI6
I2C mode register 2
SIMR2
8
8
2, 3 PCLKB
2 ICLK
0008 A0CBh
SCI6
I2C mode register 3
SIMR3
8
8
2, 3 PCLKB
2 ICLK
0008 A0CCh
SCI6
I2C status register
SISR
8
8
2, 3 PCLKB
2 ICLK
0008 A0CDh
SCI6
SPI mode register
SPMR
8
8
2, 3 PCLKB
2 ICLK
0008 A120h
SCI9
Serial mode register
SMR
8
8
2, 3 PCLKB
2 ICLK
0008 A121h
SCI9
Bit rate register
BRR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 A122h
SCI9
Serial control register
SCR
8
8
2, 3 PCLKB
0008 A123h
SCI9
Transmit data register
TDR
8
8
2, 3 PCLKB
2 ICLK
0008 A124h
SCI9
Serial status register
SSR
8
8
2, 3 PCLKB
2 ICLK
0008 A125h
SCI9
Receive data register
RDR
8
8
2, 3 PCLKB
2 ICLK
0008 A126h
SCI9
Smart card mode register
SCMR
8
8
2, 3 PCLKB
2 ICLK
0008 A127h
SCI9
Serial extended mode register
SEMR
8
8
2, 3 PCLKB
2 ICLK
0008 A128h
SCI9
Noise filter setting register
SNFR
8
8
2, 3 PCLKB
2 ICLK
0008 A129h
SCI9
I2 C
mode register 1
SIMR1
8
8
2, 3 PCLKB
2 ICLK
0008 A12Ah
SCI9
I2C mode register 2
SIMR2
8
8
2, 3 PCLKB
2 ICLK
0008 A12Bh
SCI9
I2C mode register 3
SIMR3
8
8
2, 3 PCLKB
2 ICLK
0008 A12Ch
SCI9
I2C status register
SISR
8
8
2, 3 PCLKB
2 ICLK
0008 A12Dh
SCI9
SPI mode register
SPMR
8
8
2, 3 PCLKB
2 ICLK
0008 B000h
CAC
CAC control register 0
CACR0
8
8
2, 3 PCLKB
2 ICLK
0008 B001h
CAC
CAC control register 1
CACR1
8
8
2, 3 PCLKB
2 ICLK
0008 B002h
CAC
CAC control register 2
CACR2
8
8
2, 3 PCLKB
2 ICLK
0008 B003h
CAC
CAC interrupt control register
CAICR
8
8
2, 3 PCLKB
2 ICLK
0008 B004h
CAC
CAC status register
CASTR
8
8
2, 3 PCLKB
2 ICLK
0008 B006h
CAC
CAC upper-limit value setting register
CAULVR
16
16
2, 3 PCLKB
2 ICLK
0008 B008h
CAC
CAC lower-limit value setting register
CALLVR
16
16
2, 3 PCLKB
2 ICLK
0008 B00Ah
CAC
CAC counter buffer register
CACNTBR
16
16
2, 3 PCLKB
2 ICLK
0008 B080h
DOC
DOC control register
DOCR
8
8
2, 3 PCLKB
2 ICLK
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 39 of 105
RX220 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (14 / 20)
Number of Access Cycles
Address
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
ICLK
PCLK
ICLK <
PCLK
0008 B082h
DOC
DOC data input register
DODIR
16
16
2, 3 PCLKB
0008 B084h
DOC
DOC data setting register
DODSR
16
16
2, 3 PCLKB
2 ICLK
2 ICLK
0008 B100h
ELC
Event link control register
ELCR
8
8
2, 3 PCLKB
2 ICLK
0008 B102h
ELC
Event link setting register 1
ELSR1
8
8
2, 3 PCLKB
2 ICLK
0008 B103h
ELC
Event link setting register 2
ELSR2
8
8
2, 3 PCLKB
2 ICLK
0008 B104h
ELC
Event link setting register 3
ELSR3
8
8
2, 3 PCLKB
2 ICLK
0008 B105h
ELC
Event link setting register 4
ELSR4
8
8
2, 3 PCLKB
2 ICLK
0008 B10Bh
ELC
Event link setting register 10
ELSR10
8
8
2, 3 PCLKB
2 ICLK
0008 B10Dh
ELC
Event link setting register 12
ELSR12
8
8
2, 3 PCLKB
2 ICLK
0008 B110h
ELC
Event link setting register 15
ELSR15
8
8
2, 3 PCLKB
2 ICLK
0008 B113h
ELC
Event link setting register 18
ELSR18
8
8
2, 3 PCLKB
2 ICLK
0008 B115h
ELC
Event link setting register 20
ELSR20
8
8
2, 3 PCLKB
2 ICLK
0008 B117h
ELC
Event link setting register 22
ELSR22
8
8
2, 3 PCLKB
2 ICLK
0008 B119h
ELC
Event link setting register 24
ELSR24
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 B11Ah
ELC
Event link setting register 25
ELSR25
8
8
2, 3 PCLKB
0008 B11Fh
ELC
Event link option setting register A
ELOPA
8
8
2, 3 PCLKB
2 ICLK
0008 B120h
ELC
Event link option setting register B
ELOPB
8
8
2, 3 PCLKB
2 ICLK
0008 B122h
ELC
Event link option setting register D
ELOPD
8
8
2, 3 PCLKB
2 ICLK
0008 B123h
ELC
Port group setting register 1
PGR1
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 B125h
ELC
Port group control register 1
PGC1
8
8
2, 3 PCLKB
0008 B127h
ELC
Port buffer register 1
PDBF1
8
8
2, 3 PCLKB
2 ICLK
0008 B129h
ELC
Event link port setting register 0
PEL0
8
8
2, 3 PCLKB
2 ICLK
0008 B12Ah
ELC
Event link port setting register 1
PEL1
8
8
2, 3 PCLKB
2 ICLK
0008 B12Dh
ELC
Event link software event generation register
ELSEGR
8
8
2, 3 PCLKB
2 ICLK
0008 B300h
SCI12
Serial mode register
SMR
8
8
2, 3 PCLKB
2 ICLK
0008 B301h
SCI12
Bit rate register
BRR
8
8
2, 3 PCLKB
2 ICLK
0008 B302h
SCI12
Serial control register
SCR
8
8
2, 3 PCLKB
2 ICLK
0008 B303h
SCI12
Transmit data register
TDR
8
8
2, 3 PCLKB
2 ICLK
0008 B304h
SCI12
Serial status register
SSR
8
8
2, 3 PCLKB
2 ICLK
0008 B305h
SCI12
Receive data register
RDR
8
8
2, 3 PCLKB
2 ICLK
0008 B306h
SCI12
Smart card mode register
SCMR
8
8
2, 3 PCLKB
2 ICLK
0008 B307h
SCI12
Serial extended mode register
SEMR
8
8
2, 3 PCLKB
2 ICLK
0008 B308h
SCI12
Noise filter setting register
SNFR
8
8
2, 3 PCLKB
2 ICLK
0008 B309h
SCI12
I2C mode register 1
SIMR1
8
8
2, 3 PCLKB
2 ICLK
0008 B30Ah
SCI12
I2C mode register 2
SIMR2
8
8
2, 3 PCLKB
2 ICLK
0008 B30Bh
SCI12
I2C mode register 3
SIMR3
8
8
2, 3 PCLKB
2 ICLK
0008 B30Ch
SCI12
I2C status register
SISR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 B30Dh
SCI12
SPI mode register
SPMR
8
8
2, 3 PCLKB
0008 B320h
SCI12
Extended serial mode enable register
ESMER
8
8
2, 3 PCLKB
2 ICLK
0008 B321h
SCI12
Control register 0
CR0
8
8
2, 3 PCLKB
2 ICLK
0008 B322h
SCI12
Control register 1
CR1
8
8
2, 3 PCLKB
2 ICLK
0008 B323h
SCI12
Control register 2
CR2
8
8
2, 3 PCLKB
2 ICLK
0008 B324h
SCI12
Control register 3
CR3
8
8
2, 3 PCLKB
2 ICLK
0008 B325h
SCI12
Port control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 B326h
SCI12
Interrupt control register
ICR
8
8
2, 3 PCLKB
2 ICLK
0008 B327h
SCI12
Status register
STR
8
8
2, 3 PCLKB
2 ICLK
0008 B328h
SCI12
Status clear register
STCR
8
8
2, 3 PCLKB
2 ICLK
0008 B329h
SCI12
Control Field 0 data register
CF0DR
8
8
2, 3 PCLKB
2 ICLK
0008 B32Ah
SCI12
Control Field 0 compare enable register
CF0CR
8
8
2, 3 PCLKB
2 ICLK
0008 B32Bh
SCI12
Control Field 0 receive data register
CF0RR
8
8
2, 3 PCLKB
2 ICLK
0008 B32Ch
SCI12
Primary control field 1 data register
PCF1DR
8
8
2, 3 PCLKB
2 ICLK
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 40 of 105
RX220 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (15 / 20)
Number of Access Cycles
Register
Symbol
Number
of Bits
Access
Size
ICLK
PCLK
Address
Module
Symbol
Register Name
ICLK <
PCLK
0008 B32Dh
SCI12
Secondary control field 1 data register
SCF1DR
8
8
2, 3 PCLKB
2 ICLK
0008 B32Eh
SCI12
Control field 1 compare enable register
CF1CR
8
8
2, 3 PCLKB
2 ICLK
0008 B32Fh
SCI12
Control field 1 receive data register
CF1RR
8
8
2, 3 PCLKB
2 ICLK
0008 B330h
SCI12
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 B331h
SCI12
Timer mode register
TMR
8
8
2, 3 PCLKB
2 ICLK
0008 B332h
SCI12
Timer prescaler register
TPRE
8
8
2, 3 PCLKB
2 ICLK
0008 B333h
SCI12
Timer count register
TCNT
8
8
2, 3 PCLKB
2 ICLK
0008 C000h
PORT0
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C001h
PORT1
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C002h
PORT2
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C003h
PORT3
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C004h
PORT4
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 C005h
PORT5
Port direction register
PDR
8
8
2, 3 PCLKB
0008 C00Ah
PORTA
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C00Bh
PORTB
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C00Ch
PORTC
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C00Dh
PORTD
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C00Eh
PORTE
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C011h
PORTH
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C012h
PORTJ
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C020h
PORT0
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C021h
PORT1
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C022h
PORT2
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C023h
PORT3
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C024h
PORT4
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C025h
PORT5
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C02Ah
PORTA
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C02Bh
PORTB
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C02Ch
PORTC
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C02Dh
PORTD
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C02Eh
PORTE
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C031h
PORTH
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C032h
PORTJ
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C040h
PORT0
Port input data register
PIDR
8
8
3 or 4
PCLKB
cycles when
reading,
2 or 3
PCLKB
cycles when
writing
3 ICLK
cycles when
reading,
2 ICLK
cycles when
writing
0008 C041h
PORT1
Port input data register
PIDR
8
8
3 or 4
PCLKB
cycles when
reading,
2 or 3
PCLKB
cycles when
writing
3 ICLK
cycles when
reading,
2 ICLK
cycles when
writing
0008 C042h
PORT2
Port input data register
PIDR
8
8
3 or 4
PCLKB
cycles when
reading,
2 or 3
PCLKB
cycles when
writing
3 ICLK
cycles when
reading,
2 ICLK
cycles when
writing
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 41 of 105
RX220 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (16 / 20)
Number of Access Cycles
ICLK
PCLK
ICLK <
PCLK
8
3 or 4
PCLKB
cycles when
reading,
2 or 3
PCLKB
cycles when
writing
3 ICLK
cycles when
reading,
2 ICLK
cycles when
writing
8
8
3 or 4
PCLKB
cycles when
reading,
2 or 3
PCLKB
cycles when
writing
3 ICLK
cycles when
reading,
2 ICLK
cycles when
writing
PIDR
8
8
3 or 4
PCLKB
cycles when
reading,
2 or 3
PCLKB
cycles when
writing
3 ICLK
cycles when
reading,
2 ICLK
cycles when
writing
Port input data register
PIDR
8
8
3 or 4
PCLKB
cycles when
reading,
2 or 3
PCLKB
cycles when
writing
3 ICLK
cycles when
reading,
2 ICLK
cycles when
writing
PORTB
Port input data register
PIDR
8
8
3 or 4
PCLKB
cycles when
reading,
2 or 3
PCLKB
cycles when
writing
3 ICLK
cycles when
reading,
2 ICLK
cycles when
writing
0008 C04Ch
PORTC
Port input data register
PIDR
8
8
3 or 4
PCLKB
cycles when
reading,
2 or 3
PCLKB
cycles when
writing
3 ICLK
cycles when
reading,
2 ICLK
cycles when
writing
0008 C04Dh
PORTD
Port input data register
PIDR
8
8
3 or 4
PCLKB
cycles when
reading,
2 or 3
PCLKB
cycles when
writing
3 ICLK
cycles when
reading,
2 ICLK
cycles when
writing
0008 C04Eh
PORTE
Port input data register
PIDR
8
8
3 or 4
PCLKB
cycles when
reading,
2 or 3
PCLKB
cycles when
writing
3 ICLK
cycles when
reading,
2 ICLK
cycles when
writing
0008 C051h
PORTH
Port input data register
PIDR
8
8
3 or 4
PCLKB
cycles when
reading,
2 or 3
PCLKB
cycles when
writing
3 ICLK
cycles when
reading,
2 ICLK
cycles when
writing
0008 C052h
PORTJ
Port input data register
PIDR
8
8
3 or 4
PCLKB
cycles when
reading,
2 or 3
PCLKB
cycles when
writing
3 ICLK
cycles when
reading,
2 ICLK
cycles when
writing
0008 C060h
PORT0
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C061h
PORT1
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
Address
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
0008 C043h
PORT3
Port input data register
PIDR
8
0008 C044h
PORT4
Port input data register
PIDR
0008 C045h
PORT5
Port input data register
0008 C04Ah
PORTA
0008 C04Bh
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 42 of 105
RX220 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (17 / 20)
Number of Access Cycles
Address
Module
Symbol
Register Name
Register
Symbol
0008 C062h
PORT2
Port mode register
0008 C063h
PORT3
Port mode register
0008 C064h
PORT4
0008 C065h
0008 C06Ah
ICLK
PCLK
Number
of Bits
Access
Size
ICLK <
PCLK
PMR
8
8
2, 3 PCLKB
2 ICLK
PMR
8
8
2, 3 PCLKB
2 ICLK
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
PORT5
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
PORTA
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C06Bh
PORTB
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C06Ch
PORTC
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C06Dh
PORTD
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C06Eh
PORTE
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C071h
PORTH
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C072h
PORTJ
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C082h
PORT1
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C083h
PORT1
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C085h
PORT2
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C086h
PORT3
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C087h
PORT3
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C094h
PORTA
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C095h
PORTA
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C096h
PORTB
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C097h
PORTB
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C098h
PORTC
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C099h
PORTC
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C09Ch
PORTE
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C0C0h
PORT0
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0C1h
PORT1
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0C2h
PORT2
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0C3h
PORT3
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0C4h
PORT4
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0C5h
PORT5
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0CAh
PORTA
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0CBh
PORTB
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0CCh
PORTC
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0CDh
PORTD
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0CEh
PORTE
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0D1h
PORTH
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0D2h
PORTJ
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0E1h
PORT1
Drive capacity control register
DSCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0EBh
PORTB
Drive capacity control register
DSCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0ECh
PORTC
Drive capacity control register
DSCR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 C11Fh
MPC
Write-protect register
PWPR
8
8
2, 3 PCLKB
0008 C120h
PORT
Port switching register B
PSRB
8
8
2, 3 PCLKB
2 ICLK
0008 C121h
PORT
Port switching register A
PSRA
8
8
2, 3 PCLKB
2 ICLK
0008 C147h
MPC
P07 pin function control register
P07PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C14Ah
MPC
P12 pin function control register
P12PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C14Bh
MPC
P13 pin function control register
P13PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C14Ch
MPC
P14 pin function control register
P14PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C14Dh
MPC
P15 pin function control register
P15PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C14Eh
MPC
P16 pin function control register
P16PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C14Fh
MPC
P17 pin function control register
P17PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C150h
MPC
P20 pin function control register
P20PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C151h
MPC
P21 pin function control register
P21PFS
8
8
2, 3 PCLKB
2 ICLK
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 43 of 105
RX220 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (18 / 20)
Number of Access Cycles
Address
Module
Symbol
0008 C152h
0008 C153h
ICLK
PCLK
Register Name
Register
Symbol
Number
of Bits
Access
Size
ICLK <
PCLK
MPC
P22 pin function control register
P22PFS
8
8
2, 3 PCLKB
2 ICLK
MPC
P23 pin function control register
P23PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C154h
MPC
P24 pin function control register
P24PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C155h
MPC
P25 pin function control register
P25PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C156h
MPC
P26 pin function control register
P26PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C157h
MPC
P27 pin function control register
P27PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C158h
MPC
P30 pin function control register
P30PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C159h
MPC
P31 pin function control register
P31PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C15Ah
MPC
P32 pin function control register
P32PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C15Bh
MPC
P33 pin function control register
P33PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C15Ch
MPC
P34 pin function control register
P34PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C160h
MPC
P40 pin function control register
P40PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C161h
MPC
P41 pin function control register
P41PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C162h
MPC
P42 pin function control register
P42PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C163h
MPC
P43 pin function control register
P43PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C164h
MPC
P44 pin function control register
P44PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C165h
MPC
P45 pin function control register
P45PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C166h
MPC
P46 pin function control register
P46PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C167h
MPC
P47 pin function control register
P47PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C16Ch
MPC
P54 pin function control register
P54PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C16Dh
MPC
P55 pin function control register
P55PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C190h
MPC
PA0 pin function control register
PA0PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C191h
MPC
PA1 pin function control register
PA1PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C192h
MPC
PA2 pin function control register
PA2PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C193h
MPC
PA3 pin function control register
PA3PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C194h
MPC
PA4 pin function control register
PA4PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C195h
MPC
PA5 pin function control register
PA5PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C196h
MPC
PA6 pin function control register
PA6PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C197h
MPC
PA7 pin function control register
PA7PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C198h
MPC
PB0 pin function control register
PB0PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C199h
MPC
PB1 pin function control register
PB1PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C19Ah
MPC
PB2 pin function control register
PB2PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C19Bh
MPC
PB3 pin function control register
PB3PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C19Ch
MPC
PB4 pin function control register
PB4PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C19Dh
MPC
PB5 pin function control register
PB5PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C19Eh
MPC
PB6 pin function control register
PB6PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C19Fh
MPC
PB7 pin function control register
PB7PFS
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 C1A0h
MPC
PC0 pin function control register
PC0PFS
8
8
2, 3 PCLKB
0008 C1A1h
MPC
PC1 pin function control register
PC1PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1A2h
MPC
PC2 pin function control register
PC2PFS
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 C1A3h
MPC
PC3 pin function control register
PC3PFS
8
8
2, 3 PCLKB
0008 C1A4h
MPC
PC4 pin function control register
PC4PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1A5h
MPC
PC5 pin function control register
PC5PFS
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 C1A6h
MPC
PC6 pin function control register
PC6PFS
8
8
2, 3 PCLKB
0008 C1A7h
MPC
PC7 pin function control register
PC7PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1A8h
MPC
PD0 pin function control register
PD0PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1A9h
MPC
PD1 pin function control register
PD1PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1AAh
MPC
PD2 pin function control register
PD2PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1ABh
MPC
PD3 pin function control register
PD3PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1ACh
MPC
PD4 pin function control register
PD4PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1ADh
MPC
PD5 pin function control register
PD5PFS
8
8
2, 3 PCLKB
2 ICLK
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 44 of 105
RX220 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (19 / 20)
Number of Access Cycles
Address
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
ICLK
PCLK
ICLK <
PCLK
0008 C1AEh
MPC
PD6 pin function control register
PD6PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1AFh
MPC
PD7 pin function control register
PD7PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1B0h
MPC
PE0 pin function control register
PE0PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1B1h
MPC
PE1 pin function control register
PE1PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1B2h
MPC
PE2 pin function control register
PE2PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1B3h
MPC
PE3 pin function control register
PE3PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1B4h
MPC
PE4 pin function control register
PE4PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1B5h
MPC
PE5 pin function control register
PE5PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1B6h
MPC
PE6 pin function control register
PE6PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1B7h
MPC
PE7 pin function control register
PE7PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1C8h
MPC
PH0 pin function control register
PH0PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1C9h
MPC
PH1 pin function control register
PH1PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1CAh
MPC
PH2 pin function control register
PH2PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1CBh
MPC
PH3 pin function control register
PH3PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1D1h
MPC
PJ1 pin function control register
PJ1PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1D3h
MPC
PJ3 pin function control register
PJ3PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C28Fh
SYSTEM
Flash HOCO software standby control register
FHSSBYCR
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C290h
SYSTEM
Reset status register 0
RSTSR0
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C291h
SYSTEM
Reset status register 1
RSTSR1
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C293h
SYSTEM
Main clock oscillator forced oscillation control register
MOFCR
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C294h
SYSTEM
High-speed clock oscillator power supply control register
HOCOPCR
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C296h
FLASH
Flash write erase protection register
FWEPROR
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C297h
SYSTEM
Voltage monitoring circuit/comparator A control register
LVCMPCR
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C298h
SYSTEM
Voltage detection level select register
LVDLVLR
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C29Ah
SYSTEM
Voltage monitoring 1 circuit/comparator A1 control register 0
LVD1CR0
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C29Bh
SYSTEM
Voltage monitoring 2 circuit/comparator A2 control register 0
LVD2CR0
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C400h
RTC
64-Hz counter
R64CNT
8
8
2, 3 PCLKB
2 ICLK
0008 C402h
RTC
Second counter/Binary counter 0
RSECCNT/
BCNT0
8
8
2, 3 PCLKB
2 ICLK
0008 C404h
RTC
Minute counter/Binary counter 1
RMINCNT/
BCNT1
8
8
2, 3 PCLKB
2 ICLK
0008 C406h
RTC
Hour counter/Binary counter 2
RHRCNT/
BCNT2
8
8
2, 3 PCLKB
2 ICLK
0008 C408h
RTC
Day-of-week counter/Binary counter 3
RWKCNT/
BCNT3
8
8
2, 3 PCLKB
2 ICLK
0008 C40Ah
RTC
Date counter
RDAYCNT
8
8
2, 3 PCLKB
2 ICLK
0008 C40Ch
RTC
Month counter
RMONCNT
8
8
2, 3 PCLKB
2 ICLK
0008 C40Eh
RTC
Year counter
RYRCNT
16
16
2, 3 PCLKB
2 ICLK
0008 C410h
RTC
Second alarm register/Binary counter 0 alarm register
RSECAR/
BCNT0AR
8
8
2, 3 PCLKB
2 ICLK
0008 C412h
RTC
Minute alarm register/Binary counter 1 alarm register
RMINAR/
BCNT1AR
8
8
2, 3 PCLKB
2 ICLK
0008 C414h
RTC
Hour alarm register/Binary counter 2 alarm register
RHRAR/
BCNT2AR
8
8
2, 3 PCLKB
2 ICLK
0008 C416h
RTC
Day-of-week alarm register/Binary counter 3 alarm register
RWKAR/
BCNT3AR
8
8
2, 3 PCLKB
2 ICLK
0008 C418h
RTC
Date alarm register/Binary counter 0 alarm enable register
RDAYAR/
BCNT0AER
8
8
2, 3 PCLKB
2 ICLK
0008 C41Ah
RTC
Month alarm register/Binary counter 1 alarm enable register
RMONAR/
BCNT1AER
8
8
2, 3 PCLKB
2 ICLK
0008 C41Ch
RTC
Year alarm register/Binary counter 2 alarm enable register
RYRAR/
BCNT2AER
16
16
2, 3 PCLKB
2 ICLK
0008 C41Eh
RTC
Year alarm enable register/Binary counter 3 alarm enable register
RYRAREN/
BCNT3AER
8
8
2, 3 PCLKB
2 ICLK
0008 C422h
RTC
RTC control register 1
RCR1
8
8
2, 3 PCLKB
2 ICLK
0008 C424h
RTC
RTC control register 2
RCR2
8
8
2, 3 PCLKB
2 ICLK
0008 C426h
RTC
RTC control register 3
RCR3
8
8
2, 3 PCLKB
2 ICLK
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 45 of 105
RX220 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (20 / 20)
Number of Access Cycles
0008 C42Eh
RTC
Time error adjustment register
RADJ
8
8
2, 3 PCLKB
007F C402h
FLASH
Flash mode register
FMODR
8
8
2, 3 FCLK
2 ICLK
007F C410h
FLASH
Flash access status register
FASTAT
8
8
2, 3 FCLK
2 ICLK
Register Name
Register
Symbol
Number
of Bits
Access
Size
ICLK
PCLK
Address
Module
Symbol
ICLK <
PCLK
2 ICLK
007F C411h
FLASH
Flash access error interrupt enable register
FAEINT
8
8
2, 3 FCLK
2 ICLK
007F C412h
FLASH
Flash ready interrupt enable register
FRDYIE
8
8
2, 3 FCLK
2 ICLK
007F C440h
FLASH
E2 DataFlash read enable register 0
DFLRE0
16
16
2, 3 FCLK
2 ICLK
007F C450h
FLASH
E2 DataFlash programming/erasure enable register 0
DFLWE0
16
16
2, 3 FCLK
2 ICLK
007F FFB0h
FLASH
Flash status register 0
FSTATR0
8
8
2, 3 FCLK
2 ICLK
007F FFB1h
FLASH
Flash status register 1
FSTATR1
8
8
2, 3 FCLK
2 ICLK
007F FFB2h
FLASH
Flash P/E mode entry register
FENTRYR
16
16
2, 3 FCLK
2 ICLK
007F FFB4h
FLASH
Flash protection register
FPROTR
16
16
2, 3 FCLK
2 ICLK
007F FFB6h
FLASH
Flash reset register
FRESETR
16
16
2, 3 FCLK
2 ICLK
007F FFBAh
FLASH
FCU command register
FCMDR
16
16
2, 3 FCLK
2 ICLK
007F FFC8h
FLASH
FCU processing switching register
FCPSR
16
16
2, 3 FCLK
2 ICLK
007F FFCAh
FLASH
E2 DataFlash blank check control register
DFLBCCNT
16
16
2, 3 FCLK
2 ICLK
007F FFCCh
FLASH
Flash P/E status register
FPESTAT
16
16
2, 3 FCLK
2 ICLK
007F FFCEh
FLASH
E2 DataFlash blank check status register
DFLBCSTAT
16
16
2, 3 FCLK
2 ICLK
007F FFE8h
FLASH
Peripheral clock notification register
PCKAR
16
16
2, 3 FCLK
2 ICLK
Note 1.
Note 2.
Odd addresses cannot be accessed in 16-bit units. When accessing a register in 16-bit units, access the address of the TMR0 or TMR2 register.
Odd addresses cannot be accessed in 16-bit units. When accessing a register in 16-bit units, access the address of the TMOCNTL register.
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 46 of 105
RX220 Group
5. Electrical Characteristics
5.
Electrical Characteristics
5.1
Absolute Maximum Ratings
Table 5.1
Conditions:
Absolute Maximum Ratings
VSS = AVSS0 = VREFL0 = 0 V
Item
Power supply voltage
Symbol
Value
VCC
–0.3 to +6.5
Unit
+0.3*3
V
Input voltage
(except for ports for 5V tolerant*1 and port 4)
Vin
Input voltage (port 4)
Vin
–0.3 to AVCC0 +0.3*3
V
Vin
–0.3 to +6.5
V
AVCC0*2
–0.3 to +6.5
V
Input voltage (ports for 5 V
tolerant*1)
Analog power supply voltage
Reference power supply voltage
VREFH0*2
–0.3 to VCC
–0.3 to AVCC0
+0.3*3
+0.3*3
V
V
Analog input voltage (except for port 4)
VAN
Analog input voltage (port 4)
VAN
–0.3 to AVCC0 +0.3*3
V
Operating temperature
Topr
–40 to +105
°C
Storage temperature
Tstg
–55 to +125
°C
–0.3 to VCC
V
Caution: Permanent damage to the LSI may result if absolute maximum ratings are exceeded.
To preclude any malfunctions due to noise interferences, insert capacitors of high frequency characteristics between the VCC
and VSS pins, between the AVCC0 and AVSS0 pins, and between the VREFH0 and VREFL0 pins. Place capacitors of 0.1 µF or
so as close to every power pin and use the shortest and heaviest possible traces.
Connect the VCL pin to a VSS pin via a 0.1 µF (±20% accuracy) capacitor. The capacitor must be placed as close to the pin as
possible.
Note 1. Ports 12, 13, 16, and 17 are 5 V tolerant.
Note 2. Set to the same potential as VCC. When the A/D converter is not used, do not leave the AVCC0, VREFH0, AVSS0, and VREFL0
pins open. Connect the AVCC0 and VREFH0 pins to VCC, and the AVSS0 and VREFL0 pins to VSS, respectively.
Note 3. The maximum value is 6.5 V.
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 47 of 105
RX220 Group
5.2
5. Electrical Characteristics
DC Characteristics
Table 5.2
DC Characteristics (1)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
Schmitt trigger
input voltage
Symbol
Min.
Typ.
Max.
Unit
VIH
VCC × 0.7
—
5.8
V
Ports 12, 13, 16, and 17 (5 V
tolerant)
VCC × 0.8
—
5.8
Ports 0, 14, 15, 2, 3, 4, 5, A, B,
C, D, E, H, J, and RES#
VCC × 0.8
—
VCC + 0.3
VIL
–0.3
—
VCC × 0.3
–0.3
—
VCC × 0.2
∆VT
VCC × 0.05
—
—
VCC × 0.1
—
—
VCC × 0.9
—
VCC + 0.3
RIIC input pin (except for
SMBus, 5 V tolerant)
RIIC input pin (except for
SMBus)
Other than RIIC input pin
RIIC input pin (except for
SMBus)
Other than RIIC input pin
Input level voltage
(except for
Schmitt trigger
input pins)
MD pin
EXTAL
RIIC input pin (SMBus)
MD pin
Table 5.3
VIH
VIL
VCC × 0.8
—
VCC + 0.3
2.1
—
VCC + 0.3
–0.3
—
VCC × 0.1
EXTAL
–0.3
—
VCC × 0.2
RIIC input pin (SMBus)
–0.3
—
0.8
Test
Conditions
V
DC Characteristics (2)
Conditions: VCC = AVCC0 = 1.62 to 2.7 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
Schmitt trigger input
voltage
Symbol
Min.
Typ.
Max.
Unit
VIH
VCC × 0.8
—
5.8
V
Ports 0, 14, 15, 2, 3, 4, 5, A,
B, C, D, E, H, and J
VCC × 0.8
—
VCC + 0.3
RES#
VCC × 0.9
—
VCC + 0.3
–0.3
—
VCC × 0.2
–0.3
—
VCC × 0.1
VCC × 0.01
—
—
Ports 12, 13, 16, and 17
(5 V tolerant)
Ports 0, 1, 2, 3, 4, 5, A, B, C,
D, E, H, and J
VIL
RES#
Input level voltage
(except for Schmitt
trigger input pins)
All input pins
∆VT
MD pin
VIH
EXTAL
MD pin
EXTAL
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
VIL
VCC × 0.9
—
VCC + 0.3
VCC × 0.8
—
VCC + 0.3
–0.3
—
VCC × 0.1
–0.3
—
VCC × 0.2
Test
Conditions
V
Page 48 of 105
RX220 Group
Table 5.4
5. Electrical Characteristics
DC Characteristics (3)
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
Input leakage
current
RES#, MD pin, P35/NMI
Three-state
leakage current
(off-state)
Other pins except for ports for 5 V
tolerant
Input capacitance
All input pins
(except for XCIN and XCOUT)
Symbol
Min.
Typ.
Max.
Unit
Iin
—
—
1.0
µA
Vin = 0 V, VCC
ITSI
—
—
0.2
µA
Vin = 0 V, VCC
—
—
1.0
—
—
15
—
—
3
Ports for 5 V tolerant
Cin
XCIN and XCOUT
Table 5.5
Conditions:
Test Conditions
Vin = 0 V, 5.8 V
pF
Vin = 0 V,
f = 1 MHz,
Ta = 25°C
DC Characteristics (4)
VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
VCC
Item
Input pull-up MOS
current
All ports
(except for port 35)
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Symbol
Ip
1.62 to 2.7 V
2.7 to 4.0 V
4.0 to 5.5 V
Min.
Max.
Min.
Max.
Min.
Max.
–150
–5
–200
–10
–400
–50
Unit
µA
Test Conditions
Vin = 0 V
Page 49 of 105
RX220 Group
Table 5.6
5. Electrical Characteristics
DC Characteristics (5)
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
Supply
current*1
Medium-speed
operating modes
1A and 1B
Normal operating
mode
Sleep mode
Max.
Unit
ICC
4.6
—
mA
ICLK = 32 MHz
ICLK = 20 MHz
3.2
—
All peripheral
operation: Normal*3
ICLK = 32 MHz
14
—
ICLK = 20 MHz
9.5
—
All peripheral
operation: Max.*3
ICLK = 32 MHz
—
25
ICLK = 20 MHz
—
19
No peripheral
operation*2
ICLK = 32 MHz
3.8
—
ICLK = 20 MHz
3.0
—
All peripheral
operation: Normal*3
ICLK = 32 MHz
10
—
ICLK = 20 MHz
7
—
ICLK = 32 MHz
2.5
—
ICLK = 20 MHz
2.0
—
17
—
Increase during
BGO operation*4
Medium-speed operating mode 1A
Medium-speed operating mode 1B
17
—
Normal operating
mode
No peripheral
operation*5
ICLK = 8 MHz
1.4
—
ICLK = 4 MHz
0.9
—
ICLK = 2 MHz
0.7
—
ICLK = 8 MHz
4.2
—
ICLK = 4 MHz
2.6
—
ICLK = 2 MHz
1.8
—
ICLK = 8 MHz
—
6.5
ICLK = 4 MHz
—
3.7
ICLK = 2 MHz
—
2.4
ICLK = 8 MHz
1.5
—
ICLK = 4 MHz
1.2
—
ICLK = 2 MHz
1.1
—
ICLK = 8 MHz
3.1
—
ICLK = 4 MHz
2.1
—
ICLK = 2 MHz
1.5
—
ICLK = 8 MHz
1.4
—
ICLK = 4 MHz
1.1
—
All peripheral
operation: Normal*6
All peripheral
operation: Max.*6
Sleep mode
No peripheral
operation*5
All peripheral
operation: Normal*6
All-module clock stop mode
Low-speed
operating mode 2
Typ.*9
No peripheral
operation*2
All-module clock stop mode
Low-speed
operating mode 1
Symbol
Normal operating
mode
No peripheral
operation*7
All peripheral
operation: Normal*8
All peripheral
operation: Max.*8
Sleep mode
No peripheral
operation*7
All peripheral
operation: Normal*8
All-module clock stop mode
ICLK = 2 MHz
1.0
—
ICLK = 32 kHz
0.027
—
ICLK = 32 kHz
0.04
—
ICLK = 32 kHz
—
0.23
ICLK = 32 kHz
0.024
—
ICLK = 32 kHz
0.034
—
0.016
—
Test
Conditions
Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up MOSs
are in the off state.
Note 2. Clock supply to the peripheral functions is stopped. This does not include BGO operation. The clock source is HOCO. BCLK,
FCLK, and PCLK are set to divided by 64.
Note 3. Clocks are supplied to the peripheral functions. This does not include BGO operation. The clock source is HOCO. BCLK, FCLK,
and PCLK are ICLK divided by 1.
Note 4. This is the increase if data is programmed to or erasing from the ROM or E2 DataFlash during program execution.
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 50 of 105
RX220 Group
5. Electrical Characteristics
Note 5. Clock supply to the peripheral functions is stopped. This does not include BGO operation. The clock source is HOCO. BCLK,
FCLK, and PCLK are set to divided by 64.
Note 6. Clocks are supplied to the peripheral functions. This does not include BGO operation. The clock source is HOCO. BCLK, FCLK,
and PCLK are ICLK divided by 1.
Note 7. Clock supply to the peripheral functions is stopped. This does not include BGO operation. The clock source is the sub oscillation
circuit. BCLK, FCLK, and PCLK are set to divided by 64.
Note 8. Clocks are supplied to the peripheral functions. This does not include BGO operation. The clock source is the sub oscillation
circuit. BCLK, FCLK, and PCLK are ICLK divided by 1.
Note 9. VCC = 3.3 V.
25
Ta = 105°C, ICLK = 32 MHz*2
20
ICC (mA)
Ta = 25°C, ICLK = 32 MHz*1
15
Ta = 105°C, ICLK = 20 MHz*2
10
Ta = 25°C, ICLK = 20 MHz*1
5
0
1.0
2.0
3.0
4.0
5.0
6.0
VCC (V)
Note 1. All peripheral operation is normal. This does not include BGO operation.
Average value of the tested middle samples during product evaluation.
Note 2. All peripheral operation is maximum. This does not include BGO operation.
Average value of the tested upper-limit samples during product evaluation.
Figure 5.1
Voltage Dependency in Medium-Speed Operating Modes 1A and 1B (Reference Data)
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 51 of 105
RX220 Group
5. Electrical Characteristics
7
Ta = 105°C, ICLK = 8 MHz*2
6
5
ICC (mA)
Ta = 25°C, ICLK = 8 MHz*1
4
Ta = 105°C, ICLK = 4 MHz*2
Ta = 105°C, ICLK = 2 MHz*2
3
Ta = 25°C, ICLK = 4 MHz*1
2
Ta = 25°C, ICLK = 2 MHz*1
1
0
1.0
2.0
3.0
4.0
5.0
6.0
VCC (V)
Note 1. All peripheral operation is normal. This does not include BGO operation.
Average value of the tested middle samples during product evaluation.
Note 2. All peripheral operation is maximum. This does not include BGO operation.
Average value of the tested upper-limit samples during product evaluation.
Figure 5.2
Voltage Dependency in Low-Speed Operating Mode 1 (Reference Data)
200
Ta = 105°C, ICLK = 32.768 kHz*2
ICC (A)
150
100
50
Ta = 25°C, ICLK = 32.768 kHz*1
0
1.0
2.0
3.0
4.0
5.0
6.0
VCC (V)
Note 1. All peripheral operation is normal. This does not include BGO operation.
Average value of the tested middle samples during product evaluation.
Note 2. All peripheral operation is maximum. This does not include BGO operation.
Average value of the tested upper-limit samples during product evaluation.
Figure 5.3
Voltage Dependency in Low-Speed Operating Mode 2 (Reference Data)
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 52 of 105
RX220 Group
Table 5.7
5. Electrical Characteristics
DC Characteristics (6)
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
Supply
current*1
Software
standby mode*2
Flash memory power supplied,
HOCO power supplied, POR low
power consumption function disabled
(SOFTCUT bit = 000b)
Flash memory power not supplied,
HOCO power not supplied, POR low
power consumption function enabled
(SOFTCUT bit = 11xb)
Ta = 25°C
Symbol
Typ.*3
Max.
Unit
ICC
9.3
16.4
µA
Ta = 55°C
11.3
25
Ta = 85°C
16
62
Ta = 105°C
25
127
Ta = 25°C
1.7
7.0
Ta = 55°C
2.6
15
Ta = 85°C
6.3
51
Ta = 105°C
14.2
115
Increments produced by running voltage detection circuits and disabling
the POR low power consumption function
1.4
—
Increment for RTC operation (low CL)
0.6
—
Increment for RTC operation (standard CL)
1.4
—
Test
Conditions
Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.
Note 2. The IWDT and LVD are stopped.
Note 3. VCC = 3.3 V.
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 53 of 105
RX220 Group
5. Electrical Characteristics
100
Ta = 105°C*2
Ta = 85°C*2
ICC (A)
Ta = 105°C*1
Ta = 55°C*2
10
Ta = 85°C*1
Ta = 25°C*2
Ta = 55°C*1
Ta = 25°C*1
1
1.5
2.0
2.5
3.5
3.0
4.0
4.5
5.0
5.5
6.0
VCC (V)
Note 1. Average value of the tested middle samples during product evaluation.
Note 2. Average value of the tested upper-limit samples during product evaluation.
Figure 5.4
Voltage Dependency in Software Standby Mode (SOFTCUT Bit = 11xb) (Reference Data)
100
VCC = 3.3 V*2
ICC (A)
10
VCC = 3.3 V*1
1
0.1
-50
-30
-10
10
30
50
70
90
Ta (°C)
Note 1. Average value of the tested middle samples during product evaluation.
Note 2. Average value of the tested upper-limit samples during product evaluation.
Figure 5.5
Temperature Dependency in Software Standby Mode (SOFTCUT Bit = 11xb) (Reference
Data)
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 54 of 105
RX220 Group
Table 5.8
5. Electrical Characteristics
DC Characteristics (7)
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
Permissible total consumption
power*1
Symbol
Typ.
Max.
Unit
Test Conditions
Pd
—
350
mW
—
150
Ta = –40 to 85°C
85°C < Ta ≤ 105°C
Note: • Please contact Renesas Electronics sales office for derating of operation under Ta = +85°C to +105°C. Derating is the
systematic reduction of load for the sake of improved reliability.
Note 1. Total power dissipated by the entire chip (including output currents)
Table 5.9
DC Characteristics (8)
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VREFH0 = 1.62 to AVCC0, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
Analog power
supply current
During A/D conversion
Min.
Typ.
Max.
Unit
AICC
—
1.0
3.0
mA
—
0.2
3.0
µA
IREFH0
—
0.1
0.2
mA
—
0.2
0.4
µA
Waiting for A/D conversion (all units)
Reference
power supply
current
Table 5.10
Conversion time = 1.56 µs
Symbol
During A/D conversion
Conversion time = 1.56 µs
Waiting for A/D conversion (all units)
Test Conditions
DC Characteristics (9)
Conditions: VCC = AVCC0, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
RAM standby voltage
Table 5.11
Symbol
Min.
Typ.
Max.
Unit
VRAM
1.62
—
—
V
Test Conditions
DC Characteristics (10)
Conditions: VCC = AVCC0 = 0 to 5.5 V, VREFH0 = 0 to AVCC0, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
VCC rising gradient
Table 5.12
Symbol
Min.
Typ.
Max.
Unit
SrVCC
0.02
—
20
ms/V
Test Conditions
At cold start
DC Characteristics (11)
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (5.5 V) and
lower limit (1.62 V).
When VCC change exceeds VCC ±10%, the allowable voltage change rising/falling gradient dt/dVCC must be met.
Item
Allowable ripple frequency
Allowable voltage change rising/
falling gradient
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
fr(VCC)
—
—
10
kHz
VCC × 0.1 < Vr(VCC) ≤ VCC × 0.2
—
—
1
MHz
VCC × 0.05 < Vr(VCC) ≤ VCC × 0.1
—
—
10
MHz
Vr(VCC) ≤ VCC × 0.05
1.0
—
—
ms/V
When VCC change exceeds VCC ±10%
dt/dVCC
Page 55 of 105
RX220 Group
5. Electrical Characteristics
1/fr(VCC)
VCC
Figure 5.6
Table 5.13
Vr(VCC)
Ripple Waveform
Permissible Output Currents (1)
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, when total power (mW) < 1000 – 10 × Ta
Item
Permissible output low current (average value per 1 pin)
Permissible output low current (maximum value per 1 pin)
Symbol
Normal output mode
IOL
Unit
4.0
mA
High-drive output mode
16.0
Normal output mode
4.0
High-drive output mode
Permissible output low current (total)
Max.
Total of all output pins
16.0
IOL
80
mA
IOH
–4.0
mA
Permissible output high current (average value per 1 pin)
Normal output mode
High-drive output mode
–8.0
Permissible output high current (maximum value per 1 pin)
Normal output mode
–4.0
High-drive output mode
–8.0
Permissible output high current (total)
Table 5.14
Total of all output pins
mA
IOH
mA
–60
mA
Permissible Output Currents (2)
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, when total power (mW) ≥ 1000 – 10 × Ta
Item
Symbol
Max.
Unit
IOL
2.0
mA
Permissible output low current (average value per 1 pin)
Normal output mode
High-drive output mode
8.0
Permissible output low current (maximum value per 1 pin)
Normal output mode
2.0
High-drive output mode
8.0
Permissible output low current (total)
Total of all output pins
Permissible output high current (average value per 1 pin)
Normal output mode
IOL
40
mA
IOH
–2.0
mA
High-drive output mode
Permissible output high current (maximum value per 1 pin)
Permissible output high current (total)
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
–4.0
Normal output mode
–2.0
High-drive output mode
–4.0
Total of all output pins
mA
IOH
–30
mA
mA
Page 56 of 105
RX220 Group
Table 5.15
Conditions:
5. Electrical Characteristics
Output Values of Voltage (1)
VCC = AVCC0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, when total power (mW) < 1000 – 10 × Ta
Item
Output low
All output pins
(other than RIIC)
Symbol
Min.
Max.
Unit
VOL
—
1.0
V
—
Normal output
mode
IOL = 4.0 mA
1.0
IOL = 8.0 mA
IOL = 16.0 mA
—
0.4
IOL = 3.0 mA
—
0.6
IOL = 6.0 mA
VCC – 1.0
—
VCC – 1.0
—
RIIC pins
All output pins
Normal output
mode
VOH
High-drive
output mode
Table 5.16
Conditions:
All output pins
(other than RIIC)
Symbol
Min.
Max.
Unit
VOL
—
1.0
V
—
Normal output
mode
RIIC pins
All output pins
Normal output
mode
VOH
High-drive
output mode
Table 5.17
Conditions:
IOH = – 3.0 mA
IOH = – 4.0 mA
IOH = – 5.0 mA
IOH = – 8.0 mA
Output Values of Voltage (2)
High-drive
output mode
Output high
V
VCC = AVCC0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, when total power (mW) ≥ 1000 – 10 × Ta
Item
Output low
VCC = 2.7 to 4.0 V VCC = 4.0 to 5.5 V
IOL = 3.0 mA
High-drive
output mode
Output high
Test Conditions
Test Conditions
VCC = 2.7 to 4.0 V VCC = 4.0 to 5.5 V
IOL = 2.0 mA
IOL = 2.0 mA
1.0
IOL = 8.0 mA
IOL = 8.0 mA
—
0.4
IOL = 3.0 mA
—
0.6
IOL = 6.0 mA
VCC – 1.0
—
VCC – 1.0
—
V
IOH = – 2.0 mA
IOH = – 2.0 mA
IOH = – 4.0 mA
IOH = – 4.0 mA
Output Values of Voltage (3)
VCC = AVCC0 = 1.62 to 2.7 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
Output low
All output pins
(other than RIIC)
Output high
All output pins
Normal output mode
Min.
Max.
Unit
VOL
—
0.4
V
—
0.4
VOH
VCC – 0.4
—
VCC – 0.4
—
High-drive output mode
Normal output mode
High-drive output mode
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Symbol
Test Conditions
IOL = 0.5 mA
IOL = 2.0 mA
V
IOH = –0.5 mA
IOH = –1.0 mA
Page 57 of 105
RX220 Group
5.2.1
5. Electrical Characteristics
Standard I/O Pin Output Characteristics (1)
Figure 5.7 to Figure 5.11 show the characteristics when normal output is selected by the drive capacity control register.
IOH/IOL vs VOH/VOL
60
50
VCC = 5.5 V
40
30
VCC = 3.3 V
20
IOH/IOL [mA]
VCC = 2.7 V
10
0
VCC = 1.62 V
0
1
2
3
4
5
6
VCC = 1.62 V
–10
VCC = 2.7 V
–20
VCC = 3.3 V
–30
–40
VCC = 5.5 V
–50
–60
VOH/VOL [V]
Figure 5.7
VOH/VOL and IOH/IOL Voltage Characteristics at Ta = 25°C when Normal Output is
Selected (Reference Data)
IOH/IOL vs VOH/VOL
5
Ta = –40°C
4
Ta = 25°C
Ta = 105°C
3
IOH/IOL [mA]
2
1
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
–1
–2
–3
–4
Ta = 105°C
Ta = 25°C
Ta = –40°C
–5
VOH/VOL [V]
Figure 5.8
VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 1.62 V when Normal Output
is Selected (Reference Data)
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 58 of 105
RX220 Group
5. Electrical Characteristics
IOH/IOL vs VOH/VOL
20
Ta = –40°C
15
Ta = 25°C
Ta = 105°C
10
IOH/IOL [mA]
5
0
0
0.5
1
1.5
2
2.5
3
–5
–10
Ta = 105°C
Ta = 25°C
–15
Ta = –40°C
–20
VOH/VOL [V]
Figure 5.9
VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 2.7 V when Normal Output is
Selected (Reference Data)
IOH/IOL vs VOH/VOL
30
Ta = –40°C
Ta = 25°C
20
Ta = 105°C
IOH/IOL [mA]
10
0
0
0.5
1
1.5
2
2.5
3
3.5
–10
Ta = 105°C
–20
Ta = 25°C
Ta = –40°C
–30
VOH/VOL [V]
Figure 5.10
VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 3.3 V when Normal Output is
Selected (Reference Data)
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 59 of 105
RX220 Group
5. Electrical Characteristics
IOH/IOL vs VOH/VOL
60
Ta = –40°C
50
Ta = 25°C
40
Ta = 105°C
30
IOH/IOL [mA]
20
10
0
0
1
2
3
4
5
6
–10
–20
–30
Ta = 105 °C
–40
–50
Ta = 25°C
Ta = –40°C
–60
VOH/VOL [V]
Figure 5.11
VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 5.5 V when Normal Output is
Selected (Reference Data)
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 60 of 105
RX220 Group
5.2.2
5. Electrical Characteristics
Standard I/O Pin Output Characteristics (2)
Figure 5.12 to Figure 5.16 show the characteristics when high-drive output is selected by the drive capacity control
register.
IOH/IOL vs VOH/VOL
120
VCC = 5.5 V
100
80
60
VCC = 3.3 V
40
VCC = 2.7 V
IOH/IOL [mA]
20
0
VCC = 1.62 V
0
1
2
3
4
5
6
VCC = 1.62 V
–20
VCC = 2.7 V
–40
VCC = 3.3 V
–60
–80
VCC = 5.5 V
–100
–120
VOH/VOL [V]
VOH/VOL and IOH/IOL Voltage Characteristics at Ta = 25°C when High-Drive Output is
Selected (Reference Data)
Figure 5.12
IOH/IOL vs VOH/VOL
12
Ta = –40°C
10
Ta = 25°C
Ta = 105°C
8
6
IOH/IOL [mA]
4
2
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
–2
–4
–6
–8
Ta = 105°C
Ta = 25°C
Ta = –40°C
–10
–12
VOH/VOL [V]
Figure 5.13
VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 1.62 V when High-Drive
Output is Selected (Reference Data)
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 61 of 105
RX220 Group
5. Electrical Characteristics
IOH/IOL vs VOH/VOL
50
Ta = –40°C
40
Ta = 25°C
30
Ta = 105°C
IOH/IOL [mA]
20
10
0
0
0.5
1
1.5
2
2.5
3
–10
Ta = 105°C
–20
Ta = 25°C
–30
Ta = –40°C
–40
–50
VOH/VOL [V]
Figure 5.14
VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 2.7 V when High-Drive
Output is Selected (Reference Data)
IOH/IOL vs VOH/VOL
60
Ta = –40°C
50
Ta = 25°C
40
Ta = 105°C
30
IOH/IOL [mA]
20
10
0
0
0.5
1
1.5
2
2.5
3
3.5
–10
–20
Ta = 105°C
–30
–40
Ta = 25°C
Ta = –40°C
–50
–60
VOH/VOL [V]
Figure 5.15
VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 3.3 V when High-Drive
Output is Selected (Reference Data)
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 62 of 105
RX220 Group
5. Electrical Characteristics
IOH/IOL vs VOH/VOL
140
120
Ta = –40°C
100
Ta = 25°C
80
Ta = 105°C
60
IOH/IOL [mA]
40
20
0
0
1
2
3
4
5
6
–20
–40
–60
Ta = 105°C
–80
Ta = 25°C
–100
Ta = –40°C
–120
–140
VOH/VOL [V]
Figure 5.16
VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 5.5 V when High-Drive
Output is Selected (Reference Data)
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Dec 20, 2013
Page 63 of 105
RX220 Group
5.2.3
5. Electrical Characteristics
RIIC Pin Output Characteristics
Figure 5.17 to Figure 5.20 show the output characteristics of the RIIC pin.
IOL vs VOL [V]
80
70
VCC = 5.5 V
IOL [mA]
60
50
40
VCC = 3.3 V
30
VCC = 2.7 V
20
10
0
0
1
2
3
4
5
6
VOL [V]
Figure 5.17
VOL and IOL Voltage Characteristics of RIIC Output Pin at Ta = 25°C (Reference Data)
IOL vs VOL [V]
30
Ta = –40°C
25
Ta = 25°C
IOL [mA]
20
Ta = 105°C
15
10
5
0
0
0.5
1
1.5
2
2.5
3
VOL [V]
Figure 5.18
VOL and IOL Temperature Characteristics of RIIC Output Pin at VCC = 2.7 V (Reference
Data)
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 64 of 105
RX220 Group
5. Electrical Characteristics
IOL vs VOL [V]
40
Ta = –40°C
35
Ta = 25°C
IOL [mA]
30
25
Ta = 105°C
20
15
10
5
0
0
0.5
1
1.5
2
2.5
3
3.5
VOL [V]
Figure 5.19
VOL and IOL Temperature Characteristics of RIIC Output Pin at VCC = 3.3 V (Reference
Data)
IOL vs VOL [V]
80
Ta = –40°C
70
Ta = 25°C
60
IOL [mA]
Ta = 105°C
50
40
30
20
10
0
0
1
2
3
4
5
6
VOL [V]
Figure 5.20
VOL and IOL Temperature Characteristics of RIIC Output Pin at VCC = 5.5 V (Reference
Data)
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 65 of 105
RX220 Group
5.3
5. Electrical Characteristics
AC Characteristics
Table 5.18
Operation Frequency Value (Medium-Speed Operating Mode 1A)
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
Maximum operating
frequency
Symbol
System clock (ICLK)
FlashIF clock
fmax
(FCLK)*1
VCC
1.62 to 1.8 V
1.8 to 2.7 V
2.7 to 5.5 V
8
8
32
8
8
32
Peripheral module clock (PCLKB)
8
8
32
Peripheral module clock (PCLKD)*2
8
8
32
Unit
MHz
Note 1. The VCC is 2.7 to 5.5 V and the FCLK must be running at a frequency of at least 4 MHz during programming or erasing of the
flash memory.
Note 2. The lower-limit frequency of PCLKD is 1 MHz when the A/D converter is in use.
Table 5.19
Operation Frequency Value (Medium-Speed Operating Mode 1B)
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 =VREFL0 = 0 V, Ta = –40 to +105°C
Item
Maximum operating
frequency
Symbol
System clock (ICLK)
fmax
FlashIF clock (FCLK)*1
Peripheral module clock (PCLKB)
Peripheral module clock
(PCLKD)*2
VCC
1.62 to 1.8 V
1.8 to 2.7 V
2.7 to 5.5 V
8
8
32
8
8
32
8
8
32
8
8
32
Unit
MHz
Note 1. The VCC is 1.62 to 3.6 V and the FCLK must be running at a frequency of at least 4 MHz during programming or erasing of the
flash memory.
Note 2. The lower-limit frequency of PCLKD is 1 MHz when the A/D converter is in use.
Table 5.20
Operation Frequency Value (Low-Speed Operating Mode 1)
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
Maximum operating
frequency
Symbol
System clock (ICLK)
FlashIF clock
fmax
(FCLK)*1
Peripheral module clock (PCLKB)
Peripheral module clock
(PCLKD)*2
VCC
1.62 to 1.8 V
1.8 to 2.7 V
2.7 to 5.5 V
2
4
8
2
4
8
2
4
8
2
4
8
Unit
MHz
Note 1. Programming and erasing the flash memory is impossible.
Note 2. The lower-limit frequency of PCLKD is 1 MHz when the A/D converter is in use.
Table 5.21
Operation Frequency Value (Low-Speed Operating Mode 2)
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
Maximum operating
frequency
Symbol
System clock (ICLK)
FlashIF clock
fmax
(FCLK)*1
Peripheral module clock (PCLKB)
Peripheral module clock
(PCLKD)*2
VCC
1.62 to 1.8 V
1.8 to 2.7 V
2.7 to 5.5 V
32.768
32.768
32.768
32.768
32.768
32.768
32.768
32.768
32.768
32.768
32.768
32.768
Unit
kHz
Note 1. Programming and erasing the flash memory is impossible.
Note 2. The A/D converter cannot be used.
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 66 of 105
RX220 Group
5. Electrical Characteristics
5.3.1
Clock Timing
Table 5.22
Clock Timing
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
Symbol
Min.
Typ.
Max.
Unit
tEXcyc
50
—
—
ns
EXTAL external clock input high pulse width
tEXH
20
—
—
ns
EXTAL external clock input low pulse width
tEXL
20
—
—
ns
EXTAL external clock rising time
tEXr
—
—
5
ns
EXTAL external clock falling time
tEXf
—
—
5
ns
tEXWT
1
—
—
ms
fMAIN
1
—
20
MHz
tMAINOSC
—
3
—
ms
tMAINOSC
—
50
—
µs
tMAINOSCWT
—
6
—
ms
tMAINOSCWT
—
100
—
µs
tcyc
7.27
8
8.89
µs
fLOCO
112.5
125
137.5
kHz
tLOCOWT
—
—
20
µs
fHOCO
31.680
32
32.320
MHz
36.495
36.864
37.233
39.600
40
40.400
49.500
50
50.500
31.520
32
32.480
36.311
36.864
37.417
39.400
40
40.600
49.250
50
50.750
EXTAL external clock input cycle time
EXTAL external clock input wait
Main clock oscillator oscillation
time*1
frequency*2
Main clock oscillation stabilization time
(crystal)*2
Main clock oscillation stabilization time (ceramic
Main clock oscillation stabilization wait time
resonator)*2
(crystal)*2
Main clock oscillation stabilization wait time (ceramic
resonator)*2
LOCO clock cycle time
LOCO clock oscillation frequency
LOCO clock oscillation stabilization wait time
HOCO clock oscillation frequency
Test Conditions
Figure 5.21
Figure 5.22
Figure 5.23
Ta = 0 to 50°C
Ta = -40 to 105°C
HOCO clock oscillation stabilization time 1
tHOCO1
—
—
50
µs
Figure 5.24
HOCO clock oscillation stabilization time 2
tHOCO2
—
—
10
µs
Figure 5.25
HOCO clock oscillation stabilization wait time
tHOCOWT
—
—
20
µs
Figure 5.25
HOCO clock power supply stabilization time
tHOCOP
—
—
350
µs
Figure 5.26
Sub-clock oscillator oscillation frequency
fSUB
—
32.768
—
kHz
Sub-clock oscillation stabilization time*3
tSUBOSC
2
—
—
s
tSUBOSCWT
4
—
—
s
Sub-clock oscillation stabilization wait time*3
Figure 5.27
Note 1. The time interval from the time P36 and P37 are configured for input and the main clock oscillator stopping bit
(MOSCCR.MOSTP) is set to 0 (operating) until the clock becomes available.
Note 2. When specifying the main clock oscillator stabilization time, load MOSCWTCR register with a stabilization time value that is
greater than the resonator-vendor-recommended value. When determining the main lock oscillation stabilization wait time, allow
an adequate margin (2 times is recommended) for the main clock oscillation stabilization time.
Start using the main clock in the main clock oscillation stabilization wait time (tMAINOSCWT) after setting up the main clock
oscillator for operation with the MOSCCR.MOSTP bit.
The indicated value is a reference value that is measured for an 8 MHz resonator.
Note 3. When specifying the sub-clock oscillation stabilization time, load SOSCWTCR register with the resonator-vendor-recommended
stabilization time value minus 2 seconds. When determining the sub-clock oscillation stabilization wait time, allow an adequate
margin (2 times is recommended) for the sub-clock oscillation stabilization time. Start using the sub-clock in the sub-clock
oscillation stabilization wait time (tSUBOSCWT) after setting up the sub-clock oscillator for operation with the SOSCCR.SOSTP
or RCR3.RTCEN bit.
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 67 of 105
RX220 Group
5. Electrical Characteristics
tEXcyc
tEXL
tEXH
EXTAL external clock input
VCC × 0.5
tEXr
Figure 5.21
tEXf
EXTAL External Clock Input Timing
MOSCCR.MOSTP
tMAINOSC
Main clock oscillator output
tMAINOSCWT
Main clock
Figure 5.22
Main Clock Oscillation Start Timing
LOCOCR.LCSTP
tLOCOWT
LOCO clock
Figure 5.23
LOCO Clock Oscillation Start Timing
RES#
Internal reset
tRESWT
OFS1.HOCOEN
tHOCO1
HOCO clock
Figure 5.24
HOCO Clock Oscillation Start Timing (After Reset is Canceled by Setting the
OFS1.HOCOEN Bit to 0)
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 68 of 105
RX220 Group
5. Electrical Characteristics
HOCOCR.HCSTP
tHOCO2
HOCO clock output
tHOCOWT
HOCO clock
Figure 5.25
HOCO Clock Oscillation Start Timing (Oscillation is Started by Setting the
HOCOCR.HCSTP Bit)
HOCOPCR.HOCOPCNT
HOCOCR.HCSTP
tHOCOP
Internal power supply for HOCO
Figure 5.26
HOCO Power Control Timing
SOSCCR.SOSTP
tSUBOSC
Sub-clock oscillator output
tSUBOSCWT
Sub-clock
Figure 5.27
Sub-clock Oscillation Start Timing
R01DS0130EJ0110 Rev.1.10
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Page 69 of 105
RX220 Group
5. Electrical Characteristics
5.3.2
Reset Timing
Table 5.23
Reset Timing
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
Test
Conditions
Symbol
Min.
Typ.
Max.
Unit
Power-on
tRESWP
8
—
—
ms
Figure 5.28
Software standby mode, low-speed
operating modes 1 and 2
tRESWS
1
—
—
ms
Figure 5.29
Programming or erasure of the ROM or E2
DataFlash memory or blank checking of the
E2 DataFlash memory
tRESWF
200
—
—
µs
Other than above
tRESW
200
—
—
µs
Wait time after RES# cancellation
tRESWT
—
—
912
µs
Internal reset time
(independent watchdog timer reset, software reset)
tRESW2
—
—
1.4
ms
RES# pulse
width
Figure 5.28
1.55 V
VCC
RES#
tRESWP
Internal reset
tRESWT
Figure 5.28
Reset Input Timing at Power-On
tRESWS, tRESWF, tRESW
RES#
Internal reset
tRESWT
Figure 5.29
Reset Input Timing
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Dec 20, 2013
Page 70 of 105
RX220 Group
5. Electrical Characteristics
5.3.3
Timing of Recovery from Low Power Consumption Modes
Table 5.24
Timing of Recovery from Low Power Consumption Modes
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
Recovery time
after
cancellation of
software
standby mode
(HOCO power
supplied)
(SOFTCUT[2:0]
bits = 000b)*1
Recovery time
after
cancellation of
software
standby mode
(HOCO power
not supplied)
(SOFTCUT[2:0]
bits = 11xb)*1
Symbol
Min.
Typ.
Max.
Unit
Crystal resonator
connected to
main clock
oscillator*2
Main clock oscillator
operating
tSBYMC
—
3
—
ms
External clock
input to main
clock oscillator*4
Main clock oscillator
operating
tSBYEX
7
—
—
µs
Sub-clock oscillator operating*5
tSBYSC
2*3
—
—
s
HOCO clock oscillator operating*6
tSBYHO
—
—
50
µs
LOCO clock oscillator operating*5
tSBYLO
—
—
90
µs
Crystal resonator
connected to
main clock
oscillator*2
Main clock oscillator
operating
tSBYMC
—
3
—
ms
External clock
input to main
clock oscillator*4
Main clock oscillator
operating
tSBYEX
40
—
—
µs
Sub-clock oscillator operating*5
tSBYSC
2*3
—
—
s
HOCO clock oscillator operating*6
tSBYHO
—
—
0.8
ms
LOCO clock oscillator operating*5
tSBYLO
—
—
90
µs
Test
Conditions
Figure 5.30
Figure 5.30
Note 1. The recovery time varies depending on the state of each oscillator when the WAIT instruction is executed. The recovery time
when multiple oscillators are operating varies depending on the operating state of the oscillators that are not selected as the
system clock source, and depends on the time set in the wait control registers corresponding to the oscillators.
Note 2. The indicated value is measured for an 8 MHz crystal resonator. ICLK is set to divided by 1.
Note 3. When RCR3.RTCEN = 1, the time will be the time set in the SOSCWTCR register minus 2 s.
Note 4. When the external clock frequency is 20 MHz. ICLK is set to divided by 1.
Note 5. ICLK is set to divided by 1.
Note 6. When the frequency is 50 MHz, HOCOWTCR2.HSTS2[4:0] = 10101b and ICLK is set to divided by 2.
When the frequency is 32 MHz, HOCOWTCR2.HSTS2[4:0] = 10100b and ICLK is set to divided by 1.
Oscillator
ICLK
IRQ
Software standby mode
tSBYMC, tSBYEX, tSBYSC,
tSBYHO, tSBYLO
Figure 5.30
Software Standby Mode Cancellation Timing
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Dec 20, 2013
Page 71 of 105
RX220 Group
5. Electrical Characteristics
5.3.4
Control Signal Timing
Table 5.25
Control Signal Timing
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
NMI pulse width
IRQ pulse width
Symbol
Min.
tNMIW
tIRQW
Typ.
Max.
Unit
200
—
—
ns
tc(PCLKB) × 2 ≤ 200 ns, Figure 5.31
Test Conditions
tc(PCLKB) × 2
—
—
ns
tc(PCLKB) × 2 > 200 ns, Figure 5.31
200
—
—
ns
tc(PCLKB) × 2 ≤ 200 ns, Figure 5.32
tc(PCLKB) × 2
—
—
ns
tc(PCLKB) × 2 > 200 ns, Figure 5.32
Note: • 200 ns minimum in software standby mode.
NMI
tNMIW
Figure 5.31
NMI Interrupt Input Timing
IRQ
tIRQW
Figure 5.32
IRQ Interrupt Input Timing
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RX220 Group
5. Electrical Characteristics
5.3.5
Timing of On-Chip Peripheral Modules
Table 5.26
Timing of On-Chip Peripheral Modules (1)
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Min.
Max.
Unit*1
tPRW
1.5
—
tPcyc
Figure 5.33
tTICW
1.5
—
tPcyc
Figure 5.34
2.5
—
1.5
—
tPcyc
Figure 5.35
2.5
—
2.5
—
tPOEW
1.5
—
tPcyc
Figure 5.36
tTMCWH,
tTMCWL
1.5
—
tPcyc
Figure 5.37
2.5
—
tScyc
4
—
tPcyc
Figure 5.38
6
—
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
—
20
ns
Input clock fall time
tSCKf
—
20
ns
tScyc
16
—
tPcyc
4
—
I/O ports
Input data pulse width
MTU
Input capture input pulse width
Single-edge setting
Timer clock pulse width
Single-edge setting
Both-edge setting
Both-edge setting
tTCKWH,
tTCKWL
Phase counting
mode
POE
POE# input pulse width
8-bit
timer
Timer clock pulse width
SCI
Input clock cycle
Single-edge setting
Both-edge setting
Asynchronous
Clock synchronous
Output clock
cycle*2
Asynchronous
Clock synchronous
Output clock pulse width*2
tSCKW
0.4
0.6
tScyc
Output clock rise time*2
tSCKr
—
20
ns
tSCKf
—
20
ns
tTXD
—
40
ns
—
80
tRXS
40
—
Output clock fall
time*2
Transmit data delay
time*3
Clock
synchronous
2.7 V ≤ VCC ≤ 5.5 V
Receive data setup time
Clock
synchronous
2.7 V ≤ VCC ≤ 5.5 V
Receive data hold time
A/D
converter
Trigger input pulse width
CAC
CACREF input pulse width
1.62 V ≤ VCC < 2.7 V
1.62 V ≤ VCC < 2.7 V
Clock synchronous
tPcyc ≤ tcac*4
C = 30 pF
Figure 5.39
ns
80
—
tRXH
40
—
ns
tTRGW
1.5
—
tPcyc
tCACREF
4.5 tcac + 3 tPcyc
—
ns
tPcyc > tcac*4
Note 1.
Note 2.
Note 3.
Note 4.
Test
Conditions
Symbol
Item
Figure 5.40
5 tcac + 6.5 tPcyc
tPcyc: PCLKB cycle
Value when the drive capacity of clock output ports is set to normal output.
Value when the drive capacity of data output ports is set to normal output.
tcac: CAC count clock source cycle
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Dec 20, 2013
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RX220 Group
Table 5.27
5. Electrical Characteristics
Timing of On-Chip Peripheral Modules (2)
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
RSPI
RSPCK clock cycle*2
Master
Symbol
Min.
Max.
Unit*1
tSPcyc
2
4096
tPcyc
8
4096
tSPCKWH
(tSPcyc – tSPCKr –
tSPCKf)/2 – 3
—
(tSPcyc – tSPCKr –
tSPCKf)/2
—
(tSPcyc – tSPCKr –
tSPCKf)/2 – 3
—
(tSPcyc – tSPCKr –
tSPCKf)/2
—
—
10
—
20
—
1
μs
ns
Slave
RSPCK clock high
pulse width*2
Master
Slave
RSPCK clock low
pulse width*2
Master
tSPCKWL
Slave
RSPCK clock rise/fall
time*2
Output
2.7 V ≤ VCC ≤ 5.5 V
1.62 V ≤ VCC < 2.7 V
tSPCKr,
tSPCKf
Input
Data input setup time
Master
tSU
Slave
Data input hold time
SSL setup time
Master
4
—
20 – tPcyc
—
SSL hold time
ns
ns
ns
tPcyc
—
PCLKB set to
divided by 2
tHF
0
—
Slave
tH
20 + 2 × tPcyc
—
Master
tLEAD
1
8
tSPcyc
4
—
tPcyc
tLAG
Master
Master
2.7 V ≤ VCC ≤ 5.5 V
tOD
ns
1
8
tSPcyc
4
—
tPcyc
—
14
ns
1.62 V ≤ VCC < 2.7 V
—
28
2.7 V ≤ VCC ≤ 5.5 V
—
3 × tPcyc + 40
1.62 V ≤ VCC < 2.7 V
—
3 × tPcyc + 80
0
—
0
—
tSPcyc + 2 × tPcyc
8 × tSPcyc + 2 ×
tPcyc
4 × tPcyc
—
—
10
—
20
—
1
tSSLr,
tSSLf
—
20
ns
—
1
μs
Slave access time
tSA
—
4
tPcyc
Slave output release time
tREL
—
3
tPcyc
Slave
Data output hold time
Master
tOH
Slave
Successive
transmission delay
time
MOSI and MISO rise/
fall time
Master
tTD
Slave
Output
2.7 V ≤ VCC ≤ 5.5 V
tDr, tDf
1.62 V ≤ VCC < 2.7 V
Input
SSL rise/fall time
C = 30 pF
Figure 5.42
to
Figure 5.47
tH
Slave
Data output delay
time
C = 30 pF
Figure 5.41
PCLKB set to a
division ratio other
than divided by 2
Slave
Output
Input
Test
Conditions
ns
ns
ns
μs
C = 30 pF
Figure 5.45
and
Figure 5.47
Note 1. tPcyc: PCLKB cycle
Note 2. Value when the drive capacity of clock output ports is set to normal output.
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RX220 Group
Table 5.28
5. Electrical Characteristics
Timing of On-Chip Peripheral Modules (3)
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
Simple
SPI
SCK clock cycle output
Symbol
(master)*2
tSPcyc
SCK clock cycle input (slave)
Min.
Max.
Unit*1
tPcyc
4
65536
6
65536
SCK clock high pulse width*2
tSPCKWH
0.4
0.6
tSPcyc
SCK clock low pulse width*2
tSPCKWL
0.4
0.6
tSPcyc
tSPCKr, tSPCKf
—
20
ns
ns
SCK clock rise/fall time
Data input setup time
2.7 V ≤ VCC ≤ 5.5 V
tSU
1.62 V ≤ VCC < 2.7 V
40
—
80
—
Data input hold time
tH
40
—
ns
SS input setup time
tLEAD
6
—
tPcyc
SS input hold time
tLAG
6
—
tPcyc
tOD
—
40
ns
Data output delay time
2.7 V ≤ VCC ≤ 5.5 V
1.62 V ≤ VCC < 2.7 V
Data output hold time
Data rise/fall time
SS input rise/fall time
—
80
tOH
0
—
ns
tDr, tDf
—
20
ns
tSSLr, tSSLf
—
20
ns
Slave access time
tSA
—
5
tPcyc
Slave output release time
tREL
—
5
tPcyc
Test Conditions
C = 30 pF
Figure 5.41
C = 30 pF
Figure 5.42 to
Figure 5.47
C = 30 pF
Figure 5.45
and
Figure 5.47
Note 1. tPcyc: PCLKB cycle
Note 2. Value when the drive capacity of clock output ports is set to normal output.
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RX220 Group
Table 5.29
5. Electrical Characteristics
Timing of On-Chip Peripheral Modules (4)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, fPCLKB = up to 32 MHz, Ta = –40 to +105°C
Symbol
Min.*1,*2
Max.
Unit
SCL input cycle time
tSCL
6 (12) × tIICcyc + 1300
—
ns
SCL input high pulse width
tSCLH
3 (6) × tIICcyc + 300
—
ns
SCL input low pulse width
tSCLL
3 (6) × tIICcyc + 300
—
ns
SCL, SDA input rise time
tSr
—
1000
ns
SCL, SDA input fall time
tSf
—
300
ns
SCL, SDA input spike pulse removal time
tSP
0
1 (5) × tIICcyc
ns
SDA input bus free time
tBUF
3 (6) × tIICcyc + 300
—
ns
Start condition input hold time
tSTAH
tIICcyc + 300
—
ns
Restart condition input setup time
tSTAS
1000
—
ns
Stop condition input setup time
tSTOS
1000
—
ns
Data input setup time
tSDAS
tIICcyc + 50
—
ns
Data input hold time
tSDAH
0
—
ns
Item
RIIC
(Standard
mode, SMBus)
SCL, SDA capacitive load
RIIC
(Fast mode)
Cb
—
400
pF
SCL input cycle time
tSCL
6 (12) × tIICcyc + 600
—
ns
SCL input high pulse width
tSCLH
3 (6) × tIICcyc + 300
—
ns
SCL input low pulse width
tSCLL
3 (6) × tIICcyc + 300
—
ns
SCL, SDA input rise time
tSr
20 + 0.1Cb
300
ns
SCL, SDA input fall time
tSf
20 + 0.1Cb
300
ns
SCL, SDA input spike pulse removal time
tSP
0
1 (4) × tIICcyc
ns
SDA input bus free time
tBUF
3 (6) × tIICcyc + 300
—
ns
Start condition input hold time
tSTAH
tIICcyc + 300
—
ns
Restart condition input setup time
tSTAS
300
—
ns
Stop condition input setup time
tSTOS
300
—
ns
Data input setup time
tSDAS
tIICcyc + 50
—
ns
Data input hold time
tSDAH
0
—
ns
Cb
—
400
pF
SCL, SDA capacitive load
Test
Conditions
Figure 5.48
Figure 5.48
Note: • tIICcyc: RIIC internal reference count clock (IICφ) cycle
Note 1. The value in parentheses is used when ICMR3.NF[1:0] are set to 11b while a digital filter is enabled with ICFER.NFE = 1.
Note 2. Cb indicates the total capacity of the bus line.
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RX220 Group
Table 5.30
5. Electrical Characteristics
Timing of On-Chip Peripheral Modules (5)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, fPCLKB = up to 32 MHz, Ta = –40 to +105°C
Symbol
Min.*1
Max.
SDA input rise time
tSr
—
1000
ns
SDA input fall time
tSf
—
300
ns
SDA input spike pulse removal time
tSP
0
4 × tPcyc*2
ns
Data input setup time
tSDAS
250
—
ns
Data input hold time
tSDAH
0
—
ns
Item
Simple IIC
(Standard mode)
Simple IIC
(Fast mode)
Unit Test Conditions
SCL, SDA capacitive load
Cb
—
400
pF
SCL, SDA input rise time
tSr
20 + 0.1Cb
300
ns
SCL, SDA input fall time
tSf
20 + 0.1Cb
300
SCL, SDA input spike pulse removal time
tSP
0
tSDAS
100
—
ns
Data input hold time
tSDAH
0
—
ns
Cb
—
400
pF
SCL, SDA capacitive load
Figure 5.48
ns
*2
Data input setup time
4 × tPcyc
Figure 5.48
ns
Note: • tPcyc: PCLKB cycle
Note 1. Cb indicates the total capacity of the bus line.
Note 2. This applies when the SMR.CKS[1:0] bits = 00b and the SNFR.NFCS[2:0] bits = 010b while the SNFR.NFE bit = 1 and the digital
filter is enabled.
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RX220 Group
5. Electrical Characteristics
PCLK
Port
tPRW
Figure 5.33
I/O Port Input Timing
PCLK
Output
compare output
Input capture
input
Figure 5.34
tTICW
MTU Input/Output Timing
PCLK
MTCLKA to
MTCLKD
tTCKWL
Figure 5.35
tTCKWH
MTU Clock Input Timing
PCLK
POEn# input
tPOEW
Figure 5.36
POE# Input Timing
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Dec 20, 2013
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RX220 Group
5. Electrical Characteristics
PCLK
TMCI0 to TMCI3
tTMCWL
Figure 5.37
tTMCWH
8-Bit Timer Clock Input Timing
tSCKW
tSCKr
tSCKf
SCKn
(n = 1, 5, 6, 9, 12)
tScyc
Figure 5.38
SCK Clock Input Timing
SCKn
tTXD
TXDn
tRXS tRXH
RXDn
n = 1, 5, 6, 9, 12
Figure 5.39
SCI Input/Output Timing: Clock Synchronous Mode
PCLK
ADTRG0#
tTRGW
Figure 5.40
A/D Converter External Trigger Input Timing
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Dec 20, 2013
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RX220 Group
5. Electrical Characteristics
RSPI
Simple SPI
RSPCKA
Master select output
SCKn
Master select output
tSPCKr
tSPCKWH
VOH
VOH
VOL
tSPCKf
VOH
VOH
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
VIH
RSPCKA
Slave select input
SCKn
Slave select input
VIH
VIL
(n = 1, 5, 6, 9, 12)
tSPCKf
VIH
VIL
tSPCKWL
VIH
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Figure 5.41
RSPI Clock Timing and Simple SPI Clock Timing
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Dec 20, 2013
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RX220 Group
RSPI
5. Electrical Characteristics
Simple SPI
tTD
SSLA0 to
SSLA3
output
tLEAD
RSPCKA
CPOL = 0
output
SCKn
CKPOL = 0
output
RSPCKA
CPOL = 1
output
SCKn
CKPOL = 1
output
tLAG
tSSLr, tSSLf
tSU
MISOA
input
SMISOn
input
tH
MSB IN
DATA
tDr, tDf
MOSIA
output
SMOSIn
output
LSB IN
tOH
MSB OUT
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
(n = 1, 5, 6, 9, 12)
Figure 5.42
RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKB Set to Division Ratio Other Than
Divided by 2) and Simple SPI Timing (Master, CKPH = 1)
tTD
SSLA0 to
SSLA3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
tSU
tHF
MISOA
input
MSB IN
tDr, tDf
MOSIA
output
Figure 5.43
tHF
tOH
MSB OUT
LSB IN
DATA
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKB Set to Divided by 2)
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Dec 20, 2013
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RX220 Group
RSPI
5. Electrical Characteristics
Simple SPI
tTD
SSLA0 to
SSLA3
output
tLEAD
RSPCKA
CPOL = 0
output
SCKn
CKPOL = 0
output
RSPCKA
CPOL = 1
output
SCKn
CKPOL = 1
output
tLAG
tSSLr, tSSLf
tSU
MISOA
input
SMISOn
input
tH
MSB IN
DATA
tOH
MOSIA
output
SMOSIn
output
LSB IN
tOD
MSB OUT
MSB IN
tDr, tDf
DATA
LSB OUT
IDLE
MSB OUT
(n = 1, 5, 6, 9, 12)
Figure 5.44
RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKB Set to Division Ratio Other Than
Divided by 2) and Simple SPI Timing (Master, CKPH = 0)
tTD
SSLA0 to
SSLA3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
tSU
MISOA
input
tHF
MSB IN
tOH
MOSIA
output
Figure 5.45
tH
DATA
LSB IN
tOD
MSB OUT
MSB IN
tDr, tDf
DATA
LSB OUT
IDLE
MSB OUT
RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKB Set to Divided by 2)
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Dec 20, 2013
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RX220 Group
RSPI
5. Electrical Characteristics
SimpleSPI
tTD
SSLA0
input
SSn#
input
tLEAD
RSPCKA
CPOL = 0
input
SCKn
CKPOL = 0
input
RSPCKA
CPOL = 1
input
SCKn
CKPOL = 1
input
tLAG
tSA
MISOA
output
tOH
SMISOn
output
MSB OUT
tSU
MOSIA
input
tOD
SMOSIn
input
DATA
tREL
LSB OUT
tH
MSB IN
MSB OUT
tDr, tDf
MSB IN
DATA
LSB IN
MSB IN
(n = 1, 5, 6, 9, 12)
Figure 5.46
RSPI Timing (Slave, CPHA = 0) and Simple SPI Timing (Slave, CKPH = 1)
RSPI
Simple SPI
SSLA0
input
SSn#
input
tTD
tLEAD
RSPCKA
CPOL = 0
input
SCKn
CKPOL = 1
input
RSPCKA
CPOL = 1
input
SCKn
CKPOL = 0
input
MISOA
output
SMISOn
output
tSA
tLAG
tOH
tOD
LSB OUT
(Last data)
MSB OUT
tSU
MOSIA
input
SMOSIn
input
tREL
DATA
tH
MSB IN
LSB OUT
MSB OUT
tDr, tDf
DATA
LSB IN
MSB IN
(n = 1, 5, 6, 9, 12)
Figure 5.47
RSPI Timing (Slave, CPHA = 1) and Simple SPI Timing (Slave, CKPH = 0)
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Dec 20, 2013
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RX220 Group
5. Electrical Characteristics
VIH
SDA
VIL
tBUF
tSCLH
tSTAS
tSTAH
tSTOS
tSP
SCL
P*1
S*1
tSCLL
tSr
tSf
tSCL
tSDAS
tSDAH
Note 1. S, P, and Sr indicate the following conditions, respectively.
S : Start condition
P : Stop condition
Sr : Restart condition
Figure 5.48
P*1
Sr*1
Test conditions
VIH = VCC × 0.7, VIL = VCC × 0.3
RIIC Bus Interface Input/Output Timing and Simple IIC Bus Interface Input/Output
Timing
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Dec 20, 2013
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RX220 Group
5.4
5. Electrical Characteristics
A/D Conversion Characteristics
Table 5.31
A/D Conversion Characteristics (1)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, 2.7 ≤ VREFH0 ≤ 5.5 V, AVCC0 – 0.9 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
A/D conversion clock frequency (fPCLKD)
Resolution
Conversion time*1
(Operation at
fPCLKD = 32 MHz)
Min.
Typ.
Max.
Unit
1
—
32
MHz
—
—
12
Bit
Permissible signal source
impedance (Max.) = 1 kΩ
1.56
(0.652)*2
—
—
µs
Permissible signal source
impedance (Max.) = 5 kΩ
3.29
(2.35)*2
—
—
—
—
30
pF
Offset error
—
±0.5
±4.5
LSB
±7.5
—
±0.75
Sampling in 20 states
Sampling in 75 states
Analog input capacitance
Full-scale error
Test Conditions
High-precision channel
Normal-precision channel
±4.5
LSB
±7.5
High-precision channel
Normal-precision channel
Quantization error
—
±0.5
—
LSB
Absolute accuracy
—
±1.25
±5.0
LSB
High-precision channel
—
±1.25
±8.0
LSB
Normal-precision channel
DNL differential nonlinearity error
—
±1.0
—
LSB
INL integral nonlinearity error
—
±1.0
±3.0
LSB
High-precision channel
—
±1.0
±5.0
LSB
Normal-precision channel
Note: • The characteristics apply when no pin functions other than A/D converter input are used. Absolute accuracy includes
quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not
include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. As the test conditions, the number of sampling
states is indicated.
Note 2. The value in parentheses indicates the sampling time.
Table 5.32
Channel Classification for A/D Converter
Classification
Channel
High-precision channel
AN000 to AN007
Normal-precision channel
AN008 to AN015
Table 5.33
It is disallowed to use pins AN000 to
AN007 as digital outputs when the A/D
converter is used.
A/D Internal Reference Voltage Characteristics
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = 40 to +105
Item
A/D internal reference voltage
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Min.
Typ.
Max.
Unit
1.35
1.50
1.65
V
Test Conditions
Page 85 of 105
RX220 Group
Table 5.34
5. Electrical Characteristics
A/D Conversion Characteristics (2)
Conditions: VCC = AVCC0 = 1.62 to 3.6 V, 1.62 ≤ VREFH0 ≤ 2.7 V, AVCC0 – 0.9 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
Min.
Typ.
Max.
Unit
1
—
8
MHz
A/D conversion clock frequency (fPCLKD)
Resolution
Conversion time*1
(Operation at
fPCLKD = 8 MHz)
—
—
12
Bit
Permissible signal source
impedance (Max.) = 1 kΩ
5.25
(1.5)*2
—
—
µs
Permissible signal source
impedance (Max.) = 5 kΩ
6.25
(2.5)*2
—
—
Test Conditions
Sampling in 12 states
Sampling in 20 states
Analog input capacitance
—
—
30
pF
Offset error
—
±0.5
±7.5
LSB
Full-scale error
—
±1.25
±7.5
LSB
Quantization error
—
±0.5
—
LSB
Absolute accuracy
—
±3.0
±8.0
LSB
DNL differential nonlinearity error
—
±1.25
—
LSB
INL integral nonlinearity error
—
±1.5
±5.0
LSB
Note: • The characteristics apply when no pin functions other than A/D converter input are used. Absolute accuracy includes
quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not
include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. As the test conditions, the number of sampling
states is indicated.
Note 2. The value in parentheses indicates the sampling time.
Table 5.35
Sampling Time
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
Sampling time
High-precision channel
Symbol
Typ.
Unit
Ts
0.208 + 0.417 × R0 (kΩ)
µs
Test Conditions
Figure 5.49
Normal-precision channel
RX220
R0
ANi
Figure 5.49
Internal Equivalent Circuit of Analog Input Pin
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Page 86 of 105
RX220 Group
5. Electrical Characteristics
FFFh
Full-scale error
Integral nonlinearity
error (INL)
A/D converter
output code
Ideal line of actual A/D
conversion characteristic
Actual A/D conversion
characteristic
Ideal A/D conversion
characteristic
Differential nonlinearity error (DNL)
1-LSB width for ideal A/D
conversion characteristic
Differential nonlinearity error (DNL)
1-LSB width for ideal A/D
conversion characteristic
Absolute accuracy
000h
Offset error
0
Figure 5.50
Analog input voltage
VREFH0
(full-scale)
Illustration of A/D Converter Characteristic Terms
Absolute accuracy
Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the
actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of analog
input voltage (1-LSB width), that can meet the expectation of outputting an equal code based on the theoretical A/D
conversion characteristics, is used as an analog input voltage. For example, if 12-bit resolution is used and if reference
voltage (VREFH0) = 5.12 V, then 1-LSB width becomes 1.25 mV, and 0 mV, 1.25 mV, 2.5 mV, ... are used as analog
input voltages.
If analog input voltage is 10 mV, absolute accuracy = ±5 LSB means that the actual A/D conversion result is in the range
of 003h to 00Dh though an output code, 008h, can be expected from the theoretical A/D conversion characteristics.
Integral nonlinearity error (INL)
Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale
errors are zeroed, and the actual output code.
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 87 of 105
RX220 Group
5. Electrical Characteristics
Differential nonlinearity error (DNL)
Differential nonlinearity error is the difference between 1-LSB width based on the ideal A/D conversion characteristics
and the width of the actually output code.
Offset error
Offset error is the difference between a transition point of the ideal first output code and the actual first output code.
Full-scale error
Full-scale error is the difference between a transition point of the ideal last output code and the actual last output code.
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 88 of 105
RX220 Group
5.5
5. Electrical Characteristics
Comparator Characteristics
Table 5.36
Comparator Characteristics
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
Comparator A
Symbol
Min.
Typ.
Max.
Unit
External standard voltage input
range
LVREF
1.4
―
VCC
V
External comparison voltage*1
(CMPA1, CMPA2) input range
VI
–0.3
―
VCC + 0.3
V
Offset
―
―
±50
±150
mV
Comparator output delay time*2
―
―
3
―
µs
At falling edge
VI = LVREF – 110 mV
―
2
―
µs
At falling edge
VI < LVREF – 1 V
―
3
―
µs
At rising edge
VI = LVREF + 160 mV
―
1.5
―
µs
At rising edge
VI > LVREF + 1 V
―
0.5
―
µA
VCC = 5.0 V
Comparator operating current
ICMPA
Test Conditions
Note 1. VCC does not include ripple.
Note 2. When the digital filter is disabled.
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 89 of 105
RX220 Group
5.6
5. Electrical Characteristics
Power-on Reset Circuit and Voltage Detection Circuit Characteristics
Table 5.37
Power-on Reset Circuit and Voltage Detection Circuit Characteristics (1)
Conditions: VCC = AVCC, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
Voltage detection
level
Power-on reset
(POR)
Low power
consumption
function disabled*1
Symbol
Min.
Typ.
Max.
Unit
VPOR
1.30
1.40
1.55
V
Figure 5.51 and
Figure 5.52
1.00
1.20
1.45
V
Figure 5.53
V
Figure 5.54
Low power
consumption
function enabled*2
Voltage detection circuit (LVD0)*3
Voltage detection circuit (LVD1)*4
Vdet0_0
3.65
3.80
3.95
Vdet0_1
2.70
2.80
2.90
Vdet0_2
1.80
1.90
2.00
Vdet0_3
1.62
1.72
1.82
Vdet1_0
4.00
4.15
4.30
Vdet1_1
3.85
4.00
4.15
Vdet1_2
3.70
3.85
4.00
Vdet1_3
3.55
3.70
3.85
Vdet1_4
3.40
3.55
3.70
Vdet1_5
3.25
3.40
3.55
Vdet1_6
3.10
3.25
3.40
Vdet1_7
2.95
3.10
3.25
Vdet1_8
2.85
2.95
3.05
Vdet1_9
2.70
2.80
2.90
Vdet1_A
2.55
2.65
2.75
Vdet1_B
2.40
2.50
2.60
Vdet1_C
2.25
2.35
2.45
Vdet1_D
2.10
2.20
2.30
Vdet1_E
1.95
2.05
2.15
Vdet1_F
1.80
1.90
2.00
Test Conditions
At falling edge
VCC
Note: • These characteristics apply when noise is not superimposed on the power supply.
Note 1. When the CPU is in a mode other than software standby mode, when the CPU transits to software standby mode with the
FHSSBYCR.SOFTCUT[2] bit set to 0.
Note 2. When the CPU transits to software standby mode with the FHSSBYCR.SOFTCUT[2] bit set to 1.
Note 3. # in the symbol Vdet0_# denotes the value of the OFS1.VDSEL[1:0] bits.
Note 4. # in the symbol Vdet1_# denotes the value of the LVDLVLR.LVD1LVL[3:0] bits.
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 90 of 105
RX220 Group
Table 5.38
5. Electrical Characteristics
Power-on Reset Circuit and Voltage Detection Circuit Characteristics (2)
Conditions: VCC = AVCC0, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
Voltage detection
level
Internal reset time
Voltage detection circuit
(LVD2)*1
Symbol
Min.
Typ.
Max.
Unit
V
Vdet2_0
4.00
4.15
4.30
Vdet2_1
3.85
4.00
4.15
Vdet2_2
3.70
3.85
4.00
Vdet2_3
3.55
3.70
3.85
Vdet2_4
3.40
3.55
3.70
Vdet2_5
3.25
3.40
3.55
Vdet2_6
3.10
3.25
3.40
Vdet2_7
2.95
3.10
3.25
Vdet2_8
2.85
2.95
3.05
Vdet2_9
2.70
2.80
2.90
Vdet2_A
2.55
2.65
2.75
Test Conditions
Figure 5.55
At falling edge VCC
Vdet2_B
2.40
2.50
2.60
Vdet2_C
2.25
2.35
2.45
Vdet2_D
2.10
2.20
2.30
Vdet2_E
1.95
2.05
2.15
Vdet2_F
1.80
1.90
2.00
VCMPA2
1.18
1.33
1.48
Power-on reset time
tPOR
—
9
—
Voltage monitoring 0 reset time
tLVD0
—
9
—
Figure 5.53
Voltage monitoring 1 reset time
tLVD1
—
1.4
—
Figure 5.54
Voltage monitoring 2 reset time
Minimum VCC down time*2
tLVD2
—
1.4
—
tVOFF
200
—
—
EXVCCINP2 = 1
ms
Figure 5.52
Figure 5.55
µs
Figure 5.51
tdet
—
—
200
µs
Figure 5.52
LVD operation stabilization time (after LVD is enabled)
Td(E-A)
—
—
15
µs
Figure 5.54 and
Figure 5.55
Power-on reset enable time
tW(POR)
1
—
—
ms
Figure 5.52
VCC = 0.9 V or lower
V LVH
—
100
—
mV
When selection is from
among VdetX_0 to 7.
—
50
—
Response delay time
Hysteresis width (LVD1 and LVD2)
When selection is from
among VdetX_8 to F.
Note: • These characteristics apply when noise is not superimposed on the power supply.
Note 1. # in the symbol Vdet2_# denotes the value of the LVDLVLR.LVD2LVL[3:0] bits.
Note 2. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet0,
Vdet1, and Vdet2 for the POR/ LVD.
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 91 of 105
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5. Electrical Characteristics
tVOFF
VCC
VPOR
Internal reset signal
(active-low)
tdet
Figure 5.51
tdet
tPOR
Voltage Detection Reset Timing
VPOR
VCC
0.9 V
tw(por)
Internal reset signal
(active-low)
*1
tdet
tPOR
Note 1. tw(por) is the time required for a power-on reset to be enabled while the external power VCC is being held below the
valid voltage (0.9 V).
When VCC turns on, maintain tw(por) for 1 ms or more.
Figure 5.52
Power-on Reset Timing
tVOFF
VCC
Vdet0
VPOR
Internal reset signal
(active-low)
tdet
Figure 5.53
tdet
tLVD0
Voltage Detection Circuit Timing (Vdet0)
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 92 of 105
RX220 Group
5. Electrical Characteristics
tVOFF
VCC
VLVH
Vdet1
LVD1E
Td(E-A)
LVD1
Comparator output
LVD1CMPE
LVD1MON
Internal reset signal
(active-low)
When LVD1RN = L
tdet
tdet
tLVD1
When LVD1RN = H
tLVD1
Figure 5.54
Voltage Detection Circuit Timing (Vdet1)
tVOFF
VCC
VLVH
Vdet2
LVD2E
Td(E-A)
LVD2
Comparator output
LVD2CMPE
LVD2MON
Internal reset signal
(active-low)
When LVD2RN = L
tdet
tdet
tLVD2
When LVD2RN = H
tLVD2
Figure 5.55
Voltage Detection Circuit Timing (Vdet2)
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 93 of 105
RX220 Group
5.7
5. Electrical Characteristics
Oscillation Stop Detection Timing
Table 5.39
Oscillation Stop Detection Circuit Characteristics
Conditions: VCC = AVCC0 = 1.62 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
Detection time
Symbol
Min.
Typ.
Max.
Unit
tdr
—
—
1
ms
Test
Conditions
Figure 5.56
Main clock
tdr
OSTDSR.OSTDF
LOCO clock
ICLK
Figure 5.56
Oscillation Stop Detection Timing
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 94 of 105
RX220 Group
5.8
5. Electrical Characteristics
ROM (Flash Memory for Code Storage) Characteristics
Table 5.40
ROM (Flash Memory for Code Storage) Characteristics (1)
Item
Symbol
Min.
cycle*1
NPEC
10000
After 1000 times
of NPEC
tDRP
30*2
1*2
—
Reprogramming/erasure
Data hold time
After 10000 times
of NPEC
Typ.
Max.
Unit
—
—
Times
—
—
Year
—
Year
Conditions
Ta = +85°C
Note 1. Definition of reprogram/erase cycle: The reprogram/erase cycle is the number of erasing for each block. When the reprogram/
erase cycle is n times (n = 10000), erasing can be performed n times for each block. For instance, when 128-byte programming
is performed 16 times for different addresses in 2-Kbyte block and then the entire block is erased, the reprogram/erase cycle is
counted as one. However, programming the same address for several times as one erasing is not enabled (overwriting is
prohibited).
Note 2. This result is obtained from reliability testing.
Table 5.41
ROM (Flash Memory for Code Storage) Characteristics (2)
Item
Peripheral clock notification command
wait time
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Symbol
tPCKA
FCLK = 4 MHz
FCLK = 32 MHz
Min.
Typ.
Max.
Min.
Typ.
Max.
—
—
960
—
—
120
Unit
µs
Page 95 of 105
RX220 Group
Table 5.42
5. Electrical Characteristics
ROM (Flash Memory for Code Storage) Characteristics (3)
medium-speed operating mode 1A
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V
Temperature range for the programming/erasure operation: Ta = –40 to +105°C
Item
Symbol
FCLK = 4 MHz
FCLK = 32 MHz
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Programming time
when NPEC ≤ 100 times
2 bytes
tP2
—
0.19
4.3
—
0.12
2.0
8 bytes
tP8
—
0.19
4.4
—
0.12
2.0
tP128
—
0.67
10.7
—
0.41
4.8
Programming time
when NPEC > 100 times
2 bytes
tP2
—
0.23
5.3
—
0.15
2.5
8 bytes
tP8
—
0.23
5.4
—
0.15
2.5
128 bytes
tP128
—
0.80
13.2
—
0.48
6.0
Erasure time
when NPEC ≤ 100 times
2 Kbytes
tE2K
—
13.0
92.8
—
10.5
29
ms
Erasure time
when NPEC > 100 times
2 Kbytes
tE2K
—
15.9
176.9
—
12.8
60
ms
Suspend delay time during programming
(in programming/erasure priority mode)
tSPD
—
—
0.9
—
—
0.8
ms
First suspend delay time during
programming (in suspend priority mode)
tSPSD1
—
—
220
—
—
120
μs
Second suspend delay time during
programming (in suspend priority mode)
tSPSD2
—
—
0.9
—
—
0.8
ms
Suspend delay time during erasing
(in programming/erasure priority mode)
tSED
—
—
0.9
—
—
0.8
ms
First suspend delay time during erasing
(in suspend priority mode)
tSESD1
—
—
220
—
—
120
μs
Second suspend delay time during erasing
(in suspend priority mode)
tSESD2
—
—
0.9
—
—
0.8
ms
FCU reset time
tFCUR
20 μs or longer
and FCLK × 6
or greater
—
—
20 μs or longer
and FCLK × 6
or greater
—
—
μs
128 bytes
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
ms
ms
Page 96 of 105
RX220 Group
Table 5.43
5. Electrical Characteristics
ROM (Flash Memory for Code Storage) Characteristics (4)
medium-speed operating mode 1B
Conditions: VCC = AVCC0 = 1.62 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V
Temperature range for the programming/erasure operation: Ta = –40 to +105°C
Item
Symbol
FCLK = 32 MHz*1
FCLK = 4 MHz
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Programming time
when NPEC ≤ 100 times
2 bytes
tP2
—
0.25
5.0
—
0.21
2.8
8 bytes
tP8
—
0.25
5.3
—
0.21
3.0
tP128
—
0.92
14.0
—
0.65
8.3
Programming time
when NPEC > 100 times
2 bytes
tP2
—
0.31
6.2
—
0.26
3.5
8 bytes
tP8
—
0.31
6.6
—
0.26
3.7
128 bytes
tP128
—
1.09
17.5
—
0.77
10.0
Erasure time
when NPEC ≤ 100 times
2 Kbytes
tE2K
—
21.0
113.6
—
18.5
46
ms
Erasure time
when NPEC > 100 times
2 Kbytes
tE2K
—
25.6
220.6
—
22.5
90 (1000 times ≥
NPEC > 100 times),
98 (10000 times ≥
NPEC > 1000 times)
ms
Suspend delay time during programming
(in programming/erasure priority mode)
tSPD
—
—
1.7
—
—
1.6
ms
First suspend delay time during
programming (in suspend priority mode)
tSPSD1
—
—
220
—
—
120
μs
Second suspend delay time during
programming (in suspend priority mode)
tSPSD2
—
—
1.7
—
—
1.6
ms
Suspend delay time during erasing
(in programming/erasure priority mode)
tSED
—
—
1.7
—
—
1.6
ms
First suspend delay time during erasing
(in suspend priority mode)
tSESD1
—
—
220
—
—
120
μs
Second suspend delay time during
erasing (in suspend priority mode)
tSESD2
—
—
1.7
—
—
1.6
ms
FCU reset time
tFCUR
20 μs or
longer and
FCLK × 6
or greater
—
—
20 μs or
longer and
FCLK × 6
or greater
—
—
μs
128 bytes
ms
ms
Note 1. The operating frequency is 8 MHz (max.) when the voltage is in the range from 1.62 V to less than 2.7 V.
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 97 of 105
RX220 Group
5.9
5. Electrical Characteristics
E2 DataFlash (Flash Memory for Data Storage) Characteristics
Table 5.44
E2 DataFlash Characteristics (1)
Item
Symbol
Min.
cycle*1
NDPEC
100000
After 100000
times of NDPEC
tDRP
30*2
Reprogramming/erasure
Data hold time
Typ.
Max.
Unit
—
—
Times
—
—
Year
Test Conditions
Ta = +85°C
Note 1. The reprogram/erase cycle is the number of erasing for each block. When the reprogram/erase cycle is n times (n = 100000),
erasing can be performed n times for each block. For instance, when 8-byte programming is performed 16 times for different
addresses in 128-byte block and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address for several times as one erasing is not enabled (overwriting is prohibited).
Note 2. This result is obtained from reliability testing.
Table 5.45
E2 DataFlash Characteristics (2)
Item
Symbol
Peripheral clock notification command wait
time
Table 5.46
tPCKA
FCLK = 4 MHz
FCLK = 32 MHz
Min.
Typ.
Max.
Min.
Typ.
Max.
—
—
960
—
—
120
Unit
μs
E2 DataFlash Characteristics (3)
medium-speed operating mode 1A
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = AVCC0, VSS = AVSS0 = VREFL0 = 0 V
Temperature range for the programming/erasure operation: Ta = –40 to +105°C
Item
Symbol
FCLK = 4 MHz
FCLK = 32 MHz
Min.
Typ.
Max.
Min.
Typ.
Max.
tDP2
—
0.19
4.4
—
0.13
2.0
Unit
Programming time
when NDPEC ≤ 100 times
2 bytes
8 bytes
tDP8
—
0.24
5.1
—
0.13
2.2
Programming time
when NDPEC > 100 times
2 bytes
tDP2
—
0.25
6.4
—
0.17
3.0
8 bytes
tDP8
—
0.32
7.5
—
0.18
3.2
Erasure time
when NDPEC ≤ 100 times
128 bytes
tDE128
—
3.3
27.1
—
2.5
8
ms
Erasure time
when NDPEC > 100 times
128 bytes
tDE128
—
4.0
45.1
—
3.0
12
ms
Blank check time
2 bytes
tDBC2
—
—
98
—
—
35
μs
2 Kbytes
tDBC2K
—
—
16
—
—
2.5
ms
Suspend delay time during programming
(in programming/erasure priority mode)
tDSPD
—
—
0.9
—
—
0.8
ms
First suspend delay time during
programming (in suspend priority mode)
tDSPSD1
—
—
220
—
—
120
μs
Second suspend delay time during
programming (in suspend priority mode)
tDSPSD2
—
—
0.9
—
—
0.8
ms
Suspend delay time during erasing
(in programming/erasure priority mode)
tDSED
—
—
0.9
—
—
0.8
ms
First suspend delay time during erasing
(in suspend priority mode)
tDSESD1
—
—
220
—
—
120
μs
Second suspend delay time during erasing
(in suspend priority mode)
tDSESD2
—
—
0.9
—
—
0.8
ms
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
ms
ms
Page 98 of 105
RX220 Group
Table 5.47
5. Electrical Characteristics
E2 DataFlash Characteristics (4)
medium-speed operating mode 1B
Conditions: VCC = AVCC0 = 1.62 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V
Temperature range for the programming/erasure operation: Ta = –40 to +105°C
Item
Symbol
FCLK = 32 MHz*1
FCLK = 4 MHz
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Programming time
when NDPEC ≤ 100 times
2 bytes
tDP2
—
0.28
5.1
—
0.20
2.8
8 bytes
tDP8
—
0.32
6.0
—
0.22
3.2
Programming time
when NDPEC > 100 times
2 bytes
tDP2
—
0.36
7.6
—
0.25
4.2
8 bytes
tDP8
—
0.40
8.8
—
0.28
4.5
Erasure time
when NDPEC ≤ 100 times
128 bytes
tDE128
—
4.8
32.3
—
4.1
12
ms
Erasure time
when NDPEC > 100 times
128 bytes
tDE128
—
5.8
51.4
—
4.9
17
ms
Blank check time
2 bytes
tDBC2
—
—
110
—
—
40
μs
ms
ms
2 Kbytes
tDBC2K
—
—
16.3
—
—
2.6
ms
Suspend delay time during programming
(in programming/erasure priority mode)
tDSPD
—
—
1.7
—
—
1.6
ms
First suspend delay time during
programming (in suspend priority mode)
tDSPSD1
—
—
220
—
—
120
μs
Second suspend delay time during
programming (in suspend priority mode)
tDSPSD2
—
—
1.7
—
—
1.6
ms
Suspend delay time during erasing
(in programming/erasure priority mode)
tDSED
—
—
1.7
—
—
1.6
ms
First suspend delay time during erasing
(in suspend priority mode)
tDSESD1
—
—
220
—
—
120
μs
Second suspend delay time during erasing
(in suspend priority mode)
tDSESD2
—
—
1.7
—
—
1.6
ms
Note 1. The operating frequency is 8 MHz (max.) when the voltage is in the range from 1.62 V to less than 2.7 V.
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 99 of 105
RX220 Group
5. Electrical Characteristics
In suspend priority mode
• Suspension during programming
FCU command
Program
Suspend
Resume
Suspend
Resume
tSPSD1
FSTATR0.FRDY
Ready
Programming pulse
Suspend
tSPSD2
Resume
tSPSD1
Not Ready
Not Ready
Not Ready
Programming
Programming
Programming
Application of the pulse stops
Application of the pulse continues
• Suspension during erasure
FCU command
Erase
Suspend
Resume
Suspend
Resume
tSESD1
FSTATR0.FRDY
Ready
Erasure pulse
Suspend
tSESD2
Resume
tSESD1
Not Ready
Not Ready
Not Ready
Erasing
Erasing
Erasing
Application of the pulse stops
Application of the pulse continues
In programming/erasure priority mode
• Suspension during programming
FCU command
Program
Suspend
tSPD
FSTATR0.FRDY
Ready
Programming pulse
Not Ready
Ready
Programming
• Suspension during erasure
FCU command
Erase
Suspend
tSED
FSTATR0.FRDY
Erasure pulse
Figure 5.57
Ready
Not Ready
Ready
Erasing
Flash Memory Program/Erase Suspend Timing
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 100 of 105
RX220 Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
Information on the latest version of the package dimensions or mountings has been displayed in “Packages” on Renesas
Electronics Corporation. website.
JEITA Package Code
P-LFQFP100-14x14-0.50
RENESAS Code
PLQP0100KB-A
Previous Code
100P6Q-A / FP-100U / FP-100UV
MASS[Typ.]
0.6g
HD
*1
D
51
75
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
50
76
bp
c1
Reference Dimension in Millimeters
Symbol
c
E
*2
HE
b1
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
100
26
1
ZE
Terminal cross section
25
Index mark
ZD
F
y S
e
*3
bp
A1
c
A
A2
S
L
x
L1
Detail F
Figure A
e
x
y
ZD
ZE
L
L1
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.08
1.0
1.0
0.35 0.5 0.65
1.0
100-Pin LQFP (PLQP0100KB-A)
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 101 of 105
RX220 Group
Appendix 1. Package Dimensions
JEITA Package Code
P-LFQFP64-10x10-0.50
RENESAS Code
PLQP0064KB-A
Previous Code
64P6Q-A / FP-64K / FP-64KV
MASS[Typ.]
0.3g
HD
*1
D
48
33
49
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
32
bp
64
1
c1
Terminal cross section
ZE
17
Reference
Symbol
c
E
*2
HE
b1
16
Index mark
ZD
c
A
*3
A1
y S
e
A2
F
S
bp
L
x
L1
Detail F
Figure B
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
9.9 10.0 10.1
9.9 10.0 10.1
1.4
11.8 12.0 12.2
11.8 12.0 12.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.08
1.25
1.25
0.35 0.5 0.65
1.0
64-Pin LQFP (PLQP0064KB-A)
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 102 of 105
RX220 Group
Appendix 1. Package Dimensions
JEITA Package Code
P-LQFP64-14x14-0.80
RENESAS Code
PLQP0064GA-A
Previous Code
64P6U-A/ ⎯
MASS[Typ.]
0.7g
HD
*1
D
33
48
49
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
32
bp
c
Reference Dimension in Millimeters
Symbol
*2
E
HE
c1
b1
ZE
Terminal cross section
64
17
c
Index mark
A2
16
ZD
A
1
F
A1
S
L
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
L1
y S
e
Figure C
Detail F
*3
bp
x
e
x
y
ZD
ZE
L
L1
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.1 0.2
0
0.32 0.37 0.42
0.35
0.09 0.145 0.20
0.125
0°
8°
0.8
0.20
0.10
1.0
1.0
0.3 0.5 0.7
1.0
64-Pin LQFP (PLQP0064GA-A)
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 103 of 105
RX220 Group
Appendix 1. Package Dimensions
JEITA Package Code
P-LFQFP48-7x7-0.50
RENESAS Code
PLQP0048KB-A
Previous Code
48P6Q-A
MASS[Typ.]
0.2g
HD
*1
D
36
25
37
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
24
bp
c
c1
*2
E
HE
b1
Reference Dimension in Millimeters
Symbol
48
13
1
ZE
Terminal cross section
12
c
A
F
A2
Index mark
ZD
S
A1
L
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
e
Figure D
*3
bp
Detail F
x
8.8
8.8
0
0.17
0.09
0°
L1
y S
Min
6.9
6.9
e
x
y
ZD
ZE
L
L1
0.35
Nom Max
7.0 7.1
7.0 7.1
1.4
9.0 9.2
9.0 9.2
1.7
0.1 0.2
0.22 0.27
0.20
0.145 0.20
0.125
8°
0.5
0.08
0.10
0.75
0.75
0.5 0.65
1.0
48-Pin LQFP (PLQP0048KB-A)
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 104 of 105
REVISION HISTORY
RX220 Group
REVISION HISTORY
REVISION HISTORY
Rev.
0.51
1.00
1.10
RX220 Group Datasheet
Description
Summary
Date
Page
May 24, 2012
—
Dec 25, 2012 Feature
1
Dec 20, 2013
First edition, issued
IrDA, added
Low-power design and architecture, Real-time clock, Up to seven communications channels,
Operating temp. range, changed
1. Overview
3, 4
Table 1.1 Outline of Specifications:
General I/O ports, Event link controller (ELC),
Realtime clock (RTCc), Serial communications interfaces (SCIe, SCIf), IrDA, Power supply voltage/
Operating frequency, Supply current, Operating temperature, changed
5
Table 1.2 Comparison of Functions for Different Packages, changed
6
Table 1.3 List of Products, changed
Note 1, added
7
Figure 1.1 How to Read the Product Part No., Memory Capacity, and Package Type, changed
8
Figure 1.2 Block Diagram, changed
9, 10
Table 1.4 Pin Functions:
Power supply, On-chip emulator, Serial communications interface (SCIe), changed
13
Figure 1.4 Pin Assignments of the 64-Pin LQFP,
Figure 1.5 Pin Assignments of the 48-Pin LQFP, changed
14, 15
Table 1.5 List of Pins and Pin Functions (100-Pin LQFP), chaned
17
Table 1.6 List of Pins and Pin Functions (64-Pin LQFP), chaned
19
Table 1.7 List of Pins and Pin Functions (48-Pin LQFP), chaned
4. I/O Registers
32 to 46 Table 4.1 List of I/O Registers, changed
Notes 1 and 2, added
5. Electrical Characteristics
47 to 99 Added
All
PLQP0064GA-A 14×14 mm, 0.8-mm pitch added
Features
1
■ Operating temp. range changed
1. Overview
4
Table 1.1 Outline of Specifications changed, Note 1 added
6
Table 1.3 List of Products changed, Note added
7
Figure 1.1 How to Read the Product Part No., Memory Capacity, and Package Type changed
5. Electrical Characteristics
49
Table 5.4 DC Characteristics (3) changed
55
Table 5.8 DC Characteristics (7) added
56
Table 5.13 Permissible Output Currents (1) changed, Table 5.14 Permissible Output Currents (2)
added
57
Table 5.15 Output Values of Voltage (1) changed, Table 5.16 Output Values of Voltage (2) added
73
Table 5.26 Timing of On-Chip Peripheral Modules (1) changed
85
Table 5.31 A/D Conversion Characteristics (1) changed
86
Table 5.34 A/D Conversion Characteristics (2) changed
91
Table 5.38 Power-on Reset Circuit and Voltage Detection Circuit Characteristics (2) changed
All trademarks and registered trademarks are the property of their respective owners.
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 105 of 105
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the
products covered by this document, refer to the relevant sections of the document as well as any technical updates that
have been issued for the products.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.
⎯ The input pins of CMOS products are generally in the high-impedance state. In operation with an
unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an
associated shoot-through current flows internally, and malfunctions occur due to the false
recognition of the pin state as an input signal become possible. Unused pins should be handled as
described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
⎯ The states of internal circuits in the LSI are indeterminate and the states of register settings and
pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states of pins
are not guaranteed from the moment when power is supplied until the reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function
are not guaranteed from the moment when power is supplied until the power reaches the level at
which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
⎯ The reserved addresses are provided for the possible future expansion of functions. Do not access
these addresses; the correct operation of LSI is not guaranteed if they are accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become stable.
When switching the clock signal during program execution, wait until the target clock signal has
stabilized.
⎯ When the clock signal is generated with an external resonator (or from an external oscillator)
during a reset, ensure that the reset line is only released after full stabilization of the clock signal.
Moreover, when switching to a clock signal produced with an external resonator (or by an external
oscillator) while program execution is in progress, wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to a product with a different part number, confirm
that the change will not lead to problems.
⎯ The characteristics of an MPU or MCU in the same group but having a different part number may
differ in terms of the internal memory capacity, layout pattern, and other factors, which can affect
the ranges of electrical characteristics, such as characteristic values, operating margins, immunity
to noise, and amount of radiated noise. When changing to a product with a different part number,
implement a system-evaluation test for the given product.
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
2.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
3.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
4.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or
5.
Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on
third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.
the product's quality grade, as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; and industrial robots etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical
implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it
in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses
incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
6.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or systems manufactured by you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
9.
Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or
regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the
development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the
contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics
products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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Refer to "http://www.renesas.com/" for the latest and detailed information.
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