R5F56108VNFP

Datasheet RX610 Group Datasheet RENESAS 32-Bit MCU R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 1. 1.1 Overview Features The RX610 Group is an MCU with the high-speed, high-performance RX CPU as its core. One basic instruction is executable in one cycle of the system clock. Calculation functionality is further enhanced, with the inclusion of a single-precision floating-point calculation unit as well as a 32-bit multiplier and divider. Additionally, code efficiency is improved by instructions with lengths that are variable in byte units and by an enhanced range of addressing modes. Timers, serial communication interfaces, I2C bus interfaces, an A/D converter, and a D/A converter are incorporated as peripheral functions which are essential to embedded devices. Facilities for connecting external memory are also included, enabling direct connection to memory and peripheral LSI circuits. The on-chip memory is flash memory capable of large-capacity, high-speed operation, and this significantly reduces the cost of configuring systems. 1.1.1 Applications Office automation equipment and digital industrial equipment R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 1 of 84 RX610 Group 1. Overview 1.1.2 Outline of Specifications Table 1.1 lists the specifications of the RX610 Group in outline. Table 1.1 CPU Outline of Specifications Module/Function CPU Description  Maximum operating frequency: 100 MHz  32-bit RX CPU  Minimum instruction execution time: One instruction in one state (in one system clock Classification cycle)  Address space: 4-Gbyte linear address  Register set of the CPU General purpose: Sixteen 32-bit registers Control: Nine 32-bit registers Accumulator: One 64-bit register  Basic instructions: 73  Floating-point operation instructions: 8  DSP instructions: 9  Addressing modes: 10  Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian  On-chip 32-bit multiplier: 32 x 32  64 bits  On-chip divider: 32 / 32  32 bits  Barrel shifter: 32 bits FPU  Single precision (32-bit) floating point  Data types and floating-point exceptions conforming to the IEEE754 standard Memory Flash  Flash capacity: 2 Mbytes (max.)  Three types of on-board programming modes SCI boot mode, user program mode, and user boot mode RAM Data flash MCU operating modes RAM capacity: 128 Kbytes Data flash capacity: 32 Kbytes Single-chip mode, on-chip ROM enabled extended mode, and on-chip ROM disabled extended mode Clock Clock generation circuit  One main clock oscillation circuit  Includes a PLL circuit and frequency divider, so the operating frequency is selectable  System clock, peripheral module clock, and external bus clock are independently specifiable. The CPU, DMAC, DTC, ROM, and RAM run in synchronization with the system clock (ICLK): 8 to 100 MHz Peripheral modules run in synchronization with the peripheral module clock (PCLK): 8 to 50 MHz Devices connected to the external bus run in synchronization with the external bus clock (BCLK): 8 to 25 MHz Power down Power-down function  Module stop function  Four power-down modes Sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 2 of 83 RX610 Group Classification Interrupt Module/Function Interrupt control unit Description  Peripheral function interrupts: 116  External interrupts: 16 (pins IRQ15 to IRQ0)  Non-maskable interrupt: 1 (the NMI pin)  Eight priority orders specifiable 1. Overview External bus extension  The external address space can be divided into eight areas (CS0 to CS7), each of which is independently controllable. Capacity of each area: 16 Mbytes Chip-select signals (CS0# to CS7#) can be output for each area. 8-bit or 16-bit bus space can be specified for each area. The data arrangement is selectable as little endian or big endian for each area. (only for data)  Separate bus system  Wait control  Write buffer programming DMA DMA controller  4-channel DMA transfer available  Activation sources: Software trigger, external interrupts, and interrupt requests from peripheral functions Data transfer controller  Three transfer modes: Normal transfer, repeat transfer, and block transfer  Activated by interrupt requests (chain transfer enabled) I/O ports Programmable I/O ports  I/O pins: 117 (144-pin LQFP), 140 (176-pin LFBGA)  Pull-up resistors: 40  Open-drain outputs: 16  5-V tolerance: 10 Timer 16-bit timer pulse unit  (16 bits x 6 channels) x 2 units  Up to 16 pulse inputs and outputs  Select from among 7 or 8 counter-input clocks for each channel  Input capture/output compare function  Maximum of 15-phase PWM output possible in PWM mode  Buffered operation, phase counting mode (two-phase encoder input), and cascaded operation (32 bits x 2 channels) settable for each channel  PPG output trigger can be generated  Conversion start trigger for the A/D converter can be generated Programmable pulse generator  (4 bits x 4 groups) x 2 units  Provides pulse outputs by using the TPU output as a trigger  Maximum of 32-bit pulse output possible 8-bit timer  (8 bits x 2 channels) x 2 units  Select from among 8 clock sources (7 internal clocks and 1 external clock)  Allows the output of pulse trains with a desired duty cycle or PWM signals  Cascading of 2 channels enables it to be used as a 16-bit timer  Generation of trigger to start A/D converter conversion  Capable of generating baud rate clock for SCI5 and SCI6 Compare match timer  (16 bits x 2 channels) x 2 units  Select from among 4 counter-input clocks R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 3 of 83 RX610 Group Classification Watchdog timer Module/Function Description  8 bits x 1 channel  Select from among 8 counter-input clocks  Switchable between watchdog timer mode and interval timer mode 1. Overview Communication function Serial communication interface  7 channels  Serial communication mode: Asynchronous, clock synchronous, and smart card interface  On-chip baud rate generator allows any bit rate to be selected  Choice of LSB-first or MSB-first transfer  Enables average transfer rate clock input from TMR (SCI5, SCI6) I C bus interface 2  2 channels  Communication format I C bus format/SMBus format Master/slave selectable (For multi-master operation)  Maximum transfer rate: 1 Mbps  4 units (1 unit x 4 channels)  10-bit resolution  Conversion time: 1.0 s per channel (at 50-MHz (PCLK) operation)  Two kinds of operating modes 2 A/D converter Single mode and scan mode (single scan mode or continuous scan mode)  Sample-and-hold function  Three types of A/D conversion start Conversion can be started by software, a conversion start trigger by the timer (TPU or TMR), or an external trigger signal. D/A converter  2 channels  10-bit resolution  Output voltage: 0 V to VREFH CRC calculator  CRC code generation for arbitrary data lengths in 8-bit units  One of three generating polynomials selectable X + X + X + 1 , X + X + X + 1, X + X + X + 1  CRC code generation for LSB-first or MSB-first communication selectable 8 2 16 15 2 16 12 5 Operating frequency Power supply voltage Supply current Operating temperature Package 8 to 100 MHz VCC = PLLVCC = AVCC = 3.0 to 3.6V, VREFH = 3.0 to AVCC 50 mA (typ.) (regular specifications) 20 to +85 C (regular specifications), 40 to +85 C (wide-range specifications) 176-pin LFBGA (PLBG0176GA-A) 144-pin LQFP (PLQP0144KA-A) R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 4 of 83 RX610 Group 1. Overview 1.2 List of Products Table 1.2 is the list of products, and figure 1.1 shows how to read the product part no. Table 1.2 Part No. List of Products Operating Package PLQP0144KA-A PLBG0176GA-A PLQP0144KA-A PLBG0176GA-A PLQP0144KA-A PLBG0176GA-A PLQP0144KA-A PLBG0176GA-A ROM Capacity 2 Mbytes 2 Mbytes 1.5 Mbytes 1.5 Mbytes 1 Mbyte 1 Mbyte 768 Kbytes 768 Kbytes RAM Capacity 128 Kbytes 128 Kbytes 128 Kbytes 128 Kbytes 128 Kbytes 128 Kbytes 128 Kbytes 128 Kbytes Data Flash 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes Frequency (Max.) 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz R5F56108VNFP R5F56108WNBG R5F56107VNFP R5F56107WNBG R5F56106VNFP R5F56106WNBG R5F56104VNFP R5F56104WNBG R 5 F 56 10 8 V N FP Indicates the package. FP: LQFP BG: LFBGA Indicates the characteristic code. N: Regular specifications D: Wide-range specifications Indicates the number of pins. V: 144 pins W: 176 pins Indicates the ROM capacity, RAM capacity, and data flash capacity. 8: 2 Mbytes/128 Kbytes/32 Kbytes 7: 1.5 Mbytes/128 Kbytes/32 Kbytes 6: 1 Mbyte/128 Kbytes/32 Kbytes 4: 768 Kbytes/128 Kbytes/32 Kbytes Indicates the RX610 Group. Indicates the RX600 Series. Indicates the type of memory. F: Flash memory version Indicates a Renesas MCU. Indicates a Renesas semiconductor product. Figure 1.1 How to Read the Product Part No. R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 5 of 83 RX610 Group 1. Overview 1.3 Block Diagram Figure 1.2 shows a block diagram of the RX610 Group. * Data flash WDT CRC Port 2 SCI TPU TPU 7 channels Port 3 6 channels (unit 0) 6 channels (unit 1) PPG (unit 0) Internal peripheral bus 2 Port 0 Port 1 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port B Port C Port D Port E PPG (unit 1) TMR TMR CMT CMT 2 channels (unit 0) 2 channels (unit 1) 2 channels (unit 0) 2 channels (unit 1) 2 channels 4 channels (unit 0) 4 channels (unit 1) 4 channels (unit 2) 4 channels (unit 3) ICU DTC DMAC Internal peripheral bus 1 ROM Internal main bus 2 RIIC A/D converter A/D converter A/D converter Instruction bus Operand bus RAM RX CPU Internal main bus 1 A/D converter D/A converter 2 channels Port F Port G Clock generation circuit BSC External bus Port H [Legend] ICU: DTC: DMAC: BSC: WDT: CRC: Interrupt control unit Data transfer controller DMA controller Bus controller Watchdog timer CRC (Cyclic Redundancy Check) calculator SCI: TPU: PPG: TMR: CMT: RIIC: Serial communications interfaces 16-bit timer pulse unit Programmable pulse generator 8-bit timer Compare match timer I2C bus interface Note: * Ports F and H are not included in the 144-pin LQFP package. Figure 1.2 Block Diagram R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 6 of 83 RX610 Group 1. Overview 1.4 Pin Assignments Figures 1.3 and 1.4 show the pin assignments of the 176-pin LFBGA and the 144-pin LQFP, respectively. Figure 1.5 (assistance diagram) shows the pin assignment the 144-pin LQFP. Tables 1.3 and 1.4 show the lists of pins and pin functions of the 176-pin LFBGA and the 144-pin LQFP, respectively. Figure 1.3 Pin Assignment of the 176-pin LFBGA R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 7 of 83 RX610 Group 1. Overview Figure 1.4 Pin Assignment of the 144-Pin LQFP R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 8 of 83 RX610 Group 1. Overview Figure 1.5 Pin Assignment (Assistance Diagram) of the 144-Pin LQFP R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 9 of 83 RX610 Group Table 1.3 Pin No. 176-Pin LFBGA A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 AVCC VREFL P43 P46 P90 P93 P97 PG2 PD1 P60 D1 CS0#/ CS4#-A/ CS5#-B A12 P63 CS3#-A/ CS7#-A A13 A14 A15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 VCC P92 P96 PG1 PD0 P61 D0 CS1#/ CS2#-B/ CS5#-A/ CS6#-B/ CS7#-B B12 B13 B14 B15 C1 C2 C3 C4 C5 VCC PD5 PE1 PE2 P02 P66 P03 P41 P47 IRQ11-A IRQ9-B IRQ15-B TMRI3 SCK4 AN1 AN7 IRQ10-A D5 D9 D10 TMO2 SCK6 DA0 AN10 AN14 VREFH P42 P45 IRQ10-B IRQ13-B AN2 AN5 PD4 PD6 PE0 P67 P05 IRQ13-A TMO3 RxD4 D4 D6 D8 DA1 IRQ11-B IRQ14-B AN3 AN6 AN8 AN11 AN15 1. Overview List of Pins and Pin Functions (176-Pin LFBGA) Power Supply Clock System Control I/O Port P04 Interrupt IRQ12-A External Bus Timer TMCI3 Communication TxD4 Analog On-Chip Emulator TDI TCK TRST# TMS R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 10 of 83 RX610 Group Pin No. 176-Pin LFBGA C6 C7 C8 C9 C10 C11 BSCANP PG3 PD2 P62 D2 CS2#-A/ CS6#-A C12 C13 C14 C15 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 E1 E2 E3 E4 E12 E13 E14 E15 F1 F2 F3 F4 F12 VSS MD1 MD0 VCL MDE PA3 A3 PO19/ TIOCC6/ TIOCD6/ TCLKF VCC PG7 PG6 VSS WDTOVF# EMLE P00 IRQ8-A TMRI2 TxD6 AVSS P40 P44 P91 P95 PG0 PG4 PD3 P64 PE4 PE6 PE7 PG5 IRQ6-A IRQ7-A D3 CS4#-B D12 D14 D15 IRQ8-B IRQ12-B AN0 AN4 AN9 AN13 VSS PD7 PE3 PE5 P65 P01 IRQ5-A IRQ15-A IRQ9-A TMCI2 RxD6 D7 D11 D13 Power Supply Clock System Control VSS P94 AN12 I/O Port Interrupt External Bus Timer Communication Analog 1. Overview On-Chip Emulator TDO R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 11 of 83 RX610 Group Pin No. 176-Pin LFBGA F13 Power Supply Clock System Control I/O Port PA2 Interrupt External Bus A2 Timer PO18/ TIOCC6/ TCLKE F14 PA0 A0/BC0# PO16/ TIOCA6 F15 PA1 A1 PO17/ TIOCA6/ TIOCB6 G1 G2 G3 G4 G12 RES# XTAL P85 P86 PA7 A7 PO23/ TIOCA8/ TIOCB8/ TCLKH G13 PA6 A6 PO22/ TIOCA8 G14 PA4 A4 PO20/ TIOCA7 G15 PA5 A5 PO21/ TIOCA7/ TIOCB7/ TCLKG H1 H2 H3 H4 H12 EXTAL VSS PB0 A8 PO24/ TIOCA9 H13 H14 H15 J1 J2 J3 J4 VSS PH0 PH1 PF5 PF4 PF6 P34 IRQ4-A PO12/ TIOCA1 J12 J13 P72 P71 CS4#-C/ CS5#-C/ CS6#-C/ CS7#-C J14 VCC VCC NMI Communication Analog 1. Overview On-Chip Emulator R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 12 of 83 RX610 Group Pin No. 176-Pin LFBGA J15 K1 Power Supply Clock System Control I/O Port P70 P31 IRQ1-A Interrupt External Bus CS3#-B PO9/ TIOCA0/ TIOCB0 K2 P30 IRQ0-A PO8/ TIOCA0 K3 P32 IRQ2-A PO10/ TIOCC0/ TCLKA-A K4 P33 IRQ3-A PO11/ TIOCC0/ TIOCD0/ TCLKB-A K12 PB2 A10 PO26/ TIOCC9 K13 PB1 A9 PO25/ TIOCA9/ TIOCB9 K14 K15 L1 L2 L3 L4 L12 P73 P74 PF2 PF1 PF3 PF0 PB7 A15 PO31/ TIOCA11/ TIOCB11 L13 PB5 A13 PO29/ TIOCA10/ TIOCB10 L14 PB4 A12 PO28/ TIOCA10 L15 PB3 A11 PO27/ TIOCC9/ TIOCD9 M1 P27 PO7/ TIOCA5/ TIOCB5 M2 P26 PO6/ TIOCA5/ TMO1 M3 M4 M5 VCC VSS P14 IRQ4-B TCLKA-B SDA1 TxD1 SCK1 ADTRG3# Timer Communication Analog ADTRG2# 1. Overview On-Chip Emulator R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 13 of 83 RX610 Group Pin No. 176-Pin LFBGA M6 Power Supply Clock System Control I/O Port P37 Interrupt External Bus Timer PO15/ TIOCA2/ TIOCB2/ TCLKD-A M7 M8 M9 M10 M11 M12 P57 P83 P81 P51 PH4 PC7 A23/ CS4#-D/ CS7#-D M13 M14 M15 VSS PC0 PB6 A16 A14 PO30/ TIOCA11 N1 P25 PO5/ TIOCA4/ TMCI1 N2 P24 PO4/ TIOCA4/ TIOCB4/ TMRI1 N3 P20 PO0/ TIOCA3/ TIOCB3/ TMRI0 N4 N5 N6 P16 P12 P36 IRQ6-B IRQ2-B PO14/ TIOCA2 N7 N8 N9 N10 N11 N12 N13 N14 N15 P1 VSS P76 PH2 PC2 PC1 P23 A18 A17 PO3/ TIOCC3/ TIOCD3 IRQ14-A VSS P80 P50 WR0#/WR# P56 TCLKC-B RxD3/SDA0 RxD2 TxD0 RxD1 TxD5 WR1#/BC1# WAIT# Communication Analog 1. Overview On-Chip Emulator TRDATA3 TRSYNC TRDATA2 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 14 of 83 RX610 Group Pin No. 176-Pin LFBGA P2 Power Supply Clock System Control I/O Port P22 Interrupt External Bus Timer PO2/ TIOCC3/ TMO0 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 VCC P77 PC6 A22/ CS6#-D P14 P15 R1 VCC P21 PO1/ TIOCA3/ TMCI0 R2 R3 R4 R5 R6 PLLVSS P13 P10 P35 IRQ3-B IRQ0-B PO13/ TIOCA1/ TIOCB1/ TCLKC-A R7 R8 R9 R10 R11 R12 R13 R14 BCLK P55 P82 P53 PH7 PH5 PH3 P75 PC5 A21/ CS5#-D R15 PC3 A19 SCK5 TxD2 ADTRG0# P17 IRQ7-B TCLKD-B TxD3/SCL0 ADTRG1# RxD0 PC4 A20 RxD5 VCC P52 PH6 RD# PLLVCC P15 P11 P84 P54 IRQ5-B IRQ1-B TCLKB-B SCK3/SCL1 SCK2 Communication SCK0 Analog 1. Overview On-Chip Emulator TRDATA0 TRDATA1 TRCLK R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 15 of 83 RX610 Group Table 1.4 Pin No. 144-Pin LQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P34 RES# XTAL VSS EXTAL VCC NMI IRQ4-A PO12/ TIOCA1 26 P33 IRQ3-A PO11/ TIOCC0/ TIOCD0/ TCLKB-A 27 P32 IRQ2-A PO10/ TIOCC0/ TCLKA-A 28 P31 IRQ1-A PO9/ TIOCA0/ TIOCB0 29 P30 IRQ0-A PO8/ TIOCA0 30 P27 PO7/ TIOCA5/ TIOCB5 31 P26 PO6/ TIOCA5/ TMO1 TxD1 SCK1 EMLE WDTOVF# VSS MDE VCL MD1 MD0 P86 P85 AVSS P02 P01 P00 P65 IRQ10-A IRQ9-A IRQ8-A IRQ15-A TMO2 TMCI2 TMRI2 SCK6 RxD6 TxD6 1. Overview List of Pins and Pin Functions (144-Pin LQFP) Power Supply Clock System Control I/O Port P04 P03 P67 P66 Interrupt IRQ12-A IRQ11-A External Bus Timer TMCI3 TMRI3 Communication TxD4 SCK4 DA1 DA0 Analog On-Chip Emulator TDI TMS TRST# TDO R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 16 of 83 RX610 Group Pin No. 144-Pin LQFP 32 Power Supply Clock System Control I/O Port P25 Interrupt External Bus Timer PO5/ TIOCA4/ TMCI1 33 P24 PO4/ TIOCA4/ TIOCB4/ TMRI1 34 P23 PO3/ TIOCC3/ TIOCD3 35 P22 PO2/ TIOCC3/ TMO0 36 P21 PO1/ TIOCA3/ TMCI0 37 P20 PO0/ TIOCA3/ TIOCB3/ TMRI0 38 P17 IRQ7-B TCLKD-B TxD3/SCL0 ADTRG1# TxD0 RxD0 SCK0 Communication RxD1 Analog 1. Overview On-Chip Emulator 39 40 41 42 43 44 45 46 47 48 PLLVCC P16 PLLVSS P15 P14 P13 P12 P11 P10 P37 IRQ5-B IRQ4-B IRQ3-B IRQ2-B IRQ1-B IRQ0-B PO15/ TIOCA2/ TIOCB2/ TCLKD-A TCLKB-B TCLKA-B SCK3/SCL1 SDA1 TxD2 RxD2 SCK2 ADTRG0# IRQ6-B TCLKC-B RxD3/SDA0 49 P36 PO14/ TIOCA2 50 P35 PO13/ TIOCA1/ TIOCB1/ TCLKC-A 51 52 53 54 P84 P57 P56 P55 WAIT# TRDATA3 TRDATA2 TRDATA1 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 17 of 83 RX610 Group Pin No. 144-Pin LQFP 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 BCLK VCC P81 P80 P53 P52 P51 P50 P77 P76 P75 PC7 A23/ CS4#-D/ CS7#-D 70 PC6 A22/ CS6#-D 71 PC5 A21/ CS5#-D 72 73 74 75 76 77 78 79 VSS PC1 PC0 PB7 A17 A16 A15 PO31/ TIOCA11/ TIOCB11 80 PB6 A14 PO30/ TIOCA11 81 PB5 A13 PO29/ TIOCA10/ TIOCB10 82 PB4 A12 PO28/ TIOCA10 83 PB3 A11 PO27/ TIOCC9/ TIOCD9 84 PB2 A10 PO26/ TIOCC9 VCC PC2 A18 PC4 PC3 A20 A19 SCK5 RxD5 TxD5 IRQ14-A RD# WR1#/BC1# WR0#/WR# VSS P82 Power Supply Clock System Control I/O Port P54 P83 Interrupt External Bus Timer Communication Analog 1. Overview On-Chip Emulator TRDATA0 TRCLK TRSYNC# R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 18 of 83 RX610 Group Pin No. 144-Pin LQFP 85 Power Supply Clock System Control I/O Port PB1 Interrupt External Bus A9 Timer PO25/ TIOCA9/ TIOCB9 86 87 88 89 P74 P73 P72 P71 CS4#-C/ CS5#-C/ CS6#-C/ CS7#-C 90 91 92 VCC PB0 A8 PO24/ TIOCA9 93 94 VSS PA7 A7 PO23/ TIOCA8/ TIOCB8/ TCLKH 95 PA6 A6 PO22/ TIOCA8 96 PA5 A5 PO21/ TIOCA7/ TIOCB7/ TCLKG 97 PA4 A4 PO20/ TIOCA7 98 PA3 A3 PO19/ TIOCC6/ TIOCD6/ TCLKF 99 PA2 A2 PO18/ TIOCC6/ TCLKE 100 PA1 A1 PO17/ TIOCA6/ TIOCB6 101 PA0 A0/BC0# PO16/ TIOCA6 102 103 104 105 106 107 PE7 PE6 PE5 PE4 PE3 PE2 IRQ7-A IRQ6-A IRQ5-A D15 D14 D13 D12 D11 D10 P70 CS3#-B ADTRG2# ADTRG3# Communication Analog 1. Overview On-Chip Emulator R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 19 of 83 RX610 Group Pin No. 144-Pin LQFP 108 109 110 111 112 113 114 115 Power Supply Clock System Control I/O Port PE1 PE0 PD7 PD6 PD5 PD4 P64 P63 Interrupt External Bus D9 D8 D7 D6 D5 D4 CS4#-B CS3#-A/ CS7#-A 116 P62 CS2#-A/ CS6#-A 117 P61 CS1#/ CS2#-B/ CS5#-A/ CS6#-B/ CS7#-B 118 P60 CS0#/ CS4#-A/ CS5#-B 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 VREFH AVCC P05 IRQ13-A TMO3 RxD4 VREFL P40 IRQ8-B AN0 VCC P47 P46 P45 P44 P43 P42 P41 IRQ15-B IRQ14-B IRQ13-B IRQ12-B IRQ11-B IRQ10-B IRQ9-B AN7 AN6 AN5 AN4 AN3 AN2 AN1 VSS P90 AN8 PD3 PD2 PD1 PD0 P97 P96 P95 P94 P93 P92 P91 D3 D2 D1 D0 AN15 AN14 AN13 AN12 AN11 AN10 AN9 Timer Communication Analog 1. Overview On-Chip Emulator TCK R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 20 of 83 RX610 Group 1. Overview 1.5 Pin Functions Table 1.5 lists the pin functions. Table 1.5 Pin Functions Pin Name VCC VCL I/O Input Input Description Power supply pin. Connect it to the system power supply. Connect this pin to VSS via a 0.1-F capacitor. The capacitor should be placed close to the pin. VSS PLLVCC Input Input Ground pin. Connect it to the system power supply (0 V). Power supply pin for the PLL circuit. Connect it to the system power supply. PLLVSS Input Input Input Output Input Ground pin for the PLL circuit Pins for a crystal resonator. An external clock signal can be input through the EXTAL pin. Outputs the system clock for external devices. Pins for setting the operating mode. The signal levels on these pins must not be changed during operation. Classifications Power supply Clock XTAL EXTAL BCLK Operating mode control MD0, MD1, MDE System control RES# Input Reset signal input pin. This LSI enters the reset state when this signal goes low. EMLE Input Input pin to enable on-chip emulator signal. When the on-chip emulator is used, this pin should be driven high. When not used, it should be driven low. BSCANP Input Input pin to enable boundary-scan signal. When this pin is driven high, the boundary scan is enabled. When the boundary scan is not used, this pin should be driven low. On-chip emulator TRST# TMS TDI TCK TDO TRCLK Input Input Input Input Output Output On-chip emulator pins. When the EMLE pin is driven high, these pins are dedicated for the on-chip emulator. This pin outputs the clock for synchronization with the trace data. TRSYNC Output This pin indicates that output from the TRDATA0 to TRDATA3 pins is valid. TRDATA0 to TRDATA3 Address bus Data bus A0 to A23 D0 to D15 Output Output I/O These pins output the trace information. Output pins for the address Input and output pins for the bidirectional data bus R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 21 of 83 RX610 Group Classifications Bus control Pin Name RD# I/O Output Description 1. Overview Strobe signal which indicates that reading from the external bus interface space is in progress. WR0# Output Strobe signal which indicates that the lower-order byte (D0 to D7) is valid in writing to the external bus interface space, in byte strobe mode. WR1# Output Strobe signal which indicates that the higher-order byte (D8 to D15) is valid in writing to the external bus interface space, in byte strobe mode. WR# Output Strobe signal which indicates that writing to the external bus interface space is in progress, in 1-write strobe mode. BC0# Output Strobe signal which indicates that the lower-order byte (D0 to D7) is valid in access to the external bus interface space, in 1-write strobe mode. BC1# Output Strobe signal which indicates that the higher-order byte (D8 to D15) is valid in access to the external bus interface space, in 1- write strobe mode. CS0#, CS1# CS2#-A/CS2#-B CS3#-A/CS3#-B CS4#-A/CS4#-B/ CS4#-C/CS4#-D CS5#-A/CS5#-B/ CS5#-C/CS5#-D CS6#-A/CS6#-B/ CS6#-C/CS6#-D CS7#-A/CS7#-B/ CS7#-C/CS7#-D WAIT# Output Select signals for areas 0 to 7 Input Requests wait cycles in access to the external space R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 22 of 83 RX610 Group Classifications Interrupt Pin Name NMI IRQ0-A/IRQ0-B IRQ1-A/IRQ1-B IRQ2-A/IRQ2-B IRQ3-A/IRQ3-B IRQ4-A/IRQ4-B IRQ5-A/IRQ5-B IRQ6-A/IRQ6-B IRQ7-A/IRQ7-B IRQ8-A/IRQ8-B IRQ9-A/IRQ9-B IRQ10-A/IRQ10-B IRQ11-A/IRQ11-B IRQ12-A/IRQ12-B IRQ13-A/IRQ13-B IRQ14-A/IRQ14-B IRQ15-A/IRQ15-B 16-bit timer pulse unit TIOCA0, TIOCB0 TIOCC0, TIOCD0 TIOCA1, TIOCB1 I/O I/O I/O Input Input Description Non-maskable interrupt request signal Maskable request signals 1. Overview Signals for TGRA0 to TGRD0. These pins are used as input capture inputs, output compare outputs, or PWM outputs. Signals for TGRA1 and TGRB1. These pins are used as input capture inputs, output compare outputs, or PWM outputs. TIOCA2, TIOCB2 I/O Signals for TGRA2 and TGRB2. These pins are used as input capture inputs, output compare outputs, or PWM outputs. TIOCA3, TIOCB3 TIOCC3, TIOCD3 TIOCA4, TIOCB4 I/O Signals for TGRA3 to TGRD3. These pins are used as input capture inputs, output compare outputs, or PWM outputs. I/O Signals for TGRA4 and TGRB4. These pins are used as input capture inputs, output compare outputs, or PWM outputs. TIOCA5, TIOCB5 I/O Signals for TGRA5 and TGRB5. These pins are used as input capture inputs, output compare outputs, or PWM outputs. TIOCA6, TIOCB6 TIOCC6, TIOCD6 TIOCA7, TIOCB7 I/O Signals for TGRA6 to TGRD6. These pins are used as input capture inputs, output compare outputs, or PWM outputs. I/O Signals for TGRA7 and TGRB7. These pins are used as input capture inputs, output compare outputs, or PWM outputs. TIOCA8, TIOCB8 I/O Signals for TGRA8 and TGRB8. These pins are used as input capture inputs, output compare outputs, or PWM outputs. TIOCA9, TIOCB9 TIOCC9, TIOCD9 TIOCA10, TIOCB10 I/O Signals for TGRA9 to TGRD9. These pins are used as input capture inputs, output compare outputs, or PWM outputs. I/O Signals for TGRA10 and TGRB10. These pins are used as input capture inputs, output compare outputs, or PWM outputs. TIOCA11, TIOCB11 I/O Signals for TGRA11 and TGRB11. These pins are used as input capture inputs, output compare outputs, or PWM outputs. R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 23 of 83 RX610 Group Classifications 16-bit timer pulse unit Pin Name TCLKA-A/TCLKA-B TCLKB-A/TCLKB-B TCLKC-A/TCLKC-B TCLKD-A/TCLKD-B TCLKE, TCLKF TCLKG, TCLKH Programmable pulse generator 8-bit timer TMO0 to TMO3 TMCI0 to TMCI3 Output Input Output pins for the compare match signals PO0 to PO31 Output Output pins for the pulse signals I/O Input Description Input pins for external clock signals 1. Overview Input pins for the external clock signals that drive for the counters TMRI0 to TMRI3 Watchdog timer WDTOVF# Input Output Input pins for the counter-reset signals Output pin for the counter-overflow signal in watchdog-timer mode Serial communication interface TxD0, TxD1, TxD2, TxD3, TxD4, TxD5, TxD6 RxD0, RxD1, RxD2, RxD3, RxD4, RxD5, RxD6 SCK0, SCK1, SCK2, SCK3, SCK4, SCK5, SCK6 Output Output pins for data transmission Input Input pins for data reception I/O Input/output pins for clock signals I C bus interface 2 SCL0, SCL1 I/O Input/output pins for RIIC clocks. Bus can be directly driven by the NMOS open drain output. SDA0, SDA1 I/O Input/output pins for RIIC data. Bus can be directly driven by the NMOS open drain output. A/D converter AN0 to AN15 Input Input pins for the analog signals to be processed by the A/D converter ADTRG0# to ADTRG3# Input Input pins for the external trigger signals that start the A/D conversion D/A converter DA0, DA1 Output Output pins for the analog signals from the D/A converter R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 24 of 83 RX610 Group Classifications Analog power supply Pin Name AVCC I/O Input Description 1. Overview Analog power supply pin for the A/D and D/A converters. When the A/D and D/A converters are not in use, connect this pin to the system power supply. AVSS Input Ground pin for the A/D and D/A converters. Connect this pin to the system power supply (0 V). VREFH Input Reference power supply pin for the A/D and D/A converters. When the A/D and D/A converters are not in use, connect this pin to the system power supply. VREFL Input Reference ground pin for the A/D and D/A converters. Make sure to connect this pin to the analog reference power supply (0 V). When the A/D and D/A converters are not in use, connect this pin to the system power supply (0 V). For details, see section 23.6.7, Ranges of Settings for Analog Power Supply and Other Pins. I/O ports P00 to P05 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P86 P90 to P97 PA0 to PA7 PB0 to PB7 PC0 to PC7 PD0 to PD7 PE0 to PE7 PF0 to PF6 PG0 to PG7 PH0 to PH7 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 6-bit input/output pins 8-bit input/output pins 8-bit input/output pins 8-bit input/output pins 8-bit input/output pins 8-bit input/output pins. (P53 is an input-only pin.) 8-bit input/output pins 8-bit input/output pins 7-bit input/output pins 8-bit input/output pins 8-bit input/output pins 8-bit input/output pins 8-bit input/output pins 8-bit input/output pins 8-bit input/output pins 7-bit input/output pins 8-bit input/output pins 8-bit input/output pins R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 25 of 83 RX610 Group 2. CPU 2. CPU The RX CPU has sixteen general-purpose registers, nine control registers, and one accumulator used for DSP instructions. General-purpose register b31 b0 R0 (SP) * R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Control register b31 b0 ISP USP INTB PC PSW BPC BPSW FINTV FPSW DSP instruction register b63 (Interrupt stack pointer) (User stack pointer) (Interrupt table register) (Program counter) (Processor status word) (Backup PC) (Backup PSW) (Fast interrupt vector register) (Floating-point status word) b0 ACC (Accumulator) Note: * The stack pointer (SP) can be the interrupt stack pointer (ISP) or user stack pointer (USP), according to the value of the U bit in the PSW. Figure 2.1 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Register Set of the CPU Page 26 of 83 RX610 Group 2. CPU 2.1 General-Purpose Registers (R0 to R15) This CPU has sixteen general-purpose registers (R0 to R15). R1 to R15 can be used as data registers or address registers. R0, a general-purpose register, also functions as the stack pointer (SP). The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the stack pointer select bit (U) in the processor status word (PSW). 2.2 (1) Control Registers Interrupt Stack Pointer (ISP)/User Stack Pointer (USP) The stack pointer (SP) can be either of two types, the interrupt stack pointer (ISP) or the user stack pointer (USP). Whether the stack pointer operates as the ISP or USP depends on the value of the stack pointer select bit (U) in the processor status word (PSW). Set the ISP or USP to a multiple of four, as this reduces the numbers of cycles required to execute interrupt sequences and instructions entailing stack manipulation. (2) Interrupt Table Register (INTB) The interrupt table register (INTB) specifies the address where the relocatable vector table starts. Set INTB to a multiple of four. (3) Program Counter (PC) The program counter (PC) indicates the address of the instruction being executed. (4) Processor Status Word (PSW) The processor status word (PSW) indicates results of instruction execution or the state of the CPU. (5) Backup PC (BPC) The backup PC (BPC) is provided to speed up response to interrupts. After a fast interrupt has been generated, the contents of the program counter (PC) are saved in the BPC. (6) Backup PSW (BPSW) The backup PSW (BPSW) is provided to speed up response to interrupts. After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in the BPSW. The allocation of bits in the BPSW corresponds to that in the PSW. (7) Fast Interrupt Vector Register (FINTV) The fast interrupt vector register (FINTV) is provided to speed up response to interrupts. The FINTV specifies a branch destination address when a fast interrupt has been generated. R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 27 of 83 RX610 Group 2. CPU (8) Floating-Point Status Word (FPSW) The floating-point status word (FPSW) indicates the results of floating-point operations. When an exception handling enable bit (Ej) enables the exception handling (Ej = 1), the corresponding Cj flag indicates the source of the exception within the exception handling routine. If the exception handling is masked (Ej = 0), check the Fj flag at the end of a series of processing whether an exception is generated or not. The Fj flag is the accumulation type flag (j = X, U, Z, O, or V). (9) Accumulator (ACC) The accumulator (ACC) is a 64-bit register used for DSP instructions. The accumulator is also used for the multiply and multiply-and-accumulate instructions; EMUL, EMULU, FMUL, MUL, and RMPA, in which case the prior value in the accumulator is modified by execution of the instruction. Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The MVTACHI and MVTACLO instructions write data to the higher-order 32 bits (bits 63 to 32) and the lower-order 32 bits (bits 31 to 0), respectively. Use the MVFACHI and MVFACMI instructions for reading data from the accumulator. The MVFACHI and MVFACMI instructions read data from the higher-order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively. R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 28 of 83 RX610 Group 3. Address Space 3. 3.1 Address Space Address Space This MCU has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is, linear access to an address space of up to 4 Gbytes is possible, and this contains both program and data areas. Figures 4.1 to 4.4 show the memory maps in the respective operating modes of each product. Accessible areas will differ according to the operating mode and states of control bits. Single-chip mode*2 0000 0000h 0002 0000h 0008 0000h Peripheral I/O registers 0010 0000h 0010 8000h 007F 8000h 007F A000h Reserved area*1 007F C000h 007F C500h Peripheral I/O registers Reserved area* 007F FC00h 0080 0000h 00E0 0000h 1 On-chip ROM enabled extended mode 0000 0000h 0002 0000h 0008 0000h Peripheral I/O registers 0010 0000h 0010 8000h 007F 8000h 007F A000h Reserved area*1 007F C000h 007F C500h Peripheral I/O registers Reserved area* 007F FC00h 0080 0000h 00E0 0000h On-chip ROM (program ROM) (write only) 0100 0000h 0100 0000h 1 On-chip ROM disabled extended mode 0000 0000h 0002 0000h 0008 0000h Peripheral /O registers 0010 0000h On-chip RAM Reserved area*1 On-chip RAM Reserved area*1 On-chip RAM Reserved area*1 On-chip ROM (data flash) Reserved area*1 FCU RAM area*3 On-chip ROM (data flash) Reserved area*1 FCU RAM area*3 Reserved area*1 Peripheral I/O registers Reserved area*1 On-chip ROM (program ROM) (write only) Peripheral I/O registers Reserved area*1 0100 0000h External address space External address space 0800 0000h Reserved area* 1 0800 0000h Reserved area*1 Reserved area*1 FEFF E000h FF00 0000h FF7F C000h FF80 0000h FFE0 0000h FFFF FFFFh On-chip ROM (FCU firmware)*3 (read only) Reserved area*1 On-chip ROM (user boot) (read only) Reserved area* 1 FEFF E000h FF00 0000h FF7F C000h FF80 0000h FFE0 0000h FFFF FFFFh On-chip ROM (FCU firmware)*3 (read only) Reserved area*1 On-chip ROM (user boot) (read only) Reserved area*1 On-chip ROM (program ROM) (read only) FFFF FFFFh External address space FF00 0000h On-chip ROM (program ROM) (read only) Notes: 1. A reserved area should not be accessed. 2. The address space in boot mode and user boot mode is the same as the address space in single-chip mode. 3. For detaIls on the FCU, see section 26, ROM (Flash Memory for Code Storage) and section 27, Data Flash (Flash Memory for Data Storage) in the User's manual: Hardware. Figure 3.1 Memory Map of the R5F56108 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 29 of 83 RX610 Group 3. Address Space Figure 3.2 Memory Map of the R5F56107 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 30 of 83 RX610 Group On-chip ROM enabled extended mode 0000 0000h 1 3. Address Space On-chip ROM disabled extended mode 0000 0000h 1 Single-chip mode*2 0000 0000h 0002 0000h 0008 0000h Peripheral I/O registers 0010 0000h 0010 8000h 007F 8000h 007F A000h Reserved area*1 007F C000h 007F C500h Peripheral I/O registers Reserved area* 007F FC00h 0080 0000h Reserved area* 00F0 0000h 0100 0000h 1 1 On-chip RAM Reserved area* On-chip RAM Reserved area* On-chip RAM Reserved area*1 Peripheral /O registers 0002 0000h 0008 0000h 0002 0000h 0008 0000h Peripheral I/O registers 0010 0000h 0010 8000h 007F 8000h 007F A000h Reserved area*1 007F C000h 007F C500h Peripheral I/O registers Reserved area* 007F FC00h 0080 0000h Reserved area*1 00F0 0000h 0100 0000h On-chip ROM (program ROM) (write only) 0100 0000h 1 On-chip ROM (data flash) Reserved area*1 FCU RAM area* 3 On-chip ROM (data flash) Reserved area*1 FCU RAM area*3 0010 0000h Reserved area*1 Peripheral I/O registers Peripheral I/O registers On-chip ROM (program ROM) (write only) External address space External address space 0800 0000h Reserved area* 1 0800 0000h Reserved area*1 Reserved area*1 FEFF E000h FF00 0000h FF7F C000h FF80 0000h On-chip ROM (FCU firmware)*3 (read only) Reserved area*1 On-chip ROM (user boot) (read only) Reserved area*1 FEFF E000h FF00 0000h FF7F C000h FF80 0000h On-chip ROM (FCU firmware)*3 (read only) Reserved area*1 On-chip ROM (user boot) (read only) Reserved area*1 External address space FF00 0000h FFF0 0000h FFFF FFFFh On-chip ROM (program ROM) (read only) FFF0 0000h FFFF FFFFh On-chip ROM (program ROM) (read only) FFFF FFFFh Notes: 1. A reserved area should not be accessed. 2. The address space in boot mode and user boot mode is the same as the address space in single-chip mode. 3. For details on the FCU, see section 26, ROM (Flash Memory for Code Storage) and section 27, Data Flash (Flash Memory for Data Storage) in the User's manual: Hardware. Figure 3.3 Memory Map of the R5F56106 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 31 of 83 RX610 Group On-chip ROM enabled extended mode 0000 0000h 1 3. Address Space On-chip ROM disabled extended mode 0000 0000h 1 Single-chip mode*2 0000 0000h 0002 0000h 0008 0000h Peripheral I/O registers 0010 0000h 0010 8000h 007F 8000h 007F A000h Reserved area*1 007F C000h 007F C500h Peripheral I/O registers Reserved area* 007F FC00h 0080 0000h Reserved area* 00F4 0000h 0100 0000h 1 1 On-chip RAM Reserved area* On-chip RAM Reserved area* On-chip RAM Reserved area*1 Peripheral /O registers 0002 0000h 0008 0000h 0002 0000h 0008 0000h Peripheral I/O registers 0010 0000h 0010 8000h 007F 8000h 007F A000h Reserved area*1 007F C000h 007F C500h Peripheral I/O registers Reserved area* 007F FC00h 0080 0000h Reserved area*1 00F4 0000h 0100 0000h On-chip ROM (program ROM) (write only) 0100 0000h 1 On-chip ROM (data flash) Reserved area*1 FCU RAM area* 3 On-chip ROM (data flash) Reserved area*1 FCU RAM area*3 0010 0000h Reserved area*1 Peripheral I/O registers Peripheral I/O registers On-chip ROM (program ROM) (write only) External address space External address space 0800 0000h Reserved area* 1 0800 0000h Reserved area*1 Reserved area*1 FEFF E000h FF00 0000h FF7F C000h FF80 0000h On-chip ROM (FCU firmware)*3 (read only) Reserved area*1 On-chip ROM (user boot) (read only) Reserved area*1 FEFF E000h FF00 0000h FF7F C000h FF80 0000h On-chip ROM (FCU firmware)*3 (read only) Reserved area*1 On-chip ROM (user boot) (read only) External address space Reserved area*1 FF00 0000h FFF4 0000h FFFF FFFFh On-chip ROM (program ROM) (read only) FFF4 0000h FFFF FFFFh On-chip ROM (program ROM) (read only) FFFF FFFFh Notes: 1. A reserved area should not be accessed. 2. The address space in boot mode and user boot mode is the same as the address space in single-chip mode. 3. For details on the FCU, see section 26, ROM (Flash Memory for Code Storage) and section 27, Data Flash (Flash Memory for Data Storage) in the User's manual: Hardware. Figure 3.4 Memory Map of the R5F56104 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 32 of 83 RX610 Group 3. Address Space 3.2 External Address Space The external address space is divided into up to 8 areas, each corresponding to the CSi# signal output from a CSi# (i = 0 to 7) pin. Figure 4.5 shows the address ranges corresponding to the individual CSi# signals (CSi areas, i = 0 to 7) in on-chip ROM disabled external extended mode. 0000 0000h 0002 0000h 0008 0000h On-chip RAM Reserved area Peripheral /O registers 0010 0000h 0100 0000h CS7 (16 Mbytes) Reserved area 01FF FFFFh 0200 0000h CS6 (16 Mbytes) 02FF FFFFh 0300 0000h CS5 (16 Mbytes) 0100 0000h 03FF FFFFh 0400 0000h External address space 04FF FFFFh 0500 0000h 0800 0000h CS3 (16 Mbytes) 05FF FFFFh 0600 0000h CS2 (16 Mbytes) 06FF FFFFh 0700 0000h CS1 (16 Mbytes) 07FF FFFFh CS4 (16 Mbytes) Reserved area* FF00 0000h External address space* FFFF FFFFh FF00 0000h CS0 (16 Mbytes) FFFF FFFFh Note: * CS0 area is disabled in on-chip ROM enabled external extended mode. In this mode, the address space for addresses above 0800 0000h is as shown in figure 4.1. Figure 3.5 Correspondence between External Address Spaces and CSi Areas (In On-Chip ROM Disabled External Extended Mode) R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 33 of 83 RX610 Group 4. I/O Registers 4. Table 4.1 I/O Registers List of I/O Registers (Address Order) Number of Module Register Number Access Size 16 16 16 16 16 32 32 32 32 8 8 8 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Access Cycles 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 2 ICLK 2 ICLK 2 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK * 4 to 5 ICLK * 4 to 5 ICLK * 4 to 5 ICLK 8 8 8 Address 0008 0000h 0008 0002h 0008 0006h 0008 0008h 0008 000Ch 0008 0010h 0008 0014h 0008 0018h 0008 0020h 0008 1300h 0008 1304h 0008 1306h 0008 2000h 0008 2004h 0008 2008h 0008 200Ch 0008 2010h 0008 2014h 0008 2018h 0008 201Ch 0008 2020h 0008 2024h 0008 2028h 0008 202Ch 0008 2030h 0008 2034h 0008 2038h 0008 203Ch 0008 2200h 0008 2204h 0008 2208h 0008 2210h 0008 2214h 0008 2218h 0008 2220h 0008 2224h 0008 2228h 0008 2230h 0008 2234h Abbreviation Register Name SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM BSC BSC BSC DMAC0 DMAC0 DMAC0 DMAC0 DMAC1 DMAC1 DMAC1 DMAC1 DMAC2 DMAC2 DMAC2 DMAC2 DMAC3 DMAC3 DMAC3 DMAC3 DMAC0 DMAC0 DMAC0 DMAC1 DMAC1 DMAC1 DMAC2 DMAC2 DMAC2 DMAC3 DMAC3 Mode monitor register Mode status register System control register 0 System control register 1 Standby control register Module stop control register A Module stop control register B Module stop control register C System clock control register Bus error source clear register Bus error monitor enable register Bus error interrupt enable register DMA current transfer source address register DMA current transfer destination address register DMA current transfer byte count register DMA mode register DMA current transfer source address register DMA current transfer destination address register DMA current transfer byte count register DMA mode register DMA current transfer source address register DMA current transfer destination address register DMA current transfer byte count register DMA mode register DMA current transfer source address register DMA current transfer destination address register DMA current transfer byte count register DMA mode register DMA reload transfer source address register DMA reload transfer destination address register DMA reload transfer byte count register DMA reload transfer source address register DMA reload transfer destination address register DMA reload transfer byte count register DMA reload transfer source address register DMA reload transfer destination address register DMA reload transfer byte count register DMA reload transfer source address register DMA reload transfer destination address register Abbreviation of Bits MDMONR MDSR SYSCR0 SYSCR1 SBYCR MSTPCRA MSTPCRB MSTPCRC SCKCR BERCLR BEREN BERIE DMCSA DMCDA DMCBC DMMOD DMCSA DMCDA DMCBC DMMOD DMCSA DMCDA DMCBC DMMOD DMCSA DMCDA DMCBC DMMOD DMRSA DMRDA DMRBC DMRSA DMRDA DMRBC DMRSA DMRDA DMRBC DMRSA DMRDA 16 16 16 16 16 32 32 32 32 8 8 8 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 *8 8 8 8 4 to 5 ICLK * 4 to 5 ICLK * 4 to 5 ICLK * 4 to 5 ICLK *8 8 8 8 4 to 5 ICLK * 4 to 5 ICLK * 4 to 5 ICLK * R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 34 of 83 RX610 Group 4. I/O Registers Number of Module Register Number Access Size 32 32 8 8 8 8 32 8 8 8 8 32 8 8 8 8 32 8 8 8 8 8 8 8 8 16 32 32 16 32 32 16 32 32 16 32 32 16 32 32 16 32 32 16 32 Access Cycles 4 to 5 ICLK * 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 1 to 2 BCLK * 1 to 2 BCLK * 1 to 2 BCLK 7 7 8 Address 0008 2238h 0008 2400h 0008 2404h 0008 2405h 0008 2406h 0008 2407h 0008 2408h 0008 240Ch 0008 240Dh 0008 240Eh 0008 240Fh 0008 2410h 0008 2414h 0008 2415h 0008 2416h 0008 2417h 0008 2418h 0008 241Ch 0008 241Dh 0008 241Eh 0008 241Fh 0008 2502h 0008 250Bh 0008 2517h 0008 251Bh 0008 3002h 0008 3004h 0008 3008h 0008 3012h 0008 3014h 0008 3018h 0008 3022h 0008 3024h 0008 3028h 0008 3032h 0008 3034h 0008 3038h 0008 3042h 0008 3044h 0008 3048h 0008 3052h 0008 3054h 0008 3058h 0008 3062h 0008 3064h Abbreviation Register Name DMAC3 DMAC0 DMAC0 DMAC0 DMAC0 DMAC0 DMAC1 DMAC1 DMAC1 DMAC1 DMAC1 DMAC2 DMAC2 DMAC2 DMAC2 DMAC2 DMAC3 DMAC3 DMAC3 DMAC3 DMAC3 DMAC common DMAC common DMAC common DMAC common Abbreviation of Bits DMRBC DMCRA DMCRB DMCRC DMCRD DMCRE DMCRA DMCRB DMCRC DMCRD DMCRE DMCRA DMCRB DMCRC DMCRD DMCRE DMCRA DMCRB DMCRC DMCRD DMCRE DMSCNT DMICNT DMEDET DMASTS CS0MOD CS0WCNT1 CS0WCNT2 CS1MOD CS1WCNT1 CS1WCNT2 CS2MOD CS2WCNT1 CS2WCNT2 CS3MOD CS3WCNT1 CS3WCNT2 CS4MOD CS4WCNT1 CS4WCNT2 CS5MOD CS5WCNT1 CS5WCNT2 CS6MOD CS6WCNT1 32 32 8 8 8 8 32 8 8 8 8 32 8 8 8 8 32 8 8 8 8 8 8 8 8 16 32 32 16 32 32 16 32 32 16 32 32 16 32 32 16 32 32 16 32 DMA reload transfer byte count register DMA control register A DMA control register B DMA control register C DMA control register D DMA control register E DMA control register A DMA control register B DMA control register C DMA control register D DMA control register E DMA control register A DMA control register B DMA control register C DMA control register D DMA control register E DMA control register A DMA control register B DMA control register C DMA control register D DMA control register E DMA start control register DMA interrupt control register DMA transfer end detect register DMA arbitration status register CS0 mode register CS0 wait control register 1 CS0 wait control register 2 CS1 mode register CS1 wait control register 1 CS1 wait control register 2 CS2 mode register CS2 wait control register 1 CS2 wait control register 2 CS3 mode register CS3 wait control register 1 CS3 wait control register 2 CS4 mode register CS4 wait control register 1 CS4 wait control register 2 CS5 mode register CS5 wait control register 1 CS5 wait control register 2 CS6 mode register CS6 wait control register 1 BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC *7 7 7 7 7 1 to 2 BCLK * 1 to 2 BCLK * 1 to 2 BCLK * 1 to 2 BCLK * 1 to 2 BCLK *7 7 7 1 to 2 BCLK * 1 to 2 BCLK * 1 to 2 BCLK *7 7 7 7 7 1 to 2 BCLK * 1 to 2 BCLK * 1 to 2 BCLK * 1 to 2 BCLK * 1 to 2 BCLK *7 7 7 1 to 2 BCLK * 1 to 2 BCLK * 1 to 2 BCLK *7 7 1 to 2 BCLK * R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 35 of 83 RX610 Group 4. I/O Registers Number of Module Register Number Access Size 32 16 32 32 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access Cycles 1 to 2 BCLK * 1 to 2 BCLK * 1 to 2 BCLK * 1 to 2 BCLK * 1 to 2 BCLK 7 7 7 7 Address 0008 3068h 0008 3072h 0008 3074h 0008 3078h 0008 3802h 0008 380Ah 0008 3812h 0008 381Ah 0008 3822h 0008 382Ah 0008 3832h 0008 383Ah 0008 3842h 0008 384Ah 0008 3852h 0008 385Ah 0008 3862h 0008 386Ah 0008 3872h 0008 387Ah 0008 7010h 0008 7015h 0008 7017h 0008 701Ch 0008 701Dh 0008 701Eh 0008 701Fh 0008 7040h 0008 7041h 0008 7042h 0008 7043h 0008 7044h 0008 7045h 0008 7046h 0008 7047h 0008 7048h 0008 7049h 0008 704Ah 0008 704Bh 0008 704Ch 0008 704Dh 0008 704Eh 0008 704Fh 0008 7060h 0008 7062h Abbreviation Register Name BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU CS6 wait control register 2 CS7 mode register CS7 wait control register 1 CS7 wait control register 2 CS0 control register CS0 recovery cycle register CS1 control register CS1 recovery cycle register CS2 control register CS2 recovery cycle register CS3 control register CS3 recovery cycle register CS4 control register CS4 recovery cycle register CS5 control register CS5 recovery cycle register CS6 control register CS6 recovery cycle register CS7 control register CS7 recovery cycle register Interrupt request register 016 Interrupt request register 021 Interrupt request register 023 Interrupt request register 028 Interrupt request register 029 Interrupt request register 030 Interrupt request register 031 Interrupt request register 064 Interrupt request register 065 Interrupt request register 066 Interrupt request register 067 Interrupt request register 068 Interrupt request register 069 Interrupt request register 070 Interrupt request register 071 Interrupt request register 072 Interrupt request register 073 Interrupt request register 074 Interrupt request register 075 Interrupt request register 076 Interrupt request register 077 Interrupt request register 078 Interrupt request register 079 Interrupt request register 096 Interrupt request register 098 Abbreviation of Bits CS6WCNT2 CS7MOD CS7WCNT1 CS7WCNT2 CS0CNT CS0REC CS1CNT CS1REC CS2CNT CS2REC CS3CNT CS3REC CS4CNT CS4REC CS5CNT CS5REC CS6CNT CS6REC CS7CNT CS7REC IR016 IR021 IR023 IR028 IR029 IR030 IR031 IR064 IR065 IR066 IR067 IR068 IR069 IR070 IR071 IR072 IR073 IR074 IR075 IR076 IR077 IR078 IR079 IR096 IR098 32 16 32 32 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 *7 7 7 1 to 2 BCLK * 1 to 2 BCLK * 1 to 2 BCLK *7 7 7 7 7 1 to 2 BCLK * 1 to 2 BCLK * 1 to 2 BCLK * 1 to 2 BCLK * 1 to 2 BCLK *7 7 7 1 to 2 BCLK * 1 to 2 BCLK * 1 to 2 BCLK *7 7 7 7 7 1 to 2 BCLK * 1 to 2 BCLK * 1 to 2 BCLK * 1 to 2 BCLK * 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 36 of 83 RX610 Group 4. I/O Registers Number of Module Register Number Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access Cycles 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK Address 0008 7063h 0008 7064h 0008 7065h 0008 7068h 0008 7069h 0008 706Ah 0008 706Bh 0008 706Ch 0008 706Fh 0008 7070h 0008 7073h 0008 7074h 0008 7075h 0008 7076h 0008 7078h 0008 7079h 0008 707Ah 0008 707Bh 0008 707Ch 0008 707Dh 0008 707Eh 0008 707Fh 0008 7080h 0008 7083h 0008 7084h 0008 7085h 0008 7086h 0008 7088h 0008 7089h 0008 708Ah 0008 708Bh 0008 708Ch 0008 708Dh 0008 708Eh 0008 7091h 0008 7092h 0008 7095h 0008 7096h 0008 7097h 0008 7098h 0008 709Ah 0008 709Bh 0008 709Ch 0008 709Dh 0008 709Eh Abbreviation Register Name ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU Interrupt request register 099 Interrupt request register 100 Interrupt request register 101 Interrupt request register 104 Interrupt request register 105 Interrupt request register 106 Interrupt request register 107 Interrupt request register 108 Interrupt request register 111 Interrupt request register 112 Interrupt request register 115 Interrupt request register 116 Interrupt request register 117 Interrupt request register 118 Interrupt request register 120 Interrupt request register 121 Interrupt request register 122 Interrupt request register 123 Interrupt request register 124 Interrupt request register 125 Interrupt request register 126 Interrupt request register 127 Interrupt request register 128 Interrupt request register 131 Interrupt request register 132 Interrupt request register 133 Interrupt request register 134 Interrupt request register 136 Interrupt request register 137 Interrupt request register 138 Interrupt request register 139 Interrupt request register 140 Interrupt request register 141 Interrupt request register 142 Interrupt request register 145 Interrupt request register 146 Interrupt request register 149 Interrupt request register 150 Interrupt request register 151 Interrupt request register 152 Interrupt request register 154 Interrupt request register 155 Interrupt request register 156 Interrupt request register 157 Interrupt request register 158 Abbreviation of Bits IR099 IR100 IR101 IR104 IR105 IR106 IR107 IR108 IR111 IR112 IR115 IR116 IR117 IR118 IR120 IR121 IR122 IR123 IR124 IR125 IR126 IR127 IR128 IR131 IR132 IR133 IR134 IR136 IR137 IR138 IR139 IR140 IR141 IR142 IR145 IR146 IR149 IR150 IR151 IR152 IR154 IR155 IR156 IR157 IR158 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 37 of 83 RX610 Group 4. I/O Registers Number of Module Register Number Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access Cycles 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK Address 0008 709Fh 0008 70A0h 0008 70A1h 0008 70A2h 0008 70A5h 0008 70A6h 0008 70A7h 0008 70A8h 0008 70AAh 0008 70ABh 0008 70AEh 0008 70AFh 0008 70B0h 0008 70B1h 0008 70B2h 0008 70B3h 0008 70B4h 0008 70B5h 0008 70B6h 0008 70B7h 0008 70B8h 0008 70B9h 0008 70C6h 0008 70C7h 0008 70C8h 0008 70C9h 0008 70D6h 0008 70D7h 0008 70D8h 0008 70D9h 0008 70DAh 0008 70DBh 0008 70DCh 0008 70DDh 0008 70DEh 0008 70DFh 0008 70E0h 0008 70E1h 0008 70E2h 0008 70E3h 0008 70E4h 0008 70E5h 0008 70E6h 0008 70E7h 0008 70E8h Abbreviation Register Name ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU Interrupt request register 159 Interrupt request register 160 Interrupt request register 161 Interrupt request register 162 Interrupt request register 165 Interrupt request register 166 Interrupt request register 167 Interrupt request register 168 Interrupt request register 170 Interrupt request register 171 Interrupt request register 174 Interrupt request register 175 Interrupt request register 176 Interrupt request register 177 Interrupt request register 178 Interrupt request register 179 Interrupt request register 180 Interrupt request register 181 Interrupt request register 182 Interrupt request register 183 Interrupt request register 184 Interrupt request register 185 Interrupt request register 198 Interrupt request register 199 Interrupt request register 200 Interrupt request register 201 Interrupt request register 214 Interrupt request register 215 Interrupt request register 216 Interrupt request register 217 Interrupt request register 218 Interrupt request register 219 Interrupt request register 220 Interrupt request register 221 Interrupt request register 222 Interrupt request register 223 Interrupt request register 224 Interrupt request register 225 Interrupt request register 226 Interrupt request register 227 Interrupt request register 228 Interrupt request register 229 Interrupt request register 230 Interrupt request register 231 Interrupt request register 232 Abbreviation of Bits IR159 IR160 IR161 IR162 IR165 IR166 IR167 IR168 IR170 IR171 IR174 IR175 IR176 IR177 IR178 IR179 IR180 IR181 IR182 IR183 IR184 IR185 IR198 IR199 IR200 IR201 IR214 IR215 IR216 IR217 IR218 IR219 IR220 IR221 IR222 IR223 IR224 IR225 IR226 IR227 IR228 IR229 IR230 IR231 IR232 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 38 of 83 RX610 Group 4. I/O Registers Number of Module Register Number Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access Cycles 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK Address 0008 70E9h 0008 70EAh 0008 70EBh 0008 70ECh 0008 70EDh 0008 70EEh 0008 70EFh 0008 70F0h 0008 70F1h 0008 70F6h 0008 70F7h 0008 70F8h 0008 70F9h 0008 70FAh 0008 70FBh 0008 70FCh 0008 70FDh 0008 711Ch 0008 711Dh 0008 711Eh 0008 711Fh 0008 7140h 0008 7141h 0008 7142h 0008 7143h 0008 7144h 0008 7145h 0008 7146h 0008 7147h 0008 7148h 0008 7149h 0008 714Ah 0008 714Bh 0008 714Ch 0008 714Dh 0008 714Eh 0008 714Fh 0008 7162h 0008 7163h 0008 7164h 0008 7165h 0008 7168h 0008 7169h 0008 716Ah 0008 716Bh Abbreviation Register Name ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU Interrupt request register 233 Interrupt request register 234 Interrupt request register 235 Interrupt request register 236 Interrupt request register 237 Interrupt request register 238 Interrupt request register 239 Interrupt request register 240 Interrupt request register 241 Interrupt request register 246 Interrupt request register 247 Interrupt request register 248 Interrupt request register 249 Interrupt request register 250 Interrupt request register 251 Interrupt request register 252 Interrupt request register 253 Interrupt request destination setting register 028 Interrupt request destination setting register 029 Interrupt request destination setting register 030 Interrupt request destination setting register 031 Interrupt request destination setting register 064 Interrupt request destination setting register 065 Interrupt request destination setting register 066 Interrupt request destination setting register 067 Interrupt request destination setting register 068 Interrupt request destination setting register 069 Interrupt request destination setting register 070 Interrupt request destination setting register 071 Interrupt request destination setting register 072 Interrupt request destination setting register 073 Interrupt request destination setting register 074 Interrupt request destination setting register 075 Interrupt request destination setting register 076 Interrupt request destination setting register 077 Interrupt request destination setting register 078 Interrupt request destination setting register 079 Interrupt request destination setting register 098 Interrupt request destination setting register 099 Interrupt request destination setting register 100 Interrupt request destination setting register 101 Interrupt request destination setting register 104 Interrupt request destination setting register 105 Interrupt request destination setting register 106 Interrupt request destination setting register 107 Abbreviation of Bits IR233 IR234 IR235 IR236 IR237 IR238 IR239 IR240 IR241 IR246 IR247 IR248 IR249 IR250 IR251 IR252 IR253 ISELR028 ISELR029 ISELR030 ISELR031 ISELR064 ISELR065 ISELR066 ISELR067 ISELR068 ISELR069 ISELR070 ISELR071 ISELR072 ISELR073 ISELR074 ISELR075 ISELR076 ISELR077 ISELR078 ISELR079 ISELR098 ISELR099 ISELR100 ISELR101 ISELR104 ISELR105 ISELR106 ISELR107 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 39 of 83 RX610 Group 4. I/O Registers Number of Module Register Number Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access Cycles 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK Address 0008 716Fh 0008 7170h 0008 7175h 0008 7176h 0008 717Ah 0008 717Bh 0008 717Ch 0008 717Dh 0008 717Fh 0008 7180h 0008 7185h 0008 7186h 0008 718Ah 0008 718Bh 0008 718Ch 0008 718Dh 0008 7191h 0008 7192h 0008 7197h 0008 7198h 0008 719Ch 0008 719Dh 0008 719Eh 0008 719Fh 0008 71A1h 0008 71A2h 0008 71A7h 0008 71A8h 0008 71AEh 0008 71AFh 0008 71B1h 0008 71B2h 0008 71B4h 0008 71B5h 0008 71B7h 0008 71B8h 0008 71C6h 0008 71C7h 0008 71C8h 0008 71C9h 0008 71D7h 0008 71D8h 0008 71DBh 0008 71DCh 0008 71DFh Abbreviation Register Name ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU Interrupt request destination setting register 111 Interrupt request destination setting register 112 Interrupt request destination setting register 117 Interrupt request destination setting register 118 Interrupt request destination setting register 122 Interrupt request destination setting register 123 Interrupt request destination setting register 124 Interrupt request destination setting register 125 Interrupt request destination setting register 127 Interrupt request destination setting register 128 Interrupt request destination setting register 133 Interrupt request destination setting register 134 Interrupt request destination setting register 138 Interrupt request destination setting register 139 Interrupt request destination setting register 140 Interrupt request destination setting register 141 Interrupt request destination setting register 145 Interrupt request destination setting register 146 Interrupt request destination setting register 151 Interrupt request destination setting register 152 Interrupt request destination setting register 156 Interrupt request destination setting register 157 Interrupt request destination setting register 158 Interrupt request destination setting register 159 Interrupt request destination setting register 161 Interrupt request destination setting register 162 Interrupt request destination setting register 167 Interrupt request destination setting register 168 Interrupt request destination setting register 174 Interrupt request destination setting register 175 Interrupt request destination setting register 177 Interrupt request destination setting register 178 Interrupt request destination setting register 180 Interrupt request destination setting register 181 Interrupt request destination setting register 183 Interrupt request destination setting register 184 Interrupt request destination setting register 198 Interrupt request destination setting register 199 Interrupt request destination setting register 200 Interrupt request destination setting register 201 Interrupt request destination setting register 215 Interrupt request destination setting register 216 Interrupt request destination setting register 219 Interrupt request destination setting register 220 Interrupt request destination setting register 223 Abbreviation of Bits ISELR111 ISELR112 ISELR117 ISELR118 ISELR122 ISELR123 ISELR124 ISELR125 ISELR127 ISELR128 ISELR133 ISELR134 ISELR138 ISELR139 ISELR140 ISELR141 ISELR145 ISELR146 ISELR151 ISELR152 ISELR156 ISELR157 ISELR158 ISELR159 ISELR161 ISELR162 ISELR167 ISELR168 ISELR174 ISELR175 ISELR177 ISELR178 ISELR180 ISELR181 ISELR183 ISELR184 ISELR198 ISELR199 ISELR200 ISELR201 ISELR215 ISELR216 ISELR219 ISELR220 ISELR223 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 40 of 83 RX610 Group 4. I/O Registers Number of Module Register Number Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access Cycles 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK Address 0008 71E0h 0008 71E3h 0008 71E4h 0008 71E7h 0008 71E8h 0008 71EBh 0008 71ECh 0008 71EFh 0008 71F0h 0008 71F7h 0008 71F8h 0008 71FBh 0008 71FCh 0008 71FDh 0008 7202h 0008 7203h 0008 7208h 0008 7209h 0008 720Ch 0008 720Dh 0008 720Eh 0008 720Fh 0008 7210h 0008 7211h 0008 7212h 0008 7213h 0008 7214h 0008 7215h 0008 7216h 0008 7217h 0008 7218h 0008 7219h 0008 721Ah 0008 721Bh 0008 721Ch 0008 721Dh 0008 721Eh 0008 721Fh 0008 7300h 0008 7301h 0008 7302h 0008 7304h 0008 7305h 0008 7306h 0008 7307h Abbreviation Register Name ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU Interrupt request destination setting register 224 Interrupt request destination setting register 227 Interrupt request destination setting register 228 Interrupt request destination setting register 231 Interrupt request destination setting register 232 Interrupt request destination setting register 235 Interrupt request destination setting register 236 Interrupt request destination setting register 239 Interrupt request destination setting register 240 Interrupt request destination setting register 247 Interrupt request destination setting register 248 Interrupt request destination setting register 251 Interrupt request destination setting register 252 Interrupt request destination setting register 253 Interrupt request enable register 02 Interrupt request enable register 03 Interrupt request enable register 08 Interrupt request enable register 09 Interrupt request enable register 0C Interrupt request enable register 0D Interrupt request enable register 0E Interrupt request enable register 0F Interrupt request enable register 10 Interrupt request enable register 11 Interrupt request enable register 12 Interrupt request enable register 13 Interrupt request enable register 14 Interrupt request enable register 15 Interrupt request enable register 16 Interrupt request enable register 17 Interrupt request enable register 18 Interrupt request enable register 19 Interrupt request enable register 1A Interrupt request enable register 1B Interrupt request enable register 1C Interrupt request enable register 1D Interrupt request enable register 1E Interrupt request enable register 1F Interrupt priority register 00 Interrupt priority register 01 Interrupt priority register 02 Interrupt priority register 04 Interrupt priority register 05 Interrupt priority register 06 Interrupt priority register 07 Abbreviation of Bits ISELR224 ISELR227 ISELR228 ISELR231 ISELR232 ISELR235 ISELR236 ISELR239 ISELR240 ISELR247 ISELR248 ISELR251 ISELR252 ISELR253 IER02 IER03 IER08 IER09 IER0C IER0D IER0E IER0F IER10 IER11 IER12 IER13 IER14 IER15 IER16 IER17 IER18 IER19 IER1A IER1B IER1C IER1D IER1E IER1F IPR00 IPR01 IPR02 IPR04 IPR05 IPR06 IPR07 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 41 of 83 RX610 Group 4. I/O Registers Number of Module Register Number Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access Cycles 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK Address 0008 7320h 0008 7321h 0008 7322h 0008 7323h 0008 7324h 0008 7325h 0008 7326h 0008 7327h 0008 7328h 0008 7329h 0008 732Ah 0008 732Bh 0008 732Ch 0008 732Dh 0008 732Eh 0008 732Fh 0008 7340h 0008 7344h 0008 7345h 0008 7346h 0008 7347h 0008 734Ch 0008 734Dh 0008 734Eh 0008 734Fh 0008 7350h 0008 7351h 0008 7352h 0008 7353h 0008 7354h 0008 7355h 0008 7356h 0008 7357h 0008 7358h 0008 7359h 0008 735Ah 0008 735Bh 0008 735Ch 0008 735Dh 0008 735Eh 0008 735Fh 0008 7360h 0008 7361h 0008 7362h 0008 7363h Abbreviation Register Name ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU Interrupt priority register 20 Interrupt priority register 21 Interrupt priority register 22 Interrupt priority register 23 Interrupt priority register 24 Interrupt priority register 25 Interrupt priority register 26 Interrupt priority register 27 Interrupt priority register 28 Interrupt priority register 29 Interrupt priority register 2A Interrupt priority register 2B Interrupt priority register 2C Interrupt priority register 2D Interrupt priority register 2E Interrupt priority register 2F Interrupt priority register 40 Interrupt priority register 44 Interrupt priority register 45 Interrupt priority register 46 Interrupt priority register 47 Interrupt priority register 4C Interrupt priority register 4D Interrupt priority register 4E Interrupt priority register 4F Interrupt priority register 50 Interrupt priority register 51 Interrupt priority register 52 Interrupt priority register 53 Interrupt priority register 54 Interrupt priority register 55 Interrupt priority register 56 Interrupt priority register 57 Interrupt priority register 58 Interrupt priority register 59 Interrupt priority register 5A Interrupt priority register 5B Interrupt priority register 5C Interrupt priority register 5D Interrupt priority register 5E Interrupt priority register 5F Interrupt priority register 60 Interrupt priority register 61 Interrupt priority register 62 Interrupt priority register 63 Abbreviation of Bits IPR20 IPR21 IPR22 IPR23 IPR24 IPR25 IPR26 IPR27 IPR28 IPR29 IPR2A IPR2B IPR2C IPR2D IPR2E IPR2F IPR40 IPR44 IPR45 IPR46 IPR47 IPR4C IPR4D IPR4E IPR4F IPR50 IPR51 IPR52 IPR53 IPR54 IPR55 IPR56 IPR57 IPR58 IPR59 IPR5A IPR5B IPR5C IPR5D IPR5E IPR5F IPR60 IPR61 IPR62 IPR63 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 42 of 83 RX610 Group 4. I/O Registers Number of Module Register Number Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 32 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 16 8 Access Cycles 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 to 3 PCLK * 7 7 Address 0008 7368h 0008 7369h 0008 736Ah 0008 736Bh 0008 7370h 0008 7371h 0008 7372h 0008 7373h 0008 7380h 0008 7381h 0008 7382h 0008 7383h 0008 7384h 0008 7385h 0008 7386h 0008 7388h 0008 7389h 0008 738Ah 0008 738Bh 0008 738Ch 0008 738Dh 0008 738Eh 0008 738Fh 0008 73F0h 0008 7400h 0008 7404h 0008 7408h 0008 740Ch 0008 8000h 0008 8002h 0008 8004h 0008 8006h 0008 8008h 0008 800Ah 0008 800Ch 0008 8010h 0008 8012h 0008 8014h 0008 8016h 0008 8018h 0008 801Ah 0008 801Ch 0008 8028h 0008 8028h 0008 8029h Abbreviation Register Name ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU DTC DTC DTC DTC CMT (unit 0) CMT0 CMT0 CMT0 CMT1 CMT1 CMT1 CMT (unit 1) CMT2 CMT2 CMT2 CMT3 CMT3 CMT3 WDT WDT WDT Interrupt priority register 68 Interrupt priority register 69 Interrupt priority register 6A Interrupt priority register 6B Interrupt priority register 70 Interrupt priority register 71 Interrupt priority register 72 Interrupt priority register 73 Interrupt priority register 80 Interrupt priority register 81 Interrupt priority register 82 Interrupt priority register 83 Interrupt priority register 84 Interrupt priority register 85 Interrupt priority register 86 Interrupt priority register 88 Interrupt priority register 89 Interrupt priority register 8A Interrupt priority register 8B Interrupt priority register 8C Interrupt priority register 8D Interrupt priority register 8E Interrupt priority register 8F Fast interrupt register DTC control register DTC vector base register DTC address mode register DTC module start register Compare match timer start register 0 Compare match timer control register Compare match timer counter Compare match timer constant register Compare match timer control register Compare match timer counter Compare match timer constant register Compare match timer start register 1 Compare match timer control register Compare match timer counter Compare match timer constant register Compare match timer control register Compare match timer counter Compare match timer constant register Timer control/status register Write window A register Timer counter Abbreviation of Bits IPR68 IPR69 IPR6A IPR6B IPR70 IPR71 IPR72 IPR73 IPR80 IPR81 IPR82 IPR83 IPR84 IPR85 IPR86 IPR88 IPR89 IPR8A IPR8B IPR8C IPR8D IPR8E IPR8F FIR DTCCR DTCVBR DTCADMOD DTCST CMSTR0 CMCR CMCNT CMCOR CMCR CMCNT CMCOR CMSTR1 CMCR CMCNT CMCOR CMCR CMCNT CMCOR TCSR WINA TCNT 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 32 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 16 8 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 43 of 83 RX610 Group 4. I/O Registers Number of Module Register Number Access Size 16 8 16 16 16 16 8 8 8 8 16 16 16 16 8 8 8 8 16 16 16 16 8 8 8 8 16 16 16 16 8 8 8 8 16 16 8 8 8 8 8 8 8 8 8 Access Cycles 2 to 3 PCLK * 7 7 Address 0008 802Ah 0008 802Bh 0008 8040h 0008 8042h 0008 8044h 0008 8046h 0008 8050h 0008 8051h 0008 8052h 0008 8053h 0008 8060h 0008 8062h 0008 8064h 0008 8066h 0008 8070h 0008 8071h 0008 8072h 0008 8073h 0008 8080h 0008 8082h 0008 8084h 0008 8086h 0008 8090h 0008 8091h 0008 8092h 0008 8093h 0008 80A0h 0008 80A2h 0008 80A4h 0008 80A6h 0008 80B0h 0008 80B1h 0008 80B2h 0008 80B3h 0008 80C0h 0008 80C2h 0008 80C4h 0008 80C5h 0008 8100h 0008 8101h 0008 8110h 0008 8111h 0008 8112h 0008 8113h 0008 8114h Abbreviation Register Name WDT WDT AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD2 AD2 AD2 AD2 AD2 AD2 AD2 AD2 AD3 AD3 AD3 AD3 AD3 AD3 AD3 AD3 D/A D/A D/A D/A TPU (unit 0) TPU (unit 0) TPU0 TPU0 TPU0 TPU0 TPU0 Write window B register Reset control/status register A/D data register A A/D data register B A/D data register C A/D data register D A/D control/status register A/D control register ADDRy format select register A/D sampling state register A/D data register A A/D data register B A/D data register C A/D data register D A/D control/status register A/D control register ADDRy format select register A/D sampling state register A/D data register A A/D data register B A/D data register C A/D data register D A/D control/status register A/D control register ADDRy format select register A/D sampling state register A/D data register A A/D data register B A/D data register C A/D data register D A/D control/status register A/D control register ADDRy format select register A/D sampling state register D/A data register 0 D/A data register 1 D/A control register DADRy format select register Timer start register Timer synchronous register Timer control register Timer mode register Timer I/O control register H Timer I/O control register L Timer interrupt enable register Abbreviation of Bits WINB RSTCSR ADDRA ADDRB ADDRC ADDRD ADCSR ADCR ADDPR ADSSTR ADDRA ADDRB ADDRC ADDRD ADCSR ADCR ADDPR ADSSTR ADDRA ADDRB ADDRC ADDRD ADCSR ADCR ADDPR ADSSTR ADDRA ADDRB ADDRC ADDRD ADCSR ADCR ADDPR ADSSTR DADR0 DADR1 DACR DADPR TSTRA TSYRA TCR TMDR TIORH TIORL TIER 16 8 16 16 16 16 8 8 8 8 16 16 16 16 8 8 8 8 16 16 16 16 8 8 8 8 16 16 16 16 8 8 8 8 16 16 8 8 8 8 8 8 8 8 8 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 44 of 83 RX610 Group 4. I/O Registers Number of Module Register Number Access Size 8 16 16 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 Access Cycles 2 to 3 PCLK * 7 7 Address 0008 8115h 0008 8116h 0008 8118h 0008 811Ah 0008 811Ch 0008 811Eh 0008 8120h 0008 8121h 0008 8122h 0008 8124h 0008 8125h 0008 8126h 0008 8128h 0008 812Ah 0008 8130h 0008 8131h 0008 8132h 0008 8134h 0008 8135h 0008 8136h 0008 8138h 0008 813Ah 0008 8140h 0008 8141h 0008 8142h 0008 8143h 0008 8144h 0008 8145h 0008 8146h 0008 8148h 0008 814Ah 0008 814Ch 0008 814Eh 0008 8150h 0008 8151h 0008 8152h 0008 8154h 0008 8155h 0008 8156h 0008 8158h 0008 815Ah 0008 8160h 0008 8161h 0008 8162h 0008 8164h Abbreviation Register Name TPU0 TPU0 TPU0 TPU0 TPU0 TPU0 TPU1 TPU1 TPU1 TPU1 TPU1 TPU1 TPU1 TPU1 TPU2 TPU2 TPU2 TPU2 TPU2 TPU2 TPU2 TPU2 TPU3 TPU3 TPU3 TPU3 TPU3 TPU3 TPU3 TPU3 TPU3 TPU3 TPU3 TPU4 TPU4 TPU4 TPU4 TPU4 TPU4 TPU4 TPU4 TPU5 TPU5 TPU5 TPU5 Timer status register Timer counter Timer general register A Timer general register B Timer general register C Timer general register D Timer control register Timer mode register Timer I/O control register Timer interrupt enable register Timer status register Timer counter Timer general register A Timer general register B Timer control register Timer mode register Timer I/O control register Timer interrupt enable register Timer status register Timer counter Timer general register A Timer general register B Timer control register Timer mode register Timer I/O control register H Timer I/O control register L Timer interrupt enable register Timer status register Timer counter Timer general register A Timer general register B Timer general register C Timer general register D Timer control register Timer mode register Timer I/O control register Timer interrupt enable register Timer status register Timer counter Timer general register A Timer general register B Timer control register Timer mode register Timer I/O control register Timer interrupt enable register Abbreviation of Bits TSR TCNT TGRA TGRB TGRC TGRD TCR TMDR TIOR TIER TSR TCNT TGRA TGRB TCR TMDR TIOR TIER TSR TCNT TGRA TGRB TCR TMDR TIORH TIORL TIER TSR TCNT TGRA TGRB TGRC TGRD TCR TMDR TIOR TIER TSR TCNT TGRA TGRB TCR TMDR TIOR TIER 8 16 16 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 45 of 83 RX610 Group 4. I/O Registers Number of Module Register Number Access Size 8 16 16 16 8 8 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 8 16 16 16 16 16 8 Access Cycles 2 to 3 PCLK * 7 7 Address 0008 8165h 0008 8166h 0008 8168h 0008 816Ah 0008 8170h 0008 8171h 0008 8180h 0008 8181h 0008 8182h 0008 8183h 0008 8184h 0008 8185h 0008 8186h 0008 8188h 0008 818Ah 0008 818Ch 0008 818Eh 0008 8190h 0008 8191h 0008 8192h 0008 8194h 0008 8195h 0008 8196h 0008 8198h 0008 819Ah 0008 81A0h 0008 81A1h 0008 81A2h 0008 81A4h 0008 81A5h 0008 81A6h 0008 81A8h 0008 81AAh 0008 81B0h 0008 81B1h 0008 81B2h 0008 81B3h 0008 81B4h 0008 81B5h 0008 81B6h 0008 81B8h 0008 81BAh 0008 81BCh 0008 81BEh 0008 81C0h Abbreviation Register Name TPU5 TPU5 TPU5 TPU5 TPU (unit 1) TPU (unit 1) TPU6 TPU6 TPU6 TPU6 TPU6 TPU6 TPU6 TPU6 TPU6 TPU6 TPU6 TPU7 TPU7 TPU7 TPU7 TPU7 TPU7 TPU7 TPU7 TPU8 TPU8 TPU8 TPU8 TPU8 TPU8 TPU8 TPU8 TPU9 TPU9 TPU9 TPU9 TPU9 TPU9 TPU9 TPU9 TPU9 TPU9 TPU9 TPU10 Timer status register Timer counter Timer general register A Timer general register B Timer start register Timer synchronous register Timer control register Timer mode register Timer I/O control register H Timer I/O control register L Timer interrupt enable register Timer status register Timer counter Timer general register A Timer general register B Timer general register C Timer general register D Timer control register Timer mode register Timer I/O control register Timer interrupt enable register Timer status register Timer counter Timer general register A Timer general register B Timer control register Timer mode register Timer I/O control register Timer interrupt enable register Timer status register Timer counter Timer general register A Timer general register B Timer control register Timer mode register Timer I/O control register H Timer I/O control register L Timer interrupt enable register Timer status register Timer counter Timer general register A Timer general register B Timer general register C Timer general register D Timer control register Abbreviation of Bits TSR TCNT TGRA TGRB TSTRB TSYRB TCR TMDR TIORH TIORL TIER TSR TCNT TGRA TGRB TGRC TGRD TCR TMDR TIOR TIER TSR TCNT TGRA TGRB TCR TMDR TIOR TIER TSR TCNT TGRA TGRB TCR TMDR TIORH TIORL TIER TSR TCNT TGRA TGRB TGRC TGRD TCR 8 16 16 16 8 8 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 8 16 16 16 16 16 8 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 46 of 83 RX610 Group 4. I/O Registers Number of Module Register Number Access Size 8 8 8 8 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 or 16 8 or 16* 8 or 16 8 or 16* 8 or 16 5 5 Access Cycles 2 to 3 PCLK * 7 7 Address 0008 81C1h 0008 81C2h 0008 81C4h 0008 81C5h 0008 81C6h 0008 81C8h 0008 81CAh 0008 81D0h 0008 81D1h 0008 81D2h 0008 81D4h 0008 81D5h 0008 81D6h 0008 81D8h 0008 81DAh 0008 81E6h 0008 81E7h 0008 81E8h 0008 81E9h 0008 81EAh 0008 81EBh 0008 81Ech* 1 2 Abbreviation Register Name TPU10 TPU10 TPU10 TPU10 TPU10 TPU10 TPU10 TPU11 TPU11 TPU11 TPU11 TPU11 TPU11 TPU11 TPU11 PPG0 PPG0 PPG0 PPG0 PPG0 PPG0 PPG0 PPG0 PPG0 PPG0 PPG1 PPG1 PPG1 PPG1 PPG1 PPG1 PPG1 3 4 Abbreviation of Bits TMDR TIOR TIER TSR TCNT TGRA TGRB TCR TMDR TIOR TIER TSR TCNT TGRA TGRB PCR PMR NDERH NDERL PODRH PODRL NDRH NDRL NDRH NDRL PTRSLR PCR PMR NDERH NDERL PODRH PODRL NDRH NDRL NDRH NDRL TCR TCR TCSR TCSR TCORA TCORA TCORB TCORB TCNT 8 8 8 8 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Timer mode register Timer I/O control register Timer interrupt enable register Timer status register Timer counter Timer general register A Timer general register B Timer control register Timer mode register Timer I/O control register Timer interrupt enable register Timer status register Timer counter Timer general register A Timer general register B PPG output control register PPG output mode register Next data enable register H Next data enable register L Output data register H Output data register L Next data register H Next data register L Next data register H Next data register L PPG trigger select register PPG output control register PPG output mode register Next data enable register H Next data enable register L Output data register H Output data register L Next data register H Next data register L Next data register H Next data register L Timer control register Timer control register Timer control/status register Timer control/status register Time constant register A Time constant register A Time constant register B Time constant register B Timer counter 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 0008 81EDh* 0008 81EEh* 0008 81EFh* 0008 81F0h 0008 81F6h 0008 81F7h 0008 81F8h 0008 81F9h 0008 81FAh 0008 81FBh 0008 81FCh* 0008 81FDh* 0008 81FEh* 0008 81FFh* 0008 8200h 0008 8201h 0008 8202h 0008 8203h 0008 8204h 0008 8205h 0008 8206h 0008 8207h 0008 8208h 2 to 3 PCLK * 2 to 3 PCLK 1 *7 7 2 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 PPG1 PPG1 PPG1 PPG1 TMR0 TMR1 TMR0 TMR1 TMR0 TMR1 TMR0 TMR1 TMR0 2 to 3 PCLK * 2 to 3 PCLK *7 7 3 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 4 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 47 of 83 RX610 Group 4. I/O Registers Number of Module Register Number Access Size 8 or 16* 8 or 16 8 or 16 8 8 8 8 8 or 16 8 or 16* 8 or 16 8 or 16* 8 or 16 8 or 16* 8 or 16 8 or 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 5 5 5 5 Access Cycles 2 to 3 PCLK * 7 7 Address 0008 8209h 0008 820Ah 0008 820Bh 0008 8210h 0008 8211h 0008 8212h 0008 8213h 0008 8214h 0008 8215h 0008 8216h 0008 8217h 0008 8218h 0008 8219h 0008 821Ah 0008 821Bh 0008 8240h 0008 8241h 0008 8242h 0008 8243h 0008 8244h 0008 8245h 0008 8246h 0008 8247h 0008 8248h 0008 8249h 0008 824Ah 0008 824Bh 0008 824Ch 0008 824Dh 0008 824Eh 0008 824Fh 0008 8250h 0008 8251h 0008 8252h 0008 8253h 0008 8254h 0008 8255h 0008 8256h 0008 8257h 0008 8258h 0008 8259h 0008 825Ah 0008 825Bh 0008 825Ch 0008 825Dh Abbreviation Register Name TMR1 TMR0 TMR1 TMR2 TMR3 TMR2 TMR3 TMR2 TMR3 TMR2 TMR3 TMR2 TMR3 TMR2 TMR3 SCI0 SCI0 SCI0 SCI0 SCI0 SCI0 SCI0 SCI0 SCI1 SCI1 SCI1 SCI1 SCI1 SCI1 SCI1 SCI1 SCI2 SCI2 SCI2 SCI2 SCI2 SCI2 SCI2 SCI2 SCI3 SCI3 SCI3 SCI3 SCI3 SCI3 Timer counter Timer counter control register Timer counter control register Timer control register Timer control register Timer control/status register Timer control/status register Time constant register A Time constant register A Time constant register B Time constant register B Timer counter Timer counter Timer counter control register Timer counter control register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial extended mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial extended mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial extended mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Abbreviation of Bits TCNT TCCR TCCR TCR TCR TCSR TCSR TCORA TCORA TCORB TCORB TCNT TCNT TCCR TCCR SMR* BRR SCR* TDR SSR* RDR SCMR SEMR SMR* BRR SCR* TDR SSR* RDR SCMR SEMR SMR* BRR SCR* TDR SSR* RDR SCMR SEMR SMR* BRR SCR* TDR SSR* RDR 6 6 6 6 6 6 6 6 6 6 6 6 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 48 of 83 RX610 Group 4. I/O Registers Number of Module Register Number Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access Cycles 2 to 3 PCLK * 7 7 Address 0008 825Eh 0008 825Fh 0008 8260h 0008 8261h 0008 8262h 0008 8263h 0008 8264h 0008 8265h 0008 8266h 0008 8267h 0008 8268h 0008 8269h 0008 826Ah 0008 826Bh 0008 826Ch 0008 826Dh 0008 826Eh 0008 826Fh 0008 8270h 0008 8271h 0008 8272h 0008 8273h 0008 8274h 0008 8275h 0008 8276h 0008 8277h 0008 8280h 0008 8281h 0008 8282h 0008 8300h 0008 8301h 0008 8302h 0008 8303h 0008 8304h 0008 8305h 0008 8306h 0008 8307h 0008 8308h 0008 8309h 0008 830Ah 0008 830Bh 0008 830Ch 0008 830Dh 0008 830Eh 0008 830Fh Abbreviation Register Name SCI3 SCI3 SCI4 SCI4 SCI4 SCI4 SCI4 SCI4 SCI4 SCI4 SCI5 SCI5 SCI5 SCI5 SCI5 SCI5 SCI5 SCI5 SCI6 SCI6 SCI6 SCI6 SCI6 SCI6 SCI6 SCI6 CRC CRC CRC RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 Smart card mode register Serial extended mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial extended mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial extended mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial extended mode register CRC control register CRC data input register CRC data output register I C bus control register 1 I C bus control register 2 I C bus mode register 1 I C bus mode register 2 I C bus mode register 3 I C bus function enable register I C bus status enable register I C bus interrupt enable register I C bus status register 1 I C bus status register 2 Slave address register L0 Slave address register U0 Slave address register L1 Slave address register U1 Slave address register L2 Slave address register U2 2 2 2 2 2 2 2 2 2 2 Abbreviation of Bits SCMR SEMR SMR* BRR SCR* TDR SSR* RDR SCMR SEMR SMR* BRR SCR* TDR SSR* RDR SCMR SEMR SMR* BRR SCR* TDR SSR* RDR SCMR SEMR CRCCR CRCDIR CRCDOR ICCR1 ICCR2 ICMR1 ICMR2 ICMR3 ICFER ICSER ICIER ICSR1 ICSR2 SARL0 SARU0 SARL1 SARU1 SARL2 SARU2 6 6 6 6 6 6 6 6 6 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 49 of 83 RX610 Group 4. I/O Registers Number of Module Register 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Number Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access Cycles 2 to 3 PCLK * 7 7 Address 0008 8310h 0008 8311h 0008 8312h 0008 8313h 0008 8320h 0008 8321h 0008 8322h 0008 8323h 0008 8324h 0008 8325h 0008 8326h 0008 8327h 0008 8328h 0008 8329h 0008 832Ah 0008 832Bh 0008 832Ch 0008 832Dh 0008 832Eh 0008 832Fh 0008 8330h 0008 8331h 0008 8332h 0008 8333h 0008 C000h 0008 C001h 0008 C002h 0008 C003h 0008 C004h 0008 C005h 0008 C006h 0008 C007h 0008 C008h 0008 C009h 0008 C00Ah 0008 C00Bh 0008 C00Ch 0008 C00Dh 0008 C00Eh 0008 C00Fh 0008 C010h 0008 C011h 0008 C020h 0008 C021h 0008 C022h Abbreviation Register Name RIIC0 RIIC0 RIIC0 RIIC0 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH P0 P1 P2 I C bus bit rate low-level register I C bus bit rate high-level register I C bus transmit data register I C bus receive data register I C bus control register 1 I C bus control register 2 I C bus mode register 1 I C bus mode register 2 I C bus mode register 3 I C bus function enable register I C bus status enable register I C bus interrupt enable register I C bus status register 1 I C bus status register 2 Slave address register L0 Slave address register U0 Slave address register L1 Slave address register U1 Slave address register L2 Slave address register U2 I C bus bit rate low-level register I C bus bit rate high-level register I C bus transmit data register I C bus receive data register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data register Data register Data register 2 2 2 2 Abbreviation of Bits ICBRL ICBRH ICDRT ICDRR ICCR1 ICCR2 ICMR1 ICMR2 ICMR3 ICFER ICSER ICIER ICSR1 ICSR2 SARL0 SARU0 SARL1 SARU1 SARL2 SARU2 ICBRL ICBRH ICDRT ICDRR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DR DR DR 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 50 of 83 RX610 Group 4. I/O Registers Number of Module Register Number Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access Cycles 2 to 3 PCLK * 7 7 Address 0008 C023h 0008 C024h 0008 C025h 0008 C026h 0008 C027h 0008 C028h 0008 C029h 0008 C02Ah 0008 C02Bh 0008 C02Ch 0008 C02Dh 0008 C02Eh 0008 C02Fh 0008 C030h 0008 C031h 0008 C040h 0008 C041h 0008 C042h 0008 C043h 0008 C044h 0008 C045h 0008 C046h 0008 C047h 0008 C048h 0008 C049h 0008 C04Ah 0008 C04Bh 0008 C04Ch 0008 C04Dh 0008 C04Eh 0008 C04Fh 0008 C050h 0008 C051h 0008 C060h 0008 C061h 0008 C062h 0008 C063h 0008 C064h 0008 C065h 0008 C066h 0008 C067h 0008 C068h 0008 C069h 0008 C06Ah 0008 C06Bh Abbreviation Register Name P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB Data register Data register Data register Data register Data register Data register Data register Data register Data register Data register Data register Data register Data register Data register Data register Port register Port register Port register Port register Port register Port register Port register Port register Port register Port register Port register Port register Port register Port register Port register Port register Port register Port register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Abbreviation of Bits DR DR DR DR DR DR DR DR DR DR DR DR DR DR DR PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT ICR ICR ICR ICR ICR ICR ICR ICR ICR ICR ICR ICR 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 51 of 83 RX610 Group 4. I/O Registers Number of Module Register Number Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access Cycles 2 to 3 PCLK * 7 7 Address 0008 C06Ch 0008 C06Dh 0008 C06Eh 0008 C06Fh 0008 C070h 0008 C071h 0008 C082h 0008 C08Ch 0008 C0CAh 0008 C0CBh 0008 C0CCh 0008 C0CDh 0008 C0CEh 0008 C100h 0008 C101h 0008 C102h 0008 C103h 0008 C104h 0008 C105h 0008 C106h 0008 C107h 0008 C108h 0008 C109h 0008 C280h 0008 C281h 0008 C282h 0008 C283h 0008 C284h 0008 C285h 0008 C289h 0008 C290h 0008 C291h 0008 C292h 0008 C293h 0008 C294h 0008 C295h 0008 C296h 0008 C297h 0008 C298h 0008 C299h 0008 C29Ah 0008 C29Bh 0008 C29Ch 0008 C29Dh 0008 C29Eh Abbreviation Register Name PC PD PE PF PG PH P2 PC PA PB PC PD PE I/O PORT I/O PORT I/O PORT I/O PORT I/O PORT I/O PORT I/O PORT I/O PORT I/O PORT I/O PORT SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM FLASH SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Open drain control register Open drain control register Pull-Up resistor control register Pull-Up resistor control register Pull-Up resistor control register Pull-Up resistor control register Pull-Up resistor control register Port function control register 0 Port function control register 1 Port function control register 2 Port function control register 3 Port function control register 4 Port function control register 5 Port function control register 6 Port function control register 7 Port function control register 8 Port function control register 9 Deep standby control register Deep standby wait control register Deep standby interrupt enable register Deep standby interrupt flag register Deep standby interrupt edge register Reset status register Flash write erase protection register Deep standby backup register 0 Deep standby backup register 1 Deep standby backup register 2 Deep standby backup register 3 Deep standby backup register 4 Deep standby backup register 5 Deep standby backup register 6 Deep standby backup register 7 Deep standby backup register 8 Deep standby backup register 9 Deep standby backup register 10 Deep standby backup register 11 Deep standby backup register 12 Deep standby backup register 13 Deep standby backup register 14 Abbreviation of Bits ICR ICR ICR ICR ICR ICR ODR ODR PCR PCR PCR PCR PCR PFCR0 PFCR1 PFCR2 PFCR3 PFCR4 PFCR5 PFCR6 PFCR7 PFCR8 PFCR9 DPSBYCR DPSWCR DPSIER DPSIFR DPSIEGR RSTSR FWEPROR DPSBKR0 DPSBKR1 DPSBKR2 DPSBKR3 DPSBKR4 DPSBKR5 DPSBKR6 DPSBKR7 DPSBKR8 DPSBKR9 DPSBKR10 DPSBKR11 DPSBKR12 DPSBKR13 DPSBKR14 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 4 to 5 PCLK *7 7 7 7 7 4 to 5 PCLK * 4 to 5 PCLK * 4 to 5 PCLK * 4 to 5 PCLK * 4 to 5 PCLK *7 7 7 4 to 5 PCLK * 4 to 5 PCLK * 4 to 5 PCLK *7 7 7 7 7 4 to 5 PCLK * 4 to 5 PCLK * 4 to 5 PCLK * 4 to 5 PCLK * 4 to 5 PCLK *7 7 7 4 to 5 PCLK * 4 to 5 PCLK * 4 to 5 PCLK *7 7 7 4 to 5 PCLK * 4 to 5 PCLK * 4 to 5 PCLK 4 to 5 PCLK *7 *7 7 4 to 5 PCLK * R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 52 of 83 RX610 Group 4. I/O Registers Number of Module Register Number Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access Cycles 4 to 5 PCLK * 4 to 5 PCLK * 4 to 5 PCLK * 4 to 5 PCLK * 4 to 5 PCLK 7 7 7 7 Address 0008 C29Fh 0008 C2A0h 0008 C2A1h 0008 C2A2h 0008 C2A3h 0008 C2A4h 0008 C2A5h 0008 C2A6h 0008 C2A7h 0008 C2A8h 0008 C2A9h 0008 C2AAh 0008 C2ABh 0008 C2ACh 0008 C2ADh 0008 C2AEh 0008 C2AFh 0008 C300h 0008 C301h 0008 C302h 0008 C303h 0008 C304h 0008 C305h 0008 C306h 0008 C307h 0008 C308h 0008 C309h 0008 C30Ah 0008 C30Bh 0008 C30Ch 0008 C30Dh 0008 C30Eh 0008 C30Fh 0008 C320h 0008 C321h 0008 C322h 0008 C323h 0008 C324h 0008 C325h 0008 C326h 0008 C327h 0008 C328h 0008 C329h 0008 C32Ah 0008 C32Bh Abbreviation Register Name SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU Deep standby backup register 15 Deep standby backup register 16 Deep standby backup register 17 Deep standby backup register 18 Deep standby backup register 19 Deep standby backup register 20 Deep standby backup register 21 Deep standby backup register 22 Deep standby backup register 23 Deep standby backup register 24 Deep standby backup register 25 Deep standby backup register 26 Deep standby backup register 27 Deep standby backup register 28 Deep standby backup register 29 Deep standby backup register 30 Deep standby backup register 31 IRQ detection enable registrar 0 IRQ detection enable registrar 1 IRQ detection enable registrar 2 IRQ detection enable registrar 3 IRQ detection enable registrar 4 IRQ detection enable registrar 5 IRQ detection enable registrar 6 IRQ detection enable registrar 7 IRQ detection enable registrar 8 IRQ detection enable registrar 9 IRQ detection enable registrar 10 IRQ detection enable registrar 11 IRQ detection enable registrar 12 IRQ detection enable registrar 13 IRQ detection enable registrar 14 IRQ detection enable registrar 15 IRQ control register 0 IRQ control register 1 IRQ control register 2 IRQ control register 3 IRQ control register 4 IRQ control register 5 IRQ control register 6 IRQ control register 7 IRQ control register 8 IRQ control register 9 IRQ control register 10 IRQ control register 11 Abbreviation of Bits DPSBKR15 DPSBKR16 DPSBKR17 DPSBKR18 DPSBKR19 DPSBKR20 DPSBKR21 DPSBKR22 DPSBKR23 DPSBKR24 DPSBKR25 DPSBKR26 DPSBKR27 DPSBKR28 DPSBKR29 DPSBKR30 DPSBKR31 IRQER0 IRQER1 IRQER2 IRQER3 IRQER4 IRQER5 IRQER6 IRQER7 IRQER8 IRQER9 IRQER10 IRQER11 IRQER12 IRQER13 IRQER14 IRQER15 IRQCR0 IRQCR1 IRQCR2 IRQCR3 IRQCR4 IRQCR5 IRQCR6 IRQCR7 IRQCR8 IRQCR9 IRQCR10 IRQCR11 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 *7 7 7 4 to 5 PCLK * 4 to 5 PCLK * 4 to 5 PCLK *7 7 7 7 7 4 to 5 PCLK * 4 to 5 PCLK * 4 to 5 PCLK * 4 to 5 PCLK * 4 to 5 PCLK *7 7 7 4 to 5 PCLK * 4 to 5 PCLK * 4 to 5 PCLK *7 7 7 7 7 4 to 5 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 2 to 3 PCLK * 2 to 3 PCLK *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 53 of 83 RX610 Group 4. I/O Registers Number of Module Register Number Access Size 8 8 8 8 16 8 8 8 8 8 8 8 8 16 16 16 8 8 16 16 16 16 16 16 16 16 16 Access Cycles 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK 7 7 7 7 Address 0008 C32Ch 0008 C32Dh 0008 C32Eh 0008 C32Fh 0008 C340h 0008 C350h 0008 C351h 0008 C352h 0008 C353h 007F C402h 007F C410h 007F C411h 007F C412h 007F C440h 007F C450h 007F C454h 007F FFB0h 007F FFB1h 007F FFB2h 007F FFB4h 007F FFB6h 007F FFBAh 007F FFC8h 007F FFCAh 007F FFCCh 007F FFCEh 007F FFE8h Notes: 1. Abbreviation Register Name ICU ICU ICU ICU ICU ICU ICU ICU ICU FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH IRQ control register 12 IRQ control register 13 IRQ control register 14 IRQ control register 15 Software standby release IRQ enable register Non-maskable interrupt enable register NMI pin interrupt control register Non-maskable interrupt status register Non-maskable interrupt clear register Flash mode register Flash access status register Flash access error interrupt enable register Flash ready interrupt enable register Data flash read enable register Data flash programming/erasure enable register FCU RAM enable register Flash status register 0 Flash status register 1 Flash P/E mode entry register Flash protection register Flash reset register FCU command register FCU processing switching register Data flash blank check control register Flash P/E status register Data flash blank check status register Peripheral clock notification register Abbreviation of Bits IRQCR12 IRQCR13 IRQCR14 IRQCR15 SSIER NMIER NMICR NMISR NMICLR FMODR FASTAT FAEINT FRDYIE DFLRE DFLWE FCURAME FSTATR0 FSTATR1 FENTRYR FPROTR FRESETR FCMDR FCPSR DFLBCCNT FPESTAT DFLBCSTAT PCKAR 8 8 8 8 16 8 8 8 8 8 8 8 8 16 16 16 8 8 16 16 16 16 16 16 16 16 16 *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK *7 7 7 7 2 to 3 PCLK * 2 to 3 PCLK * 2 to 3 PCLK * When the same output trigger is specified for pulse output groups 2 and 3 by the PPG0.PCR setting, the PPG0.NDRH address is 000881ECh. When different output triggers are specified, the PPG0.NDRH addresses for pulse output groups 2 and 3 are 000881EEh and 000881ECh, respectively. 2. When the same output trigger is specified for pulse output groups 0 and 1 by the PPG0.PCR setting, the PPG0.NDRL address is 000881EDh. When different output triggers are specified, the PPG0.NDRL addresses for pulse output groups 0 and 1 are 000881EFh and 000881EDh, respectively. 3. When the same output trigger is specified for pulse output groups 6 and 7 by the PPG1.PCR setting, the PPG1.NDRH address is 000881FCh. When different output triggers are specified, the PPG1.NDRH addresses for pulse output groups 6 and 7 are 000881FEh and 000881FCh, respectively. 4. When the same output trigger is specified for pulse output groups 4 and 5 by the PPG1.PCR setting, the PPG1.NDRL address is 000881FDh. When different output triggers are specified, the PPG1.NDRL addresses for pulse output groups 4 and 5 are 000881FFh and 000881FDh, respectively. 5. 6. 7. 8. 16-bit access to odd addresses is proh bited. When 16-bit access is required, access is at the address corresponding to TMR0 or TMR2. For certain bits, functions differ according to whether the mode is serial communications or smart card interface. The number of access cycles varies depending on the number of divided cycles for clock synchronization (0 to one PCLK). The number of access cycles may be 5 ICLK if the register is accessed during the DMAC operation. R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 54 of 83 RX610 Group 5. Electrical Characteristics 5. 5.1 Electrical Characteristics Absolute Maximum Ratings Table 5.1 Item Absolute Maximum Ratings Symbol VCC, PLLVCC Vin Vin VREFH AVCC* VAN Topr 2 Value -0.3 to +4.6 -0.3 to VCC +0.3 -0.3 to +6.5 -0.3 to VCC +0.3 -0.3 to +4.6 -0.3 to VCC +0.3 Regular specifications: -20 to +85 Wide-range specifications: -40 to +85 Unit V V V V V V C Power supply voltage Input voltage (except for ports 0, 14 to 17) Input voltage (ports 0, 14 to 17* ) Reference power supply voltage Analog power supply voltage Analog input voltage Operating temperature 1 Storage temperature Caution: Notes: 1. 2. Tstg -55 to +125 C Permanent damage to the LSI may result if absolute maximum ratings are exceeded. Ports 0, and 14 to 17 are 5 V tolerant. Connect AVCC to VCC. When neither the A/D converter nor the D/A converter is in use, do not leave the AVSS, VREFH, and VREFL pins open. Connect the AVCC and VREFH pins to VCC, and the AVSS and VREFL pins to VSS, respectively. R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 55 of 83 RX610 Group 5. Electrical Characteristics 5.2 Table 5.2 DC Characteristics DC Characteristics Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V Ta = -20 to +85C (regular specifications), Ta = -40 to +85C (wide-range specifications) Item Symbol IRQ input pin* 1 1 1 Min. VCC x 0.8 -0.3 VCC x 0.06 Typ.    Max. VCC + 0.3 VCC x 0.2  Unit V Test Conditions Schmitt trigger input voltage VIH VIL ΔV T 1 TPU input pin* TMR input pin* SCI input pin* 1 ADTRG# input pin* RES#, NMI RIIC input pin VIH VIL ΔV T VCC x 0.7 -0.3 VCC x 0.05 VCC x 0.8 -0.3 VCC x 0.8 -0.3        5.8 VCC x 0.3  5.8 VCC x 0.2 VCC + 0.3 VCC x 0.2 Ports 0, 14 to 17* 2 VIH VIL Ports 10 to 13, ports 2 to E (144-pin LQFP) ports 2 to H (176-pin LFBGA) Other input pins VIH VIL Input high voltage (except Schmitt trigger input pin) Input low voltage (except Schmitt trigger input pin) Output high voltage Output low voltage MD pin, EMLE EXTAL D0 to D15 MD pin, EMLE EXTAL D0 to D15 VIH VCC x 0.9 VCC x 0.8 VCC x 0.7            VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC x 0.1 VCC x 0.2 VCC x 0.3  0.5 0.4 0.6 0.4 V VIL -0.3 -0.3 -0.3 V All output pins All output pins (except for RIIC pins) RIIC pins VOH VOL VCC-0.5    V V IOH = -1 mA IOL = 1.0 mA IOL = 3.0 mA IOL = 6.0 mA IOL = 15 mA (ICFER.FMPE = 1) RIIC pins (only P14 and P15 in channel 1)   0.4  IOL = 20 mA (ICFER.FMPE = 1) Input leakage current RES#, MD pin, EMLE, NMI Three-state leakage current (off state) Ports 10 to 13, ports 2 to E (144-pin LQFP) ports 2 to H (176-pin LFBGA) Port 0, ports 14 to 17 Iin ITSI     1.0 1.0 μA μA Vin = 0 V, VCC Vin = 0 V, VCC   5.0 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 56 of 83 RX610 Group Item Symbol Ports A to E -Ip Min. 10 Typ.  5. Electrical Characteristics Max. 300 Unit μA Test Conditions VCC = 3.0 to 3.6 V, Vin = 0 V Input pull-up resistor current Input capacitance All input pins (except port 0, ports 14 to 17) Port 0, ports 14 to 17 Cin   15 pF Vin = 0 V, f = 1 MHz,    35 15 30 100   mA Ta= 25 C ICLK = 100 MHz PCLK = 50 MHz BCLK = 25 MHz Supply current*3 In operation Max.*4 Normal*6 Increased by BGO operation*7 ICC* 5    Sleep All-module-clock-stop mode*8 Standby Software standby mode mode Deep software standby mode RAM retained RAM power supply halted      18 14 0.08 15 0.9 52 28 3.0 200 26 μA Analog power supply During A/D conversion (per unit) current During D/A conversion (per unit) Idle (all units) AICC       0.8 0.3 0.3 0.06 0.4 0.3    1.2 1.0 1.0 0.1 0.6 1.0  0.8 20 mA μA Reference power supply current During A/D conversion (per unit) During D/A conversion (per unit) Idle (all units) mA μA V V ms/V RAM standby voltage VCC start voltage* 9 VRAM VCCSTART 2.5   VCC rising gradient* Notes: 1. 2. 3. 9 SVCC This does not include the pins, which are multiplexed as ports 0, and 14 to 17 for 5 V tolerant. This includes the multiplexed pins, but RIIC input pins for ports 14 to 17 are excluded. Supply current values are with all output pins unloaded, all input pins for VIH = VCC and VIL= 0 V, and all input pull-up resistors in the off state. 4. 5. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation. ICC depends on f (ICLK) as follows. (ICLK : PCLK : BCLK = 8 : 4: 2) ICC max. = 0.89 x f + 11 (max.) ICC typ. = 0.30 x f + 5 (normal operation) ICC max. = 0.41 x f + 11 (sleep mode) 6. 7. 8. 9. Measured with clocks not supplied to the peripheral functions. This does not include the BGO operation. Incremented if data is written to or erased from the ROM or data flash for data storage during the program execution. The values are for reference. This can be applied when the RES# pin is held low at power-on. R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 57 of 83 RX610 Group Table 5.3 Permissible Output Currents 5. Electrical Characteristics Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V Ta = -20 to +85C (regular specifications), Ta = -40 to +85C (wide-range specifications) Item Permissible output low current (average value per pin) All output pins except for RIIC pins RIIC pins (ICFER.FMPE = 0) RIIC pins (ICFER.FMPE = 1) Permissible output low current (max. value per pin) All output pins except for RIIC pins RIIC pins (ICFER.FMPE = 0) RIIC pins (ICFER.FMPE = 1) Permissible output low current (total) Permissible output high current (average value per pin) Permissible output high current (max. value per pin) Permissible output high current (total) All output pins Total of all output pins -IOH Σ-IOH     4.0 80 mA mA Total of all output pins All output pins ΣIOL -IOH     80 2.0 mA mA IOL   20.0 mA IOL   6.0 mA IOL   4.0 mA IOL   20.0 mA IOL   6.0 mA Symbol IOL Min.  Typ.  Max. 2.0 Unit mA Caution: To protect the LSI's reliability, do not exceed the output current values in table 29.3. R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 58 of 83 RX610 Group 5. Electrical Characteristics 5.3 Table 5.4 AC Characteristics Operation Frequency Value Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V Ta = -20 to +85C (regular specifications), Ta = -40 to +85C (wide-range specifications) Item Operation frequency System clock (ICLK) Peripheral module clock (PCLK) External bus clock (BCLK) Symbol f Min. 8 8 8 Typ.    Max. 100 50 25 Unit MHz 5.3.1 Table 5.5 Clock Timing Clock Timing Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V ICLK = 8 to 100 MHz, BCLK = 8 to 25 MHz, PCLK = 8 to 50 MHz Ta = -20 to +85C (regular specifications), Ta = -40 to +85C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions Clock cycle time Clock high pulse width Clock low pulse width Clock rising time Clock falling time Oscillation settling time after reset (crystal) Oscillation settling time after leaving software standby mode (crystal) Oscillation settling time after leaving deep software standby mode (crystal) External clock output delay settling time External clock input low pulse width External clock input high pulse width External clock rising time External clock falling time tcyc tCH tCL tCr tCf tOSC1 tOSC2 tOSC3 tDEXT tEXL tEXH tEXr tEXf 40 15 15   10 10 10 1 30.71 30.71   125   5 5       5 5 ns ns ns ns ns ms ms ms ms ns ns ns ns Figure 5.1 Figure 5.4 Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 5.1 External Bus Clock Timing R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 59 of 83 RX610 Group 5. Electrical Characteristics Oscillator ICLK IRQ IRQMD[1:0] 01 10 SSIER.SSIi SSBY IRQ exception handling IRQMD[1:0] = 10b SSBY = 1 WAIT instruction Software standby mode (power-down mode) Oscillation settling time tOSC2 IRQ exception handling Figure 5.2 Oscillation Settling Timing after Software Standby Mode R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 60 of 83 RX610 Group 5. Electrical Characteristics Figure 5.3 Oscillation Settling Timing after Deep Software Standby Mode R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 61 of 83 RX610 Group 5. Electrical Characteristics Figure 5.4 Oscillation Settling Timing Figure 5.5 External Input Clock Timing R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 62 of 83 RX610 Group 5. Electrical Characteristics 5.3.2 Table 5.6 Control Signal Timing Control Signal Timing Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V ICLK = 8 to 100 MHz, BCLK = 8 to 25 MHz Ta = -20 to +85C (regular specifications), Ta = -40 to +85C (wide-range specifications) Test Item RES# pulse width (except for ROM, data flash programming/erasure) Internal reset time (during ROM, data flash programming/erasure) NMI pulse width IRQ pulse width tNMIW tIRQW 200 200 tRESW2* 2 Symbol tRESW* 1 Min. 20 1.5 35 Max. Unit tcyc s s Conditions Figure 5.6      ns ns Figure 5.7 Figure 5.8 Notes: 1. Both the time and the number of cycles should satisfy the specifications. 2. This is to specify the FCU reset and the WDT reset. RES# tRESW Figure 5.6 Reset Input Timing Figure 5.7 NMI Interrupt Input Timing IRQ t RQW Note: * SSIER must be set to cancel software standby mode. Figure 5.8 IRQ Interrupt Input Timing R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 63 of 83 RX610 Group 5. Electrical Characteristics 5.3.3 Table 5.7 Bus Timing Bus Timing Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V, BCLK = 8 to 25 MHz Ta = -20 to +85C (regular specifications), Ta = -40 to +85C (wide-range specifications) Output load conditions: VOH = VCC x 0.5, VOL = VCC x 0.5, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF Item Address delay time Byte control delay time CS# delay time RD# delay time RD# setup time Read data setup time Read data hold time WR# delay time WR# setup time Write data delay time Write data hold time WAIT# setup time WAIT# hold time Symbol tAD tBCD tCSD tRSD tRSS tRDS tRDH tWRD tWRS tWDD tWDH tWTS tWTH Min.     0.5 × (1/BCLK) - 20 15 0  0.5 × (1/BCLK) - 20  0 15 0 Max. 30 30 30 20    20  35    Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 5.13 Test Conditions Figures 29.9 to 29.12 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 64 of 83 RX610 Group 5. Electrical Characteristics Figure 5.9 External Bus Timing/Normal Read Cycle (Bus Clock Synchronized) R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 65 of 83 RX610 Group 5. Electrical Characteristics Figure 5.10 External Bus Timing/Normal Write Cycle (Bus Clock Synchronized) R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 66 of 83 RX610 Group 5. Electrical Characteristics Figure 5.11 External Bus Timing/Page Read Cycle (Bus Clock Synchronized) CSPWWAIT: 2 WRON: 1 WDOFF: 1* WDON: 1* TW2 Tend Tdw1 Tpw1 Tpw2 Tend CSPWWAIT: 2 WRON: 1 WDOFF: 1* WDON: 1* Tdw1 Tpw1 Tpw2 Tend CSWOFF: 1 WDOFF: 1* Tn1 Th CSWWAIT: 2 WRON: 1 WDON: 1* CSON:0 TW1 BCLK Byte write strobe mode tAD A23 to A0 1-write strobe mode A23 to A1 tAD tAD tAD tAD tAD tAD tAD tBCD BC1#, BC0# tBCD Common to both byte write strobe mode and 1-write strobe mode CS7# to CS0# tCSD tCSD tWRD tWRS WR0#, WR1#, WR# (Write) tWDD D15 to D0 (Write) tWRD tWRS tWRD tWRS tWRD tWRS tWRD tWRS tWRD tWRS tWDH tWDD tWDH tWDD tWDH Note: * Be sure to specify WDON and WDOFF as at least one cycle of BCLK. Figure 5.12 External Bus Timing/Page Write Cycle (Bus Clock Synchronized) R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 67 of 83 RX610 Group 5. Electrical Characteristics Figure 5.13 External Bus Timing/External Wait Control R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 68 of 83 RX610 Group 5. Electrical Characteristics 5.3.4 Table 5.8 Timing of On-Chip Peripheral Modules Timing of On-Chip Peripheral Modules (1) Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V, PCLK = 8 to 50 MHz Ta = -20 to +85C (regular specifications), Ta = -40 to +85C (wide-range specifications) Output load conditions: VOH = VCC x 0.5, VOL = VCC x 0.5, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF Test Item I/O ports Output data delay time Input data setup time Input data hold time TPU Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single-edge setting Both-edge setting PPG 8-bit timer Pulse output delay time Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width Single-edge setting Both-edge setting WDT SCI Overflow output delay time Input clock cycle Asynchronous Clock synchronous Input clock pulse width Input clock rise time Input clock fall time Output clock cycle Asynchronous Clock synchronous Output clock pulse width Output clock rise time Output clock fall time Transmit data delay time Receive data setup time (clock synchronous) Receive data hold time (clock synchronous) A/D converter Trigger input setup time tSCKW tSCKr tSCKf tTXD tRXS tRXH tTRGS 0.4 x tScyc    40 40 25 0.6 x tScyc 20 20 40    tScyc ns ns ns ns ns ns Figure 5.24 Figure 5.23 tSCKW tSCKr tSCKf tScyc 0.4 x tScyc   4 x (1/PCLK) 6 x (1/PCLK) 0.6 x tScyc 20 20   tScyc ns ns tcyc tTMCWL tWOVD tScyc 2.5 x (1/PCLK)  4 x (1/PCLK) 6 x (1/PCLK)  40   tcyc ns tcyc Figure 5.21 Figure 5.22 tTCKWL tPOD tTMOD tTMRS tTMCS tTMCWH 2.5 x (1/PCLK)   25 25 1.5 x (1/PCLK)  40 40    tcyc ns ns ns ns tcyc Figure 5.17 Figure 5.18 Figure 5.19 Figure 5.20 Symbol tPWD tPRS tPRH tTOCD tTICS tTCKS tTCKWH Min.  25 25  25 25 1.5 x (1/PCLK) Max. 40   40    Unit ns ns ns ns ns ns tcyc Figure 5.16 Figure 5.15 Conditions Figure 5.14 R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 69 of 83 RX610 Group Table 5.8 Timing of On-Chip Peripheral Modules (2) 5. Electrical Characteristics Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V, PCLK = 8 to 50 MHz Ta = -20 to +85C (regular specifications), Ta = -40 to +85C (wide-range specifications) Test Item RIIC (Standard-mode) ICFER.FMPE = 0 SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rising time SCL, SDA input falling time SCL, SDA input spike pulse removal time SDA input bus free time Start condition input hold time Re-start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load RIIC (Fast-mode) ICFER.FMPE = 0 SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rising time SCL, SDA input falling time tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb tSCL tSCLH tSCLL tSr tSf 5x (1/PCLK) + 1000 3(5) x (1/PCLK) + 300 5x (1/PCLK) + 1000 3(5) x (1/PCLK) + 300 250 0  8(10) x (1/PCLK) + 600 3(5) x (1/PCLK) + 300 5 x (1/PCLK) + 300 20 + 0.1Cb 20 + 0.1Cb 0       400    300 300 4 x (1/PCLK) ns ns ns ns ns ns pF ns ns ns ns ns ns Symbol tSCL tSCLH tSCLL tSr tSf tSP Min. * * 12 Max.    1000 300 4 x (1/PCLK) Unit ns ns ns ns ns ns Conditions Figure 5.25 8(10) x (1/PCLK) + 1300 3(5) x (1/PCLK) + 300 5x (1/PCLK) + 1000   0 SCL, SDA input spike pulse removal tSP time SDA input bus free time Start condition input hold time Re-start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb 5 x (1/PCLK) + 300 3(5) x (1/PCLK) + 300 5 x (1/PCLK) + 300 3(5) x (1/PCLK) + 300 100 0        400 ns ns ns ns ns ns pF R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 70 of 83 RX610 Group Table 5.8 Timing of On-Chip Peripheral Modules (3) 5. Electrical Characteristics Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V, Ta = -20 to +85C (regular specifications), Ta = -40 to +85C (wide-range specifications) Test Item RIIC (Fast-mode+) ICFER.FMPE = 1 SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rising time SCL, SDA input falling time Symbol tSCL tSCLH tSCLL tSr tSf Min. *1*2 8(10) x (1/PCLK) + 240 3(5) x (1/PCLK) + 120 5 x (1/PCLK) + 120   0 Max.    120 120 4 x (1/PCLK) Unit ns ns ns ns ns ns Conditions Figure 5.25 SCL, SDA input spike pulse removal tSP time SDA input bus free time Start condition input hold time Re-start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load Boundary scan (176-pin LFBGA) TCK clock cycle time TCK clock high level pulse width TCK clock low level pulse width TCK clock rising time TCK clock falling time TRST# pulse width TMS setup time TMS hold time TDI setup time TDI hold time TDO data delay time tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb tTCKcyc tTCKH tTCKL tTCKr tTCKf tTRSTW tTMSS tTMSH tTDIS tTDIH tTDOD 5 x (1/PCLK) + 120 3(5) x (1/PCLK) + 5 x (1/PCLK) + 120 3(5) x (1/PCLK) + 120 50 0  100 45 45   20 20 20 20 20  120       550    5 5      40 ns ns ns ns ns ns pF ns ns ns ns ns Tcyc ns ns ns ns ns Figure 5.27 Figure 5.28 Figure 5.26 Notes:1. The value in parentheses is used when ICMR3.NF[1:0] are set to 11b while a digital filter is enabled with ICFER.NFE = 1. 2. Cb indicates the total capacity of the bus line. R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 71 of 83 RX610 Group 5. Electrical Characteristics Figure 5.14 I/O Port Input/Output Timing Figure 5.15 TPU Input/Output Timing Figure 5.16 TPU Clock Input Timing R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 72 of 83 RX610 Group 5. Electrical Characteristics PCLK tPOD PO31 to PO0 Figure 5.17 PPG Output Timing Figure 5.18 8-Bit Timer Output Timing Figure 5.19 8-Bit Timer Reset Input Timing Figure 5.20 8-Bit Timer Clock Input Timing R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 73 of 83 RX610 Group 5. Electrical Characteristics PCLK tWOVD WDTOVF# tWOVD Figure 5.21 WDT Output Timing Figure 5.22 SCK Clock Input Timing Figure 5.23 SCI Input/Output Timing: Clock Synchronous Mode Figure 5.24 A/D Converter External Trigger Input Timing R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 74 of 83 RX610 Group 5. Electrical Characteristics Figure 5.25 I2C Bus Interface Input/Output Timing tTCKcyc tTCKH TCK tTCKf tTCKL tTCKr Figure 5.26 Boundary Scan TCK Timing TCK RES# TRST# tTRSTW Figure 5.27 Boundary Scan TRST# Timing R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 75 of 83 RX610 Group 5. Electrical Characteristics TCK tTMSS tTMSH TMS tTDIS tTDIH TDI tTDOD TDO Figure 5.28 Boundary Scan Input/Output Timing R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 76 of 83 RX610 Group 5. Electrical Characteristics 5.4 Table 5.9 A/D Conversion Characteristics A/D Conversion Characteristics Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V, PCLK = 8 to 50 MHz, ADCLK = 4 to 50 MHz Ta = -20 to +85C (regular specifications), Ta = -40 to +85C (wide-range specifications) Item Resolution Conversion time* 1 Min. 10 With 0.1-F external capacitor Without external capacitor Permiss ble signal source impedance (max.) = 1.0 k Permiss ble signal source impedance (max.) = 5.0 k 2.6 (2.1)* 3 Typ. 10 3 Max. 10  Unit Bit μs Test Conditions When the capacitor is charged enough* 2 0.8 (0.3)*  Sampling 15 states (ADCLK = 50-MHz operation) 1.0 (0.5)* 3   Sampling 25 states   Sampling 105 states Analog input capacitance INL integral nonlinearity error (INL) Offset error Full-scale error Quantization error Absolute accuracy DNL differential nonlinearity error (DNL)         ±1.5 ±1.5 ±1.5 ±0.5 ±1.5 ±0.5 6.0 ±3.0 ±3.0 ±3.0  ±3.0 ±1.0 pF LSB LSB LSB LSB LSB LSB Notes: 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states is indicated. 2. The scanning is not supported. 3. The value in parentheses indicates the sampling time. 5.5 D/A Conversion Characteristics D/A Conversion Characteristics Table 5.10 Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V, PCLK = 8 to 50 MHz Ta = -20 to +85C (regular specifications), Ta = -40 to +85C (wide-range specifications) Item Resolution Conversion time Absolute accuracy Min. 10     RO output resistance  Typ. 10  2.0   3.6 Max. 10 3 4.0 3.0 2.0  Unit Bit μs LSB LSB LSB kΩ 20-pF capacitive load 2-MΩ resistive load 4-MΩ resistive load 10-MΩ resistive load Test Conditions R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 77 of 83 RX610 Group 5. Electrical Characteristics 5.6 ROM (Flash Memory for Code Storage) Characteristics ROM (Flash Memory for Code Storage) Characteristics Table 5.11 Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V Operating temperature range during programming/erasing: Ta = -20 to +85C (regular specifications), Ta = -40 to +85C (wide-range specifications) Item Programming time 256 bytes 8 Kbytes 256 bytes 8 Kbytes Erasure time 8 Kbytes 64 Kbytes 128 Kbytes 8 Kbytes 64 Kbytes 128 Kbytes Rewrite/erase cycle* 1 Symbol tP256 tP8K tP256 tP8K tE8K tE64K tE128K tE8K tE64K tE128K NPEC tSPD tSESD1 Min.           1000*   2 Typ. 2 45 2.4 54 50 400 800 60 480 960    Max. 12 100 14.4 120 120 875 1750 144 1050 2100  120 120 Unit ms ms ms ms ms ms ms ms ms ms Times s s Test Conditions PCLK = 50 MHz NPEC  100 PCLK = 50 MHz NPEC  100 PCLK = 50 MHz NPEC  100 PCLK = 50 MHz NPEC  100 Suspend delay time during writing First suspend delay time during erasing (in suspend priority mode) Second suspend delay time during erasing (in suspend priority mode) Suspend delay time during erasing (in erasure priority mode) Data hold time* 3 Figure 5.29 PCLK = 50 MHz tSESD2   1.7 ms tSEED   1.7 ms TDRP 10   Year Notes: 1. Definition of rewrite/erase cycle: The rewrite/erase cycle is the number of erasing for each block. When the rewrite/erase cycle is n times (n = 1000), erasing can be performed n times for each block. For instance, when 256-byte writing is performed 32 times for different addresses in 8-Kbyte block and then the entire block is erased, the rewrite/erase cycle is counted as one. However, writing to the same address for several times as one erasing is not enabled (over writing is prohibited). 2. This indicates the minimum number that guarantees the characteristics after rewriting. (The guaranteed value is in the range from one to the minimum number.) 3. This indicates the characteristic when rewrite is performed within the specification range including the minimum number. R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 78 of 83 RX610 Group 5. Electrical Characteristics 5.7 Data Flash (Flash Memory for Data Storage) Characteristics Data Flash (Flash Memory for Data Storage) Characteristics Table 5.12 Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V Operating temperature range during programming/erasing: Ta = -20 to +85C (regular specifications), Ta = -40 to +85C (wide-range specifications) Item Programming time 8 bytes 128 bytes Erasure time 8 Kbytes Symbol tDP8 tDP128 tDE8K Min.      30000*   2 Typ. 0.4 1 300      Max. 2 5 900 Unit ms ms ms s ms Times s s Test Conditions PCLK = 50-MHz operation PCLK = 50-MHz operation Blank check time 8 bytes 8 Kbytes tDBC8 tDBC8K NDPEC tDSPD tDSESD1 30 2.5  120 120 PCLK = 50-MHz operation Rewrite/erase cycle* 1 Suspend delay time during writing First suspend delay time during erasing (in suspend priority mode) Second suspend delay time during erasing (in suspend priority mode) Suspend delay time during erasing (in erasure priority mode) Data hold time* 3 Figure 5.29 PCLK = 50-MHz operation tDSESD2   1.7 ms tDSEED   1.7 ms TDDRP 10   Year Notes: 1. Definition of rewrite/erase cycle: The rewrite/erase cycle is the number of erasing for each block. When the rewrite/erase cycle is n times (n = 30000), erasing can be performed n times for each block. For instance, when 128-byte writing is performed 64 times for different addresses in 8-Kbyte block and then the entire block is erased, the rewrite/erase cycle is counted as one. However, writing to the same address for several times as one erasing is not enabled (over writing is prohibited). 2. This indicates the minimum number that guarantees the characteristics after rewriting. (The guaranteed value is in the range from one to the minimum number.) 3. This indicates the characteristic when rewrite is performed within the specification range including the minimum number. R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 79 of 83 RX610 Group 5. Electrical Characteristics Figure 5.29 ROM, Data Flash Write/Erase Suspend Timing R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 80 of 83 RX610 Group Appendix 1. Package Dimensions Appendix 1. JEITA Package Code P-LFBGA176-13x13-0.80 Package Dimensions RENESAS Code PLBG0176GA-A Previous Code BP-176/BP-176V MASS[Typ.] 0.45g wSA D wSB x4 v y1 S S A yS e A ZD e R P N M L K J H G F E D C B A A1 E Reference Symbol Dimension in Millimeters Min Nom 13.0 13.0 0.15 0.20 1.40 0.35 0.40 0.80 0.45 0.50 0.55 0.08 0.10 0.2 0.45 Max B D E v w A ZE A1 e b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 x y y1 SD SE ZD ZE 0.90 0.90 φb φxM S A B 176-pin LFBGA (PLBG0176GA-A) R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 81 of 83 RX610 Group JEITA Package Code P-LQFP144-20x20-0.50 RENESAS Code PLQP0144KA-A Previous Code 144P6Q-A / FP-144L / FP-144LV MASS[Typ.] 1.2g Appendix 1. Package Dimensions HD *1 108 D 73 NOTE) 1 DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH 2 DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET bp b1 109 72 c1 HE E c Reference Dimension in Millimeters Symbol *2 Terminal cross section ZE 144 37 A2 A 1 ZD Index mark 36 F L L1 D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Min Nom 19.9 20.0 19.9 20.0 1.4 21.8 22.0 21.8 22.0 Max 20.1 20.1 c 0.05 0.17 0.09 0° *3 e y bp x Detail F 0.35 22.2 22.2 1.7 0.1 0.15 0.22 0.27 0.20 0.145 0.20 0.125 8° 0.5 0.08 0.10 1.25 1.25 0.5 0.65 1.0 144-pin LQFP (PLQP0144KA-A) R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 A1 Page 82 of 83 RX610 Group REVISION HISTORY REVISION HISTORY RX610 Group Datasheet Description Rev. 0.50 1.00 Data Mar. 24, 2009 Apr. 22, 2011 Page  Summary First edition issued 1. Overview 6 7 10 to 15 Figure 1.2 Block Diagram: Ports F to H added Figure 1.3 Pin Assignment of the 176-pin LFBGA, added Table 1.3 List of Pins and Pin Functions (176-Pin LFBGA), added Table 1.5 Pin Functions: 21, 25 Description on the BSCANP, PF0 to PF6, PG0 to PG7, and PH0 to PH7 pins added 4. I/O Registers 34 to 54 Table 4.1 List of I/O Registers (Address Order), changed 5. Electrical Characteristics 58 59 Table 5.3 Permiss ble Output Currents, changed Table 5.5 Clock Timing: Oscillation settling time after leaving deep software standby mode (crystal), tOSC3, added 60 61 71 75 75 76 Figure 5.2 Oscillation Settling Timing after Software Standby Mode, changed Figure 5.3 Oscillation Settling Timing after Deep Software Standby Mode, added Table 5.8 Timing of On-Chip Peripheral Modules (3), changed Figure 5.26 Boundary Scan TCK Timing, added Figure 5.27 Boundary Scan TRST# Timing, added Figure 5.28 Boundary Scan Input/Output Timing, added R01DS0097EJ0100 Rev.1.00 Apr 22, 2011 Page 83 of 83 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.  The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.  The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.  The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.  When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems.  The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products. Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. 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