Features
DATASHEET
RX630 Group
Renesas MCUs
R01DS0060EJ0160
Rev.1.60
May 19, 2014
100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS,
up to 2-MB flash memory, USB 2.0 full-speed function interface,
CAN, 10- & 12-bit A/D converter, RTC, up to 22 comms interfaces
Features
PLQP0176KB-A
PLQP0144KA-A
PLQP0100KB-A
PLQP0080KB-A
■ 32-bit RX CPU core
Max. operating frequency: 100 MHz
Capable of 165 DMIPS in operation at 100 MHz
Single precision 32-bit IEEE-754 floating point
Two types of multiply-and-accumulation unit (between memories
and between registers)
32-bit multiplier (fastest instruction execution takes one CPU
clock cycle)
Divider (fastest instruction execution takes two CPU clock cycles)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions: Ultra-compact code
Supports the memory protection unit (MPU)
Two types of debugging interfaces: JTAG and FINE (two-line)
PTLG0177JB-A 8 × 8 mm, 0.5-mm pitch
PTLG0145KA-A 7 × 7 mm, 0.5-mm pitch
PTLG0100KA-A 5.5 × 5.5 mm, 0.5-mm pitch
■ Low-power design and architecture
Operation from a single 2.7- to 3.6-V supply
Low power consumption: A product that supports all peripheral
functions draws only 500 μA/MHz.
RTC is capable of operation from a dedicated power supply (min.
operating voltage: 2.3 V).
Four low-power modes
■ On-chip main flash memory, no wait states
100-MHz operation, 10-ns read cycle (no wait states)
384-Kbyte to 2-Mbyte capacities
User code is programmable by on-board or off-board
programming.
■ On-chip data flash memory
Max. 32 Kbytes, reprogrammable up to 100,000 times
Programming/erasing as background operations (BGOs)
■ On-chip SRAM, no wait states
32- to 128-Kbyte capacities
For instructions and operands
Can provide backup on deep software standby
■ DMA
DMAC: Incorporates four channels
DTC
■ Reset and supply management
Power-on reset (POR)
Low voltage detection (LVD) with voltage settings
■ Clock functions
External crystal oscillator or internal PLL for operation at 4 to 16
MHz
Internal 125-kHz LOCO and 50-MHz HOCO
125-kHz clock for the IWDT
Frequency of the oscillator for sub-clock generation: 32 kHz
■ Real-time clock
Adjustment functions (30 seconds, leap year, and error)
Time capture function
(for capturing times in response to event-signal input on external
pins)
■ Independent watchdog timer
125-kHz LOCO clock operation
■ Useful functions for IEC60730 compliance
Oscillation-stop detection, frequency measurement, CRC, IWDT,
self-diagnostic function for the A/D converter, etc.
R01DS0060EJ0160 Rev.1.60
May 19, 2014
24 × 24 mm, 0.5-mm pitch
20 × 20 mm, 0.5-mm pitch
14 × 14 mm, 0.5-mm pitch
12 × 12 mm, 0.5-mm pitch
PLBG0176GA-A 13 × 13 mm, 0.8-mm pitch
■ Up to 22 communications interfaces
USB 2.0 full-speed function interface (1 channel)
CAN (compliant with ISO11898-1), incorporating 32 mailboxes
(up to 3 channels)
SCI with multiple functionalities (up to 13 channels)
Choose from among asynchronous mode, clock-synchronous
mode, smart-card interface mode, simple SPI, simple I2C, and
extended serial mode.
I2C bus interface for transfer at up to 1 Mbps (up to 4 channels)
RSPI for high-speed transfer (up to 3 channels)
■ External address space
8 CS areas (8 × 16 Mbytes)
Multiplexed address data or separate address lines are selectable
per area.
8-, 16-, or 32-bit bus space is selectable per area
■ Up to 20 extended-function timers
16-bit MTU2: input capture, output capture, complementary PWM
output, phase-counting mode (6 channels)
16-bit TPU: input capture, output capture, phase-counting mode
(12 channels)
8-bit TMR (4 channels)
16-bit compare-match timers (4 channels)
■ A/D converter for 1-MHz operation
Up to 21 12-bit channels, and incorporating 1 sample-and-hold
circuit
Up to 8 10-bit channels, and incorporating 1 sample-and-hold
circuit
Addition of results of A/D conversion (in the 12-bit A/D converter)
self-diagnosis (for the 10-bit A/D converter)
■ 10-bit D/A converter: 2 channels
■ Temperature sensor for measuring temperature
within the chip
■ Register write protection function can protect
values in important registers against overwriting.
■ Up to 148 general I/O port pins for GPIO
5-V tolerance, open drain, input pull-up, switchable driving ability
■ Unique ID
16-byte ID code is provided for each chip (only for the G version)
■ Operating temp. range
D version: -40 to +85°C
G version: -40 to +105°C
Page 1 of 154
RX630 Group
1. Overview
1.
Overview
1.1
Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 lists the functions of products.
Table 1.1 shows the outline of maximum specifications, and the number of peripheral module channels differs
depending on the pin number on the package and the ROM capacity. For details, see Table 1.2, Comparison of
Functions for Different Packages.
Table 1.1
Outline of Specifications (1/5)
Classification
Module/Function
Description
CPU
CPU
Maximum operating frequency: 100 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per state (cycle of the system
clock)
Address space: 4-Gbyte linear
Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Nine 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
Floating-point operation instructions: 8
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32 × 32 64 bits
On-chip divider: 32 / 32 32 bits
Barrel shifter: 32 bits
Memory protection unit (MPU)
FPU
Single precision floating point (32 bits)
Data types and floating-point exceptions in conformance with the IEEE754 standard
ROM
RAM
Capacity: 64 Kbytes, 96 Kbytes, 128 Kbytes
100 MHz, no-wait access
E2 data flash
Capacity: 32 Kbytes
Programming/erasing: 100,000 times
Memory
Capacity: 384 Kbytes, 512 Kbytes, 768 Kbytes, 1 Mbyte, 1.5 Mbytes, 2 Mbytes
100 MHz, no-wait access
On-board programming: Four types
Off-board programming (parallel programmer mode)
MCU operating modes
Single-chip mode, on-chip ROM enabled extended mode, and on-chip ROM disabled
extended mode (software switching)
Clock
Main clock oscillator, sub-clock oscillator, low-speed/high-speed on-chip oscillator, PLL
frequency synthesizer, and dedicated on-chip oscillator for the IWDT
Main-clock oscillation stop detection
Separate frequency-division and multiplication settings for the system clock (ICLK),
peripheral module clock (PCLK), FlashIF clock (FCLK) and external bus clock (BCLK)
The CPU and other bus masters run in synchronization with the system clock (ICLK):
Up to 100 MHz
Peripheral modules run in synchronization with the peripheral module clock (PCLK):
Up to 50 MHz
Flash IF run in synchronization with the FlashIF clock (FCLK): Up to 50 MHz
Devices connected to the external bus run in synchronization with the external bus
clock (BCLK): Up to 50 MHz
Clock generation circuit
Reset
RES# pin reset, power-on reset, voltage-monitoring reset, independent watchdog timer
reset, watchdog timer reset, deep software standby reset, and software reset
Voltage detection circuit
When the voltage on VCC passes the voltage detection level (Vdet), an internal reset or
internal interrupt is generated.
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 2 of 154
RX630 Group
Table 1.1
1. Overview
Outline of Specifications (2/5)
Classification
Module/Function
Description
Low power
consumption
Low power
consumption facilities
Module stop function
Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software
standby mode
Battery backup function
Interrupt
Interrupt controller
(ICUb)
Peripheral function interrupts: 180 sources
External interrupts: 16 (pins IRQ0 to IRQ15)
Software interrupts: One source
Non-maskable interrupts: 6 sources
Sixteen levels specifiable for the order of priority
External bus extension
The external address space can be divided into eight areas (CS0 to CS7), each with
independent control of access settings.
Capacity of each area: 16 Mbytes (CS0 to CS7)
A chip-select signal (CS0# to CS7#) can be output for each area.
Each area is specifiable as an 8-, 16- or 32-bit bus space
The data arrangement in each area is selectable as little or big endian (only for data).
Bus format: Separate bus, multiplex bus
Wait control
Write buffer facility
DMA
DMA controller
(DMACA)
4 channels
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software trigger, external interrupts, and interrupt requests from
peripheral functions
Data transfer controller
(DTCa)
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: External interrupts and interrupt requests from peripheral functions
General I/O port pins
177-pin TFLGA (in planning), 176-pin LFBGA (in planning), 176-pin LQFP
I/O pins: 148
Input pin: 1
Pull-up resistors: 148
Open-drain outputs: 148
5-V tolerance: 54
145-pin TFLGA (in planning), 144-pin LQFP
I/O pins: 117
Input pin: 1
Pull-up resistors: 117
Open-drain outputs: 117
5-V tolerance: 53
100-pin TFLGA (in planning), 100-pin LQFP
I/O pins: 78
Input pin: 1
Pull-up resistors: 78
Open-drain outputs: 78
5-V tolerance: 44
80-pin LQFP (in planning)
I/O pins: 58
Input pin: 1
Pull-up resistors: 58
Open-drain outputs: 58
5-V tolerance: 34
I/O ports
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 3 of 154
RX630 Group
Table 1.1
1. Overview
Outline of Specifications (3/5)
Classification
Module/Function
Description
Timers
16-bit timer pulse unit
(TPUa)
(16 bits × 6 channels) × 2 units
Maximum of 16 pulse-input/output possible
Select from among seven or eight counter-input clock signals for each channel
Supports the input capture/output compare function
Output of PWM waveforms in up to 15 phases in PWM mode
Support for buffered operation, phase-counting mode (two phase encoder input) and
cascade-connected operation (32 bits × 2 channels) depending on the channel.
PPG output trigger can be generated
Capable of generating conversion start triggers for the A/D converters
Signals from the input capture pins are input via a digital filter
Clock frequency measuring method
Multi-function timer
pulse unit 2 (MTU2a)
(16 bits × 6 channels) × 1 unit
Time bases for the 6 16-bit timer channels can be provided via up to 16 pulse-input/
output lines and three pulse-input lines
Select from among eight counter-input clock signals for each channel (PCLK/1, PCLK/
4, PCLK/16, PCLK/64, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than channel 5,
for which only four signals are available.
Input capture function
21 output compare/input capture registers
Complementary PWM output mode
Reset synchronous PWM mode
Phase-counting mode
Generation of triggers for A/D converter conversion
Digital filter
Signals from the input capture pins are input via a digital filter
PPG output trigger can be generated
Clock frequency measuring function
Frequency
measurement function
(MCK)
The MTU or unit 0 TPU module can be used to monitor the main clock, sub-clock, HOCO
clock, LOCO clock, and PLL clock for abnormal frequencies.
Port output enable 2
(POE2a)
Controls the high-impedance state of the MTU’s waveform output pins
Programmable pulse
generator (PPG)
(4 bits × 4 groups) × 2 units
Pulse output with the MTU or TPU output as a trigger
Maximum of 32 pulse-output possible
8-bit timers (TMR)
(8 bits × 2 channels) × 2 units
Select from among seven internal clock signals (PCLK/1, PCLK/2, PCLK/8, PCLK/32,
PCLK/64, PCLK/1024, PCLK/8192) and one external clock signal
Capable of output of pulse trains with desired duty cycles or of PWM signals
The 2 channels of each unit can be cascaded to create a 16-bit timer
Generation of triggers for A/D converter conversion
Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12
Compare match timer
(CMT)
(16 bits × 2 channels) × 2 units
Select from among four internal clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/
512)
Realtime clock (RTCa)
Clock sources: Main clock, sub-clock
Clock and calendar functions
Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
Battery backup operation
Time-capture facility for three values
Watchdog timer
(WDTA)
14 bits × 1 channel
Select from among 6 counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/
512, PCLK/2048, PCLK/8192)
Independent watchdog
timer (IWDTA)
14 bits × 1 channel
Counter-input clock: Dedicated on-chip oscillator for the IWDT
Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,
dedicated clock/128, dedicated clock/256
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 4 of 154
RX630 Group
Table 1.1
1. Overview
Outline of Specifications (4/5)
Classification
Module/Function
Description
Communication
function
USB 2.0 function
module (USBa)
Serial communications
interfaces (SCIc, SCId)
13 channels (SCIc: 12 channels + SCId: 1 channel)
SCIc
Serial communications modes: Asynchronous, clock synchronous, and smart-card
interface
Multi-processor function
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12
Simple I2C
Simple SPI
SCId (The following functions are added to SCIc)
Supports the serial communications protocol, which contains the start frame and
information frame
Supports the LIN format
I2C bus interfaces
(RIIC)
4 channels (one of them is FM+)
Communication formats
I2C bus format/SMBus format
Supports the multi-master
Max. transfer rate: 1 Mbps (channel 0)
IEBus (IEB)
1 channel
Supports protocol control for the IEBus
Half-duplex asynchronous transfer
Multi-master operation
Broadcast communications function
Two selectable modes, differentiated by transfer rate
CAN module (CAN)
3 channels
Compliance with the ISO11898-1 specification (standard frame and extended frame)
32 mailboxes per channel
Serial peripheral
interfaces (RSPI)
3 channels
RSPI transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),
and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four
lines) or clock-synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Switching between MSB first and LSB first
The number of bits in each transfer can be changed to any number of bits from 8 to 16,
or to 20, 24, or 32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with
each frame having up to 32 bits)
Buffered structure
Double buffers for both transmission and reception
12-bit A/D converter (S12ADa)
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Includes a UDC (USB Device Controller) and transceiver for USB 2.0
Single port
Compliance with the USB 2.0 specification
Transfer rate: Full speed (12 Mbps)
Self-power mode and bus power are selectable
Incorporates 2 Kbytes of RAM as a transfer buffer
1 unit (1 unit × 21 channels)
12-bit resolution
Conversion time: 1.0 s per channel (in operation with PCLK at 50 MHz)
Operating mode
Scan mode (single scan mode or continuous scan mode)
Sample-and-hold function
Reference voltage generation
Three ways to start A/D conversion
Conversion can be started by a software trigger, a trigger from a timer (MTU, TPU, or
TMR), or an external trigger signal
A/D conversion of the temperature sensor output
Page 5 of 154
RX630 Group
Table 1.1
Classification
1. Overview
Outline of Specifications (5/5)
Module/Function
Description
10-bit A/D converter (ADb)
D/A converter (DAa)
2 channels
10-bit resolution
Output voltage: 0 V to VREFH
Temperature sensor
1 channel
Precision: ± 1 ºC
The voltage of the temperature is converted into a digital value by the 12-bit A/D
converter.
CRC calculator (CRC)
CRC code generation for arbitrary amounts of data in 8-bit units
Select any of three generating polynomials:
X8 + X2 + X + 1, X16 + X15 + X2 + 1, or X16 + X12 + X5 + 1.
Generation of CRC codes for use with LSB-first or MSB-first communications is
selectable
1 unit (1 unit × 8 channels)
10-bit resolution
Conversion time: 1.0 µs per channel (in operation with PCLK at 50 MHz)
Operating mode
Scan mode (single scan mode or continuous scan mode)
External amplifier connection mode
Sample-and-hold function
Three ways to start A/D conversion
Conversion can be started by software, a conversion start trigger from a timer (MTU,
TPU, or TMR), or an external trigger signal.
Unique ID
A 16-byte device-specific ID (only for the G version)
Operating frequency
Up to 100 MHz
Power supply voltage
VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, Vbatt =
2.3 to 3.6 V
Operating temperature
D version: -40 to +85°C,
G version: -40 to +105°C*1
Package
177-pin TFLGA (PTLG0177KA-A) (in planning)
176-pin LFBGA (PLBG0176GA-A) (in planning)
176-pin LQFP (PLQP0176KB-A)
145-pin TFLGA (PTLG0145KA-A) (in planning)
144-pin LQFP (PLQP0144KA-A)
100-pin TFLGA (PTLG0100KA-A) (in planning)
100-pin LQFP (PLQP0100KB-A)
80-pin LQFP (PLQP0080KB-A) (in planning)
On-chip debugging system
E1 emulator (JTAG and FINE interfaces)
E20 emulator (JTAG interface)
Note 1. Please contact us if you are using a G version.
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 6 of 154
RX630 Group
Table 1.2
1. Overview
Comparison of Functions for Different Packages
Functions
RX630 Group
177 Pins,
176 Pins
Package
External bus
External bus width
DMA
DMA controller
Timers
16-bit timer pulse unit
145 Pins,
144 Pins
100 Pins
32 bits
16 bits
Supported
Ch. 0 to 11
Ch. 0 to 5
Multi-function timer pulse unit 2
Ch. 0 to 5
Port output enable 2
Supported
Programmable pulse generator
Ch. 0 and 1
8-bit timers
Ch. 0 to 3
Compare match timer
Ch. 0 to 3
Realtime clock
Supported
Watchdog timer
Supported
Independent watchdog timer
Supported
USB 2.0 function module
Serial communications interfaces (SClc)
Ch. 0
Ch. 0 to 11
Serial communications interfaces (SCld)
I2C
bus interfaces
CAN module
12-bit A/D converter
Ch. 0 to 3
Ch. 0, 2
Ch. 0 to 2
Ch. 0, 1
For 1 M or less: Ch. 0, 1
For 1.5 M or more: Ch. 0 to 2
AN000 to 020
For 512 K or
less: Ch. 1
For 768 K or
more: Ch. 0, 1
Ch. 1
AN000 to 013
AN000 to 010
AN0 to 7
AN0 to 3
Ch. 0, 1
Ch. 1
Temperature sensor
Supported
CRC calculator
Supported
Unique ID
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Ch. 1, 5, 6, 8, 9
Supported
10-bit A/D converter
D/A converter
Ch. 0 to 3, 5, 6,
8, 9
Ch. 12
IEBus
Serial peripheral interfaces
Not supported
Ch. 0 to 3
Data transfer controller
Communication
function
80 Pins
Available (only for the G version)
Page 7 of 154
RX630 Group
1.2
1. Overview
List of Products
Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part number.
Table 1.3
List of Products (1/2)
Group
Part No.
Package
ROM
Capacity
RAM
Capacity
E2 Data
Flash
Operating
Frequency (Max.)
Operating
Temp. Range
RX630
(D version)
R5F56307CDFN
PLQP0080KB-A
384 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56307DDFN
PLQP0080KB-A
384 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56307CDFP
PLQP0100KB-A
384 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56307DDFP
PLQP0100KB-A
384 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56307CDLA
PTLG0100KA-A
384 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56307DDLA
PTLG0100KA-A
384 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56308CDFN
PLQP0080KB-A
512 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56308DDFN
PLQP0080KB-A
512 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56308CDFP
PLQP0100KB-A
512 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56308DDFP
PLQP0100KB-A
512 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56308CDLA
PTLG0100KA-A
512 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56308DDLA
PTLG0100KA-A
512 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630ACDFP*1
PLQP0100KB-A
768 Kbytes
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630ADDFP*1
PLQP0100KB-A
768 Kbytes
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630ACDFB*1
PLQP0144KA-A
768 Kbytes
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630ADDFB*1
PLQP0144KA-A
768 Kbytes
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630ACDLK*1
PTLG0145KA-A
768 Kbytes
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630ADDLK*1
PTLG0145KA-A
768 Kbytes
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630ACDFC
PLQP0176KB-A
768 Kbytes
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630ADDFC
PLQP0176KB-A
768 Kbytes
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630ACDBG
PLBG0176GA-A
768 Kbytes
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630ADDBG
PLBG0176GA-A
768 Kbytes
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630ACDLC
PTLG0177KA-A
768 Kbytes
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630ADDLC
PTLG0177KA-A
768 Kbytes
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630BCDFP*1
PLQP0100KB-A
1 Mbyte
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630BDDFP*1
PLQP0100KB-A
1 Mbyte
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630BCDFB*1
PLQP0144KA-A
1 Mbyte
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630BDDFB*1
PLQP0144KA-A
1 Mbyte
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630BCDLK*1
PTLG0145KA-A
1 Mbyte
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630BDDLK*1
PTLG0145KA-A
1 Mbyte
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630BCDFC
PLQP0176KB-A
1 Mbyte
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630BDDFC
PLQP0176KB-A
1 Mbyte
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630BCDBG
PLBG0176GA-A
1 Mbyte
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630BDDBG
PLBG0176GA-A
1 Mbyte
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630BCDLC
PTLG0177KA-A
1 Mbyte
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630BDDLC
PTLG0177KA-A
1 Mbyte
96 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630DCDFP
PLQP0100KB-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630DDDFP
PLQP0100KB-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630DCDFB
PLQP0144KA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630DDDFB
PLQP0144KA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630DCDLK
PTLG0145KA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 8 of 154
RX630 Group
Table 1.3
1. Overview
List of Products (2/2)
RAM
Capacity
E2 Data
Flash
Operating
Frequency (Max.)
Operating
Temp. Range
Part No.
RX630
(D version)
R5F5630DDDLK
PTLG0145KA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630DCDFC
PLQP0176KB-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
RX630
(G version)
*2
Package
ROM
Capacity
Group
R5F5630DDDFC
PLQP0176KB-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630DCDBG
PLBG0176GA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630DDDBG
PLBG0176GA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630DCDLC
PTLG0177KA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630DDDLC
PTLG0177KA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630ECDFP
PLQP0100KB-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630EDDFP
PLQP0100KB-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630ECDFB
PLQP0144KA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630EDDFB
PLQP0144KA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630ECDLK
PTLG0145KA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630EDDLK
PTLG0145KA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630ECDFC
PLQP0176KB-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630EDDFC
PLQP0176KB-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630ECDBG
PLBG0176GA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630EDDBG
PLBG0176GA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630ECDLC
PTLG0177KA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630EDDLC
PTLG0177KA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5630BDGFB
PLQP0144KA-A
1 Mbyte
96 Kbytes
32 Kbytes
100MHz
-40 to +105°C
R5F5630ADGFB
PLQP0144KA-A
768 Kbytes
96 Kbytes
32 Kbytes
100MHz
-40 to +105°C
R5F5630BDGFP
PLQP0100KB-A
1 Mbyte
96 Kbytes
32 Kbytes
100MHz
-40 to +105°C
R5F5630ADGFP
PLQP0100KB-A
768 Kbytes
96 Kbytes
32 Kbytes
100MHz
-40 to +105°C
R5F56308DGFP
PLQP0100KB-A
512 Kbytes
64 Kbytes
32 Kbytes
100MHz
-40 to +105°C
R5F56307DGFP
PLQP0100KB-A
384 Kbytes
64 Kbytes
32 Kbytes
100MHz
-40 to +105°C
R5F56308DGFN
PLQP0080KB-A
512 Kbytes
64 Kbytes
32 Kbytes
100MHz
-40 to +105°C
R5F56307DGFN
PLQP0080KB-A
384 Kbytes
64 Kbytes
32 Kbytes
100MHz
-40 to +105°C
Note 1. The sub-clock oscillator, real-time clock, and boundary scan have different specifications. For details, see section 11.2.8, SubClock Oscillator Wait Control Register (SOSCWTCR), section 28.2.19, RTC Control Register 3 (RCR3), and section 44.2.4,
Boundary Scan Register (JTBSR) in the User's manual: Hardware.
Note 2. The specifications of the temperature sensor calibration and unique ID for G-version products differ from those for other
products. For details, see section 41.2.2, Temperature Sensor Calibration Data Registers (TSCDRH, TSCDRL), section 41.3,
Using the Temperature Sensor, and section 43.2.22, Unique ID Registers n (UIDRn) (n = 0 to 15) in the User's manual:
Hardware.
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 9 of 154
RX630 Group
R 5
F
1. Overview
5
6
3
0
7
C
D
F
N
Package type, num ber of pins, and pin pitch
F C: LQ FP/176/0.50
BG : LF BG A/176/0.80
LC : T FLG A/177/0.50
F B: LQ FP/144/0.50
LK: T FLG A/145/0.50
F P: LQ FP/100/0.50
LA: T FLG A/100/0.50
F N: LQ FP/80/0.50
D : O perating tem perature range: -40 to +85°C
G: Operating temperature range : -40 to +105°C
C : C AN m odule not included
D : C AN m odule included
R O M , R AM , and E2 data flash capacity
E: 2 M bytes/128 Kbytes/32 Kbytes
D : 1.5 M bytes/128 Kbytes/32 Kbytes
B: 1 M byte/96 Kbytes/32 Kbytes
A: 768 Kbytes/96 Kbytes/32 Kbytes
8: 512 Kbytes/64 Kbytes/32 Kbytes
7: 384 Kbytes/64 Kbytes/32 Kbytes
G roup nam e
30: R X630 G roup
Series nam e
R X600 Series
T ype of m em ory
F : Flash m em ory version
R enesas M C U
R enesas sem iconductor product
Figure 1.1
How to Read the Product Part Number
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 10 of 154
RX630 Group
1.3
1. Overview
Block Diagram
Figure 1.2 shows a block diagram.
E2 DataFlash
WDTA
IWDTa
CRC
SCIc × 12 channels
SCId × 1 channel
USBa × 1 port
RSPI (unit 0)
RSPI (unit 1)
Port 1
RSPI (unit 2)
Port 2
Internal peripheral buses 1 to 6
CAN × 3 channels
MTU2a × 6 channels
TPUa × 6 channels (unit 0)
Operand bus
Internal main bus 1
MPU
Clock
generation
circuit
ICUb:
DTCa:
DMACA:
BSC:
WDTA:
IWDTa:
CRC:
SCIc, SCId:
USBa:
RSPI:
MPU:
Figure 1.2
Port 5
Port 6
PPG (unit 0)
Port 7
PPG (unit 1)
Port 8
TMR × 2 channels (unit 0)
TMR × 2 channels (unit 1)
DTCa
Internal main bus 2
Instruction bus
RX CPU
Port 4
TPUa × 6 channels (unit 1)
Port 9
CMT × 2 channels (unit 0)
Port A
CMT × 2 channels (unit 1)
Port B
RTCa
RAM
Port 3
POE2a
ICUb
ROM
Port 0
RIIC × 4 channels
Port C
Port D
IEB
DMACA ×
4 channels
12-bit ADC × 21 channels
10-bit ADC × 8 channels
Port E
Port F
10-bit DAC × 2 channels
Port G
Temperature sensor
Port H
Port J
Port K
BSC
Interrupt controller
Data transfer controller
DMA controller
Bus controller
Watchdog timer
Independent watchdog timer
CRC (cyclic redundancy check) calculator
Serial communications interface
USB 2.0 function module
Serial peripheral interface
Memory protection unit
External bus
CAN:
MTU2a:
POE2a:
TPUa:
PPG:
TMR:
CMT:
RTCa:
RIIC:
IEB:
Port L
CAN module
Multi-function timer pulse unit 2
Port output enable 2
16-bit timer pulse unit
Programmable pulse generator
8-bit timer
Compare match timer
Realtime clock
I2C bus interface
IEBus controller
Block Diagram
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 11 of 154
RX630 Group
1.4
1. Overview
Pin Functions
Table 1.4 lists the pin functions.
Table 1.4
Pin Functions (1/5)
Classifications
Pin Name
I/O
Description
Power supply
VCC
Input
Power supply pin. Connect it to the system power supply. Connect
this pin to VSS via a 0.1-µF capacitor. The capacitor should be
placed close to the pin
VCL
Input
Connect this pin to VSS via a 0.1-F capacitor. The capacitor
should be placed close to the pin
Clock
VSS
Input
Ground pin. Connect it to the system power supply (0 V)
VBATT
Input
Backup power pin. When the battery backup function is not to be
used, connect it to the VCC pin.
XTAL
Output
EXTAL
Input
Pins for a crystal resonator. An external clock signal can be input
through the EXTAL pin
BCLK
Output
Outputs the external bus clock for external devices
XCOUT
Output
XCIN
Input
Input/output pins for the sub-clock oscillator circuit. Connect a
crystal resonator between XCOUT and XCIN
Operating mode control
MD
Input
Pin for setting the operating mode. The signal levels on these pins
must not be changed during operation
System control
RES#
Input
Reset signal input pin. This LSI enters the reset state when this
signal goes low
EMLE
Input
Input pin for the on-chip emulator enable signal. When the on-chip
emulator is used, this pin should be driven high. When not used, it
should be driven low
BSCANP
Input
Boundary scan enable pin. Boundary scan is enabled when this pin
goes high. When not used, it should be driven low
FINEC
Input
Fine interface clock pin
FINED
I/O
Fine interface pin
TRST#
Input
TMS
Input
On-chip emulator or boundary scan pins. When the EMLE pin is
driven high, these pins are dedicated for the on-chip emulator
TDI
Input
TCK
Input
TDO
Output
TRCLK
Output
This pin outputs the clock for synchronization with the trace data
TRSYNC
Output
This pin indicates that output from the TRDATA0 to TRDATA3 pins
is valid
TRDATA0 to TRDATA3
Output
These pins output the trace information
On-chip emulator
Address bus
A0 to A23
Output
Output pins for the address
Data bus
D0 to D31
I/O
Input and output pins for the bidirectional data bus
Multiplexed bus
A0/D0 to A15/D15
I/O
Address/data multiplexed bus
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 12 of 154
RX630 Group
Table 1.4
1. Overview
Pin Functions (2/5)
Classifications
Pin Name
I/O
Description
Bus control
RD#
Output
Strobe signal which indicates that reading from the external bus
interface space is in progress
WR#
Output
Strobe signal which indicates that writing to the external bus
interface space is in progress, in 1-write strobe mode
WR0# to WR3#
Output
Strobe signals which indicate that either group of data bus pins (D7
to D0, D15 to D8, D23 to D16 and D31 to D24) is valid in writing to
the external bus interface space, in byte strobe mode
BC0# to BC3#
Output
Strobe signals which indicate that either group of data bus pins (D7
to D0, D15 to D8, D23 to D16 and D31 to D24) is valid in access to
the external bus interface space, in 1-write strobe mode
ALE
Output
Address latch signal when address/data multiplexed bus is selected
WAIT#
Input
Input pin for wait request signals in access to the external space
CS0# to CS7#
Output
Select signals for CS areas
Interrupt
Multi-function timer pulse
unit 2
Port output enable 2
NMI
Input
Non-maskable interrupt request pin
IRQ0 to IRQ15
Input
Maskable interrupt request pin
MTIOC0A, MTIOC0B
MTIOC0C, MTIOC0D
I/O
The TGRA0 to TGRD0 input capture input/output compare output/
PWM output pins
MTIOC1A, MTIOC1B
I/O
The TGRA1 and TGRB1 input capture input/output compare output/
PWM output pins
MTIOC2A, MTIOC2B
I/O
The TGRA2 and TGRB2 input capture input/output compare output/
PWM output pins
MTIOC3A, MTIOC3B
MTIOC3C, MTIOC3D
I/O
The TGRA3 to TGRD3 input capture input/output compare output/
PWM output pins
MTIOC4A, MTIOC4B
MTIOC4C, MTIOC4D
I/O
The TGRA4 to TGRD4 input capture input/output compare output/
PWM output pins
MTIC5U, MTIC5V
MTIC5W
Input
The TGRU5, TGRV5, and TGRW5 input capture input/dead time
compensation input pins
MTCLKA, MTCLKB
MTCLKC, MTCLKD
Input
Input pins for external clock
POE0# to POE3#
POE8#
Input
Input pins for request signals to place the MTU large-current pins in
the high impedance state
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 13 of 154
RX630 Group
Table 1.4
1. Overview
Pin Functions (3/5)
Classifications
Pin Name
I/O
Description
16-bit timer pulse unit
TIOCA0, TIOCB0
TIOCC0, TIOCD0
I/O
The TGRA0 to TGRD0 input capture input/output compare output/
PWM output pins
TIOCA1, TIOCB1
I/O
The TGRA1 and TGRB1 input capture input/output compare output/
PWM output pins
TIOCA2, TIOCB2
I/O
The TGRA2 and TGRB2 input capture input/output compare output/
PWM output pins
TIOCA3, TIOCB3
TIOCC3, TIOCD3
I/O
The TGRA3 to TGRD3 input capture input/output compare output/
PWM output pins
TIOCA4, TIOCB4
I/O
The TGRA4 and TGRB4 input capture input/output compare output/
PWM output pins
TIOCA5, TIOCB5
I/O
The TGRA5 and TGRB5 input capture input/output compare output/
PWM output pins
TCLKA, TCLKB
TCLKC, TCLKD
Input
Input pins for external clock signals
TIOCA6, TIOCB6,
TIOCC6, TIOCD6
I/O
The TGRA6 to TGRD6 input capture input/output compare output/
PWM output pins
TIOCA7, TIOCB7
I/O
The TGRA7 and TGRB7 input capture input/output compare output/
PWM output pins
TIOCA8, TIOCB8
I/O
The TGRA8 and TGRB8 input capture input/output compare output/
PWM output pins
TIOCA9, TIOCB9,
TIOCC9, TIOCD9
I/O
The TGRA9 to TGRD9 input capture input/output compare output/
PWM output pins
TIOCA10, TIOCB10
I/O
The TGRA10 and TGRB10 input capture input/output compare
output/PWM output pins
TIOCA11, TIOCB11
I/O
The TGRA11 and TGRB11 input capture input/output compare
output/PWM output pins
TCLKE, TCLKF,
TCLKG, TCLKH
Input
Input pins for external clock signals
Programmable pulse
generator
PO0 to PO31
Output
Output pins for the pulse signals
8-bit timer
TMO0 to TMO3
Output
Compare match output pins
TMCI0 to TMCI3
Input
Input pins for external clocks to be input to the counter
TMRI0 to TMRI3
Input
Input pins for the counter reset
Serial communications
interface (SCIc)
Asynchronous mode/clock synchronous mode
SCK0 to SCK11
I/O
Input/output pins for the clock
RXD0 to RXD11
Input
Input pins for received data
TXD0 to TXD11
Output
Output pins for transmitted data
CTS0# to CTS11#
Input
Input pins for controlling the start of transmission and reception
RTS0# to RTS11#
Output
Output pins for controlling the start of transmission and reception
SSCL0 to SSCL11
I/O
Input/output pins for the I2C clock
SSDA0 to SSDA11
I/O
Input/output pins for the I2C data
Simple I2C mode
Simple SPI mode
SCK0 to SCK11
I/O
Input/output pins for the clock
SMISO0 to SMISO11
I/O
Input/output pins for slave transmission of data
SMOSI0 to SMOSI11
I/O
Input/output pins for master transmission of data
SS0# to SS11#
Input
Chip-select input pins
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 14 of 154
RX630 Group
Table 1.4
1. Overview
Pin Functions (4/5)
Classifications
Pin Name
I/O
Description
Serial communications
interface (SCId)
Asynchronous mode/clock synchronous mode
SCK12
I/O
Input/output pin for the clock
RXD12
Input
Input pin for received data
TXD12
Output
Output pin for transmitted data
CTS12#
Input
Input pin for controlling the start of transmission and reception
RTS12#
Output
Output pin for controlling the start of transmission and reception
SSCL12
I/O
Input/output pin for the I2C clock
SSDA12
I/O
Input/output pin for the I2C data
Simple
I 2C
mode
Simple SPI mode
SCK12
I/O
Input/output pin for the clock
SMISO12
I/O
Input/output pin for slave transmission of data
SMOSI12
I/O
Input/output pin for master transmission of data
SS12#
Input
Chip-select input pin
RXDX12
Input
Input pin for received data
TXDX12
Output
Output pin for transmitted data
SIOX12
I/O
Input/output pin for received or transmitted data
SCL0[FM+],
SCL1 to SCL3
I/O
Input/output pins for clocks. Bus can be directly driven by the Nchannel open drain
SDA0[FM+],
SDA1 to SDA3
I/O
Input/output pins for data. Bus can be directly driven by the Nchannel open drain
VCC_USB
Input
Power supply pin. When the USB is not to be used, connect it to the
VCC pin.
VSS_USB
Input
Ground pin. When the USB is not to be used, connect it to the VSS
pin.
USB0_DP
I/O
Inputs or outputs D+ data for the USB bus
USB0_DM
I/O
Inputs or outputs D- data for the USB bus
USB0_DPUPE
Output
Pull-up pin
USB0_VBUS
Input
Input pin for detection of connection and disconnection of the USB
cable
CRX0 to CRX2
Input
Input pins
CTX0 to CTX2
Output
Output pins
RSPCKA, RSPCKB
RSPCKC
I/O
Clock input/output pins
MOSIA, MOSIB, MOSIC
I/O
Inputs or outputs data output from the master
Extended serial mode
I 2C
bus interface
USB power pins
USB 2.0 function module
CAN module
Serial peripheral interface
IEBus controller
Realtime clock
MISOA, MISOB, MISOC
I/O
Inputs or outputs data output from the slave
SSLA0, SSLB0, SSLC0
I/O
Input or output pins for slave selection
SSLA1 to SSLA3
SSLB1 to SSLB3
SSLC1 to SSLC3
Output
Output pins for slave selection
IERXD
Input
Input pin for data reception
IETXD
Output
Output pin for data transmission
RTCOUT
Output
Output pin for 1-Hz clock
RTCIC0 to RTCIC2
Input
Time capture event input pin
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 15 of 154
RX630 Group
Table 1.4
1. Overview
Pin Functions (5/5)
Classifications
Pin Name
I/O
Description
12-bit A/D converter
AN000 to AN020
Input
Input pins for the analog signals to be processed by the A/D
converter
ADTRG0#
Input
Input pins for the external trigger signals that start the A/D
conversion
AN0 to AN7
Input
Input pins for the analog signals to be processed by the A/D
converter
ANEX0
Output
Extended analog output pin
ANEX1
Input
Extended analog input pin
ADTRG#
Input
Input pins for the external trigger signals that start the A/D
conversion
D/A converter
DA0, DA1
Output
Output pins for the analog signals to be processed by the D/A
converter
Analog power supply
AVCC0
Input
Analog voltage supply pin for the 12-bit A/D converter. Connect this
pin to VCC if the 12-bit A/D converter is not to be used
AVSS0
Input
Analog ground pin for the 12-bit A/D converter. Connect this pin to
VSS if the 12-bit A/D converter is not to be used
VREFH0
Input
Analog reference voltage supply pin for the 12-bit A/D converter.
Connect this pin to VCC if the 12-bit A/D converter is not to be used
VREFL0
Input
Analog reference ground pin for the 12-bit A/D converter. Connect
this pin to VSS if the 12-bit A/D converter is not to be used
VREFH
Input
Reference voltage input pin for the 10-bit A/D converter and D/A
converter. This is used as the analog power supply for the
respective modules. Connect this pin to VCC if neither the 10-bit
A/D converter nor the D/A converter is in use
VREFL
Input
Reference ground pin for the 10-bit A/D converter and D/A
converter. This is used as the analog ground for the respective
modules. Set this pin to the same potential as the VSS pin
P00 to P03, P05, P07
I/O
6-bit input/output pins
P10 to P17
I/O
8-bit input/output pins
10-bit A/D converter
I/O ports
P20 to P27
I/O
8-bit input/output pins
P30 to P37
I/O
8-bit input/output pins (P35: input pin)
P40 to P47
I/O
8-bit input/output pins
P50 to P57
I/O
8-bit input/output pins
P60 to P67
I/O
8-bit input/output pins
P70 to P77
I/O
8-bit input/output pins
P80 to P87
I/O
8-bit input/output pins
P90 to P97
I/O
8-bit input/output pins
PA0 to PA7
I/O
8-bit input/output pins
PB0 to PB7
I/O
8-bit input/output pins
PC0 to PC7
I/O
8-bit input/output pins
PD0 to PD7
I/O
8-bit input/output pins
PE0 to PE7
I/O
8-bit input/output pins
PF0 to PF5
I/O
6-bit input/output pins
PG0 to PG7
I/O
8-bit input/output pins
PH4, PH5
I/O
2-bit input/output pins
PJ3, PJ5
I/O
2-bit input/output pins
PK0 to PK7
I/O
8-bit input/output pins
PL0 to PL4
I/O
5-bit input/output pins
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 16 of 154
RX630 Group
1.5
1. Overview
Pin Assignments
Figure 1.3 to Figure 1.10 show the pin assignments. Table 1.5 to Table 1.11 show the lists of pins and pin functions.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
15
PE2
PE3
P70
P65
P67
VSS
VCC
PG7
PA6
PB0
P72
PB4
PL0
PL1
PC1
15
14
PE1
PE0
PK4
PE7
PG3
PA0
PA1
PA2
PA7
PK7
PB1
PB5
P73
P75
P74
14
13
P63
P64
PE4
PK5
PG2
PG4
PG6
PA3
PK6
P71
PB3
PB7
PC0
PC2
P76
13
12
P60
PK3
P62
PE5
PE6
P66
PG5
PA4
PA5
PB2
PB6
P77
PC3
PC4
P80
12
11
PD6
PG1
PK2
P61
P81
P82
PC6
VCC
11
10
P97
PD4
PG0
PD7
PC5
PC7
P83
VSS
10
9
PK0
P96
PD3
PD5
P50
P51
P52
P84
9
8
P94
PD1
PD2
PK1
P53
PL2
PL3
PL4
8
7
VSS
P92
PD0
P95
P54
P55
VSS_
USB
USB0_
DP
7
6
VCC
P91
P90
P93
P56
P57
VCC_
USB
USB0_
DM
6
5
P46
P47
P45
P44
NC
P13
P12
P10
P11
5
4
P42
P41
P43
P00
VSS
BSCANP
PF4
P35
PF3
PF1
P25
P86
P15
P14
P85
4
3 VREFL0
P40
VREFH0
P03
PF5
PJ3
MD
RES#
P34
PF2
PF0
P24
P22
P87
P16
3
2 AVCC0
P07
VREFH
P02
EMLE
VCL
XCOUT
VSS
VCC
P32
P30
P26
P23
P17
P20
2
1 AVSS0
P05
VREFL
P01
PJ5
VBATT
XCIN
XTAL
EXTAL
P33
P31
P27
PH5
PH4
P21
1
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
Note:
Figure 1.3
RX630 Group
PTLG0177KA-A
(177-Pin TFLGA)
(Upper perspective view)
This figure indicates the power supply pins and I/O port pins. For the pin configuration, see Table 1.5, List of
Pins and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA).
Pin Assignment (177-Pin TFLGA)
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 17 of 154
RX630 Group
1. Overview
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
15
PE2
PE3
P70
P65
P67
VSS
VCC
PG7
PA6
PB0
P72
PB4
PL0
PL1
PC1
15
14
PE1
PE0
PK4
PE7
PG3
PA0
PA1
PA2
PA7
PK7
PB1
PB5
P73
P75
P74
14
13
P63
P64
PE4
PK5
PG2
PG4
PG6
PA3
PK6
P71
PB3
PB7
PC0
PC2
P76
13
12
P60
PK3
P62
PE5
PE6
P66
PG5
PA4
PA5
PB2
PB6
P77
PC3
PC4
P80
12
11
PD6
PG1
PK2
P61
P81
P82
PC6
VCC
11
10
P97
PD4
PG0
PD7
PC5
PC7
P83
VSS
10
9
PK0
P96
PD3
PD5
P50
P51
P52
P84
9
8
P94
PD1
PD2
PK1
P53
PL2
PL3
PL4
8
7
VSS
P92
PD0
P95
P54
P55
VSS_
USB
USB0_
DP
7
6
VCC
P91
P90
P93
P56
P57
VCC_
USB
USB0_
DM
6
5
P46
P47
P45
P44
P13
P12
P10
P11
5
4
P42
P41
P43
P00
VSS
BSCANP
PF4
P35
PF3
PF1
P25
P86
P15
P14
P85
4
3 VREFL0
P40
VREFH0
P03
PF5
PJ3
MD
RES#
P34
PF2
PF0
P24
P22
P87
P16
3
2 AVCC0
P07
VREFH
P02
EMLE
VCL
XCOUT
VSS
VCC
P32
P30
P26
P23
P17
P20
2
1 AVSS0
P05
VREFL
P01
PJ5
VBATT
XCIN
XTAL
EXTAL
P33
P31
P27
PH5
PH4
P21
1
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
Note:
Figure 1.4
RX630 Group
PLBG0176GA-A
(176-Pin LFBGA)
(Upper perspective view)
This figure indicates the power supply pins and I/O port pins. For the pin configuration, see Table 1.5, List of
Pins and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA).
Pin Assignment (176-Pin LFBGA)
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 18 of 154
1. Overview
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
133
88
134
87
135
86
136
85
137
84
138
83
139
82
140
81
141
80
142
79
143
78
144
77
145
76
146
75
147
74
148
73
149
72
150
71
RX630 Group
PLQP0176KB-A
(176-Pin LQFP)
(Top View)
151
152
153
154
155
156
157
158
159
70
69
68
67
66
65
64
63
62
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
P74
P75
PC2
P76
P77
PC3
PC4
P80
P81
P82
PC5
PC6
PC7
VCC
P83
VSS
P50
P51
P52
P84
P53
P54
P55
PL2
PL3
PL4
P56
P57
VSS_USB
USB0_DP
USB0_DM
VCC_USB
P10
P11
P12
P13
P85
P14
P15
P86
P16
P87
P17
P20
AVSS0
P05
VREFH
P03
VREFL
P02
P01
P00
PF5
EMLE
PJ5
VSS
PJ3
VCL
VBATT
NC
PF4
MD/FINED
XCIN
XCOUT
RES#
P37/XTAL
VSS
P36/EXTAL
VCC
P35
P34
P33
P32
PF3
PF2
P31
P30
PF1
PF0
P27
P26
P25
PH5
P24
PH4
P23
P22
P21
19
45
18
46
176
17
47
175
16
48
174
15
49
173
14
50
172
13
51
171
12
52
170
11
53
169
10
54
168
9
55
167
8
56
166
7
57
165
6
58
164
5
59
163
4
60
162
3
61
161
2
160
1
PE2
PE1
PE0
P64
P63
P62
P61
PK3
P60
PK2
PD7
PG1
PD6
PG0
PD5
PD4
P97
PD3
PK1
P96
PK0
PD2
P95
PD1
P94
PD0
P93
P92
P91
VSS
P90
VCC
P47
P46
P45
P44
P43
P42
P41
VREFL0
P40
VREFH0
AVCC0
P07
132
PE3
PE4
PE5
PK4
P70
PK5
PE6
PE7
P65
PG2
P66
PG3
P67
PG4
PA0
VSS
PG5
VCC
PA1
PG6
PA2
PG7
PA3
PA4
PA5
PA6
PA7
PK6
PB0
PK7
P71
P72
PB1
PB2
PB3
PB4
PB5
PB6
PB7
P73
PL0
PC0
PL1
PC1
RX630 Group
Note:
Figure 1.5
This figure indicates the power supply pins and I/O port pins. For the pin configuration, see Table 1.6, List of Pins and
Pin Functions (176-Pin LQFP).
Pin Assignment (176-Pin LQFP)
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 19 of 154
RX630 Group
1. Overview
A
B
C
D
E
F
G
H
J
K
L
M
N
13
PE3
PE4
PK4
PE6
P67
PA2
PA4
PA7
PB1
PB5
PL0
PL1
P74
13
12
PE1
PE2
P70
PE5
P65
PA1
VCC
PB0
PB2
PB6
P73
PC1
P75
12
11
P62
P61
PE0
PK5
P66
VSS
PA6
P71
PB4
PB7
PC2
PC0
PC3
11
10
PK3
PK2
P63
PE7
PA0
PA3
PA5
P72
PB3
P76
PC4
P77
P82
10
9
PD6
PD4
PD7
P64
P80
PC5
P81
PC7
9
8
PD2
PD0
PD3
P60
VCC
P83
PC6
VSS
8
7
P92
P91
PD1
PD5
P51
P52
P50
P55
7
6
P90
P47
VSS
P93
P53
P56
VSS_
USB
USB0_
DP
6
5
P45
P43
P46
VCC
P44
P54
P13
VCC_
USB
USB0_
DM
5
4
P42
VREFL0
P41
P01
EMLE
3
P40
P05
VREFH0
P03
PJ5
PJ3
2
P07
AVCC0
P02
PF5
VCL
1
AVSS0
VREFH
VREFL
P00
A
B
C
D
Note:
Figure 1.6
RX630 Group
PTLG0145KA-A
(145-Pin TFLGA)
(Upper perspective view)
VBATT BSCANP
P35
P30
P15
P24
P12
P14
4
MD
VSS
P32
P31
P16
P86
P87
3
XCOUT
RES#
VCC
P33
P26
P23
P17
P20
2
VSS
XCIN
XTAL
EXTAL
P34
P27
P25
P22
P21
1
E
F
G
H
J
K
L
M
N
This figure indicates the power supply pins and I/O port pins. For the pin configuration, see Table 1.7,
List of Pins and Pin Functions (145-Pin TFLGA).
Pin Assignment (145-Pin TFLGA)
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 20 of 154
PA3
VSS
PA4
VCC
PA5
PA6
PA7
PB0
P71
P72
PB1
PB2
PB3
PB4
PB5
PB6
PB7
P73
PL0
PC0
PL1
PC1
94
92
91
90
89
88
87
85
84
83
81
79
77
76
75
74
73
PA1
PA2
96
78
PA0
97
80
P66
P67
99
82
P65
100
86
PE7
101
93
PE6
102
95
P70
PK5
104
98
PE5
PK4
103
PE4
106
105
PE3
107
1. Overview
108
RX630 Group
PE2
109
72
P74
PE1
110
71
P75
PE0
111
70
PC2
P64
112
69
P76
P63
113
68
P62
114
67
P77
PC3
P61
PK3
115
66
PC4
116
65
P80
P60
117
64
P81
PK2
118
63
P82
PD7
119
62
PC5
PD6
120
61
PC6
PD5
121
60
PC7
PD4
122
59
PD3
123
58
VCC
P83
PD2
124
PD1
PD0
125
P93
127
P92
128
P91
129
VSS
130
P90
VCC
RX630 Group
PLQP0144KA-A
(144-Pin LQFP)
(Top View)
57
VSS
P50
55
P51
54
P52
53
P53
52
P54
51
P55
131
50
P56
132
49
VSS_USB
P47
133
48
P46
134
47
USB0_DP
USB0_DM
P45
135
46
VCC_USB
P44
136
45
P12
P43
137
44
P13
P42
138
43
P14
P41
VREFL0
139
42
P15
140
41
P86
P40
VREFH0
AVCC0
141
40
142
39
143
38
P16
P87
P17
P07
144
37
P20
Note:
Figure 1.7
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PJ5
VSS
PJ3
VCL
VBATT
MD/FINED
XCIN
XCOUT
RES#
P37/XTAL
VSS
P36/EXTAL
VCC
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
P23
P22
P21
10
9
PF5
EMLE
5
VREFL
P02
8
4
P03
7
3
VREFH
P01
P00
2
P05
6
1
AVSS0
126
14
56
This figure indicates the power supply pins and I/O port pins. For the pin configuration, see Table 1.8, List of Pins and
Pin Functions (144-Pin LQFP).
Pin Assignment (144-Pin LQFP)
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 21 of 154
RX630 Group
1. Overview
RX630 Group
PTLG0100KA-A (100-Pin TFLGA)
(Top View)
A
B
C
D
E
F
G
H
J
K
10
PE2
PE3
PE4
PA0
PA3
VSS
VCC
PB7
PC1
PC2
10
9
PE1
PD7
PE5
PA1
PA5
PA7
PB1
PB6
PC0
PC3
9
8
PE0
PD6
PD5
PE7
PA4
PB0
PB4
PC6
PC4
PC5
8
7
PD4
PD3
PD2
PE6
PA6
PB2
PB5
PC7
P50
P51
7
6
PD0
PD1
P47
P46
PA2
PB3
P52
P54
VCC_
USB
USB0_
DP
6
5
P43
P44
P42
P45
P41
P12
P53
P55
VSS_
USB
USB0_
DM
5
P34
P32
P27
P15
P13
P14
4
4 VREFL0
3
P07
VREFH0 VBATT
AVCC0
PJ3
MD
RES#
P35
P30
P16
P17
P20
3
2 VREFH
AVSS0
VREFL
XCOUT
VSS
VCC
P31
P25
P21
P22
2
1
P05
EMLE
VCL
XCIN
XTAL
EXTAL
P33
P26
P24
P23
1
A
B
C
D
E
F
G
H
J
K
Note:
Figure 1.8
P40
This figure indicates the power supply pins and I/O port pins. For the pin
configuration, see Table 1.7, List of Pins and Pin Functions (145-Pin TFLGA).
Pin Assignment (100-Pin TFLGA)
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 22 of 154
PE3
PE4
PE5
PE6
PE7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
VSS
PB0
VCC
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PE2
76
50
PE1
77
49
PC2
PC3
PE0
78
48
PC4
PD7
79
47
PC5
PD6
80
46
PC6
PD5
81
45
PC7
PD4
82
44
P50
PD3
83
43
P51
PD2
84
42
P52
PD1
85
41
P53
PD0
86
40
P54
P47
87
39
P55
P46
88
38
VSS_USB
P45
89
37
USB0_DP
P44
90
36
USB0_DM
P43
91
35
VCC_USB
P42
92
34
P12
P41
93
33
P13
VREFL0
94
32
P14
P40
95
31
P15
VREFH0
96
30
P16
AVCC0
97
29
P17
P07
98
28
P20
AVSS0
99
27
P21
P05
100
26
P22
Note:
Figure 1.9
74
1. Overview
75
RX630 Group
14
15
16
17
18
19
20
21
22
23
24
25
VCC
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
P23
9
XCOUT
13
8
XCIN
P36/EXTAL
7
MD/FINED
12
6
VBATT
VSS
5
VCL
11
4
PJ3
P37/XTAL
3
VREFL
10
2
EMLE
RES#
1
VREFH
RX630 Group
PLQP0100KB-A
(100-Pin LQFP)
(Top View)
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.10, List of Pins and Pin Functions (100-Pin LQFP).
Pin Assignment (100-Pin LQFP)
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 23 of 154
PE3
PE4
PE5
PA0
PA1
PA2
PA3
PA4
PA5
PA6
VSS
PB0
VCC
PB1
PB2
PB3
PB4
PB5
PB6
PB7
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PE2
61
40
PC2
PE1
62
39
PC3
PE0
63
38
PC4
PD2
64
37
PC5
PD1
65
36
PC6
PD0
66
35
PC7
P47
67
34
P54
P46
68
33
P55
P45
69
32
VSS_USB
P44
70
31
USB0_DP
P43
71
30
USB0_DM
P42
72
29
VCC_USB
P41
73
28
P12
VREFL0
74
27
P13
P40
75
26
P14
VREFH0
76
25
P15
AVCC0
77
24
P16
P07
78
23
P17
AVSS0
79
22
P20
P05
80
21
P21
Note:
Figure 1.10
59
1. Overview
60
RX630 Group
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VREFH
EMLE
VREFL
VCL
VBATT
MD/FINED
XCIN
XCOUT
RES#
P37/XTAL
VSS
P36/EXTAL
VCC
P35
P34
P32
P31
P30
P27
P26
RX630 Group
PLQP0080KB-A
(80-Pin LQFP)
(Top View)
This figure indicates the power supply pins and I/O port pins. For the pin configuration, see
Table 1.11, List of Pins and Pin Functions (80-Pin LQFP).
Pin Assignment (80-Pin LQFP)
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 24 of 154
RX630 Group
Table 1.5
1. Overview
List of Pins and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (1/5)
Pin Number
177-Pin
TFLGA
176-Pin
LFBGA
Power Supply
Clock System
Control
A1
AVSS0
A2
AVCC0
A3
VREFL0
A4
A5
A6
VCC
A7
VSS
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
Interrupt
S12AD,
AD, DA
P42
IRQ10-DS
AN002
P46
IRQ14-DS
AN006
IRQ6
AN6
I/O Port
Bus
A8
P94
A9
PK0
A20/D20
A10
P97
A11
PD6
D6[A6/D6]
A12
P60
CS0#
A13
P63
CS3#
A14
PE1
D9[A9/D9]
MTIOC4C/TIOCD9/PO18
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/SSLB2/RSPCKB
A15
PE2
D10[A10/D10]
MTIOC4A/TIOCA9/PO23
RXD12/SMISO12/
SSCL12/RXDX12/SSLB3/
MOSIB
B1
B2
A23/D23
MTIC5V/POE1#
SSLC2
SCK9
ANEX1
IRQ7-DS
AN0
P05
IRQ13
DA1
P07
IRQ15
ADTRG0#
B3
P40
IRQ8-DS
AN000
B4
P41
IRQ9-DS
AN001
B5
P47
B6
P91
A17/D17
SCK7
IRQ15-DS
AN015
AN007
B7
P92
A18/D18
RXD7/SMISO7/SSCL7
AN016
B8
PD1
D1[A1/D1]
B9
P96
A22/D22
MTIOC4B/TIOCB7/
TCLKG
MOSIC/CTX0
IRQ1
AN009
POE3#
SSLC0
IRQ4
AN012
B10
PD4
D4[A4/D4]
B11
PG1
D25
B12
PK3
B13
P64
CS4#
B14
PE0
D8[A8/D8]
TIOCC9
SCK12/SSLB1
ANEX0
B15
PE3
D11[A11/D11]
MTIOC4B/TIOCB9/PO26/
POE8#
CTS12#/RTS12#/SS12#/
MISOB
AN1
C1
VREFL
C2
VREFH
C3
VREFH0
RXD9/SMISO9/SSCL9
C4
P43
C5
P45
C6
P90
A16/D16
C7
PD0
D0[A0/D0]
TIOCA7
C8
PD2
D2[A2/D2]
MTIOC4D/TIOCA8
MISOC/CRX0
IRQ2
AN010
C9
PD3
D3[A3/D3]
TIOCB8/TCLKH/POE8#
RSPCKC
IRQ3
AN011
C10
PG0
D24
C11
PK2
C12
P62
R01DS0060EJ0160 Rev.1.60
May 19, 2014
IRQ11-DS
IRQ13-DS
TXD7/SMOSI7/SSDA7
AN003
AN005
AN014
IRQ0
AN008
TXD9/SMOSI9/SSDA9
CS2#
Page 25 of 154
RX630 Group
Table 1.5
1. Overview
List of Pins and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (2/5)
Pin Number
177-Pin
TFLGA
176-Pin
LFBGA
Power Supply
Clock System
Control
I/O Port
Bus
C13
PE4
D12[A12/D12]
C14
PK4
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
MTIOC4D/MTIOC1A/
TIOCA10/PO28
SSLB0
C15
P70
P01
TMCI0
RXD6/SMISO6/SSCL6
D2
P02
TMCI1
SCK6
D3
P03
D4
P00
D5
P44
D6
P93
A19/D19
D7
P95
A21/D21
D8
PK1
D9
PD5
SCK4
TMRI0
AN020
DA0
IRQ8
AN018
AN004
AN017
MTIC5W/POE2#
SSLC1
IRQ5
AN013
MTIC5U/POE0#
SSLC3
IRQ7
AN7
IRQ5
AN3
IRQ7
AN5
D7[A7/D7]
P61
CS1#
D12
PE5
D13[A13/D13]
MTIOC4C/MTIOC2B/
TIOCB10
D13
PK5
D14
PE7
D15[A15/D15]
TIOCB11
D15
P65
CS5#
E1
PJ5
CTS9#/RTS9#/SS9#
RSPCKB
TXD4/SMOSI4/SSDA4
MISOB
EMLE
E3
PF5
E4
VSS
E5*1
NC
E12
IRQ4
PE6
D14[A14/D14]
E13
TRDATA0
PG2
D26
E14
TRDATA1
PG3
D27
P67
CS7#
E15
F1
VBATT
F2
VCL
F3
PJ3
TIOCA11
MTIOC3C
CTS4#/RTS4#/SS4#/
MOSIB
IRQ6
CRX2*2
IRQ15
AN4
CTS6#/RTS6#/CTS0#/
RTS0#/SS6#/SS0#
BSCANP
F12
P66
TRSYNC#
F14
CTX2*2
CS6#
PG4
D28
PA0
A0/BC0#
MTIOC4A/TIOCA0/PO16
SSLA1
MTIOC0B/MTCLKC/
TIOCB0/PO17
SCK5/SSLA2
VSS
G1
XCIN
G2
XCOUT
G3
MD
FINED
G4
TRST#
G12
TRCLK
PG5
D29
G13
TRDATA2
PG6
D30
PA1
A1
G14
G15
IRQ10
IRQ11
D5[A5/D5]
PD7
F15
AN019
IRQ12-DS
D10
F13
TXD6/SMOSI6/SSDA6
IRQ9
CTS7#/RTS7#/SS7#
D11
F4
AN2
RXD4/SMISO4/SSCL4
D1
E2
S12AD,
AD, DA
Interrupt
PF4
IRQ11
VCC
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 26 of 154
RX630 Group
Table 1.5
1. Overview
List of Pins and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (3/5)
Pin Number
177-Pin
TFLGA
176-Pin
LFBGA
Power Supply
Clock System
Control
I/O Port
P37
H1
XTAL
H2
VSS
H3
RES#
Bus
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
Interrupt
H4
P35
H12
PA4
A4
MTIC5U/MTCLKA/
TIOCA1/TMRI0/PO20
TXD5/SMOSI5/SSDA5/
SSLA0
IRQ5-DS
H13
PA3
A3
MTIOC0D/MTCLKD/
TIOCD0/TCLKB/PO19
RXD5/SMISO5/SSCL5
IRQ6-DS
H14
PA2
A2
PO18
RXD5/SMISO5/SSCL5/
SSLA3
D31
MTIOC0A/TMCI3/PO12/
POE2#
SCK6/SCK0
TIOCB1/PO21
RSPCKA
H15
TRDATA3
PG7
J1
EXTAL
P36
J2
VCC
J3
J4
NMI
P34
TMS
IRQ4
PF3
J12
PA5
J13
PK6
J14
PA7
A7
TIOCB2/PO23
MISOA
J15
PA6
A6
MTIC5V/MTCLKB/
TIOCA2/TMCI3/PO22/
POE2#
CTS5#/RTS5#/SS5#/
MOSIA
K1
P33
MTIOC0D/TIOCD0/
TMRI3/PO11/POE3#
RXD6/RXD0/SMISO6/
SMISO0/SSCL6/SSCL0/
CRX0
IRQ3-DS
K2
P32
MTIOC0C/TIOCC0/
TMO3/PO10/RTCOUT/
RTCIC2
TXD6/TXD0/SMOSI6/
SMOSI0/SSDA6/SSDA0/
CTX0
IRQ2-DS
K3
TDI
K4
TCK/FINEC
A5
PF2
RXD1/SMISO1/SSCL1
PF1
SCK1
K12
PB2
A10
K13
P71
CS1#
TIOCC3/TCLKC/PO26
CTS4#/RTS4#/CTS6#/
RTS6#/SS4#/SS6#
MTIC5W/TIOCA3/PO24
RXD4/RXD6/SMISO4/
SMISO6/SSCL4/SSCL6/
RSPCKA
IRQ12
K14
PK7
K15
PB0
L1
P31
MTIOC4D/TMCI2/PO9/
RTCIC1
CTS1#/RTS1#/SS1#/
SSLB0
IRQ1-DS
L2
P30
MTIOC4B/TMRI3/PO8/
RTCIC0/POE8#
RXD1/SMISO1/SSCL1/
MISOB
IRQ0-DS
L3
TDO
S12AD,
AD, DA
A8
PF0
TXD1/SMOSI1/SSDA1
L4
P25
CS5#
MTIOC4C/MTCLKB/
TIOCA4/PO5
RXD3/SMISO3/SSCL3
L12
PB6
A14
MTIOC3D/TIOCA5/PO30
RXD9/SMISO9/SSCL9
L13
PB3
A11
MTIOC0A/MTIOC4A/
TIOCD3/TCLKD/TMO0/
PO27POE3#
SCK4/SCK6
L14
PB1
A9
MTIOC0C/MTIOC4C/
TIOCB3/TMCI0/PO25
TXD4/TXD6/SMOSI4/
SMOSI6/SSDA4/SSDA6
L15
P72
CS2#
M1
P27
CS7#
MTIOC2B/TMCI3/PO7
SCK1/RSPCKB
M2
P26
CS6#
MTIOC2A/TMO1/PO6
TXD1/CTS3#/RTS3#/
SMOSI1/SS3#/SSDA1/
MOSIB
R01DS0060EJ0160 Rev.1.60
May 19, 2014
ADTRG0#
IRQ4-DS
Page 27 of 154
RX630 Group
Table 1.5
1. Overview
List of Pins and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (4/5)
Pin Number
177-Pin
TFLGA
176-Pin
LFBGA
Power Supply
Clock System
Control
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
MTIOC4A/MTCLKA/
TIOCB4/TMRI1/PO4
SCK3
I/O Port
Bus
M3
P24
CS4#
M4
P86
TIOCA0
M5
P13
MTIOC0B/TIOCA5/TMO3/
PO13
M6
P56
WR2#/BC2#
MTIOC3C/TIOCA1
P54
ALE
MTIOC4B/TMCI1
M7
M8
BCLK
TXD2/SMOSI2/SSDA2/
SDA0[FM+]
Interrupt
S12AD,
AD, DA
IRQ3
ADTRG#
CTS2#/RTS2#/S2#/CTX1
P53*3
M9
P50
WR0#/WR#
M10
PC5
A21/CS2#/
WAIT#
M11
P81
TXD2/SMOSI2/SSDA2/
SSLB1
MTIOC3B/MTCLKD/
TIOCD6/TCLKF/TMRI2/
PO29
SCK8/RSPCKA
MTIOC3D/PO27
RXD10/SMISO10/SSCL10
TXD11/SMOSI11/SSDA11
M12
P77
CS7#
PO23
M13
PB7
A15
MTIOC3B/TIOCB5/PO31
TXD9/SMOSI9/SSDA9
M14
PB5
A13
MTIOC2A/MTIOC1B/
TIOCB4/TMRI1/PO29/
POE1#
SCK9
M15
PB4
A12
TIOCA4/PO28
CTS9#/RTS9#/SS9#
N1
PH5
N2
P23
MTIOC3D/MTCLKD/
TIOCD3/PO3
TXD3/CTS0#/RTS0#/
SMOSI3/SS0#/SSDA3
N3
P22
MTIOC3B/MTCLKC/
TIOCC3/TMO0/PO2
SCK0
N4
P15
MTIOC0B/MTCLKB/
TIOCB2/TCLKB/TMCI2/
PO13
RXD1/SCK3/SMISO1/
SSCL1/CRX1-DS
IRQ5
N5
P12
MTIC5U/TMCI1
RXD2/SMISO2/SSCL2/
SCL0[FM+]
IRQ2
N6
P57
WAIT#/WR3#/
BC3#
N7
P55
WAIT#
MTIOC4D/TMO3
CRX1/
IRQ10
N8
PL2
N9
P51
WR1#/BC1#/
WAIT#
N10
PC7
A23/CS0#
N11
P82
N12
PC3
N13
SCK2/SSLB2
MTIOC3A/MTCLKB/
TIOCB6/TMO2/PO31
TXD8/SMOSI8/SSDA8/
MISOA
MTIOC4A/PO28
TXD10/SMOSI10/SSDA10
A19
MTIOC4D/TCLKB/PO24
TXD5/SMOSI5/SSDA5/
IETXD
PC0
A16
MTIOC3C/TCLKC/PO17
CTS5#/RTS5#/SS5#/
SSLA1/SCL3
IRQ14
N14
P73
CS3#
PO16
N15
PL0
P1
PH4
P2
P17
SCK1/TXD3/SMOSI3/
SSDA3/MISOA/SDA2-DS/
IETXD
IRQ7
CTS1#/RTS1#/SS1#/
CTX1/USB0_DPUPE
IRQ4
MTIOC3A/MTIOC3B/
TIOCB0/TCLKD/TMO1/
PO15/POE8#
P3
P87
TIOCA2
P4
P14
MTIOC3A/MTCLKA/
TIOCB5/TCLKA/TMRI2/
PO15
P10
MTIC5W/TMRI3
P5
P6
IRQ14
ADTRG#
IRQ0
VCC_USB
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 28 of 154
RX630 Group
Table 1.5
1. Overview
List of Pins and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (5/5)
Pin Number
177-Pin
TFLGA
176-Pin
LFBGA
Power Supply
Clock System
Control
P7
VSS_USB
I/O Port
P8
PL3
P9
P52
P10
P83
P11
PC6
P12
P13
Bus
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
RD#
Interrupt
S12AD,
AD, DA
RXD2/SMISO2/SSCL2/
SSLB3
MTIOC4C
CTS10#/RTS10#/SS10#
A22/CS1#
MTIOC3C/MTCLKA/
TIOCA6/TMCI2/PO30
RXD8/SMISO8/SSCL8/
MOSIA
PC4
A20/CS3#
MTIOC3D/MTCLKC/
TIOCC6/TCLKE/TMCI1/
PO25/POE0#
SCK5/CTS8#/RTS8#/
SS8#/SSLA0
PC2
A18
MTIOC4B/TCLKA/PO21
RXD5/SMISO5/SSCL5/
SSLA3/IERXD
CS5#
PO20
SCK11
IRQ13
P14
P75
P15
PL1
R1
P21
MTIOC1B/TIOCA3/
TMCI0/PO1
RXD0/SMISO0/SSCL0/
SCL1
IRQ9
R2
P20
MTIOC1A/TIOCB3/
TMRI0/PO0
TXD0/SMOSI0/SSDA0/
SDA1
IRQ8
R3
P16
MTIOC3C/MTIOC3D/
TIOCB1/TCLKC/TMO2/
PO14/RTCOUT
TXD1/RXD3/SMOSI1/
SMISO3/SSDA1/SSCL3/
MOSIA/SCL2-DS/IERXD/
USB0_VBUS
IRQ6
R4
P85
R5
P11
MTIC5V/TMCI3
SCK2
IRQ1
R6
ADTRG0#
USB0_DM
R7
USB0_DP
R8
PL4
R9
P84
R10
VSS
R11
VCC
R12
P80
R13
P76
CS6#
MTIOC3B/PO26
SCK10
PO22
RXD11/SMISO11/SSCL11
R14
P74
R15
PC1
CS4#
PO19
CTS11#/RTS11#/SS11#
A17
MTIOC3A/TCLKD/PO18
SCK5/SSLA2/SDA3
IRQ12
Note 1. The 176-pin LFBGA does not include the E5 pin.
Note 2. Enabled only for the ROM capacity: 2 MB/1.5 MB
Note 3. The BCLK function is multiplexed with the I/O port function for pin P53, so the port function is not available if the external bus is
enabled.
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 29 of 154
RX630 Group
Table 1.6
Pin Number
1. Overview
List of Pins and Pin Functions (176-Pin LQFP) (1/5)
176-Pin
LQFP
Power Supply
Clock System
Control
1
AVSS0
2
3
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
Interrupt
S12AD,
AD, DA
P05
IRQ13
DA1
P03
IRQ11
DA0
I/O Port
Bus
VREFH
4
5
Timer
VREFL
6
P02
TMCI1
SCK6
IRQ10
AN020
7
P01
TMCI0
RXD6/SMISO6/SSCL6
IRQ9
AN019
8
P00
TMRI0
TXD6/SMOSI6/SSDA6
IRQ8
AN018
9
PF5
10
EMLE
11
12
PJ5
VSS
13
14
IRQ4
PJ3
MTIOC3C
CTS6#/RTS6#/CTS0#/
RTS0#/SS6#/SS0#
VCL
15
VBATT
16
NC
17
TRST#
18
MD/FINED
19
XCIN
20
XCOUT
21
RES#
22
XTAL
23
VSS
24
EXTAL
25
VCC
PF4
P37
P36
26
P35
27
P34
MTIOC0A/TMCI3/PO12/
POE2#
SCK6/SCK0
IRQ4
28
P33
MTIOC0D/TIOCD0/
TMRI3/PO11/POE3#
RXD6/RXD0/SMISO6/
SMISO0/SSCL6/SSCL0/
CRX0
IRQ3-DS
29
P32
MTIOC0C/TIOCC0/TMO3/
PO10/RTCOUT/RTCIC2
TXD6/TXD0/SMOSI6/
SMOSI0/SSDA6/SSDA0/
CTX0
IRQ2-DS
30
TMS
PF3
31
TDI
PF2
NMI
RXD1/SMISO1/SSCL1
32
P31
MTIOC4D/TMCI2/PO9/
RTCIC1
CTS1#/RTS1#/SS1#/
SSLB0
IRQ1-DS
33
P30
MTIOC4B/TMRI3/PO8/
RTCIC0/POE8#
RXD1/SMISO1/SSCL1/
MISOB
IRQ0-DS
34
TCK/FINEC
35
TDO
PF1
SCK1
PF0
TXD1/SMOSI1/SSDA1
36
P27
CS7#
MTIOC2B/TMCI3/PO7
SCK1/RSPCKB
37
P26
CS6#
MTIOC2A/TMO1/PO6
TXD1/CTS3#/RTS3#/
SMOSI1/SS3#/SSDA1/
MOSIB
38
P25
CS5#
MTIOC4C/MTCLKB/
TIOCA4/PO5
RXD3/SMISO3/SSCL3
39
PH5
40
P24
CS4#
MTIOC4A/MTCLKA/
TIOCB4/TMRI1/PO4
SCK3
R01DS0060EJ0160 Rev.1.60
May 19, 2014
ADTRG0#
Page 30 of 154
RX630 Group
Table 1.6
Pin Number
176-Pin
LQFP
1. Overview
List of Pins and Pin Functions (176-Pin LQFP) (2/5)
Power Supply
Clock System
Control
I/O Port
Bus
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
Interrupt
S12AD,
AD, DA
41
PH4
42
P23
MTIOC3D/MTCLKD/
TIOCD3/PO3
TXD3/CTS0#/RTS0#/
SMOSI3/SS0#/SSDA3
43
P22
MTIOC3B/MTCLKC/
TIOCC3/TMO0/PO2
SCK0
44
P21
MTIOC1B/TIOCA3/
TMCI0/PO1
RXD0/SMISO0/SSCL0/
SCL1
IRQ9
45
P20
MTIOC1A/TIOCB3/
TMRI0/PO0
TXD0/SMOSI0/SSDA0/
SDA1
IRQ8
46
P17
MTIOC3A/MTIOC3B/
TIOCB0/TCLKD/TMO1/
PO15/POE8#
SCK1/TXD3/SMOSI3/
SSDA3/MISOA/SDA2-DS/
IETXD
IRQ7
ADTRG#
47
P87
TIOCA2
48
P16
MTIOC3C/MTIOC3D/
TIOCB1/TCLKC/TMO2/
PO14/RTCOUT
TXD1/RXD3/SMOSI1/
SMISO3/SSDA1/SSCL3/
MOSIA/SCL2-DS/IERXD/
USB0_VBUS
IRQ6
ADTRG0#
49
P86
TIOCA0
50
P15
MTIOC0B/MTCLKB/
TIOCB2/TCLKB/TMCI2/
PO13
RXD1/SCK3/SMISO1/
SSCL1/CRX1-DS
IRQ5
51
P14
MTIOC3A/MTCLKA/
TIOCB5/TCLKA/TMRI2/
PO15
CTS1#/RTS1#/SS1#/
CTX1/USB0_DPUPE
IRQ4
52
P85
53
P13
MTIOC0B/TIOCA5/
TMO3/PO13
TXD2/SMOSI2/SSDA2/
SDA0[FM+]
IRQ3
54
P12
MTIC5U/TMCI1
RXD2/SMISO2/SSCL2/
SCL0[FM+]
IRQ2
55
P11
MTIC5V/TMCI3
SCK2
IRQ1
56
P10
MTIC5W/TMRI3
57
IRQ0
VCC_USB
58
USB0_DM
59
USB0_DP
60
VSS_USB
61
P57
WAIT#/WR3#/
BC3#
62
P56
WR2#/BC2#
63
PL4
64
PL3
MTIOC3C/TIOCA1
65
PL2
66
P55
WAIT#
MTIOC4D/TMO3
CRX1
67
P54
ALE
MTIOC4B/TMCI1
CTS2#/RTS2#/SS2#/
CTX1
68
BCLK
P84
70
P52
RD#
RXD2/SMISO2/SSCL2/
SSLB3
71
P51
WR1#/BC1#/
WAIT#
SCK2/SSLB2
72
P50
WR0#/WR#
TXD2/SMOSI2/SSDA2/
SSLB1
VSS
74
75
IRQ10
P53*1
69
73
ADTRG#
P83
MTIOC4C
CTS10#/RTS10#/SS10#
VCC
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 31 of 154
RX630 Group
Table 1.6
Pin Number
176-Pin
LQFP
1. Overview
List of Pins and Pin Functions (176-Pin LQFP) (3/5)
Power Supply
Clock System
Control
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
I/O Port
Bus
76
PC7
A23/CS0#
MTIOC3A/MTCLKB/
TIOCB6/TMO2/PO31
TXD8/SMOSI8/SSDA8/
MISOA
IRQ14
77
PC6
A22/CS1#
MTIOC3C/MTCLKA/
TIOCA6/TMCI2/PO30
RXD8/SMISO8/SSCL8/
MOSIA
IRQ13
78
PC5
A21/CS2#/
WAIT#
MTIOC3B/MTCLKD/
TIOCD6/TCLKF/TMRI2/
PO29
SCK8/RSPCKA
79
P82
MTIOC4A/PO28
TXD10/SMOSI10/SSDA10
80
P81
MTIOC3D/PO27
RXD10/SMISO10/
SSCL10
81
P80
MTIOC3B/PO26
SCK10
82
PC4
A20/CS3#
MTIOC3D/MTCLKC/
TIOCC6/TCLKE/TMCI1/
PO25/POE0#
SCK5/CTS8#/RTS8#/
SS8#/SSLA0
83
PC3
A19
MTIOC4D/TCLKB/PO24
TXD5/SMOSI5/SSDA5/
IETXD
84
P77
CS7#
PO23
TXD11/SMOSI11/SSDA11
85
P76
CS6#
PO22
RXD11/SMISO11/SSCL11
86
PC2
A18
MTIOC4B/TCLKA/PO21
RXD5/SMISO5/SSCL5/
SSLA3/IERXD
87
P75
CS5#
PO20
SCK11
Interrupt
88
P74
CS4#
PO19
CTS11#/RTS11#/SS11#
89
PC1
A17
MTIOC3A/TCLKD/PO18
SCK5/SSLA2/SDA3
IRQ12
A16
MTIOC3C/TCLKC/PO17
CTS5#/RTS5#/SS5#/
SSLA1/SCL3
IRQ14
90
PL1
91
PC0
92
PL0
93
P73
CS3#
PO16
94
PB7
A15
MTIOC3B/TIOCB5/PO31
TXD9/SMOSI9/SSDA9
95
PB6
A14
MTIOC3D/TIOCA5/PO30
RXD9/SMISO9/SSCL9
96
PB5
A13
MTIOC2A/MTIOC1B/
TIOCB4/TMRI1/PO29/
POE1#
SCK9
97
PB4
A12
TIOCA4/PO28
CTS9#/RTS9#/SS9#
98
PB3
A11
MTIOC0A/MTIOC4A/
TIOCD3/TCLKD/TMO0/
PO27/POE3#
SCK4/SCK6
99
PB2
A10
TIOCC3/TCLKC/PO26
CTS4#/RTS4#/CTS6#/
RTS6#/SS4#/SS6#
100
PB1
A9
MTIOC0C/MTIOC4C/
TIOCB3/TMCI0/PO25
TXD4/TXD6/SMOSI4/
SMOSI6/SSDA4/SSDA6
IRQ4-DS
101
P72
CS2#
102
P71
CS1#
103
PK7
104
PB0
MTIC5W/TIOCA3/PO24
RXD4/RXD6/SMISO4/
SMISO6/SSCL4/SSCL6/
RSPCKA
IRQ12
105
PK6
A8
106
PA7
A7
TIOCB2/PO23
MISOA
107
PA6
A6
MTIC5V/MTCLKB/
TIOCA2/TMCI3/PO22/
POE2#
CTS5#/RTS5#/SS5#/
MOSIA
108
PA5
A5
TIOCB1/PO21
RSPCKA
109
PA4
A4
MTIC5U/MTCLKA/
TIOCA1/TMRI0/PO20
TXD5/SMOSI5/SSDA5/
SSLA0
R01DS0060EJ0160 Rev.1.60
May 19, 2014
S12AD,
AD, DA
IRQ5-DS
Page 32 of 154
RX630 Group
Table 1.6
Pin Number
176-Pin
LQFP
1. Overview
List of Pins and Pin Functions (176-Pin LQFP) (4/5)
Power Supply
Clock System
Control
110
111
TRDATA3
112
113
TRDATA2
114
115
VCC
116
TRCLK
117
VSS
118
119
TRSYNC#
I/O Port
Bus
PA3
A3
PG7
D31
PA2
A2
PG6
D30
PA1
A1
PG5
D29
PA0
A0/BC0#
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
Interrupt
MTIOC0D/MTCLKD/
TIOCD0/TCLKB/PO19
RXD5/SMISO5/SSCL5
IRQ6-DS
PO18
RXD5/SMISO5/SSCL5/
SSLA3
MTIOC0B/MTCLKC/
TIOCB0/PO17
SCK5/SSLA2
MTIOC4A/TIOCA0/PO16
SSLA1
S12AD,
AD, DA
IRQ11
PG4
D28
P67
CS7#
PG3
D27
P66
CS6#
PG2
D26
124
P65
CS5#
125
PE7
D15[A15/D15]
TIOCB11
MISOB
IRQ7
AN5
126
PE6
D14[A14/D14]
TIOCA11
CTS4#/RTS4#/SS4#/
MOSIB
IRQ6
AN4
IRQ5
AN3
120
121
TRDATA1
122
123
TRDATA0
CRX2*2
IRQ15
CTX2*2
127
PK5
TXD4/SMOSI4/SSDA4
128
P70
SCK4
129
PK4
130
PE5
D13[A13/D13]
MTIOC4C/MTIOC2B/
TIOCB10
RSPCKB
RXD4/SMISO4/SSCL4
131
PE4
D12[A12/D12]
MTIOC4D/MTIOC1A/
TIOCA10/PO28
SSLB0
AN2
132
PE3
D11[A11/D11]
MTIOC4B/TIOCB9/PO26/
POE8#
CTS12#/RTS12#/SS12#/
MISOB
AN1
133
PE2
D10[A10/D10]
MTIOC4A/TIOCA9/PO23
RXD12/SMISO12/
SSCL12/RXDX12/SSLB3/
MOSIB
134
PE1
D9[A9/D9]
MTIOC4C/TIOCD9/PO18
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/SSLB2/RSPCKB
ANEX1
TIOCC9
SCK12/SSLB1
ANEX0
135
PE0
D8[A8/D8]
136
P64
CS4#
137
P63
CS3#
138
P62
CS2#
139
P61
CS1#
CTS9#/RTS9#/SS9#
140
PK3
141
P60
CS0#
SCK9
142
PK2
143
PD7
144
PG1
D25
145
PD6
D6[A6/D6]
146
PG0
D24
IRQ7-DS
AN0
RXD9/SMISO9/SSCL9
TXD9/SMOSI9/SSDA9
D7[A7/D7]
MTIC5U/POE0#
SSLC3
IRQ7
AN7
MTIC5V/POE1#
SSLC2
IRQ6
AN6
147
PD5
D5[A5/D5]
MTIC5W/POE2#
SSLC1
IRQ5
AN013
148
PD4
D4[A4/D4]
POE3#
SSLC0
IRQ4
AN012
149
P97
A23/D23
150
PD3
D3[A3/D3]
TIOCB8/TCLKH/POE8#
RSPCKC
IRQ3
AN011
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 33 of 154
RX630 Group
Table 1.6
Pin Number
176-Pin
LQFP
1. Overview
List of Pins and Pin Functions (176-Pin LQFP) (5/5)
Power Supply
Clock System
Control
I/O Port
151
PK1
152
P96
153
PK0
154
PD2
Bus
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
Interrupt
S12AD,
AD, DA
MTIOC4D/TIOCA8
MISOC/CRX0
IRQ2
AN010
MTIOC4B/TIOCB7/CLKG
MOSIC/CTX0
IRQ1
AN009
A22/D22
D2[A2/D2]
155
P95
A21/D21
156
PD1
D1[A1/D1]
157
P94
A20/D20
158
PD0
D0[A0/D0]
159
P93
A19/D19
TIOCA7
IRQ0
AN008
CTS7#/RTS7#/SS7#
AN017
160
P92
A18/D18
RXD7/SMISO7/SSCL7
AN016
161
P91
A17/D17
SCK7
AN015
P90
A16/D16
TXD7/SMOSI7/SSDA7
AN014
162
VSS
163
164
VCC
165
P47
IRQ15-DS
AN007
166
P46
IRQ14-DS
AN006
167
P45
IRQ13-DS
AN005
168
P44
IRQ12-DS
AN004
169
P43
IRQ11-DS
AN003
170
P42
IRQ10-DS
AN002
171
P41
IRQ9-DS
AN001
P40
IRQ8-DS
AN000
P07
IRQ15
ADTRG0#
172
VREFL0
173
174
VREFH0
175
AVCC0
176
Note 1. The BCLK function is multiplexed with the I/O port function for pin P53, so the port function is not available if the external bus is
enabled.
Note 2. Enabled only for the ROM capacity: 2 MB/1.5 MB
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 34 of 154
RX630 Group
Table 1.7
Pin Number
1. Overview
List of Pins and Pin Functions (145-Pin TFLGA) (1/4)
145-Pin
TFLGA
Power Supply
Clock System
Control
A1
AVSS0
I/O Port
Bus
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
Interrupt
S12AD,
AD, DA
ADTRG0#
A2
P07
IRQ15
A3
P40
IRQ8-DS
AN000
A4
P42
IRQ10-DS
AN002
IRQ13-DS
AN005
A5
P45
A6
P90
A16
TXD7/SMOSI7/SSDA7
AN014
A7
P92
A18
RXD7/SMISO7/SSCL7
AN016
A8
PD2
D2[A2/D2]
MTIOC4D/TIOCA8
MISOC/CRX0
IRQ2
AN010
A9
PD6
D6[A6/D6]
MTIC5V/POE1#
SSLC2
IRQ6
AN6
A10
PK3
A11
P62
CS2#
A12
PE1
D9[A9/D9]
MTIOC4C/TIOCD9/PO18
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/SSLB2/RSPCKB
ANEX1
A13
PE3
D11[A11/D11]
MTIOC4B/TIOCB9/PO26/
POE8#
CTS12#/RTS12#/SS12#/
MISOB
AN1
B1
VREFH
B2
AVCC0
B3
RXD9/SMISO9/SSCL9
P05
IRQ13
B5
P43
IRQ11-DS
AN003
B6
P47
IRQ15-DS
AN007
IRQ0
AN008
IRQ4
AN012
IRQ7-DS
AN0
B4
B7
P91
A17
B8
PD0
D0[A0/D0]
TIOCA7
B9
PD4
D4[A4/D4]
POE3#
SCK7
SSLC0
B10
PK2
B11
P61
CS1#
B12
PE2
D10[A10/D10]
MTIOC4A/TIOCA9/PO23
RXD12/SMISO12/
SSCL12/RXDX12/SSLB3/
MOSIB
B13
PE4
D12[A12/D12]
MTIOC4D/MTIOC1A/
TIOCA10/PO28
SSLB0
TMCI1
SCK6
C1
AN015
TXD9/SMOSI9/SSDA9
CTS9#/RTS9#/SS9#
AN2
VREFL
C2
C3
DA1
VREFL0
P02
IRQ10
AN020
VREFH0
C4
P41
IRQ9-DS
AN001
C5
P46
IRQ14-DS
AN006
C6
VSS
C7
PD1
D1[A1/D1]
MTIOC4B/TIOCB7/
TCLKG
MOSIC/CTX0
IRQ1
AN009
C8
PD3
D3[A3/D3]
TIOCB8/TCLKH/POE8#
RSPCKC
IRQ3
AN011
MTIC5U/POE0#
SSLC3
IRQ7
AN7
TIOCC9
SCK12/SSLB1
C9
PD7
D7[A7/D7]
C10
P63
CS3#
C11
PE0
D8[A8/D8]
ANEX0
C12
P70
SCK4
C13
PK4
RXD4/SMISO4/SSCL4
D1
P00
D2
PF5
IRQ4
D3
P03
IRQ11
DA0
D4
P01
IRQ9
AN019
R01DS0060EJ0160 Rev.1.60
May 19, 2014
TMRI0
TMCI0
TXD6/SMOSI6/SSDA6
RXD6/SMISO6/SSCL6
IRQ8
AN018
Page 35 of 154
RX630 Group
Table 1.7
Pin Number
1. Overview
List of Pins and Pin Functions (145-Pin TFLGA) (2/4)
145-Pin
TFLGA
Power Supply
Clock System
Control
D5
VCC
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
I/O Port
Bus
D6
P93
A19
D7
PD5
D5[A5/D5]
D8
P60
CS0#
D9
P64
CS4#
D10
PE7
D15[A15/D15]
D11
PK5
D12
PE5
D13[A13/D13]
MTIOC4C/MTIOC2B/
TIOCB10
D13
PE6
D14[A14/D14]
TIOCA11
E1
VSS
E2
VCL
E3
E4
CTS7#/RTS7#/SS7#
MTIC5W/POE2#
SSLC1
AN017
IRQ5
AN013
IRQ7
AN5
RSPCKB
IRQ5
AN3
CTS4#/RTS4#/SS4#/
MOSIB
IRQ6
AN4
IRQ12-DS
AN004
SCK9
TIOCB11
MISOB
TXD4/SMOSI4/SSDA4
PJ5
EMLE
E5
P44
E10
PA0
A0/BC0#
E11
P66
CS6#
E12
P65
CS5#
E13
P67
CS7#
F1
XCIN
F2
XCOUT
F3
F4
PJ3
MTIOC4A/TIOCA0/PO16
SSLA1
CTX2*1
CRX2*1
MTIOC3C
CTS6#/RTS6#/CTS0#/
RTS0#/SS6#/SS0#
IRQ15
VBATT
F10
PA3
A3
MTIOC0D/MTCLKD/
TIOCD0/TCLKB/PO19
RXD5/SMISO5/SSCL5
IRQ6-DS
F12
PA1
A1
MTIOC0B/MTCLKC/
TIOCB0/PO17
SCK5/SSLA2
IRQ11
F13
PA2
A2
PO18
RXD5/SMISO5/SSCL5/
SSLA3
F11
VSS
G1
XTAL
G2
RES#
G3
MD/FINED
G4
BSCANP
P37
G10
PA5
A5
TIOCB1/PO21
RSPCKA
G11
PA6
A6
MTIC5V/MTCLKB/
TIOCA2/TMCI3/PO22/
POE2#
CTS5#/RTS5#/SS5#/
MOSIA
PA4
A4
MTIC5U/MTCLKA/
TIOCA1/TMRI0/PO20
TXD5/SMOSI5/SSDA5/
SSLA0
G12
S12AD,
AD, DA
Interrupt
VCC
G13
H1
EXTAL
H2
VCC
H3
VSS
IRQ5-DS
P36
H4
P35
H10
P72
H11
P71
CS1#
H12
PB0
A8
R01DS0060EJ0160 Rev.1.60
May 19, 2014
NMI
CS2#
MTIC5W/TIOCA3/PO24
RXD4/RXD6/SMISO4/
SMISO6/SSCL4/SSCL6/
RSPCKA
IRQ12
Page 36 of 154
RX630 Group
Table 1.7
Pin Number
145-Pin
TFLGA
1. Overview
List of Pins and Pin Functions (145-Pin TFLGA) (3/4)
Power Supply
Clock System
Control
H13
Timer
Communications
I/O Port
Bus
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
PA7
A7
Interrupt
TIOCB2/PO23
MISOA
P34
MTIOC0A/TMCI3/PO12/
POE2#
SCK6/SCK0
IRQ4
J2
P33
MTIOC0D/TIOCD0/
TMRI3/PO11/POE3#
RXD6/RXD0/SMISO6/
SMISO0/SSCL6/SSCL0/
CRX0
IRQ3-DS
J3
P32
MTIOC0C/TIOCC0/TMO3/
PO10/RTCOUT/RTCIC2
TXD6/TXD0/SMOSI6/
SMOSI0/SSDA6/SSDA0/
CTX0
IRQ2-DS
P30
MTIOC4B/TMRI3/PO8/
RTCIC0/POE8#
RXD1/SMISO1/SSCL1/
MISOB
IRQ0-DS
J1
J4
TRST#
TDI
J10
PB3
A11
MTIOC0A/MTIOC4A/
TIOCD3/TCLKD/TMO0/
PO27/POE3#
SCK4/SCK6
J11
PB4
A12
TIOCA4/PO28
CTS9#/RTS9#/SS9#
J12
PB2
A10
TIOCC3/TCLKC/PO26
CTS4#/RTS4#/CTS6#/
RTS6#/SS4#/SS6#
J13
PB1
A9
MTIOC0C/MTIOC4C/
TIOCB3/TMCI0/PO25
TXD4/TXD6/SMOSI4/
SMOSI6/SSDA4/SSDA6
IRQ4-DS
K1
TCK/FINEC
P27
CS7#
MTIOC2B/TMCI3/PO7
SCK1/RSPCKB
K2
TDO
P26
CS6#
MTIOC2A/TMO1/PO6
TXD1/CTS3#/RTS3#/
SMOSI1/SS3#/SSDA1/
MOSIB
K3
TMS
P31
MTIOC4D/TMCI2/PO9/
RTCIC1
CTS1#/RTS1#/SS1#/
SSLB0
IRQ1-DS
P15
MTIOC0B/MTCLKB/
TIOCB2/TCLKB/TMCI2/
PO13
RXD1/SCK3/SMISO1/
SSCL1/CRX1-DS
IRQ5
MTIOC4B/TMCI1
CTS2#/RTS2#/SS2#/
CTX1
K4
K5
TRDATA2
P54
ALE
K6
P53*2
BCLK
K7
P51
WR1#/BC1#/
WAIT#
K8
VCC
K9
TRDATA0
K10
P80
P76
CS6#
SCK2/SSLB2
MTIOC3B/PO26
SCK10
PO22
RXD11/SMISO11/SSCL11
K11
PB7
A15
MTIOC3B/TIOCB5/PO31
TXD9/SMOSI9/SSDA9
K12
PB6
A14
MTIOC3D/TIOCA5/PO30
RXD9/SMISO9/SSCL9
K13
PB5
A13
MTIOC2A/MTIOC1B/
TIOCB4/TMRI1/PO29/
POE1#
SCK9
L1
P25
CS5#
MTIOC4C/MTCLKB/
TIOCA4/PO5
RXD3/SMISO3/SSCL3
L2
P23
MTIOC3D/MTCLKD/
TIOCD3/PO3
TXD3/CTS0#/RTS0#/
SMOSI3/SS0#/SSDA3
L3
P16
MTIOC3C/MTIOC3D/
TIOCB1/TCLKC/TMO2/
PO14/RTCOUT
TXD1/RXD3/SMOSI1/
SMISO3/SSDA1/SSCL3/
MOSIA/SCL2-DS/IERXD/
USB0_VBUS
L4
P24
MTIOC4A/MTCLKA/
TIOCB4/TMRI1/PO4
SCK3
L5
P13
MTIOC0B/TIOCA5/TMO3/
PO13
TXD2/SMOSI2/SSDA2/
SDA0[FM+]
L6
P56
L7
P52
L8
TRCLK
P83
R01DS0060EJ0160 Rev.1.60
May 19, 2014
CS4#
S12AD,
AD, DA
ADTRG0#
IRQ6
ADTRG0#
IRQ3
ADTRG#
MTIOC3C/TIOCA1
RD#
RXD2/SMISO2/SSCL2/
SSLB3
MTIOC4C
CTS10#/RTS10#/SS10#
Page 37 of 154
RX630 Group
Table 1.7
Pin Number
145-Pin
TFLGA
1. Overview
List of Pins and Pin Functions (145-Pin TFLGA) (4/4)
Power Supply
Clock System
Control
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
I/O Port
Bus
L9
PC5
A21/CS2#/
WAIT#
MTIOC3B/MTCLKD/
TIOCD6/TCLKF/TMRI2/
PO29
SCK8/RSPCKA
L10
PC4
A20/CS3#
MTIOC3D/MTCLKC/
TIOCC6/TCLKE/TMCI1/
PO25/POE0#
SCK5/CTS8#/RTS8#/
SS8#/SSLA0
L11
PC2
A18
MTIOC4B/TCLKA/PO21
RXD5/SMISO5/SSCL5/
SSLA3/IERXD
L12
P73
CS3#
PO16
Interrupt
S12AD,
AD, DA
ADTRG#
L13
PL0
M1
P22
MTIOC3B/MTCLKC/
TIOCC3/TMO0/PO2
SCK0
M2
P17
MTIOC3A/MTIOC3B/
TIOCB0/TCLKD/TMO1/
PO15/POE8#
SCK1/TXD3/SMOSI3/
SSDA3/MISOA/SDA2-DS/
IETXD
IRQ7
M3
P86
TIOCA0
M4
P12
TMCI1
RXD2/SMISO2/SSCL2/
SCL0[FM+]
IRQ2
M5
VCC_USB
M6
VSS_USB
M7
P50
WR0#/WR#
M8
PC6
A22/CS1#
M9
TRDATA1
P81
TXD2/SMOSI2/SSDA2/
SSLB1
MTIOC3C/MTCLKA/
TIOCA6/TMCI2/PO30
RXD8/SMISO8/SSCL8/
MOSIA
MTIOC3D/PO27
RXD10/SMISO10/SSCL10
IRQ13
M10
P77
CS7#
PO23
TXD11/SMOSI11/SSDA11
M11
PC0
A16
MTIOC3C/TCLKC/PO17
CTS5#/RTS5#/SS5#/
SSLA1/SCL3
IRQ14
M12
PC1
A17
MTIOC3A/TCLKD/PO18
SCK5/SSLA2/SDA3
IRQ12
M13
PL1
N1
P21
MTIOC1B/TIOCA3/
TMCI0/PO1
RXD0/SMISO0/SSCL0/
SCL1
IRQ9
N2
P20
MTIOC1A/TIOCB3/
TMRI0/PO0
TXD0/SMOSI0/SSDA0/
SDA1
IRQ8
N3
P87
TIOCA2
N4
P14
MTIOC3A/MTCLKA/
TIOCB5/TCLKA/TMRI2/
PO15
CTS1#/RTS1#/SS1#/
CTX1/USB0_DPUPE
IRQ4
N5
USB0_DM
N6
USB0_DP
N7
TRDATA3
N8
VSS
N9
N10
TRSYNC#
P55
WAIT#
MTIOC4D/TMO3
CRX1
IRQ10
PC7
A23/CS0#
MTIOC3A/MTCLKB/
TIOCB6/TMO2/PO31
TXD8/SMOSI8/SSDA8/
MISOA
IRQ14
MTIOC4A/PO28
TXD10/SMOSI10/SSDA10
N11
P82
PC3
A19
MTIOC4D/TCLKB/PO24
TXD5/SMOSI5/SSDA5/
IETXD
N12
P75
CS5#
PO20
SCK11
N13
P74
CS4#
PO19
CTS11#/RTS11#/SS11#
Note 1. Enabled only for the ROM capacity: 2 MB/1.5 MB
Note 2. The BCLK function is multiplexed with the I/O port function for pin P53, so the port function is not available if the external bus is
enabled.
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 38 of 154
RX630 Group
Table 1.8
Pin Number
1. Overview
List of Pins and Pin Functions (144-Pin LQFP) (1/4)
144-Pin
LQFP
Power Supply
Clock System
Control
1
AVSS0
2
3
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
Interrupt
S12AD,
AD, DA
P05
IRQ13
DA1
P03
IRQ11
DA0
I/O Port
Bus
VREFH
4
5
Timer
VREFL
6
P02
TMCI1
SCK6
IRQ10
AN020
7
P01
TMCI0
RXD6/SMISO6/SSCL6
IRQ9
AN019
8
P00
TMRI0
TXD6/SMOSI6/SSDA6
IRQ8
AN018
9
PF5
10
EMLE
11
12
PJ5
VSS
13
PJ3
14
VCL
15
VBATT
16
MD/FINED
17
XCIN
18
XCOUT
19
RES#
20
XTAL
21
VSS
22
EXTAL
23
VCC
24
25
IRQ4
MTIOC3C
CTS6#/RTS6#/CTS0#/
RTS0#/SS6#/SS0#
P37
P36
P35
TRST#
NMI
P34
MTIOC0A/TMCI3/PO12/
POE2#
SCK6/SCK0
IRQ4
26
P33
MTIOC0D/TIOCD0/
TMRI3/PO11/POE3#
RXD6/RXD0/SMISO6/
SMISO0/SSCL6/SSCL0/
CRX0
IRQ3-DS
27
P32
MTIOC0C/TIOCC0/TMO3/
PO10/RTCOUT/RTCIC2
TXD6/TXD0/SMOSI6/
SMOSI0/SSDA6/SSDA0/
CTX0
IRQ2-DS
28
TMS
P31
MTIOC4D/TMCI2/PO9/
RTCIC1
CTS1#/RTS1#/SS1#/
SSLB0
IRQ1-DS
29
TDI
P30
MTIOC4B/TMRI3/PO8/
RTCIC0/POE8#
RXD1/SMISO1/SSCL1/
MISOB
IRQ0-DS
30
TCK/FINEC
P27
CS7#
MTIOC2B/TMCI3/PO7
SCK1/RSPCKB
31
TDO
P26
CS6#
MTIOC2A/TMO1/PO6
TXD1/CTS3#/RTS3#/
SMOSI1/SS3#/SSDA1/
MOSIB
32
P25
CS5#
MTIOC4C/MTCLKB/
TIOCA4/PO5
RXD3/SMISO3/SSCL3
33
P24
CS4#
MTIOC4A/MTCLKA/
TIOCB4/TMRI1/PO4
SCK3
34
P23
MTIOC3D/MTCLKD/
TIOCD3/PO3
TXD3/CTS0#/RTS0#/
SMOSI3/SS0#/SSDA3
35
P22
MTIOC3B/MTCLKC/
TIOCC3/TMO0/PO2
SCK0
36
P21
MTIOC1B/TIOCA3/
TMCI0/PO1
RXD0/SMISO0/SSCL0/
SCL1
IRQ9
37
P20
MTIOC1A/TIOCB3/
TMRI0/PO0
TXD0/SMOSI0/SSDA0/
SDA1
IRQ8
R01DS0060EJ0160 Rev.1.60
May 19, 2014
ADTRG0#
Page 39 of 154
RX630 Group
Table 1.8
Pin Number
144-Pin
LQFP
1. Overview
List of Pins and Pin Functions (144-Pin LQFP) (2/4)
Power Supply
Clock System
Control
I/O Port
Bus
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
Interrupt
S12AD,
AD, DA
SCK1/TXD3/SMOSI3/
SSDA3/MISOA/SDA2-DS/
IETXD
IRQ7
ADTRG#
TXD1/RXD3/SMOSI1/
SMISO3/SSDA1/SSCL3/
MOSIA/SCL2-DS/IERXD/
USB0_VBUS
IRQ6
ADTRG0#
38
P17
MTIOC3A/MTIOC3B/
TIOCB0/TCLKD/TMO1/
PO15/POE8#
39
P87
TIOCA2
40
P16
MTIOC3C/MTIOC3D/
TIOCB1/TCLKC/TMO2/
PO14/RTCOUT
41
P86
TIOCA0
42
P15
MTIOC0B/MTCLKB/
TIOCB2/TCLKB/TMCI2/
PO13
RXD1/SCK3/SMISO1/
SSCL1/CRX1-DS
IRQ5
43
P14
MTIOC3A/MTCLKA/
TIOCB5/TCLKA/TMRI2/
PO15
CTS1#/RTS1#/SS1#/
CTX1/USB0_DPUPE
IRQ4
44
P13
MTIOC0B/TIOCA5/TMO3/
PO13
TXD2/SMOSI2/SSDA2/
SDA0[FM+]
IRQ3
45
P12
TMCI1
RXD2/SMISO2/SSCL2/
SCL0[FM+]
IRQ2
46
VCC_USB
47
USB0_DM
48
49
ADTRG#
USB0_DP
VSS_USB
50
P56
MTIOC3C/TIOCA1
51
TRDATA3
P55
WAIT#
MTIOC4D/TMO3
CRX1
52
TRDATA2
P54
ALE
MTIOC4B/TMCI1
CTS2#/RTS2#/SS2#/
CTX1
53
BCLK
P53*1
54
P52
RD#
RXD2/SMISO2/SSCL2/
SSLB3
55
P51
WR1#/BC1#/
WAIT#
SCK2/SSLB2
56
P50
WR0#/WR#
TXD2/SMOSI2/SSDA2/
SSLB1
57
VSS
58
TRCLK
59
VCC
IRQ10
P83
MTIOC4C
CTS10#/RTS10#/SS10#
60
PC7
A23/CS0#
MTIOC3A/MTCLKB/
TIOCB6/TMO2/PO31
TXD8/SMOSI8/SSDA8/
MISOA
IRQ14
61
PC6
A22/CS1#
MTIOC3C/MTCLKA/
TIOCA6/TMCI2/PO30
RXD8/SMISO8/SSCL8/
MOSIA
IRQ13
62
PC5
A21/CS2#/
WAIT#
MTIOC3B/MTCLKD/
TIOCD6/TCLKF/TMRI2/
PO29
SCK8/RSPCKA
63
TRSYNC#
P82
MTIOC4A/PO28
TXD10/SMOSI10/SSDA10
64
TRDATA1
P81
MTIOC3D/PO27
RXD10/SMISO10/SSCL10
65
TRDATA0
MTIOC3B/PO26
SCK10
66
PC4
P80
A20/CS3#
MTIOC3D/MTCLKC/
TIOCC6/TCLKE/TMCI1/
PO25/POE0#
SCK5/CTS8#/RTS8#/
SS8#/SSLA0
67
PC3
A19
MTIOC4D/TCLKB/PO24
TXD5/SMOSI5/SSDA5/
IETXD
68
P77
CS7#
PO23
TXD11/SMOSI11/SSDA11
69
P76
CS6#
PO22
RXD11/SMISO11/SSCL11
70
PC2
A18
MTIOC4B/TCLKA/PO21
RXD5/SMISO5/SSCL5/
SSLA3/IERXD
71
P75
CS5#
PO20
SCK11
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 40 of 154
RX630 Group
Table 1.8
Pin Number
144-Pin
LQFP
1. Overview
List of Pins and Pin Functions (144-Pin LQFP) (3/4)
Power Supply
Clock System
Control
I/O Port
Bus
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
Interrupt
72
P74
CS4#
PO19
CTS11#/RTS11#/SS11#
73
PC1
A17
MTIOC3A/TCLKD/PO18
SCK5/SSLA2/SDA3
IRQ12
A16
MTIOC3C/TCLKC/PO17
CTS5#/RTS5#/SS5#/
SSLA1/SCL3
IRQ14
74
PL1
75
PC0
76
PL0
77
P73
CS3#
PO16
78
PB7
A15
MTIOC3B/TIOCB5/PO31
TXD9/SMOSI9/SSDA9
79
PB6
A14
MTIOC3D/TIOCA5/PO30
RXD9/SMISO9/SSCL9
80
PB5
A13
MTIOC2A/MTIOC1B/
TIOCB4/TMRI1/PO29/
POE1#
SCK9
81
PB4
A12
TIOCA4/PO28
CTS9#/RTS9#/SS9#
82
PB3
A11
MTIOC0A/MTIOC4A/
TIOCD3/TCLKD/TMO0/
PO27/POE3#
SCK4/SCK6
83
PB2
A10
TIOCC3/TCLKC/PO26
CTS4#/RTS4#/CTS6#/
RTS6#/SS4#/SS6#
84
PB1
A9
MTIOC0C/MTIOC4C/
TIOCB3/TMCI0/PO25
TXD4/TXD6/SMOSI4/
SMOSI6/SSDA4/SSDA6
IRQ4-DS
85
P72
CS2#
86
P71
CS1#
87
PB0
A8
MTIC5W/TIOCA3/PO24
RXD4/RXD6/SMISO4/
SMISO6/SSCL4/SSCL6/
RSPCKA
IRQ12
88
PA7
A7
TIOCB2/PO23
MISOA
89
PA6
A6
MTIC5V/MTCLKB/
TIOCA2/TMCI3/PO22/
POE2#
CTS5#/RTS5#/SS5#/
MOSIA
90
PA5
A5
TIOCB1/PO21
RSPCKA
PA4
A4
MTIC5U/MTCLKA/
TIOCA1/TMRI0/PO20
TXD5/SMOSI5/SSDA5/
SSLA0
IRQ5-DS
94
PA3
A3
MTIOC0D/MTCLKD/
TIOCD0/TCLKB/PO19
RXD5/SMISO5/SSCL5
IRQ6-DS
95
PA2
A2
PO18
RXD5/SMISO5/SSCL5/
SSLA3
96
PA1
A1
MTIOC0B/MTCLKC/
TIOCB0/PO17
SCK5/SSLA2
97
PA0
A0/BC0#
MTIOC4A/TIOCA0/PO16
98
P67
CS7#
CRX2*2
CTX2*2
91
VCC
92
93
S12AD,
AD, DA
VSS
IRQ11
SSLA1
IRQ15
99
P66
CS6#
100
P65
CS5#
101
PE7
D15[A15/D15]
TIOCB11
MISOB
IRQ7
AN5
102
PE6
D14[A14/D14]
TIOCA11
CTS4#/RTS4#/SS4#/
MOSIB
IRQ6
AN4
103
PK5
TXD4/SMOSI4/SSDA4
104
P70
SCK4
105
PK4
RXD4/SMISO4/SSCL4
106
PE5
D13[A13/D13]
MTIOC4C/MTIOC2B/
TIOCB10
RSPCKB
IRQ5
AN3
107
PE4
D12[A12/D12]
MTIOC4D/MTIOC1A/
TIOCA10/PO28
SSLB0
R01DS0060EJ0160 Rev.1.60
May 19, 2014
AN2
Page 41 of 154
RX630 Group
Table 1.8
Pin Number
144-Pin
LQFP
1. Overview
List of Pins and Pin Functions (144-Pin LQFP) (4/4)
Power Supply
Clock System
Control
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
S12AD,
AD, DA
I/O Port
Bus
Interrupt
108
PE3
D11[A11/D11]
MTIOC4B/TIOCB9/PO26/
POE8#
CTS12#/RTS12#/SS12#/
MISOB
109
PE2
D10[A10/D10]
MTIOC4A/TIOCA9/PO23
RXD12/SMISO12/
SSCL12/RXDX12/SSLB3/
MOSIB
110
PE1
D9[A9/D9]
MTIOC4C/TIOCD9/PO18
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/SSLB2/RSPCKB
ANEX1
111
PE0
D8[A8/D8]
TIOCC9
SCK12/SSLB1
ANEX0
112
P64
CS4#
113
P63
CS3#
114
P62
CS2#
115
P61
CS1#
116
PK3
AN1
IRQ7-DS
AN0
CTS9#/RTS9#/SS9#
RXD9/SMISO9/SSCL9
117
P60
118
PK2
CS0#
119
PD7
D7[A7/D7]
SCK9
TXD9/SMOSI9/SSDA9
MTIC5U/POE0#
SSLC3
IRQ7
AN7
120
PD6
D6[A6/D6]
MTIC5V/POE1#
SSLC2
IRQ6
AN6
121
PD5
D5[A5/D5]
MTIC5W/POE2#
SSLC1
IRQ5
AN013
122
PD4
D4[A4/D4]
POE3#
SSLC0
IRQ4
AN012
123
PD3
D3[A3/D3]
TIOCB8/TCLKH/POE8#
RSPCKC
IRQ3
AN011
124
PD2
D2[A2/D2]
MTIOC4D/TIOCA8
MISOC/CRX0
IRQ2
AN010
125
PD1
D1[A1/D1]
MTIOC4B/TIOCB7/
TCLKG
MOSIC/CTX0
IRQ1
AN009
126
PD0
D0[A0/D0]
TIOCA7
IRQ0
AN008
127
P93
A19
CTS7#/RTS7#/SS7#
AN017
128
P92
A18
RXD7/SMISO7/SSCL7
AN016
129
P91
A17
SCK7
AN015
P90
A16
TXD7/SMOSI7/SSDA7
AN014
130
VSS
131
132
VCC
133
P47
IRQ15-DS
AN007
134
P46
IRQ14-DS
AN006
135
P45
IRQ13-DS
AN005
136
P44
IRQ12-DS
AN004
137
P43
IRQ11-DS
AN003
138
P42
IRQ10-DS
AN002
139
P41
IRQ9-DS
AN001
P40
IRQ8-DS
AN000
P07
IRQ15
ADTRG0#
140
VREFL0
141
142
VREFH0
143
AVCC0
144
Note 1. The BCLK function is multiplexed with the I/O port function for pin P53, so the port function is not available if the external bus is
enabled.
Note 2. Enabled only for the ROM capacity: 2 MB/1.5 MB
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 42 of 154
RX630 Group
Table 1.9
Pin Number
100-Pin
TFLGA
1. Overview
List of Pins and Pin Functions (100-Pin TFLGA) (1/3)
Power Supply
Clock System
Control
A1
A2
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
Interrupt
S12AD,
AD, DA
P05
IRQ13
DA1
P07
IRQ15
ADTRG0#
I/O Port
Bus
VREFH
A3
A4
Timer
VREFL0
A5
P43
A6
PD0
D0[A0/D0]
A7
PD4
D4[A4/D4]
A8
PE0
D8[A8/D8]
SCK12/SSLB1
ANEX0
A9
PE1
D9[A9/D9]
MTIOC4C/PO18
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/SSLB2/RSPCKB
ANEX1
A10
PE2
D10[A10/D10]
MTIOC4A/PO23
RXD12/SMISO12/
SSCL12/RXDX12/SSLB3/
MOSIB
B1
EMLE
B2
AVSS0
B3
AVCC0
POE3#
B4
P40
B5
P44
B6
PD1
D1[A1/D1]
MTIOC4B
B7
PD3
D3[A3/D3]
B8
PD6
B9
PD7
B10
PE3
C1
VCL
C2
VREFL
C3
C4
IRQ11-DS
AN003
IRQ0
AN008
IRQ4
AN012
IRQ7-DS
AN0
IRQ8-DS
AN000
IRQ12-DS
AN004
IRQ1
AN009
POE8#
IRQ3
AN011
D6[A6/D6]
MTIC5V/POE1#
IRQ6
AN6
D7[A7/D7]
MTIC5U/POE0#
IRQ7
AN7
D11[A11/D11]
MTIOC4B/PO26/POE8#
CTS12#/RTS12#/SS12#/
MISOB
MTIOC3C
CTS6#/RTS6#/CTS0#/
RTS0#/SS6#/SS0#
PJ3
CTX0*1
AN1
VREFH0
C5
P42
IRQ10-DS
C6
P47
IRQ15-DS
AN007
C7
PD2
D2[A2/D2]
MTIOC4D
CRX0*1
IRQ2
AN010
IRQ5
AN013
IRQ5
AN3
C8
PD5
D5[A5/D5]
MTIC5W/POE2#
C9
PE5
D13[A13/D13]
MTIOC4C/MTIOC2B
RSPCKB
C10
PE4
D12[A12/D12]
MTIOC4D/MTIOC1A/
PO28
SSLB0
D1
XCIN
D2
XCOUT
D3
MD/FINED
D4
VBATT
AN002
AN2
D5
P45
IRQ13-DS
D6
P46
IRQ14-DS
AN006
D7
PE6
MOSIB
IRQ6
AN4
AN5
D14[A14/D14]
D8
PE7
D15[A15/D15]
MISOB
IRQ7
D9
PA1
A1
MTIOC0B/MTCLKC/
TIOCB0/PO17
SCK5/SSLA2
IRQ11
PA0
A0/BC0#
MTIOC4A/TIOCA0/PO16
SSLA1
D10
E1
XTAL
E2
VSS
E3
RES#
AN005
P37
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 43 of 154
RX630 Group
Table 1.9
Pin Number
1. Overview
List of Pins and Pin Functions (100-Pin TFLGA) (2/3)
100-Pin
TFLGA
Power Supply
Clock System
Control
I/O Port
E4
TRST#
P34
Bus
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
Interrupt
MTIOC0A/TMCI3/PO12/
POE2#
SCK6/SCK0
IRQ4
E5
P41
IRQ9-DS
E6
PA2
A2
PO18
RXD5/SMISO5/SSCL5/
SSLA3
E7
PA6
A6
MTIC5V/MTCLKB/
TIOCA2/TMCI3/PO22/
POE2#
CTS5#/RTS5#/SS5#/
MOSIA
E8
PA4
A4
MTIC5U/MTCLKA/
TIOCA1/TMRI0/PO20
TXD5/SMOSI5/SSDA5/
SSLA0
PA5
A5
TIOCB1/PO21
RSPCKA
E10
PA3
A3
MTIOC0D/MTCLKD/
TIOCD0/TCLKB/PO19
RXD5/SMISO5/SSCL5
IRQ6-DS
EXTAL
F2
VCC
P36
F3
P35
F4
P32
MTIOC0C/TIOCC0/
TMO3/PO10/RTCOUT/
RTCIC2
TXD6/TXD0/SMOSI6/
SMOSI0/SSDA6/SSDA0/
CTX0*1
IRQ2-DS
F5
P12
TMCI1
RXD2/SMISO2/SSCL2/
SCL0[FM+]
IRQ2
F6
PB3
A11
MTIOC0A/MTIOC4A/
TIOCD3/TCLKD/TMO0/
PO27/POE3#
SCK6
F7
PB2
A10
TIOCC3/TCLKC/PO26
CTS6#/RTS6#/SS6#
F8
PB0
A8
MTIC5W/TIOCA3/PO24
RXD6/SMISO6/SSCL6/
RSPCKA
PA7
A7
TIOCB2/PO23
MISOA
P33
MTIOC0D/TIOCD0/TMRI3
PO11/POE3#
RXD6/RXD0/SMISO6/
SMISO0/SSCL6/SSCL0/
CRX0*1
IRQ3-DS
F9
F10
AN001
IRQ5-DS
E9
F1
S12AD,
AD, DA
NMI
IRQ12
VSS
G1
G2
TMS
P31
MTIOC4D/TMCI2/PO9/
RTCIC1
CTS1#/RTS1#/SS1#/
SSLB0
IRQ1-DS
G3
TDI
P30
MTIOC4B/TMRI3/PO8/
RTCIC0/POE8#
RXD1/SMISO1/SSCL1/
MISOB
IRQ0-DS
G4
TCK/FINEC
P27
CS7#
MTIOC2B/TMCI3/
PO7
SCK1/RSPCKB
G5
P53*2
BCLK
G6
P52
RD#
G7
PB5
A13
MTIOC2A/MTIOC1B/
TIOCB4/TMRI1/PO29/
POE1#
SCK9
G8
PB4
A12
TIOCA4/PO28
CTS9#/RTS9#/SS9#
G9
PB1
A9
MTIOC0C/MTIOC4C/
TIOCB3/TMCI0/PO25
TXD6/SMOSI6/SSDA6
P26
CS6#
MTIOC2A/TMO1/PO6
TXD1/CTS3#/RTS3#/
SMOSI1/SS3#/SSDA1/
MOSIB
H2
P25
CS5#
MTIOC4C/MTCLKB/
TIOCA4/PO5
RXD3/SMISO3/SSCL3
H3
P16
MTIOC3C/MTIOC3D/
TIOCB1/TCLKC/TMO2/
PO14/RTCOUT
TXD1/RXD3/SMOSI1/
SMISO3/SSDA1/SSCL3/
MOSIA/SCL2-DS/IERXD/
USB0_VBUS
G10
VCC
H1
TDO
R01DS0060EJ0160 Rev.1.60
May 19, 2014
RXD2/SMISO2/SSCL2/
SSLB3
IRQ4-DS
ADTRG0#
IRQ6
ADTRG0#
Page 44 of 154
RX630 Group
Table 1.9
Pin Number
100-Pin
TFLGA
1. Overview
List of Pins and Pin Functions (100-Pin TFLGA) (3/3)
Power Supply
Clock System
Control
I/O Port
Bus
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
MTIOC0B/MTCLKB/
TIOCB2/TCLKB/TMCI2/
PO13
RXD1/SCK3/SMISO1/
SSCL1/CRX1-DS
IRQ5
IRQ10
Interrupt
H4
P15
H5
P55
WAIT#
MTIOC4D/TMO3
CRX1
H6
P54
ALE
MTIOC4B/TMCI1
CTS2#/RTS2#/SS2#/
CTX1
H7
PC7
A23/CS0#
MTIOC3A/MTCLKB/
TMO2/PO31
TXD8/SMOSI8/SSDA8/
MISOA
IRQ14
H8
PC6
A22/CS1#
MTIOC3C/MTCLKA/
TMCI2/PO30
RXD8/SMISO8/SSCL8/
MOSIA
IRQ13
S12AD,
AD, DA
H9
PB6
A14
MTIOC3D/TIOCA5/PO30
RXD9/SMISO9/SSCL9
H10
PB7
A15
MTIOC3B/TIOCB5/PO31
TXD9/SMOSI9/SSDA9
J1
P24
CS4#
MTIOC4A/MTCLKA/
TIOCB4/TMRI1/PO4
SCK3
J2
P21
MTIOC1B/TIOCA3/
TMCI0/PO1
RXD0/SMISO0/SSCL0
IRQ9
J3
P17
MTIOC3A/MTIOC3B/
TIOCB0/TCLKD/TMO1/
PO15/POE8#
SCK1/TXD3/SMOSI3/
SSDA3/MISOA/SDA2-DS/
IETXD
IRQ7
ADTRG#
J4
P13
MTIOC0B/TIOCA5/TMO3/
PO13
TXD2/SMOSI2/SSDA2/
SDA0[FM+]
IRQ3
ADTRG#
J5
VSS_USB
J6
VCC_USB
J7
P50
WR0#/WR#
TXD2/SMOSI2/SSDA2/
SSLB1
J8
PC4
A20/CS3#
MTIOC3D/MTCLKC/
TMCI1/PO25/POE0#
SCK5/CTS8#/RTS8#/
SS8#/SSLA0
J9
PC0
A16
MTIOC3C/TCLKC/PO17
CTS5#/RTS5#/SS5#/
SSLA1
IRQ14
J10
PC1
A17
MTIOC3A/TCLKD/PO18
SCK5/SSLA2
IRQ12
K1
P23
MTIOC3D/MTCLKD/
TIOCD3/PO3
TXD3/CTS0#/RTS0#/
SMOSI3/SS0#/SSDA3
K2
P22
MTIOC3B/MTCLKC/
TIOCC3/TMO0/PO2
SCK0
K3
P20
MTIOC1A/TIOCB3/
TMRI0/PO0
TXD0/SMOSI0/SSDA0
IRQ8
K4
P14
MTIOC3A/MTCLKA/
TIOCB5/TCLKA/TMRI2/
PO15
CTS1#/RTS1#/SS1#/
CTX1/USB0_DPUPE
IRQ4
K5
USB0_DM
K6
USB0_DP
K7
P51
WR1#/BC1#/
WAIT#
SCK2/SSLB2
K8
PC5
A21/CS2#/
WAIT#
MTIOC3B/MTCLKD/
TMRI2/PO29
SCK8/RSPCKA
K9
PC3
A19
MTIOC4D/TCLKB/PO24
TXD5/SMOSI5/SSDA5/
IETXD
K10
PC2
A18
MTIOC4B/TCLKA/PO21
RXD5/SMISO5/SSCL5/
SSLA3/IERXD
Note 1. Enabled only for the ROM capacity of 768 Kbytes or more
Note 2. The BCLK function is multiplexed with the I/O port function for pin P53, so the port function is not available if the external bus is
enabled.
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 45 of 154
RX630 Group
Table 1.10
Pin Number
1. Overview
List of Pins and Pin Functions (100-Pin LQFP) (1/3)
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
MTIOC3C
CTS6#/RTS6#/CTS0#/
RTS0#/SS6#/SS0#
P34
MTIOC0A/TMCI3/PO12/
POE2#
SCK6/SCK0
IRQ4
17
P33
MTIOC0D/TIOCD0/
TMRI3/PO11/POE3#
RXD6/RXD0/SMISO6/
SMISO0/SSCL6/SSCL0/
CRX0*1
IRQ3-DS
18
P32
MTIOC0C/TIOCC0/TMO3/
PO10/RTCOUT/RTCIC2
TXD6/TXD0/SMOSI6/
SMOSI0/SSDA6/SSDA0/
CTX0*1
IRQ2-DS
100-Pin
LQFP
Power Supply
Clock System
Control
1
VREFH
2
EMLE
3
VREFL
4
5
Bus
PJ3
Interrupt
S12AD,
AD, DA
VCL
6
VBATT
7
MD/FINED
8
XCIN
9
XCOUT
10
RES#
11
XTAL
12
VSS
13
EXTAL
14
VCC
15
16
I/O Port
P37
P36
P35
TRST#
NMI
19
TMS
P31
MTIOC4D/TMCI2/PO9/
RTCIC1
CTS1#/RTS1#/SS1#/
SSLB0
IRQ1-DS
20
TDI
P30
MTIOC4B/TMRI3/PO8/
RTCIC0/POE8#
RXD1/SMISO1/SSCL1/
MISOB
IRQ0-DS
21
TCK/FINEC
P27
CS7#
MTIOC2B/TMCI3/PO7
SCK1/RSPCKB
22
TDO
P26
CS6#
MTIOC2A/TMO1/PO6
TXD1/CTS3#/RTS3#/
SMOSI1/SS3#/SSDA1/
MOSIB
23
P25
CS5#
MTIOC4C/MTCLKB/
TIOCA4/PO5
RXD3/SMISO3/SSCL3
24
P24
CS4#
MTIOC4A/MTCLKA/
TIOCB4/TMRI1/PO4
SCK3
25
P23
MTIOC3D/MTCLKD/
TIOCD3/PO3
TXD3/CTS0#/RTS0#/
SMOSI3/SS0#/SSDA3
26
P22
MTIOC3B/MTCLKC/
TIOCC3/TMO0/PO2
SCK0
27
P21
MTIOC1B/TIOCA3/
TMCI0/PO1
RXD0/SMISO0/SSCL0
IRQ9
28
P20
MTIOC1A/TIOCB3/
TMRI0/PO0
TXD0/SMOSI0/SSDA0
IRQ8
29
P17
MTIOC3A/MTIOC3B/
TIOCB0/TCLKD/TMO1/
PO15/POE8#
SCK1/TXD3/SMOSI3/
SSDA3/MISOA/SDA2-DS/
IETXD
IRQ7
ADTRG#
30
P16
MTIOC3C/MTIOC3D/
TIOCB1/TCLKC/TMO2/
PO14/RTCOUT
TXD1/RXD3/SMOSI1/
SMISO3/SSDA1/SSCL3/
MOSIA/SCL2-DS/IERXD/
USB0_VBUS
IRQ6
ADTRG0#
31
P15
MTIOC0B/MTCLKB/
TIOCB2/TCLKB/TMCI2/
PO13
RXD1/SCK3/SMISO1/
SSCL1/CRX1-DS
IRQ5
32
P14
MTIOC3A/MTCLKA/
TIOCB5/TCLKA/TMRI2/
PO15
CTS1#/RTS1#/SS1#/
CTX1/USB0_DPUPE
IRQ4
R01DS0060EJ0160 Rev.1.60
May 19, 2014
ADTRG0#
Page 46 of 154
RX630 Group
Table 1.10
Pin Number
100-Pin
LQFP
1. Overview
List of Pins and Pin Functions (100-Pin LQFP) (2/3)
Power Supply
Clock System
Control
I/O Port
Bus
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
Interrupt
S12AD,
AD, DA
ADTRG#
33
P13
MTIOC0B/TIOCA5/TMO3/
PO13
TXD2/SMOSI2/SSDA2/
SDA0[FM+]
IRQ3
34
P12
TMCI1
RXD2/SMISO2/SSCL2/
SCL0[FM+]
IRQ2
35
VCC_USB
36
USB0_DM
37
38
USB0_DP
VSS_USB
39
P55
WAIT#
MTIOC4D/TMO3
CRX1
40
P54
ALE
MTIOC4B/TMCI1
CTS2#/RTS2#/SS2#/
CTX1
41
BCLK
IRQ10
P53*2
42
P52
RD#
RXD2/SMISO2/SSCL2/
SSLB3
43
P51
WR1#/BC1#/
WAIT#
SCK2/SSLB2
44
P50
WR0#/WR#
TXD2/SMOSI2/SSDA2/
SSLB1
45
PC7
A23/CS0#
MTIOC3A/MTCLKB/
TMO2/PO31
TXD8/SMOSI8/SSDA8/
MISOA
IRQ14
46
PC6
A22/CS1#
MTIOC3C/MTCLKA/
TMCI2/PO30
RXD8/SMISO8/SSCL8/
MOSIA
IRQ13
47
PC5
A21/CS2#/
WAIT#
MTIOC3B/MTCLKD/
TMRI2/PO29
SCK8/RSPCKA
48
PC4
A20/CS3#
MTIOC3D/MTCLKC/
TMCI1/PO25/POE0#
SCK5/CTS8#/RTS8#/
SS8#/SSLA0
49
PC3
A19
MTIOC4D/TCLKB/PO24
TXD5/SMOSI5/SSDA5/
IETXD
50
PC2
A18
MTIOC4B/TCLKA/PO21
RXD5/SMISO5/SSCL5/
SSLA3/IERXD
51
PC1
A17
MTIOC3A/TCLKD/PO18
SCK5/SSLA2
IRQ12
52
PC0
A16
MTIOC3C/TCLKC/PO17
CTS5#/RTS5#/SS5#/
SSLA1
IRQ14
53
PB7
A15
MTIOC3B/TIOCB5/PO31
TXD9/SMOSI9/SSDA9
54
PB6
A14
MTIOC3D/TIOCA5/PO30
RXD9/SMISO9/SSCL9
55
PB5
A13
MTIOC2A/MTIOC1B/
TIOCB4/TMRI1/PO29/
POE1#
SCK9
56
PB4
A12
TIOCA4/PO28
CTS9#/RTS9#/SS9#
57
PB3
A11
MTIOC0A/MTIOC4A/
TIOCD3/TCLKD/TMO0/
PO27/POE3#
SCK6
58
PB2
A10
TIOCC3/TCLKC/PO26
CTS6#/RTS6#/SS6#
59
PB1
A9
MTIOC0C/MTIOC4C/
TIOCB3/TMCI0/PO25
TXD6/SMOSI6/SSDA6
IRQ4-DS
PB0
A8
MTIC5W/TIOCA3/PO24
RXD6/SMISO6/SSCL6/
RSPCKA
IRQ12
60
VCC
61
62
VSS
63
PA7
A7
TIOCB2/PO23
MISOA
64
PA6
A6
MTIC5V/MTCLKB/
TIOCA2/TMCI3/PO22/
POE2#
CTS5#/RTS5#/SS5#/
MOSIA
65
PA5
A5
TIOCB1/PO21
RSPCKA
66
PA4
A4
MTIC5U/MTCLKA/
TIOCA1/TMRI0/PO20
TXD5/SMOSI5/SSDA5/
SSLA0
R01DS0060EJ0160 Rev.1.60
May 19, 2014
IRQ5-DS
Page 47 of 154
RX630 Group
Table 1.10
Pin Number
100-Pin
LQFP
1. Overview
List of Pins and Pin Functions (100-Pin LQFP) (3/3)
Power Supply
Clock System
Control
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
Interrupt
IRQ6-DS
S12AD,
AD, DA
I/O Port
Bus
67
PA3
A3
MTIOC0D/MTCLKD/
TIOCD0/TCLKB/PO19
RXD5/SMISO5/SSCL5
68
PA2
A2
PO18
RXD5/SMISO5/SSCL5/
SSLA3
69
PA1
A1
MTIOC0B/MTCLKC/
TIOCB0/PO17
SCK5/SSLA2
70
PA0
A0/BC0#
MTIOC4A/TIOCA0/PO16
SSLA1
71
PE7
D15[A15/D15]
MISOB
IRQ7
AN5
72
PE6
D14[A14/D14]
MOSIB
IRQ6
AN4
73
PE5
D13[A13/D13]
MTIOC4C/MTIOC2B
RSPCKB
IRQ5
AN3
74
PE4
D12[A12/D12]
MTIOC4D/MTIOC1A/
PO28
SSLB0
AN2
75
PE3
D11[A11/D11]
MTIOC4B/PO26/POE8#
CTS12#/RTS12#/SS12#/
MISOB
AN1
76
PE2
D10[A10/D10]
MTIOC4A/PO23
RXD12/SMISO12/
SSCL12/RXDX12/SSLB3/
MOSIB
77
PE1
D9[A9/D9]
MTIOC4C/PO18
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/SSLB2/RSPCKB
ANEX1
78
PE0
D8[A8/D8]
SCK12/SSLB1
ANEX0
79
PD7
D7[A7/D7]
MTIC5U/POE0#
IRQ7
AN7
80
PD6
D6[A6/D6]
MTIC5V/POE1#
IRQ6
AN6
81
PD5
D5[A5/D5]
MTIC5W/POE2#
IRQ5
AN013
82
PD4
D4[A4/D4]
POE3#
IRQ4
AN012
83
PD3
D3[A3/D3]
POE8#
IRQ11
IRQ7-DS
AN0
IRQ3
AN011
IRQ2
AN010
IRQ1
AN009
84
PD2
D2[A2/D2]
MTIOC4D
CRX0*1
85
PD1
D1[A1/D1]
MTIOC4B
CTX0*1
86
PD0
D0[A0/D0]
IRQ0
AN008
87
P47
IRQ15-DS
AN007
88
P46
IRQ14-DS
AN006
89
P45
IRQ13-DS
AN005
90
P44
IRQ12-DS
AN004
91
P43
IRQ11-DS
AN003
92
P42
IRQ10-DS
AN002
93
P41
IRQ9-DS
AN001
P40
IRQ8-DS
AN000
P07
IRQ15
ADTRG0#
P05
IRQ13
DA1
94
VREFL0
95
96
VREFH0
97
AVCC0
98
99
100
AVSS0
Note 1. Enabled only for the ROM capacity of 768 Kbytes or more
Note 2. The BCLK function is multiplexed with the I/O port function for pin P53, so the port function is not available if the external bus is
enabled.
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 48 of 154
RX630 Group
Table 1.11
Pin Number
1. Overview
List of Pins and Pin Functions (80-Pin LQFP) (1/3)
100-Pin
LQFP
Power Supply
Clock System
Control
1
VREFH
2
EMLE
3
VREFL
4
VCL
5
VBATT
6
MD/FINED
7
XCIN
8
XCOUT
9
RES#
10
XTAL
11
VSS
12
EXTAL
13
VCC
14
15
I/O Port
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
16
S12AD,
AD, DA
P37
P36
P35
TRST#
Interrupt
NMI
P34
MTIOC0A/TMCI3/PO12/
POE2#
SCK6
IRQ4
P32
MTIOC0C/TIOCC0/TMO3/
PO10/RTCOUT/RTCIC2
TXD6/SMOSI6/SSDA6
IRQ2-DS
17
TMS
P31
MTIOC4D/TMCI2/PO9/
RTCIC1
CTS1#/RTS1#/SS1#/
SSLB0
IRQ1-DS
18
TDI
P30
MTIOC4B/TMRI3/PO8/
RTCIC0/POE8#
RXD1/SMISO1/SSCL1/
MISOB
IRQ0-DS
19
TCK/FINEC
P27
MTIOC2B/TMCI3/PO7
SCK1/RSPCKB
20
TDO
P26
MTIOC2A/TMO1/PO6
TXD1/SMOSI1/SSDA1/
MOSIB
21
P21
MTIOC1B/TIOCA3/TMCI0/
PO1
IRQ9
22
P20
MTIOC1A/TIOCB3/TMRI0/
PO0
IRQ8
23
P17
MTIOC3A/MTIOC3B/
TIOCB0/TCLKD/TMO1/
PO15/POE8#
SCK1/MISOA/SDA2-DS/
IETXD
IRQ7
ADTRG#
24
P16
MTIOC3C/MTIOC3D/
TIOCB1/TCLKC/TMO2/
PO14/RTCOUT
TXD1/SMOSI1/SSDA1/
MOSIA/SCL2-DS/IERXD/
USB0_VBUS
IRQ6
ADTRG0#
25
P15
MTIOC0B/MTCLKB/
TIOCB2/TCLKB/TMCI2/
PO13
RXD1/SMISO1/SSCL1/
CRX1-DS
IRQ5
26
P14
MTIOC3A/MTCLKA/
TIOCB5/TCLKA/TMRI2/
PO15
CTS1#/RTS1#/SS1#/
CTX1/USB0_DPUPE
IRQ4
27
P13
MTIOC0B/TIOCA5/TMO3/
PO13
SDA0[FM+]
IRQ3
P12
TMCI1
SCL0[FM+]
IRQ2
28
29
VCC_USB
30
USB0_DM
31
32
ADTRG#
USB0_DP
VSS_USB
33
P55
MTIOC4D/TMO3
CRX1
34
P54
MTIOC4B/TMCI1
CTX1
35
PC7
MTIOC3A/MTCLKB/TMO2/
PO31
TXD8/SMOSI8/SSDA8/
MISOA
IRQ14
36
PC6
MTIOC3C/MTCLKA/
TMCI2/PO30
RXD8/SMISO8/SSCL8/
MOSIA
IRQ13
R01DS0060EJ0160 Rev.1.60
May 19, 2014
IRQ10
Page 49 of 154
RX630 Group
Table 1.11
Pin Number
100-Pin
LQFP
1. Overview
List of Pins and Pin Functions (80-Pin LQFP) (2/3)
Power Supply
Clock System
Control
I/O Port
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
Interrupt
37
PC5
MTIOC3B/MTCLKD/
TMRI2/PO29
SCK8/RSPCKA
38
PC4
MTIOC3D/MTCLKC/
TMCI1/PO25/POE0#
SCK5/CTS8#/RTS8#/
SS8#/SSLA0
39
PC3
MTIOC4D/TCLKB/PO24
TXD5/SMOSI5/SSDA5/
IETXD
40
PC2
MTIOC4B/TCLKA/PO21
RXD5/SMISO5/SSCL5/
SSLA3/IERXD
41
PB7
MTIOC3B/TIOCB5/PO31
TXD9/SMOSI9/SSDA9
42
PB6
MTIOC3D/TIOCA5/PO30
RXD9/SMISO9/SSCL9
43
PB5
MTIOC2A/MTIOC1B/
TIOCB4/TMRI1/PO29/
POE1#
SCK9
44
PB4
TIOCA4/PO28
CTS9#/RTS9#/SS9#
45
PB3
MTIOC0A/MTIOC4A/
TIOCD3/TCLKD/TMO0/
PO27/POE3#
SCK6
46
PB2
TIOCC3/TCLKC/PO26
CTS6#/RTS6#/SS6#
47
PB1
MTIOC0C/MTIOC4C/
TIOCB3/TMCI0/PO25
TXD6/SMOSI6/SSDA6
IRQ4-DS
PB0
MTIC5W/TIOCA3/PO24
RXD6/SMISO6/SSCL6/
RSPCKA
IRQ12
PA6
MTIC5V/MTCLKB/TIOCA2/
TMCI3/PO22/POE2#
CTS5#/RTS5#/SS5#/
MOSIA
48
VCC
49
50
51
S12AD,
AD, DA
VSS
52
PA5
TIOCB1/PO21
RSPCKA
53
PA4
MTIC5U/MTCLKA/TIOCA1/
TMRI0/PO20
TXD5/SMOSI5/SSDA5/
SSLA0
IRQ5-DS
54
PA3
MTIOC0D/MTCLKD/
TIOCD0/TCLKB/PO19
RXD5/SMISO5/SSCL5
IRQ6-DS
55
PA2
PO18
RXD5/SMISO5/SSCL5/
SSLA3
56
PA1
MTIOC0B/MTCLKC/
TIOCB0/PO17
SCK5/SSLA2
57
PA0
MTIOC4A/TIOCA0/PO16
SSLA1
58
PE5
MTIOC4C/MTIOC2B
RSPCKB
59
PE4
MTIOC4D/MTIOC1A/PO28
SSLB0
AN2
60
PE3
MTIOC4B/PO26/POE8#
CTS12#/RTS12#/SS12#/
MISOB
AN1
61
PE2
MTIOC4A/PO23
RXD12/SMISO12/SSCL12/
RXDX12/SSLB3/MOSIB
62
PE1
MTIOC4C/PO18
TXD12/SMOSI12/SSDA12/
TXDX12/SIOX12/SSLB2/
RSPCKB
ANEX1
63
PE0
SCK12/SSLB1
ANEX0
64
PD2
MTIOC4D
IRQ2
AN010
65
PD1
MTIOC4B
IRQ1
AN009
IRQ11
IRQ5
IRQ7-DS
AN3
AN0
66
PD0
IRQ0
AN008
67
P47
IRQ15-DS
AN007
68
P46
IRQ14-DS
AN006
69
P45
IRQ13-DS
AN005
70
P44
IRQ12-DS
AN004
71
P43
IRQ11-DS
AN003
72
P42
IRQ10-DS
AN002
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 50 of 154
RX630 Group
Table 1.11
Pin Number
100-Pin
LQFP
1. Overview
List of Pins and Pin Functions (80-Pin LQFP) (3/3)
Power Supply
Clock System
Control
73
74
76
VREFH0
77
AVCC0
78
80
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(SCIc, SCId, RSPI, RIIC,
CAN, IEB, USB)
Interrupt
S12AD,
AD, DA
P41
IRQ9-DS
AN001
P40
IRQ8-DS
AN000
P07
IRQ15
ADTRG0#
P05
IRQ13
DA1
I/O Port
VREFL0
75
79
Timer
AVSS0
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 51 of 154
RX630 Group
2.
2. CPU
CPU
The RX CPU has sixteen general-purpose registers, nine control registers, and one accumulator used for DSP
instructions.
General-purpose register
b31
b0
R0
(SP)*1
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
Control register
b31
b0
ISP
(Interrupt stack pointer)
USP
(User stack pointer)
INTB
(Interrupt table register)
PC
(Program counter)
PSW
(Processor status word)
BPC
(Backup PC)
BPSW
(Backup PSW)
FINTV
(Fast interrupt vector register)
FPSW
(Floating-point status word)
DSP instruction register
b63
b0
ACC (Accumulator)
Note 1. The stack pointer (SP) can be the interrupt stack pointer (ISP) or user stack pointer (USP), according
to the value of the U bit in the PSW.
Figure 2.1
Register Set of the CPU
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 52 of 154
RX630 Group
2.1
2. CPU
General-Purpose Registers (R0 to R15)
This CPU has sixteen general-purpose registers (R0 to R15). R1 to R15 can be used as data registers or address registers.
R0, a general-purpose register, also functions as the stack pointer (SP).
The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the
stack pointer select bit (U) in the processor status word (PSW).
2.2
(1)
Control Registers
Interrupt Stack Pointer (ISP)/User Stack Pointer (USP)
The stack pointer (SP) can be either of two types, the interrupt stack pointer (ISP) or the user stack pointer (USP).
Whether the stack pointer operates as the ISP or USP depends on the value of the stack pointer select bit (U) in the
processor status word (PSW).
Set the ISP or USP to a multiple of four, as this reduces the numbers of cycles required to execute interrupt sequences
and instructions entailing stack manipulation.
(2)
Interrupt Table Register (INTB)
The interrupt table register (INTB) specifies the address where the relocatable vector table starts.
(3)
Program Counter (PC)
The program counter (PC) indicates the address of the instruction being executed.
(4)
Processor Status Word (PSW)
The processor status word (PSW) indicates the results of instruction execution or the state of the CPU.
(5)
Backup PC (BPC)
The backup PC (BPC) is provided to speed up response to interrupts.
After a fast interrupt has been generated, the contents of the program counter (PC) are saved in the BPC register.
(6)
Backup PSW (BPSW)
The backup PSW (BPSW) is provided to speed up response to interrupts.
After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in the BPSW. The
allocation of bits in the BPSW corresponds to that in the PSW.
(7)
Fast Interrupt Vector Register (FINTV)
The fast interrupt vector register (FINTV) is provided to speed up response to interrupts.
The FINTV register specifies a branch destination address when a fast interrupt has been generated.
(8)
Floating-Point Status Word (FPSW)
The floating-point status word (FPSW) indicates the results of floating-point operations.
When an exception handling enable bit (Ej) enables the exception handling (Ej = 1), the exception cause can be identified
by checking the corresponding Cj flag in the exception handling routine. If the exception handling is masked (Ej = 0), the
occurrence of exception can be checked by reading the Fj flag at the end of a series of processing. Once the Fj flag has
been set to 1, this value is retained until it is cleared to 0 by software (j = X, U, Z, O, or V).
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2.3
(1)
2. CPU
Register Associated with DSP Instructions
Accumulator (ACC)
The accumulator (ACC) is a 64-bit register used for DSP instructions. The accumulator is also used for the multiply and
multiply-and-accumulate instructions; EMUL, EMULU, FMUL, MUL, and RMPA, in which case the prior value in the
accumulator is modified by execution of the instruction.
Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The MVTACHI and MVTACLO
instructions write data to the higher-order 32 bits (bits 63 to 32) and the lower-order 32 bits (bits 31 to 0), respectively.
Use the MVFACHI and MVFACMI instructions for reading data from the accumulator. The MVFACHI and MVFACMI
instructions read data from the higher-order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively.
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3.
Address Space
3.1
Address Space
3. Address Space
This LSI has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is,
linear access to an address space of up to 4 Gbytes is possible, and this contains both program and data areas.
Figure 3.1 shows the memory maps in the respective operating modes. Accessible areas will differ according to the
operating mode and states of control bits.
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RX630 Group
3. Address Space
On-chip ROM enabled
extended mode
Single-chip mode*1
On-chip ROM disabled
extended mode
0000 0000h
RAM*2
0000 0000h
RAM*2
0000 0000h
RAM*2
0002 0000h
Reserved area*3
0002 0000h
Reserved area*3
0002 0000h
Reserved area*3
0008 0000h
0008 0000h
0008 0000h
Peripheral I/O registers
0010 0000h
On-chip ROM (E2 data flash)
0010 8000h
007F 8000h
007F A000h
0010 0000h
Reserved area*3
0010 8000h
FCU-RAM*4
007F 8000h
007F A000h
On-chip ROM (E2 data flash)
Peripheral I/O registers
FCU-RAM*4
Reserved area*3
007F C000h
007F C500h
Peripheral I/O registers
Reserved area*3
007F FC00h
0080 0000h
00E0 0000h
007F FC00h
Peripheral I/O registers
Reserved area*3
0080 0000h
Reserved area*3
00E0 0000h
On-chip ROM (program ROM)
(write only)
0100 0000h
0100 0000h
Reserved area*3
Reserved area*3
Peripheral I/O registers
On-chip ROM (program ROM)
(write only)
0010 0000h
Reserved area*3
Reserved area*3
007F C000h
007F C500h
Peripheral I/O registers
Peripheral I/O registers
0100 0000h
External address space
External address space
Reserved area*3
0800 0000h
0800 0000h
Reserved area*3
Reserved area*3
FEFF E000h
On-chip ROM (FCU firmware)
(read only)*4
FF00 0000h
FF7F C000h
Reserved area*3
On-chip ROM (user boot)
(read only)
FF80 0000h
Reserved area*3
FFE0 0000h
FEFF E000h
On-chip ROM (FCU firmware)
(read only)*4
FF00 0000h
FF7F C000h
Reserved area*3
FF00 0000h
On-chip ROM (user boot)
(read only)
FF80 0000h
External address space
Reserved area*3
FFE0 0000h
On-chip ROM (program ROM)
(read only)*2
FFFF FFFFh
On-chip ROM (program ROM)
(read only)*2
FFFF FFFFh
FFFF FFFFh
Note 1. The address space in boot mode and user boot mode/USB boot mode is the same as the address space in single-chip mode.
Note 2. The capacity of ROM/RAM differs depending on the products.
ROM (bytes)
Capacity
RAM (bytes)
Address
Capacity
Address
2M
FFE0 0000h to FFFF FFFFh
128 K
0000 0000h to 0001 FFFFh
1.5 M
FFE8 0000h to FFFF FFFFh
96 K
0000 0000h to 0001 7FFFh
64 K
0000 0000h to 0000 FFFFh
1M
FFF0 0000h to FFFF FFFFh
768 K
FFF4 0000h to FFFF FFFFh
512 K
FFF8 0000h to FFFF FFFFh
384 K
FFFA 0000h to FFFF FFFFh
Note:See Table 1.3, List of Products, for the product type name.
Note 3. Reserved areas should not be accessed.
Note 4. For details on the FCU, see section 43, Flash Memory in the User’s manual: Hardware.
Figure 3.1
Memory Map in Each Operating Mode
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RX630 Group
3.2
3. Address Space
External Address Space
The external address space is divided into up to eight CS areas (CS0 to CS7), each corresponding to the CSn# signal
output from a CSn# (n = 0 to 7) pin.
Figure 3.2 shows the address ranges corresponding to the individual CS areas (CS0 to CS7) in on-chip ROM disabled
extended mode.
0000 0000h
RAM
0002 0000h
Reserved area*1
0008 0000h
Peripheral I/O registers
0010 0000h
0100 0000h
CS7 (16 Mbytes)
Reserved area*1
01FF FFFFh
0200 0000h
CS6 (16 Mbytes)
02FF FFFFh
0300 0000h
CS5 (16 Mbytes)
0100 0000h
03FF FFFFh
0400 0000h
External address space
(CS area)
CS4 (16 Mbytes)
04FF FFFFh
0500 0000h
0800 0000h
CS3 (16 Mbytes)
05FF FFFFh
0600 0000h
CS2 (16 Mbytes)
Reserved area*1
06FF FFFFh
0700 0000h
CS1 (16 Mbytes)
07FF FFFFh
FF00 0000h
FF00 0000h
External address space*2
CS0 (16 Mbytes)
FFFF FFFFh
FFFF FFFFh
Note 1.
Reserved areas should not be accessed.
Note 2.
The CS0 area is disabled in on-chip ROM enabled extended mode.
In this mode, the address space for addresses above 0800 0000h is as shown in figure on
this section, Memory Map in Each Operating Mode.
Figure 3.2
Correspondence between External Address Spaces and CS Areas
(In On-Chip ROM Disabled Extended Mode)
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RX630 Group
4.
4. I/O Registers
I/O Registers
This section gives information on the on-chip I/O register addresses. The information is given as shown below. Notes on
writing to registers are also given at the end.
(1)
I/O register addresses (address order)
Registers are listed from the lower allocation addresses.
Registers are classified according to module symbols.
The number of access cycles indicates the number of cycles based on the specified reference clock.
Among the internal I/O register area, addresses not listed in the list of registers are reserved. Reserved addresses
must not be accessed. Do not access these addresses; otherwise, the operation when accessing these bits and
subsequent operations cannot be guaranteed.
(2)
Notes on writing to I/O registers
When writing to an I/O register, the CPU starts executing the subsequent instruction before completing I/O register write.
This may cause the subsequent instruction to be executed before the post-update I/O register value is reflected on the
operation.
As described in the following examples, special care is required for the cases in which the subsequent instruction must be
executed after the post-update I/O register value is actually reflected.
[Examples of cases requiring special care]
The subsequent instruction must be executed while an interrupt request is disabled with the IENj bit in IERn of the
ICU (interrupt request enable bit) cleared to 0.
A WAIT instruction is executed immediately after the preprocessing for causing a transition to the low power
consumption state.
In the above cases, after writing to an I/O register, wait until the write operation is completed using the following
procedure and then execute the subsequent instruction.
(a) Write to an I/O register.
(b) Read the value from the I/O register to a general register.
(c) Execute the operation using the value read.
(d) Execute the subsequent instruction.
[Instruction examples]
Byte-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.B #SFR_DATA, [R1]
CMP [R1].UB, R1
;; Next process
Word-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.W #SFR_DATA, [R1]
CMP [R1].W, R1
;; Next process
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4. I/O Registers
Longword-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.L #SFR_DATA, [R1]
CMP [R1].L, R1
;; Next process
If multiple registers are written to and a subsequent instruction should be executed after the write operations are entirely
completed, only read the I/O register that was last written to and execute the operation using the value; it is not necessary
to read or execute operation for all the registers that were written to.
(3)
Number of Access Cycles to I/O Registers
For the number of I/O register access cycles, refer to Table 4.1, List of I/O Registers (Address Order).
The number of access cycles to I/O registers is obtained by following equation.*1
Number of access cycles to I/O registers = Number of bus cycles for internal main bus 1 +
Number of divided clock synchronization cycles +
Number of bus cycles for internal peripheral busses 1 to 6
The number of bus cycles of internal peripheral bus 1 to 6 differs according to the register to be accessed.
When peripheral functions connected to internal peripheral bus 2 to 6 or registers for the external bus control unit (except
for bus error related registers) are accessed, the number of divided clock synchronization cycles is added.
The number of divided clock synchronization cycles differs depending on the frequency ratio between ICLK and PCLK
(or FCLK, BCLK) or bus access timing.
In the peripheral function unit, when the frequency ratio of ICLK is equal to or greater than that of PCLK (or FCLK), the
sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will
be one cycle of PCLK (or FCLK) at a maximum. Therefore, one PCLK (or FCLK) has been added to the number of
access states shown in Table 4.1.
When the frequency ratio of ICLK is lower than that of PCLK (or FCLK), the subsequent bus access is started from the
ICLK cycle following the completion of the access to the peripheral functions. Therefore, the access cycles are described
on an ICLK basis.
In the external bus control unit, the sum of the number of bus cycles for internal main bus 1 and the number of divided
clock synchronization cycles will be one cycle of BCLK at a maximum. Therefore, one BCLK is added to the number of
access cycles shown in Table 4.1.
Note 1. This applies to the number of cycles when the access from the CPU does not conflict with the instruction fetching
to the external memory or bus access from the different bus master (DMAC or DTC).
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4.1
Table 4.1
Address
4. I/O Registers
I/O Register Addresses (Address Order)
List of I/O Registers (Address Order) (1/42)
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
Number of Access States
ICLK PCLK
ICLK PCLK
0008 0000h
SYSTEM
Mode monitor register
MDMONR
16
16
3 ICLK
0008 0002h
SYSTEM
Mode status register
MDSR
16
16
3 ICLK
0008 0006h
SYSTEM
System control register 0
SYSCR0
16
16
3 ICLK
0008 0008h
SYSTEM
System control register 1
SYSCR1
16
16
3 ICLK
0008 000Ch
SYSTEM
Standby control register
SBYCR
16
16
3 ICLK
0008 0010h
SYSTEM
Module stop control register A
MSTPCRA
32
32
3 ICLK
0008 0014h
SYSTEM
Module stop control register B
MSTPCRB
32
32
3 ICLK
0008 0018h
SYSTEM
Module stop control register C
MSTPCRC
32
32
3 ICLK
0008 0020h
SYSTEM
System clock control register
SCKCR
32
32
3 ICLK
0008 0024h
SYSTEM
System clock control register 2
SCKCR2
16
16
3 ICLK
0008 0026h
SYSTEM
System clock control register 3
SCKCR3
16
16
3 ICLK
0008 0028h
SYSTEM
PLL control register
PLLCR
16
16
3 ICLK
0008 002Ah
SYSTEM
PLL control register 2
PLLCR2
8
8
3 ICLK
0008 0030h
SYSTEM
External bus clock control register
BCKCR
8
8
3 ICLK
0008 0032h
SYSTEM
Main clock oscillator control register
MOSCCR
8
8
3 ICLK
0008 0033h
SYSTEM
Sub-clock oscillator control register
SOSCCR
8
8
3 ICLK
0008 0034h
SYSTEM
Low-speed on-chip oscillator control register
LOCOCR
8
8
3 ICLK
0008 0035h
SYSTEM
IWDT-dedicated on-chip oscillator control
register
ILOCOCR
8
8
3 ICLK
0008 0036h
SYSTEM
High-speed on-chip oscillator control register
HOCOCR
8
8
3 ICLK
0008 0040h
SYSTEM
Oscillation stop detection control register
OSTDCR
8
8
3 ICLK
0008 0041h
SYSTEM
Oscillation stop detection status register
OSTDSR
8
8
3 ICLK
0008 00A0h
SYSTEM
Operating power control register
OPCCR
8
8
3 ICLK
0008 00A1h
SYSTEM
Sleep mode return clock source switching
register
RSTCKCR
8
8
3 ICLK
0008 00A2h
SYSTEM
Main clock oscillator wait control register
MOSCWTCR
8
8
3 ICLK
0008 00A3h
SYSTEM
Sub-clock oscillator wait control register
SOSCWTCR
8
8
3 ICLK
0008 00A6h
SYSTEM
PLL wait control register
PLLWTCR
8
8
3 ICLK
0008 00C0h
SYSTEM
Reset status register 2
RSTSR2
8
8
3 ICLK
0008 00C2h
SYSTEM
Software reset register
SWRR
16
16
3 ICLK
0008 00E0h
SYSTEM
Voltage monitoring 1 circuit control register 1
LVD1CR1
8
8
3 ICLK
Related
Function
Operating
Modes
Low Power
Consumption
Clock
Generation
Circuit
Low Power
Consumption
Resets
LVDA
0008 00E1h
SYSTEM
Voltage monitoring 1 circuit status register
LVD1SR
8
8
3 ICLK
0008 00E2h
SYSTEM
Voltage monitoring 2 circuit control register 1
LVD2CR1
8
8
3 ICLK
0008 00E3h
SYSTEM
Voltage monitoring 2 circuit status register
LVD2SR
8
8
3 ICLK
0008 03FEh
SYSTEM
Protect register
PRCR
16
16
3 ICLK
Register Write
Protection
Function
Buses
0008 1300h
BSC
Bus error status clear register
BERCLR
8
8
2 ICLK
0008 1304h
BSC
Bus error monitoring enable register
BEREN
8
8
2 ICLK
0008 1308h
BSC
Bus error status register 1
BERSR1
8
8
2 ICLK
0008 130Ah
BSC
Bus error status register 2
BERSR2
16
16
2 ICLK
0008 1310h
BSC
Bus priority control register
BUSPRI
16
16
2 ICLK
0008 2000h
DMAC0
DMA source address register
DMSAR
32
32
2 ICLK
0008 2004h
DMAC0
DMA destination address register
DMDAR
32
32
2 ICLK
0008 2008h
DMAC0
DMA transfer count register
DMCRA
32
32
2 ICLK
0008 200Ch
DMAC0
DMA block transfer count register
DMCRB
16
16
2 ICLK
0008 2010h
DMAC0
DMA transfer mode register
DMTMD
16
16
2 ICLK
0008 2013h
DMAC0
DMA interrupt setting register
DMINT
8
8
2 ICLK
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DMACA
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Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (2/42)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
0008 2014h
DMAC0
DMA address mode register
DMAMD
16
16
2 ICLK
0008 2018h
DMAC0
DMA offset register
DMOFR
32
32
2 ICLK
ICLK PCLK
ICLK PCLK
0008 201Ch
DMAC0
DMA transfer enable register
DMCNT
8
8
2 ICLK
0008 201Dh
DMAC0
DMA software start register
DMREQ
8
8
2 ICLK
0008 201Eh
DMAC0
DMA status register
DMSTS
8
8
2 ICLK
0008 201Fh
DMAC0
DMA activation source flag control register
DMCSL
8
8
2 ICLK
0008 2040h
DMAC1
DMA source address register
DMSAR
32
32
2 ICLK
2 ICLK
0008 2044h
DMAC1
DMA destination address register
DMDAR
32
32
0008 2048h
DMAC1
DMA transfer count register
DMCRA
32
32
2 ICLK
0008 204Ch
DMAC1
DMA block transfer count register
DMCRB
16
16
2 ICLK
0008 2050h
DMAC1
DMA transfer mode register
DMTMD
16
16
2 ICLK
2 ICLK
0008 2053h
DMAC1
DMA interrupt setting register
DMINT
8
8
0008 2054h
DMAC1
DMA address mode register
DMAMD
16
16
2 ICLK
0008 205Ch
DMAC1
DMA transfer enable register
DMCNT
8
8
2 ICLK
0008 205Dh
DMAC1
DMA software start register
DMREQ
8
8
2 ICLK
0008 205Eh
DMAC1
DMA status register
DMSTS
8
8
2 ICLK
0008 205Fh
DMAC1
DMA activation source flag control register
DMCSL
8
8
2 ICLK
0008 2080h
DMAC2
DMA source address register
DMSAR
32
32
2 ICLK
2 ICLK
0008 2084h
DMAC2
DMA destination address register
DMDAR
32
32
0008 2088h
DMAC2
DMA transfer count register
DMCRA
32
32
2 ICLK
0008 208Ch
DMAC2
DMA block transfer count register
DMCRB
16
16
2 ICLK
0008 2090h
DMAC2
DMA transfer mode register
DMTMD
16
16
2 ICLK
2 ICLK
0008 2093h
DMAC2
DMA interrupt setting register
DMINT
8
8
0008 2094h
DMAC2
DMA address mode register
DMAMD
16
16
2 ICLK
0008 209Ch
DMAC2
DMA transfer enable register
DMCNT
8
8
2 ICLK
0008 209Dh
DMAC2
DMA software start register
DMREQ
8
8
2 ICLK
0008 209Eh
DMAC2
DMA status register
DMSTS
8
8
2 ICLK
0008 209Fh
DMAC2
DMA activation source flag control register
DMCSL
8
8
2 ICLK
0008 20C0h
DMAC3
DMA source address register
DMSAR
32
32
2 ICLK
2 ICLK
0008 20C4h
DMAC3
DMA destination address register
DMDAR
32
32
0008 20C8h
DMAC3
DMA transfer count register
DMCRA
32
32
2 ICLK
0008 20CCh
DMAC3
DMA block transfer count register
DMCRB
16
16
2 ICLK
0008 20D0h
DMAC3
DMA transfer mode register
DMTMD
16
16
2 ICLK
2 ICLK
0008 20D3h
DMAC3
DMA interrupt setting register
DMINT
8
8
0008 20D4h
DMAC3
DMA address mode register
DMAMD
16
16
2 ICLK
0008 20DCh
DMAC3
DMA transfer enable register
DMCNT
8
8
2 ICLK
0008 20DDh
DMAC3
DMA software start register
DMREQ
8
8
2 ICLK
0008 20DEh
DMAC3
DMA status register
DMSTS
8
8
2 ICLK
0008 20DFh
DMAC3
DMA activation source flag control register
DMCSL
8
8
2 ICLK
0008 2200h
DMAC
DMA module activation register
DMAST
8
8
2 ICLK
0008 2400h
DTC
DTC control register
DTCCR
8
8
2 ICLK
0008 2404h
DTC
DTC vector base register
DTCVBR
32
32
2 ICLK
0008 2408h
DTC
DTC address mode register
DTCADMOD
8
8
2 ICLK
0008 240Ch
DTC
DTC module start register
DTCST
8
8
2 ICLK
0008 240Eh
DTC
DTC status register
DTCSTS
16
16
2 ICLK
0008 3002h
BSC
CS0 mode register
CS0MOD
16
16
1, 2 BCLK
0008 3004h
BSC
CS0 wait control register 1
CS0WCR1
32
32
1, 2 BCLK
0008 3008h
BSC
CS0 wait control register 2
CS0WCR2
32
32
1, 2 BCLK
0008 3012h
BSC
CS1 mode register
CS1MOD
16
16
1, 2 BCLK
0008 3014h
BSC
CS1 wait control register 1
CS1WCR1
32
32
1, 2 BCLK
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Related
Function
DMACA
DTCa
Buses
Page 61 of 154
RX630 Group
Table 4.1
Address
4. I/O Registers
List of I/O Registers (Address Order) (3/42)
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
Number of Access States
ICLK PCLK
ICLK PCLK
0008 3018h
BSC
CS1 wait control register 2
CS1WCR2
32
32
1, 2 BCLK
0008 3022h
BSC
CS2 mode register
CS2MOD
16
16
1, 2 BCLK
0008 3024h
BSC
CS2 wait control register 1
CS2WCR1
32
32
1, 2 BCLK
0008 3028h
BSC
CS2 wait control register 2
CS2WCR2
32
32
1, 2 BCLK
0008 3032h
BSC
CS3 mode register
CS3MOD
16
16
1, 2 BCLK
0008 3034h
BSC
CS3 wait control register 1
CS3WCR1
32
32
1, 2 BCLK
0008 3038h
BSC
CS3 wait control register 2
CS3WCR2
32
32
1, 2 BCLK
0008 3042h
BSC
CS4 mode register
CS4MOD
16
16
1, 2 BCLK
0008 3044h
BSC
CS4 wait control register 1
CS4WCR1
32
32
1, 2 BCLK
0008 3048h
BSC
CS4 wait control register 2
CS4WCR2
32
32
1, 2 BCLK
0008 3052h
BSC
CS5 mode register
CS5MOD
16
16
1, 2 BCLK
0008 3054h
BSC
CS5 wait control register 1
CS5WCR1
32
32
1, 2 BCLK
0008 3058h
BSC
CS5 wait control register 2
CS5WCR2
32
32
1, 2 BCLK
0008 3062h
BSC
CS6 mode register
CS6MOD
16
16
1, 2 BCLK
0008 3064h
BSC
CS6 wait control register 1
CS6WCR1
32
32
1, 2 BCLK
0008 3068h
BSC
CS6 wait control register 2
CS6WCR2
32
32
1, 2 BCLK
0008 3072h
BSC
CS7 mode register
CS7MOD
16
16
1, 2 BCLK
0008 3074h
BSC
CS7 wait control register 1
CS7WCR1
32
32
1, 2 BCLK
0008 3078h
BSC
CS7 wait control register 2
CS7WCR2
32
32
1, 2 BCLK
0008 3802h
BSC
CS0 control register
CS0CR
16
16
1, 2 BCLK
0008 380Ah
BSC
CS0 recovery cycle register
CS0REC
16
16
1, 2 BCLK
0008 3812h
BSC
CS1 control register
CS1CR
16
16
1, 2 BCLK
0008 381Ah
BSC
CS1 recovery cycle register
CS1REC
16
16
1, 2 BCLK
0008 3822h
BSC
CS2 control register
CS2CR
16
16
1, 2 BCLK
0008 382Ah
BSC
CS2 recovery cycle register
CS2REC
16
16
1, 2 BCLK
0008 3832h
BSC
CS3 control register
CS3CR
16
16
1, 2 BCLK
0008 383Ah
BSC
CS3 recovery cycle register
CS3REC
16
16
1, 2 BCLK
0008 3842h
BSC
CS4 control register
CS4CR
16
16
1, 2 BCLK
0008 384Ah
BSC
CS4 recovery cycle register
CS4REC
16
16
1, 2 BCLK
0008 3852h
BSC
CS5 control register
CS5CR
16
16
1, 2 BCLK
0008 385Ah
BSC
CS5 recovery cycle register
CS5REC
16
16
1, 2 BCLK
0008 3862h
BSC
CS6 control register
CS6CR
16
16
1, 2 BCLK
0008 386Ah
BSC
CS6 recovery cycle register
CS6REC
16
16
1, 2 BCLK
0008 3872h
BSC
CS7 control register
CS7CR
16
16
1, 2 BCLK
0008 387Ah
BSC
CS7 recovery cycle register
CS7REC
16
16
1, 2 BCLK
0008 3880h
BSC
CS recovery cycle insertion enable register
CSRECEN
16
16
1, 2 BCLK
0008 6400h
MPU
Region-0 start page number register
RSPAGE0
32
32
1ICLK
0008 6404h
MPU
Region-0 end page number register
REPAGE0
32
32
1ICLK
0008 6408h
MPU
Region-1 start page number register
RSPAGE1
32
32
1ICLK
0008 640Ch
MPU
Region-1 end page number register
REPAGE1
32
32
1ICLK
0008 6410h
MPU
Region-2 start page number register
RSPAGE2
32
32
1ICLK
0008 6414h
MPU
Region-2 end page number register
REPAGE2
32
32
1ICLK
0008 6418h
MPU
Region-3 start page number register
RSPAGE3
32
32
1ICLK
0008 641Ch
MPU
Region-3 end page number register
REPAGE3
32
32
1ICLK
0008 6420h
MPU
Region-4 start page number register
RSPAGE4
32
32
1ICLK
0008 6424h
MPU
Region-4 end page number register
REPAGE4
32
32
1ICLK
0008 6428h
MPU
Region-5 start page number register
RSPAGE5
32
32
1ICLK
0008 642Ch
MPU
Region-5 end page number register
REPAGE5
32
32
1ICLK
0008 6430h
MPU
Region-6 start page number register
RSPAGE6
32
32
1ICLK
0008 6434h
MPU
Region-6 end page number register
REPAGE6
32
32
1ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
Buses
MPU
Page 62 of 154
RX630 Group
Table 4.1
Address
4. I/O Registers
List of I/O Registers (Address Order) (4/42)
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
Number of Access States
ICLK PCLK
ICLK PCLK
0008 6438h
MPU
Region-7 start page number register
RSPAGE7
32
32
1ICLK
0008 643Ch
MPU
Region-7 end page number register
REPAGE7
32
32
1ICLK
0008 6500h
MPU
Memory-protection enable register
MPEN
32
32
1ICLK
0008 6504h
MPU
Background access control register
MPBAC
32
32
1ICLK
0008 6508h
MPU
Memory-protection error status-clearing register MPECLR
32
32
1ICLK
0008 650Ch
MPU
Memory-protection error status register
MPESTS
32
32
1ICLK
0008 6514h
MPU
Data memory-protection error address register
MPDEA
32
32
1ICLK
0008 6520h
MPU
Region search address register
MPSA
32
32
1ICLK
0008 6524h
MPU
Region search operation register
MPOPS
16
16
1ICLK
0008 6526h
MPU
Region invalidation operation register
MPOPI
16
16
1ICLK
0008 6528h
MPU
Instruction-hit region register
MHITI
32
32
1ICLK
0008 652Ch
MPU
Data-hit region register
MHITD
32
32
1ICLK
0008 7010h
ICU
Interrupt request register 016
IR016
8
8
2 ICLK
0008 7015h
ICU
Interrupt request register 021
IR021
8
8
2 ICLK
0008 7017h
ICU
Interrupt request register 023
IR023
8
8
2 ICLK
0008 701Bh
ICU
Interrupt request register 027
IR027
8
8
2 ICLK
0008 701Ch
ICU
Interrupt request register 028
IR028
8
8
2 ICLK
0008 701Dh
ICU
Interrupt request register 029
IR029
8
8
2 ICLK
0008 701Eh
ICU
Interrupt request register 030
IR030
8
8
2 ICLK
0008 701Fh
ICU
Interrupt request register 031
IR031
8
8
2 ICLK
0008 7021h
ICU
Interrupt request register 033
IR033
8
8
2 ICLK
0008 7022h
ICU
Interrupt request register 034
IR034
8
8
2 ICLK
0008 7023h
ICU
Interrupt request register 035
IR035
8
8
2 ICLK
0008 7027h
ICU
Interrupt request register 039
IR039
8
8
2 ICLK
0008 7028h
ICU
Interrupt request register 040
IR040
8
8
2 ICLK
2 ICLK
0008 7029h
ICU
Interrupt request register 041
IR041
8
8
0008 702Ah
ICU
Interrupt request register 042
IR042
8
8
2 ICLK
0008 702Bh
ICU
Interrupt request register 043
IR043
8
8
2 ICLK
0008 702Ch
ICU
Interrupt request register 044
IR044
8
8
2 ICLK
0008 702Dh
ICU
Interrupt request register 045
IR045
8
8
2 ICLK
0008 702Eh
ICU
Interrupt request register 046
IR046
8
8
2 ICLK
0008 702Fh
ICU
Interrupt request register 047
IR047
8
8
2 ICLK
0008 7030h
ICU
Interrupt request register 048
IR048
8
8
2 ICLK
0008 7031h
ICU
Interrupt request register 049
IR049
8
8
2 ICLK
0008 7032h
ICU
Interrupt request register 050
IR050
8
8
2 ICLK
0008 7033h
ICU
Interrupt request register 051
IR051
8
8
2 ICLK
0008 7034h
ICU
Interrupt request register 052
IR052
8
8
2 ICLK
0008 7035h
ICU
Interrupt request register 053
IR053
8
8
2 ICLK
0008 7036h
ICU
Interrupt request register 054
IR054
8
8
2 ICLK
0008 7037h
ICU
Interrupt request register 055
IR055
8
8
2 ICLK
0008 7038h
ICU
Interrupt request register 056
IR056
8
8
2 ICLK
0008 7039h
ICU
Interrupt request register 057
IR057
8
8
2 ICLK
0008 703Ah
ICU
Interrupt request register 058
IR058
8
8
2 ICLK
0008 703Bh
ICU
Interrupt request register 059
IR059
8
8
2 ICLK
0008 703Eh
ICU
Interrupt request register 062
IR062
8
8
2 ICLK
0008 7040h
ICU
Interrupt request register 064
IR064
8
8
2 ICLK
0008 7041h
ICU
Interrupt request register 065
IR065
8
8
2 ICLK
0008 7042h
ICU
Interrupt request register 066
IR066
8
8
2 ICLK
0008 7043h
ICU
Interrupt request register 067
IR067
8
8
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
MPU
ICUb
Page 63 of 154
RX630 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (5/42)
Address
Module
Symbol
Register Name
Register
Symbol
0008 7044h
ICU
Interrupt request register 068
0008 7045h
ICU
Interrupt request register 069
0008 7046h
ICU
0008 7047h
ICU
0008 7048h
0008 7049h
Number of Access States
Number
of Bits
Access
Size
IR068
8
8
2 ICLK
IR069
8
8
2 ICLK
Interrupt request register 070
IR070
8
8
2 ICLK
Interrupt request register 071
IR071
8
8
2 ICLK
ICU
Interrupt request register 072
IR072
8
8
2 ICLK
ICU
Interrupt request register 073
IR073
8
8
2 ICLK
0008 704Ah
ICU
Interrupt request register 074
IR074
8
8
2 ICLK
0008 704Bh
ICU
Interrupt request register 075
IR075
8
8
2 ICLK
0008 704Ch
ICU
Interrupt request register 076
IR076
8
8
2 ICLK
0008 704Dh
ICU
Interrupt request register 077
IR077
8
8
2 ICLK
0008 704Eh
ICU
Interrupt request register 078
IR078
8
8
2 ICLK
ICLK PCLK
ICLK PCLK
0008 704Fh
ICU
Interrupt request register 079
IR079
8
8
2 ICLK
0008 705Ah
ICU
Interrupt request register 090
IR090
8
8
2 ICLK
0008 705Ch
ICU
Interrupt request register 092
IR092
8
8
2 ICLK
0008 705Dh
ICU
Interrupt request register 093
IR093
8
8
2 ICLK
0008 7062h
ICU
Interrupt request register 098
IR098
8
8
2 ICLK
0008 7066h
ICU
Interrupt request register 102
IR102
8
8
2 ICLK
0008 706Ah
ICU
Interrupt request register 106
IR106
8
8
2 ICLK
0008 706Bh
ICU
Interrupt request register 107
IR107
8
8
2 ICLK
0008 706Ch
ICU
Interrupt request register 108
IR108
8
8
2 ICLK
0008 706Dh
ICU
Interrupt request register 109
IR109
8
8
2 ICLK
0008 706Eh
ICU
Interrupt request register 110
IR110
8
8
2 ICLK
0008 706Fh
ICU
Interrupt request register 111
IR111
8
8
2 ICLK
0008 7070h
ICU
Interrupt request register 112
IR112
8
8
2 ICLK
0008 7072h
ICU
Interrupt request register 114
IR114
8
8
2 ICLK
0008 707Ah
ICU
Interrupt request register 122
IR122
8
8
2 ICLK
0008 707Bh
ICU
Interrupt request register 123
IR123
8
8
2 ICLK
0008 707Ch
ICU
Interrupt request register 124
IR124
8
8
2 ICLK
0008 707Dh
ICU
Interrupt request register 125
IR125
8
8
2 ICLK
0008 707Eh
ICU
Interrupt request register 126
IR126
8
8
2 ICLK
0008 707Fh
ICU
Interrupt request register 127
IR127
8
8
2 ICLK
0008 7080h
ICU
Interrupt request register 128
IR128
8
8
2 ICLK
0008 7081h
ICU
Interrupt request register 129
IR129
8
8
2 ICLK
0008 7082h
ICU
Interrupt request register 130
IR130
8
8
2 ICLK
0008 7083h
ICU
Interrupt request register 131
IR131
8
8
2 ICLK
0008 7084h
ICU
Interrupt request register 132
IR132
8
8
2 ICLK
2 ICLK
0008 7085h
ICU
Interrupt request register 133
IR133
8
8
0008 7086h
ICU
Interrupt request register 134
IR134
8
8
2 ICLK
0008 7087h
ICU
Interrupt request register 135
IR135
8
8
2 ICLK
0008 7088h
ICU
Interrupt request register 136
IR136
8
8
2 ICLK
2 ICLK
0008 7089h
ICU
Interrupt request register 137
IR137
8
8
0008 708Ah
ICU
Interrupt request register 138
IR138
8
8
2 ICLK
0008 708Bh
ICU
Interrupt request register 139
IR139
8
8
2 ICLK
0008 708Ch
ICU
Interrupt request register 140
IR140
8
8
2 ICLK
2 ICLK
0008 708Dh
ICU
Interrupt request register 141
IR141
8
8
0008 708Eh
ICU
Interrupt request register 142
IR142
8
8
2 ICLK
0008 708Fh
ICU
Interrupt request register 143
IR143
8
8
2 ICLK
0008 7090h
ICU
Interrupt request register 144
IR144
8
8
2 ICLK
0008 7091h
ICU
Interrupt request register 145
IR145
8
8
2 ICLK
0008 7092h
ICU
Interrupt request register 146
IR146
8
8
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
ICUb
Page 64 of 154
RX630 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (6/42)
Address
Module
Symbol
Register Name
Register
Symbol
0008 7093h
ICU
Interrupt request register 147
0008 7094h
ICU
Interrupt request register 148
Number of Access States
Number
of Bits
Access
Size
IR147
8
8
2 ICLK
IR148
8
8
2 ICLK
ICLK PCLK
ICLK PCLK
0008 7095h
ICU
Interrupt request register 149
IR149
8
8
2 ICLK
0008 7096h
ICU
Interrupt request register 150
IR150
8
8
2 ICLK
2 ICLK
0008 7097h
ICU
Interrupt request register 151
IR151
8
8
0008 7098h
ICU
Interrupt request register 152
IR152
8
8
2 ICLK
0008 7099h
ICU
Interrupt request register 153
IR153
8
8
2 ICLK
0008 709Ah
ICU
Interrupt request register 154
IR154
8
8
2 ICLK
0008 709Bh
ICU
Interrupt request register 155
IR155
8
8
2 ICLK
0008 709Ch
ICU
Interrupt request register 156
IR156
8
8
2 ICLK
0008 709Dh
ICU
Interrupt request register 157
IR157
8
8
2 ICLK
0008 709Eh
ICU
Interrupt request register 158
IR158
8
8
2 ICLK
0008 709Fh
ICU
Interrupt request register 159
IR159
8
8
2 ICLK
0008 70A0h
ICU
Interrupt request register 160
IR160
8
8
2 ICLK
0008 70A1h
ICU
Interrupt request register 161
IR161
8
8
2 ICLK
0008 70A2h
ICU
Interrupt request register 162
IR162
8
8
2 ICLK
0008 70A3h
ICU
Interrupt request register 163
IR163
8
8
2 ICLK
0008 70A4h
ICU
Interrupt request register 164
IR164
8
8
2 ICLK
2 ICLK
0008 70A5h
ICU
Interrupt request register 165
IR165
8
8
0008 70A6h
ICU
Interrupt request register 166
IR166
8
8
2 ICLK
0008 70A7h
ICU
Interrupt request register 167
IR167
8
8
2 ICLK
0008 70AAh
ICU
Interrupt request register 170
IR170
8
8
2 ICLK
0008 70ABh
ICU
Interrupt request register 171
IR171
8
8
2 ICLK
0008 70ACh
ICU
Interrupt request register 172
IR172
8
8
2 ICLK
0008 70ADh
ICU
Interrupt request register 173
IR173
8
8
2 ICLK
0008 70AEh
ICU
Interrupt request register 174
IR174
8
8
2 ICLK
0008 70AFh
ICU
Interrupt request register 175
IR175
8
8
2 ICLK
0008 70B0h
ICU
Interrupt request register 176
IR176
8
8
2 ICLK
0008 70B1h
ICU
Interrupt request register 177
IR177
8
8
2 ICLK
0008 70B2h
ICU
Interrupt request register 178
IR178
8
8
2 ICLK
0008 70B3h
ICU
Interrupt request register 179
IR179
8
8
2 ICLK
0008 70B4h
ICU
Interrupt request register 180
IR180
8
8
2 ICLK
0008 70B5h
ICU
Interrupt request register 181
IR181
8
8
2 ICLK
0008 70B6h
ICU
Interrupt request register 182
IR182
8
8
2 ICLK
0008 70B7h
ICU
Interrupt request register 183
IR183
8
8
2 ICLK
0008 70B8h
ICU
Interrupt request register 184
IR184
8
8
2 ICLK
0008 70B9h
ICU
Interrupt request register 185
IR185
8
8
2 ICLK
0008 70BAh
ICU
Interrupt request register 186
IR186
8
8
2 ICLK
0008 70BBh
ICU
Interrupt request register 187
IR187
8
8
2 ICLK
0008 70BCh
ICU
Interrupt request register 188
IR188
8
8
2 ICLK
0008 70BDh
ICU
Interrupt request register 189
IR189
8
8
2 ICLK
0008 70BEh
ICU
Interrupt request register 190
IR190
8
8
2 ICLK
0008 70BFh
ICU
Interrupt request register 191
IR191
8
8
2 ICLK
0008 70C0h
ICU
Interrupt request register 192
IR192
8
8
2 ICLK
0008 70C1h
ICU
Interrupt request register 193
IR193
8
8
2 ICLK
0008 70C2h
ICU
Interrupt request register 194
IR194
8
8
2 ICLK
0008 70C3h
ICU
Interrupt request register 195
IR195
8
8
2 ICLK
0008 70C4h
ICU
Interrupt request register 196
IR196
8
8
2 ICLK
0008 70C5h
ICU
Interrupt request register 197
IR197
8
8
2 ICLK
0008 70C6h
ICU
Interrupt request register 198
IR198
8
8
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
ICUb
Page 65 of 154
RX630 Group
Table 4.1
Address
4. I/O Registers
List of I/O Registers (Address Order) (7/42)
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
Number of Access States
ICLK PCLK
ICLK PCLK
0008 70C7h
ICU
Interrupt request register 199
IR199
8
8
2 ICLK
0008 70C8h
ICU
Interrupt request register 200
IR200
8
8
2 ICLK
0008 70C9h
ICU
Interrupt request register 201
IR201
8
8
2 ICLK
0008 70D6h
ICU
Interrupt request register 214
IR214
8
8
2 ICLK
0008 70D7h
ICU
Interrupt request register 215
IR215
8
8
2 ICLK
0008 70D8h
ICU
Interrupt request register 216
IR216
8
8
2 ICLK
0008 70D9h
ICU
Interrupt request register 217
IR217
8
8
2 ICLK
2 ICLK
0008 70DAh
ICU
Interrupt request register 218
IR218
8
8
0008 70DBh
ICU
Interrupt request register 219
IR219
8
8
2 ICLK
0008 70DCh
ICU
Interrupt request register 220
IR220
8
8
2 ICLK
0008 70DDh
ICU
Interrupt request register 221
IR221
8
8
2 ICLK
0008 70DEh
ICU
Interrupt request register 222
IR222
8
8
2 ICLK
0008 70DFh
ICU
Interrupt request register 223
IR223
8
8
2 ICLK
0008 70E0h
ICU
Interrupt request register 224
IR224
8
8
2 ICLK
0008 70E1h
ICU
Interrupt request register 225
IR225
8
8
2 ICLK
0008 70E2h
ICU
Interrupt request register 226
IR226
8
8
2 ICLK
0008 70E3h
ICU
Interrupt request register 227
IR227
8
8
2 ICLK
0008 70E4h
ICU
Interrupt request register 228
IR228
8
8
2 ICLK
0008 70E5h
ICU
Interrupt request register 229
IR229
8
8
2 ICLK
0008 70E6h
ICU
Interrupt request register 230
IR230
8
8
2 ICLK
0008 70E7h
ICU
Interrupt request register 231
IR231
8
8
2 ICLK
0008 70E8h
ICU
Interrupt request register 232
IR232
8
8
2 ICLK
0008 70E9h
ICU
Interrupt request register 233
IR233
8
8
2 ICLK
0008 70EAh
ICU
Interrupt request register 234
IR234
8
8
2 ICLK
0008 70EBh
ICU
Interrupt request register 235
IR235
8
8
2 ICLK
0008 70ECh
ICU
Interrupt request register 236
IR236
8
8
2 ICLK
0008 70EDh
ICU
Interrupt request register 237
IR237
8
8
2 ICLK
0008 70EEh
ICU
Interrupt request register 238
IR238
8
8
2 ICLK
0008 70EFh
ICU
Interrupt request register 239
IR239
8
8
2 ICLK
2 ICLK
0008 70F0h
ICU
Interrupt request register 240
IR240
8
8
0008 70F1h
ICU
Interrupt request register 241
IR241
8
8
2 ICLK
0008 70F2h
ICU
Interrupt request register 242
IR242
8
8
2 ICLK
0008 70F3h
ICU
Interrupt request register 243
IR243
8
8
2 ICLK
0008 70F4h
ICU
Interrupt request register 244
IR244
8
8
2 ICLK
0008 70F5h
ICU
Interrupt request register 245
IR245
8
8
2 ICLK
0008 70F6h
ICU
Interrupt request register 246
IR246
8
8
2 ICLK
0008 70F7h
ICU
Interrupt request register 247
IR247
8
8
2 ICLK
0008 70F8h
ICU
Interrupt request register 248
IR248
8
8
2 ICLK
0008 70F9h
ICU
Interrupt request register 249
IR249
8
8
2 ICLK
0008 70FAh
ICU
Interrupt request register 250
IR250
8
8
2 ICLK
0008 70FBh
ICU
Interrupt request register 251
IR251
8
8
2 ICLK
0008 70FCh
ICU
Interrupt request register 252
IR252
8
8
2 ICLK
0008 70FDh
ICU
Interrupt request register 253
IR253
8
8
2 ICLK
0008 711Bh
ICU
DTC activation enable register 027
DTCER027
8
8
2 ICLK
0008 711Ch
ICU
DTC activation enable register 028
DTCER028
8
8
2 ICLK
0008 711Dh
ICU
DTC activation enable register 029
DTCER029
8
8
2 ICLK
0008 711Eh
ICU
DTC activation enable register 030
DTCER030
8
8
2 ICLK
0008 711Fh
ICU
DTC activation enable register 031
DTCER031
8
8
2 ICLK
0008 7121h
ICU
DTC activation enable register 033
DTCER033
8
8
2 ICLK
0008 7122h
ICU
DTC activation enable register 034
DTCER034
8
8
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
ICUb
Page 66 of 154
RX630 Group
Table 4.1
Address
4. I/O Registers
List of I/O Registers (Address Order) (8/42)
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
Number of Access States
ICLK PCLK
ICLK PCLK
0008 7127h
ICU
DTC activation enable register 039
DTCER039
8
8
2 ICLK
0008 7128h
ICU
DTC activation enable register 040
DTCER040
8
8
2 ICLK
0008 712Ah
ICU
DTC activation enable register 042
DTCER042
8
8
2 ICLK
0008 712Bh
ICU
DTC activation enable register 043
DTCER043
8
8
2 ICLK
0008 712Dh
ICU
DTC activation enable register 045
DTCER045
8
8
2 ICLK
0008 712Eh
ICU
DTC activation enable register 046
DTCER046
8
8
2 ICLK
0008 7140h
ICU
DTC activation enable register 064
DTCER064
8
8
2 ICLK
0008 7141h
ICU
DTC activation enable register 065
DTCER065
8
8
2 ICLK
0008 7142h
ICU
DTC activation enable register 066
DTCER066
8
8
2 ICLK
0008 7143h
ICU
DTC activation enable register 067
DTCER067
8
8
2 ICLK
0008 7144h
ICU
DTC activation enable register 068
DTCER068
8
8
2 ICLK
0008 7145h
ICU
DTC activation enable register 069
DTCER069
8
8
2 ICLK
0008 7146h
ICU
DTC activation enable register 070
DTCER070
8
8
2 ICLK
0008 7147h
ICU
DTC activation enable register 071
DTCER071
8
8
2 ICLK
0008 7148h
ICU
DTC activation enable register 072
DTCER072
8
8
2 ICLK
0008 7149h
ICU
DTC activation enable register 073
DTCER073
8
8
2 ICLK
0008 714Ah
ICU
DTC activation enable register 074
DTCER074
8
8
2 ICLK
0008 714Bh
ICU
DTC activation enable register 075
DTCER075
8
8
2 ICLK
0008 714Ch
ICU
DTC activation enable register 076
DTCER076
8
8
2 ICLK
0008 714Dh
ICU
DTC activation enable register 077
DTCER077
8
8
2 ICLK
0008 714Eh
ICU
DTC activation enable register 078
DTCER078
8
8
2 ICLK
0008 714Fh
ICU
DTC activation enable register 079
DTCER079
8
8
2 ICLK
0008 7162h
ICU
DTC activation enable register 098
DTCER098
8
8
2 ICLK
0008 7166h
ICU
DTC activation enable register 102
DTCER102
8
8
2 ICLK
0008 717Eh
ICU
DTC activation enable register 126
DTCER126
8
8
2 ICLK
0008 717Fh
ICU
DTC activation enable register 127
DTCER127
8
8
2 ICLK
0008 7180h
ICU
DTC activation enable register 128
DTCER128
8
8
2 ICLK
0008 7181h
ICU
DTC activation enable register 129
DTCER129
8
8
2 ICLK
0008 7182h
ICU
DTC activation enable register 130
DTCER130
8
8
2 ICLK
0008 7183h
ICU
DTC activation enable register 131
DTCER131
8
8
2 ICLK
0008 7184h
ICU
DTC activation enable register 132
DTCER132
8
8
2 ICLK
0008 7185h
ICU
DTC activation enable register 133
DTCER133
8
8
2 ICLK
0008 7186h
ICU
DTC activation enable register 134
DTCER134
8
8
2 ICLK
0008 7187h
ICU
DTC activation enable register 135
DTCER135
8
8
2 ICLK
0008 7188h
ICU
DTC activation enable register 136
DTCER136
8
8
2 ICLK
0008 7189h
ICU
DTC activation enable register 137
DTCER137
8
8
2 ICLK
0008 718Ah
ICU
DTC activation enable register 138
DTCER138
8
8
2 ICLK
0008 718Bh
ICU
DTC activation enable register 139
DTCER139
8
8
2 ICLK
0008 718Ch
ICU
DTC activation enable register 140
DTCER140
8
8
2 ICLK
0008 718Dh
ICU
DTC activation enable register 141
DTCER141
8
8
2 ICLK
0008 718Eh
ICU
DTC activation enable register 142
DTCER142
8
8
2 ICLK
0008 718Fh
ICU
DTC activation enable register 143
DTCER143
8
8
2 ICLK
0008 7190h
ICU
DTC activation enable register 144
DTCER144
8
8
2 ICLK
0008 7191h
ICU
DTC activation enable register 145
DTCER145
8
8
2 ICLK
0008 7194h
ICU
DTC activation enable register 148
DTCER148
8
8
2 ICLK
0008 7195h
ICU
DTC activation enable register 149
DTCER149
8
8
2 ICLK
0008 7196h
ICU
DTC activation enable register 150
DTCER150
8
8
2 ICLK
0008 7197h
ICU
DTC activation enable register 151
DTCER151
8
8
2 ICLK
0008 7198h
ICU
DTC activation enable register 152
DTCER152
8
8
2 ICLK
0008 7199h
ICU
DTC activation enable register 153
DTCER153
8
8
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
ICUb
Page 67 of 154
RX630 Group
Table 4.1
Address
4. I/O Registers
List of I/O Registers (Address Order) (9/42)
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
Number of Access States
ICLK PCLK
ICLK PCLK
0008 719Ah
ICU
DTC activation enable register 154
DTCER154
8
8
2 ICLK
0008 719Bh
ICU
DTC activation enable register 155
DTCER155
8
8
2 ICLK
0008 719Ch
ICU
DTC activation enable register 156
DTCER156
8
8
2 ICLK
0008 719Dh
ICU
DTC activation enable register 157
DTCER157
8
8
2 ICLK
0008 719Eh
ICU
DTC activation enable register 158
DTCER158
8
8
2 ICLK
0008 719Fh
ICU
DTC activation enable register 159
DTCER159
8
8
2 ICLK
0008 71A0h
ICU
DTC activation enable register 160
DTCER160
8
8
2 ICLK
0008 71A1h
ICU
DTC activation enable register 161
DTCER161
8
8
2 ICLK
0008 71A2h
ICU
DTC activation enable register 162
DTCER162
8
8
2 ICLK
0008 71A3h
ICU
DTC activation enable register 163
DTCER163
8
8
2 ICLK
0008 71A4h
ICU
DTC activation enable register 164
DTCER164
8
8
2 ICLK
0008 71A5h
ICU
DTC activation enable register 165
DTCER165
8
8
2 ICLK
0008 71AAh
ICU
DTC activation enable register 170
DTCER170
8
8
2 ICLK
0008 71ABh
ICU
DTC activation enable register 171
DTCER171
8
8
2 ICLK
0008 71ADh
ICU
DTC activation enable register 173
DTCER173
8
8
2 ICLK
0008 71AEh
ICU
DTC activation enable register 174
DTCER174
8
8
2 ICLK
0008 71B0h
ICU
DTC activation enable register 176
DTCER176
8
8
2 ICLK
0008 71B1h
ICU
DTC activation enable register 177
DTCER177
8
8
2 ICLK
0008 71B3h
ICU
DTC activation enable register 179
DTCER179
8
8
2 ICLK
0008 71B4h
ICU
DTC activation enable register 180
DTCER180
8
8
2 ICLK
0008 71B7h
ICU
DTC activation enable register 183
DTCER183
8
8
2 ICLK
0008 71B8h
ICU
DTC activation enable register 184
DTCER184
8
8
2 ICLK
0008 71BBh
ICU
DTC activation enable register 187
DTCER187
8
8
2 ICLK
0008 71BCh
ICU
DTC activation enable register 188
DTCER188
8
8
2 ICLK
0008 71BFh
ICU
DTC activation enable register 191
DTCER191
8
8
2 ICLK
0008 71C0h
ICU
DTC activation enable register 192
DTCER192
8
8
2 ICLK
0008 71C3h
ICU
DTC activation enable register 195
DTCER195
8
8
2 ICLK
0008 71C4h
ICU
DTC activation enable register 196
DTCER196
8
8
2 ICLK
0008 71C6h
ICU
DTC activation enable register 198
DTCER198
8
8
2 ICLK
0008 71C7h
ICU
DTC activation enable register 199
DTCER199
8
8
2 ICLK
0008 71C8h
ICU
DTC activation enable register 200
DTCER200
8
8
2 ICLK
0008 71C9h
ICU
DTC activation enable register 201
DTCER201
8
8
2 ICLK
0008 71D6h
ICU
DTC activation enable register 214
DTCER214
8
8
2 ICLK
0008 71D7h
ICU
DTC activation enable register 215
DTCER215
8
8
2 ICLK
0008 71D9h
ICU
DTC activation enable register 217
DTCER217
8
8
2 ICLK
0008 71DAh
ICU
DTC activation enable register 218
DTCER218
8
8
2 ICLK
0008 71DCh
ICU
DTC activation enable register 220
DTCER220
8
8
2 ICLK
0008 71DDh
ICU
DTC activation enable register 221
DTCER221
8
8
2 ICLK
0008 71DFh
ICU
DTC activation enable register 223
DTCER223
8
8
2 ICLK
0008 71E0h
ICU
DTC activation enable register 224
DTCER224
8
8
2 ICLK
0008 71E2h
ICU
DTC activation enable register 226
DTCER226
8
8
2 ICLK
0008 71E3h
ICU
DTC activation enable register 227
DTCER227
8
8
2 ICLK
0008 71E5h
ICU
DTC activation enable register 229
DTCER229
8
8
2 ICLK
0008 71E6h
ICU
DTC activation enable register 230
DTCER230
8
8
2 ICLK
0008 71E8h
ICU
DTC activation enable register 232
DTCER232
8
8
2 ICLK
0008 71E9h
ICU
DTC activation enable register 233
DTCER233
8
8
2 ICLK
0008 71EBh
ICU
DTC activation enable register 235
DTCER235
8
8
2 ICLK
0008 71ECh
ICU
DTC activation enable register 236
DTCER236
8
8
2 ICLK
0008 71EEh
ICU
DTC activation enable register 238
DTCER238
8
8
2 ICLK
0008 71EFh
ICU
DTC activation enable register 239
DTCER239
8
8
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
ICUb
Page 68 of 154
RX630 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (10/42)
Address
Module
Symbol
Register Name
Register
Symbol
0008 71F1h
ICU
DTC activation enable register 241
0008 71F2h
ICU
DTC activation enable register 242
Number of Access States
Number
of Bits
Access
Size
DTCER241
8
8
2 ICLK
DTCER242
8
8
2 ICLK
ICLK PCLK
ICLK PCLK
0008 71F4h
ICU
DTC activation enable register 244
DTCER244
8
8
2 ICLK
0008 71F5h
ICU
DTC activation enable register 245
DTCER245
8
8
2 ICLK
0008 71F7h
ICU
DTC activation enable register 247
DTCER247
8
8
2 ICLK
0008 71F8h
ICU
DTC activation enable register 248
DTCER248
8
8
2 ICLK
0008 71FAh
ICU
DTC activation enable register 250
DTCER250
8
8
2 ICLK
0008 71FBh
ICU
DTC activation enable register 251
DTCER251
8
8
2 ICLK
0008 7202h
ICU
Interrupt request enable register 02
IER02
8
8
2 ICLK
0008 7203h
ICU
Interrupt request enable register 03
IER03
8
8
2 ICLK
0008 7204h
ICU
Interrupt request enable register 04
IER04
8
8
2 ICLK
0008 7205h
ICU
Interrupt request enable register 05
IER05
8
8
2 ICLK
0008 7206h
ICU
Interrupt request enable register 06
IER06
8
8
2 ICLK
0008 7207h
ICU
Interrupt request enable register 07
IER07
8
8
2 ICLK
0008 7208h
ICU
Interrupt request enable register 08
IER08
8
8
2 ICLK
0008 7209h
ICU
Interrupt request enable register 09
IER09
8
8
2 ICLK
0008 720Bh
ICU
Interrupt request enable register 0B
IER0B
8
8
2 ICLK
0008 720Ch
ICU
Interrupt request enable register 0C
IER0C
8
8
2 ICLK
0008 720Dh
ICU
Interrupt request enable register 0D
IER0D
8
8
2 ICLK
0008 720Eh
ICU
Interrupt request enable register 0E
IER0E
8
8
2 ICLK
0008 720Fh
ICU
Interrupt request enable register 0F
IER0F
8
8
2 ICLK
0008 7210h
ICU
Interrupt request enable register 10
IER10
8
8
2 ICLK
0008 7211h
ICU
Interrupt request enable register 11
IER11
8
8
2 ICLK
0008 7212h
ICU
Interrupt request enable register 12
IER12
8
8
2 ICLK
0008 7213h
ICU
Interrupt request enable register 13
IER13
8
8
2 ICLK
0008 7214h
ICU
Interrupt request enable register 14
IER14
8
8
2 ICLK
0008 7215h
ICU
Interrupt request enable register 15
IER15
8
8
2 ICLK
0008 7216h
ICU
Interrupt request enable register 16
IER16
8
8
2 ICLK
0008 7217h
ICU
Interrupt request enable register 17
IER17
8
8
2 ICLK
0008 7218h
ICU
Interrupt request enable register 18
IER18
8
8
2 ICLK
0008 7219h
ICU
Interrupt request enable register 19
IER19
8
8
2 ICLK
0008 721Ah
ICU
Interrupt request enable register 1A
IER1A
8
8
2 ICLK
0008 721Bh
ICU
Interrupt request enable register 1B
IER1B
8
8
2 ICLK
0008 721Ch
ICU
Interrupt request enable register 1C
IER1C
8
8
2 ICLK
0008 721Dh
ICU
Interrupt request enable register 1D
IER1D
8
8
2 ICLK
0008 721Eh
ICU
Interrupt request enable register 1E
IER1E
8
8
2 ICLK
0008 721Fh
ICU
Interrupt request enable register 1F
IER1F
8
8
2 ICLK
0008 72E0h
ICU
Software interrupt activation register
SWINTR
8
8
2 ICLK
0008 72F0h
ICU
Fast interrupt set register
FIR
16
16
2 ICLK
0008 7300h
ICU
Interrupt source priority register 000
IPR000
8
8
2 ICLK
0008 7301h
ICU
Interrupt source priority register 001
IPR001
8
8
2 ICLK
0008 7302h
ICU
Interrupt source priority register 002
IPR002
8
8
2 ICLK
0008 7303h
ICU
Interrupt source priority register 003
IPR003
8
8
2 ICLK
0008 7304h
ICU
Interrupt source priority register 004
IPR004
8
8
2 ICLK
0008 7305h
ICU
Interrupt source priority register 005
IPR005
8
8
2 ICLK
0008 7306h
ICU
Interrupt source priority register 006
IPR006
8
8
2 ICLK
0008 7307h
ICU
Interrupt source priority register 007
IPR007
8
8
2 ICLK
0008 7321h
ICU
Interrupt source priority register 033
IPR033
8
8
2 ICLK
0008 7322h
ICU
Interrupt source priority register 034
IPR034
8
8
2 ICLK
0008 7323h
ICU
Interrupt source priority register 035
IPR035
8
8
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
ICUb
Page 69 of 154
RX630 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (11/42)
Address
Module
Symbol
Register Name
Register
Symbol
0008 7327h
ICU
Interrupt source priority register 039
0008 732Ah
ICU
Interrupt source priority register 042
0008 732Dh
ICU
0008 7330h
ICU
0008 7334h
0008 7338h
Number of Access States
Number
of Bits
Access
Size
IPR039
8
8
2 ICLK
IPR042
8
8
2 ICLK
Interrupt source priority register 045
IPR045
8
8
2 ICLK
Interrupt source priority register 048
IPR048
8
8
2 ICLK
ICU
Interrupt source priority register 052
IPR052
8
8
2 ICLK
ICU
Interrupt source priority register 056
IPR056
8
8
2 ICLK
0008 733Eh
ICU
Interrupt source priority register 062
IPR062
8
8
2 ICLK
0008 7340h
ICU
Interrupt source priority register 064
IPR064
8
8
2 ICLK
0008 7341h
ICU
Interrupt source priority register 065
IPR065
8
8
2 ICLK
0008 7342h
ICU
Interrupt source priority register 066
IPR066
8
8
2 ICLK
0008 7343h
ICU
Interrupt source priority register 067
IPR067
8
8
2 ICLK
0008 7344h
ICU
Interrupt source priority register 068
IPR068
8
8
2 ICLK
0008 7345h
ICU
Interrupt source priority register 069
IPR069
8
8
2 ICLK
0008 7346h
ICU
Interrupt source priority register 070
IPR070
8
8
2 ICLK
0008 7347h
ICU
Interrupt source priority register 071
IPR071
8
8
2 ICLK
0008 7348h
ICU
Interrupt source priority register 072
IPR072
8
8
2 ICLK
0008 7349h
ICU
Interrupt source priority register 073
IPR073
8
8
2 ICLK
0008 734Ah
ICU
Interrupt source priority register 074
IPR074
8
8
2 ICLK
0008 734Bh
ICU
Interrupt source priority register 075
IPR075
8
8
2 ICLK
0008 734Ch
ICU
Interrupt source priority register 076
IPR076
8
8
2 ICLK
0008 734Dh
ICU
Interrupt source priority register 077
IPR077
8
8
2 ICLK
0008 734Eh
ICU
Interrupt source priority register 078
IPR078
8
8
2 ICLK
ICLK PCLK
ICLK PCLK
0008 734Fh
ICU
Interrupt source priority register 079
IPR079
8
8
2 ICLK
0008 735Ah
ICU
Interrupt source priority register 090
IPR090
8
8
2 ICLK
0008 735Ch
ICU
Interrupt source priority register 092
IPR092
8
8
2 ICLK
0008 735Dh
ICU
Interrupt source priority register 093
IPR093
8
8
2 ICLK
0008 7362h
ICU
Interrupt source priority register 098
IPR098
8
8
2 ICLK
0008 7366h
ICU
Interrupt source priority register 102
IPR102
8
8
2 ICLK
0008 736Ah
ICU
Interrupt source priority register 106
IPR106
8
8
2 ICLK
0008 736Bh
ICU
Interrupt source priority register 107
IPR107
8
8
2 ICLK
0008 736Ch
ICU
Interrupt source priority register 108
IPR108
8
8
2 ICLK
0008 736Dh
ICU
Interrupt source priority register 109
IPR109
8
8
2 ICLK
0008 736Eh
ICU
Interrupt source priority register 110
IPR110
8
8
2 ICLK
0008 736Fh
ICU
Interrupt source priority register 111
IPR111
8
8
2 ICLK
0008 7370h
ICU
Interrupt source priority register 112
IPR112
8
8
2 ICLK
0008 7372h
ICU
Interrupt source priority register 114
IPR114
8
8
2 ICLK
0008 737Ah
ICU
Interrupt source priority register 122
IPR122
8
8
2 ICLK
0008 737Eh
ICU
Interrupt source priority register 126
IPR126
8
8
2 ICLK
0008 7382h
ICU
Interrupt source priority register 130
IPR130
8
8
2 ICLK
0008 7384h
ICU
Interrupt source priority register 132
IPR132
8
8
2 ICLK
0008 7386h
ICU
Interrupt source priority register 134
IPR134
8
8
2 ICLK
0008 738Ah
ICU
Interrupt source priority register 138
IPR138
8
8
2 ICLK
0008 738Ch
ICU
Interrupt source priority register 140
IPR140
8
8
2 ICLK
0008 738Eh
ICU
Interrupt source priority register 142
IPR142
8
8
2 ICLK
0008 7392h
ICU
Interrupt source priority register 146
IPR146
8
8
2 ICLK
0008 7394h
ICU
Interrupt source priority register 148
IPR148
8
8
2 ICLK
0008 7396h
ICU
Interrupt source priority register 150
IPR150
8
8
2 ICLK
0008 7398h
ICU
Interrupt source priority register 152
IPR152
8
8
2 ICLK
0008 739Ch
ICU
Interrupt source priority register 156
IPR156
8
8
2 ICLK
0008 73A0h
ICU
Interrupt source priority register 160
IPR160
8
8
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
ICUb
Page 70 of 154
RX630 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (12/42)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
0008 73A1h
ICU
Interrupt source priority register 161
0008 73A4h
ICU
Interrupt source priority register 164
IPR161
8
8
2 ICLK
IPR164
8
8
2 ICLK
0008 73A6h
ICU
Interrupt source priority register 166
IPR166
8
8
2 ICLK
0008 73AAh
ICU
Interrupt source priority register 170
IPR170
8
8
2 ICLK
ICLK PCLK
ICLK PCLK
0008 73ADh
ICU
Interrupt source priority register 173
IPR173
8
8
2 ICLK
0008 73B0h
ICU
Interrupt source priority register 176
IPR176
8
8
2 ICLK
0008 73B3h
ICU
Interrupt source priority register 179
IPR179
8
8
2 ICLK
0008 73B6h
ICU
Interrupt source priority register 182
IPR182
8
8
2 ICLK
0008 73B7h
ICU
Interrupt source priority register 183
IPR183
8
8
2 ICLK
0008 73B8h
ICU
Interrupt source priority register 184
IPR184
8
8
2 ICLK
0008 73B9h
ICU
Interrupt source priority register 185
IPR185
8
8
2 ICLK
0008 73BAh
ICU
Interrupt source priority register 186
IPR186
8
8
2 ICLK
0008 73BBh
ICU
Interrupt source priority register 187
IPR187
8
8
2 ICLK
0008 73BCh
ICU
Interrupt source priority register 188
IPR188
8
8
2 ICLK
0008 73BDh
ICU
Interrupt source priority register 189
IPR189
8
8
2 ICLK
2 ICLK
0008 73BEh
ICU
Interrupt source priority register 190
IPR190
8
8
0008 73BFh
ICU
Interrupt source priority register 191
IPR191
8
8
2 ICLK
0008 73C0h
ICU
Interrupt source priority register 192
IPR192
8
8
2 ICLK
0008 73C1h
ICU
Interrupt source priority register 193
IPR193
8
8
2 ICLK
0008 73C2h
ICU
Interrupt source priority register 194
IPR194
8
8
2 ICLK
0008 73C3h
ICU
Interrupt source priority register 195
IPR195
8
8
2 ICLK
0008 73C4h
ICU
Interrupt source priority register 196
IPR196
8
8
2 ICLK
0008 73C5h
ICU
Interrupt source priority register 197
IPR197
8
8
2 ICLK
0008 73C6h
ICU
Interrupt source priority register 198
IPR198
8
8
2 ICLK
0008 73C7h
ICU
Interrupt source priority register 199
IPR199
8
8
2 ICLK
0008 73C8h
ICU
Interrupt source priority register 200
IPR200
8
8
2 ICLK
0008 73C9h
ICU
Interrupt source priority register 201
IPR201
8
8
2 ICLK
0008 73D6h
ICU
Interrupt source priority register 214
IPR214
8
8
2 ICLK
0008 73D9h
ICU
Interrupt source priority register 217
IPR217
8
8
2 ICLK
0008 73DCh
ICU
Interrupt source priority register 220
IPR220
8
8
2 ICLK
0008 73DFh
ICU
Interrupt source priority register 223
IPR223
8
8
2 ICLK
0008 73E2h
ICU
Interrupt source priority register 226
IPR226
8
8
2 ICLK
0008 73E5h
ICU
Interrupt source priority register 229
IPR229
8
8
2 ICLK
0008 73E8h
ICU
Interrupt source priority register 232
IPR232
8
8
2 ICLK
0008 73EBh
ICU
Interrupt source priority register 235
IPR235
8
8
2 ICLK
0008 73EEh
ICU
Interrupt source priority register 238
IPR238
8
8
2 ICLK
0008 73F1h
ICU
Interrupt source priority register 241
IPR241
8
8
2 ICLK
0008 73F4h
ICU
Interrupt source priority register 244
IPR244
8
8
2 ICLK
0008 73F7h
ICU
Interrupt source priority register 247
IPR247
8
8
2 ICLK
0008 73FAh
ICU
Interrupt source priority register 250
IPR250
8
8
2 ICLK
0008 73FDh
ICU
Interrupt source priority register 253
IPR253
8
8
2 ICLK
0008 7400h
ICU
DMAC activation request select register 0
DMRSR0
8
8
2 ICLK
0008 7404h
ICU
DMAC activation request select register 1
DMRSR1
8
8
2 ICLK
0008 7408h
ICU
DMAC activation request select register 2
DMRSR2
8
8
2 ICLK
0008 740Ch
ICU
DMAC activation request select register 3
DMRSR3
8
8
2 ICLK
0008 7500h
ICU
IRQ control register 0
IRQCR0
8
8
2 ICLK
0008 7501h
ICU
IRQ control register 1
IRQCR1
8
8
2 ICLK
0008 7502h
ICU
IRQ control register 2
IRQCR2
8
8
2 ICLK
0008 7503h
ICU
IRQ control register 3
IRQCR3
8
8
2 ICLK
0008 7504h
ICU
IRQ control register 4
IRQCR4
8
8
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
ICUb
Page 71 of 154
RX630 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (13/42)
Address
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
Number of Access States
ICLK PCLK
ICLK PCLK
0008 7505h
ICU
IRQ control register 5
IRQCR5
8
8
2 ICLK
0008 7506h
ICU
IRQ control register 6
IRQCR6
8
8
2 ICLK
0008 7507h
ICU
IRQ control register 7
IRQCR7
8
8
2 ICLK
0008 7508h
ICU
IRQ control register 8
IRQCR8
8
8
2 ICLK
0008 7509h
ICU
IRQ control register 9
IRQCR9
8
8
2 ICLK
0008 750Ah
ICU
IRQ control register 10
IRQCR10
8
8
2 ICLK
0008 750Bh
ICU
IRQ control register 11
IRQCR11
8
8
2 ICLK
0008 750Ch
ICU
IRQ control register 12
IRQCR12
8
8
2 ICLK
0008 750Dh
ICU
IRQ control register 13
IRQCR13
8
8
2 ICLK
0008 750Eh
ICU
IRQ control register 14
IRQCR14
8
8
2 ICLK
0008 750Fh
ICU
IRQ control register 15
IRQCR15
8
8
2 ICLK
0008 7510h
ICU
IRQ pin digital filter enable register 0
IRQFLTE0
8
8
2 ICLK
0008 7511h
ICU
IRQ pin digital filter enable register 1
IRQFLTE1
8
8
2 ICLK
0008 7514h
ICU
IRQ pin digital filter setting register 0
IRQFLTC0
8
8
2 ICLK
0008 7516h
ICU
IRQ pin digital filter setting register 1
IRQFLTC1
8
8
2 ICLK
0008 7580h
ICU
Non-maskable interrupt status register
NMISR
8
8
2 ICLK
0008 7581h
ICU
Non-maskable interrupt enable register
NMIER
8
8
2 ICLK
0008 7582h
ICU
Non-maskable interrupt status clear register
NMICLR
8
8
2 ICLK
0008 7583h
ICU
NMI pin interrupt control register
NMICR
8
8
2 ICLK
0008 7590h
ICU
NMI pin digital filter enable register
NMIFLTE
8
8
2 ICLK
0008 7594h
ICU
NMI pin digital filter setting register
NMIFLTC
8
8
0008 8000h
CMT
Compare match timer start register 0
CMSTR0
16
16
ICUb
2 ICLK
2, 3 PCLKB
2 ICLK
0008 8002h
CMT0
Compare match timer control register
CMCR
16
16
2, 3 PCLKB
2 ICLK
0008 8004h
CMT0
Compare match timer counter
CMCNT
16
16
2, 3 PCLKB
2 ICLK
0008 8006h
CMT0
Compare match timer constant register
CMCOR
16
16
2, 3 PCLKB
2 ICLK
0008 8008h
CMT1
Compare match timer control register
CMCR
16
16
2, 3 PCLKB
2 ICLK
0008 800Ah
CMT1
Compare match timer counter
CMCNT
16
16
2, 3 PCLKB
2 ICLK
0008 800Ch
CMT1
Compare match timer constant register
CMCOR
16
16
2, 3 PCLKB
2 ICLK
0008 8010h
CMT
Compare match timer start register 1
CMSTR1
16
16
2, 3 PCLKB
2 ICLK
0008 8012h
CMT2
Compare match timer control register
CMCR
16
16
2, 3 PCLKB
2 ICLK
0008 8014h
CMT2
Compare match timer counter
CMCNT
16
16
2, 3 PCLKB
2 ICLK
0008 8016h
CMT2
Compare match timer constant register
CMCOR
16
16
2, 3 PCLKB
2 ICLK
0008 8018h
CMT3
Compare match timer control register
CMCR
16
16
2, 3 PCLKB
2 ICLK
0008 801Ah
CMT3
Compare match timer counter
CMCNT
16
16
2, 3 PCLKB
2 ICLK
0008 801Ch
CMT3
Compare match timer constant register
CMCOR
16
16
2, 3 PCLKB
2 ICLK
0008 8020h
WDT
WDT refresh register
WDTRR
8
8
2, 3 PCLKB
2 ICLK
0008 8022h
WDT
WDT control register
WDTCR
16
16
2, 3 PCLKB
2 ICLK
0008 8024h
WDT
WDT status register
WDTSR
16
16
2, 3 PCLKB
2 ICLK
0008 8026h
WDT
WDT reset control register
WDTRCR
8
8
2, 3 PCLKB
2 ICLK
0008 8030h
IWDT
IWDT refresh register
IWDTRR
8
8
2, 3 PCLKB
2 ICLK
0008 8032h
IWDT
IWDT control register
IWDTCR
16
16
2, 3 PCLKB
2 ICLK
0008 8034h
IWDT
IWDT status register
IWDTSR
16
16
2, 3 PCLKB
2 ICLK
0008 8036h
IWDT
IWDT reset control register
IWDTRCR
8
8
2, 3 PCLKB
2 ICLK
0008 8038h
IWDT
IWDT count stop control register
IWDTCSTPR
8
8
2, 3 PCLKB
2 ICLK
0008 80C0h
DA
D/A data register 0
DADR0
16
16
2, 3 PCLKB
2 ICLK
0008 80C2h
DA
D/A data register 1
DADR1
16
16
2, 3 PCLKB
2 ICLK
0008 80C4h
DA
D/A control register
DACR
8
8
2, 3 PCLKB
2 ICLK
0008 80C5h
DA
DADRm format select register
DADPR
8
8
2, 3 PCLKB
2 ICLK
0008 80C6h
DA
D/A A/D synchronous start control register
DAADSCR
8
8
2, 3 PCLKB
2 ICLK
0008 8100h
TPUA
Timer start register
TSTR
8
8
2, 3 PCLKB
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
CMT
WDTA
IWDTa
DAa
TPUa
Page 72 of 154
RX630 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (14/42)
Register
Symbol
Number
of Bits
Access
Size
Number of Access States
Address
Module
Symbol
Register Name
0008 8101h
TPUA
Timer synchronous register
TSYR
8
0008 8108h
TPU0
Noise filter control register
NFCR
8
0008 8109h
TPU1
Noise filter control register
NFCR
8
0008 810Ah
TPU2
Noise filter control register
NFCR
8
0008 810Bh
TPU3
Noise filter control register
NFCR
8
8
2, 3 PCLKB
2 ICLK
0008 810Ch
TPU4
Noise filter control register
NFCR
8
8
2, 3 PCLKB
2 ICLK
0008 810Dh
TPU5
Noise filter control register
NFCR
8
8
2, 3 PCLKB
2 ICLK
ICLK PCLK
ICLK PCLK
8
2, 3 PCLKB
2 ICLK
8
2, 3 PCLKB
2 ICLK
8
2, 3 PCLKB
2 ICLK
8
2, 3 PCLKB
2 ICLK
0008 8110h
TPU0
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8111h
TPU0
Timer mode register
TMDR
8
8
2, 3 PCLKB
2 ICLK
0008 8112h
TPU0
Timer I/O control register H
TIORH
8
8
2, 3 PCLKB
2 ICLK
0008 8113h
TPU0
Timer I/O control register L
TIORL
8
8
2, 3 PCLKB
2 ICLK
0008 8114h
TPU0
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
0008 8115h
TPU0
Timer status register
TSR
8
8
2, 3 PCLKB
2 ICLK
0008 8116h
TPU0
Timer counter
TCNT
16
16
2, 3 PCLKB
2 ICLK
0008 8118h
TPU0
Timer general register A
TGRA
16
16
2, 3 PCLKB
2 ICLK
0008 811Ah
TPU0
Timer general register B
TGRB
16
16
2, 3 PCLKB
2 ICLK
0008 811Ch
TPU0
Timer general register C
TGRC
16
16
2, 3 PCLKB
2 ICLK
0008 811Eh
TPU0
Timer general register D
TGRD
16
16
2, 3 PCLKB
2 ICLK
0008 8120h
TPU1
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8121h
TPU1
Timer mode register
TMDR
8
8
2, 3 PCLKB
2 ICLK
0008 8122h
TPU1
Timer I/O control register
TIOR
8
8
2, 3 PCLKB
2 ICLK
0008 8124h
TPU1
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
0008 8125h
TPU1
Timer status register
TSR
8
8
2, 3 PCLKB
2 ICLK
0008 8126h
TPU1
Timer counter
TCNT
16
16
2, 3 PCLKB
2 ICLK
0008 8128h
TPU1
Timer general register A
TGRA
16
16
2, 3 PCLKB
2 ICLK
0008 812Ah
TPU1
Timer general register B
TGRB
16
16
2, 3 PCLKB
2 ICLK
0008 8130h
TPU2
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8131h
TPU2
Timer mode register
TMDR
8
8
2, 3 PCLKB
2 ICLK
0008 8132h
TPU2
Timer I/O control register
TIOR
8
8
2, 3 PCLKB
2 ICLK
0008 8134h
TPU2
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
0008 8135h
TPU2
Timer status register
TSR
8
8
2, 3 PCLKB
2 ICLK
0008 8136h
TPU2
Timer counter
TCNT
16
16
2, 3 PCLKB
2 ICLK
0008 8138h
TPU2
Timer general register A
TGRA
16
16
2, 3 PCLKB
2 ICLK
0008 813Ah
TPU2
Timer general register B
TGRB
16
16
2, 3 PCLKB
2 ICLK
0008 8140h
TPU3
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8141h
TPU3
Timer mode register
TMDR
8
8
2, 3 PCLKB
2 ICLK
0008 8142h
TPU3
Timer I/O control register H
TIORH
8
8
2, 3 PCLKB
2 ICLK
0008 8143h
TPU3
Timer I/O control register L
TIORL
8
8
2, 3 PCLKB
2 ICLK
0008 8144h
TPU3
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
0008 8145h
TPU3
Timer status register
TSR
8
8
2, 3 PCLKB
2 ICLK
0008 8146h
TPU3
Timer counter
TCNT
16
16
2, 3 PCLKB
2 ICLK
0008 8148h
TPU3
Timer general register A
TGRA
16
16
2, 3 PCLKB
2 ICLK
0008 814Ah
TPU3
Timer general register B
TGRB
16
16
2, 3 PCLKB
2 ICLK
0008 814Ch
TPU3
Timer general register C
TGRC
16
16
2, 3 PCLKB
2 ICLK
0008 814Eh
TPU3
Timer general register D
TGRD
16
16
2, 3 PCLKB
2 ICLK
0008 8150h
TPU4
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8151h
TPU4
Timer mode register
TMDR
8
8
2, 3 PCLKB
2 ICLK
0008 8152h
TPU4
Timer I/O control register
TIOR
8
8
2, 3 PCLKB
2 ICLK
0008 8154h
TPU4
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
0008 8155h
TPU4
Timer status register
TSR
8
8
2, 3 PCLKB
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
TPUa
Page 73 of 154
RX630 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (15/42)
Address
Module
Symbol
Register Name
Register
Symbol
0008 8156h
TPU4
Timer counter
0008 8158h
TPU4
Timer general register A
0008 815Ah
TPU4
0008 8160h
TPU5
Number of Access States
Number
of Bits
Access
Size
TCNT
16
16
2, 3 PCLKB
2 ICLK
TGRA
16
16
2, 3 PCLKB
2 ICLK
Timer general register B
TGRB
16
16
2, 3 PCLKB
2 ICLK
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
ICLK PCLK
ICLK PCLK
0008 8161h
TPU5
Timer mode register
TMDR
8
8
2, 3 PCLKB
0008 8162h
TPU5
Timer I/O control register
TIOR
8
8
2, 3 PCLKB
2 ICLK
0008 8164h
TPU5
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
0008 8165h
TPU5
Timer status register
TSR
8
8
2, 3 PCLKB
2 ICLK
0008 8166h
TPU5
Timer counter
TCNT
16
16
2, 3 PCLKB
2 ICLK
0008 8168h
TPU5
Timer general register A
TGRA
16
16
2, 3 PCLKB
2 ICLK
0008 816Ah
TPU5
Timer general register B
TGRB
16
16
2, 3 PCLKB
2 ICLK
0008 8170h
TPUB
Timer start register
TSTR
8
8
2, 3 PCLKB
2 ICLK
0008 8171h
TPUB
Timer synchronous register
TSYR
8
8
2, 3 PCLKB
2 ICLK
0008 8178h
TPU6
Noise filter control register
NFCR
8
8
2, 3 PCLKB
2 ICLK
0008 8179h
TPU7
Noise filter control register
NFCR
8
8
2, 3 PCLKB
2 ICLK
0008 817Ah
TPU8
Noise filter control register
NFCR
8
8
2, 3 PCLKB
2 ICLK
0008 817Bh
TPU9
Noise filter control register
NFCR
8
8
2, 3 PCLKB
2 ICLK
0008 817Ch
TPU10
Noise filter control register
NFCR
8
8
2, 3 PCLKB
2 ICLK
0008 817Dh
TPU11
Noise filter control register
NFCR
8
8
2, 3 PCLKB
2 ICLK
0008 8180h
TPU6
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8181h
TPU6
Timer mode register
TMDR
8
8
2, 3 PCLKB
2 ICLK
0008 8182h
TPU6
Timer I/O control register H
TIORH
8
8
2, 3 PCLKB
2 ICLK
0008 8183h
TPU6
Timer I/O control register L
TIORL
8
8
2, 3 PCLKB
2 ICLK
0008 8184h
TPU6
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
0008 8185h
TPU6
Timer status register
TSR
8
8
2, 3 PCLKB
2 ICLK
0008 8186h
TPU6
Timer counter
TCNT
16
16
2, 3 PCLKB
2 ICLK
0008 8188h
TPU6
Timer general register A
TGRA
16
16
2, 3 PCLKB
2 ICLK
0008 818Ah
TPU6
Timer general register B
TGRB
16
16
2, 3 PCLKB
2 ICLK
0008 818Ch
TPU6
Timer general register C
TGRC
16
16
2, 3 PCLKB
2 ICLK
0008 818Eh
TPU6
Timer general register D
TGRD
16
16
2, 3 PCLKB
2 ICLK
0008 8190h
TPU7
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8191h
TPU7
Timer mode register
TMDR
8
8
2, 3 PCLKB
2 ICLK
0008 8192h
TPU7
Timer I/O control register
TIOR
8
8
2, 3 PCLKB
2 ICLK
0008 8194h
TPU7
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
0008 8195h
TPU7
Timer status register
TSR
8
8
2, 3 PCLKB
2 ICLK
0008 8196h
TPU7
Timer counter
TCNT
16
16
2, 3 PCLKB
2 ICLK
0008 8198h
TPU7
Timer general register A
TGRA
16
16
2, 3 PCLKB
2 ICLK
0008 819Ah
TPU7
Timer general register B
TGRB
16
16
2, 3 PCLKB
2 ICLK
0008 81A0h
TPU8
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 81A1h
TPU8
Timer mode register
TMDR
8
8
2, 3 PCLKB
2 ICLK
0008 81A2h
TPU8
Timer I/O control register
TIOR
8
8
2, 3 PCLKB
2 ICLK
0008 81A4h
TPU8
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
0008 81A5h
TPU8
Timer status register
TSR
8
8
2, 3 PCLKB
2 ICLK
0008 81A6h
TPU8
Timer counter
TCNT
16
16
2, 3 PCLKB
2 ICLK
0008 81A8h
TPU8
Timer general register A
TGRA
16
16
2, 3 PCLKB
2 ICLK
0008 81AAh
TPU8
Timer general register B
TGRB
16
16
2, 3 PCLKB
2 ICLK
0008 81B0h
TPU9
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 81B1h
TPU9
Timer mode register
TMDR
8
8
2, 3 PCLKB
2 ICLK
0008 81B2h
TPU9
Timer I/O control register H
TIORH
8
8
2, 3 PCLKB
2 ICLK
0008 81B3h
TPU9
Timer I/O control register L
TIORL
8
8
2, 3 PCLKB
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
TPUa
Page 74 of 154
RX630 Group
Table 4.1
Address
4. I/O Registers
List of I/O Registers (Address Order) (16/42)
Module
Symbol
Register Name
Register
Symbol
Number of Access States
Number
of Bits
Access
Size
ICLK PCLK
ICLK PCLK
0008 81B4h
TPU9
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
0008 81B5h
TPU9
Timer status register
TSR
8
8
2, 3 PCLKB
2 ICLK
0008 81B6h
TPU9
Timer counter
TCNT
16
16
2, 3 PCLKB
2 ICLK
0008 81B8h
TPU9
Timer general register A
TGRA
16
16
2, 3 PCLKB
2 ICLK
0008 81BAh
TPU9
Timer general register B
TGRB
16
16
2, 3 PCLKB
2 ICLK
0008 81BCh
TPU9
Timer general register C
TGRC
16
16
2, 3 PCLKB
2 ICLK
0008 81BEh
TPU9
Timer general register D
TGRD
16
16
2, 3 PCLKB
2 ICLK
0008 81C0h
TPU10
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 81C1h
TPU10
Timer mode register
TMDR
8
8
2, 3 PCLKB
2 ICLK
0008 81C2h
TPU10
Timer I/O control register
TIOR
8
8
2, 3 PCLKB
2 ICLK
0008 81C4h
TPU10
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 81C5h
TPU10
Timer status register
TSR
8
8
2, 3 PCLKB
0008 81C6h
TPU10
Timer counter
TCNT
16
16
2, 3 PCLKB
2 ICLK
0008 81C8h
TPU10
Timer general register A
TGRA
16
16
2, 3 PCLKB
2 ICLK
0008 81CAh
TPU10
Timer general register B
TGRB
16
16
2, 3 PCLKB
2 ICLK
0008 81D0h
TPU11
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 81D1h
TPU11
Timer mode register
TMDR
8
8
2, 3 PCLKB
2 ICLK
0008 81D2h
TPU11
Timer I/O control register
TIOR
8
8
2, 3 PCLKB
2 ICLK
0008 81D4h
TPU11
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
0008 81D5h
TPU11
Timer status register
TSR
8
8
2, 3 PCLKB
2 ICLK
0008 81D6h
TPU11
Timer counter
TCNT
16
16
2, 3 PCLKB
2 ICLK
0008 81D8h
TPU11
Timer general register A
TGRA
16
16
2, 3 PCLKB
2 ICLK
0008 81DAh
TPU11
Timer general register B
TGRB
16
16
2, 3 PCLKB
2 ICLK
0008 81E6h
PPG0
PPG output control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 81E7h
PPG0
PPG output mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 81E8h
PPG0
Next data enable register H
NDERH
8
8
2, 3 PCLKB
2 ICLK
0008 81E9h
PPG0
Next data enable register L
NDERL
8
8
2, 3 PCLKB
2 ICLK
0008 81EAh
PPG0
Output data register H
PODRH
8
8
2, 3 PCLKB
2 ICLK
0008 81EBh
PPG0
Output data register L
PODRL
8
8
2, 3 PCLKB
2 ICLK
81ECh*1
PPG0
Next data register H
NDRH
8
8
2, 3 PCLKB
2 ICLK
0008 81EDh*2
PPG0
Next data register L
NDRL
8
8
2, 3 PCLKB
2 ICLK
0008 81EEh*1
PPG0
Next data register H
NDRH2
8
8
2, 3 PCLKB
2 ICLK
0008 81EFh*2
PPG0
Next data register L
NDRL2
8
8
2, 3 PCLKB
2 ICLK
0008
0008 81F0h
PPG1
PPG trigger select register
PTRSLR
8
8
2, 3 PCLKB
2 ICLK
0008 81F6h
PPG1
PPG output control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 81F7h
PPG1
PPG output mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 81F8h
PPG1
Next data enable register H
NDERH
8
8
2, 3 PCLKB
2 ICLK
0008 81F9h
PPG1
Next data enable register L
NDERL
8
8
2, 3 PCLKB
2 ICLK
0008 81FAh
PPG1
Output data register H
PODRH
8
8
2, 3 PCLKB
2 ICLK
0008 81FBh
PPG1
Output data register L
PODRL
8
8
2, 3 PCLKB
2 ICLK
0008 81FCh*3
PPG1
Next data register H
NDRH
8
8
2, 3 PCLKB
2 ICLK
0008 81FDh*4
PPG1
Next data register L
NDRL
8
8
2, 3 PCLKB
2 ICLK
0008 81FEh*3
PPG1
Next data register H
NDRH2
8
8
2, 3 PCLKB
2 ICLK
0008 81FFh*4
PPG1
Next data register L
NDRL2
8
8
2, 3 PCLKB
2 ICLK
0008 8200h
TMR0
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8201h
TMR1
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8202h
TMR0
Timer control/status register
TCSR
8
8
2, 3 PCLKB
2 ICLK
0008 8203h
TMR1
Timer control/status register
TCSR
8
8
2, 3 PCLKB
2 ICLK
0008 8204h
TMR0
Time constant register A
TCORA
8
8
2, 3 PCLKB
2 ICLK
0008 8205h
TMR1
Time constant register A
TCORA
8
8*5
2, 3 PCLKB
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
TPUa
PPG
TMR
Page 75 of 154
RX630 Group
Table 4.1
Address
4. I/O Registers
List of I/O Registers (Address Order) (17/42)
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Number of Access States
Access
Size
ICLK PCLK
ICLK PCLK
0008 8206h
TMR0
Time constant register B
TCORB
8
8
2, 3 PCLKB
2 ICLK
0008 8207h
TMR1
Time constant register B
TCORB
8
8*5
2, 3 PCLKB
2 ICLK
0008 8208h
TMR0
Timer counter
TCNT
8
8
2, 3 PCLKB
2 ICLK
0008 8209h
TMR1
Timer counter
TCNT
8
8*5
2, 3 PCLKB
2 ICLK
0008 820Ah
TMR0
Timer counter control register
TCCR
8
8
2, 3 PCLKB
2 ICLK
0008 820Bh
TMR1
Timer counter control register
TCCR
8
8*5
2, 3 PCLKB
2 ICLK
0008 8210h
TMR2
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8211h
TMR3
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8212h
TMR2
Timer control/status register
TCSR
8
8
2, 3 PCLKB
2 ICLK
0008 8213h
TMR3
Timer control/status register
TCSR
8
8
2, 3 PCLKB
2 ICLK
0008 8214h
TMR2
Time constant register A
TCORA
8
8
2, 3 PCLKB
2 ICLK
0008 8215h
TMR3
Time constant register A
TCORA
8
8*5
2, 3 PCLKB
2 ICLK
0008 8216h
TMR2
Time constant register B
TCORB
8
8
2, 3 PCLKB
2 ICLK
0008 8217h
TMR3
Time constant register B
TCORB
8
8*5
2, 3 PCLKB
2 ICLK
2 ICLK
0008 8218h
TMR2
Timer counter
TCNT
8
8
2, 3 PCLKB
0008 8219h
TMR3
Timer counter
TCNT
8
8*5
2, 3 PCLKB
2 ICLK
0008 821Ah
TMR2
Timer counter control register
TCCR
8
8
2, 3 PCLKB
2 ICLK
0008 821Bh
TMR3
Timer counter control register
TCCR
8
8*5
2, 3 PCLKB
2 ICLK
0008 8280h
CRC
CRC control register
CRCCR
8
8
2, 3 PCLKB
2 ICLK
0008 8281h
CRC
CRC data input register
CRCDIR
8
8
2, 3 PCLKB
2 ICLK
0008 8282h
CRC
CRC data output register
CRCDOR
16
16
2, 3 PCLKB
2 ICLK
0008 8300h
RIIC0
I2C bus control register 1
ICCR1
8
8
2, 3 PCLKB
2 ICLK
0008 8301h
RIIC0
I2 C
ICCR2
8
8
2, 3 PCLKB
2 ICLK
0008 8302h
RIIC0
I2C bus mode register 1
ICMR1
8
8
2, 3 PCLKB
2 ICLK
0008 8303h
RIIC0
I2C bus mode register 2
ICMR2
8
8
2, 3 PCLKB
2 ICLK
0008 8304h
RIIC0
I2C
0008 8305h
RIIC0
I2C bus function enable register
0008 8306h
RIIC0
I2C bus status enable register
ICSER
8
8
2, 3 PCLKB
2 ICLK
0008 8307h
RIIC0
I2C bus interrupt enable register
ICIER
8
8
2, 3 PCLKB
2 ICLK
0008 8308h
RIIC0
I2C bus status register 1
ICSR1
8
8
2, 3 PCLKB
2 ICLK
0008 8309h
RIIC0
I2C bus status register 2
ICSR2
8
8
2, 3 PCLKB
2 ICLK
0008 830Ah
RIIC0
Slave address register L0
SARL0
8
8
2, 3 PCLKB
2 ICLK
0008 830Ah
RIIC0
Timeout Internal Counter L
TMOCNTL
8
8
2, 3 PCLKB
2 ICLK
bus control register 2
bus mode register 3
ICMR3
8
8
2, 3 PCLKB
2 ICLK
ICFER
8
8
2, 3 PCLKB
2 ICLK
0008 830Bh
RIIC0
Slave address register U0
SARU0
8
8
2, 3 PCLKB
2 ICLK
0008 830Bh
RIIC0
Timeout Internal Counter U
TMOCNTU
8
8
2, 3 PCLKB
2 ICLK
0008 830Ch
RIIC0
Slave address register L1
SARL1
8
8
2, 3 PCLKB
2 ICLK
0008 830Dh
RIIC0
Slave address register U1
SARU1
8
8
2, 3 PCLKB
2 ICLK
0008 830Eh
RIIC0
Slave address register L2
SARL2
8
8
2, 3 PCLKB
2 ICLK
0008 830Fh
RIIC0
Slave address register U2
SARU2
8
8
2, 3 PCLKB
2 ICLK
0008 8310h
RIIC0
I2C bus bit rate low-level register
ICBRL
8
8
2, 3 PCLKB
2 ICLK
ICBRH
8
8
2, 3 PCLKB
2 ICLK
ICDRT
8
8
2, 3 PCLKB
2 ICLK
0008 8311h
RIIC0
I2 C
0008 8312h
RIIC0
I2C bus transmit data register
0008 8313h
RIIC0
I2C bus receive data register
ICDRR
8
8
2, 3 PCLKB
2 ICLK
0008 8320h
RIIC1
I2C bus control register 1
ICCR1
8
8
2, 3 PCLKB
2 ICLK
0008 8321h
RIIC1
I2 C
ICCR2
8
8
2, 3 PCLKB
2 ICLK
0008 8322h
RIIC1
I2C bus mode register 1
ICMR1
8
8
2, 3 PCLKB
2 ICLK
0008 8323h
RIIC1
I2C bus mode register 2
ICMR2
8
8
2, 3 PCLKB
2 ICLK
0008 8324h
RIIC1
I2C
ICMR3
8
8
2, 3 PCLKB
2 ICLK
0008 8325h
RIIC1
I2C bus function enable register
ICFER
8
8
2, 3 PCLKB
2 ICLK
0008 8326h
RIIC1
I2C bus status enable register
ICSER
8
8
2, 3 PCLKB
2 ICLK
bus bit rate high-level register
bus control register 2
bus mode register 3
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
TMR
CRC
RIIC
Page 76 of 154
RX630 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (18/42)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
ICLK PCLK
ICLK PCLK
0008 8327h
RIIC1
I2C bus interrupt enable register
0008 8328h
RIIC1
I2C bus status register 1
ICIER
8
8
2, 3 PCLKB
2 ICLK
ICSR1
8
8
2, 3 PCLKB
2 ICLK
0008 8329h
RIIC1
I2C bus status register 2
ICSR2
8
8
2, 3 PCLKB
2 ICLK
0008 832Ah
RIIC1
Slave address register L0
SARL0
8
8
2, 3 PCLKB
2 ICLK
0008 832Ah
RIIC1
Timeout Internal Counter L
TMOCNTL
8
8
2, 3 PCLKB
2 ICLK
0008 832Bh
RIIC1
Slave address register U0
SARU0
8
8
2, 3 PCLKB
2 ICLK
0008 832Bh
RIIC1
Timeout Internal Counter U
TMOCNTU
8
8
2, 3 PCLKB
2 ICLK
0008 832Ch
RIIC1
Slave address register L1
SARL1
8
8
2, 3 PCLKB
2 ICLK
0008 832Dh
RIIC1
Slave address register U1
SARU1
8
8
2, 3 PCLKB
2 ICLK
0008 832Eh
RIIC1
Slave address register L2
SARL2
8
8
2, 3 PCLKB
2 ICLK
0008 832Fh
RIIC1
Slave address register U2
SARU2
8
8
2, 3 PCLKB
2 ICLK
0008 8330h
RIIC1
I 2C
ICBRL
8
8
2, 3 PCLKB
2 ICLK
0008 8331h
RIIC1
I2C bus bit rate high-level register
ICBRH
8
8
2, 3 PCLKB
2 ICLK
0008 8332h
RIIC1
I2C bus transmit data register
ICDRT
8
8
2, 3 PCLKB
2 ICLK
0008 8333h
RIIC1
I2 C
ICDRR
8
8
2, 3 PCLKB
2 ICLK
0008 8340h
RIIC2
I2C bus control register 1
ICCR1
8
8
2, 3 PCLKB
2 ICLK
0008 8341h
RIIC2
I2C bus control register 2
ICCR2
8
8
2, 3 PCLKB
2 ICLK
0008 8342h
RIIC2
I2C bus mode register 1
ICMR1
8
8
2, 3 PCLKB
2 ICLK
0008 8343h
RIIC2
I2C bus mode register 2
ICMR2
8
8
2, 3 PCLKB
2 ICLK
0008 8344h
RIIC2
I2C bus mode register 3
ICMR3
8
8
2, 3 PCLKB
2 ICLK
0008 8345h
RIIC2
I2C bus function enable register
ICFER
8
8
2, 3 PCLKB
2 ICLK
0008 8346h
RIIC2
I2C bus status enable register
ICSER
8
8
2, 3 PCLKB
2 ICLK
bus bit rate low-level register
bus receive data register
0008 8347h
RIIC2
I2C
ICIER
8
8
2, 3 PCLKB
2 ICLK
0008 8348h
RIIC2
I2C bus status register 1
ICSR1
8
8
2, 3 PCLKB
2 ICLK
0008 8349h
RIIC2
I2C bus status register 2
ICSR2
8
8
2, 3 PCLKB
2 ICLK
bus interrupt enable register
0008 834Ah
RIIC2
Slave address register L0
SARL0
8
8
2, 3 PCLKB
2 ICLK
0008 834Bh
RIIC2
Slave address register U0
SARU0
8
8
2, 3 PCLKB
2 ICLK
0008 834Ch
RIIC2
Slave address register L1
SARL1
8
8
2, 3 PCLKB
2 ICLK
0008 834Dh
RIIC2
Slave address register U1
SARU1
8
8
2, 3 PCLKB
2 ICLK
0008 834Eh
RIIC2
Slave address register L2
SARL2
8
8
2, 3 PCLKB
2 ICLK
0008 834Fh
RIIC2
Slave address register U2
SARU2
8
8
2, 3 PCLKB
2 ICLK
0008 8350h
RIIC2
I2C bus bit rate low-level register
ICBRL
8
8
2, 3 PCLKB
2 ICLK
0008 8351h
RIIC2
I2C bus bit rate high-level register
ICBRH
8
8
2, 3 PCLKB
2 ICLK
0008 8352h
RIIC2
I2C bus transmit data register
ICDRT
8
8
2, 3 PCLKB
2 ICLK
0008 8353h
RIIC2
I2C bus receive data register
ICDRR
8
8
2, 3 PCLKB
2 ICLK
0008 8360h
RIIC3
I2C bus control register 1
ICCR1
8
8
2, 3 PCLKB
2 ICLK
0008 8361h
RIIC3
I2 C
ICCR2
8
8
2, 3 PCLKB
2 ICLK
0008 8362h
RIIC3
I2C bus mode register 1
ICMR1
8
8
2, 3 PCLKB
2 ICLK
0008 8363h
RIIC3
I2C bus mode register 2
ICMR2
8
8
2, 3 PCLKB
2 ICLK
0008 8364h
RIIC3
I2C bus mode register 3
ICMR3
8
8
2, 3 PCLKB
2 ICLK
0008 8365h
RIIC3
I2C
ICFER
8
8
2, 3 PCLKB
2 ICLK
0008 8366h
RIIC3
I2C bus status enable register
ICSER
8
8
2, 3 PCLKB
2 ICLK
0008 8367h
RIIC3
I2C bus interrupt enable register
ICIER
8
8
2, 3 PCLKB
2 ICLK
0008 8368h
RIIC3
I2C bus status register 1
ICSR1
8
8
2, 3 PCLKB
2 ICLK
0008 8369h
RIIC3
I2 C
ICSR2
8
8
2, 3 PCLKB
2 ICLK
0008 836Ah
RIIC3
Slave address register L0
SARL0
8
8
2, 3 PCLKB
2 ICLK
0008 836Bh
RIIC3
Slave address register U0
SARU0
8
8
2, 3 PCLKB
2 ICLK
bus control register 2
bus function enable register
bus status register 2
0008 836Ch
RIIC3
Slave address register L1
SARL1
8
8
2, 3 PCLKB
2 ICLK
0008 836Dh
RIIC3
Slave address register U1
SARU1
8
8
2, 3 PCLKB
2 ICLK
0008 836Eh
RIIC3
Slave address register L2
SARL2
8
8
2, 3 PCLKB
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
RIIC
Page 77 of 154
RX630 Group
Table 4.1
Address
4. I/O Registers
List of I/O Registers (Address Order) (19/42)
Module
Symbol
Register Name
Register
Symbol
Number of Access States
Number
of Bits
Access
Size
ICLK PCLK
ICLK PCLK
0008 836Fh
RIIC3
Slave address register U2
SARU2
8
8
2, 3 PCLKB
2 ICLK
0008 8370h
RIIC3
I2C bus bit rate low-level register
ICBRL
8
8
2, 3 PCLKB
2 ICLK
0008 8371h
RIIC3
I2C bus bit rate high-level register
ICBRH
8
8
2, 3 PCLKB
2 ICLK
0008 8372h
RIIC3
I2C bus transmit data register
ICDRT
8
8
2, 3 PCLKB
2 ICLK
0008 8373h
RIIC3
I2C bus receive data register
ICDRR
8
8
2, 3 PCLKB
2 ICLK
0008 8380h
RSPI0
RSPI control register
SPCR
8
8
2, 3 PCLKB
2 ICLK
0008 8381h
RSPI0
RSPI slave select polarity register
SSLP
8
8
2, 3 PCLKB
2 ICLK
0008 8382h
RSPI0
RSPI pin control register
SPPCR
8
8
2, 3 PCLKB
2 ICLK
0008 8383h
RSPI0
RSPI status register
SPSR
8
8
2, 3 PCLKB
2 ICLK
0008 8384h
RSPI0
RSPI data register
SPDR
32
16, 32
2, 3 PCLKB
2 ICLK
0008 8388h
RSPI0
RSPI sequence control register
SPSCR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 8389h
RSPI0
RSPI sequence status register
SPSSR
8
8
2, 3 PCLKB
0008 838Ah
RSPI0
RSPI bit rate register
SPBR
8
8
2, 3 PCLKB
2 ICLK
0008 838Bh
RSPI0
RSPI data control register
SPDCR
8
8
2, 3 PCLKB
2 ICLK
0008 838Ch
RSPI0
RSPI clock delay register
SPCKD
8
8
2, 3 PCLKB
2 ICLK
0008 838Dh
RSPI0
RSPI slave select negation delay register
SSLND
8
8
2, 3 PCLKB
2 ICLK
0008 838Eh
RSPI0
RSPI next-access delay register
SPND
8
8
2, 3 PCLKB
2 ICLK
0008 838Fh
RSPI0
RSPI control register 2
SPCR2
8
8
2, 3 PCLKB
2 ICLK
0008 8390h
RSPI0
RSPI command register 0
SPCMD0
16
16
2, 3 PCLKB
2 ICLK
0008 8392h
RSPI0
RSPI command register 1
SPCMD1
16
16
2, 3 PCLKB
2 ICLK
0008 8394h
RSPI0
RSPI command register 2
SPCMD2
16
16
2, 3 PCLKB
2 ICLK
0008 8396h
RSPI0
RSPI command register 3
SPCMD3
16
16
2, 3 PCLKB
2 ICLK
0008 8398h
RSPI0
RSPI command register 4
SPCMD4
16
16
2, 3 PCLKB
2 ICLK
0008 839Ah
RSPI0
RSPI command register 5
SPCMD5
16
16
2, 3 PCLKB
2 ICLK
0008 839Ch
RSPI0
RSPI command register 6
SPCMD6
16
16
2, 3 PCLKB
2 ICLK
2 ICLK
0008 839Eh
RSPI0
RSPI command register 7
SPCMD7
16
16
2, 3 PCLKB
0008 83A0h
RSPI1
RSPI control register
SPCR
8
8
2, 3 PCLKB
2 ICLK
0008 83A1h
RSPI1
RSPI slave select polarity register
SSLP
8
8
2, 3 PCLKB
2 ICLK
0008 83A2h
RSPI1
RSPI pin control register
SPPCR
8
8
2, 3 PCLKB
2 ICLK
0008 83A3h
RSPI1
RSPI status register
SPSR
8
8
2, 3 PCLKB
2 ICLK
0008 83A4h
RSPI1
RSPI data register
SPDR
32
16, 32
2, 3 PCLKB
2 ICLK
0008 83A8h
RSPI1
RSPI sequence control register
SPSCR
8
8
2, 3 PCLKB
2 ICLK
0008 83A9h
RSPI1
RSPI sequence status register
SPSSR
8
8
2, 3 PCLKB
2 ICLK
0008 83AAh
RSPI1
RSPI bit rate register
SPBR
8
8
2, 3 PCLKB
2 ICLK
0008 83ABh
RSPI1
RSPI data control register
SPDCR
8
8
2, 3 PCLKB
2 ICLK
0008 83ACh
RSPI1
RSPI clock delay register
SPCKD
8
8
2, 3 PCLKB
2 ICLK
0008 83ADh
RSPI1
RSPI slave select negation delay register
SSLND
8
8
2, 3 PCLKB
2 ICLK
0008 83AEh
RSPI1
RSPI next-access delay register
SPND
8
8
2, 3 PCLKB
2 ICLK
0008 83AFh
RSPI1
RSPI control register 2
SPCR2
8
8
2, 3 PCLKB
2 ICLK
0008 83B0h
RSPI1
RSPI command register 0
SPCMD0
16
16
2, 3 PCLKB
2 ICLK
0008 83B2h
RSPI1
RSPI command register 1
SPCMD1
16
16
2, 3 PCLKB
2 ICLK
0008 83B4h
RSPI1
RSPI command register 2
SPCMD2
16
16
2, 3 PCLKB
2 ICLK
0008 83B6h
RSPI1
RSPI command register 3
SPCMD3
16
16
2, 3 PCLKB
2 ICLK
0008 83B8h
RSPI1
RSPI command register 4
SPCMD4
16
16
2, 3 PCLKB
2 ICLK
0008 83BAh
RSPI1
RSPI command register 5
SPCMD5
16
16
2, 3 PCLKB
2 ICLK
0008 83BCh
RSPI1
RSPI command register 6
SPCMD6
16
16
2, 3 PCLKB
2 ICLK
0008 83BEh
RSPI1
RSPI command register 7
SPCMD7
16
16
2, 3 PCLKB
2 ICLK
0008 83C0h
RSPI2
RSPI control register
SPCR
8
8
2, 3 PCLKB
2 ICLK
0008 83C1h
RSPI2
RSPI slave select polarity register
SSLP
8
8
2, 3 PCLKB
2 ICLK
0008 83C2h
RSPI2
RSPI pin control register
SPPCR
8
8
2, 3 PCLKB
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
RIIC
RSPI
Page 78 of 154
RX630 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (20/42)
Address
Module
Symbol
Register Name
Register
Symbol
0008 83C3h
RSPI2
RSPI status register
SPSR
0008 83C4h
RSPI2
RSPI data register
SPDR
Number
of Bits
Number of Access States
Access
Size
ICLK PCLK
ICLK PCLK
8
8
2, 3 PCLKB
2 ICLK
32
16, 32
2, 3 PCLKB
2 ICLK
0008 83C8h
RSPI2
RSPI sequence control register
SPSCR
8
8
2, 3 PCLKB
2 ICLK
0008 83C9h
RSPI2
RSPI sequence status register
SPSSR
8
8
2, 3 PCLKB
2 ICLK
0008 83CAh
RSPI2
RSPI bit rate register
SPBR
8
8
2, 3 PCLKB
2 ICLK
0008 83CBh
RSPI2
RSPI data control register
SPDCR
8
8
2, 3 PCLKB
2 ICLK
0008 83CCh
RSPI2
RSPI clock delay register
SPCKD
8
8
2, 3 PCLKB
2 ICLK
0008 83CDh
RSPI2
RSPI slave select negation delay register
SSLND
8
8
2, 3 PCLKB
2 ICLK
0008 83CEh
RSPI2
RSPI next-access delay register
SPND
8
8
2, 3 PCLKB
2 ICLK
0008 83CFh
RSPI2
RSPI control register 2
SPCR2
8
8
2, 3 PCLKB
2 ICLK
0008 83D0h
RSPI2
RSPI command register 0
SPCMD0
16
16
2, 3 PCLKB
2 ICLK
0008 83D2h
RSPI2
RSPI command register 1
SPCMD1
16
16
2, 3 PCLKB
2 ICLK
0008 83D4h
RSPI2
RSPI command register 2
SPCMD2
16
16
2, 3 PCLKB
2 ICLK
0008 83D6h
RSPI2
RSPI command register 3
SPCMD3
16
16
2, 3 PCLKB
2 ICLK
0008 83D8h
RSPI2
RSPI command register 4
SPCMD4
16
16
2, 3 PCLKB
2 ICLK
0008 83DAh
RSPI2
RSPI command register 5
SPCMD5
16
16
2, 3 PCLKB
2 ICLK
0008 83DCh
RSPI2
RSPI command register 6
SPCMD6
16
16
2, 3 PCLKB
2 ICLK
0008 83DEh
RSPI2
RSPI command register 7
SPCMD7
16
16
2, 3 PCLKB
2 ICLK
0008 8600h
MTU3
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8601h
MTU4
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8602h
MTU3
Timer mode register
TMDR
8
8
2, 3 PCLKB
2 ICLK
0008 8603h
MTU4
Timer mode register
TMDR
8
8
2, 3 PCLKB
2 ICLK
0008 8604h
MTU3
Timer I/O control register H
TIORH
8
8
2, 3 PCLKB
2 ICLK
0008 8605h
MTU3
Timer I/O control register L
TIORL
8
8
2, 3 PCLKB
2 ICLK
0008 8606h
MTU4
Timer I/O control register H
TIORH
8
8
2, 3 PCLKB
2 ICLK
0008 8607h
MTU4
Timer I/O control register L
TIORL
8
8
2, 3 PCLKB
2 ICLK
0008 8608h
MTU3
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
0008 8609h
MTU4
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
0008 860Ah
MTU
Timer output master enable register
TOER
8
8
2, 3 PCLKB
2 ICLK
0008 860Dh
MTU
Timer gate control register
TGCR
8
8
2, 3 PCLKB
2 ICLK
0008 860Eh
MTU
Timer output control register 1
TOCR1
8
8
2, 3 PCLKB
2 ICLK
0008 860Fh
MTU
Timer output control register 2
TOCR2
8
8
2, 3 PCLKB
2 ICLK
0008 8610h
MTU3
Timer counter
TCNT
16
16
2, 3 PCLKB
2 ICLK
0008 8612h
MTU4
Timer counter
TCNT
16
16
2, 3 PCLKB
2 ICLK
0008 8614h
MTU
Timer cycle data register
TCDR
16
16
2, 3 PCLKB
2 ICLK
0008 8616h
MTU
Timer dead time data register
TDDR
16
16
2, 3 PCLKB
2 ICLK
0008 8618h
MTU3
Timer general register A
TGRA
16
16
2, 3 PCLKB
2 ICLK
0008 861Ah
MTU3
Timer general register B
TGRB
16
16
2, 3 PCLKB
2 ICLK
0008 861Ch
MTU4
Timer general register A
TGRA
16
16
2, 3 PCLKB
2 ICLK
0008 861Eh
MTU4
Timer general register B
TGRB
16
16
2, 3 PCLKB
2 ICLK
0008 8620h
MTU
Timer subcounter
TCNTS
16
16
2, 3 PCLKB
2 ICLK
0008 8622h
MTU
Timer cycle buffer register
TCBR
16
16
2, 3 PCLKB
2 ICLK
0008 8624h
MTU3
Timer general register C
TGRC
16
16
2, 3 PCLKB
2 ICLK
0008 8626h
MTU3
Timer general register D
TGRD
16
16
2, 3 PCLKB
2 ICLK
0008 8628h
MTU4
Timer general register C
TGRC
16
16
2, 3 PCLKB
2 ICLK
0008 862Ah
MTU4
Timer general register D
TGRD
16
16
2, 3 PCLKB
2 ICLK
0008 862Ch
MTU3
Timer status register
TSR
8
8
2, 3 PCLKB
2 ICLK
0008 862Dh
MTU4
Timer status register
TSR
8
8
2, 3 PCLKB
2 ICLK
0008 8630h
MTU
Timer interrupt skipping set register
TITCR
8
8
2, 3 PCLKB
2 ICLK
0008 8631h
MTU
Timer interrupt skipping counter
TITCNT
8
8
2, 3 PCLKB
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
RSPI
MTU2a
Page 79 of 154
RX630 Group
Table 4.1
Address
4. I/O Registers
List of I/O Registers (Address Order) (21/42)
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
Number of Access States
ICLK PCLK
ICLK PCLK
0008 8632h
MTU
Timer buffer transfer set register
TBTER
8
8
2, 3 PCLKB
2 ICLK
0008 8634h
MTU
Timer dead time enable register
TDER
8
8
2, 3 PCLKB
2 ICLK
0008 8636h
MTU
Timer output level buffer register
TOLBR
8
8
2, 3 PCLKB
2 ICLK
0008 8638h
MTU3
Timer buffer operation transfer mode register
TBTM
8
8
2, 3 PCLKB
2 ICLK
0008 8639h
MTU4
Timer buffer operation transfer mode register
TBTM
8
8
2, 3 PCLKB
2 ICLK
0008 8640h
MTU4
Timer A/D converter start request control
register
TADCR
16
16
2, 3 PCLKB
2 ICLK
0008 8644h
MTU4
Timer A/D converter start request cycle set
register A
TADCORA
16
16
2, 3 PCLKB
2 ICLK
0008 8646h
MTU4
Timer A/D converter start request cycle set
register B
TADCORB
16
16
2, 3 PCLKB
2 ICLK
0008 8648h
MTU4
Timer A/D converter start request cycle set
buffer register A
TADCOBRA
16
16
2, 3 PCLKB
2 ICLK
0008 864Ah
MTU4
Timer A/D converter start request cycle set
buffer register B
TADCOBRB
16
16
2, 3 PCLKB
2 ICLK
0008 8660h
MTU
Timer waveform control register
TWCR
8
8, 16
2, 3 PCLKB
2 ICLK
0008 8680h
MTU
Timer start register
TSTR
8
8, 16
2, 3 PCLKB
2 ICLK
0008 8681h
MTU
Timer synchronous register
TSYR
8
8, 16
2, 3 PCLKB
2 ICLK
0008 8684h
MTU
Timer read/write enable register
TRWER
8
8, 16
2, 3 PCLKB
2 ICLK
0008 8690h
MTU0
Noise filter control register
NFCR
8
8, 16
2, 3 PCLKB
2 ICLK
0008 8691h
MTU1
Noise filter control register
NFCR
8
8, 16
2, 3 PCLKB
2 ICLK
0008 8692h
MTU2
Noise filter control register
NFCR
8
8, 16
2, 3 PCLKB
2 ICLK
0008 8693h
MTU3
Noise filter control register
NFCR
8
8, 16
2, 3 PCLKB
2 ICLK
0008 8694h
MTU4
Noise filter control register
NFCR
8
8, 16
2, 3 PCLKB
2 ICLK
0008 8695h
MTU5
Noise filter control register
NFCR
8
8, 16
2, 3 PCLKB
2 ICLK
0008 8700h
MTU0
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8701h
MTU0
Timer mode register
TMDR
8
8
2, 3 PCLKB
2 ICLK
0008 8702h
MTU0
Timer I/O control register H
TIORH
8
8
2, 3 PCLKB
2 ICLK
0008 8703h
MTU0
Timer I/O control register L
TIORL
8
8
2, 3 PCLKB
2 ICLK
0008 8704h
MTU0
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
0008 8705h
MTU0
Timer status register
TSR
8
8
2, 3 PCLKB
2 ICLK
0008 8706h
MTU0
Timer counter
TCNT
16
16
2, 3 PCLKB
2 ICLK
0008 8708h
MTU0
Timer general register A
TGRA
16
16
2, 3 PCLKB
2 ICLK
0008 870Ah
MTU0
Timer general register B
TGRB
16
16
2, 3 PCLKB
2 ICLK
0008 870Ch
MTU0
Timer general register C
TGRC
16
16
2, 3 PCLKB
2 ICLK
0008 870Eh
MTU0
Timer general register D
TGRD
16
16
2, 3 PCLKB
2 ICLK
0008 8720h
MTU0
Timer general register E
TGRE
16
16
2, 3 PCLKB
2 ICLK
0008 8722h
MTU0
Timer general register F
TGRF
16
16
2, 3 PCLKB
2 ICLK
0008 8724h
MTU0
Timer interrupt enable register 2
TIER2
8
8
2, 3 PCLKB
2 ICLK
0008 8726h
MTU0
Timer buffer operation transfer mode register
TBTM
8
8
2, 3 PCLKB
2 ICLK
0008 8780h
MTU1
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8781h
MTU1
Timer mode register
TMDR
8
8
2, 3 PCLKB
2 ICLK
0008 8782h
MTU1
Timer I/O control register
TIOR
8
8
2, 3 PCLKB
2 ICLK
0008 8784h
MTU1
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 8785h
MTU1
Timer status register
TSR
8
8
2, 3 PCLKB
0008 8786h
MTU1
Timer counter
TCNT
16
16
2, 3 PCLKB
2 ICLK
0008 8788h
MTU1
Timer general register A
TGRA
16
16
2, 3 PCLKB
2 ICLK
0008 878Ah
MTU1
Timer general register B
TGRB
16
16
2, 3 PCLKB
2 ICLK
0008 8790h
MTU1
Timer input capture control register
TICCR
8
8
2, 3 PCLKB
2 ICLK
0008 8800h
MTU2
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 8801h
MTU2
Timer mode register
TMDR
8
8
2, 3 PCLKB
2 ICLK
0008 8802h
MTU2
Timer I/O control register
TIOR
8
8
2, 3 PCLKB
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
MTU2a
Page 80 of 154
RX630 Group
Table 4.1
Address
4. I/O Registers
List of I/O Registers (Address Order) (22/42)
Module
Symbol
Register Name
Register
Symbol
Number of Access States
Number
of Bits
Access
Size
ICLK PCLK
ICLK PCLK
0008 8804h
MTU2
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
0008 8805h
MTU2
Timer status register
TSR
8
8
2, 3 PCLKB
2 ICLK
0008 8806h
MTU2
Timer counter
TCNT
16
16
2, 3 PCLKB
2 ICLK
0008 8808h
MTU2
Timer general register A
TGRA
16
16
2, 3 PCLKB
2 ICLK
0008 880Ah
MTU2
Timer general register B
TGRB
16
16
2, 3 PCLKB
2 ICLK
0008 8880h
MTU5
Timer counter U
TCNTU
16
16
2, 3 PCLKB
2 ICLK
0008 8882h
MTU5
Timer general register U
TGRU
16
16
2, 3 PCLKB
2 ICLK
2 ICLK
0008 8884h
MTU5
Timer control register U
TCRU
8
8
2, 3 PCLKB
0008 8886h
MTU5
Timer I/O control register U
TIORU
8
8
2, 3 PCLKB
2 ICLK
0008 8890h
MTU5
Timer counter V
TCNTV
16
16
2, 3 PCLKB
2 ICLK
0008 8892h
MTU5
Timer general register V
TGRV
16
16
2, 3 PCLKB
2 ICLK
0008 8894h
MTU5
Timer control register V
TCRV
8
8
2, 3 PCLKB
2 ICLK
0008 8896h
MTU5
Timer I/O control register V
TIORV
8
8
2, 3 PCLKB
2 ICLK
0008 88A0h
MTU5
Timer counter W
TCNTW
16
16
2, 3 PCLKB
2 ICLK
0008 88A2h
MTU5
Timer general register W
TGRW
16
16
2, 3 PCLKB
2 ICLK
0008 88A4h
MTU5
Timer control register W
TCRW
8
8
2, 3 PCLKB
2 ICLK
0008 88A6h
MTU5
Timer I/O control register W
TIORW
8
8
2, 3 PCLKB
2 ICLK
0008 88B2h
MTU5
Timer interrupt enable register
TIER
8
8
2, 3 PCLKB
2 ICLK
0008 88B4h
MTU5
Timer start register
TSTR
8
8
2, 3 PCLKB
2 ICLK
0008 88B6h
MTU5
Timer compare match clear register
TCNTCMPCLR
8
8
2, 3 PCLKB
2 ICLK
0008 8900h
POE
Input level control/status register 1
ICSR1
16
16
2, 3 PCLKB
2 ICLK
0008 8902h
POE
Output level control/status register 1
OCSR1
16
16
2, 3 PCLKB
2 ICLK
0008 8908h
POE
Input level control/status register 2
ICSR2
16
16
2, 3 PCLKB
2 ICLK
0008 890Ah
POE
Software port output enable register
SPOER
8
8
2, 3 PCLKB
2 ICLK
0008 890Bh
POE
Port output enable control register 1
POECR1
8
8
2, 3 PCLKB
2 ICLK
0008 890Ch
POE
Port output enable control register 2
POECR2
8
8
2, 3 PCLKB
2 ICLK
0008 890Eh
POE
Input level control/status register 3
ICSR3
16
16
2, 3 PCLKB
2 ICLK
0008 9000h
S12AD
A/D control register
ADCSR
8
8
2, 3 PCLKB
2 ICLK
0008 9004h
S12AD
A/D channel select register 0
ADANS0
16
16
2, 3 PCLKB
2 ICLK
0008 9006h
S12AD
A/D channel select register 1
ADANS1
16
16
2, 3 PCLKB
2 ICLK
0008 9008h
S12AD
A/D-converted value addition mode select
register 0
ADADS0
16
16
2, 3 PCLKB
2 ICLK
0008 900Ah
S12AD
A/D-converted value addition mode select
register 1
ADADS1
16
16
2, 3 PCLKB
2 ICLK
0008 900Ch
S12AD
A/D-converted value addition count select
register
ADADC
8
8
2, 3 PCLKB
2 ICLK
0008 900Eh
S12AD
A/D control extended register
ADCER
16
16
2, 3 PCLKB
2 ICLK
0008 9010h
S12AD
A/D start trigger select register
ADSTRGR
8
8
2, 3 PCLKB
2 ICLK
0008 9012h
S12AD
A/D conversion extended input control register
ADEXICR
16
16
2, 3 PCLKB
2 ICLK
0008 901Ah
S12AD
A/D temperature sensor data register
ADTSDR
16
16
2, 3 PCLKB
2 ICLK
0008 901Ch
S12AD
A/D internal reference voltage data register
ADOCDR
16
16
2, 3 PCLKB
2 ICLK
0008 9020h
S12AD
A/D data register 0
ADDR0
16
16
2, 3 PCLKB
2 ICLK
0008 9022h
S12AD
A/D data register 1
ADDR1
16
16
2, 3 PCLKB
2 ICLK
0008 9024h
S12AD
A/D data register 2
ADDR2
16
16
2, 3 PCLKB
2 ICLK
0008 9026h
S12AD
A/D data register 3
ADDR3
16
16
2, 3 PCLKB
2 ICLK
0008 9028h
S12AD
A/D data register 4
ADDR4
16
16
2, 3 PCLKB
2 ICLK
0008 902Ah
S12AD
A/D data register 5
ADDR5
16
16
2, 3 PCLKB
2 ICLK
0008 902Ch
S12AD
A/D data register 6
ADDR6
16
16
2, 3 PCLKB
2 ICLK
0008 902Eh
S12AD
A/D data register 7
ADDR7
16
16
2, 3 PCLKB
2 ICLK
0008 9030h
S12AD
A/D data register 8
ADDR8
16
16
2, 3 PCLKB
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
MTU2a
POE2a
S12ADa
Page 81 of 154
RX630 Group
Table 4.1
Address
4. I/O Registers
List of I/O Registers (Address Order) (23/42)
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
Number of Access States
ICLK PCLK
ICLK PCLK
Related
Function
S12ADa
0008 9032h
S12AD
A/D data register 9
ADDR9
16
16
2, 3 PCLKB
2 ICLK
0008 9034h
S12AD
A/D data register 10
ADDR10
16
16
2, 3 PCLKB
2 ICLK
0008 9036h
S12AD
A/D data register 11
ADDR11
16
16
2, 3 PCLKB
2 ICLK
0008 9038h
S12AD
A/D data register 12
ADDR12
16
16
2, 3 PCLKB
2 ICLK
0008 903Ah
S12AD
A/D data register 13
ADDR13
16
16
2, 3 PCLKB
2 ICLK
0008 903Ch
S12AD
A/D data register 14
ADDR14
16
16
2, 3 PCLKB
2 ICLK
0008 903Eh
S12AD
A/D data register 15
ADDR15
16
16
2, 3 PCLKB
2 ICLK
0008 9040h
S12AD
A/D data register 16
ADDR16
16
16
2, 3 PCLKB
2 ICLK
0008 9042h
S12AD
A/D data register 17
ADDR17
16
16
2, 3 PCLKB
2 ICLK
0008 9044h
S12AD
A/D data register 18
ADDR18
16
16
2, 3 PCLKB
2 ICLK
0008 9046h
S12AD
A/D data register 19
ADDR19
16
16
2, 3 PCLKB
2 ICLK
0008 9048h
S12AD
A/D data register 20
ADDR20
16
16
2, 3 PCLKB
2 ICLK
0008 9060h
S12AD
A/D sampling state register 01
ADSSTR01
16
16
2, 3 PCLKB
2 ICLK
0008 9070h
S12AD
A/D sampling state register 23
ADSSTR23
16
16
2, 3 PCLKB
2 ICLK
0008 9800h
AD
A/D data register A
ADDRA
16
16
2, 3 PCLKB
2 ICLK
0008 9802h
AD
A/D data register B
ADDRB
16
16
2, 3 PCLKB
2 ICLK
0008 9804h
AD
A/D data register C
ADDRC
16
16
2, 3 PCLKB
2 ICLK
0008 9806h
AD
A/D data register D
ADDRD
16
16
2, 3 PCLKB
2 ICLK
0008 9808h
AD
A/D data register E
ADDRE
16
16
2, 3 PCLKB
2 ICLK
0008 980Ah
AD
A/D data register F
ADDRF
16
16
2, 3 PCLKB
2 ICLK
0008 980Ch
AD
A/D data register G
ADDRG
16
16
2, 3 PCLKB
2 ICLK
0008 980Eh
AD
A/D data register H
ADDRH
16
16
2, 3 PCLKB
2 ICLK
0008 9810h
AD
A/D control/status register
ADCSR
8
8
2, 3 PCLKB
2 ICLK
0008 9811h
AD
A/D control register
ADCR
8
8
2, 3 PCLKB
2 ICLK
0008 9812h
AD
A/D control register 2
ADCR2
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 9813h
AD
A/D sampling state register
ADSSTR
8
8
2, 3 PCLKB
0008 981Fh
AD
A/D self-diagnostic register
ADDIAGR
8
8
2, 3 PCLKB
2 ICLK
0008 A000h
SCI0
Serial mode register
SMR
8
8
2, 3 PCLKB
2 ICLK
0008 A001h
SCI0
Bit rate register
BRR
8
8
2, 3 PCLKB
2 ICLK
0008 A002h
SCI0
Serial control register
SCR
8
8
2, 3 PCLKB
2 ICLK
0008 A003h
SCI0
Transmit data register
TDR
8
8
2, 3 PCLKB
2 ICLK
0008 A004h
SCI0
Serial status register
SSR
8
8
2, 3 PCLKB
2 ICLK
0008 A005h
SCI0
Receive data register
RDR
8
8
2, 3 PCLKB
2 ICLK
0008 A006h
SCI0
Smart card mode register
SCMR
8
8
2, 3 PCLKB
2 ICLK
0008 A007h
SCI0
Serial extended mode register
SEMR
8
8
2, 3 PCLKB
2 ICLK
0008 A008h
SCI0
Noise filter setting register
SNFR
8
8
2, 3 PCLKB
2 ICLK
0008 A009h
SCI0
I 2C
mode register 1
SIMR1
8
8
2, 3 PCLKB
2 ICLK
0008 A00Ah
SCI0
I2C mode register 2
SIMR2
8
8
2, 3 PCLKB
2 ICLK
0008 A00Bh
SCI0
I2C mode register 3
SIMR3
8
8
2, 3 PCLKB
2 ICLK
0008 A00Ch
SCI0
I2C status register
SISR
8
8
2, 3 PCLKB
2 ICLK
0008 A00Dh
SCI0
SPI mode register
SPMR
8
8
2, 3 PCLKB
2 ICLK
0008 A020h
SCI1
Serial mode register
SMR
8
8
2, 3 PCLKB
2 ICLK
0008 A021h
SCI1
Bit rate register
BRR
8
8
2, 3 PCLKB
2 ICLK
0008 A022h
SCI1
Serial control register
SCR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 A023h
SCI1
Transmit data register
TDR
8
8
2, 3 PCLKB
0008 A024h
SCI1
Serial status register
SSR
8
8
2, 3 PCLKB
2 ICLK
0008 A025h
SCI1
Receive data register
RDR
8
8
2, 3 PCLKB
2 ICLK
0008 A026h
SCI1
Smart card mode register
SCMR
8
8
2, 3 PCLKB
2 ICLK
0008 A027h
SCI1
Serial extended mode register
SEMR
8
8
2, 3 PCLKB
2 ICLK
0008 A028h
SCI1
Noise filter setting register
SNFR
8
8
2, 3 PCLKB
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
ADb
SCIc,
SCId
Page 82 of 154
RX630 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (24/42)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
ICLK PCLK
ICLK PCLK
0008 A029h
SCI1
I2C mode register 1
0008 A02Ah
SCI1
I2C bus mode register 2
SIMR1
8
8
2, 3 PCLKB
2 ICLK
SIMR2
8
8
2, 3 PCLKB
2 ICLK
0008 A02Bh
SCI1
I2C bus mode register 3
SIMR3
8
8
2, 3 PCLKB
2 ICLK
0008 A02Ch
SCI1
I2C status register
SISR
8
8
2, 3 PCLKB
2 ICLK
0008 A02Dh
SCI1
SPI mode register
SPMR
8
8
2, 3 PCLKB
2 ICLK
0008 A040h
SCI2
Serial mode register
SMR
8
8
2, 3 PCLKB
2 ICLK
0008 A041h
SCI2
Bit rate register
BRR
8
8
2, 3 PCLKB
2 ICLK
0008 A042h
SCI2
Serial control register
SCR
8
8
2, 3 PCLKB
2 ICLK
0008 A043h
SCI2
Transmit data register
TDR
8
8
2, 3 PCLKB
2 ICLK
0008 A044h
SCI2
Serial status register
SSR
8
8
2, 3 PCLKB
2 ICLK
0008 A045h
SCI2
Receive data register
RDR
8
8
2, 3 PCLKB
2 ICLK
0008 A046h
SCI2
Smart card mode register
SCMR
8
8
2, 3 PCLKB
2 ICLK
0008 A047h
SCI2
Serial extended mode register
SEMR
8
8
2, 3 PCLKB
2 ICLK
0008 A048h
SCI2
Noise filter setting register
SNFR
8
8
2, 3 PCLKB
2 ICLK
0008 A049h
SCI2
I 2C
mode register 1
SIMR1
8
8
2, 3 PCLKB
2 ICLK
0008 A04Ah
SCI2
I2C mode register 2
SIMR2
8
8
2, 3 PCLKB
2 ICLK
0008 A04Bh
SCI2
I2C mode register 3
SIMR3
8
8
2, 3 PCLKB
2 ICLK
0008 A04Ch
SCI2
I2C status register
SISR
8
8
2, 3 PCLKB
2 ICLK
0008 A04Dh
SCI2
SPI mode register
SPMR
8
8
2, 3 PCLKB
2 ICLK
0008 A060h
SCI3
Serial mode register
SMR
8
8
2, 3 PCLKB
2 ICLK
0008 A061h
SCI3
Bit rate register
BRR
8
8
2, 3 PCLKB
2 ICLK
0008 A062h
SCI3
Serial control register
SCR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 A063h
SCI3
Transmit data register
TDR
8
8
2, 3 PCLKB
0008 A064h
SCI3
Serial status register
SSR
8
8
2, 3 PCLKB
2 ICLK
0008 A065h
SCI3
Receive data register
RDR
8
8
2, 3 PCLKB
2 ICLK
0008 A066h
SCI3
Smart card mode register
SCMR
8
8
2, 3 PCLKB
2 ICLK
0008 A067h
SCI3
Serial extended mode register
SEMR
8
8
2, 3 PCLKB
2 ICLK
0008 A068h
SCI3
Noise filter setting register
SNFR
8
8
2, 3 PCLKB
2 ICLK
0008 A069h
SCI3
I2C mode register 1
SIMR1
8
8
2, 3 PCLKB
2 ICLK
0008 A06Ah
SCI3
I2 C
mode register 2
SIMR2
8
8
2, 3 PCLKB
2 ICLK
0008 A06Bh
SCI3
I2C mode register 3
SIMR3
8
8
2, 3 PCLKB
2 ICLK
0008 A06Ch
SCI3
I2C status register
SISR
8
8
2, 3 PCLKB
2 ICLK
0008 A06Dh
SCI3
SPI mode register
SPMR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 A080h
SCI4
Serial mode register
SMR
8
8
2, 3 PCLKB
0008 A081h
SCI4
Bit rate register
BRR
8
8
2, 3 PCLKB
2 ICLK
0008 A082h
SCI4
Serial control register
SCR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 A083h
SCI4
Transmit data register
TDR
8
8
2, 3 PCLKB
0008 A084h
SCI4
Serial status register
SSR
8
8
2, 3 PCLKB
2 ICLK
0008 A085h
SCI4
Receive data register
RDR
8
8
2, 3 PCLKB
2 ICLK
0008 A086h
SCI4
Smart card mode register
SCMR
8
8
2, 3 PCLKB
2 ICLK
0008 A087h
SCI4
Serial extended mode register
SEMR
8
8
2, 3 PCLKB
2 ICLK
0008 A088h
SCI4
Noise filter setting register
SNFR
8
8
2, 3 PCLKB
2 ICLK
0008 A089h
SCI4
I2C mode register 1
SIMR1
8
8
2, 3 PCLKB
2 ICLK
0008 A08Ah
SCI4
I2C mode register 2
SIMR2
8
8
2, 3 PCLKB
2 ICLK
0008 A08Bh
SCI4
I2 C
SIMR3
8
8
2, 3 PCLKB
2 ICLK
0008 A08Ch
SCI4
I2C status register
SISR
8
8
2, 3 PCLKB
2 ICLK
0008 A08Dh
SCI4
SPI mode register
SPMR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
mode register 3
0008 A0A0h
SCI5
Serial mode register
SMR
8
8
2, 3 PCLKB
0008 A0A1h
SCI5
Bit rate register
BRR
8
8
2, 3 PCLKB
2 ICLK
0008 A0A2h
SCI5
Serial control register
SCR
8
8
2, 3 PCLKB
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
SCIc,
SCId
Page 83 of 154
RX630 Group
Table 4.1
Address
4. I/O Registers
List of I/O Registers (Address Order) (25/42)
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
Number of Access States
ICLK PCLK
ICLK PCLK
0008 A0A3h
SCI5
Transmit data register
TDR
8
8
2, 3 PCLKB
2 ICLK
0008 A0A4h
SCI5
Serial status register
SSR
8
8
2, 3 PCLKB
2 ICLK
0008 A0A5h
SCI5
Receive data register
RDR
8
8
2, 3 PCLKB
2 ICLK
0008 A0A6h
SCI5
Smart card mode register
SCMR
8
8
2, 3 PCLKB
2 ICLK
0008 A0A7h
SCI5
Serial extended mode register
SEMR
8
8
2, 3 PCLKB
2 ICLK
0008 A0A8h
SCI5
Noise filter setting register
SNFR
8
8
2, 3 PCLKB
2 ICLK
0008 A0A9h
SCI5
I2C mode register 1
SIMR1
8
8
2, 3 PCLKB
2 ICLK
0008 A0AAh
SCI5
I2C
mode register 2
SIMR2
8
8
2, 3 PCLKB
2 ICLK
0008 A0ABh
SCI5
I2C mode register 3
SIMR3
8
8
2, 3 PCLKB
2 ICLK
0008 A0ACh
SCI5
I2C status register
SISR
8
8
2, 3 PCLKB
2 ICLK
0008 A0ADh
SCI5
SPI mode register
SPMR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 A0C0h
SCI6
Serial mode register
SMR
8
8
2, 3 PCLKB
0008 A0C1h
SCI6
Bit rate register
BRR
8
8
2, 3 PCLKB
2 ICLK
0008 A0C2h
SCI6
Serial control register
SCR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 A0C3h
SCI6
Transmit data register
TDR
8
8
2, 3 PCLKB
0008 A0C4h
SCI6
Serial status register
SSR
8
8
2, 3 PCLKB
2 ICLK
0008 A0C5h
SCI6
Receive data register
RDR
8
8
2, 3 PCLKB
2 ICLK
0008 A0C6h
SCI6
Smart card mode register
SCMR
8
8
2, 3 PCLKB
2 ICLK
0008 A0C7h
SCI6
Serial extended mode register
SEMR
8
8
2, 3 PCLKB
2 ICLK
0008 A0C8h
SCI6
Noise filter setting register
SNFR
8
8
2, 3 PCLKB
2 ICLK
0008 A0C9h
SCI6
I2C mode register 1
SIMR1
8
8
2, 3 PCLKB
2 ICLK
0008 A0CAh
SCI6
I2C mode register 2
SIMR2
8
8
2, 3 PCLKB
2 ICLK
0008 A0CBh
SCI6
I2 C
SIMR3
8
8
2, 3 PCLKB
2 ICLK
0008 A0CCh
SCI6
I2C status register
SISR
8
8
2, 3 PCLKB
2 ICLK
0008 A0CDh
SCI6
SPI mode register
SPMR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
mode register 3
0008 A0E0h
SCI7
Serial mode register
SMR
8
8
2, 3 PCLKB
0008 A0E1h
SCI7
Bit rate register
BRR
8
8
2, 3 PCLKB
2 ICLK
0008 A0E2h
SCI7
Serial control register
SCR
8
8
2, 3 PCLKB
2 ICLK
0008 A0E3h
SCI7
Transmit data register
TDR
8
8
2, 3 PCLKB
2 ICLK
0008 A0E4h
SCI7
Serial status register
SSR
8
8
2, 3 PCLKB
2 ICLK
0008 A0E5h
SCI7
Receive data register
RDR
8
8
2, 3 PCLKB
2 ICLK
0008 A0E6h
SCI7
Smart card mode register
SCMR
8
8
2, 3 PCLKB
2 ICLK
0008 A0E7h
SCI7
Serial extended mode register
SEMR
8
8
2, 3 PCLKB
2 ICLK
0008 A0E8h
SCI7
Noise filter setting register
SNFR
8
8
2, 3 PCLKB
2 ICLK
0008 A0E9h
SCI7
I2C mode register 1
SIMR1
8
8
2, 3 PCLKB
2 ICLK
0008 A0EAh
SCI7
I2C mode register 2
SIMR2
8
8
2, 3 PCLKB
2 ICLK
0008 A0EBh
SCI7
I2C
0008 A0ECh
SCI7
I2C status register
mode register 3
SIMR3
8
8
2, 3 PCLKB
2 ICLK
SISR
8
8
2, 3 PCLKB
2 ICLK
0008 A0EDh
SCI7
SPI mode register
SPMR
8
8
2, 3 PCLKB
2 ICLK
0008 A100h
SCI8
Serial mode register
SMR
8
8
2, 3 PCLKB
2 ICLK
0008 A101h
SCI8
Bit rate register
BRR
8
8
2, 3 PCLKB
2 ICLK
0008 A102h
SCI8
Serial control register
SCR
8
8
2, 3 PCLKB
2 ICLK
0008 A103h
SCI8
Transmit data register
TDR
8
8
2, 3 PCLKB
2 ICLK
0008 A104h
SCI8
Serial status register
SSR
8
8
2, 3 PCLKB
2 ICLK
0008 A105h
SCI8
Receive data register
RDR
8
8
2, 3 PCLKB
2 ICLK
0008 A106h
SCI8
Smart card mode register
SCMR
8
8
2, 3 PCLKB
2 ICLK
0008 A107h
SCI8
Serial extended mode register
SEMR
8
8
2, 3 PCLKB
2 ICLK
0008 A108h
SCI8
Noise filter setting register
SNFR
8
8
2, 3 PCLKB
2 ICLK
0008 A109h
SCI8
I2C mode register 1
SIMR1
8
8
2, 3 PCLKB
2 ICLK
0008 A10Ah
SCI8
I2C mode register 2
SIMR2
8
8
2, 3 PCLKB
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
SCIc,
SCId
Page 84 of 154
RX630 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (26/42)
Register
Symbol
Number
of Bits
Access
Size
Number of Access States
Address
Module
Symbol
Register Name
0008 A10Bh
SCI8
I2C mode register 3
SIMR3
8
8
2, 3 PCLKB
2 ICLK
0008 A10Ch
SCI8
I2C status register
SISR
8
8
2, 3 PCLKB
2 ICLK
ICLK PCLK
ICLK PCLK
0008 A10Dh
SCI8
SPI mode register
SPMR
8
8
2, 3 PCLKB
2 ICLK
0008 A120h
SCI9
Serial mode register
SMR
8
8
2, 3 PCLKB
2 ICLK
0008 A121h
SCI9
Bit rate register
BRR
8
8
2, 3 PCLKB
2 ICLK
0008 A122h
SCI9
Serial control register
SCR
8
8
2, 3 PCLKB
2 ICLK
0008 A123h
SCI9
Transmit data register
TDR
8
8
2, 3 PCLKB
2 ICLK
0008 A124h
SCI9
Serial status register
SSR
8
8
2, 3 PCLKB
2 ICLK
0008 A125h
SCI9
Receive data register
RDR
8
8
2, 3 PCLKB
2 ICLK
0008 A126h
SCI9
Smart card mode register
SCMR
8
8
2, 3 PCLKB
2 ICLK
0008 A127h
SCI9
Serial extended mode register
SEMR
8
8
2, 3 PCLKB
2 ICLK
0008 A128h
SCI9
Noise filter setting register
SNFR
8
8
2, 3 PCLKB
2 ICLK
0008 A129h
SCI9
I2C mode register 1
SIMR1
8
8
2, 3 PCLKB
2 ICLK
0008 A12Ah
SCI9
I2C mode register 2
SIMR2
8
8
2, 3 PCLKB
2 ICLK
0008 A12Bh
SCI9
I2 C
0008 A12Ch
SCI9
I2C status register
mode register 3
SIMR3
8
8
2, 3 PCLKB
2 ICLK
SISR
8
8
2, 3 PCLKB
2 ICLK
0008 A12Dh
SCI9
SPI mode register
SPMR
8
8
2, 3 PCLKB
2 ICLK
0008 A140h
SCI10
Serial mode register
SMR
8
8
2, 3 PCLKB
2 ICLK
0008 A141h
SCI10
Bit rate register
BRR
8
8
2, 3 PCLKB
2 ICLK
0008 A142h
SCI10
Serial control register
SCR
8
8
2, 3 PCLKB
2 ICLK
0008 A143h
SCI10
Transmit data register
TDR
8
8
2, 3 PCLKB
2 ICLK
0008 A144h
SCI10
Serial status register
SSR
8
8
2, 3 PCLKB
2 ICLK
0008 A145h
SCI10
Receive data register
RDR
8
8
2, 3 PCLKB
2 ICLK
0008 A146h
SCI10
Smart card mode register
SCMR
8
8
2, 3 PCLKB
2 ICLK
0008 A147h
SCI10
Serial extended mode register
SEMR
8
8
2, 3 PCLKB
2 ICLK
0008 A148h
SCI10
Noise filter setting register
SNFR
8
8
2, 3 PCLKB
2 ICLK
0008 A149h
SCI10
I2C mode register 1
SIMR1
8
8
2, 3 PCLKB
2 ICLK
0008 A14Ah
SCI10
I2C mode register 2
SIMR2
8
8
2, 3 PCLKB
2 ICLK
0008 A14Bh
SCI10
I2C mode register 3
SIMR3
8
8
2, 3 PCLKB
2 ICLK
0008 A14Ch
SCI10
I2 C
SISR
8
8
2, 3 PCLKB
2 ICLK
0008 A14Dh
SCI10
SPI mode register
SPMR
8
8
2, 3 PCLKB
2 ICLK
status register
0008 A160h
SCI11
Serial mode register
SMR
8
8
2, 3 PCLKB
2 ICLK
0008 A161h
SCI11
Bit rate register
BRR
8
8
2, 3 PCLKB
2 ICLK
0008 A162h
SCI11
Serial control register
SCR
8
8
2, 3 PCLKB
2 ICLK
0008 A163h
SCI11
Transmit data register
TDR
8
8
2, 3 PCLKB
2 ICLK
0008 A164h
SCI11
Serial status register
SSR
8
8
2, 3 PCLKB
2 ICLK
0008 A165h
SCI11
Receive data register
RDR
8
8
2, 3 PCLKB
2 ICLK
0008 A166h
SCI11
Smart card mode register
SCMR
8
8
2, 3 PCLKB
2 ICLK
0008 A167h
SCI11
Serial extended mode register
SEMR
8
8
2, 3 PCLKB
2 ICLK
0008 A168h
SCI11
Noise filter setting register
SNFR
8
8
2, 3 PCLKB
2 ICLK
0008 A169h
SCI11
I 2C
mode register 1
SIMR1
8
8
2, 3 PCLKB
2 ICLK
0008 A16Ah
SCI11
I2C mode register 2
SIMR2
8
8
2, 3 PCLKB
2 ICLK
0008 A16Bh
SCI11
I2C mode register 3
SIMR3
8
8
2, 3 PCLKB
2 ICLK
0008 A16Ch
SCI11
I2C status register
SISR
8
8
2, 3 PCLKB
2 ICLK
0008 A16Dh
SCI11
SPI mode register
SPMR
8
8
2, 3 PCLKB
2 ICLK
0008 A800h
IEB
IEBus control register
IECTR
8
8
3, 4 PCLKB
2, 3 ICLK
0008 A801h
IEB
IEBus command register
IECMR
8
8
3, 4 PCLKB
2, 3 ICLK
0008 A802h
IEB
IEBus master control register
IEMCR
8
8
3, 4 PCLKB
2, 3 ICLK
0008 A803h
IEB
IEBus master unit address register 1
IEAR1
8
8
3, 4 PCLKB
2, 3 ICLK
0008 A804h
IEB
IEBus master unit address register 2
IEAR2
8
8
3, 4 PCLKB
2, 3 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
SCIc,
SCId
IEB
Page 85 of 154
RX630 Group
Table 4.1
Address
4. I/O Registers
List of I/O Registers (Address Order) (27/42)
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
Number of Access States
ICLK PCLK
ICLK PCLK
0008 A805h
IEB
IEBus slave address setting register 1
IESA1
8
8
3, 4 PCLKB
2, 3 ICLK
0008 A806h
IEB
IEBus slave address setting register 2
IESA2
8
8
3, 4 PCLKB
2, 3 ICLK
0008 A807h
IEB
IEBus transmit message length register
IETBFL
8
8
3, 4 PCLKB
2, 3 ICLK
0008 A809h
IEB
IEBus reception master address register 1
IEMA1
8
8
3, 4 PCLKB
2, 3 ICLK
0008 A80Ah
IEB
IEBus reception master address register 2
IEMA2
8
8
3, 4 PCLKB
2, 3 ICLK
0008 A80Bh
IEB
IEBus receive control field register
IERCTL
8
8
3, 4 PCLKB
2, 3 ICLK
0008 A80Ch
IEB
IEBus receive message length register
IERBFL
8
8
3, 4 PCLKB
2, 3 ICLK
0008 A80Eh
IEB
IEBus lock address register 1
IELA1
8
8
3, 4 PCLKB
2, 3 ICLK
0008 A80Fh
IEB
IEBus lock address register 2
IELA2
8
8
3, 4 PCLKB
2, 3 ICLK
0008 A810h
IEB
IEBus general flag register
IEFLG
8
8
3, 4 PCLKB
2, 3 ICLK
0008 A811h
IEB
IEBus transmit status register
IETSR
8
8
3, 4 PCLKB
2, 3 ICLK
0008 A812h
IEB
IEBus transmit interrupt enable register
IEIET
8
8
3, 4 PCLKB
2, 3 ICLK
0008 A814h
IEB
IEBus receive status register
IERSR
8
8
3, 4 PCLKB
2, 3 ICLK
0008 A815h
IEB
IEBus receive interrupt enable register
IEIER
8
8
3, 4 PCLKB
2, 3 ICLK
0008 A818h
IEB
IEBus clock select register
IECKSR
8
8
3, 4 PCLKB
2, 3 ICLK
0008 A900h to
0008 A91Fh
IEB
IEBus transmit data buffer register 001 to 032
IETB001 to 032
8
8
3, 4 PCLKB
2, 3 ICLK
0008 AA00h to
0008 AA1Fh
IEB
IEBus receive data buffer register 001 to 032
IERB001 to 032
8
8
3, 4 PCLKB
2, 3 ICLK
0008 B300h
SCI12
Serial mode register
SMR12
8
8
3, 4 PCLKB
2, 3 ICLK
0008 B301h
SCI12
Bit rate register
BRR12
8
8
3, 4 PCLKB
2, 3 ICLK
0008 B302h
SCI12
Serial control register
SCR12
8
8
2, 3 PCLKB
2 ICLK
0008 B303h
SCI12
Transmit data register
TDR12
8
8
2, 3 PCLKB
2 ICLK
0008 B304h
SCI12
Serial status register
SSR12
8
8
2, 3 PCLKB
2 ICLK
0008 B305h
SCI12
Receive data register
RDR12
8
8
2, 3 PCLKB
2 ICLK
0008 B306h
SCI12
Smart card mode register
SCMR12
8
8
2, 3 PCLKB
2 ICLK
0008 B307h
SCI12
Serial extended mode register
SEMR12
8
8
2, 3 PCLKB
2 ICLK
0008 B308h
SCI12
Noise filter setting register
SNFR12
8
8
2, 3 PCLKB
2 ICLK
0008 B309h
SCI12
I2 C
mode register 1
SIMR112
8
8
2, 3 PCLKB
2 ICLK
0008 B30Ah
SCI12
I2C mode register 2
SIMR212
8
8
2, 3 PCLKB
2 ICLK
0008 B30Bh
SCI12
I2C mode register 3
SIMR312
8
8
2, 3 PCLKB
2 ICLK
0008 B30Ch
SCI12
I2C status register
SIS12
8
8
2, 3 PCLKB
2 ICLK
0008 B30Dh
SCI12
SPI mode register
SPMR
8
8
2, 3 PCLKB
2 ICLK
0008 B320h
SCI12
Extended serial module enable register
ESMER
8
8
2, 3 PCLKB
2 ICLK
0008 B321h
SCI12
Control register 0
CR0
8
8
2, 3 PCLKB
2 ICLK
0008 B322h
SCI12
Control register 1
CR1
8
8
2, 3 PCLKB
2 ICLK
0008 B323h
SCI12
Control register 2
CR2
8
8
2, 3 PCLKB
2 ICLK
0008 B324h
SCI12
Control register 3
CR3
8
8
2, 3 PCLKB
2 ICLK
0008 B325h
SCI12
Port control register
PCR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 B326h
SCI12
Interrupt control register
ICR
8
8
2, 3 PCLKB
0008 B327h
SCI12
Status register
STR
8
8
2, 3 PCLKB
2 ICLK
0008 B328h
SCI12
Status clear register
STCR
8
8
2, 3 PCLKB
2 ICLK
0008 B329h
SCI12
Control field 0 data register
CF0DR
8
8
2, 3 PCLKB
2 ICLK
0008 B32Ah
SCI12
Control field 0 compare enable register
CF0CR
8
8
2, 3 PCLKB
2 ICLK
0008 B32Bh
SCI12
Control field 0 receive data register
CF0RR
8
8
2, 3 PCLKB
2 ICLK
0008 B32Ch
SCI12
Primary control field 1 data register
PCF1DR
8
8
2, 3 PCLKB
2 ICLK
0008 B32Dh
SCI12
Secondary control field 1 data register
SCF1DR
8
8
2, 3 PCLKB
2 ICLK
0008 B32Eh
SCI12
Control field 1 compare enable register
CF1CR
8
8
2, 3 PCLKB
2 ICLK
0008 B32Fh
SCI12
Control field 1 receive data register
CF1RR
8
8
2, 3 PCLKB
2 ICLK
0008 B330h
SCI12
Timer control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 B331h
SCI12
Timer mode register
TMR
8
8
2, 3 PCLKB
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
IEB
SCIc, SCId
Page 86 of 154
RX630 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (28/42)
Number of Access States
Number
of Bits
Access
Size
ICLK PCLK
ICLK PCLK
Related
Function
TPRE
8
8
2, 3 PCLKB
2 ICLK
I/O Ports
TCNT
8
8
2, 3 PCLKB
2 ICLK
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
PORT2
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
PORT3
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C004h
PORT4
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C005h
PORT5
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C006h
PORT6
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C007h
PORT7
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C008h
PORT8
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C009h
PORT9
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C00Ah
PORTA
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C00Bh
PORTB
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C00Ch
PORTC
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C00Dh
PORTD
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C00Eh
PORTE
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C00Fh
PORTF
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C010h
PORTG
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C011h
PORTH
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C012h
PORTJ
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C013h
PORTK
Port direction register
PDR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
Address
Module
Symbol
Register Name
Register
Symbol
0008 B332h
SCI12
Timer prescaler register
0008 B333h
SCI12
Timer count register
0008 C000h
PORT0
0008 C001h
PORT1
0008 C002h
0008 C003h
0008 C014h
PORTL
Port direction register
PDR
8
8
2, 3 PCLKB
0008 C020h
PORT0
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C021h
PORT1
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C022h
PORT2
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C023h
PORT3
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C024h
PORT4
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C025h
PORT5
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 C026h
PORT6
Port output data register
PODR
8
8
2, 3 PCLKB
0008 C027h
PORT7
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C028h
PORT8
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C029h
PORT9
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C02Ah
PORTA
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C02Bh
PORTB
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C02Ch
PORTC
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C02Dh
PORTD
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C02Eh
PORTE
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C02Fh
PORTF
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C030h
PORTG
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C031h
PORTH
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C032h
PORTJ
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C033h
PORTK
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C034h
PORTL
Port output data register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C040h
PORT0
Port input data register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C041h
PORT1
Port input data register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C042h
PORT2
Port input data register
PIDR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 C043h
PORT3
Port input data register
PIDR
8
8
2, 3 PCLKB
0008 C044h
PORT4
Port input data register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C045h
PORT5
Port input data register
PIDR
8
8
2, 3 PCLKB
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 87 of 154
RX630 Group
Table 4.1
Address
4. I/O Registers
List of I/O Registers (Address Order) (29/42)
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
Number of Access States
ICLK PCLK
ICLK PCLK
Related
Function
I/O Ports
0008 C046h
PORT6
Port input data register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C047h
PORT7
Port input data register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C048h
PORT8
Port input data register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C049h
PORT9
Port input data register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C04Ah
PORTA
Port input data register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C04Bh
PORTB
Port input data register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C04Ch
PORTC
Port input data register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C04Dh
PORTD
Port input data register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C04Eh
PORTE
Port input data register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C04Fh
PORTF
Port input data register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C050h
PORTG
Port input data register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C051h
PORTH
Port input data register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C052h
PORTJ
Port input data register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C053h
PORTK
Port input data register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C054h
PORTL
Port input data register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C060h
PORT0
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C061h
PORT1
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C062h
PORT2
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C063h
PORT3
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C064h
PORT4
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C065h
PORT5
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C066h
PORT6
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 C067h
PORT7
Port mode register
PMR
8
8
2, 3 PCLKB
0008 C068h
PORT8
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C069h
PORT9
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C06Ah
PORTA
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C06Bh
PORTB
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C06Ch
PORTC
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C06Dh
PORTD
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C06Eh
PORTE
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C06Fh
PORTF
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C070h
PORTG
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C071h
PORTH
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 C072h
PORTJ
Port mode register
PMR
8
8
2, 3 PCLKB
0008 C073h
PORTK
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C074h
PORTL
Port mode register
PMR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 C080h
PORT0
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
0008 C081h
PORT0
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C082h
PORT1
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C083h
PORT1
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
2 ICLK
0008 C084h
PORT2
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
0008 C085h
PORT2
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C086h
PORT3
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C087h
PORT3
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
2 ICLK
0008 C088h
PORT4
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
0008 C089h
PORT4
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C08Ah
PORT5
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C08Bh
PORT5
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C08Ch
PORT6
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C08Dh
PORT6
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 88 of 154
RX630 Group
Table 4.1
Address
4. I/O Registers
List of I/O Registers (Address Order) (30/42)
Module
Symbol
Register Name
Register
Symbol
Number of Access States
Number
of Bits
Access
Size
ICLK PCLK
ICLK PCLK
Related
Function
I/O Ports
0008 C08Eh
PORT7
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C08Fh
PORT7
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C090h
PORT8
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C091h
PORT8
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
2 ICLK
0008 C092h
PORT9
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
0008 C093h
PORT9
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C094h
PORTA
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C095h
PORTA
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C096h
PORTB
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C097h
PORTB
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C098h
PORTC
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C099h
PORTC
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C09Ah
PORTD
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C09Bh
PORTD
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C09Ch
PORTE
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C09Dh
PORTE
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C09Eh
PORTF
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C09Fh
PORTF
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C0A0h
PORTG
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C0A1h
PORTG
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C0A3h
PORTH
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C0A4h
PORTJ
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C0A5h
PORTJ
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C0A6h
PORTK
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C0A7h
PORTK
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
2 ICLK
0008 C0A8h
PORTL
Open drain control register 0
ODR0
8
8, 16
2, 3 PCLKB
0008 C0A9h
PORTL
Open drain control register 1
ODR1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C0C0h
PORT0
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0C1h
PORT1
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0C2h
PORT2
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0C3h
PORT3
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0C4h
PORT4
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0C5h
PORT5
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0C6h
PORT6
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0C7h
PORT7
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0C8h
PORT8
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 C0C9h
PORT9
Pull-up control register
PCR
8
8
2, 3 PCLKB
0008 C0CAh
PORTA
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0CBh
PORTB
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0CCh
PORTC
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 C0CDh
PORTD
Pull-up control register
PCR
8
8
2, 3 PCLKB
0008 C0CEh
PORTE
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0CFh
PORTF
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0D0h
PORTG
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 C0D1h
PORTH
Pull-up control register
PCR
8
8
2, 3 PCLKB
0008 C0D2h
PORTJ
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0D3h
PORTK
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0D4h
PORTL
Pull-up control register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0E0h
PORT0
Driving ability control register
DSCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0E2h
PORT2
Driving ability control register
DSCR
8
8
2, 3 PCLKB
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 89 of 154
RX630 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (31/42)
Number of Access States
Number
of Bits
Access
Size
ICLK PCLK
ICLK PCLK
Related
Function
DSCR
8
8
2, 3 PCLKB
2 ICLK
I/O Ports
DSCR
8
8
2, 3 PCLKB
2 ICLK
Driving ability control register
DSCR
8
8
2, 3 PCLKB
2 ICLK
Driving ability control register
DSCR
8
8
2, 3 PCLKB
2 ICLK
PORTA
Driving ability control register
DSCR
8
8
2, 3 PCLKB
2 ICLK
PORTB
Driving ability control register
DSCR
8
8
2, 3 PCLKB
2 ICLK
PORTC
Driving ability control register
DSCR
8
8
2, 3 PCLKB
2 ICLK
Address
Module
Symbol
Register Name
Register
Symbol
0008 C0E5h
PORT5
Driving ability control register
0008 C0E6h
PORT6
Driving ability control register
0008 C0E7h
PORT7
0008 C0E9h
PORT9
0008 C0EAh
0008 C0EBh
0008 C0ECh
0008 C0EDh
PORTD
Driving ability control register
DSCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0EEh
PORTE
Driving ability control register
DSCR
8
8
2, 3 PCLKB
2 ICLK
0008 C0F0h
PORTG
Driving ability control register
DSCR
8
8
2, 3 PCLKB
2 ICLK
0008 C100h
MPC
CS output enable register
PFCSE
8
8
2, 3 PCLKB
2 ICLK
0008 C102h
MPC
CS output pin select register 0
PFCSS0
8
8
2, 3 PCLKB
2 ICLK
0008 C103h
MPC
CS output pin select register 1
PFCSS1
8
8
2, 3 PCLKB
2 ICLK
0008 C104h
MPC
Address output enable register 0
PFAOE0
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C105h
MPC
Address output enable register 1
PFAOE1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C106h
MPC
External bus control register 0
PFBCR0
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C107h
MPC
External bus control register 1
PFBCR1
8
8, 16
2, 3 PCLKB
2 ICLK
0008 C114h
MPC
USB0 control register
PFUSB0
8
8
2, 3 PCLKB
2 ICLK
0008 C11Fh
MPC
Write-protect register
PWPR
8
8
2, 3 PCLKB
2 ICLK
0008 C140h
MPC
P00 pin function control register
P00PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C141h
MPC
P01 pin function control register
P01PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C142h
MPC
P02 pin function control register
P02PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C143h
MPC
P03 pin function control register
P03PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C145h
MPC
P05 pin function control register
P05PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C147h
MPC
P07 pin function control register
P07PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C148h
MPC
P10 pin function control register
P10PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C149h
MPC
P11 pin function control register
P11PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C14Ah
MPC
P12 pin function control register
P12PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C14Bh
MPC
P13 pin function control register
P13PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C14Ch
MPC
P14 pin function control register
P14PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C14Dh
MPC
P15 pin function control register
P15PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C14Eh
MPC
P16 pin function control register
P16PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C14Fh
MPC
P17 pin function control register
P17PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C150h
MPC
P20 pin function control register
P20PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C151h
MPC
P21 pin function control register
P21PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C152h
MPC
P22 pin function control register
P22PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C153h
MPC
P23 pin function control register
P23PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C154h
MPC
P24 pin function control register
P24PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C155h
MPC
P25 pin function control register
P25PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C156h
MPC
P26 pin function control register
P26PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C157h
MPC
P27 pin function control register
P27PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C158h
MPC
P30 pin function control register
P30PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C159h
MPC
P31 pin function control register
P31PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C15Ah
MPC
P32 pin function control register
P32PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C15Bh
MPC
P33 pin function control register
P33PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C15Ch
MPC
P34 pin function control register
P34PFS
8
8
0008 C160h
MPC
P40 pin function control register
P40PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C161h
MPC
P41 pin function control register
P41PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C162h
MPC
P42 pin function control register
P42PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C163h
MPC
P43 pin function control register
P43PFS
8
8
2, 3 PCLKB
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
2, 3 PCLKB
MPC
2 ICLK
Page 90 of 154
RX630 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (32/42)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
ICLK PCLK
ICLK PCLK
0008 C164h
MPC
P44 pin function control register
P44PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C165h
MPC
P45 pin function control register
P45PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C166h
MPC
P46 pin function control register
P46PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C167h
MPC
P47 pin function control register
P47PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C168h
MPC
P50 pin function control register
P50PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C169h
MPC
P51 pin function control register
P51PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C16Ah
MPC
P52 pin function control register
P52PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C16Ch
MPC
P54 pin function control register
P54PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C16Dh
MPC
P55 pin function control register
P55PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C16Eh
MPC
P56 pin function control register
P56PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C170h
MPC
P60 pin function control register
P60PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C171h
MPC
P61 pin function control register
P61PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C176h
MPC
P66 pin function control register
P66PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C177h
MPC
P67 pin function control register
P67PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C178h
MPC
P70 pin function control register
P70PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C17Bh
MPC
P73 pin function control register
P73PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C17Ch
MPC
P74 pin function control register
P74PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C17Dh
MPC
P75 pin function control register
P75PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C17Eh
MPC
P76 pin function control register
P76PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C17Fh
MPC
P77 pin function control register
P77PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C180h
MPC
P80 pin function control register
P80PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C181h
MPC
P81 pin function control register
P81PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C182h
MPC
P82 pin function control register
P82PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C183h
MPC
P83 pin function control register
P83PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C186h
MPC
P86 pin function control register
P86PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C187h
MPC
P87 pin function control register
P87PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C188h
MPC
P90 pin function control register
P90PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C189h
MPC
P91 pin function control register
P91PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C18Ah
MPC
P92 pin function control register
P92PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C18Bh
MPC
P93 pin function control register
P93PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C190h
MPC
PA0 pin function control register
PA0PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C191h
MPC
PA1 pin function control register
PA1PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C192h
MPC
PA2 pin function control register
PA2PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C193h
MPC
PA3 pin function control register
PA3PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C194h
MPC
PA4 pin function control register
PA4PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C195h
MPC
PA5 pin function control register
PA5PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C196h
MPC
PA6 pin function control register
PA6PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C197h
MPC
PA7 pin function control register
PA7PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C198h
MPC
PB0 pin function control register
PB0PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C199h
MPC
PB1 pin function control register
PB1PFS
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 C19Ah
MPC
PB2 pin function control register
PB2PFS
8
8
2, 3 PCLKB
0008 C19Bh
MPC
PB3 pin function control register
PB3PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C19Ch
MPC
PB4 pin function control register
PB4PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C19Dh
MPC
PB5 pin function control register
PB5PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C19Eh
MPC
PB6 pin function control register
PB6PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C19Fh
MPC
PB7 pin function control register
PB7PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1A0h
MPC
PC0 pin function control register
PC0PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1A1h
MPC
PC1 pin function control register
PC1PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1A2h
MPC
PC2 pin function control register
PC2PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1A3h
MPC
PC3 pin function control register
PC3PFS
8
8
2, 3 PCLKB
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
MPC
Page 91 of 154
RX630 Group
Table 4.1
Address
4. I/O Registers
List of I/O Registers (Address Order) (33/42)
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
Number of Access States
ICLK PCLK
ICLK PCLK
0008 C1A4h
MPC
PC4 pin function control register
PC4PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1A5h
MPC
PC5 pin function control register
PC5PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1A6h
MPC
PC6 pin function control register
PC6PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1A7h
MPC
PC7 pin function control register
PC7PFS
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 C1A8h
MPC
PD0 pin function control register
PD0PFS
8
8
2, 3 PCLKB
0008 C1A9h
MPC
PD1 pin function control register
PD1PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1AAh
MPC
PD2 pin function control register
PD2PFS
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 C1ABh
MPC
PD3 pin function control register
PD3PFS
8
8
2, 3 PCLKB
0008 C1ACh
MPC
PD4 pin function control register
PD4PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1ADh
MPC
PD5 pin function control register
PD5PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1AEh
MPC
PD6 pin function control register
PD6PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1AFh
MPC
PD7 pin function control register
PD7PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1B0h
MPC
PE0 pin function control register
PE0PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1B1h
MPC
PE1 pin function control register
PE1PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1B2h
MPC
PE2 pin function control register
PE2PFS
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 C1B3h
MPC
PE3 pin function control register
PE3PFS
8
8
2, 3 PCLKB
0008 C1B4h
MPC
PE4 pin function control register
PE4PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1B5h
MPC
PE5 pin function control register
PE5PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1B6h
MPC
PE6 pin function control register
PE6PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1B7h
MPC
PE7 pin function control register
PE7PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1B8h
MPC
PF0 pin function control register
PF0PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1B9h
MPC
PF1 pin function control register
PF1PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1BAh
MPC
PF2 pin function control register
PF2PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1BDh
MPC
PF5 pin function control register
PF5PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1D3h
MPC
PJ3 pin function control register
PJ3PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1DAh
MPC
PK2 pin function control register
PK2PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1DBh
MPC
PK3 pin function control register
PK3PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1DCh
MPC
PK4 pin function control register
PK4PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1DDh
MPC
PK5 pin function control register
PK5PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C280h
SYSTEM
Deep standby control register
DPSBYCR
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C282h
SYSTEM
Deep standby interrupt enable register 0
DPSIER0
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C283h
SYSTEM
Deep standby interrupt enable register 1
DPSIER1
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C284h
SYSTEM
Deep standby interrupt enable register 2
DPSIER2
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C285h
SYSTEM
Deep standby interrupt enable register 3
DPSIER3
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C286h
SYSTEM
Deep standby interrupt flag register 0
DPSIFR0
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C287h
SYSTEM
Deep standby interrupt flag register 1
DPSIFR1
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C288h
SYSTEM
Deep standby interrupt flag register 2
DPSIFR2
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C289h
SYSTEM
Deep standby interrupt flag register 3
DPSIFR3
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C28Ah
SYSTEM
Deep standby interrupt edge register 0
DPSIEGR0
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C28Bh
SYSTEM
Deep standby interrupt edge register 1
DPSIEGR1
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C28Ch
SYSTEM
Deep standby interrupt edge register 2
DPSIEGR2
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C28Dh
SYSTEM
Deep standby interrupt edge register 3
DPSIEGR3
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C290h
SYSTEM
Reset status register 0
RSTSR0
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C291h
SYSTEM
Reset status register 1
RSTSR1
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C293h
SYSTEM
Main clock oscillator forced oscillation control
register
MOFCR
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C294h
SYSTEM
High-speed on-chip oscillator power supply
control register
HOCOPCR
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C296h
FLASH
Flash write erase protection register
FWEPROR
8
8
4, 5 PCLKB
2, 3 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
MPC
Low Power
Consumption
Resets
Clock
Generation
Circuit
ROM
Page 92 of 154
RX630 Group
Table 4.1
Address
4. I/O Registers
List of I/O Registers (Address Order) (34/42)
Module
Symbol
Register Name
Register
Symbol
Number of Access States
Number
of Bits
Access
Size
ICLK PCLK
ICLK PCLK
0008 C297h
SYSTEM
Voltage monitoring circuit control register
LVCMPCR
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C298h
SYSTEM
Voltage detection level select register
LVDLVLR
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C29Ah
SYSTEM
Voltage monitoring 1 circuit control register 0
LVD1CR0
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C29Bh
SYSTEM
Voltage monitoring 2 circuit control register 0
LVD2CR0
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C2A0h to
0008 C2BFh
SYSTEM
Deep standby backup register 0 to 31
DPSBKR0 to
31
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C300h
ICU
Group 0 interrupt source register
GRP00
32
32
1, 2 PCLKB
2 ICLK
0008 C304h
ICU
Group 1 interrupt source register
GRP01
32
32
1, 2 PCLKB
2 ICLK
0008 C308h
ICU
Group 2 interrupt source register
GRP02
32
32
1, 2 PCLKB
2 ICLK
0008 C30Ch
ICU
Group 3 interrupt source register
GRP03
32
32
1, 2 PCLKB
2 ICLK
0008 C310h
ICU
Group 4 interrupt source register
GRP04
32
32
1, 2 PCLKB
2 ICLK
0008 C314h
ICU
Group 5 interrupt source register
GRP05
32
32
1, 2 PCLKB
2 ICLK
0008 C318h
ICU
Group 6 interrupt source register
GRP06
32
32
1, 2 PCLKB
2 ICLK
0008 C330h
ICU
Group 12 interrupt source register
GRP12
32
32
1, 2 PCLKB
2 ICLK
0008 C340h
ICU
Group 0 interrupt enable register
GEN00
32
32
1, 2 PCLKB
2 ICLK
0008 C344h
ICU
Group 1 interrupt enable register
GEN01
32
32
1, 2 PCLKB
2 ICLK
0008 C348h
ICU
Group 2 interrupt enable register
GEN02
32
32
1, 2 PCLKB
2 ICLK
0008 C34Ch
ICU
Group 3 interrupt enable register
GEN03
32
32
1, 2 PCLKB
2 ICLK
0008 C350h
ICU
Group 4 interrupt enable register
GEN04
32
32
1, 2 PCLKB
2 ICLK
0008 C354h
ICU
Group 5 interrupt enable register
GEN05
32
32
1, 2 PCLKB
2 ICLK
0008 C358h
ICU
Group 6 interrupt enable register
GEN06
32
32
1, 2 PCLKB
2 ICLK
0008 C370h
ICU
Group 12 interrupt enable register
GEN12
32
32
1, 2 PCLKB
2 ICLK
0008 C380h
ICU
Group 0 interrupt clear register
GCR00
32
32
1, 2 PCLKB
2 ICLK
0008 C384h
ICU
Group 1 interrupt clear register
GCR01
32
32
1, 2 PCLKB
2 ICLK
0008 C388h
ICU
Group 2 interrupt clear register
GCR02
32
32
1, 2 PCLKB
2 ICLK
0008 C38Ch
ICU
Group 3 interrupt clear register
GCR03
32
32
1, 2 PCLKB
2 ICLK
0008 C390h
ICU
Group 4 interrupt clear register
GCR04
32
32
1, 2 PCLKB
2 ICLK
0008 C394h
ICU
Group 5 interrupt clear register
GCR05
32
32
1, 2 PCLKB
2 ICLK
0008 C398h
ICU
Group 6 interrupt clear register
GCR06
32
32
1, 2 PCLKB
2 ICLK
0008 C3C0h
ICU
Unit select register
SEL
32
32
1, 2 PCLKB
2 ICLK
0008 C400h
RTC
64-Hz counter
R64CNT
8
8
2, 3 PCLKB
2 ICLK
0008 C402h
RTC
Second counter
RSECCNT
8
8
2, 3 PCLKB
2 ICLK
0008 C404h
RTC
Minute counter
RMINCNT
8
8
2, 3 PCLKB
2 ICLK
0008 C406h
RTC
Hour counter
RHRCNT
8
8
2, 3 PCLKB
2 ICLK
0008 C408h
RTC
Day-of-week counter
RWKCNT
8
8
2, 3 PCLKB
2 ICLK
0008 C40Ah
RTC
Date counter
RDAYCNT
8
8
2, 3 PCLKB
2 ICLK
0008 C40Ch
RTC
Month counter
RMONCNT
8
8
2, 3 PCLKB
2 ICLK
0008 C40Eh
RTC
Year counter
RYRCNT
16
16
2, 3 PCLKB
2 ICLK
0008 C410h
RTC
Second alarm register
RSECAR
8
8
2, 3 PCLKB
2 ICLK
0008 C412h
RTC
Minute alarm register
RMINAR
8
8
2, 3 PCLKB
2 ICLK
0008 C414h
RTC
Hour alarm register
RHRAR
8
8
2, 3 PCLKB
2 ICLK
0008 C416h
RTC
Day-of-week alarm register
RWKAR
8
8
2, 3 PCLKB
2 ICLK
0008 C418h
RTC
Date alarm register
RDAYAR
8
8
2, 3 PCLKB
2 ICLK
0008 C41Ah
RTC
Month alarm register
RMONAR
8
8
2, 3 PCLKB
2 ICLK
0008 C41Ch
RTC
Year alarm register
RYRAR
16
16
2, 3 PCLKB
2 ICLK
0008 C41Eh
RTC
Year alarm enable register
RYRAREN
8
8
2, 3 PCLKB
2 ICLK
0008 C422h
RTC
RTC control register 1
RCR1
8
8
2, 3 PCLKB
2 ICLK
0008 C424h
RTC
RTC control register 2
RCR2
8
8
2, 3 PCLKB
2 ICLK
0008 C426h
RTC
RTC control register 3
RCR3
8
8
2, 3 PCLKB
2 ICLK
0008 C428h
RTC
RTC control register 4
RCR4
8
8
2, 3 PCLKB
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
LVDA
Low Power
Consumption
ICUb
RTCa
Page 93 of 154
RX630 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (35/42)
Address
Module
Symbol
Register Name
Register
Symbol
0008 C42Ah
RTC
Frequency register H
0008 C42Ch
RTC
Frequency register L
0008 C42Eh
RTC
Time error adjustment register
0008 C440h
RTC
Time capture control register 0
Number of Access States
Number
of Bits
Access
Size
ICLK PCLK
ICLK PCLK
RFRH
16
16
2, 3 PCLKB
2 ICLK
RFRL
16
16
2, 3 PCLKB
2 ICLK
RADJ
8
8
2, 3 PCLKB
2 ICLK
RTCCR0
8
8
2, 3 PCLKB
2 ICLK
0008 C442h
RTC
Time capture control register 1
RTCCR1
8
8
2, 3 PCLKB
2 ICLK
0008 C444h
RTC
Time capture control register 2
RTCCR2
8
8
2, 3 PCLKB
2 ICLK
0008 C452h
RTC
Second capture register 0
RSECCP0
8
8
2, 3 PCLKB
2 ICLK
0008 C454h
RTC
Minute capture register 0
RMINCP0
8
8
2, 3 PCLKB
2 ICLK
0008 C456h
RTC
Hour capture register 0
RHRCP0
8
8
2, 3 PCLKB
2 ICLK
0008 C45Ah
RTC
Date capture register 0
RDAYCP0
8
8
2, 3 PCLKB
2 ICLK
0008 C45Ch
RTC
Month capture register 0
RMONCP0
8
8
2, 3 PCLKB
2 ICLK
0008 C462h
RTC
Second capture register 1
RSECCP1
8
8
2, 3 PCLKB
2 ICLK
0008 C464h
RTC
Minute capture register 1
RMINCP1
8
8
2, 3 PCLKB
2 ICLK
0008 C466h
RTC
Hour capture register 1
RHRCP1
8
8
2, 3 PCLKB
2 ICLK
0008 C46Ah
RTC
Date capture register 1
RDAYCP1
8
8
2, 3 PCLKB
2 ICLK
Related
Function
RTCa
0008 C46Ch
RTC
Month capture register 1
RMONCP1
8
8
2, 3 PCLKB
2 ICLK
0008 C472h
RTC
Second capture register 2
RSECCP2
8
8
2, 3 PCLKB
2 ICLK
0008 C474h
RTC
Minute capture register 2
RMINCP2
8
8
2, 3 PCLKB
2 ICLK
0008 C476h
RTC
Hour capture register 2
RHRCP2
8
8
2, 3 PCLKB
2 ICLK
0008 C47Ah
RTC
Date capture register 2
RDAYCP2
8
8
2, 3 PCLKB
2 ICLK
0008 C47Ch
RTC
Month capture register 2
RMONCP2
8
8
2, 3 PCLKB
2 ICLK
0008 C500h
TEMPS
Temperature sensor control register
TSCR
8
8
2, 3 PCLKB
2 ICLK
Temperature
Sensor
0008 C880h
SYSTEM
Counter-clock extension register 1
SCK1
8
8
2, 3 PCLKB
2 ICLK
MCK
0008 C890h
SYSTEM
Counter-clock extension register 2
SCK2
8
8
2, 3 PCLKB
2 ICLK
0009 0200h to
0009 03FFh
CAN0
Mailbox registers 0 to 31
MB0 to 31
128
8, 16,
32
2, 3 PCLKB
2 ICLK
0009 0400h to
0009 041Fh
CAN0
Mask registers 0 to 7
MKR0 to 7
32
8, 16,
32
2, 3 PCLKB
2 ICLK
0009 0420h
CAN0
FIFO received ID compare register 0
FIDCR0
32
8, 16,
32
2, 3 PCLKB
2 ICLK
0009 0424h
CAN0
FIFO received ID compare register 1
FIDCR1
32
8, 16,
32
2, 3 PCLKB
2 ICLK
0009 0428h
CAN0
Mask invalid register
MKIVLR
32
8, 16,
32
2, 3 PCLKB
2 ICLK
0009 042Ch
CAN0
Mailbox interrupt enable register
MIER
32
8, 16,
32
2, 3 PCLKB
2 ICLK
0009 0820h to
0009 083Fh
CAN0
Message control registers 0 to 31
MCTL0 to 31
8
8
2, 3 PCLKB
2 ICLK
0009 0840h
CAN0
Control register
CTLR
16
8, 16
2, 3 PCLKB
2 ICLK
0009 0842h
CAN0
Status register
STR
16
8, 16
2, 3 PCLKB
2 ICLK
0009 0844h
CAN0
Bit configuration register
BCR
32
8, 16,
32
2, 3 PCLKB
2 ICLK
0009 0848h
CAN0
Receive FIFO control register
RFCR
8
8
2, 3 PCLKB
2 ICLK
0009 0849h
CAN0
Receive FIFO pointer control register
RFPCR
8
8
2, 3 PCLKB
2 ICLK
0009 084Ah
CAN0
Transmit FIFO control register
TFCR
8
8
2, 3 PCLKB
2 ICLK
0009 084Bh
CAN0
Transmit FIFO pointer control register
TFPCR
8
8
2, 3 PCLKB
2 ICLK
0009 084Ch
CAN0
Error interrupt enable register
EIER
8
8
2, 3 PCLKB
2 ICLK
0009 084Dh
CAN0
Error interrupt factor judge register
EIFR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0009 084Eh
CAN0
Receive error count register
RECR
8
8
2, 3 PCLKB
0009 084Fh
CAN0
Transmit error count register
TECR
8
8
2, 3 PCLKB
2 ICLK
0009 0850h
CAN0
Error code store register
ECSR
8
8
2, 3 PCLKB
2 ICLK
0009 0851h
CAN0
Channel search support register
CSSR
8
8
2, 3 PCLKB
2 ICLK
0009 0852h
CAN0
Mailbox search status register
MSSR
8
8
2, 3 PCLKB
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
CAN
Page 94 of 154
RX630 Group
Table 4.1
Address
4. I/O Registers
List of I/O Registers (Address Order) (36/42)
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Number of Access States
Access
Size
ICLK PCLK
ICLK PCLK
0009 0853h
CAN0
Mailbox search mode register
MSMR
8
8
2, 3 PCLKB
2 ICLK
0009 0854h
CAN0
Time stamp register
TSR
16
16
2, 3 PCLKB
2 ICLK
0009 0856h
CAN0
Acceptance filter support register
AFSR
16
16
2, 3 PCLKB
2 ICLK
0009 0858h
CAN0
Test control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0009 1200h to
0009 13FFh
CAN1
Mailbox registers 0 to 31
MB0 to 31
128
8, 16,
32
2, 3 PCLKB
2 ICLK
0009 1400h to
0009 141Fh
CAN1
Mask register 0 to 7
MKR0 to 7
32
8, 16,
32
2, 3 PCLKB
2 ICLK
0009 1420h
CAN1
FIFO received ID compare register 0
FIDCR0
32
8, 16,
32
2, 3 PCLKB
2 ICLK
0009 1424h
CAN1
FIFO received ID compare register 1
FIDCR1
32
8, 16,
32
2, 3 PCLKB
2 ICLK
0009 1428h
CAN1
Mask invalid register
MKIVLR
32
8, 16,
32
2, 3 PCLKB
2 ICLK
0009 142Ch
CAN1
Mailbox interrupt enable register
MIER
32
8, 16,
32
2, 3 PCLKB
2 ICLK
0009 1820h to
0009 183Fh
CAN1
Message control registers 0 to 31
MCTL0 to 31
8
8
2, 3 PCLKB
2 ICLK
0009 1840h
CAN1
Control register
CTLR
16
8, 16
2, 3 PCLKB
2 ICLK
0009 1842h
CAN1
Status register
STR
16
8, 16
2, 3 PCLKB
2 ICLK
0009 1844h
CAN1
Bit configuration register
BCR
32
8, 16,
32
2, 3 PCLKB
2 ICLK
0009 1848h
CAN1
Receive FIFO control register
RFCR
8
8
2, 3 PCLKB
2 ICLK
0009 1849h
CAN1
Receive FIFO pointer control register
RFPCR
8
8
2, 3 PCLKB
2 ICLK
0009 184Ah
CAN1
Transmit FIFO control register
TFCR
8
8
2, 3 PCLKB
2 ICLK
0009 184Bh
CAN1
Transmit FIFO pointer control register
TFPCR
8
8
2, 3 PCLKB
2 ICLK
0009 184Ch
CAN1
Error interrupt enable register
EIER
8
8
2, 3 PCLKB
2 ICLK
0009 184Dh
CAN1
Error interrupt factor judge register
EIFR
8
8
2, 3 PCLKB
2 ICLK
0009 184Eh
CAN1
Receive error count register
RECR
8
8
2, 3 PCLKB
2 ICLK
0009 184Fh
CAN1
Transmit error count register
TECR
8
8
2, 3 PCLKB
2 ICLK
0009 1850h
CAN1
Error code store register
ECSR
8
8
2, 3 PCLKB
2 ICLK
0009 1851h
CAN1
Channel search support register
CSSR
8
8
2, 3 PCLKB
2 ICLK
0009 1852h
CAN1
Mailbox search status register
MSSR
8
8
2, 3 PCLKB
2 ICLK
0009 1853h
CAN1
Mailbox search mode register
MSMR
8
8
2, 3 PCLKB
2 ICLK
0009 1854h
CAN1
Time stamp register
TSR
16
8, 16
2, 3 PCLKB
2 ICLK
0009 1856h
CAN1
Acceptance filter support register
AFSR
16
8, 16
2, 3 PCLKB
2 ICLK
0009 1858h
CAN1
Test control register
TCR
8
8
2, 3 PCLKB
2 ICLK
0009 2200h to
0009 23FFh
CAN2
Mailbox registers 0 to 31
MB0 to 31
128
8, 16,
32
2, 3 PCLKB
2 ICLK
0009 2400h to
0009 241Fh
CAN2
Mask register 0 to 7
MKR0 to 7
32
8, 16,
32
2, 3 PCLKB
2 ICLK
0009 2420h
CAN2
FIFO received ID compare register 0
FIDCR0
32
8, 16,
32
2, 3 PCLKB
2 ICLK
0009 2424h
CAN2
FIFO received ID compare register 1
FIDCR1
32
8, 16,
32
2, 3 PCLKB
2 ICLK
0009 2428h
CAN2
Mask invalid register
MKIVLR
32
8, 16,
32
2, 3 PCLKB
2 ICLK
0009 242Ch
CAN2
Mailbox interrupt enable register
MIER
32
8, 16,
32
2, 3 PCLKB
2 ICLK
0009 2820h to
0009 283Fh
CAN2
Message control registers 0 to 31
MCTL0 to 31
8
8
2, 3 PCLKB
2 ICLK
0009 2820h to
0009 283Fh
CAN2
Message control registers 0 to 31
MCTL0 to 31
8
8
2, 3 PCLKB
2 ICLK
0009 2840h
CAN2
Control register
CTLR
16
8, 16
2, 3 PCLKB
2 ICLK
0009 2842h
CAN2
Status register
STR
16
8, 16
2, 3 PCLKB
2 ICLK
0009 2844h
CAN2
Bit configuration register
BCR
32
8, 16,
32
2, 3 PCLKB
2 ICLK
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
CAN
Page 95 of 154
RX630 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (37/42)
Address
Module
Symbol
Register Name
Register
Symbol
0009 2848h
CAN2
Receive FIFO control register
0009 2849h
CAN2
Receive FIFO pointer control register
Number of Access States
Number
of Bits
Access
Size
ICLK PCLK
ICLK PCLK
RFCR
8
8
2, 3 PCLKB
2 ICLK
RFPCR
8
8
2, 3 PCLKB
2 ICLK
0009 284Ah
CAN2
Transmit FIFO control register
TFCR
8
8
2, 3 PCLKB
2 ICLK
0009 284Bh
CAN2
Transmit FIFO pointer control register
TFPCR
8
8
2, 3 PCLKB
2 ICLK
0009 284Ch
CAN2
Error interrupt enable register
EIER
8
8
2, 3 PCLKB
2 ICLK
0009 284Dh
CAN2
Error interrupt factor judge register
EIFR
8
8
2, 3 PCLKB
2 ICLK
0009 284Eh
CAN2
Receive error count register
RECR
8
8
2, 3 PCLKB
2 ICLK
0009 284Fh
CAN2
Transmit error count register
TECR
8
8
2, 3 PCLKB
2 ICLK
0009 2850h
CAN2
Error code store register
ECSR
8
8
2, 3 PCLKB
2 ICLK
0009 2851h
CAN2
Channel search support register
CSSR
8
8
2, 3 PCLKB
2 ICLK
0009 2852h
CAN2
Mailbox search status register
MSSR
8
8
2, 3 PCLKB
2 ICLK
CAN
0009 2853h
CAN2
Mailbox search mode register
MSMR
8
8
2, 3 PCLKB
2 ICLK
0009 2854h
CAN2
Time stamp register
TSR
16
16
2, 3 PCLKB
2 ICLK
0009 2856h
CAN2
Acceptance filter support register
AFSR
16
16
2, 3 PCLKB
2 ICLK
0009 2858h
CAN2
Test control register
TCR
8
8
2, 3 PCLKB
2 ICLK
000A 0000h
USB0
System configuration control register
SYSCFG
16
16
3, 4 PCLKB
2, 3 ICLK
000A 0004h
USB0
System configuration status register 0
SYSSTS0
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 0008h
USB0
Device state control register 0
DVSTCTR0
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 0014h
USB0
CFIFO port register
CFIFO
16
8, 16
3, 4 PCLKB
2, 3 ICLK
000A 0018h
USB0
D0FIFO port register
D0FIFO
16
8, 16
3, 4 PCLKB
2, 3 ICLK
USBa
000A 001Ch
USB0
D1FIFO port register
D1FIFO
16
8, 16
3, 4 PCLKB
2, 3 ICLK
000A 0020h
USB0
CFIFO port select register
CFIFOSEL
16
16
3, 4 PCLKB
2, 3 ICLK
000A 0022h
USB0
CFIFO port control register
CFIFOCTR
16
16
3, 4 PCLKB
2, 3 ICLK
000A 0028h
USB0
D0FIFO port select register
D0FIFOSEL
16
16
3, 4 PCLKB
2, 3 ICLK
000A 002Ah
USB0
D0FIFO port control register
D0FIFOCTR
16
16
3, 4 PCLKB
2, 3 ICLK
000A 002Ch
USB0
D1FIFO port select register
D1FIFOSEL
16
16
3, 4 PCLKB
2, 3 ICLK
000A 002Eh
USB0
D1FIFO port control register
D1FIFOCTR
16
16
3, 4 PCLKB
2, 3 ICLK
000A 0030h
USB0
Interrupt enable register 0
INTENB0
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 0036h
USB0
BRDY interrupt status register
BRDYENB
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 0038h
USB0
NRDY interrupt status register
NRDYENB
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Related
Function
Page 96 of 154
RX630 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (38/42)
Address
Module
Symbol
Register Name
Register
Symbol
000A 003Ah
USB0
BEMP interrupt status register
000A 003Ch
USB0
000A 0040h
Number of Access States
Related
Function
Number
of Bits
Access
Size
BEMPENB
16
16
9 PCLKB or
more
Rounded up to USBa
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
SOF output configuration register
SOFCFG
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
USB0
Interrupt status register 0
INTSTS0
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 0046h
USB0
BRDY interrupt status register
BRDYSTS
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 0048h
USB0
NRDY interrupt status register
NRDYSTS
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 004Ah
USB0
BEMP interrupt status register
BEMPSTS
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 004Ch
USB0
Frame number register
FRMNUM
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 004Eh
USB0
Device state changing register
DVCHGR
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 0050h
USB0
USB address register
USBADDR
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 0054h
USB0
USB request type register
USBREQ
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
R01DS0060EJ0160 Rev.1.60
May 19, 2014
ICLK PCLK
ICLK PCLK
Page 97 of 154
RX630 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (39/42)
Number of Access States
Related
Function
Address
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
000A 0056h
USB0
USB request value register
USBVAL
16
16
9 PCLKB or
more
Rounded up to USBa
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 0058h
USB0
USB request index register
USBINDX
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 005Ah
USB0
USB request length register
USBLENG
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 005Eh
USB0
DCP maximum packet size register
DCPMAXP
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 0060h
USB0
DCP control register
DCPCTR
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 0064h
USB0
Pipe window select register
PIPESEL
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 0068h
USB0
Pipe configuration register
PIPECFG
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 006Ch
USB0
Pipe maximum packet size register
PIPEMAXP
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 006Eh
USB0
Pipe cycle control register
PIPEPERI
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 0070h
USB0
Pipe 1 control register
PIPE1CTR
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
R01DS0060EJ0160 Rev.1.60
May 19, 2014
ICLK PCLK
ICLK PCLK
Page 98 of 154
RX630 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (40/42)
Address
Module
Symbol
Register Name
Register
Symbol
000A 0072h
USB0
Pipe 2 control register
000A 0074h
USB0
000A 0076h
Number of Access States
Related
Function
Number
of Bits
Access
Size
PIPE2CTR
16
16
9 PCLKB or
more
Rounded up to USBa
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
Pipe 3 control register
PIPE3CTR
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
USB0
Pipe 4 control register
PIPE4CTR
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 0078h
USB0
Pipe 5 control register
PIPE5CTR
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 007Ah
USB0
Pipe 6 control register
PIPE6CTR
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 007Ch
USB0
Pipe 7 control register
PIPE7CTR
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 007Eh
USB0
Pipe 8 control register
PIPE8CTR
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 0080h
USB0
Pipe 9 control register
PIPE9CTR
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 0090h
USB0
Pipe 1 transaction counter enable register
PIPE1TRE
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 0092h
USB0
Pipe 1 transaction counter register
PIPE1TRN
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
R01DS0060EJ0160 Rev.1.60
May 19, 2014
ICLK PCLK
ICLK PCLK
Page 99 of 154
RX630 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (41/42)
Address
Module
Symbol
Register Name
Register
Symbol
000A 0094h
USB0
Pipe 2 transaction counter enable register
000A 0096h
USB0
000A 0098h
Number of Access States
Related
Function
Number
of Bits
Access
Size
PIPE2TRE
16
16
9 PCLKB or
more
Rounded up to USBa
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
Pipe 2 transaction counter register
PIPE2TRN
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
USB0
Pipe 3 transaction counter enable register
PIPE3TRE
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 009Ah
USB0
Pipe 3 transaction counter register
PIPE3TRN
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 009Ch
USB0
Pipe 4 transaction counter enable register
PIPE4TRE
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 009Eh
USB0
Pipe 4 transaction counter register
PIPE4TRN
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 00A0h
USB0
Pipe 5 transaction counter enable register
PIPE5TRE
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 00A2h
USB0
Pipe 5 transaction counter register
PIPE5TRN
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 0400h
USB0
Deep standby USB transceiver control/pin
monitor register
DPUSR0R
32
32
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
000A 0404h
USB0
Deep standby USB suspend/resume interrupt
register
DPUSR1R
32
32
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*8
R01DS0060EJ0160 Rev.1.60
May 19, 2014
ICLK PCLK
ICLK PCLK
Page 100 of 154
RX630 Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (42/42)
Module
Symbol
Address
Register
Symbol
Register Name
Number
of Bits
Access
Size
Number of Access States
ICLK PCLK
ICLK PCLK
007F C402h
FLASH
Flash mode register
FMODR
8
8
2, 3 FCLK
2, 3 ICLK
007F C410h
FLASH
Flash access status register
FASTAT
8
8
2, 3 FCLK
2, 3 ICLK
007F C411h
FLASH
Flash access error interrupt enable register
FAEINT
8
8
2, 3 FCLK
2, 3 ICLK
007F C412h
FLASH
Flash ready interrupt enable register
FRDYIE
8
8
2, 3 FCLK
2, 3 ICLK
007F C440h
FLASH
E2 DataFlash read enable register 0
DFLRE0
16
16
2, 3 FCLK
2, 3 ICLK
007F C442h
FLASH
E2 DataFlash read enable register 1
DFLRE1
16
16
2, 3 FCLK
2, 3 ICLK
007F C450h
FLASH
E2 DataFlash P/E enable register 0
DFLWE0
16
16
2, 3 FCLK
2, 3 ICLK
007F C452h
FLASH
E2 DataFlash P/E enable register 1
DFLWE1
16
16
2, 3 FCLK
2, 3 ICLK
007F C454h
FLASH
FCU RAM enable register
FCURAME
16
16
2, 3 FCLK
2, 3 ICLK
007F FFB0h
FLASH
Flash status register 0
FSTATR0
8
8
2, 3 FCLK
2, 3 ICLK
007F FFB1h
FLASH
Flash status register 1
FSTATR1
8
8
2, 3 FCLK
2, 3 ICLK
007F FFB2h
FLASH
Flash P/E mode entry register
FENTRYR
16
16
2, 3 FCLK
2, 3 ICLK
007F FFB4h
FLASH
Flash protection register
FPROTR
16
16
2, 3 FCLK
2, 3 ICLK
007F FFB6h
FLASH
Flash reset register
FRESETR
16
16
2, 3 FCLK
2, 3 ICLK
007F FFBAh
FLASH
FCU command register
FCMDR
16
16
2, 3 FCLK
2, 3 ICLK
007F FFC8h
FLASH
FCU processing switching register
FCPSR
16
16
2, 3 FCLK
2, 3 ICLK
007F FFCAh
FLASH
E2 data flash blank check control register
DFLBCCNT
16
16
2, 3 FCLK
2, 3 ICLK
007F FFCCh
FLASH
Flash P/E status register
FPESTAT
16
16
2, 3 FCLK
2, 3 ICLK
007F FFCEh
FLASH
E2 DataFlash blank check status register
DFLBCSTAT
16
16
2, 3 FCLK
2, 3 ICLK
007F FFE8h
FLASH
Peripheral clock notification register
PCKAR
16
16
2, 3 FCLK
2, 3 ICLK
FEFF FAC0h
FLASH
Unique ID register 0*9
UIDR0
8
8
1 ICLK
1 ICLK
FEFF FAC1h
FLASH
Unique ID register 1*9
UIDR1
8
8
1 ICLK
1 ICLK
FEFF FAC2h
FLASH
Unique ID register
2*9
UIDR2
8
8
1 ICLK
1 ICLK
FEFF FAC3h
FLASH
Unique ID register 3*9
UIDR3
8
8
1 ICLK
1 ICLK
FEFF FAC4h
FLASH
Unique ID register 4*9
UIDR4
8
8
1 ICLK
1 ICLK
FEFF FAC5h
FLASH
Unique ID register
5*9
UIDR5
8
8
1 ICLK
1 ICLK
FEFF FAC6h
FLASH
Unique ID register 6*9
UIDR6
8
8
1 ICLK
1 ICLK
FEFF FAC7h
FLASH
Unique ID register 7*9
UIDR7
8
8
1 ICLK
1 ICLK
FEFF FAC8h
FLASH
Unique ID register 8*9
UIDR8
8
8
1 ICLK
1 ICLK
FEFF FAC9h
FLASH
Unique ID register
9*9
UIDR9
8
8
1 ICLK
1 ICLK
FEFF FACAh
FLASH
Unique ID register 10*9
UIDR10
8
8
1 ICLK
1 ICLK
FEFF FACBh
FLASH
Unique ID register 11*9
UIDR11
8
8
1 ICLK
1 ICLK
FEFF FACCh
FLASH
Unique ID register 12*9
UIDR12
8
8
1 ICLK
1 ICLK
FEFF FACDh
FLASH
Unique ID register
13*9
UIDR13
8
8
1 ICLK
1 ICLK
FEFF FACEh
FLASH
Unique ID register 14*9
UIDR14
8
8
1 ICLK
1 ICLK
FEFF FACFh
FLASH
Unique ID register 15*9
UIDR15
8
8
1 ICLK
1 ICLK
register*9
TSCDRL
8
8
1 ICLK
1 ICLK
TSCDRH
8
8
1 ICLK
1 ICLK
FEFF FAD2h
TEMPS
Temperature sensor calibration data
FEFF FAD3h
TEMPS
Temperature sensor calibration data register*9
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Note 7.
Note 8.
Note 9.
Related
Function
Flash Memory
Temperature
sensor
When the same output trigger is specified for pulse output groups 2 and 3 by the PPG0.PCR setting, the PPG0.NDRH address is 000881ECh. When different output
triggers are specified, the PPG0.NDRH addresses for pulse output groups 2 and 3 are 000881EEh and 000881ECh, respectively.
When the same output trigger is specified for pulse output groups 0 and 1 by the PPG0.PCR setting, the PPG0.NDRL address is 000881EDh. When different output
triggers are specified, the PPG0.NDRL addresses for pulse output groups 0 and 1 are 000881EFh and 000881EDh, respectively.
When the same output trigger is specified for pulse output groups 6 and 7 by the PPG1.PCR setting, the PPG1.NDRH address is 000881FCh. When different output
triggers are specified, the PPG1.NDRH addresses for pulse output groups 6 and 7 are 000881FEh and 000881FCh, respectively.
When the same output trigger is specified for pulse output groups 4 and 5 by the PPG1.PCR setting, the PPG1.NDRL address is 000881FDh. When different output
triggers are specified, the PPG1.NDRL addresses for pulse output groups 4 and 5 are 000881FFh and 000881FDh, respectively.
Odd addresses should not be accessed in 16-bit units. When accessing a register in 16-bit units, access the address of the TMR0 or TMR2 register. Table 26.4 lists
register allocation for 16-bit access in the User’s manual: Hardware.
The CAN2 module is not provided in products less than 1 Mbyte of ROM.
The CAN0 module is not provided in products less than 512 Kbytes of ROM.
When the register is accessed while the USB is operating, a delay may be generated in accessing.
These registers are only present in the G version.
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 101 of 154
RX630 Group
5. Electrical Characteristics
5.
Electrical Characteristics
5.1
Absolute Maximum Ratings
Table 5.1
Absolute Maximum Ratings
Conditions: VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
Item
Symbol
Value
Unit
Power supply voltage
VCC, VCC_USB
–0.3 to +4.6
V
VBATT power supply voltage
VBATT
–0.3 to +4.6
V
Vin
–0.3 to VCC +0.3
V
Input voltage (except for ports for 5 V
Input voltage (ports for 5 V
tolerant*1)
tolerant*1)
Vin
–0.3 to +5.8
V
Reference power supply voltage
VREFH
–0.3 to VCC +0.3
V
Analog power supply voltage
AVCC*2
–0.3 to +4.6
V
Analog input voltage
Operating temperature
VAN
–0.3 to VCC +0.3
V
D version
Topr
–40 to +85
°C
G version
Topr
–40 to +105
°C
Tstg
–55 to +125
°C
Storage temperature
Caution: Permanent damage to the LSI may result if absolute maximum ratings are exceeded.
Note 1. Ports 07, 12 to 17, 20 to 25, 30 to 34, 50 to 52, 54 to 57, 67, 74 to 77, 80 to 82, A1 to A4, A6, B, and C are 5 V tolerant.
Note 2. Connect AVCC0 to VCC. When neither the A/D converter nor the D/A converter is in use, do not leave the AVCC0, VREFH/
VREFH0, AVSS0, and VREFL/VREFL0 pins open. Connect the AVCC0 and VREFH/VREFH0 pins to VCC, and the AVSS0 and
VREFL/VREFL0 pins to VSS, respectively.
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 102 of 154
RX630 Group
5.2
5. Electrical Characteristics
DC Characteristics
Table 5.2
DC Characteristics (1)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr
Item
Schmitt trigger
input voltage
IRQ input pin*1
MTU input pin*1
TMR input pin*1
SCI input pin*1
ADTRG# input pin*1
RES#, NMI
RIIC input pin
(except for SMBus)
Input high voltage
(except for
Schmitt trigger
input pin)
Input low voltage
(except for
Schmitt trigger
input pin)
Symbol
Min.
Typ.
Max.
Unit
VIH
VCC × 0.8
—
VCC + 0.3
V
VIL
–0.3
—
VCC × 0.2
VT
VCC × 0.06
—
—
VIH
VCC × 0.7
—
5.8
VIL
–0.3
—
VCC × 0.3
VT
VCC × 0.05
—
—
Ports for 5 V tolerant*2
VIH
VCC × 0.8
—
5.8
VIL
–0.3
—
VCC × 0.2
Other input pins excluding ports
for 5 V tolerant*3
VIH
VCC × 0.8
—
VCC + 0.3
VIL
–0.3
—
VCC × 0.2
VIH
MD pin, EMLE
VCC × 0.9
—
VCC + 0.3
EXTAL, RSPI, WAIT#, TCK
VCC × 0.8
—
VCC + 0.3
XCIN*3
VCC × 0.8
—
VCC + 0.3
D0 to D31
VCC × 0.7
—
VCC + 0.3
RIIC (SMBus)
2.1
—
VCC + 0.3
–0.3
—
VCC × 0.1
MD pin, EMLE
VIL
EXTAL, RSPI, WAIT#, TCK
–0.3
—
VCC × 0.2
XCIN*3
–0.3
—
VCC × 0.2
D0 to D31
–0.3
—
VCC × 0.3
RIIC (SMBus)
–0.3
—
0.8
Test
Conditions
V
V
Note 1. This does not include the pins, which are multiplexed as ports for 5 V tolerant.
Note 2. Ports 07, 12 to 17, 20 to 25, 30 to 34, 50 to 52, 54 to 57, 67, 74 to 77, 80 to 82, A1 to A4, A6, B, and C are 5 V tolerant.
Note 3. For P32, P31, P30, and XCIN, input as follows when the VBATT power supply is selected.
VIH Min. = VBATT × 0.8, VIH Max. = VBATT + 0.3, VIL Min. = –0.3, VIL Max. = VBATT × 0.2
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 103 of 154
RX630 Group
Table 5.3
5. Electrical Characteristics
DC Characteristics (2)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Output high voltage
All output pins
VOH
VCC – 0.5
—
—
V
IOH = –1 mA
Output low voltage
All output pins
(except for RIIC pins)
VOL
—
—
0.5
V
IOL = 1.0 mA
—
—
0.4
V
IOL = 3.0 mA
—
—
0.6
—
—
0.4
—
0.4
—
RIIC pins
RIIC pins
(only P12 and P13 in channel 0)
VOL
IOL = 6.0 mA
V
IOL = 15.0 mA
(ICFER.FMPE = 1)
IOL = 20.0 mA
(ICFER.FMPE = 1)
Input leakage
current
RES#, MD pin, EMLE*1, NMI
Iin
—
—
1.0
µA
Vin = 0 V
Vin = VCC
Three-state leakage
current (off state)
Other than ports for 5 V tolerant
ITSI
—
—
1.0
µA
Vin = 0 V
Vin = VCC
—
—
5.0
Ports for 5 V tolerant
Vin = 0 V
Vin = 5.5 V
Input pull-up MOS
current
Ports 0 to 2, 30 to 34, 36, 37, 4
to G, H4, H5, J3, J5, K, L
Ip
–300
—
–10
µA
VCC= 2.7 to 3.6 V
Vin = 0 V
Input capacitance
All input pins
(except for ports 12, 13, 16, 17,
20, 21, 4, C0, C1, and EMLE)
Cin
—
—
15
pF
Vin = 0 V
f = 1 MHz
Ta = 25°C
—
—
30
10
—
300
µA
Vin = VCC
Ports 12, 13, 16, 17, 20, 21, 4,
C0, C1, EMLE
Input pull-down
MOS current
EMLE
BSCANP*2
Ip
Note 1. The input leakage current value at the EMLE pin is only when Vin = 0 V.
Note 2. The BSCANP pin is present in 177-, 176-, and 145-pin versions.
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 104 of 154
RX630 Group
5. Electrical Characteristics
DC Characteristics (3) (for D and G Versions (-40 ≤ Ta ≤ +85°C))
Table 5.4
Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr
Item
High-speed operating mode
Supply
current*1
Normal
ICC
*3
Typ.
Max.
Unit
Test Conditions
mA
ICLK = 100 MHz
PCLKB = 50 MHz
FCLK = 50 MHz
BCLK = 50 MHz
—
—
100
Peripheral function: clock signal
supplied*4
—
52
—
Peripheral function: clock signal
stopped*4
—
40
—
—
25
60
—
20
30
Sleep mode
All-module-clock-stop mode (reference value)
Increased by BGO
operation*5
—
15
—
—
4
—
ICLK = 1 MHz
Low-speed operating mode 2
—
1
—
ICLK = 32.768 kHz
Software standby mode
—
0.2
6
—
22
200
Power-on reset circuit
and low-power function
enabled consumption
function disabled
—
21
60
Power-on reset circuit
and low-power function
enabled consumption
function enabled
—
6.2
28
Increased by RTC operation
—
3
—
RTC operation when VCC is off
—
1.7
—
VBATT = 2.3 V
—
3.3
—
VBATT = 3.3 V
Power supplied to RAM and USB resume
detecting unit
Power not supplied
to RAM and USB
resume detecting
unit
µA
During 12-bit A/D conversion (including temperature
sensor)
IAVCC0
—
2.3
3.2
mA
During 10-bit A/D conversion
IVREFH*7
—
1.0
1.65
mA
—
0.7
1.0
mA
—
25
35
µA
—
0.1
4.0
µA
—
0.6
0.7
mA
—
0.5
0.6
mA
During D/A conversion (per unit)
Waiting for A/D, D/A conversion (all units)*8
A/D, D/A converter in standby mode (all
Reference
power supply
current
Min.
Low-speed operating mode 1*6
Deep software standby mode
Analog power
supply
current*7
Symbol
Max.*2
—
units)*8
During 12-bit A/D conversion
IVREFH0
Waiting for 12-bit A/D conversion (per unit)
—
0.1
2.0
µA
RAM standby voltage
12-bit A/D converter in standby mode (per unit)
VRAM
2.7
—
—
V
VCC rising gradient
SrVCC
8.4
—
20000
µs/V
SfVCC
8.4
—
—
µs/V
VCC falling
gradient*8
Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.
Note 2. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation.
Note 3. ICC depends on f (ICLK) as follows. (ICLK:PCLK:BCLK:BCLK pin = 8:4:4:2)
ICC Max. = 0.87 × f + 13 (max. operation in high-speed operating mode)
ICC Typ. = 0.35 × f + 5 (normal operation in high-speed operating mode)
ICC Typ. = 1.0 × f + 3 (low-speed operating mode 1)
ICC Max. = 0.48 × f + 12 (sleep mode)
Note 4. This does not include the BGO operation.
Note 5. This is the increase for programming or erasure of the ROM or flash memory for data storage during program execution.
Note 6. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.
Note 7. The current values for 10-bit A/D converter and 10-bit D/A converter are included in the current from the VREFH pin.
Note 8. The values are the sum of IAVCC0 and IVREFH.
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 105 of 154
RX630 Group
5. Electrical Characteristics
DC Characteristics (4) (for G Version (+85 < Ta ≤ +105°C))
Table 5.5
Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr
Item
High-speed operating mode
Supply
current*1
Normal
ICC
*3
Typ.
Max.
Unit
Test Conditions
mA
ICLK = 100 MHz
PCLKB = 50 MHz
FCLK = 50 MHz
BCLK = 50 MHz
—
—
115
Peripheral function: clock signal
supplied*4
—
52
—
Peripheral function: clock signal
stopped*4
—
40
—
—
25
75
—
20
45
Sleep mode
All-module-clock-stop mode (reference value)
Increased by BGO
operation*5
—
15
—
—
4
—
ICLK = 1 MHz
Low-speed operating mode 2
—
1
—
ICLK = 32.768 kHz
Software standby mode
—
0.2
6
—
22
200
Power-on reset circuit and
low-power function
enabled consumption
function disabled
—
21
60
Power-on reset circuit and
low-power function
enabled consumption
function enabled
—
6.2
28
Increased by RTC operation
—
3
—
RTC operation when VCC is off
—
1.7
—
VBATT = 2.3 V
—
3.3
—
VBATT = 3.3 V
Power supplied to RAM and USB resume
detecting unit
Power not supplied
to RAM and USB
resume detecting
unit
µA
During 12-bit A/D conversion (including temperature
sensor)
IAVCC0
—
2.3
3.2
mA
During 10-bit A/D conversion
IVREFH*7
—
1.0
1.65
mA
—
0.7
1.0
mA
—
—
25
35
µA
During D/A conversion (per unit)
Waiting for A/D, D/A conversion (all units)*8
A/D, D/A converter in standby mode (all units)*8
Reference
power supply
current
Min.
Low-speed operating mode 1*6
Deep software standby mode
Analog power
supply
current*7
Symbol
Max.*2
During 12-bit A/D conversion
IVREFH0
Waiting for 12-bit A/D conversion (per unit)
12-bit A/D converter in standby mode (per unit)
—
0.1
5
µA
—
0.6
0.7
mA
—
0.5
0.6
mA
—
0.1
2.0
µA
RAM standby voltage
VRAM
2.7
—
—
V
VCC rising gradient
SrVCC
8.4
—
20000
µs/V
SfVCC
8.4
—
—
µs/V
VCC falling
gradient*8
Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.
Note 2. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation.
Note 3. ICC depends on f (ICLK) as follows. (ICLK:PCLK:BCLK:BCLK pin = 8:4:4:2)
ICC Max. = 0.87 × f + 13 (max. operation in high-speed operating mode)
ICC Typ. = 0.35 × f + 5 (normal operation in high-speed operating mode)
ICC Typ. = 1.0 × f + 3 (low-speed operating mode 1)
ICC Max. = 0.48 × f + 12 (sleep mode)
Note 4. This does not include the BGO operation.
Note 5. This is the increase for programming or erasure of the ROM or flash memory for data storage during program execution.
Note 6. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.
Note 7. The current values for 10-bit A/D converter and 10-bit D/A converter are included in the current from the VREFH pin.
Note 8. The values are the sum of IAVCC0 and IVREFH.
R01DS0060EJ0160 Rev.1.60
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Page 106 of 154
RX630 Group
Table 5.6
5. Electrical Characteristics
Permissible Output Currents
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr
Item
Permissible output low current
(average value per pin)
Permissible output low current
(max. value per pin)
All output
pins*1
All output pins*2
All output
pins*1
All output pins*2
Permissible output low current (total)
Total of all output pins
Permissible output high current
(average value per pin)
All output pins (except for
USB_DPUPE pin)*1
USB_DPUPE pin*2
Permissible output high current
(max. value per pin)
Permissible output high current (total)
All output
pins*1
All output pins*2
Total of all output pins
Symbol
Min.
Typ.
Normal drive
IOL
—
—
High drive
IOL
Normal drive
IOL
High drive
IOL
—
—
Max.
Unit
2.0
mA
3.8
mA
4.0
mA
7.6
mA
IOL
—
—
80
mA
Normal drive
–IOH
—
—
–2.0
mA
High drive
–IOH
—
—
–3.8
mA
Normal drive
–IOH
—
—
–4.0
mA
High drive
–IOH
—
—
–7.6
mA
–IOH
—
—
–80
mA
Caution: To protect the LSI’s reliability, the output current values should not exceed the values in this table.
Note 1. This is the value when normal driving ability is set with a pin for which normal driving ability is selectable.
Note 2. This is the value when high driving ability is set with a pin for which normal driving ability is selectable or the value of the pin to
which high driving ability is fixed.
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RX630 Group
5.3
5. Electrical Characteristics
AC Characteristics
Table 5.7
Operation Frequency Value (High-Speed Operating Mode)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr
Item
Operation
frequency
Symbol
Min.
Typ.
Max.
Unit
f
—
—
100
MHz
Peripheral module clock (PCLKB)
—*1
—
50
FlashIF clock (FCLK)
—*2
—
50
External bus clock (BCLK)
—
—
50
BCLK pin output
—
—
25
USB clock (UCLK)
—
—
48
IEBUS clock (IECLK)
—
—
44.03
System clock (ICLK)
Note 1. The PCLKB must run at a frequency of at least 24 MHz if the USB is in use.
Note 2. The FCLK must run at a frequency of at least 4 MHz when changing the ROM or E2 DataFlash memory contents.
Table 5.8
Operation Frequency Value (Low-Speed Operating Mode 1)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr
Item
Operation
frequency
Table 5.9
Symbol
Min.
Typ.
Max.
Unit
f
—
—
1
MHz
Peripheral module clock (PCLKB)
—
—
1
FlashIF clock (FCLK)
—
—
1
External bus clock (BCLK)
—
—
1
BCLK pin output
—
—
1
USB clock (UCLK)
—
—
1
IEBUS clock (IECLK)
—
—
1
System clock (ICLK)
Operation Frequency Value (Low-Speed Operating Mode 2)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr
Item
Operation
frequency
Symbol
Min.
Typ.
Max.
Unit
f
32
—
143.75
kHz
Peripheral module clock (PCLKB)
—
—
143.75
FlashIF clock (FCLK)
32
—
143.75
External bus clock (BCLK)
—
—
143.75
BCLK pin output
—
—
143.75
USB clock (UCLK)
—
—
143.75
IEBUS clock (IECLK)
—
—
143.75
System clock (ICLK)
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 108 of 154
RX630 Group
5. Electrical Characteristics
5.3.1
Reset Timing
Table 5.10
Reset Timing
Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
tRESWP
2
—
—
ms
Figure 5.1
Deep software standby mode
tRESWD
1
—
—
ms
Figure 5.2
Software standby mode, low-speed
operating mode 2
tRESWS
1
—
—
ms
Programming or erasure of the ROM or E2
data-flash memory or blank checking of the
E2 DataFlash memory
tRESW
200
—
—
µs
Other than above
tRESW
200
—
—
µs
Wait time after RES# cancellation
tRESWT
59
—
60
tcyc
Internal reset time
(independent watchdog timer reset, watchdog timer reset,
software reset)
tRESW2
112
—
120
tcyc
Item
RES# pulse
width
Power-on
Figure 5.1
VCC
RES#
tRESWP
Internal reset
tRESWT
Figure 5.1
Reset Input Timing at Power-On
tRESWD, tRESWS, tRESWF, tRESW
RES#
Internal reset
tRESWT
Figure 5.2
Reset Input Timing
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May 19, 2014
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RX630 Group
5. Electrical Characteristics
5.3.2
Clock Timing
Table 5.11
Clock Timing (Except for Sub-Clock Related)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
BCLK pin output cycle time
tBcyc
40
—
—
ns
Figure 5.3
BCLK pin output high pulse width
tCH
15
—
—
ns
BCLK pin output low pulse width
tCL
15
—
—
ns
BCLK pin output rising time
tCr
—
—
5
ns
BCLK pin output falling time
tCf
—
—
5
ns
EXTAL external clock input cycle time
tEXcyc
50
—
—
ns
EXTAL external clock input high pulse width
tEXH
20
—
—
ns
EXTAL external clock input low pulse width
tEXL
20
—
—
ns
EXTAL external clock rising time
tEXr
—
—
5
ns
EXTAL external clock falling time
tEXf
—
—
5
ns
EXTAL external clock input wait time*1
tEXWT
1
—
—
ms
Main clock oscillator oscillation frequency
fMAIN
4
—
16
MHz
Main clock oscillation stabilization time (crystal)
tMAINOSC
—
—
—*3
ms
—
—*4
ms
Item
Figure 5.4
Figure 5.5
Main clock oscillation stabilization wait time (crystal)
tMAINOSCWT
—
LOCO and IWDTCLK clock cycle time
tcyc
6.96
8
9.4
µs
LOCO and IWDTCLK clock oscillation frequency
fLOCO
106.25
125
143.75
kHz
LOCO and IWDTCLK clock oscillation stabilization wait time
tLOCOWT
—
—
20
µs
Figure 5.6
HOCO clock oscillator oscillation frequency
fHOCO
45
50
55
MHz
HOCO clock oscillation stabilization wait time 1*2
tHOCOWT1
—
—
1.8
ms
Figure 5.7
HOCO clock oscillation stabilization wait time 2
tHOCOWT2
—
—
2.0
ms
Figure 5.8
HOCO clock power supply settling time
tHOCOP
—
—
1
ms
Figure 5.9
PLL circuit oscillation frequency
fPLL
104
—
200
MHz
tPLL1
—
—
500
µs
tPLLWT1
—
—
—*5
ms
tPLL2
—
—
tMAINOSC
+tPLL1
ms
tPLLWT2
—
—
—*5
ms
PLL operation started
after main clock
oscillation has settled
PLL clock oscillation stabilization time
PLL clock oscillation stabilization wait
PLL clock oscillation stabilization time
PLL operation started
before main clock
oscillation has settled
PLL clock oscillation stabilization wait
Figure 5.10
Figure 5.11
Note 1. This is the time until the clock is used after setting P36 and P37 as inputs, and then clearing the main clock oscillator stop bit
(MOSCCR.MOSTP) to 0 (selecting operation).
Note 2. This is the time until the frequency of oscillation by the HOCO (fHOCO) reaches the range for guaranteed operation. after
release from the reset state.
Note 3. When using a main clock, ask the manufacturer of the oscillator to evaluate its oscillation. Refer to the results of evaluation
provided by the manufacturer for the oscillation stabilization time.
Note 4. The number of cycles n selected by the value of the MOSCWTCR.MSTS[4:0] bits determines the main-clock oscillation
stabilization waiting time in accord with the formula below.
tMAINOSCWT = tMAINOSC +
n +16384
fMAIN
Note 5. The number of cycles n selected by the value of the PLLWTCR.PSTS[4:0] bits determines the PLL-clock oscillation stabilization
waiting time in accord with the formula below.
tPLLWT1 = tPLL1 +
tPLLWT2 = tPLL2 +
n +131072
fPLL
n +131072
fPLL
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May 19, 2014
= tMAINOSC + tPLL1 +
n +131072
fPLL
Page 110 of 154
RX630 Group
Table 5.12
5. Electrical Characteristics
Clock Timing (Sub-Clock Related)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VBATT = 2.3 to 3.6 V,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr
Item
Sub-clock oscillator oscillation frequency
Symbol
Min.
Typ.
Max.
Unit
fSUB
—
32.768
—
kHz
s
Sub-clock oscillation stabilization time
tSUBOSC
—
—
*1
Sub-clock oscillation stabilization wait offset time*2
tSUBOSCWT0
1.8
—
2.6
s
Sub-clock oscillation stabilization waiting time
tSUBOSCWT
—
—
*2
s
Test
Conditions
Figure 5.12
Note 1. When using a sub-clock, ask the manufacturer of the oscillator to evaluate its oscillation. Refer to the results of evaluation
provided by the manufacturer for the oscillation stabilization time.
Note 2. The minimum and maximum values for sub-clock oscillation stabilization waiting offset time (tSUBOSCWT0) only apply to products
tagged with “*1” in Figure 1.3, List of Products. For other products, take the value of (tSUBOSCWT0) to be 0.
Note 3. The number of cycles n selected by the value of the SOSCWTCR.SSTS[4:0] bits determines the sub-clock oscillation
stabilization waiting time in accord with the formula below.
tSUBOSCWT = max (tSUBOSC, tSUBOSCWT0) +
n
fSUB
The notation “max(tSUBOSC, tSUBOSCWT0)“ indicates whichever is higher of tSUBOSC and tSUBOSCWT0.
tBcyc
tCH
tCf
BCLK pin output
tCL
tCr
Test conditions: VOH = VCC × 0.7, VOL = VCC × 0.3, IOH = –1.0 mA, IOL = 1.0 mA, C = 30 pF
Figure 5.3
BCLK Pin Output Timing
tEXcyc
tEXH
EXTAL external clock input
VCC × 0.5
tEXr
Figure 5.4
tEXL
tEXf
EXTAL External Clock Input Timing
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Page 111 of 154
RX630 Group
5. Electrical Characteristics
MOSCCR.MOSTP
tMAINOSC
Main clock oscillator output
tMAINOSCWT
Main clock
Figure 5.5
Main Clock Oscillation Start Timing
LOCOCR.LCSTP,
ILOCOCR.ILCSTP
tLOCOWT
LOCO, IWDTCLK clock
Figure 5.6
LOCO, IWDTCLK Oscillation Start Timing
RES#
Internal reset
tRESWT
HOCOCR.HCSTP
tHOCOWT1
HOCO clock
Figure 5.7
HOCO Oscillation Start Timing (After Reset is Canceled by Setting the OFS1.HOCOEN
Bit to 0)
RES#
Internal reset
tRESWT
HOCOCR.HCSTP
tHOCOWT2
HOCO clock
Figure 5.8
HOCO Clock Oscillation Start Timing (Oscillation is Started by Setting the
HOCOCR.HCSTP Bit)
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May 19, 2014
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RX630 Group
5. Electrical Characteristics
HOCOPCR.HOCOPCNT
HOCOCR.HCSTP
tHOCOP
Internal power supply for HOCO
Figure 5.9
HOCO Power Supply Control Timing
MOSCCR.MOSTP
tMAINOSC
Main clock oscillator output
PLLCR2.PLLEN
tPLL1
PLL circuit output
tPLLWT1
PLL clock
Figure 5.10
PLL Clock Oscillation Start Timing (PLL is Operated after Main Clock Oscillation Has
Settled)
MOSCCR.MOSTP
tMAINOSC
Main clock oscillator output
PLLCR2.PLLEN
tPLL2
PLL circuit output
tPLLWT2
PLL clock
Figure 5.11
PLL Clock Oscillation Start Timing (PLL is Operated before Main Clock Oscillation Has
Settled)
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May 19, 2014
Page 113 of 154
RX630 Group
5. Electrical Characteristics
SOSCCR.SOSTP
tSUBOSC
Sub-clock oscillator output
tSUBOSCWT0
*1
Sub-clock
Note 1: This is the waiting period obtained by setting the SOCCWTCR.SSTS[4:0] bits.
Figure 5.12
Sub-Clock Oscillation Start Timing
5.3.3
Timing of Recovery from Low Power Consumption Modes
Table 5.13
Timing of Recovery from Low Power Consumption Modes
Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
Figure 5.13
Crystal resonator
connected to
main clock
oscillator
Main clock oscillator
operating
tSBYMC
10
—
—
ms
Main clock oscillator and
PLL circuit operating
tSBYPC
10
—
—
ms
External clock
input to main
clock oscillator
Main clock oscillator
operating
tSBYEX
1
—
—
ms
Main clock oscillator and
PLL circuit operating
tSBYPE
1
—
—
ms
Sub-clock oscillator operating
tSBYSC
2
—
—
s
High-speed on-chip oscillator operating
tSBYHO
—
—
2
ms
Low-speed on-chip oscillator or IWDT-dedicated
on-chip oscillator operating
tSBYLO
—
—
800
µs
Recovery time after cancellation of deep software standby mode
tDSBY
—
—
1.0
ms
Wait time after cancellation of deep software standby mode
tDSBYWT
45
—
46
tcyc
Recovery time
after
cancellation of
software
standby mode
Note:
Figure 5.14
The wait time varies depending on the state in which each oscillator was when the WAIT instruction was executed. The recovery
time when multiple oscillators are operating is the same period as that when the oscillator which requires the longest time of all
operating oscillators to recover is operating alone.
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Page 114 of 154
RX630 Group
5. Electrical Characteristics
Oscillator
ICLK
IRQ
Software standby mode
tSBYMC, tSBYPC, tSBYEX, tSBYPE,
tSBYSC, tSBYHO, tSBYLO
Figure 5.13
Software Standby Mode Cancellation Timing
Oscillator
IRQ
Deep software
standby reset
Internal reset
Deep software standby mode
tDSBY
tDSBYWT
Reset exception handling start
Figure 5.14
Deep Software Standby Mode Cancellation Timing
5.3.4
Control Signal Timing
Table 5.14
Control Signal Timing
Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
NMI pulse width
tNMIW
200
—
—
ns
tc (PCLK) × 2
IRQ pulse width
tIRQW
200
tc (PCLK) × 2
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Test Conditions
tc (PCLK) × 2 ≤ 200 ns Figure 5.15
tc (PCLK) × 2 > 200 ns Figure 5.15
—
—
ns
tc (PCLK) × 2 ≤ 200 ns Figure 5.16
tc (PCLK) × 2 > 200 ns Figure 5.16
Page 115 of 154
RX630 Group
5. Electrical Characteristics
NMI
tNMIW
Figure 5.15
NMI Interrupt Input Timing
IRQ
tIRQW
Figure 5.16
IRQ Interrupt Input Timing
5.3.5
Bus Timing
Table 5.15
Bus Timing
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V,
ICLK = 8 to 100 MHz, BCLK = 8 to 50 MHz, Ta = Topr
Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, IOH = –1.0 mA, IOL = 1.0 mA, C = 30 pF
High drive output is selected by the drive capacity control register.
Item
Symbol
Min.
Address delay time
tAD
—
Byte control delay time
tBCD
—
CS# delay time
tCSD
—
20
ns
ALE delay time
tALED
—
20
ns
RD# delay time
tRSD
—
20
ns
Read data setup time
tRDS
15
—
ns
Read data hold time
tRDH
0
—
ns
WR# delay time
tWRD
—
20
ns
Write data delay time
tWDD
—
20
ns
Write data hold time
tWDH
0
—
ns
WAIT# setup time
tWTS
15
—
ns
WAIT# hold time
tWTH
0
—
ns
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Max.
Unit
Test Conditions
20
ns
20
ns
Figure 5.17 to
Figure 5.22
Figure 5.23
Page 116 of 154
RX630 Group
5. Electrical Characteristics
Data cycle
Address cycle
T a1
T a1
T an
T W1
T W2
T W3
T W4
T end
T W5
T n1
T n2
BCLK
tAD
Address bus
t AD
tRDS
tAD
tRDH
Address bus/
data bus
tALED
tALED
Address latch
(ALE)
tRSD
tRSD
Data read
(RD#)
Figure 5.17
tCSD
tCSD
Chip select
(CS1#)
Address/Data Multiplexed Bus Read Access Timing
Data cycle
Address cycle
Ta1
Ta1
Tan
TW1
TW2
TW3
TW4
TW5
Tend
Tn1
Tn2
Tn3
BCLK
tAD
Address bus
tAD
tAD
tWDD
tWDH
Address bus/
data bus
tALED
tALED
Address latch
(ALE)
tWRD
tWRD
Data write
(WRm#)
tCSD
Chip select
(CS1#)
Figure 5.18
tCSD
Address/Data Multiplexed Bus Write Access Timing
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RX630 Group
5. Electrical Characteristics
CSRWAIT:2
RDON:1
CSROFF:2
CSON:0
TW1
TW2
Tend
Tn1
Tn2
BCLK
Byte write strobe mode
tAD
tAD
tAD
tAD
tBCD
tBCD
tCSD
tCSD
A23 to A0
1-write strobe mode
A23 to A1
BC3# to BC0#
Common to both byte write strobe
mode and 1-write strobe mode
CS7# to CS0#
tRSD
tRSD
RD# (Read)
tRDS
tRDH
D31 to D0 (Read)
Figure 5.19
External Bus Timing/Normal Read Cycle (Bus Clock Synchronized)
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Page 118 of 154
RX630 Group
5. Electrical Characteristics
CSWWAIT:2
WRON:1
WDON:1*1
CSWOFF:2
WDOFF:1*1
CSON:0
T W1
T W2
T end
T n1
Tn2
BCLK
Byte write strobe mode
tAD
tAD
tAD
tAD
tBCD
tBCD
tCSD
tCSD
A23 to A0
1-write strobe mode
A23 to A1
BC3# to BC0#
Common to both byte write strobe
mode and 1-write strobe mode
CS7# to CS0#
tWRD
tWRD
WR3# to WR0#, WR# (Write)
tWDD
tWDH
D31 to D0 (Write)
Note1. Be sure to specify WDON and WDOFF as at least one cycle of BCLK.
Figure 5.20
External Bus Timing/Normal Write Cycle (Bus Clock Synchronized)
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May 19, 2014
Page 119 of 154
RX630 Group
5. Electrical Characteristics
CSRWAIT:2
CSON:0
CSPRWAIT:2
CSPRWAIT:2
RDON:1
RDON:1
TW1
TW2
Tend
CSROFF:2
CSROFF:2
RDON:1
Tpw1
Tpw2
Tend
Tpw1
Tpw2
Tend
Tn1
Tn2
Tend
Tn1
Tn2
BCLK
Byte write strobe mode
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tAD
A23 to A0
1-write strobe mode
A23 to A1
tBCD
tBCD
tCSD
tCSD
BC3# to BC0#
Common to both byte write strobe
mode and 1-write strobe mode
CS7# to CS0#
tRSD
tRSD
tRSD
tRSD
tRSD
tRSD
tRSD
tRSD
RD# (Read)
tRDS
tRDH
tRDS
tRDH
tRDS
tRDH
tRDS
tRDH
D31 to D0 (Read)
Figure 5.21
External Bus Timing/Page Read Cycle (Bus Clock Synchronized)
CSPWWAIT:2
CSWWAIT:2
WRON:1
WDON:1*1
CSON:0 TW1
WDOFF:1*1
TW2
Tend
Tdw1
WRON:1
WDON:1*1
Tpw1
CSPWWAIT:2
WDOFF:1*1
Tpw2
Tend
Tdw1
WRON:1
WDON:1*1
Tpw1
CSWOFF:2
WDOFF:1*1
Tpw2
Tend
Tn1
Tn2
BCLK
Byte write strobe mode
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tAD
A23 to A0
1-write strobe mode
A23 to A1
tBCD
tBCD
tCSD
tCSD
BC3# to BC0#
Common to both byte write strobe
mode and 1-write strobe mode
CS7# to CS0#
tWRD
tWRD
tWRD
tWRD
tWRD
tWRD
WR3# to WR0#, WR# (Write)
tWDD
tWDH
tWDD
tWDH
tWDD
tWDH
D31 to D0 (Write)
Note 1. Be sure to specify WDON and WDOFF as at least one cycle of BCLK.
Figure 5.22
External Bus Timing/Page Write Cycle (Bus Clock Synchronized)
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RX630 Group
5. Electrical Characteristics
CSRWAIT:3
CSWWAIT:3
TW1
TW2
TW3
(Tend)
Tend
Tn1
Tn2
BCLK
A23 to A0
CS7# to CS0#
RD# (Read)
WR# (Write)
External wait
tWTS tWTH
tWTS tWTH
WAIT#
Figure 5.23
External Bus Timing/External Wait Control
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5. Electrical Characteristics
5.3.6
Timing of On-Chip Peripheral Modules
Table 5.16
Timing of On-Chip Peripheral Modules (1)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
PCLK = 8 to 50 MHz
Ta = Topr
High drive output is selected by the drive capacity control register.
Symbol
Min.
Max.
Unit*1
Test
Conditions
tPRW
1.5
—
tPcyc
Figure 5.24
tTICW
1.5
—
tPcyc
Figure 5.25
2.5
—
1.5
—
tPcyc
Figure 5.26
Both-edge
setting
2.5
—
Phase counting
mode
2.5
—
tPOEW
1.5
—
tPcyc
Figure 5.27
tTMCWH,
tTMCWL
1.5
—
tPcyc
Figure 5.28
2.5
—
4
—
tPcyc
Figure 5.29
6
—
Item
I/O ports
Input data pulse width
MTU/TPU
Input capture input pulse
width
Single-edge
setting
Both-edge
setting
Timer clock pulse width
POE
POE# input pulse width
8-bit timer
Timer clock pulse width
Single-edge
setting
Single-edge
setting
tTCKWH,
tTCKWL
Both-edge
setting
SCI
Input clock cycle
Asynchronous
tScyc
Clock
synchronous
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
—
20
ns
Input clock fall time
tSCKf
—
20
ns
tScyc
16
—
tPcyc
4
—
Output clock cycle
Asynchronous
Clock
synchronous
A/D
converter
Output clock pulse width
tSCKW
0.4
0.6
tScyc
Output clock rise time
tSCKr
—
20
ns
Output clock fall time
tSCKf
—
20
ns
Transmit data delay time
Clock
synchronous
tTXD
—
40
ns
Receive data setup time
Clock
synchronous
tRXS
40
—
ns
Receive data hold time
Clock
synchronous
tRXH
40
—
ns
tTRGW
1.5
—
tPcyc
1.5
—
10-bit A/D converter trigger input pulse width
12-bit A/D converter trigger input pulse width
Figure 5.30
Figure 5.31
Note 1. tPcyc: PCLK cycle
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 122 of 154
RX630 Group
Table 5.17
5. Electrical Characteristics
Timing of On-Chip Peripheral Modules (2)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V*1, VREFH0 = 3.0 V to AVCC0*1,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V,
PCLK = 8 to 50 MHz,
Ta = Topr
High drive output is selected by the drive capacity control register.
Item
RSPI
RSPCK clock cycle
Master
Symbol
Min.
Max.
Unit*2
Test Conditions
tSPcyc
2
4096
tPcyc
8
4096
C = 30PF,
Figure 5.32
(tSPcyc – tSPCKR
– tSPCKF) / 2 – 3
—
(tSPcyc – tSPCKR
– tSPCKF) / 2
—
(tSPcyc – tSPCKR
– tSPCKF) / 2 – 3
—
(tSPcyc – tSPCKR
– tSPCKF) / 2
—
tSPCKr,
tSPCKf
—
5
ns
—
1
μs
tSU
15
—
ns
20
—
20 – tPcyc
—
0
—
20 + 2 × tPcyc
—
Slave
RSPCK clock high pulse
width
Master
tSPCKWH
Slave
RSPCK clock low pulse
width
Master
tSPCKWL
Slave
RSPCK clock rise/fall time
Output
Input
Data input setup time
Master
VCC 3.0 V
VCC < 3.0 V
Slave
Data input hold time
Master
tH
Slave
SSL setup time
Master
Master
Master
8
tSPcyc
—
tPcyc
tLAG
1
8
tSPcyc
4
—
tPcyc
tOD
—
18
ns
—
3 × tPcyc + 40
Slave
Data output hold time
Master
tOH
Slave
Successive transmission
delay time
Master
tTD
Slave
—
0
—
tSPcyc + 2 × tPcyc
8 × tSPcyc
+ 2 × tPcyc
4 × tPcyc
—
ns
ns
—
5
ns
—
1
μs
tSSLr,
tSSLf
—
5
ns
—
1
μs
Slave access time
tSA
—
4
tPcyc
Slave output release time
tREL
—
3
tPcyc
MOSI and MISO rise/
fall time
SSL rise/fall time
Output
tDr, tDf
0
Input
Output
Input
C = 30PF,
Figure 5.33 to
Figure 5.36
ns
4
Slave
Data output delay time
ns
1
tLEAD
Slave
SSL hold time
ns
C = 30PF,
Figure 5.35 and
Figure 5.36
Note 1. When operation at 3.0 V or a lower voltage is needed, please contact a Renesas sales office.
Note 2. tPcyc: PCLK cycle
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 123 of 154
RX630 Group
Table 5.18
5. Electrical Characteristics
Timing of On-Chip Peripheral Modules (3)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
PCLK = 8 to 50 MHz
Ta = Topr
High drive output is selected by the drive capacity control register.
Item
Simple
SPI
SCK clock cycle output (master)
Symbol
Min.
Max.
Unit*1
Test Conditions
tSPcyc
4
65536
tPcyc
Figure 5.32
8
65536
SCK clock cycle input (slave)
SCK clock high pulse width
tSPCKWH
0.4
0.6
tSPcyc
SCK clock low pulse width
tSPCKWL
0.4
0.6
tSPcyc
SCK clock rise/fall time
tSPCKr, tSPCKf
—
20
ns
Data input setup time
tSU
40
—
ns
Data input hold time
tH
40
—
ns
SS input setup time
tLEAD
1
—
tSPcyc
SS input hold time
tLAG
1
—
tSPcyc
Data output delay time
tOD
—
40
ns
Data output hold time
tOH
–10
—
ns
Data rise/fall time
tDr, tDf
—
20
ns
SS input rise/fall time
tSSLr, tSSLf
—
20
ns
Slave access time
tSA
—
5
tPcyc
Slave output release time
tREL
—
5
tPcyc
Figure 5.33 to
Figure 5.36
Figure 5.35 and
Figure 5.36
Note 1. tPcyc: PCLK cycle
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May 19, 2014
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RX630 Group
Table 5.19
5. Electrical Characteristics
Timing of On-Chip Peripheral Modules (4)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
PCLK = 8 to 50 MHz
Ta = Topr
High drive output is selected by the drive capacity control register.
Symb
ol
Min.*1,*2
Max.
Unit
Test
Conditions
tSCL
6(12) × tIICcyc + 1300
—
ns
Figure 5.37
SCL input high pulse width
tSCLH
3(6) × tIICcyc + 300
—
ns
SCL input low pulse width
tSCLL
3(6) × tIICcyc + 300
—
ns
Item
RIIC
(Standard-mode,
SMBus)
ICFER.FMPE = 0
RIIC
(Fast-mode)
SCL input cycle time
SCL, SDA input rise time
tSr
—
1000
ns
SCL, SDA input fall time
tSf
—
300
ns
SCL, SDA input spike pulse removal time
tSP
0
1(4) × tIICcyc
ns
SDA input bus free time
tBUF
3(6) × tIICcyc + 300
—
ns
Start condition input hold time
tSTAH
tIICcyc + 300
—
ns
Restart condition input setup time
tSTAS
1000
—
ns
Stop condition input setup time
tSTOS
1000
—
ns
Data input setup time
tSDAS
tIICcyc + 50
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb
—
400
pF
SCL input cycle time
tSCL
6(12) × tIICcyc + 600
—
ns
SCL input high pulse width
tSCLH
3(6) × tIICcyc + 300
—
ns
SCL input low pulse width
tSCLL
3(6) × tIICcyc + 300
—
ns
SCL, SDA input rise time
tSr
20 + 0.1Cb
300
ns
SCL, SDA input fall time
tSf
20 + 0.1Cb
300
ns
SCL, SDA input spike pulse removal time
tSP
0
1(4) × tIICcyc
ns
SDA input bus free time
tBUF
3(6) × tIICcyc + 300
—
ns
Start condition input hold time
tSTAH
tIICcyc + 300
—
ns
Restart condition input setup time
tSTAS
300
—
ns
Stop condition input setup time
tSTOS
300
—
ns
Data input setup time
tSDAS
tIICcyc + 50
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb
—
400
pF
Note:
tIICcyc: RIIC internal reference clock (IIC) Cycle
Note 1. The value within parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 11b while the digital filter is enabled by
the setting ICFER.NFE = 1.
Note 2. Cb is the total capacitance of the bus lines.
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May 19, 2014
Page 125 of 154
RX630 Group
Table 5.20
5. Electrical Characteristics
Timing of On-Chip Peripheral Modules (5)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
PCLK = 8 to 50 MHz
Ta = Topr
High drive output is selected by the drive capacity control register.
Symbol
Min.*, *2
Max.*
Unit
SCL input cycle time
tSCL
6(12) × tIICcyc + 240
—
ns
Item
RIIC
(Fast-mode+)
ICFER.FMPE = 1
Simple IIC
(Standard-mode)
Simple IIC
(Fast-mode)
SCL input high pulse width
tSCLH
3(6) × tIICcyc + 120
—
ns
SCL input low pulse width
tSCLL
3(6) × tIICcyc + 120
—
ns
SCL, SDA input rise time
tSr
—
120
ns
SCL, SDA input fall time
tSf
—
120
ns
SCL, SDA input spike pulse removal time
tSP
0
1(4) × tIICcyc
ns
SDA input bus free time
tBUF
3(6) × tIICcyc + 120
—
ns
Start condition input hold time
tSTAH
tIICcyc + 120
—
ns
Restart condition input setup time
tSTAS
120
—
ns
Stop condition input setup time
tSTOS
120
—
ns
Data input setup time
tSDAS
tIICcyc + 120
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb
—
550
pF
SDA input rise time
tSr
—
1000
ns
SDA input fall time
tSf
—
300
ns
SDA input spike pulse removal time
tSP
0
4 × tIICcyc
ns
Data input setup time
tSDAS
250
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb
—
400
pF
SCL, SDA input rise time
tSr
20 + 0.1Cb
300
ns
SCL, SDA input fall time
tSf
20 + 0.1Cb
300
ns
SCL, SDA input spike pulse removal time
tSP
0
4 × tIICcyc
ns
Data input setup time
tSDAS
100
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb
—
400
pF
Test
Conditions
Figure
5.37
Note:
tIICcyc: RIIC internal reference clock (IIC) Cycle, tPcyc: PCLK cycle
Note 1. The value in parentheses is used when ICMR3.NF[1:0] are set to 11b while a digital filter is enabled with ICFER.NFE = 1.
Note 2. Cb indicates the total capacity of the bus line.
PCLK
Port
tPRW
Figure 5.24
I/O Port Input Timing
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May 19, 2014
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RX630 Group
5. Electrical Characteristics
PCLK
Output compare
output
Input capture
input
Figure 5.25
tTICW
MTU Input/Output Timing
PCLK
MTCLKA to
MTCLKH
tTCKWL
Figure 5.26
tTCKWH
MTU Clock Input Timing
PCLK
POEn# input
tPOEW
Figure 5.27
POE# Input Timing
PCLK
TMCI0 to TMCI3
tTMCWL
Figure 5.28
tTMCWH
8-Bit Timer Clock Input Timing
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May 19, 2014
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RX630 Group
5. Electrical Characteristics
tSCKW
tSCKr
tSCKf
SCKn
(n = 0 to 12)
tScyc
Figure 5.29
SCK Clock Input Timing
SCKn
tTXD
TxDn
tRXS tRXH
RxDn
n = 0 to 12
Figure 5.30
SCI Input/Output Timing: Clock Synchronous Mode
PCLK
ADTRG0#-A/B
ADTRG1#
tTRGW
Figure 5.31
A/D Converter External Trigger Input Timing
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May 19, 2014
Page 128 of 154
RX630 Group
5. Electrical Characteristics
RSPI
Simple SPI
RSPCKm
Master select
output
SCKn
Master select
output
tSPCKr
tSPCKWH
VOH
VOH
tSPCKf
VOH
VOH
VOL
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
RSPCKm
Slave select input
SCKn
Slave select input
(m = A to C)
(n = 0 to 12)
VIH
VIH
VIL
tSPCKf
VIH
VIH
VIL
tSPCKWL
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Figure 5.32
RSPI
RSPI Clock Timing and Simple SPI Clock Timing
Simple SPI
tTD
SSLm0 to SSLm3
output
tLEAD
RSPCKm
CPOL = 0
output
SCKn
CKPOL = 0
output
RSPCKm
CPOL = 1
output
SCKn
CKPOL = 1
output
tSSLr, tSSLf
tSU
MISOm input
SMISOm input
MOSIm input
SMOSIm input
(m = A to C)
(n = 0 to 12)
tLAG
tH
MSB IN
tDr, tDf
tOH
MSB OUT
Figure 5.33
DATA
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
RSPI Timing (Master, CPHA = 0) and Simple SPI Timing (Master, CKPH = 1)
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May 19, 2014
Page 129 of 154
RX630 Group
RSPI
5. Electrical Characteristics
Simple SPI
tTD
SSLm0 to SSLm3
output
tLEAD
RSPCKm
CPOL = 0
output
SCKn
CKPOL = 1
output
RSPCKm
CPOL = 1
output
SCKn
CKPOL = 0
output
tLAG
tSSLr, tSSLf
tSU
MISOm input
SMISOm input
tH
MSB IN
DATA
tOH
MOSIm output
SMOSIm output
(m = A to C)
(n = 0 to 12)
Figure 5.34
LSB IN
tOD
MSB IN
tDr, tDf
MSB OUT
DATA
LSB OUT
IDLE
MSB OUT
RSPI Timing (Master, CPHA = 1) and Simple SPI Timing (Master, CKPH = 0)
RSPI
Simple SPI
SSLm0
input
SSLn#
input
RSPCKm
CPOL = 0
input
SCKn
CKPOL = 0
input
RSPCKm
CPOL = 1
input
SCKn
CKPOL = 1
input
tTD
tLEAD
tLAG
tSA
MISOm output
SMISOm output
MOSIm input
SMOSIm input
(m = A to C)
(n = 0 to 12)
tOH
MSB OUT
tSU
DATA
tREL
LSB OUT
tH
MSB IN
Figure 5.35
tOD
MSB IN
MSB OUT
tDr, tDf
DATA
LSB IN
MSB IN
RSPI Timing (Slave, CPHA = 0) and Simple SPI Timing (Slave, CKPH = 1)
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 130 of 154
RX630 Group
5. Electrical Characteristics
RSPI
Simple SPI
SSLm0
input
SSLn#
input
RSPCKm
CPOL = 0
input
SCKn
CKPOL = 1
input
RSPCKm
CPOL = 1
input
SCKn
CKPOL = 0
input
tTD
tLEAD
tLAG
tSA
MISOm output
SMISOm output
tOH
tOD
LSB OUT
(Last data)
MSB OUT
tSU
MOSIm input
SMOSIm input
(m = A to C)
(n = 0 to 12)
Figure 5.36
tREL
DATA
tH
MSB IN
MSB OUT
LSB OUT
tDr, tDf
DATA
LSB IN
MSB IN
RSPI Timing (Slave, CPHA = 1) and Simple SPI Timing (Slave, CKPH = 0)
VIH
SDA0 to SDA3
VIL
tBUF
tSCLH
tSTAS
tSTAH
tSTOS
tSP
SCL0 to SCL3
P *1
tSCLL
tSr
tSf
tSCL
tSDAS
tSDAH
Note 1. S, P, and Sr indicate the following conditions.
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 5.37
P *1
Sr *1
S *1
Test conditions
VIH = VCC × 0.7, VIL = VCC × 0.3
RIIC Bus Interface Input/Output Timing and Simple IIC Bus Interface Input/Output
Timing
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May 19, 2014
Page 131 of 154
RX630 Group
5.4
5. Electrical Characteristics
USB Characteristics
Table 5.21
On-Chip USB Full-Speed Characteristics (DP and DM Pin Characteristics)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
PCLK = 24 to 50 MHz
Ta = Topr
High drive output is selected by the drive capacity control register.
Item
Input
characteristics
Output
characteristics
Symbol
Min.
Max.
Unit
Input high level voltage
VIH
2.0
—
V
Input low level voltage
VIL
—
0.8
V
Differential input sensitivity
VDI
0.2
—
V
Differential common mode range
VCM
0.8
2.5
V
Output high level voltage
VOH
2.8
3.6
V
IOH = –200 µA
IOL = 2 mA
| DP – DM |
Output low level voltage
VOL
0.0
0.3
V
Cross-over voltage
VCRS
1.3
2.0
V
Rise time
tLr
4
20
ns
Fall time
tLf
4
20
ns
Rise/fall time ratio
tLr / tLf
90
111.11
%
tLr / tLf
Output resistance
ZDRV
28
44
Ω
Rs = 22 Ω
included
DP, DM
90%
VCRS
Figure 5.38
90%
10%
10%
tLr
Figure 5.38
Test Conditions
tLf
DP and DM Output Timing (Full-Speed)
dp
22
Observation
point
50 pF
dm
22
50 pF
Figure 5.39
Test Circuit (Full-Speed)
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May 19, 2014
Page 132 of 154
RX630 Group
5.5
5. Electrical Characteristics
A/D Conversion Characteristics
Table 5.22
10-Bit A/D Conversion Characteristics
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
PCLK = 8 to 50 MHz
Ta = Topr
Item
Resolution
Conversion
time*1
(Operation at
PCLK = 50
MHz)
enough*2
Min.
Typ.
Max.
Unit
10
3.0
10
10
Bit
(2.5)*3
—
—
µs
Test
Conditions
Sampling
in 125
states
With 0.1-µF
external
capacitor
When the capacitor is charged
Without 0.1-µF
external
capacitor
Permissible signal source
impedance (max.) = 1.0 kΩ, VCC 3.0 V
1.5 (1.0)*3
—
—
Sampling
in 50
states
Permissible signal source
impedance (max.) = 1.0 kΩ, VCC 2.7 V
3.5 (3.0)*3
—
—
Sampling
in 150
states
Permissible signal source
impedance (max.) = 5.0 kΩ, VCC 3.0 V
2.0 (1.5)*3
—
—
Sampling
in 75
states
Permissible signal source
impedance (max.) = 5.0 kΩ, VCC 2.7 V
4.0 (3.5)*3
—
—
Sampling
in 175
states
—
—
6.0
Analog input capacitance
pF
Offset error
—
±1.5
±3.0
LSB
Full-scale error
—
±1.5
±3.0
LSB
Quantization error
—
±0.5
—
LSB
Absolute accuracy
—
±1.5
±3.0
LSB
DNL differential nonlinearity error
—
±0.5
±1.0
LSB
INL integral nonlinearity error
—
±1.5
±3.0
LSB
Note:
The above specification values apply when there is no access to the external bus during A/D conversion. If access proceeds
during A/D conversion, values may not fall within the above ranges.
Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states
is indicated.
Note 2. The scanning is not supported.
Note 3. The value in parentheses indicates the sampling time.
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 133 of 154
RX630 Group
Table 5.23
5. Electrical Characteristics
12-Bit A/D Conversion Characteristics
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
PCLK = 8 to 50 MHz
Ta = Topr
Item
Resolution
Conversion
time*1
(Operation
at PCLK =
50 MHz)
Min.
Typ.
Max.
Unit
12
Test
Conditions
12
12
Bit
(0.4)*2
—
—
µs
Sampling
in 20
states
AN0 to AN7
Permissible signal source impedance
(max.) = 1.0 kΩ
1.0
Other channels
Permissible signal source impedance
(max.) = 1.0 kΩ, AVCC 3.0 V
2.0 (1.4)*2
—
—
µs
Sampling
in 70
states
Permissible signal source impedance
(max.) = 1.0 kΩ, AVCC 2.7 V
5.6 (5.0)*2
—
—
µs
Sampling
in 250
states
Analog input capacitance
—
—
30
pF
Offset error
—
±2.0
±7.5
LSB
Full-scale error
—
±2.0
±7.5
LSB
Quantization error
—
±0.5
—
LSB
Absolute accuracy
—
±2.5
±8.0
LSB
DNL differential nonlinearity error
—
±2.0
±4.0
LSB
INL integral nonlinearity error
—
±2.0
±4.0
LSB
Note:
The above specification values apply when there is no access to the external bus during A/D conversion. If access proceeds
during A/D conversion, values may not fall within the above ranges.
Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states
is indicated.
Note 2. The value in parentheses indicates the sampling time.
Table 5.24
A/D Internal Reference Voltage Characteristics
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
PCLK = 8 to 50 MHz
Ta = Topr
Item
A/D Internal reference voltage
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Min.
Typ.
Max.
Unit
1.45
1.50
1.55
V
Test
Conditions
Page 134 of 154
RX630 Group
5.6
5. Electrical Characteristics
D/A Conversion Characteristics
Table 5.25
D/A Conversion Characteristics
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to VCC
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
Ta = Topr
Item
Min.
Typ.
Max.
Unit
Test Conditions
Resolution
10
10
10
Bit
Conversion time
—
—
3.0
µs
20-pF capacitive load
Absolute accuracy
—
±2.0
±4.0
LSB
2-MΩ resistive load
—
—
±3.0
LSB
4-MΩ resistive load
—
—
±2.0
LSB
10-MΩ resistive load
—
3.6
—
kΩ
RO output resistance
5.7
Temperature Sensor Characteristics
Table 5.26
Temperature Sensor Characteristics
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to VCC
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
Ta = Topr
Item
Min.
Typ.
Max.
Unit
Relative accuracy
―
±1
―
°C
Temperature slope
―
4.1
―
mV/°C
Output voltage (@25°C)
―
1.26
―
V
Temperature sensor start time
―
―
30
µs
Sampling time
―
―
5
µs
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Test
Conditions
Page 135 of 154
RX630 Group
5.8
5. Electrical Characteristics
Power-on Reset Circuit and Voltage Detection Circuit Characteristics
Table 5.27
Power-on Reset Circuit and Voltage Detection Circuit Characteristics
Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
Ta = Topr
Item
Voltage detection
level
Power-on reset
(POR)
Low power
consumption
function disabled
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
VPOR
2.5
2.6
2.7
V
Figure 5.40
2.0
2.35
2.7
Low power
consumption
function enabled
Voltage detection circuit (LVD0)
Vdet0
2.7
2.80
2.9
Voltage detection circuit (LVD1)
Vdet1_A
2.75
2.95
3.15
Figure 5.41
Voltage detection circuit (LVD2)
Vdet2_A
2.75
2.95
3.15
Power-on reset time
tPOR
—
4.6
—
LVD0 reset time
tLVD0
—
4.6
—
Figure 5.41
LVD1 reset time
tLVD1
—
0.9
—
Figure 5.42
LVD2 reset time
tLVD2
—
0.9
—
Figure 5.43
Minimum VCC down time
tVOFF
200
—
—
µs
Figure 5.40 and
Figure 5.41
Response delay time
tdet
—
—
200
µs
Figure 5.40 to
Figure 5.43
LVD operation stabilization time (after LVD is enabled)
Td(E-A)
—
—
3
µs
Hysteresis width (LVD1 and LVD2)
V LVH
—
80
—
mV
Figure 5.42 and
Figure 5.43
Internal reset time
Note:
ms
Figure 5.40
The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet1,
and Vdet2 for the POR/ LVD.
tVOFF
VPOR
VCC
Internal reset signal
(active-low)
tdet
Figure 5.40
tPOR
tdet
tdet
tPOR
Power-on Reset Timing
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 136 of 154
RX630 Group
5. Electrical Characteristics
tVOFF
VCC
Vdet0
Internal reset signal
(active-low)
tdet
Figure 5.41
tLVD0
Voltage Detection Circuit Timing (Vdet0)
tVOFF
VCC
VLVH
Vdet1
LVD1E
Td(E-A)
LVD1
Comparator output
LVD1CMPE
LVD1MON
Internal reset signal
(active-low)
When LVD1RN = L
tdet
tdet
tLVD1
When LVD1RN = H
tLVD1
Figure 5.42
Voltage Detection Circuit Timing (Vdet1)
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 137 of 154
RX630 Group
5. Electrical Characteristics
tVOFF
VCC
VLVH
Vdet2
LVD2E
Td(E-A)
LVD2
Comparator output
LVD2CMPE
LVD2MON
Internal reset signal
(active-low)
When LVD2RN = L
tdet
tdet
tLVD2
When LVD2RN = H
tLVD2
Figure 5.43
Voltage Detection Circuit Timing (Vdet2)
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 138 of 154
RX630 Group
5.9
5. Electrical Characteristics
Oscillation Stop Detection Timing
Table 5.28
Oscillation Stop Detection Circuit Characteristics
Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
Detection time
tdr
—
—
1
ms
Figure 5.44
Main clock or
PLL clock
tdr
OSTDSR.OSTDF
LOCO clock
ICLK
Figure 5.44
Oscillation Stop Detection Timing
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 139 of 154
RX630 Group
5.10
5. Electrical Characteristics
Battery Backup Function Characteristics
Table 5.29
Battery Backup Function Characteristics
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VBATT = 2.3 to 3.6 V
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
V
Figure 5.45
Voltage level for switching to battery backup
VDETBATT
2.50
2.60
2.70
Lower-limit VBATT voltage for power supply switching due to
VCC voltage drop
VBATTSW
2.70
—
—
VCC-off period for starting power supply switching
tVOFFBATT
200
—
—
Note:
μs
The VCC-off period for starting power supply switching indicates the period in which VCC is below the minimum value of the
voltage level for switching to battery backup (VDETBATT).
tVOFFBATT
VCC
VDETBATT
VBATT
VBATT
Switching prohibited
VCC voltage
guaranteed range
VCC
Return from battery
backup not possible
VBATTSW
Backup power
area
VCC supply
VBATT
Switching prohibited
VBATT supply
VBATT voltage
guaranteed range
VCC supply
Note. When VCC falls below VDETBATT, the voltage for switching to battery backup, make sure that VCC does not rise
above VDETBATT during the VCC-off period required to start switching between power supplies.
The VBATT voltage when the supplied power source switches from Vcc to V BATT should not be lower than VBATTSW,
the lower-limit VBATT voltage for switching between power supplies due to a drop in the VCC voltage.
Figure 5.45
Battery Backup Function Characteristics
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 140 of 154
RX630 Group
5.11
5. Electrical Characteristics
ROM (Flash Memory for Code Storage) Characteristics
Table 5.30
ROM (Flash Memory for Code Storage) Characteristics (1)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
Temperature range for the programming/erasure operation: Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
Reprogram/erase cycle*1
NPEC
1000
—
—
Times
Data hold time
tDRP
30*2
—
—
Year
Test Conditions
Ta = +85°C
Note 1. Definition of reprogram/erase cycle:
The reprogram/erase cycle is the number of erasing for each block. When the reprogram/erase cycle is n times (n = 1000),
erasing can be performed n times for each block. For instance, when 256-byte programming is performed 16 times for different
addresses in 4-Kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address for several times as one erasing is not enabled (overwriting is prohibited).
Note 2. The value is obtained from the reliability test.
Table 5.31
ROM (Flash Memory for Code Storage) Characteristics (2)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
Temperature range for the programming/erasure operation: Ta = Topr
Item
Programming time
NPEC 100 times
Symbol
20 MHz ≤ FCLK ≤ 50 MHz
FCLK = 4 MHz
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
128 bytes
tP128
—
2.8
28
—
1
10
ms
4 Kbytes
tP4K
—
63
140
—
23
50
ms
16 Kbytes
tP16K
—
252
560
—
90
200
ms
128 bytes
tP128
—
3.4
33.6
—
1.2
12
ms
4 Kbytes
tP4K
—
75.6
168
—
27.6
60
ms
16 Kbytes
tP16K
—
302.4
672
—
108
240
ms
4 Kbytes
tE4K
—
50
120
—
25
60
ms
16 Kbytes
tE16K
—
200
480
—
100
240
ms
4 Kbytes
tE4K
—
60
144
—
30
72
ms
16 Kbytes
tE16K
—
240
576
—
120
288
ms
Suspend delay time during programming
tSPD
—
—
400
—
—
120
μs
First suspend delay time during erasure
(in suspend priority mode)
tSESD1
—
—
300
—
—
120
μs
Second suspend delay time during erasure
(in suspend priority mode)
tSESD2
—
—
1.7
—
—
1.7
ms
Suspend delay time during erasure
(in erasure priority mode)
tSEED
—
—
1.7
—
—
1.7
ms
FCU reset time
tFCUR
35
—
—
35
—
—
μs
Programming time
NPEC > 100 times
Erasure time
NPEC 100 times
Erasure time
NPEC > 100 times
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 141 of 154
RX630 Group
5.12
5. Electrical Characteristics
E2 Flash Characteristics
Table 5.32
E2 Flash Characteristics (1)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
Temperature range for the programming/erasure operation: Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
Reprogram/erase cycle*1
NDPEC
100000
—
—
Times
Data hold time
tDDRP
30*2
—
—
Year
Test Conditions
Ta = +85°C
Note 1. Definition of reprogram/erase cycle:
The reprogram/erase cycle is the number of erasing for each block. When the reprogram/erase cycle is n times (n = 100000),
erasing can be performed n times for each block. For instance, when 128-byte programming is performed 16 times for different
addresses in 2-Kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address for several times as one erasing is not enabled (overwriting is prohibited).
Note 2. This value is based on the result of the reliability test.
Table 5.33
E2 Flash Characteristics (2)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
Temperature range for the programming/erasure operation: Ta = Topr
Item
Symbol
FCLK = 4 MHz
20 MHz ≤ FCLK ≤ 50 MHz
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Programming time
NDPEC 100 times
2 bytes
tDP2
—
0.7
6
—
0.25
2
ms
Programming time
NDPEC > 100 times
2 bytes
tDP2
—
0.7
6
—
0.25
2
ms
Erasure time
NDPEC 100 times
32 bytes
tDE32
—
4
40
—
2
20
ms
Erasure time
NDPEC > 100 times
32 bytes
tDE32
—
7
40
—
4
20
ms
Blank check time
2 bytes
tDBC2
—
—
100
—
—
30
μs
Suspend delay time during programming
tDSPD
—
—
250
—
—
120
μs
First suspend delay time during erasure
(in suspend priority mode)
tDSESD1
—
—
250
—
—
120
μs
Second suspend delay time during erasure
(in suspend priority mode)
tDSESD2
—
—
500
—
—
300
μs
Suspend delay time during erasure
(in erasure priority mode)
tDSEED
—
—
500
—
—
300
μs
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 142 of 154
RX630 Group
5. Electrical Characteristics
• Suspension during programming
FCU command
Program
Suspend
tSPD
FSTATR0.FRDY
Ready
Programming pulse
Not Ready
Ready
Programming
• Suspension during erasure in suspend priority mode
FCU command
Erase
Suspend
Resume
Suspend
tSESD1
FSTATR0.FRDY
Ready
Erasure pulse
Not Ready
tSESD2
Ready
Erasing
Not Ready
Erasing
• Suspension during erasure in erasure priority mode
FCU command
Erase
Suspend
tSEED
FSTATR0.FRDY
Ready
Erasure pulse
Figure 5.46
Not Ready
Ready
Erasing
Flash Memory Program/Erase Suspend Timing
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 143 of 154
RX630 Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
JEITA Package Code
P-TFLGA177-8x8-0.50
RENESAS Code
PTLG0177KA-A
w S B
Information on the latest version of the package dimensions or mountings has been displayed in “Packages” on Renesas
Electronics Corporation website.
D
Previous Code
177F0E-A
MASS[Typ.]
0.2g
φ b1
φ × M S AB
φb
w S A
φ × M S AB
e
ZD
A
A
e
R
P
N
M
L
K
B
E
J
H
G
F
E
D
C
B
y S
x4
v
Index mark
(Laser mark)
S
ZE
A
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Reference Dimension in Millimeters
Symbol
Min
D
E
v
w
A
e
b
b1
x
y
ZD
ZE
Nom
8.0
8.0
Max
0.15
0.20
1.05
0.21
0.29
0.5
0.25
0.34
0.29
0.39
0.08
0.08
0.5
0.5
Figure A 177-Pin TFLGA (PTLG0177KA-A)
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 144 of 154
RX630 Group
Appendix 1. Package Dimensions
Figure B 176-Pin LFBGA (PLBG0176GA-A)
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 145 of 154
RX630 Group
Appendix 1. Package Dimensions
JEITA Package Code
P-LQFP176-24x24-0.50
RENESAS Code
PLQP0176KB-A
Previous Code
176P6Q-A / FP-176E / FP-176EV
MASS[Typ.]
1.8g
HD
*1
D
132
89
88
133
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
bp
c
c1
HE
Reference Dimension in Millimeters
Symbol
*2
E
b1
176
45
c
F
A
Index mark
A1
ZD
44
A2
1
ZE
Terminal cross section
e
y
*3 b
L
L1
p
x
Detail F
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
e
x
y
ZD
ZE
L
L1
Min Nom Max
23.9 24.0 24.1
23.9 24.0 24.1
1.4
25.8 26.0 26.2
25.8 26.0 26.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.10
1.25
1.25
0.35 0.5 0.65
1.0
Figure C 176-Pin LQFP (PLQP0176KB-A)
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 146 of 154
RX630 Group
Appendix 1. Package Dimensions
JEITA Package Code
P-TFLGA145-7x7-0.50
RENESAS Code
PTLG0145KA-A
Previous Code
145F0G
MASS[Typ.]
0.1g
w S B
b1
D
S AB
b
S AB
w S A
ZD
A
e
e
N
M
L
K
J
E
H
G
F
E
D
C
B
y S
x4
v
Index mark
(Laser mark)
ZE
A
1
2
3
4
5
6
7
8
9
10 11 12 13
Reference Dimension in Millimeters
Symbol
Min
D
E
v
w
A
e
b
b1
x
y
ZD
ZE
Nom Max
7.0
7.0
0.15
0.20
1.05
0.5
0.21 0.25 0.29
0.29 0.34 0.39
0.08
0.10
0.5
0.5
Figure D 145-Pin TFLGA (PTLG0145KA-A)
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 147 of 154
RX630 Group
Appendix 1. Package Dimensions
JEITA Package Code
P-LQFP144-20x20-0.50
RENESAS Code
PLQP0144KA-A
Previous Code
144P6Q-A / FP-144L / FP-144LV
MASS[Typ.]
1.2g
HD
*1
D
108
73
109
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
72
bp
c
HE
Reference Dimension in Millimeters
Symbol
*2
E
c1
b1
36
A
1
ZD
Index mark
c
37
A2
144
ZE
Terminal cross section
A1
F
L
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
L1
*3
e
y
bp
x
Detail F
e
x
y
ZD
ZE
L
L1
Min Nom Max
19.9 20.0 20.1
19.9 20.0 20.1
1.4
21.8 22.0 22.2
21.8 22.0 22.2
1.7
0.05 0.1 0.15
0.17 0.22 0.27
0.20
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.10
1.25
1.25
0.35 0.5 0.65
1.0
Figure E 144-Pin LQFP (PLQP0144KA-A)
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 148 of 154
RX630 Group
Appendix 1. Package Dimensions
JEITA Package Code
P-TFLGA100-5.5x5.5-0.50
RENESAS Code
PTLG0100KA-A
Previous Code
100F0M
MASS[Typ.]
0.1g
φ b1
φ× M S
w S B
φb
D
w S A
AB
φ× M S
ZD
A
AB
e
e
A
K
J
H
G
B
E
F
E
D
C
B
ZE
A
×4
1
v
2
y S
Index mark
Index mark
(Laser mark)
S
3
4
5
6
7
8
9
10
Reference Dimension in Millimeters
Symbol
D
E
v
w
A
e
b
b1
x
y
ZD
ZE
Min Nom Max
5.5
5.5
0.15
0.20
1.05
0.5
0.21 0.25 0.29
0.29 0.34 0.39
0.08
0.10
0.5
0.5
Figure F 100-Pin TFLGA (PTLG0100KA-A)
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 149 of 154
RX630 Group
Appendix 1. Package Dimensions
JEITA Package Code
P-LQFP100-14x14-0.50
RENESAS Code
PLQP0100KB-A
Previous Code
100P6Q-A / FP-100U / FP-100UV
MASS[Typ.]
0.6g
HD
*1
D
51
75
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
50
76
bp
c1
Reference Dimension in Millimeters
Symbol
c
E
*2
HE
b1
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
26
1
ZE
Terminal cross section
100
25
Index mark
ZD
y
e
*3
bp
A1
c
A
A2
F
L
x
L1
Detail F
e
x
y
ZD
ZE
L
L1
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.08
1.0
1.0
0.35 0.5 0.65
1.0
Figure G 100-Pin LQFP (PLQP0100KB-A)
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 150 of 154
RX630 Group
Appendix 1. Package Dimensions
JEITA Package Code
P-LQFP80-12x12-0.50
RENESAS Code
PLQP0080KB-A
Previous Code
80P6Q-A
MASS[Typ.]
0.5g
HD
*1
D
60
41
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
40
61
bp
E
c
*2
HE
c1
b1
Reference Dimension in Millimeters
Symbol
ZE
Terminal cross section
80
21
1
20
ZD
Index mark
F
bp
c
A
*3
A1
y S
e
A2
S
L
x
L1
Detail F
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
e
x
y
ZD
ZE
L
L1
Min Nom Max
11.9 12.0 12.1
11.9 12.0 12.1
1.4
13.8 14.0 14.2
13.8 14.0 14.2
1.7
0.1 0.2
0
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
10°
0.5
0.08
0.08
1.25
1.25
0.3 0.5 0.7
1.0
Figure H 80-Pin LQFP (PLQP0080KB-A)
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 151 of 154
REVISION HISTORY
RX630 Group
REVISION HISTORY
REVISION HISTORY
Rev.
0.50
1.00
Date
Page
—
RX630 Group Datasheet
Description
Summary
May 13, 2011
First Edition issued
Sep 13, 2011 All
1. Overview
2, 4, 6
Table 1.1 Outline of Specifications: Reset, real time clock, package, changed
8 to 9
Table 1.3 List of Products Table, changed
12
Table 1.4 List of Pin Functions: BSCANP pin, added
17
Figure 1.3 Pin Assignments (177-Pin TFLGA), added
18
Figure 1.4 Pin Assignments (176-Pin LFBGA), added
19
Figure 1.5 Pin Assignments (176-Pin LQFP): 16-pin and 18-pin, changed
20
Figure 1.6 Pin Assignments (145-Pin TFLGA), added
21
Figure 1.7 Pin Assignments (144-Pin LQFP): 16-pin, changed
22
Figure 1.8 Pin Assignments (100-Pin TFLGA), added
23
Figure 1.9 Pin Assignments (100-Pin LQFP): 7-pin, changed
25 to 32
Table 1.5 List of Pins and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA), added
41 to 47
Table 1.7 List of Pins and Pin Functions (145-Pin TFLGA), added
55 to 59
Table 1.9 List of Pins and Pin Functions (100-Pin TFLGA), added
4. I/O Registers
75
(1) I/O Register Addresses (Address Order), changed
76
(3) Number of I/O Registers to Access Cycles, changed
77 to 116 Table 5.1 List of I/O Registers, changed
5. Electrical Characteristics
117 to 156 Added
Appendix 1. Port States in Each Processing Mode
157
Figure A. 177-Pin TFLGA (PTLG0177KA-A), added
158
Figure B. 176-Pin LFBGA (PLBG0176GA-A), added
160
Figure D. 145-Pin TFLGA (PTLG0145KA-A), added
162
Figure F. 100-Pin TFLGA (PTLG0100KA-A), added
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 152 of 154
RX630 Group
REVISION HISTORY
Classifications
- Items with Technical Update document number: Changes according to the corresponding issued Technical Update
- Items without Technical Update document number: Minor changes that do not require Technical Update to be issued
Rev.
1.60
Date
Page
May 19. 2014 Features
1
Description
Summary
Operating temp. range, changed
Unique ID, added
1. Overview
All
Name of the on-chip emulator pin, changed: TRSYNC# → TRSYNC
2 to 6
Table 1.1 Outline of Specifications: Reset, real time clock, package, CPU, ROM,
RAM, E2 DataFlash, clock generation circuit, temperature sensor, power
supply voltage, changed. Low power consumption, deleted
Operating temp. range changed, Unique ID and Note 1, added
7
Table 1.2 Comparison of Functions for Different Packages: Unique ID, added
8, 9
Table 1.3 List of Products: Group and Note 1 changed, Operating Temp. Range
and G version added, Note 2 added
10
Figure 1.1 How to Read the Product Part Number: Operating temperature range,
changed
12, 15
Table 1.4 Pin Functions: VCC, VBATT and USB power pins, changed
43 to 45 Table 1.9 List of Pins and Pin Functions (100-Pin TFLGA), changed (pinsTPU6 to
TPU11, and RSPI2 have been deleted)
46 to 48 Table 1.10 List of Pins and Pin Functions (100-Pin LQFP), changed (pinsTPU6 to
TPU11, and RSPI2 have been deleted)
3. Address Space
56
Figure 3.1 Memory Map in Each Operating Mode, changed
4. I/O Registers
63, 76,
Table 4.1 List of I/O Registers (Address Order), changed, Note 9 added
101
5. Electrical Characteristics
All
Characteristics and timing conditions in the tables, changed
102
Table 5.1 Absolute Maximum Ratings: Operating temperature, changed
104
Table 5.3 DC Characteristics (2): Three-state leakage current (off state), Test
conditions, changed; Input pull-up MOS current, changed
105
Table 5.4 DC Characteristics (3) (for D and G Versions (-40 ≤ Ta ≤ +85°C)): Title,
Analog power supply current, Reference power supply current, Note 7, and Note
8, changed
RAM standby voltage, added
106
Table 5.5 DC Characteristics (4) (for G Version (-85 < Ta ≤ +105°C)), added
108 to 131 5.3 AC Characteristics, section structure changed
108
Table 5.7 Operation Frequency Value (High-Speed Operating Mode): Note,
changed
109
Table 5.10 Reset Timing: changed, Note deleted
109
Figure 5.1 Reset Input Timing at Power-On, changed
109
Figure 5.2 Reset Input Timing, changed
110
Table 5.11 Clock Timing (Except for Sub-Clock Related): Item and Table,
changed, Note, added
111
Table 5.12 Clock Timing (Sub-Clock Related): Sub-clock oscillation stabilization
wait offset time, changed, Note, added
112
Figure 5.6 LOCO, IWDTCLK Oscillation Start Timing: Title and figure, changed
112
Figure 5.7 HOCO Oscillation Start Timing (After Reset is Canceled by Setting the
OFS1.HOCOEN Bit to 0), changed
112
Figure 5.8 HOCO Clock Oscillation Start Timing (Oscillation is Started by Setting
the HOCOCR.HCSTP Bit), changed
114
Figure 5.12 Sub-Clock Oscillation Start Timing, changed
115
Figure 5.14 Deep Software Standby Mode Cancellation Timing, changed
116
Table 5.15 Bus Timing, changed
118
Figure 5.19 External Bus Timing/Normal Read Cycle (Bus Clock Synchronized),
changed
119
Figure 5.20 External Bus Timing/Normal Write Cycle (Bus Clock Synchronized),
changed
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Classification
TN-RX*-A092A/E
TN-RX*-A007A/E
TN-RX*-A007A/E
TN-RX*-A048A/E
TN-RX*-A021A/E
TN-RX*-A097A/E
TN-RX*-A097A/E
Page 153 of 154
RX630 Group
Rev.
1.60
Date
May 19. 2014
2.
Page
120
120
121
123
124
125
126
129
129
130
130
131
131
132
133
134
139
140
141
141
142
142
Description
Classification
Summary
Figure 5.21 External Bus Timing/Page Read Cycle (Bus Clock Synchronized),
changed
Figure 5.22 External Bus Timing/Page Write Cycle (Bus Clock Synchronized),
changed
Figure 5.23 External Bus Timing/External Wait Control, changed
Table 5.17 Timing of On-Chip Peripheral Modules (2), changed
Table 5.18 Timing of On-Chip Peripheral Modules (3), changed
Table 5.19 Timing of On-Chip Peripheral Modules (4): min and max, changed,
TN-RX*-A014A/E
Note, added
Table 5.20 Timing of On-Chip Peripheral Modules (5): min and max, changed,
TN-RX*-A014A/E
Note, added
Figure 5.32 RSPI Clock Timing and Simple SPI Clock Timing, changed
Figure 5.33 RSPI Timing (Master, CPHA = 0) and Simple SPI Timing (Master,
CKPH = 1), changed
Figure 5.34 RSPI Timing (Master, CPHA = 1) and Simple SPI Timing (Master,
CKPH = 0), changed
Figure 5.35 RSPI Timing (Slave, CPHA = 0) and Simple SPI Timing (Slave,
CKPH = 1), changed
Figure 5.36 RSPI Timing (Slave, CPHA = 1) and Simple SPI Timing (Slave,
CKPH = 0), changed
Figure 5.37 RIIC Bus Interface Input/Output Timing and Simple IIC Bus Interface
Input/Output Timing, changed
Table 5.21 On-Chip USB Full-Speed Characteristics (DP and DM Pin
Characteristics): Item, changed
Table 5.22 10-Bit A/D Conversion Characteristics: Note, changed
Table 5.23 12-Bit A/D Conversion Characteristics: Note, changed
Figure 5.44 Oscillation Stop Detection Timing, changed
Figure 5.45 Battery Backup Function Characteristics, changed
Table 5.30 ROM (Flash Memory for Code Storage) Characteristics (1), added
Table 5.31 ROM (Flash Memory for Code Storage) Characteristics (2): Table and
title, changed
Table 5.32 E2 Flash Characteristics (1), added
Table 5.33 E2 Flash Characteristics (2): Table and title, changed
All trademarks and registered trademarks are the property of their respective owners.
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 154 of 154
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the
products covered by this document, refer to the relevant sections of the document as well as any technical updates that
have been issued for the products.
1. Handling of Unused Pins
Handle unused pins in accordance with the directions given under Handling of Unused Pins in the
manual.
⎯ The input pins of CMOS products are generally in the high-impedance state. In operation with an
unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an
associated shoot-through current flows internally, and malfunctions occur due to the false
recognition of the pin state as an input signal become possible. Unused pins should be handled as
described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
⎯ The states of internal circuits in the LSI are indeterminate and the states of register settings and
pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states of pins
are not guaranteed from the moment when power is supplied until the reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function
are not guaranteed from the moment when power is supplied until the power reaches the level at
which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
⎯ The reserved addresses are provided for the possible future expansion of functions. Do not access
these addresses; the correct operation of LSI is not guaranteed if they are accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become stable.
When switching the clock signal during program execution, wait until the target clock signal has
stabilized.
⎯ When the clock signal is generated with an external resonator (or from an external oscillator)
during a reset, ensure that the reset line is only released after full stabilization of the clock signal.
Moreover, when switching to a clock signal produced with an external resonator (or by an external
oscillator) while program execution is in progress, wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to a product with a different part number, confirm
that the change will not lead to problems.
⎯ The characteristics of an MPU or MCU in the same group but having a different part number may
differ in terms of the internal memory capacity, layout pattern, and other factors, which can affect
the ranges of electrical characteristics, such as characteristic values, operating margins, immunity
to noise, and amount of radiated noise. When changing to a product with a different part number,
implement a system-evaluation test for the given product.
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
2.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
3.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
4.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or
5.
Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on
third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.
the product's quality grade, as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; and industrial robots etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical
implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it
in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses
incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
6.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or systems manufactured by you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
9.
Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or
regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the
development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the
contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics
products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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