Features
RX63N Group, RX631 Group
Renesas MCUs
R01DS0098EJ0180
Rev.1.80
May 13, 2014
100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS, up to 2-MB flash
memory, various communications interfaces including Ethernet MAC,
full-speed USB 2.0 host/function/OTG interface, CAN, 10- & 12-bit A/D
converters, RTC
Features
RX63N Group products incorporate an Ethernet controller while
RX631 Group products do not.
PLQP0176KB-A
PLQP0144KA-A
PLQP0100KB-A
PLQP0064KB-A
PLQP0048KB-A
■ 32-bit RX CPU core
Max. operating frequency: 100 MHz
Capable of 165 DMIPS in operation at 100 MHz
Single precision 32-bit IEEE-754 floating point
Two types of multiply-and-accumulation unit (between memories and
between registers)
32-bit multiplier (fastest instruction execution takes one CPU clock cycle)
Divider (fastest instruction execution takes two CPU clock cycles)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions: Ultra-compact code
Supports the memory protection unit (MPU)
JTAG and FINE (two-line) debugging interfaces
■ Low-power design and architecture
Operation from a single 2.7- to 3.6-V supply
Low power consumption: A product that supports all peripheral functions
draws only 500 μA/MHz.
RTC is capable of operation from a dedicated power supply (min. operating
voltage: 2.3 V).
Four low-power modes
■ On-chip main flash memory, no wait states
Supports ROM-less versions and versions with up to 2 Mbytes of ROM
(ROMless/256 Kbytes/384 Kbytes/512 Kbytes: RX631 Group only)
100-MHz operation, 10-ns read cycle (no wait states)
768-Kbyte to 2-Mbyte capacities
User code is programmable by on-board or off-board programming
■ On-chip data flash memory
ROM-less or 32 Kbytes of ROM (reprogrammable up to 100,000 times)
Programming/erasing as background operations (BGOs)
■ On-chip SRAM, no wait states
64 Kbytes/128 Kbytes/192 Kbytes/256 Kbytes of SRAM
For instructions and operands
Can provide backup on deep software standby
■ DMA
DMAC: Four channels
DTC
EXDMAC: Two channels
Dedicated DMAC for the Ethernet controller: Single channel
■ Reset and supply management
Power-on reset (POR)
Low voltage detection (LVD) with voltage settings
■ Clock functions
External crystal oscillator or internal PLL for operation at 4 to 16 MHz
Internal 125-kHz LOCO and 50-MHz HOCO
125-kHz clocks for the IWDT
■ Real-time clock
Adjustment functions (30 seconds, leap year, and error)
Time capture function
(for capturing times in response to event-signal input on external pins)
■ Independent watchdog timer
125-kHz LOCO clock operation
■ Useful functions for IEC60730 compliance
Oscillation-stoppage detection, frequency measurement, CRC, IWDT, selfdiagnostic function for the A/D converter, etc.
24 × 24 mm, 0.5-mm pitch
20 × 20 mm, 0.5-mm pitch
14 × 14 mm, 0.5-mm pitch
10 × 10 mm, 0.5-mm pitch
7 × 7 mm, 0.5-mm pitch
PTLG0177KA-A 8 × 8 mm, 0.5-mm pitch
PTLG0145KA-A 7 × 7 mm, 0.5-mm pitch
PTLG0100JA-A 7 × 7 mm, 0.65-mm pitch
PTLG0064JA-A 6 × 6 mm, 0.65-mm pitch
PLBG0176GA-A 13 × 13mm, 0.8-mm pitch
■ Various communications interfaces
Ethernet MAC (1) (not in RX631 Group products)
Host/function or OTG controller (1) and function controller (1) with fullspeed USB 2.0 transfer
CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up to 3
modules)
SCI with multiple functionalities (up to 13)
Choose from among asynchronous mode, clock-synchronous mode, smartcard interface mode, simplified SPI, simplified I2C, and extended serial
mode.
I2C bus interface for transfer at up to 1 Mbps (up to 4)
RSPI for high-speed transfer (up to 3)
Parallel data capture unit (PDC) (1) (available for 512 Kbytes/384 Kbytes/
256 Kbytes flash memory with 177-pin, 176-pin, 145-pin, and 144-pin)
■ External address space
Buses for high-speed data transfer (max. operating frequency of 50 MHz)
8 CS areas (8 × 16 Mbytes)
Multiplexed bus or separate bus are selectable per area.
8-, 16-, or 32-bit bus space is selectable per area
Independent SDRAM area (128 Mbytes)
■ Up to 20 extended-function timers
16-bit MTU2: input capture, output compare, PWM waveform output,
phase-counting mode (6 channels)
16-bit TPU: input capture, output compare, phase-counting mode (12
channels)
8-bit TMR (4 channels)
16-bit compare-match timers (4 channels)
■ A/D converter for 1-MHz Operation
Up to 21 × 12-bit channels, and incorporating 1 sample-and-hold circuit
Up to 8 × 10-bit channels, and incorporating 1 sample-and-hold circuit
Addition of results of A/D conversion (in the 12-bit converter)
Self diagnosis (for the 10-bit converter)
■ 10-bit D/A converter: 2 channels
■ Temperature sensor for measuring temperature within
the chip
■DEU
AES encryption and decryption functions
128/192/256-bit key length
ECB/CBC mode
■ Register write protection can protect values in
important registers against overwriting.
■ Up to 134 pins for general I/O ports
5-V tolerance, open drain, input pull-up, switchable driving ability
■ Unique ID
16-byte ID code is provided for each chip (only for the G version)
■ Operating temp. range
D version: -40 to +85°C
G version: -40 to +105°C
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 1 of 208
RX63N Group, RX631 Group
1. Overview
1.
Overview
1.1
Outline of Specifications
Table 1.1 lists the specifications in outline, and table 1.2 gives a comparison of the functions of products in different
packages.
Table 1.1 is for products with the greatest number of functions, so numbers of peripheral modules and channels will
differ in accord with the package. For details, see Table 1.2, Comparison of Functions for Different Packages in the
RX63N/RX631 Group.
Table 1.1
Outline of Specifications (1/6)
Classification
Module/Function
Description
CPU
CPU
Memory
Maximum operating frequency: 100 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per state (cycle of the system clock)
Address space: 4-Gbyte linear
Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Nine 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
Floating-point instructions: 8
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32 x 32 64 bits
On-chip divider: 32 / 32 32 bits
Barrel shifter: 32 bits
Memory protection unit (MPU)
FPU
Single precision (32-bit) floating point
Data types and floating-point exceptions in conformance with the IEEE754 standard
ROM
Capacity: ROMless, 256 Kbytes, 384 Kbytes, 512 Kbytes, 768 Kbytes, 1 Mbyte, 1.5
Mbytes, 2 Mbytes
100 MHz, no-wait access
On-board programming: Four types
Off-board programming (parallel programmer mode) (for products with 100 pins or more)
RAM
Capacity: 64 Kbytes, 128 Kbytes, 192 Kbytes, 256 Kbytes
100 MHz, no-wait access
E2 data flash
Capacity: 32 Kbytes
Programming/erasing: 100,000 times
MCU operating modes
Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled
expansion mode (software switching)
Clock
Main clock oscillator, subclock oscillator, low-speed/high-speed on-chip oscillator, PLL
frequency synthesizer, and IWDT-dedicated on-chip oscillator
Main-clock oscillation stoppage detection
Separate frequency-division and multiplication settings for the system clock (ICLK),
peripheral module clock (PCLK), FlashIF clock (FCLK) and external bus clock (BCLK)
The CPU and other bus masters run in synchronization with the system clock (ICLK):
Up to 100 MHz
Peripheral modules run in synchronization with the peripheral module clock (PCLK):
Up to 50 MHz
Flash IF run in synchronization with the flashIF clock (FCLK): Up to 50 MHz
Devices connected to the external bus run in synchronization with the external bus clock
(BCLK): Up to 50 MHz
Clock generation
circuit
Reset
RES# pin reset, power-on reset, voltage-monitoring reset, independent watchdog timer
reset, watchdog timer reset, deep software standby reset, and software reset
Voltage detection circuit
When the voltage on VCC passes the voltage detection level (Vdet), an internal reset or
internal interrupt is generated.
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 2 of 208
RX63N Group, RX631 Group
Table 1.1
1. Overview
Outline of Specifications (2/6)
Classification
Module/Function
Description
Low power
consumption
Low power
consumption facilities
Module stop function
Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software
standby mode
Battery backup function
Interrupt
Interrupt controller
(ICUb)
Peripheral function interrupts: 187 sources
External interrupts: 16 (pins IRQ0 to IRQ15)
Software interrupts: One source
Non-maskable interrupts: 6 sources
Sixteen levels specifiable for the order of priority
External bus extension
The external address space can be divided into nine areas (CS0 to CS7, SDCS), each
with independent control of access settings.
Capacity of each area: 16 Mbytes (CS0 to CS7), 128 Mbytes (SDCS)
A chip-select signal (CS0# to CS7#, SDCS#) can be output for each area.
Each area is specifiable as an 8-, 16-, or 32-bit bus space.
The data arrangement in each area is selectable as little or big endian (only for data).
SDRAM interface connectable
Bus format: Separate bus, multiplex bus
Wait control
Write buffer facility
DMA
DMA controller
(DMAC)
4 channels
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software trigger, external interrupts, and interrupt requests from
peripheral functions
EXDMA controller
(EXDMACa)
Data transfer
controller (DTCa)
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: External interrupts and interrupt requests from peripheral functions
R01DS0098EJ0180 Rev.1.80
May 13, 2014
2 channels
Four transfer modes: Normal transfer, repeat transfer, block transfer, and cluster transfer
Single-address transfer enabled with the EDAKn signal
Capable of direct data transfer to TFT LCD panels
Activation sources: Software trigger, external DMA requests (EDREQn), and interrupt
requests from peripheral functions
Page 3 of 208
RX63N Group, RX631 Group
Table 1.1
1. Overview
Outline of Specifications (3/6)
Classification
Module/Function
Description
I/O ports
General I/O ports
I/O ports for the 177-pin TFLGA, 176-pin LFBGA and 176-pin LQFP
I/O pins: 133
Input pins: 1
Pull-up resistors: 133
Open-drain outputs: 133
5-V tolerance: 18
I/O ports for the 145-pin TFLGA and 144-pin LQFP
I/O pins: 111
Input pins: 1
Pull-up resistors: 111
Open-drain outputs: 111
5-V tolerance: 18
I/O ports for the 100-pin TFLGA (in the planning stage) and 100-pin LQFP
I/O pins: 78
Input pins: 1
Pull-up resistors: 78
Open-drain outputs: 78
5-V tolerance: 17
I/O ports for the 64-pin TFLGA
I/O pins: 39
Input pin: 1
Pull-up resistors: 39
Open-drain outputs: 39
5-V tolerance: 8
I/O ports for the 64-pin LQFP
I/O pins: 42
Input pin: 1
Pull-up resistors: 42
Open-drain outputs: 42
5-V tolerance: 8
8-bit port switching function
I/O ports for the 48-pin LQFP
I/O pins: 30
Input pin: 1
Pull-up resistors: 30
Open-drain outputs: 30
5-V tolerance: 6
8-bit port switching function
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 4 of 208
RX63N Group, RX631 Group
Table 1.1
1. Overview
Outline of Specifications (4/6)
Classification
Module/Function
Description
Timers
16-bit timer pulse unit
(TPUa)
(16 bits x 6 channels) x 2 unit
Maximum of 16 pulse-input/output possible
Select from among seven or eight counter-input clock signals for each channel
Input capture/output compare function
Output of PWM waveforms in up to 15 phases in PWM mode
Buffered operation and phase-counting mode (two phase encoder input) depending on
the channel
Support for cascade-connected operation (32 bits x 2 channels)
PPG output trigger can be generated
Capable of generating conversion start triggers for the A/D converters
Signals from the input capture pins are input via a digital filter
Clock frequency measuring method
Multi-function timer
pulse unit 2 (MTU2a)
(16 bits x 6 channels) x 1 unit
Time bases for the 6 × 16-bit timer channels can be provided via up to sixteen pulse-input/
output lines and three pulse-input lines
Select from among eight counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than channel 5, for
which only four signals are available.
Input capture function
21 output compare/input capture registers
Complementary PWM output mode
Reset synchronous PWM mode
Phase-counting mode
Generation of triggers for A/D converter conversion
Digital filter
Signals from the input capture pins are input via a digital filter
PPG output trigger can be generated
Clock frequency measuring function
Frequency measuring
method (MCK)
The MTU or unit 0 TPU module can be used to monitor the main clock, subclock,
HOCO clock, LOCO clock, and PLL clock for abnormal frequencies.
Port output enable 2
(POE2a)
Controls the high-impedance state of the MTU’s waveform output pins
Programmable pulse
generator (PPG)
(4 bits x 4 groups) x 2 units
Pulse output with the MTU2 or TPU output as a trigger
Maximum of 32 pulse-output possible
8-bit timers (TMR)
(8 bits x 2 channels) x 2 units
Select from among seven internal clock signals (PCLK/1, PCLK/2, PCLK/8, PCLK/32,
PCLK/64, PCLK/1024, PCLK/8192) and one external clock signal
Capable of output of pulse trains with desired duty cycles or of PWM signals
The 2 channels of each unit can be cascaded to create a 16-bit timer
Generation of triggers for A/D converter conversion
Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12
Compare match timer
(CMT)
(16 bits x 2 channels) x 2 units
Select from among four internal clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
Realtime clock
(RTCa)
Clock sources: Main clock, subclock
Clock and calendar functions
Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
Battery backup operation
Time-capture facility for three values
Watchdog timer
(WDTA)
14 bits x 1 channel
Select from among 6 counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/
512, PCLK/2048, PCLK/8192)
Independent
watchdog timer
(IWDTa)
14 bits x 1 channel
Counter-input clock: IWDT-dedicated on-chip oscillator
Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64, dedicated
clock/128, dedicated clock/256
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 5 of 208
RX63N Group, RX631 Group
Table 1.1
1. Overview
Outline of Specifications (5/6)
Classification
Module/Function
Description
Communication
function
Ethernet controller
(ETHERC)
Input and output of Ethernet/IEEE 802.3 frames
Transfer at 10 or 100 Mbps
Full- and half-duplex modes
MII (Media Independent Interface) or RMII (Reduced Media Independent Interface) as
defined in IEEE 802.3u
Detection of Magic PacketsTM*1 or output of a "wake-on-LAN" signal (WOL)
Compliance with flow control as defined in IEEE 802.3x standards
Note 1. Magic PacketTM is a registered trademark of Advanced Micro Devices, Inc.
DMA controller for
Ethernet controller
(EDMAC)
Alleviation of CPU loads by the descriptor control method
Transmission FIFO: 2 Kbytes; Reception FIFO: 2 Kbytes
USB 2.0 host/function
module (USBa)
Serial
communications
interfaces (SCIc,
SCId)
13 channels (SCIc: 12 channels + SCId: 1 channel)
SCIc
Serial communications modes: Asynchronous, clock synchronous, and smart-card
interface
Multi-processor function
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12
Simple I2C
Simple SPI
SCId (The following functions are added to SCIc)
Supports the serial communications protocol, which contains the start frame and
information frame
Supports the LIN format
I2C bus interfaces
(RIIC)
4 channels (one of them is FM+)
Communication formats
I2C bus format/SMBus format
Supports the multi-master
Max. transfer rate: 1 Mbps (channel 0)
IEBus (IEB)
1 channel
Supports protocol control for the IEBus
Half-duplex asynchronous transfer
Multi-master operation
Broadcast communications function
Two selectable modes, differentiated by transfer rate
CAN module (CAN)
3 channels
Compliance with the ISO11898-1 specification (standard frame and extended frame)
32 mailboxes each
Serial peripheral
interfaces (SPI)
3 channels
RSPI transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),
and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four lines)
or clock-synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Switching between MSB first and LSB first
The number of bits in each transfer can be changed to any number of bits from 8 to 16, or
to 20, 24, or 32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with each
frame having up to 32 bits)
Buffered structure
Double buffers for both transmission and reception
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Includes a UDC (USB Device Controller) and transceiver for USB 2.0
Host/function module: one port, function module: one port
Compliance with the USB 2.0 specification
Transfer rate: Full speed (12 Mbps)
Self-power mode and bus-power mode are selectable
OTG (On the Go) operation is possible
Incorporates 2 Kbytes of RAM as a transfer buffer
Page 6 of 208
RX63N Group, RX631 Group
Table 1.1
1. Overview
Outline of Specifications (6/6)
Classification
Module/Function
Description
Communication
function
Parallel data capture
unit (PDC)
1 channel
Communicates with an image sensor or other external I/Os and transfer parallel data such
as an image output from those devices to internal RAM or external address spaces (CS
space and SDRAM space) through DTC or DMAC.
12-bit A/D converter (S12ADa)
1 unit (1 unit x 21 channels)
12-bit resolution
Conversion time: 1.0 s per channel (in operation with PCLK at 50 MHz)
Operating mode
Scan mode (single scan mode or continuous scan mode)
Sample-and-hold function
Reference voltage generation
Three ways to start A/D conversion
Conversion can be started by software, a conversion start trigger from a timer (MTU, TPU,
or TMR), or an external trigger signal.
A/D conversion of the temperature sensor output
10-bit A/D converter (ADb)
D/A converter (DAa)
2 channels
10-bit resolution
Output voltage: 0 V to VREFH
Temperature sensor
1 channel
Precision: ±1ºC
The voltage of the temperature is converted into a digital value by the 12-bit A/D
converter.
CRC calculator (CRC)
CRC code generation for arbitrary amounts of data in 8-bit units
Select any of three generating polynomials:
X8 + X2 + X + 1, X16 + X15 + X2 + 1, or X16 + X12 + X5 + 1.
Generation of CRC codes for use with LSB-first or MSB-first communications is selectable
Unique ID
A 16-byte device-specific ID (only for the G version)
Data encryption unit
(DEU)*1
1 unit (1 unit x 8 channels)
10-bit resolution
Conversion time: 1.0 s per channel (in operation with PCLK at 50 MHz)
Operating mode
Scan mode (single scan mode or continuous scan mode)
External amplifier connection mode
Sample-and-hold function
Three ways to start A/D conversion
Conversion can be started by software, a conversion start trigger from a timer (MTU, TPU,
or TMR), or an external trigger signal.
AES encryption and decryption functions
128/192/256-bit key length
ECB/CBC mode
Operating frequency
Up to 100 MHz
Power supply voltage
VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VBATT = 2.0 V to 3.6 V (for products with 100 or more pins),
VBATT = 2.3 V to 3.6 V (for the 64-pin product)
Operating temperature
D version: -40 to +85°C,
G version: -40 to +105°C*2
Package
177-pin TFLGA (PTLG0177KA-A)
176-pin LFBGA (PLBG0176GA-A)
176-pin LQFP (PLQP0176KB-A)
145-pin TFLGA (PTLG0145KA-A)
144-pin LQFP (PLQP0144KA-A)
100-pin TFLGA (PTLG0100JA-A) (in the planning stage)
100-pin LQFP (PLQP0100KB-A)
64-pin TFLGA (PTLG0064JA-A)
64-pin LQFP (PLQP0064KB-A)
48-pin LQFP (PLQP0048KB-A)
On-chip debugging system
E1 emulator (JTAG and FINE interfaces)
E20 emulator (JTAG interface)
Note 1. Please contact our sales office for more information.
Note 2. Please contact us if you are using a G version.
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 7 of 208
RX63N Group, RX631 Group
Table 1.2
1. Overview
Comparison of Functions for Different Packages in the RX63N/RX631 Group
Functions
RX63N Group
177-pin
176-pin
Package
External bus
width
External bus width
DMA
DMA controller
SDRAM area controller
32 bits
145-pin
144-pin
32 bits
Not
available
100-pin
Ch. 0 to 3
Ch. 0 and 1
Not available
Available
Ch. 0 to 5
Ch. 0 to 11
Ch. 0 to 5
Ch. 0 to 5
Ch. 0 to 5
Port output enable 2
Available
Available
Ch. 0 and 1
Ch. 0 and 1
8-bit timers
Ch. 0 to 3
Ch. 0 to 3
Compare match timer
Ch. 0 to 3
Ch. 0 to 3
Realtime clock
Available
Watchdog timer
Available
Available
Not
available
Available
Independent watchdog timer
Available
Available
Ethernet controller
Available
Not available
DMA controller for Ethernet
controller
Available
Not available
Serial communications
interfaces (SClc)
Serial communications
interfaces (SCld)
I2C bus interfaces
IEBus
Serial peripheral interfaces
CAN module
Parallel data capture unit (PDC)
12-bit A/D converter (channel)
10-bit A/D converter (channel)
D/A converter
Ch. 0 and
1
Ch.0
Ch. 0 to 11
Ch. 0 and
1
Ch. 0 to
3, 5, 6, 8
and 9
Ch.0
Ch. 0 to 11
For 1.5 M or more:
Ch. 0 to 2, For 1 M or
less: Ch. 0 and 1
Ch.0 and
2
Ch. 0 and
1
Ch. 0 to 3
Ch.0 and
2
Ch.2
Ch.0 to 2
Ch. 0 and For 1.5 M or more:
1
Ch. 0 to 2, For 1 M or
less: Ch. 0 and 1
Ch. 0 and 1
Ch. 0
and 1
Ch.1
Available
AN000 to
013
AN0 to 7
Ch. 0 and 1
Ch. 1, 5, 6, 8 and 9 Ch. 1, 5, 6,
and 8
Available
Not available
AN000 to 020
Ch.0
Ch. 12
Available
Ch.0 to 2
Ch. 0 and
1
Ch. 0 to
3, 5, 6, 8
and 9
Ch. 12
Ch. 0 to 3
48-pin
Not available
Multi-function timer pulse unit 2
USB 2.0 host/function module
64-pin
TFLGA
Not available
Available
Available
Ch. 0 to 11
64-pin
LQFP
16 bits
Ch. 0 and 1
Programmable pulse generator
Communicatio
n function
100-pin
177-pin
176-pin
Ch. 0 to 3
Data transfer controller
16-bit timer pulse unit
RX631 Group
16 bits
Available
EXDMA controller
Timers
145-pin
144-pin
AN000 to 020
Not available
AN000 to
013
AN000 to 004, 006,
008 to 013
AN0 to 7
Ch.1
Ch. 0 and 1
AN000 to
002, 006,
009 to 012
Not available
Ch.1
Ch.1
Not
available
Temperature sensor
Available
Available
CRC calculator
Available
Available
Unique ID
Available (only for the G version)
Off-board programming (parallel programmer
mode)
Available
Sub-clock oscillator (for low clock loads)
Available
Not available
Not available
Sub-clock oscillator (for standard clock loads)
Available
Not
available
Battery backup function
Available
Not
available
I/O port switching function
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Not available
Not available
Available
Page 8 of 208
RX63N Group, RX631 Group
1.2
1. Overview
List of Products
Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part no.
Table 1.3
List of Products (1/8)
Group
Part No.
Package
ROM
Capacity
RAM
Capacity
E2 Data
Flash
Operating
Frequency (Max.)
Operating
Temp. Range
RX63N
(D version)
R5F563NECDLC
PTLG0177KA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NEDDLC
PTLG0177KA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NDCDLC
PTLG0177KA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NDDDLC
PTLG0177KA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NBCDLC
PTLG0177KA-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NBDDLC
PTLG0177KA-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NACDLC
PTLG0177KA-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NADDLC
PTLG0177KA-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NECDBG
PLBG0176GA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NEDDBG
PLBG0176GA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NDCDBG
PLBG0176GA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NDDDBG
PLBG0176GA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NBCDBG
PLBG0176GA-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NBDDBG
PLBG0176GA-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NACDBG
PLBG0176GA-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NADDBG
PLBG0176GA-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NFHDFC
PLQP0176KB-A
2 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NFDDFC
PLQP0176KB-A
2 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NKHDFC
PLQP0176KB-A*1
2 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NKDDFC
PLQP0176KB-A
2 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NECDFC
PLQP0176KB-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NEDDFC
PLQP0176KB-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NJHDFC
PLQP0176KB-A*1
1.5 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NJDDFC
PLQP0176KB-A*1
1.5 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NGHDFC
PLQP0176KB-A*1
1.5 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NGDDFC
PLQP0176KB-A*1
1.5 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NDCDFC
PLQP0176KB-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NDDDFC
PLQP0176KB-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NYHDFC
PLQP0176KB-A
1 Mbyte
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NYDDFC
PLQP0176KB-A
1 Mbyte
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NWHDFC
PLQP0176KB-A
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NWDDFC
PLQP0176KB-A
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NWGDFC
PLQP0176KB-A
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NWCDFC
PLQP0176KB-A
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NBCDFC
PLQP0176KB-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NBDDFC
PLQP0176KB-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NACDFC
PLQP0176KB-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NADDFC
PLQP0176KB-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NECDLK
PTLG0145KA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NEDDLK
PTLG0145KA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NDCDLK
PTLG0145KA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 9 of 208
RX63N Group, RX631 Group
Table 1.3
1. Overview
List of Products (2/8)
Group
Part No.
Package
ROM
Capacity
RAM
Capacity
E2 Data
Flash
Operating
Frequency (Max.)
Operating
Temp. Range
RX63N
(D version)
R5F563NDDDLK
PTLG0145KA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NBCDLK
PTLG0145KA-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NBDDLK
PTLG0145KA-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NACDLK
PTLG0145KA-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NADDLK
PTLG0145KA-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NFHDFB
PLQP0144KA-A
2 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NFDDFB
PLQP0144KA-A
2 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NKHDFB
PLQP0144KA-A*1
2 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NKDDFB
PLQP0144KA-A
2 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NECDFB
PLQP0144KA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NEDDFB
PLQP0144KA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NJHDFB
PLQP0144KA-A*1
1.5 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NJDDFB
PLQP0144KA-A*1
1.5 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NGHDFB
PLQP0144KA-A*1
1.5 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NGDDFB
PLQP0144KA-A*1
1.5 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NDCDFB
PLQP0144KA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NDDDFB
PLQP0144KA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NYHDFB
PLQP0144KA-A
1 Mbyte
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NYDDFB
PLQP0144KA-A
1 Mbyte
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NWHDFB
PLQP0144KA-A
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NWDDFB
PLQP0144KA-A
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NBCDFB
PLQP0144KA-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NBDDFB
PLQP0144KA-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NACDFB
PLQP0144KA-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NADDFB
PLQP0144KA-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NECDLJ
PTLG0100JA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NEDDLJ
PTLG0100JA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NDCDLJ
PTLG0100JA-A*1
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NDDDLJ
PTLG0100JA-A*1
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NBCDLJ
PTLG0100JA-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NBDDLJ
PTLG0100JA-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NACDLJ
PTLG0100JA-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NADDLJ
PTLG0100JA-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NFHDFP
PLQP0100KB-A
2 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NFDDFP
PLQP0100KB-A
2 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NKHDFP
PLQP0100KB-A*1
2 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NKDDFP
PLQP0100KB-A
2 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NECDFP
PLQP0100KB-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NEDDFP
PLQP0100KB-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NJHDFP
PLQP0100KB-A*1
1.5 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NJDDFP
PLQP0100KB-A*1
1.5 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NGHDFP
PLQP0100KB-A*1
1.5 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NGDDFP
PLQP0100KB-A*1
1.5 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NDCDFP
PLQP0100KB-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NDDDFP
PLQP0100KB-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 10 of 208
RX63N Group, RX631 Group
Table 1.3
1. Overview
List of Products (3/8)
Group
Part No.
Package
ROM
Capacity
RAM
Capacity
E2 Data
Flash
Operating
Frequency (Max.)
Operating
Temp. Range
RX63N
(D version)
R5F563NYHDFP
PLQP0100KB-A
1 Mbyte
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NYDDFP
PLQP0100KB-A
1 Mbyte
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NWHDFP
PLQP0100KB-A
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NWDDFP
PLQP0100KB-A
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NWGDFP
PLQP0100KB-A*1
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NWCDFP
PLQP0100KB-A*1
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NBCDFP
PLQP0100KB-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NBDDFP
PLQP0100KB-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NACDFP
PLQP0100KB-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NADDFP
PLQP0100KB-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F563NFHGFC
PLQP0176KB-A
2 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
RX63N
(G version)
*2
RX631
(D version)
R5F563NFDGFC
PLQP0176KB-A
2 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NKDGFC
PLQP0176KB-A
2 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NEDGFC
PLQP0176KB-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NDDGFC
PLQP0176KB-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NYHGFC
PLQP0176KB-A
1 Mbyte
256 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NYDGFC
PLQP0176KB-A
1 Mbyte
256 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NWHGFC
PLQP0176KB-A
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NWDGFC
PLQP0176KB-A
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NBDGFC
PLQP0176KB-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NADGFC
PLQP0176KB-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NFHGFB
PLQP0144KA-A
2 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NFDGFB
PLQP0144KA-A
2 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NKDGFB
PLQP0144KA-A
2 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NEDGFB
PLQP0144KA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NDDGFB
PLQP0144KA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NYHGFB
PLQP0144KA-A
1 Mbyte
256 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NYDGFB
PLQP0144KA-A
1 Mbyte
256 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NWHGFB
PLQP0144KA-A
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NWDGFB
PLQP0144KA-A
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NBDGFB
PLQP0144KA-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NADGFB
PLQP0144KA-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NFHGFP
PLQP0100KB-A
2 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NFDGFP
PLQP0100KB-A
2 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NKDGFP
PLQP0100KB-A
2 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NEDGFP
PLQP0100KB-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NDDGFP
PLQP0100KB-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NYHGFP
PLQP0100KB-A
1 Mbyte
256 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NYDGFP
PLQP0100KB-A
1 Mbyte
256 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NWHGFP
PLQP0100KB-A
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NWDGFP
PLQP0100KB-A
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NBDGFP
PLQP0100KB-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F563NADGFP
PLQP0100KB-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631ECDLC
PTLG0177KA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631EDDLC
PTLG0177KA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 11 of 208
RX63N Group, RX631 Group
Table 1.3
1. Overview
List of Products (4/8)
Group
Part No.
Package
ROM
Capacity
RAM
Capacity
E2 Data
Flash
Operating
Frequency (Max.)
Operating
Temp. Range
RX631
(D version)
R5F5631DCDLC
PTLG0177KA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631DDDLC
PTLG0177KA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631BDDLC
PTLG0177KA-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631BCDLC
PTLG0177KA-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631ACDLC
PTLG0177KA-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631ADDLC
PTLG0177KA-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56318CDLC
PTLG0177KA-A
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56318DDLC
PTLG0177KA-A
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56317CDLC
PTLG0177KA-A
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56317DDLC
PTLG0177KA-A
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56316CDLC
PTLG0177KA-A
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56316DDLC
PTLG0177KA-A
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631ECDBG
PLBG0176GA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631EDDBG
PLBG0176GA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631DCDBG
PLBG0176GA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631DDDBG
PLBG0176GA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631BCDBG
PLBG0176GA-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631BDDBG
PLBG0176GA-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631ACDBG
PLBG0176GA-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631ADDBG
PLBG0176GA-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56318CDBG
PLBG0176GA-A
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56318DDBG
PLBG0176GA-A
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56317CDBG
PLBG0176GA-A
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56317DDBG
PLBG0176GA-A
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56316CDBG
PLBG0176GA-A
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56316DDBG
PLBG0176GA-A
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631FHDFC
PLQP0176KB-A
2 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631FDDFC
PLQP0176KB-A
2 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631KHDFC
PLQP0176KB-A*1
2 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631KDDFC
PLQP0176KB-A
2 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631ECDFC
PLQP0176KB-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631EDDFC
PLQP0176KB-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631JHDFC
PLQP0176KB-A*1
1.5 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631JDDFC
PLQP0176KB-A*1
1.5 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631GHDFC
PLQP0176KB-A*1
1.5 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631GDDFC
PLQP0176KB-A*1
1.5 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631DCDFC
PLQP0176KB-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631DDDFC
PLQP0176KB-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631YHDFC
PLQP0176KB-A
1 Mbyte
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631YDDFC
PLQP0176KB-A
1 Mbyte
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631WHDFC
PLQP0176KB-A
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631WDDFC
PLQP0176KB-A
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631BCDFC
PLQP0176KB-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631BDDFC
PLQP0176KB-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631ACDFC
PLQP0176KB-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 12 of 208
RX63N Group, RX631 Group
Table 1.3
1. Overview
List of Products (5/8)
Group
Part No.
Package
ROM
Capacity
RAM
Capacity
E2 Data
Flash
Operating
Frequency (Max.)
Operating
Temp. Range
RX631
(D version)
R5F5631ADDFC
PLQP0176KB-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56318CDFC
PLQP0176KB-A
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56318DDFC
PLQP0176KB-A
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56317CDFC
PLQP0176KB-A
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56317DDFC
PLQP0176KB-A
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56316CDFC
PLQP0176KB-A
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56316DDFC
PLQP0176KB-A
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631ECDLK
PTLG0145KA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631EDDLK
PTLG0145KA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631DCDLK
PTLG0145KA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631DDDLK
PTLG0145KA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631BCDLK
PTLG0145KA-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631BDDLK
PTLG0145KA-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631ACDLK
PTLG0145KA-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631ADDLK
PTLG0145KA-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56318CDLK
PTLG0145KA-A
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56318DDLK
PTLG0145KA-A
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56317CDLK
PTLG0145KA-A
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56317DDLK
PTLG0145KA-A
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56316CDLK
PTLG0145KA-A
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56316DDLK
PTLG0145KA-A
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631FHDFB
PLQP0144KA-A
2 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631FDDFB
PLQP0144KA-A
2 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631KHDFB
PLQP0144KA-A*1
2 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631KDDFB
PLQP0144KA-A
2 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631ECDFB
PLQP0144KA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631EDDFB
PLQP0144KA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631JHDFB
PLQP0144KA-A*1
1.5 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631JDDFB
PLQP0144KA-A
1.5 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631GHDFB
PLQP0144KA-A*1
1.5 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631GDDFB
PLQP0144KA-A
1.5 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631DCDFB
PLQP0144KA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631DDDFB
PLQP0144KA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631YHDFB
PLQP0144KA-A
1 Mbyte
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631YDDFB
PLQP0144KA-A
1 Mbyte
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631WHDFB
PLQP0144KA-A
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631WDDFB
PLQP0144KA-A
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631BCDFB
PLQP0144KA-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631BDDFB
PLQP0144KA-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631ACDFB
PLQP0144KA-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631ADDFB
PLQP0144KA-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56318CDFB
PLQP0144KA-A
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56318DDFB
PLQP0144KA-A
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56316CDFB
PLQP0144KA-A
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56316DDFB
PLQP0144KA-A
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 13 of 208
RX63N Group, RX631 Group
Table 1.3
1. Overview
List of Products (6/8)
Group
Part No.
Package
ROM
Capacity
RAM
Capacity
E2 Data
Flash
Operating
Frequency (Max.)
Operating
Temp. Range
RX631
(D version)
R5F56317CDFB
PLQP0144KA-A
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56317DDFB
PLQP0144KA-A
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631ECDLJ
PTLG0100JA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631EDDLJ
PTLG0100JA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631DCDLJ
PTLG0100JA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631DDDLJ
PTLG0100JA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631BCDLJ
PTLG0100JA-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631BDDLJ
PTLG0100JA-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631ACDLJ
PTLG0100JA-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631ADDLJ
PTLG0100JA-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56318CDLJ
PTLG0100JA-A
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56318DDLJ
PTLG0100JA-A
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56317CDLJ
PTLG0100JA-A
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56317DDLJ
PTLG0100JA-A
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56316CDLJ
PTLG0100JA-A
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56316DDLJ
PTLG0100JA-A
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631FHDFP
PLQP0100KB-A
2 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631FDDFP
PLQP0100KB-A
2 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631KHDFP
PLQP0100KB-A*1
2 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631KDDFP
PLQP0100KB-A
2 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631ECDFP
PLQP0100KB-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631EDDFP
PLQP0100KB-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631JHDFP
PLQP0100KB-A*1
1.5 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631JDDFP
PLQP0100KB-A
1.5 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631GHDFP
PLQP0100KB-A*1
1.5 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631GDDFP
PLQP0100KB-A
1.5 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631DCDFP
PLQP0100KB-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631DDDFP
PLQP0100KB-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631YHDFP
PLQP0100KB-A
1 Mbyte
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631YDDFP
PLQP0100KB-A
1 Mbyte
256 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631WHDFP
PLQP0100KB-A
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631WDDFP
PLQP0100KB-A
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631BCDFP
PLQP0100KB-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631BDDFP
PLQP0100KB-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631ACDFP
PLQP0100KB-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631ADDFP
PLQP0100KB-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56318CDFP
PLQP0100KB-A
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56318DDFP
PLQP0100KB-A
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56317CDFP
PLQP0100KB-A
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56317DDFP
PLQP0100KB-A
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56316CDFP
PLQP0100KB-A
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56316DDFP
PLQP0100KB-A
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631PCDFM
PLQP0064KB-A
512 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631PDDFM
PLQP0064KB-A
512 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631NCDFM
PLQP0064KB-A
384 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 14 of 208
RX63N Group, RX631 Group
Table 1.3
1. Overview
List of Products (7/8)
Group
Part No.
Package
ROM
Capacity
RAM
Capacity
E2 Data
Flash
Operating
Frequency (Max.)
Operating
Temp. Range
RX631
(D version)
R5F5631NDDFM
PLQP0064KB-A
384 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631MCDFM
PLQP0064KB-A
256 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
RX631
(G version)
*2
R5F5631MDDFM
PLQP0064KB-A
256 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631PCDFL
PLQP0048KB-A
512 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631PDDFL
PLQP0048KB-A
512 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631NCDFL
PLQP0048KB-A
384 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631NDDFL
PLQP0048KB-A
384 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631MCDFL
PLQP0048KB-A
256 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631MDDFL
PLQP0048KB-A
256 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56318SDLC
PTLG0177KA-A
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56317SDLC
PTLG0177KA-A
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56316SDLC
PTLG0177KA-A
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56318SDBG
PLBG0176GA-A*1
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56317SDBG
PLBG0176GA-A*1
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56316SDBG
PLBG0176GA-A*1
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56318SDFC
PLQP0176KB-A*1
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56317SDFC
PLQP0176KB-A*1
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56316SDFC
PLQP0176KB-A*1
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56318SDLK
PTLG0145KA-A
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56317SDLK
PTLG0145KA-A
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56316SDLK
PTLG0145KA-A
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56318SDFB
PLQP144KA-A*1
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56317SDFB
PLQP144KA-A*1
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F56316SDFB
PLQP144KA-A*1
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631PFDLH
PTLG0064JA-A
512 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5F5631MFDLH
PTLG0064JA-A*1
256 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +85°C
R5S56310CDFC
PLQP0176KB-A
0 bytes
128 Kbytes
0 bytes
100 MHz
-40 to +85°C
R5F5631FDGFC
PLQP0176KB-A
2 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631KDGFC
PLQP0176KB-A
2 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631EDGFC
PLQP0176KB-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631DDGFC
PLQP0176KB-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631YDGFC
PLQP0176KB-A
1 Mbyte
256 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631WDGFC
PLQP0176KB-A
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631BDGFC
PLQP0176KB-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631ADGFC
PLQP0176KB-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F56318SGFC
PLQP0176KB-A
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F56318DGFC
PLQP0176KB-A
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F56317SGFC
PLQP0176KB-A
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F56317DGFC
PLQP0176KB-A
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F56316SGFC
PLQP0176KB-A
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F56316DGFC
PLQP0176KB-A
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631FDGFB
PLQP0144KA-A
2 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631KDGFB
PLQP0144KA-A
2 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631EDGFB
PLQP0144KA-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631JDGFB
PLQP0144KA-A
1.5 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 15 of 208
RX63N Group, RX631 Group
Table 1.3
1. Overview
List of Products (8/8)
Group
Part No.
Package
ROM
Capacity
RAM
Capacity
E2 Data
Flash
Operating
Frequency (Max.)
Operating
Temp. Range
RX631
(G version)
*2
R5F5631GDGFB
PLQP0144KA-A
1.5 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631DDGFB
PLQP0144KA-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631YDGFB
PLQP0144KA-A
1 Mbyte
256 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631WDGFB
PLQP0144KA-A
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631BDGFB
PLQP0144KA-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631ADGFB
PLQP0144KA-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F56318SGFB
PLQP0144KA-A
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F56318DGFB
PLQP0144KA-A
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F56317SGFB
PLQP0144KA-A
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F56317DGFB
PLQP0144KA-A
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F56316SGFB
PLQP0144KA-A
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F56316DGFB
PLQP0144KA-A
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631FDGFP
PLQP0100KB-A
2 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631KDGFP
PLQP0100KB-A
2 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631EDGFP
PLQP0100KB-A
2 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631JDGFP
PLQP0100KB-A
1.5 Mbytes
256 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631GDGFP
PLQP0100KB-A
1.5 Mbytes
192 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631DDGFP
PLQP0100KB-A
1.5 Mbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631YDGFP
PLQP0100KB-A
1 Mbyte
256 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631WDGFP
PLQP0100KB-A
1 Mbyte
192 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631BDGFP
PLQP0100KB-A
1 Mbyte
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631ADGFP
PLQP0100KB-A
768 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F56318DGFP
PLQP0100KB-A
512 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F56317DGFP
PLQP0100KB-A
384 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F56316DGFP
PLQP0100KB-A
256 Kbytes
128 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631PDGFM
PLQP0064KB-A
512 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631NDGFM
PLQP0064KB-A
384 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631MDGFM
PLQP0064KB-A
256 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631PDGFL
PLQP0048KB-A
512 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631NDGFL
PLQP0048KB-A
384 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
R5F5631MDGFL
PLQP0048KB-A
256 Kbytes
64 Kbytes
32 Kbytes
100 MHz
-40 to +105°C
Note 1. In the planning stage
Note 2. The specifications of the temperature sensor calibration and unique ID for G-version products differ from those for other
products. For details, see section 45.2.2, Temperature Sensor Calibration Data Registers (TSCDRH, TSCDRL), section 45.3,
Using the Temperature Sensor, and section 47.2.22, Unique ID Registers n (UIDRn) (n = 0 to 15) in the User’s manual:
Hardware.
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 16 of 208
RX63N Group, RX631 Group
R 5 F 5
6
3 N A C D
1. Overview
F
P
Package type, number of pins, and pin pitch
FC : LQFP/176/0.50
BG: LFBGA/176/0.80
LC : TFLGA/177/0.50
FB : LQFP/144/0.50
LK : TFLGA/145/0.50
LJ : TFLGA/100/0.65
FP : LQFP/100/0.50
LH: TFLGA/64/0.65
FM: LQFP/64/0.50
FL: LQFP/48/0.50
D: Operating temperature range: -40 to +85°C
G: Operating temperature range: -40 to +105°C
H : CAN included/DEU included/PDC not included
D : CAN included/DEU not included/PDC not included
G : CAN not included/DEU included/PDC not included
C : CAN not included/DEU not included/PDC not included
S : CAN included/DEU not included/PDC included
F (only 64-pin TFLGA) : CAN included/DEU not included/PDC not included
ROM, RAM and E2 data flash capacity
F : 2 Mbytes/256 Kbytes/32 Kbytes
K : 2 Mbytes/192 Kbytes/32 Kbytes
E : 2 Mbytes/128 Kbytes/32 Kbytes
J : 1.5 Mbytes/256 Kbytes/32 Kbytes
G : 1.5 Mbytes/192 Kbytes/32 Kbytes
D : 1.5 Mbytes/128 Kbytes/32 Kbytes
Y : 1 Mbyte/256 Kbytes/32 Kbytes
W: 1 Mbyte/192 Kbytes/32 Kbytes
B : 1 Mbyte/128 Kbytes/32 Kbytes
A : 768 Kbytes/128 Kbytes/32 Kbytes
8 : 512 Kbytes/128 Kbytes/32 Kbytes
7 : 384 Kbytes/128 Kbytes/32 Kbytes
6 : 256 Kbytes/128 Kbytes/32 Kbytes
P : 512 Kbytes/64 Kbytes/32 Kbytes
N : 384 Kbytes/64 Kbytes/32 Kbytes
M: 256 Kbytes/64 Kbytes/32 Kbytes
0 : 0 bytes/128 Kbytes/0 bytes
Group name
3N : RX63N Group
31 : RX631 Group
Series name
RX600 Series
Type of memory
F : Flash memory version
S : ROMless version
Renesas MCU
Renesas semiconductor product
Figure 1.1
How to Read the Product Part No.
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 17 of 208
RX63N Group, RX631 Group
1.3
1. Overview
Block Diagram
Figure 1.2 shows a block diagram.
DEU
E2 Data Flash
WDTA
IWDTa
CRC
SCIc × 12 ch
SCId × 1 ch
USB 2.0 host/function module
USB 2.0 function module
RSPI (unit 0)
PDC
ETHERC
Internal peripheral buses 1 to 6
RSPI (unit 1)
RSPI (unit 2)
CAN × 3 ch
POE2a
TPUa × 6 ch (unit 0)
Internal main bus 1
MPU
Clock
generati
on circuit
ETHERC
EDMAC
ICUb
DTCa
DMACA
EXDMACa
BSC
WDTA
IWDTa
CRC
SCIc, SCId
MPU
Figure 1.2
Internal main bus 2
Operand bus
RX CPU
Port 2
Port 3
TPUa × 6 ch (unit 1)
Port 4
PPG (unit 0)
PPG (unit 1)
Port 5
Port 6
TMR × 2 ch (unit 0)
ICUb
Instruction bus
RAM
Port 1
MTU2a × 6 ch
EDMAC
ROM
Port 0
TMR × 2 ch (unit 1)
Port 7
CMT × 2 ch (unit 0)
Port 8
CMT × 2 ch (unit 1)
Port 9
RTCa
DTCa
Port A
RIIC × 4ch
Port B
IEB
DMACA ×
4ch
12-bit ADC × 21 ch
Port C
10-bit ADC × 8 ch
Port D
10-bit DAC × 2 ch
Port E
Temperature sensor
Port F
Port G
EXDMACa
: Ethernet controller
: DMA controller for Ethernet controller
: Interrupt controller
: Data transfer controller
: DMA controller
: EXDMA controller
: Bus controller
: Watchdog timer
: Independent watchdog timer
: CRC (cyclic redundancy check) calculator
: Serial communications interface
: Memory protection unit
Port H
BSC
External bus
RSPI
CAN
MTU2a
POE2a
TPUa
PPG
TMR
CMT
RTCa
RIIC
IEB
DEU
PDC
Port J
: Serial peripheral interface
: CAN module
: Multi-function timer pulse unit 2
: Port output enable 2
: 16-bit timer pulse unit
: Programmable pulse generator
: 8-bit timer
: Compare match timer
: Realtime clock
: I2C bus interface
: IEBus controller
: Data encryption unit
: Parallel data capture unit
Block Diagram
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May 13, 2014
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RX63N Group, RX631 Group
1.4
1. Overview
Pin Functions
Table 1.4 lists the pin functions.
Table 1.4
Pin Functions (1/6)
Classifications
Pin Name
I/O
Description
Power supply
VCC
Input
Power supply pin. Connect it to the system power supply.
Connect this pin to VSS via a 0.1-µF capacitor. The capacitor
should be placed close to the pin.
VCL
Input
Connect this pin to VSS via a 0.1-F capacitor. The capacitor
should be placed close to the pin.
VSS
Input
Ground pin. Connect it to the system power supply (0 V).
VBATT
Input
Backup power pin. When the battery backup function is not to
be used, connect it to the VCC pin.
XTAL
Output
EXTAL
Input
Pins for a crystal resonator. An external clock signal can be
input through the EXTAL pin.
Clock
BCLK
Output
Outputs the external bus clock for external devices.
SDCLK
Output
Outputs the clock dedicated for the SDRAM.
XCOUT
Output
XCIN
Input
Input/output pins for the subclock oscillator. Connect a crystal
resonator between XCOUT and XCIN.
Operating mode control
MD
Input
Pins for setting the operating mode. The signal levels on these
pins must not be changed during operation.
System control
RES#
Input
Reset signal input pin. This LSI enters the reset state when this
signal goes low.
EMLE
Input
Input pin for the on-chip emulator enable signal. When the onchip emulator is used, this pin should be driven high. When not
used, it should be driven low.
BSCANP
Input
Boundary scan enable pin. Boundary scan is enabled when this
pin goes high. When not used, it should be driven low.
FINEC
Input
Fine interface clock pin
FINED
I/O
Fine interface pin
TRST#
Input
TMS
Input
On-chip emulator or boundary scan pins. When the EMLE pin is
driven high, these pins are dedicated for the on-chip emulator.
TDI
Input
TCK
Input
On-chip emulator
TDO
Output
TRCLK
Output
This pin outputs the clock for synchronization with the trace
data.
TRSYNC
Output
This pin indicates that output from the TRDATA0 to TRDATA3
pins is valid.
TRDATA0 to TRDATA3
Output
These pins output the trace information.
Address bus
A0 to A23
Output
Output pins for the address.
Data bus
D0 to D31
I/O
Input and output pins for the bidirectional data bus.
Multiplexed bus
A0/D0 to A15/D15
I/O
Address/data multiplexed bus
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Page 19 of 208
RX63N Group, RX631 Group
Table 1.4
1. Overview
Pin Functions (2/6)
Classifications
Pin Name
I/O
Description
Bus control
RD#
Output
Strobe signal which indicates that reading from the external bus
interface space is in progress.
WR#
Output
Strobe signal which indicates that writing to the external bus
interface space is in progress, in 1-write strobe mode.
WR0# to WR3#
Output
Strobe signals which indicate that either group of data bus pins
(D7 to D0, D15 to D8, D23 to D16, and D31 to D24) is valid in
writing to the external bus interface space, in byte strobe mode.
BC0# to BC3#
Output
Strobe signals which indicate that either group of data bus pins
(D7 to D0, D15 to D8, D23 to D16, and D31 to D24) is valid in
access to the external bus interface space, in 1-write strobe
mode.
ALE
Output
Address latch signal when address/data multiplexed bus is
selected.
EXDMA controller
Interrupt
Multi-function timer pulse
unit 2
Port output enable 2
CKE
Output
Output pin for SDRAM clock enable signals.
SDCS#
Output
Output pin for SDRAM chip select signals.
RAS#
Output
Output pin for SDRAM row address strobe signals.
CAS#
Output
Output pin for SDRAM column address strobe signals.
WE#
Output
Output pin for SDRAM write enable signals.
DQM0 to DQM3
Output
Output pins for SDRAM I/O data mask enable signals.
CS0# to CS7#
Output
Select signals for CS area.
WAIT#
Input
Input pins for wait request signals in access to the external
space.
EDREQ0, EDREQ1
Input pins for external DMA transfer requests.
EDACK0, EDACK1
Output pins for single address transfer acknowledge signals.
NMI
Input
Non-maskable interrupt request signal.
IRQ0 to IRQ15
Input
Maskable interrupt request signals.
MTIOC0A, MTIOC0B
MTIOC0C, MTIOC0D
I/O
The TGRA0 to TGRD0 input capture input/output compare
output/PWM output pins.
MTIOC1A, MTIOC1B
I/O
The TGRA1 and TGRB1 input capture input/output compare
output/PWM output pins.
MTIOC2A, MTIOC2B
I/O
The TGRA2 and TGRB2 input capture input/output compare
output/PWM output pins.
MTIOC3A, MTIOC3B
MTIOC3C, MTIOC3D
I/O
The TGRA3 to TGRD3 input capture input/output compare
output/PWM output pins.
MTIOC4A, MTIOC4B
MTIOC4C, MTIOC4D
I/O
The TGRA4 to TGRD4 input capture input/output compare
output/PWM output pins.
MTIC5U, MTIC5V
MTIC5W
Input
The TGRU5, TGRV5, and TGRW5 input capture input/dead
time compensation input pins.
MTCLKA, MTCLKB
MTCLKC, MTCLKD
Input
Input pins for external clock signals.
POE0# to POE3#
POE8#
Input
Input pins for request signals to place the MTU large-current
pins in the high impedance state.
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May 13, 2014
Page 20 of 208
RX63N Group, RX631 Group
Table 1.4
1. Overview
Pin Functions (3/6)
Classifications
Pin Name
I/O
Description
16-bit timer pulse unit
TIOCA0, TIOCB0
TIOCC0, TIOCD0
I/O
The TGRA0 to TGRD0 input capture input/output compare
output/PWM output pins.
TIOCA1, TIOCB1
I/O
The TGRA1 and TGRB1 input capture input/output compare
output/PWM output pins.
TIOCA2, TIOCB2
I/O
The TGRA2 and TGRB2 input capture input/output compare
output/PWM output pins.
TIOCA3, TIOCB3
TIOCC3, TIOCD3
I/O
The TGRA3 to TGRD3 input capture input/output compare
output/PWM output pins.
TIOCA4, TIOCB4
I/O
The TGRA4 and TGRB4 input capture input/output compare
output/PWM output pins.
TIOCA5, TIOCB5
I/O
The TGRA5 and TGRB5 input capture input/output compare
output/PWM output pins.
TCLKA, TCLKB
TCLKC, TCLKD
Input
Input pins for external clock signals.
TIOCA6, TIOCB6
TIOCC6, TIOCD6
I/O
The TGRA6 to TGRD6 input capture input/output compare
output/PWM output pins.
TIOCA7, TIOCB7
I/O
The TGRA7 and TGRB7 input capture input/output compare
output/PWM output pins.
TIOCA8, TIOCB8
I/O
The TGRA8 and TGRB8 input capture input/output compare
output/PWM output pins.
TIOCA9, TIOCB9
TIOCC9, TIOCD9
I/O
The TGRA9 to TGRD9 input capture input/output compare
output/PWM output pins.
TIOCA10, TIOCB10
I/O
The TGRA10 and TGRB10 input capture input/output compare
output/PWM output pins.
TIOCA11, TIOCB11
I/O
The TGRA11 and TGRB11 input capture input/output compare
output/PWM output pins.
TCLKE, TCLKF
TCLKG, TCLKH
Input
Input pins for external clock signals.
PO0 to PO31
Output
Output pins for the pulse signals.
Programmable pulse
generator
8-bit timer
Serial communications
interface (SCIc)
TMO0 to TMO3
Output
Output pins for the compare match signals.
TMCI0 to TMCI3
Input
Input pins for the external clock signals that drive for the
counters.
TMRI0 to TMRI3
Input
Input pins for the counter-reset signals.
Asynchronous mode/clock synchronous mode
SCK0 to SCK11
I/O
Input/output pins for clock signals.
RXD0 to RXD11
Input
Input pins for data reception.
TXD0 to TXD11
Output
Output pins for data transmission.
CTS0# to CTS11#
Input
Transmit/receive start control input pins
RTS0# to RTS11#
Output
Transmit/receive start control output pins
SSCL0 to SSCL11
I/O
Input/output pins for the I2C clock
SSDA0 to SSDA11
I/O
Input/output pins for the I2C data
I/O
Input/output pins for the clock
Simple I2C mode
Serial communications
interface (SCIc)
Simple SPI mode
SCK0 to SCK11
SMISO0 to SMISO11
I/O
Input/output pins for slave transmit data.
SMOSI0 to SMOSI11
I/O
Input/output pins for master transmit data.
SS0# to SS11#
Input
Input pins for chip select signals
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RX63N Group, RX631 Group
Table 1.4
1. Overview
Pin Functions (4/6)
Classifications
Pin Name
Serial communications
interface (SCId)
Asynchronous mode/clock synchronous mode
I/O
Description
SCK12
I/O
Input/output pin for clock signals.
RXD12
Input
Input pin for data reception.
TXD12
Output
Output pin for data transmission.
CTS12#
Input
Transmit/receive start control input pins
RTS12#
Output
Transmit/receive start control output pins
Simple I2C mode
SSCL12
I/O
Input/output pins for the I2C clock
SSDA12
I/O
Input/output pins for the I2C data
Simple SPI mode
SCK12
I/O
Input/output pins for the clock
SMISO12
I/O
Input/output pins for slave transmit data.
SMOSI12
I/O
Input/output pins for master transmit data.
SS12#
Input
Input pins for chip select signals
RXDX12
Input
Input pin for receive data
TXDX12
Output
Output pin for transmit data
Extended serial mode
I2C bus interface
Ethernet controller
SIOX12
I/O
Input/output pin for Transmit/receive data
SCL0[FM+],
SCL1 to SCL3
I/O
Input/output pin for clocks. Bus can be directly driven by the
N-channel open drain output.
SDA0[FM+],
SDA1 to SDA3
I/O
Input/output pin for data. Bus can be directly driven by the
N-channel open drain output.
REF50CK
Input
50-MHz reference clock. This pin inputs reference signals for
transmission/reception timings in RMII mode.
RMII_CRS_DV
Input
Indicates that there are carrier detection signals and valid
receive data on RMII_RXD1 and RMII_RXD0 in RMII mode.
RMII_TXD0, RMII_TXD1
Output
2-bit transmit data in RMII mode.
RMII_RXD0, RMII_RXD1
Input
2-bit receive data in RMII mode.
RMII_TXD_EN
Output
Output pin for data transmit enable signals in RMII mode.
RMII_RX_ER
Input
Indicates an error has occurred during reception of data in RMII
mode.
ET_CRS
Input
Carrier detection/data reception enable pin.
ET_RX_DV
Input
Indicates that there are valid receive data on ET_ERXD3 to
ET_ERXD0.
ET_EXOUT
Output
General-purpose external output pin.
ET_LINKSTA
Input
Inputs link status from the PHY-LSI.
ET_ETXD0 to ET_ETXD3
Output
4 bits of MII transmit data.
ET_ERXD0 to ET_ERXD3
Input
4 bits of MII receive data.
ET_TX_EN
Output
Transmit enable pin. Indicates that transmit data is ready on
ET_ETXD3 to ET_ETXD0.
ET_TX_ER
Output
Transmit error pin. Notifies the PHY_LSI of an error during
transmission.
ET_RX_ER
Input
Receive error pin. Recognizes an error during reception.
ET_TX_CLK
Input
Transmit clock pin. This pin inputs reference signals for output
timings from ET_TX_EN, ET_ETXD3 to ET_ETXD0, and
ET_TX_ER.
ET_RX_CLK
Input
Receive clock pin. This pin inputs reference signals for input
timings to ET_RX_DV, ET_ERXD3 to ET_ERXD0, and
ET_RX_ER.
ET_COL
Input
Inputs collision detection signals.
ET_WOL
Output
Receives Magic packets.
ET_MDC
Output
Outputs reference clock signals for information transfer via
ET_MDIO.
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May 13, 2014
Page 22 of 208
RX63N Group, RX631 Group
Table 1.4
1. Overview
Pin Functions (5/6)
Classifications
Pin Name
I/O
Description
Ethernet controller
ET_MDIO
I/O
Inputs or outputs bidirectional signals for exchange of
management information between the RX63N Group and the
PHY-LSI.
Parallel data capture unit
(PDC)
PIXCLK
Input
Parallel data transfer clock
VSYNC
Input
Vertical synchronization signal
HSYNC
Input
Horizontal synchronization signal
PIXD7 to PIXD0
Input
8-bit data
USB power pins
USB 2.0 host/function
module
CAN module
Serial peripheral
interface
IEBus controller
Realtime clock
12-bit A/D converter
10-bit A/D converter
D/A converter
PCKO
Output
Outputs parallel data transfer clock signal
VCC_USB
Input
Power supply pin. When the USB is not to be used, connect it to
the VCC pin.
VSS_USB
Input
Ground pin. When the USB is not to be used, connect it to the
VSS pin.
USB0_DP, USB1_DP
I/O
Inputs or outputs USB transceiver D+ data.
USB0_DM, USB1_DM
I/O
Inputs or outputs USB transceiver D- data.
USB0_VBUS, USB1_VBUS
Input
Input pins for detection of connection and disconnection of the
USB cable.
USB0_EXICEN
Output
Output pin for control the low power of the OTG chip.
USB0_VBUSEN
Output
Supply enable pin of VBUS (5 V) for the OTG chip.
USB0_OVRCURA,
USB0_OVRCURB,
Input
Input pin for detection of external over current.
USB0_ID
Input
ID input pin of mini-AB connector at the OTG operation.
USB0_DPUPE,
USB1_DPUPE
Output
Pull-up control pins of the D+ signal at the function operation.
USB0_DPRPD
Output
Pull-down control pins of the D+ signal at the host operation.
USB0_DRPD
Output
Pull-down control pins of the D- signal at the host operation.
CRX0 to CRX2
Input
Input pin.
CTX0 to CTX2
Output
Output pin.
RSPCKA, RSPCKB
RSPCKC
I/O
Clock input/output pin.
MOSIA, MOSIB, MOSIC
I/O
Inputs or outputs data output from the master.
MISOA, MISOB, MISOC
I/O
Inputs or outputs data output from the slave.
SSLA0, SSLB0, SSLC0
I/O
Input or output pins slave selection
SSLA1 to SSLA3
SSLB1 to SSLB3
SSLC1 to SSLC3
Output
Output pins slave selection
IERXD
Input
Input pin for data reception.
IETXD
Output
Output pin for data transmission.
RTCOUT
Output
Output pin for 1-Hz clock.
RTCIC0 to RTCIC2
Input
Time capture event input pin
AN000 to AN020
Input
Input pins for the analog signals to be processed by the A/D
converter.
ADTRG0#
Input
Input pins for the external trigger signals that start the A/D
conversion.
AN0 to AN7
Input
Input pins for the analog signals to be processed by the A/D
converter.
ANEX0
Output
Extended analog output pin
ANEX1
Input
Extended analog input pin
ADTRG#
Input
Input pins for the external trigger signals that start the A/D
conversion.
DA0, DA1
Output
Output pins for the analog signals to be processed by the D/A
converter.
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 23 of 208
RX63N Group, RX631 Group
Table 1.4
1. Overview
Pin Functions (6/6)
Classifications
Pin Name
I/O
Description
Analog power supply
AVCC0
Input
Analog voltage supply pin for the 12-bit A/D converter. Connect
this pin to VCC if the 12-bit A/D converter is not to be used.
AVSS0
Input
Analog ground pin for the 12-bit A/D converter. Connect this pin
to VSS if the 12-bit A/D converter is not to be used.
VREFH0
Input
Analog reference voltage supply pin for the 12-bit A/D converter.
Connect this pin to VCC if the 12-bit A/D converter is not to be
used.
VREFL0
Input
Analog reference ground pin for the 12-bit A/D converter.
Connect this pin to VSS if the 12-bit A/D converter is not to be
used.
VREFH
Input
Reference voltage input pin for the 10-bit A/D converter and D/A
converter. This is used as the analog power supply for the
respective modules. Connect this pin to VCC if neither the 10-bit
A/D converter nor the D/A converter is in use.
VREFL
Input
Reference ground pin for the 10-bit A/D converter and D/A
converter. This is used as the analog ground for the respective
modules. Set this pin to the same potential as the VSS pin.
P00 to P03, P05, P07
I/O
6-bit input/output pins.
P10 to P17
I/O
8-bit input/output pins.
P20 to P27
I/O
8-bit input/output pins.
P30 to P37
I/O
8-bit input/output pins. (P35 is an input pin)
P40 to P47
I/O
8-bit input/output pins.
P50 to P57
I/O
8-bit input/output pins.
P60 to P67
I/O
8-bit input/output pins.
P70 to P77
I/O
8-bit input/output pins.
P80 to P87
I/O
8-bit input/output pins.
P90 to P97
I/O
8-bit input/output pins.
PA0 to PA7
I/O
8-bit input/output pins.
PB0 to PB7
I/O
8-bit input/output pins.
PC0 to PC7
I/O
8-bit input/output pins.
I/O ports
PD0 to PD7
I/O
8-bit input/output pins.
PE0 to PE7
I/O
8-bit input/output pins.
PF0 to PF5
I/O
6-bit input/output pins.
PG0 to PG7
I/O
8-bit input/output pins.
PJ3, PJ5
I/O
2-bit input/output pins.
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 24 of 208
RX63N Group, RX631 Group
1.5
1. Overview
Pin Assignments
Figure 1.5 to Figure 1.12 show the pins assignments. Table 1.5 to Table 1.13 show the list of pins and pin functions.
Power pins and I/O ports are shown in the pin assignment diagrams.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
15
PE2
PE3
P70
P65
P67
VSS
VCC
PG7
PA6
PB0
P72
PB4
VSS
VCC
PC1
15
14
PE1
PE0
VSS
PE7
PG3
PA0
PA1
PA2
PA7
VCC
PB1
PB5
P73
P75
P74
14
13
P63
P64
PE4
VCC
PG2
PG4
PG6
PA3
VSS
P71
PB3
PB7
PC0
PC2
P76
13
12
P60
VSS
P62
PE5
PE6
P66
PG5
PA4
PA5
PB2
PB6
P77
PC3
PC4
P80
12
11
PD6
PG1
VCC
P61
P81
P82
PC6
VCC
11
10
P97
PD4
PG0
PD7
PC5
PC7
P83
VSS
10
9
VCC
P96
PD3
PD5
P50
P51
P52
P84
9
8
P94
PD1
PD2
VSS
P53
VCC_
USB
USB1_
DP
USB1_
DM
8
7
VSS
P92
PD0
P95
P54
P55
VSS_
USB
USB0_
DP
7
6
VCC
P91
P90
P93
P56
P57
VCC_
USB
USB0_
DM
6
5
P46
P47
P45
P44
NC
P13
P12
P10
P11
5
4
P42
P41
P43
P00
VSS
BSCANP
PF4
P35
PF3
PF1
P25
P86
P15
P14
P85
4
3 VREFL0
P40
VREFH0
P03
PF5
PJ3
MD/
FINED
RES#
P34
PF2
PF0
P24
P22
P87
P16
3
2 AVCC0
P07
VREFH
P02
EMLE
VCL
XCOUT
VSS
VCC
P32
P30
P26
P23
P17
P20
2
1
AVSS0
P05
VREFL
P01
PJ5
VBATT
XCIN
XTAL
EXTAL
P33
P31
P27
VCC
VSS
P21
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Note:
Figure 1.3
RX63N Group
RX631 Group
PTLG0177KA-A
(177-pin TFLGA)
(Top perspective view)
This figure indicates the power supply pins and I/O port pins. For the pin configuration, see Table 1.5, List of
Pin and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA).
Pin Assignment (177-Pin TFLGA)
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 25 of 208
RX63N Group, RX631 Group
1. Overview
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
15
PE2
PE3
P70
P65
P67
VSS
VCC
PG7
PA6
PB0
P72
PB4
VSS
VCC
PC1
15
14
PE1
PE0
VSS
PE7
PG3
PA0
PA1
PA2
PA7
VCC
PB1
PB5
P73
P75
P74
14
13
P63
P64
PE4
VCC
PG2
PG4
PG6
PA3
VSS
P71
PB3
PB7
PC0
PC2
P76
13
12
P60
VSS
P62
PE5
PE6
P66
PG5
PA4
PA5
PB2
PB6
P77
PC3
PC4
P80
12
11
PD6
PG1
VCC
P61
P81
P82
PC6
VCC
11
10
P97
PD4
PG0
PD7
PC5
PC7
P83
VSS
10
9
VCC
P96
PD3
PD5
P50
P51
P52
P84
9
8
P94
PD1
PD2
VSS
P53
VCC_
USB
USB1_
DP
USB1_
DM
8
7
VSS
P92
PD0
P95
P54
P55
VSS_
USB
USB0_
DP
7
6
VCC
P91
P90
P93
P56
P57
VCC_
USB
USB0_
DM
6
5
P46
P47
P45
P44
P13
P12
P10
P11
5
4
P42
P41
P43
P00
VSS
BSCANP
PF4
P35
PF3
PF1
P25
P86
P15
P14
P85
4
3 VREFL0
P40
VREFH0
P03
PF5
PJ3
MD/
FINED
RES#
P34
PF2
PF0
P24
P22
P87
P16
3
2 AVCC0
P07
VREFH
P02
EMLE
VCL
XCOUT
VSS
VCC
P32
P30
P26
P23
P17
P20
2
1
AVSS0
P05
VREFL
P01
PJ5
VBATT
XCIN
XTAL
EXTAL
P33
P31
P27
VCC
VSS
P21
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Note:
Figure 1.4
RX63N Group
RX631 Group
PTBG0176GA-A
(176-pin LFBGA)
(Top perspective view)
This figure indicates the power supply pins and I/O port pins. For the pin configuration, see Table 1.5, List of
Pin and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA).
Pin Assignment (176-Pin LFBGA)
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 26 of 208
1. Overview
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
133
88
134
87
135
86
136
85
137
84
138
83
139
82
140
81
141
80
142
79
143
78
144
77
145
76
146
75
147
74
148
73
149
72
RX63N Group
RX631 Group
PLQP0176KB-A
(176-pin LQFP)
(Top view)
150
151
152
153
154
155
156
157
158
159
160
71
70
69
68
67
66
65
64
63
62
61
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
P74
P75
PC2
P76
P77
PC3
PC4
P80
P81
P82
PC5
PC6
PC7
VCC
P83
VSS
P50
P51
P52
P84
P53
P54
P55
VCC_USB
USB1_DP
USB1_DM
P56
P57
VSS_USB
USB0_DP
USB0_DM
VCC_USB
P10
P11
P12
P13
P85
P14
P15
P86
P16
P87
P17
P20
AVSS0
P05
VREFH
P03
VREFL
P02
P01
P00
PF5
EMLE
PJ5
VSS
PJ3
VCL
VBATT
NC
PF4
MD/FINED
XCIN
XCOUT
RES#
P37/XTAL
VSS
P36/EXTAL
VCC
P35
P34
P33
P32
PF3
PF2
P31
P30
PF1
PF0
P27
P26
P25
VCC
P24
VSS
P23
P22
P21
18
45
17
46
176
16
47
175
15
48
174
14
49
173
13
50
172
12
51
171
11
52
170
10
53
169
9
54
168
8
55
167
7
56
166
6
57
165
5
58
164
4
59
163
3
60
162
2
161
1
PE2
PE1
PE0
P64
P63
P62
P61
VSS
P60
VCC
PD7
PG1
PD6
PG0
PD5
PD4
P97
PD3
VSS
P96
VCC
PD2
P95
PD1
P94
PD0
P93
P92
P91
VSS
P90
VCC
P47
P46
P45
P44
P43
P42
P41
VREFL0
P40
VREFH0
AVCC0
P07
132
PE3
PE4
PE5
VSS
P70
VCC
PE6
PE7
P65
PG2
P66
PG3
P67
PG4
PA0
VSS
PG5
VCC
PA1
PG6
PA2
PG7
PA3
PA4
PA5
PA6
PA7
VSS
PB0
VCC
P71
P72
PB1
PB2
PB3
PB4
PB5
PB6
PB7
P73
VSS
PC0
VCC
PC1
RX63N Group, RX631 Group
Note:
Figure 1.5
This figure indicates the power supply pins and I/O port pins. For the pin configuration, see Table 1.6, List of
Pin and Pin Functions (176-Pin LQFP).
Pin Assignment (176-Pin LQFP)
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 27 of 208
RX63N Group, RX631 Group
1. Overview
A
B
C
D
E
F
G
H
J
K
L
M
N
13
PE3
PE4
VSS
PE6
P67
PA2
PA4
PA7
PB1
PB5
VSS
VCC
P74
13
12
PE1
PE2
P70
PE5
P65
PA1
VCC
PB0
PB2
PB6
P73
PC1
P75
12
11
P62
P61
PE0
VCC
P66
VSS
PA6
P71
PB4
PB7
PC2
PC0
PC3
11
10
VSS
VCC
P63
PE7
PA0
PA3
PA5
P72
PB3
P76
PC4
P77
P82
10
9
PD6
PD4
PD7
P64
P80
PC5
P81
PC7
9
8
PD2
PD0
PD3
P60
VCC
P83
PC6
VSS
8
7
P92
P91
PD1
PD5
P51
P52
P50
P55
7
6
P90
P47
VSS
P93
P53
P56
VSS_
USB
USB0_
DP
6
5
P45
P43
P46
VCC
P44
P54
P13
VCC_
USB
USB0_
DM
5
4
P42
VREFL0
P41
P01
EMLE
VBATT
BSCANP
P35
P30
P15
P24
P12
P14
4
3
P40
P05
VREFH0
P03
PJ5
PJ3
MD/
FINED
VSS
P32
P31
P16
P86
P87
3
2
P07
AVCC0
P02
PF5
VCL
XCOUT
RES#
VCC
P33
P26
P23
P17
P20
2
1
AVSS0
VREFH
VREFL
P00
VSS
XCIN
XTAL
EXTAL
P34
P27
P25
P22
P21
1
A
B
C
D
E
F
G
H
J
K
L
M
N
Note:
Figure 1.6
RX63N Group
RX631 Group
PTLG0145KA-A
(145-pin TFLGA)
(Top perspective view)
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.7, List of Pins and Pin Functions (145-Pin TFLGA).
Pin Assignment (145-Pin TFLGA)
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 28 of 208
73
74
VSS
PC0
VCC
PC1
75
76
77
PB6
PB7
P73
79
78
PB4
PB5
80
81
82
83
84
85
86
87
88
89
90
PA4
VCC
PA5
PA6
PA7
PB0
P71
P72
PB1
PB2
PB3
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
PE3
PE4
PE5
VSS
P70
VCC
PE6
PE7
P65
P66
P67
PA0
PA1
PA2
PA3
VSS
1. Overview
108
RX63N Group, RX631 Group
PE2
109
72
P74
PE1
110
71
P75
PE0
111
70
PC2
P64
112
69
P76
P63
113
68
P62
114
67
P77
PC3
P61
VSS
115
66
PC4
116
65
P80
P60
117
64
P81
VCC
118
63
P82
PD7
119
62
PC5
PD6
120
61
PC6
PD5
121
60
PC7
PD4
122
59
PD3
123
VCC
P83
PD2
124
PD1
PD0
125
P93
127
P92
128
P91
129
VSS
130
P90
VCC
131
RX63N Group
RX631 Group
PLQP0144KA-A
(144-pin LQFP)
(Top view)
58
57
P13
P42
138
43
P14
P41
VREFL0
139
42
P15
140
41
P86
P40
141
40
P16
VREFH0
AVCC0
142
39
143
38
P87
P17
P07
144
37
P20
Figure 1.7
P23
P22
P21
P34
P33
P32
P31
P30
P27
P26
P25
P24
XCIN
PH6/XCOUT
RES#
P37/XTAL
VSS
P36/EXTAL
VCC
P35
PJ3
VCL
VBATT
MD/FINED
12
11
PJ5
VSS
10
9
PF5
EMLE
8
7
P01
P00
6
5
4
3
2
1
AVSS0
P05
VREFH
P03
VREFL
P02
Note:
36
44
35
137
34
P12
P43
33
VCC_USB
45
32
46
136
31
135
P44
30
P45
29
USB0_DP
USB0_DM
28
47
27
134
26
P46
25
48
24
133
23
VSS_USB
P47
22
49
21
P56
132
20
P55
50
19
P54
51
18
P53
52
17
P52
53
16
P51
54
15
55
126
14
VSS
P50
13
56
This figure indicates the power supply pins and I/O port pins. For the pin configuration, see Table 1.8, List of
Pins and Pin Functions (144-Pin LQFP).
Pin Assignment (144-Pin LQFP)
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 29 of 208
RX63N Group, RX631 Group
1. Overview
RX63N Group, RX631 Group
PTLG0100JA-A (100-pin TFLGA)
(Top view)
A
B
C
D
E
F
G
H
J
K
10
PE2
PE3
PE4
PA0
PA3
VSS
VCC
PB7
PC1
PC2
10
9
PE1
PD7
PE5
PA1
PA5
PA7
PB1
PB6
PC0
PC3
9
8
PE0
PD6
PD5
PE7
PA4
PB0
PB4
PC6
PC4
PC5
8
7
PD4
PD3
PD2
PE6
PA6
PB2
PB5
PC7
P50
P51
7
6
PD0
PD1
P47
P46
PA2
PB3
P52
P54
VCC_
USB
USB0_
DP
6
5
P43
P44
P42
P45
P41
P12
P53
P55
VSS_
USB
USB0_
DM
5
P34
P32
P27
P15
P13
P14
4
4 VREFL0
VREFH0 VBATT
AVCC0
PJ3
MD/
FINED
RES#
P35
P30
P16
P17
P20
3
2 VREFH
AVSS0
VREFL
XCOUT
VSS
VCC
P31
P25
P21
P22
2
1
P05
EMLE
VCL
XCIN
XTAL
EXTAL
P33
P26
P24
P23
1
A
B
C
D
E
F
G
H
J
K
3
P07
Note:
Figure 1.8
P40
This figure indicates the power supply pins and I/O port pins. For the pin configuration, see Table
1.10, List of Pins and Pin Functions (100-Pin LQFP).
Pin Assignment (100-Pin TFLGA)
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 30 of 208
Note:
Figure 1.9
PE3
PE4
PE5
PE6
PE7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
VSS
PB0
VCC
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1. Overview
75
RX63N Group, RX631 Group
PE2
76
50
PE1
77
49
PC2
PC3
PE0
78
48
PC4
PD7
79
47
PC5
PD6
80
46
PC6
PD5
81
45
PC7
PD4
82
44
P50
PD3
83
43
P51
PD2
84
42
P52
PD1
85
41
P53
PD0
86
40
P54
P47
87
39
P55
P46
88
38
VSS_USB
P45
89
37
USB0_DP
P44
90
36
USB0_DM
P43
91
35
VCC_USB
P42
92
34
P12
P41
93
33
P13
VREFL0
94
32
P14
P40
95
31
P15
VREFH0
96
30
P16
AVCC0
97
29
P17
P07
98
28
P20
AVSS0
99
27
P21
P05
100
26
P22
14
15
16
17
18
19
20
21
22
23
24
25
VCC
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
P23
9
PH6/XCOUT
13
8
XCIN
P36/EXTAL
7
MD/FINED
12
6
VBATT
VSS
5
VCL
11
4
PJ3
P37/XTAL
3
VREFL
10
2
EMLE
RES#
1
VREFH
RX63N Group
RX631 Group
PLQP0100KB-A
(100-pin LQFP)
(Top view)
This figure indicates the power supply pins and I/O port pins. For the pin configuration, see Table 1.10, List of
Pins and Pin Functions (100-Pin LQFP).
Pin Assignment (100-Pin LQFP)
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 31 of 208
RX63N Group, RX631 Group
1. Overview
RX631 Group
PTLG0064JA-A (64-pin TFLGA)
(Top perspective view)
Figure 1.10
A
B
C
D
E
F
G
H
8
PE3
PE4
PA0
PA3
PB0
PB3
PB6
PB7
8
7
PE2
PE1
PE5
PA1
VSS
PB5
PC3
PC2
7
6
VREFL
P46
PE0
PA4
VCC
PB1
PC6
5
VREFH
P44
P43
PA6
PC4
P15
VCC_USB USB1_DM 5
4
VREFL0
P42
P41
P14
P16
PC5
VSS_USB USB0_DP 4
3
VREFH0
P40
EMLE
P27
P30
P31
VCC_USB USB0_DM 3
2
AVCC0
AVSS0
MD/FINED
RES#
VBATT
P35
P26
P17
2
1
P05
VCL
XCIN
XCOUT
VSS
VCC
EXTAL
XTAL
1
A
B
C
D
E
F
G
H
USB1_DP 6
Pin Assignment (64-pin TFLGA)
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 32 of 208
PB0
VCC
PB1
PB3
PB5
PB6
PB7
37
36
35
34
33
VSS
40
38
PA6
41
39
PA3
PA4
43
42
PA0
PA1
PE5
44
PE4
46
45
PE3
47
PE2
49
32
PC2
PE1
50
31
PC3
PE0
51
30
PC4
VREFL
52
29
PC5
P46
53
28
PC6
VREFH
54
27
PC7
P44
55
26
P54
P43
56
25
P42
57
24
P55
VSS_USB
P41
58
23
USB0_DP
VREFL0
59
22
USB0_DM
P40
60
21
VCC_USB
VREFH0
61
20
P14
AVCC0
62
19
P15
P05
63
18
P16
AVSS0
64
17
P17
Note:
Figure 1.11
1. Overview
48
RX63N Group, RX631 Group
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
EMLE
VCL
MD/FINED
XCIN
XCOUT
RES#
P37/XTAL
VSS
P36/EXTAL
VCC
P35/NMI
VBATT
P31
P30
P27
P26
RX631 Group
PLQP0064KB-A
(64-pin LQFP)
(Top view)
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.12, List of Pins and Pin Functions (64-Pin LQFP).
Pin Assignment (64-Pin LQFP)
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 33 of 208
PB1
PB3
PB5
26
25
VCC
28
27
PB0
29
PA4
32
PA6
PA3
33
VSS
PA1
30
PE4
34
31
PE3
35
PE2
37
24
PC4
PE1
38
23
PC5
VREFL
39
22
PC6
P46
40
21
VREFH
41
20
PC7
VSS_USB
P42
42
19
USB0_DP
18
USB0_DM
17
VCC_USB
16
P14
RX631 Group
PLQP0048KB-A
(48-pin LQFP)
(Top view)
7
8
9
10
11
12
P35/NMI
P31
P30
P27
P26
P17
VCC
13
6
48
P36/EXTAL
P16
AVSS0
5
14
4
47
VSS
P15
AVCC0
P37/XTAL
15
3
VREFH0
46
RES#
45
2
P40
MD/FINED
44
1
VREFL0
VCL
P41
43
Note:
Figure 1.12
1. Overview
36
RX63N Group, RX631 Group
This figure indicates the power supply pins and I/O port pins. For the pin
configuration, see Table 1.13, List of Pins and Pin Functions (48-Pin LQFP).
Pin Assignment (48-Pin LQFP)
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 34 of 208
RX63N Group, RX631 Group
Table 1.5
1. Overview
List of Pin and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (1/5)
Pin Number
177-Pin
TFLGA
176-Pin
LFBGA
Power Supply
Clock System
Control
A1
AVSS0
A2
AVCC0
A3
VREFL0
I/O Port
Bus
EXDMAC
SDRAMC
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB, and PDC)
Interrupt
S12AD,
AD, DA
A4
P42
IRQ10-DS
AN002
A5
P46
IRQ14-DS
AN006
IRQ6
AN6
A6
VCC
A7
VSS
A8
P94
A20/D20
A10
P97
A23/D23
A11
PD6
D6[A6/D6]
A12
P60
CS0#
A13
P63
CS3#/CAS#
A14
PE1
A15
PE2
B1
B2
A9
VCC
MTIC5V/POE1#
SSLC2
D9[A9/D9]
MTIOC4C/TIOCD9/PO18
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/SSLB2/RSPCKB
D10[A10/D10]
MTIOC4A/TIOCA9/PO23
RXD12/SMISO12/
SSCL12/RXDX12/SSLB3/
MOSIB
ANEX1
IRQ7-DS
AN0
P05
IRQ13
DA1
P07
IRQ15
ADTRG0#
B3
P40
IRQ8-DS
AN000
B4
P41
IRQ9-DS
AN001
B5
P47
IRQ15-DS
AN007
B6
P91
A17/D17
SCK7
AN015
B7
P92
A18/D18
RXD7/SMISO7/SSCL7
AN016
B8
PD1
D1[A1/D1]
B9
P96
A22/D22
B10
PD4
D4[A4/D4]
PG1
D25
P64
CS4#/WE#
B11
B12
MTIOC4B/TIOCB7/
TCLKG
MOSIC/CTX0
IRQ1
AN009
POE3#
SSLC0
IRQ4
AN012
VSS
B13
B14
PE0
D8[A8/D8]
TIOCC9
SCK12/SSLB1
ANEX0
B15
PE3
D11[A11/D11]
MTIOC4B/TIOCB9/PO26/
POE8#
ET_ERXD3/CTS12#/
RTS12#/SS12#/MISOB
AN1
C1
VREFL
C2
VREFH
C3
VREFH0
C4
P43
IRQ11-DS
AN003
IRQ13-DS
AN005
IRQ0
AN008
C5
P45
C6
P90
A16/D16
C7
PD0
D0[A0/D0]
C8
PD2
D2[A2/D2]
MTIOC4D/TIOCA8
MISOC/CRX0
IRQ2
AN010
C9
PD3
D3[A3/D3]
TIOCB8/TCLKH/POE8#
RSPCKC
IRQ3
AN011
C10
PG0
D24
C12
P62
CS2#/RAS#
C13
PE4
D12[A12/D12]
MTIOC4D/MTIOC1A/
TIOCA10/PO28
ET_ERXD2/SSLB0
C11
TXD7/SMOSI7/SSDA7
TIOCA7
AN014
VCC
R01DS0098EJ0180 Rev.1.80
May 13, 2014
AN2
Page 35 of 208
RX63N Group, RX631 Group
Table 1.5
1. Overview
List of Pin and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (2/5)
Pin Number
177-Pin
TFLGA
176-Pin
LFBGA
Power Supply
Clock System
Control
C14
VSS
C15
SDCLK
I/O Port
Bus
EXDMAC
SDRAMC
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB, and PDC)
Interrupt
S12AD,
AD, DA
P70
D1
P01
TMCI0
RXD6/SMISO6/SSCL6
IRQ9
AN019
D2
P02
TMCI1
SCK6
IRQ10
AN020
D3
P03
IRQ11
DA0
D4
P00
D5
P44
D6
P93
A19/D19
P95
A21/D21
D9
PD5
D5[A5/D5]
MTIC5W/POE2#
SSLC1
IRQ5
AN013
D10
PD7
D7[A7/D7]
MTIC5U/POE0#
SSLC3
IRQ7
AN7
D11
P61
CS1#/SDCS#
D12
PE5
D13[A13/D13]
MTIOC4C/MTIOC2B/
TIOCB10
ET_RX_CLK/REF50CK/
RSPCKB
IRQ5
AN3
D14
PE7
D15[A15/D15]
TIOCB11
MISOB
IRQ7
AN5
D15
P65
CS5#/CKE
D7
D8
D13
CTS7#/RTS7#/SS7#
AN017
PJ5
PF5
E4
VSS
NC
E12
IRQ4
PE6
D14[A14/D14]
E13
TRDATA0
PG2
D26
E14
TRDATA1
PG3
D27
P67
CS7#/DQM1
E15
F1
VBATT
F2
VCL
F3
PJ3
TIOCA11
MTIOC3C
MOSIB
IRQ6
CRX2*3
IRQ15
AN4
CTS6#/RTS6#/CTS0#/
RTS0#/SS6#/SS0#
BSCANP
F12
TRSYNC
F14
F15
AN018
AN004
EMLE
E5*1
F13
IRQ8
IRQ12-DS
VCC
E3
F4
TXD6/SMOSI6/SSDA6
VSS
E1
E2
TMRI0
P66
CS6#/DQM0
PG4
D28
PA0
A0/BC0#/DQM2
CTX2*3
MTIOC4A/TIOCA0/PO16
ET_TX_EN/
RMII_TXD_EN/SSLA1
MTIOC0B/MTCLKC/
TIOCB0/PO17
ET_WOL/SCK5/SSLA2
VSS
G1
XCIN
G2
XCOUT
G3
MD/FINED
G4
TRST#
G12
TRCLK
PG5
D29
G13
TRDATA2
PG6
D30
PA1
A1/DQM3
G14
G15
VCC
H1
XTAL
H2
VSS
PF4
IRQ11
P37
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 36 of 208
RX63N Group, RX631 Group
Table 1.5
1. Overview
List of Pin and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (3/5)
Pin Number
177-Pin
TFLGA
176-Pin
LFBGA
H3
Power Supply
Clock System
Control
I/O Port
Bus
EXDMAC
SDRAMC
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB, and PDC)
Interrupt
RES#
H4
P35
H12
PA4
A4
MTIC5U/MTCLKA/
TIOCA1/TMRI0/PO20
ET_MDC/TXD5/SMOSI5/
SSDA5/SSLA0
IRQ5-DS
H13
PA3
A3
MTIOC0D/MTCLKD/
TIOCD0/TCLKB/PO19
ET_MDIO/RXD5/SMISO5/
SSCL5
IRQ6-DS
H14
PA2
A2
PO18
RXD5/SMISO5/SSCL5/
SSLA3
D31
MTIOC0A/TMCI3/PO12/
POE2#
SCK6/SCK0/
USB0_DPRPD
TIOCB1/PO21
ET_LINKSTA/RSPCKA
H15
TRDATA3
PG7
J1
EXTAL
P36
J2
VCC
J3
J4
NMI
P34
TMS
J12
J13
IRQ4
PF3
PA5
A5
VSS
J14
PA7
A7
TIOCB2/PO23
ET_WOL/MISOA
J15
PA6
A6
MTIC5V/MTCLKB/
TIOCA2/TMCI3/PO22/
POE2#
ET_EXOUT/CTS5#/
RTS5#/SS5#/MOSIA
K1
P33
MTIOC0D/TIOCD0/
TMRI3/PO11/POE3#
RXD6/RXD0/SMISO6/
SMISO0/SSCL6/SSCL0/
CRX0/PCKO
IRQ3-DS
K2
P32
MTIOC0C/TIOCC0/TMO3/
PO10/RTCOUT/RTCIC2
TXD6/TXD0/SMOSI6/
SMOSI0/SSDA6/SSDA0/
CTX0/USB0_VBUSEN/
VSYNC
IRQ2-DS
K3
TDI
K4
TCK/FINEC
PF2
RXD1/SMISO1/SSCL1
PF1
SCK1
K12
PB2
A10
K13
P71
CS1#
K15
PB0
A8
L1
L2
K14
L3
S12AD,
AD, DA
TIOCC3/TCLKC/PO26
ET_RX_CLK/REF50CK/
CTS4#/RTS4#/CTS6#/
RTS6#/SS4#/SS6#
ET_MDIO
VCC
TDO
MTIC5W/TIOCA3/PO24
ET_ERXD1/RMII_RXD1/
RXD4/RXD6/SMISO4/
SMISO6/SSCL4/SSCL6/
RSPCKA
IRQ12
P31
MTIOC4D/TMCI2/PO9/
RTCIC1
CTS1#/RTS1#/SS1#/
SSLB0/USB0_DPUPE
IRQ1-DS
P30
MTIOC4B/TMRI3/PO8/
RTCIC0/POE8#
RXD1/SMISO1/SSCL1/
MISOB/USB0_DRPD
IRQ0-DS
PF0
TXD1/SMOSI1/SSDA1
L4
P25
CS5#/EDACK1
MTIOC4C/MTCLKB/
TIOCA4/PO5
RXD3/SMISO3/SSCL3/
USB0_DPRPD/HSYNC
L12
PB6
A14
MTIOC3D/TIOCA5/PO30
ET_ETXD1/RMII_TXD1/
RXD9/SMISO9/SSCL9
L13
PB3
A11
MTIOC0A/MTIOC4A/
TIOCD3/TCLKD/TMO0/
PO27/POE3#
ET_RX_ER/RMII_RX_ER/
SCK4/SCK6
L14
PB1
A9
MTIOC0C/MTIOC4C/
TIOCB3/TMCI0/PO25
ET_ERXD0/RMII_RXD0/
TXD4/TXD6/SMOSI4/
SMOSI6/SSDA4/SSDA6
L15
P72
CS2#
M1
P27
CS7#
R01DS0098EJ0180 Rev.1.80
May 13, 2014
ADTRG0#
IRQ4-DS
ET_MDC
MTIOC2B/TMCI3/PO7
SCK1/RSPCKB
Page 37 of 208
RX63N Group, RX631 Group
Table 1.5
1. Overview
List of Pin and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (4/5)
Pin Number
Timer
Communications
I/O Port
Bus
EXDMAC
SDRAMC
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB, and PDC)
M2
P26
CS6#
MTIOC2A/TMO1/PO6
TXD1/CTS3#/RTS3#
SMOSI1/SS3#/SSDA1/
MOSIB
M3
P24
CS4#/EDREQ1
MTIOC4A/MTCLKA/
TIOCB4/TMRI1/PO4
SCK3/USB0_VBUSEN/
PIXCLK
177-Pin
TFLGA
176-Pin
LFBGA
Power Supply
Clock System
Control
Interrupt
S12AD,
AD, DA
IRQ3
ADTRG#
M4
P86
TIOCA0
PIXD1
M5
P13
MTIOC0B/TIOCA5/TMO3/
PO13
TXD2/SMOSI2/SSDA2/
SDA0[FM+]
M6
P56
WR2#/BC2#/
EDACK1
MTIOC3C/TIOCA1
M7
P54
ALE/EDACK0
MTIOC4B/TMCI1
M8
P53*2
BCLK
M9
P50
WR0#/WR#
M10
PC5
A21/CS2#/
WAIT#
MTIOC3B/MTCLKD/
TIOCD6/TCLKF/TMRI2/
PO29
ET_ETXD2/SCK8/
RSPCKA
M11
P81
EDACK0
MTIOC3D/PO27
ET_ETXD0/RMII_TXD0/
RXD10/SMISO10/SSCL10
M12
P77
CS7#
PO23
ET_RX_ER/RMII_RX_ER/
TXD11/SMOSI11/SSDA11
M13
PB7
A15
MTIOC3B/TIOCB5/PO31
ET_CRS/RMII_CRS_DV/
TXD9/SMOSI9/SSDA9
M14
PB5
A13
MTIOC2A/MTIOC1B/
TIOCB4/TMRI1/PO29/
POE1#
ET_ETXD0/RMII_TXD0/
SCK9
M15
PB4
A12
TIOCA4/PO28
ET_TX_EN/
RMII_TXD_EN/CTS9#/
RTS9#/SS9#
N2
P23
EDACK0
MTIOC3D/MTCLKD/
TIOCD3/PO3
TXD3/CTS0#/RTS0#/
SMOSI3/SS0#/SSDA3/
USB0_DPUPE/PIXD7
N3
P22
EDREQ0
MTIOC3B/MTCLKC/
TIOCC3/TMO0/PO2
SCK0/USB0_DRPD/
PIXD6
N4
P15
MTIOC0B/MTCLKB/
TIOCB2/TCLKB/TMCI2/
PO13
RXD1/SCK3/SMISO1/
SSCL1/CRX1-DS/
USB1_DPUPE/PIXD0
IRQ5
N5
P12
MTIC5U/TMCI1
RXD2/SMISO2/SSCL2/
SCL0[FM+]
IRQ2
N6
P57
WAIT#/WR3#/
BC3#/EDREQ1
N7
P55
WAIT#/
EDREQ0
MTIOC4D/TMO3
ET_EXOUT/CRX1
IRQ10
N9
P51
WR1#/BC1#/
WAIT#
N10
PC7
A23/CS0#
MTIOC3A/MTCLKB/
TIOCB6/TMO2/PO31
ET_COL/TXD8/SMOSI8/
SSDA8/MISOA
N11
P82
EDREQ1
MTIOC4A/PO28
ET_ETXD1/RMII_TXD1/
TXD10/SMOSI10/SSDA10
N12
PC3
A19
MTIOC4D/TCLKB/PO24
ET_TX_ER/TXD5/
SMOSI5/SSDA5/IETXD
N13
PC0
A16
MTIOC3C/TCLKC/PO17
ET_ERXD3/CTS5#/
RTS5#/SS5#/SSLA1/
SCL3
N14
P73
CS3#
PO16
ET_WOL
N1
N8
N15
ET_LINKSTA/CTS2#/
RTS2#/SS2#/CTX1
TXD2/SMOSI2/SSDA2/
SSLB1
VCC
VCC_USB
SCK2/SSLB2
IRQ14
IRQ14
VSS
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 38 of 208
RX63N Group, RX631 Group
Table 1.5
1. Overview
List of Pin and Pin Functions (177-Pin TFLGA, 176-Pin LFBGA) (5/5)
Pin Number
177-Pin
TFLGA
176-Pin
LFBGA
P1
Power Supply
Clock System
Control
I/O Port
Bus
EXDMAC
SDRAMC
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB, and PDC)
S12AD,
AD, DA
IRQ7
ADTRG#
VSS
P2
P17
MTIOC3A/MTIOC3B/
TIOCB0/TCLKD/TMO1/
PO15/POE8#
SCK1/TXD3/SMOSI3/
SSDA3/MISOA/SDA2-DS/
IETXD/USB1_VBUS/
PIXD3
P3
P87
TIOCA2
PIXD2
P4
P14
MTIOC3A/MTCLKA/
TIOCB5/TCLKA/TMRI2/
PO15
CTS1#/RTS1#/SS1#/
CTX1/USB0_DPUPE/
USB0_OVRCURA
P5
P10
MTIC5W/TMRI3
P6
VCC_USB
P7
VSS_USB
P8
IRQ4
IRQ0
USB1_DP
P9
P52
RD#
P10
P83
EDACK1
MTIOC4C
ET_CRS/RMII_CRS_DV/
CTS10#/RTS10#/SS10#
P11
PC6
A22/CS1#
MTIOC3C/MTCLKA/
TIOCA6/TMCI2/PO30
ET_ETXD3/RXD8/
SMISO8/SSCL8/MOSIA
P12
PC4
A20/CS3#
MTIOC3D/MTCLKC/
TIOCC6/TCLKE/TMCI1/
PO25/POE0#
ET_TX_CLK/SCK5/
CTS8#/RTS8#/SS8#/
SSLA0
P13
PC2
A18
MTIOC4B/TCLKA/PO21
ET_RX_DV/RXD5/
SMISO5/SSCL5/SSLA3/
IERXD
P14
P75
CS5#
PO20
ET_ERXD0/RMII_RXD0/
SCK11
P15
Interrupt
RXD2/SMISO2/SSCL2/
SSLB3
IRQ13
VCC
R1
P21
MTIOC1B/TIOCA3/
TMCI0/PO1
RXD0/SMISO0/SSCL0/
SCL1/USB0_EXICEN/
PIXD5
IRQ9
R2
P20
MTIOC1A/TIOCB3/
TMRI0/PO0
TXD0/SMOSI0/SSDA0/
SDA1/USB0_ID/PIXD4
IRQ8
R3
P16
MTIOC3C/MTIOC3D/
TIOCB1/TCLKC/TMO2/
PO14/RTCOUT
TXD1/RXD3/SMOSI1/
SMISO3/SSDA1/SSCL3/
MOSIA/SCL2-DS/IERXD/
USB0_VBUS/
USB0_VBUSEN/
USB0_OVRCURB
IRQ6
R4
P85
R5
P11
MTIC5V/TMCI3
SCK2
IRQ1
R6
USB0_DM
R7
USB0_DP
R8
ADTRG0#
USB1_DM
R9
P84
R10
VSS
R11
VCC
R12
P80
EDREQ0
MTIOC3B/PO26
ET_TX_EN/
RMII_TXD_EN/SCK10
R13
P76
CS6#
PO22
ET_RX_CLK/REF50CK/
RXD11/SMISO11/SSCL11
R14
P74
CS4#
PO19
ET_ERXD1/RMII_RXD1/
CTS11#/RTS11#/SS11#
R15
PC1
A17
MTIOC3A/TCLKD/PO18
ET_ERXD2/SCK5/SSLA2/
SDA3
IRQ12
Note 1. 176-pin LFBGA does not have E5 pin
Note 2. The BCLK function is multiplexed with the I/O port function for pin P53, so the port function is not available if the external bus is
enabled.
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 39 of 208
RX63N Group, RX631 Group
1. Overview
Note 3. Enabled only for the ROM capacity: 2 Mbytes/1.5 Mbytes
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 40 of 208
RX63N Group, RX631 Group
Table 1.6
1. Overview
List of Pin and Pin Functions (176-Pin LQFP) (1/5)
Pin Number
176-Pin
LQFP
1
Power Supply
Clock System
Control
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB, and PDC)
Interrupt
S12AD,
AD, DA
P05
IRQ13
DA1
P03
IRQ11
DA0
I/O Port
VREFH
4
5
Timer
AVSS0
2
3
Bus
EXDMAC
SDRAMC
VREFL
6
P02
TMCI1
SCK6
IRQ10
AN020
7
P01
TMCI0
RXD6/SMISO6/SSCL6
IRQ9
AN019
8
P00
TMRI0
TXD6/SMOSI6/SSDA6
IRQ8
AN018
9
10
PF5
11
12
PJ5
VSS
13
14
IRQ4
EMLE
PJ3
MTIOC3C
CTS6#/RTS6#/CTS0#/
RTS0#/SS6#/SS0#
VCL
15
VBATT
16
NC
17
TRST#
18
MD/FINED
19
XCIN
20
XCOUT
21
RES#
22
XTAL
23
VSS
24
EXTAL
25
VCC
PF4
P37
P36
26
P35
27
P34
MTIOC0A/TMCI3/PO12/
POE2#
SCK6/SCK0/
USB0_DPRPD
IRQ4
28
P33
MTIOC0D/TIOCD0/
TMRI3/PO11/POE3#
RXD6/RXD0/SMISO6/
SMISO0/SSCL6/SSCL0/
CRX0/PCKO
IRQ3-DS
29
P32
MTIOC0C/TIOCC0/TMO3/
PO10/RTCOUT/RTCIC2
TXD6/TXD0/SMOSI6/
SMOSI0/SSDA6/SSDA0/
CTX0/USB0_VBUSEN/
VSYNC
IRQ2-DS
30
TMS
PF3
31
TDI
PF2
NMI
RXD1/SMISO1/SSCL1
32
P31
MTIOC4D/TMCI2/PO9/
RTCIC1
CTS1#/RTS1#/SS1#/
SSLB0/USB0_DPUPE
IRQ1-DS
33
P30
MTIOC4B/TMRI3/PO8/
RTCIC0/POE8#
RXD1/SMISO1/SSCL1/
MISOB/USB0_DRPD
IRQ0-DS
34
TCK/FINEC
35
TDO
PF1
SCK1
PF0
TXD1/SMOSI1/SSDA1
36
P27
CS7#
MTIOC2B/TMCI3/PO7
SCK1/RSPCKB
37
P26
CS6#
MTIOC2A/TMO1/PO6
TXD1/CTS3#/RTS3#
SMOSI1/SS3#/SSDA1/
MOSIB
38
P25
CS5#/EDACK1
MTIOC4C/MTCLKB/
TIOCA4/PO5
RXD3/SMISO3/SSCL3/
USB0_DPRPD/HSYNC
P24
CS4#/EDREQ1
MTIOC4A/MTCLKA/
TIOCB4/TMRI1/PO4
SCK3/USB0_VBUSEN/
PIXCLK
39
40
ADTRG0#
VCC
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 41 of 208
RX63N Group, RX631 Group
Table 1.6
1. Overview
List of Pin and Pin Functions (176-Pin LQFP) (2/5)
Pin Number
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB, and PDC)
I/O Port
Bus
EXDMAC
SDRAMC
42
P23
EDACK0
MTIOC3D/MTCLKD/
TIOCD3/PO3
TXD3/CTS0#/RTS0#/
SMOSI3/SS0#/SSDA3/
USB0_DPUPE/PIXD7
43
P22
EDREQ0
MTIOC3B/MTCLKC/
TIOCC3/TMO0/PO2
SCK0/USB0_DRPD/
PIXD6
44
P21
MTIOC1B/TIOCA3/
TMCI0/PO1
RXD0/SMISO0/SSCL0/
SCL1/USB0_EXICEN/
PIXD5
IRQ9
45
P20
MTIOC1A/TIOCB3/
TMRI0/PO0
TXD0/SMOSI0/SSDA0/
SDA1/USB0_ID/PIXD4
IRQ8
46
P17
MTIOC3A/MTIOC3B/
TIOCB0/TCLKD/TMO1/
PO15/POE8#
SCK1/TXD3/SMOSI3/
SSDA3/MISOA/SDA2-DS/
IETXD/USB1_VBUS/
PIXD3
IRQ7
ADTRG#
47
P87
TIOCA2
PIXD2
48
P16
MTIOC3C/MTIOC3D/
TIOCB1/TCLKC/TMO2/
PO14/RTCOUT
TXD1/RXD3/SMOSI1/
SMISO3/SSDA1/SSCL3/
MOSIA/SCL2-DS/IERXD/
USB0_VBUS/
USB0_VBUSEN/
USB0_OVRCURB
IRQ6
ADTRG0#
49
P86
TIOCA0
PIXD1
50
P15
MTIOC0B/MTCLKB/
TIOCB2/TCLKB/TMCI2/
PO13
RXD1/SCK3/SMISO1/
SSCL1/CRX1-DS/
USB1_DPUPE/PIXD0
IRQ5
51
P14
MTIOC3A/MTCLKA/
TIOCB5/TCLKA/TMRI2/
PO15
CTS1#/RTS1#/SS1#/
CTX1/USB0_DPUPE/
USB0_OVRCURA
IRQ4
176-Pin
LQFP
41
Power Supply
Clock System
Control
Interrupt
VSS
52
P85
53
P13
MTIOC0B/TIOCA5/TMO3/
PO13
TXD2/SMOSI2/SSDA2/
SDA0[FM+]
IRQ3
54
P12
MTIC5U/TMCI1
RXD2/SMISO2/SSCL2/
SCL0[FM+]
IRQ2
55
P11
MTIC5V/TMCI3
SCK2
IRQ1
56
P10
MTIC5W/TMRI3
57
IRQ0
USB0_DM
59
USB0_DP
VSS_USB
61
P57
WAIT#/WR3#/
BC3#/EDREQ1
62
P56
WR2#/BC2#/
EDACK1
MTIOC3C/TIOCA1
63
USB1_DM
64
65
ADTRG#
VCC_USB
58
60
S12AD,
AD, DA
USB1_DP
VCC_USB
66
P55
WAIT#/
EDREQ0
MTIOC4D/TMO3
ET_EXOUT/CRX1
67
P54
ALE/EDACK0
MTIOC4B/TMCI1
ET_LINKSTA/CTS2#/
RTS2#/SS2#/CTX1
68
P53*1
BCLK
69
P84
70
P52
RD#
RXD2/SMISO2/SSCL2/
SSLB3
71
P51
WR1#/BC1#/
WAIT#
SCK2/SSLB2
R01DS0098EJ0180 Rev.1.80
May 13, 2014
IRQ10
Page 42 of 208
RX63N Group, RX631 Group
Table 1.6
1. Overview
List of Pin and Pin Functions (176-Pin LQFP) (3/5)
Pin Number
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB, and PDC)
I/O Port
Bus
EXDMAC
SDRAMC
P50
WR0#/WR#
P83
EDACK1
MTIOC4C
ET_CRS/RMII_CRS_DV/
CTS10#/RTS10#/SS10#
76
PC7
A23/CS0#
MTIOC3A/MTCLKB/
TIOCB6/TMO2/PO31
ET_COL/TXD8/SMOSI8/
SSDA8/MISOA
IRQ14
77
PC6
A22/CS1#
MTIOC3C/MTCLKA/
TIOCA6/TMCI2/PO30
ET_ETXD3/RXD8/
SMISO8/SSCL8/MOSIA
IRQ13
78
PC5
A21/CS2#/
WAIT#
MTIOC3B/MTCLKD/
TIOCD6/TCLKF/TMRI2/
PO29
ET_ETXD2/SCK8/
RSPCKA
79
P82
EDREQ1
MTIOC4A/PO28
ET_ETXD1/RMII_TXD1/
TXD10/SMOSI10/SSDA10
80
P81
EDACK0
MTIOC3D/PO27
ET_ETXD0/RMII_TXD0/
RXD10/SMISO10/SSCL10
81
P80
EDREQ0
MTIOC3B/PO26
ET_TX_EN/
RMII_TXD_EN/SCK10
82
PC4
A20/CS3#
MTIOC3D/MTCLKC/
TIOCC6/TCLKE/TMCI1/
PO25/POE0#
ET_TX_CLK/SCK5/
CTS8#/RTS8#/SS8#/
SSLA0
83
PC3
A19
MTIOC4D/TCLKB/PO24
ET_TX_ER/TXD5/
SMOSI5/SSDA5/IETXD
84
P77
CS7#
PO23
ET_RX_ER/RMII_RX_ER/
TXD11/SMOSI11/SSDA11
85
P76
CS6#
PO22
ET_RX_CLK/REF50CK/
RXD11/SMISO11/SSCL11
86
PC2
A18
MTIOC4B/TCLKA/PO21
ET_RX_DV/RXD5/
SMISO5/SSCL5/SSLA3/
IERXD
87
P75
CS5#
PO20
ET_ERXD0/RMII_RXD0/
SCK11
88
P74
CS4#
PO19
ET_ERXD1/RMII_RXD1/
CTS11#/RTS11#/SS11#
89
PC1
A17
MTIOC3A/TCLKD/PO18
ET_ERXD2/SCK5/SSLA2/
SDA3
IRQ12
PC0
A16
MTIOC3C/TCLKC/PO17
ET_ERXD3/CTS5#/
RTS5#/SS5#/SSLA1/
SCL3
IRQ14
93
P73
CS3#
PO16
ET_WOL
94
PB7
A15
MTIOC3B/TIOCB5/PO31
ET_CRS/RMII_CRS_DV/
TXD9/SMOSI9/SSDA9
95
PB6
A14
MTIOC3D/TIOCA5/PO30
ET_ETXD1/RMII_TXD1/
RXD9/SMISO9/SSCL9
96
PB5
A13
MTIOC2A/MTIOC1B/
TIOCB4/TMRI1/PO29/
POE1#
ET_ETXD0/RMII_TXD0/
SCK9
97
PB4
A12
TIOCA4/PO28
ET_TX_EN/
RMII_TXD_EN/CTS9#/
RTS9#/SS9#
98
PB3
A11
MTIOC0A/MTIOC4A/
TIOCD3/TCLKD/TMO0/
PO27/POE3#
ET_RX_ER/RMII_RX_ER/
SCK4/SCK6
99
PB2
A10
TIOCC3/TCLKC/PO26
ET_RX_CLK/REF50CK/
CTS4#/RTS4#/CTS6#/
RTS6#/SS4#/SS6#
176-Pin
LQFP
Power Supply
Clock System
Control
72
73
90
TXD2/SMOSI2/SSDA2/
SSLB1
VCC
VCC
91
92
S12AD,
AD, DA
VSS
74
75
Interrupt
VSS
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 43 of 208
RX63N Group, RX631 Group
Table 1.6
1. Overview
List of Pin and Pin Functions (176-Pin LQFP) (4/5)
Pin Number
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB, and PDC)
I/O Port
Bus
EXDMAC
SDRAMC
100
PB1
A9
101
P72
CS2#
ET_MDC
P71
CS1#
ET_MDIO
PB0
A8
176-Pin
LQFP
Power Supply
Clock System
Control
102
103
ET_ERXD0/RMII_RXD0/
TXD4/TXD6/SMOSI4/
SMOSI6/SSDA4/SSDA6
MTIC5W/TIOCA3/PO24
ET_ERXD1/RMII_RXD1/
RXD4/RXD6/SMISO4/
SMISO6/SSCL4/SSCL6/
RSPCKA
IRQ4-DS
IRQ12
VSS
106
PA7
A7
TIOCB2/PO23
ET_WOL/MISOA
107
PA6
A6
MTIC5V/MTCLKB/
TIOCA2/TMCI3/PO22/
POE2#
ET_EXOUT/CTS5#/
RTS5#/SS5#/MOSIA
108
PA5
A5
TIOCB1/PO21
ET_LINKSTA/RSPCKA
109
PA4
A4
MTIC5U/MTCLKA/
TIOCA1/TMRI0/PO20
ET_MDC/TXD5/SMOSI5/
SSDA5/SSLA0
IRQ5-DS
110
PA3
A3
MTIOC0D/MTCLKD/
TIOCD0/TCLKB/PO19
ET_MDIO/RXD5/SMISO5/
SSCL5
IRQ6-DS
PO18
RXD5/SMISO5/SSCL5/
SSLA3
MTIOC0B/MTCLKC/
TIOCB0/PO17
ET_WOL/SCK5/SSLA2
MTIOC4A/TIOCA0/PO16
ET_TX_EN/
RMII_TXD_EN/SSLA1
111
TRDATA3
112
113
TRDATA2
114
115
VCC
116
TRCLK
117
VSS
118
119
TRSYNC
120
121
TRDATA1
122
123
S12AD,
AD, DA
VCC
104
105
MTIOC0C/MTIOC4C/
TIOCB3/TMCI0/PO25
Interrupt
TRDATA0
PG7
D31
PA2
A2
PG6
D30
PA1
A1/DQM3
PG5
D29
PA0
A0/BC0#/DQM2
PG4
D28
P67
CS7#/DQM1
PG3
D27
P66
CS6#/DQM0
CRX2*2
IRQ11
IRQ15
CTX2*2
PG2
D26
124
P65
CS5#/CKE
125
PE7
D15[A15/D15]
TIOCB11
MISOB
IRQ7
AN5
126
PE6
D14[A14/D14]
TIOCA11
MOSIB
IRQ6
AN4
IRQ5
AN3
127
VCC
128
SDCLK
129
VSS
P70
130
PE5
D13[A13/D13]
MTIOC4C/MTIOC2B/
TIOCB10
ET_RX_CLK/REF50CK/
RSPCKB
131
PE4
D12[A12/D12]
MTIOC4D/MTIOC1A/
TIOCA10/PO28
ET_ERXD2/SSLB0
AN2
132
PE3
D11[A11/D11]
MTIOC4B/TIOCB9/PO26/
POE8#
ET_ERXD3/CTS12#/
RTS12#/SS12#/MISOB
AN1
133
PE2
D10[A10/D10]
MTIOC4A/TIOCA9/PO23
RXD12/SMISO12/
SSCL12/RXDX12/SSLB3/
MOSIB
134
PE1
D9[A9/D9]
MTIOC4C/TIOCD9/PO18
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/SSLB2/RSPCKB
ANEX1
135
PE0
D8[A8/D8]
TIOCC9
SCK12/SSLB1
ANEX0
R01DS0098EJ0180 Rev.1.80
May 13, 2014
IRQ7-DS
AN0
Page 44 of 208
RX63N Group, RX631 Group
Table 1.6
1. Overview
List of Pin and Pin Functions (176-Pin LQFP) (5/5)
Pin Number
Timer
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB, and PDC)
Interrupt
S12AD,
AD, DA
MTIC5U/POE0#
SSLC3
IRQ7
AN7
MTIC5V/POE1#
SSLC2
IRQ6
AN6
I/O Port
Bus
EXDMAC
SDRAMC
136
P64
CS4#/WE#
137
P63
CS3#/CAS#
138
P62
CS2#/RAS#
139
P61
CS1#/SDCS#
P60
CS0#
PD7
D7[A7/D7]
144
PG1
D25
145
PD6
D6[A6/D6]
146
PG0
D24
147
PD5
D5[A5/D5]
MTIC5W/POE2#
SSLC1
IRQ5
AN013
148
PD4
D4[A4/D4]
POE3#
SSLC0
IRQ4
AN012
149
P97
A23/D23
PD3
D3[A3/D3]
TIOCB8/TCLKH/POE8#
RSPCKC
IRQ3
AN011
P96
A22/D22
154
PD2
D2[A2/D2]
MTIOC4D/TIOCA8
MISOC/CRX0
IRQ2
AN010
155
P95
A21/D21
156
PD1
D1[A1/D1]
MTIOC4B/TIOCB7/
TCLKG
MOSIC/CTX0
IRQ1
AN009
157
P94
A20/D20
158
PD0
D0[A0/D0]
159
P93
A19/D19
CTS7#/RTS7#/SS7#
AN017
160
P92
A18/D18
RXD7/SMISO7/SSCL7
AN016
P91
A17/D17
SCK7
AN015
P90
A16/D16
TXD7/SMOSI7/SSDA7
AN014
176-Pin
LQFP
140
Power Supply
Clock System
Control
VSS
141
142
VCC
143
150
151
VSS
152
153
VCC
161
162
IRQ0
AN008
VSS
163
164
TIOCA7
VCC
165
P47
IRQ15-DS
AN007
166
P46
IRQ14-DS
AN006
167
P45
IRQ13-DS
AN005
168
P44
IRQ12-DS
AN004
169
P43
IRQ11-DS
AN003
170
P42
IRQ10-DS
AN002
171
P41
IRQ9-DS
AN001
P40
IRQ8-DS
AN000
P07
IRQ15
ADTRG0#
172
VREFL0
173
174
VREFH0
175
AVCC0
176
Note 1. The BCLK function is multiplexed with the I/O port function for pin P53, so the port function is not available if the external bus is
enabled.
Note 2. Enabled only for the ROM capacity: 2 Mbytes/1.5 Mbytes
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 45 of 208
RX63N Group, RX631 Group
Table 1.7
1. Overview
List of Pins and Pin Functions (145-Pin TFLGA) (1/5)
Pin No.
145-pin
TFLGA
A1
Power Supply
Clock
System Control
I/O Port
Bus
EXDMAC
SDRAMC
Timers
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB, and PDC)
Interrupt
S12AD
AD
DA
AVSS0
A2
P07
IRQ15
ADTRG0#
A3
P40
IRQ8-DS
AN000
A4
P42
IRQ10-DS
AN002
A5
P45
IRQ13-DS
AN005
A6
P90
A16
TXD7/SMOSI7/SSDA7
AN014
A7
P92
A18
RXD7/SMISO7/SSCL7
AN016
A8
PD2
D2[A2/D2]
MTIOC4D/TIOCA8
MISOC/CRX0
IRQ2
AN010
A9
PD6
D6[A6/D6]
MTIC5V/POE1#
SSLC2
IRQ6
AN6
A11
P62
CS2#/RAS#
A12
PE1
D9[A9/D9]
MTIOC4C/TIOCD9/
PO18
TXD12/SMOSI12/SSDA12/
TXDX12/SIOX12/SSLB2/
RSPCKB
ANEX1
A13
PE3
D11[A11/D11]
MTIOC4B/TIOCB9/
PO26/POE8#
CTS12#/RTS12#/SS12#/
MISOB/ET_ERXD3
AN1
A10
VSS
B1
VREFH
B2
AVCC0
B3
P05
IRQ13
DA1
B5
P43
IRQ11-DS
AN003
B6
P47
IRQ15-DS
AN007
B7
P91
A17
B8
PD0
D0[A0/D0]
TIOCA7
B9
PD4
D4[A4/D4]
POE3#
B11
P61
CS1#/SDCS#
B12
PE2
D10[A10/D10]
B13
PE4
D12[A12/D12]
B4
B10
C1
VREFL0
AN015
IRQ0
AN008
SSLC0
IRQ4
AN012
MTIOC4A/TIOCA9/
PO23
RXD12/SMISO12/SSCL12/
RXDX12/SSLB3/MOSIB
IRQ7-DS
AN0
MTIOC4D/MTIOC1A/
TIOCA10/PO28
SSLB0/ET_ERXD2
TMCI1
SCK6
VCC
AN2
VREFL
C2
C3
SCK7
P02
IRQ10
AN020
VREFH0
C4
P41
IRQ9-DS
AN001
C5
P46
IRQ14-DS
AN006
C6
VSS
C7
PD1
D1[A1/D1]
MTIOC4B/TIOCB7/
TCLKG
MOSIC/CTX0
IRQ1
AN009
C8
PD3
D3[A3/D3]
TIOCB8/TCLKH/POE8#
RSPCKC
IRQ3
AN011
MTIC5U/POE0#
SSLC3
IRQ7
AN7
TIOCC9
SCK12/SSLB1
TMRI0
TXD6/SMOSI6/SSDA6
C9
PD7
D7[A7/D7]
C10
P63
CS3#/CAS#
C11
PE0
D8[A8/D8]
C12
SDCLK
C13
VSS
ANEX0
P70
D1
P00
D2
PF5
IRQ4
D3
P03
IRQ11
DA0
D4
P01
IRQ9
AN019
R01DS0098EJ0180 Rev.1.80
May 13, 2014
TMCI0
RXD6/SMISO6/SSCL6
IRQ8
AN018
Page 46 of 208
RX63N Group, RX631 Group
Table 1.7
1. Overview
List of Pins and Pin Functions (145-Pin TFLGA) (2/5)
Pin No.
Power Supply
Clock
System Control
I/O Port
Bus
EXDMAC
SDRAMC
D6
P93
A19
D7
PD5
D5[A5/D5]
D8
P60
CS0#
D9
P64
CS4#/WE#
D10
PE7
D12
D13
145-pin
TFLGA
D5
D11
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB, and PDC)
VSS
VCL
E3
Interrupt
CTS7#/RTS7#/SS7#
AN017
MTIC5W/POE2#
SSLC1
IRQ5
AN013
D15[A15/D15]
TIOCB11
MISOB
IRQ7
AN5
PE5
D13[A13/D13]
MTIOC4C/MTIOC2B/
TIOCB10
RSPCKB/ET_RX_CLK/
REF50CK
IRQ5
AN3
PE6
D14[A14/D14]
TIOCA11
MOSIB
IRQ6
AN4
IRQ12-DS
AN004
PJ5
EMLE
E5
P44
E10
PA0
A0/BC0#
E11
P66
CS6#/DQM0
E12
P65
CS5#/CKE
E13
P67
CS7#/DQM1
F1
XCIN
F2
XCOUT
F3
PJ3
MTIOC4A/TIOCA0/
PO16
SSLA1/ET_TX_EN/
RMII_TXD_EN
CTX2*2
CRX2*2
MTIOC3C
CTS6#/RTS6#/CTS0#/
RTS0#/SS6#/SS0#
IRQ15
VBATT
F10
PA3
A3
MTIOC0D/MTCLKD/
TIOCD0/TCLKB/PO19
RXD5/SMISO5/SSCL5/
ET_MDIO
IRQ6-DS
F12
PA1
A1
MTIOC0B/MTCLKC/
TIOCB0/PO17
SCK5/SSLA2/ET_WOL
IRQ11
F13
PA2
A2
PO18
RXD5/SMISO5/SSCL5/
SSLA3
F11
VSS
G1
XTAL
G2
RES#
G3
MD/FINED
G4
BSCANP
P37
G10
PA5
A5
TIOCB1/PO21
RSPCKA/ET_LINKSTA
G11
PA6
A6
MTIC5V/MTCLKB/
TIOCA2/TMCI3/PO22/
POE2#
CTS5#/RTS5#/SS5#
MOSIA/ET_EXOUT
PA4
A4
MTIC5U/MTCLKA/
TIOCA1/TMRI0/PO20
TXD5/SMOSI5/SSDA5/
SSLA0/ET_MDC
G12
S12AD
AD
DA
VCC
E2
F4
Communications
VCC
E1
E4
Timers
VCC
G13
H1
EXTAL
H2
VCC
H3
VSS
IRQ5-DS
P36
H4
P35
H10
P72
CS2#
ET_MDC
H11
P71
CS1#
ET_MDIO
R01DS0098EJ0180 Rev.1.80
May 13, 2014
NMI
Page 47 of 208
RX63N Group, RX631 Group
Table 1.7
1. Overview
List of Pins and Pin Functions (145-Pin TFLGA) (3/5)
Pin No.
Power Supply
Clock
System Control
Timers
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB, and PDC)
I/O Port
Bus
EXDMAC
SDRAMC
H12
PB0
A8
MTIC5W/TIOCA3/PO24
RXD4/RXD6/SMISO4/
SMISO6/SSCL4/SSCL6/
RSPCKA/T_ERXD1/
RMII_RXD1
H13
PA7
A7
TIOCB2/PO23
MISOA/ET_WOL
P34
MTIOC0A/TMCI3/PO12/
POE2#
SCK6/SCK0/
USB0_DPRPD
IRQ4
J2
P33
MTIOC0D/TIOCD0/
TMRI3/PO11/POE3#
RXD6/RXD0/SMISO6/
SMISO0/SSCL6/SSCL0/
CRX0/PCKO
IRQ3-DS
J3
P32
MTIOC0C/TIOCC0/
TMO3/PO10/RTCOUT/
RTCIC2
TXD6/TXD0/SMOSI6/
SMOSI0/SSDA6/SSDA0/
CTX0/USB0_VBUSEN/
VSYNC
IRQ2-DS
P30
MTIOC4B/TMRI3/PO8/
RTCIC0/POE8#
RXD1/SMISO1/SSCL1/
MISOB/USB0_DRPD
IRQ0-DS
145-pin
TFLGA
J1
J4
TRST#
TDI
J10
PB3
A11
MTIOC0A/MTIOC4A/
TIOCD3/TCLKD/TMO0/
PO27/POE3#
SCK4/SCK6/ET_RX_ER/
RMII_RX_ER
J11
PB4
A12
TIOCA4/PO28
CTS9#/RTS9#/SS9#/
ET_TX_EN/RMII_TXD_EN
J12
PB2
A10
TIOCC3/TCLKC/PO26
CTS4#/RTS4#/CTS6#/
RTS6#/SS4#/SS6#/
ET_RX_CLK/REF50CK
J13
PB1
A9
MTIOC0C/MTIOC4C/
TIOCB3/TMCI0/PO25
TXD4/TXD6/SMOSI4/
SMOSI6/SSDA4/SSDA6/
ET_ERXD0/RMII_RXD0
Interrupt
IRQ12
IRQ4-DS
K1
TCK/FINEC
P27
CS7#
MTIOC2B/TMCI3/PO7
SCK1/RSPCKB
K2
TDO
P26
CS6#
MTIOC2A/TMO1/PO6
TXD1/CTS3#/RTS3#/
SMOSI1/SS3#/SSDA1/
MOSIB
K3
TMS
P31
MTIOC4D/TMCI2/PO9/
RTCIC1
CTS1#/RTS1#/SS1#/
SSLB0/USB0_DPUPE
IRQ1-DS
P15
MTIOC0B/MTCLKB/
TIOCB2/TCLKB/TMCI2/
PO13
RXD1/SCK3/SMISO1/
SSCL1/CRX1-DS/PIXD0
IRQ5
MTIOC4B/TMCI1
CTS2#/RTS2#/SS2#/
CTX1/ET_LINKSTA
K4
K5
TRDATA2
P54
ALE/EDACK0
K6
P53*1
BCLK
K7
P51
WR1#/BC1#/
WAIT#
P80
EDREQ0
MTIOC3B/PO26
SCK10/ET_TX_EN/
RMII_TXD_EN
K10
P76
CS6#
PO22
RXD11/SMISO11/SSCL11/
ET_RX_CLK/REF50CK
K11
PB7
A15
MTIOC3B/TIOCB5/
PO31
TXD9/SMOSI9/SSDA9/
ET_CRS/RMII_CRS_DV
K12
PB6
A14
MTIOC3D/TIOCA5/
PO30
RXD9/SMISO9/SSCL9/
ET_ETXD1/RMII_TXD1
K13
PB5
A13
MTIOC2A/MTIOC1B/
TIOCB4/TMRI1/PO29/
POE1#
SCK9/ET_ETXD0/
RMII_TXD0
L1
P25
CS5#/EDACK1
MTIOC4C/MTCLKB/
TIOCA4/PO5
RXD3/SMISO3/SSCL3/
USB0_DPRPD/HSYNC
L2
P23
EDACK0
MTIOC3D/MTCLKD/
TIOCD3/PO3
TXD3/CTS0#/RTS0#/
SMOSI3/SS0#/SSDA3/
USB0_DPUPE/PIXD7
K8
VCC
K9
TRDATA0
R01DS0098EJ0180 Rev.1.80
May 13, 2014
S12AD
AD
DA
SCK2/SSLB2
ADTRG0#
Page 48 of 208
RX63N Group, RX631 Group
Table 1.7
1. Overview
List of Pins and Pin Functions (145-Pin TFLGA) (4/5)
Pin No.
145-pin
TFLGA
Power Supply
Clock
System Control
I/O Port
Bus
EXDMAC
SDRAMC
Timers
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB, and PDC)
L3
P16
L4
P24
L5
P13
L6
P56
EDACK1
L7
P52
RD#
P83
EDACK1
MTIOC4C
CTS10#/RTS10#/SS10#/
ET_CRS/RMII_CRS_DV
L9
PC5
A21/CS2#/
WAIT#
MTIOC3B/MTCLKD/
TIOCD6/TCLKF/TMRI2/
PO29
SCK8/RSPCKA/
ET_ETXD2
L10
PC4
A20/CS3#
MTIOC3D/MTCLKC/
TIOCC6/TCLKE/TMCI1/
PO25/POE0#
SCK5/CTS8#/RTS8#/
SS8#/SSLA0/ET_TX_CLK
L11
PC2
A18
MTIOC4B/TCLKA/PO21
RXD5/SMISO5/SSCL5/
SSLA3/IERXD/ET_RX_DV
P73
CS3#
PO16
ET_WOL
M1
P22
EDREQ0
MTIOC3B/MTCLKC/
TIOCC3/TMO0/PO2
SCK0/USB0_DRPD/PIXD6
M2
P17
MTIOC3A/MTIOC3B/
TIOCB0/TCLKD/TMO1/
PO15/POE8#
SCK1/TXD3/SMOSI3/
SSDA3/MISOA/SDA2-DS/
IETXD/PIXD3
M3
P86
TIOCA0
PIXD1
M4
P12
TMCI1
RXD2/SMISO2/SSCL2/
SCL0[FM+]
L8
TRCLK
L12
L13
CS4#/EDREQ1
MTIOC3C/MTIOC3D/
TIOCB1/TCLKC/TMO2/
PO14/RTCOUT
TXD1/RXD3/SMOSI1/
SMISO3/SSDA1/SSCL3/
MOSIA/SCL2-DS/IERXD/
USB0_VBUS/
USB0_VBUSEN/
USB0_OVRCURB
MTIOC4A/MTCLKA/
TIOCB4/TMRI1/PO4
SCK3/USB0_VBUSEN/
PIXCLK
MTIOC0B/TIOCA5/
TMO3/PO13
TXD2/SMOSI2/SSDA2/
SDA0[FM+]
Interrupt
S12AD
AD
DA
IRQ6
ADTRG0#
IRQ3
ADTRG#
IRQ7
ADTRG#
MTIOC3C/TIOCA1
RXD2/SMISO2/SSCL2/
SSLB3
VSS
M5
VCC_USB
M6
VSS_USB
IRQ2
M7
P50
WR0#/WR#
M8
PC6
A22/CS1#
MTIOC3C/MTCLKA/
TIOCA6/TMCI2/PO30
RXD8/SMISO8/SSCL8/
MOSIA/ET_ETXD3
P81
EDACK0
MTIOC3D/PO27
RXD10/SMISO10/SSCL10/
ET_ETXD0/RMII_TXD0
M10
P77
CS7#
PO23
TXD11/SMOSI11/SSDA11/
ET_RX_ER/RMII_RX_ER
M11
PC0
A16
MTIOC3C/TCLKC/PO17
CTS5#/RTS5#/SS5#/
SSLA1/SCL3/ET_ERXD3
IRQ14
M12
PC1
A17
MTIOC3A/TCLKD/PO18
SCK5/SSLA2/SDA3/
ET_ERXD2
IRQ12
M9
M13
TRDATA1
TXD2/SMOSI2/SSDA2/
SSLB1
IRQ13
VCC
N1
P21
MTIOC1B/TIOCA3/
TMCI0/PO1
RXD0/SMISO0/SSCL0/
SCL1/USB0_EXICEN/
PIXD5
IRQ9
N2
P20
MTIOC1A/TIOCB3/
TMRI0/PO0
TXD0/SMOSI0/SSDA0/
SDA1/USB0_ID/PIXD4
IRQ8
N3
P87
TIOCA2
PIXD2
N4
P14
MTIOC3A/MTCLKA/
TIOCB5/TCLKA/TMRI2/
PO15
CTS1#/RTS1#/SS1#/
CTX1/USB0_DPUPE/
USB0_OVRCURA
N5
USB0_DM
N6
USB0_DP
R01DS0098EJ0180 Rev.1.80
May 13, 2014
IRQ4
Page 49 of 208
RX63N Group, RX631 Group
Table 1.7
1. Overview
List of Pins and Pin Functions (145-Pin TFLGA) (5/5)
Pin No.
Timers
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB, and PDC)
Interrupt
Power Supply
Clock
System Control
I/O Port
N7
TRDATA3
P55
WAIT#/
EDREQ0
MTIOC4D/TMO3
CRX1/ET_EXOUT
IRQ10
N8
VSS
PC7
A23/CS0#
MTIOC3A/MTCLKB/
TIOCB6/TMO2/PO31
TXD8/SMOSI8/SSDA8/
MISOA/ET_COL
IRQ14
P82
EDREQ1
MTIOC4A/PO28
TXD10/SMOSI10/SSDA10/
ET_ETXD1/RMII_TXD1
N11
PC3
A19
MTIOC4D/TCLKB/PO24
TXD5/SMOSI5/SSDA5/
IETXD/ET_TX_ER
N12
P75
CS5#
PO20
SCK11/ET_ERXD0/
RMII_RXD0
N13
P74
CS4#
PO19
CTS11#/RTS11#/SS11#/
ET_ERXD1/RMII_RXD1
145-pin
TFLGA
N9
N10
TRSYNC
Bus
EXDMAC
SDRAMC
S12AD
AD
DA
Note 1. The BCLK function is multiplexed with the I/O port function for pin P53, so the port function is not available if the external bus is
enabled.
Note 2. Enabled only for the ROM capacity: 2 Mbytes/1.5 Mbytes
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 50 of 208
RX63N Group, RX631 Group
Table 1.8
1. Overview
List of Pins and Pin Functions (144-Pin LQFP) (1/5)
Pin No.
144-pin
LQFP
1
Power Supply
Clock
System Control
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB, and PDC)
Interrupt
S12AD
AD
DA
P05
IRQ13
DA1
P03
IRQ11
DA0
I/O Port
VREFH
4
5
Communications
AVSS0
2
3
Bus
EXDMAC
SDRAMC
Timers
VREFL
6
P02
TMCI1
SCK6
IRQ10
AN020
7
P01
TMCI0
RXD6/SMISO6/SSCL6
IRQ9
AN019
8
P00
TMRI0
TXD6/SMOSI6/SSDA6
IRQ8
AN018
9
PF5
10
EMLE
11
12
PJ5
VSS
13
14
PJ3
MTIOC3C
CTS6#/RTS6#/CTS0#/
RTS0#/SS6#/SS0#
VCL
15
VBATT
16
MD/FINED
17
XCIN
18
XCOUT
19
RES#
20
XTAL
21
VSS
22
EXTAL
23
VCC
24
25
IRQ4
P37
P36
P35
TRST#
NMI
P34
MTIOC0A/TMCI3/
PO12/POE2#
SCK6/SCK0/
USB0_DPRPD
IRQ4
26
P33
MTIOC0D/TIOCD0/
TMRI3/PO11/POE3#
RXD6/RXD0/SMISO6/
SMISO0/SSCL6/
SSCL0/CRX0/PCKO
IRQ3-DS
27
P32
MTIOC0C/TIOCC0/
TMO3/PO10/RTCOUT/
RTCIC2
TXD6/TXD0/SMOSI6/
SMOSI0/SSDA6/
SSDA0/CTX0/
USB0_VBUSEN/
VSYNC
IRQ2-DS
28
TMS
P31
MTIOC4D/TMCI2/PO9/
RTCIC1
CTS1#/RTS1#/SS1#/
SSLB0/USB0_DPUPE
IRQ1-DS
29
TDI
P30
MTIOC4B/TMRI3/PO8/
RTCIC0/POE8#
RXD1/SMISO1/SSCL1/
MISOB/USB0_DRPD
IRQ0-DS
30
TCK/FINEC
P27
CS7#
MTIOC2B/TMCI3/PO7
SCK1/RSPCKB
31
TDO
P26
CS6#
MTIOC2A/TMO1/PO6
TXD1/CTS3#/RTS3#/
SMOSI1/SS3#/SSDA1/
MOSIB
32
P25
CS5#/EDACK1
MTIOC4C/MTCLKB/
TIOCA4/PO5
RXD3/SMISO3/SSCL3/
USB0_DPRPD/HSYNC
33
P24
CS4#/EDREQ1
MTIOC4A/MTCLKA/
TIOCB4/TMRI1/PO4
SCK3/USB0_VBUSEN/
PIXCLK
34
P23
EDACK0
MTIOC3D/MTCLKD/
TIOCD3/PO3
TXD3/CTS0#/RTS0#/
SMOSI3/SS0#/SSDA3/
USB0_DPUPE/PIXD7
35
P22
EDREQ0
MTIOC3B/MTCLKC/
TIOCC3/TMO0/PO2
SCK0/USB0_DRPD/
PIXD6
R01DS0098EJ0180 Rev.1.80
May 13, 2014
ADTRG0#
Page 51 of 208
RX63N Group, RX631 Group
Table 1.8
1. Overview
List of Pins and Pin Functions (144-Pin LQFP) (2/5)
Pin No.
144-pin
LQFP
Power Supply
Clock
System Control
I/O Port
Bus
EXDMAC
SDRAMC
Timers
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB, and PDC)
Interrupt
S12AD
AD
DA
36
P21
MTIOC1B/TIOCA3/
TMCI0/PO1
RXD0/SMISO0/SSCL0/
SCL1/USB0_EXICEN/
PIXD5
IRQ9
37
P20
MTIOC1A/TIOCB3/
TMRI0/PO0
TXD0/SMOSI0/SSDA0/
SDA1/USB0_ID/PIXD4
IRQ8
38
P17
MTIOC3A/MTIOC3B/
TIOCB0/TCLKD/TMO1/
PO15/POE8#
SCK1/TXD3/SMOSI3/
SSDA3/MISOA/SDA2DS/IETXD/PIXD3
IRQ7
ADTRG#
39
P87
TIOCA2
PIXD2
40
P16
MTIOC3C/MTIOC3D/
TIOCB1/TCLKC/TMO2/
PO14/RTCOUT
TXD1/RXD3/SMOSI1/
SMISO3/SSDA1/
SSCL3/MOSIA/SCL2DS/IERXD/
USB0_VBUS/
USB0_VBUSEN/
USB0_OVRCURB
IRQ6
ADTRG0#
41
P86
TIOCA0
PIXD1
42
P15
MTIOC0B/MTCLKB/
TIOCB2/TCLKB/
TMCI2/PO13
RXD1/SCK3/SMISO1/
SSCL1/CRX1-DS/
PIXD0
IRQ5
43
P14
MTIOC3A/MTCLKA/
TIOCB5/TCLKA/
TMRI2/PO15
CTS1#/RTS1#/SS1#/
CTX1/USB0_DPUPE/
USB0_OVRCURA
IRQ4
44
P13
MTIOC0B/TIOCA5/
TMO3/PO13
TXD2/SMOSI2/SSDA2/
SDA0[FM+]
IRQ3
45
P12
TMCI1
RXD2/SMISO2/SSCL2/
SCL0[FM+]
IRQ2
46
VCC_USB
47
USB0_DM
48
49
USB0_DP
VSS_USB
50
P56
EDACK1
MTIOC3C/TIOCA1
51
TRDATA3
P55
WAIT#/
EDREQ0
MTIOC4D/TMO3
CRX1/ET_EXOUT
52
TRDATA2
P54
ALE/EDACK0
MTIOC4B/TMCI1
CTS2#/RTS2#/SS2#/
CTX1/ET_LINKSTA
IRQ10
53
P53*1
BCLK
54
P52
RD#
RXD2/SMISO2/SSCL2/
SSLB3
55
P51
WR1#/BC1#/
WAIT#
SCK2/SSLB2
56
P50
WR0#/WR#
TXD2/SMOSI2/SSDA2/
SSLB1
P83
EDACK1
MTIOC4C
CTS10#/RTS10#/
SS10#/ET_CRS/
RMII_CRS_DV
60
PC7
A23/CS0#
MTIOC3A/MTCLKB/
TIOCB6/TMO2/PO31
TXD8/SMOSI8/SSDA8/
MISOA/ET_COL
IRQ14
61
PC6
A22/CS1#
MTIOC3C/MTCLKA/
TIOCA6/TMCI2/PO30
RXD8/SMISO8/SSCL8/
MOSIA/ET_ETXD3
IRQ13
62
PC5
A21/CS2#/
WAIT#
MTIOC3B/MTCLKD/
TIOCD6/TCLKF/
TMRI2/PO29
SCK8/RSPCKA/
ET_ETXD2
P82
EDREQ1
MTIOC4A/PO28
TXD10/SMOSI10/
SSDA10/ET_ETXD1/
RMII_TXD1
57
VSS
58
TRCLK
59
VCC
63
ADTRG#
TRSYNC
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 52 of 208
RX63N Group, RX631 Group
Table 1.8
1. Overview
List of Pins and Pin Functions (144-Pin LQFP) (3/5)
Pin No.
Timers
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB, and PDC)
Power Supply
Clock
System Control
I/O Port
Bus
EXDMAC
SDRAMC
64
TRDATA1
P81
EDACK0
MTIOC3D/PO27
RXD10/SMISO10/
SSCL10/ET_ETXD0/
RMII_TXD0
65
TRDATA0
P80
EDREQ0
MTIOC3B/PO26
SCK10/ET_TX_EN/
RMII_TXD_EN
66
PC4
A20/CS3#
MTIOC3D/MTCLKC/
TIOCC6/TCLKE/
TMCI1/PO25/POE0#
SCK5/CTS8#/RTS8#/
SS8#/SSLA0/
ET_TX_CLK
67
PC3
A19
MTIOC4D/TCLKB/
PO24
TXD5/SMOSI5/SSDA5/
IETXD/ET_TX_ER
68
P77
CS7#
PO23
TXD11/SMOSI11/
SSDA11/ET_RX_ER/
RMII_RX_ER
69
P76
CS6#
PO22
RXD11/SMISO11/
SSCL11/ET_RX_CLK/
REF50CK
70
PC2
A18
MTIOC4B/TCLKA/
PO21
RXD5/SMISO5/SSCL5/
SSLA3/IERXD/
ET_RX_DV
71
P75
CS5#
PO20
SCK11/ET_ERXD0/
RMII_RXD0
72
P74
CS4#
PO19
CTS11#/RTS11#/
SS11#/ET_ERXD1/
RMII_RXD1
73
PC1
A17
MTIOC3A/TCLKD/
PO18
SCK5/SSLA2/SDA3/
ET_ERXD2
IRQ12
PC0
A16
MTIOC3C/TCLKC/
PO17
CTS5#/RTS5#/SS5#/
SSLA1/SCL3/
ET_ERXD3
IRQ14
77
P73
CS3#
PO16
ET_WOL
78
PB7
A15
MTIOC3B/TIOCB5/
PO31
TXD9/SMOSI9/SSDA9/
ET_CRS/
RMII_CRS_DV
79
PB6
A14
MTIOC3D/TIOCA5/
PO30
RXD9/SMISO9/SSCL9/
ET_ETXD1/RMII_TXD1
80
PB5
A13
MTIOC2A/MTIOC1B/
TIOCB4/TMRI1/PO29/
POE1#
SCK9/ET_ETXD0/
RMII_TXD0
81
PB4
A12
TIOCA4/PO28
CTS9#/RTS9#/SS9#/
ET_TX_EN/
RMII_TXD_EN
82
PB3
A11
MTIOC0A/MTIOC4A/
TIOCD3/TCLKD/TMO0/
PO27/POE3#
SCK4/SCK6/
ET_RX_ER/
RMII_RX_ER
83
PB2
A10
TIOCC3/TCLKC/PO26
CTS4#/RTS4#/CTS6#/
RTS6#/SS4#/SS6#/
ET_RX_CLK/REF50CK
84
PB1
A9
MTIOC0C/MTIOC4C/
TIOCB3/TMCI0/PO25
TXD4/TXD6/SMOSI4/
SMOSI6/SSDA4/
SSDA6/ET_ERXD0/
RMII_RXD0
85
P72
CS2#
144-pin
LQFP
74
VCC
75
76
Interrupt
S12AD
AD
DA
VSS
ET_MDC
86
P71
CS1#
87
PB0
A8
MTIC5W/TIOCA3/
PO24
RXD4/RXD6/SMISO4/
SMISO6/SSCL4/
SSCL6/RSPCKA/
T_ERXD1/RMII_RXD1
88
PA7
A7
TIOCB2/PO23
MISOA/ET_WOL
R01DS0098EJ0180 Rev.1.80
May 13, 2014
IRQ4-DS
ET_MDIO
IRQ12
Page 53 of 208
RX63N Group, RX631 Group
Table 1.8
1. Overview
List of Pins and Pin Functions (144-Pin LQFP) (4/5)
Pin No.
Power Supply
Clock
System Control
Timers
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB, and PDC)
I/O Port
Bus
EXDMAC
SDRAMC
89
PA6
A6
MTIC5V/MTCLKB/
TIOCA2/TMCI3/PO22/
POE2#
CTS5#/RTS5#/SS5#
MOSIA/ET_EXOUT
90
PA5
A5
TIOCB1/PO21
RSPCKA/ET_LINKSTA
PA4
A4
MTIC5U/MTCLKA/
TIOCA1/TMRI0/PO20
TXD5/SMOSI5/SSDA5/
SSLA0/ET_MDC
IRQ5-DS
94
PA3
A3
MTIOC0D/MTCLKD/
TIOCD0/TCLKB/PO19
RXD5/SMISO5/SSCL5/
ET_MDIO
IRQ6-DS
95
PA2
A2
PO18
RXD5/SMISO5/SSCL5/
SSLA3
96
PA1
A1
MTIOC0B/MTCLKC/
TIOCB0/PO17
SCK5/SSLA2/ET_WOL
97
PA0
A0/BC0#
MTIOC4A/TIOCA0/
PO16
SSLA1/ET_TX_EN/
RMII_TXD_EN
98
P67
CS7#/DQM1
CRX2*2
99
P66
CS6#/DQM0
CTX2*2
100
P65
CS5#/CKE
101
PE7
D15[A15/D15]
TIOCB11
MISOB
IRQ7
AN5
102
PE6
D14[A14/D14]
TIOCA11
MOSIB
IRQ6
AN4
IRQ5
AN3
144-pin
LQFP
91
VCC
92
93
Interrupt
S12AD
AD
DA
VSS
103
VCC
104
SDCLK
105
VSS
IRQ11
IRQ15
P70
106
PE5
D13[A13/D13]
MTIOC4C/MTIOC2B/
TIOCB10
RSPCKB/ET_RX_CLK/
REF50CK
107
PE4
D12[A12/D12]
MTIOC4D/MTIOC1A/
TIOCA10/PO28
SSLB0/ET_ERXD2
AN2
108
PE3
D11[A11/D11]
MTIOC4B/TIOCB9/
PO26/POE8#
CTS12#/RTS12#/
SS12#/MISOB/
ET_ERXD3
AN1
109
PE2
D10[A10/D10]
MTIOC4A/TIOCA9/
PO23
RXD12/SMISO12/
SSCL12/RXDX12/
SSLB3/MOSIB
110
PE1
D9[A9/D9]
MTIOC4C/TIOCD9/
PO18
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/SSLB2/
RSPCKB
ANEX1
TIOCC9
SCK12/SSLB1
ANEX0
111
PE0
D8[A8/D8]
112
P64
CS4#/WE#
113
P63
CS3#/CAS#
114
P62
CS2#/RAS#
115
P61
CS1#/SDCS#
P60
CS0#
116
AN0
VSS
117
118
IRQ7-DS
VCC
119
PD7
D7[A7/D7]
MTIC5U/POE0#
SSLC3
IRQ7
AN7
120
PD6
D6[A6/D6]
MTIC5V/POE1#
SSLC2
IRQ6
AN6
121
PD5
D5[A5/D5]
MTIC5W/POE2#
SSLC1
IRQ5
AN013
122
PD4
D4[A4/D4]
POE3#
SSLC0
IRQ4
AN012
123
PD3
D3[A3/D3]
TIOCB8/TCLKH/
POE8#
RSPCKC
IRQ3
AN011
124
PD2
D2[A2/D2]
MTIOC4D/TIOCA8
MISOC/CRX0
IRQ2
AN010
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 54 of 208
RX63N Group, RX631 Group
Table 1.8
1. Overview
List of Pins and Pin Functions (144-Pin LQFP) (5/5)
Pin No.
Power Supply
Clock
System Control
Timers
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB, and PDC)
Interrupt
S12AD
AD
DA
MOSIC/CTX0
IRQ1
AN009
IRQ0
AN008
I/O Port
Bus
EXDMAC
SDRAMC
125
PD1
D1[A1/D1]
MTIOC4B/TIOCB7/
TCLKG
126
PD0
D0[A0/D0]
TIOCA7
127
P93
A19
CTS7#/RTS7#/SS7#
AN017
128
P92
A18
RXD7/SMISO7/SSCL7
AN016
P91
A17
SCK7
AN015
P90
A16
TXD7/SMOSI7/SSDA7
AN014
144-pin
LQFP
129
130
VSS
131
132
VCC
133
P47
IRQ15-DS
AN007
134
P46
IRQ14-DS
AN006
135
P45
IRQ13-DS
AN005
136
P44
IRQ12-DS
AN004
137
P43
IRQ11-DS
AN003
138
P42
IRQ10-DS
AN002
P41
IRQ9-DS
AN001
P40
IRQ8-DS
AN000
P07
IRQ15
ADTRG0#
139
140
VREFL0
141
142
VREFH0
143
AVCC0
144
Note 1. The BCLK function is multiplexed with the I/O port function for pin P53, so the port function is not available if the external bus is
enabled.
Note 2. Enabled only for the ROM capacity: 2 Mbytes/1.5 Mbytes
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 55 of 208
RX63N Group, RX631 Group
Table 1.9
Pin No.
100-pin
TFLGA
List of Pins and Pin Functions (100-Pin TFLGA) (1/5)
Power Supply
Clock
System
Control
A1
A2
I/O Port
Bus
EXDMAC
Timers
Communications
(MTU, TPU,
TMR, PPG,
RTC, POE)
(ETHERC, SCIc,
SCId, RSPI, RIIC,
CAN, IEB, USB)
Interrupt
S12AD
AD
DA
P05
IRQ13
DA1
P07
IRQ15
ADTRG0#
IRQ11-DS
AN003
IRQ0
AN008
IRQ4
AN012
VREFH
A3
A4
1. Overview
VREFL0
A5
P43
A6
PD0
D0[A0/D0]
A7
PD4
D4[A4/D4]
A8
PE0
D8[A8/D8]
SCK12/SSLB1
ANEX0
A9
PE1
D9[A9/D9]
MTIOC4C/
PO18
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/SSLB2/
RSPCKB
ANEX1
A10
PE2
D10[A10/D10]
MTIOC4A/
PO23
RXD12/SMISO12/
SSCL12/RXDX12/
SSLB3/MOSIB
B1
POE3#
AVSS0
B3
AVCC0
B4
P40
B5
P44
B6
PD1
D1[A1/D1]
MTIOC4B
B7
PD3
D3[A3/D3]
B8
PD6
B9
B10
C1
VCL
C2
VREFL
C3
IRQ8-DS
AN000
IRQ12-DS
AN004
IRQ1
AN009
POE8#
IRQ3
AN011
D6[A6/D6]
MTIC5V/
POE1#
IRQ6
AN6
PD7
D7[A7/D7]
MTIC5U/
POE0#
IRQ7
AN7
PE3
D11[A11/D11]
MTIOC4B/
PO26/POE8#
CTS12#/RTS12#/
SS12#/MISOB/
ET_ERXD3
MTIOC3C
CTS6#/RTS6#/
CTS0#/RTS0#/
SS6#/SS0#
PJ3
CTX0*1
AN1
VREFH0
C5
P42
C6
P47
C7
PD2
D2[A2/D2]
MTIOC4D
C8
PD5
D5[A5/D5]
MTIC5W/
POE2#
C9
PE5
D13[A13/D13]
MTIOC4C/
MTIOC2B
RSPCKB/
ET_RX_CLK/
REF50CK
C10
PE4
D12[A12/D12]
MTIOC4D/
MTIOC1A/
PO28
SSLB0/ET_ERXD2
D1
AN0
EMLE
B2
C4
IRQ7-DS
CRX0*1
IRQ10-DS
AN002
IRQ15-DS
AN007
IRQ2
AN010
IRQ5
AN013
IRQ5
AN3
AN2
XCIN
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 56 of 208
RX63N Group, RX631 Group
Table 1.9
Pin No.
100-pin
TFLGA
1. Overview
List of Pins and Pin Functions (100-Pin TFLGA) (2/5)
Power Supply
Clock
System
Control
D2
XCOUT
D3
MD/FINED
D4
VBATT
I/O Port
Bus
EXDMAC
Timers
Communications
(MTU, TPU,
TMR, PPG,
RTC, POE)
(ETHERC, SCIc,
SCId, RSPI, RIIC,
CAN, IEB, USB)
Interrupt
S12AD
AD
DA
D5
P45
IRQ13-DS
AN005
D6
P46
IRQ14-DS
AN006
D7
PE6
MOSIB
IRQ6
AN4
AN5
D14[A14/D14]
D8
PE7
D15[A15/D15]
MISOB
IRQ7
D9
PA1
A1
MTIOC0B/
MTCLKC/
TIOCB0/PO17
SCK5/SSLA2/
ET_WOL
IRQ11
D10
PA0
A0/BC0#
MTIOC4A/
TIOCA0/PO16
SSLA1/ET_TX_EN/
RMII_TXD_EN
MTIOC0A/
TMCI3/PO12/
POE2#
SCK6/SCK0/
USB0_DPRPD
E1
XTAL
E2
VSS
E3
RES#
E4
TRST#
P37
P34
E5
P41
E6
PA2
A2
PO18
RXD5/SMISO5/
SSCL5/SSLA3
E7
PA6
A6
MTIC5V/
MTCLKB/
TIOCA2/
TMCI3/PO22/
POE2#
CTS5#/RTS5#/
SS5#/MOSIA/
ET_EXOUT
E8
PA4
A4
MTIC5U/
MTCLKA/
TIOCA1/
TMRI0/PO20
TXD5/SMOSI5/
SSDA5/SSLA0/
ET_MDC
E9
PA5
A5
TIOCB1/PO21
RSPCKA/
ET_LINKSTA
E10
PA3
A3
MTIOC0D/
MTCLKD/
TIOCD0/
TCLKB/PO19
RXD5/SMISO5/
SSCL5/ET_MDIO
F1
EXTAL
F2
VCC
IRQ4
IRQ9-DS
AN001
IRQ5-DS
IRQ6-DS
P36
F3
P35
F4
P32
MTIOC0C/
TIOCC0/TMO3/
PO10/
RTCOUT/
RTCIC2
TXD6/TXD0/
SMOSI6/SMOSI0/
SSDA6/SSDA0/
CTX0*1/
USB0_VBUSEN
IRQ2-DS
F5
P12
TMCI1
RXD2/SMISO2/
SSCL2/SCL0[FM+]
IRQ2
F6
PB3
MTIOC0A/
MTIOC4A/
TIOCD3/
TCLKD/TMO0/
PO27/POE3#
SCK6/ET_RX_ER/
RMII_RX_ER
R01DS0098EJ0180 Rev.1.80
May 13, 2014
NMI
A11
Page 57 of 208
RX63N Group, RX631 Group
Table 1.9
Pin No.
100-pin
TFLGA
1. Overview
List of Pins and Pin Functions (100-Pin TFLGA) (3/5)
Power Supply
Clock
System
Control
I/O Port
Bus
EXDMAC
Timers
Communications
(MTU, TPU,
TMR, PPG,
RTC, POE)
(ETHERC, SCIc,
SCId, RSPI, RIIC,
CAN, IEB, USB)
Interrupt
F7
PB2
A10
TIOCC3/
TCLKC/PO26
CTS6#/RTS6#/
SS6#/ET_RX_CLK/
REF50CK
F8
PB0
A8
MTIC5W/
TIOCA3/PO24
RXD6/SMISO6/
SSCL6/RSPCKA/
ET_ERXD1/
RMII_RXD1
F9
PA7
A7
TIOCB2/PO23
MISOA/ET_WOL
P33
MTIOC0D/
TIOCD0/
TMRI3/PO11/
POE3#
RXD6/RXD0/
SMISO6/SMISO0/
SSCL6/SSCL0/
CRX0*1
IRQ3-DS
F10
S12AD
AD
DA
IRQ12
VSS
G1
G2
TMS
P31
MTIOC4D/
TMCI2/PO9/
RTCIC1
CTS1#/RTS1#/
SS1#/SSLB0/
USB0_DPUPE
IRQ1-DS
G3
TDI
P30
MTIOC4B/
TMRI3/PO8/
RTCIC0/POE8#
RXD1/SMISO1/
SSCL1/MISOB/
USB0_DRPD
IRQ0-DS
G4
TCK/FINEC
P27
MTIOC2B/
TMCI3/PO7
SCK1/RSPCKB
G5
BCLK
P53*2
CS7#
G6
P52
RD#
G7
PB5
A13
MTIOC2A/
MTIOC1B/
TIOCB4/
TMRI1/PO29/
POE1#
SCK9/ET_ETXD0/
RMII_TXD0
G8
PB4
A12
TIOCA4/PO28
CTS9#/RTS9#/
SS9#/ET_TX_EN/
RMII_TXD_EN
G9
PB1
A9
MTIOC0C/
MTIOC4C/
TIOCB3/
TMCI0/PO25
TXD6/SMOSI6/
SSDA6/ET_ERXD0/
RMII_RXD0
P26
CS6#
MTIOC2A/
TMO1/PO6
TXD1/CTS3#/
RTS3#/SMOSI1/
SS3#/SSDA1/
MOSIB
H2
P25
CS5#/
EDACK1
MTIOC4C/
MTCLKB/
TIOCA4/PO5
RXD3/SMISO3/
SSCL3/
USB0_DPRPD
H3
P16
MTIOC3C/
MTIOC3D/
TIOCB1/
TCLKC/TMO2/
PO14/RTCOUT
TXD1/RXD3/
SMOSI1/SMISO3/
SSDA1/SSCL3/
MOSIA/SCL2-DS/
IERXD/
USB0_VBUS/
USB0_VBUSEN/
USB0_OVRCURB
G10
VCC
H1
TDO
R01DS0098EJ0180 Rev.1.80
May 13, 2014
RXD2/SMISO2/
SSCL2/SSLB3
IRQ4-DS
ADTRG0#
IRQ6
ADTRG0#
Page 58 of 208
RX63N Group, RX631 Group
Table 1.9
Pin No.
100-pin
TFLGA
1. Overview
List of Pins and Pin Functions (100-Pin TFLGA) (4/5)
Power Supply
Clock
System
Control
I/O Port
H4
P15
H5
P55
H6
Bus
EXDMAC
Timers
Communications
(MTU, TPU,
TMR, PPG,
RTC, POE)
(ETHERC, SCIc,
SCId, RSPI, RIIC,
CAN, IEB, USB)
Interrupt
S12AD
AD
DA
MTIOC0B/
MTCLKB/
TIOCB2/
TCLKB/TMCI2/
PO13
RXD1/SCK3/
SMISO1/SSCL1/
CRX1-DS
IRQ5
WAIT#/
EDREQ0
MTIOC4D/
TMO3
CRX1/ET_EXOUT
IRQ10
P54
ALE/EDACK0
MTIOC4B/
TMCI1
CTS2#/RTS2#/
SS2#/CTX1/
ET_LINKSTA
H7
PC7
A23/CS0#
MTIOC3A/
MTCLKB/
TMO2/PO31
TXD8/SMOSI8/
SSDA8/MISOA/
ET_COL
IRQ14
H8
PC6
A22/CS1#
MTIOC3C/
MTCLKA/
TMCI2/PO30
RXD8/SMISO8/
SSCL8/MOSIA/
ET_ETXD3
IRQ13
H9
PB6
A14
MTIOC3D/
TIOCA5/PO30
RXD9/SMISO9/
SSCL9/ET_ETXD1/
RMII_TXD1
H10
PB7
A15
MTIOC3B/
TIOCB5/PO31
TXD9/SMOSI9/
SSDA9/ET_CRS/
RMII_CRS_DV
J1
P24
CS4#/
EDREQ1
MTIOC4A/
MTCLKA/
TIOCB4/
TMRI1/PO4
SCK3/
USB0_VBUSEN
J2
P21
MTIOC1B/
TIOCA3/
TMCI0/PO1
RXD0/SMISO0/
SSCL0/
USB0_EXICEN
IRQ9
J3
P17
MTIOC3A/
MTIOC3B/
TIOCB0/
TCLKD/TMO1/
PO15/POE8#
SCK1/TXD3/
SMOSI3/SSDA3/
MISOA/SDA2-DS/
IETXD
IRQ7
ADTRG#
J4
P13
MTIOC0B/
TIOCA5/TMO3/
PO13
TXD2/SMOSI2/
SSDA2/SDA0[FM+]
IRQ3
ADTRG#
J5
VSS_USB
J6
VCC_USB
J7
P50
WR0#/WR#
J8
PC4
A20/CS3#
MTIOC3D/
MTCLKC/
TMCI1/PO25/
POE0#
SCK5/CTS8#/
RTS8#/SS8#/
SSLA0/ET_TX_CLK
J9
PC0
A16
MTIOC3C/
TCLKC/PO17
CTS5#/RTS5#/
SS5#/SSLA1/
ET_ERXD3
IRQ14
J10
PC1
A17
MTIOC3A/
TCLKD/PO18
SCK5/SSLA2/
ET_ERXD2
IRQ12
K1
P23
EDACK0
MTIOC3D/
MTCLKD/
TIOCD3/PO3
TXD3/CTS0#/
RTS0#/SMOSI3/
SS0#/SSDA3/
USB0_DPUPE
R01DS0098EJ0180 Rev.1.80
May 13, 2014
TXD2/SMOSI2/
SSDA2/SSLB1
Page 59 of 208
RX63N Group, RX631 Group
Table 1.9
Pin No.
100-pin
TFLGA
1. Overview
List of Pins and Pin Functions (100-Pin TFLGA) (5/5)
Power Supply
Clock
System
Control
I/O Port
Bus
EXDMAC
EDREQ0
Timers
Communications
(MTU, TPU,
TMR, PPG,
RTC, POE)
(ETHERC, SCIc,
SCId, RSPI, RIIC,
CAN, IEB, USB)
MTIOC3B/
MTCLKC/
TIOCC3/TMO0/
PO2
SCK0/USB0_DRPD
Interrupt
K2
P22
K3
P20
MTIOC1A/
TIOCB3/
TMRI0/PO0
TXD0/SMOSI0/
SSDA0/USB0_ID
IRQ8
K4
P14
MTIOC3A/
MTCLKA/
TIOCB5/
TCLKA/TMRI2/
PO15
CTS1#/RTS1#/
SS1#/CTX1/
USB0_DPUPE/
USB0_OVRCURA
IRQ4
K5
S12AD
AD
DA
USB0_DM
K6
USB0_DP
K7
P51
WR1#/BC1#/
WAIT#
SCK2/SSLB2
K8
PC5
A21/CS2#/
WAIT#
MTIOC3B/
MTCLKD/
TMRI2/PO29
SCK8/RSPCKA/
ET_ETXD2
K9
PC3
A19
MTIOC4D/
TCLKB/PO24
TXD5/SMOSI5/
SSDA5/IETXD/
ET_TX_ER
K10
PC2
A18
MTIOC4B/
TCLKA/PO21
RXD5/SMISO5/
SSCL5/SSLA3/
IERXD/ET_RX_DV
Note 1. Enabled only for the ROM capacity of 768 Kbytes or more.
Note 2. The BCLK function is multiplexed with the I/O port function for pin P53, so the port function is not available if the external bus is
enabled.
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 60 of 208
RX63N Group, RX631 Group
Table 1.10
1. Overview
List of Pins and Pin Functions (100-Pin LQFP) (1/4)
Pin No.
100-pin
LQFP
Power Supply
Clock
System Control
1
VREFH
2
EMLE
3
VREFL
4
I/O Port
Bus
EXDMAC
PJ3
Timers
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB)
Interrupt
MTIOC3C
CTS6#/RTS6#/CTS0#/
RTS0#/SS6#/SS0#
P34
MTIOC0A/TMCI3/
PO12/POE2#
SCK6/SCK0/
USB0_DPRPD
IRQ4
17
P33
MTIOC0D/TIOCD0/
TMRI3/PO11/POE3#
RXD6/RXD0/SMISO6/
SMISO0/SSCL6/
SSCL0/CRX0*1
IRQ3-DS
18
P32
MTIOC0C/TIOCC0/
TMO3/PO10/RTCOUT/
RTCIC2
TXD6/TXD0/SMOSI6/
SMOSI0/SSDA6/
SSDA0/CTX0*1/
USB0_VBUSEN
IRQ2-DS
5
VCL
6
VBATT
7
MD/FINED
8
XCIN
9
XCOUT
10
RES#
11
XTAL
12
VSS
13
EXTAL
14
VCC
15
16
P37
P36
P35
TRST#
S12AD
AD
DA
NMI
19
TMS
P31
MTIOC4D/TMCI2/PO9/
RTCIC1
CTS1#/RTS1#/SS1#/
SSLB0/USB0_DPUPE
IRQ1-DS
20
TDI
P30
MTIOC4B/TMRI3/PO8/
RTCIC0/POE8#
RXD1/SMISO1/SSCL1/
MISOB/USB0_DRPD
IRQ0-DS
21
TCK/FINEC
P27
CS7#
MTIOC2B/TMCI3/PO7
SCK1/RSPCKB
22
TDO
P26
CS6#
MTIOC2A/TMO1/PO6
TXD1/CTS3#/RTS3#/
SMOSI1/SS3#/SSDA1/
MOSIB
23
P25
CS5#/EDACK1
MTIOC4C/MTCLKB/
TIOCA4/PO5
RXD3/SMISO3/SSCL3/
USB0_DPRPD
24
P24
CS4#/EDREQ1
MTIOC4A/MTCLKA/
TIOCB4/TMRI1/PO4
SCK3/USB0_VBUSEN
25
P23
EDACK0
MTIOC3D/MTCLKD/
TIOCD3/PO3
TXD3/CTS0#/RTS0#/
SMOSI3/SS0#/SSDA3/
USB0_DPUPE
26
P22
EDREQ0
MTIOC3B/MTCLKC/
TIOCC3/TMO0/PO2
SCK0/USB0_DRPD
27
P21
MTIOC1B/TIOCA3/
TMCI0/PO1
RXD0/SMISO0/SSCL0/
USB0_EXICEN
IRQ9
28
P20
MTIOC1A/TIOCB3/
TMRI0/PO0
TXD0/SMOSI0/SSDA0/
USB0_ID
IRQ8
29
P17
MTIOC3A/MTIOC3B/
TIOCB0/TCLKD/TMO1/
PO15/POE8#
SCK1/TXD3/SMOSI3/
SSDA3/MISOA/SDA2DS/IETXD
IRQ7
ADTRG#
30
P16
MTIOC3C/MTIOC3D/
TIOCB1/TCLKC/TMO2/
PO14/RTCOUT
TXD1/RXD3/SMOSI1/
SMISO3/SSDA1/
SSCL3/MOSIA/SCL2DS/IERXD/
USB0_VBUS/
USB0_VBUSEN/
USB0_OVRCURB
IRQ6
ADTRG0#
R01DS0098EJ0180 Rev.1.80
May 13, 2014
ADTRG0#
Page 61 of 208
RX63N Group, RX631 Group
Table 1.10
1. Overview
List of Pins and Pin Functions (100-Pin LQFP) (2/4)
Pin No.
100-pin
LQFP
Power Supply
Clock
System Control
I/O Port
Bus
EXDMAC
Timers
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB)
Interrupt
31
P15
MTIOC0B/MTCLKB/
TIOCB2/TCLKB/TMCI2/
PO13
RXD1/SCK3/SMISO1/
SSCL1/CRX1-DS
IRQ5
32
P14
MTIOC3A/MTCLKA/
TIOCB5/TCLKA/TMRI2/
PO15
CTS1#/RTS1#/SS1#/
CTX1/USB0_DPUPE/
USB0_OVRCURA
IRQ4
33
P13
MTIOC0B/TIOCA5/
TMO3/PO13
TXD2/SMOSI2/SSDA2/
SDA0[FM+]
IRQ3
34
P12
TMCI1
RXD2/SMISO2/SSCL2/
SCL0[FM+]
IRQ2
35
ADTRG#
VCC_USB
36
USB0_DM
37
USB0_DP
38
S12AD
AD
DA
VSS_USB
39
P55
WAIT#/
EDREQ0
MTIOC4D/TMO3
CRX1/ET_EXOUT
40
P54
ALE/EDACK0
MTIOC4B/TMCI1
CTS2#/RTS2#/SS2#/
CTX1/ET_LINKSTA
41
P53*2
BCLK
42
P52
RD#
RXD2/SMISO2/SSCL2/
SSLB3
43
P51
WR1#/BC1#/
WAIT#
SCK2/SSLB2
44
P50
WR0#/WR#
TXD2/SMOSI2/SSDA2/
SSLB1
45
PC7
A23/CS0#
MTIOC3A/MTCLKB/
TMO2/PO31
TXD8/SMOSI8/SSDA8/
MISOA/ET_COL
IRQ14
46
PC6
A22/CS1#
MTIOC3C/MTCLKA/
TMCI2/PO30
RXD8/SMISO8/SSCL8/
MOSIA/ET_ETXD3
IRQ13
47
PC5
A21/CS2#/
WAIT#
MTIOC3B/MTCLKD/
TMRI2/PO29
SCK8/RSPCKA/
ET_ETXD2
48
PC4
A20/CS3#
MTIOC3D/MTCLKC/
TMCI1/PO25/POE0#
SCK5/CTS8#/RTS8#/
SS8#/SSLA0/
ET_TX_CLK
49
PC3
A19
MTIOC4D/TCLKB/
PO24
TXD5/SMOSI5/SSDA5/
IETXD/ET_TX_ER
50
PC2
A18
MTIOC4B/TCLKA/PO21
RXD5/SMISO5/SSCL5/
SSLA3/IERXD/
ET_RX_DV
51
PC1
A17
MTIOC3A/TCLKD/
PO18
SCK5/SSLA2/
ET_ERXD2
IRQ12
52
PC0
A16
MTIOC3C/TCLKC/
PO17
CTS5#/RTS5#/SS5#/
SSLA1/ET_ERXD3
IRQ14
53
PB7
A15
MTIOC3B/TIOCB5/
PO31
TXD9/SMOSI9/SSDA9/
ET_CRS/
RMII_CRS_DV
54
PB6
A14
MTIOC3D/TIOCA5/
PO30
RXD9/SMISO9/SSCL9/
ET_ETXD1/RMII_TXD1
55
PB5
A13
MTIOC2A/MTIOC1B/
TIOCB4/TMRI1/PO29/
POE1#
SCK9/ET_ETXD0/
RMII_TXD0
56
PB4
A12
TIOCA4/PO28
CTS9#/RTS9#/SS9#/
ET_TX_EN/
RMII_TXD_EN
57
PB3
A11
MTIOC0A/MTIOC4A/
TIOCD3/TCLKD/TMO0/
PO27/POE3#
SCK6/ET_RX_ER/
RMII_RX_ER
58
PB2
A10
TIOCC3/TCLKC/PO26
CTS6#/RTS6#/SS6#/
ET_RX_CLK/REF50CK
R01DS0098EJ0180 Rev.1.80
May 13, 2014
IRQ10
Page 62 of 208
RX63N Group, RX631 Group
Table 1.10
1. Overview
List of Pins and Pin Functions (100-Pin LQFP) (3/4)
Pin No.
Timers
Communications
I/O Port
Bus
EXDMAC
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB)
PB1
A9
MTIOC0C/MTIOC4C/
TIOCB3/TMCI0/PO25
TXD6/SMOSI6/SSDA6/
ET_ERXD0/
RMII_RXD0
IRQ4-DS
PB0
A8
MTIC5W/TIOCA3/PO24
RXD6/SMISO6/SSCL6/
RSPCKA/ET_ERXD1/
RMII_RXD1
IRQ12
63
PA7
A7
TIOCB2/PO23
MISOA/ET_WOL
64
PA6
A6
MTIC5V/MTCLKB/
TIOCA2/TMCI3/PO22/
POE2#
CTS5#/RTS5#/SS5#/
MOSIA/ET_EXOUT
65
PA5
A5
TIOCB1/PO21
RSPCKA/ET_LINKSTA
66
PA4
A4
MTIC5U/MTCLKA/
TIOCA1/TMRI0/PO20
TXD5/SMOSI5/SSDA5/
SSLA0/ET_MDC
IRQ5-DS
67
PA3
A3
MTIOC0D/MTCLKD/
TIOCD0/TCLKB/PO19
RXD5/SMISO5/SSCL5/
ET_MDIO
IRQ6-DS
68
PA2
A2
PO18
RXD5/SMISO5/SSCL5/
SSLA3
69
PA1
A1
MTIOC0B/MTCLKC/
TIOCB0/PO17
SCK5/SSLA2/ET_WOL
70
PA0
A0/BC0#
MTIOC4A/TIOCA0/
PO16
SSLA1/ET_TX_EN/
RMII_TXD_EN
100-pin
LQFP
Power Supply
Clock
System Control
59
60
VCC
61
62
Interrupt
S12AD
AD
DA
VSS
IRQ11
71
PE7
D15[A15/D15]
MISOB
IRQ7
AN5
72
PE6
D14[A14/D14]
MOSIB
IRQ6
AN4
73
PE5
D13[A13/D13]
MTIOC4C/MTIOC2B
RSPCKB/ET_RX_CLK/
REF50CK
IRQ5
AN3
74
PE4
D12[A12/D12]
MTIOC4D/MTIOC1A/
PO28
SSLB0/ET_ERXD2
AN2
75
PE3
D11[A11/D11]
MTIOC4B/PO26/POE8#
CTS12#/RTS12#/
SS12#/MISOB/
ET_ERXD3
AN1
76
PE2
D10[A10/D10]
MTIOC4A/PO23
RXD12/SMISO12/
SSCL12/RXDX12/
SSLB3/MOSIB
77
PE1
D9[A9/D9]
MTIOC4C/PO18
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/SSLB2/
RSPCKB
78
PE0
D8[A8/D8]
79
PD7
D7[A7/D7]
MTIC5U/POE0#
IRQ7
AN7
80
PD6
D6[A6/D6]
MTIC5V/POE1#
IRQ6
AN6
IRQ7-DS
AN0
ANEX1
SCK12/SSLB1
ANEX0
81
PD5
D5[A5/D5]
MTIC5W/POE2#
IRQ5
AN013
82
PD4
D4[A4/D4]
POE3#
IRQ4
AN012
83
PD3
D3[A3/D3]
POE8#
IRQ3
AN011
84
PD2
D2[A2/D2]
MTIOC4D
CRX0*1
IRQ2
AN010
85
PD1
D1[A1/D1]
MTIOC4B
CTX0*1
IRQ1
AN009
D0[A0/D0]
86
PD0
IRQ0
AN008
87
P47
IRQ15-DS
AN007
88
P46
IRQ14-DS
AN006
89
P45
IRQ13-DS
AN005
90
P44
IRQ12-DS
AN004
91
P43
IRQ11-DS
AN003
92
P42
IRQ10-DS
AN002
93
P41
IRQ9-DS
AN001
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 63 of 208
RX63N Group, RX631 Group
Table 1.10
1. Overview
List of Pins and Pin Functions (100-Pin LQFP) (4/4)
Pin No.
100-pin
LQFP
94
Power Supply
Clock
System Control
96
VREFH0
97
AVCC0
98
100
Communications
(MTU, TPU, TMR, PPG,
RTC, POE)
(ETHERC, SCIc, SCId,
RSPI, RIIC, CAN, IEB,
USB)
Interrupt
S12AD
AD
DA
P40
IRQ8-DS
AN000
P07
IRQ15
ADTRG0#
P05
IRQ13
DA1
I/O Port
Bus
EXDMAC
VREFL0
95
99
Timers
AVSS0
Note 1. Enabled only for the ROM capacity of 768 Kbytes or more
Note 2. The BCLK function is multiplexed with the I/O port function for pin P53, so the port function is not available if the external bus is
enabled.
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 64 of 208
RX63N Group, RX631 Group
Table 1.11
Pin No.
64-pin
TFLGA
1. Overview
List of Pins and Pin Functions (64-Pin TFLGA) (1/2)
Power Supply
Clock System
Control
A1
I/O Port
Timers
Communications
(MTU2a, TPUa, TMR, PPG,
RTCa, POE2a)
(SCIc, SCId, RSPI, RIIC, CAN,
IEB, USB)
P05
A2
AVCC0
A3
VREFH0
A4
VREFL0
A5
VREFH
A6
VREFL
A7
PE2
MTIOC4A/PO23
RXD12/SMISO12/SSCL12/
RXDX12/SSLB3/MOSIB
A8
PE3
MTIOC4B/PO26/POE8#
CTS12#/RTS12#/SS12#/
MISOB
B1
VCL
B2
AVSS0
Interrupt
S12ADa, DAa
IRQ13
DA1
IRQ7-DS
AN010
AN011
B3
P40
IRQ8-DS
AN000
B4
P42
IRQ10-DS
AN002
B5
P44
IRQ12-DS
AN004
IRQ14-DS
AN006
B6
P46
B7
PE1
MTIOC4C/PO18
TXD12/SMOSI12/SSDA12/
TXDX12/SIOX12/SSLB2/
RSPCKB
AN009
B8
PE4
MTIOC4D/MTIOC1A/PO28
SSLB0
AN012
C1
XCIN
C2
MD/FINED
C3
EMLE
C4
P41
IRQ9-DS
AN001
C5
P43
IRQ11-DS
AN003
C6
PE0
C7
PE5
MTIOC4C/MTIOC2B
RSPCKB
C8
PA0
MTIOC4A/TIOCA0/PO16
SSLA1
P27
MTIOC2B/TMCI3
SCK1/RSPCKB
D4
P14
MTIOC3A/MTCLKA/
TIOCB5/TCLKA/TMRI2
CTS1#/RTS1#/SS1#/CTX1/
USB0_DPUPE/
USB0_OVRCURA
D5
PA6
MTIC5V/MTCLKB/TIOCA2/
TMCI3/PO22/POE2#
CTS5#/RTS5#/SS5#/
MOSIA
D6
PA4
MTIC5U/MTCLKA/TIOCA1/
TMRI0/PO20
TXD5/SMOSI5/SSDA5/
SSLA0
IRQ5-DS
D7
PA1
MTIOC0B/MTCLKC/
TIOCB0/PO17
SCK5/SSLA2/SCL2
IRQ11
D8
PA3
MTIOC0D/MTCLKD/
TIOCD0/TCLKB/PO19
RXD5/SMISO5/SSCL5/
SDA2
IRQ6-DS
P30
MTIOC4B/TMRI3/POE8#/
RTCIC0
RXD1/SMISO1/SSCL1/
MISOB/USB0_DRPD
IRQ0-DS
D1
XCOUT
D2
RES#
D3
TCK
FINEC
E1
VSS
E2
VBATT
E3
TDI
R01DS0098EJ0180 Rev.1.80
May 13, 2014
SCK12/SSLB1
AN008
IRQ5
AN013
IRQ4
Page 65 of 208
RX63N Group, RX631 Group
Table 1.11
Pin No.
List of Pins and Pin Functions (64-Pin TFLGA) (2/2)
Timers
Communications
(MTU2a, TPUa, TMR, PPG,
RTCa, POE2a)
(SCIc, SCId, RSPI, RIIC, CAN,
IEB, USB)
P16
MTIOC3C/MTIOC3D/
TIOCB1/TCLKC/TMO2/
RTCOUT
TXD1/SMOSI1/SSDA1/
MOSIA/SCL2-DS/IERXD/
USB0_VBUS/
USB0_VBUSEN/
USB0_OVRCURB
PC4
MTIOC3D/MTCLKC/TMCI1/
PO25/POE0#
SCK5/SSLA0/
USB0_DPRPD
PB0
MTIC5W/TIOCA3/PO24
RXD6/SMISO6/SSCL6/
RSPCKA
64-pin
TFLGA
Power Supply
Clock System
Control
I/O Port
E4
TMS
E5
E6
VCC
E7
VSS
E8
F1
1. Overview
Interrupt
S12ADa, DAa
IRQ6
ADTRG0#
IRQ12
VCC
F2
P35
NMI
F3
P31
MTIOC4D/TMCI2/RTCIC1
CTS1#/RTS1#/SS1#/
SSLB0/USB0_DPUPE
F4
PC5
MTIOC3B/MTCLKD/TMRI2/
PO29
RSPCKA/USB0_ID
F5
P15
MTIOC0B/MTCLKB/
TIOCB2/TCLKB/TMCI2
RXD1/SMISO1/SSCL1/
CRX1-DS/USB1_DPUPE
IRQ5
F6
PB1
MTIOC0C/MTIOC4C/
TIOCB3/TMCI0/PO25
TXD6/SMOSI6/SSDA6
IRQ4-DS
F7
PB5
MTIOC2A/MTIOC1B/
TIOCB4/TMRI1/PO29/
POE1#
SCK9
F8
PB3
MTIOC0A/MTIOC4A/
TIOCD3/TCLKD/TMO0/
PO27/POE3#
SCK6
G1
EXTAL
P36
G2
TDO
P26
MTIOC2A/TMO1
TXD1/SMOSI1/SSDA1/
MOSIB/USB0_VBUSEN
G3
VCC_USB
G4
VSS_USB
G5
VCC_USB
G6
PC6
MTIOC3C/MTCLKA/TMCI2/
PO30
MOSIA/USB0_EXICEN
G7
PC3
MTIOC4D/TCLKB/PO24
TXD5/SMOSI5/SSDA5/
SDA2/IETXD
PB6
MTIOC3D/TIOCA5/PO30
RXD9/SMISO9/SSCL9
MTIOC3A/MTIOC3B/
TIOCB0/TCLKD/TMO1/
POE8#
SCK1/MISOA/SDA2-DS/
IETXD/USB1_VBUS
G8
H1
XTAL
P37
H2
TRST#
P17
H3
USB0_DM
H4
USB0_DP
H5
USB1_DM
H6
IRQ1-DS
IRQ13
IRQ7
USB1_DP
H7
PC2
MTIOC4B/TCLKA/PO21
RXD5/SMISO5/SSCL5/
SSLA3/SCL2/IERXD
H8
PB7
MTIOC3B/TIOCB5/PO31
TXD9/SMOSI9/SSDA9
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 66 of 208
RX63N Group, RX631 Group
Table 1.12
Pin
Number
64-Pin
LQFP
List of Pins and Pin Functions (64-Pin LQFP) (1/3)
Power Supply
Clock
System Control
1
EMLE
2
VCL
3
MD/FINED
4
XCIN
5
XCOUT
6
RES#
7
XTAL
8
VSS
9
EXTAL
10
VCC
11
12
1. Overview
I/O Port
Timer
Timer
Communications
(MTU2a, TPUa, TMR, PPG,
RTCa, POE2a)
(SCIc, SCId, RSPI, RIIC, CAN,
IEB, USB)
Interrupt
P37
P36
P35
NMI
VBATT
13
P31
MTIOC4D/TMCI2/PO9/
RTCIC1
CTS1#/RTS1#/SS1#/
SSLB0/USB0_DPUPE
IRQ1-DS
IRQ0-DS
14
TDI
P30
MTIOC4B/TMRI3/PO8/
POE8#/RTCIC0
RXD1/SMISO1/SSCL1/
MISOB/USB0_DRPD
15
TCK/FINEC
P27
MTIOC2B/TMCI3/PO7
SCK1/RSPCKB
16
TDO
P26
MTIOC2A/TMO1/PO6
TXD1/SMOSI1/SSDA1/
MOSIB/USB0_VBUSEN
17
TRST#
P17
MTIOC3A/MTIOC3B/
TIOCB0/TCLKD/TMO1/
PO15/POE8#
SCK1/MISOA/
SDA2-DS/IETXD
IRQ7
18
TMS
P16
MTIOC3C/MTIOC3D/
TIOCB1/TCLKC/TMO2/
PO14/RTCOUT
TXD1/SMOSI1/SSDA1/
MOSIA/SCL2-DS/IERXD/
USB0_VBUS/
USB0_VBUSEN/
USB0_OVRCURB
IRQ6
19
P15
MTIOC0B/MTCLKB/
TIOCB2/TCLKB/TMCI2/
PO13
RXD1/SMISO1/SSCL1/
CRX1-DS
IRQ5
20
P14
MTIOC3A/MTCLKA/
TIOCB5/TCLKA/TMRI2/
PO15
CTS1#/RTS1#/SS1#/
CTX1/USB0_DPUPE/
USB0_OVRCURA
IRQ4
21
ADTRG0#
VCC_USB
22
USB0_DM
23
USB0_DP
24
S12ADa, DAa
VSS_USB
25
P55
MTIOC4D/TMO3
CRX1
26
P54
MTIOC4B/TMCI1
CTX1
27
PC7
MTIOC3A/
MTCLKB/TMO2 /PO31
TXD8/SMOSI8/SSDA8/
MISOA
IRQ14
28
PC6
MTIOC3C/MTCLKA/
TMCI2/PO30
RXD8/SMISO8/SSCL8/
MOSIA/USB0_EXICEN
IRQ13
29
PC5
MTIOC3B/MTCLKD/
TMRI2/PO29
SCK8/RSPCKA/USB0_ID
30
PC4
MTIOC3D/MTCLKC/
TMCI1/PO25/POE0#
SCK5/CTS8#/RTS8#/SS8#/
SSLA0/USB0_DPRPD
31
PC3
MTIOC4D/TCLKB/
PO24
TXD5/SMOSI5/SSDA5/
IETXD
R01DS0098EJ0180 Rev.1.80
May 13, 2014
IRQ10
Page 67 of 208
RX63N Group, RX631 Group
Table 1.12
Pin
Number
64-Pin
LQFP
1. Overview
List of Pins and Pin Functions (64-Pin LQFP) (2/3)
Power Supply
Clock
System Control
I/O Port
Timer
Timer
Communications
(MTU2a, TPUa, TMR, PPG,
RTCa, POE2a)
(SCIc, SCId, RSPI, RIIC, CAN,
IEB, USB)
Interrupt
32
PC2
MTIOC4B/TCLKA/
PO21
RXD5/SMISO5/SSCL5/
SSLA3/IERXD
33
PB7/
PC1
MTIOC3B/TIOCB5/
PO31
TXD9/SMOSI9/SSDA9
34
PB6/
PC0
MTIOC3D/TIOCA5/
PO30
RXD9/SMISO9/SSCL9
35
PB5
MTIOC2A/MTIOC1B/
TIOCB4/TMRI1/PO29/
POE1#
SCK9
36
PB3
MTIOC0A/MTIOC4A/
TIOCD3/TCLKD/TMO0/
PO27/POE3#
SCK6
37
PB1
MTIOC0C/MTIOC4C/
TIOCB3/TMCI0/PO25
TXD6/SMOSI6/SSDA6
IRQ4-DS
PB0
MTIC5W/TIOCA3/PO24
RXD6/SMISO6/SSCL6/
RSPCKA
IRQ12
41
PA6
MTIC5V/MTCLKB/
TIOCA2/TMCI3/PO22/
POE2#
CTS5#/RTS5#/SS5#/
MOSIA
42
PA4
MTIC5U/MTCLKA/
TIOCA1/TMRI0/PO20
TXD5/SMOSI5/SSDA5/
SSLA0
IRQ5-DS
43
PA3
MTIOC0D/MTCLKD/
TIOCD0/TCLKB/PO19
RXD5/SMISO5/SSCL5
IRQ6-DS
44
PA1
MTIOC0B/MTCLKC/
TIOCB0/PO17
SCK5/SSLA2/SCL2
IRQ11
45
PA0
MTIOC4A/TIOCA0/
PO16
SSLA1
38
VCC
39
40
S12ADa, DAa
VSS
46
PE5
MTIOC4C/MTIOC2B
RSPCKB
47
PE4
MTIOC4D/MTIOC1A/
PO28
SSLB0
AN012
48
PE3
MTIOC4B/PO26/POE8#
CTS12#/RTS12#/
SS12#/MISOB
AN011
49
PE2
MTIOC4A/PO23
RXD12/SMISO12/
SSCL12/RXDX12/
SSLB3/MOSIB
50
PE1
MTIOC4C/PO18
TXD12/SMOSI12/SSDA12/
TXDX12/SIOX12/SSLB2/
RSPCKB
AN009
51
PE0
SCK12/SSLB1
AN008
52
IRQ7-DS
AN013
AN010
VREFL
53
54
IRQ5
P46
IRQ14-DS
AN006
VREFH
55
P44
IRQ12-DS
AN004
56
P43
IRQ11-DS
AN003
57
P42
IRQ10-DS
AN002
P41
IRQ9-DS
AN001
P40
IRQ8-DS
AN000
58
59
60
VREFL0
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 68 of 208
RX63N Group, RX631 Group
Table 1.12
Pin
Number
64-Pin
LQFP
List of Pins and Pin Functions (64-Pin LQFP) (3/3)
Power Supply
Clock
System Control
61
VREFH0
62
AVCC0
63
64
1. Overview
I/O Port
P05
Timer
Timer
Communications
(MTU2a, TPUa, TMR, PPG,
RTCa, POE2a)
(SCIc, SCId, RSPI, RIIC, CAN,
IEB, USB)
Interrupt
S12ADa, DAa
IRQ13
DA1
AVSS0
R01DS0098EJ0180 Rev.1.80
May 13, 2014
Page 69 of 208
RX63N Group, RX631 Group
Table 1.13
Pin
Number
48-Pin
LQFP
1
1. Overview
List of Pins and Pin Functions (48-Pin LQFP) (1/2)
Power Supply
Clock
System Control
I/O Port
Timer
Communications
(MTU2a, TPUa, TMR, PPG,
POE2a)
(SCIc, SCId, RSPI, RIIC, CAN,
IEB, USB)
Interrupt
2
MD/FINED
3
RES#
4
XTAL
5
VSS
6
EXTAL
7
VCC
P37
P36
8
P35
9
P31
MTIOC4D/TMCI2/PO9
CTS1#/RTS1#/SS1#/
SSLB0/USB0_DPUPE
IRQ1-DS
10
P30
MTIOC4B/TMRI3/PO8/
POE8#
RXD1/SMISO1/SSCL1/
MISOB/USB0_DRPD
IRQ0-DS
11
FINEC
NMI
P27
MTIOC2B/TMCI3/PO7
SCK1/RSPCKB
12
P26
MTIOC2A/TMO1/PO6
TXD1/SMOSI1/SSDA1/
MOSIB/USB0_VBUSEN
13
P17
MTIOC3A/MTIOC3B/
TIOCB0/TCLKD/TMO1/
PO15/POE8#
SCK1/MISOA/SDA2-DS/
IETXD
IRQ7
14
P16
MTIOC3C/MTIOC3D/
TIOCB1/TCLKC/TMO2/
PO14
TXD1/SMOSI1/SSDA1/
MOSIA/SCL2-DS/IERXD/
USB0_VBUS/
USB0_VBUSEN/
USB0_OVRCURB
IRQ6
15
P15
MTIOC0B/MTCLKB/
TIOCB2/TCLKB/TMCI2/
PO13
RXD1/SMISO1/SSCL1/
CRX1-DS
IRQ5
16
P14
MTIOC3A/MTCLKA/
TIOCB5/TCLKA/TMRI2/
PO15
CTS1#/RTS1#/SS1#/
CTX1/USB0_DPUPE/
USB0_OVRCURA
IRQ4
17
USB0_DM
19
USB0_DP
VSS_USB
21
PC7
MTIOC3A/MTCLKB/
TMO2 /PO31
TXD8/SMOSI8/SSDA8/
MISOA
IRQ14
22
PC6
MTIOC3C/MTCLKA/
TMCI2/PO30
RXD8/SMISO8/SSCL8/
MOSIA/USB0_EXICEN
IRQ13
23
PC5
MTIOC3B/MTCLKD/
TMRI2/PO29
SCK8/RSPCKA/USB0_ID
24
PC4
MTIOC3D/MTCLKC/
TMCI1/PO25/POE0#
SCK5/CTS8#/RTS8#/SS8#/
/SSLA0/
USB0_DPRPD
25
PB5/
PC3
MTIOC2A/MTIOC1B/
TIOCB4/TMRI1/PO29/
POE1#
26
PB3/
PC2
MTIOC0A/MTIOC4A/
TIOCD3/TCLKD/TMO0/
PO27/POE3#
SCK6
27
PB1/
PC1
MTIOC0C/MTIOC4C/
TIOCB3/TMCI0/PO25
TXD6/SMOSI6/SSDA6
28
ADTRG0#
VCC_USB
18
20
S12ADa, DAa
VCL
IRQ4-DS
VCC
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RX63N Group, RX631 Group
Table 1.13
Pin
Number
1. Overview
List of Pins and Pin Functions (48-Pin LQFP) (2/2)
Timer
Communications
(MTU2a, TPUa, TMR, PPG,
POE2a)
(SCIc, SCId, RSPI, RIIC, CAN,
IEB, USB)
PB0/
PC0
MTIC5W/TIOCA3/PO24
RXD6/SMISO6/SSCL6/
RSPCKA
31
PA6
MTIC5V/MTCLKB/TIOCA2/
TMCI3/PO22/POE2#
CTS5#/RTS5#/SS5#/
MOSIA
32
PA4
MTIC5U/MTCLKA/
TIOCA1/TMRI0/PO20
TXD5/SMOSI5/SSDA5/
SSLA0
IRQ5-DS
33
PA3
MTIOC0D/MTCLKD/
TIOCD0/TCLKB/PO19
RXD5/SMISO5/SSCL5
IRQ6-DS
34
PA1
MTIOC0B/MTCLKC/
TIOCB0/PO17
SCK5/SSLA2
IRQ11
35
PE4
MTIOC4D/MTIOC1A/
PO28
SSLB0
AN012
36
PE3
MTIOC4B/PO26/POE8#
CTS12#/RTS12#/SS12#/
MISOB
AN011
37
PE2
MTIOC4A/PO23
RXD12/SMISO12/SSCL12/
RXDX12/
SSLB3/MOSIB
38
PE1
MTIOC4C/PO18
TXD12/SMISO12/SSDA12/
TXDX12/SIOX12/SSLB2/
RSPCKB
48-Pin
LQFP
Power Supply
Clock
System Control
29
30
39
S12ADa, DAa
IRQ7-DS
AN010
AN009
VREFL
P46
IRQ14-DS
AN006
P42
IRQ10-DS
AN002
P41
IRQ9-DS
AN001
P40
IRQ8-DS
AN000
VREFH
42
43
44
Interrupt
IRQ12
VSS
40
41
I/O Port
VREFL0
45
46
VREFH0
47
AVCC0
48
AVSS0
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RX63N Group, RX631 Group
2.
2. CPU
CPU
The RX CPU has sixteen general-purpose registers, nine control registers, and one accumulator used for DSP
instructions.
General-purpose register
b31
b0
R0
(SP)*1
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
Control register
b31
b0
ISP
(Interrupt stack pointer)
USP
(User stack pointer)
INTB
(Interrupt table register)
PC
(Program counter)
PSW
(Processor status word)
BPC
(Backup PC)
BPSW
(Backup PSW)
FINTV
(Fast interrupt vector register)
FPSW
(Floating-point status word)
DSP instruction register
b63
b0
ACC (Accumulator)
Note 1. The stack pointer (SP) can be the interrupt stack pointer (ISP) or user stack pointer (USP), according
to the value of the U bit in the PSW.
Figure 2.1
Register Set of the CPU
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RX63N Group, RX631 Group
2.1
2. CPU
General-Purpose Registers (R0 to R15)
This CPU has sixteen general-purpose registers (R0 to R15). R1 to R15 can be used as data registers or address registers.
R0, a general-purpose register, also functions as the stack pointer (SP).
The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the
stack pointer select bit (U) in the processor status word (PSW).
2.2
(1)
Control Registers
Interrupt Stack Pointer (ISP)/User Stack Pointer (USP)
The stack pointer (SP) can be either of two types, the interrupt stack pointer (ISP) or the user stack pointer (USP).
Whether the stack pointer operates as the ISP or USP depends on the value of the stack pointer select bit (U) in the
processor status word (PSW).
Set the ISP or USP to a multiple of four, as this reduces the numbers of cycles required to execute interrupt sequences
and instructions entailing stack manipulation.
(2)
Interrupt Table Register (INTB)
The interrupt table register (INTB) specifies the address where the relocatable vector table starts.
(3)
Program Counter (PC)
The program counter (PC) indicates the address of the instruction being executed.
(4)
Processor Status Word (PSW)
The processor status word (PSW) indicates the results of instruction execution or the state of the CPU.
(5)
Backup PC (BPC)
The backup PC (BPC) is provided to speed up response to interrupts.
After a fast interrupt has been generated, the contents of the program counter (PC) are saved in the BPC register.
(6)
Backup PSW (BPSW)
The backup PSW (BPSW) is provided to speed up response to interrupts.
After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in the BPSW. The
allocation of bits in the BPSW corresponds to that in the PSW.
(7)
Fast Interrupt Vector Register (FINTV)
The fast interrupt vector register (FINTV) is provided to speed up response to interrupts.
The FINTV register specifies a branch destination address when a fast interrupt has been generated.
(8)
Floating-Point Status Word (FPSW)
The floating-point status word (FPSW) indicates the results of floating-point operations.
When an exception handling enable bit (Ej) enables the exception handling (Ej = 1), the exception cause can be identified
by checking the corresponding Cj flag in the exception handling routine. If the exception handling is masked (Ej = 0), the
occurrence of exception can be checked by reading the Fj flag at the end of a series of processing. Once the Fj flag has
been set to 1, this value is retained until it is cleared to 0 by software (j = X, U, Z, O, or V).
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RX63N Group, RX631 Group
2.3
(1)
2. CPU
Register Associated with DSP Instructions
Accumulator (ACC)
The accumulator (ACC) is a 64-bit register used for DSP instructions. The accumulator is also used for the multiply and
multiply-and-accumulate instructions; EMUL, EMULU, FMUL, MUL, and RMPA, in which case the prior value in the
accumulator is modified by execution of the instruction.
Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The MVTACHI and MVTACLO
instructions write data to the higher-order 32 bits (bits 63 to 32) and the lower-order 32 bits (bits 31 to 0), respectively.
Use the MVFACHI and MVFACMI instructions for reading data from the accumulator. The MVFACHI and MVFACMI
instructions read data from the higher-order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively.
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RX63N Group, RX631 Group
3.
Address Space
3.1
Address Space
3. Address Space
This LSI has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is,
linear access to an address space of up to 4 Gbytes is possible, and this contains both program and data areas.
Figure 3.1 shows the memory maps in the respective operating modes. Accessible areas will differ according to the
operating mode and states of control bits.
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3. Address Space
On-chip ROM enabled
extended mode
Single-chip mode*1
On-chip ROM disabled
extended mode
0000 0000h
RAM*2
0000 0000h
RAM*2
0000 0000h
RAM*2
0004 0000h
Reserved area*3
0004 0000h
Reserved area*3
0004 0000h
Reserved area*3
0008 0000h
0008 0000h
0008 0000h
Peripheral I/O registers
0010 0000h
0010 0000h
On-chip ROM (E2 data flash)
0010 8000h
0010 0000h
On-chip ROM (E2 data flash)
0010 8000h
Reserved area*3
007F 8000h
FCU-RAM*4
Reserved area*3
007F 8000h
007F A000h
007F A000h
FCU-RAM*4
Reserved area*3
007F C000h
007F C500h
Reserved area*3
007F C000h
007F C500h
Peripheral I/O registers
Reserved
007F FC00h
0080 0000h
Peripheral I/O registers
area*3
Reserved area*3
Reserved area*3
007F FC00h
0080 0000h
Peripheral I/O registers
Reserved area*3
00E0 0000h
Peripheral I/O registers
Peripheral I/O registers
Peripheral I/O registers
Reserved area*3
00E0 0000h
On-chip ROM (program ROM)
(write only)
On-chip ROM (program ROM)
(write only)
0100 0000h
0100 0000h
0100 0000h
0800 0000h
Reserved area*3
External address space
External address space
(CS area)
(CS area)
0800 0000h
External address space
External address space
(SDRAM area)
(SDRAM area)
1000 0000h
1000 0000h
Reserved area*3
Reserved area*3
FEFF E000h
FF00 0000h
FF7F C000h
FF80 0000h
FEFF E000h
On-chip ROM (FCU firmware)
(read only)*4
FF00 0000h
Reserved area*3
On-chip ROM (user boot)
(read only)
FF80 0000h
Reserved area*3
FF00 0000h
Reserved area*3
FF7F C000h
On-chip ROM (user boot)
(read only)
FFE0 0000h
External address space
Reserved area*3
FFE0 0000h
On-chip ROM (program ROM)
(read only)*2
On-chip ROM (program ROM)
(read only)*3
FFFF FFFFh
Note 1.
Note 2.
On-chip ROM (FCU firmware)
(read only)*4
FFFF FFFFh
FFFF FFFFh
The address space in boot mode and user boot mode/USB boot mode is the same as the address space in single-chip mode.
The capacity of ROM/RAM differs depending on the products.
ROM (byt)
RAM (byt)
Capacity
Address (for reading only)
Address (for programming only)
2M
FFE0 0000h to FFFF FFFFh
00E0 0000h to 00FF FFFFh
1.5 M
1M
FFE8 0000h to FFFF FFFFh
FFF0 0000h to FFFF FFFFh
00E8 0000h to 00FF FFFFh
00F0 0000h to 00FF FFFFh
768 K
FFF4 0000h to FFFF FFFFh
00F4 0000h to 00FF FFFFh
512K
FFF8 0000h to FFFF FFFFh
00F8 0000h to 00FF FFFFh
384K
FFFA 0000h to FFFF FFFFh
00FA 0000h to 00FF FFFFh
256K
FFFC 0000h to FFFF FFFFh
00FC 0000h to 00FF FFFFh
512K
FFF8 0000h to FFFF FFFFh
00F8 0000h to 00FF FFFFh
384K
FFFA 0000h to FFFF FFFFh
00FA 0000h to 00FF FFFFh
256K
FFFC 0000h to FFFF FFFFh
00FC 0000h to 00FF FFFFh
Capacity
Address
256 K
0000 0000h to 0003 FFFFh
192 K
0000 0000h to 0002 FFFFh
128 K
0000 0000h to 0001 FFFFh
256 K
0000 0000h to 0003 FFFFh
192 K
0000 0000h to 0002 FFFFh
128 K
0000 0000h to 0001 FFFFh
256 K
0000 0000h to 0003 FFFFh
192 K
0000 0000h to 0002 FFFFh
128 K
0000 0000h to 0001 FFFFh
64K
0000 0000h to 0000 FFFFh
Note:See Table 1.3, List of Products, for the product type name.
Note 3. Reserved areas should not be accessed.
Note 4. For details on the FCU, see section 47, Flash Memory in the User’s manual: Hardware.
Figure 3.1
Memory Map in Each Operating Mode
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RX63N Group, RX631 Group
3.2
3. Address Space
External Address Space
The external address space is classified into CS areas (CS0 to CS7) and SDRAM area (SDCS). CS areas can be divided
into up to eight areas (CS0 to SC7) corresponding to the CSn# signal to be output from the CSn# pin.
Figure 3.2 shows the address ranges corresponding to the individual CS areas (CS0 to CS7) and SDRAM area (SDCS)
in on-chip ROM disabled extended mode.
0000 0000h
0004 0000h
RAM
Reserved
0100 0000h
area*1
CS7 (16 Mbytes)
0008 0000h
Peripheral I/O registers
01FF FFFFh
0200 0000h
0010 0000h
CS6 (16 Mbytes)
Reserved area*1
02FF FFFFh
0300 0000h
CS5 (16 Mbytes)
03FF FFFFh
0400 0000h
0100 0000h
CS4 (16 Mbytes)
External address space
(CS area)
04FF FFFFh
0500 0000h
CS3 (16 Mbytes)
0800 0000h
External address space
(SDRAM area)
05FF FFFFh
0600 0000h
1000 0000h
CS2 (16 Mbytes)
06FF FFFFh
0700 0000h
CS1 (16 Mbytes)
07FF FFFFh
0800 0000h
Reserved area*1
SDCS (128 Mbytes)
0FFF FFFFh
FF00 0000h
FF00 0000h
External address space
(CS area)*2
FFFF FFFFh
CS0 (16 Mbytes)
FFFF FFFFh
Note 1. Reserved areas should not be accessed.
Note 2. The CS0 area is disabled in on-chip ROM enabled extended mode.
In this mode, the address space for addresses above 1000 0000h is as shown in figure on
this section, Memory Map in Each Operating Mode.
Figure 3.2
Correspondence between External Address Spaces and CS Areas
(In On-Chip ROM Disabled Extended Mode)
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RX63N Group, RX631 Group
4.
4. I/O Registers
I/O Registers
This section gives information on the on-chip I/O register addresses. The information is given as shown below. Notes on
writing to registers are also given at the end.
(1)
I/O register addresses (address order)
Registers are listed from the lower allocation addresses.
Registers are classified according to module symbols.
The number of access cycles indicates the number of cycles based on the specified reference clock.
Among the internal I/O register area, addresses not listed in the list of registers are reserved. Reserved addresses
must not be accessed. Do not access these addresses; otherwise, the operation when accessing these bits and
subsequent operations cannot be guaranteed.
(2)
Notes on writing to I/O registers
When writing to an I/O register, the CPU starts executing the subsequent instruction before completing I/O register write.
This may cause the subsequent instruction to be executed before the post-update I/O register value is reflected on the
operation.
As described in the following examples, special care is required for the cases in which the subsequent instruction must be
executed after the post-update I/O register value is actually reflected.
[Examples of cases requiring special care]
The subsequent instruction must be executed while an interrupt request is disabled with the IENj bit in IERn of the
ICU (interrupt request enable bit) cleared to 0.
A WAIT instruction is executed immediately after the preprocessing for causing a transition to the low power
consumption state.
In the above cases, after writing to an I/O register, wait until the write operation is completed using the following
procedure and then execute the subsequent instruction.
(a) Write to an I/O register.
(b) Read the value from the I/O register to a general register.
(c) Execute the operation using the value read.
(d) Execute the subsequent instruction.
[Instruction examples]
Byte-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.B #SFR_DATA, [R1]
CMP [R1].UB, R1
;; Next process
Word-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.W #SFR_DATA, [R1]
CMP [R1].W, R1
;; Next process
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4. I/O Registers
Longword-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.L #SFR_DATA, [R1]
CMP [R1].L, R1
;; Next process
If multiple registers are written to and a subsequent instruction should be executed after the write operations are entirely
completed, only read the I/O register that was last written to and execute the operation using the value; it is not necessary
to read or execute operation for all the registers that were written to.
(3)
Number of Access Cycles to I/O Registers
For the number of I/O register access cycles, refer to Table 4.1, List of I/O Registers (Address Order).
The number of access cycles to I/O registers is obtained by following equation.*1
Number of access cycles to I/O registers = Number of bus cycles for internal main bus 1 +
Number of divided clock synchronization cycles +
Number of bus cycles for internal peripheral busses 1 to 6
The number of bus cycles of internal peripheral bus 1 to 6 differs according to the register to be accessed.
When peripheral functions connected to internal peripheral bus 2 to 6 or registers for the external bus control unit (except
for bus error related registers) are accessed, the number of divided clock synchronization cycles is added.
The number of divided clock synchronization cycles differs depending on the frequency ratio between ICLK and PCLK
(or FCLK, BCLK) or bus access timing.
In the peripheral function unit, when the frequency ratio of ICLK is equal to or greater than that of PCLK (or FCLK), the
sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will
be one cycle of PCLK (or FCLK) at a maximum. Therefore, one PCLK (or FCLK) has been added to the number of
access states shown in Table 4.1.
When the frequency ratio of ICLK is lower than that of PCLK (or FCLK), the subsequent bus access is started from the
ICLK cycle following the completion of the access to the peripheral functions. Therefore, the access cycles are described
on an ICLK basis.
In the external bus control unit, the sum of the number of bus cycles for internal main bus 1 and the number of divided
clock synchronization cycles will be one cycle of BCLK at a maximum. Therefore, one BCLK is added to the number of
access cycles shown in Table 4.1.
Note 1. This applies to the number of cycles when the access from the CPU does not conflict with the instruction fetching
to the external memory or bus access from the different bus master (DMAC or DTC).
(4)
Restrictions in Relation to RMPA and String-Manipulation Instructions
The allocation of data to be handled by RMPA or string-manipulation instructions to I/O registers is prohibited, and
operation is not guaranteed if this restriction is not observed.
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4.1
4. I/O Registers
I/O Register Addresses (Address Order)
Table 4.1
List of I/O Registers (Address Order) (1/50)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number
of Bits
Access
Size
0008 0000h
SYSTEM
Mode monitor register
MDMONR
16
16
3 ICLK
0008 0002h
SYSTEM
Mode status register
MDSR
16
16
3 ICLK
0008 0006h
SYSTEM
System control register 0
SYSCR0
16
16
3 ICLK
0008 0008h
SYSTEM
System control register 1
SYSCR1
16
16
3 ICLK
0008 000Ch
SYSTEM
Standby control register
SBYCR
16
16
3 ICLK
0008 0010h
SYSTEM
Module stop control register A
MSTPCRA
32
32
3 ICLK
0008 0014h
SYSTEM
Module stop control register B
MSTPCRB
32
32
3 ICLK
0008 0018h
SYSTEM
Module stop control register C
MSTPCRC
32
32
3 ICLK
0008 001Ch
SYSTEM
Module stop control register D
MSTPCRD
32
32
3 ICLK
0008 0020h
SYSTEM
System clock control register
SCKCR
32
32
3 ICLK
0008 0024h
SYSTEM
System clock control register 2
SCKCR2
16
16
3 ICLK
0008 0026h
SYSTEM
System clock control register 3
SCKCR3
16
16
3 ICLK
0008 0028h
SYSTEM
PLL control register
PLLCR
16
16
3 ICLK
0008 002Ah
SYSTEM
PLL control register 2
PLLCR2
8
8
3 ICLK
0008 0030h
SYSTEM
External bus clock control register
BCKCR
8
8
3 ICLK
0008 0032h
SYSTEM
Main clock oscillator control register
MOSCCR
8
8
3 ICLK
0008 0033h
SYSTEM
Sub-clock oscillator control register
SOSCCR
8
8
3 ICLK
0008 0034h
SYSTEM
Low-speed on-chip oscillator control register
LOCOCR
8
8
3 ICLK
0008 0035h
SYSTEM
IWDT-dedicated on-chip oscillator control register
ILOCOCR
8
8
3 ICLK
0008 0036h
SYSTEM
High-speed on-chip oscillator control register
HOCOCR
8
8
3 ICLK
0008 0040h
SYSTEM
Oscillation stop detection control register
OSTDCR
8
8
3 ICLK
0008 0041h
SYSTEM
Oscillation stop detection status register
OSTDSR
8
8
3 ICLK
0008 00A0h
SYSTEM
Operating power control register
OPCCR
8
8
3 ICLK
0008 00A1h
SYSTEM
Sleep mode return clock source switching register
RSTCKCR
8
8
3 ICLK
3 ICLK
ICLKPCLK
ICLK
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