Features
Datasheet
RX63T Group
Renesas MCUs
R01DS0087EJ0220
Rev.2.20
Mar 31, 2016
100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS,
Two 12-bit ADCs (three S/H circuits, double data registers, amplifier, comparator), one 10-bit ADC, simultaneous
sampling on 7 channels using three ADCs, 100 MHz PWM (2 three-phase complementary channels + 4 single-phase
complementary channels or 3 three-phase complementary channels + 1 single-phase complementary channel)
Features
■ 32-bit RX CPU core
Max. operating frequency: 100 MHz
Capable of 165 DMIPS in operation at 100 MHz
Single precision 32-bit IEEE-754 floating point
Two types of multiply-and-accumulation unit (between memories
and between registers)
32-bit multiplier (fastest instruction execution takes one CPU clock
cycle)
Divider (fastest instruction execution takes two CPU clock cycles)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions: Ultra-compact code
Supports the memory protection unit (MPU)
Two types of debugging interfaces: JTAG and FINE (two-line)
■ Low-power design and architecture
Single 3.3-V supply or single 5-V supply; 3.3-V products can be
used with a 5-V analog power supply
Four low-power modes
■ On-chip main flash memory, no wait states
100-MHz operation, 10-ns read cycle (no wait states)
Max. 512 Kbytes
User code is programmable by USB, SCI, or JTAG.
■ On-chip data flash memory
Max. 32 Kbytes, reprogrammable up to 100,000 times
Programming/erasing as background operations (BGOs)
■ On-chip SRAM, no wait states
Max. 48 Kbytes
For instructions and operands
■ DMA
DMA: Incorporates four channels
DTC: A single unit can handle transfer on multiple channels.
■ Reset and supply management
Power-on reset (POR)
Low voltage detection (LVD) with voltage settings
■ Clock functions
External crystal oscillator or internal PLL for operation at 4 to 12.5
MHz
Internal 125-kHz LOCO
Dedicated 125-kHz LOCO for the IWDT
■ Independent watchdog timer
125-kHz LOCO clock operation
■ Useful functions for IEC60730 compliance
Oscillation-stop detection, frequency measurement, CRC, IWDT,
self-diagnostic function for the A/D converter, etc.
■ External address space
4 CS areas (4 × 1 Mbyte)
Multiplexed address data or separate address lines are selectable per
area.
8- or 16-bit bus space is selectable per area.
PLQP0144KA-A
PLQP0120KA-A
PLQP0112JA-A
PLQP0100KB-A
PLQP0064KB-A
PLQP0048KB-A
20 × 20mm, 0.5mm pitch
16 × 16mm, 0.5mm pitch
20 × 20mm, 0.65mm pitch
14 × 14mm, 0.5mm pitch
10 × 10mm, 0.5mm pitch
7 × 7mm, 0.5mm pitch
■ Up to 11 communications interfaces
USB 2.0 full-speed function interface (1 channel)
CAN (compliant with ISO11898-1), incorporating 32 mailboxes (1
channel)
SCI with multiple functionalities (5 channels)
Choose from among asynchronous mode, clock-synchronous mode,
smart-card interface mode, simple SPI, simple I2C, and extended
serial mode.
I2C bus interface for SMBus (2 channels)
RSPI for high-speed transfer (2 channels)
■ Up to twenty 16-bit timers
16-bit MTU3: 100-MHz operation, input capture, output compare,
three-phase complementary PWM waveform output (2 channels),
phase-counting mode (8 channels); complementary PWM does not
burden the CPU.
16-bit GPT: 100-MHz operation, input capture, output compare, 4channel single-phase complementary PWM waveform output or 1channel three-phase complementary + 1-channel single-phase
complementary output, interlocking with comparator (counter
operation, PWM negation control), detection of abnormal oscillation
frequencies (useful for IEC60730 compliance)
(8 channels); complementary PWM does not burden the CPU.
16-bit CMT (4 channels)
■ Generation of delays in PWM waveforms (for
products with the product ID code 1)
The timing with which signals on the 16-bit GPT PWM output pin
rise and fall can be controlled with an accuracy of up to 312 ps (in
operation at 100 MHz).
■ Two A/D converters for 1-MHz operation, total of 8
channels
Simultaneous sampling on 7 channels is possible with three units.
Self-diagnosis function (useful for IEC60730 compliance)
Two 12-bit ADCs: three sample-and-hold circuits, double data
registers, amplifier, comparator (8 channels)
One 10-bit ADC (12 channels)
■ One A/D converter for 2-MHz operation, total of 20
channels
One 10-bit ADC (20 channels)
■ 10-bit D/A converter: 2 channels
■ Digital Power Supply Controller-Dedicated
Calculation Function (for products with product ID
code 1)
16-bit fixed-point calculation function that handles compensatory
calculations in the method of digital control for switched-mode
power supplies.
■ Register write protection function can protect values
in important registers against overwriting.
■ Up to 110 pins for GPIO
Open drain, switchable driving ability
■ Operating temp. range
–40C to +85C
–40C to +105C
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 1 of 186
RX63T Group
1. Overview
1.
Overview
1.1
Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 lists the functions of products.
Table 1.1 shows an outline of the maximum specifications, and the available peripheral modules and number of
channels differ according to the number of pins on the package and the ROM capacity. For details, see Table 1.2,
Comparison of Functions for Different Packages.
Table 1.1
Outline of Specifications (1/7)
Classification
Module/Function
Description
CPU
CPU
Maximum operating frequency: 100 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per state (cycle of the system
clock)
Address space: 4-Gbyte linear
Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Nine 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
Floating-point operation instructions: 8
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32 × 32 64 bits
On-chip divider: 32 / 32 32 bits
Barrel shifter: 32 bits
Memory protection unit (MPU)
FPU
Single precision floating point (32 bits)
Data types and floating-point exceptions in conformance with the IEEE754 standard
ROM
Capacity: 512 Kbytes, 384 Kbytes, 256 Kbytes, 64 Kbytes, 48 Kbytes, 32 Kbytes
100 MHz, no-wait access
On-board programming: Programs can be modified through SCI or USB while the MCU
is mounted on the board.
Off-board programming: Programs can be modified using parallel programmer.
(only in 144-, 120-, 112- and 100-pin versions)
RAM
Capacity: 48 Kbytes, 32 Kbytes, 24 Kbytes, 8 Kbytes
100 MHz, no-wait access
E2 data flash
Capacity: 32 Kbytes, 8 Kbytes
Programming/erasing: 100,000 times
On-board programming:
Programs can be modified through SCI or USB while the MCU is mounted on the board.
Programming from the user program is possible.
Memory
MCU operating modes
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
[144-, 120-, 112- and 100-pin versions]
Single-chip mode, on-chip ROM enabled extended mode, on-chip ROM disabled
extended mode (switchable by software)
[64- and 48-pin versions]
Single-chip mode
Page 2 of 186
RX63T Group
Table 1.1
1. Overview
Outline of Specifications (2/7)
Classification
Module/Function
Description
Clock
Clock generation circuit
Main clock oscillator, low-speed on-chip oscillator, PLL frequency synthesizer, and
dedicated on-chip oscillator for the IWDT
Main-clock oscillation stop detection
Separate frequency-division and multiplication settings for the system clock (ICLK),
peripheral module clock (PCLKA), peripheral module clock (PCLKB), AD clock
(PCLKC), FlashIF clock (FCLK) and S12AD clock (PCLKD).
The CPU and other bus masters run in synchronization with the system clock (ICLK):
Up to 100 MHz
Multi-function timer pulse unit 3 and general PWM timer run in synchronization with
PCLKA: Up to 100 MHz
Peripheral modules run in synchronization with the peripheral module clock (PCLKB):
Up to 50 MHz
Flash IF run in synchronization with the FlashIF clock (FCLK): Up to 50 MHz
Devices connected to the external bus run in synchronization with the external bus
clock (BCLK): Up to 50 MHz
10-bit A/D converter runs in synchronization with the AD clock (PCLKC): Up to 100 MHz
12-bit A/D converter runs in synchronization with the S12AD clock (PCLKD): Up to 50
MHz
Clock
Clock frequency
accuracy measurement
circuit (CAC)
The frequency of the following clocks can be measured; the main clock oscillator, PLL
circuit, and IWDT-dedicated on-chip oscillator.
Reset
RES# pin reset, power-on reset, voltage-monitoring reset, independent watchdog timer
reset, watchdog timer reset, deep software standby reset, and software reset
Voltage detection circuit
When the voltage on VCC passes the voltage detection level (Vdet), an internal reset or
internal interrupt is generated.
Low power
consumption
Low power
consumption facilities
Module stop function
Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software
standby mode
Interrupt
Interrupt controller
(ICUb)
Peripheral function interrupts: Up to 169 sources
External interrupts: Up to 8 (pins IRQ0 to IRQ7)
Software interrupts: One source
Non-maskable interrupts: 6 sources
Sixteen levels specifiable for the order of priority
External bus extension
The external address space can be divided into four areas (CS0 to CS3), each with
independent control of access settings.
Capacity of each area: 1 Mbyte (CS0 to CS3)
A chip-select signal (CS0# to CS3#) can be output for each area.
Each area is specifiable as an 8- or 16-bit bus space
The data arrangement in each area is selectable as little or big endian (only for data).
Bus format: Separate bus, multiplex bus
Wait control
Write buffer facility
DMA
DMA controller
(DMACA)
4 channels
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software trigger, external interrupts, and interrupt requests from
peripheral functions
Data transfer controller
(DTCa)
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software interrupt activation register settings, external interrupts,
and interrupt requests from peripheral functions
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 3 of 186
RX63T Group
Table 1.1
1. Overview
Outline of Specifications (3/7)
Classification
Module/Function
Description
I/O ports
General I/O ports
144-pin LQFP
I/O pins: 81
Input pins: 29
Open-drain outputs: 27
120-pin LQFP
I/O pins: 72
Input pin: 21
Open-drain outputs: 26
112-pin LQFP
I/O pins: 69
Input pins: 21
Open-drain outputs: 20
100-pin LQFP
I/O pins: 57
Input pins: 21
Open-drain outputs: 16
64-pin LQFP
I/O pins: 39
Input pins: 9
Open-drain outputs: 10
5-V tolerance: 39
48-pin LQFP
I/O pins: 25
Input pins: 7
Open-drain outputs: 8
5-V tolerance: 25
Timers
Multi-function timer
pulse unit 3 (MTU3)
(16 bits × 8 channels)
Maximum of 16 pulse-input/output and 3 pulse-input possible
Select eight clocks from among ten count clocks (PCLKA/1, PCLKA/4, PCLKA/16,
PCLKA/64, PCLKA/256, PCLKA/1024, MTCLKA, MTCLKB, MTCLKC, and MTCLKD)
for each channel (seven clocks for channel 1, four clocks for channel 5, and six clocks
for channel 6 or 7)
24 output compare/input capture registers
Counter-clearing operation (simultaneous clearing on compare match or input capture)
Simultaneous writing to multiple timer counters (TCNT)
Simultaneous input and output to registers in synchronization with counter operations
Buffer operation specifiable
Capable of cascade-connected operation
Interrupts: 38 sources
Automatic transfer of register data
Pulse output modes
Topple, PWM, complementary PWM, and reset-synchronous PWM modes
Complementary PWM output mode
Outputs non-overlapping waveforms for controlling 3-phase inverters
Automatic specification of dead times
PWM duty cycle: Selectable as any value from 0% to 100%
Delay can be applied to requests for A/D conversion.
Non-generation of interrupt requests at peak or trough values of counters can be
selected.
Double buffering
Reset-synchronous PWM mode
Three PWM waveforms and corresponding inverse waveforms are output with the
desired duty cycles.
Phase-counting mode
Counter functionality for dead-time compensation
Generation of triggers for A/D converters
Differential timing for initiation of A/D conversion
Port output enable 3
(POE3)
Control of the high-impedance state of the MTU3 and GPT’s waveform output pins
Six pins for input from signal sources: POE0, POE4, POE8, POE10, POE11, and
POE12
Initiation on detection of short-circuited outputs (detection of PWM outputs having
simultaneously become an active level.)
Initiation by comparator-detection, oscillation-stoppage detection, or software
Software control of the states of pins for output control can also be added.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 4 of 186
RX63T Group
Table 1.1
1. Overview
Outline of Specifications (4/7)
Classification
Module/Function
Description
Timers
General PWM timer
(GPT)
16 bits x 8 channels
Counting up or down (saw-wave), counting up and down (triangle-wave) selectable for
all channels
Select from among four count clocks (PCLKA/1, PCLKA/4, PCLKA/8, and PCLKA/16)
for each channel
2 input/output pins per channel
2 output compare/input capture registers per channel
For the 2 output compare/input capture registers of each channel, 4 registers are
provided as buffer registers and are capable of operating as comparison registers when
buffering is not in use.
In output compare operation, buffer switching can be at peaks or troughs, enabling the
generation of laterally asymmetrically PWM waveforms.
Registers for setting up frame intervals on each channel (with capability for generating
interrupts on overflow or underflow)
Synchronizable operation of the several counters
Modes of synchronized operation (synchronized, or displaced by desired times for
phase shifting)
Generation of dead times in PWM operation
Through combination of three counters, generation of automatic three-phase PWM
waveforms incorporating dead times
Starting, clearing, and stopping counters in response to external or internal triggers
Internal trigger sources: Output of the internal comparator detection, software, and
compare-match
The main clock can be used as a counter clock for measuring the timing of the edges of
signals produced by frequency-dividing the dedicated clock signal for the IWDT (to
detect abnormal oscillation).
A PWM delay with an accuracy of up to 1/32 times the period of the system clock (ICLK)
can be generated to control the timing with which signals from the two PWM output pins
from each of channels 0 to 3 rise and fall.
Compare match timer
(CMT)
(16 bits × 2 channels) × 2 units
Select from among four internal clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/
512)
Watchdog timer
(WDTA)
14 bits × 1 channel
Select from among 6 counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/
512, PCLK/2048, PCLK/8192)
Independent watchdog
timer (IWDTa)
14 bits × 1 channel
Counter-input clock: Dedicated on-chip oscillator
Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,
dedicated clock/128, dedicated clock/256
USB 2.0 host/function
module (USBa)
Serial communications
interfaces (SCIc, SCId)
5 channels (SCIc: 4 channels + SCId: 1 channel)
SCIc
Serial communications modes: Asynchronous, clock synchronous, and smart-card
interface
Multi-processor function
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Simple I2C
Simple SPI
SCId (The following functions are added to SCIc)
Supports the serial communications protocol, which contains the start frame and
information frame
Supports the LIN format
Communication
function
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Includes a UDC (USB Device Controller) and transceiver for USB 2.0
Single port
Compliance with the USB 2.0 specification
Transfer rate: Full speed (12 Mbps)
Self-power mode and bus power mode are selectable
Supports the OTG (On-The-Go)
Incorporates 2 Kbytes of RAM as a transfer buffer
Page 5 of 186
RX63T Group
Table 1.1
1. Overview
Outline of Specifications (5/7)
Classification
Module/Function
Description
Communication
function
I2 C
bus interfaces
(RIIC)
2 channels
Communication formats
I2C bus format/SMBus format
Supports the multi-master
Max. transfer rate: 400 kbps
CAN module (CAN)
1 channels
Compliance with the ISO11898-1 specification (standard frame and extended frame)
32 mailboxes per channel
Serial peripheral
interfaces (RSPI)
2 channels
RSPI transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),
and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four
lines) or clock-synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Switching between MSB first and LSB first
The number of bits in each transfer can be changed to any number of bits from 8 to 16,
or to 20, 24, or 32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with
each frame having up to 32 bits)
Buffered structure
Double buffers for both transmission and reception
Max. transfer rate
In master mode: [144-, 120-, 112- and 100-pin versions]
25 Mbps
[64- and 48-pin versions]
12.5 Mbps
In slave mode: 6.25 Mbps
12-bit A/D converter (S12ADB)
[144-, 120-, 112- and 100-pin versions]
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
12 bits (4 channels x 2 unit)
12-bit resolution
Conversion time
1.0 s per channel (clock for S12ADB, PCLKD (A/D conversion clock ADCLK) = 50
MHz, AVCC0 = 4.0 to 5.5 V)
2.0 s per channel (clock for S12ADB, PCLKD (A/D conversion clock ADCLK) = 25
MHz, AVCC0 = 3.0 to 3.6 V)
Operating modes
Scan mode (single-cycle scan mode/continuous scan mode/group scan mode)
Group A priority control (only for the group scan mode)
Sample-and-hold function
A common sample-and-hold circuit for units is included.
Additionally, sample-and-hold circuit for each unit is included. (three channels per unit)
Self-diagnostic function
The self-diagnostic function internally generates three analog input voltages (VREFL0,
VREFH0 x 1/2, VREFH0).
Double trigger mode (duplication of A/D converted data)
Input signal amplification function using programmable gain amplifier (three channels
per unit)
Amplification factors: 2.0 times, 2.5 times, 3.077 times, 3.636 times, 4.0 times, 4.444
times, 5.0 times, 5.714 times, 6.667 times, 10.0 times, 13.333 times (total of 11 steps)
Three ways to start A/D conversion
Conversion can be started by software, a conversion start trigger from a timer (MTU3 or
GPT), or an external trigger signal.
Window comparators (three channels per unit)
Page 6 of 186
RX63T Group
Table 1.1
Classification
1. Overview
Outline of Specifications (6/7)
Module/Function
Description
12-bit A/D converter (S12ADB)
[64- and 48-pin versions]
12 bits (8 channels x 1 unit)
12-bit resolution
Conversion time
1.0 µs per channel (S12ADB clock: PCLKD (A/D conversion clock: ADCLK) = 50 MHz
Operating modes
Scan mode (single scan mode / continuous scan mode / group scan mode)
Group A priority control (group scan mode only)
Sample-and-hold function
A common sample-and-hold circuit for units is included
Separate sample-and-hold circuits are also included (three channels per unit)
Self-diagnosis function
Three analog input voltages (VREFL0, VREFH0 × 1/2, VREFH0) can be generated
internally by the self-diagnosis function.
Double trigger mode (double the results of A/D conversion)
Three ways to start A/D conversion
Conversion can be started by software, a conversion start trigger from a timer (MTU3 or
GPT), or an external trigger signal.
Window comparators (three channels per unit)
10-bit A/D converter (ADA)
10 bits (20 channels × 1 unit)
10-bit resolution
Conversion time
0.5 µs per channel (A/D conversion clock ADCLK = 100 MHz)
Two operating modes
Single mode, scan mode
Scan mode
Single-cycle scan mode
Continuous scan mode
Sample-and-hold function
A common sample-and-hold circuit for units is included
Three ways to start A/D conversion
Conversion can be started by software, a conversion start trigger from a timer (MTU3 or
GPT), or an external trigger signal.
8-bit precision output
2-bit right shifting for output of conversion results is selectable.
Self-diagnostic function
The self-diagnostic function internally generates three analog input voltages (AVSS,
VREF x 1/2, VREF)
D/A converter (DAa)
2 channels
10-bit resolution
Output voltage: 0 V to VREF
CRC calculator (CRC)
CRC code generation for arbitrary amounts of data in 8-bit units
Select any of three generating polynomials:
X8 + X2 + X + 1, X16 + X15 + X2 + 1, or X16 + X12 + X5 + 1.
Generation of CRC codes for use with LSB-first or MSB-first communications is
selectable
Data operating circuit (DOC)
Comparison, addition, and subtraction of 16-bit data
Digital power supply controller (DPC)
Control parameters calculation unit of the digital switch-mode power supply systems.
Adopt robust control algorithm with high control stability
Results of measurement by the 10-bit A/D converter can be used in calculating the
control parameters.
Operating frequency
Up to 100 MHz
Power supply voltage
[144-, 120-, 112- and 100-pin versions]
3-V product
VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, or 4.0 to 5.5 V
VREFH0 = 3.0 to AVCC0, or 4.0 to AVCC0
5-V product
VCC = PLLVCC = 4.0 to 5.5 V
VCC_USB = 3.0 to 3.6 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V
VREFH0 = 4.0 to AVCC0
Power supply voltage
[64- and 48-pin versions]
VCC = 2.7 to 3.6 V, AVCC0 = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 7 of 186
RX63T Group
Table 1.1
Classification
1. Overview
Outline of Specifications (7/7)
Module/Function
Description
Operating temperature
D version: -40 to +85°C,
G version: -40 to +105°C *1
Package
144-pin LQFP (PLQP0144KA-A (20 × 20, 0.5-mm pitch))
120-pin LQFP (PLQP0120KA-A (16 × 16, 0.5-mm pitch))
112-pin LQFP (PLQP0112JA-A (20 × 20, 0.65-mm pitch))
100-pin LQFP (PLQP0100KB-A (14 × 14, 0.5-mm pitch))
64-pin LQFP (PLQP0064KB-A (10 × 10, 0.5-mm pitch))
48-pin LQFP (PLQP0048KB-A (07 × 07, 0.5-mm pitch))
On-chip debugging system
E1 emulator (JTAG and FINE interfaces)
E20 emulator (JTAG interface)
Note 1. Please contact Renesas Electronics sales office for derating of operation under Ta = +85°C to +105°C. Derating is the
systematic reduction of load for the sake of improved reliability.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 8 of 186
RX63T Group
Table 1.2
1. Overview
Comparison of Functions for Different Packages
Functions
RX63T Group
Package
144 Pins
120 Pins
External bus
64 Pins
48 Pins
—
1 Mbyte × 4 areas
—
DMA controller (DMACA)
Ch. 0 to 3
Data transfer controller (DTCa)
Supported
Interrupt
controller (ICUb)
NMI pin
Timers
Multi-function timer pulse unit 3
(MTU3)*1
Supported
IRQ pin
General
PWM timer
(GPT)*1
Supported (x 8)
Supported (x 6)
Ch. 0 to 7
Generation of
delays in PWM,
not supported
Ch. 0 to 7
Ch. 0 to 3
Generation of
delays in PWM,
supported
Ch. 0 to 3
—
Port output enable 3 (POE3)
Communication
function
100 Pins
16 bits
External address space
DMA
112 Pins
Supported (POE pins × 6)
Supported
(POE pins
× 5)
Compare match timer (CMT)
Ch. 0 to 3
Watchdog timer (WDTA)
Supported
Independent watchdog timer
(IWDTa)
Supported
USB2.0 host/function module
(USBa)
Ch. 0
Serial communications
interfaces (SClc)
—
Ch. 0 to 3
Ch. 0 to 2
Serial communications
interfaces (SCld)
I2C bus interfaces (RIIC)
Supported
(POE pins × 4)
Ch. 0, 1
Ch. 12
Ch. 0, 1
Ch. 0
Serial peripheral interfaces
(RSPI)
Ch. 0, 1
Ch. 0
CAN module (CAN)
(as an optional function)*1
Ch. 0
—
12-bit A/D converter (S12ADB)
4 channels × 2 units
8 channels
× 1 unit
(AN000 to
007)
8 channels
× 1 unit
(AN000 to
004, 007)
Three-channel simultaneous
sampling function
2 units
1 unit
Programmable gain amplifier
3 channels × 2 units
—
3 channels × 2 units
3 channels × 1 unit
Window comparator
10-bit A/D converter (ADA)
D/A converter (DAa)
20
channels
12 channels
Ch. 0, 1
Clock Frequency Accuracy Measurement Circuit
Digital power supply controller (DPC)*2
—
—
Supported
Supported
Not supported
Note 1. For the MTU3 and GPT, the number of pins will differ with the package. See the list of pins and pin functions for details.
In addition, the CAN module is an optional function. For details, see Table 1.3.
Note 2. Not provided for the product ID code O.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 9 of 186
RX63T Group
1.2
1. Overview
List of Products
Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part number.
Table 1.3
List of Products (1/4)
Group
Part No.
Order Part No.
Package
On-chip ROM
Capacity
On-chip RAM
Capacity
RX63T
R5F563TEADFB
R5F563TEADFB#V0
PLQP0144KA-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TEADFB
R5F563TEADFB#V1
PLQP0144KA-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TEADFA
R5F563TEADFA#V0
PLQP0120KA-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TEADFA
R5F563TEADFA#V1
PLQP0120KA-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TEADFH
R5F563TEADFH#V0
PLQP0112JA-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TEADFH
R5F563TEADFH#V1
PLQP0112JA-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TEADFP
R5F563TEADFP#V0
PLQP0100KB-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TEADFP
R5F563TEADFP#V1
PLQP0100KB-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TCADFB
R5F563TCADFB#V0
PLQP0144KA-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TCADFB
R5F563TCADFB#V1
PLQP0144KA-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TCADFA
R5F563TCADFA#V0
PLQP0120KA-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TCADFA
R5F563TCADFA#V1
PLQP0120KA-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TCADFH
R5F563TCADFH#V0
PLQP0112JA-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TCADFH
R5F563TCADFH#V1
PLQP0112JA-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TCADFP
R5F563TCADFP#V0
PLQP0100KB-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TCADFP
R5F563TCADFP#V1
PLQP0100KB-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TBADFB
R5F563TBADFB#V0
PLQP0144KA-A
256 Kbytes
24 Kbytes
CAN module
included
R5F563TBADFB
R5F563TBADFB#V1
PLQP0144KA-A
256 Kbytes
24 Kbytes
CAN module
included
R5F563TBADFA
R5F563TBADFA#V0
PLQP0120KA-A
256 Kbytes
24 Kbytes
CAN module
included
R5F563TBADFA
R5F563TBADFA#V1
PLQP0120KA-A
256 Kbytes
24 Kbytes
CAN module
included
R5F563TBADFH
R5F563TBADFH#V0
PLQP0112JA-A
256 Kbytes
24 Kbytes
CAN module
included
R5F563TBADFH
R5F563TBADFH#V1
PLQP0112JA-A
256 Kbytes
24 Kbytes
CAN module
included
R5F563TBADFP
R5F563TBADFP#V0
PLQP0100KB-A
256 Kbytes
24 Kbytes
CAN module
included
R5F563TBADFP
R5F563TBADFP#V1
PLQP0100KB-A
256 Kbytes
24 Kbytes
CAN module
included
R5F563TEDDFB
R5F563TEDDFB#V0
PLQP0144KA-A
512 Kbytes
48 Kbytes
CAN module
not included
R5F563TEDDFA
R5F563TEDDFA#V0
PLQP0120KA-A
512 Kbytes
48 Kbytes
CAN module
not included
R5F563TEDDFH
R5F563TEDDFH#V0
PLQP0112JA-A
512 Kbytes
48 Kbytes
CAN module
not included
R5F563TEDDFP
R5F563TEDDFP#V0
PLQP0100KB-A
512 Kbytes
48 Kbytes
CAN module
not included
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Option
Operating
Voltage
Operating
Temperature
VCC/
PLLVCC
4.0 to 5.5V
VCC_USB
3.0 to 3.6V
AVCC/
AVCC0 4.0
to 5.5V
-40 to +85°C
(D Version)
Page 10 of 186
RX63T Group
Table 1.3
1. Overview
List of Products (2/4)
Group
Part No.
Order Part No.
Package
On-chip ROM
Capacity
On-chip RAM
Capacity
RX63T
R5F563TCDDFB
R5F563TCDDFB#V0
PLQP0144KA-A
384 Kbytes
32 Kbytes
CAN module
not included
R5F563TCDDFA
R5F563TCDDFA#V0
PLQP0120KA-A
384 Kbytes
32 Kbytes
CAN module
not included
R5F563TCDDFH
R5F563TCDDFH#V0
PLQP0112JA-A
384 Kbytes
32 Kbytes
CAN module
not included
R5F563TCDDFP
R5F563TCDDFP#V0
PLQP0100KB-A
384 Kbytes
32 Kbytes
CAN module
not included
R5F563TBDDFB
R5F563TBDDFB#V0
PLQP0144KA-A
256 Kbytes
24 Kbytes
CAN module
not included
R5F563TBDDFA
R5F563TBDDFA#V0
PLQP0120KA-A
256 Kbytes
24 Kbytes
CAN module
not included
R5F563TBDDFH
R5F563TBDDFH#V0
PLQP0112JA-A
256 Kbytes
24 Kbytes
CAN module
not included
R5F563TBDDFP
R5F563TBDDFP#V0
PLQP0100KB-A
256 Kbytes
24 Kbytes
CAN module
not included
R5F563TEBDFB
R5F563TEBDFB#V0
PLQP0144KA-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TEBDFB
R5F563TEBDFB#V1
PLQP0144KA-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TEBDFA
R5F563TEBDFA#V0
PLQP0120KA-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TEBDFA
R5F563TEBDFA#V1
PLQP0120KA-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TEBDFH
R5F563TEBDFH#V0
PLQP0112JA-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TEBDFH
R5F563TEBDFH#V1
PLQP0112JA-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TEBDFP
R5F563TEBDFP#V0
PLQP0100KB-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TEBDFP
R5F563TEBDFP#V1
PLQP0100KB-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TCBDFB
R5F563TCBDFB#V0
PLQP0144KA-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TCBDFB
R5F563TCBDFB#V1
PLQP0144KA-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TCBDFA
R5F563TCBDFA#V0
PLQP0120KA-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TCBDFA
R5F563TCBDFA#V1
PLQP0120KA-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TCBDFH
R5F563TCBDFH#V0
PLQP0112JA-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TCBDFH
R5F563TCBDFH#V1
PLQP0112JA-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TCBDFP
R5F563TCBDFP#V0
PLQP0100KB-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TCBDFP
R5F563TCBDFP#V1
PLQP0100KB-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TBBDFB
R5F563TBBDFB#V0
PLQP0144KA-A
256 Kbytes
24 Kbytes
CAN module
included
R5F563TBBDFB
R5F563TBBDFB#V1
PLQP0144KA-A
256 Kbytes
24 Kbytes
CAN module
included
R5F563TBBDFA
R5F563TBBDFA#V0
PLQP0120KA-A
256 Kbytes
24 Kbytes
CAN module
included
R5F563TBBDFA
R5F563TBBDFA#V1
PLQP0120KA-A
256 Kbytes
24 Kbytes
CAN module
included
R5F563TBBDFH
R5F563TBBDFH#V0
PLQP0112JA-A
256 Kbytes
24 Kbytes
CAN module
included
R5F563TBBDFH
R5F563TBBDFH#V1
PLQP0112JA-A
256 Kbytes
24 Kbytes
CAN module
included
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Option
Operating
Voltage
Operating
Temperature
VCC/
PLLVCC
4.0 to 5.5V
VCC_USB
3.0 to 3.6V
AVCC/
AVCC0 4.0
to 5.5V
-40 to +85°C
(D Version)
VCC/
PLLVCC/
VCC_USB
2.7 to 3.6V
AVCC/
AVCC0 3.0
to 3.6V or
4.0 to 5.5V
Page 11 of 186
RX63T Group
Table 1.3
1. Overview
List of Products (3/4)
Group
Part No.
Order Part No.
Package
On-chip ROM
Capacity
On-chip RAM
Capacity
RX63T
R5F563TBBDFP
R5F563TBBDFP#V0
PLQP0100KB-A
256 Kbytes
24 Kbytes
CAN module
included
R5F563TBBDFP
R5F563TBBDFP#V1
PLQP0100KB-A
256 Kbytes
24 Kbytes
CAN module
included
R5F563TEEDFB
R5F563TEEDFB#V0
PLQP0144KA-A
512 Kbytes
48 Kbytes
CAN module
not included
R5F563TEEDFA
R5F563TEEDFA#V0
PLQP0120KA-A
512 Kbytes
48 Kbytes
CAN module
not included
R5F563TEEDFH
R5F563TEEDFH#V0
PLQP0112JA-A
512 Kbytes
48 Kbytes
CAN module
not included
R5F563TEEDFP
R5F563TEEDFP#V0
PLQP0100KB-A
512 Kbytes
48 Kbytes
CAN module
not included
R5F563TCEDFB
R5F563TCEDFB#V0
PLQP0144KA-A
384 Kbytes
32 Kbytes
CAN module
not included
R5F563TCEDFA
R5F563TCEDFA#V0
PLQP0120KA-A
384 Kbytes
32 Kbytes
CAN module
not included
R5F563TCEDFH
R5F563TCEDFH#V0
PLQP0112JA-A
384 Kbytes
32 Kbytes
CAN module
not included
R5F563TCEDFP
R5F563TCEDFP#V0
PLQP0100KB-A
384 Kbytes
32 Kbytes
CAN module
not included
R5F563TBEDFB
R5F563TBEDFB#V0
PLQP0144KA-A
256 Kbytes
24 Kbytes
CAN module
not included
R5F563TBEDFA
R5F563TBEDFA#V0
PLQP0120KA-A
256 Kbytes
24 Kbytes
CAN module
not included
R5F563TBEDFH
R5F563TBEDFH#V0
PLQP0112JA-A
256 Kbytes
24 Kbytes
CAN module
not included
R5F563TBEDFP
R5F563TBEDFP#V0
PLQP0100KB-A
256 Kbytes
24 Kbytes
CAN module
not included
R5F563T6EDFM
R5F563T6EDFM#V0
PLQP0064KB-A
64 Kbytes
8 Kbytes
CAN module
not included
R5F563T5EDFM
R5F563T5EDFM#V0
PLQP0064KB-A
48 Kbytes
8 Kbytes
CAN module
not included
R5F563T4EDFM
R5F563T4EDFM#V0
PLQP0064KB-A
32 Kbytes
8 Kbytes
CAN module
not included
R5F563T6EDFL
R5F563T6EDFL#V0
PLQP0048KB-A
64 Kbytes
8 Kbytes
CAN module
not included
R5F563T5EDFL
R5F563T5EDFL#V0
PLQP0048KB-A
48 Kbytes
8 Kbytes
CAN module
not included
R5F563T4EDFL
R5F563T4EDFL#V0
PLQP0048KB-A
32 Kbytes
8 Kbytes
CAN module
not included
R5F563TEAGFB
R5F563TEAGFB#V1
PLQP0144KA-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TEAGFA
R5F563TEAGFA#V1
PLQP0120KA-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TEAGFH
R5F563TEAGFH#V1
PLQP0112JA-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TEAGFP
R5F563TEAGFP#V1
PLQP0100KB-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TCAGFB
R5F563TCAGFB#V1
PLQP0144KA-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TCAGFA
R5F563TCAGFA#V1
PLQP0120KA-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TCAGFH
R5F563TCAGFH#V1
PLQP0112JA-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TCAGFP
R5F563TCAGFP#V1
PLQP0100KB-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TBAGFB
R5F563TBAGFB#V1
PLQP0144KA-A
256 Kbytes
24 Kbytes
CAN module
included
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Option
Operating
Voltage
Operating
Temperature
VCC/
PLLVCC/
VCC_USB
2.7 to 3.6V
AVCC/
AVCC0 3.0
to 3.6V or
4.0 to 5.5V
-40 to +85°C
(D Version)
VCC/
PLLVCC
2.7 to 3.6V
AVCC0 3.0
to 3.6V
VCC/
PLLVCC
4.0 to 5.5V
VCC_USB
3.0 to 3.6V
AVCC/
AVCC0 4.0
to 5.5V
-40 to +105°C
(G Version)*1
Page 12 of 186
RX63T Group
Table 1.3
1. Overview
List of Products (4/4)
Group
Part No.
Order Part No.
Package
On-chip ROM
Capacity
On-chip RAM
Capacity
RX63T
R5F563TBAGFA
R5F563TBAGFA#V1
PLQP0120KA-A
256 Kbytes
24 Kbytes
CAN module
included
R5F563TBAGFH
R5F563TBAGFH#V1
PLQP0112JA-A
256 Kbytes
24 Kbytes
CAN module
included
R5F563TBAGFP
R5F563TBAGFP#V1
PLQP0100KB-A
256 Kbytes
24 Kbytes
CAN module
included
R5F563TEBGFB
R5F563TEBGFB#V1
PLQP0144KA-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TEBGFA
R5F563TEBGFA#V1
PLQP0120KA-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TEBGFH
R5F563TEBGFH#V1
PLQP0112JA-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TEBGFP
R5F563TEBGFP#V1
PLQP0100KB-A
512 Kbytes
48 Kbytes
CAN module
included
R5F563TCBGFB
R5F563TCBGFB#V1
PLQP0144KA-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TCBGFA
R5F563TCBGFA#V1
PLQP0120KA-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TCBGFH
R5F563TCBGFH#V1
PLQP0112JA-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TCBGFP
R5F563TCBGFP#V1
PLQP0100KB-A
384 Kbytes
32 Kbytes
CAN module
included
R5F563TBBGFB
R5F563TBBGFB#V1
PLQP0144KA-A
256 Kbytes
24 Kbytes
CAN module
included
R5F563TBBGFA
R5F563TBBGFA#V1
PLQP0120KA-A
256 Kbytes
24 Kbytes
CAN module
included
R5F563TBBGFH
R5F563TBBGFH#V1
PLQP0112JA-A
256 Kbytes
24 Kbytes
CAN module
included
R5F563TBBGFP
R5F563TBBGFP#V1
PLQP0100KB-A
256 Kbytes
24 Kbytes
CAN module
included
R5F563T6EGFM
R5F563T6EGFM#V0
PLQP0064KB-A
64 Kbytes
8 Kbytes
CAN module
not included
R5F563T5EGFM
R5F563T5EGFM#V0
PLQP0064KB-A
48 Kbytes
8 Kbytes
CAN module
not included
R5F563T4EGFM
R5F563T4EGFM#V0
PLQP0064KB-A
32 Kbytes
8 Kbytes
CAN module
not included
R5F563T6EGFL
R5F563T6EGFL#V0
PLQP0048KB-A
64 Kbytes
8 Kbytes
CAN module
not included
R5F563T5EGFL
R5F563T5EGFL#V0
PLQP0048KB-A
48 Kbytes
8 Kbytes
CAN module
not included
R5F563T4EGFL
R5F563T4EGFL#V0
PLQP0048KB-A
32 Kbytes
8 Kbytes
CAN module
not included
Option
Operating
Voltage
Operating
Temperature
VCC/
PLLVCC
4.0 to 5.5V
VCC_USB
3.0 to 3.6V
AVCC/
AVCC0 4.0
to 5.5V
-40 to +105°C
(G Version)*1
VCC/
PLLVCC/
VCC_USB
2.7 to 3.6V
AVCC/
AVCC0 3.0
to 3.6V or
4.0 to 5.5V
VCC/
PLLVCC
2.7 to 3.6V
AVCC0 3.0
to 3.6V
Note: • Orderable part numbers are current as of when this manual was published. Please make sure to refer to the relevant product
page on the Renesas website for the latest part numbers.
Note: • The products with the product ID code 1 (ex. R5F563TEADFB#V1) are the revised version to the specification constraints of
technical update TX-RX*-A84A / E described.
Note 1. Please contact Renesas Electronics sales office for derating of operation under Ta = +85°C to +105°C. Derating is the
systematic reduction of load for the sake of improved reliability.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 13 of 186
RX63T Group
R 5
F 5
1. Overview
6
3 T
E A D
F
B
#V
0
Product ID code
Form of packing/External pin surface finishing (lead-free)
#V: Tray/Sn (Tin) only
Package type, number of pins, and pin pitch
FB: LQFP/144/0.5
FA: LQFP/120/0.5
FH: LQFP/112/0.65
FP: LQFP/100/0.5
FM: LQFP/64/0.5
FL: LQFP/48/0.5
D: Operating temperature range (-40 to +85°C)
G: Operating temperature range (-40 to +105°C)
A: 5-V product, CAN module included
B: 3-V product, CAN module included
D: 5-V product, CAN module not included
E: 3-V product, CAN module not included
ROM and RAM data flash capacity
E: 512 Kbytes/48 Kbytes/32 Kbytes
C: 384 Kbytes/32 Kbytes/32 Kbytes
B: 256 Kbytes/24 Kbytes/32 Kbytes
6: 64 Kbytes/8 Kbytes/8 Kbytes
5: 48 Kbytes/8 Kbytes/8 Kbytes
4: 32 Kbytes/8 Kbytes/8 Kbytes
Group name
3T: RX63T Group
Series name
RX600 Series
Type of memory
F: Flash memory version
Renesas MCU
Renesas semiconductor product
Figure 1.1
How to Read the Product Part Number
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 14 of 186
RX63T Group
1.3
1. Overview
Block Diagram
Figure 1.2 shows a block diagram.
E2 DataFlash
WDTA
IWDTa
CRC
SCIc × 4 channels
SCId × 1 channels
USBa*1
RSPI x 2 channels
CAN (optional)
POE3
CMT × 2 channels (unit 0)
CMT × 2 channels (unit 1)
RIIC × 2 channels
MTU3
× 8ch
Internal peripheral buses 1 to 6
CAC
GPT
× 8ch
Sample-and-hold circuits for
the pin section × 3 channels
Window comparator
× 3 channels
Port 0
*1
12-bit ADC × 4 channels
(unit 0)
Port 1
Programmable gain amplifier
× 3 channels
Port 2
Port 3
Sample-and-hold circuits for the
pin section × 3 channels
Port 4
Window comparator × 3 channels
Port 5
ICUb
ROM
Port 6
MPU
Clock
generation
circuit
Internal main bus 1
RX CPU
Internal main bus 2
DTCa
Operand bus
Instruction bus
RAM
DOC
12-bit ADC x 8 channels*1
DMACA
× 4ch
12-bit ADC × 4 channels*1
(unit 1)
Port 7
Programmable gain amplifier
× 3 channels
Port 8
Sample-and-hold circuits for the
pin section × 3 channels
Window comparator × 3 channels
10-bit ADC × 20 channels*1
*1
10-bit DAC × 2 channels
Port B
Port C
Port D
Port E
Port F
BSC
ICUb:
Interrupt controller
DTCa:
Data transfer controller
DMACA:
DMA controller
WDTA:
Watchdog timer
IWDTa:
Independent watchdog timer
CRC:
CRC (cyclic redundancy check) calculator
SCIc, SCId: Serial communications interface
USBa:
USB 2.0 host/function module
RSPI:
Serial peripheral interface
Port 9
Port A
External bus
CAN:
GPT:
MTU3:
POE3:
CMT:
RIIC:
CAC:
DOC:
MPU:
Port G
CAN module
General PWM timer
Multi-function timer pulse unit 3
Port output enable 3
Compare match timer
I2C bus interface
Clock frequency accuracy measurement circuit
Data operating circuit
Memory protection unit
Note 1: Numbers of pins and availability of the USB2.0 host/function module, 12-bit A/D converter, 10-bit D/A converter,
and 10-bit D/A converter differ with the package.
Figure 1.2
Block Diagram
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 15 of 186
RX63T Group
1.4
1. Overview
Pin Functions
Table 1.4 lists the pin functions.
Table 1.4
Pin Functions (1/5)
Classifications
Pin Name
I/O
Description
Power supply
VCC
—
Power supply pin. Connect it to the system power supply. Connect
this pin to VSS via a 0.1-µF capacitor. The capacitor should be
placed close to the pin
VCL
—
Connect this pin to VSS via a 0.1-F capacitor. The capacitor
should be placed close to the pin
VSS
—
Ground pin. Connect it to the system power supply (0 V)
PLLVCC
—
Power supply pin. Connect it to the system power supply.
PLLVSS
—
Ground pin. Connect it to the system power supply (0 V)
XTAL
Output
EXTAL
Input
Pins for a crystal resonator. An external clock signal can be input
through the EXTAL pin
BCLK
Output
Outputs the external bus clock for external devices
Clock frequency accuracy
measurement
CACREF
Input
Input for the trigger signal in measuring accuracy of the clock
frequency
Operating mode control
MD
Input
Pin for setting the operating mode. The signal levels on these pins
must not be changed during operation
System control
RES#
Input
Reset signal input pin. This LSI enters the reset state when this
signal goes low
EMLE
Input
Input pin for the on-chip emulator enable signal. When the on-chip
emulator is used, this pin should be driven high. When not used, it
should be driven low
FINEC
Input
Fine interface clock pin
FINED
I/O
Fine interface pin
TRST#
Input
TMS
Input
On-chip emulator pins. When the EMLE pin is driven high, these
pins are dedicated for the on-chip emulator.
TDI
Input
TCK
Input
TDO
Output
TRCLK
Output
This pin outputs the clock for synchronization with the trace data
TRSYNC
Output
This pin indicates that output from the TRDATA0 to TRDATA3 pins
is valid
TRDATA0 to TRDATA3
Output
These pins output the trace information
Clock
On-chip emulator
Address bus
A0 to A19
Output
Output pins for the address
Data bus
D0 to D15
I/O
Input and output pins for the bidirectional data bus
Multiplexed bus
A0/D0 to A15/D15
I/O
Address/data multiplexed bus
Bus control
RD#
Output
Strobe signal which indicates that reading from the external bus
interface space is in progress
WR#
Output
Strobe signal which indicates that writing to the external bus
interface space is in progress, in 1-write strobe mode
WR0# to WR1#
Output
Strobe signals which indicate that either group of data bus pins (D7
to D0 and D15 to D8) is valid in writing to the external bus interface
space, in byte strobe mode
BC0# to BC1#
Output
Strobe signals which indicate that either group of data bus pins (D7
to D0 and D15 to D8) is valid in access to the external bus interface
space, in 1-write strobe mode
ALE
Output
Address latch signal when address/data multiplexed bus is selected
WAIT#
Input
Input pin for wait request signals in access to the external space
CS0# to CS3#
Output
Select signals for CS areas
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 16 of 186
RX63T Group
Table 1.4
1. Overview
Pin Functions (2/5)
Classifications
Pin Name
I/O
Description
Interrupt
NMI
Input
Non-maskable interrupt request pin
IRQ0 to IRQ7
Input
Maskable interrupt request pin
MTIOC0A, MTIOC0B
MTIOC0C, MTIOC0D
I/O
The TGRA0 to TGRD0 input capture input/output compare output/
PWM output pins
MTIOC1A, MTIOC1B
I/O
The TGRA1 and TGRB1 input capture input/output compare output/
PWM output pins
MTIOC2A, MTIOC2B
I/O
The TGRA2 and TGRB2 input capture input/output compare output/
PWM output pins
MTIOC3A, MTIOC3B
MTIOC3C, MTIOC3D
I/O
The TGRA3 to TGRD3 input capture input/output compare output/
PWM output pins
MTIOC4A, MTIOC4B
MTIOC4C, MTIOC4D
I/O
The TGRA4 to TGRD4 input capture input/output compare output/
PWM output pins
MTIC5U, MTIC5V
MTIC5W
Input
The TGRU5, TGRV5, and TGRW5 input capture input/dead time
compensation input pins
MTIOC6A, MTIOC6B
MTIOC6C, MTIOC6D
I/O
The TGRA6 to TGRD6 input capture input/output compare output/
PWM output pins
MTIOC7A, MTIOC7B
MTIOC7C, MTIOC7D
I/O
The TGRA7 to TGRD7 input capture input/output compare output/
PWM output pins
MTCLKA, MTCLKB
MTCLKC, MTCLKD
Input
Input pins for external clock
Port output enable 3
POE0#, POE4#
POE8#, POE10#
POE11#, POE12#
Input
Input pins for request signals to place the MTU/GPT large-current
pins in the high impedance state
General PWM timer
GTIOC0A, GTIOC0B
I/O
The GPT0.GTGRA and GPT0.GTGRB input capture input/output
compare output/PWM output pins.
GTIOC1A, GTIOC1B
I/O
The GPT1.GTGRA and GPT1.GTGRB input capture input/output
compare output/PWM output pins.
GTIOC2A, GTIOC2B
I/O
The GPT2.GTGRA and GPT2.GTGRB input capture input/output
compare output/PWM output pins.
GTIOC3A, GTIOC3B
I/O
The GPT3.GTGRA and GPT3.GTGRB input capture input/output
compare output/PWM output pins.
GTETRG0
Input
External trigger input pin for the GPT0 to GPT3
GTIOC4A, GTIOC4B
I/O
The GPT4.GTGRA and GPT4.GTGRB input capture input/output
compare output/PWM output pins.
GTIOC5A, GTIOC5B
I/O
The GPT5.GTGRA and GPT5.GTGRB input capture input/output
compare output/PWM output pins.
GTIOC6A, GTIOC6B
I/O
The GPT6.GTGRA and GPT6.GTGRB input capture input/output
compare output/PWM output pins.
GTIOC7A, GTIOC7B
I/O
The GPT7.GTGRA and GPT7.GTGRB input capture input/output
compare output/PWM output pins.
GTETRG1
Input
External trigger input pin for the GPT4 to GPT7
Multi-function timer pulse
unit 3
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 17 of 186
RX63T Group
Table 1.4
1. Overview
Pin Functions (3/5)
Classifications
Pin Name
I/O
Description
Serial communications
interface (SCIc)
Asynchronous mode/clock synchronous mode
SCK0, SCK1, SCK2, SCK3
I/O
Input/output pins for clock signals.
RXD0, RXD1, RXD2, RXD3
Input
Input pins for data reception.
TXD0, TXD1, TXD2, TXD3
Output
Output pins for data transmission.
CTS0#, CTS1#, CTS2#, CTS3#
Input
Transmit/receive start control input pins
RTS0#, RTS1#, RTS2#, RTS3#
Output
Transmit/receive start control output pins
SSCL0, SSCL1, SSCL2,
SSCL3
I/O
Input/output pins for the I2C clock
SSDA0, SSDA1, SSDA2,
SSDA3
I/O
Input/output pins for the I2C data
SCK0, SCK1, SCK2, SCK3
I/O
Input/output pins for the clock
SMISO0, SMISO1,
SMISO2, SMISO3
I/O
Input/output pins for slave transmit data.
SMOSI0, SMOSI1,
SMOSI2, SMOSI3
I/O
Input/output pins for master transmit data.
SS0#, SS1#, SS2#, SS3#
Input
Input pins for chip select signals
Simple
I 2C
mode
Simple SPI mode
Serial communications
interface (SCId)
Asynchronous mode/clock synchronous mode
SCK12
I/O
Input/output pin for clock signals.
RXD12
Input
Input pin for data reception.
TXD12
Output
Output pin for data transmission.
CTS12#
Input
Transmit/receive start control input pins
RTS12#
Output
Transmit/receive start control output pins
SSCL12
I/O
Input/output pins for the I2C clock
SSDA12
I/O
Input/output pins for the I2C data
Simple I2C mode
Simple SPI mode
SCK12
I/O
Input/output pins for the clock
SMISO12
I/O
Input/output pins for slave transmit data.
SMOSI12
I/O
Input/output pins for master transmit data.
SS12#
Input
Input pins for chip select signals
Input
Input pin for receive data
Extended serial mode
RXDX12
I2C bus interface
TXDX12
Output
Output pin for transmit data
SIOX12
I/O
Input/output pin for transfer data
SCL, SCL0, SCL1
I/O
Clock input/output pin. N-channel open drain can directly drive
buses.
SDA, SDA0, SDA1
I/O
Data input/output pin. N-channel open drain can directly drive
buses.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 18 of 186
RX63T Group
Table 1.4
1. Overview
Pin Functions (4/5)
Classifications
USB 2.0 host/function
module
CAN module
Serial peripheral interface
Pin Name
I/O
Description
VCC_USB
Input
Power supply pin for USB
VSS_USB
Input
Ground pin for USB
USB0_DP
I/O
USB internal transceiver D + input and output pins
USB0_DM
I/O
USB internal transceiver D - input and output pins
USB0_EXICEN
Output
Low power control signal for OTG chip
USB0_VBUSEN
Output
Supply enable signal of VBUS (5 V) to OTG chip
USB0_ID
Input
Mini AB connector ID input pin for use in OTG operation
USB0_DPRPD
Output
D+ signal pull-down control pin for use during host operation
USB0_DRPD
Output
D- signal pull-down control pin for use during host operation
USB0_DPUPE
Output
D+ signal pull-up control pin for use during function operation
USB0_VBUS
Input
Pin for monitoring USB cable connection
USB0_OVRCURA,
USB0_OVRCURB
Input
Pin for detecting external over current
CRX1
Input
Input pins
CTX1
Output
Output pins
RSPCKA, RSPCKB
I/O
Clock input/output pins
MOSIA, MOSIB
I/O
Inputs or outputs data output from the master
MISOA, MISOB
I/O
Inputs or outputs data output from the slave
SSLA0, SSLB0
I/O
Input or output pins for slave selection
SSLA1 to SSLA3
SSLB1 to SSLB3
Output
Output pins for slave selection
AN000 to AN007
AN100 to AN103
Input
Input pins for the analog signals to be processed by the A/D
converter
ADTRG0#, ADTRG1#
Input
Input pins for the external trigger signals that start the A/D
conversion
CVREFH
Input
Input pin for the high-level reference voltage to the comparator
CVREFL
Input
Input pin for the low-level reference voltage to the comparator
AN0 to AN19
Input
Input pins for the analog signals to be processed by the 10-bit A/D
converter
ADTRG#
Input
Input pins for the external trigger signals that start the A/D
conversion
D/A converter
DA0, DA1
Output
Output pins for the analog signals to be processed by the 10-bit A/D
converter
Analog power supply
AVCC0
—
Analog voltage supply pin for the 12-bit A/D converter. Connect this
pin to VCC if the 12-bit A/D converter is not to be used
AVSS0
—
Analog ground pin for the 12-bit A/D converter. Connect this pin to
VSS if the 12-bit A/D converter is not to be used
VREFH0
—
Reference voltage supply pin for the 12-bit A/D converter. Connect
this pin to VCC if the 12-bit A/D converter is not to be used
VREFL0
—
Reference ground pin for the 12-bit A/D converter. Connect this pin
to VSS if the 12-bit A/D converter is not to be used
AVCC
—
Analog voltage supply pin for the 10-bit A/D converter and the 10-bit
D/A converter. Connect this pin to the power supply of the system if
the A/D converter and the D/A converter are not to be used.
AVSS
—
Ground pin for the 10-bit A/D converter and 10-bit D/A converter.
Connect this pin to the power-supply ground for the system (0 V).
—
Reference-voltage input pin for the 10-bit A/D converter and the 10bit D/A converter. Connect this pin to the power supply for the
system if the A/D converter and the D/A converter are not to be
used.
12-bit A/D converter
10-bit A/D converter
VREF
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 19 of 186
RX63T Group
Table 1.4
1. Overview
Pin Functions (5/5)
Classifications
Pin Name
I/O
Description
I/O ports
P00 to P05
I/O
6-bit input/output pins
P10 to P14
I/O
5-bit input/output pins
P20 to P26
I/O
7-bit input/output pins
P30 to P35
I/O
6-bit input/output pins
P40 to P47
Input
8-bit input pins
P50 to P57
Input
8-bit input pins
P60 to P65
Input
6-bit input pins
P70 to P76
I/O
7-bit input/output pins
P80 to P82
I/O
3-bit input/output pins
P90 to P96
I/O
7-bit input/output pins
PA0 to PA6
I/O
7-bit input/output pins
PB0 to PB7
I/O
8-bit input/output pins
PC0 to PC5
Input
6-bit input pins
PD0 to PD7
I/O
8-bit input/output pins
PE0, PE1, PE3 to PE5
I/O
6-bit input/output pins
PE2
Input
1-bit input pin
PF0 to PF4
I/O
5-bit input/output pins
PG0 to PG6
I/O
7-bit input/output pins
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 20 of 186
RX63T Group
1.5
1. Overview
Pin Assignments
P24
P25
P26
P30
VSS
P31
VCC
P32
P33
P70
P71
P72
P73
P74
P75
P76
PG0
PG1
PG2
91
90
89
88
87
85
83
81
79
76
75
74
73
P23
92
77
P21
P22
94
78
PC5
P20
96
80
PC4
97
82
P64
P65
99
84
PC3
100
86
PC2
101
93
AVCC
102
95
AVSS
VREF
104
98
PC0
PC1
106
103
P63
107
105
P62
108
Figure 1.3 to Figure 1.8 show the pin assignments. Table 1.5 to Table 1.10 show the lists of pins and pin functions.
P61
109
72
PG3
P60
110
71
PG4
P57
111
70
PG5
P56
112
69
P90
P55
113
68
P54
114
67
P91
P92
P53
P52
115
66
P93
116
65
P94
P51
117
64
P95
P50
118
63
VSS
P47
119
62
PG6
P46
120
61
P96
P45
121
60
VCC
P44
122
59
P43
123
58
P34
P35
P42
124
P41
P40
125
AVCC0
127
VREFH0
128
VREFL0
129
AVSS0
130
P82
P81
RX63T Group
PLQP0144KA-A
(144-Pin LQFP)
(Top View)
57
PA2
54
PA3
53
PA4
52
PA5
51
PA6
131
50
PB0
132
49
PB1
VSS
133
48
P80
134
47
PB2
PB3
P12
135
46
P11
136
45
TDO
TCK
P10
137
44
TDI
P05
138
43
PLLVSS
VCC
P04
139
42
PB4
140
41
PLLVCC
USB0_DPUPE
VSS_USB
USB0_DM
141
40
142
39
143
38
PB5
PB6
PB7
USB0_DP
144
37
PF0
11
12
13
15
16
17
18
19
20
21
22
23
24
25
27
28
29
30
31
33
34
35
36
PE4
PE3
P14
VCC
P13
RES#
XTAL
VSS
EXTAL
VCC
PE2
PE1
PE0
PD7
PD6
PD5
VSS
PD4
PD3
PD2
PD1
PD0
PF4
PF3
PF2
PF1
10
9
P00
MD
8
5
P02
VSS
7
4
P03
P01
VCL
3
EMLE
6
2
1
PE5
VCC_USB
32
55
126
26
PA0
PA1
14
56
Note: • This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.5, List of Pins and Pin Functions (144-Pin LQFP).
Figure 1.3
Pin Assignment (144-Pin LQFP)
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 21 of 186
VCC
P32
P33
P70
P71
P72
P73
P74
P75
P76
PG0
PG1
PG2
73
71
69
67
64
63
62
61
VSS
P31
75
65
P30
76
66
P26
77
68
P25
78
70
P24
79
72
P23
80
74
P21
P22
81
82
83
P64
P65
P20
85
84
AVCC
86
87
P63
AVSS
VREF
88
P62
89
1. Overview
90
RX63T Group
P61
91
60
PG3
P60
P55
92
59
PG4
93
58
PG5
P54
94
57
P90
P53
P52
95
56
96
55
P91
P92
P51
97
54
P93
P50
98
53
P94
P47
99
52
P95
P46
100
51
VSS
P45
101
50
PG6
P44
102
49
P96
P43
103
48
VCC
P42
104
47
P41
P40
105
46
PA0
PA1
45
PA2
AVCC0
107
44
PA3
VREFH0
108
43
PA4
VREFL0
109
42
PA5
AVSS0
110
41
PB0
P82
P81
111
40
PB1
112
39
P80
113
38
PB2
PB3
P12
114
37
PLLVSS
P11
115
36
PB4
P10
116
35
PLLVCC
USB0_DPUPE
VSS_USB
USB0_DM
117
34
118
33
119
32
PB5
PB6
PB7
USB0_DP
120
31
PF0
RX63T Group
PLQP0120KA-A
(120-Pin LQFP)
(Top View)
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PE3
P13
RES#
XTAL
VSS
EXTAL
VCC
PE2
PE1
PE0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PF3
PF2
PF1
5
P01
VCL
PE4
4
VSS
7
3
EMLE
P00
MD
2
PE5
6
1
VCC_USB
106
Note: • This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.6, List of Pins and Pin Functions (120-Pin LQFP).
Figure 1.4
Pin Assignment (120-Pin LQFP)
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 22 of 186
P76
PG0
PG1
PG2
60
59
58
57
P75
61
P73
P74
62
63
P71
P72
64
65
P33
P70
66
67
VSS
P31
71
VCC
P32
P30
72
68
P24
73
69
P23
74
70
P21
P22
75
76
77
P64
P65
P20
79
78
AVCC
80
81
P63
AVSS
VREF
82
P62
83
1. Overview
84
RX63T Group
P61
85
56
PG3
P60
P55
86
55
PG4
87
54
PG5
P54
88
53
P90
P53
P52
89
52
90
51
P91
P92
P51
91
50
P93
P50
92
49
P94
P47
93
48
P95
P46
94
47
VSS
P45
95
46
P96
P44
96
45
VCC
P43
97
44
P42
98
43
PA0
PA1
P41
P40
42
PA2
100
41
PA3
AVCC0
101
40
PA4
VREFH0
102
39
PA5
VREFL0
103
38
PB0
AVSS0
104
37
PB1
P82
P81
105
36
106
35
PB2
PB3
P80
107
34
PLLVSS
P12
108
33
PB4
P11
109
32
PLLVCC
P10
110
31
P05
P04
111
30
112
29
PB5
PB6
PB7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
PE4
PE3
RES#
XTAL
VSS
EXTAL
VCC
PE2
PE1
PE0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PF4
PF3
PF2
7
4
P01
VCL
6
3
VSS
P00
MD
2
5
1
PE5
EMLE
99
28
RX63T Group
PLQP0112JA-A
(112-Pin LQFP)
(Top View)
Note: • This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.7, List of Pins and Pin Functions (112-Pin LQFP).
Figure 1.5
Pin Assignment (112-Pin LQFP)
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 23 of 186
P75
P76
51
52
P73
P74
53
54
P71
P72
55
56
P33
P70
57
58
VCC
P32
VSS
P31
62
59
P30
63
60
P24
64
61
P23
65
P21
P22
66
67
68
AVCC
P64
P65
P20
69
70
71
72
P63
AVSS
VREF
73
P62
74
1. Overview
75
RX63T Group
P61
76
50
P90
P60
P55
77
49
78
48
P91
P92
P54
79
47
P93
P53
P52
80
46
P94
81
45
P95
P51
82
44
VSS
P50
83
43
P96
P47
84
42
VCC
P46
85
41
P45
86
40
PA0
PA1
P44
87
39
PA2
P43
88
38
PA3
P42
89
37
PA4
P41
P40
90
36
PA5
35
PB0
AVCC0
92
34
PB1
VREFH0
93
33
VREFL0
94
32
PB2
PB3
AVSS0
95
31
PLLVSS
P82
P81
96
30
PB4
97
29
PLLVCC
P80
P11
98
28
99
27
P10
100
26
PB5
PB6
PB7
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PE4
PE3
RES#
XTAL
VSS
EXTAL
VCC
PE2
PE1
PE0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
4
P01
VCL
6
3
VSS
P00
MD
2
5
1
PE5
EMLE
91
25
RX63T Group
PLQP0100KB-A
(100-Pin LQFP)
(Top View)
Note: • This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.8, List of Pins and Pin Functions (100-Pin LQFP).
Figure 1.6
Pin Assignment (100-Pin LQFP)
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 24 of 186
P33
P70
P71
P72
P73
P74
P75
P76
39
38
37
36
35
34
33
P31
40
VSS
43
VCC
P30
44
P32
P24
45
41
P23
46
42
P22
47
1. Overview
48
RX63T Group
P47
49
32
P91
P46
50
31
P92
P45
51
30
P93
P44
52
29
P94
P43
53
28
PA2
P42
54
27
PA3
P41
55
26
PB0
P40
56
25
PB1
AVCC0
57
24
PB2
VREFH0
58
23
PB3
VREFL0
59
22
VSS
AVSS0
60
21
PB4
P11
61
20
VCC
P10
62
19
PB5
PA5
63
18
PB6
PA4
64
17
PB7
12
13
14
15
16
PD6
PD5
PD4
PD3
8
VSS
PD7
7
XTAL
11
6
RES#
PE2
5
MD
9
4
P01
10
3
VCL
VCC
2
P00
EXTAL
1
EMLE
RX63T Group
PLQP0064KB-A
(64-Pin LQFP)
(Top View)
Note: • This figure indicates the power supply pins and I /O port pins. For the pin configuration,
see Table 1.9, List of Pins and Pin Functions (64-Pin LQFP).
Figure 1.7
Pin Assignment (64-Pin LQFP)
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 25 of 186
P30
P70
P71
P72
P73
P74
P75
30
29
28
27
26
25
VSS
VCC
P24
33
31
P23
34
32
P22
35
1. Overview
36
RX63T Group
P47
37
24
P76
P44
38
23
PA2
P43
39
22
PA3
P42
40
21
PB0
P41
41
20
PB1
P40
42
19
PB2
AVCC0
43
18
PB3
VREFH0
44
17
VSS
VREFL0
45
16
PB4
AVSS0
46
15
VCC
VCL
47
14
PB5
EMLE
48
13
PB6
9
10
11
12
PD5
PD4
PD3
6
VCC
PD6
5
EXTAL
8
4
VSS
7
3
XTAL
PE2
2
PD7
1
MD
RES#
RX63T Group
PLQP0048KB-A
(48-Pin LQFP)
(Top View)
Note: • This figure indicates the power supply pins and I /O port pins. For the pin configuration,
see Table 1.10, List of Pins and Pin Functions (48-Pin LQFP).
Figure 1.8
Pin Assignment (48-Pin LQFP)
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 26 of 186
RX63T Group
Table 1.5
Pin Number
1. Overview
List of Pins and Pin Functions (144-Pin LQFP) (1/4)
144-Pin
LQFP
Power Supply
Clock System
Control
1
VCC_USB
2
I/O Port
Bus
PE5
BCLK
Timer
(MTU3, GPT, POE3, CAC)
Communications
(SCIc, SCId, RSPI, RIIC,
CAN, USB)
Interrupt
USB0_VBUS
IRQ0
IRQ7
3
EMLE
4
TRSYNC
P03
RXD2/SMISO2/SSCL2
5
TRDATA3
P02
TXD2/SMOSI2/SSDA2
6
VSS
7
8
RD#
CTS0#/RTS0#/SS0#/
USB0_DRPD
P00
CS1#
CACREF
PE4
A10
POE10#/MTCLKC
PE3
A11
POE11#/MTCLKD
VCL
9
10
P01
MD/FINED
11
12
13
TRDATA2
14
VCC
15
16
RES#
17
XTAL
18
VSS
19
EXTAL
20
VCC
IRQ1
IRQ2-DS
P14
SCK2
P13
CTS2#/RTS2#/SS2#/
USB0_VBUSEN
21
PE2
22
PE1
WR0#/WR#
CTS12#/RTS12#/
SS12#/SSLA3/SSLB3/
USB0_OVRCURA
23
PE0
WR1#/BC1#/
WAIT#
SSLA2/SSLB2/CRX1/
USB0_OVRCURB
24
PD7
POE10#
NMI
GTIOC0A
CTS0#/RTS0#/SS0#/
SSLA1/SSLB1/CTX1
25
PD6
GTIOC0B
SSLA0/SSLB0
26
PD5
GTIOC1A
RXD1/SMISO1/SSCL1
28
PD4
GTIOC1B
SCK1
29
PD3
GTIOC2A
TXD1/SMOSI1/SSDA1
30
PD2
CS2#
GTIOC2B
MOSIA/MOSIB/
USB0_ID
31
PD1
CS0#
GTIOC3A
MISOA/MISOB/
USB0_EXICEN
32
PD0
A12
GTIOC3B
RSPCKA/RSPCKB
33
PF4
CS3#
34
PF3
35
PF2
27
IRQ7
IRQ6
VSS
36
TRST#
PF1
37
TMS
PF0
38
S12ADB,
AD, DA
PB7
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
TXD1/SMOSI1/SSDA1
CS1#
RXD1/SMISO1/SSCL1
A19
SCK12
IRQ5
Page 27 of 186
RX63T Group
Table 1.5
Pin Number
144-Pin
LQFP
1. Overview
List of Pins and Pin Functions (144-Pin LQFP) (2/4)
Power Supply
Clock System
Control
Timer
(MTU3, GPT, POE3, CAC)
Communications
(SCIc, SCId, RSPI, RIIC,
CAN, USB)
I/O Port
Bus
39
PB6
A18
RXD12/SMISO12/
SSCL12/RXDX12/
CRX1
40
PB5
A17
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/
CTX1
PB4
A16
41
IRQ2
PLLVCC
42
43
PLLVSS
44
TDI
45
TCK/FINEC
46
TDO
POE8#/
GTETRG0
IRQ3-DS
RXD1*1
TXD1*1
47
PB3
MTIOC0A/CACREF
SCK0
48
PB2
MTIOC0B
TXD0/SMOSI0/
SSDA0/SDA0
49
PB1
MTIOC0C
RXD0/SMISO0/
SSCL0/SCL0
50
PB0
A14
MTIOC0D
MOSIA/MOSIB
PA6
CS3#
51
S12ADB,
AD, DA
Interrupt
TRDATA1
A15
IRQ4
CTS3#/RTS3#/SS3#
52
PA5
MTIOC1A
RXD0/SMISO0/
SSCL0/
MISOA/MISOB
ADTRG1#
53
PA4
MTIOC1B
TXD0/SMOSI0/
SSDA0/SMOSI0/
RSPCKA/RSPCKB
ADTRG0#
54
PA3
MTIOC2A
SCK0/SSLA0/SSLB0
55
PA2
MTIOC2B
RXD2/SMISO2/
SSCL2/
SSLA1/SSLB1
56
PA1
MTIOC6A
TXD2/SMOSI2/
SSDA2/SMOSI2/
SSLA2/SSLB2
57
PA0
MTIOC6C
SCK2/SSLA3/SSLB3
GTETRG1
RXD3/SMISO3/SSCL3
IRQ3
POE4#
RXD1/SMISO1/SSCL1
IRQ4-DS
58
TRDATA0
P35
59
TRCLK
P34
60
VCC
TXD3/SMOSI3/SSDA3
61
P96
A13
62
PG6
CS2#
63
SCK1
VSS
64
P95
MTIOC6B/GTIOC4A
TXD1/SMOSI1/SSDA1
65
P94
MTIOC7A/GTIOC5A
CTS1#/RTS1#/SS1#
66
P93
MTIOC7B/GTIOC6A
CTS2#/RTS2#/SS2#
67
P92
MTIOC6D/GTIOC4B
68
P91
MTIOC7C/GTIOC5B
69
P90
MTIOC7D/GTIOC6B
70
PG5
POE12#
SCK3
71
PG4
GTIOC6B
RXD3/SMISO3/SSCL3
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
ADTRG#
IRQ6
Page 28 of 186
RX63T Group
Table 1.5
Pin Number
144-Pin
LQFP
1. Overview
List of Pins and Pin Functions (144-Pin LQFP) (3/4)
Power Supply
Clock System
Control
72
I/O Port
Bus
PG3
Timer
(MTU3, GPT, POE3, CAC)
Communications
(SCIc, SCId, RSPI, RIIC,
CAN, USB)
GTIOC6A
TXD3/SMOSI3/SSDA3
S12ADB,
AD, DA
Interrupt
73
PG2
SCK2
IRQ2
74
PG1
GTIOC7B
RXD2/SMISO2/SSCL2
IRQ1
75
PG0
GTIOC7A
TXD2/SMOSI2/SSDA2
IRQ0
76
P76
D0/[A0/D0]
MTIOC4D/GTIOC2B
77
P75
D1/[A1/D1]
MTIOC4C/GTIOC1B
78
P74
D2/[A2/D2]
MTIOC3D/GTIOC0B
79
P73
D3/[A3/D3]
MTIOC4B/GTIOC2A
80
P72
D4/[A4/D4]
MTIOC4A/GTIOC1A
81
P71
D5/[A5/D5]
MTIOC3B/GTIOC0A
82
P70
D6/[A6/D6]
POE0#
CTS1#/RTS1#/SS1#
IRQ5-DS
83
P33
D7/[A7/D7]
MTIOC3A/MTCLKA
SSLA3/SSLB3
84
P32
D8/[A8/D8]
MTIOC3C/MTCLKB
SSLA2/SSLB2
P31
D9/[A9/D9]
MTIOC0A/MTCLKC
SSLA1/SSLB1
88
P30
D10/[A10/
D10]
MTIOC0B/MTCLKD
SCK0/SSLA0/SSLB0
89
P26
CS0#
TXD1/SMOSI1/
SSDA1/SDA1
90
P25
CS1#
SCK1/SCL1
91
P24
D11/[A11/D11]
CTS0#/RTS0#/SS0#/
RSPCKA/RSPCKB
92
P23
D12/[A12/
D12]
93
P22
D13/[A13/
D13]
94
P21
D14/[A14/
D14]
MTCLKA
IRQ6-DS
ADTRG1#
95
P20
D15/[A15/
D15]
MTCLKB
IRQ7-DS
ADTRG0#
96
PC5
AN19
97
PC4
AN18
98
P65
A0/BC0#
AN5
99
P64
A1
AN4
100
PC3
AN17
PC2
AN16
105
PC1
AN15
106
PC0
107
P63
A2
AN3
108
P62
A3
AN2
109
P61
A4
AN1
85
VCC
86
87
VSS
101
102
AVCC
103
VREF
104
AVSS
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
CACREF
IRQ4
TXD0/SMOSI0/
SSDA0/MOSIA/
MOSIB/CTX1
RXD0/SMISO0/
SSCL0/MISOA/
MISOB/CRX1
ADTRG#
AN14
Page 29 of 186
RX63T Group
Table 1.5
Pin Number
144-Pin
LQFP
1. Overview
List of Pins and Pin Functions (144-Pin LQFP) (4/4)
Power Supply
Clock System
Control
110
I/O Port
Bus
P60
A5
Timer
(MTU3, GPT, POE3, CAC)
Communications
(SCIc, SCId, RSPI, RIIC,
CAN, USB)
S12ADB,
AD, DA
Interrupt
AN0
111
P57
AN13
112
P56
AN12
113
P55
AN11/DA1
114
P54
AN10/
DA0
115
P53
A6
AN9
116
P52
A7
AN8
117
P51
AN7
118
P50
AN6
119
P47
AN103/
CVREFH
120
P46
AN102
121
P45
AN101
122
P44
AN100
123
P43
AN003/
CVREFL
124
P42
AN002
125
P41
AN001
126
P40
AN000
127
AVCC0
128
VREFH0
129
VREFL0
130
AVSS0
131
P82
WAIT#
MTIC5U
SCK12
132
P81
A8
MTIC5V
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12
134
P80
A9
MTIC5W
RXD12/SMISO12/
SSCL12/RXDX12
135
P12
CS3#
136
P11
ALE
137
P10
138
P05
133
139
VSS
IRQ5
USB0_DPRPD
MTCLKC
IRQ1-DS
MTCLKD
IRQ0-DS
CS2#/WAIT#
VCC
140
P04
141
142
IRQ3
USB0_DPUPE
VSS_USB
143
USB0_DM
144
USB0_DP
Note 1. Available for use as SCI pin only in boot mode.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 30 of 186
RX63T Group
Table 1.6
Pin Number
1. Overview
List of Pins and Pin Functions (120-Pin LQFP) (1/4)
120-Pin
LQFP
Power Supply
Clock System
Control
1
VCC_USB
Timer
(MTU3, GPT, POE3, CAC)
Communications
(SCIc, SCId, RSPI, RIIC,
CAN, USB)
Interrupt
IRQ0
I/O Port
Bus
PE5
BCLK
USB0_VBUS
P01
RD#
CTS0#/RTS0#/SS0#/
USB0_DRPD
P00
CS1#
CACREF
9
PE4
A10
POE10#/MTCLKC
10
PE3
A11
POE11#/MTCLKD
11
P13
2
3
EMLE
4
VSS
5
6
VCL
7
8
MD/FINED
12
RES#
13
XTAL
14
VSS
15
EXTAL
16
VCC
IRQ1
IRQ2-DS
CTS2#/RTS2#/SS2#/
USB0_VBUSEN
17
PE2
18
PE1
WR0#/WR#
CTS12#/RTS12#/
SS12#/SSLA3/SSLB3/
USB0_OVRCURA
19
PE0
WR1#/BC1#/
WAIT#
SSLA2/SSLB2/CRX1/
USB0_OVRCURB
POE10#
NMI
20
TRST#
PD7
GTIOC0A
CTS0#/RTS0#/SS0#/
SSLA1/SSLB1/CTX1
21
TMS
PD6
GTIOC0B
SSLA0/SSLB0
22
TDI
PD5
GTIOC1A
RXD1/SMISO1/SSCL1
23
TCK/FINEC
PD4
GTIOC1B
SCK1
24
TDO
PD3
GTIOC2A
TXD1/SMOSI1/SSDA1
25
PD2
CS2#
GTIOC2B
MOSIA/MOSIB/
USB0_ID
26
PD1
CS0#
GTIOC3A
MISOA/MISOB/
USB0_EXICEN
27
PD0
A12
GTIOC3B
RSPCKA/RSPCKB
28
PF3
29
PF2
30
PF1
31
PF0
32
RXD1/SMISO1/SSCL1
PB7
A19
SCK12
33
PB6
A18
RXD12/SMISO12/
SSCL12/RXDX12/
CRX1
34
PB5
A17
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/CTX1
PB4
A16
36
IRQ7
IRQ6
TXD1/SMOSI1/SSDA1
CS1#
35
S12ADB,
AD, DA
IRQ5
IRQ2
PLLVCC
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
POE8#/GTETRG0
IRQ3-DS
Page 31 of 186
RX63T Group
Table 1.6
Pin Number
1. Overview
List of Pins and Pin Functions (120-Pin LQFP) (2/4)
120-Pin
LQFP
Power Supply
Clock System
Control
37
PLLVSS
Timer
(MTU3, GPT, POE3, CAC)
Communications
(SCIc, SCId, RSPI, RIIC,
CAN, USB)
I/O Port
Bus
38
PB3
A15
MTIOC0A/CACREF
SCK0
39
PB2
MTIOC0B
TXD0/SMOSI0/
SSDA0/SDA0
40
PB1
MTIOC0C
RXD0/SMISO0/
SSCL0/SCL0
A14
S12ADB,
AD, DA
Interrupt
IRQ4
41
PB0
MTIOC0D
MOSIA/MOSIB
42
PA5
MTIOC1A
RXD0/SMISO0/
SSCL0/
MISOA/MISOB
ADTRG1#
43
PA4
MTIOC1B
TXD0/SMOSI0/
SSDA0/RSPCKA/
RSPCKB
ADTRG0#
44
PA3
MTIOC2A
SCK0/SSLA0/SSLB0
45
PA2
MTIOC2B
RXD2/SMISO2/
SSCL2/
SSLA1/SSLB1
46
PA1
MTIOC6A
TXD2/SMOSI2/
SSDA2/SSLA2/SSLB2
47
PA0
MTIOC6C
SCK2/SSLA3/SSLB3
POE4#
RXD1/SMISO1/SSCL1
48
VCC
49
P96
A13
50
PG6
CS2#
51
SCK1
VSS
52
P95
MTIOC6B/GTIOC4A
TXD1/SMOSI1/SSDA1
53
P94
MTIOC7A/GTIOC5A
CTS1#/RTS1#/SS1#
54
P93
MTIOC7B/GTIOC6A
CTS2#/RTS2#/SS2#
55
P92
MTIOC6D/GTIOC4B
56
P91
MTIOC7C/GTIOC5B
57
P90
MTIOC7D/GTIOC6B
58
TRCLK
PG5
POE12#
SCK3
59
TRDATA3
PG4
GTIOC6B
RXD3/SMISO3/SSCL3
60
TRDATA2
PG3
GTIOC6A
61
TRDATA1
PG2
62
TRDATA0
PG1
63
TRSYNC
PG0
IRQ6
TXD3/SMOSI3/SSDA3
IRQ2
GTIOC7B
RXD2/SMISO2/SSCL2
IRQ1
GTIOC7A
TXD2/SMOSI2/SSDA2
IRQ0
IRQ5-DS
P76
D0/[A0/D0]
MTIOC4D/GTIOC2B
65
P75
D1/[A1/D1]
MTIOC4C/GTIOC1B
66
P74
D2/[A2/D2]
MTIOC3D/GTIOC0B
67
P73
D3/[A3/D3]
MTIOC4B/GTIOC2A
68
P72
D4/[A4/D4]
MTIOC4A/GTIOC1A
69
P71
D5/[A5/D5]
MTIOC3B/GTIOC0A
70
P70
D6/[A6/D6]
POE0#
CTS1#/RTS1#/SS1#
71
P33
D7/[A7/D7]
MTIOC3A/MTCLKA
SSLA3/SSLB3
72
P32
D8/[A8/D8]
MTIOC3C/MTCLKB
SSLA2/SSLB2
P31
D9/[A9/D9]
MTIOC0A/MTCLKC
SSLA1/SSLB1
74
ADTRG#
SCK2
64
73
IRQ4-DS
VCC
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 32 of 186
RX63T Group
Table 1.6
Pin Number
1. Overview
List of Pins and Pin Functions (120-Pin LQFP) (3/4)
120-Pin
LQFP
Power Supply
Clock System
Control
75
VSS
Timer
(MTU3, GPT, POE3, CAC)
Communications
(SCIc, SCId, RSPI, RIIC,
CAN, USB)
MTIOC0B/MTCLKD
SCK0/SSLA0/SSLB0
S12ADB,
AD, DA
I/O Port
Bus
76
P30
D10/[A10/
D10]
77
P26
CS0#
TXD1/SMOSI1/
SSDA1/SDA1
78
P25
CS1#
SCK1/SCL1
79
P24
D11/[A11/D11]
CTS0#/RTS0#/SS0#/
RSPCKA/RSPCKB
80
P23
D12/[A12/
D12]
81
P22
D13/[A13/
D13]
82
P21
D14/[A14/
D14]
MTCLKA
IRQ6-DS
ADTRG1#
83
P20
D15/[A15/
D15]
MTCLKB
IRQ7-DS
ADTRG0#
84
P65
A0/BC0#
AN5
85
P64
A1
AN4
89
P63
A2
AN3
90
P62
A3
AN2
91
P61
A4
AN1
92
P60
A5
AN0
93
P55
AN11/DA1
94
P54
AN10/
DA0
95
P53
A6
AN9
96
P52
A7
AN8
97
P51
AN7
98
P50
AN6
99
P47
AN103/
CVREFH
100
P46
AN102
101
P45
AN101
102
P44
AN100
103
P43
AN003/
CVREFL
104
P42
AN002
105
P41
AN001
106
P40
AN000
86
AVCC
87
VREF
88
AVSS
107
AVCC0
108
VREFH0
109
VREFL0
110
AVSS0
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
CACREF
Interrupt
IRQ4
TXD0/SMOSI0/
SSDA0/MOSIA/
MOSIB/CTX1
RXD0/SMISO0/
SSCL0/MISOA/
MISOB/CRX1
ADTRG#
Page 33 of 186
RX63T Group
Table 1.6
Pin Number
120-Pin
LQFP
1. Overview
List of Pins and Pin Functions (120-Pin LQFP) (4/4)
Power Supply
Clock System
Control
Communications
(SCIc, SCId, RSPI, RIIC,
CAN, USB)
Interrupt
IRQ3
I/O Port
Bus
Timer
(MTU3, GPT, POE3, CAC)
111
P82
WAIT#
MTIC5U
SCK12
112
P81
A8
MTIC5V
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12
113
P80
A9
MTIC5W
RXD12/SMISO12/
SSCL12/RXDX12
114
P12
CS3#
115
P11
ALE
116
P10
117
118
S12ADB,
AD, DA
IRQ5
USB0_DPRPD
MTCLKC
IRQ1-DS
MTCLKD
IRQ0-DS
USB0_DPUPE
VSS_USB
119
USB0_DM
120
USB0_DP
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 34 of 186
RX63T Group
Table 1.7
Pin Number
112-Pin
LQFP
1. Overview
List of Pins and Pin Functions (112-Pin LQFP) (1/4)
Power Supply
Clock System
Control
Timer
(MTU3, GPT, POE3, CAC)
Communications
(SCIc, SCId, RSPI, RIIC,
CAN)
S12ADB,
AD, DA
I/O Port
Bus
PE5
BCLK
P01
RD#
P00
CS1#
CACREF
8
PE4
A10
POE10#/MTCLKC
IRQ1
9
PE3
A11
POE11#/MTCLKD
IRQ2-DS
POE10#
NMI
1
2
EMLE
3
VSS
4
5
IRQ0
CTS0#/RTS0#/SS0#
VCL
6
7
MD/FINED
10
RES#
11
XTAL
12
VSS
13
EXTAL
14
VCC
15
PE2
16
PE1
WR0#/WR#
CTS12#/RTS12#/
SS12#/SSLA3/SSLB3
17
PE0
WR1#/BC1#/
WAIT#
SSLA2/SSLB2/CRX1
18
PD7
GTIOC0A
CTS0#/RTS0#/SS0#/
SSLA1/SSLB1/CTX1
19
PD6
GTIOC0B
SSLA0/SSLB0
20
PD5
GTIOC1A
RXD1/SMISO1/SSCL1
21
PD4
GTIOC1B
SCK1
22
PD3
GTIOC2A
TXD1/SMOSI1/SSDA1
23
PD2
CS2#
GTIOC2B
MOSIA/MOSIB
24
PD1
CS0#
GTIOC3A
MISOA/MISOB
25
PD0
A12
GTIOC3B
RSPCKA/RSPCKB
PF4
CS3#
RXD1*1
26
TDI
27
TCK/FINEC
PF3
28
TDO
PF2
CS1#
RXD1/SMISO1/
SSCL1/TXD1*1
29
PB7
A19
SCK12
30
PB6
A18
RXD12/SMISO12/
SSCL12/RXDX12/
CRX1
31
PB5
A17
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/CTX1
PB4
A16
POE8#/GTETRG0
35
PB3
A15
MTIOC0A/CACREF
SCK0
36
PB2
MTIOC0B
TXD0/SMOSI0/
SSDA0/SDA0
37
PB1
MTIOC0C
RXD0/SMISO0/
SSCL0/SCL0
32
IRQ7
IRQ6
TXD1/SMOSI1/SSDA1
IRQ5
IRQ2
PLLVCC
33
34
Interrupt
IRQ3-DS
PLLVSS
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
IRQ4
Page 35 of 186
RX63T Group
Table 1.7
Pin Number
112-Pin
LQFP
1. Overview
List of Pins and Pin Functions (112-Pin LQFP) (2/4)
Power Supply
Clock System
Control
Communications
(SCIc, SCId, RSPI, RIIC,
CAN)
I/O Port
Bus
Timer
(MTU3, GPT, POE3, CAC)
38
PB0
A14
MTIOC0D
MOSIA/MOSIB
39
PA5
MTIOC1A
RXD0/SMISO0/
SSCL0/
MISOA/MISOB
ADTRG1#
40
PA4
MTIOC1B
TXD0/SMOSI0/
SSDA0/RSPCKA/
RSPCKB
ADTRG0#
41
PA3
MTIOC2A
SCK0/SSLA0/SSLB0
42
PA2
MTIOC2B
RXD2/SMISO2/
SSCL2/
SSLA1/SSLB1
43
PA1
MTIOC6A
TXD2/SMOSI2/
SSDA2/SSLA2/SSLB2
PA0
MTIOC6C
SCK2/SSLA3/SSLB3
POE4#
RXD1/SMISO1/SSCL1
44
45
VCC
46
47
P96
A13
P95
MTIOC6B/
GTIOC4A
TXD1/SMOSI1/SSDA1
49
P94
MTIOC7A/
GTIOC5A
CTS1#/RTS1#/SS1#
50
P93
MTIOC7B/
GTIOC6A
CTS2#/RTS2#/SS2#
51
P92
MTIOC6D/GTIOC4B
52
P91
MTIOC7C/GTIOC5B
53
P90
MTIOC7D/GTIOC6B
54
TRCLK
PG5
POE12#
SCK3
55
TRDATA3
PG4
GTIOC6B
RXD3/SMISO3/SSCL3
56
TRDATA2
PG3
GTIOC6A
TXD3/SMOSI3/SSDA3
57
TRDATA1
PG2
58
TRDATA0
PG1
59
TRSYNC
PG0
SCK2
IRQ2
RXD2/SMISO2/SSCL2
IRQ1
GTIOC7A
TXD2/SMOSI2/SSDA2
IRQ0
IRQ5-DS
P76
D0/[A0/D0]
MTIOC4D/GTIOC2B
61
P75
D1/[A1/D1]
MTIOC4C/GTIOC1B
62
P74
D2/[A2/D2]
MTIOC3D/GTIOC0B
63
P73
D3/[A3/D3]
MTIOC4B/GTIOC2A
64
P72
D4/[A4/D4]
MTIOC4A/GTIOC1A
65
P71
D5/[A5/D5]
MTIOC3B/GTIOC0A
66
P70
D6/[A6/D6]
POE0#
CTS1#/RTS1#/SS1#
67
P33
D7/[A7/D7]
MTIOC3A/MTCLKA
SSLA3/SSLB3
P32
D8/[A8/D8]
MTIOC3C/MTCLKB
SSLA2/SSLB2
P31
D9/[A9/D9]
MTIOC0A/MTCLKC
SSLA1/SSLB1
72
P30
D10/[A10/
D10]
MTIOC0B/MTCLKD
SCK0/SSLA0/SSLB0
73
P24
D11/[A11/D11]
68
ADTRG#
IRQ6
GTIOC7B
60
VCC
70
71
IRQ4-DS
VSS
48
69
S12ADB,
AD, DA
Interrupt
VSS
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
CTS0#/RTS0#/SS0#/
RSPCKA/RSPCKB
IRQ4
Page 36 of 186
RX63T Group
Table 1.7
Pin Number
112-Pin
LQFP
1. Overview
List of Pins and Pin Functions (112-Pin LQFP) (3/4)
Power Supply
Clock System
Control
Timer
(MTU3, GPT, POE3, CAC)
Communications
(SCIc, SCId, RSPI, RIIC,
CAN)
S12ADB,
AD, DA
I/O Port
Bus
74
P23
D12/[A12/
D12]
75
P22
D13/[A13/
D13]
76
P21
D14/[A14/
D14]
MTCLKA
IRQ6-DS
ADTRG1#
77
P20
D15/[A15/
D15]
MTCLKB
IRQ7-DS
ADTRG0#
78
P65
A0/BC0#
AN5
79
P64
A1
AN4
83
P63
A2
AN3
84
P62
A3
AN2
85
P61
A4
AN1
86
P60
A5
AN0
87
P55
AN11/DA1
88
P54
AN10/
DA0
89
P53
A6
AN9
90
P52
A7
AN8
91
P51
AN7
92
P50
AN6
93
P47
AN103/
CVREFH
94
P46
AN102
95
P45
AN101
96
P44
AN100
97
P43
AN003/
CVREFL
98
P42
AN002
99
P41
AN001
P40
AN000
80
AVCC
81
VREF
82
AVSS
100
101
AVCC0
102
VREFH0
103
VREFL0
104
AVSS0
CACREF
TXD0/SMOSI0/
SSDA0/MOSIA/
MOSIB/CTX1
RXD0/SMISO0/
SSCL0/MISOA/
MISOB/CRX1
105
P82
WAIT#
MTIC5U
SCK12
106
P81
A8
MTIC5V
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12
107
P80
A9
MTIC5W
RXD12/SMISO12/
SSCL12/RXDX12
108
P12
CS3#
109
P11
ALE
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Interrupt
MTCLKC
ADTRG#
IRQ3
IRQ5
IRQ1-DS
Page 37 of 186
RX63T Group
Table 1.7
Pin Number
112-Pin
LQFP
1. Overview
List of Pins and Pin Functions (112-Pin LQFP) (4/4)
Power Supply
Clock System
Control
110
I/O Port
Bus
P10
111
TRST#
P05
112
TMS
P04
Timer
(MTU3, GPT, POE3, CAC)
MTCLKD
Communications
(SCIc, SCId, RSPI, RIIC,
CAN)
S12ADB,
AD, DA
Interrupt
IRQ0-DS
WAIT#/CS2#
Note 1. Available for use as SCI pin only in boot mode.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 38 of 186
RX63T Group
Table 1.8
Pin Number
100-Pin
LQFP
1. Overview
List of Pins and Pin Functions (100-Pin LQFP) (1/3)
Power Supply
Clock System
Control
Timer
(MTU3, GPT, POE3, CAC)
Communications
(SCIc, SCId, RSPI, RIIC,
CAN)
S12ADB,
AD, DA
I/O Port
Bus
PE5
BCLK
P01
RD#
P00
CS1#
CACREF
8
PE4
A10
POE10#/MTCLKC
IRQ1
9
PE3
A11
POE11#/MTCLKD
IRQ2-DS
POE10#
NMI
1
2
EMLE
3
VSS
4
5
IRQ0
CTS0#/RTS0#/SS0#
VCL
6
7
MD/FINED
10
RES#
11
XTAL
12
VSS
13
EXTAL
14
VCC
15
PE2
16
PE1
WR0#/WR#
CTS12#/RTS12#/
SS12#/SSLA3/SSLB3
17
PE0
WR1#/BC1#/
WAIT#
SSLA2/SSLB2/CRX1
18
TRST#
PD7
GTIOC0A
CTS0#/RTS0#/SS0#/
SSLA1/SSLB1/CTX1
19
TMS
PD6
GTIOC0B
SSLA0/SSLB0
20
TDI
PD5
GTIOC1A
RXD1/SMISO1/SSCL1
21
TCK/FINEC
PD4
GTIOC1B
SCK1
22
TDO
PD3
GTIOC2A
TXD1/SMOSI1/SSDA1
23
PD2
CS2#
GTIOC2B
MOSIA/MOSIB
24
PD1
CS0#
GTIOC3A
MISOA/MISOB
25
PD0
A12
GTIOC3B
RSPCKA/RSPCKB
26
PB7
A19
SCK12
27
PB6
A18
RXD12/SMISO12/
SSCL12/RXDX12/
CRX1
28
PB5
A17
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/CTX1
PB4
A16
POE8#/GTETRG0
32
PB3
A15
MTIOC0A/CACREF
SCK0
33
PB2
MTIOC0B
TXD0/SMOSI0/
SSDA0/SDA0
34
PB1
MTIOC0C
RXD0/SMISO0/
SSCL0/SCL0
MTIOC0D
MOSIA/MOSIB
MTIOC1A
RXD0/SMISO0/
SSCL0/
MISOA/MISOB
29
IRQ7
IRQ6
IRQ2
PLLVCC
30
31
Interrupt
IRQ3-DS
PLLVSS
35
PB0
36
PA5
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
A14
IRQ4
ADTRG1#
Page 39 of 186
RX63T Group
Table 1.8
Pin Number
100-Pin
LQFP
1. Overview
List of Pins and Pin Functions (100-Pin LQFP) (2/3)
Power Supply
Clock System
Control
37
I/O Port
Bus
PA4
Timer
(MTU3, GPT, POE3, CAC)
Communications
(SCIc, SCId, RSPI, RIIC,
CAN)
MTIOC1B
TXD0/SMOSI0/
SSDA0/
RSPCKA/RSPCKB
38
PA3
MTIOC2A
SCK0/SSLA0/SSLB0
39
PA2
MTIOC2B
RXD2/SMISO2/
SSCL2/
SSLA1/SSLB1
40
PA1
MTIOC6A
TXD2/SMOSI2/
SSDA2/
SSLA2/SSLB2
PA0
MTIOC6C
SCK2/SSLA3/SSLB3
POE4#
RXD1/SMISO1/SSCL1
41
42
ADTRG0#
VCC
43
44
S12ADB,
AD, DA
Interrupt
P96
A13
IRQ4-DS
VSS
45
P95
MTIOC6B/GTIOC4A
TXD1/SMOSI1/SSDA1
46
P94
MTIOC7A/GTIOC5A
CTS1#/RTS1#/SS1#
47
P93
MTIOC7B/GTIOC6A
CTS2#/RTS2#/SS2#
48
P92
MTIOC6D/GTIOC4B
49
P91
MTIOC7C/GTIOC5B
50
P90
51
P76
D0/[A0/D0]
MTIOC4D/GTIOC2B
52
P75
D1/[A1/D1]
MTIOC4C/GTIOC1B
53
P74
D2/[A2/D2]
MTIOC3D/GTIOC0B
54
P73
D3/[A3/D3]
MTIOC4B/GTIOC2A
55
P72
D4/[A4/D4]
MTIOC4A/GTIOC1A
56
P71
D5/[A5/D5]
MTIOC3B/GTIOC0A
57
P70
D6/[A6/D6]
POE0#
CTS1#/RTS1#/SS1#
58
P33
D7/[A7/D7]
MTIOC3A/MTCLKA
SSLA3/SSLB3
59
P32
D8/[A8/D8]
MTIOC3C/MTCLKB
SSLA2/SSLB2
P31
D9/[A9/D9]
MTIOC0A/MTCLKC
SSLA1/SSLB1
63
P30
D10/[A10/
D10]
MTIOC0B/MTCLKD
SCK0/SSLA0/SSLB0
64
P24
D11/[A11/D11]
65
P23
D12/[A12/
D12]
66
P22
D13/[A13/
D13]
67
P21
D14/[A14/
D14]
MTCLKA
IRQ6-DS
ADTRG1#
68
P20
D15/[A15/
D15]
MTCLKB
IRQ7-DS
ADTRG0#
69
P65
A0/BC0#
AN5
70
P64
A1
AN4
60
IRQ5-DS
VCC
61
62
MTIOC7D/GTIOC6B
VSS
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
CTS0#/RTS0#/SS0#/
RSPCKA/RSPCKB
CACREF
IRQ4
TXD0/SMOSI0/
SSDA0/MOSIA/
MOSIB/CTX1
RXD0/SMISO0/
SSCL0/MISOA/
MISOB/CRX1
ADTRG#
Page 40 of 186
RX63T Group
Table 1.8
Pin Number
1. Overview
List of Pins and Pin Functions (100-Pin LQFP) (3/3)
100-Pin
LQFP
Power Supply
Clock System
Control
71
AVCC
72
VREF
73
AVSS
Timer
(MTU3, GPT, POE3, CAC)
Communications
(SCIc, SCId, RSPI, RIIC,
CAN)
S12ADB,
AD, DA
I/O Port
Bus
74
P63
A2
AN3
75
P62
A3
AN2
76
P61
A4
AN1
77
P60
A5
AN0
78
P55
AN11/DA1
79
P54
AN10/
DA0
80
P53
A6
AN9
81
P52
A7
AN8
82
P51
AN7
83
P50
AN6
84
P47
AN103/
CVREFH
85
P46
AN102
86
P45
AN101
87
P44
AN100
88
P43
AN003/
CVREFL
89
P42
AN002
90
P41
AN001
P40
AN000
91
92
AVCC0
93
VREFH0
94
VREFL0
95
AVSS0
Interrupt
96
P82
WAIT#
MTIC5U
SCK12
97
P81
A8
MTIC5V
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12
98
P80
A9
MTIC5W
RXD12/SMISO12/
SSCL12/RXDX12
99
P11
ALE
MTCLKC
IRQ1-DS
100
P10
MTCLKD
IRQ0-DS
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
IRQ3
IRQ5
Page 41 of 186
RX63T Group
Table 1.9
Pin Number
1. Overview
List of Pins and Pin Functions (64-Pin LQFP) (1/3)
64-Pin
LQFP
Power Supply
Clock
System
Control
1
EMLE
2
3
Timer
I/O Port
POE3
(MTU3,
GPT, CAC)
P00
GTIOC3A
P01
GTIOC3B
CACREF
Communications
(SCIc, SCId)
CTS0#
RTS0#
SS0#
5
MD
FINED
6
RES#
7
XTAL
8
VSS
9
EXTAL
10
VCC
11
S12ADB
IRQ2-DS
PE2
IRQ4-DS
POE10#
NMI
12
TRST#
PD7
GTIOC0A
13
TMS
PD6
GTIOC0B
14
TDI
PD5
GTIOC1A
RXD1
SMISO1
SSCL1
15
TCK
FINEC
PD4
GTIOC1B
SCK1
16
TDO
PD3
GTIOC2A
TXD1
SMOSI1
SSDA1
17
PB7
GTIOC2B
SCK12
18
PB6
GTIOC2B
RXD12
SMISO12
SSCL12
RXDX12
19
PB5
POE11#
CTS0#
RTS0#
SS0#
PB4
POE8#
TXD12
SMOSI12
SSDA12
TXDX12
SIOX12
IRQ0
GTETRG
CTS12#
RTS12#
SS12#
IRQ3-DS
VCC
21
22
Interrupt
VCL
4
20
(RSPI, RIIC)
VSS
23
PB3
MTIOC0A
MTCLKA
CACREF
SCK0
24
PB2
MTIOC0B
MTCLKB
TXD0
SMOSI0
SSDA0
SDA
25
PB1
MTIOC0C
RXD0
SMISO0
SSCL0
SCL
26
PB0
MTIOC0D
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
MOSIA
Page 42 of 186
RX63T Group
Table 1.9
Pin Number
64-Pin
LQFP
1. Overview
List of Pins and Pin Functions (64-Pin LQFP) (2/3)
Power Supply
Clock
System
Control
Timer
I/O Port
POE3
(MTU3,
GPT, CAC)
Communications
(SCIc, SCId)
(RSPI, RIIC)
27
PA3
MTIOC2A
SSLA0
28
PA2
MTIOC2B
SSLA1
29
P94
TXD1
SMOSI1
SSDA1
30
P93
RXD1
SMISO1
SSCL1
31
P92
SCK1
32
P91
CTS1#
RTS1#
SS1#
33
P76
MTIOC4D
GTIOC2B
MTIOC7D
34
P75
MTIOC4C
GTIOC1B
MTIOC7C
35
P74
MTIOC3D
GTIOC0B
MTIOC6D
36
P73
MTIOC4B
GTIOC2A
MTIOC7B
37
P72
MTIOC4A
GTIOC1A
MTIOC7A
38
P71
MTIOC3B
GTIOC0A
MTIOC6B
39
P70
40
P33
MTIOC3A
MTIOC6A
SSLA3
41
P32
MTIOC3C
MTIOC6C
SSLA2
P31
MTIOC0A
SSLA1
45
P30
MTIOC0B
MTCLKD
TXD0
SMOSI0
SSDA0
SSLA0
46
P24
MTIC5U
MTCLKC
RXD0
SMISO0
SSCL0
RSPCKA
47
P23
MTIC5V
MTCLKB
CACREF
SCK0
MOSIA
48
P22
MTIC5W
MTCLKA
CTS0#
RTS0#
SS0#
MISOA
49
P47
42
S12ADB
IRQ1
CTS1#
RTS1#
SS1#
IRQ5-DS
VCC
43
44
POE0#
Interrupt
VSS
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
AN007
CVREFH
Page 43 of 186
RX63T Group
Table 1.9
Pin Number
64-Pin
LQFP
1. Overview
List of Pins and Pin Functions (64-Pin LQFP) (3/3)
Power Supply
Clock
System
Control
Timer
I/O Port
POE3
(MTU3,
GPT, CAC)
Communications
(SCIc, SCId)
(RSPI, RIIC)
Interrupt
S12ADB
50
P46
AN006
51
P45
AN005
52
P44
AN004
53
P43
AN003
CVREFL
54
P42
AN002
55
P41
AN001
56
P40
AN000
57
AVCC0
58
VREFH0
59
VREFL0
60
AVSS0
61
P11
MTCLKC
IRQ1-DS
62
P10
MTCLKD
IRQ0-DS
63
PA5
MTIOC1A
MISOA
64
PA4
MTIOC1B
RSPCKA
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
ADTRG0#
Page 44 of 186
RX63T Group
Table 1.10
Pin Number
64-Pin
LQFP
1. Overview
List of Pins and Pin Functions (48-Pin LQFP) (1/2)
Power Supply
Clock
System Control
1
MD
FINED
2
RES#
3
XTAL
4
VSS
5
EXTAL
6
VCC
7
Timer
I/O Port
POE3
PE2
POE10#
(MTU3,
GPT, CAC)
Communications
(SCIc, SCId)
TRST#
PD7
GTIOC0A
9
TMS
PD6
GTIOC0B
10
TDI
PD5
GTIOC1A
RXD1
SMISO1
SSCL1
11
TCK
FINEC
PD4
GTIOC1B
SCK1
12
TDO
PD3
GTIOC2A
TXD1
SMOSI1
SSDA1
13
PB6
GTIOC2B
RXD12
SMISO12
SSCL12
RXDX12
14
PB5
POE11#
S12ADB
CTS0#
RTS0#
SS0#
PB4
POE8#
TXD12
SMOSI12
SSDA12
TXDX12
SIOX12
IRQ0
GTETRG
CTS12#
RTS12#
SS12#
IRQ3-DS
VCC
16
17
Interrupt
NMI
8
15
(RSPI, RIIC)
VSS
18
PB3
MTIOC0A
MTCLKA
CACREF
SCK0
19
PB2
MTIOC0B
MTCLKB
TXD0
SMOSI0
SSDA0
SDA
20
PB1
MTIOC0C
RXD0
SMISO0
SSCL0
SCL
21
PB0
MTIOC0D
MOSIA
22
PA3
MTIOC2A
SSLA0
23
PA2
MTIOC2B
SSLA1
24
P76
MTIOC4D
GTIOC2B
MTIOC7D
25
P75
MTIOC4C
GTIOC1B
MTIOC7C
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 45 of 186
RX63T Group
Table 1.10
Pin Number
64-Pin
LQFP
1. Overview
List of Pins and Pin Functions (48-Pin LQFP) (2/2)
Power Supply
Clock
System Control
Timer
I/O Port
POE3
(MTU3,
GPT, CAC)
26
P74
MTIOC3D
GTIOC0B
MTIOC6D
27
P73
MTIOC4B
GTIOC2A
MTIOC7B
28
P72
MTIOC4A
GTIOC1A
MTIOC7A
29
P71
MTIOC3B
GTIOC0A
MTIOC6B
30
P70
31
POE0#
Communications
(SCIc, SCId)
(RSPI, RIIC)
CTS1#
RTS1#
SS1#
Interrupt
S12ADB
IRQ5-DS
VCC
32
P30
MTIOC0B
MTCLKD
TXD0
SMOSI0
SSDA0
SSLA0
34
P24
MTIC5U
MTCLKC
RXD0
SMISO0
SSCL0
RSPCKA
35
P23
MTIC5V
MTCLKB
CACREF
SCK0
MOSIA
36
P22
MTIC5W
MTCLKA
CTS0#
RTS0#
SS0#
MISOA
37
P47
AN007
CVREFH
38
P44
AN004
39
P43
AN003
CVREFL
40
P42
AN002
41
P41
AN001
P40
AN000
33
VSS
42
43
AVCC0
44
VREFH0
45
VREFL0
46
AVSS0
47
VCL
48
EMLE
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RX63T Group
2.
2. CPU
CPU
The RX CPU has sixteen general-purpose registers, nine control registers, and one accumulator used for DSP
instructions.
General-purpose register
b31
b0
R0 (SP)*
1
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
Control register
b31
b0
ISP
(Interrupt stack pointer)
USP
(User stack pointer)
INTB
(Interrupt table register)
PC
(Program counter)
PSW
(Processor status word)
BPC
(Backup PC)
BPSW
(Backup PSW)
FINTV
(Fast interrupt vector register)
FPSW
(Floating-point status word)
DSP instruction register
b63
b0
ACC (Accumulator)
Note 1. The stack pointer (SP) can be the interrupt stack pointer (ISP) or user stack pointer (USP), according
to the value of the U bit in the PSW.
Figure 2.1
Register Set of the CPU
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RX63T Group
2.1
2. CPU
General-Purpose Registers (R0 to R15)
This CPU has sixteen general-purpose registers (R0 to R15). R1 to R15 can be used as data registers or address registers.
R0, a general-purpose register, also functions as the stack pointer (SP).
The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the
stack pointer select bit (U) in the processor status word (PSW).
2.2
(1)
Control Registers
Interrupt Stack Pointer (ISP)/User Stack Pointer (USP)
The stack pointer (SP) can be either of two types, the interrupt stack pointer (ISP) or the user stack pointer (USP).
Whether the stack pointer operates as the ISP or USP depends on the value of the stack pointer select bit (U) in the
processor status word (PSW).
Set the ISP or USP to a multiple of four, as this reduces the numbers of cycles required to execute interrupt sequences
and instructions entailing stack manipulation.
(2)
Interrupt Table Register (INTB)
The interrupt table register (INTB) specifies the address where the relocatable vector table starts.
(3)
Program Counter (PC)
The program counter (PC) indicates the address of the instruction being executed.
(4)
Processor Status Word (PSW)
The processor status word (PSW) indicates the results of instruction execution or the state of the CPU.
(5)
Backup PC (BPC)
The backup PC (BPC) is provided to speed up response to interrupts.
After a fast interrupt has been generated, the contents of the program counter (PC) are saved in the BPC register.
(6)
Backup PSW (BPSW)
The backup PSW (BPSW) is provided to speed up response to interrupts.
After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in the BPSW. The
allocation of bits in the BPSW corresponds to that in the PSW.
(7)
Fast Interrupt Vector Register (FINTV)
The fast interrupt vector register (FINTV) is provided to speed up response to interrupts.
The FINTV register specifies a branch destination address when a fast interrupt has been generated.
(8)
Floating-Point Status Word (FPSW)
The floating-point status word (FPSW) indicates the results of floating-point operations.
When an exception handling enable bit (Ej) enables the exception handling (Ej = 1), the exception cause can be identified
by checking the corresponding Cj flag in the exception handling routine. If the exception handling is masked (Ej = 0), the
occurrence of exception can be checked by reading the Fj flag at the end of a series of processing. Once the Fj flag has
been set to 1, this value is retained until it is cleared to 0 by software (j = X, U, Z, O, or V).
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RX63T Group
2.2.1
(1)
2. CPU
Register Associated with DSP Instructions
Accumulator (ACC)
The accumulator (ACC) is a 64-bit register used for DSP instructions. The accumulator is also used for the multiply and
multiply-and-accumulate instructions; EMUL, EMULU, FMUL, MUL, and RMPA, in which case the prior value in the
accumulator is modified by execution of the instruction.
Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The MVTACHI and MVTACLO
instructions write data to the higher-order 32 bits (bits 63 to 32) and the lower-order 32 bits (bits 31 to 0), respectively.
Use the MVFACHI and MVFACMI instructions for reading data from the accumulator. The MVFACHI and MVFACMI
instructions read data from the higher-order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively.
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RX63T Group
3.
Address Space
3.1
Address Space
3. Address Space
This MCU has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is,
linear access to an address space of up to 4 Gbytes is possible, and this contains both program and data areas.
Figure 3.1 shows the memory maps in the respective operating modes. Accessible areas will differ according to the
operating mode and states of control bits.
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RX63T Group
3. Address Space
On-chip ROM enabled
extended mode
Single-chip mode*1
On-chip ROM disabled
extended mode
0000 0000h
On-chip RAM*2
0000 0000h
On-chip RAM*2
0000 0000h
On-chip RAM*2
0000 C000h
Reserved area*3
0000 C000h
Reserved area*3
0000 C000h
Reserved area*3
0008 0000h
0008 0000h
Peripheral I/O registers
0010 0000h
On-chip ROM (E2 data flash)
0010 8000h
0008 0000h
0010 0000h
0010 0000h
On-chip ROM (E2 data flash)
0010 8000h
Reserved area*3
007F C000h
007F C500h
Peripheral I/O registers
Reserved area*3
007F C000h
007F C500h
On-chip ROM (E2 data flash)
Reserved area*3
007F FC00h
0080 0000h
00F8 0000h
Peripheral I/O registers
Peripheral I/O registers
Peripheral I/O registers
007F FC00h
On-chip ROM (E2 data flash)
Reserved area*3
0080 0000h
Reserved area*3
On-chip ROM (program ROM)
(write only)
00F8 0000h
On-chip ROM (program ROM)
(write only)
0100 0000h
0100 0000h
Reserved area*3
Reserved area*3
Reserved area*3
0500 0000h
0500 0000h
External address space
External address space
0800 0000h
0800 0000h
Reserved area*3
Reserved area*3
Reserved area*3
FF00 0000h
FF7F C000h
FF80 0000h
On-chip ROM (user boot)
(read only)
Reserved area*3
FFF8 0000h
FF7F C000h
On-chip ROM (user boot)
(read only)
FF80 0000h
External address space
Reserved area*3
FFF8 0000h
On-chip ROM (program ROM)
(read only)*2
FFFF FFFFh
On-chip ROM (program ROM)
(read only)*2
FFFF FFFFh
FFFF FFFFh
Note 1. The address space in boot mode and user boot mode is the same as the address space in single-chip mode.
Note 2. The capacity of ROM/RAM differs depending on the products.
ROM (bytes)
Capacity Address
RAM (bytes)
Capacity Address
E2 DataFlash (bytes)
Capacity Address
512 K
FFF8 0000h to FFFF FFFFh 48 K
0000 0000h to 0000 BFFFh 32 K
384 K
FFFA 0000h to FFFF FFFFh 32 K
0000 0000h to 0000 7FFFh
256 K
FFFC 0000h to FFFF FFFFh 24 K
0000 0000h to 0000 5FFFh
64 K
FFFF 0000h to FFFF FFFFh
48 K
FFFF 4000h to FFFF FFFFh
32 K
FFFF 8000h to FFFF FFFFh
8K
0000 0000h to 0000 1FFFh 8 K
0010 0000h to 0010 8000h
0010 0000h to 0010 2000h
Note:•See Table 1.3, List of Products, for the product type name.
Note 3. Reserved areas should not be accessed.
Note 4. For details on the FCU, see section 41, Flash Memory in the User’s Manual: Hardware.
Figure 3.1
Memory Map in Each Operating Mode
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RX63T Group
3.2
3. Address Space
External Address Space
The external address space is divided into up to four CS areas (CS0 to CS3), each corresponding to the CSn# signal
output from a CSn# (n = 0 to 3) pin.
Figure 3.2 shows the address ranges corresponding to the individual CS areas (CS0 to CS3) in on-chip ROM disabled
extended mode.
0000 0000h
On-chip RAM
0000 C000h
Reserved area*1
0008 0000h
Peripheral I/O registers
0010 0000h
0500 0000h
Reserved area*1
Reserved area*1
05EF FFFFh
05F0 0000h
CS3 (1 Mbytes)
05FF FFFFh
0600 0000h
0500 0000h
Reserved area*1
06EF FFFFh
06F0 0000h
External address space
CS2 (1 Mbytes)
06FF FFFFh
0700 0000h
0800 0000h
Reserved area*1
07EF FFFFh
07F0 0000h
CS1 (1 Mbytes)
Reserved area*1
07FF FFFFh
FF00 0000h
FF00 0000h
Reserved area*1
External address space*
2
FFEF FFFFh
FFF0 0000h
CS0 (1 Mbytes)
FFFF FFFFh
FFFF FFFFh
Note 1. Reserved areas should not be accessed.
Note 2. The CS0 area is disabled in on-chip ROM enabled extended mode.
In this mode, the address space for addresses above 0800 0000h is as shown in Figure 3.1, Memory
Map in Each Operating Mode.
Figure 3.2
Correspondence between External Address Spaces and CS Areas
(In On-Chip ROM Disabled Extended Mode)
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RX63T Group
4.
4. I/O Registers
I/O Registers
This section gives information on the on-chip I/O register addresses. The information is given as shown below. Notes on
writing to registers are also given at the end.
(1)
I/O register addresses (address order)
Registers are listed from the lower allocation addresses.
Registers are classified according to module symbols.
The number of access cycles indicates the number of cycles based on the specified reference clock.
Among the internal I/O register area, addresses not listed in the list of registers are reserved. Reserved addresses
must not be accessed. Do not access these addresses; otherwise, the operation when accessing these bits and
subsequent operations cannot be guaranteed.
(2)
Notes on writing to I/O registers
When writing to an I/O register, the CPU starts executing the subsequent instruction before completing I/O register write.
This may cause the subsequent instruction to be executed before the post-update I/O register value is reflected on the
operation.
As described in the following examples, special care is required for the cases in which the subsequent instruction must be
executed after the post-update I/O register value is actually reflected.
[Examples of cases requiring special care]
The subsequent instruction must be executed while an interrupt request is disabled with the IENj bit in IERn of the
ICU (interrupt request enable bit) cleared to 0.
A WAIT instruction is executed immediately after the preprocessing for causing a transition to the low power
consumption state.
In the above cases, after writing to an I/O register, wait until the write operation is completed using the following
procedure and then execute the subsequent instruction.
(a) Write to an I/O register.
(b) Read the value from the I/O register to a general register.
(c) Execute the operation using the value read.
(d) Execute the subsequent instruction.
[Instruction examples]
Byte-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.B #SFR_DATA, [R1]
CMP [R1].UB, R1
;; Next process
Word-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.W #SFR_DATA, [R1]
CMP [R1].W, R1
;; Next process
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RX63T Group
4. I/O Registers
Longword-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.L #SFR_DATA, [R1]
CMP [R1].L, R1
;; Next process
If multiple registers are written to and a subsequent instruction should be executed after the write operations are entirely
completed, only read the I/O register that was last written to and execute the operation using the value; it is not necessary
to read or execute operation for all the registers that were written to.
(3)
Number of Access Cycles to I/O Registers
For the number of I/O register access cycles, refer to Table 4.1, List of I/O Registers (Address Order).
The number of access cycles to I/O registers is obtained by following equation.*1
Number of access cycles to I/O registers = Number of bus cycles for internal main bus 1 +
Number of divided clock synchronization cycles +
Number of bus cycles for internal peripheral bus 1 to 6
The number of bus cycles of internal peripheral bus 1 to 6 differs according to the register to be accessed.
When peripheral functions connected to internal peripheral bus 2 to 6 are accessed, the number of divided clock
synchronization cycles is added.
The number of divided clock synchronization cycles differs depending on the frequency ratio between ICLK and PCLK
(or FCLK, BCLK) or bus access timing.
In the peripheral function unit, when the frequency ratio of ICLK is equal to or greater than that of PCLK (or FCLK), the
sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will
be one cycle of PCLK (or FCLK) at a maximum. Therefore, one PCLK (or FCLK) has been added to the number of
access states shown in Table 4.1.
When the frequency ratio of ICLK is lower than that of PCLK (or FCLK), the subsequent bus access is started from the
ICLK cycle following the completion of the access to the peripheral functions. Therefore, the access cycles are described
on an ICLK basis.
In the external bus control unit, the sum of the number of bus cycles for internal main bus 1 and the number of divided
clock synchronization cycles will be one cycle of BCLK at a maximum. Therefore, one BCLK is added to the number of
access cycles shown in Table 4.1.
Note 1.
(4)
This applies to the number of cycles when the access from the CPU does not conflict with the instruction
fetching to the external memory or bus access from the different bus master (DMAC or DTC).
Note on Sleep Mode and Mode Transition
During sleep mode or a mode transition, do not write to the system control related registers (indicated by 'SYSTEM' in
the Module Symbol column in Table 4.1, List of I/O Registers (Address Order)).
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RX63T Group
4.1
4. I/O Registers
I/O Register Addresses (Address Order)
Table 4.1
List of I/O Registers (Address Order) (1/48)
Number of Access States
Address
Module
Symbol
0008 0000h
SYSTEM
Mode Monitor Register
MDMONR
16
16
3 ICLK
0008 0002h
SYSTEM
Mode Status Register
MDSR
16
16
3 ICLK
0008 0006h
SYSTEM
System Control Register 0
SYSCR0
16
16
3 ICLK
0008 0008h
SYSTEM
System Control Register 1
SYSCR1
16
16
3 ICLK
0008 000Ch SYSTEM
Standby Control Register
SBYCR
16
16
3 ICLK
0008 0010h
SYSTEM
Module Stop Control Register A
MSTPCRA
32
32
3 ICLK
0008 0014h
SYSTEM
Module Stop Control Register B
MSTPCRB
32
32
3 ICLK
0008 0018h
SYSTEM
Module Stop Control Register C
MSTPCRC
32
32
3 ICLK
0008 0020h
SYSTEM
System Clock Control Register
SCKCR
32
32
3 ICLK
0008 0024h
SYSTEM
System Clock Control Register 2
SCKCR2
16
16
3 ICLK
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
0008 0026h
SYSTEM
System Clock Control Register 3
SCKCR3
16
16
3 ICLK
0008 0028h
SYSTEM
PLL Control Register
PLLCR
16
16
3 ICLK
0008 002Ah SYSTEM
PLL Control Register 2
PLLCR2
8
8
3 ICLK
0008 0030h
SYSTEM
External Bus Clock Control Register
BCKCR
8
8
3 ICLK
0008 0032h
SYSTEM
Main Clock Oscillator Control Register
MOSCCR
8
8
3 ICLK
0008 0034h
SYSTEM
Low-Speed On-Chip Oscillator Control
Register
LOCOCR
8
8
3 ICLK
0008 0035h
SYSTEM
IWDT-Dedicated On-Chip Oscillator Control
Register
ILOCOCR
8
8
3 ICLK
0008 0040h
SYSTEM
Oscillation Stop Detection Control Register
OSTDCR
8
8
3 ICLK
0008 0041h
SYSTEM
Oscillation Stop Detection Status Register
OSTDSR
8
8
3 ICLK
ICLK PCLK
Module
Name
Not present in versions
with 64 or 48 pins.
Low Power
Consumption
Clock
Generation
Circuit
Main Clock Oscillator Wait Control Register
MOSCWTCR 8
8
3 ICLK
0008 00A6h SYSTEM
PLL Wait Control Register
PLLWTCR
8
8
3 ICLK
0008 00C0h SYSTEM
Reset Status Register 2
RSTSR2
8
8
3 ICLK
0008 00C2h SYSTEM
Software Reset Register
SWRR
16
16
3 ICLK
0008 00E0h SYSTEM
Voltage Monitoring 1 Circuit Control Register 1
LVD1CR1
8
8
3 ICLK
0008 00E1h SYSTEM
Voltage Monitoring 1 Circuit Status Register
LVD1SR
8
8
3 ICLK
0008 00E2h SYSTEM
Voltage Monitoring 2 Circuit Control Register LVD2CR1
1
8
8
3 ICLK
0008 00E3h SYSTEM
Voltage Monitoring 2 Circuit Status Register
LVD2SR
8
8
3 ICLK
0008 03FEh SYSTEM
Protect Register
PRCR
16
16
3 ICLK
Register
Write
Protection
Function
Buses
0008 1300h
BSC
Bus Error Status Clear Register
BERCLR
8
8
2 ICLK
BSC
Bus Error Monitoring Enable Register
BEREN
8
8
2 ICLK
0008 1308h
BSC
Bus Error Status Register 1
BERSR1
8
8
2 ICLK
0008 130Ah BSC
Bus Error Status Register 2
BERSR2
16
16
2 ICLK
0008 1310h
BSC
Bus Priority Control Register
BUSPRI
16
16
2 ICLK
0008 2000h
DMAC0
DMA Source Address Register
DMSAR
32
32
2 ICLK
0008 2004h
DMAC0
DMA Destination Address Register
DMDAR
32
32
2 ICLK
0008 2008h
DMAC0
DMA Transfer Count Register
DMCRA
32
32
2 ICLK
0008 200Ch DMAC0
DMA Block Transfer Count Register
DMCRB
16
16
2 ICLK
0008 2010h
DMAC0
DMA Transfer Mode Register
DMTMD
16
16
2 ICLK
0008 2013h
DMAC0
DMA Interrupt Setting Register
DMINT
8
8
2 ICLK
0008 2014h
DMAC0
DMA Address Mode Register
DMAMD
16
16
2 ICLK
0008 2018h
DMAC0
DMA Offset Register
DMOFR
32
32
2 ICLK
0008 201Ch DMAC0
DMA Transfer Enable Register
DMCNT
8
8
2 ICLK
0008 201Dh DMAC0
DMA Software Start Register
DMREQ
8
8
2 ICLK
0008 201Eh DMAC0
DMA Status Register
DMSTS
8
8
2 ICLK
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Not present in versions
with 64 or 48 pins.
Not present in versions
with 64 or 48 pins.
0008 00A2h SYSTEM
0008 1304h
Remarks
Operating
Modes
Low Power
Consumption
Resets
LVDA
DMACA
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RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (2/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
0008 201Fh
DMAC0
DMA Activation Source Flag Control Register DMCSL
8
8
2 ICLK
0008 2040h
DMAC1
DMA Source Address Register
DMSAR
32
32
2 ICLK
0008 2044h
DMAC1
DMA Destination Address Register
DMDAR
32
32
2 ICLK
0008 2048h
DMAC1
DMA Transfer Count Register
DMCRA
32
32
2 ICLK
0008 204Ch DMAC1
DMA Block Transfer Count Register
DMCRB
16
16
2 ICLK
0008 2050h
DMAC1
DMA Transfer Mode Register
DMTMD
16
16
2 ICLK
0008 2053h
DMAC1
DMA Interrupt Setting Register
DMINT
8
8
2 ICLK
0008 2054h
DMAC1
DMA Address Mode Register
DMAMD
16
16
2 ICLK
0008 205Ch DMAC1
DMA Transfer Enable Register
DMCNT
8
8
2 ICLK
0008 205Dh DMAC1
DMA Software Start Register
DMREQ
8
8
2 ICLK
0008 205Eh DMAC1
DMA Status Register
DMSTS
8
8
2 ICLK
0008 205Fh
DMAC1
DMA Activation Source Flag Control Register DMCSL
8
8
2 ICLK
0008 2080h
DMAC2
DMA Source Address Register
DMSAR
32
32
2 ICLK
0008 2084h
DMAC2
DMA Destination Address Register
DMDAR
32
32
2 ICLK
0008 2088h
DMAC2
DMA Transfer Count Register
DMCRA
32
32
2 ICLK
2 ICLK
0008 208Ch DMAC2
DMA Block Transfer Count Register
DMCRB
16
16
0008 2090h
DMAC2
DMA Transfer Mode Register
DMTMD
16
16
2 ICLK
0008 2093h
DMAC2
DMA Interrupt Setting Register
DMINT
8
8
2 ICLK
0008 2094h
DMAC2
DMA Address Mode Register
DMAMD
16
16
2 ICLK
0008 209Ch DMAC2
DMA Transfer Enable Register
DMCNT
8
8
2 ICLK
0008 209Dh DMAC2
DMA Software Start Register
DMREQ
8
8
2 ICLK
0008 209Eh DMAC2
DMA Status Register
DMSTS
8
8
2 ICLK
0008 209Fh
DMAC2
DMA Activation Source Flag Control Register DMCSL
8
8
2 ICLK
0008 20C0h DMAC3
DMA Source Address Register
DMSAR
32
32
2 ICLK
0008 20C4h DMAC3
DMA Destination Address Register
DMDAR
32
32
2 ICLK
0008 20C8h DMAC3
DMA Transfer Count Register
DMCRA
32
32
2 ICLK
0008 20CCh DMAC3
DMA Block Transfer Count Register
DMCRB
16
16
2 ICLK
0008 20D0h DMAC3
DMA Transfer Mode Register
DMTMD
16
16
2 ICLK
0008 20D3h DMAC3
DMA Interrupt Setting Register
DMINT
8
8
2 ICLK
0008 20D4h DMAC3
DMA Address Mode Register
DMAMD
16
16
2 ICLK
0008 20DCh DMAC3
DMA Transfer Enable Register
DMCNT
8
8
2 ICLK
0008 20DDh DMAC3
DMA Software Start Register
DMREQ
8
8
2 ICLK
0008 20DEh DMAC3
DMA Status Register
DMSTS
8
8
2 ICLK
0008 20DFh DMAC3
DMA Activation Source Flag Control Register DMCSL
8
8
2 ICLK
0008 2200h
DMACA Module Activation Register
DMAST
8
8
2 ICLK
DMAC
0008 2400h
DTC
DTC Control Register
DTCCR
8
8
2ICLK
0008 2404h
DTC
DTC Vector Base Register
DTCVBR
32
32
2ICLK
0008 2408h
DTC
2ICLK
ICLK PCLK
Module
Name
Remarks
DMACA
DTCa
DTC Address Mode Register
DTCADMOD 8
8
0008 240Ch DTC
DTC Module Start Register
DTCST
8
8
2ICLK
0008 240Eh DTC
DTC Status Register
DTCSTS
16
16
2ICLK
0008 3002h
BSC
CS0 Mode Register
CS0MOD
16
16
1, 2 BCLK
0008 3004h
BSC
CS0 Wait Control Register 1
CS0WCR1
32
32
1, 2 BCLK
Not present in versions
with 64 or 48 pins.
0008 3008h
BSC
CS0 Wait Control Register 2
CS0WCR2
32
32
1, 2 BCLK
Not present in versions
with 64 or 48 pins.
0008 3012h
BSC
CS1 Mode Register
CS1MOD
16
16
1, 2 BCLK
Not present in versions
with 64 or 48 pins.
0008 3014h
BSC
CS1 Wait Control Register 1
CS1WCR1
32
32
1, 2 BCLK
Not present in versions
with 64 or 48 pins.
0008 3018h
BSC
CS1 Wait Control Register 2
CS1WCR2
32
32
1, 2 BCLK
Not present in versions
with 64 or 48 pins.
0008 3022h
BSC
CS2 Mode Register
CS2MOD
16
16
1, 2 BCLK
Not present in versions
with 64 or 48 pins.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Buses
Not present in versions
with 64 or 48 pins.
Page 56 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (3/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
BSC
CS2 Wait Control Register 1
CS2WCR1
32
32
1, 2 BCLK
0008 3028h
BSC
CS2 Wait Control Register 2
CS2WCR2
32
32
1, 2 BCLK
Not present in versions
with 64 or 48 pins.
0008 3032h
BSC
CS3 Mode Register
CS3MOD
16
16
1, 2 BCLK
Not present in versions
with 64 or 48 pins.
0008 3034h
BSC
CS3 Wait Control Register 1
CS3WCR1
32
32
1, 2 BCLK
Not present in versions
with 64 or 48 pins.
0008 3038h
BSC
CS3 Wait Control Register 2
CS3WCR2
32
32
1, 2 BCLK
Not present in versions
with 64 or 48 pins.
0008 3802h
BSC
CS0 Control Register
CS0CR
16
16
1, 2 BCLK
Not present in versions
with 64 or 48 pins.
0008 380Ah BSC
CS0 Recovery Cycle Register
CS0REC
16
16
1, 2 BCLK
Not present in versions
with 64 or 48 pins.
0008 3812h
CS1 Control Register
CS1CR
16
16
1, 2 BCLK
Not present in versions
with 64 or 48 pins.
0008 381Ah BSC
CS1 Recovery Cycle Register
CS1REC
16
16
1, 2 BCLK
Not present in versions
with 64 or 48 pins.
0008 3822h
CS2 Control Register
CS2CR
16
16
1, 2 BCLK
Not present in versions
with 64 or 48 pins.
0008 382Ah BSC
CS2 Recovery Cycle Register
CS2REC
16
16
1, 2 BCLK
Not present in versions
with 64 or 48 pins.
0008 3832h
CS3 Control Register
CS3CR
16
16
1, 2 BCLK
Not present in versions
with 64 or 48 pins.
0008 383Ah BSC
CS3 Recovery Cycle Register
CS3REC
16
16
1, 2 BCLK
Not present in versions
with 64 or 48 pins.
0008 3880h
BSC
CS Recovery Cycle Insertion Enable
Register
CSRECEN
16
16
1, 2 BCLK
Not present in versions
with 64 or 48 pins.
0008 6400h
MPU
Region-0 Start Page Number Register
RSPAGE0
32
32
1 ICLK
0008 6404h
MPU
Region-0 End Page Number Register
REPAGE0
32
32
1 ICLK
0008 6408h
BSC
BSC
BSC
MPU
Region-1 Start Page Number Register
RSPAGE1
32
32
1 ICLK
0008 640Ch MPU
Region-1 End Page Number Register
REPAGE1
32
32
1 ICLK
0008 6410h
MPU
Region-2 Start Page Number Register
RSPAGE2
32
32
1 ICLK
0008 6414h
MPU
Region-2 End Page Number Register
REPAGE2
32
32
1 ICLK
0008 6418h
MPU
Region-3 Start Page Number Register
RSPAGE3
32
32
1 ICLK
0008 641Ch MPU
Region-3 End Page Number Register
REPAGE3
32
32
1 ICLK
0008 6420h
Region-4 Start Page Number Register
RSPAGE4
32
32
1 ICLK
MPU
0008 6424h
MPU
Region-4 End Page Number Register
REPAGE4
32
32
1 ICLK
0008 6428h
MPU
Region-5 Start Page Number Register
RSPAGE5
32
32
1 ICLK
0008 642Ch MPU
Region-5 End Page Number Register
REPAGE5
32
32
1 ICLK
0008 6430h
Region-6 Start Page Number Register
RSPAGE6
32
32
1 ICLK
MPU
0008 6434h
MPU
Region-6 End Page Number Register
REPAGE6
32
32
1 ICLK
0008 6438h
MPU
Region-7 Start Page Number Register
RSPAGE7
32
32
1 ICLK
0008 643Ch MPU
Region-7 End Page Number Register
REPAGE7
32
32
1 ICLK
0008 6500h
MPU
Memory-Protection Enable Register
MPEN
32
32
1 ICLK
0008 6504h
MPU
Background Access Control Register
MPBAC
32
32
1 ICLK
0008 6508h
MPU
Memory-Protection Error Status-Clearing
Register
MPECLR
32
32
1 ICLK
0008 650Ch MPU
Memory-Protection Error Status Register
MPESTS
32
32
1 ICLK
0008 6514h
MPU
Data Memory-Protection Error Address
Register
MPDEA
32
32
1 ICLK
0008 6520h
MPU
Region Search Address Register
MPSA
32
32
1 ICLK
0008 6524h
MPU
Region Search Operation Register
MPOPS
16
16
1 ICLK
0008 6526h
MPU
Region Invalidation Operation Register
MPOPI
16
16
1 ICLK
0008 6528h
MPU
Instruction-Hit Region Register
MHITI
32
32
1 ICLK
Data-Hit Region Register
MHITD
32
32
1 ICLK
0008 652Ch MPU
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Buses
Remarks
0008 3024h
Not present in versions
with 64 or 48 pins.
MPU
Page 57 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (4/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
0008 7010h
ICU
Interrupt Request Register 016
IR016
8
8
2 ICLK
0008 7015h
ICU
Interrupt Request Register 021
IR021
8
8
2 ICLK
0008 7017h
ICLK PCLK
Module
Name
Remarks
ICUb
ICU
Interrupt Request Register 023
IR023
8
8
2 ICLK
0008 701Bh ICU
Interrupt Request Register 027
IR027
8
8
2 ICLK
0008 701Ch ICU
Interrupt Request Register 028
IR028
8
8
2 ICLK
0008 701Dh ICU
Interrupt Request Register 029
IR029
8
8
2 ICLK
0008 701Eh ICU
Interrupt Request Register 030
IR030
8
8
2 ICLK
0008 701Fh
ICU
Interrupt Request Register 031
IR031
8
8
2 ICLK
0008 7021h
ICU
Interrupt Request Register 033
IR033
8
8
2 ICLK
Not present in versions
with 112, 100, 64 or 48
pins.
0008 7022h
ICU
Interrupt Request Register 034
IR034
8
8
2 ICLK
Not present in versions
with 112, 100, 64 or 48
pins.
0008 7023h
ICU
Interrupt Request Register 035
IR035
8
8
2 ICLK
Not present in versions
with 112, 100, 64 or 48
pins.
0008 7024h
ICU
Interrupt Request Register 036
IR036
8
8
2 ICLK
0008 7025h
ICU
Interrupt Request Register 037
IR037
8
8
2 ICLK
0008 7026h
ICU
Interrupt Request Register 038
IR038
8
8
2 ICLK
0008 7027h
ICU
Interrupt Request Register 039
IR039
8
8
2 ICLK
0008 7028h
ICU
Interrupt Request Register 040
IR040
8
8
2 ICLK
0008 7029h
ICU
Interrupt Request Register 041
IR041
8
8
2 ICLK
0008 702Ah ICU
Interrupt Request Register 042
IR042
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 702Bh ICU
Interrupt Request Register 043
IR043
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 702Ch ICU
Interrupt Request Register 044
IR044
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 702Dh ICU
Interrupt Request Register 045
IR045
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 702Eh ICU
Interrupt Request Register 046
IR046
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 702Fh
ICU
Interrupt Request Register 047
IR047
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7030h
ICU
Interrupt Request Register 048
IR048
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7031h
ICU
Interrupt Request Register 049
IR049
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7032h
ICU
Interrupt Request Register 050
IR050
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7033h
ICU
Interrupt Request Register 051
IR051
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7034h
ICU
Interrupt Request Register 052
IR052
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7035h
ICU
Interrupt Request Register 053
IR053
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7036h
ICU
Interrupt Request Register 054
IR054
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7037h
ICU
Interrupt Request Register 055
IR055
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7038h
ICU
Interrupt Request Register 056
IR056
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7039h
ICU
Interrupt Request Register 057
IR057
8
8
2 ICLK
0008 703Ah ICU
Interrupt Request Register 058
IR058
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 703Bh ICU
Interrupt Request Register 059
IR059
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 703Ch ICU
Interrupt Request Register 060
IR060
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 703Dh ICU
Interrupt Request Register 061
IR061
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 58 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (5/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
ICUb
Remarks
0008 703Eh ICU
Interrupt Request Register 062
IR062
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7040h
ICU
Interrupt Request Register 064
IR064
8
8
2 ICLK
0008 7041h
ICU
Interrupt Request Register 065
IR065
8
8
2 ICLK
0008 7042h
ICU
Interrupt Request Register 066
IR066
8
8
2 ICLK
0008 7043h
ICU
Interrupt Request Register 067
IR067
8
8
2 ICLK
0008 7044h
ICU
Interrupt Request Register 068
IR068
8
8
2 ICLK
0008 7045h
ICU
Interrupt Request Register 069
IR069
8
8
2 ICLK
0008 7046h
ICU
Interrupt Request Register 070
IR070
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7047h
ICU
Interrupt Request Register 071
IR071
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 705Ah ICU
Interrupt Request Register 090
IR090
8
8
2 ICLK
Not present in versions
with 112, 100, 64 or 48
pins.
0008 7062h
ICU
Interrupt Request Register 098
IR098
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7066h
ICU
Interrupt Request Register 102
IR102
8
8
2 ICLK
0008 7067h
ICU
Interrupt Request Register 103
IR103
8
8
2 ICLK
0008 7068h
ICU
Interrupt Request Register 104
IR104
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7069h
ICU
Interrupt Request Register 105
IR105
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 706Ah ICU
Interrupt Request Register 106
IR106
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7072h
ICU
Interrupt Request Register 114
IR114
8
8
2 ICLK
0008 707Ah ICU
Interrupt Request Register 122
IR122
8
8
2 ICLK
0008 707Bh ICU
Interrupt Request Register 123
IR123
8
8
2 ICLK
0008 707Ch ICU
Interrupt Request Register 124
IR124
8
8
2 ICLK
0008 707Dh ICU
Interrupt Request Register 125
IR125
8
8
2 ICLK
0008 707Eh ICU
Interrupt Request Register 126
IR126
8
8
2 ICLK
0008 707Fh
ICU
Interrupt Request Register 127
IR127
8
8
2 ICLK
0008 7080h
ICU
Interrupt Request Register 128
IR128
8
8
2 ICLK
0008 7081h
ICU
Interrupt Request Register 129
IR129
8
8
2 ICLK
0008 7082h
ICU
Interrupt Request Register 130
IR130
8
8
2 ICLK
0008 7083h
ICU
Interrupt Request Register 131
IR131
8
8
2 ICLK
0008 7084h
ICU
Interrupt Request Register 132
IR132
8
8
2 ICLK
0008 7085h
ICU
Interrupt Request Register 133
IR133
8
8
2 ICLK
0008 7086h
ICU
Interrupt Request Register 134
IR134
8
8
2 ICLK
0008 7087h
ICU
Interrupt Request Register 135
IR135
8
8
2 ICLK
0008 7088h
ICU
Interrupt Request Register 136
IR136
8
8
2 ICLK
0008 7089h
ICU
Interrupt Request Register 137
IR137
8
8
2 ICLK
0008 708Ah ICU
Interrupt Request Register 138
IR138
8
8
2 ICLK
0008 708Bh ICU
Interrupt Request Register 139
IR139
8
8
2 ICLK
0008 708Ch ICU
Interrupt Request Register 140
IR140
8
8
2 ICLK
0008 708Dh ICU
Interrupt Request Register 141
IR141
8
8
2 ICLK
0008 708Eh ICU
Interrupt Request Register 142
IR142
8
8
2 ICLK
0008 708Fh
ICU
Interrupt Request Register 143
IR143
8
8
2 ICLK
0008 7090h
ICU
Interrupt Request Register 144
IR144
8
8
2 ICLK
0008 7091h
ICU
Interrupt Request Register 145
IR145
8
8
2 ICLK
0008 7092h
ICU
Interrupt Request Register 146
IR146
8
8
2 ICLK
0008 7093h
ICU
Interrupt Request Register 147
IR147
8
8
2 ICLK
0008 7094h
ICU
Interrupt Request Register 148
IR148
8
8
2 ICLK
0008 7095h
ICU
Interrupt Request Register 149
IR149
8
8
2 ICLK
0008 7096h
ICU
Interrupt Request Register 150
IR150
8
8
2 ICLK
0008 7097h
ICU
Interrupt Request Register 151
IR151
8
8
2 ICLK
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 59 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (6/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
0008 7098h
ICU
Interrupt Request Register 152
IR152
8
8
2 ICLK
0008 7099h
ICU
Interrupt Request Register 153
IR153
8
8
2 ICLK
0008 709Ah ICU
Interrupt Request Register 154
IR154
8
8
2 ICLK
0008 709Bh ICU
Interrupt Request Register 155
IR155
8
8
2 ICLK
0008 709Ch ICU
Interrupt Request Register 156
IR156
8
8
2 ICLK
0008 709Dh ICU
Interrupt Request Register 157
IR157
8
8
2 ICLK
ICLK PCLK
Module
Name
Remarks
ICUb
0008 709Eh ICU
Interrupt Request Register 158
IR158
8
8
2 ICLK
0008 70A1h ICU
Interrupt Request Register 161
IR161
8
8
2 ICLK
0008 70A2h ICU
Interrupt Request Register 162
IR162
8
8
2 ICLK
0008 70A3h ICU
Interrupt Request Register 163
IR163
8
8
2 ICLK
0008 70A4h ICU
Interrupt Request Register 164
IR164
8
8
2 ICLK
0008 70A5h ICU
Interrupt Request Register 165
IR165
8
8
2 ICLK
0008 70A6h ICU
Interrupt Request Register 166
IR166
8
8
2 ICLK
0008 70A7h ICU
Interrupt Request Register 167
IR167
8
8
2 ICLK
0008 70A8h ICU
Interrupt Request Register 168
IR168
8
8
2 ICLK
0008 70A9h ICU
Interrupt Request Register 169
IR169
8
8
2 ICLK
0008 70AAh ICU
Interrupt Request Register 170
IR170
8
8
2 ICLK
0008 70ABh ICU
Interrupt Request Register 171
IR171
8
8
2 ICLK
0008 70ACh ICU
Interrupt Request Register 172
IR172
8
8
2 ICLK
0008 70ADh ICU
Interrupt Request Register 173
IR173
8
8
2 ICLK
0008 70AEh ICU
Interrupt Request Register 174
IR174
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 70AFh ICU
Interrupt Request Register 175
IR175
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 70B0h ICU
Interrupt Request Register 176
IR176
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 70B1h ICU
Interrupt Request Register 177
IR177
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 70B2h ICU
Interrupt Request Register 178
IR178
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 70B3h ICU
Interrupt Request Register 179
IR179
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 70B4h ICU
Interrupt Request Register 180
IR180
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 70B5h ICU
Interrupt Request Register 181
IR181
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 70B6h ICU
Interrupt Request Register 182
IR182
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 70B7h ICU
Interrupt Request Register 183
IR183
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 70B8h ICU
Interrupt Request Register 184
IR184
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 70B9h ICU
Interrupt Request Register 185
IR185
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 70BAh ICU
Interrupt Request Register 186
IR186
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 70BBh ICU
Interrupt Request Register 187
IR187
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 70BCh ICU
Interrupt Request Register 188
IR188
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 70BDh ICU
Interrupt Request Register 189
IR189
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 70BEh ICU
Interrupt Request Register 190
IR190
8
8
2 ICLK
Not present in versions
with 112, 100, 64 or 48
pins.
0008 70BFh ICU
Interrupt Request Register 191
IR191
8
8
2 ICLK
Not present in versions
with 112, 100, 64 or 48
pins.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Not present in versions
with 64 or 48 pins.
Not present in versions
with 64 or 48 pins.
Page 60 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (7/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
Interrupt Request Register 192
IR192
8
8
2 ICLK
0008 70C1h ICU
Interrupt Request Register 193
IR193
8
8
2 ICLK
0008 70C2h ICU
Interrupt Request Register 194
IR194
8
8
2 ICLK
0008 70C3h ICU
Interrupt Request Register 195
IR195
8
8
2 ICLK
0008 70C4h ICU
Interrupt Request Register 196
IR196
8
8
2 ICLK
0008 70C5h ICU
Interrupt Request Register 197
IR197
8
8
2 ICLK
0008 70C6h ICU
Interrupt Request Register 198
IR198
8
8
2 ICLK
0008 70C7h ICU
Interrupt Request Register 199
IR199
8
8
2 ICLK
0008 70C8h ICU
Interrupt Request Register 200
IR200
8
8
2 ICLK
0008 70C9h ICU
Interrupt Request Register 201
IR201
8
8
2 ICLK
0008 70D6h ICU
Interrupt Request Register 214
IR214
8
8
2 ICLK
0008 70D7h ICU
Interrupt Request Register 215
IR215
8
8
2 ICLK
0008 70D8h ICU
Interrupt Request Register 216
IR216
8
8
2 ICLK
0008 70D9h ICU
Interrupt Request Register 217
IR217
8
8
2 ICLK
0008 70DAh ICU
Interrupt Request Register 218
IR218
8
8
2 ICLK
0008 70DBh ICU
Interrupt Request Register 219
IR219
8
8
2 ICLK
0008 70DCh ICU
Interrupt Request Register 220
IR220
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 70DDh ICU
Interrupt Request Register 221
IR221
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 70DEh ICU
Interrupt Request Register 222
IR222
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 70DFh ICU
Interrupt Request Register 223
IR223
8
8
2 ICLK
Not present in versions
with 100, 64 or 48 pins.
0008 70E0h ICU
Interrupt Request Register 224
IR224
8
8
2 ICLK
Not present in versions
with 100, 64 or 48 pins.
0008 70E1h ICU
Interrupt Request Register 225
IR225
8
8
2 ICLK
Not present in versions
with 100, 64 or 48 pins.
0008 70E2h ICU
Interrupt Request Register 226
IR226
8
8
2 ICLK
0008 70E3h ICU
Interrupt Request Register 227
IR227
8
8
2 ICLK
0008 70E4h ICU
Interrupt Request Register 228
IR228
8
8
2 ICLK
0008 70E5h ICU
Interrupt Request Register 229
IR229
8
8
2 ICLK
0008 70E6h ICU
Interrupt Request Register 230
IR230
8
8
2 ICLK
0008 70E7h ICU
Interrupt Request Register 231
IR231
8
8
2 ICLK
0008 70E8h ICU
Interrupt Request Register 232
IR232
8
8
2 ICLK
0008 70E9h ICU
Interrupt Request Register 233
IR233
8
8
2 ICLK
0008 70EAh ICU
Interrupt Request Register 234
IR234
8
8
2 ICLK
0008 70EBh ICU
Interrupt Request Register 235
IR235
8
8
2 ICLK
0008 70ECh ICU
Interrupt Request Register 236
IR236
8
8
2 ICLK
0008 70EEh ICU
Interrupt Request Register 238
IR238
8
8
2 ICLK
0008 70EFh ICU
Interrupt Request Register 239
IR239
8
8
2 ICLK
0008 70F0h
ICU
Interrupt Request Register 240
IR240
8
8
2 ICLK
0008 70F1h
ICU
Interrupt Request Register 241
IR241
8
8
2 ICLK
0008 70F2h
ICU
Interrupt Request Register 242
IR242
8
8
2 ICLK
0008 70F4h
ICU
Interrupt Request Register 244
IR244
8
8
2 ICLK
0008 70F5h
ICU
Interrupt Request Register 245
IR245
8
8
2 ICLK
0008 70F6h
ICU
Interrupt Request Register 246
IR246
8
8
2 ICLK
0008 70F7h
ICU
Interrupt Request Register 247
IR247
8
8
2 ICLK
0008 70F8h
ICU
Interrupt Request Register 248
IR248
8
8
2 ICLK
0008 70FAh ICU
Interrupt Request Register 250
IR250
8
8
2 ICLK
0008 70FBh ICU
Interrupt Request Register 251
IR251
8
8
2 ICLK
0008 70FCh ICU
Interrupt Request Register 252
IR252
8
8
2 ICLK
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
ICUb
Remarks
0008 70C0h ICU
Not present in versions
with 112, 100, 64 or 48
pins.
Not present in versions
with 112, 100, 64 or 48
pins.
Page 61 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (8/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
Remarks
0008 711Bh
ICU
DTC Activation Enable Register 027
DTCER027
8
8
2 ICLK
ICUb
0008 711Ch
ICU
DTC Activation Enable Register 028
DTCER028
8
8
2 ICLK
0008 711Dh
ICU
DTC Activation Enable Register 029
DTCER029
8
8
2 ICLK
0008 711Eh
ICU
DTC Activation Enable Register 030
DTCER030
8
8
2 ICLK
0008 711Fh
ICU
DTC Activation Enable Register 031
DTCER031
8
8
2 ICLK
0008 7121h
ICU
DTC Activation Enable Register 033
DTCER033
8
8
2 ICLK
Not present in versions
with 112, 100, 64 or 48
pins.
0008 7122h
ICU
DTC Activation Enable Register 034
DTCER034
8
8
2 ICLK
Not present in versions
with 112, 100, 64 or 48
pins.
0008 7127h
ICU
DTC Activation Enable Register 039
DTCER039
8
8
2 ICLK
0008 7128h
ICU
DTC Activation Enable Register 040
DTCER040
8
8
2 ICLK
0008 712Ah ICU
DTC Activation Enable Register 042
DTCER042
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 712Bh ICU
DTC Activation Enable Register 043
DTCER043
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7131h
ICU
DTC Activation Enable Register 049
DTCER049
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7132h
ICU
DTC Activation Enable Register 050
DTCER050
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7133h
ICU
DTC Activation Enable Register 051
DTCER051
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7134h
ICU
DTC Activation Enable Register 052
DTCER052
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7135h
ICU
DTC Activation Enable Register 053
DTCER053
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7136h
ICU
DTC Activation Enable Register 054
DTCER054
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7137h
ICU
DTC Activation Enable Register 055
DTCER055
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7138h
ICU
DTC Activation Enable Register 056
DTCER056
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 713Ah ICU
DTC Activation Enable Register 058
DTCER058
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 713Bh ICU
DTC Activation Enable Register 059
DTCER059
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 713Ch ICU
DTC Activation Enable Register 060
DTCER060
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 713Dh ICU
DTC Activation Enable Register 061
DTCER061
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 713Eh ICU
DTC Activation Enable Register 062
DTCER062
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7140h
ICU
DTC Activation Enable Register 064
DTCER064
8
8
2 ICLK
0008 7141h
ICU
DTC Activation Enable Register 065
DTCER065
8
8
2 ICLK
0008 7142h
ICU
DTC Activation Enable Register 066
DTCER066
8
8
2 ICLK
0008 7143h
ICU
DTC Activation Enable Register 067
DTCER067
8
8
2 ICLK
0008 7144h
ICU
DTC Activation Enable Register 068
DTCER068
8
8
2 ICLK
0008 7145h
ICU
DTC Activation Enable Register 069
DTCER069
8
8
2 ICLK
0008 7146h
ICU
DTC Activation Enable Register 070
DTCER070
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7147h
ICU
DTC Activation Enable Register 071
DTCER071
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7162h
ICU
DTC Activation Enable Register 098
DTCER098
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7166h
ICU
DTC Activation Enable Register 102
DTCER102
8
8
2 ICLK
0008 7167h
ICU
DTC Activation Enable Register 103
DTCER103
8
8
2 ICLK
0008 7168h
ICU
DTC Activation Enable Register 104
DTCER104
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7169h
ICU
DTC Activation Enable Register 105
DTCER105
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 717Eh ICU
DTC Activation Enable Register 126
DTCER126
8
8
2 ICLK
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 62 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (9/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
Remarks
0008 717Fh
ICU
DTC Activation Enable Register 127
DTCER127
8
8
2 ICLK
0008 7180h
ICU
DTC Activation Enable Register 128
DTCER128
8
8
2 ICLK
0008 7181h
ICU
DTC Activation Enable Register 129
DTCER129
8
8
2 ICLK
0008 7185h
ICU
DTC Activation Enable Register 133
DTCER133
8
8
2 ICLK
0008 7186h
ICU
DTC Activation Enable Register 134
DTCER134
8
8
2 ICLK
0008 7189h
ICU
DTC Activation Enable Register 137
DTCER137
8
8
2 ICLK
0008 718Ah ICU
DTC Activation Enable Register 138
DTCER138
8
8
2 ICLK
0008 718Dh ICU
DTC Activation Enable Register 141
DTCER141
8
8
2 ICLK
0008 718Eh ICU
DTC Activation Enable Register 142
DTCER142
8
8
2 ICLK
0008 718Fh
ICU
DTC Activation Enable Register 143
DTCER143
8
8
2 ICLK
0008 7190h
ICU
DTC Activation Enable Register 144
DTCER144
8
8
2 ICLK
0008 7192h
ICU
DTC Activation Enable Register 146
DTCER146
8
8
2 ICLK
0008 7193h
ICU
DTC Activation Enable Register 147
DTCER147
8
8
2 ICLK
0008 7194h
ICU
DTC Activation Enable Register 148
DTCER148
8
8
2 ICLK
0008 7195h
ICU
DTC Activation Enable Register 149
DTCER149
8
8
2 ICLK
0008 7196h
ICU
DTC Activation Enable Register 150
DTCER150
8
8
2 ICLK
0008 7197h
ICU
DTC Activation Enable Register 151
DTCER151
8
8
2 ICLK
0008 7198h
ICU
DTC Activation Enable Register 152
DTCER152
8
8
2 ICLK
0008 7199h
ICU
DTC Activation Enable Register 153
DTCER153
8
8
2 ICLK
0008 719Ah ICU
DTC Activation Enable Register 154
DTCER154
8
8
2 ICLK
0008 719Bh ICU
DTC Activation Enable Register 155
DTCER155
8
8
2 ICLK
0008 719Ch ICU
DTC Activation Enable Register 156
DTCER156
8
8
2 ICLK
0008 719Dh ICU
DTC Activation Enable Register 157
DTCER157
8
8
2 ICLK
0008 71A1h ICU
DTC Activation Enable Register 161
DTCER161
8
8
2 ICLK
0008 71A2h ICU
DTC Activation Enable Register 162
DTCER162
8
8
2 ICLK
0008 71A3h ICU
DTC Activation Enable Register 163
DTCER163
8
8
2 ICLK
0008 71A4h ICU
DTC Activation Enable Register 164
DTCER164
8
8
2 ICLK
0008 71A5h ICU
DTC Activation Enable Register 165
DTCER165
8
8
2 ICLK
0008 71ABh ICU
DTC Activation Enable Register 171
DTCER171
8
8
2 ICLK
0008 71ACh ICU
DTC Activation Enable Register 172
DTCER172
8
8
2 ICLK
0008 71ADh ICU
DTC Activation Enable Register 173
DTCER173
8
8
2 ICLK
0008 71AEh ICU
DTC Activation Enable Register 174
DTCER174
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 71AFh ICU
DTC Activation Enable Register 175
DTCER175
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 71B0h ICU
DTC Activation Enable Register 176
DTCER176
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 71B1h ICU
DTC Activation Enable Register 177
DTCER177
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 71B2h ICU
DTC Activation Enable Register 178
DTCER178
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 71B3h ICU
DTC Activation Enable Register 179
DTCER179
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 71B4h ICU
DTC Activation Enable Register 180
DTCER180
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 71B5h ICU
DTC Activation Enable Register 181
DTCER181
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 71B6h ICU
DTC Activation Enable Register 182
DTCER182
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 71B7h ICU
DTC Activation Enable Register 183
DTCER183
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 71B8h ICU
DTC Activation Enable Register 184
DTCER184
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 71B9h ICU
DTC Activation Enable Register 185
DTCER185
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 71BAh ICU
DTC Activation Enable Register 186
DTCER186
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
ICUb
Page 63 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (10/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
DTC Activation Enable Register 187
DTCER187
8
8
2 ICLK
0008 71BCh ICU
DTC Activation Enable Register 188
DTCER188
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 71BDh ICU
DTC Activation Enable Register 189
DTCER189
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 71BFh ICU
DTC Activation Enable Register 191
DTCER191
8
8
2 ICLK
Not present in versions
with 112, 100, 64 or 48
pins.
0008 71C0h ICU
DTC Activation Enable Register 192
DTCER192
8
8
2 ICLK
Not present in versions
with 112, 100, 64 or 48
pins.
0008 71C3h ICU
DTC Activation Enable Register 195
DTCER195
8
8
2 ICLK
0008 71C4h ICU
DTC Activation Enable Register 196
DTCER196
8
8
2 ICLK
0008 71C6h ICU
DTC Activation Enable Register 198
DTCER198
8
8
2 ICLK
0008 71C7h ICU
DTC Activation Enable Register 199
DTCER199
8
8
2 ICLK
0008 71C8h ICU
DTC Activation Enable Register 200
DTCER200
8
8
2 ICLK
0008 71C9h ICU
DTC Activation Enable Register 201
DTCER201
8
8
2 ICLK
0008 71D6h ICU
DTC Activation Enable Register 214
DTCER214
8
8
2 ICLK
0008 71D7h ICU
DTC Activation Enable Register 215
DTCER215
8
8
2 ICLK
0008 71D9h ICU
DTC Activation Enable Register 217
DTCER217
8
8
2 ICLK
0008 71DAh ICU
DTC Activation Enable Register 218
DTCER218
8
8
2 ICLK
0008 71DCh ICU
DTC Activation Enable Register 220
DTCER220
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 71DDh ICU
DTC Activation Enable Register 221
DTCER221
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 71DFh ICU
DTC Activation Enable Register 223
DTCER223
8
8
2 ICLK
Not present in versions
with 100, 64 or 48 pins.
0008 71E0h ICU
DTC Activation Enable Register 224
DTCER224
8
8
2 ICLK
Not present in versions
with 100, 64 or 48 pins.
0008 71E2h ICU
DTC Activation Enable Register 226
DTCER226
8
8
2 ICLK
0008 71E3h ICU
DTC Activation Enable Register 227
DTCER227
8
8
2 ICLK
0008 71E4h ICU
DTC Activation Enable Register 228
DTCER228
8
8
2 ICLK
0008 71E5h ICU
DTC Activation Enable Register 229
DTCER229
8
8
2 ICLK
0008 71E6h ICU
DTC Activation Enable Register 230
DTCER230
8
8
2 ICLK
0008 71E7h ICU
DTC Activation Enable Register 231
DTCER231
8
8
2 ICLK
0008 71E8h ICU
DTC Activation Enable Register 232
DTCER232
8
8
2 ICLK
0008 71E9h ICU
DTC Activation Enable Register 233
DTCER233
8
8
2 ICLK
0008 71EAh ICU
DTC Activation Enable Register 234
DTCER234
8
8
2 ICLK
0008 71EBh ICU
DTC Activation Enable Register 235
DTCER235
8
8
2 ICLK
0008 71ECh ICU
DTC Activation Enable Register 236
DTCER236
8
8
2 ICLK
0008 71EEh ICU
DTC Activation Enable Register 238
DTCER238
8
8
2 ICLK
0008 71EFh ICU
DTC Activation Enable Register 239
DTCER239
8
8
2 ICLK
0008 71F0h
ICU
DTC Activation Enable Register 240
DTCER240
8
8
2 ICLK
0008 71F1h
ICU
DTC Activation Enable Register 241
DTCER241
8
8
2 ICLK
0008 71F2h
ICU
DTC Activation Enable Register 242
DTCER242
8
8
2 ICLK
0008 71F4h
ICU
DTC Activation Enable Register 244
DTCER244
8
8
2 ICLK
0008 71F5h
ICU
DTC Activation Enable Register 245
DTCER245
8
8
2 ICLK
0008 71F6h
ICU
DTC Activation Enable Register 246
DTCER246
8
8
2 ICLK
0008 71F7h
ICU
DTC Activation Enable Register 247
DTCER247
8
8
2 ICLK
0008 71F8h
ICU
DTC Activation Enable Register 248
DTCER248
8
8
2 ICLK
0008 71FAh ICU
DTC Activation Enable Register 250
DTCER250
8
8
2 ICLK
0008 71FBh ICU
DTC Activation Enable Register 251
DTCER251
8
8
2 ICLK
0008 7202h
ICU
Interrupt Request Enable Register 02
IER02
8
8
2 ICLK
0008 7203h
ICU
Interrupt Request Enable Register 03
IER03
8
8
2 ICLK
0008 7204h
ICU
Interrupt Request Enable Register 04
IER04
8
8
2 ICLK
0008 7205h
ICU
Interrupt Request Enable Register 05
IER05
8
8
2 ICLK
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
ICUb
Remarks
0008 71BBh ICU
Not present in versions
with 64 or 48 pins.
Page 64 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (11/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
0008 7206h
ICU
Interrupt Request Enable Register 06
IER06
8
8
2 ICLK
0008 7207h
ICU
Interrupt Request Enable Register 07
IER07
8
8
2 ICLK
0008 7208h
ICU
Interrupt Request Enable Register 08
IER08
8
8
2 ICLK
0008 720Bh ICU
Interrupt Request Enable Register 0B
IER0B
8
8
2 ICLK
0008 720Ch ICU
Interrupt Request Enable Register 0C
IER0C
8
8
2 ICLK
0008 720Dh ICU
Interrupt Request Enable Register 0D
IER0D
8
8
2 ICLK
0008 720Eh ICU
Interrupt Request Enable Register 0E
IER0E
8
8
2 ICLK
0008 720Fh
Interrupt Request Enable Register 0F
IER0F
8
8
2 ICLK
ICU
ICLK PCLK
Module
Name
ICUb
Remarks
Not present in versions
with 64 or 48 pins.
Not present in versions
with 112, 100, 64 or 48
pins.
Not present in versions
with 64 or 48 pins.
0008 7210h
ICU
Interrupt Request Enable Register 10
IER10
8
8
2 ICLK
0008 7211h
ICU
Interrupt Request Enable Register 11
IER11
8
8
2 ICLK
0008 7212h
ICU
Interrupt Request Enable Register 12
IER12
8
8
2 ICLK
0008 7213h
ICU
Interrupt Request Enable Register 13
IER13
8
8
2 ICLK
0008 7214h
ICU
Interrupt Request Enable Register 14
IER14
8
8
2 ICLK
0008 7215h
ICU
Interrupt Request Enable Register 15
IER15
8
8
2 ICLK
0008 7216h
ICU
Interrupt Request Enable Register 16
IER16
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7217h
ICU
Interrupt Request Enable Register 17
IER17
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7218h
ICU
Interrupt Request Enable Register 18
IER18
8
8
2 ICLK
0008 7219h
ICU
Interrupt Request Enable Register 19
IER19
8
8
2 ICLK
0008 721Ah ICU
Interrupt Request Enable Register 1A
IER1A
8
8
2 ICLK
0008 721Bh ICU
Interrupt Request Enable Register 1B
IER1B
8
8
2 ICLK
0008 721Ch ICU
Interrupt Request Enable Register 1C
IER1C
8
8
2 ICLK
0008 721Dh ICU
Interrupt Request Enable Register 1D
IER1D
8
8
2 ICLK
0008 721Eh ICU
Interrupt Request Enable Register 1E
IER1E
8
8
2 ICLK
0008 721Fh
ICU
Interrupt Request Enable Register 1F
IER1F
8
8
2 ICLK
0008 72E0h ICU
Software Interrupt Activation Register
SWINTR
8
8
2 ICLK
0008 72F0h
ICU
Fast Interrupt Set Register
FIR
16
16
2 ICLK
0008 7300h
ICU
Interrupt Source Priority Register 000
IPR000
8
8
2 ICLK
0008 7301h
ICU
Interrupt Source Priority Register 001
IPR001
8
8
2 ICLK
0008 7302h
ICU
Interrupt Source Priority Register 002
IPR002
8
8
2 ICLK
0008 7303h
ICU
Interrupt Source Priority Register 003
IPR003
8
8
2 ICLK
0008 7304h
ICU
Interrupt Source Priority Register 004
IPR004
8
8
2 ICLK
0008 7305h
ICU
Interrupt Source Priority Register 005
IPR005
8
8
2 ICLK
0008 7306h
ICU
Interrupt Source Priority Register 006
IPR006
8
8
2 ICLK
0008 7307h
ICU
Interrupt Source Priority Register 007
IPR007
8
8
2 ICLK
0008 7321h
ICU
Interrupt Source Priority Register 033
IPR033
8
8
2 ICLK
Not present in versions
with 112, 100, 64 or 48
pins.
0008 7322h
ICU
Interrupt Source Priority Register 034
IPR034
8
8
2 ICLK
Not present in versions
with 112, 100, 64 or 48
pins.
0008 7323h
ICU
Interrupt Source Priority Register 035
IPR035
8
8
2 ICLK
Not present in versions
with 112, 100, 64 or 48
pins.
0008 7324h
ICU
Interrupt Source Priority Register 036
IPR036
8
8
2 ICLK
0008 7327h
ICU
Interrupt Source Priority Register 039
IPR039
8
8
2 ICLK
0008 7328h
ICU
Interrupt Source Priority Register 040
IPR040
8
8
2 ICLK
0008 7329h
ICU
Interrupt Source Priority Register 041
IPR041
8
8
2 ICLK
0008 732Ah ICU
Interrupt Source Priority Register 042
IPR042
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 732B
Interrupt Source Priority Register 043
IPR043
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
ICU
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 65 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (12/48)
Number of Access States
Address
0008 732C
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
Remarks
ICU
Interrupt Source Priority Register 044
IPR044
8
8
2 ICLK
0008 732Dh ICU
Interrupt Source Priority Register 045
IPR045
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7331h
ICU
Interrupt Source Priority Register 049
IPR049
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7334h
ICU
Interrupt Source Priority Register 052
IPR052
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7336h
ICU
Interrupt Source Priority Register 054
IPR054
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7337h
ICU
Interrupt Source Priority Register 055
IPR055
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7338h
ICU
Interrupt Source Priority Register 056
IPR056
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7339h
ICUb
Not present in versions
with 64 or 48 pins.
ICU
Interrupt Source Priority Register 057
IPR057
8
8
2 ICLK
0008 733Ah ICU
Interrupt Source Priority Register 058
IPR058
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 733Bh ICU
Interrupt Source Priority Register 059
IPR059
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 733Ch ICU
Interrupt Source Priority Register 060
IPR060
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 733Dh ICU
Interrupt Source Priority Register 061
IPR061
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 733Eh ICU
Interrupt Source Priority Register 062
IPR062
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7340h
ICU
Interrupt Source Priority Register 064
IPR064
8
8
2 ICLK
0008 7341h
ICU
Interrupt Source Priority Register 065
IPR065
8
8
2 ICLK
0008 7342h
ICU
Interrupt Source Priority Register 066
IPR066
8
8
2 ICLK
0008 7343h
ICU
Interrupt Source Priority Register 067
IPR067
8
8
2 ICLK
0008 7344h
ICU
Interrupt Source Priority Register 068
IPR068
8
8
2 ICLK
0008 7345h
ICU
Interrupt Source Priority Register 069
IPR069
8
8
2 ICLK
0008 7346h
ICU
Interrupt Source Priority Register 070
IPR070
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7347h
ICU
Interrupt Source Priority Register 071
IPR071
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 735Ah ICU
Interrupt Source Priority Register 090
IPR090
8
8
2 ICLK
Not present in versions
with 112, 100, 64 or 48
pins.
0008 7362h
ICU
Interrupt Source Priority Register 098
IPR098
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7366h
ICU
Interrupt Source Priority Register 102
IPR102
8
8
2 ICLK
0008 7367h
ICU
Interrupt Source Priority Register 103
IPR103
8
8
2 ICLK
0008 7368h
ICU
Interrupt Source Priority Register 104
IPR104
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7369h
ICU
Interrupt Source Priority Register 105
IPR105
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 736Ah ICU
Interrupt Source Priority Register 106
IPR106
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 7372h
ICU
Interrupt Source Priority Register 114
IPR114
8
8
2 ICLK
0008 737Ah ICU
Interrupt Source Priority Register 122
IPR122
8
8
2 ICLK
0008 737Eh ICU
Interrupt Source Priority Register 126
IPR126
8
8
2 ICLK
0008 7382h
ICU
Interrupt Source Priority Register 130
IPR130
8
8
2 ICLK
0008 7385h
ICU
Interrupt Source Priority Register 133
IPR133
8
8
2 ICLK
0008 7387h
ICU
Interrupt Source Priority Register 135
IPR135
8
8
2 ICLK
0008 7389h
ICU
Interrupt Source Priority Register 137
IPR137
8
8
2 ICLK
0008 738Bh ICU
Interrupt Source Priority Register 139
IPR139
8
8
2 ICLK
0008 738Dh ICU
Interrupt Source Priority Register 141
IPR141
8
8
2 ICLK
0008 7391h
ICU
Interrupt Source Priority Register 145
IPR145
8
8
2 ICLK
0008 7392h
ICU
Interrupt Source Priority Register 146
IPR146
8
8
2 ICLK
0008 7396h
ICU
Interrupt Source Priority Register 150
IPR150
8
8
2 ICLK
0008 7397h
ICU
Interrupt Source Priority Register 151
IPR151
8
8
2 ICLK
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 66 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (13/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
Remarks
0008 739Ah ICU
Interrupt Source Priority Register 154
IPR154
8
8
2 ICLK
0008 739Eh ICU
Interrupt Source Priority Register 158
IPR158
8
8
2 ICLK
0008 73A1h ICU
Interrupt Source Priority Register 161
IPR161
8
8
2 ICLK
0008 73A3h ICU
Interrupt Source Priority Register 163
IPR163
8
8
2 ICLK
0008 73A5h ICU
Interrupt Source Priority Register 165
IPR165
8
8
2 ICLK
0008 73A6h ICU
Interrupt Source Priority Register 166
IPR166
8
8
2 ICLK
0008 73ABh ICU
Interrupt Source Priority Register 171
IPR171
8
8
2 ICLK
0008 73ACh ICU
Interrupt Source Priority Register 172
IPR172
8
8
2 ICLK
0008 73ADh ICU
Interrupt Source Priority Register 173
IPR173
8
8
2 ICLK
0008 73AEh ICU
Interrupt Source Priority Register 174
IPR174
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 73B1h ICU
Interrupt Source Priority Register 177
IPR177
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 73B4h ICU
Interrupt Source Priority Register 180
IPR180
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 73B7h ICU
Interrupt Source Priority Register 183
IPR183
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 73B9h ICU
Interrupt Source Priority Register 185
IPR185
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 73BCh ICU
Interrupt Source Priority Register 188
IPR188
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 73BEh ICU
Interrupt Source Priority Register 190
IPR190
8
8
2 ICLK
Not present in versions
with 112, 100, 64 or 48
pins.
0008 73C2h ICU
Interrupt Source Priority Register 194
IPR194
8
8
2 ICLK
0008 73C6h ICU
Interrupt Source Priority Register 198
IPR198
8
8
2 ICLK
0008 73C7h ICU
Interrupt Source Priority Register 199
IPR199
8
8
2 ICLK
0008 73C8h ICU
Interrupt Source Priority Register 200
IPR200
8
8
2 ICLK
0008 73C9h ICU
Interrupt Source Priority Register 201
IPR201
8
8
2 ICLK
0008 73D6h ICU
Interrupt Source Priority Register 214
IPR214
8
8
2 ICLK
0008 73D9h ICU
Interrupt Source Priority Register 217
IPR217
8
8
2 ICLK
0008 73DCh ICU
Interrupt Source Priority Register 220
IPR220
8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 73DFh ICU
Interrupt Source Priority Register 223
IPR223
8
8
2 ICLK
Not present in versions
with 100, 64 or 48 pins.
0008 73E2h ICU
Interrupt Source Priority Register 226
IPR226
8
8
2 ICLK
0008 73E5h ICU
Interrupt Source Priority Register 229
IPR229
8
8
2 ICLK
0008 73E8h ICU
Interrupt Source Priority Register 232
IPR232
8
8
2 ICLK
0008 73EBh ICU
Interrupt Source Priority Register 235
IPR235
8
8
2 ICLK
0008 73EEh ICU
Interrupt Source Priority Register 238
IPR238
8
8
2 ICLK
0008 73F1h
ICU
Interrupt Source Priority Register 241
IPR241
8
8
2 ICLK
0008 73F4h
ICU
Interrupt Source Priority Register 244
IPR244
8
8
2 ICLK
0008 73F7h
2 ICLK
ICU
Interrupt Source Priority Register 247
IPR247
8
8
0008 73FAh ICU
Interrupt Source Priority Register 250
IPR250
8
8
2 ICLK
0008 7400h
ICU
DMAC Activation Request Select Register 0 DMRSR0
8
8
2 ICLK
0008 7404h
ICU
DMAC Activation Request Select Register 1 DMRSR1
8
8
2 ICLK
0008 7408h
ICU
DMAC Activation Request Select Register 2 DMRSR2
8
8
2 ICLK
0008 740Ch ICU
DMAC Activation Request Select Register 3 DMRSR3
8
8
2 ICLK
0008 7500h
ICU
IRQ Control Register 0
IRQCR0
8
8
2 ICLK
0008 7501h
ICU
IRQ Control Register 1
IRQCR1
8
8
2 ICLK
0008 7502h
ICU
IRQ Control Register 2
IRQCR2
8
8
2 ICLK
0008 7503h
ICU
IRQ Control Register 3
IRQCR3
8
8
2 ICLK
0008 7504h
ICU
IRQ Control Register 4
IRQCR4
8
8
2 ICLK
0008 7505h
ICU
IRQ Control Register 5
IRQCR5
8
8
2 ICLK
0008 7506h
ICU
IRQ Control Register 6
IRQCR6
8
8
2 ICLK
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
ICUb
Not present in versions
with 64 or 48 pins.
Page 67 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (14/48)
Number of Access States
Address
0008 7507h
Module
Symbol
ICU
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
IRQ Control Register 7
IRQCR7
8
8
2 ICLK
Register Name
0008 7510h
ICU
IRQ Pin Digital Filter Enable Register 0
IRQFLTE0
8
8
2 ICLK
0008 7514h
ICU
IRQ Pin Digital Filter Setting Register 0
IRQFLTC0
16
16
2 ICLK
0008 7580h
ICU
Non-Maskable Interrupt Status Register
NMISR
8
8
2 ICLK
0008 7581h
ICU
Non-Maskable Interrupt Enable Register
NMIER
8
8
2 ICLK
0008 7582h
ICU
Non-Maskable Interrupt Status Clear
Register
NMICLR
8
8
2 ICLK
0008 7583h
ICU
NMI Pin Interrupt Control Register
NMICR
8
8
2 ICLK
0008 7590h
ICU
NMI Pin Digital Filter Enable Register
NMIFLTE
8
8
2 ICLK
0008 7594h
ICU
NMI Pin Digital Filter Setting Register
NMIFLTC
8
8
2 ICLK
ICLK PCLK
ICUb
0008 8000h
CMT
Compare Match Timer Start Register 0
CMSTR0
16
16
2, 3 PCLKB
2 ICLK
0008 8002h
CMT0
Compare Match Timer Control Register
CMCR
16
16
2, 3 PCLKB
2 ICLK
0008 8004h
CMT0
Compare Match Timer Counter
CMCNT
16
16
2, 3 PCLKB
2 ICLK
2 ICLK
0008 8006h
CMT0
Compare Match Timer Constant Register
CMCOR
16
16
2, 3 PCLKB
0008 8008h
CMT1
Compare Match Timer Control Register
CMCR
16
16
2, 3 PCLKB
2 ICLK
0008 800Ah CMT1
Compare Match Timer Counter
CMCNT
16
16
2, 3 PCLKB
2 ICLK
0008 800Ch CMT1
Compare Match Timer Constant Register
CMCOR
16
16
2, 3 PCLKB
2 ICLK
0008 8010h
CMT
Compare Match Timer Start Register 1
CMSTR1
16
16
2, 3 PCLKB
2 ICLK
0008 8012h
CMT2
Compare Match Timer Control Register
CMCR
16
16
2, 3 PCLKB
2 ICLK
0008 8014h
CMT2
Compare Match Timer Counter
CMCNT
16
16
2, 3 PCLKB
2 ICLK
0008 8016h
CMT2
Compare Match Timer Constant Register
CMCOR
16
16
2, 3 PCLKB
2 ICLK
0008 8018h
CMT3
Compare Match Timer Control Register
CMCR
16
16
2, 3 PCLKB
2 ICLK
Compare Match Timer Counter
CMCNT
16
16
2, 3 PCLKB
2 ICLK
0008 801Ch CMT3
Compare Match Timer Constant Register
CMCOR
16
16
2, 3 PCLKB
2 ICLK
0008 8020h
WDT
WDT Refresh Register
WDTRR
8
8
2, 3 PCLKB
2 ICLK
0008 8022h
WDT
WDT Control Register
WDTCR
16
16
2, 3 PCLKB
2 ICLK
0008 8024h
WDT
WDT Status Register
WDTSR
16
16
2, 3 PCLKB
2 ICLK
0008 8026h
WDT
WDT Reset Control Register
WDTRCR
8
8
2, 3 PCLKB
2 ICLK
0008 8030h
IWDT
IWDT Refresh Register
IWDTRR
8
8
2, 3 PCLKB
2 ICLK
0008 8032h
IWDT
IWDT Control Register
IWDTCR
16
16
2, 3 PCLKB
2 ICLK
0008 801Ah CMT3
Module
Name
Remarks
Not present in versions
with 64 or 48 pins.
CMT
WDTA
IWDTa
0008 8034h
IWDT
IWDT Status Register
IWDTSR
16
16
2, 3 PCLKB
2 ICLK
0008 8036h
IWDT
IWDT Reset Control Register
IWDTRCR
8
8
2, 3 PCLKB
2 ICLK
0008 8038h
IWDT
IWDT Count Stop Control Register
IWDTCSTPR 8
8
2, 3 PCLKB
2 ICLK
0008 80C0h DA
D/A Data Register 0
DADR0
16
16
2, 3 PCLKB
2 ICLK
0008 80C2h DA
D/A Data Register 1
DADR1
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 80C4h DA
D/A Control Register
DACR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 80C5h DA
DADRm Format Select Register
DADPR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 80C6h DA
D/A A/D Synchronous Start Control Register
DAADSCR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 8280h
CRC
CRC Control Register
CRCCR
8
8
2, 3 PCLKB
2 ICLK
0008 8281h
CRC
CRC Data Input Register
CRCDIR
8
8
2, 3 PCLKB
2 ICLK
0008 8282h
CRC
CRC Data Output Register
CRCDOR
16
16
2, 3 PCLKB
2 ICLK
0008 8300h
RIIC0
I2C
Bus Control Register 1
ICCR1
8
8
2, 3 PCLKB
2 ICLK
0008 8301h
RIIC0
I2C Bus Control Register 2
ICCR2
8
8
2, 3 PCLKB
2 ICLK
0008 8302h
RIIC0
I2C Bus Mode Register 1
ICMR1
8
8
2, 3 PCLKB
2 ICLK
0008 8303h
RIIC0
I2C Bus Mode Register 2
ICMR2
8
8
2, 3 PCLKB
2 ICLK
0008 8304h
RIIC0
I2C Bus Mode Register 3
ICMR3
8
8
2, 3 PCLKB
2 ICLK
0008 8305h
RIIC0
I2C Bus Function Enable Register
ICFER
8
8
2, 3 PCLKB
2 ICLK
0008 8306h
RIIC0
I2C Bus Status Enable Register
ICSER
8
8
2, 3 PCLKB
2 ICLK
0008 8307h
RIIC0
I2C Bus Interrupt Enable Register
ICIER
8
8
2, 3 PCLKB
2 ICLK
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
DAa
Not present in versions
with 64 or 48 pins.
CRC
RIIC
Page 68 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (15/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
RIIC
0008 8308h
RIIC0
I2C Bus Status Register 1
ICSR1
8
8
2, 3 PCLKB
2 ICLK
0008 8309h
RIIC0
I2C Bus Status Register 2
ICSR2
8
8
2, 3 PCLKB
2 ICLK
Remarks
0008 830Ah RIIC0
Slave Address Register L0
SARL0
8
8
2, 3 PCLKB
2 ICLK
0008 830Ah RIIC0
Timeout Internal Counter L
TMOCNTL
8
8
2, 3 PCLKB
2 ICLK
0008 830Bh RIIC0
Slave Address Register U0
SARU0
8
8
2, 3 PCLKB
2 ICLK
0008 830Bh RIIC0
Timeout Internal Counter U
TMOCNTU
8
8*2
2, 3 PCLKB
2 ICLK
0008 830Ch RIIC0
Slave Address Register L1
SARL1
8
8
2, 3 PCLKB
2 ICLK
0008 830Dh RIIC0
Slave Address Register U1
SARU1
8
8
2, 3 PCLKB
2 ICLK
0008 830Eh RIIC0
Slave Address Register L2
SARL2
8
8
2, 3 PCLKB
2 ICLK
0008 830Fh
RIIC0
Slave Address Register U2
SARU2
8
8
2, 3 PCLKB
2 ICLK
0008 8310h
RIIC0
I2C Bus Bit Rate Low-Level Register
ICBRL
8
8
2, 3 PCLKB
2 ICLK
0008 8311h
RIIC0
I2C Bus Bit Rate High-Level Register
ICBRH
8
8
2, 3 PCLKB
2 ICLK
0008 8312h
RIIC0
I2C Bus Transmit Data Register
ICDRT
8
8
2, 3 PCLKB
2 ICLK
0008 8313h
RIIC0
I2C Bus Receive Data Register
ICDRR
8
8
2, 3 PCLKB
2 ICLK
0008 8320h
RIIC1
I2C Bus Control Register 1
ICCR1
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 8321h
RIIC1
I2C Bus Control Register 2
ICCR2
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 8322h
RIIC1
I2C Bus Mode Register 1
ICMR1
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 8323h
RIIC1
I2C Bus Mode Register 2
ICMR2
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 8324h
RIIC1
I2C Bus Mode Register 3
ICMR3
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 8325h
RIIC1
I2C Bus Function Enable Register
ICFER
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 8326h
RIIC1
I2C Bus Status Enable Register
ICSER
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 8327h
RIIC1
I2C Bus Interrupt Enable Register
ICIER
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 8328h
RIIC1
I2C Bus Status Register 1
ICSR1
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 8329h
RIIC1
I2C Bus Status Register 2
ICSR2
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 832Ah RIIC1
Slave Address Register L0
SARL0
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 832Ah RIIC1
Timeout Internal Counter L
TMOCNTL
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 832Bh RIIC1
Slave Address Register U0
SARU0
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 832Bh RIIC1
Timeout Internal Counter U
TMOCNTU
8
8*2
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 832Ch RIIC1
Slave Address Register L1
SARL1
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 832Dh RIIC1
Slave Address Register U1
SARU1
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 832Eh RIIC1
Slave Address Register L2
SARL2
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 832Fh
Slave Address Register U2
SARU2
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
RIIC1
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 69 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (16/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
Remarks
0008 8330h
RIIC1
I2C Bus Bit Rate Low-Level Register
ICBRL
8
8
2, 3 PCLKB
2 ICLK
0008 8331h
RIIC1
I2C Bus Bit Rate High-Level Register
ICBRH
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 8332h
RIIC1
I2C Bus Transmit Data Register
ICDRT
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 8333h
RIIC1
I2C Bus Receive Data Register
ICDRR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 8380h
RSPI0
RSPI Control Register
SPCR
8
8
2, 3 PCLKB
2 ICLK
0008 8381h
RSPI0
RSPI Slave Select Polarity Register
SSLP
8
8
2, 3 PCLKB
2 ICLK
0008 8382h
RSPI0
RSPI Pin Control Register
SPPCR
8
8
2, 3 PCLKB
2 ICLK
0008 8383h
RSPI0
RSPI Status Register
SPSR
8
8
2, 3 PCLKB
2 ICLK
0008 8384h
RSPI0
RSPI Data Register
SPDR
32
16, 32
2, 3 PCLKB
2 ICLK
0008 8388h
RSPI0
RSPI Sequence Control Register
SPSCR
8
8
2, 3 PCLKB
2 ICLK
0008 8389h
RSPI0
RSPI Sequence Status Register
SPSSR
8
8
2, 3 PCLKB
2 ICLK
0008 838Ah RSPI0
RSPI Bit Rate Register
SPBR
8
8
2, 3 PCLKB
2 ICLK
0008 838Bh RSPI0
RSPI Data Control Register
SPDCR
8
8
2, 3 PCLKB
2 ICLK
RIIC
Not present in versions
with 112, 100, 64, or 48
pins.
RSPI
0008 838Ch RSPI0
RSPI Clock Delay Register
SPCKD
8
8
2, 3 PCLKB
2 ICLK
0008 838Dh RSPI0
RSPI Slave Select Negation Delay Register
SSLND
8
8
2, 3 PCLKB
2 ICLK
0008 838Eh RSPI0
RSPI Next-Access Delay Register
SPND
8
8
2, 3 PCLKB
2 ICLK
0008 838Fh
RSPI0
RSPI Control Register 2
SPCR2
8
8
2, 3 PCLKB
2 ICLK
0008 8390h
RSPI0
RSPI Command Register 0
SPCMD0
16
16
2, 3 PCLKB
2 ICLK
0008 8392h
RSPI0
RSPI Command Register 1
SPCMD1
16
16
2, 3 PCLKB
2 ICLK
0008 8394h
RSPI0
RSPI Command Register 2
SPCMD2
16
16
2, 3 PCLKB
2 ICLK
0008 8396h
RSPI0
RSPI Command Register 3
SPCMD3
16
16
2, 3 PCLKB
2 ICLK
0008 8398h
RSPI0
RSPI Command Register 4
SPCMD4
16
16
2, 3 PCLKB
2 ICLK
0008 839Ah RSPI0
RSPI Command Register 5
SPCMD5
16
16
2, 3 PCLKB
2 ICLK
0008 839Ch RSPI0
RSPI Command Register 6
SPCMD6
16
16
2, 3 PCLKB
2 ICLK
0008 839Eh RSPI0
RSPI Command Register 7
SPCMD7
16
16
2, 3 PCLKB
2 ICLK
0008 83A0h RSPI1
RSPI Control Register
SPCR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 83A1h RSPI1
RSPI Slave Select Polarity Register
SSLP
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 83A2h RSPI1
RSPI Pin Control Register
SPPCR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 83A3h RSPI1
RSPI Status Register
SPSR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 83A4h RSPI1
RSPI Data Register
SPDR
32
16, 32
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 83A8h RSPI1
RSPI Sequence Control Register
SPSCR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 83A9h RSPI1
RSPI Sequence Status Register
SPSSR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 83AAh RSPI1
RSPI Bit Rate Register
SPBR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 83ABh RSPI1
RSPI Data Control Register
SPDCR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 83ACh RSPI1
RSPI Clock Delay Register
SPCKD
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 83ADh RSPI1
RSPI Slave Select Negation Delay Register
SSLND
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 83AEh RSPI1
RSPI Next-Access Delay Register
SPND
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 83AFh RSPI1
RSPI Control Register 2
SPCR2
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 83B0h RSPI1
RSPI Command Register 0
SPCMD0
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 70 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (17/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
RSPI
Remarks
0008 83B2h RSPI1
RSPI Command Register 1
SPCMD1
16
16
2, 3 PCLKB
2 ICLK
0008 83B4h RSPI1
RSPI Command Register 2
SPCMD2
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 83B6h RSPI1
RSPI Command Register 3
SPCMD3
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 83B8h RSPI1
RSPI Command Register 4
SPCMD4
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 83BAh RSPI1
RSPI Command Register 5
SPCMD5
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 83BCh RSPI1
RSPI Command Register 6
SPCMD6
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 83BEh RSPI1
RSPI Command Register 7
SPCMD7
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9000h
S12AD
A/D Control Register
ADCSR
16
16
2, 3 PCLKB
2 ICLK
0008 9004h
S12AD
A/D Channel Select Register A
ADANSA
16
16
2, 3 PCLKB
2 ICLK
0008 9008h
S12AD
A/D-Converted Value Addition Mode Select
Register
ADADS
16
16
2, 3 PCLKB
2 ICLK
0008 900Ch S12AD
A/D-Converted Value Addition Count Select
Register
ADADC
8
8
2, 3 PCLKB
2 ICLK
0008 900Eh S12AD
A/D Control Extended Register
ADCER
16
16
2, 3 PCLKB
2 ICLK
0008 9010h
S12AD
A/D Start Trigger Select Register
ADSTRGR
16
16
2, 3 PCLKB
2 ICLK
0008 9014h
S12AD
A/D Channel Select Register B
ADANSB
16
16
2, 3 PCLKB
2 ICLK
0008 9018h
S12AD
Not present in versions
with 64 or 48 pins.
S12ADB
A/D Data-Doubling Register
ADDBLDR
16
16
2, 3 PCLKB
2 ICLK
0008 901Eh S12AD
A/D Self-Diagnosis Data Register
ADRD
16
16
2, 3 PCLKB
2 ICLK
0008 9020h
S12AD
A/D Data Register 0
ADDR0
16
16
2, 3 PCLKB
2 ICLK
0008 9022h
S12AD
A/D Data Register 1
ADDR1
16
16
2, 3 PCLKB
2 ICLK
0008 9024h
S12AD
A/D Data Register 2
ADDR2
16
16
2, 3 PCLKB
2 ICLK
0008 9026h
S12AD
A/D Data Register 3
ADDR3
16
16
2, 3 PCLKB
2 ICLK
0008 9028h
S12AD
A/D Data Register 4
ADDR4
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 144, 120, 112, or
100 pins.
0008 902Ah S12AD
A/D Data Register 5
ADDR5
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 144, 120, 112, or
100 pins.
0008 902Ch S12AD
A/D Data Register 6
ADDR6
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 144, 120, 112, or
100 pins.
0008 902Eh S12AD
A/D Data Register 7
ADDR7
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 144, 120, 112, or
100 pins.
ADSSTR0
2 ICLK
0008 9060h
S12AD
A/D Sampling State Register 0
8
8
2, 3 PCLKB
0008 9066h
S12AD
A/D Sample and Hold Circuit Control Register ADSHCR
16
16
2, 3 PCLKB
2 ICLK
0008 9073h
S12AD
A/D Sampling State Register 1
ADSSTR1
8
8
2, 3 PCLKB
2 ICLK
0008 9074h
S12AD
A/D Sampling State Register 2
ADSSTR2
8
8
2, 3 PCLKB
2 ICLK
0008 9075h
S12AD
A/D Sampling State Register 3
ADSSTR3
8
8
2, 3 PCLKB
2 ICLK
0008 9076h
S12AD
A/D Sampling State Register 4
ADSSTR4
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 144, 120, 112, or
100 pins.
0008 9077h
S12AD
A/D Sampling State Register 5
ADSSTR5
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 144, 120, 112, or
100 pins.
0008 9078h
S12AD
A/D Sampling State Register 6
ADSSTR6
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 144, 120, 112, or
100 pins.
0008 9079h
S12AD
A/D Sampling State Register 7
ADSSTR7
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 144, 120, 112, or
100 pins.
0008 9080h
S12AD
A/D Group Scan Priority Control Register
ADGSPCR
16
16
2, 3 PCLKB
2 ICLK
0008 9084h
S12AD
A/D Data-Doubling Register A
ADDBLDRA
16
16
2, 3 PCLKB
2 ICLK
0008 9086h
S12AD
A/D Data-Doubling Register B
ADDBLDRB
16
16
2, 3 PCLKB
2 ICLK
A/D Programmable Gain Amplifier Register
ADPG
16
16
2, 3 PCLKB
2 ICLK
0008 908Ah S12AD
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Not present in versions
with 64 or 48 pins.
Page 71 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (18/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
0008 90E0h S12AD
Comparator Operating Mode Selection
Register 0
ADCMPMD0 16
16
2, 3 PCLKB
2 ICLK
0008 90E2h S12AD
Comparator Operating-Mode Selection
Register 1
ADCMPMD1 16
16
2, 3 PCLKB
2 ICLK
Module
Name
Remarks
S12ADB
0008 90E4h S12AD
Comparator Filter-Mode Register
ADCMPNR0
16
16
2, 3 PCLKB
2 ICLK
0008 90E8h S12AD
Comparator Detection Flag Register
ADCMPFR
8
8
2, 3 PCLKB
2 ICLK
0008 90EAh S12AD
Comparator Interrupt Selection Register
ADCMPSEL
16
16
2, 3 PCLKB
2 ICLK
0008 90FCh S12AD
A/D Group Scan Priority Control Register
ADGSPMR
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9100h
S12AD1
A/D Control Register
ADCSR
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9104h
S12AD1
A/D Channel Select Register A
ADANSA
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9108h
S12AD1
A/D-Converted Value Addition Mode Select
Register (ADADS)
ADADS
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 910Ch S12AD1
A/D-Converted Value Addition Count Select
Register
ADADC
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 910Eh S12AD1
A/D Control Extended Register
ADCER
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9110h
S12AD1
A/D Start Trigger Select Register
ADSTRGR
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9114h
S12AD1
A/D Channel Select Register B
ADANSB
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9118h
S12AD1
A/D Data-Doubling Register
ADDBLDR
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 911Eh
S12AD1
A/D Self-Diagnosis Data Register
ADRD
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9120h
S12AD1
A/D Data Register 0
ADDR0
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9122h
S12AD1
A/D Data Register 1
ADDR1
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9124h
S12AD1
A/D Data Register 2
ADDR2
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9126h
S12AD1
A/D Data Register 3
ADDR3
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9160h
S12AD1
A/D Sampling State Register 0
ADSSTR0
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9166h
S12AD1
A/D Sample and Hold Circuit Control
Register
ADSHCR
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9173h
S12AD1
A/D Sampling State Register 1
ADSSTR1
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9174h
S12AD1
A/D Sampling State Register 2
ADSSTR2
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9175h
S12AD1
A/D Sampling State Register 3
ADSSTR3
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9180h
S12AD1
A/D Group Scan Priority Control Register
ADGSPCR
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9184h
S12AD1
A/D Data-Doubling Register A
ADDBLDRA
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9186h
S12AD1
A/D Data-Doubling Register B
ADDBLDRB
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 918Ah S12AD1
A/D Programmable Gain Amplifier Register
ADPG
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 91E0h S12AD1
Comparator Operating Mode Selection
Register 0
ADCMPMD0 16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 91E2h S12AD1
Comparator Operating-Mode Selection
Register 1
ADCMPMD1 16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 91E4h S12AD1
Comparator Filter-Mode Register
ADCMPNR0
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 91E8h S12AD1
Comparator Detection Flag Register
ADCMPFR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 91EAh S12AD1
Comparator Interrupt Selection Register
ADCMPSEL
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9800h
A/D Control Register
ADCSR
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
AD
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 72 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (19/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
AD
Remarks
0008 9804h
AD
A/D Channel Select Register 0
ADANSA0
16
16
2, 3 PCLKB
2 ICLK
0008 9806h
AD
A/D Channel Select Register 1
ADANSA1
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64
or 48 pins.
0008 9808h
AD
A/D-Converted Value Addition Mode Select
Register0
ADADS0
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 980Ah AD
A/D-Converted Value Addition Mode Select
Register1
ADADS1
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64
or 48 pins.
0008 980Ch AD
A/D-Converted Value Addition Count Select
Register
ADADC
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 980Eh AD
A/D Control Extended Register
ADCER
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9810h
A/D Start Trigger Select Register
ADSTRGR
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 981Eh AD
A/D Self-Diagnosis Data Register
ADRD
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9820h
AD
A/D Data Register A
ADDRA
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9822h
AD
A/D Data Register B
ADDRB
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9824h
AD
A/D Data Register C
ADDRC
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9826h
AD
A/D Data Register D
ADDRD
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9828h
AD
A/D Data Register E
ADDRE
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 982Ah AD
A/D Data Register F
ADDRF
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 982Ch AD
A/D Data Register G
ADDRG
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 982Eh AD
A/D Data Register H
ADDRH
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9830h
AD
A/D Data Register I
ADDRI
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9832h
AD
A/D Data Register J
ADDRJ
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9834h
AD
A/D Data Register K
ADDRK
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9836h
AD
A/D Data Register L
ADDRL
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9838h
AD
A/D Data Register M
ADDRM
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64,
or 48 pins.
0008 983Ah AD
A/D Data Register N
ADDRN
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64,
or 48 pins.
0008 983Ch AD
A/D Data Register O
ADDRO
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64,
or 48 pins.
0008 983Eh AD
A/D Data Register P
ADDRP
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64,
or 48 pins.
0008 9840h
AD
A/D Data Register Q
ADDRQ
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64,
or 48 pins.
0008 9842h
AD
A/D Data Register R
ADDRR
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64,
or 48 pins.
0008 9844h
AD
A/D Data Register S
ADDRS
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64,
or 48 pins.
0008 9846h
AD
A/D Data Register T
ADDRT
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64,
or 48 pins.
0008 9860h
AD
A/D Sampling State Register 0
ADSSTR0
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9861h
AD
A/D Sampling State Register L
ADSSTRL
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
AD
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Not present in versions
with 64 or 48 pins.
Page 73 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (20/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
AD
Remarks
0008 9873h
AD
A/D Sampling State Register 1
ADSSTR1
8
8
2, 3 PCLKB
2 ICLK
0008 9874h
AD
A/D Sampling State Register 2
ADSSTR2
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9875h
AD
A/D Sampling State Register 3
ADSSTR3
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9876h
AD
A/D Sampling State Register 4
ADSSTR4
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9877h
AD
A/D Sampling State Register 5
ADSSTR5
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9878h
AD
A/D Sampling State Register 6
ADSSTR6
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 9879h
AD
A/D Sampling State Register 7
ADSSTR7
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 987Dh AD
Digital Power Supply Control Circuit Output
Register
ADDPCONR 8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64, or 48 pins.
0008 A000h SCI0
Serial Mode Register
SMR
8
8
2, 3 PCLKB
2 ICLK
0008 A001h SCI0
Bit Rate Register
BRR
8
8
2, 3 PCLKB
2 ICLK
0008 A002h SCI0
Serial Control Register
SCR
8
8
2, 3 PCLKB
2 ICLK
0008 A003h SCI0
Transmit Data Register
TDR
8
8
2, 3 PCLKB
2 ICLK
0008 A004h SCI0
Serial Status Register
SSR
8
8
2, 3 PCLKB
2 ICLK
0008 A005h SCI0
Receive Data Register
RDR
8
8
2, 3 PCLKB
2 ICLK
0008 A006h SCI0
Smart Card Mode Register
SCMR
8
8
2, 3 PCLKB
2 ICLK
0008 A007h SCI0
Serial Extended Mode Register
SEMR
8
8
2, 3 PCLKB
2 ICLK
0008 A008h SCI0
Noise Filter Setting Register
SNFR
8
8
2, 3 PCLKB
2 ICLK
0008 A009h SCI0
I2C Mode Register 1
SIMR1
8
8
2, 3 PCLKB
2 ICLK
0008 A00Ah SCI0
I2C Mode Register 2
SIMR2
8
8
2, 3 PCLKB
2 ICLK
0008 A00Bh SCI0
I2C Mode Register 3
SIMR3
8
8
2, 3 PCLKB
2 ICLK
0008 A00Ch SCI0
I2C Status Register
SISR
8
8
2, 3 PCLKB
2 ICLK
0008 A00Dh SCI0
SPI Mode Register
SPMR
8
8
2, 3 PCLKB
2 ICLK
0008 A020h SCI1
Serial Mode Register
SMR
8
8
2, 3 PCLKB
2 ICLK
0008 A021h SCI1
Bit Rate Register
BRR
8
8
2, 3 PCLKB
2 ICLK
0008 A022h SCI1
Serial Control Register
SCR
8
8
2, 3 PCLKB
2 ICLK
0008 A023h SCI1
Transmit Data Register
TDR
8
8
2, 3 PCLKB
2 ICLK
0008 A024h SCI1
Serial Status Register
SSR
8
8
2, 3 PCLKB
2 ICLK
0008 A025h SCI1
Receive Data Register
RDR
8
8
2, 3 PCLKB
2 ICLK
0008 A026h SCI1
Smart Card Mode Register
SCMR
8
8
2, 3 PCLKB
2 ICLK
0008 A027h SCI1
Serial Extended Mode Register
SEMR
8
8
2, 3 PCLKB
2 ICLK
0008 A028h SCI1
Noise Filter Setting Register
SNFR
8
8
2, 3 PCLKB
2 ICLK
0008 A029h SCI1
I2C Mode Register 1
SIMR1
8
8
2, 3 PCLKB
2 ICLK
0008 A02Ah SCI1
I2C Mode Register 2
SIMR2
8
8
2, 3 PCLKB
2 ICLK
0008 A02Bh SCI1
I2C Mode Register 3
SIMR3
8
8
2, 3 PCLKB
2 ICLK
0008 A02Ch SCI1
I2C Status Register
SISR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
SCIc, SCId
0008 A02Dh SCI1
SPI Mode Register
SPMR
8
8
2, 3 PCLKB
2 ICLK
0008 A040h SCI2
Serial Mode Register
SMR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 A041h SCI2
Bit Rate Register
BRR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 A042h SCI2
Serial Control Register
SCR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 A043h SCI2
Transmit Data Register
TDR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 A044h SCI2
Serial Status Register
SSR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 A045h SCI2
Receive Data Register
RDR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 A046h SCI2
Smart Card Mode Register
SCMR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 74 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (21/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
Serial Extended Mode Register
SEMR
8
8
2, 3 PCLKB
2 ICLK
0008 A048h SCI2
Noise Filter Setting Register
SNFR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 A049h SCI2
I2C Mode Register 1
SIMR1
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 A04Ah SCI2
I2C Mode Register 2
SIMR2
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 A04Bh SCI2
I2C Mode Register 3
SIMR3
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 A04Ch SCI2
I2C Status Register
SISR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 A04Dh SCI2
SPI Mode Register
SPMR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 A060h SCI3
Serial Mode Register
SMR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 A061h SCI3
Bit Rate Register
BRR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 A062h SCI3
Serial Control Register
SCR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 A063h SCI3
Transmit Data Register
TDR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 A064h SCI3
Serial Status Register
SSR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 A065h SCI3
Receive Data Register
RDR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 A066h SCI3
Smart Card Mode Register
SCMR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 A067h SCI3
Serial Extended Mode Register
SEMR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 A068h SCI3
Noise Filter Setting Register
SNFR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 A069h SCI3
I2C Mode Register 1
SIMR1
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 A06Ah SCI3
I2C Mode Register 2
SIMR2
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 A06Bh SCI3
I2C Mode Register 3
SIMR3
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 A06Ch SCI3
I2C Status Register
SISR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 A06Dh SCI3
SPI Mode Register
SPMR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 B000h CAC
CAC Control Register 0
CACR0
8
8
2, 3 PCLKB
2 ICLK
0008 B001h CAC
CAC Control Register 1
CACR1
8
8
2, 3 PCLKB
2 ICLK
0008 B002h CAC
CAC Control Register 2)
CACR2
8
8
2, 3 PCLKB
2 ICLK
0008 B003h CAC
CAC Interrupt Control Register
CAICR
8
8
2, 3 PCLKB
2 ICLK
0008 B004h CAC
CAC Status Register
CASTR
8
8
2, 3 PCLKB
2 ICLK
0008 B006h CAC
CAC Upper-Limit Value Setting Register
CAULVR
16
16
2, 3 PCLKB
2 ICLK
0008 B008h CAC
CAC Lower-Limit Value Setting Register
CALLVR
16
16
2, 3 PCLKB
2 ICLK
0008 B00Ah CAC
CAC Counter Buffer Register
CACNTBR
16
16
2, 3 PCLKB
2 ICLK
0008 B080h DOC
DOC Control Register
DOCR
8
8
2, 3 PCLKB
2 ICLK
0008 B082h DOC
DOC Data Input Register
DODIR
16
16
2, 3 PCLKB
2 ICLK
0008 B084h DOC
DOC Data Setting Register
DODSR
16
16
2, 3 PCLKB
2 ICLK
0008 B300h SCI12
Serial Mode Register
SMR
8
8
2, 3 PCLKB
2 ICLK
0008 B301h SCI12
Bit Rate Register
BRR
8
8
2, 3 PCLKB
2 ICLK
2 ICLK
0008 B302h SCI12
Serial Control Register
SCR
8
8
2, 3 PCLKB
0008 B303h SCI12
Transmit Data Register
TDR
8
8
2, 3 PCLKB
2 ICLK
0008 B304h SCI12
Serial Status Register
SSR
8
8
2, 3 PCLKB
2 ICLK
0008 B305h SCI12
Receive Data Register
RDR
8
8
2, 3 PCLKB
2 ICLK
0008 B306h SCI12
Smart Card Mode Register
SCMR
8
8
2, 3 PCLKB
2 ICLK
0008 B307h SCI12
Serial Extended Mode Register
SEMR
8
8
2, 3 PCLKB
2 ICLK
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
SCIc, SCId
Remarks
0008 A047h SCI2
Not present in versions
with 64 or 48 pins.
CAC
DOC
SCIc, SCId
Page 75 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (22/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
SCIc, SCId
0008 B308h SCI12
Noise Filter Setting Register
SNFR
8
8
2, 3 PCLKB
2 ICLK
0008 B309h SCI12
I2C Mode Register 1
SIMR1
8
8
2, 3 PCLKB
2 ICLK
0008 B30Ah SCI12
I2C
Mode Register 2
SIMR2
8
8
2, 3 PCLKB
2 ICLK
0008 B30Bh SCI12
I2C Mode Register 3
SIMR3
8
8
2, 3 PCLKB
2 ICLK
0008 B30Ch SCI12
I2C Status Register
SISR
8
8
2, 3 PCLKB
2 ICLK
Remarks
0008 B30Dh SCI12
SPI Mode Register
SPMR
8
8
2, 3 PCLKB
2 ICLK
0008 B320h SCI12
Extended Serial Module Enable Register
ESMER
8
8
2, 3 PCLKB
2 ICLK
0008 B321h SCI12
Control Register 0
CR0
8
8
2, 3 PCLKB
2 ICLK
0008 B322h SCI12
Control Register 1
CR1
8
8
2, 3 PCLKB
2 ICLK
0008 B323h SCI12
Control Register 2
CR2
8
8
2, 3 PCLKB
2 ICLK
0008 B324h SCI12
Control Register 3
CR3
8
8
2, 3 PCLKB
2 ICLK
0008 B325h SCI12
Port Control Register
PCR
8
8
2, 3 PCLKB
2 ICLK
0008 B326h SCI12
Interrupt Control Register
ICR
8
8
2, 3 PCLKB
2 ICLK
0008 B327h SCI12
Status Register
STR
8
8
2, 3 PCLKB
2 ICLK
0008 B328h SCI12
Status Clear Register
STCR
8
8
2, 3 PCLKB
2 ICLK
0008 B329h SCI12
Control Field 0 Data Register
CF0DR
8
8
2, 3 PCLKB
2 ICLK
0008 B32Ah SCI12
Control Field 0 Compare Enable Register
CF0CR
8
8
2, 3 PCLKB
2 ICLK
0008 B32Bh SCI12
Control Field 0 Receive Data Register
CF0RR
8
8
2, 3 PCLKB
2 ICLK
0008 B32Ch SCI12
Primary Control Field 1 Data Register
PCF1DR
8
8
2, 3 PCLKB
2 ICLK
0008 B32Dh SCI12
Primary Control Field 1 Data Register
SCF1DR
8
8
2, 3 PCLKB
2 ICLK
0008 B32Eh SCI12
Secondary Control Field 1 Data Register
CF1CR
8
8
2, 3 PCLKB
2 ICLK
0008 B32Fh SCI12
Control Field 1 Receive Data Register
CF1RR
8
8
2, 3 PCLKB
2 ICLK
0008 B330h SCI12
Timer Control Register
TCR
8
8
2, 3 PCLKB
2 ICLK
0008 B331h SCI12
Timer Mode Register
TMR
8
8
2, 3 PCLKB
2 ICLK
0008 B332h SCI12
Timer Prescaler Register
TPRE
8
8
2, 3 PCLKB
2 ICLK
0008 B333h SCI12
Timer Count Register
TCNT
8
8
2, 3 PCLKB
2 ICLK
0008 C000h PORT0
Port Direction Register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C001h PORT1
Port Direction Register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C002h PORT2
Port Direction Register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C003h PORT3
Port Direction Register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C007h PORT7
Port Direction Register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C008h PORT8
Port Direction Register
PDR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C009h PORT9
Port Direction Register
PDR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C00Ah PORTA
Port Direction Register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C00Bh PORTB
Port Direction Register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C00Dh PORTD
Port Direction Register
PDR
8
8
2, 3 PCLKB
2 ICLK
0008 C00Eh PORTE
Port Direction Register
PDR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C00Fh PORTF
Port Direction Register
PDR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 C010h PORTG
Port Direction Register
PDR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 C020h PORT0
Port Output Data Register
PODR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C021h PORT1
Port Output Data Register
PODR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C022h PORT2
Port Output Data Register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C023h PORT3
Port Output Data Register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C027h PORT7
Port Output Data Register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C028h PORT8
Port Output Data Register
PODR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C029h PORT9
Port Output Data Register
PODR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
I/O Ports
Not present in versions
with 48 pins.
Not present in versions
with 48 pins.
Page 76 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (23/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
I/O Ports
Remarks
0008 C02Ah PORTA
Port Output Data Register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C02Bh PORTB
Port Output Data Register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C02Dh PORTD
Port Output Data Register
PODR
8
8
2, 3 PCLKB
2 ICLK
0008 C02Eh PORTE
Port Output Data Register
PODR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C02Fh PORTF
Port Output Data Register
PODR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 C030h PORTG
Port Output Data Register
PODR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 C040h PORT0
Port Input Data Register
PIDR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C041h PORT1
Port Input Data Register
PIDR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C042h PORT2
Port Input Data Register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C043h PORT3
Port Input Data Register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C044h PORT4
Port Input Data Register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C045h PORT5
Port Input Data Register
PIDR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C046h PORT6
Port Input Data Register
PIDR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C047h PORT7
Port Input Data Register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C048h PORT8
Port Input Data Register
PIDR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C049h PORT9
Port Input Data Register
PIDR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C04Ah PORTA
Port Input Data Register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C04Bh PORTB
Port Input Data Register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C04Ch PORTC
Port Input Data Register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C04Dh PORTD
Port Input Data Register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C04Eh PORTE
Port Input Data Register
PIDR
8
8
2, 3 PCLKB
2 ICLK
0008 C04Fh PORTF
Port Input Data Register
PIDR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 C050h PORTG
Port Input Data Register
PIDR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 C060h PORT0
Port Mode Register
PMR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C061h PORT1
Port Mode Register
PMR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C062h PORT2
Port Mode Register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C063h PORT3
Port Mode Register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C067h PORT7
Port Mode Register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C068h PORT8
Port Mode Register
PMR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C069h PORT9
Port Mode Register
PMR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C06Ah PORTA
Port Mode Register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C06Bh PORTB
Port Mode Register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C06Dh PORTD
Port Mode Register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C06Eh PORTE
Port Mode Register
PMR
8
8
2, 3 PCLKB
2 ICLK
0008 C06Fh PORTF
Port Mode Register
PMR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 C070h PORTG
Port Mode Register
PMR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 C080h PORT0
Open Drain Control Register 0
ODR0
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64
or 48 pins.
0008 C084h PORT2
Open Drain Control Register 0
ODR0
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C085h PORT2
Open Drain Control Register 1
ODR1
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112 or 100 pins.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Not present in versions
with 120, 112, 100, 64,
or 48 pins.
Page 77 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (24/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
I/O Ports
Remarks
0008 C086h PORT3
Open Drain Control Register 0
ODR0
8
8
2, 3 PCLKB
2 ICLK
0008 C087h PORT3
Open Drain Control Register 1
ODR1
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64
or 48 pins.
0008 C090h PORT8
Open Drain Control Register 0
ODR0
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C092h PORT9
Open Drain Control Register 0
ODR0
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 144, 120, 112, 100
or 48 pins.
0008 C093h PORT9
Open Drain Control Register 1
ODR1
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C094h PORTA
Open Drain Control Register 0
ODR0
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C095h PORTA
Open Drain Control Register 1
ODR1
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C096h PORTB
Open Drain Control Register 0
ODR0
8
8
2, 3 PCLKB
2 ICLK
0008 C097h PORTB
Open Drain Control Register 1
ODR1
8
8
2, 3 PCLKB
2 ICLK
0008 C09Ah PORTD
Open Drain Control Register 0
ODR0
8
8
2, 3 PCLKB
2 ICLK
0008 C09Bh PORTD
Open Drain Control Register 1
ODR1
8
8
2, 3 PCLKB
2 ICLK
0008 C09Eh PORTF
Open Drain Control Register 0
ODR0
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 C0A0h PORTG
Open Drain Control Register 0
ODR0
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 C0A1h PORTG
Open Drain Control Register 1
ODR1
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 C0F2h PORT
Driving Ability Control Register 1
DSCR1
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C0F3h PORT
Driving Ability Control Register 2
DSCR2
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C100h MPC
CS Output Enable Register
PFCSE
8
8
2, 3 PCLKB
2 ICLK
0008 C102h MPC
CS Output Pin Select Register 0
PFCSS0
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C104h MPC
Address Output Enable Register 0
PFAOE0
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C105h MPC
Address Output Enable Register 1
PFAOE1
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C106h MPC
External Bus Control Register 0
PFBCR0
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C107h MPC
External Bus Control Register 1
PFBCR1
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C114h
MPC
USB0 Control Register
PFUSB0
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 C11Fh MPC
Write-Protect Register
PWPR
8
8
2, 3 PCLKB
2 ICLK
0008 C140h MPC
P00 Pin Function Control Register
P00PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C141h MPC
P01 Pin Function Control Register
P01PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C142h MPC
P02 Pin Function Control Register
P02PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64,
or 48 pins.
0008 C143h MPC
P03 Pin Function Control Register
P03PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64,
or 48 pins.
0008 C148h MPC
P10 Pin Function Control Register
P10PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C149h MPC
P11 Pin Function Control Register
P11PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C14Ah MPC
P12 Pin Function Control Register
P12PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 C14Bh MPC
P13 Pin Function Control Register
P13PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
MPC
Not present in versions
with 144, 120, 112, or
100 pins.
Not present in versions
with 64 or 48 pins.
Page 78 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (25/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
MPC
Remarks
0008 C14Ch MPC
P14 Pin Function Control Register
P14PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C150h MPC
P20 Pin Function Control Register
P20PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C151h MPC
P21 Pin Function Control Register
P21PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C152h MPC
P22 Pin Function Control Register
P22PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C153h MPC
P23 Pin Function Control Register
P23PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C154h MPC
P24 Pin Function Control Register
P24PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C155h MPC
P25 Pin Function Control Register
P25PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 C156h MPC
P26 Pin Function Control Register
P26PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 C158h MPC
P30 Pin Function Control Register
P30PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C159h MPC
P31 Pin Function Control Register
P31PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C15Ah MPC
P32 Pin Function Control Register
P32PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C15Bh MPC
P33 Pin Function Control Register
P33PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C15Ch MPC
P34 Pin Function Control Register
P34PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64,
or 48 pins.
0008 C15Dh MPC
P35 Pin Function Control Register
P35PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64,
or 48 pins.
0008 C160h MPC
P40 Pin Function Control Register
P40PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C161h MPC
P41 Pin Function Control Register
P41PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C162h MPC
P42 Pin Function Control Register
P42PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C163h MPC
P43 Pin Function Control Register
P43PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C164h MPC
P44 Pin Function Control Register
P44PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C165h MPC
P45 Pin Function Control Register
P45PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C166h MPC
P46 Pin Function Control Register
P46PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C167h MPC
P47 Pin Function Control Register
P47PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C168h MPC
P50 Pin Function Control Register
P50PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C169h MPC
P51 Pin Function Control Register
P51PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C16Ah MPC
P52 Pin Function Control Register
P52PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C16Bh MPC
P53 Pin Function Control Register
P53PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C16Ch MPC
P54 Pin Function Control Register
P54PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C16Dh MPC
P55 Pin Function Control Register
P55PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C16Eh MPC
P56 Pin Function Control Register
P56PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64,
or 48 pins.
0008 C16Fh MPC
P57 Pin Function Control Register
P57PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64,
or 48 pins.
0008 C170h MPC
P60 Pin Function Control Register
P60PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C171h MPC
P61 Pin Function Control Register
P61PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C172h MPC
P62 Pin Function Control Register
P62PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C173h MPC
P63 Pin Function Control Register
P63PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Not present in versions
with 120, 112, 100, 64,
or 48 pins.
Page 79 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (26/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
MPC
Remarks
0008 C174h MPC
P64 Pin Function Control Register
P64PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C175h MPC
P65 Pin Function Control Register
P65PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C178h MPC
P70 Pin Function Control Register
P70PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C179h MPC
P71 Pin Function Control Register
P71PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C17Ah MPC
P72 Pin Function Control Register
P72PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C17Bh MPC
P73 Pin Function Control Register
P73PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C17Ch MPC
P74 Pin Function Control Register
P74PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C17Dh MPC
P75 Pin Function Control Register
P75PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C17Eh MPC
P76 Pin Function Control Register
P76PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C180h MPC
P80 Pin Function Control Register
P80PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C181h MPC
P81 Pin Function Control Register
P81PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C182h MPC
P82 Pin Function Control Register
P82PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C188h MPC
P90 Pin Function Control Register
P90PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C189h MPC
P91 Pin Function Control Register
P91PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C18Ah MPC
P92 Pin Function Control Register
P92PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C18Bh MPC
P93 Pin Function Control Register
P93PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C18Ch MPC
P94 Pin Function Control Register
P94PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C18Dh MPC
P95 Pin Function Control Register
P95PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C18Eh MPC
P96 Pin Function Control Register
P96PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C190h MPC
PA0 Pin Function Control Register
PA0PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C191h MPC
PA1 Pin Function Control Register
PA1PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C192h MPC
PA2 Pin Function Control Register
PA2PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C193h MPC
PA3 Pin Function Control Register
PA3PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C194h MPC
PA4 Pin Function Control Register
PA4PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C195h MPC
PA5 Pin Function Control Register
PA5PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C196h MPC
PA6 Pin Function Control Register
PA6PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64
or 48 pins.
0008 C198h MPC
PB0 Pin Function Control Register
PB0PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C199h MPC
PB1 Pin Function Control Register
PB1PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C19Ah MPC
PB2 Pin Function Control Register
PB2PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C19Bh MPC
PB3 Pin Function Control Register
PB3PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C19Ch MPC
PB4 Pin Function Control Register
PB4PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C19Dh MPC
PB5 Pin Function Control Register
PB5PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C19Eh MPC
PB6 Pin Function Control Register
PB6PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C19Fh MPC
PB7 Pin Function Control Register
PB7PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 48 pins.
0008 C1A0h MPC
PC0 Pin Function Control Register
PC0PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64,
or 48 pins.
0008 C1A1h MPC
PC1 Pin Function Control Register
PC1PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64,
or 48 pins.
0008 C1A2h MPC
PC2 Pin Function Control Register
PC2PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64,
or 48 pins.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 80 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (27/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
MPC
Remarks
0008 C1A3h MPC
PC3 Pin Function Control Register
PC3PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1A4h MPC
PC4 Pin Function Control Register
PC4PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64,
or 48 pins.
0008 C1A5h MPC
PC5 Pin Function Control Register
PC5PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 120, 112, 100, 64,
or 48 pins.
0008 C1A8h MPC
PD0 Pin Function Control Register
PD0PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C1A9h MPC
PD1 Pin Function Control Register
PD1PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C1AAh MPC
PD2 Pin Function Control Register
PD2PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C1ABh MPC
PD3 Pin Function Control Register
PD3PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1ACh MPC
PD4 Pin Function Control Register
PD4PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1ADh MPC
PD5 Pin Function Control Register
PD5PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1AEh MPC
PD6 Pin Function Control Register
PD6PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1AFh MPC
PD7 Pin Function Control Register
PD7PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1B0h MPC
PE0 Pin Function Control Register
PE0PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C1B1h MPC
PE1 Pin Function Control Register
PE1PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C1B2h MPC
PE2 Pin Function Control Register
PE2PFS
8
8
2, 3 PCLKB
2 ICLK
0008 C1B3h MPC
PE3 Pin Function Control Register
PE3PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C1B4h MPC
PE4 Pin Function Control Register
PE4PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C1B5h MPC
PE5 Pin Function Control Register
PE5PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C1BAh MPC
PF2 Pin Function Control Register
PF2PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 C1BBh MPC
PF3 Pin Function Control Register
PF3PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 C1C0h MPC
PG0 Pin Function Control Register
PG0PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 C1C1h MPC
PG1 Pin Function Control Register
PG1PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 C1C2h MPC
PG2 Pin Function Control Register
PG2PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 C1C3h MPC
PG3 Pin Function Control Register
PG3PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 C1C4h MPC
PG4 Pin Function Control Register
PG4PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 C1C5h MPC
PG5 Pin Function Control Register
PG5PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 100, 64, or 48 pins.
0008 C1C6h MPC
PG6 Pin Function Control Register
PG6PFS
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 C1D0h MPC
USB0_DPUPE Pin Function Control Register
UDPUPEPFS 8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
0008 C280h SYSTEM
Deep Standby Control Register
DPSBYCR
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C282h SYSTEM
Deep Standby Interrupt Enable Register 0
DPSIER0
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C284h SYSTEM
Deep Standby Interrupt Enable Register 2
DPSIER2
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C286h SYSTEM
Deep Standby Interrupt Flag Register 0
DPSIFR0
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C288h SYSTEM
Deep Standby Interrupt Flag Register 2
DPSIFR2
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C28Ah SYSTEM
Deep Standby Interrupt Edge Register 0
DPSIEGR0
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C28Ch SYSTEM
Deep Standby Interrupt Edge Register 2
DPSIEGR2
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C290h SYSTEM
Reset Status Register 0
RSTSR0
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C291h SYSTEM
Reset Status Register 1
RSTSR1
8
8
4, 5 PCLKB
2, 3 ICLK
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Not present in versions
with 120, 112, 100, 64,
or 48 pins.
Low Power
Consumption
Resets
Page 81 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (28/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
Remarks
0008 C293h SYSTEM
Main Clock Oscillator Forced Oscillation
Control Register
MOFCR
8
8
4, 5 PCLKB
2, 3 ICLK
Clock
Generation
Circuit
0008 C296h FLASH
Flash P/E Protection Register
FWEPROR
8
8
4, 5 PCLKB
2, 3 ICLK
ROM
0008 C297h SYSTEM
Voltage Monitoring Circuit Control Register
LVCMPCR
8
8
4, 5 PCLKB
2, 3 ICLK
LVDA
0008 C298h SYSTEM
Voltage Detection Level Select Register
LVDLVLR
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C29Ah SYSTEM
Voltage Monitoring 1 Circuit Control Register 0
LVD1CR0
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C29Bh SYSTEM
Voltage Monitoring 2 Circuit Control Register 0
LVD2CR0
8
8
4, 5 PCLKB
2, 3 ICLK
0008 C2A0h SYSTEM
to
0008 C2BFh
Deep Standby Backup Register 0 to 31
DPSBKR0 to 8
31
8
4, 5 PCLKB
2, 3 ICLK
Low Power
Consumption
0008 C300h ICU
Group 0 Interrupt Source Register
GRP00
32
32
1, 2 PCLKB
2 ICLK
ICUb
0008 C330h ICU
Group 12 Interrupt Source Register
GRP12
32
32
1, 2 PCLKB
2 ICLK
0008 C340h ICU
Group 0 Interrupt Enable Register
GEN00
32
32
1, 2 PCLKB
2 ICLK
0008 C370h ICU
Group 12 Interrupt Enable Register
GEN12
32
32
1, 2 PCLKB
2 ICLK
0008 C380h ICU
Group 0 Interrupt Clear Register
GCR00
32
32
1, 2 PCLKB
2 ICLK
0008 C4C0h POE
Input Level Control/Status Register 1
ICSR1
16
8, 16
2, 3 PCLKB
2 ICLK
0008 C4C2h POE
Output Level Control/Status Register 1
OCSR1
16
8, 16
2, 3 PCLKB
2 ICLK
0008 C4C4h POE
Input Level Control/Status Register 2
ICSR2
16
8, 16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C4C6h POE
Output Level Control/Status Register 2
OCSR2
16
8, 16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C4C8h POE
Input Level Control/Status Register 3
ICSR3
16
8, 16
2, 3 PCLKB
2 ICLK
0008 C4CAh POE
Software Port Output Enable Register
SPOER
8
8
2, 3 PCLKB
2 ICLK
0008 C4CBh POE
Port Output Enable Control Register 1
POECR1
8
8
2, 3 PCLKB
2 ICLK
0008 C4CCh POE
Port Output Enable Control Register 2
POECR2
16
16
2, 3 PCLKB
2 ICLK
0008 C4CEh POE
Port Output Enable Control Register 3
POECR3
16
16
2, 3 PCLKB
2 ICLK
0008 C4D0h POE
Port Output Enable Control Register 4
POECR4
16
16
2, 3 PCLKB
2 ICLK
0008 C4D2h POE
Port Output Enable Control Register 5
POECR5
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
Not present in versions
with 64 or 48 pins.
Not present in versions
with 64 or 48 pins.
POE3
0008 C4D4h POE
Port Output Enable Control Register 6
POECR6
16
16
2, 3 PCLKB
2 ICLK
0008 C4D6h POE
Input Level Control/Status Register 4
ICSR4
16
8, 16
2, 3 PCLKB
2 ICLK
0008 C4D8h POE
Input Level Control/Status Register 5
ICSR5
16
8, 16
2, 3 PCLKB
2 ICLK
0008 C4DAh POE
Active Level Setting Register 1
ALR1
16
8, 16
2, 3 PCLKB
2 ICLK
0008 C4DCh POE
Input Level Control/Status Register 6
ICSR6
16
16
2, 3 PCLKB
2 ICLK
0008 C4DEh POE
Active Level Setting Register 2
ALR2
16
8, 16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C4E0h POE
Input Level Control/Status Register 7
ICSR7
16
8, 16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C4E2h POE
Port Output Enable Control Register 7
POECR7
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0008 C4E4h POE
Port Output Enable Control Register 8
POECR8
16
16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0009 1200h CAN1
to
0009 13FFh
Mailbox Register 0 to 31
MB0 to 31
128
8, 16, 32 2, 3 PCLKB
2 ICLK
0009 1400h CAN1
to
0009 141Ch
Mask Register 0 to 7
MKR0 to 7
32
8, 16, 32 2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0009 1420h
CAN1
FIFO Received ID Compare Register 0 and 1 FIDCR0
32
8, 16, 32 2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0009 1424h
CAN1
FIFO Received ID Compare Register 0 and 1 FIDCR1
32
8, 16, 32 2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0009 1428h
CAN1
Mask Invalid Register
MKIVLR
32
8, 16, 32 2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0009 142Ch CAN1
Mailbox Interrupt Enable Register
MIER
32
8, 16, 32 2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0009 1820h
to
0009 183Fh
Message Control Register 0 to 31
MCTL0 to 31 8
8
2 ICLK
Not present in versions
with 64 or 48 pins.
CAN1
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
2, 3 PCLKB
CAN
Not present in versions
with 64 or 48 pins.
Page 82 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (29/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
CAN
Remarks
0009 1840h
CAN1
Control Register
CTLR
16
8, 16
2, 3 PCLKB
2 ICLK
0009 1842h
CAN1
Status Register
STR
16
8, 16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0009 1844h
CAN1
Bit Configuration Register
BCR
32
8, 16, 32 2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0009 1848h
CAN1
Receive FIFO Control Register
RFCR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0009 1849h
CAN1
Receive FIFO Pointer Control Register
RFPCR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0009 184Ah CAN1
Transmit FIFO Control Register
TFCR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0009 184Bh CAN1
Transmit FIFO Pointer Control Register
TFPCR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0009 184Ch CAN1
Error Interrupt Enable Register
EIER
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0009 184Dh CAN1
Error Interrupt Factor Judge Register
EIFR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0009 184Eh CAN1
Receive Error Count Register
RECR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0009 184Fh
CAN1
Transmit Error Count Register
TECR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0009 1850h
CAN1
Error Code Store Register
ECSR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0009 1851h
CAN1
Channel Search Support Register
CSSR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0009 1852h
CAN1
Mailbox Search Status Register
MSSR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0009 1853h
CAN1
Mailbox Search Mode Register
MSMR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0009 1854h
CAN1
Time Stamp Register
TSR
16
8, 16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0009 1856h
CAN1
Acceptance Filter Support Register
AFSR
16
8, 16
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
0009 1858h
CAN1
Test Control Register
TCR
8
8
2, 3 PCLKB
2 ICLK
Not present in versions
with 64 or 48 pins.
000A 0000h USB0
System Configuration Control Register
SYSCFG
16
16
3, 4 PCLKB
2, 3 ICLK
000A 0004h USB0
System Configuration Status Register 0
SYSSTS0
16
16
9 PCLKB or
more
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0008h USB0
Device State Control Register 0
DVSTCTR0
16
16
9 PCLKB or
more
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0014h USB0
CFIFO Port Register
CFIFO
16
8, 16
3, 4 PCLKB
2, 3 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0018h USB0
D0FIFO Port Registe
D0FIFO
16
8, 16
3, 4 PCLKB
2, 3 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
000A 001Ch USB0
D1FIFO Port Register
D1FIFO
16
8, 16
3, 4 PCLKB
2, 3 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0020h USB0
CFIFO Port Select Register
CFIFOSEL
16
16
3, 4 PCLKB
2, 3 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0022h USB0
CFIFO Port Control Register
CFIFOCTR
16
16
3, 4 PCLKB
2, 3 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0028h USB0
D0FIFO Port Select Register
D0FIFOSEL
16
16
3, 4 PCLKB
2, 3 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
000A 002Ah USB0
D0FIFO Port Control Register
D0FIFOCTR 16
16
3, 4 PCLKB
2, 3 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
000A 002Ch USB0
D1FIFO Port Select Register
D1FIFOSEL
16
3, 4 PCLKB
2, 3 ICLK
Not present in versions
with 112, 100, 64, or 48
pins.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
16
USBa
Not present in versions
with 64 or 48 pins.
Not present in versions
with 112, 100, 64, or 48
pins.
Page 83 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (30/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
USBa
Remarks
000A 002Eh USB0
D1FIFO Port Control Register
D1FIFOCTR 16
16
3, 4 PCLKB
2, 3 ICLK
000A 0030h USB0
Interrupt Enable Register 0
INTENB0
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0032h USB0
Interrupt Enable Register 1
INTENB1
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0036h USB0
BRDY Interrupt Enable Register
BRDYENB
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0038h USB0
NRDY Interrupt Enable Register
NRDYENB
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 003Ah USB0
BEMP Interrupt Enable Register
BEMPENB
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 003Ch USB0
SOF Output Configuration Register
SOFCFG
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0040h USB0
Interrupt Status Register 0
INTSTS0
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0042h USB0
Interrupt Status Register 1
INTSTS1
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0046h USB0
BRDY Interrupt Status Register
BRDYSTS
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0048h USB0
NRDY Interrupt Status Register
NRDYSTS
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 004Ah USB0
BEMP Interrupt Status Register
BEMPSTS
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Not present in versions
with 112, 100, 64, or 48
pins.
Page 84 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (31/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
Remarks
000A 004Ch USB0
Frame Number Register
FRMNUM
16
16
9 PCLKB or
more
Rounded up to USBa
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 004Eh USB0
Device State Change Register
DVCHGR
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0050h USB0
USB Address Register
USBADDR
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0054h USB0
USB Request Type Register
USBREQ
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0056h USB0
USB Request Value Register
USBVAL
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0058h USB0
USB Request Index Register
USBINDX
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 005Ah USB0
USB Request Length Register
USBLENG
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 005Ch USB0
DCP Configuration Register
DCPCFG
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 005Eh USB0
DCP Maximum Packet Size Register
DCPMAXP
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0060h USB0
DCP Control Register
DCPCTR
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0064h USB0
Pipe Window Select Register
PIPESEL
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0068h USB0
Pipe Configuration Register
PIPECFG
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 85 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (32/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
Remarks
000A 006Ch USB0
Pipe Maximum Packet Size Register
PIPEMAXP
16
16
9 PCLKB or
more
Rounded up to USBa
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 006Eh USB0
Pipe Cycle Control Register
PIPEPERI
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0070h USB0
PIPE1 Control Register
PIPE1CTR
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0072h USB0
PIPE2 Control Register
PIPE2CTR
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0074h USB0
PIPE3 Control Register
PIPE3CTR
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0076h USB0
PIPE4 Control Register
PIPE4CTR
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0078h USB0
PIPE5 Control Register
PIPE5CTR
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 007Ah USB0
PIPE6 Control Register
PIPE6CTR
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 007Ch USB0
PIPE7 Control Register
PIPE7CTR
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 007Eh USB0
PIPE8 Control Register
PIPE8CTR
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0080h USB0
PIPE9 Control Register
PIPE9CTR
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0090h USB0
PIPE1 Transaction Counter Enable Register
PIPE1TRE
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 86 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (33/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
Remarks
000A 0092h USB0
PIPE1 Transaction Counter Register
PIPE1TRN
16
16
9 PCLKB or
more
Rounded up to USBa
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0094h USB0
PIPE2 Transaction Counter Enable Register
PIPE2TRE
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0096h USB0
PIPE2 Transaction Counter Register
PIPE2TRN
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 0098h USB0
PIPE3 Transaction Counter Enable Register
PIPE3TRE
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 009Ah USB0
PIPE3 Transaction Counter Register
PIPE3TRN
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 009Ch USB0
PIPE4 Transaction Counter Enable Register
PIPE4TRE
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 009Eh USB0
PIPE4 Transaction Counter Register
PIPE4TRN
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 00A0h USB0
PIPE5 Transaction Counter Enable Register
PIPE5TRE
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000A 00A2h USB0
PIPE5 Transaction Counter Register
PIPE5TRN
16
16
9 PCLKB or
more
Rounded up to
the nearest
integer greater
than 1 + 9/
(frequency ratio
of ICLK/
PCLKB)*1
Not present in versions
with 112, 100, 64, or 48
pins.
000C 1200h MTU3
Timer Control Register
TCR
8
8, 16, 32 4, 5 PCLKA
2, 3 ICLK
000C 1201h MTU4
Timer Control Register
TCR
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1202h MTU3
Timer Mode Register 1
TMDR1
8
8, 16
4, 5 PCLKA
2, 3 ICLK
000C 1203h MTU4
Timer Mode Register 1
TMDR1
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1204h MTU3
Timer I/O Control Register H
TIORH
8
8, 16, 32 4, 5 PCLKA
2, 3 ICLK
000C 1205h MTU3
Timer I/O Control Register L
TIORL
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1206h MTU4
Timer I/O Control Register H
TIORH
8
8, 16
4, 5 PCLKA
2, 3 ICLK
000C 1207h MTU4
Timer I/O Control Register L
TIORL
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1208h MTU3
Timer Interrupt Enable Register
TIER
8
8, 16
4, 5 PCLKA
2, 3 ICLK
000C 1209h MTU4
Timer Interrupt Enable Register
TIER
8
8
4, 5 PCLKA
2, 3 ICLK
000C 120Ah MTU
Timer Output Master Enable Register A
TOERA
8
8
4, 5 PCLKA
2, 3 ICLK
000C 120Dh MTU
Timer Gate Control Register A
TGCRA
8
8
4, 5 PCLKA
2, 3 ICLK
000C 120Eh MTU
Timer Output Control Register 1A
TOCR1A
8
8, 16
4, 5 PCLKA
2, 3 ICLK
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
MTU3
Page 87 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (34/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
MTU3
000C 120Fh MTU
Timer Output Control Register 2A
TOCR2A
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1210h MTU3
Timer Counter
TCNT
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 1212h MTU4
Timer Counter
TCNT
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1214h MTU
Timer Cycle Data Register A
TCDRA
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 1216h MTU
Timer Dead Time Data Register A
TDDRA
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1218h MTU3
Timer General Register A
TGRA
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 121Ah MTU3
Timer General Register B
TGRB
16
16
4, 5 PCLKA
2, 3 ICLK
000C 121Ch MTU4
Timer General Register A
TGRA
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 121Eh MTU4
Timer General Register B
TGRB
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1220h MTU
Timer Subcounter A
TCNTSA
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 1222h MTU
Timer Cycle Buffer Register A
TCBRA
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1224h MTU3
Timer General Register C
TGRC
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 1226h MTU3
Timer General Register D
TGRD
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1228h MTU4
Timer General Register C
TGRC
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 122Ah MTU4
Timer General Register D
TGRD
16
16
4, 5 PCLKA
2, 3 ICLK
000C 122Ch MTU3
Timer Status Register
TSR
8
8, 16
4, 5 PCLKA
2, 3 ICLK
000C 122Dh MTU4
Timer Status Register
TSR
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1230h MTU
Timer Interrupt Skipping Set Register 1A
TITCR1A
8
8, 16
4, 5 PCLKA
2, 3 ICLK
000C 1231h MTU
Timer Interrupt Skipping Counters 1A
TITCNT1A
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1232h MTU
Timer Buffer Transfer Set Register A
TBTERA
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1234h MTU
Timer dead time enable register A
TDERA
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1236h MTU
Timer output level buffer register A
TOLBRA
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1238h MTU3
Timer Buffer Operation Transfer Mode
Register
TBTM
8
8, 16
4, 5 PCLKA
2, 3 ICLK
000C 1239h MTU4
Timer Buffer Operation Transfer Mode
Register
TBTM
8
8
4, 5 PCLKA
2, 3 ICLK
000C 123Ah MTU
Timer Interrupt Skipping Mode Register A
TITMRA
8
8
4, 5 PCLKA
2, 3 ICLK
000C 123Bh MTU
Timer Interrupt Skipping Set Register 2A
TITCR2A
8
8
4, 5 PCLKA
2, 3 ICLK
000C 123Ch MTU
Timer Interrupt Skipping Counters 2A
TITCNT2A
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1240h MTU4
Timer A/D Converter Start Request Control
Register
TADCR
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1244h MTU4
Timer A/D Converter Start Request Cycle
Set Register A
TADCORA
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 1246h MTU4
Timer A/D Converter Start Request Cycle
Set Register B
TADCORB
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1248h MTU4
Timer A/D Converter Start Request Cycle
Set Buffer Register A
TADCOBRA
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 124Ah MTU4
Timer A/D Converter Start Request Cycle
Set Buffer Register B
TADCOBRB
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1260h MTU
Timer Waveform Control Register A
TWCRA
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1270h MTU
Timer Mode Register 2A
TMDR2A
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1272h MTU3
Timer General Register E
TGRE
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1274h MTU4
Timer General Register E
TGRE
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1276h MTU4
Timer General Register F
TGRF
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1280h MTU
Timer Start Register A
TSTRA
8
8, 16
4, 5 PCLKA
2, 3 ICLK
000C 1281h MTU
Timer Synchronous Register A
TSYRA
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1282h MTU
Timer Counter Synchronous Start Register
TCSYSTR
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1284h MTU
Timer Read/Write Enable Register A
TRWERA
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1300h MTU0
Timer Control Register
TCR
8
8, 16, 32 4, 5 PCLKA
2, 3 ICLK
000C 1301h MTU0
Timer Mode Register 1
TMDR1
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1302h MTU0
Timer I/O Control Register H
TIORH
8
8, 16
4, 5 PCLKA
2, 3 ICLK
000C 1303h MTU0
Timer I/O Control Register L
TIORL
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1304h MTU0
Timer Interrupt Enable Register
TIER
8
8, 16, 32 4, 5 PCLKA
2, 3 ICLK
000C 1305h MTU0
Timer Status Register
TSR
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1306h MTU0
Timer Counter
TCNT
16
16
4, 5 PCLKA
2, 3 ICLK
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Remarks
Page 88 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (35/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
MTU3
000C 1308h MTU0
Timer General Register A
TGRA
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 130Ah MTU0
Timer General Register B
TGRB
16
16
4, 5 PCLKA
2, 3 ICLK
000C 130Ch MTU0
Timer General Register C
TGRC
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 130Eh MTU0
Timer General Register D
TGRD
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1320h MTU0
Timer General Register E
TGRE
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 1322h MTU0
Timer General Register F
TGRF
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1324h MTU0
Timer Interrupt Enable Register 2
TIER2
8
8, 16
4, 5 PCLKA
2, 3 ICLK
000C 1325h MTU0
Timer Status Register 2
TSR2
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1326h MTU0
Timer Buffer Operation Transfer Mode
Register
TBTM
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1380h MTU1
Timer Control Register
TCR
8
8, 16
4, 5 PCLKA
2, 3 ICLK
000C 1381h MTU1
Timer Mode Register 1
TMDR1
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1382h MTU1
Timer I/O Control Register
TIOR
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1384h MTU1
Timer Interrupt Enable Register
TIER
8
8, 16, 32 4, 5 PCLKA
2, 3 ICLK
000C 1385h MTU1
Timer Status Register
TSR
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1386h MTU1
Timer Counter
TCNT
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1388h MTU1
Timer General Register A
TGRA
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 138Ah MTU1
Timer General Register B
TGRB
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1390h MTU1
Timer Input Capture Control Register
TICCR
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1400h MTU2
Timer Control Register
TCR
8
8, 16
4, 5 PCLKA
2, 3 ICLK
000C 1401h MTU2
Timer Mode Register 1
TMDR1
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1402h MTU2
Timer I/O Control Register
TIOR
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1404h MTU2
Timer Interrupt Enable Register
TIER
8
8, 16, 32 4, 5 PCLKA
2, 3 ICLK
000C 1405h MTU2
Timer Status Register
TSR
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1406h MTU2
Timer Counter
TCNT
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1408h MTU2
Timer General Register A
TGRA
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 140Ah MTU2
Timer General Register B
TGRB
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1A00h MTU6
Timer Control Register
TCR
8
8, 16, 32 4, 5 PCLKA
2, 3 ICLK
000C 1A01h MTU7
Timer Control Register
TCR
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1A02h MTU6
Timer Mode Register 1
TMDR1
8
8, 16
4, 5 PCLKA
2, 3 ICLK
000C 1A03h MTU7
Timer Mode Register 1
TMDR1
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1A04h MTU6
Timer I/O Control Register H
TIORH
8
8, 16, 32 4, 5 PCLKA
2, 3 ICLK
000C 1A05h MTU6
Timer I/O Control Register L
TIORL
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1A06h MTU7
Timer I/O Control Register H
TIORH
8
8, 16
4, 5 PCLKA
2, 3 ICLK
000C 1A07h MTU7
Timer I/O Control Register L
TIORL
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1A08h MTU6
Timer Interrupt Enable Register
TIER
8
8, 16
4, 5 PCLKA
2, 3 ICLK
000C 1A09h MTU7
Timer Interrupt Enable Register
TIER
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1A0Ah MTU
Timer Output Master Enable Register B
TOERB
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1A0Eh MTU
Timer Output Control Register 1B
TOCR1B
8
8, 16
4, 5 PCLKA
2, 3 ICLK
000C 1A0Fh MTU
Timer Output Control Register 2B
TOCR2B
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1A10h MTU6
Timer Counter
TCNT
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 1A12h MTU7
Timer Counter
TCNT
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1A14h MTU
Timer Cycle Data Register B
TCDRB
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 1A16h MTU
Timer Dead Time Data Register B
TDDRB
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1A18h MTU6
Timer General Register A
TGRA
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 1A1Ah MTU6
Timer General Register B
TGRB
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1A1Ch MTU7
Timer General Register A
TGRA
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 1A1Eh MTU7
Timer General Register B
TGRB
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1A20h MTU
Timer Subcounter B
TCNTSB
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 1A22h MTU
Timer Cycle Buffer Register B
TCBRB
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1A24h MTU6
Timer General Register C
TGRC
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 1A26h MTU6
Timer General Register D
TGRD
16
16
4, 5 PCLKA
2, 3 ICLK
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Remarks
Page 89 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (36/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
MTU3
000C 1A28h MTU7
Timer General Register C
TGRC
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 1A2Ah MTU7
Timer General Register D
TGRD
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1A2Ch MTU6
Timer Status Register
TSR
8
8, 16
4, 5 PCLKA
2, 3 ICLK
000C 1A2Dh MTU7
Timer Status Register
TSR
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1A30h MTU
Timer Interrupt Skipping Set Register 1B
TITCR1B
8
8, 16
4, 5 PCLKA
2, 3 ICLK
000C 1A31h MTU
Timer Interrupt Skipping Counters 1B
TITCNT1B
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1A32h MTU
Timer Buffer Transfer Set Register B
TBTERB
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1A34h MTU
Timer Dead Time Enable Register B
TDERB
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1A36h MTU
Timer Output Level Buffer Register B
TOLBRB
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1A38h MTU6
Timer Buffer Operation Transfer Mode
Register
TBTM
8
8, 16
4, 5 PCLKA
2, 3 ICLK
000C 1A39h MTU7
Timer Buffer Operation Transfer Mode
Register
TBTM
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1A3Ah MTU
Timer Interrupt Skipping Mode Register B
TITMRB
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1A3Bh MTU
Timer Interrupt Skipping Set Register 2B
TITCR2B
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1A3Ch MTU
Timer Interrupt Skipping Counters 2B
TITCNT2B
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1A40h MTU7
Timer A/D Converter Start Request Control
Register
TADCR
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1A44h MTU7
Timer A/D Converter Start Request Cycle
Set Register A
TADCORA
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 1A46h MTU7
Timer A/D Converter Start Request Cycle
Set Register B
TADCORB
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1A48h MTU7
Timer A/D Converter Start Request Cycle
Set Buffer Register A
TADCOBRA
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 1A4Ah MTU7
Timer A/D Converter Start Request Cycle
Set Buffer Register B
TADCOBRB
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1A50h MTU
Timer Synchronous Clear Register
TSYCR
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1A60h MTU
Timer Waveform Control Register B
TWCRB
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1A70h MTU
Timer Mode Register 2B
TMDR2B
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1A72h MTU6
Timer General Register E
TGRE
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1A74h MTU7
Timer General Register E
TGRE
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1A76h MTU7
Timer General Register F
TGRF
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1A80h MTU
Timer Start Register B
TSTRB
8
8, 16
4, 5 PCLKA
2, 3 ICLK
000C 1A81h MTU
Timer Synchronous Register B
TSYRB
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1A84h MTU
Timer Read/Write Enable Register B
TRWERB
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1C80h MTU5
Timer Counter U
TCNTU
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 1C82h MTU5
Timer General Register U
TGRU
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1C84h MTU5
Timer Control Register U
TCRU
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1C86h MTU5
Timer I/O Control Register U
TIORU
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1C90h MTU5
Timer Counter V
TCNTV
16
16, 32
4, 5 PCLKA
2, 3 ICLK
2, 3 ICLK
000C 1C92h MTU5
Timer General Register V
TGRV
16
16
4, 5 PCLKA
000C 1C94h MTU5
Timer Control Register V
TCRV
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1C96h MTU5
Timer I/O Control Register V
TIORV
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1CA0h MTU5
Timer Counter W
TCNTW
16
16, 32
4, 5 PCLKA
2, 3 ICLK
000C 1CA2h MTU5
Timer General Register W
TGRW
16
16
4, 5 PCLKA
2, 3 ICLK
000C 1CA4h MTU5
Timer Control Register W
TCRW
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1CA6h MTU5
Timer I/O Control Register W
TIORW
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1CB0h MTU5
Timer Status Register
TSR
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1CB2h MTU5
Timer Interrupt Enable Register
TIER
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1CB4h MTU5
Timer Start Register
TSTR
8
8
4, 5 PCLKA
2, 3 ICLK
000C 1CB6h MTU5
Timer Compare Match Clear Register
TCNTCMPC 8
LR
8
4, 5 PCLKA
2, 3 ICLK
000C 2000h GPT
General PWM Timer Software Start Register
GTSTR
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2004h GPT
General PWM Timer Hardware Source Start GTHSCR
Control Register
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Remarks
GPT
Page 90 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (37/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
GPT
000C 2006h GPT
General PWM Timer Hardware Source
Clear Control Register
GTHCCR
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2008h GPT
General PWM Timer Hardware Start Source GTHSSR
Select Register
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 200Ah GPT
General PWM Timer Hardware Stop/Clear
Source Select Register
GTHPSR
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 200Ch GPT
General PWM Timer Write-Protection Register
GTWP
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 200Eh GPT
General PWM Timer Sync Register
GTSYNC
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2010h GPT
General PWM Timer External Trigger Input
Interrupt Register
GTETINT
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2014h GPT
General PWM Timer Buffer Operation
Disable Register
GTBDR
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2018h GPT
General PWM Timer Start Write-Protection
Register
GTSWP
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2080h GPT
LOCO Count Control Register
LCCR
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2082h GPT
LOCO Count Status Register
LCST
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2084h GPT
LOCO Count Value Register
LCNT
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2086h GPT
LOCO Count Result Average Register
LCNTA
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2088h GPT
LOCO Count Result Register 0
LCNT00
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 208Ah GPT
LOCO Count Result Register 1
LCNT01
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 208Ch GPT
LOCO Count Result Register 2
LCNT02
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 208Eh GPT
LOCO Count Result Register 3
LCNT03
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2090h GPT
LOCO Count Result Register 4
LCNT04
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2092h GPT
LOCO Count Result Register 5
LCNT05
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2094h GPT
LOCO Count Result Register 6
LCNT06
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2096h GPT
LOCO Count Result Register 7
LCNT07
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2098h
GPT
LOCO Count Result Register 8
LCNT08
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 209Ah GPT
LOCO Count Result Register 9
LCNT09
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 209Ch GPT
LOCO Count Result Register 10
LCNT10
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 209Eh GPT
LOCO Count Result Register 11
LCNT11
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 20A0h GPT
LOCO Count Result Register 12
LCNT12
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 20A2h GPT
LOCO Count Result Register 13
LCNT13
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 20A4h GPT
LOCO Count Result Register 14
LCNT14
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 20A6h GPT
LOCO Count Result Register 15
LCNT15
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 20A8h GPT
LOCO Count Upper Permissible Deviation
Register
LCNTDU
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 20AAh GPT
LOCO Count Lower Permissible Deviation
Register
LCNTDL
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2100h GPT0
General PWM Timer I/O Control Register
GTIOR
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2102h GPT0
General PWM Timer Interrupt Output Setting GTINTAD
Register
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2104h GPT0
General PWM Timer Control Register
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2106h GPT0
General PWM Timer Buffer Enable Register GTBER
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2108h GPT0
General PWM Timer Count Direction Register
GTUDC
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 210Ah GPT0
General PWM Timer Interrupt,
A/D Converter Start Request Skipping
Setting Register
GTITC
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 210Ch GPT0
General PWM Timer Status Register
GTST
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 210Eh GPT0
General PWM Timer Counter
GTCNT
16
16
2 to 5 PCLKA
2, 3 ICLK
000C 2110h
GPT0
General PWM Timer Compare Capture
Register A
GTCCRA
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2112h
GPT0
General PWM Timer Compare Capture
Register B
GTCCRB
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2114h
GPT0
General PWM Timer Compare Capture
Register C
GTCCRC
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2116h
GPT0
General PWM Timer Compare Capture
Register D
GTCCRD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2118h
GPT0
General PWM Timer Compare Capture
Register E
GTCCRE
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
GTCR
Remarks
Page 91 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (38/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
GTCCRF
16
2 to 5 PCLKA
2, 3 ICLK
GPT
000C 211Ah GPT0
General PWM Timer Compare Capture
Register F
000C 211Ch GPT0
General PWM Timer Cycle Setting Register
GTPR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 211Eh GPT0
General PWM Timer Cycle Setting Buffer
Register
GTPBR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2120h GPT0
General PWM Timer Cycle Setting DoubleBuffer Register
GTPDBR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2124h GPT0
A/D Converter Start Request Timing Register GTADTRA
A
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2126h GPT0
A/D Converter Start Request Timing Buffer
Register A
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2128h GPT0
A/D Converter Start Request Timing Double- GTADTDBRA 16
Buffer Register A
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 212Ch GPT0
A/D Converter Start Request Timing Register GTADTRB
B
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 212Eh GPT0
A/D Converter Start Request Timing Buffer
Register B
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2130h GPT0
A/D Converter Start Request Timing Double- GTADTDBRB 16
Buffer Register B
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2134h GPT0
General PWM Timer Output Negate Control GTONCR
Register
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2136h GPT0
General PWM Timer Dead Time Control
Register
GTDTCR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2138h GPT0
General PWM Timer Dead Time Value
Register U
GTDVU
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 213Ah GPT0
General PWM Timer Dead Time Value
Register D
GTDVD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 213Ch GPT0
General PWM Timer Dead Time Buffer
Register U
GTDBU
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 213Eh GPT0
General PWM Timer Dead Time Buffer
Register D
GTDBD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2140h GPT0
General PWM Timer Output Protection
Function Status Register
GTSOS
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2142h GPT0
General PWM Timer Output Protection
Function Temporary Release Register
GTSOTR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2180h GPT1
General PWM Timer I/O Control Register
GTIOR
000C 2182h GPT1
General PWM Timer Interrupt Output Setting GTINTAD
Register
GTADTBRA
GTADTBRB
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2184h GPT1
General PWM Timer Control Register
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2186h GPT1
General PWM Timer Buffer Enable Register GTBER
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2188h GPT1
General PWM Timer Count Direction Register GTUDC
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 218Ah GPT1
General PWM Timer Interrupt,
A/D Converter Start Request Skipping
Setting Register
GTITC
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 218Ch GPT1
General PWM Timer Status Register
GTST
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 218Eh GPT1
General PWM Timer Counter
GTCNT
16
16
2 to 5 PCLKA
2, 3 ICLK
000C 2190h GPT1
General PWM Timer Compare Capture
Register A
GTCCRA
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2192h GPT1
General PWM Timer Compare Capture
Register B
GTCCRB
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2194h GPT1
General PWM Timer Compare Capture
Register C
GTCCRC
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2196h GPT1
General PWM Timer Compare Capture
Register D
GTCCRD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2198h GPT1
General PWM Timer Compare Capture
Register E
GTCCRE
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 219Ah GPT1
General PWM Timer Compare Capture
Register F
GTCCRF
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 219Ch GPT1
General PWM Timer Cycle Setting Register
GTPR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 219Eh GPT1
General PWM Timer Cycle Setting Buffer
Register
GTPBR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 21A0h GPT1
General PWM Timer Cycle Setting DoubleBuffer Register
GTPDBR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 21A4h GPT1
A/D Converter Start Request Timing Register GTADTRA
A
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
GTCR
16, 32
Remarks
Page 92 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (39/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
GTADTBRA
GPT
000C 21A6h GPT1
A/D Converter Start Request Timing Buffer
Register A
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 21A8h GPT1
A/D Converter Start Request Timing Double- GTADTDBRA 16
Buffer Register A
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 21ACh GPT1
A/D Converter Start Request Timing Register GTADTRB
B
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 21AEh GPT1
A/D Converter Start Request Timing Buffer
Register B
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 21B0h GPT1
A/D Converter Start Request Timing Double- GTADTDBRB 16
Buffer Register B
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 21B4h GPT1
General PWM Timer Output Negate Control GTONCR
Register
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 21B6h GPT1
General PWM Timer Dead Time Control
Register
GTDTCR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 21B8h GPT1
General PWM Timer Dead Time Value
Register U
GTDVU
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 21BAh GPT1
General PWM Timer Dead Time Value
Register D
GTDVD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 21BCh GPT1
General PWM Timer Dead Time Buffer
Register U
GTDBU
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 21BEh GPT1
General PWM Timer Dead Time Buffer
Register D
GTDBD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 21C0h GPT1
General PWM Timer Output Protection
Function Status Register
GTSOS
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 21C2h GPT1
General PWM Timer Output Protection
Function Temporary Release Register
GTSOTR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2200h GPT2
General PWM Timer I/O Control Register
GTIOR
000C 2202h GPT2
General PWM Timer Interrupt Output Setting GTINTAD
Register
GTADTBRB
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2204h GPT2
General PWM Timer Control Register
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2206h GPT2
General PWM Timer Buffer Enable Register GTBER
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2208h GPT2
General PWM Timer Count Direction
Register
GTUDC
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 220Ah GPT2
General PWM Timer Interrupt and A/D
Converter Start Request Skipping Setting
Register
GTITC
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 220Ch GPT2
General PWM Timer Status Register
GTST
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 220Eh GPT2
General PWM Timer Counter
GTCNT
16
16
2 to 5 PCLKA
2, 3 ICLK
000C 2210h GPT2
General PWM Timer Compare Capture
Register A
GTCCRA
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2212h GPT2
General PWM Timer Compare Capture
Register B
GTCCRB
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2214h GPT2
General PWM Timer Compare Capture
Register C
GTCCRC
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2216h GPT2
General PWM Timer Compare Capture
Register D
GTCCRD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2218h GPT2
General PWM Timer Compare Capture
Register E
GTCCRE
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 221Ah GPT2
General PWM Timer Compare Capture
Register F
GTCCRF
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 221Ch GPT2
General PWM Timer Cycle Setting Register
GTPR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 221Eh GPT2
General PWM Timer Cycle Setting Buffer
Register
GTPBR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2220h GPT2
General PWM Timer Cycle Setting DoubleBuffer Register
GTPDBR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2224h GPT2
A/D Converter Start Request Timing Register GTADTRA
A
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2226h GPT2
A/D Converter Start Request Timing Buffer
Register A
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2228h GPT2
A/D Converter Start Request Timing Double- GTADTDBRA 16
Buffer Register A
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 222Ch GPT2
A/D Converter Start Request Timing Register GTADTRB
B
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 222Eh GPT2
A/D Converter Start Request Timing Buffer
Register B
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
GTCR
16
16
GTADTBRA
GTADTBRB
Remarks
Page 93 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (40/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
GPT
000C 2230h GPT2
A/D Converter Start Request Timing Double- GTADTDBRB 16
Buffer Register B
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2234h GPT2
General PWM Timer Output Negate Control GTONCR
Register
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2236h GPT2
General PWM Timer Dead Time Control
Register
GTDTCR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2238h GPT2
General PWM Timer Dead Time Value
Register U
GTDVU
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 223Ah GPT2
General PWM Timer Dead Time Value
Register D
GTDVD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 223Ch GPT2
General PWM Timer Dead Time Buffer
Register U
GTDBU
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 223Eh GPT2
General PWM Timer Dead Time Buffer
Register D
GTDBD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2240h GPT2
General PWM Timer Output Protection
Function Status Register
GTSOS
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2242h GPT2
General PWM Timer Output Protection
Function Temporary Release Register
GTSOTR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2280h GPT3
General PWM Timer I/O Control Register
GTIOR
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2282h GPT3
General PWM Timer Interrupt Output Setting GTINTAD
Register
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2284h GPT3
General PWM Timer Control Register
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
GTCR
000C 2286h GPT3
General PWM Timer Buffer Enable Register GTBER
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2288h GPT3
General PWM Timer Count Direction Register
GTUDC
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 228Ah GPT3
General PWM Timer Interrupt and A/D
Converter Start Request Skipping Setting
Register
GTITC
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 228Ch GPT3
General PWM Timer Status Register
GTST
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 228Eh GPT3
General PWM Timer Counter
GTCNT
16
16
2 to 5 PCLKA
2, 3 ICLK
000C 2290h GPT3
General PWM Timer Compare Capture
Register A
GTCCRA
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2292h GPT3
General PWM Timer Compare Capture
Register B
GTCCRB
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2294h GPT3
General PWM Timer Compare Capture
Register C
GTCCRC
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2296h GPT3
General PWM Timer Compare Capture
Register D
GTCCRD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2298h GPT3
General PWM Timer Compare Capture
Register E
GTCCRE
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 229Ah GPT3
General PWM Timer Compare Capture
Register F
GTCCRF
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 229Ch GPT3
General PWM Timer Cycle Setting Register
GTPR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 229Eh GPT3
General PWM Timer Cycle Setting Buffer
Register
GTPBR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 22A0h GPT3
General PWM Timer Cycle Setting DoubleBuffer Register
GTPDBR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 22A4h GPT3
A/D Converter Start Request Timing Register GTADTRA
A
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 22A6h GPT3
A/D Converter Start Request Timing Buffer
Register A
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 22A8h GPT3
A/D Converter Start Request Timing Double- GTADTDBRA 16
Buffer Register A
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 22ACh GPT3
A/D Converter Start Request Timing Register GTADTRB
B
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 22AEh GPT3
A/D Converter Start Request Timing Buffer
Register B
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 22B0h GPT3
A/D Converter Start Request Timing Double- GTADTDBRB 16
Buffer Register B
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 22B4h GPT3
General PWM Timer Output Negate Control GTONCR
Register
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 22B6h GPT3
General PWM Timer Dead Time Control
Register
GTDTCR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 22B8h GPT3
General PWM Timer Dead Time Value
Register U
GTDVU
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
GTADTBRA
GTADTBRB
Remarks
Page 94 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (41/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
GPT
Remarks
000C 22BAh GPT3
General PWM Timer Dead Time Value
Register D
GTDVD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 22BCh GPT3
General PWM Timer Dead Time Buffer
Register U
GTDBU
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 22BEh GPT3
General PWM Timer Dead Time Buffer
Register D
GTDBD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 22C0h GPT3
General PWM Timer Output Protection
Function Status Register
GTSOS
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 22C2h GPT3
General PWM Timer Output Protection
Function Temporary Release Register
GTSOTR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2318h
GPT0
GTIOCA Rising Output Delay Register
GTDLYRA
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 231Ah GPT0
GTIOCB Rising Output Delay Register
GTDLYRB
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 231Ch GPT1
GTIOCA Rising Output Delay Register
GTDLYRA
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 231Eh GPT1
GTIOCB Rising Output Delay Register
GTDLYRB
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 2320h
GPT2
GTIOCA Rising Output Delay Register
GTDLYRA
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 2322h
GPT2
GTIOCB Rising Output Delay Register
GTDLYRB
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 2324h
GPT3
GTIOCA Rising Output Delay Register
GTDLYRA
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 2326h
GPT3
GTIOCB Rising Output Delay Register
GTDLYRB
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 2328h
GPT0
GTIOCA Falling Output Delay Register
GTDLYFA
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 232Ah GPT0
GTIOCB Falling Output Delay Register
GTDLYFB
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 232Ch GPT1
GTIOCA Falling Output Delay Register
GTDLYFA
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 232Eh GPT1
GTIOCB Falling Output Delay Register
GTDLYFB
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 2330h
GPT2
GTIOCA Falling Output Delay Register
GTDLYFA
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 2332h
GPT2
GTIOCB Falling Output Delay Register
GTDLYFB
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 2334h
GPT3
GTIOCA Falling Output Delay Register
GTDLYFA
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 2336h
GPT3
GTIOCB Falling Output Delay Register
GTDLYFB
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 2800h GPTB
General PWM Timer Software Start Register GTSTR
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 2804h GPTB
General PWM Timer Hardware Source Start GTHSCR
Control Register
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 2806h GPTB
General PWM Timer Hardware Source
Clear Control Register
GTHCCR
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 2808h GPTB
General PWM Timer Hardware Start Source GTHSSR
Select Register
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 280Ah GPTB
General PWM Timer Hardware Stop/Clear
Source Select Register
GTHPSR
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 280Ch GPTB
General PWM Timer Write-Protection
Register
GTWP
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 280Eh GPTB
General PWM Timer Sync Register
GTSYNC
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 2810h GPTB
General PWM Timer External Trigger Input
Interrupt Register
GTETINT
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 2814h GPTB
General PWM Timer Buffer Operation
Disable Register
GTBDR
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 2818h GPTB
General PWM Timer Start Write-Protection
Register
GTSWP
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 2880h GPTB
LOCO Count Control Register
LCCR
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 2882h GPTB
LOCO Count Status Register
LCST
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 95 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (42/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
GPT
Remarks
000C 2884h GPTB
LOCO Count Value Register
LCNT
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
000C 2886h GPTB
LOCO Count Result Average Register
LCNTA
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 2888h GPTB
LOCO Count Result Register 0
LCNT00
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 288Ah GPTB
LOCO Count Result Register 1
LCNT01
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64, or 48 pins.
000C 288Ch GPTB
LOCO Count Result Register 2
LCNT02
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 288Eh GPTB
LOCO Count Result Register 3
LCNT03
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2890h GPTB
LOCO Count Result Register 4
LCNT04
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2892h GPTB
LOCO Count Result Register 5
LCNT05
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2894h GPTB
LOCO Count Result Register 6
LCNT06
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2896h GPTB
LOCO Count Result Register 7
LCNT07
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2898h
GPTB
LOCO Count Result Register 8
LCNT08
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 289Ah GPTB
LOCO Count Result Register 9
LCNT09
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 289Ch GPTB
LOCO Count Result Register 10
LCNT10
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 289Eh GPTB
LOCO Count Result Register 11
LCNT11
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 28A0h GPTB
LOCO Count Result Register 12
LCNT12
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 28A2h GPTB
LOCO Count Result Register 13
LCNT13
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 28A4h GPTB
LOCO Count Result Register 14
LCNT14
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 28A6h GPTB
LOCO Count Result Register 15
LCNT15
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 28A8h GPTB
LOCO Count Upper Permissible Deviation
Register
LCNTDU
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 28AAh GPTB
LOCO Count Lower Permissible Deviation
Register
LCNTDL
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2900h GPT4
General PWM Timer I/O Control Register
GTIOR
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2902h GPT4
General PWM Timer Interrupt Output Setting GTINTAD
Register
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2904h GPT4
General PWM Timer Control Register
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2906h GPT4
General PWM Timer Buffer Enable Register GTBER
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2908h GPT4
General PWM Timer Count Direction
Register
GTUDC
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 290Ah GPT4
General PWM Timer Interrupt and A/D
Converter Start Request Skipping Setting
Register
GTITC
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 290Ch GPT4
General PWM Timer Status Register
GTST
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 290Eh GPT4
General PWM Timer Counter
GTCNT
16
16
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2910h GPT4
General PWM Timer Compare Capture
Register A
GTCCRA
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2912h GPT4
General PWM Timer Compare Capture
Register B
GTCCRB
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2914h GPT4
General PWM Timer Compare Capture
Register C
GTCCRC
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2916h GPT4
General PWM Timer Compare Capture
Register D
GTCCRD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2918h GPT4
General PWM Timer Compare Capture
Register E
GTCCRE
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
GTCR
Not present in versions
with 64, or 48 pins.
Page 96 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (43/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
GPT
Remarks
000C 291Ah GPT4
General PWM Timer Compare Capture
Register F
GTCCRF
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 291Ch GPT4
General PWM Timer Cycle Setting Register
GTPR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 291Eh GPT4
General PWM Timer Cycle Setting Buffer
Register
GTPBR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2920h GPT4
General PWM Timer Cycle Setting DoubleBuffer Register
GTPDBR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2924h GPT4
A/D Converter Start Request Timing Register GTADTRA
A
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2926h GPT4
A/D Converter Start Request Timing Buffer
Register A
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2928h GPT4
A/D Converter Start Request Timing Double- GTADTDBRA 16
Buffer Register A
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 292Ch GPT4
A/D Converter Start Request Timing Register GTADTRB
B
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 292Eh GPT4
A/D Converter Start Request Timing Buffer
Register B
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2930h GPT4
A/D Converter Start Request Timing Double- GTADTDBRB 16
Buffer Register B
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2934h GPT4
General PWM Timer Output Negate Control GTONCR
Register
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2936h GPT4
General PWM Timer Dead Time Control
Register
GTDTCR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2938h GPT4
General PWM Timer Dead Time Value
Register U
GTDVU
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 293Ah GPT4
General PWM Timer Dead Time Value
Register D
GTDVD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 293Ch GPT4
General PWM Timer Dead Time Buffer
Register U
GTDBU
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 293Eh GPT4
General PWM Timer Dead Time Buffer
Register D
GTDBD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2940h GPT4
General PWM Timer Output Protection
Function Status Register
GTSOS
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2942h GPT4
General PWM Timer Output Protection
Function Temporary Release Register
GTSOTR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2980h GPT5
General PWM Timer I/O Control Register
GTIOR
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2982h GPT5
General PWM Timer Interrupt Output Setting GTINTAD
Register
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2984h GPT5
General PWM Timer Control Register
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2986h GPT5
General PWM Timer Buffer Enable Register GTBER
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2988h GPT5
General PWM Timer Count Direction
Register
GTUDC
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 298Ah GPT5
General PWM Timer Interrupt and A/D
Converter Start Request Skipping Setting
Register
GTITC
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 298Ch GPT5
General PWM Timer Status Register
GTST
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 298Eh GPT5
General PWM Timer Counter
GTCNT
16
16
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2990h GPT5
General PWM Timer Compare Capture
Register A
GTCCRA
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2992h GPT5
General PWM Timer Compare Capture
Register B
GTCCRB
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2994h GPT5
General PWM Timer Compare Capture
Register C
GTCCRC
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2996h GPT5
General PWM Timer Compare Capture
Register D
GTCCRD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2998h GPT5
General PWM Timer Compare Capture
Register E
GTCCRE
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 299Ah GPT5
General PWM Timer Compare Capture
Register F
GTCCRF
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 299Ch GPT5
General PWM Timer Cycle Setting Register
GTPR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
GTADTBRA
GTADTBRB
GTCR
Not present in versions
with 64 or 48 pins.
Page 97 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (44/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
GPT
Remarks
000C 299Eh GPT5
General PWM Timer Cycle Setting Buffer
Register
GTPBR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 29A0h GPT5
General PWM Timer Cycle Setting DoubleBuffer Register
GTPDBR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 29A4h GPT5
A/D Converter Start Request Timing Register GTADTRA
A
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 29A6h GPT5
A/D Converter Start Request Timing Buffer
Register A
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 29A8h GPT5
A/D Converter Start Request Timing Double- GTADTDBRA 16
Buffer Register A
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 29ACh GPT5
A/D Converter Start Request Timing Register GTADTRB
B
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 29AEh GPT5
A/D Converter Start Request Timing Buffer
Register B
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 29B0h GPT5
A/D Converter Start Request Timing Double- GTADTDBRB 16
Buffer Register B
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 29B4h GPT5
General PWM Timer Output Negate Control GTONCR
Register
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 29B6h GPT5
General PWM Timer Dead Time Control
Register
GTDTCR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 29B8h GPT5
General PWM Timer Dead Time Value
Register U
GTDVU
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 29BAh GPT5
General PWM Timer Dead Time Value
Register D
GTDVD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 29BCh GPT5
General PWM Timer Dead Time Buffer
Register U
GTDBU
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 29BEh GPT5
General PWM Timer Dead Time Buffer
Register D
GTDBD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 29C0h GPT5
General PWM Timer Output Protection
Function Status Register
GTSOS
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 29C2h GPT5
General PWM Timer Output Protection
Function Temporary Release Register
GTSOTR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A00h GPT6
General PWM Timer I/O Control Register
GTIOR
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A02h GPT6
General PWM Timer Interrupt Output Setting GTINTAD
Register
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A04h GPT6
General PWM Timer Control Register
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A06h GPT6
General PWM Timer Buffer Enable Register GTBER
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A08h GPT6
General PWM Timer Count Direction
Register
GTUDC
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A0Ah GPT6
General PWM Timer Interrupt,
A/D Converter Start Request Skipping
Setting Register
GTITC
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A0Ch GPT6
General PWM Timer Status Register
GTST
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A0Eh GPT6
General PWM Timer Counter
GTCNT
16
16
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A10h GPT6
General PWM Timer Compare Capture
Register A
GTCCRA
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A12h GPT6
General PWM Timer Compare Capture
Register B
GTCCRB
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A14h GPT6
General PWM Timer Compare Capture
Register C
GTCCRC
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A16h GPT6
General PWM Timer Compare Capture
Register D
GTCCRD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A18h GPT6
General PWM Timer Compare Capture
Register E
GTCCRE
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A1Ah GPT6
General PWM Timer Compare Capture
Register F
GTCCRF
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A1Ch GPT6
General PWM Timer Cycle Setting Register
GTPR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A1Eh GPT6
General PWM Timer Cycle Setting Buffer
Register
GTPBR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A20h GPT6
General PWM Timer Cycle Setting DoubleBuffer Register
GTPDBR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
GTADTBRA
GTADTBRB
GTCR
Not present in versions
with 64 or 48 pins.
Page 98 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (45/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
GPT
Remarks
000C 2A24h GPT6
A/D Converter Start Request Timing Register GTADTRA
A
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2A26h GPT6
A/D Converter Start Request Timing Buffer
Register A
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A28h GPT6
A/D Converter Start Request Timing Double- GTADTDBRA 16
Buffer Register A
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A2Ch GPT6
A/D Converter Start Request Timing Register GTADTRB
B
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A2Eh GPT6
A/D Converter Start Request Timing Buffer
Register B
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A30h GPT6
A/D Converter Start Request Timing Double- GTADTDBRB 16
Buffer Register B
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A34h GPT6
General PWM Timer Output Negate Control GTONCR
Register
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A36h GPT6
General PWM Timer Dead Time Control
Register
GTDTCR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A38h GPT6
General PWM Timer Dead Time Value
Register U
GTDVU
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A3Ah GPT6
General PWM Timer Dead Time Value
Register D
GTDVD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A3Ch GPT6
General PWM Timer Dead Time Buffer
Register U
GTDBU
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A3Eh GPT6
General PWM Timer Dead Time Buffer
Register D
GTDBD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A40h GPT6
General PWM Timer Output Protection
Function Status Register
GTSOS
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A42h GPT6
General PWM Timer Output Protection
Function Temporary Release Register
GTSOTR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A80h GPT7
General PWM Timer I/O Control Register
GTIOR
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A82h GPT7
General PWM Timer Interrupt Output Setting GTINTAD
Register
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A84h GPT7
General PWM Timer Control Register
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A86h GPT7
General PWM Timer Buffer Enable Register GTBER
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A88h GPT7
General PWM Timer Count Direction
Register
GTUDC
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A8Ah GPT7
General PWM Timer Interrupt and A/D
Converter Start Request Skipping Setting
Register
GTITC
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A8Ch GPT7
General PWM Timer Status Register
GTST
16
8, 16, 32 2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A8Eh GPT7
General PWM Timer Counter
GTCNT
16
16
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A90h GPT7
General PWM Timer Compare Capture
Register A
GTCCRA
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A92h GPT7
General PWM Timer Compare Capture
Register B
GTCCRB
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A94h GPT7
General PWM Timer Compare Capture
Register C
GTCCRC
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A96h GPT7
General PWM Timer Compare Capture
Register D
GTCCRD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A98h GPT7
General PWM Timer Compare Capture
Register E
GTCCRE
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A9Ah GPT7
General PWM Timer Compare Capture
Register F
GTCCRF
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A9Ch GPT7
General PWM Timer Cycle Setting Register
GTPR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2A9Eh GPT7
General PWM Timer Cycle Setting Buffer
Register
GTPBR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2AA0h GPT7
General PWM Timer Cycle Setting DoubleBuffer Register
GTPDBR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2AA4h GPT7
A/D Converter Start Request Timing Register GTADTRA
A
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2AA6h GPT7
A/D Converter Start Request Timing Buffer
Register A
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
GTADTBRA
GTADTBRB
GTCR
GTADTBRA
Not present in versions
with 64 or 48 pins.
Page 99 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (46/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
GPT
Remarks
000C 2AA8h GPT7
A/D Converter Start Request Timing Double- GTADTDBRA 16
Buffer Register A
16, 32
2 to 5 PCLKA
2, 3 ICLK
000C 2AACh GPT7
A/D Converter Start Request Timing Register GTADTRB
B
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2AAEh GPT7
A/D Converter Start Request Timing Buffer
Register B
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2AB0h GPT7
A/D Converter Start Request Timing Double- GTADTDBRB 16
Buffer Register B
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2AB4h GPT7
General PWM Timer Output Negate Control GTONCR
Register
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2AB6h GPT7
General PWM Timer Dead Time Control
Register
GTDTCR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2AB8h GPT7
General PWM Timer Dead Time Value
Register U
GTDVU
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2ABAh GPT7
General PWM Timer Dead Time Value
Register D
GTDVD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2ABCh GPT7
General PWM Timer Dead Time Buffer
Register U
GTDBU
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2ABEh GPT7
General PWM Timer Dead Time Buffer
Register D
GTDBD
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2AC0h GPT7
General PWM Timer Output Protection
Function Status Register
GTSOS
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C 2AC2h GPT7
General PWM Timer Output Protection
Function Temporary Release Register
GTSOTR
16
16, 32
2 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C3002h
DPC
Software Start Setting Register 0
SOFTSTART 16
0
16
3 to 5 PCLKA
2, 3 ICLK
000C3006h
DPC
Software Start Setting Register 1
SOFTSTART 16
1
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C300Ah
DPC
Software Start Setting Register 2
SOFTSTART 16
2
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C300Eh
DPC
Software Start Setting Register 3
SOFTSTART 16
3
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C3012h
DPC
Reference Value Setting Register 0
VOTARGET
0
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C3016h
DPC
Reference Value Setting Register 1
VOTARGET
1
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C301Ah
DPC
Reference Value Setting Register 2
VOTARGET
2
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C301Eh
DPC
Reference Value Setting Register 3
VOTARGET
3
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C3022h
DPC
Reference Value Select Register
REFSEL
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C3026h
DPC
PWM Channel Setting Register
CHLSEL
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C302Ah
DPC
Control Enable Setting Register
ENABLE
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C302Eh
DPC
Control Calculation Parameter Setting
Register KP0
PARAMKP0
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C3032h
DPC
Control Calculation Parameter Setting
Register KI0
PARAMKI0
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C3036h
DPC
Control Calculation Parameter Setting
Register KQ0
PARAMKQ0
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C303Ah
DPC
Control Calculation Parameter Setting
Register KF0
PARAMKF0
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C303Eh
DPC
Control Calculation Parameter Setting
Register KP1
PARAMKP1
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C3042h
DPC
Control Calculation Parameter Setting
Register KI1
PARAMKI1
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C3046h
DPC
Control Calculation Parameter Setting
Register KQ1
PARAMKQ1
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C304Ah
DPC
Control Calculation Parameter Setting
Register KF1
PARAMKF1
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C304Eh
DPC
Control Calculation Parameter Setting
Register KP2
PARAMKP2
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C3052h
DPC
Control Calculation Parameter Setting
Register KI2
PARAMKI2
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
GTADTBRB
DPC
Not present in versions
with 64 or 48 pins.
Not present in versions
with 64 or 48 pins.
Page 100 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (47/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
DPC
Remarks
000C3056h
DPC
Control Calculation Parameter Setting
Register KQ2
PARAMKQ2
16
16
3 to 5 PCLKA
2, 3 ICLK
000C305Ah
DPC
Control Calculation Parameter Setting
Register KF2
PARAMKF2
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C305Eh
DPC
Control Calculation Parameter Setting
Register KP3
PARAMKP3
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C3062h
DPC
Control Calculation Parameter Setting
Register KI3
PARAMKI3
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C3066h
DPC
Control Calculation Parameter Setting
Register KQ3
PARAMKQ3
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C306Ah
DPC
Control Calculation Parameter Setting
Register KF3
PARAMKF3
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C306Ch
DPC
Control Calculation Result Higher-Order Bits RESULTU0
Store Register 0
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C306Eh
DPC
Control Calculation Result Lower-Order Bits RESULTL0
Store Register 0
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C3070h
DPC
Control Calculation Result Higher-Order Bits RESULTU1
Store Register 1
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C3072h
DPC
Control Calculation Result Lower-Order Bits RESULTL1
Store Register 1
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C3074h
DPC
Control Calculation Result Higher-Order Bits RESULTU2
Store Register 2
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C3076h
DPC
Control Calculation Result Lower-Order Bits RESULTL2
Store Register 2
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C3078h
DPC
Control Calculation Result Higher-Order Bits RESULTU3
Store Register 3
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C307Ah
DPC
Control Calculation Result Lower-Order Bits RESULTL3
Store Register 3
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C307Eh
DPC
Input Code Monitor Enable Register
TMONEN
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C3082h
DPC
Maximum Input Code Monitor Register 0
TMONMAX0 16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C3086h
DPC
Minimum Input Code Monitor Register 0
TMONMIN0
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C308Ah
DPC
Maximum Input Code Monitor Register 1
TMONMAX1 16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C308Eh
DPC
Minimum Input Code Monitor Register 1
TMONMIN1
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C3092h
DPC
Maximum Input Code Monitor Register 2
TMONMAX2 16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C3096h
DPC
Minimum Input Code Monitor Register 2
TMONMIN2
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C309Ah
DPC
Maximum Input Code Monitor Register 3
TMONMAX3 16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C309Eh
DPC
Minimum Input Code Monitor Register 3
TMONMIN3
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C30A2h
DPC
Overvoltage Output Error Judgment Thresh- ERRVTH0
old Setting Register 0
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C30A6h
DPC
Overvoltage Output Error Judgment Thresh- ERRVTH1
old Setting Register 1
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C30AAh DPC
Overvoltage Output Error Judgment Thresh- ERRVTH2
old Setting Register 2
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C30AEh DPC
Overvoltage Output Error Judgment Thresh- ERRVTH3
old Setting Register 3
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
000C30B2h
PWM Shut-Down at Overvoltage Output
Error Setting Register
ERRDWN
16
16
3 to 5 PCLKA
2, 3 ICLK
Not present in versions
with 64 or 48 pins.
007F C402h FLASH
Flash Mode Register
FMODR
8
8
2, 3 FCLK
2, 3 ICLK
007F C410h FLASH
Flash Access Status Register
FASTAT
8
8
2, 3 FCLK
2, 3 ICLK
007F C411h FLASH
Flash Access Error Interrupt Enable
Register
FAEINT
8
8
2, 3 FCLK
2, 3 ICLK
007F C412h FLASH
Flash Ready Interrupt Enable Register
FRDYIE
8
8
2, 3 FCLK
2, 3 ICLK
ROM
007F C440h FLASH
E2 DataFlash Read Enable Register 0
DFLRE0
16
16
2, 3 FCLK
2, 3 ICLK
E2 DataFlash
Memory
007F C442h FLASH
E2 DataFlash Read Enable Register 1
DFLRE1
16
16
2, 3 FCLK
2, 3 ICLK
007F C450h FLASH
E2 DataFlash P/E Enable Register 0
DFLWE0
16
16
2, 3 FCLK
2, 3 ICLK
007F C452h FLASH
E2 DataFlash P/E Enable Register 1
DFLWE1
16
16
2, 3 FCLK
2, 3 ICLK
DPC
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Not present in versions
with 64 or 48 pins.
ROM/
E2 DataFlash
Memory
Page 101 of 186
RX63T Group
Table 4.1
4. I/O Registers
List of I/O Registers (Address Order) (48/48)
Number of Access States
Address
Module
Symbol
Register Name
Register
Symbol
Number Access
of Bits Size
ICLK PCLK
ICLK PCLK
Module
Name
ROM
007F FFB0h FLASH
Flash Status Register 0
FSTATR0
8
8
2, 3 FCLK
2, 3 ICLK
007F FFB1h FLASH
Flash Status Register 1
FSTATR1
8
8
2, 3 FCLK
2, 3 ICLK
007F FFB2h FLASH
Flash P/E Mode Entry Register
FENTRYR
16
16
2, 3 FCLK
2, 3 ICLK
ROM/
E2 DataFlash
Memory
007F FFB4h FLASH
Flash Protection Register
FPROTR
16
16
2, 3 FCLK
2, 3 ICLK
ROM
007F FFB6h FLASH
Flash Reset Register
FRESETR
16
16
2, 3 FCLK
2, 3 ICLK
007F FFBAh FLASH
FCU Command Register
FCMDR
16
16
2, 3 FCLK
2, 3 ICLK
007F FFC8h FLASH
FCU Processing Switching Register
FCPSR
16
16
2, 3 FCLK
2, 3 ICLK
007F FFCAh FLASH
E2 DataFlash Blank Check Control Register DFLBCCNT
16
16
2, 3 FCLK
2, 3 ICLK
007F FFCCh FLASH
Flash P/E Status Register
FPESTAT
16
16
2, 3 FCLK
2, 3 ICLK
ROM
007F FFCEh FLASH
E2 DataFlash Blank Check Status Register
DFLBCSTAT 16
16
2, 3 FCLK
2, 3 ICLK
E2 DataFlash
Memory
007F FFE8h FLASH
Peripheral Clock Notification Register
PCKAR
16
2, 3 FCLK
2, 3 ICLK
ROM
Note:
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
16
Remarks
E2 DataFlash
Memory
• This table shows the maximum specifications of I/O registers. The I/O registers of individual products correspond to the list of functions given as Table 1.2. For details, refer
to Table 1.2, Comparison of Functions for Different Packages.
When the register is accessed while the USB is operating, a delay may be generated in accessing.
Odd addresses are not accessible in 16-bit units. Obtain 16-bit access to the two registers by access to the address of TMOCNTL.
Pins USB0 and RIIC1 are not present in 112-pin products.
Pins USB0, RIIC1, and SCI3 are not present in 100-pin products.
Pins GPT4 to GPT7, USB0, RSPI1, RIIC1, SCI2, SCI3, CAN1, AD, and S12AD1 are not present in 64- and 48-pin products.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 102 of 186
RX63T Group
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
5.
Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
5.1
Absolute Maximum Ratings
Table 5.1
Absolute Maximum Ratings
Conditions: VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
Item
Symbol
Value
Unit
Power supply voltage
VCC, PLLVCC
–0.3 to +6.5
V
USB power supply voltage
VCC_USB*1
–0.3 to +6.5
V
AVCC*2
Analog power supply voltage
AVCC0,
–0.3 to +6.5
V
Reference power supply voltage
VREFH0*2
–0.3 to AVCC0 + 0.3
V
VREF*2
–0.3 to AVCC0 + 0.3
V
Input voltage (except for ports 4 to 6, C,
USB0_DP, and USB0_DM)
Vin
–0.3 to VCC + 0.3
V
Input voltage (USB0_DP and USB0_DM)
Vin
–0.3 to VCC_USB + 0.3
V
Input voltage (port 4)
Vin
–0.3 to AVCC0 + 0.3
V
Input voltage (ports 5, 6, and C)
Vin
–0.3 to AVCC + 0.3
V
Analog input voltage (port 4)
VAN
–0.3 to AVCC0 + 0.3
V
Analog input voltage (ports 5, 6, and C)
VAN
–0.3 to AVCC + 0.3
V
Operating
temperature
D version product
Topr
–40 to +85
ºC
G version product
Topr
–40 to +105
ºC
Tstg
–55 to +125
ºC
Storage temperature
Caution: Permanent damage to the LSI may result if absolute maximum ratings are exceeded.
Note 1. When the USB is not in use, do not leave the VCC_USB and VSS_USB pins open.
Connect the VCC_USB pin to VCC, and the VSS_USB pin to VSS, respectively.
Note 2. When the A/D converter is not in use, do not leave the AVCC0, VREFH0, VREFL0, AVSS0, AVCC, VREF, and AVSS pins open.
• When the 12-bit A/D converter is not in use
Connect the AVCC0 pin to AVCC, the VREFH0 pin to VREF, and the AVSS0 and VREFL0 pins to AVSS, respectively.
• When the 10-bit A/D converter is not in use
Connect the AVCC pin to AVCC0, the VREF pin to VREFH0, and the AVSS pin to AVSS0, respectively.
• When the 12-bit A/D converter and 10-bit A/D converter are not in use
Connect the AVCC0, VREFH0, AVCC, and VREF pins to VCC, and the AVSS0, VREFL0, and AVSS pins to VSS, respectively.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 103 of 186
RX63T Group
5.2
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
DC Characteristics
Table 5.2
DC Characteristics (1)
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
The following relation applies when the USB is in use under condition 1 or condition 2: Vcc = PLLVcc = Vcc_USB = 3.0 to 3.6 V.
Ta = Topr. Ta is common to conditions 1 to 3.
Item
Schmitt trigger
input voltage
Input high voltage
(except for Schmitt
trigger input pin)
Input low voltage
(except for Schmitt
trigger input pin)
Symbol
Min.
Typ.
Max.
Unit
CAN input pin
IRQ input pin
MTU3 input pin
POE3 input pin
SCI input pin
A/D trigger input pin
GPT input pin
RES#, NMI
VIH
VCC × 0.8
—
VCC + 0.3
V
VIL
–0.3
—
VCC × 0.2
∆VT
VCC × 0.06
—
—
RIIC input pin (IICBus
operating)
VIH
VCC × 0.7
—
VCC + 0.3
VIL
–0.3
—
VCC × 0.3
∆VT
VCC × 0.05
—
—
USB0_VBUS input pin
VIH
VCC × 0.7
—
VCC + 0.3
VIL
–0.3
—
VCC × 0.2
∆VT
VCC × 0.06
—
—
Port 4*1
(also used as an analog
port)
VIH
AVCC0 × 0.8
—
AVCC0 + 0.3
VIL
–0.3
—
AVCC0 × 0.2
Ports 5, 6, and C*1
(also used as an analog
port)
VIH
AVCC × 0.8
—
AVCC + 0.3
VIL
–0.3
—
AVCC × 0.2
Ports 0 to 3*1
Ports 7 to B*1
Ports D to G*1
VIH
VCC × 0.8
—
VCC + 0.3
VIL
–0.3
—
VCC × 0.2
MD pin, EMLE
VIH
VCC × 0.9
—
VCC + 0.3
EXTAL, WAIT#, TCK
RSPI input pin
VCC × 0.8
—
VCC + 0.3
D0 to D15
VCC × 0.7
—
VCC + 0.3
RIIC input pin (SMBus
operating)
2.1
—
VCC + 0.3
–0.3
—
VCC × 0.1
–0.3
—
VCC × 0.2
MD pin, EMLE
EXTAL, WAIT#, TCK
RSPI input pin
VIL
D0 to D15
–0.3
—
VCC × 0.3
RIIC input pin (SMBus
operating)
–0.3
—
0.8
Test Conditions
V
Conditions 1 and 2
V
Conditions 1 and 2
Note 1. This includes the multiplexed pin functions, except for P25, P26, PB1, or PB2 when the RIIC input functions are in use, P22 to
P24, P30, PA3 to PA5, PB0, PD0 to PD2, or PD6 when the RSPI input functions are in use, and PD4 or PF3 when the TCK input
function is in use.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 104 of 186
RX63T Group
Table 5.3
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
DC Characteristics (2)
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
The following relation applies when the USB is in use under condition 1 or condition 2: Vcc = PLLVcc = Vcc_USB = 3.0 to 3.6 V.
Ta = Topr. Ta is common to conditions 1 to 3.
Item
Output high voltage
All output pins (except for
P52, P53, P60 to P65, P71
to P76, P90 to P95, and
USB0_DPUPE)
Symbol
VOH
Typ.
Max.
Unit
VCC – 0.5
—
—
P52, P53, and P60 to P65
AVCC – 0.5
—
—
USB0_DPUPE
VCC_USB –
0.5
P71 to P76, and P90 to P95
Output low voltage
Min.
V
Test Conditions
IOH = –1 mA
IOH = –1 mA
IOH = –1 mA
VCC – 1.0
—
—
—
—
0.5
P71 to P76, and P90 to P95
—
—
1.1
IOL = 15 mA
RIIC pins
—
—
0.4
IOL = 3 mA
All output pins (except for
P71 to P76, P90 to P95, and
RIIC pins)
VOL
IOH = –5 mA
V
IOL = 1.0 mA
IOL = 6 mA
—
—
0.6
Input leakage
current
RES#, MD pin, EMLE,
Port 4,
Ports P50, P51, P54 to P57,
and
Port C
Iin
—
—
1.0
μA
Vin = 0 V, Vin = VCC
Three-state
leakage current (off
state)
Port 0,
Port 1,
Ports P20 to P24,
Port 3,
Ports P52, P53,
Ports 6 to A,
Ports PB0, PB3 to PB7, and
Ports D to G
ITSI
—
—
1.0
μA
Vin = 0 V, Vin = VCC
—
—
5.0
—
—
15
pF
—
—
30
Vin = 0 V,
f = 1 MHz,
Ta = 25 ºC
Ports P25, P26, PB1, and
PB2
Input capacitance
All output pins (except for
P25, P26, PB1, and PB2)
Ports P25, P26, PB1, and
PB2
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Cin
Page 105 of 186
RX63T Group
Table 5.4
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
DC Characteristics (3)
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
The following relation applies when the USB is in use under condition 1 or condition 2: Vcc = PLLVcc = Vcc_USB = 3.0 to 3.6 V.
Ta = Topr. Ta is common to conditions 1 to 3.
Item
Supply current
*1
Min.
Typ.
Max.
Unit
—
—
70
mA
*4
—
40
—
Increased by BGO
operation *5
—
15
—
Sleep mode
40
55
All-module-clock-stop mode *6
20
30
During
operation
During
standby
Analog power
supply current
Symbol
Max. *2
Normal
ICC*3
Software standby mode
—
0.10
3
mA
Deep software standby
mode
—
20
60
μA
—
1.5
4.2
mA
Programmable gain amplifier (per channel)
—
1
1.5
mA
Window comparator (per channel)
—
0.5
0.7
mA
—
0.1
8
μA
—
0.9
1.4
mA
0.1
4
μA
0.1
4
μA
During 12-bit A/D conversion (per unit)
AICC0
Waiting for 12-bit A/D conversion (all units)
During 10-bit A/D conversion (per channel)
AICC
During D/A conversion (per unit)
Waiting for 10-bit A/D, D/A conversion (all
units)
Reference
power supply
current
During 12-bit A/D conversion (per unit)
—
AIREFH0
Waiting for 12-bit A/D conversion (all units)
During 10-bit A/D conversion (per channel)
AIREF
—
1.6
2.5
mA
—
0.1
1.5
μA
—
0.2
0.3
mA
1
1.5
mA
—
0.1
1.2
μA
—
—
20
ms/
V
During D/A conversion (per unit)
Waiting for 10-bit A/D, D/A conversion (all
units)
VCC rising gradient
SVCC
Test Conditions
ICLK = 100 MHz
PCLKA = 100 MHz
PCLKB = 50 MHz
PCLKC = 100 MHz
PCLKD = 50 MHz
FCLK = 50 MHz
Note 1. Supply current values are with all output pins unloaded.
Note 2. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation.
Note 3. ICC depends on f (ICLK) as follows. (ICLK: PCLK = 8:4)
ICC max = 0.6 × f + 10 (max)
ICC typ = 0.3 × f + 10 (normal)
ICC max = 0.45 × f + 10 (sleep mode)
Note 4. Measured with clocks not supplied to the peripheral functions. This does not include the BGO operation.
Note 5. Incremented if data is written to or erased from the on-chip ROM or on-chip data-flash memory for data storage during the
program execution.
Note 6. The values are for reference.
R01DS0087EJ0220 Rev.2.20
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Page 106 of 186
RX63T Group
Table 5.5
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
Permissible Output Currents
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
The following relation applies when the USB is in use under condition 1 or condition 2: Vcc = PLLVcc = Vcc_USB = 3.0 to 3.6 V.
Ta = Topr. Ta is common to conditions 1 to 3.
Item
Symbol
Min.
Typ.
Max.
Unit
All output pins (except
for P71 to P76, P90 to
P95, and RIIC pins)*1
IOL
—
—
2.0
mA
RIIC pins
IOL
—
—
6.0
mA
P71 to P76, and P90 to
P95*2
IOL
—
—
15.0
mA
All output pins (except
for P71 to P76, P90 to
P95, and RIIC pins)*1
IOL
—
—
4.0
mA
RIIC pins
IOL
—
—
6.0
mA
P71 to P76, and P90 to
P95*2
IOL
—
—
15.0
mA
Permissible output low current (total)
Total of output pins
ΣIOL
—
—
110
mA
Permissible output high current (average
value per pin)
All output pins (except
for P71 to P76, P90 to
P95, and
USB0_DPUPE pin)*1
–IOH
—
—
2.0
mA
USB0_DPUPE pin
–IOH
—
—
3.0
mA
P71 to P76, and P90 to
P95*2
–IOH
—
—
5.0
mA
All output pins (except
for P71 to P76, P90 to
P95)*1
–IOH
—
—
4.0
mA
P71 to P76, and P90 to
P95*2
–IOH
—
—
5.0
mA
Σ–IOH
—
—
35
mA
Permissible output low current (average
value per pin)
Permissible output low current (max.
value per pin)
Permissible output high current (max.
value per pin)
Permissible output high current (total)
Note 1. USB0_DP and USB0_DM are not included.
Note 2. For pins P71 to P76 and P90 to P95, IOL = 15 mA (max.) and –IOH = 5 mA (max.). However, if several of the pins are to supply
IOL and –IOH of more than 2.0 mA at the same time, the number of pins should be six or less.
Caution: To protect the MCU’s reliability, the output current values should not exceed the values in this table.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 107 of 186
RX63T Group
Table 5.6
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
Permissible Power Consumption (G version product only)
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 3.0 to 3.6V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC
Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0V
AVCC0 = AVCC = 4.0 to 5.5V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Ta = -40 to +105°C. Ta is common to conditions 1 to 3.
Item
Total permissible power
consumption*1
Symbol
Typ.
Max.
Unit
Test Conditions
Pd
—
345
mW
85°C < Ta ≤ 105°C
Note: • Please contact Renesas Electronics sales office for derating of operation under Ta = +85°C to +105°C. Derating is the
systematic reduction of load for the sake of improved reliability.
Note 1. The total power consumption of the whole chip including output current.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 108 of 186
RX63T Group
5.3
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
AC Characteristics
Table 5.7
Operation Frequency Value
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS =PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Ta = Topr. Ta is common to conditions 1 to 3.
Item
Operation
frequency
System clock (ICLK)
Symbol
Min.
Typ.
Max.
Unit
f
MHz
—
—
100
Peripheral module clock (PCLK) *1
—
—
50
Timer module clock (PCLKA)
—
—
100
AD clock (PCLKC)
—
—
100
S12AD clock (PCLKD)
—
—
50
FlashIF clock (FCLK)
—
—
50
External bus clock (BCLK)
—
—
50
BCLK pin output
—
—
25
USB clock (UCLK)
—
—
48
Note 1. The PCLK must run at a frequency of at least 24 MHz when the USB is in use.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 109 of 186
RX63T Group
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
5.3.1
Reset Timing
Table 5.8
Reset Timing
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Ta = Topr. Ta is common to conditions 1 to 3.
Item
RES# pulse
width
Symbol
Min.
Typ.
Max.
Power-on
tRESWP
2
—
—
Deep software standby mode
tRESWD
1
—
Software standby mode
tRESWS
1
—
Programming or erasure of the ROM or E2
DataFlash memory or blank checking of the E2
DataFlash memory
tRESWF
200
—
Unit
ms
Figure 5.1
—
ms
Figure 5.2
—
ms
—
μs
tRESW
200
—
—
μs
Wait time after RES# cancellation
tRESWT
59
—
60
tcyc
Internal reset time (independent watchdog timer reset, watchdog
timer reset, software reset)
tRESW2
112
—
120
tcyc
Other than above
Test
Conditions
VCC
RES#
tRESWP
Internal reset
tRESWT
Figure 5.1
Reset Input Timing at Power-On
tRESWD, tRESWS, tRESW
RES#
Internal reset
tRESWT
Figure 5.2
Reset Input Timing
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Mar 31, 2016
Page 110 of 186
RX63T Group
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
5.3.2
Clock Timing
Table 5.9
Clock Timing
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Ta = Topr. Ta is common to conditions 1 to 3.
Item
Symbol
BCLK pin output cycle time
Min.
Typ.
Max.
Unit
Test
Conditions
Figure 5.3
Only condition 3
tBcyc
20
—
—
ns
Other than condition 3
tBcyc
40
—
—
ns
BCLK pin output high pulse width
tCH
5
—
—
ns
BCLK pin output low pulse width
tCL
5
—
—
ns
BCLK pin output rising time
tCr
—
—
5
ns
BCLK pin output falling time
tCf
—
—
5
ns
tEXcyc
70
—
—
ns
EXTAL external clock input high pulse width
tEXH
35
—
—
ns
EXTAL external clock input low pulse width
tEXL
35
—
—
ns
EXTAL external clock rising time
tEXr
—
—
5
ns
EXTAL external clock input cycle time
EXTAL external clock falling time
tEXf
—
—
5
ns
EXTAL external clock input wait time*1
tEXWT
1
—
—
ms
Main clock oscillator oscillation frequency
fMAIN
8
—
12.5
MHz
ms
ms
Main clock oscillation stabilization time (crystal)
Main clock oscillation stabilization wait time (crystal)
LOCO, IWDTCLK clock cycle time
LOCO, IWDTCLK clock oscillation frequency
LOCO, IWDTCLK clock oscillation stabilization wait time
PLL clock frequency
PLL clock oscillation stabilization time
PLL clock oscillation stabilization wait
time
PLL clock oscillation stabilization time
PLL clock oscillation stabilization wait
time
PLL operation started
after main clock
oscillation has settled
PLL operation started
before main clock
oscillation has settled
tMAINOSC
—
—
*2
tMAINOSCWT
—
—
*3
tLOCOCYC
6.96
8
9.4
μs
fLOCO
106.25
125
143.75
kHz
tLOCOWT
—
—
20
μs
fPLL
104
—
200
MHz
tPLL1
—
—
500
μs
tPLLWT1
—
—
*4
ms
tPLL2
—
—
tMAINOSC
+ tPLL1
ms
tPLLWT2
—
—
*4
ms
Figure 5.4
Figure 5.5
Figure 5.6
Figure 5.7
Figure 5.8
Note 1. This is the time until the clock is used after clearing the main clock oscillator stop bit (MOSCCR.MOSTP) to 0 (selecting
operation).
Note 2. When using a main clock, ask the manufacturer of the oscillator to evaluate its oscillation. Refer to the results of evaluation
provided by the manufacturer for the oscillation stabilization time.
Note 3. This is calculated from the formula below, where n is the number of cycles set by the MOSCWTCR.MSTS[4:0] bits.
tMAINOSCWT = tMAINOSC +
n +16384
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
fMAIN
Page 111 of 186
RX63T Group
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
Note 4. This is calculated from the formula below, where n is the number of cycles set by the PLLWTCR.PSTS[4:0] bits.
tPLLWT1 = tPLL1 +
tPLLWT2 = tPLL2 +
n +131072
fPLL
n +131072
fPLL
= tMAINOSC + tPLL1 +
n +131072
fPLL
tBcyc, tSDcyc
tCH
tCf
BCLK pin output
tCL
tCr
Test conditions: VOH = VCC × 0.7, VOL = VCC × 0.3, IOH = –1.0 mA, IOL = 1.0 mA, C = 30 pF
Figure 5.3
BCLK Pin Output Timing
tEXcyc
tEXL
tEXH
EXTAL external clock input
VCC × 0.5
tEXr
Figure 5.4
tEXf
EXTAL External Clock Input Timing
MOSCCR.MOSTP
tMAINOSC
Main clock oscillation output
tMAINOSCWT
Main clock
Figure 5.5
Main Clock Oscillation Start Timing
LOCOCR.LCSTP,
ILOCOCR.ILCSTP
tLOCOWT
LOCO, IWDTCLK
clock
Figure 5.6
LOCO, IWDTCLK Clock Oscillation Start Timing
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RX63T Group
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
MOSCCR.MOSTP
tMAINOSC
Main clock oscillation output
PLLCR2.PLLEN
tPLL1
PLL circuit output
tPLLWT1
PLL clock
Figure 5.7
PLL Clock Oscillation Start Timing (PLL is Operated after Main Clock Oscillation Has
Settled)
MOSCCR.MOSTP
tMAINOSC
Main clock oscillation output
PLLCR2.PLLEN
tPLL2
PLL circuit output
tPLLWT2
PLL clock
Figure 5.8
PLL Clock Oscillation Start Timing (PLL is Operated before Main Clock Oscillation Has
Settled)
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Mar 31, 2016
Page 113 of 186
RX63T Group
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
5.3.3
Timing of Recovery from Low Power Consumption Modes
Table 5.10
Timing of Recovery from Low Power Consumption Modes
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Ta = Topr. Ta is common to conditions 1 to 3.
Item
Recovery time
after
cancellation of
software
standby mode
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
Figure 5.9
Crystal resonator
connected to
main clock
oscillator
Main clock oscillator
operating
tSBYMC
10
—
—
ms
Main clock oscillator and
PLL circuit operating
tSBYPC
10
—
—
ms
External clock
input to main
clock oscillator
Main clock oscillator
operating
tSBYEX
1
—
—
ms
Main clock oscillator and
PLL circuit operating
tSBYPE
1
—
—
ms
—
—
800
µs
Low-speed clock oscillator or IWDT-specific low- tSBYLO
speed clock oscillator operating
Recovery time after cancellation of deep software standby mode
tDSBY
—
—
1
ms
Wait time after cancellation of deep software standby mode
tDSBYWT
45
—
46
tcyc
Figure 5.10
Note: • The wait time varies depending on the state in which each oscillator was when the WAIT instruction was executed. The recovery
time when multiple oscillators are operating is the same period as that when the oscillator, which takes the longest time for
recovery among the operating oscillators, is operating alone.
Oscillator
ICLK
IRQ
Software standby mode
tSBYMC, tSBYPC, tSBYEX, tSBYPE,
tSBYSC, tSBYHO, tSBYLO
Figure 5.9
Software Standby Mode Cancellation Timing
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RX63T Group
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
Oscillator
IRQ
Deep software
standby reset
Internal reset
Deep software standby mode
tDSBY
tDSBYWT
Reset exception handling start
Figure 5.10
Deep Software Standby Mode Cancellation Timing
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Mar 31, 2016
Page 115 of 186
RX63T Group
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
5.3.4
Control Signal Timing
Table 5.11
Control Signal Timing
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Ta = Topr. Ta is common to conditions 1 to 3.
Item
Symbol
Min.
Typ.
NMI pulse width
tNMIW
200
IRQ pulse width
tIRQW
Max.
Unit
Test Conditions
—
—
ns
tc(PCLK) × 2 ≤ 200 ns, Figure 5.11
tc(PCLK) × 2 —
—
ns
tc(PCLK) > 200 ns, Figure 5.11
200
—
—
ns
tc(PCLK) ≤ 200 ns, Figure 5.12
tc(PCLK) × 2 —
—
ns
tc(PCLK) > 200 ns, Figure 5.12
NMI
tNMIW
Figure 5.11
NMI Interrupt Input Timing
IRQ
tIRQW
Figure 5.12
IRQ Interrupt Input Timing
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RX63T Group
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
5.3.5
Bus Timing
Table 5.12
Bus Timing (1)
Condition: VCC = PLLVCC = VCC_USB = AVCC0 = AVCC = 3.0 to 3.6 V,
VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC
Ta = Topr
Output load conditions: VOH = VCC x 0.5, VOL = VCC x 0.5, IOH = –1.0 mA, IOL = 1.0 mA, C = 30 pF
Item
Symbol
Min.
Max.
Unit
Test Conditions
Address delay time
tAD
—
30
ns
Byte control delay time
tBCD
—
30
ns
Figure 5.13 to
Figure 5.16
CS# delay time
tCSD
—
30
ns
RD# delay time
tRSD
—
30
ns
Read data setup time
tRDS
20
—
ns
Read data hold time
tRDH
0
—
ns
WR# delay time
tWRD
—
30
ns
Write data delay time
tWDD
—
35
ns
Write data hold time
tWDH
0
—
ns
WAIT# setup time
tWTS
20
—
ns
WAIT# hold time
tWTH
0
—
ns
Table 5.13
Figure 5.17
Bus Timing (2)
Condition: VCC = PLLVCC = AVCC0 = AVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V,
VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Ta = Topr
Output load conditions: VOH = VCC x 0.5, VOL = VCC x 0.5, IOH = –1.0 mA, IOL = 1.0 mA, C = 30 pF
Item
Symbol
Min.
Max.
Unit
Test Conditions
Figure 5.13 to
Figure 5.16
Address delay time
tAD
—
15
ns
Byte control delay time
tBCD
—
15
ns
CS# delay time
tCSD
—
15
ns
RD# delay time
tRSD
—
15
ns
Read data setup time
tRDS
15
—
ns
Read data hold time
tRDH
0
—
ns
WR# delay time
tWRD
—
15
ns
Write data delay time
tWDD
—
15
ns
Write data hold time
tWDH
0
—
ns
WAIT# setup time
tWTS
15
—
ns
WAIT# hold time
tWTH
0
—
ns
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Figure 5.17
Page 117 of 186
RX63T Group
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
CSRWAIT:2
RDON:1
CSROFF:1
CSON:0
TW1
TW2
Tend
Tn1
Th
BCLK
Byte write strobe mode
tAD
tAD
tAD
tAD
A19 to A0
1-write strobe mode
A19 to A1
tBCD
tBCD
tCSD
tCSD
BC1#, BC0#
Common to both byte write strobe
mode and 1-write strobe mode
CS3# to CS0#
tRSD
tRSD
RD# (Read)
tRDS
tRDH
D15 to D0 (Read)
Figure 5.13
External Bus Timing/Normal Read Cycle (Bus Clock Synchronized)
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Mar 31, 2016
Page 118 of 186
RX63T Group
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
CSWWAIT:2
WRON:1
WDON:1*1
CSWOFF:1
WDOFF:1*1
CSON:0
TW1
TW2
Tend
Tn1
Th
BCLK
Byte write strobe mode
tAD
tAD
tAD
tAD
A19 to A0
1-write strobe mode
A19 to A1
tBCD
tBCD
tCSD
tCSD
BC1#, BC0#
Common to both byte write strobe
mode and 1-write strobe mode
CS3# to CS0#
tWRD
tWRD
WR1#, WR0#, WR# (Write)
tWDD
tWDH
D15 to D0 (Write)
Note1. Be sure to specify WDON and WDOFF as at least one cycle of BCLK.
Figure 5.14
External Bus Timing/Normal Write Cycle (Bus Clock Synchronized)
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Mar 31, 2016
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RX63T Group
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
CSPRWAIT:3
CSRWAIT:3
CSON:0
CSPRWAIT:3
RDON:1
RDON:1
TW1
TW2
Tend
TW3
CSROFF:2
RDON:1
Tpw1
Tpw2
Tpw3
Tend
Tpw1
Tpw2
Tpw3
Tend
Tn1
Tn2
BCLK
Byte write strobe mode
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tAD
A19 to A0
1-write strobe mode
A19 to A1
tBCD
tBCD
tCSD
tCSD
BC1#, BC0#
Common to both byte write strobe
mode and 1-write strobe mode
CS3# to CS0#
tRSD
tRSD
tRSD
tRSD
tRSD
tRSD
RD# (Read)
tRDS
tRDH
tRDS
tRDH
tRDS
tRDH
D15 to D0 (Read)
Figure 5.15
External Bus Timing/Page Read Cycle (Bus Clock Synchronized)
CSPWWAIT:2
CSWWAIT:2
WRON:1
WDON:1*1
WDOFF:1*1
CSON:0 TW1
TW2
Tend
Tdw1
WRON:1
WDON:1*1
Tpw1
CSPWWAIT:2
WDOFF:1*1
Tpw2
Tend
Tdw1
WRON:1
WDON:1*1
Tpw1
CSWOFF:1
WDOFF:1*1
Tpw2
Tend
Tn1
Th
BCLK
Byte write strobe mode
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tAD
A19 to A0
1-write strobe mode
A19 to A1
tBCD
tBCD
tCSD
tCSD
BC1#, BC0#
Common to both byte write strobe
mode and 1-write strobe mode
CS3# to CS0#
tWRD
tWRD
tWRD
tWRD
tWRD
tWRD
WR1#, WR0#, WR# (Write)
tWDD
tWDH
tWDD
tWDH
tWDD
tWDH
D15 to D0 (Write)
Note 1. Be sure to specify WDON and WDOFF as at least one cycle of BCLK.
Figure 5.16
External Bus Timing/Page Write Cycle (Bus Clock Synchronized)
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 120 of 186
RX63T Group
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
CSRWAIT:3
CSWWAIT:3
TW1
TW2
TW3
(Tend)
Tend
Tn1
Th
BCLK
A19 to A0
CS3# to CS0#
RD# (Read)
WR# (Write)
External wait
tWTS tWTH
tWTS tWTH
WAIT#
Figure 5.17
Table 5.14
External Bus Timing/External Wait Control
Bus Timing (Multiplexed Bus) (3)
Condition: PLLVCC = VCC_USB = AVCC0 = AVCC = VREF = 3.0 to 3.6 V
VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V, VREFH0 = 3.0 V to AVCC0
Ta = Topr
Output load conditions: VOH = VCC x 0.5, VOL = VCC x 0.5, IOH = –1.0 mA, IOL = 1.0 mA, C = 30 pF
Item
Symbol
Min.
Max.
Unit
Test Conditions
Address delay time
tAD
—
35
ns
Byte control delay time
tBCD
—
30
ns
Figure 5.18, Figure
5.19
CS# delay time
tCSD
—
30
ns
RD# delay time
tRSD
—
30
ns
ALE delay time
tALED
—
30
ns
Read data setup time
tRDS
20
—
ns
Read data hold time
tRDH
0
—
ns
WR# delay time
tWRD
—
30
ns
Write data delay time
tWDD
—
35
ns
Write data hold time
tWDH
0
—
ns
WAIT# setup time
tWTS
20
—
ns
WAIT# hold time
tWTH
0.0
—
ns
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Figure 5.17
Page 121 of 186
RX63T Group
Table 5.15
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
Bus Timing (Multiplexed Bus) (4)
Condition: VCC = PLLVCC = AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V
VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V, VREFH0 = 4.0 V to AVCC0
Ta = Topr
Output load conditions: VOH = VCC x 0.5, VOL = VCC x 0.5, IOH = –1.0 mA, IOL = 1.0 mA, C = 30 pF
Item
Symbol
Min.
Max.
Unit
Test Conditions
Address delay time
tAD
—
15
ns
Byte control delay time
tBCD
—
15
ns
Figure 5.18, Figure
5.19
CS# delay time
tCSD
—
15
ns
RD# delay time
tRSD
—
15
ns
ALE delay time
tALED
—
15
ns
Read data setup time
tRDS
15
—
ns
Read data hold time
tRDH
0
—
ns
WR# delay time
tWRD
—
15
ns
Write data delay time
tWDD
—
15
ns
Write data hold time
tWDH
0
—
ns
WAIT# setup time
tWTS
15
—
ns
WAIT# hold time
tWTH
0.0
—
ns
Figure 5.17
Data cycle
Address cycle
Ta1
Ta1
Tan
TW1
TW2
TW3
TW4
TW5
Tend
Tn1
Tn2
BCLK
tAD
Address bus
tAD
tRDS
tAD
tRDH
Address/data bus
(A15/D15 to A0/D0)
tALED
tALED
Address latch
(ALE)
tRSD
tRSD
Data read
(RD#)
Chip select
(CS3# to CS0#)
Figure 5.18
tCSD
tCSD
Example of External Bus Timing/Read Access Operation (Multiplexed)
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Mar 31, 2016
Page 122 of 186
RX63T Group
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
Data cycle
Address cycle
Ta1
Ta1
Tan
TW1
TW2
TW3
TW4
TW5
Tend
Tn1
Tn2
Tn3
BCLK
tAD
Address bus
Address/data
bus
(A15/D15 to
A0/D0)
tAD
tAD
tALED
tWDD
tWDH
tALED
Address latch
(ALE)
tWRD
tWRD
Data write
(WRm#)
tCSD
Chip select
(CS3# to CS0#)
Figure 5.19
tCSD
Example of External Bus Timing/Write Access Operation (Multiplexed)
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 123 of 186
RX63T Group
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
5.3.6
Timing of On-Chip Peripheral Modules
Table 5.16
Timing of On-Chip Peripheral Modules (1)
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Ta = Topr. Ta is common to conditions 1 to 3.
Item
I/O ports
Input data pulse width
MTU3
Input capture input pulse
width
Single-edge setting
Min.
Max.
Single-edge setting
Both-edge setting
POE3
POE# input pulse width
GPT
Input capture input pulse
width
Single-edge setting
1.5
—
tPcyc
Figure 5.22
3
—
tPAcyc
Figure 5.23
5
—
tTICTF
—
0.1
μs/V
tTCKWH,
tTCKWL
3
—
tPAcyc
5
—
5
—
tTCKTF
—
0.1
tPOEW
1.5
—
tPcyc
Figure 5.28
tGTICW
3
—
tPAcyc
Figure 5.26
5
—
tGTICTF
—
0.1
μs/V
tOTETW
3
—
tPAcyc
5
—
—
0.1
Both-edge setting
Input capture input fall time
External trigger input pulse
width
External trigger input fall time
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Single-edge setting
Test Conditions
tPRW
Phase counting
mode
Timer clock input fall time
Unit*1
tTICW
Both-edge setting
Input capture input fall time
Timer clock pulse width
Symbol
Both-edge setting
tGTETRGTF
When Input capture at rising
edge, or Input capture
at both edges is selected.
Figure 5.25
μs/V
μs/V
When Input capture at rising
edge, or Input capture
at both edges is selected.
When Count operation is
started at rising edge, or
Count operation is started at
both edges is selected.
When Count operation is
stopped at rising edge, or
Count operation is stopped
at both edges is selected.
When Counter is cleared at
rising edge, or Counter is
cleared at both edges is
selected.
Figure 5.27
When Count operation is
started at rising edge, or
Count operation is started at
both edges is selected.
When Count operation is
stopped at rising edge, or
Count operation is stopped
at both edges is selected.
When Counter is cleared at
rising edge, or Counter is
cleared at both edges is
selected.
Page 124 of 186
RX63T Group
Table 5.16
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
Timing of On-Chip Peripheral Modules (2)
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Ta = Topr. Ta is common to conditions 1 to 3.
Item
SCI
Input clock cycle
Asynchronous
Symbol
Min.
Max.
Unit*1
Test Conditions
tScyc
4
—
tPcyc
6
—
C = 30 pF
Figure 5.29
Clock synchronous
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
—
20
ns
Input clock fall time
tSCKf
—
20
ns
tScyc
16
—
tPcyc
4
—
Output clock cycle
Asynchronous
Clock synchronous
Output clock pulse width
tSCKW
0.4
0.6
tScyc
Output clock rise time
tSCKr
—
20
ns
Output clock fall time
tSCKf
—
20
ns
Clock synchronous
tTXD
—
40
ns
Receive data setup time
Clock synchronous
tRXS
40
—
ns
Receive data hold time
Clock synchronous
tRXH
40
—
ns
Receive data fall time
tTICTF
—
0.1
μs/V
When Noise Cancellation
Function is not used.
A/D
converter
10-bit A/D converter trigger input pulse width
tTRGW
1.5
—
tPcyc
Figure 5.31
1.5
—
CAC
CACREF input pulse width
4.5 tcac +
3 tPcyc
—
ns
5 tcac +
6.5 tPcyc
—
ns
—
0.1
μs/V
Transmit data delay time
12-bit A/D converter trigger input pulse width
tPcyc ≤ tcac*2
tCACREF
tPcyc > tcac*2
CACREF input fall time
tCACREFTF
Figure 5.30
Note 1. tPcyc: PCLK cycle, tPAcye: PCLKA cycle
Note 2. tcac: CAC count clock source cycle.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 125 of 186
RX63T Group
Table 5.16
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
Timing of On-Chip Peripheral Modules (3)
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS =PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Ta = Topr. Ta is common to conditions 1 to 3.
High drive output is selected by the drive capacity control register.
Item
RSPI
Symbol
RSPCK clock
cycle
Master
RSPCK clock
high pulse width
Master
tSPcyc
Slave
tSPCKWH
Slave
RSPCK clock low
pulse width
Master
tSPCKWL
Slave
Min.
Max.
Unit*1
Test Conditions
tPcyc
C = 30 pF,
Figure 5.32
2
4096
8
4096
(tSPcyc – tSPCKR
– tSPCKF) / 2 – 3
—
(tSPcyc – tSPCKR
– tSPCKF) / 2
—
(tSPcyc – tSPCKR
– tSPCKF) / 2 – 3
—
(tSPcyc – tSPCKR
– tSPCKF) / 2
—
ns
ns
RSPCK clock
rise/fall time
Output
tSPCKR,
tSPCKF
—
5
Input
—
1
μs
RSPCK clock
fall time
Input
tSPCKF
—
0.1
μs/V
Data input setup
time
Master
tSU
4
—
ns
20 – tPcyc
—
Data input hold
time
Master
tPcyc
—
tHF
0
—
Slave
tH
20 + 2 × tPcyc
—
Master
tLEAD
1
8
tSPcyc
4
—
tPcyc
tSPcyc
Slave
tH
PCLKB
division ratio
set to a value
other than 1/2
PCLKB
division ratio
set to 1/2
SSL setup time
Slave
SSL hold time
Master
tLAG
Slave
Data output delay
time
Data output hold
time
Successive
transmission
delay time
Master
tOD
Slave
Master
tOH
Slave
Master
tTD
Slave
MOSI and MISO
rise/fall time
Output
SSL rise/fall time
Output
tDR, tDF
Input
ns
ns
1
8
4
—
tPcyc
—
10
ns
—
3 × tPcyc + 40
0
—
0
—
ns
tSPcyc + 2 × tPcyc
8 × tSPcyc+ 2 × tPcyc
4 × tPcyc
—
ns
—
5
ns
—
1
μs
tSSLr,
tSSLf
—
15
ns
—
1
μs
Slave access time
tSA
—
4
tPcyc
Slave output release time
tREL
—
3
tPcyc
Input
C = 30 pF,
Figure 5.33 to
Figure 5.40
Figure 5.39
and Figure
5.40
Note 1. tPcyc: PCLK cycle
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 126 of 186
RX63T Group
Table 5.16
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
Timing of On-Chip Peripheral Modules (4)
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Ta = Topr. Ta is common to conditions 1 to 3.
Item
Simple
SPI
SCK clock cycle output (master)
Symbol
Min.
Max.
Unit*1
Test Conditions
tSPcyc
4
65536
tPcyc
C = 30 pF,
Figure 5.30
SCK clock cycle input (slave)
8
65536
SCK clock high pulse width
tSPCKWH
0.4
0.6
tSPcyc
SCK clock low pulse width
tSPCKWL
0.4
0.6
tSPcyc
SCK clock rise/fall time
tSPCKR, tSPCKF
—
20
ns
Data input setup time
tSU
40
—
ns
Data input hold time
tH
40
—
ns
SS input setup time
tLEAD
6
—
tPcyc
SS input hold time
tLAG
6
—
tPcyc
Data output delay time
tOD
—
40
ns
Data output hold time
tOH
–10
—
ns
Data rise/fall time
tDR, tDF
—
20
ns
SS input rise/fall time
tSSLr, tSSLf
—
20
ns
Slave access time
tSA
—
5
tPcyc
Slave output release time
tREL
—
5
tPcyc
C = 30 pF,
Figure 5.31 to
Figure 5.38
C = 30 pF,
Figure 5.37 and
Figure 5.38
Note 1. tPcyc: PCLK cycle
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 127 of 186
RX63T Group
Table 5.16
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
Timing of On-Chip Peripheral Modules (5)
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Ta = Topr. Ta is common to conditions 1 to 3.
Item
RIIC
(Standard-mode)
RIIC
(Fast-mode)
Symbol
Min.*1,*2
Max.
Unit
Test
Conditions
Figure 5.36
SCL input cycle time
tSCL
6(12) × tIICcyc + 1300
—
ns
SCL input high pulse width
tSCLH
3(6) × tIICcyc + 300
—
ns
SCL input low pulse width
tSCLL
3(6) × tIICcyc + 300
—
ns
SCL, SDA input rise time
tSr
—
1000
ns
SCL, SDA input fall time
tSf
—
300
ns
SCL, SDA input spike pulse removal time
tSP
0
1(4) × tIICcyc
ns
SDA input bus free time
tBUF
3(6) × tIICcyc + 300
—
ns
Start condition input hold time
tSTAH
tIICcyc + 300
—
ns
Restart condition input setup time
tSTAS
1000
—
ns
Stop condition input setup time
tSTOS
1000
—
ns
Data input setup time
tSDAS
tIICcyc + 50
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb
—
400
pF
SCL input cycle time
tSCL
6(12) × tIICcyc + 600
—
ns
SCL input high pulse width
tSCLH
3(6) × tIICcyc + 300
—
ns
SCL input low pulse width
tSCLL
3(6) × tIICcyc + 300
—
ns
SCL, SDA input rise time
tSr
20 + 0.1Cb
300
ns
SCL, SDA input fall time
tSf
20 + 0.1Cb
300
ns
SCL, SDA input spike pulse removal time
tSP
0
1(4) × tIICcyc
ns
SDA input bus free time
tBUF
3(6) × tIICcyc + 300
—
ns
Start condition input hold time
tSTAH
tIICcyc + 300
—
ns
Restart condition input setup time
tSTAS
300
—
ns
Stop condition input setup time
tSTOS
300
—
ns
Data input setup time
tSDAS
tIICcyc + 50
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb
—
400
pF
Note: • tIICcyc: RIIC internal reference clock (IIC) cycle
Note 1. The value within parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 11b while the digital filter is enabled by
the setting ICFER.NFE = 1.
Note 2. Cb is the total capacitance of the bus lines.
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RX63T Group
Table 5.16
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
Timing of On-Chip Peripheral Modules (6)
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Ta = Topr. Ta is common to conditions 1 to 3.
Symbol
Min.*1, *2
Max.
Unit
Test Conditions
SCL, SDA input rise time
tSr
—
1000
ns
Figure 5.36
Item
Simple IIC
(Standard-mode)
Simple IIC
(Fast-mode)
SCL, SDA input fall time
tSf
—
300
ns
SCL, SDA input spike pulse removal time
tSP
0
4 × tPcyc
ns
Data input setup time
tSDAS
250
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb
—
400
pF
SCL, SDA input rise time
tSr
20 + 0.1Cb
300
ns
SCL, SDA input fall time
tSf
20 + 0.1Cb
300
ns
SCL, SDA input spike pulse removal time
tSP
0
4 × tPcyc
ns
Data input setup time
tSDAS
100
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb
—
400
pF
Note 1. The value in parentheses is used when ICMR3.NF[1:0] are set to 11b while a digital filter is enabled with ICFER.NFE = 1.
Note 2. Cb indicates the total capacity of the bus line.
Note 3. tPcyc: PCLK cycle
5.3.7
Timing of PWM Delay Generation Circuit
Table 5.17
Timing of the PWM Delay Generation Circuit
Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC
Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Ta = Topr. Ta is common to conditions 1 to 3.
Item
Symbol
Typ.
Max.
Unit
Test Conditions
Resolution
—
312.5
—
ps
PCLKA = 100 MHz
DNL*1
—
2.0
—
LSB
Note 1. This value is correct when the difference between each code and the next is a resolution of one bit (1 LSB).
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RX63T Group
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
PCLK
Port
tPRW
Figure 5.20
I/O port Input Timing
PCLKA
Input capture
input
Figure 5.21
tTICW
MTU3 Input/Output Timing
PCLKA
MTCLKA to
MTCLKD
tTCKWL
Figure 5.22
tTCKWH
MTU3 Clock Input Timing
PCLKA
Input capture
input
Figure 5.23
tGTICW
GPT Input Capture Input Timing
PCLKA
External trigger input
tGTEW
Figure 5.24
GPT External Trigger Input Timing
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RX63T Group
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
PCLK
POEn# input
tPOEW
Figure 5.25
POE3# Input Timing
tSCKW
tSCKr
tSCKf
SCKn
(n = 0 to 3, 12)
tScyc
Figure 5.26
SCK Clock Input Timing
SCKn
tTXD
TxDn
tRXS tRXH
RxDn
n = 0 to 3, 12
Figure 5.27
SCI Input/Output Timing: Clock Synchronous Mode
PCLK
ADTRG#
ADTRG0#
ADTRG1#
tTRGW
Figure 5.28
AD Converter External Trigger Input Timing
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RX63T Group
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
tSPCKr
tSPCKWH
RSPI
Simple SPI
RSPCKm
Master select
output
SCKn
Master select
output
VOH
VOH
tSPCKf
VOH
VOH
VOL
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
RSPCKm
Slave select
input
SCKn
Slave select
input
(m = A, B)
(n = 0 to 3, 12)
VIH
VIH
tSPCKf
VIH
VIL
VIL
tSPCKWL
VIH
VIL
tSPcyc
VOH = 0.7 x VCC, VOL = 0.3 x VCC, VIH = 0.7 x VCC, VIL = 0.3 x VCC
Figure 5.29
RSPI
RSPI Clock Timing and Simple SPI Clock Timing
Simple SPI
tTD
SSLn0 to 3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn SCKm
CPOL = 0 CKPOL = 0
output
output
RSPCKn SCKm
CPOL = 1 CKPOL = 1
output
output
MISOn
input
tSU
SMISOm
input
tH
MSB IN
tDR, tDF
MOSIn
output
(n = A, B)
SMOSIm
output
DATA
tOH
MSB OUT
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
(m = 0 to 3, 12)
Figure 5.30
RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKB Division Ratio Set to a Value Other
Than 1/2) and Simple SPI Timing (Master, CKPH = 1)
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RX63T Group
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
tTD
SSLN0 to 3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
MISOn
input
tHF
tHF
MSB IN
DATA
tDR, tDF
MOSIn
output
tOH
MSB OUT
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
(n = A, B)
Figure 5.31
RSPI
RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKB Division Ratio Set to 1/2)
Simple SPI
tTD
SSLN0 to 3
output
tLEAD
RSPCKn
CPOL = 0
output
SCKm
CKPOL = 0
output
RSPCKn
CPOL = 1
output
SCKm
CKPOL = 1
output
tLAG
tSSLr, tSSLf
tSU
MISOn
input
SMISOm
input
tH
MSB IN
tOH
MOSIn
output
SMOSIm
output
(n = A, B)
(m = 0 to 3, 12)
Figure 5.32
DATA
LSB IN
tOD
MSB OUT
MSB IN
tDR, tDF
DATA
LSB OUT
IDLE
MSB OUT
RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKB Division Ratio Set to a Value Other
Than 1/2) and Simple SPI Timing (Master, CKPH = 0)
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RX63T Group
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
RSPI
tTD
SSLN0 to 3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
MISOn
input
tH
tHF
MSB IN
tOH
DATA
LSB IN
tOD
MOSIn
output
MSB OUT
MSB IN
tDR, tDF
DATA
LSB OUT
IDLE
MSB OUT
(n = A, B)
Figure 5.33
RSPI
RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKB Division Ratio Set to 1/2)
Simple SPI
tTD
SSLn0
input
SSm#
input
tLEAD
tLAG
RSPCKn SCKm
CPOL = 0 CKPOL = 0
input
input
RSPCKn SCKm
CPOL = 1 CKPOL = 1
input
input
tSA
MISOn
output
tOH
SMISOm
output
MSB OUT
tSU
MOSIn
input
(n = A, B)
SMOSIm
input
tOD
DATA
tREL
LSB OUT
tH
MSB IN
MSB IN
MSB OUT
tDR, tDF
DATA
LSB IN
MSB IN
(m = 0 to 3, 12)
Figure 5.34
RSPI Timing (Slave, CPHA = 0) and Simple SPI Timing (Slave, CKPH = 1)
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RX63T Group
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
RSPI
Simple SPI
SSLn0
input
SSm#
input
tTD
tLEAD
tLAG
RSPCKn SCKm
CPOL = 0 CPOL = 0
input
input
RSPCKn SCKm
CPOL = 1 CPOL = 1
input
input
tSA
LSB OUT
(Last data)
SMISOm
output
MISOn
output
tOH
tOD
MSB OUT
tSU
SMOSIm
input
MOSIn
input
(n = A, B)
tREL
LSB OUT
DATA
tH
MSB OUT
tDR, tDF
MSB IN
DATA
LSB IN
MSB IN
(m = 0 to 3, 12)
Figure 5.35
RSPI Timing (Slave, CPHA = 1) and Simple SPI Timing (Slave, CKPH = 0)
RIIC
Simple IIC
SDAn
SSDAm
VIH
VIL
tBUF
tSCLH
tSTAS
tSTAH
SCLn
SSCLm
(n = 0, 1)
(m = 0 to 3,12)
P *1
tSCLL
tSr
tSf
tSCL
tSDAS
tSDAH
Note 1. S, P, and Sr indicate the following conditions.
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 5.36
P *1
Sr *1
S *1
tSTOS
tSP
Test conditions
VIH = VCC×0.7, VIL = VCC×0.3
VOL = 0.6V, IOL = 6mA
RIIC Bus Interface Input/Output Timing and Simple IIC Bus Interface Input/Output
Timing
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RX63T Group
5.4
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
USB Characteristics
Table 5.18
On-Chip USB Full-Speed Characteristics (DP and DM Pin Characteristics)
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Ta = Topr. Ta is common to conditions 1 to 3.
Item
Input
characteristics
Output
characteristics
Symbol
Min.
Max.
Unit
Input high level voltage
VIH
2.0
—
V
Input low level voltage
VIL
—
0.8
V
Differential input sensitivity
VDI
0.2
—
V
Differential common mode range
VCM
0.8
2.5
V
Figure 5.37
Figure 5.38
| DP – DM |
Output high level voltage
VOH
2.8
3.6
V
IOH = –200 µA
Output low level voltage
VOL
0.0
0.3
V
IOL = 2 mA
Cross-over voltage
VCRS
1.3
2.0
V
Rise time
tLr
4
20
ns
Fall time
tLf
4
20
ns
Rise/fall time ratio
tLr / tLf
90
111.11
%
tLr / tLf
Output resistance
ZDRV
28
44
Ω
Rs = 24 Ω
included
DP, DM
90%
VCRS
90%
10%
10%
tLr
Figure 5.37
Test Conditions
tLf
DP and DM Output Timing (Full-Speed)
dp
24
Observation
point
50 pF
dm
24
50 pF
Figure 5.38
Test Circuit (Full-Speed)
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RX63T Group
5.5
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
A/D Conversion Characteristics
Table 5.19
10-Bit A/D Conversion Characteristics (1)
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Ta = Topr. Ta is common to conditions 1 to 3.
Item
Resolution
Min.
Typ.
Max.
Unit
Test
Conditions
10
10
10
Bit
AN0 to AN7
0.5
—
—
µs
Sampling
in 25
states
Other channels
0.75
—
—
μs
Sampling
in 50
states
AN0 to AN7
0.6
—
—
μs
Sampling
in 35
states
Other channels
0.75
—
—
μs
Sampling
in 50
states
Analog input capacitance
—
—
6
pF
Integral nonlinearity error
—
—
±3.0
LSB
Offset error
—
—
±2.0
LSB
Full-scale error
—
—
±3.0
LSB
Quantization error
—
±0.5
—
LSB
Absolute accuracy
—
—
±6.0
LSB
Conversion
time*1
(Operation at
ADCLK =
100 MHz)
With 0.1-µF
external capacitor
Without 0.1-µF
external capacitor
Permissible signal source
impedance
(max.) = 1 kΩ
Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states
is indicated.
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RX63T Group
Table 5.20
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
10-Bit A/D Conversion Characteristics (2)
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Ta = Topr is common to conditions 1 to 3.
Item
Resolution
Min.
Typ.
Max.
Unit
Test
Conditions
10
10
10
Bit
AN0 to AN7
0.8
—
—
μs
Sampling
in 15
states
Other channels
1.0
—
—
μs
Sampling
in 25
states
Analog input capacitance
—
—
6
pF
Integral nonlinearity error
—
—
±2.0
LSB
Conversion
time*1
(Operation at
ADCLK = 50
MHz)
Without 0.1-µF
external capacitor
Permissible signal source
impedance
(max.) = 1 kΩ
Offset error
—
—
±2.0
LSB
Full-scale error
—
—
±3.0
LSB
Quantization error
—
±0.5
—
LSB
Absolute accuracy
—
—
±4.0
LSB
Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states
is indicated.
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RX63T Group
Table 5.21
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
12-Bit A/D Conversion Characteristics (1)
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Ta = Topr
Item
Resolution
time*1
Conversion
(ADCLK = 25 MHz)
Without 0.1-µF external capacitor
Permissible signal source
impedance (max.) = 1.0 kΩ
Analog input capacitance
Sample and hold circuit
in use
Sample and hold circuit
not in use
Integral nonlinearity error
Min.
Typ.
Max.
Unit
12
12
12
Bit
2.0
—
—
µs
—
—
8
pF
—
—
±4.0
LSB
Offset error
—
—
±4.0
LSB
Full-scale error
—
—
±4.0
LSB
Quantization error
—
±0.5
—
LSB
Absolute accuracy
—
—
±8.0
LSB
Integral nonlinearity error
—
—
±3.0
LSB
Offset error
—
—
±3.0
LSB
Full-scale error
—
—
±3.0
LSB
Quantization error
—
±0.5
—
LSB
Absolute accuracy
—
—
±6.0
LSB
Test Conditions
Sampling in 20
states
AVin = 0.25 to
AVREFH–0.25
AVin = AVREFL to
AVREFH
Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states
is indicated.
Table 5.22
12-Bit A/D Conversion Characteristics (2)
Note: Common standard values for conditions not given in the table are listed as “Condition 1” and “Condition 2” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 2: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Ta = Topr. Ta is common to conditions 2 and 3.
Item
Resolution
Conversion time*1
(ADCLK = 50 MHz)
Without 0.1-µF external capacitor
Permissible signal source
impedance (max.) = 1.0 kΩ
Analog input capacitance
Sample and hold circuit
in use
Sample and hold circuit
not in use
Integral nonlinearity error
Min.
Typ.
Max.
Unit
12
12
12
Bit
1.0
—
—
µs
—
—
6
pF
—
—
±6.0
LSB
Offset error
—
—
±6.0
LSB
Full-scale error
—
—
±6.0
LSB
Quantization error
—
±0.5
—
LSB
Absolute accuracy
—
—
±8.0
LSB
Integral nonlinearity error
—
—
±3.0
LSB
Offset error
—
—
±3.0
LSB
Full-scale error
—
—
±3.0
LSB
Quantization error
—
±0.5
—
LSB
Absolute accuracy
—
—
±6.0
LSB
Test Conditions
Sampling in 20
states
AVin = 0.25 to
AVREFH–0.25
AVin = AVREFL to
AVREFH
Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states
is indicated.
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RX63T Group
Table 5.23
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
Characteristics of the Programmable Gain Amplifier
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Ta = Topr. Ta is common to conditions 1 to 3.
Item
Symbol
Min.
Typ.
Max.
Unit
Analog input capacitance
Cin
—
—
8
pF
Input offset voltage
Voff
—
—
8
mV
Vin
0.050 × AVcc
—
0.450 × AVcc
V
Input voltage range
(Vin)
Gain × 2.000
Gain × 2.500
0.047 × AVcc
0.360 × AVcc
Gain × 3.077
0.045 × AVcc
0.292 × AVcc
Gain × 3.636
0.042 × AVcc
0.247 × AVcc
Gain × 4.000
0.040 × AVcc
0.212 × AVcc
Gain × 4.444
0.036 × AVcc
0.191 × AVcc
Gain × 5.000
0.033 × AVcc
0.170 × AVcc
Gain × 5.714
0.031 × AVcc
0.148 × AVcc
Gain × 6.667
0.029 × AVcc
0.127 × AVcc
Gain × 10.000
0.025 × AVcc
Gain × 13.333
0.023 × AVcc
—
0.06 × AVcc
SR
10
—
—
V/μs
—
%
Slew rate
Gain error
Gain × 2.000
0.08 × AVcc
—
—
1
Gain × 2.500
—
—
1
Gain × 3.077
—
—
1
Gain × 3.636
—
—
1.5
Gain × 4.000
—
—
1.5
Gain × 4.444
—
—
2
Gain × 5.000
—
—
2
Gain × 5.714
—
—
2
Gain × 6.667
—
—
3
Gain × 10.000
—
—
4
Gain × 13.333
—
—
4
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Test Conditions
Page 140 of 186
RX63T Group
Table 5.24
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
Comparator Characteristics
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Ta = Topr. Ta is common to conditions 1 to 3.
Item
Symbol
Min.
Typ.
Max.
Unit
Analog input capacitance
Cin
—
—
8
pF
REFH pin offset voltage
Voff
—
—
5
mV
—
—
5
mV
REFL pin offset voltage
REFH input voltage range
Vin
REFL input voltage range
1.7
—
AVcc – 0.3
V
0.3
—
AVcc – 1.7
V
REFH reply time
tCR
—
—
500
ns
REFL reply time
tCF
—
—
500
ns
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Test Conditions
VI = VREF±25mV
Page 141 of 186
RX63T Group
5.6
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
D/A Conversion Characteristics
Table 5.25
D/A Conversion Characteristics
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Ta = Topr. Ta is common to conditions 1 to 3.
Item
Min.
Typ.
Max.
Unit
Resolution
10
10
10
Bit
Conversion time
—
—
3.0
µs
20-pF capacitive load
Absolute accuracy
—
±2.0
±4.0
LSB
2-MΩ resistive load
—
—
±3.0
LSB
4-MΩ resistive load
10-MΩ resistive load
RO output resistance
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
—
—
±2.0
LSB
—
3.6
—
kΩ
Test Conditions
Page 142 of 186
RX63T Group
5.7
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
Power-on Reset Circuit and Voltage Detection Circuit Characteristics
Table 5.26
Power-on Reset Circuit and Voltage Detection Circuit Characteristics (1)
Note: Common standard values for conditions not given in the table are listed as “Condition 1” and “Condition 2” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Ta = Topr. Ta is common to conditions 1 and 2.
Item
Voltage detection
level
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Power-on reset (POR)
VPOR
2.46
2.58
2.7
V
Figure 5.41
Voltage detection circuit (LVD0)
VDET0
2.7
2.82
2.94
Figure 5.42
Voltage detection circuit (LVD1)*1
VDET1_8
2.75
2.90
3.05
Figure 5.43
VDET1_9
2.70
2.85
3.00
VDET1_A
2.73
2.88
3.03
VDET2_8
2.75
2.9
3.05
VDET2_9
2.70
2.85
3.00
VDET2_A
2.73
2.88
3.03
Voltage detection circuit (LVD2)*2
Internal reset time
Figure 5.44
Power-on reset (POR)
tPOR
9.7
Voltage detection circuit (LVD0)
tLVD0
9.7
Figure 5.42
Voltage detection circuit (LVD1)
tLVD1
0.9
Figure 5.43
Voltage detection circuit (LVD2)
tLVD2
0.9
Figure 5.44
time*3
tVOFF
Minimum VCC down
200
—
ms
—
µs
Response delay time
tDET
200
µs
LVD operation stabilization time (after LVD is enabled)
Td(E-A)
3
µs
Hysteresis width (LVD1 and LVD2)
V LVH
80
mV
Figure 5.41
Figure 5.41 and
Figure 5.42
Figure 5.41 to
Figure 5.44
Note 1. # in symbol VDET1_# indicates the value of the LVDLVLR.LVD1LVL[3:0] bits.
Note 2. # in symbol VDET2_# indicates the value of the LVDLVLR.LVD2LVL[3:0] bits.
Note 3. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR,
VDET1, and VDET2 for the POR/ LVD.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 143 of 186
RX63T Group
Table 5.27
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
Power-on Reset Circuit and Voltage Detection Circuit Characteristics (2)
Condition: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Ta = Topr
Item
Voltage detection
level
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Power-on reset (POR)
VPOR
3.6
3.8
4.0
V
Figure 5.41
Voltage detection circuit (LVD0)
VDET0
4.0
4.2
4.4
Figure 5.42
Voltage detection circuit (LVD1)*1
VDET1_8
4.59
4.77
4.95
Figure 5.43
VDET1_9
4.05
4.23
4.41
VDET1_A
4.32
4.50
4.68
VDET2_8
4.59
4.77
4.95
VDET2_9
4.05
4.23
4.41
VDET2_A
4.32
4.50
4.68
Voltage detection circuit (LVD2)*2
Internal reset time
Figure 5.44
Power-on reset (POR)
tPOR
9.7
Voltage detection circuit (LVD0)
tLVD0
9.7
Figure 5.42
Voltage detection circuit (LVD1)
tLVD1
0.9
Figure 5.43
Voltage detection circuit (LVD2)
tLVD2
0.9
Figure 5.44
time*3
tVOFF
Minimum VCC down
200
—
ms
—
µs
Response delay time
tDET
200
µs
LVD operation stabilization time (after LVD is enabled)
Td(E-A)
3
µs
Hysteresis width (LVD1 and LVD2)
V LVH
80
mV
Figure 5.41
Figure 5.41 to
Figure 5.44
Figure 5.41 to
Figure 5.44
Note 1. # in symbol VDET1_# indicates the value of the LVDLVLR.LVD1LVL[3:0] bits.
Note 2. # in symbol VDET2_# indicates the value of the LVDLVLR.LVD2LVL[3:0] bits.
Note 3. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR,
VDET1, and VDET2 for the POR/ LVD.
tVOFF
VPOR
VCC
Internal reset signal
(active-low)
tDET
Figure 5.39
tPOR
tDET
tDET tPOR
Power-on Reset Timing
tVOFF
VCC
VDET0
Internal reset signal
(active-low)
tDET
Figure 5.40
tLVD0
Voltage Detection Circuit Timing (VDET0)
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 144 of 186
RX63T Group
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
tVOFF
VCC
VDET1_#
(# = 8, 9, A)
VLVH
LVD1E
Td(E-A)
LVD1
Comparator output
LVD1CMPE
LVD1MON
Internal reset signal
(active-low)
When LVD1RN = L
tDET
tDET
tLVD1
When LVD1RN = H
tLVD1
Figure 5.41
Voltage Detection Circuit Timing (VDET1)
tVOFF
VCC
VDET2_#
(# = 8, 9, A)
VLVH
LVD2E
Td(E-A)
LVD2
Comparator output
LVD2CMPE
LVD2MON
Internal reset signal
(active-low)
When LVD2RN = L
tDET
tDET
tLVD2
When LVD2RN = H
tLVD2
Figure 5.42
Voltage Detection Circuit Timing (VDET2)
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 145 of 186
RX63T Group
5.8
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
Oscillation Stop Detection Circuit Characteristics
Table 5.28
Oscillation Stop Detection Circuit Characteristics
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Ta = Topr. Ta is common to conditions 1 to 3.
Item
Symbol
Detection time
tdr
Min.
Typ.
—
—
Max.
1.0
Unit
ms
Test Conditions
Figure 5.43
Main clock or PLL clock
tdr
OSTDSR.OSTDF
LOCO clock
ICLK
Figure 5.43
Oscillation Stop Detection Timing
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 146 of 186
RX63T Group
5.9
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
ROM (Flash Memory for Code Storage) Characteristics
Table 5.29
ROM (Flash Memory for Code Storage) Characteristics (1)
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Temperature range for the programming/erasure operation: Ta = Topr. Ta is common to conditions 1 to 3.
Item
Reprogram/erase
Symbol
cycle*1
Data hold time
Min.
Typ.
Max.
Unit
Test Conditions
Npec
1000
—
—
Times
tDRP
30*2
—
—
Year
Ta = +85°C
Note 1. Definition of reprogram/erase cycle:
The reprogram/erase cycle is the number of erasing for each block. When the reprogram/erase cycle is n times (n = 1000),
erasing can be performed n times for each block. For instance, when 128-byte programming is performed 16 times for different
addresses in 2-Kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address for several times as one erasing is not enabled (overwriting is prohibited).
Note 2. The value is obtained from the reliability test.
Table 5.30
ROM (Flash Memory for Code Storage) Characteristics (2)
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0,
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Temperature range for the programming/erasure operation: Ta = Topr. Ta is common to conditions 1 to 3.
Item
Symbol
20 MHz ≤ FCLK ≤ 50 MHz
FCLK = 4 MHz
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
128 bytes
tP128
—
2.8
28
—
1
10
ms
4 Kbytes
tP4K
—
63
140
—
23
50
ms
16 Kbytes
tP16K
—
252
560
—
90
200
ms
128 bytes
tP128
—
3.4
33.6
—
1.2
12
ms
4 Kbytes
tP4K
—
75.6
168
—
27.6
60
ms
16 Kbytes
tP16K
—
302.4
672
—
108
240
ms
Erasure time
NPEC 100 times
4 Kbytes
tE4K
—
50
120
—
25
60
ms
16 Kbytes
tE16K
—
200
480
—
100
240
ms
Erasure time
NPEC > 100 times
4 Kbytes
tE4K
—
60
144
—
30
72
ms
16 Kbytes
Programming time
NPEC 100 times
Programming time
NPEC > 100 times
tE16K
—
240
576
—
120
288
ms
Suspend delay time during programming
tSPD
—
—
400
—
—
120
μs
First suspend delay time during erasing
(in suspend priority mode)
tSESD1
—
—
300
—
—
120
μs
Second suspend delay time during erasing
(in suspend priority mode)
tSESD2
—
—
1.7
—
—
1.7
ms
Suspend delay time during erasing
(in erasure priority mode)
tSEED
—
—
1.7
—
—
1.7
ms
FCU reset time
tFCUR
35
—
—
35
—
—
μs
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 147 of 186
RX63T Group
5.10
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
E2 Flash Characteristics
E2 Flash Characteristics (1)
Table 5.31
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Temperature range for the programming/erasure operation: Ta = Topr. Ta is common to conditions 1 to 3.
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Reprogram/erase cycle*1
NDPEC
100000
—
—
Times
Data hold time
tDDRP
30*2
—
—
Year
Ta = +85°C
Note 1. Definition of reprogram/erase cycle:
The reprogram/erase cycle is the number of erasing for each block. When the reprogram/erase cycle is n times (n = 100000),
erasing can be performed n times for each block. For instance, when 128-byte programming is performed 16 times for different
addresses in 2-Kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address for several times as one erasing is not enabled (overwriting is prohibited).
Note 2. The value is obtained from the reliability test.
Table 5.32
E2 Flash Characteristics (2)
Note: Common standard values for conditions not given in the table are listed as “Condition 1” to “Condition 3” below.
Condition 1: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Condition 2: VCC = PLLVCC = VCC_USB = 2.7 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VCC_USB = 3.0 to 3.6 V, VSS = PLLVSS = VSS_USB = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = VREF = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0
Temperature range for the programming/erasure operation: Ta = Topr. Ta is common to conditions 1 to 3.
Item
Symbol
FCLK = 4 MHz
20 MHz ≤ FCLK ≤ 50 MHz
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Programming time
NDPEC 100 times
2 bytes
tDP2
—
0.7
6
—
0.25
2
ms
Programming time
NDPEC > 100 times
2 bytes
tDP2
—
0.7
6
—
0.25
2
ms
Erasure time
NDPEC 100 times
32 bytes
tDE32
—
4
40
—
2
20
ms
Erasure time
NDPEC > 100 times
32 bytes
tDE32
—
7
40
—
4
20
ms
Blank check time
2 bytes
tDBC2
—
—
100
—
—
30
μs
Suspend delay time during programming
tDSPD
—
—
250
—
—
120
μs
First suspend delay time during erasing
(in suspend priority mode)
tDSESD1
—
—
250
—
—
120
μs
Second suspend delay time during erasing
(in suspend priority mode)
tDSESD2
—
—
500
—
—
300
μs
Suspend delay time during erasing
(in erasure priority mode)
tDSEED
—
—
500
—
—
300
μs
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 148 of 186
RX63T Group
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
• Suspension during programming
FCU command
Program
Suspend
tSPD
FSTATR0.FRDY
Ready
Programming pulse
Not Ready
Ready
Programming
• Suspension during erasure in suspend priority mode
FCU command
Erase
Suspend
Resume
Suspend
tSESD1
FSTATR0.FRDY
Ready
Erasure pulse
Not Ready
tSESD2
Ready
Erasing
Not Ready
Erasing
• Suspension during erasure in erasure priority mode
FCU command
Erase
Suspend
tSEED
FSTATR0.FRDY
Ready
Erasure pulse
Figure 5.44
Not Ready
Ready
Erasing
Flash Memory Program/Erase Suspend Timing
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 149 of 186
RX63T Group
6. Electrical Characteristics [64- and 48-Pin Versions]
6.
Electrical Characteristics [64- and 48-Pin Versions]
6.1
Absolute Maximum Ratings
Table 6.1
Absolute Maximum Ratings
Item
Symbol
Value
Unit
Power supply voltage
VCC
–0.3 to +4.6
V
Input voltage (except for ports for 5 V
tolerant*1 and port 4)
Vin
–0.3 to VCC+0.3
V
Input voltage (port 4)
Vin
–0.3 to AVCC0+0.3
V
Input voltage (ports for 5 V
tolerant)*1
Vin
–0.3 to +5.8
V
Analog power supply voltage
AVCC0*2
–0.3 to +4.6
V
Reference power supply voltage
VREFH0*2
–0.3 to AVCC0+0.3
V
Analog input voltage (port 4)
VAN
–0.3 to AVCC0+0.3
V
Operating
temperature
D version product
Topr
–40 to +85
°C
G version product
Topr
–40 to +105
°C
Tstg
–55 to +125
°C
Storage temperature
Caution: Permanent damage to the LSI may result if absolute maximum ratings are exceeded.
Note 1. Ports 0, 1, 2, 3, 7, 9, A, B, and D are 5 V tolerant.
Note 2. When the A/D converter is not in use, do not leave the AVCC0, VREFH0, VREFL0, and AVSS0 pins open. Connect the AVCC0
and VREFH0 pins to VCC, and the AVSS0 and VREFL0 pins to VSS, respectively.
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RX63T Group
6.2
6. Electrical Characteristics [64- and 48-Pin Versions]
DC Characteristics
Table 6.2
DC Characteristics (1)
Conditions: VCC = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V,
AVCC0 = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0,
Ta = Topr
Item
Schmitt trigger
input voltage
Typ.
Max.
VIH
VCC × 0.8
—
VCC + 0.3
VIL
–0.3
—
VCC × 0.2
∆VT
VCC × 0.06
—
—
RIIC input pin (IICBus
operating)
VIH
VCC × 0.7
—
5.8
VIL
–0.3
—
VCC × 0.3
∆VT
VCC × 0.05
—
—
VIH
AVCC0 × 0.8
—
AVCC0 + 0.3
VIL
–0.3
—
AVCC0×0.2
Ports for 5 V tolerant*1
Input low voltage
(except for Schmitt
trigger input pin)
Min.
IRQ input pin
MTU3 input pin
POE3 input pin
SCI input pin
A/D trigger input pin
GPT input pin
RES#, NMI
Port 4
(also used as an analog
port)
Input high voltage
(except for Schmitt
trigger input pin)
Symbol
VIH
VCC × 0.8
—
5.8
VIL
–0.3
—
VCC × 0.2
VIH
VCC × 0.9
—
VCC + 0.3
EXTAL, TCK, RSPI input pin
VCC × 0.8
—
VCC + 0.3
RIIC input pin (SMBus
operating)
2.1
—
VCC + 0.3
MD pin, EMLE
MD pin, EMLE
VIL
–0.3
—
VCC × 0.1
EXTAL, TCK, RSPI input pin
–0.3
—
VCC × 0.2
RIIC input pin (SMBus
operating)
–0.3
—
0.8
Unit
Test Conditions
V
Output high voltage
All output pins
VOH
VCC – 0.5
—
—
V
IOH = –1 mA
Output low voltage
All output pins
(except for RIIC pins)
VOL
—
—
0.5
V
IOL = 1.0 mA
—
—
0.4
IOL = 3 mA
—
—
0.6
IOL = 6 mA
RIIC pins
Input leakage
current
RES#, MD pin, EMLE,
Ports 4 and PE2
Iin
—
—
1.0
μA
Vin = 0V, Vin = VCC
Three-state
leakage current
(off state)
Ports for 5V tolerant
ITSI
—
—
1.0
μA
Vin = 0V, Vin = 5.5 V
—
—
5.0
Input capacitance
All input pins
(except for ports PB1 and
PB2)
—
—
15
pF
Vin = 0V,
f = 1 MHz,
Ta = 25ºC
—
—
30
Cin
Ports PB1 and PB2
Note 1. Ports 0, 1, 2, 3, 7, 9, A, B, and D are 5 V tolerant.
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RX63T Group
Table 6.3
6. Electrical Characteristics [64- and 48-Pin Versions]
DC Characteristics (2)
Conditions: VCC = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V,
AVCC0 = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0,
Ta = Topr
Item
Supply
current*1
ICC*3
Min.
Max.
—
60
Normal *4
—
25
—
Increased by BGO
operation*5
—
15
—
Sleep mode
25
35
All-module-clock-stop mode*6
14
25
Unit
mA
Software standby mode
—
0.2
6
mA
Deep software standby
mode
—
16
40
μA
—
3
4
mA
—
2
3
mA
0.4
1
mA
During 12-bit A/D conversion (sample &
hold circuit in use)
AICC0
During 12-bit A/D conversion (sample &
hold circuit not in use)
Window comparator (1-channel operation)
Reference
power supply
current
Typ.
—
During
standby
Analog power
supply current
Symbol
Max. *2
During
operation
Window comparator (3-channel operation)
—
0.5
1
mA
Waiting for 12-bit AD conversion
—
25
32
μA
—
0.6
0.7
mA
—
0.6
0.7
mA
—
—
20000
ms/V
During 12-bit A/D conversion
AIREFH0
Waiting for 12-bit A/D conversion
VCC rising gradient
SrVcc
Test Conditions
ICLK = 100MHz
PCLKA = 100MHz
PCLKB = 50MHz
PCLKD = 50MHz
FCLK = 50MHz
Note 1. Supply current values are with all output pins unloaded.
Note 2. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation.
Note 3. ICC depends on f (ICLK) as follows. (ICLK: PCLK = 8:4)
ICC max = 0.45 × f + 15 (Max)
ICC typ = 0.18 × f + 7 (Normal)
ICC max = 0.22 × f + 13 (sleep mode)
Note 4. Measured with clocks not supplied to the peripheral functions. This does not include the BGO operation.
Note 5. Incremented if data is written to or erased from the on-chip ROM or on-chip data-flash memory for data storage during the
program execution.
Note 6. The values are for reference.
Table 6.4
Permissible Output Currents
Conditions: VCC = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V,
AVCC0 = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0,
Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
Permissible output low current (average value per pin)
IOL
—
—
2.0*1
Permissible output low current (max. value per pin)
IOL
—
—
4.0*1
mA
Permissible output low current (total)
ΣIOL
—
—
32
mA
Permissible output high current (average value per pin)
–IOH
—
—
2.0
mA
Permissible output high current (max. value per pin)
–IOH
—
—
4.0
mA
Permissible output high current (total)
Σ–IOH
—
—
32
mA
mA
Caution: To protect the MCU’s reliability, the output current values should not exceed the values in this table.
Note 1. RIIC pin: IOL = 6 mA (max.)
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RX63T Group
Table 6.5
6. Electrical Characteristics [64- and 48-Pin Versions]
Permissible Power Consumption (G version product only)
Condition: VCC = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V
AVCC0 = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Ta = Topr
Item
Total permissible power consumption*1
Symbol
Typ.
Max.
Unit
Test Conditions
Pd
—
150
mW
85°C < Ta ≤ 105°C
64-pin version
Pd
—
120
mW
85°C < Ta ≤ 105 °C
48-pin version
Note: • Please contact Renesas Electronics sales office for derating of operation under Ta = +85°C to +105°C. Derating is the
systematic reduction of load for the sake of improved reliability.
Note 1. The total power consumption of the whole chip including output current.
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RX63T Group
6.3
6. Electrical Characteristics [64- and 48-Pin Versions]
AC Characteristics
Table 6.6
Operation Frequency Value
Conditions: VCC = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V,
AVCC0 = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0,
Ta = Topr
Item
Operation
frequency
Symbol
System clock (ICLK)
f
Peripheral module clock PCLK
Min.
Typ
Max.
—
—
100
—
—
50
Timer module clock (PCLKA)
—
—
100
S12AD clock (PCLKD)
—
—
50
Flash clock (FCLK)
—*1
—
50
Unit
MHz
Note 1. The FCLK must run at a frequency of at least 4 MHz when changing the ROM or E2 DataFlash memory contents.
6.3.1
Clock Timing
Table 6.7
Clock Timing
Conditions: VCC = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V,
AVCC0 = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0,
Ta = Topr
Symbol
Min
Typ
Max.
Unit
Test
Conditions
tEXcyc
50
—
—
ns
Figure 6.1
EXTAL external clock input high pulse width
tEXH
20
—
—
ns
EXTAL external clock input low pulse width
tEXL
20
—
—
ns
EXTAL external clock rising time
tEXr
—
—
5
ns
Item
EXTAL external clock input cycle time
EXTAL external clock falling time
tEXf
—
—
5
ns
EXTAL external clock input wait time*1
tEXWT
1
—
—
ms
Main clock oscillator oscillation frequency
fMAIN
4
—
16
MHz
ms
Main clock oscillation stabilization time (crystal)
Main clock oscillation stabilization wait time (crystal)
LOCO, IWDTCLK clock cycle time
LOCO, IWDTCLK clock oscillation frequency
LOCO, IWDTCLK clock oscillation stabilization wait time
PLL clock oscillation stabilization time
PLL clock oscillation stabilization wait
time
PLL clock oscillation stabilization time
PLL
PLL clock oscillation stabilization wait
time
PLL operation started
after main clock
oscillation has settled
PLL operation started
before main clock
oscillation has settled
tMAINOSC
—
—
—*2
tMAINOSCWT
—
—
—*3
ms
tcyc
6.96
8
9.4
μs
Figure 6.2
fLOCO
106.25
125
143.75
kHz
tLOCOWT
—
—
20
μs
Figure 6.2
tPLL1
—
—
500
μs
Figure 6.4
ms
tPLLWT1
—
—
—*4
tPLL2
—
—
tMAINOSC
+ tPLL1
ms
tPLLWT2
—
—
—*4
ms
Figure 6.5
Note 1. This is the time until the clock is used after clearing the main clock oscillator stop bit (MOSCCR.MOSTP) to 0 (selecting
operation).
Note 2. When using a main clock, ask the manufacturer of the oscillator to evaluate its oscillation. Refer to the results of evaluation
provided by the manufacturer for the oscillation stabilization time.
Note 3. This is calculated from the formula below, where n is the number of cycles set by the MOSCWTCR.MSTS[4:0] bits.
tMAINOSCWT = tMAINOSC +
n +16384
R01DS0087EJ0220 Rev.2.20
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fMAIN
Page 154 of 186
RX63T Group
6. Electrical Characteristics [64- and 48-Pin Versions]
Note 4. This is calculated from the formula below, where n is the number of cycles set by the PLLWTCR.PSTS[4:0] bits.
tPLLWT1 = tPLL1 +
tPLLWT2 = tPLL2 +
n +131072
fPLL
n +131072
fPLL
= tMAINOSC + tPLL1 +
n +131072
fPLL
tEXcyc
tEXH
tEXL
EXTAL external clock input
VCC × 0.5
tEXr
Figure 6.1
tEXf
EXTAL External Clock Input Timing
MOSCCR.MOSTP
tMAINOSC
Main clock oscillation output
tMAINOSCWT
Main clock
Figure 6.2
Main Clock Oscillation Start Timing
LOCOCR.LCSTP,
ILOCOCR.ILCSTP
tLOCOWT
LOCO, IWDTCLK
clock
Figure 6.3
LOCO, IWDTCLK Clock Oscillation Start Timing
MOSCCR.MOSTP
tMAINOSC
Main clock oscillation output
PLLCR2.PLLEN
tPLL1
PLL circuit output
tPLLWT1
PLL clock
Figure 6.4
PLL Clock Oscillation Start Timing (PLL is Operated after Main Clock Oscillation Has
Settled)
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RX63T Group
6. Electrical Characteristics [64- and 48-Pin Versions]
MOSCCR.MOSTP
tMAINOSC
Main clock oscillation output
PLLCR2.PLLEN
tPLL2
PLL circuit output
tPLLWT2
PLL clock
Figure 6.5
PLL Clock Oscillation Start Timing (PLL is Operated before Main Clock Oscillation Has
Settled)
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RX63T Group
6. Electrical Characteristics [64- and 48-Pin Versions]
6.3.2
Reset Timing
Table 6.8
Reset Timing
Conditions: VCC = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V,
AVCC0 = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0,
Ta = Topr
Symbol
Min
Typ
Max.
Unit
Test
Conditions
Power-on
tRESWP
2
—
—
ms
Figure 6.6
Deep software standby mode
tRESWD
1
—
—
ms
Figure 6.7
Software standby mode
tRESWS
1
—
—
ms
Other than above (except for programming or
erasure of the ROM or E2 DataFlash memory or
blank checking of the E2 DataFlash memory)
tRESW
200
—
—
μs
Item
RES# pulse
width
Wait time after RES# cancellation
tRESWT
59
—
60
tcyc
Internal reset time (independent watchdog timer reset, watchdog
timer reset, software reset)
tRESW2
112
—
120
tcyc
VCC
RES#
tRESWP
Internal reset
tRESWT
Figure 6.6
Reset Input Timing at Power-On
tRESWD, tRESWS, tRESW
RES#
Internal reset
tRESWT
Figure 6.7
Reset Input Timing
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RX63T Group
6. Electrical Characteristics [64- and 48-Pin Versions]
6.3.3
Timing of Recovery from Low Power Consumption Modes
Table 6.9
Timing of Recovery from Low Power Consumption Modes
Conditions: VCC = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V,
AVCC0 = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0,
Ta = Topr
Item
Recovery time
after
cancellation of
software
standby mode
Symbol
Min.
Typ.
Max.
Unit
Crystal resonator
connected to
main clock
oscillator
Main clock oscillator
operating
tSBYMC
10
—
—
ms
Main clock oscillator and
PLL circuit operating
tSBYPC
10
—
—
ms
External clock
input to main
clock oscillator
Main clock oscillator
operating
tSBYEX
1
—
—
ms
Main clock oscillator and
PLL circuit operating
tSBYPE
1
—
—
ms
—
—
800
µs
Low-speed clock oscillator or IWDT-specific low- tSBYLO
speed clock oscillator operating
Recovery time after cancellation of deep software standby mode
tDSBY
—
—
1
ms
Wait time after cancellation of deep software standby mode
tDSBYWT
45
—
46
tcyc
Test
Conditions
Figure 6.8
Figure 6.9
Note: • The wait time varies depending on the state in which each oscillator was when the WAIT instruction was executed. The recovery
time when multiple oscillators are operating is the same period as that when the oscillator, which takes the longest time for
recovery among the operating oscillators, is operating alone.
Oscillator
ICLK
IRQ
Software standby mode
tSBYMC, tSBYPC, tSBYEX, tSBYPE, tSBYLO
Figure 6.8
Software Standby Mode Cancellation Timing
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RX63T Group
6. Electrical Characteristics [64- and 48-Pin Versions]
Oscillator
IRQ
Deep software
standby reset
Internal reset
Deep software standby mode
tDSBY
tDSBYWT
Reset exception handling start
Figure 6.9
Deep Software Standby Mode Cancellation Timing
6.3.4
Control Signal Timing
Table 6.10
Control Signal Timing
Conditions: VCC = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V,
AVCC0 = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0,
Ta = Topr
Item
Symbol
Min.
NMI pulse width
tNMIW
200
IRQ pulse width
tIRQW
200
Typ.
Max.
Unit
Test Conditions
tPcyc × 2 ≤ 200ns, Figure 6.10
—
—
ns
tPcyc
tPcyc × 2 > 200ns, Figure 6.10
—
—
ns
tPcyc × 2 ≤ 200ns, Figure 6.11
tPcyc
tPcyc × 2 > 200ns, Figure 6.11
2
2
Note 1. tPcyc: PCLK cycle
NMI
tNMIW
Figure 6.10
NMI Interrupt Input Timing
IRQ
tIRQW
Figure 6.11
IRQ Interrupt Input Timing
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RX63T Group
6. Electrical Characteristics [64- and 48-Pin Versions]
6.3.5
Timing of On-Chip Peripheral Modules
Table 6.11
Timing of On-Chip Peripheral Modules (1)
Conditions: VCC = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V,
AVCC0 = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0,
Ta = Topr
Symbol
Min.
Max.
Unit*1
Test
Conditions
tPRW
1.5
—
tPcyc
Figure 6.12
tTICW
3
—
tPAcyc
Figure 6.13
5
—
3
—
tPAcyc
Figure 6.14
Both-edge
setting
5
—
Phase counting
mode
5
—
tPOEW
1.5
—
tPcyc
Figure 6.16
tGTICW
3
—
tPAcyc
Figure 6.15
5
—
3
—
tPAcyc
Figure 6.18
5
—
4
—
tPcyc
Figure 6.17
6
—
Item
I/O ports
Input data pulse width
MTU3
Input capture input pulse
width
Single-edge
setting
Both-edge
setting
Timer clock pulse width
POE3
POE# input pulse width
GPT
Input capture input pulse
width
Single-edge
setting
Single-edge
setting
tTCKWH,
tTCKWL
Both-edge
setting
External trigger input pulse
width
Single-edge
setting
tOTETW
Both-edge
setting
SCI
Input clock cycle
Asynchronous
tScyc
Clock
synchronous
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
—
20
ns
Input clock fall time
tSCKf
—
20
ns
tScyc
16
—
tPcyc
4
—
Output clock cycle
Asynchronous
Clock
synchronous
Output clock pulse width
tSCKW
0.4
0.6
tScyc
Output clock rise time
tSCKr
—
20
ns
tSCKf
—
20
ns
Transmit data delay time
Clock
synchronous
tTXD
—
40
ns
Receive data setup time
Clock
synchronous
tRXS
40
—
ns
Receive data hold time
Clock
synchronous
tRXH
40
—
ns
tTRGW
1.5
—
tPcyc
Output clock fall time
A/D
converter
12-bit A/D converter trigger input pulse width
Figure 6.18
Figure 6.19
Note 1. tPcyc: PCLK cycle, tPAcye: PCLKA cycle
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RX63T Group
Table 6.12
6. Electrical Characteristics [64- and 48-Pin Versions]
Timing of On-Chip Peripheral Modules (2)
Conditions: VCC = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V,
AVCC0 = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0,
Ta = Topr
Item
RSPI
RSPCK clock cycle
Symbol
Master
tSPcyc
Slave
RSPCK clock high pulse
width
Master
tSPCKWH
Slave
RSPCK clock low pulse
width
Master
tSPCKWL
Slave
RSPCK clock rise/fall time
Data input setup time
Output
Figure 6.20
4096
4096
(tSPcyc – tSPCKR
– tSPCKF) / 2 – 3
—
(tSPcyc – tSPCKR
– tSPCKF) / 2
—
(tSPcyc – tSPCKR
– tSPCKF) / 2 – 3
—
(tSPcyc – tSPCKR
– tSPCKF) / 2
—
ns
ns
5
ns
1
μs
Master
tSU
15
—
ns
20
—
20 – tPcyc
—
Master
tH
0
—
Master
20 + 2 × tPcyc
—
tLEAD
1
8
tSPcyc
4
—
tPcyc
Master
tLAG
Master
tOD
Slave
Data output hold time
tPcyc
2
8
—
Slave
Data output delay time
Test Conditions
—
Slave
SSL hold time
Unit*1
tSPCKR,
tSPCKF
Slave
SSL setup time
Max.
Input
Slave
Data input hold time
Min.
Master
tOH
Slave
Successive transmission
delay time
Master
MOSI rise/fall time
Output
tTD
Slave
ns
1
8
tSPcyc
4
—
tPcyc
—
18
ns
—
3 × tPcyc + 40
0
—
0
—
tSPcyc + 2 × tPcyc
8 × tSPcyc
+ 2 × tPcyc
4 × tPcyc
—
ns
ns
tMODR,
tMODF
—
5
ns
—
1
μs
tMODR,
tMODF
—
5
ns
—
1
μs
tSSLr,
tSSLf
—
15
ns
—
1
μs
Slave access time
tSA
—
4
tPcyc
Slave output release time
tREL
—
3
tPcyc
Input
MISO rise/fall time
Output
Input
SSL rise/fall time
Output
Input
Figure 6.21 to
Figure 6.24
Figure 6.23 and
Figure 6.24
Note 1. tPcyc: PCLK cycle
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RX63T Group
Table 6.13
6. Electrical Characteristics [64- and 48-Pin Versions]
Timing of On-Chip Peripheral Modules (3)
Conditions: VCC = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V,
AVCC0 = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0,
Ta = Topr
Item
Simple
SPI
SCK clock cycle output (master)
Symbol
tSPcyc
Min.
Max.
Unit*1
Test Conditions
tPcyc
Figure 6.20
4
65536
8
65536
tSPCKWH
0.4
0.6
SCK clock low pulse width
tSPCKWL
0.4
0.6
tSPcyc
SCK clock rise/fall time
tSPCKR, tSPCKF
—
20
ns
Data input setup time
tSU
40
—
ns
SCK clock cycle input (slave)
SCK clock high pulse width
tSPcyc
Data input hold time
tH
40
—
ns
SS input setup time
tLEAD
6
—
tPcyc
SS input hold time
tLAG
6
—
tPcyc
Data output delay time
tOD
—
40
ns
Data output hold time
tOH
–10
—
ns
Data rise/fall time
tDR, tDF
—
20
ns
SS input rise/fall time
tSSLr, tSSLf
—
20
ns
Slave access time
tSA
—
5
tPcyc
Slave output release time
tREL
—
5
tPcyc
Figure 6.21 to
Figure 6.24
Figure 6.23 and
Figure 6.24
Note 1. tPcyc: PCLK cycle
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 162 of 186
RX63T Group
Table 6.14
6. Electrical Characteristics [64- and 48-Pin Versions]
Timing of On-Chip Peripheral Modules (4)
Conditions: VCC = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V,
AVCC0 = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0,
Ta = Topr
Symb
ol
Min.
Max.
Unit
Test
Conditions
SCL input cycle time
tSCL
6(12) × tIICcyc + 1300
—
ns
Figure 6.25
SCL input high pulse width
tSCLH
3(6) × tIICcyc + 300
—
ns
SCL input low pulse width
tSCLL
3(6) × tIICcyc + 300
—
ns
SCL, SDA input rise time
tSr
—
1000
ns
SCL, SDA input fall time
tSf
—
300
ns
SCL, SDA input spike pulse removal time
tSP
0
1(4) × tIICcyc
ns
SDA input bus free time
tBUF
3(6) × tIICcyc + 300
—
ns
Item
RIIC
(Standard-mode)
RIIC
(Fast-mode)
Start condition input hold time
tSTAH
tIICcyc + 300
—
ns
Restart condition input setup time
tSTAS
1000
—
ns
Stop condition input setup time
tSTOS
1000
—
ns
Data input setup time
tSDAS
tIICcyc + 50
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb
—
400
pF
SCL input cycle time
tSCL
6(12) × tIICcyc + 600
—
ns
SCL input high pulse width
tSCLH
3(6) × tIICcyc + 300
—
ns
SCL input low pulse width
tSCLL
3(6) × tIICcyc + 300
—
ns
SCL, SDA input rise time
tSr
20 + 0.1Cb
300
ns
SCL, SDA input fall time
tSf
20 + 0.1Cb
300
ns
SCL, SDA input spike pulse removal time
tSP
0
1(4) × tIICcyc
ns
SDA input bus free time
tBUF
3(6) × tIICcyc + 300
—
ns
Start condition input hold time
tSTAH
tIICcyc + 300
—
ns
Restart condition input setup time
tSTAS
300
—
ns
Stop condition input setup time
tSTOS
300
—
ns
Data input setup time
tSDAS
tIICcyc + 50
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb
—
400
pF
Note 1. tIICcyc: RIIC internal reference clock (IIC) Cycle
Note 2. The value within parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 11b while the digital filter is enabled by
the setting ICFER.NFE = 1.
Note 3. Cb is the total capacitance of the bus lines.
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 163 of 186
RX63T Group
Table 6.15
6. Electrical Characteristics [64- and 48-Pin Versions]
Timing of On-Chip Peripheral Modules (5)
Conditions: VCC = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V,
AVCC0 = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0,
Ta = Topr
Symbol
Min.*1, *2
Max.
Unit
Test Conditions
SCL, SDAinput rise time
tSr
—
1000
ns
Figure 6.25
SCL, SDA input fall time
tSf
—
300
ns
SCL, SDA input spike pulse removal time
tSP
0
4 × tIICcyc
ns
Item
Simple IIC
(Standard-mode)
Simple IIC
(Fast-mode)
Data input setup time
tSDAS
250
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb
—
400
pF
SCL, SDA input rise time
tSr
20 + 0.1Cb
300
ns
SCL, SDA input fall time
tSf
20 + 0.1Cb
300
ns
SCL, SDA input spike pulse removal time
tSP
0
4 × tIICcyc
ns
Data input setup time
tSDAS
100
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb
—
400
pF
Note 1. The value in parentheses is used when ICMR3.NF[1:0] are set to 11b while a digital filter is enabled with ICFER.NFE = 1.
Note 2. Cb indicates the total capacity of the bus line.
PCLK
Port
tPRW
Figure 6.12
I/O port Input Timing
PCLKA
Input capture
input
Figure 6.13
tTICW
MTU3 Input/Output Timing
ICLK
MTCLKA to
MTCLKD
tTCKWL
Figure 6.14
tTCKWH
MTU3 Clock Input Timing
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 164 of 186
RX63T Group
6. Electrical Characteristics [64- and 48-Pin Versions]
PCLKA
Input Capture
input
Figure 6.15
tGTICW
GPT Input/Output Timing
PCLK
POEn# input
tPOEW
Figure 6.16
POE3# Input Timing
tSCKW
tSCKr
tSCKf
SCKn
(n = 0, 1, 12)
tScyc
Figure 6.17
SCK Clock Input Timing
SCKn
tTXD
TxDn
tRXS tRXH
RxDn
n = 0, 1, 12
Figure 6.18
SCI Input/Output Timing: Clock Synchronous Mode
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 165 of 186
RX63T Group
6. Electrical Characteristics [64- and 48-Pin Versions]
PCLK
ADTRG0#
tTRGW
Figure 6.19
AD Converter External Trigger Input Timing
tSPCKr
tSPCKWH
VOH
RSPCKA
Master select
output
VOH
tSPCKf
VOH
VOL
VOH
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
VIH
VIH
RSPCKA
Slave serect input
tSPCKf
VIH
VIL
VIH
VIL
tSPCKWL
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Figure 6.20
RSPI Clock Timing and Simple SPI Clock Timing
tTD
SSLA3 to SSLA0
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
tSU
MISOA input
tH
MSB IN
tMODR, tMODF
MOSIA output
Figure 6.21
MSB OUT
DATA
tOH
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
RSPI Timing (Master, CPHA = 0) and Simple SPI Timing (Master, CKPH = 1)
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 166 of 186
RX63T Group
6. Electrical Characteristics [64- and 48-Pin Versions]
tTD
SSLA3 to SSLA0
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
tSU
MISOA input
tH
MSB IN
tOH
LSB IN
tOD
MOSIA output
Figure 6.22
DATA
MSB OUT
MSB IN
tMODR, tMODF
DATA
LSB OUT
IDLE
MSB OUT
RSPI Timing (Master, CPHA = 1) and Simple SPI Timing (Master, CKPH = 0)
tTD
SSLA0 input
tLEAD
tLAG
RSPCKA
CPOL = 0
input
RSPCKA
CPOL = 1
input
tSA
tOH
MISOA output
MSB OUT
tSU
MOSIA input
Figure 6.23
tOD
DATA
tREL
LSB OUT
tH
MSB IN
MSB IN
MSB OUT
tSODR, tSODF
DATA
LSB IN
MSB IN
RSPI Timing (Slave, CPHA = 0) and Simple SPI Timing (Slave, CKPH = 1)
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 167 of 186
RX63T Group
6. Electrical Characteristics [64- and 48-Pin Versions]
tTD
SSLA0 input
tLEAD
tLAG
RSPCKA
CPOL = 0
input
RSPCKA
CPOL = 1
input
tSA
tOH
tOD
LSB OUT
(Last data)
MISOA output
MSB OUT
tSU
LSB OUT
DATA
MSB OUT
tSODR, tSODF
MSB IN
MOSIA input
Figure 6.24
tH
tREL
DATA
LSB IN
MSB IN
RSPI Timing (Slave, CPHA = 1) and Simple SPI Timing (Slave, CKPH = 0)
VIH
SDA
VIL
tBUF
tSCLH
tSTAS
tSTAH
tSTOS
tSP
SCL
P *1
tSCLL
tSr
tSf
tSCL
tSDAS
tSDAH
Note 1. S, P, and Sr indicate the following conditions.
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 6.25
P *1
Sr *1
S *1
Test conditions
VIH = VCC × 0.7, VIL = VCC × 0.3
VOL = 0.6V, IOL = 6 mA
RIIC Bus Interface Input/Output Timing and Simple IIC Bus Interface Input/Output
Timing
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 168 of 186
RX63T Group
6.4
6. Electrical Characteristics [64- and 48-Pin Versions]
A/D Conversion Characteristics
Table 6.16
12-Bit A/D Conversion Characteristics
Conditions: VCC = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V,
AVCC0 = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0,
Ta = Topr
Item
min
Resolution
typ
max
Unit
Test Conditions
12
12
12
Bit
When the sample-and-hold
circuit is in use per pin
1.6
—
—
μs
Sampling by the sample-and-hold circuit in
30 states.
Sampling by the A/D converter in 20 states.
When the sample-and-hold
circuit is not in use per pin
1.0
—
—
μs
Sampling by the A/D converter in 20 states.
Analog input capacitance
—
—
6
pF
Integral nonlinearity error
—
—
±4.0
LSB
Offset error
—
—
±7.5
LSB
Full-scale error
—
—
±7.5
LSB
Conversion time *1
(ADCLK = 50 MHz)
Quantization error
Absol
ute
accur
acy
—
±0.5
—
LSB
Sample and hold circuit in use
—
—
±8.0
LSB
AVin = 0.25 to AVREFH–0.25
Sample and hold circuit not in use
—
—
±8.0
LSB
AVin = AVREFL to AVREFH
—
—
3.0
kΩ
Permissible signal source impedance
Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states
is indicated.
Table 6.17
Comparator Characteristics
Conditions: VCC = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V,
AVCC0 = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0,
Ta = Topr
Item
Symbol
Min
Typ
Max.
Unit
Analog input capacitance
Cin
—
—
6
pF
REFH pin offset voltage
Voff
—
—
5
mV
—
—
5
mV
1.7
—
AVcc – 0.3
V
0.3
—
AVcc – 1.7
V
REFL pin offset voltage
REFH input voltage range
Vin
REFL input voltage range
REFH reply time
tCR
—
—
0.5
μs
REFL reply time
tCF
—
—
0.5
μs
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Test Conditions
Page 169 of 186
RX63T Group
6.5
6. Electrical Characteristics [64- and 48-Pin Versions]
Power-on Reset Circuit and Voltage Detection Circuit Characteristics
Table 6.18
Power-on Reset Circuit and Voltage Detection Circuit Characteristics
Conditions: VCC = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V,
AVCC0 = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0,
Ta = Topr
Item
Voltage detection
level
Internal reset time
Symbol
Min.
Typ.
Max.
Unit
Power-on reset (POR)
VPOR
2.5
2.6
2.7
Voltage detection circuit (LVD0)
VDET0
2.7
2.8
2.9
Voltage detection circuit (LVD1)
VDET1
2.80
2.95
3.10
Voltage detection circuit (LVD2)
VDET2
2.80
2.95
3.10
Power-on reset (POR)
tPOR
—
4.6
Voltage detection circuit (LVD0)
tLVD0
—
4.6
Figure 6.27
Voltage detection circuit (LVD1)
tLVD1
—
0.9
Figure 6.28
Voltage detection circuit (LVD2)
tLVD2
—
0.9
Figure 6.29
time*1
tVOFF
200
—
Minimum VCC down
V
Test Conditions
Figure 6.26
Figure 6.27
ms
Figure 6.26
—
µs
Figure 6.26,
Figure 6.27
Response delay time
tdet
200
µs
Figure 6.26 to
Figure 6.29
LVD operation stabilization time (after LVD is enabled)
Td(E-A)
3
µs
Hysteresis width (LVD1 and LVD2)
V LVH
Figure 6.28
Figure 6.29
80
mV
Note 1. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, VDET1,
and VDET2 for the POR/ LVD.
tVOFF
VPOR
VCC
Internal reset signal
(active-low)
tdet
Figure 6.26
tPOR
tdet
tdet
tPOR
Power-on Reset Timing
tVOFF
VCC
Vdet0
Internal reset signal
(active-low)
tdet
Figure 6.27
tLVD0
Voltage Detection Circuit Timing (Vdet0)
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 170 of 186
RX63T Group
6. Electrical Characteristics [64- and 48-Pin Versions]
tVOFF
VCC
VLVH
Vdet1
LVD1E
Td(E-A)
LVD1
Comparator output
LVD1CMPE
LVD1MON
Internal reset signal
(active-low)
When LVD1RN = L
tdet
tdet
tLVD1
When LVD1RN = H
tLVD1
Figure 6.28
Voltage Detection Circuit Timing (Vdet1)
tVOFF
VCC
VLVH
Vdet2
LVD2E
Td(E-A)
LVD2
Comparator output
LVD2CMPE
LVD2MON
Internal reset signal
(active-low)
When LVD2RN = L
tdet
tdet
tLVD2
When LVD2RN = H
tLVD2
Figure 6.29
Voltage Detection Circuit Timing (Vdet2)
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 171 of 186
RX63T Group
6.6
6. Electrical Characteristics [64- and 48-Pin Versions]
Oscillation Stop Detection Circuit Characteristics
Table 6.19
Oscillation Stop Detection Circuit Characteristics
Conditions: VCC = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V, AVCC0 = 3.0 to 3.6 V,
VREFH0 = 3.0 V to AVCC0, Ta = Topr
Item
Detection time
Symbol
Min.
Typ.
Max.
Unit
tdr
—
—
1.0
ms
Test Conditions
Figure 6.30
Main clock
tdr
OSTDSR.OSTDF
Low-speed
clock
ICLK
Figure 6.30
Oscillation Stop Detection Timing
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 172 of 186
RX63T Group
6.7
6. Electrical Characteristics [64- and 48-Pin Versions]
ROM (Flash Memory for Code Storage) Characteristics
Table 6.20
ROM (Flash Memory for Code Storage) Characteristics (1)
Condition: VCC = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V
AVCC0 = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0,
Temperature range for the programming/erasure operation: Ta = Topr. Ta is common to conditions 1 to 3.
Item
Reprogram/erase
Symbol
cycle*1
Data hold time
Min.
Typ.
Max.
Unit
Test Conditions
Npec
1000
—
—
Times
tDRP
30*2
—
—
Year
Ta = +85°C
Note 1. Definition of reprogram/erase cycle:
The reprogram/erase cycle is the number of erasing for each block. When the reprogram/erase cycle is n times (n = 1000),
erasing can be performed n times for each block. For instance, when 128-byte programming is performed 16 times for different
addresses in 2-Kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address for several times as one erasing is not enabled (overwriting is prohibited).
Note 2. The value is obtained from the reliability test.
Table 6.21
ROM (Flash Memory for Code Storage) Characteristics (2)
Conditions: VCC = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V,
AVCC0 = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0,
Temperature range for the programming/erasure operation: Ta = Topr. Ta is common to conditions 1 to 3.
Item
Programming time
Erasure time
Symbol
min
typ
max
Unit
128 bytes
tP128
—
1
10
ms
4 Kbytes
tP4K
—
23
50
ms
16 Kbytes
tP16K
—
90
200
ms
128 bytes
tP128
—
1.2
12
ms
4 Kbytes
tP4K
—
27.6
60
ms
16 Kbytes
tP16K
—
108
240
ms
4 Kbytes
tE4K
—
25
60
ms
16 Kbytes
tE16K
—
100
240
ms
4 Kbytes
tE4K
—
30
72
ms
16 Kbytes
tE16K
—
120
288
ms
Suspend delay time during programming
tSPD
—
—
120
μs
First suspend delay time during erasing (in
suspend priority mode)
tSESD1
—
—
120
μs
Second suspend delay time during
erasing (in suspend priority mode)
tSESD2
—
—
1.7
ms
Suspend delay time during erasing (in
erasure priority mode)
tSEED
—
—
1.7
ms
FCU reset time
tFCUR
35
—
—
μs
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Test Conditions
FCLK = 50MHz
NPEC ≤ 100
FCLK=50MHz
NPEC > 100
FCLK=50MHz
NPEC ≤ 100
FCLK=50MHz
NPEC > 100
Figure 6.31
FCLK = 50MHz
Page 173 of 186
RX63T Group
6.8
6. Electrical Characteristics [64- and 48-Pin Versions]
E2 DataFlash Characteristic
E2 DataFlash (Flash Memory for Data Storage) Characteristics (1)
Table 6.22
Conditions: VCC = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V
AVCC0 = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0
Temperature range for the programming/erasure operation: Ta = Topr. Ta is common to conditions 1 to 3.
Item
Reprogram/erase
Symbol
cycle*1
Data hold time
Min.
Typ.
Max.
Unit
Test Conditions
NDPEC
100000
—
—
Times
tDDRP
30*2
—
—
Year
Ta = +85°C
Note 1. Definition of reprogram/erase cycle:
The reprogram/erase cycle is the number of erasing for each block. When the reprogram/erase cycle is n times (n = 1000),
erasing can be performed n times for each block. For instance, when 128-byte programming is performed 16 times for different
addresses in 2-Kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address for several times as one erasing is not enabled (overwriting is prohibited).
Note 2. The value is obtained from the reliability test.
Table 6.23
E2 DataFlash (Flash Memory for Data Storage) Characteristics (2)
Conditions: VCC = 2.7 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V,
AVCC0 = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0,
Ta = Topr
Item
Symbol
min
typ
max
Unit
Test Condition
Programming time
2 bytes
tDP2
—
0.25
2
ms
FCLK = 50 MHz
Erasure time
32 bytes
tDE32
—
2
20
ms
FCLK = 50 MHz
NDPEC ≤ 100
32 bytes
tDE32
—
4
20
ms
FCLK = 50 MHz
NDPEC > 100
2 bytes
tDBC2
—
—
30
μs
FCLK = 50 MHz
Suspend delay time during programming
tDSPD
—
—
120
μs
First suspend delay time during erasing (in
suspend priority mode)
tDSESD1
—
—
120
μs
Figure 6.31
PCLKB = 50 MHz
Second suspend delay time during
erasing (in suspend priority mode)
tDSESD2
—
—
300
μs
Suspend delay time during erasing (in
erasure priority mode)
tDSEED
—
—
300
μs
Blank check time
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 174 of 186
RX63T Group
6. Electrical Characteristics [64- and 48-Pin Versions]
• Suspension during programming
FCU command
Program
Suspend
tSPD
FSTATR0.FRDY
Ready
Programming pulse
Not Ready
Ready
Programming
• Suspension during erasure in suspend priority mode
FCU command
Erase
Suspend
Resume
Suspend
tSESD1
FSTATR0.FRDY
Ready
Erasure pulse
Not Ready
tSESD2
Ready
Erasing
Not Ready
Erasing
• Suspension during erasure in erasure priority mode
FCU command
Erase
Suspend
tSEED
FSTATR0.FRDY
Ready
Erasure pulse
Figure 6.31
Not Ready
Ready
Erasing
Flash Memory Program/Erase Suspend Timing
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 175 of 186
RX63T Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
Information on the latest version of the package dimensions or mountings has been displayed in “Packages” on Renesas
Electronics Corporation website.
JEITA Package Code
P-LQFP144-20x20-0.50
RENESAS Code
PLQP0144KA-A
Previous Code
144P6Q-A / FP-144L / FP-144LV
MASS[Typ.]
1.2g
HD
*1
D
108
73
109
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
72
bp
c
HE
Reference Dimension in Millimeters
Symbol
*2
E
c1
b1
36
A
1
ZD
Index mark
c
37
A2
144
ZE
Terminal cross section
F
A1
S
L
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
L1
*3
e
y S
bp
x
Detail F
e
x
y
ZD
ZE
L
L1
Min Nom Max
19.9 20.0 20.1
19.9 20.0 20.1
1.4
21.8 22.0 22.2
21.8 22.0 22.2
1.7
0.05 0.1 0.15
0.17 0.22 0.27
0.20
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.10
1.25
1.25
0.35 0.5 0.65
1.0
Figure A 144-Pin LQFP (PLQP0144KA-A)
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 176 of 186
RX63T Group
Appendix 1. Package Dimensions
JEITA Package Code
P-LQFP120-16x16-0.50
RENESAS Code
PLQP0120KA-A
Previous Code
⎯
MASS[Typ.]
0.9g
HD
*1
D
61
90
60
91
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
bp
c
c1
HE
*2
E
b1
Reference
Symbol
ZE
Terminal cross section
120
31
1
30
Index mark
ZD
A1
θ
C
A
A2
F
S
y S
e
*3
bp
L
L1
×M
Detail F
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
θ
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min
Nom
Max
15.9
15.9
16.0
16.0
1.4
18.0
18.0
16.1
16.1
17.8
17.8
18.2
18.2
1.7
0.15
0.27
0.1
0.22
0.20
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.08
0.75
0.75
0.35 0.5 0.65
1.0
0.05
0.17
Figure B 120-Pin LQFP (PLQP0120KA-A)
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 177 of 186
RX63T Group
Appendix 1. Package Dimensions
JEITA Package Code
P-LQFP112-20x20-0.65
RENESAS Code
PLQP0112JA-A
Previous Code
FP-112E/FP-112EV
MASS[Typ.]
1.2g
HD
*1
D
57
84
85
56
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
bp
c
Reference
Symbol
*2
E
HE
c1
b1
ZE
Terminal cross section
112
29
c
F
A
28
Index mark
ZD
A2
1
A1
θ
S
e
y S
L
L1
*3
bp
× M
Detail F
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
θ
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
19.9 20.0 20.1
19.9 20.0 20.1
1.4
21.8 22.0 22.2
21.8 22.0 22.2
1.7
0.05 0.1 0.15
0.27 0.32 0.37
0.30
0.09 0.145 0.20
0.125
0°
8°
0.65
0.13
0.10
1.225
1.225
0.35 0.5 0.65
1.0
Figure C 112-Pin LQFP (PLQP0112JA-A)
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 178 of 186
RX63T Group
Appendix 1. Package Dimensions
JEITA Package Code
P-LQFP100-14x14-0.50
RENESAS Code
PLQP0100KB-A
Previous Code
100P6Q-A / FP-100U / FP-100UV
MASS[Typ.]
0.6g
HD
*1
D
51
75
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
50
76
bp
c1
Reference Dimension in Millimeters
Symbol
c
E
*2
HE
b1
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
100
26
1
ZE
Terminal cross section
25
Index mark
ZD
F
y S
e
*3
bp
A1
c
A
A2
S
L
x
L1
Detail F
e
x
y
ZD
ZE
L
L1
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.08
1.0
1.0
0.35 0.5 0.65
1.0
Figure D 100-Pin LQFP (PLQP0100KB-A)
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 179 of 186
RX63T Group
Appendix 1. Package Dimensions
JEITA Package Code
P-LQFP64-10x10-0.50
RENESAS Code
PLQP0064KB-A
Previous Code
64P6Q-A / FP-64K / FP-64KV
MASS[Typ.]
0.3g
HD
*1
D
48
33
49
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
32
bp
64
1
c1
Terminal cross section
ZE
17
Reference Dimension in Millimeters
Symbol
c
E
*2
HE
b1
16
Index mark
ZD
c
A
*3
A1
y S
e
A2
F
S
bp
L
x
L1
Detail F
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
e
x
y
ZD
ZE
L
L1
Min Nom Max
9.9 10.0 10.1
9.9 10.0 10.1
1.4
11.8 12.0 12.2
11.8 12.0 12.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.08
1.25
1.25
0.35 0.5 0.65
1.0
Figure E 64-Pin LQFP (PLQP0064KB-A)
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 180 of 186
RX63T Group
Appendix 1. Package Dimensions
JEITA Package Code
P-LQFP48-7x7-0.50
RENESAS Code
PLQP0048KB-A
Previous Code
48P6Q-A
MASS[Typ.]
0.2g
HD
*1
D
36
25
37
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
24
bp
c
c1
*2
E
HE
b1
Reference Dimension in Millimeters
Symbol
48
13
1
ZE
Terminal cross section
12
c
A
F
A2
Index mark
ZD
S
A1
L
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
e
*3
bp
Detail F
x
8.8
8.8
0
0.17
0.09
0°
L1
y S
Min
6.9
6.9
e
x
y
ZD
ZE
L
L1
0.35
Nom Max
7.0 7.1
7.0 7.1
1.4
9.0 9.2
9.0 9.2
1.7
0.1 0.2
0.22 0.27
0.20
0.145 0.20
0.125
8°
0.5
0.08
0.10
0.75
0.75
0.5 0.65
1.0
Figure F 48-Pin LQFP (PLQP0048KB-A)
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 181 of 186
REVISION HISTORY
RX63T Group
REVISION HISTORY
REVISION HISTORY
Rev.
1.00
2.00
2.10
Date
Page
RX63T Group Datasheet
Description
Summary
Aug 28, 2012 —
First Edition issued
Mar 11, 2013 Features
1
Changed
1. Overview
2
1.1 Outline of Specifications, description changed
2 to 8
Table 1.1 Outline of Specifications, changed
9
Table 1.2 Comparison of Functions for Different Packages, changed
10 to 12
Table 1.3 List of Products, changed
12
Figure 1.1 How to Read the Product Part Number, changed
13
Figure 1.2 Block Diagram, changed
14 to 18
Table 1.4 Pin Functions, changed
19
Figure 1.3 Pin Assignment (144-Pin LQFP), added
20
Figure 1.4 Pin Assignment (120-Pin LQFP), added
21
Figure 1.5 Pin Assignment (112-Pin LQFP), added
22
Figure 1.6 Pin Assignment (100-Pin LQFP), added
23
Figure 1.7 Pin Assignment (64-Pin LQFP), notes changed
24
Figure 1.8 Pin Assignment (48-Pin LQFP), notes changed
25 to 28
Table 1.5 List of Pins and Pin Functions (144-Pin LQFP), added
29 to 32
Table 1.6 List of Pins and Pin Functions (120-Pin LQFP), added
33 to 36
Table 1.7 List of Pins and Pin Functions (112-Pin LQFP), added
37 to 39
Table 1.8 List of Pins and Pin Functions (100-Pin LQFP), added
3. Address Space
49
Figure 3.1 Memory Map in Each Operating Mode, changed
50
3.2 External Address Space, added
4. I/O Registers
52
(3) Number of Access Cycles to I/O Registers, description changed
53 to 103
Table 4.1 List of I/O Registers (Address Order), changed
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
104 to 148
Added
6. Electrical Characteristics [64- and 48-Pin Versions]
149
Title changed
152
Table 6.6 Clock Timing, changed
158
Table 6.10 Timing of On-Chip Peripheral Modules (1), changed
160
Table 6.12 Timing of On-Chip Peripheral Modules (3), changed
170
6.6 Oscillation Stop Detection Circuit Characteristics, title changed
170
Table 6.18 Oscillation Stop Detection Circuit Characteristics, title changed
171
Table 6.19 ROM (Flash Memory for Code Storage) Characteristics (1), added
171
Table 6.20 ROM (Flash Memory for Code Storage) Characteristics (2), title and description
changed
172
Table 6.21 DataFlash (Flash Memory for Data Storage) Characteristics (1), added
172
Table 6.22 DataFlash (Flash Memory for Data Storage) Characteristics (2), title and description
changed
Appendix 1. Package Dimensions
174 to 177
Figure A 144-Pin LQFP (PLQP0144KA-A) to Figure D 100-Pin LQFP (PLQP0100KB-A), added
Sep 26, 2013 The RX63T Group and RX63T changed to this MCU
Features
1
Changed
1. Overview
2 to 8
Table 1.1 Outline of Specifications, changed, Note 1, added.
9
Table 1.2 Comparison of Functions for Different Packages, changed, Note 2, added.
10 to 14
Table 1.3 List of Products, changed, Note 1, added
15
Figure 1.1 How to Read the Product Part Number, changed
28 to 31
Table 1.5 List of Pins and Pin Functions (144-Pin LQFP), changed
32 to 35
Table 1.6 List of Pins and Pin Functions (120-Pin LQFP), changed
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 182 of 186
RX63T Group
Rev.
2.10
REVISION HISTORY
Description
Page
Summary
Sep 26, 2013 36 to 39
Table 1.7 List of Pins and Pin Functions (112-Pin LQFP), changed
40 to 42
Table 1.8 List of Pins and Pin Functions (100-Pin LQFP), changed
43 to 45
Table 1.9 List of Pins and Pin Functions (64-Pin LQFP), changed
46 to 47
Table 1.10 List of Pins and Pin Functions (48-Pin LQFP), changed
4. I/O Registers
56 to 103
Table 4.1 List of I/O Registers (Address Order), changed
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
104
Table 5.1 Absolute Maximum Ratings, changed
107
Table 5.4 DC Characteristics (3), Note 7, deleted
108
Table 5.6 Permissible Power Consumption, added
128
5.3.7 Timing of PWM Delay Generation Circuit, added
128
Table 42.21 Timing of the PWM Delay Generation Circuit, added
132
Figure 5.32 RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKB Division Ratio Set to a Value Other
Than 1/2) and Simple SPI Timing (Master, CKPH = 1), changed
133
Figure 5.34 RSPI Timing (Slave, CPHA = 0) and Simple SPI Timing (Slave, CKPH = 0), changed
134
Figure 5.35 RSPI Timing (Slave, CPHA = 1) and Simple SPI Timing (Slave, CKPH = 1), changed
6. Electrical Characteristics [64- and 48-Pin Versions]
149
Table 6.1 Absolute Maximum Ratings, changed
151
Table 6.3 DC Characteristics (2), Note 3, changed
152
Table 6.5 Permissible Power Consumption, added
Date
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Page 183 of 186
RX63T Group
REVISION HISTORY
Classifications
- Items with Technical Update document number: Changes according to the corresponding issued Technical Update
- Items without Technical Update document number: Minor changes that do not require Technical Update to be issued
Description
Page
Summary
2.20 Mar 31, 2016 1. Overview
2 to 8
Table 1.1 Outline of Specifications, Note 1 changed
10 to 13 Table 1.3 List of Products, changed
16
Table 1.4 Pin Functions, changed
27 to 30 Table 1.5 List of Pins and Pin Functions (144-Pin LQFP), changed
30
Table 1.5 List of Pins and Pin Functions (144-Pin LQFP), Note 1 added
31 to 34 Table 1.6 List of Pins and Pin Functions (120-Pin LQFP), changed
35 to 38 Table 1.7 List of Pins and Pin Functions (112-Pin LQFP), changed
38
Table 1.7 List of Pins and Pin Functions (112-Pin LQFP), Note 1 added
4. I/O Registers
54
(4) Notes on Sleep Mode and Mode Transition, added
55 to 102 Table 4.1 List of I/O Registers (Address Order), changed
Rev.
Date
5. Electrical Characteristics [144-, 120-, 112- and 100-Pin Versions]
103
Table 5.1 Absolute Maximum Ratings, changed
106
Table 5.4 DC Characteristics (3), changed
107
Table 5.5 Permissible Output Currents, changed
108
Table 5.6 Permissible Power Consumption (G version product only), title changed,
notes added
111
Table 5.9 Clock Timing, changed
112
Figure 5.6 LOCO, IWDTCLK Clock Oscillation Start Timing, title changed
112
Figure 5.6 LOCO, IWDTCLK Clock Oscillation Start Timing, changed
124
Table 5.16 Timing of On-Chip Peripheral Modules (1), changed
125
Table 5.16 Timing of On-Chip Peripheral Modules (2), changed
126
Table 5.16 Timing of On-Chip Peripheral Modules (3), changed
127
Table 5.16 Timing of On-Chip Peripheral Modules (4), changed
129
Table 5.17 Timing of the PWM Delay Generation Circuit
132
Figure 5.30 RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKB Division Ratio Set
to a Value Other Than 1/2) and Simple SPI Timing (Master, CKPH = 1), title and
figure changed
133
Figure 5.32 RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKB Division Ratio Set
to a Value Other Than 1/2) and Simple SPI Timing (Master, CKPH = 0), title
changed
134
Figure 5.34 RSPI Timing (Slave, CPHA = 0) and Simple SPI Timing (Slave, CKPH
= 1), title changed
135
Figure 5.35 RSPI Timing (Slave, CPHA = 1) and Simple SPI Timing (Slave, CKPH
= 0), title changed
136
Table 5.18 On-Chip USB Full-Speed Characteristics (DP and DM Pin Characteristics), Condition 1, 2 changed
143
Table 5.26 Power-on Reset Circuit and Voltage Detection Circuit Characteristics
(1), changed
6. Electrical Characteristics [64- and 48-Pin Versions]
150
Table 6.1 Absolute Maximum Ratings, changed
153
Table 6.5 Permissible Power Consumption (G version product only), title changed,
note added
154
Table 6.7 Clock Timing, changed
155
Figure 6.3 LOCO, IWDTCLK Clock Oscillation Start Timing, title changed
155
Figure 6.3 LOCO, IWDTCLK Clock Oscillation Start Timing, changed
161
Table 6.12 Timing of On-Chip Peripheral Modules (2), changed
170
Table 6.18 Power-on Reset Circuit and Voltage Detection Circuit Characteristics,
changed
R01DS0087EJ0220 Rev.2.20
Mar 31, 2016
Classification
TN-RX*-A086A/E
TN-RX*-A086A/E
TN-RX*-A140A/E
TN-RX*-A086A/E,
TN-RX*-A140A/E
TN-RX*-A086A/E
TN-RX*-A086A/E
TN-RX*-A097A/E
TN-RX*-A097A/E
TN-RX*-A097A/E
TN-RX*-A121A/E
TN-RX*-A121A/E
TN-RX*-A121A/E
TN-RX*-A086A/E
TN-RX*-A086A/E
TN-RX*-A086A/E
TN-RX*-A086A/E
TN-RX*-A097A/E
TN-RX*-A097A/E
TN-RX*-A097A/E
Page 184 of 186
General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas.
For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well
as any technical updates that have been issued for the products.
1. Handling of Unused Pins
Handle unused pins in accordance with the directions given under Handling of Unused Pins in the
manual.
¾ The input pins of CMOS products are generally in the high-impedance state. In operation with an
unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an
associated shoot-through current flows internally, and malfunctions occur due to the false
recognition of the pin state as an input signal become possible. Unused pins should be handled as
described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
¾ The states of internal circuits in the LSI are indeterminate and the states of register settings and
pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states of pins
are not guaranteed from the moment when power is supplied until the reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function
are not guaranteed from the moment when power is supplied until the power reaches the level at
which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
¾ The reserved addresses are provided for the possible future expansion of functions. Do not access
these addresses; the correct operation of LSI is not guaranteed if they are accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become stable.
When switching the clock signal during program execution, wait until the target clock signal has
stabilized.
¾ When the clock signal is generated with an external resonator (or from an external oscillator)
during a reset, ensure that the reset line is only released after full stabilization of the clock signal.
Moreover, when switching to a clock signal produced with an external resonator (or by an external
oscillator) while program execution is in progress, wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to a product with a different part number, confirm
that the change will not lead to problems.
¾ The characteristics of Microprocessing unit or Microcontroller unit products in the same group but
having a different part number may differ in terms of the internal memory capacity, layout pattern,
and other factors, which can affect the ranges of electrical characteristics, such as characteristic
values, operating margins, immunity to noise, and amount of radiated noise. When changing to a
product with a different part number, implement a system-evaluation test for the given product.
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
2.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
3.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
4.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or
5.
Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on
third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.
the product's quality grade, as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; and industrial robots etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical
implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it
in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses
incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
6.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or systems manufactured by you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
9.
Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or
regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the
development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the
contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics
products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
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Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
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Tel: +91-80-67208700, Fax: +91-80-67208777
Renesas Electronics Korea Co., Ltd.
12F., 234 Teheran-ro, Gangnam-Gu, Seoul, 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
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