Features
Datasheet
RX660 Group
R01DS0393EJ0100
Rev.1.00
Mar 18, 2022
Renesas MCUs
120-MHz 32-bit RX MCU, on-chip FPU, 709 CoreMark, Supportive of 5V power supply, up to 1-MB flash memory,
up to 128-KB SRAM, 32-KB data flash memory, various communications interfaces, including CAN FD,
12-bit A/D converter, 12-bit D/A converter, Analog comparator, RTC, Remote control signal receiver
Features
■ 32-bit RXv3 CPU core
Maximum operating frequency: 120 MHz
Capable of 709 CoreMark in operation at 120 MHz
A collective register bank save function is available.
Supports the memory protection unit (MPU)
JTAG and FINE (one-line) debugging interfaces
■ Low-power design and architecture
Operation from a single 2.7- to 5.5-V supply
Deep software standby mode with the RTC continuing to run
Four low-power modes
■ On-chip code flash memory
Supports versions with up to 1 Mbyte of ROM
No waiting for access in 120-MHz operation
User code is programmable by on-board or off-board programming.
Programming/erasing as background operations (BGOs)
■ On-chip data flash memory
32 Kbytes, reprogrammable up to 100,000 times
Programming/erasing as background operations (BGOs)
■ On-chip SRAM
128 Kbytes of SRAM (no wait states)
■ External address space
Buses for full-speed data transfer (maximum operating frequency of
40 MHz)
Four CS areas
8- or 16-bit bus space is selectable per area
■ Data transfer
DMACAa: 8 channels
DTCb: 1 channel
■ ELC
Module operation can be initiated by event signals without using
interrupts
Linked operation between modules is possible when the CPU is in
sleep mode
■ Reset and supply management
Power-on reset (POR)
Low voltage detection (LVD)
PLQP0144KA-B
PLQP0100KB-B
PLQP0080KB-B
PLQP0064KB-C
PLQP0048KB-B
20 × 20 mm, 0.5 mm pitch
14 × 14 mm, 0.5 mm pitch
12 × 12 mm, 0.5 mm pitch
10 × 10 mm, 0.5 mm pitch
7 × 7 mm, 0.5 mm pitch
■ Various communications interfaces
CAN FD: Compliant with ISO 11898-1:2015, standard frame and
extended frame (1 channel)
SCIk, SCIm, and SCIh with multiple functionalities (up to 13
channels)
Choose from among asynchronous mode, clock-synchronous mode,
smart-card interface mode, simplified SPI, simplified I2C, and
extended serial mode.
SCIm with 16-byte transmission and reception FIFOs (up to 2
channels)
The I2C bus interfaces (RIICa) for transfer at up to 400 kbps (fast
mode), capable of SMBus operation (2 channels)
RSPId (1 channel) for transfer at up to 30 Mbps
■ Up to 19 extended-function timers
16-bit MTU3a
8-bit TMRb (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2
channels)
■ 12-bit A/D converter
Single 12-bit unit (24 channels)
Self diagnosis, detection of analog input disconnection
■ Analog Comparator (CMPC): 4 channels
■ 12-bit D/A converter (R12DAb): 2 channels
Usable as a reference voltage for the analog comparator
■ Temperature sensor for measuring temperature
within the chip
■ Up to 134 pins for general I/O ports
5-V tolerance, open drain, input pull-up, switchable driving ability
■ Operating temp. range
D-version: –40C to +85C
G-version: –40C to +105C
■ Clock functions
The main clock oscillator is connectable to an 8- to 24-MHz external
crystal resonator and usable as the PLL reference clock.
A sub-clock oscillator connectable to a 32.768-kHz crystal resonator
Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20
MHz
120-kHz clock for the IWDTa
■ Real-time clock
Adjustment functions (30 seconds, leap year, and error)
Real-time clock counting and binary counting modes are selectable
Time capture in response to an event-signal input
■ Independent watchdog timer
120-kHz IWDT-dedicated on-chip oscillator clock operation
■ Useful functions for IEC60730 compliance
Oscillation-stoppage detection, functions for self-diagnosis and
detection of disconnection for the A/D converter, clock frequency
accuracy measurement circuit, independent watchdog timer, RAM
test-assisting function by DOC, and CRCA, etc.
Register write protection function that protects important registers
against overwriting
■ Remote control signal receiver
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 1 of 123
RX660 Group
1. Overview
1.
Overview
1.1
Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 give a comparison of the functions of products in different
packages.
Table 1.1 is an outline of maximum specifications, and the peripheral modules and the number of channels of the
modules differ depending on the number of pins on the package. For details, see Table 1.2, Comparison of Functions
for Different Packages.
Table 1.1
Outline of Specifications (1/8)
Classification
Module/Function
Description
CPU
CPU
Maximum operating frequency: 120 MHz
32-bit RX CPU (RXv3)
Minimum instruction execution time: One instruction per state (cycle of the system
clock)
Address space: 4-Gbyte linear
Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Ten 32-bit registers
Accumulator: Two 72-bit registers
113 instructions
Instructions installed as standard: 111
Basic instructions: 77
Single-precision floating-point operation instructions: 11
DSP instructions: 23
Instructions for register bank save function: 2
Addressing modes: 11
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32 × 32 → 64 bits
On-chip divider: 32 / 32 → 32 bits
Barrel shifter: 32 bits
FPU
Single precision (32-bit) floating point
Data types and floating-point exceptions in conformance with the IEEE754 standard
Register bank save
function
Fast collective saving and restoration of the values of CPU registers
16 save register banks
Code flash memory
Data flash memory
Capacity: 32 Kbytes
Programming/erasing: 100,000 times
Unique ID
12-byte unique ID for the device
RAM
Capacity: 128 Kbytes
120 MHz, no-wait access
Memory
Operating modes
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Capacity: 1 Mbyte/512 Kbytes
120 MHz, no-wait access
On-board programming: Four types
Off-board programming (parallel programmer mode)
Instructions are executable only for the program stored in the TM target area by using
the Trusted Memory (TM) function and protection against data reading is realized.
Operating modes by the mode-setting pins at the time of release from the reset state
Single-chip mode
Boot mode (for the SCI interface)
Boot mode (for the FINE interface)
User boot mode
Selection of operating mode by register setting
Single-chip mode
User boot mode
On-chip ROM disabled extended mode
On-chip ROM enabled extended mode
Endian selectable
Page 2 of 123
RX660 Group
Table 1.1
1. Overview
Outline of Specifications (2/8)
Classification
Module/Function
Description
Clock
Clock generation circuit
Main clock oscillator, sub-clock oscillator, low-speed/high-speed on-chip oscillator, PLL
frequency synthesizer, and IWDT-dedicated on-chip oscillator
The peripheral module clocks can be set to frequencies above that of the system clock.
Main-clock oscillation stoppage detection
Separate frequency-division and multiplication settings for the system clock (ICLK),
peripheral module clocks (PCLKA, PCLKB, PCLKD), flash-IF clock (FCLK) and external
bus clock (BCLK)
The CPU and other bus masters run in synchronization with the system clock (ICLK): Up
to 120 MHz
The following peripheral modules run in synchronization with PCLKA, which runs at up
to 120 MHz: MTU, RSPI, SCIs (SCI10 and SCI11), RSCI, and the ECC function control
registers in the CAN FD module.
Other peripheral modules run in synchronization with PCLKB: Up to 60 MHz
ADCLK in the S12AD runs in synchronization with PCLKD: Up to 60 MHz
Flash IF run in synchronization with the flash-IF clock (FCLK): Up to 60 MHz
Devices connected to the external bus run in synchronization with the external bus clock
(BCLK): Up to 40 MHz
Multiplication is possible with using the high-speed on-chip oscillator (HOCO) as a
reference clock of the PLL circuit
Reset
Nine types of reset
RES# pin reset: Generated when the RES# pin is driven low.
Power-on reset: Generated when the RES# pin is driven high and VCC = AVCC0 rises.
Voltage-monitoring 0 reset: Generated when VCC = AVCC0 falls.
Voltage-monitoring 1 reset: Generated when VCC = AVCC0 falls.
Voltage-monitoring 2 reset: Generated when VCC = AVCC0 falls.
Deep software standby reset: Generated in response to an interrupt to trigger release
from deep software standby.
Independent watchdog timer reset: Generated when the independent watchdog timer
underflows, or a refresh error occurs.
Watchdog timer reset: Generated when the watchdog timer underflows, or a refresh
error occurs.
Software reset: Generated by register setting.
Power-on reset
If the RES# pin is at the high level when power is supplied, an internal reset is generated.
After VCC = AVCC0 has exceeded the voltage detection level and the specified period
has elapsed, the reset is cancelled.
Voltage detection circuit (LVDA)
Monitors the voltage being input to the VCC pins and generates an internal reset or
internal interrupt in response to the voltage reaching a threshold.
Voltage detection circuit 0
Capable of generating an internal reset
The option-setting memory can be used to select enabling or disabling of the reset.
Voltage detection level: Selectable from two different levels
Voltage detection circuits 1 and 2
Voltage detection level: Selectable from five different levels
Digital filtering (1/2, 1/4, 1/8, and 1/16 LOCO frequency)
Capable of generating an internal reset
Two types of timing are selectable for release from reset
An internal interrupt can be requested.
Detection of voltage rising above and falling below thresholds is selectable.
Maskable or non-maskable interrupt is selectable
Voltage detection monitoring
Event linking
Low power
consumption
Low power consumption
function
Module stop function
Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software
standby mode
Interrupt
Interrupt controller
(ICUF)
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Peripheral function interrupts: 256 sources
External interrupts: 16 (pins IRQ0 to IRQ15)
Software interrupts: 2 sources
Non-maskable interrupts: 7 sources
Sixteen levels specifiable for the order of priority
Method of interrupt source selection:
The interrupt vectors consist of 256 vectors (128 sources are fixed. The remaining 133
vectors are selected from among the other 128 sources.)
Page 3 of 123
RX660 Group
Table 1.1
Classification
1. Overview
Outline of Specifications (3/8)
Module/Function
Description
External bus extension
The external address space can be divided into four areas (CS0 to CS3), each with
independent control of access settings.
Capacity of each area: 2 Mbytes (CS0 to CS3)
A chip-select signal (CS0# to CS3#) can be output for each area.
Each area is specifiable as an 8-, or 16-bit bus space.
The data arrangement in each area is selectable as little or big endian (only for data).
Bus format: Separate bus, multiplex bus
Wait control
Write buffer facility
DMA
DMA controller
(DMACAa)
8 channels
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software trigger, external interrupts, and interrupt requests from
peripheral functions
Data transfer controller
(DTCb)
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Request sources: External interrupts and interrupt requests from peripheral functions
Programmable I/O ports
I/O ports for the 144-pin LFQFP with no JTAG interface and no sub-clock oscillator
I/O pins: 133
Input pin: 1
Pull-up resistors: 133
Open-drain outputs: 133
5-V tolerance: 4
I/O ports for the 144-pin LFQFP with a sub-clock oscillator, but no JTAG interface
I/O pins: 131
Input pin: 1
Pull-up resistors: 131
Open-drain outputs: 131
5-V tolerance: 4
I/O ports for the 144-pin LFQFP with a JTAG interface, but no sub-clock oscillator
I/O pins: 132
Input pin: 1
Pull-up resistors: 132
Open-drain outputs: 132
5-V tolerance: 4
I/O ports for the 144-pin LFQFP with a JTAG interface and a sub-clock oscillator
I/O pins: 130
Input pin: 1
Pull-up resistors: 130
Open-drain outputs: 130
5-V tolerance: 4
I/O ports for the 100-pin LFQFP with no JTAG interface and no sub-clock oscillator
I/O pins: 91
Input pin: 1
Pull-up resistors: 91
Open-drain outputs: 91
5-V tolerance: 4
I/O ports for the 100-pin LFQFP with a sub-clock oscillator, but no JTAG interface
I/O pins: 89
Input pin: 1
Pull-up resistors: 89
Open-drain outputs: 89
5-V tolerance: 4
I/O ports for the 100-pin LFQFP with a JTAG interface, but no sub-clock oscillator
I/O pins: 90
Input pin: 1
Pull-up resistors: 90
Open-drain outputs: 90
5-V tolerance: 4
I/O ports
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Page 4 of 123
RX660 Group
Table 1.1
1. Overview
Outline of Specifications (4/8)
Classification
Module/Function
Description
I/O ports
Programmable I/O ports
I/O ports for the 100-pin LFQFP with a JTAG interface and a sub-clock oscillator
I/O pins: 88
Input pin: 1
Pull-up resistors: 88
Open-drain outputs: 88
5-V tolerance: 4
I/O ports for the 80-pin LFQFP with no sub-clock oscillator
I/O pins: 71
Input pin: 1
Pull-up resistors: 71
Open-drain outputs: 71
5-V tolerance: 4
I/O ports for the 80-pin LFQFP with a sub-clock oscillator
I/O pins: 69
Input pin: 1
Pull-up resistors: 69
Open-drain outputs: 69
5-V tolerance: 4
I/O ports for the 64-pin LFQFP with no sub-clock oscillator
I/O pins: 55
Input pin: 1
Pull-up resistors: 55
Open-drain outputs: 55
5-V tolerance: 2
I/O ports for the 64-pin LFQFP with a sub-clock oscillator
I/O pins: 53
Input pin: 1
Pull-up resistors: 53
Open-drain outputs: 53
5-V tolerance: 2
I/O ports for the 48-pin LFQFP
I/O pins: 39
Input pin: 1
Pull-up resistors: 39
Open-drain outputs: 39
5-V tolerance: 2
Event link controller (ELC)
Event signals such as interrupt request signals can be interlinked with the operation of
functions such as timer counting, eliminating the need for intervention by the CPU to
control the functions.
83 internal event signals can be freely combined for interlinked operation with
connected functions.
Event signals from peripheral modules can be used to change the states of output pins
(of ports B and E).
Changes in the states of pins (of ports B and E) being used as inputs can be interlinked
with the operation of peripheral modules.
Timers
8-bit timers (TMRb)
(8 bits × 2 channels) × 2 units
Select from among seven internal clock signals (PCLKB/1, PCLKB/2, PCLKB/8,
PCLKB/32, PCLKB/64, PCLKB/1024, PCLKB/8192) and one external clock signal
Capable of output of pulse trains with desired duty cycles or of PWM signals
The 2 channels of each unit can be cascaded to create a 16-bit timer
Generation of triggers for A/D converter conversion
Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12
Capable of generating operating clock for the remote control signal receiver (REMC)
Event linking by the ELC
Compare match timer
(CMT)
(16 bits × 2 channels) × 2 units
Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128,
PCLKB/512)
Event linking by the ELC
Compare match timer W
(CMTW)
(32 bits × 1 channel) × 2 units
Compare-match, input-capture input, and output-comparison output are available.
Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128,
PCLKB/512)
Interrupt requests can be output in response to compare-match, input-capture, and
output-comparison events.
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 5 of 123
RX660 Group
Table 1.1
1. Overview
Outline of Specifications (5/8)
Classification
Module/Function
Timers
Watchdog timer (WDTA) 14 bits × 1 channel
Select from among 6 counter-input clock signals (PCLKB/4, PCLKB/64, PCLKB/128,
PCLKB/512, PCLKB/2048, PCLKB/8192)
Description
Independent watchdog
timer (IWDTa)
14 bits × 1 channel
Counter-input clock: IWDT-dedicated on-chip oscillator
Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,
dedicated clock/128, dedicated clock/256
Window function: The positions where the window starts and ends are specifiable (the
window defines the timing with which refreshing is enabled and disabled).
Event linking by the ELC
Multifunction timer pulse
unit (MTU3a)
9 channels (16 bits × 8 channels, 32 bits × 1 channel)
Maximum of 28 pulse-input/output and 3 pulse-input possible
Select from among 14 counter-input clock signals for each channel (PCLKA/1, PCLKA/
2, PCLKA/4, PCLKA/8, PCLKA/16, PCLK/A32, PCLKA/64, PCLKA/256, PCLKA/1024,
MTCLKA, MTCLKB, MTCLKC, MTCLKD, MTIOC1A)
14 of the signals are available for channel 0, 11 are available for channels 1, 3, 4, 6 to 8,
12 are available for channel 2, and 10 are available for channel 5.
Input capture function
39 output compare/input capture registers
Counter clear operation (synchronous clearing by compare match/input capture)
Simultaneous writing to multiple timer counters (TCNT)
Simultaneous register input/output by synchronous counter operation
Buffered operation
Support for cascade-connected operation
43 interrupt sources
Automatic transfer of register data
Pulse output mode
Toggle/PWM/complementary PWM/reset-synchronized PWM
Complementary PWM output mode
Outputs non-overlapping waveforms for controlling 3-phase inverters
Automatic specification of dead times
PWM duty cycle: Selectable as any value from 0% to 100%
Delay can be applied to requests for A/D conversion.
Non-generation of interrupt requests at peak or trough values of counters can be
selected.
Double buffer configuration
Reset synchronous PWM mode
Three phases of positive and negative PWM waveforms can be output with desired duty
cycles.
Phase-counting mode: 16-bit mode (channels 1 and 2); 32-bit mode (channels 1 and 2)
Counter functionality for dead-time compensation
Generation of triggers for A/D converter conversion
A/D converter start triggers can be skipped
Digital filter function for signals on the input capture and external counter clock pins
Event linking by the ELC
Port output enable 3
(POE3a)
Control of the high-impedance state of the MTU waveform output pins
5 pins for input from signal sources: POE0#, POE4#, POE8#, POE10#, POE11#
Initiation on detection of short-circuited outputs (detection of simultaneous PWM output
to the active level)
Initiation by oscillation-stoppage detection or software
Additional programming of output control target pins is enabled
Realtime clock
(RTCC)*1
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Clock sources: Sub clock
Selection of the 32-bit binary count in time count/second unit possible
Clock and calendar functions
Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
Time capture function (up to 3 pins)
Event linking by the ELC
Page 6 of 123
RX660 Group
Table 1.1
1. Overview
Outline of Specifications (6/8)
Classification
Module/Function
Description
Communication
function
Serial communications
interfaces
(SCIk, SCIm, SCIh)
13 channels (SCIk: 10 channels + SCIh: 1 channel + SCIm: 2 channels)
SCIk, SCIh, SCIm
Serial communications modes: Asynchronous, clock synchronous, and smart-card
interface
Multi-processor function
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Start-bit detection: Level or edge detection is selectable.
Simple I2C
Simple SPI
9-bit transfer mode
Bit rate modulation
Double-speed mode
SCIk, SCIh
Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12
Event linking by the ELC (only on channel 5)
SCIh
Supports the serial communications protocol, which contains the start frame and
information frame
Supports the LIN format
SCIm
Data can be transmitted or received in sequence by the 16-byte FIFO buffers of the
transmission and reception unit
SCIk, SCIm
Data match detection
Adjustment of the timing of sampling of the RXD signals
Serial communications
interfaces (RSCI)
2 channels (RSCI10, RSCI11)
Serial communications modes: Asynchronous, clock synchronous, and smart-card
interface
Multi-processor function
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Start-bit detection: Level or edge detection is selectable.
Simple I2C
Simple SPI
9-bit transfer mode
Bit rate modulation
Double-speed mode
Supports the serial communications protocol, which contains the start frame and
information frame
Supports the LIN format
Data can be transmitted or received in sequence by the 32-byte FIFO buffers of the
transmission and reception unit
Manchester encoding is supported.
RSCI has some home bus system (HBS) functionality.
Data match detection
Adjustment of the timing of sampling of the RXD signals
I2C bus interface (RIICa) 2 channels
Communication formats
I2C bus format/SMBus format
Supports the multi-master
Event linking by the ELC
CAN FD module
(CANFD)*2
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
1 channel
Compliance with the ISO11898-1:2015 specification (standard frame and extended
frame)
Page 7 of 123
RX660 Group
Table 1.1
1. Overview
Outline of Specifications (7/8)
Classification
Module/Function
Description
Communication
function
Serial peripheral
interface (RSPId)
1 channel
RSPI transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),
and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four
lines) or clock-synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Switching between MSB first and LSB first
The number of bits in each transfer can be changed to any number of bits from 8 to 16,
or to 20, 24, or 32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with
each frame having up to 32 bits)
Transmit/receive data can be swapped in byte units
Buffered structure
Double buffers for both transmission and reception
RSPCK can be stopped with the receive buffer full for master reception.
Event linking by the ELC
Remote control signal
receiver (REMCa)
1 channel
Four pattern matching (header, data 0, data 1, and special data detection)
8-byte receive buffer per unit
The operating clock can be selected from among the PCLK, sub-clock, and TMR.
12-bit A/D converter (S12ADH)
12 bits (24 channels × 1 unit)
12-bit resolution
Minimum conversion time
0.9 µs per channel (when ADCLK operates at 60 MHz)
Operating mode
Scan mode (single scan mode, continuous scan mode, or 3 group scan mode)
Group A priority control (only for 3 group scan mode)
Sampling variable
Sampling time can be set up for each channel.
Conversion function in order of arbitrarily selected channels (Serial conversion of the
same channel cannot be allowed)
Double trigger mode (A/D conversion data duplicated)
Three ways to start A/D conversion
Software trigger, synchronous trigger (MTU, TMR, ELC), external trigger
Prioritization in group scanning can be controlled among group A, B, and C.
Digital comparison
Method: Comparison to detect voltages above or below thresholds and window
comparison
Measurement: Comparison of two results of conversion or comparison of a value in the
comparison register and a result of conversion
Self-diagnostic function
Detection of analog input disconnection
Event linking by the ELC
12-bit D/A converter (R12DAb)
Comparator C (CMPC)
4 channels
Function to compare the reference voltage and the analog input voltage
Digital filtering
Temperature sensor
1 channel
Relative precision: ± 1.0°C
The voltage of the temperature is converted into a digital value by the 12-bit A/D
converter.
Arithmetic unit for trigonometric functions
(TFU)
Sine, cosine, arctangent, x 2 + y 2
Simultaneous calculation of sine and cosine
Simultaneous calculation of arctangent and x 2 + y 2
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
2 channels
12-bit resolution
Output voltage: 0 V to AVCC0
Capable of providing as a reference voltage for comparator
Event linking by the ELC
Page 8 of 123
RX660 Group
Table 1.1
1. Overview
Outline of Specifications (8/8)
Classification
Module/Function
Description
Safety
Memory protection unit
(MPU)
Protection area: Eight areas (max.) can be specified in the range from 0000 0000h to
FFFF FFFFh.
Minimum protection unit: 16 bytes
Reading from, writing to, and enabling the execution access can be specified for each
area.
An access exception occurs when the detected access is not in the permitted area.
Trusted Memory (TM)
Function
Programs in the TM target area in the code flash memory are protected against reading
Instruction fetching by the CPU is the only form of access to these areas when the TM
function is enabled.
Register write protection
function
Protects important registers from being overwritten for in case a program runs out of
control.
CRC calculator (CRCA)
Generation of CRC codes for 8-/32-bit data
8-bit data
Selectable from the following three polynomials
X8 + X2 + X + 1, X16 + X15 + X2 + 1, X16 + X12 + X5 + 1
32-bit data
Selectable from the following two polynomials
X32 + X26 + X23 + X22 + X16+ X12 + X11 + X10 + X8+ X7 + X5 + X4 + X2+ X + 1,
X32 + X28 + X27 + X26 + X25 + X23 + X22 + X20 + X19 + X18 + X14 + X13 + X11 + X10 + X9 +
X8 + X6 + 1
Generation of CRC codes for use with LSB-first or MSB-first communications is
selectable
Main clock oscillation
stop detection
Main clock oscillation stop detection: Available
Clock frequency
accuracy measurement
circuit (CAC)
Monitors the clock output from the main clock oscillator, sub-clock oscillator, low- and
high-speed on-chip oscillators, IWDT-dedicated on-chip oscillator, and PCLKB, and
generates interrupts when the setting range is exceeded.
Data operation circuit
(DOCA)
This handles the comparison, addition, subtraction, comparison in terms of which is
larger or smaller, or window comparison of 32-bit values.
Operating frequency
Up to 120 MHz
Power supply voltage
VCC = 2.7 to 5.5V
AVCC0 = 3.0 to 5.5V (VCC ≤ AVCC0)
Operating temperature
D-version: –40 to +85°C
G-version: –40 to +105°C
Package
144-pin LFQFP (PLQP0144KA-B)
100-pin LFQFP (PLQP0100KB-B)
80-pin LFQFP (PLQP0080KB-B)
64-pin LFQFP (PLQP0064KB-C)
48-pin LFQFP (PLQP0048KB-B)
Debugging interface
JTAG*3 and FINE interfaces
Note 1. When the realtime clock is not used, initialize the registers in the realtime clock according to description in section 27.6.7,
Initialization Procedure When the Realtime Clock is Not to be Used in the User’s Manual: Hardware. The realtime clock cannot
be used in products with no sub-clock oscillator. At this time, disable the realtime clock according to description in section
27.6.7, Initialization Procedure When the Realtime Clock is Not to be Used in the User’s Manual: Hardware.
Note 2. The product part number differs according to whether or not the CANFD actually supports the CAN FD protocol.
Note 3. The product part number differs according to whether or not the MCU includes a JTAG interface.
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Page 9 of 123
RX660 Group
Table 1.2
1. Overview
Comparison of Functions for Different Packages
Products
Functions
RX660
Package 144-pin LFQFP
100-pin LFQFP
80-pin LFQFP
Code Flash Memory Capacity
1 Mbyte/512 Kbytes
Data Flash Memory Capacity
32 Kbytes
RAM
External bus width
DMA
DMA controller
16 bits
Available
Data transfer controller
Available
Address Space
Not available
2 Mbytes × 4 areas
Not available
Main clock oscillator (MOSC)
Available
Sub-clock oscillator (SOSC)
Timers
Available/Not available
Multi-function timer pulse unit 3
Ch. 0 to 8
Ch. 0 to 3
Compare match timer
Ch. 0 to 2
Ch. 0 to 3
Compare match timer W
Ch. 0 and 1
Available/Not available*1
Realtime clock
Watchdog timer
Available
Independent watchdog timer
Available
Serial communications interfaces (SCIk)
Ch. 0 to 9
Ch. 0 to 6, 8, and
9
Serial communications interfaces (SCIm)
Ch. 0, 1, 3 to 6,
8, and 9
Ch. 1, 3 to 6, 8, Ch. 1, 3 to 6, and
and 9
8
Ch. 10
Ch. 12
Serial communications interfaces (RSCI)
Ch. 10 and 11
I2C bus interfaces (RIIC)
Ch. 10
Ch. 0 to 2
Ch. 2
Serial peripheral interface (RSPI)
1 channel
CAN FD module (CANFD)
1 channel
Remote control signal receiver (REMC)
Ch. 0
12-bit A/D converter
24 channels
Comparator C
17 channels
14 channels
10 channels
1 pin
Not available
4 channels
Number of channels
Number of output pins
2 channels
2 pins
2 pins/1 pin*3
Temperature sensor
2 pins
Available
CRC calculator (CRCA)
Available
Data operation circuit (DOCA)
Available
Clock frequency accuracy measurement circuit (CAC)
Available
Event link controller (ELC)
Available
Off-board programming
Debugging
interfaces
Not available*1
Ch. 10 and 11
Serial communications interfaces (SCIh)
12-bit D/A
converter*2
Ch. 0 to 5, and 7
Available
8-bit timers
Analog
Not available
Ch. 0 to 7
Port output enable 3
Communication
function
48-pin LFQFP
128 Kbytes
External bus
Oscillator
64-pin LFQFP
JTAG interface
FINE interface
Available
Not available
Available/Not available
Not available
Available
Note 1. The realtime clock cannot be used in products with no sub-clock oscillator. Disable the realtime clock according to description in
section 27.6.7, Initialization Procedure When the Realtime Clock is Not to be Used in the User’s Manual: Hardware.
Note 2. The 2-channel analog output of the D/A converters can be used as the input of the comparators in all packages.
Note 3. Products with a JTAG interface that are also in the 100-pin LFQFP have a single D/A converter channel.
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 10 of 123
RX660 Group
1.2
1. Overview
List of Products
Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part no.
Table 1.3
Group
List of Products (1/3)
Part No.
RX660
R5F56609ADFB
(D-version)
R5F56609BDFB
Package
Code Flash
Memory
RAM
Capacity Capacity
(byte(s))
(byte(s))
Data Flash
Memory
Capacity
(byte(s)) JTAG
Sub-clock
oscillator
CANFD
Operating
temperature
(°C)
PLQP0144KA-B
1M
128 K
32 K
Not available
Not available
Available*1
–40 to +85
PLQP0144KA-B
1M
128 K
32 K
Not available
Not available
Available
–40 to +85
Available
Available*1
–40 to +85
R5F56609CDFB
PLQP0144KA-B
1M
128 K
32 K
Not available
R5F56609DDFB
PLQP0144KA-B
1M
128 K
32 K
Not available
Available
Available
–40 to +85
R5F56609EDFB
PLQP0144KA-B
1M
128 K
32 K
Available
Not available
Available*1
–40 to +85
R5F56609FDFB
PLQP0144KA-B
1M
128 K
32 K
Available
Not available
Available
–40 to +85
Available
Available*1
–40 to +85
R5F56609GDFB
PLQP0144KA-B
1M
128 K
32 K
Available
R5F56609HDFB
PLQP0144KA-B
1M
128 K
32 K
Available
Available
Available
–40 to +85
R5F56609ADFP
PLQP0100KB-B
1M
128 K
32 K
Not available
Not available
Available*1
–40 to +85
R5F56609BDFP
PLQP0100KB-B
1M
128 K
32 K
Not available
Not available
Available
–40 to +85
Available
Available*1
–40 to +85
R5F56609CDFP
PLQP0100KB-B
1M
128 K
32 K
Not available
R5F56609DDFP
PLQP0100KB-B
1M
128 K
32 K
Not available
Available
Available
–40 to +85
R5F56609EDFP
PLQP0100KB-B
1M
128 K
32 K
Available
Not available
Available*1
–40 to +85
R5F56609FDFP
PLQP0100KB-B
1M
128 K
32 K
Available
Not available
Available
–40 to +85
Available
Available*1
–40 to +85
R5F56609GDFP
PLQP0100KB-B
1M
128 K
32 K
Available
R5F56609HDFP
PLQP0100KB-B
1M
128 K
32 K
Available
Available
Available
–40 to +85
R5F56609ADFN
PLQP0080KB-B
1M
128 K
32 K
Not available
Not available
Available*1
–40 to +85
R5F56609BDFN
PLQP0080KB-B
1M
128 K
32 K
Not available
Not available
Available
–40 to +85
Available
Available*1
–40 to +85
R5F56609CDFN
PLQP0080KB-B
1M
128 K
32 K
Not available
R5F56609DDFN
PLQP0080KB-B
1M
128 K
32 K
Not available
Available
Available
–40 to +85
R5F56609ADFM
PLQP0064KB-C
1M
128 K
32 K
Not available
Not available
Available*1
–40 to +85
R5F56609BDFM
PLQP0064KB-C
1M
128 K
32 K
Not available
Not available
Available
–40 to +85
Available
Available*1
–40 to +85
R5F56609CDFM
PLQP0064KB-C
1M
128 K
32 K
Not available
R5F56609DDFM
PLQP0064KB-C
1M
128 K
32 K
Not available
Available
Available
–40 to +85
R5F56609ADFL
PLQP0048KB-B
1M
128 K
32 K
Not available
Not available
Available*1
–40 to +85
R5F56609BDFL
PLQP0048KB-B
1M
128 K
32 K
Not available
Not available
Available
–40 to +85
R5F56604ADFB
PLQP0144KA-B
512 K
128 K
32 K
Not available
Not available
Available*1
–40 to +85
R5F56604BDFB
PLQP0144KA-B
512 K
128 K
32 K
Not available
Not available
Available
–40 to +85
R5F56604CDFB
PLQP0144KA-B
512 K
128 K
32 K
Not available
Available
Available*1
–40 to +85
R5F56604DDFB
PLQP0144KA-B
512 K
128 K
32 K
Not available
Available
Available
–40 to +85
–40 to +85
R5F56604EDFB
PLQP0144KA-B
512 K
128 K
32 K
Available
Not available
Available*1
R5F56604FDFB
PLQP0144KA-B
512 K
128 K
32 K
Available
Not available
Available
–40 to +85
–40 to +85
R5F56604GDFB
PLQP0144KA-B
512 K
128 K
32 K
Available
Available
Available*1
R5F56604HDFB
PLQP0144KA-B
512 K
128 K
32 K
Available
Available
Available
–40 to +85
–40 to +85
R5F56604ADFP
PLQP0100KB-B
512 K
128 K
32 K
Not available
Not available
Available*1
R5F56604BDFP
PLQP0100KB-B
512 K
128 K
32 K
Not available
Not available
Available
–40 to +85
–40 to +85
–40 to +85
R5F56604CDFP
PLQP0100KB-B
512 K
128 K
32 K
Not available
Available
Available*1
R5F56604DDFP
PLQP0100KB-B
512 K
128 K
32 K
Not available
Available
Available
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 11 of 123
RX660 Group
Table 1.3
1. Overview
List of Products (2/3)
Package
Code Flash
Memory
RAM
Capacity Capacity
(byte(s))
(byte(s))
CANFD
Operating
temperature
(°C)
RX660
R5F56604EDFP
(D-version)
R5F56604FDFP
PLQP0100KB-B
512 K
128 K
32 K
Available
Not available
Available*1
–40 to +85
PLQP0100KB-B
512 K
128 K
32 K
Available
Not available
Available
–40 to +85
R5F56604GDFP
PLQP0100KB-B
512 K
128 K
32 K
Available
Available
Available*1
–40 to +85
R5F56604HDFP
PLQP0100KB-B
512 K
128 K
32 K
Available
Available
Available
–40 to +85
–40 to +85
Group
Part No.
Data Flash
Memory
Capacity
(byte(s)) JTAG
Sub-clock
oscillator
R5F56604ADFN
PLQP0080KB-B
512 K
128 K
32 K
Not available
Not available
Available*1
R5F56604BDFN
PLQP0080KB-B
512 K
128 K
32 K
Not available
Not available
Available
–40 to +85
–40 to +85
R5F56604CDFN
PLQP0080KB-B
512 K
128 K
32 K
Not available
Available
Available*1
R5F56604DDFN
PLQP0080KB-B
512 K
128 K
32 K
Not available
Available
Available
–40 to +85
–40 to +85
R5F56604ADFM
PLQP0064KB-C
512 K
128 K
32 K
Not available
Not available
Available*1
R5F56604BDFM
PLQP0064KB-C
512 K
128 K
32 K
Not available
Not available
Available
–40 to +85
R5F56604CDFM
PLQP0064KB-C
512 K
128 K
32 K
Not available
Available
Available*1
–40 to +85
R5F56604DDFM
PLQP0064KB-C
512 K
128 K
32 K
Not available
Available
Available
–40 to +85
R5F56604ADFL
PLQP0048KB-B
512 K
128 K
32 K
Not available
Not available
Available*1
–40 to +85
R5F56604BDFL
PLQP0048KB-B
512 K
128 K
32 K
Not available
Not available
Available
–40 to +85
RX660
R5F56609AGFB
(G-version)
R5F56609BGFB
PLQP0144KA-B
1M
128 K
32 K
Not available
Not available
Available*1
–40 to +105
PLQP0144KA-B
1M
128 K
32 K
Not available
Not available
Available
–40 to +105
R5F56609CGFB
PLQP0144KA-B
1M
128 K
32 K
Not available
Available
Available*1
–40 to +105
R5F56609DGFB
PLQP0144KA-B
1M
128 K
32 K
Not available
Available
Available
–40 to +105
R5F56609EGFB
PLQP0144KA-B
1M
128 K
32 K
Available
Not available
Available*1
–40 to +105
R5F56609FGFB
PLQP0144KA-B
1M
128 K
32 K
Available
Not available
Available
–40 to +105
R5F56609GGFB
PLQP0144KA-B
1M
128 K
32 K
Available
Available
Available*1
–40 to +105
R5F56609HGFB
PLQP0144KA-B
1M
128 K
32 K
Available
Available
Available
–40 to +105
R5F56609AGFP
PLQP0100KB-B
1M
128 K
32 K
Not available
Not available
Available*1
–40 to +105
R5F56609BGFP
PLQP0100KB-B
1M
128 K
32 K
Not available
Not available
Available
–40 to +105
R5F56609CGFP
PLQP0100KB-B
1M
128 K
32 K
Not available
Available
Available*1
–40 to +105
R5F56609DGFP
PLQP0100KB-B
1M
128 K
32 K
Not available
Available
Available
–40 to +105
R5F56609EGFP
PLQP0100KB-B
1M
128 K
32 K
Available
Not available
Available*1
–40 to +105
R5F56609FGFP
PLQP0100KB-B
1M
128 K
32 K
Available
Not available
Available
–40 to +105
R5F56609GGFP
PLQP0100KB-B
1M
128 K
32 K
Available
Available
Available*1
–40 to +105
R5F56609HGFP
PLQP0100KB-B
1M
128 K
32 K
Available
Available
Available
–40 to +105
R5F56609AGFN
PLQP0080KB-B
1M
128 K
32 K
Not available
Not available
Available*1
–40 to +105
R5F56609BGFN
PLQP0080KB-B
1M
128 K
32 K
Not available
Not available
Available
–40 to +105
R5F56609CGFN
PLQP0080KB-B
1M
128 K
32 K
Not available
Available
Available*1
–40 to +105
R5F56609DGFN
PLQP0080KB-B
1M
128 K
32 K
Not available
Available
Available
–40 to +105
R5F56609AGFM
PLQP0064KB-C
1M
128 K
32 K
Not available
Not available
Available*1
–40 to +105
R5F56609BGFM
PLQP0064KB-C
1M
128 K
32 K
Not available
Not available
Available
–40 to +105
R5F56609CGFM
PLQP0064KB-C
1M
128 K
32 K
Not available
Available
Available*1
–40 to +105
R5F56609DGFM
PLQP0064KB-C
1M
128 K
32 K
Not available
Available
Available
–40 to +105
R5F56609AGFL
PLQP0048KB-B
1M
128 K
32 K
Not available
Not available
Available*1
–40 to +105
R5F56609BGFL
PLQP0048KB-B
1M
128 K
32 K
Not available
Not available
Available
–40 to +105
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 12 of 123
RX660 Group
Table 1.3
1. Overview
List of Products (3/3)
Package
Code Flash
Memory
RAM
Capacity Capacity
(byte(s))
(byte(s))
CANFD
Operating
temperature
(°C)
RX660
R5F56604AGFB
(G-version)
R5F56604BGFB
PLQP0144KA-B
512 K
128 K
32 K
Not available
Not available
Available*1
–40 to +105
PLQP0144KA-B
512 K
128 K
32 K
Not available
Not available
Available
–40 to +105
R5F56604CGFB
PLQP0144KA-B
512 K
128 K
32 K
Not available
Available
Available*1
–40 to +105
R5F56604DGFB
PLQP0144KA-B
512 K
128 K
32 K
Not available
Available
Available
–40 to +105
–40 to +105
Group
Part No.
Data Flash
Memory
Capacity
(byte(s)) JTAG
Sub-clock
oscillator
R5F56604EGFB
PLQP0144KA-B
512 K
128 K
32 K
Available
Not available
Available*1
R5F56604FGFB
PLQP0144KA-B
512 K
128 K
32 K
Available
Not available
Available
–40 to +105
–40 to +105
R5F56604GGFB
PLQP0144KA-B
512 K
128 K
32 K
Available
Available
Available*1
R5F56604HGFB
PLQP0144KA-B
512 K
128 K
32 K
Available
Available
Available
–40 to +105
–40 to +105
R5F56604AGFP
PLQP0100KB-B
512 K
128 K
32 K
Not available
Not available
Available*1
R5F56604BGFP
PLQP0100KB-B
512 K
128 K
32 K
Not available
Not available
Available
–40 to +105
R5F56604CGFP
PLQP0100KB-B
512 K
128 K
32 K
Not available
Available
Available*1
–40 to +105
R5F56604DGFP
PLQP0100KB-B
512 K
128 K
32 K
Not available
Available
Available
–40 to +105
R5F56604EGFP
PLQP0100KB-B
512 K
128 K
32 K
Available
Not available
Available*1
–40 to +105
R5F56604FGFP
PLQP0100KB-B
512 K
128 K
32 K
Available
Not available
Available
–40 to +105
R5F56604GGFP
PLQP0100KB-B
512 K
128 K
32 K
Available
Available
Available*1
–40 to +105
R5F56604HGFP
PLQP0100KB-B
512 K
128 K
32 K
Available
Available
Available
–40 to +105
R5F56604AGFN
PLQP0080KB-B
512 K
128 K
32 K
Not available
Not available
Available*1
–40 to +105
R5F56604BGFN
PLQP0080KB-B
512 K
128 K
32 K
Not available
Not available
Available
–40 to +105
R5F56604CGFN
PLQP0080KB-B
512 K
128 K
32 K
Not available
Available
Available*1
–40 to +105
R5F56604DGFN
PLQP0080KB-B
512 K
128 K
32 K
Not available
Available
Available
–40 to +105
R5F56604AGFM
PLQP0064KB-C
512 K
128 K
32 K
Not available
Not available
Available*1
–40 to +105
R5F56604BGFM
PLQP0064KB-C
512 K
128 K
32 K
Not available
Not available
Available
–40 to +105
R5F56604CGFM
PLQP0064KB-C
512 K
128 K
32 K
Not available
Available
Available*1
–40 to +105
R5F56604DGFM
PLQP0064KB-C
512 K
128 K
32 K
Not available
Available
Available
–40 to +105
–40 to +105
–40 to +105
R5F56604AGFL
PLQP0048KB-B
512 K
128 K
32 K
Not available
Not available
Available*1
R5F56604BGFL
PLQP0048KB-B
512 K
128 K
32 K
Not available
Not available
Available
Note 1. Products with this part number support only CAN 2.0 protocol.
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 13 of 123
RX660 Group
R
5
F
1. Overview
5 6
6 0
9
A D
F B #3 0
Product identification code
Packing
#1, #3: Tray (LFQFP)
Package type, number of pins, and pin pitch
FB : LFQFP/144/0.50
FP : LFQFP/100/0.50
FN: LFQFP/80/0.50
FM: LFQFP/64/0.50
FL : LFQFP/48/0.50
D : Operating peripheral temperature: –40 to +85°C
G : Operating peripheral temperature: –40 to +105°C
A : Without JTAG interface, without sub-clock oscillator, only CAN 2.0 protocol supported
B : Without JTAG interface, without sub-clock oscillator, CAN FD protocol supported
C : Without JTAG interface, with sub-clock oscillator,
only CAN 2.0 protocol supported
D : Without JTAG interface, with sub-clock oscillator,
CAN FD protocol supported
E : With JTAG interface, without sub-clock oscillator,
only CAN 2.0 protocol supported
F : With JTAG interface, without sub-clock oscillator,
CAN FD protocol supported
G : With JTAG interface, with sub-clock oscillator, only
CAN 2.0 protocol supported
H : With JTAG interface, with sub-clock oscillator,
CAN FD protocol supported
Code flash memory, RAM, and data flash memory
capacity
9 : 1 Mbyte/128 Kbytes/32 Kbytes
4 : 512 Kbytes/128 Kbytes/32 Kbytes
Group name
RX660 Group
Series name
RX600 Series
Type of memory
F : Flash memory version
Renesas MCU
Renesas semiconductor product
Figure 1.1
How to Read the Product Part Number
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 14 of 123
RX660 Group
1.3
1. Overview
Block Diagram
Figure 1.2 shows a block diagram.
Data Flash
RSCI × 2ch
REMC
ELC
CAC
DOC
CRC
Port 0
MTU × 9ch
Port 1
POE3
Port 2
TFU
Clock
generation
circuit
Internal main bus 2
MPU
WDT
Port 6
IWDT
Port 7
RTC
Port 8
SCIk × 10ch
Port 9
SCIm × 2ch
Port A
SCIh × 1ch
DMAC
× 8ch
Port B
CANFD × 1ch
Port C
RSPI × 1ch
Port D
12-bit A/D converter × 24 ch
Port E
Temperature sensor
Port F
Comparator C × 4ch
Port H
12-bit D/A converter × 2ch
Port J
Interrupt controller
Data transfer controller
DMA controller
Bus controller
Clock frequency accuracy measurement circuit
CRC (cyclic redundancy check) calculator
Data operation circuit
Event link controller
Serial communications interface
Serial peripheral interface
I2C bus interface
Port K
Port L
BSC
Port N
CANFD:
MTU:
POE3:
TMR:
CMT:
CMTW:
WDT:
IWDT:
RTC:
REMC:
TFU:
Note:
Figure 1.2
Port 5
CMTW × 2ch
DTC
Internal main bus 1
RX CPU
ICU:
DTC
DMAC:
BSC:
CAC:
CRC:
DOC:
ELC:
SCIk, SCIh,
SCIm, RSCI:
RSPI:
RIIC:
Port 4
CMT × 4ch
RIIC × 2ch
Operand bus
ROM
Port 3
TMR × 2ch (unit 1)
ICU
Instruction bus
RAM
Internal peripheral buses 1 to 6
TMR × 2ch (unit 0)
CAN FD module
Multi-function timer pulse unit 3
Port output enable 3
8-bit timer
Compare match timer
Compare match timer W
Watchdog timer
Independent watchdog timer
Realtime clock
Remote control signal receiver
Arithmetic unit for trigonometric functions
Available functions depend on the product.
Block Diagram
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 15 of 123
RX660 Group
1.4
1. Overview
Pin Functions
Table 1.4 lists the pin functions.
Table 1.4
Pin Functions (1/5)
Classifications
Pin Name
I/O
Description
Digital power supply
VCC
Input
Power supply pin. Connect this pin to the system power supply.
Connect the pin to VSS via a 0.1-µF multilayer ceramic
capacitor. The capacitor should be placed close to the pin.
VCL
Input
Connect this pin to VSS via a 0.47-µF smoothing capacitor used
to stabilize the internal power supply. The capacitor should be
placed close to the pin.
VSS
Input
Ground pin. Connect it to the system power supply (0 V).
XTAL
Output
EXTAL
Input
Pins for a crystal resonator. An external clock signal can be
input through the EXTAL pin.
BCLK
Output
Outputs the external bus clock for external devices.
Input/output pins for the sub-clock oscillator. Connect a crystal
resonator between XCOUT and XCIN.
Clock
XCOUT
Output
XCIN
Input
Clock frequency accuracy
measurement
CACREF
Input
Reference clock input pin for the clock frequency accuracy
measurement circuit
Operating mode control
MD
Input
Pin for setting the operating mode. For details on how to use
this pin, see section 3.1, Operating Mode Types and Selection
in the User’s Manual: Hardware.
UB
Input
User boot mode enable pin
RES#
Input
Reset signal input pin. This LSI enters the reset state when this
signal goes low.
EMLE
Input
On-chip emulator enable pin while the JTAG pins are in use
If the on-chip emulator is to be used, drive this pin to the high
level. If the on-chip emulator is not to be used, drive this pin to
the low level.
FINED
I/O
Fine interface pin
TRST#
Input
TMS
Input
On-chip emulator pins. When the EMLE pin is driven high,
these pins are dedicated for the on-chip emulator.
TDI
Input
TCK
Input
TDO
Output
TRCLK
Output
This pin outputs the clock for synchronization with the trace
data.
TRSYNC
TRSYNC1
Output
These pins indicate that output from the TRDATA0 to TRDATA7
pins is valid.
TRDATA0
TRDATA1
TRDATA2
TRDATA3
TRDATA4
TRDATA5
TRDATA6
TRDATA7
Output
These pins output the trace information.
Address bus
A0 to A20
Output
Output pins for the address
Data bus
D0 to D15
I/O
Input and output pins for the bidirectional data bus
Multiplexed bus
A0/D0 to A15/D15
I/O
Address/data multiplexed bus
System control
On-chip emulator
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 16 of 123
RX660 Group
Table 1.4
1. Overview
Pin Functions (2/5)
Classifications
Pin Name
I/O
Description
Bus control
RD#
Output
Strobe signal which indicates that reading from the external bus
interface space is in progress
WR#
Output
Strobe signal which indicates that writing to the external bus
interface space is in progress, in 1-write strobe mode
WR0#, WR1#
Output
Strobe signals which indicate that either group of data bus pins
(D7 to D0 and D15 to D8) is valid in writing to the external bus
interface space, in byte strobe mode
BC0#, BC1#
Output
Strobe signals which indicate that either group of data bus pins
(D7 to D0 and D15 to D8) is valid in access to the external bus
interface space, in 1-write strobe mode
ALE
Output
Address latch signal when address/data multiplexed bus is
selected
WAIT#
Input
Input pin for wait request signals in access to the external space
CS0# to CS3#
Output
Select signals for CS areas
NMI
Input
Non-maskable interrupt request pin
IRQ0 to IRQ15, IRQ0-DS to
IRQ15-DS
Input
Maskable interrupt request pins
MTIOC0A, MTIOC0B,
MTIOC0C, MTIOC0D
I/O
The TGRA0 to TGRD0 input capture input/output compare
output/PWM output pins
MTIOC1A, MTIOC1B
I/O
The TGRA1 and TGRB1 input capture input/output compare
output/PWM output pins
MTIOC2A, MTIOC2B
I/O
The TGRA2 and TGRB2 input capture input/output compare
output/PWM output pins
MTIOC3A, MTIOC3B,
MTIOC3C, MTIOC3D
I/O
The TGRA3 to TGRD3 input capture input/output compare
output/PWM output pins
MTIOC4A, MTIOC4B,
MTIOC4C, MTIOC4D
I/O
The TGRA4 to TGRD4 input capture input/output compare
output/PWM output pins
MTIC5U, MTIC5V, MTIC5W
Input
The TGRU5, TGRV5, and TGRW5 input capture input/dead
time compensation input pins
MTIOC6A, MTIOC6B,
MTIOC6C, MTIOC6D
I/O
The TGRA6 to TGRD6 input capture input/output compare
output/PWM output pins
MTIOC7A, MTIOC7B,
MTIOC7C, MTIOC7D
I/O
The TGRA7 to TGRD7 input capture input/output compare
output/PWM output pins
MTIOC8A, MTIOC8B,
MTIOC8C, MTIOC8D
I/O
The TGRA8 to TGRD8 input capture input/output compare
output/PWM output pins
MTCLKA, MTCLKB,
MTCLKC, MTCLKD
Input
Input pins for external clock signals or for phase counting mode
clock signals
Port output enable 3
POE0#, POE4#, POE8#,
POE10#, POE11#
Input
Input pins for request signals to place the MTU in the high
impedance state
8-bit timer
TMO0 to TMO3
Output
Compare match output pins
TMCI0 to TMCI3
Input
Input pins for external clocks to be input to the counter
Interrupt
Multi-function timer pulse
unit 3
Compare match timer W
Serial communications
interface (SCIk)
TMRI0 to TMRI3
Input
Input pins for the counter reset
TIC0 to TIC3
Input
Input pins for CMTW
TOC0 to TOC3
Output
Output pins for CMTW
Asynchronous mode/clock synchronous mode
SCK0 to SCK9
I/O
Input/output pins for the clock
RXD0 to RXD9
Input
Input pins for received data
TXD0 to TXD9
Output
Output pins for transmitted data
CTS0# to CTS9#
Input
Input pins for controlling the start of transmission and reception
RTS0# to RTS9#
Output
Output pins for controlling the start of transmission and
reception
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 17 of 123
RX660 Group
Table 1.4
1. Overview
Pin Functions (3/5)
Classifications
Pin Name
I/O
Description
Serial communications
interface (SCIk)
Simple
SSCL0 to SSCL9
I/O
Input/output pins for the I2C clock
SSDA0 to SSDA9
I/O
Input/output pins for the I2C data
I2C
mode
Simple SPI mode
Serial communications
interface (SCIh)
SCK0 to SCK9
I/O
Input/output pins for the clock
SMISO0 to SMISO9
I/O
Input/output pins for slave transmission of data
SMOSI0 to SMOSI9
I/O
Input/output pins for master transmission of data
SS0# to SS9#
Input
Chip-select input pins
Asynchronous mode/clock synchronous mode
SCK12
I/O
Input/output pin for the clock
RXD12
Input
Input pin for received data
TXD12
Output
Output pin for transmitted data
CTS12#
Input
Input pin for controlling the start of transmission and reception
RTS12#
Output
Output pin for controlling the start of transmission and reception
SSCL12
I/O
Input/output pin for the I2C clock
SSDA12
I/O
Input/output pin for the I2C data
Simple I2C mode
Simple SPI mode
SCK12
I/O
Input/output pin for the clock
SMISO12
I/O
Input/output pin for slave transmission of data
SMOSI12
I/O
Input/output pin for master transmission of data
SS12#
Input
Chip-select input pin
Input
Input pin for received data
Extended serial mode
RXDX12
Serial communications
interface (SCIm)
TXDX12
Output
Output pin for transmitted data
SIOX12
I/O
Input/output pin for received or transmitted data
Asynchronous mode/clock synchronous mode
SCK10, SCK11
I/O
Input/output pins for the clock
RXD10, RXD11
Input
Input pins for received data
TXD10, TXD11
Output
Output pins for transmitted data
CTS10#, CTS11#
Input
Input pins for controlling the start of transmission and reception
RTS10#, RTS11#
Output
Output pins for controlling the start of transmission and
reception
SSCL10, SSCL11
I/O
Input/output pins for the I2C clock
SSDA10, SSDA11
I/O
Input/output pins for the I2C data
I/O
Input/output pins for the clock
Simple I2C mode
Simple SPI mode
SCK10, SCK11
SMISO10, SMISO11
I/O
Input/output pins for slave transmission of data
SMOSI10, SMOSI11
I/O
Input/output pins for master transmission of data
SS10#, SS11#
Input
Chip-select input pins
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 18 of 123
RX660 Group
Table 1.4
1. Overview
Pin Functions (4/5)
Classifications
Pin Name
I/O
Description
Serial communications
interface (RSCI)
Asynchronous mode/clock synchronous mode
SCK010, SCK011
I/O
Input/output pins for the clock
RXD010, RXD011
Input
Input pins for received data
TXD010, TXD011
Output
Output pins for transmitted data
CTS010#, CTS011#
Input
Input pins for controlling the start of transmission and reception
RTS010#, RTS011#
Output
Output pins for controlling the start of transmission and
reception
DE010, DE011
Output
DriveEnable output pins
SSCL010, SSCL011
I/O
Input/output pins for the I2C clock
SSDA010, SSDA011
I/O
Input/output pins for the I2C data
SCK010, SCK011
I/O
Input/output pins for the clock
SMISO010, SMISO011
I/O
Input/output pins for slave transmission of data
SMOSI010, SMOSI011
I/O
Input/output pins for master transmission of data
SS010#, SS011#
Input
Chip-select input pins
RXD010, RXD011
Input
Input pin for received data
TXD010, TXD011, TXDA011,
TXDB011
Output
Output pins for transmitted data
SCL0, SCL2
I/O
Input/output pins for clocks. Bus can be directly driven by the
N-channel open drain
SDA0, SDA2,
I/O
Input/output pins for data. Bus can be directly driven by the
N-channel open drain
CRX0
Input
Input pins
CTX0
Output
Output pins
RSPCKA
I/O
Input/output pin for the RSPI clock
MOSIA
I/O
Input/output pin for transmitting data from the RSPI master
MISOA
I/O
Input/output pin for transmitting data from the RSPI slave
SSLA0
I/O
Input/output pin to select the slave for the RSPI
SSLA1 to SSLA3
Output
Output pins to select the slave for the RSPI
AN000 to AN023
Input
Input pins for the analog signals to be processed by the A/D
converter
ADST0
Output
Output pin for A/D conversion status.
ADTRG0#
Input
Input pin for the external trigger signals that start the A/D
conversion
DA0, DA1
Output
Output pins for the analog signals to be processed by the D/A
converter
Simple I2C mode
Simple SPI mode
HBS support mode
I2C bus interface
CAN FD module
Serial peripheral interface
12-bit A/D converter
12-bit D/A converter
Comparator C
Realtime clock
Remote control signal
receiver (REMC)
COMP0 to COMP3
Output
Comparator detection result output pins
CVREFC0 to CVREFC3
Input
Analog reference voltage supply pins for comparator C
CMPC00, CMPC10, CMPC20,
CMPC30
Input
Analog input pins for CMPCn0 (n = 0 to 3)
RTCOUT
Output
Output pin for 1-Hz/64-Hz clock
RTCIC0 to RTCIC2
Input
Time capture event input pins
PMC0
Input
Input pin for external pulse signal
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 19 of 123
RX660 Group
Table 1.4
1. Overview
Pin Functions (5/5)
Classifications
Pin Name
I/O
Description
Analog power supply
AVCC0*1
Input
Analog voltage supply pin for the 12-bit A/D converter, 12-bit D/
A converter, comparator C, and temperature sensor. Connect
the pin to AVSS0 via a 0.1-µF multilayer ceramic capacitor. The
capacitor should be placed close to the pin.
AVSS0*1
Input
Analog ground pin for the 12-bit A/D converter, 12-bit D/A
converter, comparator C, and temperature sensor. Connect the
pin to AVCC0 via a 0.1-µF multilayer ceramic capacitor. The
capacitor should be placed close to the pin.
VREFH0
Input
Analog reference voltage supply pin for the 12-bit A/D
converter. Connect the pin to VREFL0 via a 0.1-µF multilayer
ceramic capacitor. The capacitor should be placed close to the
pin. If the 12-bit A/D converter is not to be used, set this pin to
its general-purpose function.
VREFL0
Input
Analog reference ground pin for the 12-bit A/D converter.
Connect the pin to VREFH0 via a 0.1-µF multilayer ceramic
capacitor. The capacitor should be placed close to the pin. If the
12-bit A/D converter is not to be used, set this pin to its generalpurpose function.
I/O ports
P00 to P07
I/O
8-bit input/output pins
P12 to P17
I/O
6-bit input/output pins
P20 to P27
I/O
8-bit input/output pins
P30 to P37
I/O
8-bit input/output pins (P35: input pin)
P40 to P47
I/O
8-bit input/output pins
P50 to P56
I/O
7-bit input/output pins
P60 to P67
I/O
8-bit input/output pins
P70 to P77
I/O
8-bit input/output pins
P80 to P83, P86, P87
I/O
6-bit input/output pins
P90 to P93
I/O
4-bit input/output pins
PA0 to PA7
I/O
8-bit input/output pins
PB0 to PB7
I/O
8-bit input/output pins
PC0 to PC7
I/O
8-bit input/output pins
PD0 to PD7
I/O
8-bit input/output pins
PE0 to PE7
I/O
8-bit input/output pins
PF5, PF6, PF7
I/O
3-bit input/output pins
PH0 to PH3, PH6, PH7
I/O
6-bit input/output pins
PJ1, PJ3 to PJ7
I/O
6-bit input/output pins
PK2 to PK5
I/O
4-bit input/output pins
PL0, PL1
I/O
2-bit input/output pins
PN6, PN7
I/O
2-bit input/output pins
Note:
Note the following regarding pin names. For details, see section 1.6, List of Pin and Pin Functions.
- When a letter “-A”, “-B”, etc. to indicate group membership is appended to the pin name, each pin is recommended to use in
combination with the pins in the same group.
- When the pin functions have “-DS” appended to their names, they can also be used as triggers for release from deep software
standby.
Note 1. When neither the 12-bit A/D converter nor temperature sensor is to be used, connect the AVCC0 pin to VCC, and the AVSS0
pin to VSS.
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 20 of 123
RX660 Group
Pin Assignments
PE3
PE4
PE5
PK4
P70
PK5
PE6
PE7
P65
P66
P67
PA0
PA1
PA2
PA3
VSS
PA4
VCC
PA5
PA6
PA7
PB0
P71
P72
PB1
PB2
PB3
PB4
PB5
PB6
PB7
P73
PL0
PC0
PL1
PC1
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
144-Pin LFQFP
(without JTAG Interface, without Sub-clock Oscillator)
107
1.5.1
108
1.5
1. Overview
109
72
P74
PE1
110
71
P75
PE0
111
70
PC2
P64
112
69
P76
P63
113
68
P62
114
67
P77
PC3
P61
PK3
115
66
PC4
116
65
P80
P60
117
64
P81
PK2
118
63
P82
PD7
119
62
PC5
PD6
120
61
PC6
PD5
121
60
PC7
PD4
122
59
PD3
123
58
VCC
P83
PD2
124
57
PD1
PD0
125
56
VSS
P50
55
P51
P93
127
54
P52
P92
128
53
P53
P91
129
52
P54
PF7
130
51
P55
P90
PF6
131
50
P56
132
49
PH0
P47
133
48
PH1
P46
134
47
PH2
P45
135
46
PH3
P44
136
45
P12
P43
137
44
P13
P42
138
43
P14
P41
PJ7/VREFL0
139
42
P15
140
41
P86
P40
PJ6/VREFH0
AVCC0
141
40
142
39
143
38
P16
P87
P17
P07
144
37
P20
Note:
Figure 1.3
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
PJ4
PJ3
VCL
PJ1
PN6/MD
PH7
PH6
RES#
P37/XTAL
VSS
P36/EXTAL
VCC
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
P23
P22
P21
11
PJ5
10
9
PF5
PN7
5
P04
P02
8
4
P03
7
3
P06
P01
P00
2
P05
6
1
AVSS0
14
RX660 Group
PLQP0144KA-B
(Top view)
126
36
PE2
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.5, List of Pin and Pin Functions (144-Pin LFQFP).
Pin Assignment (144-Pin LFQFP (without JTAG Interface, without Sub-clock Oscillator))
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 21 of 123
RX660 Group
PE3
PE4
PE5
PK4
P70
PK5
PE6
PE7
P65
P66
P67
PA0
PA1
PA2
PA3
VSS
PA4
VCC
PA5
PA6
PA7
PB0
P71
P72
PB1
PB2
PB3
PB4
PB5
PB6
PB7
P73
PL0
PC0
PL1
PC1
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
144-Pin LFQFP (without JTAG Interface, with Sub-clock Oscillator)
108
1.5.2
1. Overview
PE2
109
72
P74
PE1
110
71
P75
PE0
111
70
PC2
P64
112
69
P76
P63
113
68
P62
114
67
P77
PC3
P61
PK3
115
66
PC4
116
65
P80
P60
117
64
P81
PK2
118
63
P82
PD7
119
62
PC5
PD6
120
61
PC6
PD5
121
60
PC7
PD4
122
59
PD3
123
58
VCC
P83
PD2
124
57
PD1
PD0
125
56
VSS
P50
55
P51
P93
127
54
P52
P92
128
53
P53
P91
129
52
P54
PF7
130
51
P55
P90
PF6
131
50
P56
132
49
PH0
P47
133
48
PH1
P46
134
47
PH2
P45
135
46
PH3
P44
136
45
P12
P43
137
44
P13
P42
138
43
P14
P41
PJ7/VREFL0
139
42
P15
140
41
P86
P40
PJ6/VREFH0
AVCC0
141
40
142
39
143
38
P16
P87
P17
P07
144
37
P20
Note:
Figure 1.4
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
PJ4
PJ3
VCL
PJ1
PN6/MD
XCIN
XCOUT
RES#
P37/XTAL
VSS
P36/EXTAL
VCC
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
P23
P22
36
11
PJ5
P21
10
9
PF5
PN7
5
P04
P02
8
4
P03
7
3
P06
P01
P00
2
P05
6
1
AVSS0
14
RX660 Group
PLQP0144KA-B
(Top view)
126
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.5, List of Pin and Pin Functions (144-Pin LFQFP).
Pin Assignment (144-Pin LFQFP (without JTAG Interface, with Sub-clock Oscillator))
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 22 of 123
RX660 Group
PE3
PE4
PE5
PK4
P70
PK5
PE6
PE7
P65
P66
P67
PA0
PA1
PA2
PA3
VSS
PA4
VCC
PA5
PA6
PA7
PB0
P71
P72
PB1
PB2
PB3
PB4
PB5
PB6
PB7
P73
PL0
PC0
PL1
PC1
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
144-Pin LFQFP
(with JTAG Interface, without Sub-clock Oscillator)
108
1.5.3
1. Overview
PE2
109
72
P74
PE1
110
71
P75
PE0
111
70
PC2
P64
112
69
P76
P63
113
68
P62
114
67
P77
PC3
P61
PK3
115
66
PC4
116
65
P80
P60
117
64
P81
PK2
118
63
P82
PD7
119
62
PC5
PD6
120
61
PC6
PD5
121
60
PC7
PD4
122
59
PD3
123
58
VCC
P83
PD2
124
57
PD1
PD0
125
56
VSS
P50
55
P51
P93
127
54
P52
P92
128
53
P53
P91
129
52
P54
PF7
130
51
P55
P90
PF6
131
50
P56
132
49
PH0
P47
133
48
PH1
P46
134
47
PH2
P45
135
46
PH3
P44
136
45
P12
P43
137
44
P13
P42
138
43
P14
P41
PJ7/VREFL0
139
42
P15
140
41
P86
P40
PJ6/VREFH0
AVCC0
141
40
142
39
143
38
P16
P87
P17
P07
144
37
P20
Note:
Figure 1.5
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
PJ4
PJ3
VCL
PJ1
PN6/MD
PH7
PH6
RES#
P37/XTAL
VSS
P36/EXTAL
VCC
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
P23
P22
36
11
PJ5
P21
10
9
PF5
EMLE
5
P04
P02
8
4
P03
7
3
P06
P01
P00
2
P05
6
1
AVSS0
14
RX660 Group
PLQP0144KA-B
(Top view)
126
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.5, List of Pin and Pin Functions (144-Pin LFQFP).
Pin Assignment (144-Pin LFQFP (with JTAG Interface, without Sub-clock Oscillator))
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 23 of 123
RX660 Group
PE3
PE4
PE5
PK4
P70
PK5
PE6
PE7
P65
P66
P67
PA0
PA1
PA2
PA3
VSS
PA4
VCC
PA5
PA6
PA7
PB0
P71
P72
PB1
PB2
PB3
PB4
PB5
PB6
PB7
P73
PL0
PC0
PL1
PC1
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
144-Pin LFQFP (with JTAG Interface, with Sub-clock Oscillator)
108
1.5.4
1. Overview
109
72
P74
PE1
110
71
P75
PE0
111
70
PC2
P64
112
69
P76
P63
113
68
P62
114
67
P77
PC3
P61
PK3
115
66
PC4
116
65
P80
P60
117
64
P81
PK2
118
63
P82
PD7
119
62
PC5
PD6
120
61
PC6
PD5
121
60
PC7
PD4
122
59
PD3
123
58
VCC
P83
PD2
124
57
PD1
PD0
125
56
VSS
P50
55
P51
P93
127
54
P52
P92
128
53
P53
P91
129
52
P54
PF7
130
51
P55
P90
PF6
131
50
P56
132
49
PH0
P47
133
48
PH1
P46
134
47
PH2
P45
135
46
PH3
P44
136
45
P12
P43
137
44
P13
P42
138
43
P14
P41
PJ7/VREFL0
139
42
P15
140
41
P86
P40
PJ6/VREFH0
AVCC0
141
40
142
39
143
38
P16
P87
P17
P07
144
37
P20
Note:
Figure 1.6
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
PJ5
PJ4
PJ3
VCL
PJ1
PN6/MD
XCIN
XCOUT
RES#
P37/XTAL
VSS
P36/EXTAL
VCC
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
P23
P22
P21
10
9
PF5
EMLE
5
P04
P02
8
4
P03
7
3
P06
P01
P00
2
P05
6
1
AVSS0
14
RX660 Group
PLQP0144KA-B
(Top view)
126
36
PE2
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.5, List of Pin and Pin Functions (144-Pin LFQFP).
Pin Assignment (144-Pin LFQFP (with JTAG Interface, with Sub-clock Oscillator))
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 24 of 123
RX660 Group
PE3
PE4
PE5
PE6
PE7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
VSS
PB0
VCC
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PE2
76
50
PE1
77
49
PC2
PC3
PE0
78
48
PC4
PD7
79
47
PC5
PD6
80
46
PC6
PD5
81
45
PC7
PD4
82
44
P50
PD3
83
43
P51
PD2
84
42
P52
PD1
85
41
P53
PD0
86
40
P54
P47
87
39
P55
P46
88
38
PH0
P45
89
37
PH1
P44
90
36
PH2
P43
91
35
PH3
P42
92
34
P12
P41
93
33
P13
PJ7/VREFL0
94
32
P14
P40
95
31
P15
PJ6/VREFH0
96
30
P16
AVCC0
97
29
P17
P07
98
28
P20
AVSS0
99
27
P21
P05
100
26
P22
Note:
Figure 1.7
75
100-Pin LFQFP
(without JTAG Interface, without Sub-clock Oscillator)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P03
P04
PJ3
VCL
PJ1
PN6/MD
PH7
PH6
RES#
P37/XTAL
VSS
P36/EXTAL
VCC
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
P23
RX660 Group
PLQP0100KB-B
(Top view)
P06
1.5.5
1. Overview
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.6, List of Pin and Pin Functions (100-Pin LFQFP).
Pin Assignment (100-Pin LFQFP (without JTAG Interface, without Sub-clock Oscillator))
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 25 of 123
RX660 Group
PE3
PE4
PE5
PE6
PE7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
VSS
PB0
VCC
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PE2
76
50
PE1
77
49
PC2
PC3
PE0
78
48
PC4
PD7
79
47
PC5
PD6
80
46
PC6
PD5
81
45
PC7
PD4
82
44
P50
PD3
83
43
P51
PD2
84
42
P52
PD1
85
41
P53
PD0
86
40
P54
P47
87
39
P55
P46
88
38
PH0
P45
89
37
PH1
P44
90
36
PH2
P43
91
35
PH3
P42
92
34
P12
P41
93
33
P13
PJ7/VREFL0
94
32
P14
P40
95
31
P15
PJ6/VREFH0
96
30
P16
AVCC0
97
29
P17
P07
98
28
P20
AVSS0
99
27
P21
P05
100
26
P22
Note:
Figure 1.8
75
100-Pin LFQFP (without JTAG Interface, with Sub-clock Oscillator)
14
15
16
17
18
19
20
21
22
23
24
25
VCC
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
P23
9
XCOUT
13
8
XCIN
P36/EXTAL
7
PN6/MD
12
6
PJ1
VSS
5
VCL
11
4
PJ3
P37/XTAL
3
P04
10
2
RES#
1
P03
RX660 Group
PLQP0100KB-B
(Top view)
P06
1.5.6
1. Overview
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.6, List of Pin and Pin Functions (100-Pin LFQFP).
Pin Assignment (100-Pin LFQFP (without JTAG Interface, with Sub-clock Oscillator))
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 26 of 123
RX660 Group
PE3
PE4
PE5
PE6
PE7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
VSS
PB0
VCC
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PE2
76
50
PE1
77
49
PC2
PC3
PE0
78
48
PC4
PD7
79
47
PC5
PD6
80
46
PC6
PD5
81
45
PC7
PD4
82
44
P50
PD3
83
43
P51
PD2
84
42
P52
PD1
85
41
P53
PD0
86
40
P54
P47
87
39
P55
P46
88
38
PH0
P45
89
37
PH1
P44
90
36
PH2
P43
91
35
PH3
P42
92
34
P12
P41
93
33
P13
PJ7/VREFL0
94
32
P14
P40
95
31
P15
PJ6/VREFH0
96
30
P16
AVCC0
97
29
P17
P07
98
28
P20
AVSS0
99
27
P21
P05
100
26
P22
Note:
Figure 1.9
75
100-Pin LFQFP (with JTAG Interface, without Sub-clock Oscillator)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P06
P04
PJ3
VCL
PJ1
PN6/MD
PH7
PH6
RES#
P37/XTAL
VSS
P36/EXTAL
VCC
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
P23
RX660 Group
PLQP0100KB-B
(Top view)
EMLE
1.5.7
1. Overview
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.6, List of Pin and Pin Functions (100-Pin LFQFP).
Pin Assignment (100-Pin LFQFP (with JTAG Interface, without Sub-clock Oscillator))
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 27 of 123
RX660 Group
PE3
PE4
PE5
PE6
PE7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
VSS
PB0
VCC
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PE2
76
50
PE1
77
49
PC2
PC3
PE0
78
48
PC4
PD7
79
47
PC5
PD6
80
46
PC6
PD5
81
45
PC7
PD4
82
44
P50
PD3
83
43
P51
PD2
84
42
P52
PD1
85
41
P53
PD0
86
40
P54
P47
87
39
P55
P46
88
38
PH0
P45
89
37
PH1
P44
90
36
PH2
P43
91
35
PH3
P42
92
34
P12
P41
93
33
P13
PJ7/VREFL0
94
32
P14
P40
95
31
P15
PJ6/VREFH0
96
30
P16
AVCC0
97
29
P17
P07
98
28
P20
AVSS0
99
27
P21
P05
100
26
P22
Note:
Figure 1.10
75
100-Pin LFQFP (with JTAG Interface, with Sub-clock Oscillator)
14
15
16
17
18
19
20
21
22
23
24
25
VCC
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
P23
9
XCOUT
13
8
XCIN
P36/EXTAL
7
PN6/MD
12
6
PJ1
VSS
5
VCL
11
4
PJ3
P37/XTAL
3
P04
10
2
RES#
1
P06
RX660 Group
PLQP0100KB-B
(Top view)
EMLE
1.5.8
1. Overview
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.6, List of Pin and Pin Functions (100-Pin LFQFP).
Pin Assignment (100-Pin LFQFP (with JTAG Interface, with Sub-clock Oscillator))
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 28 of 123
RX660 Group
PE3
PE4
PE5
PA0
PA1
PA2
PA3
PA4
PA5
PA6
VSS
PB0
VCC
PB1
PB2
PB3
PB4
PB5
PB6
PB7
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PE2
61
40
PC2
PE1
62
39
PC3
PE0
63
38
PC4
PD2
64
37
PC5
PD1
65
36
PC6
PD0
66
35
PC7
P47
67
34
P54
P46
68
33
P55
P45
69
32
PH0
P44
70
31
PH1
P43
71
30
PH2
P42
72
29
PH3
P41
73
28
P12
PJ7/VREFL0
74
27
P13
P40
75
26
P14
PJ6/VREFH0
76
25
P15
AVCC0
77
24
P16
P07
78
23
P17
AVSS0
79
22
P20
P05
80
21
P21
Note:
Figure 1.11
60
80-Pin LFQFP (without Sub-clock Oscillator)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
P06
P04
VCL
PJ1
PN6/MD
PH7
PH6
RES#
P37/XTAL
VSS
P36/EXTAL
VCC
P35
P34
P32
P31
P30
P27
P26
RX660 Group
PLQP0080KB-B
(Top view)
P03
1.5.9
1. Overview
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.7, List of Pin and Pin Functions (80-Pin LFQFP).
Pin Assignment (80-Pin LFQFP (without Sub-clock Oscillator))
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 29 of 123
RX660 Group
PE3
PE4
PE5
PA0
PA1
PA2
PA3
PA4
PA5
PA6
VSS
PB0
VCC
PB1
PB2
PB3
PB4
PB5
PB6
PB7
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PE2
61
40
PC2
PE1
62
39
PC3
PE0
63
38
PC4
PD2
64
37
PC5
PD1
65
36
PC6
PD0
66
35
PC7
P47
67
34
P54
P46
68
33
P55
P45
69
32
PH0
P44
70
31
PH1
P43
71
30
PH2
P42
72
29
PH3
P41
73
28
P12
PJ7/VREFL0
74
27
P13
P40
75
26
P14
PJ6/VREFH0
76
25
P15
AVCC0
77
24
P16
P07
78
23
P17
AVSS0
79
22
P20
P05
80
21
P21
Note:
Figure 1.12
60
80-Pin LFQFP (with Sub-clock Oscillator)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
P06
P04
VCL
PJ1
PN6/MD
XCIN
XCOUT
RES#
P37/XTAL
VSS
P36/EXTAL
VCC
P35
P34
P32
P31
P30
P27
P26
RX660 Group
PLQP0080KB-B
(Top view)
P03
1.5.10
1. Overview
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.7, List of Pin and Pin Functions (80-Pin LFQFP).
Pin Assignment (80-Pin LFQFP (with Sub-clock Oscillator))
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 30 of 123
RX660 Group
Note:
Figure 1.13
VSS
PB0
VCC
PB1
PB3
PB5
PB6
PB7
39
38
37
36
35
34
33
PA3
43
40
PA1
44
PA4
PA0
45
PA6
PE5
46
41
PE4
47
42
PE3
48
64-Pin LFQFP (without Sub-clock Oscillator)
PE2
49
32
PC2
PE1
50
31
PC3
PE0
51
30
PC4
P47
52
29
PC5
P46
53
28
PC6
P45
54
27
PC7
P44
55
26
P54
P43
56
25
P55
P42
57
24
PH0
P41
58
23
PH1
PJ7/VREFL0
59
22
PH2
P40
60
21
PH3
PJ6/VREFH0
61
20
P14
AVCC0
62
19
P15
P07
63
18
P16
AVSS0
64
17
P17
12
13
14
15
16
P31
P30
P27
P26
8
VSS
P32
7
P37/XTAL
11
6
RES#
P35
5
PH6
9
4
PH7
10
3
PN6/MD
VCC
2
P36/EXTAL
1
P03
RX660 Group
PLQP0064KB-C
(Top view)
VCL
1.5.11
1. Overview
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.8, List of Pin and Pin Functions (64-Pin LFQFP).
Pin Assignment (64-Pin LFQFP (without Sub-clock Oscillator))
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 31 of 123
RX660 Group
Note:
Figure 1.14
VSS
PB0
VCC
PB1
PB3
PB5
PB6
PB7
39
38
37
36
35
34
33
PA3
43
40
PA1
44
PA4
PA0
45
PA6
PE5
46
41
PE4
47
42
PE3
48
64-Pin LFQFP (with Sub-clock Oscillator)
PE2
49
32
PC2
PE1
50
31
PC3
PE0
51
30
PC4
P47
52
29
PC5
P46
53
28
PC6
P45
54
27
PC7
P44
55
26
P54
P43
56
25
P55
P42
57
24
PH0
P41
58
23
PH1
PJ7/VREFL0
59
22
PH2
P40
60
21
PH3
PJ6/VREFH0
61
20
P14
AVCC0
62
19
P15
P07
63
18
P16
AVSS0
64
17
P17
12
13
14
15
16
P31
P30
P27
P26
8
VSS
P32
7
P37/XTAL
11
6
RES#
P35
5
XCOUT
9
4
XCIN
10
3
PN6/MD
VCC
2
P36/EXTAL
1
P03
RX660 Group
PLQP0064KB-C
(Top view)
VCL
1.5.12
1. Overview
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.8, List of Pin and Pin Functions (64-Pin LFQFP).
Pin Assignment (64-Pin LFQFP (with Sub-clock Oscillator))
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 32 of 123
RX660 Group
Note:
Figure 1.15
PA4
VSS
PB0
VCC
PB1
PB3
PB5
30
29
28
27
26
25
PA3
33
PA6
PA1
34
31
PE4
35
32
PE3
36
48-Pin LFQFP
PE2
37
24
PC4
PE1
38
23
PC5
P47
39
22
PC6
P46
40
21
PC7
P45
41
20
PH0
P42
42
19
PH1
P41
43
18
PH2
PJ7/VREFL0
44
17
PH3
P40
45
16
P14
PJ6/VREFH0
46
15
P15
AVCC0
47
14
P16
AVSS0
48
13
P17
12
P26
P35
11
8
P27
7
VCC
9
6
P36/EXTAL
10
5
VSS
P30
4
P31
3
PN6/MD
RES#
2
P37/XTAL
1
RX660 Group
PLQP0048KB-B
(Top view)
VCL
1.5.13
1. Overview
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.9, List of Pin and Pin Functions (48-Pin LFQFP).
Pin Assignment (48-Pin LFQFP)
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 33 of 123
RX660 Group
1.6
1. Overview
List of Pin and Pin Functions
1.6.1
144-Pin LFQFP
Table 1.5
Pin No.
List of Pin and Pin Functions (144-Pin LFQFP) (1/6)
144-Pin
LFQFP
Power Supply
Clock
System
Control
I/O Port
1
AVSS0
Timer
Bus
(MTU, TMR, RTC,
POE, CAC, CMTW)
Communication
Interrupt
(SCI, RSCI, RSPI,
RIIC, CANFD, REMC) (IRQ, NMI)
2
P05
3
P06
4
P03
5
P04
6
P02
TMCI1
SCK6
IRQ10
7
P01
TMCI0
RXD6/SMISO6/
SSCL6
IRQ9
8
P00
TMRI0
TXD6/SMOSI6/
SSDA6
IRQ8
9
10
PF5
EMLE*1
IRQ13
DA1
IRQ11
DA0
IRQ4
PN7*2
11
PJ5
12
PJ4
13
14
POE8#
CTS2#/RTS2#/SS2#
IRQ13
PJ3
MTIOC3C
CTS6#/RTS6#/SS6#/
CTS0#/RTS0#/SS0#
IRQ11
PJ1
MTIOC3A
VCL
15
16
MD/FINED
PN6
17
XCIN*3
PH7*4
18
XCOUT*3
PH6*4
19
RES#
20
XTAL
21
VSS
22
EXTAL
23
VCC
24
TRST#*1
P37
IRQ4
P36
IRQ5
P35
NMI
P34
MTIOC0A/TMCI3/
POE10#
SCK6/SCK0
IRQ4
26
P33
MTIOC0D/TMRI3/
POE4#/POE11#
RXD6/SMISO6/
SSCL6/RXD0/
SMISO0/SSCL0/
CRX0-A
IRQ3-DS
27
P32
MTIOC0C/TMO3/
TXD6/SMOSI6/
RTCIC2*5/RTCOUT*5/ SSDA6/TXD0/
POE0#/POE10#
SMOSI0/SSDA0/
CTX0-A
IRQ2-DS
25
A/D, D/A,
CMPC
28
TMS*1
P31
MTIOC4D/TMCI2/
RTCIC1*5
CTS1#/RTS1#/SS1#
IRQ1-DS
29
TDI*1
P30
MTIOC4B/TMRI3/
RTCIC0*5/POE8#
RXD1/SMISO1/
SSCL1
IRQ0-DS
COMP3
30
TCK*1
P27
MTIOC2B/TMCI3
SCK1
IRQ7
CVREFC3
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
CS3#
Page 34 of 123
RX660 Group
Table 1.5
Pin No.
1. Overview
List of Pin and Pin Functions (144-Pin LFQFP) (2/6)
144-Pin
LFQFP
Power Supply
Clock
System
Control
I/O Port
Bus
(MTU, TMR, RTC,
POE, CAC, CMTW)
(SCI, RSCI, RSPI,
RIIC, CANFD, REMC) (IRQ, NMI)
A/D, D/A,
CMPC
31
TDO*1
P26
CS2#
MTIOC2A/TMO1
TXD1/SMOSI1/
SSDA1/CTS3#/
RTS3#/SS3#
IRQ6
CMPC30
32
P25
CS1#
MTIOC4C/MTCLKB
RXD3/SMISO3/
SSCL3
IRQ5
ADTRG0#
33
P24
CS0#
MTIOC4A/MTCLKA/
TMRI1
SCK3
IRQ12
34
P23
MTIOC3D/MTCLKD
TXD3/SMOSI3/
SSDA3/CTS0#/
RTS0#/SS0#
IRQ3
35
P22
MTIOC3B/MTCLKC/
TMO0
SCK0
IRQ15
36
P21
MTIOC1B/TMCI0/
MTIOC4A
RXD0/SMISO0/
SSCL0
IRQ9
37
P20
MTIOC1A/TMRI0
TXD0/SMOSI0/
SSDA0
IRQ8
38
P17
MTIOC3A/MTIOC3B/
TMO1/POE8#/
MTIOC4B
SCK1/TXD3/SMOSI3/ IRQ7
SSDA3/MISOA-C/
SDA2
39
P87
MTIOC4C
SMOSI10/SSDA10/
TXD10/TXD010-B/
SMOSI010-B/
SSDA010-B
IRQ15
40
P16
MTIOC3C/MTIOC3D/
TMO2/RTCOUT*5
TXD1/SMOSI1/
SSDA1/RXD3/
SMISO3/SSCL3/
MOSIA-C/SCL2
IRQ6
41
P86
MTIOC4D
SMISO10/SSCL10/
RXD10/RXD010-B/
SMISO010-B/
SSCL010-B
IRQ14
42
P15
MTIOC0B/MTCLKB/
TMCI2
RXD1/SMISO1/
SSCL1/SCK3/
CRX0-C
IRQ5
CMPC20
43
P14
MTIOC3A/MTCLKA/
TMRI2
CTS1#/RTS1#/SS1#/
CTX0-C
IRQ4
CVREFC2
44
P13
MTIOC0B/TMO3
TXD2/SMOSI2/
SSDA2/SDA0
IRQ3
45
P12
MTIC5U/TMCI1
RXD2/SMISO2/
SSCL2/SCL0
IRQ2
46
PH3
MTIOC4D/TMCI0
47
PH2
MTIOC4C/TMRI0/
TOC1
IRQ1
48
PH1
MTIOC3D/TMO0/TIC1
IRQ0
49
PH0
MTIOC3B/CACREF
50
Timer
P56
Communication
Interrupt
ADTRG0#
ADST0
ADTRG0#
MTIOC3C
SCK7
IRQ6
51
TRDATA3*1
P55
D0[A0/D0]/
WAIT#
MTIOC4D/MTIOC4A/
TMO3
TXD7/SMOSI7/
SSDA7/CRX0-D
IRQ10
52
TRDATA2*1
P54
ALE/
D1[A1/D1]
MTIOC4B/TMCI1
CTS2#/RTS2#/SS2#/
CTX0-D
IRQ4
53
P53
BCLK
PMC0
IRQ3
54
P52
RD#
RXD2/SMISO2/
SSCL2
IRQ2
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
COMP2
Page 35 of 123
RX660 Group
Table 1.5
Pin No.
144-Pin
LFQFP
1. Overview
List of Pin and Pin Functions (144-Pin LFQFP) (3/6)
Power Supply
Clock
System
Control
I/O Port
Timer
Bus
(MTU, TMR, RTC,
POE, CAC, CMTW)
Communication
Interrupt
(SCI, RSCI, RSPI,
RIIC, CANFD, REMC) (IRQ, NMI)
55
P51
WR1#/BC1#/
WAIT#
SCK2/PMC0
IRQ1
56
P50
WR0#/WR#
TXD2/SMOSI2/
SSDA2
IRQ0
57
VSS
58
TRCLK*1
59
VCC
60
UB
P83
MTIOC4C
SCK10/SS10#/
IRQ3
CTS10#/SCK010-B/
CTS010#-A/SS010#-A
PC7
CS0#
MTIOC3A/MTCLKB/
TXD8/SMOSI8/
IRQ14
TMO2/CACREF/TOC0 SSDA8/SMOSI10/
SSDA10/TXD10/
TXD010-C/
SMOSI010-C/
SSDA010-C/MISOA-A
61
PC6
D2[A2/D2]/
CS1#
MTIOC3C/MTCLKA/
TMCI2/TIC0
RXD8/SMISO8/
IRQ13
SSCL8/SMISO10/
SSCL10/RXD10/
RXD010-C/
SMISO010-C/
SSCL010-C/MOSIA-A
62
PC5
D3[A3/D3]/
CS2#/WAIT#
MTIOC3B/MTCLKD/
TMRI2/MTIOC0C
SCK8/SCK10/
SCK010-C/
RSPCKA-A/PMC0
IRQ5
63
TRSYNC*1
P82
MTIOC4A
SMOSI10/SSDA10/
TXD10/TXD010-A/
SMOSI010-A/
SSDA010-A
IRQ2
64
TRDATA1*1
P81
MTIOC3D
SMISO10/SSCL10/
RXD10/RXD010-A/
SMISO010-A/
SSCL010-A
IRQ9
65
TRDATA0*1
P80
MTIOC3B
SCK10/RTS10#/
SCK010-A/
RTS010#-A/DE010-A
IRQ8
66
PC4
A20/CS3#
MTIOC3D/MTCLKC/
TMCI1/POE0#/
MTIOC0A
SCK5/CTS8#/RTS8#/ IRQ12
SS8#/SS10#/CTS10#/
RTS10#/CTS010#-B/
RTS010#-B/
SS010#-B/DE010-B/
SSLA0-A/PMC0
67
PC3
A19
MTIOC4D
TXD5/SMOSI5/
SSDA5/PMC0
IRQ11
68
TRDATA7*1
P77
SMOSI11/SSDA11/
TXD11/TXD011-A/
SMOSI011-A/
SSDA011-A
IRQ7
69
TRDATA6*1
P76
SMISO11/SSCL11/
RXD11/RXD011-A/
SMISO011-A/
SSCL011-A
IRQ14
RXD5/SMISO5/
SSCL5/TXDB011-A/
SSLA3-A
IRQ10
SCK11/RTS11#/
SCK011-A/
RTS011#-A/DE011-A
IRQ13
70
71
PC2
TRSYNC1*1
P75
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
A18
MTIOC4B
A/D, D/A,
CMPC
Page 36 of 123
RX660 Group
Table 1.5
Pin No.
1. Overview
List of Pin and Pin Functions (144-Pin LFQFP) (4/6)
144-Pin
LFQFP
Power Supply
Clock
System
Control
I/O Port
Bus
72
TRDATA5*1
P74
A20
73
PC1
A17
MTIOC3A
SCK5/TXD011-C/
IRQ12
SMOSI011-C/
SSDA011-C/
TXDA011-C/SSLA2-A
74
PL1
75
PC0
A16
MTIOC3C
CTS5#/RTS5#/SS5#/ IRQ14
RXD011-C/
SMISO011-C/
SSCL011-C/SSLA1-A
76
PL0
TRDATA4*1
Timer
(MTU, TMR, RTC,
POE, CAC, CMTW)
Communication
Interrupt
(SCI, RSCI, RSPI,
RIIC, CANFD, REMC) (IRQ, NMI)
SS11#/CTS11#/
IRQ12
CTS011#-A/SS011#-A
P73
CS3#
78
PB7
A15
MTIOC3B
TXD9/SMOSI9/
SSDA9/SMOSI11/
SSDA11/TXD11/
TXD011-B/
SMOSI011-B/
SSDA011-B
IRQ15
79
PB6
A14
MTIOC3D
RXD9/SMISO9/
SSCL9/SMISO11/
SSCL11/RXD11/
RXD011-B/
SMISO011-B/
SSCL011-B
IRQ6
80
PB5
A13
MTIOC2A/MTIOC1B/
TMRI1/POE4#/TOC2
SCK9/SCK11/
SCK011-B
IRQ13
81
PB4
A12
CTS9#/RTS9#/SS9#/
SS11#/CTS11#/
RTS11#/CTS011#-B/
RTS011#-B/
SS011#-B/DE011-B
IRQ4
82
PB3
A11
SCK4/SCK6/PMC0
IRQ3
83
PB2
A10
CTS4#/RTS4#/SS4#/
CTS6#/RTS6#/SS6#
IRQ2
84
PB1
A9
TXD4/SMOSI4/
SSDA4/TXD6/
SMOSI6/SSDA6
IRQ4-DS
85
P72
A19/CS2#
IRQ10
86
P71
A18/CS1#
IRQ1
87
PB0
A8
88
PA7
A7
89
PA6
A6
MTIC5V/MTCLKB/
TMCI3/POE10#/
MTIOC3D/MTIOC6B
90
PA5
A5
MTIOC6B
77
91
A/D, D/A,
CMPC
IRQ8
MTIOC0A/MTIOC4A/
TMO0/POE11#/TIC2
MTIOC0C/MTIOC4C/
TMCI0
MTIC5W/MTIOC3D
RXD4/SMISO4/
SSCL4/RXD6/
SMISO6/SSCL6/
RSPCKA-C
IRQ12
MISOA-B
IRQ7
CTS5#/RTS5#/SS5#/
CTS12#/RTS12#/
SS12#/MOSIA-B
IRQ14
RSPCKA-B
IRQ5
COMP1
VCC
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 37 of 123
RX660 Group
Table 1.5
Pin No.
144-Pin
LFQFP
1. Overview
List of Pin and Pin Functions (144-Pin LFQFP) (5/6)
Power Supply
Clock
System
Control
I/O Port
92
Timer
Bus
Communication
Interrupt
(MTU, TMR, RTC,
POE, CAC, CMTW)
(SCI, RSCI, RSPI,
RIIC, CANFD, REMC) (IRQ, NMI)
A/D, D/A,
CMPC
PA4
A4
MTIC5U/MTCLKA/
TMRI0/MTIOC4C/
MTIOC7C
TXD5/SMOSI5/
SSDA5/TXD12/
SMOSI12/SSDA12/
TXDX12/SIOX12/
SSLA0-B
IRQ5-DS
CVREFC1/
ADST0
94
PA3
A3
MTIOC0D/MTCLKD/
MTIC5V/MTIOC4D
RXD5/SMISO5/
SSCL5
IRQ6-DS
CMPC10
95
PA2
A2
MTIOC7A
RXD5/SMISO5/
SSCL5/RXD12/
SMISO12/SSCL12/
RXDX12/SSLA3-B
IRQ10
96
PA1
A1
MTIOC0B/MTCLKC/
MTIOC7B/MTIOC3B
SCK5/SCK12/
SSLA2-B
IRQ11
97
PA0
BC0#/A0
MTIOC4A/CACREF/
MTIOC6D
SSLA1-B
IRQ0
98
P67
MTIOC7C
IRQ15
99
P66
MTIOC7D
IRQ14
100
P65
101
PE7
D15[A15/D15]/ MTIOC6A/TOC1
D7[A7/D7]
102
PE6
D14[A14/D14]/ MTIOC6C/TIC1
D6[A6/D6]
103
PK5
TXD4/SMOSI4/
SSDA4
93
VSS
ADTRG0#
IRQ13
CTS4#/RTS4#/SS4#
IRQ7
AN015
IRQ6
AN014
104
P70
SCK4
105
PK4
RXD4/SMISO4/
SSCL4
106
PE5
D13[A13/D13]/ MTIOC4C/MTIOC2B
D5[A5/D5]
IRQ5
AN013/
COMP0
107
PE4
D12[A12/D12]/ MTIOC4D/MTIOC1A/
D4[A4/D4]
MTIOC4A/MTIOC7D
IRQ12
AN012
108
PE3
D11[A11/D11]/ MTIOC4B/POE8#/
D3[A3/D3]
MTIOC1B/TOC3
CTS12#/RTS12#/
SS12#
IRQ11
AN011
109
PE2
D10[A10/D10]/ MTIOC4A/MTIOC7A/
D2[A2/D2]
TIC3
RXD12/SMISO12/
SSCL12/RXDX12
IRQ7-DS
AN010/
CVREFC0
110
PE1
D9[A9/D9]/
D1[A1/D1]
MTIOC4C/MTIOC3B
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12
IRQ9
AN009/
CMPC00
111
PE0
D8[A8/D8]/
D0[A0/D0]
MTIOC3D
SCK12
IRQ8
AN008
112
P64
D3[A3/D3]
IRQ4
113
P63
D2[A2/D2]/
CS3#
IRQ3
114
P62
D1[A1/D1]/
CS2#
IRQ2
115
P61
D0[A0/D0]/
CS1#
116
PK3
117
P60
118
PK2
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
CTS9#/RTS9#/SS9#
IRQ0
IRQ1
RXD9/SMISO9/
SSCL9
CS0#
SCK9
IRQ0
TXD9/SMOSI9/
SSDA9
Page 38 of 123
RX660 Group
Table 1.5
Pin No.
1. Overview
List of Pin and Pin Functions (144-Pin LFQFP) (6/6)
144-Pin
LFQFP
Power Supply
Clock
System
Control
I/O Port
Bus
(MTU, TMR, RTC,
POE, CAC, CMTW)
119
TRDATA3*1
PD7
D7[A7/D7]
MTIC5U/POE0#
IRQ7
AN023
120
TRDATA2*1
PD6
D6[A6/D6]
MTIC5V/POE4#/
MTIOC8A
IRQ6
AN022
121
TRCLK*1
PD5
D5[A5/D5]
MTIC5W/POE10#/
MTIOC8C
IRQ5
AN021
122
TRSYNC*1
PD4
D4[A4/D4]
POE11#/MTIOC8B
IRQ4
AN020
123
TRDATA1*1
PD3
D3[A3/D3]
POE8#/MTIOC8D/
TOC2
IRQ3
AN019
124
TRDATA0*1
PD2
D2[A2/D2]
MTIOC4D/TIC2
CRX0-B
IRQ2
AN018
125
TRDATA7*1
PD1
D1[A1/D1]
MTIOC4B/POE0#
CTX0-B
IRQ1
AN017
126
TRDATA6*1
PD0
D0[A0/D0]
POE4#
IRQ0
AN016
127
TRSYNC1*1
P93
A19
POE0#
CTS7#/RTS7#/SS7#
IRQ11
128
TRDATA5*1
P92
A18
POE4#
RXD7/SMISO7/
SSCL7
IRQ10
129
TRDATA4*1
P91
A17
SCK7
IRQ9
A16
TXD7/SMOSI7/
SSDA7
IRQ0
Timer
Communication
Interrupt
(SCI, RSCI, RSPI,
RIIC, CANFD, REMC) (IRQ, NMI)
A/D, D/A,
CMPC
130
PF7
131
P90
132
PF6
133
P47
IRQ15-DS
AN007
134
P46
IRQ14-DS
AN006
135
P45
IRQ13-DS
AN005
136
P44
IRQ12-DS
AN004
137
P43
IRQ11-DS
AN003
138
P42
IRQ10-DS
AN002
139
P41
IRQ9-DS
AN001
IRQ8-DS
AN000
IRQ15
ADTRG0#
140
VREFL0
141
142
VREFH0
143
AVCC0
144
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
PJ7
P40
PJ6
P07
This pin function is not provided for products with no JTAG interface.
This pin function is not provided for products with a JTAG interface.
This pin function is not provided for products with no sub-clock oscillator.
This pin function is not provided for products with a sub-clock oscillator.
This pin function is not available in products with no sub-clock oscillator.
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 39 of 123
RX660 Group
1.6.2
1. Overview
100-Pin LFQFP
Table 1.6
Pin No.
100-Pin
LFQFP
List of Pin and Pin Functions (100-Pin LFQFP) (1/5)
Power Supply
Clock
System
Control
I/O Port
1
2
Timer
Bus
(MTU, TMR, RTC,
POE, CAC, CMTW)
Interrupt
(SCI, RSCI, RSPI,
RIIC, CANFD, REMC) (IRQ, NMI)
EMLE*1
P03*2
IRQ11*2
P04
4
PJ3
MTIOC3C
PJ1
MTIOC3A
CTS6#/RTS6#/SS6#/
CTS0#/RTS0#/SS0#
DA0*2
IRQ11
VCL
6
7
MD/FINED
PN6
8
XCIN*3
PH7*4
9
XCOUT*3
PH6*4
10
RES#
11
XTAL
12
VSS
13
EXTAL
14
VCC
15
TRST#*1
P37
IRQ4
P36
IRQ5
P35
NMI
P34
MTIOC0A/TMCI3/
POE10#
SCK6/SCK0
IRQ4
17
P33
MTIOC0D/TMRI3/
POE4#/POE11#
RXD6/SMISO6/
SSCL6/RXD0/
SMISO0/SSCL0/
CRX0-A
IRQ3-DS
18
P32
TXD6/SMOSI6/
MTIOC0C/TMO3/
RTCIC2*5/RTCOUT*5/ SSDA6/TXD0/
POE0#/POE10#
SMOSI0/SSDA0/
CTX0-A
IRQ2-DS
16
A/D, D/A,
CMPC
P06
3
5
Communication
19
TMS*1
P31
MTIOC4D/TMCI2/
RTCIC1*5
CTS1#/RTS1#/SS1#
IRQ1-DS
20
TDI*1
P30
MTIOC4B/TMRI3/
RTCIC0*5/POE8#
RXD1/SMISO1/
SSCL1
IRQ0-DS
COMP3
21
TCK*1
P27
CS3#
MTIOC2B/TMCI3
SCK1
IRQ7
CVREFC3
22
TDO*1
P26
CS2#
MTIOC2A/TMO1
TXD1/SMOSI1/
SSDA1/CTS3#/
RTS3#/SS3#
IRQ6
CMPC30
23
P25
CS1#
MTIOC4C/MTCLKB
RXD3/SMISO3/
SSCL3
IRQ5
ADTRG0#
24
P24
CS0#
MTIOC4A/MTCLKA/
TMRI1
SCK3
IRQ12
25
P23
MTIOC3D/MTCLKD
TXD3/SMOSI3/
SSDA3/CTS0#/
RTS0#/SS0#
IRQ3
26
P22
MTIOC3B/MTCLKC/
TMO0
SCK0
IRQ15
27
P21
MTIOC1B/TMCI0/
MTIOC4A
RXD0/SMISO0/
SSCL0
IRQ9
28
P20
MTIOC1A/TMRI0
TXD0/SMOSI0/
SSDA0
IRQ8
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 40 of 123
RX660 Group
Table 1.6
Pin No.
100-Pin
LFQFP
1. Overview
List of Pin and Pin Functions (100-Pin LFQFP) (2/5)
Power Supply
Clock
System
Control
I/O Port
Timer
Bus
Communication
Interrupt
(MTU, TMR, RTC,
POE, CAC, CMTW)
(SCI, RSCI, RSPI,
RIIC, CANFD, REMC) (IRQ, NMI)
A/D, D/A,
CMPC
29
P17
MTIOC3A/MTIOC3B/
TMO1/POE8#/
MTIOC4B
SCK1/TXD3/SMOSI3/ IRQ7
SSDA3/MISOA-C/
SDA2
COMP2
30
P16
MTIOC3C/MTIOC3D/
TMO2/RTCOUT*5
TXD1/SMOSI1/
SSDA1/RXD3/
SMISO3/SSCL3/
MOSIA-C/SCL2
IRQ6
ADTRG0#
31
P15
MTIOC0B/MTCLKB/
TMCI2
RXD1/SMISO1/
SSCL1/SCK3/
CRX0-C
IRQ5
CMPC20
32
P14
MTIOC3A/MTCLKA/
TMRI2
CTS1#/RTS1#/SS1#/
CTX0-C
IRQ4
CVREFC2
33
P13
MTIOC0B/TMO3
TXD2/SMOSI2/
SSDA2/SDA0
IRQ3
34
P12
MTIC5U/TMCI1
RXD2/SMISO2/
SSCL2/SCL0
IRQ2
35
PH3
MTIOC4D/TMCI0
36
PH2
MTIOC4C/TMRI0/
TOC1
IRQ1
37
PH1
MTIOC3D/TMO0/TIC1
IRQ0
38
PH0
MTIOC3B/CACREF
39
P55
D0[A0/D0]/
WAIT#
MTIOC4D/MTIOC4A/
TMO3
CRX0-D
IRQ10
40
P54
ALE/
D1[A1/D1]
MTIOC4B/TMCI1
CTS2#/RTS2#/SS2#/
CTX0-D
IRQ4
41
P53
BCLK
PMC0
IRQ3
42
P52
RD#
RXD2/SMISO2/
SSCL2
IRQ2
43
P51
WR1#/BC1#/
WAIT#
SCK2/PMC0
IRQ1
44
P50
WR0#/WR#
TXD2/SMOSI2/
SSDA2
IRQ0
PC7
CS0#
MTIOC3A/MTCLKB/
TXD8/SMOSI8/
IRQ14
TMO2/CACREF/TOC0 SSDA8/SMOSI10/
SSDA10/TXD10/
TXD010-C/
SMOSI010-C/
SSDA010-C/MISOA-A
46
PC6
D2[A2/D2]/
CS1#
MTIOC3C/MTCLKA/
TMCI2/TIC0
RXD8/SMISO8/
IRQ13
SSCL8/SMISO10/
SSCL10/RXD10/
RXD010-C/
SMISO010-C/
SSCL010-C/MOSIA-A
47
PC5
D3[A3/D3]/
CS2#/WAIT#
MTIOC3B/MTCLKD/
TMRI2/MTIOC0C
SCK8/SCK10/
SCK010-C/
RSPCKA-A/PMC0
48
PC4
A20/CS3#
MTIOC3D/MTCLKC/
TMCI1/POE0#/
MTIOC0A
SCK5/CTS8#/RTS8#/ IRQ12
SS8#/SS10#/CTS10#/
RTS10#/CTS010#-B/
RTS010#-B/
SS010#-B/DE010-B/
SSLA0-A/PMC0
49
PC3
A19
MTIOC4D
TXD5/SMOSI5/
SSDA5/PMC0
45
UB
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
ADST0
ADTRG0#
IRQ5
IRQ11
Page 41 of 123
RX660 Group
Table 1.6
Pin No.
100-Pin
LFQFP
1. Overview
List of Pin and Pin Functions (100-Pin LFQFP) (3/5)
Power Supply
Clock
System
Control
I/O Port
Timer
Communication
Interrupt
Bus
(MTU, TMR, RTC,
POE, CAC, CMTW)
(SCI, RSCI, RSPI,
RIIC, CANFD, REMC) (IRQ, NMI)
A/D, D/A,
CMPC
50
PC2
A18
MTIOC4B
RXD5/SMISO5/
SSCL5/TXDB011-A/
SSLA3-A
51
PC1
A17
MTIOC3A
SCK5/TXD011-C/
IRQ12
SMOSI011-C/
SSDA011-C/
TXDA011-C/SSLA2-A
52
PC0
A16
MTIOC3C
CTS5#/RTS5#/SS5#/ IRQ14
RXD011-C/
SMISO011-C/
SSCL011-C/SSLA1-A
53
PB7
A15
MTIOC3B
TXD9/SMOSI9/
SSDA9/SMOSI11/
SSDA11/TXD11/
TXD011-B/
SMOSI011-B/
SSDA011-B
IRQ15
54
PB6
A14
MTIOC3D
RXD9/SMISO9/
SSCL9/SMISO11/
SSCL11/RXD11/
RXD011-B/
SMISO011-B/
SSCL011-B
IRQ6
55
PB5
A13
MTIOC2A/MTIOC1B/
TMRI1/POE4#/TOC2
SCK9/SCK11/
SCK011-B
IRQ13
56
PB4
A12
CTS9#/RTS9#/SS9#/
SS11#/CTS11#/
RTS11#/CTS011#-B/
RTS011#-B/
SS011#-B/DE011-B
IRQ4
57
PB3
A11
SCK4/SCK6/PMC0
IRQ3
58
PB2
A10
CTS4#/RTS4#/SS4#/
CTS6#/RTS6#/SS6#
IRQ2
59
PB1
A9
MTIOC0C/MTIOC4C/
TMCI0
TXD4/SMOSI4/
SSDA4/TXD6/
SMOSI6/SSDA6
IRQ4-DS
PB0
A8
MTIC5W/MTIOC3D
RXD4/SMISO4/
SSCL4/RXD6/
SMISO6/SSCL6/
RSPCKA-C
IRQ12
63
PA7
A7
MISOA-B
IRQ7
64
PA6
A6
MTIC5V/MTCLKB/
TMCI3/POE10#/
MTIOC3D/MTIOC6B
CTS5#/RTS5#/SS5#/
CTS12#/RTS12#/
SS12#/MOSIA-B
IRQ14
65
PA5
A5
MTIOC6B
RSPCKA-B
IRQ5
66
PA4
A4
MTIC5U/MTCLKA/
TMRI0/MTIOC4C/
MTIOC7C
TXD5/SMOSI5/
SSDA5/TXD12/
SMOSI12/SSDA12/
TXDX12/SIOX12/
SSLA0-B
IRQ5-DS
CVREFC1/
ADST0
67
PA3
A3
MTIOC0D/MTCLKD/
MTIC5V/MTIOC4D
RXD5/SMISO5/
SSCL5
IRQ6-DS
CMPC10
60
COMP1
VCC
61
62
MTIOC0A/MTIOC4A/
TMO0/POE11#/TIC2
IRQ10
VSS
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 42 of 123
RX660 Group
Table 1.6
Pin No.
100-Pin
LFQFP
1. Overview
List of Pin and Pin Functions (100-Pin LFQFP) (4/5)
Power Supply
Clock
System
Control
I/O Port
Timer
Communication
Interrupt
Bus
(MTU, TMR, RTC,
POE, CAC, CMTW)
(SCI, RSCI, RSPI,
RIIC, CANFD, REMC) (IRQ, NMI)
68
PA2
A2
MTIOC7A
RXD5/SMISO5/
SSCL5/RXD12/
SMISO12/SSCL12/
RXDX12/SSLA3-B
IRQ10
69
PA1
A1
MTIOC0B/MTCLKC/
MTIOC7B/MTIOC3B
SCK5/SCK12/
SSLA2-B
IRQ11
70
PA0
BC0#/A0
MTIOC4A/CACREF/
MTIOC6D
SSLA1-B
IRQ0
71
PE7
D15[A15/D15]/ MTIOC6A/TOC1
D7[A7/D7]
72
PE6
D14[A14/D14]/ MTIOC6C/TIC1
D6[A6/D6]
73
PE5
74
A/D, D/A,
CMPC
ADTRG0#
IRQ7
AN015
IRQ6
AN014
D13[A13/D13]/ MTIOC4C/MTIOC2B
D5[A5/D5]
IRQ5
AN013/
COMP0
PE4
D12[A12/D12]/ MTIOC4D/MTIOC1A/
D4[A4/D4]
MTIOC4A/MTIOC7D
IRQ12
AN012
75
PE3
D11[A11/D11]/ MTIOC4B/POE8#/
D3[A3/D3]
MTIOC1B/TOC3
CTS12#/RTS12#/
SS12#
IRQ11
AN011
76
PE2
D10[A10/D10]/ MTIOC4A/MTIOC7A/
D2[A2/D2]
TIC3
RXD12/SMISO12/
SSCL12/RXDX12
IRQ7-DS
AN010/
CVREFC0
77
PE1
D9[A9/D9]/
D1[A1/D1]
MTIOC4C/MTIOC3B
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12
IRQ9
AN009/
CMPC00
78
PE0
D8[A8/D8]/
D0[A0/D0]
MTIOC3D
SCK12
IRQ8
AN008
79
PD7
D7[A7/D7]
MTIC5U/POE0#
IRQ7
AN023
80
PD6
D6[A6/D6]
MTIC5V/POE4#/
MTIOC8A
IRQ6
AN022
81
PD5
D5[A5/D5]
MTIC5W/POE10#/
MTIOC8C
IRQ5
AN021
82
PD4
D4[A4/D4]
POE11#/MTIOC8B
IRQ4
AN020
83
PD3
D3[A3/D3]
POE8#/MTIOC8D/
TOC2
IRQ3
AN019
84
PD2
D2[A2/D2]
MTIOC4D/TIC2
CRX0-B
IRQ2
AN018
85
PD1
D1[A1/D1]
MTIOC4B/POE0#
CTX0-B
IRQ1
AN017
86
PD0
D0[A0/D0]
POE4#
IRQ0
AN016
87
P47
IRQ15-DS
AN007
88
P46
IRQ14-DS
AN006
89
P45
IRQ13-DS
AN005
90
P44
IRQ12-DS
AN004
91
P43
IRQ11-DS
AN003
92
P42
IRQ10-DS
AN002
93
P41
IRQ9-DS
AN001
IRQ8-DS
AN000
IRQ15
ADTRG0#
94
VREFL0
95
VREFH0
97
AVCC0
98
99
PJ7
P40
96
CTS4#/RTS4#/SS4#
PJ6
P07
AVSS0
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 43 of 123
RX660 Group
Table 1.6
Pin No.
100-Pin
LFQFP
100
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
1. Overview
List of Pin and Pin Functions (100-Pin LFQFP) (5/5)
Power Supply
Clock
System
Control
I/O Port
Timer
Bus
(MTU, TMR, RTC,
POE, CAC, CMTW)
P05
Communication
Interrupt
(SCI, RSCI, RSPI,
RIIC, CANFD, REMC) (IRQ, NMI)
IRQ13
A/D, D/A,
CMPC
DA1
This pin function is not provided for products with no JTAG interface.
This pin function is not provided for products with a JTAG interface.
This pin function is not provided for products with no sub-clock oscillator.
This pin function is not provided for products with a sub-clock oscillator.
This pin function is not available in products with no sub-clock oscillator.
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 44 of 123
RX660 Group
1.6.3
1. Overview
80-Pin LFQFP
Table 1.7
Pin No.
80-Pin
LFQFP
List of Pin and Pin Functions (80-Pin LFQFP) (1/4)
Power Supply
Clock
System Control
Timer
I/O Port
1
P06
2
P03
3
P04
4
(MTU, TMR, RTC,
POE, CAC, CMTW)
Communication
Interrupt
(SCI, RSCI, RSPI,
RIIC, CANFD, REMC) (IRQ, NMI)
IRQ11
A/D, D/A,
CMPC
DA0
VCL
5
PJ1
6
MD/FINED
PN6
7
XCIN*1
PH7*2
8
XCOUT*1
PH6*2
9
RES#
10
XTAL
11
VSS
12
EXTAL
13
VCC
MTIOC3A
P37
IRQ4
P36
IRQ5
14
P35
15
P34
MTIOC0A/TMCI3/
POE10#
16
P32
TXD6/SMOSI6/
MTIOC0C/TMO3/
RTCIC2*3/RTCOUT*3/ SSDA6/TXD0/
POE0#/POE10#
SMOSI0/SSDA0/
CTX0-A
17
P31
MTIOC4D/TMCI2/
RTCIC1*3
CTS1#/RTS1#/SS1#
IRQ1-DS
18
P30
MTIOC4B/TMRI3/
RTCIC0*3/POE8#
RXD1/SMISO1/
SSCL1
IRQ0-DS
COMP3
19
P27
MTIOC2B/TMCI3
SCK1
IRQ7
CVREFC3
20
P26
MTIOC2A/TMO1
TXD1/SMOSI1/
SSDA1/CTS3#/
RTS3#/SS3#
IRQ6
CMPC30
21
P21
MTIOC1B/TMCI0/
MTIOC4A
RXD0/SMISO0/
SSCL0
IRQ9
22
P20
MTIOC1A/TMRI0
TXD0/SMOSI0/
SSDA0
IRQ8
23
P17
MTIOC3A/MTIOC3B/
TMO1/POE8#/
MTIOC4B
SCK1/TXD3/SMOSI3/ IRQ7
SSDA3/MISOA-C/
SDA2
COMP2
24
P16
MTIOC3C/MTIOC3D/
TMO2/RTCOUT*3
TXD1/SMOSI1/
SSDA1/RXD3/
SMISO3/SSCL3/
MOSIA-C/SCL2
IRQ6
ADTRG0#
25
P15
MTIOC0B/MTCLKB/
TMCI2
RXD1/SMISO1/
SSCL1/SCK3/
CRX0-C
IRQ5
CMPC20
26
P14
MTIOC3A/MTCLKA/
TMRI2
CTS1#/RTS1#/SS1#/
CTX0-C
IRQ4
CVREFC2
27
P13
MTIOC0B/TMO3
SDA0
IRQ3
28
P12
MTIC5U/TMCI1
SCL0
IRQ2
29
PH3
MTIOC4D/TMCI0
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
NMI
SCK6/SCK0
IRQ4
IRQ2-DS
Page 45 of 123
RX660 Group
Table 1.7
Pin No.
80-Pin
LFQFP
1. Overview
List of Pin and Pin Functions (80-Pin LFQFP) (2/4)
Power Supply
Clock
System Control
Timer
I/O Port
(MTU, TMR, RTC,
POE, CAC, CMTW)
Communication
Interrupt
(SCI, RSCI, RSPI,
RIIC, CANFD, REMC) (IRQ, NMI)
30
PH2
MTIOC4C/TMRI0/
TOC1
IRQ1
31
PH1
MTIOC3D/TMO0/TIC1
IRQ0
32
PH0
MTIOC3B/CACREF
33
P55
MTIOC4D/MTIOC4A/
TMO3
CRX0-D
IRQ10
P54
MTIOC4B/TMCI1
CTX0-D
IRQ4
PC7
MTIOC3A/MTCLKB/
TXD8/SMOSI8/
IRQ14
TMO2/CACREF/TOC0 SSDA8/SMOSI10/
SSDA10/TXD10/
TXD010-C/
SMOSI010-C/
SSDA010-C/MISOA-A
36
PC6
MTIOC3C/MTCLKA/
TMCI2/TIC0
RXD8/SMISO8/
IRQ13
SSCL8/SMISO10/
SSCL10/RXD10/
RXD010-C/
SMISO010-C/
SSCL010-C/MOSIA-A
37
PC5
MTIOC3B/MTCLKD/
TMRI2/MTIOC0C
SCK8/SCK10/
SCK010-C/
RSPCKA-A/PMC0
38
PC4
MTIOC3D/MTCLKC/
TMCI1/POE0#/
MTIOC0A
SCK5/CTS8#/RTS8#/ IRQ12
SS8#/SS10#/CTS10#/
RTS10#/CTS010#-B/
RTS010#-B/
SS010#-B/DE010-B/
SSLA0-A/PMC0
39
PC3
MTIOC4D
TXD5/SMOSI5/
SSDA5/PMC0
IRQ11
40
PC2
MTIOC4B
RXD5/SMISO5/
SSCL5/TXDB011-A/
SSLA3-A
IRQ10
41
PB7
MTIOC3B
TXD9/SMOSI9/
SSDA9/SMOSI11/
SSDA11/TXD11/
TXD011-B/
SMOSI011-B/
SSDA011-B
IRQ15
42
PB6
MTIOC3D
RXD9/SMISO9/
SSCL9/SMISO11/
SSCL11/RXD11/
RXD011-B/
SMISO011-B/
SSCL011-B
IRQ6
43
PB5
MTIOC2A/MTIOC1B/
TMRI1/POE4#/TOC2
SCK9/SCK11/
SCK011-B
IRQ13
44
PB4
CTS9#/RTS9#/SS9#/
SS11#/CTS11#/
RTS11#/CTS011#-B/
RTS011#-B/
SS011#-B/DE011-B
IRQ4
45
PB3
SCK4/SCK6/PMC0
IRQ3
46
PB2
CTS4#/RTS4#/SS4#/
CTS6#/RTS6#/SS6#
IRQ2
34
35
UB
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
MTIOC0A/MTIOC4A/
TMO0/POE11#/TIC2
A/D, D/A,
CMPC
ADST0
ADTRG0#
IRQ5
Page 46 of 123
RX660 Group
Table 1.7
Pin No.
80-Pin
LFQFP
1. Overview
List of Pin and Pin Functions (80-Pin LFQFP) (3/4)
Power Supply
Clock
System Control
47
48
Communication
Interrupt
(MTU, TMR, RTC,
POE, CAC, CMTW)
(SCI, RSCI, RSPI,
RIIC, CANFD, REMC) (IRQ, NMI)
A/D, D/A,
CMPC
PB1
MTIOC0C/MTIOC4C/
TMCI0
TXD4/SMOSI4/
SSDA4/TXD6/
SMOSI6/SSDA6
IRQ4-DS
COMP1
PB0
MTIC5W/MTIOC3D
RXD4/SMISO4/
SSCL4/RXD6/
SMISO6/SSCL6/
RSPCKA-C
IRQ12
PA6
MTIC5V/MTCLKB/
TMCI3/POE10#/
MTIOC3D/MTIOC6B
CTS5#/RTS5#/SS5#/
CTS12#/RTS12#/
SS12#/MOSIA-B
IRQ14
I/O Port
VCC
49
50
Timer
VSS
51
52
PA5
MTIOC6B
RSPCKA-B
IRQ5
53
PA4
MTIC5U/MTCLKA/
TMRI0/MTIOC4C/
MTIOC7C
TXD5/SMOSI5/
SSDA5/TXD12/
SMOSI12/SSDA12/
TXDX12/SIOX12/
SSLA0-B
IRQ5-DS
CVREFC1/
ADST0
54
PA3
MTIOC0D/MTCLKD/
MTIC5V/MTIOC4D
RXD5/SMISO5/
SSCL5
IRQ6-DS
CMPC10
55
PA2
MTIOC7A
RXD5/SMISO5/
SSCL5/RXD12/
SMISO12/SSCL12/
RXDX12/SSLA3-B
IRQ10
56
PA1
MTIOC0B/MTCLKC/
MTIOC7B/MTIOC3B
SCK5/SCK12/
SSLA2-B
IRQ11
57
PA0
MTIOC4A/CACREF/
MTIOC6D
SSLA1-B
IRQ0
58
PE5
MTIOC4C/MTIOC2B
IRQ5
AN013/COMP0
59
PE4
MTIOC4D/MTIOC1A/
MTIOC4A/MTIOC7D
IRQ12
AN012
60
PE3
MTIOC4B/POE8#/
MTIOC1B/TOC3
CTS12#/RTS12#/
SS12#
IRQ11
AN011
61
PE2
MTIOC4A/MTIOC7A/
TIC3
RXD12/SMISO12/
SSCL12/RXDX12
IRQ7-DS
AN010/
CVREFC0
62
PE1
MTIOC4C/MTIOC3B
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12
IRQ9
AN009/
CMPC00
63
PE0
MTIOC3D
SCK12
IRQ8
AN008
64
PD2
MTIOC4D/TIC2
CRX0-B
IRQ2
AN018
CTX0-B
IRQ1
AN017
IRQ0
AN016
ADTRG0#
65
PD1
MTIOC4B/POE0#
66
PD0
POE4#
67
P47
IRQ15-DS
AN007
68
P46
IRQ14-DS
AN006
69
P45
IRQ13-DS
AN005
70
P44
IRQ12-DS
AN004
71
P43
IRQ11-DS
AN003
72
P42
IRQ10-DS
AN002
P41
IRQ9-DS
AN001
IRQ8-DS
AN000
73
74
75
VREFL0
PJ7
P40
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 47 of 123
RX660 Group
Table 1.7
Pin No.
1. Overview
List of Pin and Pin Functions (80-Pin LFQFP) (4/4)
Timer
80-Pin
LFQFP
Power Supply
Clock
System Control
I/O Port
76
VREFH0
PJ6
77
AVCC0
78
79
80
(MTU, TMR, RTC,
POE, CAC, CMTW)
Communication
Interrupt
(SCI, RSCI, RSPI,
RIIC, CANFD, REMC) (IRQ, NMI)
A/D, D/A,
CMPC
P07
IRQ15
ADTRG0#
P05
IRQ13
DA1
AVSS0
Note 1. This pin function is not provided for products with no sub-clock oscillator.
Note 2. This pin function is not provided for products with a sub-clock oscillator.
Note 3. This pin function is not available in products with no sub-clock oscillator.
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 48 of 123
RX660 Group
1.6.4
1. Overview
64-Pin LFQFP
Table 1.8
Pin No.
64-Pin
LFQFP
List of Pin and Pin Functions (64-Pin LFQFP) (1/3)
Power Supply
Clock
System Control
1
Timer
I/O Port
(MTU, TMR, RTC,
POE, CAC, CMTW)
Communication
P03
2
VCL
3
MD/FINED
PN6
4
XCIN*1
PH7*2
5
XCOUT*1
PH6*2
6
RES#
7
XTAL
8
VSS
9
EXTAL
10
VCC
Interrupt
(SCI, RSCI, RSPI,
RIIC, CANFD, REMC) (IRQ, NMI)
IRQ11
P37
IRQ4
P36
IRQ5
11
P35
12
P32
TXD6/SMOSI6/
MTIOC0C/TMO3/
RTCIC2*3/RTCOUT*3/ SSDA6/CTX0-A
POE0#/POE10#
13
P31
MTIOC4D/TMCI2/
RTCIC1*3
CTS1#/RTS1#/SS1#
IRQ1-DS
14
P30
MTIOC4B/TMRI3/
RTCIC0*3/POE8#
RXD1/SMISO1/
SSCL1
IRQ0-DS
A/D, D/A,
CMPC
DA0
NMI
IRQ2-DS
COMP3
15
P27
MTIOC2B/TMCI3
SCK1
IRQ7
CVREFC3
16
P26
MTIOC2A/TMO1
TXD1/SMOSI1/
SSDA1/CTS3#/
RTS3#/SS3#
IRQ6
CMPC30
17
P17
MTIOC3A/MTIOC3B/
TMO1/POE8#/
MTIOC4B
SCK1/TXD3/SMOSI3/ IRQ7
SSDA3/MISOA-C/
SDA2
COMP2
18
P16
MTIOC3C/MTIOC3D/
TMO2/RTCOUT*3
TXD1/SMOSI1/
SSDA1/RXD3/
SMISO3/SSCL3/
MOSIA-C/SCL2
IRQ6
ADTRG0#
19
P15
MTIOC0B/MTCLKB/
TMCI2
RXD1/SMISO1/
SSCL1/SCK3/
CRX0-C
IRQ5
CMPC20
20
P14
MTIOC3A/MTCLKA/
TMRI2
CTS1#/RTS1#/SS1#/
CTX0-C
IRQ4
CVREFC2
21
PH3
MTIOC4D/TMCI0
22
PH2
MTIOC4C/TMRI0/
TOC1
IRQ1
23
PH1
MTIOC3D/TMO0/TIC1
IRQ0
24
PH0
MTIOC3B/CACREF
25
P55
MTIOC4D/MTIOC4A/
TMO3
CRX0-D
IRQ10
26
P54
MTIOC4B/TMCI1
CTX0-D
IRQ4
PC7
MTIOC3A/MTCLKB/
TXD8/SMOSI8/
IRQ14
TMO2/CACREF/TOC0 SSDA8/SMOSI10/
SSDA10/TXD10/
TXD010-C/
SMOSI010-C/
SSDA010-C/MISOA-A
27
UB
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
ADST0
ADTRG0#
Page 49 of 123
RX660 Group
Table 1.8
Pin No.
64-Pin
LFQFP
1. Overview
List of Pin and Pin Functions (64-Pin LFQFP) (2/3)
Power Supply
Clock
System Control
Timer
I/O Port
Communication
Interrupt
(MTU, TMR, RTC,
POE, CAC, CMTW)
(SCI, RSCI, RSPI,
RIIC, CANFD, REMC) (IRQ, NMI)
A/D, D/A,
CMPC
28
PC6
MTIOC3C/MTCLKA/
TMCI2/TIC0
RXD8/SMISO8/
IRQ13
SSCL8/SMISO10/
SSCL10/RXD10/
RXD010-C/
SMISO010-C/
SSCL010-C/MOSIA-A
29
PC5
MTIOC3B/MTCLKD/
TMRI2/MTIOC0C
SCK8/SCK10/
SCK010-C/
RSPCKA-A/PMC0
30
PC4
MTIOC3D/MTCLKC/
TMCI1/POE0#/
MTIOC0A
SCK5/CTS8#/RTS8#/ IRQ12
SS8#/SS10#/CTS10#/
RTS10#/CTS010#-B/
RTS010#-B/
SS010#-B/DE010-B/
SSLA0-A/PMC0
31
PC3
MTIOC4D
TXD5/SMOSI5/
SSDA5/PMC0
IRQ11
32
PC2
MTIOC4B
RXD5/SMISO5/
SSCL5/TXDB011-A/
SSLA3-A
IRQ10
33
PB7
MTIOC3B
TXD9/SMOSI9/
SSDA9/SMOSI11/
SSDA11/TXD11/
TXD011-B/
SMOSI011-B/
SSDA011-B
IRQ15
34
PB6
MTIOC3D
RXD9/SMISO9/
SSCL9/SMISO11/
SSCL11/RXD11/
RXD011-B/
SMISO011-B/
SSCL011-B
IRQ6
35
PB5
MTIOC2A/MTIOC1B/
TMRI1/POE4#/TOC2
SCK9/SCK11/
SCK011-B
IRQ13
36
PB3
MTIOC0A/MTIOC4A/
TMO0/POE11#/TIC2
SCK4/SCK6/PMC0
IRQ3
37
PB1
MTIOC0C/MTIOC4C/
TMCI0
TXD4/SMOSI4/
SSDA4/TXD6/
SMOSI6/SSDA6
IRQ4-DS
PB0
MTIC5W/MTIOC3D
RXD4/SMISO4/
SSCL4/RXD6/
SMISO6/SSCL6/
RSPCKA-C
IRQ12
41
PA6
MTIC5V/MTCLKB/
TMCI3/POE10#/
MTIOC3D/MTIOC6B
CTS5#/RTS5#/SS5#/
CTS12#/RTS12#/
SS12#/MOSIA-B
IRQ14
42
PA4
MTIC5U/MTCLKA/
TMRI0/MTIOC4C/
MTIOC7C
TXD5/SMOSI5/
SSDA5/TXD12/
SMOSI12/SSDA12/
TXDX12/SIOX12/
SSLA0-B
IRQ5-DS
CVREFC1/
ADST0
43
PA3
MTIOC0D/MTCLKD/
MTIC5V/MTIOC4D
RXD5/SMISO5/
SSCL5
IRQ6-DS
CMPC10
44
PA1
MTIOC0B/MTCLKC/
MTIOC7B/MTIOC3B
SCK5/SCK12/
SSLA2-B
IRQ11
ADTRG0#
38
COMP1
VCC
39
40
IRQ5
VSS
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 50 of 123
RX660 Group
Table 1.8
Pin No.
64-Pin
LFQFP
1. Overview
List of Pin and Pin Functions (64-Pin LFQFP) (3/3)
Power Supply
Clock
System Control
Timer
I/O Port
Communication
Interrupt
(MTU, TMR, RTC,
POE, CAC, CMTW)
(SCI, RSCI, RSPI,
RIIC, CANFD, REMC) (IRQ, NMI)
SSLA1-B
A/D, D/A,
CMPC
45
PA0
MTIOC4A/CACREF/
MTIOC6D
46
PE5
MTIOC4C/MTIOC2B
IRQ5
AN013/COMP0
47
PE4
MTIOC4D/MTIOC1A/
MTIOC4A/MTIOC7D
IRQ12
AN012
48
PE3
MTIOC4B/POE8#/
MTIOC1B/TOC3
CTS12#/RTS12#/
SS12#
IRQ11
AN011
49
PE2
MTIOC4A/MTIOC7A/
TIC3
RXD12/SMISO12/
SSCL12/RXDX12
IRQ7-DS
AN010/
CVREFC0
50
PE1
MTIOC4C/MTIOC3B
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12
IRQ9
AN009/
CMPC00
51
PE0
MTIOC3D
SCK12
IRQ8
AN008
52
P47
IRQ15-DS
AN007
53
P46
IRQ14-DS
AN006
54
P45
IRQ13-DS
AN005
55
P44
IRQ12-DS
AN004
56
P43
IRQ11-DS
AN003
57
P42
IRQ10-DS
AN002
58
P41
IRQ9-DS
AN001
IRQ8-DS
AN000
IRQ15
ADTRG0#
59
VREFL0
60
VREFH0
62
AVCC0
63
64
PJ7
P40
61
IRQ0
PJ6
P07
AVSS0
Note 1. This pin function is not provided for products with no sub-clock oscillator.
Note 2. This pin function is not provided for products with a sub-clock oscillator.
Note 3. This pin function is not available in products with no sub-clock oscillator.
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 51 of 123
RX660 Group
1.6.5
1. Overview
48-Pin LFQFP
Table 1.9
Pin No.
List of Pin and Pin Functions (48-Pin LFQFP) (1/2)
48-Pin
LFQFP
Power Supply
Clock
System Control
1
VCL
2
MD/FINED
3
RES#
4
XTAL
5
VSS
6
EXTAL
7
VCC
Timer
I/O Port
(MTU, TMR, POE,
CAC, CMTW)
Communication
Interrupt
(SCI, RSCI, RSPI,
RIIC, CANFD, REMC) (IRQ, NMI)
A/D, CMPC
PN6
P37
IRQ4
P36
IRQ5
8
P35
NMI
9
P31
MTIOC4D/TMCI2
CTS1#/RTS1#/SS1#
IRQ1-DS
10
P30
MTIOC4B/POE8#
RXD1/SMISO1/
SSCL1
IRQ0-DS
COMP3
11
P27
MTIOC2B
SCK1
IRQ7
CVREFC3
12
P26
MTIOC2A/TMO1
TXD1/SMOSI1/
SSDA1/CTS3#/
RTS3#/SS3#
IRQ6
CMPC30
13
P17
MTIOC3A/MTIOC3B/
TMO1/POE8#/
MTIOC4B
SCK1/TXD3/SMOSI3/ IRQ7
SSDA3/MISOA-C/
SDA2
COMP2
14
P16
MTIOC3C/MTIOC3D/
TMO2
TXD1/SMOSI1/
SSDA1/RXD3/
SMISO3/SSCL3/
MOSIA-C/SCL2
IRQ6
ADTRG0#
15
P15
MTIOC0B/MTCLKB/
TMCI2
RXD1/SMISO1/
SSCL1/SCK3/
CRX0-C
IRQ5
CMPC20
16
P14
MTIOC3A/MTCLKA/
TMRI2
CTS1#/RTS1#/SS1#/
CTX0-C
IRQ4
CVREFC2
17
PH3
MTIOC4D/TMCI0
18
PH2
MTIOC4C/TMRI0/
TOC1
IRQ1
19
PH1
MTIOC3D/TMO0/TIC1
IRQ0
20
PH0
MTIOC3B/CACREF
PC7
MTIOC3A/MTCLKB/
TXD8/SMOSI8/
IRQ14
TMO2/CACREF/TOC0 SSDA8/SMOSI10/
SSDA10/TXD10/
TXD010-C/
SMOSI010-C/
SSDA010-C/MISOA-A
22
PC6
MTIOC3C/MTCLKA/
TMCI2/TIC0
RXD8/SMISO8/
IRQ13
SSCL8/SMISO10/
SSCL10/RXD10/
RXD010-C/
SMISO010-C/
SSCL010-C/MOSIA-A
23
PC5
MTIOC3B/MTCLKD/
TMRI2/MTIOC0C
SCK8/SCK10/
SCK010-C/
RSPCKA-A/PMC0
21
UB
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
ADST0
ADTRG0#
IRQ5
Page 52 of 123
RX660 Group
Table 1.9
Pin No.
48-Pin
LFQFP
1. Overview
List of Pin and Pin Functions (48-Pin LFQFP) (2/2)
Power Supply
Clock
System Control
Timer
I/O Port
Communication
Interrupt
(MTU, TMR, POE,
CAC, CMTW)
(SCI, RSCI, RSPI,
RIIC, CANFD, REMC) (IRQ, NMI)
A/D, CMPC
24
PC4
MTIOC3D/MTCLKC/
TMCI1/POE0#/
MTIOC0A
SCK5/CTS8#/RTS8#/ IRQ12
SS8#/SS10#/CTS10#/
RTS10#/CTS010#-B/
RTS010#-B/
SS010#-B/DE010-B/
SSLA0-A/PMC0
25
PB5
MTIOC2A/MTIOC1B/
TMRI1/POE4#/TOC2
IRQ13
26
PB3
MTIOC0A/MTIOC4A/
TMO0/POE11#/TIC2
SCK4/SCK6/PMC0
IRQ3
27
PB1
MTIOC0C/MTIOC4C/
TMCI0
TXD4/SMOSI4/
SSDA4/TXD6/
SMOSI6/SSDA6
IRQ4-DS
PB0
MTIC5W/MTIOC3D
RXD4/SMISO4/
SSCL4/RXD6/
SMISO6/SSCL6/
RSPCKA-C
IRQ12
31
PA6
MTIC5V/MTCLKB/
POE10#/MTIOC3D
CTS5#/RTS5#/SS5#/
CTS12#/RTS12#/
SS12#/MOSIA-B
IRQ14
32
PA4
MTIC5U/MTCLKA/
TMRI0/MTIOC4C/
MTIOC7C
TXD5/SMOSI5/
SSDA5/TXD12/
SMOSI12/SSDA12/
TXDX12/SIOX12/
SSLA0-B
IRQ5-DS
CVREFC1/
ADST0
33
PA3
MTIOC0D/MTCLKD/
MTIC5V/MTIOC4D
RXD5/SMISO5/
SSCL5
IRQ6-DS
CMPC10
34
PA1
MTIOC0B/MTCLKC/
MTIOC7B/MTIOC3B
SCK5/SCK12/
SSLA2-B
IRQ11
ADTRG0#
35
PE4
MTIOC4D/MTIOC1A/
MTIOC4A/MTIOC7D
IRQ12
AN012
36
PE3
MTIOC4B/POE8#/
MTIOC1B/TOC3
CTS12#/RTS12#/
SS12#
IRQ11
AN011
37
PE2
MTIOC4A/MTIOC7A/
TIC3
RXD12/SMISO12/
SSCL12/RXDX12
IRQ7-DS
AN010/
CVREFC0
38
PE1
MTIOC4C/MTIOC3B
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12
IRQ9
AN009/
CMPC00
39
P47
IRQ15-DS
AN007
40
P46
IRQ14-DS
AN006
41
P45
IRQ13-DS
AN005
42
P42
IRQ10-DS
AN002
43
P41
IRQ9-DS
AN001
IRQ8-DS
AN000
28
VCC
29
30
44
COMP1
VSS
VREFL0
45
PJ7
P40
46
VREFH0
47
AVCC0
48
AVSS0
PJ6
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 53 of 123
RX660 Group
2. Electrical Characteristics
2.
Electrical Characteristics
2.1
Absolute Maximum Ratings
Table 2.1
Absolute Maximum Rating
Conditions: VSS = AVSS0 = 0 V
Item
Symbol
Value
Unit
VCC
–0.3 to +6.5
V
Analog power supply voltage
AVCC0*1
–0.3 to +6.5
V
Reference power supply voltage
VREFH0
–0.3 to AVCC0 + 0.3 (up to 6.5)
V
Vin
–0.3 to +6.5
V
Power supply voltage
Input voltage
P12, P13, P16, P17
P03, P05 to P7, P40 to P47, PJ6, PJ7
–0.3 to AVCC0 + 0.3 (up to 6.5)
Other than above
–0.3 to VCC + 0.3 (up to 6.5)
Junction temperature
Tj
–40 to +125
°C
Storage temperature
Tstg
–55 to +125
°C
Caution: Permanent damage to the LSI may result if absolute maximum ratings are exceeded.
Note 1. Insert capacitors of high frequency characteristics between the AVCC0 and AVSS0 pins. Place capacitors of about 0.1 µF as
close as possible to every power supply pin and use the shortest and heaviest possible traces.
2.2
Recommended Operating Conditions
Table 2.2
Recommended Operating Conditions (1)
Item
Power supply
voltage*1
Analog power supply voltage*1, *2
Input voltage
P12, P13, P16, P17
Symbol
Min.
Typ.
Max.
Unit
VCC
2.7
—
5.5
V
VSS
—
0
—
AVCC0
3.0
—
5.5
AVSS0
—
0
—
VREFH0
AVCC0 – 1.0
—
AVCC0
VREFL0
—
0
—
Vin
–0.3
—
5.8
–0.3
—
AVCC0 + 0.3
–0.3
—
VCC + 0.3
–40
—
85
–40
—
105
P03, P05 to P7, P40 to P47, PJ6, PJ7
Other than above
Operating
temperature
Junction
temperature
D version
Topr
G version
D version
Tj
G version
–40
—
105
–40
—
125
V
V
°C
°C
Note 1. Comply with the following potential condition: VCC ≤ AVCC0
Note 2. For details, see section 38.6.10, Voltage Range of Analog Power Supply Pins in the User’s Manual: Hardware.
Table 2.3
Recommended Operating Conditions (2)
Item
Decoupling capacitance to stabilize the internal voltage
Symbol
Value
CVCL
0.47 μF ± 30%*1
Note 1. Use a multilayer ceramic capacitor whose nominal capacitance is 0.47 μF and a capacitance tolerance is ±30% or better.
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 54 of 123
RX660 Group
2.3
2. Electrical Characteristics
DC Characteristics
Table 2.4
DC Characteristics (1)
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Item
Schmitt trigger
input voltage
IRQ input pin
MTU input pin
POE input pin
TMR input pin
CMTW input pin
RTC input pin
SCI input pin
CANFD input pin
REMC input pin
ADTRG# input pin
RES#, NMI
RIIC input pin
(except for SMBus)
Symbol
Min.
Typ.
Max.
Unit
VIH
0.8 × VCC
VIL
—
—
—
V
—
0.2 × VCC
ΔVT
0.06 × VCC
—
—
VIH
0.7 × VCC
—
—
VIL
—
—
0.3 × VCC
ΔVT
0.05 × VCC
—
—
Ports for 5 V tolerant
(P12, P13, P16, P17)
VIH
0.8 × VCC
—
—
VIL
—
—
0.2 × VCC
Other input pins excluding ports
for 5 V tolerant
VIH
0.8 × VCC
—
—
VIL
—
—
0.2 × VCC
0.9 × VCC
—
—
0.8 × VCC
—
—
High level input
MD pin, EMLE
voltage
EXTAL, RSPI input pin,
(except for Schmitt
WAIT#
trigger input pin)
D0 to D15
VIH
RIIC (SMBus)
Low level input
MD pin, EMLE
voltage
EXTAL, RSPI input pin,
(except for Schmitt
WAIT#
trigger input pin)
D0 to D15
RIIC (SMBus)
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
VIL
0.7 × VCC
—
—
2.1
—
—
—
—
0.1 × VCC
—
—
0.2 × VCC
—
—
0.3 × VCC
—
—
0.8
Test
Conditions
V
V
Page 55 of 123
RX660 Group
Table 2.5
2. Electrical Characteristics
DC Characteristics (2)
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Item
Output high voltage
P03, P05 to P7, P40 to P47,
PJ6, PJ7
Symbol
Min.
Typ.
Max.
Unit
VOH
AVCC0 – 0.5
—
—
V
IOH = –1 mA
VCC – 0.5
—
—
—
—
0.4
V
IOL = 3.0 mA
—
—
0.6
IOL = 6.0 mA
—
—
0.5
IOL = 1.0 mA
| Iin |
—
—
1.0
µA
Vin = 0 V
Vin = VCC
| ITSI |
—
—
5.0
µA
—
—
1.0
Vin = 0 V
Vin = VCC
RPU
10
—
100
kΩ
AVCC0 = 3.0 to 5.5 V
Vin = 0 V
10
—
100
5
—
50
kΩ
Vin = VCC = AVCC0
pF
Vbias = 0 V
Vamp = 20 mV
f = 1 MHz
Ta = 25°C
Other than above
Output low voltage
RIIC pins
VOL
Other than above
Input leakage current
RES#, EMLE
Three-state leakage
current (off state)
RIIC pins
Input pull-up resistors
Other than above
P03, P05 to P7, P40 to P47,
PJ6, PJ7
Other than above
Input pull-down
resistors
EMLE
RPD
Input capacitance
RIIC pins
Cin
—
—
16
PJ6, PJ7
—
—
12
Other than above
—
—
8
—
1.25
—
Output voltage of the VCL pin
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
VCL
Test Conditions
VCC = 2.7 to 5.5 V
Vin = 0 V
V
Page 56 of 123
RX660 Group
Table 2.6
2. Electrical Characteristics
DC Characteristics (3)
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Item
Supply
current*1
Symbol
ICC*2
Full operation
Typ.
Max.
G version
Typ.
Max.
—
68
—
76
Peripheral module clocks
are supplied
21
—
21
—
Peripheral module clocks
are stopped
12
—
12
—
CoreMark
Peripheral module clocks
are stopped
19
—
19
—
Sleep mode
Peripheral module clocks
are supplied
16
36
16
44
7.8
24
7.8
32
12
—
12
—
Normal operation
Normal operating mode
D version
All module clock stop mode
Reading from the code flash
memory while the data flash
memory is being
programmed
Increased by BGO
operation*3
Unit
Test Conditions
mA
ICLK = 120 MHz,
PCLKA = 120 MHz,
PCLKB = 60 MHz,
PCLKD = 60 MHz,
FCLK = 60 MHz,
BCLK = 60 MHz,
BCLK pin = 30 MHz
Software standby mode
0.9
9
0.9
14
mA
Deep software standby mode
15
23
15
32
µA
2.6
—
2.6
—
Increase current by operating RTC
When a standard
CL crystal is in use
Note 1. Supply current values are measured when all output pins are unloaded and all input pull-up resistors are disabled.
Note 2. ICC depends on the f (ICLK) as follows.
D version
ICC max = 0.500 × f + 8 (full operation in normal operating mode)
ICC typ = 0.144 × f + 4 (normal operation in normal operating mode)
ICC max = 0.234 × f + 8 (sleep mode)
G version
ICC max = 0.534 × f + 12 (full operation in normal operating mode)
ICC typ = 0.144 × f + 4 (normal operation in normal operating mode)
ICC max = 0.267 × f + 12 (sleep mode)
Note 3. This is an increase caused by programming/erasing of the data flash memory during execution of the user program from the
code flash memory.
Table 2.7
DC Characteristics (4)
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Item
A/D
Analog power
supply current
D/A
(2 channels)
CMPC
(4 channels)
TEMPS
Symbol
Typ.
Max.
Unit
AICC
0.9
1.4
mA
During
conversion
Waiting for
conversion
Waiting
Waiting
Waiting for
conversion
During
conversion
Waiting
Waiting
0.6
0.8
Waiting for
conversion
Waiting for
conversion
During
operation
Waiting
0.4
0.5
During
conversion
Waiting for
conversion
Waiting
During
operation
1.0
1.5
When waiting
0.4
7.7
In the module-stop state
0.4
6.5
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
µA
Page 57 of 123
RX660 Group
Table 2.8
2. Electrical Characteristics
DC Characteristics (5)
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
VRAM
2.7
—
—
V
SrVCC
0.02
—
8
ms/V
0.02
—
20
1.0
—
—
RAM retension voltage
VCC ramp rate at
power-on
At normal startup
Voltage monitoring 0 reset
enabled at startup*1, *2
VCC ramp rate at power fluctuation
dt/dVCC
Test Conditions
Figure 2.1
When VCC change
exceeds VCC ±10%
Note 1. When OFS1.LVDAS = 0.
Note 2. Settings of the OFS1 register are not read in boot mode or user boot mode, so turn on the power supply voltage with a ramp rate
at normal startup.
max = 8 ms/V
min = 0.02 ms/V
Figure 2.1
Table 2.9
max = 20 ms/V
VCC Ramp Rate at Power-On
Permissible Output Currents
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Item
Permissible output low current
(average value per pin)
Permissible output low current
(max. value per pin)
All output
pins*1
High drive
All output pins*1
Normal drive
All output
pins*2
Permissible output low current (total)
Total of all output pins
Permissible output high current
(average value per pin)
All output pins*1
Permissible output high current
(max. value per pin)
Permissible output high current (total)
Normal drive
All output pins*2
All output
pins*2
All output pins*1
All output
pins*2
Total of all output pins
Symbol
Min.
Typ.
Max.
Unit
IOL
—
—
2.0
mA
—
—
3.8
IOL
—
—
4.0
—
—
7.6
ΣIOL
—
—
80
mA
IOH
—
—
–2.0
mA
—
—
–3.8
IOH
—
—
–4.0
—
—
–7.6
—
—
–80
High drive
Normal drive
High drive
Normal drive
High drive
ΣIOH
mA
mA
mA
Caution: To protect the LSI’s reliability, the output current values should not exceed the values in this table.
Note 1. This is the value when normal driving ability is set with a pin for which normal driving ability is selectable.
Note 2. This is the value when high driving ability is set with a pin for which normal driving ability is selectable or the value of the pin to
which high driving ability is fixed.
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 58 of 123
RX660 Group
Table 2.10
2. Electrical Characteristics
Standard Output Characteristics (1)
Conditions: VCC = AVCC0 = 5.0 V,
VSS = AVSS0 = 0 V, Ta = 25°C
Item
Output high voltage
Normal drive output
Symbol
Min.
Typ.
Max.
Unit
VOH
—
4.97
—
V
—
4.94
—
IOH = –1.0 mA
—
4.87
—
IOH = –2.0 mA
—
4.74
—
IOH = –4.0 mA
—
4.98
—
IOH = –0.5 mA
—
4.97
—
IOH = –1.0 mA
—
4.94
—
IOH = –2.0 mA
—
4.87
—
—
0.02
—
—
0.04
—
IOL = 1.0 mA
—
0.09
—
IOL = 2.0 mA
—
0.18
—
IOL = 4.0 mA
—
0.01
—
IOL = 0.5 mA
—
0.03
—
IOL = 1.0 mA
—
0.05
—
IOL = 2.0 mA
—
0.10
—
IOL = 4.0 mA
High-drive output
Output low voltage
Normal drive output
VOL
High-drive output
Table 2.11
Test Conditions
IOH = –0.5 mA
IOH = –4.0 mA
V
IOL = 0.5 mA
Standard Output Characteristics (2)
Conditions: VCC = AVCC0 = 3.3V,
VSS = AVSS0 = 0 V, Ta = 25°C
Item
Output high voltage
Normal drive output
Symbol
Min.
Typ.
Max.
Unit
VOH
—
3.26
—
V
—
3.22
—
IOH = –1.0 mA
—
3.13
—
IOH = –2.0 mA
—
2.94
—
IOH = –4.0 mA
—
3.28
—
IOH = –0.5 mA
—
3.26
—
IOH = –1.0 mA
—
3.22
—
IOH = –2.0 mA
—
3.13
—
IOH = –4.0 mA
High-drive output
Output low voltage
Normal drive output
High-drive output
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
VOL
V
Test Conditions
IOH = –0.5 mA
—
0.03
—
—
0.06
—
IOL = 1.0 mA
IOL = 0.5 mA
—
0.12
—
IOL = 2.0 mA
—
0.25
—
IOL = 4.0 mA
—
0.02
—
IOL = 0.5 mA
—
0.03
—
IOL = 1.0 mA
—
0.07
—
IOL = 2.0 mA
—
0.13
—
IOL = 4.0 mA
Page 59 of 123
RX660 Group
Table 2.12
2. Electrical Characteristics
Thermal Resistance Value (Reference)
Item
Thermal resistance
Package
144-pin LFQFP (PLQP0144KA-B)
Symbol
Max.
Unit
ja
52.1
°C/W
JESD51-2 and
JESD51-7 compliant
Ta = 105°C
°C/W
JESD51-2 and
JESD51-7 compliant
100-pin LFQFP (PLQP0100KB-B)
80-pin LFQFP (PLQP0080KB-B)
52.0
64-pin LFQFP (PLQP0064KB-C)
50.8
48-pin LFQFP (PLQP0048KB-B)
58.4
144-pin LFQFP (PLQP0144KA-B)
Note:
51.3
jt
1.3
100-pin LFQFP (PLQP0100KB-B)
1.3
80-pin LFQFP (PLQP0080KB-B)
1.3
64-pin LFQFP (PLQP0064KB-C)
1.3
48-pin LFQFP (PLQP0048KB-B)
1.8
Test Conditions
The values are reference values when the 4-layer board is used. Thermal resistance depends on the number of layers or size of
the board. For details, refer to the JEDEC standards.
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 60 of 123
RX660 Group
2.4
2. Electrical Characteristics
AC Characteristics
Table 2.13
Operating Frequency
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Operating
frequency
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
System clock (ICLK)
f
—
—
120
MHz
Peripheral module clock (PCLKA)
—
—
120
Peripheral module clock (PCLKB)
—
—
60
Peripheral module clock (PCLKD)
—*1
—
60
Flash-IF clock (FCLK)
—*2
—
60
External bus clock (BCLK)
—
—
60
BCLK pin output
—
—
40
VCC ≥ 4.5 V,
High-drive output is
selected in the driving
ability control register.
—
—
32
VCC < 4.5 V,
High-drive output is
selected in the driving
ability control register.
Note 1. When the 12-bit A/D converter is to be used, the frequency of PCLKD must be set to at least 8 MHz.
Note 2. The FCLK must run at a frequency of at least 4 MHz when the contents of flash memory are to be changed.
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 61 of 123
RX660 Group
2. Electrical Characteristics
2.4.1
Reset Timing
Table 2.14
Reset Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
Power-on
tRESWP
2.0
—
—
ms
Figure 2.2
Deep software standby mode
tRESWD
0.6
—
—
ms
Figure 2.3
Software standby mode
tRESWS
0.3
—
—
ms
Programming or erasure of the code flash
memory, or programming, erasure or blank
checking of the data flash memory
tRESWF
200
—
—
µs
Other than above
tRESW
200
—
—
µs
Waiting time after release from the RES# pin reset
tRESWT
62
—
63
tLcyc
Internal reset time
(independent watchdog timer reset, watchdog timer reset,
software reset)
tRESW2
108
—
116
tLcyc
RES# pulse
width
Figure 2.2
VCC
RES#
tRESWP
Internal reset signal
(Low is valid)
tRESWT
Figure 2.2
Reset Input Timing at Power-On
tRESWD, tRESWS, tRESWF, tRESW
RES#
Internal reset signal
(Low is valid)
tRESWT
Figure 2.3
Reset Input Timing
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 62 of 123
RX660 Group
2. Electrical Characteristics
2.4.2
Clock Timing
Table 2.15
BCLK Pin Output Clock Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
BCLK pin output cycle time
tBcyc
25
—
—
ns
VCC ≥ 4.5 V
BCLK pin output high pulse width
tCH
ns
VCC ≥ 4.5 V
BCLK pin output low pulse width
tCL
31.25
—
—
7.5
—
—
10.625
—
—
7.5
—
—
10.625
—
—
Test Conditions
Figure 2.4
VCC < 4.5 V
VCC < 4.5 V
ns
VCC ≥ 4.5 V
VCC < 4.5 V
BCLK pin output rising time
tCr
—
—
5
ns
BCLK pin output falling time
tCf
—
—
5
ns
tBcyc
tCH
tCf
BCLK pin output
tCL
tCr
Test conditions: VOH = 0.7 × VCC, VOL = 0.3 × VCC, C = 30 pF
Figure 2.4
BCLK Pin Output Timing
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 63 of 123
RX660 Group
Table 2.16
2. Electrical Characteristics
EXTAL Clock Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
EXTAL external clock input cycle time
tEXcyc
41.66
—
—
ns
EXTAL external clock input frequency
fEXMAIN
—
—
24
MHz
EXTAL external clock input high pulse width
tEXH
15.83
—
—
ns
EXTAL external clock input low pulse width
tEXL
15.83
—
—
ns
EXTAL external clock rising time
tEXr
—
—
5
ns
EXTAL external clock falling time
tEXf
—
—
5
ns
Test
Conditions
Figure 2.5
tEXcyc
tEXH
tEXL
EXTAL external clock input
0.5 × VCC
tEXr
Figure 2.5
Table 2.17
tEXf
EXTAL External Clock Input Timing
Main Clock Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Item
Main clock oscillation frequency
Min.
Typ.
Max.
Unit
fMAIN
8
—
24
MHz
ms
ms
tMAINOSC
—
—
—*1
tMAINOSCWT
—
—
—*2
Main clock oscillator stabilization time (crystal)
Main clock oscillation stabilization waiting time (crystal)
Symbol
Test
Conditions
Figure 2.6
Note 1. When using a main clock, ask the manufacturer of the oscillator to evaluate its oscillation. Refer to the results of evaluation
provided by the manufacturer for the oscillation stabilization time.
Note 2. The number of cycles selected by the value of the MOSCWTCR.MSTS[7:0] bits determines the main clock oscillation
stabilization waiting time in accord with the formula below.
tMAINOSCWT = [(MSTS[7:0] bits × 32) + 10] / fLOCO
MOSCCR.MOSTP
tMAINOSC
Main clock oscillator output
tMAINOSCWT
OSCOVFSR.MOOVF
Main clock
Figure 2.6
Main Clock Oscillation Start Timing
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 64 of 123
RX660 Group
Table 2.18
2. Electrical Characteristics
LOCO and IWDT-Dedicated Low-Speed Clock Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Item
Symbol
LOCO clock cycle time
LOCO clock oscillation frequency
LOCO clock oscillation stabilization waiting time
Min.
Typ.
Max.
Unit
tLcyc
3.78
4.16
4.63
µs
fLOCO
216 (–10%)
240
264 (+10%)
kHz
tLOCOWT
—
—
44
µs
IWDT-dedicated low-speed clock cycle time
tILcyc
7.57
8.33
9.26
µs
IWDT-dedicated low-speed clock oscillation
frequency
fILOCO
108 (–10%)
120
132 (+10%)
kHz
IWDT-dedicated low-speed clock oscillation
stabilization waiting time
tILOCOWT
—
142
190
µs
Test
Conditions
Figure 2.7
Figure 2.8
LOCOCR.LCSTP
On-chip oscillator output
tLOCOWT
LOCO clock
Figure 2.7
LOCO Clock Oscillation Start Timing
ILOCOCR.ILCSTP
IWDT-dedicated on-chip
oscillator output
tILOCOWT
OSCOVFSR.ILCOVF
IWDT-dedicated
low-speed clock
Figure 2.8
IWDT-dedicated Low-Speed Clock Oscillation Start Timing
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 65 of 123
RX660 Group
Table 2.19
2. Electrical Characteristics
HOCO Clock Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
fHOCO
15.84
(–1.0%)
16
16.16
(+1.0%)
MHz
17.82
(–1.0%)
18
18.18
(+1.0%)
19.80
(–1.0%)
20
20.20
(+1.0%)
15.68
(–2.0%)
16
16.16
(+1.0%)
17.64
(–2.0%)
18
18.18
(+1.0%)
19.60
(–2.0%)
20
20.20
(+1.0%)
15.960
(–0.25%)
16
16.040
(+0.25%)
17.955
(–0.25%)
18
18.045
(+0.25%)
19.950
(–0.25%)
20
20.050
(+0.25%)
tHOCOWT
—
105
149
µs
Figure 2.9
HOCO clock power supply stabilization time
tHOCOP
—
—
150
µs
Figure 2.10
FLL stabilization waiting time
tFLLWT
—
—
1.8
ms
HOCO clock oscillation frequency
FLL not in use
FLL in use
HOCO clock oscillation stabilization waiting time
fHOCO
Test Conditions
–20°C ≤ Ta
Ta < –20°C
MHz
Sub-clock frequency
precision: ±50 ppm
HOCOCR.HCSTP
High-speed on-chip
oscillator output
tHOCOWT
OSCOVFSR.HCOVF
HOCO clock
Figure 2.9
HOCO Clock Oscillation Start Timing (Oscillation is Started by Setting the
HOCOCR.HCSTP Bit)
HOCOPCR.HOCOPCNT
HOCOCR.HCSTP
tHOCOP
Internal power supply for
high-speed on-chip oscillator
Figure 2.10
High-Speed On-Chip Oscillator Power Supply Control Timing
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 66 of 123
RX660 Group
Table 2.20
2. Electrical Characteristics
PLL Clock Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Item
PLL clock oscillation frequency
PLL clock oscillation stabilization waiting time
Symbol
Min.
fPLL
120
tPLLWT
—
Symbol
Min.
fSUB
—
Typ.
Max.
Unit
—
240
MHz
259
320
µs
Typ.
Max.
Unit
32.768
—
kHz
s
s
Test
Conditions
Figure 2.11
PLLCR2.PLLEN
PLL circuit output
tPLLWT
OSCOVFSR.PLOVF
PLL clock
Figure 2.11
Table 2.21
PLL Clock Oscillation Start Timing
Sub-Clock Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Item
Sub-clock oscillation frequency
Sub-clock oscillation stabilization time
Sub-clock oscillation stabilization waiting time
tSUBOSC
—
—
*1
tSUBOSCWT
—
—
*2
Test
Conditions
Figure 2.12
Note 1. When using a sub-clock, ask the manufacturer of the oscillator to evaluate its oscillation. Refer to the results of evaluation
provided by the manufacturer for the oscillation stabilization time.
Note 2. The number of cycles selected by the value of the SOSCWTCR.SSTS[7:0] bits determines the sub-clock oscillation stabilization
waiting time in accord with the formula below.
tSUBOSCWT = [(SSTS[7:0] bits × 16384) + 10] / fLOCO
SOSCCR.SOSTP
tSUBOSC
Sub-clock oscillator output
tSUBOSCWT
OSCOVFSR.SOOVF
Sub-clock
Figure 2.12
Sub-Clock Oscillation Start Timing
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 67 of 123
RX660 Group
2. Electrical Characteristics
2.4.3
Timing of Recovery from Low Power Consumption Modes
Table 2.22
Timing of Recovery from Low Power Consumption Modes (1)
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Item
Recovery time
from software
standby mode
*1
Crystal
resonator
connected to
main clock
oscillator
Symbol Min. Typ.
—
—
Max.
tSBYOSCWT*2
tSBYSEQ*3
{(MSTS[7:0] bit × 32)
+ 76} / 0.216
100 + 7 / fICLK +
2n / fMAIN
Main clock
oscillator
operating
tSBYMC
Main clock
oscillator and
PLL circuit
operating
tSBYPC
{(MSTS[7:0] bit × 32)
+ 138} / 0.216
100 + 7 / fICLK +
2n / fPLL
tSBYEX
352
100 + 7 / fICLK +
2n / fEXMAIN
Main clock
oscillator and
PLL circuit
operating
tSBYPE
639
100 + 7 / fICLK +
2n / fPLL
Sub-clock oscillator operating
tSBYSC
{(SSTS[7:0] bit ×
16384) + 13} / 0.216
+ 10 / fFCLK
100 + 4 / fICLK +
2n / fSUE
High-speed
on-chip
oscillator
operating
High-speed
on-chip
oscillator
operating
tSBYHO
454
100 + 7 / fICLK +
2n / fHOCO
High-speed
on-chip
oscillator
operating and
PLL circuit
operating
tSBYPH
741
100 + 7 / fICLK +
2n / fPLL
tSBYLO
338
100 + 7 / fICLK +
2n / fLOCO
External clock Main clock
input to main
oscillator
clock oscillator operating
Low-speed on-chip oscillator
operating*4
Unit
Test
Conditions
µs
Figure 2.13
Note 1. The time for recovery from software standby mode is determined by the value obtained by adding the oscillation stabilization
waiting time (tSBYOSCWT) and the time required for operations by the software standby release sequencer (tSBYSEQ).
Note 2. When several oscillators were running before the transition to software standby, the greatest value of the oscillation stabilization
waiting time tSBYOSCWT is selected.
Note 3. For n, the greatest value is selected from among the internal clock division settings.
Note 4. This condition applies when fICLK:fFCLK = 1:1, 2:1, or 4:1.
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 68 of 123
RX660 Group
2. Electrical Characteristics
Oscillator
(System clock)
tSBYOSCWT
tSBYSEQ
Oscillator
(Other than the system clock)
ICLK
IRQ
Software standby mode
tSBYMC, tSBYEX, tSBYPC, tSBYPE,
tSBYPH, tSBYSC, tSBYHO, tSBYLO
When stabilization of the system clock oscillator is slower
Oscillator
(System clock)
tSBYOSCWT
tSBYSEQ
Oscillator
(Other than the system clock)
tSBYOSCWT
ICLK
IRQ
Software standby mode
tSBYMC, tSBYEX, tSBYPC, tSBYPE,
tSBYPH, tSBYSC, tSBYHO, tSBYLO
When stabilization of an oscillator other than the system clock is slower
Figure 2.13
Software Standby Mode Recovery Timing
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 69 of 123
RX660 Group
Table 2.23
2. Electrical Characteristics
Timing of Recovery from Low Power Consumption Modes (2)
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Item
Symbol
Recovery time from deep software standby mode
Waiting time after recovery from deep software standby mode
Min.
Typ.
Max.
Unit
Test
Conditions
Figure 2.14
tDSBY
—
—
0.9
ms
tDSBYWT
31
—
32
tLcyc
Oscillator
IRQ
Deep software standby reset
(Low is valid)
Internal reset
(Low is valid)
Deep software standby mode
tDSBY
tDSBYWT
Reset exception handling start
Figure 2.14
Deep Software Standby Mode Recovery Timing
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 70 of 123
RX660 Group
2. Electrical Characteristics
2.4.4
Control Signal Timing
Table 2.24
Control Signal Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Symbol
Min.*1
Typ.
Max.
Unit
NMI pulse width
tNMIW
200
—
—
ns
2 × tPBcyc ≤ 200 ns, Figure 2.15
IRQ pulse width
tIRQW
ns
2 × tPBcyc ≤ 200 ns, Figure 2.16
Item
2 × tPBcyc
—
—
200
—
—
2 × tPBcyc
—
—
Test Conditions*1
2 × tPBcyc > 200 ns, Figure 2.15
2 × tPBcyc > 200 ns, Figure 2.16
Note 1. tPBcyc: PCLKB cycle
NMI
Figure 2.15
tNMIW
tNMIW
tIRQW
tIRQW
NMI Interrupt Input Timing
IRQn
Figure 2.16
IRQ Interrupt Input Timing
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 71 of 123
RX660 Group
2. Electrical Characteristics
2.4.5
Bus Timing
Table 2.25
Bus Timing (1)
Conditions: 4.5 V ≤ VCC ≤ 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Symbol
Min.
Max.
Unit
Address delay time
Item
tAD
—
12.5
ns
Byte control delay time
tBCD
—
12.5
ns
CS# delay time
tCSD
—
12.5
ns
ALE delay time
tALED
—
12.5
ns
RD# delay time
tRSD
—
12.5
ns
Read data setup time
tRDS
12.5
—
ns
Read data hold time
tRDH
0
—
ns
WR# delay time
tWRD
—
12.5
ns
Write data delay time
tWDD
—
12.5
ns
Write data hold time
tWDH
0
—
ns
WAIT# setup time
tWTS
12.5
—
ns
WAIT# hold time
tWTH
0
—
ns
Table 2.26
Test Conditions
Figure 2.17 to
Figure 2.22
Figure 2.23
Bus Timing (2)
Conditions: 2.7 V ≤ VCC < 4.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Symbol
Min.
Max.
Unit
Address delay time
Item
tAD
—
25
ns
Byte control delay time
tBCD
—
25
ns
CS# delay time
tCSD
—
25
ns
ALE delay time
tALED
—
25
ns
RD# delay time
tRSD
—
25
ns
Read data setup time
tRDS
25
—
ns
Read data hold time
tRDH
0
—
ns
WR# delay time
tWRD
—
25
ns
Write data delay time
tWDD
—
25
ns
Write data hold time
tWDH
0
—
ns
WAIT# setup time
tWTS
25
—
ns
WAIT# hold time
tWTH
0
—
ns
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Test Conditions
Figure 2.17 to
Figure 2.22
Figure 2.23
Page 72 of 123
RX660 Group
2. Electrical Characteristics
Data cycle
Address cycle
Ta1
Ta1
Tan
TW1
TW2
TW3
TW4
Tend
TW5
Tn1
Tn2
BCLK
tAD
Address bus
tAD
tRDS
tAD
tRDH
Address bus/
data bus
tALED
tALED
Address latch
(ALE)
tRSD
tRSD
Data read
(RD#)
Figure 2.17
tCSD
tCSD
Chip select
(CS1#)
Address/Data Multiplexed Bus Read Access Timing
Data cycle
Address cycle
Ta1
Ta1
Tan
TW1
TW2
TW3
TW4
TW5
Tend
Tn1
Tn2
Tn3
BCLK
tAD
Address bus
tAD
tAD
tWDD
tWDH
Address bus/
data bus
tALED
tALED
Address latch
(ALE)
tWRD
tWRD
Data write
(WRm#)
tCSD
Chip select
(CS1#)
Figure 2.18
tCSD
Address/Data Multiplexed Bus Write Access Timing
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2. Electrical Characteristics
CSRWAIT:2
RDON:1
CSROFF:2
CSON:0
TW1
TW2
Tend
Tn1
Tn2
BCLK
Byte strobe mode
tAD
tAD
tAD
tAD
tBCD
tBCD
tCSD
tCSD
A20 to A0
1-write strobe mode
A20 to A1
BC1# to BC0#
Common to both byte strobe mode
and 1-write strobe mode
CS3# to CS0#
tRSD
tRSD
RD# (Read)
tRDS
tRDH
D15 to D0 (Read)
Figure 2.19
External Bus Timing/Normal Read Cycle (Bus Clock Synchronized)
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2. Electrical Characteristics
CSWWAIT:2
WRON:1
WDON:1 *1
CSWOFF:2
WDOFF:1 *1
CSON:0
TW1
TW2
Tend
Tn1
Tn2
BCLK
Byte strobe mode
tAD
tAD
tAD
tAD
tBCD
tBCD
tCSD
tCSD
A20 to A0
1-write strobe mode
A20 to A1
BC1# to BC0#
Common to both byte strobe mode
and 1-write strobe mode
CS3# to CS0#
tWRD
tWRD
WR1# to WR0#, WR# (Write)
tWDD
tWDH
D15 to D0 (Write)
Note 1. Be sure to specify WDON and WDOFF as at least one cycle of BCLK.
Figure 2.20
External Bus Timing/Normal Write Cycle (Bus Clock Synchronized)
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2. Electrical Characteristics
CSRWAIT:2
CSON:0
CSPRWAIT:2
CSPRWAIT:2
RDON:1
RDON:1
TW1
TW2
Tend
CSPRWAIT:2
RDON:1
Tpw1
Tpw2
Tend
CSROFF:2
RDON:1
Tpw1
Tpw2
Tend
Tpw1
Tpw2
Tend
Tn1
Tn2
BCLK
Byte strobe mode
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tAD
A20 to A0
1-write strobe mode
A20 to A1
tBCD
tBCD
tCSD
tCSD
BC1# to BC0#
Common to both byte strobe mode
and 1-write strobe mode
CS3# to CS0#
tRSD
tRSD
tRSD
tRSD
tRSD
tRSD
tRSD
tRSD
RD# (Read)
tRDS
tRDH
tRDS
tRDH
tRDS
tRDH
tRDS
tRDH
D15 to D0 (Read)
Figure 2.21
External Bus Timing/Page Read Cycle (Bus Clock Synchronized)
CSPWWAIT:2
CSWWAIT:2
WRON:1
WDON:1 *1
WDOFF:1 *1
CSON:0 TW1
TW2
Tend
Tdw1
WRON:1
WDON:1 *1
Tpw1
CSPWWAIT:2
WDOFF:1 *1
Tpw2
Tend
Tdw1
WRON:1
WDON:1 *1
Tpw1
CSWOFF:2
WDOFF:1 *1
Tpw2
Tend
Tn1
Tn2
BCLK
Byte strobe mode
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tAD
A20 to A0
1-write strobe mode
A20 to A1
tBCD
tBCD
tCSD
tCSD
BC1# to BC0#
Common to both byte strobe mode
and 1-write strobe mode
CS3# to CS0#
tWRD
tWRD
tWRD
tWRD
tWRD
tWRD
WR1# to WR0#, WR# (Write)
tWDD
tWDH
tWDD
tWDH
tWDD
tWDH
D15 to D0 (Write)
Note 1. Be sure to specify WDON and WDOFF as at least one cycle of BCLK.
Figure 2.22
External Bus Timing/Page Write Cycle (Bus Clock Synchronized)
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2. Electrical Characteristics
CSRWAIT:3
CSWWAIT:3
TW1
TW2
TW3
(Tend)
Tend
Tn1
Tn2
BCLK
A20 to A0
CS3# to CS0#
RD# (Read)
WR# (Write)
External wait
tWTS tWTH
tWTS tWTH
WAIT#
Figure 2.23
External Bus Timing/External Wait Control
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RX660 Group
2.4.6
2. Electrical Characteristics
Timing of On-Chip Peripheral Modules
2.4.6.1
I/O Port
Table 2.27
I/O Port Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
I/O ports
Input data pulse width
Symbol
Min.
Max.
Unit*1
Test
Conditions
tPRW
1.5
—
tPBcyc
Figure 2.24
Note 1. tPBcyc: PCLKB cycle
PCLKB
Port
tPRW
Figure 2.24
I/O Port Input Timing
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2. Electrical Characteristics
2.4.6.2
TMR
Table 2.28
TMR Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
TMR
Timer clock pulse width
Single-edge setting
Both-edge setting
Max.
Unit*1
Test
Conditions
1.5
—
tPBcyc
Figure 2.25
2.5
—
Symbol
Min.
tTMCWH,
tTMCWL
Note 1. tPBcyc: PCLKB cycle
PCLKB
TMCI0 to TMCI3
tTMCWL
Figure 2.25
TMR Clock Input Timing
2.4.6.3
CMTW
Table 2.29
tTMCWH
CMTW Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
CMTW
Input capture input pulse
width
Single-edge setting
Both-edge setting
Symbol
Min.
Max.
Unit*1
Test
Conditions
tCMTWTICW
1.5
—
tPBcyc
Figure 2.26
2.5
—
Note 1. tPBcyc: PCLKB cycle
PCLKB
Input capture
input
Figure 2.26
tCMTWICW
CMTW Input Capture Input Timing
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RX660 Group
2. Electrical Characteristics
2.4.6.4
MTU
Table 2.30
MTU Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
MTU
Input capture input pulse
width
Timer clock pulse width
Symbol
Single-edge setting
tMTICW
Both-edge setting
Single-edge setting
Both-edge setting
Phase counting
mode
tMTCKWH,
tMTCKWL
Max.
Unit*1
Test
Conditions
1.5
—
tPAcyc
Figure 2.27
2.5
—
tPAcyc
Figure 2.28
Min.
1.5
—
2.5
—
2.5
—
Note 1. tPAcyc: PCLKA cycle
PCLKA
Input capture
input
Figure 2.27
tMTICW
MTU Input Capture Input Timing
PCLKA
MTCLKA to
MTCLKD,
MTIOC1A
tMTCKWL
Figure 2.28
tMTCKWH
MTU Clock Input Timing
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2.4.6.5
Table 2.31
2. Electrical Characteristics
POE3
POE3 Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
POE
Symbol
Min. Typ.
Unit*1
Max.
Test Conditions
POEn# input pulse width
(n = 0, 4, 8, 10, 11)
tPOEW
1.5
—
—
Output
disable time
Transition of the POEn#
signal level
tPOEDI
—
—
5 PCLKB + 0.24
µs
Figure 2.30
When detecting falling edges
(ICSRm.POEnM[3:0] = 0000b
(m = 1 to 5; n = 0, 4, 8, 10, 11))
Simultaneous conduction
of output pins
tPOEDO
—
—
3 PCLKB + 0.2
µs
Figure 2.31
Register setting
tPOEDS
—
—
1 PCLKB + 0.2
µs
Figure 2.32
Time for access to the register
is not included.
tPOEDOS
—
—
21
µs
Figure 2.33
Oscillation stop detection
tPBcyc Figure 2.29
Note 1. tPBcyc: PCLKB cycle
PCLKB
POEn# input
(n = 0, 4, 8, 10, 11)
tPOEW
Figure 2.29
POE# Pin Input Timing
POEn# input
(n = 0, 4, 8, 10, 11)
tPOEW
Outputs disabled
MTU PWM output pins
tPOEDI
Figure 2.30
Output Disable Time for POE in Response to Transition of the POEn# Signal Level
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2. Electrical Characteristics
Simultaneous active-level outputs detected*1
Outputs
disabled
MTU PWM output pins
tPOEDO
Note 1.
Figure 2.31
When the active level is set to low.
Output Disable Time for POE in Response to the Simultaneous Conduction of Output
Pins
Corresponding bit in
the SPOER register
Outputs disabled
MTU PWM output pins
tPOEDS
Figure 2.32
Output Disable Time for POE in Response to the Register Setting
Main clock
Oscillation stop detection
signal (internal signal)
Outputs disabled
MTU PWM output pins
tPOEDOS
Figure 2.33
Output Disable Time for POE in Response to the Oscillation Stop Detection
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RX660 Group
2.4.6.6
2. Electrical Characteristics
A/D Converter Trigger
Table 2.32
A/D Converter Trigger Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
A/D
converter
A/D converter trigger input pulse width
Symbol
Min.
Max.
Unit*1
Test
Conditions
tTRGW
1.5
—
tPBcyc
Figure 2.34
Note 1. tPBcyc: PCLKB cycle
PCLKB
ADTRG0#
tTRGW
Figure 2.34
A/D Converter Trigger Input Timing
2.4.6.7
CAC
Table 2.33
CAC Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item*1, *2
CAC
CACREF input pulse width
tPBcyc ≤ tCAC
tPBcyc > tCAC
Symbol
Min.*1, *2
Max.
Unit
tCACREF
4.5 tCAC + 3 tPBcyc
—
ns
5 tCAC + 6.5 tPBcyc
—
Test
Conditions
Note 1. tPBcyc: PCLKB cycle
Note 2. tCAC: CAC count clock source cycle
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2.4.6.8
Table 2.34
2. Electrical Characteristics
SCI
SCIk, SCIh, and SCIm Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
SCIk, SCIh
Input clock cycle
Asynchronous
Symbol
Min.
Max.
Unit*1
tScyc
4
—
tPBcyc
6
—
Clock
synchronous
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
—
5
ns
Input clock fall time
tSCKf
—
5
ns
tScyc
6
—
tPBcyc
Asynchronous
(SCIh)
8
—
Clock
synchronous
4
—
Output clock cycle
SCIm
Asynchronous
(SCIk)
Output clock pulse width
tSCKW
0.4
0.6
tScyc
Output clock rise time
tSCKr
—
5
ns
Output clock fall time
tSCKf
—
5
ns
ns
Transmit data delay time
Clock
synchronous
tTXD
—
28
—
33
Receive data setup time
Clock
synchronous
tRXS
15
—
ns
Receive data hold time
Clock
synchronous
tRXH
5
—
ns
Input clock cycle
Asynchronous
tScyc
4
—
tPAcyc
6
—
Clock
synchronous
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
—
5
ns
Input clock fall time
tSCKf
—
5
ns
tScyc
6
—
tPAcyc
4
—
Asynchronous
Clock
synchronous
Figure 2.35
VCC ≥ 4.5 V
Figure 2.36
Figure 2.35
Output clock pulse width
tSCKW
0.4
0.6
tScyc
Output clock rise time
tSCKr
—
5
ns
tSCKf
—
5
ns
tTXD
—
15
ns
—
20
VCC < 4.5 V
—
28
VCC ≥ 4.5 V
—
33
VCC < 4.5 V
Output clock fall time
Transmit data delay time
Master
Slave
Figure 2.36
VCC < 4.5 V
Input clock pulse width
Output clock cycle
Test Conditions
Receive data setup time
Clock
synchronous
tRXS
20
—
ns
Receive data hold time
Clock
synchronous
tRXH
5
—
ns
VCC ≥ 4.5 V
Figure 2.36
Figure 2.36
Note 1. tPBcyc: PCLKB cycle; tPAcyc: PCLKA cycle
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2. Electrical Characteristics
tSCKW
tSCKr
tSCKf
SCKn
(n = 0 to 12)
tScyc
Figure 2.35
SCK Clock Input Timing
SCKn
tTXD
TXDn
tRXS tRXH
RXDn
(n = 0 to 12)
Figure 2.36
SCI Input/Output Timing: Clock Synchronous Mode
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Table 2.35
2. Electrical Characteristics
Simple IIC Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
High-drive output is selected by the drive capacity control register.
Symbol
Min.
Max.
Unit
Test
Conditions
tSr
—
1000
ns
Figure 2.37
SSCL, SSDA input fall time
tSf
—
300
ns
SSCL, SSDA input spike pulse removal time
tSP
0
4 × tPcyc
ns
Data input setup time
tSDAS
250
—
ns
Data input hold time
tSDAH
0
—
ns
SSCL, SSDA capacitive load
Cb*1
—
400
pF
SSCL, SSDA input rise time
tSr
—
300
ns
SSCL, SSDA input fall time
tSf
—
300
ns
SSCL, SSDA input spike pulse removal time
tSP
0
4 × tPcyc
ns
Data input setup time
tSDAS
100
—
ns
Data input hold time
tSDAH
0
—
ns
SSCL, SSDA capacitive load
Cb*1
—
400
pF
Item
Simple IIC
(Standard-mode)
SSCL, SSDA input rise time
Simple IIC
(Fast-mode)
Note:
tPcyc refers to the period of PCLKA in SCI10 and SCI11, and of PCLKB in SCI0 to SCI9, and SCI12.
Note 1. Cb is the total capacitance of the bus lines.
VIH
SSDA0 to SSDA12
VIL
tBUF
tSCLH
tSTAS
tSTAH
tSTOS
tSP
SSCL0 to SSCL12
P*1
S*1
tSCLL
tSr
tSf
tSCL
tSDAS
tSDAH
Note 1. S, P, and Sr indicate the following conditions.
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.37
P*1
Sr*1
Test conditions
VIH = 0.7 × VCC, VIL = 0.3 × VCC
VOL = 0.6 V, IOL = 6 mA
Simple IIC Bus Interface Input/Output Timing
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RX660 Group
Table 2.36
2. Electrical Characteristics
Simple SPI Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Simple
SPI
Item
Symbol
Min.
Max.
Unit
SCK clock cycle output (master)
tSPcyc
4
—
tPcyc
6
—
SCK clock cycle input (slave)
SCK clock high pulse width
tSPCKWH
0.4
0.6
tSPcyc
SCK clock low pulse width
tSPCKWL
0.4
0.6
tSPcyc
tSPCKr, tSPCKf
—
20
ns
Data input setup time
tSU
33.3
—
ns
Data input hold time
tH
33.3
—
ns
SS input setup time
tLEAD
1
—
tSPcyc
SS input hold time
tLAG
1
—
tSPcyc
Data output delay time
tOD
—
33.3
ns
Data output hold time
tOH
–10
—
ns
SCK clock rise/fall time
Data rise/fall time
tDr, tDf
—
16.6
ns
tSSLr, tSSLf
—
16.6
ns
Slave access time
tSA
—
5
tPcyc
Slave output release time
tREL
—
5
tPcyc
SS input rise/fall time
Note:
Test
Conditions
Figure 2.38
Figure 2.39 to
Figure 2.42
Figure 2.41,
Figure 2.42
tPcyc refers to the period of PCLKA in SCI10 and SCI11, and of PCLKB in SCI0 to SCI9, and SCI12.
tSPCKr
tSPCKWH
VOH
VOH
SCKn output
(master)
VOL
tSPCKf
VOH
VOH
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
VIH
SCKn input
(slave)
VIH
VIL
(n = 0 to 12)
tSPCKf
VIH
VIL
tSPCKWL
VIH
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Figure 2.38
Simple SPI Clock Timing
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2. Electrical Characteristics
tTD
SSn#
output
tLEAD
tLAG
tSSLr, tSSLf
SCKn
CKPOL = 0
output
SCKn
CKPOL = 1
output
tSU
SMISOn
input
tH
MSB IN
DATA
tDr, tDf
SMOSIn
output
tOH
MSB OUT
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
(n = 0 to 12)
Figure 2.39
Simple SPI Timing (Master, CKPH = 1)
tTD
SSn#
output
tLEAD
tLAG
tSSLr, tSSLf
SCKn
CKPOL = 1
output
SCKn
CKPOL = 0
output
tSU
SMISOn
input
tH
MSB IN
tOH
SMOSIn
output
DATA
LSB IN
tOD
MSB OUT
MSB IN
tDr, tDf
DATA
LSB OUT
IDLE
MSB OUT
(n = 0 to 12)
Figure 2.40
Simple SPI Timing (Master, CKPH = 0)
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2. Electrical Characteristics
tTD
SSn#
input
tLEAD
tLAG
SCKn
CKPOL = 0
input
SCKn
CKPOL = 1
input
tSA
tOH
SMISOn
output
tOD
MSB OUT
tSU
SMOSIn
input
tREL
DATA
LSB OUT
tH
MSB OUT
tDr, tDf
MSB IN
DATA
LSB IN
MSB IN
(n = 0 to 12)
Figure 2.41
Simple SPI Timing (Slave, CKPH = 1)
tTD
SSn#
input
tLEAD
tLAG
SCKn
CKPOL = 1
input
SCKn
CKPOL = 0
input
tSA
tOH
tOD
SMISOn
output
MSB OUT
tSU
SMOSIn
input
tREL
DATA
tH
MSB IN
LSB OUT
MSB OUT
tDr, tDf
DATA
LSB IN
MSB IN
(n = 0 to 12)
Figure 2.42
Simple SPI Timing (Slave, CKPH = 0)
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RX660 Group
2.4.6.9
2. Electrical Characteristics
RSCI
Table 2.37
RSCI Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
RSCI
Input clock cycle
Asynchronous
Symbol
Min.
Max.
Unit*1
tScyc
4
—
tPAcyc
2
—
Clock
synchronous
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
—
5
ns
Input clock fall time
tSCKf
—
5
ns
tScyc
6
—
tPAcyc
2
—
Output clock cycle
Asynchronous
Clock
synchronous
Output clock pulse width
tSCKW
0.4
0.6
tScyc
Output clock rise time
tSCKr
—
5
ns
Output clock fall time
Receive data setup time
Master
tSCKf
—
5
ns
tRXS
–1.5
—
ns
3.5
—
2.5
—
11
—
2.5
—
Slave
Receive data hold time
Master
tRXH
Slave
Transmit data delay time
Master
tTXD
Slave
Test Conditions
Figure 2.43
VCC ≥ 4.5 V
Figure 2.44
VCC < 4.5 V
Figure 2.44
ns
—
4
—
17
ns
VCC ≥ 4.5 V
—
22
VCC < 4.5 V
Figure 2.44
Note 1. tPAcyc: PCLKA cycle; tScyc: SCK cycle
tSCKW
tSCKr
tSCKf
SCKn
(n = 010, 011)
tScyc
Figure 2.43
SCK Clock Input Timing
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 90 of 123
RX660 Group
2. Electrical Characteristics
SCKn
tTXD
TXDn
tRXS tRXH
RXDn
(n = 010, 011)
Figure 2.44
RSCI Input/Output Timing: Clock Synchronous Mode
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 91 of 123
RX660 Group
Table 2.38
2. Electrical Characteristics
Simple IIC Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
High-drive output is selected by the drive capacity control register.
Simple IIC
(Standard-mode)
Simple IIC
(Fast-mode)
Item
Symbol
Min.
Max.
Unit
Test
Conditions
SSCL, SSDA input rise time
tSr
—
1000
ns
Figure 2.45
SSCL, SSDA input fall time
tSf
—
300
ns
SSCL, SSDA input spike pulse removal time
tSP
0
4 × tPAcyc
ns
Data input setup time
tSDAS
250
—
ns
Data input hold time
tSDAH
0
—
ns
SSCL, SSDA capacitive load
C b* 1
—
400
pF
SSCL, SSDA input rise time
tSr
—
300
ns
SSCL, SSDA input fall time
tSf
—
300
ns
SSCL, SSDA input spike pulse removal time
tSP
0
4 × tPAcyc
ns
Data input setup time
tSDAS
100
—
ns
Data input hold time
tSDAH
0
—
ns
SSCL, SSDA capacitive load
C b* 1
—
400
pF
Note:
tPAcyc: PCLKA cycle
Note 1. Cb is the total capacitance of the bus lines.
VIH
SSDA010, SSDA011
VIL
tBUF
tSCLH
tSTAS
tSTAH
tSTOS
tSP
SSCL010, SSCL011
P*1
S*1
tSCLL
tSr
tSf
tSCL
tSDAS
tSDAH
Note 1. S, P, and Sr indicate the following conditions.
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.45
P*1
Sr*1
Test conditions
VIH = 0.7 × VCC, VIL = 0.3 × VCC
VOL = 0.6 V, IOL = 6 mA
Simple IIC Bus Interface Input/Output Timing
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 92 of 123
RX660 Group
Table 2.39
2. Electrical Characteristics
Simple SPI Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Symbol
Min.
Max.
Unit*1
tSPcyc
2
—
tPAcyc
2
—
SCK clock high pulse width
tSPCKWH
0.4
0.6
tSPcyc
SCK clock low pulse width
tSPCKWL
0.4
0.6
tSPcyc
Item
Simple
SPI
SCK clock cycle output (master)
SCK clock cycle input (slave)
SCK clock rise/fall time
Output
tSPCKr, tSPCKf
—
5
ns
—
1
µs
0.5
—
ns
2.5
—
11
—
Slave
2.5
—
Master
—
4
—
17
Input
Data input setup time
Master
Data input hold time
Master
tSU
Slave
Data output delay time
tH
tOD
Slave
Data output hold time
Master
tOH
Slave
Data rise/fall time
Output
tDr, tDf
22
—
0
—
ns
ns
Figure 2.47 to Figure 2.50
VCC ≥ 4.5V
VCC < 4.5V
ns
Figure 2.47 to
Figure 2.50
Figure 2.47 to Figure 2.50
—
5
ns
1
—
tSA
—
5
tPAcyc
Slave output release time
tREL
—
5
tPAcyc
SS input setup time
tLEAD
1
—
tSPcyc
SS input hold time
tLAG
1
—
tSPcyc
tSSLr, tSSLf
—
1
µs
SS input rise/fall time
Figure 2.46
Figure 2.47 to Figure 2.50
—
Input
Slave access time
—
–1
Test Conditions
Figure 2.49, Figure 2.50
Figure 2.47 to Figure 2.50
Note 1. tPAcyc: PCLKA cycle
tSPCKr
tSPCKWH
VOH
VOH
SCKn output
(master)
VOL
tSPCKf
VOH
VOH
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
VIH
SCKn input
(slave)
VIH
VIL
(n = 010, 011)
tSPCKf
VIH
VIL
tSPCKWL
VIH
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Figure 2.46
Simple SPI Clock Timing
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 93 of 123
RX660 Group
2. Electrical Characteristics
tTD
SSn#
output
tLEAD
tLAG
tSSLr, tSSLf
SCKn
CPOL = 0
output
SCKn
CPOL = 1
output
tSU
SMISOn
input
tH
MSB IN
DATA
tDr, tDf
SMOSIn
output
tOH
MSB OUT
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
(n = 010, 011)
Figure 2.47
Simple SPI Timing (Master, CPHA = 0)
tTD
SSn#
output
tLEAD
tLAG
tSSLr, tSSLf
SCKn
CPOL = 0
output
SCKn
CPOL = 1
output
tSU
SMISOn
input
tH
MSB IN
tOH
SMOSIn
output
DATA
LSB IN
tOD
MSB OUT
MSB IN
tDr, tDf
DATA
LSB OUT
IDLE
MSB OUT
(n = 010, 011)
Figure 2.48
Simple SPI Timing (Master, CPHA = 1)
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 94 of 123
RX660 Group
2. Electrical Characteristics
tTD
SSn#
input
tLEAD
tLAG
SCKn
CPOL = 0
input
SCKn
CPOL = 1
input
tSA
tOH
SMISOn
output
tOD
MSB OUT
tSU
SMOSIn
input
tREL
DATA
LSB OUT
tH
MSB OUT
tDr, tDf
MSB IN
DATA
LSB IN
MSB IN
(n = 010, 011)
Figure 2.49
Simple SPI Timing (Slave, CPHA = 0)
tTD
SSn#
input
tLEAD
tLAG
SCKn
CPOL = 0
input
SCKn
CPOL = 1
input
tSA
tOH
tOD
SMISOn
output
MSB OUT
tSU
SMOSIn
input
tREL
DATA
tH
MSB IN
LSB OUT
MSB OUT
tDr, tDf
DATA
LSB IN
MSB IN
(n = 010, 011)
Figure 2.50
Simple SPI Timing (Slave, CPHA = 1)
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 95 of 123
RX660 Group
2.4.6.10
Table 2.40
2. Electrical Characteristics
RSPI
RSPI Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
RSPI
RSPCK clock cycle
Symbol
Master
tSPcyc
Slave
RSPCK clock high
pulse width
Master
tSPCKWH
Slave
RSPCK clock low
pulse width
Master
tSPCKWL
Slave
RSPCK clock rise/
fall time
Data input setup
time
Output
Input
Master
Master
0.4
0.6
tSPcyc
(tSPcyc – tSPCKr
– tSPCKf) / 2 – 3
—
ns
tSPcyc
ns
—
1
µs
tSU
6
—
ns
11
—
VCC < 4.5 V
8.3
—
Figure 2.52 to Figure 2.57
0
—
ns
PCLKA division ratio set
to a value
other than 1/2
tH
tPAcyc
—
ns
8.3
—
Master
Data output hold
time
Master
tLEAD
tLAG
tOD
Successive
transmission delay
time
Master
MOSI and MISO
rise/fall time
Output
tOH
Slave
tTD
Slave
Input
1
8
tSPcyc
4
—
tPAcyc
1
8
tSPcyc
4
—
tPAcyc
—
6.3
ns
VCC ≥ 4.5 V
—
11.3
VCC < 4.5 V
28
VCC ≥ 4.5 V
—
33
0
—
0
—
tSPcyc + 2 ×
tPAcyc
8 × tSPcyc
+ 2 × tPAcyc
Figure 2.52
to
Figure 2.57
Figure 2.52
to
Figure 2.57
VCC < 4.5 V
ns
Figure 2.52 to Figure 2.57
ns
4 × tPAcyc
—
—
5
ns
—
1
µs
tSSLr,
tSSLf
—
5
ns
—
1
µs
tSA
—
28
ns
—
33
—
28
—
33
tREL
VCC ≥ 4.5 V
—
tDr, tDf
Input
Output
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
ns
tHF
Master
Slave output release time
—
PCLKA division ratio set
to 1/2
Master
Slave access time
(tSPcyc – tSPCKr
– tSPCKf) / 2 – 3
Figure 2.51
5
Slave
SSL rise/fall time
—
—
0.6
Slave
Data output delay
time
tPAcyc
2
4
Test Conditions*2
—
Slave
SSL hold time
Unit*1
0.4
Slave
SSL setup time
Max.*1
tSPCKr,
tSPCKf
Slave
Data input hold time
Min.*1
VCC ≥ 4.5 V
VCC < 4.5 V
ns
Figure 2.56,
Figure 2.57
VCC ≥ 4.5 V
VCC < 4.5 V
Page 96 of 123
RX660 Group
2. Electrical Characteristics
Note 1. tPAcyc: PCLKA cycle
Note 2. When a letter “-A”, “-B”, etc. to indicate group membership is appended to the pin name, each pin is recommended to use in
combination with the pins in the same group. All RSPI AC timings are measured in combination with the pins in the same group.
tSPCKr
tSPCKWH
VOH
VOH
RSPCK output
(master)
VOL
tSPCKf
VOH
VOH
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
VIH
VIH
RSPCK input
(slave)
VIL
tSPCKf
VIH
VIH
VIL
tSPCKWL
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Figure 2.51
RSPI Clock Timing
tTD
SSLA0 to
SSLA3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
tSU
MISOA
input
tH
MSB IN
tDr, tDf
MOSIA
output
Figure 2.52
DATA
tOH
MSB OUT
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKA Division Ratio Set to a Value Other
Than 1/2)
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Mar 18, 2022
Page 97 of 123
RX660 Group
2. Electrical Characteristics
tTD
SSLA0 to
SSLA3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
tSU
MISOA
input
tHF
MSB IN
DATA
tDr, tDf
MOSIA
output
Figure 2.53
tHF
tOH
MSB OUT
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKA Division Ratio Set to 1/2)
tTD
SSLA0 to
SSLA3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
tSU
MISOA
input
tH
MSB IN
tOH
MOSIA
output
Figure 2.54
DATA
LSB IN
tOD
MSB OUT
MSB IN
tDr, tDf
DATA
LSB OUT
IDLE
MSB OUT
RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKA Division Ratio Set to a Value Other
Than 1/2)
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 98 of 123
RX660 Group
2. Electrical Characteristics
tTD
SSLA0 to
SSLA3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
tSU
MISOA
input
tHF
MSB IN
tOH
DATA
LSB IN
tOD
MOSIA
output
Figure 2.55
tH
MSB IN
tDr, tDf
MSB OUT
DATA
LSB OUT
IDLE
MSB OUT
RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKA Division Ratio Set to 1/2)
tTD
SSLA0
input
tLEAD
tLAG
RSPCKA
CPOL = 0
input
RSPCKA
CPOL = 1
input
tSA
tOH
MISOA
output
MSB OUT
tSU
MOSIA
input
Figure 2.56
tOD
DATA
tREL
LSB OUT
tH
MSB IN
MSB OUT
tDr, tDf
DATA
LSB IN
MSB IN
RSPI Timing (Slave, CPHA = 0)
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Mar 18, 2022
Page 99 of 123
RX660 Group
2. Electrical Characteristics
tTD
SSLA0
input
tLEAD
tLAG
RSPCKA
CPOL = 0
input
RSPCKA
CPOL = 1
input
tSA
tOH
tOD
MISOA
output
MSB OUT
tSU
MOSIA
input
Figure 2.57
tREL
DATA
tH
MSB IN
LSB OUT
MSB OUT
tDr, tDf
DATA
LSB IN
MSB IN
RSPI Timing (Slave, CPHA = 1)
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 100 of 123
RX660 Group
2. Electrical Characteristics
2.4.6.11
Table 2.41
RIIC
RIIC Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr
Symbol
Min.*1
Max.
Unit
Test
Conditions*3
SCL input cycle time
tSCL
6(12) × tIICcyc + 1300
—
ns
Figure 2.58
SCL input high pulse width
tSCLH
3(6) × tIICcyc + 300
—
ns
SCL input low pulse width
tSCLL
3(6) × tIICcyc + 300
—
ns
SCL, SDA input rise time
tSr
—
1000
ns
SCL, SDA input fall time
tSf
—
300
ns
Item
RIIC
(Standard-mode,
SMBus)
RIIC
(Fast-mode)
SCL, SDA input spike pulse removal time
tSP
0
1(4) × tIICcyc
ns
SDA input bus free time
tBUF
3(6) × tIICcyc + 300
—
ns
Start condition input hold time
tSTAH
tIICcyc + 300
—
ns
Restart condition input setup time
tSTAS
1000
—
ns
Stop condition input setup time
tSTOS
1000
—
ns
Data input setup time
tSDAS
tIICcyc + 50
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
C b* 2
—
400
pF
SCL input cycle time
tSCL
6(12) × tIICcyc + 600
—
ns
SCL input high pulse width
tSCLH
3(6) × tIICcyc + 300
—
ns
SCL input low pulse width
tSCLL
3(6) × tIICcyc + 300
—
ns
SCL, SDA input rise time
tSr
20 × (External pull-up
voltage/5.5V)
300
ns
SCL, SDA input fall time
tSf
20 × (External pull-up
voltage/5.5V)
300
ns
SCL, SDA input spike pulse removal time
tSP
0
1(4) × tIICcyc
ns
SDA input bus free time
tBUF
3(6) × tIICcyc + 300
—
ns
Start condition input hold time
tSTAH
tIICcyc + 300
—
ns
Restart condition input setup time
tSTAS
300
—
ns
Stop condition input setup time
tSTOS
300
—
ns
Data input setup time
tSDAS
tIICcyc + 50
—
ns
Data input hold time
tSDAH
0
—
ns
*2
—
400
pF
SCL, SDA capacitive load
Cb
Note:
tIICcyc: RIIC internal reference clock (IICφ) cycle
Note 1. The value within parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 11b while the digital filter is enabled by
the setting ICFER.NFE = 1.
Note 2. Cb is the total capacitance of the bus lines.
Note 3. When VCC ≥ 4.5V, VOLSR.RICVLS = 0
When VCC < 4.5V, VOLSR.RICVLS = 1
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Mar 18, 2022
Page 101 of 123
RX660 Group
2. Electrical Characteristics
VIH
SDA0, SDA2
VIL
tBUF
tSCLH
tSTAS
tSTAH
tSTOS
tSP
SCL0, SCL2
P*1
S*1
tSCLL
tSr
tSf
tSCL
tSDAS
tSDAH
Note 1. S, P, and Sr indicate the following conditions.
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.58
RIIC Bus Interface Input/Output Timing
2.4.6.12
CANFD
Table 2.42
P*1
Sr*1
Test conditions
VIH = 0.7 × VCC, VIL = 0.3 × VCC
VOL = 0.6 V, IOL = 6 mA
CANFD Timing
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Item
Classic CAN mode
CAN FD mode
Bit rate for communications
Symbol
Min.
Max.
Unit
—
1
Mbps
Bit rate for communications
—
1
Bit rate for communications (only for data)
—
5
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 102 of 123
RX660 Group
2.5
2. Electrical Characteristics
A/D Conversion Characteristics
Table 2.43
12-Bit A/D Conversion Characteristics (1)
Conditions: VCC = 2.7 to 5.5 V, 3.0 V ≤ AVCC0 ≤ 5.5 V, AVCC0 – 1.0 ≤ VREFH0 ≤ AVCC0, 3.0 V ≤ VREFH0,
VSS = AVSS0 = VREFL0 = 0 V, Ta = Topr, Source impedance = 1.0 kΩ,
The VREFH0 and VREFL0 pins are selected as the reference voltage (ADVREFCR.VREFSEL bit = 1).
Item
Min.
Typ.
Max.
Unit
Resolution
12
12
12
Bit
Analog input capacitance
—
—
30
pF
0.90 (0.50)*2
µs
Test Conditions
AN000 to AN007
Conversion time*1
(Operation at PCLKD = 60
AN008 to AN015
MHz)
AN017, AN019, AN021, AN023
—
—
(0.55)*2
—
—
Sampling in 33 states
0.95 (0.55)*2
—
—
Sampling in 33 states
AN016, AN018, AN020, AN022
1.05 (0.65)*2
—
—
Sampling in 39 states
0.95
Offset error
—
±1.5
±5.0
Full-scale error
—
±1.5
±4.5
Quantization error
—
±0.5
—
Absolute accuracy
—
±2.5
±5.5
DNL differential nonlinearity error
—
±1.0
±1.5
INL integral nonlinearity error
—
±1.5
±2.5
Sampling in 30 states
LSB
Note:
The characteristics apply when no pin functions other than A/D converter input are used. The absolute accuracy includes the
quantization error. The offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error does
not include the quantization error.
Note 1. The conversion time includes the sampling time and the comparison time. The numbers of sampling states is indicated as test
conditions for the respective items.
Note 2. The value in parentheses indicates the sampling time.
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 103 of 123
RX660 Group
Table 2.44
2. Electrical Characteristics
12-Bit A/D Conversion Characteristics (2) (144-Pin Products)
Conditions: VCC = 2.7 to 5.5 V, 3.0 V ≤ AVCC0 ≤ 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr, Source impedance = 1.0 kΩ,
The AVCC0 and AVSS0 pins are selected as the reference voltage (ADVREFCR.VREFSEL bit = 0).
Item
Min.
Typ.
Max.
Unit
Resolution
12
12
12
Bit
Analog input capacitance
—
—
30
pF
0.90 (0.50)*2
µs
Test Conditions
AN000 to AN007
Conversion time*1
(Operation at PCLKD = 60
AN008 to AN015
MHz)
AN017, AN019, AN021, AN023
—
—
(0.55)*2
—
—
Sampling in 33 states
0.95 (0.55)*2
—
—
Sampling in 33 states
AN016, AN018, AN020, AN022
1.05
(0.65)*2
—
—
Sampling in 39 states
1.30
(0.50)*2
time*1
0.95
AN000 to AN007
Conversion
(Operation at PCLKD = 30
AN008 to AN015
MHz)
AN017, AN019, AN021, AN023
—
—
1.39 (0.60)*2
—
—
Sampling in 18 states
1.39 (0.60)*2
—
—
Sampling in 18 states
AN016, AN018, AN020, AN022
(0.70)*2
—
—
Operation at PCLKD = 60 MHz
—
±4.0
—
Operation at PCLKD = 30 MHz
—
±1.5
—
Operation at PCLKD = 60 MHz
—
±2.5
—
Operation at PCLKD = 30 MHz
—
±1.5
—
—
±0.5
—
Operation at PCLKD = 60 MHz
—
±7.0
—
Operation at PCLKD = 30 MHz
—
±4.0
—
DNL differential
nonlinearity error
Operation at PCLKD = 60 MHz
—
±4.0
—
Operation at PCLKD = 30 MHz
—
±1.0
—
INL integral nonlinearity
error
Operation at PCLKD = 60 MHz
—
±4.0
—
Operation at PCLKD = 30 MHz
—
±1.5
—
Offset error
Full-scale error
Quantization error
Absolute accuracy
1.49
µs
Sampling in 30 states
Sampling in 15 states
Sampling in 21 states
LSB
Note:
The characteristics apply when no pin functions other than A/D converter input are used. The absolute accuracy includes the
quantization error. The offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error does
not include the quantization error.
Note 1. The conversion time includes the sampling time and the comparison time. The numbers of sampling states is indicated as test
conditions for the respective items.
Note 2. The value in parentheses indicates the sampling time.
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 104 of 123
RX660 Group
Table 2.45
2. Electrical Characteristics
12-Bit A/D Conversion Characteristics (2) (100-, 80-, and 64-Pin Products)
Conditions: VCC = 2.7 to 5.5 V, 3.0 V ≤ AVCC0 ≤ 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr, Source impedance = 1.0 kΩ,
The AVCC0 and AVSS0 pins are selected as the reference voltage (ADVREFCR.VREFSEL bit = 0).
Item
Min.
Typ.
Max.
Unit
Resolution
12
12
12
Bit
Analog input capacitance
—
—
30
pF
0.90 (0.50)*2
µs
Test Conditions
AN000 to AN007
Conversion time*1
(Operation at PCLKD = 60
AN008 to AN015
MHz)
AN017, AN019, AN021, AN023
—
—
(0.55)*2
—
—
Sampling in 33 states
0.95 (0.55)*2
—
—
Sampling in 33 states
AN016, AN018, AN020, AN022
1.05
(0.65)*2
—
—
Sampling in 39 states
1.30
(0.50)*2
time*1
0.95
AN000 to AN007
Conversion
(Operation at PCLKD = 30
AN008 to AN015
MHz)
AN017, AN019, AN021, AN023
—
—
1.39 (0.60)*2
—
—
Sampling in 18 states
1.39 (0.60)*2
—
—
Sampling in 18 states
AN016, AN018, AN020, AN022
(0.70)*2
—
—
Operation at PCLKD = 60 MHz
—
±2.5
—
Operation at PCLKD = 30 MHz
—
±1.5
—
Operation at PCLKD = 60 MHz
—
±2.5
—
Operation at PCLKD = 30 MHz
—
±1.5
—
—
±0.5
—
Operation at PCLKD = 60 MHz
—
±4.5
—
Operation at PCLKD = 30 MHz
—
±2.5
—
DNL differential
nonlinearity error
Operation at PCLKD = 60 MHz
—
±1.5
—
Operation at PCLKD = 30 MHz
—
±1.0
—
INL integral nonlinearity
error
Operation at PCLKD = 60 MHz
—
±2.5
—
Operation at PCLKD = 30 MHz
—
±1.5
—
Offset error
Full-scale error
Quantization error
Absolute accuracy
1.49
µs
Sampling in 30 states
Sampling in 15 states
Sampling in 21 states
LSB
Note:
The characteristics apply when no pin functions other than A/D converter input are used. The absolute accuracy includes the
quantization error. The offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error does
not include the quantization error.
Note 1. The conversion time includes the sampling time and the comparison time. The numbers of sampling states is indicated as test
conditions for the respective items.
Note 2. The value in parentheses indicates the sampling time.
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 105 of 123
RX660 Group
Table 2.46
2. Electrical Characteristics
12-Bit A/D Conversion Characteristics (2) (48-Pin Products)
Conditions: VCC = 2.7 to 5.5 V, 3.0 V ≤ AVCC0 ≤ 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr, Source impedance = 1.0 kΩ,
The AVCC0 and AVSS0 pins are selected as the reference voltage (ADVREFCR.VREFSEL bit = 0).
Item
Min.
Typ.
Resolution
12
12
12
Bit
Analog input capacitance
—
—
30
pF
0.90 (0.50)*2
—
—
µs
0.95 (0.55)*2
—
—
—
±1.5
—
AN000 to AN002, AN005 to
Conversion time*1
(Operation at PCLKD = 60 AN007
MHz)
AN009 to AN012
Offset error
Max.
Full-scale error
—
±1.5
—
Quantization error
—
±0.5
—
Absolute accuracy
—
±2.5
—
DNL differential nonlinearity error
—
±1.0
—
INL integral nonlinearity error
—
±1.5
—
Unit
Test Conditions
Sampling in 30 states
Sampling in 33 states
LSB
Note:
The characteristics apply when no pin functions other than A/D converter input are used. The absolute accuracy includes the
quantization error. The offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error does
not include the quantization error.
Note 1. The conversion time includes the sampling time and the comparison time. The numbers of sampling states is indicated as test
conditions for the respective items.
Note 2. The value in parentheses indicates the sampling time.
Table 2.47
A/D Internal Reference Voltage Characteristics
Conditions: VCC = 2.7 to 5.5 V, 3.0 V ≤ AVCC0 ≤ 5.5 V, AVCC0 – 1.0 ≤ VREFH0 ≤ AVCC0, 3.0 V ≤ VREFH0,
VSS = AVSS0 = VREFL0 = 0 V, Ta = Topr
Item
Min.
Typ.
Max.
Unit
A/D internal reference voltage
1.20
1.25
1.30
V
Note:
Test Conditions
The above specification values apply during normal operations.
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 106 of 123
RX660 Group
2.6
2. Electrical Characteristics
D/A Conversion Characteristics
Table 2.48
D/A Conversion Characteristics
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Item
Min.
Typ.
Max.
Unit
Resolution
12
12
12
Bit
Absolute accuracy
—
—
±6.0
LSB
2-MΩ resistive load
10-bit conversion
Differential nonlinearity error (DNL)
—
±1.0
±2.0
LSB
2-MΩ resistive load
Output resistance (RO)
—
5.7
—
kΩ
Conversion time
—
—
3
µs
2.7
Test Conditions
20-pF capacitive load
Temperature Sensor Characteristics
Table 2.49
Temperature Sensor Characteristics
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Min.
Typ.
Max.
Unit
Relative accuracy
Item
—
±1
—
°C
Temperature slope
—
–2.0
—
mV/°C
Output voltage
—
0.63
—
V
Temperature sensor start time
—
—
200
µs
3
—
—
µs
Sampling
time*1
Test Conditions
Ta = 25°C
Note 1. Set the S12AD.ADSSTRT register such that the sampling time of the 12-bit A/D converter satisfies this specification.
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 107 of 123
RX660 Group
2.8
2. Electrical Characteristics
Comparator Characteristics
Table 2.50
Comparator Characteristics
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Item
Input offset voltage
Symbol
Min.
Typ.
Max.
Unit
VIO
—
8
40
mV
Reference input voltage range
Vref
0
—
VCC
V
Analog input voltage rang
Vain
0
—
VCC
V
Response time
ttot(r)
—
—
200
ns
ttot(f)
—
—
200
Waiting time for stabilization following
switching of the input
tcwait
300
—
—
ns
Operation stabilization time
tcmp
—
—
1
μs
Reference input
voltage
Test Conditions
VOD = 100 mV
CMPCTL.CDFS[1:0] = 00b
Figure 2.59
100 mV
100 mV
CMPCn0
(analog input voltage)
ttot(r)
COMPn
(output for monitoring the
results of comparison)
ttot(f)
(n = 0 to 3)
Figure 2.59
Comparator Response Time
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 108 of 123
RX660 Group
2.9
2. Electrical Characteristics
Power-on Reset Circuit and Voltage Detection Circuit Characteristics
Table 2.51
Power-on Reset Circuit and Voltage Detection Circuit Characteristics
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Item
Voltage detection
level
Symbol
Min.
Voltage detection circuit (LVD1)
Voltage detection circuit (LVD2)
Internal reset time
Max.
Unit
V
VPOR
2.46
2.58
2.70
Vdet0_1
4.04
4.22
4.40
Vdet0_2
2.71
2.83
2.95
Vdet1_0
4.39
4.57
4.75
Vdet1_1
4.29
4.47
4.65
Vdet1_2
4.14
4.32
4.50
Vdet1_3
2.81
2.93
3.05
Vdet1_4
2.76
2.88
3.00
Vdet2_0
4.39
4.57
4.75
Vdet2_1
4.29
4.47
4.65
Vdet2_2
4.14
4.32
4.50
Vdet2_3
2.81
2.93
3.05
Vdet2_4
2.76
2.88
3.00
tPOR
—
15.5
—
Power-on reset (POR)
Voltage detection circuit (LVD0)
Typ.
Power-on reset time
Test
Conditions
Figure 2.60
Figure 2.61
Figure 2.62
Figure 2.63
ms
Figure 2.60
LVD0 reset time
tLVD0
—
0.70
—
Figure 2.61
LVD1 reset time
tLVD1
—
0.57
—
Figure 2.62
LVD2 reset time
tLVD2
—
0.57
—
Figure 2.63
tVOFF
200
—
—
µs
Figure 2.60,
Figure 2.61
tdet
—
—
200
µs
Figure 2.60 to
Figure 2.63
LVD operation stabilization time (after LVD is enabled)
td(E-A)
—
—
20
µs
Hysteresis width (LVD1 and LVD2)
V LVH
—
80
—
mV
Figure 2.62,
Figure 2.63
Minimum VCC down time
Response delay time
Note:
The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet1,
and Vdet2 for the POR/ LVD.
tVOFF
VPOR
VCC
Internal reset signal
(Low is valid)
tdet
Figure 2.60
tPOR
tdet
tdet
tPOR
Power-on Reset Timing
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 109 of 123
RX660 Group
2. Electrical Characteristics
tVOFF
VCC
Vdet0
Internal reset signal
(Low is valid)
tdet
Figure 2.61
tdet
tLVD0
Voltage Detection Circuit Timing (Vdet0)
tVOFF
VCC
VLVH
Vdet1
LVD1E
Td(E-A)
LVD1
Comparator output
LVD1CMPE
LVD1MON
Internal reset signal
(Low is valid)
When LVD1RN = L
tdet
tdet
tLVD1
When LVD1RN = H
tLVD1
Figure 2.62
Voltage Detection Circuit Timing (Vdet1)
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 110 of 123
RX660 Group
2. Electrical Characteristics
tVOFF
VCC
VLVH
Vdet2
LVD2E
Td(E-A)
LVD2
Comparator output
LVD2CMPE
LVD2MON
Internal reset signal
(Low is valid)
When LVD2RN = L
tdet
tdet
tLVD2
When LVD2RN = H
tLVD2
Figure 2.63
Voltage Detection Circuit Timing (Vdet2)
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 111 of 123
RX660 Group
2.10
2. Electrical Characteristics
Oscillation Stop Detection Timing
Table 2.52
Oscillation Stop Detection Circuit Characteristics
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V, Ta = Topr
Item
Detection time
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
tdr
—
—
1
ms
Figure 2.64
Main clock or
PLL clock
tdr
OSTDSR.OSTDF
LOCO clock
ICLK
Figure 2.64
Oscillation Stop Detection Timing
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 112 of 123
RX660 Group
2.11
2. Electrical Characteristics
Flash Memory Characteristics
Table 2.53
Code Flash Memory Characteristics
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V,
Temperature range for programming/erasure: Ta = Topr
Item
Programming time
NPEC ≤ 100 times
Programming time
NPEC > 100 times
Symbol
20 MHz ≤ FCLK ≤ 60 MHz
FCLK = 4 MHz
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
256 bytes
tP256
—
0.9
13.2
—
0.4
6
ms
8 Kbytes
tP8K
—
29
176
—
13
80
ms
32 Kbytes
tP32K
—
116
704
—
52
320
ms
256 bytes
tP256
—
1.1
15.8
—
0.5
7.2
ms
8 Kbytes
tP8K
—
35
212
—
16
96
ms
32 Kbytes
tP32K
—
140
848
—
64
384
ms
Erasure time
NPEC ≤ 100 times
8 Kbytes
tE8K
—
71
216
—
39
120
ms
32 Kbytes
tE32K
—
254
864
—
141
480
ms
Erasure time
NPEC > 100 times
8 Kbytes
tE8K
—
85
260
—
47
144
ms
32 Kbytes
tE32K
—
304
1040
—
169
576
ms
Reprogramming/erasure cycle*1
NPEC
1000*2
—
—
1000*2
—
—
Times
Suspend delay time during
programming
tSPD
—
—
264
—
—
120
µs
First suspend delay time during
erasing
(in suspend priority mode)
tSESD1
—
—
216
—
—
120
µs
Second suspend delay time during
erasure
(in suspend priority mode)
tSESD2
—
—
1.7
—
—
1.7
ms
Suspend delay time during erasure
(in erasure priority mode)
tSEED
—
—
1.7
—
—
1.7
ms
tFD
—
—
32
—
—
20
µs
tDRP
20
—
—
20
—
—
Year
10
—
—
10
—
—
Forced stop command
Data hold
time*3, *4
Test
Conditions
Ta ≤ 85°C
Ta ≤ 105°C
Note 1. Definition of program/erase cycle:
The program/erase cycle is the number of erasing for each block. When the number of program/erase cycles is n, each block
can be erased n times. For instance, when 256-byte program is performed 32 times for different addresses in 8-Kbyte block and
then the block is erased, the program/erase cycle is counted as one. However, the same address cannot be programmed more
than once before the next erase cycle (overwriting is prohibited).
Note 2. Characteristics are degraded as the number of program/erase increases. This is the minimum value of program/erase cycles to
guarantee all characteristics listed in this table.
Note 3. This shows the characteristic when the flash memory writer or self-programming library from Renesas Electronics is in use, and
the number of times programming and erasure proceed does not exceed the specified value.
Note 4. These values are based on the results of reliability testing.
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 113 of 123
RX660 Group
Table 2.54
2. Electrical Characteristics
Data Flash Memory Characteristics
Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 3.0 to 5.5 V,
VSS = AVSS0 = 0 V,
Temperature range for programming/erasure: Ta = Topr
Item
Symbol
20 MHz ≤ FCLK ≤ 60 MHz
FCLK = 4 MHz
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Programming time
4 bytes
tDP4
—
0.36
3.8
—
0.16
1.7
ms
Erasure time
64 bytes
tDP64
—
3.1
18
—
1.7
10
ms
Blank check time
4 bytes
tDBC4
—
—
84
—
—
30
µs
64 bytes
tDBC64
—
—
280
—
—
100
µs
2 Kbytes
tDBC2K
—
—
6160
—
—
2200
µs
cycle*1
NDPEC
100000
*2
—
—
100000
*2
—
—
Times
tDSPD
—
—
264
—
—
120
µs
First suspend delay time during
erasure (in suspend priority mode)
tDSESD1
—
—
216
—
—
120
µs
Second suspend delay time during
erasure (in suspend priority mode)
tDSESD2
—
—
300
—
—
300
µs
Suspend delay time during erasure
(in erasure priority mode)
tDSEED
—
—
300
—
—
300
µs
tFD
—
—
32
—
—
20
µs
tDDRP
20
—
—
20
—
—
Year
10
—
—
10
—
—
Reprogramming/erasure
Suspend delay time during
programming
Forced stop command
Data hold time*3, *4
Test
Conditions
Ta ≤ 85°C
Ta ≤ 105°C
Note 1. Definition of program/erase cycle:
The program/erase cycle is the number of erasing for each block. When the number of program/erase cycles is n, each block
can be erased n times. For instance, when 4-byte program is performed 512 times for different addresses in 2-Kbyte block and
then the block is erased, the program/erase cycle is counted as one. However, the same address cannot be programmed more
than once before the next erase cycle (overwriting is prohibited).
Note 2. Characteristics are degraded as the number of program/erase increases. This is the minimum value of program/erase cycles to
guarantee all characteristics listed in this table.
Note 3. This shows the characteristic when the flash memory writer or self-programming library from Renesas Electronics is in use, and
the number of times programming and erasure proceed does not exceed the specified value.
Note 4. These values are based on the results of reliability testing.
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 114 of 123
RX660 Group
2. Electrical Characteristics
• Suspension during programming
FCU command
Program
Suspend
tSPD
FSTATR.FRDY
Ready
Programming pulse
Not Ready
Ready
Programming
• Suspension during erasure in suspend priority mode
FCU command
Erase
Suspend
Resume
Suspend
tSESD1
FSTATR.FRDY
Ready
Erasure pulse
Not Ready
tSESD2
Ready
Erasing
Not Ready
Erasing
• Suspension during erasure in erasure priority mode
FCU command
Erase
Suspend
tSEED
FSTATR.FRDY
Ready
Erasure pulse
Figure 2.65
Not Ready
Ready
Erasing
Flash Memory Programming/Erasure Suspension Timing
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 115 of 123
RX660 Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
Information on the latest version of the package dimensions or mountings has been displayed in “Packages” on Renesas
Electronics Corporation website.
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-LFQFP144-20x20-0.50
PLQP0144KA-B
—
1.2
Unit: mm
HD
*1 D
108
73
109
E
*2
144
HE
72
37
1
36
NOTE 4
Index area
NOTE 3
F
S
0.25
A1
T
c
y S
A2
A
e
*3
bp
Lp
L1
Detail F
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Reference Dimensions in millimeters
Symbol
M
Min
Nom
Max
D
19.9
20.0
20.1
20.1
E
19.9
20.0
A2
1.4
HD
21.8
22.0
22.2
HE
21.8
22.0
22.2
A
1.7
A1
0.05
0.15
bp
0.17
0.20
0.27
c
0.09
0.20
T
0q
3.5q
8q
e
0.5
x
0.08
y
0.10
Lp
0.45
0.6
0.75
L1
1.0
Figure A 144-Pin LFQFP (PLQP0144KA-B)
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 116 of 123
RX660 Group
Appendix 1. Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-LFQFP100-14x14-0.50
PLQP0100KB-B
—
0.6
HD
Unit: mm
*1 D
75
51
*2
E
50
100
HE
76
26
1
25
NOTE 4
Index area
NOTE 3
F
S
y S
*3
0.25
Reference Dimensions in millimeters
Symbol
bp
M
Min
Nom
Max
D
13.9
14.0
14.1
14.1
E
13.9
14.0
A2
1.4
HD
15.8
16.0
16.2
HE
15.8
16.0
16.2
A
1.7
A1
0.05
0.15
bp
0.15
0.20
0.27
c
0.09
0.20
T
0q
3.5q
8q
e
0.5
x
0.08
y
0.08
Lp
0.45
0.6
0.75
L1
1.0
A1
T
c
A2
A
e
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Lp
L1
Detail F
Figure B 100-Pin LFQFP (PLQP0100KB-B)
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 117 of 123
RX660 Group
Appendix 1. Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-LFQFP80-12x12-0.50
PLQP0080KB-B
—
0.5
HD
Unit: mm
*1 D
41
40
80
21
*2
E
61
1
20
HE
60
NOTE 4
Index area
NOTE 3
F
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Reference Dimensions in millimeters
Symbol
S
y
S
*3
0.25
A1
T
c
A2
A
e
Lp
L1
bp
M
Min
Nom
Max
D
11.9
12.0
12.1
12.1
E
11.9
12.0
A2
1.4
HD
13.8
14.0
14.2
HE
13.8
14.0
14.2
A
1.7
A1
0.05
0.15
bp
0.15
0.20
0.27
c
0.09
0.20
T
0q
3.5q
8q
e
0.5
x
0.08
y
0.08
Lp
0.45
0.6
0.75
L1
1.0
Detail F
Figure C 80-Pin LFQFP (PLQP0080KB-B)
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 118 of 123
RX660 Group
Appendix 1. Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-LFQFP64-10x10-0.50
PLQP0064KB-C
—
0.3
Unit: mm
HD
*1 D
48
33
64
HE
32
*2 E
49
17
1
16
NOTE 4
Index area
NOTE 3
F
S
y S
*3
bp
0.25
c
A1
T
A2
A
e
Lp
L1
Detail F
M
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Reference Dimensions in millimeters
Symbol
Min
Nom
Max
D
9.9
10.0
10.1
10.1
E
9.9
10.0
A2
1.4
HD
11.8
12.0
12.2
HE
11.8
12.0
12.2
A
1.7
A1
0.05
0.15
bp
0.15
0.20
0.27
c
0.09
0.20
T
0q
3.5q
8q
e
0.5
x
0.08
y
0.08
Lp
0.45
0.6
0.75
L1
1.0
Figure D 64-Pin LFQFP (PLQP0064KB-C)
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 119 of 123
RX660 Group
Appendix 1. Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-LFQFP48-7x7-0.50
PLQP0048KB-B
—
0.2
HD
Unit: mm
*1 D
36
25
*2
48
HE
24
E
37
13
1
12
NOTE 4
Index area
NOTE 3
F
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
S
Reference Dimensions in millimeters
Symbol
y S
*3
bp
0.25
M
A1
T
c
A2
A
e
Lp
L1
Detail F
Min
Nom
Max
D
6.9
7.0
7.1
E
6.9
7.0
7.1
A2
1.4
HD
8.8
9.0
9.2
HE
8.8
9.0
9.2
A
1.7
A1
0.05
0.15
bp
0.17
0.20
0.27
c
0.09
0.20
T
0q
3.5q
8q
e
0.5
x
0.08
y
0.08
Lp
0.45
0.6
0.75
L1
1.0
Figure E 48-Pin LFQFP (PLQP0048KB-B)
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Page 120 of 123
REVISION HISTORY
RX660 Group
REVISION HISTORY
REVISION HISTORY
RX660 Group Datasheet
Classifications
- Items with Technical Update document number: Changes according to the corresponding issued Technical Update
- Items without Technical Update document number: Minor changes that do not require Technical Update to be issued
Rev.
Date
1.00
Mar 18, 2022
Page
—
R01DS0393EJ0100 Rev.1.00
Mar 18, 2022
Description
Summary
Classification
First edition, issued
Page 121 of 123
General Precautions in the Handling of Microprocessing Unit and Microcontroller
Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage
notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have
been issued for the products.
1.
Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps
must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be
adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.
Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be
touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.
2.
Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of
register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset
pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins
in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the
level at which resetting is specified.
3.
Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements.
Follow the guideline for input signal during power-off state as described in your product documentation.
4.
Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are
generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of
the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
become possible.
5.
Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program
execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator
during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced
with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
6.
Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.)
and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level
is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.).
7.
Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these
addresses as the correct operation of the LSI is not guaranteed.
8.
Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.
The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms
of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,
operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a systemevaluation test for the given product.
Notice
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products
and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your
product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of
these circuits, software, or information.
Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or
other intellectual property rights of third parties, by or arising from the use of Renesas Electronics products or technical information described in this
document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application examples.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
You shall be responsible for determining what licenses are required from any third parties, and obtaining such licenses for the lawful import, export,
manufacture, sales, utilization, distribution or other disposal of any products incorporating Renesas Electronics products, if required.
You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any
and all liability for any losses or damages incurred by you or third parties arising from such alteration, modification, copying or reverse engineering.
Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for
each Renesas Electronics product depends on the product’s quality grade, as indicated below.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home
electronic appliances; machine tools; personal electronic equipment; industrial robots; etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key
financial terminal systems; safety control equipment; etc.
Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas
Electronics document, Renesas Electronics products are not intended or authorized for use in products or systems that may pose a direct threat to
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any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is
inconsistent with any Renesas Electronics data sheet, user’s manual or other Renesas Electronics document.
No semiconductor product is absolutely secure. Notwithstanding any security measures or features that may be implemented in Renesas Electronics
hardware or software products, Renesas Electronics shall have absolutely no liability arising out of any vulnerability or security breach, including but not
limited to any unauthorized access to or use of a Renesas Electronics product or a system that uses a Renesas Electronics product. RENESAS
ELECTRONICS DOES NOT WARRANT OR GUARANTEE THAT RENESAS ELECTRONICS PRODUCTS, OR ANY SYSTEMS CREATED USING
RENESAS ELECTRONICS PRODUCTS WILL BE INVULNERABLE OR FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE,
HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (“Vulnerability Issues”). RENESAS ELECTRONICS DISCLAIMS ANY AND
ALL RESPONSIBILITY OR LIABILITY ARISING FROM OR RELATED TO ANY VULNERABILITY ISSUES. FURTHERMORE, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, RENESAS ELECTRONICS DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, WITH
RESPECT TO THIS DOCUMENT AND ANY RELATED OR ACCOMPANYING SOFTWARE OR HARDWARE, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for
Handling and Using Semiconductor Devices” in the reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by
Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation characteristics, installation, etc. Renesas
Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such
specified ranges.
Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific
characteristics, such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Unless designated as a high reliability
product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products
are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury,
injury or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety
design for hardware and software, including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging
degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult and impractical, you are
responsible for evaluating the safety of the final products or systems manufactured by you.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas
Electronics product. You are responsible for carefully and sufficiently investigating applicable laws and regulations that regulate the inclusion or use of
controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics products in compliance with all these
applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance
with applicable laws and regulations.
Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is
prohibited under any applicable domestic or foreign laws or regulations. You shall comply with any applicable export control laws and regulations
promulgated and administered by the governments of any countries asserting jurisdiction over the parties or transactions.
It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or
transfers the product to a third party, to notify such third party in advance of the contents and conditions set forth in this document.
This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas
Electronics products.
(Note1)
(Note2)
“Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled
subsidiaries.
“Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
(Rev.5.0-1 October 2020)
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