Features
Datasheet
RX671 Group
R01DS0373EJ0110
Rev.1.10
Apr 15, 2022
Renesas MCUs
120-MHz 32-bit RX MCU, on-chip double-precision FPU, 707 CoreMark,
up to 2-MB flash memory (supporting the dual bank function), 384-KB SRAM,
various communications interfaces, including SD host interface, Quad SPI, and CAN, Capacitive touch sensing unit,
12-bit A/D converter, RTC, Encryption function, Serial sound interface, Remote control signal receiver
Features
PLQP0144KA-B 20 × 20 mm, 0.50-mm pitch
PLQP0100KB-B 14 × 14 mm, 0.50-mm pitch
PLQP0064KB-C 10 × 10 mm, 0.50-mm pitch
■ 32-bit RXv3 CPU core
• Maximum operating frequency: 120 MHz
Capable of 707 CoreMark in operation at 120 MHz
• Double-precision 64-bit IEEE-754 floating point
• A collective register bank save function is available.
• Supports the memory protection unit (MPU)
• JTAG and FINE (one-line) debugging interfaces
PTLG0145JC-A 9 × 9 mm, 0.65-mm pitch
PTLG0145KB-A 7 × 7 mm, 0.50-mm pitch
PTLG0100JB-A 7 × 7 mm, 0.65-mm pitch
■ Low-power design and architecture
PTBG0064KB-A 4.5 × 4.5 mm, 0.50-mm pitch
• Operation from a single 2.7- to 3.6-V supply
• Battery supply of backup power allows continued operations of the
RTC and the backup registers.
• Four low-power modes
PWQN0048KC-A 7 × 7 mm, 0.50-mm pitch
■ On-chip code flash memory
• Supports versions with up to 2 Mbytes of ROM
• No wait cycles at up to 60 MHz or when the ROM cache is hit, onewait state at up to 120 MHz
• User code is programmable by on-board or off-board programming.
• Programming/erasing as background operations (BGOs)
• A dual-bank structure allows exchanging the start-up bank.
■ On-chip data flash memory
• 8 Kbytes, reprogrammable up to 100,000 times
• Programming/erasing as background operations (BGOs)
■ On-chip SRAM
• 384 Kbytes of SRAM (no wait states)
• 4 Kbytes of standby RAM (backup on deep software standby)
■ External address space
• Buses for full-speed data transfer (maximum operating frequency of
60 MHz)
• 8 CS areas
• 8- or 16-bit bus space is selectable per area
• Independent SDRAM area (128 Mbytes)
■ Data transfer
• DMACAb: 8 channels
• DTCb: 1 channel
• EXDMACa: 2 channels
■ Reset and supply management
• Power-on reset (POR)
• Low voltage detection (LVD) with voltage settings
• Backup domain low power detection
■ Clock functions
• External crystal resonator or internal PLL for operation at 8 to 24
MHz
• A sub-clock oscillator connectable to a 32.768-kHz crystal resonator
• Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20
MHz
• 120-kHz clock for the IWDTa
■ Real-time clock
• Adjustment functions (30 seconds, leap year, and error)
• Real-time clock counting and binary counting modes are selectable
• Time capture in response to an event-signal input
■ Independent watchdog timer
• Operates with the 120-kHz clock frequency generated by the
dedicated low-speed oscillator
■ Useful functions for IEC60730 compliance
• Oscillation-stoppage detection, frequency measurement, CRCA,
IWDTa, self-diagnostic function for the A/D converter, etc.
• Register write protection function that protects important registers
against overwriting
■ Remote control signal receiver
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
■ Various communications interfaces
• PHY layer (up to 2 channels) for host/function or OTG controller
(1 channel) with full-speed USB 2.0 transfer
• CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up
to 2 channels)
• SCIk and SCIh with multiple functionalities (up to 13 channels)
Choose from among asynchronous mode, clock-synchronous mode,
smart-card interface mode, simplified SPI, simplified I2C, and
extended serial mode.
• SCIm with 16-byte transmission and reception FIFOs (up to 2
channels)
• Up to two RSCIs with Manchester encoding and HBS functionality
• The I2C bus interfaces RIIC and RIICHS for transfer at up to 3.4
Mbps (up to 3 channels), and the RIICHS also supports high-speed
mode.
• Single I/O RSPId (3 channels), single I/O RSPIA (1 channel), and
quad QSPIX (1 channel). The QSPIX supports fetching from serial
flash memory.
• SD host interface (1 channel) with a 1- or 4-bit SD bus for use with
SD memory or SDIO
• Serial sound interface supporting various audio data formats,
including I2S
■ Up to 25 extended-function timers
• 16-bit TPUa, MTU3a
• 8-bit TMRb (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2
channels)
■ 12-bit A/D converter
• Two 12-bit units (8 channels for unit 0; 12 channels for unit 1)
• Self diagnosis, detection of analog input disconnection
■ Temperature sensor for measuring temperature
within the chip
■ Capacitive touch sensing unit
• Self-capacitance method: A single pin configures a single key,
supporting up to 17 keys
• Mutual capacitance method: Matrix configuration with 17 pins,
supporting up to 64 keys
■ Encryption function
• Trusted Secure IP (TSIP)
AES128/192/256, TDES, ARC4, RSA, ECC,
True-random number generator (TRNG), SHA1, SHA224, SHA256,
MD5, GHASH, Prevention of the illicit copying of keys
■ Up to 114 pins for general I/O ports
• 5-V tolerance, open drain, input pull-up, switchable driving ability
■ Operating temp. range
• D-version: –40°C to +85°C
• G-version: –40°C to +105°C
Page 1 of 178
RX671 Group
1. Overview
1.
Overview
1.1
Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 give a comparison of the functions of products in different
packages.
Table 1.1 is an outline of maximum specifications, and the peripheral modules and the number of channels of the
modules differ depending on the number of pins on the package. For details, see Table 1.2, Comparison of Functions
for Different Packages.
Table 1.1
Outline of Specifications (1/10)
Classification
Module/Function
Description
CPU
CPU
• Maximum operating frequency: 120 MHz
• 32-bit RX CPU (RXv3)
• Minimum instruction execution time: One instruction per state (cycle of the system
clock)
• Address space: 4-Gbyte linear
• Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Ten 32-bit registers
Accumulator: Two 72-bit registers
• 113 instructions
Instructions installed as standard: 111
Basic instructions: 77
Single-precision floating-point operation instructions: 11
DSP instructions: 23
Instructions for register bank save function: 2
• Addressing modes: 11
• Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
• On-chip 32-bit multiplier: 32 × 32 → 64 bits
• On-chip divider: 32 / 32 → 32 bits
• Barrel shifter: 32 bits
FPU
• Single precision (32-bit) floating point
• Data types and floating-point exceptions in conformance with the IEEE754 standard
Double-precision
floating point
coprocessor
• Double-precision floating-point register set
Double-precision floating-point data registers: 16, each with 64-bit width
Double-precision floating-point control registers: Four, each with 32-bit width
• Double-precision floating-point processing instructions: 21
• Notifying the interrupt controller of double-precision floating-point exceptions
Register bank save
function
• Fast collective saving and restoration of the values of CPU registers
• 16 save register banks
Code flash memory
• Capacity: 1 Mbyte/1.5 Mbytes/2 Mbytes
• ROM cache: 8 Kbytes
• 60 MHz ≤ No-wait cycle access
120 MHz ≤ 1-wait cycle access
• Instructions hitting the ROM cache or operand = 120 MHz: No-wait access
• On-board programming: Four types
• Off-board programming (parallel programmer mode)
• Instructions are executable only for the program stored in the TM target area by using
the Trusted Memory (TM) function and protection against data reading is realized.
• A dual-bank structure allows programming during reading or exchanging the start-up
areas
Data flash memory
• Capacity: 8 Kbytes
• Programming/erasing: 100,000 times
Unique ID
• 16-byte unique ID for the device
RAM
• Capacity: 384 Kbytes
• 120 MHz, no-wait access
Standby RAM
• Capacity: 4 Kbytes
• Operation synchronized with PCLKB: Up to 60 MHz, two-cycle access
Memory
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Apr 15, 2022
Page 2 of 178
RX671 Group
Table 1.1
1. Overview
Outline of Specifications (2/10)
Classification
Module/Function
• Operating modes by the mode-setting pins at the time of release from the reset state
Single-chip mode
Boot mode (for the SCI interface)
Boot mode (for the USB interface)
Boot mode (for the FINE interface)
• Selection of operating mode by register setting
Single-chip mode
On-chip ROM disabled extended mode
On-chip ROM enabled extended mode
• Endian selectable
Operating modes
Clock
Description
Clock generation circuit
• Main clock oscillator, sub clock oscillator, low-speed/high-speed on-chip oscillator, PLL
frequency synthesizer, and IWDT-dedicated on-chip oscillator
• The peripheral module clocks can be set to frequencies above that of the system clock.
• Main-clock oscillation stoppage detection
• Separate frequency-division and multiplication settings for the system clock (ICLK),
peripheral module clocks (PCLKA, PCLKB, PCLKC, PCLKD), flash-IF clock (FCLK) and
external bus clock (BCLK)
The CPU and other bus masters run in synchronization with the system clock (ICLK): Up
to 120 MHz
QSPIX runs in synchronization with ICLK at Up to 120 MHz.
Peripheral modules of MTU, RSPI, SCIm, RSPIA, RSCI, and RIICHS run in
synchronization with PCLKA, which operates at up to 120 MHz.
Other peripheral modules run in synchronization with PCLKB: Up to 60 MHz
ADCLK in the S12AD (unit 0) runs in synchronization with PCLKC: Up to 60 MHz
ADCLK in the S12AD (unit 1) runs in synchronization with PCLKD: Up to 60 MHz
Flash IF run in synchronization with the flash-IF clock (FCLK): Up to 60 MHz
Devices connected to the external bus run in synchronization with the external bus clock
(BCLK): Up to 60 MHz
• Multiplication is possible with using the high-speed on-chip oscillator (HOCO) as a
reference clock of the PLL circuit
• External clock input frequency: 30 MHz (max)
• Clock output function
Reset
Nine types of reset
• RES# pin reset: Generated when the RES# pin is driven low.
• Power-on reset: Generated when the RES# pin is driven high and VCC = AVCC0 =
AVCC1 rises.
• Voltage-monitoring 0 reset: Generated when VCC = AVCC0 = AVCC1 falls.
• Voltage-monitoring 1 reset: Generated when VCC = AVCC0 = AVCC1 falls.
• Voltage-monitoring 2 reset: Generated when VCC = AVCC0 = AVCC1 falls.
• Deep software standby reset: Generated in response to an interrupt to trigger release
from deep software standby.
• Independent watchdog timer reset: Generated when the independent watchdog timer
underflows, or a refresh error occurs.
• Watchdog timer reset: Generated when the watchdog timer underflows, or a refresh
error occurs.
• Software reset: Generated by register setting.
Power-on reset
If the RES# pin is at the high level when power is supplied, an internal reset is generated.
After VCC = AVCC0 = AVCC1 has exceeded the voltage detection level and the specified
period has elapsed, the reset is cancelled.
Voltage detection circuit (LVDA)
Monitors the voltage being input to the VCC = AVCC0 = AVCC1 pins and generates an
internal reset or interrupt.
• Voltage detection circuit 0
Capable of generating an internal reset
The option-setting memory can be used to select enabling or disabling of the reset.
Voltage detection level: Selectable from three different levels (2.94 V, 2.87 V, 2.80 V)
• Voltage detection circuits 1 and 2
Voltage detection level: Selectable from three different levels (2.99 V, 2.92 V, 2.85 V)
Digital filtering (1/2, 1/4, 1/8, and 1/16 LOCO frequency)
Capable of generating an internal reset
• Two types of timing are selectable for release from reset
An internal interrupt can be requested.
• Detection of voltage rising above and falling below thresholds is selectable.
• Maskable or non-maskable interrupt is selectable
Voltage detection monitoring
Event linking
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Page 3 of 178
RX671 Group
Table 1.1
1. Overview
Outline of Specifications (3/10)
Classification
Module/Function
Description
Low power
consumption
Low power consumption
function
• Module stop function
• Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software
standby mode
Battery backup function
• When the voltage on the VCC pin drops, power can be supplied to the backup power
area from the VBATT pin.
• Backup power area:
Sub-clock oscillator
Realtime clock
Backup register
Tamper detection
• Detection of low voltage in the backup power area
Interrupt controller
(ICUE)
•
•
•
•
•
•
Interrupt
Peripheral function interrupts: 256 sources
External interrupts: 16 (pins IRQ0 to IRQ15)
Software interrupts: 2 sources
Non-maskable interrupts: 8 sources
Sixteen levels specifiable for the order of priority
Method of interrupt source selection:
The interrupt vectors consist of 256 vectors (128 sources are fixed. The remaining 133
vectors are selected from among the other 128 sources.)
External bus extension
• The external address space can be divided into eight areas (CS0 to CS7), each with
independent control of access settings.
Capacity of each area: 16 Mbytes (CS0 to CS7)
A chip-select signal (CS0# to CS7#) can be output for each area.
Each area is specifiable as an 8-, or 16-bit bus space.
The data arrangement in each area is selectable as little or big endian (only for data).
• SDRAM interface connectable
• Bus format: Separate bus, multiplex bus
• Wait control
• Write buffer facility
DMA
DMA controller
(DMACAb)
• 8 channels
• Three transfer modes: Normal transfer, repeat transfer, and block transfer
• Activation sources: Software trigger, external interrupts, and interrupt requests from
peripheral functions
• Transfer space: 4 Gbytes (0000 0000h to FFFF FFFFh excluding reserved areas)
EXDMA controller
(EXDMACa)
• 2 channels
Four transfer modes: Normal transfer, repeat transfer, block transfer, and cluster
transfer
• Single-address transfer enabled with the EDACKn signal
• Request sources: Software trigger, external DMA requests (EDREQn), and interrupt
requests from peripheral functions
Data transfer controller
(DTCb)
• Three transfer modes: Normal transfer, repeat transfer, and block transfer
• Request sources: External interrupts and interrupt requests from peripheral functions
• Sequence transfer
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Page 4 of 178
RX671 Group
Table 1.1
1. Overview
Outline of Specifications (4/10)
Classification
Module/Function
Description
I/O ports
Programmable I/O ports
• I/O ports for the 145-pin TFLGA (0.65-mm pitch)
I/O pins: 111
Input pin: 1
Pull-up resistors: 111
Open-drain outputs: 111
5-V tolerance: 20
• I/O ports for the 145-pin TFLGA (0.50-mm pitch) and 144-pin LFQFP
I/O pins: 113
Input pin: 1
Pull-up resistors: 113
Open-drain outputs: 113
5-V tolerance: 20
• I/O ports for the 100-pin TFLGA and 100-pin LFQFP
I/O pins: 80
Input pin: 1
Pull-up resistors: 80
Open-drain outputs: 80
5-V tolerance: 18
• I/O ports for the 64-pin TFBGA
I/O pins: 43
Input pin: 1
Pull-up resistors: 43
Open-drain outputs: 43
5-V tolerance: 8
• I/O ports for the 64-pin LFQFP
I/O pins: 44
Input pin: 1
Pull-up resistors: 44
Open-drain outputs: 44
5-V tolerance: 8
• I/O ports for the 48-pin HWQFN
I/O pins: 33
Input pin: 1
Pull-up resistors: 33
Open-drain outputs: 33
5-V tolerance: 6
Event link controller (ELC)
• Event signals such as interrupt request signals can be interlinked with the operation of
functions such as timer counting, eliminating the need for intervention by the CPU to
control the functions.
• 99 internal event signals can be freely combined for interlinked operation with
connected functions.
• Event signals from peripheral modules can be used to change the states of output pins
(of ports B and E).
• Changes in the states of pins (of ports B and E) being used as inputs can be interlinked
with the operation of peripheral modules.
Timers
•
•
•
•
•
•
16-bit timer pulse unit
(TPUa)
•
•
•
•
8-bit timers (TMRb)
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Apr 15, 2022
(16 bits × 6 channels) × 1 unit
Maximum of 16 pulse-input/output possible
Select from among seven or eight counter-input clock signals for each channel
Input capture/output compare function
Output of PWM waveforms in up to 15 phases in PWM mode
Support for buffered operation, phase-counting mode (two phase encoder input) and
cascade-connected operation (32 bits × 2 channels) depending on the channel.
PPG output trigger can be generated
Capable of generating conversion start triggers for the A/D converters
Digital filtering of signals from the input capture pins
Event linking by the ELC
• (8 bits × 2 channels) × 2 units
• Select from among seven internal clock signals (PCLKB/1, PCLKB/2, PCLKB/8,
PCLKB/32, PCLKB/64, PCLKB/1024, PCLKB/8192) and one external clock signal
• Capable of output of pulse trains with desired duty cycles or of PWM signals
• The 2 channels of each unit can be cascaded to create a 16-bit timer
• Generation of triggers for A/D converter conversion
• Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12
• Capable of generating operating clock for the remote control signal receiver (REMC)
• Event linking by the ELC
Page 5 of 178
RX671 Group
Table 1.1
1. Overview
Outline of Specifications (5/10)
Classification
Module/Function
Description
Timers
Compare match timer
(CMT)
• (16 bits × 2 channels) × 2 units
• Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128,
PCLKB/512)
• Event linking by the ELC
Compare match timer W
(CMTW)
• (32 bits × 1 channel) × 2 units
• Compare-match, input-capture input, and output-comparison output are available.
• Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128,
PCLKB/512)
• Interrupt requests can be output in response to compare-match, input-capture, and
output-comparison events.
• Event linking by the ELC
Watchdog timer (WDTA) • 14 bits × 1 channel
• Select from among 6 counter-input clock signals (PCLKB/4, PCLKB/64, PCLKB/128,
PCLKB/512, PCLKB/2048, PCLKB/8192)
Independent watchdog
timer (IWDTa)
• 14 bits × 1 channel
• Counter-input clock: IWDT-dedicated on-chip oscillator
• Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,
dedicated clock/128, dedicated clock/256
• Window function: The positions where the window starts and ends are specifiable (the
window defines the timing with which refreshing is enabled and disabled).
• Event linking by the ELC
Multifunction timer pulse
unit (MTU3a)
• 9 channels (16 bits × 8 channels, 32 bits × 1 channel)
• Maximum of 28 pulse-input/output and 3 pulse-input possible
• Select from among 14 counter-input clock signals for each channel (PCLKA/1, PCLKA/
2, PCLKA/4, PCLKA/8, PCLKA/16, PCLK/A32, PCLKA/64, PCLKA/256, PCLKA/1024,
MTCLKA, MTCLKB, MTCLKC, MTCLKD, MTIOC1A)
14 of the signals are available for channel 0, 11 are available for channels 1, 3, 4, 6 to 8,
12 are available for channel 2, and 10 are available for channel 5.
• Input capture function
• 39 output compare/input capture registers
• Counter clear operation (synchronous clearing by compare match/input capture)
• Simultaneous writing to multiple timer counters (TCNT)
• Simultaneous register input/output by synchronous counter operation
• Buffered operation
• Support for cascade-connected operation
• 43 interrupt sources
• Automatic transfer of register data
• Pulse output mode
Toggle/PWM/complementary PWM/reset-synchronized PWM
• Complementary PWM output mode
Outputs non-overlapping waveforms for controlling 3-phase inverters
Automatic specification of dead times
PWM duty cycle: Selectable as any value from 0% to 100%
Delay can be applied to requests for A/D conversion.
Non-generation of interrupt requests at peak or trough values of counters can be
selected.
Double buffer configuration
• Reset synchronous PWM mode
Three phases of positive and negative PWM waveforms can be output with desired duty
cycles.
• Phase-counting mode: 16-bit mode (channels 1 and 2); 32-bit mode (channels 1 and 2)
• Counter functionality for dead-time compensation
• Generation of triggers for A/D converter conversion
• A/D converter start triggers can be skipped
• Digital filter function for signals on the input capture and external counter clock pins
• PPG output trigger can be generated
• Event linking by the ELC
Port output enable 3
(POE3a)
• Control of the high-impedance state of the MTU waveform output pins
• 5 pins for input from signal sources: POE0#, POE4#, POE8#, POE10#, POE11#
• Initiation on detection of short-circuited outputs (detection of simultaneous PWM output
to the active level)
• Initiation by oscillation-stoppage detection or software
• Additional programming of output control target pins is enabled
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Page 6 of 178
RX671 Group
Table 1.1
1. Overview
Outline of Specifications (6/10)
Classification
Module/Function
Description
Timers
Programmable pulse
generator (PPG)
• (4 bits × 4 groups) × 2 units
• Pulse output with the MTU or TPU output as a trigger
• Maximum of 32 pulse-output possible
Realtime clock (RTCd)*1 •
•
•
•
•
•
•
Communication
function
Clock sources: Main clock, sub clock
Selection of the 32-bit binary count in time count/second unit possible
Clock and calendar functions
Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
Battery backup operation
Time capture function (up to 3 pins)
Event linking by the ELC
USB 2.0 FS host/
function module (USBb)
•
•
•
•
•
•
•
•
Serial communications
interfaces
(SCIk, SCIm, SCIh)
• 13 channels (SCIk: 10 channels + SCIh: 1 channel + SCIm: 2 channels)
• SCIk, SCIh, SCIm
Serial communications modes: Asynchronous, clock synchronous, and smart-card
interface
Multi-processor function
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Start-bit detection: Level or edge detection is selectable.
Simple I2C
Simple SPI
9-bit transfer mode
Bit rate modulation
Double-speed mode
• SCIk, SCIh
Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12
Event linking by the ELC (only on channel 5)
• SCIh
Supports the serial communications protocol, which contains the start frame and
information frame
Supports the LIN format
• SCIm
Data can be transmitted or received in sequence by the 16-byte FIFO buffers of the
transmission and reception unit
• SCIk, SCIm
Data match detection
Adjustment of the timing of sampling of the RXD signals
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Includes a UDC (USB Device Controller) and transceiver for USB 2.0 FS
Up to two ports
Compliance with the USB 2.0 specification
Transfer rate: Full speed (12 Mbps), low speed (1.5 Mbps) (host only)
Both self-powered mode and bus-powered mode are supported
OTG (On the Go) operation is possible (low-speed is not supported)
Incorporates 2 Kbytes of RAM as a transfer buffer
External pull-up and pull-down resistors are not required
Page 7 of 178
RX671 Group
Table 1.1
1. Overview
Outline of Specifications (7/10)
Classification
Module/Function
Description
Communication
function
Serial communications
interfaces (RSCI)
• 2 channels (RSCI10, RSCI11)
• Serial communications modes: Asynchronous, clock synchronous, and smart-card
interface
• Multi-processor function
• On-chip baud rate generator allows selection of the desired bit rate
• Choice of LSB-first or MSB-first transfer
• Start-bit detection: Level or edge detection is selectable.
• Simple I2C
• Simple SPI
• 9-bit transfer mode
• Bit rate modulation
• Double-speed mode
• Event linking by the ELC (only RSCI10)
• Supports the serial communications protocol, which contains the start frame and
information frame
• Supports the LIN format
• Data can be transmitted or received in sequence by the 32-byte FIFO buffers of the
transmission and reception unit
• Manchester encoding is supported.
• HBS (home bus system) support mode
• Data match detection
• Adjustment of the timing of sampling of the RXD signals
I2C bus interface (RIICa) • 3 channels (only channel 0 can be used in fast-mode plus)
Communication formats
I2C bus format/SMBus format
Supports the multi-master
Max. transfer rate: 1 Mbps (channel 0)
• Event linking by the ELC
High-speed I2C bus
interface (RIICHS)
• 1 channel
Communication formats
I2C bus format/SMBus format
Supports the multi-master
Max. transfer rate: 3.4 Mbps
• Event linking by the ELC
CAN module (CAN)
• 2 channels
• Compliance with the ISO11898-1 specification (standard frame and extended frame)
• 32 mailboxes per channel
Serial peripheral
interface (RSPId)
• 3 channels
• RSPI transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),
and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four
lines) or clock-synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
• Data formats
Switching between MSB first and LSB first
The number of bits in each transfer can be changed to any number of bits from 8 to 16,
or to 20, 24, or 32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with
each frame having up to 32 bits)
Transmit/receive data can be swapped in byte units
• Buffered structure
Double buffers for both transmission and reception
• RSPCK can be stopped with the receive buffer full for master reception.
• Event linking by the ELC
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Page 8 of 178
RX671 Group
Table 1.1
1. Overview
Outline of Specifications (8/10)
Classification
Module/Function
Description
Communication
function
Serial peripheral
interface (RSPIA)
• 1 channel
• RSPI transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),
and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four
lines) or clock-synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
• Data formats
Switching between MSB first and LSB first
The number of bits in each transfer can be changed to any number of bits from 8 to 16,
or to 20, 24, or 32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with
each frame having up to 32 bits)
Transit/receive data can be swapped in byte units
• Buffered structure
The transmission and reception sections have 4-stage and 32-bit-wide FIFO buffers for
the sequential transmission and reception of data.
• RSPCK can be stopped with the receive buffer full for master reception.
• Event linking by the ELC
• Communications protocol: RSPIA supports the Texas Instruments Synchronous Serial
Protocol (TI SSP).
Quad-SPI memory
interface (QSPIX)
• 1 channel
• This interface can handle fetching from serial flash memory that has an SPI-compatible
interface.
• It supports extended SPI, dual-SPI, and quad-SPI protocols.
• Address width is selectable from among 8, 16, 24, and 32 bits.
Remote control signal
receiver (REMCa)
•
•
•
•
Serial sound interface (SSIE)
•
•
•
•
•
SD host interface (SDHI)*2
•
•
•
•
1 channel
Full-duplex transmission
Various types of serial audio formatting are supported.
Master and slave operations are supported.
The bit-clock frequency is selectable from among 13 frequencies (1/1, 1/2, 1/4, 1/6, 1/8,
1/12, 1/16, 1/24, 1/32, 1/48, 1/64, 1/96, or 1/128).
• Data formats with 8, 16, 18, 20, 22, 24, and 32 bits are supported.
• 32-stage FIFO buffers for transmission and reception
• Stopping or not stopping the SSILRCK signal on stopping of data transmission is
selectable.
•
•
•
•
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
1 channel
Four pattern matching (header, data 0, data 1, and special data detection)
8-byte receive buffer per unit
The operating clock can be selected from among the PCLK, sub-clock, and TMR.
1 channel
Transfer speed: Supports high-speed mode (25 MB/s) and default speed mode (12.5 MB/s)
One interface for SD memory and I/O cards (supporting 1- and 4-bit SD buses)
SD specifications
Part 1: Physical Layer Specification Ver. 3.01 compliant (DDR not supported)
Part E1: SDIO Specification Ver. 3.00
Error checking: CRC7 for commands and CRC16 for data
Interrupt requests: Card access interrupt, SDIO access interrupt, card detection
interrupt, SD buffer access interrupt
DMA transfer requests: SD_BUF write and SD_BUF read
Support for card detection and write protection
Page 9 of 178
RX671 Group
Table 1.1
Classification
1. Overview
Outline of Specifications (9/10)
Module/Function
Description
12-bit A/D converter (S12ADFa)
• 12 bits × 2 units (unit 0: 8 channels; unit 1: 12 channels)
• 12-bit resolution (switchable between 8, 10, and 12 bits)
• Conversion time
0.48 µs per channel (for 12-bit conversion)
0.45 µs per channel (for 10-bit conversion)
0.42 µs per channel (for 8-bit conversion)
• Operating mode
Scan mode (single scan mode, continuous scan mode, or 3 group scan mode)
Group priority control (only for 3 group scan mode)
• Sample-and-hold function
Common sample-and-hold circuit included
• Sampling variable
Sampling time can be set up for each channel.
• Digital comparison
Method: Comparison to detect voltages above or below thresholds and window
comparison
Measurement: Comparison of two results of conversion or comparison of a value in the
comparison register and a result of conversion
• Self-diagnostic function
The self-diagnostic function internally generates three analog input voltages
(unit 0: VREFL0, VREFH0 × 1/2, VREFH0; unit 1: AVSS1, AVCC1 × 1/2, AVCC1)
• Double trigger mode (A/D conversion data duplicated)
• Detection of analog input disconnection
• Three ways to start A/D conversion
Software trigger, timer (MTU, TMR, TPU) trigger, external trigger
• Event linking by the ELC
Temperature sensor
• 1 channel
• Relative precision: ± 1°C
• The voltage of the temperature is converted into a digital value by the 12-bit A/D
converter (unit 1).
Capacitive touch sensing unit (CTSUa)
• Detection pin: 17 channels
Safety
Memory protection unit
(MPU)
• Protection area: Eight areas (max.) can be specified in the range from 0000 0000h to
FFFF FFFFh.
• Minimum protection unit: 16 bytes
• Reading from, writing to, and enabling the execution access can be specified for each
area.
• An access exception occurs when the detected access is not in the permitted area.
Trusted Memory (TM)
Function
• Programs in the TM target area in the code flash memory are protected against reading
• Instruction fetching by the CPU is the only form of access to these areas when the TM
function is enabled.
Register write protection
function
• Protects important registers from being overwritten for in case a program runs out of
control.
CRC calculator (CRCA)
• Generation of CRC codes for 8-/32-bit data
8-bit data
Selectable from the following three polynomials
X8 + X2 + X + 1, X16 + X15 + X2 + 1, X16 + X12 + X5 + 1
32-bit data
Selectable from the following two polynomials
X32 + X26 + X23 + X22 + X16+ X12 + X11 + X10 + X8+ X7 + X5 + X4 + X2+ X + 1,
X32 + X28 + X27 + X26 + X25 + X23 + X22 + X20 + X19 + X18 + X14 + X13 + X11 + X10 + X9 +
X8 + X6 + 1
• Generation of CRC codes for use with LSB-first or MSB-first communications is
selectable
Main clock oscillation
stop detection
• Main clock oscillation stop detection: Available
Clock frequency
accuracy measurement
circuit (CAC)
• Monitors the clock output from the main clock oscillator, sub-clock oscillator, low- and
high-speed on-chip oscillators, IWDT-dedicated on-chip oscillator, and PCLKB, and
generates interrupts when the setting range is exceeded.
Data operation circuit
(DOCA)
• This handles the comparison, addition, subtraction, comparison in terms of which is
larger or smaller, or window comparison of 32-bit values.
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 10 of 178
RX671 Group
Table 1.1
1. Overview
Outline of Specifications (10/10)
Classification
Module/Function
Description
Encryption
function
Trusted Secure IP
(TSIP)*3
• Access management circuit
• Encryption engine
Common key encryption: AES (compliant with NIST FIPS PUB 197), TDES, ARC4
Public key encryption: RSA, ECC
Hash functions: SHA1, SHA224, SHA256, MD5, GHASH
• Other features
TRNG (true-random number generator)
Prevention from illicit copying of a key
Operating frequency
Up to 120 MHz
Power supply voltage
VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VBATT = 1.62*4 to 3.6 V
Operating temperature
D-version: –40 to +85°C
G-version: –40 to +105°C
Package
145-pin TFLGA (PTLG0145JC-A)
145-pin TFLGA (PTLG0145KB-A)
144-pin LFQFP (PLQP0144KA-B)
100-pin TFLGA (PTLG0100JB-A)
100-pin LFQFP (PLQP0100KB-B)
64-pin TFBGA (PTBG0064KB-A)
64-pin LFQFP (PLQP0064KB-C)
48-pin HWQFN (PWQN0048KC-A)
Debugging interface
JTAG and FINE interfaces
Note 1. When the realtime clock is not used, initialize the registers in the time clock according to description in section 31.6.8,
Initialization Procedure When the Realtime Clock is Not to be Used in the User’s Manual: Hardware.
Note 2. The product part number differs according to whether or not the MCU includes an SDHI (SD host interface).
Note 3. The product part number differs according to whether or not the MCU includes the encryption function.
Note 4. The low CL crystal unit cannot be used when the VBATT voltage is less than 2.0 V.
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 11 of 178
RX671 Group
Table 1.2
1. Overview
Comparison of Functions for Different Packages (1/2)
Products
Package
RX671
145-pin TFLGA
(0.65-mm pitch)
Functions
Code Flash
Memory
145-pin TFLGA
(0.50-mm pitch)
144-pin LFQFP
Code Flash Memory Capacity
100-pin TFLGA
100-pin LFQFP
Available
BGO function
Available
8 Kbytes
RAM
384 Kbytes
Standby RAM
4 Kbytes
External bus
External bus width
DMA
DMA controller
SDRAM area controller
16/8 bits
Not available
Available
Not available
Ch. 0 to 7
Data transfer controller
Available
EXDMA controller
Ch. 0 and 1
Not available
16-bit timer pulse unit
Ch. 0 to 5
Multi-function timer pulse unit 3
Ch. 0 to 8
Port output enable 3
Available
Programmable pulse generator
Ch. 0 and 1
Not available
8-bit timers
Ch. 0 to 3
Compare match timer
Ch. 0 to 3
Compare match timer W
Ch. 0 and 1
Realtime clock
Communication
function
48-pin HWQFN
1 Mbyte/1.5 Mbytes/2 Mbytes
Dual bank function
Data Flash Memory
Timers
64-pin TFBGA
64-pin LFQFP
Available
Not available
Watchdog timer
Available
Independent watchdog timer
Available
USB 2.0 FS host/function module
Serial communications interfaces
(SCIk)
Ch. 0 and 1
Ch. 0*1
Ch. 0
Ch. 0 to 9
Ch. 0 to 3, 5, 6, 8
and 9
Serial communications interfaces
(SCIm)
Ch. 10 and 11
Serial communications interfaces
(SCIh)
Ch. 12
Serial communications interfaces
(RSCI)
Ch. 10 and 11
I2C bus interfaces (RIIC)
Hi-speed
(RIICHS)
I2C
Ch. 0 and 2
Ch. 0
Ch. 0 to 2
Ch. 0 and 1
Serial peripheral interface
(RSPIA)
CAN module
Ch. 0
Ch. 0 and 1
Not available
Quad-SPI memory interface
(QSPIX)
Ch. 0
SD host interface (SDHI)
Available
Serial sound interface (SSIE)
Ch. 0
Remote control signal receiver
(REMC)
Ch. 0
Capacitive touch sensing unit (CTSU)
12-bit A/D converter
17 channels + 1 channel (TSCAP)
Unit 0: 8 channels
Unit 1: 12 channels
Unit 0: 8 channels
Unit 1: 8 channels
Temperature sensor
Available
CRC calculator
Available
Data operation circuit (DOC)
Available
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Ch. 1 to 3, 5, 8 and 9
Ch. 0 to 2
bus interfaces
Serial peripheral interface (RSPI)
Not available
8 channels + 1
channel (TSCAP)
6 channels + 1
channel (TSCAP)
Unit 0: 4 channels
Unit 1: 6 channels
Unit 0: 4 channels
Unit 1: 4 channels
Page 12 of 178
RX671 Group
Table 1.2
1. Overview
Comparison of Functions for Different Packages (2/2)
Products
Package
Functions
RX671
145-pin TFLGA
(0.65-mm pitch)
145-pin TFLGA
(0.50-mm pitch)
144-pin LFQFP
100-pin TFLGA
100-pin LFQFP
Clock frequency accuracy measurement circuit
(CAC)
48-pin HWQFN
Available
Trusted Secure IP
Available/Not available
Event link controller (ELC)
Available
Battery backup function
Available
Backup register
Off-board programming (parallel programmer mode)
64-pin TFBGA
64-pin LFQFP
Not available
Available
Available
Not available
Note 1. Only supports the function controller.
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 13 of 178
RX671 Group
1.2
1. Overview
List of Products
Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part no.
Table 1.3
List of Products (1/3)
Group
Part No.
Package
Code Flash
Memory
Capacity
(byte(s))
RX671
(D-version)
R5F5671EHDFB
PLQP0144KA-B
2M
384 K
8K
120 MHz
Available
–40 to +85
R5F5671EDDFB
PLQP0144KA-B
2M
384 K
8K
120 MHz
Not available
–40 to +85
R5F5671CHDFB
PLQP0144KA-B
1.5 M
384 K
8K
120 MHz
Available
–40 to +85
RAM
Capacity
(byte(s))
Data Flash
Memory
Capacity
(byte(s))
Operating
Frequency
(Max.)
Encryption
Module
Operating
temperature
(°C)
R5F5671CDDFB
PLQP0144KA-B
1.5 M
384 K
8K
120 MHz
Not available
–40 to +85
R5F56719HDFB
PLQP0144KA-B
1M
384 K
8K
120 MHz
Available
–40 to +85
R5F56719DDFB
PLQP0144KA-B
1M
384 K
8K
120 MHz
Not available
–40 to +85
R5F5671EHDFP
PLQP0100KB-B
2M
384 K
8K
120 MHz
Available
–40 to +85
R5F5671EDDFP
PLQP0100KB-B
2M
384 K
8K
120 MHz
Not available
–40 to +85
R5F5671CHDFP
PLQP0100KB-B
1.5 M
384 K
8K
120 MHz
Available
–40 to +85
R5F5671CDDFP
PLQP0100KB-B
1.5 M
384 K
8K
120 MHz
Not available
–40 to +85
R5F56719HDFP
PLQP0100KB-B
1M
384 K
8K
120 MHz
Available
–40 to +85
R5F56719DDFP
PLQP0100KB-B
1M
384 K
8K
120 MHz
Not available
–40 to +85
R5F5671EHDFM
PLQP0064KB-C
2M
384 K
8K
120 MHz
Available
–40 to +85
R5F5671EDDFM
PLQP0064KB-C
2M
384 K
8K
120 MHz
Not available
–40 to +85
R5F5671CHDFM
PLQP0064KB-C
1.5 M
384 K
8K
120 MHz
Available
–40 to +85
R5F5671CDDFM
PLQP0064KB-C
1.5 M
384 K
8K
120 MHz
Not available
–40 to +85
R5F56719HDFM
PLQP0064KB-C
1M
384 K
8K
120 MHz
Available
–40 to +85
R5F56719DDFM
PLQP0064KB-C
1M
384 K
8K
120 MHz
Not available
–40 to +85
R5F5671EHDNE
PWQN0048KC-A
2M
384 K
8K
120 MHz
Available
–40 to +85
R5F5671EDDNE
PWQN0048KC-A
2M
384 K
8K
120 MHz
Not available
–40 to +85
R5F5671CHDNE
PWQN0048KC-A
1.5 M
384 K
8K
120 MHz
Available
–40 to +85
R5F5671CDDNE
PWQN0048KC-A
1.5 M
384 K
8K
120 MHz
Not available
–40 to +85
R5F56719HDNE
PWQN0048KC-A
1M
384 K
8K
120 MHz
Available
–40 to +85
R5F56719DDNE
PWQN0048KC-A
1M
384 K
8K
120 MHz
Not available
–40 to +85
R5F5671EHDBP
PTBG0064KB-A
2M
384 K
8K
120 MHz
Available
–40 to +85
R5F5671EDDBP
PTBG0064KB-A
2M
384 K
8K
120 MHz
Not available
–40 to +85
R5F5671CHDBP
PTBG0064KB-A
1.5 M
384 K
8K
120 MHz
Available
–40 to +85
R5F5671CDDBP
PTBG0064KB-A
1.5 M
384 K
8K
120 MHz
Not available
–40 to +85
R5F56719HDBP
PTBG0064KB-A
1M
384 K
8K
120 MHz
Available
–40 to +85
R5F56719DDBP
PTBG0064KB-A
1M
384 K
8K
120 MHz
Not available
–40 to +85
R5F5671EHDLE
PTLG0145JC-A
2M
384 K
8K
120 MHz
Available
–40 to +85
R5F5671EDDLE
PTLG0145JC-A
2M
384 K
8K
120 MHz
Not available
–40 to +85
R5F5671CHDLE
PTLG0145JC-A
1.5 M
384 K
8K
120 MHz
Available
–40 to +85
R5F5671CDDLE
PTLG0145JC-A
1.5 M
384 K
8K
120 MHz
Not available
–40 to +85
R5F56719HDLE
PTLG0145JC-A
1M
384 K
8K
120 MHz
Available
–40 to +85
R5F56719DDLE
PTLG0145JC-A
1M
384 K
8K
120 MHz
Not available
–40 to +85
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 14 of 178
RX671 Group
Table 1.3
1. Overview
List of Products (2/3)
Group
Part No.
Package
Code Flash
Memory
Capacity
(byte(s))
RX671
(D-version)
R5F5671EHDLK
PTLG0145KB-A
2M
384 K
8K
120 MHz
Available
–40 to +85
R5F5671EDDLK
PTLG0145KB-A
2M
384 K
8K
120 MHz
Not available
–40 to +85
R5F5671CHDLK
PTLG0145KB-A
1.5 M
384 K
8K
120 MHz
Available
–40 to +85
R5F5671CDDLK
PTLG0145KB-A
1.5 M
384 K
8K
120 MHz
Not available
–40 to +85
R5F56719HDLK
PTLG0145KB-A
1M
384 K
8K
120 MHz
Available
–40 to +85
R5F56719DDLK
PTLG0145KB-A
1M
384 K
8K
120 MHz
Not available
–40 to +85
R5F5671EHDLJ
PTLG0100JB-A
2M
384 K
8K
120 MHz
Available
–40 to +85
R5F5671EDDLJ
PTLG0100JB-A
2M
384 K
8K
120 MHz
Not available
–40 to +85
R5F5671CHDLJ
PTLG0100JB-A
1.5 M
384 K
8K
120 MHz
Available
–40 to +85
R5F5671CDDLJ
PTLG0100JB-A
1.5 M
384 K
8K
120 MHz
Not available
–40 to +85
R5F56719HDLJ
PTLG0100JB-A
1M
384 K
8K
120 MHz
Available
–40 to +85
R5F56719DDLJ
PTLG0100JB-A
1M
384 K
8K
120 MHz
Not available
–40 to +85
R5F5671EHGFB
PLQP0144KA-B
2M
384 K
8K
120 MHz
Available
–40 to +105
R5F5671EDGFB
PLQP0144KA-B
2M
384 K
8K
120 MHz
Not available
–40 to +105
R5F5671CHGFB
PLQP0144KA-B
1.5 M
384 K
8K
120 MHz
Available
–40 to +105
R5F5671CDGFB
PLQP0144KA-B
1.5 M
384 K
8K
120 MHz
Not available
–40 to +105
R5F56719HGFB
PLQP0144KA-B
1M
384 K
8K
120 MHz
Available
–40 to +105
R5F56719DGFB
PLQP0144KA-B
1M
384 K
8K
120 MHz
Not available
–40 to +105
R5F5671EHGFP
PLQP0100KB-B
2M
384 K
8K
120 MHz
Available
–40 to +105
R5F5671EDGFP
PLQP0100KB-B
2M
384 K
8K
120 MHz
Not available
–40 to +105
R5F5671CHGFP
PLQP0100KB-B
1.5 M
384 K
8K
120 MHz
Available
–40 to +105
R5F5671CDGFP
PLQP0100KB-B
1.5 M
384 K
8K
120 MHz
Not available
–40 to +105
R5F56719HGFP
PLQP0100KB-B
1M
384 K
8K
120 MHz
Available
–40 to +105
R5F56719DGFP
PLQP0100KB-B
1M
384 K
8K
120 MHz
Not available
–40 to +105
R5F5671EHGFM
PLQP0064KB-C
2M
384 K
8K
120 MHz
Available
–40 to +105
R5F5671EDGFM
PLQP0064KB-C
2M
384 K
8K
120 MHz
Not available
–40 to +105
R5F5671CHGFM
PLQP0064KB-C
1.5 M
384 K
8K
120 MHz
Available
–40 to +105
R5F5671CDGFM
PLQP0064KB-C
1.5 M
384 K
8K
120 MHz
Not available
–40 to +105
R5F56719HGFM
PLQP0064KB-C
1M
384 K
8K
120 MHz
Available
–40 to +105
R5F56719DGFM
PLQP0064KB-C
1M
384 K
8K
120 MHz
Not available
–40 to +105
R5F5671EHGNE
PWQN0048KC-A
2M
384 K
8K
120 MHz
Available
–40 to +105
R5F5671EDGNE
PWQN0048KC-A
2M
384 K
8K
120 MHz
Not available
–40 to +105
R5F5671CHGNE
PWQN0048KC-A
1.5 M
384 K
8K
120 MHz
Available
–40 to +105
R5F5671CDGNE
PWQN0048KC-A
1.5 M
384 K
8K
120 MHz
Not available
–40 to +105
R5F56719HGNE
PWQN0048KC-A
1M
384 K
8K
120 MHz
Available
–40 to +105
R5F56719DGNE
PWQN0048KC-A
1M
384 K
8K
120 MHz
Not available
–40 to +105
R5F5671EHGBP
PTBG0064KB-A
2M
384 K
8K
120 MHz
Available
–40 to +105
R5F5671EDGBP
PTBG0064KB-A
2M
384 K
8K
120 MHz
Not available
–40 to +105
R5F5671CHGBP
PTBG0064KB-A
1.5 M
384 K
8K
120 MHz
Available
–40 to +105
R5F5671CDGBP
PTBG0064KB-A
1.5 M
384 K
8K
120 MHz
Not available
–40 to +105
RX671
(G-version)
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
RAM
Capacity
(byte(s))
Data Flash
Memory
Capacity
(byte(s))
Operating
Frequency
(Max.)
Encryption
Module
Operating
temperature
(°C)
Page 15 of 178
RX671 Group
Table 1.3
1. Overview
List of Products (3/3)
Group
Part No.
Package
Code Flash
Memory
Capacity
(byte(s))
RX671
(G-version)
R5F56719HGBP
PTBG0064KB-A
1M
384 K
8K
120 MHz
Available
–40 to +105
R5F56719DGBP
PTBG0064KB-A
1M
384 K
8K
120 MHz
Not available
–40 to +105
R5F5671EHGLE
PTLG0145JC-A
2M
384 K
8K
120 MHz
Available
–40 to +105
R5F5671EDGLE
PTLG0145JC-A
2M
384 K
8K
120 MHz
Not available
–40 to +105
R5F5671CHGLE
PTLG0145JC-A
1.5 M
384 K
8K
120 MHz
Available
–40 to +105
R5F5671CDGLE
PTLG0145JC-A
1.5 M
384 K
8K
120 MHz
Not available
–40 to +105
R5F56719HGLE
PTLG0145JC-A
1M
384 K
8K
120 MHz
Available
–40 to +105
R5F56719DGLE
PTLG0145JC-A
1M
384 K
8K
120 MHz
Not available
–40 to +105
R5F5671EHGLK
PTLG0145KB-A
2M
384 K
8K
120 MHz
Available
–40 to +105
R5F5671EDGLK
PTLG0145KB-A
2M
384 K
8K
120 MHz
Not available
–40 to +105
R5F5671CHGLK
PTLG0145KB-A
1.5 M
384 K
8K
120 MHz
Available
–40 to +105
R5F5671CDGLK
PTLG0145KB-A
1.5 M
384 K
8K
120 MHz
Not available
–40 to +105
R5F56719HGLK
PTLG0145KB-A
1M
384 K
8K
120 MHz
Available
–40 to +105
RAM
Capacity
(byte(s))
Data Flash
Memory
Capacity
(byte(s))
Operating
Frequency
(Max.)
Encryption
Module
Operating
temperature
(°C)
R5F56719DGLK
PTLG0145KB-A
1M
384 K
8K
120 MHz
Not available
–40 to +105
R5F5671EHGLJ
PTLG0100JB-A
2M
384 K
8K
120 MHz
Available
–40 to +105
R5F5671EDGLJ
PTLG0100JB-A
2M
384 K
8K
120 MHz
Not available
–40 to +105
R5F5671CHGLJ
PTLG0100JB-A
1.5 M
384 K
8K
120 MHz
Available
–40 to +105
R5F5671CDGLJ
PTLG0100JB-A
1.5 M
384 K
8K
120 MHz
Not available
–40 to +105
R5F56719HGLJ
PTLG0100JB-A
1M
384 K
8K
120 MHz
Available
–40 to +105
R5F56719DGLJ
PTLG0100JB-A
1M
384 K
8K
120 MHz
Not available
–40 to +105
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 16 of 178
RX671 Group
R
5
F
1. Overview
5 6
7 1
E
D
D
F B
# 3
0
Production identification code
Packing
#2
: Tray (BGA, LGA)
#1, #3: Tray (LFQFP, QFN)
Package type, number of pins, and pin
pitch
LE : TFLGA/145/0.65
LK : TFLGA/145/0.50
FB : LFQFP/144/0.50
FP : LFQFP/100/0.50
LJ : TFLGA/100/0.65
FM: LFQFP/64/0.50
BP: TFBGA/64/0.50
NE: HWQFN/48/0.50
D : Operating peripheral temperature: –
40 to +85°C
G : Operating peripheral temperature: –
40 to +105°C
D : Encryption module not included
H : Encryption module included
Code flash memory, RAM, and data flash
memory capacity
9 : 1 Mbyte/384 Kbytes/8 Kbytes
C : 1.5 Mbytes/384 Kbytes/8 Kbytes
E : 2 Mbytes/384 Kbytes/8 Kbytes
Group name
RX671 Group
Series name
RX600 Series
Type of memory
F : Flash memory version
Renesas MCU
Renesas semiconductor product
Figure 1.1
How to Read the Product Part Number
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RX671 Group
1.3
1. Overview
Block Diagram
Figure 1.2 shows a block diagram.
Trusted Secure IP
ELC
Standby RAM
CAC
Data Flash
DOC
RSCI × 2ch
CRC
RIICHS
MTU × 9ch
RSPIA
POE3
REMC
TPU × 6ch
CTSU
PPG × 2ch
SSIE
TMR × 2ch (unit 0)
Internal peripheral buses 1 to 6
TMR × 2ch (unit 1)
CMT × 4ch
CMTW × 2ch
WDT
IWDT
Port 1
RTC
Port 2
SCIk × 10ch
Port 3
SCIm × 2ch
SCIh × 1ch
RAM
Operand bus
USB × 2 ports
DTC
Internal main bus 1
MPU
Clock
generation
circuit
ICU:
DTC
DMAC:
EXDMAC:
BSC:
CAC:
CRC:
DOC:
ELC:
SCIk, SCIh,
SCIm, RSCI:
RSPI, RSPIA:
RIIC, RIICHS:
USB:
CAN:
MTU:
Figure 1.2
Port 5
Port 6
CAN × 2ch
Port 7
RSPI × 3ch
Port 8
SDHI
Port 9
12-bit A/D converter × 8 channels (unit 0)
Port A
DMAC
× 8ch
12-bit A/D converter × 12 channels (unit 1)
Port B
Temperature sensor
Port C
Port D
EXDMAC
Port F
Interrupt controller
Data transfer controller
DMA controller
EXDMA controller
Bus controller
Clock frequency accuracy measurement circuit
CRC (cyclic redundancy check) calculator
Data operation circuit
Event link controller
Serial communications interface
Serial peripheral interface
I2C bus interface
USB2.0 FS host/function module
CAN module
Multi-function timer pulse unit 3
Port E
BSC
Internal
extended bus
RX CPU
Internal main bus 2
ROM
cache
Port 4
RIIC × 3ch
ICU
Instruction bus
ROM
Port 0
Port H
QSPIX
Port J
POE3:
Port output enable 3
TPU:
16-bit timer pulse unit
PPG:
Programmable pulse generator
TMR:
8-bit timer
CMT:
Compare match timer
CMTW:
Compare match timer W
WDT:
Watchdog timer
IWDT:
Independent watchdog timer
RTC:
Realtime clock
SDHI:
SD host interface
QSPIX:
Quad-SPI memory interface
SSIE:
Serial sound interface
CTSU:
Capacitive touch sensing unit
REMC:
Remote control signal receiver
Trusted Secure IP: Encryption engine
Note:
Available functions depend on the product.
Block Diagram
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RX671 Group
1.4
1. Overview
Pin Functions
Table 1.4 lists the pin functions.
Table 1.4
Pin Functions (1/8)
Classifications
Pin Name
I/O
Description
Digital power supply
VCC
Input
Power supply pin. Connect this pin to the system power supply.
Connect the pin to VSS via a 0.1-µF multilayer ceramic
capacitor. The capacitor should be placed close to the pin.
VCL
Input
Connect this pin to VSS via a 0.22-µF multilayer ceramic
capacitor. The capacitor should be placed close to the pin.
VSS
Input
Ground pin. Connect it to the system power supply (0 V).
VBATT
Input
Backup power pin
XTAL
Output
Pins for a crystal resonator. An external clock signal can be
input through the EXTAL pin.
Clock
EXTAL
Input
BCLK
Output
Outputs the external bus clock for external devices.
SDCLK
Output
Outputs the SDRAM-dedicated clock.
Input/output pins for the sub clock oscillator. Connect a crystal
resonator between XCOUT and XCIN.
XCOUT
Output
XCIN
Input
CLKOUT
Output
Clock output pin.
EXCIN
Input
External clock input pin for the RTC, battery backup, and REMC
Clock frequency accuracy
measurement
CACREF
Input
Reference clock input pin for the clock frequency accuracy
measurement circuit
Operating mode control
MD
Input
Pin for setting the operating mode. The signal level on this pin
must not be changed during operation.
UB
Input
USB boot mode enable pin
UPSEL
Input
Selects the power supply method in USB boot mode.
The low level selects self-powered mode and the high level
selects bus-powered mode.
RES#
Input
Reset signal input pin. This LSI enters the reset state when this
signal goes low.
EMLE
Input
Input pin for the on-chip emulator enable signal. When the onchip emulator is used, this pin should be driven high. When not
used, it should be driven low.
BSCANP
Input
Boundary scan enable pin. Boundary scan is enabled when this
pin goes high. When not used, it should be driven low.
FINED
I/O
Fine interface pin
TRST#
Input
TMS
Input
On-chip emulator or boundary scan pins. When the EMLE pin is
driven high, these pins are dedicated for the on-chip emulator.
System control
On-chip emulator
TDI
Input
TCK
Input
TDO
Output
TRCLK
Output
This pin outputs the clock for synchronization with the trace
data.
TRSYNC
TRSYNC1
Output
These pins indicate that output from the TRDATA0 to TRDATA7
pins is valid.
TRDATA0
TRDATA1
TRDATA2
TRDATA3
TRDATA4
TRDATA5
TRDATA6
TRDATA7
Output
These pins output the trace information.
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RX671 Group
Table 1.4
1. Overview
Pin Functions (2/8)
Classifications
Pin Name
I/O
Description
Address bus
A0 to A23
Output
Output pins for the address
Data bus
D0 to D15
I/O
Input and output pins for the bidirectional data bus
Multiplexed bus
A0/D0 to A15/D15
I/O
Address/data multiplexed bus
Bus control
RD#
Output
Strobe signal which indicates that reading from the external bus
interface space is in progress
WR#
Output
Strobe signal which indicates that writing to the external bus
interface space is in progress, in 1-write strobe mode
WR0#, WR1#
Output
Strobe signals which indicate that either group of data bus pins
(D7 to D0 and D15 to D8) is valid in writing to the external bus
interface space, in byte strobe mode
BC0#, BC1#
Output
Strobe signals which indicate that either group of data bus pins
(D7 to D0 and D15 to D8) is valid in access to the external bus
interface space, in 1-write strobe mode
ALE
Output
Address latch signal when address/data multiplexed bus is
selected
SDRAM interface
EXDMA controller
Interrupt
Multi-function timer pulse
unit 3
Port output enable 3
WAIT#
Input
Input pin for wait request signals in access to the external space
CS0# to CS7#
Output
Select signals for CS areas
CKE
Output
SDRAM clock enable signal
SDCS#
Output
SDRAM chip select signal
RAS#
Output
SDRAM row address strobe signal
CAS#
Output
SDRAM column address strove signal
WE#
Output
SDRAM write enable pin
DQM0, DQM1
Output
SDRAM I/O data mask enable signals
EDREQ0, EDREQ1
Input
External DMA transfer request pins
EDACK0, EDACK1
Output
Single address transfer acknowledge signals
NMI
Input
Non-maskable interrupt request pin
IRQ0 to IRQ15, IRQ0-DS to
IRQ15-DS
Input
Maskable interrupt request pins
MTIOC0A, MTIOC0B,
MTIOC0C, MTIOC0D
I/O
The TGRA0 to TGRD0 input capture input/output compare
output/PWM output pins
MTIOC1A, MTIOC1B
I/O
The TGRA1 and TGRB1 input capture input/output compare
output/PWM output pins
MTIOC2A, MTIOC2B
I/O
The TGRA2 and TGRB2 input capture input/output compare
output/PWM output pins
MTIOC3A, MTIOC3B,
MTIOC3C, MTIOC3D
I/O
The TGRA3 to TGRD3 input capture input/output compare
output/PWM output pins
MTIOC4A, MTIOC4B,
MTIOC4C, MTIOC4D
I/O
The TGRA4 to TGRD4 input capture input/output compare
output/PWM output pins
MTIC5U, MTIC5V, MTIC5W
Input
The TGRU5, TGRV5, and TGRW5 input capture input/dead
time compensation input pins
MTIOC6A, MTIOC6B,
MTIOC6C, MTIOC6D
I/O
The TGRA6 to TGRD6 input capture input/output compare
output/PWM output pins
MTIOC7A, MTIOC7B,
MTIOC7C, MTIOC7D
I/O
The TGRA7 to TGRD7 input capture input/output compare
output/PWM output pins
MTIOC8A, MTIOC8B,
MTIOC8C, MTIOC8D
I/O
The TGRA8 to TGRD8 input capture input/output compare
output/PWM output pins
MTCLKA, MTCLKB,
MTCLKC, MTCLKD
Input
Input pins for external clock signals or for phase counting mode
clock signals
POE0#, POE4#, POE8#,
POE10#, POE11#
Input
Input pins for request signals to place the MTU in the high
impedance state
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RX671 Group
Table 1.4
1. Overview
Pin Functions (3/8)
Classifications
Pin Name
I/O
Description
16-bit timer pulse unit
TIOCA0, TIOCB0,
TIOCC0, TIOCD0
I/O
The TGRA0 to TGRD0 input capture input/output compare
output/PWM output pins
TIOCA1, TIOCB1
I/O
The TGRA1 and TGRB1 input capture input/output compare
output/PWM output pins
TIOCA2, TIOCB2
I/O
The TGRA2 and TGRB2 input capture input/output compare
output/PWM output pins
TIOCA3, TIOCB3,
TIOCC3, TIOCD3
I/O
The TGRA3 to TGRD3 input capture input/output compare
output/PWM output pins
TIOCA4, TIOCB4
I/O
The TGRA4 and TGRB4 input capture input/output compare
output/PWM output pins
TIOCA5, TIOCB5
I/O
The TGRA5 and TGRB5 input capture input/output compare
output/PWM output pins
TCLKA, TCLKB,
TCLKC, TCLKD
Input
Input pins for external clock signals or for phase counting mode
clock signals
Programmable pulse
generator
PO0 to PO31
Output
Output pins for the pulse signals
8-bit timer
TMO0 to TMO3
Output
Compare match output pins
TMCI0 to TMCI3
Input
Input pins for external clocks to be input to the counter
Compare match timer W
Serial communications
interface (SCIk)
TMRI0 to TMRI3
Input
Input pins for the counter reset
TIC0 to TIC3
Input
Input pins for CMTW
TOC0 to TOC3
Output
Output pins for CMTW
• Asynchronous mode/clock synchronous mode
SCK0 to SCK9
I/O
Input/output pins for the clock
RXD0 to RXD9
Input
Input pins for received data
TXD0 to TXD9
Output
Output pins for transmitted data
CTS0# to CTS9#
Input
Input pins for controlling the start of transmission and reception
RTS0# to RTS9#
Output
Output pins for controlling the start of transmission and
reception
SSCL0 to SSCL9
I/O
Input/output pins for the I2C clock
SSDA0 to SSDA9
I/O
Input/output pins for the I2C data
SCK0 to SCK9
I/O
Input/output pins for the clock
SMISO0 to SMISO9
I/O
Input/output pins for slave transmission of data
• Simple I2C mode
• Simple SPI mode
SMOSI0 to SMOSI9
I/O
Input/output pins for master transmission of data
SS0# to SS9#
Input
Chip-select input pins
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RX671 Group
Table 1.4
1. Overview
Pin Functions (4/8)
Classifications
Pin Name
I/O
Description
Serial communications
interface (SCIh)
• Asynchronous mode/clock synchronous mode
SCK12
I/O
Input/output pin for the clock
RXD12
Input
Input pin for received data
TXD12
Output
Output pin for transmitted data
CTS12#
Input
Input pin for controlling the start of transmission and reception
RTS12#
Output
Output pin for controlling the start of transmission and reception
SSCL12
I/O
Input/output pin for the I2C clock
SSDA12
I/O
Input/output pin for the I2C data
• Simple I2C mode
• Simple SPI mode
SCK12
I/O
Input/output pin for the clock
SMISO12
I/O
Input/output pin for slave transmission of data
SMOSI12
I/O
Input/output pin for master transmission of data
SS12#
Input
Chip-select input pin
RXDX12
Input
Input pin for received data
TXDX12
Output
Output pin for transmitted data
SIOX12
I/O
Input/output pin for received or transmitted data
• Extended serial mode
Serial communications
interface (SCIm)
• Asynchronous mode/clock synchronous mode
SCK10, SCK11
I/O
Input/output pins for the clock
RXD10, RXD11
Input
Input pins for received data
TXD10, TXD11
Output
Output pins for transmitted data
CTS10#, CTS11#
Input
Input pins for controlling the start of transmission and reception
RTS10#, RTS11#
Output
Output pins for controlling the start of transmission and
reception
SSCL10, SSCL11
I/O
Input/output pins for the I2C clock
SSDA10, SSDA11
I/O
Input/output pins for the I2C data
• Simple I2C mode
• Simple SPI mode
SCK10, SCK11
I/O
Input/output pins for the clock
SMISO10, SMISO11
I/O
Input/output pins for slave transmission of data
SMOSI10, SMOSI11
I/O
Input/output pins for master transmission of data
SS10#, SS11#
Input
Chip-select input pins
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RX671 Group
Table 1.4
1. Overview
Pin Functions (5/8)
Classifications
Pin Name
I/O
Description
Serial communications
interface (RSCI)
• Asynchronous mode/clock synchronous mode
SCK010, SCK011
I/O
Input/output pins for the clock
RXD010, RXD011
Input
Input pins for received data
TXD010, TXD011
Output
Output pins for transmitted data
CTS010#, CTS011#
Input
Input pins for controlling the start of transmission and reception
RTS010#, RTS011#
Output
Output pins for controlling the start of transmission and
reception
DE010, DE011
Output
DriveEnable output pins
SSCL010, SSCL011
I/O
Input/output pins for the I2C clock
SSDA010, SSDA011
I/O
Input/output pins for the I2C data
• Simple I2C mode
• Simple SPI mode
SCK010, SCK011
I/O
Input/output pins for the clock
SMISO010, SMISO011
I/O
Input/output pins for slave transmission of data
SMOSI010, SMOSI011
I/O
Input/output pins for master transmission of data
SS010#, SS011#
Input
Chip-select input pins
RXD010, RXD011
Input
Input pin for received data
TXD010, TXD011, TXDA011,
TXDB011
Output
Output pins for transmitted data
SCL0[FM+], SCL1, SCL2,
SCL2-DS
I/O
Input/output pins for clocks. Bus can be directly driven by the
N-channel open drain
SDA0[FM+], SDA1, SDA2,
SDA2-DS
I/O
Input/output pins for data. Bus can be directly driven by the
N-channel open drain
SCLHS0[FM+/HS]
I/O
Input/output pin for clocks. Bus can be directly driven by the
N-channel open drain
SDAHS0[FM+/HS]
I/O
Input/output pin for data. Bus can be directly driven by the
N-channel open drain
VCC_USB
Input
Power supply pin
VSS_USB
Input
Ground pin
USB0_DP, USB1_DP
I/O
Input or output USB transceiver D+ data.
USB0_DM, USB1_DM
I/O
Input or output USB transceiver D- data.
USB0_EXICEN,
USB1_EXICEN
Output
Connect to the OTG power IC.
USB0_ID, USB1_ID
Input
Connect to the OTG power IC.
USB0_VBUSEN,
USB1_VBUSEN
Output
USB VBUS power enable pins
USB0_OVRCURA/
USB0_OVRCURB,
USB1_OVRCURA/
USB1_OVRCURB
Input
USB overcurrent pins
USB0_VBUS, USB1_VBUS
Input
USB cable connection/disconnection detection input pins
CRX0, CRX1, CRX1-DS
Input
Input pins
CTX0, CTX1
Output
Output pins
• HBS support mode
I2C bus interface
Hi-speed I2C bus
interface (RIICHS)
USB 2.0 host/function
module
CAN module
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RX671 Group
Table 1.4
1. Overview
Pin Functions (6/8)
Classifications
Pin Name
I/O
Description
Serial peripheral interface
RSPCKA-A/RSPCKA-B/
RSPCKB-A/RSPCKB-B/
RSPCKC-A/RSPCKC-B
I/O
Clock input/output pins
MOSIA-A/MOSIA-B/
MOSIB-A/MOSIB-B/
MOSIC-A/MOSIC-B
I/O
Input or output data output from the master
MISOA-A/MISOA-B/
MISOB-A/MISOB-B/
MISOC-A/MISOC-B
I/O
Input or output data output from the slave
SSLA0-A/SSLA0-B/
SSLB0-A/SSLB0-B/
SSLC0-A
I/O
Input or output pins for slave selection
SSLA1-A/SSLA1-B/
SSLB1-A/SSLB1-B/
SSLC1-A,
SSLA2-A/SSLA2-B/
SSLB2-A/SSLB2-B/
SSLC2-A,
SSLA3-A/SSLA3-B/
SSLB3-A/SSLB3-B/
SSLC3-A
Output
Output pins for slave selection
RSPCK0-A/RSPCK0-B
I/O
Clock input/output pins
MOSI0-A/MOSI0-B
I/O
Input or output data output from the master
MISO0-A/MISO0-B
I/O
Input or output data output from the slave
SSL00-A/SSL00-B
I/O
Input or output pins for slave selection
SSL01-A/SSL01-B,
SSL02-A/SSL02-B,
SSL03-A/SSL03-B
Output
Output pins for slave selection
QSPCLK-A/QSPCLK-B
Output
Clock output pins
QSSL-A/QSSL-B
Output
Output pins for slave selection
QIO0-A/QIO0-B,
QIO1-A/QIO1-B,
QIO2-A/QIO2-B,
QIO3-A/QIO3-B
I/O
Data input/output pins
SSIBCK0
I/O
SSIE serial bit-clock pin
SSILRCK0
I/O
LR clock
SSITXD0
Output
Serial data output pin
SSIRXD0
Input
Serial data input pin
AUDIO_CLK
Input
External clock pin for audio (input for an oversampling clock)
SDHI_CLK-A/SDHI_CLK-B/
SDHI_CLK-C
Output
SD clock output pins
SDHI_CMD-A/SDHI_CMD-B/
SDHI_CMD-C
I/O
SD command output, response input signal pins
SDHI_D3-A/SDHI_D3-B/
SDHI_D3-C to SDHI_D0-A/
SDHI_D0-B/SDHI_D0-C
I/O
SD data bus pins
SDHI_CD
Input
SD card detection pin
Serial peripheral interface
(RSPIA)
Quad-SPI memory
interface
Serial sound interface
SD host interface
SDHI_WP
Input
SD write-protect signal
RTCOUT
Output
Output pin for 1-Hz/64-Hz clock
RTCIC0 to RTCIC2
Input
Time capture event input pins
Battery backup
TAMPI0 to TAMPI2
Input
Input pins for detecting tampering
Remote control signal
receiver (REMC)
PMC0-DS
Input
Input pin for external pulse signal
Realtime clock
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RX671 Group
Table 1.4
1. Overview
Pin Functions (7/8)
Classifications
Pin Name
I/O
Description
12-bit A/D converter
AN000 to AN007,
AN100 to AN111
Input
Input pins for the analog signals to be processed by the A/D
converter
ADTRG0#, ADTRG1#
Input
Input pins for the external trigger signals that start the A/D
conversion
ANEX0
Output
Extended analog output pin
ANEX1
Input
Extended analog input pin
Capacitive touch sensing
unit (CTSU)
Analog power supply
TS0 to TS16
I/O
Electrostatic capacitance measurement pins (touch pins).
TSCAP
—
Connect to the VSS via a decoupling capacitor (10 nF) for
stabilizing the internal voltage. The capacitor should be placed
close to the pin.
AVCC0*1
Input
Analog voltage supply pin for the 12-bit A/D converter (unit 0).
Connect this pin to a branch from the VCC power supply.
Connect the pin to AVSS0 via a 0.1-µF multilayer ceramic
capacitor. The capacitor should be placed close to the pin.
AVSS0*1
Input
Analog ground pin for the 12-bit A/D converter (unit 0). Connect
this pin to a branch from the VSS ground power supply.
Connect the pin to AVCC0 via a 0.1-µF multilayer ceramic
capacitor. The capacitor should be placed close to the pin.
VREFH0
Input
Analog reference voltage supply pin for the 12-bit A/D converter
(unit 0). Connect this pin to VCC if the 12-bit A/D converter is
not to be used.
VREFL0
Input
Analog reference ground pin for the 12-bit A/D converter (unit
0). Connect this pin to VSS if the 12-bit A/D converter is not to
be used.
AVCC1*1
Input
Analog voltage supply and reference voltage supply pin for the
12-bit A/D converter (unit 1). This pin also supplies the analog
voltage to the temperature sensor. Connect this pin to a branch
from the VCC power supply. Connect the pin to AVSS1 via a
0.1-µF multilayer ceramic capacitor. The capacitor should be
placed close to the pin.
AVSS1*1
Input
Analog voltage supply and reference voltage supply pin for the
12-bit A/D converter (unit 1). This pin also supplies the analog
ground voltage to the temperature sensor. Connect this pin to a
branch from the VSS ground power supply. Connect the pin to
AVCC1 via a 0.1-µF multilayer ceramic capacitor. The capacitor
should be placed close to the pin.
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RX671 Group
Table 1.4
1. Overview
Pin Functions (8/8)
Classifications
Pin Name
I/O
Description
I/O ports
P00 to P03, P05, P07
I/O
6-bit input/output pins
P12 to P17
I/O
6-bit input/output pins
P20 to P27
I/O
8-bit input/output pins
P30 to P37
I/O
8-bit input/output pins (P35: input pin)
P40 to P47
I/O
8-bit input/output pins
P50 to P56
I/O
7-bit input/output pins
P60 to P67
I/O
8-bit input/output pins
P70 to P77
I/O
8-bit input/output pins
P80 to P83, P86, P87
I/O
6-bit input/output pins
P90 to P93
I/O
4-bit input/output pins
PA0 to PA7
I/O
8-bit input/output pins
PB0 to PB7
I/O
8-bit input/output pins
PC0 to PC7
I/O
8-bit input/output pins
PD0 to PD7
I/O
8-bit input/output pins
PE0 to PE7
I/O
8-bit input/output pins
PF5
I/O
1-bit input/output pins
PH1, PH2
I/O
2-bit input/output pins
PJ3, PJ5
I/O
2-bit input/output pins
Note:
Note the following regarding pin names. For details, see section 1.6, List of Pin and Pin Functions.
- When a letter “-A”, “-B”, etc. to indicate group membership is appended to the pin name, each pin is recommended to use in
combination with the pins in the same group.
All RSPI, RSPIA, QSPIX, SDHI AC timings are measured in combination with the pins in the same group.
- When the pin functions have “-DS” appended to their names, they can also be used as triggers for release from deep software
standby.
- RIIC and RIICHS pin functions that have [FM+] appended to their names support fast-mode plus.
Note 1. When neither the 12-bit A/D converter nor temperature sensor is to be used, connect the AVCC0 and AVCC1 pins to VCC, and
the AVSS0 and AVSS1 pins to VSS.
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RX671 Group
1.5
1. Overview
Pin Assignments
1.5.1
145-Pin TFLGA (0.65-mm Pitch)
A
B
C
D
E
F
G
H
J
K
L
M
N
13
PE3
PE4
VSS
PE6
P67
PA2
USB1_
DP
USB1_
DM
PB1
PB5
VSS
VCC
P74
13
12
PE1
PE2
P70
PE5
P65
PA1
VSS_
USB
VCC_
USB
PB2
PB6
P73
PC1
P75
12
11
P62
P61
PE0
VCC
P66
PA4
PA6
PA7
PB4
PB7
PC2
PC0
PC3
11
10
VSS
VCC
P63
PE7
PA0
PA3
PA5
PB0
PB3
P76
PC4
P77
P82
10
9
PD6
PD4
PD7
P64
P80
PC5
P81
PC7
9
8
PD2
PD0
PD3
P60
VCC
P83
PC6
VSS
8
7
P92
P91
PD1
PD5
P51
P52
P50
P55
7
6
P90
P47
VSS
P93
P53
P56
VSS_
USB
PH1/
USB0_
DP
6
5
P45
P43
P46
VCC
P44
P54
P13
VCC_
USB
PH2/
USB0_
DM
5
4
P42
VREFL0
P41
P01
EMLE
VBATT
BSCANP
P35
P30
P15
P24
P12
P14
4
3
P40
P05
VREFH0
P03
PJ5
PJ3
MD/
FINED
VSS
P32
P31
P16
P86
P87
3
2
P07
AVCC0
P02
PF5
VCL
XCOUT
RES#
VCC
P33
P26
P23
P17
P20
2
1
AVSS0
AVCC1
AVSS1
P00
VSS
XCIN
P37/
XTAL
P36/
EXTAL
P34
P27
P25
P22
P21
1
A
B
C
D
E
F
G
H
J
K
L
M
N
INDEX
Note:
Figure 1.3
RX671 Group
PTLG0145JC-A
(0.65-mm pitch,
145-pin TFLGA)
(Upper Perspective View)
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.5, List of Pin and Pin Functions (0.65-mm Pitch, 145-Pin TFLGA).
Pin Assignment (0.65-mm Pitch, 145-Pin TFLGA)
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 27 of 178
RX671 Group
1.5.2
1. Overview
145-Pin TFLGA (0.50-mm Pitch)
A
B
C
D
E
F
G
H
J
K
L
M
N
13
PE3
PE4
VSS
PE6
P67
PA2
PA4
PA7
PB1
PB5
VSS
VCC
P74
13
12
PE1
PE2
P70
PE5
P65
PA1
VCC
PB0
PB2
PB6
P73
PC1
P75
12
11
P62
P61
PE0
VCC
P66
VSS
PA6
P71
PB4
PB7
PC2
PC0
PC3
11
10
VSS
VCC
P63
PE7
PA0
PA3
PA5
P72
PB3
P76
PC4
P77
P82
10
9
PD6
PD4
PD7
P64
P80
PC5
P81
PC7
9
8
PD2
PD0
PD3
P60
VCC
P83
PC6
VSS
8
7
P92
P91
PD1
PD5
P51
P52
P50
P55
7
6
P90
P47
VSS
P93
P53
P56
VSS_
USB
PH1/
USB0_
DP
6
5
P45
P43
P46
VCC
P44
P54
P13
VCC_
USB
PH2/
USB0_
DM
5
4
P42
VREFL0
P41
P01
EMLE
VBATT
BSCANP
P35
P30
P15
P24
P12
P14
4
3
P40
P05
VREFH0
P03
PJ5
PJ3
MD/
FINED
VSS
P32
P31
P16
P86
P87
3
2
P07
AVCC0
P02
PF5
VCL
XCOUT
RES#
VCC
P33
P26
P23
P17
P20
2
1
AVSS0
AVCC1
AVSS1
P00
VSS
XCIN
P37/
XTAL
P36/
EXTAL
P34
P27
P25
P22
P21
1
A
B
C
D
E
F
G
H
J
K
L
M
N
INDEX
Note:
Figure 1.4
RX671 Group
PTLG0145KB-A
(0.50-mm pitch,
145-pin TFLGA)
(Upper Perspective View)
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.6, List of Pin and Pin Functions (0.50-mm Pitch, 145-Pin TFLGA).
Pin Assignment (0.50-mm Pitch, 145-Pin TFLGA)
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 28 of 178
RX671 Group
PA4
VCC
PA5
PA6
PA7
PB0
P71
P72
PB1
PB2
PB3
PB4
PB5
PB6
PB7
P73
VSS
PC0
VCC
PC1
92
91
90
89
88
87
85
83
81
79
77
76
75
74
73
PA3
VSS
94
78
PA1
PA2
96
80
PA0
97
82
P66
P67
99
84
P65
100
86
PE7
101
93
PE6
102
95
P70
VCC
104
98
PE5
VSS
103
PE4
106
105
PE3
107
144-Pin LFQFP
108
1.5.3
1. Overview
PE2
109
72
P74
PE1
110
71
P75
PE0
111
70
PC2
P64
112
69
P76
P63
113
68
P62
114
67
P77
PC3
P61
VSS
115
66
PC4
116
65
P80
P60
117
64
P81
VCC
118
63
P82
PD7
119
62
PC5
PD6
120
61
PC6
PD5
121
60
PC7
PD4
122
59
PD3
123
58
VCC
P83
PD2
124
57
PD1
PD0
125
56
VSS
P50
55
P51
P93
127
54
P52
P92
128
53
P53
P91
129
52
P54
VSS
130
51
P55
P90
VCC
131
50
P56
132
49
VSS_USB
P47
133
48
P46
134
47
PH1/USB0_DP
PH2/USB0_DM
P45
135
46
VCC_USB
P44
136
45
P12
P43
137
44
P13
P42
138
43
P14
P41
VREFL0
139
42
P15
140
41
P86
P40
VREFH0
AVCC0
141
40
P16
142
39
143
38
P87
P17
P07
144
37
P20
Note:
Figure 1.5
13
15
16
17
18
19
20
21
22
23
24
25
27
28
29
30
31
33
34
35
36
PJ3
VCL
VBATT
MD/FINED
XCIN
XCOUT
RES#
P37/XTAL
VSS
P36/EXTAL
VCC
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
P23
P22
P21
32
12
VSS
26
11
PJ5
10
9
PF5
EMLE
5
AVSS1
P02
8
4
P03
7
3
AVCC1
P01
P00
2
P05
6
1
AVSS0
14
RX671 Group
PLQP0144KA-B
(144-pin LFQFP)
(Top view)
126
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.7, List of Pin and Pin Functions (144-Pin LFQFP).
Pin Assignment (144-Pin LFQFP)
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 29 of 178
RX671 Group
1.5.4
1. Overview
100-Pin TFLGA
RX671 Group
PTLG0100JB-A (100-pin TFLGA)
(Upper Perspective View)
INDEX
A
B
C
D
E
F
G
H
J
K
10
PE2
PE3
PE4
PA0
PA3
VSS
VCC
PB7
PC1
PC2
10
9
PE1
PD7
PE5
PA1
PA5
PA7
PB1
PB6
PC0
PC3
9
8
PE0
PD6
PD5
PE7
PA4
PB0
PB4
PC6
PC4
PC5
8
7
PD4
PD3
PD2
PE6
PA6
PB2
PB5
PC7
P50
P51
7
6
PD0
PD1
P47
P46
PA2
PB3
P52
P54
VCC_
USB
PH1/
USB0_
DP
6
5
P43
P44
P42
P45
P41
P12
P53
P55
VSS_
USB
PH2/
USB0_
DM
5
4
VREFL0
P40
VREFH0
VBATT
P34
P32
P27
P15
P13
P14
4
3
P07
AVCC0
PJ3
MD/
FINED
RES#
P35
P30
P16
P17
P20
3
2
AVCC1
AVSS0
AVSS1
XCOUT
VSS
VCC
P31
P25
P21
P22
2
1
P05
EMLE
VCL
XCIN
P37/
XTAL
P36/
EXTAL
P33
P26
P24
P23
1
A
B
C
D
E
F
G
H
J
K
Note:
Figure 1.6
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.8, List of Pin and Pin Functions (100-Pin TFLGA).
Pin Assignment (100-Pin TFLGA)
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 30 of 178
RX671 Group
PE3
PE4
PE5
PE6
PE7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
VSS
PB0
VCC
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PE2
76
50
PE1
77
49
PC2
PC3
PE0
78
48
PC4
PD7
79
47
PC5
PD6
80
46
PC6
PD5
81
45
PC7
PD4
82
44
P50
PD3
83
43
P51
PD2
84
42
P52
PD1
85
41
P53
PD0
86
40
P54
P47
87
39
P55
P46
88
38
VSS_USB
P45
89
37
PH1/USB0_DP
P44
90
36
PH2/USB0_DM
P43
91
35
VCC_USB
P42
92
34
P12
P41
93
33
P13
VREFL0
94
32
P14
P40
95
31
P15
VREFH0
96
30
P16
AVCC0
97
29
P17
P07
98
28
P20
AVSS0
99
27
P21
P05
100
26
P22
Note:
Figure 1.7
75
100-Pin LFQFP
14
15
16
17
18
19
20
21
22
23
24
25
VCC
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
P23
9
XCOUT
13
8
XCIN
P36/EXTAL
7
MD/FINED
12
6
VBATT
VSS
5
VCL
11
4
PJ3
P37/XTAL
3
AVSS1
10
2
RES#
1
EMLE
RX671 Group
PLQP0100KB-B
(100-pin LFQFP)
(Top view)
AVCC1
1.5.5
1. Overview
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.9, List of Pin and Pin Functions (100-Pin LFQFP).
Pin Assignment (100-Pin LFQFP)
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 31 of 178
RX671 Group
1.5.6
1. Overview
64-Pin TFBGA
RX671 Group
PTBG0064KB-A (64-pin TFBGA)
(Upper Perspective View)
INDEX
A
B
C
D
E
F
G
H
8
PE2
PE6
PE7
PA4
VSS
PB5
PC0
PC1
8
7
PE0
PE1
PA1
PA2
VCC
PB6
PC5
PC4
7
6
PD7
PD6
PD5
PA6
PA7
PB7
PC7
PC6
6
5
PD2
PD3
PD4
P43
BSCANP
P53
VSS_USB
PH1/
USB0_DP
5
4
VREFL0
P42
P41
P40
P13
P12
VCC_USB
PH2/
USB0_DM
4
3
VREFH0
AVCC0
MD/FINED
RES#
P34
P35
P30
P16
3
2
AVSS0
AVSS1
VBATT
XCOUT
VSS
VCC
P31
P17
2
1
AVCC1
EMLE
VCL
XCIN
P37/
XTAL
P36/
EXTAL
P27
P26
1
A
B
C
D
E
F
G
H
Note:
Figure 1.8
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.10, List of Pin and Pin Functions (64-Pin TFBGA).
Pin Assignment (64-Pin TFBGA)
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 32 of 178
RX671 Group
Note:
Figure 1.9
PE1
PE2
PE6
PE7
PA1
PA2
PA4
PA6
PA7
VSS
VCC
PB5
PB6
PB7
PC0
PC1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64-Pin LFQFP
PE0
49
32
PC4
PD7
50
31
PC5
PD6
51
30
PC6
PD5
52
29
PC7
PD4
53
28
P53
PD3
54
27
VSS_USB
PD2
55
26
PH1/USB0_DP
P43
56
25
PH2/USB0_DM
P42
57
24
VCC_USB
P41
58
23
P12
VREFL0
59
22
P13
P40
60
21
P16
VREFH0
61
20
P17
AVCC0
62
19
P27
AVSS0
63
18
P26
P05
64
17
P31
14
15
16
P35
P34
P30
9
RES#
13
8
XCOUT
VCC
7
XCIN
12
6
MD/FINED
P36/EXTAL
5
VBATT
11
4
VCL
VSS
3
AVSS1
10
2
P37/XTAL
1
EMLE
RX671 Group
PLQP0064KB-C
(64-pin LFQFP)
(Top view)
AVCC1
1.5.7
1. Overview
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.11, List of Pin and Pin Functions (64-Pin LFQFP).
Pin Assignment (64-Pin LFQFP)
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 33 of 178
RX671 Group
25 PB7
26 PB6
27 PB5
28 VCC
29 VSS
30 VCL
31 PA6
32 PA4
33 PA2
34 PA1
PD5 37
24 PC4
PD4 38
23 PC5
PD3 39
22 PC6
PD2 40
21 PC7
RX671 Group
PWQN0048KC-A
(48-pin HWQFN)
(Top view)
P43 41
P42 42
P41 43
VREFL0 44
P40 45
20 P53
19 VSS
18 VCC
17 P12
16 P13
P27 12
P30 11
P31 10
P34 9
P35 8
VCC 7
P36/EXTAL 6
13 P26
VSS 5
14 P17
AVSS0/AVSS1 48
P37/XTAL 4
15 P16
AVCC0/AVCC1 47
RES# 3
VREFH0 46
EMLE 1
Figure 1.10
35 PE7
36 PE6
48-Pin HWQFN
MD/FINED 2
1.5.8
1. Overview
Note:
It is recommended to connect the exposed die pad to VSS.
Note:
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see Table 1.12, List of Pin and Pin Functions (48-Pin HWQFN).
Pin Assignment (48-Pin HWQFN)
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 34 of 178
RX671 Group
1.6
1. Overview
List of Pin and Pin Functions
1.6.1
145-Pin TFLGA (0.65-mm Pitch)
Table 1.5
List of Pin and Pin Functions (0.65-mm Pitch, 145-Pin TFLGA) (1/8)
Pin No.
Timer
Power
Supply
145-Pin
Clock
TFLGA
(0.65-mm System
Control
pitch)
A1
I/O Port
Bus
EXDMAC
SDRAMC
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
Communication
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
Interrupt
A/D
IRQ15
ADTRG0#
AVSS0
A2
P07
A3
P40
IRQ8-DS
AN000
A4
P42
IRQ10-DS
AN002
A5
P45
IRQ13-DS
AN005
A6
P90
A16
TXD7/SMOSI7/
SSDA7
IRQ0
AN108
A7
P92
A18
POE4#
RXD7/SMISO7/
SSCL7
IRQ10
A8
PD2
D2[A2/D2]
MTIOC4D/
TIC2
CRX0/MISOC-A
SDHI_D2-B/
QIO2-B
IRQ2
AN105
A9
PD6
D6[A6/D6]
MTIC5V/
MTIOC8A/
POE4#
SSLC2-A
SDHI_D0-B/
QIO0-B
IRQ6
AN101
A11
P62
CS2#/
RAS#/
D1[A1/D1]
A12
PE1
D9[A9/D9]/
D1[A1/D1]
MTIOC4C/
MTIOC3B/
PO18
A13
PE3
D11[A11/
D11]/
D3[A3/D3]
MTIOC4B/
CTS12#/RTS12#/
PO26/POE8#/ SS12#
TOC3
A10
VSS
B1
AVCC1
B2
AVCC0
B3
IRQ2
TXD12/SMOSI12/
SSDA12/
TXDX12/SIOX12/
SSLB2-B
IRQ9
ANEX1
IRQ11
P05
IRQ13
B5
P43
IRQ11-DS
AN003
B6
P47
IRQ15-DS
AN007
B7
P91
B4
VREFL0
A17
SCK7
B8
PD0
D0[A0/D0]
POE4#
B9
PD4
D4[A4/D4]
MTIOC8B/
POE11#
B11
P61
CS1#/
SDCS#/
D0[A0/D0]
B12
PE2
D10[A10/
D10]/
D2[A2/D2]
B10
Others
(CTSU,
CLKOUT,
Tamper
detection)
SSLC0-A
IRQ9
SDHI_CMDB/
QSSL-B
IRQ0
AN107
IRQ4
AN103
VCC
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
IRQ1
MTIOC4A/
PO23/TIC3
RXD12/
SMISO12/
SSCL12/
RXDX12/
SSLB3-B
IRQ7-DS
Page 35 of 178
RX671 Group
1. Overview
Table 1.5
List of Pin and Pin Functions (0.65-mm Pitch, 145-Pin TFLGA) (2/8)
Pin No.
Timer
Power
Supply
145-Pin
Clock
TFLGA
(0.65-mm System
Control
pitch)
I/O Port
B13
PE4
C1
Interrupt
Bus
EXDMAC
SDRAMC
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
D12[A12/
D12]/
D4[A4/D4]
MTIOC4D/
MTIOC1A/
PO28
SSLB0-B
IRQ12
TMCI1
SCK6
IRQ10
AN109
A/D
P02
VREFH0
C4
P41
IRQ9-DS
AN001
C5
P46
IRQ14-DS
AN006
IRQ1
AN106
C6
VSS
C7
PD1
D1[A1/D1]
MTIOC4B/
POE0#
C8
PD3
D3[A3/D3]
MTIOC8D/
RSPCKC-A
POE8#/TOC2
SDHI_D3-B/
QIO3-B
IRQ3
AN104
C9
PD7
D7[A7/D7]
MTIC5U/
POE0#
SDHI_D1-B/
QIO1-B
IRQ7
AN100
C10
P63
CS3#/
CAS#/
D2[A2/D2]
C11
PE0
D8[A8/D8]/
D0[A0/D0]
P70
SDCLK
C12
C13
CTX0/MOSIC-A
SSLC3-A
IRQ3
MTIOC3D
SCK12/SSLB1-B
IRQ8
P00
D2
PF5
D3
P03
D4
P01
IRQ0
TMRI0
TXD6/SMOSI6/
SSDA6
IRQ8
AN111
IRQ4
IRQ11
TMCI0
RXD6/SMISO6/
SSCL6
IRQ9
IRQ11
AN110
VCC
D6
P93
A19
POE0#
CTS7#/RTS7#/
SS7#
D7
PD5
D5[A5/D5]
MTIC5W/
MTIOC8C/
POE10#
SSLC1-A
D8
P60
CS0#
IRQ0
D9
P64
CS4#/WE#/
D3[A3/D3]
IRQ4
D10
PE7
D15[A15/
D15]/
D7[A7/D7]
MTIOC6A/
TOC1
MISOB-B
D12
PE5
D13[A13/
D13]/
D5[A5/D5]
MTIOC4C/
MTIOC2B
RSPCKB-B
D13
PE6
D14[A14/
D14]/
D6[A6/D6]
MTIOC6C/
TIC1
MOSIB-B
D11
ANEX0
VSS
D1
D5
Others
(CTSU,
CLKOUT,
Tamper
detection)
AVSS1
C2
C3
Communication
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
SDHI_CLKB/
QSPCLK-B
SDHI_WP/
SDHI_D1-B/
QIO1-B
IRQ5
AN102
IRQ7
VCC
E1
VSS
E2
VCL
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
IRQ5
SDHI_CD/
SDHI_D0-B/
QIO0-B
IRQ6
Page 36 of 178
RX671 Group
1. Overview
Table 1.5
List of Pin and Pin Functions (0.65-mm Pitch, 145-Pin TFLGA) (3/8)
Pin No.
Timer
Power
Supply
145-Pin
Clock
TFLGA
(0.65-mm System
Control
pitch)
I/O Port
E3
PJ5
E4
Bus
EXDMAC
SDRAMC
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
POE8#
Communication
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
CTS2#/RTS2#/
SS2#
Interrupt
IRQ13
EMLE
E5
P44
E10
PA0
A0/BC0#
MTIOC4A/
MTIOC6D/
TIOCA0/
CACREF/
PO16
E11
P66
CS6#/
DQM0
MTIOC7D
E12
P65
CS5#/CKE
E13
P67
CS7#/
DQM1
MTIOC7C
PJ3
EDACK1
MTIOC3C
CTS6#/RTS6#/
CTS0#/RTS0#/
SS6#/SS0#
IRQ11
F10
PA3
A3
MTIOC0D/
MTCLKD/
TIOCD0/
TCLKB/PO19
RXD5/SMISO5/
SSCL5
IRQ6-DS
F11
PA4
A4
MTIC5U/
MTCLKA/
TIOCA1/
TMRI0/PO20
TXD5/SMOSI5/
SSDA5/SSLA0-B/
SSL00-B/TXD12/
SMOSI12/
SSDA12/
TXDX12/SIOX12
IRQ5-DS
F12
PA1
A1
MTIOC0B/
SCK5/SSLA2-B/
MTCLKC/
SSL02-B/SCK12
MTIOC7B/
TIOCB0/PO17
F13
PA2
A2
MTIOC7A/
PO18
F1
XCIN
F2
XCOUT
F3
EXCIN
F4
VBATT
G1
XTAL
G2
RES#
G3
MD/FINED
G4
BSCANP
IRQ12-DS
SSLA1-B/
SSL01-B
AN004
IRQ0
IRQ14
IRQ13
IRQ15
SDHI_CD
IRQ11
RXD5/SMISO5/
SDHI_WP
SSCL5/SSLA3-B/
SSL03-B/RXD12/
SMISO12/
SSCL12/RXDX12
IRQ10
P37
G10
PA5
A5
MTIOC6B/
RSPCKA-B/
TIOCB1/PO21 RSPCK0-B
IRQ5
G11
PA6
A6
MTIC5V/
MTCLKB/
TIOCA2/
TMCI3/PO22/
POE10#
IRQ14
G12
A/D
Others
(CTSU,
CLKOUT,
Tamper
detection)
CTS5#/RTS5#/
SS5#/MOSIA-B/
MOSI0-B/
CTS12#/RTS12#/
SS12#
VSS_USB
G13
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
USB1_DP
Page 37 of 178
RX671 Group
1. Overview
Table 1.5
List of Pin and Pin Functions (0.65-mm Pitch, 145-Pin TFLGA) (4/8)
Pin No.
Timer
Power
Supply
145-Pin
Clock
TFLGA
(0.65-mm System
Control
pitch)
I/O Port
H1
EXTAL
P36
H2
VCC
H3
VSS
H4
UPSEL
Bus
EXDMAC
SDRAMC
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
Communication
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
P35
Interrupt
NMI
H10
PB0
A8
MTIC5W/
RXD4/RXD6/
TIOCA3/PO24 SMISO4/
SMISO6/SSCL4/
SSCL6
IRQ12
H11
PA7
A7
TIOCB2/PO23 MISOA-B/
MISO0-B
IRQ7
H12
VCC_USB
H13
J1
A/D
Others
(CTSU,
CLKOUT,
Tamper
detection)
USB1_DM
TRST#
P34
IRQ4
TS0
MTIOC0D/
TIOCD0/
TMRI3/PO11/
POE4#/
POE11#
RXD6/RXD0/
SMISO6/
SMISO0/SSCL6/
SSCL0/CRX0
IRQ3-DS
TS1
J2
P33
J3
P32
MTIOC0C/
TIOCC0/
TMO3/PO10/
RTCOUT/
RTCIC2/
POE0#/
POE10#
TXD6/TXD0/
SMOSI6/
SMOSI0/SSDA6/
SSDA0/CTX0/
USB0_VBUSEN
IRQ2-DS
TAMPI2
P30
MTIOC4B/
TMRI3/PO8/
RTCIC0/
POE8#
RXD1/SMISO1/
SSCL1/MISOB-A
IRQ0-DS
TAMPI0
SCK4/SCK6/
PMC0-DS
IRQ3
J4
TDI
EDREQ1
MTIOC0A/
SCK6/SCK0
TMCI3/PO12/
POE10#
J10
PB3
A11
MTIOC0A/
MTIOC4A/
TIOCD3/
TCLKD/
TMO0/PO27/
POE11#
J11
PB4
A12
TIOCA4/PO28 CTS9#/RTS9#/
SS9#/SS11#/
CTS11#/RTS11#/
SS011#/
CTS011#/
RTS011#/DE011
IRQ4
J12
PB2
A10
TIOCC3/
CTS4#/RTS4#/
TCLKC/PO26 CTS6#/RTS6#/
SS4#/SS6#
IRQ2
J13
PB1
A9
MTIOC0C/
MTIOC4C/
TIOCB3/
TMCI0/PO25
TXD4/TXD6/
SMOSI4/
SMOSI6/SSDA4/
SSDA6
IRQ4-DS
P27
CS7#
MTIOC2B/
TMCI3/PO7
SCK1/RSPCKB-A
IRQ7
K1
TCK
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
TS2
Page 38 of 178
RX671 Group
1. Overview
Table 1.5
List of Pin and Pin Functions (0.65-mm Pitch, 145-Pin TFLGA) (5/8)
Pin No.
Timer
Power
Supply
145-Pin
Clock
TFLGA
(0.65-mm System
Control
pitch)
I/O Port
Bus
EXDMAC
SDRAMC
K2
TDO
P26
CS6#
K3
TMS
K4
K5
TRDATA2
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
Communication
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
Interrupt
A/D
Others
(CTSU,
CLKOUT,
Tamper
detection)
MTIOC2A/
TMO1/PO6
TXD1/CTS3#/
RTS3#/SMOSI1/
SS3#/SSDA1/
MOSIB-A
IRQ6
TS3
P31
MTIOC4D/
TMCI2/PO9/
RTCIC1
CTS1#/RTS1#/
SS1#/SSLB0-A
IRQ1-DS
TAMPI1
P15
MTIOC0B/
MTCLKB/
TIOCB2/
TCLKB/
TMCI2/PO13
RXD1/SCK3/
SMISO1/SSCL1/
CRX1-DS
IRQ5
TS10
MTIOC4B/
TMCI1
CTS2#/RTS2#/
SS2#/CTX1/
MOSIC-B
IRQ4
P54
ALE/
D1[A1/D1]/
EDACK0
K6
P53*1
BCLK
SSIRXD0/
PMC0-DS
IRQ3
K7
P51
WR1#/
BC1#/
WAIT#
SCK2/SSLB2-A
IRQ1
K8
VCC
K9
TRDATA0
P80
EDREQ0
MTIOC3B/
PO26
SCK10/RTS10#/ SDHI_WP/
SCK010/
QIO2-A
RTS010#/DE010/
USB1_EXICEN
IRQ8
K10
TRDATA6
P76
CS6#
PO22
SMISO11/
SSCL11/RXD11/
SMISO011/
SSCL011/
RXD011
IRQ14
K11
PB7
A15
MTIOC3B/
TXD9/SMOSI9/
TIOCB5/PO31 SSDA9/
SMOSI11/
SSDA11/TXD11/
SMOSI011/
SSDA011/
TXD011
IRQ15
K12
PB6
A14
MTIOC3D/
RXD9/SMISO9/
TIOCA5/PO30 SSCL9/SMISO11/
SSCL11/RXD11/
SMISO011/
SSCL011/
RXD011
IRQ6
K13
PB5
A13
MTIOC2A/
SCK9/SCK11/
MTIOC1B/
SCK011
TIOCB4/
TMRI1/PO29/
POE4#
IRQ13
L1
P25
CS5#/
EDACK1
MTIOC4C/
MTCLKB/
TIOCA4/PO5
RXD3/SMISO3/
SSCL3
SDHI_CD
IRQ5
L2
P23
EDACK0
MTIOC3D/
MTCLKD/
TIOCD3/PO3
TXD3/CTS0#/
RTS0#/SMOSI3/
SS0#/SSDA3/
SSIBCK0
SDHI_D1-C
IRQ3
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
SDHI_CMDA/
QSSL-A
TS12
ADTRG0# TS4/
CLKOUT
TS6
Page 39 of 178
RX671 Group
1. Overview
Table 1.5
List of Pin and Pin Functions (0.65-mm Pitch, 145-Pin TFLGA) (6/8)
Pin No.
Timer
Power
Supply
145-Pin
Clock
TFLGA
(0.65-mm System
Control
pitch)
I/O Port
L3
P16
L4
P24
L5
P13
L6
P56
EDACK1
L7
P52
RD#
P83
EDACK1
L9
PC5
L10
L11
L8
TRCLK
L12
TRDATA4
L13
VSS
M1
Bus
EXDMAC
SDRAMC
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
Communication
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
Others
(CTSU,
CLKOUT,
Tamper
detection)
Interrupt
A/D
IRQ6
ADTRG0#
MTIOC3C/
MTIOC3D/
TIOCB1/
TCLKC/
TMO2/PO14/
RTCOUT
TXD1/RXD3/
SMOSI1/
SMISO3/SSDA1/
SSCL3/SCL2-DS/
USB0_VBUS/
USB0_VBUSEN/
USB0_OVRCUR
B
MTIOC4A/
MTCLKA/
TIOCB4/
TMRI1/PO4
SCK3/
USB0_VBUSEN
MTIOC0B/
TIOCA5/
TMO3/PO13
TXD2/SMOSI2/
SSDA2/
SDA0[FM+]/
SDAHS0[FM+/
HS]
IRQ3
MTIOC3C/
TIOCA1
SCK7/
RSPCKC-B
IRQ6
RXD2/SMISO2/
SSCL2/SSLB3-A
IRQ2
MTIOC4C
SS10#/CTS10#/
SCK10/SS010#/
CTS010#/
SCK010
IRQ3
D3[A3/D3]/
A21/CS2#/
WAIT#
MTIOC3B/
MTCLKD/
TMRI2/PO29
SCK8/SCK10/
RSPCKA-A/
SSIBCK0/
SCK010/
RSPCK0-A
IRQ5
TS14
PC4
A20/CS3#
MTIOC3D/
MTCLKC/
TMCI1/PO25/
POE0#
SCK5/CTS8#/
SDHI_D1-A/
RTS8#/SS8#/
QIO1-A
SS10#/CTS10#/
RTS10#/
SSLA0-A/
AUDIO_CLK/
SS010#/
CTS010#/
RTS010#/DE010/
SSL00-A
IRQ12
TSCAP
PC2
A18
MTIOC4B/
TCLKA/PO21
RXD5/SMISO5/
SDHI_D3-A
SSCL5/SSLA3-A/
TXDB011/
SSL03-A
IRQ10
P73
CS3#
PO16
USB1_VBUS/
USB1_VBUSEN/
USB1_OVRCUR
B
IRQ8
P22
EDREQ0
MTIOC3B/
MTCLKC/
TIOCC3/
TMO0/PO2
SCK0/
USB0_OVRCUR
B/
AUDIO_CLK
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
CS4#/
EDREQ1
SDHI_WP
SDHI_D0-C
IRQ12
IRQ15
TS5
ADTRG1#
TS7
Page 40 of 178
RX671 Group
1. Overview
Table 1.5
List of Pin and Pin Functions (0.65-mm Pitch, 145-Pin TFLGA) (7/8)
Pin No.
Timer
Power
Supply
145-Pin
Clock
TFLGA
(0.65-mm System
Control
pitch)
I/O Port
M2
P17
MTIOC3A/
MTIOC3B/
MTIOC4B/
TIOCB0/
TCLKD/
TMO1/PO15/
POE8#
M3
P86
M4
P12
M5
VCC_USB
M6
VSS_USB
Bus
EXDMAC
SDRAMC
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
Communication
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
Others
(CTSU,
CLKOUT,
Tamper
detection)
Interrupt
A/D
SCK1/TXD3/
SDHI_D3-C
SMOSI3/SSDA3/
SDA2-DS/
SSITXD0
IRQ7
ADTRG1#
MTIOC4D/
TIOCA0
SMISO10/
SSCL10/RXD10/
SMISO010/
SSCL010/
RXD010
IRQ14
MTIC5U/
TMCI1
RXD2/SMISO2/
SSCL2/
SCL0[FM+]/
SCLHS0[FM+/
HS]
IRQ2
TXD2/SMOSI2/
SSDA2/SSLB1-A
IRQ0
IRQ13
M7
P50
WR0#/WR#
M8
PC6
D2[A2/D2]/
A22/CS1#
MTIOC3C/
MTCLKA/
TMCI2/TIC0/
PO30
RXD8/SMISO8/
SSCL8/
SMISO10/
SSCL10/RXD10/
MOSIA-A/
SSILRCK0/
SMISO010/
SSCL010/
RXD010/
MOSI0-A
TS13
M9
TRDATA1
P81
EDACK0
MTIOC3D/
PO27
SMISO10/
SSCL10/RXD10/
SMISO010/
SSCL010/
RXD010/
USB1_OVRCUR
B
SDHI_CD/
QIO3-A
IRQ9
M10
TRDATA7
P77
CS7#
PO23
SMOSI11/
SSDA11/TXD11/
SMOSI011/
SSDA011/
TXD011/
USB1_ID
SDHI_CLKA/
QSPCLK-A
IRQ7
M11
PC0
A16
MTIOC3C/
CTS5#/RTS5#/
TCLKC/PO17 SS5#/SSLA1-A/
RXD011/
SMISO011/
SSCL011/
SSL01-A
IRQ14
TS16
M12
PC1
A17
MTIOC3A/
SCK5/SSLA2-A/
TCLKD/PO18 TXD011/
SMOSI011/
SSDA011/
TXDA011/
SSL02-A
IRQ12
TS15
M13
VCC
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 41 of 178
RX671 Group
1. Overview
Table 1.5
List of Pin and Pin Functions (0.65-mm Pitch, 145-Pin TFLGA) (8/8)
Pin No.
Timer
Power
Supply
145-Pin
Clock
TFLGA
(0.65-mm System
Control
pitch)
I/O Port
N1
Communication
Others
(CTSU,
CLKOUT,
Tamper
detection)
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
P21
MTIOC1B/
MTIOC4A/
TIOCA3/
TMCI0/PO1
RXD0/SMISO0/
SSCL0/SCL1/
USB0_EXICEN/
SSILRCK0
SDHI_CLK-C IRQ9
TS8
N2
P20
MTIOC1A/
TIOCB3/
TMRI0/PO0
TXD0/SMOSI0/
SSDA0/SDA1/
USB0_ID/
SSIRXD0
SDHI_CMDC
IRQ8
TS9
N3
P87
MTIOC4C/
TIOCA2
SMOSI10/
SSDA10/TXD10/
SMOSI010/
SSDA010/
TXD010
SDHI_D2-C
IRQ15
N4
P14
MTIOC3A/
MTCLKA/
TIOCB5/
TCLKA/
TMRI2/PO15
CTS1#/RTS1#/
SS1#/CTX1/
USB0_OVRCUR
A
N5
PH2
TMRI0
USB0_DM
IRQ1
N6
PH1
TMO0
USB0_DP
IRQ0
N7
TRDATA3
N8
VSS
N9
N10
Bus
EXDMAC
SDRAMC
Interrupt
IRQ4
P55
D0[A0/D0]/
WAIT#/
EDREQ0
MTIOC4D/
TMO3
TXD7/SMOSI7/
SSDA7/CRX1/
MISOC-B
IRQ10
UB
PC7
A23/CS0#
MTIOC3A/
MTCLKB/
TMO2/TOC0/
PO31/
CACREF
TXD8/SMOSI8/
SSDA8/
SMOSI10/
SSDA10/TXD10/
MISOA-A/
SSITXD0/
SMOSI010/
SSDA010/
TXD010/
MISO0-A
IRQ14
TRSYNC
P82
EDREQ1
MTIOC4A/
PO28
SMOSI10/
SSDA10/TXD10/
SMOSI010/
SSDA010/
TXD010/
USB1_VBUSEN
IRQ2
PC3
A19
MTIOC4D/
TCLKB/PO24
TXD5/SMOSI5/
SSDA5/
PMC0-DS
SDHI_D0-A/
QIO0-A
IRQ11
N11
N12
TRSYNC1
P75
CS5#
PO20
SCK11/RTS11#/ SDHI_D2-A
SCK011/
RTS011#/DE011/
USB1_OVRCUR
A
IRQ13
N13
TRDATA5
P74
A20/CS4#
PO19
SS11#/CTS11#/
SS011#/
CTS011#/
USB1_VBUSEN
IRQ12
A/D
TS11
Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled.
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 42 of 178
RX671 Group
1.6.2
1. Overview
145-Pin TFLGA (0.50-mm Pitch)
Table 1.6
List of Pin and Pin Functions (0.50-mm Pitch, 145-Pin TFLGA) (1/8)
Pin No.
Timer
145-Pin
TFLGA
(0.50-mm
pitch)
Power
Supply
Clock
System
Control
A1
AVSS0
I/O Port
Bus
EXDMAC
SDRAMC
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
Communication
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
Interrupt
Others
(CTSU,
CLKOUT,
Tamper
detection)
A/D
A2
P07
IRQ15
ADTRG0#
A3
P40
IRQ8-DS
AN000
A4
P42
IRQ10-DS
AN002
A5
P45
IRQ13-DS
AN005
A6
P90
A16
TXD7/SMOSI7/
SSDA7
IRQ0
AN108
A7
P92
A18
POE4#
RXD7/SMISO7/
SSCL7
IRQ10
A8
PD2
D2[A2/D2]
MTIOC4D/
TIC2
CRX0/MISOC-A
SDHI_D2-B/
QIO2-B
IRQ2
AN105
A9
PD6
D6[A6/D6]
MTIC5V/
MTIOC8A/
POE4#
SSLC2-A
SDHI_D0-B/
QIO0-B
IRQ6
AN101
A11
P62
CS2#/
RAS#/
D1[A1/D1]
A12
PE1
D9[A9/D9]/
D1[A1/D1]
MTIOC4C/
MTIOC3B/
PO18
A13
PE3
D11[A11/
D11]/
D3[A3/D3]
MTIOC4B/
CTS12#/RTS12#/
PO26/POE8#/ SS12#
TOC3
A10
VSS
B1
AVCC1
B2
AVCC0
B3
IRQ2
TXD12/SMOSI12/
SSDA12/
TXDX12/SIOX12/
SSLB2-B
IRQ9
ANEX1
IRQ11
P05
IRQ13
B5
P43
IRQ11-DS
AN003
B6
P47
IRQ15-DS
AN007
B7
P91
B4
VREFL0
A17
SCK7
B8
PD0
D0[A0/D0]
POE4#
B9
PD4
D4[A4/D4]
MTIOC8B/
POE11#
B11
P61
CS1#/
SDCS#/
D0[A0/D0]
B12
PE2
D10[A10/
D10]/
D2[A2/D2]
B10
SSLC0-A
IRQ9
SDHI_CMDB/
QSSL-B
IRQ0
AN107
IRQ4
AN103
VCC
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
IRQ1
MTIOC4A/
PO23/TIC3
RXD12/
SMISO12/
SSCL12/
RXDX12/
SSLB3-B
IRQ7-DS
Page 43 of 178
RX671 Group
1. Overview
Table 1.6
List of Pin and Pin Functions (0.50-mm Pitch, 145-Pin TFLGA) (2/8)
Pin No.
Timer
Power
Supply
145-Pin
Clock
TFLGA
(0.50-mm System
Control
pitch)
I/O Port
B13
PE4
C1
Interrupt
Bus
EXDMAC
SDRAMC
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
D12[A12/
D12]/
D4[A4/D4]
MTIOC4D/
MTIOC1A/
PO28
SSLB0-B
IRQ12
TMCI1
SCK6
IRQ10
AN109
A/D
P02
VREFH0
C4
P41
IRQ9-DS
AN001
C5
P46
IRQ14-DS
AN006
IRQ1
AN106
C6
VSS
C7
PD1
D1[A1/D1]
MTIOC4B/
POE0#
C8
PD3
D3[A3/D3]
MTIOC8D/
RSPCKC-A
POE8#/TOC2
SDHI_D3-B/
QIO3-B
IRQ3
AN104
C9
PD7
D7[A7/D7]
MTIC5U/
POE0#
SDHI_D1-B/
QIO1-B
IRQ7
AN100
C10
P63
CS3#/
CAS#/
D2[A2/D2]
C11
PE0
D8[A8/D8]/
D0[A0/D0]
P70
SDCLK
C12
C13
CTX0/MOSIC-A
SSLC3-A
IRQ3
MTIOC3D
SCK12/SSLB1-B
IRQ8
P00
D2
PF5
D3
P03
D4
P01
IRQ0
TMRI0
TXD6/SMOSI6/
SSDA6
IRQ8
AN111
IRQ4
IRQ11
TMCI0
RXD6/SMISO6/
SSCL6
IRQ9
IRQ11
AN110
VCC
D6
P93
A19
POE0#
CTS7#/RTS7#/
SS7#
D7
PD5
D5[A5/D5]
MTIC5W/
MTIOC8C/
POE10#
SSLC1-A
D8
P60
CS0#
IRQ0
D9
P64
CS4#/WE#/
D3[A3/D3]
IRQ4
D10
PE7
D15[A15/
D15]/
D7[A7/D7]
MTIOC6A/
TOC1
MISOB-B
D12
PE5
D13[A13/
D13]/
D5[A5/D5]
MTIOC4C/
MTIOC2B
RSPCKB-B
D13
PE6
D14[A14/
D14]/
D6[A6/D6]
MTIOC6C/
TIC1
MOSIB-B
D11
ANEX0
VSS
D1
D5
Others
(CTSU,
CLKOUT,
Tamper
detection)
AVSS1
C2
C3
Communication
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
SDHI_CLKB/
QSPCLK-B
SDHI_WP/
SDHI_D1-B/
QIO1-B
IRQ5
AN102
IRQ7
VCC
E1
VSS
E2
VCL
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
IRQ5
SDHI_CD/
SDHI_D0-B/
QIO0-B
IRQ6
Page 44 of 178
RX671 Group
1. Overview
Table 1.6
List of Pin and Pin Functions (0.50-mm Pitch, 145-Pin TFLGA) (3/8)
Pin No.
Timer
Power
Supply
145-Pin
Clock
TFLGA
(0.50-mm System
Control
pitch)
I/O Port
E3
PJ5
E4
Bus
EXDMAC
SDRAMC
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
POE8#
Communication
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
CTS2#/RTS2#/
SS2#
Interrupt
IRQ13
EMLE
E5
P44
E10
PA0
A0/BC0#
MTIOC4A/
MTIOC6D/
TIOCA0/
CACREF/
PO16
E11
P66
CS6#/
DQM0
MTIOC7D
E12
P65
CS5#/CKE
E13
P67
CS7#/
DQM1
MTIOC7C
PJ3
EDACK1
MTIOC3C
CTS6#/RTS6#/
CTS0#/RTS0#/
SS6#/SS0#
IRQ11
PA3
A3
MTIOC0D/
MTCLKD/
TIOCD0/
TCLKB/PO19
RXD5/SMISO5/
SSCL5
IRQ6-DS
F12
PA1
A1
MTIOC0B/
SCK5/SSLA2-B/
MTCLKC/
SSL02-B/SCK12
MTIOC7B/
TIOCB0/PO17
F13
PA2
A2
MTIOC7A/
PO18
F1
XCIN
F2
XCOUT
F3
EXCIN
F4
VBATT
F10
F11
IRQ12-DS
SSLA1-B/
SSL01-B
XTAL
G2
RES#
G3
MD/FINED
G4
IRQ0
IRQ14
IRQ13
IRQ15
BSCANP
SDHI_CD
IRQ11
RXD5/SMISO5/
SDHI_WP
SSCL5/SSLA3-B/
SSL03-B/RXD12/
SMISO12/
SSCL12/RXDX12
IRQ10
P37
G10
PA5
A5
MTIOC6B/
RSPCKA-B/
TIOCB1/PO21 RSPCK0-B
IRQ5
G11
PA6
A6
MTIC5V/
MTCLKB/
TIOCA2/
TMCI3/PO22/
POE10#
CTS5#/RTS5#/
SS5#/MOSIA-B/
MOSI0-B/
CTS12#/RTS12#/
SS12#
IRQ14
PA4
A4
MTIC5U/
MTCLKA/
TIOCA1/
TMRI0/PO20
TXD5/SMOSI5/
SSDA5/SSLA0-B/
SSL00-B/TXD12/
SMOSI12/
SSDA12/
TXDX12/SIOX12
IRQ5-DS
G13
AN004
VSS
G1
G12
A/D
Others
(CTSU,
CLKOUT,
Tamper
detection)
VCC
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 45 of 178
RX671 Group
1. Overview
Table 1.6
List of Pin and Pin Functions (0.50-mm Pitch, 145-Pin TFLGA) (4/8)
Pin No.
Timer
Power
Supply
145-Pin
Clock
TFLGA
(0.50-mm System
Control
pitch)
I/O Port
H1
EXTAL
P36
H2
VCC
H3
VSS
H4
UPSEL
Bus
EXDMAC
SDRAMC
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
Communication
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
P35
Interrupt
A/D
Others
(CTSU,
CLKOUT,
Tamper
detection)
NMI
H10
P72
A19/CS2#
IRQ10
H11
P71
A18/CS1#
IRQ1
H12
PB0
A8
MTIC5W/
RXD4/RXD6/
TIOCA3/PO24 SMISO4/
SMISO6/SSCL4/
SSCL6
IRQ12
H13
PA7
A7
TIOCB2/PO23 MISOA-B/
MISO0-B
IRQ7
MTIOC0A/
SCK6/SCK0
TMCI3/PO12/
POE10#
IRQ4
TS0
MTIOC0D/
TIOCD0/
TMRI3/PO11/
POE4#/
POE11#
RXD6/RXD0/
SMISO6/
SMISO0/SSCL6/
SSCL0/CRX0
IRQ3-DS
TS1
J1
TRST#
P34
J2
P33
J3
P32
MTIOC0C/
TIOCC0/
TMO3/PO10/
RTCOUT/
RTCIC2/
POE0#/
POE10#
TXD6/TXD0/
SMOSI6/
SMOSI0/SSDA6/
SSDA0/CTX0/
USB0_VBUSEN
IRQ2-DS
TAMPI2
P30
MTIOC4B/
TMRI3/PO8/
RTCIC0/
POE8#
RXD1/SMISO1/
SSCL1/MISOB-A
IRQ0-DS
TAMPI0
SCK4/SCK6/
PMC0-DS
IRQ3
J4
TDI
EDREQ1
J10
PB3
A11
MTIOC0A/
MTIOC4A/
TIOCD3/
TCLKD/
TMO0/PO27/
POE11#
J11
PB4
A12
TIOCA4/PO28 CTS9#/RTS9#/
SS9#/SS11#/
CTS11#/RTS11#/
SS011#/
CTS011#/
RTS011#/DE011
IRQ4
J12
PB2
A10
TIOCC3/
CTS4#/RTS4#/
TCLKC/PO26 CTS6#/RTS6#/
SS4#/SS6#
IRQ2
J13
PB1
A9
MTIOC0C/
MTIOC4C/
TIOCB3/
TMCI0/PO25
TXD4/TXD6/
SMOSI4/
SMOSI6/SSDA4/
SSDA6
IRQ4-DS
P27
CS7#
MTIOC2B/
TMCI3/PO7
SCK1/RSPCKB-A
IRQ7
K1
TCK
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
TS2
Page 46 of 178
RX671 Group
1. Overview
Table 1.6
List of Pin and Pin Functions (0.50-mm Pitch, 145-Pin TFLGA) (5/8)
Pin No.
Timer
Power
Supply
145-Pin
Clock
TFLGA
(0.50-mm System
Control
pitch)
I/O Port
Bus
EXDMAC
SDRAMC
K2
TDO
P26
CS6#
K3
TMS
K4
K5
TRDATA2
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
Communication
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
Interrupt
A/D
Others
(CTSU,
CLKOUT,
Tamper
detection)
MTIOC2A/
TMO1/PO6
TXD1/CTS3#/
RTS3#/SMOSI1/
SS3#/SSDA1/
MOSIB-A
IRQ6
TS3
P31
MTIOC4D/
TMCI2/PO9/
RTCIC1
CTS1#/RTS1#/
SS1#/SSLB0-A
IRQ1-DS
TAMPI1
P15
MTIOC0B/
MTCLKB/
TIOCB2/
TCLKB/
TMCI2/PO13
RXD1/SCK3/
SMISO1/SSCL1/
CRX1-DS
IRQ5
TS10
MTIOC4B/
TMCI1
CTS2#/RTS2#/
SS2#/CTX1/
MOSIC-B
IRQ4
P54
ALE/
D1[A1/D1]/
EDACK0
K6
P53*1
BCLK
SSIRXD0/
PMC0-DS
IRQ3
K7
P51
WR1#/
BC1#/
WAIT#
SCK2/SSLB2-A
IRQ1
K8
VCC
K9
TRDATA0
P80
EDREQ0
MTIOC3B/
PO26
SCK10/RTS10#/ SDHI_WP/
SCK010/
QIO2-A
RTS010#/DE010
IRQ8
K10
TRDATA6
P76
CS6#
PO22
SMISO11/
SSCL11/RXD11/
SMISO011/
SSCL011/
RXD011
IRQ14
K11
PB7
A15
MTIOC3B/
TXD9/SMOSI9/
TIOCB5/PO31 SSDA9/
SMOSI11/
SSDA11/TXD11/
SMOSI011/
SSDA011/
TXD011
IRQ15
K12
PB6
A14
MTIOC3D/
RXD9/SMISO9/
TIOCA5/PO30 SSCL9/SMISO11/
SSCL11/RXD11/
SMISO011/
SSCL011/
RXD011
IRQ6
K13
PB5
A13
MTIOC2A/
SCK9/SCK11/
MTIOC1B/
SCK011
TIOCB4/
TMRI1/PO29/
POE4#
IRQ13
L1
P25
CS5#/
EDACK1
MTIOC4C/
MTCLKB/
TIOCA4/PO5
RXD3/SMISO3/
SSCL3
SDHI_CD
IRQ5
L2
P23
EDACK0
MTIOC3D/
MTCLKD/
TIOCD3/PO3
TXD3/CTS0#/
RTS0#/SMOSI3/
SS0#/SSDA3/
SSIBCK0
SDHI_D1-C
IRQ3
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
SDHI_CMDA/
QSSL-A
TS12
ADTRG0# TS4/
CLKOUT
TS6
Page 47 of 178
RX671 Group
1. Overview
Table 1.6
List of Pin and Pin Functions (0.50-mm Pitch, 145-Pin TFLGA) (6/8)
Pin No.
Timer
Power
Supply
145-Pin
Clock
TFLGA
(0.50-mm System
Control
pitch)
I/O Port
L3
P16
L4
P24
L5
P13
L6
P56
EDACK1
L7
P52
RD#
P83
EDACK1
L9
PC5
L10
L11
Bus
EXDMAC
SDRAMC
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
Communication
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
Others
(CTSU,
CLKOUT,
Tamper
detection)
Interrupt
A/D
IRQ6
ADTRG0#
MTIOC3C/
MTIOC3D/
TIOCB1/
TCLKC/
TMO2/PO14/
RTCOUT
TXD1/RXD3/
SMOSI1/
SMISO3/SSDA1/
SSCL3/SCL2-DS/
USB0_VBUS/
USB0_VBUSEN/
USB0_OVRCUR
B
MTIOC4A/
MTCLKA/
TIOCB4/
TMRI1/PO4
SCK3/
USB0_VBUSEN
MTIOC0B/
TIOCA5/
TMO3/PO13
TXD2/SMOSI2/
SSDA2/
SDA0[FM+]/
SDAHS0[FM+/
HS]
IRQ3
MTIOC3C/
TIOCA1
SCK7/
RSPCKC-B
IRQ6
RXD2/SMISO2/
SSCL2/SSLB3-A
IRQ2
MTIOC4C
SS10#/CTS10#/
SCK10/SS010#/
CTS010#/
SCK010
IRQ3
D3[A3/D3]/
A21/CS2#/
WAIT#
MTIOC3B/
MTCLKD/
TMRI2/PO29
SCK8/SCK10/
RSPCKA-A/
SSIBCK0/
SCK010/
RSPCK0-A
IRQ5
TS14
PC4
A20/CS3#
MTIOC3D/
MTCLKC/
TMCI1/PO25/
POE0#
SCK5/CTS8#/
SDHI_D1-A/
RTS8#/SS8#/
QIO1-A
SS10#/CTS10#/
RTS10#/
SSLA0-A/
AUDIO_CLK/
SS010#/
CTS010#/
RTS010#/DE010/
SSL00-A
IRQ12
TSCAP
PC2
A18
MTIOC4B/
TCLKA/PO21
RXD5/SMISO5/
SDHI_D3-A
SSCL5/SSLA3-A/
TXDB011/
SSL03-A
IRQ10
P73
CS3#
PO16
M1
P22
EDREQ0
MTIOC3B/
MTCLKC/
TIOCC3/
TMO0/PO2
SCK0/
USB0_OVRCUR
B/
AUDIO_CLK
M2
P17
MTIOC3A/
MTIOC3B/
MTIOC4B/
TIOCB0/
TCLKD/
TMO1/PO15/
POE8#
SCK1/TXD3/
SDHI_D3-C
SMOSI3/SSDA3/
SDA2-DS/
SSITXD0
L8
TRCLK
L12
TRDATA4
L13
VSS
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
CS4#/
EDREQ1
SDHI_WP
IRQ12
TS5
ADTRG1#
IRQ8
SDHI_D0-C
IRQ15
IRQ7
TS7
ADTRG1#
Page 48 of 178
RX671 Group
1. Overview
Table 1.6
List of Pin and Pin Functions (0.50-mm Pitch, 145-Pin TFLGA) (7/8)
Pin No.
Timer
Communication
Power
Supply
145-Pin
Clock
TFLGA
(0.50-mm System
Control
pitch)
I/O Port
M3
P86
MTIOC4D/
TIOCA0
SMISO10/
SSCL10/RXD10/
SMISO010/
SSCL010/
RXD010
IRQ14
M4
P12
MTIC5U/
TMCI1
RXD2/SMISO2/
SSCL2/
SCL0[FM+]/
SCLHS0[FM+/
HS]
IRQ2
TXD2/SMOSI2/
SSDA2/SSLB1-A
IRQ0
IRQ13
M5
VCC_USB
M6
VSS_USB
Bus
EXDMAC
SDRAMC
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
M7
P50
WR0#/WR#
M8
PC6
D2[A2/D2]/
A22/CS1#
MTIOC3C/
MTCLKA/
TMCI2/TIC0/
PO30
RXD8/SMISO8/
SSCL8/
SMISO10/
SSCL10/RXD10/
MOSIA-A/
SSILRCK0/
SMISO010/
SSCL010/
RXD010/
MOSI0-A
Interrupt
A/D
Others
(CTSU,
CLKOUT,
Tamper
detection)
TS13
M9
TRDATA1
P81
EDACK0
MTIOC3D/
PO27
SMISO10/
SSCL10/RXD10/
SMISO010/
SSCL010/
RXD010
SDHI_CD/
QIO3-A
IRQ9
M10
TRDATA7
P77
CS7#
PO23
SMOSI11/
SSDA11/TXD11/
SMOSI011/
SSDA011/
TXD011
SDHI_CLKA/
QSPCLK-A
IRQ7
M11
PC0
A16
MTIOC3C/
CTS5#/RTS5#/
TCLKC/PO17 SS5#/SSLA1-A/
RXD011/
SMISO011/
SSCL011/
SSL01-A
IRQ14
TS16
M12
PC1
A17
MTIOC3A/
SCK5/SSLA2-A/
TCLKD/PO18 TXD011/
SMOSI011/
SSDA011/
TXDA011/
SSL02-A
IRQ12
TS15
M13
VCC
N1
P21
MTIOC1B/
MTIOC4A/
TIOCA3/
TMCI0/PO1
RXD0/SMISO0/
SSCL0/SCL1/
USB0_EXICEN/
SSILRCK0
SDHI_CLK-C IRQ9
TS8
N2
P20
MTIOC1A/
TIOCB3/
TMRI0/PO0
TXD0/SMOSI0/
SSDA0/SDA1/
USB0_ID/
SSIRXD0
SDHI_CMDC
TS9
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
IRQ8
Page 49 of 178
RX671 Group
1. Overview
Table 1.6
List of Pin and Pin Functions (0.50-mm Pitch, 145-Pin TFLGA) (8/8)
Pin No.
Timer
Communication
Power
Supply
145-Pin
Clock
TFLGA
(0.50-mm System
Control
pitch)
I/O Port
N3
P87
MTIOC4C/
TIOCA2
SMOSI10/
SSDA10/TXD10/
SMOSI010/
SSDA010/
TXD010
N4
P14
MTIOC3A/
MTCLKA/
TIOCB5/
TCLKA/
TMRI2/PO15
CTS1#/RTS1#/
SS1#/CTX1/
USB0_OVRCUR
A
IRQ4
N5
PH2
TMRI0
USB0_DM
IRQ1
N6
PH1
TMO0
USB0_DP
IRQ0
N7
TRDATA3
N8
VSS
N9
N10
Bus
EXDMAC
SDRAMC
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
SDHI_D2-C
Interrupt
IRQ15
P55
D0[A0/D0]/
WAIT#/
EDREQ0
MTIOC4D/
TMO3
TXD7/SMOSI7/
SSDA7/CRX1/
MISOC-B
IRQ10
UB
PC7
A23/CS0#
MTIOC3A/
MTCLKB/
TMO2/TOC0/
PO31/
CACREF
TXD8/SMOSI8/
SSDA8/
SMOSI10/
SSDA10/TXD10/
MISOA-A/
SSITXD0/
SMOSI010/
SSDA010/
TXD010/
MISO0-A
IRQ14
TRSYNC
P82
EDREQ1
MTIOC4A/
PO28
SMOSI10/
SSDA10/TXD10/
SMOSI010/
SSDA010/
TXD010
IRQ2
PC3
A19
MTIOC4D/
TCLKB/PO24
TXD5/SMOSI5/
SSDA5/
PMC0-DS
SDHI_D0-A/
QIO0-A
IRQ11
SDHI_D2-A
IRQ13
N11
N12
TRSYNC1
P75
CS5#
PO20
SCK11/RTS11#/
SCK011/
RTS011#/DE011
N13
TRDATA5
P74
A20/CS4#
PO19
SS11#/CTS11#/
SS011#/CTS011#
A/D
Others
(CTSU,
CLKOUT,
Tamper
detection)
TS11
IRQ12
Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled.
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 50 of 178
RX671 Group
1.6.3
1. Overview
144-Pin LFQFP
Table 1.7
List of Pin and Pin Functions (144-Pin LFQFP) (1/8)
Pin No.
Timer
144-Pin
LFQFP
Power
Supply
Clock
System
Control
1
AVSS0
2
3
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
Interrupt
P05
IRQ13
P03
IRQ11
A/D
AVSS1
6
P02
TMCI1
SCK6
IRQ10
AN109
7
P01
TMCI0
RXD6/SMISO6/
SSCL6
IRQ9
AN110
8
P00
TMRI0
TXD6/SMOSI6/
SSDA6
IRQ8
AN111
9
PF5
10
Others
(CTSU,
CLKOUT,
Tamper
detection)
AVCC1
4
5
I/O Port
Bus
EXDMAC
SDRAMC
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
Communication
IRQ4
EMLE
11
PJ5
12
VSS
13
EXCIN
14
VCL
15
VBATT
16
MD/FINED
17
XCIN
18
XCOUT
19
RES#
PJ3
20
XTAL
21
VSS
22
EXTAL
23
VCC
24
UPSEL
P35
25
TRST#
P34
EDACK1
POE8#
CTS2#/RTS2#/
SS2#
IRQ13
MTIOC3C
CTS6#/RTS6#/
CTS0#/RTS0#/
SS6#/SS0#
IRQ11
P37
P36
26
P33
27
P32
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
NMI
EDREQ1
MTIOC0A/
SCK6/SCK0
TMCI3/PO12/
POE10#
IRQ4
TS0
MTIOC0D/
TIOCD0/
TMRI3/PO11/
POE4#/
POE11#
RXD6/RXD0/
SMISO6/
SMISO0/SSCL6/
SSCL0/CRX0
IRQ3-DS
TS1
MTIOC0C/
TIOCC0/
TMO3/PO10/
RTCOUT/
RTCIC2/
POE0#/
POE10#
TXD6/TXD0/
SMOSI6/
SMOSI0/SSDA6/
SSDA0/CTX0/
USB0_VBUSEN
IRQ2-DS
TAMPI2
Page 51 of 178
RX671 Group
Table 1.7
1. Overview
List of Pin and Pin Functions (144-Pin LFQFP) (2/8)
Pin No.
Timer
Communication
144-Pin
LFQFP
Power
Supply
Clock
System
Control
I/O Port
28
TMS
P31
MTIOC4D/
TMCI2/PO9/
RTCIC1
CTS1#/RTS1#/
SS1#/SSLB0-A
IRQ1-DS
TAMPI1
29
TDI
P30
MTIOC4B/
TMRI3/PO8/
RTCIC0/
POE8#
RXD1/SMISO1/
SSCL1/MISOB-A
IRQ0-DS
TAMPI0
30
TCK
P27
CS7#
MTIOC2B/
TMCI3/PO7
SCK1/RSPCKB-A
IRQ7
TS2
31
TDO
P26
CS6#
MTIOC2A/
TMO1/PO6
TXD1/CTS3#/
RTS3#/SMOSI1/
SS3#/SSDA1/
MOSIB-A
IRQ6
TS3
32
P25
CS5#/
EDACK1
MTIOC4C/
MTCLKB/
TIOCA4/PO5
RXD3/SMISO3/
SSCL3
SDHI_CD
IRQ5
33
P24
CS4#/
EDREQ1
MTIOC4A/
MTCLKA/
TIOCB4/
TMRI1/PO4
SCK3/
USB0_VBUSEN
SDHI_WP
IRQ12
TS5
34
P23
EDACK0
MTIOC3D/
MTCLKD/
TIOCD3/PO3
TXD3/CTS0#/
RTS0#/SMOSI3/
SS0#/SSDA3/
SSIBCK0
SDHI_D1-C
IRQ3
TS6
35
P22
EDREQ0
MTIOC3B/
MTCLKC/
TIOCC3/
TMO0/PO2
SCK0/
USB0_OVRCUR
B/
AUDIO_CLK
SDHI_D0-C
IRQ15
TS7
36
P21
MTIOC1B/
MTIOC4A/
TIOCA3/
TMCI0/PO1
RXD0/SMISO0/
SSCL0/SCL1/
USB0_EXICEN/
SSILRCK0
SDHI_CLK-C IRQ9
TS8
37
P20
MTIOC1A/
TIOCB3/
TMRI0/PO0
TXD0/SMOSI0/
SSDA0/SDA1/
USB0_ID/
SSIRXD0
SDHI_CMDC
IRQ8
TS9
38
P17
MTIOC3A/
MTIOC3B/
MTIOC4B/
TIOCB0/
TCLKD/
TMO1/PO15/
POE8#
SCK1/TXD3/
SDHI_D3-C
SMOSI3/SSDA3/
SDA2-DS/
SSITXD0
IRQ7
39
P87
MTIOC4C/
TIOCA2
SMOSI10/
SSDA10/TXD10/
SMOSI010/
SSDA010/
TXD010
IRQ15
40
P16
MTIOC3C/
MTIOC3D/
TIOCB1/
TCLKC/
TMO2/PO14/
RTCOUT
TXD1/RXD3/
SMOSI1/
SMISO3/SSDA1/
SSCL3/SCL2-DS/
USB0_VBUS/
USB0_VBUSEN/
USB0_OVRCUR
B
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Bus
EXDMAC
SDRAMC
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
SDHI_D2-C
Interrupt
IRQ6
Others
(CTSU,
CLKOUT,
Tamper
detection)
A/D
ADTRG0# TS4/
CLKOUT
ADTRG1#
ADTRG0#
Page 52 of 178
RX671 Group
Table 1.7
1. Overview
List of Pin and Pin Functions (144-Pin LFQFP) (3/8)
Pin No.
144-Pin
LFQFP
Timer
Power
Supply
Clock
System
Control
I/O Port
Bus
EXDMAC
SDRAMC
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
Communication
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
Interrupt
Others
(CTSU,
CLKOUT,
Tamper
detection)
A/D
41
P86
MTIOC4D/
TIOCA0
SMISO10/
SSCL10/RXD10/
SMISO010/
SSCL010/
RXD010
IRQ14
42
P15
MTIOC0B/
MTCLKB/
TIOCB2/
TCLKB/
TMCI2/PO13
RXD1/SCK3/
SMISO1/SSCL1/
CRX1-DS
IRQ5
TS10
43
P14
MTIOC3A/
MTCLKA/
TIOCB5/
TCLKA/
TMRI2/PO15
CTS1#/RTS1#/
SS1#/CTX1/
USB0_OVRCUR
A
IRQ4
TS11
44
P13
MTIOC0B/
TIOCA5/
TMO3/PO13
TXD2/SMOSI2/
SSDA2/
SDA0[FM+]/
SDAHS0[FM+/
HS]
IRQ3
45
P12
MTIC5U/
TMCI1
RXD2/SMISO2/
SSCL2/
SCL0[FM+]/
SCLHS0[FM+/
HS]
IRQ2
47
PH2
TMRI0
USB0_DM
IRQ1
48
PH1
TMO0
USB0_DP
IRQ0
46
49
ADTRG1#
VCC_USB
VSS_USB
50
P56
EDACK1
MTIOC3C/
TIOCA1
SCK7/
RSPCKC-B
IRQ6
51
TRDATA3
P55
D0[A0/D0]/
WAIT#/
EDREQ0
MTIOC4D/
TMO3
TXD7/SMOSI7/
SSDA7/CRX1/
MISOC-B
IRQ10
52
TRDATA2
P54
ALE/
D1[A1/D1]/
EDACK0
MTIOC4B/
TMCI1
CTS2#/RTS2#/
SS2#/CTX1/
MOSIC-B
IRQ4
53
P53*1
BCLK
SSIRXD0/
PMC0-DS
IRQ3
54
P52
RD#
RXD2/SMISO2/
SSCL2/SSLB3-A
IRQ2
55
P51
WR1#/
BC1#/
WAIT#
SCK2/SSLB2-A
IRQ1
56
P50
WR0#/WR#
TXD2/SMOSI2/
SSDA2/SSLB1-A
IRQ0
P83
EDACK1
SS10#/CTS10#/
SCK10/SS010#/
CTS010#/
SCK010
IRQ3
57
VSS
58
TRCLK
59
VCC
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
MTIOC4C
TS12
Page 53 of 178
RX671 Group
Table 1.7
1. Overview
List of Pin and Pin Functions (144-Pin LFQFP) (4/8)
Pin No.
Timer
Communication
144-Pin
LFQFP
Power
Supply
Clock
System
Control
I/O Port
Bus
EXDMAC
SDRAMC
60
UB
PC7
A23/CS0#
MTIOC3A/
MTCLKB/
TMO2/TOC0/
PO31/
CACREF
TXD8/SMOSI8/
SSDA8/
SMOSI10/
SSDA10/TXD10/
MISOA-A/
SSITXD0/
SMOSI010/
SSDA010/
TXD010/
MISO0-A
IRQ14
61
PC6
D2[A2/D2]/
A22/CS1#
MTIOC3C/
MTCLKA/
TMCI2/TIC0/
PO30
RXD8/SMISO8/
SSCL8/
SMISO10/
SSCL10/RXD10/
MOSIA-A/
SSILRCK0/
SMISO010/
SSCL010/
RXD010/
MOSI0-A
IRQ13
TS13
62
PC5
D3[A3/D3]/
A21/CS2#/
WAIT#
MTIOC3B/
MTCLKD/
TMRI2/PO29
SCK8/SCK10/
RSPCKA-A/
SSIBCK0/
SCK010/
RSPCK0-A
IRQ5
TS14
IRQ2
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
Interrupt
63
TRSYNC
P82
EDREQ1
MTIOC4A/
PO28
SMOSI10/
SSDA10/TXD10/
SMOSI010/
SSDA010/
TXD010
64
TRDATA1
P81
EDACK0
MTIOC3D/
PO27
SMISO10/
SSCL10/RXD10/
SMISO010/
SSCL010/
RXD010
SDHI_CD/
QIO3-A
IRQ9
65
TRDATA0
P80
EDREQ0
MTIOC3B/
PO26
SCK10/RTS10#/ SDHI_WP/
SCK010/
QIO2-A
RTS010#/DE010
IRQ8
66
PC4
A20/CS3#
MTIOC3D/
MTCLKC/
TMCI1/PO25/
POE0#
SCK5/CTS8#/
SDHI_D1-A/
RTS8#/SS8#/
QIO1-A
SS10#/CTS10#/
RTS10#/
SSLA0-A/
AUDIO_CLK/
SS010#/
CTS010#/
RTS010#/DE010/
SSL00-A
IRQ12
67
PC3
A19
MTIOC4D/
TCLKB/PO24
TXD5/SMOSI5/
SSDA5/
PMC0-DS
SDHI_D0-A/
QIO0-A
IRQ11
P77
CS7#
PO23
SMOSI11/
SSDA11/TXD11/
SMOSI011/
SSDA011/
TXD011
SDHI_CLKA/
QSPCLK-A
IRQ7
68
TRDATA7
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
A/D
Others
(CTSU,
CLKOUT,
Tamper
detection)
TSCAP
Page 54 of 178
RX671 Group
Table 1.7
1. Overview
List of Pin and Pin Functions (144-Pin LFQFP) (5/8)
Pin No.
Timer
144-Pin
LFQFP
Power
Supply
Clock
System
Control
69
TRDATA6
70
Communication
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
I/O Port
Bus
EXDMAC
SDRAMC
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
P76
CS6#
PO22
SMISO11/
SSCL11/RXD11/
SMISO011/
SSCL011/
RXD011
PC2
A18
MTIOC4B/
TCLKA/PO21
RXD5/SMISO5/
SDHI_D3-A
SSCL5/SSLA3-A/
TXDB011/
SSL03-A
IRQ10
IRQ13
SDHI_CMDA/
QSSL-A
A/D
IRQ14
71
TRSYNC1
P75
CS5#
PO20
SCK11/RTS11#/
SCK011/
RTS011#/DE011
72
TRDATA5
P74
A20/CS4#
PO19
SS11#/CTS11#/
SS011#/CTS011#
PC1
A17
MTIOC3A/
SCK5/SSLA2-A/
TCLKD/PO18 TXD011/
SMOSI011/
SSDA011/
TXDA011/
SSL02-A
IRQ12
TS15
PC0
A16
MTIOC3C/
CTS5#/RTS5#/
TCLKC/PO17 SS5#/SSLA1-A/
RXD011/
SMISO011/
SSCL011/
SSL01-A
IRQ14
TS16
73
74
SDHI_D2-A
Interrupt
Others
(CTSU,
CLKOUT,
Tamper
detection)
IRQ12
VCC
75
76
VSS
77
TRDATA4
P73
CS3#
PO16
IRQ8
78
PB7
A15
MTIOC3B/
TXD9/SMOSI9/
TIOCB5/PO31 SSDA9/
SMOSI11/
SSDA11/TXD11/
SMOSI011/
SSDA011/
TXD011
IRQ15
79
PB6
A14
MTIOC3D/
RXD9/SMISO9/
TIOCA5/PO30 SSCL9/SMISO11/
SSCL11/RXD11/
SMISO011/
SSCL011/
RXD011
IRQ6
80
PB5
A13
SCK9/SCK11/
MTIOC2A/
SCK011
MTIOC1B/
TIOCB4/
TMRI1/PO29/
POE4#
IRQ13
81
PB4
A12
TIOCA4/PO28 CTS9#/RTS9#/
SS9#/SS11#/
CTS11#/RTS11#/
SS011#/
CTS011#/
RTS011#/DE011
IRQ4
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 55 of 178
RX671 Group
Table 1.7
1. Overview
List of Pin and Pin Functions (144-Pin LFQFP) (6/8)
Pin No.
Timer
Power
Supply
Clock
System
Control
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
Communication
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
I/O Port
Bus
EXDMAC
SDRAMC
82
PB3
A11
MTIOC0A/
MTIOC4A/
TIOCD3/
TCLKD/
TMO0/PO27/
POE11#
83
PB2
A10
TIOCC3/
CTS4#/RTS4#/
TCLKC/PO26 CTS6#/RTS6#/
SS4#/SS6#
IRQ2
84
PB1
A9
MTIOC0C/
MTIOC4C/
TIOCB3/
TMCI0/PO25
IRQ4-DS
85
P72
A19/CS2#
IRQ10
86
P71
A18/CS1#
IRQ1
87
PB0
A8
MTIC5W/
RXD4/RXD6/
TIOCA3/PO24 SMISO4/
SMISO6/SSCL4/
SSCL6
IRQ12
88
PA7
A7
TIOCB2/PO23 MISOA-B/
MISO0-B
IRQ7
89
PA6
A6
MTIC5V/
MTCLKB/
TIOCA2/
TMCI3/PO22/
POE10#
IRQ14
90
PA5
A5
MTIOC6B/
RSPCKA-B/
TIOCB1/PO21 RSPCK0-B
IRQ5
PA4
A4
MTIC5U/
MTCLKA/
TIOCA1/
TMRI0/PO20
TXD5/SMOSI5/
SSDA5/SSLA0-B/
SSL00-B/TXD12/
SMOSI12/
SSDA12/
TXDX12/SIOX12
IRQ5-DS
94
PA3
A3
MTIOC0D/
MTCLKD/
TIOCD0/
TCLKB/PO19
RXD5/SMISO5/
SSCL5
IRQ6-DS
95
PA2
A2
MTIOC7A/
PO18
SDHI_WP
RXD5/SMISO5/
SSCL5/SSLA3-B/
SSL03-B/RXD12/
SMISO12/
SSCL12/RXDX12
IRQ10
96
PA1
A1
MTIOC0B/
SCK5/SSLA2-B/
MTCLKC/
SSL02-B/SCK12
MTIOC7B/
TIOCB0/PO17
97
PA0
A0/BC0#
MTIOC4A/
MTIOC6D/
TIOCA0/
CACREF/
PO16
144-Pin
LFQFP
91
A/D
IRQ3
TXD4/TXD6/
SMOSI4/
SMOSI6/SSDA4/
SSDA6
CTS5#/RTS5#/
SS5#/MOSIA-B/
MOSI0-B/
CTS12#/RTS12#/
SS12#
VCC
92
93
SCK4/SCK6/
PMC0-DS
Interrupt
Others
(CTSU,
CLKOUT,
Tamper
detection)
VSS
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
SSLA1-B/
SSL01-B
SDHI_CD
IRQ11
IRQ0
Page 56 of 178
RX671 Group
Table 1.7
1. Overview
List of Pin and Pin Functions (144-Pin LFQFP) (7/8)
Pin No.
144-Pin
LFQFP
Timer
Power
Supply
Clock
System
Control
I/O Port
Bus
EXDMAC
SDRAMC
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
Communication
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
Interrupt
A/D
98
P67
CS7#/
DQM1
MTIOC7C
IRQ15
99
P66
CS6#/
DQM0
MTIOC7D
IRQ14
100
P65
CS5#/CKE
101
PE7
D15[A15/
D15]/
D7[A7/D7]
MTIOC6A/
TOC1
MISOB-B
SDHI_WP/
SDHI_D1-B/
QIO1-B
IRQ7
102
PE6
D14[A14/
D14]/
D6[A6/D6]
MTIOC6C/
TIC1
MOSIB-B
SDHI_CD/
SDHI_D0-B/
QIO0-B
IRQ6
P70
SDCLK
106
PE5
D13[A13/
D13]/
D5[A5/D5]
MTIOC4C/
MTIOC2B
RSPCKB-B
IRQ5
107
PE4
D12[A12/
D12]/
D4[A4/D4]
MTIOC4D/
MTIOC1A/
PO28
SSLB0-B
IRQ12
108
PE3
D11[A11/
D11]/
D3[A3/D3]
MTIOC4B/
CTS12#/RTS12#/
PO26/POE8#/ SS12#
TOC3
IRQ11
109
PE2
D10[A10/
D10]/
D2[A2/D2]
MTIOC4A/
PO23/TIC3
RXD12/
SMISO12/
SSCL12/
RXDX12/
SSLB3-B
IRQ7-DS
110
PE1
D9[A9/D9]/
D1[A1/D1]
MTIOC4C/
MTIOC3B/
PO18
TXD12/SMOSI12/
SSDA12/
TXDX12/SIOX12/
SSLB2-B
IRQ9
ANEX1
111
PE0
D8[A8/D8]/
D0[A0/D0]
MTIOC3D
SCK12/SSLB1-B
IRQ8
ANEX0
112
P64
CS4#/WE#/
D3[A3/D3]
IRQ4
113
P63
CS3#/
CAS#/
D2[A2/D2]
IRQ3
114
P62
CS2#/
RAS#/
D1[A1/D1]
IRQ2
115
P61
CS1#/
SDCS#/
D0[A0/D0]
IRQ1
P60
CS0#
IRQ0
119
PD7
D7[A7/D7]
MTIC5U/
POE0#
SSLC3-A
SDHI_D1-B/
QIO1-B
IRQ7
AN100
120
PD6
D6[A6/D6]
MTIC5V/
MTIOC8A/
POE4#
SSLC2-A
SDHI_D0-B/
QIO0-B
IRQ6
AN101
103
116
IRQ0
VSS
VSS
117
118
IRQ13
VCC
104
105
Others
(CTSU,
CLKOUT,
Tamper
detection)
VCC
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 57 of 178
RX671 Group
Table 1.7
1. Overview
List of Pin and Pin Functions (144-Pin LFQFP) (8/8)
Pin No.
Timer
Power
Supply
Clock
System
Control
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
Communication
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
Interrupt
A/D
I/O Port
Bus
EXDMAC
SDRAMC
121
PD5
D5[A5/D5]
MTIC5W/
MTIOC8C/
POE10#
SSLC1-A
SDHI_CLKB/
QSPCLK-B
IRQ5
AN102
122
PD4
D4[A4/D4]
MTIOC8B/
POE11#
SSLC0-A
SDHI_CMDB/
QSSL-B
IRQ4
AN103
123
PD3
D3[A3/D3]
MTIOC8D/
RSPCKC-A
POE8#/TOC2
SDHI_D3-B/
QIO3-B
IRQ3
AN104
124
PD2
D2[A2/D2]
MTIOC4D/
TIC2
CRX0/MISOC-A
SDHI_D2-B/
QIO2-B
IRQ2
AN105
125
PD1
D1[A1/D1]
MTIOC4B/
POE0#
CTX0/MOSIC-A
IRQ1
AN106
126
PD0
D0[A0/D0]
POE4#
IRQ0
AN107
127
P93
A19
POE0#
CTS7#/RTS7#/
SS7#
IRQ11
128
P92
A18
POE4#
RXD7/SMISO7/
SSCL7
IRQ10
P91
A17
SCK7
IRQ9
P90
A16
TXD7/SMOSI7/
SSDA7
IRQ0
AN108
144-Pin
LFQFP
129
130
VSS
131
132
Others
(CTSU,
CLKOUT,
Tamper
detection)
VCC
133
P47
IRQ15-DS
AN007
134
P46
IRQ14-DS
AN006
135
P45
IRQ13-DS
AN005
136
P44
IRQ12-DS
AN004
137
P43
IRQ11-DS
AN003
138
P42
IRQ10-DS
AN002
139
P41
IRQ9-DS
AN001
P40
IRQ8-DS
AN000
P07
IRQ15
ADTRG0#
140
VREFL0
141
142
VREFH0
143
AVCC0
144
Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled.
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 58 of 178
RX671 Group
1.6.4
1. Overview
100-Pin TFLGA
Table 1.8
List of Pin and Pin Functions (100-Pin TFLGA) (1/6)
Pin No.
100-Pin
TFLGA
Timer
Power
Supply
Clock
System
Control
A1
I/O Port
Bus
EXDMAC
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
Communication
(SCI, RSCI, RSPI,
RSPIA, RIIC,
RIICHS, CAN,
USB, SSIE,
(QSPIX,
REMC)
SDHI)
Interrupt
A/D
P05
IRQ13
P07
IRQ15
A5
P43
IRQ11-DS AN003
A6
PD0
D0[A0/D0]
POE4#
A7
PD4
D4[A4/D4]
MTIOC8B/
POE11#
SSLC0-A
A8
PE0
D8[A8/D8]/
D0[A0/D0]
MTIOC3D
A9
PE1
D9[A9/D9]/
D1[A1/D1]
A10
PE2
D10[A10/
D10]/
D2[A2/D2]
A2
AVCC1
A3
A4
B1
Others
(CTSU,
CLKOUT,
Tamper
detection)
ADTRG0#
VREFL0
IRQ0
AN107
IRQ4
AN103
SCK12/SSLB1-B
IRQ8
ANEX0
MTIOC4C/
MTIOC3B/
PO18
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/SSLB2-B
IRQ9
ANEX1
MTIOC4A/
PO23/TIC3
RXD12/SMISO12/
SSCL12/RXDX12/
SSLB3-B
IRQ7-DS
SDHI_CMDB/
QSSL-B
EMLE
B2
AVSS0
B3
AVCC0
B4
P40
IRQ8-DS
B5
P44
IRQ12-DS AN004
B6
PD1
D1[A1/D1]
MTIOC4B/
POE0#
B7
PD3
D3[A3/D3]
MTIOC8D/
RSPCKC-A
POE8#/TOC2
B8
PD6
D6[A6/D6]
MTIC5V/
MTIOC8A/
POE4#
B9
PD7
D7[A7/D7]
MTIC5U/
POE0#
B10
PE3
D11[A11/
D11]/
D3[A3/D3]
MTIOC4B/
CTS12#/RTS12#/
PO26/POE8#/ SS12#
TOC3
IRQ11
PJ3
EDACK1
MTIOC3C
IRQ11
C1
VCL
C2
AVSS1
C3
EXCIN
C4
VREFH0
CTX0/MOSIC-A
AN000
IRQ1
AN106
SDHI_D3-B/
QIO3-B
IRQ3
AN104
SSLC2-A
SDHI_D0-B/
QIO0-B
IRQ6
AN101
SSLC3-A
SDHI_D1-B/
QIO1-B
IRQ7
AN100
CTS6#/RTS6#/
CTS0#/RTS0#/
SS6#/SS0#
C5
P42
IRQ10-DS AN002
C6
P47
IRQ15-DS AN007
C7
PD2
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
D2[A2/D2]
MTIOC4D/
TIC2
CRX0/MISOC-A
SDHI_D2-B/
QIO2-B
IRQ2
AN105
Page 59 of 178
RX671 Group
Table 1.8
1. Overview
List of Pin and Pin Functions (100-Pin TFLGA) (2/6)
Pin No.
Timer
Power
Supply
Clock
System
Control
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
Communication
(SCI, RSCI, RSPI,
RSPIA, RIIC,
RIICHS, CAN,
USB, SSIE,
(QSPIX,
REMC)
SDHI)
Interrupt
A/D
IRQ5
AN102
I/O Port
Bus
EXDMAC
C8
PD5
D5[A5/D5]
MTIC5W/
MTIOC8C/
POE10#
SSLC1-A
C9
PE5
D13[A13/
D13]/
D5[A5/D5]
MTIOC4C/
MTIOC2B
RSPCKB-B
IRQ5
C10
PE4
D12[A12/
D12]/
D4[A4/D4]
MTIOC4D/
MTIOC1A/
PO28
SSLB0-B
IRQ12
100-Pin
TFLGA
D1
XCIN
D2
XCOUT
D3
MD/FINED
D4
VBATT
SDHI_CLKB/
QSPCLK-B
D5
P45
IRQ13-DS AN005
D6
P46
IRQ14-DS AN006
D7
PE6
D14[A14/
D14]/
D6[A6/D6]
MTIOC6C/
TIC1
MOSIB-B
SDHI_CD/
SDHI_D0-B/
QIO0-B
IRQ6
D8
PE7
D15[A15/
D15]/
D7[A7/D7]
MTIOC6A/
TOC1
MISOB-B
SDHI_WP/
SDHI_D1-B/
QIO1-B
IRQ7
D9
PA1
A1
MTIOC0B/
SCK5/SSLA2-B/
MTCLKC/
SSL02-B/SCK12
MTIOC7B/
TIOCB0/PO17
SDHI_CD
IRQ11
D10
PA0
A0/BC0#
MTIOC4A/
MTIOC6D/
TIOCA0/
CACREF/
PO16
E1
XTAL
E2
VSS
E3
RES#
E4
TRST#
SSLA1-B/
SSL01-B
Others
(CTSU,
CLKOUT,
Tamper
detection)
IRQ0
P37
P34
MTIOC0A/
SCK6/SCK0
TMCI3/PO12/
POE10#
IRQ4
E5
P41
E6
PA2
A2
MTIOC7A/
PO18
RXD5/SMISO5/
SDHI_WP
SSCL5/SSLA3-B/
SSL03-B/RXD12/
SMISO12/
SSCL12/RXDX12
IRQ10
E7
PA6
A6
MTIC5V/
MTCLKB/
TIOCA2/
TMCI3/PO22/
POE10#
CTS5#/RTS5#/
SS5#/MOSIA-B/
MOSI0-B/CTS12#/
RTS12#/SS12#
IRQ14
E8
PA4
A4
MTIC5U/
MTCLKA/
TIOCA1/
TMRI0/PO20
TXD5/SMOSI5/
SSDA5/SSLA0-B/
SSL00-B/TXD12/
SMOSI12/
SSDA12/TXDX12/
SIOX12
IRQ5-DS
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
IRQ9-DS
TS0
AN001
Page 60 of 178
RX671 Group
Table 1.8
1. Overview
List of Pin and Pin Functions (100-Pin TFLGA) (3/6)
Pin No.
Timer
Power
Supply
Clock
System
Control
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
Communication
(SCI, RSCI, RSPI,
RSPIA, RIIC,
RIICHS, CAN,
USB, SSIE,
(QSPIX,
REMC)
SDHI)
I/O Port
Bus
EXDMAC
E9
PA5
A5
MTIOC6B/
RSPCKA-B/
TIOCB1/PO21 RSPCK0-B
IRQ5
E10
PA3
A3
MTIOC0D/
MTCLKD/
TIOCD0/
TCLKB/PO19
RXD5/SMISO5/
SSCL5
IRQ6-DS
100-Pin
TFLGA
F1
EXTAL
F2
VCC
F3
UPSEL
Interrupt
A/D
Others
(CTSU,
CLKOUT,
Tamper
detection)
P36
P35
NMI
F4
P32
MTIOC0C/
TIOCC0/
TMO3/PO10/
RTCOUT/
RTCIC2/
POE0#/
POE10#
TXD6/TXD0/
SMOSI6/SMOSI0/
SSDA6/SSDA0/
CTX0/
USB0_VBUSEN
IRQ2-DS
F5
P12
MTIC5U/
TMCI1
RXD2/SMISO2/
SSCL2/
SCL0[FM+]/
SCLHS0[FM+/HS]
IRQ2
F6
PB3
A11
MTIOC0A/
MTIOC4A/
TIOCD3/
TCLKD/
TMO0/PO27/
POE11#
SCK6/PMC0-DS
IRQ3
F7
PB2
A10
TIOCC3/
CTS6#/RTS6#/
TCLKC/PO26 SS6#
IRQ2
F8
PB0
A8
MTIC5W/
RXD6/SMISO6/
TIOCA3/PO24 SSCL6
IRQ12
F9
PA7
A7
TIOCB2/PO23 MISOA-B/
MISO0-B
IRQ7
P33
EDREQ1
MTIOC0D/
TIOCD0/
TMRI3/PO11/
POE4#/
POE11#
RXD6/RXD0/
SMISO6/SMISO0/
SSCL6/SSCL0/
CRX0
IRQ3-DS
TS1
F10
TAMPI2
VSS
G1
G2
TMS
P31
MTIOC4D/
TMCI2/PO9/
RTCIC1
CTS1#/RTS1#/
SS1#/SSLB0-A
IRQ1-DS
TAMPI1
G3
TDI
P30
MTIOC4B/
TMRI3/PO8/
RTCIC0/
POE8#
RXD1/SMISO1/
SSCL1/MISOB-A
IRQ0-DS
TAMPI0
G4
TCK
P27
CS7#
MTIOC2B/
TMCI3/PO7
SCK1/RSPCKB-A
IRQ7
TS2
G5
P53*1
BCLK
SSIRXD0/
PMC0-DS
IRQ3
TS12
G6
P52
RD#
RXD2/SMISO2/
SSCL2/SSLB3-A
IRQ2
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 61 of 178
RX671 Group
Table 1.8
1. Overview
List of Pin and Pin Functions (100-Pin TFLGA) (4/6)
Pin No.
Timer
Power
Supply
Clock
System
Control
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
Communication
(SCI, RSCI, RSPI,
RSPIA, RIIC,
RIICHS, CAN,
USB, SSIE,
(QSPIX,
REMC)
SDHI)
I/O Port
Bus
EXDMAC
G7
PB5
A13
MTIOC2A/
SCK9/SCK11/
MTIOC1B/
SCK011
TIOCB4/
TMRI1/PO29/
POE4#
IRQ13
G8
PB4
A12
TIOCA4/PO28 CTS9#/RTS9#/
SS9#/SS11#/
CTS11#/RTS11#/
SS011#/CTS011#/
RTS011#/DE011
IRQ4
G9
PB1
A9
MTIOC0C/
MTIOC4C/
TIOCB3/
TMCI0/PO25
TXD6/SMOSI6/
SSDA6
IRQ4-DS
P26
CS6#
MTIOC2A/
TMO1/PO6
TXD1/CTS3#/
RTS3#/SMOSI1/
SS3#/SSDA1/
MOSIB-A
IRQ6
H2
P25
CS5#/
EDACK1
MTIOC4C/
MTCLKB/
TIOCA4/PO5
RXD3/SMISO3/
SSCL3
H3
P16
MTIOC3C/
MTIOC3D/
TIOCB1/
TCLKC/
TMO2/PO14/
RTCOUT
H4
P15
H5
P55
H6
100-Pin
TFLGA
G10
VCC
H1
TDO
H7
H8
UB
A/D
TS3
IRQ5
ADTRG0# TS4/
CLKOUT
TXD1/RXD3/
SMOSI1/SMISO3/
SSDA1/SSCL3/
SCL2-DS/
USB0_VBUS/
USB0_VBUSEN/
USB0_OVRCURB
IRQ6
ADTRG0#
MTIOC0B/
MTCLKB/
TIOCB2/
TCLKB/
TMCI2/PO13
RXD1/SCK3/
SMISO1/SSCL1/
CRX1-DS
IRQ5
D0[A0/D0]/
WAIT#/
EDREQ0
MTIOC4D/
TMO3
CRX1/MISOC-B
IRQ10
P54
ALE/
D1[A1/D1]/
EDACK0
MTIOC4B/
TMCI1
CTS2#/RTS2#/
SS2#/CTX1/
MOSIC-B
IRQ4
PC7
A23/CS0#
MTIOC3A/
MTCLKB/
TMO2/TOC0/
PO31/
CACREF
TXD8/SMOSI8/
SSDA8/SMOSI10/
SSDA10/TXD10/
MISOA-A/
SSITXD0/
SMOSI010/
SSDA010/
TXD010/MISO0-A
IRQ14
PC6
D2[A2/D2]/
A22/CS1#
MTIOC3C/
MTCLKA/
TMCI2/TIC0/
PO30
RXD8/SMISO8/
SSCL8/SMISO10/
SSCL10/RXD10/
MOSIA-A/
SSILRCK0/
SMISO010/
SSCL010/
RXD010/MOSI0-A
IRQ13
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
SDHI_CD
Interrupt
Others
(CTSU,
CLKOUT,
Tamper
detection)
TS10
TS13
Page 62 of 178
RX671 Group
Table 1.8
1. Overview
List of Pin and Pin Functions (100-Pin TFLGA) (5/6)
Pin No.
Timer
Power
Supply
Clock
System
Control
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
Communication
(SCI, RSCI, RSPI,
RSPIA, RIIC,
RIICHS, CAN,
USB, SSIE,
(QSPIX,
REMC)
SDHI)
I/O Port
Bus
EXDMAC
H9
PB6
A14
MTIOC3D/
RXD9/SMISO9/
TIOCA5/PO30 SSCL9/SMISO11/
SSCL11/RXD11/
SMISO011/
SSCL011/RXD011
IRQ6
H10
PB7
A15
MTIOC3B/
TXD9/SMOSI9/
TIOCB5/PO31 SSDA9/SMOSI11/
SSDA11/TXD11/
SMOSI011/
SSDA011/TXD011
IRQ15
J1
P24
CS4#/
EDREQ1
MTIOC4A/
MTCLKA/
TIOCB4/
TMRI1/PO4
SCK3/
USB0_VBUSEN
SDHI_WP
J2
P21
MTIOC1B/
MTIOC4A/
TIOCA3/
TMCI0/PO1
RXD0/SMISO0/
SSCL0/SCL1/
USB0_EXICEN/
SSILRCK0
SDHI_CLK-C IRQ9
J3
P17
MTIOC3A/
MTIOC3B/
MTIOC4B/
TIOCB0/
TCLKD/
TMO1/PO15/
POE8#
SCK1/TXD3/
SMOSI3/SSDA3/
SDA2-DS/
SSITXD0
SDHI_D3-C
J4
P13
MTIOC0B/
TIOCA5/
TMO3/PO13
100-Pin
TFLGA
J5
VSS_USB
J6
VCC_USB
Interrupt
Others
(CTSU,
CLKOUT,
Tamper
detection)
A/D
IRQ12
TS5
TS8
IRQ7
ADTRG1#
TXD2/SMOSI2/
SSDA2/
SDA0[FM+]/
SDAHS0[FM+/HS]
IRQ3
ADTRG1#
TXD2/SMOSI2/
SSDA2/SSLB1-A
IRQ0
SCK5/CTS8#/
SDHI_D1-A/
RTS8#/SS8#/
QIO1-A
SS10#/CTS10#/
RTS10#/SSLA0-A/
AUDIO_CLK/
SS010#/CTS010#/
RTS010#/DE010/
SSL00-A
IRQ12
TSCAP
J7
P50
WR0#/WR#
J8
PC4
A20/CS3#
MTIOC3D/
MTCLKC/
TMCI1/PO25/
POE0#
J9
PC0
A16
MTIOC3C/
CTS5#/RTS5#/
TCLKC/PO17 SS5#/SSLA1-A/
RXD011/
SMISO011/
SSCL011/
SSL01-A
IRQ14
TS16
J10
PC1
A17
MTIOC3A/
SCK5/SSLA2-A/
TCLKD/PO18 TXD011/
SMOSI011/
SSDA011/
TXDA011/
SSL02-A
IRQ12
TS15
K1
P23
EDACK0
MTIOC3D/
MTCLKD/
TIOCD3/PO3
IRQ3
TS6
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
TXD3/CTS0#/
RTS0#/SMOSI3/
SS0#/SSDA3/
SSIBCK0
SDHI_D1-C
Page 63 of 178
RX671 Group
Table 1.8
1. Overview
List of Pin and Pin Functions (100-Pin TFLGA) (6/6)
Pin No.
Timer
Power
Supply
Clock
System
Control
Communication
MTIOC3B/
MTCLKC/
TIOCC3/
TMO0/PO2
SCK0/
SDHI_D0-C
USB0_OVRCURB
/
AUDIO_CLK
IRQ15
TS7
IRQ8
TS9
TS11
I/O Port
Bus
EXDMAC
K2
P22
EDREQ0
K3
P20
MTIOC1A/
TIOCB3/
TMRI0/PO0
TXD0/SMOSI0/
SSDA0/SDA1/
USB0_ID/
SSIRXD0
K4
P14
MTIOC3A/
MTCLKA/
TIOCB5/
TCLKA/
TMRI2/PO15
CTS1#/RTS1#/
SS1#/CTX1/
USB0_OVRCURA
IRQ4
K5
PH2
TMRI0
USB0_DM
IRQ1
K6
PH1
TMO0
USB0_DP
IRQ0
K7
P51
WR1#/
BC1#/
WAIT#
SCK2/SSLB2-A
IRQ1
K8
PC5
D3[A3/D3]/
A21/CS2#/
WAIT#
MTIOC3B/
MTCLKD/
TMRI2/PO29
SCK8/SCK10/
RSPCKA-A/
SSIBCK0/
SCK010/
RSPCK0-A
IRQ5
K9
PC3
A19
MTIOC4D/
TCLKB/PO24
TXD5/SMOSI5/
SDHI_D0-A/
SSDA5/PMC0-DS QIO0-A
IRQ11
K10
PC2
A18
MTIOC4B/
TCLKA/PO21
RXD5/SMISO5/
SSCL5/SSLA3-A/
TXDB011/
SSL03-A
IRQ10
100-Pin
TFLGA
Others
(CTSU,
CLKOUT,
Tamper
detection)
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
(SCI, RSCI, RSPI,
RSPIA, RIIC,
RIICHS, CAN,
USB, SSIE,
(QSPIX,
REMC)
SDHI)
SDHI_CMDC
SDHI_D3-A
Interrupt
A/D
TS14
Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled.
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 64 of 178
RX671 Group
1.6.5
1. Overview
100-Pin LFQFP
Table 1.9
List of Pin and Pin Functions (100-Pin LFQFP) (1/6)
Pin No.
Timer
100-Pin
LFQFP
Power
Supply
Clock
System
Control
1
AVCC1
2
EMLE
3
AVSS1
4
EXCIN
5
VCL
6
VBATT
7
MD/FINED
8
XCIN
9
XCOUT
10
RES#
11
XTAL
12
VSS
13
EXTAL
14
VCC
15
UPSEL
P35
16
TRST#
P34
I/O Port
Bus
EXDMAC
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
PJ3
EDACK1
MTIOC3C
Communication
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
CTS6#/RTS6#/
CTS0#/RTS0#/
SS6#/SS0#
Interrupt
A/D
Others
(CTSU,
CLKOUT,
Tamper
detection)
IRQ11
P37
P36
NMI
EDREQ1
MTIOC0A/
SCK6/SCK0
TMCI3/PO12/
POE10#
IRQ4
TS0
MTIOC0D/
TIOCD0/
TMRI3/PO11/
POE4#/
POE11#
RXD6/RXD0/
SMISO6/
SMISO0/SSCL6/
SSCL0/CRX0
IRQ3-DS
TS1
17
P33
18
P32
MTIOC0C/
TIOCC0/
TMO3/PO10/
RTCOUT/
RTCIC2/
POE0#/
POE10#
TXD6/TXD0/
SMOSI6/
SMOSI0/SSDA6/
SSDA0/CTX0/
USB0_VBUSEN
IRQ2-DS
TAMPI2
19
TMS
P31
MTIOC4D/
TMCI2/PO9/
RTCIC1
CTS1#/RTS1#/
SS1#/SSLB0-A
IRQ1-DS
TAMPI1
20
TDI
P30
MTIOC4B/
TMRI3/PO8/
RTCIC0/
POE8#
RXD1/SMISO1/
SSCL1/MISOB-A
IRQ0-DS
TAMPI0
21
TCK
P27
CS7#
MTIOC2B/
TMCI3/PO7
SCK1/RSPCKB-A
IRQ7
TS2
22
TDO
P26
CS6#
MTIOC2A/
TMO1/PO6
TXD1/CTS3#/
RTS3#/SMOSI1/
SS3#/SSDA1/
MOSIB-A
IRQ6
TS3
P25
CS5#/
EDACK1
MTIOC4C/
MTCLKB/
TIOCA4/PO5
RXD3/SMISO3/
SSCL3
23
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
SDHI_CD
IRQ5
ADTRG0# TS4/
CLKOUT
Page 65 of 178
RX671 Group
Table 1.9
1. Overview
List of Pin and Pin Functions (100-Pin LFQFP) (2/6)
Pin No.
100-Pin
LFQFP
Timer
Power
Supply
Clock
System
Control
I/O Port
Bus
EXDMAC
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
Communication
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
Interrupt
Others
(CTSU,
CLKOUT,
Tamper
detection)
A/D
24
P24
CS4#/
EDREQ1
MTIOC4A/
MTCLKA/
TIOCB4/
TMRI1/PO4
SCK3/
USB0_VBUSEN
SDHI_WP
IRQ12
TS5
25
P23
EDACK0
MTIOC3D/
MTCLKD/
TIOCD3/PO3
TXD3/CTS0#/
RTS0#/SMOSI3/
SS0#/SSDA3/
SSIBCK0
SDHI_D1-C
IRQ3
TS6
26
P22
EDREQ0
MTIOC3B/
MTCLKC/
TIOCC3/
TMO0/PO2
SCK0/
USB0_OVRCUR
B/
AUDIO_CLK
SDHI_D0-C
IRQ15
TS7
27
P21
MTIOC1B/
MTIOC4A/
TIOCA3/
TMCI0/PO1
RXD0/SMISO0/
SSCL0/SCL1/
USB0_EXICEN/
SSILRCK0
SDHI_CLK-C IRQ9
TS8
28
P20
MTIOC1A/
TIOCB3/
TMRI0/PO0
TXD0/SMOSI0/
SSDA0/SDA1/
USB0_ID/
SSIRXD0
SDHI_CMDC
IRQ8
TS9
29
P17
MTIOC3A/
MTIOC3B/
MTIOC4B/
TIOCB0/
TCLKD/
TMO1/PO15/
POE8#
SCK1/TXD3/
SDHI_D3-C
SMOSI3/SSDA3/
SDA2-DS/
SSITXD0
IRQ7
ADTRG1#
30
P16
MTIOC3C/
MTIOC3D/
TIOCB1/
TCLKC/
TMO2/PO14/
RTCOUT
TXD1/RXD3/
SMOSI1/
SMISO3/SSDA1/
SSCL3/SCL2-DS/
USB0_VBUS/
USB0_VBUSEN/
USB0_OVRCUR
B
IRQ6
ADTRG0#
31
P15
MTIOC0B/
MTCLKB/
TIOCB2/
TCLKB/
TMCI2/PO13
RXD1/SCK3/
SMISO1/SSCL1/
CRX1-DS
IRQ5
TS10
32
P14
MTIOC3A/
MTCLKA/
TIOCB5/
TCLKA/
TMRI2/PO15
CTS1#/RTS1#/
SS1#/CTX1/
USB0_OVRCUR
A
IRQ4
TS11
33
P13
MTIOC0B/
TIOCA5/
TMO3/PO13
TXD2/SMOSI2/
SSDA2/
SDA0[FM+]/
SDAHS0[FM+/
HS]
IRQ3
34
P12
MTIC5U/
TMCI1
RXD2/SMISO2/
SSCL2/
SCL0[FM+]/
SCLHS0[FM+/
HS]
IRQ2
PH2
TMRI0
USB0_DM
IRQ1
35
36
ADTRG1#
VCC_USB
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 66 of 178
RX671 Group
Table 1.9
1. Overview
List of Pin and Pin Functions (100-Pin LFQFP) (3/6)
Pin No.
100-Pin
LFQFP
Timer
Power
Supply
Clock
System
Control
37
38
I/O Port
Bus
EXDMAC
PH1
Communication
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
Interrupt
TMO0
USB0_DP
IRQ0
A/D
Others
(CTSU,
CLKOUT,
Tamper
detection)
VSS_USB
39
P55
D0[A0/D0]/
WAIT#/
EDREQ0
MTIOC4D/
TMO3
CRX1/MISOC-B
IRQ10
40
P54
ALE/
D1[A1/D1]/
EDACK0
MTIOC4B/
TMCI1
CTS2#/RTS2#/
SS2#/CTX1/
MOSIC-B
IRQ4
41
P53*1
BCLK
SSIRXD0/
PMC0-DS
IRQ3
42
P52
RD#
RXD2/SMISO2/
SSCL2/SSLB3-A
IRQ2
43
P51
WR1#/
BC1#/
WAIT#
SCK2/SSLB2-A
IRQ1
44
P50
WR0#/WR#
TXD2/SMOSI2/
SSDA2/SSLB1-A
IRQ0
PC7
A23/CS0#
MTIOC3A/
MTCLKB/
TMO2/TOC0/
PO31/
CACREF
TXD8/SMOSI8/
SSDA8/
SMOSI10/
SSDA10/TXD10/
MISOA-A/
SSITXD0/
SMOSI010/
SSDA010/
TXD010/
MISO0-A
IRQ14
46
PC6
D2[A2/D2]/
A22/CS1#
MTIOC3C/
MTCLKA/
TMCI2/TIC0/
PO30
RXD8/SMISO8/
SSCL8/
SMISO10/
SSCL10/RXD10/
MOSIA-A/
SSILRCK0/
SMISO010/
SSCL010/
RXD010/
MOSI0-A
IRQ13
TS13
47
PC5
D3[A3/D3]/
A21/CS2#/
WAIT#
MTIOC3B/
MTCLKD/
TMRI2/PO29
SCK8/SCK10/
RSPCKA-A/
SSIBCK0/
SCK010/
RSPCK0-A
IRQ5
TS14
48
PC4
A20/CS3#
MTIOC3D/
MTCLKC/
TMCI1/PO25/
POE0#
SCK5/CTS8#/
SDHI_D1-A/
RTS8#/SS8#/
QIO1-A
SS10#/CTS10#/
RTS10#/
SSLA0-A/
AUDIO_CLK/
SS010#/
CTS010#/
RTS010#/DE010/
SSL00-A
IRQ12
TSCAP
49
PC3
A19
MTIOC4D/
TCLKB/PO24
TXD5/SMOSI5/
SSDA5/
PMC0-DS
IRQ11
45
UB
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
SDHI_D0-A/
QIO0-A
TS12
Page 67 of 178
RX671 Group
Table 1.9
1. Overview
List of Pin and Pin Functions (100-Pin LFQFP) (4/6)
Pin No.
Timer
Power
Supply
Clock
System
Control
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
Communication
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
Others
(CTSU,
CLKOUT,
Tamper
detection)
I/O Port
Bus
EXDMAC
50
PC2
A18
MTIOC4B/
TCLKA/PO21
51
PC1
A17
MTIOC3A/
SCK5/SSLA2-A/
TCLKD/PO18 TXD011/
SMOSI011/
SSDA011/
TXDA011/
SSL02-A
IRQ12
TS15
52
PC0
A16
MTIOC3C/
CTS5#/RTS5#/
TCLKC/PO17 SS5#/SSLA1-A/
RXD011/
SMISO011/
SSCL011/
SSL01-A
IRQ14
TS16
53
PB7
A15
MTIOC3B/
TXD9/SMOSI9/
TIOCB5/PO31 SSDA9/
SMOSI11/
SSDA11/TXD11/
SMOSI011/
SSDA011/
TXD011
IRQ15
54
PB6
A14
MTIOC3D/
RXD9/SMISO9/
TIOCA5/PO30 SSCL9/SMISO11/
SSCL11/RXD11/
SMISO011/
SSCL011/
RXD011
IRQ6
55
PB5
A13
MTIOC2A/
SCK9/SCK11/
MTIOC1B/
SCK011
TIOCB4/
TMRI1/PO29/
POE4#
IRQ13
56
PB4
A12
TIOCA4/PO28 CTS9#/RTS9#/
SS9#/SS11#/
CTS11#/RTS11#/
SS011#/
CTS011#/
RTS011#/DE011
IRQ4
57
PB3
A11
MTIOC0A/
MTIOC4A/
TIOCD3/
TCLKD/
TMO0/PO27/
POE11#
IRQ3
58
PB2
A10
TIOCC3/
CTS6#/RTS6#/
TCLKC/PO26 SS6#
IRQ2
59
PB1
A9
MTIOC0C/
MTIOC4C/
TIOCB3/
TMCI0/PO25
IRQ4-DS
PB0
A8
MTIC5W/
RXD6/SMISO6/
TIOCA3/PO24 SSCL6
100-Pin
LFQFP
60
SCK6/PMC0-DS
TXD6/SMOSI6/
SSDA6
A/D
IRQ10
VCC
61
62
RXD5/SMISO5/
SDHI_D3-A
SSCL5/SSLA3-A/
TXDB011/
SSL03-A
Interrupt
IRQ12
VSS
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 68 of 178
RX671 Group
Table 1.9
1. Overview
List of Pin and Pin Functions (100-Pin LFQFP) (5/6)
Pin No.
Timer
Power
Supply
Clock
System
Control
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
Communication
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
I/O Port
Bus
EXDMAC
63
PA7
A7
TIOCB2/PO23 MISOA-B/
MISO0-B
IRQ7
64
PA6
A6
MTIC5V/
MTCLKB/
TIOCA2/
TMCI3/PO22/
POE10#
IRQ14
65
PA5
A5
MTIOC6B/
RSPCKA-B/
TIOCB1/PO21 RSPCK0-B
IRQ5
66
PA4
A4
MTIC5U/
MTCLKA/
TIOCA1/
TMRI0/PO20
TXD5/SMOSI5/
SSDA5/SSLA0-B/
SSL00-B/TXD12/
SMOSI12/
SSDA12/
TXDX12/SIOX12
IRQ5-DS
67
PA3
A3
MTIOC0D/
MTCLKD/
TIOCD0/
TCLKB/PO19
RXD5/SMISO5/
SSCL5
IRQ6-DS
68
PA2
A2
MTIOC7A/
PO18
RXD5/SMISO5/
SDHI_WP
SSCL5/SSLA3-B/
SSL03-B/RXD12/
SMISO12/
SSCL12/RXDX12
IRQ10
69
PA1
A1
MTIOC0B/
SCK5/SSLA2-B/
MTCLKC/
SSL02-B/SCK12
MTIOC7B/
TIOCB0/PO17
70
PA0
A0/BC0#
MTIOC4A/
MTIOC6D/
TIOCA0/
CACREF/
PO16
SSLA1-B/
SSL01-B
71
PE7
D15[A15/
D15]/
D7[A7/D7]
MTIOC6A/
TOC1
MISOB-B
SDHI_WP/
SDHI_D1-B/
QIO1-B
IRQ7
72
PE6
D14[A14/
D14]/
D6[A6/D6]
MTIOC6C/
TIC1
MOSIB-B
SDHI_CD/
SDHI_D0-B/
QIO0-B
IRQ6
73
PE5
D13[A13/
D13]/
D5[A5/D5]
MTIOC4C/
MTIOC2B
RSPCKB-B
IRQ5
74
PE4
D12[A12/
D12]/
D4[A4/D4]
MTIOC4D/
MTIOC1A/
PO28
SSLB0-B
IRQ12
75
PE3
D11[A11/
D11]/
D3[A3/D3]
MTIOC4B/
CTS12#/RTS12#/
PO26/POE8#/ SS12#
TOC3
IRQ11
76
PE2
D10[A10/
D10]/
D2[A2/D2]
MTIOC4A/
PO23/TIC3
RXD12/
SMISO12/
SSCL12/
RXDX12/
SSLB3-B
IRQ7-DS
77
PE1
D9[A9/D9]/
D1[A1/D1]
MTIOC4C/
MTIOC3B/
PO18
TXD12/SMOSI12/
SSDA12/
TXDX12/SIOX12/
SSLB2-B
IRQ9
100-Pin
LFQFP
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
CTS5#/RTS5#/
SS5#/MOSIA-B/
MOSI0-B/
CTS12#/RTS12#/
SS12#
SDHI_CD
Interrupt
A/D
Others
(CTSU,
CLKOUT,
Tamper
detection)
IRQ11
IRQ0
ANEX1
Page 69 of 178
RX671 Group
Table 1.9
1. Overview
List of Pin and Pin Functions (100-Pin LFQFP) (6/6)
Pin No.
100-Pin
LFQFP
Timer
Power
Supply
Clock
System
Control
I/O Port
Bus
EXDMAC
Communication
(MTU, TPU,
TMR, PPG,
RTC, CMTW,
POE, CAC)
(SCI, RSCI,
RSPI, RSPIA,
RIIC, RIICHS,
CAN, USB, SSIE, (QSPIX,
REMC)
SDHI)
Interrupt
A/D
IRQ8
ANEX0
Others
(CTSU,
CLKOUT,
Tamper
detection)
78
PE0
D8[A8/D8]/
D0[A0/D0]
MTIOC3D
SCK12/SSLB1-B
79
PD7
D7[A7/D7]
MTIC5U/
POE0#
SSLC3-A
SDHI_D1-B/
QIO1-B
IRQ7
AN100
80
PD6
D6[A6/D6]
MTIC5V/
MTIOC8A/
POE4#
SSLC2-A
SDHI_D0-B/
QIO0-B
IRQ6
AN101
81
PD5
D5[A5/D5]
MTIC5W/
MTIOC8C/
POE10#
SSLC1-A
SDHI_CLKB/
QSPCLK-B
IRQ5
AN102
82
PD4
D4[A4/D4]
MTIOC8B/
POE11#
SSLC0-A
SDHI_CMDB/
QSSL-B
IRQ4
AN103
83
PD3
D3[A3/D3]
MTIOC8D/
RSPCKC-A
POE8#/TOC2
SDHI_D3-B/
QIO3-B
IRQ3
AN104
84
PD2
D2[A2/D2]
MTIOC4D/
TIC2
CRX0/MISOC-A
SDHI_D2-B/
QIO2-B
IRQ2
AN105
85
PD1
D1[A1/D1]
MTIOC4B/
POE0#
CTX0/MOSIC-A
IRQ1
AN106
86
PD0
D0[A0/D0]
POE4#
IRQ0
AN107
87
P47
IRQ15-DS
AN007
88
P46
IRQ14-DS
AN006
89
P45
IRQ13-DS
AN005
90
P44
IRQ12-DS
AN004
91
P43
IRQ11-DS
AN003
92
P42
IRQ10-DS
AN002
93
P41
IRQ9-DS
AN001
P40
IRQ8-DS
AN000
P07
IRQ15
ADTRG0#
P05
IRQ13
94
VREFL0
95
96
VREFH0
97
AVCC0
98
99
100
AVSS0
Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled.
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 70 of 178
RX671 Group
1.6.6
1. Overview
64-Pin TFBGA
Table 1.10
List of Pin and Pin Functions (64-Pin TFBGA) (1/3)
Pin No.
Timer
64-Pin
TFBGA
Power Supply
Clock
System
Control
I/O Port
A1
AVCC1
A2
AVSS0
A3
VREFH0
A4
VREFL0
Communication
(SCI, RSCI, RSPI,
(MTU, TPU, TMR, RSPIA, RIIC,
RTC, CMTW, POE, RIICHS, USB, SSIE, (QSPIX,
CAC)
REMC)
SDHI)
Interrupt
A/D
A5
PD2
MTIOC4D/TIC2
SDHI_D2-B/
QIO2-B
IRQ2
AN105
A6
PD7
MTIC5U/POE0#
SDHI_D1-B/
QIO1-B
IRQ7
AN100
A7
PE0
MTIOC3D
SCK12/SSLB1-B
IRQ8
ANEX0
A8
PE2
MTIOC4A/TIC3
RXD12/SMISO12/
SSCL12/RXDX12/
SSLB3-B
IRQ7-DS
B1
Others
(CTSU,
Tamper
detection)
EMLE
B2
AVSS1
B3
AVCC0
B4
P42
IRQ10-DS
AN002
B5
PD3
MTIOC8D/POE8#/
TOC2
SDHI_D3-B/
QIO3-B
IRQ3
AN104
B6
PD6
MTIC5V/MTIOC8A/
POE4#
SDHI_D0-B/
QIO0-B
IRQ6
AN101
B7
PE1
MTIOC4C/
MTIOC3B
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/SSLB2-B
IRQ9
ANEX1
B8
PE6
MTIOC6C/TIC1
MOSIB-B
C1
VCL
C2
VBATT
C3
MD/FINED
SDHI_CD/
SDHI_D0-B/
QIO0-B
IRQ6
C4
P41
C5
PD4
MTIOC8B/POE11#
SDHI_CMD-B/ IRQ4
QSSL-B
AN103
C6
PD5
MTIC5W/
MTIOC8C/POE10#
SDHI_CLK-B/ IRQ5
QSPCLK-B
AN102
C7
PA1
MTIOC0B/
SCK5/SSLA2-B/
MTCLKC/
SSL02-B/SCK12
MTIOC7B/TIOCB0
SDHI_CD
IRQ11
C8
PE7
MTIOC6A/TOC1
SDHI_WP/
SDHI_D1-B/
QIO1-B
IRQ7
D1
XCIN
D2
XCOUT
D3
RES#
IRQ9-DS
MISOB-B
AN001
D4
P40
IRQ8-DS
AN000
D5
P43
IRQ11-DS
AN003
D6
PA6
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
MTIC5V/MTCLKB/ CTS5#/RTS5#/
TIOCA2/TMCI3/
SS5#/MOSIA-B/
POE10#
MOSI0-B/CTS12#/
RTS12#/SS12#
IRQ14
Page 71 of 178
RX671 Group
Table 1.10
1. Overview
List of Pin and Pin Functions (64-Pin TFBGA) (2/3)
Pin No.
64-Pin
TFBGA
Timer
Power Supply
Clock
System
Control
I/O Port
Communication
(SCI, RSCI, RSPI,
(MTU, TPU, TMR, RSPIA, RIIC,
RTC, CMTW, POE, RIICHS, USB, SSIE, (QSPIX,
CAC)
REMC)
SDHI)
Interrupt
IRQ10
D7
PA2
MTIOC7A
D8
PA4
MTIC5U/MTCLKA/ TXD5/SMOSI5/
TIOCA1/TMRI0
SSDA5/SSLA0-B/
SSL00-B/TXD12/
SMOSI12/SSDA12/
TXDX12/SIOX12
IRQ5-DS
P34
MTIOC0A/TMCI3/
POE10#
IRQ4
P13
MTIOC0B/TIOCA5/ TXD2/SMOSI2/
TMO3
SSDA2/SDA0[FM+]/
SDAHS0[FM+/HS]
IRQ3
PA7
TIOCB2
MISOA-B/MISO0-B
IRQ7
TMCI1/MTIC5U
RXD2/SMISO2/
SSCL2/SCL0[FM+]/
SCLHS0[FM+/HS]
IRQ2
SSIRXD0/PMC0-DS
IRQ3
E1
XTAL
E2
VSS
E3
TRST#
E4
E5
RXD5/SMISO5/
SSCL5/SSLA3-B/
SSL03-B/RXD12/
SMISO12/SSCL12/
RXDX12
SDHI_WP
Others
(CTSU,
Tamper
detection)
A/D
P37
TS0
ADTRG1#
BSCANP
E6
E7
VCC
E8
VSS
F1
EXTAL
F2
VCC
F3
UPSEL
P36
P35
NMI
F4
P12
F5
P53
F6
PB7
MTIOC3B/TIOCB5 TXD9/SMOSI9/
SSDA9/SMOSI11/
SSDA11/TXD11/
SMOSI011/
SSDA011/TXD011
IRQ15
F7
PB6
MTIOC3D/TIOCA5 RXD9/SMISO9/
SSCL9/SMISO11/
SSCL11/RXD11/
SMISO011/
SSCL011/RXD011
IRQ6
F8
PB5
MTIOC2A/
SCK9/SCK11/
MTIOC1B/TIOCB4/ SCK011
TMRI1/POE4#
IRQ13
TS12
G1
TCK
P27
MTIOC2B/TMCI3
SCK1/RSPCKB-A
IRQ7
TS2
G2
TMS
P31
MTIOC4D/TMCI2/
RTCIC1
CTS1#/RTS1#/
SS1#/SSLB0-A
IRQ1-DS
TAMPI1
G3
TDI
P30
MTIOC4B/TMRI3/
RTCIC0/POE8#
RXD1/SMISO1/
SSCL1/MISOB-A
IRQ0-DS
TAMPI0
PC7
MTIOC3A/
MTCLKB/TMO2/
TOC0/CACREF
TXD8/SMOSI8/
SSDA8/SMOSI10/
SSDA10/TXD10/
MISOA-A/SSITXD0/
SMOSI010/
SSDA010/TXD010/
MISO0-A
IRQ14
G4
VCC_USB
G5
VSS_USB
G6
UB
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 72 of 178
RX671 Group
Table 1.10
1. Overview
List of Pin and Pin Functions (64-Pin TFBGA) (3/3)
Pin No.
64-Pin
TFBGA
Timer
Power Supply
Clock
System
Control
I/O Port
Communication
(SCI, RSCI, RSPI,
(MTU, TPU, TMR, RSPIA, RIIC,
RTC, CMTW, POE, RIICHS, USB, SSIE, (QSPIX,
CAC)
REMC)
SDHI)
Interrupt
Others
(CTSU,
Tamper
detection)
A/D
G7
PC5
MTIOC3B/
MTCLKD/TMRI2
SCK8/SCK10/
RSPCKA-A/
SSIBCK0/SCK010/
RSPCK0-A
IRQ5
TS14
G8
PC0
MTIOC3C/TCLKC
CTS5#/RTS5#/
SS5#/SSLA1-A/
RXD011/SMISO011/
SSCL011/SSL01-A
IRQ14
TS16
P26
MTIOC2A/TMO1
TXD1/CTS3#/
RTS3#/SMOSI1/
SS3#/SSDA1/
MOSIB-A
IRQ6
TS3
H2
P17
MTIOC3A/
SCK1/TXD3/
MTIOC3B/
SMOSI3/SSDA3/
MTIOC4B/TIOCB0/ SDA2-DS/SSITXD0
TCLKD/TMO1/
POE8#
H3
P16
MTIOC3C/
MTIOC3D/TIOCB1/
TCLKC/TMO2/
RTCOUT
H4
PH2
TMRI0
USB0_DM
IRQ1
H5
PH1
TMO0
USB0_DP
IRQ0
H6
PC6
MTIOC3C/
MTCLKA/TMCI2/
TIC0
RXD8/SMISO8/
SSCL8/SMISO10/
SSCL10/RXD10/
MOSIA-A/
SMISO010/
SSCL010/RXD010/
MOSI0-A/SSILRCK0
IRQ13
TS13
H7
PC4
MTIOC3D/
MTCLKC/TMCI1/
POE0#
SCK5/CTS8#/
SDHI_D1-A/
RTS8#/SS8#/SS10#/ QIO1-A
CTS10#/RTS10#/
SSLA0-A/
AUDIO_CLK/
SS010#/CTS010#/
RTS010#/DE010/
SSL00-A
IRQ12
TSCAP
H8
PC1
MTIOC3A/TCLKD
SCK5/SSLA2-A/
TXD011/SMOSI011/
SSDA011/TXDA011/
SSL02-A
IRQ12
TS15
H1
TDO
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
SDHI_D3-C
TXD1/RXD3/
SMOSI1/SMISO3/
SSDA1/SSCL3/
SCL2-DS/
USB0_VBUS
IRQ7
ADTRG1#
IRQ6
ADTRG0#
Page 73 of 178
RX671 Group
1.6.7
1. Overview
64-Pin LFQFP
Table 1.11
List of Pin and Pin Functions (64-Pin LFQFP) (1/3)
Pin No.
Timer
64-Pin
LFQFP
Power Supply
Clock
System
Control
I/O Port
1
AVCC1
2
EMLE
3
AVSS1
4
VCL
5
VBATT
6
MD/FINED
7
XCIN
8
XCOUT
9
RES#
10
XTAL
11
VSS
12
EXTAL
13
VCC
Communication
(SCI, RSCI, RSPI,
(MTU, TPU, TMR, RSPIA, RIIC,
RTC, CMTW, POE, RIICHS, USB, SSIE, (QSPIX,
CAC)
REMC)
SDHI)
P36
UPSEL
P35
15
TRST#
P34
MTIOC0A/TMCI3/
POE10#
16
TDI
P30
MTIOC4B/TMRI3/
RTCIC0/POE8#
17
TMS
P31
18
TDO
P26
NMI
19
TCK
IRQ4
TS0
RXD1/SMISO1/
SSCL1/MISOB-A
IRQ0-DS
TAMPI0
MTIOC4D/TMCI2/
RTCIC1
CTS1#/RTS1#/
SS1#/SSLB0-A
IRQ1-DS
TAMPI1
MTIOC2A/TMO1
TXD1/CTS3#/
RTS3#/SMOSI1/
SS3#/SSDA1/
MOSIB-A
IRQ6
TS3
SCK1/RSPCKB-A
P27
MTIOC2B/TMCI3
20
P17
MTIOC3A/
SCK1/TXD3/
MTIOC3B/
SMOSI3/SSDA3/
MTIOC4B/TIOCB0/ SDA2-DS/SSITXD0
TCLKD/TMO1/
POE8#
21
P16
MTIOC3C/
MTIOC3D/TIOCB1/
TCLKC/TMO2/
RTCOUT
22
P13
23
26
28
IRQ7
TS2
IRQ7
ADTRG1#
IRQ6
ADTRG0#
MTIOC0B/TIOCA5/ TXD2/SMOSI2/
TMO3
SSDA2/SDA0[FM+]/
SDAHS0[FM+/HS]
IRQ3
ADTRG1#
P12
TMCI1/MTIC5U
RXD2/SMISO2/
SSCL2/SCL0[FM+]/
SCLHS0[FM+/HS]
IRQ2
PH2
TMRI0
USB0_DM
IRQ1
PH1
TMO0
USB0_DP
IRQ0
SSIRXD0/PMC0-DS
IRQ3
TXD1/RXD3/
SMOSI1/SMISO3/
SSDA1/SSCL3/
SCL2-DS/
USB0_VBUS
SDHI_D3-C
VCC_USB
25
27
A/D
P37
14
24
Interrupt
Others
(CTSU,
Tamper
detection)
VSS_USB
P53
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
TS12
Page 74 of 178
RX671 Group
Table 1.11
1. Overview
List of Pin and Pin Functions (64-Pin LFQFP) (2/3)
Pin No.
Timer
Communication
64-Pin
LFQFP
Power Supply
Clock
System
Control
I/O Port
(SCI, RSCI, RSPI,
(MTU, TPU, TMR, RSPIA, RIIC,
RTC, CMTW, POE, RIICHS, USB, SSIE, (QSPIX,
CAC)
REMC)
SDHI)
29
UB
PC7
MTIOC3A/
MTCLKB/TMO2/
TOC0/CACREF
TXD8/SMOSI8/
SSDA8/SMOSI10/
SSDA10/TXD10/
MISOA-A/SSITXD0/
SMOSI010/
SSDA010/TXD010/
MISO0-A
IRQ14
30
PC6
MTIOC3C/
MTCLKA/TMCI2/
TIC0
RXD8/SMISO8/
SSCL8/SMISO10/
SSCL10/RXD10/
MOSIA-A/
SMISO010/
SSCL010/RXD010/
MOSI0-A/SSILRCK0
IRQ13
TS13
31
PC5
MTIOC3B/
MTCLKD/TMRI2
SCK8/SCK10/
RSPCKA-A/
SSIBCK0/SCK010/
RSPCK0-A
IRQ5
TS14
32
PC4
MTIOC3D/
MTCLKC/TMCI1/
POE0#
SCK5/CTS8#/
SDHI_D1-A/
RTS8#/SS8#/SS10#/ QIO1-A
CTS10#/RTS10#/
SSLA0-A/
AUDIO_CLK/
SS010#/CTS010#/
RTS010#/DE010/
SSL00-A
IRQ12
TSCAP
33
PC1
MTIOC3A/TCLKD
SCK5/SSLA2-A/
TXD011/SMOSI011/
SSDA011/TXDA011/
SSL02-A
IRQ12
TS15
34
PC0
MTIOC3C/TCLKC
CTS5#/RTS5#/
SS5#/SSLA1-A/
RXD011/SMISO011/
SSCL011/SSL01-A
IRQ14
TS16
35
PB7
MTIOC3B/TIOCB5 TXD9/SMOSI9/
SSDA9/SMOSI11/
SSDA11/TXD11/
SMOSI011/
SSDA011/TXD011
IRQ15
36
PB6
MTIOC3D/TIOCA5 RXD9/SMISO9/
SSCL9/SMISO11/
SSCL11/RXD11/
SMISO011/
SSCL011/RXD011
IRQ6
37
PB5
MTIOC2A/
SCK9/SCK11/
MTIOC1B/TIOCB4/ SCK011
TMRI1/POE4#
IRQ13
40
PA7
TIOCB2
41
PA6
MTIC5V/MTCLKB/ CTS5#/RTS5#/
TIOCA2/TMCI3/
SS5#/MOSIA-B/
POE10#
MOSI0-B/CTS12#/
RTS12#/SS12#
38
VCC
39
VSS
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
MISOA-B/MISO0-B
Interrupt
A/D
Others
(CTSU,
Tamper
detection)
IRQ7
IRQ14
Page 75 of 178
RX671 Group
Table 1.11
1. Overview
List of Pin and Pin Functions (64-Pin LFQFP) (3/3)
Pin No.
64-Pin
LFQFP
Timer
Power Supply
Clock
System
Control
I/O Port
Communication
(SCI, RSCI, RSPI,
(MTU, TPU, TMR, RSPIA, RIIC,
RTC, CMTW, POE, RIICHS, USB, SSIE, (QSPIX,
CAC)
REMC)
SDHI)
42
PA4
MTIC5U/MTCLKA/ TXD5/SMOSI5/
TIOCA1/TMRI0
SSDA5/SSLA0-B/
SSL00-B/TXD12/
SMOSI12/SSDA12/
TXDX12/SIOX12
43
PA2
MTIOC7A
44
PA1
45
RXD5/SMISO5/
SSCL5/SSLA3-B/
SSL03-B/RXD12/
SMISO12/SSCL12/
RXDX12
Interrupt
A/D
IRQ5-DS
SDHI_WP
IRQ10
MTIOC0B/
SCK5/SSLA2-B/
MTCLKC/
SSL02-B/SCK12
MTIOC7B/TIOCB0
SDHI_CD
IRQ11
PE7
MTIOC6A/TOC1
MISOB-B
SDHI_WP/
SDHI_D1-B/
QIO1-B
IRQ7
46
PE6
MTIOC6C/TIC1
MOSIB-B
SDHI_CD/
SDHI_D0-B/
QIO0-B
IRQ6
47
PE2
MTIOC4A/TIC3
RXD12/SMISO12/
SSCL12/RXDX12/
SSLB3-B
IRQ7-DS
48
PE1
MTIOC4C/
MTIOC3B
TXD12/SMOSI12/
SSDA12/TXDX12/
SIOX12/SSLB2-B
IRQ9
SCK12/SSLB1-B
ANEX1
49
PE0
MTIOC3D
IRQ8
ANEX0
50
PD7
MTIC5U/POE0#
SDHI_D1-B/
QIO1-B
IRQ7
AN100
51
PD6
MTIC5V/MTIOC8A/
POE4#
SDHI_D0-B/
QIO0-B
IRQ6
AN101
52
PD5
MTIC5W/
MTIOC8C/POE10#
SDHI_CLK-B/ IRQ5
QSPCLK-B
AN102
53
PD4
MTIOC8B/POE11#
SDHI_CMD-B/ IRQ4
QSSL-B
AN103
54
PD3
MTIOC8D/POE8#/
TOC2
SDHI_D3-B/
QIO3-B
IRQ3
AN104
55
PD2
MTIOC4D/TIC2
SDHI_D2-B/
QIO2-B
IRQ2
AN105
56
P43
IRQ11-DS
AN003
57
P42
IRQ10-DS
AN002
58
P41
IRQ9-DS
AN001
P40
IRQ8-DS
AN000
P05
IRQ13
59
VREFL0
60
61
VREFH0
62
AVCC0
63
AVSS0
64
Others
(CTSU,
Tamper
detection)
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 76 of 178
RX671 Group
1.6.8
1. Overview
48-Pin HWQFN
Table 1.12
List of Pin and Pin Functions (48-Pin HWQFN) (1/3)
Pin No.
Timer
48-Pin
HWQFN
Power Supply
Clock
System
Control
I/O Port
1
EMLE
2
MD/FINED
3
RES#
4
XTAL
5
VSS
(MTU, TPU, TMR,
CMTW, POE,
CAC)
Communication
(SCI, RSCI, RSPI,
RSPIA, RIIC,
RIICHS, SSIE,
REMC)
(QSPIX,
SDHI)
Interrupt
Others
(CTSU)
A/D
P37
6
EXTAL
7
VCC
P36
8
UPSEL
P35
9
TRST#
P34
MTIOC0A/TMCI3/
POE10#
10
TMS
P31
MTIOC4D/TMCI2
CTS1#/RTS1#/
SS1#/SSLB0-A
IRQ1-DS
11
TDI
P30
MTIOC4B/TMRI3/
POE8#
RXD1/SMISO1/
SSCL1/MISOB-A
IRQ0-DS
NMI
IRQ4
TS0
12
TCK
P27
MTIOC2B/TMCI3
SCK1/RSPCKB-A
IRQ7
TS2
13
TDO
P26
MTIOC2A/TMO1
TXD1/CTS3#/
RTS3#/SMOSI1/
SS3#/SSDA1/
MOSIB-A
IRQ6
TS3
14
P17
MTIOC3A/
SCK1/TXD3/
MTIOC3B/
SMOSI3/SSDA3/
MTIOC4B/TIOCB0/ SDA2-DS/SSITXD0
TCLKD/TMO1/
POE8#
15
P16
16
17
18
VCC
19
VSS
20
21
22
IRQ7
ADTRG1#
MTIOC3C/
TXD1/RXD3/
MTIOC3D/TIOCB1/ SMOSI1/SMISO3/
TCLKC/TMO2
SSDA1/SSCL3/
SCL2-DS
IRQ6
ADTRG0#
P13
MTIOC0B/TIOCA5/ TXD2/SMOSI2/
TMO3
SSDA2/SDA0[FM+]/
SDAHS0[FM+/HS]
IRQ3
ADTRG1#
P12
TMCI1/MTIC5U
RXD2/SMISO2/
SSCL2/SCL0[FM+]/
SCLHS0[FM+/HS]
IRQ2
P53
UB
SDHI_D3-C
SSIRXD0/PMC0-DS
IRQ3
PC7
MTIOC3A/
MTCLKB/TMO2/
TOC0/CACREF
TXD8/SMOSI8/
SSDA8/SMOSI10/
SSDA10/TXD10/
MISOA-A/SSITXD0/
SMOSI010/
SSDA010/TXD010/
MISO0-A
IRQ14
PC6
MTIOC3C/
MTCLKA/TMCI2/
TIC0
RXD8/SMISO8/
SSCL8/SMISO10/
SSCL10/RXD10/
MOSIA-A/
SSILRCK0/
SMISO010/
SSCL010/RXD010/
MOSI0-A
IRQ13
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
TS12
TS13
Page 77 of 178
RX671 Group
Table 1.12
1. Overview
List of Pin and Pin Functions (48-Pin HWQFN) (2/3)
Pin No.
48-Pin
HWQFN
Timer
Power Supply
Clock
System
Control
I/O Port
(MTU, TPU, TMR,
CMTW, POE,
CAC)
Communication
(SCI, RSCI, RSPI,
RSPIA, RIIC,
RIICHS, SSIE,
REMC)
(QSPIX,
SDHI)
Interrupt
A/D
Others
(CTSU)
23
PC5
MTIOC3B/
MTCLKD/TMRI2
SCK8/SCK10/
RSPCKA-A/
SSIBCK0/SCK010/
RSPCK0-A
IRQ5
TS14
24
PC4
MTIOC3D/
MTCLKC/TMCI1/
POE0#
SCK5/CTS8#/
SDHI_D1-A/
RTS8#/SS8#/SS10#/ QIO1-A
CTS10#/RTS10#/
SSLA0-A/
AUDIO_CLK/
SS010#/CTS010#/
RTS010#/DE010/
SSL00-A
IRQ12
TSCAP
25
PB7
MTIOC3B/TIOCB5 TXD9/SMOSI9/
SSDA9/SMOSI11/
SSDA11/TXD11/
SMOSI011/
SSDA011/TXD011
IRQ15
26
PB6
MTIOC3D/TIOCA5 RXD9/SMISO9/
SSCL9/SMISO11/
SSCL11/RXD11/
SMISO011/
SSCL011/RXD011
IRQ6
27
PB5
MTIOC2A/
SCK9/SCK11/
MTIOC1B/TIOCB4/ SCK011
TMRI1/POE4#
IRQ13
31
PA6
MTIC5V/MTCLKB/ CTS5#/RTS5#/
TIOCA2/TMCI3/
SS5#/MOSIA-B/
POE10#
MOSI0-B/CTS12#/
RTS12#/SS12#
IRQ14
32
PA4
MTIC5U/MTCLKA/ TXD5/SMOSI5/
TIOCA1/TMRI0
SSDA5/SSLA0-B/
SSL00-B/TXD12/
SMOSI12/SSDA12/
TXDX12/SIOX12
IRQ5-DS
33
PA2
MTIOC7A
34
PA1
35
28
VCC
29
VSS
30
VCL
SDHI_WP
IRQ10
MTIOC0B/
SCK5/SSLA2-B/
MTCLKC/
SSL02-B/SCK12
MTIOC7B/TIOCB0
SDHI_CD
IRQ11
PE7
MTIOC6A/TOC1
MISOB-B
SDHI_WP/
SDHI_D1-B/
QIO1-B
IRQ7
36
PE6
MTIOC6C/TIC1
MOSIB-B
SDHI_CD/
SDHI_D0-B/
QIO0-B
IRQ6
37
PD5
MTIC5W/
MTIOC8C/POE10#
SDHI_CLK-B/ IRQ5
QSPCLK-B
AN102
38
PD4
MTIOC8B/POE11#
SDHI_CMD-B/ IRQ4
QSSL-B
AN103
39
PD3
MTIOC8D/POE8#/
TOC2
SDHI_D3-B/
QIO3-B
AN104
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
RXD5/SMISO5/
SSCL5/SSLA3-B/
SSL03-B/RXD12/
SMISO12/SSCL12/
RXDX12
IRQ3
Page 78 of 178
RX671 Group
Table 1.12
1. Overview
List of Pin and Pin Functions (48-Pin HWQFN) (3/3)
Pin No.
48-Pin
HWQFN
Timer
Power Supply
Clock
System
Control
I/O Port
40
PD2
(MTU, TPU, TMR,
CMTW, POE,
CAC)
MTIOC4D/TIC2
Communication
(SCI, RSCI, RSPI,
RSPIA, RIIC,
RIICHS, SSIE,
REMC)
(QSPIX,
SDHI)
SDHI_D2-B/
QIO2-B
Interrupt
A/D
IRQ2
AN105
41
P43
IRQ11-DS
AN003
42
P42
IRQ10-DS
AN002
43
P41
IRQ9-DS
AN001
P40
IRQ8-DS
AN000
44
Others
(CTSU)
VREFL0
45
46
VREFH0
47
AVCC0/
AVCC1
48
AVSS0/AVSS1
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 79 of 178
RX671 Group
2. Electrical Characteristics
2.
Electrical Characteristics
2.1
Absolute Maximum Ratings
Table 2.1
Absolute Maximum Rating
Conditions: VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V
Item
Power supply voltage
VBATT power supply voltage
Analog power supply voltage
Reference power supply voltage
Input voltage
Ports for 5 V tolerant: P12 to P17, P20,
P21, P30 to P33, P67, P73, PC0 to
PC3, and PJ3
Symbol
Value
Unit
VCC, VCC_USB
–0.3 to +4.0
V
VBATT
–0.3 to +4.0
V
AVCC1*1
–0.3 to +4.0
V
VREFH0
–0.3 to AVCC0 + 0.3 (up to 4.0)
V
Vin
–0.3 to VCC + 4.0 (up to 5.8)
V
AVCC0,
–0.3 to +4.0
TAMPI0 to TAMPI2,
RTCIC0 to RTCIC2, EXCIN*2
Port for 5 V tolerant: P07
–0.3 to AVCC0 + 4.0 (up to 5.8)
P03, P05, P40 to P47
–0.3 to AVCC0 + 0.3 (up to 4.0)
Other than above
–0.3 to VCC + 0.3 (up to 4.0)
Junction temperature
Tj
–40 to +125
°C
Storage temperature
Tstg
–55 to +125
°C
Caution: Permanent damage to the LSI may result if absolute maximum ratings are exceeded.
Note 1. Connect the AVCC0, AVCC1, and VCC_USB pins to VCC, and the AVSS0, AVSS1, and VSS_USB pins to VSS.
When the A/D converter unit 0 is not to be used, connect the VREFH0 pin to VCC and the VREFL0 pin to VSS, respectively.
Do not leave these pins open. Insert capacitors of high frequency characteristics between the AVCC0 and AVSS0 pins, or
AVCC1 and AVSS1 pins. Place capacitors of about 0.1 µF as close as possible to every power supply pin and use the shortest
and heaviest possible traces.
Note 2. The listed values apply when pins P30, P31, and P32 are set for the TAMPIn or RTCICn (n = 0 to 2) functions, and pin PJ3 is set
for the EXCIN function.
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 80 of 178
RX671 Group
2.2
2. Electrical Characteristics
Recommended Operating Conditions
Table 2.2
Recommended Operating Conditions (1)
Item
Symbol
Min.
Typ.
Max.
Unit
VCC
2.7
—
3.6
V
VSS
—
0
—
VBATT power supply voltage
VBATT
1.62*2
—
3.6
V
USB power supply voltage
VCC_USB
—
VCC
—
V
VSS_USB
—
0
—
AVCC0
—
VCC
—
Power supply
voltage*1
Analog power supply voltage*1, *3
Input voltage
Ports for 5 V tolerant: P12 to P17, P20,
P21, P30 to P33, P67, P73, PC0 to PC3,
and PJ3
AVSS0
—
0
—
AVCC1
—
VCC
—
V
AVSS1
—
0
—
VREFH0
2.7
—
AVCC0
VREFL0
—
0
—
Vin
–0.3
—
VCC + 3.6 (up to 5.5)
–0.3
—
3.9
TAMPI0 to TAMPI2, RTCIC0 to RTCIC2,
EXCIN*4
SCLHS0, SDAHS0*5
–0.3
—
VCC + 0.3
Port for 5 V tolerant: P07
–0.3
—
AVCC0 + 3.6 (up to 5.5)
P03, P05, P40 to P47
–0.3
—
AVCC0 + 0.3
–0.3
—
VCC + 0.3
–40
—
85
–40
—
105
–40
—
105
–40
—
125
Other than above
Operating
temperature
D version
Junction
temperature
D version
Topr
G version
G version
Tj
V
°C
°C
Note 1.
Note 2.
Note 3.
Note 4.
Comply with the following potential condition: VCC = AVCC0 = AVCC1 = VCC_USB
The low CL crystal unit cannot be used when the VBATT voltage is less than 2.0 V.
For details, see section 50.6.11, Voltage Range of Analog Power Supply Pins in the User’s Manual: Hardware.
The listed values apply when pins P30, P31, and P32 are set for the TAMPIn or RTCICn (n = 0 to 2) functions, and pin PJ3 is set
for the EXCIN function.
Note 5. The listed values apply when pins P12 and P13 are respectively set for the SCLHS0 and SDAHS0 functions in Hs-mode of the
RIICHS.
Table 2.3
Recommended Operating Conditions (2)
Item
Decoupling capacitance to stabilize the internal voltage
Symbol
Value
CVCL
0.22 μF ± 30%*1
Note 1. Use a multilayer ceramic capacitor whose nominal capacitance is 0.22 μF and a capacitance tolerance is ±30% or better.
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 81 of 178
RX671 Group
2.3
2. Electrical Characteristics
DC Characteristics
Table 2.4
DC Characteristics (1)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Schmitt trigger
input voltage
IRQ input pin*1
MTU input pin*1
POE3 input pin*1
TPU input pin*1
TMR input pin*1
CMTW input pin*1
SCI input pin*1
RSCIA input pin*1
CAN input pin*1
CAC input pin*1
ADTRG# input pin*1
QSPIX input pin*1
SSIE input pin*1
REMC input pin*1
RES#, NMI, TCK
RIIC input pin
RIICHS input pin
(except for SMBus)
Symbol
Min.
Typ.
Max.
Unit
VIH
0.8 × VCC
—
—
V
VIL
—
—
0.2 × VCC
ΔVT
0.06 × VCC
—
—
VIH
0.7 × VCC
—
—
VIL
—
—
0.3 × VCC
ΔVT
0.05 × VCC
—
—
TAMPIn/RTCICn pin
EXCIN pin
VIH
0.8 × VBKP
—
—
VIL
—
—
0.2 × VBKP
Ports for 5 V tolerant*2
VIH
0.8 × VCC
—
—
VIL
—
—
0.2 × VCC
Other input pins excluding ports
for 5 V tolerant
VIH
0.8 × VCC
—
—
VIL
—
—
0.2 × VCC
VIH
0.9 × VCC
—
—
0.8 × VCC
—
—
0.7 × VCC
—
—
2.1
—
—
—
—
0.1 × VCC
—
—
0.2 × VCC
High level input
MD pin, EMLE
voltage
EXTAL, RSPI input pin,
(except for Schmitt
RSPIA input pin,
trigger input pin)
EXDMAC input pin, WAIT#,
SDHI input pin
D0 to D15
RIIC, RIICHS (SMBus)
Low level input
MD pin, EMLE
voltage
EXTAL, RSPI input pin,
(except for Schmitt
RSPIA input pin,
trigger input pin)
EXDMAC input pin, WAIT#,
SDHI input pin
VIL
D0 to D15
—
—
0.3 × VCC
RIIC, RIICHS (SMBus)
—
—
0.8
Test
Conditions
V
V
Note 1. This does not include the pins, which are multiplexed as ports for 5 V tolerant.
Note 2. P07, P12 to P17, P20, P21, P30 to P33, P67, P73, PC0 to PC3, and PJ3 are 5 V tolerant.
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 82 of 178
RX671 Group
Table 2.5
2. Electrical Characteristics
DC Characteristics (2)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Output high voltage
All output pins
VOH
VCC – 0.5
—
—
V
IOH = –1 mA
Output low voltage
All output pins
(except for RIIC0 to RIIC2 pins
and RIICHS0 pin)
VOL
—
—
0.5
V
IOL = 1.0 mA
RIIC0 to RIIC2 output pin
RIICHS0 output pin
—
—
0.4
—
—
0.6
IOL = 6.0 mA
RIIC0 output pin
RIICHS0 output pin
—
—
0.4
IOL = 15.0 mA
(ICFER.FMPE = 1)
—
0.4
—
IOL = 20.0 mA
(ICFER.FMPE = 1)
—
—
0.4
IOL = 3.0 mA
(ICFER.HSME = 1)
| Iin |
—
—
1.0
µA
Vin = 0 V
Vin = VCC
| ITSI |
—
—
1.0
µA
Vin = 0 V
Vin = VCC
—
—
5.0
RIICHS0 output pin
Input leakage current
RES#, MD pin, EMLE*1,
BSCANP*1, NMI
Three-state leakage
current (off state)
Other than ports for 5 V tolerant
Ports for 5 V tolerant
IOL = 3.0 mA
Vin = 0 V
Vin = 5.5 V
Input pull-up resistor
Other than P35
RPU
10
—
100
kΩ
Vin = 0 V
Input pull-down
resistor
EMLE, BSCANP
RPD
10
—
100
kΩ
Vin = VCC
Pull-up current serving SCLHS0 pin (P12)
as the SCLHS0 current
source
ICS
3
—
12
mA
VCC = 3.0 to 3.6 V
Vin = 0.3 × VCC to
0.7 × VCC
Input capacitance
Cin
—
—
8
pF
Vbias = 0 V
Vamp = 20 mV
f = 1 MHz
Ta = 25°C
—
—
16
All input pins
(except for P12, P13, P16, P17,
P20, P21, EMLE, BSCANP,
USB0_DP, USB0_DM,
USB1_DP and USB1_DM)
P12, P13, P16, P17, P20, P21,
EMLE, BSCANP, USB0_DP,
USB0_DM, USB1_DP and
USB1_DM
Power supply voltage in the backup domain
Output voltage of the VCL pin
VBKP
VCL
—
VCC
—
—
VBATT
—
—
1.18
—
V
VCC ≥ VDETBATT
VCC < VDETBATT
V
Note 1. The input leakage current value at the EMLE and BSCANP pins are only when Vin = 0 V.
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 83 of 178
RX671 Group
Table 2.6
2. Electrical Characteristics
DC Characteristics (3)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Symbol
Full operation*2
High-speed operating mode
Supply
current*1
ICC*3
D version
Typ.
Max.
G version
Typ.
Max.
—
55
—
68
Normal
Peripheral module clocks are supplied
operation *4
23
—
23
—
Peripheral module clocks are stopped
*4, *5
13
—
13
—
Peripheral module clocks are stopped
*4, *5
14.5
—
14.5
—
Sleep mode: Peripheral module clocks are
supplied*4
20
38
20
51
All module clock stop mode (reference value)
9
26
9
39
Reading from the code flash
memory while the data flash
memory is being
programmed
6
—
6
—
Reading from the code flash
memory while the code flash
memory is being
programmed
7
—
7
—
Core
Mark
Increased by BGO
operation*8
Increased by Trusted Secure IP operation
Unit
Test Conditions
mA
ICLK = 120 MHz,
PCLKA = 120 MHz,
PCLKB = 60 MHz,
PCLKC = 60 MHz,
PCLKD = 60 MHz,
FCLK = 60 MHz,
BCLK = 120 MHz,
BCLK pin = 60 MHz
—
15
—
15
Low-speed operating mode 1: Peripheral module
clocks are stopped*4
1.6
—
1.6
—
All clocks 1 MHz
Low-speed operating mode 2: Peripheral module
clocks are stopped*4
1.6
—
1.6
—
All clocks 32.768
kHz
Deep software standby mode
Software standby mode
1.1
18
1.1
27
Power is supplied to the standby RAM, USB
resume detecting unit (USB0 only) and REMC
15.5
69
15.5
85
Power is not
supplied to the
standby RAM,
USB resume
detecting unit
(USB0 only) and
REMC
Low power consumption
function of the power-on
reset circuit is disabled*6
11.5
42
11.5
54
Low power consumption
function of the power-on
reset circuit is enabled*7
4.9
32
4.9
47
When a low CL crystal is in
use
1
—
1
—
When a standard CL crystal
is in use
2
—
2
—
External clock (32 kHz) input
0.1
—
0.1
—
When a standard CL crystal
is in use
1.4
—
1.4
—
When a low CL crystal is in
use
0.9
—
0.9
—
VBATT = 2.0 V,
VCC = 0 V
1.6
—
1.6
—
VBATT = 3.3 V,
VCC = 0 V
1.6
—
1.6
—
VBATT = 1.62 V,
VCC = 0 V
1.7
—
1.7
—
VBATT = 2.0 V,
VCC = 0 V
3.3
—
3.3
—
VBATT = 3.3 V,
VCC = 0 V
Increase current
by operating RTC
Increase current
by operating
REMC
When the RTC is
operating while VCC is
not supplied (Only the
RTC and sub-clock
oscillator operate with
the battery backup
function)
Inrush current on
release from deep
software standby mode
When a standard CL crystal
is in use
µA
Inrush current*9
IRUSH
—
130
—
130
mA
Total inrush current*9
ERUSH
—
1
—
1
µC
Note 1. Supply current values are measured when all output pins are unloaded and all input pull-up resistors are disabled.
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 84 of 178
RX671 Group
2. Electrical Characteristics
Note 2. Peripheral module clocks are supplied.
Note 3. ICC depends on the f (ICLK) as follows (when ICLK/PCLKA : PCLKB/PCLKC/PCLKD : BCLK : BCLK pin = 2 : 1 : 2 : 1 and
EXTAL = 12 MHz).
• D version
ICC max = 0.28 × f + 21.0 (full operation in high-speed operating mode)
ICC typ = 0.16 × f + 3.5 (normal operation in high-speed operating mode)
ICC typ = 0.20 × f + 1.4 (ICLK 1 MHz max) (low-speed operating mode 1)
ICC max = 0.14 × f + 21.0 (sleep mode)
• G version
ICC max = 0.31 × f + 30.0 (full operation in high-speed operating mode)
ICC typ = 0.16 × f + 3.5 (normal operation in high-speed operating mode)
ICC typ = 0.20 × f + 1.4 (ICLK 1 MHz max) (low-speed operating mode 1)
ICC max = 0.17 × f + 30.0 (sleep mode)
Note 4. Whether the peripheral module clocks are supplied or stopped is controlled only by the bit settings in the module stop control
registers A to D.
Note 5. When the peripheral module clock is stopped, the settings of the clock frequency are as follows:
ICLK = 120 MHz and PCLKA = PCLKB = PCLKC = PCLKD = FCLK = BCLK = BCLK pin = 3.75 MHz (divided by 64).
Note 6. When the low power consumption function is disabled, the DEEPCUT[1:0] bits are set to 01b.
Note 7. When the low power consumption function is enabled, the DEEPCUT[1:0] bits are set to 11b.
Note 8. These are the increases during programming of the code flash memory after the code flash memory (limitations apply to the
combinations of address ranges of the program area and the readable area) or the data flash memory has been programmed or
erased.
Note 9. Reference value
Table 2.7
DC Characteristics (4)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Symbol
G version
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
IAVCC0
—
0.8
1
—
0.8
1
mA
IAVCC1
—
0.6
1
—
0.6
1
mA
—
0.7
1.1
—
0.7
1.1
—
0.9
1.4
—
0.9
1.4
mA
—
1.4
6.7
—
1.4
9.0
µA
—
38
60
—
38
60
µA
Waiting for 12-bit A/D conversion
(unit 0)
—
0.07
0.5
—
0.07
0.6
12-bit A/D converter in module stop
status (unit 0)
—
0.07
0.4
—
0.07
0.5
During 12-bit A/D conversion (unit 0)
Analog
power
During 12-bit A/D conversion (unit 1)
supply
current*1, *2 During 12-bit A/D conversion (unit 1)
+ temperature sensor
Waiting for A/D and temperature
sensor conversion (all units)
IAVCC
A/D and temperature sensor are in
standby mode (all units)
Reference
power
supply
current
D version
During 12-bit A/D conversion (unit 0)
USB operating current
(increase per channel)
IVREFH0
Low speed
ICCUSBLS
—
3.7
6.5
—
3.7
6.5
mA
Full speed
ICCUSBFS
—
4.2
10
—
4.2
10
mA
CTSU operating current
ICTSU
—
100
—
—
100
—
µA
RAM retension voltage
VRAM
2.7
—
—
2.7
—
—
V
SrVCC
8.4
—
20000
8.4
—
SfVCC
8.4
—
—
8.4
—
VCC rising gradient
VCC falling
gradient*3
Test Conditions
IAVCC = IAVCC0 +
IAVCC1
20000 µs/V
—
µs/V
Note 1. The reference power supply current is included in the power supply current value for 12-bit A/D converter (unit 1).
Note 2. The analog power supply current cannot be separated into IAVCC0 and IAVCC1 in the 48-pin products because AVCC0 and
AVCC1 share the same pin.
Note 3. This applies when VBATT is used.
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 85 of 178
RX671 Group
Table 2.8
2. Electrical Characteristics
Permissible Output Currents
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Permissible output low current
(average value per pin)
Permissible output low current
(max. value per pin)
pins*1
Max.
Unit
IOL
mA
—
—
2.0
—
—
3.8
All output pins*3
High-speed interface
high-drive
—
—
7.5
All output pins*1
Normal drive
—
—
4.0
All output
pins*2
Permissible output low current (total)
Total of all output pins
Permissible output high current
(average value per pin)
All output pins*1
Permissible output high current (total)
Typ.
High drive
All output pins*3
Permissible output high current
(max. value per pin)
Min.
All output pins*2
All output
Normal drive
Symbol
IOL
High drive
—
—
7.6
High-speed interface
high-drive
—
—
15
ΣIOL
—
—
80
mA
IOH
—
—
–2.0
mA
Normal drive
All output
pins*2
High drive
—
—
–3.8
All output
pins*3
High-speed interface
high-drive
—
—
–7.5
All output pins*1
Normal drive
—
—
–4.0
All output pins*2
High drive
—
—
–7.6
All output pins*3
High-speed interface
high-drive
—
—
–15
—
—
–80
Total of all output pins
mA
IOH
ΣIOH
mA
mA
Caution: To protect the LSI’s reliability, the output current values should not exceed the values in this table.
Note 1. This is the value when normal driving ability is set with a pin for which normal driving ability is selectable.
Note 2. This is the value when high driving ability is set with a pin for which normal driving ability is selectable or the value of the pin to
which high driving ability is fixed.
Note 3. This is the value when high-speed interface high-driving ability is set with a pin for which high-speed interface high-driving ability
is selectable.
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 86 of 178
RX671 Group
Table 2.9
2. Electrical Characteristics
Normal Output Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = 25°C
Item
Output high
level voltage
Output low
level voltage
Normal drive
(P00 to P02, P12 to P14, P27, P36, P40 to P47,
P50 to P52, P54 to P56, P72, P74 to P77,
P80 to P83, P90 to P93, PA0 to PA7,
PB0 to PB7, PC0 to PC7, PD0 to PD7,
PE0 to PE7, PH1, PH2)
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
V
IOH = –0.5 mA
—
3.26
—
—
3.22
—
IOH = –1.0 mA
—
3.13
—
IOH = –2.0 mA
—
2.94
—
IOH = –4.0 mA
High drive
(P00 to P02, P03, P05, P07, P12 to P17,
P20 to P27, P30 to P34, P37,
P50 to P56, P60 to P67, P70 to P77,
P80 to P83, P86, P87, P90 to P93,
PA0 to PA7, PB0 to PB7, PC0 to PC7,
PD0 to PD7, PE0 to PE7, PF5,
PH1, PH2, PJ3, PJ5)
—
3.28
—
IOH = –0.5 mA
—
3.25
—
IOH = –1.0 mA
—
3.20
—
IOH = –2.0 mA
—
3.10
—
IOH = –4.0 mA
Highs-peed interface high-drive
(P00 to P02, P12 to P14, P17,
P20 to P23, P27, P30, P31,
P50 to P56, P70, P72, P73 to P77,
P80 to P83, P86, P87, P90 to P93,
PA0 to PA7, PB0 to PB7, PC0 to PC7,
PD0 to PD7, PE0 to PE7, PH1, PH2)
—
3.29
—
IOH = –0.5 mA
—
3.28
—
IOH = –1.0 mA
—
3.25
—
IOH = –2.0 mA
—
3.20
—
IOH = –4.0 mA
—
3.18
—
IOH = –5.0 mA
—
0.04
—
IOL = 0.5 mA
—
0.09
—
IOL = 1.0 mA
—
0.18
—
IOL = 2.0 mA
—
0.39
—
IOL = 4.0 mA
High drive
(P00 to P02, P03, P05, P07, P12 to P17,
P20 to P27, P30 to P34, P37,
P50 to P56, P60 to P67, P70 to P77,
P80 to P83, P86, P87, P90 to P93,
PA0 to PA7, PB0 to PB7, PC0 to PC7,
PD0 to PD7, PE0 to PE7, PF5,
PH1, PH2, PJ3, PJ5)
—
0.02
—
IOL = 0.5 mA
—
0.04
—
IOL = 1.0 mA
—
0.09
—
IOL = 2.0 mA
—
0.18
—
IOL = 4.0 mA
Highs-peed interface high-drive
(P00 to P02, P12 to P14, P17,
P20 to P23, P27, P30, P31,
P50 to P56, P70, P72, P73 to P77,
P80 to P83, P86, P87, P90 to P93,
PA0 to PA7, PB0 to PB7, PC0 to PC7,
PD0 to PD7, PE0 to PE7, PH1, PH2)
—
0.01
—
IOL = 0.5 mA
—
0.02
—
IOL = 1.0 mA
—
0.04
—
IOL = 2.0 mA
—
0.09
—
IOL = 4.0 mA
—
0.11
—
IOL = 5.0 mA
—
0.23
—
IOL = 10.0 mA
—
0.36
—
IOL = 15.0 mA
Normal drive
(P00 to P02, P12 to P14, P27, P36, P40 to P47,
P50 to P52, P54 to P56, P72, P74 to P77,
P80 to P83, P90 to P93, PA0 to PA7,
PB0 to PB7, PC0 to PC7, PD0 to PD7,
PE0 to PE7, PH1, PH2)
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
VOH
VOL
Page 87 of 178
RX671 Group
Table 2.10
2. Electrical Characteristics
Thermal Resistance Value (Reference)
Item
Thermal resistance
Package
144-pin LFQFP (PLQP0144KA-B)
Symbol
θja
100-pin LFQFP (PLQP0100KB-B)
Max.
Unit
48.4
°C/W
51.7
64-pin LFQFP (PLQP0064KB-C)
51.2
145-pin TFLGA (PTLG0145JC-A)
30.9
145-pin TFLGA (PTLG0145KB-A)
30.6
100-pin TFLGA (PTLG0100JB-A)
30.9
64-pin TFBGA (PTBG0064KB-A)
32.0
100-pin LFQFP (PLQP0100KB-B)
64-pin LFQFP (PLQP0064KB-C)
48-pin HWQFN (PWQN0048KC-A)
JESD51-2 and
JESD51-7 compliant
19.1*1
48-pin HWQFN (PWQN0048KC-A)
144-pin LFQFP (PLQP0144KA-B)
Test Conditions
Ψjt
1.2
1.2
JESD51-2 and
JESD51-9 compliant
°C/W
JESD51-2 and
JESD51-7 compliant
1.2
0.1*1
145-pin TFLGA (PTLG0145JC-A)
0.4
145-pin TFLGA (PTLG0145KB-A)
0.4
100-pin TFLGA (PTLG0100JB-A)
0.4
64-pin TFBGA (PTBG0064KB-A)
0.4
JESD51-2 and
JESD51-9 compliant
Note:
The values are reference values when the 4-layer board is used. Thermal resistance depends on the number of layers or size of
the board. For details, refer to the JEDEC standards.
Note 1. This value applies when the exposed die pad for this purpose is connected to VSS.
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 88 of 178
RX671 Group
2.4
2. Electrical Characteristics
AC Characteristics
Table 2.11
Operating Frequency (High-Speed Operating Mode)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Operating
frequency
System clock (ICLK)
Symbol
Min.
Typ.
Max.
Unit
f
MHz
—
—
120
Peripheral module clock (PCLKA)
—
—
120
Peripheral module clock (PCLKB)
—
—
60
Peripheral module clock (PCLKC)
—
—
60
Peripheral module clock (PCLKD)
—
—
60
—*1
—
60
Package of 144 pins or more
—
—
120
100-pin package
—
—
60
BCLK pin output
Package of 144 pins or more
—
—
60
100-pin package
—
—
30
SDRAM clock (SDCLK)
Package of 144 pins or more
—
—
60
SDCLK pin output
Package of 144 pins or more
—
—
60
Flash-IF clock (FCLK)
External bus clock (BCLK)
Note 1. The FCLK must run at a frequency of at least 4 MHz when changing the flash memory contents.
Table 2.12
Operating Frequency (Low-Speed Operating Mode 1)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Operating
frequency
Symbol
Min.
Typ.
Max.
Unit
f
—
—
1
MHz
Peripheral module clock (PCLKA)
—
—
1
Peripheral module clock (PCLKB)
—
—
1
Peripheral module clock (PCLKC)*1
—
—
1
Peripheral module clock (PCLKD)*1
—
—
1
System clock (ICLK)
Flash-IF clock (FCLK)
—
—
1
Package of 144 pins or more
—
—
1
100-pin package
—
—
1
Package of 144 pins or more
—
—
1
100-pin package
—
—
1
SDRAM clock (SDCLK)
Package of 144 pins or more
—
—
1
SDCLK pin output
Package of 144 pins or more
—
—
1
External bus clock (BCLK)
BCLK pin output
Note 1. When the 12-bit A/D converter is used, the frequency must be set to at least 1 MHz.
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Apr 15, 2022
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RX671 Group
Table 2.13
2. Electrical Characteristics
Operating Frequency (Low-Speed Operating Mode 2)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Operating
frequency
System clock (ICLK)
Symbol
Min.
Typ.
Max.
Unit
f
kHz
32
—
264
Peripheral module clock (PCLKA)
—
—
264
Peripheral module clock (PCLKB)
—
—
264
(PCLKC)*1
—
—
264
Peripheral module clock (PCLKD)*1
—
—
264
Flash-IF clock (FCLK)
32
—
264
Package of 144 pins or more
—
—
264
100-pin package
—
—
264
BCLK pin output
Package of 144 pins or more
—
—
264
100-pin package
—
—
264
SDRAM clock (SDCLK)
Package of 144 pins or more
—
—
264
SDCLK pin output
Package of 144 pins or more
—
—
264
Peripheral module clock
External bus clock (BCLK)
Note 1. The 12-bit A/D converter cannot be used.
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Apr 15, 2022
Page 90 of 178
RX671 Group
2. Electrical Characteristics
2.4.1
Reset Timing
Table 2.14
Reset Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Test
Conditions
Symbol
Min.
Typ.
Max.
Unit
Power-on
tRESWP
1
—
—
ms
Figure 2.1
Deep software standby mode
tRESWD
0.6
—
—
ms
Figure 2.2
Software standby mode, low-speed operating
mode 2
tRESWS
0.3
—
—
ms
Programming or erasure of the code flash
memory, or programming, erasure or blank
checking of the data flash memory
tRESWF
200
—
—
µs
Other than above
tRESW
200
—
—
µs
Waiting time after release from the RES# pin reset
tRESWT
54
—
55
tLcyc
Internal reset time
(independent watchdog timer reset, watchdog timer reset,
software reset)
tRESW2
100
—
108
tLcyc
RES# pulse
width
Figure 2.1
VCC
RES#
tRESWP
Internal reset signal
(Low is valid)
tRESWT
Figure 2.1
Reset Input Timing at Power-On
tRESWD, tRESWS, tRESWF, tRESW
RES#
Internal reset signal
(Low is valid)
tRESWT
Figure 2.2
Reset Input Timing
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Apr 15, 2022
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RX671 Group
2. Electrical Characteristics
2.4.2
Clock Timing
Table 2.15
BCLK Pin Output, SDCLK Pin Output Clock Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
BCLK pin output cycle time
Package of 144 pins or more
Symbol
Min.
Typ.
Max.
Unit
tBcyc
16.6
—
—
ns
33.2
—
—
100-pin package
BCLK pin output high pulse width
tCH
3.3
—
—
ns
BCLK pin output low pulse width
tCL
3.3
—
—
ns
BCLK pin output rising time
tCr
—
—
5
ns
tCf
—
—
5
ns
tBcyc
16.6
—
—
ns
BCLK pin output falling time
SDCLK pin output cycle time
Package of 144 pins or more
SDCLK pin output high pulse width
tCH
3.3
—
—
ns
SDCLK pin output low pulse width
tCL
3.3
—
—
ns
SDCLK pin output rising time
tCr
—
—
5
ns
SDCLK pin output falling time
tCf
—
—
5
ns
Test
Conditions
Figure 2.3
tBcyc, tSDcyc
tCH
tCf
BCLK pin output, SDCLK pin output
tCL
tCr
Test conditions: VOH = 0.7 × VCC, VOL = 0.3 × VCC, C = 30 pF
Figure 2.3
BCLK Pin and SDCLK Pin Output Timing
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Apr 15, 2022
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RX671 Group
Table 2.16
2. Electrical Characteristics
EXTAL Clock Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
fEXMAIN ≤ 24MHz
Symbol
fEXMAIN > 24MHz
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
EXTAL external clock input cycle time
tEXcyc
41.66
—
—
33.33
—
—
ns
EXTAL external clock input frequency
fEXMAIN
—
—
24
—
—
30
MHz
EXTAL external clock input high pulse width
tEXH
15.83
—
—
13.33
—
—
ns
EXTAL external clock input low pulse width
tEXL
15.83
—
—
13.33
—
—
ns
EXTAL external clock rising time
tEXr
—
—
5
—
—
5
ns
EXTAL external clock falling time
tEXf
—
—
5
—
—
5
ns
Test
Conditions
Figure 2.4
tEXcyc
tEXH
tEXL
EXTAL external clock input
0.5 × VCC
tEXr
Figure 2.4
Table 2.17
tEXf
EXTAL External Clock Input Timing
Main Clock Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Symbol
Main clock oscillation frequency
Main clock oscillator stabilization time (crystal)
Main clock oscillation stabilization waiting time (crystal)
Min.
Typ.
fMAIN
8
tMAINOSC
—
tMAINOSCWT
—
Max.
Unit
—
24
MHz
—
—*1
ms
—
—*2
ms
Test
Conditions
Figure 2.5
Note 1. When using a main clock, ask the manufacturer of the oscillator to evaluate its oscillation. Refer to the results of evaluation
provided by the manufacturer for the oscillation stabilization time.
Note 2. The number of cycles selected by the value of the MOSCWTCR.MSTS[7:0] bits determines the main clock oscillation
stabilization waiting time in accord with the formula below.
tMAINOSCWT = [(MSTS[7:0] bits × 32) + 10] / fLOCO
MOSCCR.MOSTP
tMAINOSC
Main clock oscillator output
tMAINOSCWT
OSCOVFSR.MOOVF
Main clock
Figure 2.5
Main Clock Oscillation Start Timing
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Apr 15, 2022
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RX671 Group
Table 2.18
2. Electrical Characteristics
LOCO and IWDT-Dedicated Low-Speed Clock Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
LOCO clock cycle time
LOCO clock oscillation frequency
LOCO clock oscillation stabilization waiting time
Symbol
Min.
Typ.
Max.
Unit
tLcyc
3.78
4.16
4.63
µs
fLOCO
216 (–10%)
240
264 (+10%)
kHz
tLOCOWT
—
—
44
µs
IWDT-dedicated low-speed clock cycle time
tILcyc
7.57
8.33
9.26
µs
IWDT-dedicated low-speed clock oscillation
frequency
fILOCO
108 (–10%)
120
132 (+10%)
kHz
IWDT-dedicated low-speed clock oscillation
stabilization waiting time
tILOCOWT
—
142
190
µs
Test
Conditions
Figure 2.6
Figure 2.7
LOCOCR.LCSTP
On-chip oscillator output
tLOCOWT
LOCO clock
Figure 2.6
LOCO Clock Oscillation Start Timing
ILOCOCR.ILCSTP
IWDT-dedicated on-chip
oscillator output
tILOCOWT
OSCOVFSR.ILCOVF
IWDT-dedicated
low-speed clock
Figure 2.7
IWDT-dedicated Low-Speed Clock Oscillation Start Timing
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Apr 15, 2022
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RX671 Group
Table 2.19
2. Electrical Characteristics
HOCO Clock Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
fHOCO
15.616
(–2.40%)
16
16.384
(+2.40%)
MHz
17.568
(–2.40%)
18
18.432
(+2.40%)
19.520
(–2.40%)
20
20.480
(+2.40%)
15.520
(–3.00%)
16
16.480
(+3.00%)
17.460
(–3.00%)
18
18.540
(+3.00%)
19.400
(–3.00%)
20
20.600
(+3.00%)
15.960
(–0.25%)
16
16.040
(+0.25%)
17.955
(–0.25%)
18
18.045
(+0.25%)
19.950
(–0.25%)
20
20.050
(+0.25%)
tHOCOWT
—
105
149
HOCO clock power supply stabilization time
tHOCOP
—
—
FLL stabilization waiting time
tFLLWT
—
—
HOCO clock oscillation frequency
FLL not in use
FLL in use
HOCO clock oscillation stabilization waiting time
fHOCO
Test Conditions
–20°C ≤ Ta
Ta < –20°C
MHz
Sub-clock frequency
precision: ±50 ppm
µs
Figure 2.8
150
µs
Figure 2.9
1.8
ms
HOCOCR.HCSTP
High-speed on-chip
oscillator output
tHOCOWT
OSCOVFSR.HCOVF
HOCO clock
Figure 2.8
HOCO Clock Oscillation Start Timing (Oscillation is Started by Setting the
HOCOCR.HCSTP Bit)
HOCOPCR.HOCOPCNT
HOCOCR.HCSTP
tHOCOP
Internal power supply for
high-speed on-chip oscillator
Figure 2.9
High-Speed On-Chip Oscillator Power Supply Control Timing
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Apr 15, 2022
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RX671 Group
Table 2.20
2. Electrical Characteristics
PLL Clock Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
PLL clock oscillation frequency
PLL clock oscillation stabilization waiting time
Test
Conditions
Symbol
Min.
Typ.
Max.
Unit
fPLL
120
—
240
MHz
tPLLWT
—
259
320
µs
Figure 2.10
Test
Conditions
PLLCR2.PLLEN
PLL circuit output
tPLLWT
OSCOVFSR.PLOVF
PLL clock
Figure 2.10
Table 2.21
PLL Clock Oscillation Start Timing
Sub-Clock Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
When a low CL crystal resonator is in use: VBATT = 2.0 to 3.6 V,
When a standard CL crystal resonator is in use: VBATT = 1.62 to 3.6 V, Ta = Topr
Item
Sub-clock oscillation frequency
Sub-clock oscillation stabilization time
Sub-clock oscillation stabilization waiting time
Symbol
Min.
Typ.
Max.
Unit
fSUB
—
32.768
—
kHz
s
s
tSUBOSC
—
—
*1
tSUBOSCWT
—
—
*2
Figure 2.11
Note 1. When using a sub-clock, ask the manufacturer of the oscillator to evaluate its oscillation. Refer to the results of evaluation
provided by the manufacturer for the oscillation stabilization time.
Note 2. The number of cycles selected by the value of the SOSCWTCR.SSTS[7:0] bits determines the sub-clock oscillation stabilization
waiting time in accord with the formula below.
tSUBOSCWT = [(SSTS[7:0] bits × 16384) + 10] / fLOCO
SOSCCR.SOSTP
tSUBOSC
Sub-clock oscillator output
tSUBOSCWT
OSCOVFSR.SOOVF
Sub-clock
Figure 2.11
Sub-Clock Oscillation Start Timing
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Apr 15, 2022
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RX671 Group
Table 2.22
2. Electrical Characteristics
CLKOUT Pin Output Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr,
High-drive output is selected by the drive capacity control register
Item
CLKOUT pin output cycle time
CLKOUT pin output high pulse
width*1
Symbol
Min.
Typ.
Max.
Unit
tCcyc
25
—
—
ns
tCH
5
—
—
ns
CLKOUT pin output low pulse width*1
tCL
5
—
—
ns
CLKOUT pin output rising time
tCr
—
—
5
ns
CLKOUT pin output falling time
tCf
—
—
5
ns
Test
Conditions
Figure 2.12
tCcyc = 25 ns
Note 1. If the main clock oscillator is selected by the CLKOUT output source select bit (CKOCR.CKOSEL[2:0]) and the external clock
input is selected by the main clock oscillator switching bit (MOFCR.MOSEL), the pulse width depends on the input clock wave
form.
tCcyc
tCH
tCf
CLKOUT pin output
tCL
tCr
Test Conditions VOH = 0.7 × VCC, VOL = 0.3 × VCC, C = 30pF
Figure 2.12
CLKOUT Pin Output Timing
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Apr 15, 2022
Page 97 of 178
RX671 Group
2. Electrical Characteristics
2.4.3
Timing of Recovery from Low Power Consumption Modes
Table 2.23
Timing of Recovery from Low Power Consumption Modes (1)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Recovery time
from software
standby mode
*1
Crystal
resonator
connected to
main clock
oscillator
Symbol Min. Typ.
Main clock
oscillator
operating
tSBYMC
Main clock
oscillator and
PLL circuit
operating
tSBYSEQ*3
100 + 7 / fICLK +
2n / fMAIN
tSBYPC
{(MSTS[7:0] bit × 32)
+ 138} / 0.216
100 + 7 / fICLK +
2n / fPLL
tSBYEX
352
100 + 7 / fICLK +
2n / fEXMAIN
Main clock
oscillator and
PLL circuit
operating
tSBYPE
639
100 + 7 / fICLK +
2n / fPLL
Sub-clock oscillator operating
tSBYSC
{(SSTS[7:0] bit ×
16384) + 13} / 0.216
+ 10 / fFCLK
100 + 4 / fICLK +
2n / fSUE
High-speed
on-chip
oscillator
operating
tSBYHO
454
100 + 7 / fICLK +
2n / fHOCO
High-speed
on-chip
oscillator
operating and
PLL circuit
operating
tSBYPH
741
100 + 7 / fICLK +
2n / fPLL
tSBYLO
338
100 + 7 / fICLK +
2n / fLOCO
High-speed
on-chip
oscillator
operating
Low-speed on-chip oscillator
operating*4
—
tSBYOSCWT
{(MSTS[7:0] bit × 32)
+ 76} / 0.216
External clock Main clock
input to main
oscillator
clock oscillator operating
—
Max.
*2
Unit
Test
Conditions
µs
Figure 2.13
Note 1. The time for recovery from software standby mode is determined by the value obtained by adding the oscillation stabilization
waiting time (tSBYOSCWT) and the time required for operations by the software standby release sequencer (tSBYSEQ).
Note 2. When several oscillators were running before the transition to software standby, the greatest value of the oscillation stabilization
waiting time tSBYOSCWT is selected.
Note 3. For n, the greatest value is selected from among the internal clock division settings.
Note 4. This condition applies when fICLK:fFCLK = 1:1, 2:1, or 4:1.
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RX671 Group
2. Electrical Characteristics
Oscillator
(System clock)
tSBYOSCWT
tSBYSEQ
Oscillator
(Other than the system clock)
ICLK
IRQ
Software standby mode
tSBYMC, tSBYEX, tSBYPC, tSBYPE,
tSBYPH, tSBYSC, tSBYHO, tSBYLO
When stabilization of the system clock oscillator is slower
Oscillator
(System clock)
tSBYOSCWT
tSBYSEQ
Oscillator
(Other than the system clock)
tSBYOSCWT
ICLK
IRQ
Software standby mode
tSBYMC, tSBYEX, tSBYPC, tSBYPE,
tSBYPH, tSBYSC, tSBYHO, tSBYLO
When stabilization of an oscillator other than the system clock is slower
Figure 2.13
Software Standby Mode Recovery Timing
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Apr 15, 2022
Page 99 of 178
RX671 Group
Table 2.24
2. Electrical Characteristics
Timing of Recovery from Low Power Consumption Modes (2)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Recovery time from deep software standby mode
Waiting time after recovery from deep software standby mode
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
tDSBY
—
—
0.9
ms
Figure 2.14
tDSBYWT
23
—
24
tLcyc
Oscillator
IRQ
Deep software standby reset
(Low is valid)
Internal reset
(Low is valid)
Deep software standby mode
tDSBY
tDSBYWT
Reset exception handling start
Figure 2.14
Deep Software Standby Mode Recovery Timing
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Apr 15, 2022
Page 100 of 178
RX671 Group
2. Electrical Characteristics
2.4.4
Control Signal Timing
Table 2.25
Control Signal Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKB = 8 to 60 MHz, Ta = Topr
Item
Symbol
NMI pulse width
tNMIW
IRQ pulse width
tIRQW
Min.*1
Typ.
Max.
Unit
ns
200
—
—
tPBcyc × 2
—
—
200
—
—
tPBcyc × 2
—
—
Test Conditions*1
tPBcyc × 2 ≤ 200 ns, Figure 2.15
tPBcyc × 2 > 200 ns, Figure 2.15
ns
tPBcyc × 2 ≤ 200 ns, Figure 2.16
tPBcyc × 2 > 200 ns, Figure 2.16
Note 1. tPBcyc: PCLKB cycle
NMI
Figure 2.15
tNMIW
tNMIW
tIRQW
tIRQW
NMI Interrupt Input Timing
IRQn
Figure 2.16
IRQ Interrupt Input Timing
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RX671 Group
2. Electrical Characteristics
2.4.5
Bus Timing
Table 2.26
Bus Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
ICLK = PCLKA = 8 to 120 MHz, PCLKB = BCLK = SDCLK = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
Address delay time
Symbol
Min.
Max.
Unit
tAD
—
12.5
ns
Byte control delay time
tBCD
—
12.5
ns
CS# delay time
tCSD
—
12.5
ns
ALE delay time
tALED
—
12.5
ns
RD# delay time
tRSD
—
12.5
ns
Read data setup time
tRDS
12.5
—
ns
Read data hold time
tRDH
0
—
ns
WR# delay time
tWRD
—
12.5
ns
Write data delay time
tWDD
—
12.5
ns
Write data hold time
tWDH
0
—
ns
WAIT# setup time
tWTS
12.5
—
ns
WAIT# hold time
tWTH
0
—
ns
Address delay time 2 (SDRAM)
tAD2
1
12.5
ns
CS# delay time 2 (SDRAM)
tCSD2
1
12.5
ns
DQM delay time (SDRAM)
tDQMD
1
12.5
ns
CKE delay time (SDRAM)
tCKED
1
12.5
ns
Read data setup time 2 (SDRAM)
tRDS2
10
—
ns
Read data hold time 2 (SDRAM)
tRDH2
0
—
ns
Write data delay time 2 (SDRAM)
tWDD2
—
12.5
ns
Write data hold time 2 (SDRAM)
tWDH2
1
—
ns
WE# delay time (SDRAM)
tWED
1
12.5
ns
RAS# delay time (SDRAM)
tRASD
1
12.5
ns
CAS# delay time (SDRAM)
tCASD
1
12.5
ns
R01DS0373EJ0110 Rev.1.10
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Test Conditions
Figure 2.17 to
Figure 2.22
Figure 2.23
Figure 2.24 to
Figure 2.30
Page 102 of 178
RX671 Group
2. Electrical Characteristics
Data cycle
Address cycle
Ta1
Ta1
Tan
TW1
TW2
TW3
TW4
Tend
TW5
Tn1
Tn2
BCLK
tAD
Address bus
tAD
tRDS
tAD
tRDH
Address bus/
data bus
tALED
tALED
Address latch
(ALE)
tRSD
tRSD
Data read
(RD#)
Figure 2.17
tCSD
tCSD
Chip select
(CS1#)
Address/Data Multiplexed Bus Read Access Timing
Data cycle
Address cycle
Ta1
Ta1
Tan
TW1
TW2
TW3
TW4
TW5
Tend
Tn1
Tn2
Tn3
BCLK
tAD
Address bus
tAD
tAD
tWDD
tWDH
Address bus/
data bus
tALED
tALED
Address latch
(ALE)
tWRD
tWRD
Data write
(WRm#)
tCSD
Chip select
(CS1#)
Figure 2.18
tCSD
Address/Data Multiplexed Bus Write Access Timing
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RX671 Group
2. Electrical Characteristics
CSRWAIT:2
RDON:1
CSROFF:2
CSON:0
TW1
TW2
Tend
Tn1
Tn2
BCLK
Byte strobe mode
tAD
tAD
tAD
tAD
tBCD
tBCD
tCSD
tCSD
A23 to A0
1-write strobe mode
A23 to A1
BC1# to BC0#
Common to both byte strobe mode
and 1-write strobe mode
CS7# to CS0#
tRSD
tRSD
RD# (Read)
tRDS
tRDH
D15 to D0 (Read)
Figure 2.19
External Bus Timing/Normal Read Cycle (Bus Clock Synchronized)
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RX671 Group
2. Electrical Characteristics
CSWWAIT:2
WRON:1
WDON:1 *1
CSWOFF:2
WDOFF:1 *1
CSON:0
TW1
TW2
Tend
Tn1
Tn2
BCLK
Byte strobe mode
tAD
tAD
tAD
tAD
tBCD
tBCD
tCSD
tCSD
A23 to A0
1-write strobe mode
A23 to A1
BC1# to BC0#
Common to both byte strobe mode
and 1-write strobe mode
CS7# to CS0#
tWRD
tWRD
WR1# to WR0#, WR# (Write)
tWDD
tWDH
D15 to D0 (Write)
Note 1. Be sure to specify WDON and WDOFF as at least one cycle of BCLK.
Figure 2.20
External Bus Timing/Normal Write Cycle (Bus Clock Synchronized)
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Apr 15, 2022
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2. Electrical Characteristics
CSRWAIT:2
CSPRWAIT:2
RDON:1
CSON:0
TW1
TW2
Tend
CSPRWAIT:2
CSPRWAIT:2
RDON:1
RDON:1
Tpw1
Tpw2
Tend
CSROFF:2
RDON:1
Tpw1
Tpw2
Tend
Tpw1
Tpw2
Tend
Tn1
Tn2
BCLK
Byte strobe mode
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tAD
A23 to A0
1-write strobe mode
A23 to A1
tBCD
tBCD
tCSD
tCSD
BC1# to BC0#
Common to both byte strobe mode
and 1-write strobe mode
CS7# to CS0#
tRSD
tRSD
tRSD
tRSD
tRSD
tRSD
tRSD
tRSD
RD# (Read)
tRDS
tRDH
tRDS
tRDH
tRDS
tRDH
tRDS
tRDH
D15 to D0 (Read)
Figure 2.21
External Bus Timing/Page Read Cycle (Bus Clock Synchronized)
CSPWWAIT:2
CSWWAIT:2
WRON:1
WDON:1 *1
WDOFF:1 *1
CSON:0 TW1
TW2
Tend
Tdw1
WRON:1
WDON:1 *1
Tpw1
CSPWWAIT:2
WDOFF:1 *1
Tpw2
Tend
Tdw1
WRON:1
WDON:1 *1
Tpw1
CSWOFF:2
WDOFF:1 *1
Tpw2
Tend
Tn1
Tn2
BCLK
Byte strobe mode
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tAD
A23 to A0
1-write strobe mode
A23 to A1
tBCD
tBCD
tCSD
tCSD
BC1# to BC0#
Common to both byte strobe mode
and 1-write strobe mode
CS7# to CS0#
tWRD
tWRD
tWRD
tWRD
tWRD
tWRD
WR1# to WR0#, WR# (Write)
tWDD
tWDH
tWDD
tWDH
tWDD
tWDH
D15 to D0 (Write)
Note 1. Be sure to specify WDON and WDOFF as at least one cycle of BCLK.
Figure 2.22
External Bus Timing/Page Write Cycle (Bus Clock Synchronized)
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Apr 15, 2022
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RX671 Group
2. Electrical Characteristics
CSRWAIT:3
CSWWAIT:3
TW1
TW2
TW3
(Tend)
Tend
Tn1
Tn2
BCLK
A23 to A0
CS7# to CS0#
RD# (Read)
WR# (Write)
External wait
tWTS tWTH
tWTS tWTH
WAIT#
Figure 2.23
External Bus Timing/External Wait Control
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RX671 Group
2. Electrical Characteristics
SDRAM command
ACT
RD
PRA
SDCLK pin
tAD2
tAD2
Row
address
A18 to A0
tAD2
tAD2
tAD2
tAD2
tAD2
Column address
tAD2
AP*1
PRA
command
tCSD2
tCSD2
tRASD
tRASD
tCSD2
tCSD2
tCSD2
tCSD2
tRASD
tRASD
tWED
tWED
SDCS#
RAS#
tCASD
tCASD
CAS#
WE#
(High)
CKE
tDQMD
DQMn
tRDS2
tRDH2
D15 to D0
Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.
Figure 2.24
SDRAM Space Single Read Bus Timing
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RX671 Group
2. Electrical Characteristics
SDRAM command
ACT
WR
PRA
SDCLK pin
tAD2
tAD2
Row
address
A18 to A0
tAD2
tAD2
tAD2
tAD2
tAD2
Column address
tAD2
AP*1
PRA
command
tCSD2
tCSD2
tRASD
tRASD
tCSD2
tCSD2
tCSD2
tCSD2
tRASD
tRASD
tWED
tWED
SDCS#
RAS#
tCASD
tCASD
tWED
tWED
CAS#
WE#
(High)
CKE
tDQMD
DQMn
tWDD2
tWDH2
D15 to D0
Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.
Figure 2.25
SDRAM Space Single Write Bus Timing
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Apr 15, 2022
Page 109 of 178
RX671 Group
2. Electrical Characteristics
ACT
RD
RD
RD
RD PRA
SDCLK pin
tAD2 tAD2
tAD2 tAD2
A18 to A0
Row
address
C0
(column address)
C1
C2
tAD2 tAD2 tAD2
tAD2
C3
tAD2 tAD2
tAD2 tAD2
AP*1
tAD2
PRA
command
tCSD2 tCSD2 tCSD2
tCSD2
tCSD2
tRASD tRASD
tRASD
tCASD
tCASD
SDCS#
tRASD tRASD
RAS#
tCASD
CAS#
tWED tWED
WE#
(High)
CKE
tDQMD
tDQMD
DQMn
tRDS2 tRDH2
tRDS2 tRDH2
D15 to D0
Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.
Figure 2.26
SDRAM Space Multiple Read Bus Timing
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Apr 15, 2022
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RX671 Group
2. Electrical Characteristics
ACT
WR WR WR WR PRA
SDCLK pin
tAD2
A18 to A0
tAD2 tAD2
tAD2
C0
Row
address (column address)
tAD2
C1
C2
tAD2
tAD2
tAD2 tAD2
C3
tAD2
AP*1
tAD2
tAD2 tAD2
PRA
command
tCSD2 tCSD2 tCSD2
tCSD2 tCSD2
SDCS#
tRASD tRASD
tRASD tRASD tRASD
RAS#
tCASD
tCASD
tCASD
CAS#
tWED
tWED
WE#
(High)
CKE
tDQMD
tDQMD
DQMn
tWDD2 tWDH2
tWDD2 tWDH2
D15 to D0
Note 1. Address pins for output of the precharge-setting command
(Precharge-sel) for SDRAM.
Figure 2.27
SDRAM Space Multiple Write Bus Timing
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RX671 Group
2. Electrical Characteristics
SDRAM command
ACT
RD
RD
RD
RD
t AD2
t AD2
t AD2
PRA
ACT
RD
RD
RD
RD
PRA
SDCLK pin
t AD2
A18 to A0
t AD2
Row
address
t AD2
C0
(column address 0)
C1
C2
t AD2
t AD2
C3
t AD2
t AD2
t AD2
t AD2
t AD2
C4
R1
t AD2
AP*1
t AD2
t AD2
C5
t AD2
C6
t AD2
C7
t AD2
t AD2
PRA
command
t CSD2 t CSD2 t CSD2
t CSD2 t CSD2 t CSD2
t AD2
t AD2
PRA
command
t CSD2
t CSD2
SDCS#
t RASD t RASD
t RASD t RASD t RASD t RASD
t RASD t RASD
RAS#
t CASD
t CASD
t CASD
t CASD
CAS#
t WED
t WED
t WED
t WED
WE#
(High)
CKE
tDQMD
DQMn
t RDS2 t RDH2
t RDS2 t RDH2
t RDS2 t RDH2
t RDS2 t RDH2
D15 to D0
Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.
Figure 2.28
SDRAM Space Multiple Read Line Stride Bus Timing
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RX671 Group
2. Electrical Characteristics
MRS
SDRAM command
SDCLK pin
t AD2
t AD2
t AD2
t AD2
t CSD2
t CSD2
t RASD
t RASD
t CASD
t CASD
t WED
t WED
A18 to A0
AP*1
SDCS#
RAS#
CAS#
WE#
(High)
CKE
DQMn
(Hi-Z)
D15 to D0
Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.
Figure 2.29
SDRAM Space Mode Register Set Bus Timing
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RX671 Group
2. Electrical Characteristics
SDRAM command
Ts
(RFA)
(RFS)
(RFX)
(RFA)
SDCLK pin
t AD2
t AD2
t AD2
t AD2
A18 to A0
AP*1
t CSD2 t CSD2
t CSD2
t CSD2
t CSD2 t CSD2 t CSD2
t RASD t RASD
t RASD
t RASD
t RASD t RASD t RASD
t CASD
t CASD
t CASD
t CASD t CASD t CASD
SDCS#
RAS#
t CASD
CAS#
(High)
WE#
t CKED
t CKED
CKE
t DQMD
t DQMD
DQMn
(Hi-Z)
D15 to D0
Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.
Figure 2.30
SDRAM Space Self-Refresh Bus Timing
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Apr 15, 2022
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RX671 Group
2. Electrical Characteristics
2.4.6
EXDMAC Timing
Table 2.27
EXDMAC Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
ICLK = PCLKA = 8 to 120 MHz, PCLKB = BCLK = SDCLK = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
EXDMAC
Symbol
Min.
Max.
Unit
EDREQ setup time
tEDRQS
13
—
ns
EDREQ hold time
tEDRQH
2
—
ns
EDACK delay time
tEDACD
—
13
ns
Test
Conditions
Figure 2.31
Figure 2.32,
Figure 2.33
BCLK pin
tEDRQS tEDRQH
EDREQ0,
EDREQ1
Figure 2.31
EDREQ0 and EDREQ1 Input Timing
BCLK pin
tEDACD
tEDACD
EDACK0,
EDACK1
Figure 2.32
EDACK0 and EDACK1 Single-Address Transfer Timing (for a CS Area)
BCLK pin
tEDACD
tEDACD
EDACK0,
EDACK1
Figure 2.33
EDACK0 and EDACK1 Single-Address Transfer Timing (for SDRAM)
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RX671 Group
2.4.7
2. Electrical Characteristics
Timing of On-Chip Peripheral Modules
2.4.7.1
I/O Port
Table 2.28
I/O Port Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
I/O ports
Input data pulse width
Symbol
Min.
Max.
Unit*1
Test
Conditions
tPRW
1.5
—
tPBcyc
Figure 2.34
Note 1. tPBcyc: PCLKB cycle
PCLKB
Port
tPRW
Figure 2.34
I/O Port Input Timing
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2. Electrical Characteristics
2.4.7.2
TPU
Table 2.29
TPU Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Symbol
Min.
Max.
Unit*1
Test
Conditions
tTICW
1.5
—
tPBcyc
Figure 2.35
2.5
—
1.5
—
tPBcyc
Figure 2.36
Both-edge
setting
2.5
—
Phase counting
mode
2.5
—
Item
TPU
Input capture input pulse
width
Single-edge
setting
Both-edge
setting
Timer clock pulse width
Single-edge
setting
tTCKWH,
tTCKWL
Note 1. tPBcyc: PCLKB cycle
PCLKB
Input capture
input
Figure 2.35
tTICW
TPU Input Capture Input Timing
PCLKB
TCLKA to
TCLKD
tTCKWL
Figure 2.36
tTCKWH
TPU Clock Input Timing
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RX671 Group
2. Electrical Characteristics
2.4.7.3
TMR
Table 2.30
TMR Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
TMR
Timer clock pulse width
Single-edge setting
Both-edge setting
Max.
Unit*1
Test
Conditions
1.5
—
tPBcyc
Figure 2.37
2.5
—
Symbol
Min.
tTMCWH,
tTMCWL
Note 1. tPBcyc: PCLKB cycle
PCLKB
TMCI0 to TMCI3
tTMCWL
Figure 2.37
TMR Clock Input Timing
2.4.7.4
CMTW
Table 2.31
tTMCWH
CMTW Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
CMTW
Input capture input pulse
width
Single-edge setting
Both-edge setting
Symbol
Min.
Max.
Unit*1
Test
Conditions
tCMTWTICW
1.5
—
tPBcyc
Figure 2.38
2.5
—
Note 1. tPBcyc: PCLKB cycle
PCLKB
Input capture
input
Figure 2.38
tCMTWICW
CMTW Input Capture Input Timing
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RX671 Group
2. Electrical Characteristics
2.4.7.5
MTU
Table 2.32
MTU Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
MTU
Symbol
Input capture input pulse
width
Single-edge setting
Timer clock pulse width
Single-edge setting
tMTICW
Both-edge setting
Both-edge setting
Phase counting
mode
tMTCKWH,
tMTCKWL
Max.
Unit*1
Test
Conditions
1.5
—
tPAcyc
Figure 2.39
2.5
—
tPAcyc
Figure 2.40
Min.
1.5
—
2.5
—
2.5
—
Note 1. tPAcyc: PCLKA cycle
PCLKA
Input capture
input
Figure 2.39
tMTICW
MTU Input Capture Input Timing
PCLKA
MTCLKA to
MTCLKD,
MTIOC1A
tMTCKWL
Figure 2.40
tMTCKWH
MTU Clock Input Timing
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RX671 Group
2.4.7.6
2. Electrical Characteristics
POE3
Table 2.33
POE3 Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
POE
Symbol
Min. Typ.
Unit*1
Max.
Test Conditions
POEn# input pulse width
(n = 0, 4, 8, 10, 11)
tPOEW
1.5
—
—
Output
disable time
Transition of the POEn#
signal level
tPOEDI
—
—
5 PCLKB + 0.24
µs
Figure 2.42
When detecting falling edges
(ICSRm.POEnM[3:0] = 0000b
(m = 1 to 5; n = 0, 4, 8, 10, 11))
Simultaneous conduction
of output pins
tPOEDO
—
—
3 PCLKB + 0.2
µs
Figure 2.43
Register setting
tPOEDS
—
—
1 PCLKB + 0.2
µs
Figure 2.44
Time for access to the register
is not included.
tPOEDOS
—
—
21
µs
Figure 2.45
Oscillation stop detection
tPBcyc Figure 2.41
Note 1. tPBcyc: PCLKB cycle
PCLKB
POEn# input
(n = 0, 4, 8, 10, 11)
tPOEW
Figure 2.41
POE# Pin Input Timing
POEn# input
(n = 0, 4, 8, 10, 11)
tPOEW
Outputs disabled
MTU PWM output pins
tPOEDI
Figure 2.42
Output Disable Time for POE in Response to Transition of the POEn# Signal Level
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RX671 Group
2. Electrical Characteristics
Simultaneous active-level outputs detected*1
Outputs
disabled
MTU PWM output pins
tPOEDO
Note 1.
Figure 2.43
When the active level is set to low.
Output Disable Time for POE in Response to the Simultaneous Conduction of Output
Pins
Corresponding bit in
the SPOER register
Outputs disabled
MTU PWM output pins
tPOEDS
Figure 2.44
Output Disable Time for POE in Response to the Register Setting
Main clock
Oscillation stop detection
signal (internal signal)
Outputs disabled
MTU PWM output pins
tPOEDOS
Figure 2.45
Output Disable Time for POE in Response to the Oscillation Stop Detection
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RX671 Group
2.4.7.7
2. Electrical Characteristics
A/D Converter Trigger
Table 2.34
A/D Converter Trigger Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
A/D
converter
A/D converter trigger input pulse width
Symbol
Min.
Max.
Unit*1
Test
Conditions
tTRGW
1.5
—
tPBcyc
Figure 2.46
Note 1. tPBcyc: PCLKB cycle
PCLKB
ADTRG0#,
ADTRG1#
tTRGW
Figure 2.46
A/D Converter Trigger Input Timing
2.4.7.8
CAC
Table 2.35
CAC Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item*1, *2
CAC
CACREF input pulse width
tPBcyc ≤ tCAC
tPBcyc > tCAC
Symbol
Min.*1, *2
Max.
Unit
tCACREF
4.5 tCAC + 3 tPBcyc
—
ns
5 tCAC + 6.5 tPBcyc
—
Test
Conditions
Note 1. tPBcyc: PCLKB cycle
Note 2. tCAC: CAC count clock source cycle
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RX671 Group
2.4.7.9
Table 2.36
2. Electrical Characteristics
SCI
SCIk, SCIh, and SCIm Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
SCIk, SCIh
Input clock cycle
Symbol
Asynchronous
tScyc
Clock
synchronous
Max.
Unit*1
Test
Conditions
tPBcyc
Figure 2.47
4
—
6
—
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
—
5
ns
tSCKf
—
5
ns
tScyc
6
—
tPBcyc
Asynchronous
(SCIh)
8
—
Clock
synchronous
4
—
Input clock fall time
Output clock cycle
SCIm
Min.
Asynchronous
(SCIk)
Output clock pulse width
tSCKW
0.4
0.6
tScyc
Output clock rise time
tSCKr
—
5
ns
Output clock fall time
tSCKf
—
5
ns
Transmit data delay time
Clock
synchronous
tTXD
—
28
ns
Receive data setup time
Clock
synchronous
tRXS
15
—
ns
Receive data hold time
Clock
synchronous
tRXH
5
—
ns
Input clock cycle
Asynchronous
tScyc
4
—
tPAcyc
6
—
Clock
synchronous
Figure 2.48
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
—
5
ns
Input clock fall time
tSCKf
—
5
ns
tScyc
6
—
tPAcyc
4
—
Output clock cycle
Asynchronous
Clock
synchronous
Output clock pulse width
tSCKW
0.4
0.6
tScyc
Output clock rise time
tSCKr
—
5
ns
Output clock fall time
tSCKf
—
5
ns
ns
Transmit data delay time
Master
tTXD
Slave
—
15
—
28
Receive data setup time
Clock
synchronous
tRXS
20
—
ns
Receive data hold time
Clock
synchronous
tRXH
5
—
ns
Figure 2.47
Figure 2.48
Note 1. tPBcyc: PCLKB cycle; tPAcyc: PCLKA cycle
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2. Electrical Characteristics
tSCKW
tSCKr
tSCKf
SCKn
(n = 0 to 12)
tScyc
Figure 2.47
SCK Clock Input Timing
SCKn
tTXD
TXDn
tRXS tRXH
RXDn
(n = 0 to 12)
Figure 2.48
SCI Input/Output Timing: Clock Synchronous Mode
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RX671 Group
Table 2.37
2. Electrical Characteristics
Simple IIC Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
High-drive output is selected by the drive capacity control register.
Symbol
Min.
Max.
Unit
Test
Conditions
tSr
—
1000
ns
Figure 2.49
SSCL, SSDA input fall time
tSf
—
300
ns
SSCL, SSDA input spike pulse removal time
tSP
0
4 × tPcyc
ns
Item
Simple IIC
(Standard-mode)
SSCL, SSDA input rise time
Simple IIC
(Fast-mode)
Data input setup time
tSDAS
250
—
ns
Data input hold time
tSDAH
0
—
ns
SSCL, SSDA capacitive load
C b* 1
—
400
pF
SSCL, SSDA input rise time
tSr
—
300
ns
SSCL, SSDA input fall time
tSf
—
300
ns
SSCL, SSDA input spike pulse removal time
tSP
0
4 × tPcyc
ns
Data input setup time
tSDAS
100
—
ns
Data input hold time
tSDAH
0
—
ns
SSCL, SSDA capacitive load
C b* 1
—
400
pF
Note:
tPcyc refers to the period of PCLKA in SCI10 and SCI11, and of PCLKB in SCI0 to SCI9, and SCI12.
Note 1. Cb is the total capacitance of the bus lines.
VIH
SSDA0 to SSDA12
VIL
tBUF
tSCLH
tSTAS
tSTAH
tSTOS
tSP
SSCL0 to SSCL12
P*1
S*1
tSCLL
tSr
tSf
tSCL
tSDAS
tSDAH
Note 1. S, P, and Sr indicate the following conditions.
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.49
P*1
Sr*1
Test conditions
VIH = 0.7 × VCC, VIL = 0.3 × VCC
VOL = 0.6 V, IOL = 6 mA
Simple IIC Bus Interface Input/Output Timing
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RX671 Group
Table 2.38
2. Electrical Characteristics
Simple SPI Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Simple
SPI
Item
Symbol
Min.
Max.
Unit
SCK clock cycle output (master)
tSPcyc
4
—
tPcyc
6
—
SCK clock cycle input (slave)
SCK clock high pulse width
tSPCKWH
0.4
0.6
tSPcyc
SCK clock low pulse width
tSPCKWL
0.4
0.6
tSPcyc
tSPCKr, tSPCKf
—
20
ns
SCK clock rise/fall time
Data input setup time
tSU
33.3
—
ns
Data input hold time
tH
33.3
—
ns
SS input setup time
tLEAD
1
—
tSPcyc
SS input hold time
tLAG
1
—
tSPcyc
Data output delay time
tOD
—
33.3
ns
Data output hold time
tOH
–10
—
ns
Data rise/fall time
tDr, tDf
—
16.6
ns
tSSLr, tSSLf
—
16.6
ns
Slave access time
tSA
—
5
tPcyc
Slave output release time
tREL
—
5
tPcyc
SS input rise/fall time
Note:
Test
Conditions
Figure 2.50
Figure 2.51 to
Figure 2.54
Figure 2.53,
Figure 2.54
tPcyc refers to the period of PCLKA in SCI10 and SCI11, and of PCLKB in SCI0 to SCI9, and SCI12.
tSPCKr
tSPCKWH
VOH
VOH
SCKn output
(master)
VOL
tSPCKf
VOH
VOH
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
VIH
SCKn input
(slave)
VIH
VIL
(n = 0 to 12)
tSPCKf
VIH
VIL
tSPCKWL
VIH
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Figure 2.50
Simple SPI Clock Timing
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2. Electrical Characteristics
tTD
SSn#
output
tLEAD
tLAG
tSSLr, tSSLf
SCKn
CKPOL = 0
output
SCKn
CKPOL = 1
output
tSU
SMISOn
input
tH
MSB IN
DATA
tDr, tDf
SMOSIn
output
tOH
MSB OUT
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
(n = 0 to 12)
Figure 2.51
Simple SPI Timing (Master, CKPH = 1)
tTD
SSn#
output
tLEAD
tLAG
tSSLr, tSSLf
SCKn
CKPOL = 1
output
SCKn
CKPOL = 0
output
tSU
SMISOn
input
tH
MSB IN
tOH
SMOSIn
output
DATA
LSB IN
tOD
MSB OUT
MSB IN
tDr, tDf
DATA
LSB OUT
IDLE
MSB OUT
(n = 0 to 12)
Figure 2.52
Simple SPI Timing (Master, CKPH = 0)
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2. Electrical Characteristics
tTD
SSn#
input
tLEAD
tLAG
SCKn
CKPOL = 0
input
SCKn
CKPOL = 1
input
tSA
tOH
SMISOn
output
tOD
MSB OUT
tSU
SMOSIn
input
tREL
DATA
LSB OUT
tH
MSB OUT
tDr, tDf
MSB IN
DATA
LSB IN
MSB IN
(n = 0 to 12)
Figure 2.53
Simple SPI Timing (Slave, CKPH = 1)
tTD
SSn#
input
tLEAD
tLAG
SCKn
CKPOL = 1
input
SCKn
CKPOL = 0
input
tSA
tOH
tOD
SMISOn
output
MSB OUT
tSU
SMOSIn
input
tREL
DATA
tH
MSB IN
LSB OUT
MSB OUT
tDr, tDf
DATA
LSB IN
MSB IN
(n = 0 to 12)
Figure 2.54
Simple SPI Timing (Slave, CKPH = 0)
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Apr 15, 2022
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RX671 Group
2.4.7.10
2. Electrical Characteristics
RSCI
Table 2.39
RSCI Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-speed interface high-drive output is selected by the drive capacity control register.
Item
RSCI
Input clock cycle
Asynchronous
Symbol
Min.
Max.
Unit*1
Test
Conditions
tScyc
4
—
tPAcyc
Figure 2.55
2
—
Clock synchronous
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
—
5
ns
Input clock fall time
tSCKf
—
5
ns
tScyc
6
—
tPAcyc
2
—
Output clock cycle
Asynchronous
Clock synchronous
Output clock pulse width
tSCKW
0.4
0.6
tScyc
Output clock rise time
tSCKr
—
5
ns
Output clock fall time
tSCKf
—
5
ns
ns
Receive data setup time
Master
tRXS
Slave
Receive data hold time
Master
Transmit data delay time
Master
tRXH
Slave
tTXD
Slave
0.5
—
2.5
—
11
—
2.5
—
—
4
—
15
Figure 2.56
ns
ns
Note 1. tPAcyc: PCLKA cycle; tScyc: SCK cycle
tSCKW
tSCKr
tSCKf
SCKn
(n = 010, 011)
tScyc
Figure 2.55
SCK Clock Input Timing
SCKn
tTXD
TXDn
tRXS tRXH
RXDn
(n = 010, 011)
Figure 2.56
RSCI Input/Output Timing: Clock Synchronous Mode
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RX671 Group
Table 2.40
2. Electrical Characteristics
Simple IIC Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
High-speed interface high-drive output is selected by the drive capacity control register.
Simple IIC
(Standard-mode)
Simple IIC
(Fast-mode)
Item
Symbol
Min.
Max.
Unit
Test
Conditions
SSCL, SSDA input rise time
tSr
—
1000
ns
Figure 2.57
SSCL, SSDA input fall time
tSf
—
300
ns
SSCL, SSDA input spike pulse removal time
tSP
0
4 × tPAcyc
ns
Data input setup time
tSDAS
250
—
ns
Data input hold time
tSDAH
0
—
ns
SSCL, SSDA capacitive load
C b* 1
—
400
pF
SSCL, SSDA input rise time
tSr
—
300
ns
SSCL, SSDA input fall time
tSf
—
300
ns
SSCL, SSDA input spike pulse removal time
tSP
0
4 × tPAcyc
ns
Data input setup time
tSDAS
100
—
ns
Data input hold time
tSDAH
0
—
ns
SSCL, SSDA capacitive load
C b* 1
—
400
pF
Note:
tPAcyc: PCLKA cycle
Note 1. Cb is the total capacitance of the bus lines.
VIH
SSDA010, SSDA011
VIL
tBUF
tSCLH
tSTAS
tSTAH
tSTOS
tSP
SSCL010, SSCL011
P*1
S*1
tSCLL
tSr
tSf
tSCL
tSDAS
tSDAH
Note 1. S, P, and Sr indicate the following conditions.
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.57
P*1
Sr*1
Test conditions
VIH = 0.7 × VCC, VIL = 0.3 × VCC
VOL = 0.6 V, IOL = 6 mA
Simple IIC Bus Interface Input/Output Timing
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Apr 15, 2022
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RX671 Group
Table 2.41
2. Electrical Characteristics
Simple SPI Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-speed interface high-drive output is selected by the drive capacity control register.
Simple
SPI
Item
Symbol
Min.
Max.
Unit*1
SCK clock cycle output (master)
tSPcyc
2
—
tPAcyc
2
—
SCK clock cycle input (slave)
SCK clock high pulse width
tSPCKWH
0.4
0.6
tSPcyc
SCK clock low pulse width
tSPCKWL
0.4
0.6
tSPcyc
tSPCKr, tSPCKf
—
5
ns
—
1
µs
tSU
0.5
—
ns
2.5
—
SCK clock rise/fall time
Output
Data input setup time
Master
Input
Slave
Data input hold time
Master
tH
11
—
2.5
—
—
4
—
15
0
—
0
—
—
5
ns
—
1
—
tSA
—
5
tPAcyc
Slave output release time
tREL
—
5
tPAcyc
SS input setup time
tLEAD
1
—
tSPcyc
tLAG
1
—
tSPcyc
tSSLr, tSSLf
—
1
µs
Slave
Data output delay time
Master
tOD
Slave
Data output hold time
Master
tOH
Slave
Data rise/fall time
tDr, tDf
Output
Input
Slave access time
SS input hold time
SS input rise/fall time
Test
Conditions
Figure 2.58
Figure 2.59 to
Figure 2.62
ns
ns
ns
Figure 2.61,
Figure 2.62
Figure 2.59 to
Figure 2.62
Note 1. tPAcyc: PCLKA cycle
tSPCKr
tSPCKWH
VOH
VOH
SCKn output
(master)
VOL
tSPCKf
VOH
VOH
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
VIH
SCKn input
(slave)
VIH
VIL
(n = 010, 011)
tSPCKf
VIH
VIL
tSPCKWL
VIH
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Figure 2.58
Simple SPI Clock Timing
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RX671 Group
2. Electrical Characteristics
tTD
SSn#
output
tLEAD
tLAG
tSSLr, tSSLf
SCKn
CPOL = 0
output
SCKn
CPOL = 1
output
tSU
SMISOn
input
tH
MSB IN
DATA
tDr, tDf
SMOSIn
output
tOH
MSB OUT
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
(n = 010, 011)
Figure 2.59
Simple SPI Timing (Master, CPHA = 0)
tTD
SSn#
output
tLEAD
tLAG
tSSLr, tSSLf
SCKn
CPOL = 0
output
SCKn
CPOL = 1
output
tSU
SMISOn
input
tH
MSB IN
tOH
SMOSIn
output
DATA
LSB IN
tOD
MSB OUT
MSB IN
tDr, tDf
DATA
LSB OUT
IDLE
MSB OUT
(n = 010, 011)
Figure 2.60
Simple SPI Timing (Master, CPHA = 1)
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RX671 Group
2. Electrical Characteristics
tTD
SSn#
input
tLEAD
tLAG
SCKn
CPOL = 0
input
SCKn
CPOL = 1
input
tSA
tOH
SMISOn
output
tOD
MSB OUT
tSU
SMOSIn
input
tREL
DATA
LSB OUT
tH
MSB OUT
tDr, tDf
MSB IN
DATA
LSB IN
MSB IN
(n = 010, 011)
Figure 2.61
Simple SPI Timing (Slave, CPHA = 0)
tTD
SSn#
input
tLEAD
tLAG
SCKn
CPOL = 0
input
SCKn
CPOL = 1
input
tSA
tOH
tOD
SMISOn
output
MSB OUT
tSU
SMOSIn
input
tREL
DATA
tH
MSB IN
LSB OUT
MSB OUT
tDr, tDf
DATA
LSB IN
MSB IN
(n = 010, 011)
Figure 2.62
Simple SPI Timing (Slave, CPHA = 1)
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RX671 Group
2.4.7.11
Table 2.42
2. Electrical Characteristics
SSIE
Expansion Serial Sound Interface Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
AUDIO_CLK
Symbol
SSIBCK0
Unit
tEXcyc
20
—
ns
0.4
0.6
tEXcyc
tO
80
—
ns
Cycle
Master
Slave
tI
80
—
ns
Output clock high level
Master
tHC
0.35
—
tO
tLC
0.35
—
tO
tHC
0.35
—
tI
tLC
0.35
—
tI
Master
tRC
—
0.15
tO
tFC
—
0.15
tO
Slave
tRC
—
0.15
tI
tFC
—
0.15
tI
tSR
12
—
ns
12
—
tHR
8
—
15
—
tDTR
–10
5
0
20
tDTRW
—
20
Output clock low level
Input clock high level
Slave
Input clock low level
Output clock rise time
Output clock fall time
Input clock rise time
Input clock fall time
SSILRCK0,SSITXD0,
SSIRXD0
Max.
tEXL/tEXH
Cycle
High/low level
Min.
Input setup time
Master
Slave
Input hold time
Master
Slave
Output delay time
Master
Slave
Output delay time from when an
SSILRCK0 signal is changed
Slave
Test
Conditions
Figure 2.63
Figure 2.64
Figure 2.65,
Figure 2.66
ns
ns
ns
Figure 2.67
tEXcyc
tEXH
tEXL
AUDIO_CLK
(input)
1/2 VCC
tEXf
Figure 2.63
tEXr
Clock Input Timing
tHC
tRC
tFC
tLC
SSIBCK0
tI, tO
Figure 2.64
SSIE Clock Input/Output Timing
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Apr 15, 2022
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RX671 Group
2. Electrical Characteristics
SSIBCK0
(input or output)
SSILRCK0 (input),
SSIRXD0 (input)
tSR
tHR
SSILRCK0 (output),
SSITXD0 (output)
tDTR
Figure 2.65
Transmission and Reception Timing for the SSIE Data When the SSICR.BCKP Bit is 0
SSIBCK0
(input or output)
SSILRCK0 (input),
SSIRXD0 (input)
tSR
tHR
SSILRCK0 (output),
SSITXD0 (output)
tDTR
Figure 2.66
Transmission and Reception Timing for the SSIE Data When the SSICR.BCKP Bit is 1
SSILRCK0 (input)
SSITXD0 (output)
tDTRW
MSB bit output timing in slave transmission from SSILRCK0 with the settings of
DEL = 1, SDTA = 0, or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0]
Figure 2.67
Output Delay of the SSIE Data from When an SSILRCK0 Signal is Changed
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Apr 15, 2022
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RX671 Group
2.4.7.12
Table 2.43
2. Electrical Characteristics
RSPI
RSPI Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
RSPI
RSPCK clock cycle
Master
Symbol
Min.*1
Max.*1
Unit*1
tSPcyc
2
—
tPAcyc
4
—
tSPCKWH
(tSPcyc – tSPCKr
– tSPCKf) / 2 – 3
—
ns
0.4
0.6
tSPcyc
tSPCKWL
(tSPcyc – tSPCKr
– tSPCKf) / 2 – 3
—
ns
0.4
0.6
tSPcyc
Slave
RSPCK clock high pulse
width
Master
RSPCK clock low pulse
width
Master
Slave
Slave
RSPCK clock rise/fall time
Output
tSPCKr,
tSPCKf
Input
Data input setup time
Master
tSU
Slave
Data input hold time
Master
Master
SSL hold time
Master
Master
Master
PCLKA division ratio set to
a value other
than 1/2
tH
tPAcyc
—
ns
8.3
—
1
8
tSPcyc
4
—
tPAcyc
1
8
tSPcyc
4
—
tPAcyc
ns
tLEAD
tLAG
tOD
tOH
tTD
Slave
MOSI and MISO
rise/fall time
Output
SSL rise/fall time
Output
—
ns
Slave
Successive transmission
delay time
—
—
Slave
Data output hold time
ns
6
8.3
0
Slave
Master
ns
µs
tHF
Slave
Data output delay time
5
1
PCLKA division ratio set to
1/2
Slave
SSL setup time
—
—
tDr, tDf
Input
—
6.3
—
28
0
—
0
—
tSPcyc + 2 × tPAcyc
8 × tSPcyc
+ 2 × tPAcyc
4 × tPAcyc
—
Figure 2.68
Figure 2.69 to
Figure 2.74
ns
ns
—
5
ns
—
1
µs
tSSLr,
tSSLf
—
5
ns
—
1
µs
Slave access time
tSA
—
28
ns
Slave output release time
tREL
—
28
ns
Input
Test
Conditions*2
Figure 2.73,
Figure 2.74
Note 1. tPAcyc: PCLKA cycle
Note 2. When a letter “-A”, “-B”, etc. to indicate group membership is appended to the pin name, each pin is recommended to use in
combination with the pins in the same group. All RSPI AC timings are measured in combination with the pins in the same group.
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RX671 Group
2. Electrical Characteristics
tSPCKr
tSPCKWH
VOH
VOH
RSPCK output
(master)
VOL
tSPCKf
VOH
VOH
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
VIH
VIH
RSPCK input
(slave)
VIL
tSPCKf
VIH
VIH
VIL
tSPCKWL
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Figure 2.68
RSPI Clock Timing
tTD
SSLA0 to
SSLA3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
tSU
MISOA
input
tH
MSB IN
tDr, tDf
MOSIA
output
Figure 2.69
DATA
tOH
MSB OUT
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKA Division Ratio Set to a Value Other
Than 1/2)
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RX671 Group
2. Electrical Characteristics
tTD
SSLA0 to
SSLA3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
tSU
MISOA
input
tHF
MSB IN
DATA
tDr, tDf
MOSIA
output
Figure 2.70
tHF
tOH
MSB OUT
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKA Division Ratio Set to 1/2)
tTD
SSLA0 to
SSLA3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
tSU
MISOA
input
tH
MSB IN
tOH
MOSIA
output
Figure 2.71
DATA
LSB IN
tOD
MSB OUT
MSB IN
tDr, tDf
DATA
LSB OUT
IDLE
MSB OUT
RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKA Division Ratio Set to a Value Other
Than 1/2)
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RX671 Group
2. Electrical Characteristics
tTD
SSLA0 to
SSLA3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
tSU
MISOA
input
tHF
MSB IN
tOH
DATA
LSB IN
tOD
MOSIA
output
Figure 2.72
tH
MSB IN
tDr, tDf
MSB OUT
DATA
LSB OUT
IDLE
MSB OUT
RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKA Division Ratio Set to 1/2)
tTD
SSLA0
input
tLEAD
tLAG
RSPCKA
CPOL = 0
input
RSPCKA
CPOL = 1
input
tSA
tOH
MISOA
output
MSB OUT
tSU
MOSIA
input
Figure 2.73
tOD
DATA
tREL
LSB OUT
tH
MSB IN
MSB OUT
tDr, tDf
DATA
LSB IN
MSB IN
RSPI Timing (Slave, CPHA = 0)
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RX671 Group
2. Electrical Characteristics
tTD
SSLA0
input
tLEAD
tLAG
RSPCKA
CPOL = 0
input
RSPCKA
CPOL = 1
input
tSA
tOH
tOD
MISOA
output
MSB OUT
tSU
MOSIA
input
Figure 2.74
tREL
DATA
tH
MSB IN
LSB OUT
MSB OUT
tDr, tDf
DATA
LSB IN
MSB IN
RSPI Timing (Slave, CPHA = 1)
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RX671 Group
2.4.7.13
Table 2.44
2. Electrical Characteristics
RSPIA
RSPIA Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-speed interface high-drive output is selected by the drive capacity control register.
Item
RSPI
RSPCK clock cycle
Master
Symbol
Min.*1
Max.*1
Unit*1
tSPcyc
2
—
tPAcyc
2
—
tSPCKWH
(tSPcyc – tSPCKr
– tSPCKf) / 2 – 3
—
ns
0.4
0.6
tSPcyc
(tSPcyc – tSPCKr
– tSPCKf) / 2 – 3
—
ns
Slave
RSPCK clock high pulse width
Master
Slave
RSPCK clock low pulse width
Master
tSPCKWL
Slave
RSPCK clock rise/fall time
Output
Input
Data input setup time
Master
0.4
0.6
tSPcyc
tSPCKr,
tSPCKf
—
5
ns
—
1
µs
tSU
0
—
ns
2.5
—
Slave
Data input hold time
Master
tH
Slave
SSL setup time
Master
tLEAD
Slave
SSL hold time
Master
tLAG
Slave
Data output delay time
Master
tOD
Slave
Data output hold time
Master
tOH
Slave
tTD
5.7
—
2.5
—
1
8
tSPcyc
6
—
tPAcyc
1
8
tSPcyc
6
—
tPAcyc
—
4
ns
—
14
0
—
0
—
tSPcyc + 2 × tPAcyc
8 × tSPcyc
+ 2 × tPAcyc
tSPcyc
—
—
5
ns
MOSI and MISO
rise/fall time
Output
—
1
µs
SSL
rise/fall time
Output
tSSLr,
—
5
ns
Input
tSSLf
—
1
µs
tSA
—
20
ns
Input
Slave access time
Slave output release time
Figure 2.76 to
Figure 2.82
ns
Master
tDr, tDf
Figure 2.75
ns
Successive transmission delay
time
Slave
Test
Conditions*2
ns
tREL
—
20
ns
TI SSP SS input setup time
Slave
tTISS
4.5
—
ns
TI SSP SS input hold time
Slave
tTISH
2.5
—
ns
TI SSP next-access delay time
Slave
tTIND
2 × tPAcyc +
SLNDL × tPAcyc
—
ns
TI SSP SS output delay time
Master
tTISSOD
—
7
ns
Figure 2.79,
Figure 2.80
Figure 2.81,
Figure 2.82
Figure 2.78
Note 1. tPAcyc: PCLKA cycle
Note 2. When a letter “-A”, “-B”, etc. to indicate group membership is appended to the pin name, each pin is recommended to use in
combination with the pins in the same group. All RSPIA AC timings are measured in combination with the pins in the same
group.
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RX671 Group
2. Electrical Characteristics
tSPCKr
tSPCKWH
tSPCKf
RSPIA
VOH
VOH
RSPCK0 output
(master)
VOL
VOH
VOH
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
VIH
VIH
RSPCK0 input
(slave)
tSPCKf
VIH
VIL
VIH
VIL
tSPCKWL
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Figure 2.75
RSPIA Clock Timing
RSPIA
SSL00 to
SSL03
output
tTD
tLEAD
tLAG
tSSLr, tSSLf
RSPCK0
CPOL = 0
output
RSPCK0
CPOL = 1
output
tSU
MISO0
input
tH
MSB IN
tDr, tDf
MOSI0
output
Figure 2.76
DATA
tOH
MSB OUT
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
RSPIA Timing (Master, Motorola SPI, CPHA = 0)
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Apr 15, 2022
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RX671 Group
2. Electrical Characteristics
RSPIA
SSL00 to
SSL03
output
tTD
tLEAD
tLAG
tSSLr, tSSLf
RSPCK0
CPOL = 0
output
RSPCK0
CPOL = 1
output
tSU
MISO0
input
tH
MSB IN
DATA
tOH
MOSI0
output
Figure 2.77
LSB IN
tOD
MSB IN
tDr, tDf
MSB OUT
DATA
LSB OUT
IDLE
MSB OUT
RSPIA Timing (Master, Motorola SPI, CPHA = 1)
RSPIA
SSL00 to
SSL03
output
tTISSOD
RSPCK0
CPOL = 0
output
RSPCK0
CPOL = 1
output
tSU
MISO0
input
tH
MSB IN
LSB IN
tOD
tDr
MOSI0
output
Figure 2.78
INVALID
DATA
MSB OUT
tDf
LSB OUT
INVALID
DATA
RSPIA Timing (Master, TI SSP)
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RX671 Group
2. Electrical Characteristics
RSPIA
tTD
SSL00
input
tLEAD
tLAG
RSPCK0
CPOL = 0
input
RSPCK0
CPOL = 1
input
tSA
tOH
MISO0
output
MSB OUT
tSU
MOSI0
input
Figure 2.79
tOD
DATA
tREL
LSB OUT
tH
MSB OUT
tDr, tDf
MSB IN
DATA
LSB IN
MSB IN
RSPIA Timing (Slave, Motorola SPI, CPHA = 0)
RSPIA
tTD
SSL00
input
tLEAD
tLAG
RSPCK0
CPOL = 0
input
RSPCK0
CPOL = 1
input
tSA
tOH
tOD
MISO0
output
MSB OUT
tSU
MOSI0
input
Figure 2.80
tREL
DATA
tH
MSB IN
LSB OUT
MSB OUT
tDr, tDf
DATA
LSB IN
MSB IN
RSPIA Timing (Slave, Motorola SPI, CPHA = 1)
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Apr 15, 2022
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RX671 Group
RSPIA
2. Electrical Characteristics
tTISS
tTISH
tTIND
SSL00
input
RSPCK0
CPOL = 0
output
RSPCK0
CPOL = 1
output
tSU
MISO0
input
tH
MSB IN
tOH
MOSI0
output
Figure 2.81
RSPIA
MSB
IN
LSB IN
tDr
tDf
MSB OUT
LSB OUT
RSPIA Timing (Slave, TI SSP, Transmit with Delay between Frames)
tTISS
tTISH
SSL00
input
RSPCK0
CPOL = 0
output
RSPCK0
CPOL = 1
output
tSU
MISO0
input
tH
tSU
MSB IN
LSB IN
tOD
MSB IN
tOD
tDr
MOSI0
output
MSB OUT
DATA
tDf
LSB OUT
1st frame
Figure 2.82
tH
LSB OUT
2nd frame
RSPIA Timing (Slave, TI SSP, Transmit with No Delay between Frames)
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Apr 15, 2022
Page 145 of 178
RX671 Group
2.4.7.14
Table 2.45
2. Electrical Characteristics
QSPIX
QSPIX Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
ICLK = 8 to 120 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-speed interface high-drive output is selected by the drive capacity control register.
Item
QSPIX
Symbol
Min.
Max.
Unit
QSPCLK clock cycle
tQScyc
2
48
tIcyc*1
QSPCLK clock high pulse width
tQSWH
tQScyc × 0.4
—
ns
QSPCLK clock low pulse width
tQSWL
tQScyc × 0.4
—
ns
Data input setup time
tSu
8
—
ns
Data input hold time
tIH
0
—
ns
QSSL setup time
tLEAD
(N + 0.5) × tQScyc
– 5*2
(N + 0.5) × tQScyc
+ 100*2
ns
QSSL hold time
tLAG
(N + 0.5) × tQScyc
– 5*3
(N + 0.5) × tQScyc
+ 100*3
ns
Data output delay time
tOD
—
4
ns
Data output hold time
tOH
–3.3
—
ns
Successive transmission delay time
tTD
1
16
tQScyc
Test
Conditions
Figure 2.83
Figure 2.84
Note 1. tIcyc: ICLK cycle
Note 2. N: Value of the SPSSCR.SSSU bit (0 or 1)
Note 3. N: Value of the SPSSCR.SSHLD bit (0 or 1)
tQSWH
QSPCLK
output
tQSWL
tQScyc
Figure 2.83
QSPIX Clock Timing
tTD
QSSL
output
tLEAD
tLAG
QSPCLK
output
tSU
QIO0 to QIO3
input
tIH
MSB IN
DATA
tOH
QIO0 to QIO3
output
Figure 2.84
MSB OUT
LSB IN
tOD
DATA
LSB OUT
IDLE
Transmit/Receive Timing
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Apr 15, 2022
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RX671 Group
2.4.7.15
Table 2.46
2. Electrical Characteristics
RIIC
RIIC Timing (1)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr
Item
RIIC
SCL input cycle time
(Standard-mode,
SCL input high pulse width
SMBus)
ICFER.FMPE = 0 SCL input low pulse width
Symbol
Min.*1
Max.
Unit
Test
Conditions
tSCL
6(12) × tIICcyc + 1300
—
ns
Figure 2.85
tSCLH
3(6) × tIICcyc + 300
—
ns
tSCLL
3(6) × tIICcyc + 300
—
ns
SCL, SDA input rise time
tSr
—
1000
ns
SCL, SDA input fall time
tSf
—
300
ns
SCL, SDA input spike pulse removal time
tSP
0
1(4) × tIICcyc
ns
SDA input bus free time
tBUF
3(6) × tIICcyc + 300
—
ns
Start condition input hold time
tSTAH
tIICcyc + 300
—
ns
Restart condition input setup time
tSTAS
1000
—
ns
Stop condition input setup time
tSTOS
1000
—
ns
Data input setup time
tSDAS
tIICcyc + 50
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
C b* 2
—
400
pF
SCL input cycle time
RIIC
(Fast-mode)
SCL input high pulse width
ICFER.FMPE = 0
SCL input low pulse width
tSCL
6(12) × tIICcyc + 600
—
ns
tSCLH
3(6) × tIICcyc + 300
—
ns
tSCLL
3(6) × tIICcyc + 300
—
ns
SCL, SDA input rise time
tSr
20 × (External pull-up
voltage/5.5V)
300
ns
SCL, SDA input fall time
tSf
20 × (External pull-up
voltage/5.5V)
300
ns
SCL, SDA input spike pulse removal time
tSP
0
1(4) × tIICcyc
ns
SDA input bus free time
tBUF
3(6) × tIICcyc + 300
—
ns
Start condition input hold time
tSTAH
tIICcyc + 300
—
ns
Restart condition input setup time
tSTAS
300
—
ns
Stop condition input setup time
tSTOS
300
—
ns
Data input setup time
tSDAS
tIICcyc + 50
—
ns
Data input hold time
tSDAH
0
—
ns
*2
—
400
pF
SCL, SDA capacitive load
Cb
Note:
tIICcyc: RIIC internal reference clock (IICφ) cycle
Note 1. The value within parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 11b while the digital filter is enabled by
the setting ICFER.NFE = 1.
Note 2. Cb is the total capacitance of the bus lines.
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RX671 Group
Table 2.47
2. Electrical Characteristics
RIIC Timing (2)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr
Symbol
Min.*1
Max.
Unit
Test
Conditions
SCL input cycle time
tSCL
6(12) × tIICcyc + 240
—
ns
Figure 2.85
SCL input high pulse width
tSCLH
3(6) × tIICcyc + 120
—
ns
SCL input low pulse width
tSCLL
3(6) × tIICcyc + 120
—
ns
SCL, SDA input rise time
tSr
—
120
ns
SCL, SDA input fall time
tSf
—
120
ns
SCL, SDA input spike pulse removal time
tSP
0
1(4) × tIICcyc
ns
SDA input bus free time
tBUF
3(6) × tIICcyc + 120
—
ns
Start condition input hold time
tSTAH
tIICcyc + 120
—
ns
Restart condition input setup time
tSTAS
120
—
ns
Stop condition input setup time
tSTOS
120
—
ns
Item
RIIC
(Fast-mode+)
ICFER.FMPE = 1
Data input setup time
tSDAS
tIICcyc + 20
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
C b* 2
—
550
pF
Note:
tIICcyc: RIIC internal reference clock (IICφ) cycle
Note 1. The value within parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 11b while the digital filter is enabled by
the setting ICFER.NFE = 1.
Note 2. Cb is the total capacitance of the bus lines.
VIH
SDA0 to SDA2
VIL
tBUF
tSCLH
tSTAS
tSTAH
tSTOS
tSP
SCL0 to SCL2
P*1
S*1
tSCLL
tSr
tSf
tSCL
tSDAS
tSDAH
Note 1. S, P, and Sr indicate the following conditions.
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.85
P*1
Sr*1
Test conditions
VIH = 0.7 × VCC, VIL = 0.3 × VCC
VOL = 0.6 V, IOL = 6 mA
RIIC Bus Interface Input/Output Timing
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RX671 Group
2.4.7.16
Table 2.48
2. Electrical Characteristics
RIICHS
RIICHS Timing (1)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr
Item
Symbol
Min.*1
Max.
Unit
Test
Conditions
Figure 2.86
tSCL
10(18) × tIICcyc + 1300
—
ns
tSCLH
5(9) × tIICcyc + 300
—
ns
tSCLL
5(9) × tIICcyc + 300
—
ns
tSr
—
1000
ns
SCLHS, SDAHS input fall time
tSf
—
300
ns
SCLHS, SDAHS input spike pulse
removal time
tSP
0
1(4) × tIICcyc
ns
SDAHS input bus free time
tBUF
5(9) × tIICcyc + 300
—
ns
Start condition input hold time
tSTAH
tIICcyc + 300
—
ns
Restart condition input setup time
tSTAS
1000
—
ns
Stop condition input setup time
tSTOS
1000
—
ns
Data input setup time
tSDAS
tIICcyc + 50
—
ns
Data input hold time
tSDAH
0
—
ns
SCLHS, SDAHS capacitive load
C b* 2
—
400
pF
tSCL
10(18) × tIICcyc + 600
—
ns
tSCLH
5(9) × tIICcyc + 300
—
ns
RIICHS
SCLHS input cycle time
(Standard-mode, SCLHS input high pulse width
SMBus)
ICFER.FMPE = 0 SCLHS input low pulse width
SCLHS, SDAHS input rise time
RIICHS
SCLHS input cycle time
(Fast-mode)
SCLHS input high pulse width
ICFER.FMPE = 0
SCLHS input low pulse width
tSCLL
5(9) × tIICcyc + 300
—
ns
SCLHS, SDAHS input rise time
tSr
20 × (External pull-up
voltage/5.5V)
300
ns
SCLHS, SDAHS input fall time
tSf
20 × (External pull-up
voltage/5.5V)
300
ns
SCLHS, SDAHS input spike pulse
removal time
tSP
0
1(4) × tIICcyc
ns
SDAHS input bus free time
tBUF
5(9) × tIICcyc + 300
—
ns
Start condition input hold time
tSTAH
tIICcyc + 300
—
ns
Restart condition input setup time
tSTAS
300
—
ns
Stop condition input setup time
tSTOS
300
—
ns
Data input setup time
tSDAS
tIICcyc + 50
—
ns
Data input hold time
tSDAH
0
—
ns
SCLHS, SDAHS capacitive load
C b* 2
—
400
pF
tSCL
10(18) × tIICcyc + 240
—
ns
tSCLH
5(9) × tIICcyc + 120
—
ns
tSCLL
5(9) × tIICcyc + 120
—
ns
tSr
—
120
ns
SCLHS, SDAHS input fall time
tSf
—
120
ns
SCLHS, SDAHS input spike pulse
removal time
tSP
0
1(4) × tIICcyc
ns
SDAHS input bus free time
tBUF
5(9) × tIICcyc + 120
—
ns
Start condition input hold time
tSTAH
tIICcyc + 120
—
ns
Restart condition input setup time
tSTAS
120
—
ns
Stop condition input setup time
tSTOS
120
—
ns
Data input setup time
tSDAS
tIICcyc + 20
—
ns
Data input hold time
tSDAH
0
—
ns
SCLHS, SDAHS capacitive load
C b* 2
—
550
pF
RIICHS
SCLHS input cycle time
(Fast-mode+)
SCLHS input high pulse width
ICFER.FMPE = 1
SCLHS input low pulse width
SCLHS, SDAHS input rise time
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RX671 Group
2. Electrical Characteristics
Note:
tIICcyc: RIICHS internal reference clock (IICφ) cycle
Note 1. The value within parentheses is applicable when the value of the ICICR.NF[3:0] bits is 0011b while the digital filter is enabled by
the setting ICICR.NFE = 1.
Note 2. Cb is the total capacitance of the bus lines.
VIH
SDAHS0
VIL
tBUF
tSCLH
tSTAS
tSTAH
tSTOS
tSP
SCLHS0
P*1
S*1
tSCLL
tSr
tSf
tSDAS
tSCL
tSDAH
Note 1. S, P, and Sr indicate the following conditions.
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.86
Table 2.49
P*1
Sr*1
Test conditions
VIH = 0.7 × VCC, VIL = 0.3 × VCC
VOL = 0.6 V, IOL = 6 mA
RIICHS Bus Interface Input/Output Timing
RIICHS Timing (2)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr
Symbol
Min.*1
Max.
Unit
Test
Conditions
SCLHS input cycle time
tSCL
10(12) × tIICcyc + 80
—
ns
Figure 2.87
SCLHS input high pulse width
tSCLH
5(6) × tIICcyc
—
ns
tSCLL
5(6) × tIICcyc
—
ns
tSrCL
—
80
ns
Item
RIICHS
(Hs-mode)
ICFER.HSME = 1
SCLHS input low pulse width
SCLHS input rise time
Cb = 400pF
SDAHS input rise time
Cb = 400pF
Cb = 100pF
tSrDA
Cb = 100pF
SCLHS input fall time
Cb = 400pF
tSfCL
Cb = 100pF
tSfDA
160
—
80
—
80
—
40
ns
ns
—
160
80
tSP
0
1(1) × tIICcyc
SDAHS input bus free time
tBUF
5(6) × tIICcyc + 40
—
ns
Start condition input hold time
tSTAH
tIICcyc + 40
—
ns
Cb = 100pF
SCLHS, SDAHS input spike pulse removal
time
ns
ns
Restart condition input setup time
tSTAS
40
—
ns
Stop condition input setup time
tSTOS
40
—
ns
Data input setup time
tSDAS
10
—
ns
ns
Data input hold time
Cb = 400pF
tSDAH
Cb = 100pF
SCLHS, SDAHS capacitive load
Note:
40
—
—
SDAHS input fall time
Cb = 400pF
—
C b* 2
0
150
0
70
—
400
Figure 2.86
Figure 2.87
pF
tIICcyc: RIICHS internal reference clock (IICφ) cycle
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2. Electrical Characteristics
Note 1. The value within parentheses is applicable when the value of the ICICR.NF[3:0] bits is 0011b while the digital filter is enabled by
the setting ICICR.NFE = 1. Note that, in Hs-mode, the lower-order 2 bits of the NF[3:0] bits are ignored and the number of
stages in the digital filter is single.
Note 2. Cb is the total capacitance of the bus lines.
Sr
Sr
tSrDA
tSfDA
P
0.7 × VCC
SDAHS0
0.3 × VCC
tSDAH
tSTOS
tSTAS
tSDAS
tSTAH
0.7 × VCC
SCLHS0
0.3 × VCC
tSfCL
tSrCL
tSCLH
tSCLL
tSCLL
tSCLH
= MCS current source pull-up
= Rp resistor pull-up
Figure 2.87
RIICHS Bus Interface Input/Output Timing (Hs-mode)
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RX671 Group
2.4.7.17
Table 2.50
2. Electrical Characteristics
SDHI
SDHI Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
SDHI
Symbol
Min.
Max.
Unit
SDHI_CLK pin output cycle time
tPP(SD)
20
—
ns
SDHI_CLK pin output high pulse width
tWH(SD)
0.4 × tPP(SD)
—
ns
SDHI_CLK pin output low pulse width
tWL(SD)
0.4 × tPP(SD)
—
ns
SDHI_CLK pin output rise time
tTLH(SD)
—
3
ns
SDHI_CLK pin output fall time
tTHL(SD)
—
3
ns
tODLY(SD)
–6.5
4
ns
Input data setup time for SDHI_CMD and SDHI_D0 to
SDHI_D3 pins
tISU(SD)
6
—
ns
Input data hold time for SDHI_CMD and SDHI_D0 to
SDHI_D3 pins
tIH(SD)
2
—
ns
Output data delay time (data transfer mode) for
SDHI_CMD and SDHI_D0 to SDHI_D3 pins
Test Conditions*1
Figure 2.88
Note 1. When a letter “-A”, “-B”, etc. to indicate group membership is appended to the pin name, each pin is recommended to use in
combination with the pins in the same group. All SDHI AC timings are measured in combination with the pins in the same group.
tPP(SD)
tWL(SD)
VIH
SDHI_CLK output
VIH
50% VCC
VIH
50% VCC
VIL
tTHL(SD)
tWH(SD)
VIL
VIL
tTLH(SD)
tISU(SD) tIH(SD)
SDHI_CMD, SDHI_D3 to SDHI_D0 input
tODLY(SD)
tODLY(SD)
SDHI_CMD, SDHI_D3 to SDHI_D0 output
Figure 2.88
SD Host Interface Input/Output Signal Timing
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2.5
2. Electrical Characteristics
USB Characteristics
Table 2.51
On-Chip USB Low Speed (Host Only) Characteristics (DP and DM Pin Characteristics)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 3.0 to 3.6 V, 3.0 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
UCLK = 48 MHz,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr
Item
Input
characteristics
Output
characteristics
Symbol
Min.
Typ.
Max.
Unit
Input high level voltage
VIH
2.0
—
—
V
Input low level voltage
VIL
—
—
0.8
V
Differential input sensitivity
VDI
0.2
—
—
V
Differential common mode range
VCM
0.8
—
2.5
V
Output high level voltage
VOH
2.8
—
3.6
V
0.0
—
0.3
V
IOL = 2 mA
1.3
—
2.0
V
Figure 2.89
tLR
75
—
300
ns
tLF
75
—
300
ns
tLR / tLF
80
—
125
%
Rpd
14.25
—
24.80
kΩ
Fall time
Pull-down
characteristics
DP/DM pull-down resistance
(when the host controller function is
selected)
DP, DM
90%
VCRS
tLR/ tLF
90%
10%
10%
tLR
Figure 2.89
IOH = –200 µA
VOL
Rise time
Rise/fall time ratio
| DP – DM |
VCRS
Output low level voltage
Cross-over voltage
Test Conditions
tLF
DP and DM Output Timing (Low Speed)
dp
27Ω
Observation
point
200 pF to
600 pF
dm
3.6 V
1.5 kΩ
27Ω
200 pF to
600 pF
Figure 2.90
Test Circuit (Low Speed)
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Table 2.52
2. Electrical Characteristics
On-Chip USB Full-Speed Characteristics (DP and DM Pin Characteristics)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 3.0 to 3.6 V, 3.0 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
UCLK = 48 MHz,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr
Item
Input
characteristics
Output
characteristics
Symbol
Min.
Typ.
Max.
Unit
Input high level voltage
VIH
2.0
—
—
V
Input low level voltage
VIL
—
—
0.8
V
Differential input sensitivity
VDI
0.2
—
—
V
Differential common mode range
VCM
0.8
—
2.5
V
Output high level voltage
VOH
2.8
—
3.6
V
Output low level voltage
Cross-over voltage
Test Conditions
| DP – DM |
IOH = –200 µA
VOL
0.0
—
0.3
V
IOL = 2 mA
VCRS
1.3
—
2.0
V
Figure 2.91
tFR
4
—
20
ns
Rise time
Fall time
tFF
4
—
20
ns
Rise/fall time ratio
tFR / tFF
90
—
111.11
%
tFR/ tFF
Output resistance
ZDRV
28
—
44
Ω
Rs = 27 Ω included
Pull-up and pull- DP pull-up resistance
down
(when the function controller function
characteristics
is selected)
Rpu
0.900
—
1.575
kΩ
Idle state
1.425
—
3.090
14.25
—
24.80
DP/DM pull-down resistance
(when the host controller function is
selected)
DP, DM
Rpd
90%
VCRS
kΩ
90%
10%
10%
tFR
Figure 2.91
At transmission and
reception
tFF
DP and DM Output Timing (Full-Speed)
dp
27Ω
Observation
point
50 pF
dm
27Ω
50 pF
Figure 2.92
Test Circuit (Full-Speed)
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2.6
2. Electrical Characteristics
A/D Conversion Characteristics
Table 2.53
12-Bit A/D (Unit 0) Conversion Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKB = PCLKC = 1 MHz to 60 MHz, Ta = Topr,
Source impedance = 1.0 kΩ
Item
Resolution
Analog input capacitance
time*1
Conversion
(Operation at PCLKC = 60 MHz)
Min.
Typ.
Max.
Unit
8
—
12
Bit
—
—
30
pF
0.48
(0.267)*2
—
—
µs
Offset error
—
±1.0
±2.5
LSB
Full-scale error
—
±1.0
±2.5
LSB
Quantization error
—
±0.5
—
LSB
Absolute accuracy
—
±2.5
±4.5
LSB
DNL differential nonlinearity error
—
±0.5
±1.5
LSB
INL integral nonlinearity error
—
±1.0
±2.5
LSB
Test Conditions
Sampling in 16 states
Note:
The above specification values apply when there is no access to the external bus during A/D conversion. If access proceeds
during A/D conversion, values may not fall within the above ranges.
Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states
is indicated.
Note 2. The value in parentheses indicates the sampling time.
Table 2.54
12-Bit A/D (Unit 1) Conversion Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKB = PCLKD = 1 MHz to 60 MHz, Ta = Topr,
Source impedance = 1.0 kΩ
Item
Min.
Typ.
Max.
Unit
8
—
12
Bit
Conversion time*1
(Operation at PCLKD = 60 MHz)
0.88
(0.633)*2
—
—
µs
Sampling in 38 states
(ADSAM.SAM = 1)
Conversion time*1
(Operation at PCLKD = 30 MHz)
1
(0.500)*2
—
—
µs
Sampling in 15 states
(ADSAM.SAM = 1)
Analog input capacitance
—
—
30
pF
Offset error
—
±2.0
±3.5
LSB
Resolution
Full-scale error
—
±2.0
±3.5
LSB
Quantization error
—
±0.5
—
LSB
Absolute accuracy
—
±4.0
±6.0
LSB
DNL differential nonlinearity error
(Operation at PCLKD = 60 MHz)
—
±1.5
±4.0
LSB
DNL differential nonlinearity error
(Operation at PCLKD = 30 MHz)
—
±1.5
±2.5
LSB
INL integral nonlinearity error
(Operation at PCLKD = 60 MHz)
—
±2.0
±4.0
LSB
INL integral nonlinearity error
(Operation at PCLKD = 30 MHz)
—
±2.0
±3.5
LSB
Test Conditions
Note:
The above specification values apply when there is no access to the external bus during A/D conversion. If access proceeds
during A/D conversion, values may not fall within the above ranges.
Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states
is indicated.
Note 2. The value in parentheses indicates the sampling time.
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Table 2.55
2. Electrical Characteristics
A/D Internal Reference Voltage Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKB = PCLKD = 60 MHz, Ta = Topr
Item
Min.
Typ.
Max.
Unit
A/D internal reference voltage
1.13
1.18
1.23
V
2.7
Test Conditions
Temperature Sensor Characteristics
Table 2.56
Temperature Sensor Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Min.
Typ.
Max.
Unit
Relative accuracy
Item
—
±1
—
°C
Temperature slope
—
4
—
mV/°C
Output voltage
—
1.21
—
V
Temperature sensor start time
—
—
30
µs
4.15
—
—
µs
Sampling time*1
Test Conditions
Ta = 25°C
Note 1. Set the S12AD1.ADSSTRT register such that the sampling time of the 12-bit A/D converter satisfies this specification.
2.8
CTSU Characteristics
Table 2.57
CTSU Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
External capacitance connected to TSCAP pin
Ctscap
9
10
11
nF
TS pin capacitive load
Cbase
—
—
50
pF
Total sum of the high-level output current*1
ΣIOH
—
—
–40*2
mA
Test Conditions
The mutual
capacitance method
is in use.
Note 1. Total sum of IOH of the pins other than TSCAP, and TS0 to TS16
Note 2. In the mutual capacitance method, when the amount of current output from the I/O pins other than those of the CTSU is
relatively large, the VCC voltage largely drops, affecting measurement by the CTSU. Accordingly, the total sum of IOH of the
other pins should be no more than the listed value when the CTSU is in use.
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2.9
2. Electrical Characteristics
Power-on Reset Circuit and Voltage Detection Circuit Characteristics
Table 2.58
Power-on Reset Circuit and Voltage Detection Circuit Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Voltage detection
level
Power-on
reset (POR)
Symbol
Min.
Typ.
Max.
Unit
VPOR
2.5
2.6
2.7
V
1.8
2.25
2.7
Vdet0_1
2.84
2.94
3.04
Vdet0_2
2.77
2.87
2.97
Vdet0_3
2.70
2.80
2.90
Vdet1_1
2.89
2.99
3.09
Vdet1_2
2.82
2.92
3.02
Low power consumption
function disabled*1
Low power consumption
function enabled*2
Voltage detection circuit (LVD0)
Voltage detection circuit (LVD1)
Voltage detection circuit (LVD2)
Vdet1_3
2.75
2.85
2.95
Vdet2_1
2.89
2.99
3.09
Vdet2_2
2.82
2.92
3.02
Test
Conditions
Figure 2.93
Figure 2.94
Figure 2.95
Figure 2.96
Vdet2_3
2.75
2.85
2.95
Power-on reset time
tPOR
—
4.6
—
LVD0 reset time
tLVD0
—
0.70
—
Figure 2.94
LVD1 reset time
tLVD1
—
0.57
—
Figure 2.95
LVD2 reset time
tLVD2
—
0.57
—
Figure 2.96
tVOFF
200
—
—
µs
Figure 2.93,
Figure 2.94
tdet
—
—
200
µs
Figure 2.93 to
Figure 2.96
LVD operation stabilization time (after LVD is enabled)
td(E-A)
—
—
10
µs
Hysteresis width (LVD1 and LVD2)
V LVH
—
70
—
mV
Figure 2.95,
Figure 2.96
Internal reset time
Minimum VCC down time
Response delay time
ms
Figure 2.93
Note:
The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet1,
and Vdet2 for the POR/ LVD.
Note 1. The low power consumption function is disabled and DEEPCUT[1:0] = 00b or 01b.
Note 2. The low power consumption function is enabled and DEEPCUT[1:0] = 11b.
tVOFF
VPOR
VCC
Internal reset signal
(Low is valid)
tdet
Figure 2.93
tPOR
tdet
tdet
tPOR
Power-on Reset Timing
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2. Electrical Characteristics
tVOFF
VCC
Vdet0
Internal reset signal
(Low is valid)
tdet
Figure 2.94
tdet
tLVD0
Voltage Detection Circuit Timing (Vdet0)
tVOFF
VCC
VLVH
Vdet1
LVD1E
Td(E-A)
LVD1
Comparator output
LVD1CMPE
LVD1MON
Internal reset signal
(Low is valid)
When LVD1RN = L
tdet
tdet
tLVD1
When LVD1RN = H
tLVD1
Figure 2.95
Voltage Detection Circuit Timing (Vdet1)
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2. Electrical Characteristics
tVOFF
VCC
VLVH
Vdet2
LVD2E
Td(E-A)
LVD2
Comparator output
LVD2CMPE
LVD2MON
Internal reset signal
(Low is valid)
When LVD2RN = L
tdet
tdet
tLVD2
When LVD2RN = H
tLVD2
Figure 2.96
Voltage Detection Circuit Timing (Vdet2)
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RX671 Group
2.10
2. Electrical Characteristics
Oscillation Stop Detection Timing
Table 2.59
Oscillation Stop Detection Circuit Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Detection time
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
tdr
—
—
1
ms
Figure 2.97
Main clock or
PLL clock
tdr
OSTDSR.OSTDF
LOCO clock
ICLK
Figure 2.97
Oscillation Stop Detection Timing
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RX671 Group
2.11
2. Electrical Characteristics
Battery Backup Function Characteristics
Table 2.60
Battery Backup Function Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
VBATT = 1.62 to 3.6 V, Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
Voltage level for switching to battery backup
VDETBATT
2.50
2.60
2.70
V
Lower-limit VBATT voltage for power supply switching due to
VCC voltage drop
VBATTSW
2.00
—
—
V
VCC-off period for starting power supply switching*1
tVOFFBATT
200
—
—
µs
Backup domain power-down detection level
VPDR(BKP)
1.45
1.5
1.55
V
Time delay in assertion of the reset signal for the backup
domain*2
tp(PDRL)
—
—
2000
µs
Time delay in negation of the reset signal for the backup
domain
tp(PDRH)
—
—
1000
µs
Temper input pulse width
tw(TAMPI)
200
—
—
ns
Test
Conditions
Figure 2.98
Figure 2.99
Figure 2.100
Note 1. The VCC-off period for switching power supply indicates the period from VCC falling below the minimum value of the battery
backup switching threshold voltage (VDETBATT) until the source of supply is switched to VBATT. When the VCC recovers within
this period, the source may not be switched to VBATT and supply from VCC is continued.
Note 2. When the VBKP recovers within this period, the backup domain reset signal may not be generated.
tVOFFBATT
VCC
VDETBATT
VBATT
VBATT
Switching prohibited
VCC voltage
guaranteed range
VBATTSW
Backup power
area
VCC supply
VBATT
Switching prohibited
VBATT supply
VBATT voltage
guaranteed range
VCC supply
Note. The VBATT voltage when the supplied power source switches from VCC to VBATT should not be lower than
VBATTSW, the lower-limit VBATT voltage for switching between power supplies due to a drop in the VCC voltage.
Figure 2.98
Battery Backup Function Characteristics
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RX671 Group
2. Electrical Characteristics
VBKP
VPDR(BKP)
Reset signal for the
backup domain
(Active Low)
Figure 2.99
tp(PDRH)
tp(PDRL)
tp(PDRH)
Backup Domain Reset Characteristics
TAMPIn
tw(TAMPI)
tw(TAMPI)
Figure 2.100 TAMPIn Input Timing
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2.12
2. Electrical Characteristics
Flash Memory Characteristics
Table 2.61
Code Flash Memory Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Temperature range for programming/erasure: Ta = Topr
Item
Programming time
NPEC ≤ 100 times
Programming time
NPEC > 100 times
Erasure time
NPEC ≤ 100 times
Erasure time
NPEC > 100 times
Symbol
FCLK = 4 MHz
FCLK = 15 MHz
20 MHz ≤ FCLK ≤ 60
MHz
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
tP128
—
0.75
13.2
—
0.38
6.6
—
0.34
6
8 Kbytes
tP8K
—
49
176
—
25
88
—
22
80
ms
32 Kbytes
tP32K
—
194
704
—
97
352
—
88
320
ms
128 bytes
tP128
—
0.91
15.8
—
0.46
8
—
0.41
7.2
ms
8 Kbytes
tP8K
—
60
212
—
30
106
—
27
96
ms
32 Kbytes
tP32K
—
234
848
—
117
424
—
106
384
ms
128 bytes
ms
8 Kbytes
tE8K
—
78
216
—
48
132
—
43
120
ms
32 Kbytes
tE32K
—
283
864
—
173
528
—
157
480
ms
8 Kbytes
tE8K
—
94
260
—
58
158
—
52
144
ms
32 Kbytes
tE32K
—
341
1040
—
208
632
—
189
576
ms
Reprogramming/erasure
cycle*1
NPEC
10000
*2
—
—
10000
*2
—
—
10000
*2
—
—
Times
Suspend delay time during
programming
tSPD
—
—
264
—
—
132
—
—
120
µs
First suspend delay time during
erasing
(in suspend priority mode)
tSESD1
—
—
216
—
—
132
—
—
120
µs
Second suspend delay time
during erasure
(in suspend priority mode)
tSESD2
—
—
1.7
—
—
1.7
—
—
1.7
ms
Suspend delay time during
erasure
(in erasure priority mode)
tSEED
—
—
1.7
—
—
1.7
—
—
1.7
ms
Forced stop command
Data hold time*3, *4
Test
Conditions
tFD
—
—
32
—
—
22
—
—
20
µs
tDRP
20
—
—
20
—
—
20
—
—
Year
10
—
—
10
—
—
10
—
—
Ta ≤ 85°C
Ta ≤ 105°C
Note 1. Definition of program/erase cycle:
The program/erase cycle is the number of erasing for each block. When the number of program/erase cycles is n, each block
can be erased n times. For instance, when 128-byte program is performed 64 times for different addresses in 8-Kbyte block and
then the block is erased, the program/erase cycle is counted as one. However, the same address cannot be programmed more
than once before the next erase cycle (overwriting is prohibited).
Note 2. Characteristics are degraded as the number of program/erase increases. This is the minimum value of program/erase cycles to
guarantee all characteristics listed in this table.
Note 3. This shows the characteristic when the flash memory writer or self-programming library from Renesas Electronics is in use, and
the number of times programming and erasure proceed does not exceed the specified value.
Note 4. These values are based on the results of reliability testing.
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 163 of 178
RX671 Group
Table 2.62
2. Electrical Characteristics
Data Flash Memory Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Temperature range for programming/erasure: Ta = Topr
Item
Programming time
Erasure time
Blank check time
Symbol
4 bytes
FCLK = 4 MHz
FCLK = 15 MHz
20 MHz ≤ FCLK ≤ 60
MHz
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
tDP4
—
0.36
3.8
—
0.18
1.9
—
0.16
1.7
ms
64 bytes
tDP64
—
3.1
18
—
1.9
11
—
1.7
10
ms
128 bytes
tDP128
—
4.7
27
—
2.9
16
—
2.6
15
ms
256 bytes
tDP256
—
8.9
50
—
5.4
31
—
4.9
28
ms
4 bytes
tDBC4
—
—
84
—
—
33
—
—
30
µs
64 bytes
tDBC64
—
—
280
—
—
110
—
—
100
µs
2 Kbytes
tDBC2K
—
—
6160
—
—
2420
—
—
2200
µs
Reprogramming/erasure
cycle*1
NDPEC 100000
*2
—
—
100000
*2
—
—
100000
*2
—
—
Times
Suspend delay time during
programming
tDSPD
—
264
—
—
132
—
—
120
µs
—
First suspend
delay time during
erasure
(in suspend priority mode)
64 bytes
—
—
—
216
—
—
132
—
—
120
µs
128 bytes
—
—
—
216
—
—
132
—
—
120
µs
256 bytes
—
—
—
216
—
—
132
—
—
120
µs
Second suspend
delay time during
erasure
(in suspend priority mode)
64 bytes
—
—
—
300
—
—
300
—
—
300
µs
128 bytes
—
—
—
390
—
—
390
—
—
390
µs
256 bytes
—
—
—
570
—
—
570
—
—
570
µs
Suspend delay
time during erasing
(in erasure priority mode)
64 bytes
—
—
—
300
—
—
300
—
—
300
µs
128 bytes
—
—
—
390
—
—
390
—
—
390
µs
256 bytes
—
—
—
570
—
—
570
—
—
570
µs
Forced stop command
Data hold time*3, *4
tFD
—
—
32
—
—
22
—
—
20
tDDRP
20
—
—
20
—
—
20
—
—
10
—
—
10
—
—
10
—
—
Test
Conditions
µs
Year Ta ≤ 85°C
Ta ≤ 105°C
Note 1. Definition of program/erase cycle:
The program/erase cycle is the number of erasing for each block. When the number of program/erase cycles is n, each block
can be erased n times. For instance, when 4-byte program is performed 512 times for different addresses in 2-Kbyte block and
then the block is erased, the program/erase cycle is counted as one. However, the same address cannot be programmed more
than once before the next erase cycle (overwriting is prohibited).
Note 2. Characteristics are degraded as the number of program/erase increases. This is the minimum value of program/erase cycles to
guarantee all characteristics listed in this table.
Note 3. This shows the characteristic when the flash memory writer or self-programming library from Renesas Electronics is in use, and
the number of times programming and erasure proceed does not exceed the specified value.
Note 4. These values are based on the results of reliability testing.
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 164 of 178
RX671 Group
2. Electrical Characteristics
• Suspension during programming
FCU command
Program
Suspend
tSPD
FSTATR.FRDY
Ready
Programming pulse
Not Ready
Ready
Programming
• Suspension during erasure in suspend priority mode
FCU command
Erase
Suspend
Resume
Suspend
tSESD1
FSTATR.FRDY
Ready
Erasure pulse
Not Ready
tSESD2
Ready
Erasing
Not Ready
Erasing
• Suspension during erasure in erasure priority mode
FCU command
Erase
Suspend
tSEED
FSTATR.FRDY
Ready
Erasure pulse
Not Ready
Ready
Erasing
Figure 2.101 Flash Memory Programming/Erasure Suspension Timing
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 165 of 178
RX671 Group
2.13
2. Electrical Characteristics
Boundary Scan
Table 2.63
Boundary Scan Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
Figure 2.102
tTCKcyc
100
—
—
ns
TCK clock high pulse width
tTCKH
45
—
—
ns
TCK clock low pulse width
tTCKL
45
—
—
ns
TCK clock rise time
tTCKr
—
—
5
ns
TCK clock fall time
tTCKf
—
—
5
ns
TRST# pulse width
TCK clock cycle time
tTRSTW
20
—
—
tTCKcyc
Figure 2.103
TMS setup time
tTMSS
20
—
—
ns
Figure 2.104
TMS hold time
tTMSH
20
—
—
ns
TDI setup time
tTDIS
20
—
—
ns
TDI hold time
tTDIH
20
—
—
ns
TDO data delay time
tTDOD
—
—
40
ns
tTCKcyc
tTCKH
TCK
tTCKf
tTCKL
tTCKr
Figure 2.102 Boundary Scan TCK Timing
TCK
RES#
TRST#
tTRSTW
Figure 2.103 Boundary Scan TRST# Timing
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 166 of 178
RX671 Group
2. Electrical Characteristics
TCK
tTMSS
tTMSH
tTDIS
tTDIH
TMS
TDI
tTDOD
TDO
Figure 2.104 Boundary Scan Input/Output Timing
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 167 of 178
RX671 Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
Information on the latest version of the package dimensions or mountings has been displayed in “Packages” on Renesas
Electronics Corporation website.
JEITA Package code
RENESAS code
MASS(TYP.)[g]
37)/*$
37/*-&$
0.16
aaa(4X) C
E
B
A
D
㻵㻺㻰㻱㼄㻌㻭㻾㻱㻭
A
ccc C
C
ddd C
D1
e
Reference
Symbol
Øb(nX)䚷䚷
e
eee
fff
Dimension in Millimeters
Min.
Nom.
Max.
D
䠉
9.00
䠉
E
䠉
9.00
䠉
D1
䠉
㻣㻚㻤㻜
䠉
E1
䠉
㻣㻚㻤㻜
䠉
A
䠉
䠉
1.01
b
䠉
0.35
䠉
e
䠉
0.65
䠉
aaa
䠉
䠉
0.10
ccc
䠉
䠉
0.10
ddd
䠉
䠉
0.10
eee
䠉
䠉
0.08
fff
䠉
䠉
0.08
n
䠉
145
䠉
C A B
C
E1
Figure A 145-Pin TFLGA (PTLG0145JC-A)
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 168 of 178
RX671 Group
Appendix 1. Package Dimensions
JEITA Package code
RENESAS code
MASS(TYP.)[g]
37)/*$
37/*.%$
0.09
aaa(4X) C
E
B
A
D
㻵㻺㻰㻱㼄㻌㻭㻾㻱㻭
A
ccc C
C
ddd C
D1
e
Reference
Symbol
e
E1
Øb(nX)䚷䚷
eee
fff
C A B
C
Dimension in Millimeters
Min.
Nom.
Max.
D
䠉
7.00
䠉
E
䠉
7.00
䠉
D1
䠉
㻢㻚㻜㻜
䠉
E1
䠉
㻢㻚㻜㻜
䠉
A
䠉
䠉
1.01
b
䠉
0.25
䠉
e
䠉
0.50
䠉
aaa
䠉
䠉
0.10
ccc
䠉
䠉
0.10
ddd
䠉
䠉
0.08
eee
䠉
䠉
0.08
fff
䠉
䠉
0.05
n
䠉
145
䠉
Figure B 145-Pin TFLGA (PTLG0145KB-A)
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 169 of 178
RX671 Group
Appendix 1. Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-LFQFP144-20x20-0.50
PLQP0144KA-B
—
1.2
Unit: mm
HD
*1 D
108
73
109
E
*2
144
HE
72
37
1
36
NOTE 4
Index area
NOTE 3
F
S
0.25
A1
T
c
y S
A2
A
e
*3
bp
Lp
L1
Detail F
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Reference Dimensions in millimeters
Symbol
M
Min
Nom
Max
D
19.9
20.0
20.1
20.1
E
19.9
20.0
A2
1.4
HD
21.8
22.0
22.2
HE
21.8
22.0
22.2
A
1.7
A1
0.05
0.15
bp
0.17
0.20
0.27
c
0.09
0.20
T
0q
3.5q
8q
e
0.5
x
0.08
y
0.10
Lp
0.45
0.6
0.75
L1
1.0
Figure C 144-Pin LFQFP (PLQP0144KA-B)
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 170 of 178
RX671 Group
Appendix 1. Package Dimensions
JEITA Package code
RENESAS code
MASS(TYP.)[g]
37)/*$
37/*-%$
0.09
aaa(4X) C
E
B
A
D
㻵㻺㻰㻱㼄㻌㻭㻾㻱㻭
A
ccc C
C
ddd C
Reference
Symbol
Dimension in Millimeters
Nom.
Max.
D
䠉
7.00
䠉
E
䠉
7.00
䠉
D1
䠉
㻡㻚㻤㻡
䠉
E1
䠉
㻡㻚㻤㻡
䠉
A
䠉
䠉
1.01
b
䠉
0.35
䠉
e
䠉
0.65
䠉
aaa
䠉
䠉
0.10
ccc
䠉
䠉
0.10
ddd
䠉
䠉
0.08
eee
䠉
䠉
0.08
fff
䠉
䠉
0.08
n
䠉
100
䠉
D1
e
Min.
Øb(nX)䚷䚷
e
eee
fff
C A B
C
E1
Figure D 100-Pin TFLGA (PTLG0100JB-A)
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 171 of 178
RX671 Group
Appendix 1. Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-LFQFP100-14x14-0.50
PLQP0100KB-B
—
0.6
HD
Unit: mm
*1 D
75
51
*2
E
50
100
HE
76
26
1
25
NOTE 4
Index area
NOTE 3
F
S
y S
*3
0.25
Reference Dimensions in millimeters
Symbol
bp
M
Min
Nom
Max
D
13.9
14.0
14.1
14.1
E
13.9
14.0
A2
1.4
HD
15.8
16.0
16.2
HE
15.8
16.0
16.2
A
1.7
A1
0.05
0.15
bp
0.15
0.20
0.27
c
0.09
0.20
T
0q
3.5q
8q
e
0.5
x
0.08
y
0.08
Lp
0.45
0.6
0.75
L1
1.0
A1
T
c
A2
A
e
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Lp
L1
Detail F
Figure E 100-Pin LFQFP (PLQP0100KB-B)
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 172 of 178
RX671 Group
Appendix 1. Package Dimensions
-(,7$3DFNDJH&RGH
5(1(6$6&RGH
0$66 7\S >J@
37)%*$
37%*.%$
㻵㻺㻰㻱㼄㻌㻭㻾㻱㻭
㻴
㻳
㻲
㻱
㻰
㻯
㻮
㻭
㻝 㻞 㻟 㻠 㻡 㻢 㻣 㻤
0LQ
1RP
0D[
'
(
$
㸫
㸫
$
H
㸫
㸫
E
[
㸫
㸫
[
\
㸫
㸫
㸫
㸫
\
㸫
㸫
Q
㸫
㸫
='
㸫
㸫
=(
㸫
㸫
Figure F 64-Pin TFBGA (PTBG0064KB-A)
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 173 of 178
RX671 Group
Appendix 1. Package Dimensions
Figure G 64-Pin LFQFP (PLQP0064KB-C)
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 174 of 178
RX671 Group
Appendix 1. Package Dimensions
JEITA Package code
RENESAS code
MASS(TYP.)[g]
P-HWQFN048-7x7-0.50
PWQN0048KC-A
0.13 g
2X
aaa C
36
25
37
24
D
INDEX AREA
(D/2 X E/2)
48
13
2X
aaa C
1
12
B
A
E
ccc C
C
SEATING PLANE
A (A3) A1
b(48X)
e
48X
bbb
ddd
eee C
E2
1
fff
fff
C A B
12
EXPOSED
13
DIE PAD
48
C A B
C A B
C
Reference
Symbol
Dimension in Millimeters
Min.
A
䠉
䠉
0.80
0.00
0.02
0.05
A3
0.203 REF.
0.20
D
24
37
36
25
L(48X)
K(48X)
Max.
A1
b
D2
Nom.
0.25
0.30
7.00 BSC
E
7.00 BSC
e
0.50 BSC
L
0.30
0.40
K
0.20
䠉
䠉
D2
5.25
5.30
5.35
E2
5.25
5.30
5.35
aaa
0.15
bbb
0.10
ccc
0.10
ddd
0.05
eee
0.08
fff
0.10
0.50
Figure H 48-Pin HWQFN (PWQN0048KC-A)
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Page 175 of 178
REVISION HISTORY
RX671 Group
REVISION HISTORY
REVISION HISTORY
RX671 Group Datasheet
Classifications
- Items with Technical Update document number: Changes according to the corresponding issued Technical Update
- Items without Technical Update document number: Minor changes that do not require Technical Update to be issued
Rev.
Date
1.00
1.10
Mar 31, 2021
Apr 15, 2022
Description
Page
Summary
—
First edition, issued
Features
1
Coremark value, changed
1
Useful functions for IEC60730 compliance, changed
1. Overview
8
Table 1.1 Outline of Specifications (7/10), changed
11
Table 1.1 Outline of Specifications (10/10), changed
14 to 16
Table 1.3 List of Products, changed
17
Figure 1.1 How to Read the Product Part Number, changed
18
Figure 1.2 Block Diagram, changed
23
Table 1.4 Pin Functions (5/8), changed
24
Table 1.4 Pin Functions (6/8), changed
26
Table 1.4 Pin Functions, Note changed
2. Electrical Characteristics
87
Table 2.9 Normal Output Characteristics, added
88
Table 2.10 Thermal Resistance Value (Reference), changed
Appendix 1. Package Dimensions
168
Figure A 145-Pin TFLGA (PTLG0145JC-A), added
169
Figure B 145-Pin TFLGA (PTLG0145KB-A), added
171
Figure D 100-Pin TFLGA (PTLG0100JB-A), added
173
Figure F 64-Pin TFBGA (PTBG0064KB-A), added
175
Figure H 48-Pin HWQFN (PWQN0048KC-A), added
R01DS0373EJ0110 Rev.1.10
Apr 15, 2022
Classification
Page 176 of 178
General Precautions in the Handling of Microprocessing Unit and Microcontroller
Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage
notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have
been issued for the products.
1.
Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps
must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be
adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.
Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be
touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.
2.
Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of
register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset
pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins
in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the
level at which resetting is specified.
3.
Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements.
Follow the guideline for input signal during power-off state as described in your product documentation.
4.
Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are
generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of
the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
become possible.
5.
Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program
execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator
during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced
with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
6.
Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.)
and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level
is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.).
7.
Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these
addresses as the correct operation of the LSI is not guaranteed.
8.
Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.
The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms
of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,
operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a systemevaluation test for the given product.
Notice
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8.
9.
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13.
14.
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