Features
Datasheet
RX72M Group
R01DS0332EJ0120
Rev.1.20
Nov 15, 2023
Renesas MCUs
240-MHz 32-bit RX MCU, on-chip double-precision FPU, 1396 CoreMark,
Arithmetic unit for trigonometric functions, up to 4-MB flash memory (supportive of the dual bank function), 1-MB SRAM,
EtherCAT Slave Controller, various communications interfaces including Ethernet MAC compliant with IEEE 1588, SD host
interface, quad SPI, and CAN, 12-bit A/D converter, RTC, Encryption functions (optional), Serial sound interface, CMOS
camera interface, Graphic-LCD controller, 2D drawing engine
Features
PLQP0176KB-C 24 × 24 mm, 0.5-mm pitch
PLQP0144KA-B 20 × 20 mm, 0.5-mm pitch
PLQP0100KB-B 14 × 14 mm, 0.5-mm pitch
■ 32-bit RXv3 CPU core
Maximum operating frequency: 240 MHz
Capable of 1396 CoreMark in operation at 240 MHz
Double-precision 64-bit IEEE-754 floating point
A collective register bank save function is available.
Supports the memory protection unit (MPU)
JTAG and FINE (one-line) debugging interfaces
■ Low-power design and architecture
Operation from a single 2.7- to 3.6-V supply
RTC is capable of operation from a dedicated power supply.
Four low-power modes
■ On-chip code flash memory
Supports versions with up to 4 Mbytes of ROM
No wait cycles at up to 120 MHz or when the ROM cache is hit,
one-wait state at above 120 MHz
User code is programmable by on-board or off-board programming.
Programming/erasing as background operations (BGOs)
A dual-bank structure allows exchanging the start-up bank.
■ On-chip data flash memory
32 Kbytes, reprogrammable up to 100,000 times
Programming/erasing as background operations (BGOs)
■ On-chip SRAM
1 Mbyte of SRAM (no wait states; however, if ICLK is at a
frequency above 120 MHz, access to locations in the 512 Kbytes of
SRAM from 0080 0000h to 0087 FFFFh requires one cycle of
waiting)
32 Kbytes of RAM with ECC (single error correction/double error
detection)
8 Kbytes of standby RAM (backup on deep software standby)
■ Data transfer
DMACAa: 8 channels
DTCb: 1 channel
EXDMAC: 2 channels
DMAC for the Ethernet controller: 3 channels
■ Reset and supply management
Power-on reset (POR)
Low voltage detection (LVD) with voltage settings
■ Clock functions
External crystal resonator or internal PLL for operation at 8 to 24
MHz
PLL for specific purposes
Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20
MHz
120-kHz clock for the IWDTa
■ Real-time clock
Adjustment functions (30 seconds, leap year, and error)
Real-time clock counting and binary counting modes are selectable
Time capture function
(for capturing times in response to event-signal input)
■ Independent watchdog timer
120-kHz clock operation
■ Useful functions for IEC60730 compliance
Oscillation-stoppage detection, frequency measurement, CRCA,
IWDTa, self-diagnostic function for the A/D converter, etc.
Register write protection function can protect values in important
registers against overwriting.
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
PLBG0224GA-A 13 × 13 mm, 0.8-mm pitch
PLBG0176GA-A 13 × 13 mm, 0.8-mm pitch
■ Various communications interfaces
EtherCAT slave controller (two ports)
Ethernet MAC compliant with IEEE 1588 (2 channels)
PHY layer (1 channel) for host/function or OTG controller
(1 channel) with full-speed USB 2.0 transfer
CAN (compliant with ISO11898-1), incorporating 32 mailboxes (3
channels)
SCIj and SCIh with multiple functionalities (8 channels)
Choose from among asynchronous mode, clock-synchronous mode,
smart-card interface mode, simplified SPI, simplified I2C, and
extended serial mode.
SCIi with 16-byte transmission and reception FIFOs (5 channels)
I2C bus interface for transfer at up to 1 Mbps (3 channels)
Four-wire QSPI (1 channel) in addition to RSPIc (3 channels)
Parallel data capture unit (PDC) for the CMOS camera interface
Graphic-LCD controller (GLCDC)
2D drawing engine (DRW2D)
SD host interface (1 channel) with a 1- or 4-bit SD bus for use with
SD memory or SDIO
MMCIF with 1-, 4-, or 8-bit transfer bus width
■ External address space
Buses for full-speed data transfer (max. operating frequency of 80
MHz)
8 CS areas
8-, 16-, or 32-bit bus space is selectable per area
Independent SDRAM area (128 Mbytes)
■ Up to 29 extended-function timers
32-bit GPTW (4 channels)
16-bit TPUa (6 channels), MTU3a (9 channels)
8-bit TMRa (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2
channels)
■ 12-bit A/D converter
Two 12-bit units (8 channels for unit 0; 21 channels for unit 1)
Self diagnosis, detection of analog input disconnection
■ 12-bit D/A converter: 2 channels
■ Temperature sensor for measuring temperature
within the chip
■ Arithmetic unit for trigonometric functions
■ Delta-Sigma Modulator Interface
Six external delta-sigma modulators are connectable
■ Encryption functions (optional)
AES (key lengths: 128, 192, and 256 bits)
Trusted Secure IP (TSIP)
■ Up to 182 pins for general I/O ports
5-V tolerance, open drain, input pull-up, switchable driving ability
■ Operating temp. range
D-version: –40C to +85C
G-version: –40C to +105C
Page 1 of 180
RX72M Group
1. Overview
1.
Overview
1.1
Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 give a comparison of the functions of products in different
packages.
Table 1.1 is an outline of maximum specifications, and the peripheral modules and the number of channels of the
modules differ depending on the number of pins on the package and the capacity of the code flash memory. For details,
refer to Table 1.2, Comparison of Functions for Different Packages.
Table 1.1
Outline of Specifications (1/11)
Classification
Module/Function
Description
CPU
CPU
Maximum operating frequency: 240 MHz
32-bit RX CPU (RXv3)
Minimum instruction execution time: One instruction per state (cycle of the system
clock)
Address space: 4-Gbyte linear
Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Ten 32-bit registers
Accumulator: Two 72-bit registers
113 instructions
Instructions installed as standard: 111
Basic instructions: 77
Single-precision floating-point operation instructions: 11
DSP instructions: 23
Instructions for register bank save function: 2
Addressing modes: 11
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32 × 32 → 64 bits
On-chip divider: 32 / 32 → 32 bits
Barrel shifter: 32 bits
FPU
Single-precision floating-point numbers (32 bits) and double-precision floating-point
numbers (64 bits)
Data types and floating-point exceptions in conformance with the IEEE754 standard
Double-precision
floating point
coprocessor
Double-precision floating-point register set
Double-precision floating-point data registers: 16, each with 64-bit width
Double-precision floating-point control registers: Four, each with 32-bit width
Double-precision floating-point processing instructions: 21
Notifying the interrupt controller of double-precision floating-point exceptions
Register bank save
function
Fast collective saving and restoration of the values of CPU registers
16 save register banks
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 2 of 180
RX72M Group
Table 1.1
1. Overview
Outline of Specifications (2/11)
Classification
Module/Function
Description
Memory
Code flash memory
Capacity: 2 Mbytes/4 Mbytes
ROM cache: 8 Kbytes
120 MHz ≤ No-wait cycle access,
120 MHz > One-wait cycle access
Instructions hitting the ROM cache or operand = 240 MHz: No-wait access
On-board programming: Four types
Off-board programming (parallel programmer mode)
Instructions are executable only for the program stored in the TM target area by using
the Trusted Memory (TM) function and protection against data reading is realized.
A dual-bank structure allows programming during reading or exchanging the start-up
areas
Data flash memory
Capacity: 32 Kbytes
Programming/erasing: 100,000 times
Unique ID
16-byte unique ID for each device
RAM
Capacity: 512 Kbytes
Up to 240 MHz, no-wait access
Expansion RAM
Capacity: 512 Kbytes
120 MHz ≤ No-wait cycle access,
120 MHz > One-wait cycle access
ECC RAM
Capacity: 32 Kbytes
If the operating frequency is no greater than 120 MHz, one-wait cycle access,
if greater than 120MHz, two-wait cycle access in the case of reading, and three-wait
cycle access in the case of writing
SEC-DED (single-bit error correction and double-bit error detection)
Standby RAM
Capacity: 8 Kbytes
Operation synchronized with PCLKB: Up to 60 MHz, two-cycle access
Operating modes by the mode-setting pins at the time of release from the reset state
Single-chip mode
Boot mode (for the SCI interface)
Boot mode (for the USB interface)
Boot mode (for the FINE interface)
Selection of operating mode by register setting
Single-chip mode
On-chip ROM disabled extended mode
On-chip ROM enabled extended mode
Endian selectable
Operating modes
Clock
Clock generation circuit
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Main clock oscillator, sub-clock oscillator, low-speed/high-speed on-chip oscillator, PLL
frequency synthesizer (two circuits), and IWDT-dedicated on-chip oscillator
The peripheral module clocks can be set to frequencies above that of the system clock.
Main-clock oscillation stoppage detection
Separate frequency-division and multiplication settings for the system clock (ICLK),
peripheral module clocks (PCLKA, PCLKB, PCLKC, PCLKD), flash-IF clock (FCLK) and
external bus clock (BCLK)
The CPU and other bus masters run in synchronization with the system clock (ICLK): Up
to 240 MHz
Peripheral modules of MTU, RSPI, SCIi, ETHERC, EPTPC, PMGI, EDMAC, GPTW,
GLCDC, DRW2D, and ESC run in synchronization with PCLKA, which operates at up to
120 MHz.
Other peripheral modules run in synchronization with PCLKB: Up to 60 MHz
ADCLK in the S12AD (unit 0) runs in synchronization with PCLKC: Up to 60 MHz
ADCLK in the S12AD (unit 1) runs in synchronization with PCLKD: Up to 60 MHz
Flash IF run in synchronization with the flash-IF clock (FCLK): Up to 60 MHz
Devices connected to the external bus run in synchronization with the external bus clock
(BCLK): Up to 80 MHz
The high-speed on-chip oscillator (HOCO) can be obtained through frequencymultiplication of the PLL or PPLL reference clock
External clock input frequency: 30 MHz (max)
Clock output function
Page 3 of 180
RX72M Group
Table 1.1
Classification
1. Overview
Outline of Specifications (3/11)
Module/Function
Description
Reset
Nine types of reset
RES# pin reset: Generated when the RES# pin is driven low.
Power-on reset: Generated when the RES# pin is driven high and VCC = AVCC0 =
AVCC1 rises.
Voltage-monitoring 0 reset: Generated when VCC = AVCC0 = AVCC1 falls.
Voltage-monitoring 1 reset: Generated when VCC = AVCC0 = AVCC1 falls.
Voltage-monitoring 2 reset: Generated when VCC = AVCC0 = AVCC1 falls.
Deep software standby reset: Generated in response to an interrupt to trigger release
from deep software standby.
Independent watchdog timer reset: Generated when the independent watchdog timer
underflows, or a refresh error occurs.
Watchdog timer reset: Generated when the watchdog timer underflows, or a refresh
error occurs.
Software reset: Generated by register setting.
Power-on reset
If the RES# pin is at the high level when power is supplied, an internal reset is
generated.
After VCC = AVCC0 = AVCC1 has exceeded the voltage detection level and the
specified period has elapsed, the reset is cancelled.
Voltage detection circuit (LVDA)
Monitors the voltage being input to the VCC = AVCC0 = AVCC1 pins and generates an
internal reset or interrupt.
Voltage detection circuit 0
Capable of generating an internal reset
The option-setting memory can be used to select enabling or disabling of the reset.
Voltage detection level: Selectable from three different levels (2.94 V, 2.87 V, 2.80 V)
Voltage detection circuits 1 and 2
Voltage detection level: Selectable from three different levels (2.99 V, 2.92 V, 2.85 V)
Digital filtering (1/2, 1/4, 1/8, and 1/16 LOCO frequency)
Capable of generating an internal reset
Two types of timing are selectable for release from reset
An internal interrupt can be requested.
Detection of voltage rising above and falling below thresholds is selectable.
Maskable or non-maskable interrupt is selectable
Voltage detection monitoring
Event linking
Low power
consumption
Low power consumption
function
Module stop function
Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software
standby mode
Battery backup function
When the voltage on the VCC pin drops, battery power from the VBATT pin is supplied
to keep the real-time clock (RTC) operating.
Interrupt controller
(ICUD)
Interrupt
External bus extension
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Number of interrupt vectors: 256
External interrupts: 16 (pins IRQ0 to IRQ15)
Software interrupts: 2 sources
Non-maskable interrupts: 8 sources
Sixteen levels specifiable for the order of priority
Method of interrupt source selection:
The interrupt vectors consist of 256 vectors (128 sources are fixed. The remaining 128
vectors are selected from among the other 169 sources.)
The external address space can be divided into eight areas (CS0 to CS7), each with
independent control of access settings.
Capacity of each area: 16 Mbytes (CS0 to CS7)
A chip-select signal (CS0# to CS7#) can be output for each area.
Each area is specifiable as an 8-, 16-, or 32-bit bus space.
The data arrangement in each area is selectable as little or big endian (only for data).
SDRAM interface connectable
Bus format: Separate bus, multiplex bus
Wait control
Write buffer facility
Page 4 of 180
RX72M Group
Table 1.1
1. Overview
Outline of Specifications (4/11)
Classification
Module/Function
Description
DMA
DMA controller
(DMACAa)
8 channels
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software trigger and interrupt requests from peripheral functions
EXDMA controller
(EXDMACa)
2 channels
Four transfer modes: Normal transfer, repeat transfer, block transfer, and cluster
transfer
Single-address transfer enabled with the EDACKn signal
Request sources: Software trigger, external DMA requests (EDREQn), and interrupt
requests from peripheral functions
Data transfer controller
(DTCb)
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Request sources: External interrupts and interrupt requests from peripheral functions
Sequence transfer
Programmable I/O ports
I/O ports for the 224-pin LFBGA
I/O pins: 182
Input pin: 1
Pull-up resistors: 182
Open-drain outputs: 182
5-V tolerance: 19
I/O ports for the 176-pin LFBGA and 176-pin LFQFP
I/O pins: 136
Input pin: 1
Pull-up resistors: 136
Open-drain outputs: 136
5-V tolerance: 19
I/O ports for the 144-pin LFQFP
I/O pins: 111
Input pin: 1
Pull-up resistors: 111
Open-drain outputs: 111
5-V tolerance: 17
I/O ports for the 100-pin LFQFP
I/O pins: 72
Input pin: 1
Pull-up resistors: 72
Open-drain outputs: 72
5-V tolerance: 12
I/O ports
Event link controller (ELC)
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Event signals such as interrupt request signals can be interlinked with the operation of
functions such as timer counting, eliminating the need for intervention by the CPU to
control the functions.
137 internal event signals can be freely combined for interlinked operation with
connected functions.
Event signals from peripheral modules can be used to change the states of output pins
(of ports B and E).
Changes in the states of pins (of ports B and E) being used as inputs can be interlinked
with the operation of peripheral modules.
Page 5 of 180
RX72M Group
Table 1.1
1. Overview
Outline of Specifications (5/11)
Classification
Module/Function
Description
Timers
16-bit timer pulse unit
(TPUa)
(16 bits × 6 channels) × 1 unit
Maximum of 16 pulse-input/output possible
Select from among seven or eight counter-input clock signals for each channel
Input capture/output compare function
Output of PWM waveforms in up to 15 phases in PWM mode
Support for buffered operation, phase-counting mode (two phase encoder input) and
cascade-connected operation (32 bits × 2 channels) depending on the channel.
PPG output trigger can be generated
Capable of generating conversion start triggers for the A/D converters
Digital filtering of signals from the input capture pins
Event linking by the ELC
Multifunction timer pulse
unit (MTU3a)
9 channels (16 bits × 8 channels, 32 bits × 1 channel)
Maximum of 28 pulse-input/output and 3 pulse-input possible
Select from among 14 counter-input clock signals for each channel (PCLKA/1, PCLKA/
2, PCLKA/4, PCLKA/8, PCLKA/16, PCLK/A32, PCLKA/64, PCLKA/256, PCLKA/1024,
MTCLKA, MTCLKB, MTCLKC, MTCLKD, MTIOC1A)
14 of the signals are available for channel 0, 11 are available for channels 1, 3, 4, 6 to 8,
12 are available for channel 2, and 10 are available for channel 5.
Input capture function
39 output compare/input capture registers
Counter clear operation (synchronous clearing by compare match/input capture)
Simultaneous writing to multiple timer counters (TCNT)
Simultaneous register input/output by synchronous counter operation
Buffered operation
Support for cascade-connected operation
43 interrupt sources
Automatic transfer of register data
Pulse output mode
Toggle/PWM/complementary PWM/reset-synchronized PWM
Complementary PWM output mode
Outputs non-overlapping waveforms for controlling 3-phase inverters
Automatic specification of dead times
PWM duty cycle: Selectable as any value from 0% to 100%
Delay can be applied to requests for A/D conversion.
Non-generation of interrupt requests at peak or trough values of counters can be
selected.
Double buffer configuration
Reset synchronous PWM mode
Three phases of positive and negative PWM waveforms can be output with desired duty
cycles.
Phase-counting mode: 16-bit mode (channels 1 and 2); 32-bit mode (channels 1 and 2)
Counter functionality for dead-time compensation
Generation of triggers for A/D converter conversion
A/D converter start triggers can be skipped
Digital filter function for signals on the input capture and external counter clock pins
PPG output trigger can be generated
Event linking by the ELC
Port output enable 3
(POE3a)
Control of the high-impedance state of the MTU waveform output pins
5 pins for input from signal sources: POE0#, POE4#, POE8#, POE10#, POE11#
Initiation on detection of short-circuited outputs (detection of simultaneous PWM output
to the active level)
Initiation by oscillation-stoppage detection or software
Additional programming of output control target pins is enabled
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 6 of 180
RX72M Group
Table 1.1
1. Overview
Outline of Specifications (6/11)
Classification
Module/Function
Description
Timers
General PWM timer
(GPTW)
32 bits × 4 channels (GPTW0 to GPTW3)
Counting up or down (sawtooth-wave), counting up and down (triangle-wave) selectable
for all channels
Clock sources independently selectable for each channel
2 input/output pins per channel
2 output compare/input capture registers per channel
For the 2 output compare/input capture registers of each channel, 4 registers are
provided as buffer registers and are capable of operating as comparison registers when
buffering is not in use.
In output compare operation, buffer switching can be at crests or troughs, enabling the
generation of laterally asymmetrically PWM waveforms.
Registers for setting up frame intervals on each channel (with capability for generating
interrupts on overflow or underflow)
Generation of dead times in PWM operation
Capable of synchronous start, stop, or clearing of counter for any channel
Capable of a start, stop, clearing, or up-/down-counting of the counter supporting input
level comparison
Capable of a start, stop, clearing, or up-/down-counting of the counter supporting
maximum of 4 external triggers
Output pin disabling function by a dead time error or a short circuit detection among
output pins
Capable of generating conversion start triggers for the A/D converters as well as
monitoring external pins for a start timing of conversion.
Capable of outputting events, such as compare-match from A to F and overflow/
underflow, to ELC
Capable of using noise filter of input capture
Port output enable for
GPTW (POEG)
Programmable pulse
generator (PPG)
(4 bits × 4 groups) × 2 units
Pulse output with the MTU or TPU output as a trigger
Maximum of 32 pulse-output possible
8-bit timers (TMR)
(8 bits × 2 channels) × 2 units
Select from among seven internal clock signals (PCLKB/1, PCLKB/2, PCLKB/8,
PCLKB/32, PCLKB/64, PCLKB/1024, PCLKB/8192) and one external clock signal
Capable of output of pulse trains with desired duty cycles or of PWM signals
The 2 channels of each unit can be cascaded to create a 16-bit timer
Generation of triggers for A/D converter conversion
Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12
Event linking by the ELC
Compare match timer
(CMT)
(16 bits × 2 channels) × 2 units
Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128,
PCLKB/512)
Compare match timer W
(CMTW)
(32 bits × 1 channel) × 2 units
Compare-match, input-capture input, and output-comparison output are available.
Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128,
PCLKB/512)
Interrupt requests can be output in response to compare-match, input-capture, and
output-comparison events.
Event linking by the ELC
Realtime clock (RTCd)*1
Controlling the output disable for GPTW waveform output
Initiation by input level detection of GTETRG pins
Initiation by output disable request from GPTW
Initiation by detection of oscillation stop or by software
Clock sources: Main clock, sub-clock
Selection of the 32-bit binary count in time count/second unit possible
Clock and calendar functions
Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
Battery backup operation
Time-capture facility for three values
Event linking by the ELC
Watchdog timer (WDTA) 14 bits × 1 channel
Select from among 6 counter-input clock signals (PCLKB/4, PCLKB/64, PCLKB/128,
PCLKB/512, PCLKB/2048, PCLKB/8192)
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Nov 15, 2023
Page 7 of 180
RX72M Group
Table 1.1
1. Overview
Outline of Specifications (7/11)
Classification
Module/Function
Description
Timers
Independent watchdog
timer (IWDTa)
14 bits × 1 channel
Counter-input clock: IWDT-dedicated on-chip oscillator
Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,
dedicated clock/128, dedicated clock/256
Window function: The positions where the window starts and ends are specifiable (the
window defines the timing with which refreshing is enabled and disabled).
Event linking by the ELC
Communication
function
Ethernet controller
(ETHERC)
2 channels
Input and output of Ethernet/IEEE 802.3 frames
Transfer at 10 or 100 Mbps
Full- and half-duplex modes
MII (Media Independent Interface) and RMII (Reduced Media Independent Interface) as
defined in IEEE 802.3u
Detection of Magic PacketsTM*2 or output of a “wake-on-LAN” signal (WOL)
Compliance with flow control as defined in IEEE 802.3x standards
Filtering of multicast frames is supported.
Frame data can be directly transferred between 2 channels by cut-through switching.
PHY management
interface (PMGI)
2 channels
This module is compliant with the MII (Media Independent Interface) as defined in the
IEEE 802.3u standard.
Transmission and reception of management frames through PHY-LSI chips having an
MII or RMII interface is supported.
Alleviates load on the CPU by shifting it to dedicated hardware
The timing of management data is adjustable.
Preambles can be deleted.
PTP module for the
ethernet controller
(EPTPCb)
In connection with the Ethernet controller (ETHERC), this module is compliant with the
IEEE1588 standard.
Matching with time stamps can be used to trigger counting by the MTU and GPTW.
DMA controller for
ethernet controller
(EDMACa)
3 channels (each EDMAC determines the order of priority by a round-robin algorithm)
For ETHERC: 2 channels, for EPTPC: 1 channel
Alleviation of CPU load by the descriptor control method
Transmission FIFO: 2 Kbytes; Reception FIFO: 4 Kbytes
EtherCAT slave
controller (ESC)*3
One channel (two ports)
The Beckoff EtherCAT Slave Controller IP Core was adopted for this.
USB 2.0 FS host/
function module (USBb)
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Includes a UDC (USB Device Controller) and transceiver for USB 2.0 FS
One port
Compliance with the USB 2.0 specification
Transfer rate: Full speed (12 Mbps), low speed (1.5 Mbps) (host only)
Both self-power mode and bus-power mode are supported
OTG (On the Go) operation is possible (low-speed is not supported)
Incorporates 2 Kbytes of RAM as a transfer buffer
External pull-up and pull-down resistors are not required
Page 8 of 180
RX72M Group
Table 1.1
1. Overview
Outline of Specifications (8/11)
Classification
Module/Function
Description
Communication
function
Serial communications
interfaces
(SCIj, SCIi, SCIh)
13 channels (SCIj: 7 channels + SCIi: 5 channels + SCIh: 1 channel)
SCIj, SCIi, SCIh
Serial communications modes: Asynchronous, clock synchronous, and smart-card
interface
Multi-processor function
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Start-bit detection: Level or edge detection is selectable.
Simple I2C
Simple SPI
7- to 9-bit transfer mode
Bit rate modulation
Double-speed mode
Detecting matches of data is supported (other than for SCI12)
SCIj, SCIh
Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12
Event linking by the ELC (only on channel 5)
SCIh
Supports the serial communications protocol, which contains the start frame and
information frame
Supports the LIN format
SCIi
Data can be transmitted or received in sequence by the 16-byte FIFO buffers of the
transmission and reception unit
I2C bus interface (RIICa) 3 channels (only channel 0 can be used in fast-mode plus)
Communication formats
I2C bus format/SMBus format
Supports the multi-master
Max. transfer rate: 1 Mbps (channel 0)
Event linking by the ELC
CAN module (CAN)
3 channels
Compliance with the ISO11898-1 specification (standard frame and extended frame)
32 mailboxes per channel
Serial peripheral
interface (RSPIc)
3 channels
RSPI transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),
and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four
lines) or clock-synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Switching between MSB first and LSB first
The number of bits in each transfer can be changed to any number of bits from 8 to 16,
or to 20, 24, or 32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with
each frame having up to 32 bits)
Transit/receive data can be swapped in byte units
Buffered structure
Double buffers for both transmission and reception
RSPCK can be stopped with the receive buffer full for master reception.
Event linking by the ELC
Quad serial peripheral
interface (QSPI)
1 channel
Connectable with serial flash memory equipped with multiple input and output lines (i.e.
for single, dual, or quad operation)
Programmable bit length and selectable active sense and phase of the clock signal
Sequential execution of transfer
LSB or MSB first is selectable
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Page 9 of 180
RX72M Group
Table 1.1
Classification
1. Overview
Outline of Specifications (9/11)
Module/Function
Description
Extended serial sound interface (SSIE)
SD host interface (SDHI)
1 channel
Transfer speed: Supports high-speed mode (25 MB/s) and default speed mode
(12.5 MB/s)
One interface for SD memory and I/O cards (supporting 1- and 4-bit SD buses)
SD specifications
Part 1: Physical Layer Specification Ver. 3.01 compliant (DDR not supported)
Part E1: SDIO Specification Ver. 3.00
Error checking: CRC7 for commands and CRC16 for data
Interrupt requests: Card access interrupt, SDIO access interrupt, card detection
interrupt, interrupt of SD buffer access
DMA transfer requests: SD_BUF write and SD_BUF read
Support for card detection and write protection
MMC host interface (MMCIF)
The arithmetic unit for trigonometric
functions (TFU)
Sine, cosine, arctangent, x 2 + y 2
Simultaneous calculation of sine and cosine
Simultaneous calculation of arctangent and x 2 + y 2
Delta-sigma modulator interface (DSMIF)
6 channels
Up to six external delta-sigma modulators are connectable.
The sinc filters are selectable as first-, second-, or third-order.
Parallel data capture unit (PDC)
1 channel
Acquisition of synchronization through external 8-bit horizontal and vertical
synchronization signals
Setting of the image size when clipping of the output for a one-frame image is required
Graphic-LCD controller (GLCDC)
1 channel
Various data formats and LCD panels are supported
Superposition of 3 planes (single-color background, graphic 1, graphic 2)
32- and 16-bpp graphics data and 8-, 4-, and 1-bit CLUT data formats are supported
2D drawing engine (DRW2D)
1 channel
Vector drawing (straight lines, triangles, and circles)
Bit blitting (with support for filling, copying, stretching, and rotation)
Bus master function for input and output of frame buffer data
32-, 16-, and 8-bit pixel graphics data are supported
Bus master function for input of texture data
Input of texture data (32, 24, 16, 8, 4, 2, or 1 bit) are supported.
Run length encoding is supported
A CLUT is installed and index data can be converted into color data
Two rendering modes are supported (register mode and display list mode)
Performance counting
Interrupts in response to completion of rendering and processing of the display list
2 channels
Full-duplex transmission (only for channel 0)
Various types of serial audio formatting are supported.
Master and slave operations are supported.
The bit-clock frequency is selectable from among 13 frequencies (1/1, 1/2, 1/4, 1/6, 1/8,
1/12, 1/16, 1/24, 1/32, 1/48, 1/64, 1/96, or 1/128).
Data formats with 8, 16, 18, 20, 22, 24, and 32 bits are supported.
32-stage FIFO buffers for transmission and reception
Stopping or not stopping the SSILRCK signal on stopping of data transmission is
selectable.
1 channel
Transfer speed: Data transfer mode (30 MB/s), backward compatible mode (25 MB/s)
Compliant with JEDEC STANDARD JESD84-A441 (DDR is not supported)
Interface for Multimedia Cards (MMCs)
Data buses: Support for 1-, 4-, and 8-bit MMC buses
Interrupt requests: Card detection interrupt, error/timeout interrupt, normal operation
interrupt, interrupt of MMCIF buffer access
DMA transfer requests: CE_DATA write and CE_DATA read
Support for card detection, boot operation, high priority interrupt (HPI)
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 10 of 180
RX72M Group
Table 1.1
Classification
1. Overview
Outline of Specifications (10/11)
Module/Function
Description
12-bit A/D converter (S12ADFa)
12 bits × 2 units (unit 0: 8 channels; unit 1: 21 channels)
12-bit resolution (switchable between 8, 10, and 12 bits)
Conversion time
0.48 µs per channel (for 12-bit conversion)
0.45 µs per channel (for 10-bit conversion)
0.42 µs per channel (for 8-bit conversion)
Operating mode
Scan mode (single scan mode, continuous scan mode, or 3 group scan mode)
Group priority control (only for 3 group scan mode)
Sample-and-hold function
Common sample-and-hold circuit included
In addition, channel-dedicated sample-and-hold function (3 channels: in unit 0 only)
included
Sampling variable
Sampling time can be set up for each channel.
Digital comparison
Method: Comparison to detect voltages above or below thresholds and window
comparison
Measurement: Comparison of two results of conversion or comparison of a value in the
comparison register and a result of conversion
Self-diagnostic function
The self-diagnostic function internally generates three analog input voltages
(unit 0: VREFL0, VREFH0 × 1/2, VREFH0; unit 1: AVSS1, AVCC1 × 1/2, AVCC1)
Double trigger mode (A/D conversion data duplicated)
Detection of analog input disconnection
Three ways to start A/D conversion
Software trigger, timer (MTU, TMR, TPU) trigger, external trigger
Event linking by the ELC
12-bit D/A converter (R12DAa)
2 channels
12-bit resolution
Output voltage: 0.2 V to AVCC1 – 0.2 V (buffered output), 0 V to AVCC1 (unbuffered
output)
Buffered output or unbuffered output can be selected.
Event linking by the ELC
Temperature sensor
1 channel
Relative precision: ± 1°C
The voltage of the temperature is converted into a digital value by the 12-bit A/D
converter (unit 1).
Safety
Memory protection unit
(MPU)
Protection area: Eight areas (max.) can be specified in the range from 0000 0000h to
FFFF FFFFh.
Minimum protection unit: 16 bytes
Reading from, writing to, and enabling the execution access can be specified for each
area.
An access exception occurs when the detected access is not in the permitted area.
Trusted Memory (TM)
Function
Programs in the TM target area in the code flash memory are protected against reading
Instruction fetching by the CPU is the only form of access to these areas when the TM
function is enabled.
Register write protection
function
Protects important registers from being overwritten for in case a program runs out of
control.
CRC calculator (CRCA)
Generation of CRC codes for 8-/32-bit data
8-bit data
Selectable from the following three polynomials
X8 + X2 + X + 1, X16 + X15 + X2 + 1, X16 + X12 + X5 + 1
32-bit data
Selectable from the following two polynomials
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1,
X32 + X28 + X27 + X26 + X25 + X23 + X22 + X20 + X19 + X18 + X14 + X13 + X11 + X10 + X9 +
X8 + X6 + 1
Generation of CRC codes for use with LSB-first or MSB-first communications is
selectable
Main clock oscillation
stop detection
Main clock oscillation stop detection: Available
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 11 of 180
RX72M Group
Table 1.1
1. Overview
Outline of Specifications (11/11)
Classification
Module/Function
Description
Safety
Clock frequency
accuracy measurement
circuit (CAC)
Monitors the clock output from the main clock oscillator, sub-clock oscillator, low- and
high-speed on-chip oscillators, IWDT-dedicated on-chip oscillator, USB clock, EthernetPHY external clock, and PCLKB, and generates interrupts when the setting range is
exceeded.
Data operation circuit
(DOC)
The function to compare, add, or subtract 16-bit data
Trusted Secure IP
(TSIP)*4
Security algorithm
Common key encryption: AES (compliant with NIST FIPS PUB 197), TDES, ARC4
Non-common key encryption: RSA
Other features
TRNG (true-random number generator)
Hash value generation: SHA1, SHA224, SHA256, MD5, GHASH
Prevention of the illicit copying of keys
Encryption
function
Operating frequency
Up to 240 MHz
Power supply voltage
VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VBATT = 1.62 to 3.6 V*5
Operating temperature
D-version: –40 to +85°C
G-version: –40 to +105°C
Package
224-pin LFBGA (PLBG0224GA-A)
176-pin LFBGA (PLBG0176GA-A)
176-pin LFQFP (PLQP0176KB-C)
144-pin LFQFP (PLQP0144KA-B)
100-pin LFQFP (PLQP0100KB-B)
On-chip debugging system
E1 emulator (JTAG and FINE interfaces)
Note 1. When the realtime clock is not used, initialize the registers in the time clock according to description in section 33.6.7,
Initialization Procedure When the Realtime Clock is Not to be Used in the User’s Manual: Hardware.
Note 2. Magic PacketTM is a registered trademark of Advanced Micro Devices, Inc.
Note 3. EtherCAT® is a registered trademark and patented technology, licensed by Beckhoff Automation GmbH, Germany.
Note 4. The product part number differs according to whether or not the MCU includes the encryption function.
Note 5. The low CL crystal unit cannot be used when the VBATT voltage is less than 2.0 V.
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 12 of 180
RX72M Group
Table 1.2
1. Overview
Comparison of Functions for Different Packages (1/2)
Functions
RX72M
Package
224 Pins
External bus
External bus width
SDRAM area controller
DMA
176 Pins
144 Pins
32 bits/16 bits/8 bits
16 bits/8 bits
Available
Ch. 0 to 7
Data transfer controller
Timers
Available
Ch. 0 and 1
Ch. 0 to 5
Multi-function timer pulse unit 3
Ch. 0 to 8
General PWM timer
Ch. 0 to 3
Port output enable 3
Available
Port output enable for GPTW
Available
Programmable pulse generator
Communication
function
Ch. 0 and 1
8-bit timers
Ch. 0 to 3
Compare match timer
Ch. 0 to 3
Ch. 0 and 1
Available
Watchdog timer
Available
Independent watchdog timer
Available
Ethernet controller
Ch. 0 and 1
PHY management interface
Ch. 0 and 1
PTP controller for the ethernet
controller
Available
DMA controller for the ethernet
controller
Ch. 0 and 1 (ETHERC)
Ch. 2 (EPTPC)
Ch. 0 and 1
USB 2.0 FS host/function module
Ch. 0
Serial communications interfaces (SCIj)
Ch. 0 to 6
Serial communications interfaces (SCIi)
Ch. 7 to 11
Serial communications interfaces
(SCIh)
Ch. 12
Not available
I2C bus interfaces
Ch. 0 to 2
Ch. 1 and 2
Serial peripheral interface
Ch. 0 to 2
CAN module
Quad serial peripheral interface
Ch. 1
Ch. 0 to 2
Ch. 0
Expansion serial sound interface
12-bit A/D
converter
Not available
Realtime clock
EtherCAT slave controller
Graphics
Not available
16-bit timer pulse unit
Compare match timer W
Not available
Not available
DMA controller
EXDMA controller
100 Pins
Not available
Ch. 0 and 1
SD host interface
Ch. 0
Not available
Multimediacard interface
Ch. 0
Not available
Parallel data capture unit
Available
Not available
Graphic-LCD controller
Available
Not available
2D drawing engine
Available
Not available
Unit 0
Unit 1
12-bit D/A converter
Temperature sensor
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
AN000 to 007 (8 channels)
AN000 to 004
(5 channels)
AN000 to 002
(3 channels)
AN100 to 120 (21 channels)
AN101 to 103,
106, 107, 109,
110, 114 to 118
(12 channels)
Ch. 0 and 1
Not available
Available
Page 13 of 180
RX72M Group
Table 1.2
1. Overview
Comparison of Functions for Different Packages (2/2)
Functions
RX72M
Package
224 Pins
176 Pins
Arithmetic unit for trigonometric functions
Delta-sigma modulator interface
144 Pins
Available
Available
Available
(unit 0 only)
CRC calculator
Available
Data operation circuit
Available
Clock frequency accuracy measurement circuit
Trusted Secure IP
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Not available
Available
Available/Not available
Event link controller
Off-board programming (parallel programmer mode)
100 Pins
Available
Available
Not available
Page 14 of 180
RX72M Group
1.2
1. Overview
List of Products
Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part no.
Table 1.3
List of Products
Code Flash
Memory
Capacity
RAM
Capacity
Data Flash
Memory
Capacity
Operating
Frequency
(Max.)
Encryption
Module
Operating
temperature
(°C)
Not available
–40 to +85
Group
Part No.
Package
RX72M
(D-version)
R5F572MNDDFC
PLQP0176KB-C
4 Mbytes
1 Mbyte
32 Kbytes
240 MHz
R5F572MNHDFC
PLQP0176KB-C
4 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Available
–40 to +85
R5F572MDDDFC
PLQP0176KB-C
2 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Not available
–40 to +85
R5F572MDHDFC
PLQP0176KB-C
2 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Available
–40 to +85
R5F572MNDDFB
PLQP0144KA-B
4 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Not available
–40 to +85
R5F572MNHDFB
PLQP0144KA-B
4 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Available
–40 to +85
R5F572MDDDFB
PLQP0144KA-B
2 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Not available
–40 to +85
R5F572MDHDFB
PLQP0144KA-B
2 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Available
–40 to +85
R5F572MNDDFP
PLQP0100KB-B
4 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Not available
–40 to +85
R5F572MNHDFP
PLQP0100KB-B
4 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Available
–40 to +85
R5F572MDDDFP
PLQP0100KB-B
2 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Not available
–40 to +85
RX72M
(G-version)
R5F572MDHDFP
PLQP0100KB-B
2 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Available
–40 to +85
R5F572MNDDBD
PLBG0224GA-A
4 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Not available
–40 to +85
R5F572MNHDBD
PLBG0224GA-A
4 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Available
–40 to +85
R5F572MDDDBD
PLBG0224GA-A
2 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Not available
–40 to +85
R5F572MDHDBD
PLBG0224GA-A
2 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Available
–40 to +85
R5F572MNDDBG
PLBG0176GA-A
4 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Not available
–40 to +85
R5F572MNHDBG
PLBG0176GA-A
4 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Available
–40 to +85
R5F572MDDDBG
PLBG0176GA-A
2 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Not available
–40 to +85
R5F572MDHDBG
PLBG0176GA-A
2 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Available
–40 to +85
R5F572MNDGFC
PLQP0176KB-C
4 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Not available
–40 to +105
R5F572MNHGFC
PLQP0176KB-C
4 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Available
–40 to +105
R5F572MDDGFC
PLQP0176KB-C
2 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Not available
–40 to +105
R5F572MDHGFC
PLQP0176KB-C
2 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Available
–40 to +105
R5F572MNDGFB
PLQP0144KA-B
4 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Not available
–40 to +105
R5F572MNHGFB
PLQP0144KA-B
4 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Available
–40 to +105
R5F572MDDGFB
PLQP0144KA-B
2 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Not available
–40 to +105
R5F572MDHGFB
PLQP0144KA-B
2 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Available
–40 to +105
R5F572MNDGFP
PLQP0100KB-B
4 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Not available
–40 to +105
R5F572MNHGFP
PLQP0100KB-B
4 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Available
–40 to +105
R5F572MDDGFP
PLQP0100KB-B
2 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Not available
–40 to +105
R5F572MDHGFP
PLQP0100KB-B
2 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Available
–40 to +105
R5F572MNDGBD
PLBG0224GA-A
4 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Not available
–40 to +105
–40 to +105
R5F572MNHGBD
PLBG0224GA-A
4 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Available
R5F572MDDGBD
PLBG0224GA-A
2 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Not available
–40 to +105
R5F572MDHGBD
PLBG0224GA-A
2 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Available
–40 to +105
R5F572MNDGBG
PLBG0176GA-A
4 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Not available
–40 to +105
R5F572MNHGBG
PLBG0176GA-A
4 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Available
–40 to +105
R5F572MDDGBG
PLBG0176GA-A
2 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Not available
–40 to +105
R5F572MDHGBG
PLBG0176GA-A
2 Mbytes
1 Mbyte
32 Kbytes
240 MHz
Available
–40 to +105
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 15 of 180
RX72M Group
R
5
F
1. Overview
5 7
2 M
N
D
D
B D
Package type, number of pins, and pin pitch
BD: LFBGA/224/0.80
FC: LFQFP/176/0.50
BG: LFBGA/176/0.80
FB : LFQFP/144/0.50
FP : LFQFP/100/0.50
D : Operating peripheral temperature: –40 to +85°C
G : Operating peripheral temperature: –40 to +105°C
D : Encryption module not included
H : Encryption module included
Code flash memory, RAM, and data flash memory capacity
N : 4 Mbytes/1 Mbyte/32 Kbytes
D : 2 Mbytes/1 Mbyte/32 Kbytes
Group name
RX72M Group
Series name
RX700 Series
Type of memory
F : Flash memory version
Renesas MCU
Renesas semiconductor product
Figure 1.1
How to Read the Product Part Number
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 16 of 180
RX72M Group
1.3
1. Overview
Block Diagram
DMAC × 8 channels
DTC
EDMAC × 3 channels
GLCDC
DRW2D
RAM
Internal main bus 2
Operand bus
ECCRAM
Instruction bus
Expansion
RAM
RX CPU
MPU
Clock
generation
circuit
CAC:
ICU:
BSC:
MPU:
DMAC:
EXDMAC:
DTC:
ELC:
MTU:
POE3:
GPTW:
POEG:
TPU:
PPG:
TMR:
CMT:
CMTW:
RTC:
WDT:
IWDT:
ETHERC:
Internal main bus 1
ROM
ROM Cache
Internal peripheral buses 1 to 6
Figure 1.2 shows a block diagram.
CAC
ICU
ELC
MTU × 9 channels
POE3
GPTW × 4 channels
POEG
TPU × 6 channels (unit 0)
PPG (unit 0)
PPG (unit 1)
TMR × 2 channels (unit 0)
TMR × 2 channels (unit 1)
CMT × 2 channels (unit 0)
CMT × 2 channels (unit 1)
CMTW × 1 channel (unit 0)
CMTW × 1 channel (unit 1)
RTC
WDT
IWDT
ETHERC × 2 channels
EPTPC
PMGI × 2 channels
ESC
USB × 1 port
SCIh × 1 channel
SCIi × 5 channels
SCIj × 7 channels
RIIC × 3 channels
CAN × 3 channels
SSIE × 2 channels
RSPI × 3 channels
QSPI
CRC
SDHI
MMCIF
PDC
TFU
Trusted Secure IP*1
DSMIF × 3 channels (unit 0)
DSMIF × 3 channels (unit 1)
12-bit A/D converter × 8 channels (unit 0)
12-bit A/D converter × 21 channels (unit 1)
12-bit D/A converter × 2 channels
Temperature sensor
DOC
Standby RAM
Data flash
EXDMAC
Clock frequency accuracy measurement circuit
Interrupt controller
Bus controller
Memory protection unit
DMA controller
EXDMA controller
Data transfer controller
Event link controller
Multi-function timer pulse unit 3
Port output enable 3
General PWM timer
GPTW port output enable
16-bit timer pulse unit
Programmable pulse unit
8-bit timer
Compare match timer
Compare match timer W
Realtime clock
Watchdog timer
Independent watchdog timer
Ethernet controller
BSC
External bus
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port B
Port C
Port D
Port E
Port F
Port G
Port H
Port J
Port K
Port L
Port M
Port N
Port Q
EPTPC:
PTP module for the ethernet controller
EDMAC: DMA controller for the ethernet controller
PMGI:
Phy management interface
ESC:
EtherCAT slave controller
USB:
USB2.0 FS host/function module
SCIj, SCIi, SCIh: Serial communications interface
RIIC:
I2C-bus interface
CAN:
CAN module
SSIE:
Serial sound interface enhanced
RSPI:
Serial communications interface
QSPI:
Quad serial peripheral interface
CRC:
CRC calculator
SDHI:
SD host interface
MMCIF:
MultiMediaCard interface
PDC:
Parallel data capture unit
GLCDC: Graphic LCD controller
DRW2D: 2D drawing engine
TFU:
Arithmetic unit for trigonometric functions
Trusted Secure IP: Trusted secure IP*1
DSMIF:
Delta-sigma modulator interface
DOC:
Data operation circuit
Note 1. Optional
Figure 1.2
Block Diagram
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 17 of 180
RX72M Group
1.4
1. Overview
Pin Functions
Table 1.4 lists the pin functions.
Table 1.4
Pin Functions (1/9)
Classifications
Pin Name
I/O
Description
Digital power supply
VCC
Input
Power supply pin. Connect this pin to the system power supply.
Connect the pin to VSS via a 0.1-µF multilayer ceramic
capacitor. The capacitor should be placed close to the pin.
VCL
Input
Connect this pin to VSS via a 0.22-µF multilayer ceramic
capacitor. The capacitor should be placed close to the pin.
VSS
Input
Ground pin. Connect it to the system power supply (0 V).
VBATT
Input
Backup power pin
XTAL
Output
Input/output pins for a crystal resonator. An external clock signal
can be input through the EXTAL pin.
Clock
EXTAL
Input
BCLK
Output
Outputs the external bus clock for external devices.
SDCLK
Output
Outputs the SDRAM-dedicated clock.
Input/output pins for the sub-clock oscillator. Connect a crystal
resonator between XCOUT and XCIN.
XCOUT
Output
XCIN
Input
CLKOUT
Output
Clock output pin.
Clock frequency accuracy
measurement
CACREF
Input
Reference clock input pin for the clock frequency accuracy
measurement circuit
Operating mode control
MD
Input
Input pin for setting the operating mode. The signal level on this
pin must not be changed during operation.
UB
Input
USB boot mode enable pin
UPSEL
Input
Selects the power supply method in USB boot mode.
The low level selects self-power mode and the high level selects
bus power mode.
RES#
Input
Reset signal input pin. This MCU enters the reset state when
this signal goes low.
EMLE
Input
Input pin for the on-chip emulator enable signal. When the onchip emulator is used, this pin should be driven high. When not
used, it should be driven low.
BSCANP
Input
Boundary scan enable pin. Boundary scan is enabled when this
pin goes high. When not used, it should be driven low.
FINED
I/O
FINE interface pin
TRST#
Input
TMS
Input
On-chip emulator or boundary scan pins. When the EMLE pin is
driven high, these pins are dedicated for the on-chip emulator.
TDI
Input
TCK
Input
TDO
Output
TRCLK
Output
This pin outputs the clock for synchronization with the trace
data.
TRSYNC, TRSYNC1
Output
These pins indicate that output from the TRDATA0 to TRDATA7
pins is valid.
TRDATA0 to TRDATA7
Output
These pins output the trace information.
Address bus
A0 to A23
Output
Output pins for the address
Data bus
D0 to D31
I/O
Input and output pins for the bidirectional data bus
Multiplexed bus
A0/D0 to A15/D15
I/O
Address/data multiplexed bus
System control
On-chip emulator
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 18 of 180
RX72M Group
Table 1.4
1. Overview
Pin Functions (2/9)
Classifications
Pin Name
I/O
Description
Bus control
RD#
Output
Strobe signal which indicates that reading from the external bus
interface space is in progress
WR#
Output
Strobe signal which indicates that writing to the external bus
interface space is in progress, in 1-write strobe mode
WR0# to WR3#
Output
Strobe signals which indicate that either group of data bus pins
(D7 to D0, D15 to D8, D23 to D16 and D31 to D24) is valid in
writing to the external bus interface space, in byte strobe mode
BC0# to BC3#
Output
Strobe signals which indicate that either group of data bus pins
(D7 to D0, D15 to D8, D23 to D16 and D31 to D24) is valid in
access to the external bus interface space, in 1-write strobe
mode
ALE
Output
Address latch signal when address/data multiplexed bus is
selected
WAIT#
Input
Input pin for wait request signals in access to the external space
CS0# to CS7#
Output
Select signals for CS areas
SDRAM interface
EXDMA controller
Interrupt
Multi-function timer pulse
unit 3
Port output enable 3
CKE
Output
SDRAM clock enable signal
SDCS#
Output
SDRAM chip select signal
RAS#
Output
SDRAM row address strobe signal
CAS#
Output
SDRAM column address strove signal
WE#
Output
SDRAM write enable pin
DQM0 to DQM3
Output
SDRAM I/O data mask enable signals
EDREQ0, EDREQ1
Input
External DMA transfer request pins
EDACK0, EDACK1
Output
Single address transfer acknowledge signals
NMI
Input
Non-maskable interrupt request pin
IRQ0 to IRQ15, IRQ0-DS to
IRQ15-DS
Input
Maskable interrupt request pins
MTIOC0A, MTIOC0B,
MTIOC0C, MTIOC0D
I/O
The TGRA0 to TGRD0 input capture input/output compare
output/PWM output pins
MTIOC1A, MTIOC1B
I/O
The TGRA1 and TGRB1 input capture input/output compare
output/PWM output pins
MTIOC2A, MTIOC2B
I/O
The TGRA2 and TGRB2 input capture input/output compare
output/PWM output pins
MTIOC3A, MTIOC3B,
MTIOC3C, MTIOC3D
I/O
The TGRA3 to TGRD3 input capture input/output compare
output/PWM output pins
MTIOC4A, MTIOC4B,
MTIOC4C, MTIOC4D
I/O
The TGRA4 to TGRD4 input capture input/output compare
output/PWM output pins
MTIC5U, MTIC5V, MTIC5W
Input
The TGRU5, TGRV5, and TGRW5 input capture input/dead
time compensation input pins
MTIOC6A, MTIOC6B,
MTIOC6C, MTIOC6D
I/O
The TGRA6 to TGRD6 input capture input/output compare
output/PWM output pins
MTIOC7A, MTIOC7B,
MTIOC7C, MTIOC7D
I/O
The TGRA7 to TGRD7 input capture input/output compare
output/PWM output pins
MTIOC8A, MTIOC8B,
MTIOC8C, MTIOC8D
I/O
The TGRA8 to TGRD8 input capture input/output compare
output/PWM output pins
MTCLKA, MTCLKB, MTCLKC,
MTCLKD
Input
Input pins for external clock signals or for phase counting mode
clock signals
POE0#, POE4#, POE8#,
POE10#, POE11#
Input
Input pins for request signals to place the MTU in the high
impedance state
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Nov 15, 2023
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RX72M Group
Table 1.4
1. Overview
Pin Functions (3/9)
Classifications
Pin Name
I/O
Description
General PWM timer W
GTETRGA, GTETRGB,
GTETRGC, GTETRGD
Input
Input pins for the external trigger signals
GTIOC0A to GTIOC3A,
GTIOC0B to GTIOC3B
I/O
Input capture input/output compare output/PWM output pins
GTADSM0, GTADSM1
Output
Output pins for monitoring A/D conversion start requests.
TIOCA0, TIOCB0, TIOCC0,
TIOCD0
I/O
The TGRA0 to TGRD0 input capture input/output compare
output/PWM output pins
TIOCA1, TIOCB1
I/O
The TGRA1 and TGRB1 input capture input/output compare
output/PWM output pins
TIOCA2, TIOCB2
I/O
The TGRA2 and TGRB2 input capture input/output compare
output/PWM output pins
TIOCA3, TIOCB3, TIOCC3,
TIOCD3
I/O
The TGRA3 to TGRD3 input capture input/output compare
output/PWM output pins
TIOCA4, TIOCB4
I/O
The TGRA4 and TGRB4 input capture input/output compare
output/PWM output pins
TIOCA5, TIOCB5
I/O
The TGRA5 and TGRB5 input capture input/output compare
output/PWM output pins
TCLKA, TCLKB, TCLKC,
TCLKD
Input
Input pins for external clock signals or for phase counting mode
clock signals
Programmable pulse
generator
PO0 to PO31
Output
Output pins for the pulse signals
8-bit timer
TMO0 to TMO3
Output
Compare match output pins
16-bit timer pulse unit
Compare match timer W
Serial communications
interface (SCIj)
TMCI0 to TMCI3
Input
Input pins for external clocks to be input to the counter
TMRI0 to TMRI3
Input
Input pins for the counter reset
TIC0 to TIC3
Input
Input pins for CMTW
TOC0 to TOC3
Output
Output pins for CMTW
Asynchronous mode/clock synchronous mode
SCK0 to SCK6
I/O
Input/output pins for the clock
RXD0 to RXD6
Input
Input pins for received data
TXD0 to TXD6
Output
Output pins for transmitted data
CTS0# to CTS6#
Input
Input pins for controlling the start of transmission and reception
RTS0# to RTS6#
Output
Output pins for controlling the start of transmission and
reception
SSCL0 to SSCL6
I/O
Input/output pins for the I2C clock
SSDA0 to SSDA6
I/O
Input/output pins for the I2C data
SCK0 to SCK6
I/O
Input/output pins for the clock
SMISO0 to SMISO6
I/O
Input/output pins for slave transmission of data
Simple I2C mode
Simple SPI mode
SMOSI0 to SMOSI6
I/O
Input/output pins for master transmission of data
SS0# to SS6#
Input
Chip-select input pins
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Nov 15, 2023
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RX72M Group
Table 1.4
1. Overview
Pin Functions (4/9)
Classifications
Pin Name
I/O
Description
Serial communications
interface (SCIh)
Asynchronous mode/clock synchronous mode
SCK12
I/O
Input/output pin for the clock
RXD12
Input
Input pin for received data
TXD12
Output
Output pin for transmitted data
CTS12#
Input
Input pin for controlling the start of transmission and reception
RTS12#
Output
Output pin for controlling the start of transmission and reception
SSCL12
I/O
Input/output pin for the I2C clock
SSDA12
I/O
Input/output pin for the I2C data
Simple I2C mode
Simple SPI mode
SCK12
I/O
Input/output pin for the clock
SMISO12
I/O
Input/output pin for slave transmission of data
SMOSI12
I/O
Input/output pin for master transmission of data
SS12#
Input
Chip-select input pin
RXDX12
Input
Input pin for received data
TXDX12
Output
Output pin for transmitted data
SIOX12
I/O
Input/output pin for received or transmitted data
Extended serial mode
Serial communications
interface (SCIi)
Asynchronous mode/clock synchronous mode
SCK7 to SCK11
I/O
Input/output pins for the clock
RXD7 to RXD11
Input
Input pins for received data
TXD7 to TXD11
Output
Output pins for transmitted data
CTS7# to CTS11#
Input
Input pins for controlling the start of transmission and reception
RTS7# to RTS11#
Output
Output pins for controlling the start of transmission and
reception
SSCL7 to SSCL11
I/O
Input/output pins for the I2C clock
SSDA7 to SSDA11
I/O
Input/output pins for the I2C data
Simple I2C mode
Simple SPI mode
I2C bus interface
SCK7 to SCK11
I/O
Input/output pins for the clock
SMISO7 to SMISO11
I/O
Input/output pins for slave transmission of data
SMOSI7 to SMOSI11
I/O
Input/output pins for master transmission of data
SS7# to SS11#
Input
Chip-select input pins
SCL0[FM+], SCL1, SCL2,
SCL2-DS
I/O
Input/output pins for clocks. Bus can be directly driven by
the N-channel open drain
SDA0[FM+], SDA1, SDA2,
SDA2-DS
I/O
Input/output pins for data. Bus can be directly driven by
the N-channel open drain
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Nov 15, 2023
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RX72M Group
Table 1.4
1. Overview
Pin Functions (5/9)
Classifications
Pin Name
I/O
Description
Ethernet controller
REF50CK0, REF50CK1
Input
50-MHz reference clocks. These pins input reference signals for
transmission/reception timings in RMII mode.
RMII0_CRS_DV,
RMII1_CRS_DV
Input
These pins indicate that there are carrier detection signals and
valid receive data on RMIIn_RXD1 and RMIIn_RXD0 in RMII
mode.
RMII0_TXD0, RMII0_TXD1,
RMII1_TXD0, RMII1_TXD1
Output
2-bit transmit data in RMII mode
RMII0_RXD0, RMII0_RXD1,
RMII1_RXD0, RMII1_RXD1
Input
2-bit receive data in RMII mode
RMII0_TXD_EN,
RMII1_TXD_EN
Output
Output pins for data transmit enable signals in RMII mode
RMII0_RX_ER,
RMII1_RX_ER
Input
These pins indicate an error has occurred during reception of
data in RMII mode.
ET0_CRS, ET1_CRS
Input
Carrier detection/data reception enable pins
ET0_RX_DV, ET1_RX_DV
Input
These pins indicate that there are valid receive data on
ETn_ERXD3 to ETn_ERXD0.
ET0_EXOUT, ET1_EXOUT
Output
General-purpose external output pins
ET0_LINKSTA, ET1_LINKSTA
Input
Input link status from the PHY-LSI.
ET0_ETXD0 to ET0_ETXD3,
ET1_ETXD0 to ET1_ETXD3
Output
4 bits of MII transmit data
ET0_ERXD0 to ET0_ERXD3,
ET1_ERXD0 to ET1_ERXD3
Input
4 bits of MII receive data
ET0_TX_EN, ET1_TX_EN
Output
Transmit enable pins. These pins function as signals indicating
that transmit data are ready on ETn_ETXD3 to ETn_ETXD0.
ET0_TX_ER, ET1_TX_ER
Output
Transmit error pins. These pins function as signals notifying the
PHY-LSI of an error during transmission.
ET0_RX_ER, ET1_RX_ER
Input
Receive error pins. These pins function as signals to recognize
an error during reception.
ET0_TX_CLK, ET1_RX_CLK
Input
Transmit clock pins. These pins input reference signals for
output timings from ETn_TX_EN, ETn_ETXD3 to ETn_ETXD0,
and ETn_TX_ER.
ET0_RX_CLK, ET1_RX_CLK
Input
Receive clock pins. These pins input reference signals for input
timings to ETn_RX_DV, ETn_ERXD3 to ETn_ERXD0, and
ETn_RX_ER.
ET0_COL, ET1_COL
Input
Input collision detection signals.
ET0_WOL, ET1_WOL
Output
Receive Magic packets.
ET0_MDC, ET1_MDC
Output
Output reference clock signals for information transfer via
ETn_MDIO.
ET0_MDIO, ET1_MDIO
I/O
Input or output bidirectional signals for exchange of
management information between this MCU and the PHY-LSI.
CLKOUT25M
Output
25-MHz clock output pin for PHY clock input (used in common
by the EtherCAT module)
EPLSOUT0, EPLSOUT1
Output
Pulse output signals for time synchronization
PMGI0_MDC, PMGI1_MDC
Output
Reference clock signals for information transfer by
PMGIn_MDIO
PMGI0_MDIO, PMGI1_MDIO
I/O
Bi-directional signals for the exchange of management
information between the PHY LSI chip and this MCU
PHY management
interface
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Nov 15, 2023
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RX72M Group
Table 1.4
1. Overview
Pin Functions (6/9)
Classifications
EtherCAT slave controller
Pin Name
I/O
Description
CAT0_LINKSTA,
CAT1_LINKSTA
Input
PHY link signal input pins
CAT0_RX_CLK,
CAT1_RX_CLK
Input
Receive clock input pins
CAT0_RX_DV, CAT1_RX_DV
Input
Receive data enabling signal input pins
CAT0_ERXD0 to
CAT0_ERXD3,
CAT1_ERXD0 to
CAT1_ERXD3
Input
Receive data signal input pins
CAT0_RX_ER, CAT1_RX_ER
Input
Receive data error signal input pins
CAT0_TX_CLK,
CAT1_TX_CLK
Input
Transmit clock input pins
MII mode
CAT0_TX_EN, CAT1_TX_EN
Output
Transmit enabling signal output pins
CAT0_ETXD0 to
CAT0_ETXD3,
CAT1_ETXD0 to
CAT1_ETXD3
Output
Transmit data signal output pins
CAT0_MDC
Output
Management interface clock output pin
CAT0_MDIO
I/O
Management data signal input/output pin
CLKOUT25M
Output
25-MHz clock output pin for PHY clock input (used in common
by the EtherC module)
CATRESTOUT
Output
Output signal for resetting the PHY chip
CATLEDRUN
Output
EtherCAT run LED signal output pin
Exclusively for EtherCAT
USB 2.0 host/function
module
CAN module
CATIRQ
Output
EtherCAT IRQ signal output pin
CATLEDSTER
Output
EtherCAT dual-color state LED signal output pin
CATLEDERR
Output
EtherCAT error LED signal output pin
CATLINKACT0,
CATLINKACT1
Output
EtherCAT link/activity LED signal output pins
CATSYNC0, CATSYNC1
Output
EtherCAT sync signal output pins
CATLATCH0, CATLATCH1
Input
EtherCAT latch signal output pins
CATI2CCLK
Output
EtherCAT EEPROM I2C clock signal output pin
CATI2CDATA
I/O
EtherCAT EEPROM I2C data signal input/output pin
VCC_USB
Input
Power supply pin
VSS_USB
Input
Ground pin
USB0_DP
I/O
Input or output USB transceiver D+ data.
USB0_DM
I/O
Input or output USB transceiver D- data.
USB0_EXICEN
Output
Connect to the OTG power IC.
USB0_ID
Input
Connect to the OTG power IC.
USB0_VBUSEN
Output
USB VBUS power enable pin
USB0_OVRCURA/
USB0_OVRCURB
Input
USB overcurrent pins
USB0_VBUS
Input
USB cable connection/disconnection detection input pin
CRX0, CRX1, CRX2,
CRX1-DS
Input
Input pins
CTX0, CTX1, CTX2
Output
Output pins
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Nov 15, 2023
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RX72M Group
Table 1.4
1. Overview
Pin Functions (7/9)
Classifications
Pin Name
I/O
Description
Serial peripheral interface
RSPCKA-A/RSPCKA-B/
RSPCKB-A/RSPCKB-B/
RSPCKC-A/RSPCKC-B
I/O
Clock input/output pins
MOSIA-A/MOSIA-B/
MOSIB-A/MOSIB-B/
MOSIC-A/MOSIC-B
I/O
Input or output data output from the master
MISOA-A/MISOA-B/
MISOB-A/MISOB-B/
MISOC-A/MISOC-B
I/O
Input or output data output from the slave
SSLA0-A/SSLA0-B/
SSLB0-A/SSLB0-B/
SSLC0-A/SSLC0-B
I/O
Input or output pins for slave selection
SSLA1-A/SSLA1-B/
SSLB1-A/SSLB1-B/
SSLC1-A/SSLC1-B,
SSLA2-A/SSLA2-B/
SSLB2-A/SSLB2-B/
SSLC2-A/SSLC2-B,
SSLA3-A/SSLA3-B/
SSLB3-A/SSLB3-B/
SSLC3-A/SSLC3-B
Output
Output pins for slave selection
QSPCLK-A/QSPCLK-B/
QSPCLK-C
Output
QSPI clock output pins
QSSL-A/QSSL-B/QSSL-C
Output
QSPI slave output pins
QMO-A/QMO-B/QMO-C,
QIO0-A/QIO0-B/QIO0-C
I/O
Master transmit data/data 0
QMI-A/QMI-B/QMI-C,
QIO1-A/QIO1-B/QIO1-C
I/O
Master input data/data 1
QIO2-A/QIO2-B/QIO2-C,
QIO3-A/QIO3-B/QIO3-C
I/O
Data 2, data 3
Quad serial peripheral
interface
Serial sound interface
enhanced
MMC host interface
SD host interface
SSIBCK0, SSIBCK1
I/O
SSIE serial bit-clock pins
SSILRCK0, SSILRCK1
I/O
LR clock
SSITXD0
Output
Serial data output pin
SSIRXD0
Input
Serial data input pin
SSIDATA1
I/O
Serial data input/output pin
AUDIO_CLK
Input
External clock pin for audio
(input for an oversampling clock)
MMC_CLK-A/MMC_CLK-B
Output
MMC clock pins
MMC_CMD-A/MMC_CMD-B
I/O
Command/response pins
MMC_D7-A/MMC_D7-B to
MMC_D0-A/MMC_D0-B
I/O
Transmit data/receive data
MMC_CD-A/MMC_CD-B
Input
Card detection pins
MMC_RES#-A/MMC_RES#-B
Output
MMC reset output pins
SDHI_CLK-A/SDHI_CLK-B/
SDHI_CLK-C/SDHI_CLK-D
Output
SD clock output pins
SDHI_CMD-A/SDHI_CMD-B/
SDHI_CMD-C/SDHI_CMD-D
I/O
SD command output, response input signal pins
SDHI_D3-A/SDHI_D3-B/
SDHI_D3-C/SDHI_D3-D to
SDHI_D0-A/SDHI_D0-B/
SDHI_D0-C/SDHI_D0-D
I/O
SD data bus pins
SDHI_CD
Input
SD card detection pin
SDHI_WP
Input
SD write-protect signal
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 24 of 180
RX72M Group
Table 1.4
1. Overview
Pin Functions (8/9)
Classifications
Pin Name
I/O
Description
Delta-sigma modulator
interface
DSMCLK0 to DSMCLK5
I/O
Input/output pins for the clock
DSMDAT0 to DSMDAT5
Input
Input pins for data
Parallel data capture unit
PIXCLK
Input
Image transfer clock pin
VSYNC
Input
Vertical synchronization signal pin
Graphic-LCD controller
Realtime clock
HSYNC
Input
Horizontal synchronization signal pin
PIXD0 to PIXD7
Input
8-bit image data pins
PCKO
Output
Output pin for dot clock
LCD_CLK-A, LCD_CLK-B
Output
Panel clock output pins
LCD_TCON3-A/
LCD_TCON3-B to
LCD_TCON0-A/
LCD_TCON0-B
Output
Control signal output pins
LCD_DATA23-A/
LCD_DATA23-B to
LCD_DATA0-A/
LCD_DATA0-B
Output
LCD signal output pins
LCD_EXTCLK-A,
LCD_EXTCLK-B
Input
Panel clock source input pins
RTCOUT
Output
Output pin for 1-Hz/64-Hz clock
RTCIC0 to RTCIC2
Input
Time capture event input pins
AN000 to AN007,
AN100 to AN120
Input
Input pins for the analog signals to be processed by the A/D
converter
ADTRG0#, ADTRG1#
Input
Input pins for the external trigger signals that start the A/D
conversion
ANEX0
Output
Extended analog output pin
ANEX1
Input
Extended analog input pin
12-bit D/A converter
DA0, DA1
Output
Output pins for the analog signals to be processed by the D/A
converter
Analog power supply
AVCC0
Input
Analog voltage supply pin for the 12-bit A/D converter (unit 0).
Connect this pin to a branch from the VCC power supply.
Connect the pin to AVSS0 via a 0.1-µF multilayer ceramic
capacitor. The capacitor should be placed close to the pin.
AVSS0
Input
Analog ground pin for the 12-bit A/D converter (unit 0). Connect
this pin to a branch from the VSS ground power supply.
Connect the pin to AVCC0 via a 0.1-µF multilayer ceramic
capacitor. The capacitor should be placed close to the pin.
VREFH0
Input
Analog reference voltage supply pin for the 12-bit A/D converter
(unit 0). Connect this pin to VCC if the 12-bit A/D converter is
not to be used.
VREFL0
Input
Analog reference ground pin for the 12-bit A/D converter (unit
0). Connect this pin to VSS if the 12-bit A/D converter is not to
be used.
AVCC1
Input
Analog voltage supply and reference voltage supply pin for the
12-bit A/D converter (unit 1) and D/A converter. This pin also
supplies the analog voltage to the temperature sensor. Connect
this pin to a branch from the VCC power supply. Connect the
pin to AVSS1 via a 0.1-µF multilayer ceramic capacitor. The
capacitor should be placed close to the pin.
AVSS1
Input
Analog voltage supply and reference voltage supply pin for the
12-bit A/D converter (unit 1) and D/A converter. This pin also
supplies the analog ground voltage to the temperature sensor.
Connect this pin to a branch from the VSS ground power
supply. Connect the pin to AVCC1 via a 0.1-µF multilayer
ceramic capacitor. The capacitor should be placed close to the
pin.
12-bit A/D converter
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Nov 15, 2023
Page 25 of 180
RX72M Group
Table 1.4
1. Overview
Pin Functions (9/9)
Classifications
Pin Name
I/O
Description
I/O ports
P00 to P03, P05, P07
I/O
6-bit input/output pins
P10 to P17
I/O
8-bit input/output pins
P20 to P27
I/O
8-bit input/output pins
P30 to P37
I/O
8-bit input/output pins (P35: input pin)
P40 to P47
I/O
8-bit input/output pins
P50 to P57
I/O
8-bit input/output pins
P60 to P67
I/O
8-bit input/output pins
P70 to P77
I/O
8-bit input/output pins
P80 to P87
I/O
8-bit input/output pins
P90 to P97
I/O
8-bit input/output pins
Note:
PA0 to PA7
I/O
8-bit input/output pins
PB0 to PB7
I/O
8-bit input/output pins
PC0 to PC7
I/O
8-bit input/output pins
PD0 to PD7
I/O
8-bit input/output pins
PE0 to PE7
I/O
8-bit input/output pins
PF0 to PF5
I/O
6-bit input/output pins
PG0 to PG7
I/O
8-bit input/output pins
PJ0 to PJ3, PJ5
I/O
5-bit input/output pins
PH0 to PH7
I/O
8-bit input/output pins
PK0 to PK7
I/O
8-bit input/output pins
PL0 to PL7
I/O
8-bit input/output pins
PM0 to PM7
I/O
8-bit input/output pins
PN0 to PN5
I/O
6-bit input/output pins
PQ0 to PQ7
I/O
8-bit input/output pins
Note the following regarding pin names. For details, refer to section 1.5, Pin Assignments.
- We recommend using pins that have a letter (“-A”, “-B”, etc.) to indicate group membership appended to their names as
groups.
For the RSPI, QSPI, SDHI, MMC, and GLCDC interfaces, the AC portion of the electrical characteristics is measured for each
group.
- When the pin functions have “-DS” appended to their names, they can also be used as triggers for release from deep software
standby.
- RIIC pin functions that have [FM+] appended to their names support fast-mode plus.
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Nov 15, 2023
Page 26 of 180
RX72M Group
1.5
1. Overview
Pin Assignments
1.5.1
224-Pin LFBGA
RX72M Group
PLBG0224GA-A (224-pin LFBGA)
(Upper Perspective View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
15
P70
PE7
P66
P67
PG4
PG7
PA4
PA5
PA7
P72
PB4
PB6
PB7
PM3
PM5
15
14
PE1
PE4
P65
PG2
PG5
PG6
PA3
PA6
PB0
PB3
PB2
PC0
PC1
PM4
P74
14
13
P62
PE2
PE5
VSS
PE6
PG3
PA2
VSS
P71
PB5
VCC
PM7
PM6
PC2
P75
13
12
P61
P63
VSS
PE3
VCC
PA0
PA1
VCC
PB1
VSS
PN4
PL6
P76
PL2
PL4
12
11
PD7
VCC
P64
PE0
PQ4
PM1
PM0
PL0
PN5
PM2
P77
PL5
PK2
PC4
PC3
11
10
PG0
PD6
P60
PG1
PQ5
VSS
VCC
P73
PL1
PL3
PL7
PK0
P80
P82
PC5
10
9
PD3
PD4
P97
PD5
PQ3
PQ6
PN2
PN3
PK3
PK1
P81
P83
PC7
VSS
PC6
9
8
P96
P95
VCC
VSS
PQ1
PN1
PQ2
PQ7
P53*1
P50
P52
P51
VCC
P11
P55
8
7
PD2
P94
PD1
P93
PQ0
PK6
RES#
PJ3
P15
P10
VCC
VSS
P56
P57
P54
7
6
PD0
VCC
P90
P02
PN0
EMLE
PF5
BSCANP
PH2
PH1
PJ2
P84
PJ1
VSS_US USB0_D
6
B
P
5
P92
P91
VSS
P01
P07
PK5
PJ5
P32
P30
PF0
VCC
PJ0
P13
VCC_US USB0_D
5
B
M
4
P41
P46
P44
P40
P43
PK4
MD/
FINED
P33
P31
PH5
P24
VSS
P85
P14
P12
4
P42
P05
P03
P00
PF4
VCC
P35
PF3
PH4
PF1
P25
P86
P20
P16
3
2 VREFH0 AVCC0
AVCC1
P47
VSS
VBATT
VSS
P34
PF2
PH6
P27
P23
PH0
P17
P87
2
1
1
3 VREFL0
NC
AVSS0
AVSS1
P45
VCL
XCIN
XCOUT
XTAL
EXTAL
PH7
PH3
P26
P22
PK7
P21
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Note:
This figure indicates the power supply pins and I/O port pins. For the pin configuration, refer to Table 1.5, List
of Pin and Pin Functions (224-Pin LFBGA).
Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is
enabled.
Figure 1.3
Pin Assignment (224-Pin LFBGA)
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 27 of 180
RX72M Group
1.5.2
1. Overview
176-Pin LFBGA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
15
PE2
PE3
P70
P65
P67
VSS
VCC
PG7
PA6
PB0
P72
PB4
VSS
VCC
PC1
15
14
PE1
PE0
VSS
PE7
PG3
PA0
PA1
PA2
PA7
VCC
PB1
PB5
P73
P75
P74
14
13
P63
P64
PE4
VCC
PG2
PG4
PG6
PA3
VSS
P71
PB3
PB7
PC0
PC2
P76
13
12
P60
VSS
P62
PE5
PE6
P66
PG5
PA4
PA5
PB2
PB6
P77
PC3
PC4
P80
12
11
PD6
PG1
VCC
P61
P81
P82
PC6
VCC
11
10
P97
PD4
PG0
PD7
PC5
PC7
P83
VSS
10
9
VCC
P96
PD3
PD5
P50
P51
P52
P53*1
9
8
P94
PD1
PD2
VSS
P55
P54
P10
P11
8
7
VSS
P92
PD0
P95
P85
P84
P57
P56
7
6
VCC
P91
P90
P93
PJ1
PJ0
VSS_
USB
USB0_
DP
6
5
P46
P47
P45
P44
PJ2
P12
VCC_
USB
USB0_
DM
5
4
P42
P41
P43
P00
VSS
BSCANP
PF4
P35
PF3
PF1
P25
P86
P15
P14
P13
4
3 VREFL0
P40
VREFH0
P03
PF5
PJ3
MD/
FINED
RES#
P34
PF2
PF0
P24
P22
P87
P16
3
2 AVCC0
P07
AVCC1
P02
EMLE
VCL
XCOUT
VSS
VCC
P32
P30
P26
P23
P17
P20
2
1
AVSS0
P05
AVSS1
P01
PJ5
VBATT
XCIN
XTAL
EXTAL
P33
P31
P27
VCC
VSS
P21
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
RX72M Group
PTBG0176GA-A
(176-pin LFBGA)
(Upper Perspective View)
Note:
This figure indicates the power supply pins and I/O port pins. For the pin configuration, refer to Table 1.6, List
of Pin and Pin Functions (176-Pin LFBGA).
Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is
enabled.
Figure 1.4
Pin Assignment (176-Pin LFBGA)
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 28 of 180
RX72M Group
176-Pin LFQFP
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
133
88
134
87
135
86
136
85
137
84
138
83
139
82
140
81
141
80
142
79
143
78
144
77
145
76
146
75
147
74
148
73
149
72
150
71
RX72M Group
PLQP0176KB-C
(176-pin LFQFP)
(Top view)
151
152
153
154
155
156
157
158
70
69
68
67
66
65
64
63
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P74
P75
PC2
P76
P77
PC3
PC4
P80
P81
P82
PC5
PC6
PC7
VCC
P83
VSS
P50
P51
P52
P53*1
P10
P11
P54
P55
P56
P57
P84
P85
PJ0
PJ1
PJ2
VSS_USB
USB0_DP
USB0_DM
VCC_USB
P12
P13
P14
P15
P86
P16
P87
P17
P20
AVSS0
P05
AVCC1
P03
AVSS1
P02
P01
P00
PF5
EMLE
PJ5
VSS
PJ3
VCL
VBATT
NC
PF4
MD/FINED
XCIN
XCOUT
RES#
P37/XTAL
VSS
P36/EXTAL
VCC
P35
P34
P33
P32
PF3
PF2
P31
P30
PF1
PF0
P27
P26
P25
VCC
P24
VSS
P23
P22
P21
20
45
19
46
176
18
47
175
17
48
174
16
49
173
15
50
172
14
51
171
13
52
170
12
53
169
11
54
168
10
55
167
9
56
166
8
57
165
7
58
164
6
59
163
5
60
162
4
61
161
3
62
160
2
159
1
PE2
PE1
PE0
P64
P63
P62
P61
VSS
P60
VCC
PD7
PG1
PD6
PG0
PD5
PD4
P97
PD3
VSS
P96
VCC
PD2
P95
PD1
P94
PD0
P93
P92
P91
VSS
P90
VCC
P47
P46
P45
P44
P43
P42
P41
VREFL0
P40
VREFH0
AVCC0
P07
132
PE3
PE4
PE5
VSS
P70
VCC
PE6
PE7
P65
PG2
P66
PG3
P67
PG4
PA0
VSS
PG5
VCC
PA1
PG6
PA2
PG7
PA3
PA4
PA5
PA6
PA7
VSS
PB0
VCC
P71
P72
PB1
PB2
PB3
PB4
PB5
PB6
PB7
P73
VSS
PC0
VCC
PC1
1.5.3
1. Overview
Note:
This figure indicates the power supply pins and I/O port pins. For the pin configuration, refer to Table 1.7, List
of Pin and Pin Functions (176-Pin LFQFP).
Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is
enabled.
Figure 1.5
Pin Assignment (176-Pin LFQFP)
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 29 of 180
RX72M Group
PA3
VSS
PA4
VCC
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
P73
VSS
PC0
VCC
91
90
89
88
87
85
83
81
79
76
75
74
73
PG7
92
77
PG6
PA2
94
78
PG5
PA1
96
80
PA0
97
82
P66
P67
99
84
PG2
100
86
P65
101
93
PE7
102
95
VCC
PE6
104
98
PE5
VSS
103
PE4
106
105
PE3
107
144-Pin LFQFP
108
1.5.4
1. Overview
PE2
109
PE1
110
71
P74
PE0
111
70
P75
P64
112
69
PC2
P63
113
68
P62
114
67
P76
P77
P61
VSS
115
66
PC3
116
65
PC4
P60
117
64
P80
VCC
118
63
P81
PD7
119
62
P82
PG1
120
61
PC5
PD6
121
60
PC6
PG0
122
59
PD5
123
58
PC7
VCC
PD4
124
P97
PD3
125
P96
127
PD2
128
PD1
129
PD0
RX72M Group
PLQP0144KA-B
(144-pin LFQFP)
(Top view)
72
57
PC1
144
37
P87
11
12
PJ3
VCL
VBATT
MD/FINED
10
9
EMLE
VSS
5
AVSS1
P02
8
4
P03
7
3
AVCC1
P01
P00
2
P05
6
1
AVSS0
36
38
AVCC0
P17
39
143
35
142
P15
P86
P16
P20
40
34
141
P21
P13
VREFL0
P40
VREFH0
33
41
32
P14
140
31
42
30
139
P24
P23
P22
P12
P42
P41
P25
VCC_USB
43
29
44
138
28
137
P43
P26
P44
P27
USB0_DP
USB0_DM
27
45
26
46
136
P31
P30
135
25
P90
VCC
24
PJ2
VSS_USB
P32
47
23
134
P34
P33
VSS
22
48
P35/NMI
133
21
P56
P91
VCC
49
20
132
P36/EXTAL
P55
P92
19
50
VSS
131
18
P54
P93
17
51
P37/XTAL
P53*1
130
16
P52
52
15
P51
53
XCIN
P50
54
XCOUT
RES#
55
126
14
P83
VSS
13
56
Note:
This figure indicates the power supply pins and I/O port pins. For the pin configuration,
refer to Table 1.8, List of Pin and Pin Functions (144-Pin LFQFP).
Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled.
Figure 1.6
Pin Assignment (144-Pin LFQFP)
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 30 of 180
RX72M Group
Note:
Figure 1.7
PE3
PE4
PE5
PG2
P66
P67
PA0
PG5
PA1
PG6
PA2
PA3
VSS
PA4
VCC
PA6
PB0
PB1
PB3
PB4
PB5
PB6
PB7
PC2
PC4
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100-Pin LFQFP
P64
76
50
P63
77
49
P80
P81
P62
78
48
P82
P61
79
47
PC5
VSS
80
46
PC6
P60
81
45
PC7
VCC
82
44
VCC
PD7
83
43
VSS
PD6
84
42
P50
P97
85
41
P52
P96
86
40
P51
PD2
87
39
P56
PD1
88
38
VSS_USB
P93
89
37
USB0_DP
P92
90
36
USB0_DM
P91
91
35
VCC_USB
VSS
92
34
P14
P90
93
33
P15
VCC
94
32
P86
P42
95
31
P16
P41
96
30
P87
VREFL0
97
29
P17
P40
98
28
P20
VREFH0
99
27
P21
AVCC0
100
26
P23
14
15
16
17
18
19
20
21
22
23
24
25
P36/EXTAL
VCC
P35/NMI
P34
P33
P32
P31
P30
P27
P26
P25
P24
9
XCIN
13
8
MD/FINED
VSS
7
VBATT
12
6
VCL
P37/XTAL
5
EMLE
11
4
P00
RES#
3
AVSS1
10
2
XCOUT
1
AVSS0
RX72M Group
PLQP0100KB-B
(100-pin LFQFP)
(Top view)
AVCC1
1.5.5
1. Overview
This figure indicates the power supply pins and I/O port pins. For the pin configuration, refer to Table 1.9, List of Pin
and Pin Functions (100-Pin LFQFP).
Pin Assignment (100-Pin LFQFP)
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 31 of 180
RX72M Group
1.6
1. Overview
List of Pin and Pin Functions
1.6.1
224-Pin LFBGA
Table 1.5
List of Pin and Pin Functions (224-Pin LFBGA) (1/14)
Pin
Number
Timer
Power
Supply
Clock
224-Pin System
LFBGA Control
A1
NC
A2
VREFH0
A3
VREFL0
I/O Port
Communication
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
Memory I/F
Camera I/F
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
GLCDC
Interrupt
A/D
D/A
IRQ9-DS
AN001
DSMIF
A4
P41
A5
P92
D18/A18
A6
PD0
D0[A0/D0] POE4#
LCD_EXT IRQ0
CLK-B
AN108
A7
PD2
D2[A2/D2] MTIOC4D/ GTIOC0B MISOC-A/ ET1_EXO QIO2-B/
LCD_DAT IRQ2
TIC2
CRX0
UT
SDHI_D2- A22-B
B/
MMC_D2-B
AN110
A8
TRDATA5 P96
A9
PD3
POE4#
RXD7/
SMISO7/
SSCL7
ET1_CRS/
RMII1_CR
S_DV/
CAT1_RX
_DV
GTIOC1B
D22/A22
D3[A3/D3] MTIOC8D/ GTIOC0A RSPCKC- ET1_WOL QIO3-B/
LCD_DAT IRQ3
TOC2/
A
SDHI_D3- A21-B
POE8#
B/
MMC_D3-B
TRDATA6 PG0
A11
PD7
D7[A7/D7] MTIC5U/
POE0#
A12
P61
SDCS#/
D0[A0/D0]/
CS1#
ET1_ERX
D1/
RMII1_RX
D1/
CAT1_ER
XD1
A13
P62
RAS#/
D1[A1/D1]/
CS2#
ET1_ERX
D0/
RMII1_RX
D0/
CAT1_ER
XD0
A14
PE1
D9[A9/D9]/ MTIOC4C/ GTIOC1B TXD12/
D1[A1/D1] MTIOC3B/
SMOSI12/
PO18
SSDA12/
TXDX12/
SIOX12/
SSLB2-B
A15
P70
SDCLK
AVSS0
B2
AVCC0
B3
D24
P42
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
DSMCLK4
ET1_ERX
D2/
CAT1_ER
XD2
A10
B1
AN116
AN111
ET1_RX_
CLK/
REF50CK
1/
CAT1_RX
_CLK
SSLC3-A
ET1_RX_
ER/
RMII1_RX
_ER/
CAT1_RX
_ER
QMI-B/
LCD_DAT IRQ7
QIO1-B/
A17-B
SDHI_D1B/
MMC_D1-B
AN107
MMC_D5-B LCD_DAT
A15-B
ANEX1
CATLINKA
CT0
IRQ10-DS AN002
Page 32 of 180
RX72M Group
Table 1.5
1. Overview
List of Pin and Pin Functions (224-Pin LFBGA) (2/14)
Pin
Number
Timer
Power
Supply
Clock
224-Pin System
LFBGA Control
I/O Port
Communication
Memory I/F
Camera I/F
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
SCK7
GLCDC
Interrupt
A/D
D/A
DSMIF
B4
P46
B5
P91
D17/A17
B7
P94
D20/A20
ET1_ERX
D0/
RMII1_RX
D0/
CAT1_ER
XD0
B8
TRDATA4 P95
D21/A21
ET1_ERX
D1/
RMII1_RX
D1/
CAT1_ER
XD1
B9
PD4
D4[A4/D4] MTIOC8B/
POE11#
SSLC0-A
ET1_MDI
O/
PMGI1_M
DIO
QSSL-B/
LCD_DAT IRQ4
SDHI_CMD A20-B
-B/
MMC_CMD
-B
AN112
B10
PD6
D6[A6/D6] MTIC5V/
MTIOC8A/
POE4#
SSLC2-A
ET1_RX_
CLK/
REF50CK
1/
CAT1_RX
_CLK
QMO-B/
LCD_DAT IRQ6
QIO0-B/
A18-B
SDHI_D0B/
MMC_D0-B
AN106
B12
P63
CAS#/
D2[A2/D2]/
CS3#
B13
PE2
D10[A10/ MTIOC4A/ GTIOC0B RXD12/
D10]/
PO23/TIC3
SMISO12/
D2[A2/D2]
SSCL12/
RXDX12/
SSLB3-B
MMC_D6-B LCD_DAT IRQ7-DS
A14-B
AN100
B14
PE4
D12[A12/ MTIOC4D/ GTIOC1A SSLB0-B
D12]/
MTIOC1A/
D4[A4/D4] PO28
B15
PE7
D15[A15/ MTIOC6A/ GTIOC3A MISOB-B
D15]/
TOC1
D7[A7/D7]
B6
B11
AN115
DSMDAT5
VCC
VCC
C1
AVSS1
C2
AVCC1
C3
P05
C4
P44
C5
IRQ14-DS AN006
ET1_COL
ET1_ETX
D1/
RMII1_TX
D1/
CAT1_ET
XD1
ET0_ERX
D2/
CAT0_ER
XD2
LCD_DAT
A12-B
AN102
SDHI_WP/ LCD_DAT IRQ7
MMC_RES A9-B
#-B
SSILRCK1
IRQ13
AN105
DA1
IRQ12-DS AN004
VSS
C6
P90
D16/A16
C7
PD1
D1[A1/D1] MTIOC4B/ GTIOC1A MOSIC-A/
POE0#
CTX0
C8
VCC
C9
TRSYNC1 P97
D23/A23
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
TXD7/
SMOSI7/
SSDA7
ET1_RX_
DV/
CAT1_RX
_DV
AN114
LCD_DAT IRQ1
A23-B
DSMCLK5
AN109
ET1_ERX
D3/
CAT1_ER
XD3
Page 33 of 180
RX72M Group
Table 1.5
1. Overview
List of Pin and Pin Functions (224-Pin LFBGA) (3/14)
Pin
Number
Timer
Communication
Memory I/F
Camera I/F
Power
Supply
Clock
224-Pin System
LFBGA Control
I/O Port
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
C10
P60
CS0#
ET1_TX_E
N/
RMII1_TX
D_EN/
CAT1_TX_
EN
C11
P64
WE#/
D3[A3/D3]/
CS4#
ET1_ETX
D0/
RMII1_TX
D0/
CAT1_ET
XD0
C13
PE5
D13[A13/ MTIOC4C/ GTIOC0A RSPCKBD13]/
MTIOC2B
B
D5[A5/D5]
ET0_RX_
CLK/
REF50CK
0/
CAT0_RX
_CLK
C14
P65
CKE/CS5#
C15
P66
DQM0/
CS6#
D1
P45
IRQ13-DS AN005
D2
P47
IRQ15-DS AN007
D3
P03
D4
P40
D5
P01
TMCI0
RXD6/
SMISO6/
SSCL6/
SSIBCK0
D6
P02
TMCI1
D7
P93
D19/A19
POE0#
PD5
D5[A5/D5] MTIC5W/
MTIOC8C/
MTCLKA/
POE10#
C12
D8
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
GLCDC
Interrupt
A/D
D/A
DSMIF
VSS
MTIOC7D
LCD_DAT IRQ5
A11-B
AN103
GTIOC2B CTX2
SSIDATA1
IRQ11
DA0
IRQ8-DS
AN000
CATLEDE QIO3-C
RR
IRQ9
AN119
SCK6/
SSIBCK1
CATLEDS
TER
IRQ10
AN120
CTS7#/
RTS7#/
SS7#
ET1_LINK
STA/
CAT1_LIN
KSTA
AN117
SSLC1-A
ET1_MDC/ QSPCLK-B/ LCD_DAT IRQ5
PMGI1_M SDHI_CLK- A19-B
DC
B/
MMC_CLKB
AN113
DSMDAT4
VSS
D9
D10
TRDATA7 PG1
D11
PE0
D8[A8/D8]/ MTIOC3D
D0[A0/D0]
GTIOC2B SCK12/
SSLB1-B
MMC_D4-B LCD_DAT
A16-B
ANEX0
D12
PE3
D11[A11/ MTIOC4B/ GTIOC2A CTS12#/
D11]/
PO26/
RTS12#/
D3[A3/D3] TOC3/
SS12#
POE8#
ET0_ERX MMC_D7-B LCD_DAT
D3/
A13-B
CAT0_ER
XD3
AN101
D26
ET1_TX_
CLK/
CAT1_TX_
CLK
D13
VSS
D14
TRDATA0 PG2
D15
P67
D25
DQM1/
CS7#
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
ET1_RX_
ER/
RMII1_RX
_ER/
CAT1_RX
_ER
MTIOC7C
GTIOC1B CRX2
EPLSOUT
1/
CATSYNC
1
IRQ15
Page 34 of 180
RX72M Group
Table 1.5
1. Overview
List of Pin and Pin Functions (224-Pin LFBGA) (4/14)
Pin
Number
Timer
Power
Supply
Clock
224-Pin System
LFBGA Control
E1
VCL
E2
VSS
I/O Port
Communication
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
E3
P00
E4
P43
E5
P07
E6
PN0
E7
PQ0
SCK11
E8
PQ1
SMISO11/ ET1_COL
SSCL11/
RXD11
E9
PQ3
RTS11#/
CTS11#/
SS11#
E10
PQ5
ET1_ETX
D0/
RMII1_TX
D0/
CAT1_ET
XD0
E11
PQ4
ET1_RX_
CLK/
REF50CK
1/
CAT1_RX
_CLK
E12
TMRI0
TXD6/
CATLATC QIO2-C
SMOSI6/ H1
SSDA6/
AUDIO_CL
K
GLCDC
Interrupt
A/D
D/A
IRQ8
AN118
DSMIF
IRQ11-DS AN003
IRQ15
ADTRG0#
ET1_ETX
D2/
CAT1_ET
XD2
ET1_CRS/
RMII1_CR
S_DV/
CAT1_RX
_DV
ET1_TX_E
R
VCC
E13
PE6
D14[A14/ MTIOC6C/ GTIOC3B MOSIB-B
D14]/
TIC1
D6[A6/D6]
SDHI_CD/ LCD_DAT IRQ6
MMC_CD-B A10-B
E14
TRCLK
PG5
D29
ET1_ETX
D2/
CAT1_ET
XD2
E15
TRSYNC
PG4
D28
ET1_ETX
D1/
RMII1_TX
D1/
CAT1_ET
XD1
F1
XCIN
F2
VBATT
F3
TRST#
AN104
PF4
F4
PK4
GTADSM0 SSLB1
ET0_ERX
D2/
CAT0_ER
XD2
F5
PK5
GTADSM1 SSLB2
ET0_ERX
D3/
CAT0_ER
XD3
F6
Memory I/F
Camera I/F
EMLE
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 35 of 180
RX72M Group
Table 1.5
1. Overview
List of Pin and Pin Functions (224-Pin LFBGA) (5/14)
Pin
Number
Timer
Communication
Power
Supply
Clock
224-Pin System
LFBGA Control
I/O Port
F7
PK6
F8
PN1
ET1_ETX
D3/
CAT1_ET
XD3
F9
PQ6
ET1_ETX
D1/
RMII1_TX
D1/
CAT1_ET
XD1
F10
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
GTIOC1A SSLB3
Interrupt
A/D
D/A
DSMIF
VSS
PM1
F12
PA0
F13
TRDATA1 PG3
D27
ET1_ETX
D0/
RMII1_TX
D0/
CAT1_ET
XD0
F14
TRDATA2 PG6
D30
ET1_ETX
D3/
CAT1_ET
XD3
F15
TRDATA3 PG7
D31
ET1_TX_E
R
G1
XCOUT
G2
VSS
G3
VCC
G4
MD/FINED
G5
PJ5
G6
PF5
TOC3
DQM2/
BC0#/A0
MTIOC4A/ GTIOC0B SSLA1-B
MTIOC6D/
TIOCA0/
PO16/
CACREF
POE8#
WAIT#
GTETRGB SMISO10/ ET1_ERX SDHI_CMD
SSCL10/ D1/
-D/QSSL-A
RXD10
RMII1_RX
D1/
CAT1_ER
XD1
CTS2#/
RTS2#/
SS2#/
SSIRXD0
ET0_TX_E
N/
RMII0_TX
D_EN/
CAT0_TX_
EN/
CATLEDR
UN
LCD_DAT
A8-B
EPLSOUT QMI-C/
0/
QIO1-C
CATSYNC
0
SSILRCK0 CATLATC
H0
IRQ4
RES#
G8
PQ2
G9
PN2
G10
GLCDC
CATLINKA
CT0
F11
G7
Memory I/F
Camera I/F
SMOSI11/ ET1_RX_
SSDA11/ DV/
TXD11
CAT1_RX
_DV
ET1_TX_
CLK/
CAT1_TX_
CLK
VCC
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 36 of 180
RX72M Group
Table 1.5
1. Overview
List of Pin and Pin Functions (224-Pin LFBGA) (6/14)
Pin
Number
Timer
Communication
Memory I/F
Camera I/F
Power
Supply
Clock
224-Pin System
LFBGA Control
I/O Port
G11
PM0
G12
PA1
DQM3/A1 MTIOC0B/ GTIOC2A SCK5/
MTCLKC/
SSLA2-B
MTIOC7B/
TIOCB0/
PO17
ET0_WOL
LCD_DAT IRQ11
A7-B
G13
PA2
A2
MTIOC7A/ GTIOC1A RXD5/
PO18
SMISO5/
SSCL5/
SSLA3-B
CATLINKA
CT1
LCD_DAT
A6-B
G14
PA3
A3
MTIOC0D/
MTCLKD/
TIOCD0/
TCLKB/
PO19
RXD5/
SMISO5/
SSCL5
ET0_MDI
O/
CAT0_MDI
O/
PMGI0_M
DIO
LCD_DAT IRQ6-DS
A5-B
G15
PA4
A4
MTIC5U/
MTCLKA/
TIOCA1/
TMRI0/
PO20
TXD5/
SMOSI5/
SSDA5/
SSLA0-B
ET0_MDC/
CAT0_MD
C/
CATIRQ/
PMGI0_M
DC
LCD_DAT IRQ5-DS
A4-B
MTIOC0A/
TMCI3/
PO12/
POE10#
SCK6/
SCK0
ET0_LINK
STA/
CAT0_LIN
KSTA
H1
XTAL
H2
H3
TIC3
P34
UPSEL
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
GTETRGA SCK10
GLCDC
Interrupt
A/D
D/A
DSMIF
ET1_ERX SDHI_CLKD0/
D/QSPCLKRMII1_RX A
D0/
CAT1_ER
XD0
P37
IRQ4
P35
H4
P33
H5
P32
H6
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
DSMDAT0
NMI
EDREQ1
MTIOC0D/
TIOCD0/
TMRI3/
PO11/
POE4#/
POE11#
RXD6/
SMISO6/
SSCL6/
RXD0/
SMISO0/
SSCL0/
CRX0
PCKO
IRQ3-DS
MTIOC0C/
TIOCC0/
TMO3/
PO10/
RTCIC2/
RTCOUT/
POE0#/
POE10#
TXD6/
SMOSI6/
SSDA6/
TXD0/
SMOSI0/
SSDA0/
CTX0/
USB0_VB
USEN
VSYNC
IRQ2-DS
MTIOC3C
CTS6#/
RTS6#/
SS6#/
CTS0#/
RTS0#/
SS0#/
SSITXD0
DSMCLK0
BSCANP
H7
PJ3
H8
PQ7
EDACK1
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
ET0_EXO QMO-C/
QIO0-C
UT/
CATREST
OUT
ET1_TX_E
N/
RMII1_TX
D_EN/
CAT1_TX_
EN
Page 37 of 180
RX72M Group
Table 1.5
1. Overview
List of Pin and Pin Functions (224-Pin LFBGA) (7/14)
Pin
Number
Timer
Power
Supply
Clock
224-Pin System
LFBGA Control
I/O Port
H9
PN3
H10
P73
H11
PL0
H12
VCC
H13
VSS
Communication
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
Memory I/F
Camera I/F
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
GLCDC
CS3#
PO16
ET0_WOL
TIC2
GTETRGA SCK9/
RSPCKC
ET0_ERX
D0/
RMII0_RX
D0/
CAT0_ER
XD0
A6
MTIC5V/
MTCLKB/
TIOCA2/
TMCI3/
PO22/
POE10#
GTETRGB CTS5#/
RTS5#/
SS5#/
MOSIA-B
ET0_EXO
UT/
CATREST
OUT
LCD_DAT
A2-B
H15
PA5
A5
MTIOC6B/ GTIOC0A RSPCKATIOCB1/
B
PO21
ET0_LINK
STA/
CAT0_LIN
KSTA
LCD_DAT
A3-B
P36
J2
TDI
PF2
J3
TMS
DSMIF
LCD_EXT
CLK-A
PA6
EXTAL
A/D
D/A
ET1_RX_
ER/
RMII1_RX
_ER/
CAT1_RX
_ER
H14
J1
Interrupt
RXD1/
SMISO1/
SSCL1
CATI2CCL
K
PF3
J4
P31
MTIOC4D/
TMCI2/
PO9/
RTCIC1
CTS1#/
RTS1#/
SS1#/
SSLB0-A
ET1_MDC/
PMGI1_M
DC
IRQ1-DS
J5
P30
MTIOC4B/
TMRI3/
PO8/
RTCIC0/
POE8#
RXD1/
SMISO1/
SSCL1/
MISOB-A
ET1_MDI
O/
PMGI1_M
DIO
IRQ0-DS
J6
PH2
J7
P15
J8
P53*1
J9
PK3
J10
PL1
J11
PN5
GTETRGC SMOSI7/
SSDA7/
TXD7/
MISOA
CATI2CDA
TA
MTIOC0B/ GTETRGA RXD1/
CATLEDR PIXD0
MTCLKB/
SMISO1/ UN
TIOCB2/
SSCL1/
TCLKB/
SCK3/
TMCI2/
CRX1-DS/
PO13
SSILRCK1
IRQ5
BCLK
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
TOC2
GTETRGD RTS8#/
CTS8#/
SS8#/
SSLB0
ET0_TX_E
R
GTETRGB SMISO9/
SSCL9/
RXD9/
MOSIC
ET0_ERX
D1/
RMII0_RX
D1/
CAT0_ER
XD1
ET1_MDC/ QSSL-C
PMGI1_M
DC
Page 38 of 180
RX72M Group
Table 1.5
1. Overview
List of Pin and Pin Functions (224-Pin LFBGA) (8/14)
Pin
Number
Timer
Power
Supply
Clock
224-Pin System
LFBGA Control
Communication
Memory I/F
Camera I/F
I/O Port
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
J12
PB1
A9
TXD4/
SMOSI4/
SSDA4/
TXD6/
SMOSI6/
SSDA6
J13
P71
A18/CS1#
J14
PB0
A8
MTIC5W/
TIOCA3/
PO24
RXD4/
SMISO4/
SSCL4/
RXD6/
SMISO6/
SSCL6
ET0_ERX
D1/
RMII0_RX
D1/
CAT0_ER
XD1
LCD_DAT IRQ12
A0-B
J15
PA7
A7
TIOCB2/
PO23
MISOA-B
ET0_WOL
LCD_DAT
A1-B
MTIOC0C/
MTIOC4C/
TIOCB3/
TMCI0/
PO25
ET0_ERX
D0/
RMII0_RX
D0/
CAT0_ER
XD0
CLKOUT2 PH7
5M
GTIOC0B
K2
CLKOUT
PH6
GTIOC0A SSLA3
CATLATC
H1
K3
PH4
GTADSM0 SSLA1
CATLEDS
TER
K4
PH5
GTADSM1 SSLA2
CATLATC
H0
TDO
PF0
K6
PH1
K7
P10
ALE
K8
P50
WR0#/
WR#
K9
PK1
K10
K11
K12
K13
Interrupt
TOC0
TXD1/
SMOSI1/
SSDA1
CATI2CDA
TA
GTETRGB SMISO7/
SSCL7/
RXD7/
MOSIA
CATI2CCL
K
DSMIF
DSMCLK3
MTIC5W/
TMRI3
IRQ0
TXD2/
SMOSI2/
SSDA2/
SSLB1-A
CATLEDE
RR
GTETRGB SMISO8/
SSCL8/
RXD8/
MOSIB
ET0_COL
PL3
GTETRGD RTS9#/
CTS9#/
SS9#/
SSLC0
ET0_RX_
CLK/
REF50CK
0/
CAT0_RX
_CLK
PM2
GTETRGC SMOSI10/ ET1_ERX SDHI_D0SSDA10/ D2/
D/QMO-A/
TXD10
CAT1_ER QIO0-A
XD2
TOC1
A/D
D/A
LCD_TCO IRQ4-DS
N3-B
ET0_MDI
O/
CAT0_MDI
O/
PMGI0_M
DIO
K1
K5
GLCDC
VSS
PB5
A13
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
MTIOC2A/
MTIOC1B/
TIOCB4/
TMRI1/
PO29/
POE4#
SCK9/
RTS9#/
SCK11
ET0_ETX
D0/
RMII0_TX
D0/
CAT0_ET
XD0
LCD_CLKB
Page 39 of 180
RX72M Group
Table 1.5
1. Overview
List of Pin and Pin Functions (224-Pin LFBGA) (9/14)
Pin
Number
Timer
Power
Supply
Clock
224-Pin System
LFBGA Control
Communication
Memory I/F
Camera I/F
I/O Port
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
GLCDC
K14
PB3
A11
SCK4/
SCK6
ET0_RX_
ER/
RMII0_RX
_ER/
CAT0_RX
_ER
LCD_TCO
N1-B
K15
P72
A19/CS2#
ET0_MDC/
CAT0_MD
C/
PMGI0_M
DC
LCD_DAT
A23-A
L1
PH3
L2
P27
L3
TCK
L4
GTETRGD RTS7#/
CTS7#/
SS7#/
SSLA0
CS7#
MTIOC2B/
TMCI3/
PO7
CS4#/
EDREQ1
MTIOC4A/
MTCLKA/
TIOCB4/
TMRI1/
PO4
P24
VCC
L6
CLKOUT2 PJ2
5M
L7
VCC
A/D
D/A
DSMIF
DSMDAT3
CATLEDE
RR
ET1_WOL
/CATIRQ
SCK1
SCK3/
USB0_VB
USEN/
SSIBCK1
SDHI_WP/
PIXCLK
TXD8/
SMOSI8/
SSDA8/
SSLC3-B
L8
P52
RD#
L9
P81
EDACK0
L10
PL7
L11
P77
L12
PN4
L14
SCK1/
RSPCKBA
PF1
L5
L13
MTIOC0A/
MTIOC4A/
TIOCD3/
TCLKD/
TMO0/
PO27/
POE11#
Interrupt
RXD2/
SMISO2/
SSCL2/
SSLB3-A
CATLEDS
TER
MTIOC3D/ GTIOC0B SMISO10/ ET0_ETX QIO3-A/
LCD_DAT
PO27
SSCL10/ D0/
SDHI_CD/ A13-A
RXD10
RMII0_TX MMC_D3-A
D0/
CAT0_ET
XD0/
CATI2CCL
K
GTIOC2B
CS7#
LCD_TCO
N2-A
PO23
ET0_MDI
O/
CAT0_MDI
O/
PMGI0_M
DIO
SMOSI11/ ET0_RX_
SSDA11/ ER/
TXD11
RMII0_RX
_ER/
CAT0_RX
_ER
QSPCLK-A/ LCD_DAT
SDHI_CLK- A17-A
A/
MMC_CLKA
ET1_MDI QSPCLK-C
O/
PMGI1_M
DIO
VCC
PB2
A10
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
TIOCC3/
TCLKC/
PO26
CTS4#/
RTS4#/
SS4#/
CTS6#/
RTS6#/
SS6#
ET0_RX_
CLK/
REF50CK
0/
CAT0_RX
_CLK
LCD_TCO
N2-B
Page 40 of 180
RX72M Group
Table 1.5
1. Overview
List of Pin and Pin Functions (224-Pin LFBGA) (10/14)
Pin
Number
Timer
Power
Supply
Clock
224-Pin System
LFBGA Control
Communication
Memory I/F
Camera I/F
I/O Port
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
L15
PB4
A12
TIOCA4/
PO28
CTS9#/
SS9#/
SS11#/
CTS11#/
RTS11#
ET0_TX_E
N/
RMII0_TX
D_EN/
CAT0_TX_
EN
M1
P26
CS6#
MTIOC2A/
TMO1/PO6
TXD1/
SMOSI1/
SSDA1/
CTS3#/
RTS3#/
SS3#/
MOSIB-A
ET1_EXO
UT/
CATLINKA
CT1
M2
P23
EDACK0
MTIOC3D/ GTIOC0A TXD3/
MTCLKD/
SMOSI3/
TIOCD3/
SSDA3/
PO3
CTS0#/
RTS0#/
SS0#/
CTX1/
SSIBCK0
SDHI_D1C/PIXD7
P25
CS5#/
EDACK1
MTIOC4C/
MTCLKB/
TIOCA4/
PO5
RXD3/
SMISO3/
SSCL3/
SSIDATA1
SDHI_CD/
HSYNC
SCK8/
SSLC1-B
M3
CLKOUT
M4
VSS
M5
PJ0
MTIOC6B
M6
P84
MTIOC6D
M7
GLCDC
Interrupt
A/D
D/A
DSMIF
LCD_TCO
N0-B
ADTRG0#
EPLSOUT
0/
CATSYNC
0
LCD_DAT
A0-A
ET1_LINK
STA/
CAT1_LIN
KSTA
LCD_DAT
A2-A
LCD_DAT
A8-A
VSS
M8
P51
WR1#/
BC1#/
WAIT#
M9
P83
EDACK1
M10
PK0
M11
SCK2/
SSLB2-A
MTIOC4C
GTIOC0A SCK10/
SS10#/
CTS10#
ET0_CRS/
RMII0_CR
S_DV/
CAT0_RX
_DV
TIC1
GTETRGA SCK8/
RSPCKB
ET0_MDC/
CAT0_MD
C/
PMGI0_M
DC
PL5
GTADSM1 SSLC2
ET0_ETX
D1/
RMII0_TX
D1/
CAT0_ET
XD1
M12
PL6
GTIOC2A SSLC3
ET0_TX_E
N/
RMII0_TX
D_EN/
CAT0_TX_
EN
M13
PM7
GTIOC3B
ET0_CRS/ SDHI_WP
RMII0_CR
S_DV/
CAT0_RX
_DV
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
DSMCLK1
Page 41 of 180
RX72M Group
Table 1.5
1. Overview
List of Pin and Pin Functions (224-Pin LFBGA) (11/14)
Pin
Number
Timer
Power
Supply
Clock
224-Pin System
LFBGA Control
Communication
Memory I/F
Camera I/F
I/O Port
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
M14
PC0
A16
MTIOC3C/
TCLKC/
PO17
CTS5#/
RTS5#/
SS5#/
SSLA1-A
ET0_ERX
D3/
CAT0_ER
XD3
M15
PB6
A14
MTIOC3D/
TIOCA5/
PO30
RXD9/
SMISO9/
SSCL9/
SMISO11/
SSCL11/
RXD11
ET0_ETX
D1/
RMII0_TX
D1/
CAT0_ET
XD1
N1
P22
EDREQ0
MTIOC3B/ GTIOC1A SCK0/
MTCLKC/
USB0_OV
TIOCC3/
RCURB/
TMO0/PO2
AUDIO_CL
K
N2
PH0
TIC0
N3
P86
MTIOC4D/ GTIOC2B SMISO10/ CATLINKA PIXD1
TIOCA0
SSCL10/ CT0
RXD10
N4
P85
MTIOC6C/
TIOCC0
LCD_DAT
A1-A
N5
P13
MTIOC0B/ GTADSM1 TXD2/
TIOCA5/
SMOSI2/
TMO3/
SSDA2/
PO13
SDA0[FM+
]
LCD_TCO IRQ3
N0-A
N6
PJ1
N7
CLKOUT2 P56
5M
N8
VCC
N9
UB
WR2#/
BC2#
EDACK1
GTETRGA SCK7/
RSPCKA
MTIOC6A
RXD8/
SMISO8/
SSCL8/
SSLC2-B
MTIOC3C/
TIOCA1
SCK7/
RSPCKCB
GLCDC
Interrupt
SDHI_D0C/PIXD6
CATLEDR
UN
EPLSOUT
1/
CATSYNC
1
LCD_DAT
A4-A
N10
P80
EDREQ0
N11
PK2
N12
P76
N13
PM6
GTETRGC SMOSI8/
SSDA8/
TXD8/
MISOB
CS6#
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
PO22
DSMDAT1
LCD_DAT
ET0_TX_E QIO2-A/
SDHI_WP/ A14-A
N/
RMII0_TX MMC_D2-A
D_EN/
CAT0_TX_
EN/
CATLATC
H0
ET0_RX_
DV/
CAT0_RX
_DV
SMISO11/ ET0_RX_
SSCL11/
CLK/
RXD11
REF50CK
0/
CAT0_RX
_CLK
GTIOC3A
ADTRG1#
LCD_TCO
N3-A
A23/CS0# MTIOC3A/ GTIOC3A TXD8/
ET0_COL MMC_D7-A LCD_DAT IRQ14
MTCLKB/
SMOSI8/
A9-A
TMO2/
SSDA8/
PO31/
SMOSI10/
TOC0/
SSDA10/
CACREF
TXD10/
MISOA-A
SCK10/
RTS10#
DSMIF
IRQ14
PC7
MTIOC3B/
PO26
A/D
D/A
QSSL-A/
LCD_DAT
SDHI_CMD A18-A
-A/
MMC_CMD
-A
ET0_TX_ SDHI_CD
CLK/
CAT0_TX
_CLK
Page 42 of 180
RX72M Group
Table 1.5
1. Overview
List of Pin and Pin Functions (224-Pin LFBGA) (12/14)
Pin
Number
Timer
Power
Supply
Clock
224-Pin System
LFBGA Control
Communication
Memory I/F
Camera I/F
I/O Port
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
GLCDC
N14
PC1
A17
MTIOC3A/
TCLKD/
PO18
SCK5/
SSLA2-A
ET0_ERX
D2/
CAT0_ER
XD2
LCD_DAT IRQ12
A22-A
N15
PB7
A15
MTIOC3B/
TIOCB5/
PO31
TXD9/
SMOSI9/
SSDA9/
SMOSI11/
SSDA11/
TXD11
ET0_CRS/
RMII0_CR
S_DV/
CAT0_RX
_DV
P1
PK7
GTIOC1B
P2
P17
MTIOC3A/ GTIOC0B SCK1/
MTIOC3B/
TXD3/
MTIOC4B/
SMOSI3/
TIOCB0/
SSDA3/
TCLKD/
SDA2-DS/
TMO1/
SSITXD0
PO15/
POE8#
P3
P20
MTIOC1A/
TIOCB3/
TMRI0/
PO0
P4
P14
MTIOC3A/ GTETRGD CTS1#/
MTCLKA/
RTS1#/
TIOCB5/
SS1#/
TCLKA/
CTX1/
TMRI2/
USB0_OV
PO15
RCURA
P5
VCC_USB
P6
VSS_USB
P7
P57
P8
P11
P9
A/D
D/A
DSMIF
CATLINKA
CT1
EPLSOUT SDHI_D30/
C/PIXD3
CATSYNC
0
TXD0/
SMOSI0/
SSDA0/
SDA1/
USB0_ID/
SSIRXD0
SCK2
IRQ7
SDHI_CMD
-C/PIXD4
ADTRG1#
IRQ8
LCD_CLK- IRQ4
A
RXD7/
SMISO7/
SSCL7/
SSLC0-B
MTIC5V/
TMCI3
Interrupt
LCD_DAT
A3-A
EPLSOUT
1/
CATSYNC
1
LCD_DAT IRQ1
A7-A
VSS
P10
P82
EDREQ1
P11
PC4
A20/CS3# MTIOC3D/ GTETRGC SCK5/
CTS8#/
MTCLKC/
SS8#/
TMCI1/
SS10#/
PO25/
CTS10#/
POE0#
RTS10#/
SSLA0-A
ET0_TX_
CLK/
CAT0_TX_
CLK/
CATSYNC
0
P12
PL2
GTETRGC SMOSI9/
SSDA9/
TXD9/
MISOC
ET0_RX_
ER/
RMII0_RX
_ER/
CAT0_RX
_ER
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
MTIOC4A/ GTIOC2A SMOSI10/ ET0_ETX MMC_D4-A LCD_DAT
PO28
SSDA10/ D1/
A12-A
TXD10
RMII0_TX
D1/
CAT0_ET
XD1/
CATI2CDA
TA
QMI-A/
LCD_DAT
QIO1-A/
A15-A
SDHI_D1A/
MMC_D1-A
Page 43 of 180
RX72M Group
Table 1.5
1. Overview
List of Pin and Pin Functions (224-Pin LFBGA) (13/14)
Pin
Number
Timer
Communication
Memory I/F
Camera I/F
Power
Supply
Clock
224-Pin System
LFBGA Control
I/O Port
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
P13
PC2
A18
P14
PM4
GTADSM0
ET0_ETX SDHI_D2D2/
D/QIO2-A
CAT0_ET
XD2
P15
PM3
GTETRGD RTS10#/
CTS10#/
SS10#
ET1_ERX SDHI_D1D3/
D/QMI-A/
CAT1_ER QIO1-A
XD3
R1
P21
MTIOC1B/ GTIOC2A RXD0/
MTIOC4A/
SMISO0/
TIOCA3/
SSCL0/
TMCI0/
SCL1/
PO1
USB0_EXI
CEN/
SSILRCK0
R2
P87
MTIOC4C/ GTIOC1B SMOSI10/ EPLSOUT SDHI_D2TIOCA2
SSDA10/ 1/
C/PIXD2
TXD10
CATSYNC
1
R3
P16
MTIOC3C/
MTIOC3D/
TIOCB1/
TCLKC/
TMO2/
PO14/
RTCOUT
R4
P12
WR3#/
BC3#
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
MTIOC4B/ GTIOC2B RXD5/
TCLKA/
SMISO5/
PO21
SSCL5/
SSLA3-A
MTIC5U/
TMCI1
R5
GLCDC
Interrupt
A/D
D/A
DSMIF
ET0_RX_ SDHI_D3- LCD_DAT
DV/
A/
A19-A
CAT0_RX MMC_CD-A
_DV
SDHI_CLKC/PIXD5
IRQ9
TXD1/
SMOSI1/
SSDA1/
RXD3/
SMISO3/
SSCL3/
SCL2-DS/
USB0_VB
USEN/
USB0_VB
US/
USB0_OV
RCURB
IRQ6
GTADSM0 RXD2/
SMISO2/
SSCL2/
SCL0[FM+
]
LCD_TCO IRQ2
N1-A
ADTRG0#
USB0_DM
R6
USB0_DP
R7
P54
D1[A1/D1]/ MTIOC4B/
EDACK0/ TMCI1
ALE
CTS2#/
RTS2#/
SS2#/
MOSIC-B/
CTX1
R8
P55
D0[A0/D0]/ MTIOC4D/
EDREQ0/ TMO3
WAIT#
TXD7/
ET0_EXO
SMOSI7/ UT
SSDA7/
MISOC-B/
CRX1
R9
PC6
D2[A2/D2]/ MTIOC3C/ GTIOC3B RXD8/
A22/CS1# MTCLKA/
SMISO8/
TMCI2/
SSCL8/
PO30/TIC0
SMISO10/
SSCL10/
RXD10/
MOSIA-A
ET0_ETX MMC_D6-A LCD_DAT IRQ13
D3/
A10-A
CAT0_ET
XD3/
CATLATC
H1
R10
PC5
D3[A3/D3]/ MTIOC3B/ GTIOC1A SCK8/
A21/CS2#/ MTCLKD/
RTS8#/
WAIT#
TMRI2/
SCK10/
PO29
RSPCKAA
ET0_ETX
D2/
CAT0_ET
XD2
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
ET0_LINK
STA/
CAT0_LIN
KSTA
LCD_DAT
A6-A
LCD_DAT IRQ10
A5-A
MMC_D5-A LCD_DAT
A11-A
Page 44 of 180
RX72M Group
Table 1.5
1. Overview
List of Pin and Pin Functions (224-Pin LFBGA) (14/14)
Pin
Number
Timer
Communication
Memory I/F
Camera I/F
Power
Supply
Clock
224-Pin System
LFBGA Control
I/O Port
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
R11
PC3
A19
R12
PL4
R13
P75
CS5#
PO20
SCK11/
RTS11#
ET0_ERX
D0/
RMII0_RX
D0/
CAT0_ER
XD0
SDHI_D2- LCD_DAT
A/
A20-A
MMC_RES
#-A
DSMDAT2
R14
P74
A20/CS4# PO19
SS11#/
CTS11#
ET0_ERX
D1/
RMII0_RX
D1/
CAT0_ER
XD1
LCD_DAT
A21-A
DSMCLK2
R15
PM5
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
MTIOC4D/ GTIOC1B TXD5/
TCLKB/
SMOSI5/
PO24
SSDA5
GTADSM0 SSLC1
GTADSM1
GLCDC
Interrupt
A/D
D/A
DSMIF
ET0_TX_E QMO-A/
LCD_DAT
R
QIO0-A/
A16-A
SDHI_D0A/
MMC_D0-A
ET0_ETX
D0/
RMII0_TX
D0/
CAT0_ET
XD0
ET0_ETX SDHI_D3D3/
D/QIO3-A
CAT0_ET
XD3
Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled.
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 45 of 180
RX72M Group
1.6.2
1. Overview
176-Pin LFBGA
Table 1.6
List of Pin and Pin Functions (176-Pin LFBGA) (1/11)
Pin
Number
Timer
Power
Supply
Clock
176-Pin System
LFBGA Control
A1
AVSS0
A2
AVCC0
A3
VREFL0
I/O Port
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
Communication
Memory I/F
Camera I/F
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
GLCDC
Interrupt
A/D
D/A
DSMIF
A4
P42
IRQ10-DS AN002
A5
P46
IRQ14-DS AN006
A6
VCC
A7
VSS
A8
P94
D20/A20
ET1_ERX
D0/
RMII1_RX
D0/
CAT1_ER
XD0
A9
VCC
A10
TRSYNC1 P97
D23/A23
ET1_ERX
D3/
CAT1_ER
XD3
A11
PD6
D6[A6/D6] MTIC5V/
MTIOC8A/
POE4#
A12
P60
CS0#
ET1_TX_E
N/
RMII1_TX
D_EN/
CAT1_TX_
EN
A13
P63
CAS#/
D2[A2/D2]/
CS3#
ET1_ETX
D1/
RMII1_TX
D1/
CAT1_ET
XD1
A14
PE1
A15
SSLC2-A
ET1_RX_
CLK/
REF50CK
1/
CAT1_RX
_CLK
QMO-B/
LCD_DAT IRQ6
QIO0-B/
A18-B
SDHI_D0B/
MMC_D0-B
AN106
D9[A9/D9]/ MTIOC4C/ GTIOC1B TXD12/
D1[A1/D1] MTIOC3B/
SMOSI12/
PO18
SSDA12/
TXDX12/
SIOX12/
SSLB2-B
MMC_D5-B LCD_DAT
A15-B
ANEX1
PE2
D10[A10/ MTIOC4A/ GTIOC0B RXD12/
D10]/
PO23/TIC3
SMISO12/
D2[A2/D2]
SSCL12/
RXDX12/
SSLB3-B
MMC_D6-B LCD_DAT IRQ7-DS
A14-B
AN100
B1
P05
SSILRCK1
IRQ13
DA1
B2
P07
IRQ15
ADTRG0#
B3
P40
IRQ8-DS
AN000
AN001
B4
P41
IRQ9-DS
B5
P47
IRQ15-DS AN007
B6
P91
D17/A17
B7
P92
D18/A18
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
POE4#
SCK7
ET1_COL
AN115
DSMDAT5
RXD7/
SMISO7/
SSCL7
ET1_CRS/
RMII1_CR
S_DV/
CAT1_RX
_DV
AN116
DSMCLK4
Page 46 of 180
RX72M Group
Table 1.6
1. Overview
List of Pin and Pin Functions (176-Pin LFBGA) (2/11)
Pin
Number
Timer
Power
Supply
Clock
176-Pin System
LFBGA Control
I/O Port
B8
PD1
B9
TRDATA5 P96
B10
PD4
B11
TRDATA7 PG1
B12
VSS
Communication
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
Memory I/F
Camera I/F
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
D1[A1/D1] MTIOC4B/ GTIOC1A MOSIC-A/
POE0#
CTX0
D22/A22
GLCDC
Interrupt
A/D
D/A
DSMIF
LCD_DAT IRQ1
A23-B
AN109
QSSL-B/
LCD_DAT IRQ4
SDHI_CMD A20-B
-B/
MMC_CMD
-B
AN112
ET1_ERX
D2/
CAT1_ER
XD2
D4[A4/D4] MTIOC8B/
POE11#
SSLC0-A
ET1_MDI
O/
PMGI1_M
DIO
D25
ET1_RX_
ER/
RMII1_RX
_ER/
CAT1_RX
_ER
ET1_ETX
D0/
RMII1_TX
D0/
CAT1_ET
XD0
B13
P64
WE#/
D3[A3/D3]/
CS4#
B14
PE0
D8[A8/D8]/ MTIOC3D
D0[A0/D0]
GTIOC2B SCK12/
SSLB1-B
MMC_D4-B LCD_DAT
A16-B
ANEX0
B15
PE3
D11[A11/ MTIOC4B/ GTIOC2A CTS12#/
D11]/
PO26/
RTS12#/
D3[A3/D3] TOC3/
SS12#
POE8#
ET0_ERX MMC_D7-B LCD_DAT
D3/
A13-B
CAT0_ER
XD3
AN101
C1
AVSS1
C2
AVCC1
C3
VREFH0
C4
P43
C5
P45
C6
P90
D16/A16
C7
PD0
D0[A0/D0] POE4#
LCD_EXT IRQ0
CLK-B
AN108
C8
PD2
D2[A2/D2] MTIOC4D/ GTIOC0B MISOC-A/ ET1_EXO QIO2-B/
LCD_DAT IRQ2
TIC2
CRX0
UT
SDHI_D2- A22-B
B/
MMC_D2-B
AN110
C9
PD3
D3[A3/D3] MTIOC8D/ GTIOC0A RSPCKC- ET1_WOL QIO3-B/
LCD_DAT IRQ3
TOC2/
A
SDHI_D3- A21-B
POE8#
B/
MMC_D3-B
AN111
C10
TRDATA6 PG0
C11
VCC
C12
P62
IRQ11-DS AN003
IRQ13-DS AN005
TXD7/
SMOSI7/
SSDA7
ET1_RX_
DV/
CAT1_RX
_DV
GTIOC1B
D24
ET1_RX_
CLK/
REF50CK
1/
CAT1_RX
_CLK
RAS#/
D1[A1/D1]/
CS2#
ET1_ERX
D0/
RMII1_RX
D0/
CAT1_ER
XD0
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
AN114
DSMCLK5
Page 47 of 180
RX72M Group
Table 1.6
1. Overview
List of Pin and Pin Functions (176-Pin LFBGA) (3/11)
Pin
Number
Timer
Communication
Memory I/F
Camera I/F
Power
Supply
Clock
176-Pin System
LFBGA Control
I/O Port
C13
PE4
D12[A12/ MTIOC4D/ GTIOC1A SSLB0-B
D12]/
MTIOC1A/
D4[A4/D4] PO28
ET0_ERX
D2/
CAT0_ER
XD2
C15
P70
SDCLK
CATLINKA
CT0
D1
P01
TMCI0
RXD6/
SMISO6/
SSCL6/
SSIBCK0
CATLEDE
RR
IRQ9
AN119
D2
P02
TMCI1
SCK6/
SSIBCK1
CATLEDS
TER
IRQ10
AN120
D3
P03
SSIDATA1
IRQ11
DA0
D4
P00
TXD6/
CATLATC
SMOSI6/ H1
SSDA6/
AUDIO_CL
K
IRQ8
AN118
D5
P44
D6
P93
D19/A19
D7
TRDATA4 P95
D21/A21
D8
VSS
C14
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
GLCDC
Interrupt
LCD_DAT
A12-B
A/D
D/A
DSMIF
AN102
VSS
TMRI0
IRQ12-DS AN004
POE0#
CTS7#/
RTS7#/
SS7#
ET1_LINK
STA/
CAT1_LIN
KSTA
AN117
ET1_ERX
D1/
RMII1_RX
D1/
CAT1_ER
XD1
D9
PD5
D5[A5/D5] MTIC5W/
MTIOC8C/
MTCLKA/
POE10#
SSLC1-A
ET1_MDC/ QSPCLK-B/ LCD_DAT IRQ5
PMGI1_M SDHI_CLK- A19-B
DC
B/
MMC_CLKB
AN113
D10
PD7
D7[A7/D7] MTIC5U/
POE0#
SSLC3-A
ET1_RX_
ER/
RMII1_RX
_ER/
CAT1_RX
_ER
QMI-B/
LCD_DAT IRQ7
QIO1-B/
A17-B
SDHI_D1B/
MMC_D1-B
AN107
D11
P61
SDCS#/
D0[A0/D0]/
CS1#
ET1_ERX
D1/
RMII1_RX
D1/
CAT1_ER
XD1
D12
PE5
D13[A13/ MTIOC4C/ GTIOC0A RSPCKBD13]/
MTIOC2B
B
D5[A5/D5]
ET0_RX_
CLK/
REF50CK
0/
CAT0_RX
_CLK
LCD_DAT IRQ5
A11-B
AN103
PE7
D15[A15/ MTIOC6A/ GTIOC3A MISOB-B
TOC1
D15]/
D7[A7/D7]
SDHI_WP/ LCD_DAT IRQ7
MMC_RES A9-B
#-B
AN105
D15
P65
CKE/CS5#
E1
PJ5
D13
VCC
D14
E2
DSMDAT4
POE8#
CTS2#/
RTS2#/
SS2#/
SSIRXD0
EPLSOUT
0/
CATSYNC
0
EMLE
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 48 of 180
RX72M Group
Table 1.6
1. Overview
List of Pin and Pin Functions (176-Pin LFBGA) (4/11)
Pin
Number
Timer
Power
Supply
Clock
176-Pin System
LFBGA Control
E3
Communication
Memory I/F
Camera I/F
I/O Port
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
PF5
WAIT#
SSILRCK0 CATLATC
H0
E12
PE6
D14[A14/ MTIOC6C/ GTIOC3B MOSIB-B
D14]/
TIC1
D6[A6/D6]
E13
TRDATA0 PG2
D26
ET1_TX_
CLK/
CAT1_TX_
CLK
E14
TRDATA1 PG3
D27
ET1_ETX
D0/
RMII1_TX
D0/
CAT1_ET
XD0
E15
P67
DQM1/
CS7#
MTIOC7C
PJ3
EDACK1
MTIOC3C
P66
DQM0/
CS6#
MTIOC7D
PG4
D28
PA0
DQM2/
BC0#/A0
E4
VBATT
F2
VCL
F3
TRSYNC
F14
F15
A/D
D/A
DSMIF
IRQ4
GTIOC1B CRX2
CTS6#/
RTS6#/
SS6#/
CTS0#/
RTS0#/
SS0#/
SSITXD0
SDHI_CD/ LCD_DAT IRQ6
MMC_CD-B A10-B
EPLSOUT
1/
CATSYNC
1
AN104
IRQ15
ET0_EXO
UT/
CATREST
OUT
BSCANP
F12
F13
Interrupt
VSS
F1
F4
GLCDC
GTIOC2B CTX2
ET1_ETX
D1/
RMII1_TX
D1/
CAT1_ET
XD1
MTIOC4A/ GTIOC0B SSLA1-B
MTIOC6D/
TIOCA0/
PO16/
CACREF
ET0_TX_E
N/
RMII0_TX
D_EN/
CAT0_TX_
EN/
CATLEDR
UN
LCD_DAT
A8-B
VSS
G1
XCIN
G2
XCOUT
G3
MD/FINED
G4
TRST#
PF4
G12
TRCLK
PG5
D29
ET1_ETX
D2/
CAT1_ET
XD2
G13
TRDATA2 PG6
D30
ET1_ETX
D3/
CAT1_ET
XD3
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 49 of 180
RX72M Group
Table 1.6
1. Overview
List of Pin and Pin Functions (176-Pin LFBGA) (5/11)
Pin
Number
Timer
Power
Supply
Clock
176-Pin System
LFBGA Control
I/O Port
G14
PA1
G15
VCC
H1
XTAL
H2
VSS
H3
RES#
H4
UPSEL
Communication
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
Memory I/F
Camera I/F
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
DQM3/A1 MTIOC0B/ GTIOC2A SCK5/
MTCLKC/
SSLA2-B
MTIOC7B/
TIOCB0/
PO17
ET0_WOL
GLCDC
Interrupt
P37
P35
NMI
PA4
A4
MTIC5U/
MTCLKA/
TIOCA1/
TMRI0/
PO20
TXD5/
SMOSI5/
SSDA5/
SSLA0-B
ET0_MDC/
CAT0_MD
C/
CATIRQ/
PMGI0_M
DC
LCD_DAT IRQ5-DS
A4-B
H13
PA3
A3
MTIOC0D/
MTCLKD/
TIOCD0/
TCLKB/
PO19
RXD5/
SMISO5/
SSCL5
ET0_MDI
O/
CAT0_MDI
O/
PMGI0_M
DIO
LCD_DAT IRQ6-DS
A5-B
H14
PA2
A2
MTIOC7A/ GTIOC1A RXD5/
PO18
SMISO5/
SSCL5/
SSLA3-B
CATLINKA
CT1
LCD_DAT
A6-B
H15
TRDATA3 PG7
J1
EXTAL
J2
VCC
J4
D31
J12
ET1_TX_E
R
P36
P34
TMS
MTIOC0A/
TMCI3/
PO12/
POE10#
SCK6/
SCK0
ET0_LINK
STA/
CAT0_LIN
KSTA
IRQ4
DSMDAT0
DSMCLK0
PF3
PA5
A5
MTIOC6B/ GTIOC0A RSPCKATIOCB1/
B
PO21
ET0_LINK
STA/
CAT0_LIN
KSTA
LCD_DAT
A3-B
J14
PA7
A7
TIOCB2/
PO23
MISOA-B
ET0_WOL
LCD_DAT
A1-B
J15
PA6
A6
MTIC5V/
MTCLKB/
TIOCA2/
TMCI3/
PO22/
POE10#
GTETRGB CTS5#/
RTS5#/
SS5#/
MOSIA-B
ET0_EXO
UT/
CATREST
OUT
LCD_DAT
A2-B
K1
P33
EDREQ1
MTIOC0D/
TIOCD0/
TMRI3/
PO11/
POE4#/
POE11#
RXD6/
SMISO6/
SSCL6/
RXD0/
SMISO0/
SSCL0/
CRX0
PCKO
IRQ3-DS
K2
P32
MTIOC0C/
TIOCC0/
TMO3/
PO10/
RTCIC2/
RTCOUT/
POE0#/
POE10#
TXD6/
SMOSI6/
SSDA6/
TXD0/
SMOSI0/
SSDA0/
CTX0/
USB0_VB
USEN
VSYNC
IRQ2-DS
J13
DSMIF
LCD_DAT IRQ11
A7-B
H12
J3
A/D
D/A
VSS
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 50 of 180
RX72M Group
Table 1.6
1. Overview
List of Pin and Pin Functions (176-Pin LFBGA) (6/11)
Pin
Number
Timer
Power
Supply
Clock
176-Pin System
LFBGA Control
I/O Port
K3
TDI
PF2
K4
TCK
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
PF1
Memory I/F
Camera I/F
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
RXD1/
SMISO1/
SSCL1
GLCDC
Interrupt
A/D
D/A
DSMIF
CATI2CCL
K
SCK1
K12
PB2
A10
K13
P71
A18/CS1#
K15
PB0
A8
L1
L2
K14
Communication
TIOCC3/
TCLKC/
PO26
CTS4#/
RTS4#/
SS4#/
CTS6#/
RTS6#/
SS6#
ET0_RX_
CLK/
REF50CK
0/
CAT0_RX
_CLK
LCD_TCO
N2-B
ET0_MDI
O/
CAT0_MDI
O/
PMGI0_M
DIO
DSMCLK3
VCC
MTIC5W/
TIOCA3/
PO24
RXD4/
SMISO4/
SSCL4/
RXD6/
SMISO6/
SSCL6
ET0_ERX
D1/
RMII0_RX
D1/
CAT0_ER
XD1
P31
MTIOC4D/
TMCI2/
PO9/
RTCIC1
CTS1#/
RTS1#/
SS1#/
SSLB0-A
ET1_MDC/
PMGI1_M
DC
IRQ1-DS
P30
MTIOC4B/
TMRI3/
PO8/
RTCIC0/
POE8#
RXD1/
SMISO1/
SSCL1/
MISOB-A
ET1_MDI
O/
PMGI1_M
DIO
IRQ0-DS
TXD1/
SMOSI1/
SSDA1
CATI2CDA
TA
LCD_DAT IRQ12
A0-B
L3
TDO
PF0
L4
CLKOUT
P25
CS5#/
EDACK1
MTIOC4C/
MTCLKB/
TIOCA4/
PO5
RXD3/
SMISO3/
SSCL3/
SSIDATA1
L12
PB6
A14
MTIOC3D/
TIOCA5/
PO30
RXD9/
SMISO9/
SSCL9/
SMISO11/
SSCL11/
RXD11
ET0_ETX
D1/
RMII0_TX
D1/
CAT0_ET
XD1
L13
PB3
A11
MTIOC0A/
MTIOC4A/
TIOCD3/
TCLKD/
TMO0/
PO27/
POE11#
SCK4/
SCK6
ET0_RX_
ER/
RMII0_RX
_ER/
CAT0_RX
_ER
LCD_TCO
N1-B
L14
PB1
A9
MTIOC0C/
MTIOC4C/
TIOCB3/
TMCI0/
PO25
TXD4/
SMOSI4/
SSDA4/
TXD6/
SMOSI6/
SSDA6
ET0_ERX
D0/
RMII0_RX
D0/
CAT0_ER
XD0
LCD_TCO IRQ4-DS
N3-B
L15
P72
A19/CS2#
ET0_MDC/
CAT0_MD
C/
PMGI0_M
DC
LCD_DAT
A23-A
M1
P27
CS7#
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
MTIOC2B/
TMCI3/
PO7
SCK1/
RSPCKBA
SDHI_CD/
HSYNC
ADTRG0#
DSMDAT3
ET1_WOL
/CATIRQ
Page 51 of 180
RX72M Group
Table 1.6
1. Overview
List of Pin and Pin Functions (176-Pin LFBGA) (7/11)
Pin
Number
Timer
Power
Supply
Clock
176-Pin System
LFBGA Control
Communication
Memory I/F
Camera I/F
I/O Port
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
M2
P26
CS6#
MTIOC2A/
TMO1/PO6
TXD1/
SMOSI1/
SSDA1/
CTS3#/
RTS3#/
SS3#/
MOSIB-A
M3
P24
CS4#/
EDREQ1
MTIOC4A/
MTCLKA/
TIOCB4/
TMRI1/
PO4
SCK3/
USB0_VB
USEN/
SSIBCK1
M4
P86
M5
CLKOUT2 PJ2
5M
M6
PJ1
MTIOC6A
M7
P85
MTIOC6C/
TIOCC0
M8
P55
D0[A0/D0]/ MTIOC4D/
EDREQ0/ TMO3
WAIT#
TXD7/
ET0_EXO
SMOSI7/ UT
SSDA7/
MISOC-B/
CRX1
M9
P50
WR0#/
WR#
TXD2/
SMOSI2/
SSDA2/
SSLB1-A
M10
PC5
D3[A3/D3]/ MTIOC3B/ GTIOC1A SCK8/
A21/CS2#/ MTCLKD/
RTS8#/
WAIT#
TMRI2/
SCK10/
PO29
RSPCKAA
M11
P81
EDACK0
LCD_DAT
MTIOC3D/ GTIOC0B SMISO10/ ET0_ETX QIO3-A/
SDHI_CD/ A13-A
PO27
SSCL10/ D0/
RMII0_TX MMC_D3-A
RXD10
D0/
CAT0_ET
XD0/
CATI2CCL
K
M12
P77
CS7#
PO23
SMOSI11/ ET0_RX_
SSDA11/ ER/
TXD11
RMII0_RX
_ER/
CAT0_RX
_ER
M13
PB7
A15
MTIOC3B/
TIOCB5/
PO31
TXD9/
SMOSI9/
SSDA9/
SMOSI11/
SSDA11/
TXD11
ET0_CRS/
RMII0_CR
S_DV/
CAT0_RX
_DV
M14
PB5
A13
MTIOC2A/
MTIOC1B/
TIOCB4/
TMRI1/
PO29/
POE4#
SCK9/
RTS9#/
SCK11
ET0_ETX
D0/
RMII0_TX
D0/
CAT0_ET
XD0
GLCDC
Interrupt
A/D
D/A
DSMIF
ET1_EXO
UT/
CATLINKA
CT1
SDHI_WP/
PIXCLK
MTIOC4D/ GTIOC2B SMISO10/ CATLINKA PIXD1
TIOCA0
SSCL10/ CT0
RXD10
TXD8/
SMOSI8/
SSDA8/
SSLC3-B
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
RXD8/
SMISO8/
SSCL8/
SSLC2-B
LCD_TCO
N2-A
EPLSOUT
1/
CATSYNC
1
LCD_TCO
N3-A
LCD_DAT
A1-A
LCD_DAT IRQ10
A5-A
CATLEDE
RR
ET0_ETX
D2/
CAT0_ET
XD2
MMC_D5-A LCD_DAT
A11-A
QSPCLK-A/ LCD_DAT
SDHI_CLK- A17-A
A/
MMC_CLKA
LCD_CLKB
Page 52 of 180
RX72M Group
Table 1.6
1. Overview
List of Pin and Pin Functions (176-Pin LFBGA) (8/11)
Pin
Number
Timer
Power
Supply
Clock
176-Pin System
LFBGA Control
M15
Communication
Memory I/F
Camera I/F
I/O Port
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
PB4
A12
TIOCA4/
PO28
CTS9#/
SS9#/
SS11#/
CTS11#/
RTS11#
N2
P23
EDACK0
MTIOC3D/ GTIOC0A TXD3/
MTCLKD/
SMOSI3/
TIOCD3/
SSDA3/
PO3
CTS0#/
RTS0#/
SS0#/
CTX1/
SSIBCK0
SDHI_D1C/PIXD7
N3
P22
EDREQ0
MTIOC3B/ GTIOC1A SCK0/
MTCLKC/
USB0_OV
TIOCC3/
RCURB/
TMO0/PO2
AUDIO_CL
K
SDHI_D0C/PIXD6
N4
P15
N5
P12
N6
PJ0
MTIOC6B
N7
P84
MTIOC6D
N8
P54
D1[A1/D1]/ MTIOC4B/
EDACK0/ TMCI1
ALE
CTS2#/
RTS2#/
SS2#/
MOSIC-B/
CTX1
N9
P51
WR1#/
BC1#/
WAIT#
SCK2/
SSLB2-A
PC7
A23/CS0# MTIOC3A/ GTIOC3A TXD8/
ET0_COL MMC_D7-A LCD_DAT IRQ14
MTCLKB/
SMOSI8/
A9-A
TMO2/
SSDA8/
PO31/
SMOSI10/
TOC0/
SSDA10/
CACREF
TXD10/
MISOA-A
N11
P82
EDREQ1
MTIOC4A/ GTIOC2A SMOSI10/ ET0_ETX MMC_D4-A LCD_DAT
SSDA10/ D1/
A12-A
PO28
TXD10
RMII0_TX
D1/
CAT0_ET
XD1/
CATI2CDA
TA
N12
PC3
A19
MTIOC4D/ GTIOC1B TXD5/
TCLKB/
SMOSI5/
PO24
SSDA5
N1
N10
ET0_TX_E
N/
RMII0_TX
D_EN/
CAT0_TX_
EN
GLCDC
Interrupt
A/D
D/A
DSMIF
LCD_TCO
N0-B
VCC
UB
MTIOC0B/ GTETRGA RXD1/
CATLEDR PIXD0
MTCLKB/
SMISO1/ UN
TIOCB2/
SSCL1/
TCLKB/
SCK3/
TMCI2/
CRX1-DS/
PO13
SSILRCK1
WR3#/
BC3#
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
MTIC5U/
TMCI1
GTADSM0 RXD2/
SMISO2/
SSCL2/
SCL0[FM+
]
SCK8/
SSLC1-B
IRQ5
LCD_TCO IRQ2
N1-A
EPLSOUT
0/
CATSYNC
0
LCD_DAT
A0-A
ET1_LINK
STA/
CAT1_LIN
KSTA
LCD_DAT
A2-A
ET0_LINK
STA/
CAT0_LIN
KSTA
LCD_DAT
A6-A
ET0_TX_E QMO-A/
LCD_DAT
R
QIO0-A/
A16-A
SDHI_D0A/
MMC_D0-A
Page 53 of 180
RX72M Group
Table 1.6
1. Overview
List of Pin and Pin Functions (176-Pin LFBGA) (9/11)
Pin
Number
Timer
Power
Supply
Clock
176-Pin System
LFBGA Control
Communication
Memory I/F
Camera I/F
I/O Port
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
N13
PC0
A16
MTIOC3C/
TCLKC/
PO17
CTS5#/
RTS5#/
SS5#/
SSLA1-A
N14
P73
CS3#
PO16
ET0_WOL
EPLSOUT SDHI_D30/
C/PIXD3
CATSYNC
0
N15
VSS
P1
VSS
ET0_ERX
D3/
CAT0_ER
XD3
MTIOC3A/ GTIOC0B SCK1/
MTIOC3B/
TXD3/
MTIOC4B/
SMOSI3/
TIOCB0/
SSDA3/
TCLKD/
SDA2-DS/
TMO1/
SSITXD0
PO15/
POE8#
P3
P87
MTIOC4C/ GTIOC1B SMOSI10/ EPLSOUT SDHI_D2TIOCA2
SSDA10/ 1/
C/PIXD2
TXD10
CATSYNC
1
P4
P14
MTIOC3A/ GTETRGD CTS1#/
MTCLKA/
RTS1#/
TIOCB5/
SS1#/
TCLKA/
CTX1/
TMRI2/
USB0_OV
PO15
RCURA
P6
VSS_USB
IRQ7
P57
RXD7/
SMISO7/
SSCL7/
SSLC0-B
P8
P10
ALE
P9
P52
RD#
P10
P83
EDACK1
P11
PC6
D2[A2/D2]/ MTIOC3C/ GTIOC3B RXD8/
A22/CS1# MTCLKA/
SMISO8/
TMCI2/
SSCL8/
PO30/TIC0
SMISO10/
SSCL10/
RXD10/
MOSIA-A
ET0_ETX MMC_D6-A LCD_DAT IRQ13
D3/
A10-A
CAT0_ET
XD3/
CATLATC
H1
P12
PC4
A20/CS3# MTIOC3D/ GTETRGC SCK5/
MTCLKC/
CTS8#/
TMCI1/
SS8#/
SS10#/
PO25/
CTS10#/
POE0#
RTS10#/
SSLA0-A
ET0_TX_
CLK/
CAT0_TX_
CLK/
CATSYNC
0
P13
PC2
A18
ET0_RX_ SDHI_D3- LCD_DAT
DV/
A/
A19-A
CAT0_RX MMC_CD-A
_DV
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
DSMIF
ADTRG1#
LCD_CLK- IRQ4
A
P7
LCD_DAT
A3-A
MTIC5W/
TMRI3
IRQ0
RXD2/
SMISO2/
SSCL2/
SSLB3-A
MTIOC4C
A/D
D/A
LCD_EXT
CLK-A
P17
VCC_USB
Interrupt
IRQ14
P2
P5
GLCDC
GTIOC0A SCK10/
SS10#/
CTS10#
MTIOC4B/ GTIOC2B RXD5/
TCLKA/
SMISO5/
PO21
SSCL5/
SSLA3-A
CATLEDS
TER
ET0_CRS/
RMII0_CR
S_DV/
CAT0_RX
_DV
LCD_DAT
A8-A
DSMCLK1
QMI-A/
LCD_DAT
QIO1-A/
A15-A
SDHI_D1A/
MMC_D1-A
Page 54 of 180
RX72M Group
Table 1.6
1. Overview
List of Pin and Pin Functions (176-Pin LFBGA) (10/11)
Pin
Number
Timer
Power
Supply
Clock
176-Pin System
LFBGA Control
P14
P15
Communication
Memory I/F
Camera I/F
I/O Port
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
P75
CS5#
SCK11/
RTS11#
PO20
ET0_ERX
D0/
RMII0_RX
D0/
CAT0_ER
XD0
GLCDC
Interrupt
A/D
D/A
DSMIF
SDHI_D2- LCD_DAT
A/
A20-A
MMC_RES
#-A
DSMDAT2
VCC
R1
P21
MTIOC1B/ GTIOC2A RXD0/
MTIOC4A/
SMISO0/
TIOCA3/
SSCL0/
TMCI0/
SCL1/
PO1
USB0_EXI
CEN/
SSILRCK0
SDHI_CLKC/PIXD5
IRQ9
R2
P20
MTIOC1A/
TIOCB3/
TMRI0/
PO0
TXD0/
SMOSI0/
SSDA0/
SDA1/
USB0_ID/
SSIRXD0
SDHI_CMD
-C/PIXD4
IRQ8
R3
P16
MTIOC3C/
MTIOC3D/
TIOCB1/
TCLKC/
TMO2/
PO14/
RTCOUT
TXD1/
SMOSI1/
SSDA1/
RXD3/
SMISO3/
SSCL3/
SCL2-DS/
USB0_VB
USEN/
USB0_VB
US/
USB0_OV
RCURB
R4
P13
WR2#/
BC2#
MTIOC0B/ GTADSM1 TXD2/
TIOCA5/
SMOSI2/
TMO3/
SSDA2/
PO13
SDA0[FM+
]
R5
USB0_DM
R6
USB0_DP
R7
CLKOUT2 P56
5M
R8
P11
R9
P53*1
BCLK
R12
P80
R13
P76
R10
VSS
R11
VCC
EDACK1
IRQ6
ADTRG0#
LCD_TCO IRQ3
N0-A
ADTRG1#
MTIOC3C/
TIOCA1
SCK7/
RSPCKCB
MTIC5V/
TMCI3
SCK2
EPLSOUT
1/
CATSYNC
1
EDREQ0
MTIOC3B/
PO26
SCK10/
RTS10#
ET0_TX_E QIO2-A/
LCD_DAT
N/
SDHI_WP/ A14-A
RMII0_TX MMC_D2-A
D_EN/
CAT0_TX_
EN/
CATLATC
H0
CS6#
PO22
SMISO11/ ET0_RX_
SSCL11/
CLK/
RXD11
REF50CK
0/
CAT0_RX
_CLK
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
LCD_DAT
A4-A
DSMDAT1
LCD_DAT IRQ1
A7-A
QSSL-A/
LCD_DAT
SDHI_CMD A18-A
-A/
MMC_CMD
-A
Page 55 of 180
RX72M Group
Table 1.6
1. Overview
List of Pin and Pin Functions (176-Pin LFBGA) (11/11)
Pin
Number
Power
Supply
Clock
176-Pin System
LFBGA Control
Timer
Communication
Memory I/F
Camera I/F
I/O Port
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
GLCDC
R14
P74
A20/CS4# PO19
SS11#/
CTS11#
ET0_ERX
D1/
RMII0_RX
D1/
CAT0_ER
XD1
LCD_DAT
A21-A
R15
PC1
A17
SCK5/
SSLA2-A
ET0_ERX
D2/
CAT0_ER
XD2
LCD_DAT IRQ12
A22-A
MTIOC3A/
TCLKD/
PO18
Interrupt
A/D
D/A
DSMIF
DSMCLK2
Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled.
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 56 of 180
RX72M Group
1.6.3
1. Overview
176-Pin LFQFP
Table 1.7
List of Pin and Pin Functions (176-Pin LFQFP) (1/11)
Pin
Number
Timer
Power
Supply
Clock
176-Pin System
LFQFP Control
1
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
GLCDC
Interrupt
A/D
D/A
DSMIF
P05
SSILRCK1
IRQ13
DA1
P03
SSIDATA1
IRQ11
DA0
AVCC1
4
5
Memory I/F
Camera I/F
AVSS0
2
3
I/O Port
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
Communication
AVSS1
6
P02
TMCI1
SCK6/
SSIBCK1
CATLEDS
TER
IRQ10
AN120
7
P01
TMCI0
RXD6/
SMISO6/
SSCL6/
SSIBCK0
CATLEDE
RR
IRQ9
AN119
8
P00
TMRI0
TXD6/
CATLATC
SMOSI6/ H1
SSDA6/
AUDIO_CL
K
IRQ8
AN118
9
PF5
SSILRCK0 CATLATC
H0
IRQ4
10
EMLE
11
12
PJ5
POE8#
CTS2#/
RTS2#/
SS2#/
SSIRXD0
EPLSOUT
0/
CATSYNC
0
MTIOC3C
CTS6#/
RTS6#/
SS6#/
CTS0#/
RTS0#/
SS0#/
SSITXD0
ET0_EXO
UT/
CATREST
OUT
VSS
13
PJ3
14
VCL
15
VBATT
16
NC
17
TRST#
18
MD/FINED
19
XCIN
20
XCOUT
21
RES#
22
XTAL
23
VSS
24
EXTAL
25
VCC
26
UPSEL
27
WAIT#
EDACK1
PF4
P37
P36
P35
P34
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
NMI
MTIOC0A/
TMCI3/
PO12/
POE10#
SCK6/
SCK0
ET0_LINK
STA/
CAT0_LIN
KSTA
IRQ4
DSMDAT0
Page 57 of 180
RX72M Group
Table 1.7
1. Overview
List of Pin and Pin Functions (176-Pin LFQFP) (2/11)
Pin
Number
Timer
Power
Supply
Clock
176-Pin System
LFQFP Control
Communication
Memory I/F
Camera I/F
I/O Port
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
28
P33
EDREQ1
MTIOC0D/
TIOCD0/
TMRI3/
PO11/
POE4#/
POE11#
RXD6/
SMISO6/
SSCL6/
RXD0/
SMISO0/
SSCL0/
CRX0
PCKO
IRQ3-DS
29
P32
MTIOC0C/
TIOCC0/
TMO3/
PO10/
RTCIC2/
RTCOUT/
POE0#/
POE10#
TXD6/
SMOSI6/
SSDA6/
TXD0/
SMOSI0/
SSDA0/
CTX0/
USB0_VB
USEN
VSYNC
IRQ2-DS
30
TMS
PF3
31
TDI
PF2
RXD1/
SMISO1/
SSCL1
CATI2CCL
K
GLCDC
Interrupt
32
P31
MTIOC4D/
TMCI2/
PO9/
RTCIC1
CTS1#/
RTS1#/
SS1#/
SSLB0-A
ET1_MDC/
PMGI1_M
DC
IRQ1-DS
33
P30
MTIOC4B/
TMRI3/
PO8/
RTCIC0/
POE8#
RXD1/
SMISO1/
SSCL1/
MISOB-A
ET1_MDI
O/
PMGI1_M
DIO
IRQ0-DS
34
TCK
PF1
SCK1
35
TDO
PF0
TXD1/
SMOSI1/
SSDA1
CATI2CDA
TA
36
P27
CS7#
MTIOC2B/
TMCI3/
PO7
SCK1/
RSPCKBA
ET1_WOL
/CATIRQ
37
P26
CS6#
MTIOC2A/
TMO1/PO6
TXD1/
SMOSI1/
SSDA1/
CTS3#/
RTS3#/
SS3#/
MOSIB-A
ET1_EXO
UT/
CATLINKA
CT1
P25
CS5#/
EDACK1
MTIOC4C/
MTCLKB/
TIOCA4/
PO5
RXD3/
SMISO3/
SSCL3/
SSIDATA1
SDHI_CD/
HSYNC
P24
CS4#/
EDREQ1
MTIOC4A/
MTCLKA/
TIOCB4/
TMRI1/
PO4
SCK3/
USB0_VB
USEN/
SSIBCK1
SDHI_WP/
PIXCLK
P23
EDACK0
MTIOC3D/ GTIOC0A TXD3/
SMOSI3/
MTCLKD/
SSDA3/
TIOCD3/
CTS0#/
PO3
RTS0#/
SS0#/
CTX1/
SSIBCK0
SDHI_D1C/PIXD7
38
CLKOUT
39
VCC
40
41
42
A/D
D/A
DSMIF
DSMCLK0
ADTRG0#
VSS
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 58 of 180
RX72M Group
Table 1.7
1. Overview
List of Pin and Pin Functions (176-Pin LFQFP) (3/11)
Pin
Number
Timer
Communication
Power
Supply
Clock
176-Pin System
LFQFP Control
I/O Port
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
43
P22
EDREQ0
44
Memory I/F
Camera I/F
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
GLCDC
Interrupt
MTIOC3B/ GTIOC1A SCK0/
MTCLKC/
USB0_OV
TIOCC3/
RCURB/
TMO0/PO2
AUDIO_CL
K
SDHI_D0C/PIXD6
P21
MTIOC1B/ GTIOC2A RXD0/
MTIOC4A/
SMISO0/
TIOCA3/
SSCL0/
TMCI0/
SCL1/
PO1
USB0_EXI
CEN/
SSILRCK0
SDHI_CLKC/PIXD5
IRQ9
45
P20
MTIOC1A/
TIOCB3/
TMRI0/
PO0
SDHI_CMD
-C/PIXD4
IRQ8
46
P17
MTIOC3A/ GTIOC0B SCK1/
MTIOC3B/
TXD3/
MTIOC4B/
SMOSI3/
TIOCB0/
SSDA3/
TCLKD/
SDA2-DS/
TMO1/
SSITXD0
PO15/
POE8#
47
P87
MTIOC4C/ GTIOC1B SMOSI10/ EPLSOUT SDHI_D2TIOCA2
SSDA10/ 1/
C/PIXD2
TXD10
CATSYNC
1
48
P16
MTIOC3C/
MTIOC3D/
TIOCB1/
TCLKC/
TMO2/
PO14/
RTCOUT
49
P86
MTIOC4D/ GTIOC2B SMISO10/ CATLINKA PIXD1
TIOCA0
SSCL10/ CT0
RXD10
50
P15
MTIOC0B/ GTETRGA RXD1/
CATLEDR PIXD0
MTCLKB/
SMISO1/ UN
TIOCB2/
SSCL1/
TCLKB/
SCK3/
TMCI2/
CRX1-DS/
PO13
SSILRCK1
51
P14
MTIOC3A/ GTETRGD CTS1#/
RTS1#/
MTCLKA/
SS1#/
TIOCB5/
CTX1/
TCLKA/
USB0_OV
TMRI2/
RCURA
PO15
LCD_CLK- IRQ4
A
52
P13
WR2#/
BC2#
MTIOC0B/ GTADSM1 TXD2/
TIOCA5/
SMOSI2/
TMO3/
SSDA2/
PO13
SDA0[FM+
]
LCD_TCO IRQ3
N0-A
53
P12
WR3#/
BC3#
MTIC5U/
TMCI1
LCD_TCO IRQ2
N1-A
54
TXD0/
SMOSI0/
SSDA0/
SDA1/
USB0_ID/
SSIRXD0
EPLSOUT SDHI_D30/
C/PIXD3
CATSYNC
0
TXD1/
SMOSI1/
SSDA1/
RXD3/
SMISO3/
SSCL3/
SCL2-DS/
USB0_VB
USEN/
USB0_VB
US/
USB0_OV
RCURB
GTADSM0 RXD2/
SMISO2/
SSCL2/
SCL0[FM+
]
A/D
D/A
DSMIF
IRQ7
ADTRG1#
IRQ6
ADTRG0#
IRQ5
ADTRG1#
VCC_USB
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 59 of 180
RX72M Group
Table 1.7
1. Overview
List of Pin and Pin Functions (176-Pin LFQFP) (4/11)
Pin
Number
Timer
Power
Supply
Clock
176-Pin System
LFQFP Control
I/O Port
Communication
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
55
Memory I/F
Camera I/F
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
GLCDC
DSMIF
USB0_DP
57
VSS_USB
58
CLKOUT2 PJ2
5M
59
PJ1
MTIOC6A
RXD8/
SMISO8/
SSCL8/
SSLC2-B
EPLSOUT
1/
CATSYNC
1
LCD_TCO
N3-A
60
PJ0
MTIOC6B
SCK8/
SSLC1-B
EPLSOUT
0/
CATSYNC
0
LCD_DAT
A0-A
61
P85
MTIOC6C/
TIOCC0
62
P84
MTIOC6D
63
P57
64
CLKOUT2 P56
5M
65
P55
66
P54
67
P11
68
P10
69
P53*1
BCLK
70
P52
RD#
RXD2/
SMISO2/
SSCL2/
SSLB3-A
71
P51
WR1#/
BC1#/
WAIT#
SCK2/
SSLB2-A
72
P50
WR0#/
WR#
TXD2/
SMOSI2/
SSDA2/
SSLB1-A
P83
EDACK1
TXD8/
SMOSI8/
SSDA8/
SSLC3-B
LCD_TCO
N2-A
LCD_DAT
A1-A
ET1_LINK
STA/
CAT1_LIN
KSTA
LCD_DAT
A2-A
RXD7/
SMISO7/
SSCL7/
SSLC0-B
LCD_DAT
A3-A
SCK7/
RSPCKCB
LCD_DAT
A4-A
D0[A0/D0]/ MTIOC4D/
EDREQ0/ TMO3
WAIT#
TXD7/
ET0_EXO
SMOSI7/ UT
SSDA7/
MISOC-B/
CRX1
LCD_DAT IRQ10
A5-A
D1[A1/D1]/ MTIOC4B/
EDACK0/ TMCI1
ALE
CTS2#/
RTS2#/
SS2#/
MOSIC-B/
CTX1
ET0_LINK
STA/
CAT0_LIN
KSTA
LCD_DAT
A6-A
SCK2
EPLSOUT
1/
CATSYNC
1
LCD_DAT IRQ1
A7-A
EDACK1
MTIOC3C/
TIOCA1
MTIC5V/
TMCI3
ALE
MTIC5W/
TMRI3
DSMDAT1
IRQ0
CATLEDS
TER
CATLEDE
RR
VSS
74
75
A/D
D/A
USB0_DM
56
73
Interrupt
MTIOC4C
GTIOC0A SCK10/
SS10#/
CTS10#
ET0_CRS/
RMII0_CR
S_DV/
CAT0_RX
_DV
LCD_DAT
A8-A
DSMCLK1
VCC
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 60 of 180
RX72M Group
Table 1.7
1. Overview
List of Pin and Pin Functions (176-Pin LFQFP) (5/11)
Pin
Number
Timer
Communication
Memory I/F
Camera I/F
Power
Supply
Clock
176-Pin System
LFQFP Control
I/O Port
76
PC7
A23/CS0# MTIOC3A/ GTIOC3A TXD8/
ET0_COL MMC_D7-A LCD_DAT IRQ14
MTCLKB/
SMOSI8/
A9-A
TMO2/
SSDA8/
PO31/
SMOSI10/
TOC0/
SSDA10/
CACREF
TXD10/
MISOA-A
77
PC6
D2[A2/D2]/ MTIOC3C/ GTIOC3B RXD8/
A22/CS1# MTCLKA/
SMISO8/
TMCI2/
SSCL8/
PO30/TIC0
SMISO10/
SSCL10/
RXD10/
MOSIA-A
ET0_ETX MMC_D6-A LCD_DAT IRQ13
D3/
A10-A
CAT0_ET
XD3/
CATLATC
H1
78
PC5
D3[A3/D3]/ MTIOC3B/ GTIOC1A SCK8/
A21/CS2#/ MTCLKD/
RTS8#/
WAIT#
TMRI2/
SCK10/
PO29
RSPCKAA
ET0_ETX
D2/
CAT0_ET
XD2
79
P82
EDREQ1
MTIOC4A/ GTIOC2A SMOSI10/ ET0_ETX MMC_D4-A LCD_DAT
PO28
SSDA10/ D1/
A12-A
TXD10
RMII0_TX
D1/
CAT0_ET
XD1/
CATI2CDA
TA
80
P81
EDACK0
MTIOC3D/ GTIOC0B SMISO10/ ET0_ETX QIO3-A/
LCD_DAT
PO27
SSCL10/ D0/
SDHI_CD/ A13-A
RXD10
RMII0_TX MMC_D3-A
D0/
CAT0_ET
XD0/
CATI2CCL
K
81
P80
EDREQ0
MTIOC3B/
PO26
82
PC4
A20/CS3# MTIOC3D/ GTETRGC SCK5/
MTCLKC/
CTS8#/
SS8#/
TMCI1/
SS10#/
PO25/
CTS10#/
POE0#
RTS10#/
SSLA0-A
ET0_TX_
CLK/
CAT0_TX_
CLK/
CATSYNC
0
83
PC3
A19
MTIOC4D/ GTIOC1B TXD5/
TCLKB/
SMOSI5/
PO24
SSDA5
ET0_TX_E QMO-A/
LCD_DAT
R
QIO0-A/
A16-A
SDHI_D0A/
MMC_D0-A
84
P77
CS7#
PO23
SMOSI11/ ET0_RX_
SSDA11/ ER/
TXD11
RMII0_RX
_ER/
CAT0_RX
_ER
QSPCLK-A/ LCD_DAT
SDHI_CLK- A17-A
A/
MMC_CLKA
85
P76
CS6#
PO22
SMISO11/ ET0_RX_
SSCL11/
CLK/
RXD11
REF50CK
0/
CAT0_RX
_CLK
QSSL-A/
LCD_DAT
SDHI_CMD A18-A
-A/
MMC_CMD
-A
UB
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
SCK10/
RTS10#
GLCDC
Interrupt
A/D
D/A
DSMIF
MMC_D5-A LCD_DAT
A11-A
ET0_TX_E QIO2-A/
LCD_DAT
N/
SDHI_WP/ A14-A
RMII0_TX MMC_D2-A
D_EN/
CAT0_TX_
EN/
CATLATC
H0
QMI-A/
LCD_DAT
QIO1-A/
A15-A
SDHI_D1A/
MMC_D1-A
Page 61 of 180
RX72M Group
Table 1.7
1. Overview
List of Pin and Pin Functions (176-Pin LFQFP) (6/11)
Pin
Number
Timer
Communication
Memory I/F
Camera I/F
Power
Supply
Clock
176-Pin System
LFQFP Control
I/O Port
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
86
PC2
A18
MTIOC4B/ GTIOC2B RXD5/
TCLKA/
SMISO5/
PO21
SSCL5/
SSLA3-A
ET0_RX_ SDHI_D3- LCD_DAT
DV/
A/
A19-A
CAT0_RX MMC_CD-A
_DV
87
P75
CS5#
PO20
SCK11/
RTS11#
ET0_ERX
D0/
RMII0_RX
D0/
CAT0_ER
XD0
SDHI_D2- LCD_DAT
A/
A20-A
MMC_RES
#-A
DSMDAT2
88
P74
A20/CS4# PO19
SS11#/
CTS11#
ET0_ERX
D1/
RMII0_RX
D1/
CAT0_ER
XD1
LCD_DAT
A21-A
DSMCLK2
89
PC1
A17
MTIOC3A/
TCLKD/
PO18
SCK5/
SSLA2-A
ET0_ERX
D2/
CAT0_ER
XD2
LCD_DAT IRQ12
A22-A
PC0
A16
MTIOC3C/
TCLKC/
PO17
CTS5#/
RTS5#/
SS5#/
SSLA1-A
ET0_ERX
D3/
CAT0_ER
XD3
IRQ14
93
P73
CS3#
PO16
94
PB7
A15
MTIOC3B/
TIOCB5/
PO31
TXD9/
SMOSI9/
SSDA9/
SMOSI11/
SSDA11/
TXD11
ET0_CRS/
RMII0_CR
S_DV/
CAT0_RX
_DV
95
PB6
A14
MTIOC3D/
TIOCA5/
PO30
RXD9/
SMISO9/
SSCL9/
SMISO11/
SSCL11/
RXD11
ET0_ETX
D1/
RMII0_TX
D1/
CAT0_ET
XD1
96
PB5
A13
MTIOC2A/
MTIOC1B/
TIOCB4/
TMRI1/
PO29/
POE4#
SCK9/
RTS9#/
SCK11
ET0_ETX
D0/
RMII0_TX
D0/
CAT0_ET
XD0
LCD_CLKB
97
PB4
A12
TIOCA4/
PO28
CTS9#/
SS9#/
SS11#/
CTS11#/
RTS11#
ET0_TX_E
N/
RMII0_TX
D_EN/
CAT0_TX_
EN
LCD_TCO
N0-B
98
PB3
A11
MTIOC0A/
MTIOC4A/
TIOCD3/
TCLKD/
TMO0/
PO27/
POE11#
SCK4/
SCK6
ET0_RX_
ER/
RMII0_RX
_ER/
CAT0_RX
_ER
LCD_TCO
N1-B
99
PB2
A10
TIOCC3/
TCLKC/
PO26
CTS4#/
RTS4#/
SS4#/
CTS6#/
RTS6#/
SS6#
ET0_RX_
CLK/
REF50CK
0/
CAT0_RX
_CLK
LCD_TCO
N2-B
90
GLCDC
Interrupt
A/D
D/A
DSMIF
VCC
91
92
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
VSS
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
ET0_WOL
LCD_EXT
CLK-A
Page 62 of 180
RX72M Group
Table 1.7
1. Overview
List of Pin and Pin Functions (176-Pin LFQFP) (7/11)
Pin
Number
Timer
Power
Supply
Clock
176-Pin System
LFQFP Control
Communication
Memory I/F
Camera I/F
I/O Port
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
100
PB1
A9
TXD4/
SMOSI4/
SSDA4/
TXD6/
SMOSI6/
SSDA6
101
P72
102
MTIOC0C/
MTIOC4C/
TIOCB3/
TMCI0/
PO25
GLCDC
Interrupt
ET0_ERX
D0/
RMII0_RX
D0/
CAT0_ER
XD0
LCD_TCO IRQ4-DS
N3-B
A19/CS2#
ET0_MDC/
CAT0_MD
C/
PMGI0_M
DC
LCD_DAT
A23-A
P71
A18/CS1#
ET0_MDI
O/
CAT0_MDI
O/
PMGI0_M
DIO
PB0
A8
MTIC5W/
TIOCA3/
PO24
RXD4/
SMISO4/
SSCL4/
RXD6/
SMISO6/
SSCL6
ET0_ERX
D1/
RMII0_RX
D1/
CAT0_ER
XD1
LCD_DAT IRQ12
A0-B
106
PA7
A7
TIOCB2/
PO23
MISOA-B
ET0_WOL
LCD_DAT
A1-B
107
PA6
A6
MTIC5V/
MTCLKB/
TIOCA2/
TMCI3/
PO22/
POE10#
GTETRGB CTS5#/
RTS5#/
SS5#/
MOSIA-B
ET0_EXO
UT/
CATREST
OUT
LCD_DAT
A2-B
108
PA5
A5
MTIOC6B/ GTIOC0A RSPCKATIOCB1/
B
PO21
ET0_LINK
STA/
CAT0_LIN
KSTA
LCD_DAT
A3-B
109
PA4
A4
MTIC5U/
MTCLKA/
TIOCA1/
TMRI0/
PO20
TXD5/
SMOSI5/
SSDA5/
SSLA0-B
ET0_MDC/
CAT0_MD
C/
CATIRQ/
PMGI0_M
DC
LCD_DAT IRQ5-DS
A4-B
110
PA3
A3
MTIOC0D/
MTCLKD/
TIOCD0/
TCLKB/
PO19
RXD5/
SMISO5/
SSCL5
ET0_MDI
O/
CAT0_MDI
O/
PMGI0_M
DIO
LCD_DAT IRQ6-DS
A5-B
111
TRDATA3 PG7
112
PA2
113
TRDATA2 PG6
114
PA1
103
115
DSMIF
DSMDAT3
DSMCLK3
VCC
104
105
A/D
D/A
VSS
D31
A2
ET1_TX_E
R
MTIOC7A/ GTIOC1A RXD5/
PO18
SMISO5/
SSCL5/
SSLA3-B
CATLINKA
CT1
D30
ET1_ETX
D3/
CAT1_ET
XD3
DQM3/A1 MTIOC0B/ GTIOC2A SCK5/
MTCLKC/
SSLA2-B
MTIOC7B/
TIOCB0/
PO17
ET0_WOL
LCD_DAT
A6-B
LCD_DAT IRQ11
A7-B
VCC
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 63 of 180
RX72M Group
Table 1.7
1. Overview
List of Pin and Pin Functions (176-Pin LFQFP) (8/11)
Pin
Number
Timer
Communication
Memory I/F
Camera I/F
Power
Supply
Clock
176-Pin System
LFQFP Control
I/O Port
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
116
TRCLK
PG5
D29
117
VSS
PA0
DQM2/
BC0#/A0
PG4
D28
120
P67
DQM1/
CS7#
121
TRDATA1 PG3
122
P66
123
TRDATA0 PG2
124
P65
CKE/CS5#
125
PE7
D15[A15/ MTIOC6A/ GTIOC3A MISOB-B
D15]/
TOC1
D7[A7/D7]
SDHI_WP/ LCD_DAT IRQ7
MMC_RES A9-B
#-B
AN105
126
PE6
D14[A14/ MTIOC6C/ GTIOC3B MOSIB-B
D14]/
TIC1
D6[A6/D6]
SDHI_CD/ LCD_DAT IRQ6
MMC_CD-B A10-B
AN104
P70
SDCLK
CATLINKA
CT0
130
PE5
D13[A13/ MTIOC4C/ GTIOC0A RSPCKBD13]/
MTIOC2B
B
D5[A5/D5]
ET0_RX_
CLK/
REF50CK
0/
CAT0_RX
_CLK
LCD_DAT IRQ5
A11-B
AN103
131
PE4
D12[A12/ MTIOC4D/ GTIOC1A SSLB0-B
D12]/
MTIOC1A/
D4[A4/D4] PO28
ET0_ERX
D2/
CAT0_ER
XD2
LCD_DAT
A12-B
AN102
132
PE3
D11[A11/ MTIOC4B/ GTIOC2A CTS12#/
D11]/
PO26/
RTS12#/
D3[A3/D3] TOC3/
SS12#
POE8#
ET0_ERX MMC_D7-B LCD_DAT
A13-B
D3/
CAT0_ER
XD3
AN101
133
PE2
D10[A10/ MTIOC4A/ GTIOC0B RXD12/
D10]/
PO23/TIC3
SMISO12/
D2[A2/D2]
SSCL12/
RXDX12/
SSLB3-B
118
119
127
TRSYNC
Interrupt
A/D
D/A
DSMIF
ET1_ETX
D2/
CAT1_ET
XD2
MTIOC4A/ GTIOC0B SSLA1-B
MTIOC6D/
TIOCA0/
PO16/
CACREF
ET0_TX_E
N/
RMII0_TX
D_EN/
CAT0_TX_
EN/
CATLEDR
UN
LCD_DAT
A8-B
ET1_ETX
D1/
RMII1_TX
D1/
CAT1_ET
XD1
MTIOC7C
GTIOC1B CRX2
D27
DQM0/
CS6#
GLCDC
EPLSOUT
1/
CATSYNC
1
IRQ15
ET1_ETX
D0/
RMII1_TX
D0/
CAT1_ET
XD0
MTIOC7D
GTIOC2B CTX2
D26
ET1_TX_
CLK/
CAT1_TX_
CLK
VCC
128
129
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
VSS
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
MMC_D6-B LCD_DAT IRQ7-DS
A14-B
AN100
Page 64 of 180
RX72M Group
Table 1.7
1. Overview
List of Pin and Pin Functions (176-Pin LFQFP) (9/11)
Pin
Number
Timer
Communication
Memory I/F
Camera I/F
Power
Supply
Clock
176-Pin System
LFQFP Control
I/O Port
134
PE1
D9[A9/D9]/ MTIOC4C/ GTIOC1B TXD12/
D1[A1/D1] MTIOC3B/
SMOSI12/
PO18
SSDA12/
TXDX12/
SIOX12/
SSLB2-B
MMC_D5-B LCD_DAT
A15-B
ANEX1
135
PE0
D8[A8/D8]/ MTIOC3D
D0[A0/D0]
MMC_D4-B LCD_DAT
A16-B
ANEX0
136
P64
WE#/
D3[A3/D3]/
CS4#
ET1_ETX
D0/
RMII1_TX
D0/
CAT1_ET
XD0
137
P63
CAS#/
D2[A2/D2]/
CS3#
ET1_ETX
D1/
RMII1_TX
D1/
CAT1_ET
XD1
138
P62
RAS#/
D1[A1/D1]/
CS2#
ET1_ERX
D0/
RMII1_RX
D0/
CAT1_ER
XD0
139
P61
SDCS#/
D0[A0/D0]/
CS1#
ET1_ERX
D1/
RMII1_RX
D1/
CAT1_ER
XD1
P60
CS0#
ET1_TX_E
N/
RMII1_TX
D_EN/
CAT1_TX_
EN
143
PD7
D7[A7/D7] MTIC5U/
POE0#
QMI-B/
LCD_DAT IRQ7
QIO1-B/
A17-B
SDHI_D1B/
MMC_D1-B
AN107
144
TRDATA7 PG1
145
PD6
QMO-B/
LCD_DAT IRQ6
QIO0-B/
A18-B
SDHI_D0B/
MMC_D0-B
AN106
146
TRDATA6 PG0
140
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
GTIOC2B SCK12/
SSLB1-B
GLCDC
Interrupt
A/D
D/A
DSMIF
VSS
141
142
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
VCC
SSLC3-A
D25
D6[A6/D6] MTIC5V/
MTIOC8A/
POE4#
D24
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
ET1_RX_
ER/
RMII1_RX
_ER/
CAT1_RX
_ER
ET1_RX_
ER/
RMII1_RX
_ER/
CAT1_RX
_ER
SSLC2-A
ET1_RX_
CLK/
REF50CK
1/
CAT1_RX
_CLK
ET1_RX_
CLK/
REF50CK
1/
CAT1_RX
_CLK
Page 65 of 180
RX72M Group
Table 1.7
1. Overview
List of Pin and Pin Functions (176-Pin LFQFP) (10/11)
Pin
Number
Timer
Power
Supply
Clock
176-Pin System
LFQFP Control
I/O Port
147
Communication
Memory I/F
Camera I/F
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
PD5
D5[A5/D5] MTIC5W/
MTIOC8C/
MTCLKA/
POE10#
SSLC1-A
ET1_MDC/ QSPCLK-B/ LCD_DAT IRQ5
PMGI1_M SDHI_CLK- A19-B
DC
B/
MMC_CLKB
AN113
148
PD4
D4[A4/D4] MTIOC8B/
POE11#
SSLC0-A
ET1_MDI
O/
PMGI1_M
DIO
QSSL-B/
LCD_DAT IRQ4
SDHI_CMD A20-B
-B/
MMC_CMD
-B
AN112
149
TRSYNC1 P97
150
PD3
D3[A3/D3] MTIOC8D/ GTIOC0A RSPCKC- ET1_WOL QIO3-B/
LCD_DAT IRQ3
TOC2/
A
SDHI_D3- A21-B
POE8#
B/
MMC_D3-B
AN111
151
VSS
152
TRDATA5 P96
153
VCC
D23/A23
GLCDC
Interrupt
A/D
D/A
DSMIF
ET1_ERX
D3/
CAT1_ER
XD3
D22/A22
ET1_ERX
D2/
CAT1_ER
XD2
154
PD2
155
TRDATA4 P95
156
PD1
D1[A1/D1] MTIOC4B/ GTIOC1A MOSIC-A/
POE0#
CTX0
157
P94
D20/A20
158
PD0
D0[A0/D0] POE4#
159
P93
D19/A19
POE0#
CTS7#/
RTS7#/
SS7#
ET1_LINK
STA/
CAT1_LIN
KSTA
AN117
DSMDAT4
160
P92
D18/A18
POE4#
RXD7/
SMISO7/
SSCL7
ET1_CRS/
RMII1_CR
S_DV/
CAT1_RX
_DV
AN116
DSMCLK4
P91
D17/A17
SCK7
ET1_COL
AN115
DSMDAT5
P90
D16/A16
TXD7/
SMOSI7/
SSDA7
ET1_RX_
DV/
CAT1_RX
_DV
AN114
DSMCLK5
161
162
D21/A21
AN110
ET1_ERX
D1/
RMII1_RX
D1/
CAT1_ER
XD1
LCD_DAT IRQ1
A23-B
AN109
LCD_EXT IRQ0
CLK-B
AN108
ET1_ERX
D0/
RMII1_RX
D0/
CAT1_ER
XD0
GTIOC1B
VSS
163
164
D2[A2/D2] MTIOC4D/ GTIOC0B MISOC-A/ ET1_EXO QIO2-B/
LCD_DAT IRQ2
TIC2
CRX0
UT
SDHI_D2- A22-B
B/
MMC_D2-B
VCC
165
P47
IRQ15-DS AN007
166
P46
IRQ14-DS AN006
167
P45
IRQ13-DS AN005
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 66 of 180
RX72M Group
Table 1.7
1. Overview
List of Pin and Pin Functions (176-Pin LFQFP) (11/11)
Pin
Number
Timer
Communication
Memory I/F
Camera I/F
Power
Supply
Clock
176-Pin System
LFQFP Control
I/O Port
168
P44
IRQ12-DS AN004
169
P43
IRQ11-DS AN003
170
P42
IRQ10-DS AN002
P41
IRQ9-DS
AN001
P40
IRQ8-DS
AN000
P07
IRQ15
ADTRG0#
171
172
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
GLCDC
Interrupt
A/D
D/A
DSMIF
VREFL0
173
174
VREFH0
175
AVCC0
176
(MTU,
TPU, TMR,
Bus
PPG, RTC,
EXDMAC CMTW,
(GPTW,
SDRAMC POE, CAC) POEG)
Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled.
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 67 of 180
RX72M Group
1.6.4
1. Overview
144-Pin LFQFP
Table 1.8
List of Pin and Pin Functions (144-Pin LFQFP) (1/9)
Pin
Number
Timer
Communication
Power
Supply
Clock
144-Pin System
LFQFP Control
(MTU,
TPU, TMR,
PPG, RTC,
CMTW,
(GPTW,
POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
1
GLCDC
Interrupt
A/D
D/A
DSMIF
P05
SSILRCK1
IRQ13
DA1
P03
SSIDATA1
IRQ11
DA0
AVCC1
4
5
Bus
EXDMAC
AVSS0
2
3
I/O Port
Memory I/F
Camera I/F
AVSS1
6
P02
TMCI1
SCK6/
SSIBCK1
CATLEDS
TER
IRQ10
AN120
7
P01
TMCI0
RXD6/
SMISO6/
SSCL6/
SSIBCK0
CATLEDE
RR
IRQ9
AN119
8
P00
TMRI0
TXD6/
CATLATC
SMOSI6/ H1
SSDA6/
AUDIO_CL
K
IRQ8
AN118
MTIOC3C
CTS6#/
RTS6#/
SS6#/
CTS0#/
RTS0#/
SS0#/
SSITXD0
ET0_EXO
UT/
CATREST
OUT
MTIOC0A/
TMCI3/
PO12/
POE10#
SCK6/
SCK0
ET0_LINK
STA/
CAT0_LIN
KSTA
MTIOC0D/
TIOCD0/
TMRI3/
PO11/
POE4#/
POE11#
RXD6/
SMISO6/
SSCL6/
RXD0/
SMISO0/
SSCL0/
CRX0
MTIOC0C/
TIOCC0/
TMO3/
PO10/
RTCIC2/
RTCOUT/
POE0#/
POE10#
TXD6/
SMOSI6/
SSDA6/
TXD0/
SMOSI0/
SSDA0/
CTX0/
USB0_VB
USEN
9
EMLE
10
VSS
11
PJ3
12
VCL
13
VBATT
14
MD/FINED
15
XCIN
16
XCOUT
17
RES#
18
XTAL
19
VSS
20
EXTAL
21
VCC
EDACK1
P37
P36
22
UPSEL
P35
23
TRST#
P34
24
P33
25
P32
NMI
EDREQ1
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
IRQ4
DSMDAT0
PCKO
IRQ3-DS
DSMCLK0
VSYNC
IRQ2-DS
Page 68 of 180
RX72M Group
Table 1.8
1. Overview
List of Pin and Pin Functions (144-Pin LFQFP) (2/9)
Pin
Number
Timer
Communication
Power
Supply
Clock
144-Pin System
LFQFP Control
I/O Port
(MTU,
TPU, TMR,
PPG, RTC,
CMTW,
(GPTW,
POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
26
TMS
P31
MTIOC4D/
TMCI2/
PO9/
RTCIC1
CTS1#/
RTS1#/
SS1#/
SSLB0-A
ET1_MDC/
PMGI1_M
DC
IRQ1-DS
27
TDI
P30
MTIOC4B/
TMRI3/
PO8/
RTCIC0/
POE8#
RXD1/
SMISO1/
SSCL1/
MISOB-A
ET1_MDI
O/
PMGI1_M
DIO
IRQ0-DS
28
TCK
P27
CS7#
MTIOC2B/
TMCI3/
PO7
SCK1/
RSPCKBA
ET1_WOL
/CATIRQ
29
TDO
P26
CS6#
MTIOC2A/
TMO1/PO6
TXD1/
SMOSI1/
SSDA1/
CTS3#/
RTS3#/
SS3#/
MOSIB-A
ET1_EXO
UT/
CATLINKA
CT1
30
CLKOUT
P25
CS5#/
EDACK1
MTIOC4C/
MTCLKB/
TIOCA4/
PO5
RXD3/
SMISO3/
SSCL3/
SSIDATA1
SDHI_CD/
HSYNC
31
P24
CS4#/
EDREQ1
MTIOC4A/
MTCLKA/
TIOCB4/
TMRI1/
PO4
SCK3/
USB0_VB
USEN/
SSIBCK1
SDHI_WP/
PIXCLK
32
P23
EDACK0
MTIOC3D/ GTIOC0A TXD3/
MTCLKD/
SMOSI3/
TIOCD3/
SSDA3/
PO3
CTS0#/
RTS0#/
SS0#/
CTX1/
SSIBCK0
SDHI_D1C/PIXD7
33
P22
EDREQ0
MTIOC3B/ GTIOC1A SCK0/
MTCLKC/
USB0_OV
TIOCC3/
RCURB/
TMO0/PO2
AUDIO_CL
K
SDHI_D0C/PIXD6
34
P21
MTIOC1B/ GTIOC2A RXD0/
MTIOC4A/
SMISO0/
TIOCA3/
SSCL0/
TMCI0/
SCL1/
PO1
USB0_EXI
CEN/
SSILRCK0
SDHI_CLKC/PIXD5
IRQ9
35
P20
MTIOC1A/
TIOCB3/
TMRI0/
PO0
SDHI_CMD
-C/PIXD4
IRQ8
36
P17
MTIOC3A/ GTIOC0B SCK1/
MTIOC3B/
TXD3/
MTIOC4B/
SMOSI3/
TIOCB0/
SSDA3/
TCLKD/
SDA2-DS/
TMO1/
SSITXD0
PO15/
POE8#
37
P87
MTIOC4C/ GTIOC1B SMOSI10/ EPLSOUT SDHI_D2TIOCA2
SSDA10/ 1/
C/PIXD2
TXD10
CATSYNC
1
Bus
EXDMAC
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
TXD0/
SMOSI0/
SSDA0/
SDA1/
USB0_ID/
SSIRXD0
Memory I/F
Camera I/F
EPLSOUT SDHI_D30/
C/PIXD3
CATSYNC
0
GLCDC
Interrupt
A/D
D/A
DSMIF
ADTRG0#
IRQ7
ADTRG1#
Page 69 of 180
RX72M Group
Table 1.8
1. Overview
List of Pin and Pin Functions (144-Pin LFQFP) (3/9)
Pin
Number
Timer
Communication
Power
Supply
Clock
144-Pin System
LFQFP Control
I/O Port
(MTU,
TPU, TMR,
PPG, RTC,
CMTW,
(GPTW,
POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
38
P16
MTIOC3C/
MTIOC3D/
TIOCB1/
TCLKC/
TMO2/
PO14/
RTCOUT
TXD1/
SMOSI1/
SSDA1/
RXD3/
SMISO3/
SSCL3/
SCL2-DS/
USB0_VB
USEN/
USB0_VB
US/
USB0_OV
RCURB
39
P86
MTIOC4D/ GTIOC2B SMISO10/ CATLINKA PIXD1
TIOCA0
SSCL10/ CT0
RXD10
40
P15
MTIOC0B/ GTETRGA RXD1/
CATLEDR PIXD0
MTCLKB/
SMISO1/ UN
TIOCB2/
SSCL1/
TCLKB/
SCK3/
TMCI2/
CRX1-DS/
PO13
SSILRCK1
IRQ5
41
P13
MTIOC0B/ GTADSM1 TXD2/
TIOCA5/
SMOSI2/
TMO3/
SSDA2/
PO13
SDA0[FM+
]
IRQ3
42
P14
MTIOC3A/ GTETRGD CTS1#/
MTCLKA/
RTS1#/
TIOCB5/
SS1#/
TCLKA/
CTX1/
TMRI2/
USB0_OV
PO15
RCURA
IRQ4
43
P12
TMCI1
IRQ2
44
Bus
EXDMAC
GTADSM0 RXD2/
SMISO2/
SSCL2/
SCL0[FM+
]
Memory I/F
Camera I/F
GLCDC
Interrupt
A/D
D/A
IRQ6
ADTRG0#
DSMIF
ADTRG1#
VCC_USB
45
USB0_DM
46
USB0_DP
47
VSS_USB
48
CLKOUT2 PJ2
5M
49
CLKOUT2 P56
5M
EDACK1
50
TRDATA3 P55
D0[A0/D0]/ MTIOC4D/
WAIT#/
TMO3
EDREQ0
TXD7/
SMOSI7/
SSDA7/
CRX1
ET0_EXO
UT
51
TRDATA2 P54
ALE/
MTIOC4B/
D1[A1/D1]/ TMCI1
EDACK0
CTS2#/
RTS2#/
SS2#/
CTX1
ET0_LINK
STA/
CAT0_LIN
KSTA
CATLEDS
TER
TXD8/
SMOSI8/
SSDA8
MTIOC3C/
TIOCA1
SCK7
52
P53*1
BCLK
53
P52
RD#
RXD2/
SMISO2/
SSCL2/
SSLB3-A
54
P51
WR1#/
BC1#/
WAIT#
SCK2/
SSLB2-A
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
DSMDAT1
IRQ10
Page 70 of 180
RX72M Group
Table 1.8
1. Overview
List of Pin and Pin Functions (144-Pin LFQFP) (4/9)
Pin
Number
Timer
Communication
Power
Supply
Clock
144-Pin System
LFQFP Control
I/O Port
(MTU,
TPU, TMR,
PPG, RTC,
CMTW,
(GPTW,
POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
55
P50
WR0#/
WR#
P83
EDACK1
PC7
A23/CS0# MTIOC3A/ GTIOC3A TXD8/
ET0_COL MMC_D7-A
MTCLKB/
SMOSI8/
TMO2/
SSDA8/
PO31/
SMOSI10/
TOC0/
SSDA10/
CACREF
TXD10/
MISOA-A
IRQ14
60
PC6
D2[A2/D2]/ MTIOC3C/ GTIOC3B RXD8/
A22/CS1# MTCLKA/
SMISO8/
TMCI2/
SSCL8/
PO30/TIC0
SMISO10/
SSCL10/
RXD10/
MOSIA-A
ET0_ETX MMC_D6-A
D3/
CAT0_ET
XD3/
CATLATC
H1
IRQ13
61
PC5
D3[A3/D3]/ MTIOC3B/ GTIOC1A SCK8/
A21/CS2#/ MTCLKD/
RTS8#/
WAIT#
TMRI2/
SCK10/
PO29
RSPCKAA
ET0_ETX
D2/
CAT0_ET
XD2
56
VSS
57
TRCLK
58
VCC
59
UB
Bus
EXDMAC
TXD2/
SMOSI2/
SSDA2/
SSLB1-A
MTIOC4C
GTIOC0A SCK10/
SS10#/
CTS10#
Memory I/F
Camera I/F
ET0_CRS/
RMII0_CR
S_DV/
CAT0_RX
_DV
DSMIF
MMC_D5-A
P82
EDREQ1
MTIOC4A/ GTIOC2A SMOSI10/ ET0_ETX MMC_D4-A
PO28
SSDA10/ D1/
TXD10
RMII0_TX
D1/
CAT0_ET
XD1/
CATI2CDA
TA
63
TRDATA1 P81
EDACK0
MTIOC3D/ GTIOC0B SMISO10/ ET0_ETX QIO3-A/
PO27
SSCL10/ D0/
SDHI_CD/
RXD10
RMII0_TX MMC_D3-A
D0/
CAT0_ET
XD0/
CATI2CCL
K
64
TRDATA0 P80
EDREQ0
MTIOC3B/
PO26
65
PC4
A20/CS3# MTIOC3D/ GTETRGC SCK5/
SS8#/
MTCLKC/
CTS8#/
TMCI1/
PO25/
SS10#/
POE0#
CTS10#/
RTS10#/
SSLA0-A
ET0_TX_
CLK/
CAT0_TX_
CLK/
CATSYNC
0
66
PC3
A19
ET0_TX_E QMO-A/
R
QIO0-A/
SDHI_D0A/
MMC_D0-A
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
A/D
D/A
DSMCLK1
TRSYNC
MTIOC4D/ GTIOC1B TXD5/
TCLKB/
SMOSI5/
PO24
SSDA5
Interrupt
CATLEDE
RR
62
SCK10/
RTS10#
GLCDC
ET0_TX_E QIO2-A/
N/
SDHI_WP/
RMII0_TX MMC_D2-A
D_EN/
CAT0_TX_
EN/
CATLATC
H0
QMI-A/
QIO1-A/
SDHI_D1A/
MMC_D1-A
Page 71 of 180
RX72M Group
Table 1.8
1. Overview
List of Pin and Pin Functions (144-Pin LFQFP) (5/9)
Pin
Number
Timer
Communication
Power
Supply
Clock
144-Pin System
LFQFP Control
Bus
EXDMAC
(MTU,
TPU, TMR,
PPG, RTC,
CMTW,
(GPTW,
POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
I/O Port
Memory I/F
Camera I/F
GLCDC
Interrupt
67
TRDATA7 P77
CS7#
PO23
SMOSI11/ ET0_RX_
SSDA11/ ER/
TXD11
RMII0_RX
_ER/
CAT0_RX
_ER
QSPCLK-A/
SDHI_CLKA/
MMC_CLKA
68
TRDATA6 P76
CS6#
PO22
SMISO11/ ET0_RX_
SSCL11/
CLK/
RXD11
REF50CK
0/
CAT0_RX
_CLK
QSSL-A/
SDHI_CMD
-A/
MMC_CMD
-A
69
PC2
A18
MTIOC4B/ GTIOC2B RXD5/
TCLKA/
SMISO5/
PO21
SSCL5/
SSLA3-A
ET0_RX_ SDHI_D3DV/
A/
CAT0_RX MMC_CD-A
_DV
70
TRSYNC1 P75
CS5#
PO20
SCK11/
RTS11#
ET0_ERX
D0/
RMII0_RX
D0/
CAT0_ER
XD0
71
TRDATA5 P74
A20/CS4# PO19
SS11#/
CTS11#
ET0_ERX
D1/
RMII0_RX
D1/
CAT0_ER
XD1
72
PC1
A17
MTIOC3A/
TCLKD/
PO18
SCK5/
SSLA2-A
ET0_ERX
D2/
CAT0_ER
XD2
IRQ12
PC0
A16
MTIOC3C/
TCLKC/
PO17
CTS5#/
RTS5#/
SS5#/
SSLA1-A
ET0_ERX
D3/
CAT0_ER
XD3
IRQ14
73
SDHI_D2A/
MMC_RES
#-A
A/D
D/A
DSMIF
DSMDAT2
DSMCLK2
VCC
74
75
VSS
76
TRDATA4 P73
CS3#
PO16
77
PB7
A15
MTIOC3B/
TIOCB5/
PO31
TXD9/
SMOSI9/
SSDA9/
SMOSI11/
SSDA11/
TXD11
ET0_CRS/
RMII0_CR
S_DV/
CAT0_RX
_DV
78
PB6
A14
MTIOC3D/
TIOCA5/
PO30
RXD9/
SMISO9/
SSCL9/
SMISO11/
SSCL11/
RXD11
ET0_ETX
D1/
RMII0_TX
D1/
CAT0_ET
XD1
79
PB5
A13
MTIOC2A/
MTIOC1B/
TIOCB4/
TMRI1/
PO29/
POE4#
SCK9/
RTS9#/
SCK11
ET0_ETX
D0/
RMII0_TX
D0/
CAT0_ET
XD0
LCD_CLKB
80
PB4
A12
TIOCA4/
PO28
SS9#/
CTS9#/
SS11#/
CTS11#/
RTS11#
ET0_TX_E
N/
RMII0_TX
D_EN/
CAT0_TX_
EN
LCD_TCO
N0-B
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
ET0_WOL
Page 72 of 180
RX72M Group
Table 1.8
1. Overview
List of Pin and Pin Functions (144-Pin LFQFP) (6/9)
Pin
Number
Timer
Communication
Power
Supply
Clock
144-Pin System
LFQFP Control
I/O Port
Bus
EXDMAC
(MTU,
TPU, TMR,
PPG, RTC,
CMTW,
(GPTW,
POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
GLCDC
81
PB3
A11
MTIOC0A/
MTIOC4A/
TIOCD3/
TCLKD/
TMO0/
PO27/
POE11#
SCK4/
SCK6
ET0_RX_
ER/
RMII0_RX
_ER/
CAT0_RX
_ER
LCD_TCO
N1-B
82
PB2
A10
TIOCC3/
TCLKC/
PO26
CTS4#/
RTS4#/
SS4#/
CTS6#/
RTS6#/
SS6#
ET0_RX_
CLK/
REF50CK
0/
CAT0_RX
_CLK
LCD_TCO
N2-B
83
PB1
A9
MTIOC0C/
MTIOC4C/
TIOCB3/
TMCI0/
PO25
TXD4/
SMOSI4/
SSDA4/
TXD6/
SMOSI6/
SSDA6
ET0_ERX
D0/
RMII0_RX
D0/
CAT0_ER
XD0
LCD_TCO IRQ4-DS
N3-B
84
PB0
A8
MTIC5W/
TIOCA3/
PO24
RXD4/
SMISO4/
SSCL4/
RXD6/
SMISO6/
SSCL6
ET0_ERX
D1/
RMII0_RX
D1/
CAT0_ER
XD1
LCD_DAT IRQ12
A0-B
85
PA7
A7
TIOCB2/
PO23
MISOA-B
ET0_WOL
LCD_DAT
A1-B
86
PA6
A6
MTIC5V/
MTCLKB/
TIOCA2/
TMCI3/
PO22/
POE10#
GTETRGB CTS5#/
RTS5#/
SS5#/
MOSIA-B
ET0_EXO
UT/
CATREST
OUT
LCD_DAT
A2-B
87
PA5
A5
MTIOC6B/ GTIOC0A RSPCKATIOCB1/
B
PO21
ET0_LINK
STA/
CAT0_LIN
KSTA
LCD_DAT
A3-B
PA4
A4
MTIC5U/
MTCLKA/
TIOCA1/
TMRI0/
PO20
TXD5/
SMOSI5/
SSDA5/
SSLA0-B
ET0_MDC/
CAT0_MD
C/
CATIRQ/
PMGI0_M
DC
LCD_DAT IRQ5-DS
A4-B
91
PA3
A3
MTIOC0D/
MTCLKD/
TIOCD0/
TCLKB/
PO19
RXD5/
SMISO5/
SSCL5
ET0_MDI
O/
CAT0_MDI
O/
PMGI0_M
DIO
LCD_DAT IRQ6-DS
A5-B
92
PG7
93
PA2
94
PG6
95
PA1
88
Interrupt
A/D
D/A
DSMIF
VCC
89
90
Memory I/F
Camera I/F
VSS
ET1_TX_E
R
A2
MTIOC7A/ GTIOC1A RXD5/
PO18
SMISO5/
SSCL5/
SSLA3-B
CATLINKA
CT1
LCD_DAT
A6-B
ET1_ETX
D3/
CAT1_ET
XD3
A1
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
MTIOC0B/ GTIOC2A SCK5/
MTCLKC/
SSLA2-B
MTIOC7B/
TIOCB0/
PO17
ET0_WOL
LCD_DAT IRQ11
A7-B
Page 73 of 180
RX72M Group
Table 1.8
1. Overview
List of Pin and Pin Functions (144-Pin LFQFP) (7/9)
Pin
Number
Timer
Communication
Power
Supply
Clock
144-Pin System
LFQFP Control
I/O Port
(MTU,
TPU, TMR,
PPG, RTC,
CMTW,
(GPTW,
POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
96
PG5
97
PA0
BC0#/A0
MTIOC4A/ GTIOC0B SSLA1-B
MTIOC6D/
TIOCA0/
PO16/
CACREF
ET0_TX_E
N/
RMII0_TX
D_EN/
CAT0_TX_
EN/
CATLEDR
UN
98
P67
CS7#
MTIOC7C
GTIOC1B CRX2
EPLSOUT
1/
CATSYNC
1
99
P66
CS6#
MTIOC7D
GTIOC2B CTX2
100
PG2
101
P65
CS5#
102
PE7
D15[A15/ MTIOC6A/ GTIOC3A MISOB-B
D15]/
TOC1
D7[A7/D7]
SDHI_WP/ LCD_DAT IRQ7
MMC_RES A9-B
#-B
AN105
103
PE6
D14[A14/ MTIOC6C/ GTIOC3B MOSIB-B
D14]/
TIC1
D6[A6/D6]
SDHI_CD/ LCD_DAT IRQ6
MMC_CD-B A10-B
AN104
106
PE5
D13[A13/ MTIOC4C/ GTIOC0A RSPCKBD13]/
MTIOC2B
B
D5[A5/D5]
ET0_RX_
CLK/
REF50CK
0/
CAT0_RX
_CLK
LCD_DAT IRQ5
A11-B
AN103
107
PE4
D12[A12/ MTIOC4D/ GTIOC1A SSLB0-B
D12]/
MTIOC1A/
D4[A4/D4] PO28
ET0_ERX
D2/
CAT0_ER
XD2
LCD_DAT
A12-B
AN102
108
PE3
D11[A11/ MTIOC4B/ GTIOC2A CTS12#/
D11]/
PO26/
RTS12#/
D3[A3/D3] TOC3/
SS12#
POE8#
ET0_ERX MMC_D7-B LCD_DAT
D3/
A13-B
CAT0_ER
XD3
AN101
109
PE2
D10[A10/ MTIOC4A/ GTIOC0B RXD12/
D10]/
PO23/TIC3
SMISO12/
D2[A2/D2]
SSCL12/
RXDX12/
SSLB3-B
MMC_D6-B LCD_DAT IRQ7-DS
A14-B
AN100
110
PE1
D9[A9/D9]/ MTIOC4C/ GTIOC1B TXD12/
SMOSI12/
D1[A1/D1] MTIOC3B/
SSDA12/
PO18
TXDX12/
SIOX12/
SSLB2-B
MMC_D5-B LCD_DAT
A15-B
ANEX1
111
PE0
D8[A8/D8]/ MTIOC3D
D0[A0/D0]
MMC_D4-B LCD_DAT
A16-B
ANEX0
112
P64
D3[A3/D3]/
CS4#
104
VCC
105
VSS
Bus
EXDMAC
Memory I/F
Camera I/F
GLCDC
Interrupt
A/D
D/A
DSMIF
ET1_ETX
D2/
CAT1_ET
XD2
LCD_DAT
A8-B
IRQ15
ET1_TX_
CLK/
CAT1_TX_
CLK
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
GTIOC2B SCK12/
SSLB1-B
ET1_ETX
D0/
RMII1_TX
D0/
CAT1_ET
XD0
Page 74 of 180
RX72M Group
Table 1.8
1. Overview
List of Pin and Pin Functions (144-Pin LFQFP) (8/9)
Pin
Number
Timer
Communication
Power
Supply
Clock
144-Pin System
LFQFP Control
I/O Port
(MTU,
TPU, TMR,
PPG, RTC,
CMTW,
(GPTW,
POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
113
P63
D2[A2/D2]/
CS3#
ET1_ETX
D1/
RMII1_TX
D1/
CAT1_ET
XD1
114
P62
D1[A1/D1]/
CS2#
ET1_ERX
D0/
RMII1_RX
D0/
CAT1_ER
XD0
115
P61
D0[A0/D0]/
CS1#
ET1_ERX
D1/
RMII1_RX
D1/
CAT1_ER
XD1
P60
CS0#
ET1_TX_E
N/
RMII1_TX
D_EN/
CAT1_TX_
EN
119
PD7
D7[A7/D7] MTIC5U/
POE0#
120
PG1
121
PD6
122
PG0
123
PD5
D5[A5/D5] MTIC5W/
MTCLKA/
MTIOC8C/
POE10#
124
PD4
D4[A4/D4] MTIOC8B/
POE11#
125
126
116
GLCDC
Interrupt
A/D
D/A
DSMIF
VSS
117
118
Bus
EXDMAC
Memory I/F
Camera I/F
VCC
SSLC3-A
ET1_RX_
ER/
RMII1_RX
_ER/
CAT1_RX
_ER
QMI-B/
LCD_DAT IRQ7
QIO1-B/
A17-B
SDHI_D1B/
MMC_D1-B
AN107
QMO-B/
LCD_DAT IRQ6
QIO0-B/
A18-B
SDHI_D0B/
MMC_D0-B
AN106
SSLC1-A
ET1_MDC/ QSPCLK-B/ LCD_DAT IRQ5
PMGI1_M SDHI_CLK- A19-B
DC
B/
MMC_CLKB
AN113
SSLC0-A
ET1_MDI
O/
PMGI1_M
DIO
QSSL-B/
LCD_DAT IRQ4
SDHI_CMD A20-B
-B/
MMC_CMD
-B
AN112
P97
A23
PD3
D3[A3/D3] MTIOC8D/ GTIOC0A RSPCKC- ET1_WOL QIO3-B/
LCD_DAT IRQ3
TOC2/
A
SDHI_D3- A21-B
POE8#
B/
MMC_D3-B
AN111
ET1_RX_
ER/
RMII1_RX
_ER/
CAT1_RX
_ER
D6[A6/D6] MTIC5V/
MTIOC8A/
POE4#
SSLC2-A
ET1_RX_
CLK/
REF50CK
1/
CAT1_RX
_CLK
ET1_RX_
CLK/
REF50CK
1/
CAT1_RX
_CLK
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
ET1_ERX
D3/
CAT1_ER
XD3
Page 75 of 180
RX72M Group
Table 1.8
1. Overview
List of Pin and Pin Functions (144-Pin LFQFP) (9/9)
Pin
Number
Timer
Communication
Power
Supply
Clock
144-Pin System
LFQFP Control
I/O Port
Bus
EXDMAC
(MTU,
TPU, TMR,
PPG, RTC,
CMTW,
(GPTW,
POE, CAC) POEG)
(SCI,
RSPI,
(QSPI,
RIIC, CAN, (ETHERC, SDHI,
USB,
ESC,
MMCIF,
SSIE)
PMGI)
PDC)
127
P96
A22
128
PD2
D2[A2/D2] MTIOC4D/ GTIOC0B MISOC-A/ ET1_EXO QIO2-B/
LCD_DAT IRQ2
TIC2
CRX0
UT
SDHI_D2- A22-B
B/
MMC_D2-B
AN110
129
PD1
D1[A1/D1] MTIOC4B/ GTIOC1A MOSIC-A/
POE0#
CTX0
LCD_DAT IRQ1
A23-B
AN109
130
PD0
D0[A0/D0] POE4#
LCD_EXT IRQ0
CLK-B
AN108
131
P93
A19
POE0#
CTS7#/
RTS7#/
SS7#
ET1_LINK
STA/
CAT1_LIN
KSTA
AN117
132
P92
A18
POE4#
RXD7/
SMISO7/
SSCL7
ET1_CRS/
RMII1_CR
S_DV/
CAT1_RX
_DV
AN116
P91
A17
SCK7
ET1_COL
AN115
P90
A16
TXD7/
SMOSI7/
SSDA7
ET1_RX_
DV/
CAT1_RX
_DV
AN114
133
134
GLCDC
Interrupt
A/D
D/A
DSMIF
ET1_ERX
D2/
CAT1_ER
XD2
GTIOC1B
VSS
135
136
Memory I/F
Camera I/F
VCC
137
P44
IRQ12-DS AN004
138
P43
IRQ11-DS AN003
139
P42
IRQ10-DS AN002
140
P41
IRQ9-DS
AN001
P40
IRQ8-DS
AN000
141
VREFL0
142
143
VREFH0
144
AVCC0
Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled.
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 76 of 180
RX72M Group
1.6.5
1. Overview
100-Pin LFQFP
Table 1.9
List of Pin and Pin Functions (100-Pin LFQFP) (1/4)
Pin
Number Power
Supply
Clock
100-Pin System
LFQFP Control
1
AVSS0
2
AVCC1
3
AVSS1
4
5
EMLE
6
VCL
7
VBATT
8
MD/FINED
9
XCIN
10
XCOUT
11
RES#
12
XTAL
13
VSS
14
EXTAL
15
VCC
Timer
Communication
I/O Port
(MTU, TPU, TMR,
PPG, RTC, CMTW,
POE, CAC)
(GPTW, POEG)
(SCI, RSPI, RIIC,
CAN, USB, SSIE)
(ETHERC, ESC,
PMGI)
Interrupt
A/D
D/A
P00
TMRI0
TXD6/SMOSI6/
SSDA6/
AUDIO_CLK
CATLATCH1
IRQ8
AN118
ET0_LINKSTA/
CAT0_LINKSTA
P37
P36
16
UPSEL
P35
17
TRST#
P34
MTIOC0A/TMCI3/
PO12/POE10#
SCK6/SCK0
NMI
18
P33
MTIOC0D/TIOCD0/
TMRI3/PO11/
POE4#/POE11#
RXD6/SMISO6/
SSCL6/RXD0/
SMISO0/SSCL0/
CRX0
IRQ3-DS
19
P32
MTIOC0C/TIOCC0/
TMO3/PO10/
RTCIC2/RTCOUT/
POE0#/POE10#
TXD6/SMOSI6/
SSDA6/TXD0/
SMOSI0/SSDA0/
CTX0/
USB0_VBUSEN
IRQ2-DS
IRQ4
20
TMS
P31
MTIOC4D/TMCI2/
PO9/RTCIC1
CTS1#/RTS1#/
SS1#/SSLB0-A
ET1_MDC/
PMGI1_MDC
IRQ1-DS
21
TDI
P30
MTIOC4B/TMRI3/
PO8/RTCIC0/
POE8#
RXD1/SMISO1/
SSCL1/MISOB-A
ET1_MDIO/
PMGI1_MDIO
IRQ0-DS
22
TCK
P27
MTIOC2B/TMCI3/
PO7
SCK1/RSPCKB-A
ET1_WOL/CATIRQ
23
TDO
P26
MTIOC2A/TMO1/
PO6
TXD1/SMOSI1/
SSDA1/CTS3#/
RTS3#/SS3#/
MOSIB-A
ET1_EXOUT/
CATLINKACT1
24
CLKOUT
P25
MTIOC4C/
MTCLKB/TIOCA4/
PO5
RXD3/SMISO3/
SSCL3/SSIDATA1
25
P24
MTIOC4A/
MTCLKA/TIOCB4/
TMRI1/PO4
SCK3/
USB0_VBUSEN/
SSIBCK1
26
P23
MTIOC3D/
MTCLKD/TIOCD3/
PO3
GTIOC0A
TXD3/SMOSI3/
SSDA3/CTS0#/
RTS0#/SS0#/
CTX1/SSIBCK0
27
P21
MTIOC1B/
GTIOC2A
MTIOC4A/TIOCA3/
TMCI0/PO1
RXD0/SMISO0/
SSCL0/SCL1/
USB0_EXICEN/
SSILRCK0
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
ADTRG0#
IRQ9
Page 77 of 180
RX72M Group
Table 1.9
1. Overview
List of Pin and Pin Functions (100-Pin LFQFP) (2/4)
Pin
Number Power
Supply
Clock
100-Pin System
LFQFP Control
I/O Port
28
P20
MTIOC1A/TIOCB3/
TMRI0/PO0
TXD0/SMOSI0/
SSDA0/SDA1/
USB0_ID/SSIRXD0
IRQ8
29
P17
MTIOC3A/
GTIOC0B
MTIOC3B/
MTIOC4B/TIOCB0/
TCLKD/TMO1/
PO15/POE8#
SCK1/TXD3/
EPLSOUT0/
SMOSI3/SSDA3/
CATSYNC0
SDA2-DS/SSITXD0
IRQ7
ADTRG1#
30
P87
MTIOC4C/TIOCA2 GTIOC1B
SMOSI10/SSDA10/ EPLSOUT1/
TXD10
CATSYNC1
31
P16
MTIOC3C/
MTIOC3D/TIOCB1/
TCLKC/TMO2/
PO14/RTCOUT
TXD1/SMOSI1/
SSDA1/RXD3/
SMISO3/SSCL3/
SCL2-DS/
USB0_VBUSEN/
USB0_VBUS/
USB0_OVRCURB
IRQ6
ADTRG0#
32
P86
MTIOC4D/TIOCA0 GTIOC2B
SMISO10/SSCL10/ CATLINKACT0
RXD10
33
P15
MTIOC0B/
MTCLKB/TIOCB2/
TCLKB/TMCI2/
PO13
GTETRGA
RXD1/SMISO1/
SSCL1/SCK3/
CRX1-DS/
SSILRCK1
34
P14
MTIOC3A/
MTCLKA/TIOCB5/
TCLKA/TMRI2/
PO15
GTETRGD
CTS1#/RTS1#/
SS1#/CTX1/
USB0_OVRCURA
35
Timer
Communication
(MTU, TPU, TMR,
PPG, RTC, CMTW,
POE, CAC)
(GPTW, POEG)
(SCI, RSPI, RIIC,
CAN, USB, SSIE)
(ETHERC, ESC,
PMGI)
CATLEDRUN
Interrupt
A/D
D/A
IRQ5
IRQ4
VCC_USB
36
USB0_DM
37
USB0_DP
38
VSS_USB
39
CLKOUT25M P56
40
P51
SCK2/SSLB2-A
41
P52
RXD2/SMISO2/
SSCL2/SSLB3-A
CATLEDSTER
42
P50
TXD2/SMOSI2/
SSDA2/SSLB1-A
CATLEDERR
43
VSS
44
VCC
45
UB
MTIOC3C/TIOCA1
SCK7
PC7
MTIOC3A/
MTCLKB/TMO2/
PO31/CACREF
GTIOC3A
TXD8/SMOSI8/
SSDA8/SMOSI10/
SSDA10/TXD10
ET0_COL
IRQ14
46
PC6
MTIOC3C/
MTCLKA/TMCI2/
PO30
GTIOC3B
RXD8/SMISO8/
SSCL8/SMISO10/
SSCL10/RXD10
ET0_ETXD3/
CAT0_ETXD3/
CATLATCH1
IRQ13
47
PC5
MTIOC3B/
MTCLKD/TMRI2/
PO29
GTIOC1A
SCK8/RTS8#/
SCK10
ET0_ETXD2/
CAT0_ETXD2
48
P82
MTIOC4A/PO28
GTIOC2A
SMOSI10/SSDA10/ ET0_ETXD1/
TXD10
RMII0_TXD1/
CAT0_ETXD1/
CATI2CDATA
49
P81
MTIOC3D/PO27
GTIOC0B
SMISO10/SSCL10/ ET0_ETXD0/
RXD10
RMII0_TXD0/
CAT0_ETXD0/
CATI2CCLK
50
P80
MTIOC3B/PO26
51
PC4
MTIOC3D/
MTCLKC/TMCI1/
PO25/POE0#
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
GTETRGC
SCK10/RTS10#
ET0_TX_EN/
RMII0_TXD_EN/
CAT0_TX_EN/
CATLATCH0
SCK5/SS8#/
CTS8#/SS10#/
CTS10#/RTS10#
ET0_TX_CLK/
CAT0_TX_CLK/
CATSYNC0
Page 78 of 180
RX72M Group
Table 1.9
1. Overview
List of Pin and Pin Functions (100-Pin LFQFP) (3/4)
Pin
Number Power
Supply
Clock
100-Pin System
LFQFP Control
I/O Port
52
Timer
Communication
(MTU, TPU, TMR,
PPG, RTC, CMTW,
POE, CAC)
(GPTW, POEG)
(SCI, RSPI, RIIC,
CAN, USB, SSIE)
(ETHERC, ESC,
PMGI)
PC2
MTIOC4B/TCLKA/
PO21
RXD5/SMISO5/
SSCL5
ET0_RX_DV/
CAT0_RX_DV
53
PB7
MTIOC3B/TIOCB5/
PO31
TXD9/SMOSI9/
SSDA9/SMOSI11/
SSDA11/TXD11
ET0_CRS/
RMII0_CRS_DV/
CAT0_RX_DV
54
PB6
MTIOC3D/TIOCA5/
PO30
RXD9/SMISO9/
SSCL9/SMISO11/
SSCL11/RXD11
ET0_ETXD1/
RMII0_TXD1/
CAT0_ETXD1
55
PB5
MTIOC2A/
MTIOC1B/TIOCB4/
TMRI1/PO29/
POE4#
SCK9/RTS9#/
SCK11
ET0_ETXD0/
RMII0_TXD0/
CAT0_ETXD0
56
PB4
TIOCA4/PO28
SS9#/CTS9#/
SS11#/CTS11#/
RTS11#
ET0_TX_EN/
RMII0_TXD_EN/
CAT0_TX_EN
57
PB3
MTIOC0A/
MTIOC4A/TIOCD3/
TCLKD/TMO0/
PO27/POE11#
SCK4/SCK6
ET0_RX_ER/
RMII0_RX_ER/
CAT0_RX_ER
58
PB1
MTIOC0C/
MTIOC4C/TIOCB3/
TMCI0/PO25
TXD4/SMOSI4/
SSDA4/TXD6/
SMOSI6/SSDA6
ET0_ERXD0/
RMII0_RXD0/
CAT0_ERXD0
IRQ4-DS
59
PB0
MTIC5W/TIOCA3/
PO24
RXD4/SMISO4/
SSCL4/RXD6/
SMISO6/SSCL6
ET0_ERXD1/
RMII0_RXD1/
CAT0_ERXD1
IRQ12
60
PA6
MTIC5V/MTCLKB/
TIOCA2/TMCI3/
PO22/POE10#
CTS5#/RTS5#/
SS5#
ET0_EXOUT/
CATRESTOUT
PA4
MTIC5U/MTCLKA/
TIOCA1/TMRI0/
PO20
TXD5/SMOSI5/
SSDA5
ET0_MDC/
CAT0_MDC/
CATIRQ/
PMGI0_MDC
IRQ5-DS
64
PA3
MTIOC0D/
MTCLKD/TIOCD0/
TCLKB/PO19
RXD5/SMISO5/
SSCL5
ET0_MDIO/
CAT0_MDIO/
PMGI0_MDIO
IRQ6-DS
65
PA2
MTIOC7A/PO18
RXD5/SMISO5/
SSCL5
CATLINKACT1
66
PG6
67
PA1
68
PG5
69
PA0
GTIOC0B
MTIOC4A/
MTIOC6D/TIOCA0/
PO16/CACREF
70
P67
MTIOC7C
GTIOC1B
CRX2
71
P66
MTIOC7D
GTIOC2B
CTX2
72
PG2
73
PE5
MTIOC4C/
MTIOC2B
GTIOC0A
ET0_RX_CLK/
REF50CK0/
CAT0_RX_CLK
74
PE4
MTIOC4D/
MTIOC1A/PO28
GTIOC1A
ET0_ERXD2/
CAT0_ERXD2
AN102
75
PE3
MTIOC4B/PO26/
POE8#
GTIOC2A
ET0_ERXD3/
CAT0_ERXD3
AN101
61
GTETRGB
A/D
D/A
VCC
62
63
GTIOC2B
Interrupt
VSS
GTIOC1A
ET1_ETXD3/
CAT1_ETXD3
MTIOC0B/
GTIOC2A
MTCLKC/
MTIOC7B/TIOCB0/
PO17
SCK5
ET0_WOL
IRQ11
ET1_ETXD2/
CAT1_ETXD2
ET0_TX_EN/
RMII0_TXD_EN/
CAT0_TX_EN/
CATLEDRUN
EPLSOUT1/
CATSYNC1
IRQ15
ET1_TX_CLK/
CAT1_TX_CLK
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
IRQ5
AN103
Page 79 of 180
RX72M Group
Table 1.9
1. Overview
List of Pin and Pin Functions (100-Pin LFQFP) (4/4)
Pin
Number Power
Supply
Clock
100-Pin System
LFQFP Control
I/O Port
76
P64
ET1_ETXD0/
RMII1_TXD0/
CAT1_ETXD0
77
P63
ET1_ETXD1/
RMII1_TXD1/
CAT1_ETXD1
78
P62
ET1_ERXD0/
RMII1_RXD0/
CAT1_ERXD0
79
P61
ET1_ERXD1/
RMII1_RXD1/
CAT1_ERXD1
P60
ET1_TX_EN/
RMII1_TXD_EN/
CAT1_TX_EN
80
Communication
(SCI, RSPI, RIIC,
CAN, USB, SSIE)
(ETHERC, ESC,
PMGI)
Interrupt
A/D
D/A
VSS
81
82
Timer
(MTU, TPU, TMR,
PPG, RTC, CMTW,
POE, CAC)
(GPTW, POEG)
VCC
83
PD7
MTIC5U/POE0#
ET1_RX_ER/
RMII1_RX_ER/
CAT1_RX_ER
IRQ7
AN107
84
PD6
MTIC5V/MTIOC8A/
POE4#
ET1_RX_CLK/
REF50CK1/
CAT1_RX_CLK
IRQ6
AN106
85
P97
ET1_ERXD3/
CAT1_ERXD3
86
P96
ET1_ERXD2/
CAT1_ERXD2
87
PD2
IRQ2
AN110
88
IRQ1
AN109
89
90
91
92
CRX0
ET1_EXOUT
PD1
MTIOC4B/POE0#
GTIOC1A
P93
POE0#
CTS7#/RTS7#/
SS7#
ET1_LINKSTA/
CAT1_LINKSTA
AN117
P92
POE4#
RXD7/SMISO7/
SSCL7
ET1_CRS/
RMII1_CRS_DV/
CAT1_RX_DV
AN116
P91
SCK7
ET1_COL
AN115
P90
TXD7/SMOSI7/
SSDA7
ET1_RX_DV/
CAT1_RX_DV
AN114
CTX0
VCC
95
96
97
GTIOC0B
VSS
93
94
MTIOC4D
P42
IRQ10-DS
AN002
P41
IRQ9-DS
AN001
P40
IRQ8-DS
AN000
VREFL0
98
99
VREFH0
100
AVCC0
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 80 of 180
RX72M Group
2. Electrical Characteristics
2.
Electrical Characteristics
2.1
Absolute Maximum Ratings
Table 2.1
Absolute Maximum Rating
Conditions: VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V
Item
Power supply voltage
VBATT power supply voltage
Input voltage (except for ports for 5 V
tolerant*1)
Input voltage (ports for 5 V tolerant*1)
Reference power supply voltage
Analog power supply voltage
D version
G version
Storage temperature
Value
Unit
VCC, VCC_USB
–0.3 to +4.0
V
VBATT
–0.3 to +4.0
V
Vin
–0.3 to VCC + 0.3 (up to 4.0)
V
Vin
–0.3 to VCC + 4.0 (up to 5.8)
V
VREFH0
–0.3 to AVCC0 + 0.3 (up to 4.0)
V
AVCC1*2
–0.3 to +4.0
V
VAN
–0.3 to AVCC + 0.3 (up to 4.0)
V
Tj
–40 to +105
°C
Tj
–40 to +125
°C
Tstg
–55 to +125
°C
AVCC0,
Analog input voltage
Junction temperature
Symbol
Caution: Permanent damage to the LSI may result if absolute maximum ratings are exceeded.
Note 1. P07, P11 to P17, P20, P21, P30 to P33, P67, and PC0 to PC3 are 5 V tolerant.
Note 2. Connect the AVCC0, AVCC1, and VCC_USB pins to VCC, and the AVSS0, AVSS1, and VSS_USB pins to VSS.
When the A/D converter unit 0 is not to be used, connect the VREFH0 pin to VCC and the VREFL0 pin to VSS, respectively.
Do not leave these pins open. Insert capacitors of high frequency characteristics between the AVCC0 and AVSS0 pins, or
AVCC1 and AVSS1 pins. Place capacitors of about 0.1 µF as close as possible to every power supply pin and use the shortest
and heaviest possible traces.
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 81 of 180
RX72M Group
2.2
2. Electrical Characteristics
Recommended Operating Conditions
Table 2.2
Recommended Operating Conditions (1)
Item
Symbol
Min.
Typ.
Max.
Unit
VCC
2.7
—
3.6
V
VSS
—
0
—
VBATT power supply voltage
VBATT
1.62*2
—
3.6
V
USB power supply voltage
VCC_USB
—
VCC
—
V
VSS_USB
—
0
—
AVCC0
—
VCC
—
AVSS0
—
0
—
AVCC1
—
VCC
—
Power supply voltage*1
Analog power supply
voltage*1, *3
V
AVSS1
—
0
—
VREFH0
2.7
—
AVCC0
VREFL0
—
0
—
Input voltage (except for 5 V tolerant ports,
except for P03, P05 and P40 to P47)*4
Vin
–0.3
—
VCC + 0.3
V
Input voltage (P03, P05 and P40 to P47)
Vin
–0.3
—
AVCC0 + 0.3
V
Input voltage (5V tolerant ports: P11 to P17, P20, P21,
P30 to P33, P67, and PC0 to PC3)*5
Vin
–0.3
—
VCC + 3.6 (up to 5.5)
V
Input voltage (5V tolerant port: P07)
Vin
–0.3
—
AVCC0 + 3.6 (up to 5.5)
V
Operating temperature (D version)
Topr
–40
—
85
°C
Operating temperature (G version)
Topr
–40
—
105
°C
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Comply with the following potential condition: VCC = AVCC0 = AVCC1 = VCC_USB
The low CL crystal unit cannot be used when the VBATT voltage is less than 2.0 V.
For details, refer to section 58.6.11, Voltage Range of Analog Power Supply Pins in the User’s Manual: Hardware.
P07, P11 to P17, P20, P21, P30 to P33, P67, and PC0 to PC3 are 5 V tolerant.
For P30 to P32, input as follows when the VBATT power supply is selected.
Vin Min. = –0.3, Max. = VBATT + 0.3 (VBATT = 1.62 to 3.6 V)
Table 2.3
Recommended Operating Conditions (2)
Item
Decoupling capacitance for stabilizing the internal voltage
Symbol
Value
CVCL
0.22 µF ± 30%*1
Note 1. Use a multilayer ceramic capacitor with a nominal capacitance of 0.22 µF, for which the sum of the capacitance tolerance and
change in the capacitance under the usage conditions will be no greater than ±30%.
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 82 of 180
RX72M Group
2.3
2. Electrical Characteristics
DC Characteristics
Table 2.4
DC Characteristics (1)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Schmitt trigger
input voltage
Symbol
Min.
Typ.
Max.
Unit
VIH
0.8 × VCC
—
—
V
VIL
—
—
0.2 × VCC
ΔVT
0.06 × VCC
—
—
VIH
0.7 × VCC
—
—
VIL
—
—
0.3 × VCC
ΔVT
0.05 × VCC
—
—
VIH
0.8 × VCC
—
—
VIL
—
—
0.2 × VCC
Other input pins excluding ports
for 5 V tolerant*3
VIH
0.8 × VCC
—
—
VIL
—
—
0.2 × VCC
MD pin, EMLE
VIH
0.9 × VCC
—
—
0.8 × VCC
—
—
2.3
—
—
0.7 × VCC
—
—
2.1
—
—
—
—
0.1 × VCC
EXTAL, RSPI input pin,
ETHERC input pin,
EXDMAC input pin, WAIT#,
SDHI input pin, MMC input pin,
PDC input pin, PMGI input pin,
ESC input pin (MII pin)
—
—
0.2 × VCC
D0 to D31
—
—
0.3 × VCC
RIIC (SMBus)
—
—
0.8
IRQ input pin*1,
MTU input pin*1,
POE input pin*1,
TPU input pin*1,
TMR input pin*1,
CMTW input pin*1,
SCI input pin*1,
CAN input pin*1,
CAC input pin*1,
ADTRG# input pin*1,
QSPI input pin*1,
SSIE input pin*1,
DSMIF input pin*1,
GPTW input pin*1,
POEG input pin*1,
ESC input pin (except for MII
pin)*1,
RES#, NMI, TCK
RIIC input pin
(except for SMBus)
Ports for 5 V
High level input
voltage (except for
Schmitt trigger
input pin)
tolerant*2
EXTAL, RSPI input pin,
EXDMAC input pin, WAIT#,
SDHI input pin, MMC input pin,
PDC input pin, PMGI input pin
ETHERC input pin,
ESC input pin (MII pin)
D0 to D31
RIIC (SMBus)
Low level input
voltage (except for
Schmitt trigger
input pin)
MD pin, EMLE
VIL
Test
Conditions
V
V
Note 1. This does not include the pins, which are multiplexed as ports for 5 V tolerant.
Note 2. P07, P11 to P17, P20, P21, P30 to P33, P67, and PC0 to PC3 are 5 V tolerant.
Note 3. For P30 to P32, input as follows when the VBATT power supply is selected.
VIH Min. = VBATT × 0.8, VIL Max. = VBATT × 0.2 (VBATT = 1.62 to 3.6 V)
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 83 of 180
RX72M Group
Table 2.5
2. Electrical Characteristics
DC Characteristics (2)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Output high voltage
All output pins
VOH
VCC – 0.5
—
—
V
IOH = –1 mA
Output low voltage
All output pins
(except for RIIC pins and
ETHERC output pin)
VOL
—
—
0.5
V
IOL = 1.0 mA
—
—
0.4
IOL = 3.0 mA
—
—
0.6
IOL = 6.0 mA
—
—
0.4
—
0.4
—
VOL
—
—
0.4
V
IOL = 1.0 mA
| Iin |
—
—
1.0
µA
Vin = 0 V
Vin = VCC
| ITSI |
—
—
1.0
µA
Vin = 0 V
Vin = VCC
—
—
5.0
RIIC output pin
RIIC output pin
(only P12 and P13 in channel 0)
ETHERC output pin
EMLE*1,
Input leakage current RES#, MD pin,
BSCANP*1, NMI
Three-state leakage
current (off state)
Other than ports for 5 V tolerant
VOL
Ports for 5 V tolerant
V
IOL = 15.0 mA
(ICFER.FMPE = 1)
IOL = 20.0 mA
(ICFER.FMPE = 1)
Vin = 0 V
Vin = 5.5 V
Input pull-up resistor
current
Other than P35
Ip
–300
—
–10
µA
VCC = 2.7 to 3.6 V
Vin = 0 V
Input pull-down
resistor current
EMLE, BSCANP
Ip
10
—
300
µA
Vin = VCC
Input capacitance
All input pins
(except for P03, P05, P12, P13,
P16, P17, P20, P21, EMLE,
BSCANP, USB0_DP, and
USB0_DM)
Cin
—
—
8
pF
Vbias = 0 V
Vamp = 20 mV
f = 1 MHz
Ta = 25°C
—
—
16
—
1.18
—
P03, P05, P12, P13, P16, P17,
P20, P21, EMLE, BSCANP,
USB0_DP, and USB0_DM
Output voltage of the VCL pin
VCL
V
Note 1. The input leakage current value at the EMLE and BSCANP pins are only when Vin = 0 V.
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RX72M Group
Table 2.6
2. Electrical Characteristics
DC Characteristics (3)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Symbol
Full operation*2
High-speed operating mode
Supply
current
*1
ICC*3
D version
Typ.
Max.
G version
Typ.
Max.
—
261
—
319
Normal
Peripheral module clocks are supplied
operation *4
61
—
61
—
Peripheral module clocks are stopped
*4, *5
30
—
30
—
Peripheral module clocks are stopped
*4, *5
37
—
37
—
Sleep mode: Peripheral module clocks are
supplied*4
42
144
42
196
All module clock stop mode (reference value)
Core
Mark
Increased by BGO
operation*8
14
115
14
167
Reading from the code flash
memory while the data flash
memory is being programmed
6
—
6
—
Reading from the code flash
memory while the code flash
memory is being programmed
7
—
7
—
Test Conditions
mA
ICLK = 240 MHz,
PCLKA = 120 MHz,
PCLKB = 60 MHz,
PCLKC = 60 MHz,
PCLKD = 60 MHz,
FCLK = 60 MHz,
BCLK = 120 MHz,
BCLK pin = 60 MHz
—
15
—
15
Low-speed operating mode 1: Peripheral module clocks
are stopped*4
4.2
—
4.2
—
All clocks 1 MHz
Low-speed operating mode 2: Peripheral module clocks
are stopped*4
4.2
—
4.2
—
All clocks 32.768
kHz
Software standby mode
3.95
107
3.95
155
Power is supplied to the standby RAM and USB
resume detecting unit (USB0 only)
15.5
70
15.5
98
Power is not
supplied to the
standby RAM and
USB resume
detecting unit
(USB0 only)
Low power consumption
function of the power-on reset
circuit is disabled*6
11.5
42
11.5
58
Low power consumption
function of the power-on reset
circuit is enabled*7
4.9
32
4.9
47
Increase current
by operating RTC
When a low CL crystal is in
use
1
—
1
—
When a standard CL crystal is
in use
2
—
2
—
0.9
—
0.9
—
VBATT = 2.0 V,
VCC = 0 V
1.6
—
1.6
—
VBATT = 3.3 V,
VCC = 0 V
1.6
—
1.6
—
VBATT = 1.62 V,
VCC = 0 V
1.7
—
1.7
—
VBATT = 2.0 V,
VCC = 0 V
3.3
—
3.3
—
VBATT = 3.3 V,
VCC = 0 V
—
211
—
211
Deep software standby mode
Increased by Trusted Secure IP operation
Unit
When the RTC is
operating while VCC is
not supplied (Only the
RTC and sub-clock
oscillator operate with
the battery backup
function)
Inrush current on
returning from deep
software standby mode
When a low CL crystal is in
use
When a standard CL crystal is
in use
Inrush current*9
IRUSH
µA
mA
Note 1. Supply current values are measured when all output pins are unloaded and all input pull-up resistors are disabled.
Note 2. Peripheral module clocks are supplied.
Note 3. ICC depends on the f (ICLK) as follows.
(when ICLK : PCLKA : PCLKB/PCLKC/PCLKD : BCLK : BCLK pin = 4 : 2 : 1 : 2 : 1 and EXTAL = 12 MHz)
D version
ICC max. = 0.62 × f + 113 (full operation in high-speed operating mode)
ICC typ. = 0.22 × f + 7 (normal operation in high-speed operating mode)
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Nov 15, 2023
Page 85 of 180
RX72M Group
Note 4.
Note 5.
Note 6.
Note 7.
Note 8.
Note 9.
2. Electrical Characteristics
ICC typ. = 0.50 × f + 3.7 (ICLK 1 MHz max) (low-speed operating mode 1)
ICC max. = 0.13 × f + 113 (sleep mode)
G version
ICC max. = 0.65 × f + 164 (full operation in high-speed operating mode)
ICC typ. = 0.22 × f + 7 (normal operation in high-speed operating mode)
ICC typ. = 0.50 × f + 3.7 (ICLK 1 MHz max) (low-speed operating mode 1)
ICC max. = 0.13 × f + 164 (sleep mode)
Whether the peripheral module clocks are supplied or stopped is controlled only by the bit settings in the module stop control
registers A to D.
When the peripheral module clock is stopped, the settings of the clock frequency are as follows:
ICLK = 240 MHz and PCLKA = PCLKB = PCLKC = PCLKD = FCLK = BCLK = BCLK pin = 3.75 MHz (divided by 64).
When the low power consumption function is disabled, the DEEPCUT[1:0] bits are set to 01b.
When the low power consumption function is enabled, the DEEPCUT[1:0] bits are set to 11b.
These are the increases during programming of the code flash memory after the code flash memory (limitations apply to the
combinations of address ranges of the program area and the readable area) or the data flash memory has been programmed or
erased.
Reference value
Table 2.7
DC Characteristics (4)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Symbol
Analog
During 12-bit A/D conversion (unit 0)
power
During 12-bit A/D conversion (unit 0)
supply
with channel-dedicated sample-andcurrent*1, *3
hold circuits (3 channels)
AICC
Reference
power
supply
current
USB
operating
current
D version
Min.
Typ.
—
—
During 12-bit A/D conversion (unit 1)
G version
Test Conditions
Min.
Typ.
0.8
1
—
0.8
1
1.7
2.5
—
1.7
2.5
—
0.6
1
—
0.6
1
During 12-bit A/D conversion (unit 1)
+ temperature sensor
—
0.7
1.1
—
0.7
1.1
IAVCC1_AD +
TEMP
During D/A
conversion
(2 channels)
Unbuffered output
—
0.25
0.4
—
0.25
0.4
IAVCC1_DA
Buffered output
—
0.75
1.1
—
0.75
1.1
Waiting for A/D, D/A, and
temperature sensor conversion
(all units)
—
0.9
1.4
—
0.9
1.4
A/D, D/A, and temperature sensor
are in standby mode (all units)
—
1.4
6.7
—
1.4
9.0
µA
IAVCC0 +
IAVCC1
—
38
60
—
38
60
µA
IVREFH0
Waiting for 12-bit A/D conversion
(unit 0)
—
0.07
0.5
—
0.07
0.6
IVREFH0
12-bit A/D converter in module stop
mode (unit 0)
—
0.07
0.4
—
0.07
0.5
IVREFH0
During 12-bit A/D conversion (unit 0)
AIREFH
Max.
Unit
Max.
mA
IAVCC0_AD
IAVCC0_AD + SH
IAVCC1_AD
IAVCC0 +
IAVCC1
Low speed
USB0
ICCUSBLS
—
3.7
6.5
—
3.7
6.5
mA
VCC_USB
Full speed
USB0
ICCUSBFS
—
4.2
10
—
4.2
10
mA
VCC_USB
—
V
VRAM
2.7
—
—
2.7
—
VCC rising gradient
SrVCC
8.4
—
20000
8.4
—
VCC falling gradient*2
SfVCC
8.4
—
—
8.4
—
RAM retension voltage
20000 µs/V
—
µs/V
Note 1. The reference power supply current is included in the power supply current value for 12-bit A/D converter (unit 1) and D/A
converter.
Note 2. This applies when VBATT is used.
Note 3. Supply current values are measured when all output pins are unloaded.
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Nov 15, 2023
Page 86 of 180
RX72M Group
Table 2.8
2. Electrical Characteristics
Permissible Output Currents
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Permissible output low current
(average value per pin)
Permissible output low current
(max. value per pin)
All output
pins*1
Normal drive
All output
pins*2
Permissible output high current
(average value per pin)
Permissible output high current
(max. value per pin)
Typ.
Max.
Unit
IOL
—
—
2.0
mA
High drive
—
—
3.8
High-speed interface
high-drive
—
—
7.5
All output pins*1
Normal drive
—
—
4.0
All output pins*2
High drive
—
—
7.6
High-speed interface
high-drive
—
—
15
ΣIOL
—
—
80
mA
IOH
mA
pins*3
IOL
Total of all output pins
All output
pins*1
—
—
–2.0
All output pins*2
High drive
—
—
–3.8
All output pins*3
High-speed interface
high-drive
—
—
–7.5
All output pins*1
Normal drive
—
—
–4.0
All output
pins*2
All output pins*3
Permissible output high current (total)
Min.
All output pins*3
All output
Permissible output low current (total)
Symbol
Normal drive
IOH
High drive
—
—
–7.6
High-speed interface
high-drive
—
—
–15
—
—
–80
Total of all output pins
ΣIOH
mA
mA
mA
Caution: To protect the MCU’s reliability, the output current values should not exceed the values in Table 2.8.
Note 1. This is the value when normal driving ability is set with a pin for which normal driving ability is selectable.
Note 2. This is the value when high driving ability is set with a pin for which normal driving ability is selectable or the value of the pin to
which high driving ability is fixed.
Note 3. This is the value when high-speed interface high-driving ability is set with a pin for which high-speed interface high-driving ability
is selectable.
Table 2.9
Thermal Resistance Value (Reference)
Item
Thermal resistance
Package
176-pin LFQFP (PLQP0176KB-C)
ja
Max.
Unit
31.5
°C/W
144-pin LFQFP (PLQP0144KA-B)
32.6
100-pin LFQFP (PLQP0100KB-B)
34.0
224-pin LFBGA (PLBG0224GA-A)
23.1
176-pin LFBGA (PLBG0176GA-A)
30.5
176-pin LFQFP (PLQP0176KB-C)
Note:
Symbol
jt
0.4
144-pin LFQFP (PLQP0144KA-B)
0.5
100-pin LFQFP (PLQP0100KB-B)
0.6
224-pin LFBGA (PLBG0224GA-A)
0.2
176-pin LFBGA (PLBG0176GA-A)
0.3
Test Conditions
JESD51-2 and
JESD51-7 compliant
JESD51-2 and
JESD51-9 compliant
°C/W
JESD51-2 and
JESD51-7 compliant
JESD51-2 and
JESD51-9 compliant
The values are reference values when the 4-layer board is used. Thermal resistance depends on the number of layers or size of
the board. For details, refer to the JEDEC standards.
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 87 of 180
RX72M Group
2.4
2. Electrical Characteristics
AC Characteristics
Table 2.10
Operating Frequency (High-Speed Operating Mode)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Operating
frequency
Symbol
Min.
Typ.
Max.
Unit
f
—
—
240
MHz
Peripheral module clock (PCLKA)
—
—
120
Peripheral module clock (PCLKB)
—
—
60
Peripheral module clock (PCLKC)
—
—
60
System clock (ICLK)
Peripheral module clock (PCLKD)
—
—
60
—*1
—
60
External bus clock (BCLK)
—
—
120
BCLK pin output
—
—
80
SDRAM clock (SDCLK)
—
—
80
SDCLK pin output
—
—
80
Flash-IF clock (FCLK)
Note 1. The FCLK must run at a frequency of at least 4 MHz when changing the flash memory contents.
Table 2.11
Operating Frequency (Low-Speed Operating Mode 1)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Operating
frequency
System clock (ICLK)
Symbol
Min.
Typ.
Max.
Unit
f
MHz
—
—
1
Peripheral module clock (PCLKA)
—
—
1
Peripheral module clock (PCLKB)
—
—
1
(PCLKC)*1
—
—
1
Peripheral module clock (PCLKD)*1
—
—
1
Flash-IF clock (FCLK)
—
—
1
Peripheral module clock
External bus clock (BCLK)
—
—
1
BCLK pin output
—
—
1
SDRAM clock (SDCLK)
—
—
1
SDCLK pin output
—
—
1
Note 1. When the 12-bit A/D converter is used, the frequency must be set to at least 1 MHz.
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Page 88 of 180
RX72M Group
Table 2.12
2. Electrical Characteristics
Operating Frequency (Low-Speed Operating Mode 2)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Operating
frequency
Symbol
Min.
Typ.
Max.
Unit
f
32
—
264
kHz
Peripheral module clock (PCLKA)
—
—
264
Peripheral module clock (PCLKB)
—
—
264
—
—
264
System clock (ICLK)
Peripheral module clock
(PCLKC)*1
Peripheral module clock
(PCLKD)*1
—
—
264
Flash-IF clock (FCLK)
32
—
264
External bus clock (BCLK)
—
—
264
BCLK pin output
—
—
264
SDRAM clock (SDCLK)
—
—
264
SDCLK pin output
—
—
264
Note 1. The 12-bit A/D converter cannot be used.
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RX72M Group
2.4.1
Table 2.13
2. Electrical Characteristics
Reset Timing
Reset Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
RES# pulse
width
Test
Conditions
Symbol
Min.
Typ.
Max.
Unit
Power-on
tRESWP
1
—
—
ms
Figure 2.1
Deep software standby mode
tRESWD
0.6
—
—
ms
Figure 2.2
Software standby mode, low-speed operating
mode 2
tRESWS
0.3
—
—
ms
Programming or erasure of the code flash
memory, or programming, erasure or blank
checking of the data flash memory
tRESWF
200
—
—
µs
Other than above
tRESW
200
—
—
µs
Waiting time after release from the RES# pin reset
tRESWT
54
—
55
tLcyc
Internal reset time
(independent watchdog timer reset, watchdog timer reset,
software reset)
tRESW2
100
—
108
tLcyc
Figure 2.1
VCC
RES#
Internal reset signal
(Low is valid)
tRESWP
tRESWT
Figure 2.1
Reset Input Timing at Power-On
tRESWD, tRESWS, tRESWF, tRESW
RES#
Internal reset signal
(Low is valid)
tRESWT
Figure 2.2
Reset Input Timing
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RX72M Group
2.4.2
Table 2.14
2. Electrical Characteristics
Clock Timing
BCLK Pin Output, SDCLK Pin Output Clock Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
BCLK pin output cycle time
tBcyc
12.5
—
—
ns
BCLK pin output high pulse width
tCH
3.25
—
—
ns
BCLK pin output low pulse width
tCL
3.25
—
—
ns
BCLK pin output rising time
tCr
—
—
3
ns
BCLK pin output falling time
tCf
—
—
3
ns
SDCLK pin output cycle time
tBcyc
12.5
—
—
ns
SDCLK pin output high pulse width
tCH
3.25
—
—
ns
SDCLK pin output low pulse width
tCL
3.25
—
—
ns
SDCLK pin output rising time
tCr
—
—
3
ns
SDCLK pin output falling time
tCf
—
—
3
ns
Test
Conditions
Figure 2.3
tBcyc, tSDcyc
tCH
tCf
BCLK pin output, SDCLK pin output
tCL
tCr
Test conditions: VOH = 0.7 × VCC, VOL = 0.3 × VCC, C = 30 pF
Figure 2.3
BCLK Pin and SDCLK Pin Output Timing
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Nov 15, 2023
Page 91 of 180
RX72M Group
Table 2.15
2. Electrical Characteristics
EXTAL Clock Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Symbol
fEXMAIN ≤ 24 MHz
Min.
Typ.
fEXMAIN > 24 MHz
Max.
Min.
Typ.
Max.
Unit
EXTAL external clock input cycle time
tEXcyc
41.66
—
—
33.33
—
—
ns
EXTAL external clock input frequency
fEXMAIN
—
—
24
—
—
30
MHz
EXTAL external clock input high pulse width
tEXH
15.83
—
—
13.33
—
—
ns
EXTAL external clock input low pulse width
tEXL
15.83
—
—
13.33
—
—
ns
EXTAL external clock rising time
tEXr
—
—
5
—
—
5
ns
EXTAL external clock falling time
tEXf
—
—
5
—
—
5
ns
Test
Conditions
Figure 2.4
tEXcyc
tEXH
tEXL
EXTAL external clock input
0.5 × VCC
tEXr
Figure 2.4
Table 2.16
tEXf
EXTAL External Clock Input Timing
Main Clock Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Symbol
Main clock oscillation frequency
Main clock oscillator stabilization time (crystal)
Main clock oscillation stabilization wait time (crystal)
Min.
Typ.
fMAIN
8
tMAINOSC
—
tMAINOSCWT
—
Max.
Unit
—
24
MHz
—
—*1
ms
—
—*2
ms
Test
Conditions
Figure 2.5
Note 1. When using a main clock, ask the manufacturer of the oscillator to evaluate its oscillation. Refer to the results of evaluation
provided by the manufacturer for the oscillation stabilization time.
Note 2. The number of cycles selected by the value of the MOSCWTCR.MSTS[7:0] bits determines the main clock oscillation
stabilization wait time in accord with the formula below.
tMAINOSCWT = [(MSTS[7:0] bits × 32) + 10] / fLOCO
MOSCCR.MOSTP
tMAINOSC
Main clock oscillator output
tMAINOSCWT
OSCOVFSR.MOOVF
Main clock
Figure 2.5
Main Clock Oscillation Start Timing
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RX72M Group
Table 2.17
2. Electrical Characteristics
LOCO and IWDT-Dedicated Low-Speed Clock Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
LOCO clock cycle time
LOCO clock oscillation frequency
Symbol
Min.
Typ.
Max.
Unit
tLcyc
4.63
4.16
3.78
µs
fLOCO
216
240
264
kHz
LOCO clock oscillation stabilization wait time
tLOCOWT
—
—
44
µs
IWDT-dedicated low-speed clock cycle time
tILcyc
9.26
8.33
7.57
µs
fILOCO
108
120
132
kHz
tILOCOWT
—
142
190
µs
IWDT-dedicated low-speed clock oscillation frequency
IWDT-dedicated low-speed clock oscillation stabilization wait
time
Test
Conditions
Figure 2.6
Figure 2.7
LOCOCR.LCSTP
On-chip oscillator output
tLOCOWT
LOCO clock
Figure 2.6
LOCO Clock Oscillation Start Timing
ILOCOCR.ILCSTP
IWDT-dedicated on-chip
oscillator output
tILOCOWT
OSCOVFSR.ILCOVF
IWDT-dedicated
low-speed clock
Figure 2.7
IWDT-dedicated Low-Speed Clock Oscillation Start Timing
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RX72M Group
Table 2.18
2. Electrical Characteristics
HOCO Clock Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
HOCO clock oscillation frequency
Symbol
Min.
Typ.
Max.
Unit
fHOCO
15.61
16
16.39
MHz
17.56
18
18.44
19.52
20
20.48
15.52
16
16.48
17.46
18
18.54
19.4
20
20.6
Test Conditions
Ta ≥ –20°C
–40°C ≤ Ta < –20°C
HOCO clock oscillation stabilization wait time
tHOCOWT
—
105
149
µs
Figure 2.8
HOCO clock power supply stabilization time
tHOCOP
—
—
150
µs
Figure 2.9
HOCOCR.HCSTP
High-speed on-chip
oscillator output
tHOCOWT
OSCOVFSR.HCOVF
HOCO clock
Figure 2.8
HOCO Clock Oscillation Start Timing (Oscillation is Started by Setting the HOCOCR.HCSTP Bit)
HOCOPCR.HOCOPCNT
HOCOCR.HCSTP
tHOCOP
Internal power supply for
high-speed on-chip oscillator
Figure 2.9
High-Speed On-Chip Oscillator Power Supply Control Timing
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RX72M Group
Table 2.19
2. Electrical Characteristics
PLL/PPLL Clock Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
PLL/PPLL clock oscillation frequency
PLL/PPLL clock oscillation stabilization wait time
Test
Conditions
Symbol
Min.
Typ.
Max.
Unit
fPLL
120
—
240
MHz
tPLLWT
—
259
320
µs
Figure 2.10
Test
Conditions
PLLCR2.PLLEN
PPLLCR2.PPLLEN
PLL/PPLL circuit output
tPLLWT
OSCOVFSR.PLOVF
OSCOVFSR.PPLOVF
PLL/PPLL clock
Figure 2.10
Table 2.20
PLL/PPLL Clock Oscillation Start Timing
Sub-Clock Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
VBATT = 1.62 to 3.6 V, Ta = Topr
Item
Sub-clock oscillation frequency
Sub-clock oscillation stabilization time
Sub-clock oscillation stabilization wait time
Symbol
Min.
Typ.
Max.
Unit
fSUB
—
32.768
—
kHz
tSUBOSC
—
—
*1
s
—
*2
s
tSUBOSCWT
—
Figure 2.11
Note 1. When using a sub-clock, ask the manufacturer of the oscillator to evaluate its oscillation. Refer to the results of evaluation
provided by the manufacturer for the oscillation stabilization time.
Note 2. The number of cycles selected by the value of the SOSCWTCR.SSTS[7:0] bits determines the sub-clock oscillation stabilization
wait time in accord with the formula below.
tSUBOSCWT = [(SSTS[7:0] bits × 16384) + 10] / fLOCO
SOSCCR.SOSTP
tSUBOSC
Sub-clock oscillator output
tSUBOSCWT
OSCOVFSR.SOOVF
Sub-clock
Figure 2.11
Sub-Clock Oscillation Start Timing
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RX72M Group
Table 2.21
2. Electrical Characteristics
CLKOUT Pin Output Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr,
High-drive output is selected by the drive capacity control register
Item
CLKOUT pin output cycle time
CLKOUT pin output high pulse
width*1
Symbol
Min.
Typ.
Max.
Unit
tCcyc
25
—
—
ns
tCH
5
—
—
ns
CLKOUT pin output low pulse width*1
tCL
5
—
—
ns
CLKOUT pin output rising time
tCr
—
—
5
ns
CLKOUT pin output falling time
tCf
—
—
5
ns
Test
Conditions
Figure 2.12
tCcyc = 25 ns
Note 1. If the main clock oscillator is selected by the CLKOUT output source select bit (CKOCR.CKOSEL[2:0]) and the external clock
input is selected by the main clock oscillator switching bit (MOFCR.MOSEL), the pulse width depends on the input clock wave
form.
tCcyc
tCH
tCf
CLKOUT pin output
tCr
tCL
Test Conditions VOH = 0.7 × VCC, VOL = 0.3 × VCC, C = 30pF
Figure 2.12
Table 2.22
CLKOUT Pin Output Timing
CLKOUT25M Pin Output Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr,
High-speed interface high-drive is selected by the drive capacity control register
Item
Symbol
CLKOUT25M pin output cycle time
Min.
Typ.
Max.
Unit
Test
Conditions
Figure 2.13
tCcyc
—
40
—
ns
CLKOUT25M pin output high pulse width
tCH
13
—
—
ns
CLKOUT25M pin output low pulse width
tCL
13
—
—
ns
CLKOUT25M pin output rising time
tCr
—
—
3
ns
CLKOUT25M pin output falling time
tCf
—
—
3
ns
tCcyc
tCH
tCf
CLKOUT25M pin output
tCL
tCr
Test Conditions VOH = 0.7 × VCC, VOL = 0.3 × VCC, C = 30pF
Figure 2.13
CLKOUT25M Pin Output Timing
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RX72M Group
2.4.3
Table 2.23
2. Electrical Characteristics
Timing of Recovery from Low Power Consumption Modes
Timing of Recovery from Low Power Consumption Modes (1)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Recovery time
from software
standby mode
*1
Crystal
resonator
connected to
main clock
oscillator
Symbol Min. Typ.
tSBYSEQ*3
100 + 7 / fICLK +
2n / fMAIN
tSBYPC
{(MSTS[7:0] bit × 32)
+ 138} / 0.216
100 + 7 / fICLK +
2n / fPLL
tSBYEX
352
100 + 7 / fICLK +
2n / fEXMAIN
Main clock
oscillator and
PLL circuit
operating
tSBYPE
639
100 + 7 / fICLK +
2n / fPLL
Sub-clock oscillator operating
tSBYSC
{(SSTS[7:0] bit ×
16384) + 13} / 0.216
+ 10 / fFCLK
100 + 4 / fICLK +
2n / fSUE
High-speed
on-chip
oscillator
operating
High-speed
on-chip
oscillator
operating
tSBYHO
454
100 + 7 / fICLK +
2n / fHOCO
High-speed
on-chip
oscillator
operating and
PLL circuit
operating
tSBYPH
741
100 + 7 / fICLK +
2n / fPLL
tSBYLO
338
100 + 7 / fICLK +
2n / fLOCO
tSBYMC
Main clock
oscillator and
PLL circuit
operating
External clock Main clock
input to main
oscillator
clock oscillator operating
Low-speed on-chip oscillator
operating*4
—
tSBYOSCWT
{(MSTS[7:0] bit × 32)
+ 76} / 0.216
Main clock
oscillator
operating
—
Max.
*2
Unit
Test
Conditions
µs
Figure 2.14
Note 1. The time for recovery from software standby mode is determined by the value obtained by adding the oscillation stabilization
waiting time (tSBYOSCWT) and the time required for operations by the software standby release sequencer (tSBYSEQ).
Note 2. When several oscillators were running before the transition to software standby, the greatest value of the oscillation stabilization
waiting time tSBYOSCWT is selected.
Note 3. For n, the greatest value is selected from among the internal clock division settings.
Note 4. This condition applies when fICLK:fFCLK = 1:1, 2:1, or 4:1.
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2. Electrical Characteristics
Oscillator
(System clock)
tSBYOSCWT
tSBYSEQ
Oscillator
(Other than the system clock)
ICLK
IRQ
Software standby mode
tSBYMC, tSBYEX, tSBYPC, tSBYPE,
tSBYPH, tSBYSC, tSBYHO, tSBYLO
When stabilization of the system clock oscillator is slower
Oscillator
(System clock)
tSBYOSCWT
tSBYSEQ
Oscillator
(Other than the system clock)
tSBYOSCWT
ICLK
IRQ
Software standby mode
tSBYMC, tSBYEX, tSBYPC, tSBYPE,
tSBYPH, tSBYSC, tSBYHO, tSBYLO
When stabilization of an oscillator other than the system clock is slower
Figure 2.14
Software Standby Mode Recovery Timing
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RX72M Group
Table 2.24
2. Electrical Characteristics
Timing of Recovery from Low Power Consumption Modes (2)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Recovery time from deep software standby mode
Wait time after recovery from deep software standby mode
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
tDSBY
—
—
0.9
ms
Figure 2.15
tDSBYWT
23
—
24
tLcyc
Oscillator
IRQ
Deep software standby reset
(Low is valid)
Internal reset
(Low is valid)
Deep software standby mode
tDSBY
tDSBYWT
Reset exception handling start
Figure 2.15
Deep Software Standby Mode Recovery Timing
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2.4.4
2. Electrical Characteristics
Control Signal Timing
Table 2.25
Control Signal Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKB = 8 to 60 MHz, Ta = Topr
Symbol
Min.*1
Typ.
Max.
Unit
NMI pulse width
tNMIW
200
—
—
ns
tPBcyc × 2 ≤ 200 ns, Figure 2.16
IRQ pulse width
tIRQW
ns
tPBcyc × 2 ≤ 200 ns, Figure 2.17
Item
tPBcyc × 2
—
—
200
—
—
tPBcyc × 2
—
—
Test Conditions*1
tPBcyc × 2 > 200 ns, Figure 2.16
tPBcyc × 2 > 200 ns, Figure 2.17
Note 1. tPBcyc: PCLKB cycle
NMI
Figure 2.16
tNMIW
tNMIW
tIRQW
tIRQW
NMI Interrupt Input Timing
IRQn
Figure 2.17
IRQ Interrupt Input Timing
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2.4.5
2. Electrical Characteristics
Bus Timing
Table 2.26
Bus Timing
Conditions 1: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
ICLK = 8 to 240 MHz, PCLKA = 8 to 120 MHz, PCLKB = BCLK = SDCLK = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Conditions 2: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 3.0 to 3.6 V, 3.0 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
ICLK = 60 to 240 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, 60 MHz < BCLK = SDCLK ≤ 80 MHz,
Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC,
C = 15 pF for the SDCLK pin, C = 30 pF for other pins.
To control the drive capacity when using the SDRAM: set the PFBCR3.SDCLKDRV bit in external bus control
register 1 to 1 to select the drive capacity of the SDCLK pin,
and set the SDRAM pins other than the SDCLK pin as highspeed-interface driving outputs.
Item
Symbol
Conditions 1
Conditions 2
Min.
Max.
Min.
Max.
Unit
Address delay time
tAD
—
12.5
—
12.5
ns
Byte control delay time
tBCD
—
12.5
—
12.5
ns
CS# delay time
tCSD
—
12.5
—
12.5
ns
ALE delay time
tALED
—
12.5
—
12.5
ns
RD# delay time
tRSD
—
12.5
—
12.5
ns
Read data setup time
tRDS
12.5
—
12.5
—
ns
Read data hold time
tRDH
0
—
0
—
ns
WR# delay time
tWRD
—
12.5
—
12.5
ns
Write data delay time
tWDD
—
12.5
—
12.5
ns
Write data hold time
tWDH
0
—
0
—
ns
WAIT# setup time
tWTS
12.5
—
12.5
—
ns
WAIT# hold time
tWTH
0
—
0
—
ns
Address delay time 2 (SDRAM)
tAD2
1
12.5
1
10.0
ns
CS# delay time 2 (SDRAM)
tCSD2
1
12.5
1
10.0
ns
DQM delay time (SDRAM)
tDQMD
1
12.5
1
10.0
ns
CKE delay time (SDRAM)
tCKED
1
12.5
1
10.0
ns
Read data setup time 2 (SDRAM)
tRDS2
10
—
6.0
—
ns
Read data hold time 2 (SDRAM)
tRDH2
0
—
0
—
ns
Write data delay time 2 (SDRAM)
tWDD2
—
12.5
—
10.0
ns
Write data hold time 2 (SDRAM)
tWDH2
1
—
1
—
ns
WE# delay time (SDRAM)
tWED
1
12.5
1
10.0
ns
RAS# delay time (SDRAM)
tRASD
1
12.5
1
10.0
ns
CAS# delay time (SDRAM)
tCASD
1
12.5
1
10.0
ns
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Test Conditions
Figure 2.18 to
Figure 2.23
Figure 2.24
Figure 2.25 to
Figure 2.31
Page 101 of 180
RX72M Group
2. Electrical Characteristics
Data cycle
Address cycle
Ta1
Ta1
Tan
TW1
TW2
TW3
TW4
Tend
TW5
Tn1
Tn2
BCLK
tAD
Address bus
tAD
Address bus/
data bus
tRDS
tAD
tRDH
tALED
tALED
Address latch
(ALE)
tRSD
tRSD
Data read
(RD#)
Figure 2.18
tCSD
tCSD
Chip select
(CS1#)
Address/Data Multiplexed Bus Read Access Timing
Data cycle
Address cycle
Ta1
Ta1
Tan
TW1
TW2
TW3
TW4
TW5
Tend
Tn1
Tn2
Tn3
BCLK
tAD
Address bus
Address bus/
data bus
tAD
tAD
tALED
tWDD
tWDH
tALED
Address latch
(ALE)
tWRD
tWRD
Data write
(WRm#)
tCSD
Chip select
(CS1#)
Figure 2.19
tCSD
Address/Data Multiplexed Bus Write Access Timing
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2. Electrical Characteristics
CSRWAIT:2
RDON:1
CSROFF:2
CSON:0
TW1
TW2
Tend
Tn1
Tn2
BCLK
Byte strobe mode
tAD
tAD
tAD
tAD
tBCD
tBCD
tCSD
tCSD
A23 to A0
1-write strobe mode
A23 to A1
BC3# to BC0#
Common to both byte strobe mode
and 1-write strobe mode
CS7# to CS0#
tRSD
tRSD
RD# (Read)
tRDS
tRDH
D31 to D0 (Read)
Figure 2.20
External Bus Timing/Normal Read Cycle (Bus Clock Synchronized)
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2. Electrical Characteristics
CSWWAIT:2
WRON:1
WDON:1 *1
CSWOFF:2
WDOFF:1 *1
CSON:0
TW1
TW2
Tend
Tn1
Tn2
BCLK
Byte strobe mode
tAD
tAD
tAD
tAD
tBCD
tBCD
tCSD
tCSD
A23 to A0
1-write strobe mode
A23 to A1
BC3# to BC0#
Common to both byte strobe mode
and 1-write strobe mode
CS7# to CS0#
tWRD
tWRD
WR3# to WR0#, WR# (Write)
tWDD
tWDH
D31 to D0 (Write)
Note 1. Be sure to specify WDON and WDOFF as at least one cycle of BCLK.
Figure 2.21
External Bus Timing/Normal Write Cycle (Bus Clock Synchronized)
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2. Electrical Characteristics
CSRWAIT:2
CSON:0
CSPRWAIT:2
CSPRWAIT:2
RDON:1
RDON:1
TW1
TW2
Tend
CSPRWAIT:2
RDON:1
Tpw1
Tpw2
Tend
CSROFF:2
RDON:1
Tpw1
Tpw2
Tend
Tpw1
Tpw2
Tend
Tn1
Tn2
BCLK
Byte strobe mode
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tAD
A23 to A0
1-write strobe mode
A23 to A1
tBCD
tBCD
tCSD
tCSD
BC3# to BC0#
Common to both byte strobe mode
and 1-write strobe mode
CS7# to CS0#
tRSD
tRSD
tRSD
tRSD
tRSD
tRSD
tRSD
tRSD
RD# (Read)
tRDS
tRDH
tRDS
tRDH
tRDS
tRDH
tRDS
tRDH
D31 to D0 (Read)
Figure 2.22
External Bus Timing/Page Read Cycle (Bus Clock Synchronized)
CSPWWAIT:2
CSWWAIT:2
WRON:1
WDON:1 *1
WDOFF:1
CSON:0 TW1
TW2
Tend
Tdw1
*1
WRON:1
WDON:1 *1
Tpw1
CSPWWAIT:2
WDOFF:1
Tpw2
Tend
*1
Tdw1
WRON:1
WDON:1 *1
Tpw1
CSWOFF:2
WDOFF:1 *1
Tpw2
Tend
Tn1
Tn2
BCLK
Byte strobe mode
tAD
tAD
tAD
tAD
tAD
tAD
tAD
tAD
A23 to A0
1-write strobe mode
A23 to A1
tBCD
tBCD
tCSD
tCSD
BC3# to BC0#
Common to both byte strobe mode
and 1-write strobe mode
CS7# to CS0#
tWRD
tWRD
tWRD
tWRD
tWRD
tWRD
WR3# to WR0#, WR# (Write)
tWDD
tWDH
tWDD
tWDH
tWDD
tWDH
D31 to D0 (Write)
Note 1. Be sure to specify WDON and WDOFF as at least one cycle of BCLK.
Figure 2.23
External Bus Timing/Page Write Cycle (Bus Clock Synchronized)
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RX72M Group
2. Electrical Characteristics
CSRWAIT:3
CSWWAIT:3
TW1
TW2
TW3
(Tend)
Tend
Tn1
Tn2
BCLK
A23 to A0
CS7# to CS0#
RD# (Read)
WR# (Write)
External wait
tWTS tWTH
tWTS tWTH
WAIT#
Figure 2.24
External Bus Timing/External Wait Control
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RX72M Group
2. Electrical Characteristics
SDRAM command
ACT
RD
PRA
SDCLK pin
tAD2
tAD2
Row
address
A18 to A0
tAD2
tAD2
tAD2
tAD2
tAD2
Column address
tAD2
AP*1
PRA
command
tCSD2
tCSD2
tRASD
tRASD
tCSD2
tCSD2
tCSD2
tCSD2
tRASD
tRASD
tWED
tWED
SDCS#
RAS#
tCASD
tCASD
CAS#
WE#
(High)
CKE
tDQMD
DQMn
tRDS2
tRDH2
D31 to D0
Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.
Figure 2.25
SDRAM Space Single Read Bus Timing
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RX72M Group
2. Electrical Characteristics
SDRAM command
ACT
WR
PRA
SDCLK pin
tAD2
tAD2
Row
address
A18 to A0
tAD2
tAD2
tAD2
tAD2
tAD2
Column address
tAD2
AP*1
PRA
command
tCSD2
tCSD2
tRASD
tRASD
tCSD2
tCSD2
tCSD2
tCSD2
tRASD
tRASD
tWED
tWED
SDCS#
RAS#
tCASD
tCASD
tWED
tWED
CAS#
WE#
(High)
CKE
tDQMD
DQMn
tWDD2
tWDH2
D31 to D0
Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.
Figure 2.26
SDRAM Space Single Write Bus Timing
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RX72M Group
2. Electrical Characteristics
ACT
RD
RD
RD
RD PRA
SDCLK pin
tAD2 tAD2
tAD2 tAD2
A18 to A0
Row
address
C0
(column address)
C1
C2
tAD2 tAD2 tAD2
tAD2
C3
tAD2 tAD2
tAD2 tAD2
AP*1
tAD2
PRA
command
tCSD2 tCSD2 tCSD2
tCSD2
tCSD2
tRASD tRASD
tRASD
tCASD
tCASD
SDCS#
tRASD tRASD
RAS#
tCASD
CAS#
tWED tWED
WE#
(High)
CKE
tDQMD
tDQMD
DQMn
tRDS2 tRDH2
tRDS2 tRDH2
D31 to D0
Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.
Figure 2.27
SDRAM Space Multiple Read Bus Timing
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RX72M Group
2. Electrical Characteristics
WR WR WR WR PRA
ACT
SDCLK pin
tAD2
A18 to A0
Row
address
tAD2
tAD2 tAD2
tAD2
C0
(column address)
C1
C2
tAD2
tAD2
tAD2 tAD2
C3
tAD2
AP*1
tAD2
tAD2 tAD2
PRA
command
tCSD2 tCSD2 tCSD2
tCSD2 tCSD2
SDCS#
tRASD tRASD
tRASD tRASD tRASD
RAS#
tCASD
tCASD
tCASD
CAS#
tWED
tWED
WE#
(High)
CKE
tDQMD
tDQMD
DQMn
tWDD2 tWDH2
tWDD2 tWDH2
D31 to D0
Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.
Figure 2.28
SDRAM Space Multiple Write Bus Timing
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RX72M Group
2. Electrical Characteristics
SDRAM command
ACT
RD
RD
RD
RD
t AD2
t AD2
t AD2
PRA
ACT
RD
RD
RD
RD
PRA
SDCLK pin
t AD2
A18 to A0
t AD2
Row
address
t AD2
C0
(column address 0)
C1
C2
t AD2
t AD2
C3
t AD2
t AD2
t AD2
t AD2
t AD2
C4
R1
t AD2
AP*1
t AD2
t AD2
C5
t AD2
C6
t AD2
C7
t AD2
t AD2
PRA
command
t CSD2 t CSD2 t CSD2
t CSD2 t CSD2 t CSD2
t AD2
t AD2
PRA
command
t CSD2
t CSD2
SDCS#
t RASD t RASD
t RASD t RASD t RASD t RASD
t RASD t RASD
RAS#
t CASD
t CASD
t CASD
t CASD
CAS#
t WED
t WED
t WED
t WED
WE#
(High)
CKE
tDQMD
DQMn
t RDS2 t RDH2
t RDS2 t RDH2
t RDS2 t RDH2
t RDS2 t RDH2
D31 to D0
Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.
Figure 2.29
SDRAM Space Multiple Read Line Stride Bus Timing
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RX72M Group
2. Electrical Characteristics
MRS
SDRAM command
SDCLK pin
t AD2
t AD2
t AD2
t AD2
t CSD2
t CSD2
t RASD
t RASD
t CASD
t CASD
t WED
t WED
A18 to A0
AP*1
SDCS#
RAS#
CAS#
WE#
(High)
CKE
DQMn
(Hi-Z)
D31 to D0
Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.
Figure 2.30
SDRAM Space Mode Register Set Bus Timing
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RX72M Group
2. Electrical Characteristics
SDRAM command
Ts
(RFA)
(RFS)
(RFX)
(RFA)
SDCLK pin
t AD2
t AD2
t AD2
t AD2
A18 to A0
AP*1
t CSD2 t CSD2
t CSD2
t CSD2
t CSD2 t CSD2 t CSD2
t RASD t RASD
t RASD
t RASD
t RASD t RASD t RASD
t CASD t CASD
t CASD
t CASD
t CASD t CASD t CASD
SDCS#
RAS#
CAS#
(High)
WE#
t CKED
t CKED
CKE
t DQMD
t DQMD
DQMn
(Hi-Z)
D31 to D0
Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM.
Figure 2.31
SDRAM Space Self-Refresh Bus Timing
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RX72M Group
2.4.6
Table 2.27
2. Electrical Characteristics
EXDMAC Timing
EXDMAC Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
ICLK = 8 to 240 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, BCLK = SDCLK = 8 to 80 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
EXDMAC
Symbol
Min.
Max.
Unit
EDREQ setup time
tEDRQS
13
—
ns
EDREQ hold time
tEDRQH
2
—
ns
EDACK delay time
tEDACD
—
13
ns
Test Conditions
Figure 2.32
Figure 2.33,
Figure 2.34
BCLK pin
tEDRQS tEDRQH
EDREQ0,
EDREQ1
Figure 2.32
EDREQ0 and EDREQ1 Input Timing
BCLK pin
tEDACD
tEDACD
EDACK0,
EDACK1
Figure 2.33
EDACK0 and EDACK1 Single-Address Transfer Timing (for a CS Area)
BCLK pin
tEDACD
tEDACD
EDACK0,
EDACK1
Figure 2.34
EDACK0 and EDACK1 Single-Address Transfer Timing (for SDRAM)
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RX72M Group
2.4.7
2.4.7.1
Table 2.28
2. Electrical Characteristics
Timing of On-Chip Peripheral Modules
I/O Port
I/O Port Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
I/O ports
Input data pulse width
Symbol
Min.
Max.
Unit*1
tPRW
1.5
—
tPBcyc
Test Conditions
Figure 2.35
Note 1. tPBcyc: PCLKB cycle
PCLKB
Port
tPRW
Figure 2.35
I/O Port Input Timing
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2. Electrical Characteristics
2.4.7.2
TPU
Table 2.29
TPU Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
TPU
Input capture input pulse
width
Timer clock pulse width
Symbol
Single-edge setting
tTICW
Both-edge setting
Single-edge setting
Both-edge setting
Phase counting mode
tTCKWH,
tTCKWL
Min.
Max.
Unit*1
Test
Conditions
tPBcyc
Figure 2.36
tPBcyc
Figure 2.37
1.5
—
2.5
—
1.5
—
2.5
—
2.5
—
Note 1. tPBcyc: PCLKB cycle
PCLKB
Input capture
input
Figure 2.36
tTICW
TPU Input Capture Input Timing
PCLKB
TCLKA to
TCLKD
tTCKWL
Figure 2.37
tTCKWH
TPU Clock Input Timing
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2. Electrical Characteristics
2.4.7.3
TMR
Table 2.30
TMR Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
TMR
Timer clock pulse width
Single-edge setting
Both-edge setting
Max.
Unit*1
Test
Conditions
1.5
—
tPBcyc
Figure 2.38
2.5
—
Symbol
Min.
tTMCWH,
tTMCWL
Note 1. tPBcyc: PCLKB cycle
PCLKB
TMCI0 to TMCI3
tTMCWL
Figure 2.38
TMR Clock Input Timing
2.4.7.4
CMTW
Table 2.31
tTMCWH
CMTW Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
CMTW
Input capture input pulse
width
Single-edge setting
Both-edge setting
Symbol
Min.
Max.
Unit*1
Test
Conditions
tCMTWTICW
1.5
—
tPBcyc
Figure 2.39
2.5
—
Note 1. tPBcyc: PCLKB cycle
PCLKB
Input capture
input
Figure 2.39
tCMTWICW
CMTW Input Capture Input Timing
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2. Electrical Characteristics
2.4.7.5
MTU
Table 2.32
MTU Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
MTU
Input capture input pulse
width
Timer clock pulse width
Symbol
Single-edge setting
tMTICW
Both-edge setting
Single-edge setting
Both-edge setting
Phase counting mode
tMTCKWH,
tMTCKWL
Min.
Max.
Unit*1
Test
Conditions
tPAcyc
Figure 2.40
tPAcyc
Figure 2.41
1.5
—
2.5
—
1.5
—
2.5
—
2.5
—
Note 1. tPAcyc: PCLKA cycle
PCLKA
Input capture
input
Figure 2.40
tMTICW
MTU Input Capture Input Timing
PCLKA
MTCLKA to
MTCLKD,
MTIOC1A
tMTCKWL
Figure 2.41
tMTCKWH
MTU Clock Input Timing
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RX72M Group
2.4.7.6
Table 2.33
2. Electrical Characteristics
POE
POE Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
POE
Symbol
Min. Typ.
Unit*1
Max.
Test Conditions
POEn# input pulse width
(n = 0, 4, 8, 10, 11)
tPOEW
1.5
—
—
Output
disable time
Transition of the POEn#
signal level
tPOEDI
—
—
5 PCLKB + 0.24
µs
Figure 2.43
When detecting falling edges
(ICSRm.POEnM[3:0] = 0000
(m = 1 to 5; n = 0, 4, 8, 10, 11))
Simultaneous conduction
of output pins
tPOEDO
—
—
3 PCLKB + 0.2
µs
Figure 2.44
Register setting
tPOEDS
—
—
1 PCLKB + 0.2
µs
Figure 2.45
Time for access to the register
is not included.
tPOEDOS
—
—
21
µs
Figure 2.46
Oscillation stop detection
tPBcyc Figure 2.42
Note 1. tPBcyc: PCLKB cycle
PCLKB
POEn# input
(n = 0, 4, 8, 10, 11)
tPOEW
Figure 2.42
POE# Input Timing
POEn# input
(n = 0, 4, 8, 10, 11)
tPOEW
Outputs disabled
MTU PWM output pins
tPOEDI
Figure 2.43
Output Disable Time for POE in Response to Transition of the POEn# Signal Level
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2. Electrical Characteristics
Simultaneous active-level outputs detected*1
Outputs
disabled
MTU PWM output pins
tPOEDO
Note 1.
Figure 2.44
When the active level is set to low.
Output Disable Time for POE in Response to the Simultaneous Conduction of Output Pins
Corresponding bit in
the SPOER register
Outputs disabled
MTU PWM output pins
tPOEDS
Figure 2.45
Output Disable Time for POE in Response to the Register Setting
Main clock
Oscillation stop detection
signal (internal signal)
Outputs disabled
MTU PWM output pins
tPOEDOS
Figure 2.46
Output Disable Time for POE in Response to the Oscillation Stop Detection
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RX72M Group
2.4.7.7
2. Electrical Characteristics
POEG
Table 2.34
POEG Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
POEG
Min. Typ.
GTETRGn input pulse width (n = A to D)
tPOEGW
1.5
—
—
Output
disable time
Input level detection of the
GTETRGn pin (via flag)
tPOEGDI
—
—
3 PCLKB + 0.34
µs
Figure 2.48
When the digital noise filter is
not in use (POEGGn.NFEN = 0
(n = A to D))
Detection of the output
stopping signal from
GPTW (deadtime error,
simultaneous high output,
or simultaneous low
output)
tPOEGDE
—
—
0.5
µs
Figure 2.49
Register setting
tPOEGDS
—
—
1 PCLKB + 0.3
µs
Figure 2.50
Time for access to the register
is not included.
tPOEGDOS
—
—
21
µs
Figure 2.51
Oscillation stop detection
Max.
Unit*1
Symbol
Test Conditions
tPBcyc Figure 2.47
Note 1. tPBcyc: PCLKB cycle
PCLKB
GTETRGn input
(n = A to D)
tPOEGW
Figure 2.47
POEG Input Timing
GTETRGn input
(n = A to D)
tPOEGW
POEGGn.PIDF flag
(n = A to D)
Outputs disabled
GPTW PWM output pins
tPOEGDI
Figure 2.48
Output Disable Time for POEG via Detection Flag in Response to the Input Level Detection of the
GTETRGn pin
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2. Electrical Characteristics
Output stopping signal
from GPTW*1
Outputs disabled
GPTW PWM output pins
tPOEGDE
Note 1.
Figure 2.49
GPTWn.GTST.DTEF (dead time error flag), GPTWn.GTST.OABLF (simultaneous low output flag),
or GPTWn.GTST.OABHF (simultaneous high output flag)
Output Disable Time for POEG in Response to Detection of the Output Stopping Signal from
GPTW
POEGGn.SSF bit
(n = A to D)
Outputs disabled
GPTW PWM output pins
tPOEGDS
Figure 2.50
Output Disable Time for POEG in Response to the Register Setting
Main clock
Oscillation stop detection
signal (internal signal)
Outputs disabled
GPTW PWM output pins
tPOEGDOS
Figure 2.51
Output Disable Time of POEG in Response to the Oscillation Stop Detection
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2. Electrical Characteristics
2.4.7.8
GPTW
Table 2.35
GPTW Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
GPTW
Input capture input pulse width
Symbol
Single-edge setting
tGTICW
Both-edge setting
External trigger input pulse width Single-edge setting
Both-edge setting
tGTEW
Min.
Test
Conditions
Max.
Unit*1, *2
tPAcyc
Figure 2.52
tPBcyc
Figure 2.53
1.5
—
2.5
—
1.5
—
2.5
—
Note 1. tPAcyc: PCLKA cycle
Note 2. tPBcyc: PCLKB cycle
PCLKA
Input capture
input
Figure 2.52
tGTICW
GPTW Input Capture Input Timing
PCLKB
GTETRGn input
(n = A to D)
tGTEW
Figure 2.53
GPTW External Trigger Input Timing
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RX72M Group
2.4.7.9
Table 2.36
2. Electrical Characteristics
SCI
SCI Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
SCIh, SCIj
Input clock cycle
Symbol
Asynchronous
tScyc
Clock
synchronous
Max.
Unit*1
Test
Conditions
tPBcyc
Figure 2.54
4
—
6
—
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
—
5
ns
tSCKf
—
5
ns
tPBcyc
Input clock fall time
Output clock cycle
Asynchronous*2
tScyc
Clock
synchronous
8
—
4
—
Output clock pulse width
tSCKW
0.4
0.6
tScyc
Output clock rise time
tSCKr
—
5
ns
Output clock fall time
SCIi
Min.
tSCKf
—
5
ns
Transmit data delay time
Clock
synchronous
tTXD
—
28
ns
Receive data setup time
Clock
synchronous
tRXS
15
—
ns
Receive data hold time
Clock
synchronous
tRXH
5
—
ns
Asynchronous
tScyc
tPAcyc
Input clock cycle
Clock
synchronous
4
—
12
—
Figure 2.55
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
—
5
ns
tSCKf
—
5
ns
tScyc
8
—
tPAcyc
8
—
Input clock fall time
Output clock cycle
Asynchronous*2
Clock
synchronous
Output clock pulse width
tSCKW
0.4
0.6
tScyc
Output clock rise time
tSCKr
—
5
ns
tSCKf
—
5
ns
tTXD
—
15
ns
—
28
Output clock fall time
Transmit data delay time
Master
Slave
Receive data setup time
Clock
synchronous
tRXS
20
—
Receive data hold time
Clock
synchronous
tRXH
5
—
Figure 2.54
Figure 2.55
ns
Note 1. tPBcyc: PCLKB cycle; tPAcyc: PCLKA cycle
Note 2. When the SEMR.ABCS and SEMR.BGDM bits are set to 1
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2. Electrical Characteristics
tSCKW
tSCKr
tSCKf
SCKn
(n = 0 to 12)
tScyc
Figure 2.54
SCK Clock Input Timing
SCKn
tTXD
TXDn
tRXS tRXH
RXDn
(n = 0 to 12)
Figure 2.55
SCI Input/Output Timing: Clock Synchronous Mode
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RX72M Group
Table 2.37
2. Electrical Characteristics
Simple IIC Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
High-drive output is selected by the drive capacity control register.
Simple IIC
(Standard-mode)
Simple IIC
(Fast-mode)
Item
Symbol
Min.
Max.
Unit
Test
Conditions
SSDA input rise time
tSr
—
1000
ns
Figure 2.56
SSDA input fall time
tSf
—
300
ns
SSDA input spike pulse removal time
tSP
0
4 × tPBcyc
ns
Data input setup time
tSDAS
250
—
ns
Data input hold time
tSDAH
0
—
ns
SSCL, SSDA capacitive load
Cb * 1
—
400
pF
SSCL, SSDA input rise time
tSr
—
300
ns
SSCL, SSDA input fall time
tSf
—
300
ns
SSCL, SSDA input spike pulse removal
time
tSP
0
4 × tPBcyc
ns
Data input setup time
tSDAS
100
—
ns
Data input hold time
tSDAH
0
—
ns
*1
—
400
pF
SSCL, SSDA capacitive load
Cb
Note:
tPBcyc: PCLKB cycle
Note 1. Cb is the total capacitance of the bus lines.
VIH
SSDA0 to SSDA12
VIL
tBUF
tSCLH
tSTAH
tSTAS
tSTOS
tSP
SSCL0 to SSCL12
P*1
S*1
tSf
tSCLL
tSr
tSCL
tSDAS
tSDAH
Note 1. S, P, and Sr indicate the following conditions.
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.56
P*1
Sr*1
Test conditions
VIH = 0.7 × VCC, VIL = 0.3 × VCC
VOL = 0.6 V, IOL = 6 mA
Simple IIC Bus Interface Input/Output Timing
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RX72M Group
Table 2.38
2. Electrical Characteristics
Simple SPI Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Simple
SPI
Item
Symbol
SCK clock cycle output (master)
tSPcyc
Min.
Unit*1
tPAcyc
4
65536
8
65536
tSPCKWH
0.4
0.6
tSPcyc
SCK clock cycle input (slave)
SCK clock high pulse width
Max.
SCK clock low pulse width
tSPCKWL
0.4
0.6
tSPcyc
tSPCKr, tSPCKf
—
20
ns
tSU
33.3
—
ns
Data input hold time
tH
33.3
—
ns
SS input setup time
tLEAD
1
—
tSPcyc
SS input hold time
tLAG
1
—
tSPcyc
Data output delay time
tOD
—
33.3
ns
Data output hold time
tOH
–10
—
ns
tDr, tDf
—
16.6
ns
SCK clock rise/fall time
Data input setup time
Data rise/fall time
tSSLr, tSSLf
—
16.6
ns
Slave access time
tSA
—
5
tPBcyc
Slave output release time
tREL
—
5
tPBcyc
SS input rise/fall time
Test
Conditions
Figure 2.57
Figure 2.58 to
Figure 2.61
Figure 2.60,
Figure 2.61
Note 1. tPAcyc: PCLKA cycle, tPBcyc: PCLKB cycle
tSPCKr
tSPCKWH
SCKn
master select
output
VOH
VOH
VOL
tSPCKf
VOH
VOH
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
VIH
SCKn
slave select input
VIH
VIL
(n = 0 to 12)
tSPCKf
VIH
VIL
tSPCKWL
VIH
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Figure 2.57
Simple SPI Clock Timing
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RX72M Group
2. Electrical Characteristics
tTD
SSn#
output
tLEAD
tLAG
tSSLr, tSSLf
SCKn
CKPOL = 0
output
SCKn
CKPOL = 1
output
tSU
SMISOn
input
tH
MSB IN
DATA
tDr, tDf
SMOSIn
output
LSB IN
tOH
MSB OUT
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
(n = 0 to 12)
Figure 2.58
Simple SPI Timing (Master, CKPH = 1)
tTD
SSn#
output
tLEAD
tLAG
tSSLr, tSSLf
SCKn
CKPOL = 1
output
SCKn
CKPOL = 0
output
tSU
SMISOn
input
tH
MSB IN
tOH
SMOSIn
output
DATA
LSB IN
tOD
MSB OUT
MSB IN
tDr, tDf
DATA
LSB OUT
IDLE
MSB OUT
(n = 0 to 12)
Figure 2.59
Simple SPI Timing (Master, CKPH = 0)
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RX72M Group
2. Electrical Characteristics
tTD
SSn#
input
tLEAD
tLAG
SCKn
CKPOL = 0
input
SCKn
CKPOL = 1
input
tSA
tOH
SMISOn
output
tOD
MSB OUT
tSU
SMOSIn
input
tREL
DATA
LSB OUT
tH
Invaild DATA
MSB OUT
tDr, tDf
MSB IN
DATA
LSB IN
MSB IN
(n = 0 to 12)
Figure 2.60
Simple SPI Timing (Slave, CKPH = 1)
tTD
SSn#
input
tLEAD
tLAG
SCKn
CKPOL = 1
input
SCKn
CKPOL = 0
input
tSA
SMISOn
output
tOH
tOD
Invaild DATA
MSB OUT
tSU
SMOSIn
input
tREL
DATA
tH
MSB IN
LSB OUT
MSB OUT
tDr, tDf
DATA
LSB IN
MSB IN
(n = 0 to 12)
Figure 2.61
Simple SPI Timing (Slave, CKPH = 0)
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RX72M Group
2.4.7.10
Table 2.39
2. Electrical Characteristics
RIIC
RIIC Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
High-drive output is selected by the drive capacity control register.
Item
Symbol
Min.*1
Max.
Unit
Test
Conditions
Figure 2.62
tSCL
6(12) × tIICcyc + 1300
—
ns
tSCLH
3(6) × tIICcyc + 300
—
ns
tSCLL
3(6) × tIICcyc + 300
—
ns
SCL, SDA input rise time
tSr
—
1000
ns
SCL, SDA input fall time
tSf
—
300
ns
RIIC
SCL input cycle time
(Standard-mode,
SCL input high pulse width
SMBus)
ICFER.FMPE = 0 SCL input low pulse width
SCL, SDA input spike pulse removal time
tSP
0
1(4) × tIICcyc
ns
SDA input bus free time
tBUF
3(6) × tIICcyc + 300
—
ns
Start condition input hold time
tSTAH
tIICcyc + 300
—
ns
Restart condition input setup time
tSTAS
1000
—
ns
Stop condition input setup time
tSTOS
1000
—
ns
Data input setup time
tSDAS
tIICcyc + 50
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
C b* 2
—
400
pF
tSCL
6(12) × tIICcyc + 600
—
ns
tSCLH
3(6) × tIICcyc + 300
—
ns
RIIC
SCL input cycle time
(Fast-mode)
SCL input high pulse width
ICFER.FMPE = 0
SCL input low pulse width
tSCLL
3(6) × tIICcyc + 300
—
ns
SCL, SDA input rise time
tSr
20 × (External pull-up
voltage/5.5V)
300
ns
SCL, SDA input fall time
tSf
20 × (External pull-up
voltage/5.5V)
300
ns
SCL, SDA input spike pulse removal time
tSP
0
1(4) × tIICcyc
ns
SDA input bus free time
tBUF
3(6) × tIICcyc + 300
—
ns
Start condition input hold time
tSTAH
tIICcyc + 300
—
ns
Restart condition input setup time
tSTAS
300
—
ns
Stop condition input setup time
tSTOS
300
—
ns
Data input setup time
tSDAS
tIICcyc + 50
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
C b* 2
—
400
pF
tSCL
6(12) × tIICcyc + 240
—
ns
tSCLH
3(6) × tIICcyc + 120
—
ns
tSCLL
3(6) × tIICcyc + 120
—
ns
tSr
—
120
ns
SCL, SDA input fall time
tSf
—
120
ns
SCL, SDA input spike pulse removal time
tSP
0
1(4) × tIICcyc
ns
SDA input bus free time
tBUF
3(6) × tIICcyc + 120
—
ns
Start condition input hold time
tSTAH
tIICcyc + 120
—
ns
Restart condition input setup time
tSTAS
120
—
ns
Stop condition input setup time
tSTOS
120
—
ns
RIIC
SCL input cycle time
(Fast-mode+)
SCL input high pulse width
ICFER.FMPE = 1
SCL input low pulse width
SCL, SDA input rise time
Data input setup time
tSDAS
tIICcyc + 20
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
C b* 2
—
550
pF
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2. Electrical Characteristics
Note:
tIICcyc: RIIC internal reference clock (IICφ) cycle
Note 1. The value within parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 11b while the digital filter is enabled by
the setting ICFER.NFE = 1.
Note 2. Cb is the total capacitance of the bus lines.
VIH
SDA0 to SDA2
VIL
tBUF
tSCLH
tSTAH
tSTAS
tSTOS
tSP
SCL0 to SCL2
P*1
S*1
tSf
tSCLL
tSr
tSCL
tSDAS
tSDAH
Note 1. S, P, and Sr indicate the following conditions.
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.62
P*1
Sr*1
Test conditions
VIH = 0.7 × VCC, VIL = 0.3 × VCC
VOL = 0.6 V, IOL = 6 mA (ICFER.FMPE = 0)
VOL = 0.4 V, IOL = 15 mA (ICFER.FMPE = 1)
RIIC Bus Interface Input/Output Timing
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RX72M Group
2.4.7.11
Table 2.40
2. Electrical Characteristics
RSPI
RSPI Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
RSPI
RSPCK clock cycle
Symbol
Master
tSPcyc
Slave
RSPCK clock high pulse
width
Master
tSPCKWH
Slave
RSPCK clock low pulse
width
Master
tSPCKWL
Slave
RSPCK clock rise/fall time
Output
Data input setup time
Master
Data input hold time
Master
Input
Master
Master
Master
Master
SSL
rise/fall time
Output
(tSPcyc – tSPCKr
– tSPCKf) / 2
—
(tSPcyc – tSPCKr
– tSPCKf) / 2 – 3
—
(tSPcyc – tSPCKr
– tSPCKf) / 2
—
—
5
ns
8.3
—
tHF
0
—
PCLKA division ratio set to
a value other
than 1/2
tH
tPAcyc
—
8.3
—
tLEAD
tLAG
tOD
1
8
tSPcyc
—
tPAcyc
1
8
tSPcyc
6
—
tPAcyc
ns
—
6.3
28
tOH
0
—
0
—
tTD
tSPcyc + 2 × tPAcyc
8 × tSPcyc
+ 2 × tPAcyc
6 × tPAcyc
—
tDr, tDf
Input
Figure 2.64 to
Figure 2.69
ns
6
—
Figure 2.63
ns
ns
PCLKA division ratio set to
1/2
Test
Conditions*2
ns
µs
Slave
MOSI and MISO
rise/fall time
—
1
Slave
Successive transmission
delay time
(tSPcyc – tSPCKr
– tSPCKf) / 2 – 3
—
Slave
Data output hold time
—
—
6
Slave
Data output delay time
tPAcyc
2
4
—
Slave
SSL hold time
Unit*1
tSU
Slave
Master
Max.*1
tSPCKr,
tSPCKf
Slave
SSL setup time
Min.*1
ns
ns
—
5
ns
—
1
µs
5
ns
Output
tSSLr,
—
Input
tSSLf
—
1
µs
Slave access time
tSA
—
2 × tPAcyc
+ 28
ns
Slave output release time
tREL
—
2 × tPAcyc
+ 28
ns
Figure 2.68,
Figure 2.69
Note 1. tPAcyc: PCLKA cycle
Note 2. We recommend using pins that have a letter (“-A”, “-B”, etc.) to indicate group membership appended to their names as groups.
For the RSPI interface, the AC portion of the electrical characteristics is measured for each group.
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RX72M Group
2. Electrical Characteristics
tSPCKr
tSPCKWH
VOH
RSPCKA
master select
output
VOH
VOL
tSPCKf
VOH
VOH
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
VIH
VIH
RSPCKA
slave select input
VIL
tSPCKf
VIH
VIL
tSPCKWL
VIH
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Figure 2.63
RSPI Clock Timing
tTD
SSLA0 to
SSLA3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
tSU
MISOA
input
tH
MSB IN
tDr, tDf
MOSIA
output
Figure 2.64
DATA
tOH
MSB OUT
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKA Division Ratio Set to a Value Other Than 1/2)
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RX72M Group
2. Electrical Characteristics
tTD
SSLA0 to
SSLA3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
tSU
MISOA
input
tHF
MSB IN
DATA
tDr, tDf
MOSIA
output
Figure 2.65
tHF
tOH
MSB OUT
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKA Division Ratio Set to 1/2)
tTD
SSLA0 to
SSLA3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
tSU
MISOA
input
tH
MSB IN
tOH
MOSIA
output
Figure 2.66
DATA
LSB IN
tOD
MSB OUT
MSB IN
tDr, tDf
DATA
LSB OUT
IDLE
MSB OUT
RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKA Division Ratio Set to a Value Other Than 1/2)
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RX72M Group
2. Electrical Characteristics
tTD
SSLA0 to
SSLA3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
tSU
MISOA
input
tHF
MSB IN
tOH
DATA
LSB IN
tOD
MOSIA
output
Figure 2.67
tH
MSB IN
tDr, tDf
MSB OUT
DATA
LSB OUT
IDLE
MSB OUT
RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKA Division Ratio Set to 1/2)
tTD
SSLA0
input
tLEAD
tLAG
RSPCKA
CPOL = 0
input
RSPCKA
CPOL = 1
input
tSA
tOH
MISOA
output
MSB OUT
tSU
MOSIA
input
Figure 2.68
tOD
DATA
tREL
LSB OUT
tH
MSB IN
Invaild DATA
MSB OUT
tDr, tDf
DATA
LSB IN
MSB IN
RSPI Timing (Slave, CPHA = 0)
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2. Electrical Characteristics
tTD
SSLA0
input
tLEAD
tLAG
RSPCKA
CPOL = 0
input
RSPCKA
CPOL = 1
input
tSA
MISOA
output
tOH
tOD
Invaild DATA
MSB OUT
tSU
MOSIA
input
Figure 2.69
tREL
tH
MSB IN
LSB OUT
DATA
MSB OUT
tDr, tDf
DATA
LSB IN
MSB IN
RSPI Timing (Slave, CPHA = 1)
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RX72M Group
2.4.7.12
Table 2.41
2. Electrical Characteristics
QSPI
QSPI Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
QSPI
Symbol
Min.
Max.
Unit*1
Test
Conditions*2
QSPCLK clock cycle
tQScyc
2
4080
tPBcyc
Figure 2.70
Data input setup time
tSu
6.5
—
ns
Data input hold time
tIH
5
—
ns
Figure 2.71,
Figure 2.72
SS setup time
tLEAD
1.5
8.5
tQScyc
SS hold time
tLAG
1
8
tQScyc
Data output delay time
tOD
—
10.0
ns
Data output hold time
tOH
–5
—
ns
Successive transmission delay time
tTD
1
8
tQScyc
Note 1. tPBcyc: PCLKB cycle
Note 2. We recommend using pins that have a letter (“-A”, “-B”, etc.) to indicate group membership appended to their names as groups.
For the QSPI interface, the AC portion of the electrical characteristics is measured for each group.
QSPCLK
output
tQScyc
Figure 2.70
QSPI Clock Timing
tTD
QSSL
output
QSPCLK
CPOL = 0
output
tLEAD
QSPCLK
CPOL = 1
output
QMI,
QIO0 to QIO3
input
QMO,
QIO0 to QIO3
output
Figure 2.71
tLAG
tSU
tIH
MSB IN
DATA
tOH
MSB OUT
LSB IN
tOD
DATA
LSB OUT
IDLE
Transmit/Receive Timing (CPHA = 0)
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RX72M Group
2. Electrical Characteristics
tTD
QSSL
output
QSPCLK
CPOL = 0
output
tLEAD
tLAG
QSPCLK
CPOL = 1
output
tSU
QMI,
QIO0 to QIO3
input
tIH
MSB IN
tOH
QMO,
QIO0 to QIO3
output
Figure 2.72
DATA
LSB IN
tOD
MSB OUT
DATA
LSB OUT
IDLE
Transmit/Receive Timing (CPHA = 1)
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RX72M Group
2.4.7.13
Table 2.42
2. Electrical Characteristics
SSIE
Expansion Serial Sound Interface Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
AUDIO_CLK
Symbol
Cycle
Unit
tEXcyc
20
—
ns
0.4
0.6
tEXcyc
Master
tO
80
—
ns
Slave
tI
80
—
ns
Master
tHC
0.35
—
tO
tLC
0.35
—
tO
tHC
0.35
—
tI
tLC
0.35
—
tI
Master
tRC
—
0.15
tO
tFC
—
0.15
tO
Slave
tRC
—
0.15
tI
tFC
—
0.15
tI
Input setup time
Master
tSR
12
—
ns
Input hold time
Master
Cycle
Output clock high level
Output clock low level
Input clock high level
Slave
Input clock low level
Output clock rise time
Output clock fall time
Input clock rise time
Input clock fall time
SSILRCKn,SSITXD0,
SSIRXD0, SSIDATA1
Max.
tEXL/tEXH
High/low level
SSIBCKn
Min.
Slave
12
—
ns
tHR
8
—
ns
15
—
ns
tDTR
–10
5
ns
0
20
ns
tDTRW
—
20
ns
Slave
Output delay time
Master
Slave
Slave
Output delay time from when an
SSILRCK0 signal is changed*1
Test
Conditions
Figure 2.73
Figure 2.74
Figure 2.75,
Figure 2.76
Figure 2.77
n = 0, 1
Note 1. The SSIE has a single path for transmission in slave mode. To generate the data for transmission, the signals input through the
SSILRCKn pin through the abovementioned path are used. After that, the data for transmission proceed to be used as the
logical outputs to the SSITXD0 or SSIDATA1 pin.
tEXcyc
tEXH
tEXL
AUDIO_CLK
(input)
1/2 VCC
tEXf
Figure 2.73
tEXr
Clock Input Timing
tHC
tRC
tFC
tLC
SSIBCKn
tI, tO
(n = 0, 1)
Figure 2.74
SSIE Clock Input/Output Timing
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RX72M Group
2. Electrical Characteristics
SSIBCKn
(input or output)
SSILRCKn (input),
SSIRXD0, SSIDATA1 (input)
tSR
tHR
SSILRCKn (output),
SSITXD0, SSIDATA1 (output)
(n = 0, 1)
Figure 2.75
tDTR
Transmission and Reception Timing for the SSIE Data When the SSICR.BCKP Bit is 0
SSIBCKn
(input or output)
SSILRCKn (input),
SSIRXD0, SSIDATA1 (input)
tSR
tHR
SSILRCKn (output),
SSITXD0, SSIDATA1 (output)
(n = 0, 1)
Figure 2.76
tDTR
Transmission and Reception Timing for the SSIE Data When the SSICR.BCKP Bit is 1
SSILRCKn (input)
SSITXD0, SSIDATA1 (output)
(n = 0, 1)
tDTRW
MSB bit output timing in slave transmission from SSILRCKn with the settings
of DEL = 1, SDTA = 0, or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0]
Figure 2.77
Output Delay of the SSIE Data from When an SSILRCKn Signal is Changed
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RX72M Group
2.4.7.14
2. Electrical Characteristics
PMGI
Table 2.43
PMGI Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
ICLK = PCLKA = 8 to 120 MHz, PCLKB = BCLK = SDCLK = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
PMGI
PMGIn_MDC output cycle
Symbol
Min.
Max.
Unit
tMDC
80
—
ns
PMGIn_MDIO setup time (relative to PMGIn_MDC↑)
tSMDIO
20
—
ns
PMGIn_MDIO hold time (relative to PMGIn_MDC↑)
tHMDIO
0
—
ns
PMGIn_MDIO output delay time (relative to PMGIn_MDC↑)
tDMDIO
0
20
ns
Test
Conditions
Figure 2.78
n = 0, 1
tMDC
PMGIn_MDC
(output)
tSMDIO
tHMDIO
PMGIn_MDIO
PMGIn_MDIO
(input)
(input)
tDMDIO
tDMDIO
PMGIn_MDIO
PMGIn_MDIO
(output)
(output)
(n = 0, 1)
Figure 2.78
Timing of Serial Management Access
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RX72M Group
2.4.7.15
Table 2.44
2. Electrical Characteristics
MMC
MMC Host Interface Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
MMCIF MMC_CLK clock cycle
Symbol
Min.*1
Max.
Unit
Test
Conditions*2
Figure 2.79
tMMCPP
2 × tPBcyc
—
ns
MMC_CLK clock high level width
tMMCWH
6.5
—
ns
MMC_CLK clock low level width
tMMCWL
6.5
—
ns
MMC_CLK clock rising time
tMMCLH
—
3
ns
MMC_CLK clock falling time
tMMCHL
—
3
ns
MMC_CMD, MMC_D7 to MMC_D0 output data delay
(data transfer mode)
tMMCODLY
–6.6
6.6
ns
MMC_CMD, MMC_D7 to MMC_D0 input data setup
tMMCISU
8
—
ns
MMC_CMD, MMC_D7 to MMC_D0 input data hold
tMMCIH
2.5
—
ns
Note 1. tPBcyc: PCLKB cycle
Note 2. We recommend using pins that have a letter (“-A”, “-B”, etc.) to indicate group membership appended to their names as groups.
For the MMC interface, the AC portion of the electrical characteristics is measured for each group.
tMMCPP
tMMCWL
tMMCWH
MMC_CLK
tMMCHL
tMMCLH
tMMCISU
tMMCIH
MMC_CMD,
MMC_D7 to MMC_D0 input
MMC_CMD,
MMC_D7 to MMC_D0 output
tMMCODLY (max)
Figure 2.79
tMMCODLY (min)
MMC Interface
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RX72M Group
2.4.7.16
Table 2.45
2. Electrical Characteristics
SDHI
SDHI Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6V, 2.7V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30pF
High-drive output is selected by the drive capacity control register.
Item
SDHI
Symbol
Min.
Max.
Unit
Test
Conditions*1
Figure 2.80
SDHI_CLK output cycle time
tPP(SD)
20
—
ns
SDHI_CLK output width at high level
tWH(SD)
0.4 × tPP(SD)
—
ns
SDHI_CLK output width at low level
tWL(SD)
0.4 × tPP(SD)
—
ns
SDHI_CLK output rising time
tTLH(SD)
—
3
ns
SDHI_CLK output falling time
tTHL(SD)
—
3
ns
tODLY(SD)
–6.5
4
ns
SDHI_CMD, SDHI_D3 to SDHI_D0 input data setup time
tISU(SD)
6
—
ns
SDHI_CMD, SDHI_D3 to SDHI_D0 input data hold time
tIH(SD)
2
—
ns
SDHI_CMD, SDHI_D3 to SDHI_D0 output data delay (data
transfer mode)
Note 1. We recommend using pin names that have a letter (“-A”, “-B”, etc.) to indicate group membership per group in the test.
For the SDHI, the AC portion of the electrical characteristics is measured per group.
tPP(SD)
tWL(SD)
SDHI_CLK output
VIH
VIH
50% VCC
VIH
50% VCC
VL
tTHL(SD)
tWH(SD)
VL
VL
tTLH(SD)
tISU(SD) tIH(SD)
SDHI_CMD, SDHI_D3 to SDHI_D0 input
tODLY(SD)
tODLY(SD)
SDHI_CMD, SDHI_D3 to SDHI_D0 output
Figure 2.80
SD Host Interface Input/Output Signal Timing
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RX72M Group
2.4.7.17
2. Electrical Characteristics
ESC
Table 2.46
ESC Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
MII: High-drive output for the high-speed interface is selected in the drive capacity control register.
Item
ESC (MII)
ESC
(MDIO)
Symbol
Min.
Max.
Unit
CATn_TX_CLK cycle time
tTcyc
40
—
ns
CATn_TX_EN output delay time
tTENd
1
25
ns
CATn_ETXD0 to CATn_ETXD3 output delay time
tMTDd
1
25
ns
CATn_RX_CLK cycle time
tTRcyc
40
—
ns
CATn_RX_DV setup time
tRDVs
10
—
ns
CATn_RX_DV hold time
tRDVh
10
—
ns
CATn_ERXD0 to CATn_ERXD3 setup time
tMRDs
10
—
ns
CATn_ERXD0 to CATn_ERXD3 hold time
tMRDh
10
—
ns
CATn_RX_ER setup time
tRERs
10
—
ns
CATn_RX_ER hold time
tRERh
10
—
ns
CAT0_MDIO setup time (CAT0_MDC↑)
tSMDIO
60
—
ns
CAT0_MDIO hold time (CAT0_MDC↑)
tHMDIO
0
—
ns
CAT0_MDIO output delay time (CAT0_MDC↓)
tDMDIO
0
30
ns
Test
Conditions
—
Figure 2.81
—
Figure 2.82
Figure 2.83
Figure 2.84
n = 0, 1
CATn_TX_CLK
tTENd
CATn_TX_EN
tMTDd
Preamble
CATn_ETXD[3:0]
SFD
DATA
CRC
(n = 0, 1)
Figure 2.81
MII Transmission Timing (Normal Operation)
CATn_RX_CLK
tRDVs
tRDVh
CATn_RX_DV
tMRDh
tMRDs
CATn_ERXD[3:0]
Preamble
SFD
DATA
CRC
CATn_RX_ER
(n = 0, 1)
Figure 2.82
MII Reception Timing (Normal Operation)
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2. Electrical Characteristics
CATn_RX_CLK
CATn_RX_DV
CATn_ERXD[3:0]
Preamble
SFD
DATA
xxxx
tRERh
tRERs
CATn_RX_ER
(n = 0, 1)
Figure 2.83
MII Reception Timing (Error Occurrence)
CAT0_MDC
(output)
tSMDIO
tHMDIO
CAT0_MDIO
(input)
tDMDIO
tDMDIO
CAT0_MDIO
(output)
Figure 2.84
Timing of Serial Management Access
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RX72M Group
2.4.7.18
Table 2.47
2. Electrical Characteristics
ETHERC
ETHERC Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
RMII: High-drive output for the high-speed interface is selected in the drive capacity control register.
MII: High-drive output is selected by the drive capacity control register.
Item
ETHERC
(RMII)
Symbol
Min.
Max.
Unit
REF50CK cycle time
Tck
20
—
ns
REF50CK frequency Typ. 50 MHz
—
—
50 + 100 ppm
MHz
REF50CK duty
REF50CK rise/fall time
RMIIn_xxxx*1 output delay time
RMIIn_xxxx*2
ETHERC
(MII)
setup time
—
35
65
%
Tckr/ckf
0.5
3.5
ns
Tco
2.5
15.0
ns
Tsu
3
—
ns
RMIIn_xxxx*2 hold time
Thd
1
—
ns
RMIIn_xxxx*1, *2
Tr/Tf
—
5
ns
rise/fall time
ETn_WOL output delay time
tWOLd
1
23.5
ns
ETn_TX_CLK cycle time
tTcyc
40
—
ns
ETn_TX_EN output delay time
tTENd
1
20
ns
ETn_ETXD0 to ETn_ETXD3 output delay time
tMTDd
1
20
ns
ETn_CRS setup time
tCRSs
10
—
ns
ETn_CRS hold time
tCRSh
10
—
ns
ETn_COL setup time
tCOLs
10
—
ns
ETn_COL hold time
tCOLh
10
—
ns
ETn_RX_CLK cycle time
tTRcyc
40
—
ns
ETn_RX_DV setup time
tRDVs
10
—
ns
ETn_RX_DV hold time
tRDVh
10
—
ns
ETn_ERXD0 to ETn_ERXD3 setup time
tMRDs
10
—
ns
ETn_ERXD0 to ETn_ERXD3 hold time
tMRDh
10
—
ns
ETn_RX_ER setup time
tRERs
10
—
ns
ETn_RX_ER hold time
tRERh
10
—
ns
ETn_WOL output delay time
tWOLd
1
23.5
ns
Test
Conditions
Figure 2.85 to
Figure 2.88
Figure 2.89
—
Figure 2.90
Figure 2.91
—
Figure 2.92
Figure 2.93
Figure 2.94
n = 0, 1
Note 1. RMIIn_TXD_EN, RMIIn_TXD1, RMIIn_TXD0
Note 2. RMIIn_CRS_DV, RMIIn_RXD1, RMIIn_RXD0, RMIIn_RX_ER
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RX72M Group
2. Electrical Characteristics
Tck
90%
Tckr
REF50CK 50%
Tckf
10%
Tco
Tf
Tr
Tsu
Thd
70%
*11
RMIIn_xxxx*
RMII0_xxxx
50% Change in
Signal
signal level
Change in
signal level
Change in
signal level
Signal
30%
(n = 0, 1)
Note 1.
RMIIn_TXD_EN, RMIIn_TXD1, RMIIn_TXD0, RMIIn_CRS_DV, RMIIn_RXD1, RMIIn_RXD0, RMIIn_RX_ER
Figure 2.85
Timing with the REF50CK and RMII Signals
TCK
REF50CK
TCO
RMIIn_TXD_EN
RMII0_TXD_EN
TCO
RMIIn_TXD_1,
RMII0_TXD1,
RMIIn_TXD_0
RMII0_TXD0
Preamble
SFD
DATA
CRC
(n = 0, 1)
Figure 2.86
RMII Transmission Timing
REF50CK
Tsu
Thd
RMII0_CRS_DV
RMIIn_CRS_DV
Tsu
RMIIn_RXD_1,
RMII0_RXD1,
RMIIn_RXD_0
RMII0_RXD0
Thd
Preamble
DATA
CRC
SFD
RMIIn_RX_ER
RMII0_RX_ER
L
(n = 0, 1)
Figure 2.87
RMII Reception Timing (Normal Operation)
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RX72M Group
2. Electrical Characteristics
REF50CK
RMIIn_CRS_DV
RMII0_CRS_DV
RMII0_RXD1,
RMIIn_RXD_1,
RMII0_RXD0
RMIIn_RXD_0
Preamble
SFD
DATA
xxxx
Thd
Tsu
RMIIn_RX_ER
RMII0_RX_ER
(n = 0, 1)
Figure 2.88
RMII Reception Timing (Error Occurrence)
REF50CK
tWOLd
ETn_WOL
ET0_WOL
(n = 0, 1)
Figure 2.89
WOL Output Timing (RMII)
ETn_TX_CLK
ET0_TX_CLK
tTENd
ETn_TX_EN
ET0_TX_EN
tMTDd
ETn_ETXD[3:0]
ET0_ETXD[3:0]
Preamble
SFD
DATA
CRC
ETn_TX_ER
ET0_TX_ER
tCRSs
tCRSh
ETn_CRS
ET0_CRS
ETn_COL
ET0_COL
(n = 0, 1)
Figure 2.90
MII Transmission Timing (Normal Operation)
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RX72M Group
2. Electrical Characteristics
ETn_TX_CLK
ET0_TX_CLK
ETn_TX_EN
ET0_TX_EN
ETn_ETXD[3:0]
ET0_ETXD[3:0]
JAM
Preamble
ETn_TX_ER
ET0_TX_ER
ETn_CRS
ET0_CRS
tCOLs
tCOLh
ETn_COL
ET0_COL
(n = 0, 1)
Figure 2.91
MII Transmission Timing (Conflict Occurrence)
ETn_RX_CLK
ET0_RX_CLK
tRDVs
tRDVh
ETn_RX_DV
ET0_RX_DV
tMRDh
tMRDs
ETn_ERXD[3:0]
ET0_ERXD[3:0]
Preamble
SFD
DATA
CRC
ETn_RX_ER
ET0_RX_ER
(n = 0, 1)
Figure 2.92
MII Reception Timing (Normal Operation)
ETn_RX_CLK
ET0_RX_CLK
ETn_RX_DV
ET0_RX_DV
ET0_ERXD[3:0]
ETn_ERXD[3:0]
Preamble
SFD
DATA
xxxx
tRERh
tRERs
ETn_RX_ER
ET0_RX_ER
(n = 0, 1)
Figure 2.93
MII Reception Timing (Error Occurrence)
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RX72M Group
2. Electrical Characteristics
ETn_RX_CLK
ET0_RX_CLK
tWOLd
ETn_WOL
ET0_WOL
(n = 0, 1)
Figure 2.94
WOL Output Timing (MII)
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Nov 15, 2023
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RX72M Group
2.4.7.19
Table 2.48
2. Electrical Characteristics
PDC
PDC Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
PDC
Symbol
Min.*1
Max.
Unit
tPIXcyc
37
—
ns
PIXCLK input high pulse width
tPIXH
10
—
ns
PIXCLK input low pulse width
tPIXL
10
—
ns
PIXCLK rising time
tPIXr
—
5
ns
PIXCLK falling time
tPIXf
—
5
ns
tPCKcyc
2 × tPBcyc
—
ns
PIXCLK input cycle time
PCKO output cycle time
PCKO output high pulse width
tPCKH
(tPCKcyc – tPCKr – tPCKf)/2 – 3
—
ns
PCKO output low pulse width
tPCKL
(tPCKcyc – tPCKr – tPCKf)/2 – 3
—
ns
PCKO rising time
tPCKr
—
5
ns
PCKO falling time
tPCKf
—
5
ns
VSYNC/HSYNC input setup time
tSYNCS
10
—
ns
VSYNC/HSYNC input hold time
tSYNCH
5
—
ns
PIXD input setup time
tPIXDS
10
—
ns
PIXD input hold time
tPIXDH
5
—
ns
Test
Conditions
Figure 2.95
Figure 2.96
Figure 2.97
Note 1. tPBcyc: PCLKB cycle
tPIXcyc
tPIXH
tPIXf
PIXCLK input
tPIXr
tPIXL
Figure 2.95
PDC Input Clock Timing
tPCKcyc
tPCKH
tPCKf
PCKO pin output
tPCKr
tPCKL
Figure 2.96
PDC Output Clock Timing
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RX72M Group
2. Electrical Characteristics
PIXCLK
tSYNCS
tSYNCH
VSYNC
tSYNCS
tSYNCH
HSYNC
tPIXDS
tPIXDH
PIXD7 to PIXD0
Figure 2.97
PDC AC Timing
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Nov 15, 2023
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RX72M Group
2.4.7.20
Table 2.49
2. Electrical Characteristics
GLCDC
GLCDC Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF
Item
Symbol
Min.
Typ.
Max.
Unit
MHz
LCD_EXTCLK Input clock frequency
tEcyc
—
—
30*1
LCD_EXTCLK Input clock Low pulse width
tWL
0.45
—
0.55
tEcyc
LCD_EXTCLK Input clock High pulse width
tWH
0.45
—
0.55
tEcyc
MHz
LCD_CLK Output clock frequency
tLcyc
—
—
30*1
LCD_CLK Output clock Low pulse width
tLOL
0.4
—
0.6
tLcyc
LCD_CLK Output clock High pulse width
tLOH
0.4
—
0.6
tLcyc
LCD_CLK Output clock rise time
tLOR
—
—
5
ns
LCD_CLK Output clock fall time
tLOF
—
—
5
ns
tDD
–3.5*2
—
4*2
ns
LCD data output Delay timing
Test Conditions
Figure 2.98
Figure 2.99
Figure 2.100
Note 1. Parallel RGB888,666,565: Max. 27 MHz
Serial RGB888: Max. 30 MHz (4x speed)
Note 2. We recommend using pins that have a letter (“-A”, “-B”, etc) to indicate group membership appended to their names as groups.
For the GLCDC interface, the AC portion of the electrical characteristics is measured for each group.
If we use group “-A” and “-B” combination, “LCD data output Delay timing (tDD)” is Min = –5.0 ns, Max = 5.5 ns.
tDcyc, tEcyc
tWH
1/2 Vcc
VIH
tWL
VIH
VIL
LCD_EXTCLK
Figure 2.98
VIL
LCD_EXTCLK Clock Input Timing
tLcyc
tLOL
tLOH
LCD_CLK
tLOF
Figure 2.99
tLOR
LCD_CLK Clock Output Timing
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RX72M Group
2. Electrical Characteristics
LCD_CLK
tDD
Output on
falling edge
LCD_DATA23 to
LCD_DATA0,
LCD_TCON3 to
LCD_TCON0
Figure 2.100
tDD
Output on
rising edge
LCD Output Data Timing
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RX72M Group
2. Electrical Characteristics
2.4.7.21
A/D Converter Trigger
Table 2.50
A/D Converter Trigger Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
A/D converter
A/D converter trigger input pulse width
Symbol
Min.
Max.
Unit*1
tTRGW
1.5
—
tPBcyc
Test Conditions
Figure 2.101
Note 1. tPBcyc: PCLKB cycle
PCLKB
ADTRG0#,
ADTRG1#
tTRGW
Figure 2.101
A/D Converter Trigger Input Timing
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RX72M Group
2.4.7.22
Table 2.51
2. Electrical Characteristics
Δ-Σ Interface
Δ-Σ Interface Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
DSMIF
Clock cycle
Master
Symbol
Min.
Max.
Unit*1
Test Conditions
tDScyc
2
32
tPBcyc
Figure 2.102
40
200
ns
ns
Slave
Clock high level
Master
tDSCKWH
Slave
Clock low level
Master
Setup time
Master
tDSCKWL
Slave
tSU
Slave
Hold time
Master
tH
Slave
16
—
16
—
16
—
16
—
15
—
10
—
0
—
10
—
ns
ns
Figure 2.103,
Figure 2.104
ns
Note 1. tPBcyc: PCLKB cycle
tDSCKWH
tDSCKWL
DSMCLKn
tDScyc
(n = 0 to 5)
Figure 2.102
Clock Input/Output Timing
DSMCLKn
(input or output)
DSMDATn (input)
(n = 0 to 5)
Figure 2.103
tSU
tH
Reception Timing (DSMCLKn Rising Synchronous)
DSMCLKn
(input or output)
DSMDATn (input)
(n = 0 to 5)
Figure 2.104
tSU
tH
Reception Timing (DSMCLKn Falling Synchronous)
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RX72M Group
2.4.7.23
Table 2.52
2. Electrical Characteristics
CAC
CAC Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item*1, *2
CAC
CACREF input pulse width
tPBcyc ≤ tcac
tPBcyc > tcac
Symbol
Min.*1, *2
Max.
Unit
tCACREF
4.5 tcac +
3 tPBcyc
—
ns
5 tcac +
6.5 tPBcyc
—
Test
Conditions
Note 1. tPBcyc: PCLKB cycle
Note 2. tcac: CAC count clock source cycle
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RX72M Group
2.5
2. Electrical Characteristics
USB Characteristics
Table 2.53
On-Chip USB Low Speed (Host Only) Characteristics (DP and DM Pin Characteristics)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 3.0 to 3.6 V, 3.0 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
UCLK = 48 MHz, PCLKA = 8 to 120 MHz,
PCLKB = 8 to 60 MHz, Ta = Topr
Item
Input
characteristics
Output
characteristics
Symbol
Min.
Typ.
Test Conditions
Input high level voltage
VIH
2.0
—
—
V
VIL
—
—
0.8
V
Differential input sensitivity
VDI
0.2
—
—
V
Differential common mode range
VCM
0.8
—
2.5
V
Output high level voltage
VOH
2.8
—
3.6
V
IOH = –200 µA
Output low level voltage
VOL
0.0
—
0.3
V
IOL = 2 mA
VCRS
1.3
—
2.0
V
Figure 2.105
tLR
75
—
300
ns
Rise time
tLF
75
—
300
ns
tLR / tLF
80
—
125
%
Rpd
14.25
—
24.80
kΩ
Fall time
Rise/fall time ratio
DP/DM pull-down resistance
(when the host controller function is
selected)
DP, DM
VCRS
90%
| DP – DM |
tLR/ tLF
90%
10%
10%
tLR
Figure 2.105
Unit
Input low level voltage
Cross-over voltage
Pull-down
characteristics
Max.
tLF
DP and DM Output Timing (Low Speed)
dp
27
Observation
point
200 pF to
600 pF
dm
3.6 V
1.5 k
27
200 pF to
600 pF
Figure 2.106
Test Circuit (Low Speed)
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 158 of 180
RX72M Group
Table 2.54
2. Electrical Characteristics
On-Chip USB Full-Speed Characteristics (DP and DM Pin Characteristics)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 3.0 to 3.6 V, 3.0 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
UCLK = 48 MHz, PCLKA = 8 to 120 MHz,
PCLKB = 8 to 60 MHz, Ta = Topr
Item
Input
characteristics
Output
characteristics
Min.
Typ.
Unit
Test Conditions
Input high level voltage
VIH
2.0
—
—
V
VIL
—
—
0.8
V
Differential input sensitivity
VDI
0.2
—
—
V
Differential common mode range
VCM
0.8
—
2.5
V
Output high level voltage
VOH
2.8
—
3.6
V
IOH = –200 µA
Output low level voltage
VOL
0.0
—
0.3
V
IOL = 2 mA
VCRS
1.3
—
2.0
V
Figure 2.107
tFR
4
—
20
ns
Rise time
Fall time
| DP – DM |
tFF
4
—
20
ns
Rise/fall time ratio
tFR / tFF
90
—
111.11
%
tFR/ tFF
Output resistance
ZDRV
28
—
44
Ω
Rs = 27 Ω included
DP pull-up resistance
(when the function controller function
is selected)
Rpu
0.900
—
1.575
kΩ
Idle state
1.425
—
3.090
DP/DM pull-down resistance
(when the host controller function is
selected)
Rpd
14.25
—
24.80
DP, DM
VCRS
90%
At transmission and
reception
kΩ
90%
10%
10%
tFR
Figure 2.107
Max.
Input low level voltage
Cross-over voltage
Pull-up and
pull-down
characteristics
Symbol
tFF
DP and DM Output Timing (Full-Speed)
dp
27
Observation
point
50 pF
dm
27
50 pF
Figure 2.108
Test Circuit (Full-Speed)
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 159 of 180
RX72M Group
2.6
2. Electrical Characteristics
A/D Conversion Characteristics
Table 2.55
12-Bit A/D (Unit 0) Conversion Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKB = PCLKC = 1 MHz to 60 MHz, Ta = Topr, Source impedance = 1.0 kΩ
Item
Resolution
Analog input capacitance
Min.
Typ.
Max.
Unit
8
—
12
Bit
Test Conditions
—
—
30
pF
Channel-dediConversion time*1
cated sample-and- (Operation at PCLKC = 60 MHz)
hold circuits in use
(AN000 to AN002)
1.06
(0.4 + 0.25)
*2
—
—
µs
Sampling of channeldedicated sample-andhold circuits in 24 states
Sampling in 15 states
Offset error
—
±1.5
±3.5
LSB
AN000 to AN002 = 0.25 V
Full-scale error
—
±1.5
±3.5
LSB
AN000 to AN002 = VREFH0
– 0.25 V
Quantization error
—
±0.5
—
LSB
Absolute accuracy
—
±3.0
±5.5
LSB
DNL differential nonlinearity error
—
±1.0
±2.0
LSB
INL integral nonlinearity error
—
±1.5
±3.0
LSB
Holding characteristics of sample-andhold circuits
—
—
20
µs
0.25
—
VREFH0
– 0.25
V
0.48
(0.267)*2
—
—
µs
Offset error
—
±1.0
±2.5
LSB
Full-scale error
—
±1.0
±2.5
LSB
Dynamic range
Channel-dedicated sample-andhold circuits not in
use
(AN000 to AN007)
Conversion time*1
(Operation at PCLKC = 60 MHz)
Quantization error
—
±0.5
—
LSB
Absolute accuracy
—
±2.5
±4.5
LSB
DNL differential nonlinearity error
—
±0.5
±1.5
LSB
INL integral nonlinearity error
—
±1.0
±2.5
LSB
Sampling in 16 states
Note:
The above specification values apply when there is no access to the external bus during A/D conversion. If access proceeds
during A/D conversion, values may not fall within the above ranges.
Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states
is indicated.
Note 2. The value in parentheses indicates the sampling time.
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 160 of 180
RX72M Group
Table 2.56
2. Electrical Characteristics
12-Bit A/D (Unit 1) Conversion Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKB = PCLKD = 1 MHz to 60 MHz, Ta = Topr, Source impedance = 1.0 kΩ
Item
Min.
Typ.
Max.
Unit
8
—
12
Bit
Conversion
(Operation at PCLKD = 60 MHz)
0.88
(0.633)*2
—
—
µs
Sampling in 38 states
(ADSAM.SAM = 1)
Conversion time*1
(Operation at PCLKD = 30 MHz)
1
(0.500)*2
—
—
µs
Sampling in 15 states
(ADSAM.SAM = 1)
—
—
30
pF
Resolution
time*1
Analog input capacitance
Offset error
—
±2.0
±3.5
LSB
Full-scale error
—
±2.0
±3.5
LSB
Quantization error
—
±0.5
—
LSB
Absolute accuracy
—
±4.0
±6.0
LSB
DNL differential nonlinearity error
(Operation at PCLKD = 60 MHz)
—
±1.5
±4.0
LSB
DNL differential nonlinearity error
(Operation at PCLKD = 30 MHz)
—
±1.5
±2.5
LSB
INL integral nonlinearity error
(Operation at PCLKD = 60 MHz)
—
±2.0
±4.0
LSB
INL integral nonlinearity error
(Operation at PCLKD = 30 MHz)
—
±2.0
±3.5
LSB
Test Conditions
Note:
The above specification values apply when there is no access to the external bus during A/D conversion. If access proceeds
during A/D conversion, values may not fall within the above ranges.
Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states
is indicated.
Note 2. The value in parentheses indicates the sampling time.
Table 2.57
A/D Internal Reference Voltage Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKB = PCLKD = 60 MHz, Ta = Topr
Item
A/D internal reference voltage
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Min.
Typ.
Max.
Unit
1.13
1.18
1.23
V
Test Conditions
Page 161 of 180
RX72M Group
2.7
2. Electrical Characteristics
D/A Conversion Characteristics
Table 2.58
D/A Conversion Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
Resolution
—
12
12
12
Bit
Unbuffered output Absolute accuracy
—
—
—
±6.0
LSB
2-MΩ resistive load
10-bit conversion
2-MΩ resistive load
Differential nonlinearity error
Buffered output
DNL
—
±1.0
±2.0
LSB
Output resistance
RO
—
8.6
—
kΩ
Setting time
tS
—
—
3
µs
Load resistance
RL
5
—
—
kΩ
Load capacitance
CL
—
—
50
pF
Output voltage
VO
0.2
—
AVCC1 –
0.2
V
Differential nonlinearity error
DNL
—
±1.0
±2.0
LSB
Integral nonlinearity error
INL
—
±2.0
±4.0
LSB
tS
—
—
4
µs
Setting time
2.8
Test Conditions
20-pF capacitive load
Temperature Sensor Characteristics
Table 2.59
Temperature Sensor Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Min.
Typ.
Max.
Unit
Relative accuracy
Item
—
±1
—
°C
Temperature slope
—
4
—
mV/°C
Output voltage
—
1.21
—
V
Temperature sensor start time
—
—
30
µs
4.15
—
—
µs
Sampling time*1
Test Conditions
Ta = 25°C
Note 1. Set the S12AD1.ADSSTRT register such that the sampling time of the 12-bit A/D converter satisfies this specification.
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 162 of 180
RX72M Group
2.9
2. Electrical Characteristics
Power-on Reset Circuit and Voltage Detection Circuit Characteristics
Table 2.60
Power-on Reset Circuit and Voltage Detection Circuit Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Voltage detection
level
Min.
Typ.
Max.
Unit
VPOR
2.5
2.6
2.7
V
1.8
2.25
2.7
Vdet0_1
2.84
2.94
3.04
Vdet0_2
2.77
2.87
2.97
Vdet0_3
2.70
2.80
2.90
Vdet1_1
2.89
2.99
3.09
Vdet1_2
2.82
2.92
3.02
Vdet1_3
2.75
2.85
2.95
Vdet2_1
2.89
2.99
3.09
Vdet2_2
2.82
2.92
3.02
Vdet2_3
2.75
2.85
2.95
Power-on reset time
tPOR
—
4.6
—
LVD0 reset time
tLVD0
—
0.70
—
Figure 2.110
LVD1 reset time
tLVD1
—
0.57
—
Figure 2.111
Power-on
reset (POR)
Low power consumption
function disabled*1
Low power consumption
function enabled*2
Voltage detection circuit (LVD0)
Voltage detection circuit (LVD1)
Voltage detection circuit (LVD2)
Internal reset time
Test
Conditions
Symbol
Figure 2.109
Figure 2.110
Figure 2.111
Figure 2.112
ms
Figure 2.109
tLVD2
—
0.57
—
tVOFF
200
—
—
µs
Figure 2.109,
Figure 2.110
tdet
—
—
200
µs
Figure 2.109 to
Figure 2.112
LVD operation stabilization time (after LVD is enabled)
td(E-A)
—
—
10
µs
Hysteresis width (LVD1 and LVD2)
V LVH
—
70
—
mV
Figure 2.111,
Figure 2.112
LVD2 reset time
Minimum VCC down time
Response delay time
Figure 2.112
Note:
The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet1,
and Vdet2 for the POR/ LVD.
Note 1. The low power consumption function is disabled and DEEPCUT[1:0] = 00b or 01b.
Note 2. The low power consumption function is enabled and DEEPCUT[1:0] = 11b.
tVOFF
VPOR
VCC
Internal reset signal
(Low is valid)
tdet
Figure 2.109
tPOR
tdet
tdet
tPOR
Power-on Reset Timing
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 163 of 180
RX72M Group
2. Electrical Characteristics
tVOFF
VCC
Vdet0
Internal reset signal
(Low is valid)
tdet
Figure 2.110
tdet
tLVD0
Voltage Detection Circuit Timing (Vdet0)
tVOFF
VCC
VLVH
Vdet1
LVD1E
Td(E-A)
LVD1
Comparator output
LVD1CMPE
LVD1MON
Internal reset signal
(Low is valid)
When LVD1RN = L
tdet
tdet
tLVD1
When LVD1RN = H
tLVD1
Figure 2.111
Voltage Detection Circuit Timing (Vdet1)
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 164 of 180
RX72M Group
2. Electrical Characteristics
tVOFF
VCC
VLVH
Vdet2
LVD2E
LVD2
Comparator output
Td(E-A)
LVD2CMPE
LVD2MON
Internal reset signal
(Low is valid)
When LVD2RN = L
tdet
tdet
tLVD2
When LVD2RN = H
tLVD2
Figure 2.112
Voltage Detection Circuit Timing (Vdet2)
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 165 of 180
RX72M Group
2.10
2. Electrical Characteristics
Oscillation Stop Detection Timing
Table 2.61
Oscillation Stop Detection Circuit Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr
Item
Detection time
Symbol
Min.
Typ.
Max.
Unit
tdr
—
—
1
ms
Test Conditions
Figure 2.113
Main clock or
PLL clock
tdr
OSTDSR.OSTDF
LOCO clock
ICLK
Figure 2.113
Oscillation Stop Detection Timing
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 166 of 180
RX72M Group
2.11
2. Electrical Characteristics
Battery Backup Function Characteristics
Table 2.62
Battery Backup Function Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
VBATT = 1.62 to 3.6 V, Ta = Topr
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
Voltage level for switching to battery backup
VDETBATT
2.50
2.60
2.70
V
Figure 2.114
Lower-limit VBATT voltage for power supply switching due to
VCC voltage drop
VBATTSW
2.70
—
—
VCC-off period for starting power supply switching
tVOFFBATT
200
—
—
Item
Note:
µs
The VCC-off period for starting power supply switching indicates the period in which VCC is below the minimum value of the
voltage level for switching to battery backup (VDETBATT).
tVOFFBATT
VDETBATT
VCC
VBATT
Backup power
area
VCC voltage
guaranteed range
VBATTSW
VBATT
Switching
prohibited
VCC supply
VBATT
Switching
prohibited
VBATT supply
VBATT voltage
guaranteed range
VCC supply
Note. The VBATT voltage when the supplied power source switches from VCC to VBATT should not be lower than VBATTSW,
the lower-limit VBATT voltage for switching between power supplies due to a drop in the VCC voltage.
Figure 2.114
Battery Backup Function Characteristics
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 167 of 180
RX72M Group
2.12
2. Electrical Characteristics
Flash Memory Characteristics
Table 2.63
Code Flash Memory Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Temperature range for programming/erasure: Ta = Topr
Item
Programming time
NPEC ≤ 100 times
Programming time
NPEC > 100 times
Erasure time
NPEC ≤ 100 times
Erasure time
NPEC > 100 times
Symbol
FCLK = 4 MHz
FCLK = 15 MHz
20 MHz ≤ FCLK ≤ 60 MHz
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
128 bytes
tP128
—
0.75
13.2
—
0.38
6.6
—
0.34
6
ms
8 Kbytes
tP8K
—
49
176
—
25
88
—
22
80
ms
32 Kbytes
tP32K
—
194
704
—
97
352
—
88
320
ms
128 bytes
tP128
—
0.91
15.8
—
0.46
8
—
0.41
7.2
ms
8 Kbytes
tP8K
—
60
212
—
30
106
—
27
96
ms
32 Kbytes
tP32K
—
234
848
—
117
424
—
106
384
ms
8 Kbytes
tE8K
—
78
216
—
48
132
—
43
120
ms
32 Kbytes
tE32K
—
283
864
—
173
528
—
157
480
ms
8 Kbytes
tE8K
—
94
260
—
58
158
—
52
144
ms
32 Kbytes
tE32K
—
341
1040
—
208
632
—
189
576
ms
Reprogramming/erasure cycle*1
NPEC
10000
*2
—
—
10000
*2
—
—
10000
*2
—
—
Times
Suspend delay time during
programming
tSPD
—
—
264
—
—
132
—
—
120
µs
First suspend delay time during
erasing
(in suspend priority mode)
tSESD1
—
—
216
—
—
132
—
—
120
µs
Second suspend delay time
during erasure
(in suspend priority mode)
tSESD2
—
—
1.7
—
—
1.7
—
—
1.7
ms
Suspend delay time during
erasure
(in erasure priority mode)
tSEED
—
—
1.7
—
—
1.7
—
—
1.7
ms
Forced stop command
Data retention*3, *4
tFD
—
—
32
—
—
22
—
—
20
µs
tDRP
20
—
—
20
—
—
20
—
—
Year
10
—
—
10
—
—
10
—
—
Conditions
Ta ≤ 85°C
Ta ≤ 105°C
Note 1. Definition of reprogram/erase cycle:
The program/erase cycle is the number of erasing for each block. When the number of program/erase cycles is n, each block
can be erased n times. For instance, when 128-byte program is performed 64 times for different addresses in 8-Kbyte block and
then the block is erased, the program/erase cycle is counted as one. However, the same address cannot be programmed more
than once before the next erase cycle (overwriting is prohibited).
Note 2. Characteristics are degraded as the number of program/erase increases. This is the minimum value of program/erase cycles to
guarantee all characteristics listed in this table.
Note 3. This shows the characteristics when a self-programming library provided by Renesas Electronics or a flash programmer is used
and the program/erase cycle does not exceed the specified value.
Note 4. This result is obtained from reliability testing.
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 168 of 180
RX72M Group
Table 2.64
2. Electrical Characteristics
Data Flash Memory Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Temperature range for programming/erasure: Ta = Topr
Item
Symbol
FCLK = 4 MHz
FCLK = 15 MHz
20 MHz ≤ FCLK ≤ 60 MHz
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Programming time
4 bytes
tDP4
—
0.36
3.8
—
0.18
1.9
—
0.16
1.7
ms
Erasure time
64 bytes
tDP64
—
3.1
18
—
1.9
11
—
1.7
10
ms
128 bytes
tDP128
—
4.7
27
—
2.9
16
—
2.6
15
ms
256 bytes
tDP256
—
8.9
50
—
5.4
31
—
4.9
28
ms
4 bytes
tDBC4
—
—
84
—
—
33
—
—
30
µs
64 bytes
tDBC64
—
—
280
—
—
110
—
—
100
µs
2 Kbytes
tDBC2K
—
—
6160
—
—
2420
—
—
2200
µs
NDPEC
100000
*2
—
—
100000
*2
—
—
100000
*2
—
—
Times
tDSPD
—
—
264
—
—
132
—
—
120
µs
Blank check time
Reprogramming/erasure
cycle*1
Suspend delay time during
programming
First suspend delay
time during erasure
(in suspend priority
mode)
64 bytes
—
—
—
216
—
—
132
—
—
120
µs
128 bytes
—
—
—
216
—
—
132
—
—
120
µs
256 bytes
—
—
—
216
—
—
132
—
—
120
µs
Second suspend
delay time during
erasure (in suspend
priority mode)
64 bytes
—
—
—
300
—
—
300
—
—
300
µs
128 bytes
—
—
—
390
—
—
390
—
—
390
µs
256 bytes
—
—
—
570
—
—
570
—
—
570
µs
Suspend delay time
during erasing
(in suspend priority
mode)
64 bytes
—
—
—
300
—
—
300
—
—
300
µs
128 bytes
—
—
—
390
—
—
390
—
—
390
µs
—
—
—
570
—
—
570
—
—
570
µs
tFD
—
—
32
—
—
22
—
—
20
µs
Year
256 bytes
Forced stop command
Data
retention*3, *4
tDDRP
20
—
—
20
—
—
20
—
—
10
—
—
10
—
—
10
—
—
Conditions
Ta ≤ 85°C
Ta ≤ 105°C
Note 1. Definition of reprogram/erase cycle:
The program/erase cycle is the number of erasing for each block. When the number of program/erase cycles is n, each block
can be erased n times. For instance, when 4-byte program is performed 512 times for different addresses in 2-Kbyte block and
then the block is erased, the program/erase cycle is counted as one. However, the same address cannot be programmed more
than once before the next erase cycle (overwriting is prohibited).
Note 2. Characteristics are degraded as the number of program/erase increases. This is the minimum value of program/erase cycles to
guarantee all characteristics listed in this table.
Note 3. This shows the characteristics when a self-programming library provided by Renesas Electronics or a flash programmer is used
and the program/erase cycle does not exceed the specified value.
Note 4. This result is obtained from reliability testing.
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 169 of 180
RX72M Group
2. Electrical Characteristics
• Suspension during programming
FCU command
Program
Suspend
tSPD
FSTATR.FRDY
Ready
Programming pulse
Not Ready
Ready
Programming
• Suspension during erasure in suspend priority mode
FCU command
Erase
Suspend
Resume
Suspend
tSESD1
FSTATR.FRDY
Ready
Erasure pulse
Not Ready
tSESD2
Ready
Erasing
Not Ready
Erasing
• Suspension during erasure in erasure priority mode
FCU command
Erase
Suspend
tSEED
FSTATR.FRDY
Ready
Erasure pulse
Figure 2.115
Not Ready
Ready
Erasing
Flash Memory Programming/Erasure Suspension Timing
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Nov 15, 2023
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RX72M Group
2.13
2. Electrical Characteristics
Boundary Scan
Table 2.65
Boundary Scan Characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
tTCKcyc
100
—
—
ns
TCK clock high pulse width
tTCKH
45
—
—
ns
TCK clock low pulse width
tTCKL
45
—
—
ns
TCK clock rise time
tTCKr
—
—
5
ns
TCK clock fall time
tTCKf
—
—
5
ns
TRST# pulse width
tTRSTW
20
—
—
tTCKcyc
Figure 2.117
Figure 2.118
TCK clock cycle time
TMS setup time
tTMSS
20
—
—
ns
TMS hold time
tTMSH
20
—
—
ns
TDI setup time
tTDIS
20
—
—
ns
TDI hold time
tTDIH
20
—
—
ns
TDO data delay time
tTDOD
—
—
40
ns
Figure 2.116
tTCKcyc
tTCKH
TCK
tTCKf
tTCKL
Figure 2.116
tTCKr
Boundary Scan TCK Timing
TCK
RES#
TRST#
tTRSTW
Figure 2.117
Boundary Scan TRST# Timing
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 171 of 180
RX72M Group
2. Electrical Characteristics
TCK
tTMSS
tTMSH
tTDIS
tTDIH
TMS
TDI
tTDOD
TDO
Figure 2.118
Boundary Scan Input/Output Timing
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 172 of 180
RX72M Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
Information on the latest version of the package dimensions or mountings has been displayed in “Packages” on Renesas
Electronics Corporation website.
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-LFBGA224-13x13-0.80
PLBG0224GA-A
224FHE
0.4
Unit: mm
E
B
A
D
INDEX AREA
y1 S
A
S
A1
y CZ
e
(ZE)
e
R
P
N
Reference Dimensions in millimeters
Symbol
M
Min
Nom
Max
D
12.9
13.0
13.1
E
12.9
13.0
13.1
G
A
1.40
F
A1
0.30
0.35
0.40
E
e
0.80
b
0.40
0.45
0.50
L
K
J
H
D
(ZD)
C
B
A
1 2
3 4 5
6 7
n x ݊b
8 9 10 11 12 13 14 15
x1
x2
S A
S
B
x1
0.15
x2
0.08
y
0.10
y1
0.20
n
224
ZD
0.90
ZE
0.90
Figure A 224-Pin LFBGA (PLBG0224GA-A)
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Page 173 of 180
RX72M Group
Appendix 1. Package Dimensions
Figure B 176-Pin LFBGA (PLBG0176GA-A)
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
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RX72M Group
Appendix 1. Package Dimensions
Figure C 176-Pin LFQFP (PLQP0176KB-C)
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
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RX72M Group
Appendix 1. Package Dimensions
Figure D 144-Pin LFQFP (PLQP0144KA-B)
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RX72M Group
Appendix 1. Package Dimensions
Figure E 100-Pin LFQFP (PLQP0100KB-B)
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Nov 15, 2023
Page 177 of 180
REVISION HISTORY
RX72M Group
REVISION HISTORY
REVISION HISTORY
RX72M Group Datasheet
Classifications
- Items with Technical Update document number: Changes according to the corresponding issued Technical Update
- Items without Technical Update document number: Minor changes that do not require Technical Update to be issued
Rev.
Date
1.00
1.11
May 31, 2019
Feb 26, 2021
1.20
Nov 15, 2023
Page
—
Features
Description
Summary
First edition, issued
144-pin LFQFP and 100-pin LFQFP Package Images, added
1. Overview
All
144-pin LFQFP and 100-pin LFQFP specifications, added
2. Electrical Characteristics
85, 86
Table 2.6 DC Characteristics (3), Note 3, changed
87
Table 2.9 Thermal Resistance Value (Reference), changed
94
Table 2.18 HOCO Clock Timing, changed
101
Table 2.26 Bus Timing, Conditions 1, Conditions 2, changed
104
Figure 2.21 External Bus Timing/Normal Write Cycle (Bus Clock
Synchronized), changed
105
Figure 2.23 External Bus Timing/Page Write Cycle (Bus Clock
Synchronized), changed
114
Table 2.27 EXDMAC Timing, Conditions, changed
115 to 157 2.4.7 Timing of On-Chip Peripheral Modules, order of tables changed
118
Figure 2.41 MTU Clock Input Timing, changed
122
Figure 2.51 Output Disable Time of POEG in Response to the Oscillation
Stop Detection, changed
126
Figure 2.56 Simple IIC Bus Interface Input/Output Timing, added
153
Table 2.49 GLCDC Timing, changed
Appendix 1. Package Dimensions
All
144-pin LFQFP and 100-pin LFQFP package dimensions, added
1. Overview
12
Table 1.1 Outline of Specifications (11/11), changed
2. Electrical Characteristics
82
Table 2.2 Recommended Operating Conditions (1), changed
Table 2.3 Recommended Operating Conditions (2), changed
83
Table 2.4 DC Characteristics (1), changed
85, 86
Table 2.6 DC Characteristics (3), changed
95
Table 2.20 Sub-Clock Timing, changed
96
Table 2.21 CLKOUT Pin Output Timing, changed
Table 2.22 CLKOUT25M Pin Output Timing, changed
167
Table 2.62 Battery Backup Function Characteristics, changed
168
Table 2.63 Code Flash Memory Characteristics, changed
169
Table 2.64 Data Flash Memory Characteristics, changed
R01DS0332EJ0120 Rev.1.20
Nov 15, 2023
Classification
TN-RX*-A0220A/E
TN-RX*-A0243A/E
TN-RX*-A0243A/E
TN-RX*-A0243A/E
TN-RX*-A0252A/E
TN-RX*-A0252A/E
TN-RX*-A0273A/E
TN-RX*-A0252A/E
TN-RX*-A0251A/E
Page 178 of 180
General Precautions in the Handling of Microprocessing Unit and Microcontroller
Unit Products
General Precautions in the Handling of Microprocessing Unit and Microcontroller
Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage
notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have
been issued for the products.
1.
Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps
must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be
adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.
Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be
touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.
2.
Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of
register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset
pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins
in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the
level at which resetting is specified.
3.
Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements.
Follow the guideline for input signal during power-off state as described in your product documentation.
4.
Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are
generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of
the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
become possible.
5.
Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program
execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator
during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced
with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
6.
Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.)
and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level
is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.).
7.
Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these
addresses as the correct operation of the LSI is not guaranteed.
8.
Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.
The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms
of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,
operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a systemevaluation test for the given product.
Notice
Notice
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products
and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your
product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of
these circuits, software, or information.
Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or
other intellectual property rights of third parties, by or arising from the use of Renesas Electronics products or technical information described in this
document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application examples.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
You shall be responsible for determining what licenses are required from any third parties, and obtaining such licenses for the lawful import, export,
manufacture, sales, utilization, distribution or other disposal of any products incorporating Renesas Electronics products, if required.
You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any
and all liability for any losses or damages incurred by you or third parties arising from such alteration, modification, copying or reverse engineering.
Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for
each Renesas Electronics product depends on the product’s quality grade, as indicated below.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home
electronic appliances; machine tools; personal electronic equipment; industrial robots; etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key
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Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas
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any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is
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hardware or software products, Renesas Electronics shall have absolutely no liability arising out of any vulnerability or security breach, including but not
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ELECTRONICS DOES NOT WARRANT OR GUARANTEE THAT RENESAS ELECTRONICS PRODUCTS, OR ANY SYSTEMS CREATED USING
RENESAS ELECTRONICS PRODUCTS WILL BE INVULNERABLE OR FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE,
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THE IMPLIED WARRANTIES OF MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE.
When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for
Handling and Using Semiconductor Devices” in the reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by
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Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific
characteristics, such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Unless designated as a high reliability
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design for hardware and software, including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging
degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult and impractical, you are
responsible for evaluating the safety of the final products or systems manufactured by you.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas
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controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics products in compliance with all these
applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance
with applicable laws and regulations.
Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is
prohibited under any applicable domestic or foreign laws or regulations. You shall comply with any applicable export control laws and regulations
promulgated and administered by the governments of any countries asserting jurisdiction over the parties or transactions.
It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or
transfers the product to a third party, to notify such third party in advance of the contents and conditions set forth in this document.
This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas
Electronics products.
(Note1)
“Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled
subsidiaries.
(Note2)
“Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
(Rev.5.0-1 October 2020)
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