R5F572NNDDBG#20

Features Datasheet RX72N Group R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Renesas MCUs 240-MHz 32-bit RX MCU, on-chip double-precision FPU, 1396 CoreMark, Arithmetic unit for trigonometric functions, up to 4-MB flash memory (supportive of the dual bank function), 1-MB SRAM, various communications interfaces including Ethernet MAC compliant with IEEE 1588, SD host interface, quad SPI, and CAN, 12-bit A/D converter, RTC, Encryption functions (optional), Serial sound interface, CMOS camera interface, Graphic-LCD controller, 2D drawing engine Features PLQP0176KB-C 24 × 24 mm, 0.5-mm pitch PLQP0144KA-B 20 × 20 mm, 0.5-mm pitch PLQP0100KB-B 14 × 14 mm, 0.5-mm pitch ■ 32-bit RXv3 CPU core  Maximum operating frequency: 240 MHz Capable of 1396 CoreMark in operation at 240 MHz  Double-precision 64-bit IEEE-754 floating point  A collective register bank save function is available.  Supports the memory protection unit (MPU)  JTAG and FINE (one-line) debugging interfaces PTLG0145KA-A 7 × 7 mm, 0.5-mm pitch ■ Low-power design and architecture  Operation from a single 2.7- to 3.6-V supply  RTC is capable of operation from a dedicated power supply.  Four low-power modes ■ On-chip code flash memory  Supports versions with up to 4 Mbytes of ROM  No wait cycles at up to 120 MHz or when the ROM cache is hit, one-wait state at above 120 MHz  User code is programmable by on-board or off-board programming.  Programming/erasing as background operations (BGOs)  A dual-bank structure allows exchanging the start-up bank. ■ On-chip data flash memory  32 Kbytes, reprogrammable up to 100,000 times  Programming/erasing as background operations (BGOs) ■ On-chip SRAM  1 Mbyte of SRAM (no wait states; however, if ICLK is at a frequency above 120 MHz, access to locations in the 512 Kbytes of SRAM from 0080 0000h to 0087 FFFFh requires one cycle of waiting)  32 Kbytes of RAM with ECC (single error correction/double error detection)  8 Kbytes of standby RAM (backup on deep software standby) ■ Data transfer     DMACAa: 8 channels DTCb: 1 channel EXDMAC: 2 channels DMAC for the Ethernet controller: 3 channels ■ Reset and supply management  Power-on reset (POR)  Low voltage detection (LVD) with voltage settings ■ Clock functions  External crystal resonator or internal PLL for operation at 8 to 24 MHz  PLL for specific purposes  Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20 MHz  120-kHz clock for the IWDTa ■ Real-time clock  Adjustment functions (30 seconds, leap year, and error)  Real-time clock counting and binary counting modes are selectable  Time capture function (for capturing times in response to event-signal input) ■ Independent watchdog timer  120-kHz clock operation ■ Useful functions for IEC60730 compliance  Oscillation-stoppage detection, frequency measurement, CRCA, IWDTa, self-diagnostic function for the A/D converter, etc.  Register write protection function can protect values in important registers against overwriting. PLBG0224GA-A 13 × 13 mm, 0.8-mm pitch PLBG0176GA-A 13 × 13 mm, 0.8-mm pitch ■ Various communications interfaces  Ethernet MAC compliant with IEEE 1588 (2 channels)  PHY layer (1 channel) for host/function or OTG controller (1 channel) with full-speed USB 2.0 transfer  CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up to 3 channels)  SCIj and SCIh with multiple functionalities (up to 8 channels) Choose from among asynchronous mode, clock-synchronous mode, smart-card interface mode, simplified SPI, simplified I2C, and extended serial mode.  SCIi with 16-byte transmission and reception FIFOs (up to 5 channels)  I2C bus interface for transfer at up to 1 Mbps (3 channels)  Four-wire QSPI (1 channel) in addition to RSPIc (3 channels)  Parallel data capture unit (PDC) for the CMOS camera interface (except for 100-pin products)  Graphic-LCD controller (GLCDC)  2D drawing engine (DRW2D)  SD host interface (1 channel) with a 1- or 4-bit SD bus for use with SD memory or SDIO  MMCIF with 1-, 4-, or 8-bit transfer bus width ■ External address space  Buses for full-speed data transfer (max. operating frequency of 80 MHz)  8 CS areas  8-, 16-, or 32-bit bus space is selectable per area  Independent SDRAM area (128 Mbytes) ■ Up to 29 extended-function timers  32-bit GPTW (4 channels)  16-bit TPUa (6 channels), MTU3a (9 channels)  8-bit TMRa (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2 channels) ■ 12-bit A/D converter  Two 12-bit units (8 channels for unit 0; 21 channels for unit 1)  Self diagnosis, detection of analog input disconnection ■ 12-bit D/A converter: 2 channels ■ Temperature sensor for measuring temperature within the chip ■ Arithmetic unit for trigonometric functions ■ Encryption functions (optional)  AES (key lengths: 128, 192, and 256 bits)  Trusted Secure IP (TSIP) ■ Up to 182 pins for general I/O ports  5-V tolerance, open drain, input pull-up, switchable driving ability ■ Operating temp. range  D-version: –40C to +85C  G-version: –40C to +105C R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 1 of 179 RX72N Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications in outline, and Table 1.2 give a comparison of the functions of products in different packages. Table 1.1 is an outline of maximum specifications, and the peripheral modules and the number of channels of the modules differ depending on the number of pins on the package and the capacity of the code flash memory. For details, refer to Table 1.2, Comparison of Functions for Different Packages. Table 1.1 Outline of Specifications (1/11) Classification Module/Function Description CPU CPU  Maximum operating frequency: 240 MHz  32-bit RX CPU (RXv3)  Minimum instruction execution time: One instruction per state (cycle of the system clock)  Address space: 4-Gbyte linear  Register set of the CPU General purpose: Sixteen 32-bit registers Control: Ten 32-bit registers Accumulator: Two 72-bit registers  113 instructions Instructions installed as standard: 111 Basic instructions: 77 Single-precision floating-point operation instructions: 11 DSP instructions: 23 Instructions for register bank save function: 2  Addressing modes: 11  Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian  On-chip 32-bit multiplier: 32 × 32 → 64 bits  On-chip divider: 32 / 32 → 32 bits  Barrel shifter: 32 bits FPU  Single-precision floating-point numbers (32 bits) and double-precision floating-point numbers (64 bits)  Data types and floating-point exceptions in conformance with the IEEE754 standard Double-precision floating point coprocessor  Double-precision floating-point register set Double-precision floating-point data registers: 16, each with 64-bit width Double-precision floating-point control registers: Four, each with 32-bit width  Double-precision floating-point processing instructions: 21  Notifying the interrupt controller of double-precision floating-point exceptions Register bank save function  Fast collective saving and restoration of the values of CPU registers  16 save register banks R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 2 of 179 RX72N Group Table 1.1 1. Overview Outline of Specifications (2/11) Classification Module/Function Description Memory Code flash memory  Capacity: 2 Mbytes/4 Mbytes  ROM cache: 8 Kbytes  120 MHz ≤ No-wait cycle access, 120 MHz > One-wait cycle access  Instructions hitting the ROM cache or operand = 240 MHz: No-wait access  On-board programming: Four types  Off-board programming (parallel programmer mode)  Instructions are executable only for the program stored in the TM target area by using the Trusted Memory (TM) function and protection against data reading is realized.  A dual-bank structure allows programming during reading or exchanging the start-up areas Data flash memory  Capacity: 32 Kbytes  Programming/erasing: 100,000 times Unique ID  16-byte unique ID for each device RAM  Capacity: 512 Kbytes  Up to 240 MHz, no-wait access Expansion RAM  Capacity: 512 Kbytes  120 MHz ≤ No-wait cycle access, 120 MHz > One-wait cycle access ECC RAM  Capacity: 32 Kbytes  If the operating frequency is no greater than 120 MHz, one-wait cycle access, if greater than 120MHz, two-wait cycle access in the case of reading, and three-wait cycle access in the case of writing  SEC-DED (single-bit error correction and double-bit error detection) Standby RAM  Capacity: 8 Kbytes  Operation synchronized with PCLKB: Up to 60 MHz, two-cycle access  Operating modes by the mode-setting pins at the time of release from the reset state Single-chip mode Boot mode (for the SCI interface) Boot mode (for the USB interface) Boot mode (for the FINE interface)  Selection of operating mode by register setting Single-chip mode On-chip ROM disabled extended mode On-chip ROM enabled extended mode  Endian selectable Operating modes Clock Clock generation circuit R01DS0343EJ0111 Rev.1.11 Feb 26, 2021  Main clock oscillator, sub-clock oscillator, low-speed/high-speed on-chip oscillator, PLL frequency synthesizer (two circuits), and IWDT-dedicated on-chip oscillator  The peripheral module clocks can be set to frequencies above that of the system clock.  Main-clock oscillation stoppage detection  Separate frequency-division and multiplication settings for the system clock (ICLK), peripheral module clocks (PCLKA, PCLKB, PCLKC, PCLKD), flash-IF clock (FCLK) and external bus clock (BCLK) The CPU and other bus masters run in synchronization with the system clock (ICLK): Up to 240 MHz Peripheral modules of MTU, RSPI, SCIi, ETHERC, EPTPC, PMGI, EDMAC, GPTW, GLCDC, and DRW2D, run in synchronization with PCLKA, which operates at up to 120 MHz. Other peripheral modules run in synchronization with PCLKB: Up to 60 MHz ADCLK in the S12AD (unit 0) runs in synchronization with PCLKC: Up to 60 MHz ADCLK in the S12AD (unit 1) runs in synchronization with PCLKD: Up to 60 MHz Flash IF run in synchronization with the flash-IF clock (FCLK): Up to 60 MHz Devices connected to the external bus run in synchronization with the external bus clock (BCLK): Up to 80 MHz  The high-speed on-chip oscillator (HOCO) can be obtained through frequencymultiplication of the PLL or PPLL reference clock  External clock input frequency: 30 MHz (max)  Clock output function Page 3 of 179 RX72N Group Table 1.1 Classification 1. Overview Outline of Specifications (3/11) Module/Function Description Reset Nine types of reset  RES# pin reset: Generated when the RES# pin is driven low.  Power-on reset: Generated when the RES# pin is driven high and VCC = AVCC0 = AVCC1 rises.  Voltage-monitoring 0 reset: Generated when VCC = AVCC0 = AVCC1 falls.  Voltage-monitoring 1 reset: Generated when VCC = AVCC0 = AVCC1 falls.  Voltage-monitoring 2 reset: Generated when VCC = AVCC0 = AVCC1 falls.  Deep software standby reset: Generated in response to an interrupt to trigger release from deep software standby.  Independent watchdog timer reset: Generated when the independent watchdog timer underflows, or a refresh error occurs.  Watchdog timer reset: Generated when the watchdog timer underflows, or a refresh error occurs.  Software reset: Generated by register setting. Power-on reset  If the RES# pin is at the high level when power is supplied, an internal reset is generated. After VCC = AVCC0 = AVCC1 has exceeded the voltage detection level and the specified period has elapsed, the reset is cancelled. Voltage detection circuit (LVDA) Monitors the voltage being input to the VCC = AVCC0 = AVCC1 pins and generates an internal reset or interrupt.  Voltage detection circuit 0 Capable of generating an internal reset The option-setting memory can be used to select enabling or disabling of the reset. Voltage detection level: Selectable from three different levels (2.94 V, 2.87 V, 2.80 V)  Voltage detection circuits 1 and 2 Voltage detection level: Selectable from three different levels (2.99 V, 2.92 V, 2.85 V) Digital filtering (1/2, 1/4, 1/8, and 1/16 LOCO frequency) Capable of generating an internal reset  Two types of timing are selectable for release from reset An internal interrupt can be requested.  Detection of voltage rising above and falling below thresholds is selectable.  Maskable or non-maskable interrupt is selectable Voltage detection monitoring Event linking Low power consumption Low power consumption function  Module stop function  Four low power consumption modes Sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode Battery backup function  When the voltage on the VCC pin drops, battery power from the VBATT pin is supplied to keep the real-time clock (RTC) operating. Interrupt controller (ICUD)       Interrupt External bus extension R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Number of interrupt vectors: 256 External interrupts: 16 (pins IRQ0 to IRQ15) Software interrupts: 2 sources Non-maskable interrupts: 8 sources Sixteen levels specifiable for the order of priority Method of interrupt source selection: The interrupt vectors consist of 256 vectors (128 sources are fixed. The remaining 128 vectors are selected from among the other 163 sources.)  The external address space can be divided into eight areas (CS0 to CS7), each with independent control of access settings. Capacity of each area: 16 Mbytes (CS0 to CS7) A chip-select signal (CS0# to CS7#) can be output for each area. Each area is specifiable as an 8-, 16-, or 32-bit bus space. The data arrangement in each area is selectable as little or big endian (only for data).  SDRAM interface connectable  Bus format: Separate bus, multiplex bus  Wait control  Write buffer facility Page 4 of 179 RX72N Group Table 1.1 1. Overview Outline of Specifications (4/11) Classification Module/Function Description DMA DMA controller (DMACAa)  8 channels  Three transfer modes: Normal transfer, repeat transfer, and block transfer  Activation sources: Software trigger and interrupt requests from peripheral functions EXDMA controller (EXDMACa)  2 channels Four transfer modes: Normal transfer, repeat transfer, block transfer, and cluster transfer  Single-address transfer enabled with the EDACKn signal  Request sources: Software trigger, external DMA requests (EDREQn), and interrupt requests from peripheral functions Data transfer controller (DTCb)  Three transfer modes: Normal transfer, repeat transfer, and block transfer  Request sources: External interrupts and interrupt requests from peripheral functions  Sequence transfer Programmable I/O ports  I/O ports for the 224-pin LFBGA I/O pins: 182 Input pin: 1 Pull-up resistors: 182 Open-drain outputs: 182 5-V tolerance: 19  I/O ports for the 176-pin LFBGA and 176-pin LFQFP I/O pins: 136 Input pin: 1 Pull-up resistors: 136 Open-drain outputs: 136 5-V tolerance: 19  I/O ports for the 145-pin TFLGA and 144-pin LFQFP I/O pins: 111 Input pin: 1 Pull-up resistors: 111 Open-drain outputs: 111 5-V tolerance: 18  I/O ports for the 100-pin LFQFP I/O pins: 78 Input pin: 1 Pull-up resistors: 78 Open-drain outputs: 78 5-V tolerance: 17 I/O ports Event link controller (ELC) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021  Event signals such as interrupt request signals can be interlinked with the operation of functions such as timer counting, eliminating the need for intervention by the CPU to control the functions.  135 internal event signals can be freely combined for interlinked operation with connected functions.  Event signals from peripheral modules can be used to change the states of output pins (of ports B and E).  Changes in the states of pins (of ports B and E) being used as inputs can be interlinked with the operation of peripheral modules. Page 5 of 179 RX72N Group Table 1.1 1. Overview Outline of Specifications (5/11) Classification Module/Function Description Timers 16-bit timer pulse unit (TPUa)           (16 bits × 6 channels) × 1 unit Maximum of 16 pulse-input/output possible Select from among seven or eight counter-input clock signals for each channel Input capture/output compare function Output of PWM waveforms in up to 15 phases in PWM mode Support for buffered operation, phase-counting mode (two phase encoder input) and cascade-connected operation (32 bits × 2 channels) depending on the channel. PPG output trigger can be generated Capable of generating conversion start triggers for the A/D converters Digital filtering of signals from the input capture pins Event linking by the ELC Multifunction timer pulse unit (MTU3a)  9 channels (16 bits × 8 channels, 32 bits × 1 channel)  Maximum of 28 pulse-input/output and 3 pulse-input possible  Select from among 14 counter-input clock signals for each channel (PCLKA/1, PCLKA/ 2, PCLKA/4, PCLKA/8, PCLKA/16, PCLK/A32, PCLKA/64, PCLKA/256, PCLKA/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD, MTIOC1A) 14 of the signals are available for channel 0, 11 are available for channels 1, 3, 4, 6 to 8, 12 are available for channel 2, and 10 are available for channel 5.  Input capture function  39 output compare/input capture registers  Counter clear operation (synchronous clearing by compare match/input capture)  Simultaneous writing to multiple timer counters (TCNT)  Simultaneous register input/output by synchronous counter operation  Buffered operation  Support for cascade-connected operation  43 interrupt sources  Automatic transfer of register data  Pulse output mode Toggle/PWM/complementary PWM/reset-synchronized PWM  Complementary PWM output mode Outputs non-overlapping waveforms for controlling 3-phase inverters Automatic specification of dead times PWM duty cycle: Selectable as any value from 0% to 100% Delay can be applied to requests for A/D conversion. Non-generation of interrupt requests at peak or trough values of counters can be selected. Double buffer configuration  Reset synchronous PWM mode Three phases of positive and negative PWM waveforms can be output with desired duty cycles.  Phase-counting mode: 16-bit mode (channels 1 and 2); 32-bit mode (channels 1 and 2)  Counter functionality for dead-time compensation  Generation of triggers for A/D converter conversion  A/D converter start triggers can be skipped  Digital filter function for signals on the input capture and external counter clock pins  PPG output trigger can be generated  Event linking by the ELC Port output enable 3 (POE3a)  Control of the high-impedance state of the MTU waveform output pins  5 pins for input from signal sources: POE0#, POE4#, POE8#, POE10#, POE11#  Initiation on detection of short-circuited outputs (detection of simultaneous PWM output to the active level)  Initiation by oscillation-stoppage detection or software  Additional programming of output control target pins is enabled R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 6 of 179 RX72N Group Table 1.1 1. Overview Outline of Specifications (6/11) Classification Module/Function Description Timers General PWM timer (GPTW)  32 bits × 4 channels (GPTW0 to GPTW3)  Counting up or down (sawtooth-wave), counting up and down (triangle-wave) selectable for all channels  Clock sources independently selectable for each channel  2 input/output pins per channel  2 output compare/input capture registers per channel  For the 2 output compare/input capture registers of each channel, 4 registers are provided as buffer registers and are capable of operating as comparison registers when buffering is not in use.  In output compare operation, buffer switching can be at crests or troughs, enabling the generation of laterally asymmetrically PWM waveforms.  Registers for setting up frame intervals on each channel (with capability for generating interrupts on overflow or underflow)  Generation of dead times in PWM operation  Capable of synchronous start, stop, or clearing of counter for any channel  Capable of a start, stop, clearing, or up-/down-counting of the counter supporting input level comparison  Capable of a start, stop, clearing, or up-/down-counting of the counter supporting maximum of 4 external triggers  Output pin disabling function by a dead time error or a short circuit detection among output pins  Capable of generating conversion start triggers for the A/D converters as well as monitoring external pins for a start timing of conversion.  Capable of outputting events, such as compare-match from A to F and overflow/ underflow, to ELC  Capable of using noise filter of input capture Port output enable for GPTW (POEG)     Programmable pulse generator (PPG)  (4 bits × 4 groups) × 2 units  Pulse output with the MTU or TPU output as a trigger  Maximum of 32 pulse-output possible 8-bit timers (TMR)  (8 bits × 2 channels) × 2 units  Select from among seven internal clock signals (PCLKB/1, PCLKB/2, PCLKB/8, PCLKB/32, PCLKB/64, PCLKB/1024, PCLKB/8192) and one external clock signal  Capable of output of pulse trains with desired duty cycles or of PWM signals  The 2 channels of each unit can be cascaded to create a 16-bit timer  Generation of triggers for A/D converter conversion  Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12  Event linking by the ELC Compare match timer (CMT)  (16 bits × 2 channels) × 2 units  Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128, PCLKB/512) Compare match timer W (CMTW)  (32 bits × 1 channel) × 2 units  Compare-match, input-capture input, and output-comparison output are available.  Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128, PCLKB/512)  Interrupt requests can be output in response to compare-match, input-capture, and output-comparison events.  Event linking by the ELC Realtime clock (RTCd)*1        Controlling the output disable for GPTW waveform output Initiation by input level detection of GTETRG pins Initiation by output disable request from GPTW Initiation by detection of oscillation stop or by software Clock sources: Main clock, sub-clock Selection of the 32-bit binary count in time count/second unit possible Clock and calendar functions Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt Battery backup operation Time-capture facility for three values Event linking by the ELC Watchdog timer (WDTA)  14 bits × 1 channel  Select from among 6 counter-input clock signals (PCLKB/4, PCLKB/64, PCLKB/128, PCLKB/512, PCLKB/2048, PCLKB/8192) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 7 of 179 RX72N Group Table 1.1 1. Overview Outline of Specifications (7/11) Classification Module/Function Description Timers Independent watchdog timer (IWDTa)  14 bits × 1 channel  Counter-input clock: IWDT-dedicated on-chip oscillator  Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64, dedicated clock/128, dedicated clock/256  Window function: The positions where the window starts and ends are specifiable (the window defines the timing with which refreshing is enabled and disabled).  Event linking by the ELC Communication function Ethernet controller (ETHERC)          2 channels Input and output of Ethernet/IEEE 802.3 frames Transfer at 10 or 100 Mbps Full- and half-duplex modes MII (Media Independent Interface) and RMII (Reduced Media Independent Interface) as defined in IEEE 802.3u Detection of Magic PacketsTM*2 or output of a “wake-on-LAN” signal (WOL) Compliance with flow control as defined in IEEE 802.3x standards Filtering of multicast frames is supported. Frame data can be directly transferred between 2 channels by cut-through switching. PHY management interface (PMGI)  2 channels  This module is compliant with the MII (Media Independent Interface) as defined in the IEEE 802.3u standard.  Transmission and reception of management frames through PHY-LSI chips having an MII or RMII interface is supported.  Alleviates load on the CPU by shifting it to dedicated hardware  The timing of management data is adjustable.  Preambles can be deleted. PTP module for the ethernet controller (EPTPCb)  In connection with the Ethernet controller (ETHERC), this module is compliant with the IEEE1588 standard.  Matching with time stamps can be used to trigger counting by the MTU and GPTW. DMA controller for ethernet controller (EDMACa)  3 channels (each EDMAC determines the order of priority by a round-robin algorithm) For ETHERC: 2 channels, for EPTPC: 1 channel  Alleviation of CPU load by the descriptor control method  Transmission FIFO: 2 Kbytes; Reception FIFO: 4 Kbytes USB 2.0 FS host/ function module (USBb)         R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Includes a UDC (USB Device Controller) and transceiver for USB 2.0 FS One port Compliance with the USB 2.0 specification Transfer rate: Full speed (12 Mbps), low speed (1.5 Mbps) (host only) Both self-power mode and bus-power mode are supported OTG (On the Go) operation is possible (low-speed is not supported) Incorporates 2 Kbytes of RAM as a transfer buffer External pull-up and pull-down resistors are not required Page 8 of 179 RX72N Group Table 1.1 1. Overview Outline of Specifications (8/11) Classification Module/Function Description Communication function Serial communications interfaces (SCIj, SCIi, SCIh)  13 channels (SCIj: 7 channels + SCIi: 5 channels + SCIh: 1 channel)  SCIj, SCIi, SCIh Serial communications modes: Asynchronous, clock synchronous, and smart-card interface Multi-processor function On-chip baud rate generator allows selection of the desired bit rate Choice of LSB-first or MSB-first transfer Start-bit detection: Level or edge detection is selectable. Simple I2C Simple SPI 7- to 9-bit transfer mode Bit rate modulation Double-speed mode Detecting matches of data is supported (other than for SCI12)  SCIj, SCIh Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12 Event linking by the ELC (only on channel 5)  SCIh Supports the serial communications protocol, which contains the start frame and information frame Supports the LIN format  SCIi Data can be transmitted or received in sequence by the 16-byte FIFO buffers of the transmission and reception unit I2C bus interface (RIICa)  3 channels (only channel 0 can be used in fast-mode plus) Communication formats I2C bus format/SMBus format Supports the multi-master Max. transfer rate: 1 Mbps (channel 0)  Event linking by the ELC CAN module (CAN)  3 channels  Compliance with the ISO11898-1 specification (standard frame and extended frame)  32 mailboxes per channel Serial peripheral interface (RSPIc)  3 channels  RSPI transfer facility Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four lines) or clock-synchronous operation (three lines) Capable of handling serial transfer as a master or slave  Data formats Switching between MSB first and LSB first The number of bits in each transfer can be changed to any number of bits from 8 to 16, or to 20, 24, or 32 bits. 128-bit buffers for transmission and reception Up to four frames can be transmitted or received in a single transfer operation (with each frame having up to 32 bits) Transit/receive data can be swapped in byte units  Buffered structure Double buffers for both transmission and reception  RSPCK can be stopped with the receive buffer full for master reception.  Event linking by the ELC Quad serial peripheral interface (QSPI)  1 channel  Connectable with serial flash memory equipped with multiple input and output lines (i.e. for single, dual, or quad operation)  Programmable bit length and selectable active sense and phase of the clock signal  Sequential execution of transfer  LSB or MSB first is selectable R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 9 of 179 RX72N Group Table 1.1 Classification 1. Overview Outline of Specifications (9/11) Module/Function Description Extended serial sound interface (SSIE)      SD host interface (SDHI)  1 channel  Transfer speed: Supports high-speed mode (25 MB/s) and default speed mode (12.5 MB/s)  One interface for SD memory and I/O cards (supporting 1- and 4-bit SD buses)  SD specifications Part 1: Physical Layer Specification Ver. 3.01 compliant (DDR not supported) Part E1: SDIO Specification Ver. 3.00  Error checking: CRC7 for commands and CRC16 for data  Interrupt requests: Card access interrupt, SDIO access interrupt, card detection interrupt, interrupt of SD buffer access  DMA transfer requests: SD_BUF write and SD_BUF read  Support for card detection and write protection MMC host interface (MMCIF)       The arithmetic unit for trigonometric functions (TFU)  Sine, cosine, arctangent, x 2 + y 2 Simultaneous calculation of sine and cosine Simultaneous calculation of arctangent and x 2 + y 2 Parallel data capture unit (PDC)  1 channel  Acquisition of synchronization through external 8-bit horizontal and vertical synchronization signals  Setting of the image size when clipping of the output for a one-frame image is required Graphic-LCD controller (GLCDC)     1 channel Various data formats and LCD panels are supported Superposition of 3 planes (single-color background, graphic 1, graphic 2) 32- and 16-bpp graphics data and 8-, 4-, and 1-bit CLUT data formats are supported 2D drawing engine (DRW2D)     1 channel Vector drawing (straight lines, triangles, and circles) Bit blitting (with support for filling, copying, stretching, and rotation) Bus master function for input and output of frame buffer data 32-, 16-, and 8-bit pixel graphics data are supported Bus master function for input of texture data Input of texture data (32, 24, 16, 8, 4, 2, or 1 bit) are supported. Run length encoding is supported A CLUT is installed and index data can be converted into color data Two rendering modes are supported (register mode and display list mode) Performance counting Interrupts in response to completion of rendering and processing of the display list 2 channels Full-duplex transmission (only for channel 0) Various types of serial audio formatting are supported. Master and slave operations are supported. The bit-clock frequency is selectable from among 13 frequencies (1/1, 1/2, 1/4, 1/6, 1/8, 1/12, 1/16, 1/24, 1/32, 1/48, 1/64, 1/96, or 1/128).  Data formats with 8, 16, 18, 20, 22, 24, and 32 bits are supported.  32-stage FIFO buffers for transmission and reception  Stopping or not stopping the SSILRCK signal on stopping of data transmission is selectable. 1 channel Transfer speed: Data transfer mode (30 MB/s), backward compatible mode (25 MB/s) Compliant with JEDEC STANDARD JESD84-A441 (DDR is not supported) Interface for Multimedia Cards (MMCs) Data buses: Support for 1-, 4-, and 8-bit MMC buses Interrupt requests: Card detection interrupt, error/timeout interrupt, normal operation interrupt, interrupt of MMCIF buffer access  DMA transfer requests: CE_DATA write and CE_DATA read  Support for card detection, boot operation, high priority interrupt (HPI)     R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 10 of 179 RX72N Group Table 1.1 Classification 1. Overview Outline of Specifications (10/11) Module/Function Description 12-bit A/D converter (S12ADFa)  12 bits × 2 units (unit 0: 8 channels; unit 1: 21 channels)  12-bit resolution (switchable between 8, 10, and 12 bits)  Conversion time 0.48 µs per channel (for 12-bit conversion) 0.45 µs per channel (for 10-bit conversion) 0.42 µs per channel (for 8-bit conversion)  Operating mode Scan mode (single scan mode, continuous scan mode, or 3 group scan mode) Group priority control (only for 3 group scan mode)  Sample-and-hold function Common sample-and-hold circuit included In addition, channel-dedicated sample-and-hold function (3 channels: in unit 0 only) included  Sampling variable Sampling time can be set up for each channel.  Digital comparison Method: Comparison to detect voltages above or below thresholds and window comparison Measurement: Comparison of two results of conversion or comparison of a value in the comparison register and a result of conversion  Self-diagnostic function The self-diagnostic function internally generates three analog input voltages (unit 0: VREFL0, VREFH0 × 1/2, VREFH0; unit 1: AVSS1, AVCC1 × 1/2, AVCC1)  Double trigger mode (A/D conversion data duplicated)  Detection of analog input disconnection  Three ways to start A/D conversion Software trigger, timer (MTU, TMR, TPU) trigger, external trigger  Event linking by the ELC 12-bit D/A converter (R12DAa)  2 channels  12-bit resolution  Output voltage: 0.2 V to AVCC1 – 0.2 V (buffered output), 0 V to AVCC1 (unbuffered output)  Buffered output or unbuffered output can be selected.  Event linking by the ELC Temperature sensor  1 channel  Relative precision: ± 1°C  The voltage of the temperature is converted into a digital value by the 12-bit A/D converter (unit 1). Safety Memory protection unit (MPU)  Protection area: Eight areas (max.) can be specified in the range from 0000 0000h to FFFF FFFFh.  Minimum protection unit: 16 bytes  Reading from, writing to, and enabling the execution access can be specified for each area.  An access exception occurs when the detected access is not in the permitted area. Trusted Memory (TM) Function  Programs in the TM target area in the code flash memory are protected against reading  Instruction fetching by the CPU is the only form of access to these areas when the TM function is enabled. Register write protection function  Protects important registers from being overwritten for in case a program runs out of control. CRC calculator (CRCA)  Generation of CRC codes for 8-/32-bit data 8-bit data Selectable from the following three polynomials X8 + X2 + X + 1, X16 + X15 + X2 + 1, X16 + X12 + X5 + 1 32-bit data Selectable from the following two polynomials X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1, X32 + X28 + X27 + X26 + X25 + X23 + X22 + X20 + X19 + X18 + X14 + X13 + X11 + X10 + X9 + X8 + X6 + 1  Generation of CRC codes for use with LSB-first or MSB-first communications is selectable Main clock oscillation stop detection  Main clock oscillation stop detection: Available R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 11 of 179 RX72N Group Table 1.1 1. Overview Outline of Specifications (11/11) Classification Module/Function Description Safety Clock frequency accuracy measurement circuit (CAC)  Monitors the clock output from the main clock oscillator, sub-clock oscillator, low- and high-speed on-chip oscillators, IWDT-dedicated on-chip oscillator, USB clock, EthernetPHY external clock, and PCLKB, and generates interrupts when the setting range is exceeded. Data operation circuit (DOC)  The function to compare, add, or subtract 16-bit data Trusted Secure IP (TSIP)*3  Security algorithm Common key encryption: AES (compliant with NIST FIPS PUB 197), TDES, ARC4 Non-common key encryption: RSA  Other features TRNG (true-random number generator) Hash value generation: SHA1, SHA224, SHA256, MD5, GHASH Prevention of the illicit copying of keys Encryption function Operating frequency Up to 240 MHz Power supply voltage VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0, VBATT = 2.0 to 3.6 V Operating temperature D-version: –40 to +85°C G-version: –40 to +105°C Package 224-pin LFBGA (PLBG0224GA-A) 176-pin LFBGA (PLBG0176GA-A) 176-pin LFQFP (PLQP0176KB-C) 145-pin TFLGA (PTLG0145KA-A) 144-pin LFQFP (PLQP0144KA-B) 100-pin LFQFP (PLQP0100KB-B) On-chip debugging system  E1 emulator (JTAG and FINE interfaces) Note 1. When the realtime clock is not used, initialize the registers in the time clock according to description in section 33.6.7, Initialization Procedure When the Realtime Clock is Not to be Used in the User’s Manual: Hardware. Note 2. Magic PacketTM is a registered trademark of Advanced Micro Devices, Inc. Note 3. The product part number differs according to whether or not the MCU includes the encryption function. R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 12 of 179 RX72N Group Table 1.2 1. Overview Comparison of Functions for Different Packages (1/2) Functions RX72N Package 224 Pins 176 Pins 144 Pins/145 Pins External bus External bus width DMA DMA controller Ch. 0 to 7 Data transfer controller Available SDRAM area controller EXDMA controller Timers 32 bits/16 bits/8 bits 16 bits/8 bits Available Ch. 0 and 1 Ch. 0 to 5 Multi-function timer pulse unit 3 Ch. 0 to 8 General PWM timer Ch. 0 to 3 Port output enable 3 Available Port output enable for GPTW Available 8-bit timers Compare match timer Compare match timer W Ch. 0 and 1 Ch. 0 to 3 Ch. 0 to 3 Ch. 0 and 1 Realtime clock Communication function Not available 16-bit timer pulse unit Programmable pulse generator Available Watchdog timer Available Independent watchdog timer Available Ethernet controller Ch. 0 and 1 Ch. 0 PHY management interface Ch. 0 and 1 Ch. 0 PTP controller for the ethernet controller DMA controller for the ethernet controller Available Ch. 0 and 1 (ETHERC) and 2 (EPTPC) USB2.0 FS host/function module Ch. 0 Ch. 0 to 6 Ch. 0 to 3, 5, and 6 Serial communications interfaces (SCIi) Ch. 7 to 11 Ch. 8 to 11 Ch. 12 I2C bus interfaces Ch. 0 to 2 Serial peripheral interface Ch. 0 to 2 CAN module Ch. 0 to 2 Ch. 0 and 1 Quad serial peripheral interface Ch. 0 Expansion serial sound interface Ch. 0 and 1 SD host interface Ch. 0 Multimediacard interface Ch. 0 Parallel data capture unit 12-bit A/D converter Ch. 0 (ETHERC) and 2 (EPTPC) Serial communications interfaces (SCIj) Serial communications interfaces (SCIh) Graphics 100 Pins Available Not available Graphic-LCD controller Available 2D drawing engine Available Unit 0 Unit 1 12-bit D/A converter AN000 to AN007 (8 channels) AN100 to AN120 (21 channels) AN100 to AN113 (14 channels) Ch. 0 and 1 Ch. 1 Temperature sensor Available Arithmetic unit for trigonometric functions Available R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 13 of 179 RX72N Group Table 1.2 1. Overview Comparison of Functions for Different Packages (2/2) Functions RX72N Package 224 Pins 176 Pins 144 Pins/145 Pins CRC calculator Available Data operation circuit Available Clock frequency accuracy measurement circuit Available Trusted Secure IP Event link controller R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 100 Pins Available/Not available Available Page 14 of 179 RX72N Group 1.2 1. Overview List of Products Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part no. Table 1.3 List of Products (1/2) Code Flash Memory Capacity RAM Capacity Data Flash Memory Capacity Operating Frequency (Max.) Encryption Module Operating temperature (°C) Not available –40 to +85 Group Part No. Package RX72N (D-version) R5F572NNDDFC PLQP0176KB-C 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz R5F572NNHDFC PLQP0176KB-C 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +85 R5F572NDDDFC PLQP0176KB-C 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Not available –40 to +85 R5F572NDHDFC PLQP0176KB-C 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +85 R5F572NNDDFB PLQP0144KA-B 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz Not available –40 to +85 R5F572NNHDFB PLQP0144KA-B 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +85 R5F572NDDDFB PLQP0144KA-B 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Not available –40 to +85 R5F572NDHDFB PLQP0144KA-B 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +85 R5F572NNDDFP PLQP0100KB-B 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz Not available –40 to +85 R5F572NNHDFP PLQP0100KB-B 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +85 R5F572NDDDFP PLQP0100KB-B 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Not available –40 to +85 RX72N (G-version) R5F572NDHDFP PLQP0100KB-B 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +85 R5F572NNDDBD PLBG0224GA-A 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz Not available –40 to +85 R5F572NNHDBD PLBG0224GA-A 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +85 R5F572NDDDBD PLBG0224GA-A 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Not available –40 to +85 R5F572NDHDBD PLBG0224GA-A 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +85 R5F572NNDDBG PLBG0176GA-A 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz Not available –40 to +85 R5F572NNHDBG PLBG0176GA-A 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +85 R5F572NDDDBG PLBG0176GA-A 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Not available –40 to +85 R5F572NDHDBG PLBG0176GA-A 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +85 R5F572NNDDLK PTLG0145KA-A 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz Not available –40 to +85 R5F572NNHDLK PTLG0145KA-A 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +85 R5F572NDDDLK PTLG0145KA-A 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Not available –40 to +85 R5F572NDHDLK PTLG0145KA-A 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +85 R5F572NNDGFC PLQP0176KB-C 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz Not available –40 to +105 R5F572NNHGFC PLQP0176KB-C 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +105 R5F572NDDGFC PLQP0176KB-C 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Not available –40 to +105 R5F572NDHGFC PLQP0176KB-C 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +105 R5F572NNDGFB PLQP0144KA-B 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz Not available –40 to +105 R5F572NNHGFB PLQP0144KA-B 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +105 R5F572NDDGFB PLQP0144KA-B 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Not available –40 to +105 R5F572NDHGFB PLQP0144KA-B 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +105 R5F572NNDGFP PLQP0100KB-B 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz Not available –40 to +105 R5F572NNHGFP PLQP0100KB-B 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +105 R5F572NDDGFP PLQP0100KB-B 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Not available –40 to +105 R5F572NDHGFP PLQP0100KB-B 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +105 R5F572NNDGBD PLBG0224GA-A 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz Not available –40 to +105 R5F572NNHGBD PLBG0224GA-A 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +105 R5F572NDDGBD PLBG0224GA-A 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Not available –40 to +105 R5F572NDHGBD PLBG0224GA-A 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +105 R5F572NNDGBG PLBG0176GA-A 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz Not available –40 to +105 R5F572NNHGBG PLBG0176GA-A 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +105 R5F572NDDGBG PLBG0176GA-A 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Not available –40 to +105 R5F572NDHGBG PLBG0176GA-A 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +105 R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 15 of 179 RX72N Group Table 1.3 1. Overview List of Products (2/2) Code Flash Memory Capacity RAM Capacity Data Flash Memory Capacity Operating Frequency (Max.) Encryption Module Operating temperature (°C) –40 to +105 Group Part No. Package RX72N (G-version) R5F572NNDGLK PTLG0145KA-A 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz Not available R5F572NNHGLK PTLG0145KA-A 4 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +105 R5F572NDDGLK PTLG0145KA-A 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Not available –40 to +105 R5F572NDHGLK PTLG0145KA-A 2 Mbytes 1 Mbyte 32 Kbytes 240 MHz Available –40 to +105 R 5 F 5 7 2 N N D D B D Package type, number of pins, and pin pitch BD: LFBGA/224/0.80 FC: LFQFP/176/0.50 BG: LFBGA/176/0.80 FB : LFQFP/144/0.50 LK : TFLGA/145/0.50 FP : LFQFP/100/0.50 D : Operating peripheral temperature: –40 to +85°C G : Operating peripheral temperature: –40 to +105°C D : Encryption module not included H : Encryption module included Code flash memory, RAM, and data flash memory capacity N : 4 Mbytes/1 Mbyte/32 Kbytes D : 2 Mbytes/1 Mbyte/32 Kbytes Group name RX72N Group Series name RX700 Series Type of memory F : Flash memory version Renesas MCU Renesas semiconductor product Figure 1.1 How to Read the Product Part Number R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 16 of 179 RX72N Group 1.3 1. Overview Block Diagram DMAC × 8 channels DTC EDMAC × 3 channels GLCDC DRW2D RAM Internal main bus 2 Operand bus ECCRAM Instruction bus Expansion RAM ROM CAC: ICU: BSC: MPU: DMAC: EXDMAC: DTC: ELC: MTU: POE3: GPTW: POEG: TPU: PPG: TMR: CMT: CMTW: RTC: WDT: IWDT: ETHERC: Internal main bus 1 Clock generation circuit CAC ICU ELC MTU × 9 channels POE3 GPTW × 4 channels POEG TPU × 6 channels (unit 0) PPG (unit 0) PPG (unit 1) TMR × 2 channels (unit 0) TMR × 2 channels (unit 1) CMT × 2 channels (unit 0) CMT × 2 channels (unit 1) CMTW × 1 channel (unit 0) CMTW × 1 channel (unit 1) RTC WDT IWDT ETHERC × 2 channels EPTPC PMGI × 2 channels USB × 1 port SCIh × 1 channel SCIi × 5 channels SCIj × 7 channels RIIC × 3 channels CAN × 3 channels SSIE × 2 channels RSPI × 3 channels QSPI CRC SDHI MMCIF PDC TFU Trusted Secure IP*1 12-bit A/D converter × 8 channels (unit 0) 12-bit A/D converter × 21 channels (unit 1) 12-bit D/A converter × 2 channels Temperature sensor DOC Standby RAM Data flash ROM Cache RX CPU MPU Internal peripheral buses 1 to 6 Figure 1.2 shows a block diagram. EXDMAC Clock frequency accuracy measurement circuit Interrupt controller Bus controller Memory protection unit DMA controller EXDMA controller Data transfer controller Event link controller Multi-function timer pulse unit 3 Port output enable 3 General PWM timer GPTW port output enable 16-bit timer pulse unit Programmable pulse unit 8-bit timer Compare match timer Compare match timer W Realtime clock Watchdog timer Independent watchdog timer Ethernet controller BSC External bus Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port B Port C Port D Port E Port F Port G Port H Port J Port K Port L Port M Port N Port Q EPTPC: PTP module for the ethernet controller EDMAC: DMA controller for the ethernet controller PMGI: Phy management interface USB: USB2.0 FS host/function module SCIj, SCIi, SCIh: Serial communications interface RIIC: I2C-bus interface CAN: CAN module SSIE: Serial sound interface enhanced RSPI: Serial communications interface QSPI: Quad serial peripheral interface CRC: CRC calculator SDHI: SD host interface MMCIF: MultiMediaCard interface PDC: Parallel data capture unit GLCDC: Graphic LCD controller DRW2D: 2D drawing engine TFU: Arithmetic unit for trigonometric functions Trusted Secure IP: Trusted secure IP*1 DOC: Data operation circuit Note 1. Optional Figure 1.2 Block Diagram R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 17 of 179 RX72N Group 1.4 1. Overview Pin Functions Table 1.4 lists the pin functions. Table 1.4 Pin Functions (1/8) Classifications Pin Name I/O Description Digital power supply VCC Input Power supply pin. Connect this pin to the system power supply. Connect the pin to VSS via a 0.1-µF multilayer ceramic capacitor. The capacitor should be placed close to the pin. VCL Input Connect this pin to VSS via a 0.22-µF multilayer ceramic capacitor. The capacitor should be placed close to the pin. VSS Input Ground pin. Connect it to the system power supply (0 V). VBATT Input Backup power pin XTAL Output Input/output pins for a crystal resonator. An external clock signal can be input through the EXTAL pin. Clock EXTAL Input BCLK Output Outputs the external bus clock for external devices. SDCLK Output Outputs the SDRAM-dedicated clock. Input/output pins for the sub-clock oscillator. Connect a crystal resonator between XCOUT and XCIN. XCOUT Output XCIN Input CLKOUT Output Clock output pin. Clock frequency accuracy measurement CACREF Input Reference clock input pin for the clock frequency accuracy measurement circuit Operating mode control MD Input Input pin for setting the operating mode. The signal level on this pin must not be changed during operation. UB Input USB boot mode enable pin UPSEL Input Selects the power supply method in USB boot mode. The low level selects self-power mode and the high level selects bus power mode. RES# Input Reset signal input pin. This MCU enters the reset state when this signal goes low. EMLE Input Input pin for the on-chip emulator enable signal. When the onchip emulator is used, this pin should be driven high. When not used, it should be driven low. BSCANP Input Boundary scan enable pin. Boundary scan is enabled when this pin goes high. When not used, it should be driven low. FINED I/O FINE interface pin TRST# Input TMS Input On-chip emulator or boundary scan pins. When the EMLE pin is driven high, these pins are dedicated for the on-chip emulator. TDI Input TCK Input TDO Output TRCLK Output This pin outputs the clock for synchronization with the trace data. TRSYNC, TRSYNC1 Output These pins indicate that output from the TRDATA0 to TRDATA7 pins is valid. TRDATA0 to TRDATA7 Output These pins output the trace information. Address bus A0 to A23 Output Output pins for the address Data bus D0 to D31 I/O Input and output pins for the bidirectional data bus Multiplexed bus A0/D0 to A15/D15 I/O Address/data multiplexed bus System control On-chip emulator R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 18 of 179 RX72N Group Table 1.4 1. Overview Pin Functions (2/8) Classifications Pin Name I/O Description Bus control RD# Output Strobe signal which indicates that reading from the external bus interface space is in progress WR# Output Strobe signal which indicates that writing to the external bus interface space is in progress, in 1-write strobe mode WR0# to WR3# Output Strobe signals which indicate that either group of data bus pins (D7 to D0, D15 to D8, D23 to D16 and D31 to D24) is valid in writing to the external bus interface space, in byte strobe mode BC0# to BC3# Output Strobe signals which indicate that either group of data bus pins (D7 to D0, D15 to D8, D23 to D16 and D31 to D24) is valid in access to the external bus interface space, in 1-write strobe mode ALE Output Address latch signal when address/data multiplexed bus is selected WAIT# Input Input pin for wait request signals in access to the external space CS0# to CS7# Output Select signals for CS areas SDRAM interface EXDMA controller Interrupt Multi-function timer pulse unit 3 Port output enable 3 CKE Output SDRAM clock enable signal SDCS# Output SDRAM chip select signal RAS# Output SDRAM row address strobe signal CAS# Output SDRAM column address strove signal WE# Output SDRAM write enable pin DQM0 to DQM3 Output SDRAM I/O data mask enable signals EDREQ0, EDREQ1 Input External DMA transfer request pins EDACK0, EDACK1 Output Single address transfer acknowledge signals NMI Input Non-maskable interrupt request pin IRQ0 to IRQ15, IRQ0-DS to IRQ15-DS Input Maskable interrupt request pins MTIOC0A, MTIOC0B, MTIOC0C, MTIOC0D I/O The TGRA0 to TGRD0 input capture input/output compare output/PWM output pins MTIOC1A, MTIOC1B I/O The TGRA1 and TGRB1 input capture input/output compare output/PWM output pins MTIOC2A, MTIOC2B I/O The TGRA2 and TGRB2 input capture input/output compare output/PWM output pins MTIOC3A, MTIOC3B, MTIOC3C, MTIOC3D I/O The TGRA3 to TGRD3 input capture input/output compare output/PWM output pins MTIOC4A, MTIOC4B, MTIOC4C, MTIOC4D I/O The TGRA4 to TGRD4 input capture input/output compare output/PWM output pins MTIC5U, MTIC5V, MTIC5W Input The TGRU5, TGRV5, and TGRW5 input capture input/dead time compensation input pins MTIOC6A, MTIOC6B, MTIOC6C, MTIOC6D I/O The TGRA6 to TGRD6 input capture input/output compare output/PWM output pins MTIOC7A, MTIOC7B, MTIOC7C, MTIOC7D I/O The TGRA7 to TGRD7 input capture input/output compare output/PWM output pins MTIOC8A, MTIOC8B, MTIOC8C, MTIOC8D I/O The TGRA8 to TGRD8 input capture input/output compare output/PWM output pins MTCLKA, MTCLKB, MTCLKC, MTCLKD Input Input pins for external clock signals or for phase counting mode clock signals POE0#, POE4#, POE8#, POE10#, POE11# Input Input pins for request signals to place the MTU in the high impedance state R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 19 of 179 RX72N Group Table 1.4 1. Overview Pin Functions (3/8) Classifications Pin Name I/O Description General PWM timer W GTETRGA, GTETRGB, GTETRGC, GTETRGD Input Input pins for the external trigger signals GTIOC0A to GTIOC3A, GTIOC0B to GTIOC3B I/O Input capture input/output compare output/PWM output pins GTADSM0, GTADSM1 Output Output pins for monitoring A/D conversion start requests. TIOCA0, TIOCB0, TIOCC0, TIOCD0 I/O The TGRA0 to TGRD0 input capture input/output compare output/PWM output pins TIOCA1, TIOCB1 I/O The TGRA1 and TGRB1 input capture input/output compare output/PWM output pins TIOCA2, TIOCB2 I/O The TGRA2 and TGRB2 input capture input/output compare output/PWM output pins TIOCA3, TIOCB3, TIOCC3, TIOCD3 I/O The TGRA3 to TGRD3 input capture input/output compare output/PWM output pins TIOCA4, TIOCB4 I/O The TGRA4 and TGRB4 input capture input/output compare output/PWM output pins TIOCA5, TIOCB5 I/O The TGRA5 and TGRB5 input capture input/output compare output/PWM output pins TCLKA, TCLKB, TCLKC, TCLKD Input Input pins for external clock signals or for phase counting mode clock signals Programmable pulse generator PO0 to PO31 Output Output pins for the pulse signals 8-bit timer TMO0 to TMO3 Output Compare match output pins 16-bit timer pulse unit Compare match timer W Serial communications interface (SCIj) TMCI0 to TMCI3 Input Input pins for external clocks to be input to the counter TMRI0 to TMRI3 Input Input pins for the counter reset TIC0 to TIC3 Input Input pins for CMTW TOC0 to TOC3 Output Output pins for CMTW  Asynchronous mode/clock synchronous mode SCK0 to SCK6 I/O Input/output pins for the clock RXD0 to RXD6 Input Input pins for received data TXD0 to TXD6 Output Output pins for transmitted data CTS0# to CTS6# Input Input pins for controlling the start of transmission and reception RTS0# to RTS6# Output Output pins for controlling the start of transmission and reception SSCL0 to SSCL6 I/O Input/output pins for the I2C clock SSDA0 to SSDA6 I/O Input/output pins for the I2C data SCK0 to SCK6 I/O Input/output pins for the clock SMISO0 to SMISO6 I/O Input/output pins for slave transmission of data  Simple I2C mode  Simple SPI mode SMOSI0 to SMOSI6 I/O Input/output pins for master transmission of data SS0# to SS6# Input Chip-select input pins R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 20 of 179 RX72N Group Table 1.4 1. Overview Pin Functions (4/8) Classifications Pin Name I/O Description Serial communications interface (SCIh)  Asynchronous mode/clock synchronous mode SCK12 I/O Input/output pin for the clock RXD12 Input Input pin for received data TXD12 Output Output pin for transmitted data CTS12# Input Input pin for controlling the start of transmission and reception RTS12# Output Output pin for controlling the start of transmission and reception SSCL12 I/O Input/output pin for the I2C clock SSDA12 I/O Input/output pin for the I2C data  Simple I2C mode  Simple SPI mode SCK12 I/O Input/output pin for the clock SMISO12 I/O Input/output pin for slave transmission of data SMOSI12 I/O Input/output pin for master transmission of data SS12# Input Chip-select input pin RXDX12 Input Input pin for received data TXDX12 Output Output pin for transmitted data SIOX12 I/O Input/output pin for received or transmitted data  Extended serial mode Serial communications interface (SCIi)  Asynchronous mode/clock synchronous mode SCK7 to SCK11 I/O Input/output pins for the clock RXD7 to RXD11 Input Input pins for received data TXD7 to TXD11 Output Output pins for transmitted data CTS7# to CTS11# Input Input pins for controlling the start of transmission and reception RTS7# to RTS11# Output Output pins for controlling the start of transmission and reception SSCL7 to SSCL11 I/O Input/output pins for the I2C clock SSDA7 to SSDA11 I/O Input/output pins for the I2C data  Simple I2C mode  Simple SPI mode I2C bus interface SCK7 to SCK11 I/O Input/output pins for the clock SMISO7 to SMISO11 I/O Input/output pins for slave transmission of data SMOSI7 to SMOSI11 I/O Input/output pins for master transmission of data SS7# to SS11# Input Chip-select input pins SCL0[FM+], SCL1, SCL2, SCL2-DS I/O Input/output pins for clocks. Bus can be directly driven by the N-channel open drain SDA0[FM+], SDA1, SDA2, SDA2-DS I/O Input/output pins for data. Bus can be directly driven by the N-channel open drain R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 21 of 179 RX72N Group Table 1.4 1. Overview Pin Functions (5/8) Classifications Pin Name I/O Description Ethernet controller REF50CK0, REF50CK1 Input 50-MHz reference clocks. These pins input reference signals for transmission/reception timings in RMII mode. RMII0_CRS_DV, RMII1_CRS_DV Input These pins indicate that there are carrier detection signals and valid receive data on RMIIn_RXD1 and RMIIn_RXD0 in RMII mode. RMII0_TXD0, RMII0_TXD1, RMII1_TXD0, RMII1_TXD1 Output 2-bit transmit data in RMII mode RMII0_RXD0, RMII0_RXD1, RMII1_RXD0, RMII1_RXD1 Input 2-bit receive data in RMII mode RMII0_TXD_EN, RMII1_TXD_EN Output Output pins for data transmit enable signals in RMII mode RMII0_RX_ER, RMII1_RX_ER Input These pins indicate an error has occurred during reception of data in RMII mode. ET0_CRS, ET1_CRS Input Carrier detection/data reception enable pins ET0_RX_DV, ET1_RX_DV Input These pins indicate that there are valid receive data on ETn_ERXD3 to ETn_ERXD0. ET0_EXOUT, ET1_EXOUT Output General-purpose external output pins ET0_LINKSTA, ET1_LINKSTA Input Input link status from the PHY-LSI. ET0_ETXD0 to ET0_ETXD3, ET1_ETXD0 to ET1_ETXD3 Output 4 bits of MII transmit data ET0_ERXD0 to ET0_ERXD3, ET1_ERXD0 to ET1_ERXD3 Input 4 bits of MII receive data ET0_TX_EN, ET1_TX_EN Output Transmit enable pins. These pins function as signals indicating that transmit data are ready on ETn_ETXD3 to ETn_ETXD0. ET0_TX_ER, ET1_TX_ER Output Transmit error pins. These pins function as signals notifying the PHY-LSI of an error during transmission. ET0_RX_ER, ET1_RX_ER Input Receive error pins. These pins function as signals to recognize an error during reception. ET0_TX_CLK, ET1_RX_CLK Input Transmit clock pins. These pins input reference signals for output timings from ETn_TX_EN, ETn_ETXD3 to ETn_ETXD0, and ETn_TX_ER. ET0_RX_CLK, ET1_RX_CLK Input Receive clock pins. These pins input reference signals for input timings to ETn_RX_DV, ETn_ERXD3 to ETn_ERXD0, and ETn_RX_ER. ET0_COL, ET1_COL Input Input collision detection signals. ET0_WOL, ET1_WOL Output Receive Magic packets. ET0_MDC, ET1_MDC Output Output reference clock signals for information transfer via ETn_MDIO. ET0_MDIO, ET1_MDIO I/O Input or output bidirectional signals for exchange of management information between this MCU and the PHY-LSI. CLKOUT25M Output 25-MHz clock output pin for PHY clock input PHY management interface EPLSOUT0, EPLSOUT1 Output Pulse output signals for time synchronization PMGI0_MDC, PMGI1_MDC Output Reference clock signals for information transfer by PMGIn_MDIO PMGI0_MDIO, PMGI1_MDIO I/O Bi-directional signals for the exchange of management information between the PHY LSI chip and this MCU R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 22 of 179 RX72N Group Table 1.4 1. Overview Pin Functions (6/8) Classifications Pin Name I/O Description USB 2.0 host/function module VCC_USB Input Power supply pin VSS_USB Input Ground pin USB0_DP I/O Input or output USB transceiver D+ data. USB0_DM I/O Input or output USB transceiver D- data. USB0_EXICEN Output Connect to the OTG power IC. USB0_ID Input Connect to the OTG power IC. USB0_VBUSEN Output USB VBUS power enable pin USB0_OVRCURA/ USB0_OVRCURB Input USB overcurrent pins USB0_VBUS Input USB cable connection/disconnection detection input pin CRX0, CRX1, CRX2, CRX1-DS Input Input pins CAN module Serial peripheral interface Quad serial peripheral interface Serial sound interface enhanced CTX0, CTX1, CTX2 Output Output pins RSPCKA-A/RSPCKA-B/ RSPCKB-A/RSPCKB-B/ RSPCKC-A/RSPCKC-B I/O Clock input/output pins MOSIA-A/MOSIA-B/ MOSIB-A/MOSIB-B/ MOSIC-A/MOSIC-B I/O Input or output data output from the master MISOA-A/MISOA-B/ MISOB-A/MISOB-B/ MISOC-A/MISOC-B I/O Input or output data output from the slave SSLA0-A/SSLA0-B/ SSLB0-A/SSLB0-B/ SSLC0-A/SSLC0-B I/O Input or output pins for slave selection SSLA1-A/SSLA1-B/ SSLB1-A/SSLB1-B/ SSLC1-A/SSLC1-B, SSLA2-A/SSLA2-B/ SSLB2-A/SSLB2-B/ SSLC2-A/SSLC2-B, SSLA3-A/SSLA3-B/ SSLB3-A/SSLB3-B/ SSLC3-A/SSLC3-B Output Output pins for slave selection QSPCLK-A/QSPCLK-B Output QSPI clock output pins QSSL-A/QSSL-B Output QSPI slave output pins QMO-A/QMO-B, QIO0-A/QIO0-B I/O Master transmit data/data 0 QMI-A/QMI-B, QIO1-A/QIO1-B I/O Master input data/data 1 QIO2-A/QIO2-B, QIO3-A/QIO3-B I/O Data 2, data 3 SSIBCK0, SSIBCK1 I/O SSIE serial bit-clock pins SSILRCK0, SSILRCK1 I/O LR clock SSITXD0 Output Serial data output pin SSIRXD0 Input Serial data input pin SSIDATA1 I/O Serial data input/output pin AUDIO_CLK Input External clock pin for audio (input for an oversampling clock) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 23 of 179 RX72N Group Table 1.4 1. Overview Pin Functions (7/8) Classifications Pin Name I/O Description MMC host interface MMC_CLK-A/MMC_CLK-B Output MMC clock pins SD host interface Parallel data capture unit Graphic-LCD controller Realtime clock 12-bit A/D converter 12-bit D/A converter MMC_CMD-A/MMC_CMD-B I/O Command/response pins MMC_D7-A/MMC_D7-B to MMC_D0-A/MMC_D0-B I/O Transmit data/receive data MMC_CD-A/MMC_CD-B Input Card detection pins MMC_RES#-A/MMC_RES#-B Output MMC reset output pins SDHI_CLK-A/SDHI_CLK-B/ SDHI_CLK-C Output SD clock output pins SDHI_CMD-A/SDHI_CMD-B/ SDHI_CMD-C I/O SD command output, response input signal pins SDHI_D3-A/SDHI_D3-B/ SDHI_D3-C to SDHI_D0-A/ SDHI_D0-B/SDHI_D0-C I/O SD data bus pins SDHI_CD Input SD card detection pin SDHI_WP Input SD write-protect signal PIXCLK Input Image transfer clock pin VSYNC Input Vertical synchronization signal pin HSYNC Input Horizontal synchronization signal pin PIXD0 to PIXD7 Input 8-bit image data pins PCKO Output Output pin for dot clock LCD_CLK-A, LCD_CLK-B Output Panel clock output pins LCD_TCON3-A/ LCD_TCON3-B to LCD_TCON0-A/ LCD_TCON0-B Output Control signal output pins LCD_DATA23-A/ LCD_DATA23-B to LCD_DATA0-A/ LCD_DATA0-B Output LCD signal output pins LCD_EXTCLK-A, LCD_EXTCLK-B Input Panel clock source input pins RTCOUT Output Output pin for 1-Hz/64-Hz clock RTCIC0 to RTCIC2 Input Time capture event input pins AN000 to AN007, AN100 to AN120 Input Input pins for the analog signals to be processed by the A/D converter ADTRG0#, ADTRG1# Input Input pins for the external trigger signals that start the A/D conversion ANEX0 Output Extended analog output pin ANEX1 Input Extended analog input pin DA0, DA1 Output Output pins for the analog signals to be processed by the D/A converter R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 24 of 179 RX72N Group Table 1.4 1. Overview Pin Functions (8/8) Classifications Pin Name I/O Description Analog power supply AVCC0 Input Analog voltage supply pin for the 12-bit A/D converter (unit 0). Connect this pin to a branch from the VCC power supply. Connect the pin to AVSS0 via a 0.1-µF multilayer ceramic capacitor. The capacitor should be placed close to the pin. AVSS0 Input Analog ground pin for the 12-bit A/D converter (unit 0). Connect this pin to a branch from the VSS ground power supply. Connect the pin to AVCC0 via a 0.1-µF multilayer ceramic capacitor. The capacitor should be placed close to the pin. VREFH0 Input Analog reference voltage supply pin for the 12-bit A/D converter (unit 0). Connect this pin to VCC if the 12-bit A/D converter is not to be used. VREFL0 Input Analog reference ground pin for the 12-bit A/D converter (unit 0). Connect this pin to VSS if the 12-bit A/D converter is not to be used. AVCC1 Input Analog voltage supply and reference voltage supply pin for the 12-bit A/D converter (unit 1) and D/A converter. This pin also supplies the analog voltage to the temperature sensor. Connect this pin to a branch from the VCC power supply. Connect the pin to AVSS1 via a 0.1-µF multilayer ceramic capacitor. The capacitor should be placed close to the pin. AVSS1 Input Analog voltage supply and reference voltage supply pin for the 12-bit A/D converter (unit 1) and D/A converter. This pin also supplies the analog ground voltage to the temperature sensor. Connect this pin to a branch from the VSS ground power supply. Connect the pin to AVCC1 via a 0.1-µF multilayer ceramic capacitor. The capacitor should be placed close to the pin. P00 to P03, P05, P07 I/O 6-bit input/output pins P10 to P17 I/O 8-bit input/output pins I/O ports Note: P20 to P27 I/O 8-bit input/output pins P30 to P37 I/O 8-bit input/output pins (P35: input pin) P40 to P47 I/O 8-bit input/output pins P50 to P57 I/O 8-bit input/output pins P60 to P67 I/O 8-bit input/output pins P70 to P77 I/O 8-bit input/output pins P80 to P87 I/O 8-bit input/output pins P90 to P97 I/O 8-bit input/output pins PA0 to PA7 I/O 8-bit input/output pins PB0 to PB7 I/O 8-bit input/output pins PC0 to PC7 I/O 8-bit input/output pins PD0 to PD7 I/O 8-bit input/output pins PE0 to PE7 I/O 8-bit input/output pins PF0 to PF5 I/O 6-bit input/output pins PG0 to PG7 I/O 8-bit input/output pins PJ0 to PJ3, PJ5 I/O 5-bit input/output pins PH0 to PH7 I/O 8-bit input/output pins PK0 to PK7 I/O 8-bit input/output pins PL0 to PL7 I/O 8-bit input/output pins PM0 to PM7 I/O 8-bit input/output pins PN0 to PN5 I/O 6-bit input/output pins PQ0 to PQ7 I/O 8-bit input/output pins Note the following regarding pin names. For details, refer to section 1.5, Pin Assignments. - We recommend using pins that have a letter (“-A”, “-B”, etc.) to indicate group membership appended to their names as R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 25 of 179 RX72N Group 1. Overview groups. For the RSPI, QSPI, SDHI, MMC, and GLCDC interfaces, the AC portion of the electrical characteristics is measured for each group. - When the pin functions have “-DS” appended to their names, they can also be used as triggers for release from deep software standby. - RIIC pin functions that have [FM+] appended to their names support fast-mode plus. R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 26 of 179 RX72N Group 1.5 1. Overview Pin Assignments 1.5.1 224-Pin LFBGA RX72N Group PLBG0224GA-A (224-pin LFBGA) (Upper Perspective View) A B C D E F G H J K L M N P R 15 P70 PE7 P66 P67 PG4 PG7 PA4 PA5 PA7 P72 PB4 PB6 PB7 PM3 PM5 15 14 PE1 PE4 P65 PG2 PG5 PG6 PA3 PA6 PB0 PB3 PB2 PC0 PC1 PM4 P74 14 13 P62 PE2 PE5 VSS PE6 PG3 PA2 VSS P71 PB5 VCC PM7 PM6 PC2 P75 13 12 P61 P63 VSS PE3 VCC PA0 PA1 VCC PB1 VSS PN4 PL6 P76 PL2 PL4 12 11 PD7 VCC P64 PE0 PQ4 PM1 PM0 PL0 PN5 PM2 P77 PL5 PK2 PC4 PC3 11 10 PG0 PD6 P60 PG1 PQ5 VSS VCC P73 PL1 PL3 PL7 PK0 P80 P82 PC5 10 9 PD3 PD4 P97 PD5 PQ3 PQ6 PN2 PN3 PK3 PK1 P81 P83 PC7 VSS PC6 9 8 P96 P95 VCC VSS PQ1 PN1 PQ2 PQ7 P53*1 P50 P52 P51 VCC P11 P55 8 7 PD2 P94 PD1 P93 PQ0 PK6 RES# PJ3 P15 P10 VCC VSS P56 P57 P54 7 6 PD0 VCC P90 P02 PN0 EMLE PF5 BSCANP PH2 PH1 PJ2 P84 PJ1 VSS_US USB0_D 6 B P 5 P92 P91 VSS P01 P07 PK5 PJ5 P32 P30 PF0 VCC PJ0 P13 VCC_US USB0_D 5 B M 4 P41 P46 P44 P40 P43 PK4 MD/ FINED P33 P31 PH5 P24 VSS P85 P14 P12 4 P42 P05 P03 P00 PF4 VCC P35 PF3 PH4 PF1 P25 P86 P20 P16 3 2 VREFH0 AVCC0 AVCC1 P47 VSS VBATT VSS P34 PF2 PH6 P27 P23 PH0 P17 P87 2 1 1 3 VREFL0 NC AVSS0 AVSS1 P45 VCL XCIN XCOUT XTAL EXTAL PH7 PH3 P26 P22 PK7 P21 A B C D E F G H J K L M N P R Note: This figure indicates the power supply pins and I/O port pins. For the pin configuration, refer to Table 1.5, List of Pin and Pin Functions (224-Pin LFBGA). Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled. Figure 1.3 Pin Assignment (224-Pin LFBGA) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 27 of 179 RX72N Group 1.5.2 1. Overview 176-Pin LFBGA A B C D E F G H J K L M N P R 15 PE2 PE3 P70 P65 P67 VSS VCC PG7 PA6 PB0 P72 PB4 VSS VCC PC1 15 14 PE1 PE0 VSS PE7 PG3 PA0 PA1 PA2 PA7 VCC PB1 PB5 P73 P75 P74 14 13 P63 P64 PE4 VCC PG2 PG4 PG6 PA3 VSS P71 PB3 PB7 PC0 PC2 P76 13 12 P60 VSS P62 PE5 PE6 P66 PG5 PA4 PA5 PB2 PB6 P77 PC3 PC4 P80 12 11 PD6 PG1 VCC P61 P81 P82 PC6 VCC 11 10 P97 PD4 PG0 PD7 PC5 PC7 P83 VSS 10 9 VCC P96 PD3 PD5 P50 P51 P52 P53*1 9 8 P94 PD1 PD2 VSS P55 P54 P10 P11 8 7 VSS P92 PD0 P95 P85 P84 P57 P56 7 6 VCC P91 P90 P93 PJ1 PJ0 VSS_ USB USB0_ DP 6 5 P46 P47 P45 P44 PJ2 P12 VCC_ USB USB0_ DM 5 4 P42 P41 P43 P00 VSS BSCANP PF4 P35 PF3 PF1 P25 P86 P15 P14 P13 4 3 VREFL0 P40 VREFH0 P03 PF5 PJ3 MD/ FINED RES# P34 PF2 PF0 P24 P22 P87 P16 3 2 AVCC0 P07 AVCC1 P02 EMLE VCL XCOUT VSS VCC P32 P30 P26 P23 P17 P20 2 1 AVSS0 P05 AVSS1 P01 PJ5 VBATT XCIN XTAL EXTAL P33 P31 P27 VCC VSS P21 1 A B C D E F G H J K L M N P R RX72N Group PTBG0176GA-A (176-pin LFBGA) (Upper Perspective View) Note: This figure indicates the power supply pins and I/O port pins. For the pin configuration, refer to Table 1.6, List of Pin and Pin Functions (176-Pin LFBGA). Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled. Figure 1.4 Pin Assignment (176-Pin LFBGA) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 28 of 179 RX72N Group 176-Pin LFQFP 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 133 88 134 87 135 86 136 85 137 84 138 83 139 82 140 81 141 80 142 79 143 78 144 77 145 76 146 75 147 74 148 73 149 72 150 71 RX72N Group PLQP0176KB-C (176-pin LFQFP) (Top view) 151 152 153 154 155 156 157 158 70 69 68 67 66 65 64 63 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P74 P75 PC2 P76 P77 PC3 PC4 P80 P81 P82 PC5 PC6 PC7 VCC P83 VSS P50 P51 P52 P53*1 P10 P11 P54 P55 P56 P57 P84 P85 PJ0 PJ1 PJ2 VSS_USB USB0_DP USB0_DM VCC_USB P12 P13 P14 P15 P86 P16 P87 P17 P20 AVSS0 P05 AVCC1 P03 AVSS1 P02 P01 P00 PF5 EMLE PJ5 VSS PJ3 VCL VBATT NC PF4 MD/FINED XCIN XCOUT RES# P37/XTAL VSS P36/EXTAL VCC P35 P34 P33 P32 PF3 PF2 P31 P30 PF1 PF0 P27 P26 P25 VCC P24 VSS P23 P22 P21 20 45 19 46 176 18 47 175 17 48 174 16 49 173 15 50 172 14 51 171 13 52 170 12 53 169 11 54 168 10 55 167 9 56 166 8 57 165 7 58 164 6 59 163 5 60 162 4 61 161 3 62 160 2 159 1 PE2 PE1 PE0 P64 P63 P62 P61 VSS P60 VCC PD7 PG1 PD6 PG0 PD5 PD4 P97 PD3 VSS P96 VCC PD2 P95 PD1 P94 PD0 P93 P92 P91 VSS P90 VCC P47 P46 P45 P44 P43 P42 P41 VREFL0 P40 VREFH0 AVCC0 P07 132 PE3 PE4 PE5 VSS P70 VCC PE6 PE7 P65 PG2 P66 PG3 P67 PG4 PA0 VSS PG5 VCC PA1 PG6 PA2 PG7 PA3 PA4 PA5 PA6 PA7 VSS PB0 VCC P71 P72 PB1 PB2 PB3 PB4 PB5 PB6 PB7 P73 VSS PC0 VCC PC1 1.5.3 1. Overview Note: This figure indicates the power supply pins and I/O port pins. For the pin configuration, refer to Table 1.7, List of Pin and Pin Functions (176-Pin LFQFP). Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled. Figure 1.5 Pin Assignment (176-Pin LFQFP) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 29 of 179 RX72N Group 1.5.4 1. Overview 145-Pin TFLGA A B C D E F G H J K L M N 13 PE3 PE4 VSS PE6 P67 PA2 PA4 PA7 PB1 PB5 VSS VCC P74 13 12 PE1 PE2 P70 PE5 P65 PA1 VCC PB0 PB2 PB6 P73 PC1 P75 12 11 P62 P61 PE0 VCC P66 VSS PA6 P71 PB4 PB7 PC2 PC0 PC3 11 10 VSS VCC P63 PE7 PA0 PA3 PA5 P72 PB3 P76 PC4 P77 P82 10 9 PD6 PD4 PD7 P64 P80 PC5 P81 PC7 9 8 PD2 PD0 PD3 P60 VCC P83 PC6 VSS 8 7 P92 P91 PD1 PD5 P51 P52 P50 P55 7 6 P90 P47 VSS P93 P53*1 P56 VSS_ USB USB0_ DP 6 5 P45 P43 P46 VCC P44 P54 P13 VCC_ USB USB0_ DM 5 4 P42 VREFL0 P41 P01 EMLE VBATT BSCANP P35 P30 P15 P24 P12 P14 4 3 P40 P05 VREFH0 P03 PJ5 PJ3 MD/ FINED VSS P32 P31 P16 P86 P87 3 2 P07 AVCC0 P02 PF5 VCL XCOUT RES# VCC P33 P26 P23 P17 P20 2 1 AVSS0 AVCC1 AVSS1 P00 VSS XCIN XTAL EXTAL P34 P27 P25 P22 P21 1 A B C D E F G H J K L M N RX72N Group PTLG0145KA-A (145-pin TFLGA) (Upper Perspective View) Note: This figure indicates the power supply pins and I/O port pins. For the pin configuration, refer to Table 1.8, List of Pin and Pin Functions (145-Pin TFLGA). Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled. Figure 1.6 Pin Assignment (145-Pin TFLGA) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 30 of 179 RX72N Group PA4 VCC PA5 PA6 PA7 PB0 P71 P72 PB1 PB2 PB3 PB4 PB5 PB6 PB7 P73 VSS PC0 VCC PC1 92 91 90 89 88 87 85 83 81 79 77 76 75 74 73 PA3 VSS 94 78 PA1 PA2 96 80 PA0 97 82 P66 P67 99 84 P65 100 86 PE7 101 93 PE6 102 95 P70 VCC 104 98 PE5 VSS 103 PE4 106 105 PE3 107 144-Pin LFQFP 108 1.5.5 1. Overview PE2 109 PE1 110 71 P75 PE0 111 70 PC2 P64 112 69 P76 P63 113 68 P62 114 67 P77 PC3 P61 VSS 115 66 PC4 116 65 P80 P60 117 64 P81 VCC 118 63 P82 PD7 119 62 PC5 PD6 120 61 PC6 PD5 121 60 PC7 PD4 122 59 PD3 123 58 VCC P83 PD2 124 PD1 PD0 125 P93 127 P92 128 72 RX72N Group PLQP0144KA-B (144-pin LFQFP) (Top view) 126 57 P74 56 VSS P50 55 P51 54 P52 53 P53*1 52 P54 26 27 28 29 30 31 32 33 34 35 36 P31 P30 P27 P26 P25 P24 P23 P22 P21 9 P32 P01 P00 P33 P20 25 37 24 144 P34 P07 P35 P87 P17 23 38 VCC 39 143 22 142 P36/EXTAL P16 21 40 VSS 141 20 P86 P40 VREFH0 AVCC0 P37/XTAL 41 19 P15 140 18 42 17 139 XCIN P14 P41 VREFL0 XCOUT RES# 43 16 138 15 P13 P42 MD/FINED 44 14 137 13 P12 P43 12 VCC_USB 45 PJ3 VCL VBATT 46 136 VSS 135 P44 11 P45 PJ5 USB0_DP USB0_DM 10 47 PF5 EMLE 134 8 P46 7 48 6 133 5 VSS_USB P47 AVSS1 P02 49 4 P56 132 P03 50 3 131 AVCC1 P55 P90 VCC 2 51 1 130 P05 VSS AVSS0 P91 129 Note: This figure indicates the power supply pins and I/O port pins. For the pin configuration, refer to Table 1.9, List of Pin and Pin Functions (144-Pin LFQFP). Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled. Figure 1.7 Pin Assignment (144-Pin LFQFP) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 31 of 179 RX72N Group PE3 PE4 PE5 PE6 PE7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 VSS PB0 VCC PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100-Pin LFQFP PE2 76 50 PE1 77 49 PC2 PC3 PE0 78 48 PC4 PD7 79 47 PC5 PD6 80 46 PC6 PD5 81 45 PC7 PD4 82 44 P50 PD3 83 43 P51 PD2 84 42 P52 PD1 85 41 P53*1 PD0 86 40 P54 P47 87 39 P55 P46 88 38 VSS_USB P45 89 37 USB0_DP P44 90 36 USB0_DM P43 91 35 VCC_USB P42 92 34 P12 P41 93 33 P13 VREFL0 94 32 P14 P40 95 31 P15 VREFH0 96 30 P16 AVCC0 97 29 P17 P07 98 28 P20 AVSS0 99 27 P21 P05 100 26 P22 14 15 16 17 18 19 20 21 22 23 24 25 VCC P35 P34 P33 P32 P31 P30 P27 P26 P25 P24 P23 9 XCOUT 13 8 XCIN P36/EXTAL 7 MD/FINED 12 6 VBATT VSS 5 VCL 11 4 PJ3 P37/XTAL 3 AVSS1 10 2 RES# 1 EMLE RX72N Group PLQP0100KB-B (100-pin LFQFP) (Top view) AVCC1 1.5.6 1. Overview Note: This figure indicates the power supply pins and I/O port pins. For the pin configuration, refer to Table 1.10, List of Pin and Pin Functions (100-Pin LFQFP). Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled. Figure 1.8 Pin Assignment (100-Pin LFQFP) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 32 of 179 RX72N Group 1.6 1. Overview List of Pin and Pin Functions 1.6.1 224-Pin LFBGA Table 1.5 List of Pin and Pin Functions (224-Pin LFBGA) (1/11) Pin Number Timer Power Supply Clock 224-Pin System LFBGA Control A1 NC A2 VREFH0 A3 VREFL0 I/O Port Bus EXDMAC SDRAMC (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) Communication (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC RXD7/ SMISO7/ SSCL7 ET1_CRS/ RMII1_CR S_DV A4 P41 A5 P92 D18/A18 POE4# A6 PD0 D0[A0/D0] POE4# GTIOC1B A7 PD2 D2[A2/D2] MTIOC4D/ TIC2 GTIOC0B MISOC-A/ CRX0 A8 TRDATA5 P96 A9 PD3 D22/A22 D3[A3/D3] LCD_DAT IRQ2 A22-B AN110 LCD_DAT IRQ3 A21-B AN111 ET1_RX_E QMI-B/QIO1- LCD_DAT IRQ7 R/ B/SDHI_D1-B/ A17-B RMII1_RX_ MMC_D1-B ER AN107 ET1_EXOU QIO2-B/ T SDHI_D2-B/ MMC_D2-B ET1_ERXD 2 MTIOC8D/ TOC2/POE8# GTIOC0A RSPCKC-A D7[A7/D7] A12 P61 SDCS#/ D0[A0/D0]/ CS1# ET1_ERXD 1/ RMII1_RX D1 A13 P62 RAS#/ D1[A1/D1]/ CS2# ET1_ERXD 0/ RMII1_RX D0 A14 PE1 D9[A9/D9]/ D1[A1/D1] P70 SDCLK AVCC0 D24 ET1_WOL PD7 B2 AN001 AN116 AN108 A11 AVSS0 A/D D/A LCD_EXT IRQ0 CLK-B TRDATA6 PG0 B1 Interrupt IRQ9-DS A10 A15 Memory I/F Camera I/F QIO3-B/ SDHI_D3-B/ MMC_D3-B ET1_RX_C LK/ REF50CK1 MTIC5U/ POE0# MTIOC4C/ MTIOC3B/ PO18 SSLC3-A MMC_D5-B GTIOC1B TXD12/ SMOSI12/ SSDA12/ TXDX12/ SIOX12/ SSLB2-B LCD_DAT A15-B ANEX1 B3 P42 IRQ10-DS AN002 B4 P46 IRQ14-DS AN006 B5 P91 D17/A17 B7 P94 D20/A20 ET1_ERXD 0/ RMII1_RX D0 B8 TRDATA4 P95 D21/A21 ET1_ERXD 1/ RMII1_RX D1 B6 SCK7 ET1_COL AN115 VCC R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 33 of 179 RX72N Group Table 1.5 1. Overview List of Pin and Pin Functions (224-Pin LFBGA) (2/11) Pin Number Timer Communication Memory I/F Camera I/F Power Supply Clock 224-Pin System LFBGA Control I/O Port Bus EXDMAC SDRAMC B9 PD4 D4[A4/D4] MTIOC8B/ POE11# SSLC0-A ET1_MDIO QSSL-B/ LCD_DAT IRQ4 / SDHI_CMD-B/ A20-B PMGI1_MD MMC_CMD-B IO AN112 B10 PD6 D6[A6/D6] MTIC5V/ MTIOC8A/ POE4# SSLC2-A ET1_RX_C QMO-B/QIO0- LCD_DAT IRQ6 LK/ B/SDHI_D0-B/ A18-B REF50CK1 MMC_D0-B AN106 B12 P63 CAS#/ D2[A2/D2]/ CS3# B13 PE2 D10[A10/ MTIOC4A/ D10]/D2[A2/ PO23/TIC3 D2] GTIOC0B RXD12/ SMISO12/ SSCL12/ RXDX12/ SSLB3-B B14 PE4 D12[A12/ MTIOC4D/ D12]/D4[A4/ MTIOC1A/ D4] PO28 GTIOC1A SSLB0-B B15 PE7 D15[A15/ MTIOC6A/ D15]/D7[A7/ TOC1 D7] GTIOC3A MISOB-B B11 (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC Interrupt A/D D/A VCC C1 AVSS1 C2 AVCC1 C3 ET1_ETXD 1/ RMII1_TXD 1 P05 C4 C5 (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) MMC_D6-B ET0_ERXD 2 LCD_DAT IRQ7-DS A14-B AN100 LCD_DAT A12-B AN102 SDHI_WP/ LCD_DAT IRQ7 MMC_RES#-B A9-B SSILRCK1 IRQ13 P44 AN105 DA1 IRQ12-DS AN004 VSS C6 P90 D16/A16 C7 PD1 D1[A1/D1] C8 VCC C9 TRSYNC1 P97 TXD7/ SMOSI7/ SSDA7 MTIOC4B/ POE0# ET1_RX_D V AN114 GTIOC1A MOSIC-A/ CTX0 D23/A23 ET1_ERXD 3 LCD_DAT IRQ1 A23-B AN109 LCD_DAT IRQ5 A11-B AN103 C10 P60 CS0# ET1_TX_E N/ RMII1_TXD _EN C11 P64 WE#/D3[A3/ D3]/CS4# ET1_ETXD 0/ RMII1_TXD 0 C13 PE5 D13[A13/ MTIOC4C/ D13]/D5[A5/ MTIOC2B D5] C14 P65 CKE/CS5# C15 P66 DQM0/ CS6# D1 P45 IRQ13-DS AN005 D2 P47 IRQ15-DS AN007 C12 VSS D3 P03 D4 P40 D5 P01 R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 MTIOC7D GTIOC0A RSPCKB-B ET0_RX_C LK/ REF50CK0 GTIOC2B CTX2 SSIDATA1 TMCI0 RXD6/ SMISO6/ SSCL6/ SSIBCK0 QIO3-C IRQ11 DA0 IRQ8-DS AN000 IRQ9 AN119 Page 34 of 179 RX72N Group Table 1.5 1. Overview List of Pin and Pin Functions (224-Pin LFBGA) (3/11) Pin Number Timer Power Supply Clock 224-Pin System LFBGA Control I/O Port D6 P02 D7 P93 PD5 D8 Bus EXDMAC SDRAMC (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) Communication (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC TMCI1 SCK6/ SSIBCK1 D19/A19 POE0# CTS7#/ ET1_LINK RTS7#/SS7# STA D5[A5/D5] MTIC5W/ MTIOC8C/ MTCLKA/ POE10# SSLC1-A Interrupt A/D D/A IRQ10 AN120 AN117 VSS D9 D10 TRDATA7 PG1 D11 PE0 D8[A8/D8]/ D0[A0/D0] D12 PE3 D11[A11/ MTIOC4B/ D11]/D3[A3/ PO26/TOC3/ D3] POE8# D13 VSS D14 TRDATA0 PG2 D15 P67 E1 VCL E2 VSS D25 LCD_DAT IRQ5 A19-B AN113 ET1_RX_E R/ RMII1_RX_ ER MTIOC3D GTIOC2B SCK12/ SSLB1-B MMC_D4-B LCD_DAT A16-B ANEX0 GTIOC2A CTS12#/ RTS12#/ SS12# ET0_ERXD MMC_D7-B 3 LCD_DAT A13-B AN101 D26 DQM1/ CS7# ET1_MDC/ QSPCLK-B/ PMGI1_MD SDHI_CLK-B/ C MMC_CLK-B ET1_TX_C LK MTIOC7C TMRI0 GTIOC1B CRX2 EPLSOUT1 E3 P00 E4 P43 E5 P07 E6 PN0 E7 PQ0 SCK11 ET1_CRS/ RMII1_CR S_DV E8 PQ1 SMISO11/ SSCL11/ RXD11 ET1_COL E9 PQ3 RTS11#/ CTS11#/ SS11# ET1_TX_E R E10 PQ5 ET1_ETXD 0/ RMII1_TXD 0 E11 PQ4 ET1_RX_C LK/ REF50CK1 E12 Memory I/F Camera I/F TXD6/ SMOSI6/ SSDA6/ AUDIO_CLK IRQ15 QIO2-C IRQ8 AN118 IRQ11-DS AN003 IRQ15 ADTRG0# ET1_ETXD 2 VCC E13 PE6 D14[A14/ MTIOC6C/ D14]/D6[A6/ TIC1 D6] GTIOC3B MOSIB-B SDHI_CD/ MMC_CD-B E14 TRCLK PG5 D29 ET1_ETXD 2 E15 TRSYNC PG4 D28 ET1_ETXD 1/ RMII1_TXD 1 F1 XCIN R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 LCD_DAT IRQ6 A10-B AN104 Page 35 of 179 RX72N Group Table 1.5 1. Overview List of Pin and Pin Functions (224-Pin LFBGA) (4/11) Pin Number Timer Power Supply Clock 224-Pin System LFBGA Control F2 VBATT F3 TRST# I/O Port Bus EXDMAC SDRAMC (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) Communication (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC PK4 GTADSM0 SSLB1 ET0_ERXD 2 F5 PK5 GTADSM1 SSLB2 ET0_ERXD 3 F7 PK6 GTIOC1A SSLB3 F8 PN1 ET1_ETXD 3 F9 PQ6 ET1_ETXD 1/ RMII1_TXD 1 F10 VSS PM1 F12 PA0 F13 TRDATA1 PG3 D27 ET1_ETXD 0/ RMII1_TXD 0 F14 TRDATA2 PG6 D30 ET1_ETXD 3 F15 TRDATA3 PG7 D31 ET1_TX_E R G1 XCOUT G2 VSS G3 VCC G4 MD/FINED G5 TOC3 DQM2/ BC0#/A0 PJ5 G6 PF5 GTETRGB SMISO10/ SSCL10/ RXD10 MTIOC4A/ GTIOC0B SSLA1-B MTIOC6D/ TIOCA0/PO16/ CACREF POE8# WAIT# CTS2#/ RTS2#/ SS2#/ SSIRXD0 ET1_ERXD SDHI_CMD-D/ 1/ QSSL-A RMII1_RX D1 ET0_TX_E N/ RMII0_TXD _EN LCD_DAT A8-B EPLSOUT0 QMI-C/QIO1-C SSILRCK0 IRQ4 RES# G8 PQ2 G9 PN2 G10 A/D D/A EMLE F11 G7 Interrupt PF4 F4 F6 Memory I/F Camera I/F SMOSI11/ SSDA11/ TXD11 ET1_RX_D V ET1_TX_C LK VCC G11 PM0 TIC3 G12 PA1 DQM3/A1 MTIOC0B/ GTIOC2A SCK5/ MTCLKC/ SSLA2-B MTIOC7B/ TIOCB0/PO17 G13 PA2 A2 MTIOC7A/ PO18 R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 GTETRGA SCK10 GTIOC1A RXD5/ SMISO5/ SSCL5/ SSLA3-B ET1_ERXD SDHI_CLK-D/ 0/ QSPCLK-A RMII1_RX D0 ET0_WOL LCD_DAT IRQ11 A7-B LCD_DAT A6-B Page 36 of 179 RX72N Group Table 1.5 1. Overview List of Pin and Pin Functions (224-Pin LFBGA) (5/11) Pin Number Timer Communication Memory I/F Camera I/F Power Supply Clock 224-Pin System LFBGA Control I/O Port Bus EXDMAC SDRAMC G14 PA3 A3 MTIOC0D/ MTCLKD/ TIOCD0/ TCLKB/PO19 RXD5/ SMISO5/ SSCL5 ET0_MDIO / PMGI0_MD IO LCD_DAT IRQ6-DS A5-B G15 PA4 A4 MTIC5U/ MTCLKA/ TIOCA1/ TMRI0/PO20 TXD5/ SMOSI5/ SSDA5/ SSLA0-B ET0_MDC/ PMGI0_MD C LCD_DAT IRQ5-DS A4-B MTIOC0A/ TMCI3/PO12/ POE10# SCK6/SCK0 ET0_LINK STA H1 XTAL H2 H3 (SCI, RSPI, RIIC, CAN, USB, SSIE) (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC Interrupt A/D D/A IRQ4 P35 H4 P33 H5 P32 H6 (GPTW, POEG) P37 P34 UPSEL (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) NMI EDREQ1 MTIOC0D/ TIOCD0/ TMRI3/PO11/ POE4#/ POE11# RXD6/ SMISO6/ SSCL6/ RXD0/ SMISO0/ SSCL0/ CRX0 PCKO IRQ3-DS MTIOC0C/ TIOCC0/ TMO3/PO10/ RTCIC2/ RTCOUT/ POE0#/ POE10# TXD6/ SMOSI6/ SSDA6/ TXD0/ SMOSI0/ SSDA0/ CTX0/ USB0_VBUS EN VSYNC IRQ2-DS MTIOC3C CTS6#/ RTS6#/ SS6#/ CTS0#/ RTS0#/ SS0#/ SSITXD0 BSCANP H7 PJ3 H8 PQ7 ET1_TX_E N/ RMII1_TXD _EN H9 PN3 ET1_RX_E R/ RMII1_RX_ ER H10 P73 H11 PL0 H12 VCC H13 VSS EDACK1 CS3# PO16 ET0_WOL GTETRGA SCK9/ RSPCKC ET0_ERXD 0/ RMII0_RX D0 GTETRGB CTS5#/ RTS5#/ SS5#/ MOSIA-B ET0_EXOU T LCD_DAT A2-B ET0_LINK STA LCD_DAT A3-B PA6 A6 MTIC5V/ MTCLKB/ TIOCA2/ TMCI3/PO22/ POE10# H15 PA5 A5 MTIOC6B/ GTIOC0A RSPCKA-B TIOCB1/PO21 EXTAL P36 J2 TDI PF2 R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 LCD_EXT CLK-A TIC2 H14 J1 ET0_EXOU QMO-C/QIO0T C RXD1/ SMISO1/ SSCL1 Page 37 of 179 RX72N Group Table 1.5 1. Overview List of Pin and Pin Functions (224-Pin LFBGA) (6/11) Pin Number Timer Power Supply Clock 224-Pin System LFBGA Control J3 TMS I/O Port Bus EXDMAC SDRAMC (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) Communication (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC Interrupt PF3 J4 P31 MTIOC4D/ TMCI2/PO9/ RTCIC1 CTS1#/ RTS1#/ SS1#/ SSLB0-A ET1_MDC/ PMGI1_MD C IRQ1-DS J5 P30 MTIOC4B/ TMRI3/PO8/ RTCIC0/ POE8# RXD1/ SMISO1/ SSCL1/ MISOB-A ET1_MDIO / PMGI1_MD IO IRQ0-DS J6 PH2 GTETRG C J7 P15 MTIOC0B/ GTETRGA RXD1/ MTCLKB/ SMISO1/ TIOCB2/ SSCL1/ TCLKB/TMCI2/ SCK3/CRX1PO13 DS/ SSILRCK1 J8 P53*1 J9 PK3 J10 PL1 J11 PN5 J12 PB1 A9 J13 P71 A18/CS1# J14 PB0 A8 MTIC5W/ TIOCA3/PO24 RXD4/ SMISO4/ SSCL4/ RXD6/ SMISO6/ SSCL6 ET0_ERXD 1/ RMII0_RX D1 LCD_DAT IRQ12 A0-B J15 PA7 A7 TIOCB2/PO23 MISOA-B ET0_WOL LCD_DAT A1-B K1 CLKOUT2 PH7 5M K2 CLKOUT K3 K4 K5 TDO A/D D/A SMOSI7/ SSDA7/ TXD7/MISOA GTETRG D TOC2 RTS8#/ ET0_TX_E CTS8#/ R SS8#/SSLB0 GTETRGB SMISO9/ SSCL9/ RXD9/ MOSIC MTIOC0C/ MTIOC4C/ TIOCB3/ TMCI0/PO25 TXD4/ SMOSI4/ SSDA4/ TXD6/ SMOSI6/ SSDA6 LCD_TCO IRQ4-DS N3-B GTIOC0B GTIOC0A SSLA3 PH5 GTADSM1 SSLA2 PF0 P10 ET0_ERXD 0/ RMII0_RX D0 ET0_MDIO / PMGI0_MD IO GTADSM0 SSLA1 K7 ET0_ERXD 1/ RMII0_RX D1 ET1_MDC/ QSSL-C PMGI1_MD C PH6 PH1 IRQ5 BCLK PH4 K6 PIXD0 TXD1/ SMOSI1/ SSDA1 TOC0 ALE R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 MTIC5W/ TMRI3 GTETRGB SMISO7/ SSCL7/ RXD7/ MOSIA IRQ0 Page 38 of 179 RX72N Group Table 1.5 1. Overview List of Pin and Pin Functions (224-Pin LFBGA) (7/11) Pin Number Timer Communication Memory I/F Camera I/F Power Supply Clock 224-Pin System LFBGA Control I/O Port Bus EXDMAC SDRAMC K8 P50 WR0#/WR# K9 PK1 K10 PL3 GTETRG D RTS9#/ ET0_RX_C CTS9#/ LK/ SS9#/SSLC0 REF50CK0 K11 PM2 GTETRG C SMOSI10/ SSDA10/ TXD10 ET1_ERXD SDHI_D0-D/ 2 QMO-A/QIO0A K12 (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC A/D D/A TXD2/ SMOSI2/ SSDA2/ SSLB1-A TOC1 GTETRGB SMISO8/ SSCL8/ RXD8/ MOSIB ET0_COL VSS K13 PB5 A13 MTIOC2A/ MTIOC1B/ TIOCB4/ TMRI1/PO29/ POE4# SCK9/ RTS9#/ SCK11 ET0_ETXD 0/ RMII0_TXD 0 LCD_CLKB K14 PB3 A11 MTIOC0A/ MTIOC4A/ TIOCD3/ TCLKD/TMO0/ PO27/POE11# SCK4/SCK6 ET0_RX_E R/ RMII0_RX_ ER LCD_TCO N1-B K15 P72 A19/CS2# ET0_MDC/ PMGI0_MD C LCD_DAT A23-A L1 PH3 L2 P27 L3 Interrupt TCK L4 GTETRG D CS7# MTIOC2B/ TMCI3/PO7 SCK1/ RSPCKB-A CS4#/ EDREQ1 MTIOC4A/ MTCLKA/ TIOCB4/ TMRI1/PO4 SCK3/ USB0_VBUS EN/SSIBCK1 PF1 P24 L5 VCC L6 CLKOUT2 PJ2 5M L7 VCC RTS7#/ CTS7#/ SS7#/SSLA0 ET1_WOL SCK1 SDHI_WP/ PIXCLK TXD8/ SMOSI8/ SSDA8/ SSLC3-B L8 P52 RD# L9 P81 EDACK0 L10 PL7 L11 P77 L12 PN4 CS7# R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 LCD_TCO N2-A RXD2/ SMISO2/ SSCL2/ SSLB3-A MTIOC3D/ PO27 PO23 GTIOC0B SMISO10/ SSCL10/ RXD10 ET0_ETXD QIO3-A/ 0/ SDHI_CD/ RMII0_TXD MMC_D3-A 0 GTIOC2B ET0_MDIO / PMGI0_MD IO SMOSI11/ SSDA11/ TXD11 ET0_RX_E QSPCLK-A/ R/ SDHI_CLK-A/ RMII0_RX_ MMC_CLK-A ER LCD_DAT A13-A LCD_DAT A17-A ET1_MDIO QSPCLK-C / PMGI1_MD IO Page 39 of 179 RX72N Group Table 1.5 1. Overview List of Pin and Pin Functions (224-Pin LFBGA) (8/11) Pin Number Timer Power Supply Clock 224-Pin System LFBGA Control (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) Communication Memory I/F Camera I/F I/O Port Bus EXDMAC SDRAMC L14 PB2 A10 TIOCC3/ TCLKC/PO26 CTS4#/ ET0_RX_C RTS4#/ LK/ SS4#/ REF50CK0 CTS6#/ RTS6#/SS6# LCD_TCO N2-B L15 PB4 A12 TIOCA4/PO28 CTS9#/ SS9#/SS11#/ CTS11#/ RTS11# ET0_TX_E N/ RMII0_TXD _EN LCD_TCO N0-B M1 P26 CS6# MTIOC2A/ TMO1/PO6 TXD1/ SMOSI1/ SSDA1/ CTS3#/ RTS3#/ SS3#/ MOSIB-A ET1_EXOU T M2 P23 EDACK0 MTIOC3D/ MTCLKD/ TIOCD3/PO3 P25 CS5#/ EDACK1 MTIOC4C/ MTCLKB/ TIOCA4/PO5 RXD3/ SMISO3/ SSCL3/ SSIDATA1 SCK8/ SSLC1-B L13 (SCI, RSPI, RIIC, CAN, USB, SSIE) (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC Interrupt A/D D/A VCC M3 CLKOUT M4 VSS M5 PJ0 MTIOC6B M6 P84 MTIOC6D M7 (GPTW, POEG) GTIOC0A TXD3/ SMOSI3/ SSDA3/ CTS0#/ RTS0#/ SS0#/CTX1/ SSIBCK0 SDHI_D1-C/ PIXD7 SDHI_CD/ HSYNC ADTRG0# EPLSOUT0 LCD_DAT A0-A ET1_LINK STA LCD_DAT A2-A LCD_DAT A8-A VSS M8 P51 WR1#/ BC1#/ WAIT# M9 P83 EDACK1 M10 PK0 M11 SCK2/ SSLB2-A MTIOC4C GTIOC0A SCK10/ SS10#/ CTS10# ET0_CRS/ RMII0_CR S_DV TIC1 GTETRGA SCK8/ RSPCKB ET0_MDC/ PMGI0_MD C PL5 GTADSM1 SSLC2 ET0_ETXD 1/ RMII0_TXD 1 M12 PL6 GTIOC2A SSLC3 ET0_TX_E N/ RMII0_TXD _EN M13 PM7 GTIOC3B ET0_CRS/ SDHI_WP RMII0_CR S_DV M14 PC0 A16 MTIOC3C/ TCLKC/PO17 CTS5#/ RTS5#/ SS5#/ SSLA1-A ET0_ERXD 3 M15 PB6 A14 MTIOC3D/ TIOCA5/PO30 RXD9/ SMISO9/ SSCL9/ SMISO11/ SSCL11/ RXD11 ET0_ETXD 1/ RMII0_TXD 1 R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 IRQ14 Page 40 of 179 RX72N Group Table 1.5 1. Overview List of Pin and Pin Functions (224-Pin LFBGA) (9/11) Pin Number Timer Power Supply Clock 224-Pin System LFBGA Control I/O Port Bus EXDMAC SDRAMC N1 P22 EDREQ0 N2 Communication (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) (GPTW, POEG) MTIOC3B/ MTCLKC/ TIOCC3/ TMO0/PO2 GTIOC1A SCK0/ USB0_OVRC URB/ AUDIO_CLK PH0 TIC0 GTETRGA SCK7/ RSPCKA N3 P86 MTIOC4D/ TIOCA0 GTIOC2B SMISO10/ SSCL10/ RXD10 N4 P85 MTIOC6C/ TIOCC0 N5 P13 N6 PJ1 N7 CLKOUT2 P56 5M N8 VCC N9 UB WR2#/BC2# MTIOC0B/ TIOCA5/ TMO3/PO13 (SCI, RSPI, RIIC, CAN, USB, SSIE) Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC Interrupt SDHI_D0-C/ PIXD6 PIXD1 LCD_DAT A1-A GTADSM1 TXD2/ SMOSI2/ SSDA2/ SDA0[FM+] LCD_TCO IRQ3 N0-A MTIOC6A RXD8/ SMISO8/ SSCL8/ SSLC2-B EDACK1 MTIOC3C/ TIOCA1 SCK7/ RSPCKC-B PC7 A23/CS0# MTIOC3A/ MTCLKB/ TMO2/PO31/ TOC0/ CACREF N10 P80 EDREQ0 MTIOC3B/ PO26 N11 PK2 N12 P76 N13 PM6 N14 PC1 A17 MTIOC3A/ TCLKD/PO18 SCK5/ SSLA2-A ET0_ERXD 2 N15 PB7 A15 MTIOC3B/ TIOCB5/PO31 TXD9/ SMOSI9/ SSDA9/ SMOSI11/ SSDA11/ TXD11 ET0_CRS/ RMII0_CR S_DV P1 PK7 P2 P17 MTIOC3A/ GTIOC0B SCK1/TXD3/ EPLSOUT0 SDHI_D3-C/ MTIOC3B/ SMOSI3/ PIXD3 MTIOC4B/ SSDA3/ TIOCB0/ SDA2-DS/ TCLKD/TMO1/ SSITXD0 PO15/POE8# IRQ7 P3 P20 MTIOC1A/ TIOCB3/ TMRI0/PO0 IRQ8 GTIOC3A TXD8/ SMOSI8/ SSDA8/ SMOSI10/ SSDA10/ TXD10/ MISOA-A SCK10/ RTS10# GTETRG C CS6# PO22 EPLSOUT1 ADTRG1# LCD_TCO N3-A LCD_DAT A4-A ET0_COL MMC_D7-A ET0_TX_E QIO2-A/ N/ SDHI_WP/ RMII0_TXD MMC_D2-A _EN LCD_DAT IRQ14 A9-A LCD_DAT A14-A SMOSI8/ ET0_RX_D SSDA8/ V TXD8/MISOB SMISO11/ SSCL11/ RXD11 GTIOC3A R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 A/D D/A ET0_RX_C QSSL-A/ LCD_DAT LK/ SDHI_CMD-A/ A18-A REF50CK0 MMC_CMD-A ET0_TX_C SDHI_CD LK LCD_DAT IRQ12 A22-A GTIOC1B TXD0/ SMOSI0/ SSDA0/ SDA1/ USB0_ID/ SSIRXD0 SDHI_CMD-C/ PIXD4 ADTRG1# Page 41 of 179 RX72N Group Table 1.5 1. Overview List of Pin and Pin Functions (224-Pin LFBGA) (10/11) Pin Number Timer Power Supply Clock 224-Pin System LFBGA Control I/O Port P4 P14 P5 VCC_USB P6 VSS_USB P7 P57 P8 P11 P9 Bus EXDMAC SDRAMC (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) Communication (GPTW, POEG) MTIOC3A/ GTETRG MTCLKA/ D TIOCB5/ TCLKA/TMRI2/ PO15 MTIC5V/ TMCI3 (SCI, RSPI, RIIC, CAN, USB, SSIE) Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC Interrupt CTS1#/ RTS1#/ SS1#/CTX1/ USB0_OVRC URA LCD_CLK- IRQ4 A RXD7/ SMISO7/ SSCL7/ SSLC0-B LCD_DAT A3-A SCK2 EPLSOUT1 LCD_DAT IRQ1 A7-A ET0_ETXD MMC_D4-A 1/ RMII0_TXD 1 LCD_DAT A12-A A/D D/A VSS P10 P82 EDREQ1 MTIOC4A/ PO28 GTIOC2A SMOSI10/ SSDA10/ TXD10 P11 PC4 A20/CS3# MTIOC3D/ MTCLKC/ TMCI1/PO25/ POE0# GTETRG C SCK5/ ET0_TX_C QMI-A/QIO1- LCD_DAT CTS8#/ LK A/SDHI_D1-A/ A15-A SS8#/SS10#/ MMC_D1-A CTS10#/ RTS10#/ SSLA0-A P12 PL2 GTETRG C SMOSI9/ SSDA9/ TXD9/ MISOC P13 PC2 P14 A18 MTIOC4B/ TCLKA/PO21 ET0_RX_E R/ RMII0_RX_ ER GTIOC2B RXD5/ SMISO5/ SSCL5/ SSLA3-A ET0_RX_D SDHI_D3-A/ V MMC_CD-A PM4 GTADSM0 ET0_ETXD SDHI_D2-D/ 2 QIO2-A P15 PM3 GTETRG D R1 P21 MTIOC1B/ MTIOC4A/ TIOCA3/ TMCI0/PO1 GTIOC2A RXD0/ SMISO0/ SSCL0/ SCL1/ USB0_EXIC EN/ SSILRCK0 R2 P87 MTIOC4C/ TIOCA2 GTIOC1B SMOSI10/ SSDA10/ TXD10 R3 P16 MTIOC3C/ MTIOC3D/ TIOCB1/ TCLKC/TMO2/ PO14/ RTCOUT R4 P12 WR3#/BC3# MTIC5U/ TMCI1 RTS10#/ CTS10#/ SS10# TXD1/ SMOSI1/ SSDA1/ RXD3/ SMISO3/ SSCL3/ SCL2-DS/ USB0_VBUS EN/ USB0_VBUS / USB0_OVRC URB GTADSM0 RXD2/ SMISO2/ SSCL2/ SCL0[FM+] R5 USB0_DM R6 USB0_DP R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 LCD_DAT A19-A ET1_ERXD SDHI_D1-D/ 3 QMI-A/QIO1-A SDHI_CLK-C/ PIXD5 IRQ9 EPLSOUT1 SDHI_D2-C/ PIXD2 IRQ6 ADTRG0# LCD_TCO IRQ2 N1-A Page 42 of 179 RX72N Group Table 1.5 1. Overview List of Pin and Pin Functions (224-Pin LFBGA) (11/11) Pin Number Timer Communication Memory I/F Camera I/F Power Supply Clock 224-Pin System LFBGA Control I/O Port R7 P54 D1[A1/D1]/ EDACK0/ ALE MTIOC4B/ TMCI1 CTS2#/ RTS2#/ SS2#/ MOSIC-B/ CTX1 ET0_LINK STA LCD_DAT A6-A R8 P55 D0[A0/D0]/ EDREQ0/ WAIT# MTIOC4D/ TMO3 TXD7/ SMOSI7/ SSDA7/ MISOC-B/ CRX1 ET0_EXOU T LCD_DAT IRQ10 A5-A R9 PC6 D2[A2/D2]/ A22/CS1# MTIOC3C/ MTCLKA/ TMCI2/PO30/ TIC0 GTIOC3B RXD8/ SMISO8/ SSCL8/ SMISO10/ SSCL10/ RXD10/ MOSIA-A ET0_ETXD MMC_D6-A 3 LCD_DAT IRQ13 A10-A R10 PC5 D3[A3/D3]/ A21/CS2#/ WAIT# MTIOC3B/ MTCLKD/ TMRI2/PO29 GTIOC1A SCK8/ RTS8#/ SCK10/ RSPCKA-A ET0_ETXD MMC_D5-A 2 LCD_DAT A11-A R11 PC3 A19 MTIOC4D/ TCLKB/PO24 GTIOC1B TXD5/ SMOSI5/ SSDA5 ET0_TX_E QMO-A/QIO0- LCD_DAT R A/SDHI_D0-A/ A16-A MMC_D0-A R12 PL4 GTADSM0 SSLC1 ET0_ETXD 0/ RMII0_TXD 0 R13 P75 CS5# PO20 SCK11/ RTS11# ET0_ERXD SDHI_D2-A/ LCD_DAT 0/ MMC_RES#-A A20-A RMII0_RX D0 R14 P74 A20/CS4# PO19 SS11#/ CTS11# ET0_ERXD 1/ RMII0_RX D1 R15 PM5 Bus EXDMAC SDRAMC (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) (GPTW, POEG) GTADSM1 (SCI, RSPI, RIIC, CAN, USB, SSIE) (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC Interrupt A/D D/A LCD_DAT A21-A ET0_ETXD SDHI_D3-D/ 3 QIO3-A Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled. R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 43 of 179 RX72N Group 1.6.2 1. Overview 176-Pin LFBGA Table 1.6 List of Pin and Pin Functions (176-Pin LFBGA) (1/9) Pin Number Timer Power Supply Clock 176-Pin System LFBGA Control A1 AVSS0 A2 AVCC0 A3 VREFL0 A4 A5 A6 VCC A7 VSS A8 I/O Port Bus EXDMAC SDRAMC (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) Communication (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC Interrupt A/D D/A P42 IRQ10-DS AN002 P46 IRQ14-DS AN006 P94 D20/A20 ET1_ERXD 0/ RMII1_RX D0 A9 VCC A10 TRSYNC1 P97 D23/A23 ET1_ERXD 3 A11 PD6 D6[A6/D6] A12 P60 CS0# ET1_TX_E N/ RMII1_TXD _EN A13 P63 CAS#/ D2[A2/D2]/ CS3# ET1_ETXD 1/ RMII1_TXD 1 A14 PE1 D9[A9/D9]/ D1[A1/D1] MTIOC4C/ MTIOC3B/ PO18 GTIOC1B TXD12/ SMOSI12/ SSDA12/ TXDX12/ SIOX12/ SSLB2-B MMC_D5-B LCD_DAT A15-B ANEX1 A15 PE2 D10[A10/ MTIOC4A/ D10]/D2[A2/ PO23/TIC3 D2] GTIOC0B RXD12/ SMISO12/ SSCL12/ RXDX12/ SSLB3-B MMC_D6-B LCD_DAT IRQ7-DS A14-B AN100 B1 P05 IRQ13 DA1 B2 P07 IRQ15 ADTRG0# B3 P40 IRQ8-DS AN000 B4 P41 IRQ9-DS AN001 B5 P47 IRQ15-DS AN007 MTIC5V/ MTIOC8A/ POE4# P91 D17/A17 B7 P92 D18/A18 POE4# B8 PD1 D1[A1/D1] MTIOC4B/ POE0# B9 TRDATA5 P96 PD4 ET1_RX_C QMO-B/QIO0- LCD_DAT IRQ6 LK/ B/SDHI_D0-B/ A18-B REF50CK1 MMC_D0-B SSILRCK1 B6 B10 SSLC2-A SCK7 ET1_COL AN115 RXD7/ SMISO7/ SSCL7 ET1_CRS/ RMII1_CR S_DV AN116 R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 LCD_DAT IRQ1 A23-B AN109 ET1_MDIO QSSL-B/ LCD_DAT IRQ4 / SDHI_CMD-B/ A20-B PMGI1_MD MMC_CMD-B IO AN112 GTIOC1A MOSIC-A/ CTX0 D22/A22 D4[A4/D4] AN106 ET1_ERXD 2 MTIOC8B/ POE11# SSLC0-A Page 44 of 179 RX72N Group Table 1.6 1. Overview List of Pin and Pin Functions (176-Pin LFBGA) (2/9) Pin Number Timer Power Supply Clock 176-Pin System LFBGA Control I/O Port B11 TRDATA7 PG1 B12 VSS Bus EXDMAC SDRAMC (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) ET1_RX_E R/ RMII1_RX_ ER ET1_ETXD 0/ RMII1_TXD 0 P64 WE#/D3[A3/ D3]/CS4# B14 PE0 D8[A8/D8]/ D0[A0/D0] B15 PE3 D11[A11/ MTIOC4B/ D11]/D3[A3/ PO26/TOC3/ D3] POE8# MTIOC3D Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC D25 B13 C1 Communication Interrupt A/D D/A GTIOC2B SCK12/ SSLB1-B MMC_D4-B LCD_DAT A16-B ANEX0 GTIOC2A CTS12#/ RTS12#/ SS12# ET0_ERXD MMC_D7-B 3 LCD_DAT A13-B AN101 AVSS1 C2 AVCC1 C3 VREFH0 C4 P43 IRQ11-DS AN003 C5 P45 IRQ13-DS AN005 C6 P90 D16/A16 C7 PD0 D0[A0/D0] POE4# GTIOC1B C8 PD2 D2[A2/D2] MTIOC4D/ TIC2 GTIOC0B MISOC-A/ CRX0 C9 PD3 D3[A3/D3] MTIOC8D/ TOC2/POE8# GTIOC0A RSPCKC-A C10 TRDATA6 PG0 C11 VCC TXD7/ SMOSI7/ SSDA7 ET1_RX_D V AN114 LCD_EXT IRQ0 CLK-B AN108 ET1_EXOU QIO2-B/ T SDHI_D2-B/ MMC_D2-B LCD_DAT IRQ2 A22-B AN110 ET1_WOL LCD_DAT IRQ3 A21-B AN111 LCD_DAT A12-B AN102 D24 ET1_RX_C LK/ REF50CK1 ET1_ERXD 0/ RMII1_RX D0 QIO3-B/ SDHI_D3-B/ MMC_D3-B C12 P62 RAS#/ D1[A1/D1]/ CS2# C13 PE4 D12[A12/ MTIOC4D/ D12]/D4[A4/ MTIOC1A/ D4] PO28 C15 P70 SDCLK D1 P01 TMCI0 RXD6/ SMISO6/ SSCL6/ SSIBCK0 IRQ9 AN119 D2 P02 TMCI1 SCK6/ SSIBCK1 IRQ10 AN120 SSIDATA1 IRQ11 DA0 TMRI0 TXD6/ SMOSI6/ SSDA6/ AUDIO_CLK IRQ8 AN118 POE0# CTS7#/ ET1_LINK RTS7#/SS7# STA C14 GTIOC1A SSLB0-B ET0_ERXD 2 VSS D3 P03 D4 P00 D5 P44 D6 P93 IRQ12-DS AN004 D19/A19 R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 AN117 Page 45 of 179 RX72N Group Table 1.6 1. Overview List of Pin and Pin Functions (176-Pin LFBGA) (3/9) Pin Number Timer Power Supply Clock 176-Pin System LFBGA Control I/O Port D7 TRDATA4 P95 D8 VSS Bus EXDMAC SDRAMC (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) Communication (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) D21/A21 Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC Interrupt A/D D/A ET1_ERXD 1/ RMII1_RX D1 D9 PD5 D5[A5/D5] MTIC5W/ MTIOC8C/ MTCLKA/ POE10# SSLC1-A ET1_MDC/ QSPCLK-B/ PMGI1_MD SDHI_CLK-B/ C MMC_CLK-B LCD_DAT IRQ5 A19-B AN113 D10 PD7 D7[A7/D7] MTIC5U/ POE0# SSLC3-A ET1_RX_E QMI-B/QIO1- LCD_DAT IRQ7 R/ B/SDHI_D1-B/ A17-B RMII1_RX_ MMC_D1-B ER AN107 D11 P61 SDCS#/ D0[A0/D0]/ CS1# D12 PE5 D13[A13/ MTIOC4C/ D13]/D5[A5/ MTIOC2B D5] GTIOC0A RSPCKB-B PE7 D15[A15/ MTIOC6A/ D15]/D7[A7/ TOC1 D7] GTIOC3A MISOB-B D15 P65 CKE/CS5# E1 PJ5 D13 ET0_RX_C LK/ REF50CK0 POE8# CTS2#/ RTS2#/ SS2#/ SSIRXD0 WAIT# E12 PE6 D14[A14/ MTIOC6C/ D14]/D6[A6/ TIC1 D6] E13 TRDATA0 PG2 D26 ET1_TX_C LK E14 TRDATA1 PG3 D27 ET1_ETXD 0/ RMII1_TXD 0 E15 P67 DQM1/ CS7# MTIOC7C AN105 SSILRCK0 IRQ4 PJ3 EDACK1 MTIOC3C P66 DQM0/ CS6# MTIOC7D PG4 D28 VSS F1 VBATT F2 VCL F3 GTIOC3B MOSIB-B GTIOC1B CRX2 CTS6#/ RTS6#/ SS6#/ CTS0#/ RTS0#/ SS0#/ SSITXD0 SDHI_CD/ MMC_CD-B EPLSOUT1 LCD_DAT IRQ6 A10-B AN104 IRQ15 ET0_EXOU T BSCANP F12 F13 SDHI_WP/ LCD_DAT IRQ7 MMC_RES#-B A9-B EPLSOUT0 PF5 F4 AN103 EMLE E3 E4 LCD_DAT IRQ5 A11-B VCC D14 E2 ET1_ERXD 1/ RMII1_RX D1 TRSYNC R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 GTIOC2B CTX2 ET1_ETXD 1/ RMII1_TXD 1 Page 46 of 179 RX72N Group Table 1.6 1. Overview List of Pin and Pin Functions (176-Pin LFBGA) (4/9) Pin Number Timer Power Supply Clock 176-Pin System LFBGA Control I/O Port F14 PA0 F15 Bus EXDMAC SDRAMC DQM2/ BC0#/A0 (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) Communication (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) MTIOC4A/ GTIOC0B SSLA1-B MTIOC6D/ TIOCA0/PO16/ CACREF Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC ET0_TX_E N/ RMII0_TXD _EN Interrupt LCD_DAT A8-B VSS G1 XCIN G2 XCOUT G3 MD/FINED G4 TRST# PF4 G12 TRCLK PG5 D29 ET1_ETXD 2 G13 TRDATA2 PG6 D30 ET1_ETXD 3 G14 PA1 G15 VCC H1 XTAL H2 VSS H3 RES# H4 UPSEL DQM3/A1 MTIOC0B/ GTIOC2A SCK5/ MTCLKC/ SSLA2-B MTIOC7B/ TIOCB0/PO17 ET0_WOL LCD_DAT IRQ11 A7-B P37 P35 NMI H12 PA4 A4 MTIC5U/ MTCLKA/ TIOCA1/ TMRI0/PO20 TXD5/ SMOSI5/ SSDA5/ SSLA0-B ET0_MDC/ PMGI0_MD C LCD_DAT IRQ5-DS A4-B H13 PA3 A3 MTIOC0D/ MTCLKD/ TIOCD0/ TCLKB/PO19 RXD5/ SMISO5/ SSCL5 ET0_MDIO / PMGI0_MD IO LCD_DAT IRQ6-DS A5-B H14 PA2 A2 MTIOC7A/ PO18 H15 TRDATA3 PG7 J1 EXTAL J2 VCC J3 J4 TMS GTIOC1A RXD5/ SMISO5/ SSCL5/ SSLA3-B D31 LCD_DAT A6-B ET1_TX_E R P36 P34 J12 MTIOC0A/ TMCI3/PO12/ POE10# SCK6/SCK0 ET0_LINK STA IRQ4 PF3 PA5 A5 MTIOC6B/ GTIOC0A RSPCKA-B TIOCB1/PO21 ET0_LINK STA LCD_DAT A3-B J14 PA7 A7 TIOCB2/PO23 ET0_WOL LCD_DAT A1-B J15 PA6 A6 MTIC5V/ MTCLKB/ TIOCA2/ TMCI3/PO22/ POE10# GTETRGB CTS5#/ RTS5#/ SS5#/ MOSIA-B ET0_EXOU T LCD_DAT A2-B K1 P33 EDREQ1 MTIOC0D/ TIOCD0/ TMRI3/PO11/ POE4#/ POE11# RXD6/ SMISO6/ SSCL6/ RXD0/ SMISO0/ SSCL0/ CRX0 J13 A/D D/A VSS R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 MISOA-B PCKO IRQ3-DS Page 47 of 179 RX72N Group Table 1.6 1. Overview List of Pin and Pin Functions (176-Pin LFBGA) (5/9) Pin Number Timer Power Supply Clock 176-Pin System LFBGA Control I/O Port K2 P32 K3 TDI PF2 K4 TCK PF1 Bus EXDMAC SDRAMC MTIOC0C/ TIOCC0/ TMO3/PO10/ RTCIC2/ RTCOUT/ POE0#/ POE10# (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC TXD6/ SMOSI6/ SSDA6/ TXD0/ SMOSI0/ SSDA0/ CTX0/ USB0_VBUS EN VSYNC Interrupt A/D D/A IRQ2-DS RXD1/ SMISO1/ SSCL1 SCK1 K12 PB2 A10 K13 P71 A18/CS1# K15 PB0 A8 L1 L2 K14 (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) Communication TIOCC3/ TCLKC/PO26 CTS4#/ ET0_RX_C RTS4#/ LK/ SS4#/ REF50CK0 CTS6#/ RTS6#/SS6# LCD_TCO N2-B ET0_MDIO / PMGI0_MD IO VCC MTIC5W/ TIOCA3/PO24 RXD4/ SMISO4/ SSCL4/ RXD6/ SMISO6/ SSCL6 ET0_ERXD 1/ RMII0_RX D1 P31 MTIOC4D/ TMCI2/PO9/ RTCIC1 CTS1#/ RTS1#/ SS1#/ SSLB0-A ET1_MDC/ PMGI1_MD C IRQ1-DS P30 MTIOC4B/ TMRI3/PO8/ RTCIC0/ POE8# RXD1/ SMISO1/ SSCL1/ MISOB-A ET1_MDIO / PMGI1_MD IO IRQ0-DS LCD_DAT IRQ12 A0-B L3 TDO PF0 TXD1/ SMOSI1/ SSDA1 L4 CLKOUT P25 CS5#/ EDACK1 MTIOC4C/ MTCLKB/ TIOCA4/PO5 RXD3/ SMISO3/ SSCL3/ SSIDATA1 L12 PB6 A14 MTIOC3D/ TIOCA5/PO30 RXD9/ SMISO9/ SSCL9/ SMISO11/ SSCL11/ RXD11 L13 PB3 A11 MTIOC0A/ MTIOC4A/ TIOCD3/ TCLKD/TMO0/ PO27/POE11# SCK4/SCK6 ET0_RX_E R/ RMII0_RX_ ER LCD_TCO N1-B L14 PB1 A9 MTIOC0C/ MTIOC4C/ TIOCB3/ TMCI0/PO25 TXD4/ SMOSI4/ SSDA4/ TXD6/ SMOSI6/ SSDA6 ET0_ERXD 0/ RMII0_RX D0 LCD_TCO IRQ4-DS N3-B L15 P72 A19/CS2# ET0_MDC/ PMGI0_MD C LCD_DAT A23-A M1 P27 CS7# R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 MTIOC2B/ TMCI3/PO7 SCK1/ RSPCKB-A SDHI_CD/ HSYNC ADTRG0# ET0_ETXD 1/ RMII0_TXD 1 ET1_WOL Page 48 of 179 RX72N Group Table 1.6 1. Overview List of Pin and Pin Functions (176-Pin LFBGA) (6/9) Pin Number Timer Communication Power Supply Clock 176-Pin System LFBGA Control I/O Port Bus EXDMAC SDRAMC M2 P26 CS6# MTIOC2A/ TMO1/PO6 TXD1/ SMOSI1/ SSDA1/ CTS3#/ RTS3#/ SS3#/ MOSIB-A M3 P24 CS4#/ EDREQ1 MTIOC4A/ MTCLKA/ TIOCB4/ TMRI1/PO4 SCK3/ USB0_VBUS EN/SSIBCK1 M4 P86 M5 CLKOUT2 PJ2 5M M6 PJ1 MTIOC6A M7 P85 MTIOC6C/ TIOCC0 M8 P55 D0[A0/D0]/ EDREQ0/ WAIT# M9 P50 WR0#/WR# M10 PC5 D3[A3/D3]/ A21/CS2#/ WAIT# MTIOC3B/ MTCLKD/ TMRI2/PO29 M11 P81 EDACK0 MTIOC3D/ PO27 M12 P77 CS7# PO23 M13 PB7 A15 M14 PB5 M15 PB4 N1 (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) MTIOC4D/ TIOCA0 (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC SDHI_WP/ PIXCLK PIXD1 TXD8/ SMOSI8/ SSDA8/ SSLC3-B MTIOC4D/ TMO3 A/D D/A ET1_EXOU T GTIOC2B SMISO10/ SSCL10/ RXD10 RXD8/ SMISO8/ SSCL8/ SSLC2-B Interrupt LCD_TCO N2-A EPLSOUT1 LCD_TCO N3-A LCD_DAT A1-A TXD7/ SMOSI7/ SSDA7/ MISOC-B/ CRX1 ET0_EXOU T LCD_DAT IRQ10 A5-A GTIOC1A SCK8/ RTS8#/ SCK10/ RSPCKA-A ET0_ETXD MMC_D5-A 2 LCD_DAT A11-A GTIOC0B SMISO10/ SSCL10/ RXD10 ET0_ETXD QIO3-A/ 0/ SDHI_CD/ RMII0_TXD MMC_D3-A 0 LCD_DAT A13-A SMOSI11/ SSDA11/ TXD11 ET0_RX_E QSPCLK-A/ R/ SDHI_CLK-A/ RMII0_RX_ MMC_CLK-A ER LCD_DAT A17-A MTIOC3B/ TIOCB5/PO31 TXD9/ SMOSI9/ SSDA9/ SMOSI11/ SSDA11/ TXD11 ET0_CRS/ RMII0_CR S_DV A13 MTIOC2A/ MTIOC1B/ TIOCB4/ TMRI1/PO29/ POE4# SCK9/ RTS9#/ SCK11 ET0_ETXD 0/ RMII0_TXD 0 LCD_CLKB A12 TIOCA4/PO28 CTS9#/ SS9#/SS11#/ CTS11#/ RTS11# ET0_TX_E N/ RMII0_TXD _EN LCD_TCO N0-B TXD2/ SMOSI2/ SSDA2/ SSLB1-A VCC R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 49 of 179 RX72N Group Table 1.6 1. Overview List of Pin and Pin Functions (176-Pin LFBGA) (7/9) Pin Number Timer Communication Memory I/F Camera I/F Power Supply Clock 176-Pin System LFBGA Control I/O Port Bus EXDMAC SDRAMC N2 P23 EDACK0 MTIOC3D/ MTCLKD/ TIOCD3/PO3 GTIOC0A TXD3/ SMOSI3/ SSDA3/ CTS0#/ RTS0#/ SS0#/CTX1/ SSIBCK0 SDHI_D1-C/ PIXD7 N3 P22 EDREQ0 MTIOC3B/ MTCLKC/ TIOCC3/ TMO0/PO2 GTIOC1A SCK0/ USB0_OVRC URB/ AUDIO_CLK SDHI_D0-C/ PIXD6 N4 P15 N5 P12 N6 PJ0 MTIOC6B N7 P84 MTIOC6D N8 P54 D1[A1/D1]/ EDACK0/ ALE N9 P51 WR1#/ BC1#/ WAIT# PC7 A23/CS0# MTIOC3A/ MTCLKB/ TMO2/PO31/ TOC0/ CACREF GTIOC3A TXD8/ SMOSI8/ SSDA8/ SMOSI10/ SSDA10/ TXD10/ MISOA-A ET0_COL N11 P82 EDREQ1 MTIOC4A/ PO28 GTIOC2A SMOSI10/ SSDA10/ TXD10 ET0_ETXD MMC_D4-A 1/ RMII0_TXD 1 N12 PC3 A19 MTIOC4D/ TCLKB/PO24 GTIOC1B TXD5/ SMOSI5/ SSDA5 ET0_TX_E QMO-A/QIO0- LCD_DAT R A/SDHI_D0-A/ A16-A MMC_D0-A N13 PC0 A16 MTIOC3C/ TCLKC/PO17 CTS5#/ RTS5#/ SS5#/ SSLA1-A N14 P73 CS3# PO16 N10 UB N15 VSS P1 VSS (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC MTIOC0B/ GTETRGA RXD1/ MTCLKB/ SMISO1/ TIOCB2/ SSCL1/ TCLKB/TMCI2/ SCK3/CRX1PO13 DS/ SSILRCK1 WR3#/BC3# MTIC5U/ TMCI1 MTIOC4B/ TMCI1 PIXD0 GTADSM0 RXD2/ SMISO2/ SSCL2/ SCL0[FM+] SCK8/ SSLC1-B CTS2#/ RTS2#/ SS2#/ MOSIC-B/ CTX1 A/D D/A IRQ5 LCD_TCO IRQ2 N1-A EPLSOUT0 LCD_DAT A0-A ET1_LINK STA LCD_DAT A2-A ET0_LINK STA LCD_DAT A6-A SCK2/ SSLB2-A MMC_D7-A ET0_WOL P17 MTIOC3A/ GTIOC0B SCK1/TXD3/ EPLSOUT0 SDHI_D3-C/ MTIOC3B/ SMOSI3/ PIXD3 MTIOC4B/ SSDA3/ TIOCB0/ SDA2-DS/ TCLKD/TMO1/ SSITXD0 PO15/POE8# P3 P87 MTIOC4C/ TIOCA2 GTIOC1B SMOSI10/ SSDA10/ TXD10 LCD_DAT IRQ14 A9-A LCD_DAT A12-A ET0_ERXD 3 P2 R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Interrupt IRQ14 LCD_EXT CLK-A IRQ7 ADTRG1# EPLSOUT1 SDHI_D2-C/ PIXD2 Page 50 of 179 RX72N Group Table 1.6 1. Overview List of Pin and Pin Functions (176-Pin LFBGA) (8/9) Pin Number Timer Power Supply Clock 176-Pin System LFBGA Control I/O Port P4 P14 P5 VCC_USB P6 VSS_USB Bus EXDMAC SDRAMC (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) Communication (GPTW, POEG) MTIOC3A/ GTETRG MTCLKA/ D TIOCB5/ TCLKA/TMRI2/ PO15 (SCI, RSPI, RIIC, CAN, USB, SSIE) Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC Interrupt CTS1#/ RTS1#/ SS1#/CTX1/ USB0_OVRC URA LCD_CLK- IRQ4 A RXD7/ SMISO7/ SSCL7/ SSLC0-B LCD_DAT A3-A P7 P57 P8 P10 ALE P9 P52 RD# P10 P83 EDACK1 MTIOC4C GTIOC0A SCK10/ SS10#/ CTS10# ET0_CRS/ RMII0_CR S_DV LCD_DAT A8-A P11 PC6 D2[A2/D2]/ A22/CS1# MTIOC3C/ MTCLKA/ TMCI2/PO30/ TIC0 GTIOC3B RXD8/ SMISO8/ SSCL8/ SMISO10/ SSCL10/ RXD10/ MOSIA-A ET0_ETXD MMC_D6-A 3 LCD_DAT IRQ13 A10-A P12 PC4 A20/CS3# MTIOC3D/ MTCLKC/ TMCI1/PO25/ POE0# GTETRG C P13 PC2 A18 MTIOC4B/ TCLKA/PO21 GTIOC2B RXD5/ SMISO5/ SSCL5/ SSLA3-A P14 P75 CS5# PO20 P15 MTIC5W/ TMRI3 A/D D/A IRQ0 RXD2/ SMISO2/ SSCL2/ SSLB3-A SCK5/ ET0_TX_C QMI-A/QIO1- LCD_DAT CTS8#/ LK A/SDHI_D1-A/ A15-A SS8#/SS10#/ MMC_D1-A CTS10#/ RTS10#/ SSLA0-A SCK11/ RTS11# ET0_RX_D SDHI_D3-A/ V MMC_CD-A LCD_DAT A19-A ET0_ERXD SDHI_D2-A/ LCD_DAT 0/ MMC_RES#-A A20-A RMII0_RX D0 VCC R1 P21 MTIOC1B/ MTIOC4A/ TIOCA3/ TMCI0/PO1 R2 P20 MTIOC1A/ TIOCB3/ TMRI0/PO0 TXD0/ SMOSI0/ SSDA0/ SDA1/ USB0_ID/ SSIRXD0 R3 P16 MTIOC3C/ MTIOC3D/ TIOCB1/ TCLKC/TMO2/ PO14/ RTCOUT TXD1/ SMOSI1/ SSDA1/ RXD3/ SMISO3/ SSCL3/ SCL2-DS/ USB0_VBUS EN/ USB0_VBUS / USB0_OVRC URB R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 GTIOC2A RXD0/ SMISO0/ SSCL0/ SCL1/ USB0_EXIC EN/ SSILRCK0 SDHI_CLK-C/ PIXD5 IRQ9 SDHI_CMD-C/ PIXD4 IRQ8 IRQ6 ADTRG0# Page 51 of 179 RX72N Group Table 1.6 1. Overview List of Pin and Pin Functions (176-Pin LFBGA) (9/9) Pin Number Timer Power Supply Clock 176-Pin System LFBGA Control I/O Port R4 P13 Bus EXDMAC SDRAMC (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) WR2#/BC2# MTIOC0B/ TIOCA5/ TMO3/PO13 R5 Communication (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC GTADSM1 TXD2/ SMOSI2/ SSDA2/ SDA0[FM+] Interrupt LCD_TCO IRQ3 N0-A A/D D/A ADTRG1# USB0_DM R6 USB0_DP R7 CLKOUT2 P56 5M MTIOC3C/ TIOCA1 SCK7/ RSPCKC-B R8 P11 MTIC5V/ TMCI3 SCK2 EPLSOUT1 LCD_DAT IRQ1 A7-A R9 P53*1 BCLK R12 P80 EDREQ0 MTIOC3B/ PO26 SCK10/ RTS10# ET0_TX_E QIO2-A/ N/ SDHI_WP/ RMII0_TXD MMC_D2-A _EN LCD_DAT A14-A R13 P76 CS6# PO22 SMISO11/ SSCL11/ RXD11 ET0_RX_C QSSL-A/ LCD_DAT LK/ SDHI_CMD-A/ A18-A REF50CK0 MMC_CMD-A R14 P74 A20/CS4# PO19 SS11#/ CTS11# ET0_ERXD 1/ RMII0_RX D1 LCD_DAT A21-A R15 PC1 A17 MTIOC3A/ TCLKD/PO18 SCK5/ SSLA2-A ET0_ERXD 2 LCD_DAT IRQ12 A22-A R10 VSS R11 VCC EDACK1 LCD_DAT A4-A Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled. R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 52 of 179 RX72N Group 1.6.3 1. Overview 176-Pin LFQFP Table 1.7 List of Pin and Pin Functions (176-Pin LFQFP) (1/9) Pin Number Timer Power Supply Clock 176-Pin System LFQFP Control 1 (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC Interrupt A/D D/A P05 SSILRCK1 IRQ13 DA1 P03 SSIDATA1 IRQ11 DA0 AVCC1 4 5 (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) Memory I/F Camera I/F AVSS0 2 3 I/O Port Bus EXDMAC SDRAMC Communication AVSS1 6 P02 TMCI1 SCK6/ SSIBCK1 IRQ10 AN120 7 P01 TMCI0 RXD6/ SMISO6/ SSCL6/ SSIBCK0 IRQ9 AN119 8 P00 TMRI0 TXD6/ SMOSI6/ SSDA6/ AUDIO_CLK IRQ8 AN118 9 PF5 SSILRCK0 IRQ4 10 EMLE 11 12 WAIT# PJ5 POE8# CTS2#/ RTS2#/ SS2#/ SSIRXD0 EPLSOUT0 MTIOC3C CTS6#/ RTS6#/ SS6#/ CTS0#/ RTS0#/ SS0#/ SSITXD0 ET0_EXOU T MTIOC0A/ TMCI3/PO12/ POE10# SCK6/SCK0 ET0_LINK STA MTIOC0D/ TIOCD0/ TMRI3/PO11/ POE4#/ POE11# RXD6/ SMISO6/ SSCL6/ RXD0/ SMISO0/ SSCL0/ CRX0 VSS 13 PJ3 14 VCL 15 VBATT 16 NC 17 TRST# 18 MD/FINED 19 XCIN 20 XCOUT 21 RES# 22 XTAL 23 VSS 24 EXTAL 25 VCC 26 UPSEL EDACK1 PF4 P37 P36 P35 27 P34 28 P33 NMI EDREQ1 R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 IRQ4 PCKO IRQ3-DS Page 53 of 179 RX72N Group Table 1.7 1. Overview List of Pin and Pin Functions (176-Pin LFQFP) (2/9) Pin Number Timer Power Supply Clock 176-Pin System LFQFP Control I/O Port 29 P32 30 TMS PF3 31 TDI PF2 Bus EXDMAC SDRAMC (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) MTIOC0C/ TIOCC0/ TMO3/PO10/ RTCIC2/ RTCOUT/ POE0#/ POE10# Communication (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC TXD6/ SMOSI6/ SSDA6/ TXD0/ SMOSI0/ SSDA0/ CTX0/ USB0_VBUS EN VSYNC Interrupt IRQ2-DS RXD1/ SMISO1/ SSCL1 32 P31 MTIOC4D/ TMCI2/PO9/ RTCIC1 CTS1#/ RTS1#/ SS1#/ SSLB0-A ET1_MDC/ PMGI1_MD C IRQ1-DS 33 P30 MTIOC4B/ TMRI3/PO8/ RTCIC0/ POE8# RXD1/ SMISO1/ SSCL1/ MISOB-A ET1_MDIO / PMGI1_MD IO IRQ0-DS 34 TCK PF1 SCK1 35 TDO PF0 TXD1/ SMOSI1/ SSDA1 36 P27 CS7# MTIOC2B/ TMCI3/PO7 SCK1/ RSPCKB-A ET1_WOL 37 P26 CS6# MTIOC2A/ TMO1/PO6 TXD1/ SMOSI1/ SSDA1/ CTS3#/ RTS3#/ SS3#/ MOSIB-A ET1_EXOU T P25 CS5#/ EDACK1 MTIOC4C/ MTCLKB/ TIOCA4/PO5 RXD3/ SMISO3/ SSCL3/ SSIDATA1 SDHI_CD/ HSYNC P24 CS4#/ EDREQ1 MTIOC4A/ MTCLKA/ TIOCB4/ TMRI1/PO4 SCK3/ USB0_VBUS EN/SSIBCK1 SDHI_WP/ PIXCLK 42 P23 EDACK0 MTIOC3D/ MTCLKD/ TIOCD3/PO3 GTIOC0A TXD3/ SMOSI3/ SSDA3/ CTS0#/ RTS0#/ SS0#/CTX1/ SSIBCK0 SDHI_D1-C/ PIXD7 43 P22 EDREQ0 MTIOC3B/ MTCLKC/ TIOCC3/ TMO0/PO2 GTIOC1A SCK0/ USB0_OVRC URB/ AUDIO_CLK SDHI_D0-C/ PIXD6 44 P21 MTIOC1B/ MTIOC4A/ TIOCA3/ TMCI0/PO1 GTIOC2A RXD0/ SMISO0/ SSCL0/ SCL1/ USB0_EXIC EN/ SSILRCK0 SDHI_CLK-C/ PIXD5 38 CLKOUT 39 VCC 40 41 A/D D/A ADTRG0# VSS R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 IRQ9 Page 54 of 179 RX72N Group Table 1.7 1. Overview List of Pin and Pin Functions (176-Pin LFQFP) (3/9) Pin Number Timer Communication Memory I/F Camera I/F Power Supply Clock 176-Pin System LFQFP Control I/O Port 45 P20 MTIOC1A/ TIOCB3/ TMRI0/PO0 46 P17 MTIOC3A/ GTIOC0B SCK1/TXD3/ EPLSOUT0 SDHI_D3-C/ MTIOC3B/ SMOSI3/ PIXD3 MTIOC4B/ SSDA3/ TIOCB0/ SDA2-DS/ TCLKD/TMO1/ SSITXD0 PO15/POE8# 47 P87 MTIOC4C/ TIOCA2 48 P16 MTIOC3C/ MTIOC3D/ TIOCB1/ TCLKC/TMO2/ PO14/ RTCOUT 49 P86 MTIOC4D/ TIOCA0 50 P15 MTIOC0B/ GTETRGA RXD1/ MTCLKB/ SMISO1/ TIOCB2/ SSCL1/ TCLKB/TMCI2/ SCK3/CRX1PO13 DS/ SSILRCK1 51 P14 MTIOC3A/ GTETRG MTCLKA/ D TIOCB5/ TCLKA/TMRI2/ PO15 52 P13 WR2#/BC2# MTIOC0B/ TIOCA5/ TMO3/PO13 GTADSM1 TXD2/ SMOSI2/ SSDA2/ SDA0[FM+] LCD_TCO IRQ3 N0-A 53 P12 WR3#/BC3# MTIC5U/ TMCI1 GTADSM0 RXD2/ SMISO2/ SSCL2/ SCL0[FM+] LCD_TCO IRQ2 N1-A 54 Bus EXDMAC SDRAMC (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC TXD0/ SMOSI0/ SSDA0/ SDA1/ USB0_ID/ SSIRXD0 GTIOC1B SMOSI10/ SSDA10/ TXD10 SDHI_CMD-C/ PIXD4 Interrupt A/D D/A IRQ8 IRQ7 ADTRG1# IRQ6 ADTRG0# EPLSOUT1 SDHI_D2-C/ PIXD2 TXD1/ SMOSI1/ SSDA1/ RXD3/ SMISO3/ SSCL3/ SCL2-DS/ USB0_VBUS EN/ USB0_VBUS / USB0_OVRC URB GTIOC2B SMISO10/ SSCL10/ RXD10 PIXD1 PIXD0 CTS1#/ RTS1#/ SS1#/CTX1/ USB0_OVRC URA IRQ5 LCD_CLK- IRQ4 A ADTRG1# VCC_USB 55 USB0_DM 56 USB0_DP 57 VSS_USB 58 CLKOUT2 PJ2 5M 59 PJ1 MTIOC6A RXD8/ SMISO8/ SSCL8/ SSLC2-B EPLSOUT1 LCD_TCO N3-A 60 PJ0 MTIOC6B SCK8/ SSLC1-B EPLSOUT0 LCD_DAT A0-A 61 P85 MTIOC6C/ TIOCC0 R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 TXD8/ SMOSI8/ SSDA8/ SSLC3-B LCD_TCO N2-A LCD_DAT A1-A Page 55 of 179 RX72N Group Table 1.7 1. Overview List of Pin and Pin Functions (176-Pin LFQFP) (4/9) Pin Number Timer Power Supply Clock 176-Pin System LFQFP Control I/O Port 62 P84 63 P57 64 CLKOUT2 P56 5M 65 Bus EXDMAC SDRAMC (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) Communication (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) MTIOC6D Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC ET1_LINK STA Interrupt LCD_DAT A2-A RXD7/ SMISO7/ SSCL7/ SSLC0-B LCD_DAT A3-A LCD_DAT A4-A EDACK1 MTIOC3C/ TIOCA1 SCK7/ RSPCKC-B P55 D0[A0/D0]/ EDREQ0/ WAIT# MTIOC4D/ TMO3 TXD7/ SMOSI7/ SSDA7/ MISOC-B/ CRX1 ET0_EXOU T LCD_DAT IRQ10 A5-A 66 P54 D1[A1/D1]/ EDACK0/ ALE MTIOC4B/ TMCI1 CTS2#/ RTS2#/ SS2#/ MOSIC-B/ CTX1 ET0_LINK STA LCD_DAT A6-A 67 P11 MTIC5V/ TMCI3 SCK2 EPLSOUT1 LCD_DAT IRQ1 A7-A 68 P10 ALE 69 P53*1 BCLK 70 P52 RD# RXD2/ SMISO2/ SSCL2/ SSLB3-A 71 P51 WR1#/ BC1#/ WAIT# SCK2/ SSLB2-A 72 P50 WR0#/WR# TXD2/ SMOSI2/ SSDA2/ SSLB1-A P83 EDACK1 MTIOC4C GTIOC0A SCK10/ SS10#/ CTS10# ET0_CRS/ RMII0_CR S_DV PC7 A23/CS0# MTIOC3A/ MTCLKB/ TMO2/PO31/ TOC0/ CACREF GTIOC3A TXD8/ SMOSI8/ SSDA8/ SMOSI10/ SSDA10/ TXD10/ MISOA-A ET0_COL MMC_D7-A LCD_DAT IRQ14 A9-A 77 PC6 D2[A2/D2]/ A22/CS1# MTIOC3C/ MTCLKA/ TMCI2/PO30/ TIC0 GTIOC3B RXD8/ SMISO8/ SSCL8/ SMISO10/ SSCL10/ RXD10/ MOSIA-A ET0_ETXD MMC_D6-A 3 LCD_DAT IRQ13 A10-A 78 PC5 D3[A3/D3]/ A21/CS2#/ WAIT# MTIOC3B/ MTCLKD/ TMRI2/PO29 GTIOC1A SCK8/ RTS8#/ SCK10/ RSPCKA-A ET0_ETXD MMC_D5-A 2 LCD_DAT A11-A 79 P82 EDREQ1 MTIOC4A/ PO28 GTIOC2A SMOSI10/ SSDA10/ TXD10 ET0_ETXD MMC_D4-A 1/ RMII0_TXD 1 LCD_DAT A12-A 80 P81 EDACK0 MTIOC3D/ PO27 GTIOC0B SMISO10/ SSCL10/ RXD10 ET0_ETXD QIO3-A/ 0/ SDHI_CD/ RMII0_TXD MMC_D3-A 0 LCD_DAT A13-A 73 A/D D/A MTIC5W/ TMRI3 IRQ0 VSS 74 75 VCC 76 UB R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 LCD_DAT A8-A Page 56 of 179 RX72N Group Table 1.7 1. Overview List of Pin and Pin Functions (176-Pin LFQFP) (5/9) Pin Number Timer Communication Memory I/F Camera I/F Power Supply Clock 176-Pin System LFQFP Control I/O Port Bus EXDMAC SDRAMC 81 P80 EDREQ0 MTIOC3B/ PO26 82 PC4 A20/CS3# MTIOC3D/ MTCLKC/ TMCI1/PO25/ POE0# GTETRG C 83 PC3 A19 MTIOC4D/ TCLKB/PO24 GTIOC1B TXD5/ SMOSI5/ SSDA5 84 P77 CS7# PO23 SMOSI11/ SSDA11/ TXD11 ET0_RX_E QSPCLK-A/ R/ SDHI_CLK-A/ RMII0_RX_ MMC_CLK-A ER 85 P76 CS6# PO22 SMISO11/ SSCL11/ RXD11 ET0_RX_C QSSL-A/ LCD_DAT LK/ SDHI_CMD-A/ A18-A REF50CK0 MMC_CMD-A 86 PC2 A18 MTIOC4B/ TCLKA/PO21 87 P75 CS5# PO20 SCK11/ RTS11# ET0_ERXD SDHI_D2-A/ LCD_DAT 0/ MMC_RES#-A A20-A RMII0_RX D0 88 P74 A20/CS4# PO19 SS11#/ CTS11# ET0_ERXD 1/ RMII0_RX D1 LCD_DAT A21-A 89 PC1 A17 MTIOC3A/ TCLKD/PO18 SCK5/ SSLA2-A ET0_ERXD 2 LCD_DAT IRQ12 A22-A PC0 A16 MTIOC3C/ TCLKC/PO17 CTS5#/ RTS5#/ SS5#/ SSLA1-A ET0_ERXD 3 IRQ14 93 P73 CS3# PO16 94 PB7 A15 MTIOC3B/ TIOCB5/PO31 TXD9/ SMOSI9/ SSDA9/ SMOSI11/ SSDA11/ TXD11 ET0_CRS/ RMII0_CR S_DV 95 PB6 A14 MTIOC3D/ TIOCA5/PO30 RXD9/ SMISO9/ SSCL9/ SMISO11/ SSCL11/ RXD11 ET0_ETXD 1/ RMII0_TXD 1 96 PB5 A13 MTIOC2A/ MTIOC1B/ TIOCB4/ TMRI1/PO29/ POE4# SCK9/ RTS9#/ SCK11 ET0_ETXD 0/ RMII0_TXD 0 LCD_CLKB 97 PB4 A12 TIOCA4/PO28 CTS9#/ SS9#/SS11#/ CTS11#/ RTS11# ET0_TX_E N/ RMII0_TXD _EN LCD_TCO N0-B 90 (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) SCK10/ RTS10# (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC ET0_TX_E QIO2-A/ N/ SDHI_WP/ RMII0_TXD MMC_D2-A _EN Interrupt A/D D/A LCD_DAT A14-A SCK5/ ET0_TX_C QMI-A/QIO1- LCD_DAT CTS8#/ LK A/SDHI_D1-A/ A15-A SS8#/SS10#/ MMC_D1-A CTS10#/ RTS10#/ SSLA0-A GTIOC2B RXD5/ SMISO5/ SSCL5/ SSLA3-A ET0_TX_E QMO-A/QIO0- LCD_DAT R A/SDHI_D0-A/ A16-A MMC_D0-A ET0_RX_D SDHI_D3-A/ V MMC_CD-A LCD_DAT A17-A LCD_DAT A19-A VCC 91 92 (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) VSS R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 ET0_WOL LCD_EXT CLK-A Page 57 of 179 RX72N Group Table 1.7 1. Overview List of Pin and Pin Functions (176-Pin LFQFP) (6/9) Pin Number Timer Communication Memory I/F Camera I/F Power Supply Clock 176-Pin System LFQFP Control I/O Port Bus EXDMAC SDRAMC 98 PB3 A11 MTIOC0A/ MTIOC4A/ TIOCD3/ TCLKD/TMO0/ PO27/POE11# SCK4/SCK6 ET0_RX_E R/ RMII0_RX_ ER LCD_TCO N1-B 99 PB2 A10 TIOCC3/ TCLKC/PO26 CTS4#/ ET0_RX_C RTS4#/ LK/ SS4#/ REF50CK0 CTS6#/ RTS6#/SS6# LCD_TCO N2-B 100 PB1 A9 MTIOC0C/ MTIOC4C/ TIOCB3/ TMCI0/PO25 TXD4/ SMOSI4/ SSDA4/ TXD6/ SMOSI6/ SSDA6 ET0_ERXD 0/ RMII0_RX D0 LCD_TCO IRQ4-DS N3-B 101 P72 A19/CS2# ET0_MDC/ PMGI0_MD C LCD_DAT A23-A 102 P71 A18/CS1# ET0_MDIO / PMGI0_MD IO PB0 A8 MTIC5W/ TIOCA3/PO24 RXD4/ SMISO4/ SSCL4/ RXD6/ SMISO6/ SSCL6 ET0_ERXD 1/ RMII0_RX D1 LCD_DAT IRQ12 A0-B 106 PA7 A7 TIOCB2/PO23 MISOA-B ET0_WOL LCD_DAT A1-B 107 PA6 A6 MTIC5V/ MTCLKB/ TIOCA2/ TMCI3/PO22/ POE10# ET0_EXOU T LCD_DAT A2-B 108 PA5 A5 MTIOC6B/ GTIOC0A RSPCKA-B TIOCB1/PO21 ET0_LINK STA LCD_DAT A3-B 109 PA4 A4 MTIC5U/ MTCLKA/ TIOCA1/ TMRI0/PO20 TXD5/ SMOSI5/ SSDA5/ SSLA0-B ET0_MDC/ PMGI0_MD C LCD_DAT IRQ5-DS A4-B 110 PA3 A3 MTIOC0D/ MTCLKD/ TIOCD0/ TCLKB/PO19 RXD5/ SMISO5/ SSCL5 ET0_MDIO / PMGI0_MD IO LCD_DAT IRQ6-DS A5-B 111 TRDATA3 PG7 112 PA2 113 TRDATA2 PG6 114 PA1 DQM3/A1 PG5 D29 103 (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC Interrupt A/D D/A VCC 104 105 (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) VSS 115 VCC 116 TRCLK 117 VSS GTETRGB CTS5#/ RTS5#/ SS5#/ MOSIA-B D31 A2 ET1_TX_E R MTIOC7A/ PO18 GTIOC1A RXD5/ SMISO5/ SSCL5/ SSLA3-B D30 R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 LCD_DAT A6-B ET1_ETXD 3 MTIOC0B/ GTIOC2A SCK5/ MTCLKC/ SSLA2-B MTIOC7B/ TIOCB0/PO17 ET0_WOL LCD_DAT IRQ11 A7-B ET1_ETXD 2 Page 58 of 179 RX72N Group Table 1.7 1. Overview List of Pin and Pin Functions (176-Pin LFQFP) (7/9) Pin Number Timer Communication Memory I/F Camera I/F Power Supply Clock 176-Pin System LFQFP Control I/O Port 118 PA0 DQM2/ BC0#/A0 PG4 D28 120 P67 DQM1/ CS7# 121 TRDATA1 PG3 122 P66 123 TRDATA0 PG2 124 P65 CKE/CS5# 125 PE7 D15[A15/ MTIOC6A/ D15]/D7[A7/ TOC1 D7] GTIOC3A MISOB-B SDHI_WP/ LCD_DAT IRQ7 MMC_RES#-B A9-B AN105 126 PE6 D14[A14/ MTIOC6C/ D14]/D6[A6/ TIC1 D6] GTIOC3B MOSIB-B SDHI_CD/ MMC_CD-B LCD_DAT IRQ6 A10-B AN104 P70 SDCLK 130 PE5 D13[A13/ MTIOC4C/ D13]/D5[A5/ MTIOC2B D5] GTIOC0A RSPCKB-B ET0_RX_C LK/ REF50CK0 LCD_DAT IRQ5 A11-B AN103 131 PE4 D12[A12/ MTIOC4D/ D12]/D4[A4/ MTIOC1A/ D4] PO28 GTIOC1A SSLB0-B ET0_ERXD 2 LCD_DAT A12-B AN102 132 PE3 D11[A11/ MTIOC4B/ D11]/D3[A3/ PO26/TOC3/ D3] POE8# GTIOC2A CTS12#/ RTS12#/ SS12# ET0_ERXD MMC_D7-B 3 LCD_DAT A13-B AN101 133 PE2 D10[A10/ MTIOC4A/ D10]/D2[A2/ PO23/TIC3 D2] GTIOC0B RXD12/ SMISO12/ SSCL12/ RXDX12/ SSLB3-B MMC_D6-B LCD_DAT IRQ7-DS A14-B AN100 134 PE1 D9[A9/D9]/ D1[A1/D1] MTIOC4C/ MTIOC3B/ PO18 GTIOC1B TXD12/ SMOSI12/ SSDA12/ TXDX12/ SIOX12/ SSLB2-B MMC_D5-B LCD_DAT A15-B ANEX1 135 PE0 D8[A8/D8]/ D0[A0/D0] MTIOC3D GTIOC2B SCK12/ SSLB1-B MMC_D4-B LCD_DAT A16-B ANEX0 136 P64 WE#/D3[A3/ D3]/CS4# ET1_ETXD 0/ RMII1_TXD 0 137 P63 CAS#/ D2[A2/D2]/ CS3# ET1_ETXD 1/ RMII1_TXD 1 138 P62 RAS#/ D1[A1/D1]/ CS2# ET1_ERXD 0/ RMII1_RX D0 119 127 TRSYNC (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) MTIOC4A/ GTIOC0B SSLA1-B MTIOC6D/ TIOCA0/PO16/ CACREF ET0_TX_E N/ RMII0_TXD _EN Interrupt A/D D/A LCD_DAT A8-B ET1_ETXD 1/ RMII1_TXD 1 MTIOC7C GTIOC1B CRX2 D27 DQM0/ CS6# (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC EPLSOUT1 IRQ15 ET1_ETXD 0/ RMII1_TXD 0 MTIOC7D GTIOC2B CTX2 D26 ET1_TX_C LK VCC 128 129 Bus EXDMAC SDRAMC VSS R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 59 of 179 RX72N Group Table 1.7 1. Overview List of Pin and Pin Functions (176-Pin LFQFP) (8/9) Pin Number Timer Communication Memory I/F Camera I/F Power Supply Clock 176-Pin System LFQFP Control I/O Port 139 P61 SDCS#/ D0[A0/D0]/ CS1# ET1_ERXD 1/ RMII1_RX D1 P60 CS0# ET1_TX_E N/ RMII1_TXD _EN 143 PD7 D7[A7/D7] 144 TRDATA7 PG1 145 PD6 146 TRDATA6 PG0 147 PD5 D5[A5/D5] MTIC5W/ MTIOC8C/ MTCLKA/ POE10# SSLC1-A ET1_MDC/ QSPCLK-B/ PMGI1_MD SDHI_CLK-B/ C MMC_CLK-B LCD_DAT IRQ5 A19-B AN113 148 PD4 D4[A4/D4] MTIOC8B/ POE11# SSLC0-A ET1_MDIO QSSL-B/ LCD_DAT IRQ4 / SDHI_CMD-B/ A20-B PMGI1_MD MMC_CMD-B IO AN112 149 TRSYNC1 P97 150 PD3 140 (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC Interrupt A/D D/A VSS 141 142 Bus EXDMAC SDRAMC VCC 151 VSS 152 TRDATA5 P96 153 VCC MTIC5U/ POE0# SSLC3-A D25 D6[A6/D6] MTIC5V/ MTIOC8A/ POE4# SSLC2-A ET1_RX_C QMO-B/QIO0- LCD_DAT IRQ6 LK/ B/SDHI_D0-B/ A18-B REF50CK1 MMC_D0-B AN106 ET1_RX_C LK/ REF50CK1 D23/A23 ET1_ERXD 3 MTIOC8D/ TOC2/POE8# GTIOC0A RSPCKC-A D22/A22 D2[A2/D2] AN107 ET1_RX_E R/ RMII1_RX_ ER D24 D3[A3/D3] ET1_RX_E QMI-B/QIO1- LCD_DAT IRQ7 R/ B/SDHI_D1-B/ A17-B RMII1_RX_ MMC_D1-B ER ET1_WOL QIO3-B/ SDHI_D3-B/ MMC_D3-B LCD_DAT IRQ3 A21-B AN111 ET1_EXOU QIO2-B/ T SDHI_D2-B/ MMC_D2-B LCD_DAT IRQ2 A22-B AN110 LCD_DAT IRQ1 A23-B AN109 LCD_EXT IRQ0 CLK-B AN108 ET1_ERXD 2 154 PD2 MTIOC4D/ TIC2 GTIOC0B MISOC-A/ CRX0 155 TRDATA4 P95 156 PD1 D1[A1/D1] 157 P94 D20/A20 158 PD0 D0[A0/D0] POE4# 159 P93 D19/A19 POE0# CTS7#/ ET1_LINK RTS7#/SS7# STA AN117 160 P92 D18/A18 POE4# RXD7/ SMISO7/ SSCL7 ET1_CRS/ RMII1_CR S_DV AN116 161 P91 D17/A17 SCK7 ET1_COL AN115 D21/A21 R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 ET1_ERXD 1/ RMII1_RX D1 MTIOC4B/ POE0# GTIOC1A MOSIC-A/ CTX0 ET1_ERXD 0/ RMII1_RX D0 GTIOC1B Page 60 of 179 RX72N Group Table 1.7 1. Overview List of Pin and Pin Functions (176-Pin LFQFP) (9/9) Pin Number Timer Power Supply Clock 176-Pin System LFQFP Control 162 P90 D16/A16 (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC Interrupt A/D D/A VSS 163 164 I/O Port Bus EXDMAC SDRAMC Communication TXD7/ SMOSI7/ SSDA7 ET1_RX_D V AN114 VCC 165 P47 IRQ15-DS AN007 166 P46 IRQ14-DS AN006 167 P45 IRQ13-DS AN005 168 P44 IRQ12-DS AN004 169 P43 IRQ11-DS AN003 170 P42 IRQ10-DS AN002 171 P41 IRQ9-DS AN001 P40 IRQ8-DS AN000 P07 IRQ15 ADTRG0# 172 VREFL0 173 174 VREFH0 175 AVCC0 176 Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled. R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 61 of 179 RX72N Group 1.6.4 1. Overview 145-Pin TFLGA Table 1.8 List of Pin and Pin Functions (145-Pin TFLGA) (1/7) Pin Number Power Supply Clock 145-Pin System TFLGA Control A1 Timer I/O Port Bus EXDMAC SDRAMC (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) Communication (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC Interrupt A/D D/A AVSS0 A2 P07 IRQ15 ADTRG0# A3 P40 IRQ8-DS AN000 A4 P42 IRQ10-DS AN002 A5 P45 A6 P90 A16 A7 P92 A18 POE4# A8 PD2 D2[A2/D2] MTIOC4D/ TIC2 A9 PD6 D6[A6/D6] MTIC5V/ MTIOC8A/ POE4# A11 P62 RAS#/ D1[A1/D1]/ CS2# A12 PE1 D9[A9/D9]/ D1[A1/D1] A13 PE3 D11[A11/ MTIOC4B/ D11]/D3[A3/ PO26/TOC3/ D3] POE8# A10 RXD7/ SMISO7/ SSCL7 GTIOC0B MISOC-A/ CRX0 SSLC2-A AN114 RMII1_CR S_DV AN116 ET1_EXOU QIO2-B/ T SDHI_D2-B/ MMC_D2-B LCD_DAT IRQ2 A22-B AN110 REF50CK1 QMO-B/QIO0- LCD_DAT IRQ6 B/SDHI_D0-B/ A18-B MMC_D0-B AN106 VSS B1 AVCC1 B2 AVCC0 RMII1_RX D0 MTIOC4C/ MTIOC3B/ PO18 GTIOC1B TXD12/ SMOSI12/ SSDA12/ TXDX12/ SIOX12/ SSLB2-B GTIOC2A CTS12#/ RTS12#/ SS12# P05 B3 B4 IRQ13-DS AN005 TXD7/ SMOSI7/ SSDA7 MMC_D5-B LCD_DAT A15-B ANEX1 ET0_ERXD MMC_D7-B 3 LCD_DAT A13-B AN101 SSILRCK1 IRQ13 DA1 VREFL0 B5 P43 IRQ11-DS AN003 B6 P47 IRQ15-DS AN007 B7 P91 A17 B8 PD0 D0[A0/D0] POE4# B9 PD4 D4[A4/D4] MTIOC8B/ POE11# B11 P61 SDCS#/ D0[A0/D0]/ CS1# B12 PE2 D10[A10/ MTIOC4A/ D10]/D2[A2/ PO23/TIC3 D2] GTIOC0B RXD12/ SMISO12/ SSCL12/ RXDX12/ SSLB3-B B13 PE4 D12[A12/ MTIOC4D/ D12]/D4[A4/ MTIOC1A/ D4] PO28 GTIOC1A SSLB0-B B10 C1 SCK7 AN115 GTIOC1B SSLC0-A LCD_EXT IRQ0 CLK-B AN108 ET1_MDIO QSSL-B/ LCD_DAT IRQ4 / SDHI_CMD-B/ A20-B PMGI1_MD MMC_CMD-B IO AN112 VCC RMII1_RX D1 MMC_D6-B ET0_ERXD 2 LCD_DAT IRQ7-DS A14-B AN100 LCD_DAT A12-B AN102 AVSS1 R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 62 of 179 RX72N Group Table 1.8 1. Overview List of Pin and Pin Functions (145-Pin TFLGA) (2/7) Pin Number Timer Power Supply Clock 145-Pin System TFLGA Control I/O Port C2 P02 C3 Bus EXDMAC SDRAMC (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) TMCI1 Communication (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC SCK6/ SSIBCK1 Interrupt A/D D/A IRQ10 AN120 AN001 VREFH0 C4 P41 IRQ9-DS C5 P46 IRQ14-DS AN006 C6 VSS C7 PD1 D1[A1/D1] MTIOC4B/ POE0# GTIOC1A MOSIC-A/ CTX0 C8 PD3 D3[A3/D3] MTIOC8D/ TOC2/POE8# GTIOC0A RSPCKC-A C9 PD7 D7[A7/D7] MTIC5U/ POE0# C10 P63 CAS#/ D2[A2/D2]/ CS3# C11 PE0 D8[A8/D8]/ D0[A0/D0] P70 SDCLK C12 C13 AN109 LCD_DAT IRQ3 A21-B AN111 RMII1_RX_ QMI-B/QIO1- LCD_DAT IRQ7 ER B/SDHI_D1-B/ A17-B MMC_D1-B AN107 ET1_WOL P00 D2 PF5 D3 P03 D4 P01 RMII1_TXD 1 MTIOC3D GTIOC2B SCK12/ SSLB1-B MMC_D4-B TMRI0 WAIT# TXD6/ SMOSI6/ SSDA6/ AUDIO_CLK ANEX0 AN118 SSILRCK0 IRQ4 SSIDATA1 IRQ11 DA0 TMCI0 RXD6/ SMISO6/ SSCL6/ SSIBCK0 IRQ9 AN119 VCC P93 A19 POE0# CTS7#/ ET1_LINK RTS7#/SS7# STA D7 PD5 D5[A5/D5] MTIC5W/ MTIOC8C/ MTCLKA/ POE10# SSLC1-A D8 P60 CS0# RMII1_TXD _EN D9 P64 WE#/ D3[A3/D3]/ CS4# RMII1_TXD 0 D10 PE7 D15[A15/ MTIOC6A/ D15]/D7[A7/ TOC1 D7] GTIOC3A MISOB-B D12 PE5 D13[A13/ MTIOC4C/ D13]/D5[A5/ MTIOC2B D5] GTIOC0A RSPCKB-B D13 PE6 D14[A14/ MTIOC6C/ D14]/D6[A6/ TIC1 D6] GTIOC3B MOSIB-B AN117 ET1_MDC/ QSPCLK-B/ PMGI1_MD SDHI_CLK-B/ C MMC_CLK-B LCD_DAT IRQ5 A19-B AN113 SDHI_WP/ LCD_DAT IRQ7 MMC_RES#-B A9-B AN105 LCD_DAT IRQ5 A11-B AN103 LCD_DAT IRQ6 A10-B AN104 VCC E1 VSS E2 VCL E3 E4 LCD_DAT A16-B IRQ8 D6 D11 QIO3-B/ SDHI_D3-B/ MMC_D3-B VSS D1 D5 SSLC3-A LCD_DAT IRQ1 A23-B PJ5 POE8# CTS2#/ RTS2#/ SS2#/ SSIRXD0 ET0_RX_C LK/ REF50CK0 SDHI_CD/ MMC_CD-B EPLSOUT0 EMLE R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 63 of 179 RX72N Group Table 1.8 1. Overview List of Pin and Pin Functions (145-Pin TFLGA) (3/7) Pin Number Timer Communication Memory I/F Camera I/F Power Supply Clock 145-Pin System TFLGA Control I/O Port E5 P44 E10 PA0 BC0#/A0 MTIOC4A/ GTIOC0B SSLA1-B MTIOC6D/ TIOCA0/PO16/ CACREF E11 P66 DQM0/ CS6# MTIOC7D GTIOC2B CTX2 E12 P65 CKE/CS5# E13 P67 DQM1/ CS7# MTIOC7C GTIOC1B CRX2 PJ3 EDACK1 MTIOC3C CTS6#/ RTS6#/ SS6#/ CTS0#/ RTS0#/ SS0#/ SSITXD0 ET0_EXOU T PA3 A3 MTIOC0D/ MTCLKD/ TIOCD0/ TCLKB/PO19 RXD5/ SMISO5/ SSCL5 ET0_MDIO / PMGI0_MD IO LCD_DAT IRQ6-DS A5-B F12 PA1 A1 MTIOC0B/ GTIOC2A SCK5/ MTCLKC/ SSLA2-B MTIOC7B/ TIOCB0/PO17 ET0_WOL LCD_DAT IRQ11 A7-B F13 PA2 A2 MTIOC7A/ PO18 F1 XCIN F2 XCOUT F3 F4 (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC Interrupt IRQ12-DS AN004 ET0_TX_E N/ RMII0_TXD _EN LCD_DAT A8-B EPLSOUT1 IRQ15 VSS G1 XTAL G2 RES# G3 MD/FINED G4 BSCANP GTIOC1A RXD5/ SMISO5/ SSCL5/ SSLA3-B LCD_DAT A6-B P37 G10 PA5 A5 MTIOC6B/ GTIOC0A RSPCKA-B TIOCB1/PO21 ET0_LINK STA LCD_DAT A3-B G11 PA6 A6 MTIC5V/ MTCLKB/ TIOCA2/ TMCI3/PO22/ POE10# GTETRGB CTS5#/ RTS5#/ SS5#/ MOSIA-B ET0_EXOU T LCD_DAT A2-B PA4 A4 MTIC5U/ MTCLKA/ TIOCA1/ TMRI0/PO20 TXD5/ SMOSI5/ SSDA5/ SSLA0-B ET0_MDC/ PMGI0_MD C LCD_DAT IRQ5-DS A4-B G12 A/D D/A VBATT F10 F11 Bus EXDMAC SDRAMC VCC G13 H1 EXTAL H2 VCC H3 VSS H4 UPSEL P36 P35 NMI H10 P72 A19/CS2# ET0_MDC/ PMGI0_MD C H11 P71 A18/CS1# ET0_MDIO / PMGI0_MD IO R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 64 of 179 RX72N Group Table 1.8 1. Overview List of Pin and Pin Functions (145-Pin TFLGA) (4/7) Pin Number Timer Communication Memory I/F Camera I/F Power Supply Clock 145-Pin System TFLGA Control I/O Port Bus EXDMAC SDRAMC H12 PB0 A8 MTIC5W/ TIOCA3/PO24 RXD4/ SMISO4/ SSCL4/ RXD6/ SMISO6/ SSCL6 ET0_ERXD 1/ RMII0_RX D1 LCD_DAT IRQ12 A0-B H13 PA7 A7 TIOCB2/PO23 MISOA-B ET0_WOL LCD_DAT A1-B MTIOC0A/ TMCI3/PO12/ POE10# SCK6/SCK0 ET0_LINK STA MTIOC0D/ TIOCD0/ TMRI3/PO11/ POE4#/ POE11# RXD6/ SMISO6/ SSCL6/ RXD0/ SMISO0/ SSCL0/ CRX0 PCKO IRQ3-DS VSYNC IRQ2-DS J1 TRST# P34 (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) J2 P33 J3 P32 MTIOC0C/ TIOCC0/ TMO3/PO10/ RTCIC2/ RTCOUT/ POE0#/ POE10# TXD6/ SMOSI6/ SSDA6/ TXD0/ SMOSI0/ SSDA0/ CTX0/ USB0_VBUS EN P30 MTIOC4B/ TMRI3/PO8/ RTCIC0/ POE8# RXD1/ SMISO1/ SSCL1/ MISOB-A J4 TDI EDREQ1 (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC Interrupt IRQ4 ET1_MDIO / PMGI1_MD IO IRQ0-DS J10 PB3 A11 MTIOC0A/ MTIOC4A/ TIOCD3/ TCLKD/TMO0/ PO27/POE11# SCK4/SCK6 ET0_RX_E R/ RMII0_RX_ ER LCD_TCO N1-B J11 PB4 A12 TIOCA4/PO28 CTS9#/ SS9#/SS11#/ CTS11#/ RTS11# ET0_TX_E N/ RMII0_TXD _EN LCD_TCO N0-B J12 PB2 A10 TIOCC3/ TCLKC/PO26 CTS4#/ ET0_RX_C RTS4#/ LK/ SS4#/ REF50CK0 CTS6#/ RTS6#/SS6# LCD_TCO N2-B J13 PB1 A9 MTIOC0C/ MTIOC4C/ TIOCB3/ TMCI0/PO25 TXD4/ SMOSI4/ SSDA4/ TXD6/ SMOSI6/ SSDA6 ET0_ERXD 0/ RMII0_RX D0 LCD_TCO IRQ4-DS N3-B K1 TCK P27 CS7# MTIOC2B/ TMCI3/PO7 SCK1/ RSPCKB-A ET1_WOL K2 TDO P26 CS6# MTIOC2A/ TMO1/PO6 TXD1/ SMOSI1/ SSDA1/ CTS3#/ RTS3#/ SS3#/ MOSIB-A ET1_EXOU T K3 TMS P31 MTIOC4D/ TMCI2/PO9/ RTCIC1 CTS1#/ RTS1#/ SS1#/ SSLB0-A ET1_MDC/ PMGI1_MD C P15 MTIOC0B/ GTETRGA RXD1/ MTCLKB/ SMISO1/ TIOCB2/ SSCL1/ TCLKB/TMCI2/ SCK3/CRX1PO13 DS/ SSILRCK1 K4 R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 A/D D/A IRQ1-DS PIXD0 IRQ5 Page 65 of 179 RX72N Group Table 1.8 1. Overview List of Pin and Pin Functions (145-Pin TFLGA) (5/7) Pin Number Power Supply Clock 145-Pin System TFLGA Control K5 Timer I/O Port TRDATA2 P54 Bus EXDMAC SDRAMC ALE/ D1[A1/D1]/ EDACK0 K6 P53*1 BCLK K7 P51 WR1#/ BC1#/ WAIT# (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) MTIOC4B/ TMCI1 Communication (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) CTS2#/ RTS2#/ SS2#/CTX1 Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC SCK2/ SSLB2-A VCC K9 TRDATA0 P80 EDREQ0 MTIOC3B/ PO26 SCK10/ RTS10# ET0_TX_E QIO2-A/ N/ SDHI_WP/ RMII0_TXD MMC_D2-A _EN K10 TRDATA6 P76 CS6# PO22 SMISO11/ SSCL11/ RXD11 ET0_RX_C QSSL-A/ LK/ SDHI_CMD-A/ REF50CK0 MMC_CMD-A K11 PB7 A15 MTIOC3B/ TIOCB5/PO31 TXD9/ SMOSI9/ SSDA9/ SMOSI11/ SSDA11/ TXD11 ET0_CRS/ RMII0_CR S_DV K12 PB6 A14 MTIOC3D/ TIOCA5/PO30 RXD9/ SMISO9/ SSCL9/ SMISO11/ SSCL11/ RXD11 ET0_ETXD 1/ RMII0_TXD 1 K13 PB5 A13 MTIOC2A/ MTIOC1B/ TIOCB4/ TMRI1/PO29/ POE4# SCK9/ RTS9#/ SCK11 ET0_ETXD 0/ RMII0_TXD 0 P25 CS5#/ EDACK1 MTIOC4C/ MTCLKB/ TIOCA4/PO5 RXD3/ SMISO3/ SSCL3/ SSIDATA1 L2 P23 EDACK0 MTIOC3D/ MTCLKD/ TIOCD3/PO3 L3 P16 L4 P24 L5 P13 L6 CLKOUT2 P56 5M CLKOUT CS4#/ EDREQ1 R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 GTIOC0A TXD3/ SMOSI3/ SSDA3/ CTS0#/ RTS0#/ SS0#/CTX1/ SSIBCK0 MTIOC3C/ MTIOC3D/ TIOCB1/ TCLKC/TMO2/ PO14/ RTCOUT TXD1/ SMOSI1/ SSDA1/ RXD3/ SMISO3/ SSCL3/ SCL2-DS/ USB0_VBUS EN/ USB0_VBUS / USB0_OVRC URB MTIOC4A/ MTCLKA/ TIOCB4/ TMRI1/PO4 SCK3/ USB0_VBUS EN/SSIBCK1 MTIOC0B/ TIOCA5/ TMO3/PO13 EDACK1 A/D D/A ET0_LINK STA K8 L1 Interrupt MTIOC3C/ TIOCA1 GTADSM1 TXD2/ SMOSI2/ SSDA2/ SDA0[FM+] LCD_CLKB SDHI_CD/ HSYNC ADTRG0# SDHI_D1-C/ PIXD7 IRQ6 ADTRG0# IRQ3 ADTRG1# SDHI_WP/ PIXCLK SCK7 Page 66 of 179 RX72N Group Table 1.8 1. Overview List of Pin and Pin Functions (145-Pin TFLGA) (6/7) Pin Number Timer Communication Memory I/F Camera I/F Power Supply Clock 145-Pin System TFLGA Control I/O Port Bus EXDMAC SDRAMC L7 P52 RD# P83 EDACK1 MTIOC4C GTIOC0A SCK10/ SS10#/ CTS10# ET0_CRS/ RMII0_CR S_DV L9 PC5 D3[A3/D3]/ A21/CS2#/ WAIT# MTIOC3B/ MTCLKD/ TMRI2/PO29 GTIOC1A SCK8/ RTS8#/ SCK10/ RSPCKA-A ET0_ETXD MMC_D5-A 2 L10 PC4 A20/CS3# MTIOC3D/ MTCLKC/ TMCI1/PO25/ POE0# GTETRG C L11 PC2 A18 MTIOC4B/ TCLKA/PO21 GTIOC2B RXD5/ SMISO5/ SSCL5/ SSLA3-A L12 TRDATA4 P73 CS3# PO16 L13 VSS EDREQ0 MTIOC3B/ MTCLKC/ TIOCC3/ TMO0/PO2 L8 TRCLK (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC ET0_WOL P17 MTIOC3A/ GTIOC0B SCK1/TXD3/ EPLSOUT0 SDHI_D3-C/ MTIOC3B/ SMOSI3/ PIXD3 MTIOC4B/ SSDA3/ TIOCB0/ SDA2-DS/ TCLKD/TMO1/ SSITXD0 PO15/POE8# M3 P86 MTIOC4D/ TIOCA0 GTIOC2B SMISO10/ SSCL10/ RXD10 M4 P12 TMCI1 GTADSM0 RXD2/ SMISO2/ SSCL2/ SCL0[FM+] VSS_USB GTIOC1A SCK0/ USB0_OVRC URB/ AUDIO_CLK SDHI_D0-C/ PIXD6 PIXD1 IRQ2 M7 P50 WR0#/WR# M8 PC6 D2[A2/D2]/ A22/CS1# MTIOC3C/ MTCLKA/ TMCI2/PO30/ TIC0 GTIOC3B RXD8/ SMISO8/ SSCL8/ SMISO10/ SSCL10/ RXD10/ MOSIA-A ET0_ETXD MMC_D6-A 3 M9 TRDATA1 P81 EDACK0 MTIOC3D/ PO27 GTIOC0B SMISO10/ SSCL10/ RXD10 ET0_ETXD QIO3-A/ 0/ SDHI_CD/ RMII0_TXD MMC_D3-A 0 M10 TRDATA7 P77 CS7# PO23 SMOSI11/ SSDA11/ TXD11 ET0_RX_E QSPCLK-A/ R/ SDHI_CLK-A/ RMII0_RX_ MMC_CLK-A ER M11 PC0 A16 MTIOC3C/ TCLKC/PO17 CTS5#/ RTS5#/ SS5#/ SSLA1-A ET0_ERXD 3 R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 ADTRG1# ET0_RX_D SDHI_D3-A/ V MMC_CD-A M2 VCC_USB IRQ7 SCK5/ ET0_TX_C QMI-A/ CTS8#/ LK QIO1-A/ SS8#/SS10#/ SDHI_D1-A/ CTS10#/ MMC_D1-A RTS10#/ SSLA0-A P22 M6 A/D D/A RXD2/ SMISO2/ SSCL2/ SSLB3-A M1 M5 Interrupt TXD2/ SMOSI2/ SSDA2/ SSLB1-A IRQ13 IRQ14 Page 67 of 179 RX72N Group Table 1.8 1. Overview List of Pin and Pin Functions (145-Pin TFLGA) (7/7) Pin Number Timer Power Supply Clock 145-Pin System TFLGA Control I/O Port Bus EXDMAC SDRAMC M12 PC1 A17 M13 (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) Communication (GPTW, POEG) MTIOC3A/ TCLKD/PO18 (SCI, RSPI, RIIC, CAN, USB, SSIE) (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC SCK5/ SSLA2-A ET0_ERXD 2 Interrupt A/D D/A IRQ12 VCC N1 P21 MTIOC1B/ MTIOC4A/ TIOCA3/ TMCI0/PO1 N2 P20 MTIOC1A/ TIOCB3/ TMRI0/PO0 N3 P87 MTIOC4C/ TIOCA2 N4 P14 MTIOC3A/ GTETRG MTCLKA/ D TIOCB5/ TCLKA/TMRI2/ PO15 N5 GTIOC2A RXD0/ SMISO0/ SSCL0/ SCL1/ USB0_EXIC EN/ SSILRCK0 TXD0/ SMOSI0/ SSDA0/ SDA1/ USB0_ID/ SSIRXD0 GTIOC1B SMOSI10/ SSDA10/ TXD10 SDHI_CLK-C/ PIXD5 IRQ9 SDHI_CMD-C/ PIXD4 IRQ8 EPLSOUT1 SDHI_D2-C/ PIXD2 CTS1#/ RTS1#/ SS1#/CTX1/ USB0_OVRC URA IRQ4 USB0_DM N6 N7 Memory I/F Camera I/F USB0_DP TRDATA3 P55 D0[A0/D0]/ WAIT#/ EDREQ0 MTIOC4D/ TMO3 TXD7/ SMOSI7/ SSDA7/ CRX1 ET0_EXOU T IRQ10 N8 VSS N9 UB PC7 A23/CS0# MTIOC3A/ MTCLKB/ TMO2/PO31/ TOC0/ CACREF GTIOC3A TXD8/ SMOSI8/ SSDA8/ SMOSI10/ SSDA10/ TXD10/ MISOA-A ET0_COL N10 TRSYNC P82 EDREQ1 MTIOC4A/ PO28 GTIOC2A SMOSI10/ SSDA10/ TXD10 ET0_ETXD MMC_D4-A 1/ RMII0_TXD 1 N11 PC3 A19 MTIOC4D/ TCLKB/PO24 GTIOC1B TXD5/ SMOSI5/ SSDA5 ET0_TX_E QMO-A/QIO0R A/SDHI_D0-A/ MMC_D0-A N12 TRSYNC1 P75 CS5# PO20 SCK11/ RTS11# ET0_ERXD SDHI_D2-A/ 0/ MMC_RES#-A RMII0_RX D0 N13 TRDATA5 P74 A20/CS4# PO19 SS11#/ CTS11# ET0_ERXD 1/ RMII0_RX D1 MMC_D7-A IRQ14 Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled. R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 68 of 179 RX72N Group 1.6.5 1. Overview 144-Pin LFQFP Table 1.9 List of Pin and Pin Functions (144-Pin LFQFP) (1/7) Pin Number Power Supply Clock 144-Pin System LFQFP Control 1 (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC Interrupt A/D D/A P05 SSILRCK1 IRQ13 DA1 P03 SSIDATA1 IRQ11 DA0 AVCC1 4 5 I/O Port Bus EXDMAC SDRAMC Communication AVSS0 2 3 Timer AVSS1 6 P02 TMCI1 SCK6/ SSIBCK1 IRQ10 AN120 7 P01 TMCI0 RXD6/ SMISO6/ SSCL6/ SSIBCK0 IRQ9 AN119 8 P00 TMRI0 TXD6/ SMOSI6/ SSDA6/ AUDIO_CLK IRQ8 AN118 9 PF5 SSILRCK0 IRQ4 10 EMLE 11 12 PJ5 POE8# CTS2#/ RTS2#/ SS2#/ SSIRXD0 EPLSOUT0 MTIOC3C CTS6#/ RTS6#/ SS6#/ CTS0#/ RTS0#/ SS0#/ SSITXD0 ET0_EXOU T VSS 13 PJ3 14 VCL 15 VBATT 16 MD/FINED 17 XCIN 18 XCOUT 19 RES# 20 XTAL 21 VSS EDACK1 P37 22 EXTAL 23 VCC 24 UPSEL P35 25 TRST# P34 26 WAIT# P36 P33 NMI EDREQ1 R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 MTIOC0A/ TMCI3/PO12/ POE10# SCK6/SCK0 ET0_LINK STA MTIOC0D/ TIOCD0/ TMRI3/PO11/ POE4#/ POE11# RXD6/ SMISO6/ SSCL6/ RXD0/ SMISO0/ SSCL0/ CRX0 IRQ4 PCKO IRQ3-DS Page 69 of 179 RX72N Group Table 1.9 1. Overview List of Pin and Pin Functions (144-Pin LFQFP) (2/7) Pin Number Timer Communication Power Supply Clock 144-Pin System LFQFP Control I/O Port 27 P32 MTIOC0C/ TIOCC0/ TMO3/PO10/ RTCIC2/ RTCOUT/ POE0#/ POE10# TXD6/ SMOSI6/ SSDA6/ TXD0/ SMOSI0/ SSDA0/ CTX0/ USB0_VBUS EN Bus EXDMAC SDRAMC (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC VSYNC Interrupt IRQ2-DS 28 TMS P31 MTIOC4D/ TMCI2/PO9/ RTCIC1 CTS1#/ RTS1#/ SS1#/ SSLB0-A ET1_MDC/ PMGI1_MD C IRQ1-DS 29 TDI P30 MTIOC4B/ TMRI3/PO8/ RTCIC0/ POE8# RXD1/ SMISO1/ SSCL1/ MISOB-A ET1_MDIO / PMGI1_MD IO IRQ0-DS 30 TCK P27 CS7# MTIOC2B/ TMCI3/PO7 SCK1/ RSPCKB-A ET1_WOL 31 TDO P26 CS6# MTIOC2A/ TMO1/PO6 TXD1/ SMOSI1/ SSDA1/ CTS3#/ RTS3#/ SS3#/ MOSIB-A ET1_EXOU T 32 CLKOUT P25 CS5#/ EDACK1 MTIOC4C/ MTCLKB/ TIOCA4/PO5 RXD3/ SMISO3/ SSCL3/ SSIDATA1 SDHI_CD/ HSYNC 33 P24 CS4#/ EDREQ1 MTIOC4A/ MTCLKA/ TIOCB4/ TMRI1/PO4 SCK3/ USB0_VBUS EN/SSIBCK1 SDHI_WP/ PIXCLK 34 P23 EDACK0 MTIOC3D/ MTCLKD/ TIOCD3/PO3 GTIOC0A TXD3/ SMOSI3/ SSDA3/ CTS0#/ RTS0#/ SS0#/CTX1/ SSIBCK0 SDHI_D1-C/ PIXD7 35 P22 EDREQ0 MTIOC3B/ MTCLKC/ TIOCC3/ TMO0/PO2 GTIOC1A SCK0/ USB0_OVRC URB/ AUDIO_CLK SDHI_D0-C/ PIXD6 36 P21 MTIOC1B/ MTIOC4A/ TIOCA3/ TMCI0/PO1 GTIOC2A RXD0/ SMISO0/ SSCL0/ SCL1/ USB0_EXIC EN/ SSILRCK0 SDHI_CLK-C/ PIXD5 IRQ9 37 P20 MTIOC1A/ TIOCB3/ TMRI0/PO0 SDHI_CMD-C/ PIXD4 IRQ8 38 P17 MTIOC3A/ GTIOC0B SCK1/TXD3/ EPLSOUT0 SDHI_D3-C/ MTIOC3B/ SMOSI3/ PIXD3 MTIOC4B/ SSDA3/ TIOCB0/ SDA2-DS/ TCLKD/TMO1/ SSITXD0 PO15/POE8# 39 P87 MTIOC4C/ TIOCA2 R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 TXD0/ SMOSI0/ SSDA0/ SDA1/ USB0_ID/ SSIRXD0 GTIOC1B SMOSI10/ SSDA10/ TXD10 A/D D/A ADTRG0# IRQ7 ADTRG1# EPLSOUT1 SDHI_D2-C/ PIXD2 Page 70 of 179 RX72N Group Table 1.9 1. Overview List of Pin and Pin Functions (144-Pin LFQFP) (3/7) Pin Number Timer Communication Memory I/F Camera I/F Power Supply Clock 144-Pin System LFQFP Control I/O Port 40 P16 MTIOC3C/ MTIOC3D/ TIOCB1/ TCLKC/TMO2/ PO14/ RTCOUT 41 P86 MTIOC4D/ TIOCA0 42 P15 MTIOC0B/ GTETRGA RXD1/ MTCLKB/ SMISO1/ TIOCB2/ SSCL1/ TCLKB/TMCI2/ SCK3/CRX1PO13 DS/ SSILRCK1 43 P14 MTIOC3A/ GTETRG MTCLKA/ D TIOCB5/ TCLKA/TMRI2/ PO15 44 P13 MTIOC0B/ TIOCA5/ TMO3/PO13 GTADSM1 TXD2/ SMOSI2/ SSDA2/ SDA0[FM+] IRQ3 45 P12 TMCI1 GTADSM0 RXD2/ SMISO2/ SSCL2/ SCL0[FM+] IRQ2 46 Bus EXDMAC SDRAMC (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC TXD1/ SMOSI1/ SSDA1/ RXD3/ SMISO3/ SSCL3/ SCL2-DS/ USB0_VBUS EN/ USB0_VBUS / USB0_OVRC URB GTIOC2B SMISO10/ SSCL10/ RXD10 Interrupt A/D D/A IRQ6 ADTRG0# PIXD1 PIXD0 CTS1#/ RTS1#/ SS1#/CTX1/ USB0_OVRC URA IRQ5 IRQ4 ADTRG1# VCC_USB 47 USB0_DM 48 USB0_DP 49 VSS_USB 50 CLKOUT2 P56 5M EDACK1 MTIOC3C/ TIOCA1 SCK7 51 TRDATA3 P55 D0[A0/D0]/ WAIT#/ EDREQ0 MTIOC4D/ TMO3 TXD7/ SMOSI7/ SSDA7/ CRX1 ET0_EXOU T 52 TRDATA2 P54 ALE/D1[A1/ MTIOC4B/ D1]/ TMCI1 EDACK0 CTS2#/ RTS2#/ SS2#/CTX1 ET0_LINK STA 53 P53*1 BCLK 54 P52 RD# RXD2/ SMISO2/ SSCL2/ SSLB3-A 55 P51 WR1#/ BC1#/ WAIT# SCK2/ SSLB2-A 56 P50 WR0#/WR# TXD2/ SMOSI2/ SSDA2/ SSLB1-A P83 EDACK1 57 VSS 58 TRCLK 59 VCC R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 MTIOC4C GTIOC0A SCK10/ SS10#/ CTS10# IRQ10 ET0_CRS/ RMII0_CR S_DV Page 71 of 179 RX72N Group Table 1.9 1. Overview List of Pin and Pin Functions (144-Pin LFQFP) (4/7) Pin Number Timer Power Supply Clock 144-Pin System LFQFP Control I/O Port Bus EXDMAC SDRAMC 60 PC7 A23/CS0# MTIOC3A/ MTCLKB/ TMO2/PO31/ TOC0/ CACREF 61 PC6 D2[A2/D2]/ A22/CS1# 62 PC5 UB (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) Communication (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC Interrupt GTIOC3A TXD8/ SMOSI8/ SSDA8/ SMOSI10/ SSDA10/ TXD10/ MISOA-A ET0_COL MMC_D7-A IRQ14 MTIOC3C/ MTCLKA/ TMCI2/PO30/ TIC0 GTIOC3B RXD8/ SMISO8/ SSCL8/ SMISO10/ SSCL10/ RXD10/ MOSIA-A ET0_ETXD MMC_D6-A 3 IRQ13 D3[A3/D3]/ A21/CS2#/ WAIT# MTIOC3B/ MTCLKD/ TMRI2/PO29 GTIOC1A SCK8/ RTS8#/ SCK10/ RSPCKA-A ET0_ETXD MMC_D5-A 2 63 TRSYNC P82 EDREQ1 MTIOC4A/ PO28 GTIOC2A SMOSI10/ SSDA10/ TXD10 ET0_ETXD MMC_D4-A 1/ RMII0_TXD 1 64 TRDATA1 P81 EDACK0 MTIOC3D/ PO27 GTIOC0B SMISO10/ SSCL10/ RXD10 ET0_ETXD QIO3-A/ 0/ SDHI_CD/ RMII0_TXD MMC_D3-A 0 65 TRDATA0 P80 EDREQ0 MTIOC3B/ PO26 66 PC4 A20/CS3# MTIOC3D/ MTCLKC/ TMCI1/PO25/ POE0# GTETRG C 67 PC3 A19 MTIOC4D/ TCLKB/PO24 GTIOC1B TXD5/ SMOSI5/ SSDA5 68 TRDATA7 P77 CS7# PO23 SMOSI11/ SSDA11/ TXD11 ET0_RX_E QSPCLK-A/ SDHI_CLK-A/ R/ RMII0_RX_ MMC_CLK-A ER 69 TRDATA6 P76 CS6# PO22 SMISO11/ SSCL11/ RXD11 ET0_RX_C QSSL-A/ LK/ SDHI_CMD-A/ REF50CK0 MMC_CMD-A 70 PC2 A18 MTIOC4B/ TCLKA/PO21 71 TRSYNC1 P75 CS5# PO20 SCK11/ RTS11# ET0_ERXD SDHI_D2-A/ 0/ MMC_RES#-A RMII0_RX D0 72 TRDATA5 P74 A20/CS4# PO19 SS11#/ CTS11# ET0_ERXD 1/ RMII0_RX D1 73 PC1 A17 MTIOC3A/ TCLKD/PO18 SCK5/ SSLA2-A ET0_ERXD 2 IRQ12 PC0 A16 MTIOC3C/ TCLKC/PO17 CTS5#/ RTS5#/ SS5#/ SSLA1-A ET0_ERXD 3 IRQ14 CS3# PO16 74 SCK10/ RTS10# A/D D/A ET0_TX_E QIO2-A/ N/ SDHI_WP/ RMII0_TXD MMC_D2-A _EN SCK5/ ET0_TX_C QMI-A/ CTS8#/ LK QIO1-A/ SS8#/SS10#/ SDHI_D1-A/ CTS10#/ MMC_D1-A RTS10#/ SSLA0-A GTIOC2B RXD5/ SMISO5/ SSCL5/ SSLA3-A ET0_TX_E QMO-A/QIO0R A/SDHI_D0-A/ MMC_D0-A ET0_RX_D SDHI_D3-A/ V MMC_CD-A VCC 75 76 VSS 77 TRDATA4 P73 R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 ET0_WOL Page 72 of 179 RX72N Group Table 1.9 1. Overview List of Pin and Pin Functions (144-Pin LFQFP) (5/7) Pin Number Timer Communication Memory I/F Camera I/F Power Supply Clock 144-Pin System LFQFP Control I/O Port Bus EXDMAC SDRAMC 78 PB7 A15 MTIOC3B/ TIOCB5/PO31 TXD9/ SMOSI9/ SSDA9/ SMOSI11/ SSDA11/ TXD11 ET0_CRS/ RMII0_CR S_DV 79 PB6 A14 MTIOC3D/ TIOCA5/PO30 RXD9/ SMISO9/ SSCL9/ SMISO11/ SSCL11/ RXD11 ET0_ETXD 1/ RMII0_TXD 1 80 PB5 A13 MTIOC2A/ MTIOC1B/ TIOCB4/ TMRI1/PO29/ POE4# SCK9/ RTS9#/ SCK11 ET0_ETXD 0/ RMII0_TXD 0 LCD_CLKB 81 PB4 A12 TIOCA4/PO28 CTS9#/ SS9#/SS11#/ CTS11#/ RTS11# ET0_TX_E N/ RMII0_TXD _EN LCD_TCO N0-B 82 PB3 A11 MTIOC0A/ MTIOC4A/ TIOCD3/ TCLKD/TMO0/ PO27/POE11# SCK4/SCK6 ET0_RX_E R/ RMII0_RX_ ER LCD_TCO N1-B 83 PB2 A10 TIOCC3/ TCLKC/PO26 CTS4#/ ET0_RX_C RTS4#/ LK/ SS4#/ REF50CK0 CTS6#/ RTS6#/SS6# LCD_TCO N2-B 84 PB1 A9 MTIOC0C/ MTIOC4C/ TIOCB3/ TMCI0/PO25 TXD4/ SMOSI4/ SSDA4/ TXD6/ SMOSI6/ SSDA6 LCD_TCO IRQ4-DS N3-B 85 P72 A19/CS2# ET0_MDC/ PMGI0_MD C 86 P71 A18/CS1# ET0_MDIO / PMGI0_MD IO 87 PB0 A8 MTIC5W/ TIOCA3/PO24 RXD4/ SMISO4/ SSCL4/ RXD6/ SMISO6/ SSCL6 ET0_ERXD 1/ RMII0_RX D1 LCD_DAT IRQ12 A0-B 88 PA7 A7 TIOCB2/PO23 MISOA-B ET0_WOL LCD_DAT A1-B 89 PA6 A6 MTIC5V/ MTCLKB/ TIOCA2/ TMCI3/PO22/ POE10# ET0_EXOU T LCD_DAT A2-B 90 PA5 A5 MTIOC6B/ GTIOC0A RSPCKA-B TIOCB1/PO21 ET0_LINK STA LCD_DAT A3-B PA4 A4 MTIC5U/ MTCLKA/ TIOCA1/ TMRI0/PO20 ET0_MDC/ PMGI0_MD C LCD_DAT IRQ5-DS A4-B 91 (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) GTETRGB CTS5#/ RTS5#/ SS5#/ MOSIA-B (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC ET0_ERXD 0/ RMII0_RX D0 Interrupt A/D D/A VCC 92 93 (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) TXD5/ SMOSI5/ SSDA5/ SSLA0-B VSS R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 73 of 179 RX72N Group Table 1.9 1. Overview List of Pin and Pin Functions (144-Pin LFQFP) (6/7) Pin Number Timer Communication Memory I/F Camera I/F Power Supply Clock 144-Pin System LFQFP Control I/O Port Bus EXDMAC SDRAMC 94 PA3 A3 MTIOC0D/ MTCLKD/ TIOCD0/ TCLKB/PO19 95 PA2 A2 MTIOC7A/ PO18 96 PA1 A1 MTIOC0B/ GTIOC2A SCK5/ MTCLKC/ SSLA2-B MTIOC7B/ TIOCB0/PO17 ET0_WOL LCD_DAT IRQ11 A7-B 97 PA0 BC0#/A0 MTIOC4A/ GTIOC0B SSLA1-B MTIOC6D/ TIOCA0/PO16/ CACREF ET0_TX_E N/ RMII0_TXD _EN LCD_DAT A8-B 98 P67 DQM1/ CS7# MTIOC7C GTIOC1B CRX2 EPLSOUT1 99 P66 DQM0/ CS6# MTIOC7D GTIOC2B CTX2 100 P65 CKE/CS5# 101 PE7 D15[A15/ MTIOC6A/ D15]/D7[A7/ TOC1 D7] GTIOC3A MISOB-B SDHI_WP/ LCD_DAT IRQ7 MMC_RES#-B A9-B AN105 102 PE6 D14[A14/ MTIOC6C/ D14]/D6[A6/ TIC1 D6] GTIOC3B MOSIB-B SDHI_CD/ MMC_CD-B LCD_DAT IRQ6 A10-B AN104 P70 SDCLK 106 PE5 D13[A13/ MTIOC4C/ D13]/D5[A5/ MTIOC2B D5] GTIOC0A RSPCKB-B ET0_RX_C LK/ REF50CK0 LCD_DAT IRQ5 A11-B AN103 107 PE4 D12[A12/ MTIOC4D/ D12]/D4[A4/ MTIOC1A/ D4] PO28 GTIOC1A SSLB0-B ET0_ERXD 2 LCD_DAT A12-B AN102 108 PE3 D11[A11/ MTIOC4B/ D11]/D3[A3/ PO26/TOC3/ D3] POE8# GTIOC2A CTS12#/ RTS12#/ SS12# ET0_ERXD MMC_D7-B 3 LCD_DAT A13-B AN101 109 PE2 D10[A10/ MTIOC4A/ D10]/D2[A2/ PO23/TIC3 D2] GTIOC0B RXD12/ SMISO12/ SSCL12/ RXDX12/ SSLB3-B MMC_D6-B LCD_DAT IRQ7-DS A14-B AN100 110 PE1 D9[A9/D9]/ D1[A1/D1] MTIOC4C/ MTIOC3B/ PO18 GTIOC1B TXD12/ SMOSI12/ SSDA12/ TXDX12/ SIOX12/ SSLB2-B MMC_D5-B LCD_DAT A15-B ANEX1 111 PE0 D8[A8/D8]/ D0[A0/D0] MTIOC3D GTIOC2B SCK12/ SSLB1-B MMC_D4-B LCD_DAT A16-B ANEX0 112 P64 WE#/D3[A3/ D3]/CS4# RMII1_TXD 0 113 P63 CAS#/ D2[A2/D2]/ CS3# RMII1_TXD 1 114 P62 RAS#/ D1[A1/D1]/ CS2# RMII1_RX D0 115 P61 SDCS#/ D0[A0/D0]/ CS1# RMII1_RX D1 103 116 (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) RXD5/ SMISO5/ SSCL5 (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC ET0_MDIO / PMGI0_MD IO Interrupt A/D D/A LCD_DAT IRQ6-DS A5-B GTIOC1A RXD5/ SMISO5/ SSCL5/ SSLA3-B LCD_DAT A6-B IRQ15 VCC 104 105 (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) VSS VSS R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 74 of 179 RX72N Group Table 1.9 1. Overview List of Pin and Pin Functions (144-Pin LFQFP) (7/7) Pin Number Timer Communication Memory I/F Camera I/F Power Supply Clock 144-Pin System LFQFP Control I/O Port Bus EXDMAC SDRAMC 117 P60 CS0# 119 PD7 D7[A7/D7] MTIC5U/ POE0# SSLC3-A RMII1_RX_ QMI-B/ ER QIO1-B/ SDHI_D1-B/ MMC_D1-B LCD_DAT IRQ7 A17-B AN107 120 PD6 D6[A6/D6] MTIC5V/ MTIOC8A/ POE4# SSLC2-A REF50CK1 QMO-B/QIO0- LCD_DAT IRQ6 B/SDHI_D0-B/ A18-B MMC_D0-B AN106 121 PD5 D5[A5/D5] MTIC5W/ MTIOC8C/ MTCLKA/ POE10# SSLC1-A ET1_MDC/ QSPCLK-B/ PMGI1_MD SDHI_CLK-B/ C MMC_CLK-B LCD_DAT IRQ5 A19-B AN113 122 PD4 D4[A4/D4] MTIOC8B/ POE11# SSLC0-A ET1_MDIO QSSL-B/ LCD_DAT IRQ4 / SDHI_CMD-B/ A20-B PMGI1_MD MMC_CMD-B IO AN112 123 PD3 D3[A3/D3] MTIOC8D/ TOC2/POE8# GTIOC0A RSPCKC-A ET1_WOL QIO3-B/ SDHI_D3-B/ MMC_D3-B LCD_DAT IRQ3 A21-B AN111 124 PD2 D2[A2/D2] MTIOC4D/ TIC2 GTIOC0B MISOC-A/ CRX0 ET1_EXOU QIO2-B/ T SDHI_D2-B/ MMC_D2-B LCD_DAT IRQ2 A22-B AN110 125 PD1 D1[A1/D1] MTIOC4B/ POE0# GTIOC1A MOSIC-A/ CTX0 LCD_DAT IRQ1 A23-B AN109 126 PD0 D0[A0/D0] POE4# GTIOC1B LCD_EXT IRQ0 CLK-B AN108 127 P93 A19 POE0# CTS7#/ ET1_LINK RTS7#/SS7# STA AN117 128 P92 A18 POE4# RXD7/ SMISO7/ SSCL7 AN116 P91 A17 SCK7 AN115 P90 A16 TXD7/ SMOSI7/ SSDA7 AN114 118 (SCI, RSPI, RIIC, CAN, USB, SSIE) (ETHERC, (QSPI, SDHI, PMGI) MMCIF, PDC) GLCDC Interrupt A/D D/A RMII1_TXD _EN RMII1_CR S_DV VSS 131 132 (GPTW, POEG) VCC 129 130 (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) VCC 133 P47 IRQ15-DS AN007 134 P46 IRQ14-DS AN006 135 P45 IRQ13-DS AN005 136 P44 IRQ12-DS AN004 137 P43 IRQ11-DS AN003 138 P42 IRQ10-DS AN002 139 P41 IRQ9-DS AN001 P40 IRQ8-DS AN000 P07 IRQ15 ADTRG0# 140 VREFL0 141 142 VREFH0 143 AVCC0 144 Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled. R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 75 of 179 RX72N Group 1.6.6 1. Overview 100-Pin LFQFP Table 1.10 List of Pin and Pin Functions (100-Pin LFQFP) (1/6) Pin Number Timer Power Supply Clock 100-Pin System LFQFP Control 1 AVCC1 2 EMLE 3 AVSS1 4 5 VCL 6 VBATT 7 MD/FINED 8 XCIN 9 XCOUT 10 RES# 11 XTAL 12 VSS I/O Port Bus EXDMAC (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) PJ3 EDACK1 MTIOC3C Communication (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) CTS6#/ RTS6#/ SS6#/ CTS0#/ RTS0#/ SS0#/ SSITXD0 Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF) GLCDC Interrupt A/D D/A ET0_EXOU T P37 13 EXTAL 14 VCC P36 15 UPSEL P35 16 TRST# P34 NMI EDREQ1 MTIOC0A/ TMCI3/PO12/ POE10# SCK6/SCK0 ET0_LINK STA IRQ4 MTIOC0D/ TIOCD0/ TMRI3/PO11/ POE4#/ POE11# RXD6/ SMISO6/ SSCL6/ RXD0/ SMISO0/ SSCL0/ CRX0 IRQ3-DS 17 P33 18 P32 MTIOC0C/ TIOCC0/ TMO3/PO10/ RTCIC2/ RTCOUT/ POE0#/ POE10# TXD6/ SMOSI6/ SSDA6/ TXD0/ SMOSI0/ SSDA0/ CTX0/ USB0_VBUS EN IRQ2-DS 19 TMS P31 MTIOC4D/ TMCI2/PO9/ RTCIC1 CTS1#/ RTS1#/ SS1#/ SSLB0-A IRQ1-DS 20 TDI P30 MTIOC4B/ TMRI3/PO8/ RTCIC0/ POE8# RXD1/ SMISO1/ SSCL1/ MISOB-A IRQ0-DS 21 TCK P27 CS7# MTIOC2B/ TMCI3/PO7 SCK1/ RSPCKB-A 22 TDO P26 CS6# MTIOC2A/ TMO1/PO6 TXD1/ SMOSI1/ SSDA1/ CTS3#/ RTS3#/ SS3#/ MOSIB-A R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 76 of 179 RX72N Group Table 1.10 1. Overview List of Pin and Pin Functions (100-Pin LFQFP) (2/6) Pin Number Timer Power Supply Clock 100-Pin System LFQFP Control I/O Port (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) 23 P25 CS5#/ EDACK1 MTIOC4C/ MTCLKB/ TIOCA4/PO5 RXD3/ SMISO3/ SSCL3/ SSIDATA1 24 P24 CS4#/ EDREQ1 MTIOC4A/ MTCLKA/ TIOCB4/ TMRI1/PO4 SCK3/ USB0_VBUS EN/SSIBCK1 25 P23 EDACK0 MTIOC3D/ MTCLKD/ TIOCD3/PO3 GTIOC0A TXD3/ SMOSI3/ SSDA3/ CTS0#/ RTS0#/ SS0#/CTX1/ SSIBCK0 26 P22 EDREQ0 MTIOC3B/ MTCLKC/ TIOCC3/ TMO0/PO2 GTIOC1A SCK0/ USB0_OVRC URB/ AUDIO_CLK 27 P21 MTIOC1B/ MTIOC4A/ TIOCA3/ TMCI0/PO1 GTIOC2A RXD0/ SMISO0/ SSCL0/ USB0_EXIC EN/ SSILRCK0/ SCL1 28 P20 MTIOC1A/ TIOCB3/ TMRI0/PO0 29 P17 MTIOC3A/ GTIOC0B SCK1/TXD3/ EPLSOUT0 MTIOC3B/ SMOSI3/ MTIOC4B/ SSDA3/ TIOCB0/ SDA2-DS/ TCLKD/TMO1/ SSITXD0 PO15/POE8# IRQ7 ADTRG1# 30 P16 MTIOC3C/ MTIOC3D/ TIOCB1/ TCLKC/TMO2/ PO14/ RTCOUT IRQ6 ADTRG0# 31 P15 MTIOC0B/ GTETRGA RXD1/ MTCLKB/ SMISO1/ TIOCB2/ SSCL1/ TCLKB/TMCI2/ SCK3/ PO13 CRX1-DS/ SSILRCK1 IRQ5 32 P14 MTIOC3A/ GTETRG MTCLKA/ D TIOCB5/ TCLKA/TMRI2/ PO15 IRQ4 33 P13 MTIOC0B/ TIOCA5/ TMO3/PO13 GTADSM1 TXD2/ SMOSI2/ SSDA2/ SDA0[FM+] IRQ3 34 P12 TMCI1 GTADSM0 RXD2/ SMISO2/ SSCL2/ SCL0[FM+] IRQ2 CLKOUT Bus EXDMAC R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Communication (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) (ETHERC, (QSPI, SDHI, PMGI) MMCIF) TXD0/ SMOSI0/ SSDA0/ USB0_ID/ SSIRXD0/ SDA1 TXD1/ SMOSI1/ SSDA1/ RXD3/ SMISO3/ SSCL3/ SCL2-DS/ USB0_VBUS EN/ USB0_VBUS / USB0_OVRC URB CTS1#/ RTS1#/ SS1#/CTX1/ USB0_OVRC URA Memory I/F Camera I/F GLCDC Interrupt A/D D/A ADTRG0# IRQ9 IRQ8 ADTRG1# Page 77 of 179 RX72N Group Table 1.10 1. Overview List of Pin and Pin Functions (100-Pin LFQFP) (3/6) Pin Number Timer Power Supply Clock 100-Pin System LFQFP Control (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) 35 I/O Port Bus EXDMAC Communication (GPTW, POEG) (ETHERC, (QSPI, SDHI, PMGI) MMCIF) GLCDC Interrupt USB0_DM 37 USB0_DP VSS_USB 39 P55 D0[A0/D0]/ WAIT#/ EDREQ0 MTIOC4D/ TMO3 CRX1 ET0_EXOU T 40 P54 ALE/ D1[A1/D1]/ EDACK0 MTIOC4B/ TMCI1 CTS2#/ RTS2#/ SS2#/CTX1 ET0_LINK STA 41 P53*1 BCLK 42 P52 RD# RXD2/ SMISO2/ SSCL2/ SSLB3-A 43 P51 WR1#/ BC1#/ WAIT# SCK2/ SSLB2-A 44 P50 WR0#/WR# TXD2/ SMOSI2/ SSDA2/ SSLB1-A PC7 A23/CS0# MTIOC3A/ MTCLKB/ TMO2/PO31/ TOC0/ CACREF GTIOC3A TXD8/ SMOSI8/ SSDA8/ SMOSI10/ SSDA10/ TXD10/ MISOA-A ET0_COL IRQ14 46 PC6 D2[A2/D2]/ A22/CS1# MTIOC3C/ MTCLKA/ TMCI2/PO30/ TIC0 GTIOC3B RXD8/ SMISO8/ SSCL8/ SMISO10/ SSCL10/ RXD10/ MOSIA-A ET0_ETXD 3 IRQ13 47 PC5 D3[A3/D3]/ A21/CS2#/ WAIT# MTIOC3B/ MTCLKD/ TMRI2/PO29 GTIOC1A SCK8/ RTS8#/ SCK10/ RSPCKA-A ET0_ETXD 2 48 PC4 A20/CS3# MTIOC3D/ MTCLKC/ TMCI1/PO25/ POE0# GTETRG C 49 PC3 A19 MTIOC4D/ TCLKB/PO24 GTIOC1B TXD5/ SMOSI5/ SSDA5 ET0_TX_E R 50 PC2 A18 MTIOC4B/ TCLKA/PO21 GTIOC2B RXD5/ SMISO5/ SSCL5/ SSLA3-A ET0_RX_D V 51 PC1 A17 MTIOC3A/ TCLKD/PO18 SCK5/ SSLA2-A ET0_ERXD 2 IRQ12 52 PC0 A16 MTIOC3C/ TCLKC/PO17 CTS5#/ RTS5#/ SS5#/ SSLA1-A ET0_ERXD 3 IRQ14 53 PB7 A15 MTIOC3B/ TIOCB5/PO31 TXD9/ SMOSI9/ SSDA9/ SMOSI11/ SSDA11/ TXD11 ET0_CRS/ RMII0_CR S_DV 45 A/D D/A VCC_USB 36 38 (SCI, RSPI, RIIC, CAN, USB, SSIE) Memory I/F Camera I/F UB R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 IRQ10 SCK5/ ET0_TX_C CTS8#/ LK SS8#/SS10#/ CTS10#/ RTS10#/ SSLA0-A Page 78 of 179 RX72N Group Table 1.10 1. Overview List of Pin and Pin Functions (100-Pin LFQFP) (4/6) Pin Number Timer Power Supply Clock 100-Pin System LFQFP Control I/O Port Bus EXDMAC (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) 54 PB6 A14 MTIOC3D/ TIOCA5/PO30 RXD9/ SMISO9/ SSCL9/ SMISO11/ SSCL11/ RXD11 ET0_ETXD 1/ RMII0_TXD 1 55 PB5 A13 MTIOC2A/ MTIOC1B/ TIOCB4/ TMRI1/PO29/ POE4# SCK9/ RTS9#/ SCK11 ET0_ETXD 0/ RMII0_TXD 0 LCD_CLKB 56 PB4 A12 TIOCA4/PO28 CTS9#/ SS9#/SS11#/ CTS11#/ RTS11# ET0_TX_E N/ RMII0_TXD _EN LCD_TCO N0-B 57 PB3 A11 MTIOC0A/ MTIOC4A/ TIOCD3/ TCLKD/TMO0/ PO27/POE11# SCK6 ET0_RX_E R/ RMII0_RX_ ER LCD_TCO N1-B 58 PB2 A10 TIOCC3/ TCLKC/PO26 CTS6#/ ET0_RX_C RTS6#/SS6# LK/ REF50CK0 LCD_TCO N2-B 59 PB1 A9 MTIOC0C/ MTIOC4C/ TIOCB3/ TMCI0/PO25 TXD6/ SMOSI6/ SSDA6 ET0_ERXD 0/ RMII0_RX D0 LCD_TCO IRQ4-DS N3-B PB0 A8 MTIC5W/ TIOCA3/PO24 RXD6/ SMISO6/ SSCL6 ET0_ERXD 1/ RMII0_RX D1 LCD_DAT IRQ12 A0-B 63 PA7 A7 TIOCB2/PO23 MISOA-B ET0_WOL LCD_DAT A1-B 64 PA6 A6 MTIC5V/ MTCLKB/ TIOCA2/ TMCI3/PO22/ POE10# ET0_EXOU T LCD_DAT A2-B 65 PA5 A5 MTIOC6B/ GTIOC0A RSPCKA-B TIOCB1/PO21 ET0_LINK STA LCD_DAT A3-B 66 PA4 A4 MTIC5U/ MTCLKA/ TIOCA1/ TMRI0/PO20 TXD5/ SMOSI5/ SSDA5/ SSLA0-B ET0_MDC/ PMGI0_MD C LCD_DAT IRQ5-DS A4-B 67 PA3 A3 MTIOC0D/ MTCLKD/ TIOCD0/ TCLKB/PO19 RXD5/ SMISO5/ SSCL5 ET0_MDIO / PMGI0_MD IO LCD_DAT IRQ6-DS A5-B 68 PA2 A2 MTIOC7A/ PO18 69 PA1 A1 MTIOC0B/ GTIOC2A SCK5/ MTCLKC/ SSLA2-B MTIOC7B/ TIOCB0/PO17 ET0_WOL LCD_DAT IRQ11 A7-B 70 PA0 BC0#/A0 MTIOC4A/ GTIOC0B SSLA1-B MTIOC6D/ TIOCA0/PO16/ CACREF ET0_TX_E N/ RMII0_TXD _EN LCD_DAT A8-B 71 PE7 D15[A15/ MTIOC6A/ D15]/D7[A7/ TOC1 D7] 60 (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF) GLCDC Interrupt A/D D/A VCC 61 62 Communication VSS R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 GTETRGB CTS5#/ RTS5#/ SS5#/ MOSIA-B GTIOC1A RXD5/ SMISO5/ SSCL5/ SSLA3-B GTIOC3A MISOB-B LCD_DAT A6-B SDHI_WP/ LCD_DAT IRQ7 MMC_RES#-B A9-B AN105 Page 79 of 179 RX72N Group Table 1.10 1. Overview List of Pin and Pin Functions (100-Pin LFQFP) (5/6) Pin Number Timer Power Supply Clock 100-Pin System LFQFP Control I/O Port (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) 72 PE6 D14[A14/ MTIOC6C/ D14]/D6[A6/ TIC1 D6] GTIOC3B MOSIB-B 73 PE5 D13[A13/ MTIOC4C/ D13]/D5[A5/ MTIOC2B D5] GTIOC0A RSPCKB-B 74 PE4 D12[A12/ MTIOC4D/ D12]/D4[A4/ MTIOC1A/ D4] PO28 75 PE3 76 Bus EXDMAC Communication (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF) SDHI_CD/ MMC_CD-B GLCDC Interrupt A/D D/A LCD_DAT IRQ6 A10-B AN104 ET0_RX_C LK/ REF50CK0 LCD_DAT IRQ5 A11-B AN103 GTIOC1A SSLB0-B ET0_ERXD 2 LCD_DAT A12-B AN102 D11[A11/ MTIOC4B/ D11]/D3[A3/ PO26/TOC3/ D3] POE8# GTIOC2A CTS12#/ RTS12#/ SS12# ET0_ERXD MMC_D7-B 3 LCD_DAT A13-B AN101 PE2 D10[A10/ MTIOC4A/ D10]/D2[A2/ PO23/TIC3 D2] GTIOC0B RXD12/ SMISO12/ SSCL12/ RXDX12/ SSLB3-B MMC_D6-B LCD_DAT IRQ7-DS A14-B AN100 77 PE1 D9[A9/D9]/ D1[A1/D1] MTIOC4C/ MTIOC3B/ PO18 GTIOC1B TXD12/ SMOSI12/ SSDA12/ TXDX12/ SIOX12/ SSLB2-B MMC_D5-B LCD_DAT A15-B ANEX1 78 PE0 D8[A8/D8]/ D0[A0/D0] MTIOC3D GTIOC2B SCK12/ SSLB1-B MMC_D4-B LCD_DAT A16-B ANEX0 79 PD7 D7[A7/D7] MTIC5U/ POE0# SSLC3-A QMI-B/QIO1- LCD_DAT IRQ7 B/SDHI_D1-B/ A17-B MMC_D1-B AN107 80 PD6 D6[A6/D6] MTIC5V/ MTIOC8A/ POE4# SSLC2-A QMO-B/QIO0- LCD_DAT IRQ6 B/SDHI_D0-B/ A18-B MMC_D0-B AN106 81 PD5 D5[A5/D5] MTIC5W/ MTIOC8C/ MTCLKA/ POE10# SSLC1-A QSPCLK-B/ SDHI_CLK-B/ MMC_CLK-B LCD_DAT IRQ5 A19-B AN113 82 PD4 D4[A4/D4] MTIOC8B/ POE11# SSLC0-A QSSL-B/ LCD_DAT IRQ4 SDHI_CMD-B/ A20-B MMC_CMD-B AN112 83 PD3 D3[A3/D3] MTIOC8D/ TOC2/POE8# GTIOC0A RSPCKC-A QIO3-B/ SDHI_D3-B/ MMC_D3-B LCD_DAT IRQ3 A21-B AN111 84 PD2 D2[A2/D2] MTIOC4D/ TIC2 GTIOC0B MISOC-A/ CRX0 QIO2-B/ SDHI_D2-B/ MMC_D2-B LCD_DAT IRQ2 A22-B AN110 85 PD1 D1[A1/D1] MTIOC4B/ POE0# GTIOC1A MOSIC-A/ CTX0 LCD_DAT IRQ1 A23-B AN109 86 PD0 D0[A0/D0] POE4# GTIOC1B LCD_EXT IRQ0 CLK-B AN108 87 P47 IRQ15-DS AN007 88 P46 IRQ14-DS AN006 89 P45 IRQ13-DS AN005 90 P44 IRQ12-DS AN004 91 P43 IRQ11-DS AN003 92 P42 IRQ10-DS AN002 P41 IRQ9-DS AN001 P40 IRQ8-DS AN000 P07 IRQ15 ADTRG0# 93 94 VREFL0 95 96 VREFH0 97 AVCC0 98 R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 80 of 179 RX72N Group Table 1.10 1. Overview List of Pin and Pin Functions (100-Pin LFQFP) (6/6) Pin Number Timer Power Supply Clock 100-Pin System LFQFP Control (MTU, TPU, TMR, PPG, RTC, CMTW, POE, CAC) 99 100 I/O Port Bus EXDMAC Communication (GPTW, POEG) (SCI, RSPI, RIIC, CAN, USB, SSIE) Memory I/F Camera I/F (ETHERC, (QSPI, SDHI, PMGI) MMCIF) GLCDC Interrupt A/D D/A IRQ13 DA1 AVSS0 P05 SSILRCK1 Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled. R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 81 of 179 RX72N Group 2. Electrical Characteristics 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Table 2.1 Absolute Maximum Rating Conditions: VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V Item Power supply voltage VBATT power supply voltage Input voltage (except for ports for 5 V tolerant*1) Input voltage (ports for 5 V tolerant*1) Reference power supply voltage Analog power supply voltage D version G version Storage temperature Value Unit VCC, VCC_USB –0.3 to +4.0 V VBATT –0.3 to +4.0 V Vin –0.3 to VCC + 0.3 (up to 4.0) V Vin –0.3 to VCC + 4.0 (up to 5.8) V VREFH0 –0.3 to AVCC0 + 0.3 (up to 4.0) V AVCC1*2 –0.3 to +4.0 V VAN –0.3 to AVCC + 0.3 (up to 4.0) V Tj –40 to +105 °C Tj –40 to +125 °C Tstg –55 to +125 °C AVCC0, Analog input voltage Junction temperature Symbol Caution: Permanent damage to the LSI may result if absolute maximum ratings are exceeded. Note 1. P07, P11 to P17, P20, P21, P30 to P33, P67, and PC0 to PC3 are 5 V tolerant. Note 2. Connect the AVCC0, AVCC1, and VCC_USB pins to VCC, and the AVSS0, AVSS1, and VSS_USB pins to VSS. When the A/D converter unit 0 is not to be used, connect the VREFH0 pin to VCC and the VREFL0 pin to VSS, respectively. Do not leave these pins open. Insert capacitors of high frequency characteristics between the AVCC0 and AVSS0 pins, or AVCC1 and AVSS1 pins. Place capacitors of about 0.1 µF as close as possible to every power supply pin and use the shortest and heaviest possible traces. R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 82 of 179 RX72N Group 2.2 2. Electrical Characteristics Recommended Operating Conditions Table 2.2 Recommended Operating Conditions (1) Item Symbol Min. Typ. Max. Unit VCC 2.7 — 3.6 V VSS — 0 — VBATT power supply voltage VBATT 2.0 — 3.6 V USB power supply voltage VCC_USB — VCC — V VSS_USB — 0 — AVCC0 — VCC — AVSS0 — 0 — AVCC1 — VCC — Power supply voltage*1 Analog power supply voltage*1, *2 V AVSS1 — 0 — VREFH0 2.7 — AVCC0 VREFL0 — 0 — Input voltage (except for 5 V tolerant ports, except for P03, P05 and P40 to P47)*3 Vin –0.3 — VCC + 0.3 V Input voltage (P03, P05 and P40 to P47) Vin –0.3 — AVCC0 + 0.3 V Input voltage (5V tolerant ports: P11 to P17, P20, P21, P30 to P33, P67, and PC0 to PC3)*4 Vin –0.3 — VCC + 3.6 (up to 5.5) V Input voltage (5V tolerant port: P07) Vin –0.3 — AVCC0 + 3.6 (up to 5.5) V Operating temperature (D version) Topr –40 — 85 °C Operating temperature (G version) Topr –40 — 105 °C Note 1. Note 2. Note 3. Note 4. Comply with the following potential condition: VCC = AVCC0 = AVCC1 = VCC_USB For details, refer to section 56.6.11, Voltage Range of Analog Power Supply Pins in the User’s Manual: Hardware. P07, P11 to P17, P20, P21, P30 to P33, P67, and PC0 to PC3 are 5 V tolerant. For P30 to P32, input as follows when the VBATT power supply is selected. Vin Min. = –0.3, Max. = VBATT + 0.3 (VBATT = 2.0 to 3.6 V) Table 2.3 Recommended Operating Conditions (2) Item Decoupling capacitance to stabilize the internal voltage Symbol Value CVCL 0.22 µF ± 30%*1 Note 1. Use a multilayer ceramic capacitor whose nominal capacitance is 0.22 µF and a capacitance tolerance is ±30% or better. R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 83 of 179 RX72N Group 2.3 2. Electrical Characteristics DC Characteristics Table 2.4 DC Characteristics (1) Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr Item Schmitt trigger input voltage IRQ input pin*1, MTU input pin*1, POE input pin*1, TPU input pin*1, TMR input pin*1, CMTW input pin*1, SCI input pin*1, CAN input pin*1, CAC input pin*1, ADTRG# input pin*1, QSPI input pin*1, SSIE input pin*1, GPTW input pin*1, POEG input pin*1, RES#, NMI, TCK RIIC input pin (except for SMBus) High level input voltage (except for Schmitt trigger input pin) Symbol Min. Typ. Max. Unit VIH 0.8 × VCC — — V VIL — — 0.2 × VCC ΔVT 0.06 × VCC — — VIH 0.7 × VCC — — VIL — — 0.3 × VCC ΔVT 0.05 × VCC — — Ports for 5 V tolerant*2 VIH 0.8 × VCC — — VIL — — 0.2 × VCC Other input pins excluding ports for 5 V tolerant*3 VIH 0.8 × VCC — — VIL — — 0.2 × VCC MD pin, EMLE VIH 0.9 × VCC — — 0.8 × VCC — — EXTAL, RSPI input pin, EXDMAC input pin, WAIT#, SDHI input pin, MMC input pin, PDC input pin, PMGI input pin ETHERC input pin D0 to D31 RIIC (SMBus) Low level input voltage (except for Schmitt trigger input pin) MD pin, EMLE EXTAL, RSPI input pin, ETHERC input pin, EXDMAC input pin, WAIT#, SDHI input pin, MMC input pin, PDC input pin, PMGI input pin VIL 2.3 — — 0.7 × VCC — — 2.1 — — — — 0.1 × VCC — — 0.2 × VCC D0 to D31 — — 0.3 × VCC RIIC (SMBus) — — 0.8 Test Conditions V V Note 1. This does not include the pins, which are multiplexed as ports for 5 V tolerant. Note 2. P07, P11 to P17, P20, P21, P30 to P33, P67, and PC0 to PC3 are 5 V tolerant. Note 3. For P30 to P32, input as follows when the VBATT power supply is selected. VIH Min. = VBATT × 0.8, VIL Max. = VBATT × 0.2 (VBATT = 2.0 to 3.6 V) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 84 of 179 RX72N Group Table 2.5 2. Electrical Characteristics DC Characteristics (2) Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr Item Symbol Min. Typ. Max. Unit Test Conditions Output high voltage All output pins VOH VCC – 0.5 — — V IOH = –1 mA Output low voltage All output pins (except for RIIC pins and ETHERC output pin) VOL — — 0.5 V IOL = 1.0 mA — — 0.4 IOL = 3.0 mA — — 0.6 IOL = 6.0 mA — — 0.4 — 0.4 — VOL — — 0.4 V IOL = 1.0 mA | Iin | — — 1.0 µA Vin = 0 V Vin = VCC | ITSI | — — 1.0 µA Vin = 0 V Vin = VCC — — 5.0 RIIC output pin RIIC output pin (only P12 and P13 in channel 0) ETHERC output pin EMLE*1, Input leakage current RES#, MD pin, BSCANP*1, NMI Three-state leakage current (off state) Other than ports for 5 V tolerant VOL Ports for 5 V tolerant V IOL = 15.0 mA (ICFER.FMPE = 1) IOL = 20.0 mA (ICFER.FMPE = 1) Vin = 0 V Vin = 5.5 V Input pull-up resistor current Other than P35 Ip –300 — –10 µA VCC = 2.7 to 3.6 V Vin = 0 V Input pull-down resistor current EMLE, BSCANP Ip 10 — 300 µA Vin = VCC Input capacitance All input pins (except for P03, P05, P12, P13, P16, P17, P20, P21, EMLE, BSCANP, USB0_DP, and USB0_DM) Cin — — 8 pF Vbias = 0 V Vamp = 20 mV f = 1 MHz Ta = 25°C — — 16 — 1.18 — P03, P05, P12, P13, P16, P17, P20, P21, EMLE, BSCANP, USB0_DP, and USB0_DM Output voltage of the VCL pin VCL V Note 1. The input leakage current value at the EMLE and BSCANP pins are only when Vin = 0 V. R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 85 of 179 RX72N Group Table 2.6 2. Electrical Characteristics DC Characteristics (3) Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr Item Symbol Full operation*2 High-speed operating mode Supply current *1 ICC*3 D version Typ. Max. G version Typ. Max. — 261 — 319 Normal Peripheral module clocks are supplied operation *4 61 — 61 — Peripheral module clocks are stopped *4, *5 30 — 30 — Peripheral module clocks are stopped *4, *5 37 — 37 — Sleep mode: Peripheral module clocks are supplied*4 42 144 42 196 All module clock stop mode (reference value) Core Mark Increased by BGO operation*8 14 115 14 167 Reading from the code flash memory while the data flash memory is being programmed 6 — 6 — Reading from the code flash memory while the code flash memory is being programmed 7 — 7 — Test Conditions mA ICLK = 240 MHz, PCLKA = 120 MHz, PCLKB = 60 MHz, PCLKC = 60 MHz, PCLKD = 60 MHz, FCLK = 60 MHz, BCLK = 120 MHz, BCLK pin = 60 MHz — 15 — 15 Low-speed operating mode 1: Peripheral module clocks are stopped*4 4.2 — 4.2 — All clocks 1 MHz Low-speed operating mode 2: Peripheral module clocks are stopped*4 4.2 — 4.2 — All clocks 32.768 kHz Software standby mode 3.95 107 3.95 155 Power is supplied to the standby RAM and USB resume detecting unit (USB0 only) 15.5 70 15.5 98 Power is not supplied to the standby RAM and USB resume detecting unit (USB0 only) Low power consumption function of the power-on reset circuit is disabled*6 11.5 42 11.5 58 Low power consumption function of the power-on reset circuit is enabled*7 4.9 32 4.9 47 Increase current by operating RTC When a low CL crystal is in use 1 — 1 — When a standard CL crystal is in use 2 — 2 — 0.9 — 0.9 — VBATT = 2.0 V, VCC = 0 V 1.6 — 1.6 — VBATT = 3.3 V, VCC = 0 V 1.7 — 1.7 — VBATT = 2.0 V, VCC = 0 V 3.3 — 3.3 — VBATT = 3.3 V, VCC = 0 V — 211 — 211 Deep software standby mode Increased by Trusted Secure IP operation Unit When the RTC is operating while VCC is not supplied (Only the RTC and sub-clock oscillator operate with the battery backup function) Inrush current on returning from deep software standby mode When a low CL crystal is in use When a standard CL crystal is in use Inrush current*9 IRUSH µA mA Note 1. Supply current values are measured when all output pins are unloaded and all input pull-up resistors are disabled. Note 2. Peripheral module clocks are supplied. Note 3. ICC depends on the f (ICLK) as follows. (when ICLK : PCLKA : PCLKB/PCLKC/PCLKD : BCLK : BCLK pin = 4 : 2 : 1 : 2 : 1 and EXTAL = 12 MHz)  D version ICC max. = 0.62 × f + 113 (full operation in high-speed operating mode) ICC typ. = 0.22 × f + 7 (normal operation in high-speed operating mode) ICC typ. = 0.50 × f + 3.7 (ICLK 1 MHz max) (low-speed operating mode 1) ICC max. = 0.13 × f + 113 (sleep mode) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 86 of 179 RX72N Group Note 4. Note 5. Note 6. Note 7. Note 8. Note 9. 2. Electrical Characteristics  G version ICC max. = 0.65 × f + 164 (full operation in high-speed operating mode) ICC typ. = 0.22 × f + 7 (normal operation in high-speed operating mode) ICC typ. = 0.50 × f + 3.7 (ICLK 1 MHz max) (low-speed operating mode 1) ICC max. = 0.13 × f + 164 (sleep mode) Whether the peripheral module clocks are supplied or stopped is controlled only by the bit settings in the module stop control registers A to D. When the peripheral module clock is stopped, the settings of the clock frequency are as follows: ICLK = 240 MHz and PCLKA = PCLKB = PCLKC = PCLKD = FCLK = BCLK = BCLK pin = 3.75 MHz (divided by 64). When the low power consumption function is disabled, the DEEPCUT[1:0] bits are set to 01b. When the low power consumption function is enabled, the DEEPCUT[1:0] bits are set to 11b. These are the increases during programming of the code flash memory after the code flash memory (limitations apply to the combinations of address ranges of the program area and the readable area) or the data flash memory has been programmed or erased. Reference value Table 2.7 DC Characteristics (4) Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr Item Symbol Analog During 12-bit A/D conversion (unit 0) power During 12-bit A/D conversion (unit 0) supply with channel-dedicated sample-andcurrent*1, *3 hold circuits (3 channels) AICC Reference power supply current USB operating current D version Min. Typ. — — During 12-bit A/D conversion (unit 1) G version Test Conditions Min. Typ. 0.8 1 — 0.8 1 1.7 2.5 — 1.7 2.5 — 0.6 1 — 0.6 1 During 12-bit A/D conversion (unit 1) + temperature sensor — 0.7 1.1 — 0.7 1.1 IAVCC1_AD + TEMP During D/A conversion (2 channels) Unbuffered output — 0.25 0.4 — 0.25 0.4 IAVCC1_DA Buffered output — 0.75 1.1 — 0.75 1.1 Waiting for A/D, D/A, and temperature sensor conversion (all units) — 0.9 1.4 — 0.9 1.4 A/D, D/A, and temperature sensor are in standby mode (all units) — 1.4 6.7 — 1.4 9.0 µA IAVCC0 + IAVCC1 — 38 60 — 38 60 µA IVREFH0 Waiting for 12-bit A/D conversion (unit 0) — 0.07 0.5 — 0.07 0.6 IVREFH0 12-bit A/D converter in module stop mode (unit 0) — 0.07 0.4 — 0.07 0.5 IVREFH0 During 12-bit A/D conversion (unit 0) AIREFH Max. Unit Max. mA IAVCC0_AD IAVCC0_AD + SH IAVCC1_AD IAVCC0 + IAVCC1 Low speed USB0 ICCUSBLS — 3.7 6.5 — 3.7 6.5 mA VCC_USB Full speed USB0 ICCUSBFS — 4.2 10 — 4.2 10 mA VCC_USB — V VRAM 2.7 — — 2.7 — VCC rising gradient RAM retension voltage SrVCC 8.4 — 20000 8.4 — VCC falling gradient*2 SfVCC 8.4 — — 8.4 — 20000 µs/V — µs/V Note 1. The reference power supply current is included in the power supply current value for 12-bit A/D converter (unit 1) and D/A converter. Note 2. This applies when VBATT is used. Note 3. Supply current values are measured when all output pins are unloaded. R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 87 of 179 RX72N Group Table 2.8 2. Electrical Characteristics Permissible Output Currents Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr Item Permissible output low current (average value per pin) Permissible output low current (max. value per pin) All output pins*1 Normal drive All output pins*2 Permissible output high current (average value per pin) Permissible output high current (max. value per pin) Typ. Max. Unit IOL — — 2.0 mA High drive — — 3.8 High-speed interface high-drive — — 7.5 All output pins*1 Normal drive — — 4.0 All output pins*2 High drive — — 7.6 High-speed interface high-drive — — 15 ΣIOL — — 80 mA IOH mA pins*3 IOL Total of all output pins All output pins*1 — — –2.0 All output pins*2 High drive — — –3.8 All output pins*3 High-speed interface high-drive — — –7.5 All output pins*1 Normal drive — — –4.0 All output pins*2 All output pins*3 Permissible output high current (total) Min. All output pins*3 All output Permissible output low current (total) Symbol Normal drive IOH High drive — — –7.6 High-speed interface high-drive — — –15 — — –80 ΣIOH Total of all output pins mA mA mA Caution: To protect the MCU’s reliability, the output current values should not exceed the values in Table 2.8. Note 1. This is the value when normal driving ability is set with a pin for which normal driving ability is selectable. Note 2. This is the value when high driving ability is set with a pin for which normal driving ability is selectable or the value of the pin to which high driving ability is fixed. Note 3. This is the value when high-speed interface high-driving ability is set with a pin for which high-speed interface high-driving ability is selectable. Table 2.9 Thermal Resistance Value (Reference) Item Thermal resistance Package 176-pin LFQFP (PLQP0176KB-C) Symbol ja Unit 31.5 °C/W 144-pin LFQFP (PLQP0144KA-B) 32.6 100-pin LFQFP (PLQP0100KB-B) 34.0 224-pin LFBGA (PLBG0224GA-A) 23.1 176-pin LFBGA (PLBG0176GA-A) 30.5 145-pin TFLGA (PTLG0145KA-A) 176-pin LFQFP (PLQP0176KB-C) Note: Max. Test Conditions JESD51-2 and JESD51-7 compliant JESD51-2 and JESD51-9 compliant 22.9 jt 0.4 144-pin LFQFP (PLQP0144KA-B) 0.5 100-pin LFQFP (PLQP0100KB-B) 0.6 224-pin LFBGA (PLBG0224GA-A) 0.2 176-pin LFBGA (PLBG0176GA-A) 0.3 145-pin TFLGA (PTLG0145KA-A) 0.2 °C/W JESD51-2 and JESD51-7 compliant JESD51-2 and JESD51-9 compliant The values are reference values when the 4-layer board is used. Thermal resistance depends on the number of layers or size of the board. For details, refer to the JEDEC standards. R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 88 of 179 RX72N Group 2.4 2. Electrical Characteristics AC Characteristics Table 2.10 Operating Frequency (High-Speed Operating Mode) Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr Item Operating frequency Symbol Min. Typ. Max. Unit f — — 240 MHz Peripheral module clock (PCLKA) — — 120 Peripheral module clock (PCLKB) — — 60 Peripheral module clock (PCLKC) — — 60 System clock (ICLK) Peripheral module clock (PCLKD) Flash-IF clock (FCLK) — — 60 —*1 — 60 — — 120 External bus clock (BCLK) Package of 144 pins or more 100-pin package — — 60 BCLK pin output Package of 144 pins or more — — 80 100-pin package — — 30 SDRAM clock (SDCLK) Package of 144 pins or more — — 80 SDCLK pin output Package of 144 pins or more — — 80 Note 1. The FCLK must run at a frequency of at least 4 MHz when changing the flash memory contents. Table 2.11 Operating Frequency (Low-Speed Operating Mode 1) Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr Item Operating frequency Symbol Min. Typ. Max. Unit f — — 1 MHz Peripheral module clock (PCLKA) — — 1 Peripheral module clock (PCLKB) — — 1 Peripheral module clock (PCLKC)*1 — — 1 Peripheral module clock (PCLKD)*1 System clock (ICLK) — — 1 Flash-IF clock (FCLK) — — 1 External bus clock (BCLK) — — 1 BCLK pin output — — 1 SDRAM clock (SDCLK) Package of 144 pins or more — — 1 SDCLK pin output Package of 144 pins or more — — 1 Note 1. When the 12-bit A/D converter is used, the frequency must be set to at least 1 MHz. R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 89 of 179 RX72N Group Table 2.12 2. Electrical Characteristics Operating Frequency (Low-Speed Operating Mode 2) Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr Item Operating frequency Symbol Min. Typ. Max. Unit f 32 — 264 kHz Peripheral module clock (PCLKA) — — 264 Peripheral module clock (PCLKB) — — 264 — — 264 System clock (ICLK) Peripheral module clock (PCLKC)*1 Peripheral module clock (PCLKD)*1 — — 264 Flash-IF clock (FCLK) 32 — 264 External bus clock (BCLK) — — 264 BCLK pin output — — 264 SDRAM clock (SDCLK) Package of 144 pins or more — — 264 SDCLK pin output Package of 144 pins or more — — 264 Note 1. The 12-bit A/D converter cannot be used. R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 90 of 179 RX72N Group 2.4.1 Table 2.13 2. Electrical Characteristics Reset Timing Reset Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr Item RES# pulse width Test Conditions Symbol Min. Typ. Max. Unit Power-on tRESWP 1 — — ms Figure 2.1 Deep software standby mode tRESWD 0.6 — — ms Figure 2.2 Software standby mode, low-speed operating mode 2 tRESWS 0.3 — — ms Programming or erasure of the code flash memory, or programming, erasure or blank checking of the data flash memory tRESWF 200 — — µs Other than above tRESW 200 — — µs Waiting time after release from the RES# pin reset tRESWT 54 — 55 tLcyc Internal reset time (independent watchdog timer reset, watchdog timer reset, software reset) tRESW2 100 — 108 tLcyc Figure 2.1 VCC RES# tRESWP Internal reset signal (Low is valid) tRESWT Figure 2.1 Reset Input Timing at Power-On tRESWD, tRESWS, tRESWF, tRESW RES# Internal reset signal (Low is valid) tRESWT Figure 2.2 Reset Input Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 91 of 179 RX72N Group 2.4.2 Table 2.14 2. Electrical Characteristics Clock Timing BCLK Pin Output, SDCLK Pin Output Clock Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr Item BCLK pin output cycle time Symbol Min. Typ. Max. Unit tBcyc 12.5 — — ns Package of 144 pins or more 33.2 — — BCLK pin output high pulse width 100-pin package tCH 3.25 — — ns BCLK pin output low pulse width tCL 3.25 — — ns BCLK pin output rising time tCr — — 3 ns BCLK pin output falling time tCf — — 3 ns tBcyc 12.5 — — ns SDCLK pin output cycle time SDCLK pin output high pulse width Package of 144 pins or more tCH 3.25 — — ns SDCLK pin output low pulse width tCL 3.25 — — ns SDCLK pin output rising time tCr — — 3 ns SDCLK pin output falling time tCf — — 3 ns Test Conditions Figure 2.3 tBcyc, tSDcyc tCH tCf BCLK pin output, SDCLK pin output tCL tCr Test conditions: VOH = 0.7 × VCC, VOL = 0.3 × VCC, C = 30 pF Figure 2.3 BCLK Pin and SDCLK Pin Output Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 92 of 179 RX72N Group Table 2.15 2. Electrical Characteristics EXTAL Clock Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr Item Symbol fEXMAIN ≤ 24 MHz Min. Typ. fEXMAIN > 24 MHz Max. Min. Typ. Max. Unit EXTAL external clock input cycle time tEXcyc 41.66 — — 33.33 — — ns EXTAL external clock input frequency fEXMAIN — — 24 — — 30 MHz EXTAL external clock input high pulse width tEXH 15.83 — — 13.33 — — ns EXTAL external clock input low pulse width tEXL 15.83 — — 13.33 — — ns EXTAL external clock rising time tEXr — — 5 — — 5 ns EXTAL external clock falling time tEXf — — 5 — — 5 ns Test Conditions Figure 2.4 tEXcyc tEXH tEXL EXTAL external clock input 0.5 × VCC tEXr Figure 2.4 Table 2.16 tEXf EXTAL External Clock Input Timing Main Clock Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr Item Symbol Main clock oscillation frequency Main clock oscillator stabilization time (crystal) Main clock oscillation stabilization wait time (crystal) Min. Typ. fMAIN 8 tMAINOSC — tMAINOSCWT — Max. Unit — 24 MHz — —*1 ms — —*2 ms Test Conditions Figure 2.5 Note 1. When using a main clock, ask the manufacturer of the oscillator to evaluate its oscillation. Refer to the results of evaluation provided by the manufacturer for the oscillation stabilization time. Note 2. The number of cycles selected by the value of the MOSCWTCR.MSTS[7:0] bits determines the main clock oscillation stabilization wait time in accord with the formula below. tMAINOSCWT = [(MSTS[7:0] bits × 32) + 10] / fLOCO MOSCCR.MOSTP tMAINOSC Main clock oscillator output tMAINOSCWT OSCOVFSR.MOOVF Main clock Figure 2.5 Main Clock Oscillation Start Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 93 of 179 RX72N Group Table 2.17 2. Electrical Characteristics LOCO and IWDT-Dedicated Low-Speed Clock Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr Item LOCO clock cycle time LOCO clock oscillation frequency Symbol Min. Typ. Max. Unit tLcyc 4.63 4.16 3.78 µs fLOCO 216 240 264 kHz LOCO clock oscillation stabilization wait time tLOCOWT — — 44 µs IWDT-dedicated low-speed clock cycle time tILcyc 9.26 8.33 7.57 µs fILOCO 108 120 132 kHz tILOCOWT — 142 190 µs IWDT-dedicated low-speed clock oscillation frequency IWDT-dedicated low-speed clock oscillation stabilization wait time Test Conditions Figure 2.6 Figure 2.7 LOCOCR.LCSTP On-chip oscillator output tLOCOWT LOCO clock Figure 2.6 LOCO Clock Oscillation Start Timing ILOCOCR.ILCSTP IWDT-dedicated on-chip oscillator output tILOCOWT OSCOVFSR.ILCOVF IWDT-dedicated low-speed clock Figure 2.7 IWDT-dedicated Low-Speed Clock Oscillation Start Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 94 of 179 RX72N Group Table 2.18 2. Electrical Characteristics HOCO Clock Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr Item HOCO clock oscillation frequency Symbol Min. Typ. Max. Unit fHOCO 15.61 16 16.39 MHz 17.56 18 18.44 19.52 20 20.48 15.52 16 16.48 17.46 18 18.54 19.4 20 20.6 Test Conditions Ta ≥ –20°C –40°C ≤ Ta < –20°C HOCO clock oscillation stabilization wait time tHOCOWT — 105 149 µs Figure 2.8 HOCO clock power supply stabilization time tHOCOP — — 150 µs Figure 2.9 HOCOCR.HCSTP High-speed on-chip oscillator output tHOCOWT OSCOVFSR.HCOVF HOCO clock Figure 2.8 HOCO Clock Oscillation Start Timing (Oscillation is Started by Setting the HOCOCR.HCSTP Bit) HOCOPCR.HOCOPCNT HOCOCR.HCSTP tHOCOP Internal power supply for high-speed on-chip oscillator Figure 2.9 High-Speed On-Chip Oscillator Power Supply Control Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 95 of 179 RX72N Group Table 2.19 2. Electrical Characteristics PLL/PPLL Clock Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr Item PLL/PPLL clock oscillation frequency PLL/PPLL clock oscillation stabilization wait time Test Conditions Symbol Min. Typ. Max. Unit fPLL 120 — 240 MHz tPLLWT — 259 320 µs Figure 2.10 Test Conditions PLLCR2.PLLEN PPLLCR2.PPLLEN PLL/PPLL circuit output tPLLWT OSCOVFSR.PLOVF OSCOVFSR.PPLOVF PLL/PPLL clock Figure 2.10 Table 2.20 PLL/PPLL Clock Oscillation Start Timing Sub-Clock Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, VBATT = 2.0 to 3.6 V, Ta = Topr Item Sub-clock oscillation frequency Sub-clock oscillation stabilization time Sub-clock oscillation stabilization wait time Symbol Min. Typ. Max. Unit fSUB — 32.768 — kHz tSUBOSC — — *1 s — *2 s tSUBOSCWT — Figure 2.11 Note 1. When using a sub-clock, ask the manufacturer of the oscillator to evaluate its oscillation. Refer to the results of evaluation provided by the manufacturer for the oscillation stabilization time. Note 2. The number of cycles selected by the value of the SOSCWTCR.SSTS[7:0] bits determines the sub-clock oscillation stabilization wait time in accord with the formula below. tSUBOSCWT = [(SSTS[7:0] bits × 16384) + 10] / fLOCO SOSCCR.SOSTP tSUBOSC Sub-clock oscillator output tSUBOSCWT OSCOVFSR.SOOVF Sub-clock Figure 2.11 Sub-Clock Oscillation Start Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 96 of 179 RX72N Group Table 2.21 2. Electrical Characteristics CLKOUT Pin Output Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, VBATT = 2.0 to 3.6 V, Ta = Topr, High-drive output is selected by the driving ability control register Item CLKOUT pin output cycle time CLKOUT pin output high pulse width*1 Symbol Min. Typ. Max. Unit tCcyc 25 — — ns tCH 5 — — ns CLKOUT pin output low pulse width*1 tCL 5 — — ns CLKOUT pin output rising time tCr — — 5 ns CLKOUT pin output falling time tCf — — 5 ns Test Conditions Figure 2.12 tCcyc = 25 ns Note 1. If the main clock oscillator is selected by the CLKOUT output source select bit (CKOCR.CKOSEL[2:0]) and the external clock input is selected by the main clock oscillator switching bit (MOFCR.MOSEL), the pulse width depends on the input clock wave form. tCcyc tCH tCf CLKOUT pin output tCr tCL Test Conditions VOH = 0.7 × VCC, VOL = 0.3 × VCC, C = 30pF Figure 2.12 Table 2.22 CLKOUT Pin Output Timing CLKOUT25M Pin Output Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, VBATT = 2.0 to 3.6 V, Ta = Topr, High-speed interface high-drive is selected by the driving ability control register Item Symbol CLKOUT25M pin output cycle time Min. Typ. Max. Unit Test Conditions Figure 2.13 tCcyc — 40 — ns CLKOUT25M pin output high pulse width tCH 13 — — ns CLKOUT25M pin output low pulse width tCL 13 — — ns CLKOUT25M pin output rising time tCr — — 3 ns CLKOUT25M pin output falling time tCf — — 3 ns tCcyc tCH tCf CLKOUT25M pin output tCL tCr Test Conditions VOH = 0.7 × VCC, VOL = 0.3 × VCC, C = 30pF Figure 2.13 CLKOUT25M Pin Output Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 97 of 179 RX72N Group 2.4.3 Table 2.23 2. Electrical Characteristics Timing of Recovery from Low Power Consumption Modes Timing of Recovery from Low Power Consumption Modes (1) Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr Item Recovery time from software standby mode *1 Crystal resonator connected to main clock oscillator Symbol Min. Typ. tSBYSEQ*3 100 + 7 / fICLK + 2n / fMAIN tSBYPC {(MSTS[7:0] bit × 32) + 138} / 0.216 100 + 7 / fICLK + 2n / fPLL tSBYEX 352 100 + 7 / fICLK + 2n / fEXMAIN Main clock oscillator and PLL circuit operating tSBYPE 639 100 + 7 / fICLK + 2n / fPLL Sub-clock oscillator operating tSBYSC {(SSTS[7:0] bit × 16384) + 13} / 0.216 + 10 / fFCLK 100 + 4 / fICLK + 2n / fSUE High-speed on-chip oscillator operating High-speed on-chip oscillator operating tSBYHO 454 100 + 7 / fICLK + 2n / fHOCO High-speed on-chip oscillator operating and PLL circuit operating tSBYPH 741 100 + 7 / fICLK + 2n / fPLL tSBYLO 338 100 + 7 / fICLK + 2n / fLOCO tSBYMC Main clock oscillator and PLL circuit operating External clock Main clock input to main oscillator clock oscillator operating Low-speed on-chip oscillator operating*4 — tSBYOSCWT {(MSTS[7:0] bit × 32) + 76} / 0.216 Main clock oscillator operating — Max. *2 Unit Test Conditions µs Figure 2.14 Note 1. The time for recovery from software standby mode is determined by the value obtained by adding the oscillation stabilization waiting time (tSBYOSCWT) and the time required for operations by the software standby release sequencer (tSBYSEQ). Note 2. When several oscillators were running before the transition to software standby, the greatest value of the oscillation stabilization waiting time tSBYOSCWT is selected. Note 3. For n, the greatest value is selected from among the internal clock division settings. Note 4. This condition applies when fICLK:fFCLK = 1:1, 2:1, or 4:1. R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 98 of 179 RX72N Group 2. Electrical Characteristics Oscillator (System clock) tSBYOSCWT tSBYSEQ Oscillator (Other than the system clock) ICLK IRQ Software standby mode tSBYMC, tSBYEX, tSBYPC, tSBYPE, tSBYPH, tSBYSC, tSBYHO, tSBYLO When stabilization of the system clock oscillator is slower Oscillator (System clock) tSBYOSCWT tSBYSEQ Oscillator (Other than the system clock) tSBYOSCWT ICLK IRQ Software standby mode tSBYMC, tSBYEX, tSBYPC, tSBYPE, tSBYPH, tSBYSC, tSBYHO, tSBYLO When stabilization of an oscillator other than the system clock is slower Figure 2.14 Software Standby Mode Recovery Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 99 of 179 RX72N Group Table 2.24 2. Electrical Characteristics Timing of Recovery from Low Power Consumption Modes (2) Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr Item Recovery time from deep software standby mode Wait time after recovery from deep software standby mode Symbol Min. Typ. Max. Unit Test Conditions tDSBY — — 0.9 ms Figure 2.15 tDSBYWT 23 — 24 tLcyc Oscillator IRQ Deep software standby reset (Low is valid) Internal reset (Low is valid) Deep software standby mode tDSBY tDSBYWT Reset exception handling start Figure 2.15 Deep Software Standby Mode Recovery Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 100 of 179 RX72N Group 2.4.4 2. Electrical Characteristics Control Signal Timing Table 2.25 Control Signal Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKB = 8 to 60 MHz, Ta = Topr Symbol Min.*1 Typ. Max. Unit NMI pulse width tNMIW 200 — — ns tPBcyc × 2 ≤ 200 ns, Figure 2.16 IRQ pulse width tIRQW ns tPBcyc × 2 ≤ 200 ns, Figure 2.17 Item tPBcyc × 2 — — 200 — — tPBcyc × 2 — — Test Conditions*1 tPBcyc × 2 > 200 ns, Figure 2.16 tPBcyc × 2 > 200 ns, Figure 2.17 Note 1. tPBcyc: PCLKB cycle NMI Figure 2.16 tNMIW tNMIW tIRQW tIRQW NMI Interrupt Input Timing IRQn Figure 2.17 IRQ Interrupt Input Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 101 of 179 RX72N Group 2.4.5 2. Electrical Characteristics Bus Timing Table 2.26 Bus Timing Conditions 1: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, ICLK = 8 to 240 MHz, PCLKA = 8 to 120 MHz, PCLKB = BCLK = SDCLK = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Conditions 2: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 3.0 to 3.6 V, 3.0 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, ICLK = 60 to 240 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, 60 MHz < BCLK = SDCLK ≤ 80 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 15 pF for the SDCLK pin, C = 30 pF for other pins. To control the drive capacity when using the SDRAM: set the PFBCR3.SDCLKDRV bit in external bus control register 1 to 1 to select the drive capacity of the SDCLK pin, and set the SDRAM pins other than the SDCLK pin as highspeed-interface driving outputs. Item Symbol Conditions 1 Conditions 2 Min. Max. Min. Max. Unit Address delay time tAD — 12.5 — 12.5 ns Byte control delay time tBCD — 12.5 — 12.5 ns CS# delay time tCSD — 12.5 — 12.5 ns ALE delay time tALED — 12.5 — 12.5 ns RD# delay time tRSD — 12.5 — 12.5 ns Read data setup time tRDS 12.5 — 12.5 — ns Read data hold time tRDH 0 — 0 — ns WR# delay time tWRD — 12.5 — 12.5 ns Write data delay time tWDD — 12.5 — 12.5 ns Write data hold time tWDH 0 — 0 — ns WAIT# setup time tWTS 12.5 — 12.5 — ns WAIT# hold time tWTH 0 — 0 — ns Address delay time 2 (SDRAM) tAD2 1 12.5 1 10.0 ns CS# delay time 2 (SDRAM) tCSD2 1 12.5 1 10.0 ns DQM delay time (SDRAM) tDQMD 1 12.5 1 10.0 ns CKE delay time (SDRAM) tCKED 1 12.5 1 10.0 ns Read data setup time 2 (SDRAM) tRDS2 10 — 6.0 — ns Read data hold time 2 (SDRAM) tRDH2 0 — 0 — ns Write data delay time 2 (SDRAM) tWDD2 — 12.5 — 10.0 ns Write data hold time 2 (SDRAM) tWDH2 1 — 1 — ns WE# delay time (SDRAM) tWED 1 12.5 1 10.0 ns RAS# delay time (SDRAM) tRASD 1 12.5 1 10.0 ns CAS# delay time (SDRAM) tCASD 1 12.5 1 10.0 ns R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Test Conditions Figure 2.18 to Figure 2.23 Figure 2.24 Figure 2.25 to Figure 2.31 Page 102 of 179 RX72N Group 2. Electrical Characteristics Data cycle Address cycle Ta1 Ta1 Tan TW1 TW2 TW3 TW4 Tend TW5 Tn1 Tn2 BCLK tAD Address bus tAD tRDS tAD tRDH Address bus/ data bus tALED tALED Address latch (ALE) tRSD tRSD Data read (RD#) Figure 2.18 tCSD tCSD Chip select (CS1#) Address/Data Multiplexed Bus Read Access Timing Data cycle Address cycle Ta1 Ta1 Tan TW1 TW2 TW3 TW4 TW5 Tend Tn1 Tn2 Tn3 BCLK tAD Address bus tAD tAD tWDD tWDH Address bus/ data bus tALED tALED Address latch (ALE) tWRD tWRD Data write (WRm#) tCSD Chip select (CS1#) Figure 2.19 tCSD Address/Data Multiplexed Bus Write Access Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 103 of 179 RX72N Group 2. Electrical Characteristics CSRWAIT:2 RDON:1 CSROFF:2 CSON:0 TW1 TW2 Tend Tn1 Tn2 BCLK Byte strobe mode tAD tAD tAD tAD tBCD tBCD tCSD tCSD A23 to A0 1-write strobe mode A23 to A1 BC3# to BC0# Common to both byte strobe mode and 1-write strobe mode CS7# to CS0# tRSD tRSD RD# (Read) tRDS tRDH D31 to D0 (Read) Figure 2.20 External Bus Timing/Normal Read Cycle (Bus Clock Synchronized) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 104 of 179 RX72N Group 2. Electrical Characteristics CSWWAIT:2 WRON:1 WDON:1 *1 CSWOFF:2 WDOFF:1 *1 CSON:0 TW1 TW2 Tend Tn1 Tn2 BCLK Byte strobe mode tAD tAD tAD tAD tBCD tBCD tCSD tCSD A23 to A0 1-write strobe mode A23 to A1 BC3# to BC0# Common to both byte strobe mode and 1-write strobe mode CS7# to CS0# tWRD tWRD WR3# to WR0#, WR# (Write) tWDD tWDH D31 to D0 (Write) Note 1. Be sure to specify WDON and WDOFF as at least one cycle of BCLK. Figure 2.21 External Bus Timing/Normal Write Cycle (Bus Clock Synchronized) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 105 of 179 RX72N Group 2. Electrical Characteristics CSRWAIT:2 CSON:0 CSPRWAIT:2 CSPRWAIT:2 RDON:1 RDON:1 TW1 TW2 Tend CSPRWAIT:2 RDON:1 Tpw1 Tpw2 Tend CSROFF:2 RDON:1 Tpw1 Tpw2 Tend Tpw1 Tpw2 Tend Tn1 Tn2 BCLK Byte strobe mode tAD tAD tAD tAD tAD tAD tAD tAD tAD tAD A23 to A0 1-write strobe mode A23 to A1 tBCD tBCD tCSD tCSD BC3# to BC0# Common to both byte strobe mode and 1-write strobe mode CS7# to CS0# tRSD tRSD tRSD tRSD tRSD tRSD tRSD tRSD RD# (Read) tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH D31 to D0 (Read) Figure 2.22 External Bus Timing/Page Read Cycle (Bus Clock Synchronized) CSPWWAIT:2 CSWWAIT:2 WRON:1 WDON:1 *1 WDOFF:1 CSON:0 TW1 TW2 Tend Tdw1 *1 WRON:1 WDON:1 *1 Tpw1 CSPWWAIT:2 WDOFF:1 Tpw2 Tend *1 Tdw1 WRON:1 WDON:1 *1 Tpw1 CSWOFF:2 WDOFF:1 *1 Tpw2 Tend Tn1 Tn2 BCLK Byte strobe mode tAD tAD tAD tAD tAD tAD tAD tAD A23 to A0 1-write strobe mode A23 to A1 tBCD tBCD tCSD tCSD BC3# to BC0# Common to both byte strobe mode and 1-write strobe mode CS7# to CS0# tWRD tWRD tWRD tWRD tWRD tWRD WR3# to WR0#, WR# (Write) tWDD tWDH tWDD tWDH tWDD tWDH D31 to D0 (Write) Note 1. Be sure to specify WDON and WDOFF as at least one cycle of BCLK. Figure 2.23 External Bus Timing/Page Write Cycle (Bus Clock Synchronized) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 106 of 179 RX72N Group 2. Electrical Characteristics CSRWAIT:3 CSWWAIT:3 TW1 TW2 TW3 (Tend) Tend Tn1 Tn2 BCLK A23 to A0 CS7# to CS0# RD# (Read) WR# (Write) External wait tWTS tWTH tWTS tWTH WAIT# Figure 2.24 External Bus Timing/External Wait Control R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 107 of 179 RX72N Group 2. Electrical Characteristics SDRAM command ACT RD PRA SDCLK pin tAD2 tAD2 Row address A18 to A0 tAD2 tAD2 tAD2 tAD2 tAD2 Column address tAD2 AP*1 PRA command tCSD2 tCSD2 tRASD tRASD tCSD2 tCSD2 tCSD2 tCSD2 tRASD tRASD tWED tWED SDCS# RAS# tCASD tCASD CAS# WE# (High) CKE tDQMD DQMn tRDS2 tRDH2 D31 to D0 Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM. Figure 2.25 SDRAM Space Single Read Bus Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 108 of 179 RX72N Group 2. Electrical Characteristics SDRAM command ACT WR PRA SDCLK pin tAD2 tAD2 Row address A18 to A0 tAD2 tAD2 tAD2 tAD2 tAD2 Column address tAD2 AP*1 PRA command tCSD2 tCSD2 tRASD tRASD tCSD2 tCSD2 tCSD2 tCSD2 tRASD tRASD tWED tWED SDCS# RAS# tCASD tCASD tWED tWED CAS# WE# (High) CKE tDQMD DQMn tWDD2 tWDH2 D31 to D0 Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM. Figure 2.26 SDRAM Space Single Write Bus Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 109 of 179 RX72N Group 2. Electrical Characteristics ACT RD RD RD RD PRA SDCLK pin tAD2 tAD2 tAD2 tAD2 A18 to A0 Row address C0 (column address) C1 C2 tAD2 tAD2 tAD2 tAD2 C3 tAD2 tAD2 tAD2 tAD2 AP*1 tAD2 PRA command tCSD2 tCSD2 tCSD2 tCSD2 tCSD2 tRASD tRASD tRASD tCASD tCASD SDCS# tRASD tRASD RAS# tCASD CAS# tWED tWED WE# (High) CKE tDQMD tDQMD DQMn tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM. Figure 2.27 SDRAM Space Multiple Read Bus Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 110 of 179 RX72N Group 2. Electrical Characteristics WR WR WR WR PRA ACT SDCLK pin tAD2 A18 to A0 Row address tAD2 tAD2 tAD2 tAD2 C0 (column address) C1 C2 tAD2 tAD2 tAD2 tAD2 C3 tAD2 AP*1 tAD2 tAD2 tAD2 PRA command tCSD2 tCSD2 tCSD2 tCSD2 tCSD2 SDCS# tRASD tRASD tRASD tRASD tRASD RAS# tCASD tCASD tCASD CAS# tWED tWED WE# (High) CKE tDQMD tDQMD DQMn tWDD2 tWDH2 tWDD2 tWDH2 D31 to D0 Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM. Figure 2.28 SDRAM Space Multiple Write Bus Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 111 of 179 RX72N Group 2. Electrical Characteristics SDRAM command ACT RD RD RD RD t AD2 t AD2 t AD2 PRA ACT RD RD RD RD PRA SDCLK pin t AD2 t AD2 Row address A18 to A0 t AD2 C0 (column address 0) C1 C2 t AD2 t AD2 C3 t AD2 t AD2 t AD2 t AD2 t AD2 C4 R1 t AD2 AP*1 t AD2 t AD2 C5 t AD2 C6 t AD2 C7 t AD2 t AD2 PRA command t CSD2 t CSD2 t CSD2 t CSD2 t CSD2 t CSD2 t AD2 t AD2 PRA command t CSD2 t CSD2 SDCS# t RASD t RASD t RASD t RASD t RASD t RASD t RASD t RASD RAS# t CASD t CASD t CASD t CASD CAS# t WED t WED t WED t WED WE# (High) CKE tDQMD DQMn t RDS2 t RDH2 t RDS2 t RDH2 t RDS2 t RDH2 t RDS2 t RDH2 D31 to D0 Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM. Figure 2.29 SDRAM Space Multiple Read Line Stride Bus Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 112 of 179 RX72N Group 2. Electrical Characteristics MRS SDRAM command SDCLK pin t AD2 t AD2 t AD2 t AD2 t CSD2 t CSD2 t RASD t RASD t CASD t CASD t WED t WED A18 to A0 AP*1 SDCS# RAS# CAS# WE# (High) CKE DQMn (Hi-Z) D31 to D0 Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM. Figure 2.30 SDRAM Space Mode Register Set Bus Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 113 of 179 RX72N Group 2. Electrical Characteristics SDRAM command Ts (RFA) (RFS) (RFX) (RFA) SDCLK pin t AD2 t AD2 t AD2 t AD2 A18 to A0 AP*1 t CSD2 t CSD2 t CSD2 t CSD2 t CSD2 t CSD2 t CSD2 t RASD t RASD t RASD t RASD t RASD t RASD t RASD t CASD t CASD t CASD t CASD t CASD t CASD t CASD SDCS# RAS# CAS# (High) WE# t CKED t CKED CKE t DQMD t DQMD DQMn (Hi-Z) D31 to D0 Note 1. Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM. Figure 2.31 SDRAM Space Self-Refresh Bus Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 114 of 179 RX72N Group 2.4.6 Table 2.27 2. Electrical Characteristics EXDMAC Timing EXDMAC Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, ICLK = 8 to 240 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, BCLK = SDCLK = 8 to 80 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Item EXDMAC Symbol Min. Max. Unit EDREQ setup time tEDRQS 13 — ns EDREQ hold time tEDRQH 2 — ns EDACK delay time tEDACD — 13 ns Test Conditions Figure 2.32 Figure 2.33, Figure 2.34 BCLK pin tEDRQS tEDRQH EDREQ0, EDREQ1 Figure 2.32 EDREQ0 and EDREQ1 Input Timing BCLK pin tEDACD tEDACD EDACK0, EDACK1 Figure 2.33 EDACK0 and EDACK1 Single-Address Transfer Timing (for a CS Area) BCLK pin tEDACD tEDACD EDACK0, EDACK1 Figure 2.34 EDACK0 and EDACK1 Single-Address Transfer Timing (for SDRAM) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 115 of 179 RX72N Group 2.4.7 2.4.7.1 Table 2.28 2. Electrical Characteristics Timing of On-Chip Peripheral Modules I/O Port I/O Port Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Item I/O ports Input data pulse width Symbol Min. Max. Unit*1 tPRW 1.5 — tPBcyc Test Conditions Figure 2.35 Note 1. tPBcyc: PCLKB cycle PCLKB Port tPRW Figure 2.35 I/O Port Input Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 116 of 179 RX72N Group 2. Electrical Characteristics 2.4.7.2 TPU Table 2.29 TPU Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Item TPU Input capture input pulse width Timer clock pulse width Symbol Single-edge setting tTICW Both-edge setting Single-edge setting Both-edge setting Phase counting mode tTCKWH, tTCKWL Min. Max. Unit*1 Test Conditions tPBcyc Figure 2.36 tPBcyc Figure 2.37 1.5 — 2.5 — 1.5 — 2.5 — 2.5 — Note 1. tPBcyc: PCLKB cycle PCLKB Input capture input Figure 2.36 tTICW TPU Input Capture Input Timing PCLKB TCLKA to TCLKD tTCKWL Figure 2.37 tTCKWH TPU Clock Input Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 117 of 179 RX72N Group 2. Electrical Characteristics 2.4.7.3 TMR Table 2.30 TMR Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Item TMR Timer clock pulse width Single-edge setting Both-edge setting Max. Unit*1 Test Conditions 1.5 — tPBcyc Figure 2.38 2.5 — Symbol Min. tTMCWH, tTMCWL Note 1. tPBcyc: PCLKB cycle PCLKB TMCI0 to TMCI3 tTMCWL Figure 2.38 TMR Clock Input Timing 2.4.7.4 CMTW Table 2.31 tTMCWH CMTW Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Item CMTW Input capture input pulse width Single-edge setting Both-edge setting Symbol Min. Max. Unit*1 Test Conditions tCMTWTICW 1.5 — tPBcyc Figure 2.39 2.5 — Note 1. tPBcyc: PCLKB cycle PCLKB Input capture input Figure 2.39 tCMTWICW CMTW Input Capture Input Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 118 of 179 RX72N Group 2. Electrical Characteristics 2.4.7.5 MTU Table 2.32 MTU Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Item MTU Input capture input pulse width Timer clock pulse width Symbol Single-edge setting tMTICW Both-edge setting Single-edge setting Both-edge setting Phase counting mode tMTCKWH, tMTCKWL Min. Max. Unit*1 Test Conditions tPAcyc Figure 2.40 tPAcyc Figure 2.41 1.5 — 2.5 — 1.5 — 2.5 — 2.5 — Note 1. tPAcyc: PCLKA cycle PCLKA Input capture input Figure 2.40 tMTICW MTU Input Capture Input Timing PCLKA MTCLKA to MTCLKD, MTIOC1A tMTCKWL Figure 2.41 tMTCKWH MTU Clock Input Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 119 of 179 RX72N Group 2.4.7.6 Table 2.33 2. Electrical Characteristics POE POE Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Item POE Symbol Min. Typ. Unit*1 Max. Test Conditions POEn# input pulse width (n = 0, 4, 8, 10, 11) tPOEW 1.5 — — Output disable time Transition of the POEn# signal level tPOEDI — — 5 PCLKB + 0.24 µs Figure 2.43 When detecting falling edges (ICSRm.POEnM[3:0] = 0000 (m = 1 to 5; n = 0, 4, 8, 10, 11)) Simultaneous conduction of output pins tPOEDO — — 3 PCLKB + 0.2 µs Figure 2.44 Register setting tPOEDS — — 1 PCLKB + 0.2 µs Figure 2.45 Time for access to the register is not included. tPOEDOS — — 21 µs Figure 2.46 Oscillation stop detection tPBcyc Figure 2.42 Note 1. tPBcyc: PCLKB cycle PCLKB POEn# input (n = 0, 4, 8, 10, 11) tPOEW Figure 2.42 POE# Input Timing POEn# input (n = 0, 4, 8, 10, 11) tPOEW Outputs disabled MTU PWM output pins tPOEDI Figure 2.43 Output Disable Time for POE in Response to Transition of the POEn# Signal Level R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 120 of 179 RX72N Group 2. Electrical Characteristics Simultaneous active-level outputs detected*1 Outputs disabled MTU PWM output pins tPOEDO Note 1. Figure 2.44 When the active level is set to low. Output Disable Time for POE in Response to the Simultaneous Conduction of Output Pins Corresponding bit in the SPOER register Outputs disabled MTU PWM output pins tPOEDS Figure 2.45 Output Disable Time for POE in Response to the Register Setting Main clock Oscillation stop detection signal (internal signal) Outputs disabled MTU PWM output pins tPOEDOS Figure 2.46 Output Disable Time for POE in Response to the Oscillation Stop Detection R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 121 of 179 RX72N Group 2.4.7.7 2. Electrical Characteristics POEG Table 2.34 POEG Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Item POEG Min. Typ. GTETRGn input pulse width (n = A to D) tPOEGW 1.5 — — Output disable time Input level detection of the GTETRGn pin (via flag) tPOEGDI — — 3 PCLKB + 0.34 µs Figure 2.48 When the digital noise filter is not in use (POEGGn.NFEN = 0 (n = A to D)) Detection of the output stopping signal from GPTW (deadtime error, simultaneous high output, or simultaneous low output) tPOEGDE — — 0.5 µs Figure 2.49 Register setting tPOEGDS — — 1 PCLKB + 0.3 µs Figure 2.50 Time for access to the register is not included. tPOEGDOS — — 21 µs Figure 2.51 Oscillation stop detection Max. Unit*1 Symbol Test Conditions tPBcyc Figure 2.47 Note 1. tPBcyc: PCLKB cycle PCLKB GTETRGn input (n = A to D) tPOEGW Figure 2.47 POEG Input Timing GTETRGn input (n = A to D) tPOEGW POEGGn.PIDF flag (n = A to D) Outputs disabled GPTW PWM output pins tPOEGDI Figure 2.48 Output Disable Time for POEG via Detection Flag in Response to the Input Level Detection of the GTETRGn pin R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 122 of 179 RX72N Group 2. Electrical Characteristics Output stopping signal from GPTW*1 Outputs disabled GPTW PWM output pins tPOEGDE Note 1. Figure 2.49 GPTWn.GTST.DTEF (dead time error flag), GPTWn.GTST.OABLF (simultaneous low output flag), or GPTWn.GTST.OABHF (simultaneous high output flag) Output Disable Time for POEG in Response to Detection of the Output Stopping Signal from GPTW POEGGn.SSF bit (n = A to D) Outputs disabled GPTW PWM output pins tPOEGDS Figure 2.50 Output Disable Time for POEG in Response to the Register Setting Main clock Oscillation stop detection signal (internal signal) Outputs disabled GPTW PWM output pins tPOEGDOS Figure 2.51 Output Disable Time of POEG in Response to the Oscillation Stop Detection R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 123 of 179 RX72N Group 2. Electrical Characteristics 2.4.7.8 GPTW Table 2.35 GPTW Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Item GPTW Input capture input pulse width Symbol Single-edge setting tGTICW Both-edge setting External trigger input pulse width Single-edge setting Both-edge setting tGTEW Min. Test Conditions Max. Unit*1, *2 tPAcyc Figure 2.52 tPBcyc Figure 2.53 1.5 — 2.5 — 1.5 — 2.5 — Note 1. tPAcyc: PCLKA cycle Note 2. tPBcyc: PCLKB cycle PCLKA Input capture input Figure 2.52 tGTICW GPTW Input Capture Input Timing PCLKB GTETRGn input (n = A to D) tGTEW Figure 2.53 GPTW External Trigger Input Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 124 of 179 RX72N Group 2.4.7.9 Table 2.36 2. Electrical Characteristics SCI SCI Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Item SCIh, SCIj Input clock cycle Symbol Asynchronous tScyc Clock synchronous Max. Unit*1 Test Conditions tPBcyc Figure 2.54 4 — 6 — Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr — 5 ns tSCKf — 5 ns tPBcyc Input clock fall time Output clock cycle Asynchronous*2 tScyc Clock synchronous 8 — 4 — Output clock pulse width tSCKW 0.4 0.6 tScyc Output clock rise time tSCKr — 5 ns Output clock fall time SCIi Min. tSCKf — 5 ns Transmit data delay time Clock synchronous tTXD — 28 ns Receive data setup time Clock synchronous tRXS 15 — ns Receive data hold time Clock synchronous tRXH 5 — ns Asynchronous tScyc tPAcyc Input clock cycle Clock synchronous 4 — 12 — Figure 2.55 Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr — 5 ns tSCKf — 5 ns tScyc 8 — tPAcyc 8 — Input clock fall time Output clock cycle Asynchronous*2 Clock synchronous Output clock pulse width tSCKW 0.4 0.6 tScyc Output clock rise time tSCKr — 5 ns tSCKf — 5 ns tTXD — 15 ns — 28 Output clock fall time Transmit data delay time Master Slave Receive data setup time Clock synchronous tRXS 20 — Receive data hold time Clock synchronous tRXH 5 — Figure 2.54 Figure 2.55 ns Note 1. tPBcyc: PCLKB cycle; tPAcyc: PCLKA cycle Note 2. When the SEMR.ABCS and SEMR.BGDM bits are set to 1 R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 125 of 179 RX72N Group 2. Electrical Characteristics tSCKW tSCKr tSCKf SCKn (n = 0 to 12) tScyc Figure 2.54 SCK Clock Input Timing SCKn tTXD TXDn tRXS tRXH RXDn (n = 0 to 12) Figure 2.55 SCI Input/Output Timing: Clock Synchronous Mode R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 126 of 179 RX72N Group Table 2.37 2. Electrical Characteristics Simple IIC Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, High-drive output is selected by the driving ability control register. Simple IIC (Standard-mode) Simple IIC (Fast-mode) Item Symbol Min. Max. Unit Test Conditions SSDA input rise time tSr — 1000 ns Figure 2.56 SSDA input fall time tSf — 300 ns SSDA input spike pulse removal time tSP 0 4 × tPBcyc ns Data input setup time tSDAS 250 — ns Data input hold time tSDAH 0 — ns SSCL, SSDA capacitive load Cb * 1 — 400 pF SSCL, SSDA input rise time tSr — 300 ns SSCL, SSDA input fall time tSf — 300 ns SSCL, SSDA input spike pulse removal time tSP 0 4 × tPBcyc ns Data input setup time tSDAS 100 — ns Data input hold time tSDAH 0 — ns *1 — 400 pF SSCL, SSDA capacitive load Cb Note: tPBcyc: PCLKB cycle Note 1. Cb is the total capacitance of the bus lines. VIH SSDA0 to SSDA12 VIL tBUF tSCLH tSTAS tSTAH tSTOS tSP SSCL0 to SSCL12 P*1 S*1 tSCLL tSr tSf tSCL tSDAS tSDAH Note 1. S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Restart condition Figure 2.56 P*1 Sr*1 Test conditions VIH = 0.7 × VCC, VIL = 0.3 × VCC VOL = 0.6 V, IOL = 6 mA Simple IIC Bus Interface Input/Output Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 127 of 179 RX72N Group Table 2.38 2. Electrical Characteristics Simple SPI Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Simple SPI Item Symbol SCK clock cycle output (master) tSPcyc Min. Unit*1 tPAcyc 4 65536 8 65536 tSPCKWH 0.4 0.6 tSPcyc SCK clock cycle input (slave) SCK clock high pulse width Max. SCK clock low pulse width tSPCKWL 0.4 0.6 tSPcyc tSPCKr, tSPCKf — 20 ns tSU 33.3 — ns Data input hold time tH 33.3 — ns SS input setup time tLEAD 1 — tSPcyc SS input hold time tLAG 1 — tSPcyc Data output delay time tOD — 33.3 ns Data output hold time tOH –10 — ns tDr, tDf — 16.6 ns SCK clock rise/fall time Data input setup time Data rise/fall time tSSLr, tSSLf — 16.6 ns Slave access time tSA — 5 tPBcyc Slave output release time tREL — 5 tPBcyc SS input rise/fall time Test Conditions Figure 2.57 Figure 2.58 to Figure 2.61 Figure 2.60, Figure 2.61 Note 1. tPAcyc: PCLKA cycle, tPBcyc: PCLKB cycle tSPCKr tSPCKWH SCKn master select output VOH VOH VOL tSPCKf VOH VOH VOL tSPCKWL VOL tSPcyc tSPCKr tSPCKWH VIH SCKn slave select input VIH VIL tSPCKf VIH VIL tSPCKWL VIH VIL tSPcyc (n = 0 to 12) VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC Figure 2.57 Simple SPI Clock Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 128 of 179 RX72N Group 2. Electrical Characteristics tTD SSn# output tLEAD tLAG tSSLr, tSSLf SCKn CKPOL = 0 output SCKn CKPOL = 1 output tSU SMISOn input tH MSB IN DATA tDr, tDf SMOSIn output LSB IN tOH MSB OUT MSB IN tOD DATA LSB OUT IDLE MSB OUT (n = 0 to 12) Figure 2.58 Simple SPI Timing (Master, CKPH = 1) tTD SSn# output tLEAD tLAG tSSLr, tSSLf SCKn CKPOL = 1 output SCKn CKPOL = 0 output tSU SMISOn input tH MSB IN tOH SMOSIn output DATA LSB IN tOD MSB OUT MSB IN tDr, tDf DATA LSB OUT IDLE MSB OUT (n = 0 to 12) Figure 2.59 Simple SPI Timing (Master, CKPH = 0) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 129 of 179 RX72N Group 2. Electrical Characteristics tTD SSn# input tLEAD tLAG SCKn CKPOL = 0 input SCKn CKPOL = 1 input tSA tOH SMISOn output tOD MSB OUT tSU SMOSIn input tREL DATA LSB OUT tH Invaild DATA MSB OUT tDr, tDf MSB IN DATA LSB IN MSB IN (n = 0 to 12) Figure 2.60 Simple SPI Timing (Slave, CKPH = 1) tTD SSn# input tLEAD tLAG SCKn CKPOL = 1 input SCKn CKPOL = 0 input tSA SMISOn output tOH tOD Invaild DATA MSB OUT tSU SMOSIn input tREL DATA tH MSB IN LSB OUT MSB OUT tDr, tDf DATA LSB IN MSB IN (n = 0 to 12) Figure 2.61 Simple SPI Timing (Slave, CKPH = 0) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 130 of 179 RX72N Group 2.4.7.10 Table 2.39 2. Electrical Characteristics RIIC RIIC Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, High-drive output is selected by the driving ability control register. Item Symbol Min.*1 Max. Unit Test Conditions Figure 2.62 tSCL 6(12) × tIICcyc + 1300 — ns tSCLH 3(6) × tIICcyc + 300 — ns tSCLL 3(6) × tIICcyc + 300 — ns SCL, SDA input rise time tSr — 1000 ns SCL, SDA input fall time tSf — 300 ns RIIC SCL input cycle time (Standard-mode, SCL input high pulse width SMBus) ICFER.FMPE = 0 SCL input low pulse width SCL, SDA input spike pulse removal time tSP 0 1(4) × tIICcyc ns SDA input bus free time tBUF 3(6) × tIICcyc + 300 — ns Start condition input hold time tSTAH tIICcyc + 300 — ns Restart condition input setup time tSTAS 1000 — ns Stop condition input setup time tSTOS 1000 — ns Data input setup time tSDAS tIICcyc + 50 — ns Data input hold time tSDAH 0 — ns SCL, SDA capacitive load C b* 2 — 400 pF tSCL 6(12) × tIICcyc + 600 — ns tSCLH 3(6) × tIICcyc + 300 — ns RIIC SCL input cycle time (Fast-mode) SCL input high pulse width ICFER.FMPE = 0 SCL input low pulse width tSCLL 3(6) × tIICcyc + 300 — ns SCL, SDA input rise time tSr 20 × (External pull-up voltage/5.5V) 300 ns SCL, SDA input fall time tSf 20 × (External pull-up voltage/5.5V) 300 ns SCL, SDA input spike pulse removal time tSP 0 1(4) × tIICcyc ns SDA input bus free time tBUF 3(6) × tIICcyc + 300 — ns Start condition input hold time tSTAH tIICcyc + 300 — ns Restart condition input setup time tSTAS 300 — ns Stop condition input setup time tSTOS 300 — ns Data input setup time tSDAS tIICcyc + 50 — ns Data input hold time tSDAH 0 — ns SCL, SDA capacitive load C b* 2 — 400 pF tSCL 6(12) × tIICcyc + 240 — ns tSCLH 3(6) × tIICcyc + 120 — ns tSCLL 3(6) × tIICcyc + 120 — ns tSr — 120 ns SCL, SDA input fall time tSf — 120 ns SCL, SDA input spike pulse removal time tSP 0 1(4) × tIICcyc ns SDA input bus free time tBUF 3(6) × tIICcyc + 120 — ns Start condition input hold time tSTAH tIICcyc + 120 — ns Restart condition input setup time tSTAS 120 — ns Stop condition input setup time tSTOS 120 — ns RIIC SCL input cycle time (Fast-mode+) SCL input high pulse width ICFER.FMPE = 1 SCL input low pulse width SCL, SDA input rise time Data input setup time tSDAS tIICcyc + 20 — ns Data input hold time tSDAH 0 — ns SCL, SDA capacitive load C b* 2 — 550 pF R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 131 of 179 RX72N Group 2. Electrical Characteristics Note: tIICcyc: RIIC internal reference clock (IICφ) cycle Note 1. The value within parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 11b while the digital filter is enabled by the setting ICFER.NFE = 1. Note 2. Cb is the total capacitance of the bus lines. VIH SDA0 to SDA2 VIL tBUF tSCLH tSTAS tSTAH tSTOS tSP SCL0 to SCL2 P*1 S*1 tSCLL tSr tSf tSCL tSDAS tSDAH Note 1. S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Restart condition Figure 2.62 P*1 Sr*1 Test conditions VIH = 0.7 × VCC, VIL = 0.3 × VCC VOL = 0.6 V, IOL = 6 mA (ICFER.FMPE = 0) VOL = 0.4 V, IOL = 15 mA (ICFER.FMPE = 1) RIIC Bus Interface Input/Output Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 132 of 179 RX72N Group 2.4.7.11 Table 2.40 2. Electrical Characteristics RSPI RSPI Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Item RSPI RSPCK clock cycle Symbol Master tSPcyc Master (tSPcyc – tSPCKr – tSPCKf) / 2 – 3 — (tSPcyc – tSPCKr – tSPCKf) / 2 — (tSPcyc – tSPCKr – tSPCKf) / 2 – 3 — (tSPcyc – tSPCKr – tSPCKf) / 2 — tSPCKr, tSPCKf — 5 ns — 1 µs tSU 6 — ns tSPCKWL Slave RSPCK clock rise/fall time Output Data input setup time Master Data input hold time Master Input Slave 8.3 — PCLKA division ratio set to 1/2 tHF 0 — PCLKA division ratio set to a value other than 1/2 tH tPAcyc — 8.3 — Slave SSL setup time Master tLEAD Slave SSL hold time Master tLAG Slave Data output delay time Master tOD Master Master MOSI and MISO rise/fall time SSL rise/fall time Output 1 8 tSPcyc 6 — tPAcyc 1 8 tSPcyc 6 — tPAcyc ns 28 tOH 0 — 0 — tTD tSPcyc + 2 × tPAcyc 8 × tSPcyc + 2 × tPAcyc 6 × tPAcyc — — 5 ns — 1 µs — 5 ns tDr, tDf Input Figure 2.64 to Figure 2.69 ns 6.3 Slave Figure 2.63 ns — Slave Successive transmission delay time Test Conditions*2 ns — Slave Data output hold time tPAcyc — — tSPCKWH Master Unit*1 2 Slave RSPCK clock low pulse width Max.*1 4 Slave RSPCK clock high pulse width Min.*1 ns ns Output tSSLr, Input tSSLf — 1 µs Slave access time tSA — 2 × tPAcyc + 28 ns Slave output release time tREL — 2 × tPAcyc + 28 ns Figure 2.68, Figure 2.69 Note 1. tPAcyc: PCLKA cycle Note 2. We recommend using pins that have a letter (“-A”, “-B”, etc.) to indicate group membership appended to their names as groups. For the RSPI interface, the AC portion of the electrical characteristics is measured for each group. R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 133 of 179 RX72N Group 2. Electrical Characteristics tSPCKr tSPCKWH VOH RSPCKA master select output VOH VOL tSPCKf VOH VOH VOL tSPCKWL VOL tSPcyc tSPCKr tSPCKWH VIH VIH RSPCKA slave select input VIL tSPCKf VIH VIH VIL tSPCKWL VIL tSPcyc VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC Figure 2.63 RSPI Clock Timing tTD SSLA0 to SSLA3 output tLEAD tLAG tSSLr, tSSLf RSPCKA CPOL = 0 output RSPCKA CPOL = 1 output tSU MISOA input tH MSB IN tDr, tDf MOSIA output Figure 2.64 DATA tOH MSB OUT LSB IN MSB IN tOD DATA LSB OUT IDLE MSB OUT RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKA Division Ratio Set to a Value Other Than 1/2) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 134 of 179 RX72N Group 2. Electrical Characteristics tTD SSLA0 to SSLA3 output tLEAD tLAG tSSLr, tSSLf RSPCKA CPOL = 0 output RSPCKA CPOL = 1 output tSU MISOA input tHF MSB IN DATA tDr, tDf MOSIA output Figure 2.65 tHF tOH MSB OUT LSB IN MSB IN tOD DATA LSB OUT IDLE MSB OUT RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKA Division Ratio Set to 1/2) tTD SSLA0 to SSLA3 output tLEAD tLAG tSSLr, tSSLf RSPCKA CPOL = 0 output RSPCKA CPOL = 1 output tSU MISOA input tH MSB IN tOH MOSIA output Figure 2.66 DATA LSB IN tOD MSB OUT MSB IN tDr, tDf DATA LSB OUT IDLE MSB OUT RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKA Division Ratio Set to a Value Other Than 1/2) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 135 of 179 RX72N Group 2. Electrical Characteristics tTD SSLA0 to SSLA3 output tLEAD tLAG tSSLr, tSSLf RSPCKA CPOL = 0 output RSPCKA CPOL = 1 output tSU MISOA input tHF MSB IN tOH DATA LSB IN tOD MOSIA output Figure 2.67 tH MSB IN tDr, tDf MSB OUT DATA LSB OUT IDLE MSB OUT RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKA Division Ratio Set to 1/2) tTD SSLA0 input tLEAD tLAG RSPCKA CPOL = 0 input RSPCKA CPOL = 1 input tSA tOH MISOA output MSB OUT tSU MOSIA input Figure 2.68 tOD DATA tREL LSB OUT tH MSB IN Invaild DATA MSB OUT tDr, tDf DATA LSB IN MSB IN RSPI Timing (Slave, CPHA = 0) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 136 of 179 RX72N Group 2. Electrical Characteristics tTD SSLA0 input tLEAD tLAG RSPCKA CPOL = 0 input RSPCKA CPOL = 1 input tSA MISOA output tOH tOD Invaild DATA MSB OUT tSU MOSIA input Figure 2.69 tREL tH MSB IN LSB OUT DATA MSB OUT tDr, tDf DATA LSB IN MSB IN RSPI Timing (Slave, CPHA = 1) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 137 of 179 RX72N Group 2.4.7.12 Table 2.41 2. Electrical Characteristics QSPI QSPI Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Item QSPI Symbol Min. Max. Unit*1 Test Conditions*2 QSPCLK clock cycle tQScyc 2 4080 tPBcyc Figure 2.70 Data input setup time tSu 6.5 — ns Data input hold time tIH 5 — ns Figure 2.71, Figure 2.72 SS setup time tLEAD 1.5 8.5 tQScyc SS hold time tLAG 1 8 tQScyc Data output delay time tOD — 10.0 ns Data output hold time tOH –5 — ns Successive transmission delay time tTD 1 8 tQScyc Note 1. tPBcyc: PCLKB cycle Note 2. We recommend using pins that have a letter (“-A”, “-B”, etc.) to indicate group membership appended to their names as groups. For the QSPI interface, the AC portion of the electrical characteristics is measured for each group. QSPCLK output tQScyc Figure 2.70 QSPI Clock Timing tTD QSSL output QSPCLK CPOL = 0 output tLEAD tLAG QSPCLK CPOL = 1 output tSU QMI, QIO0 to QIO3 input tIH MSB IN DATA tOH QMO, QIO0 to QIO3 output Figure 2.71 MSB OUT LSB IN tOD DATA LSB OUT IDLE Transmit/Receive Timing (CPHA = 0) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 138 of 179 RX72N Group 2. Electrical Characteristics tTD QSSL output QSPCLK CPOL = 0 output tLEAD tLAG QSPCLK CPOL = 1 output tSU QMI, QIO0 to QIO3 input tIH MSB IN tOH QMO, QIO0 to QIO3 output Figure 2.72 DATA LSB IN tOD MSB OUT DATA LSB OUT IDLE Transmit/Receive Timing (CPHA = 1) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 139 of 179 RX72N Group 2.4.7.13 Table 2.42 2. Electrical Characteristics SSIE Expansion Serial Sound Interface Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Item AUDIO_CLK Symbol Cycle Unit tEXcyc 20 — ns 0.4 0.6 tEXcyc Master tO 80 — ns Slave tI 80 — ns Master tHC 0.35 — tO tLC 0.35 — tO tHC 0.35 — tI tLC 0.35 — tI Master tRC — 0.15 tO tFC — 0.15 tO Slave tRC — 0.15 tI tFC — 0.15 tI Input setup time Master tSR 12 — ns Input hold time Master Cycle Output clock high level Output clock low level Input clock high level Slave Input clock low level Output clock rise time Output clock fall time Input clock rise time Input clock fall time SSILRCKn,SSITXD0, SSIRXD0, SSIDATA1 Max. tEXL/tEXH High/low level SSIBCKn Min. Slave 12 — ns tHR 8 — ns 15 — ns tDTR –10 5 ns 0 20 ns tDTRW — 20 ns Slave Output delay time Master Slave Slave Output delay time from when an SSILRCK0 signal is changed*1 Test Conditions Figure 2.73 Figure 2.74 Figure 2.75, Figure 2.76 Figure 2.77 n = 0, 1 Note 1. The SSIE has a single path for transmission in slave mode. To generate the data for transmission, the signals input through the SSILRCKn pin through the abovementioned path are used. After that, the data for transmission proceed to be used as the logical outputs to the SSITXD0 or SSIDATA1 pin. tEXcyc tEXH tEXL AUDIO_CLK (input) 1/2 VCC tEXf Figure 2.73 tEXr Clock Input Timing tHC tRC tFC tLC SSIBCKn tI, tO (n = 0, 1) Figure 2.74 SSIE Clock Input/Output Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 140 of 179 RX72N Group 2. Electrical Characteristics SSIBCKn (input or output) SSILRCKn (input), SSIRXD0, SSIDATA1 (input) tSR tHR SSILRCKn (output), SSITXD0, SSIDATA1 (output) (n = 0, 1) Figure 2.75 tDTR Transmission and Reception Timing for the SSIE Data When the SSICR.BCKP Bit is 0 SSIBCKn (input or output) SSILRCKn (input), SSIRXD0, SSIDATA1 (input) tSR tHR SSILRCKn (output), SSITXD0, SSIDATA1 (output) (n = 0, 1) tDTR Figure 2.76 Transmission and Reception Timing for the SSIE Data When the SSICR.BCKP Bit is 1 SSILRCKn (input) SSITXD0, SSIDATA1 (output) (n = 0, 1) tDTRW MSB bit output timing in slave transmission from SSILRCKn with the settings of DEL = 1, SDTA = 0, or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0] Figure 2.77 Output Delay of the SSIE Data from When an SSILRCKn Signal is Changed R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 141 of 179 RX72N Group 2.4.7.14 2. Electrical Characteristics PMGI Table 2.43 PMGI Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, ICLK = PCLKA = 8 to 120 MHz, PCLKB = BCLK = SDCLK = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Item PMGI PMGIn_MDC output cycle Symbol Min. Max. Unit tMDC 80 — ns PMGIn_MDIO setup time (relative to PMGIn_MDC↑) tSMDIO 20 — ns PMGIn_MDIO hold time (relative to PMGIn_MDC↑) tHMDIO 0 — ns PMGIn_MDIO output delay time (relative to PMGIn_MDC↑) tDMDIO 0 20 ns Test Conditions Figure 2.78 n = 0, 1 tMDC PMGIn_MDC (output) tSMDIO tHMDIO PMGIn_MDIO PMGIn_MDIO (input) (input) tDMDIO tDMDIO PMGIn_MDIO PMGIn_MDIO (output) (output) (n = 0, 1) Figure 2.78 Timing of Serial Management Access R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 142 of 179 RX72N Group 2.4.7.15 Table 2.44 2. Electrical Characteristics MMC MMC Host Interface Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Item MMCIF MMC_CLK clock cycle Symbol Min.*1 Max. Unit Test Conditions*2 Figure 2.79 tMMCPP 2 × tPBcyc — ns MMC_CLK clock high level width tMMCWH 6.5 — ns MMC_CLK clock low level width tMMCWL 6.5 — ns MMC_CLK clock rising time tMMCLH — 3 ns MMC_CLK clock falling time tMMCHL — 3 ns MMC_CMD, MMC_D7 to MMC_D0 output data delay (data transfer mode) tMMCODLY –6.6 6.6 ns MMC_CMD, MMC_D7 to MMC_D0 input data setup tMMCISU 8 — ns MMC_CMD, MMC_D7 to MMC_D0 input data hold tMMCIH 2.5 — ns Note 1. tPBcyc: PCLKB cycle Note 2. We recommend using pins that have a letter (“-A”, “-B”, etc.) to indicate group membership appended to their names as groups. For the MMC interface, the AC portion of the electrical characteristics is measured for each group. tMMCPP tMMCWL tMMCWH MMC_CLK tMMCHL tMMCLH tMMCISU tMMCIH MMC_CMD, MMC_D7 to MMC_D0 input MMC_CMD, MMC_D7 to MMC_D0 output tMMCODLY (max) Figure 2.79 tMMCODLY (min) MMC Interface R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 143 of 179 RX72N Group 2.4.7.16 Table 2.45 2. Electrical Characteristics SDHI SDHI Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6V, 2.7V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30pF High-drive output is selected by the driving ability control register. Item SDHI Symbol Min. Max. Unit Test Conditions*1 Figure 2.80 SDHI_CLK output cycle time tPP(SD) 20 — ns SDHI_CLK output width at high level tWH(SD) 0.4 × tPP(SD) — ns SDHI_CLK output width at low level tWL(SD) 0.4 × tPP(SD) — ns SDHI_CLK output rising time tTLH(SD) — 3 ns SDHI_CLK output falling time tTHL(SD) — 3 ns tODLY(SD) –6.5 4 ns SDHI_CMD, SDHI_D3 to SDHI_D0 input data setup time tISU(SD) 6 — ns SDHI_CMD, SDHI_D3 to SDHI_D0 input data hold time tIH(SD) 2 — ns SDHI_CMD, SDHI_D3 to SDHI_D0 output data delay (data transfer mode) Note 1. We recommend using pin names that have a letter (“-A”, “-B”, etc.) to indicate group membership per group in the test. For the SDHI, the AC portion of the electrical characteristics is measured per group. tPP(SD) tWL(SD) SDHI_CLK output VIH VIH 50% VCC VIH 50% VCC VL tTHL(SD) tWH(SD) VL VL tTLH(SD) tISU(SD) tIH(SD) SDHI_CMD, SDHI_D3 to SDHI_D0 input tODLY(SD) tODLY(SD) SDHI_CMD, SDHI_D3 to SDHI_D0 output Figure 2.80 SD Host Interface Input/Output Signal Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 144 of 179 RX72N Group 2.4.7.17 Table 2.46 2. Electrical Characteristics ETHERC ETHERC Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, RMII: High-drive output for the high-speed interface is selected in the drive capacity selection control register. MII: High-drive output is selected by the driving ability control register. Item ETHERC (RMII) Symbol Min. Max. Unit REF50CK cycle time Tck 20 — ns REF50CK frequency Typ. 50 MHz — — 50 + 100 ppm MHz REF50CK duty REF50CK rise/fall time RMIIn_xxxx*1 output delay time RMIIn_xxxx*2 ETHERC (MII) setup time — 35 65 % Tckr/ckf 0.5 3.5 ns Tco 2.5 15.0 ns Tsu 3 — ns RMIIn_xxxx*2 hold time Thd 1 — ns RMIIn_xxxx*1, *2 Tr/Tf — 5 ns rise/fall time ETn_WOL output delay time tWOLd 1 23.5 ns ETn_TX_CLK cycle time tTcyc 40 — ns ETn_TX_EN output delay time tTENd 1 20 ns ETn_ETXD0 to ETn_ETXD3 output delay time tMTDd 1 20 ns ETn_CRS setup time tCRSs 10 — ns ETn_CRS hold time tCRSh 10 — ns ETn_COL setup time tCOLs 10 — ns ETn_COL hold time tCOLh 10 — ns ETn_RX_CLK cycle time tTRcyc 40 — ns ETn_RX_DV setup time tRDVs 10 — ns ETn_RX_DV hold time tRDVh 10 — ns ETn_ERXD0 to ETn_ERXD3 setup time tMRDs 10 — ns ETn_ERXD0 to ETn_ERXD3 hold time tMRDh 10 — ns ETn_RX_ER setup time tRERs 10 — ns ETn_RX_ER hold time tRERh 10 — ns ETn_WOL output delay time tWOLd 1 23.5 ns Test Conditions Figure 2.81 to Figure 2.84 Figure 2.85 — Figure 2.86 Figure 2.87 — Figure 2.88 Figure 2.89 Figure 2.90 n = 0, 1 Note 1. RMIIn_TXD_EN, RMIIn_TXD1, RMIIn_TXD0 Note 2. RMIIn_CRS_DV, RMIIn_RXD1, RMIIn_RXD0, RMIIn_RX_ER R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 145 of 179 RX72N Group 2. Electrical Characteristics Tck 90% Tckr REF50CK 50% Tckf 10% Tco Tf Tr Tsu Thd 70% *11 RMIIn_xxxx* RMII0_xxxx 50% Change in Signal signal level Change in signal level Change in signal level Signal 30% (n = 0, 1) Note 1. RMIIn_TXD_EN, RMIIn_TXD1, RMIIn_TXD0, RMIIn_CRS_DV, RMIIn_RXD1, RMIIn_RXD0, RMIIn_RX_ER Figure 2.81 Timing with the REF50CK and RMII Signals TCK REF50CK TCO RMIIn_TXD_EN RMII0_TXD_EN TCO RMIIn_TXD_1, RMII0_TXD1, RMIIn_TXD_0 RMII0_TXD0 Preamble SFD DATA CRC (n = 0, 1) Figure 2.82 RMII Transmission Timing REF50CK Tsu Thd RMII0_CRS_DV RMIIn_CRS_DV Thd Tsu RMIIn_RXD_1, RMII0_RXD1, RMIIn_RXD_0 RMII0_RXD0 Preamble DATA CRC SFD RMIIn_RX_ER RMII0_RX_ER L (n = 0, 1) Figure 2.83 RMII Reception Timing (Normal Operation) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 146 of 179 RX72N Group 2. Electrical Characteristics REF50CK RMIIn_CRS_DV RMII0_CRS_DV RMII0_RXD1, RMIIn_RXD_1, RMII0_RXD0 RMIIn_RXD_0 Preamble SFD DATA xxxx Thd Tsu RMIIn_RX_ER RMII0_RX_ER (n = 0, 1) Figure 2.84 RMII Reception Timing (Error Occurrence) REF50CK tWOLd ETn_WOL ET0_WOL (n = 0, 1) Figure 2.85 WOL Output Timing (RMII) ETn_TX_CLK ET0_TX_CLK tTENd ETn_TX_EN ET0_TX_EN tMTDd ETn_ETXD[3:0] ET0_ETXD[3:0] Preamble SFD DATA CRC ETn_TX_ER ET0_TX_ER tCRSs tCRSh ETn_CRS ET0_CRS ETn_COL ET0_COL (n = 0, 1) Figure 2.86 MII Transmission Timing (Normal Operation) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 147 of 179 RX72N Group 2. Electrical Characteristics ETn_TX_CLK ET0_TX_CLK ETn_TX_EN ET0_TX_EN ETn_ETXD[3:0] ET0_ETXD[3:0] JAM Preamble ETn_TX_ER ET0_TX_ER ETn_CRS ET0_CRS tCOLs tCOLh ETn_COL ET0_COL (n = 0, 1) Figure 2.87 MII Transmission Timing (Conflict Occurrence) ETn_RX_CLK ET0_RX_CLK tRDVs tRDVh ETn_RX_DV ET0_RX_DV tMRDh tMRDs ETn_ERXD[3:0] ET0_ERXD[3:0] Preamble SFD DATA CRC ETn_RX_ER ET0_RX_ER (n = 0, 1) Figure 2.88 MII Reception Timing (Normal Operation) ETn_RX_CLK ET0_RX_CLK ETn_RX_DV ET0_RX_DV ET0_ERXD[3:0] ETn_ERXD[3:0] Preamble SFD DATA xxxx tRERh tRERs ETn_RX_ER ET0_RX_ER (n = 0, 1) Figure 2.89 MII Reception Timing (Error Occurrence) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 148 of 179 RX72N Group 2. Electrical Characteristics ETn_RX_CLK ET0_RX_CLK tWOLd ETn_WOL ET0_WOL (n = 0, 1) Figure 2.90 WOL Output Timing (MII) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 149 of 179 RX72N Group 2.4.7.18 Table 2.47 2. Electrical Characteristics PDC PDC Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Item PDC Symbol Min.*1 Max. Unit tPIXcyc 37 — ns PIXCLK input high pulse width tPIXH 10 — ns PIXCLK input low pulse width tPIXL 10 — ns PIXCLK rising time tPIXr — 5 ns PIXCLK falling time tPIXf — 5 ns tPCKcyc 2 × tPBcyc — ns PIXCLK input cycle time PCKO output cycle time PCKO output high pulse width tPCKH (tPCKcyc – tPCKr – tPCKf)/2 – 3 — ns PCKO output low pulse width tPCKL (tPCKcyc – tPCKr – tPCKf)/2 – 3 — ns PCKO rising time tPCKr — 5 ns PCKO falling time tPCKf — 5 ns VSYNC/HSYNC input setup time tSYNCS 10 — ns VSYNC/HSYNC input hold time tSYNCH 5 — ns PIXD input setup time tPIXDS 10 — ns PIXD input hold time tPIXDH 5 — ns Test Conditions Figure 2.91 Figure 2.92 Figure 2.93 Note 1. tPBcyc: PCLKB cycle tPIXcyc tPIXH tPIXf PIXCLK input tPIXr tPIXL Figure 2.91 PDC Input Clock Timing tPCKcyc tPCKH tPCKf PCKO pin output tPCKr tPCKL Figure 2.92 PDC Output Clock Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 150 of 179 RX72N Group 2. Electrical Characteristics PIXCLK tSYNCS tSYNCH VSYNC tSYNCS tSYNCH HSYNC tPIXDS tPIXDH PIXD7 to PIXD0 Figure 2.93 PDC AC Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 151 of 179 RX72N Group 2.4.7.19 Table 2.48 2. Electrical Characteristics GLCDC GLCDC Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF Item Symbol Min. Typ. Max. Unit MHz LCD_EXTCLK Input clock frequency tEcyc — — 30*1 LCD_EXTCLK Input clock Low pulse width tWL 0.45 — 0.55 tEcyc LCD_EXTCLK Input clock High pulse width tWH 0.45 — 0.55 tEcyc MHz LCD_CLK Output clock frequency tLcyc — — 30*1 LCD_CLK Output clock Low pulse width tLOL 0.4 — 0.6 tLcyc LCD_CLK Output clock High pulse width tLOH 0.4 — 0.6 tLcyc LCD_CLK Output clock rise time tLOR — — 5 ns LCD_CLK Output clock fall time tLOF — — 5 ns tDD –3.5*2 — 4*2 ns LCD data output Delay timing Test Conditions Figure 2.94 Figure 2.95 Figure 2.96 Note 1. Parallel RGB888,666,565: Max. 27 MHz Serial RGB888: Max. 30 MHz (4x speed) Note 2. We recommend using pins that have a letter (“-A”, “-B”, etc) to indicate group membership appended to their names as groups. For the GLCDC interface, the AC portion of the electrical characteristics is measured for each group. If we use group “-A” and “-B” combination, “LCD data output Delay timing (tDD)” is Min = –5.0 ns, Max = 5.5 ns. tDcyc, tEcyc tWH 1/2 Vcc VIH tWL VIH VIL LCD_EXTCLK Figure 2.94 VIL LCD_EXTCLK Clock Input Timing tLcyc tLOL tLOH LCD_CLK tLOF Figure 2.95 tLOR LCD_CLK Clock Output Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 152 of 179 RX72N Group 2. Electrical Characteristics LCD_CLK tDD Output on falling edge LCD_DATA23 to LCD_DATA0, LCD_TCON3 to LCD_TCON0 Figure 2.96 tDD Output on rising edge LCD Output Data Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 153 of 179 RX72N Group 2. Electrical Characteristics 2.4.7.20 A/D Converter Trigger Table 2.49 A/D Converter Trigger Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Item A/D converter A/D converter trigger input pulse width Symbol Min. Max. Unit*1 tTRGW 1.5 — tPBcyc Test Conditions Figure 2.97 Note 1. tPBcyc: PCLKB cycle PCLKB ADTRG0#, ADTRG1# tTRGW Figure 2.97 A/D Converter Trigger Input Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 154 of 179 RX72N Group 2.4.7.21 Table 2.50 2. Electrical Characteristics CAC CAC Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Item*1, *2 CAC CACREF input pulse width tPBcyc ≤ tcac tPBcyc > tcac Symbol Min.*1, *2 Max. Unit tCACREF 4.5 tcac + 3 tPBcyc — ns 5 tcac + 6.5 tPBcyc — Test Conditions Note 1. tPBcyc: PCLKB cycle Note 2. tcac: CAC count clock source cycle R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 155 of 179 RX72N Group 2.5 2. Electrical Characteristics USB Characteristics Table 2.51 On-Chip USB Low Speed (Host Only) Characteristics (DP and DM Pin Characteristics) Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 3.0 to 3.6 V, 3.0 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, UCLK = 48 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr Item Input characteristics Output characteristics Symbol Min. Typ. Input high level voltage VIH 2.0 Input low level voltage VIL — Differential input sensitivity VDI Differential common mode range Output high level voltage Output low level voltage Cross-over voltage Max. Unit — — V — 0.8 V 0.2 — — V VCM 0.8 — 2.5 V VOH 2.8 — 3.6 V IOH = –200 µA VOL 0.0 — 0.3 V IOL = 2 mA VCRS 1.3 — 2.0 V Figure 2.98 tLR 75 — 300 ns Rise time Fall time Rise/fall time ratio Pull-down characteristics tLF 75 — 300 ns tLR / tLF 80 — 125 % Rpd 14.25 — 24.80 kΩ DP/DM pull-down resistance (when the host controller function is selected) DP, DM 90% VCRS | DP – DM | tLR/ tLF 90% 10% 10% tLR Figure 2.98 Test Conditions tLF DP and DM Output Timing (Low Speed) dp 27 Observation point 200 pF to 600 pF 3.6 V 1.5 k dm 27 200 pF to 600 pF Figure 2.99 Test Circuit (Low Speed) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 156 of 179 RX72N Group Table 2.52 2. Electrical Characteristics On-Chip USB Full-Speed Characteristics (DP and DM Pin Characteristics) Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 3.0 to 3.6 V, 3.0 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, UCLK = 48 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr Item Input characteristics Output characteristics Min. Typ. Unit Test Conditions Input high level voltage VIH 2.0 — — V VIL — — 0.8 V Differential input sensitivity VDI 0.2 — — V Differential common mode range VCM 0.8 — 2.5 V Output high level voltage VOH 2.8 — 3.6 V IOH = –200 µA Output low level voltage VOL 0.0 — 0.3 V IOL = 2 mA VCRS 1.3 — 2.0 V Figure 2.100 tFR 4 — 20 ns Rise time | DP – DM | tFF 4 — 20 ns Rise/fall time ratio tFR / tFF 90 — 111.11 % tFR/ tFF Output resistance ZDRV 28 — 44 Ω Rs = 27 Ω included DP pull-up resistance (when the function controller function is selected) Rpu 0.900 — 1.575 kΩ Idle state 1.425 — 3.090 DP/DM pull-down resistance (when the host controller function is selected) Rpd 14.25 — 24.80 Fall time DP, DM 90% VCRS At transmission and reception kΩ 90% 10% 10% tFR Figure 2.100 Max. Input low level voltage Cross-over voltage Pull-up and pull-down characteristics Symbol tFF DP and DM Output Timing (Full-Speed) dp 27 Observation point 50 pF dm 27 50 pF Figure 2.101 Test Circuit (Full-Speed) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 157 of 179 RX72N Group 2.6 2. Electrical Characteristics A/D Conversion Characteristics Table 2.53 12-Bit A/D (Unit 0) Conversion Characteristics Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKB = PCLKC = 1 MHz to 60 MHz, Ta = Topr, Source impedance = 1.0 kΩ Item Resolution Analog input capacitance Min. Typ. Max. Unit 8 — 12 Bit Test Conditions — — 30 pF Channel-dediConversion time*1 cated sample-and- (Operation at PCLKC = 60 MHz) hold circuits in use (AN000 to AN002) 1.06 (0.4 + 0.25) *2 — — µs  Sampling of channeldedicated sample-andhold circuits in 24 states  Sampling in 15 states Offset error — ±1.5 ±3.5 LSB AN000 to AN002 = 0.25 V Full-scale error — ±1.5 ±3.5 LSB AN000 to AN002 = VREFH0 – 0.25 V Quantization error — ±0.5 — LSB Absolute accuracy — ±3.0 ±5.5 LSB DNL differential nonlinearity error — ±1.0 ±2.0 LSB INL integral nonlinearity error — ±1.5 ±3.0 LSB Holding characteristics of sample-andhold circuits — — 20 µs 0.25 — VREFH0 – 0.25 V 0.48 (0.267)*2 — — µs Offset error — ±1.0 ±2.5 LSB Full-scale error — ±1.0 ±2.5 LSB Quantization error — ±0.5 — LSB Absolute accuracy — ±2.5 ±4.5 LSB DNL differential nonlinearity error — ±0.5 ±1.5 LSB INL integral nonlinearity error — ±1.0 ±2.5 LSB Dynamic range Channel-dedicated sample-andhold circuits not in use (AN000 to AN007) Conversion time*1 (Operation at PCLKC = 60 MHz) Sampling in 16 states Note: The above specification values apply when there is no access to the external bus during A/D conversion. If access proceeds during A/D conversion, values may not fall within the above ranges. Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states is indicated. Note 2. The value in parentheses indicates the sampling time. R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 158 of 179 RX72N Group Table 2.54 2. Electrical Characteristics 12-Bit A/D (Unit 1) Conversion Characteristics Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKB = PCLKD = 1 MHz to 60 MHz, Ta = Topr, Source impedance = 1.0 kΩ Item Min. Typ. Max. Unit 8 — 12 Bit Conversion (Operation at PCLKD = 60 MHz) 0.88 (0.633)*2 — — µs Sampling in 38 states (ADSAM.SAM = 1) Conversion time*1 (Operation at PCLKD = 30 MHz) 1 (0.500)*2 — — µs Sampling in 15 states (ADSAM.SAM = 1) — — 30 pF Resolution time*1 Analog input capacitance Offset error — ±2.0 ±3.5 LSB Full-scale error — ±2.0 ±3.5 LSB Quantization error — ±0.5 — LSB Absolute accuracy — ±4.0 ±6.0 LSB DNL differential nonlinearity error (Operation at PCLKD = 60 MHz) — ±1.5 ±4.0 LSB DNL differential nonlinearity error (Operation at PCLKD = 30 MHz) — ±1.5 ±2.5 LSB INL integral nonlinearity error (Operation at PCLKD = 60 MHz) — ±2.0 ±4.0 LSB INL integral nonlinearity error (Operation at PCLKD = 30 MHz) — ±2.0 ±3.5 LSB Test Conditions Note: The above specification values apply when there is no access to the external bus during A/D conversion. If access proceeds during A/D conversion, values may not fall within the above ranges. Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states is indicated. Note 2. The value in parentheses indicates the sampling time. Table 2.55 A/D Internal Reference Voltage Characteristics Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKB = PCLKD = 60 MHz, Ta = Topr Item A/D internal reference voltage R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Min. Typ. Max. Unit 1.13 1.18 1.23 V Test Conditions Page 159 of 179 RX72N Group 2.7 2. Electrical Characteristics D/A Conversion Characteristics Table 2.56 D/A Conversion Characteristics Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr Item Symbol Min. Typ. Max. Unit Resolution — 12 12 12 Bit Unbuffered output Absolute accuracy — — — ±6.0 LSB 2-MΩ resistive load 10-bit conversion 2-MΩ resistive load Differential nonlinearity error Buffered output DNL — ±1.0 ±2.0 LSB Output resistance RO — 8.6 — kΩ Setting time tS — — 3 µs Load resistance RL 5 — — kΩ Load capacitance CL — — 50 pF Output voltage VO 0.2 — AVCC1 – 0.2 V Differential nonlinearity error DNL — ±1.0 ±2.0 LSB Integral nonlinearity error INL — ±2.0 ±4.0 LSB tS — — 4 µs Setting time 2.8 Test Conditions 20-pF capacitive load Temperature Sensor Characteristics Table 2.57 Temperature Sensor Characteristics Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr Min. Typ. Max. Unit Relative accuracy Item — ±1 — °C Temperature slope — 4 — mV/°C Output voltage — 1.21 — V Temperature sensor start time — — 30 µs 4.15 — — µs Sampling time*1 Test Conditions Ta = 25°C Note 1. Set the S12AD1.ADSSTRT register such that the sampling time of the 12-bit A/D converter satisfies this specification. R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 160 of 179 RX72N Group 2.9 2. Electrical Characteristics Power-on Reset Circuit and Voltage Detection Circuit Characteristics Table 2.58 Power-on Reset Circuit and Voltage Detection Circuit Characteristics Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr Item Voltage detection level Power-on reset (POR) Symbol Min. Typ. Max. Unit VPOR 2.5 2.6 2.7 V 1.8 2.25 2.7 Low power consumption function disabled*1 Low power consumption function enabled*2 Voltage detection circuit (LVD0) Figure 2.102 Vdet0_1 2.84 2.94 3.04 Vdet0_2 2.77 2.87 2.97 Vdet0_3 2.70 2.80 2.90 Vdet1_1 2.89 2.99 3.09 Vdet1_2 2.82 2.92 3.02 Vdet1_3 2.75 2.85 2.95 Vdet2_1 2.89 2.99 3.09 Vdet2_2 2.82 2.92 3.02 Vdet2_3 2.75 2.85 2.95 Power-on reset time tPOR — 4.6 — LVD0 reset time tLVD0 — 0.70 — Figure 2.103 LVD1 reset time tLVD1 — 0.57 — Figure 2.104 Voltage detection circuit (LVD1) Voltage detection circuit (LVD2) Internal reset time Test Conditions LVD2 reset time Figure 2.103 Figure 2.104 Figure 2.105 ms Figure 2.102 tLVD2 — 0.57 — tVOFF 200 — — µs Figure 2.102, Figure 2.103 tdet — — 200 µs Figure 2.102 to Figure 2.105 LVD operation stabilization time (after LVD is enabled) td(E-A) — — 10 µs Hysteresis width (LVD1 and LVD2) V LVH — 70 — mV Figure 2.104, Figure 2.105 Minimum VCC down time Response delay time Figure 2.105 Note: The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet1, and Vdet2 for the POR/ LVD. Note 1. The low power consumption function is disabled and DEEPCUT[1:0] = 00b or 01b. Note 2. The low power consumption function is enabled and DEEPCUT[1:0] = 11b. tVOFF VPOR VCC Internal reset signal (Low is valid) tdet Figure 2.102 tPOR tdet tdet tPOR Power-on Reset Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 161 of 179 RX72N Group 2. Electrical Characteristics tVOFF VCC Vdet0 Internal reset signal (Low is valid) tdet Figure 2.103 tdet tLVD0 Voltage Detection Circuit Timing (Vdet0) tVOFF VCC VLVH Vdet1 LVD1E Td(E-A) LVD1 Comparator output LVD1CMPE LVD1MON Internal reset signal (Low is valid) When LVD1RN = L tdet tdet tLVD1 When LVD1RN = H tLVD1 Figure 2.104 Voltage Detection Circuit Timing (Vdet1) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 162 of 179 RX72N Group 2. Electrical Characteristics tVOFF VCC VLVH Vdet2 LVD2E Td(E-A) LVD2 Comparator output LVD2CMPE LVD2MON Internal reset signal (Low is valid) When LVD2RN = L tdet tdet tLVD2 When LVD2RN = H tLVD2 Figure 2.105 Voltage Detection Circuit Timing (Vdet2) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 163 of 179 RX72N Group 2.10 2. Electrical Characteristics Oscillation Stop Detection Timing Table 2.59 Oscillation Stop Detection Circuit Characteristics Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr Item Detection time Symbol Min. Typ. Max. Unit tdr — — 1 ms Test Conditions Figure 2.106 Main clock or PLL clock tdr OSTDSR.OSTDF LOCO clock ICLK Figure 2.106 Oscillation Stop Detection Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 164 of 179 RX72N Group 2.11 2. Electrical Characteristics Battery Backup Function Characteristics Table 2.60 Battery Backup Function Characteristics Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, VBATT = 2.0 to 3.6 V, Ta = Topr Symbol Min. Typ. Max. Unit Test Conditions Voltage level for switching to battery backup VDETBATT 2.50 2.60 2.70 V Figure 2.107 Lower-limit VBATT voltage for power supply switching due to VCC voltage drop VBATTSW 2.70 — — VCC-off period for starting power supply switching tVOFFBATT 200 — — Item Note: µs The VCC-off period for starting power supply switching indicates the period in which VCC is below the minimum value of the voltage level for switching to battery backup (VDETBATT). tVOFFBATT VDETBATT VCC VBATT Backup power area VCC voltage guaranteed range VBATTSW VBATT Switching prohibited VCC supply VBATT voltage guaranteed range VBATT Switching prohibited VBATT supply VCC supply Note. The VBATT voltage when the supplied power source switches from VCC to VBATT should not be lower than VBATTSW, the lower-limit VBATT voltage for switching between power supplies due to a drop in the VCC voltage. Figure 2.107 Battery Backup Function Characteristics R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 165 of 179 RX72N Group 2.12 2. Electrical Characteristics Flash Memory Characteristics Table 2.61 Code Flash Memory Characteristics Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Temperature range for programming/erasure: Ta = Topr Item Programming time NPEC ≤ 100 times Programming time NPEC > 100 times Symbol FCLK = 4 MHz 20 MHz ≤ FCLK ≤ 60 MHz FCLK = 15 MHz Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit 128 bytes tP128 — 0.75 13.2 — 0.38 6.6 — 0.34 6 ms 8 Kbytes tP8K — 49 176 — 25 88 — 22 80 ms 32 Kbytes tP32K — 194 704 — 97 352 — 88 320 ms 128 bytes tP128 — 0.91 15.8 — 0.46 8 — 0.41 7.2 ms 8 Kbytes tP8K — 60 212 — 30 106 — 27 96 ms 32 Kbytes tP32K — 234 848 — 117 424 — 106 384 ms 8 Kbytes tE8K — 78 216 — 48 132 — 43 120 ms 32 Kbytes tE32K — 283 864 — 173 528 — 157 480 ms 8 Kbytes tE8K — 94 260 — 58 158 — 52 144 ms tE32K — 341 1040 — 208 632 — 189 576 ms Reprogramming/erasure cycle*1 NPEC 10000 *2 — — 10000 *2 — — 10000 *2 — — Times Suspend delay time during programming tSPD — — 264 — — 132 — — 120 µs First suspend delay time during erasing (in suspend priority mode) tSESD1 — — 216 — — 132 — — 120 µs Second suspend delay time during erasure (in suspend priority mode) tSESD2 — — 1.7 — — 1.7 — — 1.7 ms Suspend delay time during erasure (in erasure priority mode) tSEED — — 1.7 — — 1.7 — — 1.7 ms tFD — — 32 — — 22 — — 20 µs tDRP 10 — — 10 — — 10 — — Year Erasure time NPEC ≤ 100 times Erasure time NPEC > 100 times 32 Kbytes Forced stop command Data hold time*3 Note 1. Definition of reprogram/erase cycle: The program/erase cycle is the number of erasing for each block. When the number of program/erase cycles is n, each block can be erased n times. For instance, when 128-byte program is performed 64 times for different addresses in 8-Kbyte block and then the block is erased, the program/erase cycle is counted as one. However, the same address cannot be programmed more than once before the next erase cycle (overwriting is prohibited). Note 2. Characteristics are degraded as the number of program/erase increases. This is the minimum value of program/erase cycles to guarantee all characteristics listed in this table. Note 3. This shows the characteristics when the program/erase cycle does not exceed the specified value. R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 166 of 179 RX72N Group Table 2.62 2. Electrical Characteristics Data Flash Memory Characteristics Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Temperature range for programming/erasure: Ta = Topr Item Symbol FCLK = 4 MHz FCLK = 15 MHz 20 MHz ≤ FCLK ≤ 60 MHz Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Programming time 4 bytes tDP4 — 0.36 3.8 — 0.18 1.9 — 0.16 1.7 ms Erasure time 64 bytes tDP64 — 3.1 18 — 1.9 11 — 1.7 10 ms 128 bytes tDP128 — 4.7 27 — 2.9 16 — 2.6 15 ms Blank check time 256 bytes tDP256 — 8.9 50 — 5.4 31 — 4.9 28 ms 4 bytes tDBC4 — — 84 — — 33 — — 30 µs 64 bytes tDBC64 — — 280 — — 110 — — 100 µs 2 Kbytes tDBC2K — — 6160 — — 2420 — — 2200 µs Reprogramming/erasure cycle*1 NDPEC 100000 *2 — — 100000 *2 — — 100000 *2 — — Times Suspend delay time during programming tDSPD — — 264 — — 132 — — 120 µs First suspend delay time during erasure (in suspend priority mode) 64 bytes — — — 216 — — 132 — — 120 µs 128 bytes — — — 216 — — 132 — — 120 µs 256 bytes — — — 216 — — 132 — — 120 µs Second suspend delay time during erasure (in suspend priority mode) 64 bytes — — — 300 — — 300 — — 300 µs 128 bytes — — — 390 — — 390 — — 390 µs 256 bytes — — — 570 — — 570 — — 570 µs Suspend delay time during erasing (in suspend priority mode) 64 bytes — — — 300 — — 300 — — 300 µs 128 bytes — — — 390 — — 390 — — 390 µs 256 bytes — — — 570 — — 570 — — 570 µs tFD — — 32 — — 22 — — 20 µs tDDRP 10 — — 10 — — 10 — — Year Forced stop command Data hold time*3 Note 1. Definition of reprogram/erase cycle: The program/erase cycle is the number of erasing for each block. When the number of program/erase cycles is n, each block can be erased n times. For instance, when 4-byte program is performed 512 times for different addresses in 2-Kbyte block and then the block is erased, the program/erase cycle is counted as one. However, the same address cannot be programmed more than once before the next erase cycle (overwriting is prohibited). Note 2. Characteristics are degraded as the number of program/erase increases. This is the minimum value of program/erase cycles to guarantee all characteristics listed in this table. Note 3. This shows the characteristics when the program/erase cycle does not exceed the specified value. R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 167 of 179 RX72N Group 2. Electrical Characteristics • Suspension during programming FCU command Program Suspend tSPD FSTATR.FRDY Ready Programming pulse Not Ready Ready Programming • Suspension during erasure in suspend priority mode FCU command Erase Suspend Resume Suspend tSESD1 FSTATR.FRDY Ready Erasure pulse Not Ready tSESD2 Ready Erasing Not Ready Erasing • Suspension during erasure in erasure priority mode FCU command Erase Suspend tSEED FSTATR.FRDY Ready Erasure pulse Figure 2.108 Not Ready Ready Erasing Flash Memory Programming/Erasure Suspension Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 168 of 179 RX72N Group 2.13 2. Electrical Characteristics Boundary Scan Table 2.63 Boundary Scan Characteristics Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Item Symbol Min. Typ. Max. Unit Test Conditions Figure 2.109 tTCKcyc 100 — — ns TCK clock high pulse width tTCKH 45 — — ns TCK clock low pulse width tTCKL 45 — — ns TCK clock rise time tTCKr — — 5 ns TCK clock fall time tTCKf — — 5 ns TRST# pulse width tTRSTW 20 — — tTCKcyc Figure 2.110 Figure 2.111 TCK clock cycle time TMS setup time tTMSS 20 — — ns TMS hold time tTMSH 20 — — ns TDI setup time tTDIS 20 — — ns TDI hold time tTDIH 20 — — ns TDO data delay time tTDOD — — 40 ns tTCKcyc tTCKH TCK tTCKf tTCKL Figure 2.109 tTCKr Boundary Scan TCK Timing TCK RES# TRST# tTRSTW Figure 2.110 Boundary Scan TRST# Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 169 of 179 RX72N Group 2. Electrical Characteristics TCK tTMSS tTMSH tTDIS tTDIH TMS TDI tTDOD TDO Figure 2.111 Boundary Scan Input/Output Timing R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 170 of 179 RX72N Group Appendix 1. Package Dimensions Appendix 1. Package Dimensions Information on the latest version of the package dimensions or mountings has been displayed in “Packages” on Renesas Electronics Corporation website. JEITA Package Code RENESAS Code Previous Code MASS (Typ) [g] P-LFBGA224-13x13-0.80 PLBG0224GA-A 224FHE 0.4 Unit: mm E B A D INDEX AREA y1 S A S A1 y CZ e (ZE) e R P N Reference Dimensions in millimeters Symbol M Min Nom Max D 12.9 13.0 13.1 E 12.9 13.0 13.1 G A   1.40 F A1 0.30 0.35 0.40 E e  0.80  b 0.40 0.45 0.50 L K J H D (ZD) C B A 1 2 3 4 5 6 7 n x ݊b 8 9 10 11 12 13 14 15 x1 x2 S A S B x1   0.15 x2   0.08 y   0.10 y1   0.20 n  224  ZD  0.90  ZE  0.90  Figure A 224-Pin LFBGA (PLBG0224GA-A) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 171 of 179 RX72N Group Appendix 1. Package Dimensions Figure B 176-Pin LFBGA (PLBG0176GA-A) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 172 of 179 RX72N Group Appendix 1. Package Dimensions Figure C 176-Pin LFQFP (PLQP0176KB-C) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 173 of 179 RX72N Group Appendix 1. Package Dimensions JEITA Package Code P-TFLGA145-7x7-0.50 RENESAS Code PTLG0145KA-A Previous Code 145F0G MASS[Typ.] 0.1g w S B φb1 D φ φb φ w S A ZD A M S AB M S AB e A e N M L K J E H B G F E D C B x4 v Index mark (Laser mark) S ZE A y S 1 2 3 4 5 6 7 8 9 10 11 12 13 Reference Dimension in Millimeters Symbol Min D E v w A e b b1 x y ZD ZE Nom 7.0 7.0 Max 0.15 0.20 1.05 0.21 0.29 0.5 0.25 0.34 0.29 0.39 0.08 0.08 0.5 0.5 Figure D 145-Pin TFLGA (PTLG0145KA-A) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 174 of 179 RX72N Group Appendix 1. Package Dimensions Figure E 144-Pin LFQFP (PLQP0144KA-B) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 175 of 179 RX72N Group Appendix 1. Package Dimensions Figure F 100-Pin LFQFP (PLQP0100KB-B) R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 176 of 179 REVISION HISTORY RX72N Group REVISION HISTORY REVISION HISTORY RX72N Group Datasheet Classifications - Items with Technical Update document number: Changes according to the corresponding issued Technical Update - Items without Technical Update document number: Minor changes that do not require Technical Update to be issued Rev. Date 1.00 1.11 May 31, 2019 Feb 26, 2021 Description Page Summary — First edition, issued 1. Overview 15, 16 Table 1.3 List of Products, changed 62, 63, 65 Table 1.8 List of Pin and Pin Functions (145-Pin TFLGA), changed 70, 75 Table 1.9 List of Pin and Pin Functions (144-Pin LFQFP), changed 2. Electrical Characteristics 86, 87 Table 2.6 DC Characteristics (3), Note 3, changed 95 Table 2.18 HOCO Clock Timing, changed 102 Table 2.26 Bus Timing, Conditions 1, Conditions 2, changed 105 Figure 2.21 External Bus Timing/Normal Write Cycle (Bus Clock Synchronized), changed 106 Figure 2.23 External Bus Timing/Page Write Cycle (Bus Clock Synchronized), changed 115 Table 2.27 EXDMAC Timing, Conditions, changed 116 to 155 2.4.7 Timing of On-Chip Peripheral Modules, order of tables changed 119 Figure 2.41 MTU Clock Input Timing, changed 123 Figure 2.51 Output Disable Time of POEG in Response to the Oscillation Stop Detection, changed 127 Figure 2.56 Simple IIC Bus Interface Input/Output Timing, added 152 Table 2.48 GLCDC Timing, changed Classification TN-RX*-A0222A/E TN-RX*-A0222A/E TN-RX*-A0243A/E TN-RX*-A0243A/E TN-RX*-A0243A/E All trademarks and registered trademarks are the property of their respective owners. R01DS0343EJ0111 Rev.1.11 Feb 26, 2021 Page 177 of 179 General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-off state as described in your product documentation. 4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6. Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.). 7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a systemevaluation test for the given product. Notice 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your product or system. 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