R5F64185NFD

R32C/118 Group Datasheet R32C/118 Group RENESAS MCU REJ03B0255-0100 Rev.1.00 Nov 19, 2009 1. 1.1 Overview Features The M16C Family offers a robust platform of 32-/16-bit CISC microcomputers (MCUs) featuring high ROM code efficiency, extensive EMI/EMS noise immunity, ultra-low power consumption, high-speed processing in actual applications, and numerous and varied integrated peripherals. Extensive device scalability from low- to high-end, featuring a single architecture as well as compatible pin assignments and peripheral functions, provides support for a vast range of application fields. The R32C/100 Series is a high-end microcontroller series in the M16C Family. With a 4-Gbyte memory space, it achieves maximum code efficiency and high-speed processing with 32-bit CISC architecture, multiplier, multiply-accumulate unit, and floating point unit. The selection from the broadest choice of onchip peripheral devices — UART, CRC, DMAC, A/D and D/A converters, timers, I2C, and WDT enables to minimize external components. The R32C/100 Series, in particular, provides the R32C/118 Group as a standard product. This product, provided as a 100/144-pin plastic molded LQFP package, configures nine channels of serial interface, one channel of multi-master I2C-bus interface, and two channels of CAN module. 1.1.1 Applications Car audio, audio, printer, office/industrial equipment etc. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 1 of 122 R32C/118 Group 1. Overview 1.1.2 Performance Overview Table 1.1 to Table 1.4 show the performance overview of the R32C/118 Group. Table 1.1 Unit CPU R32C/118 Group Performance for the 144 pin-Package (1/2) Function Central processing unit Performance R32C/100 Series CPU Core • Basic instructions: 108 • Minimum instruction execution time: 20 ns (f(CPU) = 50 MHz) • Multiplier: 32-bit × 32-bit 64-bit • Multiply-accumulate unit: 32-bit × 32-bit + 64-bit 64-bit • IEEE-754 floating point standard: Single precision • 32-bit barrel shifter • Operating mode: Single-chip mode, memory expansion mode, microprocessor mode (optional (1)) Flash memory: 384 Kbytes to 1 Mbyte RAM: 40 K/48 K/63 Kbytes Data flash: 4 Kbytes × 2 blocks Refer to Table 1.5 for memory size of each product group Low voltage detector Clock generator Optional (1) Low voltage detection interrupt • 4 circuits (main clock, sub clock, PLL, on-chip oscillator) • Oscillation stop detector: Main clock oscillator stop/re-oscillation detection • Frequency divide circuit: Divide-by-2 to divide-by-24 selectable • Low power modes: Wait mode, stop mode • Address space: 4 Gbytes (of which up to 64 Mbytes is user accessible) • External bus Interface: Support for wait-state insertion, 4 chip select outputs • Bus format: Separate bus/Multiplexed bus selectable, data bus width selectable (8/16/32 bits) Interrupt vectors: 261 External interrupt inputs: NMI, INT × 9, key input × 4 Interrupt priority levels: 7 levels 15 bits × 1 (selectable input frequency from prescaler output) 4 channels • Cycle-steal transfer mode • Request sources: 57 • 2 transfer modes: Single transfer, repeat transfer • Can be activated by any peripheral interrupt source • 3 transfer functions: Immediate data transfer, calculation transfer, chained transfer • 2 input-only ports • 120 CMOS inputs/outputs • 32 ports are 5 V tolerant • A pull-up resistor is selectable for every 4 input ports (except 5 V tolerant inputs) DMAC Memory Voltage Detector Clock External Bus Expansion Bus and memory expansion Interrupts Watchdog Timer DMA DMAC II I/O Ports Programmable I/O ports Note: 1. Please contact a Renesas sales office to use the optional feature. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 2 of 122 R32C/118 Group 1. Overview Table 1.2 Unit Timer R32C/118 Group Performance for the 144-pin Package (2/2) Function Timer A Performance 16-bit timer × 5 Timer mode, event counter mode, one-shot timer mode, pulse-width modulation (PWM) mode Two-phase pulse signal processing in event counter mode (twophase encoder input) × 3 16-bit timer × 6 Timer mode, event counter mode, pulse frequency measurement mode, pulse-width measurement mode Three-phase motor control timer ×1 (timers A1, A2, A4, and B2 used) 8-bit programmable dead time timer Timer B Three-phase motor control timer Serial Interface UART0 to UART8 Asynchronous/synchronous serial interface × 9 channels • I2C-bus (UART0 to UART6) • Special mode 2 (UART0 to UART6) • IEBus (1) (optional (2)) (UART0 to UART6) 10-bit resolution × 34 channels Sample and hold functionality integrated 8-bit resolution × 2 CRC-CCITT (X16 + X12 + X5 + 1) 16 bits × 16 bits Time measurement (input capture): 16 bits × 16 Waveform generation (output compare): 16 bits × 24 Serial interface: Variable-length synchronous serial I/O mode, IEBus (1) mode (optional (2)) 1 channel 2 channels CAN functionality compliant with ISO11898-1 32 mailboxes Programming and erasure supply voltage: VCC = 3.0 to 5.5 V Minimum endurance: 1, 000 program/erase cycles Security protection: ROM code protect, ID code protect Debugging: On-chip debug, on-board flash programming 50 MHz/VCC = 3.0 to 5.5 V -20°C to 85°C (version N) -40°C to 85°C (version D) -40°C to 85°C (version P) 35 mA (VCC = 5.0 V, f(CPU) = 50 MHz) 8 µA (VCC = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode) 144-pin plastic molded LQFP (PLQP0144KA-A) A/D Converter D/A Converter CRC Calculator X-Y Converter Intelligent I/O Multi-master I2C-bus Interface CAN Module Flash Memory Operating Frequency/Supply Voltage Operating Temperature Current Consumption Package Notes: 1. IEBus is a trademark of NEC Electronics Corporation. 2. Please contact a Renesas sales office to use the optional feature. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 3 of 122 R32C/118 Group 1. Overview Table 1.3 Unit CPU R32C/118 Group Performance for the 100-pin Package (1/2) Function Central processing unit Performance R32C/100 Series CPU Core • Basic instructions: 108 • Minimum instruction execution time: 20 ns (f(CPU) = 50 MHz) • Multiplier: 32-bit × 32-bit 64-bit • Multiply-accumulate unit: 32-bit × 32-bit + 64-bit 64-bit • IEEE-754 floating point standard: Single precision • 32-bit barrel shifter • Operating mode: Single-chip mode, memory expansion mode, microprocessor mode (optional (1)) Flash memory: 384 Kbytes to 1 Mbyte RAM: 40 K/48 K/63 Kbytes Data flash: 4 Kbytes × 2 blocks Refer to Table 1.5 for memory size of each product group Low voltage detector Clock generator Optional (1) Low voltage detection interrupt • 4 circuits (main clock, sub clock, PLL, on-chip oscillator) • Oscillation stop detector: Main clock oscillator stop/re-oscillation detection • Frequency divide circuit: Divide-by-2 to divide-by-24 selectable • Low power modes: Wait mode, stop mode • Address space: 4 Gbytes (of which up to 64 Mbytes is user accessible) • External bus Interface: Support for wait-state insertion, 4 chip select outputs • Bus format: Separate bus/Multiplexed bus selectable, data bus width selectable (8/16 bits) Interrupt vectors: 261 External interrupt inputs: NMI, INT × 6, key input × 4 Interrupt priority levels: 7 levels 15 bits × 1 (selectable input frequency from prescaler output) 4 channels • Cycle-steal transfer mode • Request sources: 51 • 2 transfer modes: Single transfer, repeat transfer • Can be activated by any peripheral interrupt source • 3 transfer functions: Immediate data transfer, calculation transfer, chained transfer • 2 input-only ports • 84 CMOS inputs/outputs • 32 ports are 5 V tolerant • A pull-up resistor is selectable for every 4 input ports (except 5 V tolerant inputs) DMAC Memory Voltage Detector Clock External Bus Expansion Bus and memory expansion Interrupts Watchdog Timer DMA DMAC II I/O Ports Programmable I/O ports Note: 1. Please contact a Renesas sales office to use the optional feature. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 4 of 122 R32C/118 Group 1. Overview Table 1.4 Unit Timer R32C/118 Group Performance for the 100-pin Package (2/2) Function Timer A Performance 16-bit timer × 5 Timer mode, event counter mode, one-shot timer mode, pulse-width modulation (PWM) mode Two-phase pulse signal processing in event counter mode (twophase encoder input) × 3 16-bit timer × 6 Timer mode, event counter mode, pulse frequency measurement mode, pulse-width measurement mode Three-phase motor control timer ×1 (timers A1, A2, A4, and B2 used) 8-bit programmable dead time timer Timer B Three-phase motor control timer Serial Interface UART0 to UART8 Asynchronous/synchronous serial interface × 9 channels • I2C-bus (UART0 to UART6) • Special mode 2 (UART0 to UART6) • IEBus (1) (optional (2)) (UART0 to UART6) 10-bit resolution × 26 channels Sample and hold functionality integrated 8-bit resolution × 2 CRC-CCITT (X16 + X12 + X5 + 1) 16 bits × 16 bits Time measurement (input capture): 16 bits × 16 Waveform generation (output compare): 16 bits × 19 Serial interface: Variable-length synchronous serial I/O mode, IEBus (1) mode (optional (2)) 1 channel 2 channels CAN functionality compliant with ISO11898-1 32 mailboxes Programming and erasure supply voltage: VCC = 3.0 to 5.5 V Minimum endurance: 1, 000 program/erase cycles Security protection: ROM code protect, ID code protect Debugging: On-chip debug, on-board flash programming 50 MHz/VCC = 3.0 to 5.5 V -20°C to 85°C (version N) -40°C to 85°C (version D) -40°C to 85°C (version P) 35 mA (VCC = 5.0 V, f(CPU) = 50 MHz) 8 µA (VCC = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode) 100-pin plastic molded LQFP (PLQP0100KB-A) A/D Converter D/A Converter CRC Calculator X-Y Converter Intelligent I/O Multi-master I2C-bus Interface CAN Module Flash Memory Operating Frequency/Supply Voltage Operating Temperature Current Consumption Package Notes: 1. IEBus is a trademark of NEC Electronics Corporation. 2. Please contact a Renesas sales office to use the optional feature. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 5 of 122 R32C/118 Group 1. Overview 1.2 Product Information Table 1.5 lists the product information and Figure 1.1 shows the details of the part number. Table 1.5 R5F64185NFD R5F64185DFD R5F64185PFD R5F64185NFB R5F64185DFB R5F64185PFB R5F64186NFD R5F64186DFD R5F64186PFD R5F64186NFB R5F64186DFB R5F64186PFB R5F64187NFD R5F64187DFD R5F64187PFD R5F64187NFB R5F64187DFB R5F64187PFB R5F64188NFD R5F64188DFD R5F64188PFD R5F64188NFB R5F64188DFB R5F64188PFB R5F64189NFD R5F64189DFD R5F64189PFD R5F64189NFB R5F64189DFB R5F64189PFB (P): On planning phase (P) PLQP0100KB-A (P) PLQP0144KA-A 1 Mbyte + 8 Kbytes (P) PLQP0100KB-A 63 Kbytes (P) PLQP0144KA-A 768 Kbytes + 8 Kbytes (P) PLQP0100KB-A (P) PLQP0144KA-A 640 Kbytes + 8 Kbytes 48Kbytes (P) PLQP0100KB-A (P) PLQP0144KA-A 512 Kbytes + 8 Kbytes (P) PLQP0100KB-A 40 Kbytes R32C/118 Group Product List Package Code (1) ROM Capacity (2) RAM Capacity (P) PLQP0144KA-A 384 Kbytes + 8 Kbytes As of November, 2009 Remarks -20°C to 85°C (version N) -40°C to 85°C (version D) -40°C to 85°C (version P) -20°C to 85°C (version N) -40°C to 85°C (version D) -40°C to 85°C (version P) -20°C to 85°C (version N) -40°C to 85°C (version D) -40°C to 85°C (version P) -20°C to 85°C (version N) -40°C to 85°C (version D) -40°C to 85°C (version P) -20°C to 85°C (version N) -40°C to 85°C (version D) -40°C to 85°C (version P) -20°C to 85°C (version N) -40°C to 85°C (version D) -40°C to 85°C (version P) -20°C to 85°C (version N) -40°C to 85°C (version D) -40°C to 85°C (version P) -20°C to 85°C (version N) -40°C to 85°C (version D) -40°C to 85°C (version P) -20°C to 85°C (version N) -40°C to 85°C (version D) -40°C to 85°C (version P) -20°C to 85°C (version N) -40°C to 85°C (version D) -40°C to 85°C (version P) Part Number Notes: 1. The old package codes are as follows:PLQP0100KB-A: 100P6Q-A, PLQP0144KA-A: 144P6Q-A 2. Data flash memory provides an additional 8 Kbytes of ROM capacity. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 6 of 122 R32C/118 Group 1. Overview Part Number R5 F 64 18 9 P XXX FD Package Code FB : PLQP0100KB-A FD : PLQP0144KA-A ROM Number Omitted in the flash memory version Temperature Code N : -20°C to 85°C D : -40°C to 85°C P : -40°C to 85°C ROM/RAM Capacity 5 : 384 KB/40 KB 6 : 512 KB/40 KB 7 : 640 KB/48 KB 8 : 768 KB/63 KB 9 : 1 MB/63 KB R32C/118 Group R32C/100 Series Memory Type F : Flash memory version Figure 1.1 Part Numbering REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 7 of 122 R32C/118 Group 1. Overview 1.3 Block Diagram Figure 1.2 shows a block diagram of the R32C/118 Group. 8 8 8 8 8 8 8 Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Peripheral functions Timer: Timer A Timer B 16 bits × 5 timers 16 bits × 6 timers A/D converter: 10 bits × 1 circuit Standard: 10 inputs Maximum: 34 inputs (1) Clock generator: 4 circuits - XIN-XOUT - XCIN-XCOUT - On-chip oscillator - PLL frequency synthesizer Port P7 8 Three-phase motor controller Serial interface: 9 channels Port P8 D/A converter: 8 bits × 2 channels Watchdog timer: 15 bits 7 X-Y converter: 16 bits × 16 bits Multi-master I2C-bus interface: 1 channel DMAC DMAC II Memory ROM RAM P8_5 CRC calculator (CCITT) X16 + X12 + X5 + 1 Port P9 Intelligent I/O Time Measurement: 16 Wave generation: 24 (2) Serial interface: - Variable-length synchronous serial I/O - IEBus (4) R32C/100 Series CPU Core R2R0 R2R0 R3R1 R3R1 R6R4 R6R4 R7R5 R7R5 A0 A0 A1 A1 A2 A2 A3 A3 FB FB SB SB FLG INTB ISP USP PC SVF SVP VCT 8 (3) Port P10 CAN module: 2 channels Multiplier Floating-point unit 8 Port P15 Port P14 Port P14_1 Port P13 Port P12 Port P11 8 4 (Note 5) 8 8 5 Notes: 1. 34 inputs are available in the 144-pin package. In the 100-pin package, up to 26 inputs are provided. 2. 24 outputs are available in the 144-pin package. In the 100-pin package, 19 outputs are provided. 3. Eight ports are available in the 144-pin package. In the 100-pin package, five I/O ports and one inputonly port (P9_1) are provided. 4. IEBus is a trademark of NEC Electronics Corporation. 5. Ports P11 to P15 are available in the 144-pin package only. Figure 1.2 R32C/118 Group Block Diagram REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 8 of 122 R32C/118 Group 1. Overview 1.4 Pin Assignments Figure 1.3 and Figure 1.4 show the pin assignments (top view) and Table 1.6 to Table 1.12 show the pin characteristics. 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 IIO0_0 / IIO1_0 / D8 / P1_0 AN0_7 / D7 / P0_7 AN0_6 / D6 / P0_6 AN0_5 / D5 / P0_5 AN0_4 / D4 / P0_4 WR3 / BC3 / P11_4 IIO1_3 / RTS8 / CTS8 / WR2 / CS3 / P11_3 IIO1_2 / RXD8 / CS2 / P11_2 IIO1_1 / CLK8 / CS1 / P11_1 IIO1_0 / TXD8 / CS0 / P11_0 AN0_3 / D3 / P0_3 AN0_2 / D2 / P0_2 AN0_1 / D1 / P0_1 AN0_0 / D0 / P0_0 IIO0_7 / RTS6 / CTS6 / SS6 / AN15_7 / P15_7 IIO0_6 / CLK6 / AN15_6 / P15_6 IIO0_5 / RXD6 / SCL6 / STXD6 / AN15_5 / P15_5 IIO0_4 / TXD6 / SDA6 / SRXD6 / AN15_4 / P15_4 IIO0_3 / RTS7 / CTS7 / AN15_3 / P15_3 IIO0_2 / RXD7 / AN15_2 / P15_2 IIO0_1 / CLK7 / AN15_1 / P15_1 VSS IIO0_0 / TXD7 / AN15_0 / P15_0 VCC KI3 / AN_7 / P10_7 KI2 / AN_6 / P10_6 KI1 / AN_5 / P10_5 KI0 / AN_4 / P10_4 AN_3 / P10_3 AN_2 / P10_2 AN_1 / P10_1 AVSS AN_0 / P10_0 VREF AVCC STXD4 / SCL4 / RXD4 / ADTRG / P9_7 73 P1_1 / D9 / IIO0_1 / IIO1_1 P1_2 / D10 / IIO0_2 / IIO1_2 P1_3 / D11 / IIO0_3 / IIO1_3 P1_4 / D12 / IIO0_4 / IIO1_4 P1_5 / D13 / INT3 / IIO0_5 / IIO1_5 P1_6 / D14 / INT4 / IIO0_6 / IIO1_6 P1_7 / D15 / INT5 / IIO0_7 / IIO1_7 P2_0 / A0 / [A0/D0] / BC0 / [BC0/D0] / AN2_0 P2_1 / A1 / [A1/D1] / BC2 / [BC2/D1] / AN2_1 P2_2 / A2 / [A2/D2] / AN2_2 P2_3 / A3 / [A3/D3] / AN2_3 P2_4 / A4 / [A4/D4] / AN2_4 P2_5 / A5 / [A5/D5] / AN2_5 P2_6 / A6 / [A6/D6] / AN2_6 P2_7 / A7 / [A7/D7] / AN2_7 VSS P3_0 / A8 / [A8/D8] / TA0OUT / UD0A / UD1A VCC P12_0 / D16 / TXD6 / SDA6 / SRXD6 P12_1 / D17 / CLK6 P12_2 / D18 / RXD6 / SCL6 / STXD6 P12_3 / D19 / CTS6 / RTS6 / SS6 P12_4 / D20 P3_1 / A9 / [A9/D9] / TA3OUT / UD0B / UD1B P3_2 / A10 / [A10/D10] / TA1OUT / V P3_3 / A11 / [A11/D11] / TA1IN / V P3_4 / A12 / [A12/D12] / TA2OUT / W P3_5 / A13 / [A13/D13] / TA2IN / W P3_6 / A14 / [A14/D14] / TA4OUT / U P3_7 / A15 / [A15/D15] / TA4IN / U P4_0 / A16 / CTS3 / RTS3 / SS3 P4_1 / A17 / CLK3 VSS P4_2 / A18 / RXD3 / SCL3 / STXD3 / ISRXD2 / IEIN VCC P4_3 / A19 / TXD3 / SDA3 / SRXD3 / OUTC2_0 / ISTXD2 / IEOUT (Note 1) 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72 71 70 69 68 67 66 65 64 63 62 61 60 R32C/118 GROUP PLQP0144KA-A (144P6Q-A) (Top view) 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 P4_4 / CS3 / A20 / CTS6 / RTS6 / SS6 P4_5 / CS2 / A21 / CLK6 P4_6 / CS1 / A22 / RXD6 / SCL6 / STXD6 P4_7 / CS0 / A23 / TXD6 / SDA6 / SRXD6 P12_5 / D21 P12_6 / D22 P12_7 / D23 P5_0 / WR0 / WR P5_1 / WR1 / BC1 P5_2 / RD P5_3 / CLKOUT / BCLK P13_0 / D24 / OUTC2_4 P13_1 / D25 / OUTC2_5 VCC P13_2 / D26 / OUTC2_6 (Note 2) VSS P13_3 / D27 / OUTC2_3 P5_4 / HLDA / CS1 / TXD7 P5_5 / HOLD / CLK7 P5_6 / ALE / CS2 / RXD7 P5_7 / RDY / CS3 / CTS7 / RTS7 P13_4 / D28 / OUTC2_0 / ISTXD2 / IEOUT P13_5 / D29 / OUTC2_2 / ISRXD2 / IEIN P13_6 / D30 / OUTC2_1 / ISCLK2 P13_7 / D31 / OUTC2_7 P6_0 / TB0IN / CTS0 / RTS0 / SS0 P6_1 / TB1IN / CLK0 P6_2 / TB2IN / RXD0 / SCL0 / STXD0 P6_3 / TXD0 / SDA0 / SRXD0 P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2 P6_5 / CLK1 VSS P6_6 / RXD1 / SCL1 / STXD1 VCC P6_7 / TXD1 / SDA1 / SRXD1 P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT / MSDA (Note 3) 1 2 3 4 5 6 7 8 Notes: 1. Pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins. 2. The following pins are 5 V tolerant inputs: P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7, P7_0 to P7_7, and P8_0 to P8_3 3. The position of pin number 1 varies by product. Refer to the index mark in attached “Package Dimensions”. Figure 1.3 Pin Assignment for the 144-pin Package (top view) REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 9 of 122 CAN1OUT / SRXD4 / SDA4 / TXD4 / ANEX1 / P9_6 CAN1IN / CAN1WU / CLK4 / ANEX0 / P9_5 SS4 / RTS4 / CTS4 / TB4IN / DA1 / P9_4 SS3 / RTS3 / CTS3 / TB3IN / DA0 / P9_3 IEOUT / ISTXD2 / OUTC2_0 / SRXD3 / SDA3 / TXD3 / TB2IN / P9_2 IEIN / ISRXD2 / STXD3 / SCL3 / RXD3 / TB1IN / P9_1 CLK3 / TB0IN / P9_0 INT8 / P14_6 INT7 / P14_5 INT6 / P14_4 P14_3 VDC0 P14_1 VDC1 NSD CNVSS XCIN / P8_7 XCOUT / P8_6 RESET XOUT VSS XIN VCC NMI / P8_5 INT2 / P8_4 CAN0IN / CAN0WU / CAN1IN / CAN1WU / INT1 / P8_3 CAN0OUT / CAN1OUT / INT0 / P8_2 UD0B / UD1B / IIO1_5 / RTS5 / CTS5 / SS5 / U / TA4IN / P8_1 UD0A / UD1A / RXD5 / SCL5 / STXD5 / U / TA4OUT / P8_0 CAN0IN / CAN0WU / UD0B / UD1B / IIO1_4 / CLK5 / TA3IN / P7_7 CAN0OUT / UD0A / UD1A / IIO1_3 / RTS8 / CTS8 / TXD5 / SDA5 / SRXD5 / TA3OUT / P7_6 IIO1_2 / RXD8 / W / TA2IN / P7_5 IIO1_1 / CLK8 / W / TA2OUT / P7_4 IIO1_0 / TXD8 / SS2 / RTS2 / CTS2 / V / TA1IN / P7_3 CLK2 / V / TA1OUT / P7_2 MSCL / IEIN / ISRXD2 / OUTC2_2 / IIO1_7 / STXD2 / SCL2 / RXD2 / TA0IN / TB5IN / P7_1 9 R32C/118 Group 1. Overview Table 1.6 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VDC1 NSD CNVSS XCIN RESET XOUT VDC0 Control Pin Pin Characteristics for the 144-pin Package (1/4) Port P9_6 P9_5 P9_4 P9_3 P9_2 P9_1 P9_0 P14_6 INT8 P14_5 INT7 P14_4 INT6 P14_3 TB4IN TB3IN TB2IN TB1IN TB0IN Interrupt Pin Timer Pin UART/CAN Module Pin TXD4/SDA4/SRXD4/ CAN1OUT CLK4/CAN1IN/ CAN1WU CTS4/RTS4/SS4 CTS3/RTS3/SS3 TXD3/SDA3/SRXD3 RXD3/SCL3/STXD3 CLK3 OUTC2_0/ISTXD2/ IEOUT ISRXD2/IEIN Intelligent I/O Pin Analog Pin ANEX1 ANEX0 DA1 DA0 Bus Control Pin P14_1 P8_7 XCOUT P8_6 VSS XIN VCC P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 NMI INT2 INT1 INT0 TA4IN/U CAN0IN/CAN0WU/ CAN1IN/CAN1WU CAN0OUT/CAN1OUT CTS5/RTS5/SS5 IIO1_5/UD0B/UD1B UD0A/UD1A IIO1_4/UD0B/UD1B TA4OUT/U RXD5/SCL5/STXD5 TA3IN TA3OUT TA2IN/W TA1IN/V TB5IN/ TA0IN CLK5/CAN0IN/ CAN0WU TXD5/SDA5/SRXD5/ IIO1_3/UD0A/UD1A CTS8/RTS8/CAN0OUT RXD8 IIO1_2 IIO1_1 TA2OUT/W CLK8 TA1OUT/V CLK2 RXD2/SCL2/STXD2/ MSCL CTS2/RTS2/SS2/TXD8 IIO1_0 IIO1_7/OUTC2_2/ ISRXD2/IEIN REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 10 of 122 R32C/118 Group 1. Overview Table 1.7 Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 VCC VCC VSS VSS VCC Control Pin Pin Characteristics for the 144-pin Package (2/4) Port P7_0 P6_7 Interrupt Pin Timer Pin TA0OUT UART/CAN Module Pin TXD2/SDA2/SRXD2/ MSDA TXD1/SDA1/SRXD1 Intelligent I/O Pin IIO1_6/OUTC2_0/ ISTXD2/IEOUT Analog Pin Bus Control Pin P6_6 P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 P13_7 P13_6 P13_5 P13_4 P5_7 P5_6 P5_5 P5_4 P13_3 P13_2 P13_1 P13_0 P5_3 P5_2 P5_1 P5_0 P12_7 P12_6 P12_5 P4_7 P4_6 P4_5 P4_4 P4_3 TB2IN TB1IN TB0IN RXD1/SCL1/STXD1 CLK1 CTS1/RTS1/SS1 TXD0/SDA0/SRXD0 RXD0/SCL0/STXD0 CLK0 CTS0/RTS0/SS0 OUTC2_7 OUTC2_1/ISCLK2 OUTC2_2/ISRXD2/ IEIN OUTC2_0/ISTXD2/ IEOUT CTS7/RTS7 RXD7 CLK7 TXD7 OUTC2_3 OUTC2_6 OUTC2_5 OUTC2_4 D31 D30 D29 D28 RDY/CS3 ALE/CS2 HOLD HLDA/CS1 D27 D26 D25 D24 CLKOUT/ BCLK RD WR1/BC1 WR0/WR D23 D22 D21 TXD6/SDA6/SRXD6 RXD6/SCL6/STXD6 CLK6 CTS6/RTS6/SS6 TXD3/SDA3/SRXD3 OUTC2_0/ISTXD2/ IEOUT CS0/A23 CS1/A22 CS2/A21 CS3/A20 A19 OUTC2_1/ISCLK2 REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 11 of 122 R32C/118 Group 1. Overview Table 1.8 Pin No. 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 VSS VCC VSS Control Pin Pin Characteristics for the 144-pin Package (3/4) Port P4_2 P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 P12_4 P12_3 P12_2 P12_1 P12_0 P3_0 P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P11_4 INT5 INT4 INT3 IIO0_7/IIO1_7 IIO0_6/IIO1_6 IIO0_5/IIO1_5 IIO0_4/IIO1_4 IIO0_3/IIO1_3 IIO0_2/IIO1_2 IIO0_1/IIO1_1 IIO0_0/IIO1_0 AN0_7 AN0_6 AN0_5 AN0_4 TA0OUT CTS6/RTS6/SS6 RXD6/SCL6/STXD6 CLK6 TXD6/SDA6/SRXD6 UD0A/UD1A AN2_7 AN2_6 AN2_5 AN2_4 AN2_3 AN2_2 AN2_1 AN2_0 TA4IN/U TA4OUT/U TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V TA3OUT UD0B/UD1B Interrupt Pin Timer Pin UART/CAN Module Pin RXD3/SCL3/STXD3 CLK3 CTS3/RTS3/SS3 Intelligent I/O Pin ISRXD2/IEIN Analog Pin Bus Control Pin A18 A17 A16 A15(/D15) A14(/D14) A13(/D13) A12(/D12) A11(/D11) A10(/D10) A9(/D9) D20 D19 D18 D17 D16 A8(/D8) A7(/D7) A6(/D6) A5(/D5) A4(/D4) A3(/D3) A2(/D2) A1(/D1)/ BC2(/D1) A0(/D0)/ BC0(/D0) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 BC3/WR3 REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 12 of 122 R32C/118 Group 1. Overview Table 1.9 Pin No. 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 VREF AVCC AVSS VCC VSS Control Pin Pin Characteristics for the 144-pin Package (4/4) Port P11_3 P11_2 P11_1 P11_0 P0_3 P0_2 P0_1 P0_0 P15_7 P15_6 P15_5 P15_4 P15_3 P15_2 P15_1 P15_0 P10_7 KI3 P10_6 KI2 P10_5 KI1 P10_4 KI0 P10_3 P10_2 P10_1 P10_0 CTS6/RTS6/SS6 CLK6 RXD6/SCL6/STXD6 TXD6/SDA6/SRXD6 CTS7/RTS7 RXD7 CLK7 TXD7 IIO0_7 IIO0_6 IIO0_5 IIO0_4 IIO0_3 IIO0_2 IIO0_1 IIO0_0 Interrupt Pin Timer Pin UART/CAN Module Pin CTS8/RTS8 RXD8 CLK8 TXD8 Intelligent I/O Pin IIO1_3 IIO1_2 IIO1_1 IIO1_0 AN0_3 AN0_2 AN0_1 AN0_0 AN15_7 AN15_6 AN15_5 AN15_4 AN15_3 AN15_2 AN15_1 AN15_0 AN_7 AN_6 AN_5 AN_4 AN_3 AN_2 AN_1 AN_0 Analog Pin Bus Control Pin CS3/WR2 CS2 CS1 CS0 D3 D2 D1 D0 P9_7 RXD4/SCL4/STXD4 ADTRG REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 13 of 122 R32C/118 Group 1. Overview (Note 1) P1_3 / D11 / IIO0_3 / IIO1_3 P1_4 / D12 / IIO0_4 / IIO1_4 P1_5 / D13 / INT3 / IIO0_5 / IIO1_5 P1_6 / D14 / INT4 / IIO0_6 / IIO1_6 P1_7 / D15 / INT5 / IIO0_7 / IIO1_7 P2_0 / A0 / [A0/D0] / BC0 / [BC0/D0] / AN2_0 P2_1 / A1 / [A1/D1] / AN2_1 P2_2 / A2 / [A2/D2] / AN2_2 P2_3 / A3 / [A3/D3] / AN2_3 P2_4 / A4 / [A4/D4] / AN2_4 P2_5 / A5 / [A5/D5] / AN2_5 P2_6 / A6 / [A6/D6] / AN2_6 P2_7 / A7 / [A7/D7] / AN2_7 VSS P3_0 / A8 / [A8/D8] / TA0OUT / UD0A / UD1A VCC P3_1 / A9 / [A9/D9] / TA3OUT / UD0B / UD1B P3_2 / A10 / [A10/D10] / TA1OUT / V P3_3 / A11 / [A11/D11] / TA1IN / V P3_4 / A12 / [A12/D12] / TA2OUT / W P3_5 / A13 / [A13/D13] / TA2IN / W P3_6 / A14 / [A14/D14] / TA4OUT / U P3_7 / A15 / [A15/D15] / TA4IN / U P4_0 / A16 / CTS3 / RTS3 / SS3 P4_1 / A17 / CLK3 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 IIO0_2 / IIO1_2 / D10 / P1_2 IIO0_1 / IIO1_1 / D9 / P1_1 IIO0_0 / IIO1_0 / D8 / P1_0 AN0_7 / D7 / P0_7 AN0_6 / D6 / P0_6 AN0_5 / D5 / P0_5 AN0_4 / D4 / P0_4 AN0_3 / D3 / P0_3 AN0_2 / D2 / P0_2 AN0_1 / D1 / P0_1 AN0_0 / D0 / P0_0 KI3 / AN_7 / P10_7 KI2 / AN_6 / P10_6 KI1 / AN_5 / P10_5 KI0 / AN_4 / P10_4 AN_3 / P10_3 AN_2 / P10_2 AN_1 / P10_1 AVSS AN_0 / P10_0 VREF AVCC STXD4 / SCL4 / RXD4 / ADTRG / P9_7 CAN1OUT / SRXD4 / SDA4 / TXD4 / ANEX1 / P9_6 CAN1IN / CAN1WU / CLK4 / ANEX0 / P9_5 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 R32C/118 GROUP PLQP0100KB-A (100P6Q-A) (Top view) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P4_2 / A18 / RXD3 / SCL3 / STXD3 / ISRXD2 / IEIN P4_3 / A19 / TXD3 / SDA3 / SRXD3 / OUTC2_0 / ISTXD2 / IEOUT P4_4 / CS3 / A20 / CTS6 / RTS6 / SS6 P4_5 / CS2 / A21 / CLK6 P4_6 / CS1 / A22 / RXD6 / SCL6 / STXD6 P4_7 / CS0 / A23 / TXD6 / SDA6 / SRXD6 P5_0 / WR0 / WR P5_1 / WR1 / BC1 P5_2 / RD P5_3 / CLKOUT / BCLK (Note 2) P5_4 / HLDA / CS1 / TXD7 P5_5 / HOLD / CLK7 P5_6 / ALE / CS2 / RXD7 P5_7 / RDY / CS3 / CTS7 / RTS7 P6_0 / TB0IN / CTS0 / RTS0 / SS0 P6_1 / TB1IN / CLK0 P6_2 / TB2IN / RXD0 / SCL0 / STXD0 P6_3 / TXD0 / SDA0 / SRXD0 P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2 P6_5 / CLK1 P6_6 / RXD1 / SCL1 / STXD1 P6_7 / TXD1 / SDA1 / SRXD1 P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT / MSDA P7_1 / TB5IN / TA0IN / RXD2 / SCL2 / STXD2 / IIO1_7 / OUTC2_2 / ISRXD2 / IEIN / MSCL P7_2 / TA1OUT / V / CLK2 (Note 3) 1 2 3 4 5 6 7 8 Notes: 1. Pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins. 2. The following pins are 5 V tolerant inputs: P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7, P7_0 to P7_7, and P8_0 to P8_3 3. The position of pin number 1 varies by product. Refer to the index mark in attached “Package Dimensions”. Figure 1.4 Pin Assignment for the 100-pin Package (top view) REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 14 of 122 SS4 / RTS4 / CTS4 / TB4IN / DA1 / P9_4 TB3IN / DA0 / P9_3 VDC0 P9_1 VDC1 NSD CNVSS XCIN / P8_7 XCOUT / P8_6 RESET XOUT VSS XIN VCC NMI / P8_5 INT2 / P8_4 CAN0IN / CAN0WU / CAN1IN / CAN1WU / INT1 / P8_3 CAN0OUT / CAN1OUT / INT0 / P8_2 UD0B / UD1B / IIO1_5 / RTS5 / CTS5 / SS5 / U / TA4IN / P8_1 UD0A / UD1A / RXD5 / SCL5 / STXD5 / U / TA4OUT / P8_0 CAN0IN / CAN0WU / UD0B / UD1B / IIO1_4 / CLK5 / TA3IN / P7_7 CAN0OUT / UD0A / UD1A / IIO1_3 / RTS8 / CTS8 / TXD5 / SDA5 / SRXD5 / TA3OUT / P7_6 IIO1_2 / RXD8 / W / TA2IN / P7_5 IIO1_1 / CLK8 / W / TA2OUT / P7_4 IIO1_0 / TXD8 / SS2 / RTS2 / CTS2 / V / TA1IN / P7_3 9 R32C/118 Group 1. Overview Table 1.10 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 VDC1 NSD CNVSS XCIN RESET XOUT VSS XIN VCC VDC0 Control Pin Pin Characteristics for the 100-pin Package (1/3) Port P9_4 P9_3 P9_1 Interrupt Pin Timer Pin TB4IN TB3IN UART/CAN Module Pin CTS4/RTS4/SS4 Intelligent I/O Pin Analog Pin DA1 DA0 Bus Control Pin P8_7 XCOUT P8_6 P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7 P6_6 P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 P5_7 P5_6 NMI INT2 INT1 INT0 TA4IN/U TA3IN TA3OUT TA2IN/W TA1IN/V TB5IN/ TA0IN TA0OUT CAN0IN/CAN0WU/ CAN1IN/CAN1WU CAN0OUT/CAN1OUT CTS5/RTS5/SS5 CLK5/CAN0IN/ CAN0WU IIO1_5/UD0B/UD1B UD0A/UD1A IIO1_4/UD0B/UD1B TA4OUT/U RXD5/SCL5/STXD5 TXD5/SDA5/SRXD5/ IIO1_3/UD0A/UD1A CTS8/RTS8/CAN0OUT RXD8 IIO1_2 IIO1_1 TA2OUT/W CLK8 TA1OUT/V CLK2 RXD2/SCL2/STXD2/ MSCL TXD2/SDA2/SRXD2/ MSDA TXD1/SDA1/SRXD1 RXD1/SCL1/STXD1 CLK1 CTS1/RTS1/SS1 TXD0/SDA0/SRXD0 TB2IN TB1IN TB0IN RXD0/SCL0/STXD0 CLK0 CTS0/RTS0/SS0 CTS7/RTS7 RXD7 CTS2/RTS2/SS2/TXD8 IIO1_0 IIO1_7/OUTC2_2/ ISRXD2/IEIN IIO1_6/OUTC2_0/ ISTXD2/IEOUT OUTC2_1/ISCLK2 RDY/CS3 ALE/CS2 REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 15 of 122 R32C/118 Group 1. Overview Table 1.11 Pin No. 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 VSS VCC Control Pin Pin Characteristics for the 100-pin Package (2/3) Port P5_5 P5_4 P5_3 P5_2 P5_1 P5_0 P4_7 P4_6 P4_5 P4_4 P4_3 P4_2 P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 P3_0 P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 INT5 INT4 INT3 IIO0_7/IIO1_7 IIO0_6/IIO1_6 IIO0_5/IIO1_5 IIO0_4/IIO1_4 IIO0_3/IIO1_3 TA4IN/U TA4OUT/U TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V TA3OUT TA0OUT UD0B/UD1B UD0A/UD1A AN2_7 AN2_6 AN2_5 AN2_4 AN2_3 AN2_2 AN2_1 AN2_0 TXD6/SDA6/SRXD6 RXD6/SCL6/STXD6 CLK6 CTS6/RTS6/SS6 TXD3/SDA3/SRXD3 RXD3/SCL3/STXD3 CLK3 CTS3/RTS3/SS3 OUTC2_0/ISTXD2/ IEOUT ISRXD2/IEIN Interrupt Pin Timer Pin UART/CAN Module Pin CLK7 TXD7 Intelligent I/O Pin Analog Pin Bus Control Pin HOLD HLDA/CS1 CLKOUT/ BCLK RD WR1/BC1 WR0/WR CS0/A23 CS1/A22 CS2/A21 CS3/A20 A19 A18 A17 A16 A15(/D15) A14(/D14) A13(/D13) A12(/D12) A11(/D11) A10(/D10) A9(/D9) A8(/D8) A7(/D7) A6(/D6) A5(/D5) A4(/D4) A3(/D3) A2(/D2) A1(/D1) A0(/D0)/ BC0(/D0) D15 D14 D13 D12 D11 REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 16 of 122 R32C/118 Group 1. Overview Table 1.12 Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VREF AVCC AVSS Control Pin Pin Characteristics for the 100-pin Package (3/3) Port P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 P10_7 KI3 P10_6 KI2 P10_5 KI1 P10_4 KI0 P10_3 P10_2 P10_1 P10_0 Interrupt Pin Timer Pin UART/CAN Module Pin Intelligent I/O Pin IIO0_2/IIO1_2 IIO0_1/IIO1_1 IIO0_0/IIO1_0 AN0_7 AN0_6 AN0_5 AN0_4 AN0_3 AN0_2 AN0_1 AN0_0 AN_7 AN_6 AN_5 AN_4 AN_3 AN_2 AN_1 AN_0 Analog Pin Bus Control Pin D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P9_7 P9_6 P9_5 RXD4/SCL4/STXD4 TXD4/SDA4/SRXD4/ CAN1OUT CLK4/CAN1IN/ CAN1WU ADTRG ANEX1 ANEX0 REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 17 of 122 R32C/118 Group 1. Overview 1.5 Pin Definitions and Functions Table 1.13 to Table 1.17 show the pin definitions and functions. Table 1.13 Pin Definitions and Functions (1/4) Function Power supply Connecting pins for decoupling capacitor Analog power supply Reset input CNVSS Debug port Main clock input Symbol VCC, VSS VDC0, VDC1 I/O I — Description Applicable as follows: VCC = 3.0 to 5.5 V, VSS = 0 V A decoupling capacitor for internal voltage should be connected between VDC0 and VDC1 Power supply for the A/D converter. AVCC and AVSS should be connected to VCC and VSS, respectively The MCU is reset when this pin is driven low This pin should be connected to VSS via a resistor This pin is to communicate with a debugger. It should be connected to VCC via a resistor of 1 to 4.7 kΩ Input/output for the main clock oscillator. A crystal, or a ceramic resonator should be connected between pins XIN and XOUT. An external clock should be input at the XIN while leaving the XOUT open Input/output for the sub clock oscillator. A crystal oscillator should be connected between pins XCIN and XCOUT. An external clock should be input at the XCIN while leaving the XCOUT open BCLK output Output of the clock with the same frequency as fC, f8, or f32 Input for external interrupts Input for NMI Input for the key input interrupt Input/output of data (D0 to D7) while accessing an external memory space with a separate bus Input/output of data (D8 to D15) while accessing an external memory space with 16-bit or 32-bit separate bus Input/output of data (D16 to D31) while accessing an external memory space with 32-bit separate bus Output of address bits A0 to A23 Output of address bits (A0 to A7) and input/output of data (D0 to D7) by time-division while accessing an external memory space with multiplexed bus Output of address bits (A8 to A15) and input/output of data (D8 to D15) by time-division while accessing an external memory space with 16-bit or 32-bit multiplexed bus AVCC, AVSS RESET I I I I/O I O I O O O I I I I/O I/O I/O O I/O CNVSS NSD XIN Main clock output XOUT Sub clock input Sub clock output BCLK output Clock output XCIN XCOUT BCLK CLKOUT External interrupt INT0 to INT8 (1) input NMI input Bus control pins P8_5/NMI D0 to D7 D8 to D15 D16 to D31 (2) A0 to A23 A0/D0 to A7/D7 Key input interrupt KI0 to KI3 A8/D8 to A15/D15 I/O Notes: 1. Pins INT6 to INT8 are available in the 144-pin package only. 2. Pins D16 to D31 are available in the 144-pin package only. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 18 of 122 R32C/118 Group 1. Overview Table 1.14 Pin Definitions and Functions (2/4) Function Bus control pins (1) Symbol BC0/D0, BC2/D1 I/O I/O O Description Output of byte control (BC0 and BC2) and input/output of data (D0 and D1) by time-division while accessing an external memory space with multiplexed bus Chip select output Output of write, byte control, and read signals. Either WRx or WR and BCx can be selected by a program. Data is read when RD is low. • When WR0, WR1, WR2, WR3, and RD are selected, data is written to the following address: 4n+0, when WR0 is low 4n+1, when WR1 is low 4n+2, when WR2 is low 4n+3, when WR3 is low on 32-bit external data bus or an even address, when WR0 is low an odd address, when WR1 is low on 16-bit external data bus • When WR, BC0, BC1, BC2, BC3, and RD are selected, data is written, when WR is low and the following address is accessed: 4n+0, when BC0 is low 4n+1, when BC1 is low 4n+2, when BC2 is low 4n+3, when BC3 is low on 32-bit external data bus or an even address, when BC0 is low an odd address, when BC1 is low on 16-bit external data bus CS0 to CS3 WR0/WR1/WR2/ WR3 WR/BC0/BC1/ BC2/BC3 RD (1) O ALE HOLD HLDA RDY O I O I Latch enable signal in multiplexed bus format The MCU is in a hold state while this pin is held low This pin is driven low while the MCU is held in a hold state Bus cycle is extended by the CPU if this pin is low on the falling edge of the BCLK Note: 1. Pins BC2/D1, WR2, WR3, BC2, and BC3 are available in the 144-pin package only. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 19 of 122 R32C/118 Group 1. Overview Table 1.15 Pin Definitions and Functions (3/4) Function I/O port (1, 2) Symbol P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_7 P6_0 to P6_7 P7_0 to P7_7 P8_0 to P8_4 P8_6, P8_7 P9_0 to P9_7 P10_0 to P10_7 P11_0 to P11_4 P12_0 to P12_7 P13_0 to P13_7 P14_3 to P14_6 P15_0 to P15_7 P9_1 (for 100-pin package) P14_1 (for 144pin package) TA0OUT to TA4OUT TA0IN to TA4IN TB0IN to TB5IN U,U,V,V,W,W I/O Description I/O ports in CMOS. Each port can be programmed to input or output under the control of the direction register. Some ports are 5 V tolerant inputs. Pull-up resistors and N-channel open drain setting can be enabled on some ports. Refer to Table 1.17 “Pin Specifications” for details I/O Input port (2) I Input port in CMOS Pull-up resistor is selectable. Refer to Table 1.17 “Pin Specifications” for details Timers A0 to A4 input/output Timers A0 to A4 input Timers B0 to B5 input Three-phase motor control timer output Timer A I/O I I O Timer B Three-phase motor control timer output Serial interface CTS0 to CTS8 RTS0 to RTS8 I O I/O I O I/O I/O O I I Handshake input Handshake output Transmit/receive clock input/output Serial data input Serial data output Serial data input/output Transmit/receive clock input/output Serial data output in slave mode Serial data input in slave mode Input to control serial interface special functions CLK0 to CLK8 RXD0 to RXD8 TXD0 to TXD8 I2C bus (simplified) Serial interface special functions SDA0 to SDA6 SCL0 to SCL6 STXD0 to STXD6 SRXD0 to SRXD6 SS0 to SS6 Notes: 1. Port P9_1 in the 100-pin package is an input-only port. 2. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 20 of 122 R32C/118 Group 1. Overview Table 1.16 Pin Definitions and Functions (4/4) Function A/D converter Symbol AN_0 to AN_7 AN0_0 to AN0_7 AN2_0 to AN2_7 AN15_0 to AN15_7 (1) ADTRG I/O Description Analog input for the A/D converter I I I/O I O I I/O I/O I O I/O I O I O I/O I/O I O I External trigger input for the A/D converter Expanded analog input for the A/D converter and output in external op-amp connection mode Expanded analog input for the A/D converter Output for the D/A converter Reference voltage input for the A/D converter and D/A converter Input/output for the Intelligent I/O group 0. Either input capture or output compare is selectable Input/output for the Intelligent I/O group 1. Either input capture or output compare is selectable Input for the two-phase encoder Output for OC (output compare) of the Intelligent I/O group 2 Clock input/output for the serial interface Receive data input for the serial interface Transmit data output for the serial interface Receive data input for the serial interface Transmit data output for the serial interface Serial data input/output Transmit/receive clock input/output Receive data input for the CAN communications Transmit data output for the CAN communications Input for the CAN wake-up interrupt ANEX0 ANEX1 D/A converter DA0, DA1 Reference voltage VREF input Intelligent I/O IIO0_0 to IIO0_7 IIO1_0 to IIO1_7 UD0A, UD0B, UD1A, UD1B OUTC2_0 to OUTC2_7 (2) ISCLK2 ISRXD2 ISTXD2 IEIN IEOUT Multi-master I2C- MSDA bus MSCL CAN Module CAN0IN, CAN1IN CAN0OUT, CAN1OUT CAN0WU, CAN1WU Notes: 1. Pins AN15_0 to AN15_7 are available in the 144-pin package only. 2. Pins OUTC2_3 to OUTC2_7 are available in the 144-pin package only. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 21 of 122 R32C/118 Group 1. Overview Table 1.17 Pin Specifications Package Pin names P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_3 P5_4 to P5_7 P6_0 to P6_7 P7_0 to P7_7 P8_0 to P8_3 P8_4, P8_6, P8_7 P9_0 to P9_3 (144-pin) P9_1, P9_3 (100-pin) P9_4 to P9_7 P10_0 to P10_7 P11_0 to P11_3 P11_4 P12_0 to P12_3 P12_4 to P12_7 P13_0 to P13_7 P14_1 P14_3 to P14_6 P15_0 to P15_7 144pin 100pin Selectable Functions Pull-up resistor (1) N-channel open drain (2) 5 V tolerant input (3) Notes: 1. Pull-up resistors are selected in 4-pin units, but are only enabled for those pins set as input ports. 2. N-channel open drain output can be enabled on the applicable pins on a discrete pin basis. 3. 5 V tolerant input is enabled when an applicable pin is set as an input port. When it is set as an I/O port, to enable 5 V tolerant input, this pin should be set as N-channel open drain output. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 22 of 122 R32C/118 Group 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) The CPU contains registers as shown below. There are two register banks each consisting of registers R2R0, R3R1, R6R4, R7R5, A0 to A3, SB, and FB. General purpose registers R2R0 R3R1 R6R4 R7R5 b31 b23 b15 b7 b0 R2H R3H R6 R7 R2L R3L R0H R1H R4 R5 A0 A1 A2 A3 SB FB USP ISP R0L R1L Data registers (1) Address registers (1) Static base register (1) Frame base register (1) User stack pointer Interrupt stack pointer Interrupt vector table base register Program counter Flag register INTB PC FLG b31 b24 b23 b16 b15 b8 b7 b0 RND DP IPL FU FO U I OBSZDC Blank fields represent reserved. Fast interrupt registers b31 b0 SVF SVP VCT Save flag register Save PC register Vector register b0 DMAC-associated registers (2) b31 b23 DMD0 DMD0 DMD0 DMD0 DCT0 DCT0 DCT0 DCT0 DCR0 DCR0 DCR0 DCR0 DSA0 DSA0 DSA0 DSA0 DSR0 DSR0 DSR0 DSR0 DDA0 DDA0 DDA0 DDA0 DDR0 DDR0 DDR0 DDR0 DMA mode register DMA terminal count register DMA terminal count reload register DMA source address register DMA source address reload register DMA destination address register DMA destination address reload register Notes: 1. There are two banks of these registers. 2. There are four identical sets of DMAC-associated registers. Figure 2.1 CPU Registers REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 23 of 122 R32C/118 Group 2. Central Processing Unit (CPU) 2.1 2.1.1 General Purpose Registers Data Registers (R2R0, R3R1, R6R4, and R7R5) These 32-bit registers are primarily used for transfers and arithmetic/logic operations. Each of the registers can be divided into upper and lower 16-bit registers, e.g. R2R0 can be divided into R2 and R0, R3R0 can be divided into R3 and R1, etc. Moreover, data registers R2R0 and R3R1 can be divided into four 8-bit data registers: upper (R2H and R3H), mid-upper (R2L and R3L), mid-lower (R0H and R1H), and lower (R0L and R1L). 2.1.2 Address Registers (A0, A1, A2, and A3) These 32-bit registers have functions similar to data registers. They are also used for address register indirect addressing and address register relative addressing. 2.1.3 Static Base Register (SB) This 32-bit register is used for SB relative addressing. 2.1.4 Frame Base Register (FB) This 32-bit register is used for FB relative addressing. 2.1.5 Program Counter (PC) This 32-bit counter indicates the address of the instruction to be executed next. 2.1.6 Interrupt Vector Table Base Register (INTB) This 32-bit register indicates the start address of a relocatable vector table. 2.1.7 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) Two types of 32-bit stack pointers (SPs) are provided: user stack pointer (USP) and interrupt stack pointer (ISP). Use the stack pointer select flag (U flag) to select either the user stack pointer (USP) or the interrupt stack pointer (ISP). The U flag is bit 7 in the flag register (FLG). Refer to 2.1.8 “Flag Register (FLG)” for details. To minimize the overhead of interrupt sequence due to less memory access, set the user stack pointer (USP) or the interrupt stack pointer (ISP) to a multiple of 4. 2.1.8 Flag Register (FLG) This 32-bit register indicates the CPU status. 2.1.8.1 Carry Flag (C flag) This flag becomes 1 when any of the carry, borrow, shifted-out bit, etc. is generated in the arithmetic logic unit (ALU). 2.1.8.2 Debug Flag (D flag) This flag is only for debugging. Only set this bit to 0. 2.1.8.3 Zero Flag (Z flag) This flag becomes 1 when the result of an operation is 0; otherwise it is 0. 2.1.8.4 Sign Flag (S flag) This flag becomes 1 when the result of an operation is a negative value; otherwise it is 0. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 24 of 122 R32C/118 Group 2. Central Processing Unit (CPU) 2.1.8.5 Register Bank Select Flag (B flag) This flag selects a register bank. It indicates 0 when the register bank 0 is selected, and 1 when the register bank 1 is selected. 2.1.8.6 Overflow Flag (O flag) This flag becomes 1 if an overflow occurs in an operation; otherwise it is 0. 2.1.8.7 Interrupt Enable Flag (I flag) This flag enables maskable interrupts. To disable maskable interrupts, set this flag to 0. To enable them, set this flag to 1. When an interrupt is accepted, the flag becomes 0. 2.1.8.8 Stack Pointer Select Flag (U flag) To select the interrupt stack pointer (ISP), set this flag to 0. To select the user stack pointer (USP), set this flag to 1. It becomes 0 when a hardware interrupts is accepted or when an INT instruction designated by a software interrupt number from 0 to 127 is executed. 2.1.8.9 Floating-point Underflow Flag (FU flag) This flag becomes 1 when an underflow occurs in a floating-point operation; otherwise it is 0. It also becomes 1 when the operand has invalid numbers (subnormal numbers). 2.1.8.10 Floating-point Overflow Flag (FO flag) This flag becomes 1 when an overflow occurs in a floating-point operation; otherwise it is 0. It also becomes 1 when the operand has invalid numbers (subnormal numbers). 2.1.8.11 Processor Interrupt Priority Level (IPL) The processor interrupt priority level (IPL), consisting of three bits, selects a processor interrupt priority level from level 0 to 7. An interrupt is acceptable when the interrupt request level is higher than the selected IPL. When the processor interrupt priority level (IPL) is set to 111b (level 7), all interrupts are disabled. 2.1.8.12 Fixed-point Radix Point Designation Bit (DP bit) This bit designates the radix point. It also specifies which portion of the fixed-point multiplication result to take. It is used in the MULX instruction. 2.1.8.13 Floating-point Rounding Mode (RND) The 2-bit floating-point rounding mode selects a rounding mode for floating-point calculation results. 2.1.8.14 Reserved Only set this bit to 0. The read value is undefined. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 25 of 122 R32C/118 Group 2. Central Processing Unit (CPU) 2.2 Fast Interrupt Registers The following three registers are provided to minimize the overhead of interrupt sequence. 2.2.1 Save Flag Register (SVF) This 32-bit register is used to save the flag register when a fast interrupt is generated. 2.2.2 Save PC Register (SVP) This 32-bit register is used to save the program counter when a fast interrupt is generated. 2.2.3 Vector Register (VCT) This 32-bit register is used to indicate a jump address when a fast interrupt is generated. 2.3 DMAC-associated Registers There are seven types of DMAC-associated registers. 2.3.1 DMA Mode Registers (DMD0, DMD1, DMD2, and DMD3) These 32-bit registers are used to set DMA transfer mode, bit rate etc. 2.3.2 DMA Terminal Count Registers (DCT0, DCT1, DCT2, and DCT3) These 24-bit registers are used to set DMA transfer counting. 2.3.3 DMA Terminal Count Reload Registers (DCR0, DCR1, DCR2, and DCR3) These 24-bit registers are used to set the reloaded values for DMA terminal count registers. 2.3.4 DMA Source Address Registers (DSA0, DSA1, DSA2, and DSA3) These 32-bit registers are used to set DMA source addresses. 2.3.5 DMA Source Address Reload Registers (DSR0, DSR1, DSR2, and DSR3) These 32-bit registers are used to set the reloaded value for DMA source address register. 2.3.6 DMA Destination Address Registers (DDA0, DDA1, DDA2, and DDA3) These 32-bit registers are used to set DMA destination address. 2.3.7 DMA Destination Address Reload Registers (DDR0, DDR1, DDR2, and DDR3) These 32-bit registers are used to set reloaded values for DMA destination address registers. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 26 of 122 R32C/118 Group 3. Memory 3. Memory Figure 3.1 shows the memory map of the R32C/118 Group. The R32C/118 Group provides a 4-Gbyte address space from 00000000h to FFFFFFFFh. The internal ROM is mapped to the end of the memory map with the ending address fixed at FFFFFFFFh. Therefore, the 1-Mbyte internal ROM is mapped from FFF00000h to FFFFFFFFh. The fixed interrupt vector table which contains each start address of interrupt handlers is mapped from FFFFFFDCh to FFFFFFFFh. The internal RAM is mapped to the beginning of the memory map with the starting address fixed at 00000400h. Therefore, the 63-Kbyte internal RAM is mapped from 00000400h to 0000FFFFh. Besides being used for data storage, the internal RAM functions as a stack(s) for subroutines and/or interrupt handlers. Special Function Registers (SFRs), which are control registers for peripheral functions, are mapped from 00000000h to 000003FFh, and from 00040000h to 0004FFFFh. Unoccupied SFR locations are reserved. No access is allowed. In memory expansion mode or microprocessor mode, some spaces are reserved for internal use and should not be accessed. 00000000h 00000400h Internal RAM Capacity 40 Kbytes 48 Kbytes 63 Kbytes XXXXXXXXh 0000A400h 0000C400h 00010000h 00040000h 00050000h 00060000h XXXXXXXXh SFR1 Internal RAM Reserved SFR2 Reserved Internal ROM (Data space) (1) Reserved Internal ROM Capacity 384 Kbytes 512 Kbytes 640 Kbytes 768 Kbytes 1 Mbyte YYYYYYYYh FFFA0000h FFF80000h FFF60000h FFF40000h FFF00000h 00062000h FFFFFFDCh Undefined instruction Overflow BRK instruction Reserved Reserved Watchdog timer (5) Reserved NMI Reset FFFFFFFFh 00080000h External space (2) FFE00000h Reserved (3) YYYYYYYYh Internal ROM (4) FFFFFFFFh Notes: 1. Additional two 4-Kbyte spaces (blocks A and B) for storing data are provided in the flash memory version. 2. This space can be used in memory expansion mode or microprocessor mode. Addresses from 02000000h to FDFFFFFFh are inaccessible. 3. This space is reserved in memory expansion mode. It can be external space in microprocessor mode. 4. This space can be used in single-chip mode or memory expansion mode. It can be external space in microprocessor mode. 5. The watchdog timer interrupt shares the vector table with the oscillator stop detection interrupt and low voltage detection interrupt. Figure 3.1 Memory Map REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 27 of 122 R32C/118 Group 4. Special Function Registers (SFRs) 4. Special Function Registers (SFRs) SFRs are memory-mapped peripheral registers that control the operation of peripherals. Table 4.1 SFR List (1) to Table 4.53 SFR List (53) list the SFR details. Table 4.1 SFR List (1) Symbol Reset Value Address Register 000000h 000001h 000002h 000003h 000004h Clock Control Register 000005h 000006h Flash Memory Control Register 000007h Protect Release Register 000008h 000009h 00000Ah 00000Bh 00000Ch 00000Dh 00000Eh 00000Fh 000010h External Bus Control Register 3/Flash Memory Rewrite Bus 000011h Control Register 3 000012h Chip Selects 2 and 3 Boundary Setting Register 000013h 000014h External Bus Control Register 2 000015h 000016h Chip Selects 1 and 2 Boundary Setting Register 000017h 000018h External Bus Control Register 1 000019h 00001Ah Chip selects 0 and 1 Boundary Setting Register 00001Bh 00001Ch External Bus Control Register 0/Flash Memory Rewrite Bus 00001Dh Control Register 0 00001Eh Peripheral Bus Control Register 00001Fh 000020h to 00005Fh X: Undefined Blanks are reserved. No access is allowed. CCR FMCR PRR 0001 1000b 0000 0001b 00h EBC3/FEBC3 CB23 EBC2 CB12 EBC1 CB01 EBC0/FEBC0 PBC 0000h 00h 0000h 00h 0000h 00h 0000h 0504h REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 28 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.2 SFR List (2) Symbol TB5IC S5TIC S2RIC/I2CLIC S6TIC S3RIC BCN5IC/BCN6IC S4RIC DM0IC BCN0IC/BCN3IC DM2IC AD0IC TA0IC IIO0IC TA2IC IIO2IC TA4IC IIO4IC S0RIC IIO6IC S1RIC IIO8IC TB1IC IIO10IC TB3IC INT5IC C0WIC INT3IC INT1IC Reset Value XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XX00 X000b XXXX X000b XX00 X000b XX00 X000b Address Register 000060h 000061h Timer B5 Interrupt Control Register 000062h UART5 Transmit/NACK Interrupt Control Register 000063h UART2 Receive/ACK Interrupt Control Register/I2C Bus Line Interrupt Control Register 000064h UART6 Transmit/NACK Interrupt Control Register 000065h UART3 Receive/ACK Interrupt Control Register 000066h UART5/6 Bus Collision, Start Condition/Stop Condition Detection Interrupt Control Register 000067h UART4 Receive/ACK Interrupt Control Register 000068h DMA0 Transfer Complete Interrupt Control Register 000069h UART0/3 Bus Collision, Start Condition/Stop Condition Detection Interrupt Control Register 00006Ah DMA2 Transfer Complete Interrupt Control Register 00006Bh A/D Converter 0 Convert Completion Interrupt Control Register 00006Ch Timer A0 Interrupt Control Register 00006Dh Intelligent I/O Interrupt Control Register 0 00006Eh Timer A2 Interrupt Control Register 00006Fh Intelligent I/O Interrupt Control Register 2 000070h Timer A4 Interrupt Control Register 000071h Intelligent I/O Interrupt Control Register 4 000072h UART0 Receive/ACK Interrupt Control Register 000073h Intelligent I/O Interrupt Control Register 6 000074h UART1 Receive/ACK Interrupt Control Register 000075h Intelligent I/O Interrupt Control Register 8 000076h Timer B1 Interrupt Control Register 000077h Intelligent I/O Interrupt Control Register 10 000078h Timer B3 Interrupt Control Register 000079h 00007Ah INT5 Interrupt Control Register 00007Bh CAN0 Wake-up Interrupt Control Register 00007Ch INT3 Interrupt Control Register 00007Dh 00007Eh INT1 Interrupt Control Register 00007Fh 000080h 000081h UART2 Transmit/NACK Interrupt Control Register/I2C-Bus Interrupt Control Register 000082h UART5 Receive/ACK Interrupt Control Register 000083h UART3 Transmit/NACK Interrupt Control Register 000084h UART6 Receive/ACK Interrupt Control Register 000085h UART4 Transmit/NACK Interrupt Control Register 000086h 000087h UART2 Bus Collision, Start Condition/Stop Condition Detection Interrupt Control Register X: Undefined Blanks are reserved. No access is allowed. S2TIC/I2CIC S5RIC S3TIC S6RIC S4TIC BCN2IC XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 29 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.3 SFR List (3) Symbol DM1IC BCN1IC/BCN4IC DM3IC KUPIC TA1IC IIO1IC TA3IC IIO3IC S0TIC IIO5IC S1TIC IIO7IC TB0IC IIO9IC TB2IC IIO11IC TB4IC INT4IC C1WIC INT2IC INT0IC IIO0IR IIO1IR IIO2IR IIO3IR IIO4IR IIO5IR IIO6IR IIO7IR IIO8IR IIO9IR IIO10IR IIO11IR Reset Value XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XX00 X000b XXXX X000b XX00 X000b XX00 X000b 0000 0XX1b 0000 0XX1b 0000 0X01b 0000 XXX1b 000X 0XX1b 000X 0XX1b 000X 0XX1b X00X 0XX1b XX0X 0XX1b 0X00 0XX1b 0X00 0XX1b 0X00 0XX1b Address Register 000088h DMA1 Transfer Complete Interrupt Control Register 000089h UART1/4 Bus Collision, Start Condition/Stop Condition Detection Interrupt Control Register 00008Ah DMA3 Transfer Complete Interrupt Control Register 00008Bh Key Input Interrupt Control Register 00008Ch Timer A1 Interrupt Control Register 00008Dh Intelligent I/O Interrupt Control Register 1 00008Eh Timer A3 Interrupt Control Register 00008Fh Intelligent I/O Interrupt Control Register 3 000090h UART0 Transmit/NACK Interrupt Control Register 000091h Intelligent I/O Interrupt Control Register 5 000092h UART1 Transmit/NACK Interrupt Control Register 000093h Intelligent I/O Interrupt Control Register 7 000094h Timer B0 Interrupt Control Register 000095h Intelligent I/O Interrupt Control Register 9 000096h Timer B2 Interrupt Control Register 000097h Intelligent I/O Interrupt Control Register 11 000098h Timer B4 Interrupt Control Register 000099h 00009Ah INT4 Interrupt Control Register 00009Bh CAN1 Wake-up Interrupt Control Register 00009Ch INT2 Interrupt Control Register 00009Dh 00009Eh INT0 Interrupt Control Register 00009Fh 0000A0h Intelligent I/O Interrupt Request Register 0 0000A1h Intelligent I/O Interrupt Request Register 1 0000A2h Intelligent I/O Interrupt Request Register 2 0000A3h Intelligent I/O Interrupt Request Register 3 0000A4h Intelligent I/O Interrupt Request Register 4 0000A5h Intelligent I/O Interrupt Request Register 5 0000A6h Intelligent I/O Interrupt Request Register 6 0000A7h Intelligent I/O Interrupt Request Register 7 0000A8h Intelligent I/O Interrupt Request Register 8 0000A9h Intelligent I/O Interrupt Request Register 9 0000AAh Intelligent I/O Interrupt Request Register 10 0000ABh Intelligent I/O Interrupt Request Register 11 0000ACh 0000ADh 0000AEh 0000AFh X: Undefined Blanks are reserved. No access is allowed. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 30 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.4 SFR List (4) Symbol IIO0IE IIO1IE IIO2IE IIO3IE IIO4IE IIO5IE IIO6IE IIO7IE IIO8IE IIO9IE IIO10IE IIO11IE Reset Value 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Address Register 0000B0h Intelligent I/O Interrupt Enable Register 0 0000B1h Intelligent I/O Interrupt Enable Register 1 0000B2h Intelligent I/O Interrupt Enable Register 2 0000B3h Intelligent I/O Interrupt Enable Register 3 0000B4h Intelligent I/O Interrupt Enable Register 4 0000B5h Intelligent I/O Interrupt Enable Register 5 0000B6h Intelligent I/O Interrupt Enable Register 6 0000B7h Intelligent I/O Interrupt Enable Register 7 0000B8h Intelligent I/O Interrupt Enable Register 8 0000B9h Intelligent I/O Interrupt Enable Register 9 0000BAh Intelligent I/O Interrupt Enable Register 10 0000BBh Intelligent I/O Interrupt Enable Register 11 0000BCh 0000BDh 0000BEh 0000BFh 0000C0h 0000C1h CAN0 Transmit Interrupt Control Register 0000C2h 0000C3h CAN0 Error Interrupt Control Register 0000C4h 0000C5h CAN1 Receive Interrupt Control Register 0000C6h 0000C7h 0000C8h 0000C9h 0000CAh 0000CBh 0000CCh 0000CDh 0000CEh 0000CFh 0000D0h CAN0 Transmit FIFO Interrupt Control Register 0000D1h 0000D2h CAN1 Transmit FIFO Interrupt Control Register 0000D3h 0000D4h 0000D5h 0000D6h 0000D7h 0000D8h 0000D9h 0000DAh 0000DBh 0000DCh 0000DDh UART7 Transmit Interrupt Control Register 0000DEh INT7 Interrupt Control Register 0000DFh UART8 Transmit Interrupt Control Register X: Undefined Blanks are reserved. No access is allowed. C0TIC C0EIC C1RIC XXXX X000b XXXX X000b XXXX X000b C0FTIC C1FTIC XXXX X000b XXXX X000b S7TIC INT7IC S8TIC XXXX X000b XX00 X000b XXXX X000b REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 31 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.5 SFR List (5) Symbol C0RIC C1TIC C1EIC Reset Value XXXX X000b XXXX X000b XXXX X000b Address Register 0000E0h 0000E1h CAN0 Receive Interrupt Control Register 0000E2h 0000E3h CAN1 Transmit Interrupt Control Register 0000E4h 0000E5h CAN1 Error Interrupt Control Register 0000E6h 0000E7h 0000E8h 0000E9h 0000EAh 0000EBh 0000ECh 0000EDh 0000EEh 0000EFh 0000F0h CAN0 Receive FIFO Interrupt Control Register 0000F1h 0000F2h CAN1 Receive FIFO Interrupt Control Register 0000F3h 0000F4h 0000F5h 0000F6h 0000F7h 0000F8h 0000F9h 0000FAh 0000FBh 0000FCh INT8 Interrupt Control Register 0000FDh UART7 Receive Interrupt Control Register 0000FEh INT6 Interrupt Control Register 0000FFh UART8 Receive Interrupt Control Register 000100h Group 1 Time Measurement/Waveform Generation Register 0 000101h 000102h Group 1 Time Measurement/Waveform Generation Register 1 000103h 000104h Group 1 Time Measurement/Waveform Generation Register 2 000105h 000106h Group 1 Time Measurement/Waveform Generation Register 3 000107h X: Undefined Blanks are reserved. No access is allowed. C0FRIC C1FRIC XXXX X000b XXXX X000b INT8IC S7RIC INT6IC S8RIC G1TM0/G1PO0 G1TM1/G1PO1 G1TM2/G1PO2 G1TM3/G1PO3 XX00 X000b XXXX X000b XX00 X000b XXXX X000b XXXXh XXXXh XXXXh XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 32 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.6 SFR List (6) Symbol G1TM4/G1PO4 G1TM5/G1PO5 G1TM6/G1PO6 G1TM7/G1PO7 G1POCR0 G1POCR1 G1POCR2 G1POCR3 G1POCR4 G1POCR5 G1POCR6 G1POCR7 G1TMCR0 G1TMCR1 G1TMCR2 G1TMCR3 G1TMCR4 G1TMCR5 G1TMCR6 G1TMCR7 G1BT G1BCR0 G1BCR1 G1TPR6 G1TPR7 G1FE G1FS Reset Value XXXXh XXXXh XXXXh XXXXh 0000 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 00h 00h 00h 00h 00h 00h 00h 00h XXXXh 00h 0000 0000b 00h 00h 00h 00h Address Register 000108h Group 1 Time Measurement/Waveform Generation Register 4 000109h 00010Ah Group 1 Time Measurement/Waveform Generation Register 5 00010Bh 00010Ch Group 1 Time Measurement/Waveform Generation Register 6 00010Dh 00010Eh Group 1 Time Measurement/Waveform Generation Register 7 00010Fh 000110h Group 1 Waveform Generation Control Register 0 000111h Group 1 Waveform Generation Control Register 1 000112h Group 1 Waveform Generation Control Register 2 000113h Group 1 Waveform Generation Control Register 3 000114h Group 1 Waveform Generation Control Register 4 000115h Group 1 Waveform Generation Control Register 5 000116h Group 1 Waveform Generation Control Register 6 000117h Group 1 Waveform Generation Control Register 7 000118h Group 1 Time Measurement Control Register 0 000119h Group 1 Time Measurement Control Register 1 00011Ah Group 1 Time Measurement Control Register 2 00011Bh Group 1 Time Measurement Control Register 3 00011Ch Group 1 Time Measurement Control Register 4 00011Dh Group 1 Time Measurement Control Register 5 00011Eh Group 1 Time Measurement Control Register 6 00011Fh Group 1 Time Measurement Control Register 7 000120h Group 1 Base Timer Register 000121h 000122h Group 1 Base Timer Control Register 0 000123h Group 1 Base Timer Control Register 1 000124h Group 1 Timer Measurement Prescaler Register 6 000125h Group 1 Timer Measurement Prescaler Register 7 000126h Group 1 Function Enable Register 000127h Group 1 Function Select Register 000128h 000129h 00012Ah 00012Bh 00012Ch 00012Dh 00012Eh 00012Fh 000130h to 00013Fh X: Undefined Blanks are reserved. No access is allowed. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 33 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.7 SFR List (7) Symbol G2PO0 G2PO1 G2PO2 G2PO3 G2PO4 G2PO5 G2PO6 G2PO7 G2POCR0 G2POCR1 G2POCR2 G2POCR3 G2POCR4 G2POCR5 G2POCR6 G2POCR7 Reset Value XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b Address Register 000140h Group 2 Waveform Generation Register 0 000141h 000142h Group 2 Waveform Generation Register 1 000143h 000144h Group 2 Waveform Generation Register 2 000145h 000146h Group 2 Waveform Generation Register 3 000147h 000148h Group 2 Waveform Generation Register 4 000149h 00014Ah Group 2 Waveform Generation Register 5 00014Bh 00014Ch Group 2 Waveform Generation Register 6 00014Dh 00014Eh Group 2 Waveform Generation Register 7 00014Fh 000150h Group 2 Waveform Generation Control Register 0 000151h Group 2 Waveform Generation Control Register 1 000152h Group 2 Waveform Generation Control Register 2 000153h Group 2 Waveform Generation Control Register 3 000154h Group 2 Waveform Generation Control Register 4 000155h Group 2 Waveform Generation Control Register 5 000156h Group 2 Waveform Generation Control Register 6 000157h Group 2 Waveform Generation Control Register 7 000158h 000159h 00015Ah 00015Bh 00015Ch 00015Dh 00015Eh 00015Fh 000160h Group 2 Base Timer Register 000161h 000162h Group 2 Base Timer Control Register 0 000163h Group 2 Base Timer Control Register 1 000164h Base Timer Start Register 000165h 000166h Group 2 Function Enable Register 000167h Group 2 RTP Output Buffer Register 000168h 000169h 00016Ah Group 2 Serial Interface Mode Register 00016Bh Group 2 Serial Interface Control Register 00016Ch Group 2 SI/O Transmit Buffer Register 00016Dh 00016Eh Group 2 SI/O Receive Buffer Register 00016Fh X: Undefined Blanks are reserved. No access is allowed. G2BT G2BCR0 G2BCR1 BTSR G2FE G2RTP XXXXh 00h 0000 0000b XXXX 0000b 00h 00h G2MR G2CR G2TB G2RB 00XX X000b 0000 X110b XXXXh XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 34 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.8 SFR List (8) Symbol IEAR IECR IETIF IERIF Reset Value XXXXh 00XX X000b XXX0 0000b XXX0 0000b Address Register 000170h Group 2 IE Bus Address Register 000171h 000172h Group 2 IE Bus Control Register 000173h Group 2 IE Bus Transmit Interrupt Source Detect Register 000174h Group 2 IE Bus Receive Interrupt Source Detect Register 000175h 000176h 000177h 000178h 000179h 00017Ah 00017Bh 00017Ch 00017Dh 00017Eh 00017Fh 000180h Group 0 Time Measurement/Waveform Generation Register 0 000181h 000182h Group 0 Time Measurement/Waveform Generation Register 1 000183h 000184h Group 0 Time Measurement/Waveform Generation Register 2 000185h 000186h Group 0 Time Measurement/Waveform Generation Register 3 000187h 000188h Group 0 Time Measurement/Waveform Generation Register 4 000189h 00018Ah Group 0 Time Measurement/Waveform Generation Register 5 00018Bh 00018Ch Group 0 Time Measurement/Waveform Generation Register 6 00018Dh 00018Eh Group 0 Time Measurement/Waveform Generation Register 7 00018Fh 000190h Group 0 Waveform Generation Control Register 0 000191h Group 0 Waveform Generation Control Register 1 000192h Group 0 Waveform Generation Control Register 2 000193h Group 0 Waveform Generation Control Register 3 000194h Group 0 Waveform Generation Control Register 4 000195h Group 0 Waveform Generation Control Register 5 000196h Group 0 Waveform Generation Control Register 6 000197h Group 0 Waveform Generation Control Register 7 000198h Group 0 Time Measurement Control Register 0 000199h Group 0 Time Measurement Control Register 1 00019Ah Group 0 Time Measurement Control Register 2 00019Bh Group 0 Time Measurement Control Register 3 00019Ch Group 0 Time Measurement Control Register 4 00019Dh Group 0 Time Measurement Control Register 5 00019Eh Group 0 Time Measurement Control Register 6 00019Fh Group 0 Time Measurement Control Register 7 X: Undefined Blanks are reserved. No access is allowed. G0TM0/G0PO0 G0TM1/G0PO1 G0TM2/G0PO2 G0TM3/G0PO3 G0TM4/G0PO4 G0TM5/G0PO5 G0TM6/G0PO6 G0TM7/G0PO7 G0POCR0 G0POCR1 G0POCR2 G0POCR3 G0POCR4 G0POCR5 G0POCR6 G0POCR7 G0TMCR0 G0TMCR1 G0TMCR2 G0TMCR3 G0TMCR4 G0TMCR5 G0TMCR6 G0TMCR7 XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh 0000 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 00h 00h 00h 00h 00h 00h 00h 00h REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 35 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.9 SFR List (9) Symbol G0BT G0BCR0 G0BCR1 G0TPR6 G0TPR7 G0FE G0FS Reset Value XXXXh 00h 0000 0000b 00h 00h 00h 00h Address Register 0001A0h Group 0 Base Timer Register 0001A1h 0001A2h Group 0 Base Timer Control Register 0 0001A3h Group 0 Base Timer Control Register 1 0001A4h Group 0 Timer Measurement Prescaler Register 6 0001A5h Group 0 Timer Measurement Prescaler Register 7 0001A6h Group 0 Function Enable Register 0001A7h Group 0 Function Select Register 0001A8h 0001A9h 0001AAh 0001ABh 0001ACh 0001ADh 0001AEh 0001AFh 0001B0h 0001B1h 0001B2h 0001B3h 0001B4h 0001B5h 0001B6h 0001B7h 0001B8h 0001B9h 0001BAh 0001BBh 0001BCh 0001BDh 0001BEh 0001BFh 0001C0h 0001C1h 0001C2h 0001C3h 0001C4h UART5 Special Mode Register 4 0001C5h UART5 Special Mode Register 3 0001C6h UART5 Special Mode Register 2 0001C7h UART5 Special Mode Register 0001C8h UART5 Transmit/Receive Mode Register 0001C9h UART5 Bit Rate Register 0001CAh UART5 Transmit Buffer Register 0001CBh 0001CCh UART5 Transmit/Receive Control Register 0 0001CDh UART5 Transmit/Receive Control Register 1 0001CEh UART5 Receive Buffer Register 0001CFh X: Undefined Blanks are reserved. No access is allowed. U5SMR4 U5SMR3 U5SMR2 U5SMR U5MR U5BRG U5TB U5C0 U5C1 U5RB 00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 36 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.10 SFR List (10) Symbol Reset Value Address Register 0001D0h 0001D1h 0001D2h 0001D3h 0001D4h UART6 Special Mode Register 4 0001D5h UART6 Special Mode Register 3 0001D6h UART6 Special Mode Register 2 0001D7h UART6 Special Mode Register 0001D8h UART6 Transmit/Receive Mode Register 0001D9h UART6 Bit Rate Register 0001DAh UART6 Transmit Buffer Register 0001DBh 0001DCh UART6 Transmit/Receive Control Register 0 0001DDh UART6 Transmit/Receive Control Register 1 0001DEh UART6 Receive Buffer Register 0001DFh 0001E0h UART7 Transmit/Receive Mode Register 0001E1h UART7 Bit Rate Register 0001E2h UART7 Transmit Buffer Register 0001E3h 0001E4h UART7 Transmit/Receive Control Register 0 0001E5h UART7 Transmit/Receive Control Register 1 0001E6h UART7 Receive Buffer Register 0001E7h 0001E8h UART8 Transmit/Receive Mode Register 0001E9h UART8 Bit Rate Register 0001EAh UART8 Transmit Buffer Register 0001EBh 0001ECh UART8 Transmit/Receive Control Register 0 0001EDh UART8 Transmit/Receive Control Register 1 0001EEh UART8 Receive Buffer Register 0001EFh 0001F0h UART7, UART8 Transmit/Receive Control Register 2 0001F1h 0001F2h 0001F3h 0001F4h 0001F5h 0001F6h 0001F7h 0001F8h 0001F9h 0001FAh 0001FBh 0001FCh 0001FDh 0001FEh 0001FFh X: Undefined Blanks are reserved. No access is allowed. U6SMR4 U6SMR3 U6SMR2 U6SMR U6MR U6BRG U6TB U6C0 U6C1 U6RB U7MR U7BRG U7TB U7C0 U7C1 U7RB U8MR U8BRG U8TB U8C0 U8C1 U8RB U78CON 00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh 00h XXh XXXXh 00X0 1000b XXXX 0010b XXXXh 00h XXh XXXXh 00X0 1000b XXXX 0010b XXXXh X000 0000b REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 37 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.11 SFR List (11) Symbol Reset Value Address Register 000200h to 0002BFh 0002C0h X0 Register/Y0 Register 0002C1h 0002C2h X1 Register/Y1 Register 0002C3h 0002C4h X2 Register/Y2 Register 0002C5h 0002C6h X3 Register/Y3 Register 0002C7h 0002C8h X4 Register/Y4 Register 0002C9h 0002CAh X5 Register/Y5 Register 0002CBh 0002CCh X6 Register/Y6 Register 0002CDh 0002CEh X7 Register/Y7 Register 0002CFh 0002D0h X8 Register/Y8 Register 0002D1h 0002D2h X9 Register/Y9 Register 0002D3h 0002D4h X10 Register/Y10 Register 0002D5h 0002D6h X11 Register/Y11 Register 0002D7h 0002D8h X12 Register/Y12 Register 0002D9h 0002DAh X13 Register/Y13 Register 0002DBh 0002DCh X14 Register/Y14 Register 0002DDh 0002DEh X15 Register/Y15 Register 0002DFh 0002E0h XY Control Register 0002E1h 0002E2h 0002E3h 0002E4h UART1 Special Mode Register 4 0002E5h UART1 Special Mode Register 3 0002E6h UART1 Special Mode Register 2 0002E7h UART1 Special Mode Register 0002E8h UART1 Transmit/Receive Mode Register 0002E9h UART1 Bit Rate Register 0002EAh UART1 Transmit Buffer Register 0002EBh 0002ECh UART1 Transmit/Receive Control Register 0 0002EDh UART1 Transmit/Receive Control Register 1 0002EEh UART1 Receive Buffer Register 0002EFh X: Undefined Blanks are reserved. No access is allowed. X0R/Y0R X1R/Y1R X2R/Y2R X3R/Y3R X4R/Y4R X5R/Y5R X6R/Y6R X7R/Y7R X8R/Y8R X9R/Y9R X10R/Y10R X11R/Y11R X12R/Y12R X13R/Y13R X14R/Y14R X15R/Y15R XYC XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXX XX00b U1SMR4 U1SMR3 U1SMR2 U1SMR U1MR U1BRG U1TB U1C0 U1C1 U1RB 00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 38 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.12 SFR List (12) Symbol Reset Value Address Register 0002F0h 0002F1h 0002F2h 0002F3h 0002F4h UART4 Special Mode Register 4 0002F5h UART4 Special Mode Register 3 0002F6h UART4 Special Mode Register 2 0002F7h UART4 Special Mode Register 0002F8h UART4 Transmit/Receive Mode Register 0002F9h UART4 Bit Rate Register 0002FAh UART4 Transmit Buffer Register 0002FBh 0002FCh UART4 Transmit/Receive Control Register 0 0002FDh UART4 Transmit/Receive Control Register 1 0002FEh UART4 Receive Buffer Register 0002FFh 000300h Count Start Register for Timers B3, B4 and B5 000301h 000302h Timer A1-1 Register 000303h 000304h Timer A2-1 Register 000305h 000306h Timer A4-1 Register 000307h 000308h Three-phase PWM Control Register 0 000309h Three-phase PWM Control Register 1 00030Ah Three-phase Output Buffer Register 0 00030Bh Three-phase Output Buffer Register 1 00030Ch Dead Time Timer 00030Dh Timer B2 Interrupt Generating Frequency Set Counter 00030Eh 00030Fh 000310h Timer B3 Register 000311h 000312h Timer B4 Register 000313h 000314h Timer B5 Register 000315h 000316h 000317h 000318h 000319h 00031Ah 00031Bh Timer B3 Mode Register 00031Ch Timer B4 Mode Register 00031Dh Timer B5 Mode Register 00031Eh 00031Fh X: Undefined Blanks are reserved. No access is allowed. U4SMR4 U4SMR3 U4SMR2 U4SMR U4MR U4BRG U4TB U4C0 U4C1 U4RB TBSR TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2 00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh 000X XXXXb XXXXh XXXXh XXXXh 00h 00h XX11 1111b XX11 1111b XXh XXh TB3 TB4 TB5 XXXXh XXXXh XXXXh TB3MR TB4MR TB5MR 00XX 0000b 00XX 0000b 00XX 0000b REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 39 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.13 SFR List (13) Symbol Reset Value Address Register 000320h 000321h 000322h 000323h 000324h UART3 Special Mode Register 4 000325h UART3 Special Mode Register 3 000326h UART3 Special Mode Register 2 000327h UART3 Special Mode Register 000328h UART3 Transmit/Receive Mode Register 000329h UART3 Bit Rate Register 00032Ah UART3 Transmit Buffer Register 00032Bh 00032Ch UART3 Transmit/Receive Control Register 0 00032Dh UART3 Transmit/Receive Control Register 1 00032Eh UART3 Receive Buffer Register 00032Fh 000330h 000331h 000332h 000333h 000334h UART2 Special Mode Register 4 000335h UART2 Special Mode Register 3 000336h UART2 Special Mode Register 2 000337h UART2 Special Mode Register 000338h UART2 Transmission/Receive Mode Register 000339h UART2 Bit Rate Register 00033Ah UART2 Transmit Buffer Register 00033Bh 00033Ch UART2 Transmit/Receive Control Register 0 00033Dh UART2 Transmit/Receive Control Register 1 00033Eh UART2 Receive Buffer Register 00033Fh 000340h Count Start Register 000341h Clock Prescaler Reset Register 000342h One-shot Start Register 000343h Trigger Select Register 000344h Increment/Decrement Counting Select Register 000345h 000346h Timer A0 Register 000347h 000348h Timer A1 Register 000349h 00034Ah Timer A2 Register 00034Bh 00034Ch Timer A3 Register 00034Dh 00034Eh Timer A4 Register 00034Fh X: Undefined Blanks are reserved. No access is allowed. U3SMR4 U3SMR3 U3SMR2 U3SMR U3MR U3BRG U3TB U3C0 U3C1 U3RB 00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB TABSR CPSRF ONSF TRGSR UDF TA0 TA1 TA2 TA3 TA4 00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh 00h 0XXX XXXXb 00h 00h 0000 0000b XXXXh XXXXh XXXXh XXXXh XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 40 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.14 SFR List (14) Symbol TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC TCSPR Reset Value XXXXh XXXXh XXXXh 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 00XX 0000b 00XX 0000b 00XX 0000b XXXX XXX0b 0000 0000b Address Register 000350h Timer B0 Register 000351h 000352h Timer B1 Register 000353h 000354h Timer B2 Register 000355h 000356h Timer A0 Mode Register 000357h Timer A1 Mode Register 000358h Timer A2 Mode Register 000359h Timer A3 Mode Register 00035Ah Timer A4 Mode Register 00035Bh Timer B0 Mode Register 00035Ch Timer B1 Mode Register 00035Dh Timer B2 Mode Register 00035Eh Timer B2 Special Mode Register 00035Fh Count Source Prescaler Register 000360h 000361h 000362h 000363h 000364h UART0 Special Mode Register 4 000365h UART0 Special Mode Register 3 000366h UART0 Special Mode Register 2 000367h UART0 Special Mode Register 000368h UART0 Transmit/Receive Mode Register 000369h UART0 Bit Rate Register 00036Ah UART0 Transmit Buffer Register 00036Bh 00036Ch UART0 Transmit/Receive Control Register 0 00036Dh UART0 Transmit/Receive Control Register 1 00036Eh UART0 Receive Buffer Register 00036Fh 000370h 000371h 000372h 000373h 000374h 000375h 000376h 000377h 000378h 000379h 00037Ah 00037Bh 00037Ch CRC Data Register 00037Dh 00037Eh CRC Input Register 00037Fh X: Undefined Blanks are reserved. No access is allowed. U0SMR4 U0SMR3 U0SMR2 U0SMR U0MR U0BRG U0TB U0C0 U0C1 U0RB 00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh CRCD CRCIN XXXXh XXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 41 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.15 SFR List (15) Symbol AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 Reset Value 00XXh 00XXh 00XXh 00XXh 00XXh 00XXh 00XXh 00XXh Address Register 000380h A/D0 Register 0 000381h 000382h A/D0 Register 1 000383h 000384h A/D0 Register 2 000385h 000386h A/D0 Register 3 000387h 000388h A/D0 Register 4 000389h 00038Ah A/D0 Register 5 00038Bh 00038Ch A/D0 Register 6 00038Dh 00038Eh A/D0 Register 7 00038Fh 000390h 000391h 000392h A/D0 Control Register 4 000393h 000394h A/D0 Control Register 2 000395h A/D0 Control Register 3 000396h A/D0 Control Register 0 000397h A/D0 Control Register 1 000398h D/A Register 0 000399h 00039Ah D/A Register 1 00039Bh 00039Ch D/A Control Register 00039Dh 00039Eh 00039Fh 0003A0h 0003A1h 0003A2h 0003A3h 0003A4h 0003A5h 0003A6h 0003A7h 0003A8h 0003A9h 0003AAh 0003ABh 0003ACh 0003ADh 0003AEh 0003AFh X: Undefined Blanks are reserved. No access is allowed. AD0CON4 AD0CON2 AD0CON3 AD0CON0 AD0CON1 DA0 DA1 DACON XXXX 00XXb X00X X000b XXXX X000b 00h 00h XXh XXh XXXX XX00b REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 42 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.16 SFR List (16) Symbol Reset Value Address Register 0003B0h 0003B1h 0003B2h 0003B3h 0003B4h 0003B5h 0003B6h 0003B7h 0003B8h 0003B9h 0003BAh 0003BBh 0003BCh 0003BDh 0003BEh 0003BFh 0003C0h Port P0 Register 0003C1h Port P1 Register 0003C2h Port P0 Direction Register 0003C3h Port P1 Direction Register 0003C4h Port P2 Register 0003C5h Port P3 Register 0003C6h Port P2 Direction Register 0003C7h Port P3 Direction Register 0003C8h Port P4 Register 0003C9h Port P5 Register 0003CAh Port P4 Direction Register 0003CBh Port P5 Direction Register 0003CCh Port P6 Register 0003CDh Port P7 Register 0003CEh Port P6 Direction Register 0003CFh Port P7 Direction Register 0003D0h Port P8 Register 0003D1h Port P9 Register 0003D2h Port P8 Direction Register 0003D3h Port P9 Direction Register 0003D4h Port P10 Register 0003D5h Port P11 Register 0003D6h Port P10 Direction Register 0003D7h Port P11 Direction Register 0003D8h Port P12 Register 0003D9h Port P13 Register 0003DAh Port P12 Direction Register 0003DBh Port P13 Direction Register 0003DCh Port P14 Register 0003DDh Port P15 Register 0003DEh Port P14 Direction Register 0003DFh Port P15 Direction Register X: Undefined Blanks are reserved. No access is allowed. P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 P11 PD10 PD11 P12 P13 PD12 PD13 P14 P15 PD14 PD15 XXh XXh 0000 0000b 0000 0000b XXh XXh 0000 0000b 0000 0000b XXh XXh 0000 0000b 0000 0000b XXh XXh 0000 0000b 0000 0000b XXh XXh 00X0 0000b 0000 0000b XXh XXh 0000 0000b XXX0 0000b XXh XXh 0000 0000b 0000 0000b XXh XXh X000 0000b 0000 0000b REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 43 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.17 SFR List (17) Symbol Reset Value Address Register 0003E0h 0003E1h 0003E2h 0003E3h 0003E4h 0003E5h 0003E6h 0003E7h 0003E8h 0003E9h 0003EAh 0003EBh 0003ECh 0003EDh 0003EEh 0003EFh 0003F0h Pull-up Control Register 0 0003F1h Pull-up Control Register 1 0003F2h Pull-up Control Register 2 0003F3h Pull-up Control Register 3 0003F4h Pull-up Control Register 4 0003F5h 0003F6h 0003F7h 0003F8h 0003F9h 0003FAh 0003FBh 0003FCh 0003FDh 0003FEh 0003FFh Port Control Register X: Undefined Blanks are reserved. No access is allowed. PUR0 PUR1 PUR2 PUR3 PUR4 0000 0000b XXXX X0XXb 000X XXXXb 0000 0000b XXXX 0000b PCR 0XXX XXX0b REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 44 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.18 SFR List (18) Symbol FMR0 FMSR0 Reset Value 0X01 XX00b 1000 0000b Address Register 040000h Flash Memory Control Register 0 040001h Flash Memory Status Register 0 040002h 040003h 040004h 040005h 040006h 040007h 040008h Flash Register Protection Unlock Register 0 040009h Flash Memory Control Register 1 04000Ah Block Protect Bit Monitor Register 0 04000Bh Block Protect Bit Monitor Register 1 04000Ch 04000Dh 04000Eh 04000Fh 040010h 040011h Block Protect Bit Monitor Register 2 040012h 040013h 040014h 040015h 040016h 040017h 040018h 040019h 04001Ah 04001Bh 04001Ch 04001Dh 04001Eh 04001Fh 040020h PLL Control Register 0 040021h PLL Control Register 1 040022h 040023h 040024h 040025h 040026h 040027h 040028h 040029h 04002Ah 04002Bh 04002Ch 04002Dh 04002Eh 04002Fh X: Undefined Blanks are reserved. No access is allowed. Note: 1. The status of protect bit of each block in flash memory is reflected. FPR0 FMR1 FBPM0 FBPM1 00h 0000 0010b ??X? ????b (1) XXX? ????b (1) FBPM2 ???? ????b (1) PLC0 PLC1 0000 0001b 0001 1111b REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 45 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.19 SFR List (19) Symbol Reset Value Address Register 040030h to 04003Fh 040040h 040041h 040042h 040043h 040044h Processor Mode Register 0 (1) PM0 1000 0000b (CNVSS pin = Low) 0000 0011b (CNVSS pin = High) 0000 1000b 0010 0000b 00h XXXX X000b 0000 0000b 00h 040045h 040046h System Clock Control Register 0 040047h System Clock Control Register 1 040048h Processor Mode Register 3 040049h 04004Ah Protect Register 04004Bh 04004Ch Protect Register 3 04004Dh Oscillator Stop Detection Register 04004Eh 04004Fh 040050h 040051h 040052h 040053h Processor Mode Register 2 040054h Chip Select Output Pin Setting Register 0 040055h Chip Select Output Pin Setting Register 1 040056h Chip Select Output Pin Setting Register 2 040057h 040058h 040059h 04005Ah Low Speed Mode Clock Control Register 04005Bh 04005Ch 04005Dh 04005Eh 04005Fh 040060h Voltage Regulator Control Register 040061h 040062h Low Voltage Detector Control Register 040063h 040064h Detection Voltage Configuration Register 040065h 040066h 040067h 040068h to 040093h X: Undefined Blanks are reserved. No access is allowed. CM0 CM1 PM3 PRCR PRCR3 CM2 PM2 CSOP0 CSOP1 CSOP2 00h 1000 XXXXb 01X0 XXXXb XXXX 0000b CM3 XXXX XX00b VRCR LVDC DVCR 0000 0000b 0000 XX00b 0000 XXXXb Note: 1. The value in the PM0 register remains unchanged even after a software reset or watchdog timer reset. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 46 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.20 SFR List (20) Symbol Reset Value Address Register 040094h 040095h 040096h 040097h Three-phase Output Buffer Control Register 040098h Input Function Select Register 0 040099h Input Function Select Register 1 04009Ah Input Function Select Register 2 04009Bh Input Function Select Register 3 04009Ch 04009Dh 04009Eh 04009Fh 0400A0h Port P0_0 Function Select Register 0400A1h Port P1_0 Function Select Register 0400A2h Port P0_1 Function Select Register 0400A3h Port P1_1 Function Select Register 0400A4h Port P0_2 Function Select Register 0400A5h Port P1_2 Function Select Register 0400A6h Port P0_3 Function Select Register 0400A7h Port P1_3 Function Select Register 0400A8h Port P0_4 Function Select Register 0400A9h Port P1_4 Function Select Register 0400AAh Port P0_5 Function Select Register 0400ABh Port P1_5 Function Select Register 0400ACh Port P0_6 Function Select Register 0400ADh Port P1_6 Function Select Register 0400AEh Port P0_7 Function Select Register 0400AFh Port P1_7 Function Select Register 0400B0h Port P2_0 Function Select Register 0400B1h Port P3_0 Function Select Register 0400B2h Port P2_1 Function Select Register 0400B3h Port P3_1 Function Select Register 0400B4h Port P2_2 Function Select Register 0400B5h Port P3_2 Function Select Register 0400B6h Port P2_3 Function Select Register 0400B7h Port P3_3 Function Select Register 0400B8h Port P2_4 Function Select Register 0400B9h Port P3_4 Function Select Register 0400BAh Port P2_5 Function Select Register 0400BBh Port P3_5 Function Select Register 0400BCh Port P2_6 Function Select Register 0400BDh Port P3_6 Function Select Register 0400BEh Port P2_7 Function Select Register 0400BFh Port P3_7 Function Select Register X: Undefined Blanks are reserved. No access is allowed. IOBC IFS0 IFS1 IFS2 IFS3 0XXX XXXXb X000 0000b XXXX X0X0b 0000 00X0b XXXX XX00b P0_0S P1_0S P0_1S P1_1S P0_2S P1_2S P0_3S P1_3S P0_4S P1_4S P0_5S P1_5S P0_6S P1_6S P0_7S P1_7S P2_0S P3_0S P2_1S P3_1S P2_2S P3_2S P2_3S P3_3S P2_4S P3_4S P2_5S P3_5S P2_6S P3_6S P2_7S P3_7S 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b 0XXX X000b XXXX X000b REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 47 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.21 SFR List (21) Symbol P4_0S P5_0S P4_1S P5_1S P4_2S P5_2S P4_3S P5_3S P4_4S P5_4S P4_5S P5_5S P4_6S P5_6S P4_7S P5_7S P6_0S P7_0S P6_1S P7_1S P6_2S P7_2S P6_3S P7_3S P6_4S P7_4S P6_5S P7_5S P6_6S P7_6S P6_7S P7_7S P8_0S P9_0S P8_1S P9_1S P8_2S P9_2S P8_3S P9_3S P8_4S P9_4S P9_5S P8_6S P9_6S P8_7S P9_7S Reset Value X0XX X000b XXXX X000b X0XX X000b XXXX X000b X0XX X000b XXXX X000b X0XX X000b XXXX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b X0XX X000b 00XX X000b XXXX X000b 00XX X000b 00XX X000b XXXX X000b 00XX X000b XXXX X000b X0XX X000b Address Register 0400C0h Port P4_0 Function Select Register 0400C1h Port P5_0 Function Select Register 0400C2h Port P4_1 Function Select Register 0400C3h Port P5_1 Function Select Register 0400C4h Port P4_2 Function Select Register 0400C5h Port P5_2 Function Select Register 0400C6h Port P4_3 Function Select Register 0400C7h Port P5_3 Function Select Register 0400C8h Port P4_4 Function Select Register 0400C9h Port P5_4 Function Select Register 0400CAh Port P4_5 Function Select Register 0400CBh Port P5_5 Function Select Register 0400CCh Port P4_6 Function Select Register 0400CDh Port P5_6 Function Select Register 0400CEh Port P4_7 Function Select Register 0400CFh Port P5_7 Function Select Register 0400D0h Port P6_0 Function Select Register 0400D1h Port P7_0 Function Select Register 0400D2h Port P6_1 Function Select Register 0400D3h Port P7_1 Function Select Register 0400D4h Port P6_2 Function Select Register 0400D5h Port P7_2 Function Select Register 0400D6h Port P6_3 Function Select Register 0400D7h Port P7_3 Function Select Register 0400D8h Port P6_4 Function Select Register 0400D9h Port P7_4 Function Select Register 0400DAh Port P6_5 Function Select Register 0400DBh Port P7_5 Function Select Register 0400DCh Port P6_6 Function Select Register 0400DDh Port P7_6 Function Select Register 0400DEh Port P6_7 Function Select Register 0400DFh Port P7_7 Function Select Register 0400E0h Port P8_0 Function Select Register 0400E1h Port P9_0 Function Select Register 0400E2h Port P8_1 Function Select Register 0400E3h Port P9_1 Function Select Register 0400E4h Port P8_2 Function Select Register 0400E5h Port P9_2 Function Select Register 0400E6h Port P8_3 Function Select Register 0400E7h Port P9_3 Function Select Register 0400E8h Port P8_4 Function Select Register 0400E9h Port P9_4 Function Select Register 0400EAh 0400EBh Port P9_5 Function Select Register 0400ECh Port P8_6 Function Select Register 0400EDh Port P9_6 Function Select Register 0400EEh Port P8_7 Function Select Register 0400EFh Port P9_7 Function Select Register X: Undefined Blanks are reserved. No access is allowed. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 48 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.22 SFR List (22) Symbol P10_0S P11_0S P10_1S P11_1S P10_2S P11_2S P10_3S P11_3S P10_4S P11_4S P10_5S P10_6S P10_7S P12_0S P13_0S P12_1S P13_1S P12_2S P13_2S P12_3S P13_3S P12_4S P13_4S P12_5S P13_5S P12_6S P13_6S P12_7S P13_7S P15_0S P15_1S P15_2S P14_3S P15_3S P14_4S P15_4S P14_5S P15_5S P14_6S P15_6S P15_7S Reset Value 0XXX X000b X0XX X000b 0XXX X000b X0XX X000b 0XXX X000b X0XX X000b 0XXX X000b X0XX X000b 0XXX X000b XXXX X000b 0XXX X000b 0XXX X000b 0XXX X000b X0XX X000b XXXX X000b X0XX X000b XXXX X000b X0XX X000b XXXX X000b X0XX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b 00XX X000b 00XX X000b 00XX X000b XXXX X000b 00XX X000b XXXX X000b 00XX X000b XXXX X000b 00XX X000b XXXX X000b 00XX X000b 00XX X000b Address Register 0400F0h Port P10_0 Function Select Register 0400F1h Port P11_0 Function Select Register 0400F2h Port P10_1 Function Select Register 0400F3h Port P11_1 Function Select Register 0400F4h Port P10_2 Function Select Register 0400F5h Port P11_2 Function Select Register 0400F6h Port P10_3 Function Select Register 0400F7h Port P11_3 Function Select Register 0400F8h Port P10_4 Function Select Register 0400F9h Port P11_4 Function Select Register 0400FAh Port P10_5 Function Select Register 0400FBh 0400FCh Port P10_6 Function Select Register 0400FDh 0400FEh Port P10_7 Function Select Register 0400FFh 040100h Port P12_0 Function Select Register 040101h Port P13_0 Function Select Register 040102h Port P12_1 Function Select Register 040103h Port P13_1 Function Select Register 040104h Port P12_2 Function Select Register 040105h Port P13_2 Function Select Register 040106h Port P12_3 Function Select Register 040107h Port P13_3 Function Select Register 040108h Port P12_4 Function Select Register 040109h Port P13_4 Function Select Register 04010Ah Port P12_5 Function Select Register 04010Bh Port P13_5 Function Select Register 04010Ch Port P12_6 Function Select Register 04010Dh Port P13_6 Function Select Register 04010Eh Port P12_7 Function Select Register 04010Fh Port P13_7 Function Select Register 040110h 040111h Port P15_0 Function Select Register 040112h 040113h Port P15_1 Function Select Register 040114h 040115h Port P15_2 Function Select Register 040116h Port P14_3 Function Select Register 040117h Port P15_3 Function Select Register 040118h Port P14_4 Function Select Register 040119h Port P15_4 Function Select Register 04011Ah Port P14_5 Function Select Register 04011Bh Port P15_5 Function Select Register 04011Ch Port P14_6 Function Select Register 04011Dh Port P15_6 Function Select Register 04011Eh 04011Fh Port P15_7 Function Select Register X: Undefined Blanks are reserved. No access is allowed. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 49 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.23 SFR List (23) Symbol Reset Value Address Register 040120h to 04403Fh 044040h 044041h 044042h 044043h 044044h 044045h 044046h 044047h 044048h 044049h 04404Ah 04404Bh 04404Ch 04404Dh 04404Eh Watchdog Timer Start Register 04404Fh Watchdog Timer Control Register 044050h 044051h 044052h 044053h 044054h 044055h 044056h 044057h 044058h 044059h 04405Ah 04405Bh 04405Ch 04405Dh 04405Eh 04405Fh Protect Register 2 X: Undefined Blanks are reserved. No access is allowed. WDTS WDC XXXX XXXXb 000X XXXXb PRCR2 0XXX XXXXb REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 50 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.24 SFR List (24) Symbol Reset Value Address Register 044060h 044061h 044062h 044063h 044064h 044065h 044066h 044067h 044068h 044069h 04406Ah 04406Bh 04406Ch 04406Dh External Interrupt Source Select Register 1 04406Eh 04406Fh External Interrupt Source Select Register 0 044070h DMA0 Request Source Select Register 2 044071h DMA1 Request Source Select Register 2 044072h DMA2 Request Source Select Register 2 044073h DMA3 Request Source Select Register 2 044074h 044075h 044076h 044077h 044078h DMA0 Request Source Select Register 044079h DMA1 Request Source Select Register 04407Ah DMA2 Request Source Select Register 04407Bh DMA3 Request Source Select Register 04407Ch 04407Dh Wake-up IPL Setting Register 2 04407Eh 04407Fh Wake-up IPL Setting Register 1 044080h 044081h 044082h 044083h 044084h 044085h 044086h 044087h 044088h 044089h 04408Ah 04408Bh 04408Ch 04408Dh 04408Eh 04408Fh X: Undefined Blanks are reserved. No access is allowed. IFSR1 IFSR0 DM0SL2 DM1SL2 DM2SL2 DM3SL2 X0XX X000b 0000 0000b XX00 0000b XX00 0000b XX00 0000b XX00 0000b DM0SL DM1SL DM2SL DM3SL RIPL2 RIPL1 XXX0 0000b XXX0 0000b XXX0 0000b XXX0 0000b XX0X 0000b XX0X 0000b REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 51 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.25 Address 044090h to 0443FFh 044400h 044401h 044402h 044403h 044404h 044405h SFR List (25) Register Symbol Reset Value I2C Bus Transmit/Receive Shift Register I2CTRSR I2CSAR I2CCR0 I2CCCR I2CSSCR I2CCR1 I2CCR2 I2CSR XXh 00h 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b I2C Bus Slave Address Register I2C Bus Control Register 0 I2C Bus Clock Control Register I2C Bus START Condition/STOP Condition Control Register 044406h I2C Bus Control Register 1 044407h I2C Bus Control Register 2 044408h I2C Bus Status Register 044409h 04440Ah 04440Bh 04440Ch 04440Dh 04440Eh 04440Fh 044410h I2C Bus Mode Register 044411h 044412h 044413h 044414h 044415h 044416h 044417h 044418h 044419h 04441Ah 04441Bh 04441Ch 04441Dh 04441Eh 04441Fh 044420h to 0467FFh X: Undefined Blanks are reserved. No access is allowed. I2CMR 0000 0000b REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 52 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.26 SFR List (26) Symbol Reset Value Address Register 046800h to 0477FFh 047800h CAN1 Mailbox 0: Message Identifier 047801h 047802h 047803h 047804h 047805h CAN1 Mailbox 0: Data Length 047806h CAN1 Mailbox 0: Data Field 047807h 047808h 047809h 04780Ah 04780Bh 04780Ch 04780Dh 04780Eh CAN1 Mailbox 0: Time Stamp 04780Fh 047810h CAN1 Mailbox 1: Message Identifier 047811h 047812h 047813h 047814h 047815h CAN1 Mailbox 1: Data Length 047816h CAN1 Mailbox 1: Data Field 047817h 047818h 047819h 04781Ah 04781Bh 04781Ch 04781Dh 04781Eh CAN1 Mailbox 1: Time Stamp 04781Fh 047820h CAN1 Mailbox 2: Message Identifier 047821h 047822h 047823h 047824h 047825h CAN1 Mailbox 2: Data Length 047826h CAN1 Mailbox 2: Data Field 047827h 047828h 047829h 04782Ah 04782Bh 04782Ch 04782Dh 04782Eh CAN1 Mailbox 2: Time Stamp 04782Fh X: Undefined Blanks are reserved. No access is allowed. C1MB0 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C1MB1 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C1MB2 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 53 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.27 SFR List (27) Symbol C1MB3 Reset Value XXXX XXXXh Address Register 047830h CAN1 Mailbox 3: Message Identifier 047831h 047832h 047833h 047834h 047835h CAN1 Mailbox 3: Data Length 047836h CAN1 Mailbox 3: Data Field 047837h 047838h 047839h 04783Ah 04783Bh 04783Ch 04783Dh 04783Eh CAN1 Mailbox 3: Time Stamp 04783Fh 047840h CAN1 Mailbox 4: Message Identifier 047841h 047842h 047843h 047844h 047845h CAN1 Mailbox 4: Data Length 047846h CAN1 Mailbox 4: Data Field 047847h 047848h 047849h 04784Ah 04784Bh 04784Ch 04784Dh 04784Eh CAN1 Mailbox 4: Time Stamp 04784Fh 047850h CAN1 Mailbox 5: Message Identifier 047851h 047852h 047853h 047854h 047855h CAN1 Mailbox 5: Data Length 047856h CAN1 Mailbox 5: Data Field 047857h 047858h 047859h 04785Ah 04785Bh 04785Ch 04785Dh 04785Eh CAN1 Mailbox 5: Time Stamp 04785Fh X: Undefined Blanks are reserved. No access is allowed. XXh XXXX XXXX XXXX XXXXh XXXXh C1MB4 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C1MB5 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 54 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.28 SFR List (28) Symbol C1MB6 Reset Value XXXX XXXXh Address Register 047860h CAN1 Mailbox 6: Message Identifier 047861h 047862h 047863h 047864h 047865h CAN1 Mailbox 6: Data Length 047866h CAN1 Mailbox 6: Data Field 047867h 047868h 047869h 04786Ah 04786Bh 04786Ch 04786Dh 04786Eh CAN1 Mailbox 6: Time Stamp 04786Fh 047870h CAN1 Mailbox 7: Message Identifier 047871h 047872h 047873h 047874h 047875h CAN1 Mailbox 7: Data Length 047876h CAN1 Mailbox 7: Data Field 047877h 047878h 047879h 04787Ah 04787Bh 04787Ch 04787Dh 04787Eh CAN1 Mailbox 7: Time Stamp 04787Fh 047880h CAN1 Mailbox 8: Message Identifier 047881h 047882h 047883h 047884h 047885h CAN1 Mailbox 8: Data Length 047886h CAN1 Mailbox 8: Data Field 047887h 047888h 047889h 04788Ah 04788Bh 04788Ch 04788Dh 04788Eh CAN1 Mailbox 8: Time Stamp 04788Fh X: Undefined Blanks are reserved. No access is allowed. XXh XXXX XXXX XXXX XXXXh XXXXh C1MB7 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C1MB8 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 55 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.29 SFR List (29) Symbol C1MB9 Reset Value XXXX XXXXh Address Register 047890h CAN1 Mailbox 9: Message Identifier 047891h 047892h 047893h 047894h 047895h CAN1 Mailbox 9: Data Length 047896h CAN1 Mailbox 9: Data Field 047897h 047898h 047899h 04789Ah 04789Bh 04789Ch 04789Dh 04789Eh CAN1 Mailbox 9: Time Stamp 04789Fh 0478A0h CAN1 Mailbox 10: Message Identifier 0478A1h 0478A2h 0478A3h 0478A4h 0478A5h CAN1 Mailbox 10: Data Length 0478A6h CAN1 Mailbox 10: Data Field 0478A7h 0478A8h 0478A9h 0478AAh 0478ABh 0478ACh 0478ADh 0478AEh CAN1 Mailbox 10: Time Stamp 0478AFh 0478B0h CAN1 Mailbox 11: Message Identifier 0478B1h 0478B2h 0478B3h 0478B4h 0478B5h CAN1 Mailbox 11: Data Length 0478B6h CAN1 Mailbox 11: Data Field 0478B7h 0478B8h 0478B9h 0478BAh 0478BBh 0478BCh 0478BDh 0478BEh CAN1 Mailbox 11: Time Stamp 0478BFh X: Undefined Blanks are reserved. No access is allowed. XXh XXXX XXXX XXXX XXXXh XXXXh C1MB10 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C1MB11 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 56 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.30 SFR List (30) Symbol C1MB12 Reset Value XXXX XXXXh Address Register 0478C0h CAN1 Mailbox 12: Message Identifier 0478C1h 0478C2h 0478C3h 0478C4h 0478C5h CAN1 Mailbox 12: Data Length 0478C6h CAN1 Mailbox 12: Data Field 0478C7h 0478C8h 0478C9h 0478CAh 0478CBh 0478CCh 0478CDh 0478CEh CAN1 Mailbox 12: Time Stamp 0478CFh 0478D0h CAN1 Mailbox 13: Message Identifier 0478D1h 0478D2h 0478D3h 0478D4h 0478D5h CAN1 Mailbox 13: Data Length 0478D6h CAN1 Mailbox 13: Data Field 0478D7h 0478D8h 0478D9h 0478DAh 0478DBh 0478DCh 0478DDh 0478DEh CAN1 Mailbox 13: Time Stamp 0478DFh 0478E0h CAN1 Mailbox 14: Message Identifier 0478E1h 0478E2h 0478E3h 0478E4h 0478E5h CAN1 Mailbox 14: Data Length 0478E6h CAN1 Mailbox 14: Data Field 0478E7h 0478E8h 0478E9h 0478EAh 0478EBh 0478ECh 0478EDh 0478EEh CAN1 Mailbox 14: Time Stamp 0478EFh X: Undefined Blanks are reserved. No access is allowed. XXh XXXX XXXX XXXX XXXXh XXXXh C1MB13 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C1MB14 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 57 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.31 SFR List (31) Symbol C1MB15 Reset Value XXXX XXXXh Address Register 0478F0h CAN1 Mailbox 15: Message Identifier 0478F1h 0478F2h 0478F3h 0478F4h 0478F5h CAN1 Mailbox 15: Data Length 0478F6h CAN1 Mailbox 15: Data Field 0478F7h 0478F8h 0478F9h 0478FAh 0478FBh 0478FCh 0478FDh 0478FEh CAN1 Mailbox 15: Time Stamp 0478FFh 047900h CAN1 Mailbox 16: Message Identifier 047901h 047902h 047903h 047904h 047905h CAN1 Mailbox 16: Data Length 047906h CAN1 Mailbox 16: Data Field 047907h 047908h 047909h 04790Ah 04790Bh 04790Ch 04790Dh 04790Eh CAN1 Mailbox 16: Time Stamp 04790Fh 047910h CAN1 Mailbox 17: Message Identifier 047911h 047912h 047913h 047914h 047915h CAN1 Mailbox 17: Data Length 047916h CAN1 Mailbox 17: Data Field 047917h 047918h 047919h 04791Ah 04791Bh 04791Ch 04791Dh 04791Eh CAN1 Mailbox 17: Time Stamp 04791Fh X: Undefined Blanks are reserved. No access is allowed. XXh XXXX XXXX XXXX XXXXh XXXXh C1MB16 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C1MB17 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 58 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.32 SFR List (32) Symbol C1MB18 Reset Value XXXX XXXXh Address Register 047920h CAN1 Mailbox 18: Message Identifier 047921h 047922h 047923h 047924h 047925h CAN1 Mailbox 18: Data Length 047926h CAN1 Mailbox 18: Data Field 047927h 047928h 047929h 04792Ah 04792Bh 04792Ch 04792Dh 04792Eh CAN1 Mailbox18: Time Stamp 04792Fh 047930h CAN1 Mailbox 19: Message Identifier 047931h 047932h 047933h 047934h 047935h CAN1 Mailbox 19: Data Length 047936h CAN1 Mailbox 19: Data Field 047937h 047938h 047939h 04793Ah 04793Bh 04793Ch 04793Dh 04793Eh CAN1 Mailbox 19: Time Stamp 04793Fh 047940h CAN1 Mailbox 20: Message Identifier 047941h 047942h 047943h 047944h 047945h CAN1 Mailbox 20: Data Length 047946h CAN1 Mailbox 20: Data Field 047947h 047948h 047949h 04794Ah 04794Bh 04794Ch 04794Dh 04794Eh CAN1 Mailbox 20: Time Stamp 04794Fh X: Undefined Blanks are reserved. No access is allowed. XXh XXXX XXXX XXXX XXXXh XXXXh C1MB19 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C1MB20 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 59 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.33 SFR List (33) Symbol C1MB21 Reset Value XXXX XXXXh Address Register 047950h CAN1 Mailbox 21: Message Identifier 047951h 047952h 047953h 047954h 047955h CAN1 Mailbox 21: Data Length 047956h CAN1 Mailbox 21: Data Field 047957h 047958h 047959h 04795Ah 04795Bh 04795Ch 04795Dh 04795Eh CAN1 Mailbox 21: Time Stamp 04795Fh 047960h CAN1 Mailbox 22: Identifier 047961h 047962h 047963h 047964h 047965h CAN1 Mailbox 22: Data Length 047966h CAN1 Mailbox 22: Data Field 047967h 047968h 047969h 04796Ah 04796Bh 04796Ch 04796Dh 04796Eh CAN1 Mailbox 22: Time Stamp 04796Fh 047970h CAN1 Mailbox 23: Message Identifier 047971h 047972h 047973h 047974h 047975h CAN1 Mailbox 23: Data Length 047976h CAN1 Mailbox 23: Data Field 047977h 047978h 047979h 04797Ah 04797Bh 04797Ch 04797Dh 04797Eh CAN1 Mailbox 23: Time Stamp 04797Fh X: Undefined Blanks are reserved. No access is allowed. XXh XXXX XXXX XXXX XXXXh XXXXh C1MB22 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C1MB23 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 60 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.34 SFR List (34) Symbol C1MB24 Reset Value XXXX XXXXh Address Register 047980h CAN1 Mailbox 24: Message Identifier 047981h 047982h 047983h 047984h 047985h CAN1 Mailbox 24: Data Length 047986h CAN1 Mailbox 24: Data Field 047987h 047988h 047989h 04798Ah 04798Bh 04798Ch 04798Dh 04798Eh CAN1 Mailbox 24: Time Stamp 04798Fh 047990h CAN1 Mailbox 25: Message Identifier 047991h 047992h 047993h 047994h 047995h CAN1 Mailbox 25: Data Length 047996h CAN1 Mailbox 25: Data Field 047997h 047998h 047999h 04799Ah 04799Bh 04799Ch 04799Dh 04799Eh CAN1 Mailbox 25: Time Stamp 04799Fh 0479A0h CAN1 Mailbox 26: Message Identifier 0479A1h 0479A2h 0479A3h 0479A4h 0479A5h CAN1 Mailbox 26: Data Length 0479A6h CAN1 Mailbox 26: Data Field 0479A7h 0479A8h 0479A9h 0479AAh 0479ABh 0479ACh 0479ADh 0479AEh CAN1 Mailbox 26: Time Stamp 0479AFh X: Undefined Blanks are reserved. No access is allowed. XXh XXXX XXXX XXXX XXXXh XXXXh C1MB25 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C1MB26 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 61 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.35 SFR List (35) Symbol C1MB27 Reset Value XXXX XXXXh Address Register 0479B0h CAN1 Mailbox 27: Message Identifier 0479B1h 0479B2h 0479B3h 0479B4h 0479B5h CAN1 Mailbox 27: Data Length 0479B6h CAN1 Mailbox 27: Data Field 0479B7h 0479B8h 0479B9h 0479BAh 0479BBh 0479BCh 0479BDh 0479BEh CAN1 Mailbox 27: Time Stamp 0479BFh 0479C0h CAN1 Mailbox 28: Message Identifier 0479C1h 0479C2h 0479C3h 0479C4h 0479C5h CAN1 Mailbox 28: Data Length 0479C6h CAN1 Mailbox 28: Data Field 0479C7h 0479C8h 0479C9h 0479CAh 0479CBh 0479CCh 0479CDh 0479CEh CAN1 Mailbox 28: Time Stamp 0479CFh 0479D0h CAN1 Mailbox 29: Message Identifier 0479D1h 0479D2h 0479D3h 0479D4h 0479D5h CAN1 Mailbox 29: Data Length 0479D6h CAN1 Mailbox 29: Data Field 0479D7h 0479D8h 0479D9h 0479DAh 0479DBh 0479DCh 0479DDh 0479DEh CAN1 Mailbox 29: Time Stamp 0479DFh X: Undefined Blanks are reserved. No access is allowed. XXh XXXX XXXX XXXX XXXXh XXXXh C1MB28 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C1MB29 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 62 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.36 SFR List (36) Symbol C1MB30 Reset Value XXXX XXXXh Address Register 0479E0h CAN1 Mailbox 30: Message Identifier 0479E1h 0479E2h 0479E3h 0479E4h 0479E5h CAN1 Mailbox 30: Data Length 0479E6h CAN1 Mailbox 30: Data Field 0479E7h 0479E8h 0479E9h 0479EAh 0479EBh 0479ECh 0479EDh 0479EEh CAN1 Mailbox 30: Time Stamp 0479EFh 0479F0h CAN1 Mailbox 31: Message Identifier 0479F1h 0479F2h 0479F3h 0479F4h 0479F5h CAN1 Mailbox 31: Data Length 0479F6h CAN1 Mailbox 31: Data Field 0479F7h 0479F8h 0479F9h 0479FAh 0479FBh 0479FCh 0479FDh 0479FEh CAN1 Mailbox 31: Time Stamp 0479FFh 047A00h CAN1 Acceptance Mask Register 0 047A01h 047A02h 047A03h 047A04h CAN1 Acceptance Mask Register 1 047A05h 047A06h 047A07h 047A08h CAN1 Acceptance Mask Register 2 047A09h 047A0Ah 047A0Bh 047A0Ch CAN1 Acceptance Mask Register 3 047A0Dh 047A0Eh 047A0Fh X: Undefined Blanks are reserved. No access is allowed. XXh XXXX XXXX XXXX XXXXh XXXXh C1MB31 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C1MKR0 XXXX XXXXh C1MKR1 XXXX XXXXh C1MKR2 XXXX XXXXh C1MKR3 XXXX XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 63 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.37 SFR List (37) Symbol C1MKR4 Reset Value XXXX XXXXh Address Register 047A10h CAN1 Acceptance Mask Register 4 047A11h 047A12h 047A13h 047A14h CAN1 Acceptance Mask Register 5 047A15h 047A16h 047A17h 047A18h CAN1 Acceptance Mask Register 6 047A19h 047A1Ah 047A1Bh 047A1Ch CAN1 Acceptance Mask Register 7 047A1Dh 047A1Eh 047A1Fh 047A20h CAN1 FIFO Received ID Compare Register 0 047A21h 047A22h 047A23h 047A24h CAN1 FIFO Received ID Compare Register 1 047A25h 047A26h 047A27h 047A28h CAN1 Mask Invalid Register 047A29h 047A2Ah 047A2Bh 047A2Ch CAN1 Mailbox Interrupt Enable Register 047A2Dh 047A2Eh 047A2Fh 047A30h 047A31h 047A32h 047A33h 047A34h 047A35h 047A36h 047A37h 047A38h 047A39h 047A3Ah 047A3Bh 047A3Ch 047A3Dh 047A3Eh 047A3Fh 047A40h to 047B1Fh X: Undefined Blanks are reserved. No access is allowed. C1MKR5 XXXX XXXXh C1MKR6 XXXX XXXXh C1MKR7 XXXX XXXXh C1FIDCR0 XXXX XXXXh C1FIDCR1 XXXX XXXXh C1MKIVLR XXXX XXXXh C1MIER XXXX XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 64 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.38 SFR List (38) Symbol C1MCTL0 C1MCTL1 C1MCTL2 C1MCTL3 C1MCTL4 C1MCTL5 C1MCTL6 C1MCTL7 C1MCTL8 C1MCTL9 C1MCTL10 C1MCTL11 C1MCTL12 C1MCTL13 C1MCTL14 C1MCTL15 C1MCTL16 C1MCTL17 C1MCTL18 C1MCTL19 C1MCTL20 C1MCTL21 C1MCTL22 C1MCTL23 C1MCTL24 C1MCTL25 C1MCTL26 C1MCTL27 C1MCTL28 C1MCTL29 C1MCTL30 C1MCTL31 Reset Value 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Address Register 047B20h CAN1 Message Control Register 0 047B21h CAN1 Message Control Register 1 047B22h CAN1 Message Control Register 2 047B23h CAN1 Message Control Register 3 047B24h CAN1 Message Control Register 4 047B25h CAN1 Message Control Register 5 047B26h CAN1 Message Control Register 6 047B27h CAN1 Message Control Register 7 047B28h CAN1 Message Control Register 8 047B29h CAN1 Message Control Register 9 047B2Ah CAN1 Message Control Register 10 047B2Bh CAN1 Message Control Register 11 047B2Ch CAN1 Message Control Register 12 047B2Dh CAN1 Message Control Register 13 047B2Eh CAN1 Message Control Register 14 047B2Fh CAN1 Message Control Register 15 047B30h CAN1 Message Control Register 16 047B31h CAN1 Message Control Register 17 047B32h CAN1 Message Control Register 18 047B33h CAN1 Message Control Register 19 047B34h CAN1 Message Control Register 20 047B35h CAN1 Message Control Register 21 047B36h CAN1 Message Control Register 22 047B37h CAN1 Message Control Register 23 047B38h CAN1 Message Control Register 24 047B39h CAN1 Message Control Register 25 047B3Ah CAN1 Message Control Register 26 047B3Bh CAN1 Message Control Register 27 047B3Ch CAN1 Message Control Register 28 047B3Dh CAN1 Message Control Register 29 047B3Eh CAN1 Message Control Register 30 047B3Fh CAN1 Message Control Register 31 X: Undefined Blanks are reserved. No access is allowed. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 65 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.39 SFR List (39) Symbol C1CTLR C1STR C1BCR Reset Value 0000 0101b 0000 0000b 0000 0101b 0000 0000b 00 0000h Address Register 047B40h CAN1 Control Register 047B41h 047B42h CAN1 Status Register 047B43h 047B44h CAN1 Bit Configuration Register 047B45h 047B46h 047B47h CAN1 Clock Select Register 047B48h CAN1 Receive FIFO Control Register 047B49h CAN1 Receive FIFO Pointer Control Register 047B4Ah CAN1 Transmit FIFO Control Register 047B4Bh CAN1 Transmit FIFO Pointer Control Register 047B4Ch CAN1 Error Interrupt Enable Register 047B4Dh CAN1 Error Interrupt Factor Judge Register 047B4Eh CAN1 Reception Error Count Register 047B4Fh CAN1 Transmission Error Count Register 047B50h CAN1 Error Code Store Register 047B51h CAN1 Channel Search Support Register 047B52h CAN1 Mailbox Search Status Register 047B53h CAN1 Mailbox Search Mode Register 047B54h CAN1 Time Stamp Register 047B55h 047B56h CAN1 Acceptance Filter Support Register 047B57h 047B58h CAN1 Test Control Register 047B59h 047B5Ah 047B5Bh 047B5Ch 047B5Dh 047B5Eh 047B5Fh 047B60h to 047BFFh X: Undefined Blanks are reserved. No access is allowed. C1CLKR C1RFCR C1RFPCR C1TFCR C1TFPCR C1EIER C1EIFR C1RECR C1TECR C1ECSR C1CSSR C1MSSR C1MSMR C1TSR C1AFSR C1TCR 000X 0000b 1000 0000b XXh 1000 0000b XXh 00h 00h 00h 00h 00h XXh 1000 0000b XXXX XX00b 0000h XXXXh 00h REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 66 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.40 SFR List (40) Symbol C0MB0 Reset Value XXXX XXXXh Address Register 047C00h CAN0 Mailbox 0: Message Identifier 047C01h 047C02h 047C03h 047C04h 047C05h CAN0 Mailbox 0: Data Length 047C06h CAN0 Mailbox 0: Data Field 047C07h 047C08h 047C09h 047C0Ah 047C0Bh 047C0Ch 047C0Dh 047C0Eh CAN0 Mailbox 0: Time Stamp 047C0Fh 047C10h CAN0 Mailbox 1: Message Identifier 047C11h 047C12h 047C13h 047C14h 047C15h CAN0 Mailbox 1: Data Length 047C16h CAN0 Mailbox 1: Data Field 047C17h 047C18h 047C19h 047C1Ah 047C1Bh 047C1Ch 047C1Dh 047C1Eh CAN0 Mailbox 1: Time Stamp 047C1Fh 047C20h CAN0 Mailbox 2: Message Identifier 047C21h 047C22h 047C23h 047C24h 047C25h CAN0 Mailbox 2: Data Length 047C26h CAN0 Mailbox 2: Data Field 047C27h 047C28h 047C29h 047C2Ah 047C2Bh 047C2Ch 047C2Dh 047C2Eh CAN0 Mailbox 2: Time Stamp 047C2Fh X: Undefined Blanks are reserved. No access is allowed. XXh XXXX XXXX XXXX XXXXh XXXXh C0MB1 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C0MB2 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 67 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.41 SFR List (41) Symbol C0MB3 Reset Value XXXX XXXXh Address Register 047C30h CAN0 Mailbox 3: Message Identifier 047C31h 047C32h 047C33h 047C34h 047C35h CAN0 Mailbox 3: Data Length 047C36h CAN0 Mailbox 3: Data Field 047C37h 047C38h 047C39h 047C3Ah 047C3Bh 047C3Ch 047C3Dh 047C3Eh CAN0 Mailbox 3: Time Stamp 047C3Fh 047C40h CAN0 Mailbox 4: Message Identifier 047C41h 047C42h 047C43h 047C44h 047C45h CAN0 Mailbox 4: Data Length 047C46h CAN0 Mailbox 4: Data Field 047C47h 047C48h 047C49h 047C4Ah 047C4Bh 047C4Ch 047C4Dh 047C4Eh CAN0 Mailbox 4: Time Stamp 047C4Fh 047C50h CAN0 Mailbox 5: Message Identifier 047C51h 047C52h 047C53h 047C54h 047C55h CAN0 Mailbox 5: Data Length 047C56h CAN0 Mailbox 5: Data Field 047C57h 047C58h 047C59h 047C5Ah 047C5Bh 047C5Ch 047C5Dh 047C5Eh CAN0 Mailbox 5: Time Stamp 047C5Fh X: Undefined Blanks are reserved. No access is allowed. XXh XXXX XXXX XXXX XXXXh XXXXh C0MB4 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C0MB5 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 68 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.42 SFR List (42) Symbol C0MB6 Reset Value XXXX XXXXh Address Register 047C60h CAN0 Mailbox 6: Message Identifier 047C61h 047C62h 047C63h 047C64h 047C65h CAN0 Mailbox 6: Data Length 047C66h CAN0 Mailbox 6: Data Field 047C67h 047C68h 047C69h 047C6Ah 047C6Bh 047C6Ch 047C6Dh 047C6Eh CAN0 Mailbox 6: Time Stamp 047C6Fh 047C70h CAN0 Mailbox 7: Message Identifier 047C71h 047C72h 047C73h 047C74h 047C75h CAN0 Mailbox 7: Data Length 047C76h CAN0 Mailbox 7: Data Field 047C77h 047C78h 047C79h 047C7Ah 047C7Bh 047C7Ch 047C7Dh 047C7Eh CAN0 Mailbox 7: Time Stamp 047C7Fh 047C80h CAN0 Mailbox 8: Message Identifier 047C81h 047C82h 047C83h 047C84h 047C85h CAN0 Mailbox 8: Data Length 047C86h CAN0 Mailbox 8: Data Field 047C87h 047C88h 047C89h 047C8Ah 047C8Bh 047C8Ch 047C8Dh 047C8Eh CAN0 Mailbox 8: Time Stamp 047C8Fh X: Undefined Blanks are reserved. No access is allowed. XXh XXXX XXXX XXXX XXXXh XXXXh C0MB7 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C0MB8 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 69 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.43 SFR List (43) Symbol C0MB9 Reset Value XXXX XXXXh Address Register 047C90h CAN0 Mailbox 9: Message Identifier 047C91h 047C92h 047C93h 047C94h 047C95h CAN0 Mailbox 9: Data Length 047C96h CAN0 Mailbox 9: Data Field 047C97h 047C98h 047C99h 047C9Ah 047C9Bh 047C9Ch 047C9Dh 047C9Eh CAN0 Mailbox 9: Time Stamp 047C9Fh 047CA0h CAN0 Mailbox 10: Message Identifier 047CA1h 047CA2h 047CA3h 047CA4h 047CA5h CAN0 Mailbox 10: Data Length 047CA6h CAN0 Mailbox 10: Data Field 047CA7h 047CA8h 047CA9h 047CAAh 047CABh 047CACh 047CADh 047CAEh CAN0 Mailbox 10: Time Stamp 047CAFh 047CB0h CAN0 Mailbox 11: Message Identifier 047CB1h 047CB2h 047CB3h 047CB4h 047CB5h CAN0 Mailbox 11: Data Length 047CB6h CAN0 Mailbox 11: Data Field 047CB7h 047CB8h 047CB9h 047CBAh 047CBBh 047CBCh 047CBDh 047CBEh CAN0 Mailbox 11: Time Stamp 047CBFh X: Undefined Blanks are reserved. No access is allowed. XXh XXXX XXXX XXXX XXXXh XXXXh C0MB10 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C0MB11 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 70 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.44 SFR List (44) Symbol C0MB12 Reset Value XXXX XXXXh Address Register 047CC0h CAN0 Mailbox 12: Message Identifier 047CC1h 047CC2h 047CC3h 047CC4h 047CC5h CAN0 Mailbox 12: Data Length 047CC6h CAN0 Mailbox 12: Data Field 047CC7h 047CC8h 047CC9h 047CCAh 047CCBh 047CCCh 047CCDh 047CCEh CAN0 Mailbox 12: Time Stamp 047CCFh 047CD0h CAN0 Mailbox 13: Message Identifier 047CD1h 047CD2h 047CD3h 047CD4h 047CD5h CAN0 Mailbox 13: Data Length 047CD6h CAN0 Mailbox 13: Data Field 047CD7h 047CD8h 047CD9h 047CDAh 047CDBh 047CDCh 047CDDh 047CDEh CAN0 Mailbox 13: Time Stamp 047CDFh 047CE0h CAN0 Mailbox 14: Message Identifier 047CE1h 047CE2h 047CE3h 047CE4h 047CE5h CAN0 Mailbox 14: Data Length 047CE6h CAN0 Mailbox 14: Data Field 047CE7h 047CE8h 047CE9h 047CEAh 047CEBh 047CECh 047CEDh 047CEEh CAN0 Mailbox 14: Time Stamp 047CEFh X: Undefined Blanks are reserved. No access is allowed. XXh XXXX XXXX XXXX XXXXh XXXXh C0MB13 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C0MB14 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 71 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.45 SFR List (45) Symbol C0MB15 Reset Value XXXX XXXXh Address Register 047CF0h CAN0 Mailbox 15: Message Identifier 047CF1h 047CF2h 047CF3h 047CF4h 047CF5h CAN0 Mailbox 15: Data Length 047CF6h CAN0 Mailbox 15: Data Field 047CF7h 047CF8h 047CF9h 047CFAh 047CFBh 047CFCh 047CFDh 047CFEh CAN0 Mailbox 15: Time Stamp 047CFFh 047D00h CAN0 Mailbox 16: Message Identifier 047D01h 047D02h 047D03h 047D04h 047D05h CAN0 Mailbox 16: Data Length 047D06h CAN0 Mailbox 16: Data Field 047D07h 047D08h 047D09h 047D0Ah 047D0Bh 047D0Ch 047D0Dh 047D0Eh CAN0 Mailbox 16: Time Stamp 047D0Fh 047D10h CAN0 Mailbox 17: Message Identifier 047D11h 047D12h 047D13h 047D14h 047D15h CAN0 Mailbox 17: Data Length 047D16h CAN0 Mailbox 17: Data Field 047D17h 047D18h 047D19h 047D1Ah 047D1Bh 047D1Ch 047D1Dh 047D1Eh CAN0 Mailbox 17: Time Stamp 047D1Fh X: Undefined Blanks are reserved. No access is allowed. XXh XXXX XXXX XXXX XXXXh XXXXh C0MB16 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C0MB17 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 72 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.46 SFR List (46) Symbol C0MB18 Reset Value XXXX XXXXh Address Register 047D20h CAN0 Mailbox 18: Message Identifier 047D21h 047D22h 047D23h 047D24h 047D25h CAN0 Mailbox 18: Data Length 047D26h CAN0 Mailbox 18: Data Field 047D27h 047D28h 047D29h 047D2Ah 047D2Bh 047D2Ch 047D2Dh 047D2Eh CAN0 Mailbox 18: Time Stamp 047D2Fh 047D30h CAN0 Mailbox 19: Message Identifier 047D31h 047D32h 047D33h 047D34h 047D35h CAN0 Mailbox 19: Data Length 047D36h CAN0 Mailbox 19: Data Field 047D37h 047D38h 047D39h 047D3Ah 047D3Bh 047D3Ch 047D3Dh 047D3Eh CAN0 Mailbox 19: Time Stamp 047D3Fh 047D40h CAN0 Mailbox 20: Message Identifier 047D41h 047D42h 047D43h 047D44h 047D45h CAN0 Mailbox 20: Data Length 047D46h CAN0 Mailbox 20: Data Field 047D47h 047D48h 047D49h 047D4Ah 047D4Bh 047D4Ch 047D4Dh 047D4Eh CAN0 Mailbox 20: Time Stamp 047D4Fh X: Undefined Blanks are reserved. No access is allowed. XXh XXXX XXXX XXXX XXXXh XXXXh C0MB19 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C0MB20 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 73 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.47 SFR List (47) Symbol C0MB21 Reset Value XXXX XXXXh Address Register 047D50h CAN0 Mailbox 21: Message Identifier 047D51h 047D52h 047D53h 047D54h 047D55h CAN0 Mailbox 21: Data Length 047D56h CAN0 Mailbox 21: Data Field 047D57h 047D58h 047D59h 047D5Ah 047D5Bh 047D5Ch 047D5Dh 047D5Eh CAN0 Mailbox 21: Time Stamp 047D5Fh 047D60h CAN0 Mailbox 22: Message Identifier 047D61h 047D62h 047D63h 047D64h 047D65h CAN0 Mailbox 22: Data Length 047D66h CAN0 Mailbox 22: Data Field 047D67h 047D68h 047D69h 047D6Ah 047D6Bh 047D6Ch 047D6Dh 047D6Eh CAN0 Mailbox 22: Time Stamp 047D6Fh 047D70h CAN0 Mailbox 23: Message Identifier 047D71h 047D72h 047D73h 047D74h 047D75h CAN0 Mailbox 23: Data Length 047D76h CAN0 Mailbox 23: Data Field 047D77h 047D78h 047D79h 047D7Ah 047D7Bh 047D7Ch 047D7Dh 047D7Eh CAN0 Mailbox 23: Time Stamp 047D7Fh X: Undefined Blanks are reserved. No access is allowed. XXh XXXX XXXX XXXX XXXXh XXXXh C0MB22 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C0MB23 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 74 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.48 SFR List (48) Symbol C0MB24 Reset Value XXXX XXXXh Address Register 047D80h CAN0 Mailbox 24: Message Identifier 047D81h 047D82h 047D83h 047D84h 047D85h CAN0 Mailbox 24: Data Length 047D86h CAN0 Mailbox 24: Data Field 047D87h 047D88h 047D89h 047D8Ah 047D8Bh 047D8Ch 047D8Dh 047D8Eh CAN0 Mailbox 24: Time Stamp 047D8Fh 047D90h CAN0 Mailbox 25: Message Identifier 047D91h 047D92h 047D93h 047D94h 047D95h CAN0 Mailbox 25: Data Length 047D96h CAN0 Mailbox 25: Data Field 047D97h 047D98h 047D99h 047D9Ah 047D9Bh 047D9Ch 047D9Dh 047D9Eh CAN0 Mailbox 25: Time Stamp 047D9Fh 047DA0h CAN0 Mailbox 26: Message Identifier 047DA1h 047DA2h 047DA3h 047DA4h 047DA5h CAN0 Mailbox 26: Data Length 047DA6h CAN0 Mailbox 26: Data Field 047DA7h 047DA8h 047DA9h 047DAAh 047DABh 047DACh 047DADh 047DAEh CAN0 Mailbox 26: Time Stamp 047DAFh X: Undefined Blanks are reserved. No access is allowed. XXh XXXX XXXX XXXX XXXXh XXXXh C0MB25 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C0MB26 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 75 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.49 SFR List (49) Symbol C0MB27 Reset Value XXXX XXXXh Address Register 047DB0h CAN0 Mailbox 27: Message Identifier 047DB1h 047DB2h 047DB3h 047DB4h 047DB5h CAN0 Mailbox 27: Data Length 047DB6h CAN0 Mailbox 27: Data Field 047DB7h 047DB8h 047DB9h 047DBAh 047DBBh 047DBCh 047DBDh 047DBEh CAN0 Mailbox 27: Time Stamp 047DBFh 047DC0h CAN0 Mailbox 28: Message Identifier 047DC1h 047DC2h 047DC3h 047DC4h 047DC5h CAN0 Mailbox 28: Data Length 047DC6h CAN0 Mailbox 28: Data Field 047DC7h 047DC8h 047DC9h 047DCAh 047DCBh 047DCCh 047DCDh 047DCEh CAN0 Mailbox 28: Time Stamp 047DCFh 047DD0h CAN0 Mailbox 29: Message Identifier 047DD1h 047DD2h 047DD3h 047DD4h 047DD5h CAN0 Mailbox 29: Data Length 047DD6h CAN0 Mailbox 29: Data Field 047DD7h 047DD8h 047DD9h 047DDAh 047DDBh 047DDCh 047DDDh 047DDEh CAN0 Mailbox 29: Time Stamp 047DDFh X: Undefined Blanks are reserved. No access is allowed. XXh XXXX XXXX XXXX XXXXh XXXXh C0MB28 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C0MB29 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 76 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.50 SFR List (50) Symbol C0MB30 Reset Value XXXX XXXXh Address Register 047DE0h CAN0 Mailbox 30: Message Identifier 047DE1h 047DE2h 047DE3h 047DE4h 047DE5h CAN0 Mailbox 30: Data Length 047DE6h CAN0 Mailbox 30: Data Field 047DE7h 047DE8h 047DE9h 047DEAh 047DEBh 047DECh 047DEDh 047DEEh CAN0 Mailbox 30: Time Stamp 047DEFh 047DF0h CAN0 Mailbox 31: Message Identifier 047DF1h 047DF2h 047DF3h 047DF4h 047DF5h CAN0 Mailbox 31: Data Length 047DF6h CAN0 Mailbox 31: Data Field 047DF7h 047DF8h 047DF9h 047DFAh 047DFBh 047DFCh 047DFDh 047DFEh CAN0 Mailbox 31: Time Stamp 047DFFh 047E00h CAN0 Acceptance Mask Register 0 047E01h 047E02h 047E03h 047E04h CAN0 Acceptance Mask Register 1 047E05h 047E06h 047E07h 047E08h CAN0 Acceptance Mask Register 2 047E09h 047E0Ah 047E0Bh 047E0Ch CAN0 Acceptance Mask Register 3 047E0Dh 047E0Eh 047E0Fh X: Undefined Blanks are reserved. No access is allowed. XXh XXXX XXXX XXXX XXXXh XXXXh C0MB31 XXXX XXXXh XXh XXXX XXXX XXXX XXXXh XXXXh C0MKR0 XXXX XXXXh C0MKR1 XXXX XXXXh C0MKR2 XXXX XXXXh C0MKR3 XXXX XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 77 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.51 SFR List (51) Symbol C0MKR4 Reset Value XXXX XXXXh Address Register 047E10h CAN0 Acceptance Mask Register 4 047E11h 047E12h 047E13h 047E14h CAN0 Acceptance Mask Register 5 047E15h 047E16h 047E17h 047E18h CAN0 Acceptance Mask Register 6 047E19h 047E1Ah 047E1Bh 047E1Ch CAN0 Acceptance Mask Register 7 047E1Dh 047E1Eh 047E1Fh 047E20h CAN0 FIFO Receive ID Compare Register 0 047E21h 047E22h 047E23h 047E24h CAN0 FIFO Receive ID Compare Register 1 047E25h 047E26h 047E27h 047E28h CAN0 Mask Invalid Register 047E29h 047E2Ah 047E2Bh 047E2Ch CAN0 Mailbox Interrupt Enable Register 047E2Dh 047E2Eh 047E2Fh 047E30h 047E31h 047E32h 047E33h 047E34h 047E35h 047E36h 047E37h 047E38h 047E39h 047E3Ah 047E3Bh 047E3Ch 047E3Dh 047E3Eh 047E3Fh 047E40h to 047F1Fh X: Undefined Blanks are reserved. No access is allowed. C0MKR5 XXXX XXXXh C0MKR6 XXXX XXXXh C0MKR7 XXXX XXXXh C0FIDCR0 XXXX XXXXh C0FIDCR1 XXXX XXXXh C0MKIVLR XXXX XXXXh C0MIER XXXX XXXXh REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 78 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.52 SFR List (52) Symbol C0MCTL0 C0MCTL1 C0MCTL2 C0MCTL3 C0MCTL4 C0MCTL5 C0MCTL6 C0MCTL7 C0MCTL8 C0MCTL9 C0MCTL10 C0MCTL11 C0MCTL12 C0MCTL13 C0MCTL14 C0MCTL15 C0MCTL16 C0MCTL17 C0MCTL18 C0MCTL19 C0MCTL20 C0MCTL21 C0MCTL22 C0MCTL23 C0MCTL24 C0MCTL25 C0MCTL26 C0MCTL27 C0MCTL28 C0MCTL29 C0MCTL30 C0MCTL31 Reset Value 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Address Register 047F20h CAN0 Message Control Register 0 047F21h CAN0 Message Control Register 1 047F22h CAN0 Message Control Register 2 047F23h CAN0 Message Control Register 3 047F24h CAN0 Message Control Register 4 047F25h CAN0 Message Control Register 5 047F26h CAN0 Message Control Register 6 047F27h CAN0 Message Control Register 7 047F28h CAN0 Message Control Register 8 047F29h CAN0 Message Control Register 9 047F2Ah CAN0 Message Control Register 10 047F2Bh CAN0 Message Control Register 11 047F2Ch CAN0 Message Control Register 12 047F2Dh CAN0 Message Control Register 13 047F2Eh CAN0 Message Control Register 14 047F2Fh CAN0 Message Control Register 15 047F30h CAN0 Message Control Register 16 047F31h CAN0 Message Control Register 17 047F32h CAN0 Message Control Register 18 047F33h CAN0 Message Control Register 19 047F34h CAN0 Message Control Register 20 047F35h CAN0 Message Control Register 21 047F36h CAN0 Message Control Register 22 047F37h CAN0 Message Control Register 23 047F38h CAN0 Message Control Register 24 047F39h CAN0 Message Control Register 25 047F3Ah CAN0 Message Control Register 26 047F3Bh CAN0 Message Control Register 27 047F3Ch CAN0 Message Control Register 28 047F3Dh CAN0 Message Control Register 29 047F3Eh CAN0 Message Control Register 30 047F3Fh CAN0 Message Control Register 31 X: Undefined Blanks are reserved. No access is allowed. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 79 of 122 R32C/118 Group 4. Special Function Registers (SFRs) Table 4.53 SFR List (53) Symbol C0CTLR C0STR C0BCR Reset Value 0000 0101b 0000 0000b 0000 0101b 0000 0000b 00 0000h Address Register 047F40h CAN0 Control Register 047F41h 047F42h CAN0 Status Register 047F43h 047F44h CAN0 Bit Configuration Register 047F45h 047F46h 047F47h CAN0 Clock Select Register 047F48h CAN0 Receive FIFO Control Register 047F49h CAN0 Receive FIFO Pointer Control Register 047F4Ah CAN0 Transmit FIFO Control Register 047F4Bh CAN0 Transmit FIFO Pointer Control Register 047F4Ch CAN0 Error Interrupt Enable Register 047F4Dh CAN0 Error Interrupt Factor Judge Register 047F4Eh CAN0 Reception Error Count Register 047F4Fh CAN0 Transmission Error Count Register 047F50h CAN0 Error Code Store Register 047F51h CAN0 Channel Search Support Register 047F52h CAN0 Mailbox Search Status Register 047F53h CAN0 Mailbox Search Mode Register 047F54h CAN0 Time Stamp Register 047F55h 047F56h CAN0 Acceptance Filter Support Register 047F57h 047F58h CAN0 Test Control Register 047F59h 047F5Ah 047F5Bh 047F5Ch 047F5Dh 047F5Eh 047F5Fh 047F60h to 047FFFh 048000h to 04FFFFh X: Undefined Blanks are reserved. No access is allowed. C0CLKR C0RFCR C0RFPCR C0TFCR C0TFPCR C0EIER C0EIFR C0RECR C0TECR C0ECSR C0CSSR C0MSSR C0MSMR C0TSR C0AFSR C0TCR 000X 0000b 1000 0000b XXh 1000 0000b XXh 00h 00h 00h 00h 00h XXh 1000 0000b XXXX XX00b 0000h XXXXh 00h REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 80 of 122 R32C/118 Group 5. Electrical Characteristics 5. Electrical Characteristics Absolute Maximum Ratings (1) Table 5.1 Symbol VCC AVCC VI Supply voltage Characteristic Analog supply voltage Input voltage XIN, RESET, CNVSS, NSD, VREF, P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P5_0 to P5_3, P8_4 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_1, P14_3 to P14_6, P15_0 to P15_7 (2) P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_3 Condition VCC = AVCC VCC = AVCC Value -0.3 to 6.0 -0.3 to 6.0 Unit V V -0.3 to VCC + 0.3 V -0.3 to 6.0 V VO Output voltage XOUT, P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_3 to P14_6, P15_0 to P15_7 (2) Ta = 25°C -0.3 to VCC + 0.3 V Pd — Tstg Power consumption Operating temperature range Storage temperature range 500 -40 to 85 -65 to 150 mW °C °C Notes: 1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated as input pin in the 100-pin package. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 81 of 122 R32C/118 Group 5. Electrical Characteristics Table 5.2 Operating Conditions (1/5) (1) Symbol VCC AVCC VREF VSS AVSS VIH Digital supply voltage Analog supply voltage Reference voltage Digital ground voltage Analog ground voltage Characteristic Value Min. 3.0 3.0 0 0 0.05 Typ. 5.0 VCC Max. 5.5 VCC Unit V V V V V V/ms dVCC/dt VCC ramp up rate (VCC < 2.0 V) High level input voltage XIN, RESET, CNVSS, NSD, P2_0 to P2_7, P3_0 to P3_7, P5_0 to P5_3, P8_4 to P8_7 (2), P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P14_1, P14_3 to P14_6, P15_0 to P15_7 (3) P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_3 0.8 × VCC VCC V 0.8 × VCC 6.0 VCC V P0_0 to P0_7, P1_0 to P1_7, P12_0 to P12_7, 0.8 × VCC P13_0 to P13_7 (in single-chip mode) (3) P0_0 to P0_7, P1_0 to P1_7, P12_0 to P12_7, P13_0 to P13_7 (in memory expansion mode 0.5 × VCC or microprocessor mode) (3) VIL Low level input voltage XIN, RESET, CNVSS, NSD, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7 (2), P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P14_1, P14_3 to P14_6, P15_0 to P15_7 (3) P0_0 to P0_7, P1_0 to P1_7, P12_0 to P12_7, P13_0 to P13_7 (in single-chip mode) (3) P0_0 to P0_7, P1_0 to P1_7, P12_0 to P12_7, P13_0 to P13_7 (in memory expansion mode or microprocessor mode) (3) Topr Operating Version N temperature Version D range Version P V VCC V 0 0.2 × VCC V 0 0.2 × VCC V 0 -20 -40 -40 0.16 × VCC 85 85 85 V °C °C °C Notes: 1. The device is operationally guaranteed under these operating conditions. 2. VIH and VIL for P8_7 are specified for P8_7 as a programmable port. These values are not applicable to P8_7 as XCIN. 3. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated as input pin in the 100-pin package. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 82 of 122 R32C/118 Group 5. Electrical Characteristics Table 5.3 Operating Conditions (2/5) (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1) Symbol CVDC Characteristic Decoupling capacitance for voltage regulator Inter-pin voltage: 1.5 V Value (2) Min. Typ. Max. 2.4 10.0 Unit µF Notes: 1. The device is operationally guaranteed under these operating conditions. 2. This value should be satisfied with due consideration of every condition as follows: operating temperature, DC bias, aging, etc. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 83 of 122 R32C/118 Group 5. Electrical Characteristics Table 5.4 Operating Conditions (3/5) (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1) Symbol IOH(peak) High level peak output current (2) Characteristic P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_3 to P14_6, P15_0 to P15_7 (3) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_3 to P14_6, P15_0 to P15_7 (3) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_3 to P14_6, P15_0 to P15_7 (3) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_3 to P14_6, P15_0 to P15_7 (3) Value Min. Typ. Max. Unit -10.0 mA IOH(avg) High level average output current (4) -5.0 mA IOL(peak) Low level peak output current (2) 10.0 mA IOL(avg) Low level average output current (4) 5.0 mA Notes: 1. The device is operationally guaranteed under these operating conditions. 2. The following conditions should be satisfied: • The sum of IOL(peak) of ports P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14, and P15 is 80 mA or less. • The sum of IOL(peak) of ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 is 80 mA or less. • The sum of IOH(peak) of ports P0, P1, P2, and P11 is -40 mA or less. • The sum of IOH(peak) of ports P8_6, P8_7, P9, P10, P14, and P15 is -40 mA or less. • The sum of IOH(peak) of ports P3, P4, P5, P12, and P13 is -40 mA or less. • The sum of IOH(peak) of ports P6, P7, and P8_0 to P8_4 is -40 mA or less. 3. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated as input pin in the 100-pin package. 4. Average value within 100 ms. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 84 of 122 R32C/118 Group 5. Electrical Characteristics Table 5.5 Operating Conditions (4/5) (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1) Symbol f(XIN) f(XRef) f(PLL) f(Base) tc(Base) f(CPU) tc(CPU) f(BCLK) tc(BCLK) f(PER) f(XCIN) Characteristic Main clock oscillator frequency Reference clock frequency PLL clock oscillator frequency Base clock frequency Base clock cycle time CPU operating frequency CPU clock cycle time Peripheral bus clock operating frequency Peripheral bus clock cycle time Peripheral clock source frequency Sub clock oscillator frequency Value Min. 4 2 96 Typ. Max. 16 4 128 50 20 50 20 25 40 32 32.768 62.5 Unit MHz MHz MHz MHz ns MHz ns MHz ns MHz kHz Note: 1. The device is operationally guaranteed under these operating conditions. t c(Base) Base clock (Internal signal) t c(CPU) CPU clock (Internal signal) t c(BCLK) Peripheral bus clock (Internal signal) Figure 5.1 Clock Cycle Time REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 85 of 122 R32C/118 Group 5. Electrical Characteristics Table 5.6 Operating Conditions (5/5) (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) (1) Symbol Vr(VCC) Allowable ripple voltage Characteristic VCC = 5.0 V VCC = 3.0 V VCC = 5.0 V VCC = 3.0 V Value Min. Typ. Max. 0.5 0.3 ±0.3 ±0.3 10 Unit Vp-p Vp-p V/ms V/ms kHz dVr(VCC)/dt Ripple voltage gradient fr(VCC) Allowable ripple frequency Note: 1. The device is operationally guaranteed under these operating conditions. 1 / f r(VCC) VCC V r(VCC) Figure 5.2 Ripple Waveform REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 86 of 122 R32C/118 Group 5. Electrical Characteristics Table 5.7 RAM Electrical Characteristics (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Symbol VRDR Characteristic RAM data retention voltage Measurement condition in stop mode Value Min. 2.0 Typ. Max. Unit V Table 5.8 Flash Memory Electrical Characteristics (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Symbol — — — — Characteristic Programming and erasure endurance of flash Program area memory (1) Data area 4-word program time Lock bit-program time Block erasure time Program area Data area Program area Data area 4 Kbyte block 32 Kbyte block 64 Kbyte block Value Min. 1000 10000 150 300 70 140 0.12 0.17 0.20 10 900 1700 500 1000 3.0 3.0 3.0 Typ. Max. Unit times times µs µs µs µs s s s years — Data retention (2) Ta = 55°C (3) Notes: 1. Program/erase definition This value represents the number of erasures per block. If the flash memory is programmed/erased n times, each block can be erased n times. i.e. If 4-word write is performed in 512 different addresses in the block A of 4 Kbyte and then the block is erased, it is considered the programming/erasure is performed just once. However a write in the same address more than once for one erasure is disabled. (overwrite disabled). 2. The data retention time includes the periods when the supply voltage is not applied and no clock is provided. 3. Please contact a Renesas sales office regarding data retention time other than the above. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 87 of 122 R32C/118 Group 5. Electrical Characteristics Table 5.9 Power Supply Circuit Timing Characteristics (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Symbol td(P-R) Characteristic Internal power supply start-up stabilization time after the main power supply is turned on Measurement condition Value Min. Typ. Max. 2 Unit ms t d(P-R) Internal power supply start-up stabilization time after the main power supply is turned on V CC Recommended operating voltage t d(P-R) Supply voltage for internal logic PLL oscillatoroutput waveform Figure 5.3 Power Supply Circuit Timing Table 5.10 Electrical Characteristics of Voltage Regulator for Internal Logic (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Symbol VVDC1 Characteristics Output voltage Measurement condition Value Min. Typ. 1.5 Max. Unit V Table 5.11 Electrical Characteristics of Low Voltage Detector (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Symbol ∆Vdet Characteristics Detected voltage error Measurement condition Value Min. 0 Typ. Max. ±0.3 Unit V V Vdet(R)-Vdet(F) Hysteresis width — td(E-A) Self-consuming current VCC = 5.0 V, low voltage detector enabled 4 150 µA µs Operation start time of low voltage detector REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 88 of 122 R32C/118 Group 5. Electrical Characteristics Table 5.12 Electrical Characteristics of Oscillator (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Symbol fSO(PLL) tLOCK(PLL) tjitter(p-p) f(OCO) Characteristics PLL clock self-oscillation frequency PLL lock time (1) PLL jitter period (p-p) On-chip oscillator frequency Measurement condition Value Min. 35 Typ. 50 Max. 65 1 2.0 62.5 125 250 Unit MHz ms ns kHz Note: 1. This value is applicable only when the main clock oscillation is stable. Table 5.13 Electrical Characteristics of Clock Circuitry (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Symbol trec(WAIT) trec(STOP) Characteristics Measurement condition Value Min. Typ. Max. 225 225 Unit µs µs Recovery time from wait mode to low power mode Recovery time from stop mode (1) Note: 1. This recovery time does not include the period until the main clock oscillator is stabilized. The CPU starts operating before the oscillator is stabilized. t rec(WAIT) Recovery time from wait mode to low power mode Interrupt for exiting wait mode Sub clock oscillator output On-chip oscillator output CPU clock t rec(WAIT) t rec(STOP) Recovery time from stop mode Interrupt for exiting stop mode Main clock oscillator output On-chip oscillator output CPU clock t rec(STOP) Figure 5.4 Clock Circuit Timing REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 89 of 122 R32C/118 Group 5. Electrical Characteristics Timing Requirements (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.14 Flash Memory CPU Rewrite Mode Timing Symbol tcR tsu(S-R) th(R-S) tsu(A-R) th(R-A) tw(R) tcW tsu(S-W) th(W-S) tsu(A-W) th(W-A) tw(W) Read cycle time Characteristics Value Min. 200 200 0 200 0 100 200 0 30 0 30 50 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns Chip-select setup time for read Chip-select hold time after read Address setup time for read Address hold time after read Read pulse width Write cycle time Chip-select setup time for write Chip-select hold time after write Address setup time for write Address hold time after write Write pulse width Read cycle t su(S-R) CS0 t su(A-R) A23 to A0, BC0 to BC3 t cR t h(R-S) t h(R-A) t w(R) RD Write cycle t su(S-W) CS0 to CS3 t su(A-W) A23 to A0, BC0 to BC3 t cW t h(W-S) t h(W-A) t w(W) WR Figure 5.5 Flash Memory CPU Rewrite Mode Timing REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 90 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 5 V Table 5.15 Electrical Characteristics (1/3) (VCC = 4.2 to 5.5 V, VSS = 0 V, Ta = Topr, and f(CPU) = 50 MHz, unless otherwise noted) Symbol VOH High level output voltage Characteristic P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_3 to P14_6, P15_0 to P15_7 (1) Measurement condition Value Min. Typ. Max. Unit IOH = -5 mA VCC - 2.0 VCC V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, IOH = -200 µA VCC - 0.3 P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_3 to P14_6, P15_0 to P15_7 (1) VOL Low level output voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_3 to P14_6, P15_0 to P15_7 (1) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_3 to P14_6, P15_0 to P15_7 (1) VCC V IOL = 5 mA 2.0 V IOL = 200 µA 0.45 V Note: 1. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated as input pin in the 100-pin package. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 91 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 5 V Table 5.16 Electrical Characteristics (2/3) (VCC = 4.2 to 5.5 V, VSS = 0 V, Ta = Topr, and f(CPU) = 50 MHz, unless otherwise noted) Symbol Characteristic Value Measurement Unit condition Min. Typ. Max. VT+ - VT- Hysteresis HOLD, RDY, NMI, INT0 to INT8, KI0 to KI3, TA0IN to TA4IN, TA0OUT to TA4OUT, TB0IN to TB5IN, CTS0 to CTS8, CLK0 to CLK8, RXD0 to RXD8, SCL0 to SCL6, SDA0 to SDA6, SS0 to SS6, SRXD0 to SRXD6, ADTRG, IIO0_0 to IIO0_7, IIO1_0 to IIO1_7, UD0A, UD0B, UD1A, UD1B, ISCLK2, ISRXD2, IEIN, CAN0IN, CAN1IN, CAN0WU, CAN1WU (1) RESET 0.2 1.0 V 0.2 1.8 V IIH High level XIN, RESET, CNVSS, NSD, input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_1, P14_3 to P14_6, P15_0 to P15_7 (2) Low level input current XIN, RESET, CNVSS, NSD, P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_1, P14_3 to P14_6, P15_0 to P15_7 (2) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P5_0 to P5_3, P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_1, P14_3 to P14_6, P15_0 to P15_7 (2) VI = 5 V 5.0 µA IIL VI = 0 V -5.0 µA RPULLUP Pull-up resistor VI = 0 V 30 50 170 kΩ RfXIN RfXCIN Feedback XIN resistor Feedback XCIN resistor 1.5 15 MΩ MΩ Notes: 1. Pins INT6 to INT8 are available in the 144-pin package only. 2. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated as input pin in the 100-pin package. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 92 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 5 V Table 5.17 Electrical Characteristics (3/3) (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Symbol ICC Characte ristic Power supply current Measurement condition In single-chip mode, output pins are left open and others are connected to VSS XIN-XOUT Drive power: low XCIN-XCOUT Drive power: low f(CPU) = 50 MHz, f(BCLK) = 25 MHz, f(XIN) = 8 MHz, Active: XIN, PLL, Stopped: XCIN, OCO f(CPU) = fSO(PLL)/24 MHz, Active: PLL (self-oscillation), Stopped: XIN, XCIN, OCO f(CPU) = f(BCLK) = f(XIN)/256 MHz, f(XIN) = 8 MHz, Active: XIN, Stopped: PLL, XCIN, OCO f(CPU) = f(BCLK) = 32.768 kHz, Active: XCIN, Stopped: XIN, PLL, OCO, Main regulator: shutdown f(CPU) = f(BCLK) = f(OCO)/4 kHz, Active: OCO, Stopped: XIN, PLL, XCIN, Main regulator: shutdown f(CPU) = f(BCLK) = f(XIN)/256 MHz, f(XIN) = 8 MHz, Active: XIN, Stopped: PLL, XCIN, OCO, Ta = 25°C, Wait mode f(CPU) = f(BCLK) = 32.768 kHz, Active: XCIN, Stopped: XIN, PLL, OCO, Main regulator: shutdown, Ta = 25°C, Wait mode f(CPU) = f(BCLK) = f(OCO)/4 kHz, Active: OCO, Stopped: XIN, PLL, XCIN, Main regulator: shutdown, Ta = 25°C, Wait mode Stopped: all clocks, Main regulator: shutdown, Ta = 25°C Value Min. Typ. Max. Unit 35 50 mA 12 mA 1.2 mA 220 µA 230 µA 960 1600 µA 8 140 µA 10 150 µA 5 70 µA REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 93 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 5 V Table 5.18 A/D Conversion Characteristics (VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, Ta = Topr, and f(BCLK) = 25 MHz, unless otherwise noted) Symbol — Characteristic Resolution Absolute error Measurement condition VREF = VCC VREF = VCC = 5 V AN_0 to AN_7, AN0_0 to AN0_7, AN2_0 to AN2_7, AN15_0 to AN15_7, ANEX0, ANEX1 (1) External op-amp connection mode Value Min. Typ. Max. 10 Unit Bits ±3 LSB — ±7 LSB INL Integral non-linearity error VREF = VCC = 5 V AN_0 to AN_7, AN0_0 to AN0_7, AN2_0 to AN2_7, AN15_0 to AN15_7, ANEX0, ANEX1 (1) External op-amp connection mode ±3 LSB ±7 ±1 ±3 ±3 LSB LSB LSB LSB kΩ µs µs µs µs µs DNL — — RLADDER tCONV Differential non-linearity error Offset error Gain error Resistor ladder Conversion time (10 bits) VREF = VCC φAD = 16 MHz, with sample and hold function φAD = 16 MHz, without sample and hold function 4 2.06 3.69 1.75 3.06 0.188 0 20 tCONV Conversion time (8 bits) φAD = 16 MHz, with sample and hold function φAD = 16 MHz, without sample and hold function tSAMP VIA φAD Sampling time Analog input voltage Operating clock frequency φAD = 16 MHz VREF 16 16 V MHz MHz without sample and hold function with sample and hold function 0.25 1 Note: 1. Pins AN15_0 to AN15_7 are available in the 144-pin package only. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 94 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 5 V Table 5.19 D/A Conversion Characteristics (VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, and Ta = Topr, unless otherwise noted) Symbol — — tS RO IVREF Characteristic Resolution Absolute precision Settling time Output resistance Reference input current Measurement condition Value Min. Typ. Max. 8 1.0 3 4 10 20 1.5 Unit Bits % µs kΩ mA (1) Note: 1. One D/A converter is used. The DAi register (i = 0, 1) of the other unused converter is set to 00h. The resistor ladder for A/D converter is not considered. Even when the VCUT bit in the AD0CON1 register is set to 0 (VREF disconnected), IVREF is supplied. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 95 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 5 V Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.20 External Clock Input Symbol tc(X) tw(XH) tw(XL) tr(X) tf(X) tw / tc Characteristic External clock input period External clock input high level pulse width External clock input low level pulse width External clock input rise time External clock input fall time External clock input duty Value Min. 62.5 25 25 5 5 40 60 Max. 250 Unit ns ns ns ns ns % Table 5.21 External Bus Timing Symbol tsu(D-R) th(R-D) tdis(R-D) Characteristic Data setup time for read Data hold time after read Data disable time after read Value Min. 40 0 0.5 × tc(Base) + 10 Max. Unit ns ns ns REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 96 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 5 V Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.22 Timer A Input (Counting input in event counter mode) Symbol tc(TA) tw(TAH) tw(TAL) Table 5.23 Characteristic TAiIN input clock period TAiIN input high level pulse width TAiIN input low level pulse width Timer A Input (Gating input in timer mode) Value Min. 200 80 80 Max. Unit ns ns ns Symbol tc(TA) tw(TAH) tw(TAL) Table 5.24 Characteristic TAiIN input clock period TAiIN input high level pulse width TAiIN input low level pulse width Timer A Input (External trigger input in one-shot timer mode) Value Min. 400 180 180 Max. Unit ns ns ns Symbol tc(TA) tw(TAH) tw(TAL) Table 5.25 Characteristic TAiIN input clock period TAiIN input high level pulse width TAiIN input low level pulse width Value Min. 200 80 80 Max. Unit ns ns ns Timer A Input (External trigger input in pulse-width modulation mode) Symbol tw(TAH) tw(TAL) Table 5.26 Characteristic TAiIN input high level pulse width TAiIN input low level pulse width Value Min. 80 80 Max. Unit ns ns Timer A Input (Increment/decrement count switching input in event counter mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) Characteristic TAiOUT input clock period TAiOUT input high level pulse width TAiOUT input low level pulse width TAiOUT input setup time TAiOUT input hold time Value Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 97 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 5 V Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.27 Timer B Input (Counting input in event counter mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Table 5.28 Characteristic TBiIN input clock period (one edge counting) TBiIN input high level pulse width (one edge counting) TBiIN input low level pulse width (one edge counting) TBiIN input clock period (both edges counting) TBiIN input high level pulse width (both edges counting) TBiIN input low level pulse width (both edges counting) Timer B Input (Pulse period measure mode) Value Min. 200 80 80 200 80 80 Max. Unit ns ns ns ns ns ns Symbol tc(TB) tw(TBH) tw(TBL) Table 5.29 Characteristic TBiIN input clock period TBiIN input high level pulse width TBiIN input low level pulse width Timer B Input (Pulse-width measure mode) Value Min. 400 180 180 Max. Unit ns ns ns Symbol tc(TB) tw(TBH) tw(TBL) Characteristic TBiIN input clock period TBiIN input high level pulse width TBiIN input low level pulse width Value Min. 400 180 180 Max. Unit ns ns ns REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 98 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 5 V Timing requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.30 Serial Interface Symbol tc(CK) tw(CKH) tw(CKL) tsu(D-C) th(C-D) CLKi input clock period Characteristic Value Min. 200 80 80 80 90 Max. Unit ns ns ns ns ns CLKi input high level pulse width CLKi input low level pulse width RXDi input setup time RXDi input hold time Table 5.31 A/D Trigger Input Symbol tw(ADH) tw(ADL) Characteristic ADTRG input high level pulse width Hardware trigger input high level pulse width ADTRG input low level pulse width Hardware trigger input high level pulse width Value Min. 3--------φ AD Max. Unit ns ns 125 Table 5.32 External Interrupt INTi Input Symbol tw(INH) Characteristic INTi input high level pulse width INTi input low level pulse width Value Min. Edge sensitive Level sensitive 250 tc(CPU) + 200 250 tc(CPU) + 200 Max. Unit ns ns ns ns tw(INL) Edge sensitive Level sensitive Table 5.33 Intelligent I/O Symbol tc(ISCLK2) tw(ISCLK2H) tw(ISCLK2L) tsu(RXD-ISCLK2) th(ISCLK2-RXD) Characteristic ISCLK2 input clock period ISCLK2 input high level pulse width ISCLK2 input low level pulse width ISRXD2 input setup time ISRXD2 input hold time Value Min. 600 270 270 150 100 Max. Unit ns ns ns ns ns REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 99 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 5 V Timing requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.34 Multi-master I2C-bus Interface Value Symbol tw(SCLH) tw(SCLL) tr(SCL) tf(SCL) tr(SDA) tf(SDA) th(SDA-SCL)S tsu(SCL-SDA)P tw(SDAH)P tsu(SDA-SCL) th(SCL-SDA) Characteristic MSCL input high level pulse width MSCL input low level pulse width MSCL input rise time MSCL input fall time MSDA input rise time MSDA input fall time MSCL high level hold time after start condition/restart condition MSCL high level setup time for restart condition/stop condition MSDA high level pulse width after stop condition MSDA input setup time MSDA input hold time (1) Standard-mode Min. 600 600 1000 300 1000 300 Max. Fast-mode Min. 600 600 300 300 300 300 2 × tc(φIIC) + 40 2 × tc(φIIC) + 40 4 × tc(φIIC) + 40 100 0 Max. Unit ns ns ns ns ns ns ns ns ns ns ns (1) (1) 100 0 Note: 1. The value is calculated by the following formulas based on a value SSC set by bits SSC4 to SSC0 in the I2CSSCR register: th(SDA-SCL)S = SSC ÷ 2 × tc(φIIC) + 40 [ns] tsu(SCL-SDA)P = (SSC ÷ 2 + 1) × tc(φIIC) + 40 [ns] tw(SDAH)P = (SSC + 1) × tc(φIIC) + 40 [ns] REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 100 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 5 V Switching Characteristics (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.35 External Bus Timing (Separate bus) Symbol tsu(S-R) th(R-S) tsu(A-R) th(R-A) tw(R) tsu(S-W) th(W-S) tsu(A-W) th(W-A) tw(W) tsu(D-W) th(W-D) Characteristic Chip-select setup time for read Chip-select hold time after read Address setup time for read Address hold time after read Read pulse width Chip-select setup time for write Chip-select hold time after write Address setup time for write Address hold time after write Write pulse width Data setup time for write Data hold time after write Measurement condition Value Min. (1) Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns tc(Base) - 15 (1) tc(Base) - 15 (1) Refer to Figure 5.6 (1) 1.5 × tc(Base) - 15 (1) 1.5 × tc(Base) - 15 (1) (1) 0 Note: 1. The value is calculated by the following formulas based on the base clock cycles (tc(Base)) and respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the calculation results in a negative value, modify the value to be set. For the details of how to set values, refer to the Hardware manual. tsu(S-R) = tsu(A-R) = Tsu(A-R) × tc(Base) - 15 [ns] tw(R) = Tw(R) × tc(Base) - 10 [ns] tsu(S-W) = tsu(A-W) = Tsu(A-W) × tc(Base) - 15 [ns] tw(W) = tsu(D-W) = Tw(W) × tc(Base) - 10 [ns] REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 101 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 5 V Switching Characteristics (VCC = 4.2 to 5.5 V, VSS = 0 V, Ta = Topr, and unless otherwise noted) Table 5.36 External Bus Timing (Multiplexed bus) Symbol tsu(S-ALE) th(R-S) tsu(A-ALE) th(ALE-A) th(R-A) td(ALE-R) tw(ALE) tdis(R-A) tw(R) th(W-S) th(W-A) td(ALE-W) tw(W) tsu(D-W) th(W-D) Characteristic Chip-select setup time for ALE Chip-select hold time after read Address setup time for ALE Address hold time after ALE Address hold time after read ALE-read delay time ALE pulse width Address disable time after read Read pulse width Chip-select hold time after write Address hold time after write ALE-write delay time Write pulse width Data setup time for write Data hold time after write Measurement condition Value Min. (1) Max. Unit ns ns ns ns ns 1.5 × tc(Base) - 15 (1) 0.5 × tc(Base) - 5 1.5 × tc(Base) - 15 (1) 0.5 × tc(Base) - 5 0.5 × tc(Base) + 10 ns ns 8 (1) Refer to Figure 5.6 1.5 × tc(Base) - 15 1.5 × tc(Base) - 15 (1) (1) ns ns ns ns 0.5 × tc(Base) - 5 0.5 × tc(Base) + 10 ns ns ns ns 0.5 × tc(Base) Note: 1. The value is calculated by the following formulas based on the base clock cycles (tc(Base)) and respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the calculation results in a negative value, modify the value to be set. For the details of how to set values, refer to the Hardware manual. tsu(S-ALE) = tsu(A-ALE) = tw(ALE) = (Tsu(A-R) - 0.5) × tc(Base) -15 [ns] tw(R) = Tw(R) × tc(Base) -10 [ns] tw(W) = tsu(D-W) = Tw(W) × tc(Base) -10 [ns] REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 102 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 5 V Switching Characteristics (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.37 Serial Interface Symbol td(C-Q) th(C-Q) Characteristic TXDi output delay time TXDi output hold time Measurement condition Refer to Figure 5.6 Value Min. Max. 80 0 Unit ns ns Table 5.38 Intelligent I/O Symbol td(ISCLK2-TXD) th(ISCLK2-RXD) Characteristic ISTXD2 output delay time ISTXD2 output hold time Measurement condition Refer to Figure 5.6 Value Min. Max. 180 0 Unit ns ns Table 5.39 Multi-master I2C-bus Interface (Standard-mode) Symbol tf(SCL) tf(SDA) Characteristic MSCL output fall time MSDA output fall time Measurement condition Value Min. 2 2 Max. Unit ns ns ns td(SDA-SCL)S MSCL output delay time after start condition/restart condition td(SCL-SDA)P Restart condition/stop condition output delay time after MSCL becomes high td(SCL-SDA) MSDA output delay time Refer to Figure 5.6 20 × tc(φIIC) - 120 52 × tc(φIIC) - 40 20 × tc(φIIC) + 40 52 × tc(φIIC) + 120 2 × tc(φIIC) + 40 3 × tc(φIIC) + 120 ns ns Table 5.40 Multi-master I2C-bus Interface (Fast-mode) Symbol tf(SCL) tf(SDA) Characteristic MSCL output fall time MSDA output fall time Measurement condition Value Min. 2 (1) 2 (1) Max. Unit ns ns ns td(SDA-SCL)S MSCL output delay time after start condition/restart condition td(SCL-SDA)P Restart condition/stop condition output delay time after MSCL becomes high td(SCL-SDA) MSDA output delay time Refer to Figure 5.6 10 × tc(φIIC) - 120 26 × tc(φIIC) - 40 10 × tc(φIIC) + 40 26 × tc(φIIC) + 120 2 × tc(φIIC) + 40 3 × tc(φIIC) + 120 ns ns Note: 1. External circuits are required to satisfy the I2C-bus specification. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 103 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 3.3 V Table 5.41 Electrical Characteristics (1/3) (VCC = 3.0 to 3.6 V, VSS = 0 V, Ta = Topr, and f(CPU) = 50 MHz, unless otherwise noted) Symbol VOH High level output voltage Characteristic P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_3 to P14_6, P15_0 to P15_7 (1) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_3 to P14_6, P15_0 to P15_7 (1) Measurement condition Value Min. Typ. Max. Unit IOH = -1 mA VCC - 0.6 VCC V VOL Low level output voltage IOL = 1 mA 0.5 V Notes: 1. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated as input pin in the 100-pin package. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 104 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 3.3 V Table 5.42 Electrical Characteristics (2/3) (VCC = 3.0 to 3.6 V, VSS = 0 V, Ta = Topr, and f(CPU) = 50 MHz, unless otherwise noted) Symbol Characteristic Value Measurement Unit condition Min. Typ. Max. VT+ - VT- Hysteresis HOLD, RDY, NMI, INT0 to INT8, KI0 to KI3, TA0IN to TA4IN, TA0OUT to TA4OUT, TB0IN to TB5IN, CTS0 to CTS8, CLK0 to CLK8, RXD0 to RXD8, SCL0 to SCL6, SDA0 to SDA6, SS0 to SS6, SRXD0 to SRXD6, ADTRG, IIO0_0 to IIO0_7, IIO1_0 to IIO1_7, UD0A, UD0B, UD1A, UD1B, ISCLK2, ISRXD2, IEIN, CAN0IN, CAN1IN, CAN0WU, CAN1WU (1) RESET High level XIN, RESET, CNVSS, NSD, IIH input P0_0 to P0_7, P1_0 to P1_7, current P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_1, P14_3 to P14_6, P15_0 to P15_7 (2) Low level XIN, RESET, CNVSS, NSD, IIL input P0_0 to P0_7, P1_0 to P1_7, current P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_1, P14_3 to P14_6, P15_0 to P15_7 (2) P0_0 to P0_7, P1_0 to P1_7, RPULLUP Pull-up resistor P2_0 to P2_7, P3_0 to P3_7, P5_0 to P5_3, P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_1, P14_3 to P14_6, P15_0 to P15_7 (2) RfXIN Feedback XIN resistor RfXCIN Feedback XCIN resistor 0.2 1.0 V 0.2 1.8 V VI = 3.3 V 4.0 µA VI = 0 V -4.0 µA VI = 0 V 50 100 500 kΩ 3 25 MΩ MΩ Notes: 1. Pins INT6 to INT8 are available in the 144-pin package only. 2. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated as input pin in the 100-pin package. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 105 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 3.3 V Table 5.43 Electrical Characteristics (3/3) (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Symbol ICC Characte ristic Power supply current Measurement condition In single-chip mode, output pins are left open and others are connected to VSS XIN-XOUT Drive power: low XCIN-XCOUT Drive power: low f(CPU) = 50 MHz, f(BCLK) = 25 MHz, f(XIN) = 8 MHz, Active: XIN, PLL, Stopped: XCIN, OCO f(CPU) = fSO(PLL)/24 MHz, Active: PLL (self-oscillation), Stopped: XIN, XCIN, OCO f(CPU) = f(BCLK) = f(XIN)/256 MHz, f(XIN) = 8 MHz, Active: XIN, Stopped: PLL, XCIN, OCO f(CPU) = f(BCLK) = 32.768 kHz, Active: XCIN, Stopped: XIN, PLL, OCO, Main regulator: shutdown f(CPU) = f(BCLK) = f(OCO)/4 kHz, Active: OCO, Stopped: XIN, PLL, XCIN, Main regulator: shutdown f(CPU) = f(BCLK) = f(XIN)/256 MHz, f(XIN) = 8 MHz, Active: XIN, Stopped: PLL, XCIN, OCO, Ta = 25°C, Wait mode f(CPU) = f(BCLK) = 32.768 kHz, Active: XCIN, Stopped: XIN, PLL, OCO, Main regulator: shutdown, Ta = 25°C, Wait mode f(CPU) = f(BCLK) = f(OCO)/4 kHz, Active: OCO, Stopped: XIN, PLL, XCIN, Main regulator: shutdown, Ta = 25°C, Wait mode Stopped: all clocks, Main regulator: shutdown, Ta = 25°C Value Min. Typ. Max. Unit 32 45 mA 9 mA 670 µA 180 µA 190 µA 500 900 µA 8 140 µA 10 150 µA 5 70 µA REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 106 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 3.3 V Table 5.44 A/D Conversion Characteristics (VCC= AVCC = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V, Ta = Topr, and f(BCLK) = 25 MHz, unless otherwise noted) Symbol — Characteristic Resolution Absolute error Measurement condition VREF = VCC VREF = VCC = 3.3 V AN_0 to AN_7, AN0_0 to AN0_7, AN2_0 to AN2_7, AN15_0 to AN15_7, ANEX0, ANEX1 (1) External op-amp connection mode Value Min. Typ. Max. 10 Unit Bits ±5 LSB — ±7 LSB INL Integral non-linearity error VREF = VCC = 3.3 V AN_0 to AN_7, AN0_0 to AN0_7, AN2_0 to AN2_7, AN15_0 to AN15_7, ANEX0, ANEX1 (1) External op-amp connection mode ±5 LSB ±7 ±1 ±3 ±3 LSB LSB LSB LSB kΩ µs µs µs DNL — — RLADDER tCONV tCONV tSAMP VIA φAD Differential nonlinearity error Offset error Gain error Resistor ladder Conversion time (10 bits) Conversion time (8 bits) Sampling time Analog input voltage Operating clock frequency VREF = VCC = 3.3 V VREF = VCC φAD = 10 MHz, with sample and hold function φAD = 10 MHz, with sample and hold function φAD = 10 MHz 4 3.3 2.8 0.3 0 20 VREF 10 10 V MHz MHz without sample and hold function with sample and hold function 0.25 1 Note: 1. Pins AN15_0 to AN15_7 are available in the 144-pin package only. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 107 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 3.3 V Table 5.45 D/A Conversion Characteristics (VCC= AVCC = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V, and Ta = Topr, unless otherwise noted) Symbol — — tS RO IVREF Characteristic Resolution Absolute precision Settling time Output resistance Reference input current Measurement condition Min. Value Typ. Max. 8 1.0 3 4 10 20 1.0 Unit Bits % µs kΩ mA (1) Note: 1. One D/A converter is used. The DAi register (i = 0, 1) of the other unused converter is set to 00h. The resistor ladder for A/D converter is not considered. Even when the VCUT bit in the AD0CON1 register is set to 0 (VREF disconnected), IVREF is supplied. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 108 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 3.3 V Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.46 External Clock Input Symbol tc(X) tw(XH) tw(XL) tr(X) tf(X) tw / tc Characteristic External clock input period External clock input high level pulse width External clock input low level pulse width External clock input rise time External clock input fall time External clock input duty Value Min. 62.5 25 25 5 5 40 60 Max. 250 Unit ns ns ns ns ns % Table 5.47 External Bus Timing Symbol tsu(D-R) th(R-D) tdis(R-D) Characteristic Data setup time for read Data hold time after read Data disable time after read Value Min. 40 0 0.5 × tc(Base) + 10 Max. Unit ns ns ns REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 109 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 3.3 V Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.48 Timer A Input (Counting input in event counter mode) Symbol tc(TA) tw(TAH) tw(TAL) Table 5.49 Characteristic TAiIN input clock period TAiIN input high level pulse width TAiIN input low level pulse width Timer A Input (Gating input in timer mode) Value Min. 200 80 80 Max. Unit ns ns ns Symbol tc(TA) tw(TAH) tw(TAL) Table 5.50 Characteristic TAiIN input clock period TAiIN input high level pulse width TAiIN input low level pulse width Timer A Input (External trigger input in one-shot timer mode) Value Min. 400 180 180 Max. Unit ns ns ns Symbol tc(TA) tw(TAH) tw(TAL) Table 5.51 Characteristic TAiIN input clock period TAiIN input high level pulse width TAiIN input low level pulse width Value Min. 200 80 80 Max. Unit ns ns ns Timer A Input (External trigger input in pulse-width modulation mode) Symbol tw(TAH) tw(TAL) Table 5.52 Characteristic TAiIN input high level pulse width TAiIN input low level pulse width Value Min. 80 80 Max. Unit ns ns Timer A Input (Increment/decrement count switching input in event counter mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) Characteristic TAiOUT input clock period TAiOUT input high level pulse width TAiOUT input low level pulse width TAiOUT input setup time TAiOUT input hold time Value Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 110 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 3.3 V Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.53 Timer B Input (Counting input in event counter mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Table 5.54 Characteristic TBiIN input clock period (one edge counting) TBiIN input high level pulse width (one edge counting) TBiIN input low level pulse width (one edge counting) TBiIN input clock period (both edges counting) TBiIN input high level pulse width (both edges counting) TBiIN input low level pulse width (both edges counting) Timer B Input (Pulse period measure mode) Value Min. 200 80 80 200 80 80 Max. Unit ns ns ns ns ns ns Symbol tc(TB) tw(TBH) tw(TBL) Table 5.55 Characteristic TBiIN input clock period TBiIN input high level pulse width TBiIN input low level pulse width Timer B Input (Pulse-width measure mode) Value Min. 400 180 180 Max. Unit ns ns ns Symbol tc(TB) tw(TBH) tw(TBL) Characteristic TBiIN input clock period TBiIN input high level pulse width TBiIN input low level pulse width Value Min. 400 180 180 Max. Unit ns ns ns REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 111 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 3.3 V Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.56 Serial Interface Symbol tc(CK) tw(CKH) tw(CKL) tsu(D-C) th(C-D) CLKi input clock period Characteristic Value Min. 200 80 80 80 90 Max. Unit ns ns ns ns ns CLKi input high level pulse width CLKi input low level pulse width RXDi input setup time RXDi input hold time Table 5.57 A/D Trigger Input Symbol tw(ADH) tw(ADL) Characteristic ADTRG input high level pulse width Hardware trigger input high level pulse width ADTRG input low level pulse width Hardware trigger input high level pulse width Value Min. 3--------φ AD Max. Unit ns ns 125 Table 5.58 External Interrupt INTi Input Symbol tw(INH) Characteristic INTi input high level pulse width INTi input low level pulse width Value Min. Edge sensitive Level sensitive 250 tc(CPU) + 200 250 tc(CPU) + 200 Max. Unit ns ns ns ns tw(INL) Edge sensitive Level sensitive Table 5.59 Intelligent I/O Symbol tc(ISCLK2) tw(ISCLK2H) tw(ISCLK2L) Characteristic ISCLK2 input clock period ISCLK2 input high level pulse width ISCLK2 input low level pulse width Value Min. 600 270 270 150 100 Max. Unit ns ns ns ns ns tsu(RXD-ISCLK2) ISRXD2 input setup time th(ISCLK2-RXD) ISRXD2 input hold time REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 112 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 3.3 V Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.60 Multi-master I2C-bus Interface Value Symbol tw(SCLH) tw(SCLL) tr(SCL) tf(SCL) tr(SDA) tf(SDA) th(SDA-SCL)S tsu(SCL-SDA)P tw(SDAH)P tsu(SDA-SCL) th(SCL-SDA) Characteristic MSCL input high level pulse width MSCL input low level pulse width MSCL input rise time MSCL input fall time MSDA input rise time MSDA input fall time MSCL high level hold time after start condition/restart condition MSCL high level setup time for restart condition/stop condition MSDA high level pulse width after stop condition MSDA input setup time MSDA input hold time (1) Standard-mode Min. 600 600 1000 300 1000 300 Max. Fast-mode Min. 600 600 300 300 300 300 2 × tc(φIIC) + 40 2 × tc(φIIC) + 40 4 × tc(φIIC) + 40 100 0 Max. Unit ns ns ns ns ns ns ns ns ns ns ns (1) (1) 100 0 Note: 1. The value is calculated by the following formulas based on a value SSC set by bits SSC4 to SSC0 in the I2CSSCR register: th(SDA-SCL)S = SSC ÷ 2 × tc(φIIC) + 40 [ns] tsu(SCL-SDA)P = (SSC ÷ 2 + 1) × tc(φIIC) + 40 [ns] tw(SDAH)P = (SSC + 1) × tc(φIIC) + 40 [ns] REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 113 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 3.3 V Switching Characteristics (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.61 External Bus Timing (Separate bus) Symbol tsu(S-R) th(R-S) tsu(A-R) th(R-A) tw(R) tsu(S-W) th(W-S) tsu(A-W) th(W-A) tw(W) tsu(D-W) th(W-D) Characteristic Chip-select setup time for read Chip-select hold time after read Address setup time for read Address hold time after read Read pulse width Chip-select setup time for write Chip-select hold time after write Address setup time for write Address hold time after write Write pulse width Data setup time for write Data hold time after write Measurement condition Value Min. (1) Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns tc(Base) - 15 (1) tc(Base) - 15 (1) (1) Refer to Figure 5.6 1.5 × tc(Base) - 15 (1) 1.5 × tc(Base) - 15 (1) (1) 0 Note: 1. The value is calculated by the following formulas based on the base clock cycles (tc(Base)) and respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the calculation results in a negative value, modify the value to be set. For the details of how to set values, refer to the Hardware manual. tsu(S-R) = tsu(A-R) = Tsu(A-R) × tc(Base) - 15 [ns] tw(R) = Tw(R) × tc(Base) - 10 [ns] tsu(S-W) = tsu(A-W) = Tsu(A-W) × tc(Base) - 15 [ns] tw(W) = tsu(D-W) = Tw(W) × tc(Base) - 10 [ns] REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 114 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 3.3 V Switching Characteristics (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.62 External Bus Timing (Multiplexed bus) Symbol tsu(S-ALE) th(R-S) tsu(A-ALE) th(ALE-A) th(R-A) td(ALE-R) tw(ALE) tdis(R-A) tw(R) th(W-S) th(W-A) td(ALE-W) tw(W) tsu(D-W) th(W-D) Characteristic Chip-select setup time for ALE Chip-select hold time after read Address setup time for ALE Address hold time after ALE Address hold time after read ALE-read delay time ALE pulse width Address disable time after read Read pulse width Chip-select hold time after write Address hold time after write ALE-write delay time Write pulse width Data setup time for write Data hold time after write Measurement condition Value Min. (1) Max. Unit ns ns ns ns ns 1.5 × tc(Base) - 15 (1) 0.5 × tc(Base) - 5 1.5 × tc(Base) - 15 0.5 × tc(Base) - 5 0.5 × tc(Base) + 10 ns (1) ns 8 ns ns ns ns Refer to Figure 5.6 (1) 1.5 × tc(Base) - 15 1.5 × tc(Base) - 15 (1) (1) 0.5 × tc(Base) - 5 0.5 × tc(Base) + 10 ns ns ns ns 0.5 × tc(Base) Note: 1. The value is calculated by the following formulas based on the base clock cycles (tc(Base)) and respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the calculation results in a negative value, modify the value to be set. For the details of how to set values, refer to the Hardware manual. tsu(S-ALE) = tsu(A-ALE) = (Tsu(A-R) - 0.5) × tc(Base) -15 [ns] tw(ALE) = (Tsu(A-R) - 0.5) × tc(Base) - 20 [ns] tw(R) = Tw(R) × tc(Base) -10 [ns] tw(W) = tsu(D-W) = Tw(W) × tc(Base) -10 [ns] REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 115 of 122 R32C/118 Group 5. Electrical Characteristics VCC = 3.3 V Switching Characteristics (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Table 5.63 Serial Interface Symbol td(C-Q) th(C-Q) Characteristic TXDi output delay time TXDi output hold time Measurement condition Refer to Figure 5.6 Value Min. Max. 80 0 Unit ns ns Table 5.64 Intelligent I/O Symbol td(ISCLK2-TXD) th(ISCLK2-RXD) Characteristic ISTXD2 output delay time ISTXD2 output hold time Measurement condition Refer to Figure 5.6 Value Min. Max. 180 0 Unit ns ns Table 5.65 Multi-master I2C-bus Interface (Standard-mode) Symbol tf(SCL) tf(SDA) Characteristic MSCL output fall time MSDA output fall time Measurement condition Value Min. 2 2 Max. Unit ns ns ns td(SDA-SCL)S MSCL output delay time after start condition/restart condition td(SCL-SDA)P Restart condition/stop condition output delay time after MSCL becomes high td(SCL-SDA) MSDA output delay time Refer to Figure 5.6 20 × tc(φIIC) - 120 52 × tc(φIIC) - 40 20 × tc(φIIC) + 40 52 × tc(φIIC) + 120 2 ×tc(φIIC) + 40 3 × tc(φIIC) + 120 ns ns Table 5.66 Multi-master I2C-bus Interface (Fast-mode) Symbol tf(SCL) tf(SDA) Characteristic MSCL output fall time MSDA output fall time Measurement condition Value Min. 2 (1) 2 (1) Max. Unit ns ns ns td(SDA-SCL)S MSCL output delay time after start condition/restart condition td(SCL-SDA)P Restart condition/stop condition output delay time after MSCL becomes high td(SCL-SDA) MSDA output delay time Refer to Figure 5.6 10 × tc(φIIC) - 120 26 × tc(φIIC) - 40 10 × tc(φIIC) + 40 26 × tc(φIIC) + 120 2 × tc(φIIC) + 40 3 × tc(φIIC) + 120 ns ns Note: 1. External circuits are required to satisfy the I2C-bus specification. REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 116 of 122 R32C/118 Group 5. Electrical Characteristics MCU Pin to be measured 30 pF Figure 5.6 Switching Characteristic Measurement Circuit t c(X) XIN t w(XH) t r(X) t f(X) t w(XL) Figure 5.7 External Clock Input Timing REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 117 of 122 R32C/118 Group 5. Electrical Characteristics External bus timing (Separate bus) Read cycle t su(S-R) CS0 to CS3 t su(A-R) A23 to A0, BC0 to BC3 t w(R) RD t su(D-R) D31 to D0 t h(R-D) t h(R-A) t cR t h(R-S) Write cycle t su(S-W) CS0 to CS3 t su(A-W) A23 to A0, BC0 to BC3 t cW t h(W-S) t h(W-A) t w(W) WR, WR0 to WR3 t su(D-W) D31 to D0 t h(W-D) Measurement conditions Item Criterion for input voltage Criterion for output voltage VIH VIL VOH VOL V CC = 4.2 to 5.5 V 2.5 V 0.8 V 2.0 V 0.8 V V CC = 3.0 to 3.6 V 1.5 V 0.5 V 2.4 V 0.5 V Figure 5.8 External Bus Timing (Separate Bus) REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 118 of 122 R32C/118 Group 5. Electrical Characteristics External bus timing (Multiplexed bus) Read timing t su(S-ALE) CS0 to CS3 t su(A-ALE) A23 to A8, BC0 to BC3 t w(ALE) ALE t su(A-ALE) A15/D15 to A0/D0, BC0/D0, BC2/D1 Address t d(ALE-R) RD t su(D-R) D31 to D8 t h(R-D) t w(R) t dis(R-A) t su(D-R) Data t dis(R-D) t h(R-D) t h(ALE-A) t h(R-A) t cR t h(R-S) Write cycle t su(S-ALE) CS0 to CS3 t su(A-ALE) A23 to A8, BC0 to BC3 t w(ALE) ALE t su(A-ALE) A15/D15 to A0/D0, BC0/D0, BC2/D1 t h(ALE-A) t cW t h(W-S) t h(W-A) t su(D-W) Data t w(W) t h(W-D) Address t d(ALE-W) WR, WR0 to WR3 t su(D-W) D31 to D8 t h(W-D) Measurement conditions Item Criterion for input voltage Criterion for output voltage VIH VIL VOH VOL V CC = 4.2 to 5.5 V 2.5 V 0.8 V 2.0 V 0.8 V V CC = 3.0 to 3.6 V 1.5 V 0.5 V 2.4 V 0.5 V Figure 5.9 External Bus Timing (Multiplexed Bus) REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 119 of 122 R32C/118 Group 5. Electrical Characteristics t c(TA) t w(TAH) TAiIN input t c(UP) t w(UPH) TAiOUT input t w(UPL) t w(TAL) In event counter mode TAiOUT input (input for increment/ decrement count switching) t su(UP-TIN) TAiIN input (in falling edge counting) t h(TIN-UP) TAiIN input (in rising edge counting) t c(TB) t w(TBH) TBiIN input t c(CK) t w(CKH) CLKi t d(C-Q) TXDi t su(D-C) RXDi t h(C-D) t h(C-Q) t w(CKL) t w(TBL) t w(ADL) ADTRG input t w(ADH) t w(INL) INTi input t w(INH) 2 CPU clock cycles + 300 ns or more NMI input 2 CPU clock cycles + 300 ns or more Figure 5.10 Timing of Peripheral Functions REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 120 of 122 R32C/118 Group 5. Electrical Characteristics t c(SCL) MSCL t w(SCLH) t r(SCL) MSDA t r(SDA) t f(SDA) t f(SCL) t w(SCLL) t w(SDAH)P t h(SDA-SCL)S MSCL t su(SCL-SDA)P t su(SCL-SDA)P MSDA (input) t h(SDA-SCL)S t d(SDA-SCL)S MSCL t d(SCL-SDA)P t d(SCL-SDA)P MSDA (output) t d(SDA-SCL)S t su(SDA-SCL) MSCL t h(SCL-SDA) MSDA (input) t d(SCL-SDA) MSCL MSDA (output) Figure 5.11 Timing of Multi-master I2C-bus Interface REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 121 of 122 R32C/118 Group Appendix 1. Package Dimensions Appendix 1. Package Dimensions JEITA Package Code P-LQFP144-20x20-0.50 RENESAS Code PLQP0144KA-A Previous Code 144P6Q-A / FP-144L / FP-144LV MASS[Typ.] 1.2g HD *1 108 D 73 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1 109 72 c1 HE E c Reference Symbol *2 Dimension in Millimeters Terminal cross section 1 ZD A2 A 36 Index mark F ZE 144 37 L L1 D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 *3 e y bp x Detail F Min Nom Max 19.9 20.0 20.1 19.9 20.0 20.1 1.4 21.8 22.0 22.2 21.8 22.0 22.2 1.7 0.05 0.1 0.15 0.17 0.22 0.27 0.20 0.09 0.145 0.20 0.125 8° 0° 0.5 0.08 0.10 1.25 1.25 0.35 0.5 0.65 1.0 JEITA Package Code P-LQFP100-14x14-0.50 RENESAS Code PLQP0100KB-A Previous Code 100P6Q-A / FP-100U / FP-100UV MASS[Typ.] 0.6g HD *1 D 75 51 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 76 50 A1 bp b1 HE E c Reference Symbol *2 Dimension in Millimeters c1 c Terminal cross section 1 Index mark ZD 25 F ZE 100 26 A2 A D E A2 HD HE A A1 bp b1 c c1 c A1 y e *3 bp L L1 Detail F x e x y ZD ZE L L1 Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0° 8° 0.5 0.08 0.08 1.0 1.0 0.35 0.5 0.65 1.0 REJ03B0255-0100 Rev.1.00 Nov 19, 2009 Page 122 of 122 REVISION HISTORY Rev. 1.00 Date Nov 19, 2009 Page — R32C/118 Group Datasheet Description Summary Initial release All trademarks and registered trademarks are the property of their respective owners. A- 1 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. 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